diff --git a/.github/workflows/CITest.yml b/.github/workflows/CITest.yml
index 6b1850d14..898abd619 100644
--- a/.github/workflows/CITest.yml
+++ b/.github/workflows/CITest.yml
@@ -6,7 +6,7 @@ on:
       - "docs/**"
       - "ChangeLog"
       - "CREDITS.TXT"
-      - "COMPILE.TXT"
+      - "COMPILE_MAKE.TXT"
       - "COMPILE_MSVC.TXT"
       - "COMPILE_CMAKE.TXT"
       - "HACK.TXT"
@@ -34,6 +34,7 @@ jobs:
               os: ubuntu-22.04,
               arch: x64,
               build-system: 'make',
+              diet-build: 'OFF',
               enable-asan: 'OFF'
             }
           - {
@@ -41,34 +42,37 @@ jobs:
               os: ubuntu-22.04,
               arch: x64,
               build-system: 'cmake',
+              diet-build: 'OFF',
               enable-asan: 'OFF'
             }
           - {
-              name: 'ubuntu-22.04 x64 ASAN',
-              os: ubuntu-latest,
+              name: 'ubuntu-24.04 x64 ASAN',
+              os: ubuntu-24.04,
               arch: x64,
               build-system: 'cmake',
+              diet-build: 'OFF',
               enable-asan: 'ON'
             }
 
     steps:
     - uses: actions/checkout@v3
 
-    - name: prepare
+    - name: Set up Python
+      uses: actions/setup-python@v4
+      with:
+        python-version: ${{ matrix.config.python-version }}
+
+    - name: Prepare fuzzing
       run: |
         export LD_LIBRARY_PATH=`pwd`/tests/:$LD_LIBRARY_PATH
         wget https://github.com/groundx/capstonefuzz/raw/master/corpus/corpus-libFuzzer-capstone_fuzz_disasmnext-latest.zip
         unzip -q corpus-libFuzzer-capstone_fuzz_disasmnext-latest.zip -d suite/fuzz
-        git clone https://git.cryptomilk.org/projects/cmocka.git suite/cstest/cmocka
-        chmod +x suite/cstest/build_cstest.sh
 
     - name: make
       if: startsWith(matrix.config.build-system, 'make')
       run: |
         ./make.sh
-        make check
         sudo make install
-        cp libcapstone.so.5 libcapstone.so.5.0
 
     - name: cmake
       if: startsWith(matrix.config.build-system, 'cmake')
@@ -82,47 +86,55 @@ jobs:
         # build shared library
         cmake -DCAPSTONE_INSTALL=1 -DBUILD_SHARED_LIBS=1 -DCMAKE_INSTALL_PREFIX=/usr -DCAPSTONE_BUILD_CSTEST=ON -DENABLE_ASAN=${asan} ..
         sudo cmake --build . --config Release --target install
-        cp libcapstone.* ../
-        cp libcapstone.* ../tests/
-        cp test_* ../tests/
 
     - name: Lower number of KASL randomized address bits
       run: |
         # Work-around ASAN bug https://github.com/google/sanitizers/issues/1716
         sudo sysctl vm.mmap_rnd_bits=28
 
-    - name: "Compatibility header test build"
-      if: matrix.config.diet-build == 'OFF'
-      env:
-        asan: ${{ matrix.config.enable-asan }}
+    - name: "Compatibility header test"
+      if: startsWith(matrix.config.build-system, 'cmake') && matrix.config.diet-build == 'OFF'
       run: |
-        cd "$(git rev-parse --show-toplevel)/suite/auto-sync/c_tests/"
-        if [ "$asan" = "ON" ]; then
-          clang -lcapstone -fsanitize=address src/test_arm64_compatibility_header.c -o test_arm64_compatibility_header
-        else
-          clang -lcapstone src/test_arm64_compatibility_header.c -o test_arm64_compatibility_header
-        fi
-        ./test_arm64_compatibility_header
+        ctest --test-dir build --output-on-failure -R ASCompatibilityHeaderTest
 
     - name: cstool - reaches disassembler engine
       run: |
         sh suite/run_invalid_cstool.sh
 
-    - name: cstest (cmake)
+    - name: cstest unit tests
       if: startsWith(matrix.config.build-system, 'cmake')
       run: |
-        python suite/cstest/cstest_report.py -D -d suite/MC
-        python suite/cstest/cstest_report.py -D -f suite/cstest/issues.cs
-        python suite/cstest/cstest_report.py -D -f tests/cs_details/issue.cs
+        ctest --test-dir build --output-on-failure -R UnitCSTest
 
-    - name: cstest (make)
-      if: startsWith(matrix.config.build-system, 'make')
+    - name: cstest integration tests
+      if: startsWith(matrix.config.build-system, 'cmake')
       run: |
-        cd suite/cstest && ./build_cstest.sh
-        python cstest_report.py -D -t build/cstest -d ../MC
-        python cstest_report.py -D -t build/cstest -f issues.cs
-        python cstest_report.py -D -t build/cstest -f ../../tests/cs_details/issue.cs
-        cd ../../
+        ctest --test-dir build --output-on-failure -R IntegrationCSTest
+
+    - name: cstest MC
+      if: startsWith(matrix.config.build-system, 'cmake')
+      run: |
+        ctest --test-dir build --output-on-failure -R MCTests
+
+    - name: cstest details
+      if: startsWith(matrix.config.build-system, 'cmake')
+      run: |
+        ctest --test-dir build --output-on-failure -R DetailTests
+
+    - name: cstest issues
+      if: startsWith(matrix.config.build-system, 'cmake')
+      run: |
+        ctest --test-dir build --output-on-failure -R IssueTests
+
+    - name: cstest features
+      if: startsWith(matrix.config.build-system, 'cmake')
+      run: |
+        ctest --test-dir build --output-on-failure -R FeaturesTests
+
+    - name: Legacy integration tests
+      if: startsWith(matrix.config.build-system, 'cmake')
+      run: |
+        ctest --test-dir build --output-on-failure -R legacy*
 
   Windows:
     runs-on: ${{ matrix.config.os }}
diff --git a/.github/workflows/auto-sync.yml b/.github/workflows/auto-sync.yml
index 6cdaaf325..d22729333 100644
--- a/.github/workflows/auto-sync.yml
+++ b/.github/workflows/auto-sync.yml
@@ -3,11 +3,17 @@ on:
   push:
     paths:
       - "suite/auto-sync/**"
+      - ".github/workflows/auto-sync.yml"
   pull_request:
 
+# Stop previous runs on the same branch on new push
+concurrency:
+  group: ${{ github.workflow }}-${{ github.ref }}
+  cancel-in-progress: true
+
 jobs:
   check:
-    runs-on: ubuntu-latest
+    runs-on: ubuntu-24.04
     defaults:
       run:
         working-directory: suite/auto-sync/
@@ -30,9 +36,22 @@ jobs:
         run: |
           python3.11 -m black --check src/autosync
 
-      - name: Build llvm-tblgen
+      - name: Install llvm-mc
+        run: |
+          sudo apt install llvm-18
+          llvm-mc-18 --version
+          FileCheck-18 --version
+          sudo ln -s $(whereis -b llvm-mc-18 | grep -Eo "/.*") /usr/local/bin/llvm-mc
+          sudo ln -s $(whereis -b FileCheck-18 | grep -Eo "/.*") /usr/local/bin/FileCheck
+          llvm-mc --version
+          FileCheck --version
+
+      - name: Clone llvm-capstone
         run: |
           git clone https://github.com/capstone-engine/llvm-capstone.git vendor/llvm_root
+
+      - name: Build llvm-tblgen
+        run: |
           cd vendor/llvm_root
           mkdir build
           cd build
@@ -40,6 +59,17 @@ jobs:
           cmake --build . --target llvm-tblgen --config Debug
           cd ../../../
 
+      - name: Test Header patcher
+        run: |
+          python -m unittest src/autosync/Tests/test_header_patcher.py
+          python -m unittest src/autosync/Tests/test_mcupdater.py
+
+      - name: Remove llvm-mc
+        run: |
+          sudo apt remove llvm-18
+          sudo rm /usr/local/bin/llvm-mc
+          sudo rm /usr/local/bin/FileCheck
+
       - name: Test generation of inc files
         run: |
           ./src/autosync/ASUpdater.py -d -a AArch64 -s IncGen
@@ -63,11 +93,9 @@ jobs:
           ./src/autosync/ASUpdater.py --ci -d -a PPC -s Translate
           ./src/autosync/ASUpdater.py --ci -d -a LoongArch -s Translate
 
-      - name: Test Header patcher
-        run: |
-          python -m unittest src/autosync/Tests/test_header_patcher.py
-          python -m unittest src/autosync/Tests/test_mcupdater.py
-
       - name: Differ - Test save file is up-to-date
         run: |
           ./src/autosync/cpptranslator/Differ.py -a AArch64 --check_saved
+          ./src/autosync/cpptranslator/Differ.py -a ARM --check_saved
+          ./src/autosync/cpptranslator/Differ.py -a PPC --check_saved
+          ./src/autosync/cpptranslator/Differ.py -a LoongArch --check_saved
diff --git a/.github/workflows/clang-tidy.yml b/.github/workflows/clang-tidy.yml
index 0c36d6777..792a5b22d 100644
--- a/.github/workflows/clang-tidy.yml
+++ b/.github/workflows/clang-tidy.yml
@@ -8,11 +8,11 @@ on:
 
 jobs:
   analyze:
-    runs-on: ubuntu-latest
+    runs-on: ubuntu-24.04
 
     name: clang-tidy
     steps:
-    - uses: actions/checkout@v3
+    - uses: actions/checkout@v4
       with:
         fetch-depth: 0
     - name: Install clang-tidy
@@ -26,9 +26,9 @@ jobs:
         CC=clang sudo cmake --build . --config Release
         cd ..
 
-    - name: Install clang-tidy-15
+    - name: Install clang-tidy-18
       run: |
-        sudo apt install clang-tidy-15
+        sudo apt install clang-tidy-18
 
     - name: Check for warnings
       env:
@@ -36,3 +36,8 @@ jobs:
         head_sha: ${{ github.event.pull_request.head.sha }}
       run: |
         ./run-clang-tidy.sh build
+
+    - uses: actions/upload-artifact@v4
+      if: ${{ failure() }}
+      with:
+        path: ct-warnings.txt
diff --git a/.github/workflows/python-tests.yml b/.github/workflows/python-tests.yml
index c47993a2b..e72b8a4d8 100644
--- a/.github/workflows/python-tests.yml
+++ b/.github/workflows/python-tests.yml
@@ -28,5 +28,30 @@ jobs:
     - name: Build and install capstone
       run: pip install ./bindings/python
 
-    - name: Run tests
+    - name: Install cstest_py
+      run: pip install ./bindings/python/cstest_py
+
+    - name: Run legacy tests
       run: python ./bindings/python/tests/test_all.py
+
+    - name: cstest_py integration tests
+      run: |
+        cd suite/cstest/test/
+        python3 ./integration_tests.py cstest_py
+        cd ../../../
+
+    - name: cstest_py MC
+      run: |
+        cstest_py tests/MC/
+
+    - name: cstest_py details
+      run: |
+        cstest_py tests/details/
+
+    - name: cstest_py issues
+      run: |
+        cstest_py tests/issues/
+
+    - name: cstest_py features
+      run: |
+        cstest_py tests/features/
diff --git a/.gitignore b/.gitignore
index a0a901266..698c6d154 100644
--- a/.gitignore
+++ b/.gitignore
@@ -25,6 +25,7 @@
 # python
 bindings/python/build/
 bindings/python/capstone.egg-info/
+bindings/python/cstest_py/src/cstest_py.egg**
 bindings/cython/capstone.egg-info/
 *.pyc
 
@@ -133,7 +134,6 @@ fuzz_disasm
 fuzz_decode_platform
 capstone_get_setup
 suite/fuzz/corpus
-suite/cstest/cmocka/
 
 *.s
 
@@ -147,3 +147,6 @@ android-ndk-*
 
 # Auto-sync files
 suite/auto-sync/src/autosync.egg-info
+
+# clangd cache
+/.cache
diff --git a/CMakeLists.txt b/CMakeLists.txt
index c6acc4988..125f8b639 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -60,7 +60,7 @@ option(BUILD_SHARED_LIBS "Build shared library" OFF)
 option(CAPSTONE_BUILD_STATIC_RUNTIME "Embed static runtime" ${BUILD_SHARED_LIBS})
 option(CAPSTONE_BUILD_MACOS_THIN "Disable universal2 builds on macOS" OFF)
 option(CAPSTONE_BUILD_DIET "Build diet library" OFF)
-option(CAPSTONE_BUILD_TESTS "Build tests" ${PROJECT_IS_TOP_LEVEL})
+option(CAPSTONE_BUILD_LEGACY_TESTS "Build legacy tests" ${PROJECT_IS_TOP_LEVEL})
 option(CAPSTONE_BUILD_CSTOOL "Build cstool" ${PROJECT_IS_TOP_LEVEL})
 option(CAPSTONE_BUILD_CSTEST "Build cstest" OFF)
 option(CAPSTONE_USE_DEFAULT_ALLOC "Use default memory allocation functions" ON)
@@ -69,13 +69,21 @@ option(CAPSTONE_ARCHITECTURE_DEFAULT "Whether architectures are enabled by defau
 option(CAPSTONE_DEBUG "Whether to enable extra debug assertions" OFF)
 option(CAPSTONE_INSTALL "Generate install target" ${PROJECT_IS_TOP_LEVEL})
 option(ENABLE_ASAN "Enable address sanitizer" OFF)
+option(ENABLE_COVERAGE "Enable test coverage" OFF)
 
 if (ENABLE_ASAN)
+    message("Enabling ASAN")
     add_definitions(-DASAN_ENABLED)
     add_compile_options(-fsanitize=address)
     add_link_options(-fsanitize=address)
 endif()
 
+if (ENABLE_COVERAGE)
+    message("Enabling COVERAGE")
+    add_compile_options(--coverage)
+    add_link_options(--coverage)
+endif()
+
 # If building for OSX it's best to allow CMake to handle building both architectures
 if(APPLE AND NOT CAPSTONE_BUILD_MACOS_THIN)
     set(CMAKE_OSX_ARCHITECTURES "x86_64;arm64")
@@ -208,8 +216,6 @@ set(HEADERS_COMMON
     include/capstone/loongarch.h
 )
 
-set(TEST_SOURCES test_basic.c test_detail.c test_skipdata.c test_iter.c)
-
 ## architecture support
 if(CAPSTONE_ARM_SUPPORT)
     add_definitions(-DCAPSTONE_HAS_ARM)
@@ -239,7 +245,6 @@ if(CAPSTONE_ARM_SUPPORT)
         arch/ARM/ARMGenCSMappingInsnName.inc
         arch/ARM/ARMGenSystemRegister.inc
     )
-    set(TEST_SOURCES ${TEST_SOURCES} test_arm.c)
 endif()
 
 if(CAPSTONE_AARCH64_SUPPORT)
@@ -270,7 +275,6 @@ if(CAPSTONE_AARCH64_SUPPORT)
         arch/AArch64/AArch64GenCSMappingInsnName.inc
         arch/AArch64/AArch64GenCSMappingInsnOp.inc
     )
-    set(TEST_SOURCES ${TEST_SOURCES} test_aarch64.c)
 endif()
 
 if(CAPSTONE_MIPS_SUPPORT)
@@ -302,7 +306,6 @@ if(CAPSTONE_MIPS_SUPPORT)
         arch/Mips/MipsInstPrinter.h
         arch/Mips/MipsMapping.h
     )
-    set(TEST_SOURCES ${TEST_SOURCES} test_mips.c)
 endif()
 
 if(CAPSTONE_PPC_SUPPORT)
@@ -332,7 +335,6 @@ if(CAPSTONE_PPC_SUPPORT)
         arch/PowerPC/PPCGenSubtargetInfo.inc
         arch/PowerPC/PPCGenRegisterInfo.inc
     )
-    set(TEST_SOURCES ${TEST_SOURCES} test_ppc.c)
 endif()
 
 if(CAPSTONE_X86_SUPPORT)
@@ -386,7 +388,6 @@ if(CAPSTONE_X86_SUPPORT)
     if(NOT CAPSTONE_BUILD_DIET)
         set(SOURCES_X86 ${SOURCES_X86} arch/X86/X86ATTInstPrinter.c)
     endif()
-    set(TEST_SOURCES ${TEST_SOURCES} test_x86.c test_customized_mnem.c)
 endif()
 
 if(CAPSTONE_SPARC_SUPPORT)
@@ -409,7 +410,6 @@ if(CAPSTONE_SPARC_SUPPORT)
         arch/Sparc/SparcMapping.h
         arch/Sparc/SparcMappingInsn.inc
     )
-    set(TEST_SOURCES ${TEST_SOURCES} test_sparc.c)
 endif()
 
 if(CAPSTONE_SYSZ_SUPPORT)
@@ -434,7 +434,6 @@ if(CAPSTONE_SYSZ_SUPPORT)
         arch/SystemZ/SystemZMappingInsn.inc
         arch/SystemZ/SystemZMCTargetDesc.h
     )
-    set(TEST_SOURCES ${TEST_SOURCES} test_systemz.c)
 endif()
 
 if(CAPSTONE_XCORE_SUPPORT)
@@ -455,7 +454,6 @@ if(CAPSTONE_XCORE_SUPPORT)
         arch/XCore/XCoreMapping.h
         arch/XCore/XCoreMappingInsn.inc
     )
-    set(TEST_SOURCES ${TEST_SOURCES} test_xcore.c)
 endif()
 
 if(CAPSTONE_M68K_SUPPORT)
@@ -468,7 +466,6 @@ if(CAPSTONE_M68K_SUPPORT)
     set(HEADERS_M68K
         arch/M68K/M68KDisassembler.h
     )
-    set(TEST_SOURCES ${TEST_SOURCES} test_m68k.c)
 endif()
 
 if(CAPSTONE_TMS320C64X_SUPPORT)
@@ -488,7 +485,6 @@ if(CAPSTONE_TMS320C64X_SUPPORT)
         arch/TMS320C64x/TMS320C64xInstPrinter.h
         arch/TMS320C64x/TMS320C64xMapping.h
     )
-    set(TEST_SOURCES ${TEST_SOURCES} test_tms320c64x.c)
 endif()
 
 if(CAPSTONE_M680X_SUPPORT)
@@ -503,7 +499,6 @@ if(CAPSTONE_M680X_SUPPORT)
         arch/M680X/M680XDisassembler.h
         arch/M680X/M680XDisassemblerInternals.h
     )
-    set(TEST_SOURCES ${TEST_SOURCES} test_m680x.c)
 endif()
 
 if(CAPSTONE_EVM_SUPPORT)
@@ -520,7 +515,6 @@ if(CAPSTONE_EVM_SUPPORT)
         arch/EVM/EVMMapping.h
         arch/EVM/EVMMappingInsn.inc
     )
-    set(TEST_SOURCES ${TEST_SOURCES} test_evm.c)
 endif()
 
 if(CAPSTONE_WASM_SUPPORT)
@@ -536,7 +530,6 @@ if(CAPSTONE_WASM_SUPPORT)
         arch/WASM/WASMInstPrinter.h
         arch/WASM/WASMMapping.h
     )
-    set(TEST_SOURCES ${TEST_SOURCES} test_wasm.c)
 endif()
 
 if(CAPSTONE_MOS65XX_SUPPORT)
@@ -547,7 +540,6 @@ if(CAPSTONE_MOS65XX_SUPPORT)
     set(HEADERS_SOURCES_MOS65XX
             arch/MOS65XX/MOS65XXDisassembler.h
     )
-    set(TEST_SOURCES ${TEST_SOURCES} test_mos65xx.c)
 endif()
 
 if(CAPSTONE_BPF_SUPPORT)
@@ -565,7 +557,6 @@ if(CAPSTONE_BPF_SUPPORT)
         arch/BPF/BPFMapping.h
         arch/BPF/BPFModule.h
     )
-    set(TEST_SOURCES ${TEST_SOURCES} test_bpf.c)
 endif()
 
 if(CAPSTONE_RISCV_SUPPORT)
@@ -591,7 +582,6 @@ if(CAPSTONE_RISCV_SUPPORT)
         arch/RISCV/RISCVMappingInsn.inc
         arch/RISCV/RISCVMappingInsnOp.inc
     )
-    set(TEST_SOURCES ${TEST_SOURCES} test_riscv.c)
 endif()
 
 if(CAPSTONE_SH_SUPPORT)
@@ -607,7 +597,6 @@ if(CAPSTONE_SH_SUPPORT)
         arch/SH/SHModule.h
         arch/SH/SHInsnTable.inc
     )
-    set(TEST_SOURCES ${TEST_SOURCES} test_sh.c)
 endif()
 
 if (CAPSTONE_TRICORE_SUPPORT)
@@ -628,7 +617,6 @@ if (CAPSTONE_TRICORE_SUPPORT)
             arch/TriCore/TriCoreMapping.h
             arch/TriCore/TriCoreModule.h
             )
-    set(TEST_SOURCES ${TEST_SOURCES} test_tricore.c)
 endif ()
 
 if (CAPSTONE_ALPHA_SUPPORT)
@@ -652,7 +640,6 @@ if (CAPSTONE_ALPHA_SUPPORT)
             arch/Alpha/AlphaGenCSMappingInsn.inc
             arch/Alpha/AlphaGenCSMappingInsnName.inc
             )
-    set(TEST_SOURCES ${TEST_SOURCES} test_alpha.c)
 endif ()
 
 if(CAPSTONE_HPPA_SUPPORT)
@@ -670,7 +657,6 @@ if(CAPSTONE_HPPA_SUPPORT)
         arch/HPPA/HPPAMapping.h
         arch/HPPA/HPPAModule.h
     )
-    set(TEST_SOURCES ${TEST_SOURCES} test_hppa.c)
 endif()
 
 if (CAPSTONE_LOONGARCH_SUPPORT)
@@ -688,7 +674,6 @@ if (CAPSTONE_LOONGARCH_SUPPORT)
             arch/LoongArch/LoongArchModule.h
             arch/LoongArch/LoongArchLinkage.h
             )
-    set(TEST_SOURCES ${TEST_SOURCES} test_loongarch.c)
 endif ()
 
 if (CAPSTONE_OSXKERNEL_SUPPORT)
@@ -766,27 +751,13 @@ if(BUILD_SHARED_LIBS)
     )
 endif()
 
-if(CAPSTONE_BUILD_TESTS)
-    set(CMAKE_FOLDER "Tests")
-    enable_testing()
-    foreach(TSRC ${TEST_SOURCES})
-        string(REGEX REPLACE ".c$" "" TBIN ${TSRC})
-        add_executable(${TBIN} "tests/${TSRC}")
-        target_link_libraries(${TBIN} PRIVATE capstone)
-        add_test(NAME "capstone_${TBIN}" COMMAND ${TBIN})
-    endforeach()
-    if(CAPSTONE_ARM_SUPPORT)
-        set(ARM_REGRESS_TEST test_arm_regression.c)
-        string(REGEX REPLACE ".c$" "" ARM_REGRESS_BIN ${ARM_REGRESS_TEST})
-        add_executable(${ARM_REGRESS_BIN} "suite/arm/${ARM_REGRESS_TEST}")
-        target_link_libraries(${ARM_REGRESS_BIN} PRIVATE capstone)
-        add_test(NAME "capstone_${ARM_REGRESS_BIN}" COMMAND ${ARM_REGRESS_BIN})
-    endif()
-    # fuzz target built with the tests
-    add_executable(fuzz_disasm suite/fuzz/onefile.c suite/fuzz/fuzz_disasm.c suite/fuzz/platform.c)
-    target_link_libraries(fuzz_disasm PRIVATE capstone)
-    unset(CMAKE_FOLDER)
-endif()
+# Fuzzer if this is moved to it's own CMakeLists.txt (as it should be)
+# the OSS fuzzer build fails. And must be fixed.
+# Simply because it builds the fuzzer there again with hard-coded paths.
+# See: https://github.com/google/oss-fuzz/blob/master/projects/capstone/build.sh
+# and: https://github.com/capstone-engine/capstone/issues/2454
+add_executable(fuzz_disasm ${PROJECT_SOURCE_DIR}/suite/fuzz/onefile.c ${PROJECT_SOURCE_DIR}/suite/fuzz/fuzz_disasm.c ${PROJECT_SOURCE_DIR}/suite/fuzz/platform.c)
+target_link_libraries(fuzz_disasm PRIVATE capstone)
 
 source_group("Source\\Engine" FILES ${SOURCES_ENGINE})
 source_group("Source\\ARM" FILES ${SOURCES_ARM})
@@ -900,7 +871,6 @@ if(CAPSTONE_INSTALL)
             "${CMAKE_CURRENT_BINARY_DIR}/cmake_uninstall.cmake"
             IMMEDIATE @ONLY
         )
-        set(CMAKE_FOLDER)
         add_custom_target(UNINSTALL COMMAND ${CMAKE_COMMAND} -P ${CMAKE_CURRENT_BINARY_DIR}/cmake_uninstall.cmake)
         set_target_properties(UNINSTALL PROPERTIES
             FOLDER CMakePredefinedTargets
@@ -919,32 +889,17 @@ if(CAPSTONE_BUILD_CSTOOL)
 endif()
 
 if(CAPSTONE_BUILD_CSTEST)
-    include(ExternalProject)
-    ExternalProject_Add(cmocka_ext
-        PREFIX extern
-        GIT_REPOSITORY "https://git.cryptomilk.org/projects/cmocka.git"
-        GIT_TAG "origin/stable-1.1"
-        GIT_SHALLOW true
-        CONFIGURE_COMMAND cmake -DBUILD_SHARED_LIBS=OFF ../cmocka_ext/
-        BUILD_COMMAND cmake --build . --config Release
-        INSTALL_COMMAND ""
-    )
-    set(CMOCKA_INCLUDE_DIR ${CMAKE_CURRENT_BINARY_DIR}/extern/src/cmocka_ext/include)
-    set(CMOCKA_LIB_DIR ${CMAKE_CURRENT_BINARY_DIR}/extern/src/cmocka_ext-build/src/)
-    add_library(cmocka STATIC IMPORTED)
-    set_target_properties(cmocka PROPERTIES IMPORTED_LOCATION ${CMOCKA_LIB_DIR}/libcmocka.a)
+    enable_testing()
+    set(CSTEST_DIR ${PROJECT_SOURCE_DIR}/suite/cstest)
+    add_subdirectory(${CSTEST_DIR})
 
-    file(GLOB CSTEST_SRC suite/cstest/src/*.c)
-    add_executable(cstest ${CSTEST_SRC})
-    add_dependencies(cstest cmocka_ext)
-    target_link_libraries(cstest PUBLIC capstone cmocka)
-    target_include_directories(cstest PRIVATE
-            $<BUILD_INTERFACE:${PROJECT_SOURCE_DIR}/include>
-            ${PROJECT_SOURCE_DIR}/suite/cstest/include
-            ${CMOCKA_INCLUDE_DIR}
-            )
+    # Integration and unit tests
+    set(TESTS_INTEGRATION_DIR ${PROJECT_SOURCE_DIR}/tests/integration)
+    add_subdirectory(${TESTS_INTEGRATION_DIR})
+    set(TESTS_UNIT_DIR ${PROJECT_SOURCE_DIR}/tests/unit)
+    add_subdirectory(${TESTS_UNIT_DIR})
 
-    if(CAPSTONE_INSTALL)
-        install(TARGETS cstest EXPORT capstone-targets DESTINATION ${CMAKE_INSTALL_BINDIR})
-    endif()
+    # Unit tests for auto-sync
+    set(AUTO_SYNC_C_TEST_DIR ${PROJECT_SOURCE_DIR}/suite/auto-sync/c_tests/)
+    add_subdirectory(${AUTO_SYNC_C_TEST_DIR})
 endif()
diff --git a/COMPILE_CMAKE.TXT b/COMPILE_CMAKE.TXT
index ad28dab88..abf143aad 100644
--- a/COMPILE_CMAKE.TXT
+++ b/COMPILE_CMAKE.TXT
@@ -1,8 +1,6 @@
 This documentation explains how to compile Capstone with CMake, focus on
 using Microsoft Visual C as the compiler.
 
-To compile Capstone on *nix, see COMPILE.TXT.
-
 To compile Capstone on Windows using Visual Studio, see COMPILE_MSVC.TXT.
 
                         *-*-*-*-*-*
@@ -57,7 +55,7 @@ Get CMake for free from http://www.cmake.org.
   - CAPSTONE_X86_REDUCE: change this to ON to make X86 binary smaller.
   - CAPSTONE_X86_ATT_DISABLE: change this to ON to disable AT&T syntax on x86.
   - CAPSTONE_DEBUG: change this to ON to enable extra debug assertions.
-  - CAPSTONE_BUILD_CSTEST: Build `cstest` in `suite/cstest/`
+  - CAPSTONE_BUILD_CSTEST: Build `cstest` in `suite/cstest/`. `cstest` requires `libyaml` on your system.
   - ENABLE_ASAN: Compiles Capstone with the address sanitizer.
 
   By default, Capstone use system dynamic memory management, and both DIET and X86_REDUCE
diff --git a/COMPILE.TXT b/COMPILE_MAKE.TXT
similarity index 98%
rename from COMPILE.TXT
rename to COMPILE_MAKE.TXT
index 63cbf3ecd..1bafd4dc7 100644
--- a/COMPILE.TXT
+++ b/COMPILE_MAKE.TXT
@@ -1,3 +1,11 @@
+
+# NOTICE
+
+> Please be aware that the Makefile build is deprecated.
+> Use cmake instead.
+
+<hr>
+
 This documentation explains how to compile, install & run Capstone on MacOSX,
 Linux, *BSD & Solaris. We also show steps to cross-compile for Microsoft Windows.
 
diff --git a/COMPILE_MSVC.TXT b/COMPILE_MSVC.TXT
index 77d16c558..4e023ceaa 100644
--- a/COMPILE_MSVC.TXT
+++ b/COMPILE_MSVC.TXT
@@ -1,7 +1,7 @@
 This documentation explains how to compile Capstone on Windows using
 Microsoft Visual Studio version 2010 or newer.
 
-To compile Capstone on *nix, see COMPILE.TXT
+To compile Capstone on *nix, see COMPILE_CMAKE.TXT
 
 To compile Capstone with CMake, see COMPILE_CMAKE.TXT
 
diff --git a/HACK.TXT b/HACK.TXT
index 5858f61cd..7085adcc3 100644
--- a/HACK.TXT
+++ b/HACK.TXT
@@ -3,7 +3,7 @@ Code structure
 
 Capstone source is organized as followings.
 
-.                   <- core engine + README + COMPILE.TXT etc
+.                   <- core engine + README + COMPILE_CMAKE.TXT etc
 ├── arch            <- code handling disasm engine for each arch
 │   ├── AArch64     <- AArch64 engine
 │   ├── Alpha       <- Alpha engine
@@ -39,7 +39,7 @@ Capstone source is organized as followings.
 └── xcode           <- Xcode support (for MacOSX compile)
 
 
-Follow the instructions in COMPILE.TXT for how to compile and run test code.
+Follow the instructions in COMPILE_CMAKE.TXT for how to compile and run test code.
 
 Note: if you find some strange bugs, it is recommended to firstly clean
 the code and try to recompile/reinstall again. This can be done with:
@@ -111,13 +111,13 @@ Compile:
 Tests:
 - tests/Makefile
 - tests/test_basic.c
-- tests/test_detail.c
 - tests/test_iter.c
 - tests/test_newarch.c
 - suite/fuzz/platform.c: add the architecture and its modes to the list of fuzzed platforms
 - suite/capstone_get_setup.c
 - suite/MC/newarch/mode.mc: samples
 - suite/test_corpus.py: correspondence between architecture and mode as text and architecture number for fuzzing
+- suite/cstest/
 
 Bindings:
 - bindings/Makefile
diff --git a/Makefile b/Makefile
index 15ca6db23..12214c28d 100644
--- a/Makefile
+++ b/Makefile
@@ -457,12 +457,6 @@ PKGCFGF = $(BLDIR)/$(LIBNAME).pc
 all: $(LIBRARY) $(ARCHIVE) $(PKGCFGF)
 ifeq (,$(findstring yes,$(CAPSTONE_BUILD_CORE_ONLY)))
 	@V=$(V) CC=$(CC) $(MAKE) -C cstool
-ifndef BUILDDIR
-	$(MAKE) -C tests
-else
-	$(MAKE) -C tests BUILDDIR=$(BLDIR)
-endif
-	$(call install-library,$(BLDIR)/tests/)
 endif
 
 ifeq ($(CAPSTONE_SHARED),yes)
@@ -556,9 +550,7 @@ clean:
 
 ifeq (,$(findstring yes,$(CAPSTONE_BUILD_CORE_ONLY)))
 	$(MAKE) -C cstool clean
-	$(MAKE) -C tests clean
 	$(MAKE) -C suite/fuzz clean
-	rm -f $(BLDIR)/tests/lib$(LIBNAME).$(EXT)
 endif
 
 ifdef BUILDDIR
@@ -583,23 +575,8 @@ dist:
 	git archive --format=tar.gz --prefix=capstone-$(DIST_VERSION)/ $(TAG) > capstone-$(DIST_VERSION).tgz
 	git archive --format=zip --prefix=capstone-$(DIST_VERSION)/ $(TAG) > capstone-$(DIST_VERSION).zip
 
-TESTS  = test_basic test_detail test_arm test_aarch64 test_m68k test_mips test_ppc test_sparc test_tricore test_hppa
-TESTS += test_systemz test_x86 test_xcore test_iter test_evm test_riscv test_mos65xx test_wasm test_bpf test_alpha
-TESTS += test_loongarch
-TESTS += test_basic.static test_detail.static test_arm.static test_aarch64.static
-TESTS += test_m68k.static test_mips.static test_ppc.static test_sparc.static
-TESTS += test_systemz.static test_x86.static test_xcore.static test_m680x.static
-TESTS += test_skipdata test_skipdata.static test_iter.static test_evm.static test_riscv.static
-TESTS += test_mos65xx.static test_wasm.static test_bpf.static test_alpha.static test_hppa.static
-TESTS += test_loongarch.static
-
-check: $(TESTS)
-
 checkfuzz: fuzztest fuzzallcorp
 
-test_%:
-	./tests/$@ > /dev/null && echo OK || echo FAILED
-
 FUZZ_INPUTS = $(shell find suite/MC -type f -name '*.cs')
 
 buildfuzz:
diff --git a/Mapping.c b/Mapping.c
index 2f871273d..c4f352185 100644
--- a/Mapping.c
+++ b/Mapping.c
@@ -400,3 +400,44 @@ void map_set_alias_id(MCInst *MI, const SStream *O, const name_map *alias_mnem_i
 	MI->flat_insn->alias_id = name2id(alias_mnem_id_map, map_size, alias_mnem);
 }
 
+/// Does a binary search over the given map and searches for @id.
+/// If @id exists in @map, it sets @found to true and returns
+/// the value for the @id.
+/// Otherwise, @found is set to false and it returns UINT64_MAX.
+///
+/// Of course it assumes the map is sorted.
+uint64_t enum_map_bin_search(const cs_enum_id_map *map, size_t map_len,
+			     const char *id, bool *found)
+{
+	size_t l = 0;
+	size_t r = map_len;
+	size_t id_len = strlen(id);
+
+	while (l <= r) {
+		size_t m = (l + r) / 2;
+		size_t j = 0;
+		size_t i = 0;
+		size_t entry_len = strlen(map[m].str);
+
+		while (j < entry_len && i < id_len && id[i] == map[m].str[j]) {
+			++j, ++i;
+		}
+		if (i == id_len && j == entry_len) {
+			*found = true;
+			return map[m].val;
+		}
+
+		if (id[i] < map[m].str[j]) {
+			r = m - 1;
+		} else if (id[i] > map[m].str[j]) {
+			l = m + 1;
+		}
+		if (m == 0 || (l + r) / 2 >= map_len) {
+			// Break before we go out of bounds.
+			break;
+		}
+	}
+	*found = false;
+	return UINT64_MAX;
+}
+
diff --git a/Mapping.h b/Mapping.h
index 3efd3f3ca..a2f60cabf 100644
--- a/Mapping.h
+++ b/Mapping.h
@@ -232,4 +232,27 @@ bool map_use_alias_details(const MCInst *MI);
 
 void map_set_alias_id(MCInst *MI, const SStream *O, const name_map *alias_mnem_id_map, int map_size);
 
+/// Mapping from Capstone enumeration identifiers and their values.
+///
+/// This map MUST BE sorted to allow binary searches.
+/// Please always ensure the map is sorted after you added a value.
+///
+/// You can sort the map with Python.
+/// Copy the map into a file and run:
+///
+/// ```python
+/// with open("/tmp/file_with_map_entries") as f:
+///     text = f.readlines()
+///
+/// text.sort()
+/// print(''.join(text))
+/// ```
+typedef struct {
+	const char *str; ///< The name of the enumeration identifier
+	uint64_t val;	 ///< The value of the identifier
+} cs_enum_id_map;
+
+uint64_t enum_map_bin_search(const cs_enum_id_map *map, size_t map_len,
+			     const char *id, bool *found);
+
 #endif // CS_MAPPING_H
diff --git a/README.md b/README.md
index f1a53a0e0..9dbfbe542 100644
--- a/README.md
+++ b/README.md
@@ -49,7 +49,7 @@ Further information is available at https://www.capstone-engine.org
 Compile
 -------
 
-See COMPILE.TXT file for how to compile and install Capstone.
+See [COMPILE_CMAKE.TXT](COMPILE_CMAKE.TXT) file for how to compile and install Capstone.
 
 
 Documentation
diff --git a/arch/AArch64/AArch64GenDisassemblerTables.inc b/arch/AArch64/AArch64GenDisassemblerTables.inc
index 6956ba259..015d8f709 100644
--- a/arch/AArch64/AArch64GenDisassemblerTables.inc
+++ b/arch/AArch64/AArch64GenDisassemblerTables.inc
@@ -35510,6 +35510,7 @@ static DecodeStatus fname(const uint8_t DecodeTable[], MCInst *MI, \
         /* Decoding complete. */ \
         return S; \
       } else { \
+        MCInst_clear(MI); \
         /* If the decoding was incomplete, skip. */ \
         Ptr += NumToSkip; \
         /* Reset decode status. This also drops a SoftFail status that could be */ \
diff --git a/arch/AArch64/AArch64InstPrinter.c b/arch/AArch64/AArch64InstPrinter.c
index 73acbaf15..4db25f2ab 100644
--- a/arch/AArch64/AArch64InstPrinter.c
+++ b/arch/AArch64/AArch64InstPrinter.c
@@ -462,12 +462,18 @@ void printInst(MCInst *MI, uint64_t Address, const char *Annot, SStream *O)
 	if ((Opcode == AArch64_MOVZXi || Opcode == AArch64_MOVZWi ||
 	     Opcode == AArch64_MOVNXi || Opcode == AArch64_MOVNWi) &&
 	    MCOperand_isExpr(MCInst_getOperand(MI, (1)))) {
-		SStream_concat0(O, "<llvm-expr>");
+		printUInt64Bang(O, MCInst_getOpVal(MI, 1));
+		if (detail_is_set(MI) && useAliasDetails) {
+			AArch64_set_detail_op_imm(MI, 1, AARCH64_OP_IMM, MCInst_getOpVal(MI, 1));
+		}
 	}
 
 	if ((Opcode == AArch64_MOVKXi || Opcode == AArch64_MOVKWi) &&
 	    MCOperand_isExpr(MCInst_getOperand(MI, (2)))) {
-		SStream_concat0(O, "<llvm-expr>");
+		printUInt64Bang(O, MCInst_getOpVal(MI, 2));
+		if (detail_is_set(MI) && useAliasDetails) {
+			AArch64_set_detail_op_imm(MI, 2, AARCH64_OP_IMM, MCInst_getOpVal(MI, 2));
+		}
 	}
 
 	// MOVZ, MOVN and "ORR wzr, #imm" instructions are aliases for MOV, but
@@ -994,7 +1000,7 @@ void printOperand(MCInst *MI, unsigned OpNo, SStream *O)
 		printInt64Bang(O, MCOperand_getImm(Op));
 		SStream_concat0(O, markup(">"));
 	} else {
-		SStream_concat0(O, "<llvm-expr>");
+		printUInt64Bang(O, MCInst_getOpVal(MI, OpNo));
 	}
 }
 
@@ -1282,7 +1288,7 @@ DEFINE_printRegWithShiftExtend(false, 128, x, 0);
 			assert(0 && \
 			       "Unsupported predicate-as-counter register"); \
 		SStream_concat(O, "%s", "pn"); \
-		printUInt32(O, (Reg - AArch64_P0)); \
+		printUInt32(O, (Reg - AArch64_PN0)); \
 		switch (EltSize) { \
 		case 0: \
 			break; \
@@ -1380,7 +1386,7 @@ void printUImm12Offset(MCInst *MI, unsigned OpNum, unsigned Scale, SStream *O)
 		printUInt32Bang(O, (MCOperand_getImm(MO) * Scale));
 		SStream_concat0(O, markup(">"));
 	} else {
-		SStream_concat0(O, "<llvm-expr>");
+		printUInt64Bang(O, MCOperand_getImm(MO));
 	}
 }
 
@@ -1395,7 +1401,7 @@ void printAMIndexedWB(MCInst *MI, unsigned OpNum, unsigned Scale, SStream *O)
 		printUInt32Bang(O, MCOperand_getImm(MO1) * Scale);
 		SStream_concat0(O, markup(">"));
 	} else {
-		SStream_concat0(O, "<llvm-expr>");
+		printUInt64Bang(O, MCOperand_getImm(MO1));
 	}
 	SStream_concat0(O, "]");
 }
@@ -1964,7 +1970,7 @@ void printImplicitlyTypedVectorList(MCInst *MI, unsigned OpNum, SStream *O)
 					    NumLanes), \
 				     LaneKind), \
 			      OpNum, NumLanes, CHAR(LaneKind)); \
-		if (CHAR(LaneKind) == 0) { \
+		if (CHAR(LaneKind) == '0') { \
 			printVectorList(MI, OpNum, O, ""); \
 			return; \
 		} \
@@ -2026,7 +2032,7 @@ void printAlignedLabel(MCInst *MI, uint64_t Address, unsigned OpNum, SStream *O)
 		return;
 	}
 
-	SStream_concat0(O, "<llvm-expr>");
+	printUInt64Bang(O, MCOperand_getImm(Op));
 }
 
 void printAdrLabel(MCInst *MI, uint64_t Address, unsigned OpNum, SStream *O)
@@ -2048,7 +2054,7 @@ void printAdrLabel(MCInst *MI, uint64_t Address, unsigned OpNum, SStream *O)
 		return;
 	}
 
-	SStream_concat0(O, "<llvm-expr>");
+	printUInt64Bang(O, MCOperand_getImm(Op));
 }
 
 void printAdrpLabel(MCInst *MI, uint64_t Address, unsigned OpNum, SStream *O)
@@ -2070,7 +2076,7 @@ void printAdrpLabel(MCInst *MI, uint64_t Address, unsigned OpNum, SStream *O)
 		return;
 	}
 
-	SStream_concat0(O, "<llvm-expr>");
+	printUInt64Bang(O, MCOperand_getImm(Op));
 }
 
 void printAdrAdrpLabel(MCInst *MI, uint64_t Address, unsigned OpNum, SStream *O) {
@@ -2095,7 +2101,7 @@ void printAdrAdrpLabel(MCInst *MI, uint64_t Address, unsigned OpNum, SStream *O)
     return;
   }
 
-	SStream_concat0(O, "<llvm-expr>");
+	printUInt64Bang(O, MCOperand_getImm(Op));
 }
 
 void printBarrierOption(MCInst *MI, unsigned OpNo, SStream *O)
@@ -2287,6 +2293,8 @@ void printSVEPattern(MCInst *MI, unsigned OpNum, SStream *O)
 		AArch64SVEPredPattern_lookupSVEPREDPATByEncoding(Val);
 	if (Pat)
 		SStream_concat0(O, Pat->Name);
+	else
+		printUInt32Bang(O, Val);
 }
 
 void printSVEVecLenSpecifier(MCInst *MI, unsigned OpNum, SStream *O)
@@ -2371,7 +2379,7 @@ DECLARE_printImmSVE_U64(uint64_t);
 #define DEFINE_isSignedType(T) \
 	static inline bool CONCAT(isSignedType, T)() \
 	{ \
-		return CHAR(t) == 'i'; \
+		return CHAR(T) == 'i'; \
 	}
 DEFINE_isSignedType(int8_t);
 DEFINE_isSignedType(int16_t);
diff --git a/arch/AArch64/AArch64Mapping.c b/arch/AArch64/AArch64Mapping.c
index ceaaff7d9..68d588c19 100644
--- a/arch/AArch64/AArch64Mapping.c
+++ b/arch/AArch64/AArch64Mapping.c
@@ -97,9 +97,9 @@ static void setup_sme_operand(MCInst *MI)
 	AArch64_get_detail_op(MI, 0)->sme.type = AARCH64_SME_OP_INVALID;
 	AArch64_get_detail_op(MI, 0)->sme.tile = AARCH64_REG_INVALID;
 	AArch64_get_detail_op(MI, 0)->sme.slice_reg = AARCH64_REG_INVALID;
-	AArch64_get_detail_op(MI, 0)->sme.slice_offset.imm = -1;
-	AArch64_get_detail_op(MI, 0)->sme.slice_offset.imm_range.first = -1;
-	AArch64_get_detail_op(MI, 0)->sme.slice_offset.imm_range.offset = -1;
+	AArch64_get_detail_op(MI, 0)->sme.slice_offset.imm = AARCH64_SLICE_IMM_INVALID;
+	AArch64_get_detail_op(MI, 0)->sme.slice_offset.imm_range.first = AARCH64_SLICE_IMM_RANGE_INVALID;
+	AArch64_get_detail_op(MI, 0)->sme.slice_offset.imm_range.offset = AARCH64_SLICE_IMM_RANGE_INVALID;
 }
 
 static void setup_pred_operand(MCInst *MI)
@@ -556,6 +556,9 @@ static void AArch64_add_not_defined_ops(MCInst *MI, const SStream *OS)
 	default:
 		return;
 	case AARCH64_INS_ALIAS_FMOV:
+		if (AArch64_get_detail_op(MI, -1)->type == AARCH64_OP_FP) {
+			break;
+		}
 		AArch64_insert_detail_op_float_at(MI, -1, 0.0f, CS_AC_READ);
 		break;
 	case AARCH64_INS_ALIAS_LD1:
@@ -1315,6 +1318,10 @@ static void add_cs_detail_general(MCInst *MI, aarch64_op_group op_group,
 			int64_t Offset = MCInst_getOpVal(MI, OpNum);
 			AArch64_set_detail_op_imm(MI, OpNum, AARCH64_OP_IMM,
 						  (MI->address & -4) + Offset);
+		} else {
+			// Expression
+			AArch64_set_detail_op_imm(MI, OpNum, AARCH64_OP_IMM,
+						  MCOperand_isImm(MCInst_getOperand(MI, OpNum)));
 		}
 		break;
 	}
@@ -1323,11 +1330,18 @@ static void add_cs_detail_general(MCInst *MI, aarch64_op_group op_group,
 			int64_t Offset = MCInst_getOpVal(MI, OpNum) * 4096;
 			AArch64_set_detail_op_imm(MI, OpNum, AARCH64_OP_IMM,
 						  (MI->address & -4096) + Offset);
+		} else {
+			// Expression
+			AArch64_set_detail_op_imm(MI, OpNum, AARCH64_OP_IMM,
+						  MCOperand_isImm(MCInst_getOperand(MI, OpNum)));
 		}
 		break;
 	}
 	case AArch64_OP_GROUP_AdrAdrpLabel: {
 		if (!MCOperand_isImm(MCInst_getOperand(MI, OpNum))) {
+			// Expression
+			AArch64_set_detail_op_imm(MI, OpNum, AARCH64_OP_IMM,
+						  MCOperand_isImm(MCInst_getOperand(MI, OpNum)));
 			break;
 		}
 		int64_t Offset = MCInst_getOpVal(MI, OpNum);
@@ -1345,6 +1359,10 @@ static void add_cs_detail_general(MCInst *MI, aarch64_op_group op_group,
 			int64_t Offset = MCInst_getOpVal(MI, OpNum) * 4;
 			AArch64_set_detail_op_imm(MI, OpNum, AARCH64_OP_IMM,
 						  MI->address + Offset);
+		} else {
+			// Expression
+			AArch64_set_detail_op_imm(MI, OpNum, AARCH64_OP_IMM,
+						  MCOperand_isImm(MCInst_getOperand(MI, OpNum)));
 		}
 		break;
 	}
@@ -1502,7 +1520,7 @@ static void add_cs_detail_general(MCInst *MI, aarch64_op_group op_group,
 			AArch64_set_detail_op_sme(MI, OpNum,
 						  AARCH64_SME_MATRIX_TILE_LIST,
 						  AARCH64LAYOUT_VL_D,
-						  AARCH64_REG_ZAD0 + I);
+						  (int) (AARCH64_REG_ZAD0 + I));
 			AArch64_inc_op_count(MI);
 		}
 		break;
@@ -1607,8 +1625,10 @@ static void add_cs_detail_general(MCInst *MI, aarch64_op_group op_group,
 		unsigned Val = MCInst_getOpVal(MI, OpNum);
 		const AArch64SVEPredPattern_SVEPREDPAT *Pat =
 			AArch64SVEPredPattern_lookupSVEPREDPATByEncoding(Val);
-		if (!Pat)
+		if (!Pat) {
+			AArch64_set_detail_op_imm(MI, OpNum, AARCH64_OP_IMM, Val);
 			break;
+		}
 		aarch64_sysop sysop;
 		sysop.alias = Pat->SysAlias;
 		sysop.sub_type = AARCH64_OP_SVEPREDPAT;
@@ -1738,6 +1758,7 @@ static void add_cs_detail_template_1(MCInst *MI, aarch64_op_group op_group,
 				     (1 << AArch64_AM_getShiftValue(Shift));
 			AArch64_set_detail_op_imm(MI, OpNum, AARCH64_OP_IMM,
 						  Val);
+			break;
 		}
 		case AArch64_OP_GROUP_Imm8OptLsl_uint16_t:
 		case AArch64_OP_GROUP_Imm8OptLsl_uint32_t:
@@ -1747,6 +1768,7 @@ static void add_cs_detail_template_1(MCInst *MI, aarch64_op_group op_group,
 				      (1 << AArch64_AM_getShiftValue(Shift));
 			AArch64_set_detail_op_imm(MI, OpNum, AARCH64_OP_IMM,
 						  Val);
+			break;
 		}
 		}
 		break;
@@ -1791,7 +1813,7 @@ static void add_cs_detail_template_1(MCInst *MI, aarch64_op_group op_group,
 				AArch64_set_detail_op_sme(MI, OpNum,
 							  AARCH64_SME_MATRIX_SLICE_OFF,
 							  AARCH64LAYOUT_INVALID,
-							  MCInst_getOpVal(MI, OpNum) * scale);
+							  (uint32_t) (MCInst_getOpVal(MI, OpNum) * scale));
 		} else if (AArch64_get_detail_op(MI, 0)->type == AARCH64_OP_PRED) {
 			// The index is part of a predicate
 			AArch64_set_detail_op_pred(MI, OpNum);
@@ -1852,7 +1874,7 @@ static void add_cs_detail_template_1(MCInst *MI, aarch64_op_group op_group,
 		unsigned EltSize = temp_arg_0;
 		AArch64_get_detail_op(MI, 0)->vas = EltSize;
 		AArch64_set_detail_op_reg(
-			MI, OpNum, MCInst_getOpVal(MI, OpNum) - AArch64_P0);
+			MI, OpNum, MCInst_getOpVal(MI, OpNum) - AArch64_PN0);
 		break;
 	}
 	case AArch64_OP_GROUP_PrefetchOp_0:
@@ -1925,7 +1947,8 @@ static void add_cs_detail_template_1(MCInst *MI, aarch64_op_group op_group,
 	case AArch64_OP_GROUP_UImm12Offset_2:
 	case AArch64_OP_GROUP_UImm12Offset_4:
 	case AArch64_OP_GROUP_UImm12Offset_8: {
-		unsigned Scale = temp_arg_0;
+		// Otherwise it is an expression. For which we only add the immediate
+		unsigned Scale = MCOperand_isImm(MCInst_getOperand(MI, OpNum)) ? temp_arg_0 : 1;
 		AArch64_set_detail_op_imm(MI, OpNum, AARCH64_OP_IMM,
 					  Scale * MCInst_getOpVal(MI, OpNum));
 		break;
@@ -2050,6 +2073,7 @@ static void add_cs_detail_template_2(MCInst *MI, aarch64_op_group op_group,
 	case AArch64_OP_GROUP_TypedVectorList_0_h:
 	case AArch64_OP_GROUP_TypedVectorList_0_q:
 	case AArch64_OP_GROUP_TypedVectorList_0_s:
+	case AArch64_OP_GROUP_TypedVectorList_0_0:
 	case AArch64_OP_GROUP_TypedVectorList_16_b:
 	case AArch64_OP_GROUP_TypedVectorList_1_d:
 	case AArch64_OP_GROUP_TypedVectorList_2_d:
@@ -2107,7 +2131,7 @@ static void add_cs_detail_template_2(MCInst *MI, aarch64_op_group op_group,
 		case 'q':
 			vas = AARCH64LAYOUT_VL_Q;
 			break;
-		case '\0':
+		case '0':
 			// Implicitly Typed register
 			break;
 		}
@@ -2389,6 +2413,7 @@ void AArch64_add_cs_detail(MCInst *MI, int /* aarch64_op_group */ op_group,
 	case AArch64_OP_GROUP_TypedVectorList_0_h:
 	case AArch64_OP_GROUP_TypedVectorList_0_q:
 	case AArch64_OP_GROUP_TypedVectorList_0_s:
+	case AArch64_OP_GROUP_TypedVectorList_0_0:
 	case AArch64_OP_GROUP_TypedVectorList_16_b:
 	case AArch64_OP_GROUP_TypedVectorList_1_d:
 	case AArch64_OP_GROUP_TypedVectorList_2_d:
@@ -2500,7 +2525,7 @@ void AArch64_set_detail_op_imm(MCInst *MI, unsigned OpNum,
 		if (AArch64_get_detail_op(MI, 0)->type == AARCH64_OP_SME) {
 			AArch64_set_detail_op_sme(MI, OpNum,
 						  AARCH64_SME_MATRIX_SLICE_OFF,
-						  AARCH64LAYOUT_INVALID, 1);
+						  AARCH64LAYOUT_INVALID, (uint32_t) 1);
 		} else if (AArch64_get_detail_op(MI, 0)->type == AARCH64_OP_PRED) {
 			AArch64_set_detail_op_pred(MI, OpNum);
 		} else {
@@ -2524,7 +2549,7 @@ void AArch64_set_detail_op_imm(MCInst *MI, unsigned OpNum,
 }
 
 void AArch64_set_detail_op_imm_range(MCInst *MI, unsigned OpNum,
-				     int64_t FirstImm, int64_t Offset)
+				     uint32_t FirstImm, uint32_t Offset)
 {
 	if (!detail_is_set(MI))
 		return;
@@ -2534,8 +2559,8 @@ void AArch64_set_detail_op_imm_range(MCInst *MI, unsigned OpNum,
 		if (AArch64_get_detail_op(MI, 0)->type == AARCH64_OP_SME) {
 			AArch64_set_detail_op_sme(MI, OpNum,
 						  AARCH64_SME_MATRIX_SLICE_OFF_RANGE,
-						  AARCH64LAYOUT_INVALID, FirstImm,
-						  Offset);
+						  AARCH64LAYOUT_INVALID, (uint32_t) FirstImm,
+						  (uint32_t) Offset);
 		} else if (AArch64_get_detail_op(MI, 0)->type == AARCH64_OP_PRED) {
 			assert(0 && "Unkown SME predicate imm range type");
 		} else {
@@ -2694,15 +2719,15 @@ void AArch64_set_detail_op_sme(MCInst *MI, unsigned OpNum,
 	if (!detail_is_set(MI))
 		return;
 	AArch64_get_detail_op(MI, 0)->type = AARCH64_OP_SME;
-	va_list args;
 	switch (part) {
 	default:
 		printf("Unhandled SME operand part %d\n", part);
 		assert(0);
-	case AARCH64_SME_MATRIX_TILE_LIST:
+	case AARCH64_SME_MATRIX_TILE_LIST: {
 		setup_sme_operand(MI);
+		va_list args;
 		va_start(args, vas);
-		int Tile = va_arg(args, int);
+		int Tile = va_arg(args, int); // NOLINT(clang-analyzer-valist.Uninitialized)
 		va_end(args);
 		AArch64_get_detail_op(MI, 0)->sme.type = AARCH64_SME_OP_TILE;
 		AArch64_get_detail_op(MI, 0)->sme.tile = Tile;
@@ -2710,6 +2735,7 @@ void AArch64_set_detail_op_sme(MCInst *MI, unsigned OpNum,
 		AArch64_get_detail_op(MI, 0)->access = map_get_op_access(MI, OpNum);
 		AArch64_get_detail(MI)->is_doing_sme = true;
 		break;
+	}
 	case AARCH64_SME_MATRIX_TILE:
 		assert(map_get_op_type(MI, OpNum) == CS_OP_REG);
 
@@ -2731,23 +2757,26 @@ void AArch64_set_detail_op_sme(MCInst *MI, unsigned OpNum,
 		AArch64_get_detail_op(MI, 0)->sme.slice_reg =
 			MCInst_getOpVal(MI, OpNum);
 		break;
-	case AARCH64_SME_MATRIX_SLICE_OFF:
+	case AARCH64_SME_MATRIX_SLICE_OFF: {
 		assert((map_get_op_type(MI, OpNum) & ~(CS_OP_MEM | CS_OP_BOUND)) == CS_OP_IMM);
 		// Because we took care of the slice register before, the op at -1 must be a SME operand.
 		assert(AArch64_get_detail_op(MI, 0)->type ==
 		       AARCH64_OP_SME);
 		assert(AArch64_get_detail_op(MI, 0)->sme.slice_offset.imm ==
-		       -1);
+		       AARCH64_SLICE_IMM_INVALID);
+		va_list args;
 		va_start(args, vas);
-		int64_t offset = va_arg(args, int64_t);
+		uint16_t offset = va_arg(args, uint32_t); // NOLINT(clang-analyzer-valist.Uninitialized)
 		va_end(args);
 		AArch64_get_detail_op(MI, 0)->sme.slice_offset.imm =
 			offset;
 		break;
+	}
 	case AARCH64_SME_MATRIX_SLICE_OFF_RANGE: {
+		va_list args;
 		va_start(args, vas);
-		int8_t First = va_arg(args, int);
-		int8_t Offset = va_arg(args, int);
+		uint8_t First = va_arg(args, uint32_t); // NOLINT(clang-analyzer-valist.Uninitialized)
+		uint8_t Offset = va_arg(args, uint32_t); // NOLINT(clang-analyzer-valist.Uninitialized)
 		va_end(args);
 		AArch64_get_detail_op(MI, 0)->sme.slice_offset.imm_range.first =
 			First;
diff --git a/arch/AArch64/AArch64Mapping.h b/arch/AArch64/AArch64Mapping.h
index dd47fee57..3afdbeefc 100644
--- a/arch/AArch64/AArch64Mapping.h
+++ b/arch/AArch64/AArch64Mapping.h
@@ -56,7 +56,7 @@ void AArch64_set_detail_op_reg(MCInst *MI, unsigned OpNum, aarch64_reg Reg);
 void AArch64_set_detail_op_imm(MCInst *MI, unsigned OpNum,
 			       aarch64_op_type ImmType, int64_t Imm);
 void AArch64_set_detail_op_imm_range(MCInst *MI, unsigned OpNum,
-				     int64_t FirstImm, int64_t offset);
+				     uint32_t FirstImm, uint32_t offset);
 void AArch64_set_detail_op_mem(MCInst *MI, unsigned OpNum, uint64_t Val);
 void AArch64_set_detail_op_mem_offset(MCInst *MI, unsigned OpNum, uint64_t Val);
 void AArch64_set_detail_shift_ext(MCInst *MI, unsigned OpNum, bool SignExtend,
diff --git a/arch/Alpha/AlphaModule.c b/arch/Alpha/AlphaModule.c
index 271f17765..4d2279c6c 100644
--- a/arch/Alpha/AlphaModule.c
+++ b/arch/Alpha/AlphaModule.c
@@ -32,8 +32,11 @@ cs_err ALPHA_global_init(cs_struct *ud)
 
 cs_err ALPHA_option(cs_struct *handle, cs_opt_type type, size_t value)
 {
-	if (type == CS_OPT_SYNTAX)
+	if (type == CS_OPT_SYNTAX) {
 		handle->syntax = (int)value;
+	} else if (type == CS_OPT_MODE) {
+		handle->mode = (cs_mode)value;
+	}
 
 	return CS_ERR_OK;
 }
diff --git a/arch/M68K/M68KDisassembler.c b/arch/M68K/M68KDisassembler.c
index 5c555ae4c..61d8b3dbf 100644
--- a/arch/M68K/M68KDisassembler.c
+++ b/arch/M68K/M68KDisassembler.c
@@ -278,10 +278,10 @@ static unsigned int peek_imm_16(const m68k_info *info) { return m68k_read_safe_1
 static unsigned int peek_imm_32(const m68k_info *info) { return m68k_read_safe_32((info), (info)->pc); }
 static unsigned long long peek_imm_64(const m68k_info *info) { return m68k_read_safe_64((info), (info)->pc); }
 
-static unsigned int read_imm_8(m68k_info *info)  { const unsigned int value = peek_imm_8(info);  (info)->pc+=2; return value; }
-static unsigned int read_imm_16(m68k_info *info) { const unsigned int value = peek_imm_16(info); (info)->pc+=2; return value; }
-static unsigned int read_imm_32(m68k_info *info) { const unsigned int value = peek_imm_32(info); (info)->pc+=4; return value; }
-static unsigned long long read_imm_64(m68k_info *info) { const unsigned long long value = peek_imm_64(info); (info)->pc+=8; return value; }
+static unsigned int read_imm_8(m68k_info *info)  { const unsigned int value = peek_imm_8(info);  (info)->pc+=2; return value & 0xff; }
+static unsigned int read_imm_16(m68k_info *info) { const unsigned int value = peek_imm_16(info); (info)->pc+=2; return value & 0xffff; }
+static unsigned int read_imm_32(m68k_info *info) { const unsigned int value = peek_imm_32(info); (info)->pc+=4; return value & 0xffffffff; }
+static unsigned long long read_imm_64(m68k_info *info) { const unsigned long long value = peek_imm_64(info); (info)->pc+=8; return value & 0xffffffffffffffff; }
 
 /* Fake a split interface */
 #define get_ea_mode_str_8(instruction) get_ea_mode_str(instruction, 0)
@@ -472,9 +472,9 @@ static void get_ea_mode_op(m68k_info *info, cs_m68k_op* op, uint32_t instruction
 			op->type = M68K_OP_IMM;
 
 			if (size == 1)
-				op->imm = read_imm_8(info) & 0xff;
+				op->imm = read_imm_8(info);
 			else if (size == 2)
-				op->imm = read_imm_16(info) & 0xffff;
+				op->imm = read_imm_16(info);
 			else if (size == 4)
 				op->imm = read_imm_32(info);
 			else
@@ -604,7 +604,7 @@ static void build_imm_ea(m68k_info *info, int opcode, uint8_t size, int imm)
 
 	op0->type = M68K_OP_IMM;
 	op0->address_mode = M68K_AM_IMMEDIATE;
-	op0->imm = imm;
+	op0->imm = imm & info->address_mask;
 
 	get_ea_mode_op(info, op1, info->ir, size);
 }
@@ -878,7 +878,8 @@ static uint16_t reverse_bits(uint32_t v)
 		s--;
 	}
 
-	return r <<= s; // shift when v's highest bits are zero
+	r <<= s; // shift when v's highest bits are zero
+	return r;
 }
 
 static uint8_t reverse_bits_8(uint32_t v)
@@ -892,7 +893,8 @@ static uint8_t reverse_bits_8(uint32_t v)
 		s--;
 	}
 
-	return r <<= s; // shift when v's highest bits are zero
+	r <<= s; // shift when v's highest bits are zero
+	return r;
 }
 
 
diff --git a/arch/M68K/M68KInstPrinter.c b/arch/M68K/M68KInstPrinter.c
index f6805ed97..1268a46f5 100644
--- a/arch/M68K/M68KInstPrinter.c
+++ b/arch/M68K/M68KInstPrinter.c
@@ -1,17 +1,6 @@
 /* Capstone Disassembly Engine */
 /* M68K Backend by Daniel Collin <daniel@collin.com> 2015-2016 */
 
-#ifdef _MSC_VER
-// Disable security warnings for strcat & sprintf
-#ifndef _CRT_SECURE_NO_WARNINGS
-#define _CRT_SECURE_NO_WARNINGS
-#endif
-
-//Banned API Usage : strcat / sprintf is a Banned API as listed in dontuse.h for
-//security purposes.
-#pragma warning(disable:28719)
-#endif
-
 #include <stdio.h>	// DEBUG
 #include <stdlib.h>
 #include <string.h>
@@ -78,7 +67,7 @@ static const char* getRegName(m68k_reg reg)
 	return s_reg_names[(int)reg];
 }
 
-static void printRegbitsRange(char* buffer, uint32_t data, const char* prefix)
+static void printRegbitsRange(char* buffer, size_t buf_len, uint32_t data, const char* prefix)
 {
 	unsigned int first = 0;
 	unsigned int run_length = 0;
@@ -95,11 +84,11 @@ static void printRegbitsRange(char* buffer, uint32_t data, const char* prefix)
 			}
 
 			if (buffer[0] != 0)
-				strcat(buffer, "/");
+				strncat(buffer, "/", buf_len - 1);
 
-			sprintf(buffer + strlen(buffer), "%s%d", prefix, first);
+			snprintf(buffer + strlen(buffer), buf_len, "%s%d", prefix, first);
 			if (run_length > 0)
-				sprintf(buffer + strlen(buffer), "-%s%d", prefix, first + run_length);
+				snprintf(buffer + strlen(buffer), buf_len, "-%s%d", prefix, first + run_length);
 		}
 	}
 }
@@ -116,9 +105,9 @@ static void registerBits(SStream* O, const cs_m68k_op* op)
 		return;
 	}
 
-	printRegbitsRange(buffer, data & 0xff, "d");
-	printRegbitsRange(buffer, (data >> 8) & 0xff, "a");
-	printRegbitsRange(buffer, (data >> 16) & 0xff, "fp");
+	printRegbitsRange(buffer, sizeof(buffer), data & 0xff, "d");
+	printRegbitsRange(buffer, sizeof(buffer), (data >> 8) & 0xff, "a");
+	printRegbitsRange(buffer, sizeof(buffer), (data >> 16) & 0xff, "fp");
 
 	SStream_concat(O, "%s", buffer);
 }
@@ -386,3 +375,24 @@ const char *M68K_group_name(csh handle, unsigned int id)
 #endif
 }
 
+#ifndef CAPSTONE_DIET
+void M68K_reg_access(const cs_insn *insn,
+		cs_regs regs_read, uint8_t *regs_read_count,
+		cs_regs regs_write, uint8_t *regs_write_count)
+{
+	uint8_t read_count, write_count;
+
+	read_count = insn->detail->regs_read_count;
+	write_count = insn->detail->regs_write_count;
+
+	// implicit registers
+	memcpy(regs_read, insn->detail->regs_read,
+	       read_count * sizeof(insn->detail->regs_read[0]));
+	memcpy(regs_write, insn->detail->regs_write,
+	       write_count * sizeof(insn->detail->regs_write[0]));
+
+	*regs_read_count = read_count;
+	*regs_write_count = write_count;
+}
+#endif
+
diff --git a/arch/M68K/M68KInstPrinter.h b/arch/M68K/M68KInstPrinter.h
index 45841ed2d..8b9ed1b62 100644
--- a/arch/M68K/M68KInstPrinter.h
+++ b/arch/M68K/M68KInstPrinter.h
@@ -17,5 +17,10 @@ void M68K_get_insn_id(cs_struct* h, cs_insn* insn, unsigned int id);
 const char *M68K_insn_name(csh handle, unsigned int id);
 const char* M68K_group_name(csh handle, unsigned int id);
 void M68K_post_printer(csh handle, cs_insn* flat_insn, char* insn_asm, MCInst* mci);
+#ifndef CAPSTONE_DIET
+void M68K_reg_access(const cs_insn *insn,
+		cs_regs regs_read, uint8_t *regs_read_count,
+		cs_regs regs_write, uint8_t *regs_write_count);
+#endif
 
 #endif
diff --git a/arch/M68K/M68KModule.c b/arch/M68K/M68KModule.c
index 03e73f7b9..799b2c4c0 100644
--- a/arch/M68K/M68KModule.c
+++ b/arch/M68K/M68KModule.c
@@ -13,7 +13,7 @@ cs_err M68K_global_init(cs_struct *ud)
 {
 	m68k_info *info;
 
-	info = cs_mem_malloc(sizeof(m68k_info));
+	info = cs_mem_calloc(sizeof(m68k_info), 1);
 	if (!info) {
 		return CS_ERR_MEM;
 	}
@@ -29,6 +29,9 @@ cs_err M68K_global_init(cs_struct *ud)
 	ud->insn_id = M68K_get_insn_id;
 	ud->insn_name = M68K_insn_name;
 	ud->group_name = M68K_group_name;
+#ifndef CAPSTONE_DIET
+	ud->reg_access = M68K_reg_access;
+#endif
 
 	return CS_ERR_OK;
 }
diff --git a/arch/RISCV/RISCVModule.c b/arch/RISCV/RISCVModule.c
index cefd4b11a..62b2b3b98 100644
--- a/arch/RISCV/RISCVModule.c
+++ b/arch/RISCV/RISCVModule.c
@@ -33,8 +33,11 @@ cs_err RISCV_global_init(cs_struct * ud)
 
 cs_err RISCV_option(cs_struct * handle, cs_opt_type type, size_t value)
 {
-	if (type == CS_OPT_SYNTAX)
+	if (type == CS_OPT_SYNTAX) {
 		handle->syntax = (int)value;
+	} else if (type == CS_OPT_MODE) {
+		handle->mode = (cs_mode)value;
+	}
 
 	return CS_ERR_OK;
 }
diff --git a/arch/TriCore/TriCoreModule.c b/arch/TriCore/TriCoreModule.c
index c97d36b2e..e28ae3a11 100644
--- a/arch/TriCore/TriCoreModule.c
+++ b/arch/TriCore/TriCoreModule.c
@@ -35,8 +35,11 @@ cs_err TRICORE_global_init(cs_struct *ud)
 
 cs_err TRICORE_option(cs_struct *handle, cs_opt_type type, size_t value)
 {
-	if (type == CS_OPT_SYNTAX)
+	if (type == CS_OPT_SYNTAX) {
 		handle->syntax = (int)value;
+	} else if (type == CS_OPT_MODE) {
+		handle->mode = (cs_mode)value;
+	}
 
 	return CS_ERR_OK;
 }
diff --git a/arch/X86/X86ATTInstPrinter.c b/arch/X86/X86ATTInstPrinter.c
index 3106dc74a..6bff62062 100644
--- a/arch/X86/X86ATTInstPrinter.c
+++ b/arch/X86/X86ATTInstPrinter.c
@@ -288,9 +288,7 @@ static void get_op_access(cs_struct *h, unsigned int id, uint8_t *access, uint64
 
 	// initialize access
 	memset(access, 0, CS_X86_MAXIMUM_OPERAND_SIZE * sizeof(access[0]));
-
 	if (!arr) {
-		access[0] = 0;
 		return;
 	}
 
@@ -302,7 +300,7 @@ static void get_op_access(cs_struct *h, unsigned int id, uint8_t *access, uint64
 
 	// copy in reverse order this access array from Intel syntax -> AT&T syntax
 	count--;
-	for(i = 0; i <= count; i++) {
+	for(i = 0; i <= count && ((count - i) < CS_X86_MAXIMUM_OPERAND_SIZE) && i < CS_X86_MAXIMUM_OPERAND_SIZE; i++) {
 		if (arr[count - i] != CS_AC_IGNORE)
 			access[i] = arr[count - i];
 		else
diff --git a/bindings/Makefile b/bindings/Makefile
deleted file mode 100644
index 85e570500..000000000
--- a/bindings/Makefile
+++ /dev/null
@@ -1,150 +0,0 @@
-TMPDIR = /tmp/capstone_test
-
-DIFF = diff -u -w
-
-TEST_BASIC = $(TMPDIR)/test_basic
-TEST_DETAIL = $(TMPDIR)/test_detail
-TEST_CUSTOMIZED_MNEM = $(TMPDIR)/test_customized_mnem
-TEST_ARM = $(TMPDIR)/test_arm
-TEST_ARM64 = $(TMPDIR)/test_aarch64
-TEST_M68K = $(TMPDIR)/test_m68k
-TEST_MIPS = $(TMPDIR)/test_mips
-TEST_MOS65XX = $(TMPDIR)/test_mos65xx
-TEST_PPC = $(TMPDIR)/test_ppc
-TEST_SPARC = $(TMPDIR)/test_sparc
-TEST_SYSZ = $(TMPDIR)/test_systemz
-TEST_X86 = $(TMPDIR)/test_x86
-TEST_XCORE = $(TMPDIR)/test_xcore
-TEST_WASM = $(TMPDIR)/test_wasm
-TEST_BPF = $(TMPDIR)/test_bpf
-TEST_RISCV = $(TMPDIR)/test_riscv
-TEST_EVM = $(TMPDIR)/test_evm
-TEST_M680X = $(TMPDIR)/test_m680x
-TEST_TRICORE = $(TMPDIR)/test_tricore
-TEST_SH = $(TMPDIR)/test_sh
-TEST_TMS320C64X = $(TMPDIR)/test_tms320c64x
-TEST_ALPHA = $(TMPDIR)/test_alpha
-TEST_HPPA = $(TMPDIR)/test_hppa
-
-PYTHON3 ?= python3
-
-BUILD_TESTS ?= yes
-
-.PHONY: all expected python java ocaml
-
-all:
-	cd python && $(MAKE) gen_const
-	cd java && $(MAKE) gen_const
-	cd ocaml && $(MAKE) gen_const
-
-tests: expected python #java oclma ruby
-
-test_java: expected java
-test_python: expected python
-
-expected:
-	if [ "$(BUILD_TESTS)" = "yes" ]; then cd ../tests && $(MAKE); fi
-	mkdir -p $(TMPDIR)
-	../tests/test_basic > $(TEST_BASIC)_e
-	../tests/test_detail > $(TEST_DETAIL)_e
-	../tests/test_customized_mnem > $(TEST_CUSTOMIZED_MNEM)_e
-	../tests/test_arm > $(TEST_ARM)_e
-	../tests/test_aarch64 > $(TEST_ARM64)_e
-	../tests/test_m68k > $(TEST_M68K)_e
-	../tests/test_mips > $(TEST_MIPS)_e
-	../tests/test_mos65xx > $(TEST_MOS65XX)_e
-	../tests/test_ppc > $(TEST_PPC)_e
-	../tests/test_sparc > $(TEST_SPARC)_e
-	../tests/test_systemz > $(TEST_SYSZ)_e
-	../tests/test_x86 > $(TEST_X86)_e
-	../tests/test_xcore > $(TEST_XCORE)_e
-	../tests/test_wasm > $(TEST_WASM)_e
-	../tests/test_bpf > $(TEST_BPF)_e
-	../tests/test_riscv > $(TEST_RISCV)_e
-	../tests/test_evm > $(TEST_EVM)_e
-	../tests/test_m680x > $(TEST_M680X)_e
-	../tests/test_sh > $(TEST_SH)_e
-	../tests/test_tricore > $(TEST_TRICORE)_e
-	../tests/test_tms320c64x > $(TEST_TMS320C64X)_e
-	../tests/test_alpha > $(TEST_ALPHA)_e
-	../tests/test_hppa > $(TEST_HPPA)_e
-
-python: FORCE
-	cd python && $(MAKE)
-	$(PYTHON3) python/test_basic.py > $(TEST_BASIC)_o
-	$(PYTHON3) python/test_detail.py > $(TEST_DETAIL)_o
-	$(PYTHON3) python/test_customized_mnem.py > $(TEST_CUSTOMIZED_MNEM)_o
-	$(PYTHON3) python/test_arm.py > $(TEST_ARM)_o
-	$(PYTHON3) python/test_aarch64.py > $(TEST_ARM64)_o
-	$(PYTHON3) python/test_m68k.py > $(TEST_M68K)_o
-	$(PYTHON3) python/test_mips.py > $(TEST_MIPS)_o
-	$(PYTHON3) python/test_mos65xx.py > $(TEST_MOS65XX)_o
-	$(PYTHON3) python/test_ppc.py > $(TEST_PPC)_o
-	$(PYTHON3) python/test_sparc.py > $(TEST_SPARC)_o
-	$(PYTHON3) python/test_systemz.py > $(TEST_SYSZ)_o
-	$(PYTHON3) python/test_x86.py > $(TEST_X86)_o
-	$(PYTHON3) python/test_xcore.py > $(TEST_XCORE)_o
-	$(PYTHON3) python/test_wasm.py > $(TEST_WASM)_o
-	$(PYTHON3) python/test_bpf.py > $(TEST_BPF)_o
-	$(PYTHON3) python/test_riscv.py > $(TEST_RISCV)_o
-	$(PYTHON3) python/test_evm.py > $(TEST_EVM)_o
-	$(PYTHON3) python/test_m680x.py > $(TEST_M680X)_o
-	$(PYTHON3) python/test_sh.py > $(TEST_SH)_o
-	$(PYTHON3) python/test_tricore.py > $(TEST_TRICORE)_o
-	$(PYTHON3) python/test_tms320c64x.py > $(TEST_TMS320C64X)_o
-	$(PYTHON3) python/test_alpha.py > $(TEST_ALPHA)_o
-	$(PYTHON3) python/test_hppa.py > $(TEST_HPPA)_o
-	$(MAKE) test_diff
-
-java: FORCE
-	cd java && $(MAKE)
-	cd java && ./run.sh > $(TEST_BASIC)_o
-	cd java && ./run.sh arm > $(TEST_ARM)_o
-	cd java && ./run.sh arm64 > $(TEST_ARM64)_o
-	cd java && ./run.sh mips > $(TEST_MIPS)_o
-	cd java && ./run.sh ppc > $(TEST_PPC)_o
-	cd java && ./run.sh sparc > $(TEST_SPARC)_o
-	cd java && ./run.sh systemz > $(TEST_SYSZ)_o
-	cd java && ./run.sh x86 > $(TEST_X86)_o
-	cd java && ./run.sh xcore > $(TEST_XCORE)_o
-	$(MAKE) test_diff
-
-ocaml: FORCE
-
-test_diff: FORCE
-	$(DIFF) $(TEST_BASIC)_e $(TEST_BASIC)_o
-	$(DIFF) $(TEST_DETAIL)_e $(TEST_DETAIL)_o
-	$(DIFF) $(TEST_CUSTOMIZED_MNEM)_e $(TEST_CUSTOMIZED_MNEM)_o
-	$(DIFF) $(TEST_ARM)_e $(TEST_ARM)_o
-	$(DIFF) $(TEST_ARM64)_e $(TEST_ARM64)_o
-	$(DIFF) $(TEST_M68K)_e $(TEST_M68K)_o
-	$(DIFF) $(TEST_MIPS)_e $(TEST_MIPS)_o
-	$(DIFF) $(TEST_MOS65XX)_e $(TEST_MOS65XX)_o
-	$(DIFF) $(TEST_PPC)_e $(TEST_PPC)_o
-	$(DIFF) $(TEST_SPARC)_e $(TEST_SPARC)_o
-	$(DIFF) $(TEST_SYSZ)_e $(TEST_SYSZ)_o
-	$(DIFF) $(TEST_X86)_e $(TEST_X86)_o
-	$(DIFF) $(TEST_XCORE)_e $(TEST_XCORE)_o
-	$(DIFF) $(TEST_WASM)_e $(TEST_WASM)_o
-	$(DIFF) $(TEST_BPF)_e $(TEST_BPF)_o
-	$(DIFF) $(TEST_RISCV)_e $(TEST_RISCV)_o
-	$(DIFF) $(TEST_EVM)_e $(TEST_EVM)_o
-	$(DIFF) $(TEST_M680X)_e $(TEST_M680X)_o
-	$(DIFF) $(TEST_SH)_e $(TEST_SH)_o
-	$(DIFF) $(TEST_TRICORE)_e $(TEST_TRICORE)_o
-	$(DIFF) $(TEST_TMS320C64X)_e $(TEST_TMS320C64X)_o
-	$(DIFF) $(TEST_ALPHA)_e $(TEST_ALPHA)_o
-	$(DIFF) $(TEST_HPPA)_e $(TEST_HPPA)_o
-
-clean:
-	rm -rf $(TMPDIR)
-	cd java && $(MAKE) clean
-	cd python && $(MAKE) clean
-	cd ocaml && $(MAKE) clean
-
-check:
-	make -C ocaml check
-	make -C python check
-	make -C java check
-
-FORCE:
diff --git a/bindings/const_generator.py b/bindings/const_generator.py
index 1f4ec14f6..e164e62a9 100644
--- a/bindings/const_generator.py
+++ b/bindings/const_generator.py
@@ -1,11 +1,12 @@
 # Capstone Disassembler Engine
 # By Dang Hoang Vu, 2013
 from __future__ import print_function
-import sys, re
+import sys
+import re
 
 INCL_DIR = '../include/capstone/'
 
-include = [ 'arm.h', 'aarch64.h', 'm68k.h', 'mips.h', 'x86.h', 'ppc.h', 'sparc.h', 'systemz.h', 'xcore.h', 'tms320c64x.h', 'm680x.h', 'evm.h', 'mos65xx.h', 'wasm.h', 'bpf.h' ,'riscv.h', 'sh.h', 'tricore.h', 'alpha.h', 'hppa.h' ]
+include = [ 'arm.h', 'aarch64.h', 'm68k.h', 'mips.h', 'x86.h', 'ppc.h', 'sparc.h', 'systemz.h', 'xcore.h', 'tms320c64x.h', 'm680x.h', 'evm.h', 'mos65xx.h', 'wasm.h', 'bpf.h' ,'riscv.h', 'sh.h', 'tricore.h', 'alpha.h', 'hppa.h', 'loongarch.h' ]
 
 template = {
     'java': {
@@ -56,6 +57,7 @@ template = {
             'tricore.h': ['TRICORE', 'TriCore'],
             'alpha.h': ['ALPHA', 'Alpha'],
             'hppa.h': 'hppa',
+            'loongarch.h': 'loongarch',
             'comment_open': '#',
             'comment_close': '',
         },
@@ -80,81 +82,6 @@ template = {
             'comment_open': '(*',
             'comment_close': ' *)',
         },
-    # 'swift': {
-    #         'header': "// For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT (%s)\n\n",
-    #         'footer': "",
-    #         'enum_doc': '/// %s\n',
-    #         'enum_header': 'public enum %s: %s {\n',
-    #         'enum_default_type': 'UInt32',
-    #         'enum_types': {
-    #             'UInt16': r'^\w+Reg$',
-    #             'UInt8': r'^\w+Grp$'
-    #         },
-    #         'option_set_header': 'public struct %s: OptionSet {\n    public typealias RawValue = %s\n    public let rawValue: RawValue\n    public init(rawValue: RawValue) { self.rawValue = rawValue }\n',
-    #         'option_sets': {
-    #             'X86Eflags': 'UInt64',
-    #             'X86FpuFlags': 'UInt64',
-    #             'SparcHint': 'UInt32',
-    #             'M680xIdx': 'UInt8',
-    #             'M680xOpFlags': 'UInt8',
-    #         },
-    #         'rename': {
-    #             r'^M680X_(\w+_OP_IN_MNEM)$': r'M680X_OP_FLAGS_\1',
-    #         },
-    #         'option_format': '    public static let {option} = {type}(rawValue: {value})\n',
-    #         'enum_extra_options': {
-    #             # swift enum != OptionSet, so options must be specified
-    #             'ArmSysreg': {
-    #                 'spsrCx': 'spsrC + spsrX',
-    #                 'spsrCs': 'spsrC + spsrS',
-    #                 'spsrXs': 'spsrX + spsrS',
-    #                 'spsrCxs': 'spsrC + spsrX + spsrS',
-    #                 'spsrCf': 'spsrC + spsrF',
-    #                 'spsrXf': 'spsrX + spsrF',
-    #                 'spsrCxf': 'spsrC + spsrX + spsrF',
-    #                 'spsrSf': 'spsrS + spsrF',
-    #                 'spsrCsf': 'spsrC + spsrS + spsrF',
-    #                 'spsrXsf': 'spsrX + spsrS + spsrF',
-    #                 'spsrCxsf': 'spsrC + spsrX + spsrS + spsrF',
-    #                 'cpsrCx': 'cpsrC + cpsrX',
-    #                 'cpsrCs': 'cpsrC + cpsrS',
-    #                 'cpsrXs': 'cpsrX + cpsrS',
-    #                 'cpsrCxs': 'cpsrC + cpsrX + cpsrS',
-    #                 'cpsrCf': 'cpsrC + cpsrF',
-    #                 'cpsrXf': 'cpsrX + cpsrF',
-    #                 'cpsrCxf': 'cpsrC + cpsrX + cpsrF',
-    #                 'cpsrSf': 'cpsrS + cpsrF',
-    #                 'cpsrCsf': 'cpsrC + cpsrS + cpsrF',
-    #                 'cpsrXsf': 'cpsrX + cpsrS + cpsrF',
-    #                 'cpsrCxsf': 'cpsrC + cpsrX + cpsrS + cpsrF',
-    #             }
-    #         },
-    #         'enum_footer': '}\n\n',
-    #         'doc_line_format': '    /// %s\n',
-    #         'line_format': '    case %s = %s\n',
-    #         'dup_line_format': '    public static let %s = %s\n',
-    #         'out_file': './swift/Sources/Capstone/%sEnums.swift',
-    #         'reserved_words': [
-    #             'break', 'class', 'for', 'false', 'in', 'init', 'return', 'true'
-    #         ],
-    #         'reserved_word_format': '`%s`',
-    #         # prefixes for constant filenames of all archs - case sensitive
-    #         'arm.h': 'Arm',
-    #         'arm64.h': 'Arm64',
-    #         'm68k.h': 'M68k',
-    #         'mips.h': 'Mips',
-    #         'x86.h': 'X86',
-    #         'ppc.h': 'Ppc',
-    #         'sparc.h': 'Sparc',
-    #         'systemz.h': 'Sysz',
-    #         'xcore.h': 'Xcore',
-    #         'tms320c64x.h': 'TMS320C64x',
-    #         'm680x.h': 'M680x',
-    #         'evm.h': 'Evm',
-    #         'mos65xx.h': 'Mos65xx',
-    #         'comment_open': '\t//',
-    #         'comment_close': '',
-    #     },
 }
 
 excluded_prefixes = {
@@ -237,6 +164,11 @@ def gen(lang):
             elif line.startswith('}') or line.startswith('#'):
                 doc_lines = []
                 pass
+            elif re.search(r"^(\s*typedef\s+)?enum", line):
+                # First new enum value should be 0.
+                # Because `rhs` is incremented later, it must be set to -1 here.
+                # Everything about this code is so broken -.-
+                rhs = "-1"
 
             if line == '' or line.startswith('//'):
                 continue
@@ -251,7 +183,7 @@ def gen(lang):
                 xline.insert(1, '=')            # insert an = so the expression below can parse it
                 line = ' '.join(xline)
 
-            def is_with_prefix(x):
+            def has_special_arch_prefix(x):
                 if target in excluded_prefixes and any(x.startswith(excl_pre) for excl_pre in excluded_prefixes[target]):
                     return False
                 if prefixs:
@@ -259,7 +191,7 @@ def gen(lang):
                 else:
                     return x.startswith(prefix.upper())
 
-            if not is_with_prefix(line):
+            if not has_special_arch_prefix(line):
                 continue
 
             tmp = line.strip().split(',')
@@ -271,7 +203,7 @@ def gen(lang):
                 t = re.sub(r'\((\d+)ULL << (\d+)\)', r'\1 << \2', t)    # (1ULL<<1) to 1 << 1
                 f = re.split('\s+', t)
 
-                if not is_with_prefix(f[0]):
+                if not has_special_arch_prefix(f[0]):
                     continue
 
                 if len(f) > 1 and f[1] not in ('//', '///<', '='):
diff --git a/bindings/python/.gitignore b/bindings/python/.gitignore
index 61178e6a1..5ed7ca830 100644
--- a/bindings/python/.gitignore
+++ b/bindings/python/.gitignore
@@ -1,6 +1,5 @@
 MANIFEST
 dist/
-src/
 capstone/lib
 capstone/include
 pyx/lib
diff --git a/bindings/python/BUILDING.txt b/bindings/python/BUILDING.md
similarity index 58%
rename from bindings/python/BUILDING.txt
rename to bindings/python/BUILDING.md
index 78fcb0ded..9b6a1d680 100644
--- a/bindings/python/BUILDING.txt
+++ b/bindings/python/BUILDING.md
@@ -4,17 +4,12 @@
 
 1. To install Capstone and the Python bindings on *nix, run the command below:
 
-		$ sudo make install
-
-   To control the install destination, set the DESTDIR environment variable.
+```
+pip install bindings/python/
+```
 
 2. The tests directory contains some test code to show how to use the Capstone API.
 
-- test_basic.py
-  This code shows the most simple form of API where we only want to get basic
-  information out of disassembled instruction, such as address, mnemonic and
-  operand string.
-
 - test_lite.py
   Similarly to test_basic.py, but this code shows how to use disasm_lite(), a lighter
   method to disassemble binary. Unlike disasm() API (used by test_basic.py), which returns
@@ -23,12 +18,3 @@
   The main reason for using this API is better performance: disasm_lite() is at least
   20% faster than disasm(). Memory usage is also less. So if you just need basic
   information out of disassembler, use disasm_lite() instead of disasm().
-
-- test_detail.py:
-  This code shows how to access to architecture-neutral information in disassembled
-  instructions, such as implicit registers read/written, or groups of instructions
-  that this instruction belong to.
-
-- test_<arch>.py
-  These code show how to access architecture-specific information for each
-  architecture.
diff --git a/bindings/python/capstone/__init__.py b/bindings/python/capstone/__init__.py
index 75ad68083..f70c6e96e 100755
--- a/bindings/python/capstone/__init__.py
+++ b/bindings/python/capstone/__init__.py
@@ -40,6 +40,7 @@ __all__ = [
     'CS_ARCH_TRICORE',
     'CS_ARCH_ALPHA',
     'CS_ARCH_HPPA',
+    'CS_ARCH_LOONGARCH',
     'CS_ARCH_ALL',
 
     'CS_MODE_LITTLE_ENDIAN',
@@ -107,6 +108,8 @@ __all__ = [
     'CS_MODE_HPPA_11',
     'CS_MODE_HPPA_20',
     'CS_MODE_HPPA_20W',
+    'CS_MODE_LOONGARCH32',
+    'CS_MODE_LOONGARCH64',
 
     'CS_OPT_SYNTAX',
     'CS_OPT_SYNTAX_DEFAULT',
@@ -225,6 +228,7 @@ CS_ARCH_SH = 16
 CS_ARCH_TRICORE = 17
 CS_ARCH_ALPHA = 18
 CS_ARCH_HPPA = 19
+CS_ARCH_LOONGARCH = 20
 CS_ARCH_MAX = 20
 CS_ARCH_ALL = 0xFFFF
 
@@ -294,6 +298,8 @@ CS_MODE_TRICORE_162 = 1 << 7 # Tricore 1.6.2
 CS_MODE_HPPA_11 = 1 << 1 # HPPA 1.1
 CS_MODE_HPPA_20 = 1 << 2 # HPPA 2.0
 CS_MODE_HPPA_20W = CS_MODE_HPPA_20 | (1 << 3) # HPPA 2.0 wide
+CS_MODE_LOONGARCH32 = 1 << 0
+CS_MODE_LOONGARCH64 = 1 << 1
 
 # Capstone option type
 CS_OPT_INVALID = 0   # No option specified
@@ -347,16 +353,18 @@ CS_GRP_BRANCH_RELATIVE = 7 # all relative branching instructions
 CS_AC_INVALID  = 0        # Invalid/uninitialized access type.
 CS_AC_READ     = (1 << 0) # Operand that is read from.
 CS_AC_WRITE    = (1 << 1) # Operand that is written to.
-CS_AC_READ_WRITE = (2)
+CS_AC_READ_WRITE = CS_AC_READ | CS_AC_WRITE
 
 # Capstone syntax value
-CS_OPT_SYNTAX_DEFAULT = 1 << 1  # Default assembly syntax of all platforms (CS_OPT_SYNTAX)
-CS_OPT_SYNTAX_INTEL = 1 << 2  # Intel X86 asm syntax - default syntax on X86 (CS_OPT_SYNTAX, CS_ARCH_X86)
-CS_OPT_SYNTAX_ATT = 1 << 3  # ATT asm syntax (CS_OPT_SYNTAX, CS_ARCH_X86)
-CS_OPT_SYNTAX_NOREGNAME = 1 << 4  # Asm syntax prints register name with only number - (CS_OPT_SYNTAX, CS_ARCH_PPC, CS_ARCH_ARM)
-CS_OPT_SYNTAX_MASM = 1 << 5  # MASM syntax (CS_OPT_SYNTAX, CS_ARCH_X86)
-CS_OPT_SYNTAX_MOTOROLA = 1 << 6  # MOS65XX use $ as hex prefix
-CS_OPT_SYNTAX_CS_REG_ALIAS = 1 << 7  # Prints common register alias which are not defined in LLVM (ARM: r9 = sb etc.)
+CS_OPT_SYNTAX_DEFAULT = (1 << 1)  # Default assembly syntax of all platforms (CS_OPT_SYNTAX)
+CS_OPT_SYNTAX_INTEL = (1 << 2)  # Intel X86 asm syntax - default syntax on X86 (CS_OPT_SYNTAX, CS_ARCH_X86)
+CS_OPT_SYNTAX_ATT = (1 << 3)  # ATT asm syntax (CS_OPT_SYNTAX, CS_ARCH_X86)
+CS_OPT_SYNTAX_NOREGNAME = (1 << 4)  # Asm syntax prints register name with only number - (CS_OPT_SYNTAX, CS_ARCH_PPC, CS_ARCH_ARM)
+CS_OPT_SYNTAX_MASM = (1 << 5)  # MASM syntax (CS_OPT_SYNTAX, CS_ARCH_X86)
+CS_OPT_SYNTAX_MOTOROLA = (1 << 6)  # MOS65XX use $ as hex prefix
+CS_OPT_SYNTAX_CS_REG_ALIAS = (1 << 7)  # Prints common register alias which are not defined in LLVM (ARM: r9 = sb etc.)
+CS_OPT_SYNTAX_PERCENT = (1 << 8)  # Prints the % in front of PPC registers.
+CS_OPT_DETAIL_REAL = (1 << 1)  # If enabled, always sets the real instruction detail.Even if the instruction is an alias.
 
 # Capstone error type
 CS_ERR_OK = 0      # No error: everything was fine
@@ -460,7 +468,7 @@ def copy_ctypes_list(src):
     return [copy_ctypes(n) for n in src]
 
 # Weird import placement because these modules are needed by the below code but need the above functions
-from . import arm, aarch64, m68k, mips, ppc, sparc, systemz, x86, xcore, tms320c64x, m680x, evm, mos65xx, wasm, bpf, riscv, sh, tricore, alpha, hppa
+from . import arm, aarch64, m68k, mips, ppc, sparc, systemz, x86, xcore, tms320c64x, m680x, evm, mos65xx, wasm, bpf, riscv, sh, tricore, alpha, hppa, loongarch
 
 class _cs_arch(ctypes.Union):
     _fields_ = (
@@ -484,6 +492,7 @@ class _cs_arch(ctypes.Union):
         ('tricore', tricore.CsTriCore),
         ('alpha', alpha.CsAlpha),
         ('hppa', hppa.CsHPPA),
+        ('loongarch', loongarch.CsLoongArch),
     )
 
 class _cs_detail(ctypes.Structure):
@@ -695,6 +704,21 @@ class CsInsn(object):
     def size(self):
         return self._raw.size
 
+    # return instruction's is_alias flag
+    @property
+    def is_alias(self):
+        return self._raw.is_alias
+
+    # return instruction's alias_id
+    @property
+    def alias_id(self):
+        return self._raw.alias_id
+
+    # return instruction's flag if it uses alias details
+    @property
+    def uses_alias_details(self):
+        return self._raw.usesAliasDetails
+
     # return instruction's machine bytes (which should have @size bytes).
     @property
     def bytes(self):
@@ -802,7 +826,7 @@ class CsInsn(object):
         elif arch == CS_ARCH_MIPS:
                 self.operands = mips.get_arch_info(self._raw.detail.contents.arch.mips)
         elif arch == CS_ARCH_PPC:
-            (self.bc, self.update_cr0, self.operands) = \
+            (self.bc, self.update_cr0, self.format, self.operands) = \
                 ppc.get_arch_info(self._raw.detail.contents.arch.ppc)
         elif arch == CS_ARCH_SPARC:
             (self.cc, self.hint, self.operands) = sparc.get_arch_info(self._raw.detail.contents.arch.sparc)
@@ -832,6 +856,8 @@ class CsInsn(object):
             (self.operands) = alpha.get_arch_info(self._raw.detail.contents.arch.alpha)
         elif arch == CS_ARCH_HPPA:
             (self.operands) = hppa.get_arch_info(self._raw.detail.contents.arch.hppa)
+        elif arch == CS_ARCH_LOONGARCH:
+            (self.format, self.operands) = loongarch.get_arch_info(self._raw.detail.contents.arch.loongarch)
 
 
     def __getattr__(self, name):
@@ -840,14 +866,14 @@ class CsInsn(object):
 
         attr = object.__getattribute__
         if not attr(self, '_cs')._detail:
-            raise AttributeError(name)
+            raise AttributeError(f"'CsInsn' has no attribute '{name}'")
         _dict = attr(self, '__dict__')
         if 'operands' not in _dict:
             self.__gen_detail()
         if name not in _dict:
             if self._raw.id == 0:
                 raise CsError(CS_ERR_SKIPDATA)
-            raise AttributeError(name)
+            raise AttributeError(f"'CsInsn' has no attribute '{name}'")
         return _dict[name]
 
     # get the last error code
@@ -1021,9 +1047,16 @@ class Cs(object):
             except: # _cs might be pulled from under our feet
                 pass
 
-
-    # def option(self, opt_type, opt_value):
-    #    return _cs.cs_option(self.csh, opt_type, opt_value)
+    def option(self, opt_type, opt_value):
+        status = _cs.cs_option(self.csh, opt_type, opt_value)
+        if status != CS_ERR_OK:
+            raise CsError(status)
+        if opt_type == CS_OPT_DETAIL:
+            self._detail = opt_value == CS_OPT_ON
+        elif opt_type == CS_OPT_SKIPDATA:
+            self._skipdata = opt_value == CS_OPT_ON
+        elif opt_type == CS_OPT_UNSIGNED:
+            self._imm_unsigned = opt_value == CS_OPT_ON
 
 
     # is this a diet engine?
@@ -1321,7 +1354,7 @@ def debug():
         "m680x": CS_ARCH_M680X, 'evm': CS_ARCH_EVM, 'mos65xx': CS_ARCH_MOS65XX,
         'bpf': CS_ARCH_BPF, 'riscv': CS_ARCH_RISCV, 'tricore': CS_ARCH_TRICORE,
         'wasm': CS_ARCH_WASM, 'sh': CS_ARCH_SH, 'alpha': CS_ARCH_ALPHA,
-        'hppa': CS_ARCH_HPPA
+        'hppa': CS_ARCH_HPPA, 'loongarch': CS_ARCH_LOONGARCH
     }
 
     all_archs = ""
diff --git a/bindings/python/capstone/aarch64.py b/bindings/python/capstone/aarch64.py
index b5d4a87bd..bcceb8a95 100644
--- a/bindings/python/capstone/aarch64.py
+++ b/bindings/python/capstone/aarch64.py
@@ -14,7 +14,7 @@ class AArch64OpMem(ctypes.Structure):
 
 class AArch64ImmRange(ctypes.Structure):
     _fields_ = (
-        ('imm', ctypes.c_int8),
+        ('first', ctypes.c_int8),
         ('offset', ctypes.c_int8),
     )
 
diff --git a/bindings/python/capstone/aarch64_const.py b/bindings/python/capstone/aarch64_const.py
index 8ce35150e..4831adb6d 100644
--- a/bindings/python/capstone/aarch64_const.py
+++ b/bindings/python/capstone/aarch64_const.py
@@ -1615,7 +1615,7 @@ AARCH64_SYSREG_ZCR_EL2 = 0xe090
 AARCH64_SYSREG_ZCR_EL3 = 0xf090
 AARCH64_SYSREG_ENDING = UINT16_MAX
 AARCH64_TSB_CSYNC = 0x0
-AArch64_TSB_ENDING = 1
+AARCH64_TSB_ENDING = 1
 AARCH64_OP_INVALID = CS_OP_INVALID
 AARCH64_OP_REG = CS_OP_REG
 AARCH64_OP_IMM = CS_OP_IMM
@@ -2358,1787 +2358,1790 @@ AARCH64_REG_IP0 = AARCH64_REG_X16
 AARCH64_REG_IP1 = AARCH64_REG_X17
 AARCH64_REG_X29 = AARCH64_REG_FP
 AARCH64_REG_X30 = AARCH64_REG_LR
-AARCH64_SME_MATRIX_TILE = 701
-AARCH64_SME_MATRIX_TILE_LIST = 702
-AARCH64_SME_MATRIX_SLICE_REG = 703
-AARCH64_SME_MATRIX_SLICE_OFF = 704
-AARCH64_SME_MATRIX_SLICE_OFF_RANGE = 705
-AARCH64_SME_OP_INVALID = 706
-AARCH64_SME_OP_TILE = 707
-AARCH64_SME_OP_TILE_VEC = 708
-AARCH64_INS_INVALID = 709
-AARCH64_INS_ABS = 710
-AARCH64_INS_ADCLB = 711
-AARCH64_INS_ADCLT = 712
-AARCH64_INS_ADCS = 713
-AARCH64_INS_ADC = 714
-AARCH64_INS_ADDG = 715
-AARCH64_INS_ADDHA = 716
-AARCH64_INS_ADDHNB = 717
-AARCH64_INS_ADDHNT = 718
-AARCH64_INS_ADDHN = 719
-AARCH64_INS_ADDHN2 = 720
-AARCH64_INS_ADDPL = 721
-AARCH64_INS_ADDPT = 722
-AARCH64_INS_ADDP = 723
-AARCH64_INS_ADDQV = 724
-AARCH64_INS_ADDSPL = 725
-AARCH64_INS_ADDSVL = 726
-AARCH64_INS_ADDS = 727
-AARCH64_INS_ADDVA = 728
-AARCH64_INS_ADDVL = 729
-AARCH64_INS_ADDV = 730
-AARCH64_INS_ADD = 731
-AARCH64_INS_ADR = 732
-AARCH64_INS_ADRP = 733
-AARCH64_INS_AESD = 734
-AARCH64_INS_AESE = 735
-AARCH64_INS_AESIMC = 736
-AARCH64_INS_AESMC = 737
-AARCH64_INS_ANDQV = 738
-AARCH64_INS_ANDS = 739
-AARCH64_INS_ANDV = 740
-AARCH64_INS_AND = 741
-AARCH64_INS_ASRD = 742
-AARCH64_INS_ASRR = 743
-AARCH64_INS_ASR = 744
-AARCH64_INS_AUTDA = 745
-AARCH64_INS_AUTDB = 746
-AARCH64_INS_AUTDZA = 747
-AARCH64_INS_AUTDZB = 748
-AARCH64_INS_AUTIA = 749
-AARCH64_INS_HINT = 750
-AARCH64_INS_AUTIA171615 = 751
-AARCH64_INS_AUTIASPPC = 752
-AARCH64_INS_AUTIB = 753
-AARCH64_INS_AUTIB171615 = 754
-AARCH64_INS_AUTIBSPPC = 755
-AARCH64_INS_AUTIZA = 756
-AARCH64_INS_AUTIZB = 757
-AARCH64_INS_AXFLAG = 758
-AARCH64_INS_B = 759
-AARCH64_INS_BCAX = 760
-AARCH64_INS_BC = 761
-AARCH64_INS_BDEP = 762
-AARCH64_INS_BEXT = 763
-AARCH64_INS_BFDOT = 764
-AARCH64_INS_BF1CVTL2 = 765
-AARCH64_INS_BF1CVTLT = 766
-AARCH64_INS_BF1CVTL = 767
-AARCH64_INS_BF1CVT = 768
-AARCH64_INS_BF2CVTL2 = 769
-AARCH64_INS_BF2CVTLT = 770
-AARCH64_INS_BF2CVTL = 771
-AARCH64_INS_BF2CVT = 772
-AARCH64_INS_BFADD = 773
-AARCH64_INS_BFCLAMP = 774
-AARCH64_INS_BFCVT = 775
-AARCH64_INS_BFCVTN = 776
-AARCH64_INS_BFCVTN2 = 777
-AARCH64_INS_BFCVTNT = 778
-AARCH64_INS_BFMAXNM = 779
-AARCH64_INS_BFMAX = 780
-AARCH64_INS_BFMINNM = 781
-AARCH64_INS_BFMIN = 782
-AARCH64_INS_BFMLALB = 783
-AARCH64_INS_BFMLALT = 784
-AARCH64_INS_BFMLAL = 785
-AARCH64_INS_BFMLA = 786
-AARCH64_INS_BFMLSLB = 787
-AARCH64_INS_BFMLSLT = 788
-AARCH64_INS_BFMLSL = 789
-AARCH64_INS_BFMLS = 790
-AARCH64_INS_BFMMLA = 791
-AARCH64_INS_BFMOPA = 792
-AARCH64_INS_BFMOPS = 793
-AARCH64_INS_BFMUL = 794
-AARCH64_INS_BFM = 795
-AARCH64_INS_BFSUB = 796
-AARCH64_INS_BFVDOT = 797
-AARCH64_INS_BGRP = 798
-AARCH64_INS_BICS = 799
-AARCH64_INS_BIC = 800
-AARCH64_INS_BIF = 801
-AARCH64_INS_BIT = 802
-AARCH64_INS_BL = 803
-AARCH64_INS_BLR = 804
-AARCH64_INS_BLRAA = 805
-AARCH64_INS_BLRAAZ = 806
-AARCH64_INS_BLRAB = 807
-AARCH64_INS_BLRABZ = 808
-AARCH64_INS_BMOPA = 809
-AARCH64_INS_BMOPS = 810
-AARCH64_INS_BR = 811
-AARCH64_INS_BRAA = 812
-AARCH64_INS_BRAAZ = 813
-AARCH64_INS_BRAB = 814
-AARCH64_INS_BRABZ = 815
-AARCH64_INS_BRB = 816
-AARCH64_INS_BRK = 817
-AARCH64_INS_BRKAS = 818
-AARCH64_INS_BRKA = 819
-AARCH64_INS_BRKBS = 820
-AARCH64_INS_BRKB = 821
-AARCH64_INS_BRKNS = 822
-AARCH64_INS_BRKN = 823
-AARCH64_INS_BRKPAS = 824
-AARCH64_INS_BRKPA = 825
-AARCH64_INS_BRKPBS = 826
-AARCH64_INS_BRKPB = 827
-AARCH64_INS_BSL1N = 828
-AARCH64_INS_BSL2N = 829
-AARCH64_INS_BSL = 830
-AARCH64_INS_CADD = 831
-AARCH64_INS_CASAB = 832
-AARCH64_INS_CASAH = 833
-AARCH64_INS_CASALB = 834
-AARCH64_INS_CASALH = 835
-AARCH64_INS_CASAL = 836
-AARCH64_INS_CASA = 837
-AARCH64_INS_CASB = 838
-AARCH64_INS_CASH = 839
-AARCH64_INS_CASLB = 840
-AARCH64_INS_CASLH = 841
-AARCH64_INS_CASL = 842
-AARCH64_INS_CASPAL = 843
-AARCH64_INS_CASPA = 844
-AARCH64_INS_CASPL = 845
-AARCH64_INS_CASP = 846
-AARCH64_INS_CAS = 847
-AARCH64_INS_CBNZ = 848
-AARCH64_INS_CBZ = 849
-AARCH64_INS_CCMN = 850
-AARCH64_INS_CCMP = 851
-AARCH64_INS_CDOT = 852
-AARCH64_INS_CFINV = 853
-AARCH64_INS_CLASTA = 854
-AARCH64_INS_CLASTB = 855
-AARCH64_INS_CLREX = 856
-AARCH64_INS_CLS = 857
-AARCH64_INS_CLZ = 858
-AARCH64_INS_CMEQ = 859
-AARCH64_INS_CMGE = 860
-AARCH64_INS_CMGT = 861
-AARCH64_INS_CMHI = 862
-AARCH64_INS_CMHS = 863
-AARCH64_INS_CMLA = 864
-AARCH64_INS_CMLE = 865
-AARCH64_INS_CMLT = 866
-AARCH64_INS_CMPEQ = 867
-AARCH64_INS_CMPGE = 868
-AARCH64_INS_CMPGT = 869
-AARCH64_INS_CMPHI = 870
-AARCH64_INS_CMPHS = 871
-AARCH64_INS_CMPLE = 872
-AARCH64_INS_CMPLO = 873
-AARCH64_INS_CMPLS = 874
-AARCH64_INS_CMPLT = 875
-AARCH64_INS_CMPNE = 876
-AARCH64_INS_CMTST = 877
-AARCH64_INS_CNOT = 878
-AARCH64_INS_CNTB = 879
-AARCH64_INS_CNTD = 880
-AARCH64_INS_CNTH = 881
-AARCH64_INS_CNTP = 882
-AARCH64_INS_CNTW = 883
-AARCH64_INS_CNT = 884
-AARCH64_INS_COMPACT = 885
-AARCH64_INS_CPYE = 886
-AARCH64_INS_CPYEN = 887
-AARCH64_INS_CPYERN = 888
-AARCH64_INS_CPYERT = 889
-AARCH64_INS_CPYERTN = 890
-AARCH64_INS_CPYERTRN = 891
-AARCH64_INS_CPYERTWN = 892
-AARCH64_INS_CPYET = 893
-AARCH64_INS_CPYETN = 894
-AARCH64_INS_CPYETRN = 895
-AARCH64_INS_CPYETWN = 896
-AARCH64_INS_CPYEWN = 897
-AARCH64_INS_CPYEWT = 898
-AARCH64_INS_CPYEWTN = 899
-AARCH64_INS_CPYEWTRN = 900
-AARCH64_INS_CPYEWTWN = 901
-AARCH64_INS_CPYFE = 902
-AARCH64_INS_CPYFEN = 903
-AARCH64_INS_CPYFERN = 904
-AARCH64_INS_CPYFERT = 905
-AARCH64_INS_CPYFERTN = 906
-AARCH64_INS_CPYFERTRN = 907
-AARCH64_INS_CPYFERTWN = 908
-AARCH64_INS_CPYFET = 909
-AARCH64_INS_CPYFETN = 910
-AARCH64_INS_CPYFETRN = 911
-AARCH64_INS_CPYFETWN = 912
-AARCH64_INS_CPYFEWN = 913
-AARCH64_INS_CPYFEWT = 914
-AARCH64_INS_CPYFEWTN = 915
-AARCH64_INS_CPYFEWTRN = 916
-AARCH64_INS_CPYFEWTWN = 917
-AARCH64_INS_CPYFM = 918
-AARCH64_INS_CPYFMN = 919
-AARCH64_INS_CPYFMRN = 920
-AARCH64_INS_CPYFMRT = 921
-AARCH64_INS_CPYFMRTN = 922
-AARCH64_INS_CPYFMRTRN = 923
-AARCH64_INS_CPYFMRTWN = 924
-AARCH64_INS_CPYFMT = 925
-AARCH64_INS_CPYFMTN = 926
-AARCH64_INS_CPYFMTRN = 927
-AARCH64_INS_CPYFMTWN = 928
-AARCH64_INS_CPYFMWN = 929
-AARCH64_INS_CPYFMWT = 930
-AARCH64_INS_CPYFMWTN = 931
-AARCH64_INS_CPYFMWTRN = 932
-AARCH64_INS_CPYFMWTWN = 933
-AARCH64_INS_CPYFP = 934
-AARCH64_INS_CPYFPN = 935
-AARCH64_INS_CPYFPRN = 936
-AARCH64_INS_CPYFPRT = 937
-AARCH64_INS_CPYFPRTN = 938
-AARCH64_INS_CPYFPRTRN = 939
-AARCH64_INS_CPYFPRTWN = 940
-AARCH64_INS_CPYFPT = 941
-AARCH64_INS_CPYFPTN = 942
-AARCH64_INS_CPYFPTRN = 943
-AARCH64_INS_CPYFPTWN = 944
-AARCH64_INS_CPYFPWN = 945
-AARCH64_INS_CPYFPWT = 946
-AARCH64_INS_CPYFPWTN = 947
-AARCH64_INS_CPYFPWTRN = 948
-AARCH64_INS_CPYFPWTWN = 949
-AARCH64_INS_CPYM = 950
-AARCH64_INS_CPYMN = 951
-AARCH64_INS_CPYMRN = 952
-AARCH64_INS_CPYMRT = 953
-AARCH64_INS_CPYMRTN = 954
-AARCH64_INS_CPYMRTRN = 955
-AARCH64_INS_CPYMRTWN = 956
-AARCH64_INS_CPYMT = 957
-AARCH64_INS_CPYMTN = 958
-AARCH64_INS_CPYMTRN = 959
-AARCH64_INS_CPYMTWN = 960
-AARCH64_INS_CPYMWN = 961
-AARCH64_INS_CPYMWT = 962
-AARCH64_INS_CPYMWTN = 963
-AARCH64_INS_CPYMWTRN = 964
-AARCH64_INS_CPYMWTWN = 965
-AARCH64_INS_CPYP = 966
-AARCH64_INS_CPYPN = 967
-AARCH64_INS_CPYPRN = 968
-AARCH64_INS_CPYPRT = 969
-AARCH64_INS_CPYPRTN = 970
-AARCH64_INS_CPYPRTRN = 971
-AARCH64_INS_CPYPRTWN = 972
-AARCH64_INS_CPYPT = 973
-AARCH64_INS_CPYPTN = 974
-AARCH64_INS_CPYPTRN = 975
-AARCH64_INS_CPYPTWN = 976
-AARCH64_INS_CPYPWN = 977
-AARCH64_INS_CPYPWT = 978
-AARCH64_INS_CPYPWTN = 979
-AARCH64_INS_CPYPWTRN = 980
-AARCH64_INS_CPYPWTWN = 981
-AARCH64_INS_CPY = 982
-AARCH64_INS_CRC32B = 983
-AARCH64_INS_CRC32CB = 984
-AARCH64_INS_CRC32CH = 985
-AARCH64_INS_CRC32CW = 986
-AARCH64_INS_CRC32CX = 987
-AARCH64_INS_CRC32H = 988
-AARCH64_INS_CRC32W = 989
-AARCH64_INS_CRC32X = 990
-AARCH64_INS_CSEL = 991
-AARCH64_INS_CSINC = 992
-AARCH64_INS_CSINV = 993
-AARCH64_INS_CSNEG = 994
-AARCH64_INS_CTERMEQ = 995
-AARCH64_INS_CTERMNE = 996
-AARCH64_INS_CTZ = 997
-AARCH64_INS_DCPS1 = 998
-AARCH64_INS_DCPS2 = 999
-AARCH64_INS_DCPS3 = 1000
-AARCH64_INS_DECB = 1001
-AARCH64_INS_DECD = 1002
-AARCH64_INS_DECH = 1003
-AARCH64_INS_DECP = 1004
-AARCH64_INS_DECW = 1005
-AARCH64_INS_DMB = 1006
-AARCH64_INS_DRPS = 1007
-AARCH64_INS_DSB = 1008
-AARCH64_INS_DUPM = 1009
-AARCH64_INS_DUPQ = 1010
-AARCH64_INS_DUP = 1011
-AARCH64_INS_MOV = 1012
-AARCH64_INS_EON = 1013
-AARCH64_INS_EOR3 = 1014
-AARCH64_INS_EORBT = 1015
-AARCH64_INS_EORQV = 1016
-AARCH64_INS_EORS = 1017
-AARCH64_INS_EORTB = 1018
-AARCH64_INS_EORV = 1019
-AARCH64_INS_EOR = 1020
-AARCH64_INS_ERET = 1021
-AARCH64_INS_ERETAA = 1022
-AARCH64_INS_ERETAB = 1023
-AARCH64_INS_EXTQ = 1024
-AARCH64_INS_MOVA = 1025
-AARCH64_INS_EXTR = 1026
-AARCH64_INS_EXT = 1027
-AARCH64_INS_F1CVTL2 = 1028
-AARCH64_INS_F1CVTLT = 1029
-AARCH64_INS_F1CVTL = 1030
-AARCH64_INS_F1CVT = 1031
-AARCH64_INS_F2CVTL2 = 1032
-AARCH64_INS_F2CVTLT = 1033
-AARCH64_INS_F2CVTL = 1034
-AARCH64_INS_F2CVT = 1035
-AARCH64_INS_FABD = 1036
-AARCH64_INS_FABS = 1037
-AARCH64_INS_FACGE = 1038
-AARCH64_INS_FACGT = 1039
-AARCH64_INS_FADDA = 1040
-AARCH64_INS_FADD = 1041
-AARCH64_INS_FADDP = 1042
-AARCH64_INS_FADDQV = 1043
-AARCH64_INS_FADDV = 1044
-AARCH64_INS_FAMAX = 1045
-AARCH64_INS_FAMIN = 1046
-AARCH64_INS_FCADD = 1047
-AARCH64_INS_FCCMP = 1048
-AARCH64_INS_FCCMPE = 1049
-AARCH64_INS_FCLAMP = 1050
-AARCH64_INS_FCMEQ = 1051
-AARCH64_INS_FCMGE = 1052
-AARCH64_INS_FCMGT = 1053
-AARCH64_INS_FCMLA = 1054
-AARCH64_INS_FCMLE = 1055
-AARCH64_INS_FCMLT = 1056
-AARCH64_INS_FCMNE = 1057
-AARCH64_INS_FCMP = 1058
-AARCH64_INS_FCMPE = 1059
-AARCH64_INS_FCMUO = 1060
-AARCH64_INS_FCPY = 1061
-AARCH64_INS_FCSEL = 1062
-AARCH64_INS_FCVTAS = 1063
-AARCH64_INS_FCVTAU = 1064
-AARCH64_INS_FCVT = 1065
-AARCH64_INS_FCVTLT = 1066
-AARCH64_INS_FCVTL = 1067
-AARCH64_INS_FCVTL2 = 1068
-AARCH64_INS_FCVTMS = 1069
-AARCH64_INS_FCVTMU = 1070
-AARCH64_INS_FCVTNB = 1071
-AARCH64_INS_FCVTNS = 1072
-AARCH64_INS_FCVTNT = 1073
-AARCH64_INS_FCVTNU = 1074
-AARCH64_INS_FCVTN = 1075
-AARCH64_INS_FCVTN2 = 1076
-AARCH64_INS_FCVTPS = 1077
-AARCH64_INS_FCVTPU = 1078
-AARCH64_INS_FCVTXNT = 1079
-AARCH64_INS_FCVTXN = 1080
-AARCH64_INS_FCVTXN2 = 1081
-AARCH64_INS_FCVTX = 1082
-AARCH64_INS_FCVTZS = 1083
-AARCH64_INS_FCVTZU = 1084
-AARCH64_INS_FDIV = 1085
-AARCH64_INS_FDIVR = 1086
-AARCH64_INS_FDOT = 1087
-AARCH64_INS_FDUP = 1088
-AARCH64_INS_FEXPA = 1089
-AARCH64_INS_FJCVTZS = 1090
-AARCH64_INS_FLOGB = 1091
-AARCH64_INS_FMADD = 1092
-AARCH64_INS_FMAD = 1093
-AARCH64_INS_FMAX = 1094
-AARCH64_INS_FMAXNM = 1095
-AARCH64_INS_FMAXNMP = 1096
-AARCH64_INS_FMAXNMQV = 1097
-AARCH64_INS_FMAXNMV = 1098
-AARCH64_INS_FMAXP = 1099
-AARCH64_INS_FMAXQV = 1100
-AARCH64_INS_FMAXV = 1101
-AARCH64_INS_FMIN = 1102
-AARCH64_INS_FMINNM = 1103
-AARCH64_INS_FMINNMP = 1104
-AARCH64_INS_FMINNMQV = 1105
-AARCH64_INS_FMINNMV = 1106
-AARCH64_INS_FMINP = 1107
-AARCH64_INS_FMINQV = 1108
-AARCH64_INS_FMINV = 1109
-AARCH64_INS_FMLAL2 = 1110
-AARCH64_INS_FMLALB = 1111
-AARCH64_INS_FMLALLBB = 1112
-AARCH64_INS_FMLALLBT = 1113
-AARCH64_INS_FMLALLTB = 1114
-AARCH64_INS_FMLALLTT = 1115
-AARCH64_INS_FMLALL = 1116
-AARCH64_INS_FMLALT = 1117
-AARCH64_INS_FMLAL = 1118
-AARCH64_INS_FMLA = 1119
-AARCH64_INS_FMLSL2 = 1120
-AARCH64_INS_FMLSLB = 1121
-AARCH64_INS_FMLSLT = 1122
-AARCH64_INS_FMLSL = 1123
-AARCH64_INS_FMLS = 1124
-AARCH64_INS_FMMLA = 1125
-AARCH64_INS_FMOPA = 1126
-AARCH64_INS_FMOPS = 1127
-AARCH64_INS_FMOV = 1128
-AARCH64_INS_FMSB = 1129
-AARCH64_INS_FMSUB = 1130
-AARCH64_INS_FMUL = 1131
-AARCH64_INS_FMULX = 1132
-AARCH64_INS_FNEG = 1133
-AARCH64_INS_FNMADD = 1134
-AARCH64_INS_FNMAD = 1135
-AARCH64_INS_FNMLA = 1136
-AARCH64_INS_FNMLS = 1137
-AARCH64_INS_FNMSB = 1138
-AARCH64_INS_FNMSUB = 1139
-AARCH64_INS_FNMUL = 1140
-AARCH64_INS_FRECPE = 1141
-AARCH64_INS_FRECPS = 1142
-AARCH64_INS_FRECPX = 1143
-AARCH64_INS_FRINT32X = 1144
-AARCH64_INS_FRINT32Z = 1145
-AARCH64_INS_FRINT64X = 1146
-AARCH64_INS_FRINT64Z = 1147
-AARCH64_INS_FRINTA = 1148
-AARCH64_INS_FRINTI = 1149
-AARCH64_INS_FRINTM = 1150
-AARCH64_INS_FRINTN = 1151
-AARCH64_INS_FRINTP = 1152
-AARCH64_INS_FRINTX = 1153
-AARCH64_INS_FRINTZ = 1154
-AARCH64_INS_FRSQRTE = 1155
-AARCH64_INS_FRSQRTS = 1156
-AARCH64_INS_FSCALE = 1157
-AARCH64_INS_FSQRT = 1158
-AARCH64_INS_FSUB = 1159
-AARCH64_INS_FSUBR = 1160
-AARCH64_INS_FTMAD = 1161
-AARCH64_INS_FTSMUL = 1162
-AARCH64_INS_FTSSEL = 1163
-AARCH64_INS_FVDOTB = 1164
-AARCH64_INS_FVDOTT = 1165
-AARCH64_INS_FVDOT = 1166
-AARCH64_INS_GCSPOPCX = 1167
-AARCH64_INS_GCSPOPM = 1168
-AARCH64_INS_GCSPOPX = 1169
-AARCH64_INS_GCSPUSHM = 1170
-AARCH64_INS_GCSPUSHX = 1171
-AARCH64_INS_GCSSS1 = 1172
-AARCH64_INS_GCSSS2 = 1173
-AARCH64_INS_GCSSTR = 1174
-AARCH64_INS_GCSSTTR = 1175
-AARCH64_INS_LD1B = 1176
-AARCH64_INS_LD1D = 1177
-AARCH64_INS_LD1H = 1178
-AARCH64_INS_LD1Q = 1179
-AARCH64_INS_LD1SB = 1180
-AARCH64_INS_LD1SH = 1181
-AARCH64_INS_LD1SW = 1182
-AARCH64_INS_LD1W = 1183
-AARCH64_INS_LDFF1B = 1184
-AARCH64_INS_LDFF1D = 1185
-AARCH64_INS_LDFF1H = 1186
-AARCH64_INS_LDFF1SB = 1187
-AARCH64_INS_LDFF1SH = 1188
-AARCH64_INS_LDFF1SW = 1189
-AARCH64_INS_LDFF1W = 1190
-AARCH64_INS_GMI = 1191
-AARCH64_INS_HISTCNT = 1192
-AARCH64_INS_HISTSEG = 1193
-AARCH64_INS_HLT = 1194
-AARCH64_INS_HVC = 1195
-AARCH64_INS_INCB = 1196
-AARCH64_INS_INCD = 1197
-AARCH64_INS_INCH = 1198
-AARCH64_INS_INCP = 1199
-AARCH64_INS_INCW = 1200
-AARCH64_INS_INDEX = 1201
-AARCH64_INS_INSR = 1202
-AARCH64_INS_INS = 1203
-AARCH64_INS_IRG = 1204
-AARCH64_INS_ISB = 1205
-AARCH64_INS_LASTA = 1206
-AARCH64_INS_LASTB = 1207
-AARCH64_INS_LD1 = 1208
-AARCH64_INS_LD1RB = 1209
-AARCH64_INS_LD1RD = 1210
-AARCH64_INS_LD1RH = 1211
-AARCH64_INS_LD1ROB = 1212
-AARCH64_INS_LD1ROD = 1213
-AARCH64_INS_LD1ROH = 1214
-AARCH64_INS_LD1ROW = 1215
-AARCH64_INS_LD1RQB = 1216
-AARCH64_INS_LD1RQD = 1217
-AARCH64_INS_LD1RQH = 1218
-AARCH64_INS_LD1RQW = 1219
-AARCH64_INS_LD1RSB = 1220
-AARCH64_INS_LD1RSH = 1221
-AARCH64_INS_LD1RSW = 1222
-AARCH64_INS_LD1RW = 1223
-AARCH64_INS_LD1R = 1224
-AARCH64_INS_LD2B = 1225
-AARCH64_INS_LD2D = 1226
-AARCH64_INS_LD2H = 1227
-AARCH64_INS_LD2Q = 1228
-AARCH64_INS_LD2R = 1229
-AARCH64_INS_LD2 = 1230
-AARCH64_INS_LD2W = 1231
-AARCH64_INS_LD3B = 1232
-AARCH64_INS_LD3D = 1233
-AARCH64_INS_LD3H = 1234
-AARCH64_INS_LD3Q = 1235
-AARCH64_INS_LD3R = 1236
-AARCH64_INS_LD3 = 1237
-AARCH64_INS_LD3W = 1238
-AARCH64_INS_LD4B = 1239
-AARCH64_INS_LD4D = 1240
-AARCH64_INS_LD4 = 1241
-AARCH64_INS_LD4H = 1242
-AARCH64_INS_LD4Q = 1243
-AARCH64_INS_LD4R = 1244
-AARCH64_INS_LD4W = 1245
-AARCH64_INS_LD64B = 1246
-AARCH64_INS_LDADDAB = 1247
-AARCH64_INS_LDADDAH = 1248
-AARCH64_INS_LDADDALB = 1249
-AARCH64_INS_LDADDALH = 1250
-AARCH64_INS_LDADDAL = 1251
-AARCH64_INS_LDADDA = 1252
-AARCH64_INS_LDADDB = 1253
-AARCH64_INS_LDADDH = 1254
-AARCH64_INS_LDADDLB = 1255
-AARCH64_INS_LDADDLH = 1256
-AARCH64_INS_LDADDL = 1257
-AARCH64_INS_LDADD = 1258
-AARCH64_INS_LDAP1 = 1259
-AARCH64_INS_LDAPRB = 1260
-AARCH64_INS_LDAPRH = 1261
-AARCH64_INS_LDAPR = 1262
-AARCH64_INS_LDAPURB = 1263
-AARCH64_INS_LDAPURH = 1264
-AARCH64_INS_LDAPURSB = 1265
-AARCH64_INS_LDAPURSH = 1266
-AARCH64_INS_LDAPURSW = 1267
-AARCH64_INS_LDAPUR = 1268
-AARCH64_INS_LDARB = 1269
-AARCH64_INS_LDARH = 1270
-AARCH64_INS_LDAR = 1271
-AARCH64_INS_LDAXP = 1272
-AARCH64_INS_LDAXRB = 1273
-AARCH64_INS_LDAXRH = 1274
-AARCH64_INS_LDAXR = 1275
-AARCH64_INS_LDCLRAB = 1276
-AARCH64_INS_LDCLRAH = 1277
-AARCH64_INS_LDCLRALB = 1278
-AARCH64_INS_LDCLRALH = 1279
-AARCH64_INS_LDCLRAL = 1280
-AARCH64_INS_LDCLRA = 1281
-AARCH64_INS_LDCLRB = 1282
-AARCH64_INS_LDCLRH = 1283
-AARCH64_INS_LDCLRLB = 1284
-AARCH64_INS_LDCLRLH = 1285
-AARCH64_INS_LDCLRL = 1286
-AARCH64_INS_LDCLRP = 1287
-AARCH64_INS_LDCLRPA = 1288
-AARCH64_INS_LDCLRPAL = 1289
-AARCH64_INS_LDCLRPL = 1290
-AARCH64_INS_LDCLR = 1291
-AARCH64_INS_LDEORAB = 1292
-AARCH64_INS_LDEORAH = 1293
-AARCH64_INS_LDEORALB = 1294
-AARCH64_INS_LDEORALH = 1295
-AARCH64_INS_LDEORAL = 1296
-AARCH64_INS_LDEORA = 1297
-AARCH64_INS_LDEORB = 1298
-AARCH64_INS_LDEORH = 1299
-AARCH64_INS_LDEORLB = 1300
-AARCH64_INS_LDEORLH = 1301
-AARCH64_INS_LDEORL = 1302
-AARCH64_INS_LDEOR = 1303
-AARCH64_INS_LDG = 1304
-AARCH64_INS_LDGM = 1305
-AARCH64_INS_LDIAPP = 1306
-AARCH64_INS_LDLARB = 1307
-AARCH64_INS_LDLARH = 1308
-AARCH64_INS_LDLAR = 1309
-AARCH64_INS_LDNF1B = 1310
-AARCH64_INS_LDNF1D = 1311
-AARCH64_INS_LDNF1H = 1312
-AARCH64_INS_LDNF1SB = 1313
-AARCH64_INS_LDNF1SH = 1314
-AARCH64_INS_LDNF1SW = 1315
-AARCH64_INS_LDNF1W = 1316
-AARCH64_INS_LDNP = 1317
-AARCH64_INS_LDNT1B = 1318
-AARCH64_INS_LDNT1D = 1319
-AARCH64_INS_LDNT1H = 1320
-AARCH64_INS_LDNT1SB = 1321
-AARCH64_INS_LDNT1SH = 1322
-AARCH64_INS_LDNT1SW = 1323
-AARCH64_INS_LDNT1W = 1324
-AARCH64_INS_LDP = 1325
-AARCH64_INS_LDPSW = 1326
-AARCH64_INS_LDRAA = 1327
-AARCH64_INS_LDRAB = 1328
-AARCH64_INS_LDRB = 1329
-AARCH64_INS_LDR = 1330
-AARCH64_INS_LDRH = 1331
-AARCH64_INS_LDRSB = 1332
-AARCH64_INS_LDRSH = 1333
-AARCH64_INS_LDRSW = 1334
-AARCH64_INS_LDSETAB = 1335
-AARCH64_INS_LDSETAH = 1336
-AARCH64_INS_LDSETALB = 1337
-AARCH64_INS_LDSETALH = 1338
-AARCH64_INS_LDSETAL = 1339
-AARCH64_INS_LDSETA = 1340
-AARCH64_INS_LDSETB = 1341
-AARCH64_INS_LDSETH = 1342
-AARCH64_INS_LDSETLB = 1343
-AARCH64_INS_LDSETLH = 1344
-AARCH64_INS_LDSETL = 1345
-AARCH64_INS_LDSETP = 1346
-AARCH64_INS_LDSETPA = 1347
-AARCH64_INS_LDSETPAL = 1348
-AARCH64_INS_LDSETPL = 1349
-AARCH64_INS_LDSET = 1350
-AARCH64_INS_LDSMAXAB = 1351
-AARCH64_INS_LDSMAXAH = 1352
-AARCH64_INS_LDSMAXALB = 1353
-AARCH64_INS_LDSMAXALH = 1354
-AARCH64_INS_LDSMAXAL = 1355
-AARCH64_INS_LDSMAXA = 1356
-AARCH64_INS_LDSMAXB = 1357
-AARCH64_INS_LDSMAXH = 1358
-AARCH64_INS_LDSMAXLB = 1359
-AARCH64_INS_LDSMAXLH = 1360
-AARCH64_INS_LDSMAXL = 1361
-AARCH64_INS_LDSMAX = 1362
-AARCH64_INS_LDSMINAB = 1363
-AARCH64_INS_LDSMINAH = 1364
-AARCH64_INS_LDSMINALB = 1365
-AARCH64_INS_LDSMINALH = 1366
-AARCH64_INS_LDSMINAL = 1367
-AARCH64_INS_LDSMINA = 1368
-AARCH64_INS_LDSMINB = 1369
-AARCH64_INS_LDSMINH = 1370
-AARCH64_INS_LDSMINLB = 1371
-AARCH64_INS_LDSMINLH = 1372
-AARCH64_INS_LDSMINL = 1373
-AARCH64_INS_LDSMIN = 1374
-AARCH64_INS_LDTRB = 1375
-AARCH64_INS_LDTRH = 1376
-AARCH64_INS_LDTRSB = 1377
-AARCH64_INS_LDTRSH = 1378
-AARCH64_INS_LDTRSW = 1379
-AARCH64_INS_LDTR = 1380
-AARCH64_INS_LDUMAXAB = 1381
-AARCH64_INS_LDUMAXAH = 1382
-AARCH64_INS_LDUMAXALB = 1383
-AARCH64_INS_LDUMAXALH = 1384
-AARCH64_INS_LDUMAXAL = 1385
-AARCH64_INS_LDUMAXA = 1386
-AARCH64_INS_LDUMAXB = 1387
-AARCH64_INS_LDUMAXH = 1388
-AARCH64_INS_LDUMAXLB = 1389
-AARCH64_INS_LDUMAXLH = 1390
-AARCH64_INS_LDUMAXL = 1391
-AARCH64_INS_LDUMAX = 1392
-AARCH64_INS_LDUMINAB = 1393
-AARCH64_INS_LDUMINAH = 1394
-AARCH64_INS_LDUMINALB = 1395
-AARCH64_INS_LDUMINALH = 1396
-AARCH64_INS_LDUMINAL = 1397
-AARCH64_INS_LDUMINA = 1398
-AARCH64_INS_LDUMINB = 1399
-AARCH64_INS_LDUMINH = 1400
-AARCH64_INS_LDUMINLB = 1401
-AARCH64_INS_LDUMINLH = 1402
-AARCH64_INS_LDUMINL = 1403
-AARCH64_INS_LDUMIN = 1404
-AARCH64_INS_LDURB = 1405
-AARCH64_INS_LDUR = 1406
-AARCH64_INS_LDURH = 1407
-AARCH64_INS_LDURSB = 1408
-AARCH64_INS_LDURSH = 1409
-AARCH64_INS_LDURSW = 1410
-AARCH64_INS_LDXP = 1411
-AARCH64_INS_LDXRB = 1412
-AARCH64_INS_LDXRH = 1413
-AARCH64_INS_LDXR = 1414
-AARCH64_INS_LSLR = 1415
-AARCH64_INS_LSL = 1416
-AARCH64_INS_LSRR = 1417
-AARCH64_INS_LSR = 1418
-AARCH64_INS_LUTI2 = 1419
-AARCH64_INS_LUTI4 = 1420
-AARCH64_INS_MADDPT = 1421
-AARCH64_INS_MADD = 1422
-AARCH64_INS_MADPT = 1423
-AARCH64_INS_MAD = 1424
-AARCH64_INS_MATCH = 1425
-AARCH64_INS_MLAPT = 1426
-AARCH64_INS_MLA = 1427
-AARCH64_INS_MLS = 1428
-AARCH64_INS_SETGE = 1429
-AARCH64_INS_SETGEN = 1430
-AARCH64_INS_SETGET = 1431
-AARCH64_INS_SETGETN = 1432
-AARCH64_INS_MOVAZ = 1433
-AARCH64_INS_MOVI = 1434
-AARCH64_INS_MOVK = 1435
-AARCH64_INS_MOVN = 1436
-AARCH64_INS_MOVPRFX = 1437
-AARCH64_INS_MOVT = 1438
-AARCH64_INS_MOVZ = 1439
-AARCH64_INS_MRRS = 1440
-AARCH64_INS_MRS = 1441
-AARCH64_INS_MSB = 1442
-AARCH64_INS_MSR = 1443
-AARCH64_INS_MSRR = 1444
-AARCH64_INS_MSUBPT = 1445
-AARCH64_INS_MSUB = 1446
-AARCH64_INS_MUL = 1447
-AARCH64_INS_MVNI = 1448
-AARCH64_INS_NANDS = 1449
-AARCH64_INS_NAND = 1450
-AARCH64_INS_NBSL = 1451
-AARCH64_INS_NEG = 1452
-AARCH64_INS_NMATCH = 1453
-AARCH64_INS_NORS = 1454
-AARCH64_INS_NOR = 1455
-AARCH64_INS_NOT = 1456
-AARCH64_INS_ORNS = 1457
-AARCH64_INS_ORN = 1458
-AARCH64_INS_ORQV = 1459
-AARCH64_INS_ORRS = 1460
-AARCH64_INS_ORR = 1461
-AARCH64_INS_ORV = 1462
-AARCH64_INS_PACDA = 1463
-AARCH64_INS_PACDB = 1464
-AARCH64_INS_PACDZA = 1465
-AARCH64_INS_PACDZB = 1466
-AARCH64_INS_PACGA = 1467
-AARCH64_INS_PACIA = 1468
-AARCH64_INS_PACIA171615 = 1469
-AARCH64_INS_PACIASPPC = 1470
-AARCH64_INS_PACIB = 1471
-AARCH64_INS_PACIB171615 = 1472
-AARCH64_INS_PACIBSPPC = 1473
-AARCH64_INS_PACIZA = 1474
-AARCH64_INS_PACIZB = 1475
-AARCH64_INS_PACNBIASPPC = 1476
-AARCH64_INS_PACNBIBSPPC = 1477
-AARCH64_INS_PEXT = 1478
-AARCH64_INS_PFALSE = 1479
-AARCH64_INS_PFIRST = 1480
-AARCH64_INS_PMOV = 1481
-AARCH64_INS_PMULLB = 1482
-AARCH64_INS_PMULLT = 1483
-AARCH64_INS_PMULL2 = 1484
-AARCH64_INS_PMULL = 1485
-AARCH64_INS_PMUL = 1486
-AARCH64_INS_PNEXT = 1487
-AARCH64_INS_PRFB = 1488
-AARCH64_INS_PRFD = 1489
-AARCH64_INS_PRFH = 1490
-AARCH64_INS_PRFM = 1491
-AARCH64_INS_PRFUM = 1492
-AARCH64_INS_PRFW = 1493
-AARCH64_INS_PSEL = 1494
-AARCH64_INS_PTEST = 1495
-AARCH64_INS_PTRUES = 1496
-AARCH64_INS_PTRUE = 1497
-AARCH64_INS_PUNPKHI = 1498
-AARCH64_INS_PUNPKLO = 1499
-AARCH64_INS_RADDHNB = 1500
-AARCH64_INS_RADDHNT = 1501
-AARCH64_INS_RADDHN = 1502
-AARCH64_INS_RADDHN2 = 1503
-AARCH64_INS_RAX1 = 1504
-AARCH64_INS_RBIT = 1505
-AARCH64_INS_RCWCAS = 1506
-AARCH64_INS_RCWCASA = 1507
-AARCH64_INS_RCWCASAL = 1508
-AARCH64_INS_RCWCASL = 1509
-AARCH64_INS_RCWCASP = 1510
-AARCH64_INS_RCWCASPA = 1511
-AARCH64_INS_RCWCASPAL = 1512
-AARCH64_INS_RCWCASPL = 1513
-AARCH64_INS_RCWCLR = 1514
-AARCH64_INS_RCWCLRA = 1515
-AARCH64_INS_RCWCLRAL = 1516
-AARCH64_INS_RCWCLRL = 1517
-AARCH64_INS_RCWCLRP = 1518
-AARCH64_INS_RCWCLRPA = 1519
-AARCH64_INS_RCWCLRPAL = 1520
-AARCH64_INS_RCWCLRPL = 1521
-AARCH64_INS_RCWSCLR = 1522
-AARCH64_INS_RCWSCLRA = 1523
-AARCH64_INS_RCWSCLRAL = 1524
-AARCH64_INS_RCWSCLRL = 1525
-AARCH64_INS_RCWSCLRP = 1526
-AARCH64_INS_RCWSCLRPA = 1527
-AARCH64_INS_RCWSCLRPAL = 1528
-AARCH64_INS_RCWSCLRPL = 1529
-AARCH64_INS_RCWSCAS = 1530
-AARCH64_INS_RCWSCASA = 1531
-AARCH64_INS_RCWSCASAL = 1532
-AARCH64_INS_RCWSCASL = 1533
-AARCH64_INS_RCWSCASP = 1534
-AARCH64_INS_RCWSCASPA = 1535
-AARCH64_INS_RCWSCASPAL = 1536
-AARCH64_INS_RCWSCASPL = 1537
-AARCH64_INS_RCWSET = 1538
-AARCH64_INS_RCWSETA = 1539
-AARCH64_INS_RCWSETAL = 1540
-AARCH64_INS_RCWSETL = 1541
-AARCH64_INS_RCWSETP = 1542
-AARCH64_INS_RCWSETPA = 1543
-AARCH64_INS_RCWSETPAL = 1544
-AARCH64_INS_RCWSETPL = 1545
-AARCH64_INS_RCWSSET = 1546
-AARCH64_INS_RCWSSETA = 1547
-AARCH64_INS_RCWSSETAL = 1548
-AARCH64_INS_RCWSSETL = 1549
-AARCH64_INS_RCWSSETP = 1550
-AARCH64_INS_RCWSSETPA = 1551
-AARCH64_INS_RCWSSETPAL = 1552
-AARCH64_INS_RCWSSETPL = 1553
-AARCH64_INS_RCWSWP = 1554
-AARCH64_INS_RCWSWPA = 1555
-AARCH64_INS_RCWSWPAL = 1556
-AARCH64_INS_RCWSWPL = 1557
-AARCH64_INS_RCWSWPP = 1558
-AARCH64_INS_RCWSWPPA = 1559
-AARCH64_INS_RCWSWPPAL = 1560
-AARCH64_INS_RCWSWPPL = 1561
-AARCH64_INS_RCWSSWP = 1562
-AARCH64_INS_RCWSSWPA = 1563
-AARCH64_INS_RCWSSWPAL = 1564
-AARCH64_INS_RCWSSWPL = 1565
-AARCH64_INS_RCWSSWPP = 1566
-AARCH64_INS_RCWSSWPPA = 1567
-AARCH64_INS_RCWSSWPPAL = 1568
-AARCH64_INS_RCWSSWPPL = 1569
-AARCH64_INS_RDFFRS = 1570
-AARCH64_INS_RDFFR = 1571
-AARCH64_INS_RDSVL = 1572
-AARCH64_INS_RDVL = 1573
-AARCH64_INS_RET = 1574
-AARCH64_INS_RETAA = 1575
-AARCH64_INS_RETAASPPC = 1576
-AARCH64_INS_RETAB = 1577
-AARCH64_INS_RETABSPPC = 1578
-AARCH64_INS_REV16 = 1579
-AARCH64_INS_REV32 = 1580
-AARCH64_INS_REV64 = 1581
-AARCH64_INS_REVB = 1582
-AARCH64_INS_REVD = 1583
-AARCH64_INS_REVH = 1584
-AARCH64_INS_REVW = 1585
-AARCH64_INS_REV = 1586
-AARCH64_INS_RMIF = 1587
-AARCH64_INS_ROR = 1588
-AARCH64_INS_RPRFM = 1589
-AARCH64_INS_RSHRNB = 1590
-AARCH64_INS_RSHRNT = 1591
-AARCH64_INS_RSHRN2 = 1592
-AARCH64_INS_RSHRN = 1593
-AARCH64_INS_RSUBHNB = 1594
-AARCH64_INS_RSUBHNT = 1595
-AARCH64_INS_RSUBHN = 1596
-AARCH64_INS_RSUBHN2 = 1597
-AARCH64_INS_SABALB = 1598
-AARCH64_INS_SABALT = 1599
-AARCH64_INS_SABAL2 = 1600
-AARCH64_INS_SABAL = 1601
-AARCH64_INS_SABA = 1602
-AARCH64_INS_SABDLB = 1603
-AARCH64_INS_SABDLT = 1604
-AARCH64_INS_SABDL2 = 1605
-AARCH64_INS_SABDL = 1606
-AARCH64_INS_SABD = 1607
-AARCH64_INS_SADALP = 1608
-AARCH64_INS_SADDLBT = 1609
-AARCH64_INS_SADDLB = 1610
-AARCH64_INS_SADDLP = 1611
-AARCH64_INS_SADDLT = 1612
-AARCH64_INS_SADDLV = 1613
-AARCH64_INS_SADDL2 = 1614
-AARCH64_INS_SADDL = 1615
-AARCH64_INS_SADDV = 1616
-AARCH64_INS_SADDWB = 1617
-AARCH64_INS_SADDWT = 1618
-AARCH64_INS_SADDW2 = 1619
-AARCH64_INS_SADDW = 1620
-AARCH64_INS_SB = 1621
-AARCH64_INS_SBCLB = 1622
-AARCH64_INS_SBCLT = 1623
-AARCH64_INS_SBCS = 1624
-AARCH64_INS_SBC = 1625
-AARCH64_INS_SBFM = 1626
-AARCH64_INS_SCLAMP = 1627
-AARCH64_INS_SCVTF = 1628
-AARCH64_INS_SDIVR = 1629
-AARCH64_INS_SDIV = 1630
-AARCH64_INS_SDOT = 1631
-AARCH64_INS_SEL = 1632
-AARCH64_INS_SETE = 1633
-AARCH64_INS_SETEN = 1634
-AARCH64_INS_SETET = 1635
-AARCH64_INS_SETETN = 1636
-AARCH64_INS_SETF16 = 1637
-AARCH64_INS_SETF8 = 1638
-AARCH64_INS_SETFFR = 1639
-AARCH64_INS_SETGM = 1640
-AARCH64_INS_SETGMN = 1641
-AARCH64_INS_SETGMT = 1642
-AARCH64_INS_SETGMTN = 1643
-AARCH64_INS_SETGP = 1644
-AARCH64_INS_SETGPN = 1645
-AARCH64_INS_SETGPT = 1646
-AARCH64_INS_SETGPTN = 1647
-AARCH64_INS_SETM = 1648
-AARCH64_INS_SETMN = 1649
-AARCH64_INS_SETMT = 1650
-AARCH64_INS_SETMTN = 1651
-AARCH64_INS_SETP = 1652
-AARCH64_INS_SETPN = 1653
-AARCH64_INS_SETPT = 1654
-AARCH64_INS_SETPTN = 1655
-AARCH64_INS_SHA1C = 1656
-AARCH64_INS_SHA1H = 1657
-AARCH64_INS_SHA1M = 1658
-AARCH64_INS_SHA1P = 1659
-AARCH64_INS_SHA1SU0 = 1660
-AARCH64_INS_SHA1SU1 = 1661
-AARCH64_INS_SHA256H2 = 1662
-AARCH64_INS_SHA256H = 1663
-AARCH64_INS_SHA256SU0 = 1664
-AARCH64_INS_SHA256SU1 = 1665
-AARCH64_INS_SHA512H = 1666
-AARCH64_INS_SHA512H2 = 1667
-AARCH64_INS_SHA512SU0 = 1668
-AARCH64_INS_SHA512SU1 = 1669
-AARCH64_INS_SHADD = 1670
-AARCH64_INS_SHLL2 = 1671
-AARCH64_INS_SHLL = 1672
-AARCH64_INS_SHL = 1673
-AARCH64_INS_SHRNB = 1674
-AARCH64_INS_SHRNT = 1675
-AARCH64_INS_SHRN2 = 1676
-AARCH64_INS_SHRN = 1677
-AARCH64_INS_SHSUBR = 1678
-AARCH64_INS_SHSUB = 1679
-AARCH64_INS_SLI = 1680
-AARCH64_INS_SM3PARTW1 = 1681
-AARCH64_INS_SM3PARTW2 = 1682
-AARCH64_INS_SM3SS1 = 1683
-AARCH64_INS_SM3TT1A = 1684
-AARCH64_INS_SM3TT1B = 1685
-AARCH64_INS_SM3TT2A = 1686
-AARCH64_INS_SM3TT2B = 1687
-AARCH64_INS_SM4E = 1688
-AARCH64_INS_SM4EKEY = 1689
-AARCH64_INS_SMADDL = 1690
-AARCH64_INS_SMAXP = 1691
-AARCH64_INS_SMAXQV = 1692
-AARCH64_INS_SMAXV = 1693
-AARCH64_INS_SMAX = 1694
-AARCH64_INS_SMC = 1695
-AARCH64_INS_SMINP = 1696
-AARCH64_INS_SMINQV = 1697
-AARCH64_INS_SMINV = 1698
-AARCH64_INS_SMIN = 1699
-AARCH64_INS_SMLALB = 1700
-AARCH64_INS_SMLALL = 1701
-AARCH64_INS_SMLALT = 1702
-AARCH64_INS_SMLAL = 1703
-AARCH64_INS_SMLAL2 = 1704
-AARCH64_INS_SMLSLB = 1705
-AARCH64_INS_SMLSLL = 1706
-AARCH64_INS_SMLSLT = 1707
-AARCH64_INS_SMLSL = 1708
-AARCH64_INS_SMLSL2 = 1709
-AARCH64_INS_SMMLA = 1710
-AARCH64_INS_SMOPA = 1711
-AARCH64_INS_SMOPS = 1712
-AARCH64_INS_SMOV = 1713
-AARCH64_INS_SMSUBL = 1714
-AARCH64_INS_SMULH = 1715
-AARCH64_INS_SMULLB = 1716
-AARCH64_INS_SMULLT = 1717
-AARCH64_INS_SMULL2 = 1718
-AARCH64_INS_SMULL = 1719
-AARCH64_INS_SPLICE = 1720
-AARCH64_INS_SQABS = 1721
-AARCH64_INS_SQADD = 1722
-AARCH64_INS_SQCADD = 1723
-AARCH64_INS_SQCVTN = 1724
-AARCH64_INS_SQCVTUN = 1725
-AARCH64_INS_SQCVTU = 1726
-AARCH64_INS_SQCVT = 1727
-AARCH64_INS_SQDECB = 1728
-AARCH64_INS_SQDECD = 1729
-AARCH64_INS_SQDECH = 1730
-AARCH64_INS_SQDECP = 1731
-AARCH64_INS_SQDECW = 1732
-AARCH64_INS_SQDMLALBT = 1733
-AARCH64_INS_SQDMLALB = 1734
-AARCH64_INS_SQDMLALT = 1735
-AARCH64_INS_SQDMLAL = 1736
-AARCH64_INS_SQDMLAL2 = 1737
-AARCH64_INS_SQDMLSLBT = 1738
-AARCH64_INS_SQDMLSLB = 1739
-AARCH64_INS_SQDMLSLT = 1740
-AARCH64_INS_SQDMLSL = 1741
-AARCH64_INS_SQDMLSL2 = 1742
-AARCH64_INS_SQDMULH = 1743
-AARCH64_INS_SQDMULLB = 1744
-AARCH64_INS_SQDMULLT = 1745
-AARCH64_INS_SQDMULL = 1746
-AARCH64_INS_SQDMULL2 = 1747
-AARCH64_INS_SQINCB = 1748
-AARCH64_INS_SQINCD = 1749
-AARCH64_INS_SQINCH = 1750
-AARCH64_INS_SQINCP = 1751
-AARCH64_INS_SQINCW = 1752
-AARCH64_INS_SQNEG = 1753
-AARCH64_INS_SQRDCMLAH = 1754
-AARCH64_INS_SQRDMLAH = 1755
-AARCH64_INS_SQRDMLSH = 1756
-AARCH64_INS_SQRDMULH = 1757
-AARCH64_INS_SQRSHLR = 1758
-AARCH64_INS_SQRSHL = 1759
-AARCH64_INS_SQRSHRNB = 1760
-AARCH64_INS_SQRSHRNT = 1761
-AARCH64_INS_SQRSHRN = 1762
-AARCH64_INS_SQRSHRN2 = 1763
-AARCH64_INS_SQRSHRUNB = 1764
-AARCH64_INS_SQRSHRUNT = 1765
-AARCH64_INS_SQRSHRUN = 1766
-AARCH64_INS_SQRSHRUN2 = 1767
-AARCH64_INS_SQRSHRU = 1768
-AARCH64_INS_SQRSHR = 1769
-AARCH64_INS_SQSHLR = 1770
-AARCH64_INS_SQSHLU = 1771
-AARCH64_INS_SQSHL = 1772
-AARCH64_INS_SQSHRNB = 1773
-AARCH64_INS_SQSHRNT = 1774
-AARCH64_INS_SQSHRN = 1775
-AARCH64_INS_SQSHRN2 = 1776
-AARCH64_INS_SQSHRUNB = 1777
-AARCH64_INS_SQSHRUNT = 1778
-AARCH64_INS_SQSHRUN = 1779
-AARCH64_INS_SQSHRUN2 = 1780
-AARCH64_INS_SQSUBR = 1781
-AARCH64_INS_SQSUB = 1782
-AARCH64_INS_SQXTNB = 1783
-AARCH64_INS_SQXTNT = 1784
-AARCH64_INS_SQXTN2 = 1785
-AARCH64_INS_SQXTN = 1786
-AARCH64_INS_SQXTUNB = 1787
-AARCH64_INS_SQXTUNT = 1788
-AARCH64_INS_SQXTUN2 = 1789
-AARCH64_INS_SQXTUN = 1790
-AARCH64_INS_SRHADD = 1791
-AARCH64_INS_SRI = 1792
-AARCH64_INS_SRSHLR = 1793
-AARCH64_INS_SRSHL = 1794
-AARCH64_INS_SRSHR = 1795
-AARCH64_INS_SRSRA = 1796
-AARCH64_INS_SSHLLB = 1797
-AARCH64_INS_SSHLLT = 1798
-AARCH64_INS_SSHLL2 = 1799
-AARCH64_INS_SSHLL = 1800
-AARCH64_INS_SSHL = 1801
-AARCH64_INS_SSHR = 1802
-AARCH64_INS_SSRA = 1803
-AARCH64_INS_ST1B = 1804
-AARCH64_INS_ST1D = 1805
-AARCH64_INS_ST1H = 1806
-AARCH64_INS_ST1Q = 1807
-AARCH64_INS_ST1W = 1808
-AARCH64_INS_SSUBLBT = 1809
-AARCH64_INS_SSUBLB = 1810
-AARCH64_INS_SSUBLTB = 1811
-AARCH64_INS_SSUBLT = 1812
-AARCH64_INS_SSUBL2 = 1813
-AARCH64_INS_SSUBL = 1814
-AARCH64_INS_SSUBWB = 1815
-AARCH64_INS_SSUBWT = 1816
-AARCH64_INS_SSUBW2 = 1817
-AARCH64_INS_SSUBW = 1818
-AARCH64_INS_ST1 = 1819
-AARCH64_INS_ST2B = 1820
-AARCH64_INS_ST2D = 1821
-AARCH64_INS_ST2G = 1822
-AARCH64_INS_ST2H = 1823
-AARCH64_INS_ST2Q = 1824
-AARCH64_INS_ST2 = 1825
-AARCH64_INS_ST2W = 1826
-AARCH64_INS_ST3B = 1827
-AARCH64_INS_ST3D = 1828
-AARCH64_INS_ST3H = 1829
-AARCH64_INS_ST3Q = 1830
-AARCH64_INS_ST3 = 1831
-AARCH64_INS_ST3W = 1832
-AARCH64_INS_ST4B = 1833
-AARCH64_INS_ST4D = 1834
-AARCH64_INS_ST4 = 1835
-AARCH64_INS_ST4H = 1836
-AARCH64_INS_ST4Q = 1837
-AARCH64_INS_ST4W = 1838
-AARCH64_INS_ST64B = 1839
-AARCH64_INS_ST64BV = 1840
-AARCH64_INS_ST64BV0 = 1841
-AARCH64_INS_STGM = 1842
-AARCH64_INS_STGP = 1843
-AARCH64_INS_STG = 1844
-AARCH64_INS_STILP = 1845
-AARCH64_INS_STL1 = 1846
-AARCH64_INS_STLLRB = 1847
-AARCH64_INS_STLLRH = 1848
-AARCH64_INS_STLLR = 1849
-AARCH64_INS_STLRB = 1850
-AARCH64_INS_STLRH = 1851
-AARCH64_INS_STLR = 1852
-AARCH64_INS_STLURB = 1853
-AARCH64_INS_STLURH = 1854
-AARCH64_INS_STLUR = 1855
-AARCH64_INS_STLXP = 1856
-AARCH64_INS_STLXRB = 1857
-AARCH64_INS_STLXRH = 1858
-AARCH64_INS_STLXR = 1859
-AARCH64_INS_STNP = 1860
-AARCH64_INS_STNT1B = 1861
-AARCH64_INS_STNT1D = 1862
-AARCH64_INS_STNT1H = 1863
-AARCH64_INS_STNT1W = 1864
-AARCH64_INS_STP = 1865
-AARCH64_INS_STRB = 1866
-AARCH64_INS_STR = 1867
-AARCH64_INS_STRH = 1868
-AARCH64_INS_STTRB = 1869
-AARCH64_INS_STTRH = 1870
-AARCH64_INS_STTR = 1871
-AARCH64_INS_STURB = 1872
-AARCH64_INS_STUR = 1873
-AARCH64_INS_STURH = 1874
-AARCH64_INS_STXP = 1875
-AARCH64_INS_STXRB = 1876
-AARCH64_INS_STXRH = 1877
-AARCH64_INS_STXR = 1878
-AARCH64_INS_STZ2G = 1879
-AARCH64_INS_STZGM = 1880
-AARCH64_INS_STZG = 1881
-AARCH64_INS_SUBG = 1882
-AARCH64_INS_SUBHNB = 1883
-AARCH64_INS_SUBHNT = 1884
-AARCH64_INS_SUBHN = 1885
-AARCH64_INS_SUBHN2 = 1886
-AARCH64_INS_SUBP = 1887
-AARCH64_INS_SUBPS = 1888
-AARCH64_INS_SUBPT = 1889
-AARCH64_INS_SUBR = 1890
-AARCH64_INS_SUBS = 1891
-AARCH64_INS_SUB = 1892
-AARCH64_INS_SUDOT = 1893
-AARCH64_INS_SUMLALL = 1894
-AARCH64_INS_SUMOPA = 1895
-AARCH64_INS_SUMOPS = 1896
-AARCH64_INS_SUNPKHI = 1897
-AARCH64_INS_SUNPKLO = 1898
-AARCH64_INS_SUNPK = 1899
-AARCH64_INS_SUQADD = 1900
-AARCH64_INS_SUVDOT = 1901
-AARCH64_INS_SVC = 1902
-AARCH64_INS_SVDOT = 1903
-AARCH64_INS_SWPAB = 1904
-AARCH64_INS_SWPAH = 1905
-AARCH64_INS_SWPALB = 1906
-AARCH64_INS_SWPALH = 1907
-AARCH64_INS_SWPAL = 1908
-AARCH64_INS_SWPA = 1909
-AARCH64_INS_SWPB = 1910
-AARCH64_INS_SWPH = 1911
-AARCH64_INS_SWPLB = 1912
-AARCH64_INS_SWPLH = 1913
-AARCH64_INS_SWPL = 1914
-AARCH64_INS_SWPP = 1915
-AARCH64_INS_SWPPA = 1916
-AARCH64_INS_SWPPAL = 1917
-AARCH64_INS_SWPPL = 1918
-AARCH64_INS_SWP = 1919
-AARCH64_INS_SXTB = 1920
-AARCH64_INS_SXTH = 1921
-AARCH64_INS_SXTW = 1922
-AARCH64_INS_SYSL = 1923
-AARCH64_INS_SYSP = 1924
-AARCH64_INS_SYS = 1925
-AARCH64_INS_TBLQ = 1926
-AARCH64_INS_TBL = 1927
-AARCH64_INS_TBNZ = 1928
-AARCH64_INS_TBXQ = 1929
-AARCH64_INS_TBX = 1930
-AARCH64_INS_TBZ = 1931
-AARCH64_INS_TCANCEL = 1932
-AARCH64_INS_TCOMMIT = 1933
-AARCH64_INS_TRCIT = 1934
-AARCH64_INS_TRN1 = 1935
-AARCH64_INS_TRN2 = 1936
-AARCH64_INS_TSB = 1937
-AARCH64_INS_TSTART = 1938
-AARCH64_INS_TTEST = 1939
-AARCH64_INS_UABALB = 1940
-AARCH64_INS_UABALT = 1941
-AARCH64_INS_UABAL2 = 1942
-AARCH64_INS_UABAL = 1943
-AARCH64_INS_UABA = 1944
-AARCH64_INS_UABDLB = 1945
-AARCH64_INS_UABDLT = 1946
-AARCH64_INS_UABDL2 = 1947
-AARCH64_INS_UABDL = 1948
-AARCH64_INS_UABD = 1949
-AARCH64_INS_UADALP = 1950
-AARCH64_INS_UADDLB = 1951
-AARCH64_INS_UADDLP = 1952
-AARCH64_INS_UADDLT = 1953
-AARCH64_INS_UADDLV = 1954
-AARCH64_INS_UADDL2 = 1955
-AARCH64_INS_UADDL = 1956
-AARCH64_INS_UADDV = 1957
-AARCH64_INS_UADDWB = 1958
-AARCH64_INS_UADDWT = 1959
-AARCH64_INS_UADDW2 = 1960
-AARCH64_INS_UADDW = 1961
-AARCH64_INS_UBFM = 1962
-AARCH64_INS_UCLAMP = 1963
-AARCH64_INS_UCVTF = 1964
-AARCH64_INS_UDF = 1965
-AARCH64_INS_UDIVR = 1966
-AARCH64_INS_UDIV = 1967
-AARCH64_INS_UDOT = 1968
-AARCH64_INS_UHADD = 1969
-AARCH64_INS_UHSUBR = 1970
-AARCH64_INS_UHSUB = 1971
-AARCH64_INS_UMADDL = 1972
-AARCH64_INS_UMAXP = 1973
-AARCH64_INS_UMAXQV = 1974
-AARCH64_INS_UMAXV = 1975
-AARCH64_INS_UMAX = 1976
-AARCH64_INS_UMINP = 1977
-AARCH64_INS_UMINQV = 1978
-AARCH64_INS_UMINV = 1979
-AARCH64_INS_UMIN = 1980
-AARCH64_INS_UMLALB = 1981
-AARCH64_INS_UMLALL = 1982
-AARCH64_INS_UMLALT = 1983
-AARCH64_INS_UMLAL = 1984
-AARCH64_INS_UMLAL2 = 1985
-AARCH64_INS_UMLSLB = 1986
-AARCH64_INS_UMLSLL = 1987
-AARCH64_INS_UMLSLT = 1988
-AARCH64_INS_UMLSL = 1989
-AARCH64_INS_UMLSL2 = 1990
-AARCH64_INS_UMMLA = 1991
-AARCH64_INS_UMOPA = 1992
-AARCH64_INS_UMOPS = 1993
-AARCH64_INS_UMOV = 1994
-AARCH64_INS_UMSUBL = 1995
-AARCH64_INS_UMULH = 1996
-AARCH64_INS_UMULLB = 1997
-AARCH64_INS_UMULLT = 1998
-AARCH64_INS_UMULL2 = 1999
-AARCH64_INS_UMULL = 2000
-AARCH64_INS_UQADD = 2001
-AARCH64_INS_UQCVTN = 2002
-AARCH64_INS_UQCVT = 2003
-AARCH64_INS_UQDECB = 2004
-AARCH64_INS_UQDECD = 2005
-AARCH64_INS_UQDECH = 2006
-AARCH64_INS_UQDECP = 2007
-AARCH64_INS_UQDECW = 2008
-AARCH64_INS_UQINCB = 2009
-AARCH64_INS_UQINCD = 2010
-AARCH64_INS_UQINCH = 2011
-AARCH64_INS_UQINCP = 2012
-AARCH64_INS_UQINCW = 2013
-AARCH64_INS_UQRSHLR = 2014
-AARCH64_INS_UQRSHL = 2015
-AARCH64_INS_UQRSHRNB = 2016
-AARCH64_INS_UQRSHRNT = 2017
-AARCH64_INS_UQRSHRN = 2018
-AARCH64_INS_UQRSHRN2 = 2019
-AARCH64_INS_UQRSHR = 2020
-AARCH64_INS_UQSHLR = 2021
-AARCH64_INS_UQSHL = 2022
-AARCH64_INS_UQSHRNB = 2023
-AARCH64_INS_UQSHRNT = 2024
-AARCH64_INS_UQSHRN = 2025
-AARCH64_INS_UQSHRN2 = 2026
-AARCH64_INS_UQSUBR = 2027
-AARCH64_INS_UQSUB = 2028
-AARCH64_INS_UQXTNB = 2029
-AARCH64_INS_UQXTNT = 2030
-AARCH64_INS_UQXTN2 = 2031
-AARCH64_INS_UQXTN = 2032
-AARCH64_INS_URECPE = 2033
-AARCH64_INS_URHADD = 2034
-AARCH64_INS_URSHLR = 2035
-AARCH64_INS_URSHL = 2036
-AARCH64_INS_URSHR = 2037
-AARCH64_INS_URSQRTE = 2038
-AARCH64_INS_URSRA = 2039
-AARCH64_INS_USDOT = 2040
-AARCH64_INS_USHLLB = 2041
-AARCH64_INS_USHLLT = 2042
-AARCH64_INS_USHLL2 = 2043
-AARCH64_INS_USHLL = 2044
-AARCH64_INS_USHL = 2045
-AARCH64_INS_USHR = 2046
-AARCH64_INS_USMLALL = 2047
-AARCH64_INS_USMMLA = 2048
-AARCH64_INS_USMOPA = 2049
-AARCH64_INS_USMOPS = 2050
-AARCH64_INS_USQADD = 2051
-AARCH64_INS_USRA = 2052
-AARCH64_INS_USUBLB = 2053
-AARCH64_INS_USUBLT = 2054
-AARCH64_INS_USUBL2 = 2055
-AARCH64_INS_USUBL = 2056
-AARCH64_INS_USUBWB = 2057
-AARCH64_INS_USUBWT = 2058
-AARCH64_INS_USUBW2 = 2059
-AARCH64_INS_USUBW = 2060
-AARCH64_INS_USVDOT = 2061
-AARCH64_INS_UUNPKHI = 2062
-AARCH64_INS_UUNPKLO = 2063
-AARCH64_INS_UUNPK = 2064
-AARCH64_INS_UVDOT = 2065
-AARCH64_INS_UXTB = 2066
-AARCH64_INS_UXTH = 2067
-AARCH64_INS_UXTW = 2068
-AARCH64_INS_UZP1 = 2069
-AARCH64_INS_UZP2 = 2070
-AARCH64_INS_UZPQ1 = 2071
-AARCH64_INS_UZPQ2 = 2072
-AARCH64_INS_UZP = 2073
-AARCH64_INS_WFET = 2074
-AARCH64_INS_WFIT = 2075
-AARCH64_INS_WHILEGE = 2076
-AARCH64_INS_WHILEGT = 2077
-AARCH64_INS_WHILEHI = 2078
-AARCH64_INS_WHILEHS = 2079
-AARCH64_INS_WHILELE = 2080
-AARCH64_INS_WHILELO = 2081
-AARCH64_INS_WHILELS = 2082
-AARCH64_INS_WHILELT = 2083
-AARCH64_INS_WHILERW = 2084
-AARCH64_INS_WHILEWR = 2085
-AARCH64_INS_WRFFR = 2086
-AARCH64_INS_XAFLAG = 2087
-AARCH64_INS_XAR = 2088
-AARCH64_INS_XPACD = 2089
-AARCH64_INS_XPACI = 2090
-AARCH64_INS_XTN2 = 2091
-AARCH64_INS_XTN = 2092
-AARCH64_INS_ZERO = 2093
-AARCH64_INS_ZIP1 = 2094
-AARCH64_INS_ZIP2 = 2095
-AARCH64_INS_ZIPQ1 = 2096
-AARCH64_INS_ZIPQ2 = 2097
-AARCH64_INS_ZIP = 2098
-AARCH64_INS_ENDING = 2099
-AARCH64_INS_ALIAS_BEGIN = 2100
-AARCH64_INS_ALIAS_ADDPT = 2101
-AARCH64_INS_ALIAS_GCSB = 2102
-AARCH64_INS_ALIAS_GCSPOPM = 2103
-AARCH64_INS_ALIAS_LDAPUR = 2104
-AARCH64_INS_ALIAS_STLLRB = 2105
-AARCH64_INS_ALIAS_STLLRH = 2106
-AARCH64_INS_ALIAS_STLLR = 2107
-AARCH64_INS_ALIAS_STLRB = 2108
-AARCH64_INS_ALIAS_STLRH = 2109
-AARCH64_INS_ALIAS_STLR = 2110
-AARCH64_INS_ALIAS_STLUR = 2111
-AARCH64_INS_ALIAS_SUBPT = 2112
-AARCH64_INS_ALIAS_LDRAA = 2113
-AARCH64_INS_ALIAS_ADD = 2114
-AARCH64_INS_ALIAS_CMN = 2115
-AARCH64_INS_ALIAS_ADDS = 2116
-AARCH64_INS_ALIAS_AND = 2117
-AARCH64_INS_ALIAS_ANDS = 2118
-AARCH64_INS_ALIAS_LDR = 2119
-AARCH64_INS_ALIAS_STR = 2120
-AARCH64_INS_ALIAS_LDRB = 2121
-AARCH64_INS_ALIAS_STRB = 2122
-AARCH64_INS_ALIAS_LDRH = 2123
-AARCH64_INS_ALIAS_STRH = 2124
-AARCH64_INS_ALIAS_PRFM = 2125
-AARCH64_INS_ALIAS_LDAPURB = 2126
-AARCH64_INS_ALIAS_STLURB = 2127
-AARCH64_INS_ALIAS_LDUR = 2128
-AARCH64_INS_ALIAS_STUR = 2129
-AARCH64_INS_ALIAS_PRFUM = 2130
-AARCH64_INS_ALIAS_LDTR = 2131
-AARCH64_INS_ALIAS_STTR = 2132
-AARCH64_INS_ALIAS_LDP = 2133
-AARCH64_INS_ALIAS_STGP = 2134
-AARCH64_INS_ALIAS_LDNP = 2135
-AARCH64_INS_ALIAS_STNP = 2136
-AARCH64_INS_ALIAS_STG = 2137
-AARCH64_INS_ALIAS_MOV = 2138
-AARCH64_INS_ALIAS_LD1 = 2139
-AARCH64_INS_ALIAS_LD1R = 2140
-AARCH64_INS_ALIAS_STADDLB = 2141
-AARCH64_INS_ALIAS_STADDLH = 2142
-AARCH64_INS_ALIAS_STADDL = 2143
-AARCH64_INS_ALIAS_STADDB = 2144
-AARCH64_INS_ALIAS_STADDH = 2145
-AARCH64_INS_ALIAS_STADD = 2146
-AARCH64_INS_ALIAS_PTRUE = 2147
-AARCH64_INS_ALIAS_PTRUES = 2148
-AARCH64_INS_ALIAS_CNTB = 2149
-AARCH64_INS_ALIAS_SQINCH = 2150
-AARCH64_INS_ALIAS_INCB = 2151
-AARCH64_INS_ALIAS_SQINCB = 2152
-AARCH64_INS_ALIAS_UQINCB = 2153
-AARCH64_INS_ALIAS_ORR = 2154
-AARCH64_INS_ALIAS_DUPM = 2155
-AARCH64_INS_ALIAS_FMOV = 2156
-AARCH64_INS_ALIAS_EOR3 = 2157
-AARCH64_INS_ALIAS_ST1B = 2158
-AARCH64_INS_ALIAS_ST2B = 2159
-AARCH64_INS_ALIAS_ST2Q = 2160
-AARCH64_INS_ALIAS_STNT1B = 2161
-AARCH64_INS_ALIAS_LD1B = 2162
-AARCH64_INS_ALIAS_LDNT1B = 2163
-AARCH64_INS_ALIAS_LD1RQB = 2164
-AARCH64_INS_ALIAS_LD1RB = 2165
-AARCH64_INS_ALIAS_LDFF1B = 2166
-AARCH64_INS_ALIAS_LDNF1B = 2167
-AARCH64_INS_ALIAS_LD2B = 2168
-AARCH64_INS_ALIAS_LD1SB = 2169
-AARCH64_INS_ALIAS_PRFB = 2170
-AARCH64_INS_ALIAS_LDNT1SB = 2171
-AARCH64_INS_ALIAS_LD1ROB = 2172
-AARCH64_INS_ALIAS_LD1Q = 2173
-AARCH64_INS_ALIAS_ST1Q = 2174
-AARCH64_INS_ALIAS_LD1W = 2175
-AARCH64_INS_ALIAS_PMOV = 2176
-AARCH64_INS_ALIAS_SMSTART = 2177
-AARCH64_INS_ALIAS_SMSTOP = 2178
-AARCH64_INS_ALIAS_ZERO = 2179
-AARCH64_INS_ALIAS_MOVT = 2180
-AARCH64_INS_ALIAS_NOP = 2181
-AARCH64_INS_ALIAS_YIELD = 2182
-AARCH64_INS_ALIAS_WFE = 2183
-AARCH64_INS_ALIAS_WFI = 2184
-AARCH64_INS_ALIAS_SEV = 2185
-AARCH64_INS_ALIAS_SEVL = 2186
-AARCH64_INS_ALIAS_DGH = 2187
-AARCH64_INS_ALIAS_ESB = 2188
-AARCH64_INS_ALIAS_CSDB = 2189
-AARCH64_INS_ALIAS_BTI = 2190
-AARCH64_INS_ALIAS_PSB = 2191
-AARCH64_INS_ALIAS_CHKFEAT = 2192
-AARCH64_INS_ALIAS_PACIAZ = 2193
-AARCH64_INS_ALIAS_PACIBZ = 2194
-AARCH64_INS_ALIAS_AUTIAZ = 2195
-AARCH64_INS_ALIAS_AUTIBZ = 2196
-AARCH64_INS_ALIAS_PACIASP = 2197
-AARCH64_INS_ALIAS_PACIBSP = 2198
-AARCH64_INS_ALIAS_AUTIASP = 2199
-AARCH64_INS_ALIAS_AUTIBSP = 2200
-AARCH64_INS_ALIAS_PACIA1716 = 2201
-AARCH64_INS_ALIAS_PACIB1716 = 2202
-AARCH64_INS_ALIAS_AUTIA1716 = 2203
-AARCH64_INS_ALIAS_AUTIB1716 = 2204
-AARCH64_INS_ALIAS_XPACLRI = 2205
-AARCH64_INS_ALIAS_LDRAB = 2206
-AARCH64_INS_ALIAS_PACM = 2207
-AARCH64_INS_ALIAS_CLREX = 2208
-AARCH64_INS_ALIAS_ISB = 2209
-AARCH64_INS_ALIAS_SSBB = 2210
-AARCH64_INS_ALIAS_PSSBB = 2211
-AARCH64_INS_ALIAS_DFB = 2212
-AARCH64_INS_ALIAS_SYS = 2213
-AARCH64_INS_ALIAS_MOVN = 2214
-AARCH64_INS_ALIAS_MOVZ = 2215
-AARCH64_INS_ALIAS_NGC = 2216
-AARCH64_INS_ALIAS_NGCS = 2217
-AARCH64_INS_ALIAS_SUB = 2218
-AARCH64_INS_ALIAS_CMP = 2219
-AARCH64_INS_ALIAS_SUBS = 2220
-AARCH64_INS_ALIAS_NEG = 2221
-AARCH64_INS_ALIAS_NEGS = 2222
-AARCH64_INS_ALIAS_MUL = 2223
-AARCH64_INS_ALIAS_MNEG = 2224
-AARCH64_INS_ALIAS_SMULL = 2225
-AARCH64_INS_ALIAS_SMNEGL = 2226
-AARCH64_INS_ALIAS_UMULL = 2227
-AARCH64_INS_ALIAS_UMNEGL = 2228
-AARCH64_INS_ALIAS_STCLRLB = 2229
-AARCH64_INS_ALIAS_STCLRLH = 2230
-AARCH64_INS_ALIAS_STCLRL = 2231
-AARCH64_INS_ALIAS_STCLRB = 2232
-AARCH64_INS_ALIAS_STCLRH = 2233
-AARCH64_INS_ALIAS_STCLR = 2234
-AARCH64_INS_ALIAS_STEORLB = 2235
-AARCH64_INS_ALIAS_STEORLH = 2236
-AARCH64_INS_ALIAS_STEORL = 2237
-AARCH64_INS_ALIAS_STEORB = 2238
-AARCH64_INS_ALIAS_STEORH = 2239
-AARCH64_INS_ALIAS_STEOR = 2240
-AARCH64_INS_ALIAS_STSETLB = 2241
-AARCH64_INS_ALIAS_STSETLH = 2242
-AARCH64_INS_ALIAS_STSETL = 2243
-AARCH64_INS_ALIAS_STSETB = 2244
-AARCH64_INS_ALIAS_STSETH = 2245
-AARCH64_INS_ALIAS_STSET = 2246
-AARCH64_INS_ALIAS_STSMAXLB = 2247
-AARCH64_INS_ALIAS_STSMAXLH = 2248
-AARCH64_INS_ALIAS_STSMAXL = 2249
-AARCH64_INS_ALIAS_STSMAXB = 2250
-AARCH64_INS_ALIAS_STSMAXH = 2251
-AARCH64_INS_ALIAS_STSMAX = 2252
-AARCH64_INS_ALIAS_STSMINLB = 2253
-AARCH64_INS_ALIAS_STSMINLH = 2254
-AARCH64_INS_ALIAS_STSMINL = 2255
-AARCH64_INS_ALIAS_STSMINB = 2256
-AARCH64_INS_ALIAS_STSMINH = 2257
-AARCH64_INS_ALIAS_STSMIN = 2258
-AARCH64_INS_ALIAS_STUMAXLB = 2259
-AARCH64_INS_ALIAS_STUMAXLH = 2260
-AARCH64_INS_ALIAS_STUMAXL = 2261
-AARCH64_INS_ALIAS_STUMAXB = 2262
-AARCH64_INS_ALIAS_STUMAXH = 2263
-AARCH64_INS_ALIAS_STUMAX = 2264
-AARCH64_INS_ALIAS_STUMINLB = 2265
-AARCH64_INS_ALIAS_STUMINLH = 2266
-AARCH64_INS_ALIAS_STUMINL = 2267
-AARCH64_INS_ALIAS_STUMINB = 2268
-AARCH64_INS_ALIAS_STUMINH = 2269
-AARCH64_INS_ALIAS_STUMIN = 2270
-AARCH64_INS_ALIAS_IRG = 2271
-AARCH64_INS_ALIAS_LDG = 2272
-AARCH64_INS_ALIAS_STZG = 2273
-AARCH64_INS_ALIAS_ST2G = 2274
-AARCH64_INS_ALIAS_STZ2G = 2275
-AARCH64_INS_ALIAS_BICS = 2276
-AARCH64_INS_ALIAS_BIC = 2277
-AARCH64_INS_ALIAS_EON = 2278
-AARCH64_INS_ALIAS_EOR = 2279
-AARCH64_INS_ALIAS_ORN = 2280
-AARCH64_INS_ALIAS_MVN = 2281
-AARCH64_INS_ALIAS_TST = 2282
-AARCH64_INS_ALIAS_ROR = 2283
-AARCH64_INS_ALIAS_ASR = 2284
-AARCH64_INS_ALIAS_SXTB = 2285
-AARCH64_INS_ALIAS_SXTH = 2286
-AARCH64_INS_ALIAS_SXTW = 2287
-AARCH64_INS_ALIAS_LSR = 2288
-AARCH64_INS_ALIAS_UXTB = 2289
-AARCH64_INS_ALIAS_UXTH = 2290
-AARCH64_INS_ALIAS_UXTW = 2291
-AARCH64_INS_ALIAS_CSET = 2292
-AARCH64_INS_ALIAS_CSETM = 2293
-AARCH64_INS_ALIAS_CINC = 2294
-AARCH64_INS_ALIAS_CINV = 2295
-AARCH64_INS_ALIAS_CNEG = 2296
-AARCH64_INS_ALIAS_RET = 2297
-AARCH64_INS_ALIAS_DCPS1 = 2298
-AARCH64_INS_ALIAS_DCPS2 = 2299
-AARCH64_INS_ALIAS_DCPS3 = 2300
-AARCH64_INS_ALIAS_LDPSW = 2301
-AARCH64_INS_ALIAS_LDRSH = 2302
-AARCH64_INS_ALIAS_LDRSB = 2303
-AARCH64_INS_ALIAS_LDRSW = 2304
-AARCH64_INS_ALIAS_LDURH = 2305
-AARCH64_INS_ALIAS_LDURB = 2306
-AARCH64_INS_ALIAS_LDURSH = 2307
-AARCH64_INS_ALIAS_LDURSB = 2308
-AARCH64_INS_ALIAS_LDURSW = 2309
-AARCH64_INS_ALIAS_LDTRH = 2310
-AARCH64_INS_ALIAS_LDTRB = 2311
-AARCH64_INS_ALIAS_LDTRSH = 2312
-AARCH64_INS_ALIAS_LDTRSB = 2313
-AARCH64_INS_ALIAS_LDTRSW = 2314
-AARCH64_INS_ALIAS_STP = 2315
-AARCH64_INS_ALIAS_STURH = 2316
-AARCH64_INS_ALIAS_STURB = 2317
-AARCH64_INS_ALIAS_STLURH = 2318
-AARCH64_INS_ALIAS_LDAPURSB = 2319
-AARCH64_INS_ALIAS_LDAPURH = 2320
-AARCH64_INS_ALIAS_LDAPURSH = 2321
-AARCH64_INS_ALIAS_LDAPURSW = 2322
-AARCH64_INS_ALIAS_STTRH = 2323
-AARCH64_INS_ALIAS_STTRB = 2324
-AARCH64_INS_ALIAS_BIC_4H = 2325
-AARCH64_INS_ALIAS_BIC_8H = 2326
-AARCH64_INS_ALIAS_BIC_2S = 2327
-AARCH64_INS_ALIAS_BIC_4S = 2328
-AARCH64_INS_ALIAS_ORR_4H = 2329
-AARCH64_INS_ALIAS_ORR_8H = 2330
-AARCH64_INS_ALIAS_ORR_2S = 2331
-AARCH64_INS_ALIAS_ORR_4S = 2332
-AARCH64_INS_ALIAS_SXTL_8H = 2333
-AARCH64_INS_ALIAS_SXTL = 2334
-AARCH64_INS_ALIAS_SXTL_4S = 2335
-AARCH64_INS_ALIAS_SXTL_2D = 2336
-AARCH64_INS_ALIAS_SXTL2_8H = 2337
-AARCH64_INS_ALIAS_SXTL2 = 2338
-AARCH64_INS_ALIAS_SXTL2_4S = 2339
-AARCH64_INS_ALIAS_SXTL2_2D = 2340
-AARCH64_INS_ALIAS_UXTL_8H = 2341
-AARCH64_INS_ALIAS_UXTL = 2342
-AARCH64_INS_ALIAS_UXTL_4S = 2343
-AARCH64_INS_ALIAS_UXTL_2D = 2344
-AARCH64_INS_ALIAS_UXTL2_8H = 2345
-AARCH64_INS_ALIAS_UXTL2 = 2346
-AARCH64_INS_ALIAS_UXTL2_4S = 2347
-AARCH64_INS_ALIAS_UXTL2_2D = 2348
-AARCH64_INS_ALIAS_LD2 = 2349
-AARCH64_INS_ALIAS_LD3 = 2350
-AARCH64_INS_ALIAS_LD4 = 2351
-AARCH64_INS_ALIAS_ST1 = 2352
-AARCH64_INS_ALIAS_ST2 = 2353
-AARCH64_INS_ALIAS_ST3 = 2354
-AARCH64_INS_ALIAS_ST4 = 2355
-AARCH64_INS_ALIAS_LD2R = 2356
-AARCH64_INS_ALIAS_LD3R = 2357
-AARCH64_INS_ALIAS_LD4R = 2358
-AARCH64_INS_ALIAS_CLRBHB = 2359
-AARCH64_INS_ALIAS_STILP = 2360
-AARCH64_INS_ALIAS_STL1 = 2361
-AARCH64_INS_ALIAS_SYSP = 2362
-AARCH64_INS_ALIAS_LD1SW = 2363
-AARCH64_INS_ALIAS_LD1H = 2364
-AARCH64_INS_ALIAS_LD1SH = 2365
-AARCH64_INS_ALIAS_LD1D = 2366
-AARCH64_INS_ALIAS_LD1RSW = 2367
-AARCH64_INS_ALIAS_LD1RH = 2368
-AARCH64_INS_ALIAS_LD1RSH = 2369
-AARCH64_INS_ALIAS_LD1RW = 2370
-AARCH64_INS_ALIAS_LD1RSB = 2371
-AARCH64_INS_ALIAS_LD1RD = 2372
-AARCH64_INS_ALIAS_LD1RQH = 2373
-AARCH64_INS_ALIAS_LD1RQW = 2374
-AARCH64_INS_ALIAS_LD1RQD = 2375
-AARCH64_INS_ALIAS_LDNF1SW = 2376
-AARCH64_INS_ALIAS_LDNF1H = 2377
-AARCH64_INS_ALIAS_LDNF1SH = 2378
-AARCH64_INS_ALIAS_LDNF1W = 2379
-AARCH64_INS_ALIAS_LDNF1SB = 2380
-AARCH64_INS_ALIAS_LDNF1D = 2381
-AARCH64_INS_ALIAS_LDFF1SW = 2382
-AARCH64_INS_ALIAS_LDFF1H = 2383
-AARCH64_INS_ALIAS_LDFF1SH = 2384
-AARCH64_INS_ALIAS_LDFF1W = 2385
-AARCH64_INS_ALIAS_LDFF1SB = 2386
-AARCH64_INS_ALIAS_LDFF1D = 2387
-AARCH64_INS_ALIAS_LD3B = 2388
-AARCH64_INS_ALIAS_LD4B = 2389
-AARCH64_INS_ALIAS_LD2H = 2390
-AARCH64_INS_ALIAS_LD3H = 2391
-AARCH64_INS_ALIAS_LD4H = 2392
-AARCH64_INS_ALIAS_LD2W = 2393
-AARCH64_INS_ALIAS_LD3W = 2394
-AARCH64_INS_ALIAS_LD4W = 2395
-AARCH64_INS_ALIAS_LD2D = 2396
-AARCH64_INS_ALIAS_LD3D = 2397
-AARCH64_INS_ALIAS_LD4D = 2398
-AARCH64_INS_ALIAS_LD2Q = 2399
-AARCH64_INS_ALIAS_LD3Q = 2400
-AARCH64_INS_ALIAS_LD4Q = 2401
-AARCH64_INS_ALIAS_LDNT1H = 2402
-AARCH64_INS_ALIAS_LDNT1W = 2403
-AARCH64_INS_ALIAS_LDNT1D = 2404
-AARCH64_INS_ALIAS_ST1H = 2405
-AARCH64_INS_ALIAS_ST1W = 2406
-AARCH64_INS_ALIAS_ST1D = 2407
-AARCH64_INS_ALIAS_ST3B = 2408
-AARCH64_INS_ALIAS_ST4B = 2409
-AARCH64_INS_ALIAS_ST2H = 2410
-AARCH64_INS_ALIAS_ST3H = 2411
-AARCH64_INS_ALIAS_ST4H = 2412
-AARCH64_INS_ALIAS_ST2W = 2413
-AARCH64_INS_ALIAS_ST3W = 2414
-AARCH64_INS_ALIAS_ST4W = 2415
-AARCH64_INS_ALIAS_ST2D = 2416
-AARCH64_INS_ALIAS_ST3D = 2417
-AARCH64_INS_ALIAS_ST4D = 2418
-AARCH64_INS_ALIAS_ST3Q = 2419
-AARCH64_INS_ALIAS_ST4Q = 2420
-AARCH64_INS_ALIAS_STNT1H = 2421
-AARCH64_INS_ALIAS_STNT1W = 2422
-AARCH64_INS_ALIAS_STNT1D = 2423
-AARCH64_INS_ALIAS_PRFH = 2424
-AARCH64_INS_ALIAS_PRFW = 2425
-AARCH64_INS_ALIAS_PRFD = 2426
-AARCH64_INS_ALIAS_CNTH = 2427
-AARCH64_INS_ALIAS_CNTW = 2428
-AARCH64_INS_ALIAS_CNTD = 2429
-AARCH64_INS_ALIAS_DECB = 2430
-AARCH64_INS_ALIAS_INCH = 2431
-AARCH64_INS_ALIAS_DECH = 2432
-AARCH64_INS_ALIAS_INCW = 2433
-AARCH64_INS_ALIAS_DECW = 2434
-AARCH64_INS_ALIAS_INCD = 2435
-AARCH64_INS_ALIAS_DECD = 2436
-AARCH64_INS_ALIAS_SQDECB = 2437
-AARCH64_INS_ALIAS_UQDECB = 2438
-AARCH64_INS_ALIAS_UQINCH = 2439
-AARCH64_INS_ALIAS_SQDECH = 2440
-AARCH64_INS_ALIAS_UQDECH = 2441
-AARCH64_INS_ALIAS_SQINCW = 2442
-AARCH64_INS_ALIAS_UQINCW = 2443
-AARCH64_INS_ALIAS_SQDECW = 2444
-AARCH64_INS_ALIAS_UQDECW = 2445
-AARCH64_INS_ALIAS_SQINCD = 2446
-AARCH64_INS_ALIAS_UQINCD = 2447
-AARCH64_INS_ALIAS_SQDECD = 2448
-AARCH64_INS_ALIAS_UQDECD = 2449
-AARCH64_INS_ALIAS_MOVS = 2450
-AARCH64_INS_ALIAS_NOT = 2451
-AARCH64_INS_ALIAS_NOTS = 2452
-AARCH64_INS_ALIAS_LD1ROH = 2453
-AARCH64_INS_ALIAS_LD1ROW = 2454
-AARCH64_INS_ALIAS_LD1ROD = 2455
-AARCH64_INS_ALIAS_BCAX = 2456
-AARCH64_INS_ALIAS_BSL = 2457
-AARCH64_INS_ALIAS_BSL1N = 2458
-AARCH64_INS_ALIAS_BSL2N = 2459
-AARCH64_INS_ALIAS_NBSL = 2460
-AARCH64_INS_ALIAS_LDNT1SH = 2461
-AARCH64_INS_ALIAS_LDNT1SW = 2462
-AARCH64_INS_ALIAS_CFP = 2463
-AARCH64_INS_ALIAS_DVP = 2464
-AARCH64_INS_ALIAS_COSP = 2465
-AARCH64_INS_ALIAS_CPP = 2466
-AARCH64_INS_ALIAS_IC = 2467
-AARCH64_INS_ALIAS_DC = 2468
-AARCH64_INS_ALIAS_AT = 2469
-AARCH64_INS_ALIAS_TLBI = 2470
-AARCH64_INS_ALIAS_TLBIP = 2471
-AARCH64_INS_ALIAS_RPRFM = 2472
-AARCH64_INS_ALIAS_LSL = 2473
-AARCH64_INS_ALIAS_SBFX = 2474
-AARCH64_INS_ALIAS_UBFX = 2475
-AARCH64_INS_ALIAS_SBFIZ = 2476
-AARCH64_INS_ALIAS_UBFIZ = 2477
-AARCH64_INS_ALIAS_BFC = 2478
-AARCH64_INS_ALIAS_BFI = 2479
-AARCH64_INS_ALIAS_BFXIL = 2480
-AARCH64_INS_ALIAS_END = 2481
+
+AARCH64_SME_MATRIX_TILE = 0
+AARCH64_SME_MATRIX_TILE_LIST = 1
+AARCH64_SME_MATRIX_SLICE_REG = 2
+AARCH64_SME_MATRIX_SLICE_OFF = 3
+AARCH64_SME_MATRIX_SLICE_OFF_RANGE = 4
+
+AARCH64_SME_OP_INVALID = 0
+AARCH64_SME_OP_TILE = 1
+AARCH64_SME_OP_TILE_VEC = 2
+
+AARCH64_INS_INVALID = 0
+AARCH64_INS_ABS = 1
+AARCH64_INS_ADCLB = 2
+AARCH64_INS_ADCLT = 3
+AARCH64_INS_ADCS = 4
+AARCH64_INS_ADC = 5
+AARCH64_INS_ADDG = 6
+AARCH64_INS_ADDHA = 7
+AARCH64_INS_ADDHNB = 8
+AARCH64_INS_ADDHNT = 9
+AARCH64_INS_ADDHN = 10
+AARCH64_INS_ADDHN2 = 11
+AARCH64_INS_ADDPL = 12
+AARCH64_INS_ADDPT = 13
+AARCH64_INS_ADDP = 14
+AARCH64_INS_ADDQV = 15
+AARCH64_INS_ADDSPL = 16
+AARCH64_INS_ADDSVL = 17
+AARCH64_INS_ADDS = 18
+AARCH64_INS_ADDVA = 19
+AARCH64_INS_ADDVL = 20
+AARCH64_INS_ADDV = 21
+AARCH64_INS_ADD = 22
+AARCH64_INS_ADR = 23
+AARCH64_INS_ADRP = 24
+AARCH64_INS_AESD = 25
+AARCH64_INS_AESE = 26
+AARCH64_INS_AESIMC = 27
+AARCH64_INS_AESMC = 28
+AARCH64_INS_ANDQV = 29
+AARCH64_INS_ANDS = 30
+AARCH64_INS_ANDV = 31
+AARCH64_INS_AND = 32
+AARCH64_INS_ASRD = 33
+AARCH64_INS_ASRR = 34
+AARCH64_INS_ASR = 35
+AARCH64_INS_AUTDA = 36
+AARCH64_INS_AUTDB = 37
+AARCH64_INS_AUTDZA = 38
+AARCH64_INS_AUTDZB = 39
+AARCH64_INS_AUTIA = 40
+AARCH64_INS_HINT = 41
+AARCH64_INS_AUTIA171615 = 42
+AARCH64_INS_AUTIASPPC = 43
+AARCH64_INS_AUTIB = 44
+AARCH64_INS_AUTIB171615 = 45
+AARCH64_INS_AUTIBSPPC = 46
+AARCH64_INS_AUTIZA = 47
+AARCH64_INS_AUTIZB = 48
+AARCH64_INS_AXFLAG = 49
+AARCH64_INS_B = 50
+AARCH64_INS_BCAX = 51
+AARCH64_INS_BC = 52
+AARCH64_INS_BDEP = 53
+AARCH64_INS_BEXT = 54
+AARCH64_INS_BFDOT = 55
+AARCH64_INS_BF1CVTL2 = 56
+AARCH64_INS_BF1CVTLT = 57
+AARCH64_INS_BF1CVTL = 58
+AARCH64_INS_BF1CVT = 59
+AARCH64_INS_BF2CVTL2 = 60
+AARCH64_INS_BF2CVTLT = 61
+AARCH64_INS_BF2CVTL = 62
+AARCH64_INS_BF2CVT = 63
+AARCH64_INS_BFADD = 64
+AARCH64_INS_BFCLAMP = 65
+AARCH64_INS_BFCVT = 66
+AARCH64_INS_BFCVTN = 67
+AARCH64_INS_BFCVTN2 = 68
+AARCH64_INS_BFCVTNT = 69
+AARCH64_INS_BFMAXNM = 70
+AARCH64_INS_BFMAX = 71
+AARCH64_INS_BFMINNM = 72
+AARCH64_INS_BFMIN = 73
+AARCH64_INS_BFMLALB = 74
+AARCH64_INS_BFMLALT = 75
+AARCH64_INS_BFMLAL = 76
+AARCH64_INS_BFMLA = 77
+AARCH64_INS_BFMLSLB = 78
+AARCH64_INS_BFMLSLT = 79
+AARCH64_INS_BFMLSL = 80
+AARCH64_INS_BFMLS = 81
+AARCH64_INS_BFMMLA = 82
+AARCH64_INS_BFMOPA = 83
+AARCH64_INS_BFMOPS = 84
+AARCH64_INS_BFMUL = 85
+AARCH64_INS_BFM = 86
+AARCH64_INS_BFSUB = 87
+AARCH64_INS_BFVDOT = 88
+AARCH64_INS_BGRP = 89
+AARCH64_INS_BICS = 90
+AARCH64_INS_BIC = 91
+AARCH64_INS_BIF = 92
+AARCH64_INS_BIT = 93
+AARCH64_INS_BL = 94
+AARCH64_INS_BLR = 95
+AARCH64_INS_BLRAA = 96
+AARCH64_INS_BLRAAZ = 97
+AARCH64_INS_BLRAB = 98
+AARCH64_INS_BLRABZ = 99
+AARCH64_INS_BMOPA = 100
+AARCH64_INS_BMOPS = 101
+AARCH64_INS_BR = 102
+AARCH64_INS_BRAA = 103
+AARCH64_INS_BRAAZ = 104
+AARCH64_INS_BRAB = 105
+AARCH64_INS_BRABZ = 106
+AARCH64_INS_BRB = 107
+AARCH64_INS_BRK = 108
+AARCH64_INS_BRKAS = 109
+AARCH64_INS_BRKA = 110
+AARCH64_INS_BRKBS = 111
+AARCH64_INS_BRKB = 112
+AARCH64_INS_BRKNS = 113
+AARCH64_INS_BRKN = 114
+AARCH64_INS_BRKPAS = 115
+AARCH64_INS_BRKPA = 116
+AARCH64_INS_BRKPBS = 117
+AARCH64_INS_BRKPB = 118
+AARCH64_INS_BSL1N = 119
+AARCH64_INS_BSL2N = 120
+AARCH64_INS_BSL = 121
+AARCH64_INS_CADD = 122
+AARCH64_INS_CASAB = 123
+AARCH64_INS_CASAH = 124
+AARCH64_INS_CASALB = 125
+AARCH64_INS_CASALH = 126
+AARCH64_INS_CASAL = 127
+AARCH64_INS_CASA = 128
+AARCH64_INS_CASB = 129
+AARCH64_INS_CASH = 130
+AARCH64_INS_CASLB = 131
+AARCH64_INS_CASLH = 132
+AARCH64_INS_CASL = 133
+AARCH64_INS_CASPAL = 134
+AARCH64_INS_CASPA = 135
+AARCH64_INS_CASPL = 136
+AARCH64_INS_CASP = 137
+AARCH64_INS_CAS = 138
+AARCH64_INS_CBNZ = 139
+AARCH64_INS_CBZ = 140
+AARCH64_INS_CCMN = 141
+AARCH64_INS_CCMP = 142
+AARCH64_INS_CDOT = 143
+AARCH64_INS_CFINV = 144
+AARCH64_INS_CLASTA = 145
+AARCH64_INS_CLASTB = 146
+AARCH64_INS_CLREX = 147
+AARCH64_INS_CLS = 148
+AARCH64_INS_CLZ = 149
+AARCH64_INS_CMEQ = 150
+AARCH64_INS_CMGE = 151
+AARCH64_INS_CMGT = 152
+AARCH64_INS_CMHI = 153
+AARCH64_INS_CMHS = 154
+AARCH64_INS_CMLA = 155
+AARCH64_INS_CMLE = 156
+AARCH64_INS_CMLT = 157
+AARCH64_INS_CMPEQ = 158
+AARCH64_INS_CMPGE = 159
+AARCH64_INS_CMPGT = 160
+AARCH64_INS_CMPHI = 161
+AARCH64_INS_CMPHS = 162
+AARCH64_INS_CMPLE = 163
+AARCH64_INS_CMPLO = 164
+AARCH64_INS_CMPLS = 165
+AARCH64_INS_CMPLT = 166
+AARCH64_INS_CMPNE = 167
+AARCH64_INS_CMTST = 168
+AARCH64_INS_CNOT = 169
+AARCH64_INS_CNTB = 170
+AARCH64_INS_CNTD = 171
+AARCH64_INS_CNTH = 172
+AARCH64_INS_CNTP = 173
+AARCH64_INS_CNTW = 174
+AARCH64_INS_CNT = 175
+AARCH64_INS_COMPACT = 176
+AARCH64_INS_CPYE = 177
+AARCH64_INS_CPYEN = 178
+AARCH64_INS_CPYERN = 179
+AARCH64_INS_CPYERT = 180
+AARCH64_INS_CPYERTN = 181
+AARCH64_INS_CPYERTRN = 182
+AARCH64_INS_CPYERTWN = 183
+AARCH64_INS_CPYET = 184
+AARCH64_INS_CPYETN = 185
+AARCH64_INS_CPYETRN = 186
+AARCH64_INS_CPYETWN = 187
+AARCH64_INS_CPYEWN = 188
+AARCH64_INS_CPYEWT = 189
+AARCH64_INS_CPYEWTN = 190
+AARCH64_INS_CPYEWTRN = 191
+AARCH64_INS_CPYEWTWN = 192
+AARCH64_INS_CPYFE = 193
+AARCH64_INS_CPYFEN = 194
+AARCH64_INS_CPYFERN = 195
+AARCH64_INS_CPYFERT = 196
+AARCH64_INS_CPYFERTN = 197
+AARCH64_INS_CPYFERTRN = 198
+AARCH64_INS_CPYFERTWN = 199
+AARCH64_INS_CPYFET = 200
+AARCH64_INS_CPYFETN = 201
+AARCH64_INS_CPYFETRN = 202
+AARCH64_INS_CPYFETWN = 203
+AARCH64_INS_CPYFEWN = 204
+AARCH64_INS_CPYFEWT = 205
+AARCH64_INS_CPYFEWTN = 206
+AARCH64_INS_CPYFEWTRN = 207
+AARCH64_INS_CPYFEWTWN = 208
+AARCH64_INS_CPYFM = 209
+AARCH64_INS_CPYFMN = 210
+AARCH64_INS_CPYFMRN = 211
+AARCH64_INS_CPYFMRT = 212
+AARCH64_INS_CPYFMRTN = 213
+AARCH64_INS_CPYFMRTRN = 214
+AARCH64_INS_CPYFMRTWN = 215
+AARCH64_INS_CPYFMT = 216
+AARCH64_INS_CPYFMTN = 217
+AARCH64_INS_CPYFMTRN = 218
+AARCH64_INS_CPYFMTWN = 219
+AARCH64_INS_CPYFMWN = 220
+AARCH64_INS_CPYFMWT = 221
+AARCH64_INS_CPYFMWTN = 222
+AARCH64_INS_CPYFMWTRN = 223
+AARCH64_INS_CPYFMWTWN = 224
+AARCH64_INS_CPYFP = 225
+AARCH64_INS_CPYFPN = 226
+AARCH64_INS_CPYFPRN = 227
+AARCH64_INS_CPYFPRT = 228
+AARCH64_INS_CPYFPRTN = 229
+AARCH64_INS_CPYFPRTRN = 230
+AARCH64_INS_CPYFPRTWN = 231
+AARCH64_INS_CPYFPT = 232
+AARCH64_INS_CPYFPTN = 233
+AARCH64_INS_CPYFPTRN = 234
+AARCH64_INS_CPYFPTWN = 235
+AARCH64_INS_CPYFPWN = 236
+AARCH64_INS_CPYFPWT = 237
+AARCH64_INS_CPYFPWTN = 238
+AARCH64_INS_CPYFPWTRN = 239
+AARCH64_INS_CPYFPWTWN = 240
+AARCH64_INS_CPYM = 241
+AARCH64_INS_CPYMN = 242
+AARCH64_INS_CPYMRN = 243
+AARCH64_INS_CPYMRT = 244
+AARCH64_INS_CPYMRTN = 245
+AARCH64_INS_CPYMRTRN = 246
+AARCH64_INS_CPYMRTWN = 247
+AARCH64_INS_CPYMT = 248
+AARCH64_INS_CPYMTN = 249
+AARCH64_INS_CPYMTRN = 250
+AARCH64_INS_CPYMTWN = 251
+AARCH64_INS_CPYMWN = 252
+AARCH64_INS_CPYMWT = 253
+AARCH64_INS_CPYMWTN = 254
+AARCH64_INS_CPYMWTRN = 255
+AARCH64_INS_CPYMWTWN = 256
+AARCH64_INS_CPYP = 257
+AARCH64_INS_CPYPN = 258
+AARCH64_INS_CPYPRN = 259
+AARCH64_INS_CPYPRT = 260
+AARCH64_INS_CPYPRTN = 261
+AARCH64_INS_CPYPRTRN = 262
+AARCH64_INS_CPYPRTWN = 263
+AARCH64_INS_CPYPT = 264
+AARCH64_INS_CPYPTN = 265
+AARCH64_INS_CPYPTRN = 266
+AARCH64_INS_CPYPTWN = 267
+AARCH64_INS_CPYPWN = 268
+AARCH64_INS_CPYPWT = 269
+AARCH64_INS_CPYPWTN = 270
+AARCH64_INS_CPYPWTRN = 271
+AARCH64_INS_CPYPWTWN = 272
+AARCH64_INS_CPY = 273
+AARCH64_INS_CRC32B = 274
+AARCH64_INS_CRC32CB = 275
+AARCH64_INS_CRC32CH = 276
+AARCH64_INS_CRC32CW = 277
+AARCH64_INS_CRC32CX = 278
+AARCH64_INS_CRC32H = 279
+AARCH64_INS_CRC32W = 280
+AARCH64_INS_CRC32X = 281
+AARCH64_INS_CSEL = 282
+AARCH64_INS_CSINC = 283
+AARCH64_INS_CSINV = 284
+AARCH64_INS_CSNEG = 285
+AARCH64_INS_CTERMEQ = 286
+AARCH64_INS_CTERMNE = 287
+AARCH64_INS_CTZ = 288
+AARCH64_INS_DCPS1 = 289
+AARCH64_INS_DCPS2 = 290
+AARCH64_INS_DCPS3 = 291
+AARCH64_INS_DECB = 292
+AARCH64_INS_DECD = 293
+AARCH64_INS_DECH = 294
+AARCH64_INS_DECP = 295
+AARCH64_INS_DECW = 296
+AARCH64_INS_DMB = 297
+AARCH64_INS_DRPS = 298
+AARCH64_INS_DSB = 299
+AARCH64_INS_DUPM = 300
+AARCH64_INS_DUPQ = 301
+AARCH64_INS_DUP = 302
+AARCH64_INS_MOV = 303
+AARCH64_INS_EON = 304
+AARCH64_INS_EOR3 = 305
+AARCH64_INS_EORBT = 306
+AARCH64_INS_EORQV = 307
+AARCH64_INS_EORS = 308
+AARCH64_INS_EORTB = 309
+AARCH64_INS_EORV = 310
+AARCH64_INS_EOR = 311
+AARCH64_INS_ERET = 312
+AARCH64_INS_ERETAA = 313
+AARCH64_INS_ERETAB = 314
+AARCH64_INS_EXTQ = 315
+AARCH64_INS_MOVA = 316
+AARCH64_INS_EXTR = 317
+AARCH64_INS_EXT = 318
+AARCH64_INS_F1CVTL2 = 319
+AARCH64_INS_F1CVTLT = 320
+AARCH64_INS_F1CVTL = 321
+AARCH64_INS_F1CVT = 322
+AARCH64_INS_F2CVTL2 = 323
+AARCH64_INS_F2CVTLT = 324
+AARCH64_INS_F2CVTL = 325
+AARCH64_INS_F2CVT = 326
+AARCH64_INS_FABD = 327
+AARCH64_INS_FABS = 328
+AARCH64_INS_FACGE = 329
+AARCH64_INS_FACGT = 330
+AARCH64_INS_FADDA = 331
+AARCH64_INS_FADD = 332
+AARCH64_INS_FADDP = 333
+AARCH64_INS_FADDQV = 334
+AARCH64_INS_FADDV = 335
+AARCH64_INS_FAMAX = 336
+AARCH64_INS_FAMIN = 337
+AARCH64_INS_FCADD = 338
+AARCH64_INS_FCCMP = 339
+AARCH64_INS_FCCMPE = 340
+AARCH64_INS_FCLAMP = 341
+AARCH64_INS_FCMEQ = 342
+AARCH64_INS_FCMGE = 343
+AARCH64_INS_FCMGT = 344
+AARCH64_INS_FCMLA = 345
+AARCH64_INS_FCMLE = 346
+AARCH64_INS_FCMLT = 347
+AARCH64_INS_FCMNE = 348
+AARCH64_INS_FCMP = 349
+AARCH64_INS_FCMPE = 350
+AARCH64_INS_FCMUO = 351
+AARCH64_INS_FCPY = 352
+AARCH64_INS_FCSEL = 353
+AARCH64_INS_FCVTAS = 354
+AARCH64_INS_FCVTAU = 355
+AARCH64_INS_FCVT = 356
+AARCH64_INS_FCVTLT = 357
+AARCH64_INS_FCVTL = 358
+AARCH64_INS_FCVTL2 = 359
+AARCH64_INS_FCVTMS = 360
+AARCH64_INS_FCVTMU = 361
+AARCH64_INS_FCVTNB = 362
+AARCH64_INS_FCVTNS = 363
+AARCH64_INS_FCVTNT = 364
+AARCH64_INS_FCVTNU = 365
+AARCH64_INS_FCVTN = 366
+AARCH64_INS_FCVTN2 = 367
+AARCH64_INS_FCVTPS = 368
+AARCH64_INS_FCVTPU = 369
+AARCH64_INS_FCVTXNT = 370
+AARCH64_INS_FCVTXN = 371
+AARCH64_INS_FCVTXN2 = 372
+AARCH64_INS_FCVTX = 373
+AARCH64_INS_FCVTZS = 374
+AARCH64_INS_FCVTZU = 375
+AARCH64_INS_FDIV = 376
+AARCH64_INS_FDIVR = 377
+AARCH64_INS_FDOT = 378
+AARCH64_INS_FDUP = 379
+AARCH64_INS_FEXPA = 380
+AARCH64_INS_FJCVTZS = 381
+AARCH64_INS_FLOGB = 382
+AARCH64_INS_FMADD = 383
+AARCH64_INS_FMAD = 384
+AARCH64_INS_FMAX = 385
+AARCH64_INS_FMAXNM = 386
+AARCH64_INS_FMAXNMP = 387
+AARCH64_INS_FMAXNMQV = 388
+AARCH64_INS_FMAXNMV = 389
+AARCH64_INS_FMAXP = 390
+AARCH64_INS_FMAXQV = 391
+AARCH64_INS_FMAXV = 392
+AARCH64_INS_FMIN = 393
+AARCH64_INS_FMINNM = 394
+AARCH64_INS_FMINNMP = 395
+AARCH64_INS_FMINNMQV = 396
+AARCH64_INS_FMINNMV = 397
+AARCH64_INS_FMINP = 398
+AARCH64_INS_FMINQV = 399
+AARCH64_INS_FMINV = 400
+AARCH64_INS_FMLAL2 = 401
+AARCH64_INS_FMLALB = 402
+AARCH64_INS_FMLALLBB = 403
+AARCH64_INS_FMLALLBT = 404
+AARCH64_INS_FMLALLTB = 405
+AARCH64_INS_FMLALLTT = 406
+AARCH64_INS_FMLALL = 407
+AARCH64_INS_FMLALT = 408
+AARCH64_INS_FMLAL = 409
+AARCH64_INS_FMLA = 410
+AARCH64_INS_FMLSL2 = 411
+AARCH64_INS_FMLSLB = 412
+AARCH64_INS_FMLSLT = 413
+AARCH64_INS_FMLSL = 414
+AARCH64_INS_FMLS = 415
+AARCH64_INS_FMMLA = 416
+AARCH64_INS_FMOPA = 417
+AARCH64_INS_FMOPS = 418
+AARCH64_INS_FMOV = 419
+AARCH64_INS_FMSB = 420
+AARCH64_INS_FMSUB = 421
+AARCH64_INS_FMUL = 422
+AARCH64_INS_FMULX = 423
+AARCH64_INS_FNEG = 424
+AARCH64_INS_FNMADD = 425
+AARCH64_INS_FNMAD = 426
+AARCH64_INS_FNMLA = 427
+AARCH64_INS_FNMLS = 428
+AARCH64_INS_FNMSB = 429
+AARCH64_INS_FNMSUB = 430
+AARCH64_INS_FNMUL = 431
+AARCH64_INS_FRECPE = 432
+AARCH64_INS_FRECPS = 433
+AARCH64_INS_FRECPX = 434
+AARCH64_INS_FRINT32X = 435
+AARCH64_INS_FRINT32Z = 436
+AARCH64_INS_FRINT64X = 437
+AARCH64_INS_FRINT64Z = 438
+AARCH64_INS_FRINTA = 439
+AARCH64_INS_FRINTI = 440
+AARCH64_INS_FRINTM = 441
+AARCH64_INS_FRINTN = 442
+AARCH64_INS_FRINTP = 443
+AARCH64_INS_FRINTX = 444
+AARCH64_INS_FRINTZ = 445
+AARCH64_INS_FRSQRTE = 446
+AARCH64_INS_FRSQRTS = 447
+AARCH64_INS_FSCALE = 448
+AARCH64_INS_FSQRT = 449
+AARCH64_INS_FSUB = 450
+AARCH64_INS_FSUBR = 451
+AARCH64_INS_FTMAD = 452
+AARCH64_INS_FTSMUL = 453
+AARCH64_INS_FTSSEL = 454
+AARCH64_INS_FVDOTB = 455
+AARCH64_INS_FVDOTT = 456
+AARCH64_INS_FVDOT = 457
+AARCH64_INS_GCSPOPCX = 458
+AARCH64_INS_GCSPOPM = 459
+AARCH64_INS_GCSPOPX = 460
+AARCH64_INS_GCSPUSHM = 461
+AARCH64_INS_GCSPUSHX = 462
+AARCH64_INS_GCSSS1 = 463
+AARCH64_INS_GCSSS2 = 464
+AARCH64_INS_GCSSTR = 465
+AARCH64_INS_GCSSTTR = 466
+AARCH64_INS_LD1B = 467
+AARCH64_INS_LD1D = 468
+AARCH64_INS_LD1H = 469
+AARCH64_INS_LD1Q = 470
+AARCH64_INS_LD1SB = 471
+AARCH64_INS_LD1SH = 472
+AARCH64_INS_LD1SW = 473
+AARCH64_INS_LD1W = 474
+AARCH64_INS_LDFF1B = 475
+AARCH64_INS_LDFF1D = 476
+AARCH64_INS_LDFF1H = 477
+AARCH64_INS_LDFF1SB = 478
+AARCH64_INS_LDFF1SH = 479
+AARCH64_INS_LDFF1SW = 480
+AARCH64_INS_LDFF1W = 481
+AARCH64_INS_GMI = 482
+AARCH64_INS_HISTCNT = 483
+AARCH64_INS_HISTSEG = 484
+AARCH64_INS_HLT = 485
+AARCH64_INS_HVC = 486
+AARCH64_INS_INCB = 487
+AARCH64_INS_INCD = 488
+AARCH64_INS_INCH = 489
+AARCH64_INS_INCP = 490
+AARCH64_INS_INCW = 491
+AARCH64_INS_INDEX = 492
+AARCH64_INS_INSR = 493
+AARCH64_INS_INS = 494
+AARCH64_INS_IRG = 495
+AARCH64_INS_ISB = 496
+AARCH64_INS_LASTA = 497
+AARCH64_INS_LASTB = 498
+AARCH64_INS_LD1 = 499
+AARCH64_INS_LD1RB = 500
+AARCH64_INS_LD1RD = 501
+AARCH64_INS_LD1RH = 502
+AARCH64_INS_LD1ROB = 503
+AARCH64_INS_LD1ROD = 504
+AARCH64_INS_LD1ROH = 505
+AARCH64_INS_LD1ROW = 506
+AARCH64_INS_LD1RQB = 507
+AARCH64_INS_LD1RQD = 508
+AARCH64_INS_LD1RQH = 509
+AARCH64_INS_LD1RQW = 510
+AARCH64_INS_LD1RSB = 511
+AARCH64_INS_LD1RSH = 512
+AARCH64_INS_LD1RSW = 513
+AARCH64_INS_LD1RW = 514
+AARCH64_INS_LD1R = 515
+AARCH64_INS_LD2B = 516
+AARCH64_INS_LD2D = 517
+AARCH64_INS_LD2H = 518
+AARCH64_INS_LD2Q = 519
+AARCH64_INS_LD2R = 520
+AARCH64_INS_LD2 = 521
+AARCH64_INS_LD2W = 522
+AARCH64_INS_LD3B = 523
+AARCH64_INS_LD3D = 524
+AARCH64_INS_LD3H = 525
+AARCH64_INS_LD3Q = 526
+AARCH64_INS_LD3R = 527
+AARCH64_INS_LD3 = 528
+AARCH64_INS_LD3W = 529
+AARCH64_INS_LD4B = 530
+AARCH64_INS_LD4D = 531
+AARCH64_INS_LD4 = 532
+AARCH64_INS_LD4H = 533
+AARCH64_INS_LD4Q = 534
+AARCH64_INS_LD4R = 535
+AARCH64_INS_LD4W = 536
+AARCH64_INS_LD64B = 537
+AARCH64_INS_LDADDAB = 538
+AARCH64_INS_LDADDAH = 539
+AARCH64_INS_LDADDALB = 540
+AARCH64_INS_LDADDALH = 541
+AARCH64_INS_LDADDAL = 542
+AARCH64_INS_LDADDA = 543
+AARCH64_INS_LDADDB = 544
+AARCH64_INS_LDADDH = 545
+AARCH64_INS_LDADDLB = 546
+AARCH64_INS_LDADDLH = 547
+AARCH64_INS_LDADDL = 548
+AARCH64_INS_LDADD = 549
+AARCH64_INS_LDAP1 = 550
+AARCH64_INS_LDAPRB = 551
+AARCH64_INS_LDAPRH = 552
+AARCH64_INS_LDAPR = 553
+AARCH64_INS_LDAPURB = 554
+AARCH64_INS_LDAPURH = 555
+AARCH64_INS_LDAPURSB = 556
+AARCH64_INS_LDAPURSH = 557
+AARCH64_INS_LDAPURSW = 558
+AARCH64_INS_LDAPUR = 559
+AARCH64_INS_LDARB = 560
+AARCH64_INS_LDARH = 561
+AARCH64_INS_LDAR = 562
+AARCH64_INS_LDAXP = 563
+AARCH64_INS_LDAXRB = 564
+AARCH64_INS_LDAXRH = 565
+AARCH64_INS_LDAXR = 566
+AARCH64_INS_LDCLRAB = 567
+AARCH64_INS_LDCLRAH = 568
+AARCH64_INS_LDCLRALB = 569
+AARCH64_INS_LDCLRALH = 570
+AARCH64_INS_LDCLRAL = 571
+AARCH64_INS_LDCLRA = 572
+AARCH64_INS_LDCLRB = 573
+AARCH64_INS_LDCLRH = 574
+AARCH64_INS_LDCLRLB = 575
+AARCH64_INS_LDCLRLH = 576
+AARCH64_INS_LDCLRL = 577
+AARCH64_INS_LDCLRP = 578
+AARCH64_INS_LDCLRPA = 579
+AARCH64_INS_LDCLRPAL = 580
+AARCH64_INS_LDCLRPL = 581
+AARCH64_INS_LDCLR = 582
+AARCH64_INS_LDEORAB = 583
+AARCH64_INS_LDEORAH = 584
+AARCH64_INS_LDEORALB = 585
+AARCH64_INS_LDEORALH = 586
+AARCH64_INS_LDEORAL = 587
+AARCH64_INS_LDEORA = 588
+AARCH64_INS_LDEORB = 589
+AARCH64_INS_LDEORH = 590
+AARCH64_INS_LDEORLB = 591
+AARCH64_INS_LDEORLH = 592
+AARCH64_INS_LDEORL = 593
+AARCH64_INS_LDEOR = 594
+AARCH64_INS_LDG = 595
+AARCH64_INS_LDGM = 596
+AARCH64_INS_LDIAPP = 597
+AARCH64_INS_LDLARB = 598
+AARCH64_INS_LDLARH = 599
+AARCH64_INS_LDLAR = 600
+AARCH64_INS_LDNF1B = 601
+AARCH64_INS_LDNF1D = 602
+AARCH64_INS_LDNF1H = 603
+AARCH64_INS_LDNF1SB = 604
+AARCH64_INS_LDNF1SH = 605
+AARCH64_INS_LDNF1SW = 606
+AARCH64_INS_LDNF1W = 607
+AARCH64_INS_LDNP = 608
+AARCH64_INS_LDNT1B = 609
+AARCH64_INS_LDNT1D = 610
+AARCH64_INS_LDNT1H = 611
+AARCH64_INS_LDNT1SB = 612
+AARCH64_INS_LDNT1SH = 613
+AARCH64_INS_LDNT1SW = 614
+AARCH64_INS_LDNT1W = 615
+AARCH64_INS_LDP = 616
+AARCH64_INS_LDPSW = 617
+AARCH64_INS_LDRAA = 618
+AARCH64_INS_LDRAB = 619
+AARCH64_INS_LDRB = 620
+AARCH64_INS_LDR = 621
+AARCH64_INS_LDRH = 622
+AARCH64_INS_LDRSB = 623
+AARCH64_INS_LDRSH = 624
+AARCH64_INS_LDRSW = 625
+AARCH64_INS_LDSETAB = 626
+AARCH64_INS_LDSETAH = 627
+AARCH64_INS_LDSETALB = 628
+AARCH64_INS_LDSETALH = 629
+AARCH64_INS_LDSETAL = 630
+AARCH64_INS_LDSETA = 631
+AARCH64_INS_LDSETB = 632
+AARCH64_INS_LDSETH = 633
+AARCH64_INS_LDSETLB = 634
+AARCH64_INS_LDSETLH = 635
+AARCH64_INS_LDSETL = 636
+AARCH64_INS_LDSETP = 637
+AARCH64_INS_LDSETPA = 638
+AARCH64_INS_LDSETPAL = 639
+AARCH64_INS_LDSETPL = 640
+AARCH64_INS_LDSET = 641
+AARCH64_INS_LDSMAXAB = 642
+AARCH64_INS_LDSMAXAH = 643
+AARCH64_INS_LDSMAXALB = 644
+AARCH64_INS_LDSMAXALH = 645
+AARCH64_INS_LDSMAXAL = 646
+AARCH64_INS_LDSMAXA = 647
+AARCH64_INS_LDSMAXB = 648
+AARCH64_INS_LDSMAXH = 649
+AARCH64_INS_LDSMAXLB = 650
+AARCH64_INS_LDSMAXLH = 651
+AARCH64_INS_LDSMAXL = 652
+AARCH64_INS_LDSMAX = 653
+AARCH64_INS_LDSMINAB = 654
+AARCH64_INS_LDSMINAH = 655
+AARCH64_INS_LDSMINALB = 656
+AARCH64_INS_LDSMINALH = 657
+AARCH64_INS_LDSMINAL = 658
+AARCH64_INS_LDSMINA = 659
+AARCH64_INS_LDSMINB = 660
+AARCH64_INS_LDSMINH = 661
+AARCH64_INS_LDSMINLB = 662
+AARCH64_INS_LDSMINLH = 663
+AARCH64_INS_LDSMINL = 664
+AARCH64_INS_LDSMIN = 665
+AARCH64_INS_LDTRB = 666
+AARCH64_INS_LDTRH = 667
+AARCH64_INS_LDTRSB = 668
+AARCH64_INS_LDTRSH = 669
+AARCH64_INS_LDTRSW = 670
+AARCH64_INS_LDTR = 671
+AARCH64_INS_LDUMAXAB = 672
+AARCH64_INS_LDUMAXAH = 673
+AARCH64_INS_LDUMAXALB = 674
+AARCH64_INS_LDUMAXALH = 675
+AARCH64_INS_LDUMAXAL = 676
+AARCH64_INS_LDUMAXA = 677
+AARCH64_INS_LDUMAXB = 678
+AARCH64_INS_LDUMAXH = 679
+AARCH64_INS_LDUMAXLB = 680
+AARCH64_INS_LDUMAXLH = 681
+AARCH64_INS_LDUMAXL = 682
+AARCH64_INS_LDUMAX = 683
+AARCH64_INS_LDUMINAB = 684
+AARCH64_INS_LDUMINAH = 685
+AARCH64_INS_LDUMINALB = 686
+AARCH64_INS_LDUMINALH = 687
+AARCH64_INS_LDUMINAL = 688
+AARCH64_INS_LDUMINA = 689
+AARCH64_INS_LDUMINB = 690
+AARCH64_INS_LDUMINH = 691
+AARCH64_INS_LDUMINLB = 692
+AARCH64_INS_LDUMINLH = 693
+AARCH64_INS_LDUMINL = 694
+AARCH64_INS_LDUMIN = 695
+AARCH64_INS_LDURB = 696
+AARCH64_INS_LDUR = 697
+AARCH64_INS_LDURH = 698
+AARCH64_INS_LDURSB = 699
+AARCH64_INS_LDURSH = 700
+AARCH64_INS_LDURSW = 701
+AARCH64_INS_LDXP = 702
+AARCH64_INS_LDXRB = 703
+AARCH64_INS_LDXRH = 704
+AARCH64_INS_LDXR = 705
+AARCH64_INS_LSLR = 706
+AARCH64_INS_LSL = 707
+AARCH64_INS_LSRR = 708
+AARCH64_INS_LSR = 709
+AARCH64_INS_LUTI2 = 710
+AARCH64_INS_LUTI4 = 711
+AARCH64_INS_MADDPT = 712
+AARCH64_INS_MADD = 713
+AARCH64_INS_MADPT = 714
+AARCH64_INS_MAD = 715
+AARCH64_INS_MATCH = 716
+AARCH64_INS_MLAPT = 717
+AARCH64_INS_MLA = 718
+AARCH64_INS_MLS = 719
+AARCH64_INS_SETGE = 720
+AARCH64_INS_SETGEN = 721
+AARCH64_INS_SETGET = 722
+AARCH64_INS_SETGETN = 723
+AARCH64_INS_MOVAZ = 724
+AARCH64_INS_MOVI = 725
+AARCH64_INS_MOVK = 726
+AARCH64_INS_MOVN = 727
+AARCH64_INS_MOVPRFX = 728
+AARCH64_INS_MOVT = 729
+AARCH64_INS_MOVZ = 730
+AARCH64_INS_MRRS = 731
+AARCH64_INS_MRS = 732
+AARCH64_INS_MSB = 733
+AARCH64_INS_MSR = 734
+AARCH64_INS_MSRR = 735
+AARCH64_INS_MSUBPT = 736
+AARCH64_INS_MSUB = 737
+AARCH64_INS_MUL = 738
+AARCH64_INS_MVNI = 739
+AARCH64_INS_NANDS = 740
+AARCH64_INS_NAND = 741
+AARCH64_INS_NBSL = 742
+AARCH64_INS_NEG = 743
+AARCH64_INS_NMATCH = 744
+AARCH64_INS_NORS = 745
+AARCH64_INS_NOR = 746
+AARCH64_INS_NOT = 747
+AARCH64_INS_ORNS = 748
+AARCH64_INS_ORN = 749
+AARCH64_INS_ORQV = 750
+AARCH64_INS_ORRS = 751
+AARCH64_INS_ORR = 752
+AARCH64_INS_ORV = 753
+AARCH64_INS_PACDA = 754
+AARCH64_INS_PACDB = 755
+AARCH64_INS_PACDZA = 756
+AARCH64_INS_PACDZB = 757
+AARCH64_INS_PACGA = 758
+AARCH64_INS_PACIA = 759
+AARCH64_INS_PACIA171615 = 760
+AARCH64_INS_PACIASPPC = 761
+AARCH64_INS_PACIB = 762
+AARCH64_INS_PACIB171615 = 763
+AARCH64_INS_PACIBSPPC = 764
+AARCH64_INS_PACIZA = 765
+AARCH64_INS_PACIZB = 766
+AARCH64_INS_PACNBIASPPC = 767
+AARCH64_INS_PACNBIBSPPC = 768
+AARCH64_INS_PEXT = 769
+AARCH64_INS_PFALSE = 770
+AARCH64_INS_PFIRST = 771
+AARCH64_INS_PMOV = 772
+AARCH64_INS_PMULLB = 773
+AARCH64_INS_PMULLT = 774
+AARCH64_INS_PMULL2 = 775
+AARCH64_INS_PMULL = 776
+AARCH64_INS_PMUL = 777
+AARCH64_INS_PNEXT = 778
+AARCH64_INS_PRFB = 779
+AARCH64_INS_PRFD = 780
+AARCH64_INS_PRFH = 781
+AARCH64_INS_PRFM = 782
+AARCH64_INS_PRFUM = 783
+AARCH64_INS_PRFW = 784
+AARCH64_INS_PSEL = 785
+AARCH64_INS_PTEST = 786
+AARCH64_INS_PTRUES = 787
+AARCH64_INS_PTRUE = 788
+AARCH64_INS_PUNPKHI = 789
+AARCH64_INS_PUNPKLO = 790
+AARCH64_INS_RADDHNB = 791
+AARCH64_INS_RADDHNT = 792
+AARCH64_INS_RADDHN = 793
+AARCH64_INS_RADDHN2 = 794
+AARCH64_INS_RAX1 = 795
+AARCH64_INS_RBIT = 796
+AARCH64_INS_RCWCAS = 797
+AARCH64_INS_RCWCASA = 798
+AARCH64_INS_RCWCASAL = 799
+AARCH64_INS_RCWCASL = 800
+AARCH64_INS_RCWCASP = 801
+AARCH64_INS_RCWCASPA = 802
+AARCH64_INS_RCWCASPAL = 803
+AARCH64_INS_RCWCASPL = 804
+AARCH64_INS_RCWCLR = 805
+AARCH64_INS_RCWCLRA = 806
+AARCH64_INS_RCWCLRAL = 807
+AARCH64_INS_RCWCLRL = 808
+AARCH64_INS_RCWCLRP = 809
+AARCH64_INS_RCWCLRPA = 810
+AARCH64_INS_RCWCLRPAL = 811
+AARCH64_INS_RCWCLRPL = 812
+AARCH64_INS_RCWSCLR = 813
+AARCH64_INS_RCWSCLRA = 814
+AARCH64_INS_RCWSCLRAL = 815
+AARCH64_INS_RCWSCLRL = 816
+AARCH64_INS_RCWSCLRP = 817
+AARCH64_INS_RCWSCLRPA = 818
+AARCH64_INS_RCWSCLRPAL = 819
+AARCH64_INS_RCWSCLRPL = 820
+AARCH64_INS_RCWSCAS = 821
+AARCH64_INS_RCWSCASA = 822
+AARCH64_INS_RCWSCASAL = 823
+AARCH64_INS_RCWSCASL = 824
+AARCH64_INS_RCWSCASP = 825
+AARCH64_INS_RCWSCASPA = 826
+AARCH64_INS_RCWSCASPAL = 827
+AARCH64_INS_RCWSCASPL = 828
+AARCH64_INS_RCWSET = 829
+AARCH64_INS_RCWSETA = 830
+AARCH64_INS_RCWSETAL = 831
+AARCH64_INS_RCWSETL = 832
+AARCH64_INS_RCWSETP = 833
+AARCH64_INS_RCWSETPA = 834
+AARCH64_INS_RCWSETPAL = 835
+AARCH64_INS_RCWSETPL = 836
+AARCH64_INS_RCWSSET = 837
+AARCH64_INS_RCWSSETA = 838
+AARCH64_INS_RCWSSETAL = 839
+AARCH64_INS_RCWSSETL = 840
+AARCH64_INS_RCWSSETP = 841
+AARCH64_INS_RCWSSETPA = 842
+AARCH64_INS_RCWSSETPAL = 843
+AARCH64_INS_RCWSSETPL = 844
+AARCH64_INS_RCWSWP = 845
+AARCH64_INS_RCWSWPA = 846
+AARCH64_INS_RCWSWPAL = 847
+AARCH64_INS_RCWSWPL = 848
+AARCH64_INS_RCWSWPP = 849
+AARCH64_INS_RCWSWPPA = 850
+AARCH64_INS_RCWSWPPAL = 851
+AARCH64_INS_RCWSWPPL = 852
+AARCH64_INS_RCWSSWP = 853
+AARCH64_INS_RCWSSWPA = 854
+AARCH64_INS_RCWSSWPAL = 855
+AARCH64_INS_RCWSSWPL = 856
+AARCH64_INS_RCWSSWPP = 857
+AARCH64_INS_RCWSSWPPA = 858
+AARCH64_INS_RCWSSWPPAL = 859
+AARCH64_INS_RCWSSWPPL = 860
+AARCH64_INS_RDFFRS = 861
+AARCH64_INS_RDFFR = 862
+AARCH64_INS_RDSVL = 863
+AARCH64_INS_RDVL = 864
+AARCH64_INS_RET = 865
+AARCH64_INS_RETAA = 866
+AARCH64_INS_RETAASPPC = 867
+AARCH64_INS_RETAB = 868
+AARCH64_INS_RETABSPPC = 869
+AARCH64_INS_REV16 = 870
+AARCH64_INS_REV32 = 871
+AARCH64_INS_REV64 = 872
+AARCH64_INS_REVB = 873
+AARCH64_INS_REVD = 874
+AARCH64_INS_REVH = 875
+AARCH64_INS_REVW = 876
+AARCH64_INS_REV = 877
+AARCH64_INS_RMIF = 878
+AARCH64_INS_ROR = 879
+AARCH64_INS_RPRFM = 880
+AARCH64_INS_RSHRNB = 881
+AARCH64_INS_RSHRNT = 882
+AARCH64_INS_RSHRN2 = 883
+AARCH64_INS_RSHRN = 884
+AARCH64_INS_RSUBHNB = 885
+AARCH64_INS_RSUBHNT = 886
+AARCH64_INS_RSUBHN = 887
+AARCH64_INS_RSUBHN2 = 888
+AARCH64_INS_SABALB = 889
+AARCH64_INS_SABALT = 890
+AARCH64_INS_SABAL2 = 891
+AARCH64_INS_SABAL = 892
+AARCH64_INS_SABA = 893
+AARCH64_INS_SABDLB = 894
+AARCH64_INS_SABDLT = 895
+AARCH64_INS_SABDL2 = 896
+AARCH64_INS_SABDL = 897
+AARCH64_INS_SABD = 898
+AARCH64_INS_SADALP = 899
+AARCH64_INS_SADDLBT = 900
+AARCH64_INS_SADDLB = 901
+AARCH64_INS_SADDLP = 902
+AARCH64_INS_SADDLT = 903
+AARCH64_INS_SADDLV = 904
+AARCH64_INS_SADDL2 = 905
+AARCH64_INS_SADDL = 906
+AARCH64_INS_SADDV = 907
+AARCH64_INS_SADDWB = 908
+AARCH64_INS_SADDWT = 909
+AARCH64_INS_SADDW2 = 910
+AARCH64_INS_SADDW = 911
+AARCH64_INS_SB = 912
+AARCH64_INS_SBCLB = 913
+AARCH64_INS_SBCLT = 914
+AARCH64_INS_SBCS = 915
+AARCH64_INS_SBC = 916
+AARCH64_INS_SBFM = 917
+AARCH64_INS_SCLAMP = 918
+AARCH64_INS_SCVTF = 919
+AARCH64_INS_SDIVR = 920
+AARCH64_INS_SDIV = 921
+AARCH64_INS_SDOT = 922
+AARCH64_INS_SEL = 923
+AARCH64_INS_SETE = 924
+AARCH64_INS_SETEN = 925
+AARCH64_INS_SETET = 926
+AARCH64_INS_SETETN = 927
+AARCH64_INS_SETF16 = 928
+AARCH64_INS_SETF8 = 929
+AARCH64_INS_SETFFR = 930
+AARCH64_INS_SETGM = 931
+AARCH64_INS_SETGMN = 932
+AARCH64_INS_SETGMT = 933
+AARCH64_INS_SETGMTN = 934
+AARCH64_INS_SETGP = 935
+AARCH64_INS_SETGPN = 936
+AARCH64_INS_SETGPT = 937
+AARCH64_INS_SETGPTN = 938
+AARCH64_INS_SETM = 939
+AARCH64_INS_SETMN = 940
+AARCH64_INS_SETMT = 941
+AARCH64_INS_SETMTN = 942
+AARCH64_INS_SETP = 943
+AARCH64_INS_SETPN = 944
+AARCH64_INS_SETPT = 945
+AARCH64_INS_SETPTN = 946
+AARCH64_INS_SHA1C = 947
+AARCH64_INS_SHA1H = 948
+AARCH64_INS_SHA1M = 949
+AARCH64_INS_SHA1P = 950
+AARCH64_INS_SHA1SU0 = 951
+AARCH64_INS_SHA1SU1 = 952
+AARCH64_INS_SHA256H2 = 953
+AARCH64_INS_SHA256H = 954
+AARCH64_INS_SHA256SU0 = 955
+AARCH64_INS_SHA256SU1 = 956
+AARCH64_INS_SHA512H = 957
+AARCH64_INS_SHA512H2 = 958
+AARCH64_INS_SHA512SU0 = 959
+AARCH64_INS_SHA512SU1 = 960
+AARCH64_INS_SHADD = 961
+AARCH64_INS_SHLL2 = 962
+AARCH64_INS_SHLL = 963
+AARCH64_INS_SHL = 964
+AARCH64_INS_SHRNB = 965
+AARCH64_INS_SHRNT = 966
+AARCH64_INS_SHRN2 = 967
+AARCH64_INS_SHRN = 968
+AARCH64_INS_SHSUBR = 969
+AARCH64_INS_SHSUB = 970
+AARCH64_INS_SLI = 971
+AARCH64_INS_SM3PARTW1 = 972
+AARCH64_INS_SM3PARTW2 = 973
+AARCH64_INS_SM3SS1 = 974
+AARCH64_INS_SM3TT1A = 975
+AARCH64_INS_SM3TT1B = 976
+AARCH64_INS_SM3TT2A = 977
+AARCH64_INS_SM3TT2B = 978
+AARCH64_INS_SM4E = 979
+AARCH64_INS_SM4EKEY = 980
+AARCH64_INS_SMADDL = 981
+AARCH64_INS_SMAXP = 982
+AARCH64_INS_SMAXQV = 983
+AARCH64_INS_SMAXV = 984
+AARCH64_INS_SMAX = 985
+AARCH64_INS_SMC = 986
+AARCH64_INS_SMINP = 987
+AARCH64_INS_SMINQV = 988
+AARCH64_INS_SMINV = 989
+AARCH64_INS_SMIN = 990
+AARCH64_INS_SMLALB = 991
+AARCH64_INS_SMLALL = 992
+AARCH64_INS_SMLALT = 993
+AARCH64_INS_SMLAL = 994
+AARCH64_INS_SMLAL2 = 995
+AARCH64_INS_SMLSLB = 996
+AARCH64_INS_SMLSLL = 997
+AARCH64_INS_SMLSLT = 998
+AARCH64_INS_SMLSL = 999
+AARCH64_INS_SMLSL2 = 1000
+AARCH64_INS_SMMLA = 1001
+AARCH64_INS_SMOPA = 1002
+AARCH64_INS_SMOPS = 1003
+AARCH64_INS_SMOV = 1004
+AARCH64_INS_SMSUBL = 1005
+AARCH64_INS_SMULH = 1006
+AARCH64_INS_SMULLB = 1007
+AARCH64_INS_SMULLT = 1008
+AARCH64_INS_SMULL2 = 1009
+AARCH64_INS_SMULL = 1010
+AARCH64_INS_SPLICE = 1011
+AARCH64_INS_SQABS = 1012
+AARCH64_INS_SQADD = 1013
+AARCH64_INS_SQCADD = 1014
+AARCH64_INS_SQCVTN = 1015
+AARCH64_INS_SQCVTUN = 1016
+AARCH64_INS_SQCVTU = 1017
+AARCH64_INS_SQCVT = 1018
+AARCH64_INS_SQDECB = 1019
+AARCH64_INS_SQDECD = 1020
+AARCH64_INS_SQDECH = 1021
+AARCH64_INS_SQDECP = 1022
+AARCH64_INS_SQDECW = 1023
+AARCH64_INS_SQDMLALBT = 1024
+AARCH64_INS_SQDMLALB = 1025
+AARCH64_INS_SQDMLALT = 1026
+AARCH64_INS_SQDMLAL = 1027
+AARCH64_INS_SQDMLAL2 = 1028
+AARCH64_INS_SQDMLSLBT = 1029
+AARCH64_INS_SQDMLSLB = 1030
+AARCH64_INS_SQDMLSLT = 1031
+AARCH64_INS_SQDMLSL = 1032
+AARCH64_INS_SQDMLSL2 = 1033
+AARCH64_INS_SQDMULH = 1034
+AARCH64_INS_SQDMULLB = 1035
+AARCH64_INS_SQDMULLT = 1036
+AARCH64_INS_SQDMULL = 1037
+AARCH64_INS_SQDMULL2 = 1038
+AARCH64_INS_SQINCB = 1039
+AARCH64_INS_SQINCD = 1040
+AARCH64_INS_SQINCH = 1041
+AARCH64_INS_SQINCP = 1042
+AARCH64_INS_SQINCW = 1043
+AARCH64_INS_SQNEG = 1044
+AARCH64_INS_SQRDCMLAH = 1045
+AARCH64_INS_SQRDMLAH = 1046
+AARCH64_INS_SQRDMLSH = 1047
+AARCH64_INS_SQRDMULH = 1048
+AARCH64_INS_SQRSHLR = 1049
+AARCH64_INS_SQRSHL = 1050
+AARCH64_INS_SQRSHRNB = 1051
+AARCH64_INS_SQRSHRNT = 1052
+AARCH64_INS_SQRSHRN = 1053
+AARCH64_INS_SQRSHRN2 = 1054
+AARCH64_INS_SQRSHRUNB = 1055
+AARCH64_INS_SQRSHRUNT = 1056
+AARCH64_INS_SQRSHRUN = 1057
+AARCH64_INS_SQRSHRUN2 = 1058
+AARCH64_INS_SQRSHRU = 1059
+AARCH64_INS_SQRSHR = 1060
+AARCH64_INS_SQSHLR = 1061
+AARCH64_INS_SQSHLU = 1062
+AARCH64_INS_SQSHL = 1063
+AARCH64_INS_SQSHRNB = 1064
+AARCH64_INS_SQSHRNT = 1065
+AARCH64_INS_SQSHRN = 1066
+AARCH64_INS_SQSHRN2 = 1067
+AARCH64_INS_SQSHRUNB = 1068
+AARCH64_INS_SQSHRUNT = 1069
+AARCH64_INS_SQSHRUN = 1070
+AARCH64_INS_SQSHRUN2 = 1071
+AARCH64_INS_SQSUBR = 1072
+AARCH64_INS_SQSUB = 1073
+AARCH64_INS_SQXTNB = 1074
+AARCH64_INS_SQXTNT = 1075
+AARCH64_INS_SQXTN2 = 1076
+AARCH64_INS_SQXTN = 1077
+AARCH64_INS_SQXTUNB = 1078
+AARCH64_INS_SQXTUNT = 1079
+AARCH64_INS_SQXTUN2 = 1080
+AARCH64_INS_SQXTUN = 1081
+AARCH64_INS_SRHADD = 1082
+AARCH64_INS_SRI = 1083
+AARCH64_INS_SRSHLR = 1084
+AARCH64_INS_SRSHL = 1085
+AARCH64_INS_SRSHR = 1086
+AARCH64_INS_SRSRA = 1087
+AARCH64_INS_SSHLLB = 1088
+AARCH64_INS_SSHLLT = 1089
+AARCH64_INS_SSHLL2 = 1090
+AARCH64_INS_SSHLL = 1091
+AARCH64_INS_SSHL = 1092
+AARCH64_INS_SSHR = 1093
+AARCH64_INS_SSRA = 1094
+AARCH64_INS_ST1B = 1095
+AARCH64_INS_ST1D = 1096
+AARCH64_INS_ST1H = 1097
+AARCH64_INS_ST1Q = 1098
+AARCH64_INS_ST1W = 1099
+AARCH64_INS_SSUBLBT = 1100
+AARCH64_INS_SSUBLB = 1101
+AARCH64_INS_SSUBLTB = 1102
+AARCH64_INS_SSUBLT = 1103
+AARCH64_INS_SSUBL2 = 1104
+AARCH64_INS_SSUBL = 1105
+AARCH64_INS_SSUBWB = 1106
+AARCH64_INS_SSUBWT = 1107
+AARCH64_INS_SSUBW2 = 1108
+AARCH64_INS_SSUBW = 1109
+AARCH64_INS_ST1 = 1110
+AARCH64_INS_ST2B = 1111
+AARCH64_INS_ST2D = 1112
+AARCH64_INS_ST2G = 1113
+AARCH64_INS_ST2H = 1114
+AARCH64_INS_ST2Q = 1115
+AARCH64_INS_ST2 = 1116
+AARCH64_INS_ST2W = 1117
+AARCH64_INS_ST3B = 1118
+AARCH64_INS_ST3D = 1119
+AARCH64_INS_ST3H = 1120
+AARCH64_INS_ST3Q = 1121
+AARCH64_INS_ST3 = 1122
+AARCH64_INS_ST3W = 1123
+AARCH64_INS_ST4B = 1124
+AARCH64_INS_ST4D = 1125
+AARCH64_INS_ST4 = 1126
+AARCH64_INS_ST4H = 1127
+AARCH64_INS_ST4Q = 1128
+AARCH64_INS_ST4W = 1129
+AARCH64_INS_ST64B = 1130
+AARCH64_INS_ST64BV = 1131
+AARCH64_INS_ST64BV0 = 1132
+AARCH64_INS_STGM = 1133
+AARCH64_INS_STGP = 1134
+AARCH64_INS_STG = 1135
+AARCH64_INS_STILP = 1136
+AARCH64_INS_STL1 = 1137
+AARCH64_INS_STLLRB = 1138
+AARCH64_INS_STLLRH = 1139
+AARCH64_INS_STLLR = 1140
+AARCH64_INS_STLRB = 1141
+AARCH64_INS_STLRH = 1142
+AARCH64_INS_STLR = 1143
+AARCH64_INS_STLURB = 1144
+AARCH64_INS_STLURH = 1145
+AARCH64_INS_STLUR = 1146
+AARCH64_INS_STLXP = 1147
+AARCH64_INS_STLXRB = 1148
+AARCH64_INS_STLXRH = 1149
+AARCH64_INS_STLXR = 1150
+AARCH64_INS_STNP = 1151
+AARCH64_INS_STNT1B = 1152
+AARCH64_INS_STNT1D = 1153
+AARCH64_INS_STNT1H = 1154
+AARCH64_INS_STNT1W = 1155
+AARCH64_INS_STP = 1156
+AARCH64_INS_STRB = 1157
+AARCH64_INS_STR = 1158
+AARCH64_INS_STRH = 1159
+AARCH64_INS_STTRB = 1160
+AARCH64_INS_STTRH = 1161
+AARCH64_INS_STTR = 1162
+AARCH64_INS_STURB = 1163
+AARCH64_INS_STUR = 1164
+AARCH64_INS_STURH = 1165
+AARCH64_INS_STXP = 1166
+AARCH64_INS_STXRB = 1167
+AARCH64_INS_STXRH = 1168
+AARCH64_INS_STXR = 1169
+AARCH64_INS_STZ2G = 1170
+AARCH64_INS_STZGM = 1171
+AARCH64_INS_STZG = 1172
+AARCH64_INS_SUBG = 1173
+AARCH64_INS_SUBHNB = 1174
+AARCH64_INS_SUBHNT = 1175
+AARCH64_INS_SUBHN = 1176
+AARCH64_INS_SUBHN2 = 1177
+AARCH64_INS_SUBP = 1178
+AARCH64_INS_SUBPS = 1179
+AARCH64_INS_SUBPT = 1180
+AARCH64_INS_SUBR = 1181
+AARCH64_INS_SUBS = 1182
+AARCH64_INS_SUB = 1183
+AARCH64_INS_SUDOT = 1184
+AARCH64_INS_SUMLALL = 1185
+AARCH64_INS_SUMOPA = 1186
+AARCH64_INS_SUMOPS = 1187
+AARCH64_INS_SUNPKHI = 1188
+AARCH64_INS_SUNPKLO = 1189
+AARCH64_INS_SUNPK = 1190
+AARCH64_INS_SUQADD = 1191
+AARCH64_INS_SUVDOT = 1192
+AARCH64_INS_SVC = 1193
+AARCH64_INS_SVDOT = 1194
+AARCH64_INS_SWPAB = 1195
+AARCH64_INS_SWPAH = 1196
+AARCH64_INS_SWPALB = 1197
+AARCH64_INS_SWPALH = 1198
+AARCH64_INS_SWPAL = 1199
+AARCH64_INS_SWPA = 1200
+AARCH64_INS_SWPB = 1201
+AARCH64_INS_SWPH = 1202
+AARCH64_INS_SWPLB = 1203
+AARCH64_INS_SWPLH = 1204
+AARCH64_INS_SWPL = 1205
+AARCH64_INS_SWPP = 1206
+AARCH64_INS_SWPPA = 1207
+AARCH64_INS_SWPPAL = 1208
+AARCH64_INS_SWPPL = 1209
+AARCH64_INS_SWP = 1210
+AARCH64_INS_SXTB = 1211
+AARCH64_INS_SXTH = 1212
+AARCH64_INS_SXTW = 1213
+AARCH64_INS_SYSL = 1214
+AARCH64_INS_SYSP = 1215
+AARCH64_INS_SYS = 1216
+AARCH64_INS_TBLQ = 1217
+AARCH64_INS_TBL = 1218
+AARCH64_INS_TBNZ = 1219
+AARCH64_INS_TBXQ = 1220
+AARCH64_INS_TBX = 1221
+AARCH64_INS_TBZ = 1222
+AARCH64_INS_TCANCEL = 1223
+AARCH64_INS_TCOMMIT = 1224
+AARCH64_INS_TRCIT = 1225
+AARCH64_INS_TRN1 = 1226
+AARCH64_INS_TRN2 = 1227
+AARCH64_INS_TSB = 1228
+AARCH64_INS_TSTART = 1229
+AARCH64_INS_TTEST = 1230
+AARCH64_INS_UABALB = 1231
+AARCH64_INS_UABALT = 1232
+AARCH64_INS_UABAL2 = 1233
+AARCH64_INS_UABAL = 1234
+AARCH64_INS_UABA = 1235
+AARCH64_INS_UABDLB = 1236
+AARCH64_INS_UABDLT = 1237
+AARCH64_INS_UABDL2 = 1238
+AARCH64_INS_UABDL = 1239
+AARCH64_INS_UABD = 1240
+AARCH64_INS_UADALP = 1241
+AARCH64_INS_UADDLB = 1242
+AARCH64_INS_UADDLP = 1243
+AARCH64_INS_UADDLT = 1244
+AARCH64_INS_UADDLV = 1245
+AARCH64_INS_UADDL2 = 1246
+AARCH64_INS_UADDL = 1247
+AARCH64_INS_UADDV = 1248
+AARCH64_INS_UADDWB = 1249
+AARCH64_INS_UADDWT = 1250
+AARCH64_INS_UADDW2 = 1251
+AARCH64_INS_UADDW = 1252
+AARCH64_INS_UBFM = 1253
+AARCH64_INS_UCLAMP = 1254
+AARCH64_INS_UCVTF = 1255
+AARCH64_INS_UDF = 1256
+AARCH64_INS_UDIVR = 1257
+AARCH64_INS_UDIV = 1258
+AARCH64_INS_UDOT = 1259
+AARCH64_INS_UHADD = 1260
+AARCH64_INS_UHSUBR = 1261
+AARCH64_INS_UHSUB = 1262
+AARCH64_INS_UMADDL = 1263
+AARCH64_INS_UMAXP = 1264
+AARCH64_INS_UMAXQV = 1265
+AARCH64_INS_UMAXV = 1266
+AARCH64_INS_UMAX = 1267
+AARCH64_INS_UMINP = 1268
+AARCH64_INS_UMINQV = 1269
+AARCH64_INS_UMINV = 1270
+AARCH64_INS_UMIN = 1271
+AARCH64_INS_UMLALB = 1272
+AARCH64_INS_UMLALL = 1273
+AARCH64_INS_UMLALT = 1274
+AARCH64_INS_UMLAL = 1275
+AARCH64_INS_UMLAL2 = 1276
+AARCH64_INS_UMLSLB = 1277
+AARCH64_INS_UMLSLL = 1278
+AARCH64_INS_UMLSLT = 1279
+AARCH64_INS_UMLSL = 1280
+AARCH64_INS_UMLSL2 = 1281
+AARCH64_INS_UMMLA = 1282
+AARCH64_INS_UMOPA = 1283
+AARCH64_INS_UMOPS = 1284
+AARCH64_INS_UMOV = 1285
+AARCH64_INS_UMSUBL = 1286
+AARCH64_INS_UMULH = 1287
+AARCH64_INS_UMULLB = 1288
+AARCH64_INS_UMULLT = 1289
+AARCH64_INS_UMULL2 = 1290
+AARCH64_INS_UMULL = 1291
+AARCH64_INS_UQADD = 1292
+AARCH64_INS_UQCVTN = 1293
+AARCH64_INS_UQCVT = 1294
+AARCH64_INS_UQDECB = 1295
+AARCH64_INS_UQDECD = 1296
+AARCH64_INS_UQDECH = 1297
+AARCH64_INS_UQDECP = 1298
+AARCH64_INS_UQDECW = 1299
+AARCH64_INS_UQINCB = 1300
+AARCH64_INS_UQINCD = 1301
+AARCH64_INS_UQINCH = 1302
+AARCH64_INS_UQINCP = 1303
+AARCH64_INS_UQINCW = 1304
+AARCH64_INS_UQRSHLR = 1305
+AARCH64_INS_UQRSHL = 1306
+AARCH64_INS_UQRSHRNB = 1307
+AARCH64_INS_UQRSHRNT = 1308
+AARCH64_INS_UQRSHRN = 1309
+AARCH64_INS_UQRSHRN2 = 1310
+AARCH64_INS_UQRSHR = 1311
+AARCH64_INS_UQSHLR = 1312
+AARCH64_INS_UQSHL = 1313
+AARCH64_INS_UQSHRNB = 1314
+AARCH64_INS_UQSHRNT = 1315
+AARCH64_INS_UQSHRN = 1316
+AARCH64_INS_UQSHRN2 = 1317
+AARCH64_INS_UQSUBR = 1318
+AARCH64_INS_UQSUB = 1319
+AARCH64_INS_UQXTNB = 1320
+AARCH64_INS_UQXTNT = 1321
+AARCH64_INS_UQXTN2 = 1322
+AARCH64_INS_UQXTN = 1323
+AARCH64_INS_URECPE = 1324
+AARCH64_INS_URHADD = 1325
+AARCH64_INS_URSHLR = 1326
+AARCH64_INS_URSHL = 1327
+AARCH64_INS_URSHR = 1328
+AARCH64_INS_URSQRTE = 1329
+AARCH64_INS_URSRA = 1330
+AARCH64_INS_USDOT = 1331
+AARCH64_INS_USHLLB = 1332
+AARCH64_INS_USHLLT = 1333
+AARCH64_INS_USHLL2 = 1334
+AARCH64_INS_USHLL = 1335
+AARCH64_INS_USHL = 1336
+AARCH64_INS_USHR = 1337
+AARCH64_INS_USMLALL = 1338
+AARCH64_INS_USMMLA = 1339
+AARCH64_INS_USMOPA = 1340
+AARCH64_INS_USMOPS = 1341
+AARCH64_INS_USQADD = 1342
+AARCH64_INS_USRA = 1343
+AARCH64_INS_USUBLB = 1344
+AARCH64_INS_USUBLT = 1345
+AARCH64_INS_USUBL2 = 1346
+AARCH64_INS_USUBL = 1347
+AARCH64_INS_USUBWB = 1348
+AARCH64_INS_USUBWT = 1349
+AARCH64_INS_USUBW2 = 1350
+AARCH64_INS_USUBW = 1351
+AARCH64_INS_USVDOT = 1352
+AARCH64_INS_UUNPKHI = 1353
+AARCH64_INS_UUNPKLO = 1354
+AARCH64_INS_UUNPK = 1355
+AARCH64_INS_UVDOT = 1356
+AARCH64_INS_UXTB = 1357
+AARCH64_INS_UXTH = 1358
+AARCH64_INS_UXTW = 1359
+AARCH64_INS_UZP1 = 1360
+AARCH64_INS_UZP2 = 1361
+AARCH64_INS_UZPQ1 = 1362
+AARCH64_INS_UZPQ2 = 1363
+AARCH64_INS_UZP = 1364
+AARCH64_INS_WFET = 1365
+AARCH64_INS_WFIT = 1366
+AARCH64_INS_WHILEGE = 1367
+AARCH64_INS_WHILEGT = 1368
+AARCH64_INS_WHILEHI = 1369
+AARCH64_INS_WHILEHS = 1370
+AARCH64_INS_WHILELE = 1371
+AARCH64_INS_WHILELO = 1372
+AARCH64_INS_WHILELS = 1373
+AARCH64_INS_WHILELT = 1374
+AARCH64_INS_WHILERW = 1375
+AARCH64_INS_WHILEWR = 1376
+AARCH64_INS_WRFFR = 1377
+AARCH64_INS_XAFLAG = 1378
+AARCH64_INS_XAR = 1379
+AARCH64_INS_XPACD = 1380
+AARCH64_INS_XPACI = 1381
+AARCH64_INS_XTN2 = 1382
+AARCH64_INS_XTN = 1383
+AARCH64_INS_ZERO = 1384
+AARCH64_INS_ZIP1 = 1385
+AARCH64_INS_ZIP2 = 1386
+AARCH64_INS_ZIPQ1 = 1387
+AARCH64_INS_ZIPQ2 = 1388
+AARCH64_INS_ZIP = 1389
+AARCH64_INS_ENDING = 1390
+AARCH64_INS_ALIAS_BEGIN = 1391
+AARCH64_INS_ALIAS_ADDPT = 1392
+AARCH64_INS_ALIAS_GCSB = 1393
+AARCH64_INS_ALIAS_GCSPOPM = 1394
+AARCH64_INS_ALIAS_LDAPUR = 1395
+AARCH64_INS_ALIAS_STLLRB = 1396
+AARCH64_INS_ALIAS_STLLRH = 1397
+AARCH64_INS_ALIAS_STLLR = 1398
+AARCH64_INS_ALIAS_STLRB = 1399
+AARCH64_INS_ALIAS_STLRH = 1400
+AARCH64_INS_ALIAS_STLR = 1401
+AARCH64_INS_ALIAS_STLUR = 1402
+AARCH64_INS_ALIAS_SUBPT = 1403
+AARCH64_INS_ALIAS_LDRAA = 1404
+AARCH64_INS_ALIAS_ADD = 1405
+AARCH64_INS_ALIAS_CMN = 1406
+AARCH64_INS_ALIAS_ADDS = 1407
+AARCH64_INS_ALIAS_AND = 1408
+AARCH64_INS_ALIAS_ANDS = 1409
+AARCH64_INS_ALIAS_LDR = 1410
+AARCH64_INS_ALIAS_STR = 1411
+AARCH64_INS_ALIAS_LDRB = 1412
+AARCH64_INS_ALIAS_STRB = 1413
+AARCH64_INS_ALIAS_LDRH = 1414
+AARCH64_INS_ALIAS_STRH = 1415
+AARCH64_INS_ALIAS_PRFM = 1416
+AARCH64_INS_ALIAS_LDAPURB = 1417
+AARCH64_INS_ALIAS_STLURB = 1418
+AARCH64_INS_ALIAS_LDUR = 1419
+AARCH64_INS_ALIAS_STUR = 1420
+AARCH64_INS_ALIAS_PRFUM = 1421
+AARCH64_INS_ALIAS_LDTR = 1422
+AARCH64_INS_ALIAS_STTR = 1423
+AARCH64_INS_ALIAS_LDP = 1424
+AARCH64_INS_ALIAS_STGP = 1425
+AARCH64_INS_ALIAS_LDNP = 1426
+AARCH64_INS_ALIAS_STNP = 1427
+AARCH64_INS_ALIAS_STG = 1428
+AARCH64_INS_ALIAS_MOV = 1429
+AARCH64_INS_ALIAS_LD1 = 1430
+AARCH64_INS_ALIAS_LD1R = 1431
+AARCH64_INS_ALIAS_STADDLB = 1432
+AARCH64_INS_ALIAS_STADDLH = 1433
+AARCH64_INS_ALIAS_STADDL = 1434
+AARCH64_INS_ALIAS_STADDB = 1435
+AARCH64_INS_ALIAS_STADDH = 1436
+AARCH64_INS_ALIAS_STADD = 1437
+AARCH64_INS_ALIAS_PTRUE = 1438
+AARCH64_INS_ALIAS_PTRUES = 1439
+AARCH64_INS_ALIAS_CNTB = 1440
+AARCH64_INS_ALIAS_SQINCH = 1441
+AARCH64_INS_ALIAS_INCB = 1442
+AARCH64_INS_ALIAS_SQINCB = 1443
+AARCH64_INS_ALIAS_UQINCB = 1444
+AARCH64_INS_ALIAS_ORR = 1445
+AARCH64_INS_ALIAS_DUPM = 1446
+AARCH64_INS_ALIAS_FMOV = 1447
+AARCH64_INS_ALIAS_EOR3 = 1448
+AARCH64_INS_ALIAS_ST1B = 1449
+AARCH64_INS_ALIAS_ST2B = 1450
+AARCH64_INS_ALIAS_ST2Q = 1451
+AARCH64_INS_ALIAS_STNT1B = 1452
+AARCH64_INS_ALIAS_LD1B = 1453
+AARCH64_INS_ALIAS_LDNT1B = 1454
+AARCH64_INS_ALIAS_LD1RQB = 1455
+AARCH64_INS_ALIAS_LD1RB = 1456
+AARCH64_INS_ALIAS_LDFF1B = 1457
+AARCH64_INS_ALIAS_LDNF1B = 1458
+AARCH64_INS_ALIAS_LD2B = 1459
+AARCH64_INS_ALIAS_LD1SB = 1460
+AARCH64_INS_ALIAS_PRFB = 1461
+AARCH64_INS_ALIAS_LDNT1SB = 1462
+AARCH64_INS_ALIAS_LD1ROB = 1463
+AARCH64_INS_ALIAS_LD1Q = 1464
+AARCH64_INS_ALIAS_ST1Q = 1465
+AARCH64_INS_ALIAS_LD1W = 1466
+AARCH64_INS_ALIAS_PMOV = 1467
+AARCH64_INS_ALIAS_SMSTART = 1468
+AARCH64_INS_ALIAS_SMSTOP = 1469
+AARCH64_INS_ALIAS_ZERO = 1470
+AARCH64_INS_ALIAS_MOVT = 1471
+AARCH64_INS_ALIAS_NOP = 1472
+AARCH64_INS_ALIAS_YIELD = 1473
+AARCH64_INS_ALIAS_WFE = 1474
+AARCH64_INS_ALIAS_WFI = 1475
+AARCH64_INS_ALIAS_SEV = 1476
+AARCH64_INS_ALIAS_SEVL = 1477
+AARCH64_INS_ALIAS_DGH = 1478
+AARCH64_INS_ALIAS_ESB = 1479
+AARCH64_INS_ALIAS_CSDB = 1480
+AARCH64_INS_ALIAS_BTI = 1481
+AARCH64_INS_ALIAS_PSB = 1482
+AARCH64_INS_ALIAS_CHKFEAT = 1483
+AARCH64_INS_ALIAS_PACIAZ = 1484
+AARCH64_INS_ALIAS_PACIBZ = 1485
+AARCH64_INS_ALIAS_AUTIAZ = 1486
+AARCH64_INS_ALIAS_AUTIBZ = 1487
+AARCH64_INS_ALIAS_PACIASP = 1488
+AARCH64_INS_ALIAS_PACIBSP = 1489
+AARCH64_INS_ALIAS_AUTIASP = 1490
+AARCH64_INS_ALIAS_AUTIBSP = 1491
+AARCH64_INS_ALIAS_PACIA1716 = 1492
+AARCH64_INS_ALIAS_PACIB1716 = 1493
+AARCH64_INS_ALIAS_AUTIA1716 = 1494
+AARCH64_INS_ALIAS_AUTIB1716 = 1495
+AARCH64_INS_ALIAS_XPACLRI = 1496
+AARCH64_INS_ALIAS_LDRAB = 1497
+AARCH64_INS_ALIAS_PACM = 1498
+AARCH64_INS_ALIAS_CLREX = 1499
+AARCH64_INS_ALIAS_ISB = 1500
+AARCH64_INS_ALIAS_SSBB = 1501
+AARCH64_INS_ALIAS_PSSBB = 1502
+AARCH64_INS_ALIAS_DFB = 1503
+AARCH64_INS_ALIAS_SYS = 1504
+AARCH64_INS_ALIAS_MOVN = 1505
+AARCH64_INS_ALIAS_MOVZ = 1506
+AARCH64_INS_ALIAS_NGC = 1507
+AARCH64_INS_ALIAS_NGCS = 1508
+AARCH64_INS_ALIAS_SUB = 1509
+AARCH64_INS_ALIAS_CMP = 1510
+AARCH64_INS_ALIAS_SUBS = 1511
+AARCH64_INS_ALIAS_NEG = 1512
+AARCH64_INS_ALIAS_NEGS = 1513
+AARCH64_INS_ALIAS_MUL = 1514
+AARCH64_INS_ALIAS_MNEG = 1515
+AARCH64_INS_ALIAS_SMULL = 1516
+AARCH64_INS_ALIAS_SMNEGL = 1517
+AARCH64_INS_ALIAS_UMULL = 1518
+AARCH64_INS_ALIAS_UMNEGL = 1519
+AARCH64_INS_ALIAS_STCLRLB = 1520
+AARCH64_INS_ALIAS_STCLRLH = 1521
+AARCH64_INS_ALIAS_STCLRL = 1522
+AARCH64_INS_ALIAS_STCLRB = 1523
+AARCH64_INS_ALIAS_STCLRH = 1524
+AARCH64_INS_ALIAS_STCLR = 1525
+AARCH64_INS_ALIAS_STEORLB = 1526
+AARCH64_INS_ALIAS_STEORLH = 1527
+AARCH64_INS_ALIAS_STEORL = 1528
+AARCH64_INS_ALIAS_STEORB = 1529
+AARCH64_INS_ALIAS_STEORH = 1530
+AARCH64_INS_ALIAS_STEOR = 1531
+AARCH64_INS_ALIAS_STSETLB = 1532
+AARCH64_INS_ALIAS_STSETLH = 1533
+AARCH64_INS_ALIAS_STSETL = 1534
+AARCH64_INS_ALIAS_STSETB = 1535
+AARCH64_INS_ALIAS_STSETH = 1536
+AARCH64_INS_ALIAS_STSET = 1537
+AARCH64_INS_ALIAS_STSMAXLB = 1538
+AARCH64_INS_ALIAS_STSMAXLH = 1539
+AARCH64_INS_ALIAS_STSMAXL = 1540
+AARCH64_INS_ALIAS_STSMAXB = 1541
+AARCH64_INS_ALIAS_STSMAXH = 1542
+AARCH64_INS_ALIAS_STSMAX = 1543
+AARCH64_INS_ALIAS_STSMINLB = 1544
+AARCH64_INS_ALIAS_STSMINLH = 1545
+AARCH64_INS_ALIAS_STSMINL = 1546
+AARCH64_INS_ALIAS_STSMINB = 1547
+AARCH64_INS_ALIAS_STSMINH = 1548
+AARCH64_INS_ALIAS_STSMIN = 1549
+AARCH64_INS_ALIAS_STUMAXLB = 1550
+AARCH64_INS_ALIAS_STUMAXLH = 1551
+AARCH64_INS_ALIAS_STUMAXL = 1552
+AARCH64_INS_ALIAS_STUMAXB = 1553
+AARCH64_INS_ALIAS_STUMAXH = 1554
+AARCH64_INS_ALIAS_STUMAX = 1555
+AARCH64_INS_ALIAS_STUMINLB = 1556
+AARCH64_INS_ALIAS_STUMINLH = 1557
+AARCH64_INS_ALIAS_STUMINL = 1558
+AARCH64_INS_ALIAS_STUMINB = 1559
+AARCH64_INS_ALIAS_STUMINH = 1560
+AARCH64_INS_ALIAS_STUMIN = 1561
+AARCH64_INS_ALIAS_IRG = 1562
+AARCH64_INS_ALIAS_LDG = 1563
+AARCH64_INS_ALIAS_STZG = 1564
+AARCH64_INS_ALIAS_ST2G = 1565
+AARCH64_INS_ALIAS_STZ2G = 1566
+AARCH64_INS_ALIAS_BICS = 1567
+AARCH64_INS_ALIAS_BIC = 1568
+AARCH64_INS_ALIAS_EON = 1569
+AARCH64_INS_ALIAS_EOR = 1570
+AARCH64_INS_ALIAS_ORN = 1571
+AARCH64_INS_ALIAS_MVN = 1572
+AARCH64_INS_ALIAS_TST = 1573
+AARCH64_INS_ALIAS_ROR = 1574
+AARCH64_INS_ALIAS_ASR = 1575
+AARCH64_INS_ALIAS_SXTB = 1576
+AARCH64_INS_ALIAS_SXTH = 1577
+AARCH64_INS_ALIAS_SXTW = 1578
+AARCH64_INS_ALIAS_LSR = 1579
+AARCH64_INS_ALIAS_UXTB = 1580
+AARCH64_INS_ALIAS_UXTH = 1581
+AARCH64_INS_ALIAS_UXTW = 1582
+AARCH64_INS_ALIAS_CSET = 1583
+AARCH64_INS_ALIAS_CSETM = 1584
+AARCH64_INS_ALIAS_CINC = 1585
+AARCH64_INS_ALIAS_CINV = 1586
+AARCH64_INS_ALIAS_CNEG = 1587
+AARCH64_INS_ALIAS_RET = 1588
+AARCH64_INS_ALIAS_DCPS1 = 1589
+AARCH64_INS_ALIAS_DCPS2 = 1590
+AARCH64_INS_ALIAS_DCPS3 = 1591
+AARCH64_INS_ALIAS_LDPSW = 1592
+AARCH64_INS_ALIAS_LDRSH = 1593
+AARCH64_INS_ALIAS_LDRSB = 1594
+AARCH64_INS_ALIAS_LDRSW = 1595
+AARCH64_INS_ALIAS_LDURH = 1596
+AARCH64_INS_ALIAS_LDURB = 1597
+AARCH64_INS_ALIAS_LDURSH = 1598
+AARCH64_INS_ALIAS_LDURSB = 1599
+AARCH64_INS_ALIAS_LDURSW = 1600
+AARCH64_INS_ALIAS_LDTRH = 1601
+AARCH64_INS_ALIAS_LDTRB = 1602
+AARCH64_INS_ALIAS_LDTRSH = 1603
+AARCH64_INS_ALIAS_LDTRSB = 1604
+AARCH64_INS_ALIAS_LDTRSW = 1605
+AARCH64_INS_ALIAS_STP = 1606
+AARCH64_INS_ALIAS_STURH = 1607
+AARCH64_INS_ALIAS_STURB = 1608
+AARCH64_INS_ALIAS_STLURH = 1609
+AARCH64_INS_ALIAS_LDAPURSB = 1610
+AARCH64_INS_ALIAS_LDAPURH = 1611
+AARCH64_INS_ALIAS_LDAPURSH = 1612
+AARCH64_INS_ALIAS_LDAPURSW = 1613
+AARCH64_INS_ALIAS_STTRH = 1614
+AARCH64_INS_ALIAS_STTRB = 1615
+AARCH64_INS_ALIAS_BIC_4H = 1616
+AARCH64_INS_ALIAS_BIC_8H = 1617
+AARCH64_INS_ALIAS_BIC_2S = 1618
+AARCH64_INS_ALIAS_BIC_4S = 1619
+AARCH64_INS_ALIAS_ORR_4H = 1620
+AARCH64_INS_ALIAS_ORR_8H = 1621
+AARCH64_INS_ALIAS_ORR_2S = 1622
+AARCH64_INS_ALIAS_ORR_4S = 1623
+AARCH64_INS_ALIAS_SXTL_8H = 1624
+AARCH64_INS_ALIAS_SXTL = 1625
+AARCH64_INS_ALIAS_SXTL_4S = 1626
+AARCH64_INS_ALIAS_SXTL_2D = 1627
+AARCH64_INS_ALIAS_SXTL2_8H = 1628
+AARCH64_INS_ALIAS_SXTL2 = 1629
+AARCH64_INS_ALIAS_SXTL2_4S = 1630
+AARCH64_INS_ALIAS_SXTL2_2D = 1631
+AARCH64_INS_ALIAS_UXTL_8H = 1632
+AARCH64_INS_ALIAS_UXTL = 1633
+AARCH64_INS_ALIAS_UXTL_4S = 1634
+AARCH64_INS_ALIAS_UXTL_2D = 1635
+AARCH64_INS_ALIAS_UXTL2_8H = 1636
+AARCH64_INS_ALIAS_UXTL2 = 1637
+AARCH64_INS_ALIAS_UXTL2_4S = 1638
+AARCH64_INS_ALIAS_UXTL2_2D = 1639
+AARCH64_INS_ALIAS_LD2 = 1640
+AARCH64_INS_ALIAS_LD3 = 1641
+AARCH64_INS_ALIAS_LD4 = 1642
+AARCH64_INS_ALIAS_ST1 = 1643
+AARCH64_INS_ALIAS_ST2 = 1644
+AARCH64_INS_ALIAS_ST3 = 1645
+AARCH64_INS_ALIAS_ST4 = 1646
+AARCH64_INS_ALIAS_LD2R = 1647
+AARCH64_INS_ALIAS_LD3R = 1648
+AARCH64_INS_ALIAS_LD4R = 1649
+AARCH64_INS_ALIAS_CLRBHB = 1650
+AARCH64_INS_ALIAS_STILP = 1651
+AARCH64_INS_ALIAS_STL1 = 1652
+AARCH64_INS_ALIAS_SYSP = 1653
+AARCH64_INS_ALIAS_LD1SW = 1654
+AARCH64_INS_ALIAS_LD1H = 1655
+AARCH64_INS_ALIAS_LD1SH = 1656
+AARCH64_INS_ALIAS_LD1D = 1657
+AARCH64_INS_ALIAS_LD1RSW = 1658
+AARCH64_INS_ALIAS_LD1RH = 1659
+AARCH64_INS_ALIAS_LD1RSH = 1660
+AARCH64_INS_ALIAS_LD1RW = 1661
+AARCH64_INS_ALIAS_LD1RSB = 1662
+AARCH64_INS_ALIAS_LD1RD = 1663
+AARCH64_INS_ALIAS_LD1RQH = 1664
+AARCH64_INS_ALIAS_LD1RQW = 1665
+AARCH64_INS_ALIAS_LD1RQD = 1666
+AARCH64_INS_ALIAS_LDNF1SW = 1667
+AARCH64_INS_ALIAS_LDNF1H = 1668
+AARCH64_INS_ALIAS_LDNF1SH = 1669
+AARCH64_INS_ALIAS_LDNF1W = 1670
+AARCH64_INS_ALIAS_LDNF1SB = 1671
+AARCH64_INS_ALIAS_LDNF1D = 1672
+AARCH64_INS_ALIAS_LDFF1SW = 1673
+AARCH64_INS_ALIAS_LDFF1H = 1674
+AARCH64_INS_ALIAS_LDFF1SH = 1675
+AARCH64_INS_ALIAS_LDFF1W = 1676
+AARCH64_INS_ALIAS_LDFF1SB = 1677
+AARCH64_INS_ALIAS_LDFF1D = 1678
+AARCH64_INS_ALIAS_LD3B = 1679
+AARCH64_INS_ALIAS_LD4B = 1680
+AARCH64_INS_ALIAS_LD2H = 1681
+AARCH64_INS_ALIAS_LD3H = 1682
+AARCH64_INS_ALIAS_LD4H = 1683
+AARCH64_INS_ALIAS_LD2W = 1684
+AARCH64_INS_ALIAS_LD3W = 1685
+AARCH64_INS_ALIAS_LD4W = 1686
+AARCH64_INS_ALIAS_LD2D = 1687
+AARCH64_INS_ALIAS_LD3D = 1688
+AARCH64_INS_ALIAS_LD4D = 1689
+AARCH64_INS_ALIAS_LD2Q = 1690
+AARCH64_INS_ALIAS_LD3Q = 1691
+AARCH64_INS_ALIAS_LD4Q = 1692
+AARCH64_INS_ALIAS_LDNT1H = 1693
+AARCH64_INS_ALIAS_LDNT1W = 1694
+AARCH64_INS_ALIAS_LDNT1D = 1695
+AARCH64_INS_ALIAS_ST1H = 1696
+AARCH64_INS_ALIAS_ST1W = 1697
+AARCH64_INS_ALIAS_ST1D = 1698
+AARCH64_INS_ALIAS_ST3B = 1699
+AARCH64_INS_ALIAS_ST4B = 1700
+AARCH64_INS_ALIAS_ST2H = 1701
+AARCH64_INS_ALIAS_ST3H = 1702
+AARCH64_INS_ALIAS_ST4H = 1703
+AARCH64_INS_ALIAS_ST2W = 1704
+AARCH64_INS_ALIAS_ST3W = 1705
+AARCH64_INS_ALIAS_ST4W = 1706
+AARCH64_INS_ALIAS_ST2D = 1707
+AARCH64_INS_ALIAS_ST3D = 1708
+AARCH64_INS_ALIAS_ST4D = 1709
+AARCH64_INS_ALIAS_ST3Q = 1710
+AARCH64_INS_ALIAS_ST4Q = 1711
+AARCH64_INS_ALIAS_STNT1H = 1712
+AARCH64_INS_ALIAS_STNT1W = 1713
+AARCH64_INS_ALIAS_STNT1D = 1714
+AARCH64_INS_ALIAS_PRFH = 1715
+AARCH64_INS_ALIAS_PRFW = 1716
+AARCH64_INS_ALIAS_PRFD = 1717
+AARCH64_INS_ALIAS_CNTH = 1718
+AARCH64_INS_ALIAS_CNTW = 1719
+AARCH64_INS_ALIAS_CNTD = 1720
+AARCH64_INS_ALIAS_DECB = 1721
+AARCH64_INS_ALIAS_INCH = 1722
+AARCH64_INS_ALIAS_DECH = 1723
+AARCH64_INS_ALIAS_INCW = 1724
+AARCH64_INS_ALIAS_DECW = 1725
+AARCH64_INS_ALIAS_INCD = 1726
+AARCH64_INS_ALIAS_DECD = 1727
+AARCH64_INS_ALIAS_SQDECB = 1728
+AARCH64_INS_ALIAS_UQDECB = 1729
+AARCH64_INS_ALIAS_UQINCH = 1730
+AARCH64_INS_ALIAS_SQDECH = 1731
+AARCH64_INS_ALIAS_UQDECH = 1732
+AARCH64_INS_ALIAS_SQINCW = 1733
+AARCH64_INS_ALIAS_UQINCW = 1734
+AARCH64_INS_ALIAS_SQDECW = 1735
+AARCH64_INS_ALIAS_UQDECW = 1736
+AARCH64_INS_ALIAS_SQINCD = 1737
+AARCH64_INS_ALIAS_UQINCD = 1738
+AARCH64_INS_ALIAS_SQDECD = 1739
+AARCH64_INS_ALIAS_UQDECD = 1740
+AARCH64_INS_ALIAS_MOVS = 1741
+AARCH64_INS_ALIAS_NOT = 1742
+AARCH64_INS_ALIAS_NOTS = 1743
+AARCH64_INS_ALIAS_LD1ROH = 1744
+AARCH64_INS_ALIAS_LD1ROW = 1745
+AARCH64_INS_ALIAS_LD1ROD = 1746
+AARCH64_INS_ALIAS_BCAX = 1747
+AARCH64_INS_ALIAS_BSL = 1748
+AARCH64_INS_ALIAS_BSL1N = 1749
+AARCH64_INS_ALIAS_BSL2N = 1750
+AARCH64_INS_ALIAS_NBSL = 1751
+AARCH64_INS_ALIAS_LDNT1SH = 1752
+AARCH64_INS_ALIAS_LDNT1SW = 1753
+AARCH64_INS_ALIAS_CFP = 1754
+AARCH64_INS_ALIAS_DVP = 1755
+AARCH64_INS_ALIAS_COSP = 1756
+AARCH64_INS_ALIAS_CPP = 1757
+AARCH64_INS_ALIAS_IC = 1758
+AARCH64_INS_ALIAS_DC = 1759
+AARCH64_INS_ALIAS_AT = 1760
+AARCH64_INS_ALIAS_TLBI = 1761
+AARCH64_INS_ALIAS_TLBIP = 1762
+AARCH64_INS_ALIAS_RPRFM = 1763
+AARCH64_INS_ALIAS_LSL = 1764
+AARCH64_INS_ALIAS_SBFX = 1765
+AARCH64_INS_ALIAS_UBFX = 1766
+AARCH64_INS_ALIAS_SBFIZ = 1767
+AARCH64_INS_ALIAS_UBFIZ = 1768
+AARCH64_INS_ALIAS_BFC = 1769
+AARCH64_INS_ALIAS_BFI = 1770
+AARCH64_INS_ALIAS_BFXIL = 1771
+AARCH64_INS_ALIAS_END = 1772
 
 AARCH64_GRP_INVALID = 0
 AARCH64_GRP_JUMP = 1
diff --git a/bindings/python/capstone/alpha_const.py b/bindings/python/capstone/alpha_const.py
index 6cede6996..f6e5892fb 100644
--- a/bindings/python/capstone/alpha_const.py
+++ b/bindings/python/capstone/alpha_const.py
@@ -76,164 +76,166 @@ Alpha_REG_R31 = 64
 Alpha_REG_ENDING = 65
 
 # Alpha instruction
-Alpha_INS_INVALID = 66
-Alpha_INS_ADDL = 67
-Alpha_INS_ADDQ = 68
-Alpha_INS_ADDSsSU = 69
-Alpha_INS_ADDTsSU = 70
-Alpha_INS_AND = 71
-Alpha_INS_BEQ = 72
-Alpha_INS_BGE = 73
-Alpha_INS_BGT = 74
-Alpha_INS_BIC = 75
-Alpha_INS_BIS = 76
-Alpha_INS_BLBC = 77
-Alpha_INS_BLBS = 78
-Alpha_INS_BLE = 79
-Alpha_INS_BLT = 80
-Alpha_INS_BNE = 81
-Alpha_INS_BR = 82
-Alpha_INS_BSR = 83
-Alpha_INS_CMOVEQ = 84
-Alpha_INS_CMOVGE = 85
-Alpha_INS_CMOVGT = 86
-Alpha_INS_CMOVLBC = 87
-Alpha_INS_CMOVLBS = 88
-Alpha_INS_CMOVLE = 89
-Alpha_INS_CMOVLT = 90
-Alpha_INS_CMOVNE = 91
-Alpha_INS_CMPBGE = 92
-Alpha_INS_CMPEQ = 93
-Alpha_INS_CMPLE = 94
-Alpha_INS_CMPLT = 95
-Alpha_INS_CMPTEQsSU = 96
-Alpha_INS_CMPTLEsSU = 97
-Alpha_INS_CMPTLTsSU = 98
-Alpha_INS_CMPTUNsSU = 99
-Alpha_INS_CMPULE = 100
-Alpha_INS_CMPULT = 101
-Alpha_INS_COND_BRANCH = 102
-Alpha_INS_CPYSE = 103
-Alpha_INS_CPYSN = 104
-Alpha_INS_CPYS = 105
-Alpha_INS_CTLZ = 106
-Alpha_INS_CTPOP = 107
-Alpha_INS_CTTZ = 108
-Alpha_INS_CVTQSsSUI = 109
-Alpha_INS_CVTQTsSUI = 110
-Alpha_INS_CVTSTsS = 111
-Alpha_INS_CVTTQsSVC = 112
-Alpha_INS_CVTTSsSUI = 113
-Alpha_INS_DIVSsSU = 114
-Alpha_INS_DIVTsSU = 115
-Alpha_INS_ECB = 116
-Alpha_INS_EQV = 117
-Alpha_INS_EXCB = 118
-Alpha_INS_EXTBL = 119
-Alpha_INS_EXTLH = 120
-Alpha_INS_EXTLL = 121
-Alpha_INS_EXTQH = 122
-Alpha_INS_EXTQL = 123
-Alpha_INS_EXTWH = 124
-Alpha_INS_EXTWL = 125
-Alpha_INS_FBEQ = 126
-Alpha_INS_FBGE = 127
-Alpha_INS_FBGT = 128
-Alpha_INS_FBLE = 129
-Alpha_INS_FBLT = 130
-Alpha_INS_FBNE = 131
-Alpha_INS_FCMOVEQ = 132
-Alpha_INS_FCMOVGE = 133
-Alpha_INS_FCMOVGT = 134
-Alpha_INS_FCMOVLE = 135
-Alpha_INS_FCMOVLT = 136
-Alpha_INS_FCMOVNE = 137
-Alpha_INS_FETCH = 138
-Alpha_INS_FETCH_M = 139
-Alpha_INS_FTOIS = 140
-Alpha_INS_FTOIT = 141
-Alpha_INS_INSBL = 142
-Alpha_INS_INSLH = 143
-Alpha_INS_INSLL = 144
-Alpha_INS_INSQH = 145
-Alpha_INS_INSQL = 146
-Alpha_INS_INSWH = 147
-Alpha_INS_INSWL = 148
-Alpha_INS_ITOFS = 149
-Alpha_INS_ITOFT = 150
-Alpha_INS_JMP = 151
-Alpha_INS_JSR = 152
-Alpha_INS_JSR_COROUTINE = 153
-Alpha_INS_LDA = 154
-Alpha_INS_LDAH = 155
-Alpha_INS_LDBU = 156
-Alpha_INS_LDL = 157
-Alpha_INS_LDL_L = 158
-Alpha_INS_LDQ = 159
-Alpha_INS_LDQ_L = 160
-Alpha_INS_LDQ_U = 161
-Alpha_INS_LDS = 162
-Alpha_INS_LDT = 163
-Alpha_INS_LDWU = 164
-Alpha_INS_MB = 165
-Alpha_INS_MSKBL = 166
-Alpha_INS_MSKLH = 167
-Alpha_INS_MSKLL = 168
-Alpha_INS_MSKQH = 169
-Alpha_INS_MSKQL = 170
-Alpha_INS_MSKWH = 171
-Alpha_INS_MSKWL = 172
-Alpha_INS_MULL = 173
-Alpha_INS_MULQ = 174
-Alpha_INS_MULSsSU = 175
-Alpha_INS_MULTsSU = 176
-Alpha_INS_ORNOT = 177
-Alpha_INS_RC = 178
-Alpha_INS_RET = 179
-Alpha_INS_RPCC = 180
-Alpha_INS_RS = 181
-Alpha_INS_S4ADDL = 182
-Alpha_INS_S4ADDQ = 183
-Alpha_INS_S4SUBL = 184
-Alpha_INS_S4SUBQ = 185
-Alpha_INS_S8ADDL = 186
-Alpha_INS_S8ADDQ = 187
-Alpha_INS_S8SUBL = 188
-Alpha_INS_S8SUBQ = 189
-Alpha_INS_SEXTB = 190
-Alpha_INS_SEXTW = 191
-Alpha_INS_SLL = 192
-Alpha_INS_SQRTSsSU = 193
-Alpha_INS_SQRTTsSU = 194
-Alpha_INS_SRA = 195
-Alpha_INS_SRL = 196
-Alpha_INS_STB = 197
-Alpha_INS_STL = 198
-Alpha_INS_STL_C = 199
-Alpha_INS_STQ = 200
-Alpha_INS_STQ_C = 201
-Alpha_INS_STQ_U = 202
-Alpha_INS_STS = 203
-Alpha_INS_STT = 204
-Alpha_INS_STW = 205
-Alpha_INS_SUBL = 206
-Alpha_INS_SUBQ = 207
-Alpha_INS_SUBSsSU = 208
-Alpha_INS_SUBTsSU = 209
-Alpha_INS_TRAPB = 210
-Alpha_INS_UMULH = 211
-Alpha_INS_WH64 = 212
-Alpha_INS_WH64EN = 213
-Alpha_INS_WMB = 214
-Alpha_INS_XOR = 215
-Alpha_INS_ZAPNOT = 216
-ALPHA_INS_ENDING = 217
+
+Alpha_INS_INVALID = 0
+Alpha_INS_ADDL = 1
+Alpha_INS_ADDQ = 2
+Alpha_INS_ADDSsSU = 3
+Alpha_INS_ADDTsSU = 4
+Alpha_INS_AND = 5
+Alpha_INS_BEQ = 6
+Alpha_INS_BGE = 7
+Alpha_INS_BGT = 8
+Alpha_INS_BIC = 9
+Alpha_INS_BIS = 10
+Alpha_INS_BLBC = 11
+Alpha_INS_BLBS = 12
+Alpha_INS_BLE = 13
+Alpha_INS_BLT = 14
+Alpha_INS_BNE = 15
+Alpha_INS_BR = 16
+Alpha_INS_BSR = 17
+Alpha_INS_CMOVEQ = 18
+Alpha_INS_CMOVGE = 19
+Alpha_INS_CMOVGT = 20
+Alpha_INS_CMOVLBC = 21
+Alpha_INS_CMOVLBS = 22
+Alpha_INS_CMOVLE = 23
+Alpha_INS_CMOVLT = 24
+Alpha_INS_CMOVNE = 25
+Alpha_INS_CMPBGE = 26
+Alpha_INS_CMPEQ = 27
+Alpha_INS_CMPLE = 28
+Alpha_INS_CMPLT = 29
+Alpha_INS_CMPTEQsSU = 30
+Alpha_INS_CMPTLEsSU = 31
+Alpha_INS_CMPTLTsSU = 32
+Alpha_INS_CMPTUNsSU = 33
+Alpha_INS_CMPULE = 34
+Alpha_INS_CMPULT = 35
+Alpha_INS_COND_BRANCH = 36
+Alpha_INS_CPYSE = 37
+Alpha_INS_CPYSN = 38
+Alpha_INS_CPYS = 39
+Alpha_INS_CTLZ = 40
+Alpha_INS_CTPOP = 41
+Alpha_INS_CTTZ = 42
+Alpha_INS_CVTQSsSUI = 43
+Alpha_INS_CVTQTsSUI = 44
+Alpha_INS_CVTSTsS = 45
+Alpha_INS_CVTTQsSVC = 46
+Alpha_INS_CVTTSsSUI = 47
+Alpha_INS_DIVSsSU = 48
+Alpha_INS_DIVTsSU = 49
+Alpha_INS_ECB = 50
+Alpha_INS_EQV = 51
+Alpha_INS_EXCB = 52
+Alpha_INS_EXTBL = 53
+Alpha_INS_EXTLH = 54
+Alpha_INS_EXTLL = 55
+Alpha_INS_EXTQH = 56
+Alpha_INS_EXTQL = 57
+Alpha_INS_EXTWH = 58
+Alpha_INS_EXTWL = 59
+Alpha_INS_FBEQ = 60
+Alpha_INS_FBGE = 61
+Alpha_INS_FBGT = 62
+Alpha_INS_FBLE = 63
+Alpha_INS_FBLT = 64
+Alpha_INS_FBNE = 65
+Alpha_INS_FCMOVEQ = 66
+Alpha_INS_FCMOVGE = 67
+Alpha_INS_FCMOVGT = 68
+Alpha_INS_FCMOVLE = 69
+Alpha_INS_FCMOVLT = 70
+Alpha_INS_FCMOVNE = 71
+Alpha_INS_FETCH = 72
+Alpha_INS_FETCH_M = 73
+Alpha_INS_FTOIS = 74
+Alpha_INS_FTOIT = 75
+Alpha_INS_INSBL = 76
+Alpha_INS_INSLH = 77
+Alpha_INS_INSLL = 78
+Alpha_INS_INSQH = 79
+Alpha_INS_INSQL = 80
+Alpha_INS_INSWH = 81
+Alpha_INS_INSWL = 82
+Alpha_INS_ITOFS = 83
+Alpha_INS_ITOFT = 84
+Alpha_INS_JMP = 85
+Alpha_INS_JSR = 86
+Alpha_INS_JSR_COROUTINE = 87
+Alpha_INS_LDA = 88
+Alpha_INS_LDAH = 89
+Alpha_INS_LDBU = 90
+Alpha_INS_LDL = 91
+Alpha_INS_LDL_L = 92
+Alpha_INS_LDQ = 93
+Alpha_INS_LDQ_L = 94
+Alpha_INS_LDQ_U = 95
+Alpha_INS_LDS = 96
+Alpha_INS_LDT = 97
+Alpha_INS_LDWU = 98
+Alpha_INS_MB = 99
+Alpha_INS_MSKBL = 100
+Alpha_INS_MSKLH = 101
+Alpha_INS_MSKLL = 102
+Alpha_INS_MSKQH = 103
+Alpha_INS_MSKQL = 104
+Alpha_INS_MSKWH = 105
+Alpha_INS_MSKWL = 106
+Alpha_INS_MULL = 107
+Alpha_INS_MULQ = 108
+Alpha_INS_MULSsSU = 109
+Alpha_INS_MULTsSU = 110
+Alpha_INS_ORNOT = 111
+Alpha_INS_RC = 112
+Alpha_INS_RET = 113
+Alpha_INS_RPCC = 114
+Alpha_INS_RS = 115
+Alpha_INS_S4ADDL = 116
+Alpha_INS_S4ADDQ = 117
+Alpha_INS_S4SUBL = 118
+Alpha_INS_S4SUBQ = 119
+Alpha_INS_S8ADDL = 120
+Alpha_INS_S8ADDQ = 121
+Alpha_INS_S8SUBL = 122
+Alpha_INS_S8SUBQ = 123
+Alpha_INS_SEXTB = 124
+Alpha_INS_SEXTW = 125
+Alpha_INS_SLL = 126
+Alpha_INS_SQRTSsSU = 127
+Alpha_INS_SQRTTsSU = 128
+Alpha_INS_SRA = 129
+Alpha_INS_SRL = 130
+Alpha_INS_STB = 131
+Alpha_INS_STL = 132
+Alpha_INS_STL_C = 133
+Alpha_INS_STQ = 134
+Alpha_INS_STQ_C = 135
+Alpha_INS_STQ_U = 136
+Alpha_INS_STS = 137
+Alpha_INS_STT = 138
+Alpha_INS_STW = 139
+Alpha_INS_SUBL = 140
+Alpha_INS_SUBQ = 141
+Alpha_INS_SUBSsSU = 142
+Alpha_INS_SUBTsSU = 143
+Alpha_INS_TRAPB = 144
+Alpha_INS_UMULH = 145
+Alpha_INS_WH64 = 146
+Alpha_INS_WH64EN = 147
+Alpha_INS_WMB = 148
+Alpha_INS_XOR = 149
+Alpha_INS_ZAPNOT = 150
+ALPHA_INS_ENDING = 151
 
 # Group of Alpha instructions
-Alpha_GRP_INVALID = 218
+
+Alpha_GRP_INVALID = 0
 
 # Generic groups
-Alpha_GRP_CALL = 219
-Alpha_GRP_JUMP = 220
-Alpha_GRP_BRANCH_RELATIVE = 221
-Alpha_GRP_ENDING = 222
+Alpha_GRP_CALL = 1
+Alpha_GRP_JUMP = 2
+Alpha_GRP_BRANCH_RELATIVE = 3
+Alpha_GRP_ENDING = 4
diff --git a/bindings/python/capstone/arm.py b/bindings/python/capstone/arm.py
index 32718f497..8c2fe9266 100644
--- a/bindings/python/capstone/arm.py
+++ b/bindings/python/capstone/arm.py
@@ -12,6 +12,7 @@ class ArmOpMem(ctypes.Structure):
         ('scale', ctypes.c_int),
         ('disp', ctypes.c_int),
         ('lshift', ctypes.c_int),
+        ('align', ctypes.c_uint),
     )
 
 class ArmOpShift(ctypes.Structure):
@@ -38,7 +39,7 @@ class ArmOpValue(ctypes.Union):
     _fields_ = (
         ('reg', ctypes.c_uint),
         ('sysop', ArmOpSysop),
-        ('imm', ctypes.c_int32),
+        ('imm', ctypes.c_int64),
         ('pred', ctypes.c_int),
         ('fp', ctypes.c_double),
         ('mem', ArmOpMem),
diff --git a/bindings/python/capstone/arm_const.py b/bindings/python/capstone/arm_const.py
index 2e6a13808..804481bc4 100644
--- a/bindings/python/capstone/arm_const.py
+++ b/bindings/python/capstone/arm_const.py
@@ -48,22 +48,23 @@ ARM_SFT_LSL_REG = 7
 ARM_SFT_LSR_REG = 8
 ARM_SFT_ROR_REG = 9
 ARM_SFT_RRX_REG = 10
-ARM_MB_RESERVED_0 = 11
-ARM_MB_OSHLD = 12
-ARM_MB_OSHST = 13
-ARM_MB_OSH = 14
-ARM_MB_RESERVED_4 = 15
-ARM_MB_NSHLD = 16
-ARM_MB_NSHST = 17
-ARM_MB_NSH = 18
-ARM_MB_RESERVED_8 = 19
-ARM_MB_ISHLD = 20
-ARM_MB_ISHST = 21
-ARM_MB_ISH = 22
-ARM_MB_RESERVED_12 = 23
-ARM_MB_LD = 24
-ARM_MB_ST = 25
-ARM_MB_SY = 26
+
+ARM_MB_RESERVED_0 = 0
+ARM_MB_OSHLD = 1
+ARM_MB_OSHST = 2
+ARM_MB_OSH = 3
+ARM_MB_RESERVED_4 = 4
+ARM_MB_NSHLD = 5
+ARM_MB_NSHST = 6
+ARM_MB_NSH = 7
+ARM_MB_RESERVED_8 = 8
+ARM_MB_ISHLD = 9
+ARM_MB_ISHST = 10
+ARM_MB_ISH = 11
+ARM_MB_RESERVED_12 = 12
+ARM_MB_LD = 13
+ARM_MB_ST = 14
+ARM_MB_SY = 15
 ARM_FIELD_SPSR_C = 1
 ARM_FIELD_SPSR_X = 2
 ARM_FIELD_SPSR_S = 4
@@ -542,694 +543,695 @@ ARM_REG_SB = ARM_REG_R9
 ARM_REG_SL = ARM_REG_R10
 ARM_REG_FP = ARM_REG_R11
 ARM_REG_IP = ARM_REG_R12
-ARM_INS_INVALID = 297
-ARM_INS_ASR = 298
-ARM_INS_IT = 299
-ARM_INS_LDRBT = 300
-ARM_INS_LDR = 301
-ARM_INS_LDRHT = 302
-ARM_INS_LDRSBT = 303
-ARM_INS_LDRSHT = 304
-ARM_INS_LDRT = 305
-ARM_INS_LSL = 306
-ARM_INS_LSR = 307
-ARM_INS_ROR = 308
-ARM_INS_RRX = 309
-ARM_INS_STRBT = 310
-ARM_INS_STRT = 311
-ARM_INS_VLD1 = 312
-ARM_INS_VLD2 = 313
-ARM_INS_VLD3 = 314
-ARM_INS_VLD4 = 315
-ARM_INS_VST1 = 316
-ARM_INS_VST2 = 317
-ARM_INS_VST3 = 318
-ARM_INS_VST4 = 319
-ARM_INS_LDRB = 320
-ARM_INS_LDRH = 321
-ARM_INS_LDRSB = 322
-ARM_INS_LDRSH = 323
-ARM_INS_MOVS = 324
-ARM_INS_MOV = 325
-ARM_INS_STR = 326
-ARM_INS_ADC = 327
-ARM_INS_ADD = 328
-ARM_INS_ADR = 329
-ARM_INS_AESD = 330
-ARM_INS_AESE = 331
-ARM_INS_AESIMC = 332
-ARM_INS_AESMC = 333
-ARM_INS_AND = 334
-ARM_INS_VDOT = 335
-ARM_INS_VCVT = 336
-ARM_INS_VCVTB = 337
-ARM_INS_VCVTT = 338
-ARM_INS_BFC = 339
-ARM_INS_BFI = 340
-ARM_INS_BIC = 341
-ARM_INS_BKPT = 342
-ARM_INS_BL = 343
-ARM_INS_BLX = 344
-ARM_INS_BX = 345
-ARM_INS_BXJ = 346
-ARM_INS_B = 347
-ARM_INS_CX1 = 348
-ARM_INS_CX1A = 349
-ARM_INS_CX1D = 350
-ARM_INS_CX1DA = 351
-ARM_INS_CX2 = 352
-ARM_INS_CX2A = 353
-ARM_INS_CX2D = 354
-ARM_INS_CX2DA = 355
-ARM_INS_CX3 = 356
-ARM_INS_CX3A = 357
-ARM_INS_CX3D = 358
-ARM_INS_CX3DA = 359
-ARM_INS_VCX1A = 360
-ARM_INS_VCX1 = 361
-ARM_INS_VCX2A = 362
-ARM_INS_VCX2 = 363
-ARM_INS_VCX3A = 364
-ARM_INS_VCX3 = 365
-ARM_INS_CDP = 366
-ARM_INS_CDP2 = 367
-ARM_INS_CLREX = 368
-ARM_INS_CLZ = 369
-ARM_INS_CMN = 370
-ARM_INS_CMP = 371
-ARM_INS_CPS = 372
-ARM_INS_CRC32B = 373
-ARM_INS_CRC32CB = 374
-ARM_INS_CRC32CH = 375
-ARM_INS_CRC32CW = 376
-ARM_INS_CRC32H = 377
-ARM_INS_CRC32W = 378
-ARM_INS_DBG = 379
-ARM_INS_DMB = 380
-ARM_INS_DSB = 381
-ARM_INS_EOR = 382
-ARM_INS_ERET = 383
-ARM_INS_VMOV = 384
-ARM_INS_FLDMDBX = 385
-ARM_INS_FLDMIAX = 386
-ARM_INS_VMRS = 387
-ARM_INS_FSTMDBX = 388
-ARM_INS_FSTMIAX = 389
-ARM_INS_HINT = 390
-ARM_INS_HLT = 391
-ARM_INS_HVC = 392
-ARM_INS_ISB = 393
-ARM_INS_LDA = 394
-ARM_INS_LDAB = 395
-ARM_INS_LDAEX = 396
-ARM_INS_LDAEXB = 397
-ARM_INS_LDAEXD = 398
-ARM_INS_LDAEXH = 399
-ARM_INS_LDAH = 400
-ARM_INS_LDC2L = 401
-ARM_INS_LDC2 = 402
-ARM_INS_LDCL = 403
-ARM_INS_LDC = 404
-ARM_INS_LDMDA = 405
-ARM_INS_LDMDB = 406
-ARM_INS_LDM = 407
-ARM_INS_LDMIB = 408
-ARM_INS_LDRD = 409
-ARM_INS_LDREX = 410
-ARM_INS_LDREXB = 411
-ARM_INS_LDREXD = 412
-ARM_INS_LDREXH = 413
-ARM_INS_MCR = 414
-ARM_INS_MCR2 = 415
-ARM_INS_MCRR = 416
-ARM_INS_MCRR2 = 417
-ARM_INS_MLA = 418
-ARM_INS_MLS = 419
-ARM_INS_MOVT = 420
-ARM_INS_MOVW = 421
-ARM_INS_MRC = 422
-ARM_INS_MRC2 = 423
-ARM_INS_MRRC = 424
-ARM_INS_MRRC2 = 425
-ARM_INS_MRS = 426
-ARM_INS_MSR = 427
-ARM_INS_MUL = 428
-ARM_INS_ASRL = 429
-ARM_INS_DLSTP = 430
-ARM_INS_LCTP = 431
-ARM_INS_LETP = 432
-ARM_INS_LSLL = 433
-ARM_INS_LSRL = 434
-ARM_INS_SQRSHR = 435
-ARM_INS_SQRSHRL = 436
-ARM_INS_SQSHL = 437
-ARM_INS_SQSHLL = 438
-ARM_INS_SRSHR = 439
-ARM_INS_SRSHRL = 440
-ARM_INS_UQRSHL = 441
-ARM_INS_UQRSHLL = 442
-ARM_INS_UQSHL = 443
-ARM_INS_UQSHLL = 444
-ARM_INS_URSHR = 445
-ARM_INS_URSHRL = 446
-ARM_INS_VABAV = 447
-ARM_INS_VABD = 448
-ARM_INS_VABS = 449
-ARM_INS_VADC = 450
-ARM_INS_VADCI = 451
-ARM_INS_VADDLVA = 452
-ARM_INS_VADDLV = 453
-ARM_INS_VADDVA = 454
-ARM_INS_VADDV = 455
-ARM_INS_VADD = 456
-ARM_INS_VAND = 457
-ARM_INS_VBIC = 458
-ARM_INS_VBRSR = 459
-ARM_INS_VCADD = 460
-ARM_INS_VCLS = 461
-ARM_INS_VCLZ = 462
-ARM_INS_VCMLA = 463
-ARM_INS_VCMP = 464
-ARM_INS_VCMUL = 465
-ARM_INS_VCTP = 466
-ARM_INS_VCVTA = 467
-ARM_INS_VCVTM = 468
-ARM_INS_VCVTN = 469
-ARM_INS_VCVTP = 470
-ARM_INS_VDDUP = 471
-ARM_INS_VDUP = 472
-ARM_INS_VDWDUP = 473
-ARM_INS_VEOR = 474
-ARM_INS_VFMAS = 475
-ARM_INS_VFMA = 476
-ARM_INS_VFMS = 477
-ARM_INS_VHADD = 478
-ARM_INS_VHCADD = 479
-ARM_INS_VHSUB = 480
-ARM_INS_VIDUP = 481
-ARM_INS_VIWDUP = 482
-ARM_INS_VLD20 = 483
-ARM_INS_VLD21 = 484
-ARM_INS_VLD40 = 485
-ARM_INS_VLD41 = 486
-ARM_INS_VLD42 = 487
-ARM_INS_VLD43 = 488
-ARM_INS_VLDRB = 489
-ARM_INS_VLDRD = 490
-ARM_INS_VLDRH = 491
-ARM_INS_VLDRW = 492
-ARM_INS_VMAXAV = 493
-ARM_INS_VMAXA = 494
-ARM_INS_VMAXNMAV = 495
-ARM_INS_VMAXNMA = 496
-ARM_INS_VMAXNMV = 497
-ARM_INS_VMAXNM = 498
-ARM_INS_VMAXV = 499
-ARM_INS_VMAX = 500
-ARM_INS_VMINAV = 501
-ARM_INS_VMINA = 502
-ARM_INS_VMINNMAV = 503
-ARM_INS_VMINNMA = 504
-ARM_INS_VMINNMV = 505
-ARM_INS_VMINNM = 506
-ARM_INS_VMINV = 507
-ARM_INS_VMIN = 508
-ARM_INS_VMLADAVA = 509
-ARM_INS_VMLADAVAX = 510
-ARM_INS_VMLADAV = 511
-ARM_INS_VMLADAVX = 512
-ARM_INS_VMLALDAVA = 513
-ARM_INS_VMLALDAVAX = 514
-ARM_INS_VMLALDAV = 515
-ARM_INS_VMLALDAVX = 516
-ARM_INS_VMLAS = 517
-ARM_INS_VMLA = 518
-ARM_INS_VMLSDAVA = 519
-ARM_INS_VMLSDAVAX = 520
-ARM_INS_VMLSDAV = 521
-ARM_INS_VMLSDAVX = 522
-ARM_INS_VMLSLDAVA = 523
-ARM_INS_VMLSLDAVAX = 524
-ARM_INS_VMLSLDAV = 525
-ARM_INS_VMLSLDAVX = 526
-ARM_INS_VMOVLB = 527
-ARM_INS_VMOVLT = 528
-ARM_INS_VMOVNB = 529
-ARM_INS_VMOVNT = 530
-ARM_INS_VMULH = 531
-ARM_INS_VMULLB = 532
-ARM_INS_VMULLT = 533
-ARM_INS_VMUL = 534
-ARM_INS_VMVN = 535
-ARM_INS_VNEG = 536
-ARM_INS_VORN = 537
-ARM_INS_VORR = 538
-ARM_INS_VPNOT = 539
-ARM_INS_VPSEL = 540
-ARM_INS_VPST = 541
-ARM_INS_VPT = 542
-ARM_INS_VQABS = 543
-ARM_INS_VQADD = 544
-ARM_INS_VQDMLADHX = 545
-ARM_INS_VQDMLADH = 546
-ARM_INS_VQDMLAH = 547
-ARM_INS_VQDMLASH = 548
-ARM_INS_VQDMLSDHX = 549
-ARM_INS_VQDMLSDH = 550
-ARM_INS_VQDMULH = 551
-ARM_INS_VQDMULLB = 552
-ARM_INS_VQDMULLT = 553
-ARM_INS_VQMOVNB = 554
-ARM_INS_VQMOVNT = 555
-ARM_INS_VQMOVUNB = 556
-ARM_INS_VQMOVUNT = 557
-ARM_INS_VQNEG = 558
-ARM_INS_VQRDMLADHX = 559
-ARM_INS_VQRDMLADH = 560
-ARM_INS_VQRDMLAH = 561
-ARM_INS_VQRDMLASH = 562
-ARM_INS_VQRDMLSDHX = 563
-ARM_INS_VQRDMLSDH = 564
-ARM_INS_VQRDMULH = 565
-ARM_INS_VQRSHL = 566
-ARM_INS_VQRSHRNB = 567
-ARM_INS_VQRSHRNT = 568
-ARM_INS_VQRSHRUNB = 569
-ARM_INS_VQRSHRUNT = 570
-ARM_INS_VQSHLU = 571
-ARM_INS_VQSHL = 572
-ARM_INS_VQSHRNB = 573
-ARM_INS_VQSHRNT = 574
-ARM_INS_VQSHRUNB = 575
-ARM_INS_VQSHRUNT = 576
-ARM_INS_VQSUB = 577
-ARM_INS_VREV16 = 578
-ARM_INS_VREV32 = 579
-ARM_INS_VREV64 = 580
-ARM_INS_VRHADD = 581
-ARM_INS_VRINTA = 582
-ARM_INS_VRINTM = 583
-ARM_INS_VRINTN = 584
-ARM_INS_VRINTP = 585
-ARM_INS_VRINTX = 586
-ARM_INS_VRINTZ = 587
-ARM_INS_VRMLALDAVHA = 588
-ARM_INS_VRMLALDAVHAX = 589
-ARM_INS_VRMLALDAVH = 590
-ARM_INS_VRMLALDAVHX = 591
-ARM_INS_VRMLSLDAVHA = 592
-ARM_INS_VRMLSLDAVHAX = 593
-ARM_INS_VRMLSLDAVH = 594
-ARM_INS_VRMLSLDAVHX = 595
-ARM_INS_VRMULH = 596
-ARM_INS_VRSHL = 597
-ARM_INS_VRSHRNB = 598
-ARM_INS_VRSHRNT = 599
-ARM_INS_VRSHR = 600
-ARM_INS_VSBC = 601
-ARM_INS_VSBCI = 602
-ARM_INS_VSHLC = 603
-ARM_INS_VSHLLB = 604
-ARM_INS_VSHLLT = 605
-ARM_INS_VSHL = 606
-ARM_INS_VSHRNB = 607
-ARM_INS_VSHRNT = 608
-ARM_INS_VSHR = 609
-ARM_INS_VSLI = 610
-ARM_INS_VSRI = 611
-ARM_INS_VST20 = 612
-ARM_INS_VST21 = 613
-ARM_INS_VST40 = 614
-ARM_INS_VST41 = 615
-ARM_INS_VST42 = 616
-ARM_INS_VST43 = 617
-ARM_INS_VSTRB = 618
-ARM_INS_VSTRD = 619
-ARM_INS_VSTRH = 620
-ARM_INS_VSTRW = 621
-ARM_INS_VSUB = 622
-ARM_INS_WLSTP = 623
-ARM_INS_MVN = 624
-ARM_INS_ORR = 625
-ARM_INS_PKHBT = 626
-ARM_INS_PKHTB = 627
-ARM_INS_PLDW = 628
-ARM_INS_PLD = 629
-ARM_INS_PLI = 630
-ARM_INS_QADD = 631
-ARM_INS_QADD16 = 632
-ARM_INS_QADD8 = 633
-ARM_INS_QASX = 634
-ARM_INS_QDADD = 635
-ARM_INS_QDSUB = 636
-ARM_INS_QSAX = 637
-ARM_INS_QSUB = 638
-ARM_INS_QSUB16 = 639
-ARM_INS_QSUB8 = 640
-ARM_INS_RBIT = 641
-ARM_INS_REV = 642
-ARM_INS_REV16 = 643
-ARM_INS_REVSH = 644
-ARM_INS_RFEDA = 645
-ARM_INS_RFEDB = 646
-ARM_INS_RFEIA = 647
-ARM_INS_RFEIB = 648
-ARM_INS_RSB = 649
-ARM_INS_RSC = 650
-ARM_INS_SADD16 = 651
-ARM_INS_SADD8 = 652
-ARM_INS_SASX = 653
-ARM_INS_SB = 654
-ARM_INS_SBC = 655
-ARM_INS_SBFX = 656
-ARM_INS_SDIV = 657
-ARM_INS_SEL = 658
-ARM_INS_SETEND = 659
-ARM_INS_SETPAN = 660
-ARM_INS_SHA1C = 661
-ARM_INS_SHA1H = 662
-ARM_INS_SHA1M = 663
-ARM_INS_SHA1P = 664
-ARM_INS_SHA1SU0 = 665
-ARM_INS_SHA1SU1 = 666
-ARM_INS_SHA256H = 667
-ARM_INS_SHA256H2 = 668
-ARM_INS_SHA256SU0 = 669
-ARM_INS_SHA256SU1 = 670
-ARM_INS_SHADD16 = 671
-ARM_INS_SHADD8 = 672
-ARM_INS_SHASX = 673
-ARM_INS_SHSAX = 674
-ARM_INS_SHSUB16 = 675
-ARM_INS_SHSUB8 = 676
-ARM_INS_SMC = 677
-ARM_INS_SMLABB = 678
-ARM_INS_SMLABT = 679
-ARM_INS_SMLAD = 680
-ARM_INS_SMLADX = 681
-ARM_INS_SMLAL = 682
-ARM_INS_SMLALBB = 683
-ARM_INS_SMLALBT = 684
-ARM_INS_SMLALD = 685
-ARM_INS_SMLALDX = 686
-ARM_INS_SMLALTB = 687
-ARM_INS_SMLALTT = 688
-ARM_INS_SMLATB = 689
-ARM_INS_SMLATT = 690
-ARM_INS_SMLAWB = 691
-ARM_INS_SMLAWT = 692
-ARM_INS_SMLSD = 693
-ARM_INS_SMLSDX = 694
-ARM_INS_SMLSLD = 695
-ARM_INS_SMLSLDX = 696
-ARM_INS_SMMLA = 697
-ARM_INS_SMMLAR = 698
-ARM_INS_SMMLS = 699
-ARM_INS_SMMLSR = 700
-ARM_INS_SMMUL = 701
-ARM_INS_SMMULR = 702
-ARM_INS_SMUAD = 703
-ARM_INS_SMUADX = 704
-ARM_INS_SMULBB = 705
-ARM_INS_SMULBT = 706
-ARM_INS_SMULL = 707
-ARM_INS_SMULTB = 708
-ARM_INS_SMULTT = 709
-ARM_INS_SMULWB = 710
-ARM_INS_SMULWT = 711
-ARM_INS_SMUSD = 712
-ARM_INS_SMUSDX = 713
-ARM_INS_SRSDA = 714
-ARM_INS_SRSDB = 715
-ARM_INS_SRSIA = 716
-ARM_INS_SRSIB = 717
-ARM_INS_SSAT = 718
-ARM_INS_SSAT16 = 719
-ARM_INS_SSAX = 720
-ARM_INS_SSUB16 = 721
-ARM_INS_SSUB8 = 722
-ARM_INS_STC2L = 723
-ARM_INS_STC2 = 724
-ARM_INS_STCL = 725
-ARM_INS_STC = 726
-ARM_INS_STL = 727
-ARM_INS_STLB = 728
-ARM_INS_STLEX = 729
-ARM_INS_STLEXB = 730
-ARM_INS_STLEXD = 731
-ARM_INS_STLEXH = 732
-ARM_INS_STLH = 733
-ARM_INS_STMDA = 734
-ARM_INS_STMDB = 735
-ARM_INS_STM = 736
-ARM_INS_STMIB = 737
-ARM_INS_STRB = 738
-ARM_INS_STRD = 739
-ARM_INS_STREX = 740
-ARM_INS_STREXB = 741
-ARM_INS_STREXD = 742
-ARM_INS_STREXH = 743
-ARM_INS_STRH = 744
-ARM_INS_STRHT = 745
-ARM_INS_SUB = 746
-ARM_INS_SVC = 747
-ARM_INS_SWP = 748
-ARM_INS_SWPB = 749
-ARM_INS_SXTAB = 750
-ARM_INS_SXTAB16 = 751
-ARM_INS_SXTAH = 752
-ARM_INS_SXTB = 753
-ARM_INS_SXTB16 = 754
-ARM_INS_SXTH = 755
-ARM_INS_TEQ = 756
-ARM_INS_TRAP = 757
-ARM_INS_TSB = 758
-ARM_INS_TST = 759
-ARM_INS_UADD16 = 760
-ARM_INS_UADD8 = 761
-ARM_INS_UASX = 762
-ARM_INS_UBFX = 763
-ARM_INS_UDF = 764
-ARM_INS_UDIV = 765
-ARM_INS_UHADD16 = 766
-ARM_INS_UHADD8 = 767
-ARM_INS_UHASX = 768
-ARM_INS_UHSAX = 769
-ARM_INS_UHSUB16 = 770
-ARM_INS_UHSUB8 = 771
-ARM_INS_UMAAL = 772
-ARM_INS_UMLAL = 773
-ARM_INS_UMULL = 774
-ARM_INS_UQADD16 = 775
-ARM_INS_UQADD8 = 776
-ARM_INS_UQASX = 777
-ARM_INS_UQSAX = 778
-ARM_INS_UQSUB16 = 779
-ARM_INS_UQSUB8 = 780
-ARM_INS_USAD8 = 781
-ARM_INS_USADA8 = 782
-ARM_INS_USAT = 783
-ARM_INS_USAT16 = 784
-ARM_INS_USAX = 785
-ARM_INS_USUB16 = 786
-ARM_INS_USUB8 = 787
-ARM_INS_UXTAB = 788
-ARM_INS_UXTAB16 = 789
-ARM_INS_UXTAH = 790
-ARM_INS_UXTB = 791
-ARM_INS_UXTB16 = 792
-ARM_INS_UXTH = 793
-ARM_INS_VABAL = 794
-ARM_INS_VABA = 795
-ARM_INS_VABDL = 796
-ARM_INS_VACGE = 797
-ARM_INS_VACGT = 798
-ARM_INS_VADDHN = 799
-ARM_INS_VADDL = 800
-ARM_INS_VADDW = 801
-ARM_INS_VFMAB = 802
-ARM_INS_VFMAT = 803
-ARM_INS_VBIF = 804
-ARM_INS_VBIT = 805
-ARM_INS_VBSL = 806
-ARM_INS_VCEQ = 807
-ARM_INS_VCGE = 808
-ARM_INS_VCGT = 809
-ARM_INS_VCLE = 810
-ARM_INS_VCLT = 811
-ARM_INS_VCMPE = 812
-ARM_INS_VCNT = 813
-ARM_INS_VDIV = 814
-ARM_INS_VEXT = 815
-ARM_INS_VFMAL = 816
-ARM_INS_VFMSL = 817
-ARM_INS_VFNMA = 818
-ARM_INS_VFNMS = 819
-ARM_INS_VINS = 820
-ARM_INS_VJCVT = 821
-ARM_INS_VLDMDB = 822
-ARM_INS_VLDMIA = 823
-ARM_INS_VLDR = 824
-ARM_INS_VLLDM = 825
-ARM_INS_VLSTM = 826
-ARM_INS_VMLAL = 827
-ARM_INS_VMLS = 828
-ARM_INS_VMLSL = 829
-ARM_INS_VMMLA = 830
-ARM_INS_VMOVX = 831
-ARM_INS_VMOVL = 832
-ARM_INS_VMOVN = 833
-ARM_INS_VMSR = 834
-ARM_INS_VMULL = 835
-ARM_INS_VNMLA = 836
-ARM_INS_VNMLS = 837
-ARM_INS_VNMUL = 838
-ARM_INS_VPADAL = 839
-ARM_INS_VPADDL = 840
-ARM_INS_VPADD = 841
-ARM_INS_VPMAX = 842
-ARM_INS_VPMIN = 843
-ARM_INS_VQDMLAL = 844
-ARM_INS_VQDMLSL = 845
-ARM_INS_VQDMULL = 846
-ARM_INS_VQMOVUN = 847
-ARM_INS_VQMOVN = 848
-ARM_INS_VQRDMLSH = 849
-ARM_INS_VQRSHRN = 850
-ARM_INS_VQRSHRUN = 851
-ARM_INS_VQSHRN = 852
-ARM_INS_VQSHRUN = 853
-ARM_INS_VRADDHN = 854
-ARM_INS_VRECPE = 855
-ARM_INS_VRECPS = 856
-ARM_INS_VRINTR = 857
-ARM_INS_VRSHRN = 858
-ARM_INS_VRSQRTE = 859
-ARM_INS_VRSQRTS = 860
-ARM_INS_VRSRA = 861
-ARM_INS_VRSUBHN = 862
-ARM_INS_VSCCLRM = 863
-ARM_INS_VSDOT = 864
-ARM_INS_VSELEQ = 865
-ARM_INS_VSELGE = 866
-ARM_INS_VSELGT = 867
-ARM_INS_VSELVS = 868
-ARM_INS_VSHLL = 869
-ARM_INS_VSHRN = 870
-ARM_INS_VSMMLA = 871
-ARM_INS_VSQRT = 872
-ARM_INS_VSRA = 873
-ARM_INS_VSTMDB = 874
-ARM_INS_VSTMIA = 875
-ARM_INS_VSTR = 876
-ARM_INS_VSUBHN = 877
-ARM_INS_VSUBL = 878
-ARM_INS_VSUBW = 879
-ARM_INS_VSUDOT = 880
-ARM_INS_VSWP = 881
-ARM_INS_VTBL = 882
-ARM_INS_VTBX = 883
-ARM_INS_VCVTR = 884
-ARM_INS_VTRN = 885
-ARM_INS_VTST = 886
-ARM_INS_VUDOT = 887
-ARM_INS_VUMMLA = 888
-ARM_INS_VUSDOT = 889
-ARM_INS_VUSMMLA = 890
-ARM_INS_VUZP = 891
-ARM_INS_VZIP = 892
-ARM_INS_ADDW = 893
-ARM_INS_AUT = 894
-ARM_INS_AUTG = 895
-ARM_INS_BFL = 896
-ARM_INS_BFLX = 897
-ARM_INS_BF = 898
-ARM_INS_BFCSEL = 899
-ARM_INS_BFX = 900
-ARM_INS_BTI = 901
-ARM_INS_BXAUT = 902
-ARM_INS_CLRM = 903
-ARM_INS_CSEL = 904
-ARM_INS_CSINC = 905
-ARM_INS_CSINV = 906
-ARM_INS_CSNEG = 907
-ARM_INS_DCPS1 = 908
-ARM_INS_DCPS2 = 909
-ARM_INS_DCPS3 = 910
-ARM_INS_DLS = 911
-ARM_INS_LE = 912
-ARM_INS_ORN = 913
-ARM_INS_PAC = 914
-ARM_INS_PACBTI = 915
-ARM_INS_PACG = 916
-ARM_INS_SG = 917
-ARM_INS_SUBS = 918
-ARM_INS_SUBW = 919
-ARM_INS_TBB = 920
-ARM_INS_TBH = 921
-ARM_INS_TT = 922
-ARM_INS_TTA = 923
-ARM_INS_TTAT = 924
-ARM_INS_TTT = 925
-ARM_INS_WLS = 926
-ARM_INS_BLXNS = 927
-ARM_INS_BXNS = 928
-ARM_INS_CBNZ = 929
-ARM_INS_CBZ = 930
-ARM_INS_POP = 931
-ARM_INS_PUSH = 932
-ARM_INS___BRKDIV0 = 933
-ARM_INS_ENDING = 934
-ARM_INS_ALIAS_BEGIN = 935
-ARM_INS_ALIAS_VMOV = 936
-ARM_INS_ALIAS_NOP = 937
-ARM_INS_ALIAS_YIELD = 938
-ARM_INS_ALIAS_WFE = 939
-ARM_INS_ALIAS_WFI = 940
-ARM_INS_ALIAS_SEV = 941
-ARM_INS_ALIAS_SEVL = 942
-ARM_INS_ALIAS_ESB = 943
-ARM_INS_ALIAS_CSDB = 944
-ARM_INS_ALIAS_CLRBHB = 945
-ARM_INS_ALIAS_PACBTI = 946
-ARM_INS_ALIAS_BTI = 947
-ARM_INS_ALIAS_PAC = 948
-ARM_INS_ALIAS_AUT = 949
-ARM_INS_ALIAS_SSBB = 950
-ARM_INS_ALIAS_PSSBB = 951
-ARM_INS_ALIAS_DFB = 952
-ARM_INS_ALIAS_CSETM = 953
-ARM_INS_ALIAS_CSET = 954
-ARM_INS_ALIAS_CINC = 955
-ARM_INS_ALIAS_CINV = 956
-ARM_INS_ALIAS_CNEG = 957
-ARM_INS_ALIAS_VMLAV = 958
-ARM_INS_ALIAS_VMLAVA = 959
-ARM_INS_ALIAS_VRMLALVH = 960
-ARM_INS_ALIAS_VRMLALVHA = 961
-ARM_INS_ALIAS_VMLALV = 962
-ARM_INS_ALIAS_VMLALVA = 963
-ARM_INS_ALIAS_VBIC = 964
-ARM_INS_ALIAS_VEOR = 965
-ARM_INS_ALIAS_VORN = 966
-ARM_INS_ALIAS_VORR = 967
-ARM_INS_ALIAS_VAND = 968
-ARM_INS_ALIAS_VPSEL = 969
-ARM_INS_ALIAS_ERET = 970
-ARM_INS_ALIAS_ASR = 971
-ARM_INS_ALIAS_LSL = 972
-ARM_INS_ALIAS_LSR = 973
-ARM_INS_ALIAS_ROR = 974
-ARM_INS_ALIAS_RRX = 975
-ARM_INS_ALIAS_UXTW = 976
-ARM_INS_ALIAS_LDM = 977
-ARM_INS_ALIAS_POP = 978
-ARM_INS_ALIAS_PUSH = 979
-ARM_INS_ALIAS_POPW = 980
-ARM_INS_ALIAS_PUSHW = 981
-ARM_INS_ALIAS_VPOP = 982
-ARM_INS_ALIAS_VPUSH = 983
-ARM_INS_ALIAS_END = 984
+
+ARM_INS_INVALID = 0
+ARM_INS_ASR = 1
+ARM_INS_IT = 2
+ARM_INS_LDRBT = 3
+ARM_INS_LDR = 4
+ARM_INS_LDRHT = 5
+ARM_INS_LDRSBT = 6
+ARM_INS_LDRSHT = 7
+ARM_INS_LDRT = 8
+ARM_INS_LSL = 9
+ARM_INS_LSR = 10
+ARM_INS_ROR = 11
+ARM_INS_RRX = 12
+ARM_INS_STRBT = 13
+ARM_INS_STRT = 14
+ARM_INS_VLD1 = 15
+ARM_INS_VLD2 = 16
+ARM_INS_VLD3 = 17
+ARM_INS_VLD4 = 18
+ARM_INS_VST1 = 19
+ARM_INS_VST2 = 20
+ARM_INS_VST3 = 21
+ARM_INS_VST4 = 22
+ARM_INS_LDRB = 23
+ARM_INS_LDRH = 24
+ARM_INS_LDRSB = 25
+ARM_INS_LDRSH = 26
+ARM_INS_MOVS = 27
+ARM_INS_MOV = 28
+ARM_INS_STR = 29
+ARM_INS_ADC = 30
+ARM_INS_ADD = 31
+ARM_INS_ADR = 32
+ARM_INS_AESD = 33
+ARM_INS_AESE = 34
+ARM_INS_AESIMC = 35
+ARM_INS_AESMC = 36
+ARM_INS_AND = 37
+ARM_INS_VDOT = 38
+ARM_INS_VCVT = 39
+ARM_INS_VCVTB = 40
+ARM_INS_VCVTT = 41
+ARM_INS_BFC = 42
+ARM_INS_BFI = 43
+ARM_INS_BIC = 44
+ARM_INS_BKPT = 45
+ARM_INS_BL = 46
+ARM_INS_BLX = 47
+ARM_INS_BX = 48
+ARM_INS_BXJ = 49
+ARM_INS_B = 50
+ARM_INS_CX1 = 51
+ARM_INS_CX1A = 52
+ARM_INS_CX1D = 53
+ARM_INS_CX1DA = 54
+ARM_INS_CX2 = 55
+ARM_INS_CX2A = 56
+ARM_INS_CX2D = 57
+ARM_INS_CX2DA = 58
+ARM_INS_CX3 = 59
+ARM_INS_CX3A = 60
+ARM_INS_CX3D = 61
+ARM_INS_CX3DA = 62
+ARM_INS_VCX1A = 63
+ARM_INS_VCX1 = 64
+ARM_INS_VCX2A = 65
+ARM_INS_VCX2 = 66
+ARM_INS_VCX3A = 67
+ARM_INS_VCX3 = 68
+ARM_INS_CDP = 69
+ARM_INS_CDP2 = 70
+ARM_INS_CLREX = 71
+ARM_INS_CLZ = 72
+ARM_INS_CMN = 73
+ARM_INS_CMP = 74
+ARM_INS_CPS = 75
+ARM_INS_CRC32B = 76
+ARM_INS_CRC32CB = 77
+ARM_INS_CRC32CH = 78
+ARM_INS_CRC32CW = 79
+ARM_INS_CRC32H = 80
+ARM_INS_CRC32W = 81
+ARM_INS_DBG = 82
+ARM_INS_DMB = 83
+ARM_INS_DSB = 84
+ARM_INS_EOR = 85
+ARM_INS_ERET = 86
+ARM_INS_VMOV = 87
+ARM_INS_FLDMDBX = 88
+ARM_INS_FLDMIAX = 89
+ARM_INS_VMRS = 90
+ARM_INS_FSTMDBX = 91
+ARM_INS_FSTMIAX = 92
+ARM_INS_HINT = 93
+ARM_INS_HLT = 94
+ARM_INS_HVC = 95
+ARM_INS_ISB = 96
+ARM_INS_LDA = 97
+ARM_INS_LDAB = 98
+ARM_INS_LDAEX = 99
+ARM_INS_LDAEXB = 100
+ARM_INS_LDAEXD = 101
+ARM_INS_LDAEXH = 102
+ARM_INS_LDAH = 103
+ARM_INS_LDC2L = 104
+ARM_INS_LDC2 = 105
+ARM_INS_LDCL = 106
+ARM_INS_LDC = 107
+ARM_INS_LDMDA = 108
+ARM_INS_LDMDB = 109
+ARM_INS_LDM = 110
+ARM_INS_LDMIB = 111
+ARM_INS_LDRD = 112
+ARM_INS_LDREX = 113
+ARM_INS_LDREXB = 114
+ARM_INS_LDREXD = 115
+ARM_INS_LDREXH = 116
+ARM_INS_MCR = 117
+ARM_INS_MCR2 = 118
+ARM_INS_MCRR = 119
+ARM_INS_MCRR2 = 120
+ARM_INS_MLA = 121
+ARM_INS_MLS = 122
+ARM_INS_MOVT = 123
+ARM_INS_MOVW = 124
+ARM_INS_MRC = 125
+ARM_INS_MRC2 = 126
+ARM_INS_MRRC = 127
+ARM_INS_MRRC2 = 128
+ARM_INS_MRS = 129
+ARM_INS_MSR = 130
+ARM_INS_MUL = 131
+ARM_INS_ASRL = 132
+ARM_INS_DLSTP = 133
+ARM_INS_LCTP = 134
+ARM_INS_LETP = 135
+ARM_INS_LSLL = 136
+ARM_INS_LSRL = 137
+ARM_INS_SQRSHR = 138
+ARM_INS_SQRSHRL = 139
+ARM_INS_SQSHL = 140
+ARM_INS_SQSHLL = 141
+ARM_INS_SRSHR = 142
+ARM_INS_SRSHRL = 143
+ARM_INS_UQRSHL = 144
+ARM_INS_UQRSHLL = 145
+ARM_INS_UQSHL = 146
+ARM_INS_UQSHLL = 147
+ARM_INS_URSHR = 148
+ARM_INS_URSHRL = 149
+ARM_INS_VABAV = 150
+ARM_INS_VABD = 151
+ARM_INS_VABS = 152
+ARM_INS_VADC = 153
+ARM_INS_VADCI = 154
+ARM_INS_VADDLVA = 155
+ARM_INS_VADDLV = 156
+ARM_INS_VADDVA = 157
+ARM_INS_VADDV = 158
+ARM_INS_VADD = 159
+ARM_INS_VAND = 160
+ARM_INS_VBIC = 161
+ARM_INS_VBRSR = 162
+ARM_INS_VCADD = 163
+ARM_INS_VCLS = 164
+ARM_INS_VCLZ = 165
+ARM_INS_VCMLA = 166
+ARM_INS_VCMP = 167
+ARM_INS_VCMUL = 168
+ARM_INS_VCTP = 169
+ARM_INS_VCVTA = 170
+ARM_INS_VCVTM = 171
+ARM_INS_VCVTN = 172
+ARM_INS_VCVTP = 173
+ARM_INS_VDDUP = 174
+ARM_INS_VDUP = 175
+ARM_INS_VDWDUP = 176
+ARM_INS_VEOR = 177
+ARM_INS_VFMAS = 178
+ARM_INS_VFMA = 179
+ARM_INS_VFMS = 180
+ARM_INS_VHADD = 181
+ARM_INS_VHCADD = 182
+ARM_INS_VHSUB = 183
+ARM_INS_VIDUP = 184
+ARM_INS_VIWDUP = 185
+ARM_INS_VLD20 = 186
+ARM_INS_VLD21 = 187
+ARM_INS_VLD40 = 188
+ARM_INS_VLD41 = 189
+ARM_INS_VLD42 = 190
+ARM_INS_VLD43 = 191
+ARM_INS_VLDRB = 192
+ARM_INS_VLDRD = 193
+ARM_INS_VLDRH = 194
+ARM_INS_VLDRW = 195
+ARM_INS_VMAXAV = 196
+ARM_INS_VMAXA = 197
+ARM_INS_VMAXNMAV = 198
+ARM_INS_VMAXNMA = 199
+ARM_INS_VMAXNMV = 200
+ARM_INS_VMAXNM = 201
+ARM_INS_VMAXV = 202
+ARM_INS_VMAX = 203
+ARM_INS_VMINAV = 204
+ARM_INS_VMINA = 205
+ARM_INS_VMINNMAV = 206
+ARM_INS_VMINNMA = 207
+ARM_INS_VMINNMV = 208
+ARM_INS_VMINNM = 209
+ARM_INS_VMINV = 210
+ARM_INS_VMIN = 211
+ARM_INS_VMLADAVA = 212
+ARM_INS_VMLADAVAX = 213
+ARM_INS_VMLADAV = 214
+ARM_INS_VMLADAVX = 215
+ARM_INS_VMLALDAVA = 216
+ARM_INS_VMLALDAVAX = 217
+ARM_INS_VMLALDAV = 218
+ARM_INS_VMLALDAVX = 219
+ARM_INS_VMLAS = 220
+ARM_INS_VMLA = 221
+ARM_INS_VMLSDAVA = 222
+ARM_INS_VMLSDAVAX = 223
+ARM_INS_VMLSDAV = 224
+ARM_INS_VMLSDAVX = 225
+ARM_INS_VMLSLDAVA = 226
+ARM_INS_VMLSLDAVAX = 227
+ARM_INS_VMLSLDAV = 228
+ARM_INS_VMLSLDAVX = 229
+ARM_INS_VMOVLB = 230
+ARM_INS_VMOVLT = 231
+ARM_INS_VMOVNB = 232
+ARM_INS_VMOVNT = 233
+ARM_INS_VMULH = 234
+ARM_INS_VMULLB = 235
+ARM_INS_VMULLT = 236
+ARM_INS_VMUL = 237
+ARM_INS_VMVN = 238
+ARM_INS_VNEG = 239
+ARM_INS_VORN = 240
+ARM_INS_VORR = 241
+ARM_INS_VPNOT = 242
+ARM_INS_VPSEL = 243
+ARM_INS_VPST = 244
+ARM_INS_VPT = 245
+ARM_INS_VQABS = 246
+ARM_INS_VQADD = 247
+ARM_INS_VQDMLADHX = 248
+ARM_INS_VQDMLADH = 249
+ARM_INS_VQDMLAH = 250
+ARM_INS_VQDMLASH = 251
+ARM_INS_VQDMLSDHX = 252
+ARM_INS_VQDMLSDH = 253
+ARM_INS_VQDMULH = 254
+ARM_INS_VQDMULLB = 255
+ARM_INS_VQDMULLT = 256
+ARM_INS_VQMOVNB = 257
+ARM_INS_VQMOVNT = 258
+ARM_INS_VQMOVUNB = 259
+ARM_INS_VQMOVUNT = 260
+ARM_INS_VQNEG = 261
+ARM_INS_VQRDMLADHX = 262
+ARM_INS_VQRDMLADH = 263
+ARM_INS_VQRDMLAH = 264
+ARM_INS_VQRDMLASH = 265
+ARM_INS_VQRDMLSDHX = 266
+ARM_INS_VQRDMLSDH = 267
+ARM_INS_VQRDMULH = 268
+ARM_INS_VQRSHL = 269
+ARM_INS_VQRSHRNB = 270
+ARM_INS_VQRSHRNT = 271
+ARM_INS_VQRSHRUNB = 272
+ARM_INS_VQRSHRUNT = 273
+ARM_INS_VQSHLU = 274
+ARM_INS_VQSHL = 275
+ARM_INS_VQSHRNB = 276
+ARM_INS_VQSHRNT = 277
+ARM_INS_VQSHRUNB = 278
+ARM_INS_VQSHRUNT = 279
+ARM_INS_VQSUB = 280
+ARM_INS_VREV16 = 281
+ARM_INS_VREV32 = 282
+ARM_INS_VREV64 = 283
+ARM_INS_VRHADD = 284
+ARM_INS_VRINTA = 285
+ARM_INS_VRINTM = 286
+ARM_INS_VRINTN = 287
+ARM_INS_VRINTP = 288
+ARM_INS_VRINTX = 289
+ARM_INS_VRINTZ = 290
+ARM_INS_VRMLALDAVHA = 291
+ARM_INS_VRMLALDAVHAX = 292
+ARM_INS_VRMLALDAVH = 293
+ARM_INS_VRMLALDAVHX = 294
+ARM_INS_VRMLSLDAVHA = 295
+ARM_INS_VRMLSLDAVHAX = 296
+ARM_INS_VRMLSLDAVH = 297
+ARM_INS_VRMLSLDAVHX = 298
+ARM_INS_VRMULH = 299
+ARM_INS_VRSHL = 300
+ARM_INS_VRSHRNB = 301
+ARM_INS_VRSHRNT = 302
+ARM_INS_VRSHR = 303
+ARM_INS_VSBC = 304
+ARM_INS_VSBCI = 305
+ARM_INS_VSHLC = 306
+ARM_INS_VSHLLB = 307
+ARM_INS_VSHLLT = 308
+ARM_INS_VSHL = 309
+ARM_INS_VSHRNB = 310
+ARM_INS_VSHRNT = 311
+ARM_INS_VSHR = 312
+ARM_INS_VSLI = 313
+ARM_INS_VSRI = 314
+ARM_INS_VST20 = 315
+ARM_INS_VST21 = 316
+ARM_INS_VST40 = 317
+ARM_INS_VST41 = 318
+ARM_INS_VST42 = 319
+ARM_INS_VST43 = 320
+ARM_INS_VSTRB = 321
+ARM_INS_VSTRD = 322
+ARM_INS_VSTRH = 323
+ARM_INS_VSTRW = 324
+ARM_INS_VSUB = 325
+ARM_INS_WLSTP = 326
+ARM_INS_MVN = 327
+ARM_INS_ORR = 328
+ARM_INS_PKHBT = 329
+ARM_INS_PKHTB = 330
+ARM_INS_PLDW = 331
+ARM_INS_PLD = 332
+ARM_INS_PLI = 333
+ARM_INS_QADD = 334
+ARM_INS_QADD16 = 335
+ARM_INS_QADD8 = 336
+ARM_INS_QASX = 337
+ARM_INS_QDADD = 338
+ARM_INS_QDSUB = 339
+ARM_INS_QSAX = 340
+ARM_INS_QSUB = 341
+ARM_INS_QSUB16 = 342
+ARM_INS_QSUB8 = 343
+ARM_INS_RBIT = 344
+ARM_INS_REV = 345
+ARM_INS_REV16 = 346
+ARM_INS_REVSH = 347
+ARM_INS_RFEDA = 348
+ARM_INS_RFEDB = 349
+ARM_INS_RFEIA = 350
+ARM_INS_RFEIB = 351
+ARM_INS_RSB = 352
+ARM_INS_RSC = 353
+ARM_INS_SADD16 = 354
+ARM_INS_SADD8 = 355
+ARM_INS_SASX = 356
+ARM_INS_SB = 357
+ARM_INS_SBC = 358
+ARM_INS_SBFX = 359
+ARM_INS_SDIV = 360
+ARM_INS_SEL = 361
+ARM_INS_SETEND = 362
+ARM_INS_SETPAN = 363
+ARM_INS_SHA1C = 364
+ARM_INS_SHA1H = 365
+ARM_INS_SHA1M = 366
+ARM_INS_SHA1P = 367
+ARM_INS_SHA1SU0 = 368
+ARM_INS_SHA1SU1 = 369
+ARM_INS_SHA256H = 370
+ARM_INS_SHA256H2 = 371
+ARM_INS_SHA256SU0 = 372
+ARM_INS_SHA256SU1 = 373
+ARM_INS_SHADD16 = 374
+ARM_INS_SHADD8 = 375
+ARM_INS_SHASX = 376
+ARM_INS_SHSAX = 377
+ARM_INS_SHSUB16 = 378
+ARM_INS_SHSUB8 = 379
+ARM_INS_SMC = 380
+ARM_INS_SMLABB = 381
+ARM_INS_SMLABT = 382
+ARM_INS_SMLAD = 383
+ARM_INS_SMLADX = 384
+ARM_INS_SMLAL = 385
+ARM_INS_SMLALBB = 386
+ARM_INS_SMLALBT = 387
+ARM_INS_SMLALD = 388
+ARM_INS_SMLALDX = 389
+ARM_INS_SMLALTB = 390
+ARM_INS_SMLALTT = 391
+ARM_INS_SMLATB = 392
+ARM_INS_SMLATT = 393
+ARM_INS_SMLAWB = 394
+ARM_INS_SMLAWT = 395
+ARM_INS_SMLSD = 396
+ARM_INS_SMLSDX = 397
+ARM_INS_SMLSLD = 398
+ARM_INS_SMLSLDX = 399
+ARM_INS_SMMLA = 400
+ARM_INS_SMMLAR = 401
+ARM_INS_SMMLS = 402
+ARM_INS_SMMLSR = 403
+ARM_INS_SMMUL = 404
+ARM_INS_SMMULR = 405
+ARM_INS_SMUAD = 406
+ARM_INS_SMUADX = 407
+ARM_INS_SMULBB = 408
+ARM_INS_SMULBT = 409
+ARM_INS_SMULL = 410
+ARM_INS_SMULTB = 411
+ARM_INS_SMULTT = 412
+ARM_INS_SMULWB = 413
+ARM_INS_SMULWT = 414
+ARM_INS_SMUSD = 415
+ARM_INS_SMUSDX = 416
+ARM_INS_SRSDA = 417
+ARM_INS_SRSDB = 418
+ARM_INS_SRSIA = 419
+ARM_INS_SRSIB = 420
+ARM_INS_SSAT = 421
+ARM_INS_SSAT16 = 422
+ARM_INS_SSAX = 423
+ARM_INS_SSUB16 = 424
+ARM_INS_SSUB8 = 425
+ARM_INS_STC2L = 426
+ARM_INS_STC2 = 427
+ARM_INS_STCL = 428
+ARM_INS_STC = 429
+ARM_INS_STL = 430
+ARM_INS_STLB = 431
+ARM_INS_STLEX = 432
+ARM_INS_STLEXB = 433
+ARM_INS_STLEXD = 434
+ARM_INS_STLEXH = 435
+ARM_INS_STLH = 436
+ARM_INS_STMDA = 437
+ARM_INS_STMDB = 438
+ARM_INS_STM = 439
+ARM_INS_STMIB = 440
+ARM_INS_STRB = 441
+ARM_INS_STRD = 442
+ARM_INS_STREX = 443
+ARM_INS_STREXB = 444
+ARM_INS_STREXD = 445
+ARM_INS_STREXH = 446
+ARM_INS_STRH = 447
+ARM_INS_STRHT = 448
+ARM_INS_SUB = 449
+ARM_INS_SVC = 450
+ARM_INS_SWP = 451
+ARM_INS_SWPB = 452
+ARM_INS_SXTAB = 453
+ARM_INS_SXTAB16 = 454
+ARM_INS_SXTAH = 455
+ARM_INS_SXTB = 456
+ARM_INS_SXTB16 = 457
+ARM_INS_SXTH = 458
+ARM_INS_TEQ = 459
+ARM_INS_TRAP = 460
+ARM_INS_TSB = 461
+ARM_INS_TST = 462
+ARM_INS_UADD16 = 463
+ARM_INS_UADD8 = 464
+ARM_INS_UASX = 465
+ARM_INS_UBFX = 466
+ARM_INS_UDF = 467
+ARM_INS_UDIV = 468
+ARM_INS_UHADD16 = 469
+ARM_INS_UHADD8 = 470
+ARM_INS_UHASX = 471
+ARM_INS_UHSAX = 472
+ARM_INS_UHSUB16 = 473
+ARM_INS_UHSUB8 = 474
+ARM_INS_UMAAL = 475
+ARM_INS_UMLAL = 476
+ARM_INS_UMULL = 477
+ARM_INS_UQADD16 = 478
+ARM_INS_UQADD8 = 479
+ARM_INS_UQASX = 480
+ARM_INS_UQSAX = 481
+ARM_INS_UQSUB16 = 482
+ARM_INS_UQSUB8 = 483
+ARM_INS_USAD8 = 484
+ARM_INS_USADA8 = 485
+ARM_INS_USAT = 486
+ARM_INS_USAT16 = 487
+ARM_INS_USAX = 488
+ARM_INS_USUB16 = 489
+ARM_INS_USUB8 = 490
+ARM_INS_UXTAB = 491
+ARM_INS_UXTAB16 = 492
+ARM_INS_UXTAH = 493
+ARM_INS_UXTB = 494
+ARM_INS_UXTB16 = 495
+ARM_INS_UXTH = 496
+ARM_INS_VABAL = 497
+ARM_INS_VABA = 498
+ARM_INS_VABDL = 499
+ARM_INS_VACGE = 500
+ARM_INS_VACGT = 501
+ARM_INS_VADDHN = 502
+ARM_INS_VADDL = 503
+ARM_INS_VADDW = 504
+ARM_INS_VFMAB = 505
+ARM_INS_VFMAT = 506
+ARM_INS_VBIF = 507
+ARM_INS_VBIT = 508
+ARM_INS_VBSL = 509
+ARM_INS_VCEQ = 510
+ARM_INS_VCGE = 511
+ARM_INS_VCGT = 512
+ARM_INS_VCLE = 513
+ARM_INS_VCLT = 514
+ARM_INS_VCMPE = 515
+ARM_INS_VCNT = 516
+ARM_INS_VDIV = 517
+ARM_INS_VEXT = 518
+ARM_INS_VFMAL = 519
+ARM_INS_VFMSL = 520
+ARM_INS_VFNMA = 521
+ARM_INS_VFNMS = 522
+ARM_INS_VINS = 523
+ARM_INS_VJCVT = 524
+ARM_INS_VLDMDB = 525
+ARM_INS_VLDMIA = 526
+ARM_INS_VLDR = 527
+ARM_INS_VLLDM = 528
+ARM_INS_VLSTM = 529
+ARM_INS_VMLAL = 530
+ARM_INS_VMLS = 531
+ARM_INS_VMLSL = 532
+ARM_INS_VMMLA = 533
+ARM_INS_VMOVX = 534
+ARM_INS_VMOVL = 535
+ARM_INS_VMOVN = 536
+ARM_INS_VMSR = 537
+ARM_INS_VMULL = 538
+ARM_INS_VNMLA = 539
+ARM_INS_VNMLS = 540
+ARM_INS_VNMUL = 541
+ARM_INS_VPADAL = 542
+ARM_INS_VPADDL = 543
+ARM_INS_VPADD = 544
+ARM_INS_VPMAX = 545
+ARM_INS_VPMIN = 546
+ARM_INS_VQDMLAL = 547
+ARM_INS_VQDMLSL = 548
+ARM_INS_VQDMULL = 549
+ARM_INS_VQMOVUN = 550
+ARM_INS_VQMOVN = 551
+ARM_INS_VQRDMLSH = 552
+ARM_INS_VQRSHRN = 553
+ARM_INS_VQRSHRUN = 554
+ARM_INS_VQSHRN = 555
+ARM_INS_VQSHRUN = 556
+ARM_INS_VRADDHN = 557
+ARM_INS_VRECPE = 558
+ARM_INS_VRECPS = 559
+ARM_INS_VRINTR = 560
+ARM_INS_VRSHRN = 561
+ARM_INS_VRSQRTE = 562
+ARM_INS_VRSQRTS = 563
+ARM_INS_VRSRA = 564
+ARM_INS_VRSUBHN = 565
+ARM_INS_VSCCLRM = 566
+ARM_INS_VSDOT = 567
+ARM_INS_VSELEQ = 568
+ARM_INS_VSELGE = 569
+ARM_INS_VSELGT = 570
+ARM_INS_VSELVS = 571
+ARM_INS_VSHLL = 572
+ARM_INS_VSHRN = 573
+ARM_INS_VSMMLA = 574
+ARM_INS_VSQRT = 575
+ARM_INS_VSRA = 576
+ARM_INS_VSTMDB = 577
+ARM_INS_VSTMIA = 578
+ARM_INS_VSTR = 579
+ARM_INS_VSUBHN = 580
+ARM_INS_VSUBL = 581
+ARM_INS_VSUBW = 582
+ARM_INS_VSUDOT = 583
+ARM_INS_VSWP = 584
+ARM_INS_VTBL = 585
+ARM_INS_VTBX = 586
+ARM_INS_VCVTR = 587
+ARM_INS_VTRN = 588
+ARM_INS_VTST = 589
+ARM_INS_VUDOT = 590
+ARM_INS_VUMMLA = 591
+ARM_INS_VUSDOT = 592
+ARM_INS_VUSMMLA = 593
+ARM_INS_VUZP = 594
+ARM_INS_VZIP = 595
+ARM_INS_ADDW = 596
+ARM_INS_AUT = 597
+ARM_INS_AUTG = 598
+ARM_INS_BFL = 599
+ARM_INS_BFLX = 600
+ARM_INS_BF = 601
+ARM_INS_BFCSEL = 602
+ARM_INS_BFX = 603
+ARM_INS_BTI = 604
+ARM_INS_BXAUT = 605
+ARM_INS_CLRM = 606
+ARM_INS_CSEL = 607
+ARM_INS_CSINC = 608
+ARM_INS_CSINV = 609
+ARM_INS_CSNEG = 610
+ARM_INS_DCPS1 = 611
+ARM_INS_DCPS2 = 612
+ARM_INS_DCPS3 = 613
+ARM_INS_DLS = 614
+ARM_INS_LE = 615
+ARM_INS_ORN = 616
+ARM_INS_PAC = 617
+ARM_INS_PACBTI = 618
+ARM_INS_PACG = 619
+ARM_INS_SG = 620
+ARM_INS_SUBS = 621
+ARM_INS_SUBW = 622
+ARM_INS_TBB = 623
+ARM_INS_TBH = 624
+ARM_INS_TT = 625
+ARM_INS_TTA = 626
+ARM_INS_TTAT = 627
+ARM_INS_TTT = 628
+ARM_INS_WLS = 629
+ARM_INS_BLXNS = 630
+ARM_INS_BXNS = 631
+ARM_INS_CBNZ = 632
+ARM_INS_CBZ = 633
+ARM_INS_POP = 634
+ARM_INS_PUSH = 635
+ARM_INS___BRKDIV0 = 636
+ARM_INS_ENDING = 637
+ARM_INS_ALIAS_BEGIN = 638
+ARM_INS_ALIAS_VMOV = 639
+ARM_INS_ALIAS_NOP = 640
+ARM_INS_ALIAS_YIELD = 641
+ARM_INS_ALIAS_WFE = 642
+ARM_INS_ALIAS_WFI = 643
+ARM_INS_ALIAS_SEV = 644
+ARM_INS_ALIAS_SEVL = 645
+ARM_INS_ALIAS_ESB = 646
+ARM_INS_ALIAS_CSDB = 647
+ARM_INS_ALIAS_CLRBHB = 648
+ARM_INS_ALIAS_PACBTI = 649
+ARM_INS_ALIAS_BTI = 650
+ARM_INS_ALIAS_PAC = 651
+ARM_INS_ALIAS_AUT = 652
+ARM_INS_ALIAS_SSBB = 653
+ARM_INS_ALIAS_PSSBB = 654
+ARM_INS_ALIAS_DFB = 655
+ARM_INS_ALIAS_CSETM = 656
+ARM_INS_ALIAS_CSET = 657
+ARM_INS_ALIAS_CINC = 658
+ARM_INS_ALIAS_CINV = 659
+ARM_INS_ALIAS_CNEG = 660
+ARM_INS_ALIAS_VMLAV = 661
+ARM_INS_ALIAS_VMLAVA = 662
+ARM_INS_ALIAS_VRMLALVH = 663
+ARM_INS_ALIAS_VRMLALVHA = 664
+ARM_INS_ALIAS_VMLALV = 665
+ARM_INS_ALIAS_VMLALVA = 666
+ARM_INS_ALIAS_VBIC = 667
+ARM_INS_ALIAS_VEOR = 668
+ARM_INS_ALIAS_VORN = 669
+ARM_INS_ALIAS_VORR = 670
+ARM_INS_ALIAS_VAND = 671
+ARM_INS_ALIAS_VPSEL = 672
+ARM_INS_ALIAS_ERET = 673
+ARM_INS_ALIAS_ASR = 674
+ARM_INS_ALIAS_LSL = 675
+ARM_INS_ALIAS_LSR = 676
+ARM_INS_ALIAS_ROR = 677
+ARM_INS_ALIAS_RRX = 678
+ARM_INS_ALIAS_UXTW = 679
+ARM_INS_ALIAS_LDM = 680
+ARM_INS_ALIAS_POP = 681
+ARM_INS_ALIAS_PUSH = 682
+ARM_INS_ALIAS_POPW = 683
+ARM_INS_ALIAS_PUSHW = 684
+ARM_INS_ALIAS_VPOP = 685
+ARM_INS_ALIAS_VPUSH = 686
+ARM_INS_ALIAS_END = 687
 
 ARM_GRP_INVALID = 0
 ARM_GRP_JUMP = 1
diff --git a/bindings/python/capstone/loongarch.py b/bindings/python/capstone/loongarch.py
new file mode 100644
index 000000000..df4f09b55
--- /dev/null
+++ b/bindings/python/capstone/loongarch.py
@@ -0,0 +1,55 @@
+# Copyright © 2024 Rot127 <unisono@quyllur.org>
+# SPDX-License-Identifier: BSD-3
+
+import ctypes
+from . import copy_ctypes_list
+from .loongarch_const import *
+
+
+class LoongArchOpMem(ctypes.Structure):
+    _fields_ = (
+        ("base", ctypes.c_uint),
+        ("index", ctypes.c_uint),
+        ("disp", ctypes.c_int64),
+    )
+
+
+class LoongArchOpValue(ctypes.Union):
+    _fields_ = (
+        ("reg", ctypes.c_uint),
+        ("imm", ctypes.c_int64),
+        ("mem", LoongArchOpMem),
+    )
+
+
+class LoongArchOp(ctypes.Structure):
+    _fields_ = (
+        ("type", ctypes.c_uint8),
+        ("value", LoongArchOpValue),
+        ("access", ctypes.c_uint8),
+    )
+
+    @property
+    def imm(self):
+        return self.value.imm
+
+    @property
+    def reg(self):
+        return self.value.reg
+
+    @property
+    def mem(self):
+        return self.value.mem
+
+
+# Instruction structure
+class CsLoongArch(ctypes.Structure):
+    _fields_ = (
+        ("format", ctypes.c_int),
+        ("op_count", ctypes.c_uint8),
+        ("operands", LoongArchOp * 8)
+    )
+
+
+def get_arch_info(a):
+    return a.format, copy_ctypes_list(a.operands[: a.op_count])
diff --git a/bindings/python/capstone/loongarch_const.py b/bindings/python/capstone/loongarch_const.py
new file mode 100644
index 000000000..c2c953d42
--- /dev/null
+++ b/bindings/python/capstone/loongarch_const.py
@@ -0,0 +1,2401 @@
+from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_FP, CS_OP_PRED, CS_OP_SPECIAL, CS_OP_MEM, CS_OP_MEM_REG, CS_OP_MEM_IMM, UINT16_MAX
+# For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [loongarch_const.py]
+LOONGARCH_OP_INVALID = CS_OP_INVALID
+LOONGARCH_OP_REG = CS_OP_REG
+LOONGARCH_OP_IMM = CS_OP_IMM
+LOONGARCH_OP_MEM = CS_OP_MEM
+
+LOONGARCH_INSN_FORM_PSEUDO = 0
+LOONGARCH_INSN_FORM_FMT3R = 1
+LOONGARCH_INSN_FORM_FMT2RI12 = 2
+LOONGARCH_INSN_FORM_FMT2RI5 = 3
+LOONGARCH_INSN_FORM_FMT2RI16 = 4
+LOONGARCH_INSN_FORM_FMT3RI2 = 5
+LOONGARCH_INSN_FORM_NODSTFMT2RI4 = 6
+LOONGARCH_INSN_FORM_FMT1RI8 = 7
+LOONGARCH_INSN_FORM_FMT2RI4 = 8
+LOONGARCH_INSN_FORM_NODSTFMT1RI4 = 9
+LOONGARCH_INSN_FORM_NODSTFMT1RI5I4 = 10
+LOONGARCH_INSN_FORM_FMTASRT = 11
+LOONGARCH_INSN_FORM_FMTI26 = 12
+LOONGARCH_INSN_FORM_FPFMTBR = 13
+LOONGARCH_INSN_FORM_FMT1RI21 = 14
+LOONGARCH_INSN_FORM_FMT2R = 15
+LOONGARCH_INSN_FORM_FMTI15 = 16
+LOONGARCH_INSN_FORM_FMTBSTR_D = 17
+LOONGARCH_INSN_FORM_FMTBSTR_W = 18
+LOONGARCH_INSN_FORM_FMT3RI3 = 19
+LOONGARCH_INSN_FORM_FMTCACOP = 20
+LOONGARCH_INSN_FORM_FMTCSR = 21
+LOONGARCH_INSN_FORM_FMTCSRXCHG = 22
+LOONGARCH_INSN_FORM_FMTI32 = 23
+LOONGARCH_INSN_FORM_FPFMT2R = 24
+LOONGARCH_INSN_FORM_FPFMT3R = 25
+LOONGARCH_INSN_FORM_FPFMTFCMP = 26
+LOONGARCH_INSN_FORM_FPFMTMEM = 27
+LOONGARCH_INSN_FORM_FPFMT2RI12 = 28
+LOONGARCH_INSN_FORM_FPFMT4R = 29
+LOONGARCH_INSN_FORM_FPFMTMOV = 30
+LOONGARCH_INSN_FORM_FPFMTFSEL = 31
+LOONGARCH_INSN_FORM_FMTINVTLB = 32
+LOONGARCH_INSN_FORM_FMTJISCR = 33
+LOONGARCH_INSN_FORM_FMT2RI8 = 34
+LOONGARCH_INSN_FORM_FMTLDPTE = 35
+LOONGARCH_INSN_FORM_FMT2RI14 = 36
+LOONGARCH_INSN_FORM_FMT1RI20 = 37
+LOONGARCH_INSN_FORM_FMTGR2SCR = 38
+LOONGARCH_INSN_FORM_FMTSCR2GR = 39
+LOONGARCH_INSN_FORM_FMTPRELD = 40
+LOONGARCH_INSN_FORM_FMTPRELDX = 41
+LOONGARCH_INSN_FORM_FMT2RI3 = 42
+LOONGARCH_INSN_FORM_FMT2RI6 = 43
+LOONGARCH_INSN_FORM_FMT1RI4 = 44
+LOONGARCH_INSN_FORM_FMT3R_VVV = 45
+LOONGARCH_INSN_FORM_FMT2RI5_VVI = 46
+LOONGARCH_INSN_FORM_FMT2RI8_VVI = 47
+LOONGARCH_INSN_FORM_FMT2RI3_VVI = 48
+LOONGARCH_INSN_FORM_FMT2RI6_VVI = 49
+LOONGARCH_INSN_FORM_FMT2RI4_VVI = 50
+LOONGARCH_INSN_FORM_FMT4R_VVVV = 51
+LOONGARCH_INSN_FORM_FMT2R_VV = 52
+LOONGARCH_INSN_FORM_FMT2R_XX = 53
+LOONGARCH_INSN_FORM_FMT2RI4_VRI = 54
+LOONGARCH_INSN_FORM_FMT2RI1_VRI = 55
+LOONGARCH_INSN_FORM_FMT2RI3_VRI = 56
+LOONGARCH_INSN_FORM_FMT2RI2_VRI = 57
+LOONGARCH_INSN_FORM_FMT2RI12_VRI = 58
+LOONGARCH_INSN_FORM_FMT1RI13_VI = 59
+LOONGARCH_INSN_FORM_FMT2RI9_VRI = 60
+LOONGARCH_INSN_FORM_FMT2RI11_VRI = 61
+LOONGARCH_INSN_FORM_FMT2RI10_VRI = 62
+LOONGARCH_INSN_FORM_FMT3R_VRR = 63
+LOONGARCH_INSN_FORM_FMT2RI4_RVI = 64
+LOONGARCH_INSN_FORM_FMT2RI1_RVI = 65
+LOONGARCH_INSN_FORM_FMT2RI3_RVI = 66
+LOONGARCH_INSN_FORM_FMT2RI2_RVI = 67
+LOONGARCH_INSN_FORM_FMT2R_VR = 68
+LOONGARCH_INSN_FORM_FMT2RI1_VVI = 69
+LOONGARCH_INSN_FORM_FMT2RI2_VVI = 70
+LOONGARCH_INSN_FORM_FMT3R_VVR = 71
+LOONGARCH_INSN_FORM_FMT2R_CV = 72
+LOONGARCH_INSN_FORM_FMT2RI7_VVI = 73
+LOONGARCH_INSN_FORM_FMT2RI8I4_VRII = 74
+LOONGARCH_INSN_FORM_FMT2RI8I1_VRII = 75
+LOONGARCH_INSN_FORM_FMT2RI8I3_VRII = 76
+LOONGARCH_INSN_FORM_FMT2RI8I2_VRII = 77
+LOONGARCH_INSN_FORM_NODSTFMT2R = 78
+LOONGARCH_INSN_FORM_NODSTFMT1R = 79
+LOONGARCH_INSN_FORM_FMTMFTOP = 80
+LOONGARCH_INSN_FORM_FMTMTTOP = 81
+LOONGARCH_INSN_FORM_NODSTFMT1RI3 = 82
+LOONGARCH_INSN_FORM_NODSTFMT1RI6 = 83
+LOONGARCH_INSN_FORM_NODSTFMT1RI5 = 84
+LOONGARCH_INSN_FORM_FMT1RI5I8 = 85
+LOONGARCH_INSN_FORM_FMT3R_XXX = 86
+LOONGARCH_INSN_FORM_FMT2RI5_XXI = 87
+LOONGARCH_INSN_FORM_FMT2RI8_XXI = 88
+LOONGARCH_INSN_FORM_FMT2RI3_XXI = 89
+LOONGARCH_INSN_FORM_FMT2RI6_XXI = 90
+LOONGARCH_INSN_FORM_FMT2RI4_XXI = 91
+LOONGARCH_INSN_FORM_FMT4R_XXXX = 92
+LOONGARCH_INSN_FORM_FMT2RI2_XRI = 93
+LOONGARCH_INSN_FORM_FMT2RI3_XRI = 94
+LOONGARCH_INSN_FORM_FMT2RI2_XXI = 95
+LOONGARCH_INSN_FORM_FMT2RI12_XRI = 96
+LOONGARCH_INSN_FORM_FMT1RI13_XI = 97
+LOONGARCH_INSN_FORM_FMT2RI9_XRI = 98
+LOONGARCH_INSN_FORM_FMT2RI11_XRI = 99
+LOONGARCH_INSN_FORM_FMT2RI10_XRI = 100
+LOONGARCH_INSN_FORM_FMT3R_XRR = 101
+LOONGARCH_INSN_FORM_FMT2RI2_RXI = 102
+LOONGARCH_INSN_FORM_FMT2RI3_RXI = 103
+LOONGARCH_INSN_FORM_FMT2RI1_XXI = 104
+LOONGARCH_INSN_FORM_FMT2R_XR = 105
+LOONGARCH_INSN_FORM_FMT3R_XXR = 106
+LOONGARCH_INSN_FORM_FMT2R_CX = 107
+LOONGARCH_INSN_FORM_FMT2RI7_XXI = 108
+LOONGARCH_INSN_FORM_FMT2RI8I5_XRII = 109
+LOONGARCH_INSN_FORM_FMT2RI8I2_XRII = 110
+LOONGARCH_INSN_FORM_FMT2RI8I4_XRII = 111
+LOONGARCH_INSN_FORM_FMT2RI8I3_XRII = 112
+
+LOONGARCH_REG_INVALID = 0
+LOONGARCH_REG_F0 = 1
+LOONGARCH_REG_F1 = 2
+LOONGARCH_REG_F2 = 3
+LOONGARCH_REG_F3 = 4
+LOONGARCH_REG_F4 = 5
+LOONGARCH_REG_F5 = 6
+LOONGARCH_REG_F6 = 7
+LOONGARCH_REG_F7 = 8
+LOONGARCH_REG_F8 = 9
+LOONGARCH_REG_F9 = 10
+LOONGARCH_REG_F10 = 11
+LOONGARCH_REG_F11 = 12
+LOONGARCH_REG_F12 = 13
+LOONGARCH_REG_F13 = 14
+LOONGARCH_REG_F14 = 15
+LOONGARCH_REG_F15 = 16
+LOONGARCH_REG_F16 = 17
+LOONGARCH_REG_F17 = 18
+LOONGARCH_REG_F18 = 19
+LOONGARCH_REG_F19 = 20
+LOONGARCH_REG_F20 = 21
+LOONGARCH_REG_F21 = 22
+LOONGARCH_REG_F22 = 23
+LOONGARCH_REG_F23 = 24
+LOONGARCH_REG_F24 = 25
+LOONGARCH_REG_F25 = 26
+LOONGARCH_REG_F26 = 27
+LOONGARCH_REG_F27 = 28
+LOONGARCH_REG_F28 = 29
+LOONGARCH_REG_F29 = 30
+LOONGARCH_REG_F30 = 31
+LOONGARCH_REG_F31 = 32
+LOONGARCH_REG_FCC0 = 33
+LOONGARCH_REG_FCC1 = 34
+LOONGARCH_REG_FCC2 = 35
+LOONGARCH_REG_FCC3 = 36
+LOONGARCH_REG_FCC4 = 37
+LOONGARCH_REG_FCC5 = 38
+LOONGARCH_REG_FCC6 = 39
+LOONGARCH_REG_FCC7 = 40
+LOONGARCH_REG_FCSR0 = 41
+LOONGARCH_REG_FCSR1 = 42
+LOONGARCH_REG_FCSR2 = 43
+LOONGARCH_REG_FCSR3 = 44
+LOONGARCH_REG_R0 = 45
+LOONGARCH_REG_R1 = 46
+LOONGARCH_REG_R2 = 47
+LOONGARCH_REG_R3 = 48
+LOONGARCH_REG_R4 = 49
+LOONGARCH_REG_R5 = 50
+LOONGARCH_REG_R6 = 51
+LOONGARCH_REG_R7 = 52
+LOONGARCH_REG_R8 = 53
+LOONGARCH_REG_R9 = 54
+LOONGARCH_REG_R10 = 55
+LOONGARCH_REG_R11 = 56
+LOONGARCH_REG_R12 = 57
+LOONGARCH_REG_R13 = 58
+LOONGARCH_REG_R14 = 59
+LOONGARCH_REG_R15 = 60
+LOONGARCH_REG_R16 = 61
+LOONGARCH_REG_R17 = 62
+LOONGARCH_REG_R18 = 63
+LOONGARCH_REG_R19 = 64
+LOONGARCH_REG_R20 = 65
+LOONGARCH_REG_R21 = 66
+LOONGARCH_REG_R22 = 67
+LOONGARCH_REG_R23 = 68
+LOONGARCH_REG_R24 = 69
+LOONGARCH_REG_R25 = 70
+LOONGARCH_REG_R26 = 71
+LOONGARCH_REG_R27 = 72
+LOONGARCH_REG_R28 = 73
+LOONGARCH_REG_R29 = 74
+LOONGARCH_REG_R30 = 75
+LOONGARCH_REG_R31 = 76
+LOONGARCH_REG_SCR0 = 77
+LOONGARCH_REG_SCR1 = 78
+LOONGARCH_REG_SCR2 = 79
+LOONGARCH_REG_SCR3 = 80
+LOONGARCH_REG_VR0 = 81
+LOONGARCH_REG_VR1 = 82
+LOONGARCH_REG_VR2 = 83
+LOONGARCH_REG_VR3 = 84
+LOONGARCH_REG_VR4 = 85
+LOONGARCH_REG_VR5 = 86
+LOONGARCH_REG_VR6 = 87
+LOONGARCH_REG_VR7 = 88
+LOONGARCH_REG_VR8 = 89
+LOONGARCH_REG_VR9 = 90
+LOONGARCH_REG_VR10 = 91
+LOONGARCH_REG_VR11 = 92
+LOONGARCH_REG_VR12 = 93
+LOONGARCH_REG_VR13 = 94
+LOONGARCH_REG_VR14 = 95
+LOONGARCH_REG_VR15 = 96
+LOONGARCH_REG_VR16 = 97
+LOONGARCH_REG_VR17 = 98
+LOONGARCH_REG_VR18 = 99
+LOONGARCH_REG_VR19 = 100
+LOONGARCH_REG_VR20 = 101
+LOONGARCH_REG_VR21 = 102
+LOONGARCH_REG_VR22 = 103
+LOONGARCH_REG_VR23 = 104
+LOONGARCH_REG_VR24 = 105
+LOONGARCH_REG_VR25 = 106
+LOONGARCH_REG_VR26 = 107
+LOONGARCH_REG_VR27 = 108
+LOONGARCH_REG_VR28 = 109
+LOONGARCH_REG_VR29 = 110
+LOONGARCH_REG_VR30 = 111
+LOONGARCH_REG_VR31 = 112
+LOONGARCH_REG_XR0 = 113
+LOONGARCH_REG_XR1 = 114
+LOONGARCH_REG_XR2 = 115
+LOONGARCH_REG_XR3 = 116
+LOONGARCH_REG_XR4 = 117
+LOONGARCH_REG_XR5 = 118
+LOONGARCH_REG_XR6 = 119
+LOONGARCH_REG_XR7 = 120
+LOONGARCH_REG_XR8 = 121
+LOONGARCH_REG_XR9 = 122
+LOONGARCH_REG_XR10 = 123
+LOONGARCH_REG_XR11 = 124
+LOONGARCH_REG_XR12 = 125
+LOONGARCH_REG_XR13 = 126
+LOONGARCH_REG_XR14 = 127
+LOONGARCH_REG_XR15 = 128
+LOONGARCH_REG_XR16 = 129
+LOONGARCH_REG_XR17 = 130
+LOONGARCH_REG_XR18 = 131
+LOONGARCH_REG_XR19 = 132
+LOONGARCH_REG_XR20 = 133
+LOONGARCH_REG_XR21 = 134
+LOONGARCH_REG_XR22 = 135
+LOONGARCH_REG_XR23 = 136
+LOONGARCH_REG_XR24 = 137
+LOONGARCH_REG_XR25 = 138
+LOONGARCH_REG_XR26 = 139
+LOONGARCH_REG_XR27 = 140
+LOONGARCH_REG_XR28 = 141
+LOONGARCH_REG_XR29 = 142
+LOONGARCH_REG_XR30 = 143
+LOONGARCH_REG_XR31 = 144
+LOONGARCH_REG_F0_64 = 145
+LOONGARCH_REG_F1_64 = 146
+LOONGARCH_REG_F2_64 = 147
+LOONGARCH_REG_F3_64 = 148
+LOONGARCH_REG_F4_64 = 149
+LOONGARCH_REG_F5_64 = 150
+LOONGARCH_REG_F6_64 = 151
+LOONGARCH_REG_F7_64 = 152
+LOONGARCH_REG_F8_64 = 153
+LOONGARCH_REG_F9_64 = 154
+LOONGARCH_REG_F10_64 = 155
+LOONGARCH_REG_F11_64 = 156
+LOONGARCH_REG_F12_64 = 157
+LOONGARCH_REG_F13_64 = 158
+LOONGARCH_REG_F14_64 = 159
+LOONGARCH_REG_F15_64 = 160
+LOONGARCH_REG_F16_64 = 161
+LOONGARCH_REG_F17_64 = 162
+LOONGARCH_REG_F18_64 = 163
+LOONGARCH_REG_F19_64 = 164
+LOONGARCH_REG_F20_64 = 165
+LOONGARCH_REG_F21_64 = 166
+LOONGARCH_REG_F22_64 = 167
+LOONGARCH_REG_F23_64 = 168
+LOONGARCH_REG_F24_64 = 169
+LOONGARCH_REG_F25_64 = 170
+LOONGARCH_REG_F26_64 = 171
+LOONGARCH_REG_F27_64 = 172
+LOONGARCH_REG_F28_64 = 173
+LOONGARCH_REG_F29_64 = 174
+LOONGARCH_REG_F30_64 = 175
+LOONGARCH_REG_F31_64 = 176
+LOONGARCH_REG_ENDING = 177
+LOONGARCH_REG_ZERO = LOONGARCH_REG_R0
+LOONGARCH_REG_RA = LOONGARCH_REG_R1
+LOONGARCH_REG_TP = LOONGARCH_REG_R2
+LOONGARCH_REG_SP = LOONGARCH_REG_R3
+LOONGARCH_REG_A0 = LOONGARCH_REG_R4
+LOONGARCH_REG_A1 = LOONGARCH_REG_R5
+LOONGARCH_REG_A2 = LOONGARCH_REG_R6
+LOONGARCH_REG_A3 = LOONGARCH_REG_R7
+LOONGARCH_REG_A4 = LOONGARCH_REG_R8
+LOONGARCH_REG_A5 = LOONGARCH_REG_R9
+LOONGARCH_REG_A6 = LOONGARCH_REG_R10
+LOONGARCH_REG_A7 = LOONGARCH_REG_R11
+LOONGARCH_REG_T0 = LOONGARCH_REG_R12
+LOONGARCH_REG_T1 = LOONGARCH_REG_R13
+LOONGARCH_REG_T2 = LOONGARCH_REG_R14
+LOONGARCH_REG_T3 = LOONGARCH_REG_R15
+LOONGARCH_REG_T4 = LOONGARCH_REG_R16
+LOONGARCH_REG_T5 = LOONGARCH_REG_R17
+LOONGARCH_REG_T6 = LOONGARCH_REG_R18
+LOONGARCH_REG_T7 = LOONGARCH_REG_R19
+LOONGARCH_REG_T8 = LOONGARCH_REG_R20
+LOONGARCH_REG_FP = LOONGARCH_REG_R22
+LOONGARCH_REG_S9 = LOONGARCH_REG_R22
+LOONGARCH_REG_S0 = LOONGARCH_REG_R23
+LOONGARCH_REG_S1 = LOONGARCH_REG_R24
+LOONGARCH_REG_S2 = LOONGARCH_REG_R25
+LOONGARCH_REG_S3 = LOONGARCH_REG_R26
+LOONGARCH_REG_S4 = LOONGARCH_REG_R27
+LOONGARCH_REG_S5 = LOONGARCH_REG_R28
+LOONGARCH_REG_S6 = LOONGARCH_REG_R29
+LOONGARCH_REG_S7 = LOONGARCH_REG_R30
+LOONGARCH_REG_S8 = LOONGARCH_REG_R31
+
+LOONGARCH_INS_INVALID = 0
+LOONGARCH_INS_CALL36 = 1
+LOONGARCH_INS_LA_ABS = 2
+LOONGARCH_INS_LA_GOT = 3
+LOONGARCH_INS_LA_PCREL = 4
+LOONGARCH_INS_LA_TLS_GD = 5
+LOONGARCH_INS_LA_TLS_IE = 6
+LOONGARCH_INS_LA_TLS_LD = 7
+LOONGARCH_INS_LA_TLS_LE = 8
+LOONGARCH_INS_LI_D = 9
+LOONGARCH_INS_LI_W = 10
+LOONGARCH_INS_TAIL36 = 11
+LOONGARCH_INS_VREPLI_B = 12
+LOONGARCH_INS_VREPLI_D = 13
+LOONGARCH_INS_VREPLI_H = 14
+LOONGARCH_INS_VREPLI_W = 15
+LOONGARCH_INS_XVREPLI_B = 16
+LOONGARCH_INS_XVREPLI_D = 17
+LOONGARCH_INS_XVREPLI_H = 18
+LOONGARCH_INS_XVREPLI_W = 19
+LOONGARCH_INS_ADC_B = 20
+LOONGARCH_INS_ADC_D = 21
+LOONGARCH_INS_ADC_H = 22
+LOONGARCH_INS_ADC_W = 23
+LOONGARCH_INS_ADDI_D = 24
+LOONGARCH_INS_ADDI_W = 25
+LOONGARCH_INS_ADDU12I_D = 26
+LOONGARCH_INS_ADDU12I_W = 27
+LOONGARCH_INS_ADDU16I_D = 28
+LOONGARCH_INS_ADD_D = 29
+LOONGARCH_INS_ADD_W = 30
+LOONGARCH_INS_ALSL_D = 31
+LOONGARCH_INS_ALSL_W = 32
+LOONGARCH_INS_ALSL_WU = 33
+LOONGARCH_INS_AMADD_B = 34
+LOONGARCH_INS_AMADD_D = 35
+LOONGARCH_INS_AMADD_H = 36
+LOONGARCH_INS_AMADD_W = 37
+LOONGARCH_INS_AMADD_DB_B = 38
+LOONGARCH_INS_AMADD_DB_D = 39
+LOONGARCH_INS_AMADD_DB_H = 40
+LOONGARCH_INS_AMADD_DB_W = 41
+LOONGARCH_INS_AMAND_D = 42
+LOONGARCH_INS_AMAND_W = 43
+LOONGARCH_INS_AMAND_DB_D = 44
+LOONGARCH_INS_AMAND_DB_W = 45
+LOONGARCH_INS_AMCAS_B = 46
+LOONGARCH_INS_AMCAS_D = 47
+LOONGARCH_INS_AMCAS_H = 48
+LOONGARCH_INS_AMCAS_W = 49
+LOONGARCH_INS_AMCAS_DB_B = 50
+LOONGARCH_INS_AMCAS_DB_D = 51
+LOONGARCH_INS_AMCAS_DB_H = 52
+LOONGARCH_INS_AMCAS_DB_W = 53
+LOONGARCH_INS_AMMAX_D = 54
+LOONGARCH_INS_AMMAX_DU = 55
+LOONGARCH_INS_AMMAX_W = 56
+LOONGARCH_INS_AMMAX_WU = 57
+LOONGARCH_INS_AMMAX_DB_D = 58
+LOONGARCH_INS_AMMAX_DB_DU = 59
+LOONGARCH_INS_AMMAX_DB_W = 60
+LOONGARCH_INS_AMMAX_DB_WU = 61
+LOONGARCH_INS_AMMIN_D = 62
+LOONGARCH_INS_AMMIN_DU = 63
+LOONGARCH_INS_AMMIN_W = 64
+LOONGARCH_INS_AMMIN_WU = 65
+LOONGARCH_INS_AMMIN_DB_D = 66
+LOONGARCH_INS_AMMIN_DB_DU = 67
+LOONGARCH_INS_AMMIN_DB_W = 68
+LOONGARCH_INS_AMMIN_DB_WU = 69
+LOONGARCH_INS_AMOR_D = 70
+LOONGARCH_INS_AMOR_W = 71
+LOONGARCH_INS_AMOR_DB_D = 72
+LOONGARCH_INS_AMOR_DB_W = 73
+LOONGARCH_INS_AMSWAP_B = 74
+LOONGARCH_INS_AMSWAP_D = 75
+LOONGARCH_INS_AMSWAP_H = 76
+LOONGARCH_INS_AMSWAP_W = 77
+LOONGARCH_INS_AMSWAP_DB_B = 78
+LOONGARCH_INS_AMSWAP_DB_D = 79
+LOONGARCH_INS_AMSWAP_DB_H = 80
+LOONGARCH_INS_AMSWAP_DB_W = 81
+LOONGARCH_INS_AMXOR_D = 82
+LOONGARCH_INS_AMXOR_W = 83
+LOONGARCH_INS_AMXOR_DB_D = 84
+LOONGARCH_INS_AMXOR_DB_W = 85
+LOONGARCH_INS_AND = 86
+LOONGARCH_INS_ANDI = 87
+LOONGARCH_INS_ANDN = 88
+LOONGARCH_INS_ARMADC_W = 89
+LOONGARCH_INS_ARMADD_W = 90
+LOONGARCH_INS_ARMAND_W = 91
+LOONGARCH_INS_ARMMFFLAG = 92
+LOONGARCH_INS_ARMMOVE = 93
+LOONGARCH_INS_ARMMOV_D = 94
+LOONGARCH_INS_ARMMOV_W = 95
+LOONGARCH_INS_ARMMTFLAG = 96
+LOONGARCH_INS_ARMNOT_W = 97
+LOONGARCH_INS_ARMOR_W = 98
+LOONGARCH_INS_ARMROTRI_W = 99
+LOONGARCH_INS_ARMROTR_W = 100
+LOONGARCH_INS_ARMRRX_W = 101
+LOONGARCH_INS_ARMSBC_W = 102
+LOONGARCH_INS_ARMSLLI_W = 103
+LOONGARCH_INS_ARMSLL_W = 104
+LOONGARCH_INS_ARMSRAI_W = 105
+LOONGARCH_INS_ARMSRA_W = 106
+LOONGARCH_INS_ARMSRLI_W = 107
+LOONGARCH_INS_ARMSRL_W = 108
+LOONGARCH_INS_ARMSUB_W = 109
+LOONGARCH_INS_ARMXOR_W = 110
+LOONGARCH_INS_ASRTGT_D = 111
+LOONGARCH_INS_ASRTLE_D = 112
+LOONGARCH_INS_B = 113
+LOONGARCH_INS_BCEQZ = 114
+LOONGARCH_INS_BCNEZ = 115
+LOONGARCH_INS_BEQ = 116
+LOONGARCH_INS_BEQZ = 117
+LOONGARCH_INS_BGE = 118
+LOONGARCH_INS_BGEU = 119
+LOONGARCH_INS_BITREV_4B = 120
+LOONGARCH_INS_BITREV_8B = 121
+LOONGARCH_INS_BITREV_D = 122
+LOONGARCH_INS_BITREV_W = 123
+LOONGARCH_INS_BL = 124
+LOONGARCH_INS_BLT = 125
+LOONGARCH_INS_BLTU = 126
+LOONGARCH_INS_BNE = 127
+LOONGARCH_INS_BNEZ = 128
+LOONGARCH_INS_BREAK = 129
+LOONGARCH_INS_BSTRINS_D = 130
+LOONGARCH_INS_BSTRINS_W = 131
+LOONGARCH_INS_BSTRPICK_D = 132
+LOONGARCH_INS_BSTRPICK_W = 133
+LOONGARCH_INS_BYTEPICK_D = 134
+LOONGARCH_INS_BYTEPICK_W = 135
+LOONGARCH_INS_CACOP = 136
+LOONGARCH_INS_CLO_D = 137
+LOONGARCH_INS_CLO_W = 138
+LOONGARCH_INS_CLZ_D = 139
+LOONGARCH_INS_CLZ_W = 140
+LOONGARCH_INS_CPUCFG = 141
+LOONGARCH_INS_CRCC_W_B_W = 142
+LOONGARCH_INS_CRCC_W_D_W = 143
+LOONGARCH_INS_CRCC_W_H_W = 144
+LOONGARCH_INS_CRCC_W_W_W = 145
+LOONGARCH_INS_CRC_W_B_W = 146
+LOONGARCH_INS_CRC_W_D_W = 147
+LOONGARCH_INS_CRC_W_H_W = 148
+LOONGARCH_INS_CRC_W_W_W = 149
+LOONGARCH_INS_CSRRD = 150
+LOONGARCH_INS_CSRWR = 151
+LOONGARCH_INS_CSRXCHG = 152
+LOONGARCH_INS_CTO_D = 153
+LOONGARCH_INS_CTO_W = 154
+LOONGARCH_INS_CTZ_D = 155
+LOONGARCH_INS_CTZ_W = 156
+LOONGARCH_INS_DBAR = 157
+LOONGARCH_INS_DBCL = 158
+LOONGARCH_INS_DIV_D = 159
+LOONGARCH_INS_DIV_DU = 160
+LOONGARCH_INS_DIV_W = 161
+LOONGARCH_INS_DIV_WU = 162
+LOONGARCH_INS_ERTN = 163
+LOONGARCH_INS_EXT_W_B = 164
+LOONGARCH_INS_EXT_W_H = 165
+LOONGARCH_INS_FABS_D = 166
+LOONGARCH_INS_FABS_S = 167
+LOONGARCH_INS_FADD_D = 168
+LOONGARCH_INS_FADD_S = 169
+LOONGARCH_INS_FCLASS_D = 170
+LOONGARCH_INS_FCLASS_S = 171
+LOONGARCH_INS_FCMP_CAF_D = 172
+LOONGARCH_INS_FCMP_CAF_S = 173
+LOONGARCH_INS_FCMP_CEQ_D = 174
+LOONGARCH_INS_FCMP_CEQ_S = 175
+LOONGARCH_INS_FCMP_CLE_D = 176
+LOONGARCH_INS_FCMP_CLE_S = 177
+LOONGARCH_INS_FCMP_CLT_D = 178
+LOONGARCH_INS_FCMP_CLT_S = 179
+LOONGARCH_INS_FCMP_CNE_D = 180
+LOONGARCH_INS_FCMP_CNE_S = 181
+LOONGARCH_INS_FCMP_COR_D = 182
+LOONGARCH_INS_FCMP_COR_S = 183
+LOONGARCH_INS_FCMP_CUEQ_D = 184
+LOONGARCH_INS_FCMP_CUEQ_S = 185
+LOONGARCH_INS_FCMP_CULE_D = 186
+LOONGARCH_INS_FCMP_CULE_S = 187
+LOONGARCH_INS_FCMP_CULT_D = 188
+LOONGARCH_INS_FCMP_CULT_S = 189
+LOONGARCH_INS_FCMP_CUNE_D = 190
+LOONGARCH_INS_FCMP_CUNE_S = 191
+LOONGARCH_INS_FCMP_CUN_D = 192
+LOONGARCH_INS_FCMP_CUN_S = 193
+LOONGARCH_INS_FCMP_SAF_D = 194
+LOONGARCH_INS_FCMP_SAF_S = 195
+LOONGARCH_INS_FCMP_SEQ_D = 196
+LOONGARCH_INS_FCMP_SEQ_S = 197
+LOONGARCH_INS_FCMP_SLE_D = 198
+LOONGARCH_INS_FCMP_SLE_S = 199
+LOONGARCH_INS_FCMP_SLT_D = 200
+LOONGARCH_INS_FCMP_SLT_S = 201
+LOONGARCH_INS_FCMP_SNE_D = 202
+LOONGARCH_INS_FCMP_SNE_S = 203
+LOONGARCH_INS_FCMP_SOR_D = 204
+LOONGARCH_INS_FCMP_SOR_S = 205
+LOONGARCH_INS_FCMP_SUEQ_D = 206
+LOONGARCH_INS_FCMP_SUEQ_S = 207
+LOONGARCH_INS_FCMP_SULE_D = 208
+LOONGARCH_INS_FCMP_SULE_S = 209
+LOONGARCH_INS_FCMP_SULT_D = 210
+LOONGARCH_INS_FCMP_SULT_S = 211
+LOONGARCH_INS_FCMP_SUNE_D = 212
+LOONGARCH_INS_FCMP_SUNE_S = 213
+LOONGARCH_INS_FCMP_SUN_D = 214
+LOONGARCH_INS_FCMP_SUN_S = 215
+LOONGARCH_INS_FCOPYSIGN_D = 216
+LOONGARCH_INS_FCOPYSIGN_S = 217
+LOONGARCH_INS_FCVT_D_LD = 218
+LOONGARCH_INS_FCVT_D_S = 219
+LOONGARCH_INS_FCVT_LD_D = 220
+LOONGARCH_INS_FCVT_S_D = 221
+LOONGARCH_INS_FCVT_UD_D = 222
+LOONGARCH_INS_FDIV_D = 223
+LOONGARCH_INS_FDIV_S = 224
+LOONGARCH_INS_FFINT_D_L = 225
+LOONGARCH_INS_FFINT_D_W = 226
+LOONGARCH_INS_FFINT_S_L = 227
+LOONGARCH_INS_FFINT_S_W = 228
+LOONGARCH_INS_FLDGT_D = 229
+LOONGARCH_INS_FLDGT_S = 230
+LOONGARCH_INS_FLDLE_D = 231
+LOONGARCH_INS_FLDLE_S = 232
+LOONGARCH_INS_FLDX_D = 233
+LOONGARCH_INS_FLDX_S = 234
+LOONGARCH_INS_FLD_D = 235
+LOONGARCH_INS_FLD_S = 236
+LOONGARCH_INS_FLOGB_D = 237
+LOONGARCH_INS_FLOGB_S = 238
+LOONGARCH_INS_FMADD_D = 239
+LOONGARCH_INS_FMADD_S = 240
+LOONGARCH_INS_FMAXA_D = 241
+LOONGARCH_INS_FMAXA_S = 242
+LOONGARCH_INS_FMAX_D = 243
+LOONGARCH_INS_FMAX_S = 244
+LOONGARCH_INS_FMINA_D = 245
+LOONGARCH_INS_FMINA_S = 246
+LOONGARCH_INS_FMIN_D = 247
+LOONGARCH_INS_FMIN_S = 248
+LOONGARCH_INS_FMOV_D = 249
+LOONGARCH_INS_FMOV_S = 250
+LOONGARCH_INS_FMSUB_D = 251
+LOONGARCH_INS_FMSUB_S = 252
+LOONGARCH_INS_FMUL_D = 253
+LOONGARCH_INS_FMUL_S = 254
+LOONGARCH_INS_FNEG_D = 255
+LOONGARCH_INS_FNEG_S = 256
+LOONGARCH_INS_FNMADD_D = 257
+LOONGARCH_INS_FNMADD_S = 258
+LOONGARCH_INS_FNMSUB_D = 259
+LOONGARCH_INS_FNMSUB_S = 260
+LOONGARCH_INS_FRECIPE_D = 261
+LOONGARCH_INS_FRECIPE_S = 262
+LOONGARCH_INS_FRECIP_D = 263
+LOONGARCH_INS_FRECIP_S = 264
+LOONGARCH_INS_FRINT_D = 265
+LOONGARCH_INS_FRINT_S = 266
+LOONGARCH_INS_FRSQRTE_D = 267
+LOONGARCH_INS_FRSQRTE_S = 268
+LOONGARCH_INS_FRSQRT_D = 269
+LOONGARCH_INS_FRSQRT_S = 270
+LOONGARCH_INS_FSCALEB_D = 271
+LOONGARCH_INS_FSCALEB_S = 272
+LOONGARCH_INS_FSEL = 273
+LOONGARCH_INS_FSQRT_D = 274
+LOONGARCH_INS_FSQRT_S = 275
+LOONGARCH_INS_FSTGT_D = 276
+LOONGARCH_INS_FSTGT_S = 277
+LOONGARCH_INS_FSTLE_D = 278
+LOONGARCH_INS_FSTLE_S = 279
+LOONGARCH_INS_FSTX_D = 280
+LOONGARCH_INS_FSTX_S = 281
+LOONGARCH_INS_FST_D = 282
+LOONGARCH_INS_FST_S = 283
+LOONGARCH_INS_FSUB_D = 284
+LOONGARCH_INS_FSUB_S = 285
+LOONGARCH_INS_FTINTRM_L_D = 286
+LOONGARCH_INS_FTINTRM_L_S = 287
+LOONGARCH_INS_FTINTRM_W_D = 288
+LOONGARCH_INS_FTINTRM_W_S = 289
+LOONGARCH_INS_FTINTRNE_L_D = 290
+LOONGARCH_INS_FTINTRNE_L_S = 291
+LOONGARCH_INS_FTINTRNE_W_D = 292
+LOONGARCH_INS_FTINTRNE_W_S = 293
+LOONGARCH_INS_FTINTRP_L_D = 294
+LOONGARCH_INS_FTINTRP_L_S = 295
+LOONGARCH_INS_FTINTRP_W_D = 296
+LOONGARCH_INS_FTINTRP_W_S = 297
+LOONGARCH_INS_FTINTRZ_L_D = 298
+LOONGARCH_INS_FTINTRZ_L_S = 299
+LOONGARCH_INS_FTINTRZ_W_D = 300
+LOONGARCH_INS_FTINTRZ_W_S = 301
+LOONGARCH_INS_FTINT_L_D = 302
+LOONGARCH_INS_FTINT_L_S = 303
+LOONGARCH_INS_FTINT_W_D = 304
+LOONGARCH_INS_FTINT_W_S = 305
+LOONGARCH_INS_GCSRRD = 306
+LOONGARCH_INS_GCSRWR = 307
+LOONGARCH_INS_GCSRXCHG = 308
+LOONGARCH_INS_GTLBFLUSH = 309
+LOONGARCH_INS_HVCL = 310
+LOONGARCH_INS_IBAR = 311
+LOONGARCH_INS_IDLE = 312
+LOONGARCH_INS_INVTLB = 313
+LOONGARCH_INS_IOCSRRD_B = 314
+LOONGARCH_INS_IOCSRRD_D = 315
+LOONGARCH_INS_IOCSRRD_H = 316
+LOONGARCH_INS_IOCSRRD_W = 317
+LOONGARCH_INS_IOCSRWR_B = 318
+LOONGARCH_INS_IOCSRWR_D = 319
+LOONGARCH_INS_IOCSRWR_H = 320
+LOONGARCH_INS_IOCSRWR_W = 321
+LOONGARCH_INS_JIRL = 322
+LOONGARCH_INS_JISCR0 = 323
+LOONGARCH_INS_JISCR1 = 324
+LOONGARCH_INS_LDDIR = 325
+LOONGARCH_INS_LDGT_B = 326
+LOONGARCH_INS_LDGT_D = 327
+LOONGARCH_INS_LDGT_H = 328
+LOONGARCH_INS_LDGT_W = 329
+LOONGARCH_INS_LDLE_B = 330
+LOONGARCH_INS_LDLE_D = 331
+LOONGARCH_INS_LDLE_H = 332
+LOONGARCH_INS_LDLE_W = 333
+LOONGARCH_INS_LDL_D = 334
+LOONGARCH_INS_LDL_W = 335
+LOONGARCH_INS_LDPTE = 336
+LOONGARCH_INS_LDPTR_D = 337
+LOONGARCH_INS_LDPTR_W = 338
+LOONGARCH_INS_LDR_D = 339
+LOONGARCH_INS_LDR_W = 340
+LOONGARCH_INS_LDX_B = 341
+LOONGARCH_INS_LDX_BU = 342
+LOONGARCH_INS_LDX_D = 343
+LOONGARCH_INS_LDX_H = 344
+LOONGARCH_INS_LDX_HU = 345
+LOONGARCH_INS_LDX_W = 346
+LOONGARCH_INS_LDX_WU = 347
+LOONGARCH_INS_LD_B = 348
+LOONGARCH_INS_LD_BU = 349
+LOONGARCH_INS_LD_D = 350
+LOONGARCH_INS_LD_H = 351
+LOONGARCH_INS_LD_HU = 352
+LOONGARCH_INS_LD_W = 353
+LOONGARCH_INS_LD_WU = 354
+LOONGARCH_INS_LLACQ_D = 355
+LOONGARCH_INS_LLACQ_W = 356
+LOONGARCH_INS_LL_D = 357
+LOONGARCH_INS_LL_W = 358
+LOONGARCH_INS_LU12I_W = 359
+LOONGARCH_INS_LU32I_D = 360
+LOONGARCH_INS_LU52I_D = 361
+LOONGARCH_INS_MASKEQZ = 362
+LOONGARCH_INS_MASKNEZ = 363
+LOONGARCH_INS_MOD_D = 364
+LOONGARCH_INS_MOD_DU = 365
+LOONGARCH_INS_MOD_W = 366
+LOONGARCH_INS_MOD_WU = 367
+LOONGARCH_INS_MOVCF2FR = 368
+LOONGARCH_INS_MOVCF2GR = 369
+LOONGARCH_INS_MOVFCSR2GR = 370
+LOONGARCH_INS_MOVFR2CF = 371
+LOONGARCH_INS_MOVFR2GR_D = 372
+LOONGARCH_INS_MOVFR2GR_S = 373
+LOONGARCH_INS_MOVFRH2GR_S = 374
+LOONGARCH_INS_MOVGR2CF = 375
+LOONGARCH_INS_MOVGR2FCSR = 376
+LOONGARCH_INS_MOVGR2FRH_W = 377
+LOONGARCH_INS_MOVGR2FR_D = 378
+LOONGARCH_INS_MOVGR2FR_W = 379
+LOONGARCH_INS_MOVGR2SCR = 380
+LOONGARCH_INS_MOVSCR2GR = 381
+LOONGARCH_INS_MULH_D = 382
+LOONGARCH_INS_MULH_DU = 383
+LOONGARCH_INS_MULH_W = 384
+LOONGARCH_INS_MULH_WU = 385
+LOONGARCH_INS_MULW_D_W = 386
+LOONGARCH_INS_MULW_D_WU = 387
+LOONGARCH_INS_MUL_D = 388
+LOONGARCH_INS_MUL_W = 389
+LOONGARCH_INS_NOR = 390
+LOONGARCH_INS_OR = 391
+LOONGARCH_INS_ORI = 392
+LOONGARCH_INS_ORN = 393
+LOONGARCH_INS_PCADDI = 394
+LOONGARCH_INS_PCADDU12I = 395
+LOONGARCH_INS_PCADDU18I = 396
+LOONGARCH_INS_PCALAU12I = 397
+LOONGARCH_INS_PRELD = 398
+LOONGARCH_INS_PRELDX = 399
+LOONGARCH_INS_RCRI_B = 400
+LOONGARCH_INS_RCRI_D = 401
+LOONGARCH_INS_RCRI_H = 402
+LOONGARCH_INS_RCRI_W = 403
+LOONGARCH_INS_RCR_B = 404
+LOONGARCH_INS_RCR_D = 405
+LOONGARCH_INS_RCR_H = 406
+LOONGARCH_INS_RCR_W = 407
+LOONGARCH_INS_RDTIMEH_W = 408
+LOONGARCH_INS_RDTIMEL_W = 409
+LOONGARCH_INS_RDTIME_D = 410
+LOONGARCH_INS_REVB_2H = 411
+LOONGARCH_INS_REVB_2W = 412
+LOONGARCH_INS_REVB_4H = 413
+LOONGARCH_INS_REVB_D = 414
+LOONGARCH_INS_REVH_2W = 415
+LOONGARCH_INS_REVH_D = 416
+LOONGARCH_INS_ROTRI_B = 417
+LOONGARCH_INS_ROTRI_D = 418
+LOONGARCH_INS_ROTRI_H = 419
+LOONGARCH_INS_ROTRI_W = 420
+LOONGARCH_INS_ROTR_B = 421
+LOONGARCH_INS_ROTR_D = 422
+LOONGARCH_INS_ROTR_H = 423
+LOONGARCH_INS_ROTR_W = 424
+LOONGARCH_INS_SBC_B = 425
+LOONGARCH_INS_SBC_D = 426
+LOONGARCH_INS_SBC_H = 427
+LOONGARCH_INS_SBC_W = 428
+LOONGARCH_INS_SCREL_D = 429
+LOONGARCH_INS_SCREL_W = 430
+LOONGARCH_INS_SC_D = 431
+LOONGARCH_INS_SC_Q = 432
+LOONGARCH_INS_SC_W = 433
+LOONGARCH_INS_SETARMJ = 434
+LOONGARCH_INS_SETX86J = 435
+LOONGARCH_INS_SETX86LOOPE = 436
+LOONGARCH_INS_SETX86LOOPNE = 437
+LOONGARCH_INS_SLLI_D = 438
+LOONGARCH_INS_SLLI_W = 439
+LOONGARCH_INS_SLL_D = 440
+LOONGARCH_INS_SLL_W = 441
+LOONGARCH_INS_SLT = 442
+LOONGARCH_INS_SLTI = 443
+LOONGARCH_INS_SLTU = 444
+LOONGARCH_INS_SLTUI = 445
+LOONGARCH_INS_SRAI_D = 446
+LOONGARCH_INS_SRAI_W = 447
+LOONGARCH_INS_SRA_D = 448
+LOONGARCH_INS_SRA_W = 449
+LOONGARCH_INS_SRLI_D = 450
+LOONGARCH_INS_SRLI_W = 451
+LOONGARCH_INS_SRL_D = 452
+LOONGARCH_INS_SRL_W = 453
+LOONGARCH_INS_STGT_B = 454
+LOONGARCH_INS_STGT_D = 455
+LOONGARCH_INS_STGT_H = 456
+LOONGARCH_INS_STGT_W = 457
+LOONGARCH_INS_STLE_B = 458
+LOONGARCH_INS_STLE_D = 459
+LOONGARCH_INS_STLE_H = 460
+LOONGARCH_INS_STLE_W = 461
+LOONGARCH_INS_STL_D = 462
+LOONGARCH_INS_STL_W = 463
+LOONGARCH_INS_STPTR_D = 464
+LOONGARCH_INS_STPTR_W = 465
+LOONGARCH_INS_STR_D = 466
+LOONGARCH_INS_STR_W = 467
+LOONGARCH_INS_STX_B = 468
+LOONGARCH_INS_STX_D = 469
+LOONGARCH_INS_STX_H = 470
+LOONGARCH_INS_STX_W = 471
+LOONGARCH_INS_ST_B = 472
+LOONGARCH_INS_ST_D = 473
+LOONGARCH_INS_ST_H = 474
+LOONGARCH_INS_ST_W = 475
+LOONGARCH_INS_SUB_D = 476
+LOONGARCH_INS_SUB_W = 477
+LOONGARCH_INS_SYSCALL = 478
+LOONGARCH_INS_TLBCLR = 479
+LOONGARCH_INS_TLBFILL = 480
+LOONGARCH_INS_TLBFLUSH = 481
+LOONGARCH_INS_TLBRD = 482
+LOONGARCH_INS_TLBSRCH = 483
+LOONGARCH_INS_TLBWR = 484
+LOONGARCH_INS_VABSD_B = 485
+LOONGARCH_INS_VABSD_BU = 486
+LOONGARCH_INS_VABSD_D = 487
+LOONGARCH_INS_VABSD_DU = 488
+LOONGARCH_INS_VABSD_H = 489
+LOONGARCH_INS_VABSD_HU = 490
+LOONGARCH_INS_VABSD_W = 491
+LOONGARCH_INS_VABSD_WU = 492
+LOONGARCH_INS_VADDA_B = 493
+LOONGARCH_INS_VADDA_D = 494
+LOONGARCH_INS_VADDA_H = 495
+LOONGARCH_INS_VADDA_W = 496
+LOONGARCH_INS_VADDI_BU = 497
+LOONGARCH_INS_VADDI_DU = 498
+LOONGARCH_INS_VADDI_HU = 499
+LOONGARCH_INS_VADDI_WU = 500
+LOONGARCH_INS_VADDWEV_D_W = 501
+LOONGARCH_INS_VADDWEV_D_WU = 502
+LOONGARCH_INS_VADDWEV_D_WU_W = 503
+LOONGARCH_INS_VADDWEV_H_B = 504
+LOONGARCH_INS_VADDWEV_H_BU = 505
+LOONGARCH_INS_VADDWEV_H_BU_B = 506
+LOONGARCH_INS_VADDWEV_Q_D = 507
+LOONGARCH_INS_VADDWEV_Q_DU = 508
+LOONGARCH_INS_VADDWEV_Q_DU_D = 509
+LOONGARCH_INS_VADDWEV_W_H = 510
+LOONGARCH_INS_VADDWEV_W_HU = 511
+LOONGARCH_INS_VADDWEV_W_HU_H = 512
+LOONGARCH_INS_VADDWOD_D_W = 513
+LOONGARCH_INS_VADDWOD_D_WU = 514
+LOONGARCH_INS_VADDWOD_D_WU_W = 515
+LOONGARCH_INS_VADDWOD_H_B = 516
+LOONGARCH_INS_VADDWOD_H_BU = 517
+LOONGARCH_INS_VADDWOD_H_BU_B = 518
+LOONGARCH_INS_VADDWOD_Q_D = 519
+LOONGARCH_INS_VADDWOD_Q_DU = 520
+LOONGARCH_INS_VADDWOD_Q_DU_D = 521
+LOONGARCH_INS_VADDWOD_W_H = 522
+LOONGARCH_INS_VADDWOD_W_HU = 523
+LOONGARCH_INS_VADDWOD_W_HU_H = 524
+LOONGARCH_INS_VADD_B = 525
+LOONGARCH_INS_VADD_D = 526
+LOONGARCH_INS_VADD_H = 527
+LOONGARCH_INS_VADD_Q = 528
+LOONGARCH_INS_VADD_W = 529
+LOONGARCH_INS_VANDI_B = 530
+LOONGARCH_INS_VANDN_V = 531
+LOONGARCH_INS_VAND_V = 532
+LOONGARCH_INS_VAVGR_B = 533
+LOONGARCH_INS_VAVGR_BU = 534
+LOONGARCH_INS_VAVGR_D = 535
+LOONGARCH_INS_VAVGR_DU = 536
+LOONGARCH_INS_VAVGR_H = 537
+LOONGARCH_INS_VAVGR_HU = 538
+LOONGARCH_INS_VAVGR_W = 539
+LOONGARCH_INS_VAVGR_WU = 540
+LOONGARCH_INS_VAVG_B = 541
+LOONGARCH_INS_VAVG_BU = 542
+LOONGARCH_INS_VAVG_D = 543
+LOONGARCH_INS_VAVG_DU = 544
+LOONGARCH_INS_VAVG_H = 545
+LOONGARCH_INS_VAVG_HU = 546
+LOONGARCH_INS_VAVG_W = 547
+LOONGARCH_INS_VAVG_WU = 548
+LOONGARCH_INS_VBITCLRI_B = 549
+LOONGARCH_INS_VBITCLRI_D = 550
+LOONGARCH_INS_VBITCLRI_H = 551
+LOONGARCH_INS_VBITCLRI_W = 552
+LOONGARCH_INS_VBITCLR_B = 553
+LOONGARCH_INS_VBITCLR_D = 554
+LOONGARCH_INS_VBITCLR_H = 555
+LOONGARCH_INS_VBITCLR_W = 556
+LOONGARCH_INS_VBITREVI_B = 557
+LOONGARCH_INS_VBITREVI_D = 558
+LOONGARCH_INS_VBITREVI_H = 559
+LOONGARCH_INS_VBITREVI_W = 560
+LOONGARCH_INS_VBITREV_B = 561
+LOONGARCH_INS_VBITREV_D = 562
+LOONGARCH_INS_VBITREV_H = 563
+LOONGARCH_INS_VBITREV_W = 564
+LOONGARCH_INS_VBITSELI_B = 565
+LOONGARCH_INS_VBITSEL_V = 566
+LOONGARCH_INS_VBITSETI_B = 567
+LOONGARCH_INS_VBITSETI_D = 568
+LOONGARCH_INS_VBITSETI_H = 569
+LOONGARCH_INS_VBITSETI_W = 570
+LOONGARCH_INS_VBITSET_B = 571
+LOONGARCH_INS_VBITSET_D = 572
+LOONGARCH_INS_VBITSET_H = 573
+LOONGARCH_INS_VBITSET_W = 574
+LOONGARCH_INS_VBSLL_V = 575
+LOONGARCH_INS_VBSRL_V = 576
+LOONGARCH_INS_VCLO_B = 577
+LOONGARCH_INS_VCLO_D = 578
+LOONGARCH_INS_VCLO_H = 579
+LOONGARCH_INS_VCLO_W = 580
+LOONGARCH_INS_VCLZ_B = 581
+LOONGARCH_INS_VCLZ_D = 582
+LOONGARCH_INS_VCLZ_H = 583
+LOONGARCH_INS_VCLZ_W = 584
+LOONGARCH_INS_VDIV_B = 585
+LOONGARCH_INS_VDIV_BU = 586
+LOONGARCH_INS_VDIV_D = 587
+LOONGARCH_INS_VDIV_DU = 588
+LOONGARCH_INS_VDIV_H = 589
+LOONGARCH_INS_VDIV_HU = 590
+LOONGARCH_INS_VDIV_W = 591
+LOONGARCH_INS_VDIV_WU = 592
+LOONGARCH_INS_VEXT2XV_DU_BU = 593
+LOONGARCH_INS_VEXT2XV_DU_HU = 594
+LOONGARCH_INS_VEXT2XV_DU_WU = 595
+LOONGARCH_INS_VEXT2XV_D_B = 596
+LOONGARCH_INS_VEXT2XV_D_H = 597
+LOONGARCH_INS_VEXT2XV_D_W = 598
+LOONGARCH_INS_VEXT2XV_HU_BU = 599
+LOONGARCH_INS_VEXT2XV_H_B = 600
+LOONGARCH_INS_VEXT2XV_WU_BU = 601
+LOONGARCH_INS_VEXT2XV_WU_HU = 602
+LOONGARCH_INS_VEXT2XV_W_B = 603
+LOONGARCH_INS_VEXT2XV_W_H = 604
+LOONGARCH_INS_VEXTH_DU_WU = 605
+LOONGARCH_INS_VEXTH_D_W = 606
+LOONGARCH_INS_VEXTH_HU_BU = 607
+LOONGARCH_INS_VEXTH_H_B = 608
+LOONGARCH_INS_VEXTH_QU_DU = 609
+LOONGARCH_INS_VEXTH_Q_D = 610
+LOONGARCH_INS_VEXTH_WU_HU = 611
+LOONGARCH_INS_VEXTH_W_H = 612
+LOONGARCH_INS_VEXTL_QU_DU = 613
+LOONGARCH_INS_VEXTL_Q_D = 614
+LOONGARCH_INS_VEXTRINS_B = 615
+LOONGARCH_INS_VEXTRINS_D = 616
+LOONGARCH_INS_VEXTRINS_H = 617
+LOONGARCH_INS_VEXTRINS_W = 618
+LOONGARCH_INS_VFADD_D = 619
+LOONGARCH_INS_VFADD_S = 620
+LOONGARCH_INS_VFCLASS_D = 621
+LOONGARCH_INS_VFCLASS_S = 622
+LOONGARCH_INS_VFCMP_CAF_D = 623
+LOONGARCH_INS_VFCMP_CAF_S = 624
+LOONGARCH_INS_VFCMP_CEQ_D = 625
+LOONGARCH_INS_VFCMP_CEQ_S = 626
+LOONGARCH_INS_VFCMP_CLE_D = 627
+LOONGARCH_INS_VFCMP_CLE_S = 628
+LOONGARCH_INS_VFCMP_CLT_D = 629
+LOONGARCH_INS_VFCMP_CLT_S = 630
+LOONGARCH_INS_VFCMP_CNE_D = 631
+LOONGARCH_INS_VFCMP_CNE_S = 632
+LOONGARCH_INS_VFCMP_COR_D = 633
+LOONGARCH_INS_VFCMP_COR_S = 634
+LOONGARCH_INS_VFCMP_CUEQ_D = 635
+LOONGARCH_INS_VFCMP_CUEQ_S = 636
+LOONGARCH_INS_VFCMP_CULE_D = 637
+LOONGARCH_INS_VFCMP_CULE_S = 638
+LOONGARCH_INS_VFCMP_CULT_D = 639
+LOONGARCH_INS_VFCMP_CULT_S = 640
+LOONGARCH_INS_VFCMP_CUNE_D = 641
+LOONGARCH_INS_VFCMP_CUNE_S = 642
+LOONGARCH_INS_VFCMP_CUN_D = 643
+LOONGARCH_INS_VFCMP_CUN_S = 644
+LOONGARCH_INS_VFCMP_SAF_D = 645
+LOONGARCH_INS_VFCMP_SAF_S = 646
+LOONGARCH_INS_VFCMP_SEQ_D = 647
+LOONGARCH_INS_VFCMP_SEQ_S = 648
+LOONGARCH_INS_VFCMP_SLE_D = 649
+LOONGARCH_INS_VFCMP_SLE_S = 650
+LOONGARCH_INS_VFCMP_SLT_D = 651
+LOONGARCH_INS_VFCMP_SLT_S = 652
+LOONGARCH_INS_VFCMP_SNE_D = 653
+LOONGARCH_INS_VFCMP_SNE_S = 654
+LOONGARCH_INS_VFCMP_SOR_D = 655
+LOONGARCH_INS_VFCMP_SOR_S = 656
+LOONGARCH_INS_VFCMP_SUEQ_D = 657
+LOONGARCH_INS_VFCMP_SUEQ_S = 658
+LOONGARCH_INS_VFCMP_SULE_D = 659
+LOONGARCH_INS_VFCMP_SULE_S = 660
+LOONGARCH_INS_VFCMP_SULT_D = 661
+LOONGARCH_INS_VFCMP_SULT_S = 662
+LOONGARCH_INS_VFCMP_SUNE_D = 663
+LOONGARCH_INS_VFCMP_SUNE_S = 664
+LOONGARCH_INS_VFCMP_SUN_D = 665
+LOONGARCH_INS_VFCMP_SUN_S = 666
+LOONGARCH_INS_VFCVTH_D_S = 667
+LOONGARCH_INS_VFCVTH_S_H = 668
+LOONGARCH_INS_VFCVTL_D_S = 669
+LOONGARCH_INS_VFCVTL_S_H = 670
+LOONGARCH_INS_VFCVT_H_S = 671
+LOONGARCH_INS_VFCVT_S_D = 672
+LOONGARCH_INS_VFDIV_D = 673
+LOONGARCH_INS_VFDIV_S = 674
+LOONGARCH_INS_VFFINTH_D_W = 675
+LOONGARCH_INS_VFFINTL_D_W = 676
+LOONGARCH_INS_VFFINT_D_L = 677
+LOONGARCH_INS_VFFINT_D_LU = 678
+LOONGARCH_INS_VFFINT_S_L = 679
+LOONGARCH_INS_VFFINT_S_W = 680
+LOONGARCH_INS_VFFINT_S_WU = 681
+LOONGARCH_INS_VFLOGB_D = 682
+LOONGARCH_INS_VFLOGB_S = 683
+LOONGARCH_INS_VFMADD_D = 684
+LOONGARCH_INS_VFMADD_S = 685
+LOONGARCH_INS_VFMAXA_D = 686
+LOONGARCH_INS_VFMAXA_S = 687
+LOONGARCH_INS_VFMAX_D = 688
+LOONGARCH_INS_VFMAX_S = 689
+LOONGARCH_INS_VFMINA_D = 690
+LOONGARCH_INS_VFMINA_S = 691
+LOONGARCH_INS_VFMIN_D = 692
+LOONGARCH_INS_VFMIN_S = 693
+LOONGARCH_INS_VFMSUB_D = 694
+LOONGARCH_INS_VFMSUB_S = 695
+LOONGARCH_INS_VFMUL_D = 696
+LOONGARCH_INS_VFMUL_S = 697
+LOONGARCH_INS_VFNMADD_D = 698
+LOONGARCH_INS_VFNMADD_S = 699
+LOONGARCH_INS_VFNMSUB_D = 700
+LOONGARCH_INS_VFNMSUB_S = 701
+LOONGARCH_INS_VFRECIPE_D = 702
+LOONGARCH_INS_VFRECIPE_S = 703
+LOONGARCH_INS_VFRECIP_D = 704
+LOONGARCH_INS_VFRECIP_S = 705
+LOONGARCH_INS_VFRINTRM_D = 706
+LOONGARCH_INS_VFRINTRM_S = 707
+LOONGARCH_INS_VFRINTRNE_D = 708
+LOONGARCH_INS_VFRINTRNE_S = 709
+LOONGARCH_INS_VFRINTRP_D = 710
+LOONGARCH_INS_VFRINTRP_S = 711
+LOONGARCH_INS_VFRINTRZ_D = 712
+LOONGARCH_INS_VFRINTRZ_S = 713
+LOONGARCH_INS_VFRINT_D = 714
+LOONGARCH_INS_VFRINT_S = 715
+LOONGARCH_INS_VFRSQRTE_D = 716
+LOONGARCH_INS_VFRSQRTE_S = 717
+LOONGARCH_INS_VFRSQRT_D = 718
+LOONGARCH_INS_VFRSQRT_S = 719
+LOONGARCH_INS_VFRSTPI_B = 720
+LOONGARCH_INS_VFRSTPI_H = 721
+LOONGARCH_INS_VFRSTP_B = 722
+LOONGARCH_INS_VFRSTP_H = 723
+LOONGARCH_INS_VFSQRT_D = 724
+LOONGARCH_INS_VFSQRT_S = 725
+LOONGARCH_INS_VFSUB_D = 726
+LOONGARCH_INS_VFSUB_S = 727
+LOONGARCH_INS_VFTINTH_L_S = 728
+LOONGARCH_INS_VFTINTL_L_S = 729
+LOONGARCH_INS_VFTINTRMH_L_S = 730
+LOONGARCH_INS_VFTINTRML_L_S = 731
+LOONGARCH_INS_VFTINTRM_L_D = 732
+LOONGARCH_INS_VFTINTRM_W_D = 733
+LOONGARCH_INS_VFTINTRM_W_S = 734
+LOONGARCH_INS_VFTINTRNEH_L_S = 735
+LOONGARCH_INS_VFTINTRNEL_L_S = 736
+LOONGARCH_INS_VFTINTRNE_L_D = 737
+LOONGARCH_INS_VFTINTRNE_W_D = 738
+LOONGARCH_INS_VFTINTRNE_W_S = 739
+LOONGARCH_INS_VFTINTRPH_L_S = 740
+LOONGARCH_INS_VFTINTRPL_L_S = 741
+LOONGARCH_INS_VFTINTRP_L_D = 742
+LOONGARCH_INS_VFTINTRP_W_D = 743
+LOONGARCH_INS_VFTINTRP_W_S = 744
+LOONGARCH_INS_VFTINTRZH_L_S = 745
+LOONGARCH_INS_VFTINTRZL_L_S = 746
+LOONGARCH_INS_VFTINTRZ_LU_D = 747
+LOONGARCH_INS_VFTINTRZ_L_D = 748
+LOONGARCH_INS_VFTINTRZ_WU_S = 749
+LOONGARCH_INS_VFTINTRZ_W_D = 750
+LOONGARCH_INS_VFTINTRZ_W_S = 751
+LOONGARCH_INS_VFTINT_LU_D = 752
+LOONGARCH_INS_VFTINT_L_D = 753
+LOONGARCH_INS_VFTINT_WU_S = 754
+LOONGARCH_INS_VFTINT_W_D = 755
+LOONGARCH_INS_VFTINT_W_S = 756
+LOONGARCH_INS_VHADDW_DU_WU = 757
+LOONGARCH_INS_VHADDW_D_W = 758
+LOONGARCH_INS_VHADDW_HU_BU = 759
+LOONGARCH_INS_VHADDW_H_B = 760
+LOONGARCH_INS_VHADDW_QU_DU = 761
+LOONGARCH_INS_VHADDW_Q_D = 762
+LOONGARCH_INS_VHADDW_WU_HU = 763
+LOONGARCH_INS_VHADDW_W_H = 764
+LOONGARCH_INS_VHSUBW_DU_WU = 765
+LOONGARCH_INS_VHSUBW_D_W = 766
+LOONGARCH_INS_VHSUBW_HU_BU = 767
+LOONGARCH_INS_VHSUBW_H_B = 768
+LOONGARCH_INS_VHSUBW_QU_DU = 769
+LOONGARCH_INS_VHSUBW_Q_D = 770
+LOONGARCH_INS_VHSUBW_WU_HU = 771
+LOONGARCH_INS_VHSUBW_W_H = 772
+LOONGARCH_INS_VILVH_B = 773
+LOONGARCH_INS_VILVH_D = 774
+LOONGARCH_INS_VILVH_H = 775
+LOONGARCH_INS_VILVH_W = 776
+LOONGARCH_INS_VILVL_B = 777
+LOONGARCH_INS_VILVL_D = 778
+LOONGARCH_INS_VILVL_H = 779
+LOONGARCH_INS_VILVL_W = 780
+LOONGARCH_INS_VINSGR2VR_B = 781
+LOONGARCH_INS_VINSGR2VR_D = 782
+LOONGARCH_INS_VINSGR2VR_H = 783
+LOONGARCH_INS_VINSGR2VR_W = 784
+LOONGARCH_INS_VLD = 785
+LOONGARCH_INS_VLDI = 786
+LOONGARCH_INS_VLDREPL_B = 787
+LOONGARCH_INS_VLDREPL_D = 788
+LOONGARCH_INS_VLDREPL_H = 789
+LOONGARCH_INS_VLDREPL_W = 790
+LOONGARCH_INS_VLDX = 791
+LOONGARCH_INS_VMADDWEV_D_W = 792
+LOONGARCH_INS_VMADDWEV_D_WU = 793
+LOONGARCH_INS_VMADDWEV_D_WU_W = 794
+LOONGARCH_INS_VMADDWEV_H_B = 795
+LOONGARCH_INS_VMADDWEV_H_BU = 796
+LOONGARCH_INS_VMADDWEV_H_BU_B = 797
+LOONGARCH_INS_VMADDWEV_Q_D = 798
+LOONGARCH_INS_VMADDWEV_Q_DU = 799
+LOONGARCH_INS_VMADDWEV_Q_DU_D = 800
+LOONGARCH_INS_VMADDWEV_W_H = 801
+LOONGARCH_INS_VMADDWEV_W_HU = 802
+LOONGARCH_INS_VMADDWEV_W_HU_H = 803
+LOONGARCH_INS_VMADDWOD_D_W = 804
+LOONGARCH_INS_VMADDWOD_D_WU = 805
+LOONGARCH_INS_VMADDWOD_D_WU_W = 806
+LOONGARCH_INS_VMADDWOD_H_B = 807
+LOONGARCH_INS_VMADDWOD_H_BU = 808
+LOONGARCH_INS_VMADDWOD_H_BU_B = 809
+LOONGARCH_INS_VMADDWOD_Q_D = 810
+LOONGARCH_INS_VMADDWOD_Q_DU = 811
+LOONGARCH_INS_VMADDWOD_Q_DU_D = 812
+LOONGARCH_INS_VMADDWOD_W_H = 813
+LOONGARCH_INS_VMADDWOD_W_HU = 814
+LOONGARCH_INS_VMADDWOD_W_HU_H = 815
+LOONGARCH_INS_VMADD_B = 816
+LOONGARCH_INS_VMADD_D = 817
+LOONGARCH_INS_VMADD_H = 818
+LOONGARCH_INS_VMADD_W = 819
+LOONGARCH_INS_VMAXI_B = 820
+LOONGARCH_INS_VMAXI_BU = 821
+LOONGARCH_INS_VMAXI_D = 822
+LOONGARCH_INS_VMAXI_DU = 823
+LOONGARCH_INS_VMAXI_H = 824
+LOONGARCH_INS_VMAXI_HU = 825
+LOONGARCH_INS_VMAXI_W = 826
+LOONGARCH_INS_VMAXI_WU = 827
+LOONGARCH_INS_VMAX_B = 828
+LOONGARCH_INS_VMAX_BU = 829
+LOONGARCH_INS_VMAX_D = 830
+LOONGARCH_INS_VMAX_DU = 831
+LOONGARCH_INS_VMAX_H = 832
+LOONGARCH_INS_VMAX_HU = 833
+LOONGARCH_INS_VMAX_W = 834
+LOONGARCH_INS_VMAX_WU = 835
+LOONGARCH_INS_VMINI_B = 836
+LOONGARCH_INS_VMINI_BU = 837
+LOONGARCH_INS_VMINI_D = 838
+LOONGARCH_INS_VMINI_DU = 839
+LOONGARCH_INS_VMINI_H = 840
+LOONGARCH_INS_VMINI_HU = 841
+LOONGARCH_INS_VMINI_W = 842
+LOONGARCH_INS_VMINI_WU = 843
+LOONGARCH_INS_VMIN_B = 844
+LOONGARCH_INS_VMIN_BU = 845
+LOONGARCH_INS_VMIN_D = 846
+LOONGARCH_INS_VMIN_DU = 847
+LOONGARCH_INS_VMIN_H = 848
+LOONGARCH_INS_VMIN_HU = 849
+LOONGARCH_INS_VMIN_W = 850
+LOONGARCH_INS_VMIN_WU = 851
+LOONGARCH_INS_VMOD_B = 852
+LOONGARCH_INS_VMOD_BU = 853
+LOONGARCH_INS_VMOD_D = 854
+LOONGARCH_INS_VMOD_DU = 855
+LOONGARCH_INS_VMOD_H = 856
+LOONGARCH_INS_VMOD_HU = 857
+LOONGARCH_INS_VMOD_W = 858
+LOONGARCH_INS_VMOD_WU = 859
+LOONGARCH_INS_VMSKGEZ_B = 860
+LOONGARCH_INS_VMSKLTZ_B = 861
+LOONGARCH_INS_VMSKLTZ_D = 862
+LOONGARCH_INS_VMSKLTZ_H = 863
+LOONGARCH_INS_VMSKLTZ_W = 864
+LOONGARCH_INS_VMSKNZ_B = 865
+LOONGARCH_INS_VMSUB_B = 866
+LOONGARCH_INS_VMSUB_D = 867
+LOONGARCH_INS_VMSUB_H = 868
+LOONGARCH_INS_VMSUB_W = 869
+LOONGARCH_INS_VMUH_B = 870
+LOONGARCH_INS_VMUH_BU = 871
+LOONGARCH_INS_VMUH_D = 872
+LOONGARCH_INS_VMUH_DU = 873
+LOONGARCH_INS_VMUH_H = 874
+LOONGARCH_INS_VMUH_HU = 875
+LOONGARCH_INS_VMUH_W = 876
+LOONGARCH_INS_VMUH_WU = 877
+LOONGARCH_INS_VMULWEV_D_W = 878
+LOONGARCH_INS_VMULWEV_D_WU = 879
+LOONGARCH_INS_VMULWEV_D_WU_W = 880
+LOONGARCH_INS_VMULWEV_H_B = 881
+LOONGARCH_INS_VMULWEV_H_BU = 882
+LOONGARCH_INS_VMULWEV_H_BU_B = 883
+LOONGARCH_INS_VMULWEV_Q_D = 884
+LOONGARCH_INS_VMULWEV_Q_DU = 885
+LOONGARCH_INS_VMULWEV_Q_DU_D = 886
+LOONGARCH_INS_VMULWEV_W_H = 887
+LOONGARCH_INS_VMULWEV_W_HU = 888
+LOONGARCH_INS_VMULWEV_W_HU_H = 889
+LOONGARCH_INS_VMULWOD_D_W = 890
+LOONGARCH_INS_VMULWOD_D_WU = 891
+LOONGARCH_INS_VMULWOD_D_WU_W = 892
+LOONGARCH_INS_VMULWOD_H_B = 893
+LOONGARCH_INS_VMULWOD_H_BU = 894
+LOONGARCH_INS_VMULWOD_H_BU_B = 895
+LOONGARCH_INS_VMULWOD_Q_D = 896
+LOONGARCH_INS_VMULWOD_Q_DU = 897
+LOONGARCH_INS_VMULWOD_Q_DU_D = 898
+LOONGARCH_INS_VMULWOD_W_H = 899
+LOONGARCH_INS_VMULWOD_W_HU = 900
+LOONGARCH_INS_VMULWOD_W_HU_H = 901
+LOONGARCH_INS_VMUL_B = 902
+LOONGARCH_INS_VMUL_D = 903
+LOONGARCH_INS_VMUL_H = 904
+LOONGARCH_INS_VMUL_W = 905
+LOONGARCH_INS_VNEG_B = 906
+LOONGARCH_INS_VNEG_D = 907
+LOONGARCH_INS_VNEG_H = 908
+LOONGARCH_INS_VNEG_W = 909
+LOONGARCH_INS_VNORI_B = 910
+LOONGARCH_INS_VNOR_V = 911
+LOONGARCH_INS_VORI_B = 912
+LOONGARCH_INS_VORN_V = 913
+LOONGARCH_INS_VOR_V = 914
+LOONGARCH_INS_VPACKEV_B = 915
+LOONGARCH_INS_VPACKEV_D = 916
+LOONGARCH_INS_VPACKEV_H = 917
+LOONGARCH_INS_VPACKEV_W = 918
+LOONGARCH_INS_VPACKOD_B = 919
+LOONGARCH_INS_VPACKOD_D = 920
+LOONGARCH_INS_VPACKOD_H = 921
+LOONGARCH_INS_VPACKOD_W = 922
+LOONGARCH_INS_VPCNT_B = 923
+LOONGARCH_INS_VPCNT_D = 924
+LOONGARCH_INS_VPCNT_H = 925
+LOONGARCH_INS_VPCNT_W = 926
+LOONGARCH_INS_VPERMI_W = 927
+LOONGARCH_INS_VPICKEV_B = 928
+LOONGARCH_INS_VPICKEV_D = 929
+LOONGARCH_INS_VPICKEV_H = 930
+LOONGARCH_INS_VPICKEV_W = 931
+LOONGARCH_INS_VPICKOD_B = 932
+LOONGARCH_INS_VPICKOD_D = 933
+LOONGARCH_INS_VPICKOD_H = 934
+LOONGARCH_INS_VPICKOD_W = 935
+LOONGARCH_INS_VPICKVE2GR_B = 936
+LOONGARCH_INS_VPICKVE2GR_BU = 937
+LOONGARCH_INS_VPICKVE2GR_D = 938
+LOONGARCH_INS_VPICKVE2GR_DU = 939
+LOONGARCH_INS_VPICKVE2GR_H = 940
+LOONGARCH_INS_VPICKVE2GR_HU = 941
+LOONGARCH_INS_VPICKVE2GR_W = 942
+LOONGARCH_INS_VPICKVE2GR_WU = 943
+LOONGARCH_INS_VREPLGR2VR_B = 944
+LOONGARCH_INS_VREPLGR2VR_D = 945
+LOONGARCH_INS_VREPLGR2VR_H = 946
+LOONGARCH_INS_VREPLGR2VR_W = 947
+LOONGARCH_INS_VREPLVEI_B = 948
+LOONGARCH_INS_VREPLVEI_D = 949
+LOONGARCH_INS_VREPLVEI_H = 950
+LOONGARCH_INS_VREPLVEI_W = 951
+LOONGARCH_INS_VREPLVE_B = 952
+LOONGARCH_INS_VREPLVE_D = 953
+LOONGARCH_INS_VREPLVE_H = 954
+LOONGARCH_INS_VREPLVE_W = 955
+LOONGARCH_INS_VROTRI_B = 956
+LOONGARCH_INS_VROTRI_D = 957
+LOONGARCH_INS_VROTRI_H = 958
+LOONGARCH_INS_VROTRI_W = 959
+LOONGARCH_INS_VROTR_B = 960
+LOONGARCH_INS_VROTR_D = 961
+LOONGARCH_INS_VROTR_H = 962
+LOONGARCH_INS_VROTR_W = 963
+LOONGARCH_INS_VSADD_B = 964
+LOONGARCH_INS_VSADD_BU = 965
+LOONGARCH_INS_VSADD_D = 966
+LOONGARCH_INS_VSADD_DU = 967
+LOONGARCH_INS_VSADD_H = 968
+LOONGARCH_INS_VSADD_HU = 969
+LOONGARCH_INS_VSADD_W = 970
+LOONGARCH_INS_VSADD_WU = 971
+LOONGARCH_INS_VSAT_B = 972
+LOONGARCH_INS_VSAT_BU = 973
+LOONGARCH_INS_VSAT_D = 974
+LOONGARCH_INS_VSAT_DU = 975
+LOONGARCH_INS_VSAT_H = 976
+LOONGARCH_INS_VSAT_HU = 977
+LOONGARCH_INS_VSAT_W = 978
+LOONGARCH_INS_VSAT_WU = 979
+LOONGARCH_INS_VSEQI_B = 980
+LOONGARCH_INS_VSEQI_D = 981
+LOONGARCH_INS_VSEQI_H = 982
+LOONGARCH_INS_VSEQI_W = 983
+LOONGARCH_INS_VSEQ_B = 984
+LOONGARCH_INS_VSEQ_D = 985
+LOONGARCH_INS_VSEQ_H = 986
+LOONGARCH_INS_VSEQ_W = 987
+LOONGARCH_INS_VSETALLNEZ_B = 988
+LOONGARCH_INS_VSETALLNEZ_D = 989
+LOONGARCH_INS_VSETALLNEZ_H = 990
+LOONGARCH_INS_VSETALLNEZ_W = 991
+LOONGARCH_INS_VSETANYEQZ_B = 992
+LOONGARCH_INS_VSETANYEQZ_D = 993
+LOONGARCH_INS_VSETANYEQZ_H = 994
+LOONGARCH_INS_VSETANYEQZ_W = 995
+LOONGARCH_INS_VSETEQZ_V = 996
+LOONGARCH_INS_VSETNEZ_V = 997
+LOONGARCH_INS_VSHUF4I_B = 998
+LOONGARCH_INS_VSHUF4I_D = 999
+LOONGARCH_INS_VSHUF4I_H = 1000
+LOONGARCH_INS_VSHUF4I_W = 1001
+LOONGARCH_INS_VSHUF_B = 1002
+LOONGARCH_INS_VSHUF_D = 1003
+LOONGARCH_INS_VSHUF_H = 1004
+LOONGARCH_INS_VSHUF_W = 1005
+LOONGARCH_INS_VSIGNCOV_B = 1006
+LOONGARCH_INS_VSIGNCOV_D = 1007
+LOONGARCH_INS_VSIGNCOV_H = 1008
+LOONGARCH_INS_VSIGNCOV_W = 1009
+LOONGARCH_INS_VSLEI_B = 1010
+LOONGARCH_INS_VSLEI_BU = 1011
+LOONGARCH_INS_VSLEI_D = 1012
+LOONGARCH_INS_VSLEI_DU = 1013
+LOONGARCH_INS_VSLEI_H = 1014
+LOONGARCH_INS_VSLEI_HU = 1015
+LOONGARCH_INS_VSLEI_W = 1016
+LOONGARCH_INS_VSLEI_WU = 1017
+LOONGARCH_INS_VSLE_B = 1018
+LOONGARCH_INS_VSLE_BU = 1019
+LOONGARCH_INS_VSLE_D = 1020
+LOONGARCH_INS_VSLE_DU = 1021
+LOONGARCH_INS_VSLE_H = 1022
+LOONGARCH_INS_VSLE_HU = 1023
+LOONGARCH_INS_VSLE_W = 1024
+LOONGARCH_INS_VSLE_WU = 1025
+LOONGARCH_INS_VSLLI_B = 1026
+LOONGARCH_INS_VSLLI_D = 1027
+LOONGARCH_INS_VSLLI_H = 1028
+LOONGARCH_INS_VSLLI_W = 1029
+LOONGARCH_INS_VSLLWIL_DU_WU = 1030
+LOONGARCH_INS_VSLLWIL_D_W = 1031
+LOONGARCH_INS_VSLLWIL_HU_BU = 1032
+LOONGARCH_INS_VSLLWIL_H_B = 1033
+LOONGARCH_INS_VSLLWIL_WU_HU = 1034
+LOONGARCH_INS_VSLLWIL_W_H = 1035
+LOONGARCH_INS_VSLL_B = 1036
+LOONGARCH_INS_VSLL_D = 1037
+LOONGARCH_INS_VSLL_H = 1038
+LOONGARCH_INS_VSLL_W = 1039
+LOONGARCH_INS_VSLTI_B = 1040
+LOONGARCH_INS_VSLTI_BU = 1041
+LOONGARCH_INS_VSLTI_D = 1042
+LOONGARCH_INS_VSLTI_DU = 1043
+LOONGARCH_INS_VSLTI_H = 1044
+LOONGARCH_INS_VSLTI_HU = 1045
+LOONGARCH_INS_VSLTI_W = 1046
+LOONGARCH_INS_VSLTI_WU = 1047
+LOONGARCH_INS_VSLT_B = 1048
+LOONGARCH_INS_VSLT_BU = 1049
+LOONGARCH_INS_VSLT_D = 1050
+LOONGARCH_INS_VSLT_DU = 1051
+LOONGARCH_INS_VSLT_H = 1052
+LOONGARCH_INS_VSLT_HU = 1053
+LOONGARCH_INS_VSLT_W = 1054
+LOONGARCH_INS_VSLT_WU = 1055
+LOONGARCH_INS_VSRAI_B = 1056
+LOONGARCH_INS_VSRAI_D = 1057
+LOONGARCH_INS_VSRAI_H = 1058
+LOONGARCH_INS_VSRAI_W = 1059
+LOONGARCH_INS_VSRANI_B_H = 1060
+LOONGARCH_INS_VSRANI_D_Q = 1061
+LOONGARCH_INS_VSRANI_H_W = 1062
+LOONGARCH_INS_VSRANI_W_D = 1063
+LOONGARCH_INS_VSRAN_B_H = 1064
+LOONGARCH_INS_VSRAN_H_W = 1065
+LOONGARCH_INS_VSRAN_W_D = 1066
+LOONGARCH_INS_VSRARI_B = 1067
+LOONGARCH_INS_VSRARI_D = 1068
+LOONGARCH_INS_VSRARI_H = 1069
+LOONGARCH_INS_VSRARI_W = 1070
+LOONGARCH_INS_VSRARNI_B_H = 1071
+LOONGARCH_INS_VSRARNI_D_Q = 1072
+LOONGARCH_INS_VSRARNI_H_W = 1073
+LOONGARCH_INS_VSRARNI_W_D = 1074
+LOONGARCH_INS_VSRARN_B_H = 1075
+LOONGARCH_INS_VSRARN_H_W = 1076
+LOONGARCH_INS_VSRARN_W_D = 1077
+LOONGARCH_INS_VSRAR_B = 1078
+LOONGARCH_INS_VSRAR_D = 1079
+LOONGARCH_INS_VSRAR_H = 1080
+LOONGARCH_INS_VSRAR_W = 1081
+LOONGARCH_INS_VSRA_B = 1082
+LOONGARCH_INS_VSRA_D = 1083
+LOONGARCH_INS_VSRA_H = 1084
+LOONGARCH_INS_VSRA_W = 1085
+LOONGARCH_INS_VSRLI_B = 1086
+LOONGARCH_INS_VSRLI_D = 1087
+LOONGARCH_INS_VSRLI_H = 1088
+LOONGARCH_INS_VSRLI_W = 1089
+LOONGARCH_INS_VSRLNI_B_H = 1090
+LOONGARCH_INS_VSRLNI_D_Q = 1091
+LOONGARCH_INS_VSRLNI_H_W = 1092
+LOONGARCH_INS_VSRLNI_W_D = 1093
+LOONGARCH_INS_VSRLN_B_H = 1094
+LOONGARCH_INS_VSRLN_H_W = 1095
+LOONGARCH_INS_VSRLN_W_D = 1096
+LOONGARCH_INS_VSRLRI_B = 1097
+LOONGARCH_INS_VSRLRI_D = 1098
+LOONGARCH_INS_VSRLRI_H = 1099
+LOONGARCH_INS_VSRLRI_W = 1100
+LOONGARCH_INS_VSRLRNI_B_H = 1101
+LOONGARCH_INS_VSRLRNI_D_Q = 1102
+LOONGARCH_INS_VSRLRNI_H_W = 1103
+LOONGARCH_INS_VSRLRNI_W_D = 1104
+LOONGARCH_INS_VSRLRN_B_H = 1105
+LOONGARCH_INS_VSRLRN_H_W = 1106
+LOONGARCH_INS_VSRLRN_W_D = 1107
+LOONGARCH_INS_VSRLR_B = 1108
+LOONGARCH_INS_VSRLR_D = 1109
+LOONGARCH_INS_VSRLR_H = 1110
+LOONGARCH_INS_VSRLR_W = 1111
+LOONGARCH_INS_VSRL_B = 1112
+LOONGARCH_INS_VSRL_D = 1113
+LOONGARCH_INS_VSRL_H = 1114
+LOONGARCH_INS_VSRL_W = 1115
+LOONGARCH_INS_VSSRANI_BU_H = 1116
+LOONGARCH_INS_VSSRANI_B_H = 1117
+LOONGARCH_INS_VSSRANI_DU_Q = 1118
+LOONGARCH_INS_VSSRANI_D_Q = 1119
+LOONGARCH_INS_VSSRANI_HU_W = 1120
+LOONGARCH_INS_VSSRANI_H_W = 1121
+LOONGARCH_INS_VSSRANI_WU_D = 1122
+LOONGARCH_INS_VSSRANI_W_D = 1123
+LOONGARCH_INS_VSSRAN_BU_H = 1124
+LOONGARCH_INS_VSSRAN_B_H = 1125
+LOONGARCH_INS_VSSRAN_HU_W = 1126
+LOONGARCH_INS_VSSRAN_H_W = 1127
+LOONGARCH_INS_VSSRAN_WU_D = 1128
+LOONGARCH_INS_VSSRAN_W_D = 1129
+LOONGARCH_INS_VSSRARNI_BU_H = 1130
+LOONGARCH_INS_VSSRARNI_B_H = 1131
+LOONGARCH_INS_VSSRARNI_DU_Q = 1132
+LOONGARCH_INS_VSSRARNI_D_Q = 1133
+LOONGARCH_INS_VSSRARNI_HU_W = 1134
+LOONGARCH_INS_VSSRARNI_H_W = 1135
+LOONGARCH_INS_VSSRARNI_WU_D = 1136
+LOONGARCH_INS_VSSRARNI_W_D = 1137
+LOONGARCH_INS_VSSRARN_BU_H = 1138
+LOONGARCH_INS_VSSRARN_B_H = 1139
+LOONGARCH_INS_VSSRARN_HU_W = 1140
+LOONGARCH_INS_VSSRARN_H_W = 1141
+LOONGARCH_INS_VSSRARN_WU_D = 1142
+LOONGARCH_INS_VSSRARN_W_D = 1143
+LOONGARCH_INS_VSSRLNI_BU_H = 1144
+LOONGARCH_INS_VSSRLNI_B_H = 1145
+LOONGARCH_INS_VSSRLNI_DU_Q = 1146
+LOONGARCH_INS_VSSRLNI_D_Q = 1147
+LOONGARCH_INS_VSSRLNI_HU_W = 1148
+LOONGARCH_INS_VSSRLNI_H_W = 1149
+LOONGARCH_INS_VSSRLNI_WU_D = 1150
+LOONGARCH_INS_VSSRLNI_W_D = 1151
+LOONGARCH_INS_VSSRLN_BU_H = 1152
+LOONGARCH_INS_VSSRLN_B_H = 1153
+LOONGARCH_INS_VSSRLN_HU_W = 1154
+LOONGARCH_INS_VSSRLN_H_W = 1155
+LOONGARCH_INS_VSSRLN_WU_D = 1156
+LOONGARCH_INS_VSSRLN_W_D = 1157
+LOONGARCH_INS_VSSRLRNI_BU_H = 1158
+LOONGARCH_INS_VSSRLRNI_B_H = 1159
+LOONGARCH_INS_VSSRLRNI_DU_Q = 1160
+LOONGARCH_INS_VSSRLRNI_D_Q = 1161
+LOONGARCH_INS_VSSRLRNI_HU_W = 1162
+LOONGARCH_INS_VSSRLRNI_H_W = 1163
+LOONGARCH_INS_VSSRLRNI_WU_D = 1164
+LOONGARCH_INS_VSSRLRNI_W_D = 1165
+LOONGARCH_INS_VSSRLRN_BU_H = 1166
+LOONGARCH_INS_VSSRLRN_B_H = 1167
+LOONGARCH_INS_VSSRLRN_HU_W = 1168
+LOONGARCH_INS_VSSRLRN_H_W = 1169
+LOONGARCH_INS_VSSRLRN_WU_D = 1170
+LOONGARCH_INS_VSSRLRN_W_D = 1171
+LOONGARCH_INS_VSSUB_B = 1172
+LOONGARCH_INS_VSSUB_BU = 1173
+LOONGARCH_INS_VSSUB_D = 1174
+LOONGARCH_INS_VSSUB_DU = 1175
+LOONGARCH_INS_VSSUB_H = 1176
+LOONGARCH_INS_VSSUB_HU = 1177
+LOONGARCH_INS_VSSUB_W = 1178
+LOONGARCH_INS_VSSUB_WU = 1179
+LOONGARCH_INS_VST = 1180
+LOONGARCH_INS_VSTELM_B = 1181
+LOONGARCH_INS_VSTELM_D = 1182
+LOONGARCH_INS_VSTELM_H = 1183
+LOONGARCH_INS_VSTELM_W = 1184
+LOONGARCH_INS_VSTX = 1185
+LOONGARCH_INS_VSUBI_BU = 1186
+LOONGARCH_INS_VSUBI_DU = 1187
+LOONGARCH_INS_VSUBI_HU = 1188
+LOONGARCH_INS_VSUBI_WU = 1189
+LOONGARCH_INS_VSUBWEV_D_W = 1190
+LOONGARCH_INS_VSUBWEV_D_WU = 1191
+LOONGARCH_INS_VSUBWEV_H_B = 1192
+LOONGARCH_INS_VSUBWEV_H_BU = 1193
+LOONGARCH_INS_VSUBWEV_Q_D = 1194
+LOONGARCH_INS_VSUBWEV_Q_DU = 1195
+LOONGARCH_INS_VSUBWEV_W_H = 1196
+LOONGARCH_INS_VSUBWEV_W_HU = 1197
+LOONGARCH_INS_VSUBWOD_D_W = 1198
+LOONGARCH_INS_VSUBWOD_D_WU = 1199
+LOONGARCH_INS_VSUBWOD_H_B = 1200
+LOONGARCH_INS_VSUBWOD_H_BU = 1201
+LOONGARCH_INS_VSUBWOD_Q_D = 1202
+LOONGARCH_INS_VSUBWOD_Q_DU = 1203
+LOONGARCH_INS_VSUBWOD_W_H = 1204
+LOONGARCH_INS_VSUBWOD_W_HU = 1205
+LOONGARCH_INS_VSUB_B = 1206
+LOONGARCH_INS_VSUB_D = 1207
+LOONGARCH_INS_VSUB_H = 1208
+LOONGARCH_INS_VSUB_Q = 1209
+LOONGARCH_INS_VSUB_W = 1210
+LOONGARCH_INS_VXORI_B = 1211
+LOONGARCH_INS_VXOR_V = 1212
+LOONGARCH_INS_X86ADC_B = 1213
+LOONGARCH_INS_X86ADC_D = 1214
+LOONGARCH_INS_X86ADC_H = 1215
+LOONGARCH_INS_X86ADC_W = 1216
+LOONGARCH_INS_X86ADD_B = 1217
+LOONGARCH_INS_X86ADD_D = 1218
+LOONGARCH_INS_X86ADD_DU = 1219
+LOONGARCH_INS_X86ADD_H = 1220
+LOONGARCH_INS_X86ADD_W = 1221
+LOONGARCH_INS_X86ADD_WU = 1222
+LOONGARCH_INS_X86AND_B = 1223
+LOONGARCH_INS_X86AND_D = 1224
+LOONGARCH_INS_X86AND_H = 1225
+LOONGARCH_INS_X86AND_W = 1226
+LOONGARCH_INS_X86CLRTM = 1227
+LOONGARCH_INS_X86DECTOP = 1228
+LOONGARCH_INS_X86DEC_B = 1229
+LOONGARCH_INS_X86DEC_D = 1230
+LOONGARCH_INS_X86DEC_H = 1231
+LOONGARCH_INS_X86DEC_W = 1232
+LOONGARCH_INS_X86INCTOP = 1233
+LOONGARCH_INS_X86INC_B = 1234
+LOONGARCH_INS_X86INC_D = 1235
+LOONGARCH_INS_X86INC_H = 1236
+LOONGARCH_INS_X86INC_W = 1237
+LOONGARCH_INS_X86MFFLAG = 1238
+LOONGARCH_INS_X86MFTOP = 1239
+LOONGARCH_INS_X86MTFLAG = 1240
+LOONGARCH_INS_X86MTTOP = 1241
+LOONGARCH_INS_X86MUL_B = 1242
+LOONGARCH_INS_X86MUL_BU = 1243
+LOONGARCH_INS_X86MUL_D = 1244
+LOONGARCH_INS_X86MUL_DU = 1245
+LOONGARCH_INS_X86MUL_H = 1246
+LOONGARCH_INS_X86MUL_HU = 1247
+LOONGARCH_INS_X86MUL_W = 1248
+LOONGARCH_INS_X86MUL_WU = 1249
+LOONGARCH_INS_X86OR_B = 1250
+LOONGARCH_INS_X86OR_D = 1251
+LOONGARCH_INS_X86OR_H = 1252
+LOONGARCH_INS_X86OR_W = 1253
+LOONGARCH_INS_X86RCLI_B = 1254
+LOONGARCH_INS_X86RCLI_D = 1255
+LOONGARCH_INS_X86RCLI_H = 1256
+LOONGARCH_INS_X86RCLI_W = 1257
+LOONGARCH_INS_X86RCL_B = 1258
+LOONGARCH_INS_X86RCL_D = 1259
+LOONGARCH_INS_X86RCL_H = 1260
+LOONGARCH_INS_X86RCL_W = 1261
+LOONGARCH_INS_X86RCRI_B = 1262
+LOONGARCH_INS_X86RCRI_D = 1263
+LOONGARCH_INS_X86RCRI_H = 1264
+LOONGARCH_INS_X86RCRI_W = 1265
+LOONGARCH_INS_X86RCR_B = 1266
+LOONGARCH_INS_X86RCR_D = 1267
+LOONGARCH_INS_X86RCR_H = 1268
+LOONGARCH_INS_X86RCR_W = 1269
+LOONGARCH_INS_X86ROTLI_B = 1270
+LOONGARCH_INS_X86ROTLI_D = 1271
+LOONGARCH_INS_X86ROTLI_H = 1272
+LOONGARCH_INS_X86ROTLI_W = 1273
+LOONGARCH_INS_X86ROTL_B = 1274
+LOONGARCH_INS_X86ROTL_D = 1275
+LOONGARCH_INS_X86ROTL_H = 1276
+LOONGARCH_INS_X86ROTL_W = 1277
+LOONGARCH_INS_X86ROTRI_B = 1278
+LOONGARCH_INS_X86ROTRI_D = 1279
+LOONGARCH_INS_X86ROTRI_H = 1280
+LOONGARCH_INS_X86ROTRI_W = 1281
+LOONGARCH_INS_X86ROTR_B = 1282
+LOONGARCH_INS_X86ROTR_D = 1283
+LOONGARCH_INS_X86ROTR_H = 1284
+LOONGARCH_INS_X86ROTR_W = 1285
+LOONGARCH_INS_X86SBC_B = 1286
+LOONGARCH_INS_X86SBC_D = 1287
+LOONGARCH_INS_X86SBC_H = 1288
+LOONGARCH_INS_X86SBC_W = 1289
+LOONGARCH_INS_X86SETTAG = 1290
+LOONGARCH_INS_X86SETTM = 1291
+LOONGARCH_INS_X86SLLI_B = 1292
+LOONGARCH_INS_X86SLLI_D = 1293
+LOONGARCH_INS_X86SLLI_H = 1294
+LOONGARCH_INS_X86SLLI_W = 1295
+LOONGARCH_INS_X86SLL_B = 1296
+LOONGARCH_INS_X86SLL_D = 1297
+LOONGARCH_INS_X86SLL_H = 1298
+LOONGARCH_INS_X86SLL_W = 1299
+LOONGARCH_INS_X86SRAI_B = 1300
+LOONGARCH_INS_X86SRAI_D = 1301
+LOONGARCH_INS_X86SRAI_H = 1302
+LOONGARCH_INS_X86SRAI_W = 1303
+LOONGARCH_INS_X86SRA_B = 1304
+LOONGARCH_INS_X86SRA_D = 1305
+LOONGARCH_INS_X86SRA_H = 1306
+LOONGARCH_INS_X86SRA_W = 1307
+LOONGARCH_INS_X86SRLI_B = 1308
+LOONGARCH_INS_X86SRLI_D = 1309
+LOONGARCH_INS_X86SRLI_H = 1310
+LOONGARCH_INS_X86SRLI_W = 1311
+LOONGARCH_INS_X86SRL_B = 1312
+LOONGARCH_INS_X86SRL_D = 1313
+LOONGARCH_INS_X86SRL_H = 1314
+LOONGARCH_INS_X86SRL_W = 1315
+LOONGARCH_INS_X86SUB_B = 1316
+LOONGARCH_INS_X86SUB_D = 1317
+LOONGARCH_INS_X86SUB_DU = 1318
+LOONGARCH_INS_X86SUB_H = 1319
+LOONGARCH_INS_X86SUB_W = 1320
+LOONGARCH_INS_X86SUB_WU = 1321
+LOONGARCH_INS_X86XOR_B = 1322
+LOONGARCH_INS_X86XOR_D = 1323
+LOONGARCH_INS_X86XOR_H = 1324
+LOONGARCH_INS_X86XOR_W = 1325
+LOONGARCH_INS_XOR = 1326
+LOONGARCH_INS_XORI = 1327
+LOONGARCH_INS_XVABSD_B = 1328
+LOONGARCH_INS_XVABSD_BU = 1329
+LOONGARCH_INS_XVABSD_D = 1330
+LOONGARCH_INS_XVABSD_DU = 1331
+LOONGARCH_INS_XVABSD_H = 1332
+LOONGARCH_INS_XVABSD_HU = 1333
+LOONGARCH_INS_XVABSD_W = 1334
+LOONGARCH_INS_XVABSD_WU = 1335
+LOONGARCH_INS_XVADDA_B = 1336
+LOONGARCH_INS_XVADDA_D = 1337
+LOONGARCH_INS_XVADDA_H = 1338
+LOONGARCH_INS_XVADDA_W = 1339
+LOONGARCH_INS_XVADDI_BU = 1340
+LOONGARCH_INS_XVADDI_DU = 1341
+LOONGARCH_INS_XVADDI_HU = 1342
+LOONGARCH_INS_XVADDI_WU = 1343
+LOONGARCH_INS_XVADDWEV_D_W = 1344
+LOONGARCH_INS_XVADDWEV_D_WU = 1345
+LOONGARCH_INS_XVADDWEV_D_WU_W = 1346
+LOONGARCH_INS_XVADDWEV_H_B = 1347
+LOONGARCH_INS_XVADDWEV_H_BU = 1348
+LOONGARCH_INS_XVADDWEV_H_BU_B = 1349
+LOONGARCH_INS_XVADDWEV_Q_D = 1350
+LOONGARCH_INS_XVADDWEV_Q_DU = 1351
+LOONGARCH_INS_XVADDWEV_Q_DU_D = 1352
+LOONGARCH_INS_XVADDWEV_W_H = 1353
+LOONGARCH_INS_XVADDWEV_W_HU = 1354
+LOONGARCH_INS_XVADDWEV_W_HU_H = 1355
+LOONGARCH_INS_XVADDWOD_D_W = 1356
+LOONGARCH_INS_XVADDWOD_D_WU = 1357
+LOONGARCH_INS_XVADDWOD_D_WU_W = 1358
+LOONGARCH_INS_XVADDWOD_H_B = 1359
+LOONGARCH_INS_XVADDWOD_H_BU = 1360
+LOONGARCH_INS_XVADDWOD_H_BU_B = 1361
+LOONGARCH_INS_XVADDWOD_Q_D = 1362
+LOONGARCH_INS_XVADDWOD_Q_DU = 1363
+LOONGARCH_INS_XVADDWOD_Q_DU_D = 1364
+LOONGARCH_INS_XVADDWOD_W_H = 1365
+LOONGARCH_INS_XVADDWOD_W_HU = 1366
+LOONGARCH_INS_XVADDWOD_W_HU_H = 1367
+LOONGARCH_INS_XVADD_B = 1368
+LOONGARCH_INS_XVADD_D = 1369
+LOONGARCH_INS_XVADD_H = 1370
+LOONGARCH_INS_XVADD_Q = 1371
+LOONGARCH_INS_XVADD_W = 1372
+LOONGARCH_INS_XVANDI_B = 1373
+LOONGARCH_INS_XVANDN_V = 1374
+LOONGARCH_INS_XVAND_V = 1375
+LOONGARCH_INS_XVAVGR_B = 1376
+LOONGARCH_INS_XVAVGR_BU = 1377
+LOONGARCH_INS_XVAVGR_D = 1378
+LOONGARCH_INS_XVAVGR_DU = 1379
+LOONGARCH_INS_XVAVGR_H = 1380
+LOONGARCH_INS_XVAVGR_HU = 1381
+LOONGARCH_INS_XVAVGR_W = 1382
+LOONGARCH_INS_XVAVGR_WU = 1383
+LOONGARCH_INS_XVAVG_B = 1384
+LOONGARCH_INS_XVAVG_BU = 1385
+LOONGARCH_INS_XVAVG_D = 1386
+LOONGARCH_INS_XVAVG_DU = 1387
+LOONGARCH_INS_XVAVG_H = 1388
+LOONGARCH_INS_XVAVG_HU = 1389
+LOONGARCH_INS_XVAVG_W = 1390
+LOONGARCH_INS_XVAVG_WU = 1391
+LOONGARCH_INS_XVBITCLRI_B = 1392
+LOONGARCH_INS_XVBITCLRI_D = 1393
+LOONGARCH_INS_XVBITCLRI_H = 1394
+LOONGARCH_INS_XVBITCLRI_W = 1395
+LOONGARCH_INS_XVBITCLR_B = 1396
+LOONGARCH_INS_XVBITCLR_D = 1397
+LOONGARCH_INS_XVBITCLR_H = 1398
+LOONGARCH_INS_XVBITCLR_W = 1399
+LOONGARCH_INS_XVBITREVI_B = 1400
+LOONGARCH_INS_XVBITREVI_D = 1401
+LOONGARCH_INS_XVBITREVI_H = 1402
+LOONGARCH_INS_XVBITREVI_W = 1403
+LOONGARCH_INS_XVBITREV_B = 1404
+LOONGARCH_INS_XVBITREV_D = 1405
+LOONGARCH_INS_XVBITREV_H = 1406
+LOONGARCH_INS_XVBITREV_W = 1407
+LOONGARCH_INS_XVBITSELI_B = 1408
+LOONGARCH_INS_XVBITSEL_V = 1409
+LOONGARCH_INS_XVBITSETI_B = 1410
+LOONGARCH_INS_XVBITSETI_D = 1411
+LOONGARCH_INS_XVBITSETI_H = 1412
+LOONGARCH_INS_XVBITSETI_W = 1413
+LOONGARCH_INS_XVBITSET_B = 1414
+LOONGARCH_INS_XVBITSET_D = 1415
+LOONGARCH_INS_XVBITSET_H = 1416
+LOONGARCH_INS_XVBITSET_W = 1417
+LOONGARCH_INS_XVBSLL_V = 1418
+LOONGARCH_INS_XVBSRL_V = 1419
+LOONGARCH_INS_XVCLO_B = 1420
+LOONGARCH_INS_XVCLO_D = 1421
+LOONGARCH_INS_XVCLO_H = 1422
+LOONGARCH_INS_XVCLO_W = 1423
+LOONGARCH_INS_XVCLZ_B = 1424
+LOONGARCH_INS_XVCLZ_D = 1425
+LOONGARCH_INS_XVCLZ_H = 1426
+LOONGARCH_INS_XVCLZ_W = 1427
+LOONGARCH_INS_XVDIV_B = 1428
+LOONGARCH_INS_XVDIV_BU = 1429
+LOONGARCH_INS_XVDIV_D = 1430
+LOONGARCH_INS_XVDIV_DU = 1431
+LOONGARCH_INS_XVDIV_H = 1432
+LOONGARCH_INS_XVDIV_HU = 1433
+LOONGARCH_INS_XVDIV_W = 1434
+LOONGARCH_INS_XVDIV_WU = 1435
+LOONGARCH_INS_XVEXTH_DU_WU = 1436
+LOONGARCH_INS_XVEXTH_D_W = 1437
+LOONGARCH_INS_XVEXTH_HU_BU = 1438
+LOONGARCH_INS_XVEXTH_H_B = 1439
+LOONGARCH_INS_XVEXTH_QU_DU = 1440
+LOONGARCH_INS_XVEXTH_Q_D = 1441
+LOONGARCH_INS_XVEXTH_WU_HU = 1442
+LOONGARCH_INS_XVEXTH_W_H = 1443
+LOONGARCH_INS_XVEXTL_QU_DU = 1444
+LOONGARCH_INS_XVEXTL_Q_D = 1445
+LOONGARCH_INS_XVEXTRINS_B = 1446
+LOONGARCH_INS_XVEXTRINS_D = 1447
+LOONGARCH_INS_XVEXTRINS_H = 1448
+LOONGARCH_INS_XVEXTRINS_W = 1449
+LOONGARCH_INS_XVFADD_D = 1450
+LOONGARCH_INS_XVFADD_S = 1451
+LOONGARCH_INS_XVFCLASS_D = 1452
+LOONGARCH_INS_XVFCLASS_S = 1453
+LOONGARCH_INS_XVFCMP_CAF_D = 1454
+LOONGARCH_INS_XVFCMP_CAF_S = 1455
+LOONGARCH_INS_XVFCMP_CEQ_D = 1456
+LOONGARCH_INS_XVFCMP_CEQ_S = 1457
+LOONGARCH_INS_XVFCMP_CLE_D = 1458
+LOONGARCH_INS_XVFCMP_CLE_S = 1459
+LOONGARCH_INS_XVFCMP_CLT_D = 1460
+LOONGARCH_INS_XVFCMP_CLT_S = 1461
+LOONGARCH_INS_XVFCMP_CNE_D = 1462
+LOONGARCH_INS_XVFCMP_CNE_S = 1463
+LOONGARCH_INS_XVFCMP_COR_D = 1464
+LOONGARCH_INS_XVFCMP_COR_S = 1465
+LOONGARCH_INS_XVFCMP_CUEQ_D = 1466
+LOONGARCH_INS_XVFCMP_CUEQ_S = 1467
+LOONGARCH_INS_XVFCMP_CULE_D = 1468
+LOONGARCH_INS_XVFCMP_CULE_S = 1469
+LOONGARCH_INS_XVFCMP_CULT_D = 1470
+LOONGARCH_INS_XVFCMP_CULT_S = 1471
+LOONGARCH_INS_XVFCMP_CUNE_D = 1472
+LOONGARCH_INS_XVFCMP_CUNE_S = 1473
+LOONGARCH_INS_XVFCMP_CUN_D = 1474
+LOONGARCH_INS_XVFCMP_CUN_S = 1475
+LOONGARCH_INS_XVFCMP_SAF_D = 1476
+LOONGARCH_INS_XVFCMP_SAF_S = 1477
+LOONGARCH_INS_XVFCMP_SEQ_D = 1478
+LOONGARCH_INS_XVFCMP_SEQ_S = 1479
+LOONGARCH_INS_XVFCMP_SLE_D = 1480
+LOONGARCH_INS_XVFCMP_SLE_S = 1481
+LOONGARCH_INS_XVFCMP_SLT_D = 1482
+LOONGARCH_INS_XVFCMP_SLT_S = 1483
+LOONGARCH_INS_XVFCMP_SNE_D = 1484
+LOONGARCH_INS_XVFCMP_SNE_S = 1485
+LOONGARCH_INS_XVFCMP_SOR_D = 1486
+LOONGARCH_INS_XVFCMP_SOR_S = 1487
+LOONGARCH_INS_XVFCMP_SUEQ_D = 1488
+LOONGARCH_INS_XVFCMP_SUEQ_S = 1489
+LOONGARCH_INS_XVFCMP_SULE_D = 1490
+LOONGARCH_INS_XVFCMP_SULE_S = 1491
+LOONGARCH_INS_XVFCMP_SULT_D = 1492
+LOONGARCH_INS_XVFCMP_SULT_S = 1493
+LOONGARCH_INS_XVFCMP_SUNE_D = 1494
+LOONGARCH_INS_XVFCMP_SUNE_S = 1495
+LOONGARCH_INS_XVFCMP_SUN_D = 1496
+LOONGARCH_INS_XVFCMP_SUN_S = 1497
+LOONGARCH_INS_XVFCVTH_D_S = 1498
+LOONGARCH_INS_XVFCVTH_S_H = 1499
+LOONGARCH_INS_XVFCVTL_D_S = 1500
+LOONGARCH_INS_XVFCVTL_S_H = 1501
+LOONGARCH_INS_XVFCVT_H_S = 1502
+LOONGARCH_INS_XVFCVT_S_D = 1503
+LOONGARCH_INS_XVFDIV_D = 1504
+LOONGARCH_INS_XVFDIV_S = 1505
+LOONGARCH_INS_XVFFINTH_D_W = 1506
+LOONGARCH_INS_XVFFINTL_D_W = 1507
+LOONGARCH_INS_XVFFINT_D_L = 1508
+LOONGARCH_INS_XVFFINT_D_LU = 1509
+LOONGARCH_INS_XVFFINT_S_L = 1510
+LOONGARCH_INS_XVFFINT_S_W = 1511
+LOONGARCH_INS_XVFFINT_S_WU = 1512
+LOONGARCH_INS_XVFLOGB_D = 1513
+LOONGARCH_INS_XVFLOGB_S = 1514
+LOONGARCH_INS_XVFMADD_D = 1515
+LOONGARCH_INS_XVFMADD_S = 1516
+LOONGARCH_INS_XVFMAXA_D = 1517
+LOONGARCH_INS_XVFMAXA_S = 1518
+LOONGARCH_INS_XVFMAX_D = 1519
+LOONGARCH_INS_XVFMAX_S = 1520
+LOONGARCH_INS_XVFMINA_D = 1521
+LOONGARCH_INS_XVFMINA_S = 1522
+LOONGARCH_INS_XVFMIN_D = 1523
+LOONGARCH_INS_XVFMIN_S = 1524
+LOONGARCH_INS_XVFMSUB_D = 1525
+LOONGARCH_INS_XVFMSUB_S = 1526
+LOONGARCH_INS_XVFMUL_D = 1527
+LOONGARCH_INS_XVFMUL_S = 1528
+LOONGARCH_INS_XVFNMADD_D = 1529
+LOONGARCH_INS_XVFNMADD_S = 1530
+LOONGARCH_INS_XVFNMSUB_D = 1531
+LOONGARCH_INS_XVFNMSUB_S = 1532
+LOONGARCH_INS_XVFRECIPE_D = 1533
+LOONGARCH_INS_XVFRECIPE_S = 1534
+LOONGARCH_INS_XVFRECIP_D = 1535
+LOONGARCH_INS_XVFRECIP_S = 1536
+LOONGARCH_INS_XVFRINTRM_D = 1537
+LOONGARCH_INS_XVFRINTRM_S = 1538
+LOONGARCH_INS_XVFRINTRNE_D = 1539
+LOONGARCH_INS_XVFRINTRNE_S = 1540
+LOONGARCH_INS_XVFRINTRP_D = 1541
+LOONGARCH_INS_XVFRINTRP_S = 1542
+LOONGARCH_INS_XVFRINTRZ_D = 1543
+LOONGARCH_INS_XVFRINTRZ_S = 1544
+LOONGARCH_INS_XVFRINT_D = 1545
+LOONGARCH_INS_XVFRINT_S = 1546
+LOONGARCH_INS_XVFRSQRTE_D = 1547
+LOONGARCH_INS_XVFRSQRTE_S = 1548
+LOONGARCH_INS_XVFRSQRT_D = 1549
+LOONGARCH_INS_XVFRSQRT_S = 1550
+LOONGARCH_INS_XVFRSTPI_B = 1551
+LOONGARCH_INS_XVFRSTPI_H = 1552
+LOONGARCH_INS_XVFRSTP_B = 1553
+LOONGARCH_INS_XVFRSTP_H = 1554
+LOONGARCH_INS_XVFSQRT_D = 1555
+LOONGARCH_INS_XVFSQRT_S = 1556
+LOONGARCH_INS_XVFSUB_D = 1557
+LOONGARCH_INS_XVFSUB_S = 1558
+LOONGARCH_INS_XVFTINTH_L_S = 1559
+LOONGARCH_INS_XVFTINTL_L_S = 1560
+LOONGARCH_INS_XVFTINTRMH_L_S = 1561
+LOONGARCH_INS_XVFTINTRML_L_S = 1562
+LOONGARCH_INS_XVFTINTRM_L_D = 1563
+LOONGARCH_INS_XVFTINTRM_W_D = 1564
+LOONGARCH_INS_XVFTINTRM_W_S = 1565
+LOONGARCH_INS_XVFTINTRNEH_L_S = 1566
+LOONGARCH_INS_XVFTINTRNEL_L_S = 1567
+LOONGARCH_INS_XVFTINTRNE_L_D = 1568
+LOONGARCH_INS_XVFTINTRNE_W_D = 1569
+LOONGARCH_INS_XVFTINTRNE_W_S = 1570
+LOONGARCH_INS_XVFTINTRPH_L_S = 1571
+LOONGARCH_INS_XVFTINTRPL_L_S = 1572
+LOONGARCH_INS_XVFTINTRP_L_D = 1573
+LOONGARCH_INS_XVFTINTRP_W_D = 1574
+LOONGARCH_INS_XVFTINTRP_W_S = 1575
+LOONGARCH_INS_XVFTINTRZH_L_S = 1576
+LOONGARCH_INS_XVFTINTRZL_L_S = 1577
+LOONGARCH_INS_XVFTINTRZ_LU_D = 1578
+LOONGARCH_INS_XVFTINTRZ_L_D = 1579
+LOONGARCH_INS_XVFTINTRZ_WU_S = 1580
+LOONGARCH_INS_XVFTINTRZ_W_D = 1581
+LOONGARCH_INS_XVFTINTRZ_W_S = 1582
+LOONGARCH_INS_XVFTINT_LU_D = 1583
+LOONGARCH_INS_XVFTINT_L_D = 1584
+LOONGARCH_INS_XVFTINT_WU_S = 1585
+LOONGARCH_INS_XVFTINT_W_D = 1586
+LOONGARCH_INS_XVFTINT_W_S = 1587
+LOONGARCH_INS_XVHADDW_DU_WU = 1588
+LOONGARCH_INS_XVHADDW_D_W = 1589
+LOONGARCH_INS_XVHADDW_HU_BU = 1590
+LOONGARCH_INS_XVHADDW_H_B = 1591
+LOONGARCH_INS_XVHADDW_QU_DU = 1592
+LOONGARCH_INS_XVHADDW_Q_D = 1593
+LOONGARCH_INS_XVHADDW_WU_HU = 1594
+LOONGARCH_INS_XVHADDW_W_H = 1595
+LOONGARCH_INS_XVHSELI_D = 1596
+LOONGARCH_INS_XVHSUBW_DU_WU = 1597
+LOONGARCH_INS_XVHSUBW_D_W = 1598
+LOONGARCH_INS_XVHSUBW_HU_BU = 1599
+LOONGARCH_INS_XVHSUBW_H_B = 1600
+LOONGARCH_INS_XVHSUBW_QU_DU = 1601
+LOONGARCH_INS_XVHSUBW_Q_D = 1602
+LOONGARCH_INS_XVHSUBW_WU_HU = 1603
+LOONGARCH_INS_XVHSUBW_W_H = 1604
+LOONGARCH_INS_XVILVH_B = 1605
+LOONGARCH_INS_XVILVH_D = 1606
+LOONGARCH_INS_XVILVH_H = 1607
+LOONGARCH_INS_XVILVH_W = 1608
+LOONGARCH_INS_XVILVL_B = 1609
+LOONGARCH_INS_XVILVL_D = 1610
+LOONGARCH_INS_XVILVL_H = 1611
+LOONGARCH_INS_XVILVL_W = 1612
+LOONGARCH_INS_XVINSGR2VR_D = 1613
+LOONGARCH_INS_XVINSGR2VR_W = 1614
+LOONGARCH_INS_XVINSVE0_D = 1615
+LOONGARCH_INS_XVINSVE0_W = 1616
+LOONGARCH_INS_XVLD = 1617
+LOONGARCH_INS_XVLDI = 1618
+LOONGARCH_INS_XVLDREPL_B = 1619
+LOONGARCH_INS_XVLDREPL_D = 1620
+LOONGARCH_INS_XVLDREPL_H = 1621
+LOONGARCH_INS_XVLDREPL_W = 1622
+LOONGARCH_INS_XVLDX = 1623
+LOONGARCH_INS_XVMADDWEV_D_W = 1624
+LOONGARCH_INS_XVMADDWEV_D_WU = 1625
+LOONGARCH_INS_XVMADDWEV_D_WU_W = 1626
+LOONGARCH_INS_XVMADDWEV_H_B = 1627
+LOONGARCH_INS_XVMADDWEV_H_BU = 1628
+LOONGARCH_INS_XVMADDWEV_H_BU_B = 1629
+LOONGARCH_INS_XVMADDWEV_Q_D = 1630
+LOONGARCH_INS_XVMADDWEV_Q_DU = 1631
+LOONGARCH_INS_XVMADDWEV_Q_DU_D = 1632
+LOONGARCH_INS_XVMADDWEV_W_H = 1633
+LOONGARCH_INS_XVMADDWEV_W_HU = 1634
+LOONGARCH_INS_XVMADDWEV_W_HU_H = 1635
+LOONGARCH_INS_XVMADDWOD_D_W = 1636
+LOONGARCH_INS_XVMADDWOD_D_WU = 1637
+LOONGARCH_INS_XVMADDWOD_D_WU_W = 1638
+LOONGARCH_INS_XVMADDWOD_H_B = 1639
+LOONGARCH_INS_XVMADDWOD_H_BU = 1640
+LOONGARCH_INS_XVMADDWOD_H_BU_B = 1641
+LOONGARCH_INS_XVMADDWOD_Q_D = 1642
+LOONGARCH_INS_XVMADDWOD_Q_DU = 1643
+LOONGARCH_INS_XVMADDWOD_Q_DU_D = 1644
+LOONGARCH_INS_XVMADDWOD_W_H = 1645
+LOONGARCH_INS_XVMADDWOD_W_HU = 1646
+LOONGARCH_INS_XVMADDWOD_W_HU_H = 1647
+LOONGARCH_INS_XVMADD_B = 1648
+LOONGARCH_INS_XVMADD_D = 1649
+LOONGARCH_INS_XVMADD_H = 1650
+LOONGARCH_INS_XVMADD_W = 1651
+LOONGARCH_INS_XVMAXI_B = 1652
+LOONGARCH_INS_XVMAXI_BU = 1653
+LOONGARCH_INS_XVMAXI_D = 1654
+LOONGARCH_INS_XVMAXI_DU = 1655
+LOONGARCH_INS_XVMAXI_H = 1656
+LOONGARCH_INS_XVMAXI_HU = 1657
+LOONGARCH_INS_XVMAXI_W = 1658
+LOONGARCH_INS_XVMAXI_WU = 1659
+LOONGARCH_INS_XVMAX_B = 1660
+LOONGARCH_INS_XVMAX_BU = 1661
+LOONGARCH_INS_XVMAX_D = 1662
+LOONGARCH_INS_XVMAX_DU = 1663
+LOONGARCH_INS_XVMAX_H = 1664
+LOONGARCH_INS_XVMAX_HU = 1665
+LOONGARCH_INS_XVMAX_W = 1666
+LOONGARCH_INS_XVMAX_WU = 1667
+LOONGARCH_INS_XVMINI_B = 1668
+LOONGARCH_INS_XVMINI_BU = 1669
+LOONGARCH_INS_XVMINI_D = 1670
+LOONGARCH_INS_XVMINI_DU = 1671
+LOONGARCH_INS_XVMINI_H = 1672
+LOONGARCH_INS_XVMINI_HU = 1673
+LOONGARCH_INS_XVMINI_W = 1674
+LOONGARCH_INS_XVMINI_WU = 1675
+LOONGARCH_INS_XVMIN_B = 1676
+LOONGARCH_INS_XVMIN_BU = 1677
+LOONGARCH_INS_XVMIN_D = 1678
+LOONGARCH_INS_XVMIN_DU = 1679
+LOONGARCH_INS_XVMIN_H = 1680
+LOONGARCH_INS_XVMIN_HU = 1681
+LOONGARCH_INS_XVMIN_W = 1682
+LOONGARCH_INS_XVMIN_WU = 1683
+LOONGARCH_INS_XVMOD_B = 1684
+LOONGARCH_INS_XVMOD_BU = 1685
+LOONGARCH_INS_XVMOD_D = 1686
+LOONGARCH_INS_XVMOD_DU = 1687
+LOONGARCH_INS_XVMOD_H = 1688
+LOONGARCH_INS_XVMOD_HU = 1689
+LOONGARCH_INS_XVMOD_W = 1690
+LOONGARCH_INS_XVMOD_WU = 1691
+LOONGARCH_INS_XVMSKGEZ_B = 1692
+LOONGARCH_INS_XVMSKLTZ_B = 1693
+LOONGARCH_INS_XVMSKLTZ_D = 1694
+LOONGARCH_INS_XVMSKLTZ_H = 1695
+LOONGARCH_INS_XVMSKLTZ_W = 1696
+LOONGARCH_INS_XVMSKNZ_B = 1697
+LOONGARCH_INS_XVMSUB_B = 1698
+LOONGARCH_INS_XVMSUB_D = 1699
+LOONGARCH_INS_XVMSUB_H = 1700
+LOONGARCH_INS_XVMSUB_W = 1701
+LOONGARCH_INS_XVMUH_B = 1702
+LOONGARCH_INS_XVMUH_BU = 1703
+LOONGARCH_INS_XVMUH_D = 1704
+LOONGARCH_INS_XVMUH_DU = 1705
+LOONGARCH_INS_XVMUH_H = 1706
+LOONGARCH_INS_XVMUH_HU = 1707
+LOONGARCH_INS_XVMUH_W = 1708
+LOONGARCH_INS_XVMUH_WU = 1709
+LOONGARCH_INS_XVMULWEV_D_W = 1710
+LOONGARCH_INS_XVMULWEV_D_WU = 1711
+LOONGARCH_INS_XVMULWEV_D_WU_W = 1712
+LOONGARCH_INS_XVMULWEV_H_B = 1713
+LOONGARCH_INS_XVMULWEV_H_BU = 1714
+LOONGARCH_INS_XVMULWEV_H_BU_B = 1715
+LOONGARCH_INS_XVMULWEV_Q_D = 1716
+LOONGARCH_INS_XVMULWEV_Q_DU = 1717
+LOONGARCH_INS_XVMULWEV_Q_DU_D = 1718
+LOONGARCH_INS_XVMULWEV_W_H = 1719
+LOONGARCH_INS_XVMULWEV_W_HU = 1720
+LOONGARCH_INS_XVMULWEV_W_HU_H = 1721
+LOONGARCH_INS_XVMULWOD_D_W = 1722
+LOONGARCH_INS_XVMULWOD_D_WU = 1723
+LOONGARCH_INS_XVMULWOD_D_WU_W = 1724
+LOONGARCH_INS_XVMULWOD_H_B = 1725
+LOONGARCH_INS_XVMULWOD_H_BU = 1726
+LOONGARCH_INS_XVMULWOD_H_BU_B = 1727
+LOONGARCH_INS_XVMULWOD_Q_D = 1728
+LOONGARCH_INS_XVMULWOD_Q_DU = 1729
+LOONGARCH_INS_XVMULWOD_Q_DU_D = 1730
+LOONGARCH_INS_XVMULWOD_W_H = 1731
+LOONGARCH_INS_XVMULWOD_W_HU = 1732
+LOONGARCH_INS_XVMULWOD_W_HU_H = 1733
+LOONGARCH_INS_XVMUL_B = 1734
+LOONGARCH_INS_XVMUL_D = 1735
+LOONGARCH_INS_XVMUL_H = 1736
+LOONGARCH_INS_XVMUL_W = 1737
+LOONGARCH_INS_XVNEG_B = 1738
+LOONGARCH_INS_XVNEG_D = 1739
+LOONGARCH_INS_XVNEG_H = 1740
+LOONGARCH_INS_XVNEG_W = 1741
+LOONGARCH_INS_XVNORI_B = 1742
+LOONGARCH_INS_XVNOR_V = 1743
+LOONGARCH_INS_XVORI_B = 1744
+LOONGARCH_INS_XVORN_V = 1745
+LOONGARCH_INS_XVOR_V = 1746
+LOONGARCH_INS_XVPACKEV_B = 1747
+LOONGARCH_INS_XVPACKEV_D = 1748
+LOONGARCH_INS_XVPACKEV_H = 1749
+LOONGARCH_INS_XVPACKEV_W = 1750
+LOONGARCH_INS_XVPACKOD_B = 1751
+LOONGARCH_INS_XVPACKOD_D = 1752
+LOONGARCH_INS_XVPACKOD_H = 1753
+LOONGARCH_INS_XVPACKOD_W = 1754
+LOONGARCH_INS_XVPCNT_B = 1755
+LOONGARCH_INS_XVPCNT_D = 1756
+LOONGARCH_INS_XVPCNT_H = 1757
+LOONGARCH_INS_XVPCNT_W = 1758
+LOONGARCH_INS_XVPERMI_D = 1759
+LOONGARCH_INS_XVPERMI_Q = 1760
+LOONGARCH_INS_XVPERMI_W = 1761
+LOONGARCH_INS_XVPERM_W = 1762
+LOONGARCH_INS_XVPICKEV_B = 1763
+LOONGARCH_INS_XVPICKEV_D = 1764
+LOONGARCH_INS_XVPICKEV_H = 1765
+LOONGARCH_INS_XVPICKEV_W = 1766
+LOONGARCH_INS_XVPICKOD_B = 1767
+LOONGARCH_INS_XVPICKOD_D = 1768
+LOONGARCH_INS_XVPICKOD_H = 1769
+LOONGARCH_INS_XVPICKOD_W = 1770
+LOONGARCH_INS_XVPICKVE2GR_D = 1771
+LOONGARCH_INS_XVPICKVE2GR_DU = 1772
+LOONGARCH_INS_XVPICKVE2GR_W = 1773
+LOONGARCH_INS_XVPICKVE2GR_WU = 1774
+LOONGARCH_INS_XVPICKVE_D = 1775
+LOONGARCH_INS_XVPICKVE_W = 1776
+LOONGARCH_INS_XVREPL128VEI_B = 1777
+LOONGARCH_INS_XVREPL128VEI_D = 1778
+LOONGARCH_INS_XVREPL128VEI_H = 1779
+LOONGARCH_INS_XVREPL128VEI_W = 1780
+LOONGARCH_INS_XVREPLGR2VR_B = 1781
+LOONGARCH_INS_XVREPLGR2VR_D = 1782
+LOONGARCH_INS_XVREPLGR2VR_H = 1783
+LOONGARCH_INS_XVREPLGR2VR_W = 1784
+LOONGARCH_INS_XVREPLVE0_B = 1785
+LOONGARCH_INS_XVREPLVE0_D = 1786
+LOONGARCH_INS_XVREPLVE0_H = 1787
+LOONGARCH_INS_XVREPLVE0_Q = 1788
+LOONGARCH_INS_XVREPLVE0_W = 1789
+LOONGARCH_INS_XVREPLVE_B = 1790
+LOONGARCH_INS_XVREPLVE_D = 1791
+LOONGARCH_INS_XVREPLVE_H = 1792
+LOONGARCH_INS_XVREPLVE_W = 1793
+LOONGARCH_INS_XVROTRI_B = 1794
+LOONGARCH_INS_XVROTRI_D = 1795
+LOONGARCH_INS_XVROTRI_H = 1796
+LOONGARCH_INS_XVROTRI_W = 1797
+LOONGARCH_INS_XVROTR_B = 1798
+LOONGARCH_INS_XVROTR_D = 1799
+LOONGARCH_INS_XVROTR_H = 1800
+LOONGARCH_INS_XVROTR_W = 1801
+LOONGARCH_INS_XVSADD_B = 1802
+LOONGARCH_INS_XVSADD_BU = 1803
+LOONGARCH_INS_XVSADD_D = 1804
+LOONGARCH_INS_XVSADD_DU = 1805
+LOONGARCH_INS_XVSADD_H = 1806
+LOONGARCH_INS_XVSADD_HU = 1807
+LOONGARCH_INS_XVSADD_W = 1808
+LOONGARCH_INS_XVSADD_WU = 1809
+LOONGARCH_INS_XVSAT_B = 1810
+LOONGARCH_INS_XVSAT_BU = 1811
+LOONGARCH_INS_XVSAT_D = 1812
+LOONGARCH_INS_XVSAT_DU = 1813
+LOONGARCH_INS_XVSAT_H = 1814
+LOONGARCH_INS_XVSAT_HU = 1815
+LOONGARCH_INS_XVSAT_W = 1816
+LOONGARCH_INS_XVSAT_WU = 1817
+LOONGARCH_INS_XVSEQI_B = 1818
+LOONGARCH_INS_XVSEQI_D = 1819
+LOONGARCH_INS_XVSEQI_H = 1820
+LOONGARCH_INS_XVSEQI_W = 1821
+LOONGARCH_INS_XVSEQ_B = 1822
+LOONGARCH_INS_XVSEQ_D = 1823
+LOONGARCH_INS_XVSEQ_H = 1824
+LOONGARCH_INS_XVSEQ_W = 1825
+LOONGARCH_INS_XVSETALLNEZ_B = 1826
+LOONGARCH_INS_XVSETALLNEZ_D = 1827
+LOONGARCH_INS_XVSETALLNEZ_H = 1828
+LOONGARCH_INS_XVSETALLNEZ_W = 1829
+LOONGARCH_INS_XVSETANYEQZ_B = 1830
+LOONGARCH_INS_XVSETANYEQZ_D = 1831
+LOONGARCH_INS_XVSETANYEQZ_H = 1832
+LOONGARCH_INS_XVSETANYEQZ_W = 1833
+LOONGARCH_INS_XVSETEQZ_V = 1834
+LOONGARCH_INS_XVSETNEZ_V = 1835
+LOONGARCH_INS_XVSHUF4I_B = 1836
+LOONGARCH_INS_XVSHUF4I_D = 1837
+LOONGARCH_INS_XVSHUF4I_H = 1838
+LOONGARCH_INS_XVSHUF4I_W = 1839
+LOONGARCH_INS_XVSHUF_B = 1840
+LOONGARCH_INS_XVSHUF_D = 1841
+LOONGARCH_INS_XVSHUF_H = 1842
+LOONGARCH_INS_XVSHUF_W = 1843
+LOONGARCH_INS_XVSIGNCOV_B = 1844
+LOONGARCH_INS_XVSIGNCOV_D = 1845
+LOONGARCH_INS_XVSIGNCOV_H = 1846
+LOONGARCH_INS_XVSIGNCOV_W = 1847
+LOONGARCH_INS_XVSLEI_B = 1848
+LOONGARCH_INS_XVSLEI_BU = 1849
+LOONGARCH_INS_XVSLEI_D = 1850
+LOONGARCH_INS_XVSLEI_DU = 1851
+LOONGARCH_INS_XVSLEI_H = 1852
+LOONGARCH_INS_XVSLEI_HU = 1853
+LOONGARCH_INS_XVSLEI_W = 1854
+LOONGARCH_INS_XVSLEI_WU = 1855
+LOONGARCH_INS_XVSLE_B = 1856
+LOONGARCH_INS_XVSLE_BU = 1857
+LOONGARCH_INS_XVSLE_D = 1858
+LOONGARCH_INS_XVSLE_DU = 1859
+LOONGARCH_INS_XVSLE_H = 1860
+LOONGARCH_INS_XVSLE_HU = 1861
+LOONGARCH_INS_XVSLE_W = 1862
+LOONGARCH_INS_XVSLE_WU = 1863
+LOONGARCH_INS_XVSLLI_B = 1864
+LOONGARCH_INS_XVSLLI_D = 1865
+LOONGARCH_INS_XVSLLI_H = 1866
+LOONGARCH_INS_XVSLLI_W = 1867
+LOONGARCH_INS_XVSLLWIL_DU_WU = 1868
+LOONGARCH_INS_XVSLLWIL_D_W = 1869
+LOONGARCH_INS_XVSLLWIL_HU_BU = 1870
+LOONGARCH_INS_XVSLLWIL_H_B = 1871
+LOONGARCH_INS_XVSLLWIL_WU_HU = 1872
+LOONGARCH_INS_XVSLLWIL_W_H = 1873
+LOONGARCH_INS_XVSLL_B = 1874
+LOONGARCH_INS_XVSLL_D = 1875
+LOONGARCH_INS_XVSLL_H = 1876
+LOONGARCH_INS_XVSLL_W = 1877
+LOONGARCH_INS_XVSLTI_B = 1878
+LOONGARCH_INS_XVSLTI_BU = 1879
+LOONGARCH_INS_XVSLTI_D = 1880
+LOONGARCH_INS_XVSLTI_DU = 1881
+LOONGARCH_INS_XVSLTI_H = 1882
+LOONGARCH_INS_XVSLTI_HU = 1883
+LOONGARCH_INS_XVSLTI_W = 1884
+LOONGARCH_INS_XVSLTI_WU = 1885
+LOONGARCH_INS_XVSLT_B = 1886
+LOONGARCH_INS_XVSLT_BU = 1887
+LOONGARCH_INS_XVSLT_D = 1888
+LOONGARCH_INS_XVSLT_DU = 1889
+LOONGARCH_INS_XVSLT_H = 1890
+LOONGARCH_INS_XVSLT_HU = 1891
+LOONGARCH_INS_XVSLT_W = 1892
+LOONGARCH_INS_XVSLT_WU = 1893
+LOONGARCH_INS_XVSRAI_B = 1894
+LOONGARCH_INS_XVSRAI_D = 1895
+LOONGARCH_INS_XVSRAI_H = 1896
+LOONGARCH_INS_XVSRAI_W = 1897
+LOONGARCH_INS_XVSRANI_B_H = 1898
+LOONGARCH_INS_XVSRANI_D_Q = 1899
+LOONGARCH_INS_XVSRANI_H_W = 1900
+LOONGARCH_INS_XVSRANI_W_D = 1901
+LOONGARCH_INS_XVSRAN_B_H = 1902
+LOONGARCH_INS_XVSRAN_H_W = 1903
+LOONGARCH_INS_XVSRAN_W_D = 1904
+LOONGARCH_INS_XVSRARI_B = 1905
+LOONGARCH_INS_XVSRARI_D = 1906
+LOONGARCH_INS_XVSRARI_H = 1907
+LOONGARCH_INS_XVSRARI_W = 1908
+LOONGARCH_INS_XVSRARNI_B_H = 1909
+LOONGARCH_INS_XVSRARNI_D_Q = 1910
+LOONGARCH_INS_XVSRARNI_H_W = 1911
+LOONGARCH_INS_XVSRARNI_W_D = 1912
+LOONGARCH_INS_XVSRARN_B_H = 1913
+LOONGARCH_INS_XVSRARN_H_W = 1914
+LOONGARCH_INS_XVSRARN_W_D = 1915
+LOONGARCH_INS_XVSRAR_B = 1916
+LOONGARCH_INS_XVSRAR_D = 1917
+LOONGARCH_INS_XVSRAR_H = 1918
+LOONGARCH_INS_XVSRAR_W = 1919
+LOONGARCH_INS_XVSRA_B = 1920
+LOONGARCH_INS_XVSRA_D = 1921
+LOONGARCH_INS_XVSRA_H = 1922
+LOONGARCH_INS_XVSRA_W = 1923
+LOONGARCH_INS_XVSRLI_B = 1924
+LOONGARCH_INS_XVSRLI_D = 1925
+LOONGARCH_INS_XVSRLI_H = 1926
+LOONGARCH_INS_XVSRLI_W = 1927
+LOONGARCH_INS_XVSRLNI_B_H = 1928
+LOONGARCH_INS_XVSRLNI_D_Q = 1929
+LOONGARCH_INS_XVSRLNI_H_W = 1930
+LOONGARCH_INS_XVSRLNI_W_D = 1931
+LOONGARCH_INS_XVSRLN_B_H = 1932
+LOONGARCH_INS_XVSRLN_H_W = 1933
+LOONGARCH_INS_XVSRLN_W_D = 1934
+LOONGARCH_INS_XVSRLRI_B = 1935
+LOONGARCH_INS_XVSRLRI_D = 1936
+LOONGARCH_INS_XVSRLRI_H = 1937
+LOONGARCH_INS_XVSRLRI_W = 1938
+LOONGARCH_INS_XVSRLRNI_B_H = 1939
+LOONGARCH_INS_XVSRLRNI_D_Q = 1940
+LOONGARCH_INS_XVSRLRNI_H_W = 1941
+LOONGARCH_INS_XVSRLRNI_W_D = 1942
+LOONGARCH_INS_XVSRLRN_B_H = 1943
+LOONGARCH_INS_XVSRLRN_H_W = 1944
+LOONGARCH_INS_XVSRLRN_W_D = 1945
+LOONGARCH_INS_XVSRLR_B = 1946
+LOONGARCH_INS_XVSRLR_D = 1947
+LOONGARCH_INS_XVSRLR_H = 1948
+LOONGARCH_INS_XVSRLR_W = 1949
+LOONGARCH_INS_XVSRL_B = 1950
+LOONGARCH_INS_XVSRL_D = 1951
+LOONGARCH_INS_XVSRL_H = 1952
+LOONGARCH_INS_XVSRL_W = 1953
+LOONGARCH_INS_XVSSRANI_BU_H = 1954
+LOONGARCH_INS_XVSSRANI_B_H = 1955
+LOONGARCH_INS_XVSSRANI_DU_Q = 1956
+LOONGARCH_INS_XVSSRANI_D_Q = 1957
+LOONGARCH_INS_XVSSRANI_HU_W = 1958
+LOONGARCH_INS_XVSSRANI_H_W = 1959
+LOONGARCH_INS_XVSSRANI_WU_D = 1960
+LOONGARCH_INS_XVSSRANI_W_D = 1961
+LOONGARCH_INS_XVSSRAN_BU_H = 1962
+LOONGARCH_INS_XVSSRAN_B_H = 1963
+LOONGARCH_INS_XVSSRAN_HU_W = 1964
+LOONGARCH_INS_XVSSRAN_H_W = 1965
+LOONGARCH_INS_XVSSRAN_WU_D = 1966
+LOONGARCH_INS_XVSSRAN_W_D = 1967
+LOONGARCH_INS_XVSSRARNI_BU_H = 1968
+LOONGARCH_INS_XVSSRARNI_B_H = 1969
+LOONGARCH_INS_XVSSRARNI_DU_Q = 1970
+LOONGARCH_INS_XVSSRARNI_D_Q = 1971
+LOONGARCH_INS_XVSSRARNI_HU_W = 1972
+LOONGARCH_INS_XVSSRARNI_H_W = 1973
+LOONGARCH_INS_XVSSRARNI_WU_D = 1974
+LOONGARCH_INS_XVSSRARNI_W_D = 1975
+LOONGARCH_INS_XVSSRARN_BU_H = 1976
+LOONGARCH_INS_XVSSRARN_B_H = 1977
+LOONGARCH_INS_XVSSRARN_HU_W = 1978
+LOONGARCH_INS_XVSSRARN_H_W = 1979
+LOONGARCH_INS_XVSSRARN_WU_D = 1980
+LOONGARCH_INS_XVSSRARN_W_D = 1981
+LOONGARCH_INS_XVSSRLNI_BU_H = 1982
+LOONGARCH_INS_XVSSRLNI_B_H = 1983
+LOONGARCH_INS_XVSSRLNI_DU_Q = 1984
+LOONGARCH_INS_XVSSRLNI_D_Q = 1985
+LOONGARCH_INS_XVSSRLNI_HU_W = 1986
+LOONGARCH_INS_XVSSRLNI_H_W = 1987
+LOONGARCH_INS_XVSSRLNI_WU_D = 1988
+LOONGARCH_INS_XVSSRLNI_W_D = 1989
+LOONGARCH_INS_XVSSRLN_BU_H = 1990
+LOONGARCH_INS_XVSSRLN_B_H = 1991
+LOONGARCH_INS_XVSSRLN_HU_W = 1992
+LOONGARCH_INS_XVSSRLN_H_W = 1993
+LOONGARCH_INS_XVSSRLN_WU_D = 1994
+LOONGARCH_INS_XVSSRLN_W_D = 1995
+LOONGARCH_INS_XVSSRLRNI_BU_H = 1996
+LOONGARCH_INS_XVSSRLRNI_B_H = 1997
+LOONGARCH_INS_XVSSRLRNI_DU_Q = 1998
+LOONGARCH_INS_XVSSRLRNI_D_Q = 1999
+LOONGARCH_INS_XVSSRLRNI_HU_W = 2000
+LOONGARCH_INS_XVSSRLRNI_H_W = 2001
+LOONGARCH_INS_XVSSRLRNI_WU_D = 2002
+LOONGARCH_INS_XVSSRLRNI_W_D = 2003
+LOONGARCH_INS_XVSSRLRN_BU_H = 2004
+LOONGARCH_INS_XVSSRLRN_B_H = 2005
+LOONGARCH_INS_XVSSRLRN_HU_W = 2006
+LOONGARCH_INS_XVSSRLRN_H_W = 2007
+LOONGARCH_INS_XVSSRLRN_WU_D = 2008
+LOONGARCH_INS_XVSSRLRN_W_D = 2009
+LOONGARCH_INS_XVSSUB_B = 2010
+LOONGARCH_INS_XVSSUB_BU = 2011
+LOONGARCH_INS_XVSSUB_D = 2012
+LOONGARCH_INS_XVSSUB_DU = 2013
+LOONGARCH_INS_XVSSUB_H = 2014
+LOONGARCH_INS_XVSSUB_HU = 2015
+LOONGARCH_INS_XVSSUB_W = 2016
+LOONGARCH_INS_XVSSUB_WU = 2017
+LOONGARCH_INS_XVST = 2018
+LOONGARCH_INS_XVSTELM_B = 2019
+LOONGARCH_INS_XVSTELM_D = 2020
+LOONGARCH_INS_XVSTELM_H = 2021
+LOONGARCH_INS_XVSTELM_W = 2022
+LOONGARCH_INS_XVSTX = 2023
+LOONGARCH_INS_XVSUBI_BU = 2024
+LOONGARCH_INS_XVSUBI_DU = 2025
+LOONGARCH_INS_XVSUBI_HU = 2026
+LOONGARCH_INS_XVSUBI_WU = 2027
+LOONGARCH_INS_XVSUBWEV_D_W = 2028
+LOONGARCH_INS_XVSUBWEV_D_WU = 2029
+LOONGARCH_INS_XVSUBWEV_H_B = 2030
+LOONGARCH_INS_XVSUBWEV_H_BU = 2031
+LOONGARCH_INS_XVSUBWEV_Q_D = 2032
+LOONGARCH_INS_XVSUBWEV_Q_DU = 2033
+LOONGARCH_INS_XVSUBWEV_W_H = 2034
+LOONGARCH_INS_XVSUBWEV_W_HU = 2035
+LOONGARCH_INS_XVSUBWOD_D_W = 2036
+LOONGARCH_INS_XVSUBWOD_D_WU = 2037
+LOONGARCH_INS_XVSUBWOD_H_B = 2038
+LOONGARCH_INS_XVSUBWOD_H_BU = 2039
+LOONGARCH_INS_XVSUBWOD_Q_D = 2040
+LOONGARCH_INS_XVSUBWOD_Q_DU = 2041
+LOONGARCH_INS_XVSUBWOD_W_H = 2042
+LOONGARCH_INS_XVSUBWOD_W_HU = 2043
+LOONGARCH_INS_XVSUB_B = 2044
+LOONGARCH_INS_XVSUB_D = 2045
+LOONGARCH_INS_XVSUB_H = 2046
+LOONGARCH_INS_XVSUB_Q = 2047
+LOONGARCH_INS_XVSUB_W = 2048
+LOONGARCH_INS_XVXORI_B = 2049
+LOONGARCH_INS_XVXOR_V = 2050
+LOONGARCH_INS_ENDING = 2051
+
+# Group of LOONGARCH instructions
+
+LOONGARCH_GRP_INVALID = 0
+LOONGARCH_GRP_JUMP = 1
+LOONGARCH_GRP_CALL = 2
+LOONGARCH_GRP_RET = 3
+LOONGARCH_GRP_INT = 4
+LOONGARCH_GRP_IRET = 5
+LOONGARCH_GRP_PRIVILEGE = 6
+LOONGARCH_GRP_BRANCH_RELATIVE = 7
+LOONGARCH_FEATURE_ISLA64 = 128
+LOONGARCH_FEATURE_ISLA32 = 129
+LOONGARCH_FEATURE_HASLAGLOBALWITHPCREL = 130
+LOONGARCH_FEATURE_HASLAGLOBALWITHABS = 131
+LOONGARCH_FEATURE_HASLALOCALWITHABS = 132
+LOONGARCH_GRP_ENDING = 133
diff --git a/bindings/python/capstone/ppc.py b/bindings/python/capstone/ppc.py
index d73940809..b30a140c5 100644
--- a/bindings/python/capstone/ppc.py
+++ b/bindings/python/capstone/ppc.py
@@ -60,5 +60,5 @@ class CsPpc(ctypes.Structure):
     )
 
 def get_arch_info(a):
-    return (a.bc, a.update_cr0, copy_ctypes_list(a.operands[:a.op_count]))
+    return (a.bc, a.update_cr0, a.format, copy_ctypes_list(a.operands[:a.op_count]))
 
diff --git a/bindings/python/capstone/ppc_const.py b/bindings/python/capstone/ppc_const.py
index 71fb0671e..2feba7cc9 100644
--- a/bindings/python/capstone/ppc_const.py
+++ b/bindings/python/capstone/ppc_const.py
@@ -606,2337 +606,2338 @@ PPC_REG_G8p13 = 529
 PPC_REG_G8p14 = 530
 PPC_REG_G8p15 = 531
 PPC_REG_ENDING = 532
-PPC_INS_INVALID = 533
-PPC_INS_CLRLSLDI = 534
-PPC_INS_CLRLSLWI = 535
-PPC_INS_CLRRDI = 536
-PPC_INS_CLRRWI = 537
-PPC_INS_DCBFL = 538
-PPC_INS_DCBFLP = 539
-PPC_INS_DCBFPS = 540
-PPC_INS_DCBF = 541
-PPC_INS_DCBSTPS = 542
-PPC_INS_DCBTCT = 543
-PPC_INS_DCBTDS = 544
-PPC_INS_DCBTSTCT = 545
-PPC_INS_DCBTSTDS = 546
-PPC_INS_DCBTSTT = 547
-PPC_INS_DCBTST = 548
-PPC_INS_DCBTT = 549
-PPC_INS_DCBT = 550
-PPC_INS_EXTLDI = 551
-PPC_INS_EXTLWI = 552
-PPC_INS_EXTRDI = 553
-PPC_INS_EXTRWI = 554
-PPC_INS_INSLWI = 555
-PPC_INS_INSRDI = 556
-PPC_INS_INSRWI = 557
-PPC_INS_LA = 558
-PPC_INS_RLWIMI = 559
-PPC_INS_RLWINM = 560
-PPC_INS_RLWNM = 561
-PPC_INS_ROTRDI = 562
-PPC_INS_ROTRWI = 563
-PPC_INS_SLDI = 564
-PPC_INS_SLWI = 565
-PPC_INS_SRDI = 566
-PPC_INS_SRWI = 567
-PPC_INS_SUBI = 568
-PPC_INS_SUBIC = 569
-PPC_INS_SUBIS = 570
-PPC_INS_SUBPCIS = 571
-PPC_INS_ADD = 572
-PPC_INS_ADDO = 573
-PPC_INS_ADDC = 574
-PPC_INS_ADDCO = 575
-PPC_INS_ADDE = 576
-PPC_INS_ADDEO = 577
-PPC_INS_ADDEX = 578
-PPC_INS_ADDI = 579
-PPC_INS_ADDIC = 580
-PPC_INS_ADDIS = 581
-PPC_INS_ADDME = 582
-PPC_INS_ADDMEO = 583
-PPC_INS_ADDPCIS = 584
-PPC_INS_ADDZE = 585
-PPC_INS_ADDZEO = 586
-PPC_INS_AND = 587
-PPC_INS_ANDC = 588
-PPC_INS_ANDIS = 589
-PPC_INS_ANDI = 590
-PPC_INS_ATTN = 591
-PPC_INS_B = 592
-PPC_INS_BA = 593
-PPC_INS_BCDADD = 594
-PPC_INS_BCDCFN = 595
-PPC_INS_BCDCFSQ = 596
-PPC_INS_BCDCFZ = 597
-PPC_INS_BCDCPSGN = 598
-PPC_INS_BCDCTN = 599
-PPC_INS_BCDCTSQ = 600
-PPC_INS_BCDCTZ = 601
-PPC_INS_BCDSETSGN = 602
-PPC_INS_BCDSR = 603
-PPC_INS_BCDSUB = 604
-PPC_INS_BCDS = 605
-PPC_INS_BCDTRUNC = 606
-PPC_INS_BCDUS = 607
-PPC_INS_BCDUTRUNC = 608
-PPC_INS_BCTR = 609
-PPC_INS_BCTRL = 610
-PPC_INS_BL = 611
-PPC_INS_BLA = 612
-PPC_INS_BLR = 613
-PPC_INS_BLRL = 614
-PPC_INS_BPERMD = 615
-PPC_INS_BRD = 616
-PPC_INS_BRH = 617
-PPC_INS_BRINC = 618
-PPC_INS_BRW = 619
-PPC_INS_CFUGED = 620
-PPC_INS_CLRBHRB = 621
-PPC_INS_CMPB = 622
-PPC_INS_CMPD = 623
-PPC_INS_CMPDI = 624
-PPC_INS_CMPEQB = 625
-PPC_INS_CMPLD = 626
-PPC_INS_CMPLDI = 627
-PPC_INS_CMPLW = 628
-PPC_INS_CMPLWI = 629
-PPC_INS_CMPRB = 630
-PPC_INS_CMPW = 631
-PPC_INS_CMPWI = 632
-PPC_INS_CNTLZD = 633
-PPC_INS_CNTLZDM = 634
-PPC_INS_CNTLZW = 635
-PPC_INS_CNTTZD = 636
-PPC_INS_CNTTZDM = 637
-PPC_INS_CNTTZW = 638
-PPC_INS_CPABORT = 639
-PPC_INS_COPY = 640
-PPC_INS_PASTE = 641
-PPC_INS_CRAND = 642
-PPC_INS_CRANDC = 643
-PPC_INS_CREQV = 644
-PPC_INS_CRNAND = 645
-PPC_INS_CRNOR = 646
-PPC_INS_CROR = 647
-PPC_INS_CRORC = 648
-PPC_INS_CRXOR = 649
-PPC_INS_DARN = 650
-PPC_INS_DCBA = 651
-PPC_INS_DCBFEP = 652
-PPC_INS_DCBI = 653
-PPC_INS_DCBST = 654
-PPC_INS_DCBSTEP = 655
-PPC_INS_DCBTEP = 656
-PPC_INS_DCBTSTEP = 657
-PPC_INS_DCBZ = 658
-PPC_INS_DCBZEP = 659
-PPC_INS_DCBZL = 660
-PPC_INS_DCBZLEP = 661
-PPC_INS_DCCCI = 662
-PPC_INS_DIVD = 663
-PPC_INS_DIVDE = 664
-PPC_INS_DIVDEO = 665
-PPC_INS_DIVDEU = 666
-PPC_INS_DIVDEUO = 667
-PPC_INS_DIVDO = 668
-PPC_INS_DIVDU = 669
-PPC_INS_DIVDUO = 670
-PPC_INS_DIVW = 671
-PPC_INS_DIVWE = 672
-PPC_INS_DIVWEO = 673
-PPC_INS_DIVWEU = 674
-PPC_INS_DIVWEUO = 675
-PPC_INS_DIVWO = 676
-PPC_INS_DIVWU = 677
-PPC_INS_DIVWUO = 678
-PPC_INS_DMMR = 679
-PPC_INS_DMSETDMRZ = 680
-PPC_INS_DMXOR = 681
-PPC_INS_DMXXEXTFDMR256 = 682
-PPC_INS_DMXXEXTFDMR512 = 683
-PPC_INS_DMXXINSTFDMR256 = 684
-PPC_INS_DMXXINSTFDMR512 = 685
-PPC_INS_DSS = 686
-PPC_INS_DSSALL = 687
-PPC_INS_DST = 688
-PPC_INS_DSTST = 689
-PPC_INS_DSTSTT = 690
-PPC_INS_DSTT = 691
-PPC_INS_EFDABS = 692
-PPC_INS_EFDADD = 693
-PPC_INS_EFDCFS = 694
-PPC_INS_EFDCFSF = 695
-PPC_INS_EFDCFSI = 696
-PPC_INS_EFDCFSID = 697
-PPC_INS_EFDCFUF = 698
-PPC_INS_EFDCFUI = 699
-PPC_INS_EFDCFUID = 700
-PPC_INS_EFDCMPEQ = 701
-PPC_INS_EFDCMPGT = 702
-PPC_INS_EFDCMPLT = 703
-PPC_INS_EFDCTSF = 704
-PPC_INS_EFDCTSI = 705
-PPC_INS_EFDCTSIDZ = 706
-PPC_INS_EFDCTSIZ = 707
-PPC_INS_EFDCTUF = 708
-PPC_INS_EFDCTUI = 709
-PPC_INS_EFDCTUIDZ = 710
-PPC_INS_EFDCTUIZ = 711
-PPC_INS_EFDDIV = 712
-PPC_INS_EFDMUL = 713
-PPC_INS_EFDNABS = 714
-PPC_INS_EFDNEG = 715
-PPC_INS_EFDSUB = 716
-PPC_INS_EFDTSTEQ = 717
-PPC_INS_EFDTSTGT = 718
-PPC_INS_EFDTSTLT = 719
-PPC_INS_EFSABS = 720
-PPC_INS_EFSADD = 721
-PPC_INS_EFSCFD = 722
-PPC_INS_EFSCFSF = 723
-PPC_INS_EFSCFSI = 724
-PPC_INS_EFSCFUF = 725
-PPC_INS_EFSCFUI = 726
-PPC_INS_EFSCMPEQ = 727
-PPC_INS_EFSCMPGT = 728
-PPC_INS_EFSCMPLT = 729
-PPC_INS_EFSCTSF = 730
-PPC_INS_EFSCTSI = 731
-PPC_INS_EFSCTSIZ = 732
-PPC_INS_EFSCTUF = 733
-PPC_INS_EFSCTUI = 734
-PPC_INS_EFSCTUIZ = 735
-PPC_INS_EFSDIV = 736
-PPC_INS_EFSMUL = 737
-PPC_INS_EFSNABS = 738
-PPC_INS_EFSNEG = 739
-PPC_INS_EFSSUB = 740
-PPC_INS_EFSTSTEQ = 741
-PPC_INS_EFSTSTGT = 742
-PPC_INS_EFSTSTLT = 743
-PPC_INS_EQV = 744
-PPC_INS_EVABS = 745
-PPC_INS_EVADDIW = 746
-PPC_INS_EVADDSMIAAW = 747
-PPC_INS_EVADDSSIAAW = 748
-PPC_INS_EVADDUMIAAW = 749
-PPC_INS_EVADDUSIAAW = 750
-PPC_INS_EVADDW = 751
-PPC_INS_EVAND = 752
-PPC_INS_EVANDC = 753
-PPC_INS_EVCMPEQ = 754
-PPC_INS_EVCMPGTS = 755
-PPC_INS_EVCMPGTU = 756
-PPC_INS_EVCMPLTS = 757
-PPC_INS_EVCMPLTU = 758
-PPC_INS_EVCNTLSW = 759
-PPC_INS_EVCNTLZW = 760
-PPC_INS_EVDIVWS = 761
-PPC_INS_EVDIVWU = 762
-PPC_INS_EVEQV = 763
-PPC_INS_EVEXTSB = 764
-PPC_INS_EVEXTSH = 765
-PPC_INS_EVFSABS = 766
-PPC_INS_EVFSADD = 767
-PPC_INS_EVFSCFSF = 768
-PPC_INS_EVFSCFSI = 769
-PPC_INS_EVFSCFUF = 770
-PPC_INS_EVFSCFUI = 771
-PPC_INS_EVFSCMPEQ = 772
-PPC_INS_EVFSCMPGT = 773
-PPC_INS_EVFSCMPLT = 774
-PPC_INS_EVFSCTSF = 775
-PPC_INS_EVFSCTSI = 776
-PPC_INS_EVFSCTSIZ = 777
-PPC_INS_EVFSCTUI = 778
-PPC_INS_EVFSDIV = 779
-PPC_INS_EVFSMUL = 780
-PPC_INS_EVFSNABS = 781
-PPC_INS_EVFSNEG = 782
-PPC_INS_EVFSSUB = 783
-PPC_INS_EVFSTSTEQ = 784
-PPC_INS_EVFSTSTGT = 785
-PPC_INS_EVFSTSTLT = 786
-PPC_INS_EVLDD = 787
-PPC_INS_EVLDDX = 788
-PPC_INS_EVLDH = 789
-PPC_INS_EVLDHX = 790
-PPC_INS_EVLDW = 791
-PPC_INS_EVLDWX = 792
-PPC_INS_EVLHHESPLAT = 793
-PPC_INS_EVLHHESPLATX = 794
-PPC_INS_EVLHHOSSPLAT = 795
-PPC_INS_EVLHHOSSPLATX = 796
-PPC_INS_EVLHHOUSPLAT = 797
-PPC_INS_EVLHHOUSPLATX = 798
-PPC_INS_EVLWHE = 799
-PPC_INS_EVLWHEX = 800
-PPC_INS_EVLWHOS = 801
-PPC_INS_EVLWHOSX = 802
-PPC_INS_EVLWHOU = 803
-PPC_INS_EVLWHOUX = 804
-PPC_INS_EVLWHSPLAT = 805
-PPC_INS_EVLWHSPLATX = 806
-PPC_INS_EVLWWSPLAT = 807
-PPC_INS_EVLWWSPLATX = 808
-PPC_INS_EVMERGEHI = 809
-PPC_INS_EVMERGEHILO = 810
-PPC_INS_EVMERGELO = 811
-PPC_INS_EVMERGELOHI = 812
-PPC_INS_EVMHEGSMFAA = 813
-PPC_INS_EVMHEGSMFAN = 814
-PPC_INS_EVMHEGSMIAA = 815
-PPC_INS_EVMHEGSMIAN = 816
-PPC_INS_EVMHEGUMIAA = 817
-PPC_INS_EVMHEGUMIAN = 818
-PPC_INS_EVMHESMF = 819
-PPC_INS_EVMHESMFA = 820
-PPC_INS_EVMHESMFAAW = 821
-PPC_INS_EVMHESMFANW = 822
-PPC_INS_EVMHESMI = 823
-PPC_INS_EVMHESMIA = 824
-PPC_INS_EVMHESMIAAW = 825
-PPC_INS_EVMHESMIANW = 826
-PPC_INS_EVMHESSF = 827
-PPC_INS_EVMHESSFA = 828
-PPC_INS_EVMHESSFAAW = 829
-PPC_INS_EVMHESSFANW = 830
-PPC_INS_EVMHESSIAAW = 831
-PPC_INS_EVMHESSIANW = 832
-PPC_INS_EVMHEUMI = 833
-PPC_INS_EVMHEUMIA = 834
-PPC_INS_EVMHEUMIAAW = 835
-PPC_INS_EVMHEUMIANW = 836
-PPC_INS_EVMHEUSIAAW = 837
-PPC_INS_EVMHEUSIANW = 838
-PPC_INS_EVMHOGSMFAA = 839
-PPC_INS_EVMHOGSMFAN = 840
-PPC_INS_EVMHOGSMIAA = 841
-PPC_INS_EVMHOGSMIAN = 842
-PPC_INS_EVMHOGUMIAA = 843
-PPC_INS_EVMHOGUMIAN = 844
-PPC_INS_EVMHOSMF = 845
-PPC_INS_EVMHOSMFA = 846
-PPC_INS_EVMHOSMFAAW = 847
-PPC_INS_EVMHOSMFANW = 848
-PPC_INS_EVMHOSMI = 849
-PPC_INS_EVMHOSMIA = 850
-PPC_INS_EVMHOSMIAAW = 851
-PPC_INS_EVMHOSMIANW = 852
-PPC_INS_EVMHOSSF = 853
-PPC_INS_EVMHOSSFA = 854
-PPC_INS_EVMHOSSFAAW = 855
-PPC_INS_EVMHOSSFANW = 856
-PPC_INS_EVMHOSSIAAW = 857
-PPC_INS_EVMHOSSIANW = 858
-PPC_INS_EVMHOUMI = 859
-PPC_INS_EVMHOUMIA = 860
-PPC_INS_EVMHOUMIAAW = 861
-PPC_INS_EVMHOUMIANW = 862
-PPC_INS_EVMHOUSIAAW = 863
-PPC_INS_EVMHOUSIANW = 864
-PPC_INS_EVMRA = 865
-PPC_INS_EVMWHSMF = 866
-PPC_INS_EVMWHSMFA = 867
-PPC_INS_EVMWHSMI = 868
-PPC_INS_EVMWHSMIA = 869
-PPC_INS_EVMWHSSF = 870
-PPC_INS_EVMWHSSFA = 871
-PPC_INS_EVMWHUMI = 872
-PPC_INS_EVMWHUMIA = 873
-PPC_INS_EVMWLSMIAAW = 874
-PPC_INS_EVMWLSMIANW = 875
-PPC_INS_EVMWLSSIAAW = 876
-PPC_INS_EVMWLSSIANW = 877
-PPC_INS_EVMWLUMI = 878
-PPC_INS_EVMWLUMIA = 879
-PPC_INS_EVMWLUMIAAW = 880
-PPC_INS_EVMWLUMIANW = 881
-PPC_INS_EVMWLUSIAAW = 882
-PPC_INS_EVMWLUSIANW = 883
-PPC_INS_EVMWSMF = 884
-PPC_INS_EVMWSMFA = 885
-PPC_INS_EVMWSMFAA = 886
-PPC_INS_EVMWSMFAN = 887
-PPC_INS_EVMWSMI = 888
-PPC_INS_EVMWSMIA = 889
-PPC_INS_EVMWSMIAA = 890
-PPC_INS_EVMWSMIAN = 891
-PPC_INS_EVMWSSF = 892
-PPC_INS_EVMWSSFA = 893
-PPC_INS_EVMWSSFAA = 894
-PPC_INS_EVMWSSFAN = 895
-PPC_INS_EVMWUMI = 896
-PPC_INS_EVMWUMIA = 897
-PPC_INS_EVMWUMIAA = 898
-PPC_INS_EVMWUMIAN = 899
-PPC_INS_EVNAND = 900
-PPC_INS_EVNEG = 901
-PPC_INS_EVNOR = 902
-PPC_INS_EVOR = 903
-PPC_INS_EVORC = 904
-PPC_INS_EVRLW = 905
-PPC_INS_EVRLWI = 906
-PPC_INS_EVRNDW = 907
-PPC_INS_EVSEL = 908
-PPC_INS_EVSLW = 909
-PPC_INS_EVSLWI = 910
-PPC_INS_EVSPLATFI = 911
-PPC_INS_EVSPLATI = 912
-PPC_INS_EVSRWIS = 913
-PPC_INS_EVSRWIU = 914
-PPC_INS_EVSRWS = 915
-PPC_INS_EVSRWU = 916
-PPC_INS_EVSTDD = 917
-PPC_INS_EVSTDDX = 918
-PPC_INS_EVSTDH = 919
-PPC_INS_EVSTDHX = 920
-PPC_INS_EVSTDW = 921
-PPC_INS_EVSTDWX = 922
-PPC_INS_EVSTWHE = 923
-PPC_INS_EVSTWHEX = 924
-PPC_INS_EVSTWHO = 925
-PPC_INS_EVSTWHOX = 926
-PPC_INS_EVSTWWE = 927
-PPC_INS_EVSTWWEX = 928
-PPC_INS_EVSTWWO = 929
-PPC_INS_EVSTWWOX = 930
-PPC_INS_EVSUBFSMIAAW = 931
-PPC_INS_EVSUBFSSIAAW = 932
-PPC_INS_EVSUBFUMIAAW = 933
-PPC_INS_EVSUBFUSIAAW = 934
-PPC_INS_EVSUBFW = 935
-PPC_INS_EVSUBIFW = 936
-PPC_INS_EVXOR = 937
-PPC_INS_EXTSB = 938
-PPC_INS_EXTSH = 939
-PPC_INS_EXTSW = 940
-PPC_INS_EXTSWSLI = 941
-PPC_INS_EIEIO = 942
-PPC_INS_FABS = 943
-PPC_INS_FADD = 944
-PPC_INS_FADDS = 945
-PPC_INS_FCFID = 946
-PPC_INS_FCFIDS = 947
-PPC_INS_FCFIDU = 948
-PPC_INS_FCFIDUS = 949
-PPC_INS_FCMPO = 950
-PPC_INS_FCMPU = 951
-PPC_INS_FCPSGN = 952
-PPC_INS_FCTID = 953
-PPC_INS_FCTIDU = 954
-PPC_INS_FCTIDUZ = 955
-PPC_INS_FCTIDZ = 956
-PPC_INS_FCTIW = 957
-PPC_INS_FCTIWU = 958
-PPC_INS_FCTIWUZ = 959
-PPC_INS_FCTIWZ = 960
-PPC_INS_FDIV = 961
-PPC_INS_FDIVS = 962
-PPC_INS_FMADD = 963
-PPC_INS_FMADDS = 964
-PPC_INS_FMR = 965
-PPC_INS_FMSUB = 966
-PPC_INS_FMSUBS = 967
-PPC_INS_FMUL = 968
-PPC_INS_FMULS = 969
-PPC_INS_FNABS = 970
-PPC_INS_FNEG = 971
-PPC_INS_FNMADD = 972
-PPC_INS_FNMADDS = 973
-PPC_INS_FNMSUB = 974
-PPC_INS_FNMSUBS = 975
-PPC_INS_FRE = 976
-PPC_INS_FRES = 977
-PPC_INS_FRIM = 978
-PPC_INS_FRIN = 979
-PPC_INS_FRIP = 980
-PPC_INS_FRIZ = 981
-PPC_INS_FRSP = 982
-PPC_INS_FRSQRTE = 983
-PPC_INS_FRSQRTES = 984
-PPC_INS_FSEL = 985
-PPC_INS_FSQRT = 986
-PPC_INS_FSQRTS = 987
-PPC_INS_FSUB = 988
-PPC_INS_FSUBS = 989
-PPC_INS_FTDIV = 990
-PPC_INS_FTSQRT = 991
-PPC_INS_HASHCHK = 992
-PPC_INS_HASHCHKP = 993
-PPC_INS_HASHST = 994
-PPC_INS_HASHSTP = 995
-PPC_INS_HRFID = 996
-PPC_INS_ICBI = 997
-PPC_INS_ICBIEP = 998
-PPC_INS_ICBLC = 999
-PPC_INS_ICBLQ = 1000
-PPC_INS_ICBT = 1001
-PPC_INS_ICBTLS = 1002
-PPC_INS_ICCCI = 1003
-PPC_INS_ISEL = 1004
-PPC_INS_ISYNC = 1005
-PPC_INS_LBARX = 1006
-PPC_INS_LBEPX = 1007
-PPC_INS_LBZ = 1008
-PPC_INS_LBZCIX = 1009
-PPC_INS_LBZU = 1010
-PPC_INS_LBZUX = 1011
-PPC_INS_LBZX = 1012
-PPC_INS_LD = 1013
-PPC_INS_LDARX = 1014
-PPC_INS_LDAT = 1015
-PPC_INS_LDBRX = 1016
-PPC_INS_LDCIX = 1017
-PPC_INS_LDU = 1018
-PPC_INS_LDUX = 1019
-PPC_INS_LDX = 1020
-PPC_INS_LFD = 1021
-PPC_INS_LFDEPX = 1022
-PPC_INS_LFDU = 1023
-PPC_INS_LFDUX = 1024
-PPC_INS_LFDX = 1025
-PPC_INS_LFIWAX = 1026
-PPC_INS_LFIWZX = 1027
-PPC_INS_LFS = 1028
-PPC_INS_LFSU = 1029
-PPC_INS_LFSUX = 1030
-PPC_INS_LFSX = 1031
-PPC_INS_LHA = 1032
-PPC_INS_LHARX = 1033
-PPC_INS_LHAU = 1034
-PPC_INS_LHAUX = 1035
-PPC_INS_LHAX = 1036
-PPC_INS_LHBRX = 1037
-PPC_INS_LHEPX = 1038
-PPC_INS_LHZ = 1039
-PPC_INS_LHZCIX = 1040
-PPC_INS_LHZU = 1041
-PPC_INS_LHZUX = 1042
-PPC_INS_LHZX = 1043
-PPC_INS_LMW = 1044
-PPC_INS_LQ = 1045
-PPC_INS_LQARX = 1046
-PPC_INS_LSWI = 1047
-PPC_INS_LVEBX = 1048
-PPC_INS_LVEHX = 1049
-PPC_INS_LVEWX = 1050
-PPC_INS_LVSL = 1051
-PPC_INS_LVSR = 1052
-PPC_INS_LVX = 1053
-PPC_INS_LVXL = 1054
-PPC_INS_LWA = 1055
-PPC_INS_LWARX = 1056
-PPC_INS_LWAT = 1057
-PPC_INS_LWAUX = 1058
-PPC_INS_LWAX = 1059
-PPC_INS_LWBRX = 1060
-PPC_INS_LWEPX = 1061
-PPC_INS_LWZ = 1062
-PPC_INS_LWZCIX = 1063
-PPC_INS_LWZU = 1064
-PPC_INS_LWZUX = 1065
-PPC_INS_LWZX = 1066
-PPC_INS_LXSD = 1067
-PPC_INS_LXSDX = 1068
-PPC_INS_LXSIBZX = 1069
-PPC_INS_LXSIHZX = 1070
-PPC_INS_LXSIWAX = 1071
-PPC_INS_LXSIWZX = 1072
-PPC_INS_LXSSP = 1073
-PPC_INS_LXSSPX = 1074
-PPC_INS_LXV = 1075
-PPC_INS_LXVB16X = 1076
-PPC_INS_LXVD2X = 1077
-PPC_INS_LXVDSX = 1078
-PPC_INS_LXVH8X = 1079
-PPC_INS_LXVKQ = 1080
-PPC_INS_LXVL = 1081
-PPC_INS_LXVLL = 1082
-PPC_INS_LXVP = 1083
-PPC_INS_LXVPRL = 1084
-PPC_INS_LXVPRLL = 1085
-PPC_INS_LXVPX = 1086
-PPC_INS_LXVRBX = 1087
-PPC_INS_LXVRDX = 1088
-PPC_INS_LXVRHX = 1089
-PPC_INS_LXVRL = 1090
-PPC_INS_LXVRLL = 1091
-PPC_INS_LXVRWX = 1092
-PPC_INS_LXVW4X = 1093
-PPC_INS_LXVWSX = 1094
-PPC_INS_LXVX = 1095
-PPC_INS_MADDHD = 1096
-PPC_INS_MADDHDU = 1097
-PPC_INS_MADDLD = 1098
-PPC_INS_MBAR = 1099
-PPC_INS_MCRF = 1100
-PPC_INS_MCRFS = 1101
-PPC_INS_MCRXRX = 1102
-PPC_INS_MFBHRBE = 1103
-PPC_INS_MFCR = 1104
-PPC_INS_MFCTR = 1105
-PPC_INS_MFDCR = 1106
-PPC_INS_MFFS = 1107
-PPC_INS_MFFSCDRN = 1108
-PPC_INS_MFFSCDRNI = 1109
-PPC_INS_MFFSCE = 1110
-PPC_INS_MFFSCRN = 1111
-PPC_INS_MFFSCRNI = 1112
-PPC_INS_MFFSL = 1113
-PPC_INS_MFLR = 1114
-PPC_INS_MFMSR = 1115
-PPC_INS_MFOCRF = 1116
-PPC_INS_MFPMR = 1117
-PPC_INS_MFSPR = 1118
-PPC_INS_MFSR = 1119
-PPC_INS_MFSRIN = 1120
-PPC_INS_MFTB = 1121
-PPC_INS_MFVSCR = 1122
-PPC_INS_MFVSRD = 1123
-PPC_INS_MFVSRLD = 1124
-PPC_INS_MFVSRWZ = 1125
-PPC_INS_MODSD = 1126
-PPC_INS_MODSW = 1127
-PPC_INS_MODUD = 1128
-PPC_INS_MODUW = 1129
-PPC_INS_MSGSYNC = 1130
-PPC_INS_MTCRF = 1131
-PPC_INS_MTCTR = 1132
-PPC_INS_MTDCR = 1133
-PPC_INS_MTFSB0 = 1134
-PPC_INS_MTFSB1 = 1135
-PPC_INS_MTFSF = 1136
-PPC_INS_MTFSFI = 1137
-PPC_INS_MTLR = 1138
-PPC_INS_MTMSR = 1139
-PPC_INS_MTMSRD = 1140
-PPC_INS_MTOCRF = 1141
-PPC_INS_MTPMR = 1142
-PPC_INS_MTSPR = 1143
-PPC_INS_MTSR = 1144
-PPC_INS_MTSRIN = 1145
-PPC_INS_MTVSCR = 1146
-PPC_INS_MTVSRBM = 1147
-PPC_INS_MTVSRBMI = 1148
-PPC_INS_MTVSRD = 1149
-PPC_INS_MTVSRDD = 1150
-PPC_INS_MTVSRDM = 1151
-PPC_INS_MTVSRHM = 1152
-PPC_INS_MTVSRQM = 1153
-PPC_INS_MTVSRWA = 1154
-PPC_INS_MTVSRWM = 1155
-PPC_INS_MTVSRWS = 1156
-PPC_INS_MTVSRWZ = 1157
-PPC_INS_MULHD = 1158
-PPC_INS_MULHDU = 1159
-PPC_INS_MULHW = 1160
-PPC_INS_MULHWU = 1161
-PPC_INS_MULLD = 1162
-PPC_INS_MULLDO = 1163
-PPC_INS_MULLI = 1164
-PPC_INS_MULLW = 1165
-PPC_INS_MULLWO = 1166
-PPC_INS_NAND = 1167
-PPC_INS_NAP = 1168
-PPC_INS_NEG = 1169
-PPC_INS_NEGO = 1170
-PPC_INS_NOP = 1171
-PPC_INS_NOR = 1172
-PPC_INS_OR = 1173
-PPC_INS_ORC = 1174
-PPC_INS_ORI = 1175
-PPC_INS_ORIS = 1176
-PPC_INS_PADDI = 1177
-PPC_INS_PDEPD = 1178
-PPC_INS_PEXTD = 1179
-PPC_INS_PLBZ = 1180
-PPC_INS_PLD = 1181
-PPC_INS_PLFD = 1182
-PPC_INS_PLFS = 1183
-PPC_INS_PLHA = 1184
-PPC_INS_PLHZ = 1185
-PPC_INS_PLI = 1186
-PPC_INS_PLWA = 1187
-PPC_INS_PLWZ = 1188
-PPC_INS_PLXSD = 1189
-PPC_INS_PLXSSP = 1190
-PPC_INS_PLXV = 1191
-PPC_INS_PLXVP = 1192
-PPC_INS_PMXVBF16GER2 = 1193
-PPC_INS_PMXVBF16GER2NN = 1194
-PPC_INS_PMXVBF16GER2NP = 1195
-PPC_INS_PMXVBF16GER2PN = 1196
-PPC_INS_PMXVBF16GER2PP = 1197
-PPC_INS_PMXVF16GER2 = 1198
-PPC_INS_PMXVF16GER2NN = 1199
-PPC_INS_PMXVF16GER2NP = 1200
-PPC_INS_PMXVF16GER2PN = 1201
-PPC_INS_PMXVF16GER2PP = 1202
-PPC_INS_PMXVF32GER = 1203
-PPC_INS_PMXVF32GERNN = 1204
-PPC_INS_PMXVF32GERNP = 1205
-PPC_INS_PMXVF32GERPN = 1206
-PPC_INS_PMXVF32GERPP = 1207
-PPC_INS_PMXVF64GER = 1208
-PPC_INS_PMXVF64GERNN = 1209
-PPC_INS_PMXVF64GERNP = 1210
-PPC_INS_PMXVF64GERPN = 1211
-PPC_INS_PMXVF64GERPP = 1212
-PPC_INS_PMXVI16GER2 = 1213
-PPC_INS_PMXVI16GER2PP = 1214
-PPC_INS_PMXVI16GER2S = 1215
-PPC_INS_PMXVI16GER2SPP = 1216
-PPC_INS_PMXVI4GER8 = 1217
-PPC_INS_PMXVI4GER8PP = 1218
-PPC_INS_PMXVI8GER4 = 1219
-PPC_INS_PMXVI8GER4PP = 1220
-PPC_INS_PMXVI8GER4SPP = 1221
-PPC_INS_POPCNTB = 1222
-PPC_INS_POPCNTD = 1223
-PPC_INS_POPCNTW = 1224
-PPC_INS_DCBZ_L = 1225
-PPC_INS_PSQ_L = 1226
-PPC_INS_PSQ_LU = 1227
-PPC_INS_PSQ_LUX = 1228
-PPC_INS_PSQ_LX = 1229
-PPC_INS_PSQ_ST = 1230
-PPC_INS_PSQ_STU = 1231
-PPC_INS_PSQ_STUX = 1232
-PPC_INS_PSQ_STX = 1233
-PPC_INS_PSTB = 1234
-PPC_INS_PSTD = 1235
-PPC_INS_PSTFD = 1236
-PPC_INS_PSTFS = 1237
-PPC_INS_PSTH = 1238
-PPC_INS_PSTW = 1239
-PPC_INS_PSTXSD = 1240
-PPC_INS_PSTXSSP = 1241
-PPC_INS_PSTXV = 1242
-PPC_INS_PSTXVP = 1243
-PPC_INS_PS_ABS = 1244
-PPC_INS_PS_ADD = 1245
-PPC_INS_PS_CMPO0 = 1246
-PPC_INS_PS_CMPO1 = 1247
-PPC_INS_PS_CMPU0 = 1248
-PPC_INS_PS_CMPU1 = 1249
-PPC_INS_PS_DIV = 1250
-PPC_INS_PS_MADD = 1251
-PPC_INS_PS_MADDS0 = 1252
-PPC_INS_PS_MADDS1 = 1253
-PPC_INS_PS_MERGE00 = 1254
-PPC_INS_PS_MERGE01 = 1255
-PPC_INS_PS_MERGE10 = 1256
-PPC_INS_PS_MERGE11 = 1257
-PPC_INS_PS_MR = 1258
-PPC_INS_PS_MSUB = 1259
-PPC_INS_PS_MUL = 1260
-PPC_INS_PS_MULS0 = 1261
-PPC_INS_PS_MULS1 = 1262
-PPC_INS_PS_NABS = 1263
-PPC_INS_PS_NEG = 1264
-PPC_INS_PS_NMADD = 1265
-PPC_INS_PS_NMSUB = 1266
-PPC_INS_PS_RES = 1267
-PPC_INS_PS_RSQRTE = 1268
-PPC_INS_PS_SEL = 1269
-PPC_INS_PS_SUB = 1270
-PPC_INS_PS_SUM0 = 1271
-PPC_INS_PS_SUM1 = 1272
-PPC_INS_QVALIGNI = 1273
-PPC_INS_QVESPLATI = 1274
-PPC_INS_QVFABS = 1275
-PPC_INS_QVFADD = 1276
-PPC_INS_QVFADDS = 1277
-PPC_INS_QVFCFID = 1278
-PPC_INS_QVFCFIDS = 1279
-PPC_INS_QVFCFIDU = 1280
-PPC_INS_QVFCFIDUS = 1281
-PPC_INS_QVFCMPEQ = 1282
-PPC_INS_QVFCMPGT = 1283
-PPC_INS_QVFCMPLT = 1284
-PPC_INS_QVFCPSGN = 1285
-PPC_INS_QVFCTID = 1286
-PPC_INS_QVFCTIDU = 1287
-PPC_INS_QVFCTIDUZ = 1288
-PPC_INS_QVFCTIDZ = 1289
-PPC_INS_QVFCTIW = 1290
-PPC_INS_QVFCTIWU = 1291
-PPC_INS_QVFCTIWUZ = 1292
-PPC_INS_QVFCTIWZ = 1293
-PPC_INS_QVFLOGICAL = 1294
-PPC_INS_QVFMADD = 1295
-PPC_INS_QVFMADDS = 1296
-PPC_INS_QVFMR = 1297
-PPC_INS_QVFMSUB = 1298
-PPC_INS_QVFMSUBS = 1299
-PPC_INS_QVFMUL = 1300
-PPC_INS_QVFMULS = 1301
-PPC_INS_QVFNABS = 1302
-PPC_INS_QVFNEG = 1303
-PPC_INS_QVFNMADD = 1304
-PPC_INS_QVFNMADDS = 1305
-PPC_INS_QVFNMSUB = 1306
-PPC_INS_QVFNMSUBS = 1307
-PPC_INS_QVFPERM = 1308
-PPC_INS_QVFRE = 1309
-PPC_INS_QVFRES = 1310
-PPC_INS_QVFRIM = 1311
-PPC_INS_QVFRIN = 1312
-PPC_INS_QVFRIP = 1313
-PPC_INS_QVFRIZ = 1314
-PPC_INS_QVFRSP = 1315
-PPC_INS_QVFRSQRTE = 1316
-PPC_INS_QVFRSQRTES = 1317
-PPC_INS_QVFSEL = 1318
-PPC_INS_QVFSUB = 1319
-PPC_INS_QVFSUBS = 1320
-PPC_INS_QVFTSTNAN = 1321
-PPC_INS_QVFXMADD = 1322
-PPC_INS_QVFXMADDS = 1323
-PPC_INS_QVFXMUL = 1324
-PPC_INS_QVFXMULS = 1325
-PPC_INS_QVFXXCPNMADD = 1326
-PPC_INS_QVFXXCPNMADDS = 1327
-PPC_INS_QVFXXMADD = 1328
-PPC_INS_QVFXXMADDS = 1329
-PPC_INS_QVFXXNPMADD = 1330
-PPC_INS_QVFXXNPMADDS = 1331
-PPC_INS_QVGPCI = 1332
-PPC_INS_QVLFCDUX = 1333
-PPC_INS_QVLFCDUXA = 1334
-PPC_INS_QVLFCDX = 1335
-PPC_INS_QVLFCDXA = 1336
-PPC_INS_QVLFCSUX = 1337
-PPC_INS_QVLFCSUXA = 1338
-PPC_INS_QVLFCSX = 1339
-PPC_INS_QVLFCSXA = 1340
-PPC_INS_QVLFDUX = 1341
-PPC_INS_QVLFDUXA = 1342
-PPC_INS_QVLFDX = 1343
-PPC_INS_QVLFDXA = 1344
-PPC_INS_QVLFIWAX = 1345
-PPC_INS_QVLFIWAXA = 1346
-PPC_INS_QVLFIWZX = 1347
-PPC_INS_QVLFIWZXA = 1348
-PPC_INS_QVLFSUX = 1349
-PPC_INS_QVLFSUXA = 1350
-PPC_INS_QVLFSX = 1351
-PPC_INS_QVLFSXA = 1352
-PPC_INS_QVLPCLDX = 1353
-PPC_INS_QVLPCLSX = 1354
-PPC_INS_QVLPCRDX = 1355
-PPC_INS_QVLPCRSX = 1356
-PPC_INS_QVSTFCDUX = 1357
-PPC_INS_QVSTFCDUXA = 1358
-PPC_INS_QVSTFCDUXI = 1359
-PPC_INS_QVSTFCDUXIA = 1360
-PPC_INS_QVSTFCDX = 1361
-PPC_INS_QVSTFCDXA = 1362
-PPC_INS_QVSTFCDXI = 1363
-PPC_INS_QVSTFCDXIA = 1364
-PPC_INS_QVSTFCSUX = 1365
-PPC_INS_QVSTFCSUXA = 1366
-PPC_INS_QVSTFCSUXI = 1367
-PPC_INS_QVSTFCSUXIA = 1368
-PPC_INS_QVSTFCSX = 1369
-PPC_INS_QVSTFCSXA = 1370
-PPC_INS_QVSTFCSXI = 1371
-PPC_INS_QVSTFCSXIA = 1372
-PPC_INS_QVSTFDUX = 1373
-PPC_INS_QVSTFDUXA = 1374
-PPC_INS_QVSTFDUXI = 1375
-PPC_INS_QVSTFDUXIA = 1376
-PPC_INS_QVSTFDX = 1377
-PPC_INS_QVSTFDXA = 1378
-PPC_INS_QVSTFDXI = 1379
-PPC_INS_QVSTFDXIA = 1380
-PPC_INS_QVSTFIWX = 1381
-PPC_INS_QVSTFIWXA = 1382
-PPC_INS_QVSTFSUX = 1383
-PPC_INS_QVSTFSUXA = 1384
-PPC_INS_QVSTFSUXI = 1385
-PPC_INS_QVSTFSUXIA = 1386
-PPC_INS_QVSTFSX = 1387
-PPC_INS_QVSTFSXA = 1388
-PPC_INS_QVSTFSXI = 1389
-PPC_INS_QVSTFSXIA = 1390
-PPC_INS_RFCI = 1391
-PPC_INS_RFDI = 1392
-PPC_INS_RFEBB = 1393
-PPC_INS_RFI = 1394
-PPC_INS_RFID = 1395
-PPC_INS_RFMCI = 1396
-PPC_INS_RLDCL = 1397
-PPC_INS_RLDCR = 1398
-PPC_INS_RLDIC = 1399
-PPC_INS_RLDICL = 1400
-PPC_INS_RLDICR = 1401
-PPC_INS_RLDIMI = 1402
-PPC_INS_SC = 1403
-PPC_INS_SETB = 1404
-PPC_INS_SETBC = 1405
-PPC_INS_SETBCR = 1406
-PPC_INS_SETNBC = 1407
-PPC_INS_SETNBCR = 1408
-PPC_INS_SLBFEE = 1409
-PPC_INS_SLBIA = 1410
-PPC_INS_SLBIE = 1411
-PPC_INS_SLBIEG = 1412
-PPC_INS_SLBMFEE = 1413
-PPC_INS_SLBMFEV = 1414
-PPC_INS_SLBMTE = 1415
-PPC_INS_SLBSYNC = 1416
-PPC_INS_SLD = 1417
-PPC_INS_SLW = 1418
-PPC_INS_STW = 1419
-PPC_INS_STWX = 1420
-PPC_INS_SRAD = 1421
-PPC_INS_SRADI = 1422
-PPC_INS_SRAW = 1423
-PPC_INS_SRAWI = 1424
-PPC_INS_SRD = 1425
-PPC_INS_SRW = 1426
-PPC_INS_STB = 1427
-PPC_INS_STBCIX = 1428
-PPC_INS_STBCX = 1429
-PPC_INS_STBEPX = 1430
-PPC_INS_STBU = 1431
-PPC_INS_STBUX = 1432
-PPC_INS_STBX = 1433
-PPC_INS_STD = 1434
-PPC_INS_STDAT = 1435
-PPC_INS_STDBRX = 1436
-PPC_INS_STDCIX = 1437
-PPC_INS_STDCX = 1438
-PPC_INS_STDU = 1439
-PPC_INS_STDUX = 1440
-PPC_INS_STDX = 1441
-PPC_INS_STFD = 1442
-PPC_INS_STFDEPX = 1443
-PPC_INS_STFDU = 1444
-PPC_INS_STFDUX = 1445
-PPC_INS_STFDX = 1446
-PPC_INS_STFIWX = 1447
-PPC_INS_STFS = 1448
-PPC_INS_STFSU = 1449
-PPC_INS_STFSUX = 1450
-PPC_INS_STFSX = 1451
-PPC_INS_STH = 1452
-PPC_INS_STHBRX = 1453
-PPC_INS_STHCIX = 1454
-PPC_INS_STHCX = 1455
-PPC_INS_STHEPX = 1456
-PPC_INS_STHU = 1457
-PPC_INS_STHUX = 1458
-PPC_INS_STHX = 1459
-PPC_INS_STMW = 1460
-PPC_INS_STOP = 1461
-PPC_INS_STQ = 1462
-PPC_INS_STQCX = 1463
-PPC_INS_STSWI = 1464
-PPC_INS_STVEBX = 1465
-PPC_INS_STVEHX = 1466
-PPC_INS_STVEWX = 1467
-PPC_INS_STVX = 1468
-PPC_INS_STVXL = 1469
-PPC_INS_STWAT = 1470
-PPC_INS_STWBRX = 1471
-PPC_INS_STWCIX = 1472
-PPC_INS_STWCX = 1473
-PPC_INS_STWEPX = 1474
-PPC_INS_STWU = 1475
-PPC_INS_STWUX = 1476
-PPC_INS_STXSD = 1477
-PPC_INS_STXSDX = 1478
-PPC_INS_STXSIBX = 1479
-PPC_INS_STXSIHX = 1480
-PPC_INS_STXSIWX = 1481
-PPC_INS_STXSSP = 1482
-PPC_INS_STXSSPX = 1483
-PPC_INS_STXV = 1484
-PPC_INS_STXVB16X = 1485
-PPC_INS_STXVD2X = 1486
-PPC_INS_STXVH8X = 1487
-PPC_INS_STXVL = 1488
-PPC_INS_STXVLL = 1489
-PPC_INS_STXVP = 1490
-PPC_INS_STXVPRL = 1491
-PPC_INS_STXVPRLL = 1492
-PPC_INS_STXVPX = 1493
-PPC_INS_STXVRBX = 1494
-PPC_INS_STXVRDX = 1495
-PPC_INS_STXVRHX = 1496
-PPC_INS_STXVRL = 1497
-PPC_INS_STXVRLL = 1498
-PPC_INS_STXVRWX = 1499
-PPC_INS_STXVW4X = 1500
-PPC_INS_STXVX = 1501
-PPC_INS_SUBF = 1502
-PPC_INS_SUBFC = 1503
-PPC_INS_SUBFCO = 1504
-PPC_INS_SUBFE = 1505
-PPC_INS_SUBFEO = 1506
-PPC_INS_SUBFIC = 1507
-PPC_INS_SUBFME = 1508
-PPC_INS_SUBFMEO = 1509
-PPC_INS_SUBFO = 1510
-PPC_INS_SUBFUS = 1511
-PPC_INS_SUBFZE = 1512
-PPC_INS_SUBFZEO = 1513
-PPC_INS_SYNC = 1514
-PPC_INS_TABORT = 1515
-PPC_INS_TABORTDC = 1516
-PPC_INS_TABORTDCI = 1517
-PPC_INS_TABORTWC = 1518
-PPC_INS_TABORTWCI = 1519
-PPC_INS_TBEGIN = 1520
-PPC_INS_TCHECK = 1521
-PPC_INS_TD = 1522
-PPC_INS_TDI = 1523
-PPC_INS_TEND = 1524
-PPC_INS_TLBIA = 1525
-PPC_INS_TLBIE = 1526
-PPC_INS_TLBIEL = 1527
-PPC_INS_TLBIVAX = 1528
-PPC_INS_TLBLD = 1529
-PPC_INS_TLBLI = 1530
-PPC_INS_TLBRE = 1531
-PPC_INS_TLBSX = 1532
-PPC_INS_TLBSYNC = 1533
-PPC_INS_TLBWE = 1534
-PPC_INS_TRAP = 1535
-PPC_INS_TRECHKPT = 1536
-PPC_INS_TRECLAIM = 1537
-PPC_INS_TSR = 1538
-PPC_INS_TW = 1539
-PPC_INS_TWI = 1540
-PPC_INS_VABSDUB = 1541
-PPC_INS_VABSDUH = 1542
-PPC_INS_VABSDUW = 1543
-PPC_INS_VADDCUQ = 1544
-PPC_INS_VADDCUW = 1545
-PPC_INS_VADDECUQ = 1546
-PPC_INS_VADDEUQM = 1547
-PPC_INS_VADDFP = 1548
-PPC_INS_VADDSBS = 1549
-PPC_INS_VADDSHS = 1550
-PPC_INS_VADDSWS = 1551
-PPC_INS_VADDUBM = 1552
-PPC_INS_VADDUBS = 1553
-PPC_INS_VADDUDM = 1554
-PPC_INS_VADDUHM = 1555
-PPC_INS_VADDUHS = 1556
-PPC_INS_VADDUQM = 1557
-PPC_INS_VADDUWM = 1558
-PPC_INS_VADDUWS = 1559
-PPC_INS_VAND = 1560
-PPC_INS_VANDC = 1561
-PPC_INS_VAVGSB = 1562
-PPC_INS_VAVGSH = 1563
-PPC_INS_VAVGSW = 1564
-PPC_INS_VAVGUB = 1565
-PPC_INS_VAVGUH = 1566
-PPC_INS_VAVGUW = 1567
-PPC_INS_VBPERMD = 1568
-PPC_INS_VBPERMQ = 1569
-PPC_INS_VCFSX = 1570
-PPC_INS_VCFUGED = 1571
-PPC_INS_VCFUX = 1572
-PPC_INS_VCIPHER = 1573
-PPC_INS_VCIPHERLAST = 1574
-PPC_INS_VCLRLB = 1575
-PPC_INS_VCLRRB = 1576
-PPC_INS_VCLZB = 1577
-PPC_INS_VCLZD = 1578
-PPC_INS_VCLZDM = 1579
-PPC_INS_VCLZH = 1580
-PPC_INS_VCLZLSBB = 1581
-PPC_INS_VCLZW = 1582
-PPC_INS_VCMPBFP = 1583
-PPC_INS_VCMPEQFP = 1584
-PPC_INS_VCMPEQUB = 1585
-PPC_INS_VCMPEQUD = 1586
-PPC_INS_VCMPEQUH = 1587
-PPC_INS_VCMPEQUQ = 1588
-PPC_INS_VCMPEQUW = 1589
-PPC_INS_VCMPGEFP = 1590
-PPC_INS_VCMPGTFP = 1591
-PPC_INS_VCMPGTSB = 1592
-PPC_INS_VCMPGTSD = 1593
-PPC_INS_VCMPGTSH = 1594
-PPC_INS_VCMPGTSQ = 1595
-PPC_INS_VCMPGTSW = 1596
-PPC_INS_VCMPGTUB = 1597
-PPC_INS_VCMPGTUD = 1598
-PPC_INS_VCMPGTUH = 1599
-PPC_INS_VCMPGTUQ = 1600
-PPC_INS_VCMPGTUW = 1601
-PPC_INS_VCMPNEB = 1602
-PPC_INS_VCMPNEH = 1603
-PPC_INS_VCMPNEW = 1604
-PPC_INS_VCMPNEZB = 1605
-PPC_INS_VCMPNEZH = 1606
-PPC_INS_VCMPNEZW = 1607
-PPC_INS_VCMPSQ = 1608
-PPC_INS_VCMPUQ = 1609
-PPC_INS_VCNTMBB = 1610
-PPC_INS_VCNTMBD = 1611
-PPC_INS_VCNTMBH = 1612
-PPC_INS_VCNTMBW = 1613
-PPC_INS_VCTSXS = 1614
-PPC_INS_VCTUXS = 1615
-PPC_INS_VCTZB = 1616
-PPC_INS_VCTZD = 1617
-PPC_INS_VCTZDM = 1618
-PPC_INS_VCTZH = 1619
-PPC_INS_VCTZLSBB = 1620
-PPC_INS_VCTZW = 1621
-PPC_INS_VDIVESD = 1622
-PPC_INS_VDIVESQ = 1623
-PPC_INS_VDIVESW = 1624
-PPC_INS_VDIVEUD = 1625
-PPC_INS_VDIVEUQ = 1626
-PPC_INS_VDIVEUW = 1627
-PPC_INS_VDIVSD = 1628
-PPC_INS_VDIVSQ = 1629
-PPC_INS_VDIVSW = 1630
-PPC_INS_VDIVUD = 1631
-PPC_INS_VDIVUQ = 1632
-PPC_INS_VDIVUW = 1633
-PPC_INS_VEQV = 1634
-PPC_INS_VEXPANDBM = 1635
-PPC_INS_VEXPANDDM = 1636
-PPC_INS_VEXPANDHM = 1637
-PPC_INS_VEXPANDQM = 1638
-PPC_INS_VEXPANDWM = 1639
-PPC_INS_VEXPTEFP = 1640
-PPC_INS_VEXTDDVLX = 1641
-PPC_INS_VEXTDDVRX = 1642
-PPC_INS_VEXTDUBVLX = 1643
-PPC_INS_VEXTDUBVRX = 1644
-PPC_INS_VEXTDUHVLX = 1645
-PPC_INS_VEXTDUHVRX = 1646
-PPC_INS_VEXTDUWVLX = 1647
-PPC_INS_VEXTDUWVRX = 1648
-PPC_INS_VEXTRACTBM = 1649
-PPC_INS_VEXTRACTD = 1650
-PPC_INS_VEXTRACTDM = 1651
-PPC_INS_VEXTRACTHM = 1652
-PPC_INS_VEXTRACTQM = 1653
-PPC_INS_VEXTRACTUB = 1654
-PPC_INS_VEXTRACTUH = 1655
-PPC_INS_VEXTRACTUW = 1656
-PPC_INS_VEXTRACTWM = 1657
-PPC_INS_VEXTSB2D = 1658
-PPC_INS_VEXTSB2W = 1659
-PPC_INS_VEXTSD2Q = 1660
-PPC_INS_VEXTSH2D = 1661
-PPC_INS_VEXTSH2W = 1662
-PPC_INS_VEXTSW2D = 1663
-PPC_INS_VEXTUBLX = 1664
-PPC_INS_VEXTUBRX = 1665
-PPC_INS_VEXTUHLX = 1666
-PPC_INS_VEXTUHRX = 1667
-PPC_INS_VEXTUWLX = 1668
-PPC_INS_VEXTUWRX = 1669
-PPC_INS_VGBBD = 1670
-PPC_INS_VGNB = 1671
-PPC_INS_VINSBLX = 1672
-PPC_INS_VINSBRX = 1673
-PPC_INS_VINSBVLX = 1674
-PPC_INS_VINSBVRX = 1675
-PPC_INS_VINSD = 1676
-PPC_INS_VINSDLX = 1677
-PPC_INS_VINSDRX = 1678
-PPC_INS_VINSERTB = 1679
-PPC_INS_VINSERTD = 1680
-PPC_INS_VINSERTH = 1681
-PPC_INS_VINSERTW = 1682
-PPC_INS_VINSHLX = 1683
-PPC_INS_VINSHRX = 1684
-PPC_INS_VINSHVLX = 1685
-PPC_INS_VINSHVRX = 1686
-PPC_INS_VINSW = 1687
-PPC_INS_VINSWLX = 1688
-PPC_INS_VINSWRX = 1689
-PPC_INS_VINSWVLX = 1690
-PPC_INS_VINSWVRX = 1691
-PPC_INS_VLOGEFP = 1692
-PPC_INS_VMADDFP = 1693
-PPC_INS_VMAXFP = 1694
-PPC_INS_VMAXSB = 1695
-PPC_INS_VMAXSD = 1696
-PPC_INS_VMAXSH = 1697
-PPC_INS_VMAXSW = 1698
-PPC_INS_VMAXUB = 1699
-PPC_INS_VMAXUD = 1700
-PPC_INS_VMAXUH = 1701
-PPC_INS_VMAXUW = 1702
-PPC_INS_VMHADDSHS = 1703
-PPC_INS_VMHRADDSHS = 1704
-PPC_INS_VMINFP = 1705
-PPC_INS_VMINSB = 1706
-PPC_INS_VMINSD = 1707
-PPC_INS_VMINSH = 1708
-PPC_INS_VMINSW = 1709
-PPC_INS_VMINUB = 1710
-PPC_INS_VMINUD = 1711
-PPC_INS_VMINUH = 1712
-PPC_INS_VMINUW = 1713
-PPC_INS_VMLADDUHM = 1714
-PPC_INS_VMODSD = 1715
-PPC_INS_VMODSQ = 1716
-PPC_INS_VMODSW = 1717
-PPC_INS_VMODUD = 1718
-PPC_INS_VMODUQ = 1719
-PPC_INS_VMODUW = 1720
-PPC_INS_VMRGEW = 1721
-PPC_INS_VMRGHB = 1722
-PPC_INS_VMRGHH = 1723
-PPC_INS_VMRGHW = 1724
-PPC_INS_VMRGLB = 1725
-PPC_INS_VMRGLH = 1726
-PPC_INS_VMRGLW = 1727
-PPC_INS_VMRGOW = 1728
-PPC_INS_VMSUMCUD = 1729
-PPC_INS_VMSUMMBM = 1730
-PPC_INS_VMSUMSHM = 1731
-PPC_INS_VMSUMSHS = 1732
-PPC_INS_VMSUMUBM = 1733
-PPC_INS_VMSUMUDM = 1734
-PPC_INS_VMSUMUHM = 1735
-PPC_INS_VMSUMUHS = 1736
-PPC_INS_VMUL10CUQ = 1737
-PPC_INS_VMUL10ECUQ = 1738
-PPC_INS_VMUL10EUQ = 1739
-PPC_INS_VMUL10UQ = 1740
-PPC_INS_VMULESB = 1741
-PPC_INS_VMULESD = 1742
-PPC_INS_VMULESH = 1743
-PPC_INS_VMULESW = 1744
-PPC_INS_VMULEUB = 1745
-PPC_INS_VMULEUD = 1746
-PPC_INS_VMULEUH = 1747
-PPC_INS_VMULEUW = 1748
-PPC_INS_VMULHSD = 1749
-PPC_INS_VMULHSW = 1750
-PPC_INS_VMULHUD = 1751
-PPC_INS_VMULHUW = 1752
-PPC_INS_VMULLD = 1753
-PPC_INS_VMULOSB = 1754
-PPC_INS_VMULOSD = 1755
-PPC_INS_VMULOSH = 1756
-PPC_INS_VMULOSW = 1757
-PPC_INS_VMULOUB = 1758
-PPC_INS_VMULOUD = 1759
-PPC_INS_VMULOUH = 1760
-PPC_INS_VMULOUW = 1761
-PPC_INS_VMULUWM = 1762
-PPC_INS_VNAND = 1763
-PPC_INS_VNCIPHER = 1764
-PPC_INS_VNCIPHERLAST = 1765
-PPC_INS_VNEGD = 1766
-PPC_INS_VNEGW = 1767
-PPC_INS_VNMSUBFP = 1768
-PPC_INS_VNOR = 1769
-PPC_INS_VOR = 1770
-PPC_INS_VORC = 1771
-PPC_INS_VPDEPD = 1772
-PPC_INS_VPERM = 1773
-PPC_INS_VPERMR = 1774
-PPC_INS_VPERMXOR = 1775
-PPC_INS_VPEXTD = 1776
-PPC_INS_VPKPX = 1777
-PPC_INS_VPKSDSS = 1778
-PPC_INS_VPKSDUS = 1779
-PPC_INS_VPKSHSS = 1780
-PPC_INS_VPKSHUS = 1781
-PPC_INS_VPKSWSS = 1782
-PPC_INS_VPKSWUS = 1783
-PPC_INS_VPKUDUM = 1784
-PPC_INS_VPKUDUS = 1785
-PPC_INS_VPKUHUM = 1786
-PPC_INS_VPKUHUS = 1787
-PPC_INS_VPKUWUM = 1788
-PPC_INS_VPKUWUS = 1789
-PPC_INS_VPMSUMB = 1790
-PPC_INS_VPMSUMD = 1791
-PPC_INS_VPMSUMH = 1792
-PPC_INS_VPMSUMW = 1793
-PPC_INS_VPOPCNTB = 1794
-PPC_INS_VPOPCNTD = 1795
-PPC_INS_VPOPCNTH = 1796
-PPC_INS_VPOPCNTW = 1797
-PPC_INS_VPRTYBD = 1798
-PPC_INS_VPRTYBQ = 1799
-PPC_INS_VPRTYBW = 1800
-PPC_INS_VREFP = 1801
-PPC_INS_VRFIM = 1802
-PPC_INS_VRFIN = 1803
-PPC_INS_VRFIP = 1804
-PPC_INS_VRFIZ = 1805
-PPC_INS_VRLB = 1806
-PPC_INS_VRLD = 1807
-PPC_INS_VRLDMI = 1808
-PPC_INS_VRLDNM = 1809
-PPC_INS_VRLH = 1810
-PPC_INS_VRLQ = 1811
-PPC_INS_VRLQMI = 1812
-PPC_INS_VRLQNM = 1813
-PPC_INS_VRLW = 1814
-PPC_INS_VRLWMI = 1815
-PPC_INS_VRLWNM = 1816
-PPC_INS_VRSQRTEFP = 1817
-PPC_INS_VSBOX = 1818
-PPC_INS_VSEL = 1819
-PPC_INS_VSHASIGMAD = 1820
-PPC_INS_VSHASIGMAW = 1821
-PPC_INS_VSL = 1822
-PPC_INS_VSLB = 1823
-PPC_INS_VSLD = 1824
-PPC_INS_VSLDBI = 1825
-PPC_INS_VSLDOI = 1826
-PPC_INS_VSLH = 1827
-PPC_INS_VSLO = 1828
-PPC_INS_VSLQ = 1829
-PPC_INS_VSLV = 1830
-PPC_INS_VSLW = 1831
-PPC_INS_VSPLTB = 1832
-PPC_INS_VSPLTH = 1833
-PPC_INS_VSPLTISB = 1834
-PPC_INS_VSPLTISH = 1835
-PPC_INS_VSPLTISW = 1836
-PPC_INS_VSPLTW = 1837
-PPC_INS_VSR = 1838
-PPC_INS_VSRAB = 1839
-PPC_INS_VSRAD = 1840
-PPC_INS_VSRAH = 1841
-PPC_INS_VSRAQ = 1842
-PPC_INS_VSRAW = 1843
-PPC_INS_VSRB = 1844
-PPC_INS_VSRD = 1845
-PPC_INS_VSRDBI = 1846
-PPC_INS_VSRH = 1847
-PPC_INS_VSRO = 1848
-PPC_INS_VSRQ = 1849
-PPC_INS_VSRV = 1850
-PPC_INS_VSRW = 1851
-PPC_INS_VSTRIBL = 1852
-PPC_INS_VSTRIBR = 1853
-PPC_INS_VSTRIHL = 1854
-PPC_INS_VSTRIHR = 1855
-PPC_INS_VSUBCUQ = 1856
-PPC_INS_VSUBCUW = 1857
-PPC_INS_VSUBECUQ = 1858
-PPC_INS_VSUBEUQM = 1859
-PPC_INS_VSUBFP = 1860
-PPC_INS_VSUBSBS = 1861
-PPC_INS_VSUBSHS = 1862
-PPC_INS_VSUBSWS = 1863
-PPC_INS_VSUBUBM = 1864
-PPC_INS_VSUBUBS = 1865
-PPC_INS_VSUBUDM = 1866
-PPC_INS_VSUBUHM = 1867
-PPC_INS_VSUBUHS = 1868
-PPC_INS_VSUBUQM = 1869
-PPC_INS_VSUBUWM = 1870
-PPC_INS_VSUBUWS = 1871
-PPC_INS_VSUM2SWS = 1872
-PPC_INS_VSUM4SBS = 1873
-PPC_INS_VSUM4SHS = 1874
-PPC_INS_VSUM4UBS = 1875
-PPC_INS_VSUMSWS = 1876
-PPC_INS_VUPKHPX = 1877
-PPC_INS_VUPKHSB = 1878
-PPC_INS_VUPKHSH = 1879
-PPC_INS_VUPKHSW = 1880
-PPC_INS_VUPKLPX = 1881
-PPC_INS_VUPKLSB = 1882
-PPC_INS_VUPKLSH = 1883
-PPC_INS_VUPKLSW = 1884
-PPC_INS_VXOR = 1885
-PPC_INS_WAIT = 1886
-PPC_INS_WRTEE = 1887
-PPC_INS_WRTEEI = 1888
-PPC_INS_XOR = 1889
-PPC_INS_XORI = 1890
-PPC_INS_XORIS = 1891
-PPC_INS_XSABSDP = 1892
-PPC_INS_XSABSQP = 1893
-PPC_INS_XSADDDP = 1894
-PPC_INS_XSADDQP = 1895
-PPC_INS_XSADDQPO = 1896
-PPC_INS_XSADDSP = 1897
-PPC_INS_XSCMPEQDP = 1898
-PPC_INS_XSCMPEQQP = 1899
-PPC_INS_XSCMPEXPDP = 1900
-PPC_INS_XSCMPEXPQP = 1901
-PPC_INS_XSCMPGEDP = 1902
-PPC_INS_XSCMPGEQP = 1903
-PPC_INS_XSCMPGTDP = 1904
-PPC_INS_XSCMPGTQP = 1905
-PPC_INS_XSCMPODP = 1906
-PPC_INS_XSCMPOQP = 1907
-PPC_INS_XSCMPUDP = 1908
-PPC_INS_XSCMPUQP = 1909
-PPC_INS_XSCPSGNDP = 1910
-PPC_INS_XSCPSGNQP = 1911
-PPC_INS_XSCVDPHP = 1912
-PPC_INS_XSCVDPQP = 1913
-PPC_INS_XSCVDPSP = 1914
-PPC_INS_XSCVDPSPN = 1915
-PPC_INS_XSCVDPSXDS = 1916
-PPC_INS_XSCVDPSXWS = 1917
-PPC_INS_XSCVDPUXDS = 1918
-PPC_INS_XSCVDPUXWS = 1919
-PPC_INS_XSCVHPDP = 1920
-PPC_INS_XSCVQPDP = 1921
-PPC_INS_XSCVQPDPO = 1922
-PPC_INS_XSCVQPSDZ = 1923
-PPC_INS_XSCVQPSQZ = 1924
-PPC_INS_XSCVQPSWZ = 1925
-PPC_INS_XSCVQPUDZ = 1926
-PPC_INS_XSCVQPUQZ = 1927
-PPC_INS_XSCVQPUWZ = 1928
-PPC_INS_XSCVSDQP = 1929
-PPC_INS_XSCVSPDP = 1930
-PPC_INS_XSCVSPDPN = 1931
-PPC_INS_XSCVSQQP = 1932
-PPC_INS_XSCVSXDDP = 1933
-PPC_INS_XSCVSXDSP = 1934
-PPC_INS_XSCVUDQP = 1935
-PPC_INS_XSCVUQQP = 1936
-PPC_INS_XSCVUXDDP = 1937
-PPC_INS_XSCVUXDSP = 1938
-PPC_INS_XSDIVDP = 1939
-PPC_INS_XSDIVQP = 1940
-PPC_INS_XSDIVQPO = 1941
-PPC_INS_XSDIVSP = 1942
-PPC_INS_XSIEXPDP = 1943
-PPC_INS_XSIEXPQP = 1944
-PPC_INS_XSMADDADP = 1945
-PPC_INS_XSMADDASP = 1946
-PPC_INS_XSMADDMDP = 1947
-PPC_INS_XSMADDMSP = 1948
-PPC_INS_XSMADDQP = 1949
-PPC_INS_XSMADDQPO = 1950
-PPC_INS_XSMAXCDP = 1951
-PPC_INS_XSMAXCQP = 1952
-PPC_INS_XSMAXDP = 1953
-PPC_INS_XSMAXJDP = 1954
-PPC_INS_XSMINCDP = 1955
-PPC_INS_XSMINCQP = 1956
-PPC_INS_XSMINDP = 1957
-PPC_INS_XSMINJDP = 1958
-PPC_INS_XSMSUBADP = 1959
-PPC_INS_XSMSUBASP = 1960
-PPC_INS_XSMSUBMDP = 1961
-PPC_INS_XSMSUBMSP = 1962
-PPC_INS_XSMSUBQP = 1963
-PPC_INS_XSMSUBQPO = 1964
-PPC_INS_XSMULDP = 1965
-PPC_INS_XSMULQP = 1966
-PPC_INS_XSMULQPO = 1967
-PPC_INS_XSMULSP = 1968
-PPC_INS_XSNABSDP = 1969
-PPC_INS_XSNABSQP = 1970
-PPC_INS_XSNEGDP = 1971
-PPC_INS_XSNEGQP = 1972
-PPC_INS_XSNMADDADP = 1973
-PPC_INS_XSNMADDASP = 1974
-PPC_INS_XSNMADDMDP = 1975
-PPC_INS_XSNMADDMSP = 1976
-PPC_INS_XSNMADDQP = 1977
-PPC_INS_XSNMADDQPO = 1978
-PPC_INS_XSNMSUBADP = 1979
-PPC_INS_XSNMSUBASP = 1980
-PPC_INS_XSNMSUBMDP = 1981
-PPC_INS_XSNMSUBMSP = 1982
-PPC_INS_XSNMSUBQP = 1983
-PPC_INS_XSNMSUBQPO = 1984
-PPC_INS_XSRDPI = 1985
-PPC_INS_XSRDPIC = 1986
-PPC_INS_XSRDPIM = 1987
-PPC_INS_XSRDPIP = 1988
-PPC_INS_XSRDPIZ = 1989
-PPC_INS_XSREDP = 1990
-PPC_INS_XSRESP = 1991
-PPC_INS_XSRQPI = 1992
-PPC_INS_XSRQPIX = 1993
-PPC_INS_XSRQPXP = 1994
-PPC_INS_XSRSP = 1995
-PPC_INS_XSRSQRTEDP = 1996
-PPC_INS_XSRSQRTESP = 1997
-PPC_INS_XSSQRTDP = 1998
-PPC_INS_XSSQRTQP = 1999
-PPC_INS_XSSQRTQPO = 2000
-PPC_INS_XSSQRTSP = 2001
-PPC_INS_XSSUBDP = 2002
-PPC_INS_XSSUBQP = 2003
-PPC_INS_XSSUBQPO = 2004
-PPC_INS_XSSUBSP = 2005
-PPC_INS_XSTDIVDP = 2006
-PPC_INS_XSTSQRTDP = 2007
-PPC_INS_XSTSTDCDP = 2008
-PPC_INS_XSTSTDCQP = 2009
-PPC_INS_XSTSTDCSP = 2010
-PPC_INS_XSXEXPDP = 2011
-PPC_INS_XSXEXPQP = 2012
-PPC_INS_XSXSIGDP = 2013
-PPC_INS_XSXSIGQP = 2014
-PPC_INS_XVABSDP = 2015
-PPC_INS_XVABSSP = 2016
-PPC_INS_XVADDDP = 2017
-PPC_INS_XVADDSP = 2018
-PPC_INS_XVBF16GER2 = 2019
-PPC_INS_XVBF16GER2NN = 2020
-PPC_INS_XVBF16GER2NP = 2021
-PPC_INS_XVBF16GER2PN = 2022
-PPC_INS_XVBF16GER2PP = 2023
-PPC_INS_XVCMPEQDP = 2024
-PPC_INS_XVCMPEQSP = 2025
-PPC_INS_XVCMPGEDP = 2026
-PPC_INS_XVCMPGESP = 2027
-PPC_INS_XVCMPGTDP = 2028
-PPC_INS_XVCMPGTSP = 2029
-PPC_INS_XVCPSGNDP = 2030
-PPC_INS_XVCPSGNSP = 2031
-PPC_INS_XVCVBF16SPN = 2032
-PPC_INS_XVCVDPSP = 2033
-PPC_INS_XVCVDPSXDS = 2034
-PPC_INS_XVCVDPSXWS = 2035
-PPC_INS_XVCVDPUXDS = 2036
-PPC_INS_XVCVDPUXWS = 2037
-PPC_INS_XVCVHPSP = 2038
-PPC_INS_XVCVSPBF16 = 2039
-PPC_INS_XVCVSPDP = 2040
-PPC_INS_XVCVSPHP = 2041
-PPC_INS_XVCVSPSXDS = 2042
-PPC_INS_XVCVSPSXWS = 2043
-PPC_INS_XVCVSPUXDS = 2044
-PPC_INS_XVCVSPUXWS = 2045
-PPC_INS_XVCVSXDDP = 2046
-PPC_INS_XVCVSXDSP = 2047
-PPC_INS_XVCVSXWDP = 2048
-PPC_INS_XVCVSXWSP = 2049
-PPC_INS_XVCVUXDDP = 2050
-PPC_INS_XVCVUXDSP = 2051
-PPC_INS_XVCVUXWDP = 2052
-PPC_INS_XVCVUXWSP = 2053
-PPC_INS_XVDIVDP = 2054
-PPC_INS_XVDIVSP = 2055
-PPC_INS_XVF16GER2 = 2056
-PPC_INS_XVF16GER2NN = 2057
-PPC_INS_XVF16GER2NP = 2058
-PPC_INS_XVF16GER2PN = 2059
-PPC_INS_XVF16GER2PP = 2060
-PPC_INS_XVF32GER = 2061
-PPC_INS_XVF32GERNN = 2062
-PPC_INS_XVF32GERNP = 2063
-PPC_INS_XVF32GERPN = 2064
-PPC_INS_XVF32GERPP = 2065
-PPC_INS_XVF64GER = 2066
-PPC_INS_XVF64GERNN = 2067
-PPC_INS_XVF64GERNP = 2068
-PPC_INS_XVF64GERPN = 2069
-PPC_INS_XVF64GERPP = 2070
-PPC_INS_XVI16GER2 = 2071
-PPC_INS_XVI16GER2PP = 2072
-PPC_INS_XVI16GER2S = 2073
-PPC_INS_XVI16GER2SPP = 2074
-PPC_INS_XVI4GER8 = 2075
-PPC_INS_XVI4GER8PP = 2076
-PPC_INS_XVI8GER4 = 2077
-PPC_INS_XVI8GER4PP = 2078
-PPC_INS_XVI8GER4SPP = 2079
-PPC_INS_XVIEXPDP = 2080
-PPC_INS_XVIEXPSP = 2081
-PPC_INS_XVMADDADP = 2082
-PPC_INS_XVMADDASP = 2083
-PPC_INS_XVMADDMDP = 2084
-PPC_INS_XVMADDMSP = 2085
-PPC_INS_XVMAXDP = 2086
-PPC_INS_XVMAXSP = 2087
-PPC_INS_XVMINDP = 2088
-PPC_INS_XVMINSP = 2089
-PPC_INS_XVMSUBADP = 2090
-PPC_INS_XVMSUBASP = 2091
-PPC_INS_XVMSUBMDP = 2092
-PPC_INS_XVMSUBMSP = 2093
-PPC_INS_XVMULDP = 2094
-PPC_INS_XVMULSP = 2095
-PPC_INS_XVNABSDP = 2096
-PPC_INS_XVNABSSP = 2097
-PPC_INS_XVNEGDP = 2098
-PPC_INS_XVNEGSP = 2099
-PPC_INS_XVNMADDADP = 2100
-PPC_INS_XVNMADDASP = 2101
-PPC_INS_XVNMADDMDP = 2102
-PPC_INS_XVNMADDMSP = 2103
-PPC_INS_XVNMSUBADP = 2104
-PPC_INS_XVNMSUBASP = 2105
-PPC_INS_XVNMSUBMDP = 2106
-PPC_INS_XVNMSUBMSP = 2107
-PPC_INS_XVRDPI = 2108
-PPC_INS_XVRDPIC = 2109
-PPC_INS_XVRDPIM = 2110
-PPC_INS_XVRDPIP = 2111
-PPC_INS_XVRDPIZ = 2112
-PPC_INS_XVREDP = 2113
-PPC_INS_XVRESP = 2114
-PPC_INS_XVRSPI = 2115
-PPC_INS_XVRSPIC = 2116
-PPC_INS_XVRSPIM = 2117
-PPC_INS_XVRSPIP = 2118
-PPC_INS_XVRSPIZ = 2119
-PPC_INS_XVRSQRTEDP = 2120
-PPC_INS_XVRSQRTESP = 2121
-PPC_INS_XVSQRTDP = 2122
-PPC_INS_XVSQRTSP = 2123
-PPC_INS_XVSUBDP = 2124
-PPC_INS_XVSUBSP = 2125
-PPC_INS_XVTDIVDP = 2126
-PPC_INS_XVTDIVSP = 2127
-PPC_INS_XVTLSBB = 2128
-PPC_INS_XVTSQRTDP = 2129
-PPC_INS_XVTSQRTSP = 2130
-PPC_INS_XVTSTDCDP = 2131
-PPC_INS_XVTSTDCSP = 2132
-PPC_INS_XVXEXPDP = 2133
-PPC_INS_XVXEXPSP = 2134
-PPC_INS_XVXSIGDP = 2135
-PPC_INS_XVXSIGSP = 2136
-PPC_INS_XXBLENDVB = 2137
-PPC_INS_XXBLENDVD = 2138
-PPC_INS_XXBLENDVH = 2139
-PPC_INS_XXBLENDVW = 2140
-PPC_INS_XXBRD = 2141
-PPC_INS_XXBRH = 2142
-PPC_INS_XXBRQ = 2143
-PPC_INS_XXBRW = 2144
-PPC_INS_XXEVAL = 2145
-PPC_INS_XXEXTRACTUW = 2146
-PPC_INS_XXGENPCVBM = 2147
-PPC_INS_XXGENPCVDM = 2148
-PPC_INS_XXGENPCVHM = 2149
-PPC_INS_XXGENPCVWM = 2150
-PPC_INS_XXINSERTW = 2151
-PPC_INS_XXLAND = 2152
-PPC_INS_XXLANDC = 2153
-PPC_INS_XXLEQV = 2154
-PPC_INS_XXLNAND = 2155
-PPC_INS_XXLNOR = 2156
-PPC_INS_XXLOR = 2157
-PPC_INS_XXLORC = 2158
-PPC_INS_XXLXOR = 2159
-PPC_INS_XXMFACC = 2160
-PPC_INS_XXMRGHW = 2161
-PPC_INS_XXMRGLW = 2162
-PPC_INS_XXMTACC = 2163
-PPC_INS_XXPERM = 2164
-PPC_INS_XXPERMDI = 2165
-PPC_INS_XXPERMR = 2166
-PPC_INS_XXPERMX = 2167
-PPC_INS_XXSEL = 2168
-PPC_INS_XXSETACCZ = 2169
-PPC_INS_XXSLDWI = 2170
-PPC_INS_XXSPLTI32DX = 2171
-PPC_INS_XXSPLTIB = 2172
-PPC_INS_XXSPLTIDP = 2173
-PPC_INS_XXSPLTIW = 2174
-PPC_INS_XXSPLTW = 2175
-PPC_INS_BC = 2176
-PPC_INS_BCA = 2177
-PPC_INS_BCCTR = 2178
-PPC_INS_BCCTRL = 2179
-PPC_INS_BCL = 2180
-PPC_INS_BCLA = 2181
-PPC_INS_BCLR = 2182
-PPC_INS_BCLRL = 2183
-PPC_INS_ENDING = 2184
-PPC_INS_ALIAS_BEGIN = 2185
-PPC_INS_ALIAS_RFEBB = 2186
-PPC_INS_ALIAS_LI = 2187
-PPC_INS_ALIAS_LIS = 2188
-PPC_INS_ALIAS_MR = 2189
-PPC_INS_ALIAS_MR_ = 2190
-PPC_INS_ALIAS_NOT = 2191
-PPC_INS_ALIAS_NOT_ = 2192
-PPC_INS_ALIAS_NOP = 2193
-PPC_INS_ALIAS_MTUDSCR = 2194
-PPC_INS_ALIAS_MFUDSCR = 2195
-PPC_INS_ALIAS_MTVRSAVE = 2196
-PPC_INS_ALIAS_MFVRSAVE = 2197
-PPC_INS_ALIAS_MTCR = 2198
-PPC_INS_ALIAS_SUB = 2199
-PPC_INS_ALIAS_SUB_ = 2200
-PPC_INS_ALIAS_SUBC = 2201
-PPC_INS_ALIAS_SUBC_ = 2202
-PPC_INS_ALIAS_VMR = 2203
-PPC_INS_ALIAS_VNOT = 2204
-PPC_INS_ALIAS_ROTLWI = 2205
-PPC_INS_ALIAS_ROTLWI_ = 2206
-PPC_INS_ALIAS_ROTLW = 2207
-PPC_INS_ALIAS_ROTLW_ = 2208
-PPC_INS_ALIAS_CLRLWI = 2209
-PPC_INS_ALIAS_CLRLWI_ = 2210
-PPC_INS_ALIAS_ISELLT = 2211
-PPC_INS_ALIAS_ISELGT = 2212
-PPC_INS_ALIAS_ISELEQ = 2213
-PPC_INS_ALIAS_XNOP = 2214
-PPC_INS_ALIAS_CNTLZW = 2215
-PPC_INS_ALIAS_CNTLZW_ = 2216
-PPC_INS_ALIAS_MTXER = 2217
-PPC_INS_ALIAS_MFXER = 2218
-PPC_INS_ALIAS_MFRTCU = 2219
-PPC_INS_ALIAS_MFRTCL = 2220
-PPC_INS_ALIAS_MTLR = 2221
-PPC_INS_ALIAS_MFLR = 2222
-PPC_INS_ALIAS_MTCTR = 2223
-PPC_INS_ALIAS_MFCTR = 2224
-PPC_INS_ALIAS_MTUAMR = 2225
-PPC_INS_ALIAS_MFUAMR = 2226
-PPC_INS_ALIAS_MTDSCR = 2227
-PPC_INS_ALIAS_MFDSCR = 2228
-PPC_INS_ALIAS_MTDSISR = 2229
-PPC_INS_ALIAS_MFDSISR = 2230
-PPC_INS_ALIAS_MTDAR = 2231
-PPC_INS_ALIAS_MFDAR = 2232
-PPC_INS_ALIAS_MTDEC = 2233
-PPC_INS_ALIAS_MFDEC = 2234
-PPC_INS_ALIAS_MTSDR1 = 2235
-PPC_INS_ALIAS_MFSDR1 = 2236
-PPC_INS_ALIAS_MTSRR0 = 2237
-PPC_INS_ALIAS_MFSRR0 = 2238
-PPC_INS_ALIAS_MTSRR1 = 2239
-PPC_INS_ALIAS_MFSRR1 = 2240
-PPC_INS_ALIAS_MTCFAR = 2241
-PPC_INS_ALIAS_MFCFAR = 2242
-PPC_INS_ALIAS_MTAMR = 2243
-PPC_INS_ALIAS_MFAMR = 2244
-PPC_INS_ALIAS_MFSPRG = 2245
-PPC_INS_ALIAS_MFSPRG0 = 2246
-PPC_INS_ALIAS_MTSPRG = 2247
-PPC_INS_ALIAS_MTSPRG0 = 2248
-PPC_INS_ALIAS_MFSPRG1 = 2249
-PPC_INS_ALIAS_MTSPRG1 = 2250
-PPC_INS_ALIAS_MFSPRG2 = 2251
-PPC_INS_ALIAS_MTSPRG2 = 2252
-PPC_INS_ALIAS_MFSPRG3 = 2253
-PPC_INS_ALIAS_MTSPRG3 = 2254
-PPC_INS_ALIAS_MFASR = 2255
-PPC_INS_ALIAS_MTASR = 2256
-PPC_INS_ALIAS_MTTBL = 2257
-PPC_INS_ALIAS_MTTBU = 2258
-PPC_INS_ALIAS_MFPVR = 2259
-PPC_INS_ALIAS_MFSPEFSCR = 2260
-PPC_INS_ALIAS_MTSPEFSCR = 2261
-PPC_INS_ALIAS_XVMOVDP = 2262
-PPC_INS_ALIAS_XVMOVSP = 2263
-PPC_INS_ALIAS_XXSPLTD = 2264
-PPC_INS_ALIAS_XXMRGHD = 2265
-PPC_INS_ALIAS_XXMRGLD = 2266
-PPC_INS_ALIAS_XXSWAPD = 2267
-PPC_INS_ALIAS_MFFPRD = 2268
-PPC_INS_ALIAS_MTFPRD = 2269
-PPC_INS_ALIAS_MFFPRWZ = 2270
-PPC_INS_ALIAS_MTFPRWA = 2271
-PPC_INS_ALIAS_MTFPRWZ = 2272
-PPC_INS_ALIAS_TEND_ = 2273
-PPC_INS_ALIAS_TENDALL_ = 2274
-PPC_INS_ALIAS_TSUSPEND_ = 2275
-PPC_INS_ALIAS_TRESUME_ = 2276
-PPC_INS_ALIAS_DCI = 2277
-PPC_INS_ALIAS_DCCCI = 2278
-PPC_INS_ALIAS_ICI = 2279
-PPC_INS_ALIAS_ICCCI = 2280
-PPC_INS_ALIAS_MTFSFI = 2281
-PPC_INS_ALIAS_MTFSFI_ = 2282
-PPC_INS_ALIAS_MTFSF = 2283
-PPC_INS_ALIAS_MTFSF_ = 2284
-PPC_INS_ALIAS_SC = 2285
-PPC_INS_ALIAS_SYNC = 2286
-PPC_INS_ALIAS_LWSYNC = 2287
-PPC_INS_ALIAS_PTESYNC = 2288
-PPC_INS_ALIAS_WAIT = 2289
-PPC_INS_ALIAS_WAITRSV = 2290
-PPC_INS_ALIAS_WAITIMPL = 2291
-PPC_INS_ALIAS_MBAR = 2292
-PPC_INS_ALIAS_CRSET = 2293
-PPC_INS_ALIAS_CRCLR = 2294
-PPC_INS_ALIAS_CRMOVE = 2295
-PPC_INS_ALIAS_CRNOT = 2296
-PPC_INS_ALIAS_MFTB = 2297
-PPC_INS_ALIAS_MFTBL = 2298
-PPC_INS_ALIAS_MFTBU = 2299
-PPC_INS_ALIAS_MFBR0 = 2300
-PPC_INS_ALIAS_MTBR0 = 2301
-PPC_INS_ALIAS_MFBR1 = 2302
-PPC_INS_ALIAS_MTBR1 = 2303
-PPC_INS_ALIAS_MFBR2 = 2304
-PPC_INS_ALIAS_MTBR2 = 2305
-PPC_INS_ALIAS_MFBR3 = 2306
-PPC_INS_ALIAS_MTBR3 = 2307
-PPC_INS_ALIAS_MFBR4 = 2308
-PPC_INS_ALIAS_MTBR4 = 2309
-PPC_INS_ALIAS_MFBR5 = 2310
-PPC_INS_ALIAS_MTBR5 = 2311
-PPC_INS_ALIAS_MFBR6 = 2312
-PPC_INS_ALIAS_MTBR6 = 2313
-PPC_INS_ALIAS_MFBR7 = 2314
-PPC_INS_ALIAS_MTBR7 = 2315
-PPC_INS_ALIAS_MTMSRD = 2316
-PPC_INS_ALIAS_MTMSR = 2317
-PPC_INS_ALIAS_MTPID = 2318
-PPC_INS_ALIAS_MFPID = 2319
-PPC_INS_ALIAS_MFSPRG4 = 2320
-PPC_INS_ALIAS_MTSPRG4 = 2321
-PPC_INS_ALIAS_MFSPRG5 = 2322
-PPC_INS_ALIAS_MTSPRG5 = 2323
-PPC_INS_ALIAS_MFSPRG6 = 2324
-PPC_INS_ALIAS_MTSPRG6 = 2325
-PPC_INS_ALIAS_MFSPRG7 = 2326
-PPC_INS_ALIAS_MTSPRG7 = 2327
-PPC_INS_ALIAS_MTDBATU = 2328
-PPC_INS_ALIAS_MFDBATU = 2329
-PPC_INS_ALIAS_MTDBATL = 2330
-PPC_INS_ALIAS_MFDBATL = 2331
-PPC_INS_ALIAS_MTIBATU = 2332
-PPC_INS_ALIAS_MFIBATU = 2333
-PPC_INS_ALIAS_MTIBATL = 2334
-PPC_INS_ALIAS_MFIBATL = 2335
-PPC_INS_ALIAS_MTPPR = 2336
-PPC_INS_ALIAS_MFPPR = 2337
-PPC_INS_ALIAS_MTESR = 2338
-PPC_INS_ALIAS_MFESR = 2339
-PPC_INS_ALIAS_MTDEAR = 2340
-PPC_INS_ALIAS_MFDEAR = 2341
-PPC_INS_ALIAS_MTTCR = 2342
-PPC_INS_ALIAS_MFTCR = 2343
-PPC_INS_ALIAS_MFTBHI = 2344
-PPC_INS_ALIAS_MTTBHI = 2345
-PPC_INS_ALIAS_MFTBLO = 2346
-PPC_INS_ALIAS_MTTBLO = 2347
-PPC_INS_ALIAS_MTSRR2 = 2348
-PPC_INS_ALIAS_MFSRR2 = 2349
-PPC_INS_ALIAS_MTSRR3 = 2350
-PPC_INS_ALIAS_MFSRR3 = 2351
-PPC_INS_ALIAS_MTDCCR = 2352
-PPC_INS_ALIAS_MFDCCR = 2353
-PPC_INS_ALIAS_MTICCR = 2354
-PPC_INS_ALIAS_MFICCR = 2355
-PPC_INS_ALIAS_TLBIE = 2356
-PPC_INS_ALIAS_TLBREHI = 2357
-PPC_INS_ALIAS_TLBRELO = 2358
-PPC_INS_ALIAS_TLBWEHI = 2359
-PPC_INS_ALIAS_TLBWELO = 2360
-PPC_INS_ALIAS_ROTLDI = 2361
-PPC_INS_ALIAS_ROTLDI_ = 2362
-PPC_INS_ALIAS_ROTLD = 2363
-PPC_INS_ALIAS_ROTLD_ = 2364
-PPC_INS_ALIAS_CLRLDI = 2365
-PPC_INS_ALIAS_CLRLDI_ = 2366
-PPC_INS_ALIAS_LNIA = 2367
-PPC_INS_ALIAS_BCp = 2368
-PPC_INS_ALIAS_BCAp = 2369
-PPC_INS_ALIAS_BCLp = 2370
-PPC_INS_ALIAS_BCLAp = 2371
-PPC_INS_ALIAS_BCm = 2372
-PPC_INS_ALIAS_BCAm = 2373
-PPC_INS_ALIAS_BCLm = 2374
-PPC_INS_ALIAS_BCLAm = 2375
-PPC_INS_ALIAS_BT = 2376
-PPC_INS_ALIAS_BTA = 2377
-PPC_INS_ALIAS_BTLR = 2378
-PPC_INS_ALIAS_BTL = 2379
-PPC_INS_ALIAS_BTLA = 2380
-PPC_INS_ALIAS_BTLRL = 2381
-PPC_INS_ALIAS_BTCTR = 2382
-PPC_INS_ALIAS_BTCTRL = 2383
-PPC_INS_ALIAS_BDZLR = 2384
-PPC_INS_ALIAS_BDZLRL = 2385
-PPC_INS_ALIAS_BDZL = 2386
-PPC_INS_ALIAS_BDZLA = 2387
-PPC_INS_ALIAS_BDZ = 2388
-PPC_INS_ALIAS_BDNZL = 2389
-PPC_INS_ALIAS_BDNZLA = 2390
-PPC_INS_ALIAS_BDNZ = 2391
-PPC_INS_ALIAS_BDZLp = 2392
-PPC_INS_ALIAS_BDZLAp = 2393
-PPC_INS_ALIAS_BDZp = 2394
-PPC_INS_ALIAS_BDNZLp = 2395
-PPC_INS_ALIAS_BDNZLAp = 2396
-PPC_INS_ALIAS_BDNZp = 2397
-PPC_INS_ALIAS_BDZLm = 2398
-PPC_INS_ALIAS_BDZLAm = 2399
-PPC_INS_ALIAS_BDZm = 2400
-PPC_INS_ALIAS_BDNZLm = 2401
-PPC_INS_ALIAS_BDNZLAm = 2402
-PPC_INS_ALIAS_BDNZm = 2403
-PPC_INS_ALIAS_BDNZLR = 2404
-PPC_INS_ALIAS_BDNZLRL = 2405
-PPC_INS_ALIAS_BDZLRp = 2406
-PPC_INS_ALIAS_BDZLRLp = 2407
-PPC_INS_ALIAS_BDNZLRp = 2408
-PPC_INS_ALIAS_BDNZLRLp = 2409
-PPC_INS_ALIAS_BDZLRm = 2410
-PPC_INS_ALIAS_BDZLRLm = 2411
-PPC_INS_ALIAS_BDNZLRm = 2412
-PPC_INS_ALIAS_BDNZLRLm = 2413
-PPC_INS_ALIAS_BF = 2414
-PPC_INS_ALIAS_BFA = 2415
-PPC_INS_ALIAS_BFLR = 2416
-PPC_INS_ALIAS_BFL = 2417
-PPC_INS_ALIAS_BFLA = 2418
-PPC_INS_ALIAS_BFLRL = 2419
-PPC_INS_ALIAS_BFCTR = 2420
-PPC_INS_ALIAS_BFCTRL = 2421
-PPC_INS_ALIAS_BTm = 2422
-PPC_INS_ALIAS_BTAm = 2423
-PPC_INS_ALIAS_BTLRm = 2424
-PPC_INS_ALIAS_BTLm = 2425
-PPC_INS_ALIAS_BTLAm = 2426
-PPC_INS_ALIAS_BTLRLm = 2427
-PPC_INS_ALIAS_BTCTRm = 2428
-PPC_INS_ALIAS_BTCTRLm = 2429
-PPC_INS_ALIAS_BFm = 2430
-PPC_INS_ALIAS_BFAm = 2431
-PPC_INS_ALIAS_BFLRm = 2432
-PPC_INS_ALIAS_BFLm = 2433
-PPC_INS_ALIAS_BFLAm = 2434
-PPC_INS_ALIAS_BFLRLm = 2435
-PPC_INS_ALIAS_BFCTRm = 2436
-PPC_INS_ALIAS_BFCTRLm = 2437
-PPC_INS_ALIAS_BTp = 2438
-PPC_INS_ALIAS_BTAp = 2439
-PPC_INS_ALIAS_BTLRp = 2440
-PPC_INS_ALIAS_BTLp = 2441
-PPC_INS_ALIAS_BTLAp = 2442
-PPC_INS_ALIAS_BTLRLp = 2443
-PPC_INS_ALIAS_BTCTRp = 2444
-PPC_INS_ALIAS_BTCTRLp = 2445
-PPC_INS_ALIAS_BFp = 2446
-PPC_INS_ALIAS_BFAp = 2447
-PPC_INS_ALIAS_BFLRp = 2448
-PPC_INS_ALIAS_BFLp = 2449
-PPC_INS_ALIAS_BFLAp = 2450
-PPC_INS_ALIAS_BFLRLp = 2451
-PPC_INS_ALIAS_BFCTRp = 2452
-PPC_INS_ALIAS_BFCTRLp = 2453
-PPC_INS_ALIAS_BDNZT = 2454
-PPC_INS_ALIAS_BDNZTA = 2455
-PPC_INS_ALIAS_BDNZTLR = 2456
-PPC_INS_ALIAS_BDNZTL = 2457
-PPC_INS_ALIAS_BDNZTLA = 2458
-PPC_INS_ALIAS_BDNZTLRL = 2459
-PPC_INS_ALIAS_BDNZF = 2460
-PPC_INS_ALIAS_BDNZFA = 2461
-PPC_INS_ALIAS_BDNZFLR = 2462
-PPC_INS_ALIAS_BDNZFL = 2463
-PPC_INS_ALIAS_BDNZFLA = 2464
-PPC_INS_ALIAS_BDNZFLRL = 2465
-PPC_INS_ALIAS_BDZT = 2466
-PPC_INS_ALIAS_BDZTA = 2467
-PPC_INS_ALIAS_BDZTLR = 2468
-PPC_INS_ALIAS_BDZTL = 2469
-PPC_INS_ALIAS_BDZTLA = 2470
-PPC_INS_ALIAS_BDZTLRL = 2471
-PPC_INS_ALIAS_BDZF = 2472
-PPC_INS_ALIAS_BDZFA = 2473
-PPC_INS_ALIAS_BDZFLR = 2474
-PPC_INS_ALIAS_BDZFL = 2475
-PPC_INS_ALIAS_BDZFLA = 2476
-PPC_INS_ALIAS_BDZFLRL = 2477
-PPC_INS_ALIAS_B = 2478
-PPC_INS_ALIAS_BA = 2479
-PPC_INS_ALIAS_BL = 2480
-PPC_INS_ALIAS_BLA = 2481
-PPC_INS_ALIAS_BLR = 2482
-PPC_INS_ALIAS_BLRL = 2483
-PPC_INS_ALIAS_BCTR = 2484
-PPC_INS_ALIAS_BCTRL = 2485
-PPC_INS_ALIAS_BLT = 2486
-PPC_INS_ALIAS_BLTA = 2487
-PPC_INS_ALIAS_BLTLR = 2488
-PPC_INS_ALIAS_BLTCTR = 2489
-PPC_INS_ALIAS_BLTL = 2490
-PPC_INS_ALIAS_BLTLA = 2491
-PPC_INS_ALIAS_BLTLRL = 2492
-PPC_INS_ALIAS_BLTCTRL = 2493
-PPC_INS_ALIAS_BLTm = 2494
-PPC_INS_ALIAS_BLTAm = 2495
-PPC_INS_ALIAS_BLTLRm = 2496
-PPC_INS_ALIAS_BLTCTRm = 2497
-PPC_INS_ALIAS_BLTLm = 2498
-PPC_INS_ALIAS_BLTLAm = 2499
-PPC_INS_ALIAS_BLTLRLm = 2500
-PPC_INS_ALIAS_BLTCTRLm = 2501
-PPC_INS_ALIAS_BLTp = 2502
-PPC_INS_ALIAS_BLTAp = 2503
-PPC_INS_ALIAS_BLTLRp = 2504
-PPC_INS_ALIAS_BLTCTRp = 2505
-PPC_INS_ALIAS_BLTLp = 2506
-PPC_INS_ALIAS_BLTLAp = 2507
-PPC_INS_ALIAS_BLTLRLp = 2508
-PPC_INS_ALIAS_BLTCTRLp = 2509
-PPC_INS_ALIAS_BGT = 2510
-PPC_INS_ALIAS_BGTA = 2511
-PPC_INS_ALIAS_BGTLR = 2512
-PPC_INS_ALIAS_BGTCTR = 2513
-PPC_INS_ALIAS_BGTL = 2514
-PPC_INS_ALIAS_BGTLA = 2515
-PPC_INS_ALIAS_BGTLRL = 2516
-PPC_INS_ALIAS_BGTCTRL = 2517
-PPC_INS_ALIAS_BGTm = 2518
-PPC_INS_ALIAS_BGTAm = 2519
-PPC_INS_ALIAS_BGTLRm = 2520
-PPC_INS_ALIAS_BGTCTRm = 2521
-PPC_INS_ALIAS_BGTLm = 2522
-PPC_INS_ALIAS_BGTLAm = 2523
-PPC_INS_ALIAS_BGTLRLm = 2524
-PPC_INS_ALIAS_BGTCTRLm = 2525
-PPC_INS_ALIAS_BGTp = 2526
-PPC_INS_ALIAS_BGTAp = 2527
-PPC_INS_ALIAS_BGTLRp = 2528
-PPC_INS_ALIAS_BGTCTRp = 2529
-PPC_INS_ALIAS_BGTLp = 2530
-PPC_INS_ALIAS_BGTLAp = 2531
-PPC_INS_ALIAS_BGTLRLp = 2532
-PPC_INS_ALIAS_BGTCTRLp = 2533
-PPC_INS_ALIAS_BEQ = 2534
-PPC_INS_ALIAS_BEQA = 2535
-PPC_INS_ALIAS_BEQLR = 2536
-PPC_INS_ALIAS_BEQCTR = 2537
-PPC_INS_ALIAS_BEQL = 2538
-PPC_INS_ALIAS_BEQLA = 2539
-PPC_INS_ALIAS_BEQLRL = 2540
-PPC_INS_ALIAS_BEQCTRL = 2541
-PPC_INS_ALIAS_BEQm = 2542
-PPC_INS_ALIAS_BEQAm = 2543
-PPC_INS_ALIAS_BEQLRm = 2544
-PPC_INS_ALIAS_BEQCTRm = 2545
-PPC_INS_ALIAS_BEQLm = 2546
-PPC_INS_ALIAS_BEQLAm = 2547
-PPC_INS_ALIAS_BEQLRLm = 2548
-PPC_INS_ALIAS_BEQCTRLm = 2549
-PPC_INS_ALIAS_BEQp = 2550
-PPC_INS_ALIAS_BEQAp = 2551
-PPC_INS_ALIAS_BEQLRp = 2552
-PPC_INS_ALIAS_BEQCTRp = 2553
-PPC_INS_ALIAS_BEQLp = 2554
-PPC_INS_ALIAS_BEQLAp = 2555
-PPC_INS_ALIAS_BEQLRLp = 2556
-PPC_INS_ALIAS_BEQCTRLp = 2557
-PPC_INS_ALIAS_BUN = 2558
-PPC_INS_ALIAS_BUNA = 2559
-PPC_INS_ALIAS_BUNLR = 2560
-PPC_INS_ALIAS_BUNCTR = 2561
-PPC_INS_ALIAS_BUNL = 2562
-PPC_INS_ALIAS_BUNLA = 2563
-PPC_INS_ALIAS_BUNLRL = 2564
-PPC_INS_ALIAS_BUNCTRL = 2565
-PPC_INS_ALIAS_BUNm = 2566
-PPC_INS_ALIAS_BUNAm = 2567
-PPC_INS_ALIAS_BUNLRm = 2568
-PPC_INS_ALIAS_BUNCTRm = 2569
-PPC_INS_ALIAS_BUNLm = 2570
-PPC_INS_ALIAS_BUNLAm = 2571
-PPC_INS_ALIAS_BUNLRLm = 2572
-PPC_INS_ALIAS_BUNCTRLm = 2573
-PPC_INS_ALIAS_BUNp = 2574
-PPC_INS_ALIAS_BUNAp = 2575
-PPC_INS_ALIAS_BUNLRp = 2576
-PPC_INS_ALIAS_BUNCTRp = 2577
-PPC_INS_ALIAS_BUNLp = 2578
-PPC_INS_ALIAS_BUNLAp = 2579
-PPC_INS_ALIAS_BUNLRLp = 2580
-PPC_INS_ALIAS_BUNCTRLp = 2581
-PPC_INS_ALIAS_BSO = 2582
-PPC_INS_ALIAS_BSOA = 2583
-PPC_INS_ALIAS_BSOLR = 2584
-PPC_INS_ALIAS_BSOCTR = 2585
-PPC_INS_ALIAS_BSOL = 2586
-PPC_INS_ALIAS_BSOLA = 2587
-PPC_INS_ALIAS_BSOLRL = 2588
-PPC_INS_ALIAS_BSOCTRL = 2589
-PPC_INS_ALIAS_BSOm = 2590
-PPC_INS_ALIAS_BSOAm = 2591
-PPC_INS_ALIAS_BSOLRm = 2592
-PPC_INS_ALIAS_BSOCTRm = 2593
-PPC_INS_ALIAS_BSOLm = 2594
-PPC_INS_ALIAS_BSOLAm = 2595
-PPC_INS_ALIAS_BSOLRLm = 2596
-PPC_INS_ALIAS_BSOCTRLm = 2597
-PPC_INS_ALIAS_BSOp = 2598
-PPC_INS_ALIAS_BSOAp = 2599
-PPC_INS_ALIAS_BSOLRp = 2600
-PPC_INS_ALIAS_BSOCTRp = 2601
-PPC_INS_ALIAS_BSOLp = 2602
-PPC_INS_ALIAS_BSOLAp = 2603
-PPC_INS_ALIAS_BSOLRLp = 2604
-PPC_INS_ALIAS_BSOCTRLp = 2605
-PPC_INS_ALIAS_BGE = 2606
-PPC_INS_ALIAS_BGEA = 2607
-PPC_INS_ALIAS_BGELR = 2608
-PPC_INS_ALIAS_BGECTR = 2609
-PPC_INS_ALIAS_BGEL = 2610
-PPC_INS_ALIAS_BGELA = 2611
-PPC_INS_ALIAS_BGELRL = 2612
-PPC_INS_ALIAS_BGECTRL = 2613
-PPC_INS_ALIAS_BGEm = 2614
-PPC_INS_ALIAS_BGEAm = 2615
-PPC_INS_ALIAS_BGELRm = 2616
-PPC_INS_ALIAS_BGECTRm = 2617
-PPC_INS_ALIAS_BGELm = 2618
-PPC_INS_ALIAS_BGELAm = 2619
-PPC_INS_ALIAS_BGELRLm = 2620
-PPC_INS_ALIAS_BGECTRLm = 2621
-PPC_INS_ALIAS_BGEp = 2622
-PPC_INS_ALIAS_BGEAp = 2623
-PPC_INS_ALIAS_BGELRp = 2624
-PPC_INS_ALIAS_BGECTRp = 2625
-PPC_INS_ALIAS_BGELp = 2626
-PPC_INS_ALIAS_BGELAp = 2627
-PPC_INS_ALIAS_BGELRLp = 2628
-PPC_INS_ALIAS_BGECTRLp = 2629
-PPC_INS_ALIAS_BNL = 2630
-PPC_INS_ALIAS_BNLA = 2631
-PPC_INS_ALIAS_BNLLR = 2632
-PPC_INS_ALIAS_BNLCTR = 2633
-PPC_INS_ALIAS_BNLL = 2634
-PPC_INS_ALIAS_BNLLA = 2635
-PPC_INS_ALIAS_BNLLRL = 2636
-PPC_INS_ALIAS_BNLCTRL = 2637
-PPC_INS_ALIAS_BNLm = 2638
-PPC_INS_ALIAS_BNLAm = 2639
-PPC_INS_ALIAS_BNLLRm = 2640
-PPC_INS_ALIAS_BNLCTRm = 2641
-PPC_INS_ALIAS_BNLLm = 2642
-PPC_INS_ALIAS_BNLLAm = 2643
-PPC_INS_ALIAS_BNLLRLm = 2644
-PPC_INS_ALIAS_BNLCTRLm = 2645
-PPC_INS_ALIAS_BNLp = 2646
-PPC_INS_ALIAS_BNLAp = 2647
-PPC_INS_ALIAS_BNLLRp = 2648
-PPC_INS_ALIAS_BNLCTRp = 2649
-PPC_INS_ALIAS_BNLLp = 2650
-PPC_INS_ALIAS_BNLLAp = 2651
-PPC_INS_ALIAS_BNLLRLp = 2652
-PPC_INS_ALIAS_BNLCTRLp = 2653
-PPC_INS_ALIAS_BLE = 2654
-PPC_INS_ALIAS_BLEA = 2655
-PPC_INS_ALIAS_BLELR = 2656
-PPC_INS_ALIAS_BLECTR = 2657
-PPC_INS_ALIAS_BLEL = 2658
-PPC_INS_ALIAS_BLELA = 2659
-PPC_INS_ALIAS_BLELRL = 2660
-PPC_INS_ALIAS_BLECTRL = 2661
-PPC_INS_ALIAS_BLEm = 2662
-PPC_INS_ALIAS_BLEAm = 2663
-PPC_INS_ALIAS_BLELRm = 2664
-PPC_INS_ALIAS_BLECTRm = 2665
-PPC_INS_ALIAS_BLELm = 2666
-PPC_INS_ALIAS_BLELAm = 2667
-PPC_INS_ALIAS_BLELRLm = 2668
-PPC_INS_ALIAS_BLECTRLm = 2669
-PPC_INS_ALIAS_BLEp = 2670
-PPC_INS_ALIAS_BLEAp = 2671
-PPC_INS_ALIAS_BLELRp = 2672
-PPC_INS_ALIAS_BLECTRp = 2673
-PPC_INS_ALIAS_BLELp = 2674
-PPC_INS_ALIAS_BLELAp = 2675
-PPC_INS_ALIAS_BLELRLp = 2676
-PPC_INS_ALIAS_BLECTRLp = 2677
-PPC_INS_ALIAS_BNG = 2678
-PPC_INS_ALIAS_BNGA = 2679
-PPC_INS_ALIAS_BNGLR = 2680
-PPC_INS_ALIAS_BNGCTR = 2681
-PPC_INS_ALIAS_BNGL = 2682
-PPC_INS_ALIAS_BNGLA = 2683
-PPC_INS_ALIAS_BNGLRL = 2684
-PPC_INS_ALIAS_BNGCTRL = 2685
-PPC_INS_ALIAS_BNGm = 2686
-PPC_INS_ALIAS_BNGAm = 2687
-PPC_INS_ALIAS_BNGLRm = 2688
-PPC_INS_ALIAS_BNGCTRm = 2689
-PPC_INS_ALIAS_BNGLm = 2690
-PPC_INS_ALIAS_BNGLAm = 2691
-PPC_INS_ALIAS_BNGLRLm = 2692
-PPC_INS_ALIAS_BNGCTRLm = 2693
-PPC_INS_ALIAS_BNGp = 2694
-PPC_INS_ALIAS_BNGAp = 2695
-PPC_INS_ALIAS_BNGLRp = 2696
-PPC_INS_ALIAS_BNGCTRp = 2697
-PPC_INS_ALIAS_BNGLp = 2698
-PPC_INS_ALIAS_BNGLAp = 2699
-PPC_INS_ALIAS_BNGLRLp = 2700
-PPC_INS_ALIAS_BNGCTRLp = 2701
-PPC_INS_ALIAS_BNE = 2702
-PPC_INS_ALIAS_BNEA = 2703
-PPC_INS_ALIAS_BNELR = 2704
-PPC_INS_ALIAS_BNECTR = 2705
-PPC_INS_ALIAS_BNEL = 2706
-PPC_INS_ALIAS_BNELA = 2707
-PPC_INS_ALIAS_BNELRL = 2708
-PPC_INS_ALIAS_BNECTRL = 2709
-PPC_INS_ALIAS_BNEm = 2710
-PPC_INS_ALIAS_BNEAm = 2711
-PPC_INS_ALIAS_BNELRm = 2712
-PPC_INS_ALIAS_BNECTRm = 2713
-PPC_INS_ALIAS_BNELm = 2714
-PPC_INS_ALIAS_BNELAm = 2715
-PPC_INS_ALIAS_BNELRLm = 2716
-PPC_INS_ALIAS_BNECTRLm = 2717
-PPC_INS_ALIAS_BNEp = 2718
-PPC_INS_ALIAS_BNEAp = 2719
-PPC_INS_ALIAS_BNELRp = 2720
-PPC_INS_ALIAS_BNECTRp = 2721
-PPC_INS_ALIAS_BNELp = 2722
-PPC_INS_ALIAS_BNELAp = 2723
-PPC_INS_ALIAS_BNELRLp = 2724
-PPC_INS_ALIAS_BNECTRLp = 2725
-PPC_INS_ALIAS_BNU = 2726
-PPC_INS_ALIAS_BNUA = 2727
-PPC_INS_ALIAS_BNULR = 2728
-PPC_INS_ALIAS_BNUCTR = 2729
-PPC_INS_ALIAS_BNUL = 2730
-PPC_INS_ALIAS_BNULA = 2731
-PPC_INS_ALIAS_BNULRL = 2732
-PPC_INS_ALIAS_BNUCTRL = 2733
-PPC_INS_ALIAS_BNUm = 2734
-PPC_INS_ALIAS_BNUAm = 2735
-PPC_INS_ALIAS_BNULRm = 2736
-PPC_INS_ALIAS_BNUCTRm = 2737
-PPC_INS_ALIAS_BNULm = 2738
-PPC_INS_ALIAS_BNULAm = 2739
-PPC_INS_ALIAS_BNULRLm = 2740
-PPC_INS_ALIAS_BNUCTRLm = 2741
-PPC_INS_ALIAS_BNUp = 2742
-PPC_INS_ALIAS_BNUAp = 2743
-PPC_INS_ALIAS_BNULRp = 2744
-PPC_INS_ALIAS_BNUCTRp = 2745
-PPC_INS_ALIAS_BNULp = 2746
-PPC_INS_ALIAS_BNULAp = 2747
-PPC_INS_ALIAS_BNULRLp = 2748
-PPC_INS_ALIAS_BNUCTRLp = 2749
-PPC_INS_ALIAS_BNS = 2750
-PPC_INS_ALIAS_BNSA = 2751
-PPC_INS_ALIAS_BNSLR = 2752
-PPC_INS_ALIAS_BNSCTR = 2753
-PPC_INS_ALIAS_BNSL = 2754
-PPC_INS_ALIAS_BNSLA = 2755
-PPC_INS_ALIAS_BNSLRL = 2756
-PPC_INS_ALIAS_BNSCTRL = 2757
-PPC_INS_ALIAS_BNSm = 2758
-PPC_INS_ALIAS_BNSAm = 2759
-PPC_INS_ALIAS_BNSLRm = 2760
-PPC_INS_ALIAS_BNSCTRm = 2761
-PPC_INS_ALIAS_BNSLm = 2762
-PPC_INS_ALIAS_BNSLAm = 2763
-PPC_INS_ALIAS_BNSLRLm = 2764
-PPC_INS_ALIAS_BNSCTRLm = 2765
-PPC_INS_ALIAS_BNSp = 2766
-PPC_INS_ALIAS_BNSAp = 2767
-PPC_INS_ALIAS_BNSLRp = 2768
-PPC_INS_ALIAS_BNSCTRp = 2769
-PPC_INS_ALIAS_BNSLp = 2770
-PPC_INS_ALIAS_BNSLAp = 2771
-PPC_INS_ALIAS_BNSLRLp = 2772
-PPC_INS_ALIAS_BNSCTRLp = 2773
-PPC_INS_ALIAS_CMPWI = 2774
-PPC_INS_ALIAS_CMPW = 2775
-PPC_INS_ALIAS_CMPLWI = 2776
-PPC_INS_ALIAS_CMPLW = 2777
-PPC_INS_ALIAS_CMPDI = 2778
-PPC_INS_ALIAS_CMPD = 2779
-PPC_INS_ALIAS_CMPLDI = 2780
-PPC_INS_ALIAS_CMPLD = 2781
-PPC_INS_ALIAS_CMPI = 2782
-PPC_INS_ALIAS_CMP = 2783
-PPC_INS_ALIAS_CMPLI = 2784
-PPC_INS_ALIAS_CMPL = 2785
-PPC_INS_ALIAS_TRAP = 2786
-PPC_INS_ALIAS_TDLTI = 2787
-PPC_INS_ALIAS_TDLT = 2788
-PPC_INS_ALIAS_TWLTI = 2789
-PPC_INS_ALIAS_TWLT = 2790
-PPC_INS_ALIAS_TDLEI = 2791
-PPC_INS_ALIAS_TDLE = 2792
-PPC_INS_ALIAS_TWLEI = 2793
-PPC_INS_ALIAS_TWLE = 2794
-PPC_INS_ALIAS_TDEQI = 2795
-PPC_INS_ALIAS_TDEQ = 2796
-PPC_INS_ALIAS_TWEQI = 2797
-PPC_INS_ALIAS_TWEQ = 2798
-PPC_INS_ALIAS_TDGEI = 2799
-PPC_INS_ALIAS_TDGE = 2800
-PPC_INS_ALIAS_TWGEI = 2801
-PPC_INS_ALIAS_TWGE = 2802
-PPC_INS_ALIAS_TDGTI = 2803
-PPC_INS_ALIAS_TDGT = 2804
-PPC_INS_ALIAS_TWGTI = 2805
-PPC_INS_ALIAS_TWGT = 2806
-PPC_INS_ALIAS_TDNLI = 2807
-PPC_INS_ALIAS_TDNL = 2808
-PPC_INS_ALIAS_TWNLI = 2809
-PPC_INS_ALIAS_TWNL = 2810
-PPC_INS_ALIAS_TDNEI = 2811
-PPC_INS_ALIAS_TDNE = 2812
-PPC_INS_ALIAS_TWNEI = 2813
-PPC_INS_ALIAS_TWNE = 2814
-PPC_INS_ALIAS_TDNGI = 2815
-PPC_INS_ALIAS_TDNG = 2816
-PPC_INS_ALIAS_TWNGI = 2817
-PPC_INS_ALIAS_TWNG = 2818
-PPC_INS_ALIAS_TDLLTI = 2819
-PPC_INS_ALIAS_TDLLT = 2820
-PPC_INS_ALIAS_TWLLTI = 2821
-PPC_INS_ALIAS_TWLLT = 2822
-PPC_INS_ALIAS_TDLLEI = 2823
-PPC_INS_ALIAS_TDLLE = 2824
-PPC_INS_ALIAS_TWLLEI = 2825
-PPC_INS_ALIAS_TWLLE = 2826
-PPC_INS_ALIAS_TDLGEI = 2827
-PPC_INS_ALIAS_TDLGE = 2828
-PPC_INS_ALIAS_TWLGEI = 2829
-PPC_INS_ALIAS_TWLGE = 2830
-PPC_INS_ALIAS_TDLGTI = 2831
-PPC_INS_ALIAS_TDLGT = 2832
-PPC_INS_ALIAS_TWLGTI = 2833
-PPC_INS_ALIAS_TWLGT = 2834
-PPC_INS_ALIAS_TDLNLI = 2835
-PPC_INS_ALIAS_TDLNL = 2836
-PPC_INS_ALIAS_TWLNLI = 2837
-PPC_INS_ALIAS_TWLNL = 2838
-PPC_INS_ALIAS_TDLNGI = 2839
-PPC_INS_ALIAS_TDLNG = 2840
-PPC_INS_ALIAS_TWLNGI = 2841
-PPC_INS_ALIAS_TWLNG = 2842
-PPC_INS_ALIAS_TDUI = 2843
-PPC_INS_ALIAS_TDU = 2844
-PPC_INS_ALIAS_TWUI = 2845
-PPC_INS_ALIAS_TWU = 2846
-PPC_INS_ALIAS_PASTE_ = 2847
-PPC_INS_ALIAS_QVFCLR = 2848
-PPC_INS_ALIAS_QVFAND = 2849
-PPC_INS_ALIAS_QVFANDC = 2850
-PPC_INS_ALIAS_QVFCTFB = 2851
-PPC_INS_ALIAS_QVFXOR = 2852
-PPC_INS_ALIAS_QVFOR = 2853
-PPC_INS_ALIAS_QVFNOR = 2854
-PPC_INS_ALIAS_QVFEQU = 2855
-PPC_INS_ALIAS_QVFNOT = 2856
-PPC_INS_ALIAS_QVFORC = 2857
-PPC_INS_ALIAS_QVFNAND = 2858
-PPC_INS_ALIAS_QVFSET = 2859
-PPC_INS_ALIAS_SLWI = 2860
-PPC_INS_ALIAS_SRWI = 2861
-PPC_INS_ALIAS_SLDI = 2862
-PPC_INS_ALIAS_END = 2863
+
+PPC_INS_INVALID = 0
+PPC_INS_CLRLSLDI = 1
+PPC_INS_CLRLSLWI = 2
+PPC_INS_CLRRDI = 3
+PPC_INS_CLRRWI = 4
+PPC_INS_DCBFL = 5
+PPC_INS_DCBFLP = 6
+PPC_INS_DCBFPS = 7
+PPC_INS_DCBF = 8
+PPC_INS_DCBSTPS = 9
+PPC_INS_DCBTCT = 10
+PPC_INS_DCBTDS = 11
+PPC_INS_DCBTSTCT = 12
+PPC_INS_DCBTSTDS = 13
+PPC_INS_DCBTSTT = 14
+PPC_INS_DCBTST = 15
+PPC_INS_DCBTT = 16
+PPC_INS_DCBT = 17
+PPC_INS_EXTLDI = 18
+PPC_INS_EXTLWI = 19
+PPC_INS_EXTRDI = 20
+PPC_INS_EXTRWI = 21
+PPC_INS_INSLWI = 22
+PPC_INS_INSRDI = 23
+PPC_INS_INSRWI = 24
+PPC_INS_LA = 25
+PPC_INS_RLWIMI = 26
+PPC_INS_RLWINM = 27
+PPC_INS_RLWNM = 28
+PPC_INS_ROTRDI = 29
+PPC_INS_ROTRWI = 30
+PPC_INS_SLDI = 31
+PPC_INS_SLWI = 32
+PPC_INS_SRDI = 33
+PPC_INS_SRWI = 34
+PPC_INS_SUBI = 35
+PPC_INS_SUBIC = 36
+PPC_INS_SUBIS = 37
+PPC_INS_SUBPCIS = 38
+PPC_INS_ADD = 39
+PPC_INS_ADDO = 40
+PPC_INS_ADDC = 41
+PPC_INS_ADDCO = 42
+PPC_INS_ADDE = 43
+PPC_INS_ADDEO = 44
+PPC_INS_ADDEX = 45
+PPC_INS_ADDI = 46
+PPC_INS_ADDIC = 47
+PPC_INS_ADDIS = 48
+PPC_INS_ADDME = 49
+PPC_INS_ADDMEO = 50
+PPC_INS_ADDPCIS = 51
+PPC_INS_ADDZE = 52
+PPC_INS_ADDZEO = 53
+PPC_INS_AND = 54
+PPC_INS_ANDC = 55
+PPC_INS_ANDIS = 56
+PPC_INS_ANDI = 57
+PPC_INS_ATTN = 58
+PPC_INS_B = 59
+PPC_INS_BA = 60
+PPC_INS_BCDADD = 61
+PPC_INS_BCDCFN = 62
+PPC_INS_BCDCFSQ = 63
+PPC_INS_BCDCFZ = 64
+PPC_INS_BCDCPSGN = 65
+PPC_INS_BCDCTN = 66
+PPC_INS_BCDCTSQ = 67
+PPC_INS_BCDCTZ = 68
+PPC_INS_BCDSETSGN = 69
+PPC_INS_BCDSR = 70
+PPC_INS_BCDSUB = 71
+PPC_INS_BCDS = 72
+PPC_INS_BCDTRUNC = 73
+PPC_INS_BCDUS = 74
+PPC_INS_BCDUTRUNC = 75
+PPC_INS_BCTR = 76
+PPC_INS_BCTRL = 77
+PPC_INS_BL = 78
+PPC_INS_BLA = 79
+PPC_INS_BLR = 80
+PPC_INS_BLRL = 81
+PPC_INS_BPERMD = 82
+PPC_INS_BRD = 83
+PPC_INS_BRH = 84
+PPC_INS_BRINC = 85
+PPC_INS_BRW = 86
+PPC_INS_CFUGED = 87
+PPC_INS_CLRBHRB = 88
+PPC_INS_CMPB = 89
+PPC_INS_CMPD = 90
+PPC_INS_CMPDI = 91
+PPC_INS_CMPEQB = 92
+PPC_INS_CMPLD = 93
+PPC_INS_CMPLDI = 94
+PPC_INS_CMPLW = 95
+PPC_INS_CMPLWI = 96
+PPC_INS_CMPRB = 97
+PPC_INS_CMPW = 98
+PPC_INS_CMPWI = 99
+PPC_INS_CNTLZD = 100
+PPC_INS_CNTLZDM = 101
+PPC_INS_CNTLZW = 102
+PPC_INS_CNTTZD = 103
+PPC_INS_CNTTZDM = 104
+PPC_INS_CNTTZW = 105
+PPC_INS_CPABORT = 106
+PPC_INS_COPY = 107
+PPC_INS_PASTE = 108
+PPC_INS_CRAND = 109
+PPC_INS_CRANDC = 110
+PPC_INS_CREQV = 111
+PPC_INS_CRNAND = 112
+PPC_INS_CRNOR = 113
+PPC_INS_CROR = 114
+PPC_INS_CRORC = 115
+PPC_INS_CRXOR = 116
+PPC_INS_DARN = 117
+PPC_INS_DCBA = 118
+PPC_INS_DCBFEP = 119
+PPC_INS_DCBI = 120
+PPC_INS_DCBST = 121
+PPC_INS_DCBSTEP = 122
+PPC_INS_DCBTEP = 123
+PPC_INS_DCBTSTEP = 124
+PPC_INS_DCBZ = 125
+PPC_INS_DCBZEP = 126
+PPC_INS_DCBZL = 127
+PPC_INS_DCBZLEP = 128
+PPC_INS_DCCCI = 129
+PPC_INS_DIVD = 130
+PPC_INS_DIVDE = 131
+PPC_INS_DIVDEO = 132
+PPC_INS_DIVDEU = 133
+PPC_INS_DIVDEUO = 134
+PPC_INS_DIVDO = 135
+PPC_INS_DIVDU = 136
+PPC_INS_DIVDUO = 137
+PPC_INS_DIVW = 138
+PPC_INS_DIVWE = 139
+PPC_INS_DIVWEO = 140
+PPC_INS_DIVWEU = 141
+PPC_INS_DIVWEUO = 142
+PPC_INS_DIVWO = 143
+PPC_INS_DIVWU = 144
+PPC_INS_DIVWUO = 145
+PPC_INS_DMMR = 146
+PPC_INS_DMSETDMRZ = 147
+PPC_INS_DMXOR = 148
+PPC_INS_DMXXEXTFDMR256 = 149
+PPC_INS_DMXXEXTFDMR512 = 150
+PPC_INS_DMXXINSTFDMR256 = 151
+PPC_INS_DMXXINSTFDMR512 = 152
+PPC_INS_DSS = 153
+PPC_INS_DSSALL = 154
+PPC_INS_DST = 155
+PPC_INS_DSTST = 156
+PPC_INS_DSTSTT = 157
+PPC_INS_DSTT = 158
+PPC_INS_EFDABS = 159
+PPC_INS_EFDADD = 160
+PPC_INS_EFDCFS = 161
+PPC_INS_EFDCFSF = 162
+PPC_INS_EFDCFSI = 163
+PPC_INS_EFDCFSID = 164
+PPC_INS_EFDCFUF = 165
+PPC_INS_EFDCFUI = 166
+PPC_INS_EFDCFUID = 167
+PPC_INS_EFDCMPEQ = 168
+PPC_INS_EFDCMPGT = 169
+PPC_INS_EFDCMPLT = 170
+PPC_INS_EFDCTSF = 171
+PPC_INS_EFDCTSI = 172
+PPC_INS_EFDCTSIDZ = 173
+PPC_INS_EFDCTSIZ = 174
+PPC_INS_EFDCTUF = 175
+PPC_INS_EFDCTUI = 176
+PPC_INS_EFDCTUIDZ = 177
+PPC_INS_EFDCTUIZ = 178
+PPC_INS_EFDDIV = 179
+PPC_INS_EFDMUL = 180
+PPC_INS_EFDNABS = 181
+PPC_INS_EFDNEG = 182
+PPC_INS_EFDSUB = 183
+PPC_INS_EFDTSTEQ = 184
+PPC_INS_EFDTSTGT = 185
+PPC_INS_EFDTSTLT = 186
+PPC_INS_EFSABS = 187
+PPC_INS_EFSADD = 188
+PPC_INS_EFSCFD = 189
+PPC_INS_EFSCFSF = 190
+PPC_INS_EFSCFSI = 191
+PPC_INS_EFSCFUF = 192
+PPC_INS_EFSCFUI = 193
+PPC_INS_EFSCMPEQ = 194
+PPC_INS_EFSCMPGT = 195
+PPC_INS_EFSCMPLT = 196
+PPC_INS_EFSCTSF = 197
+PPC_INS_EFSCTSI = 198
+PPC_INS_EFSCTSIZ = 199
+PPC_INS_EFSCTUF = 200
+PPC_INS_EFSCTUI = 201
+PPC_INS_EFSCTUIZ = 202
+PPC_INS_EFSDIV = 203
+PPC_INS_EFSMUL = 204
+PPC_INS_EFSNABS = 205
+PPC_INS_EFSNEG = 206
+PPC_INS_EFSSUB = 207
+PPC_INS_EFSTSTEQ = 208
+PPC_INS_EFSTSTGT = 209
+PPC_INS_EFSTSTLT = 210
+PPC_INS_EQV = 211
+PPC_INS_EVABS = 212
+PPC_INS_EVADDIW = 213
+PPC_INS_EVADDSMIAAW = 214
+PPC_INS_EVADDSSIAAW = 215
+PPC_INS_EVADDUMIAAW = 216
+PPC_INS_EVADDUSIAAW = 217
+PPC_INS_EVADDW = 218
+PPC_INS_EVAND = 219
+PPC_INS_EVANDC = 220
+PPC_INS_EVCMPEQ = 221
+PPC_INS_EVCMPGTS = 222
+PPC_INS_EVCMPGTU = 223
+PPC_INS_EVCMPLTS = 224
+PPC_INS_EVCMPLTU = 225
+PPC_INS_EVCNTLSW = 226
+PPC_INS_EVCNTLZW = 227
+PPC_INS_EVDIVWS = 228
+PPC_INS_EVDIVWU = 229
+PPC_INS_EVEQV = 230
+PPC_INS_EVEXTSB = 231
+PPC_INS_EVEXTSH = 232
+PPC_INS_EVFSABS = 233
+PPC_INS_EVFSADD = 234
+PPC_INS_EVFSCFSF = 235
+PPC_INS_EVFSCFSI = 236
+PPC_INS_EVFSCFUF = 237
+PPC_INS_EVFSCFUI = 238
+PPC_INS_EVFSCMPEQ = 239
+PPC_INS_EVFSCMPGT = 240
+PPC_INS_EVFSCMPLT = 241
+PPC_INS_EVFSCTSF = 242
+PPC_INS_EVFSCTSI = 243
+PPC_INS_EVFSCTSIZ = 244
+PPC_INS_EVFSCTUI = 245
+PPC_INS_EVFSDIV = 246
+PPC_INS_EVFSMUL = 247
+PPC_INS_EVFSNABS = 248
+PPC_INS_EVFSNEG = 249
+PPC_INS_EVFSSUB = 250
+PPC_INS_EVFSTSTEQ = 251
+PPC_INS_EVFSTSTGT = 252
+PPC_INS_EVFSTSTLT = 253
+PPC_INS_EVLDD = 254
+PPC_INS_EVLDDX = 255
+PPC_INS_EVLDH = 256
+PPC_INS_EVLDHX = 257
+PPC_INS_EVLDW = 258
+PPC_INS_EVLDWX = 259
+PPC_INS_EVLHHESPLAT = 260
+PPC_INS_EVLHHESPLATX = 261
+PPC_INS_EVLHHOSSPLAT = 262
+PPC_INS_EVLHHOSSPLATX = 263
+PPC_INS_EVLHHOUSPLAT = 264
+PPC_INS_EVLHHOUSPLATX = 265
+PPC_INS_EVLWHE = 266
+PPC_INS_EVLWHEX = 267
+PPC_INS_EVLWHOS = 268
+PPC_INS_EVLWHOSX = 269
+PPC_INS_EVLWHOU = 270
+PPC_INS_EVLWHOUX = 271
+PPC_INS_EVLWHSPLAT = 272
+PPC_INS_EVLWHSPLATX = 273
+PPC_INS_EVLWWSPLAT = 274
+PPC_INS_EVLWWSPLATX = 275
+PPC_INS_EVMERGEHI = 276
+PPC_INS_EVMERGEHILO = 277
+PPC_INS_EVMERGELO = 278
+PPC_INS_EVMERGELOHI = 279
+PPC_INS_EVMHEGSMFAA = 280
+PPC_INS_EVMHEGSMFAN = 281
+PPC_INS_EVMHEGSMIAA = 282
+PPC_INS_EVMHEGSMIAN = 283
+PPC_INS_EVMHEGUMIAA = 284
+PPC_INS_EVMHEGUMIAN = 285
+PPC_INS_EVMHESMF = 286
+PPC_INS_EVMHESMFA = 287
+PPC_INS_EVMHESMFAAW = 288
+PPC_INS_EVMHESMFANW = 289
+PPC_INS_EVMHESMI = 290
+PPC_INS_EVMHESMIA = 291
+PPC_INS_EVMHESMIAAW = 292
+PPC_INS_EVMHESMIANW = 293
+PPC_INS_EVMHESSF = 294
+PPC_INS_EVMHESSFA = 295
+PPC_INS_EVMHESSFAAW = 296
+PPC_INS_EVMHESSFANW = 297
+PPC_INS_EVMHESSIAAW = 298
+PPC_INS_EVMHESSIANW = 299
+PPC_INS_EVMHEUMI = 300
+PPC_INS_EVMHEUMIA = 301
+PPC_INS_EVMHEUMIAAW = 302
+PPC_INS_EVMHEUMIANW = 303
+PPC_INS_EVMHEUSIAAW = 304
+PPC_INS_EVMHEUSIANW = 305
+PPC_INS_EVMHOGSMFAA = 306
+PPC_INS_EVMHOGSMFAN = 307
+PPC_INS_EVMHOGSMIAA = 308
+PPC_INS_EVMHOGSMIAN = 309
+PPC_INS_EVMHOGUMIAA = 310
+PPC_INS_EVMHOGUMIAN = 311
+PPC_INS_EVMHOSMF = 312
+PPC_INS_EVMHOSMFA = 313
+PPC_INS_EVMHOSMFAAW = 314
+PPC_INS_EVMHOSMFANW = 315
+PPC_INS_EVMHOSMI = 316
+PPC_INS_EVMHOSMIA = 317
+PPC_INS_EVMHOSMIAAW = 318
+PPC_INS_EVMHOSMIANW = 319
+PPC_INS_EVMHOSSF = 320
+PPC_INS_EVMHOSSFA = 321
+PPC_INS_EVMHOSSFAAW = 322
+PPC_INS_EVMHOSSFANW = 323
+PPC_INS_EVMHOSSIAAW = 324
+PPC_INS_EVMHOSSIANW = 325
+PPC_INS_EVMHOUMI = 326
+PPC_INS_EVMHOUMIA = 327
+PPC_INS_EVMHOUMIAAW = 328
+PPC_INS_EVMHOUMIANW = 329
+PPC_INS_EVMHOUSIAAW = 330
+PPC_INS_EVMHOUSIANW = 331
+PPC_INS_EVMRA = 332
+PPC_INS_EVMWHSMF = 333
+PPC_INS_EVMWHSMFA = 334
+PPC_INS_EVMWHSMI = 335
+PPC_INS_EVMWHSMIA = 336
+PPC_INS_EVMWHSSF = 337
+PPC_INS_EVMWHSSFA = 338
+PPC_INS_EVMWHUMI = 339
+PPC_INS_EVMWHUMIA = 340
+PPC_INS_EVMWLSMIAAW = 341
+PPC_INS_EVMWLSMIANW = 342
+PPC_INS_EVMWLSSIAAW = 343
+PPC_INS_EVMWLSSIANW = 344
+PPC_INS_EVMWLUMI = 345
+PPC_INS_EVMWLUMIA = 346
+PPC_INS_EVMWLUMIAAW = 347
+PPC_INS_EVMWLUMIANW = 348
+PPC_INS_EVMWLUSIAAW = 349
+PPC_INS_EVMWLUSIANW = 350
+PPC_INS_EVMWSMF = 351
+PPC_INS_EVMWSMFA = 352
+PPC_INS_EVMWSMFAA = 353
+PPC_INS_EVMWSMFAN = 354
+PPC_INS_EVMWSMI = 355
+PPC_INS_EVMWSMIA = 356
+PPC_INS_EVMWSMIAA = 357
+PPC_INS_EVMWSMIAN = 358
+PPC_INS_EVMWSSF = 359
+PPC_INS_EVMWSSFA = 360
+PPC_INS_EVMWSSFAA = 361
+PPC_INS_EVMWSSFAN = 362
+PPC_INS_EVMWUMI = 363
+PPC_INS_EVMWUMIA = 364
+PPC_INS_EVMWUMIAA = 365
+PPC_INS_EVMWUMIAN = 366
+PPC_INS_EVNAND = 367
+PPC_INS_EVNEG = 368
+PPC_INS_EVNOR = 369
+PPC_INS_EVOR = 370
+PPC_INS_EVORC = 371
+PPC_INS_EVRLW = 372
+PPC_INS_EVRLWI = 373
+PPC_INS_EVRNDW = 374
+PPC_INS_EVSEL = 375
+PPC_INS_EVSLW = 376
+PPC_INS_EVSLWI = 377
+PPC_INS_EVSPLATFI = 378
+PPC_INS_EVSPLATI = 379
+PPC_INS_EVSRWIS = 380
+PPC_INS_EVSRWIU = 381
+PPC_INS_EVSRWS = 382
+PPC_INS_EVSRWU = 383
+PPC_INS_EVSTDD = 384
+PPC_INS_EVSTDDX = 385
+PPC_INS_EVSTDH = 386
+PPC_INS_EVSTDHX = 387
+PPC_INS_EVSTDW = 388
+PPC_INS_EVSTDWX = 389
+PPC_INS_EVSTWHE = 390
+PPC_INS_EVSTWHEX = 391
+PPC_INS_EVSTWHO = 392
+PPC_INS_EVSTWHOX = 393
+PPC_INS_EVSTWWE = 394
+PPC_INS_EVSTWWEX = 395
+PPC_INS_EVSTWWO = 396
+PPC_INS_EVSTWWOX = 397
+PPC_INS_EVSUBFSMIAAW = 398
+PPC_INS_EVSUBFSSIAAW = 399
+PPC_INS_EVSUBFUMIAAW = 400
+PPC_INS_EVSUBFUSIAAW = 401
+PPC_INS_EVSUBFW = 402
+PPC_INS_EVSUBIFW = 403
+PPC_INS_EVXOR = 404
+PPC_INS_EXTSB = 405
+PPC_INS_EXTSH = 406
+PPC_INS_EXTSW = 407
+PPC_INS_EXTSWSLI = 408
+PPC_INS_EIEIO = 409
+PPC_INS_FABS = 410
+PPC_INS_FADD = 411
+PPC_INS_FADDS = 412
+PPC_INS_FCFID = 413
+PPC_INS_FCFIDS = 414
+PPC_INS_FCFIDU = 415
+PPC_INS_FCFIDUS = 416
+PPC_INS_FCMPO = 417
+PPC_INS_FCMPU = 418
+PPC_INS_FCPSGN = 419
+PPC_INS_FCTID = 420
+PPC_INS_FCTIDU = 421
+PPC_INS_FCTIDUZ = 422
+PPC_INS_FCTIDZ = 423
+PPC_INS_FCTIW = 424
+PPC_INS_FCTIWU = 425
+PPC_INS_FCTIWUZ = 426
+PPC_INS_FCTIWZ = 427
+PPC_INS_FDIV = 428
+PPC_INS_FDIVS = 429
+PPC_INS_FMADD = 430
+PPC_INS_FMADDS = 431
+PPC_INS_FMR = 432
+PPC_INS_FMSUB = 433
+PPC_INS_FMSUBS = 434
+PPC_INS_FMUL = 435
+PPC_INS_FMULS = 436
+PPC_INS_FNABS = 437
+PPC_INS_FNEG = 438
+PPC_INS_FNMADD = 439
+PPC_INS_FNMADDS = 440
+PPC_INS_FNMSUB = 441
+PPC_INS_FNMSUBS = 442
+PPC_INS_FRE = 443
+PPC_INS_FRES = 444
+PPC_INS_FRIM = 445
+PPC_INS_FRIN = 446
+PPC_INS_FRIP = 447
+PPC_INS_FRIZ = 448
+PPC_INS_FRSP = 449
+PPC_INS_FRSQRTE = 450
+PPC_INS_FRSQRTES = 451
+PPC_INS_FSEL = 452
+PPC_INS_FSQRT = 453
+PPC_INS_FSQRTS = 454
+PPC_INS_FSUB = 455
+PPC_INS_FSUBS = 456
+PPC_INS_FTDIV = 457
+PPC_INS_FTSQRT = 458
+PPC_INS_HASHCHK = 459
+PPC_INS_HASHCHKP = 460
+PPC_INS_HASHST = 461
+PPC_INS_HASHSTP = 462
+PPC_INS_HRFID = 463
+PPC_INS_ICBI = 464
+PPC_INS_ICBIEP = 465
+PPC_INS_ICBLC = 466
+PPC_INS_ICBLQ = 467
+PPC_INS_ICBT = 468
+PPC_INS_ICBTLS = 469
+PPC_INS_ICCCI = 470
+PPC_INS_ISEL = 471
+PPC_INS_ISYNC = 472
+PPC_INS_LBARX = 473
+PPC_INS_LBEPX = 474
+PPC_INS_LBZ = 475
+PPC_INS_LBZCIX = 476
+PPC_INS_LBZU = 477
+PPC_INS_LBZUX = 478
+PPC_INS_LBZX = 479
+PPC_INS_LD = 480
+PPC_INS_LDARX = 481
+PPC_INS_LDAT = 482
+PPC_INS_LDBRX = 483
+PPC_INS_LDCIX = 484
+PPC_INS_LDU = 485
+PPC_INS_LDUX = 486
+PPC_INS_LDX = 487
+PPC_INS_LFD = 488
+PPC_INS_LFDEPX = 489
+PPC_INS_LFDU = 490
+PPC_INS_LFDUX = 491
+PPC_INS_LFDX = 492
+PPC_INS_LFIWAX = 493
+PPC_INS_LFIWZX = 494
+PPC_INS_LFS = 495
+PPC_INS_LFSU = 496
+PPC_INS_LFSUX = 497
+PPC_INS_LFSX = 498
+PPC_INS_LHA = 499
+PPC_INS_LHARX = 500
+PPC_INS_LHAU = 501
+PPC_INS_LHAUX = 502
+PPC_INS_LHAX = 503
+PPC_INS_LHBRX = 504
+PPC_INS_LHEPX = 505
+PPC_INS_LHZ = 506
+PPC_INS_LHZCIX = 507
+PPC_INS_LHZU = 508
+PPC_INS_LHZUX = 509
+PPC_INS_LHZX = 510
+PPC_INS_LMW = 511
+PPC_INS_LQ = 512
+PPC_INS_LQARX = 513
+PPC_INS_LSWI = 514
+PPC_INS_LVEBX = 515
+PPC_INS_LVEHX = 516
+PPC_INS_LVEWX = 517
+PPC_INS_LVSL = 518
+PPC_INS_LVSR = 519
+PPC_INS_LVX = 520
+PPC_INS_LVXL = 521
+PPC_INS_LWA = 522
+PPC_INS_LWARX = 523
+PPC_INS_LWAT = 524
+PPC_INS_LWAUX = 525
+PPC_INS_LWAX = 526
+PPC_INS_LWBRX = 527
+PPC_INS_LWEPX = 528
+PPC_INS_LWZ = 529
+PPC_INS_LWZCIX = 530
+PPC_INS_LWZU = 531
+PPC_INS_LWZUX = 532
+PPC_INS_LWZX = 533
+PPC_INS_LXSD = 534
+PPC_INS_LXSDX = 535
+PPC_INS_LXSIBZX = 536
+PPC_INS_LXSIHZX = 537
+PPC_INS_LXSIWAX = 538
+PPC_INS_LXSIWZX = 539
+PPC_INS_LXSSP = 540
+PPC_INS_LXSSPX = 541
+PPC_INS_LXV = 542
+PPC_INS_LXVB16X = 543
+PPC_INS_LXVD2X = 544
+PPC_INS_LXVDSX = 545
+PPC_INS_LXVH8X = 546
+PPC_INS_LXVKQ = 547
+PPC_INS_LXVL = 548
+PPC_INS_LXVLL = 549
+PPC_INS_LXVP = 550
+PPC_INS_LXVPRL = 551
+PPC_INS_LXVPRLL = 552
+PPC_INS_LXVPX = 553
+PPC_INS_LXVRBX = 554
+PPC_INS_LXVRDX = 555
+PPC_INS_LXVRHX = 556
+PPC_INS_LXVRL = 557
+PPC_INS_LXVRLL = 558
+PPC_INS_LXVRWX = 559
+PPC_INS_LXVW4X = 560
+PPC_INS_LXVWSX = 561
+PPC_INS_LXVX = 562
+PPC_INS_MADDHD = 563
+PPC_INS_MADDHDU = 564
+PPC_INS_MADDLD = 565
+PPC_INS_MBAR = 566
+PPC_INS_MCRF = 567
+PPC_INS_MCRFS = 568
+PPC_INS_MCRXRX = 569
+PPC_INS_MFBHRBE = 570
+PPC_INS_MFCR = 571
+PPC_INS_MFCTR = 572
+PPC_INS_MFDCR = 573
+PPC_INS_MFFS = 574
+PPC_INS_MFFSCDRN = 575
+PPC_INS_MFFSCDRNI = 576
+PPC_INS_MFFSCE = 577
+PPC_INS_MFFSCRN = 578
+PPC_INS_MFFSCRNI = 579
+PPC_INS_MFFSL = 580
+PPC_INS_MFLR = 581
+PPC_INS_MFMSR = 582
+PPC_INS_MFOCRF = 583
+PPC_INS_MFPMR = 584
+PPC_INS_MFSPR = 585
+PPC_INS_MFSR = 586
+PPC_INS_MFSRIN = 587
+PPC_INS_MFTB = 588
+PPC_INS_MFVSCR = 589
+PPC_INS_MFVSRD = 590
+PPC_INS_MFVSRLD = 591
+PPC_INS_MFVSRWZ = 592
+PPC_INS_MODSD = 593
+PPC_INS_MODSW = 594
+PPC_INS_MODUD = 595
+PPC_INS_MODUW = 596
+PPC_INS_MSGSYNC = 597
+PPC_INS_MTCRF = 598
+PPC_INS_MTCTR = 599
+PPC_INS_MTDCR = 600
+PPC_INS_MTFSB0 = 601
+PPC_INS_MTFSB1 = 602
+PPC_INS_MTFSF = 603
+PPC_INS_MTFSFI = 604
+PPC_INS_MTLR = 605
+PPC_INS_MTMSR = 606
+PPC_INS_MTMSRD = 607
+PPC_INS_MTOCRF = 608
+PPC_INS_MTPMR = 609
+PPC_INS_MTSPR = 610
+PPC_INS_MTSR = 611
+PPC_INS_MTSRIN = 612
+PPC_INS_MTVSCR = 613
+PPC_INS_MTVSRBM = 614
+PPC_INS_MTVSRBMI = 615
+PPC_INS_MTVSRD = 616
+PPC_INS_MTVSRDD = 617
+PPC_INS_MTVSRDM = 618
+PPC_INS_MTVSRHM = 619
+PPC_INS_MTVSRQM = 620
+PPC_INS_MTVSRWA = 621
+PPC_INS_MTVSRWM = 622
+PPC_INS_MTVSRWS = 623
+PPC_INS_MTVSRWZ = 624
+PPC_INS_MULHD = 625
+PPC_INS_MULHDU = 626
+PPC_INS_MULHW = 627
+PPC_INS_MULHWU = 628
+PPC_INS_MULLD = 629
+PPC_INS_MULLDO = 630
+PPC_INS_MULLI = 631
+PPC_INS_MULLW = 632
+PPC_INS_MULLWO = 633
+PPC_INS_NAND = 634
+PPC_INS_NAP = 635
+PPC_INS_NEG = 636
+PPC_INS_NEGO = 637
+PPC_INS_NOP = 638
+PPC_INS_NOR = 639
+PPC_INS_OR = 640
+PPC_INS_ORC = 641
+PPC_INS_ORI = 642
+PPC_INS_ORIS = 643
+PPC_INS_PADDI = 644
+PPC_INS_PDEPD = 645
+PPC_INS_PEXTD = 646
+PPC_INS_PLBZ = 647
+PPC_INS_PLD = 648
+PPC_INS_PLFD = 649
+PPC_INS_PLFS = 650
+PPC_INS_PLHA = 651
+PPC_INS_PLHZ = 652
+PPC_INS_PLI = 653
+PPC_INS_PLWA = 654
+PPC_INS_PLWZ = 655
+PPC_INS_PLXSD = 656
+PPC_INS_PLXSSP = 657
+PPC_INS_PLXV = 658
+PPC_INS_PLXVP = 659
+PPC_INS_PMXVBF16GER2 = 660
+PPC_INS_PMXVBF16GER2NN = 661
+PPC_INS_PMXVBF16GER2NP = 662
+PPC_INS_PMXVBF16GER2PN = 663
+PPC_INS_PMXVBF16GER2PP = 664
+PPC_INS_PMXVF16GER2 = 665
+PPC_INS_PMXVF16GER2NN = 666
+PPC_INS_PMXVF16GER2NP = 667
+PPC_INS_PMXVF16GER2PN = 668
+PPC_INS_PMXVF16GER2PP = 669
+PPC_INS_PMXVF32GER = 670
+PPC_INS_PMXVF32GERNN = 671
+PPC_INS_PMXVF32GERNP = 672
+PPC_INS_PMXVF32GERPN = 673
+PPC_INS_PMXVF32GERPP = 674
+PPC_INS_PMXVF64GER = 675
+PPC_INS_PMXVF64GERNN = 676
+PPC_INS_PMXVF64GERNP = 677
+PPC_INS_PMXVF64GERPN = 678
+PPC_INS_PMXVF64GERPP = 679
+PPC_INS_PMXVI16GER2 = 680
+PPC_INS_PMXVI16GER2PP = 681
+PPC_INS_PMXVI16GER2S = 682
+PPC_INS_PMXVI16GER2SPP = 683
+PPC_INS_PMXVI4GER8 = 684
+PPC_INS_PMXVI4GER8PP = 685
+PPC_INS_PMXVI8GER4 = 686
+PPC_INS_PMXVI8GER4PP = 687
+PPC_INS_PMXVI8GER4SPP = 688
+PPC_INS_POPCNTB = 689
+PPC_INS_POPCNTD = 690
+PPC_INS_POPCNTW = 691
+PPC_INS_DCBZ_L = 692
+PPC_INS_PSQ_L = 693
+PPC_INS_PSQ_LU = 694
+PPC_INS_PSQ_LUX = 695
+PPC_INS_PSQ_LX = 696
+PPC_INS_PSQ_ST = 697
+PPC_INS_PSQ_STU = 698
+PPC_INS_PSQ_STUX = 699
+PPC_INS_PSQ_STX = 700
+PPC_INS_PSTB = 701
+PPC_INS_PSTD = 702
+PPC_INS_PSTFD = 703
+PPC_INS_PSTFS = 704
+PPC_INS_PSTH = 705
+PPC_INS_PSTW = 706
+PPC_INS_PSTXSD = 707
+PPC_INS_PSTXSSP = 708
+PPC_INS_PSTXV = 709
+PPC_INS_PSTXVP = 710
+PPC_INS_PS_ABS = 711
+PPC_INS_PS_ADD = 712
+PPC_INS_PS_CMPO0 = 713
+PPC_INS_PS_CMPO1 = 714
+PPC_INS_PS_CMPU0 = 715
+PPC_INS_PS_CMPU1 = 716
+PPC_INS_PS_DIV = 717
+PPC_INS_PS_MADD = 718
+PPC_INS_PS_MADDS0 = 719
+PPC_INS_PS_MADDS1 = 720
+PPC_INS_PS_MERGE00 = 721
+PPC_INS_PS_MERGE01 = 722
+PPC_INS_PS_MERGE10 = 723
+PPC_INS_PS_MERGE11 = 724
+PPC_INS_PS_MR = 725
+PPC_INS_PS_MSUB = 726
+PPC_INS_PS_MUL = 727
+PPC_INS_PS_MULS0 = 728
+PPC_INS_PS_MULS1 = 729
+PPC_INS_PS_NABS = 730
+PPC_INS_PS_NEG = 731
+PPC_INS_PS_NMADD = 732
+PPC_INS_PS_NMSUB = 733
+PPC_INS_PS_RES = 734
+PPC_INS_PS_RSQRTE = 735
+PPC_INS_PS_SEL = 736
+PPC_INS_PS_SUB = 737
+PPC_INS_PS_SUM0 = 738
+PPC_INS_PS_SUM1 = 739
+PPC_INS_QVALIGNI = 740
+PPC_INS_QVESPLATI = 741
+PPC_INS_QVFABS = 742
+PPC_INS_QVFADD = 743
+PPC_INS_QVFADDS = 744
+PPC_INS_QVFCFID = 745
+PPC_INS_QVFCFIDS = 746
+PPC_INS_QVFCFIDU = 747
+PPC_INS_QVFCFIDUS = 748
+PPC_INS_QVFCMPEQ = 749
+PPC_INS_QVFCMPGT = 750
+PPC_INS_QVFCMPLT = 751
+PPC_INS_QVFCPSGN = 752
+PPC_INS_QVFCTID = 753
+PPC_INS_QVFCTIDU = 754
+PPC_INS_QVFCTIDUZ = 755
+PPC_INS_QVFCTIDZ = 756
+PPC_INS_QVFCTIW = 757
+PPC_INS_QVFCTIWU = 758
+PPC_INS_QVFCTIWUZ = 759
+PPC_INS_QVFCTIWZ = 760
+PPC_INS_QVFLOGICAL = 761
+PPC_INS_QVFMADD = 762
+PPC_INS_QVFMADDS = 763
+PPC_INS_QVFMR = 764
+PPC_INS_QVFMSUB = 765
+PPC_INS_QVFMSUBS = 766
+PPC_INS_QVFMUL = 767
+PPC_INS_QVFMULS = 768
+PPC_INS_QVFNABS = 769
+PPC_INS_QVFNEG = 770
+PPC_INS_QVFNMADD = 771
+PPC_INS_QVFNMADDS = 772
+PPC_INS_QVFNMSUB = 773
+PPC_INS_QVFNMSUBS = 774
+PPC_INS_QVFPERM = 775
+PPC_INS_QVFRE = 776
+PPC_INS_QVFRES = 777
+PPC_INS_QVFRIM = 778
+PPC_INS_QVFRIN = 779
+PPC_INS_QVFRIP = 780
+PPC_INS_QVFRIZ = 781
+PPC_INS_QVFRSP = 782
+PPC_INS_QVFRSQRTE = 783
+PPC_INS_QVFRSQRTES = 784
+PPC_INS_QVFSEL = 785
+PPC_INS_QVFSUB = 786
+PPC_INS_QVFSUBS = 787
+PPC_INS_QVFTSTNAN = 788
+PPC_INS_QVFXMADD = 789
+PPC_INS_QVFXMADDS = 790
+PPC_INS_QVFXMUL = 791
+PPC_INS_QVFXMULS = 792
+PPC_INS_QVFXXCPNMADD = 793
+PPC_INS_QVFXXCPNMADDS = 794
+PPC_INS_QVFXXMADD = 795
+PPC_INS_QVFXXMADDS = 796
+PPC_INS_QVFXXNPMADD = 797
+PPC_INS_QVFXXNPMADDS = 798
+PPC_INS_QVGPCI = 799
+PPC_INS_QVLFCDUX = 800
+PPC_INS_QVLFCDUXA = 801
+PPC_INS_QVLFCDX = 802
+PPC_INS_QVLFCDXA = 803
+PPC_INS_QVLFCSUX = 804
+PPC_INS_QVLFCSUXA = 805
+PPC_INS_QVLFCSX = 806
+PPC_INS_QVLFCSXA = 807
+PPC_INS_QVLFDUX = 808
+PPC_INS_QVLFDUXA = 809
+PPC_INS_QVLFDX = 810
+PPC_INS_QVLFDXA = 811
+PPC_INS_QVLFIWAX = 812
+PPC_INS_QVLFIWAXA = 813
+PPC_INS_QVLFIWZX = 814
+PPC_INS_QVLFIWZXA = 815
+PPC_INS_QVLFSUX = 816
+PPC_INS_QVLFSUXA = 817
+PPC_INS_QVLFSX = 818
+PPC_INS_QVLFSXA = 819
+PPC_INS_QVLPCLDX = 820
+PPC_INS_QVLPCLSX = 821
+PPC_INS_QVLPCRDX = 822
+PPC_INS_QVLPCRSX = 823
+PPC_INS_QVSTFCDUX = 824
+PPC_INS_QVSTFCDUXA = 825
+PPC_INS_QVSTFCDUXI = 826
+PPC_INS_QVSTFCDUXIA = 827
+PPC_INS_QVSTFCDX = 828
+PPC_INS_QVSTFCDXA = 829
+PPC_INS_QVSTFCDXI = 830
+PPC_INS_QVSTFCDXIA = 831
+PPC_INS_QVSTFCSUX = 832
+PPC_INS_QVSTFCSUXA = 833
+PPC_INS_QVSTFCSUXI = 834
+PPC_INS_QVSTFCSUXIA = 835
+PPC_INS_QVSTFCSX = 836
+PPC_INS_QVSTFCSXA = 837
+PPC_INS_QVSTFCSXI = 838
+PPC_INS_QVSTFCSXIA = 839
+PPC_INS_QVSTFDUX = 840
+PPC_INS_QVSTFDUXA = 841
+PPC_INS_QVSTFDUXI = 842
+PPC_INS_QVSTFDUXIA = 843
+PPC_INS_QVSTFDX = 844
+PPC_INS_QVSTFDXA = 845
+PPC_INS_QVSTFDXI = 846
+PPC_INS_QVSTFDXIA = 847
+PPC_INS_QVSTFIWX = 848
+PPC_INS_QVSTFIWXA = 849
+PPC_INS_QVSTFSUX = 850
+PPC_INS_QVSTFSUXA = 851
+PPC_INS_QVSTFSUXI = 852
+PPC_INS_QVSTFSUXIA = 853
+PPC_INS_QVSTFSX = 854
+PPC_INS_QVSTFSXA = 855
+PPC_INS_QVSTFSXI = 856
+PPC_INS_QVSTFSXIA = 857
+PPC_INS_RFCI = 858
+PPC_INS_RFDI = 859
+PPC_INS_RFEBB = 860
+PPC_INS_RFI = 861
+PPC_INS_RFID = 862
+PPC_INS_RFMCI = 863
+PPC_INS_RLDCL = 864
+PPC_INS_RLDCR = 865
+PPC_INS_RLDIC = 866
+PPC_INS_RLDICL = 867
+PPC_INS_RLDICR = 868
+PPC_INS_RLDIMI = 869
+PPC_INS_SC = 870
+PPC_INS_SETB = 871
+PPC_INS_SETBC = 872
+PPC_INS_SETBCR = 873
+PPC_INS_SETNBC = 874
+PPC_INS_SETNBCR = 875
+PPC_INS_SLBFEE = 876
+PPC_INS_SLBIA = 877
+PPC_INS_SLBIE = 878
+PPC_INS_SLBIEG = 879
+PPC_INS_SLBMFEE = 880
+PPC_INS_SLBMFEV = 881
+PPC_INS_SLBMTE = 882
+PPC_INS_SLBSYNC = 883
+PPC_INS_SLD = 884
+PPC_INS_SLW = 885
+PPC_INS_STW = 886
+PPC_INS_STWX = 887
+PPC_INS_SRAD = 888
+PPC_INS_SRADI = 889
+PPC_INS_SRAW = 890
+PPC_INS_SRAWI = 891
+PPC_INS_SRD = 892
+PPC_INS_SRW = 893
+PPC_INS_STB = 894
+PPC_INS_STBCIX = 895
+PPC_INS_STBCX = 896
+PPC_INS_STBEPX = 897
+PPC_INS_STBU = 898
+PPC_INS_STBUX = 899
+PPC_INS_STBX = 900
+PPC_INS_STD = 901
+PPC_INS_STDAT = 902
+PPC_INS_STDBRX = 903
+PPC_INS_STDCIX = 904
+PPC_INS_STDCX = 905
+PPC_INS_STDU = 906
+PPC_INS_STDUX = 907
+PPC_INS_STDX = 908
+PPC_INS_STFD = 909
+PPC_INS_STFDEPX = 910
+PPC_INS_STFDU = 911
+PPC_INS_STFDUX = 912
+PPC_INS_STFDX = 913
+PPC_INS_STFIWX = 914
+PPC_INS_STFS = 915
+PPC_INS_STFSU = 916
+PPC_INS_STFSUX = 917
+PPC_INS_STFSX = 918
+PPC_INS_STH = 919
+PPC_INS_STHBRX = 920
+PPC_INS_STHCIX = 921
+PPC_INS_STHCX = 922
+PPC_INS_STHEPX = 923
+PPC_INS_STHU = 924
+PPC_INS_STHUX = 925
+PPC_INS_STHX = 926
+PPC_INS_STMW = 927
+PPC_INS_STOP = 928
+PPC_INS_STQ = 929
+PPC_INS_STQCX = 930
+PPC_INS_STSWI = 931
+PPC_INS_STVEBX = 932
+PPC_INS_STVEHX = 933
+PPC_INS_STVEWX = 934
+PPC_INS_STVX = 935
+PPC_INS_STVXL = 936
+PPC_INS_STWAT = 937
+PPC_INS_STWBRX = 938
+PPC_INS_STWCIX = 939
+PPC_INS_STWCX = 940
+PPC_INS_STWEPX = 941
+PPC_INS_STWU = 942
+PPC_INS_STWUX = 943
+PPC_INS_STXSD = 944
+PPC_INS_STXSDX = 945
+PPC_INS_STXSIBX = 946
+PPC_INS_STXSIHX = 947
+PPC_INS_STXSIWX = 948
+PPC_INS_STXSSP = 949
+PPC_INS_STXSSPX = 950
+PPC_INS_STXV = 951
+PPC_INS_STXVB16X = 952
+PPC_INS_STXVD2X = 953
+PPC_INS_STXVH8X = 954
+PPC_INS_STXVL = 955
+PPC_INS_STXVLL = 956
+PPC_INS_STXVP = 957
+PPC_INS_STXVPRL = 958
+PPC_INS_STXVPRLL = 959
+PPC_INS_STXVPX = 960
+PPC_INS_STXVRBX = 961
+PPC_INS_STXVRDX = 962
+PPC_INS_STXVRHX = 963
+PPC_INS_STXVRL = 964
+PPC_INS_STXVRLL = 965
+PPC_INS_STXVRWX = 966
+PPC_INS_STXVW4X = 967
+PPC_INS_STXVX = 968
+PPC_INS_SUBF = 969
+PPC_INS_SUBFC = 970
+PPC_INS_SUBFCO = 971
+PPC_INS_SUBFE = 972
+PPC_INS_SUBFEO = 973
+PPC_INS_SUBFIC = 974
+PPC_INS_SUBFME = 975
+PPC_INS_SUBFMEO = 976
+PPC_INS_SUBFO = 977
+PPC_INS_SUBFUS = 978
+PPC_INS_SUBFZE = 979
+PPC_INS_SUBFZEO = 980
+PPC_INS_SYNC = 981
+PPC_INS_TABORT = 982
+PPC_INS_TABORTDC = 983
+PPC_INS_TABORTDCI = 984
+PPC_INS_TABORTWC = 985
+PPC_INS_TABORTWCI = 986
+PPC_INS_TBEGIN = 987
+PPC_INS_TCHECK = 988
+PPC_INS_TD = 989
+PPC_INS_TDI = 990
+PPC_INS_TEND = 991
+PPC_INS_TLBIA = 992
+PPC_INS_TLBIE = 993
+PPC_INS_TLBIEL = 994
+PPC_INS_TLBIVAX = 995
+PPC_INS_TLBLD = 996
+PPC_INS_TLBLI = 997
+PPC_INS_TLBRE = 998
+PPC_INS_TLBSX = 999
+PPC_INS_TLBSYNC = 1000
+PPC_INS_TLBWE = 1001
+PPC_INS_TRAP = 1002
+PPC_INS_TRECHKPT = 1003
+PPC_INS_TRECLAIM = 1004
+PPC_INS_TSR = 1005
+PPC_INS_TW = 1006
+PPC_INS_TWI = 1007
+PPC_INS_VABSDUB = 1008
+PPC_INS_VABSDUH = 1009
+PPC_INS_VABSDUW = 1010
+PPC_INS_VADDCUQ = 1011
+PPC_INS_VADDCUW = 1012
+PPC_INS_VADDECUQ = 1013
+PPC_INS_VADDEUQM = 1014
+PPC_INS_VADDFP = 1015
+PPC_INS_VADDSBS = 1016
+PPC_INS_VADDSHS = 1017
+PPC_INS_VADDSWS = 1018
+PPC_INS_VADDUBM = 1019
+PPC_INS_VADDUBS = 1020
+PPC_INS_VADDUDM = 1021
+PPC_INS_VADDUHM = 1022
+PPC_INS_VADDUHS = 1023
+PPC_INS_VADDUQM = 1024
+PPC_INS_VADDUWM = 1025
+PPC_INS_VADDUWS = 1026
+PPC_INS_VAND = 1027
+PPC_INS_VANDC = 1028
+PPC_INS_VAVGSB = 1029
+PPC_INS_VAVGSH = 1030
+PPC_INS_VAVGSW = 1031
+PPC_INS_VAVGUB = 1032
+PPC_INS_VAVGUH = 1033
+PPC_INS_VAVGUW = 1034
+PPC_INS_VBPERMD = 1035
+PPC_INS_VBPERMQ = 1036
+PPC_INS_VCFSX = 1037
+PPC_INS_VCFUGED = 1038
+PPC_INS_VCFUX = 1039
+PPC_INS_VCIPHER = 1040
+PPC_INS_VCIPHERLAST = 1041
+PPC_INS_VCLRLB = 1042
+PPC_INS_VCLRRB = 1043
+PPC_INS_VCLZB = 1044
+PPC_INS_VCLZD = 1045
+PPC_INS_VCLZDM = 1046
+PPC_INS_VCLZH = 1047
+PPC_INS_VCLZLSBB = 1048
+PPC_INS_VCLZW = 1049
+PPC_INS_VCMPBFP = 1050
+PPC_INS_VCMPEQFP = 1051
+PPC_INS_VCMPEQUB = 1052
+PPC_INS_VCMPEQUD = 1053
+PPC_INS_VCMPEQUH = 1054
+PPC_INS_VCMPEQUQ = 1055
+PPC_INS_VCMPEQUW = 1056
+PPC_INS_VCMPGEFP = 1057
+PPC_INS_VCMPGTFP = 1058
+PPC_INS_VCMPGTSB = 1059
+PPC_INS_VCMPGTSD = 1060
+PPC_INS_VCMPGTSH = 1061
+PPC_INS_VCMPGTSQ = 1062
+PPC_INS_VCMPGTSW = 1063
+PPC_INS_VCMPGTUB = 1064
+PPC_INS_VCMPGTUD = 1065
+PPC_INS_VCMPGTUH = 1066
+PPC_INS_VCMPGTUQ = 1067
+PPC_INS_VCMPGTUW = 1068
+PPC_INS_VCMPNEB = 1069
+PPC_INS_VCMPNEH = 1070
+PPC_INS_VCMPNEW = 1071
+PPC_INS_VCMPNEZB = 1072
+PPC_INS_VCMPNEZH = 1073
+PPC_INS_VCMPNEZW = 1074
+PPC_INS_VCMPSQ = 1075
+PPC_INS_VCMPUQ = 1076
+PPC_INS_VCNTMBB = 1077
+PPC_INS_VCNTMBD = 1078
+PPC_INS_VCNTMBH = 1079
+PPC_INS_VCNTMBW = 1080
+PPC_INS_VCTSXS = 1081
+PPC_INS_VCTUXS = 1082
+PPC_INS_VCTZB = 1083
+PPC_INS_VCTZD = 1084
+PPC_INS_VCTZDM = 1085
+PPC_INS_VCTZH = 1086
+PPC_INS_VCTZLSBB = 1087
+PPC_INS_VCTZW = 1088
+PPC_INS_VDIVESD = 1089
+PPC_INS_VDIVESQ = 1090
+PPC_INS_VDIVESW = 1091
+PPC_INS_VDIVEUD = 1092
+PPC_INS_VDIVEUQ = 1093
+PPC_INS_VDIVEUW = 1094
+PPC_INS_VDIVSD = 1095
+PPC_INS_VDIVSQ = 1096
+PPC_INS_VDIVSW = 1097
+PPC_INS_VDIVUD = 1098
+PPC_INS_VDIVUQ = 1099
+PPC_INS_VDIVUW = 1100
+PPC_INS_VEQV = 1101
+PPC_INS_VEXPANDBM = 1102
+PPC_INS_VEXPANDDM = 1103
+PPC_INS_VEXPANDHM = 1104
+PPC_INS_VEXPANDQM = 1105
+PPC_INS_VEXPANDWM = 1106
+PPC_INS_VEXPTEFP = 1107
+PPC_INS_VEXTDDVLX = 1108
+PPC_INS_VEXTDDVRX = 1109
+PPC_INS_VEXTDUBVLX = 1110
+PPC_INS_VEXTDUBVRX = 1111
+PPC_INS_VEXTDUHVLX = 1112
+PPC_INS_VEXTDUHVRX = 1113
+PPC_INS_VEXTDUWVLX = 1114
+PPC_INS_VEXTDUWVRX = 1115
+PPC_INS_VEXTRACTBM = 1116
+PPC_INS_VEXTRACTD = 1117
+PPC_INS_VEXTRACTDM = 1118
+PPC_INS_VEXTRACTHM = 1119
+PPC_INS_VEXTRACTQM = 1120
+PPC_INS_VEXTRACTUB = 1121
+PPC_INS_VEXTRACTUH = 1122
+PPC_INS_VEXTRACTUW = 1123
+PPC_INS_VEXTRACTWM = 1124
+PPC_INS_VEXTSB2D = 1125
+PPC_INS_VEXTSB2W = 1126
+PPC_INS_VEXTSD2Q = 1127
+PPC_INS_VEXTSH2D = 1128
+PPC_INS_VEXTSH2W = 1129
+PPC_INS_VEXTSW2D = 1130
+PPC_INS_VEXTUBLX = 1131
+PPC_INS_VEXTUBRX = 1132
+PPC_INS_VEXTUHLX = 1133
+PPC_INS_VEXTUHRX = 1134
+PPC_INS_VEXTUWLX = 1135
+PPC_INS_VEXTUWRX = 1136
+PPC_INS_VGBBD = 1137
+PPC_INS_VGNB = 1138
+PPC_INS_VINSBLX = 1139
+PPC_INS_VINSBRX = 1140
+PPC_INS_VINSBVLX = 1141
+PPC_INS_VINSBVRX = 1142
+PPC_INS_VINSD = 1143
+PPC_INS_VINSDLX = 1144
+PPC_INS_VINSDRX = 1145
+PPC_INS_VINSERTB = 1146
+PPC_INS_VINSERTD = 1147
+PPC_INS_VINSERTH = 1148
+PPC_INS_VINSERTW = 1149
+PPC_INS_VINSHLX = 1150
+PPC_INS_VINSHRX = 1151
+PPC_INS_VINSHVLX = 1152
+PPC_INS_VINSHVRX = 1153
+PPC_INS_VINSW = 1154
+PPC_INS_VINSWLX = 1155
+PPC_INS_VINSWRX = 1156
+PPC_INS_VINSWVLX = 1157
+PPC_INS_VINSWVRX = 1158
+PPC_INS_VLOGEFP = 1159
+PPC_INS_VMADDFP = 1160
+PPC_INS_VMAXFP = 1161
+PPC_INS_VMAXSB = 1162
+PPC_INS_VMAXSD = 1163
+PPC_INS_VMAXSH = 1164
+PPC_INS_VMAXSW = 1165
+PPC_INS_VMAXUB = 1166
+PPC_INS_VMAXUD = 1167
+PPC_INS_VMAXUH = 1168
+PPC_INS_VMAXUW = 1169
+PPC_INS_VMHADDSHS = 1170
+PPC_INS_VMHRADDSHS = 1171
+PPC_INS_VMINFP = 1172
+PPC_INS_VMINSB = 1173
+PPC_INS_VMINSD = 1174
+PPC_INS_VMINSH = 1175
+PPC_INS_VMINSW = 1176
+PPC_INS_VMINUB = 1177
+PPC_INS_VMINUD = 1178
+PPC_INS_VMINUH = 1179
+PPC_INS_VMINUW = 1180
+PPC_INS_VMLADDUHM = 1181
+PPC_INS_VMODSD = 1182
+PPC_INS_VMODSQ = 1183
+PPC_INS_VMODSW = 1184
+PPC_INS_VMODUD = 1185
+PPC_INS_VMODUQ = 1186
+PPC_INS_VMODUW = 1187
+PPC_INS_VMRGEW = 1188
+PPC_INS_VMRGHB = 1189
+PPC_INS_VMRGHH = 1190
+PPC_INS_VMRGHW = 1191
+PPC_INS_VMRGLB = 1192
+PPC_INS_VMRGLH = 1193
+PPC_INS_VMRGLW = 1194
+PPC_INS_VMRGOW = 1195
+PPC_INS_VMSUMCUD = 1196
+PPC_INS_VMSUMMBM = 1197
+PPC_INS_VMSUMSHM = 1198
+PPC_INS_VMSUMSHS = 1199
+PPC_INS_VMSUMUBM = 1200
+PPC_INS_VMSUMUDM = 1201
+PPC_INS_VMSUMUHM = 1202
+PPC_INS_VMSUMUHS = 1203
+PPC_INS_VMUL10CUQ = 1204
+PPC_INS_VMUL10ECUQ = 1205
+PPC_INS_VMUL10EUQ = 1206
+PPC_INS_VMUL10UQ = 1207
+PPC_INS_VMULESB = 1208
+PPC_INS_VMULESD = 1209
+PPC_INS_VMULESH = 1210
+PPC_INS_VMULESW = 1211
+PPC_INS_VMULEUB = 1212
+PPC_INS_VMULEUD = 1213
+PPC_INS_VMULEUH = 1214
+PPC_INS_VMULEUW = 1215
+PPC_INS_VMULHSD = 1216
+PPC_INS_VMULHSW = 1217
+PPC_INS_VMULHUD = 1218
+PPC_INS_VMULHUW = 1219
+PPC_INS_VMULLD = 1220
+PPC_INS_VMULOSB = 1221
+PPC_INS_VMULOSD = 1222
+PPC_INS_VMULOSH = 1223
+PPC_INS_VMULOSW = 1224
+PPC_INS_VMULOUB = 1225
+PPC_INS_VMULOUD = 1226
+PPC_INS_VMULOUH = 1227
+PPC_INS_VMULOUW = 1228
+PPC_INS_VMULUWM = 1229
+PPC_INS_VNAND = 1230
+PPC_INS_VNCIPHER = 1231
+PPC_INS_VNCIPHERLAST = 1232
+PPC_INS_VNEGD = 1233
+PPC_INS_VNEGW = 1234
+PPC_INS_VNMSUBFP = 1235
+PPC_INS_VNOR = 1236
+PPC_INS_VOR = 1237
+PPC_INS_VORC = 1238
+PPC_INS_VPDEPD = 1239
+PPC_INS_VPERM = 1240
+PPC_INS_VPERMR = 1241
+PPC_INS_VPERMXOR = 1242
+PPC_INS_VPEXTD = 1243
+PPC_INS_VPKPX = 1244
+PPC_INS_VPKSDSS = 1245
+PPC_INS_VPKSDUS = 1246
+PPC_INS_VPKSHSS = 1247
+PPC_INS_VPKSHUS = 1248
+PPC_INS_VPKSWSS = 1249
+PPC_INS_VPKSWUS = 1250
+PPC_INS_VPKUDUM = 1251
+PPC_INS_VPKUDUS = 1252
+PPC_INS_VPKUHUM = 1253
+PPC_INS_VPKUHUS = 1254
+PPC_INS_VPKUWUM = 1255
+PPC_INS_VPKUWUS = 1256
+PPC_INS_VPMSUMB = 1257
+PPC_INS_VPMSUMD = 1258
+PPC_INS_VPMSUMH = 1259
+PPC_INS_VPMSUMW = 1260
+PPC_INS_VPOPCNTB = 1261
+PPC_INS_VPOPCNTD = 1262
+PPC_INS_VPOPCNTH = 1263
+PPC_INS_VPOPCNTW = 1264
+PPC_INS_VPRTYBD = 1265
+PPC_INS_VPRTYBQ = 1266
+PPC_INS_VPRTYBW = 1267
+PPC_INS_VREFP = 1268
+PPC_INS_VRFIM = 1269
+PPC_INS_VRFIN = 1270
+PPC_INS_VRFIP = 1271
+PPC_INS_VRFIZ = 1272
+PPC_INS_VRLB = 1273
+PPC_INS_VRLD = 1274
+PPC_INS_VRLDMI = 1275
+PPC_INS_VRLDNM = 1276
+PPC_INS_VRLH = 1277
+PPC_INS_VRLQ = 1278
+PPC_INS_VRLQMI = 1279
+PPC_INS_VRLQNM = 1280
+PPC_INS_VRLW = 1281
+PPC_INS_VRLWMI = 1282
+PPC_INS_VRLWNM = 1283
+PPC_INS_VRSQRTEFP = 1284
+PPC_INS_VSBOX = 1285
+PPC_INS_VSEL = 1286
+PPC_INS_VSHASIGMAD = 1287
+PPC_INS_VSHASIGMAW = 1288
+PPC_INS_VSL = 1289
+PPC_INS_VSLB = 1290
+PPC_INS_VSLD = 1291
+PPC_INS_VSLDBI = 1292
+PPC_INS_VSLDOI = 1293
+PPC_INS_VSLH = 1294
+PPC_INS_VSLO = 1295
+PPC_INS_VSLQ = 1296
+PPC_INS_VSLV = 1297
+PPC_INS_VSLW = 1298
+PPC_INS_VSPLTB = 1299
+PPC_INS_VSPLTH = 1300
+PPC_INS_VSPLTISB = 1301
+PPC_INS_VSPLTISH = 1302
+PPC_INS_VSPLTISW = 1303
+PPC_INS_VSPLTW = 1304
+PPC_INS_VSR = 1305
+PPC_INS_VSRAB = 1306
+PPC_INS_VSRAD = 1307
+PPC_INS_VSRAH = 1308
+PPC_INS_VSRAQ = 1309
+PPC_INS_VSRAW = 1310
+PPC_INS_VSRB = 1311
+PPC_INS_VSRD = 1312
+PPC_INS_VSRDBI = 1313
+PPC_INS_VSRH = 1314
+PPC_INS_VSRO = 1315
+PPC_INS_VSRQ = 1316
+PPC_INS_VSRV = 1317
+PPC_INS_VSRW = 1318
+PPC_INS_VSTRIBL = 1319
+PPC_INS_VSTRIBR = 1320
+PPC_INS_VSTRIHL = 1321
+PPC_INS_VSTRIHR = 1322
+PPC_INS_VSUBCUQ = 1323
+PPC_INS_VSUBCUW = 1324
+PPC_INS_VSUBECUQ = 1325
+PPC_INS_VSUBEUQM = 1326
+PPC_INS_VSUBFP = 1327
+PPC_INS_VSUBSBS = 1328
+PPC_INS_VSUBSHS = 1329
+PPC_INS_VSUBSWS = 1330
+PPC_INS_VSUBUBM = 1331
+PPC_INS_VSUBUBS = 1332
+PPC_INS_VSUBUDM = 1333
+PPC_INS_VSUBUHM = 1334
+PPC_INS_VSUBUHS = 1335
+PPC_INS_VSUBUQM = 1336
+PPC_INS_VSUBUWM = 1337
+PPC_INS_VSUBUWS = 1338
+PPC_INS_VSUM2SWS = 1339
+PPC_INS_VSUM4SBS = 1340
+PPC_INS_VSUM4SHS = 1341
+PPC_INS_VSUM4UBS = 1342
+PPC_INS_VSUMSWS = 1343
+PPC_INS_VUPKHPX = 1344
+PPC_INS_VUPKHSB = 1345
+PPC_INS_VUPKHSH = 1346
+PPC_INS_VUPKHSW = 1347
+PPC_INS_VUPKLPX = 1348
+PPC_INS_VUPKLSB = 1349
+PPC_INS_VUPKLSH = 1350
+PPC_INS_VUPKLSW = 1351
+PPC_INS_VXOR = 1352
+PPC_INS_WAIT = 1353
+PPC_INS_WRTEE = 1354
+PPC_INS_WRTEEI = 1355
+PPC_INS_XOR = 1356
+PPC_INS_XORI = 1357
+PPC_INS_XORIS = 1358
+PPC_INS_XSABSDP = 1359
+PPC_INS_XSABSQP = 1360
+PPC_INS_XSADDDP = 1361
+PPC_INS_XSADDQP = 1362
+PPC_INS_XSADDQPO = 1363
+PPC_INS_XSADDSP = 1364
+PPC_INS_XSCMPEQDP = 1365
+PPC_INS_XSCMPEQQP = 1366
+PPC_INS_XSCMPEXPDP = 1367
+PPC_INS_XSCMPEXPQP = 1368
+PPC_INS_XSCMPGEDP = 1369
+PPC_INS_XSCMPGEQP = 1370
+PPC_INS_XSCMPGTDP = 1371
+PPC_INS_XSCMPGTQP = 1372
+PPC_INS_XSCMPODP = 1373
+PPC_INS_XSCMPOQP = 1374
+PPC_INS_XSCMPUDP = 1375
+PPC_INS_XSCMPUQP = 1376
+PPC_INS_XSCPSGNDP = 1377
+PPC_INS_XSCPSGNQP = 1378
+PPC_INS_XSCVDPHP = 1379
+PPC_INS_XSCVDPQP = 1380
+PPC_INS_XSCVDPSP = 1381
+PPC_INS_XSCVDPSPN = 1382
+PPC_INS_XSCVDPSXDS = 1383
+PPC_INS_XSCVDPSXWS = 1384
+PPC_INS_XSCVDPUXDS = 1385
+PPC_INS_XSCVDPUXWS = 1386
+PPC_INS_XSCVHPDP = 1387
+PPC_INS_XSCVQPDP = 1388
+PPC_INS_XSCVQPDPO = 1389
+PPC_INS_XSCVQPSDZ = 1390
+PPC_INS_XSCVQPSQZ = 1391
+PPC_INS_XSCVQPSWZ = 1392
+PPC_INS_XSCVQPUDZ = 1393
+PPC_INS_XSCVQPUQZ = 1394
+PPC_INS_XSCVQPUWZ = 1395
+PPC_INS_XSCVSDQP = 1396
+PPC_INS_XSCVSPDP = 1397
+PPC_INS_XSCVSPDPN = 1398
+PPC_INS_XSCVSQQP = 1399
+PPC_INS_XSCVSXDDP = 1400
+PPC_INS_XSCVSXDSP = 1401
+PPC_INS_XSCVUDQP = 1402
+PPC_INS_XSCVUQQP = 1403
+PPC_INS_XSCVUXDDP = 1404
+PPC_INS_XSCVUXDSP = 1405
+PPC_INS_XSDIVDP = 1406
+PPC_INS_XSDIVQP = 1407
+PPC_INS_XSDIVQPO = 1408
+PPC_INS_XSDIVSP = 1409
+PPC_INS_XSIEXPDP = 1410
+PPC_INS_XSIEXPQP = 1411
+PPC_INS_XSMADDADP = 1412
+PPC_INS_XSMADDASP = 1413
+PPC_INS_XSMADDMDP = 1414
+PPC_INS_XSMADDMSP = 1415
+PPC_INS_XSMADDQP = 1416
+PPC_INS_XSMADDQPO = 1417
+PPC_INS_XSMAXCDP = 1418
+PPC_INS_XSMAXCQP = 1419
+PPC_INS_XSMAXDP = 1420
+PPC_INS_XSMAXJDP = 1421
+PPC_INS_XSMINCDP = 1422
+PPC_INS_XSMINCQP = 1423
+PPC_INS_XSMINDP = 1424
+PPC_INS_XSMINJDP = 1425
+PPC_INS_XSMSUBADP = 1426
+PPC_INS_XSMSUBASP = 1427
+PPC_INS_XSMSUBMDP = 1428
+PPC_INS_XSMSUBMSP = 1429
+PPC_INS_XSMSUBQP = 1430
+PPC_INS_XSMSUBQPO = 1431
+PPC_INS_XSMULDP = 1432
+PPC_INS_XSMULQP = 1433
+PPC_INS_XSMULQPO = 1434
+PPC_INS_XSMULSP = 1435
+PPC_INS_XSNABSDP = 1436
+PPC_INS_XSNABSQP = 1437
+PPC_INS_XSNEGDP = 1438
+PPC_INS_XSNEGQP = 1439
+PPC_INS_XSNMADDADP = 1440
+PPC_INS_XSNMADDASP = 1441
+PPC_INS_XSNMADDMDP = 1442
+PPC_INS_XSNMADDMSP = 1443
+PPC_INS_XSNMADDQP = 1444
+PPC_INS_XSNMADDQPO = 1445
+PPC_INS_XSNMSUBADP = 1446
+PPC_INS_XSNMSUBASP = 1447
+PPC_INS_XSNMSUBMDP = 1448
+PPC_INS_XSNMSUBMSP = 1449
+PPC_INS_XSNMSUBQP = 1450
+PPC_INS_XSNMSUBQPO = 1451
+PPC_INS_XSRDPI = 1452
+PPC_INS_XSRDPIC = 1453
+PPC_INS_XSRDPIM = 1454
+PPC_INS_XSRDPIP = 1455
+PPC_INS_XSRDPIZ = 1456
+PPC_INS_XSREDP = 1457
+PPC_INS_XSRESP = 1458
+PPC_INS_XSRQPI = 1459
+PPC_INS_XSRQPIX = 1460
+PPC_INS_XSRQPXP = 1461
+PPC_INS_XSRSP = 1462
+PPC_INS_XSRSQRTEDP = 1463
+PPC_INS_XSRSQRTESP = 1464
+PPC_INS_XSSQRTDP = 1465
+PPC_INS_XSSQRTQP = 1466
+PPC_INS_XSSQRTQPO = 1467
+PPC_INS_XSSQRTSP = 1468
+PPC_INS_XSSUBDP = 1469
+PPC_INS_XSSUBQP = 1470
+PPC_INS_XSSUBQPO = 1471
+PPC_INS_XSSUBSP = 1472
+PPC_INS_XSTDIVDP = 1473
+PPC_INS_XSTSQRTDP = 1474
+PPC_INS_XSTSTDCDP = 1475
+PPC_INS_XSTSTDCQP = 1476
+PPC_INS_XSTSTDCSP = 1477
+PPC_INS_XSXEXPDP = 1478
+PPC_INS_XSXEXPQP = 1479
+PPC_INS_XSXSIGDP = 1480
+PPC_INS_XSXSIGQP = 1481
+PPC_INS_XVABSDP = 1482
+PPC_INS_XVABSSP = 1483
+PPC_INS_XVADDDP = 1484
+PPC_INS_XVADDSP = 1485
+PPC_INS_XVBF16GER2 = 1486
+PPC_INS_XVBF16GER2NN = 1487
+PPC_INS_XVBF16GER2NP = 1488
+PPC_INS_XVBF16GER2PN = 1489
+PPC_INS_XVBF16GER2PP = 1490
+PPC_INS_XVCMPEQDP = 1491
+PPC_INS_XVCMPEQSP = 1492
+PPC_INS_XVCMPGEDP = 1493
+PPC_INS_XVCMPGESP = 1494
+PPC_INS_XVCMPGTDP = 1495
+PPC_INS_XVCMPGTSP = 1496
+PPC_INS_XVCPSGNDP = 1497
+PPC_INS_XVCPSGNSP = 1498
+PPC_INS_XVCVBF16SPN = 1499
+PPC_INS_XVCVDPSP = 1500
+PPC_INS_XVCVDPSXDS = 1501
+PPC_INS_XVCVDPSXWS = 1502
+PPC_INS_XVCVDPUXDS = 1503
+PPC_INS_XVCVDPUXWS = 1504
+PPC_INS_XVCVHPSP = 1505
+PPC_INS_XVCVSPBF16 = 1506
+PPC_INS_XVCVSPDP = 1507
+PPC_INS_XVCVSPHP = 1508
+PPC_INS_XVCVSPSXDS = 1509
+PPC_INS_XVCVSPSXWS = 1510
+PPC_INS_XVCVSPUXDS = 1511
+PPC_INS_XVCVSPUXWS = 1512
+PPC_INS_XVCVSXDDP = 1513
+PPC_INS_XVCVSXDSP = 1514
+PPC_INS_XVCVSXWDP = 1515
+PPC_INS_XVCVSXWSP = 1516
+PPC_INS_XVCVUXDDP = 1517
+PPC_INS_XVCVUXDSP = 1518
+PPC_INS_XVCVUXWDP = 1519
+PPC_INS_XVCVUXWSP = 1520
+PPC_INS_XVDIVDP = 1521
+PPC_INS_XVDIVSP = 1522
+PPC_INS_XVF16GER2 = 1523
+PPC_INS_XVF16GER2NN = 1524
+PPC_INS_XVF16GER2NP = 1525
+PPC_INS_XVF16GER2PN = 1526
+PPC_INS_XVF16GER2PP = 1527
+PPC_INS_XVF32GER = 1528
+PPC_INS_XVF32GERNN = 1529
+PPC_INS_XVF32GERNP = 1530
+PPC_INS_XVF32GERPN = 1531
+PPC_INS_XVF32GERPP = 1532
+PPC_INS_XVF64GER = 1533
+PPC_INS_XVF64GERNN = 1534
+PPC_INS_XVF64GERNP = 1535
+PPC_INS_XVF64GERPN = 1536
+PPC_INS_XVF64GERPP = 1537
+PPC_INS_XVI16GER2 = 1538
+PPC_INS_XVI16GER2PP = 1539
+PPC_INS_XVI16GER2S = 1540
+PPC_INS_XVI16GER2SPP = 1541
+PPC_INS_XVI4GER8 = 1542
+PPC_INS_XVI4GER8PP = 1543
+PPC_INS_XVI8GER4 = 1544
+PPC_INS_XVI8GER4PP = 1545
+PPC_INS_XVI8GER4SPP = 1546
+PPC_INS_XVIEXPDP = 1547
+PPC_INS_XVIEXPSP = 1548
+PPC_INS_XVMADDADP = 1549
+PPC_INS_XVMADDASP = 1550
+PPC_INS_XVMADDMDP = 1551
+PPC_INS_XVMADDMSP = 1552
+PPC_INS_XVMAXDP = 1553
+PPC_INS_XVMAXSP = 1554
+PPC_INS_XVMINDP = 1555
+PPC_INS_XVMINSP = 1556
+PPC_INS_XVMSUBADP = 1557
+PPC_INS_XVMSUBASP = 1558
+PPC_INS_XVMSUBMDP = 1559
+PPC_INS_XVMSUBMSP = 1560
+PPC_INS_XVMULDP = 1561
+PPC_INS_XVMULSP = 1562
+PPC_INS_XVNABSDP = 1563
+PPC_INS_XVNABSSP = 1564
+PPC_INS_XVNEGDP = 1565
+PPC_INS_XVNEGSP = 1566
+PPC_INS_XVNMADDADP = 1567
+PPC_INS_XVNMADDASP = 1568
+PPC_INS_XVNMADDMDP = 1569
+PPC_INS_XVNMADDMSP = 1570
+PPC_INS_XVNMSUBADP = 1571
+PPC_INS_XVNMSUBASP = 1572
+PPC_INS_XVNMSUBMDP = 1573
+PPC_INS_XVNMSUBMSP = 1574
+PPC_INS_XVRDPI = 1575
+PPC_INS_XVRDPIC = 1576
+PPC_INS_XVRDPIM = 1577
+PPC_INS_XVRDPIP = 1578
+PPC_INS_XVRDPIZ = 1579
+PPC_INS_XVREDP = 1580
+PPC_INS_XVRESP = 1581
+PPC_INS_XVRSPI = 1582
+PPC_INS_XVRSPIC = 1583
+PPC_INS_XVRSPIM = 1584
+PPC_INS_XVRSPIP = 1585
+PPC_INS_XVRSPIZ = 1586
+PPC_INS_XVRSQRTEDP = 1587
+PPC_INS_XVRSQRTESP = 1588
+PPC_INS_XVSQRTDP = 1589
+PPC_INS_XVSQRTSP = 1590
+PPC_INS_XVSUBDP = 1591
+PPC_INS_XVSUBSP = 1592
+PPC_INS_XVTDIVDP = 1593
+PPC_INS_XVTDIVSP = 1594
+PPC_INS_XVTLSBB = 1595
+PPC_INS_XVTSQRTDP = 1596
+PPC_INS_XVTSQRTSP = 1597
+PPC_INS_XVTSTDCDP = 1598
+PPC_INS_XVTSTDCSP = 1599
+PPC_INS_XVXEXPDP = 1600
+PPC_INS_XVXEXPSP = 1601
+PPC_INS_XVXSIGDP = 1602
+PPC_INS_XVXSIGSP = 1603
+PPC_INS_XXBLENDVB = 1604
+PPC_INS_XXBLENDVD = 1605
+PPC_INS_XXBLENDVH = 1606
+PPC_INS_XXBLENDVW = 1607
+PPC_INS_XXBRD = 1608
+PPC_INS_XXBRH = 1609
+PPC_INS_XXBRQ = 1610
+PPC_INS_XXBRW = 1611
+PPC_INS_XXEVAL = 1612
+PPC_INS_XXEXTRACTUW = 1613
+PPC_INS_XXGENPCVBM = 1614
+PPC_INS_XXGENPCVDM = 1615
+PPC_INS_XXGENPCVHM = 1616
+PPC_INS_XXGENPCVWM = 1617
+PPC_INS_XXINSERTW = 1618
+PPC_INS_XXLAND = 1619
+PPC_INS_XXLANDC = 1620
+PPC_INS_XXLEQV = 1621
+PPC_INS_XXLNAND = 1622
+PPC_INS_XXLNOR = 1623
+PPC_INS_XXLOR = 1624
+PPC_INS_XXLORC = 1625
+PPC_INS_XXLXOR = 1626
+PPC_INS_XXMFACC = 1627
+PPC_INS_XXMRGHW = 1628
+PPC_INS_XXMRGLW = 1629
+PPC_INS_XXMTACC = 1630
+PPC_INS_XXPERM = 1631
+PPC_INS_XXPERMDI = 1632
+PPC_INS_XXPERMR = 1633
+PPC_INS_XXPERMX = 1634
+PPC_INS_XXSEL = 1635
+PPC_INS_XXSETACCZ = 1636
+PPC_INS_XXSLDWI = 1637
+PPC_INS_XXSPLTI32DX = 1638
+PPC_INS_XXSPLTIB = 1639
+PPC_INS_XXSPLTIDP = 1640
+PPC_INS_XXSPLTIW = 1641
+PPC_INS_XXSPLTW = 1642
+PPC_INS_BC = 1643
+PPC_INS_BCA = 1644
+PPC_INS_BCCTR = 1645
+PPC_INS_BCCTRL = 1646
+PPC_INS_BCL = 1647
+PPC_INS_BCLA = 1648
+PPC_INS_BCLR = 1649
+PPC_INS_BCLRL = 1650
+PPC_INS_ENDING = 1651
+PPC_INS_ALIAS_BEGIN = 1652
+PPC_INS_ALIAS_RFEBB = 1653
+PPC_INS_ALIAS_LI = 1654
+PPC_INS_ALIAS_LIS = 1655
+PPC_INS_ALIAS_MR = 1656
+PPC_INS_ALIAS_MR_ = 1657
+PPC_INS_ALIAS_NOT = 1658
+PPC_INS_ALIAS_NOT_ = 1659
+PPC_INS_ALIAS_NOP = 1660
+PPC_INS_ALIAS_MTUDSCR = 1661
+PPC_INS_ALIAS_MFUDSCR = 1662
+PPC_INS_ALIAS_MTVRSAVE = 1663
+PPC_INS_ALIAS_MFVRSAVE = 1664
+PPC_INS_ALIAS_MTCR = 1665
+PPC_INS_ALIAS_SUB = 1666
+PPC_INS_ALIAS_SUB_ = 1667
+PPC_INS_ALIAS_SUBC = 1668
+PPC_INS_ALIAS_SUBC_ = 1669
+PPC_INS_ALIAS_VMR = 1670
+PPC_INS_ALIAS_VNOT = 1671
+PPC_INS_ALIAS_ROTLWI = 1672
+PPC_INS_ALIAS_ROTLWI_ = 1673
+PPC_INS_ALIAS_ROTLW = 1674
+PPC_INS_ALIAS_ROTLW_ = 1675
+PPC_INS_ALIAS_CLRLWI = 1676
+PPC_INS_ALIAS_CLRLWI_ = 1677
+PPC_INS_ALIAS_ISELLT = 1678
+PPC_INS_ALIAS_ISELGT = 1679
+PPC_INS_ALIAS_ISELEQ = 1680
+PPC_INS_ALIAS_XNOP = 1681
+PPC_INS_ALIAS_CNTLZW = 1682
+PPC_INS_ALIAS_CNTLZW_ = 1683
+PPC_INS_ALIAS_MTXER = 1684
+PPC_INS_ALIAS_MFXER = 1685
+PPC_INS_ALIAS_MFRTCU = 1686
+PPC_INS_ALIAS_MFRTCL = 1687
+PPC_INS_ALIAS_MTLR = 1688
+PPC_INS_ALIAS_MFLR = 1689
+PPC_INS_ALIAS_MTCTR = 1690
+PPC_INS_ALIAS_MFCTR = 1691
+PPC_INS_ALIAS_MTUAMR = 1692
+PPC_INS_ALIAS_MFUAMR = 1693
+PPC_INS_ALIAS_MTDSCR = 1694
+PPC_INS_ALIAS_MFDSCR = 1695
+PPC_INS_ALIAS_MTDSISR = 1696
+PPC_INS_ALIAS_MFDSISR = 1697
+PPC_INS_ALIAS_MTDAR = 1698
+PPC_INS_ALIAS_MFDAR = 1699
+PPC_INS_ALIAS_MTDEC = 1700
+PPC_INS_ALIAS_MFDEC = 1701
+PPC_INS_ALIAS_MTSDR1 = 1702
+PPC_INS_ALIAS_MFSDR1 = 1703
+PPC_INS_ALIAS_MTSRR0 = 1704
+PPC_INS_ALIAS_MFSRR0 = 1705
+PPC_INS_ALIAS_MTSRR1 = 1706
+PPC_INS_ALIAS_MFSRR1 = 1707
+PPC_INS_ALIAS_MTCFAR = 1708
+PPC_INS_ALIAS_MFCFAR = 1709
+PPC_INS_ALIAS_MTAMR = 1710
+PPC_INS_ALIAS_MFAMR = 1711
+PPC_INS_ALIAS_MFSPRG = 1712
+PPC_INS_ALIAS_MFSPRG0 = 1713
+PPC_INS_ALIAS_MTSPRG = 1714
+PPC_INS_ALIAS_MTSPRG0 = 1715
+PPC_INS_ALIAS_MFSPRG1 = 1716
+PPC_INS_ALIAS_MTSPRG1 = 1717
+PPC_INS_ALIAS_MFSPRG2 = 1718
+PPC_INS_ALIAS_MTSPRG2 = 1719
+PPC_INS_ALIAS_MFSPRG3 = 1720
+PPC_INS_ALIAS_MTSPRG3 = 1721
+PPC_INS_ALIAS_MFASR = 1722
+PPC_INS_ALIAS_MTASR = 1723
+PPC_INS_ALIAS_MTTBL = 1724
+PPC_INS_ALIAS_MTTBU = 1725
+PPC_INS_ALIAS_MFPVR = 1726
+PPC_INS_ALIAS_MFSPEFSCR = 1727
+PPC_INS_ALIAS_MTSPEFSCR = 1728
+PPC_INS_ALIAS_XVMOVDP = 1729
+PPC_INS_ALIAS_XVMOVSP = 1730
+PPC_INS_ALIAS_XXSPLTD = 1731
+PPC_INS_ALIAS_XXMRGHD = 1732
+PPC_INS_ALIAS_XXMRGLD = 1733
+PPC_INS_ALIAS_XXSWAPD = 1734
+PPC_INS_ALIAS_MFFPRD = 1735
+PPC_INS_ALIAS_MTFPRD = 1736
+PPC_INS_ALIAS_MFFPRWZ = 1737
+PPC_INS_ALIAS_MTFPRWA = 1738
+PPC_INS_ALIAS_MTFPRWZ = 1739
+PPC_INS_ALIAS_TEND_ = 1740
+PPC_INS_ALIAS_TENDALL_ = 1741
+PPC_INS_ALIAS_TSUSPEND_ = 1742
+PPC_INS_ALIAS_TRESUME_ = 1743
+PPC_INS_ALIAS_DCI = 1744
+PPC_INS_ALIAS_DCCCI = 1745
+PPC_INS_ALIAS_ICI = 1746
+PPC_INS_ALIAS_ICCCI = 1747
+PPC_INS_ALIAS_MTFSFI = 1748
+PPC_INS_ALIAS_MTFSFI_ = 1749
+PPC_INS_ALIAS_MTFSF = 1750
+PPC_INS_ALIAS_MTFSF_ = 1751
+PPC_INS_ALIAS_SC = 1752
+PPC_INS_ALIAS_SYNC = 1753
+PPC_INS_ALIAS_LWSYNC = 1754
+PPC_INS_ALIAS_PTESYNC = 1755
+PPC_INS_ALIAS_WAIT = 1756
+PPC_INS_ALIAS_WAITRSV = 1757
+PPC_INS_ALIAS_WAITIMPL = 1758
+PPC_INS_ALIAS_MBAR = 1759
+PPC_INS_ALIAS_CRSET = 1760
+PPC_INS_ALIAS_CRCLR = 1761
+PPC_INS_ALIAS_CRMOVE = 1762
+PPC_INS_ALIAS_CRNOT = 1763
+PPC_INS_ALIAS_MFTB = 1764
+PPC_INS_ALIAS_MFTBL = 1765
+PPC_INS_ALIAS_MFTBU = 1766
+PPC_INS_ALIAS_MFBR0 = 1767
+PPC_INS_ALIAS_MTBR0 = 1768
+PPC_INS_ALIAS_MFBR1 = 1769
+PPC_INS_ALIAS_MTBR1 = 1770
+PPC_INS_ALIAS_MFBR2 = 1771
+PPC_INS_ALIAS_MTBR2 = 1772
+PPC_INS_ALIAS_MFBR3 = 1773
+PPC_INS_ALIAS_MTBR3 = 1774
+PPC_INS_ALIAS_MFBR4 = 1775
+PPC_INS_ALIAS_MTBR4 = 1776
+PPC_INS_ALIAS_MFBR5 = 1777
+PPC_INS_ALIAS_MTBR5 = 1778
+PPC_INS_ALIAS_MFBR6 = 1779
+PPC_INS_ALIAS_MTBR6 = 1780
+PPC_INS_ALIAS_MFBR7 = 1781
+PPC_INS_ALIAS_MTBR7 = 1782
+PPC_INS_ALIAS_MTMSRD = 1783
+PPC_INS_ALIAS_MTMSR = 1784
+PPC_INS_ALIAS_MTPID = 1785
+PPC_INS_ALIAS_MFPID = 1786
+PPC_INS_ALIAS_MFSPRG4 = 1787
+PPC_INS_ALIAS_MTSPRG4 = 1788
+PPC_INS_ALIAS_MFSPRG5 = 1789
+PPC_INS_ALIAS_MTSPRG5 = 1790
+PPC_INS_ALIAS_MFSPRG6 = 1791
+PPC_INS_ALIAS_MTSPRG6 = 1792
+PPC_INS_ALIAS_MFSPRG7 = 1793
+PPC_INS_ALIAS_MTSPRG7 = 1794
+PPC_INS_ALIAS_MTDBATU = 1795
+PPC_INS_ALIAS_MFDBATU = 1796
+PPC_INS_ALIAS_MTDBATL = 1797
+PPC_INS_ALIAS_MFDBATL = 1798
+PPC_INS_ALIAS_MTIBATU = 1799
+PPC_INS_ALIAS_MFIBATU = 1800
+PPC_INS_ALIAS_MTIBATL = 1801
+PPC_INS_ALIAS_MFIBATL = 1802
+PPC_INS_ALIAS_MTPPR = 1803
+PPC_INS_ALIAS_MFPPR = 1804
+PPC_INS_ALIAS_MTESR = 1805
+PPC_INS_ALIAS_MFESR = 1806
+PPC_INS_ALIAS_MTDEAR = 1807
+PPC_INS_ALIAS_MFDEAR = 1808
+PPC_INS_ALIAS_MTTCR = 1809
+PPC_INS_ALIAS_MFTCR = 1810
+PPC_INS_ALIAS_MFTBHI = 1811
+PPC_INS_ALIAS_MTTBHI = 1812
+PPC_INS_ALIAS_MFTBLO = 1813
+PPC_INS_ALIAS_MTTBLO = 1814
+PPC_INS_ALIAS_MTSRR2 = 1815
+PPC_INS_ALIAS_MFSRR2 = 1816
+PPC_INS_ALIAS_MTSRR3 = 1817
+PPC_INS_ALIAS_MFSRR3 = 1818
+PPC_INS_ALIAS_MTDCCR = 1819
+PPC_INS_ALIAS_MFDCCR = 1820
+PPC_INS_ALIAS_MTICCR = 1821
+PPC_INS_ALIAS_MFICCR = 1822
+PPC_INS_ALIAS_TLBIE = 1823
+PPC_INS_ALIAS_TLBREHI = 1824
+PPC_INS_ALIAS_TLBRELO = 1825
+PPC_INS_ALIAS_TLBWEHI = 1826
+PPC_INS_ALIAS_TLBWELO = 1827
+PPC_INS_ALIAS_ROTLDI = 1828
+PPC_INS_ALIAS_ROTLDI_ = 1829
+PPC_INS_ALIAS_ROTLD = 1830
+PPC_INS_ALIAS_ROTLD_ = 1831
+PPC_INS_ALIAS_CLRLDI = 1832
+PPC_INS_ALIAS_CLRLDI_ = 1833
+PPC_INS_ALIAS_LNIA = 1834
+PPC_INS_ALIAS_BCp = 1835
+PPC_INS_ALIAS_BCAp = 1836
+PPC_INS_ALIAS_BCLp = 1837
+PPC_INS_ALIAS_BCLAp = 1838
+PPC_INS_ALIAS_BCm = 1839
+PPC_INS_ALIAS_BCAm = 1840
+PPC_INS_ALIAS_BCLm = 1841
+PPC_INS_ALIAS_BCLAm = 1842
+PPC_INS_ALIAS_BT = 1843
+PPC_INS_ALIAS_BTA = 1844
+PPC_INS_ALIAS_BTLR = 1845
+PPC_INS_ALIAS_BTL = 1846
+PPC_INS_ALIAS_BTLA = 1847
+PPC_INS_ALIAS_BTLRL = 1848
+PPC_INS_ALIAS_BTCTR = 1849
+PPC_INS_ALIAS_BTCTRL = 1850
+PPC_INS_ALIAS_BDZLR = 1851
+PPC_INS_ALIAS_BDZLRL = 1852
+PPC_INS_ALIAS_BDZL = 1853
+PPC_INS_ALIAS_BDZLA = 1854
+PPC_INS_ALIAS_BDZ = 1855
+PPC_INS_ALIAS_BDNZL = 1856
+PPC_INS_ALIAS_BDNZLA = 1857
+PPC_INS_ALIAS_BDNZ = 1858
+PPC_INS_ALIAS_BDZLp = 1859
+PPC_INS_ALIAS_BDZLAp = 1860
+PPC_INS_ALIAS_BDZp = 1861
+PPC_INS_ALIAS_BDNZLp = 1862
+PPC_INS_ALIAS_BDNZLAp = 1863
+PPC_INS_ALIAS_BDNZp = 1864
+PPC_INS_ALIAS_BDZLm = 1865
+PPC_INS_ALIAS_BDZLAm = 1866
+PPC_INS_ALIAS_BDZm = 1867
+PPC_INS_ALIAS_BDNZLm = 1868
+PPC_INS_ALIAS_BDNZLAm = 1869
+PPC_INS_ALIAS_BDNZm = 1870
+PPC_INS_ALIAS_BDNZLR = 1871
+PPC_INS_ALIAS_BDNZLRL = 1872
+PPC_INS_ALIAS_BDZLRp = 1873
+PPC_INS_ALIAS_BDZLRLp = 1874
+PPC_INS_ALIAS_BDNZLRp = 1875
+PPC_INS_ALIAS_BDNZLRLp = 1876
+PPC_INS_ALIAS_BDZLRm = 1877
+PPC_INS_ALIAS_BDZLRLm = 1878
+PPC_INS_ALIAS_BDNZLRm = 1879
+PPC_INS_ALIAS_BDNZLRLm = 1880
+PPC_INS_ALIAS_BF = 1881
+PPC_INS_ALIAS_BFA = 1882
+PPC_INS_ALIAS_BFLR = 1883
+PPC_INS_ALIAS_BFL = 1884
+PPC_INS_ALIAS_BFLA = 1885
+PPC_INS_ALIAS_BFLRL = 1886
+PPC_INS_ALIAS_BFCTR = 1887
+PPC_INS_ALIAS_BFCTRL = 1888
+PPC_INS_ALIAS_BTm = 1889
+PPC_INS_ALIAS_BTAm = 1890
+PPC_INS_ALIAS_BTLRm = 1891
+PPC_INS_ALIAS_BTLm = 1892
+PPC_INS_ALIAS_BTLAm = 1893
+PPC_INS_ALIAS_BTLRLm = 1894
+PPC_INS_ALIAS_BTCTRm = 1895
+PPC_INS_ALIAS_BTCTRLm = 1896
+PPC_INS_ALIAS_BFm = 1897
+PPC_INS_ALIAS_BFAm = 1898
+PPC_INS_ALIAS_BFLRm = 1899
+PPC_INS_ALIAS_BFLm = 1900
+PPC_INS_ALIAS_BFLAm = 1901
+PPC_INS_ALIAS_BFLRLm = 1902
+PPC_INS_ALIAS_BFCTRm = 1903
+PPC_INS_ALIAS_BFCTRLm = 1904
+PPC_INS_ALIAS_BTp = 1905
+PPC_INS_ALIAS_BTAp = 1906
+PPC_INS_ALIAS_BTLRp = 1907
+PPC_INS_ALIAS_BTLp = 1908
+PPC_INS_ALIAS_BTLAp = 1909
+PPC_INS_ALIAS_BTLRLp = 1910
+PPC_INS_ALIAS_BTCTRp = 1911
+PPC_INS_ALIAS_BTCTRLp = 1912
+PPC_INS_ALIAS_BFp = 1913
+PPC_INS_ALIAS_BFAp = 1914
+PPC_INS_ALIAS_BFLRp = 1915
+PPC_INS_ALIAS_BFLp = 1916
+PPC_INS_ALIAS_BFLAp = 1917
+PPC_INS_ALIAS_BFLRLp = 1918
+PPC_INS_ALIAS_BFCTRp = 1919
+PPC_INS_ALIAS_BFCTRLp = 1920
+PPC_INS_ALIAS_BDNZT = 1921
+PPC_INS_ALIAS_BDNZTA = 1922
+PPC_INS_ALIAS_BDNZTLR = 1923
+PPC_INS_ALIAS_BDNZTL = 1924
+PPC_INS_ALIAS_BDNZTLA = 1925
+PPC_INS_ALIAS_BDNZTLRL = 1926
+PPC_INS_ALIAS_BDNZF = 1927
+PPC_INS_ALIAS_BDNZFA = 1928
+PPC_INS_ALIAS_BDNZFLR = 1929
+PPC_INS_ALIAS_BDNZFL = 1930
+PPC_INS_ALIAS_BDNZFLA = 1931
+PPC_INS_ALIAS_BDNZFLRL = 1932
+PPC_INS_ALIAS_BDZT = 1933
+PPC_INS_ALIAS_BDZTA = 1934
+PPC_INS_ALIAS_BDZTLR = 1935
+PPC_INS_ALIAS_BDZTL = 1936
+PPC_INS_ALIAS_BDZTLA = 1937
+PPC_INS_ALIAS_BDZTLRL = 1938
+PPC_INS_ALIAS_BDZF = 1939
+PPC_INS_ALIAS_BDZFA = 1940
+PPC_INS_ALIAS_BDZFLR = 1941
+PPC_INS_ALIAS_BDZFL = 1942
+PPC_INS_ALIAS_BDZFLA = 1943
+PPC_INS_ALIAS_BDZFLRL = 1944
+PPC_INS_ALIAS_B = 1945
+PPC_INS_ALIAS_BA = 1946
+PPC_INS_ALIAS_BL = 1947
+PPC_INS_ALIAS_BLA = 1948
+PPC_INS_ALIAS_BLR = 1949
+PPC_INS_ALIAS_BLRL = 1950
+PPC_INS_ALIAS_BCTR = 1951
+PPC_INS_ALIAS_BCTRL = 1952
+PPC_INS_ALIAS_BLT = 1953
+PPC_INS_ALIAS_BLTA = 1954
+PPC_INS_ALIAS_BLTLR = 1955
+PPC_INS_ALIAS_BLTCTR = 1956
+PPC_INS_ALIAS_BLTL = 1957
+PPC_INS_ALIAS_BLTLA = 1958
+PPC_INS_ALIAS_BLTLRL = 1959
+PPC_INS_ALIAS_BLTCTRL = 1960
+PPC_INS_ALIAS_BLTm = 1961
+PPC_INS_ALIAS_BLTAm = 1962
+PPC_INS_ALIAS_BLTLRm = 1963
+PPC_INS_ALIAS_BLTCTRm = 1964
+PPC_INS_ALIAS_BLTLm = 1965
+PPC_INS_ALIAS_BLTLAm = 1966
+PPC_INS_ALIAS_BLTLRLm = 1967
+PPC_INS_ALIAS_BLTCTRLm = 1968
+PPC_INS_ALIAS_BLTp = 1969
+PPC_INS_ALIAS_BLTAp = 1970
+PPC_INS_ALIAS_BLTLRp = 1971
+PPC_INS_ALIAS_BLTCTRp = 1972
+PPC_INS_ALIAS_BLTLp = 1973
+PPC_INS_ALIAS_BLTLAp = 1974
+PPC_INS_ALIAS_BLTLRLp = 1975
+PPC_INS_ALIAS_BLTCTRLp = 1976
+PPC_INS_ALIAS_BGT = 1977
+PPC_INS_ALIAS_BGTA = 1978
+PPC_INS_ALIAS_BGTLR = 1979
+PPC_INS_ALIAS_BGTCTR = 1980
+PPC_INS_ALIAS_BGTL = 1981
+PPC_INS_ALIAS_BGTLA = 1982
+PPC_INS_ALIAS_BGTLRL = 1983
+PPC_INS_ALIAS_BGTCTRL = 1984
+PPC_INS_ALIAS_BGTm = 1985
+PPC_INS_ALIAS_BGTAm = 1986
+PPC_INS_ALIAS_BGTLRm = 1987
+PPC_INS_ALIAS_BGTCTRm = 1988
+PPC_INS_ALIAS_BGTLm = 1989
+PPC_INS_ALIAS_BGTLAm = 1990
+PPC_INS_ALIAS_BGTLRLm = 1991
+PPC_INS_ALIAS_BGTCTRLm = 1992
+PPC_INS_ALIAS_BGTp = 1993
+PPC_INS_ALIAS_BGTAp = 1994
+PPC_INS_ALIAS_BGTLRp = 1995
+PPC_INS_ALIAS_BGTCTRp = 1996
+PPC_INS_ALIAS_BGTLp = 1997
+PPC_INS_ALIAS_BGTLAp = 1998
+PPC_INS_ALIAS_BGTLRLp = 1999
+PPC_INS_ALIAS_BGTCTRLp = 2000
+PPC_INS_ALIAS_BEQ = 2001
+PPC_INS_ALIAS_BEQA = 2002
+PPC_INS_ALIAS_BEQLR = 2003
+PPC_INS_ALIAS_BEQCTR = 2004
+PPC_INS_ALIAS_BEQL = 2005
+PPC_INS_ALIAS_BEQLA = 2006
+PPC_INS_ALIAS_BEQLRL = 2007
+PPC_INS_ALIAS_BEQCTRL = 2008
+PPC_INS_ALIAS_BEQm = 2009
+PPC_INS_ALIAS_BEQAm = 2010
+PPC_INS_ALIAS_BEQLRm = 2011
+PPC_INS_ALIAS_BEQCTRm = 2012
+PPC_INS_ALIAS_BEQLm = 2013
+PPC_INS_ALIAS_BEQLAm = 2014
+PPC_INS_ALIAS_BEQLRLm = 2015
+PPC_INS_ALIAS_BEQCTRLm = 2016
+PPC_INS_ALIAS_BEQp = 2017
+PPC_INS_ALIAS_BEQAp = 2018
+PPC_INS_ALIAS_BEQLRp = 2019
+PPC_INS_ALIAS_BEQCTRp = 2020
+PPC_INS_ALIAS_BEQLp = 2021
+PPC_INS_ALIAS_BEQLAp = 2022
+PPC_INS_ALIAS_BEQLRLp = 2023
+PPC_INS_ALIAS_BEQCTRLp = 2024
+PPC_INS_ALIAS_BUN = 2025
+PPC_INS_ALIAS_BUNA = 2026
+PPC_INS_ALIAS_BUNLR = 2027
+PPC_INS_ALIAS_BUNCTR = 2028
+PPC_INS_ALIAS_BUNL = 2029
+PPC_INS_ALIAS_BUNLA = 2030
+PPC_INS_ALIAS_BUNLRL = 2031
+PPC_INS_ALIAS_BUNCTRL = 2032
+PPC_INS_ALIAS_BUNm = 2033
+PPC_INS_ALIAS_BUNAm = 2034
+PPC_INS_ALIAS_BUNLRm = 2035
+PPC_INS_ALIAS_BUNCTRm = 2036
+PPC_INS_ALIAS_BUNLm = 2037
+PPC_INS_ALIAS_BUNLAm = 2038
+PPC_INS_ALIAS_BUNLRLm = 2039
+PPC_INS_ALIAS_BUNCTRLm = 2040
+PPC_INS_ALIAS_BUNp = 2041
+PPC_INS_ALIAS_BUNAp = 2042
+PPC_INS_ALIAS_BUNLRp = 2043
+PPC_INS_ALIAS_BUNCTRp = 2044
+PPC_INS_ALIAS_BUNLp = 2045
+PPC_INS_ALIAS_BUNLAp = 2046
+PPC_INS_ALIAS_BUNLRLp = 2047
+PPC_INS_ALIAS_BUNCTRLp = 2048
+PPC_INS_ALIAS_BSO = 2049
+PPC_INS_ALIAS_BSOA = 2050
+PPC_INS_ALIAS_BSOLR = 2051
+PPC_INS_ALIAS_BSOCTR = 2052
+PPC_INS_ALIAS_BSOL = 2053
+PPC_INS_ALIAS_BSOLA = 2054
+PPC_INS_ALIAS_BSOLRL = 2055
+PPC_INS_ALIAS_BSOCTRL = 2056
+PPC_INS_ALIAS_BSOm = 2057
+PPC_INS_ALIAS_BSOAm = 2058
+PPC_INS_ALIAS_BSOLRm = 2059
+PPC_INS_ALIAS_BSOCTRm = 2060
+PPC_INS_ALIAS_BSOLm = 2061
+PPC_INS_ALIAS_BSOLAm = 2062
+PPC_INS_ALIAS_BSOLRLm = 2063
+PPC_INS_ALIAS_BSOCTRLm = 2064
+PPC_INS_ALIAS_BSOp = 2065
+PPC_INS_ALIAS_BSOAp = 2066
+PPC_INS_ALIAS_BSOLRp = 2067
+PPC_INS_ALIAS_BSOCTRp = 2068
+PPC_INS_ALIAS_BSOLp = 2069
+PPC_INS_ALIAS_BSOLAp = 2070
+PPC_INS_ALIAS_BSOLRLp = 2071
+PPC_INS_ALIAS_BSOCTRLp = 2072
+PPC_INS_ALIAS_BGE = 2073
+PPC_INS_ALIAS_BGEA = 2074
+PPC_INS_ALIAS_BGELR = 2075
+PPC_INS_ALIAS_BGECTR = 2076
+PPC_INS_ALIAS_BGEL = 2077
+PPC_INS_ALIAS_BGELA = 2078
+PPC_INS_ALIAS_BGELRL = 2079
+PPC_INS_ALIAS_BGECTRL = 2080
+PPC_INS_ALIAS_BGEm = 2081
+PPC_INS_ALIAS_BGEAm = 2082
+PPC_INS_ALIAS_BGELRm = 2083
+PPC_INS_ALIAS_BGECTRm = 2084
+PPC_INS_ALIAS_BGELm = 2085
+PPC_INS_ALIAS_BGELAm = 2086
+PPC_INS_ALIAS_BGELRLm = 2087
+PPC_INS_ALIAS_BGECTRLm = 2088
+PPC_INS_ALIAS_BGEp = 2089
+PPC_INS_ALIAS_BGEAp = 2090
+PPC_INS_ALIAS_BGELRp = 2091
+PPC_INS_ALIAS_BGECTRp = 2092
+PPC_INS_ALIAS_BGELp = 2093
+PPC_INS_ALIAS_BGELAp = 2094
+PPC_INS_ALIAS_BGELRLp = 2095
+PPC_INS_ALIAS_BGECTRLp = 2096
+PPC_INS_ALIAS_BNL = 2097
+PPC_INS_ALIAS_BNLA = 2098
+PPC_INS_ALIAS_BNLLR = 2099
+PPC_INS_ALIAS_BNLCTR = 2100
+PPC_INS_ALIAS_BNLL = 2101
+PPC_INS_ALIAS_BNLLA = 2102
+PPC_INS_ALIAS_BNLLRL = 2103
+PPC_INS_ALIAS_BNLCTRL = 2104
+PPC_INS_ALIAS_BNLm = 2105
+PPC_INS_ALIAS_BNLAm = 2106
+PPC_INS_ALIAS_BNLLRm = 2107
+PPC_INS_ALIAS_BNLCTRm = 2108
+PPC_INS_ALIAS_BNLLm = 2109
+PPC_INS_ALIAS_BNLLAm = 2110
+PPC_INS_ALIAS_BNLLRLm = 2111
+PPC_INS_ALIAS_BNLCTRLm = 2112
+PPC_INS_ALIAS_BNLp = 2113
+PPC_INS_ALIAS_BNLAp = 2114
+PPC_INS_ALIAS_BNLLRp = 2115
+PPC_INS_ALIAS_BNLCTRp = 2116
+PPC_INS_ALIAS_BNLLp = 2117
+PPC_INS_ALIAS_BNLLAp = 2118
+PPC_INS_ALIAS_BNLLRLp = 2119
+PPC_INS_ALIAS_BNLCTRLp = 2120
+PPC_INS_ALIAS_BLE = 2121
+PPC_INS_ALIAS_BLEA = 2122
+PPC_INS_ALIAS_BLELR = 2123
+PPC_INS_ALIAS_BLECTR = 2124
+PPC_INS_ALIAS_BLEL = 2125
+PPC_INS_ALIAS_BLELA = 2126
+PPC_INS_ALIAS_BLELRL = 2127
+PPC_INS_ALIAS_BLECTRL = 2128
+PPC_INS_ALIAS_BLEm = 2129
+PPC_INS_ALIAS_BLEAm = 2130
+PPC_INS_ALIAS_BLELRm = 2131
+PPC_INS_ALIAS_BLECTRm = 2132
+PPC_INS_ALIAS_BLELm = 2133
+PPC_INS_ALIAS_BLELAm = 2134
+PPC_INS_ALIAS_BLELRLm = 2135
+PPC_INS_ALIAS_BLECTRLm = 2136
+PPC_INS_ALIAS_BLEp = 2137
+PPC_INS_ALIAS_BLEAp = 2138
+PPC_INS_ALIAS_BLELRp = 2139
+PPC_INS_ALIAS_BLECTRp = 2140
+PPC_INS_ALIAS_BLELp = 2141
+PPC_INS_ALIAS_BLELAp = 2142
+PPC_INS_ALIAS_BLELRLp = 2143
+PPC_INS_ALIAS_BLECTRLp = 2144
+PPC_INS_ALIAS_BNG = 2145
+PPC_INS_ALIAS_BNGA = 2146
+PPC_INS_ALIAS_BNGLR = 2147
+PPC_INS_ALIAS_BNGCTR = 2148
+PPC_INS_ALIAS_BNGL = 2149
+PPC_INS_ALIAS_BNGLA = 2150
+PPC_INS_ALIAS_BNGLRL = 2151
+PPC_INS_ALIAS_BNGCTRL = 2152
+PPC_INS_ALIAS_BNGm = 2153
+PPC_INS_ALIAS_BNGAm = 2154
+PPC_INS_ALIAS_BNGLRm = 2155
+PPC_INS_ALIAS_BNGCTRm = 2156
+PPC_INS_ALIAS_BNGLm = 2157
+PPC_INS_ALIAS_BNGLAm = 2158
+PPC_INS_ALIAS_BNGLRLm = 2159
+PPC_INS_ALIAS_BNGCTRLm = 2160
+PPC_INS_ALIAS_BNGp = 2161
+PPC_INS_ALIAS_BNGAp = 2162
+PPC_INS_ALIAS_BNGLRp = 2163
+PPC_INS_ALIAS_BNGCTRp = 2164
+PPC_INS_ALIAS_BNGLp = 2165
+PPC_INS_ALIAS_BNGLAp = 2166
+PPC_INS_ALIAS_BNGLRLp = 2167
+PPC_INS_ALIAS_BNGCTRLp = 2168
+PPC_INS_ALIAS_BNE = 2169
+PPC_INS_ALIAS_BNEA = 2170
+PPC_INS_ALIAS_BNELR = 2171
+PPC_INS_ALIAS_BNECTR = 2172
+PPC_INS_ALIAS_BNEL = 2173
+PPC_INS_ALIAS_BNELA = 2174
+PPC_INS_ALIAS_BNELRL = 2175
+PPC_INS_ALIAS_BNECTRL = 2176
+PPC_INS_ALIAS_BNEm = 2177
+PPC_INS_ALIAS_BNEAm = 2178
+PPC_INS_ALIAS_BNELRm = 2179
+PPC_INS_ALIAS_BNECTRm = 2180
+PPC_INS_ALIAS_BNELm = 2181
+PPC_INS_ALIAS_BNELAm = 2182
+PPC_INS_ALIAS_BNELRLm = 2183
+PPC_INS_ALIAS_BNECTRLm = 2184
+PPC_INS_ALIAS_BNEp = 2185
+PPC_INS_ALIAS_BNEAp = 2186
+PPC_INS_ALIAS_BNELRp = 2187
+PPC_INS_ALIAS_BNECTRp = 2188
+PPC_INS_ALIAS_BNELp = 2189
+PPC_INS_ALIAS_BNELAp = 2190
+PPC_INS_ALIAS_BNELRLp = 2191
+PPC_INS_ALIAS_BNECTRLp = 2192
+PPC_INS_ALIAS_BNU = 2193
+PPC_INS_ALIAS_BNUA = 2194
+PPC_INS_ALIAS_BNULR = 2195
+PPC_INS_ALIAS_BNUCTR = 2196
+PPC_INS_ALIAS_BNUL = 2197
+PPC_INS_ALIAS_BNULA = 2198
+PPC_INS_ALIAS_BNULRL = 2199
+PPC_INS_ALIAS_BNUCTRL = 2200
+PPC_INS_ALIAS_BNUm = 2201
+PPC_INS_ALIAS_BNUAm = 2202
+PPC_INS_ALIAS_BNULRm = 2203
+PPC_INS_ALIAS_BNUCTRm = 2204
+PPC_INS_ALIAS_BNULm = 2205
+PPC_INS_ALIAS_BNULAm = 2206
+PPC_INS_ALIAS_BNULRLm = 2207
+PPC_INS_ALIAS_BNUCTRLm = 2208
+PPC_INS_ALIAS_BNUp = 2209
+PPC_INS_ALIAS_BNUAp = 2210
+PPC_INS_ALIAS_BNULRp = 2211
+PPC_INS_ALIAS_BNUCTRp = 2212
+PPC_INS_ALIAS_BNULp = 2213
+PPC_INS_ALIAS_BNULAp = 2214
+PPC_INS_ALIAS_BNULRLp = 2215
+PPC_INS_ALIAS_BNUCTRLp = 2216
+PPC_INS_ALIAS_BNS = 2217
+PPC_INS_ALIAS_BNSA = 2218
+PPC_INS_ALIAS_BNSLR = 2219
+PPC_INS_ALIAS_BNSCTR = 2220
+PPC_INS_ALIAS_BNSL = 2221
+PPC_INS_ALIAS_BNSLA = 2222
+PPC_INS_ALIAS_BNSLRL = 2223
+PPC_INS_ALIAS_BNSCTRL = 2224
+PPC_INS_ALIAS_BNSm = 2225
+PPC_INS_ALIAS_BNSAm = 2226
+PPC_INS_ALIAS_BNSLRm = 2227
+PPC_INS_ALIAS_BNSCTRm = 2228
+PPC_INS_ALIAS_BNSLm = 2229
+PPC_INS_ALIAS_BNSLAm = 2230
+PPC_INS_ALIAS_BNSLRLm = 2231
+PPC_INS_ALIAS_BNSCTRLm = 2232
+PPC_INS_ALIAS_BNSp = 2233
+PPC_INS_ALIAS_BNSAp = 2234
+PPC_INS_ALIAS_BNSLRp = 2235
+PPC_INS_ALIAS_BNSCTRp = 2236
+PPC_INS_ALIAS_BNSLp = 2237
+PPC_INS_ALIAS_BNSLAp = 2238
+PPC_INS_ALIAS_BNSLRLp = 2239
+PPC_INS_ALIAS_BNSCTRLp = 2240
+PPC_INS_ALIAS_CMPWI = 2241
+PPC_INS_ALIAS_CMPW = 2242
+PPC_INS_ALIAS_CMPLWI = 2243
+PPC_INS_ALIAS_CMPLW = 2244
+PPC_INS_ALIAS_CMPDI = 2245
+PPC_INS_ALIAS_CMPD = 2246
+PPC_INS_ALIAS_CMPLDI = 2247
+PPC_INS_ALIAS_CMPLD = 2248
+PPC_INS_ALIAS_CMPI = 2249
+PPC_INS_ALIAS_CMP = 2250
+PPC_INS_ALIAS_CMPLI = 2251
+PPC_INS_ALIAS_CMPL = 2252
+PPC_INS_ALIAS_TRAP = 2253
+PPC_INS_ALIAS_TDLTI = 2254
+PPC_INS_ALIAS_TDLT = 2255
+PPC_INS_ALIAS_TWLTI = 2256
+PPC_INS_ALIAS_TWLT = 2257
+PPC_INS_ALIAS_TDLEI = 2258
+PPC_INS_ALIAS_TDLE = 2259
+PPC_INS_ALIAS_TWLEI = 2260
+PPC_INS_ALIAS_TWLE = 2261
+PPC_INS_ALIAS_TDEQI = 2262
+PPC_INS_ALIAS_TDEQ = 2263
+PPC_INS_ALIAS_TWEQI = 2264
+PPC_INS_ALIAS_TWEQ = 2265
+PPC_INS_ALIAS_TDGEI = 2266
+PPC_INS_ALIAS_TDGE = 2267
+PPC_INS_ALIAS_TWGEI = 2268
+PPC_INS_ALIAS_TWGE = 2269
+PPC_INS_ALIAS_TDGTI = 2270
+PPC_INS_ALIAS_TDGT = 2271
+PPC_INS_ALIAS_TWGTI = 2272
+PPC_INS_ALIAS_TWGT = 2273
+PPC_INS_ALIAS_TDNLI = 2274
+PPC_INS_ALIAS_TDNL = 2275
+PPC_INS_ALIAS_TWNLI = 2276
+PPC_INS_ALIAS_TWNL = 2277
+PPC_INS_ALIAS_TDNEI = 2278
+PPC_INS_ALIAS_TDNE = 2279
+PPC_INS_ALIAS_TWNEI = 2280
+PPC_INS_ALIAS_TWNE = 2281
+PPC_INS_ALIAS_TDNGI = 2282
+PPC_INS_ALIAS_TDNG = 2283
+PPC_INS_ALIAS_TWNGI = 2284
+PPC_INS_ALIAS_TWNG = 2285
+PPC_INS_ALIAS_TDLLTI = 2286
+PPC_INS_ALIAS_TDLLT = 2287
+PPC_INS_ALIAS_TWLLTI = 2288
+PPC_INS_ALIAS_TWLLT = 2289
+PPC_INS_ALIAS_TDLLEI = 2290
+PPC_INS_ALIAS_TDLLE = 2291
+PPC_INS_ALIAS_TWLLEI = 2292
+PPC_INS_ALIAS_TWLLE = 2293
+PPC_INS_ALIAS_TDLGEI = 2294
+PPC_INS_ALIAS_TDLGE = 2295
+PPC_INS_ALIAS_TWLGEI = 2296
+PPC_INS_ALIAS_TWLGE = 2297
+PPC_INS_ALIAS_TDLGTI = 2298
+PPC_INS_ALIAS_TDLGT = 2299
+PPC_INS_ALIAS_TWLGTI = 2300
+PPC_INS_ALIAS_TWLGT = 2301
+PPC_INS_ALIAS_TDLNLI = 2302
+PPC_INS_ALIAS_TDLNL = 2303
+PPC_INS_ALIAS_TWLNLI = 2304
+PPC_INS_ALIAS_TWLNL = 2305
+PPC_INS_ALIAS_TDLNGI = 2306
+PPC_INS_ALIAS_TDLNG = 2307
+PPC_INS_ALIAS_TWLNGI = 2308
+PPC_INS_ALIAS_TWLNG = 2309
+PPC_INS_ALIAS_TDUI = 2310
+PPC_INS_ALIAS_TDU = 2311
+PPC_INS_ALIAS_TWUI = 2312
+PPC_INS_ALIAS_TWU = 2313
+PPC_INS_ALIAS_PASTE_ = 2314
+PPC_INS_ALIAS_QVFCLR = 2315
+PPC_INS_ALIAS_QVFAND = 2316
+PPC_INS_ALIAS_QVFANDC = 2317
+PPC_INS_ALIAS_QVFCTFB = 2318
+PPC_INS_ALIAS_QVFXOR = 2319
+PPC_INS_ALIAS_QVFOR = 2320
+PPC_INS_ALIAS_QVFNOR = 2321
+PPC_INS_ALIAS_QVFEQU = 2322
+PPC_INS_ALIAS_QVFNOT = 2323
+PPC_INS_ALIAS_QVFORC = 2324
+PPC_INS_ALIAS_QVFNAND = 2325
+PPC_INS_ALIAS_QVFSET = 2326
+PPC_INS_ALIAS_SLWI = 2327
+PPC_INS_ALIAS_SRWI = 2328
+PPC_INS_ALIAS_SLDI = 2329
+PPC_INS_ALIAS_END = 2330
 
 PPC_GRP_INVALID = 0
 PPC_GRP_JUMP = 1
@@ -2964,128 +2965,130 @@ PPC_FEATURE_HasPS = 144
 PPC_FEATURE_HasQPX = 145
 PPC_FEATURE_IsPPC6xx = 146
 PPC_GRP_ENDING = 147
-PPC_INSN_FORM_XOFORM_1 = 148
-PPC_INSN_FORM_Z23FORM_RTAB5_CY2 = 149
-PPC_INSN_FORM_DFORM_BASE = 150
-PPC_INSN_FORM_DXFORM = 151
-PPC_INSN_FORM_XFORM_BASE_R3XO_SWAPPED = 152
-PPC_INSN_FORM_DFORM_4 = 153
-PPC_INSN_FORM_XFORM_ATTN = 154
-PPC_INSN_FORM_IFORM = 155
-PPC_INSN_FORM_VX_RD5_RSP5_PS1_XO9 = 156
-PPC_INSN_FORM_VX_RD5_EO5_RS5_PS1_XO9 = 157
-PPC_INSN_FORM_VXFORM_1 = 158
-PPC_INSN_FORM_XLFORM_2 = 159
-PPC_INSN_FORM_BFORM = 160
-PPC_INSN_FORM_EVXFORM_1 = 161
-PPC_INSN_FORM_XFORM_BASE_R3XO = 162
-PPC_INSN_FORM_XFORM_16 = 163
-PPC_INSN_FORM_DFORM_5 = 164
-PPC_INSN_FORM_X_BF3_RS5_RS5 = 165
-PPC_INSN_FORM_X_BF3_L1_RS5_RS5 = 166
-PPC_INSN_FORM_XLFORM_1 = 167
-PPC_INSN_FORM_XFORM_45 = 168
-PPC_INSN_FORM_DCB_FORM = 169
-PPC_INSN_FORM_DCB_FORM_HINT = 170
-PPC_INSN_FORM_XFORM_ATB3 = 171
-PPC_INSN_FORM_XFORM_AT3 = 172
-PPC_INSN_FORM_XX2FORM_AT3_XBP5_P2 = 173
-PPC_INSN_FORM_XX3FORM_AT3_XABP5_P1 = 174
-PPC_INSN_FORM_DSS_FORM = 175
-PPC_INSN_FORM_EFXFORM_1 = 176
-PPC_INSN_FORM_EFXFORM_3 = 177
-PPC_INSN_FORM_EVXFORM_3 = 178
-PPC_INSN_FORM_EVXFORM_D = 179
-PPC_INSN_FORM_EVXFORM_4 = 180
-PPC_INSN_FORM_XSFORM_1 = 181
-PPC_INSN_FORM_XFORM_24_SYNC = 182
-PPC_INSN_FORM_AFORM_1 = 183
-PPC_INSN_FORM_XFORM_17 = 184
-PPC_INSN_FORM_XFORM_XD6_RA5_RB5 = 185
-PPC_INSN_FORM_XFORM_ICBT = 186
-PPC_INSN_FORM_AFORM_4 = 187
-PPC_INSN_FORM_DFORM_1 = 188
-PPC_INSN_FORM_DSFORM_1 = 189
-PPC_INSN_FORM_DFORM_2_R0 = 190
-PPC_INSN_FORM_DQFORM_RTP5_RA17_MEM = 191
-PPC_INSN_FORM_XX1FORM = 192
-PPC_INSN_FORM_DQ_RD6_RS5_DQ12 = 193
-PPC_INSN_FORM_XFORM_XT6_IMM5 = 194
-PPC_INSN_FORM_DQFORM_XTP5_RA17_MEM = 195
-PPC_INSN_FORM_XFORMMEMOP = 196
-PPC_INSN_FORM_VAFORM_1A = 197
-PPC_INSN_FORM_XFORM_MBAR = 198
-PPC_INSN_FORM_XLFORM_3 = 199
-PPC_INSN_FORM_XFXFORM_3P = 200
-PPC_INSN_FORM_XFXFORM_3 = 201
-PPC_INSN_FORM_XFXFORM_1 = 202
-PPC_INSN_FORM_XFXFORM_5A = 203
-PPC_INSN_FORM_XFORM_SR = 204
-PPC_INSN_FORM_XFORM_SRIN = 205
-PPC_INSN_FORM_VXFORM_4 = 206
-PPC_INSN_FORM_XFXFORM_5 = 207
-PPC_INSN_FORM_XFLFORM_1 = 208
-PPC_INSN_FORM_XLFORM_4 = 209
-PPC_INSN_FORM_XFORM_MTMSR = 210
-PPC_INSN_FORM_VXFORM_5 = 211
-PPC_INSN_FORM_VXFORM_RD5_XO5_RS5 = 212
-PPC_INSN_FORM_DCBZL_FORM = 213
-PPC_INSN_FORM_PSFORM_QD = 214
-PPC_INSN_FORM_PSFORM_QI = 215
-PPC_INSN_FORM_PSFORM_Y = 216
-PPC_INSN_FORM_PSFORM_X = 217
-PPC_INSN_FORM_PSFORM_C = 218
-PPC_INSN_FORM_Z23FORM_1 = 219
-PPC_INSN_FORM_XFORM_18 = 220
-PPC_INSN_FORM_XFORM_20 = 221
-PPC_INSN_FORM_Z23FORM_3 = 222
-PPC_INSN_FORM_XLFORM_S = 223
-PPC_INSN_FORM_MDSFORM_1 = 224
-PPC_INSN_FORM_MDFORM_1 = 225
-PPC_INSN_FORM_MFORM_1 = 226
-PPC_INSN_FORM_SCFORM = 227
-PPC_INSN_FORM_XFORM_44 = 228
-PPC_INSN_FORM_XOFORM_RTAB5_L1 = 229
-PPC_INSN_FORM_XFORM_HTM0 = 230
-PPC_INSN_FORM_XFORM_HTM3 = 231
-PPC_INSN_FORM_XFORM_HTM1 = 232
-PPC_INSN_FORM_XFORM_TLBWS = 233
-PPC_INSN_FORM_XFORM_24 = 234
-PPC_INSN_FORM_XFORM_HTM2 = 235
-PPC_INSN_FORM_VXFORM_2 = 236
-PPC_INSN_FORM_VXRFORM_1 = 237
-PPC_INSN_FORM_VXFORM_BF3_VAB5 = 238
-PPC_INSN_FORM_VXFORM_RD5_MP_VB5 = 239
-PPC_INSN_FORM_VXFORM_RD5_N3_VB5 = 240
-PPC_INSN_FORM_VAFORM_1 = 241
-PPC_INSN_FORM_VXFORM_BX = 242
-PPC_INSN_FORM_VXFORM_CR = 243
-PPC_INSN_FORM_VNFORM_VTAB5_SD3 = 244
-PPC_INSN_FORM_VAFORM_2 = 245
-PPC_INSN_FORM_VXFORM_3 = 246
-PPC_INSN_FORM_VXFORM_VTB5_RC = 247
-PPC_INSN_FORM_REQUIRES = 248
-PPC_INSN_FORM_XX2FORM = 249
-PPC_INSN_FORM_XX3FORM = 250
-PPC_INSN_FORM_XX3FORM_1 = 251
-PPC_INSN_FORM_XX2_RD6_XO5_RS6 = 252
-PPC_INSN_FORM_Z23FORM_8 = 253
-PPC_INSN_FORM_XX2FORM_1 = 254
-PPC_INSN_FORM_XX2_BF3_DCMX7_RS6 = 255
-PPC_INSN_FORM_X_BF3_DCMX7_RS5 = 256
-PPC_INSN_FORM_XX2_RD5_XO5_RS6 = 257
-PPC_INSN_FORM_XX3FORM_AT3_XAB6 = 258
-PPC_INSN_FORM_XX3FORM_RC = 259
-PPC_INSN_FORM_XX2_BF3_XO5_XB6_XO9 = 260
-PPC_INSN_FORM_XX2_RD6_DCMX7_RS6 = 261
-PPC_INSN_FORM_XX2_RD6_UIM5_RS6 = 262
-PPC_INSN_FORM_XFORM_XT6_IMM5_VB5 = 263
-PPC_INSN_FORM_XX3FORM_2 = 264
-PPC_INSN_FORM_XX4FORM = 265
-PPC_INSN_FORM_X_RD6_IMM8 = 266
-PPC_INSN_FORM_XX2FORM_2 = 267
-PPC_INSN_FORM_BFORM_3 = 268
-PPC_INSN_FORM_BFORM_3_AT = 269
+
+PPC_INSN_FORM_INVALID = 0
+PPC_INSN_FORM_XOFORM_1 = 1
+PPC_INSN_FORM_Z23FORM_RTAB5_CY2 = 2
+PPC_INSN_FORM_DFORM_BASE = 3
+PPC_INSN_FORM_DXFORM = 4
+PPC_INSN_FORM_XFORM_BASE_R3XO_SWAPPED = 5
+PPC_INSN_FORM_DFORM_4 = 6
+PPC_INSN_FORM_XFORM_ATTN = 7
+PPC_INSN_FORM_IFORM = 8
+PPC_INSN_FORM_VX_RD5_RSP5_PS1_XO9 = 9
+PPC_INSN_FORM_VX_RD5_EO5_RS5_PS1_XO9 = 10
+PPC_INSN_FORM_VXFORM_1 = 11
+PPC_INSN_FORM_XLFORM_2 = 12
+PPC_INSN_FORM_BFORM = 13
+PPC_INSN_FORM_EVXFORM_1 = 14
+PPC_INSN_FORM_XFORM_BASE_R3XO = 15
+PPC_INSN_FORM_XFORM_16 = 16
+PPC_INSN_FORM_DFORM_5 = 17
+PPC_INSN_FORM_X_BF3_RS5_RS5 = 18
+PPC_INSN_FORM_X_BF3_L1_RS5_RS5 = 19
+PPC_INSN_FORM_XLFORM_1 = 20
+PPC_INSN_FORM_XFORM_45 = 21
+PPC_INSN_FORM_DCB_FORM = 22
+PPC_INSN_FORM_DCB_FORM_HINT = 23
+PPC_INSN_FORM_XFORM_ATB3 = 24
+PPC_INSN_FORM_XFORM_AT3 = 25
+PPC_INSN_FORM_XX2FORM_AT3_XBP5_P2 = 26
+PPC_INSN_FORM_XX3FORM_AT3_XABP5_P1 = 27
+PPC_INSN_FORM_DSS_FORM = 28
+PPC_INSN_FORM_EFXFORM_1 = 29
+PPC_INSN_FORM_EFXFORM_3 = 30
+PPC_INSN_FORM_EVXFORM_3 = 31
+PPC_INSN_FORM_EVXFORM_D = 32
+PPC_INSN_FORM_EVXFORM_4 = 33
+PPC_INSN_FORM_XSFORM_1 = 34
+PPC_INSN_FORM_XFORM_24_SYNC = 35
+PPC_INSN_FORM_AFORM_1 = 36
+PPC_INSN_FORM_XFORM_17 = 37
+PPC_INSN_FORM_XFORM_XD6_RA5_RB5 = 38
+PPC_INSN_FORM_XFORM_ICBT = 39
+PPC_INSN_FORM_AFORM_4 = 40
+PPC_INSN_FORM_DFORM_1 = 41
+PPC_INSN_FORM_DSFORM_1 = 42
+PPC_INSN_FORM_DFORM_2_R0 = 43
+PPC_INSN_FORM_DQFORM_RTP5_RA17_MEM = 44
+PPC_INSN_FORM_XX1FORM = 45
+PPC_INSN_FORM_DQ_RD6_RS5_DQ12 = 46
+PPC_INSN_FORM_XFORM_XT6_IMM5 = 47
+PPC_INSN_FORM_DQFORM_XTP5_RA17_MEM = 48
+PPC_INSN_FORM_XFORMMEMOP = 49
+PPC_INSN_FORM_VAFORM_1A = 50
+PPC_INSN_FORM_XFORM_MBAR = 51
+PPC_INSN_FORM_XLFORM_3 = 52
+PPC_INSN_FORM_XFXFORM_3P = 53
+PPC_INSN_FORM_XFXFORM_3 = 54
+PPC_INSN_FORM_XFXFORM_1 = 55
+PPC_INSN_FORM_XFXFORM_5A = 56
+PPC_INSN_FORM_XFORM_SR = 57
+PPC_INSN_FORM_XFORM_SRIN = 58
+PPC_INSN_FORM_VXFORM_4 = 59
+PPC_INSN_FORM_XFXFORM_5 = 60
+PPC_INSN_FORM_XFLFORM_1 = 61
+PPC_INSN_FORM_XLFORM_4 = 62
+PPC_INSN_FORM_XFORM_MTMSR = 63
+PPC_INSN_FORM_VXFORM_5 = 64
+PPC_INSN_FORM_VXFORM_RD5_XO5_RS5 = 65
+PPC_INSN_FORM_DCBZL_FORM = 66
+PPC_INSN_FORM_PSFORM_QD = 67
+PPC_INSN_FORM_PSFORM_QI = 68
+PPC_INSN_FORM_PSFORM_Y = 69
+PPC_INSN_FORM_PSFORM_X = 70
+PPC_INSN_FORM_PSFORM_C = 71
+PPC_INSN_FORM_Z23FORM_1 = 72
+PPC_INSN_FORM_XFORM_18 = 73
+PPC_INSN_FORM_XFORM_20 = 74
+PPC_INSN_FORM_Z23FORM_3 = 75
+PPC_INSN_FORM_XLFORM_S = 76
+PPC_INSN_FORM_MDSFORM_1 = 77
+PPC_INSN_FORM_MDFORM_1 = 78
+PPC_INSN_FORM_MFORM_1 = 79
+PPC_INSN_FORM_SCFORM = 80
+PPC_INSN_FORM_XFORM_44 = 81
+PPC_INSN_FORM_XOFORM_RTAB5_L1 = 82
+PPC_INSN_FORM_XFORM_HTM0 = 83
+PPC_INSN_FORM_XFORM_HTM3 = 84
+PPC_INSN_FORM_XFORM_HTM1 = 85
+PPC_INSN_FORM_XFORM_TLBWS = 86
+PPC_INSN_FORM_XFORM_24 = 87
+PPC_INSN_FORM_XFORM_HTM2 = 88
+PPC_INSN_FORM_VXFORM_2 = 89
+PPC_INSN_FORM_VXRFORM_1 = 90
+PPC_INSN_FORM_VXFORM_BF3_VAB5 = 91
+PPC_INSN_FORM_VXFORM_RD5_MP_VB5 = 92
+PPC_INSN_FORM_VXFORM_RD5_N3_VB5 = 93
+PPC_INSN_FORM_VAFORM_1 = 94
+PPC_INSN_FORM_VXFORM_BX = 95
+PPC_INSN_FORM_VXFORM_CR = 96
+PPC_INSN_FORM_VNFORM_VTAB5_SD3 = 97
+PPC_INSN_FORM_VAFORM_2 = 98
+PPC_INSN_FORM_VXFORM_3 = 99
+PPC_INSN_FORM_VXFORM_VTB5_RC = 100
+PPC_INSN_FORM_REQUIRES = 101
+PPC_INSN_FORM_XX2FORM = 102
+PPC_INSN_FORM_XX3FORM = 103
+PPC_INSN_FORM_XX3FORM_1 = 104
+PPC_INSN_FORM_XX2_RD6_XO5_RS6 = 105
+PPC_INSN_FORM_Z23FORM_8 = 106
+PPC_INSN_FORM_XX2FORM_1 = 107
+PPC_INSN_FORM_XX2_BF3_DCMX7_RS6 = 108
+PPC_INSN_FORM_X_BF3_DCMX7_RS5 = 109
+PPC_INSN_FORM_XX2_RD5_XO5_RS6 = 110
+PPC_INSN_FORM_XX3FORM_AT3_XAB6 = 111
+PPC_INSN_FORM_XX3FORM_RC = 112
+PPC_INSN_FORM_XX2_BF3_XO5_XB6_XO9 = 113
+PPC_INSN_FORM_XX2_RD6_DCMX7_RS6 = 114
+PPC_INSN_FORM_XX2_RD6_UIM5_RS6 = 115
+PPC_INSN_FORM_XFORM_XT6_IMM5_VB5 = 116
+PPC_INSN_FORM_XX3FORM_2 = 117
+PPC_INSN_FORM_XX4FORM = 118
+PPC_INSN_FORM_X_RD6_IMM8 = 119
+PPC_INSN_FORM_XX2FORM_2 = 120
+PPC_INSN_FORM_BFORM_3 = 121
+PPC_INSN_FORM_BFORM_3_AT = 122
 PPC_INSN_FORM_B_BO_MASK = 0x03e00000
 PPC_INSN_FORM_XL_BO_MASK = 0x03e00000
 PPC_INSN_FORM_B_BI_MASK = 0x001f0000
diff --git a/bindings/python/capstone/sh_const.py b/bindings/python/capstone/sh_const.py
index da02844bd..5a1f05193 100644
--- a/bindings/python/capstone/sh_const.py
+++ b/bindings/python/capstone/sh_const.py
@@ -140,10 +140,11 @@ SH_OP_MEM_GBR_DISP = 6
 SH_OP_MEM_GBR_R0 = 7
 SH_OP_MEM_PCR = 8
 SH_OP_MEM_TBR_DISP = 9
-SH_INS_DSP_INVALID = 10
-SH_INS_DSP_DOUBLE = 11
-SH_INS_DSP_SINGLE = 12
-SH_INS_DSP_PARALLEL = 13
+
+SH_INS_DSP_INVALID = 0
+SH_INS_DSP_DOUBLE = 1
+SH_INS_DSP_SINGLE = 2
+SH_INS_DSP_PARALLEL = 3
 SH_INS_DSP_NOP = 1
 SH_INS_DSP_MOV = 2
 SH_INS_DSP_PSHL = 3
@@ -174,177 +175,180 @@ SH_INS_DSP_PLDS = 27
 SH_INS_DSP_PSWAP = 28
 SH_INS_DSP_PWAD = 29
 SH_INS_DSP_PWSB = 30
-SH_OP_DSP_INVALID = 31
-SH_OP_DSP_REG_PRE = 32
-SH_OP_DSP_REG_IND = 33
-SH_OP_DSP_REG_POST = 34
-SH_OP_DSP_REG_INDEX = 35
-SH_OP_DSP_REG = 36
-SH_OP_DSP_IMM = 37
-SH_DSP_CC_INVALID = 38
-SH_DSP_CC_NONE = 39
-SH_DSP_CC_DCT = 40
-SH_DSP_CC_DCF = 41
-SH_INS_INVALID = 42
-SH_INS_ADD_r = 43
-SH_INS_ADD = 44
-SH_INS_ADDC = 45
-SH_INS_ADDV = 46
-SH_INS_AND = 47
-SH_INS_BAND = 48
-SH_INS_BANDNOT = 49
-SH_INS_BCLR = 50
-SH_INS_BF = 51
-SH_INS_BF_S = 52
-SH_INS_BLD = 53
-SH_INS_BLDNOT = 54
-SH_INS_BOR = 55
-SH_INS_BORNOT = 56
-SH_INS_BRA = 57
-SH_INS_BRAF = 58
-SH_INS_BSET = 59
-SH_INS_BSR = 60
-SH_INS_BSRF = 61
-SH_INS_BST = 62
-SH_INS_BT = 63
-SH_INS_BT_S = 64
-SH_INS_BXOR = 65
-SH_INS_CLIPS = 66
-SH_INS_CLIPU = 67
-SH_INS_CLRDMXY = 68
-SH_INS_CLRMAC = 69
-SH_INS_CLRS = 70
-SH_INS_CLRT = 71
-SH_INS_CMP_EQ = 72
-SH_INS_CMP_GE = 73
-SH_INS_CMP_GT = 74
-SH_INS_CMP_HI = 75
-SH_INS_CMP_HS = 76
-SH_INS_CMP_PL = 77
-SH_INS_CMP_PZ = 78
-SH_INS_CMP_STR = 79
-SH_INS_DIV0S = 80
-SH_INS_DIV0U = 81
-SH_INS_DIV1 = 82
-SH_INS_DIVS = 83
-SH_INS_DIVU = 84
-SH_INS_DMULS_L = 85
-SH_INS_DMULU_L = 86
-SH_INS_DT = 87
-SH_INS_EXTS_B = 88
-SH_INS_EXTS_W = 89
-SH_INS_EXTU_B = 90
-SH_INS_EXTU_W = 91
-SH_INS_FABS = 92
-SH_INS_FADD = 93
-SH_INS_FCMP_EQ = 94
-SH_INS_FCMP_GT = 95
-SH_INS_FCNVDS = 96
-SH_INS_FCNVSD = 97
-SH_INS_FDIV = 98
-SH_INS_FIPR = 99
-SH_INS_FLDI0 = 100
-SH_INS_FLDI1 = 101
-SH_INS_FLDS = 102
-SH_INS_FLOAT = 103
-SH_INS_FMAC = 104
-SH_INS_FMOV = 105
-SH_INS_FMUL = 106
-SH_INS_FNEG = 107
-SH_INS_FPCHG = 108
-SH_INS_FRCHG = 109
-SH_INS_FSCA = 110
-SH_INS_FSCHG = 111
-SH_INS_FSQRT = 112
-SH_INS_FSRRA = 113
-SH_INS_FSTS = 114
-SH_INS_FSUB = 115
-SH_INS_FTRC = 116
-SH_INS_FTRV = 117
-SH_INS_ICBI = 118
-SH_INS_JMP = 119
-SH_INS_JSR = 120
-SH_INS_JSR_N = 121
-SH_INS_LDBANK = 122
-SH_INS_LDC = 123
-SH_INS_LDRC = 124
-SH_INS_LDRE = 125
-SH_INS_LDRS = 126
-SH_INS_LDS = 127
-SH_INS_LDTLB = 128
-SH_INS_MAC_L = 129
-SH_INS_MAC_W = 130
-SH_INS_MOV = 131
-SH_INS_MOVA = 132
-SH_INS_MOVCA = 133
-SH_INS_MOVCO = 134
-SH_INS_MOVI20 = 135
-SH_INS_MOVI20S = 136
-SH_INS_MOVLI = 137
-SH_INS_MOVML = 138
-SH_INS_MOVMU = 139
-SH_INS_MOVRT = 140
-SH_INS_MOVT = 141
-SH_INS_MOVU = 142
-SH_INS_MOVUA = 143
-SH_INS_MUL_L = 144
-SH_INS_MULR = 145
-SH_INS_MULS_W = 146
-SH_INS_MULU_W = 147
-SH_INS_NEG = 148
-SH_INS_NEGC = 149
-SH_INS_NOP = 150
-SH_INS_NOT = 151
-SH_INS_NOTT = 152
-SH_INS_OCBI = 153
-SH_INS_OCBP = 154
-SH_INS_OCBWB = 155
-SH_INS_OR = 156
-SH_INS_PREF = 157
-SH_INS_PREFI = 158
-SH_INS_RESBANK = 159
-SH_INS_ROTCL = 160
-SH_INS_ROTCR = 161
-SH_INS_ROTL = 162
-SH_INS_ROTR = 163
-SH_INS_RTE = 164
-SH_INS_RTS = 165
-SH_INS_RTS_N = 166
-SH_INS_RTV_N = 167
-SH_INS_SETDMX = 168
-SH_INS_SETDMY = 169
-SH_INS_SETRC = 170
-SH_INS_SETS = 171
-SH_INS_SETT = 172
-SH_INS_SHAD = 173
-SH_INS_SHAL = 174
-SH_INS_SHAR = 175
-SH_INS_SHLD = 176
-SH_INS_SHLL = 177
-SH_INS_SHLL16 = 178
-SH_INS_SHLL2 = 179
-SH_INS_SHLL8 = 180
-SH_INS_SHLR = 181
-SH_INS_SHLR16 = 182
-SH_INS_SHLR2 = 183
-SH_INS_SHLR8 = 184
-SH_INS_SLEEP = 185
-SH_INS_STBANK = 186
-SH_INS_STC = 187
-SH_INS_STS = 188
-SH_INS_SUB = 189
-SH_INS_SUBC = 190
-SH_INS_SUBV = 191
-SH_INS_SWAP_B = 192
-SH_INS_SWAP_W = 193
-SH_INS_SYNCO = 194
-SH_INS_TAS = 195
-SH_INS_TRAPA = 196
-SH_INS_TST = 197
-SH_INS_XOR = 198
-SH_INS_XTRCT = 199
-SH_INS_DSP = 200
-SH_INS_ENDING = 201
+
+SH_OP_DSP_INVALID = 0
+SH_OP_DSP_REG_PRE = 1
+SH_OP_DSP_REG_IND = 2
+SH_OP_DSP_REG_POST = 3
+SH_OP_DSP_REG_INDEX = 4
+SH_OP_DSP_REG = 5
+SH_OP_DSP_IMM = 6
+
+SH_DSP_CC_INVALID = 0
+SH_DSP_CC_NONE = 1
+SH_DSP_CC_DCT = 2
+SH_DSP_CC_DCF = 3
+
+SH_INS_INVALID = 0
+SH_INS_ADD_r = 1
+SH_INS_ADD = 2
+SH_INS_ADDC = 3
+SH_INS_ADDV = 4
+SH_INS_AND = 5
+SH_INS_BAND = 6
+SH_INS_BANDNOT = 7
+SH_INS_BCLR = 8
+SH_INS_BF = 9
+SH_INS_BF_S = 10
+SH_INS_BLD = 11
+SH_INS_BLDNOT = 12
+SH_INS_BOR = 13
+SH_INS_BORNOT = 14
+SH_INS_BRA = 15
+SH_INS_BRAF = 16
+SH_INS_BSET = 17
+SH_INS_BSR = 18
+SH_INS_BSRF = 19
+SH_INS_BST = 20
+SH_INS_BT = 21
+SH_INS_BT_S = 22
+SH_INS_BXOR = 23
+SH_INS_CLIPS = 24
+SH_INS_CLIPU = 25
+SH_INS_CLRDMXY = 26
+SH_INS_CLRMAC = 27
+SH_INS_CLRS = 28
+SH_INS_CLRT = 29
+SH_INS_CMP_EQ = 30
+SH_INS_CMP_GE = 31
+SH_INS_CMP_GT = 32
+SH_INS_CMP_HI = 33
+SH_INS_CMP_HS = 34
+SH_INS_CMP_PL = 35
+SH_INS_CMP_PZ = 36
+SH_INS_CMP_STR = 37
+SH_INS_DIV0S = 38
+SH_INS_DIV0U = 39
+SH_INS_DIV1 = 40
+SH_INS_DIVS = 41
+SH_INS_DIVU = 42
+SH_INS_DMULS_L = 43
+SH_INS_DMULU_L = 44
+SH_INS_DT = 45
+SH_INS_EXTS_B = 46
+SH_INS_EXTS_W = 47
+SH_INS_EXTU_B = 48
+SH_INS_EXTU_W = 49
+SH_INS_FABS = 50
+SH_INS_FADD = 51
+SH_INS_FCMP_EQ = 52
+SH_INS_FCMP_GT = 53
+SH_INS_FCNVDS = 54
+SH_INS_FCNVSD = 55
+SH_INS_FDIV = 56
+SH_INS_FIPR = 57
+SH_INS_FLDI0 = 58
+SH_INS_FLDI1 = 59
+SH_INS_FLDS = 60
+SH_INS_FLOAT = 61
+SH_INS_FMAC = 62
+SH_INS_FMOV = 63
+SH_INS_FMUL = 64
+SH_INS_FNEG = 65
+SH_INS_FPCHG = 66
+SH_INS_FRCHG = 67
+SH_INS_FSCA = 68
+SH_INS_FSCHG = 69
+SH_INS_FSQRT = 70
+SH_INS_FSRRA = 71
+SH_INS_FSTS = 72
+SH_INS_FSUB = 73
+SH_INS_FTRC = 74
+SH_INS_FTRV = 75
+SH_INS_ICBI = 76
+SH_INS_JMP = 77
+SH_INS_JSR = 78
+SH_INS_JSR_N = 79
+SH_INS_LDBANK = 80
+SH_INS_LDC = 81
+SH_INS_LDRC = 82
+SH_INS_LDRE = 83
+SH_INS_LDRS = 84
+SH_INS_LDS = 85
+SH_INS_LDTLB = 86
+SH_INS_MAC_L = 87
+SH_INS_MAC_W = 88
+SH_INS_MOV = 89
+SH_INS_MOVA = 90
+SH_INS_MOVCA = 91
+SH_INS_MOVCO = 92
+SH_INS_MOVI20 = 93
+SH_INS_MOVI20S = 94
+SH_INS_MOVLI = 95
+SH_INS_MOVML = 96
+SH_INS_MOVMU = 97
+SH_INS_MOVRT = 98
+SH_INS_MOVT = 99
+SH_INS_MOVU = 100
+SH_INS_MOVUA = 101
+SH_INS_MUL_L = 102
+SH_INS_MULR = 103
+SH_INS_MULS_W = 104
+SH_INS_MULU_W = 105
+SH_INS_NEG = 106
+SH_INS_NEGC = 107
+SH_INS_NOP = 108
+SH_INS_NOT = 109
+SH_INS_NOTT = 110
+SH_INS_OCBI = 111
+SH_INS_OCBP = 112
+SH_INS_OCBWB = 113
+SH_INS_OR = 114
+SH_INS_PREF = 115
+SH_INS_PREFI = 116
+SH_INS_RESBANK = 117
+SH_INS_ROTCL = 118
+SH_INS_ROTCR = 119
+SH_INS_ROTL = 120
+SH_INS_ROTR = 121
+SH_INS_RTE = 122
+SH_INS_RTS = 123
+SH_INS_RTS_N = 124
+SH_INS_RTV_N = 125
+SH_INS_SETDMX = 126
+SH_INS_SETDMY = 127
+SH_INS_SETRC = 128
+SH_INS_SETS = 129
+SH_INS_SETT = 130
+SH_INS_SHAD = 131
+SH_INS_SHAL = 132
+SH_INS_SHAR = 133
+SH_INS_SHLD = 134
+SH_INS_SHLL = 135
+SH_INS_SHLL16 = 136
+SH_INS_SHLL2 = 137
+SH_INS_SHLL8 = 138
+SH_INS_SHLR = 139
+SH_INS_SHLR16 = 140
+SH_INS_SHLR2 = 141
+SH_INS_SHLR8 = 142
+SH_INS_SLEEP = 143
+SH_INS_STBANK = 144
+SH_INS_STC = 145
+SH_INS_STS = 146
+SH_INS_SUB = 147
+SH_INS_SUBC = 148
+SH_INS_SUBV = 149
+SH_INS_SWAP_B = 150
+SH_INS_SWAP_W = 151
+SH_INS_SYNCO = 152
+SH_INS_TAS = 153
+SH_INS_TRAPA = 154
+SH_INS_TST = 155
+SH_INS_XOR = 156
+SH_INS_XTRCT = 157
+SH_INS_DSP = 158
+SH_INS_ENDING = 159
 
 SH_GRP_INVALID = 0
 SH_GRP_JUMP = 1
diff --git a/bindings/python/capstone/sparc_const.py b/bindings/python/capstone/sparc_const.py
index e009800e7..19de48d73 100644
--- a/bindings/python/capstone/sparc_const.py
+++ b/bindings/python/capstone/sparc_const.py
@@ -39,6 +39,8 @@ SPARC_HINT_INVALID = 0
 SPARC_HINT_A = 1<<0
 SPARC_HINT_PT = 1<<1
 SPARC_HINT_PN = 1<<2
+SPARC_HINT_A_PN = SPARC_HINT_A|SPARC_HINT_PN
+SPARC_HINT_A_PT = SPARC_HINT_A|SPARC_HINT_PT
 
 SPARC_OP_INVALID = 0
 SPARC_OP_REG = 1
diff --git a/bindings/python/capstone/tricore_const.py b/bindings/python/capstone/tricore_const.py
index 5a7a7f7ea..3353f3209 100644
--- a/bindings/python/capstone/tricore_const.py
+++ b/bindings/python/capstone/tricore_const.py
@@ -461,10 +461,11 @@ TRICORE_INS_XOR_LT = 388
 TRICORE_INS_XOR_NE = 389
 TRICORE_INS_XOR = 390
 TRICORE_INS_ENDING = 391
-TRICORE_GRP_INVALID = 392
-TRICORE_GRP_CALL = 393
-TRICORE_GRP_JUMP = 394
-TRICORE_GRP_ENDING = 395
+
+TRICORE_GRP_INVALID = 0
+TRICORE_GRP_CALL = 1
+TRICORE_GRP_JUMP = 2
+TRICORE_GRP_ENDING = 3
 
 TRICORE_FEATURE_INVALID = 0
 TRICORE_FEATURE_HasV110 = 128
diff --git a/bindings/python/capstone/x86_const.py b/bindings/python/capstone/x86_const.py
index 0f193a50c..ae3f93c30 100644
--- a/bindings/python/capstone/x86_const.py
+++ b/bindings/python/capstone/x86_const.py
@@ -398,6 +398,7 @@ X86_AVX_RM_RN = 1
 X86_AVX_RM_RD = 2
 X86_AVX_RM_RU = 3
 X86_AVX_RM_RZ = 4
+X86_PREFIX_0 = 0x0
 X86_PREFIX_LOCK = 0xf0
 X86_PREFIX_REP = 0xf3
 X86_PREFIX_REPE = 0xf3
diff --git a/bindings/python/cstest_py/README.md b/bindings/python/cstest_py/README.md
new file mode 100644
index 000000000..e6587450d
--- /dev/null
+++ b/bindings/python/cstest_py/README.md
@@ -0,0 +1,4 @@
+## Python cstest
+
+This is the equivalent testing tool to `suite/cstest/`. It consumes the `yaml` test files
+in `<repo-root>/tests/` and reports the results.
diff --git a/bindings/python/cstest_py/pyproject.toml b/bindings/python/cstest_py/pyproject.toml
new file mode 100644
index 000000000..34b27c5aa
--- /dev/null
+++ b/bindings/python/cstest_py/pyproject.toml
@@ -0,0 +1,18 @@
+# Copyright © 2024 Rot127 <unisono@quyllur.org>
+# SPDX-License-Identifier: BSD-3
+
+[project]
+name = "cstest_py"
+version = "0.1.0"
+dependencies = [
+  "pyyaml >= 6.0.2",
+  "capstone >= 5.0.0",
+]
+requires-python = ">= 3.8"
+
+[tool.setuptools]
+packages = ["cstest_py"]
+package-dir = {"" = "src"}
+
+[project.scripts]
+cstest_py = "cstest_py.cstest:main"
diff --git a/bindings/python/cstest_py/src/cstest_py/compare.py b/bindings/python/cstest_py/src/cstest_py/compare.py
new file mode 100644
index 000000000..7e679ec55
--- /dev/null
+++ b/bindings/python/cstest_py/src/cstest_py/compare.py
@@ -0,0 +1,337 @@
+# Copyright © 2024 Rot127 <unisono@quyllur.org>
+# SPDX-License-Identifier: BSD-3
+
+# Typing for Python3.8
+from __future__ import annotations
+
+import struct
+import capstone
+import re
+from capstone import arm_const
+from capstone import aarch64_const
+from capstone import m68k_const
+from capstone import mips_const
+from capstone import ppc_const
+from capstone import sparc_const
+from capstone import sysz_const
+from capstone import x86_const
+from capstone import xcore_const
+from capstone import tms320c64x_const
+from capstone import m680x_const
+from capstone import evm_const
+from capstone import mos65xx_const
+from capstone import wasm_const
+from capstone import bpf_const
+from capstone import riscv_const
+from capstone import sh_const
+from capstone import tricore_const
+from capstone import alpha_const
+from capstone import hppa_const
+from capstone import loongarch_const
+
+
+def cs_const_getattr(identifier: str):
+    attr = getattr(capstone, identifier, None)
+    if attr is not None:
+        return attr
+    attr = getattr(arm_const, identifier, None)
+    if attr is not None:
+        return attr
+    attr = getattr(aarch64_const, identifier, None)
+    if attr is not None:
+        return attr
+    attr = getattr(m68k_const, identifier, None)
+    if attr is not None:
+        return attr
+    attr = getattr(mips_const, identifier, None)
+    if attr is not None:
+        return attr
+    attr = getattr(ppc_const, identifier, None)
+    if attr is not None:
+        return attr
+    attr = getattr(sparc_const, identifier, None)
+    if attr is not None:
+        return attr
+    attr = getattr(sysz_const, identifier, None)
+    if attr is not None:
+        return attr
+    attr = getattr(x86_const, identifier, None)
+    if attr is not None:
+        return attr
+    attr = getattr(xcore_const, identifier, None)
+    if attr is not None:
+        return attr
+    attr = getattr(tms320c64x_const, identifier, None)
+    if attr is not None:
+        return attr
+    attr = getattr(m680x_const, identifier, None)
+    if attr is not None:
+        return attr
+    attr = getattr(evm_const, identifier, None)
+    if attr is not None:
+        return attr
+    attr = getattr(mos65xx_const, identifier, None)
+    if attr is not None:
+        return attr
+    attr = getattr(wasm_const, identifier, None)
+    if attr is not None:
+        return attr
+    attr = getattr(bpf_const, identifier, None)
+    if attr is not None:
+        return attr
+    attr = getattr(riscv_const, identifier, None)
+    if attr is not None:
+        return attr
+    attr = getattr(sh_const, identifier, None)
+    if attr is not None:
+        return attr
+    attr = getattr(tricore_const, identifier, None)
+    if attr is not None:
+        return attr
+    attr = getattr(alpha_const, identifier, None)
+    if attr is not None:
+        return attr
+    attr = getattr(hppa_const, identifier, None)
+    if attr is not None:
+        return attr
+    attr = getattr(loongarch_const, identifier, None)
+    if attr is not None:
+        return attr
+    raise ValueError(f"Python capstone doesn't have the constant: {identifier}")
+
+
+def twos_complement(val, bits):
+    if (val & (1 << (bits - 1))) != 0:
+        val = val - (1 << bits)
+    return val & ((1 << bits) - 1)
+
+
+def normalize_asm_text(text: str, arch_bits: int) -> str:
+    text = text.strip()
+    text = re.sub(r"\s+", " ", text)
+    # Replace hex numbers with decimals
+    for hex_num in re.findall(r"0x[0-9a-fA-F]+", text):
+        text = re.sub(hex_num, f"{int(hex_num, base=16)}", text, count=1)
+    # Replace negatives with twos-complement
+    for num in re.findall(r"-\d+", text):
+        n = twos_complement(int(num, base=10), arch_bits)
+        text = re.sub(num, f"{n}", text)
+    text = text.lower()
+    return text
+
+
+def compare_asm_text(
+    a_insn: capstone.CsInsn, expected: None | str, arch_bits: int
+) -> bool:
+    if expected is None:
+        return True
+    from cstest_py.cstest import log
+
+    actual = f"{a_insn.mnemonic} {a_insn.op_str}"
+    actual = normalize_asm_text(actual, arch_bits)
+    expected = normalize_asm_text(expected, arch_bits)
+
+    if actual != expected:
+        log.error(
+            "Normalized asm-text doesn't match:\n"
+            f"decoded:  '{actual}'\n"
+            f"expected: '{expected}'\n"
+        )
+        return False
+    return True
+
+
+def compare_str(actual: str, expected: None | str, msg: str) -> bool:
+    if expected is None:
+        return True
+    from cstest_py.cstest import log
+
+    if actual != expected:
+        log.error(f"{msg}: {actual} != {expected}")
+        return False
+    return True
+
+
+def compare_tbool(actual: bool, expected: None | int, msg: str) -> bool:
+    if expected is None:
+        return True
+    from cstest_py.cstest import log
+
+    if expected == 0:
+        # Unset
+        return True
+
+    if (expected < 0 and actual) or (expected > 0 and not actual):
+        log.error(f"{msg}: {actual} != {expected}")
+        return False
+    return True
+
+
+def compare_uint8(actual: int, expected: None | int, msg: str) -> bool:
+    if expected is None:
+        return True
+    from cstest_py.cstest import log
+
+    actual = actual & 0xFF
+    expected = expected & 0xFF
+    if actual != expected:
+        log.error(f"{msg}: {actual} != {expected}")
+        return False
+    return True
+
+
+def compare_int8(actual: int, expected: None | int, msg: str) -> bool:
+    if expected is None:
+        return True
+    from cstest_py.cstest import log
+
+    actual = actual & 0xFF
+    expected = expected & 0xFF
+    if actual != expected:
+        log.error(f"{msg}: {actual} != {expected}")
+        return False
+    return True
+
+
+def compare_uint16(actual: int, expected: None | int, msg: str) -> bool:
+    if expected is None:
+        return True
+    from cstest_py.cstest import log
+
+    actual = actual & 0xFFFF
+    expected = expected & 0xFFFF
+    if actual != expected:
+        log.error(f"{msg}: {actual} != {expected}")
+        return False
+    return True
+
+
+def compare_int16(actual: int, expected: None | int, msg: str) -> bool:
+    if expected is None:
+        return True
+    from cstest_py.cstest import log
+
+    actual = actual & 0xFFFF
+    expected = expected & 0xFFFF
+    if actual != expected:
+        log.error(f"{msg}: {actual} != {expected}")
+        return False
+    return True
+
+
+def compare_uint32(actual: int, expected: None | int, msg: str) -> bool:
+    if expected is None:
+        return True
+    from cstest_py.cstest import log
+
+    actual = actual & 0xFFFFFFFF
+    expected = expected & 0xFFFFFFFF
+    if actual != expected:
+        log.error(f"{msg}: {actual} != {expected}")
+        return False
+    return True
+
+
+def compare_int32(actual: int, expected: None | int, msg: str) -> bool:
+    if expected is None:
+        return True
+    from cstest_py.cstest import log
+
+    actual = actual & 0xFFFFFFFF
+    expected = expected & 0xFFFFFFFF
+    if actual != expected:
+        log.error(f"{msg}: {actual} != {expected}")
+        return False
+    return True
+
+
+def compare_uint64(actual: int, expected: None | int, msg: str) -> bool:
+    if expected is None:
+        return True
+    from cstest_py.cstest import log
+
+    actual = actual & 0xFFFFFFFFFFFFFFFF
+    expected = expected & 0xFFFFFFFFFFFFFFFF
+    if actual != expected:
+        log.error(f"{msg}: {actual} != {expected}")
+        return False
+    return True
+
+
+def compare_int64(actual: int, expected: None | int, msg: str) -> bool:
+    if expected is None:
+        return True
+    from cstest_py.cstest import log
+
+    actual = actual & 0xFFFFFFFFFFFFFFFF
+    expected = expected & 0xFFFFFFFFFFFFFFFF
+    if actual != expected:
+        log.error(f"{msg}: {actual} != {expected}")
+        return False
+    return True
+
+
+def compare_fp(actual: float, expected: None | float, msg: str) -> bool:
+    if expected is None:
+        return True
+    from cstest_py.cstest import log
+
+    def floatToBits(f):
+        return struct.unpack("=L", struct.pack("=f", f))[0]
+
+    if floatToBits(actual) != floatToBits(expected):
+        log.error(f"{msg}: {actual} != {expected}")
+        return False
+    return True
+
+
+def compare_dp(actual: float, expected: None | float, msg: str) -> bool:
+    if expected is None:
+        return True
+    from cstest_py.cstest import log
+
+    def doubleToBits(f):
+        return struct.unpack("=Q", struct.pack("=d", f))[0]
+
+    if doubleToBits(actual) != doubleToBits(expected):
+        log.error(f"{msg}: {actual} != {expected}")
+        return False
+    return True
+
+
+def compare_enum(actual, expected: None | str, msg: str) -> bool:
+    if expected is None:
+        return True
+    from cstest_py.cstest import log
+
+    enum_val = cs_const_getattr(expected)
+    if actual != enum_val:
+        log.error(f"{msg}: {actual} != {expected} ({enum_val})")
+        return False
+    return True
+
+
+def compare_bit_flags(actual: int, expected: None | list[str], msg: str) -> bool:
+    if expected is None:
+        return True
+    from cstest_py.cstest import log
+
+    for flag in expected:
+        enum_val = cs_const_getattr(flag)
+        if not actual & enum_val:
+            log.error(f"{msg}: In {actual:x} the flag {expected} isn't set.")
+            return False
+    return True
+
+
+def compare_reg(
+    insn: capstone.CsInsn, actual: int, expected: None | str, msg: str
+) -> bool:
+    if expected is None:
+        return True
+    from cstest_py.cstest import log
+
+    if insn.reg_name(actual) != expected:
+        log.error(f"{msg}: {actual} != {expected}")
+        return False
+    return True
diff --git a/bindings/python/cstest_py/src/cstest_py/cs_modes.py b/bindings/python/cstest_py/src/cstest_py/cs_modes.py
new file mode 100644
index 000000000..0290bca79
--- /dev/null
+++ b/bindings/python/cstest_py/src/cstest_py/cs_modes.py
@@ -0,0 +1,41 @@
+# Copyright © 2024 Rot127 <unisono@quyllur.org>
+# SPDX-License-Identifier: BSD-3
+
+import capstone as cs
+
+configs = {
+    "CS_OPT_DETAIL": {"type": cs.CS_OPT_DETAIL, "val": cs.CS_OPT_ON},
+    "CS_OPT_DETAIL_REAL": {
+        "type": cs.CS_OPT_DETAIL,
+        "val": cs.CS_OPT_DETAIL_REAL | cs.CS_OPT_ON,
+    },
+    "CS_OPT_SKIPDATA": {"type": cs.CS_OPT_SKIPDATA, "val": cs.CS_OPT_ON},
+    "CS_OPT_UNSIGNED": {"type": cs.CS_OPT_UNSIGNED, "val": cs.CS_OPT_ON},
+    "CS_OPT_NO_BRANCH_OFFSET": {
+        "type": cs.CS_OPT_NO_BRANCH_OFFSET,
+        "val": cs.CS_OPT_ON,
+    },
+    "CS_OPT_SYNTAX_DEFAULT": {
+        "type": cs.CS_OPT_SYNTAX,
+        "val": cs.CS_OPT_SYNTAX_DEFAULT,
+    },
+    "CS_OPT_SYNTAX_INTEL": {"type": cs.CS_OPT_SYNTAX, "val": cs.CS_OPT_SYNTAX_INTEL},
+    "CS_OPT_SYNTAX_ATT": {"type": cs.CS_OPT_SYNTAX, "val": cs.CS_OPT_SYNTAX_ATT},
+    "CS_OPT_SYNTAX_NOREGNAME": {
+        "type": cs.CS_OPT_SYNTAX,
+        "val": cs.CS_OPT_SYNTAX_NOREGNAME,
+    },
+    "CS_OPT_SYNTAX_MASM": {"type": cs.CS_OPT_SYNTAX, "val": cs.CS_OPT_SYNTAX_MASM},
+    "CS_OPT_SYNTAX_MOTOROLA": {
+        "type": cs.CS_OPT_SYNTAX,
+        "val": cs.CS_OPT_SYNTAX_MOTOROLA,
+    },
+    "CS_OPT_SYNTAX_CS_REG_ALIAS": {
+        "type": cs.CS_OPT_SYNTAX,
+        "val": cs.CS_OPT_SYNTAX_CS_REG_ALIAS,
+    },
+    "CS_OPT_SYNTAX_PERCENT": {
+        "type": cs.CS_OPT_SYNTAX,
+        "val": cs.CS_OPT_SYNTAX_PERCENT,
+    },
+}
diff --git a/bindings/python/cstest_py/src/cstest_py/cstest.py b/bindings/python/cstest_py/src/cstest_py/cstest.py
new file mode 100755
index 000000000..4fd244914
--- /dev/null
+++ b/bindings/python/cstest_py/src/cstest_py/cstest.py
@@ -0,0 +1,493 @@
+#!/usr/bin/env python3
+# Copyright © 2024 Rot127 <unisono@quyllur.org>
+# SPDX-License-Identifier: BSD-3
+
+# Typing for Python3.8
+from __future__ import annotations
+
+import argparse
+import logging
+import subprocess as sp
+import sys
+import os
+import yaml
+import capstone
+import traceback
+
+from capstone import CsInsn, Cs, CS_ARCH_AARCH64, CS_MODE_64, CS_MODE_16
+
+from cstest_py.cs_modes import configs
+from cstest_py.details import compare_details
+from cstest_py.compare import (
+    compare_asm_text,
+    compare_str,
+    compare_tbool,
+    compare_uint32,
+)
+from enum import Enum
+from pathlib import Path
+
+log = logging.getLogger("__name__")
+
+
+def get_cs_int_attr(cs, attr: str, err_msg_pre: str):
+    try:
+        attr_int = getattr(cs, attr)
+        if not isinstance(attr_int, int):
+            raise AttributeError(f"{attr} not found")
+        return attr_int
+    except AttributeError:
+        log.warning(f"{err_msg_pre}: Capstone doesn't have the attribute '{attr}'")
+        return None
+
+
+def arch_bits(arch: int, mode: int) -> int:
+    if arch == CS_ARCH_AARCH64 or mode & CS_MODE_64:
+        return 64
+    elif mode & CS_MODE_16:
+        return 16
+    return 32
+
+
+class TestResult(Enum):
+    SUCCESS = 0
+    FAILED = 1
+    SKIPPED = 2
+    ERROR = 3
+
+
+class TestStats:
+    def __init__(self, total_file_count: int):
+        self.total_file_count = total_file_count
+        self.valid_test_files = 0
+        self.test_case_count = 0
+        self.success = 0
+        self.failed = 0
+        self.skipped = 0
+        self.errors = 0
+        self.invalid_files = 0
+        self.total_valid_files = 0
+        self.err_msgs: list[str] = list()
+        self.failing_files = set()
+
+    def add_failing_file(self, test_file: Path):
+        self.failing_files.add(test_file)
+
+    def add_error_msg(self, msg: str):
+        self.err_msgs.append(msg)
+
+    def add_invalid_file_dp(self, tfile: Path):
+        self.invalid_files += 1
+        self.errors += 1
+        self.add_failing_file(tfile)
+
+    def add_test_case_data_point(self, dp: TestResult):
+        if dp == TestResult.SUCCESS:
+            self.success += 1
+        elif dp == TestResult.FAILED:
+            self.failed += 1
+        elif dp == TestResult.SKIPPED:
+            self.skipped += 1
+        elif dp == TestResult.ERROR:
+            self.errors += 1
+            self.failed += 1
+        else:
+            raise ValueError(f"Unhandled TestResult: {dp}")
+
+    def set_total_valid_files(self, total_valid_files: int):
+        self.total_valid_files = total_valid_files
+
+    def set_total_test_cases(self, total_test_cases: int):
+        self.test_case_count = total_test_cases
+
+    def get_test_case_count(self) -> int:
+        return self.test_case_count
+
+    def print_evaluate(self):
+        if self.total_file_count == 0:
+            log.error("No test files found!")
+            exit(-1)
+        if self.test_case_count == 0:
+            log.error("No test cases found!")
+            exit(-1)
+        if self.failing_files:
+            print("Test files with failures:")
+            for tf in self.failing_files:
+                print(f" - {tf}")
+            print()
+        if self.err_msgs:
+            print("Error messages:")
+            for error in self.err_msgs:
+                print(f" - {error}")
+
+        print("\n-----------------------------------------")
+        print("Test run statistics\n")
+        print(f"Valid files: {self.total_valid_files}")
+        print(f"Invalid files: {self.invalid_files}")
+        print(f"Errors: {self.errors}\n")
+        print("Test cases:")
+        print(f"\tTotal: {self.test_case_count}")
+        print(f"\tSuccessful: {self.success}")
+        print(f"\tSkipped: {self.skipped}")
+        print(f"\tFailed: {self.failed}")
+        print("-----------------------------------------")
+        print("")
+
+        if self.test_case_count != self.success + self.failed + self.skipped:
+            log.error(
+                "Inconsistent statistics: total != successful + failed + skipped\n"
+            )
+
+        if self.errors != 0:
+            log.error("Failed with errors\n")
+            exit(-1)
+        elif self.failed != 0:
+            log.warning("Not all tests succeeded\n")
+            exit(-1)
+        log.info("All tests succeeded.\n")
+        exit(0)
+
+
+class TestInput:
+    def __init__(self, input_dict: dict):
+        self.input_dict = input_dict
+        if "bytes" not in self.input_dict:
+            raise ValueError("Error: 'Missing required mapping field'\nField: 'bytes'.")
+        if "options" not in self.input_dict:
+            raise ValueError(
+                "Error: 'Missing required mapping field'\nField: 'options'."
+            )
+        if "arch" not in self.input_dict:
+            raise ValueError("Error: 'Missing required mapping field'\nField: 'arch'.")
+        self.in_bytes = bytes(self.input_dict["bytes"])
+        self.options = self.input_dict["options"]
+        self.arch = self.input_dict["arch"]
+
+        self.name = "" if "name" not in self.input_dict else self.input_dict["name"]
+        if "address" not in self.input_dict:
+            self.address: int = 0
+        else:
+            assert isinstance(self.input_dict["address"], int)
+            self.address = self.input_dict["address"]
+        self.handle = None
+        self.arch_bits = 0
+
+    def setup(self):
+        log.debug(f"Init {self}")
+        arch = get_cs_int_attr(capstone, self.arch, "CS_ARCH")
+        if arch is None:
+            cs_name = f"CS_ARCH_{self.arch.upper()}"
+            arch = get_cs_int_attr(capstone, cs_name, "CS_ARCH")
+            if arch is None:
+                raise ValueError(
+                    f"Couldn't init architecture as '{self.arch}' or '{cs_name}'.\n"
+                    f"'{self.arch}' is not mapped to a capstone architecture."
+                )
+        new_mode = 0
+        for opt in self.options:
+            if "CS_MODE_" in opt:
+                mode = get_cs_int_attr(capstone, opt, "CS_OPT")
+                if mode is not None:
+                    new_mode |= mode
+                    continue
+        self.handle = Cs(arch, new_mode)
+
+        for opt in self.options:
+            if "CS_MODE_" in opt:
+                continue
+            if "CS_OPT_" in opt and opt in configs:
+                mtype = configs[opt]["type"]
+                val = configs[opt]["val"]
+                self.handle.option(mtype, val)
+                continue
+            log.warning(f"Option: '{opt}' not used")
+
+        self.arch_bits = arch_bits(self.handle.arch, self.handle.mode)
+        log.debug("Init done")
+
+    def decode(self) -> list[CsInsn]:
+        if not self.handle:
+            raise ValueError("self.handle is None. Must be setup before.")
+        return [i for i in self.handle.disasm(self.in_bytes, self.address)]
+
+    def __str__(self):
+        default = (
+            f"TestInput {{ arch: {self.arch}, options: {self.options}, "
+            f"addr: {self.address:x}, bytes: [ {','.join([f'{b:#04x}' for b in self.in_bytes])} ] }}"
+        )
+        if self.name:
+            return f"{self.name} -- {default}"
+        return default
+
+
+class TestExpected:
+    def __init__(self, expected_dict: dict):
+        self.expected_dict = expected_dict
+        self.insns = (
+            list() if "insns" not in self.expected_dict else self.expected_dict["insns"]
+        )
+
+    def compare(self, actual_insns: list[CsInsn], bits: int) -> TestResult:
+        if len(actual_insns) != len(self.insns):
+            log.error(
+                "Number of decoded instructions don't match (actual != expected): "
+                f"{len(actual_insns)} != {len(self.insns):#x}"
+            )
+            return TestResult.FAILED
+        for a_insn, e_insn in zip(actual_insns, self.insns):
+            if not compare_asm_text(
+                a_insn,
+                e_insn.get("asm_text"),
+                bits,
+            ):
+                return TestResult.FAILED
+
+            if not compare_str(a_insn.mnemonic, e_insn.get("mnemonic"), "mnemonic"):
+                return TestResult.FAILED
+
+            if not compare_str(a_insn.op_str, e_insn.get("op_str"), "op_str"):
+                return TestResult.FAILED
+
+            if not compare_uint32(a_insn.id, e_insn.get("id"), "id"):
+                return TestResult.FAILED
+
+            if not compare_tbool(a_insn.is_alias, e_insn.get("is_alias"), "is_alias"):
+                return TestResult.FAILED
+
+            if not compare_uint32(a_insn.alias_id, e_insn.get("alias_id"), "alias_id"):
+                return TestResult.FAILED
+
+            if not compare_details(a_insn, e_insn.get("details")):
+                return TestResult.FAILED
+        return TestResult.SUCCESS
+
+
+class TestCase:
+    def __init__(self, test_case_dict: dict):
+        self.tc_dict = test_case_dict
+        if "input" not in self.tc_dict:
+            raise ValueError("Mandatory field 'input' missing")
+        if "expected" not in self.tc_dict:
+            raise ValueError("Mandatory field 'expected' missing")
+        self.input = TestInput(self.tc_dict["input"])
+        self.expected = TestExpected(self.tc_dict["expected"])
+        self.skip = "skip" in self.tc_dict
+        if self.skip and "skip_reason" not in self.tc_dict:
+            raise ValueError(
+                "If 'skip' field is set a 'skip_reason' field must be set as well."
+            )
+        self.skip_reason = (
+            self.tc_dict["skip_reason"] if "skip_reason" in self.tc_dict else ""
+        )
+
+    def __str__(self) -> str:
+        return f"{self.input}"
+
+    def test(self) -> TestResult:
+        if self.skip:
+            log.info(f"Skip {self}\nReason: {self.skip_reason}")
+            return TestResult.SKIPPED
+
+        try:
+            self.input.setup()
+        except Exception as e:
+            log.error(f"Setup failed at with: {e}")
+            traceback.print_exc()
+            return TestResult.ERROR
+
+        try:
+            insns = self.input.decode()
+        except Exception as e:
+            log.error(f"Decode failed with: {e}")
+            traceback.print_exc()
+            return TestResult.ERROR
+
+        try:
+            return self.expected.compare(insns, self.input.arch_bits)
+        except Exception as e:
+            log.error(f"Compare expected failed with: {e}")
+            traceback.print_exc()
+            return TestResult.ERROR
+
+
+class TestFile:
+    def __init__(self, tfile_path: Path):
+        self.path = tfile_path
+        with open(tfile_path) as f:
+            try:
+                self.content = yaml.safe_load(f)
+            except yaml.YAMLError as e:
+                raise e
+        self.test_cases = list()
+        if not self.content:
+            raise ValueError("Empty file")
+        for tc_dict in self.content["test_cases"]:
+            tc = TestCase(tc_dict)
+            self.test_cases.append(tc)
+
+    def num_test_cases(self) -> int:
+        return len(self.test_cases)
+
+    def __str__(self) -> str:
+        return f"{self.path}"
+
+
+class CSTest:
+    def __init__(self, path: Path, exclude: list[Path], include: list[Path]):
+        self.yaml_paths: list[Path] = list()
+
+        log.info(f"Search test files in {path}")
+        if path.is_file():
+            self.yaml_paths.append(path)
+        else:
+            for root, dirs, files in os.walk(path, onerror=print):
+                for file in files:
+                    f = Path(root).joinpath(file)
+                    if f.suffix not in [".yaml", ".yml"]:
+                        continue
+                    if f.name in exclude:
+                        continue
+                    if not include or f.name in include:
+                        log.debug(f"Add: {f}")
+                        self.yaml_paths.append(f)
+
+        log.info(f"Test files found: {len(self.yaml_paths)}")
+        self.stats = TestStats(len(self.yaml_paths))
+        self.test_files: list[TestFile] = list()
+
+    def parse_files(self):
+        total_test_cases = 0
+        total_files = len(self.yaml_paths)
+        count = 1
+        for tfile in self.yaml_paths:
+            print(
+                f"Parse {count}/{total_files}: {tfile.name}",
+                end=f"{' ' * 20}\r",
+                flush=True,
+            )
+            try:
+                tf = TestFile(tfile)
+                total_test_cases += tf.num_test_cases()
+                self.test_files.append(tf)
+            except yaml.YAMLError as e:
+                self.stats.add_error_msg(str(e))
+                self.stats.add_invalid_file_dp(tfile)
+                log.error("Error: 'libyaml parser error'")
+                log.error(f"{e}")
+                log.error(f"Failed to parse test file '{tfile}'")
+            except ValueError as e:
+                self.stats.add_error_msg(str(e))
+                self.stats.add_invalid_file_dp(tfile)
+                log.error(f"Error: ValueError: {e}")
+                log.error(f"Failed to parse test file '{tfile}'")
+            finally:
+                count += 1
+        self.stats.set_total_valid_files(len(self.test_files))
+        self.stats.set_total_test_cases(total_test_cases)
+        log.info(f"Found {self.stats.get_test_case_count()} test cases.{' ' * 20}")
+
+    def run_tests(self):
+        self.parse_files()
+        for tf in self.test_files:
+            log.info(f"Test file: {tf}\n")
+            for tc in tf.test_cases:
+                log.info(f"Run test: {tc}")
+                try:
+                    result = tc.test()
+                except Exception as e:
+                    result = TestResult.ERROR
+                    self.stats.add_error_msg(str(e))
+                if result == TestResult.FAILED or result == TestResult.ERROR:
+                    self.stats.add_failing_file(tf.path)
+                self.stats.add_test_case_data_point(result)
+                log.info(result)
+                print()
+        self.stats.print_evaluate()
+
+
+def get_repo_root() -> str | None:
+    res = sp.run(["git", "rev-parse", "--show-toplevel"], capture_output=True)
+    if res.stderr:
+        log.error("Could not get repository root directory.")
+        return None
+    return res.stdout.decode("utf8").strip()
+
+
+def parse_args() -> argparse.Namespace:
+    parser = argparse.ArgumentParser(
+        prog="Python CSTest",
+        description="Pyton binding cstest implementation.",
+    )
+    repo_root = get_repo_root()
+    if repo_root:
+        parser.add_argument(
+            dest="search_dir",
+            help="Directory to search for .yaml test files.",
+            default=Path(f"{repo_root}/tests/"),
+            type=Path,
+        )
+    else:
+        parser.add_argument(
+            dest="search_dir",
+            help="Directory to search for .yaml test files.",
+            required=True,
+            type=Path,
+        )
+    parser.add_argument(
+        "-e",
+        dest="exclude",
+        help="List of file names to exclude.",
+        nargs="+",
+        required=False,
+        default=list(),
+    )
+    parser.add_argument(
+        "-i",
+        dest="include",
+        help="List of file names to include.",
+        nargs="+",
+        required=False,
+        default=list(),
+    )
+    parser.add_argument(
+        "-v",
+        dest="verbosity",
+        help="Verbosity of the log messages.",
+        choices=["debug", "info", "warning", "error", "fatal", "critical"],
+        default="info",
+    )
+    arguments = parser.parse_args()
+    return arguments
+
+
+def main():
+    log_levels = {
+        "debug": logging.DEBUG,
+        "info": logging.INFO,
+        "warning": logging.WARNING,
+        "error": logging.ERROR,
+        "fatal": logging.FATAL,
+        "critical": logging.CRITICAL,
+    }
+    args = parse_args()
+    format = logging.Formatter("%(levelname)-5s - %(message)s", None, "%")
+    log.setLevel(log_levels[args.verbosity])
+
+    h1 = logging.StreamHandler(sys.stdout)
+    h1.addFilter(
+        lambda record: record.levelno >= log_levels[args.verbosity]
+        and record.levelno < logging.WARNING
+    )
+    h1.setFormatter(format)
+
+    h2 = logging.StreamHandler(sys.stderr)
+    h2.setLevel(logging.WARNING)
+    h2.setFormatter(format)
+
+    log.addHandler(h1)
+    log.addHandler(h2)
+    CSTest(args.search_dir, args.exclude, args.include).run_tests()
+
+
+if __name__ == "__main__":
+    main()
diff --git a/bindings/python/cstest_py/src/cstest_py/details.py b/bindings/python/cstest_py/src/cstest_py/details.py
new file mode 100644
index 000000000..e5236495b
--- /dev/null
+++ b/bindings/python/cstest_py/src/cstest_py/details.py
@@ -0,0 +1,1511 @@
+# Copyright © 2024 Rot127 <unisono@quyllur.org>
+# SPDX-License-Identifier: BSD-3
+
+# Typing for Python3.8
+from __future__ import annotations
+
+from capstone import (
+    Cs,
+    CsInsn,
+)
+from capstone.alpha_const import ALPHA_OP_IMM, ALPHA_OP_REG
+from capstone.bpf_const import (
+    BPF_OP_REG,
+    BPF_OP_IMM,
+    BPF_OP_OFF,
+    BPF_OP_MMEM,
+    BPF_OP_MSH,
+    BPF_OP_EXT,
+    BPF_OP_MEM,
+)
+from capstone.hppa_const import (
+    HPPA_OP_REG,
+    HPPA_OP_IMM,
+    HPPA_OP_MEM,
+    HPPA_OP_IDX_REG,
+    HPPA_OP_DISP,
+    HPPA_OP_TARGET,
+)
+from capstone.loongarch_const import (
+    LOONGARCH_OP_REG,
+    LOONGARCH_OP_IMM,
+    LOONGARCH_OP_MEM,
+)
+
+from capstone.m680x_const import (
+    M680X_OP_REGISTER,
+    M680X_OP_IMMEDIATE,
+    M680X_OP_INDEXED,
+    M680X_OP_EXTENDED,
+    M680X_OP_DIRECT,
+    M680X_OP_RELATIVE,
+    M680X_OP_CONSTANT,
+)
+
+from capstone.aarch64_const import (
+    AARCH64_OP_SME,
+    AARCH64_OP_PRED,
+    AARCH64_OP_SYSALIAS,
+    AARCH64_OP_SYSIMM,
+    AARCH64_OP_SYSREG,
+    AARCH64_OP_FP,
+    AARCH64_OP_IMM_RANGE,
+    AARCH64_OP_MEM,
+    AARCH64_OP_IMM,
+    AARCH64_OP_REG,
+)
+from capstone.m68k_const import (
+    M68K_OP_REG,
+    M68K_OP_REG_PAIR,
+    M68K_OP_IMM,
+    M68K_OP_BR_DISP,
+    M68K_OP_REG_BITS,
+    M68K_OP_FP_DOUBLE,
+    M68K_OP_FP_SINGLE,
+    M68K_OP_MEM,
+)
+from capstone.mips_const import MIPS_OP_REG, MIPS_OP_IMM, MIPS_OP_MEM
+from capstone.mos65xx_const import MOS65XX_OP_REG, MOS65XX_OP_MEM, MOS65XX_OP_IMM
+from capstone.riscv_const import RISCV_OP_MEM, RISCV_OP_IMM, RISCV_OP_REG
+from capstone.sh_const import SH_OP_REG, SH_OP_MEM, SH_OP_IMM
+from capstone.sparc_const import SPARC_OP_REG, SPARC_OP_IMM, SPARC_OP_MEM
+from capstone.sysz_const import SYSZ_OP_REG, SYSZ_OP_IMM, SYSZ_OP_MEM
+from capstone.tms320c64x_const import (
+    TMS320C64X_OP_REG,
+    TMS320C64X_OP_REGPAIR,
+    TMS320C64X_MEM_DISP_CONSTANT,
+    TMS320C64X_MEM_DISP_REGISTER,
+    TMS320C64X_OP_MEM,
+    TMS320C64X_OP_IMM,
+)
+from capstone.tricore_const import TRICORE_OP_REG, TRICORE_OP_IMM, TRICORE_OP_MEM
+from capstone.wasm_const import (
+    WASM_OP_INT7,
+    WASM_OP_VARUINT32,
+    WASM_OP_VARUINT64,
+    WASM_OP_UINT32,
+    WASM_OP_UINT64,
+    WASM_OP_IMM,
+    WASM_OP_BRTABLE,
+)
+
+from capstone.x86_const import (
+    X86_OP_MEM,
+    X86_OP_IMM,
+    X86_OP_REG,
+)
+
+from capstone.ppc_const import (
+    PPC_OP_MEM,
+    PPC_OP_IMM,
+    PPC_OP_REG,
+)
+
+from capstone.arm_const import (
+    ARM_OP_PRED,
+    ARM_OP_CIMM,
+    ARM_OP_PIMM,
+    ARM_OP_SETEND,
+    ARM_OP_SYSREG,
+    ARM_OP_BANKEDREG,
+    ARM_OP_SPSR,
+    ARM_OP_CPSR,
+    ARM_OP_SYSM,
+    ARM_OP_FP,
+    ARM_OP_MEM,
+    ARM_OP_IMM,
+    ARM_OP_REG,
+)
+from capstone.xcore_const import XCORE_OP_REG, XCORE_OP_IMM, XCORE_OP_MEM
+
+from cstest_py.compare import (
+    compare_tbool,
+    compare_uint8,
+    compare_int8,
+    compare_uint16,
+    compare_int16,
+    compare_uint32,
+    compare_int32,
+    compare_uint64,
+    compare_int64,
+    compare_fp,
+    compare_dp,
+    compare_enum,
+    compare_bit_flags,
+    compare_reg,
+)
+
+
+def test_reg_rw_access(insn: CsInsn, expected: dict):
+    if ("regs_read" not in expected or len(expected["regs_read"]) <= 0) and (
+        "regs_write" not in expected or len(expected["regs_write"]) <= 0
+    ):
+        return True
+
+    regs_read, regs_write = insn.regs_access()
+    if "regs_read" in expected and len(expected["regs_read"]) > 0:
+        if not compare_uint32(
+            len(regs_read), len(expected["regs_read"]), "regs_read_count"
+        ):
+            return False
+        for i, rreg in enumerate(regs_read):
+            if not compare_reg(insn, rreg, expected["regs_read"][i], "regs_read"):
+                return False
+
+    if "regs_write" in expected and len(expected["regs_write"]) > 0:
+        if not compare_uint32(
+            len(regs_write), len(expected["regs_write"]), "regs_write_count"
+        ):
+            return False
+        for i, wreg in enumerate(regs_write):
+            if not compare_reg(insn, wreg, expected["regs_write"][i], "regs_write"):
+                return False
+
+    return True
+
+
+def test_impl_reg_rw_access(insn: CsInsn, expected: dict):
+    if ("regs_impl_read" not in expected or len(expected["regs_impl_read"]) <= 0) and (
+        "regs_impl_write" not in expected or len(expected["regs_impl_write"]) <= 0
+    ):
+        return True
+
+    regs_impl_read = insn.regs_read
+    regs_impl_write = insn.regs_write
+
+    if "regs_impl_read" in expected and len(expected["regs_impl_read"]) > 0:
+        if not compare_uint32(
+            len(regs_impl_read), len(expected["regs_impl_read"]), "regs_impl_read_count"
+        ):
+            return False
+        for i, rreg in enumerate(regs_impl_read):
+            if not compare_reg(
+                insn, rreg, expected["regs_impl_read"][i], "regs_impl_read"
+            ):
+                return False
+
+    if "regs_impl_write" in expected and len(expected["regs_impl_write"]) > 0:
+        if not compare_uint32(
+            len(regs_impl_write),
+            len(expected["regs_impl_write"]),
+            "regs_impl_write_count",
+        ):
+            return False
+        for i, wreg in enumerate(regs_impl_write):
+            if not compare_reg(
+                insn, wreg, expected["regs_impl_write"][i], "regs_impl_write"
+            ):
+                return False
+
+    return True
+
+
+def compare_details(insn: CsInsn, expected: dict) -> bool:
+    if expected is None:
+        return True
+
+    if not test_reg_rw_access(insn, expected):
+        return False
+
+    if not test_impl_reg_rw_access(insn, expected):
+        return False
+
+    # The current Python bindings don't have such a thing as
+    # an detail attribute for each architecture.
+    # The attributes of each <arch_detail> are directly
+    # an attribute of the instruction.
+    actual = insn
+    if "groups" in expected and len(expected["groups"]) > 0:
+        if not compare_uint32(len(actual.groups), len(expected["groups"]), "group"):
+            return False
+
+        for agroup, egroup in zip(actual.groups, expected["groups"]):
+            if insn.group_name(agroup) == egroup:
+                continue
+            if not compare_enum(agroup, egroup, "group"):
+                return False
+
+    if not compare_tbool(insn.writeback, expected.get("writeback"), "writeback"):
+        return False
+
+    if "aarch64" in expected:
+        return test_expected_aarch64(actual, expected["aarch64"])
+    elif "arm" in expected:
+        return test_expected_arm(actual, expected["arm"])
+    elif "ppc" in expected:
+        return test_expected_ppc(actual, expected["ppc"])
+    elif "tricore" in expected:
+        return test_expected_tricore(actual, expected["tricore"])
+    elif "alpha" in expected:
+        return test_expected_alpha(actual, expected["alpha"])
+    elif "bpf" in expected:
+        return test_expected_bpf(actual, expected["bpf"])
+    elif "hppa" in expected:
+        return test_expected_hppa(actual, expected["hppa"])
+    elif "xcore" in expected:
+        return test_expected_xcore(actual, expected["xcore"])
+    elif "systemz" in expected:
+        return test_expected_sysz(actual, expected["systemz"])
+    elif "sparc" in expected:
+        return test_expected_sparc(actual, expected["sparc"])
+    elif "sh" in expected:
+        return test_expected_sh(actual, expected["sh"])
+    elif "mips" in expected:
+        return test_expected_mips(actual, expected["mips"])
+    elif "riscv" in expected:
+        return test_expected_riscv(actual, expected["riscv"])
+    elif "m680x" in expected:
+        return test_expected_m680x(actual, expected["m680x"])
+    elif "tms320c64x" in expected:
+        return test_expected_tms320c64x(actual, expected["tms320c64x"])
+    elif "mos65xx" in expected:
+        return test_expected_mos65xx(actual, expected["mos65xx"])
+    elif "evm" in expected:
+        return test_expected_evm(actual, expected["evm"])
+    elif "loongarch" in expected:
+        return test_expected_loongarch(actual, expected["loongarch"])
+    elif "wasm" in expected:
+        return test_expected_wasm(actual, expected["wasm"])
+    elif "x86" in expected:
+        return test_expected_x86(actual, expected["x86"])
+    elif "m68k" in expected:
+        return test_expected_m68k(actual, expected["m68k"])
+
+    return True
+
+
+def test_expected_x86(actual: CsInsn, expected: dict) -> bool:
+    if not compare_reg(
+        actual, actual.sib_index, expected.get("sib_index"), "sib_index"
+    ):
+        return False
+    if not compare_reg(actual, actual.sib_base, expected.get("sib_base"), "sib_base"):
+        return False
+    if not compare_enum(actual.xop_cc, expected.get("xop_cc"), "xop_cc"):
+        return False
+    if not compare_enum(actual.sse_cc, expected.get("sse_cc"), "sse_cc"):
+        return False
+    if not compare_enum(actual.avx_cc, expected.get("avx_cc"), "avx_cc"):
+        return False
+    if not compare_enum(actual.avx_rm, expected.get("avx_rm"), "avx_rm"):
+        return False
+
+    if "prefix" in expected:
+        for i, prefix in enumerate(expected.get("prefix")):
+            if not compare_enum(actual.prefix[i], expected.get("prefix")[i], "prefix"):
+                return False
+
+    if "opcode" in expected:
+        for i, opcode in enumerate(expected.get("opcode")):
+            if not compare_uint8(actual.opcode[i], expected.get("opcode")[i], "opcode"):
+                return False
+
+    if not compare_uint8(actual.rex, expected.get("rex"), "rex"):
+        return False
+    if not compare_uint8(actual.addr_size, expected.get("addr_size"), "addr_size"):
+        return False
+    if not compare_uint8(actual.modrm, expected.get("modrm"), "modrm"):
+        return False
+    if not compare_uint8(actual.sib, expected.get("sib"), "sib"):
+        return False
+    if not compare_int64(actual.disp, expected.get("disp"), "disp"):
+        return False
+    if not compare_int8(actual.sib_scale, expected.get("sib_scale"), "sib_scale"):
+        return False
+    if not compare_tbool(actual.avx_sae, expected.get("avx_sae"), "avx_sae"):
+        return False
+
+    if not compare_bit_flags(actual.eflags, expected.get("eflags"), "eflags"):
+        return False
+    if not compare_bit_flags(actual.fpu_flags, expected.get("fpu_flags"), "fpu_flags"):
+        return False
+
+    if not compare_uint8(
+        actual.encoding.modrm_offset,
+        expected.get("enc_modrm_offset"),
+        "enc_modrm_offset",
+    ):
+        return False
+    if not compare_uint8(
+        actual.encoding.disp_offset, expected.get("enc_disp_offset"), "enc_disp_offset"
+    ):
+        return False
+    if not compare_uint8(
+        actual.encoding.disp_size, expected.get("enc_disp_size"), "enc_disp_size"
+    ):
+        return False
+    if not compare_uint8(
+        actual.encoding.imm_offset, expected.get("enc_imm_offset"), "enc_imm_offset"
+    ):
+        return False
+    if not compare_uint8(
+        actual.encoding.imm_size, expected.get("enc_imm_size"), "enc_imm_size"
+    ):
+        return False
+
+    if "operands" not in expected:
+        return True
+    elif not compare_uint32(
+        len(actual.operands), len(expected["operands"]), "operands_count"
+    ):
+        return False
+
+    for aop, eop in zip(actual.operands, expected["operands"]):
+        if not compare_enum(aop.type, eop.get("type"), "type"):
+            return False
+        if not compare_enum(aop.access, eop.get("access"), "access"):
+            return False
+        if not compare_uint8(aop.size, eop.get("size"), "size"):
+            return False
+        if not compare_enum(aop.avx_bcast, eop.get("avx_bcast"), "avx_bcast"):
+            return False
+        if not compare_tbool(
+            aop.avx_zero_opmask, eop.get("avx_zero_opmask"), "avx_zero_opmask"
+        ):
+            return False
+
+        if aop.type == X86_OP_REG:
+            if not compare_reg(actual, aop.reg, eop.get("reg"), "reg"):
+                return False
+        elif aop.type == X86_OP_IMM:
+            if not compare_int64(aop.imm, eop.get("imm"), "imm"):
+                return False
+        elif aop.type == X86_OP_MEM:
+            if not compare_reg(
+                actual, aop.mem.segment, eop.get("mem_segment"), "mem_segment"
+            ):
+                return False
+            if not compare_reg(actual, aop.mem.base, eop.get("mem_base"), "mem_base"):
+                return False
+            if not compare_reg(
+                actual, aop.mem.index, eop.get("mem_index"), "mem_index"
+            ):
+                return False
+            if not compare_int32(aop.mem.scale, eop.get("mem_scale"), "mem_scale"):
+                return False
+            if not compare_int64(aop.mem.disp, eop.get("mem_disp"), "mem_disp"):
+                return False
+        else:
+            raise ValueError("x86 operand type not handled")
+
+    return True
+
+
+def test_expected_ppc(actual: CsInsn, expected: dict) -> bool:
+    if "bc" in expected and not compare_uint8(actual.bc.bo, expected["bc"].get("bo"), "bo"):
+        return False
+
+    if "bc" in expected and not compare_uint8(actual.bc.bi, expected["bc"].get("bi"), "bi"):
+        return False
+
+    if "bc" in expected and not compare_enum(
+        actual.bc.crX_bit, expected.get("bc").get("crX_bit"), "crX_bit"
+    ):
+        return False
+    if "bc" in expected and not compare_reg(
+        actual, actual.bc.crX, expected.get("bc").get("crX"), "crX"
+    ):
+        return False
+    if "bc" in expected and not compare_enum(
+        actual.bc.hint, expected.get("bc").get("hint"), "hint"
+    ):
+        return False
+    if "bc" in expected and not compare_enum(
+        actual.bc.pred_cr, expected.get("bc").get("pred_cr"), "pred_cr"
+    ):
+        return False
+    if "bc" in expected and not compare_enum(
+        actual.bc.pred_ctr, expected.get("bc").get("pred_ctr"), "pred_ctr"
+    ):
+        return False
+    if "bc" in expected and not compare_enum(
+        actual.bc.bh, expected.get("bc").get("bh"), "bh"
+    ):
+        return False
+
+    if not compare_tbool(actual.update_cr0, expected.get("update_cr0"), "update_cr0"):
+        return False
+    if not compare_enum(actual.format, expected.get("format"), "format"):
+        return False
+
+    if "operands" not in expected:
+        return True
+    elif not compare_uint32(
+        len(actual.operands), len(expected["operands"]), "operands_count"
+    ):
+        return False
+
+    for aop, eop in zip(actual.operands, expected["operands"]):
+        if not compare_enum(aop.type, eop.get("type"), "type"):
+            return False
+        if not compare_enum(aop.access, eop.get("access"), "access"):
+            return False
+
+        if aop.type == PPC_OP_REG:
+            if not compare_reg(actual, aop.reg, eop.get("reg"), "reg"):
+                return False
+        elif aop.type == PPC_OP_IMM:
+            if not compare_int64(aop.imm, eop.get("imm"), "imm"):
+                return False
+        elif aop.type == PPC_OP_MEM:
+            if not compare_reg(actual, aop.mem.base, eop.get("mem_base"), "mem_base"):
+                return False
+            if not compare_reg(
+                actual, aop.mem.offset, eop.get("mem_offset"), "mem_offset"
+            ):
+                return False
+            if not compare_int32(aop.mem.disp, eop.get("mem_disp"), "mem_disp"):
+                return False
+    return True
+
+
+def test_expected_arm(actual: CsInsn, expected: dict) -> bool:
+    if not compare_int32(
+        actual.vector_size, expected.get("vector_size"), "vector_size"
+    ):
+        return False
+    if not compare_enum(actual.vector_data, expected.get("vector_data"), "vector_data"):
+        return False
+    if not compare_enum(actual.cps_mode, expected.get("cps_mode"), "cps_mode"):
+        return False
+    if not compare_enum(actual.cps_flag, expected.get("cps_flag"), "cps_flag"):
+        return False
+    if not compare_enum(actual.cc, expected.get("cc"), "cc"):
+        return False
+    if not compare_enum(actual.vcc, expected.get("vcc"), "vcc"):
+        return False
+    if not compare_enum(actual.mem_barrier, expected.get("mem_barrier"), "mem_barrier"):
+        return False
+    if not compare_uint8(actual.pred_mask, expected.get("pred_mask"), "pred_mask"):
+        return False
+
+    if not compare_tbool(actual.usermode, expected.get("usermode"), "usermode"):
+        return False
+    if not compare_tbool(
+        actual.update_flags, expected.get("update_flags"), "update_flags"
+    ):
+        return False
+    if not compare_tbool(
+        actual.post_index, expected.get("post_indexed"), "post_indexed"
+    ):
+        return False
+
+    if "operands" not in expected:
+        return True
+    elif not compare_uint32(
+        len(actual.operands), len(expected.get("operands")), "operands_count"
+    ):
+        return False
+
+    for aop, eop in zip(actual.operands, expected["operands"]):
+        if not compare_enum(aop.type, eop.get("type"), "type"):
+            return False
+        if not compare_enum(aop.access, eop.get("access"), "access"):
+            return False
+
+        if aop.type == ARM_OP_REG:
+            if not compare_reg(actual, aop.reg, eop.get("reg"), "reg"):
+                return False
+        elif (
+            aop.type == ARM_OP_IMM or aop.type == ARM_OP_PIMM or aop.type == ARM_OP_CIMM
+        ):
+            if not compare_int64(aop.imm, eop.get("imm"), "imm"):
+                return False
+        elif aop.type == ARM_OP_SETEND:
+            if not compare_enum(aop.setend, eop.get("setend"), "setend"):
+                return False
+        elif aop.type == ARM_OP_PRED:
+            if not compare_int32(aop.pred, eop.get("pred"), "pred"):
+                return False
+        elif aop.type == ARM_OP_FP:
+            if not compare_fp(aop.fp, eop.get("fp"), "fp"):
+                return False
+        elif aop.type == ARM_OP_MEM:
+            if not compare_reg(actual, aop.mem.base, eop.get("mem_base"), "mem_base"):
+                return False
+            if not compare_reg(
+                actual, aop.mem.index, eop.get("mem_index"), "mem_index"
+            ):
+                return False
+            if not compare_int32(aop.mem.scale, eop.get("mem_scale"), "mem_scale"):
+                return False
+            if not compare_int32(aop.mem.disp, eop.get("mem_disp"), "mem_disp"):
+                return False
+            if not compare_uint32(aop.mem.align, eop.get("mem_align"), "mem_align"):
+                return False
+        elif aop.type == ARM_OP_SYSREG:
+            if not compare_enum(
+                aop.sysop.reg.mclasssysreg, eop.get("sys_reg"), "sys_reg"
+            ):
+                return False
+            if not compare_int32(aop.sysop.sysm, eop.get("sys_sysm"), "sys_sysm"):
+                return False
+            if not compare_int32(
+                aop.sysop.msr_mask, eop.get("sys_msr_mask"), "sys_msr_mask"
+            ):
+                return False
+        elif aop.type == ARM_OP_BANKEDREG:
+            if not compare_enum(aop.sysop.reg.bankedreg, eop.get("sys_reg"), "sys_reg"):
+                return False
+            if not compare_int32(aop.sysop.sysm, eop.get("sys_sysm"), "sys_sysm"):
+                return False
+            if not compare_int32(
+                aop.sysop.msr_mask, eop.get("sys_msr_mask"), "sys_msr_mask"
+            ):
+                return False
+        elif aop.type == ARM_OP_SPSR or aop.type == ARM_OP_CPSR:
+            if not compare_bit_flags(
+                aop.sysop.psr_bits, eop.get("sys_psr_bits"), "sys_psr_bits"
+            ):
+                return False
+            if not compare_int32(aop.sysop.sysm, eop.get("sys_sysm"), "sys_sysm"):
+                return False
+            if not compare_int32(
+                aop.sysop.msr_mask, eop.get("sys_msr_mask"), "sys_msr_mask"
+            ):
+                return False
+        elif aop.type == ARM_OP_SYSM:
+            if not compare_int32(aop.sysop.sysm, eop.get("sys_sysm"), "sys_sysm"):
+                return False
+            if not compare_int32(
+                aop.sysop.msr_mask, eop.get("sys_msr_mask"), "sys_msr_mask"
+            ):
+                return False
+        else:
+            raise ValueError("ARM operand type not handled")
+
+        if not compare_enum(aop.shift.type, eop.get("shift_type"), "shift_type"):
+            return False
+        if not compare_uint32(aop.shift.value, eop.get("shift_value"), "shift_value"):
+            return False
+
+        if not compare_int8(aop.neon_lane, eop.get("neon_lane"), "neon_lane"):
+            return False
+
+        if not compare_int32(
+            aop.vector_index, eop.get("vector_index"), "vector_index"
+        ):
+            return False
+
+        if not compare_tbool(aop.subtracted, eop.get("subtracted"), "subtracted"):
+            return False
+    return True
+
+
+def test_expected_m680x(actual: CsInsn, expected: dict) -> bool:
+    if not compare_bit_flags(actual.flags, expected.get("flags"), "flags"):
+        return False
+
+    if "operands" not in expected:
+        return True
+    elif not compare_uint32(
+        len(actual.operands), len(expected.get("operands")), "operands_count"
+    ):
+        return False
+
+    for aop, eop in zip(actual.operands, expected["operands"]):
+        if not compare_enum(aop.type, eop.get("type"), "type"):
+            return False
+        if not compare_enum(aop.access, eop.get("access"), "access"):
+            return False
+        if not compare_uint8(aop.size, eop.get("size"), "size"):
+            return False
+
+        if aop.type == M680X_OP_INDEXED:
+            if "idx" not in eop:
+                continue
+            if not compare_reg(
+                actual, aop.idx.base_reg, eop["idx"].get("base_reg"), "base_reg"
+            ):
+                return False
+            if not compare_reg(
+                actual, aop.idx.offset_reg, eop["idx"].get("offset_reg"), "offset_reg"
+            ):
+                return False
+            if not compare_int16(aop.idx.offset, eop["idx"].get("offset"), "offset"):
+                return False
+            if not compare_uint16(
+                aop.idx.offset_addr, eop["idx"].get("offset_addr"), "offset_addr"
+            ):
+                return False
+            if not compare_uint8(
+                aop.idx.offset_bits, eop["idx"].get("offset_bits"), "offset_bits"
+            ):
+                return False
+            if not compare_int8(aop.idx.inc_dec, eop["idx"].get("inc_dec"), "inc_dec"):
+                return False
+            if not compare_bit_flags(aop.idx.flags, eop["idx"].get("flags"), "flags"):
+                return False
+
+        elif aop.type == M680X_OP_REGISTER:
+            if not compare_reg(actual, aop.reg, eop.get("reg"), "reg"):
+                return False
+        elif aop.type == M680X_OP_IMMEDIATE:
+            if not compare_int32(aop.imm, eop.get("imm"), "imm"):
+                return False
+        elif aop.type == M680X_OP_RELATIVE:
+            if not compare_uint16(
+                aop.rel.address, eop.get("rel_address"), "rel_address"
+            ):
+                return False
+            if not compare_int16(aop.rel.offset, eop.get("rel_offset"), "rel_offset"):
+                return False
+        elif aop.type == M680X_OP_EXTENDED:
+            if not compare_uint16(
+                aop.ext.address, eop.get("ext_address"), "ext_address"
+            ):
+                return False
+            if not compare_tbool(
+                aop.ext.indirect, eop.get("ext_indirect"), "ext_indirect"
+            ):
+                return False
+        elif aop.type == M680X_OP_DIRECT:
+            if not compare_uint8(
+                aop.direct_addr, eop.get("direct_addr"), "direct_addr"
+            ):
+                return False
+        elif aop.type == M680X_OP_CONSTANT:
+            if not compare_uint8(aop.const_val, eop.get("const_val"), "const_val"):
+                return False
+
+    return True
+
+
+def test_expected_aarch64(actual: CsInsn, expected: dict) -> bool:
+    if not compare_enum(actual.cc, expected.get("cc"), "cc"):
+        return False
+    if not compare_tbool(
+        actual.update_flags, expected.get("update_flags"), "update_flags"
+    ):
+        return False
+    if not compare_tbool(
+        actual.post_index, expected.get("post_indexed"), "post_indexed"
+    ):
+        return False
+
+    if "operands" not in expected:
+        return True
+    elif not compare_uint32(
+        len(actual.operands), len(expected.get("operands")), "operands_count"
+    ):
+        return False
+
+    for aop, eop in zip(actual.operands, expected["operands"]):
+        if not compare_enum(aop.access, eop.get("access"), "access"):
+            return False
+
+        if not compare_enum(aop.shift.type, eop.get("shift_type"), "shift_type"):
+            return False
+        if not compare_uint32(aop.shift.value, eop.get("shift_value"), "shift_value"):
+            return False
+        if not compare_enum(aop.ext, eop.get("ext"), "ext"):
+            return False
+
+        if not compare_enum(aop.vas, eop.get("vas"), "vas"):
+            return False
+        if not compare_tbool(aop.is_vreg, eop.get("is_vreg"), "is_vreg"):
+            return False
+
+        if not compare_int32(
+            aop.vector_index, eop.get("vector_index"), "vector_index"
+        ):
+            return False
+
+        if not compare_tbool(
+            aop.is_list_member, eop.get("is_list_member"), "is_list_member"
+        ):
+            return False
+
+        if not compare_enum(aop.type, eop["type"], "op type"):
+            return False
+        # Operand
+        if aop.type == AARCH64_OP_REG:
+            if not compare_reg(actual, aop.value.reg, eop.get("reg"), "reg"):
+                return False
+        elif aop.type == AARCH64_OP_IMM:
+            if not compare_int64(aop.value.imm, eop.get("imm"), "imm"):
+                return False
+        elif aop.type == AARCH64_OP_MEM:
+            if not compare_reg(
+                actual, aop.value.mem.base, eop.get("mem_base"), "mem_base"
+            ):
+                return False
+            if not compare_reg(
+                actual, aop.value.mem.index, eop.get("mem_index"), "mem_index"
+            ):
+                return False
+            if not compare_int32(aop.value.mem.disp, eop.get("mem_disp"), "mem_disp"):
+                return False
+        elif aop.type == AARCH64_OP_IMM_RANGE:
+            if not compare_int8(
+                aop.value.imm_range.first, eop.get("imm_range_first"), "imm_range_first"
+            ):
+                return False
+            if not compare_int8(
+                aop.value.imm_range.offset,
+                eop.get("imm_range_offset"),
+                "imm_range_offset",
+            ):
+                return False
+        elif aop.type == AARCH64_OP_FP:
+            if not compare_fp(aop.value.fp, eop.get("fp"), "fp"):
+                return False
+        elif aop.type == AARCH64_OP_SYSREG:
+            if not compare_enum(
+                aop.value.sysop.sub_type, eop.get("sub_type"), "sub_type"
+            ):
+                return False
+            if not compare_uint64(
+                aop.value.sysop.reg.raw_val, eop.get("sys_raw_val"), "sys_raw_val"
+            ):
+                return False
+        elif aop.type == AARCH64_OP_SYSIMM:
+            if not compare_enum(
+                aop.value.sysop.sub_type, eop.get("sub_type"), "sub_type"
+            ):
+                return False
+            if not compare_uint64(
+                aop.value.sysop.imm.raw_val, eop.get("sys_raw_val"), "sys_raw_val"
+            ):
+                return False
+        elif aop.type == AARCH64_OP_SYSALIAS:
+            if not compare_enum(
+                aop.value.sysop.sub_type, eop.get("sub_type"), "sub_type"
+            ):
+                return False
+            if not compare_uint64(
+                aop.value.sysop.alias.raw_val, eop.get("sys_raw_val"), "sys_raw_val"
+            ):
+                return False
+        elif aop.type == AARCH64_OP_PRED:
+            if not compare_reg(
+                actual, aop.value.pred.reg, eop.get("pred_reg"), "pred_reg"
+            ):
+                return False
+            if not compare_reg(
+                actual,
+                aop.value.pred.vec_select,
+                eop.get("pred_vec_select"),
+                "pred_vec_select",
+            ):
+                return False
+            if not compare_int32(
+                aop.value.pred.imm_index,
+                eop.get("pred_imm_index"),
+                "pred_imm_index",
+            ):
+                return False
+        elif aop.type == AARCH64_OP_SME:
+            if "sme" not in eop:
+                continue
+
+            if not compare_enum(aop.value.sme.type, eop["sme"].get("type"), "type"):
+                return False
+            if not compare_reg(
+                actual, aop.value.sme.tile, eop["sme"].get("tile"), "tile"
+            ):
+                return False
+            if not compare_reg(
+                actual,
+                aop.value.sme.slice_reg,
+                eop["sme"].get("slice_reg"),
+                "slice_reg",
+            ):
+                return False
+            if not compare_int8(
+                aop.value.sme.slice_offset.imm,
+                eop["sme"].get("slice_offset_imm"),
+                "slice_offset_imm",
+            ):
+                return False
+            if not compare_int8(
+                aop.value.sme.slice_offset.imm_range.first,
+                eop["sme"].get("slice_offset_ir_first"),
+                "slice_offset_ir_first",
+            ):
+                return False
+            if not compare_int8(
+                aop.value.sme.slice_offset.imm_range.offset,
+                eop["sme"].get("slice_offset_ir_offset"),
+                "slice_offset_ir_offset",
+            ):
+                return False
+            if not compare_tbool(
+                aop.value.sme.has_range_offset,
+                eop["sme"].get("has_range_offset"),
+                "has_range_offset",
+            ):
+                return False
+            if not compare_tbool(
+                aop.value.sme.is_vertical, eop["sme"].get("is_vertical"), "is_vertical"
+            ):
+                return False
+        else:
+            raise ValueError(f"Operand type not handled: {aop.type}")
+    return True
+
+
+def test_expected_sparc(actual: CsInsn, expected: dict) -> bool:
+    if not compare_enum(actual.cc, expected.get("cc"), "cc"):
+        return False
+    if not compare_enum(actual.hint, expected.get("hint"), "hint"):
+        return False
+
+    if "operands" not in expected:
+        return True
+    elif not compare_uint32(
+        len(actual.operands), len(expected.get("operands")), "operands_count"
+    ):
+        return False
+
+    for aop, eop in zip(actual.operands, expected["operands"]):
+        if not compare_enum(aop.type, eop.get("type"), "type"):
+            return False
+
+        if aop.type == SPARC_OP_REG:
+            if not compare_reg(actual, aop.reg, eop.get("reg"), "reg"):
+                return False
+        elif aop.type == SPARC_OP_IMM:
+            if not compare_int64(aop.imm, eop.get("imm"), "imm"):
+                return False
+        elif aop.type == SPARC_OP_MEM:
+            if not compare_reg(actual, aop.mem.base, eop.get("mem_base"), "mem_base"):
+                return False
+            if not compare_reg(
+                actual, aop.mem.index, eop.get("mem_index"), "mem_index"
+            ):
+                return False
+            if not compare_int32(aop.mem.disp, eop.get("mem_disp"), "mem_disp"):
+                return False
+        else:
+            raise ValueError("Operand type not handled.")
+    return True
+
+
+def test_expected_tricore(actual: CsInsn, expected: dict) -> bool:
+    if not compare_tbool(
+        actual.update_flags, expected.get("update_flags"), "update_flags"
+    ):
+        return False
+
+    if "operands" not in expected:
+        return True
+    elif not compare_uint32(
+        len(actual.operands), len(expected.get("operands")), "operands_count"
+    ):
+        return False
+
+    for aop, eop in zip(actual.operands, expected["operands"]):
+        if not compare_enum(aop.type, eop.get("type"), "type"):
+            return False
+        if not compare_enum(aop.access, eop.get("access"), "access"):
+            return False
+
+        if aop.type == TRICORE_OP_REG:
+            if not compare_reg(actual, aop.reg, eop.get("reg"), "reg"):
+                return False
+        elif aop.type == TRICORE_OP_IMM:
+            if not compare_int64(aop.imm, eop.get("imm"), "imm"):
+                return False
+        elif aop.type == TRICORE_OP_MEM:
+            if not compare_reg(actual, aop.mem.base, eop.get("mem_base"), "mem_base"):
+                return False
+            if not compare_int64(aop.mem.disp, eop.get("mem_disp"), "mem_disp"):
+                return False
+        else:
+            raise ValueError("Operand type not handled.")
+    return True
+
+
+def test_expected_evm(actual: CsInsn, expected: dict) -> bool:
+    if not compare_uint8(actual.pop, expected.get("pop"), "pop"):
+        return False
+    if not compare_uint8(actual.push, expected.get("push"), "push"):
+        return False
+    if not compare_int32(actual.fee, expected.get("fee"), "fee"):
+        return False
+    return True
+
+
+def test_expected_alpha(actual: CsInsn, expected: dict) -> bool:
+    if "operands" not in expected:
+        return True
+    elif not compare_uint32(
+        len(actual.operands), len(expected.get("operands")), "operands_count"
+    ):
+        return False
+
+    for aop, eop in zip(actual.operands, expected["operands"]):
+        if not compare_enum(aop.type, eop.get("type"), "type"):
+            return False
+        if not compare_enum(aop.access, eop.get("access"), "access"):
+            return False
+
+        if aop.type == ALPHA_OP_REG:
+            if not compare_reg(actual, aop.reg, eop.get("reg"), "reg"):
+                return False
+        elif aop.type == ALPHA_OP_IMM:
+            if not compare_int32(aop.imm, eop.get("imm"), "imm"):
+                return False
+        else:
+            raise ValueError("Operand type not handled.")
+    return True
+
+
+def test_expected_xcore(actual: CsInsn, expected: dict) -> bool:
+    if "operands" not in expected:
+        return True
+    elif not compare_uint32(
+        len(actual.operands), len(expected.get("operands")), "operands_count"
+    ):
+        return False
+
+    for aop, eop in zip(actual.operands, expected["operands"]):
+        if not compare_enum(aop.type, eop.get("type"), "type"):
+            return False
+
+        if aop.type == XCORE_OP_REG:
+            if not compare_reg(actual, aop.reg, eop.get("reg"), "reg"):
+                return False
+        elif aop.type == XCORE_OP_IMM:
+            if not compare_int32(aop.imm, eop.get("imm"), "imm"):
+                return False
+        elif aop.type == XCORE_OP_MEM:
+            if not compare_reg(actual, aop.mem.base, eop.get("mem_base"), "mem_base"):
+                return False
+            if not compare_reg(
+                actual, aop.mem.index, eop.get("mem_index"), "mem_index"
+            ):
+                return False
+            if not compare_int32(aop.mem.disp, eop.get("mem_disp"), "mem_disp"):
+                return False
+            if not compare_int32(aop.mem.direct, eop.get("mem_direct"), "mem_direct"):
+                return False
+        else:
+            raise ValueError("Operand type not handled.")
+    return True
+
+
+def test_expected_tms320c64x(actual: CsInsn, expected: dict) -> bool:
+    if not compare_reg(
+        actual, actual.condition.reg, expected.get("cond_reg"), "cond_reg"
+    ):
+        return False
+    if not compare_tbool(actual.condition.zero, expected.get("cond_zero"), "cond_zero"):
+        return False
+
+    if not compare_enum(actual.funit.unit, expected.get("funit_unit"), "funit_unit"):
+        return False
+    if not compare_uint8(actual.funit.side, expected.get("funit_side"), "funit_side"):
+        return False
+    if not compare_uint8(
+        actual.funit.crosspath, expected.get("funit_crosspath"), "funit_crosspath"
+    ):
+        return False
+
+    if not compare_int8(actual.parallel, expected.get("parallel"), "parallel"):
+        return False
+
+    if "operands" not in expected:
+        return True
+    elif not compare_uint32(
+        len(actual.operands), len(expected.get("operands")), "operands_count"
+    ):
+        return False
+
+    for aop, eop in zip(actual.operands, expected["operands"]):
+        if not compare_enum(aop.type, eop.get("type"), "type"):
+            return False
+
+        if aop.type == TMS320C64X_OP_REG:
+            if not compare_reg(actual, aop.reg, eop.get("reg"), "reg"):
+                return False
+        elif aop.type == TMS320C64X_OP_REGPAIR:
+            if not compare_reg(
+                actual, aop.reg + 1, eop.get("reg_pair_0"), "reg_pair_0"
+            ):
+                return False
+            if not compare_reg(actual, aop.reg, eop.get("reg_pair_1"), "reg_pair_1"):
+                return False
+        elif aop.type == TMS320C64X_OP_IMM:
+            if not compare_int32(aop.imm, eop.get("imm"), "imm"):
+                return False
+        elif aop.type == TMS320C64X_OP_MEM:
+            if not compare_reg(actual, aop.mem.base, eop.get("mem_base"), "mem_base"):
+                return False
+            if not compare_tbool(aop.mem.scaled, eop.get("mem_scaled"), "mem_scaled"):
+                return False
+            if not compare_enum(
+                aop.mem.disptype, eop.get("mem_disptype"), "mem_disptype"
+            ):
+                return False
+            if not compare_enum(
+                aop.mem.direction, eop.get("mem_direction"), "mem_direction"
+            ):
+                return False
+            if not compare_enum(aop.mem.modify, eop.get("mem_modify"), "mem_modify"):
+                return False
+            if aop.mem.disptype == TMS320C64X_MEM_DISP_REGISTER:
+                if not compare_reg(
+                    actual, aop.mem.disp, eop.get("mem_disp_reg"), "mem_disp_reg"
+                ):
+                    return False
+            elif aop.mem.disptype == TMS320C64X_MEM_DISP_CONSTANT:
+                if not compare_uint32(
+                    aop.mem.disp, eop.get("mem_disp_const"), "mem_disp_const"
+                ):
+                    return False
+            else:
+                raise ValueError("TMS320c64x memory offset type not handled.")
+
+            if not compare_uint32(aop.mem.unit, eop.get("mem_unit"), "mem_unit"):
+                return False
+        else:
+            raise ValueError("Operand type not handled.")
+
+    return True
+
+
+def test_expected_m68k(actual: CsInsn, expected: dict) -> bool:
+    if not compare_enum(
+        actual.op_size.type, expected.get("op_size_type"), "op_size_type"
+    ):
+        return False
+    if not compare_enum(
+        actual.op_size.size, expected.get("op_size_fpu"), "op_size_fpu"
+    ):
+        return False
+    if not compare_enum(
+        actual.op_size.size, expected.get("op_size_cpu"), "op_size_cpu"
+    ):
+        return False
+
+    if "operands" not in expected:
+        return True
+    elif not compare_uint32(
+        len(actual.operands), len(expected.get("operands")), "operands_count"
+    ):
+        return False
+
+    for aop, eop in zip(actual.operands, expected["operands"]):
+        if not compare_enum(aop.type, eop.get("type"), "type"):
+            return False
+        if not compare_enum(aop.address_mode, eop.get("address_mode"), "address_mode"):
+            return False
+
+        if aop.type == M68K_OP_REG:
+            if not compare_reg(actual, aop.reg, eop.get("reg"), "reg"):
+                return False
+        elif aop.type == M68K_OP_REG_PAIR:
+            if not compare_reg(
+                actual, aop.reg_pair.reg_0, eop.get("reg_pair_0"), "reg_pair_0"
+            ):
+                return False
+            if not compare_reg(
+                actual, aop.reg_pair.reg_1, eop.get("reg_pair_1"), "reg_pair_1"
+            ):
+                return False
+        elif aop.type == M68K_OP_IMM:
+            if not compare_uint64(aop.imm, eop.get("imm"), "imm"):
+                return False
+        elif aop.type == M68K_OP_BR_DISP:
+            if not compare_int32(aop.br_disp.disp, eop.get("br_disp"), "br_disp"):
+                return False
+            if not compare_uint8(
+                aop.br_disp.disp_size, eop.get("br_disp_size"), "br_disp_size"
+            ):
+                return False
+        elif aop.type == M68K_OP_REG_BITS:
+            if not compare_uint32(
+                aop.register_bits, eop.get("register_bits"), "register_bits"
+            ):
+                return False
+        elif aop.type == M68K_OP_FP_DOUBLE:
+            if not compare_dp(aop.dimm, eop.get("dimm"), "dimm"):
+                return False
+        elif aop.type == M68K_OP_FP_SINGLE:
+            if not compare_fp(aop.simm, eop.get("simm"), "simm"):
+                return False
+        elif aop.type == M68K_OP_MEM:
+            if "mem" not in eop:
+                continue
+
+            if not compare_reg(
+                actual, aop.mem.base_reg, eop["mem"].get("base_reg"), "base_reg"
+            ):
+                return False
+            if not compare_reg(
+                actual, aop.mem.index_reg, eop["mem"].get("index_reg"), "index_reg"
+            ):
+                return False
+            if not compare_reg(
+                actual,
+                aop.mem.in_base_reg,
+                eop["mem"].get("in_base_reg"),
+                "in_base_reg",
+            ):
+                return False
+            if not compare_tbool(
+                aop.mem.index_size, eop["mem"].get("index_size"), "index_size"
+            ):
+                return False
+            if not compare_int16(aop.mem.disp, eop["mem"].get("disp"), "disp"):
+                return False
+            if not compare_uint32(
+                aop.mem.in_disp, eop["mem"].get("in_disp"), "in_disp"
+            ):
+                return False
+            if not compare_uint32(
+                aop.mem.out_disp, eop["mem"].get("out_disp"), "out_disp"
+            ):
+                return False
+            if not compare_uint8(aop.mem.scale, eop["mem"].get("scale"), "scale"):
+                return False
+            if not compare_uint8(
+                aop.mem.bitfield, eop["mem"].get("bitfield"), "bitfield"
+            ):
+                return False
+            if not compare_uint8(aop.mem.width, eop["mem"].get("width"), "width"):
+                return False
+            if not compare_uint8(aop.mem.offset, eop["mem"].get("offset"), "offset"):
+                return False
+        else:
+            raise ValueError("Operand type not handled.")
+    return True
+
+
+def test_expected_bpf(actual: CsInsn, expected: dict) -> bool:
+    if "operands" not in expected:
+        return True
+    elif not compare_uint32(
+        len(actual.operands), len(expected.get("operands")), "operands_count"
+    ):
+        return False
+
+    for aop, eop in zip(actual.operands, expected["operands"]):
+        if not compare_enum(aop.type, eop.get("type"), "type"):
+            return False
+        if not compare_enum(aop.access, eop.get("access"), "access"):
+            return False
+
+        if aop.type == BPF_OP_REG:
+            if not compare_reg(actual, aop.reg, eop.get("reg"), "reg"):
+                return False
+        elif aop.type == BPF_OP_IMM:
+            if not compare_uint64(aop.imm, eop.get("imm"), "imm"):
+                return False
+        elif aop.type == BPF_OP_OFF:
+            if not compare_uint32(aop.off, eop.get("off"), "off"):
+                return False
+        elif aop.type == BPF_OP_MMEM:
+            if not compare_uint32(aop.mmem, eop.get("mmem"), "mmem"):
+                return False
+        elif aop.type == BPF_OP_MSH:
+            if not compare_uint32(aop.msh, eop.get("msh"), "msh"):
+                return False
+        elif aop.type == BPF_OP_EXT:
+            if not compare_enum(aop.ext, eop.get("ext"), "ext"):
+                return False
+        elif aop.type == BPF_OP_MEM:
+            if not compare_reg(actual, aop.mem.base, eop.get("mem_base"), "mem_base"):
+                return False
+            if not compare_uint32(aop.mem.disp, eop.get("mem_disp"), "mem_disp"):
+                return False
+        else:
+            raise ValueError("Operand type not handled.")
+    return True
+
+
+def test_expected_sh(actual: CsInsn, expected: dict) -> bool:
+    if "operands" not in expected:
+        return True
+    elif not compare_uint32(
+        len(actual.operands), len(expected.get("operands")), "operands_count"
+    ):
+        return False
+
+    for aop, eop in zip(actual.operands, expected["operands"]):
+        if not compare_enum(aop.type, eop.get("type"), "type"):
+            return False
+
+        if aop.type == SH_OP_REG:
+            if not compare_reg(actual, aop.reg, eop.get("reg"), "reg"):
+                return False
+        elif aop.type == SH_OP_IMM:
+            if not compare_uint64(aop.imm, eop.get("imm"), "imm"):
+                return False
+        elif aop.type == SH_OP_MEM:
+            if not compare_reg(actual, aop.mem.reg, eop.get("mem_reg"), "mem_reg"):
+                return False
+            if not compare_reg(
+                actual, aop.mem.address, eop.get("mem_address"), "mem_address"
+            ):
+                return False
+            if not compare_int32(aop.mem.disp, eop.get("mem_disp"), "mem_disp"):
+                return False
+        else:
+            raise ValueError("Operand type not handled.")
+    return True
+
+
+def test_expected_hppa(actual: CsInsn, expected: dict) -> bool:
+    if "operands" not in expected:
+        return True
+    elif not compare_uint32(
+        len(actual.operands), len(expected.get("operands")), "operands_count"
+    ):
+        return False
+
+    for aop, eop in zip(actual.operands, expected["operands"]):
+        if not compare_enum(aop.type, eop.get("type"), "type"):
+            return False
+        if not compare_enum(aop.access, eop.get("access"), "access"):
+            return False
+
+        if aop.type == HPPA_OP_REG or aop.type == HPPA_OP_IDX_REG:
+            if not compare_reg(actual, aop.reg, eop.get("reg"), "reg"):
+                return False
+        elif (
+            aop.type == HPPA_OP_IMM
+            or aop.type == HPPA_OP_DISP
+            or aop.type == HPPA_OP_TARGET
+        ):
+            if not compare_int64(aop.imm, eop.get("imm"), "imm"):
+                return False
+        elif aop.type == HPPA_OP_MEM:
+            if not compare_reg(actual, aop.mem.base, eop.get("mem_base"), "mem_base"):
+                return False
+            if not compare_reg(
+                actual, aop.mem.space, eop.get("mem_space"), "mem_space"
+            ):
+                return False
+            if not compare_reg(
+                actual,
+                aop.mem.base_access,
+                eop.get("mem_base_access"),
+                "mem_base_access",
+            ):
+                return False
+        else:
+            raise ValueError("Operand type not handled.")
+    return True
+
+
+def test_expected_riscv(actual: CsInsn, expected: dict) -> bool:
+    if "operands" not in expected:
+        return True
+    elif not compare_uint32(
+        len(actual.operands), len(expected.get("operands")), "operands_count"
+    ):
+        return False
+
+    for aop, eop in zip(actual.operands, expected["operands"]):
+        if not compare_enum(aop.type, eop.get("type"), "type"):
+            return False
+        if not compare_enum(aop.access, eop.get("access"), "access"):
+            return False
+
+        if aop.type == RISCV_OP_REG:
+            if not compare_reg(actual, aop.reg, eop.get("reg"), "reg"):
+                return False
+        elif aop.type == RISCV_OP_IMM:
+            if not compare_uint64(aop.imm, eop.get("imm"), "imm"):
+                return False
+        elif aop.type == RISCV_OP_MEM:
+            if not compare_reg(actual, aop.mem.base, eop.get("mem_base"), "mem_base"):
+                return False
+            if not compare_int64(aop.mem.disp, eop.get("mem_disp"), "mem_disp"):
+                return False
+        else:
+            raise ValueError("Operand type not handled.")
+    return True
+
+
+def test_expected_mips(actual: CsInsn, expected: dict) -> bool:
+    if "operands" not in expected:
+        return True
+    elif not compare_uint32(
+        len(actual.operands), len(expected.get("operands")), "operands_count"
+    ):
+        return False
+
+    for aop, eop in zip(actual.operands, expected["operands"]):
+        if not compare_enum(aop.type, eop.get("type"), "type"):
+            return False
+
+        if aop.type == MIPS_OP_REG:
+            if not compare_reg(actual, aop.reg, eop.get("reg"), "reg"):
+                return False
+        elif aop.type == MIPS_OP_IMM:
+            if not compare_uint64(aop.imm, eop.get("imm"), "imm"):
+                return False
+        elif aop.type == MIPS_OP_MEM:
+            if not compare_reg(actual, aop.mem.base, eop.get("mem_base"), "mem_base"):
+                return False
+            if not compare_int64(aop.mem.disp, eop.get("mem_disp"), "mem_disp"):
+                return False
+        else:
+            raise ValueError("Operand type not handled.")
+    return True
+
+
+def test_expected_sysz(actual: CsInsn, expected: dict) -> bool:
+    if "operands" not in expected:
+        return True
+    elif not compare_uint32(
+        len(actual.operands), len(expected.get("operands")), "operands_count"
+    ):
+        return False
+
+    for aop, eop in zip(actual.operands, expected["operands"]):
+        if not compare_enum(aop.type, eop.get("type"), "type"):
+            return False
+
+        if aop.type == SYSZ_OP_REG:
+            if not compare_reg(actual, aop.reg, eop.get("reg"), "reg"):
+                return False
+        elif aop.type == SYSZ_OP_IMM:
+            if not compare_int64(aop.imm, eop.get("imm"), "imm"):
+                return False
+        elif aop.type == SYSZ_OP_MEM:
+            if not compare_reg(actual, aop.mem.base, eop.get("mem_base"), "mem_base"):
+                return False
+            if not compare_reg(
+                actual, aop.mem.index, eop.get("mem_index"), "mem_index"
+            ):
+                return False
+            if not compare_int64(aop.mem.disp, eop.get("mem_disp"), "mem_disp"):
+                return False
+            if not compare_uint64(aop.mem.length, eop.get("mem_length"), "mem_length"):
+                return False
+        else:
+            raise ValueError("Operand type not handled.")
+    return True
+
+
+def test_expected_mos65xx(actual: CsInsn, expected: dict) -> bool:
+    if not compare_enum(actual.am, expected.get("am"), "am"):
+        return False
+    if not compare_tbool(
+        actual.modifies_flags, expected.get("modifies_flags"), "modifies_flags"
+    ):
+        return False
+
+    if "operands" not in expected:
+        return True
+    elif not compare_uint32(
+        len(actual.operands), len(expected.get("operands")), "operands_count"
+    ):
+        return False
+
+    for aop, eop in zip(actual.operands, expected["operands"]):
+        if not compare_enum(aop.type, eop.get("type"), "type"):
+            return False
+
+        if aop.type == MOS65XX_OP_REG:
+            if not compare_reg(actual, aop.reg, eop.get("reg"), "reg"):
+                return False
+        elif aop.type == MOS65XX_OP_IMM:
+            if not compare_uint16(aop.imm, eop.get("imm"), "imm"):
+                return False
+        elif aop.type == MOS65XX_OP_MEM:
+            if not compare_uint32(aop.mem, eop.get("mem"), "mem"):
+                return False
+        else:
+            raise ValueError("Operand type not handled.")
+    return True
+
+
+def test_expected_loongarch(actual: CsInsn, expected: dict) -> bool:
+    if not compare_enum(actual.format, expected.get("format"), "format"):
+        return False
+
+    if "operands" not in expected:
+        return True
+    elif not compare_uint32(
+        len(actual.operands), len(expected.get("operands")), "operands_count"
+    ):
+        return False
+
+    for aop, eop in zip(actual.operands, expected["operands"]):
+        if not compare_enum(aop.type, eop.get("type"), "type"):
+            return False
+        if not compare_enum(aop.access, eop.get("access"), "access"):
+            return False
+
+        if aop.type == LOONGARCH_OP_REG:
+            if not compare_reg(actual, aop.reg, eop.get("reg"), "reg"):
+                return False
+        elif aop.type == LOONGARCH_OP_IMM:
+            if not compare_uint64(aop.imm, eop.get("imm"), "imm"):
+                return False
+        elif aop.type == LOONGARCH_OP_MEM:
+            if not compare_reg(actual, aop.mem.base, eop.get("mem_base"), "mem_base"):
+                return False
+            if not compare_reg(
+                actual, aop.mem.index, eop.get("mem_index"), "mem_index"
+            ):
+                return False
+            if not compare_int64(aop.mem.disp, eop.get("mem_disp"), "mem_disp"):
+                return False
+        else:
+            raise ValueError("Operand type not handled.")
+    return True
+
+
+def test_expected_wasm(actual: CsInsn, expected: dict) -> bool:
+    if "operands" not in expected:
+        return True
+    elif not compare_uint32(
+        len(actual.operands), len(expected.get("operands")), "operands_count"
+    ):
+        return False
+
+    for aop, eop in zip(actual.operands, expected["operands"]):
+        if not compare_enum(aop.type, eop.get("type"), "type"):
+            return False
+
+        if not compare_uint32(aop.size, eop.get("size"), "size"):
+            return False
+        if aop.type == WASM_OP_INT7:
+            if not compare_int8(aop.int7, eop.get("int7"), "int7"):
+                return False
+        elif aop.type == WASM_OP_VARUINT32:
+            if not compare_uint32(aop.varuint32, eop.get("varuint32"), "varuint32"):
+                return False
+        elif aop.type == WASM_OP_VARUINT64:
+            if not compare_uint64(aop.varuint64, eop.get("varuint64"), "varuint64"):
+                return False
+        elif aop.type == WASM_OP_UINT32:
+            if not compare_uint32(aop.uint32, eop.get("uint32"), "uint32"):
+                return False
+        elif aop.type == WASM_OP_UINT64:
+            if not compare_uint64(aop.uint64, eop.get("uint64"), "uint64"):
+                return False
+        elif aop.type == WASM_OP_IMM:
+            if not compare_uint32(
+                aop.immediate[0], eop.get("immediate_0"), "immediate_0"
+            ):
+                return False
+            if not compare_uint32(
+                aop.immediate[1], eop.get("immediate_1"), "immediate_1"
+            ):
+                return False
+        elif aop.type == WASM_OP_BRTABLE:
+            if not compare_uint32(
+                aop.brtable.length, eop.get("brt_length"), "brt_length"
+            ):
+                return False
+            if not compare_uint64(
+                aop.brtable.address, eop.get("brt_address"), "brt_address"
+            ):
+                return False
+            if not compare_uint32(
+                aop.brtable.default_target,
+                eop.get("brt_default_target"),
+                "brt_default_target",
+            ):
+                return False
+        else:
+            raise ValueError("Operand type not handled.")
+    return True
diff --git a/bindings/python/setup.py b/bindings/python/setup.py
index f72ea393c..e96a4589e 100755
--- a/bindings/python/setup.py
+++ b/bindings/python/setup.py
@@ -72,10 +72,12 @@ else:
     LIBRARY_FILE = "libcapstone.so"
     STATIC_LIBRARY_FILE = 'libcapstone.a'
 
+
 def clean_bins():
     shutil.rmtree(LIBS_DIR, ignore_errors=True)
     shutil.rmtree(HEADERS_DIR, ignore_errors=True)
 
+
 def copy_sources():
     """Copy the C sources into the source directory.
     This rearranges the source files under the python distribution
@@ -92,22 +94,19 @@ def copy_sources():
     shutil.copytree(os.path.join(BUILD_DIR, "include"), os.path.join(SRC_DIR, "include"))
 
     src.extend(glob.glob(os.path.join(BUILD_DIR, "*.[ch]")))
-    src.extend(glob.glob(os.path.join(BUILD_DIR, "*.mk")))
 
-    src.extend(glob.glob(os.path.join(BUILD_DIR, "Makefile")))
     src.extend(glob.glob(os.path.join(BUILD_DIR, "LICENSES/*")))
     src.extend(glob.glob(os.path.join(BUILD_DIR, "README")))
     src.extend(glob.glob(os.path.join(BUILD_DIR, "*.TXT")))
     src.extend(glob.glob(os.path.join(BUILD_DIR, "RELEASE_NOTES")))
-    src.extend(glob.glob(os.path.join(BUILD_DIR, "make.sh")))
     src.extend(glob.glob(os.path.join(BUILD_DIR, "CMakeLists.txt")))
-    src.extend(glob.glob(os.path.join(BUILD_DIR, "pkgconfig.mk")))
 
     for filename in src:
         outpath = os.path.join(SRC_DIR, os.path.basename(filename))
         logger.info("%s -> %s" % (filename, outpath))
         shutil.copy(filename, outpath)
 
+
 def build_libraries():
     """
     Prepare the capstone directory for a binary distribution or installation.
@@ -134,23 +133,22 @@ def build_libraries():
 
     os.chdir(BUILD_DIR)
 
-    # platform description refers at https://docs.python.org/3/library/sys.html#sys.platform
-    # Use cmake for both Darwin and Windows since it can generate fat binaries
-    if SYSTEM == "win32" or SYSTEM == 'darwin':
-        # Windows build: this process requires few things:
-        #    - CMake + MSVC installed
-        #    - Run this command in an environment setup for MSVC
-        if not os.path.exists("build"): os.mkdir("build")
-        os.chdir("build")
-        print("Build Directory: {}\n".format(os.getcwd()))
-        # Only build capstone.dll / libcapstone.dylib
-        if SYSTEM == "win32":
-            os.system('cmake -DCMAKE_BUILD_TYPE=Release -DBUILD_SHARED_LIBS=ON -DCAPSTONE_BUILD_TESTS=OFF -DCAPSTONE_BUILD_CSTOOL=OFF -G "NMake Makefiles" ..')
-        else:
-            os.system('cmake -DCMAKE_BUILD_TYPE=Release -DBUILD_SHARED_LIBS=ON -DCAPSTONE_BUILD_TESTS=OFF -DCAPSTONE_BUILD_CSTOOL=OFF -G "Unix Makefiles" ..')
-        os.system("cmake --build .")
-    else:  # Unix incl. cygwin
-        os.system("CAPSTONE_BUILD_CORE_ONLY=yes bash ./make.sh")
+    # Windows build: this process requires few things:
+    #    - MSVC installed
+    #    - Run this command in an environment setup for MSVC
+    if not os.path.exists("build_py"):
+        os.mkdir("build_py")
+    os.chdir("build_py")
+    print("Build Directory: {}\n".format(os.getcwd()))
+    # Only build capstone.dll / libcapstone.dylib
+    if SYSTEM == "win32":
+        os.system('cmake -DCMAKE_BUILD_TYPE=Release -DBUILD_SHARED_LIBS=ON -DCAPSTONE_BUILD_LEGACY_TESTS=OFF -DCAPSTONE_BUILD_CSTOOL=OFF -G "NMake Makefiles" ..')
+    elif 'AFL_NOOPT' in os.environ:
+        # build for test_corpus
+        os.system('cmake -DBUILD_SHARED_LIBS=ON -DCAPSTONE_BUILD_LEGACY_TESTS=OFF -DCAPSTONE_BUILD_CSTOOL=OFF ..')
+    else:
+        os.system('cmake -DCMAKE_BUILD_TYPE=Release -DBUILD_SHARED_LIBS=ON -DCAPSTONE_BUILD_LEGACY_TESTS=OFF -DCAPSTONE_BUILD_CSTOOL=OFF -G "Unix Makefiles" ..')
+    os.system("cmake --build .")
 
     shutil.copy(VERSIONED_LIBRARY_FILE, os.path.join(LIBS_DIR, LIBRARY_FILE))
 
@@ -182,8 +180,6 @@ class custom_bdist_egg(bdist_egg):
         self.run_command('build')
         return bdist_egg.run(self)
 
-def dummy_src():
-    return []
 
 cmdclass = {}
 cmdclass['build'] = custom_build
@@ -192,6 +188,7 @@ cmdclass['bdist_egg'] = custom_bdist_egg
 
 try:
     from setuptools.command.develop import develop
+
     class custom_develop(develop):
         def run(self):
             logger.info("Building C extensions")
diff --git a/bindings/python/tests/test_aarch64.py b/bindings/python/tests/test_aarch64.py
deleted file mode 100755
index df9ca0e62..000000000
--- a/bindings/python/tests/test_aarch64.py
+++ /dev/null
@@ -1,193 +0,0 @@
-#!/usr/bin/env python3
-
-# Capstone Python bindings, by Nguyen Anh Quynnh <aquynh@gmail.com>
-
-from capstone import *
-from capstone.aarch64 import *
-from xprint import to_hex, to_x, to_x_32
-
-
-AArch64_CODE = b"\x09\x00\x38\xd5\xbf\x40\x00\xd5\x0c\x05\x13\xd5\x20\x50\x02\x0e\x20\xe4\x3d\x0f\x00\x18\xa0\x5f\xa2\x00\xae\x9e\x9f\x37\x03\xd5\xbf\x33\x03\xd5\xdf\x3f\x03\xd5\x21\x7c\x02\x9b\x21\x7c\x00\x53\x00\x40\x21\x4b\xe1\x0b\x40\xb9\x20\x04\x81\xda\x20\x08\x02\x8b\x10\x5b\xe8\x3c\xfd\x7b\xba\xa9\xfd\xc7\x43\xf8"
-
-all_tests = (
-        (CS_ARCH_AARCH64, CS_MODE_ARM, AArch64_CODE, "AARCH64"),
-        )
-
-
-def print_insn_detail(insn):
-    # print address, mnemonic and operands
-    print("0x%x:\t%s\t%s" % (insn.address, insn.mnemonic, insn.op_str))
-
-    # "data" instruction generated by SKIPDATA option has no detail
-    if insn.id == 0:
-        return
-
-    if len(insn.operands) > 0:
-        print("\top_count: %u" % len(insn.operands))
-        c = -1
-        for i in insn.operands:
-            c += 1
-            if i.type == AARCH64_OP_REG:
-                print("\t\toperands[%u].type: REG = %s" % (c, insn.reg_name(i.reg)))
-            if i.type == AARCH64_OP_IMM:
-                print("\t\toperands[%u].type: IMM = 0x%s" % (c, to_x(i.imm)))
-            if i.type == AARCH64_OP_CIMM:
-                print("\t\toperands[%u].type: C-IMM = %u" % (c, i.imm))
-            if i.type == AARCH64_OP_FP:
-                print("\t\toperands[%u].type: FP = %f" % (c, i.fp))
-            if i.type == AARCH64_OP_MEM:
-                print("\t\toperands[%u].type: MEM" % c)
-                if i.mem.base != 0:
-                    print("\t\t\toperands[%u].mem.base: REG = %s" \
-                        % (c, insn.reg_name(i.mem.base)))
-                if i.mem.index != 0:
-                    print("\t\t\toperands[%u].mem.index: REG = %s" \
-                        % (c, insn.reg_name(i.mem.index)))
-                if i.mem.disp != 0:
-                    print("\t\t\toperands[%u].mem.disp: 0x%s" \
-                        % (c, to_x_32(i.mem.disp)))
-                if insn.post_index:
-                    print("\t\t\tpost-indexed: true");
-            if i.type == AARCH64_OP_SME:
-                print("\t\toperands[%u].type: SME_MATRIX" % (c))
-                print("\t\toperands[%u].sme.type: %d" % (c, i.sme.type))
-
-                if i.sme.tile != AARCH64_REG_INVALID:
-                    print("\t\toperands[%u].sme.tile: %s" % (c, insn.reg_name(i.sme.tile)))
-                if i.sme.slice_reg != AARCH64_REG_INVALID:
-                    print("\t\toperands[%u].sme.slice_reg: %s" % (c, insn.reg_name(i.sme.slice_reg)))
-                if i.sme.slice_offset.imm != -1 or i.sme.slice_offset.imm_range.first != -1:
-                    print("\t\toperands[%u].sme.slice_offset: " % (c))
-                    if i.sme.has_range_offset:
-                        print("%hhd:%hhd" % (i.sme.slice_offset.imm_range.first, i.sme.slice_offset.imm_range.offset))
-                    else:
-                        print("%d" % (i.sme.slice_offset.imm))
-                if i.sme.slice_reg != AARCH64_REG_INVALID or i.sme.slice_offset.imm != -1:
-                    print("\t\toperands[%u].sme.is_vertical: %s" % (c, ("true" if i.sme.is_vertical else "false")))
-            if i.type == AARCH64_OP_PRED:
-                print("\t\toperands[%u].type: PREDICATE\n" % c);
-                if (op.pred.reg != AARCH64_REG_INVALID):
-                    print("\t\toperands[%u].pred.reg: %s\n" % (c, insn.reg_name(i.pred.reg)));
-                if (op.pred.vec_select != AARCH64_REG_INVALID):
-                    print("\t\toperands[%u].pred.vec_select: %s\n" % (c, insn.reg_name(i.pred.vec_select)));
-                if (op.pred.imm_index != -1):
-                    print("\t\toperands[%u].pred.imm_index: %d\n" % (i, op.pred.imm_index));
-                break;
-            if i.type == AARCH64_OP_SYSREG:
-                print("\t\toperands[%u].type: SYS REG:" % (c))
-                if i.sysop.sub_type == AARCH64_OP_REG_MRS:
-                    print("\t\toperands[%u].subtype: REG_MRS = 0x%x" % (c, i.sysop.reg.sysreg))
-                if i.sysop.sub_type == AARCH64_OP_REG_MSR:
-                    print("\t\toperands[%u].subtype: REG_MSR = 0x%x" % (c, i.sysop.reg.sysreg))
-                if i.sysop.sub_type == AARCH64_OP_TLBI:
-                    print("\t\toperands[%u].subtype TLBI = 0x%x" % (c, i.sysop.reg.tlbi))
-                if i.sysop.sub_type == AARCH64_OP_IC:
-                    print("\t\toperands[%u].subtype IC = 0x%x" % (c, i.sysop.reg.ic))
-            if i.type == AARCH64_OP_SYSALIAS:
-                print("\t\toperands[%u].type: SYS ALIAS:" % (c))
-                if i.sysop.sub_type == AARCH64_OP_SVCR:
-                    if i.sysop.alias.svcr == AARCH64_SVCR_SVCRSM:
-                        print("\t\t\toperands[%u].svcr: BIT = SM" % (c))
-                    elif i.sysop.alias.svcr == AARCH64_SVCR_SVCRZA:
-                        print("\t\t\toperands[%u].svcr: BIT = ZA" % (c))
-                    elif i.sysop.alias.svcr == AARCH64_SVCR_SVCRSMZA:
-                        print("\t\t\toperands[%u].svcr: BIT = SM & ZA" % (c))
-                if i.sysop.sub_type == AARCH64_OP_AT:
-                    print("\t\toperands[%u].subtype AT = 0x%x" % (c, i.sysop.alias.at))
-                if i.sysop.sub_type == AARCH64_OP_DB:
-                    print("\t\toperands[%u].subtype DB = 0x%x" % (c, i.sysop.alias.db))
-                if i.sysop.sub_type == AARCH64_OP_DC:
-                    print("\t\toperands[%u].subtype DC = 0x%x" % (c, i.sysop.alias.dc))
-                if i.sysop.sub_type == AARCH64_OP_ISB:
-                    print("\t\toperands[%u].subtype ISB = 0x%x" % (c, i.sysop.alias.isb))
-                if i.sysop.sub_type == AARCH64_OP_TSB:
-                    print("\t\toperands[%u].subtype TSB = 0x%x" % (c, i.sysop.alias.tsb))
-                if i.sysop.sub_type == AARCH64_OP_PRFM:
-                    print("\t\toperands[%u].subtype PRFM = 0x%x" % (c, i.sysop.alias.prfm))
-                if i.sysop.sub_type == AARCH64_OP_SVEPRFM:
-                    print("\t\toperands[%u].subtype SVEPRFM = 0x%x" % (c, i.sysop.alias.sveprfm))
-                if i.sysop.sub_type == AARCH64_OP_RPRFM:
-                    print("\t\toperands[%u].subtype RPRFM = 0x%x" % (c, i.sysop.alias.rprfm))
-                if i.sysop.sub_type == AARCH64_OP_PSTATEIMM0_15:
-                    print("\t\toperands[%u].subtype PSTATEIMM0_15 = 0x%x" % (c, i.sysop.alias.pstateimm0_15))
-                if i.sysop.sub_type == AARCH64_OP_PSTATEIMM0_1:
-                    print("\t\toperands[%u].subtype PSTATEIMM0_1 = 0x%x" % (c, i.sysop.alias.pstateimm0_1))
-                if i.sysop.sub_type == AARCH64_OP_PSB:
-                    print("\t\toperands[%u].subtype PSB = 0x%x" % (c, i.sysop.alias.psb))
-                if i.sysop.sub_type == AARCH64_OP_BTI:
-                    print("\t\toperands[%u].subtype BTI = 0x%x" % (c, i.sysop.alias.bti))
-                if i.sysop.sub_type == AARCH64_OP_SVEPREDPAT:
-                    print("\t\toperands[%u].subtype SVEPREDPAT = 0x%x" % (c, i.sysop.alias.svepredpat))
-                if i.sysop.sub_type == AARCH64_OP_SVEVECLENSPECIFIER:
-                    print("\t\toperands[%u].subtype SVEVECLENSPECIFIER = 0x%x" % (c, i.sysop.alias.sveveclenspecifier))
-            if i.type == AARCH64_OP_SYSIMM:
-                print("\t\toperands[%u].type: SYS IMM:" % (c))
-                if i.sysop.sub_type == AARCH64_OP_EXACTFPIMM:
-                    print("\t\toperands[%u].subtype EXACTFPIMM = %d" % (c, i.sysop.imm.exactfpimm))
-                if i.sysop.sub_type == AARCH64_OP_DBNXS:
-                    print("\t\toperands[%u].subtype DBNXS = %d" % (c, i.sysop.imm.dbnxs))
-
-            if i.access == CS_AC_READ:
-                print("\t\toperands[%u].access: READ" % (c))
-            elif i.access == CS_AC_WRITE:
-                print("\t\toperands[%u].access: WRITE" % (c))
-            elif i.access == CS_AC_READ | CS_AC_WRITE:
-                print("\t\toperands[%u].access: READ | WRITE" % (c))
-
-            if i.shift.type != AARCH64_SFT_INVALID and i.shift.value:
-                print("\t\t\tShift: type = %u, value = %u" % (i.shift.type, i.shift.value))
-
-            if i.ext != AARCH64_EXT_INVALID:
-                print("\t\t\tExt: %u" % i.ext)
-
-            if i.vas != AARCH64LAYOUT_INVALID:
-                print("\t\t\tVector Arrangement Specifier: 0x%x" % i.vas)
-
-            if i.vector_index != -1:
-                print("\t\t\tVector Index: %u" % i.vector_index)
-
-    if insn.writeback:
-        print("\tWrite-back: True")
-            
-    if insn.cc != AArch64CC_Invalid:
-        print("\tCode-condition: %u" % insn.cc)
-    if insn.update_flags:
-        print("\tUpdate-flags: True")
-
-    (regs_read, regs_write) = insn.regs_access()
-
-    if len(regs_read) > 0:
-        print("\tRegisters read:", end="")
-        for r in regs_read:
-            print(" %s" %(insn.reg_name(r)), end="")
-        print("")
-
-    if len(regs_write) > 0:
-        print("\tRegisters modified:", end="")
-        for r in regs_write:
-            print(" %s" %(insn.reg_name(r)), end="")
-        print("")
-
-
-# ## Test class Cs
-def test_class():
-
-    for (arch, mode, code, comment) in all_tests:
-        print("*" * 16)
-        print("Platform: %s" % comment)
-        print("Code: %s" % to_hex(code))
-        print("Disasm:")
-
-        try:
-            md = Cs(arch, mode)
-            md.detail = True
-            for insn in md.disasm(code, 0x2c):
-                print_insn_detail(insn)
-                print ()
-            print("0x%x:\n" % (insn.address + insn.size))
-        except CsError as e:
-            print("ERROR: %s" % e)
-
-
-if __name__ == '__main__':
-    test_class()
diff --git a/bindings/python/tests/test_all.py b/bindings/python/tests/test_all.py
index 4b9ead884..b5f3942f0 100755
--- a/bindings/python/tests/test_all.py
+++ b/bindings/python/tests/test_all.py
@@ -1,26 +1,9 @@
 #!/usr/bin/env python3
 
-import test_basic, test_arm, test_aarch64, test_detail, test_lite, test_m68k, test_mips, \
-    test_ppc, test_x86, test_skipdata, test_sparc, test_systemz, test_tms320c64x, test_customized_mnem, \
-    test_m680x, test_mos65xx, test_xcore, test_riscv, test_alpha, test_hppa
+import test_lite
+import test_skipdata
+import test_customized_mnem
 
-test_basic.test_class()
-test_arm.test_class()
-test_aarch64.test_class()
-test_detail.test_class()
 test_lite.test_class()
-test_m68k.test_class()
-test_mips.test_class()
-test_mos65xx.test_class()
-test_ppc.test_class()
-test_sparc.test_class()
-test_systemz.test_class()
-test_x86.test_class()
-test_tms320c64x.test_class()
-test_m680x.test_class()
 test_skipdata.test_class()
 test_customized_mnem.test()
-test_xcore.test_class()
-test_riscv.test_class()
-test_alpha.test_class()
-test_hppa.test_class()
diff --git a/bindings/python/tests/test_alpha.py b/bindings/python/tests/test_alpha.py
deleted file mode 100755
index 056288ae2..000000000
--- a/bindings/python/tests/test_alpha.py
+++ /dev/null
@@ -1,57 +0,0 @@
-#!/usr/bin/env python3
-
-# Capstone Python bindings, by Dmitry Sibirtsev <sibirtsev_dl@gmail.com>
-
-from capstone import *
-from capstone.alpha import *
-from xprint import to_x, to_hex
-
-ALPHA_CODE = b'\x02\x00\xbb\x27\x50\x7a\xbd\x23\xd0\xff\xde\x23\x00\x00\x5e\xb7'
-ALPHA_CODE_BE = b'\x27\xbb\x00\x02\x23\xbd\x7a\x50\x23\xde\xff\xd0\xb7\x5e\x00\x00'
-
-all_tests = (
-    (CS_ARCH_ALPHA, CS_MODE_LITTLE_ENDIAN, ALPHA_CODE, "Alpha (Little-endian)"),
-    (CS_ARCH_ALPHA, CS_MODE_BIG_ENDIAN, ALPHA_CODE_BE, "Alpha (Big-endian)"),
-)
-
-
-def print_insn_detail(insn):
-    # print address, mnemonic and operands
-    print("0x%x:\t%s\t%s" % (insn.address, insn.mnemonic, insn.op_str))
-
-    # "data" instruction generated by SKIPDATA option has no detail
-    if insn.id == 0:
-        return
-
-    if len(insn.operands) > 0:
-        print("\top_count: %u" % len(insn.operands))
-        c = 0
-        for i in insn.operands:
-            if i.type == ALPHA_OP_REG:
-                print("\t\toperands[%u].type: REG = %s" % (c, insn.reg_name(i.reg)))
-            if i.type == ALPHA_OP_IMM:
-                print("\t\toperands[%u].type: IMM = 0x%s" % (c, to_x(i.imm)))
-            c += 1
-
-
-# ## Test class Cs
-def test_class():
-    for (arch, mode, code, comment) in all_tests:
-        print("*" * 16)
-        print("Platform: %s" % comment)
-        print("Code: %s" % to_hex(code))
-        print("Disasm:")
-
-        try:
-            md = Cs(arch, mode)
-            md.detail = True
-            for insn in md.disasm(code, 0x1000):
-                print_insn_detail(insn)
-                print()
-            print("0x%x:\n" % (insn.address + insn.size))
-        except CsError as e:
-            print("ERROR: %s" % e)
-
-
-if __name__ == '__main__':
-    test_class()
diff --git a/bindings/python/tests/test_arm.py b/bindings/python/tests/test_arm.py
deleted file mode 100755
index 305674462..000000000
--- a/bindings/python/tests/test_arm.py
+++ /dev/null
@@ -1,189 +0,0 @@
-#!/usr/bin/env python3
-
-# Capstone Python bindings, by Nguyen Anh Quynnh <aquynh@gmail.com>
-
-from capstone import *
-from capstone.arm import *
-from xprint import to_hex, to_x_32
-
-
-ARM_CODE = b"\x86\x48\x60\xf4\x4d\x0f\xe2\xf4\xED\xFF\xFF\xEB\x04\xe0\x2d\xe5\x00\x00\x00\x00\xe0\x83\x22\xe5\xf1\x02\x03\x0e\x00\x00\xa0\xe3\x02\x30\xc1\xe7\x00\x00\x53\xe3\x00\x02\x01\xf1\x05\x40\xd0\xe8\xf4\x80\x00\x00"
-ARM_CODE2 = b"\xd1\xe8\x00\xf0\xf0\x24\x04\x07\x1f\x3c\xf2\xc0\x00\x00\x4f\xf0\x00\x01\x46\x6c"
-THUMB_CODE = b"\x60\xf9\x1f\x04\xe0\xf9\x4f\x07\x70\x47\x00\xf0\x10\xe8\xeb\x46\x83\xb0\xc9\x68\x1f\xb1\x30\xbf\xaf\xf3\x20\x84\x52\xf8\x23\xf0"
-THUMB_CODE2 = b"\x4f\xf0\x00\x01\xbd\xe8\x00\x88\xd1\xe8\x00\xf0\x18\xbf\xad\xbf\xf3\xff\x0b\x0c\x86\xf3\x00\x89\x80\xf3\x00\x8c\x4f\xfa\x99\xf6\xd0\xff\xa2\x01"
-THUMB_MCLASS = b"\xef\xf3\x02\x80"
-ARMV8 = b"\xe0\x3b\xb2\xee\x42\x00\x01\xe1\x51\xf0\x7f\xf5"
-
-all_tests = (
-        (CS_ARCH_ARM, CS_MODE_ARM, ARM_CODE, "ARM", None),
-        (CS_ARCH_ARM, CS_MODE_THUMB, THUMB_CODE, "Thumb", None),
-        (CS_ARCH_ARM, CS_MODE_THUMB, ARM_CODE2, "Thumb-mixed", None),
-        (CS_ARCH_ARM, CS_MODE_THUMB, THUMB_CODE2, "Thumb-2 & register named with numbers", CS_OPT_SYNTAX_NOREGNAME),
-        (CS_ARCH_ARM, CS_MODE_THUMB + CS_MODE_MCLASS, THUMB_MCLASS, "Thumb-MClass", None),
-        (CS_ARCH_ARM, CS_MODE_ARM + CS_MODE_V8, ARMV8, "Arm-V8", None),
-        )
-
-
-def print_insn_detail(insn):
-    # print address, mnemonic and operands
-    print("0x%x:\t%s\t%s" % (insn.address, insn.mnemonic, insn.op_str))
-
-    # "data" instruction generated by SKIPDATA option has no detail
-    if insn.id == 0:
-        return
-
-    if len(insn.operands) > 0:
-        print("\top_count: %u" % len(insn.operands))
-        c = 0
-        for i in insn.operands:
-            if i.type == ARM_OP_REG:
-                print("\t\toperands[%u].type: REG = %s" % (c, insn.reg_name(i.reg)))
-            elif i.type == ARM_OP_IMM:
-                print("\t\toperands[%u].type: IMM = 0x%s" % (c, to_x_32(i.imm)))
-            elif i.type == ARM_OP_FP:
-                print("\t\toperands[%u].type: FP = %f" % (c, i.fp))
-            elif i.type == ARM_OP_PRED:
-                print("\t\toperands[%u].type: PRED = %d" % (c, i.pred))
-            elif i.type == ARM_OP_CIMM:
-                print("\t\toperands[%u].type: C-IMM = %u" % (c, i.imm))
-            elif i.type == ARM_OP_PIMM:
-                print("\t\toperands[%u].type: P-IMM = %u" % (c, i.imm))
-            elif i.type == ARM_OP_SETEND:
-                if i.setend == ARM_SETEND_BE:
-                    print("\t\toperands[%u].type: SETEND = be" % c)
-                else:
-                    print("\t\toperands[%u].type: SETEND = le" % c)
-            elif i.type == ARM_OP_MEM:
-                print("\t\toperands[%u].type: MEM" % c)
-                if i.mem.base != 0:
-                    print("\t\t\toperands[%u].mem.base: REG = %s" \
-                        % (c, insn.reg_name(i.mem.base)))
-                if i.mem.index != 0:
-                    print("\t\t\toperands[%u].mem.index: REG = %s" \
-                        % (c, insn.reg_name(i.mem.index)))
-                if i.mem.scale != 1:
-                    print("\t\t\toperands[%u].mem.scale: %u" \
-                        % (c, i.mem.scale))
-                if i.mem.disp != 0:
-                    print("\t\t\toperands[%u].mem.disp: 0x%s" \
-                        % (c, to_x_32(i.mem.disp)))
-                if i.mem.lshift != 0:
-                    print("\t\t\toperands[%u].mem.lshift: 0x%s" \
-                        % (c, to_x_32(i.mem.lshift)))
-            elif i.type == ARM_OP_SYSM:
-                print("\t\toperands[%u].type: SYSM = 0x%x" % (c, i.sysop.sysm))
-                print("\t\toperands[%u].type: MASK = %u" % (c, i.sysop.msr_mask))
-            elif i.type == ARM_OP_SYSREG:
-                print("\t\toperands[%u].type: SYSREG = %s" % (c, insn.reg_name(i.sysop.reg.mclasssysreg)))
-                print("\t\toperands[%u].type: MASK = %u" % (c, i.sysop.msr_mask))
-            elif i.type == ARM_OP_BANKEDREG:
-                print("\t\toperands[%u].type: BANKEDREG = %u" % (c, i.sysop.reg.bankedreg))
-                if i.sysop.msr_mask != 2 ** (ctypes.sizeof(ctypes.c_uint8) * 8) - 1:
-                    print("\t\toperands[%u].type: MASK = %u" % (c, i.sysop.msr_mask))
-            elif i.type in [ARM_OP_SPSR, ARM_OP_CPSR]:
-                print("\t\toperands[%u].type: %sPSR = " % (c, "S" if i.type == ARM_OP_SPSR else "C"), end="")
-                field = i.sysop.psr_bits
-                if (field & ARM_FIELD_SPSR_F) > 0 or (field & ARM_FIELD_CPSR_F) > 0:
-                    print("f", end="")
-                if (field & ARM_FIELD_SPSR_S) > 0 or (field & ARM_FIELD_CPSR_S) > 0:
-                    print("s", end="")
-                if (field & ARM_FIELD_SPSR_X) > 0 or (field & ARM_FIELD_CPSR_X) > 0:
-                    print("x", end="")
-                if (field & ARM_FIELD_SPSR_C) > 0 or (field & ARM_FIELD_CPSR_C) > 0:
-                    print("c", end="")
-                print()
-                print("\t\toperands[%u].type: MASK = %u" % (c, i.sysop.msr_mask))
-            else:
-                print("\t\toperands[%u].type: UNKNOWN = %u" % (c, i.type))
-
-            if i.neon_lane != -1:
-                print("\t\toperands[%u].neon_lane = %u" % (c, i.neon_lane))
-
-            if i.access == CS_AC_READ:
-                print("\t\toperands[%u].access: READ" % (c))
-            elif i.access == CS_AC_WRITE:
-                print("\t\toperands[%u].access: WRITE" % (c))
-            elif i.access == CS_AC_READ | CS_AC_WRITE:
-                print("\t\toperands[%u].access: READ | WRITE" % (c))
-
-            if i.shift.type != ARM_SFT_INVALID and i.shift.value:
-                if i.shift.type < ARM_SFT_ASR_REG:
-                    # shift with constant value
-                    print("\t\t\tShift: %u = %u" \
-                        % (i.shift.type, i.shift.value))
-                else:
-                    # shift with register
-                    print("\t\t\tShift: %u = %s" \
-                        % (i.shift.type, insn.reg_name(i.shift.value)))
-            if i.vector_index != -1:
-                print("\t\t\toperands[%u].vector_index = %u" %(c, i.vector_index))
-            if i.subtracted:
-                print("\t\t\toperands[%u].subtracted = True" %c)
-
-            c += 1
-
-    if not insn.cc in [ARMCC_AL, ARMCC_UNDEF]:
-        print("\tCode condition: %u" % insn.cc)
-    if insn.vcc != ARMVCC_None:
-        print("\tVector code condition: %u" % insn.vcc)
-    if insn.update_flags:
-        print("\tUpdate-flags: True")
-    if insn.writeback:
-        if insn.post_index:
-            print("\tWrite-back: Post")
-        else:
-            print("\tWrite-back: Pre")
-    if insn.cps_mode:
-        print("\tCPSI-mode: %u" %(insn.cps_mode))
-    if insn.cps_flag:
-        print("\tCPSI-flag: %u" %(insn.cps_flag))
-    if insn.vector_data:
-        print("\tVector-data: %u" %(insn.vector_data))
-    if insn.vector_size:
-        print("\tVector-size: %u" %(insn.vector_size))
-    if insn.usermode:
-        print("\tUser-mode: True")
-    if insn.mem_barrier:
-        print("\tMemory-barrier: %u" %(insn.mem_barrier))
-    if insn.pred_mask:
-        print("\tPredicate Mask: 0x%x" %(insn.pred_mask))
-
-    (regs_read, regs_write) = insn.regs_access()
-
-    if len(regs_read) > 0:
-        print("\tRegisters read:", end="")
-        for r in regs_read:
-            print(" %s" %(insn.reg_name(r)), end="")
-        print("")
-
-    if len(regs_write) > 0:
-        print("\tRegisters modified:", end="")
-        for r in regs_write:
-            print(" %s" %(insn.reg_name(r)), end="")
-        print("")
-
-
-# ## Test class Cs
-def test_class():
-
-    for (arch, mode, code, comment, syntax) in all_tests:
-        print("*" * 16)
-        print("Platform: %s" % comment)
-        print("Code: %s" % to_hex(code))
-        print("Disasm:")
-
-        try:
-            md = Cs(arch, mode)
-            if syntax is not None:
-                md.syntax = syntax
-            md.detail = True
-            for insn in md.disasm(code, 0x80001000):
-                print_insn_detail(insn)
-                print ()
-            print("0x%x:\n" % (insn.address + insn.size))
-        except CsError as e:
-            print("ERROR: %s" % e)
-
-
-if __name__ == '__main__':
-    test_class()
diff --git a/bindings/python/tests/test_basic.py b/bindings/python/tests/test_basic.py
deleted file mode 100755
index a114b1f0c..000000000
--- a/bindings/python/tests/test_basic.py
+++ /dev/null
@@ -1,144 +0,0 @@
-#!/usr/bin/env python3
-# Capstone Python bindings, by Nguyen Anh Quynnh <aquynh@gmail.com>
-
-from capstone import *
-
-from xprint import to_hex
-
-
-X86_CODE16 = b"\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00"
-X86_CODE32 = b"\xba\xcd\xab\x00\x00\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00"
-X86_CODE64 = b"\x55\x48\x8b\x05\xb8\x13\x00\x00"
-ARM_CODE = b"\xED\xFF\xFF\xEB\x04\xe0\x2d\xe5\x00\x00\x00\x00\xe0\x83\x22\xe5\xf1\x02\x03\x0e\x00\x00\xa0\xe3\x02\x30\xc1\xe7\x00\x00\x53\xe3"
-ARM_CODE2 = b"\x10\xf1\x10\xe7\x11\xf2\x31\xe7\xdc\xa1\x2e\xf3\xe8\x4e\x62\xf3"
-THUMB_CODE = b"\x70\x47\xeb\x46\x83\xb0\xc9\x68"
-THUMB_CODE2 = b"\x4f\xf0\x00\x01\xbd\xe8\x00\x88\xd1\xe8\x00\xf0"
-THUMB_MCLASS = b"\xef\xf3\x02\x80"
-ARMV8 = b"\xe0\x3b\xb2\xee\x42\x00\x01\xe1\x51\xf0\x7f\xf5"
-MIPS_CODE = b"\x0C\x10\x00\x97\x00\x00\x00\x00\x24\x02\x00\x0c\x8f\xa2\x00\x00\x34\x21\x34\x56"
-MIPS_CODE2 = b"\x56\x34\x21\x34\xc2\x17\x01\x00"
-MIPS_32R6M = b"\x00\x07\x00\x07\x00\x11\x93\x7c\x01\x8c\x8b\x7c\x00\xc7\x48\xd0"
-MIPS_32R6 = b"\xec\x80\x00\x19\x7c\x43\x22\xa0"
-AARCH64_CODE = b"\x21\x7c\x02\x9b\x21\x7c\x00\x53\x00\x40\x21\x4b\xe1\x0b\x40\xb9"
-PPC_CODE = b"\x80\x20\x00\x00\x80\x3f\x00\x00\x10\x43\x23\x0e\xd0\x44\x00\x80\x4c\x43\x22\x02\x2d\x03\x00\x80\x7c\x43\x20\x14\x7c\x43\x20\x93\x4f\x20\x00\x21\x4c\xc8\x00\x21"
-PPC_CODE2 = b"\x10\x60\x2a\x10\x10\x64\x28\x88\x7c\x4a\x5d\x0f"
-SPARC_CODE = b"\x80\xa0\x40\x02\x85\xc2\x60\x08\x85\xe8\x20\x01\x81\xe8\x00\x00\x90\x10\x20\x01\xd5\xf6\x10\x16\x21\x00\x00\x0a\x86\x00\x40\x02\x01\x00\x00\x00\x12\xbf\xff\xff\x10\xbf\xff\xff\xa0\x02\x00\x09\x0d\xbf\xff\xff\xd4\x20\x60\x00\xd4\x4e\x00\x16\x2a\xc2\x80\x03"
-SPARCV9_CODE = b"\x81\xa8\x0a\x24\x89\xa0\x10\x20\x89\xa0\x1a\x60\x89\xa0\x00\xe0"
-SYSZ_CODE = b"\xed\x00\x00\x00\x00\x1a\x5a\x0f\x1f\xff\xc2\x09\x80\x00\x00\x00\x07\xf7\xeb\x2a\xff\xff\x7f\x57\xe3\x01\xff\xff\x7f\x57\xeb\x00\xf0\x00\x00\x24\xb2\x4f\x00\x78"
-XCORE_CODE = b"\xfe\x0f\xfe\x17\x13\x17\xc6\xfe\xec\x17\x97\xf8\xec\x4f\x1f\xfd\xec\x37\x07\xf2\x45\x5b\xf9\xfa\x02\x06\x1b\x10"
-M68K_CODE = b"\xd4\x40\x87\x5a\x4e\x71\x02\xb4\xc0\xde\xc0\xde\x5c\x00\x1d\x80\x71\x12\x01\x23\xf2\x3c\x44\x22\x40\x49\x0e\x56\x54\xc5\xf2\x3c\x44\x00\x44\x7a\x00\x00\xf2\x00\x0a\x28\x4E\xB9\x00\x00\x00\x12\x4E\x75"
-TMS320C64X_CODE = b"\x01\xac\x88\x40\x81\xac\x88\x43\x00\x00\x00\x00\x02\x90\x32\x96\x02\x80\x46\x9e\x05\x3c\x83\xe6\x0b\x0c\x8b\x24"
-M680X_CODE = b"\x06\x10\x19\x1a\x55\x1e\x01\x23\xe9\x31\x06\x34\x55\xa6\x81\xa7\x89\x7f\xff\xa6\x9d\x10\x00\xa7\x91\xa6\x9f\x10\x00\x11\xac\x99\x10\x00\x39"
-EVM_CODE = b"\x60\x61"
-WASM_CODE = b"\x20\x00\x20\x01\x41\x20\x10\xc9\x01\x45\x0b"
-MOS65XX_CODE = b"\x0d\x34\x12\x00\x81\x65\x6c\x01\x00\x85\xFF\x10\x00\x19\x42\x42\x00\x49\x42"
-EBPF_CODE = b"\x97\x09\x00\x00\x37\x13\x03\x00\xdc\x02\x00\x00\x20\x00\x00\x00\x30\x00\x00\x00\x00\x00\x00\x00\xdb\x3a\x00\x01\x00\x00\x00\x00\x84\x02\x00\x00\x00\x00\x00\x00\x6d\x33\x17\x02\x00\x00\x00\x00"
-RISCV_CODE32 = b"\x37\x34\x00\x00\x97\x82\x00\x00\xef\x00\x80\x00\xef\xf0\x1f\xff\xe7\x00\x45\x00\xe7\x00\xc0\xff\x63\x05\x41\x00\xe3\x9d\x61\xfe\x63\xca\x93\x00\x63\x53\xb5\x00\x63\x65\xd6\x00\x63\x76\xf7\x00\x03\x88\x18\x00\x03\x99\x49\x00\x03\xaa\x6a\x00\x03\xcb\x2b\x01\x03\xdc\x8c\x01\x23\x86\xad\x03\x23\x9a\xce\x03\x23\x8f\xef\x01\x93\x00\xe0\x00\x13\xa1\x01\x01\x13\xb2\x02\x7d\x13\xc3\x03\xdd\x13\xe4\xc4\x12\x13\xf5\x85\x0c\x13\x96\xe6\x01\x13\xd7\x97\x01\x13\xd8\xf8\x40\x33\x89\x49\x01\xb3\x0a\x7b\x41\x33\xac\xac\x01\xb3\x3d\xde\x01\x33\xd2\x62\x40\xb3\x43\x94\x00\x33\xe5\xc5\x00\xb3\x76\xf7\x00\xb3\x54\x39\x01\xb3\x50\x31\x00\x33\x9f\x0f\x00"
-RISCV_CODE64 = b"\x13\x04\xa8\x7a"
-ALPHA_CODE = b'\x02\x00\xbb\x27\x50\x7a\xbd\x23\xd0\xff\xde\x23\x00\x00\x5e\xb7'
-ALPHA_CODE_BE = b'\x27\xbb\x00\x02\x23\xbd\x7a\x50\x23\xde\xff\xd0\xb7\x5e\x00\x00'
-HPPA_20_CODE_BE = b'\x00\x20\x50\xa2\x00\x01\x58\x20\x00\x00\x44\xa1\x00\x41\x18\x40\x00\x20\x08\xa2\x01\x60\x48\xa1\x01\x61\x18\xc0\x00\x00\x14\xa1\x00\x0f\x0d\x61\x00\x0f\x0e\x61\x00\x01\x18\x60\x00\x00\x0c\x00\x00\x00\x0c\xa0\x03\xff\xc0\x1f\x00\x00\x04\x00\x00\x10\x04\x00\x04\x22\x51\x83\x04\x22\x51\xc3\x04\x22\x51\x83\x04\x2f\x71\x83\x04\x2f\x71\xc3\x04\x2f\x71\x83\x04\x41\x53\x43\x04\x41\x53\x63\x04\x41\x53\x03\x04\x41\x12\x00\x04\x41\x16\x00\x04\x41\x16\x20\x04\x41\x42\x00\x04\x41\x46\x00\x04\x41\x46\x20\x04\x41\x12\x40\x04\x41\x12\x60\x04\x41\x42\x40\x04\x41\x42\x60\x04\x41\x18\x00\x04\x41\x08\x00\x04\x41\x13\x80\x04\x41\x13\xa0\x04\x41\x52\x80\x04\x41\x52\xa0\x04\x5e\x72\x80\x04\x41\x42\x80\x04\x41\x52\xc0\x04\x41\x52\xe0\x04\x41\x42\xc0\x04\x41\x42\xe0\x14\x00\xde\xad'
-HPPA_20_CODE =    b'\xa2\x50\x20\x00\x20\x58\x01\x00\xa1\x44\x00\x00\x40\x18\x41\x00\xa2\x08\x20\x00\xa1\x48\x60\x01\xc0\x18\x61\x01\xa1\x14\x00\x00\x61\x0d\x0f\x00\x61\x0e\x0f\x00\x60\x18\x01\x00\x00\x0c\x00\x00\xa0\x0c\x00\x00\x1f\xc0\xff\x03\x00\x04\x00\x00\x00\x04\x10\x00\x83\x51\x22\x04\xc3\x51\x22\x04\x83\x51\x22\x04\x83\x71\x2f\x04\xc3\x71\x2f\x04\x83\x71\x2f\x04\x43\x53\x41\x04\x63\x53\x41\x04\x03\x53\x41\x04\x00\x12\x41\x04\x00\x16\x41\x04\x20\x16\x41\x04\x00\x42\x41\x04\x00\x46\x41\x04\x20\x46\x41\x04\x40\x12\x41\x04\x60\x12\x41\x04\x40\x42\x41\x04\x60\x42\x41\x04\x00\x18\x41\x04\x00\x08\x41\x04\x80\x13\x41\x04\xa0\x13\x41\x04\x80\x52\x41\x04\xa0\x52\x41\x04\x80\x72\x5e\x04\x80\x42\x41\x04\xc0\x52\x41\x04\xe0\x52\x41\x04\xc0\x42\x41\x04\xe0\x42\x41\x04\xad\xde\x00\x14'
-HPPA_11_CODE_BE = b'\x24\x41\x40\xc3\x24\x41\x60\xc3\x24\x41\x40\xe3\x24\x41\x60\xe3\x24\x41\x68\xe3\x2c\x41\x40\xc3\x2c\x41\x60\xc3\x2c\x41\x40\xe3\x2c\x41\x60\xe3\x2c\x41\x68\xe3\x24\x62\x42\xc1\x24\x62\x62\xc1\x24\x62\x42\xe1\x24\x62\x46\xe1\x24\x62\x62\xe1\x24\x62\x6a\xe1\x2c\x62\x42\xc1\x2c\x62\x62\xc1\x2c\x62\x42\xe1\x2c\x62\x46\xe1\x2c\x62\x62\xe1\x2c\x62\x6a\xe1\x24\x3e\x50\xc2\x24\x3e\x50\xe2\x24\x3e\x70\xe2\x24\x3e\x78\xe2\x2c\x3e\x50\xc2\x2c\x3e\x50\xe2\x2c\x3e\x70\xe2\x2c\x3e\x78\xe2\x24\x5e\x52\xc1\x24\x5e\x52\xe1\x24\x5e\x56\xe1\x24\x5e\x72\xe1\x24\x5e\x7a\xe1\x2c\x5e\x52\xc1\x2c\x5e\x52\xe1\x2c\x5e\x56\xe1\x2c\x5e\x72\xe1\x2c\x5e\x7a\xe1'
-HPPA_11_CODE =    b'\xc3\x40\x41\x24\xc3\x60\x41\x24\xe3\x40\x41\x24\xe3\x60\x41\x24\xe3\x68\x41\x24\xc3\x40\x41\x2c\xc3\x60\x41\x2c\xe3\x40\x41\x2c\xe3\x60\x41\x2c\xe3\x68\x41\x2c\xc1\x42\x62\x24\xc1\x62\x62\x24\xe1\x42\x62\x24\xe1\x46\x62\x24\xe1\x62\x62\x24\xe1\x6a\x62\x24\xc1\x42\x62\x2c\xc1\x62\x62\x2c\xe1\x42\x62\x2c\xe1\x46\x62\x2c\xe1\x62\x62\x2c\xe1\x6a\x62\x2c\xc2\x50\x3e\x24\xe2\x50\x3e\x24\xe2\x70\x3e\x24\xe2\x78\x3e\x24\xc2\x50\x3e\x2c\xe2\x50\x3e\x2c\xe2\x70\x3e\x2c\xe2\x78\x3e\x2c\xc1\x52\x5e\x24\xe1\x52\x5e\x24\xe1\x56\x5e\x24\xe1\x72\x5e\x24\xe1\x7a\x5e\x24\xc1\x52\x5e\x2c\xe1\x52\x5e\x2c\xe1\x56\x5e\x2c\xe1\x72\x5e\x2c\xe1\x7a\x5e\x2c'
-
-
-all_tests = (
-        (CS_ARCH_X86, CS_MODE_16, X86_CODE16, "X86 16bit (Intel syntax)", None),
-        (CS_ARCH_X86, CS_MODE_32, X86_CODE32, "X86 32bit (ATT syntax)", CS_OPT_SYNTAX_ATT),
-        (CS_ARCH_X86, CS_MODE_32, X86_CODE32, "X86 32 (Intel syntax)", None),
-        (CS_ARCH_X86, CS_MODE_32, X86_CODE32, "X86 32 (MASM syntax)", CS_OPT_SYNTAX_MASM),
-        (CS_ARCH_X86, CS_MODE_64, X86_CODE64, "X86 64 (Intel syntax)", None),
-        (CS_ARCH_ARM, CS_MODE_ARM, ARM_CODE, "ARM", None),
-        (CS_ARCH_ARM, CS_MODE_THUMB, THUMB_CODE2, "THUMB-2", None),
-        (CS_ARCH_ARM, CS_MODE_ARM, ARM_CODE2, "ARM: Cortex-A15 + NEON", None),
-        (CS_ARCH_ARM, CS_MODE_THUMB, THUMB_CODE, "THUMB", None),
-        (CS_ARCH_ARM, CS_MODE_THUMB + CS_MODE_MCLASS, THUMB_MCLASS, "Thumb-MClass", None),
-        (CS_ARCH_ARM, CS_MODE_ARM + CS_MODE_V8, ARMV8, "Arm-V8", None),
-        (CS_ARCH_MIPS, CS_MODE_MIPS32 + CS_MODE_BIG_ENDIAN, MIPS_CODE, "MIPS-32 (Big-endian)", None),
-        (CS_ARCH_MIPS, CS_MODE_MIPS64 + CS_MODE_LITTLE_ENDIAN, MIPS_CODE2, "MIPS-64-EL (Little-endian)", None),
-        (CS_ARCH_MIPS, CS_MODE_MIPS32R6 + CS_MODE_MICRO + CS_MODE_BIG_ENDIAN, MIPS_32R6M, "MIPS-32R6 | Micro (Big-endian)", None),
-        (CS_ARCH_MIPS, CS_MODE_MIPS32R6 + CS_MODE_BIG_ENDIAN, MIPS_32R6, "MIPS-32R6 (Big-endian)", None),
-        (CS_ARCH_AARCH64, CS_MODE_ARM, AARCH64_CODE, "AARCH64", None),
-        (CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, PPC_CODE, "PPC-64", None),
-        (CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, PPC_CODE, "PPC-64, print register with number only", CS_OPT_SYNTAX_NOREGNAME),
-        (CS_ARCH_PPC, CS_MODE_BIG_ENDIAN + CS_MODE_QPX, PPC_CODE2, "PPC-64 + QPX", None),
-        (CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN, SPARC_CODE, "Sparc", None),
-        (CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN + CS_MODE_V9, SPARCV9_CODE, "SparcV9", None),
-        (CS_ARCH_SYSZ, 0, SYSZ_CODE, "SystemZ", None),
-        (CS_ARCH_XCORE, 0, XCORE_CODE, "XCore", None),
-        (CS_ARCH_M68K, CS_MODE_BIG_ENDIAN | CS_MODE_M68K_040, M68K_CODE, "M68K", None),
-        (CS_ARCH_TMS320C64X, 0, TMS320C64X_CODE, "TMS320C64x", None),
-        (CS_ARCH_M680X, CS_MODE_M680X_6809, M680X_CODE, "M680X_M6809", None),
-        (CS_ARCH_EVM, 0, EVM_CODE, "EVM", None),
-        (CS_ARCH_WASM, 0, WASM_CODE, "WASM", None),
-        (CS_ARCH_MOS65XX, 0, MOS65XX_CODE, "MOS65XX", None),
-        (CS_ARCH_BPF, CS_MODE_LITTLE_ENDIAN | CS_MODE_BPF_EXTENDED, EBPF_CODE, "eBPF", None),
-        (CS_ARCH_RISCV, CS_MODE_RISCV32, RISCV_CODE32, "RISCV32", None),
-        (CS_ARCH_RISCV, CS_MODE_RISCV64, RISCV_CODE64, "RISCV64", None),
-        (CS_ARCH_ALPHA, CS_MODE_LITTLE_ENDIAN, ALPHA_CODE, "Alpha (Little-endian)", None),
-        (CS_ARCH_ALPHA, CS_MODE_BIG_ENDIAN, ALPHA_CODE_BE, "Alpha (Big-endian)", None),
-        (CS_ARCH_HPPA, CS_MODE_BIG_ENDIAN | CS_MODE_HPPA_20, HPPA_20_CODE_BE, "HPPA 2.0 (Big-endian)", None),
-        (CS_ARCH_HPPA, CS_MODE_LITTLE_ENDIAN | CS_MODE_HPPA_20, HPPA_20_CODE, "HPPA 2.0 (Little-endian)", None),
-        (CS_ARCH_HPPA, CS_MODE_BIG_ENDIAN | CS_MODE_HPPA_11, HPPA_11_CODE_BE, "HPPA 1.1 (Big-endian)", None),
-        (CS_ARCH_HPPA, CS_MODE_LITTLE_ENDIAN | CS_MODE_HPPA_11, HPPA_11_CODE, "HPPA 1.1 (Little-endian)", None),
-)
-
-# ## Test cs_disasm_quick()
-def test_cs_disasm_quick():
-    for arch, mode, code, comment, syntax in all_tests:
-        print('*' * 40)
-        print("Platform: %s" % comment)
-        print("Disasm:")
-        print(to_hex(code))
-        for insn in cs_disasm_quick(arch, mode, code, 0x1000):
-            print("0x%x:\t%s\t%s" % (insn.address, insn.mnemonic, insn.op_str))
-        print()
-
-
-def test_different_data_formats():
-    data = bytes.fromhex('4831C948F7E1043B48BB0A2F62696E2F2F736852530A545F5257545E0F05')
-    mnemonics = ['xor', 'mul', 'add', 'movabs', 'push', 'pop', 'push', 'push', 'push', 'pop', 'syscall']
-    disassembler = Cs(CS_ARCH_X86, CS_MODE_64)
-    for name, code in (
-        ('bytearray', bytearray(data)),
-        ('memoryview of bytearray', memoryview(bytearray(data))),
-        ('memoryview of data', memoryview(data)),
-        ('raw data', data)
-    ):
-        if mnemonics != [op for  _, _, op, _ in disassembler.disasm_lite(code, 0)]:
-            print('failure in disassemble-lite for %s.' % name)
-        if mnemonics != [instruction.mnemonic for instruction in disassembler.disasm(code, 0)]:
-            print('failure in disassemble-full for %s.' % name)
-
-
-# ## Test class Cs
-def test_class():
-    for arch, mode, code, comment, syntax in all_tests:
-        print('*' * 16)
-        print("Platform: %s" % comment)
-        print("Code: %s" % to_hex(code))
-        print("Disasm:")
-
-        try:
-            md = Cs(arch, mode)
-
-            if syntax is not None:
-                md.syntax = syntax
-
-            for insn in md.disasm(code, 0x1000):
-                # bytes = binascii.hexlify(insn.bytes)
-                # print("0x%x:\t%s\t%s\t// hex-code: %s" %(insn.address, insn.mnemonic, insn.op_str, bytes))
-                print("0x%x:\t%s\t\t%s" % (insn.address, insn.mnemonic, insn.op_str))
-
-            print("0x%x:" % (insn.address + insn.size))
-            print()
-        except CsError as e:
-            print("ERROR: %s" % e)
-
-
-# test_cs_disasm_quick()
-# print ("*" * 40)
-if __name__ == '__main__':
-    test_class()
-    test_different_data_formats()
diff --git a/bindings/python/tests/test_bpf.py b/bindings/python/tests/test_bpf.py
deleted file mode 100755
index f7f5538a0..000000000
--- a/bindings/python/tests/test_bpf.py
+++ /dev/null
@@ -1,91 +0,0 @@
-#!/usr/bin/env python3
-
-# Capstone Python bindings
-# BPF tests by david942j <david942j@gmail.com>, 2019
-
-from capstone import *
-from capstone.bpf import *
-from xprint import to_hex, to_x, to_x_32
-
-
-CBPF_CODE = b"\x94\x09\x00\x00\x37\x13\x03\x00\x87\x00\x00\x00\x00\x00\x00\x00\x07\x00\x00\x00\x00\x00\x00\x00\x16\x00\x00\x00\x00\x00\x00\x00\x80\x00\x00\x00\x00\x00\x00\x00"
-EBPF_CODE = b"\x97\x09\x00\x00\x37\x13\x03\x00\xdc\x02\x00\x00\x20\x00\x00\x00\x30\x00\x00\x00\x00\x00\x00\x00\xdb\x3a\x00\x01\x00\x00\x00\x00\x84\x02\x00\x00\x00\x00\x00\x00\x6d\x33\x17\x02\x00\x00\x00\x00"
-
-all_tests = (
-        (CS_ARCH_BPF, CS_MODE_LITTLE_ENDIAN | CS_MODE_BPF_CLASSIC, CBPF_CODE, "cBPF Le", None),
-        (CS_ARCH_BPF, CS_MODE_LITTLE_ENDIAN | CS_MODE_BPF_EXTENDED, EBPF_CODE, "eBPF Le", None),
-        )
-
-ext_name = {}
-ext_name[BPF_EXT_LEN] = '#len'
-
-def print_insn_detail(insn):
-    # print address, mnemonic and operands
-    print("0x%x:\t%s\t%s" % (insn.address, insn.mnemonic, insn.op_str))
-
-    # "data" instruction generated by SKIPDATA option has no detail
-    if insn.id == 0:
-        return
-
-    if len(insn.groups) > 0:
-        print('\tGroups: ' + ' '.join(map(lambda g: insn.group_name(g), insn.groups)))
-
-    print("\tOperand count: %u" % len(insn.operands))
-    for c, op in enumerate(insn.operands):
-        print("\t\toperands[%u].type: " % c, end='')
-        if op.type == BPF_OP_REG:
-            print("REG = " + insn.reg_name(op.reg))
-        elif op.type == BPF_OP_IMM:
-            print("IMM = 0x" + to_x(op.imm))
-        elif op.type == BPF_OP_OFF:
-            print("OFF = +0x" + to_x_32(op.off))
-        elif op.type == BPF_OP_MEM:
-            print("MEM")
-            if op.mem.base != 0:
-                print("\t\t\toperands[%u].mem.base: REG = %s" \
-                    % (c, insn.reg_name(op.mem.base)))
-            print("\t\t\toperands[%u].mem.disp: 0x%s" \
-                % (c, to_x_32(op.mem.disp)))
-        elif op.type == BPF_OP_MMEM:
-            print("MMEM = 0x" + to_x_32(op.mmem))
-        elif op.type == BPF_OP_MSH:
-            print("MSH = 4*([0x%s]&0xf)" % to_x_32(op.msh))
-        elif op.type == BPF_OP_EXT:
-            print("EXT = " + ext_name[op.ext])
-
-    (regs_read, regs_write) = insn.regs_access()
-
-    if len(regs_read) > 0:
-        print("\tRegisters read:", end="")
-        for r in regs_read:
-            print(" %s" % insn.reg_name(r), end="")
-        print("")
-
-    if len(regs_write) > 0:
-        print("\tRegisters modified:", end="")
-        for r in regs_write:
-            print(" %s" % insn.reg_name(r), end="")
-        print("")
-
-def test_class():
-
-    for (arch, mode, code, comment, syntax) in all_tests:
-        print("*" * 16)
-        print("Platform: %s" % comment)
-        print("Code: %s" % to_hex(code))
-        print("Disasm:")
-
-        try:
-            md = Cs(arch, mode)
-            if syntax is not None:
-                md.syntax = syntax
-            md.detail = True
-            for insn in md.disasm(code, 0x0):
-                print_insn_detail(insn)
-                print ()
-        except CsError as e:
-            print("ERROR: %s" % e)
-
-
-if __name__ == '__main__':
-    test_class()
diff --git a/bindings/python/tests/test_detail.py b/bindings/python/tests/test_detail.py
deleted file mode 100755
index 4f966109f..000000000
--- a/bindings/python/tests/test_detail.py
+++ /dev/null
@@ -1,126 +0,0 @@
-#!/usr/bin/env python3
-
-# Capstone Python bindings, by Nguyen Anh Quynnh <aquynh@gmail.com>
-from capstone import *
-
-from xprint import to_hex
-
-X86_CODE16 = b"\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00"
-X86_CODE32 = b"\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00"
-X86_CODE64 = b"\x55\x48\x8b\x05\xb8\x13\x00\x00"
-ARM_CODE = b"\xED\xFF\xFF\xEB\x04\xe0\x2d\xe5\x00\x00\x00\x00\xe0\x83\x22\xe5\xf1\x02\x03\x0e\x00\x00\xa0\xe3\x02\x30\xc1\xe7\x00\x00\x53\xe3"
-ARM_CODE2 = b"\x10\xf1\x10\xe7\x11\xf2\x31\xe7\xdc\xa1\x2e\xf3\xe8\x4e\x62\xf3"
-THUMB_CODE = b"\x70\x47\xeb\x46\x83\xb0\xc9\x68"
-THUMB_CODE2 = b"\x4f\xf0\x00\x01\xbd\xe8\x00\x88\xd1\xe8\x00\xf0"
-THUMB_MCLASS = b"\xef\xf3\x02\x80"
-ARMV8 = b"\xe0\x3b\xb2\xee\x42\x00\x01\xe1\x51\xf0\x7f\xf5"
-MIPS_CODE = b"\x0C\x10\x00\x97\x00\x00\x00\x00\x24\x02\x00\x0c\x8f\xa2\x00\x00\x34\x21\x34\x56\x00\x80\x04\x08"
-MIPS_CODE2 = b"\x56\x34\x21\x34\xc2\x17\x01\x00"
-MIPS_32R6M = b"\x00\x07\x00\x07\x00\x11\x93\x7c\x01\x8c\x8b\x7c\x00\xc7\x48\xd0"
-MIPS_32R6 = b"\xec\x80\x00\x19\x7c\x43\x22\xa0"
-AARCH64_CODE = b"\x09\x00\x38\xd5\xbf\x40\x00\xd5\x0c\x05\x13\xd5\x20\x50\x02\x0e\x20\xe4\x3d\x0f\x00\x18\xa0\x5f\xa2\x00\xae\x9e\x9f\x37\x03\xd5\xbf\x33\x03\xd5\xdf\x3f\x03\xd5\x21\x7c\x02\x9b\x21\x7c\x00\x53\x00\x40\x21\x4b\xe1\x0b\x40\xb9\x20\x04\x81\xda\x20\x08\x02\x8b\x10\x5b\xe8\x3c"
-PPC_CODE = b"\x80\x20\x00\x00\x80\x3f\x00\x00\x10\x43\x23\x0e\xd0\x44\x00\x80\x4c\x43\x22\x02\x2d\x03\x00\x80\x7c\x43\x20\x14\x7c\x43\x20\x93\x4f\x20\x00\x21\x4c\xc8\x00\x21\x40\x82\x00\x14"
-PPC_CODE2 = b"\x10\x60\x2a\x10\x10\x64\x28\x88\x7c\x4a\x5d\x0f"
-SPARC_CODE = b"\x80\xa0\x40\x02\x85\xc2\x60\x08\x85\xe8\x20\x01\x81\xe8\x00\x00\x90\x10\x20\x01\xd5\xf6\x10\x16\x21\x00\x00\x0a\x86\x00\x40\x02\x01\x00\x00\x00\x12\xbf\xff\xff\x10\xbf\xff\xff\xa0\x02\x00\x09\x0d\xbf\xff\xff\xd4\x20\x60\x00\xd4\x4e\x00\x16\x2a\xc2\x80\x03"
-SPARCV9_CODE = b"\x81\xa8\x0a\x24\x89\xa0\x10\x20\x89\xa0\x1a\x60\x89\xa0\x00\xe0"
-SYSZ_CODE = b"\xed\x00\x00\x00\x00\x1a\x5a\x0f\x1f\xff\xc2\x09\x80\x00\x00\x00\x07\xf7\xeb\x2a\xff\xff\x7f\x57\xe3\x01\xff\xff\x7f\x57\xeb\x00\xf0\x00\x00\x24\xb2\x4f\x00\x78"
-XCORE_CODE = b"\xfe\x0f\xfe\x17\x13\x17\xc6\xfe\xec\x17\x97\xf8\xec\x4f\x1f\xfd\xec\x37\x07\xf2\x45\x5b\xf9\xfa\x02\x06\x1b\x10"
-M68K_CODE = b"\xd4\x40\x87\x5a\x4e\x71\x02\xb4\xc0\xde\xc0\xde\x5c\x00\x1d\x80\x71\x12\x01\x23\xf2\x3c\x44\x22\x40\x49\x0e\x56\x54\xc5\xf2\x3c\x44\x00\x44\x7a\x00\x00\xf2\x00\x0a\x28\x4E\xB9\x00\x00\x00\x12\x4E\x75"
-M680X_CODE = b"\x06\x10\x19\x1a\x55\x1e\x01\x23\xe9\x31\x06\x34\x55\xa6\x81\xa7\x89\x7f\xff\xa6\x9d\x10\x00\xa7\x91\xa6\x9f\x10\x00\x11\xac\x99\x10\x00\x39"
-MOS65XX_CODE = b"\x0A\x00\xFE\x34\x12\xD0\xFF\xEA\x19\x56\x34\x46\x80"
-EBPF_CODE = b"\x97\x09\x00\x00\x37\x13\x03\x00\xdc\x02\x00\x00\x20\x00\x00\x00\x30\x00\x00\x00\x00\x00\x00\x00\xdb\x3a\x00\x01\x00\x00\x00\x00\x84\x02\x00\x00\x00\x00\x00\x00\x6d\x33\x17\x02\x00\x00\x00\x00"
-ALPHA_CODE = b'\x02\x00\xbb\x27\x50\x7a\xbd\x23\xd0\xff\xde\x23\x00\x00\x5e\xb7'
-ALPHA_CODE_BE = b'\x27\xbb\x00\x02\x23\xbd\x7a\x50\x23\xde\xff\xd0\xb7\x5e\x00\x00'
-HPPA_20_CODE_BE = b'\x00\x20\x50\xa2\x00\x01\x58\x20\x00\x00\x44\xa1\x00\x41\x18\x40\x00\x20\x08\xa2\x01\x60\x48\xa1\x01\x61\x18\xc0\x00\x00\x14\xa1\x00\x0f\x0d\x61\x00\x0f\x0e\x61\x00\x01\x18\x60\x00\x00\x0c\x00\x00\x00\x0c\xa0\x03\xff\xc0\x1f\x00\x00\x04\x00\x00\x10\x04\x00\x04\x22\x51\x83\x04\x22\x51\xc3\x04\x22\x51\x83\x04\x2f\x71\x83\x04\x2f\x71\xc3\x04\x2f\x71\x83\x04\x41\x53\x43\x04\x41\x53\x63\x04\x41\x53\x03\x04\x41\x12\x00\x04\x41\x16\x00\x04\x41\x16\x20\x04\x41\x42\x00\x04\x41\x46\x00\x04\x41\x46\x20\x04\x41\x12\x40\x04\x41\x12\x60\x04\x41\x42\x40\x04\x41\x42\x60\x04\x41\x18\x00\x04\x41\x08\x00\x04\x41\x13\x80\x04\x41\x13\xa0\x04\x41\x52\x80\x04\x41\x52\xa0\x04\x5e\x72\x80\x04\x41\x42\x80\x04\x41\x52\xc0\x04\x41\x52\xe0\x04\x41\x42\xc0\x04\x41\x42\xe0\x14\x00\xde\xad'
-HPPA_20_CODE =    b'\xa2\x50\x20\x00\x20\x58\x01\x00\xa1\x44\x00\x00\x40\x18\x41\x00\xa2\x08\x20\x00\xa1\x48\x60\x01\xc0\x18\x61\x01\xa1\x14\x00\x00\x61\x0d\x0f\x00\x61\x0e\x0f\x00\x60\x18\x01\x00\x00\x0c\x00\x00\xa0\x0c\x00\x00\x1f\xc0\xff\x03\x00\x04\x00\x00\x00\x04\x10\x00\x83\x51\x22\x04\xc3\x51\x22\x04\x83\x51\x22\x04\x83\x71\x2f\x04\xc3\x71\x2f\x04\x83\x71\x2f\x04\x43\x53\x41\x04\x63\x53\x41\x04\x03\x53\x41\x04\x00\x12\x41\x04\x00\x16\x41\x04\x20\x16\x41\x04\x00\x42\x41\x04\x00\x46\x41\x04\x20\x46\x41\x04\x40\x12\x41\x04\x60\x12\x41\x04\x40\x42\x41\x04\x60\x42\x41\x04\x00\x18\x41\x04\x00\x08\x41\x04\x80\x13\x41\x04\xa0\x13\x41\x04\x80\x52\x41\x04\xa0\x52\x41\x04\x80\x72\x5e\x04\x80\x42\x41\x04\xc0\x52\x41\x04\xe0\x52\x41\x04\xc0\x42\x41\x04\xe0\x42\x41\x04\xad\xde\x00\x14'
-HPPA_11_CODE_BE = b'\x24\x41\x40\xc3\x24\x41\x60\xc3\x24\x41\x40\xe3\x24\x41\x60\xe3\x24\x41\x68\xe3\x2c\x41\x40\xc3\x2c\x41\x60\xc3\x2c\x41\x40\xe3\x2c\x41\x60\xe3\x2c\x41\x68\xe3\x24\x62\x42\xc1\x24\x62\x62\xc1\x24\x62\x42\xe1\x24\x62\x46\xe1\x24\x62\x62\xe1\x24\x62\x6a\xe1\x2c\x62\x42\xc1\x2c\x62\x62\xc1\x2c\x62\x42\xe1\x2c\x62\x46\xe1\x2c\x62\x62\xe1\x2c\x62\x6a\xe1\x24\x3e\x50\xc2\x24\x3e\x50\xe2\x24\x3e\x70\xe2\x24\x3e\x78\xe2\x2c\x3e\x50\xc2\x2c\x3e\x50\xe2\x2c\x3e\x70\xe2\x2c\x3e\x78\xe2\x24\x5e\x52\xc1\x24\x5e\x52\xe1\x24\x5e\x56\xe1\x24\x5e\x72\xe1\x24\x5e\x7a\xe1\x2c\x5e\x52\xc1\x2c\x5e\x52\xe1\x2c\x5e\x56\xe1\x2c\x5e\x72\xe1\x2c\x5e\x7a\xe1'
-HPPA_11_CODE =    b'\xc3\x40\x41\x24\xc3\x60\x41\x24\xe3\x40\x41\x24\xe3\x60\x41\x24\xe3\x68\x41\x24\xc3\x40\x41\x2c\xc3\x60\x41\x2c\xe3\x40\x41\x2c\xe3\x60\x41\x2c\xe3\x68\x41\x2c\xc1\x42\x62\x24\xc1\x62\x62\x24\xe1\x42\x62\x24\xe1\x46\x62\x24\xe1\x62\x62\x24\xe1\x6a\x62\x24\xc1\x42\x62\x2c\xc1\x62\x62\x2c\xe1\x42\x62\x2c\xe1\x46\x62\x2c\xe1\x62\x62\x2c\xe1\x6a\x62\x2c\xc2\x50\x3e\x24\xe2\x50\x3e\x24\xe2\x70\x3e\x24\xe2\x78\x3e\x24\xc2\x50\x3e\x2c\xe2\x50\x3e\x2c\xe2\x70\x3e\x2c\xe2\x78\x3e\x2c\xc1\x52\x5e\x24\xe1\x52\x5e\x24\xe1\x56\x5e\x24\xe1\x72\x5e\x24\xe1\x7a\x5e\x24\xc1\x52\x5e\x2c\xe1\x52\x5e\x2c\xe1\x56\x5e\x2c\xe1\x72\x5e\x2c\xe1\x7a\x5e\x2c'
-
-all_tests = (
-        (CS_ARCH_X86, CS_MODE_16, X86_CODE16, "X86 16bit (Intel syntax)", None),
-        (CS_ARCH_X86, CS_MODE_32, X86_CODE32, "X86 32bit (ATT syntax)", CS_OPT_SYNTAX_ATT),
-        (CS_ARCH_X86, CS_MODE_32, X86_CODE32, "X86 32 (Intel syntax)", None),
-        (CS_ARCH_X86, CS_MODE_64, X86_CODE64, "X86 64 (Intel syntax)", None),
-        (CS_ARCH_ARM, CS_MODE_ARM, ARM_CODE, "ARM", None),
-        (CS_ARCH_ARM, CS_MODE_ARM, ARM_CODE2, "ARM: Cortex-A15 + NEON", None),
-        (CS_ARCH_ARM, CS_MODE_THUMB, THUMB_CODE, "THUMB", None),
-        (CS_ARCH_ARM, CS_MODE_THUMB, THUMB_CODE2, "THUMB-2", None),
-        (CS_ARCH_ARM, CS_MODE_THUMB + CS_MODE_MCLASS, THUMB_MCLASS, "Thumb-MClass", None),
-        (CS_ARCH_ARM, CS_MODE_ARM + CS_MODE_V8, ARMV8, "Arm-V8", None),
-        (CS_ARCH_AARCH64, CS_MODE_ARM, AARCH64_CODE, "AARCH64", None),
-        (CS_ARCH_MIPS, CS_MODE_MIPS32 + CS_MODE_BIG_ENDIAN, MIPS_CODE, "MIPS-32 (Big-endian)", None),
-        (CS_ARCH_MIPS, CS_MODE_MIPS64 + CS_MODE_LITTLE_ENDIAN, MIPS_CODE2, "MIPS-64-EL (Little-endian)", None),
-        (CS_ARCH_MIPS, CS_MODE_MIPS32R6 + CS_MODE_MICRO + CS_MODE_BIG_ENDIAN, MIPS_32R6M, "MIPS-32R6 | Micro (Big-endian)", None),
-        (CS_ARCH_MIPS, CS_MODE_MIPS32R6 + CS_MODE_BIG_ENDIAN, MIPS_32R6, "MIPS-32R6 (Big-endian)", None),
-        (CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, PPC_CODE, "PPC-64", None),
-        (CS_ARCH_PPC, CS_MODE_BIG_ENDIAN + CS_MODE_QPX, PPC_CODE2, "PPC-64 + QPX", None),
-        (CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN, SPARC_CODE, "Sparc", None),
-        (CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN + CS_MODE_V9, SPARCV9_CODE, "SparcV9", None),
-        (CS_ARCH_SYSZ, 0, SYSZ_CODE, "SystemZ", None),
-        (CS_ARCH_XCORE, 0, XCORE_CODE, "XCore", None),
-        (CS_ARCH_M68K, CS_MODE_BIG_ENDIAN | CS_MODE_M68K_040, M68K_CODE, "M68K", None),
-        (CS_ARCH_M680X, CS_MODE_M680X_6809, M680X_CODE, "M680X_M6809", None),
-        (CS_ARCH_MOS65XX, 0, MOS65XX_CODE, "MOS65XX", None),
-        (CS_ARCH_BPF, CS_MODE_LITTLE_ENDIAN | CS_MODE_BPF_EXTENDED, EBPF_CODE, "eBPF", None),
-        (CS_ARCH_ALPHA, CS_MODE_LITTLE_ENDIAN, ALPHA_CODE, "Alpha (Little-endian)", None),
-        (CS_ARCH_ALPHA, CS_MODE_BIG_ENDIAN, ALPHA_CODE_BE, "Alpha (Big-endian)", None),
-        (CS_ARCH_HPPA, CS_MODE_BIG_ENDIAN | CS_MODE_HPPA_20, HPPA_20_CODE_BE, "HPPA 2.0 (Big-endian)", None),
-        (CS_ARCH_HPPA, CS_MODE_LITTLE_ENDIAN | CS_MODE_HPPA_20, HPPA_20_CODE, "HPPA 2.0 (Little-endian)", None),
-        (CS_ARCH_HPPA, CS_MODE_BIG_ENDIAN | CS_MODE_HPPA_11, HPPA_11_CODE_BE, "HPPA 1.1 (Big-endian)", None),
-        (CS_ARCH_HPPA, CS_MODE_LITTLE_ENDIAN | CS_MODE_HPPA_11, HPPA_11_CODE, "HPPA 1.1 (Little-endian)", None),
-)
-
-
-def print_detail(insn):
-    print("0x%x:\t%s\t%s  // insn-ID: %u, insn-mnem: %s" \
-        % (insn.address, insn.mnemonic, insn.op_str, insn.id, \
-        insn.insn_name()))
-
-    # "data" instruction generated by SKIPDATA option has no detail
-    if insn.id == 0:
-        return
-
-    if len(insn.regs_read) > 0:
-        print("\tImplicit registers read: ", end='')
-        for m in insn.regs_read:
-            print("%s " % insn.reg_name(m), end='')
-        print()
-
-    if len(insn.regs_write) > 0:
-        print("\tImplicit registers modified: ", end='')
-        for m in insn.regs_write:
-            print("%s " % insn.reg_name(m), end='')
-        print()
-
-    if len(insn.groups) > 0:
-        print("\tThis instruction belongs to groups: ", end='')
-        for m in insn.groups:
-            print("%s " % insn.group_name(m), end='')
-        print()
-
-
-# ## Test class Cs
-def test_class():
-    for (arch, mode, code, comment, syntax) in all_tests:
-        print('*' * 16)
-        print("Platform: %s" % comment)
-        print("Code: %s" % to_hex(code))
-        print("Disasm:")
-
-        try:
-            md = Cs(arch, mode)
-            md.detail = True
-
-            if syntax is not None:
-                md.syntax = syntax
-
-            for insn in md.disasm(code, 0x1000):
-                print_detail(insn)
-
-            print("0x%x:" % (insn.address + insn.size))
-            print()
-        except CsError as e:
-            print("ERROR: %s" % e)
-
-if __name__ == '__main__':
-    test_class()
diff --git a/bindings/python/tests/test_evm.py b/bindings/python/tests/test_evm.py
deleted file mode 100755
index 3fd90fdfc..000000000
--- a/bindings/python/tests/test_evm.py
+++ /dev/null
@@ -1,48 +0,0 @@
-#!/usr/bin/env python3
-
-# Capstone Python bindings, by Nguyen Anh Quynnh <aquynh@gmail.com>
-
-from capstone import *
-
-from xprint import to_hex
-
-
-EVM_CODE = b"\x60\x61\x50"
-
-all_tests = (
-        (CS_ARCH_EVM, 0, EVM_CODE, "EVM"),
-)
-
-
-def test_class():
-    address = 0x80001000
-    for (arch, mode, code, comment) in all_tests:
-        print("*" * 16)
-        print("Platform: %s" % comment)
-        print("Code: %s " % to_hex(code))
-        print("Disasm:")
-
-        try:
-            md = Cs(arch, mode)
-            md.detail = True
-            for i in md.disasm(code, address):
-                print("0x%x:\t%s\t%s" %(i.address, i.mnemonic, i.op_str))
-                if i.pop > 0:
-                    print("\tPop:     %u" %i.pop)
-                if i.push > 0:
-                    print("\tPush:    %u" %i.push)
-                if i.fee > 0:
-                    print("\tGas fee: %u" %i.fee)
-                if len(i.groups) > 0:
-                    print("\tGroups: ", end=''),
-                    for m in i.groups:
-                        print("%s " % i.group_name(m), end=''),
-                    print()
-            print ("0x%x:\n" % (i.address + i.size))
-
-        except CsError as e:
-            print("ERROR: %s" % e.__str__())
-
-
-if __name__ == '__main__':
-    test_class()
diff --git a/bindings/python/tests/test_hppa.py b/bindings/python/tests/test_hppa.py
deleted file mode 100755
index dfbe08fa3..000000000
--- a/bindings/python/tests/test_hppa.py
+++ /dev/null
@@ -1,74 +0,0 @@
-#!/usr/bin/env python3
-
-# Capstone Python bindings, by Dmitry Sibirtsev <sibirtsev_dl@gmail.com>
-
-from capstone import *
-from capstone.hppa import *
-from xprint import to_x, to_hex
-
-HPPA_20_CODE_BE = b'\x00\x20\x50\xa2\x00\x01\x58\x20\x00\x00\x44\xa1\x00\x41\x18\x40\x00\x20\x08\xa2\x01\x60\x48\xa1\x01\x61\x18\xc0\x00\x00\x14\xa1\x00\x0f\x0d\x61\x00\x0f\x0e\x61\x00\x01\x18\x60\x00\x00\x0c\x00\x00\x00\x0c\xa0\x03\xff\xc0\x1f\x00\x00\x04\x00\x00\x10\x04\x00\x04\x22\x51\x83\x04\x22\x51\xc3\x04\x22\x51\x83\x04\x2f\x71\x83\x04\x2f\x71\xc3\x04\x2f\x71\x83\x04\x41\x53\x43\x04\x41\x53\x63\x04\x41\x53\x03\x04\x41\x12\x00\x04\x41\x16\x00\x04\x41\x16\x20\x04\x41\x42\x00\x04\x41\x46\x00\x04\x41\x46\x20\x04\x41\x12\x40\x04\x41\x12\x60\x04\x41\x42\x40\x04\x41\x42\x60\x04\x41\x18\x00\x04\x41\x08\x00\x04\x41\x13\x80\x04\x41\x13\xa0\x04\x41\x52\x80\x04\x41\x52\xa0\x04\x5e\x72\x80\x04\x41\x42\x80\x04\x41\x52\xc0\x04\x41\x52\xe0\x04\x41\x42\xc0\x04\x41\x42\xe0\x14\x00\xde\xad'
-HPPA_20_CODE =    b'\xa2\x50\x20\x00\x20\x58\x01\x00\xa1\x44\x00\x00\x40\x18\x41\x00\xa2\x08\x20\x00\xa1\x48\x60\x01\xc0\x18\x61\x01\xa1\x14\x00\x00\x61\x0d\x0f\x00\x61\x0e\x0f\x00\x60\x18\x01\x00\x00\x0c\x00\x00\xa0\x0c\x00\x00\x1f\xc0\xff\x03\x00\x04\x00\x00\x00\x04\x10\x00\x83\x51\x22\x04\xc3\x51\x22\x04\x83\x51\x22\x04\x83\x71\x2f\x04\xc3\x71\x2f\x04\x83\x71\x2f\x04\x43\x53\x41\x04\x63\x53\x41\x04\x03\x53\x41\x04\x00\x12\x41\x04\x00\x16\x41\x04\x20\x16\x41\x04\x00\x42\x41\x04\x00\x46\x41\x04\x20\x46\x41\x04\x40\x12\x41\x04\x60\x12\x41\x04\x40\x42\x41\x04\x60\x42\x41\x04\x00\x18\x41\x04\x00\x08\x41\x04\x80\x13\x41\x04\xa0\x13\x41\x04\x80\x52\x41\x04\xa0\x52\x41\x04\x80\x72\x5e\x04\x80\x42\x41\x04\xc0\x52\x41\x04\xe0\x52\x41\x04\xc0\x42\x41\x04\xe0\x42\x41\x04\xad\xde\x00\x14'
-HPPA_11_CODE_BE = b'\x24\x41\x40\xc3\x24\x41\x60\xc3\x24\x41\x40\xe3\x24\x41\x60\xe3\x24\x41\x68\xe3\x2c\x41\x40\xc3\x2c\x41\x60\xc3\x2c\x41\x40\xe3\x2c\x41\x60\xe3\x2c\x41\x68\xe3\x24\x62\x42\xc1\x24\x62\x62\xc1\x24\x62\x42\xe1\x24\x62\x46\xe1\x24\x62\x62\xe1\x24\x62\x6a\xe1\x2c\x62\x42\xc1\x2c\x62\x62\xc1\x2c\x62\x42\xe1\x2c\x62\x46\xe1\x2c\x62\x62\xe1\x2c\x62\x6a\xe1\x24\x3e\x50\xc2\x24\x3e\x50\xe2\x24\x3e\x70\xe2\x24\x3e\x78\xe2\x2c\x3e\x50\xc2\x2c\x3e\x50\xe2\x2c\x3e\x70\xe2\x2c\x3e\x78\xe2\x24\x5e\x52\xc1\x24\x5e\x52\xe1\x24\x5e\x56\xe1\x24\x5e\x72\xe1\x24\x5e\x7a\xe1\x2c\x5e\x52\xc1\x2c\x5e\x52\xe1\x2c\x5e\x56\xe1\x2c\x5e\x72\xe1\x2c\x5e\x7a\xe1'
-HPPA_11_CODE =    b'\xc3\x40\x41\x24\xc3\x60\x41\x24\xe3\x40\x41\x24\xe3\x60\x41\x24\xe3\x68\x41\x24\xc3\x40\x41\x2c\xc3\x60\x41\x2c\xe3\x40\x41\x2c\xe3\x60\x41\x2c\xe3\x68\x41\x2c\xc1\x42\x62\x24\xc1\x62\x62\x24\xe1\x42\x62\x24\xe1\x46\x62\x24\xe1\x62\x62\x24\xe1\x6a\x62\x24\xc1\x42\x62\x2c\xc1\x62\x62\x2c\xe1\x42\x62\x2c\xe1\x46\x62\x2c\xe1\x62\x62\x2c\xe1\x6a\x62\x2c\xc2\x50\x3e\x24\xe2\x50\x3e\x24\xe2\x70\x3e\x24\xe2\x78\x3e\x24\xc2\x50\x3e\x2c\xe2\x50\x3e\x2c\xe2\x70\x3e\x2c\xe2\x78\x3e\x2c\xc1\x52\x5e\x24\xe1\x52\x5e\x24\xe1\x56\x5e\x24\xe1\x72\x5e\x24\xe1\x7a\x5e\x24\xc1\x52\x5e\x2c\xe1\x52\x5e\x2c\xe1\x56\x5e\x2c\xe1\x72\x5e\x2c\xe1\x7a\x5e\x2c'
-
-all_tests = (
-    (CS_ARCH_HPPA, CS_MODE_BIG_ENDIAN | CS_MODE_HPPA_20, HPPA_20_CODE_BE, "HPPA 2.0 (Big-endian)"),
-    (CS_ARCH_HPPA, CS_MODE_LITTLE_ENDIAN | CS_MODE_HPPA_20, HPPA_20_CODE, "HPPA 2.0 (Little-endian)"),
-    (CS_ARCH_HPPA, CS_MODE_BIG_ENDIAN | CS_MODE_HPPA_11, HPPA_11_CODE_BE, "HPPA 1.1 (Big-endian)"),
-    (CS_ARCH_HPPA, CS_MODE_LITTLE_ENDIAN | CS_MODE_HPPA_11, HPPA_11_CODE, "HPPA 1.1 (Little-endian)"),
-)
-
-
-def print_insn_detail(insn):
-    # print address, mnemonic and operands
-    print("0x%x:\t%s\t%s" % (insn.address, insn.mnemonic, insn.op_str))
-
-    # "data" instruction generated by SKIPDATA option has no detail
-    if insn.id == 0:
-        return
-
-    if len(insn.operands) > 0:
-        print("\top_count: %u" % len(insn.operands))
-        c = 0
-        for i in insn.operands:
-            if i.type == HPPA_OP_REG:
-                print("\t\toperands[%u].type: REG = %s" % (c, insn.reg_name(i.reg)))
-            if i.type == HPPA_OP_IMM:
-                print("\t\toperands[%u].type: IMM = 0x%s" % (c, to_x(i.imm)))
-            if i.type == HPPA_OP_IDX_REG:
-                print("\t\toperands[%u].type: IDX_REG = %s" % (c, insn.reg_name(i.reg)))
-            if i.type == HPPA_OP_DISP:
-                print("\t\toperands[%u].type: DISP = 0x%s" % (c, to_x(i.imm)))
-            if i.type == HPPA_OP_MEM:
-                print("\t\toperands[%u].type: MEM" % c)
-                if i.mem.space != HPPA_REG_INVALID:
-                    print("\t\t\toperands[%u].mem.space: REG = %s" % (c, insn.reg_name(i.mem.space)))
-                print("\t\t\toperands[%u].mem.base: REG = %s" % (c, insn.reg_name(i.mem.base)))
-            if i.type == HPPA_OP_TARGET:
-                if i.imm >= 0x8000000000000000:
-                    print("TARGET = -0x%lx" % i.imm)
-                else:
-                    print("TARGET = 0x%lx" % i.imm)
-            c += 1
-
-# ## Test class Cs
-def test_class():
-    for (arch, mode, code, comment) in all_tests:
-        print("*" * 16)
-        print("Platform: %s" % comment)
-        print("Code: %s" % to_hex(code))
-        print("Disasm:")
-
-        try:
-            md = Cs(arch, mode)
-            md.detail = True
-            for insn in md.disasm(code, 0x1000):
-                print_insn_detail(insn)
-                print()
-            print("0x%x:\n" % (insn.address + insn.size))
-        except CsError as e:
-            print("ERROR: %s" % e)
-
-
-if __name__ == '__main__':
-    test_class()
diff --git a/bindings/python/tests/test_m680x.py b/bindings/python/tests/test_m680x.py
deleted file mode 100755
index 8512ff0cc..000000000
--- a/bindings/python/tests/test_m680x.py
+++ /dev/null
@@ -1,153 +0,0 @@
-#!/usr/bin/env python3
-
-# Capstone Python bindings, by Wolfgang Schwotzer <wolfgang.schwotzer@gmx.net>
-
-from capstone import *
-from capstone.m680x import *
-
-
-s_access = (
-	"UNCHANGED", "READ", "WRITE", "READ | WRITE",
-	)
-
-M6800_CODE = b"\x01\x09\x36\x64\x7f\x74\x10\x00\x90\x10\xA4\x10\xb6\x10\x00\x39"
-
-M6801_CODE = b"\x04\x05\x3c\x3d\x38\x93\x10\xec\x10\xed\x10\x39"
-M6805_CODE = b"\x04\x7f\x00\x17\x22\x28\x00\x2e\x00\x40\x42\x5a\x70\x8e\x97\x9c\xa0\x15\xad\x00\xc3\x10\x00\xda\x12\x34\xe5\x7f\xfe"
-M6808_CODE = b"\x31\x22\x00\x35\x22\x45\x10\x00\x4b\x00\x51\x10\x52\x5e\x22\x62\x65\x12\x34\x72\x84\x85\x86\x87\x8a\x8b\x8c\x94\x95\xa7\x10\xaf\x10\x9e\x60\x7f\x9e\x6b\x7f\x00\x9e\xd6\x10\x00\x9e\xe6\x7f"
-HCS08_CODE = b"\x32\x10\x00\x9e\xae\x9e\xce\x7f\x9e\xbe\x10\x00\x9e\xfe\x7f\x3e\x10\x00\x9e\xf3\x7f\x96\x10\x00\x9e\xff\x7f\x82"
-HD6301_CODE = b"\x6b\x10\x00\x71\x10\x00\x72\x10\x10\x39"
-M6809_CODE = b"\x06\x10\x19\x1a\x55\x1e\x01\x23\xe9\x31\x06\x34\x55\xa6\x81\xa7\x89\x7f\xff\xa6\x9d\x10\x00\xa7\x91\xa6\x9f\x10\x00\x11\xac\x99\x10\x00\x39\xA6\x07\xA6\x27\xA6\x47\xA6\x67\xA6\x0F\xA6\x10\xA6\x80\xA6\x81\xA6\x82\xA6\x83\xA6\x84\xA6\x85\xA6\x86\xA6\x88\x7F\xA6\x88\x80\xA6\x89\x7F\xFF\xA6\x89\x80\x00\xA6\x8B\xA6\x8C\x10\xA6\x8D\x10\x00\xA6\x91\xA6\x93\xA6\x94\xA6\x95\xA6\x96\xA6\x98\x7F\xA6\x98\x80\xA6\x99\x7F\xFF\xA6\x99\x80\x00\xA6\x9B\xA6\x9C\x10\xA6\x9D\x10\x00\xA6\x9F\x10\x00"
-M6811_CODE = b"\x02\x03\x12\x7f\x10\x00\x13\x99\x08\x00\x14\x7f\x02\x15\x7f\x01\x1e\x7f\x20\x00\x8f\xcf\x18\x08\x18\x30\x18\x3c\x18\x67\x18\x8c\x10\x00\x18\x8f\x18\xce\x10\x00\x18\xff\x10\x00\x1a\xa3\x7f\x1a\xac\x1a\xee\x7f\x1a\xef\x7f\xcd\xac\x7f"
-CPU12_CODE = b"\x00\x04\x01\x00\x0c\x00\x80\x0e\x00\x80\x00\x11\x1e\x10\x00\x80\x00\x3b\x4a\x10\x00\x04\x4b\x01\x04\x4f\x7f\x80\x00\x8f\x10\x00\xb7\x52\xb7\xb1\xa6\x67\xa6\xfe\xa6\xf7\x18\x02\xe2\x30\x39\xe2\x10\x00\x18\x0c\x30\x39\x10\x00\x18\x11\x18\x12\x10\x00\x18\x19\x00\x18\x1e\x00\x18\x3e\x18\x3f\x00"
-HD6309_CODE = b"\x01\x10\x10\x62\x10\x10\x7b\x10\x10\x00\xcd\x49\x96\x02\xd2\x10\x30\x23\x10\x38\x10\x3b\x10\x53\x10\x5d\x11\x30\x43\x10\x11\x37\x25\x10\x11\x38\x12\x11\x39\x23\x11\x3b\x34\x11\x8e\x10\x00\x11\xaf\x10\x11\xab\x10\x11\xf6\x80\x00"
-
-all_tests = (
-        (CS_ARCH_M680X, CS_MODE_M680X_6301, HD6301_CODE, "M680X_HD6301", None),
-        (CS_ARCH_M680X, CS_MODE_M680X_6309, HD6309_CODE, "M680X_HD6309", None),
-        (CS_ARCH_M680X, CS_MODE_M680X_6800, M6800_CODE, "M680X_M6800", None),
-        (CS_ARCH_M680X, CS_MODE_M680X_6801, M6801_CODE, "M680X_M6801", None),
-        (CS_ARCH_M680X, CS_MODE_M680X_6805, M6805_CODE, "M680X_M68HC05", None),
-        (CS_ARCH_M680X, CS_MODE_M680X_6808, M6808_CODE, "M680X_M68HC08", None),
-        (CS_ARCH_M680X, CS_MODE_M680X_6809, M6809_CODE, "M680X_M6809", None),
-        (CS_ARCH_M680X, CS_MODE_M680X_6811, M6811_CODE, "M680X_M68HC11", None),
-        (CS_ARCH_M680X, CS_MODE_M680X_CPU12, CPU12_CODE, "M680X_CPU12", None),
-        (CS_ARCH_M680X, CS_MODE_M680X_HCS08, HCS08_CODE, "M680X_HCS08", None),
-        )
-
-# print hex dump from string all upper case
-def to_hex_uc(string):
-    return " ".join("0x%02x" % c for c in string)
-
-# print short hex dump from byte array all upper case
-def to_hex_short_uc(byte_array):
-    return "".join("%02x" % b for b in byte_array)
-
-def print_insn_detail(insn):
-    # print address, mnemonic and operands
-    #print("0x%x:\t%s\t%s\t%s" % (insn.address, binascii.hexlify(bytearray(insn.bytes)), \
-    print("0x%04x: %s\t%s\t%s" % (insn.address, to_hex_short_uc(insn.bytes), \
-	insn.mnemonic, insn.op_str))
-
-    # "data" instruction generated by SKIPDATA option has no detail
-    if insn.id == 0:
-        return
-
-    if len(insn.operands) > 0:
-        print("\top_count: %u" % len(insn.operands))
-        c = 0
-        for i in insn.operands:
-            if i.type == M680X_OP_REGISTER:
-                comment = "";
-                if (((c == 0) and (insn.flags & M680X_FIRST_OP_IN_MNEM)) or
-                    ((c == 1) and (insn.flags & M680X_SECOND_OP_IN_MNEM))):
-                    comment = " (in mnemonic)";
-                print("\t\toperands[%u].type: REGISTER = %s%s" % (c,
-                    insn.reg_name(i.reg), comment))
-            if i.type == M680X_OP_CONSTANT:
-                print("\t\toperands[%u].type: CONSTANT = %u" % (c, i.const_val))
-            if i.type == M680X_OP_IMMEDIATE:
-                print("\t\toperands[%u].type: IMMEDIATE = #%d" % (c, i.imm))
-            if i.type == M680X_OP_DIRECT:
-                print("\t\toperands[%u].type: DIRECT = 0x%02x" % (c, i.direct_addr))
-            if i.type == M680X_OP_EXTENDED:
-                if i.ext.indirect:
-                    indirect = "INDIRECT"
-                else:
-                    indirect = ""
-                print("\t\toperands[%u].type: EXTENDED %s = 0x%04x" % (c, indirect, i.ext.address))
-            if i.type == M680X_OP_RELATIVE:
-                print("\t\toperands[%u].type: RELATIVE = 0x%04x" % (c, i.rel.address))
-            if i.type == M680X_OP_INDEXED:
-                if (i.idx.flags & M680X_IDX_INDIRECT):
-                    indirect = " INDIRECT"
-                else:
-                    indirect = ""
-                print("\t\toperands[%u].type: INDEXED%s" % (c, indirect))
-                if i.idx.base_reg != M680X_REG_INVALID:
-                    print("\t\t\tbase register: %s" % insn.reg_name(i.idx.base_reg))
-                if i.idx.offset_reg != M680X_REG_INVALID:
-                    print("\t\t\toffset register: %s" % insn.reg_name(i.idx.offset_reg))
-                if (i.idx.offset_bits != 0) and (i.idx.offset_reg == M680X_REG_INVALID) and (i.idx.inc_dec == 0):
-                    print("\t\t\toffset: %u" % i.idx.offset)
-                    if i.idx.base_reg == M680X_REG_PC:
-                        print("\t\t\toffset address: 0x%04x" % i.idx.offset_addr)
-                    print("\t\t\toffset bits: %u" % i.idx.offset_bits)
-                if i.idx.inc_dec != 0:
-                    if i.idx.flags & M680X_IDX_POST_INC_DEC:
-                       s_post_pre = "post"
-                    else:
-                       s_post_pre = "pre"
-                    if i.idx.inc_dec > 0:
-                        s_inc_dec = "increment"
-                    else:
-                        s_inc_dec = "decrement"
-                    print("\t\t\t%s %s: %d" %
-			(s_post_pre, s_inc_dec, abs(i.idx.inc_dec)))
-            if (i.size != 0):
-                print("\t\t\tsize: %d" % i.size)
-            if (i.access != CS_AC_INVALID):
-                print("\t\t\taccess: %s" % s_access[i.access])
-
-            c += 1
-
-    (regs_read, regs_write) = insn.regs_access()
-
-    if len(regs_read) > 0:
-        print("\tRegisters read:", end="")
-        for r in regs_read:
-            print(" %s" %(insn.reg_name(r)), end="")
-        print("")
-
-    if len(regs_write) > 0:
-        print("\tRegisters modified:", end="")
-        for r in regs_write:
-            print(" %s" %(insn.reg_name(r)), end="")
-        print("")
-
-    if len(insn.groups) > 0:
-         print("\tgroups_count: %u" % len(insn.groups))
-
-# ## Test class Cs
-def test_class():
-
-    for (arch, mode, code, comment, syntax) in all_tests:
-        print("*" * 20)
-        print("Platform: %s" % comment)
-        print("Code: %s" % to_hex_uc(code))
-        print("Disasm:")
-
-        try:
-            md = Cs(arch, mode)
-            if syntax is not None:
-                md.syntax = syntax
-            md.detail = True
-            for insn in md.disasm(code, 0x1000):
-                print_insn_detail(insn)
-                print ()
-        except CsError as e:
-            print("ERROR: %s" % e)
-
-
-if __name__ == '__main__':
-    test_class()
diff --git a/bindings/python/tests/test_m68k.py b/bindings/python/tests/test_m68k.py
deleted file mode 100755
index 6efdfaedb..000000000
--- a/bindings/python/tests/test_m68k.py
+++ /dev/null
@@ -1,123 +0,0 @@
-#!/usr/bin/env python3
-
-# Capstone Python bindings, by Nicolas PLANEL <nplanel@gmail.com>
-from capstone import *
-from capstone.m68k import *
-from xprint import to_hex
-
-M68K_CODE = b"\xf0\x10\xf0\x00\x48\xaf\xff\xff\x7f\xff\x11\xb0\x01\x37\x7f\xff\xff\xff\x12\x34\x56\x78\x01\x33\x10\x10\x10\x10\x32\x32\x32\x32\x4C\x00\x54\x04\x48\xe7\xe0\x30\x4C\xDF\x0C\x07\xd4\x40\x87\x5a\x4e\x71\x02\xb4\xc0\xde\xc0\xde\x5c\x00\x1d\x80\x71\x12\x01\x23\xf2\x3c\x44\x22\x40\x49\x0e\x56\x54\xc5\xf2\x3c\x44\x00\x44\x7a\x00\x00\xf2\x00\x0a\x28\x4E\xB9\x00\x00\x00\x12\x4E\x75"
-
-all_tests = (
-        (CS_ARCH_M68K, CS_MODE_BIG_ENDIAN | CS_MODE_M68K_040, M68K_CODE, "M68K"),
-)
-
-s_addressing_modes = {
-	0:  "<invalid mode>",
-
-	1:  "Register Direct - Data",
-	2:  "Register Direct - Address",
-
-	3:  "Register Indirect - Address",
-	4:  "Register Indirect - Address with Postincrement",
-	5:  "Register Indirect - Address with Predecrement",
-	6:  "Register Indirect - Address with Displacement",
-
-	7:  "Address Register Indirect With Index - 8-bit displacement",
-	8:  "Address Register Indirect With Index - Base displacement",
-
-	9:  "Memory indirect - Postindex",
-	10: "Memory indirect - Preindex",
-
-	11: "Program Counter Indirect - with Displacement",
-
-	12: "Program Counter Indirect with Index - with 8-Bit Displacement",
-	13: "Program Counter Indirect with Index - with Base Displacement",
-
-	14: "Program Counter Memory Indirect - Postindexed",
-	15: "Program Counter Memory Indirect - Preindexed",
-
-	16: "Absolute Data Addressing  - Short",
-	17: "Absolute Data Addressing  - Long",
-	18: "Immediate value",
-    
-    19: "Branch Displacement",
-}
-
-def print_read_write_regs(insn):
-    for m in insn.regs_read:
-        print("\treading from reg: %s" % insn.reg_name(m))
-
-    for m in insn.regs_write:
-        print("\twriting to reg:   %s" % insn.reg_name(m))
-
-def print_insn_detail(insn):
-    if len(insn.operands) > 0:
-        print("\top_count: %u" % (len(insn.operands)))
-
-    print_read_write_regs(insn)
-    print("\tgroups_count: %u" % len(insn.groups))
-
-    for i, op in enumerate(insn.operands):
-        if op.type == M68K_OP_REG:
-            print("\t\toperands[%u].type: REG = %s" % (i, insn.reg_name(op.reg)))
-        elif op.type == M68K_OP_IMM:
-            print("\t\toperands[%u].type: IMM = 0x%x" % (i, op.imm & 0xffffffff))
-        elif op.type == M68K_OP_MEM:
-            print("\t\toperands[%u].type: MEM" % (i))
-            if op.mem.base_reg != M68K_REG_INVALID:
-                print("\t\t\toperands[%u].mem.base: REG = %s" % (i, insn.reg_name(op.mem.base_reg)))
-            if op.mem.index_reg != M68K_REG_INVALID:
-                print("\t\t\toperands[%u].mem.index: REG = %s" % (i, insn.reg_name(op.mem.index_reg)))
-                mem_index_str = "w"
-                if op.mem.index_size > 0:
-                    mem_index_str = "l"
-                print("\t\t\toperands[%u].mem.index: size = %s" % (i, mem_index_str))
-            if op.mem.disp != 0:
-                print("\t\t\toperands[%u].mem.disp: 0x%x" % (i, op.mem.disp))
-            if op.mem.scale != 0:
-                print("\t\t\toperands[%u].mem.scale: %d" % (i, op.mem.scale))
-            print("\t\taddress mode: %s" % (s_addressing_modes[op.address_mode]))
-        elif op.type == M68K_OP_FP_SINGLE:
-            print("\t\toperands[%u].type: FP_SINGLE" % i)
-            print("\t\toperands[%u].simm: %f" % (i, op.simm))
-        elif op.type == M68K_OP_FP_DOUBLE:
-            print("\t\toperands[%u].type: FP_DOUBLE" % i)
-            print("\t\toperands[%u].dimm: %lf" % (i, op.dimm))
-        elif op.type == M68K_OP_REG_BITS:
-            print("\t\toperands[%u].type: REG_BITS = $%x" % (i, op.register_bits))
-        elif op.type == M68K_OP_REG_PAIR:
-            print("\t\toperands[%u].type: REG_PAIR = (%s, %s)" % (i, insn.reg_name(op.reg_pair.reg_0), insn.reg_name(op.reg_pair.reg_1)))
-        elif op.type == M68K_OP_BR_DISP:
-            print("\t\toperands[%u].br_disp.disp: 0x%x" % (i, op.br_disp.disp))
-            print("\t\toperands[%u].br_disp.disp_size: %d" % (i, op.br_disp.disp_size))
-    print()
-
-# ## Test class Cs
-def test_class():
-    address = 0x01000
-    for (arch, mode, code, comment) in all_tests:
-        print("*" * 16)
-        print("Platform: %s" % comment)
-        print("Code: %s " % to_hex(code))
-        print("Disasm:")
-
-        try:
-            md = Cs(arch, mode)
-            md.detail = True
-            last_address = 0
-            for insn in md.disasm(code, address):
-                last_address = insn.address + insn.size
-                print("0x%x:\t%s\t%s" % (insn.address, insn.mnemonic, insn.op_str))
-                print_insn_detail(insn)
-            print("0x%x:\n" % (last_address))
-
-        except CsError as e:
-            print("ERROR: %s" % e.__str__())
-
-if __name__ == '__main__':
-    test_class()
-
-
-
-
-
diff --git a/bindings/python/tests/test_mips.py b/bindings/python/tests/test_mips.py
deleted file mode 100755
index b6a250299..000000000
--- a/bindings/python/tests/test_mips.py
+++ /dev/null
@@ -1,73 +0,0 @@
-#!/usr/bin/env python3
-
-# Capstone Python bindings, by Nguyen Anh Quynnh <aquynh@gmail.com>
-from capstone import *
-from capstone.mips import *
-from xprint import to_hex, to_x
-
-
-MIPS_CODE = b"\x0C\x10\x00\x97\x00\x00\x00\x00\x24\x02\x00\x0c\x8f\xa2\x00\x00\x34\x21\x34\x56"
-MIPS_CODE2 = b"\x56\x34\x21\x34\xc2\x17\x01\x00"
-MIPS_32R6M = b"\x00\x07\x00\x07\x00\x11\x93\x7c\x01\x8c\x8b\x7c\x00\xc7\x48\xd0"
-MIPS_32R6 = b"\xec\x80\x00\x19\x7c\x43\x22\xa0"
-MIPS_64SD = b"\x70\x00\xb2\xff"
-
-all_tests = (
-        (CS_ARCH_MIPS, CS_MODE_MIPS32 + CS_MODE_BIG_ENDIAN, MIPS_CODE, "MIPS-32 (Big-endian)"),
-        (CS_ARCH_MIPS, CS_MODE_MIPS64 + CS_MODE_LITTLE_ENDIAN, MIPS_CODE2, "MIPS-64-EL (Little-endian)"),
-        (CS_ARCH_MIPS, CS_MODE_MIPS32R6 + CS_MODE_MICRO + CS_MODE_BIG_ENDIAN, MIPS_32R6M, "MIPS-32R6 | Micro (Big-endian)"),
-        (CS_ARCH_MIPS, CS_MODE_MIPS32R6 + CS_MODE_BIG_ENDIAN, MIPS_32R6, "MIPS-32R6 (Big-endian)"),
-        (CS_ARCH_MIPS, CS_MODE_MIPS64 | CS_MODE_MIPS2 | CS_MODE_LITTLE_ENDIAN, MIPS_64SD, "MIPS-64-EL + Mips II (Little-endian)"),
-        (CS_ARCH_MIPS, CS_MODE_MIPS64 | CS_MODE_LITTLE_ENDIAN, MIPS_64SD, "MIPS-64-EL (Little-endian)"),
-)
-
-
-def print_insn_detail(insn):
-    # print address, mnemonic and operands
-    print("0x%x:\t%s\t%s" % (insn.address, insn.mnemonic, insn.op_str))
-
-    # "data" instruction generated by SKIPDATA option has no detail
-    if insn.id == 0:
-        return
-
-    if len(insn.operands) > 0:
-        print("\top_count: %u" % len(insn.operands))
-        c = -1
-        for i in insn.operands:
-            c += 1
-            if i.type == MIPS_OP_REG:
-                print("\t\toperands[%u].type: REG = %s" % (c, insn.reg_name(i.reg)))
-            if i.type == MIPS_OP_IMM:
-                print("\t\toperands[%u].type: IMM = 0x%s" % (c, to_x(i.imm)))
-            if i.type == MIPS_OP_MEM:
-                print("\t\toperands[%u].type: MEM" % c)
-                if i.mem.base != 0:
-                    print("\t\t\toperands[%u].mem.base: REG = %s" \
-                        % (c, insn.reg_name(i.mem.base)))
-                if i.mem.disp != 0:
-                    print("\t\t\toperands[%u].mem.disp: 0x%s" \
-                        % (c, to_x(i.mem.disp)))
-
-
-# ## Test class Cs
-def test_class():
-    for (arch, mode, code, comment) in all_tests:
-        print("*" * 16)
-        print("Platform: %s" % comment)
-        print("Code: %s" % to_hex(code))
-        print("Disasm:")
-
-        try:
-            md = Cs(arch, mode)
-            md.detail = True
-            for insn in md.disasm(code, 0x1000):
-                print_insn_detail(insn)
-                print()
-
-            print("0x%x:\n" % (insn.address + insn.size))
-        except CsError as e:
-            print("ERROR: %s" % e)
-
-
-if __name__ == '__main__':
-    test_class()
diff --git a/bindings/python/tests/test_mos65xx.py b/bindings/python/tests/test_mos65xx.py
deleted file mode 100755
index ae5db53c5..000000000
--- a/bindings/python/tests/test_mos65xx.py
+++ /dev/null
@@ -1,94 +0,0 @@
-#!/usr/bin/env python3
-
-# Capstone Python bindings, by Sebastian Macke <Sebastian Macke>
-from capstone import *
-from capstone.mos65xx import *
-from xprint import to_hex, to_x
-
-M6502_CODE = b"\xa1\x12\xa5\x12\xa9\x12\xad\x34\x12\xb1\x12\xb5\x12\xb9\x34\x12\xbd\x34\x12\x0d\x34\x12\x00\x81\x87\x6c\x01\x00\x85\xFF\x10\x00\x19\x42\x42\x00\x49\x42"
-M65C02_CODE = b"\x1a\x3a\x02\x12\x03\x5c\x34\x12"
-MW65C02_CODE = b"\x07\x12\x27\x12\x47\x12\x67\x12\x87\x12\xa7\x12\xc7\x12\xe7\x12\x10\xfe\x0f\x12\xfd\x4f\x12\xfd\x8f\x12\xfd\xcf\x12\xfd"
-M65816_CODE = b"\xa9\x34\x12\xad\x34\x12\xbd\x34\x12\xb9\x34\x12\xaf\x56\x34\x12\xbf\x56\x34\x12\xa5\x12\xb5\x12\xb2\x12\xa1\x12\xb1\x12\xa7\x12\xb7\x12\xa3\x12\xb3\x12\xc2\x00\xe2\x00\x54\x34\x12\x44\x34\x12\x02\x12"
-
-all_tests = (
-        (CS_ARCH_MOS65XX, CS_MODE_MOS65XX_6502, M6502_CODE, "MOS65XX_6502"),
-        (CS_ARCH_MOS65XX, CS_MODE_MOS65XX_65C02, M65C02_CODE, "MOS65XX_65C02"),
-        (CS_ARCH_MOS65XX, CS_MODE_MOS65XX_W65C02, MW65C02_CODE, "MOS65XX_W65C02"),
-        (CS_ARCH_MOS65XX, CS_MODE_MOS65XX_65816_LONG_MX, M65816_CODE, "MOS65XX_65816 (long m/x)"),
-)
-
-address_modes=[
-    "No address mode",
-    "implied",
-    "accumulator",
-    "immediate value",
-    "relative",
-    "interrupt signature",
-    "block move",
-    "zero page",
-    "zero page indexed with x",
-    "zero page indexed with y",
-    "relative bit branch",
-    "zero page indirect",
-    "zero page indexed with x indirect",
-    "zero page indirect indexed with y",
-    "zero page indirect long",
-    "zero page indirect long indexed with y",
-    "absolute",
-    "absolute indexed with x",
-    "absolute indexed with y",
-    "absolute indirect",
-    "absolute indexed with x indirect",
-    "absolute indirect long",
-    "absolute long",
-    "absolute long indexed with x",
-    "stack relative",
-    "stack relative indirect indexed with y",
-]
-
-
-def print_insn_detail(insn):
-    # print address, mnemonic and operands
-    print("0x%x:\t%s\t%s" % (insn.address, insn.mnemonic, insn.op_str))
-
-    # "data" instruction generated by SKIPDATA option has no detail
-    if insn.id == 0:
-        return
-    print("\taddress mode: %s" % (address_modes[insn.am]))
-    print("\tmodifies flags: %s" % ('true' if insn.modifies_flags != 0 else 'false'))
-    if len(insn.operands) > 0:
-        print("\top_count: %u" % len(insn.operands))
-        c = -1
-        for i in insn.operands:
-            c += 1
-            if i.type == MOS65XX_OP_REG:
-                print("\t\toperands[%u].type: REG = %s" % (c, insn.reg_name(i.reg)))
-            if i.type == MOS65XX_OP_IMM:
-                print("\t\toperands[%u].type: IMM = 0x%s" % (c, to_x(i.imm)))
-            if i.type == MOS65XX_OP_MEM:
-                print("\t\toperands[%u].type: MEM = 0x%s" % (c, to_x(i.mem)))
-
-
-# ## Test class Cs
-def test_class():
-    for (arch, mode, code, comment) in all_tests:
-        print("*" * 16)
-        print("Platform: %s" % comment)
-        print("Code: %s" % to_hex(code))
-        print("Disasm:")
-
-        try:
-            md = Cs(arch, mode)
-            md.detail = True
-            md.syntax = CS_OPT_SYNTAX_MOTOROLA
-            for insn in md.disasm(code, 0x1000):
-                print_insn_detail(insn)
-                print()
-
-            print("0x%x:\n" % (insn.address + insn.size))
-        except CsError as e:
-            print("ERROR: %s" % e)
-
-
-if __name__ == '__main__':
-    test_class()
diff --git a/bindings/python/tests/test_ppc.py b/bindings/python/tests/test_ppc.py
deleted file mode 100755
index 9f2b49386..000000000
--- a/bindings/python/tests/test_ppc.py
+++ /dev/null
@@ -1,93 +0,0 @@
-#!/usr/bin/env python3
-
-# Capstone Python bindings, by Nguyen Anh Quynnh <aquynh@gmail.com>
-from capstone import *
-from capstone.ppc import *
-from xprint import to_hex, to_x, to_x_32
-
-PPC_CODE = b"\x43\x20\x0c\x07\x41\x56\xff\x17\x80\x20\x00\x00\x80\x3f\x00\x00\x10\x43\x23\x0e\xd0\x44\x00\x80\x4c\x43\x22\x02\x2d\x03\x00\x80\x7c\x43\x20\x14\x7c\x43\x20\x93\x4f\x20\x00\x21\x4c\xc8\x00\x21\x40\x82\x00\x14"
-PPC_CODE2 = b"\x10\x60\x2a\x10\x10\x64\x28\x88\x7c\x4a\x5d\x0f"
-PPC_CODE3 = b"\x10\x00\x1f\xec\xe0\x6d\x80\x04\xe4\x6d\x80\x04\x10\x60\x1c\x4c\x10\x60\x1c\x0c\xf0\x6d\x80\x04\xf4\x6d\x80\x04\x10\x60\x1c\x4e\x10\x60\x1c\x0e\x10\x60\x1a\x10\x10\x60\x1a\x11\x10\x63\x20\x2a\x10\x63\x20\x2b\x10\x83\x20\x40\x10\x83\x20\xC0\x10\x83\x20\x00\x10\x83\x20\x80\x10\x63\x20\x24\x10\x63\x20\x25\x10\x63\x29\x3a\x10\x63\x29\x3b\x10\x63\x29\x1c\x10\x63\x29\x1d\x10\x63\x29\x1e\x10\x63\x29\x1f\x10\x63\x24\x20\x10\x63\x24\x21\x10\x63\x24\x60\x10\x63\x24\x61\x10\x63\x24\xA0\x10\x63\x24\xA1\x10\x63\x24\xE0\x10\x63\x24\xE1\x10\x60\x20\x90\x10\x60\x20\x91\x10\x63\x29\x38\x10\x63\x29\x39\x10\x63\x01\x32\x10\x63\x01\x33\x10\x63\x01\x18\x10\x63\x01\x19\x10\x63\x01\x1A\x10\x63\x01\x1B\x10\x60\x19\x10\x10\x60\x19\x11\x10\x60\x18\x50\x10\x60\x18\x51\x10\x63\x29\x3e\x10\x63\x29\x3f\x10\x63\x29\x3c\x10\x63\x29\x3d\x10\x60\x18\x30\x10\x60\x18\x31\x10\x60\x18\x34\x10\x60\x18\x35\x10\x63\x29\x2e\x10\x63\x29\x2f\x10\x63\x20\x28\x10\x63\x20\x29\x10\x63\x29\x14\x10\x63\x29\x15\x10\x63\x29\x16\x10\x63\x29\x17"
-
-all_tests = (
-        (CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, PPC_CODE, "PPC-64"),
-        (CS_ARCH_PPC, CS_MODE_BIG_ENDIAN + CS_MODE_QPX, PPC_CODE2, "PPC-64 + QPX"),
-        (CS_ARCH_PPC, CS_MODE_BIG_ENDIAN + CS_MODE_32 + CS_MODE_PS, PPC_CODE3, "PPC + PS"),
-        )
-
-
-def print_insn_detail(insn):
-    # print address, mnemonic and operands
-    print("0x%x:\t%s\t%s" % (insn.address, insn.mnemonic, insn.op_str))
-
-    # "data" instruction generated by SKIPDATA option has no detail
-    if insn.id == 0:
-        return
-
-    if len(insn.operands) > 0:
-        print("\top_count: %u" % len(insn.operands))
-        c = 0
-        for i in insn.operands:
-            if i.type == PPC_OP_REG:
-                print("\t\toperands[%u].type: REG = %s" % (c, insn.reg_name(i.reg)))
-            if i.type == PPC_OP_IMM:
-                print("\t\toperands[%u].type: IMM = 0x%s" % (c, to_x(i.imm)))
-            if i.type == PPC_OP_MEM:
-                print("\t\toperands[%u].type: MEM" % c)
-                if i.mem.base != PPC_REG_INVALID:
-                    print("\t\t\toperands[%u].mem.base: REG = %s" \
-                        % (c, insn.reg_name(i.mem.base)))
-                if i.mem.offset != 0:
-                    print("\t\t\toperands[%u].mem.offset: REG = %s" \
-                        % (c, insn.reg_name(i.mem.offset)))
-                if i.mem.disp != 0:
-                    print("\t\t\toperands[%u].mem.disp: 0x%s" \
-                        % (c, to_x_32(i.mem.disp)))
-            if i.access == CS_AC_READ:
-                print("\t\toperands[%u].access: READ" % (c))
-            elif i.access == CS_AC_WRITE:
-                print("\t\toperands[%u].access: WRITE" % (c))
-            elif i.access == CS_AC_READ | CS_AC_WRITE:
-                print("\t\toperands[%u].access: READ | WRITE" % (c))
-            c += 1
-    if insn.bc.pred_cr != PPC_PRED_INVALID or \
-        insn.bc.pred_ctr != PPC_PRED_INVALID:
-        print("\tBranch:")
-        print("\t\tbi: %u" % insn.bc.bi)
-        print("\t\tbo: %u" % insn.bc.bo)
-        if insn.bc.bh != PPC_BH_INVALID:
-            print("\t\tbh: %u" %insn.bc.bh)
-        if insn.bc.pred_cr != PPC_PRED_INVALID:
-            print("\t\tcrX: %s" % insn.reg_name(insn.bc.crX))
-            print("\t\tpred CR-bit: %u" % insn.bc.pred_cr)
-        if insn.bc.pred_ctr != PPC_PRED_INVALID:
-            print("\t\tpred CTR: %u" % insn.bc.pred_ctr)
-        if insn.bc.hint != PPC_BR_NOT_GIVEN:
-            print("\t\thint: %u" % insn.bc.hint)
-
-    if insn.update_cr0:
-        print("\tUpdate-CR0: True")
-
-
-# ## Test class Cs
-def test_class():
-
-    for (arch, mode, code, comment) in all_tests:
-        print("*" * 16)
-        print("Platform: %s" % comment)
-        print("Code: %s" % to_hex(code))
-        print("Disasm:")
-
-        try:
-            md = Cs(arch, mode)
-            md.detail = True
-            for insn in md.disasm(code, 0x1000):
-                print_insn_detail(insn)
-                print ()
-            print("0x%x:\n" % (insn.address + insn.size))
-        except CsError as e:
-            print("ERROR: %s" % e)
-
-
-if __name__ == '__main__':
-    test_class()
diff --git a/bindings/python/tests/test_riscv.py b/bindings/python/tests/test_riscv.py
deleted file mode 100755
index 396ef9228..000000000
--- a/bindings/python/tests/test_riscv.py
+++ /dev/null
@@ -1,79 +0,0 @@
-#!/usr/bin/env python3
-
-# Capstone Python bindings, by Nguyen Anh Quynnh <aquynh@gmail.com>
-
-from capstone import *
-from capstone.riscv import *
-from xprint import to_x, to_hex
-
-RISCV_CODE32 = b"\x37\x34\x00\x00\x97\x82\x00\x00\xef\x00\x80\x00\xef\xf0\x1f\xff\xe7\x00\x45\x00\xe7\x00\xc0\xff\x63\x05\x41\x00\xe3\x9d\x61\xfe\x63\xca\x93\x00\x63\x53\xb5\x00\x63\x65\xd6\x00\x63\x76\xf7\x00\x03\x88\x18\x00\x03\x99\x49\x00\x03\xaa\x6a\x00\x03\xcb\x2b\x01\x03\xdc\x8c\x01\x23\x86\xad\x03\x23\x9a\xce\x03\x23\x8f\xef\x01\x93\x00\xe0\x00\x13\xa1\x01\x01\x13\xb2\x02\x7d\x13\xc3\x03\xdd\x13\xe4\xc4\x12\x13\xf5\x85\x0c\x13\x96\xe6\x01\x13\xd7\x97\x01\x13\xd8\xf8\x40\x33\x89\x49\x01\xb3\x0a\x7b\x41\x33\xac\xac\x01\xb3\x3d\xde\x01\x33\xd2\x62\x40\xb3\x43\x94\x00\x33\xe5\xc5\x00\xb3\x76\xf7\x00\xb3\x54\x39\x01\xb3\x50\x31\x00\x33\x9f\x0f\x00\x73\x15\x04\xb0\xf3\x56\x00\x10\x33\x05\x7b\x03\xb3\x45\x9c\x03\x33\x66\xbd\x03\x2f\xa4\x02\x10\xaf\x23\x65\x18\x2f\x27\x2f\x01\x43\xf0\x20\x18\xd3\x72\x73\x00\x53\xf4\x04\x58\x53\x85\xc5\x28\x53\x2e\xde\xa1\xd3\x84\x05\xf0\x53\x06\x05\xe0\x53\x75\x00\xc0\xd3\xf0\x05\xd0\xd3\x15\x08\xe0\x87\xaa\x75\x00\x27\x27\x66\x01\x43\xf0\x20\x1a\xd3\x72\x73\x02\x53\xf4\x04\x5a\x53\x85\xc5\x2a\x53\x2e\xde\xa3"
-RISCV_CODE64 = b"\x13\x04\xa8\x7a\xbb\x07\x9c\x02\xbb\x40\x5d\x02\x3b\x63\xb7\x03\x2f\xb4\x02\x10\xaf\x33\x65\x18\x2f\x37\x2f\x01\x53\x75\x20\xc0\xd3\xf0\x25\xd0\xd3\x84\x05\xf2\x53\x06\x05\xe2\x53\x75\x00\xc2\xd3\x80\x05\xd2\xd3\x15\x08\xe2\x87\xba\x75\x00\x27\x37\x66\x01"
-RISCV_CODEC = b"\xe8\x1f\x7d\x61\x80\x25\x00\x46\x88\xa2\x04\xcb\x55\x13\xf2\x93\x5d\x45\x19\x80\x15\x68\x2a\xa4\x62\x24\xa6\xff\x2a\x65\x76\x86\x65\xdd\x01\x00\xfd\xaf\x82\x82\x11\x20\x82\x94"
-
-all_tests = (
-        (CS_ARCH_RISCV, CS_MODE_RISCV32, RISCV_CODE32, "riscv32"),
-        (CS_ARCH_RISCV, CS_MODE_RISCV64, RISCV_CODE64, "riscv64"),
-        (CS_ARCH_RISCV, CS_MODE_RISCVC,  RISCV_CODEC,  "riscvc"),
-)
-
-
-def print_insn_detail(insn):
-    # print address, mnemonic and operands
-    print("0x%x:\t%s\t%s" % (insn.address, insn.mnemonic, insn.op_str))
-
-    # "data" instruction generated by SKIPDATA option has no detail
-    if insn.id == 0:
-        return
-
-    if len(insn.operands) > 0:
-        print("\top_count: %u" % len(insn.operands))
-        c = 0
-        for i in insn.operands:
-            if i.type == RISCV_OP_REG:
-                print("\t\toperands[%u].type: REG = %s" % (c, insn.reg_name(i.reg)))
-            if i.type == RISCV_OP_IMM:
-                print("\t\toperands[%u].type: IMM = 0x%s" % (c, to_x(i.imm)))
-            if i.type == RISCV_OP_MEM:
-                print("\t\toperands[%u].type: MEM" % c)
-                if i.mem.base != 0:
-                    print("\t\t\toperands[%u].mem.base: REG = %s" \
-                        % (c, insn.reg_name(i.mem.base)))
-                if i.mem.disp != 0:
-                    print("\t\t\toperands[%u].mem.disp: 0x%s" \
-                        % (c, to_x(i.mem.disp)))
-
-            if i.access == CS_AC_READ:
-                print("\t\toperands[%u].access: READ" % (c))
-            elif i.access == CS_AC_WRITE:
-                print("\t\toperands[%u].access: WRITE" % (c))
-            elif i.access == CS_AC_READ | CS_AC_WRITE:
-                print("\t\toperands[%u].access: READ | WRITE" % (c))
-
-            c += 1
-    
-    if len(insn.groups) > 0:
-        print('\tgroups: ' + ' '.join(map(lambda g: insn.group_name(g), insn.groups)))
-
-
-# ## Test class Cs
-def test_class():
-
-    for (arch, mode, code, comment) in all_tests:
-        print("*" * 16)
-        print("Platform: %s" %comment)
-        print("Code: %s" % to_hex(code))
-        print("Disasm:")
-
-        try:
-            md = Cs(arch, mode)
-            md.detail = True
-            for insn in md.disasm(code, 0x1000):
-                print_insn_detail(insn)
-                print ()
-            print("0x%x:\n" % (insn.address + insn.size))
-        except CsError as e:
-            print("ERROR: %s" %e)
-
-
-if __name__ == '__main__':
-    test_class()
diff --git a/bindings/python/tests/test_sh.py b/bindings/python/tests/test_sh.py
deleted file mode 100755
index e5c2f3514..000000000
--- a/bindings/python/tests/test_sh.py
+++ /dev/null
@@ -1,96 +0,0 @@
-#!/usr/bin/env python3
-
-# Capstone Python bindings, by Peace-Maker <peacemakerctf@gmail.com>
-
-from capstone import *
-from capstone.sh import *
-from xprint import to_x, to_hex
-
-SH4A_CODE = b"\x0c\x31\x10\x20\x22\x21\x36\x64\x46\x25\x12\x12\x1c\x02\x08\xc1\x05\xc7\x0c\x71\x1f\x02\x22\xcf\x06\x89\x23\x00\x2b\x41\x0b\x00\x0e\x40\x32\x00\x0a\xf1\x09\x00"
-SH2A_CODE = b"\x32\x11\x92\x00\x32\x49\x31\x00"
-all_tests = (
-        (CS_ARCH_SH, CS_MODE_SH4A | CS_MODE_SHFPU, SH4A_CODE, "SH_SH4A"),
-        (CS_ARCH_SH, CS_MODE_SH2A | CS_MODE_SHFPU | CS_MODE_BIG_ENDIAN, SH2A_CODE, "SH_SH2A"),
-)
-
-
-reg_address_msg = [
-	"Register indirect",
-	"Register indirect with predecrement",
-	"Register indirect with postincrement",
-]
-
-def print_read_write_regs(insn):
-    if len(insn.regs_read) > 0:
-        print("\tRegisters read: %s" % " ".join(insn.reg_name(m) for m in insn.regs_read))
-
-    if len(insn.regs_write) > 0:
-        print("\tRegisters modified: %s" % " ".join(insn.reg_name(m) for m in insn.regs_write))
-
-def print_insn_detail(insn):
-    # print address, mnemonic and operands
-    print("0x%x:\t%s\t%s" % (insn.address, insn.mnemonic, insn.op_str))
-
-    # "data" instruction generated by SKIPDATA option has no detail
-    if insn.id == 0:
-        return
-
-    if len(insn.operands) > 0:
-        print("\top_count: %u" % len(insn.operands))
-        c = 0
-        for i in insn.operands:
-            if i.type == SH_OP_REG:
-                print("\t\toperands[%u].type: REG = %s" % (c, insn.reg_name(i.reg)))
-            elif i.type == SH_OP_IMM:
-                print("\t\toperands[%u].type: IMM = 0x%s" % (c, to_x(i.imm)))
-            elif i.type == SH_OP_MEM:
-                print("\t\toperands[%u].type: MEM " % c)
-                if i.mem.address in [SH_OP_MEM_REG_IND, SH_OP_MEM_REG_POST, SH_OP_MEM_REG_PRE]:
-                    print("%s REG %s" % (reg_address_msg[i.mem.address - SH_OP_MEM_REG_IND], insn.reg_name(i.mem.reg)))
-                elif i.mem.address == SH_OP_MEM_REG_DISP:
-                    print("Register indirect with displacement REG %s, DISP %d" % (insn.reg_name(i.mem.reg), i.mem.disp))
-                elif i.mem.address == SH_OP_MEM_REG_R0:
-                    print("R0 indexed")
-                elif i.mem.address == SH_OP_MEM_GBR_DISP:
-                    print("GBR base with displacement DISP %d" % i.mem.disp)
-                elif i.mem.address == SH_OP_MEM_GBR_R0:
-                    print("GBR base with R0 indexed")
-                elif i.mem.address == SH_OP_MEM_PCR:
-                    print("PC relative Address=0x%08x" % i.mem.disp)
-                elif i.mem.address == SH_OP_MEM_TBR_DISP:
-                    print("TBR base with displacement DISP %d", i.mem.disp)
-                else:
-                    print("Unknown addressing mode %x" % i.mem.address)
-            
-            if i.sh_size != 0:
-                print("\t\t\tsh_size: %u" % i.sh_size)
-            c += 1
-
-    print_read_write_regs(insn)
-
-    if len(insn.groups) > 0:
-        print('\tgroups: ' + ' '.join(map(lambda g: insn.group_name(g), insn.groups)))
-
-
-# ## Test class Cs
-def test_class():
-
-    for (arch, mode, code, comment) in all_tests:
-        print("*" * 16)
-        print("Platform: %s" %comment)
-        print("Code: %s" % to_hex(code))
-        print("Disasm:")
-
-        try:
-            md = Cs(arch, mode)
-            md.detail = True
-            for insn in md.disasm(code, 0x80000000):
-                print_insn_detail(insn)
-                print()
-            print("0x%x:" % (insn.address + insn.size))
-        except CsError as e:
-            print("ERROR: %s" %e)
-
-
-if __name__ == '__main__':
-    test_class()
diff --git a/bindings/python/tests/test_sparc.py b/bindings/python/tests/test_sparc.py
deleted file mode 100755
index e1b1344ab..000000000
--- a/bindings/python/tests/test_sparc.py
+++ /dev/null
@@ -1,74 +0,0 @@
-#!/usr/bin/env python3
-
-# Capstone Python bindings, by Nguyen Anh Quynnh <aquynh@gmail.com>
-
-from capstone import *
-from capstone.sparc import *
-from xprint import to_hex, to_x_32
-
-
-SPARC_CODE = b"\x80\xa0\x40\x02\x85\xc2\x60\x08\x85\xe8\x20\x01\x81\xe8\x00\x00\x90\x10\x20\x01\xd5\xf6\x10\x16\x21\x00\x00\x0a\x86\x00\x40\x02\x01\x00\x00\x00\x12\xbf\xff\xff\x10\xbf\xff\xff\xa0\x02\x00\x09\x0d\xbf\xff\xff\xd4\x20\x60\x00\xd4\x4e\x00\x16\x2a\xc2\x80\x03"
-SPARCV9_CODE = b"\x81\xa8\x0a\x24\x89\xa0\x10\x20\x89\xa0\x1a\x60\x89\xa0\x00\xe0"
-
-all_tests = (
-        (CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN, SPARC_CODE, "Sparc"),
-        (CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN+CS_MODE_V9, SPARCV9_CODE, "SparcV9"),
-)
-
-
-def print_insn_detail(insn):
-    # print address, mnemonic and operands
-    print("0x%x:\t%s\t%s" % (insn.address, insn.mnemonic, insn.op_str))
-
-    # "data" instruction generated by SKIPDATA option has no detail
-    if insn.id == 0:
-        return
-
-    if len(insn.operands) > 0:
-        print("\top_count: %u" % len(insn.operands))
-        c = 0
-        for i in insn.operands:
-            if i.type == SPARC_OP_REG:
-                print("\t\toperands[%u].type: REG = %s" % (c, insn.reg_name(i.reg)))
-            if i.type == SPARC_OP_IMM:
-                print("\t\toperands[%u].type: IMM = 0x%s" % (c, to_x_32(i.imm)))
-            if i.type == SPARC_OP_MEM:
-                print("\t\toperands[%u].type: MEM" % c)
-                if i.mem.base != 0:
-                    print("\t\t\toperands[%u].mem.base: REG = %s" \
-                        % (c, insn.reg_name(i.mem.base)))
-                if i.mem.index != 0:
-                    print("\t\t\toperands[%u].mem.index: REG = %s" \
-                        % (c, insn.reg_name(i.mem.index)))
-                if i.mem.disp != 0:
-                    print("\t\t\toperands[%u].mem.disp: 0x%s" \
-                        % (c, to_x_32(i.mem.disp)))
-            c += 1
-
-    if insn.cc:
-        print("\tCode condition: %u" % insn.cc)
-    if insn.hint:
-        print("\tHint code: %u" % insn.hint)
-
-
-# ## Test class Cs
-def test_class():
-    for (arch, mode, code, comment) in all_tests:
-        print("*" * 16)
-        print("Platform: %s" % comment)
-        print("Code: %s" % to_hex(code))
-        print("Disasm:")
-
-        try:
-            md = Cs(arch, mode)
-            md.detail = True
-            for insn in md.disasm(code, 0x1000):
-                print_insn_detail(insn)
-                print ()
-            print("0x%x:\n" % (insn.address + insn.size))
-        except CsError as e:
-            print("ERROR: %s" %e)
-
-
-if __name__ == '__main__':
-    test_class()
diff --git a/bindings/python/tests/test_systemz.py b/bindings/python/tests/test_systemz.py
deleted file mode 100755
index a628494fd..000000000
--- a/bindings/python/tests/test_systemz.py
+++ /dev/null
@@ -1,76 +0,0 @@
-#!/usr/bin/env python3
-
-# Capstone Python bindings, by Nguyen Anh Quynnh <aquynh@gmail.com>
-
-from capstone import *
-from capstone.systemz import *
-from xprint import to_x, to_hex
-
-
-SYSZ_CODE = b"\xed\x00\x00\x00\x00\x1a\x5a\x0f\x1f\xff\xc2\x09\x80\x00\x00\x00\x07\xf7\xeb\x2a\xff\xff\x7f\x57\xe3\x01\xff\xff\x7f\x57\xeb\x00\xf0\x00\x00\x24\xb2\x4f\x00\x78\xec\x18\x00\x00\xc1\x7f"
-
-all_tests = (
-        (CS_ARCH_SYSZ, 0, SYSZ_CODE, "SystemZ"),
-)
-
-
-def print_insn_detail(insn):
-    # print address, mnemonic and operands
-    print("0x%x:\t%s\t%s" % (insn.address, insn.mnemonic, insn.op_str))
-
-    # "data" instruction generated by SKIPDATA option has no detail
-    if insn.id == 0:
-        return
-
-    if len(insn.operands) > 0:
-        print("\top_count: %u" % len(insn.operands))
-        c = 0
-        for i in insn.operands:
-            if i.type == SYSZ_OP_REG:
-                print("\t\toperands[%u].type: REG = %s" % (c, insn.reg_name(i.reg)))
-            if i.type == SYSZ_OP_ACREG:
-                print("\t\toperands[%u].type: ACREG = %u" % (c, i.reg))
-            if i.type == SYSZ_OP_IMM:
-                print("\t\toperands[%u].type: IMM = 0x%s" % (c, to_x(i.imm)))
-            if i.type == SYSZ_OP_MEM:
-                print("\t\toperands[%u].type: MEM" % c)
-                if i.mem.base != 0:
-                    print("\t\t\toperands[%u].mem.base: REG = %s" \
-                        % (c, insn.reg_name(i.mem.base)))
-                if i.mem.index != 0:
-                    print("\t\t\toperands[%u].mem.index: REG = %s" \
-                        % (c, insn.reg_name(i.mem.index)))
-                if i.mem.length != 0:
-                    print("\t\t\toperands[%u].mem.length: 0x%s" \
-                        % (c, to_x(i.mem.length)))
-                if i.mem.disp != 0:
-                    print("\t\t\toperands[%u].mem.disp: 0x%s" \
-                        % (c, to_x(i.mem.disp)))
-            c += 1
-
-    if insn.cc:
-        print("\tConditional code: %u" % insn.cc)
-
-
-# ## Test class Cs
-def test_class():
-
-    for (arch, mode, code, comment) in all_tests:
-        print("*" * 16)
-        print("Platform: %s" %comment)
-        print("Code: %s" % to_hex(code))
-        print("Disasm:")
-
-        try:
-            md = Cs(arch, mode)
-            md.detail = True
-            for insn in md.disasm(code, 0x1000):
-                print_insn_detail(insn)
-                print ()
-            print("0x%x:\n" % (insn.address + insn.size))
-        except CsError as e:
-            print("ERROR: %s" %e)
-
-
-if __name__ == '__main__':
-    test_class()
diff --git a/bindings/python/tests/test_tms320c64x.py b/bindings/python/tests/test_tms320c64x.py
deleted file mode 100755
index 1bb64b0c1..000000000
--- a/bindings/python/tests/test_tms320c64x.py
+++ /dev/null
@@ -1,113 +0,0 @@
-#!/usr/bin/env python3
-
-# Capstone Python bindings, by Fotis Loukos <me@fotisl.com>
-
-from capstone import *
-from capstone.tms320c64x import *
-from xprint import to_x, to_hex, to_x_32
-
-
-TMS320C64X_CODE = b"\x01\xac\x88\x40\x81\xac\x88\x43\x00\x00\x00\x00\x02\x90\x32\x96\x02\x80\x46\x9e\x05\x3c\x83\xe6\x0b\x0c\x8b\x24"
-
-all_tests = (
-        (CS_ARCH_TMS320C64X, 0, TMS320C64X_CODE, "TMS320C64x"),
-)
-
-
-def print_insn_detail(insn):
-    # print address, mnemonic and operands
-    print("0x%x:\t%s\t%s" % (insn.address, insn.mnemonic, insn.op_str))
-
-    # "data" instruction generated by SKIPDATA option has no detail
-    if insn.id == 0:
-        return
-
-    if len(insn.operands) > 0:
-        print("\top_count: %u" % len(insn.operands))
-        c = 0
-        for i in insn.operands:
-            if i.type == TMS320C64X_OP_REG:
-                print("\t\toperands[%u].type: REG = %s" % (c, insn.reg_name(i.reg)))
-            if i.type == TMS320C64X_OP_IMM:
-                print("\t\toperands[%u].type: IMM = 0x%s" % (c, to_x(i.imm)))
-            if i.type == TMS320C64X_OP_MEM:
-                print("\t\toperands[%u].type: MEM" % c)
-                if i.mem.base != 0:
-                    print("\t\t\toperands[%u].mem.base: REG = %s" \
-                        % (c, insn.reg_name(i.mem.base)))
-                if i.mem.disptype == TMS320C64X_MEM_DISP_INVALID:
-                    print("\t\t\toperands[%u].mem.disptype: Invalid" % (c))
-                    print("\t\t\toperands[%u].mem.disp: 0x%s" \
-                        % (c, to_x(i.mem.disp)))
-                if i.mem.disptype == TMS320C64X_MEM_DISP_CONSTANT:
-                    print("\t\t\toperands[%u].mem.disptype: Constant" % (c))
-                    print("\t\t\toperands[%u].mem.disp: 0x%s" \
-                        % (c, to_x(i.mem.disp)))
-                if i.mem.disptype == TMS320C64X_MEM_DISP_REGISTER:
-                    print("\t\t\toperands[%u].mem.disptype: Register" % (c))
-                    print("\t\t\toperands[%u].mem.disp: %s" \
-                        % (c, insn.reg_name(i.mem.disp)))
-                print("\t\t\toperands[%u].mem.unit: %u" % (c, i.mem.unit))
-                if i.mem.direction == TMS320C64X_MEM_DIR_INVALID:
-                    print("\t\t\toperands[%u].mem.direction: Invalid" % (c))
-                if i.mem.direction == TMS320C64X_MEM_DIR_FW:
-                    print("\t\t\toperands[%u].mem.direction: Forward" % (c))
-                if i.mem.direction == TMS320C64X_MEM_DIR_BW:
-                    print("\t\t\toperands[%u].mem.direction: Backward" % (c))
-                if i.mem.modify == TMS320C64X_MEM_MOD_INVALID:
-                    print("\t\t\toperands[%u].mem.modify: Invalid" % (c))
-                if i.mem.modify == TMS320C64X_MEM_MOD_NO:
-                    print("\t\t\toperands[%u].mem.modify: No" % (c))
-                if i.mem.modify == TMS320C64X_MEM_MOD_PRE:
-                    print("\t\t\toperands[%u].mem.modify: Pre" % (c))
-                if i.mem.modify == TMS320C64X_MEM_MOD_POST:
-                    print("\t\t\toperands[%u].mem.modify: Post" % (c))
-                print("\t\t\toperands[%u].mem.scaled: %u" % (c, i.mem.scaled))
-            if i.type == TMS320C64X_OP_REGPAIR:
-                print("\t\toperands[%u].type: REGPAIR = %s:%s" % (c, insn.reg_name(i.reg + 1), insn.reg_name(i.reg)))
-            c += 1
-    
-    print("\tFunctional unit: ", end="")
-    if insn.funit.unit == TMS320C64X_FUNIT_D:
-        print("D%u" % insn.funit.side)
-    elif insn.funit.unit == TMS320C64X_FUNIT_L:
-        print("L%u" % insn.funit.side)
-    elif insn.funit.unit == TMS320C64X_FUNIT_M:
-        print("M%u" % insn.funit.side)
-    elif insn.funit.unit == TMS320C64X_FUNIT_S:
-        print("S%u" % insn.funit.side)
-    elif insn.funit.unit == TMS320C64X_FUNIT_NO:
-        print("No Functional Unit")
-    else:
-        print("Unknown (Unit %u, Side %u)" % (insn.funit.unit, insn.funit.side))
-
-    if insn.funit.crosspath == 1:
-        print("\tCrosspath: 1")
-    
-    if insn.condition.reg != TMS320C64X_REG_INVALID:
-        print("\tCondition: [%c%s]" % ("!" if insn.condition.zero == 1 else " ", insn.reg_name(insn.condition.reg)))
-    print("\tParallel: %s" % ("true" if insn.parallel == 1 else "false"))
-
-    print()
-
-# ## Test class Cs
-def test_class():
-
-    for (arch, mode, code, comment) in all_tests:
-        print("*" * 16)
-        print("Platform: %s" %comment)
-        print("Code: %s" % to_hex(code))
-        print("Disasm:")
-
-        try:
-            md = Cs(arch, mode)
-            md.detail = True
-            for insn in md.disasm(code, 0x1000):
-                print_insn_detail(insn)
-            print("0x%x:\n" % (insn.address + insn.size))
-        except CsError as e:
-            print("ERROR: %s" %e)
-
-
-if __name__ == '__main__':
-    test_class()
diff --git a/bindings/python/tests/test_tricore.py b/bindings/python/tests/test_tricore.py
deleted file mode 100755
index 632a026ad..000000000
--- a/bindings/python/tests/test_tricore.py
+++ /dev/null
@@ -1,63 +0,0 @@
-#!/usr/bin/env python3
-
-# Capstone Python bindings, by Nguyen Anh Quynnh <aquynh@gmail.com>
-
-from capstone import *
-from capstone.tricore import *
-from xprint import to_hex, to_x
-
-TRICORE_CODE = b"\x09\xcf\xbc\xf5\x09\xf4\x01\x00\x89\xfb\x8f\x74\x89\xfe\x48\x01\x29\x00\x19\x25\x29\x03\x09\xf4\x85\xf9\x68\x0f\x16\x01"
-
-all_tests = (
-    (CS_ARCH_TRICORE, CS_MODE_TRICORE_162, TRICORE_CODE, "TriCore"),
-)
-
-
-def print_insn_detail(insn):
-    # print address, mnemonic and operands
-    print("0x%x:\t%s\t%s" % (insn.address, insn.mnemonic, insn.op_str))
-
-    # "data" instruction generated by SKIPDATA option has no detail
-    if insn.id == 0:
-        return
-
-    if len(insn.operands) > 0:
-        print("\top_count: %u" % len(insn.operands))
-        c = 0
-        for i in insn.operands:
-            if i.type == TRICORE_OP_REG:
-                print("\t\toperands[%u].type: REG = %s" % (c, insn.reg_name(i.reg)))
-            if i.type == TRICORE_OP_IMM:
-                print("\t\toperands[%u].type: IMM = 0x%s" % (c, to_x(i.imm)))
-            if i.type == TRICORE_OP_MEM:
-                print("\t\toperands[%u].type: MEM" % c)
-                if i.mem.base != 0:
-                    print("\t\t\toperands[%u].mem.base: REG = %s" \
-                          % (c, insn.reg_name(i.mem.base)))
-                if i.mem.disp != 0:
-                    print("\t\t\toperands[%u].mem.disp: 0x%s" \
-                          % (c, to_x(i.mem.disp)))
-            c += 1
-    print()
-
-
-# ## Test class Cs
-def test_class():
-    for (arch, mode, code, comment) in all_tests:
-        print("*" * 16)
-        print("Platform: %s" % comment)
-        print("Code: %s" % to_hex(code))
-        print("Disasm:")
-
-        try:
-            md = Cs(arch, mode)
-            md.detail = True
-            for insn in md.disasm(code, 0x1000):
-                print_insn_detail(insn)
-            print("0x%x:" % (insn.address + insn.size))
-        except CsError as e:
-            print("ERROR: %s" % e)
-
-
-if __name__ == '__main__':
-    test_class()
diff --git a/bindings/python/tests/test_wasm.py b/bindings/python/tests/test_wasm.py
deleted file mode 100755
index eea854982..000000000
--- a/bindings/python/tests/test_wasm.py
+++ /dev/null
@@ -1,80 +0,0 @@
-#!/usr/bin/env python3
-
-# Capstone Python bindings, by Peace-Maker <peacemakerctf@gmail.com>
-
-from capstone import *
-from capstone.wasm import *
-from xprint import to_hex
-
-WASM_CODE = b"\x20\x00\x20\x01\x41\x20\x10\xc9\x01\x45\x0b"
-
-all_tests = (
-    (CS_ARCH_WASM, 0, WASM_CODE, "WASM"),
-)
-
-
-def print_insn_detail(insn):
-    # print address, mnemonic and operands
-    print("0x%x:\t%s\t%s" % (insn.address, insn.mnemonic, insn.op_str))
-
-    # "data" instruction generated by SKIPDATA option has no detail
-    if insn.id == 0:
-        return
-
-    if len(insn.groups) > 0:
-        print("\tGroups: ", end="")
-        for group in insn.groups:
-            print("%s " % insn.group_name(group), end="")
-        print()
-
-    if len(insn.operands) > 0:
-        print("\tOperand count: %u" % len(insn.operands))
-        c = 0
-        for i in insn.operands:
-            if i.type == WASM_OP_INT7:
-                print("\t\tOperand[%u] type: int7" % c)
-                print("\t\tOperand[%u] value: %d" % (c, i.int7))
-            elif i.type == WASM_OP_VARUINT32:
-                print("\t\tOperand[%u] type: varuint32" % c)
-                print("\t\tOperand[%u] value: %#x" % (c, i.varuint32))
-            elif i.type == WASM_OP_VARUINT64:
-                print("\t\tOperand[%u] type: varuint64" % c)
-                print("\t\tOperand[%u] value: %#x" % (c, i.varuint64))
-            elif i.type == WASM_OP_UINT32:
-                print("\t\tOperand[%u] type: uint32" % c)
-                print("\t\tOperand[%u] value: %#x" % (c, i.uint32))
-            elif i.type == WASM_OP_UINT64:
-                print("\t\tOperand[%u] type: uint64" % c)
-                print("\t\tOperand[%u] value: %#x" % (c, i.uint64))
-            elif i.type == WASM_OP_IMM:
-                print("\t\tOperand[%u] type: imm" % c)
-                print("\t\tOperand[%u] value: %#x %#x" % (c, i.immediate[0], i.immediate[1]))
-            elif i.type == WASM_OP_BRTABLE:
-                print("\t\tOperand[%u] type: brtable" % c)
-                print("\t\tOperand[%u] value: length=%#x, address=%#x, default_target=%#x" % (c, i.brtable.length, i.brtable.address, i.brtable.default_target))
-            print("\t\tOperand[%u] size: %u" % (c, i.size))
-            c += 1
-        
-
-
-# ## Test class Cs
-def test_class():
-    for (arch, mode, code, comment) in all_tests:
-        print("*" * 16)
-        print("Platform: %s" % comment)
-        print("Code: %s" % to_hex(code))
-        print("Disasm:")
-
-        try:
-            md = Cs(arch, mode)
-            md.detail = True
-            for insn in md.disasm(code, 0xffff):
-                print_insn_detail(insn)
-                print()
-            print("0x%x:\n" % (insn.address + insn.size))
-        except CsError as e:
-            print("ERROR: %s" % e)
-
-
-if __name__ == '__main__':
-    test_class()
diff --git a/bindings/python/tests/test_x86.py b/bindings/python/tests/test_x86.py
deleted file mode 100755
index 4bcf4238b..000000000
--- a/bindings/python/tests/test_x86.py
+++ /dev/null
@@ -1,344 +0,0 @@
-#!/usr/bin/env python3
-
-# Capstone Python bindings, by Nguyen Anh Quynnh <aquynh@gmail.com>
-from capstone import *
-from capstone.x86 import *
-from xprint import to_hex, to_x
-
-
-X86_CODE64 = b"\x55\x48\x8b\x05\xb8\x13\x00\x00\xe9\xea\xbe\xad\xde\xff\x25\x23\x01\x00\x00\xe8\xdf\xbe\xad\xde\x74\xff"
-X86_CODE16 = b"\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00\x05\x23\x01\x00\x00\x36\x8b\x84\x91\x23\x01\x00\x00\x41\x8d\x84\x39\x89\x67\x00\x00\x8d\x87\x89\x67\x00\x00\xb4\xc6\x66\xe9\xb8\x00\x00\x00\x67\xff\xa0\x23\x01\x00\x00\x66\xe8\xcb\x00\x00\x00\x74\xfc"
-X86_CODE32 = b"\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00\x05\x23\x01\x00\x00\x36\x8b\x84\x91\x23\x01\x00\x00\x41\x8d\x84\x39\x89\x67\x00\x00\x8d\x87\x89\x67\x00\x00\xb4\xc6\xe9\xea\xbe\xad\xde\xff\xa0\x23\x01\x00\x00\xe8\xdf\xbe\xad\xde\x74\xff"
-
-all_tests = (
-        (CS_ARCH_X86, CS_MODE_16, X86_CODE16, "X86 16bit (Intel syntax)", None),
-        (CS_ARCH_X86, CS_MODE_32, X86_CODE32, "X86 32 (AT&T syntax)", CS_OPT_SYNTAX_ATT),
-        (CS_ARCH_X86, CS_MODE_32, X86_CODE32, "X86 32 (Intel syntax)", None),
-        (CS_ARCH_X86, CS_MODE_64, X86_CODE64, "X86 64 (Intel syntax)", None),
-        )
-
-
-def get_eflag_name(eflag):
-    if eflag == X86_EFLAGS_UNDEFINED_OF:
-        return "UNDEF_OF"
-    elif eflag == X86_EFLAGS_UNDEFINED_SF:
-        return "UNDEF_SF"
-    elif eflag == X86_EFLAGS_UNDEFINED_ZF:
-        return "UNDEF_ZF"
-    elif eflag == X86_EFLAGS_MODIFY_AF:
-        return "MOD_AF"
-    elif eflag == X86_EFLAGS_UNDEFINED_PF:
-        return "UNDEF_PF"
-    elif eflag == X86_EFLAGS_MODIFY_CF:
-        return "MOD_CF"
-    elif eflag == X86_EFLAGS_MODIFY_SF:
-        return "MOD_SF"
-    elif eflag == X86_EFLAGS_MODIFY_ZF:
-        return "MOD_ZF"
-    elif eflag == X86_EFLAGS_UNDEFINED_AF:
-        return "UNDEF_AF"
-    elif eflag == X86_EFLAGS_MODIFY_PF:
-        return "MOD_PF"
-    elif eflag == X86_EFLAGS_UNDEFINED_CF:
-        return "UNDEF_CF"
-    elif eflag == X86_EFLAGS_MODIFY_OF:
-        return "MOD_OF"
-    elif eflag == X86_EFLAGS_RESET_OF:
-        return "RESET_OF"
-    elif eflag == X86_EFLAGS_RESET_CF:
-        return "RESET_CF"
-    elif eflag == X86_EFLAGS_RESET_DF:
-        return "RESET_DF"
-    elif eflag == X86_EFLAGS_RESET_IF:
-        return "RESET_IF"
-    elif eflag == X86_EFLAGS_TEST_OF:
-        return "TEST_OF"
-    elif eflag == X86_EFLAGS_TEST_SF:
-        return "TEST_SF"
-    elif eflag == X86_EFLAGS_TEST_ZF:
-        return "TEST_ZF"
-    elif eflag == X86_EFLAGS_TEST_PF:
-        return "TEST_PF"
-    elif eflag == X86_EFLAGS_TEST_CF:
-        return "TEST_CF"
-    elif eflag == X86_EFLAGS_RESET_SF:
-        return "RESET_SF"
-    elif eflag == X86_EFLAGS_RESET_AF:
-        return "RESET_AF"
-    elif eflag == X86_EFLAGS_RESET_TF:
-        return "RESET_TF"
-    elif eflag == X86_EFLAGS_RESET_NT:
-        return "RESET_NT"
-    elif eflag == X86_EFLAGS_PRIOR_OF:
-        return "PRIOR_OF"
-    elif eflag == X86_EFLAGS_PRIOR_SF:
-        return "PRIOR_SF"
-    elif eflag == X86_EFLAGS_PRIOR_ZF:
-        return "PRIOR_ZF"
-    elif eflag == X86_EFLAGS_PRIOR_AF:
-        return "PRIOR_AF"
-    elif eflag == X86_EFLAGS_PRIOR_PF:
-        return "PRIOR_PF"
-    elif eflag == X86_EFLAGS_PRIOR_CF:
-        return "PRIOR_CF"
-    elif eflag == X86_EFLAGS_PRIOR_TF:
-        return "PRIOR_TF"
-    elif eflag == X86_EFLAGS_PRIOR_IF:
-        return "PRIOR_IF"
-    elif eflag == X86_EFLAGS_PRIOR_DF:
-        return "PRIOR_DF"
-    elif eflag == X86_EFLAGS_TEST_NT:
-        return "TEST_NT"
-    elif eflag == X86_EFLAGS_TEST_DF:
-        return "TEST_DF"
-    elif eflag == X86_EFLAGS_RESET_PF:
-        return "RESET_PF"
-    elif eflag == X86_EFLAGS_PRIOR_NT:
-        return "PRIOR_NT"
-    elif eflag == X86_EFLAGS_MODIFY_TF:
-        return "MOD_TF"
-    elif eflag == X86_EFLAGS_MODIFY_IF:
-        return "MOD_IF"
-    elif eflag == X86_EFLAGS_MODIFY_DF:
-        return "MOD_DF"
-    elif eflag == X86_EFLAGS_MODIFY_NT:
-        return "MOD_NT"
-    elif eflag == X86_EFLAGS_MODIFY_RF:
-        return "MOD_RF"
-    elif eflag == X86_EFLAGS_SET_CF:
-        return "SET_CF"
-    elif eflag == X86_EFLAGS_SET_DF:
-        return "SET_DF"
-    elif eflag == X86_EFLAGS_SET_IF:
-        return "SET_IF"
-    else: 
-        return None
-
-def get_fpu_flag_name(flag):
-    if flag == X86_FPU_FLAGS_MODIFY_C0:
-        return "MOD_C0"
-    elif flag == X86_FPU_FLAGS_MODIFY_C1:
-        return "MOD_C1"
-    elif flag == X86_FPU_FLAGS_MODIFY_C2:
-        return "MOD_C2"
-    elif flag == X86_FPU_FLAGS_MODIFY_C3:
-        return "MOD_C3"
-    elif flag == X86_FPU_FLAGS_RESET_C0:
-        return "RESET_C0"
-    elif flag == X86_FPU_FLAGS_RESET_C1:
-        return "RESET_C1"
-    elif flag == X86_FPU_FLAGS_RESET_C2:
-        return "RESET_C2"
-    elif flag == X86_FPU_FLAGS_RESET_C3:
-        return "RESET_C3"
-    elif flag == X86_FPU_FLAGS_SET_C0:
-        return "SET_C0"
-    elif flag == X86_FPU_FLAGS_SET_C1:
-        return "SET_C1"
-    elif flag == X86_FPU_FLAGS_SET_C2:
-        return "SET_C2"
-    elif flag == X86_FPU_FLAGS_SET_C3:
-        return "SET_C3"
-    elif flag == X86_FPU_FLAGS_UNDEFINED_C0:
-        return "UNDEF_C0"
-    elif flag == X86_FPU_FLAGS_UNDEFINED_C1:
-        return "UNDEF_C1"
-    elif flag == X86_FPU_FLAGS_UNDEFINED_C2:
-        return "UNDEF_C2"
-    elif flag == X86_FPU_FLAGS_UNDEFINED_C3:
-        return "UNDEF_C3"
-    elif flag == X86_FPU_FLAGS_TEST_C0:
-        return "TEST_C0"
-    elif flag == X86_FPU_FLAGS_TEST_C1:
-        return "TEST_C1"
-    elif flag == X86_FPU_FLAGS_TEST_C2:
-        return "TEST_C2"
-    elif flag == X86_FPU_FLAGS_TEST_C3:
-        return "TEST_C3"
-    else:
-        return None
-
-
-def print_insn_detail(mode, insn):
-    def print_string_hex(comment, str):
-        print(comment, end=' '),
-        for c in str:
-            print("0x%02x " % c, end=''),
-        print()
-
-    # print address, mnemonic and operands
-    print("0x%x:\t%s\t%s" % (insn.address, insn.mnemonic, insn.op_str))
-
-    # "data" instruction generated by SKIPDATA option has no detail
-    if insn.id == 0:
-        return
-
-    # print instruction prefix
-    print_string_hex("\tPrefix:", insn.prefix)
-
-    # print instruction's opcode
-    print_string_hex("\tOpcode:", insn.opcode)
-
-    # print operand's REX prefix (non-zero value is relevant for x86_64 instructions)
-    print("\trex: 0x%x" % (insn.rex))
-
-    # print operand's address size
-    print("\taddr_size: %u" % (insn.addr_size))
-
-    # print modRM byte
-    print("\tmodrm: 0x%x" % (insn.modrm))
-
-    # print modRM offset
-    if insn.encoding.modrm_offset != 0:
-        print("\tmodrm_offset: 0x%x" % (insn.encoding.modrm_offset))
-
-    # print displacement value
-    print("\tdisp: 0x%s" % to_x(insn.disp))
-
-    # print displacement offset (offset into instruction bytes)
-    if insn.encoding.disp_offset != 0:
-        print("\tdisp_offset: 0x%x" % (insn.encoding.disp_offset))
-
-    # print displacement size
-    if insn.encoding.disp_size != 0:
-        print("\tdisp_size: 0x%x" % (insn.encoding.disp_size))
-
-    # SIB is not available in 16-bit mode
-    if (mode & CS_MODE_16 == 0):
-        # print SIB byte
-        print("\tsib: 0x%x" % (insn.sib))
-        if (insn.sib):
-            if insn.sib_base != 0:
-                print("\t\tsib_base: %s" % (insn.reg_name(insn.sib_base)))
-            if insn.sib_index != 0:
-                print("\t\tsib_index: %s" % (insn.reg_name(insn.sib_index)))
-            if insn.sib_scale != 0:
-                print("\t\tsib_scale: %d" % (insn.sib_scale))
-
-    # XOP CC type
-    if insn.xop_cc != X86_XOP_CC_INVALID:
-        print("\txop_cc: %u" % (insn.xop_cc))
-
-    # SSE CC type
-    if insn.sse_cc != X86_SSE_CC_INVALID:
-        print("\tsse_cc: %u" % (insn.sse_cc))
-
-    # AVX CC type
-    if insn.avx_cc != X86_AVX_CC_INVALID:
-        print("\tavx_cc: %u" % (insn.avx_cc))
-
-    # AVX Suppress All Exception
-    if insn.avx_sae:
-        print("\tavx_sae: TRUE")
-
-    # AVX Rounding Mode type
-    if insn.avx_rm != X86_AVX_RM_INVALID:
-        print("\tavx_rm: %u" % (insn.avx_rm))
-
-    count = insn.op_count(X86_OP_IMM)
-    if count > 0:
-        print("\timm_count: %u" % count)
-        for i in range(count):
-            op = insn.op_find(X86_OP_IMM, i + 1)
-            print("\t\timms[%u]: 0x%s" % (i + 1, to_x(op.imm)))
-            if insn.encoding.imm_offset != 0:
-                print("\timm_offset: 0x%x" % (insn.encoding.imm_offset))
-            if insn.encoding.imm_size != 0:
-                print("\timm_size: 0x%x" % (insn.encoding.imm_size))
-
-    if len(insn.operands) > 0:
-        print("\top_count: %u" % len(insn.operands))
-        c = -1
-        for i in insn.operands:
-            c += 1
-            if i.type == X86_OP_REG:
-                print("\t\toperands[%u].type: REG = %s" % (c, insn.reg_name(i.reg)))
-            if i.type == X86_OP_IMM:
-                print("\t\toperands[%u].type: IMM = 0x%s" % (c, to_x(i.imm)))
-            if i.type == X86_OP_MEM:
-                print("\t\toperands[%u].type: MEM" % c)
-                if i.mem.segment != 0:
-                    print("\t\t\toperands[%u].mem.segment: REG = %s" % (c, insn.reg_name(i.mem.segment)))
-                if i.mem.base != 0:
-                    print("\t\t\toperands[%u].mem.base: REG = %s" % (c, insn.reg_name(i.mem.base)))
-                if i.mem.index != 0:
-                    print("\t\t\toperands[%u].mem.index: REG = %s" % (c, insn.reg_name(i.mem.index)))
-                if i.mem.scale != 1:
-                    print("\t\t\toperands[%u].mem.scale: %u" % (c, i.mem.scale))
-                if i.mem.disp != 0:
-                    print("\t\t\toperands[%u].mem.disp: 0x%s" % (c, to_x(i.mem.disp)))
-
-            # AVX broadcast type
-            if i.avx_bcast != X86_AVX_BCAST_INVALID:
-                print("\t\toperands[%u].avx_bcast: %u" % (c, i.avx_bcast))
-
-            # AVX zero opmask {z}
-            if i.avx_zero_opmask:
-                print("\t\toperands[%u].avx_zero_opmask: TRUE" % (c))
-
-            print("\t\toperands[%u].size: %u" % (c, i.size))
-
-            if i.access == CS_AC_READ:
-                print("\t\toperands[%u].access: READ" % (c))
-            elif i.access == CS_AC_WRITE:
-                print("\t\toperands[%u].access: WRITE" % (c))
-            elif i.access == CS_AC_READ | CS_AC_WRITE:
-                print("\t\toperands[%u].access: READ | WRITE" % (c))
-
-    (regs_read, regs_write) = insn.regs_access()
-
-    if len(regs_read) > 0:
-        print("\tRegisters read:", end="")
-        for r in regs_read:
-            print(" %s" %(insn.reg_name(r)), end="")
-        print("")
-
-    if len(regs_write) > 0:
-        print("\tRegisters modified:", end="")
-        for r in regs_write:
-            print(" %s" %(insn.reg_name(r)), end="")
-        print("")
-    
-    if insn.eflags or insn.fpu_flags:
-        updated_flags = []
-        for group in insn.groups:
-            if group == X86_GRP_FPU:
-                for i in range(64):
-                    if insn.fpu_flags & (1 << i):
-                        updated_flags.append(get_fpu_flag_name(1 << i))
-                print("\tFPU_FLAGS: %s" % (' '.join(p for p in updated_flags)))
-                break
-
-        if not updated_flags:
-            for i in range(64):
-                if insn.eflags & (1 << i):
-                    updated_flags.append(get_eflag_name(1 << i))
-            print("\tEFLAGS: %s" % (' '.join(p for p in updated_flags)))
-        
-
-# ## Test class Cs
-def test_class():
-
-    for (arch, mode, code, comment, syntax) in all_tests:
-        print("*" * 16)
-        print("Platform: %s" % comment)
-        print("Code: %s" % to_hex(code))
-        print("Disasm:")
-
-        try:
-            md = Cs(arch, mode)
-            md.detail = True
-
-            if syntax is not None:
-                md.syntax = syntax
-
-            for insn in md.disasm(code, 0x1000):
-                print_insn_detail(mode, insn)
-                print ()
-            print ("0x%x:\n" % (insn.address + insn.size))
-        except CsError as e:
-            print("ERROR: %s" % e)
-
-
-if __name__ == '__main__':
-    test_class()
diff --git a/bindings/python/tests/test_xcore.py b/bindings/python/tests/test_xcore.py
deleted file mode 100755
index 628a5a0c8..000000000
--- a/bindings/python/tests/test_xcore.py
+++ /dev/null
@@ -1,70 +0,0 @@
-#!/usr/bin/env python3
-
-# Capstone Python bindings, by Nguyen Anh Quynnh <aquynh@gmail.com>
-
-from capstone import *
-from capstone.xcore import *
-from xprint import to_x, to_hex
-
-
-XCORE_CODE = b"\xfe\x0f\xfe\x17\x13\x17\xc6\xfe\xec\x17\x97\xf8\xec\x4f\x1f\xfd\xec\x37\x07\xf2\x45\x5b\xf9\xfa\x02\x06\x1b\x10\x09\xfd\xec\xa7"
-
-all_tests = (
-        (CS_ARCH_XCORE, 0, XCORE_CODE, "XCore"),
-)
-
-
-def print_insn_detail(insn):
-    # print address, mnemonic and operands
-    print("0x%x:\t%s\t%s" % (insn.address, insn.mnemonic, insn.op_str))
-
-    # "data" instruction generated by SKIPDATA option has no detail
-    if insn.id == 0:
-        return
-
-    if len(insn.operands) > 0:
-        print("\top_count: %u" % len(insn.operands))
-        c = 0
-        for i in insn.operands:
-            if i.type == XCORE_OP_REG:
-                print("\t\toperands[%u].type: REG = %s" % (c, insn.reg_name(i.reg)))
-            if i.type == XCORE_OP_IMM:
-                print("\t\toperands[%u].type: IMM = 0x%s" % (c, to_x(i.imm)))
-            if i.type == XCORE_OP_MEM:
-                print("\t\toperands[%u].type: MEM" % c)
-                if i.mem.base != 0:
-                    print("\t\t\toperands[%u].mem.base: REG = %s" \
-                        % (c, insn.reg_name(i.mem.base)))
-                if i.mem.index != 0:
-                    print("\t\t\toperands[%u].mem.index: REG = %s" \
-                        % (c, insn.reg_name(i.mem.index)))
-                if i.mem.disp != 0:
-                    print("\t\t\toperands[%u].mem.disp: 0x%s" \
-                        % (c, to_x(i.mem.disp)))
-                if i.mem.direct != 1:
-                    print("\t\t\toperands[%u].mem.direct: -1" % c)
-            c += 1
-
-
-# ## Test class Cs
-def test_class():
-
-    for (arch, mode, code, comment) in all_tests:
-        print("*" * 16)
-        print("Platform: %s" %comment)
-        print("Code: %s" % to_hex(code))
-        print("Disasm:")
-
-        try:
-            md = Cs(arch, mode)
-            md.detail = True
-            for insn in md.disasm(code, 0x1000):
-                print_insn_detail(insn)
-                print ()
-            print("0x%x:\n" % (insn.address + insn.size))
-        except CsError as e:
-            print("ERROR: %s" %e)
-
-
-if __name__ == '__main__':
-    test_class()
diff --git a/config.mk b/config.mk
index 5d5ac6369..fa2699729 100644
--- a/config.mk
+++ b/config.mk
@@ -1,5 +1,5 @@
 # This file contains all customized compile options for Capstone.
-# Consult COMPILE.TXT & docs/README for details.
+# Consult COMPILE_MAKE.TXT & docs/README for details.
 
 ################################################################################
 # Specify which archs you want to compile in. By default, we build all archs.
diff --git a/cs.c b/cs.c
index 2c02d9da8..4bb739a40 100644
--- a/cs.c
+++ b/cs.c
@@ -1110,9 +1110,8 @@ cs_err CAPSTONE_API cs_option(csh ud, cs_opt_type type, size_t value)
 			}
 			break;
 		case CS_OPT_NO_BRANCH_OFFSET:
-			if (handle->PrintBranchImmNotAsAddress)
-				return CS_ERR_OK;
-			break;
+			handle->PrintBranchImmNotAsAddress = value == CS_OPT_ON ? true : false;
+			return CS_ERR_OK;
 	}
 
 	if (!arch_configs[handle->arch].arch_option)
diff --git a/cstool/cstool_aarch64.c b/cstool/cstool_aarch64.c
index 7a55fa12f..294193a58 100644
--- a/cstool/cstool_aarch64.c
+++ b/cstool/cstool_aarch64.c
@@ -66,14 +66,14 @@ void print_insn_detail_aarch64(csh handle, cs_insn *ins)
 				printf("\t\toperands[%u].sme.tile: %s\n", i, cs_reg_name(handle, op->sme.tile));
 			if (op->sme.slice_reg != AARCH64_REG_INVALID)
 				printf("\t\toperands[%u].sme.slice_reg: %s\n", i, cs_reg_name(handle, op->sme.slice_reg));
-			if (op->sme.slice_offset.imm != -1 || op->sme.slice_offset.imm_range.first != -1) {
+			if (op->sme.slice_offset.imm != AARCH64_SLICE_IMM_INVALID || op->sme.slice_offset.imm_range.first != AARCH64_SLICE_IMM_RANGE_INVALID) {
 				printf("\t\toperands[%u].sme.slice_offset: ", i);
 				if (op->sme.has_range_offset)
 					printf("%hhd:%hhd\n", op->sme.slice_offset.imm_range.first, op->sme.slice_offset.imm_range.offset);
 				else
 					printf("%d\n", op->sme.slice_offset.imm);
 			}
-			if (op->sme.slice_reg != AARCH64_REG_INVALID || op->sme.slice_offset.imm != -1)
+			if (op->sme.slice_reg != AARCH64_REG_INVALID || op->sme.slice_offset.imm != AARCH64_SLICE_IMM_INVALID)
 				printf("\t\toperands[%u].sme.is_vertical: %s\n", i, (op->sme.is_vertical ? "true" : "false"));
 			break;
 		case AARCH64_OP_PRED:
diff --git a/include/capstone/aarch64.h b/include/capstone/aarch64.h
index 034a120e4..e25ca28a8 100644
--- a/include/capstone/aarch64.h
+++ b/include/capstone/aarch64.h
@@ -1965,7 +1965,7 @@ typedef enum {
 
 	// clang-format on
 	// generated content <AArch64GenCSSystemOperandsEnum.inc:GET_ENUM_VALUES_TSB> end
-	AArch64_TSB_ENDING,
+	AARCH64_TSB_ENDING,
 } aarch64_tsb;
 
 typedef union {
@@ -2788,9 +2788,12 @@ typedef enum {
 	AARCH64_SME_OP_TILE_VEC, ///< SME operand is a tile indexed by a register and/or immediate
 } aarch64_sme_op_type;
 
+#define AARCH64_SLICE_IMM_INVALID UINT16_MAX
+#define AARCH64_SLICE_IMM_RANGE_INVALID UINT8_MAX
+
 typedef struct {
-	int8_t first;
-	int8_t offset;
+	uint8_t first;
+	uint8_t offset;
 } aarch64_imm_range;
 
 /// SME Instruction's matrix operand
@@ -2799,9 +2802,9 @@ typedef struct {
   aarch64_reg tile; ///< Matrix tile register
   aarch64_reg slice_reg; ///< slice index reg
 	union {
-		int8_t imm;
-		aarch64_imm_range imm_range;
-	} slice_offset; ///< slice index offset. Is set to -1 if invalid.
+		uint16_t imm; ///< Invalid if equal to AARCH64_SLICE_IMM_INVALID
+		aarch64_imm_range imm_range; ///< Members are set to AARCH64_SLICE_IMM_RANGE_INVALID if invalid.
+	} slice_offset; ///< slice index offset.
 	bool has_range_offset; ///< If true, the offset is a range.
   bool is_vertical;	///< Flag if slice is vertical or horizontal
 } aarch64_op_sme;
diff --git a/include/capstone/alpha.h b/include/capstone/alpha.h
index 60932d0fd..839ce02b4 100644
--- a/include/capstone/alpha.h
+++ b/include/capstone/alpha.h
@@ -299,4 +299,4 @@ typedef enum alpha_insn_group {
 }
 #endif
 
-#endif
\ No newline at end of file
+#endif
diff --git a/include/capstone/arm.h b/include/capstone/arm.h
index 1fc608eb0..3824da447 100644
--- a/include/capstone/arm.h
+++ b/include/capstone/arm.h
@@ -903,7 +903,7 @@ typedef struct cs_arm {
 	ARMVCC_VPTCodes vcc;	///< Vector conditional code for this instruction.
 	bool update_flags;	///< does this insn update flags?
 	bool post_index;	///< only set if writeback is 'True', if 'False' pre-index, otherwise post.
-	int /* arm_mem_bo_opt */ mem_barrier;	///< Option for some memory barrier instructions
+	arm_mem_bo_opt mem_barrier; ///< Option for some memory barrier instructions
 	// Check ARM_PredBlockMask for encoding details.
 	uint8_t /* ARM_PredBlockMask */ pred_mask;	///< Used by IT/VPT block instructions.
 	/// Number of operands of this instruction,
diff --git a/include/capstone/arm64.h b/include/capstone/arm64.h
index 600b55b97..f7a5ca27f 100644
--- a/include/capstone/arm64.h
+++ b/include/capstone/arm64.h
@@ -1863,7 +1863,7 @@ typedef enum {
 
 	ARM64_TSB_CSYNC = AARCH64_TSB_CSYNC,
 
-	ARM64_TSB_ENDING = AArch64_TSB_ENDING,
+	ARM64_TSB_ENDING = AARCH64_TSB_ENDING,
 } arm64_tsb;
 
 typedef aarch64_sysop_reg arm64_sysop_reg;
diff --git a/include/capstone/capstone.h b/include/capstone/capstone.h
index f40774d03..7de50bfd1 100644
--- a/include/capstone/capstone.h
+++ b/include/capstone/capstone.h
@@ -284,7 +284,7 @@ typedef enum cs_opt_type {
 	CS_OPT_SKIPDATA_SETUP, ///< Setup user-defined function for SKIPDATA option
 	CS_OPT_MNEMONIC,       ///< Customize instruction mnemonic
 	CS_OPT_UNSIGNED,       ///< print immediate operands in unsigned form
-	CS_OPT_NO_BRANCH_OFFSET, ///< ARM, prints branch immediates without offset.
+	CS_OPT_NO_BRANCH_OFFSET, ///< ARM, PPC, AArch64, prints branch immediates without offset.
 } cs_opt_type;
 
 /// Runtime option value (associated with option type above)
@@ -302,6 +302,12 @@ typedef enum cs_opt_value {
 	CS_OPT_DETAIL_REAL = 1 << 1, ///< If enabled, always sets the real instruction detail. Even if the instruction is an alias.
 } cs_opt_value;
 
+/// An option
+typedef struct {
+	cs_opt_type type; ///< The option type
+	cs_opt_value val; ///< The option value to set.
+} cs_opt;
+
 /// Common instruction groups - to be consistent across all architectures.
 typedef enum cs_group_type {
 	CS_GRP_INVALID = 0,  ///< uninitialized/invalid group.
diff --git a/include/capstone/hppa.h b/include/capstone/hppa.h
index 1fa66be63..fffb6ef73 100644
--- a/include/capstone/hppa.h
+++ b/include/capstone/hppa.h
@@ -540,4 +540,4 @@ typedef enum hppa_insn_group {
 }
 #endif
 
-#endif
\ No newline at end of file
+#endif
diff --git a/include/capstone/ppc.h b/include/capstone/ppc.h
index f308b4df2..2b04b7a91 100644
--- a/include/capstone/ppc.h
+++ b/include/capstone/ppc.h
@@ -3280,6 +3280,8 @@ typedef enum ppc_insn_group {
 /// PPC instruction formats. To get details about them please
 /// refer to `PPCInstrFormats.td` in LLVM.
 typedef enum {
+	PPC_INSN_FORM_INVALID = 0,
+
 	// generated content <PPCGenCSInsnFormatsEnum.inc> begin
 	// clang-format off
 
diff --git a/include/capstone/sparc.h b/include/capstone/sparc.h
index e33d17391..f09b5ca7e 100644
--- a/include/capstone/sparc.h
+++ b/include/capstone/sparc.h
@@ -64,6 +64,8 @@ typedef enum sparc_hint {
 	SPARC_HINT_A	= 1 << 0,	///< annul delay slot instruction
 	SPARC_HINT_PT	= 1 << 1,	///< branch taken
 	SPARC_HINT_PN	= 1 << 2,	///< branch NOT taken
+	SPARC_HINT_A_PN	= SPARC_HINT_A | SPARC_HINT_PN,
+	SPARC_HINT_A_PT	= SPARC_HINT_A | SPARC_HINT_PT,
 } sparc_hint;
 
 /// Operand type for instruction's operands
diff --git a/include/capstone/x86.h b/include/capstone/x86.h
index b6b56c050..1761cc4e0 100644
--- a/include/capstone/x86.h
+++ b/include/capstone/x86.h
@@ -246,6 +246,7 @@ typedef enum x86_avx_rm {
 
 /// Instruction prefixes - to be used in cs_x86.prefix[]
 typedef enum x86_prefix {
+	X86_PREFIX_0		=	0x0,
 	X86_PREFIX_LOCK		= 	0xf0,	///< lock (cs_x86.prefix[0]
 	X86_PREFIX_REP		= 	0xf3,	///< rep (cs_x86.prefix[0]
 	X86_PREFIX_REPE		= 	0xf3,	///< repe/repz (cs_x86.prefix[0]
diff --git a/run-clang-tidy.sh b/run-clang-tidy.sh
index 9178f72e2..6f71db8d3 100755
--- a/run-clang-tidy.sh
+++ b/run-clang-tidy.sh
@@ -18,10 +18,12 @@ BUILD_PATH="$1"
 
 check_list="clang-analyzer-*,-clang-analyzer-cplusplus*,-clang-analyzer-optin.performance.Padding"
 
-if $(hash clang-tidy-15); then
-  clang-tidy-15 $(find ./arch ./*.c -type f -iregex ".*\.[c]") -p "$BUILD_PATH" -checks="$check_list" > ct-warnings.txt
+if $(hash clang-tidy-18); then
+  echo -e "#############\nProduced by\n$(clang-tidy-18 --version)\n#############\n\n" > ct-warnings.txt
+  clang-tidy-18 $(find ./arch ./*.c -type f -iregex ".*\.[c]") -p "$BUILD_PATH" -checks="$check_list" >> ct-warnings.txt
 else
-  clang-tidy $(find ./arch ./*.c -type f -iregex ".*\.[c]") -p "$BUILD_PATH" -checks="$check_list" > ct-warnings.txt
+  echo -e "#############\nProduced by\n$(clang-tidy --version)\n#############\n\n" > ct-warnings.txt
+  clang-tidy $(find ./arch ./*.c -type f -iregex ".*\.[c]") -p "$BUILD_PATH" -checks="$check_list" >> ct-warnings.txt
 fi
 
 if [ $? -ne 0 ]; then
diff --git a/suite/MC/README b/suite/MC/README
deleted file mode 100644
index 6f2555e04..000000000
--- a/suite/MC/README
+++ /dev/null
@@ -1,47 +0,0 @@
-## Input files for testing Capstone engine.
-
-Input files used to test instructions of architectures and modes.
-
-The test cases are taken from `llvm/test/MC`. Note that most of the LLVM tests
-are for **encoding** of instructions (`asm_string -> bytes`).
-
-We test the decoding (`bytes -> asm_string`).
-A few tests might decode to a different asm string than
-used to encode the instruction (because the behavior
-of instructions can be equivalent).
-
-Fix the obvious broken tests first and test the rest
-against `llvm-objdump`.
-
-### Update test files
-
-Check `suite/auto-sync/README.md`
-
-### Test file formatting
-
-**Format of input files:**
-```
-# ARCH, MODE, OPTION
-hexcode = assembly
-```
-
-**Example**
-```
-# CS_ARCH_ARM, CS_MODE_ARM+CS_MODE_V8, None
-0xa0,0x0b,0x71,0xee = vadd.f64 d16, d17, d16
-...
-```
-
-**Format of issue file:**
-
-```
-!# ARCH, MODE, OPTION
-hexcode = assembly | regs_read | regs_read_count | regs_write | regs_write_count | groups | groups_count
-```
-
-**Example**
-```
-!# CS_ARCH_ARM64, CS_MODE_ARM, CS_OPT_DETAIL
-0xc0,0x1e,0x0c,0x4e == mov v0.s[1], w22 ; operands[0].vas: 0xb ; operands[0].vector_index: 1
-...
-```
diff --git a/suite/MC/README.md b/suite/MC/README.md
new file mode 100644
index 000000000..d86ea1992
--- /dev/null
+++ b/suite/MC/README.md
@@ -0,0 +1,19 @@
+# Input files for fuzzing input
+
+These files were the legacy test files but replaced.
+No it only is consumed by `test_corpus3.py` to generate input cases for the fuzzer.
+
+### Test file formatting
+
+**Format of input files:**
+```
+# ARCH, MODE, OPTION
+<hexcode> = <assembly-text>
+```
+
+**Example**
+```
+# CS_ARCH_ARM, CS_MODE_ARM+CS_MODE_V8, None
+0xa0,0x0b,0x71,0xee = vadd.f64 d16, d17, d16
+...
+```
diff --git a/suite/README b/suite/README
index fc9b59a58..e501632f1 100644
--- a/suite/README
+++ b/suite/README
@@ -2,20 +2,9 @@ This directory contains some tools used by developers of Capstone project.
 Average users should ignore all the contents here.
 
 
-- arm/
-	Test some ARM's special input.
-
-- MC/
-	Input used to test various architectures & modes.
-
 - benchmark.py
 	This script benchmarks Python binding by disassembling some random code.
 
-- test_*.sh
-	Run all the tests and send the output to external file to be compared later.
-	This is useful when we want to verify if a commit (wrongly) changes
-	the disassemble result.
-
 - compile_all.sh
 	Compile Capstone for all platforms (*nix32, clang, cygwin, cross-compile) &
 	report the result as pass or fail.
@@ -24,10 +13,6 @@ Average users should ignore all the contents here.
 	This simple script disassembles random code for all archs (or selected arch)
 	in order to find segfaults.
 
-- test_mc.sh
-    This script compares the output of Capstone with LLVM's llvm-mc with the
-	input coming from MC/. This relies on test_mc.py to do all the hard works.
-
 - x86odd.py
 	Test some tricky X86 instructions.
 
diff --git a/suite/arm/Makefile b/suite/arm/Makefile
deleted file mode 100644
index aaf4d05d7..000000000
--- a/suite/arm/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-# Sample Makefile for Capstone Disassembly Engine
-
-LIBNAME = capstone
-
-test_arm_regression: test_arm_regression.o
-	${CC} $< -O3 -Wall -l$(LIBNAME) -o $@
-
-%.o: %.c
-	${CC} -c -I../../include $< -o $@
-
-clean:
-	rm -rf *.o test_arm_regression
diff --git a/suite/arm/test_arm_regression.c b/suite/arm/test_arm_regression.c
deleted file mode 100644
index fade56b49..000000000
--- a/suite/arm/test_arm_regression.c
+++ /dev/null
@@ -1,391 +0,0 @@
-/* Capstone Disassembler Engine */
-/* By David Hogarty, 2014 */
-
-// the following must precede stdio (woo, thanks msft)
-#if defined(_MSC_VER) && _MSC_VER < 1900
-#define _CRT_SECURE_NO_WARNINGS
-#define snprintf _snprintf
-#endif
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include <capstone/platform.h>
-#include <capstone/capstone.h>
-
-static csh handle;
-
-struct platform {
-	cs_arch arch;
-	cs_mode mode;
-	unsigned char *code;
-	size_t size;
-	char *comment;
-	int syntax;
-};
-
-static char *hex_string(unsigned char *str, size_t len)
-{
-	// returns a malloced string that has the hex version of the string in it
-	// null if failed to malloc
-	char *hex_out;
-	size_t i;
-
-	hex_out = (char *) malloc(len*2 + 1); // two ascii characters per input character, plus trailing null
-	if (!hex_out) { goto Exit; }
-
-	for (i = 0; i < len; ++i) {
-		snprintf(hex_out + (i * 2), 3, "%02x", str[i]);
-	}
-
-	hex_out[len*2] = 0; // trailing null
-
-Exit:
-	return hex_out;
-}
-
-static void snprint_insn_detail(char * buf, size_t * cur, size_t * left, cs_insn *ins)
-{
-#define _this_printf(...) \
-	{ \
-		size_t used = 0; \
-		used = snprintf(buf + *cur, *left, __VA_ARGS__); \
-		*left -= used; \
-		*cur += used; \
-	}
-
-	cs_arm *arm;
-	int i;
-
-	// detail can be NULL on "data" instruction if SKIPDATA option is turned ON
-	if (ins->detail == NULL)
-		return;
-
-	arm = &(ins->detail->arm);
-
-	if (arm->op_count)
-		_this_printf("\top_count: %u\n", arm->op_count);
-
-	for (i = 0; i < arm->op_count; i++) {
-		cs_arm_op *op = &(arm->operands[i]);
-		switch((int)op->type) {
-			default:
-				break;
-			case ARM_OP_REG:
-				_this_printf("\t\toperands[%u].type: REG = %s\n", i, cs_reg_name(handle, op->reg));
-				break;
-			case ARM_OP_IMM:
-				_this_printf("\t\toperands[%u].type: IMM = 0x%" PRIx64 "\n", i, op->imm);
-				break;
-			case ARM_OP_FP:
-				_this_printf("\t\toperands[%u].type: FP = %f\n", i, op->fp);
-				break;
-			case ARM_OP_MEM:
-				_this_printf("\t\toperands[%u].type: MEM\n", i);
-				if (op->mem.base != ARM_REG_INVALID)
-					_this_printf("\t\t\toperands[%u].mem.base: REG = %s\n",
-							i, cs_reg_name(handle, op->mem.base));
-				if (op->mem.index != ARM_REG_INVALID)
-					_this_printf("\t\t\toperands[%u].mem.index: REG = %s\n",
-							i, cs_reg_name(handle, op->mem.index));
-				if (op->mem.scale != 1)
-					_this_printf("\t\t\toperands[%u].mem.scale: %u\n", i, op->mem.scale);
-				if (op->mem.disp != 0)
-					_this_printf("\t\t\toperands[%u].mem.disp: 0x%x\n", i, op->mem.disp);
-
-				break;
-			case ARM_OP_PIMM:
-				_this_printf("\t\toperands[%u].type: P-IMM = %" PRIu64 "\n", i, op->imm);
-				break;
-			case ARM_OP_CIMM:
-				_this_printf("\t\toperands[%u].type: C-IMM = %" PRIu64 "\n", i, op->imm);
-				break;
-		}
-
-		if (op->shift.type != ARM_SFT_INVALID && op->shift.value) {
-			if (op->shift.type < ARM_SFT_ASR_REG) {
-				// shift with constant value
-				_this_printf("\t\t\tShift: %u = %u\n", op->shift.type, op->shift.value);
-			} else {
-				// shift with register
-				_this_printf("\t\t\tShift: %u = %s\n", op->shift.type,
-						cs_reg_name(handle, op->shift.value));
-			}
-		}
-	}
-
-	if (arm->cc != ARMCC_AL && arm->cc != ARMCC_UNDEF) {
-		_this_printf("\tCode condition: %u\n", arm->cc);
-	}
-
-	if (arm->update_flags) {
-		_this_printf("\tUpdate-flags: True\n");
-	}
-
-	if (ins->detail->writeback) {
-		_this_printf("\tWrite-back: True\n");
-	}
-
-#undef _this_printf
-}
-
-static void print_insn_detail(cs_insn *ins)
-{
-	char a_buf[2048];
-	size_t cur=0, left=2048;
-	snprint_insn_detail(a_buf, &cur, &left, ins);
-	printf("%s\n", a_buf);
-}
-
-struct invalid_code {
-	unsigned char *code;
-	size_t size;
-	char *comment;
-};
-
-#define MAX_INVALID_CODES 16
-
-struct invalid_instructions {
-	cs_arch arch;
-	cs_mode mode;
-	char *platform_comment;
-	int num_invalid_codes;
-	struct invalid_code invalid_codes[MAX_INVALID_CODES]; 
-};
-
-static void test_invalids()
-{
-	struct invalid_instructions invalids[] = {{
-		CS_ARCH_ARM,
-			CS_MODE_THUMB,
-			"Thumb",
-			1,
-			{{
-				 (unsigned char *)"\xbd\xe8\x1e\xff",
-				 4,
-				 "invalid thumb2 pop because sp used and because both pc and lr are "
-					 "present at the same time"
-			 }},
-	}};
-
-	struct invalid_instructions * invalid = NULL;
-
-	uint64_t address = 0x1000;
-	cs_insn *insn;
-	int i;
-	int j;
-	size_t count;
-
-	printf("\nShould be invalid\n"
-			"-----------------\n");
-
-	for (i = 0; i < sizeof(invalids)/sizeof(invalids[0]); i++) {
-		cs_err err;
-
-		invalid = invalids + i;
-		err = cs_open(invalid->arch, invalid->mode, &handle);
-
-		if (err) {
-			printf("Failed on cs_open() with error returned: %u\n", err);
-			continue;
-		}
-
-		cs_option(handle, CS_OPT_DETAIL, CS_OPT_ON);
-		cs_option(handle, CS_OPT_SYNTAX, CS_OPT_SYNTAX_NOREGNAME);
-
-		for (j = 0; j < invalid->num_invalid_codes; ++j) {
-			struct invalid_code *invalid_code = NULL;
-			char *hex_str = NULL;
-
-			invalid_code = invalid->invalid_codes + j;
-
-			hex_str = hex_string(invalid_code->code, invalid_code->size);
-
-			printf("%s %s: %s\n", invalid->platform_comment, hex_str, invalid_code->comment);
-
-			free(hex_str);
-
-			count = cs_disasm(handle,
-					invalid_code->code, invalid_code->size, address, 0, &insn
-					);
-
-			if (count) {
-				size_t k;
-				printf("    ERROR:\n");
-
-				for (k = 0; k < count; k++) {
-					printf("    0x%"PRIx64":\t%s\t%s\n", 
-							insn[k].address, insn[k].mnemonic, insn[k].op_str);
-					print_insn_detail(&insn[k]);
-				}
-				cs_free(insn, count);
-
-			} else {
-				printf("    SUCCESS: invalid\n");
-			}
-		}
-
-		cs_close(&handle);
-	}
-}
-
-struct valid_code {
-	unsigned char *code;
-	size_t size;
-	uint32_t start_addr;
-	char *expected_out;
-	char *comment;
-};
-
-#define MAX_VALID_CODES 16
-struct valid_instructions {
-	cs_arch arch;
-	cs_mode mode;
-	char *platform_comment;
-	int num_valid_codes;
-	struct valid_code valid_codes[MAX_VALID_CODES]; 
-};
-
-static void test_valids()
-{
-	struct valid_instructions valids[] = {{
-		CS_ARCH_ARM,
-			CS_MODE_THUMB,
-			"Thumb",
-			3,
-			{{ (unsigned char *)"\x00\xf0\x26\xe8", 4, 0x352,
-				"0x352:\tblx\t#0x3a0\n"
-					"\top_count: 1\n"
-					"\t\toperands[0].type: IMM = 0x3a0\n",
-
-				"thumb2 blx with misaligned immediate"
-			}, { (unsigned char *)"\x05\xdd", 2, 0x1f0,
-				"0x1f0:\tble\t#0x1fe\n"
-					"\top_count: 1\n"
-					"\t\toperands[0].type: IMM = 0x1fe\n"
-					"\tCode condition: 14\n",
-
-				"thumb b cc with thumb-aligned target"
-			}, { (unsigned char *)"\xbd\xe8\xf0\x8f", 4, 0,
-			 "0x0:\tpop.w\t{r4, r5, r6, r7, r8, r9, r10, r11, pc}\n"
-				 "\top_count: 9\n"
-				 "\t\toperands[0].type: REG = r4\n"
-				 "\t\toperands[1].type: REG = r5\n"
-				 "\t\toperands[2].type: REG = r6\n"
-				 "\t\toperands[3].type: REG = r7\n"
-				 "\t\toperands[4].type: REG = r8\n"
-				 "\t\toperands[5].type: REG = r9\n"
-				 "\t\toperands[6].type: REG = r10\n"
-				 "\t\toperands[7].type: REG = r11\n"
-				 "\t\toperands[8].type: REG = pc\n",
-
-				"thumb2 pop that should be valid"
-			},
-		}
-	}};
-
-	struct valid_instructions *valid = NULL;
-
-	cs_insn *insn;
-	int i;
-	int j;
-	size_t count;
-
-
-	for (i = 0; i < sizeof(valids)/sizeof(valids[0]); i++) {
-		cs_err err;
-
-		valid = valids + i;
-		err = cs_open(valid->arch, valid->mode, &handle);
-
-		if (err) {
-			printf("Failed on cs_open() with error returned: %u\n", err);
-			continue;
-		}
-
-		cs_option(handle, CS_OPT_DETAIL, CS_OPT_ON);
-		cs_option(handle, CS_OPT_SYNTAX, CS_OPT_SYNTAX_NOREGNAME);
-
-#define _this_printf(...) \
-		{ \
-			size_t used = 0; \
-			used = snprintf(tmp_buf + cur, left, __VA_ARGS__); \
-			left -= used; \
-			cur += used; \
-		}
-		printf("\nShould be valid\n"
-				"---------------\n");
-
-		for (j = 0; j < valid->num_valid_codes; ++j) {
-			char tmp_buf[2048];
-			size_t left = 2048;
-			size_t cur = 0;
-			char * hex_str = NULL;
-
-			struct valid_code * valid_code = NULL;
-			valid_code = valid->valid_codes + j;
-
-			hex_str = hex_string(valid_code->code, valid_code->size);
-
-			printf("%s %s @ 0x%04x: %s\n    %s", 
-					valid->platform_comment, hex_str, valid_code->start_addr, 
-					valid_code->comment, valid_code->expected_out);
-
-			free(hex_str);
-
-			count = cs_disasm(handle,
-					valid_code->code, valid_code->size, 
-					valid_code->start_addr, 0, &insn
-					);
-
-			if (count) {
-				size_t k;
-				size_t max_len = 0;
-				size_t tmp_len = 0;
-
-				for (k = 0; k < count; k++) {
-					_this_printf(
-							"0x%"PRIx64":\t%s\t%s\n", 
-							insn[k].address, insn[k].mnemonic, 
-							insn[k].op_str
-							);
-
-					snprint_insn_detail(tmp_buf, &cur, &left, &insn[k]);
-				}
-
-				max_len = strlen(tmp_buf);
-				tmp_len = strlen(valid_code->expected_out);
-				if (tmp_len > max_len) {
-					max_len = tmp_len;
-				}
-
-				if (memcmp(tmp_buf, valid_code->expected_out, max_len)) {
-					printf(
-						"    ERROR: '''\n%s''' does not match"
-						" expected '''\n%s'''\n", 
-						tmp_buf, valid_code->expected_out
-					);
-				} else {
-					printf("    SUCCESS: valid\n");
-				}
-
-				cs_free(insn, count);
-
-			} else {
-				printf("ERROR: invalid\n");
-			}
-		}
-
-		cs_close(&handle);
-	}
-
-#undef _this_prinf
-}
-
-int main()
-{
-	test_invalids();
-	test_valids();
-	return 0;
-}
-
diff --git a/suite/auto-sync/.gitignore b/suite/auto-sync/.gitignore
index fca115d2e..95a3a6a43 100644
--- a/suite/auto-sync/.gitignore
+++ b/suite/auto-sync/.gitignore
@@ -4,4 +4,9 @@ vendor/llvm_root
 src/auto-sync/config.json
 src/autosync/cpptranslator/Tests/Differ/test_saved_patches.json
 src/autosync.egg-info
-
+src/autosync/Tests/MCUpdaterTests/ARCH/Output
+src/autosync/Tests/MCUpdaterTests/Disassembler/ARCH/Output
+src/autosync/lit_config/test_dir_*
+src/autosync/lit_config/.lit_test_times.txt
+src/autosync/Tests/MCUpdaterTests/test_output
+src/autosync/Tests/MCUpdaterTests/ARCH/Output
diff --git a/suite/auto-sync/README.md b/suite/auto-sync/README.md
index 5c519139c..797320936 100644
--- a/suite/auto-sync/README.md
+++ b/suite/auto-sync/README.md
@@ -15,7 +15,7 @@ Please refer to [intro.md](intro.md) for an introduction about this tool.
 
 ## Install
 
-Setup Python environment and Tree-sitter
+#### Setup Python environment and Tree-sitter
 
 ```
 cd <root-dir-Capstone>
@@ -26,13 +26,35 @@ python3 -m venv ./.venv
 source ./.venv/bin/activate
 ```
 
-Install Auto-Sync framework
+#### Install Auto-Sync framework
 
 ```
 cd suite/auto-sync/
 pip install -e .
 ```
 
+#### Clone Capstones LLVM fork and build `llvm-tblgen`
+
+```bash
+git clone https://github.com/capstone-engine/llvm-capstone vendor/llvm_root/
+cd llvm-capstone
+git checkout auto-sync
+mkdir build
+cd build
+# You can also build the "Release" version
+cmake -G Ninja -DCMAKE_BUILD_TYPE=Debug ../llvm
+cmake --build . --target llvm-tblgen --config Debug
+cd ../../
+```
+
+#### Install `llvm-mc` and `FileCheck`
+
+Additionally, we need `llvm-mc` and `FileCheck` to generate our regression tests.
+You can build it, but it will take a lot of space on your hard drive.
+You can also get the binaries [here](https://releases.llvm.org/download.html) or
+install it with your package manager (usually something like `llvm-18-dev`).
+Just ensure it is in your `PATH` as `llvm-mc` and `FileCheck` (not as `llvm-mc-18` or similar though!).
+
 ## Architecture
 
 Please read [ARCHITECTURE.md](https://github.com/capstone-engine/capstone/blob/next/docs/ARCHITECTURE.md) to understand how Auto-Sync works.
@@ -50,20 +72,6 @@ Check if your architecture is supported.
 ./src/autosync/ASUpdater.py -h
 ```
 
-Clone Capstones LLVM fork and build `llvm-tblgen`
-
-```
-git clone https://github.com/capstone-engine/llvm-capstone vendor/llvm_root/
-cd llvm-capstone
-git checkout auto-sync
-mkdir build
-cd build
-# You can also build the "Release" version
-cmake -G Ninja -DCMAKE_BUILD_TYPE=Debug ../llvm
-cmake --build . --target llvm-tblgen --config Debug
-cd ../../
-```
-
 Run the updater
 
 ```
diff --git a/suite/auto-sync/c_tests/CMakeLists.txt b/suite/auto-sync/c_tests/CMakeLists.txt
new file mode 100644
index 000000000..ae54d3101
--- /dev/null
+++ b/suite/auto-sync/c_tests/CMakeLists.txt
@@ -0,0 +1,16 @@
+cmake_minimum_required(VERSION 3.15)
+
+set(AUTO_SYNC_C_TEST_SRC_DIR ${AUTO_SYNC_C_TEST_DIR}/src)
+set(AUTO_SYNC_C_TEST_INC_DIR ${AUTO_SYNC_C_TEST_DIR}/include)
+
+include_directories(${AUTO_SYNC_C_TEST_INC_DIR} ${PROJECT_SOURCE_DIR}/include)
+
+file(GLOB AUTO_SYNC_C_SRC ${AUTO_SYNC_C_TEST_SRC_DIR}/*.c)
+add_executable(compat_header_build_test ${AUTO_SYNC_C_SRC})
+add_dependencies(compat_header_build_test capstone)
+target_link_libraries(compat_header_build_test PUBLIC capstone)
+
+add_test(NAME ASCompatibilityHeaderTest
+  COMMAND compat_header_build_test
+  WORKING_DIRECTORY ${AUTO_SYNC_C_TEST_DIR}
+)
diff --git a/suite/auto-sync/c_tests/src/test_arm64_compatibility_header.c b/suite/auto-sync/c_tests/src/test_arm64_compatibility_header.c
index 4af052056..d1ddb8644 100644
--- a/suite/auto-sync/c_tests/src/test_arm64_compatibility_header.c
+++ b/suite/auto-sync/c_tests/src/test_arm64_compatibility_header.c
@@ -12,7 +12,7 @@ int main(void)
 	csh handle;
 
 	if (cs_open(CS_ARCH_ARM64, CS_MODE_BIG_ENDIAN, &handle) != CS_ERR_OK) {
-		printf("cs_open failed\n");
+		fprintf(stderr, "cs_open failed\n");
 		return -1;
 	}
 
@@ -20,21 +20,48 @@ int main(void)
 
 	cs_insn *insn;
 	uint8_t bytes[] = "0x1a,0x48,0xa0,0xf8";
-	size_t count = cs_disasm(handle, bytes, sizeof(bytes), 0x1000, 1, &insn);
-	if (count > 0) {
-		printf("0x%" PRIx64 ":\t%s\t\t%s\n", insn[0].address,
-		       insn[0].mnemonic, insn[0].op_str);
-		printf("A register = %s\n", cs_reg_name(handle, insn[0].detail->arm64.operands[0].reg));
-		printf("An imm = 0x%" PRIx64 "\n", insn[0].detail->arm64.operands[1].imm);
+	size_t count =
+		cs_disasm(handle, bytes, sizeof(bytes), 0x1000, 1, &insn);
+	if (count != 1) {
+		fprintf(stderr, "Failed to disassemble code.\n");
+		goto err;
+	}
+	printf("0x%" PRIx64 ":\t%s\t\t%s\n", insn[0].address, insn[0].mnemonic,
+	       insn[0].op_str);
+	printf("A register = %s\n",
+	       cs_reg_name(handle, insn[0].detail->arm64.operands[0].reg));
+	printf("An imm = 0x%" PRIx64 "\n",
+	       insn[0].detail->arm64.operands[1].imm);
 
-		cs_free(insn, count);
-	} else {
-		printf("ERROR: Failed to disassemble given code!\n");
-		cs_close(&handle);
-		return -1;
+	if (insn[0].address != 0x1000) {
+		fprintf(stderr, "Address wrong.\n");
+		goto err;
+	}
+	if (strcmp(insn[0].mnemonic, "adr") != 0) {
+		fprintf(stderr, "Mnemonic wrong.\n");
+		goto err;
+	}
+	if (strcmp(insn[0].op_str, "x1, 0xf162d") != 0) {
+		fprintf(stderr, "op_str wrong.\n");
+		goto err;
+	}
+	if (strcmp(cs_reg_name(handle, insn[0].detail->arm64.operands[0].reg),
+		   "x1") != 0) {
+		fprintf(stderr, "register wrong.\n");
+		goto err;
+	}
+	if (insn[0].detail->arm64.operands[1].imm != 0xf162d) {
+		fprintf(stderr, "Immediate wrong.\n");
+		goto err;
 	}
 
+	cs_free(insn, count);
 	cs_close(&handle);
-
 	return 0;
+
+err:
+	printf("ERROR: Failed to disassemble given code corrcetly!\n");
+	cs_free(insn, count);
+	cs_close(&handle);
+	return -1;
 }
diff --git a/suite/auto-sync/format_py.sh b/suite/auto-sync/format_py.sh
index b5fc2c64f..53e056995 100755
--- a/suite/auto-sync/format_py.sh
+++ b/suite/auto-sync/format_py.sh
@@ -1,3 +1,3 @@
 #!/usr/bin/bash
 
-python3.11 -m black src/autosync
+python3 -m black src/autosync
diff --git a/suite/auto-sync/pyproject.toml b/suite/auto-sync/pyproject.toml
index bc7729831..907d88ada 100644
--- a/suite/auto-sync/pyproject.toml
+++ b/suite/auto-sync/pyproject.toml
@@ -7,15 +7,15 @@ name = "autosync"
 version = "0.1.0"
 dependencies = [
   "termcolor >= 2.3.0",
-  "tree_sitter >= 0.21.3",
+  "tree_sitter == 0.22.3",
   "tree-sitter-cpp >=0.22.0",
   "black >= 24.3.0",
   "usort >= 1.0.8",
   "setuptools >= 69.2.0",
   "ninja >= 1.11.1.1",
-  "cmake >= 3.28.3",
   "reuse >= 3.0.1",
   "clang-format >= 18.1.1",
+  "lit >= 18.1.8",
 ]
 requires-python = ">= 3.11"
 
diff --git a/suite/auto-sync/src/autosync/ASUpdater.py b/suite/auto-sync/src/autosync/ASUpdater.py
index b88c683f6..a69803001 100755
--- a/suite/auto-sync/src/autosync/ASUpdater.py
+++ b/suite/auto-sync/src/autosync/ASUpdater.py
@@ -73,7 +73,11 @@ class ASUpdater:
             self.inc_list,
         )
         self.mc_updater = MCUpdater(
-            self.arch, get_path("{LLVM_MC_TEST_DIR}"), None, None
+            self.arch,
+            get_path("{LLVM_MC_TEST_DIR}"),
+            None,
+            None,
+            True if self.arch == "ARM" else False,
         )
 
     def clean_build_dir(self) -> None:
@@ -192,6 +196,7 @@ class ASUpdater:
             log.info(f"Copied {i} files")
 
             # MC tests
+            i = 0
             mc_dir = get_path("{MC_DIR}").joinpath(self.arch)
             log.info(f"Copy MC test files to {mc_dir}")
             for file in get_path("{MCUPDATER_OUT_DIR}").iterdir():
diff --git a/suite/auto-sync/src/autosync/Helper.py b/suite/auto-sync/src/autosync/Helper.py
index 6f7b35287..b91c1cbb8 100644
--- a/suite/auto-sync/src/autosync/Helper.py
+++ b/suite/auto-sync/src/autosync/Helper.py
@@ -34,8 +34,8 @@ def find_id_by_type(node: Node, node_types: [str], type_must_match: bool) -> byt
     """
     Recursively searches for a node sequence with given node types.
 
-    A valid sequence is a path from !\f$node_n\f$ to !\f$node_{(n + |node\_types|-1)}\f$ where
-    !\f$\forall i \in \{0, ..., |node\_types|-1\}: type(node_{(n + i)}) = node\_types_i\f$.
+    A valid sequence is a path from node_n to node_{(n + |node_types|-1)} where
+    forall i in {0, ..., |node_types|-1}: type(node_{(n + i)}) = node_types_i.
 
     If a node sequence is found, this functions returns the text associated with the
     last node in the sequence.
@@ -159,6 +159,11 @@ def get_path(config_path: str) -> Path:
     return PathVarHandler().complete_path(config_path)
 
 
+def test_only_overwrite_path_var(var_name: str, new_path: Path):
+    """Don't use outside of testing."""
+    return PathVarHandler().test_only_overwrite_var(var_name, new_path)
+
+
 def fail_exit(msg: str) -> None:
     """Logs a fatal message and exits with error code 1."""
     log.fatal(msg)
diff --git a/suite/auto-sync/src/autosync/MCUpdater.py b/suite/auto-sync/src/autosync/MCUpdater.py
index b52ee6f66..afc64873c 100755
--- a/suite/auto-sync/src/autosync/MCUpdater.py
+++ b/suite/auto-sync/src/autosync/MCUpdater.py
@@ -1,386 +1,448 @@
 #!/usr/bin/env python3
 # Copyright © 2024 Rot127 <unisono@quyllur.org>
 # SPDX-License-Identifier: BSD-3
+
 import argparse
 import logging as log
+import json
 import re
 import sys
-from enum import Enum
+import subprocess as sp
+
 from pathlib import Path
 
+from autosync.Targets import TARGETS_LLVM_NAMING
 from autosync.Helper import convert_loglevel, get_path
 
-# The CHECK prefix for tests.
-VALID_PREFIX = r"(CHECK(-NEXT)?|FP[A-Z0-9]+)"
-CHECK = rf"((#|//)\s*{VALID_PREFIX}:)"
-ASM = r"(?P<asm_text>[^/@]+)"
-ENC = r"(\[?(?P<enc_bytes>((0x[a-fA-F0-9]{1,2}[, ]{0,2}))+)[^, ]?\]?)"
-match_patterns = {
-    # A commented encoding with only CHECK or something similar in front of it, skip it.
-    "skip_pattern": (
-        rf"(^((#|//)\s*[-A-Z0-9]+):\s*{ENC}\s*$)|" r"(warning: .*)|" r"((#\s+)?NO.+)"
-    ),
-    # The encoding bytes pattern is in every file the same.
-    # But the disassembler and assembler tests pre-fix them differently.
-    # This is only the pattern for the encoding bytes. Without any prefix.
-    #
-    # The bytes are encoded with `0x` prefix and every byte is separated with a `,` or ` `.
-    # Optionally, they are enclosed in `[0x10,...]` brackets.
-    # E.g.: `[0x01,0xaa,0xb1,0x81]` or `0x01,0xaa,0xb1,0x81`.
-    # In the disassembler tests they don't have any prefix.
-    # In assembler tests they might have different prefixes like `CHECK-ENCODING`
-    # The matched bytes can be accessed from the group "enc_bytes"
-    "enc_bytes": ENC,
-    # Encodings in disassembly tests can have several prefixes
-    "enc_prefix_disas":
-    # start of line with CHECK: ... prefix
-    r"((^\s*)|"
-    # start of line with `CHECK: ...` prefix and the encoding after the asm text.
-    rf"({CHECK}.+encoding:\s+))",
-    # The asm checking line for `MC/Disassembler/*` tests follows the pattern:
-    # `# CHECK: <asm-text>`
-    # Usually multiple 'CHECK' come before or after the encoding bytes.
-    # Meaning: first comes a block of `# CHECK: ...` and afterwards for every `# CHECK: ...`
-    # line the encoding bytes.
-    # And wise versa, with the encoding bytes first and afterwards the asm text checks.
-    # The matched asm text can be accessed from the group "asm_text"
-    "asm_check": rf"{CHECK}\s+{ASM}(\s*(#|//)\s+encoding:\s+{ENC})?",
-    # Single line disassembly test
-    "single_line_disas": rf"^{ENC}\s+#\s+{ASM}",
-    # The RUN line, with the command to run the test file, contains sometimes the `mattr` flags.
-    # These are relevant, because they enable or disable features we might need to
-    # respect in our tests as well.
-    # The matched `mattr` cmd line option (if any) can be accessed from the group `mattr`
-    "run_line": r"RUN:.*(?P<mattr>mattr=[^ ]+).+",
-}
+
+class LLVM_MC_Command:
+    def __init__(self, cmd_line: str, mattr: str):
+        self.cmd: str = ""
+        self.opts: str = ""
+        self.file: Path | None = None
+        self.mattr: str = mattr
+
+        self.cmd, self.opts, self.file = self.parse_llvm_mc_line(cmd_line)
+        if not (self.cmd and self.opts and self.file):
+            log.warning(f"Could not parse llvm-mc command: {cmd_line}")
+        elif not "--show-encoding" in self.cmd:
+            self.cmd = re.sub("llvm-mc", "llvm-mc --show-encoding", self.cmd)
+
+    def parse_llvm_mc_line(self, line: str) -> tuple[str, str, Path]:
+        test_file_base_dir = str(get_path("{LLVM_LIT_TEST_DIR}").absolute())
+        file = re.findall(rf"{test_file_base_dir}\S+", line)
+        if not file:
+            log.warning(f"llvm-mc command doesn't contain a file: {line}")
+            return None, None, None
+        test_file = file[0]
+        cmd = re.sub(rf"{test_file}", "", line).strip()
+        cmd = re.sub(r"\s+", " ", cmd)
+        arch = re.finditer(r"(triple|arch)[=\s](\S+)", cmd)
+        mattr = re.finditer(r"(mattr|mcpu)[=\s](\S+)", cmd)
+        opts = ",".join([m.group(2) for m in arch]) if arch else ""
+        if mattr:
+            opts += "" if not opts else ","
+            opts += ",".join([m.group(2).strip("+") for m in mattr])
+        return cmd, opts, Path(test_file)
+
+    def exec(self) -> sp.CompletedProcess:
+        with open(self.file, "b+r") as f:
+            content = f.read()
+        if self.mattr:
+            # If mattr exists, patch it into the cmd
+            if "mattr" in self.cmd:
+                self.cmd = re.sub(
+                    r"mattr[=\s]+", f"mattr={self.mattr} -mattr=", self.cmd
+                )
+            else:
+                self.cmd = re.sub(r"llvm-mc", f"llvm-mc -mattr={self.mattr}", self.cmd)
+
+        log.debug(f"Run: {self.cmd}")
+        result = sp.run(self.cmd.split(" "), input=content, capture_output=True)
+        return result
+
+    def get_opts_list(self) -> list[str]:
+        opts = self.opts.strip().strip(",")
+        opts = re.sub(r"[, ]+", ",", opts)
+        return opts.split(",")
+
+    def __str__(self) -> str:
+        return f"{self.cmd} < {str(self.file.absolute())}"
 
 
-class Test:
-    def __init__(self, encoding: str | None, asm_text: str | None):
-        self.encoding: str | None = encoding
-        self.asm_text: str | None = asm_text
-
-    def __str__(self):
-        self.encoding.replace(" ", ",")
-        self.encoding = self.encoding.strip("[]")
-        return f"{self.encoding} == {self.asm_text}"
-
-    def test_complete(self) -> bool:
-        return self.encoding is not None and self.asm_text is not None
-
-    def add_missing(self, encoding: str | None, asm_text: str | None):
-        if encoding is None and asm_text is None:
-            raise ValueError("One of the arguments must be set.")
-        if not self.encoding:
-            if not encoding:
-                raise ValueError("Test still needs the encoding but it is None.")
-            self.encoding = encoding
-        if not self.asm_text:
-            if not asm_text:
-                raise ValueError("Test still needs the asm_text but it is None.")
-            self.asm_text = asm_text
-
-
-class TestManager:
-    """Class to manage incomplete tests. It automatically assigns the encoding and asm text
-    to the correct Test objects it holds.
-    It assumes that incomplete tests (only encoding OR the asm_text is given)
-    are all given in the same order.
-    Meaning: The first test without any asm_text but the encoding, is the same test
-    which is later given with only the asm_text but without encoding.
-
-    E.g.:
-        Order in which tests must be given to this Manager:
-
-        Test 1 -> (<encoding>, None)
-        Test 2 -> (<encoding>, None)
-        Test 3 -> (<encoding>, None)
-        ...
-
-        Test 1 -> (None, <asm_text>)
-        Test 2 -> (None, <asm_text>)
-        Test 3 -> (None, <asm_text>)
-        ...
+class MCTest:
+    """
+    A single test. It can contain multiple decoded instruction for a given byte sequence.
+    In general a MCTest always tests a sequence of instructions in a single .text segment.
     """
 
-    class AddingState(Enum):
-        ENCODING = 0
-        ASM_TEXT = 1
-        UNSET = 2
-
-    def __init__(self):
-        # If set, the already added tests are completed with the given information.
-        self.switched = False
-        self.state = self.AddingState.UNSET
-        # List of all tests which still miss a part.
-        self.incomplete_tests: list[Test] = list()
-        # Tests which are complete
-        self.completed: list[Test] = list()
-
-    def add_test(self, encoding: str | None, asm_text: str | None):
-        if encoding is not None and asm_text is not None:
-            if not (
-                self.state == self.AddingState.UNSET and len(self.incomplete_tests) == 0
-            ):
-                log.debug(
-                    f"Complete test found. Drop incomplete {len(self.incomplete_tests)} tests"
-                )
-                self.reset_incomplete()
-            self.state = self.AddingState.UNSET
-            self.completed.append(Test(encoding, asm_text))
-            return
-
-        if self.state == self.AddingState.UNSET:
-            assert len(self.incomplete_tests) == 0
-            # Add the first incomplete test
-            if encoding and asm_text:
-                self.state = self.AddingState.UNSET
-            elif encoding:
-                self.state = self.AddingState.ENCODING
-            else:
-                self.state = self.AddingState.ASM_TEXT
-
-        # Check if we complete the already added tests
-        if (self.state == self.AddingState.ENCODING and encoding is None) or (
-            self.state == self.AddingState.ASM_TEXT and asm_text is None
-        ):
-            self.switched = True
-            oldstate = self.state
-            self.state = (
-                self.AddingState.ENCODING
-                if self.state == self.AddingState.ASM_TEXT
-                else self.AddingState.ASM_TEXT
-            )
-            log.debug(f"switch {oldstate} -> {self.state}")
-
-        if self.switched:
-            log.debug(f"Add incomplete II: {encoding} {asm_text}")
-            test = self.incomplete_tests.pop(0)
-            test.add_missing(encoding, asm_text)
-            self.completed.append(test)
+    def __init__(self, arch: str, opts: list[str], encoding: str, asm_text: str):
+        self.arch = arch
+        if arch.lower() in ["arm", "powerpc", "ppc", "aarch64"]:
+            # Arch and PPC require this option for MC tests.
+            self.opts = ["CS_OPT_NO_BRANCH_OFFSET"] + opts
         else:
-            log.debug(f"Add incomplete I: {encoding} {asm_text}")
-            self.incomplete_tests.append(Test(encoding, asm_text))
+            self.opts = opts
+        self.encoding: list[str] = [encoding]
+        self.asm_text: list[str] = [asm_text]
 
-        # Lastly check if we can reset.
-        if len(self.incomplete_tests) == 0:
-            # All tests are completed. Reset
-            self.state = self.AddingState.UNSET
-            self.switched = False
-            log.debug(f"Reset: {self.state}")
+    def extend(self, encoding: str, asm_text: str):
+        self.encoding.append(encoding)
+        self.asm_text.append(asm_text)
 
-    def check_all_complete(self) -> bool:
-        if len(self.incomplete_tests) != 0:
-            log.debug(f"We have {len(self.incomplete_tests)} incomplete tests.")
-            return False
-        return True
-
-    def get_completed(self) -> list[Test]:
-        return self.completed
-
-    def get_stats(self) -> str:
-        return (
-            f"completed: {len(self.completed)} incomplete: {len(self.incomplete_tests)}"
+    def __str__(self):
+        encoding = ",".join(self.encoding)
+        encoding = re.sub(r"[\[\]]", "", encoding)
+        encoding = encoding.strip()
+        encoding = re.sub(r"[\s,]+", ", ", encoding)
+        yaml_tc = (
+            "  -\n"
+            "    input:\n"
+            "      bytes: [ <ENCODING> ]\n"
+            '      arch: "<ARCH>"\n'
+            "      options: [ <OPTIONS> ]\n"
+            "    expected:\n"
+            "      insns:\n"
         )
+        template = "        -\n          asm_text: <ASM_TEXT>\n"
+        insn_cases = ""
+        for text in self.asm_text:
+            insn_cases += template.replace("<ASM_TEXT>", f'"{text}"')
 
-    def get_num_completed(self) -> int:
-        return len(self.completed)
-
-    def get_num_incomplete(self) -> int:
-        return len(self.incomplete_tests)
-
-    def reset_incomplete(self):
-        self.incomplete_tests.clear()
-        self.state = self.AddingState.UNSET
-        self.switched = False
+        yaml_tc = yaml_tc.replace("<ENCODING>", encoding)
+        yaml_tc = yaml_tc.replace("<ARCH>", f"CS_ARCH_{self.arch.upper()}")
+        yaml_tc = yaml_tc.replace("<OPTIONS>", ", ".join([f'"{o}"' for o in self.opts]))
+        yaml_tc += insn_cases
+        return yaml_tc
 
 
 class TestFile:
     def __init__(
-        self, arch: str, filename: str, manager: TestManager, mattrs: list[str] | None
+        self,
+        arch: str,
+        file_path: Path,
+        opts: list[str] | None,
+        mc_cmd: LLVM_MC_Command,
+        unified_test_cases: bool,
     ):
-        self.arch = arch
-        self.filename = filename
-        self.manager = manager
-        self.mattrs: list[str] = list() if not mattrs else mattrs
-        self.tests = list()
+        self.arch: str = arch
+        self.file_path: Path = file_path
+        self.opts: list[str] = list() if not opts else opts
+        self.mc_cmd: LLVM_MC_Command = mc_cmd
+        # Indexed by .text section count
+        self.tests: dict[int : list[MCTest]] = dict()
 
-    def add_mattr(self, mattr: str):
-        if not self.mattrs:
-            self.mattrs = list()
-        if mattr not in self.mattrs:
-            self.mattrs.append(mattr)
+        self.init_tests(unified_test_cases)
 
-    def add_tests(self, tests: list[Test]):
-        self.tests = tests
+    def init_tests(self, unified_test_cases: bool):
+        mc_output = self.mc_cmd.exec()
+        if mc_output.stderr and not mc_output.stdout:
+            # We can still continue. We just ignore the failed cases.
+            log.debug(f"llvm-mc cmd stderr: {mc_output.stderr}")
+        log.debug(f"llvm-mc result: {mc_output}")
+        text_section = 0  # Counts the .text sections
+        asm_pat = f"(?P<asm_text>.+)"
+        enc_pat = r"(\[?(?P<full_enc_string>(?P<enc_bytes>((0x[a-fA-F0-9]{1,2}[, ]{0,2}))+)[^, ]?)\]?)"
+        for line in mc_output.stdout.splitlines():
+            line = line.decode("utf8")
+            if ".text" in line:
+                text_section += 1
+                continue
+            match = re.search(
+                rf"^\s*{asm_pat}\s*(#|//|@)\s*encoding:\s*{enc_pat}", line
+            )
+            if not match:
+                continue
+            full_enc_string = match.group("full_enc_string")
+            if not re.search(r"0x[a-fA-F0-9]{1,2}$", full_enc_string[:-1]):
+                log.debug(f"Ignore because symbol injection is needed: {line}")
+                # The encoding string contains symbol information of the form:
+                # [0xc0,0xe0,A,A,A... or similar. We ignore these for now.
+                continue
+            enc_bytes = match.group("enc_bytes").strip()
+            asm_text = match.group("asm_text").strip()
+            asm_text = re.sub(r"\t+", " ", asm_text)
+            asm_text = asm_text.strip()
+            if not self.valid_byte_seq(enc_bytes):
+                continue
+
+            if text_section in self.tests:
+                if unified_test_cases:
+                    self.tests[text_section][0].extend(enc_bytes, asm_text)
+                else:
+                    self.tests[text_section].append(
+                        MCTest(self.arch, self.opts, enc_bytes, asm_text)
+                    )
+            else:
+                self.tests[text_section] = [
+                    MCTest(self.arch, self.opts, enc_bytes, asm_text)
+                ]
 
     def has_tests(self) -> bool:
         return len(self.tests) != 0
 
-    def get_cs_testfile_content(self) -> str:
-        old_mc_test_file = get_path("{MC_DIR}").joinpath(
-            f"{self.arch}/{self.filename}.cs"
-        )
-        if not old_mc_test_file.exists():
-            header = (
-                f"# CS_ARCH_{self.arch.upper()}, None, None\n"
-                "# This regression test file is new. The option flags could not be determined.\n"
-                f"# LLVM uses the following mattr = {self.mattrs}"
-            )
-        else:
-            with open(old_mc_test_file) as f:
-                init_line = f.readlines()[0]
-            assert init_line != "" and "# CS_ARCH_" in init_line
-            header = init_line
-
-        content = header + "\n"
-        for test in self.tests:
-            content += f"{test}\n"
+    def get_cs_testfile_content(self, only_test: bool) -> str:
+        content = "\n" if only_test else "test_cases:\n"
+        for tl in self.tests.values():
+            content += "\n".join([str(t) for t in tl])
         return content
 
+    def num_test_cases(self) -> int:
+        return len(self.tests)
+
+    def valid_byte_seq(self, enc_bytes):
+        match self.arch:
+            case "AArch64":
+                # It always needs 4 bytes.
+                # Otherwise it is likely a reloc or symbol test
+                return enc_bytes.count("0x") == 4
+            case _:
+                return True
+
+    def get_multi_mode_filename(self) -> Path:
+        filename = self.file_path.stem
+        parent = self.file_path.parent
+        detailed_name = f"{filename}_{'_'.join(self.opts)}.txt"
+        detailed_name = re.sub(r"[+-]", "_", detailed_name)
+        out_path = parent.joinpath(detailed_name)
+        return Path(out_path)
+
+    def get_simple_filename(self) -> Path:
+        return self.file_path
+
+    def __lt__(self, other) -> bool:
+        return str(self.file_path) < str(other.file_path)
+
 
 class MCUpdater:
+    """
+    The MCUpdater parses all test files of the LLVM MC regression tests.
+    Each of those LLVM files can contain several llvm-mc commands to run on the same file.
+    Mostly this is done to test the same file with different CPU features enabled.
+    So it can test different flavors of assembly etc.
+
+    In Capstone all modules enable always all CPU features (even if this is not
+    possible in reality).
+    Due to this we always parse all llvm-mc commands run on a test file, generate a TestFile
+    object for each of it, but only write the last one of them to disk.
+    Once https://github.com/capstone-engine/capstone/issues/1992 is resolved, we can
+    write all variants of a test file to disk.
+
+    This is already implemented and tested with multi_mode = True.
+    """
+
     def __init__(
         self,
         arch: str,
         mc_dir: Path,
         excluded: list[str] | None,
         included: list[str] | None,
+        unified_test_cases: bool,
+        multi_mode: bool = False,
     ):
+        self.symbolic_links = list()
         self.arch = arch
+        self.test_dir_link_prefix = f"test_dir_{arch}_"
         self.mc_dir = mc_dir
         self.excluded = excluded if excluded else list()
         self.included = included if included else list()
-        self.test_files: dict[str:TestFile] = dict()
-
-    def parse_file(self, filepath: Path) -> TestFile | None:
-        """Parse a MC test file and return it as an object with all tests found.
-        If it couldn't parse the file cleanly, it prints errors but returns it anyways.
-        """
-        with open(filepath) as f:
-            lines = f.readlines()
-
-        test_file = TestFile(self.arch, filepath.name, TestManager(), None)
-        manager = test_file.manager
-        for line in lines:
-            if line == "\n":
-                # New line means new block starts. Drop all incomplete tests.
-                log.debug("New line. Drop all incomplete tests")
-                test_file.manager.reset_incomplete()
-            try:
-                if mattr := self.get_mattr(line):
-                    test_file.add_mattr(mattr)
-                    continue
-                encoding, asm_text = self.get_enc_asm(line)
-                if not encoding and not asm_text:
-                    continue
-                manager.add_test(encoding, asm_text)
-            except ValueError as e:
-                raise e
-                log.debug(f"Failed to parse {test_file.filename}. Skipping it")
-                return None
-
-        manager.check_all_complete()
-        test_file.add_tests(manager.get_completed())
-        log.debug(f"Parsed {manager.get_num_completed()} tests:\t{filepath.name}")
-        return test_file
-
-    @staticmethod
-    def get_mattr(line: str) -> str | None:
-        match = re.search(match_patterns["run_line"], line)
-        if not match or not match.group("mattr"):
-            return None
-        return match.group("mattr")
-
-    @staticmethod
-    def get_enc_asm(line: str) -> tuple[str | None, str | None]:
-        enc: str | None = None
-        asm_text: str | None = None
-        if re.search(match_patterns["skip_pattern"], line):
-            return None, None
-        # Check for single line tests
-        single_match = re.search(match_patterns["single_line_disas"], line)
-        if single_match:
-            return (
-                single_match.group("enc_bytes"),
-                single_match.group("asm_text").strip(),
-            )
-
-        asm_match = re.search(match_patterns["asm_check"], line)
-        if asm_match:
-            asm_text = asm_match.group("asm_text")
-            if asm_match.group("enc_bytes"):
-                # Single line test
-                enc = asm_match.group("enc_bytes")
-            if asm_text:
-                asm_text = asm_text.strip()
-            # A single line test. Return the result
-            if asm_text and enc:
-                return enc, asm_text
-
-        # Check if the line contains at least encoding bytes
-        pattern = rf"{match_patterns['enc_prefix_disas']}{match_patterns['enc_bytes']}"
-        enc_match = re.search(pattern, line)
-        if enc_match:
-            enc = enc_match.group("enc_bytes")
-
-        return enc, asm_text
-
-    def gen_tests_in_dir(self, curr_dir: Path) -> list[str]:
-        """Generate testcases from the files in the given dir.
-        Returns a list of files which failed to parse.
-        """
-        fails = list()
-        for file in curr_dir.iterdir():
-            if file.is_dir():
-                self.gen_tests_in_dir(file)
-                continue
-            if len(self.included) != 0 and not any(
-                re.search(x, file.name) is not None for x in self.included
-            ):
-                continue
-            if any(re.search(x, file.name) is not None for x in self.excluded):
-                continue
-            if test_file := self.parse_file(curr_dir.joinpath(file)):
-                self.test_files[file.name] = test_file
-            else:
-                fails.append(file.name)
-        return fails
-
-    def gen_all(self):
-        log.info("Generate MC regression tests")
-        assembly_tests = self.mc_dir.joinpath(f"{self.arch}")
-        disas_tests = self.mc_dir.joinpath(f"Disassembler/{self.arch}")
-        if not disas_tests.exists() or not disas_tests.is_dir():
-            raise ValueError(
-                f"'{disas_tests}' does not exits or is not a directory. Cannot generate tests from there."
-            )
-        if not assembly_tests.exists() or not assembly_tests.is_dir():
-            raise ValueError(
-                f"'{assembly_tests}' does not exits or is not a directory. Cannot generate tests from there."
-            )
-
-        fails = self.gen_tests_in_dir(disas_tests)
-        fails.extend(self.gen_tests_in_dir(assembly_tests))
-        sum_tests = sum([len(tf.tests) for tf in self.test_files.values()])
-        log.info(
-            f"Parse {len(self.test_files)} MC test files with a total of {sum_tests} tests."
+        self.test_files: list[TestFile] = list()
+        self.unified_test_cases = unified_test_cases
+        with open(get_path("{MCUPDATER_CONFIG_FILE}")) as f:
+            self.conf = json.loads(f.read())
+        # Additional mattr passed to llvm-mc
+        self.mattr: str = (
+            ",".join(self.conf["additional_mattr"][self.arch])
+            if self.arch in self.conf["additional_mattr"]
+            else ""
         )
-        if fails:
-            log.warning("The following files failed to parse:")
-            for f in fails:
-                log.warning(f"\t{f}")
-        self.write_to_build_dir()
+        # A list of options which are always added.
+        self.mandatory_options: str = (
+            self.conf["mandatory_options"][self.arch]
+            if self.arch in self.conf["mandatory_options"]
+            else list()
+        )
+        self.multi_mode = multi_mode
+
+    def check_prerequisites(self, paths):
+        for path in paths:
+            if not path.exists() or not path.is_dir():
+                raise ValueError(
+                    f"'{path}' does not exits or is not a directory. Cannot generate tests from there."
+                )
+        llvm_lit_cfg = get_path("{LLVM_LIT_TEST_DIR}")
+        if not llvm_lit_cfg.exists():
+            raise ValueError(
+                f"Could not find '{llvm_lit_cfg}'. Check {{LLVM_LIT_TEST_DIR}} in path_vars.json."
+            )
 
     def write_to_build_dir(self):
-        for filename, test in self.test_files.items():
+        file_cnt = 0
+        test_cnt = 0
+        overwritten = 0
+        files_written = set()
+        for test in sorted(self.test_files):
             if not test.has_tests():
                 continue
-            with open(
-                get_path("{MCUPDATER_OUT_DIR}").joinpath(f"{filename}.cs"), "w+"
-            ) as f:
-                f.write(test.get_cs_testfile_content())
-            log.debug(f"Write {filename}")
+            file_cnt += 1
+            test_cnt += test.num_test_cases()
+
+            if self.multi_mode:
+                rel_path = str(
+                    test.get_multi_mode_filename().relative_to(
+                        get_path("{LLVM_LIT_TEST_DIR}")
+                    )
+                )
+            else:
+                rel_path = str(
+                    test.get_simple_filename().relative_to(
+                        get_path("{LLVM_LIT_TEST_DIR}")
+                    )
+                )
+
+            filename = re.sub(rf"{self.test_dir_link_prefix}\d+", ".", rel_path)
+            filename = get_path("{MCUPDATER_OUT_DIR}").joinpath(f"{filename}.yaml")
+            if filename in files_written:
+                write_mode = "a"
+            else:
+                write_mode = "w+"
+            filename.parent.mkdir(parents=True, exist_ok=True)
+            if self.multi_mode and filename.exists():
+                raise ValueError(
+                    f"The following file exists already: {filename}\n"
+                    "This is not allowed in multi-mode."
+                )
+            else:
+                log.debug(f"Overwrite: {filename}")
+                overwritten += 1
+            with open(filename, write_mode) as f:
+                f.write(test.get_cs_testfile_content(only_test=(write_mode == "a")))
+                log.debug(f"Write {filename}")
+            files_written.add(filename)
+        log.info(
+            f"Processed {file_cnt} files with {test_cnt} test cases. Generated {len(files_written)} files"
+        )
+        if overwritten > 0:
+            log.warning(
+                f"Overwrote {overwritten} test files with the same name.\n"
+                f"These files contain instructions of several different cpu features.\n"
+                f"You have to use multi-mode to write them into distinct files.\n"
+                f"The current setting will only keep the last one written.\n"
+                f"See also: https://github.com/capstone-engine/capstone/issues/1992"
+            )
+
+    def build_test_files(self, mc_cmds: list[LLVM_MC_Command]) -> list[TestFile]:
+        log.info("Build TestFile objects")
+        test_files = list()
+        n_all = len(mc_cmds)
+        for i, mcc in enumerate(mc_cmds):
+            print(f"{i + 1}/{n_all} {mcc.file.name}", flush=True, end="\r")
+            test_files.append(
+                TestFile(
+                    self.arch,
+                    mcc.file,
+                    mcc.get_opts_list() + self.mandatory_options,
+                    mcc,
+                    self.unified_test_cases,
+                )
+            )
+        return test_files
+
+    def run_llvm_lit(self, paths: list[Path]) -> list[LLVM_MC_Command]:
+        """
+        Calls llvm-lit with the given paths to the tests.
+        It parses the llvm-lit commands to LLVM_MC_Commands.
+        """
+        lit_cfg_dir = get_path("{LLVM_LIT_TEST_DIR}")
+        llvm_lit_cfg = str(lit_cfg_dir.absolute())
+        args = ["lit", "-v", "-a", llvm_lit_cfg]
+        for i, p in enumerate(paths):
+            slink = lit_cfg_dir.joinpath(f"{self.test_dir_link_prefix}{i}")
+            self.symbolic_links.append(slink)
+            log.debug(f"Create link: {slink} -> {p}")
+            try:
+                slink.symlink_to(p, target_is_directory=True)
+            except FileExistsError as e:
+                print("Failed: Link existed. Please delete it")
+                raise e
+
+        log.info(f"Run lit: {' '.join(args)}")
+        cmds = sp.run(args, capture_output=True)
+        if cmds.stderr:
+            raise ValueError(f"llvm-lit failed with {cmds.stderr}")
+        return self.extract_llvm_mc_cmds(cmds.stdout.decode("utf8"))
+
+    def extract_llvm_mc_cmds(self, cmds: str) -> list[LLVM_MC_Command]:
+        log.debug("Parsing llvm-mc commands")
+        # Get only the RUN lines which have a show-encoding set.
+        cmd_lines = cmds.splitlines()
+        log.debug(f"NO FILTER: {cmd_lines}")
+        matches = list(
+            filter(
+                lambda l: (
+                    l
+                    if re.search(r"^RUN.+(show-encoding|disassemble)[^|]+", l)
+                    else None
+                ),
+                cmd_lines,
+            )
+        )
+        log.debug(f"FILTER RUN: {' '.join(matches)}")
+        # Don't add tests which are allowed to fail
+        matches = list(
+            filter(lambda m: None if re.search(r"not\s+llvm-mc", m) else m, matches)
+        )
+        log.debug(f"FILTER not llvm-mc: {' '.join(matches)}")
+        # Skip object file tests
+        matches = list(
+            filter(lambda m: None if re.search(r"filetype=obj", m) else m, matches)
+        )
+        log.debug(f"FILTER filetype=obj-mc: {' '.join(matches)}")
+        # Skip any relocation related tests.
+        matches = filter(lambda m: None if re.search(r"reloc", m) else m, matches)
+        # Remove 'RUN: at ...' prefix
+        matches = map(lambda m: re.sub(r"^RUN: at line \d+: ", "", m), matches)
+        # Remove redirection
+        matches = map(lambda m: re.sub(r"\d>&\d", "", m), matches)
+        # Remove unused arguments
+        matches = map(lambda m: re.sub(r"-o\s?-", "", m), matches)
+        # Remove redirection of stderr to a file
+        matches = map(lambda m: re.sub(r"2>\s?\S+", "", m), matches)
+        # Remove piping to FileCheck
+        matches = map(lambda m: re.sub(r"\|\s*FileCheck\s+.+", "", m), matches)
+        # Remove input stream
+        matches = map(lambda m: re.sub(r"\s+<", "", m), matches)
+
+        all_cmds = list()
+        for match in matches:
+            if self.included and not any(
+                re.search(x, match) is not None for x in self.included
+            ):
+                continue
+            if any(re.search(x, match) is not None for x in self.excluded):
+                continue
+            llvm_mc_cmd = LLVM_MC_Command(match, self.mattr)
+            if not llvm_mc_cmd.cmd:
+                # Invalid
+                continue
+            all_cmds.append(llvm_mc_cmd)
+            log.debug(f"Added: {llvm_mc_cmd}")
+        log.debug(f"Extracted {len(all_cmds)} llvm-mc commands")
+        return all_cmds
+
+    def gen_all(self):
+        log.info("Check prerequisites")
+        disas_tests = self.mc_dir.joinpath(f"Disassembler/{self.arch}")
+        test_paths = [disas_tests]
+        self.check_prerequisites(test_paths)
+        log.info("Generate MC regression tests")
+        llvm_mc_cmds = self.run_llvm_lit(test_paths)
+        log.info(f"Got {len(llvm_mc_cmds)} llvm-mc commands to run")
+        self.test_files = self.build_test_files(llvm_mc_cmds)
+        for slink in self.symbolic_links:
+            log.debug(f"Unlink {slink}")
+            slink.unlink()
+        self.write_to_build_dir()
 
 
 def parse_args() -> argparse.Namespace:
@@ -399,7 +461,7 @@ def parse_args() -> argparse.Namespace:
         "-a",
         dest="arch",
         help="Name of architecture to update.",
-        choices=["ARM", "PowerPC", "AArch64", "LoongArch"],
+        choices=TARGETS_LLVM_NAMING,
         required=True,
     )
     parser.add_argument(
@@ -416,6 +478,13 @@ def parse_args() -> argparse.Namespace:
         nargs="+",
         help="Specific list of file names to update (can be a regex pattern).",
     )
+    parser.add_argument(
+        "-u",
+        dest="unified_tests",
+        action="store_true",
+        default=False,
+        help="If set, all instructions of a text segment will decoded and tested at once. Should be set, if instructions depend on each other.",
+    )
     parser.add_argument(
         "-v",
         dest="verbosity",
@@ -437,5 +506,9 @@ if __name__ == "__main__":
     )
 
     MCUpdater(
-        args.arch, args.mc_dir, args.excluded_files, args.included_files
+        args.arch,
+        args.mc_dir,
+        args.excluded_files,
+        args.included_files,
+        args.unified_tests,
     ).gen_all()
diff --git a/suite/auto-sync/src/autosync/PathVarHandler.py b/suite/auto-sync/src/autosync/PathVarHandler.py
index a973f84dc..df5f83627 100644
--- a/suite/auto-sync/src/autosync/PathVarHandler.py
+++ b/suite/auto-sync/src/autosync/PathVarHandler.py
@@ -71,6 +71,13 @@ class PathVarHandler(metaclass=Singleton):
                 log.fatal(f"\t{m}")
             exit(1)
 
+    def test_only_overwrite_var(self, var_name: str, new_path: Path):
+        if var_name not in self.paths:
+            raise ValueError(f"PathVarHandler doesn't have a path for '{var_name}'")
+        if not new_path.exists():
+            raise ValueError(f"New path doesn't exists: '{new_path}")
+        self.paths[var_name] = new_path
+
     def get_path(self, name: str) -> Path:
         if name not in self.paths:
             raise ValueError(f"Path variable {name} has no path saved.")
diff --git a/suite/auto-sync/src/autosync/Targets.py b/suite/auto-sync/src/autosync/Targets.py
new file mode 100644
index 000000000..d3dfdd1c5
--- /dev/null
+++ b/suite/auto-sync/src/autosync/Targets.py
@@ -0,0 +1,4 @@
+# Copyright © 2024 Rot127 <unisono@quyllur.org>
+# SPDX-License-Identifier: BSD-3
+
+TARGETS_LLVM_NAMING = ["ARM", "PowerPC", "Alpha", "AArch64", "LoongArch"]
diff --git a/suite/auto-sync/src/autosync/Tests/MCUpdaterTests/Disassembler/ARCH/test_a.txt b/suite/auto-sync/src/autosync/Tests/MCUpdaterTests/Disassembler/ARCH/test_a.txt
new file mode 100644
index 000000000..6cbdbb6ac
--- /dev/null
+++ b/suite/auto-sync/src/autosync/Tests/MCUpdaterTests/Disassembler/ARCH/test_a.txt
@@ -0,0 +1,34 @@
+# RUN: llvm-mc -triple=aarch64 -mattr=+v8a,+fp-armv8 -disassemble < %s | FileCheck %s
+# RUN: llvm-mc -triple=arm64 -mattr=+v8.2a -disassemble < %s | FileCheck %s --check-prefix=CHECK-V82
+
+#------------------------------------------------------------------------------
+# Compare and branch (immediate)
+#------------------------------------------------------------------------------
+
+# CHECK: sbfx     x1, x2, #3, #2
+# CHECK: asr      x3, x4, #63
+# CHECK: asr      wzr, wzr, #31
+# CHECK: sbfx     w12, w9, #0, #1
+0x41 0x10 0x43 0x93
+0x83 0xfc 0x7f 0x93
+0xff 0x7f 0x1f 0x13
+0x2c 0x1 0x0 0x13
+
+# CHECK: ubfiz    x4, x5, #52, #11
+# CHECK: ubfx     xzr, x4, #0, #1
+# CHECK: ubfiz    x4, xzr, #1, #6
+# CHECK: lsr      x5, x6, #12
+0xa4 0x28 0x4c 0xd3
+0x9f 0x0 0x40 0xd3
+0xe4 0x17 0x7f 0xd3
+0xc5 0xfc 0x4c 0xd3
+
+# CHECK: bfi      x4, x5, #52, #11
+# CHECK: bfxil    xzr, x4, #0, #1
+# CHECK: bfi      x4, xzr, #1, #6
+# CHECK-V82: bfc      x4, #1, #6
+# CHECK: bfxil    x5, x6, #12, #52
+0xa4 0x28 0x4c 0xb3
+0x9f 0x0 0x40 0xb3
+0xe4 0x17 0x7f 0xb3
+0xc5 0xfc 0x4c 0xb3
diff --git a/suite/auto-sync/src/autosync/Tests/MCUpdaterTests/Disassembler/ARCH/test_b.txt b/suite/auto-sync/src/autosync/Tests/MCUpdaterTests/Disassembler/ARCH/test_b.txt
new file mode 100644
index 000000000..8aa3152ae
--- /dev/null
+++ b/suite/auto-sync/src/autosync/Tests/MCUpdaterTests/Disassembler/ARCH/test_b.txt
@@ -0,0 +1,9 @@
+# The RUN line parsing
+# RUN: llvm-mc --disassemble -triple=arm64 < %s | FileCheck %s
+
+
+[0x00,0x0a,0x31,0xd5]
+# CHECK:   mrs x0, TRCRSR
+
+[0x80,0x08,0x31,0xd5]
+# CHECK:   mrs x0, TRCEXTINSELR
diff --git a/suite/auto-sync/src/autosync/Tests/MCUpdaterTests/Disassembler/ARCH/test_no_symbol.s.txt b/suite/auto-sync/src/autosync/Tests/MCUpdaterTests/Disassembler/ARCH/test_no_symbol.s.txt
new file mode 100644
index 000000000..428b7535a
--- /dev/null
+++ b/suite/auto-sync/src/autosync/Tests/MCUpdaterTests/Disassembler/ARCH/test_no_symbol.s.txt
@@ -0,0 +1,41 @@
+# RUN: llvm-mc -triple s390x-unknown-unknown -mcpu=z13 --show-encoding %s | FileCheck %s
+
+# RUN: llvm-mc -triple s390x-unknown-unknown -mcpu=z13 -filetype=obj %s | \
+# RUN: llvm-readobj -r - | FileCheck %s -check-prefix=CHECK-REL
+
+# RUN: llvm-mc -triple s390x-unknown-unknown -mcpu=z13 -filetype=obj %s | \
+# RUN: llvm-objdump -d - | FileCheck %s -check-prefix=CHECK-DIS
+
+# CHECK: larl %r14, target                      # encoding: [0xc0,0xe0,A,A,A,A]
+# CHECK-NEXT:                                   # fixup A - offset: 2, value: target+2, kind: FK_390_PC32DBL
+# CHECK-REL:                                    0x{{[0-9A-F]*2}} R_390_PC32DBL target 0x2
+	.align 16
+	larl %r14, target
+
+# CHECK: larl %r14, target@GOT                  # encoding: [0xc0,0xe0,A,A,A,A]
+# CHECK-NEXT:                                   # fixup A - offset: 2, value: target@GOT+2, kind: FK_390_PC32DBL
+# CHECK-REL:                                    0x{{[0-9A-F]*2}} R_390_GOTENT target 0x2
+	.align 16
+	larl %r14, target@got
+
+# CHECK: vl %v0, src(%r1)                       # encoding: [0xe7,0x00,0b0001AAAA,A,0x00,0x06]
+# CHECK-NEXT:                                   # fixup A - offset: 2, value: src, kind: FK_390_U12Imm
+# CHECK-REL:                                    0x{{[0-9A-F]*2}} R_390_12 src 0x0
+        .align 16
+        vl %v0, src(%r1)
+
+
+# CHECK: .insn ss,238594023227392,dst(%r2,%r1),src,%r3  # encoding: [0xd9,0x23,0b0001AAAA,A,0b0000BBBB,B]
+# CHECK-NEXT:                                           # fixup A - offset: 2, value: dst, kind: FK_390_U12Imm
+# CHECK-NEXT:                                           # fixup B - offset: 4, value: src, kind: FK_390_U12Imm
+# CHECK-REL:                                            0x{{[0-9A-F]*2}} R_390_12 dst 0x0
+# CHECK-REL:                                            0x{{[0-9A-F]*4}} R_390_12 src 0x0
+        .align 16
+        .insn ss,0xd90000000000,dst(%r2,%r1),src,%r3	# mvck
+
+##S8
+# CHECK: asi 0(%r1), src                        # encoding: [0xeb,A,0x10,0x00,0x00,0x6a]
+# CHECK-NEXT:                                   # fixup A - offset: 1, value: src, kind: FK_390_S8Imm
+# CHECK-REL:                                    0x{{[0-9A-F]+}} R_390_8 src 0x0
+       .align 16
+       asi 0(%r1),src
diff --git a/suite/auto-sync/src/autosync/Tests/MCUpdaterTests/expected/merged/separated/test_a.txt.yaml b/suite/auto-sync/src/autosync/Tests/MCUpdaterTests/expected/merged/separated/test_a.txt.yaml
new file mode 100644
index 000000000..abc0c2971
--- /dev/null
+++ b/suite/auto-sync/src/autosync/Tests/MCUpdaterTests/expected/merged/separated/test_a.txt.yaml
@@ -0,0 +1,240 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x41, 0x10, 0x43, 0x93 ]
+      arch: "CS_ARCH_ARCH"
+      options: [ "aarch64", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "sbfx x1, x2, #3, #2"
+
+  -
+    input:
+      bytes: [ 0x83, 0xfc, 0x7f, 0x93 ]
+      arch: "CS_ARCH_ARCH"
+      options: [ "aarch64", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "asr x3, x4, #63"
+
+  -
+    input:
+      bytes: [ 0xff, 0x7f, 0x1f, 0x13 ]
+      arch: "CS_ARCH_ARCH"
+      options: [ "aarch64", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "asr wzr, wzr, #31"
+
+  -
+    input:
+      bytes: [ 0x2c, 0x01, 0x00, 0x13 ]
+      arch: "CS_ARCH_ARCH"
+      options: [ "aarch64", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "sbfx w12, w9, #0, #1"
+
+  -
+    input:
+      bytes: [ 0xa4, 0x28, 0x4c, 0xd3 ]
+      arch: "CS_ARCH_ARCH"
+      options: [ "aarch64", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ubfiz x4, x5, #52, #11"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x00, 0x40, 0xd3 ]
+      arch: "CS_ARCH_ARCH"
+      options: [ "aarch64", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ubfx xzr, x4, #0, #1"
+
+  -
+    input:
+      bytes: [ 0xe4, 0x17, 0x7f, 0xd3 ]
+      arch: "CS_ARCH_ARCH"
+      options: [ "aarch64", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ubfiz x4, xzr, #1, #6"
+
+  -
+    input:
+      bytes: [ 0xc5, 0xfc, 0x4c, 0xd3 ]
+      arch: "CS_ARCH_ARCH"
+      options: [ "aarch64", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsr x5, x6, #12"
+
+  -
+    input:
+      bytes: [ 0xa4, 0x28, 0x4c, 0xb3 ]
+      arch: "CS_ARCH_ARCH"
+      options: [ "aarch64", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfi x4, x5, #52, #11"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x00, 0x40, 0xb3 ]
+      arch: "CS_ARCH_ARCH"
+      options: [ "aarch64", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfxil xzr, x4, #0, #1"
+
+  -
+    input:
+      bytes: [ 0xe4, 0x17, 0x7f, 0xb3 ]
+      arch: "CS_ARCH_ARCH"
+      options: [ "aarch64", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfi x4, xzr, #1, #6"
+
+  -
+    input:
+      bytes: [ 0xc5, 0xfc, 0x4c, 0xb3 ]
+      arch: "CS_ARCH_ARCH"
+      options: [ "aarch64", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfxil x5, x6, #12, #52"
+
+  -
+    input:
+      bytes: [ 0x41, 0x10, 0x43, 0x93 ]
+      arch: "CS_ARCH_ARCH"
+      options: [ "arm64", "v8.2a" ]
+    expected:
+      insns:
+        -
+          asm_text: "sbfx x1, x2, #3, #2"
+
+  -
+    input:
+      bytes: [ 0x83, 0xfc, 0x7f, 0x93 ]
+      arch: "CS_ARCH_ARCH"
+      options: [ "arm64", "v8.2a" ]
+    expected:
+      insns:
+        -
+          asm_text: "asr x3, x4, #63"
+
+  -
+    input:
+      bytes: [ 0xff, 0x7f, 0x1f, 0x13 ]
+      arch: "CS_ARCH_ARCH"
+      options: [ "arm64", "v8.2a" ]
+    expected:
+      insns:
+        -
+          asm_text: "asr wzr, wzr, #31"
+
+  -
+    input:
+      bytes: [ 0x2c, 0x01, 0x00, 0x13 ]
+      arch: "CS_ARCH_ARCH"
+      options: [ "arm64", "v8.2a" ]
+    expected:
+      insns:
+        -
+          asm_text: "sbfx w12, w9, #0, #1"
+
+  -
+    input:
+      bytes: [ 0xa4, 0x28, 0x4c, 0xd3 ]
+      arch: "CS_ARCH_ARCH"
+      options: [ "arm64", "v8.2a" ]
+    expected:
+      insns:
+        -
+          asm_text: "ubfiz x4, x5, #52, #11"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x00, 0x40, 0xd3 ]
+      arch: "CS_ARCH_ARCH"
+      options: [ "arm64", "v8.2a" ]
+    expected:
+      insns:
+        -
+          asm_text: "ubfx xzr, x4, #0, #1"
+
+  -
+    input:
+      bytes: [ 0xe4, 0x17, 0x7f, 0xd3 ]
+      arch: "CS_ARCH_ARCH"
+      options: [ "arm64", "v8.2a" ]
+    expected:
+      insns:
+        -
+          asm_text: "ubfiz x4, xzr, #1, #6"
+
+  -
+    input:
+      bytes: [ 0xc5, 0xfc, 0x4c, 0xd3 ]
+      arch: "CS_ARCH_ARCH"
+      options: [ "arm64", "v8.2a" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsr x5, x6, #12"
+
+  -
+    input:
+      bytes: [ 0xa4, 0x28, 0x4c, 0xb3 ]
+      arch: "CS_ARCH_ARCH"
+      options: [ "arm64", "v8.2a" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfi x4, x5, #52, #11"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x00, 0x40, 0xb3 ]
+      arch: "CS_ARCH_ARCH"
+      options: [ "arm64", "v8.2a" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfxil xzr, x4, #0, #1"
+
+  -
+    input:
+      bytes: [ 0xe4, 0x17, 0x7f, 0xb3 ]
+      arch: "CS_ARCH_ARCH"
+      options: [ "arm64", "v8.2a" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfc x4, #1, #6"
+
+  -
+    input:
+      bytes: [ 0xc5, 0xfc, 0x4c, 0xb3 ]
+      arch: "CS_ARCH_ARCH"
+      options: [ "arm64", "v8.2a" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfxil x5, x6, #12, #52"
diff --git a/suite/auto-sync/src/autosync/Tests/MCUpdaterTests/expected/merged/separated/test_b.txt.yaml b/suite/auto-sync/src/autosync/Tests/MCUpdaterTests/expected/merged/separated/test_b.txt.yaml
new file mode 100644
index 000000000..16cf14af7
--- /dev/null
+++ b/suite/auto-sync/src/autosync/Tests/MCUpdaterTests/expected/merged/separated/test_b.txt.yaml
@@ -0,0 +1,20 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x0a, 0x31, 0xd5 ]
+      arch: "CS_ARCH_ARCH"
+      options: [ "arm64" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, TRCRSR"
+
+  -
+    input:
+      bytes: [ 0x80, 0x08, 0x31, 0xd5 ]
+      arch: "CS_ARCH_ARCH"
+      options: [ "arm64" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, TRCEXTINSELR"
diff --git a/suite/auto-sync/src/autosync/Tests/MCUpdaterTests/expected/merged/unified/test_a.txt.yaml b/suite/auto-sync/src/autosync/Tests/MCUpdaterTests/expected/merged/unified/test_a.txt.yaml
new file mode 100644
index 000000000..243d98623
--- /dev/null
+++ b/suite/auto-sync/src/autosync/Tests/MCUpdaterTests/expected/merged/unified/test_a.txt.yaml
@@ -0,0 +1,64 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x41, 0x10, 0x43, 0x93, 0x83, 0xfc, 0x7f, 0x93, 0xff, 0x7f, 0x1f, 0x13, 0x2c, 0x01, 0x00, 0x13, 0xa4, 0x28, 0x4c, 0xd3, 0x9f, 0x00, 0x40, 0xd3, 0xe4, 0x17, 0x7f, 0xd3, 0xc5, 0xfc, 0x4c, 0xd3, 0xa4, 0x28, 0x4c, 0xb3, 0x9f, 0x00, 0x40, 0xb3, 0xe4, 0x17, 0x7f, 0xb3, 0xc5, 0xfc, 0x4c, 0xb3 ]
+      arch: "CS_ARCH_ARCH"
+      options: [ "aarch64", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "sbfx x1, x2, #3, #2"
+        -
+          asm_text: "asr x3, x4, #63"
+        -
+          asm_text: "asr wzr, wzr, #31"
+        -
+          asm_text: "sbfx w12, w9, #0, #1"
+        -
+          asm_text: "ubfiz x4, x5, #52, #11"
+        -
+          asm_text: "ubfx xzr, x4, #0, #1"
+        -
+          asm_text: "ubfiz x4, xzr, #1, #6"
+        -
+          asm_text: "lsr x5, x6, #12"
+        -
+          asm_text: "bfi x4, x5, #52, #11"
+        -
+          asm_text: "bfxil xzr, x4, #0, #1"
+        -
+          asm_text: "bfi x4, xzr, #1, #6"
+        -
+          asm_text: "bfxil x5, x6, #12, #52"
+
+  -
+    input:
+      bytes: [ 0x41, 0x10, 0x43, 0x93, 0x83, 0xfc, 0x7f, 0x93, 0xff, 0x7f, 0x1f, 0x13, 0x2c, 0x01, 0x00, 0x13, 0xa4, 0x28, 0x4c, 0xd3, 0x9f, 0x00, 0x40, 0xd3, 0xe4, 0x17, 0x7f, 0xd3, 0xc5, 0xfc, 0x4c, 0xd3, 0xa4, 0x28, 0x4c, 0xb3, 0x9f, 0x00, 0x40, 0xb3, 0xe4, 0x17, 0x7f, 0xb3, 0xc5, 0xfc, 0x4c, 0xb3 ]
+      arch: "CS_ARCH_ARCH"
+      options: [ "arm64", "v8.2a" ]
+    expected:
+      insns:
+        -
+          asm_text: "sbfx x1, x2, #3, #2"
+        -
+          asm_text: "asr x3, x4, #63"
+        -
+          asm_text: "asr wzr, wzr, #31"
+        -
+          asm_text: "sbfx w12, w9, #0, #1"
+        -
+          asm_text: "ubfiz x4, x5, #52, #11"
+        -
+          asm_text: "ubfx xzr, x4, #0, #1"
+        -
+          asm_text: "ubfiz x4, xzr, #1, #6"
+        -
+          asm_text: "lsr x5, x6, #12"
+        -
+          asm_text: "bfi x4, x5, #52, #11"
+        -
+          asm_text: "bfxil xzr, x4, #0, #1"
+        -
+          asm_text: "bfc x4, #1, #6"
+        -
+          asm_text: "bfxil x5, x6, #12, #52"
diff --git a/suite/auto-sync/src/autosync/Tests/MCUpdaterTests/expected/merged/unified/test_b.txt.yaml b/suite/auto-sync/src/autosync/Tests/MCUpdaterTests/expected/merged/unified/test_b.txt.yaml
new file mode 100644
index 000000000..914ce4bad
--- /dev/null
+++ b/suite/auto-sync/src/autosync/Tests/MCUpdaterTests/expected/merged/unified/test_b.txt.yaml
@@ -0,0 +1,12 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x0a, 0x31, 0xd5, 0x80, 0x08, 0x31, 0xd5 ]
+      arch: "CS_ARCH_ARCH"
+      options: [ "arm64" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, TRCRSR"
+        -
+          asm_text: "mrs x0, TRCEXTINSELR"
diff --git a/suite/auto-sync/src/autosync/Tests/MCUpdaterTests/expected/multi/separated/test_a_aarch64_v8a__fp_armv8.txt.yaml b/suite/auto-sync/src/autosync/Tests/MCUpdaterTests/expected/multi/separated/test_a_aarch64_v8a__fp_armv8.txt.yaml
new file mode 100644
index 000000000..f44613e36
--- /dev/null
+++ b/suite/auto-sync/src/autosync/Tests/MCUpdaterTests/expected/multi/separated/test_a_aarch64_v8a__fp_armv8.txt.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x41, 0x10, 0x43, 0x93 ]
+      arch: "CS_ARCH_ARCH"
+      options: [ "aarch64", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "sbfx x1, x2, #3, #2"
+
+  -
+    input:
+      bytes: [ 0x83, 0xfc, 0x7f, 0x93 ]
+      arch: "CS_ARCH_ARCH"
+      options: [ "aarch64", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "asr x3, x4, #63"
+
+  -
+    input:
+      bytes: [ 0xff, 0x7f, 0x1f, 0x13 ]
+      arch: "CS_ARCH_ARCH"
+      options: [ "aarch64", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "asr wzr, wzr, #31"
+
+  -
+    input:
+      bytes: [ 0x2c, 0x01, 0x00, 0x13 ]
+      arch: "CS_ARCH_ARCH"
+      options: [ "aarch64", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "sbfx w12, w9, #0, #1"
+
+  -
+    input:
+      bytes: [ 0xa4, 0x28, 0x4c, 0xd3 ]
+      arch: "CS_ARCH_ARCH"
+      options: [ "aarch64", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ubfiz x4, x5, #52, #11"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x00, 0x40, 0xd3 ]
+      arch: "CS_ARCH_ARCH"
+      options: [ "aarch64", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ubfx xzr, x4, #0, #1"
+
+  -
+    input:
+      bytes: [ 0xe4, 0x17, 0x7f, 0xd3 ]
+      arch: "CS_ARCH_ARCH"
+      options: [ "aarch64", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ubfiz x4, xzr, #1, #6"
+
+  -
+    input:
+      bytes: [ 0xc5, 0xfc, 0x4c, 0xd3 ]
+      arch: "CS_ARCH_ARCH"
+      options: [ "aarch64", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsr x5, x6, #12"
+
+  -
+    input:
+      bytes: [ 0xa4, 0x28, 0x4c, 0xb3 ]
+      arch: "CS_ARCH_ARCH"
+      options: [ "aarch64", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfi x4, x5, #52, #11"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x00, 0x40, 0xb3 ]
+      arch: "CS_ARCH_ARCH"
+      options: [ "aarch64", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfxil xzr, x4, #0, #1"
+
+  -
+    input:
+      bytes: [ 0xe4, 0x17, 0x7f, 0xb3 ]
+      arch: "CS_ARCH_ARCH"
+      options: [ "aarch64", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfi x4, xzr, #1, #6"
+
+  -
+    input:
+      bytes: [ 0xc5, 0xfc, 0x4c, 0xb3 ]
+      arch: "CS_ARCH_ARCH"
+      options: [ "aarch64", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfxil x5, x6, #12, #52"
diff --git a/suite/auto-sync/src/autosync/Tests/MCUpdaterTests/expected/multi/separated/test_a_arm64_v8.2a.txt.yaml b/suite/auto-sync/src/autosync/Tests/MCUpdaterTests/expected/multi/separated/test_a_arm64_v8.2a.txt.yaml
new file mode 100644
index 000000000..4702ca3fd
--- /dev/null
+++ b/suite/auto-sync/src/autosync/Tests/MCUpdaterTests/expected/multi/separated/test_a_arm64_v8.2a.txt.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x41, 0x10, 0x43, 0x93 ]
+      arch: "CS_ARCH_ARCH"
+      options: [ "arm64", "v8.2a" ]
+    expected:
+      insns:
+        -
+          asm_text: "sbfx x1, x2, #3, #2"
+
+  -
+    input:
+      bytes: [ 0x83, 0xfc, 0x7f, 0x93 ]
+      arch: "CS_ARCH_ARCH"
+      options: [ "arm64", "v8.2a" ]
+    expected:
+      insns:
+        -
+          asm_text: "asr x3, x4, #63"
+
+  -
+    input:
+      bytes: [ 0xff, 0x7f, 0x1f, 0x13 ]
+      arch: "CS_ARCH_ARCH"
+      options: [ "arm64", "v8.2a" ]
+    expected:
+      insns:
+        -
+          asm_text: "asr wzr, wzr, #31"
+
+  -
+    input:
+      bytes: [ 0x2c, 0x01, 0x00, 0x13 ]
+      arch: "CS_ARCH_ARCH"
+      options: [ "arm64", "v8.2a" ]
+    expected:
+      insns:
+        -
+          asm_text: "sbfx w12, w9, #0, #1"
+
+  -
+    input:
+      bytes: [ 0xa4, 0x28, 0x4c, 0xd3 ]
+      arch: "CS_ARCH_ARCH"
+      options: [ "arm64", "v8.2a" ]
+    expected:
+      insns:
+        -
+          asm_text: "ubfiz x4, x5, #52, #11"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x00, 0x40, 0xd3 ]
+      arch: "CS_ARCH_ARCH"
+      options: [ "arm64", "v8.2a" ]
+    expected:
+      insns:
+        -
+          asm_text: "ubfx xzr, x4, #0, #1"
+
+  -
+    input:
+      bytes: [ 0xe4, 0x17, 0x7f, 0xd3 ]
+      arch: "CS_ARCH_ARCH"
+      options: [ "arm64", "v8.2a" ]
+    expected:
+      insns:
+        -
+          asm_text: "ubfiz x4, xzr, #1, #6"
+
+  -
+    input:
+      bytes: [ 0xc5, 0xfc, 0x4c, 0xd3 ]
+      arch: "CS_ARCH_ARCH"
+      options: [ "arm64", "v8.2a" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsr x5, x6, #12"
+
+  -
+    input:
+      bytes: [ 0xa4, 0x28, 0x4c, 0xb3 ]
+      arch: "CS_ARCH_ARCH"
+      options: [ "arm64", "v8.2a" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfi x4, x5, #52, #11"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x00, 0x40, 0xb3 ]
+      arch: "CS_ARCH_ARCH"
+      options: [ "arm64", "v8.2a" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfxil xzr, x4, #0, #1"
+
+  -
+    input:
+      bytes: [ 0xe4, 0x17, 0x7f, 0xb3 ]
+      arch: "CS_ARCH_ARCH"
+      options: [ "arm64", "v8.2a" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfc x4, #1, #6"
+
+  -
+    input:
+      bytes: [ 0xc5, 0xfc, 0x4c, 0xb3 ]
+      arch: "CS_ARCH_ARCH"
+      options: [ "arm64", "v8.2a" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfxil x5, x6, #12, #52"
diff --git a/suite/auto-sync/src/autosync/Tests/MCUpdaterTests/expected/multi/separated/test_b_arm64.txt.yaml b/suite/auto-sync/src/autosync/Tests/MCUpdaterTests/expected/multi/separated/test_b_arm64.txt.yaml
new file mode 100644
index 000000000..16cf14af7
--- /dev/null
+++ b/suite/auto-sync/src/autosync/Tests/MCUpdaterTests/expected/multi/separated/test_b_arm64.txt.yaml
@@ -0,0 +1,20 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x0a, 0x31, 0xd5 ]
+      arch: "CS_ARCH_ARCH"
+      options: [ "arm64" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, TRCRSR"
+
+  -
+    input:
+      bytes: [ 0x80, 0x08, 0x31, 0xd5 ]
+      arch: "CS_ARCH_ARCH"
+      options: [ "arm64" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, TRCEXTINSELR"
diff --git a/suite/auto-sync/src/autosync/Tests/MCUpdaterTests/expected/multi/unified/test_a_aarch64_v8a__fp_armv8.txt.yaml b/suite/auto-sync/src/autosync/Tests/MCUpdaterTests/expected/multi/unified/test_a_aarch64_v8a__fp_armv8.txt.yaml
new file mode 100644
index 000000000..1ee32dd8a
--- /dev/null
+++ b/suite/auto-sync/src/autosync/Tests/MCUpdaterTests/expected/multi/unified/test_a_aarch64_v8a__fp_armv8.txt.yaml
@@ -0,0 +1,32 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x41, 0x10, 0x43, 0x93, 0x83, 0xfc, 0x7f, 0x93, 0xff, 0x7f, 0x1f, 0x13, 0x2c, 0x01, 0x00, 0x13, 0xa4, 0x28, 0x4c, 0xd3, 0x9f, 0x00, 0x40, 0xd3, 0xe4, 0x17, 0x7f, 0xd3, 0xc5, 0xfc, 0x4c, 0xd3, 0xa4, 0x28, 0x4c, 0xb3, 0x9f, 0x00, 0x40, 0xb3, 0xe4, 0x17, 0x7f, 0xb3, 0xc5, 0xfc, 0x4c, 0xb3 ]
+      arch: "CS_ARCH_ARCH"
+      options: [ "aarch64", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "sbfx x1, x2, #3, #2"
+        -
+          asm_text: "asr x3, x4, #63"
+        -
+          asm_text: "asr wzr, wzr, #31"
+        -
+          asm_text: "sbfx w12, w9, #0, #1"
+        -
+          asm_text: "ubfiz x4, x5, #52, #11"
+        -
+          asm_text: "ubfx xzr, x4, #0, #1"
+        -
+          asm_text: "ubfiz x4, xzr, #1, #6"
+        -
+          asm_text: "lsr x5, x6, #12"
+        -
+          asm_text: "bfi x4, x5, #52, #11"
+        -
+          asm_text: "bfxil xzr, x4, #0, #1"
+        -
+          asm_text: "bfi x4, xzr, #1, #6"
+        -
+          asm_text: "bfxil x5, x6, #12, #52"
diff --git a/suite/auto-sync/src/autosync/Tests/MCUpdaterTests/expected/multi/unified/test_a_arm64_v8.2a.txt.yaml b/suite/auto-sync/src/autosync/Tests/MCUpdaterTests/expected/multi/unified/test_a_arm64_v8.2a.txt.yaml
new file mode 100644
index 000000000..bad3cb31d
--- /dev/null
+++ b/suite/auto-sync/src/autosync/Tests/MCUpdaterTests/expected/multi/unified/test_a_arm64_v8.2a.txt.yaml
@@ -0,0 +1,32 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x41, 0x10, 0x43, 0x93, 0x83, 0xfc, 0x7f, 0x93, 0xff, 0x7f, 0x1f, 0x13, 0x2c, 0x01, 0x00, 0x13, 0xa4, 0x28, 0x4c, 0xd3, 0x9f, 0x00, 0x40, 0xd3, 0xe4, 0x17, 0x7f, 0xd3, 0xc5, 0xfc, 0x4c, 0xd3, 0xa4, 0x28, 0x4c, 0xb3, 0x9f, 0x00, 0x40, 0xb3, 0xe4, 0x17, 0x7f, 0xb3, 0xc5, 0xfc, 0x4c, 0xb3 ]
+      arch: "CS_ARCH_ARCH"
+      options: [ "arm64", "v8.2a" ]
+    expected:
+      insns:
+        -
+          asm_text: "sbfx x1, x2, #3, #2"
+        -
+          asm_text: "asr x3, x4, #63"
+        -
+          asm_text: "asr wzr, wzr, #31"
+        -
+          asm_text: "sbfx w12, w9, #0, #1"
+        -
+          asm_text: "ubfiz x4, x5, #52, #11"
+        -
+          asm_text: "ubfx xzr, x4, #0, #1"
+        -
+          asm_text: "ubfiz x4, xzr, #1, #6"
+        -
+          asm_text: "lsr x5, x6, #12"
+        -
+          asm_text: "bfi x4, x5, #52, #11"
+        -
+          asm_text: "bfxil xzr, x4, #0, #1"
+        -
+          asm_text: "bfc x4, #1, #6"
+        -
+          asm_text: "bfxil x5, x6, #12, #52"
diff --git a/suite/auto-sync/src/autosync/Tests/MCUpdaterTests/expected/multi/unified/test_b_arm64.txt.yaml b/suite/auto-sync/src/autosync/Tests/MCUpdaterTests/expected/multi/unified/test_b_arm64.txt.yaml
new file mode 100644
index 000000000..914ce4bad
--- /dev/null
+++ b/suite/auto-sync/src/autosync/Tests/MCUpdaterTests/expected/multi/unified/test_b_arm64.txt.yaml
@@ -0,0 +1,12 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x0a, 0x31, 0xd5, 0x80, 0x08, 0x31, 0xd5 ]
+      arch: "CS_ARCH_ARCH"
+      options: [ "arm64" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, TRCRSR"
+        -
+          asm_text: "mrs x0, TRCEXTINSELR"
diff --git a/suite/auto-sync/src/autosync/Tests/MCUpdaterTests/test_a.txt b/suite/auto-sync/src/autosync/Tests/MCUpdaterTests/test_a.txt
deleted file mode 100644
index 4e3379f72..000000000
--- a/suite/auto-sync/src/autosync/Tests/MCUpdaterTests/test_a.txt
+++ /dev/null
@@ -1,78 +0,0 @@
-# Test simple disassembly decoding tests
-
-# The RUN line parsing
-# RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+v8.1a --disassemble < %s | FileCheck %s
-# RUN: llvm-mc -triple=arm64 -mattr=+crc -disassemble < %s | FileCheck %s
-
-
-[0x00,0x0a,0x31,0xd5]
-# CHECK:   mrs x0, TRCRSR
-
-[0x80,0x08,0x31,0xd5]
-# CHECK:   mrs x0, TRCEXTINSELR
-
-[0x80,0x09,0x31,0xd5]
-# CHECK:   mrs x0, TRCEXTINSELR1
-
-# Now a block of instruction tests
-
-[0x41,0x01,0x00,0x19]
-[0x41,0x01,0x10,0x19]
-[0x62,0xf1,0x0f,0x19]
-[0xe3,0xd3,0x1f,0x19]
-#CHECK:       stlurb    w1, [x10]
-#CHECK-NEXT:  stlurb  w1, [x10, #-256]
-#CHECK-NEXT:  stlurb  w2, [x11, #255]
-#CHECK-NEXT:  stlurb  w3, [sp, #-3]
-
-# Now the other way around defined
-
-# CHECK: crc32b  w5, w7, w20
-//CHECK: crc32h  w28, wzr, w30
-# CHECK: crc32w  w0, w1, w2
-// CHECK: crc32x  w7, w9, x20
-# CHECK: crc32cb w9, w5, w4
-#CHECK: crc32ch w13, w17, w25
-# CHECK: crc32cw wzr, w3, w5
-# CHECK: crc32cx w18, w16, xzr
-0xe5 0x40 0xd4 0x1a
-0xfc 0x47 0xde 0x1a
-0x20 0x48 0xc2 0x1a
-0x27 0x4d 0xd4 0x9a
-0xa9 0x50 0xc4 0x1a
-0x2d 0x56 0xd9 0x1a
-0x7f 0x58 0xc5 0x1a
-0x12 0x5e 0xdf 0x9a
-
-# Now one line tests
-
-# CHECK-NEXT:  mrs     x0, AMCG1IDR_EL0        // encoding: [0xc0,0xd2,0x3b,0xd5]
-// CHECK-NEXT:  msr     AMEVCNTVOFF00_EL2, x0   // encoding: [0x00,0xd8,0x1c,0xd5]
-// CHECK:  msr     AMEVCNTVOFF00_EL2, x0   // encoding: [0x00,0xd8,0x1c,0xd5]
-
-# Annoying case. The last CHECK: <encdoding> should not be matched.
-
-[0x20,0x84,0xc2,0x6e] # sqrdmlah  v0.2d, v1.2d, v2.2d
-[0x20,0x8c,0xc2,0x6e] # sqrdmlsh  v0.2d, v1.2d, v2.2d
-# CHECK: warning: invalid instruction encoding
-# CHECK: [0x20,0x84,0x02,0x2e]
-
-
-[0x62,0xfc,0x44,0x2e]
-[0x62,0xfc,0x44,0x6e]
-# Dont' parse this:
-# NOBF16: warning: invalid instruction encoding
-# NOBF16-NEXT: [0x62,0xfc,0x44,0x2e]
-# NOBF16: warning: invalid instruction encoding
-# NOBF16-NEXT: [0x62,0xfc,0x44,0x6e]
-NOBF16-NEXT: [0x62,0xfc,0x44,0x2e]
-# But this please. It belongs to the encding above
-# CHECK: bfdot   v2.2s, v3.4h, v4.4h
-# CHECK: bfdot   v2.4s, v3.8h, v4.8h
-
-# Single digit hex numbers
-
-# CHECK: svc      #0
-# CHECK: svc      #{{65535|0xffff}}
-0x1 0x0 0x0 0xd4
-0xe1 0xff 0x1f 0xd4
diff --git a/suite/auto-sync/src/autosync/Tests/MCUpdaterTests/test_a.txt.cs b/suite/auto-sync/src/autosync/Tests/MCUpdaterTests/test_a.txt.cs
deleted file mode 100644
index a36dc2b50..000000000
--- a/suite/auto-sync/src/autosync/Tests/MCUpdaterTests/test_a.txt.cs
+++ /dev/null
@@ -1,27 +0,0 @@
-# CS_ARCH_ARCH, None, None
-# This regression test file is new. The option flags could not be determined.
-# LLVM uses the following mattr = ['mattr=+v8.1a', 'mattr=+crc']
-0x00,0x0a,0x31,0xd5 == mrs x0, TRCRSR
-0x80,0x08,0x31,0xd5 == mrs x0, TRCEXTINSELR
-0x80,0x09,0x31,0xd5 == mrs x0, TRCEXTINSELR1
-0x41,0x01,0x00,0x19 == stlurb    w1, [x10]
-0x41,0x01,0x10,0x19 == stlurb  w1, [x10, #-256]
-0x62,0xf1,0x0f,0x19 == stlurb  w2, [x11, #255]
-0xe3,0xd3,0x1f,0x19 == stlurb  w3, [sp, #-3]
-0xe5 0x40 0xd4 0x1a == crc32b  w5, w7, w20
-0xfc 0x47 0xde 0x1a == crc32h  w28, wzr, w30
-0x20 0x48 0xc2 0x1a == crc32w  w0, w1, w2
-0x27 0x4d 0xd4 0x9a == crc32x  w7, w9, x20
-0xa9 0x50 0xc4 0x1a == crc32cb w9, w5, w4
-0x2d 0x56 0xd9 0x1a == crc32ch w13, w17, w25
-0x7f 0x58 0xc5 0x1a == crc32cw wzr, w3, w5
-0x12 0x5e 0xdf 0x9a == crc32cx w18, w16, xzr
-0xc0,0xd2,0x3b,0xd5 == mrs     x0, AMCG1IDR_EL0
-0x00,0xd8,0x1c,0xd5 == msr     AMEVCNTVOFF00_EL2, x0
-0x00,0xd8,0x1c,0xd5 == msr     AMEVCNTVOFF00_EL2, x0
-0x20,0x84,0xc2,0x6e == sqrdmlah  v0.2d, v1.2d, v2.2d
-0x20,0x8c,0xc2,0x6e == sqrdmlsh  v0.2d, v1.2d, v2.2d
-0x62,0xfc,0x44,0x2e == bfdot   v2.2s, v3.4h, v4.4h
-0x62,0xfc,0x44,0x6e == bfdot   v2.4s, v3.8h, v4.8h
-0x1 0x0 0x0 0xd4 == svc      #0
-0xe1 0xff 0x1f 0xd4 == svc      #{{65535|0xffff}}
diff --git a/suite/auto-sync/src/autosync/Tests/test_mcupdater.py b/suite/auto-sync/src/autosync/Tests/test_mcupdater.py
index 34c42ee42..eefa20517 100644
--- a/suite/auto-sync/src/autosync/Tests/test_mcupdater.py
+++ b/suite/auto-sync/src/autosync/Tests/test_mcupdater.py
@@ -1,10 +1,13 @@
 # SPDX-FileCopyrightText: 2024 Rot127 <unisono@quyllur.org>
 # SPDX-License-Identifier: BSD-3
+
 import logging
+import os
 import sys
 import unittest
+from pathlib import Path
 
-from autosync.Helper import get_path
+from autosync.Helper import get_path, test_only_overwrite_path_var
 from autosync.MCUpdater import MCUpdater
 
 
@@ -17,43 +20,173 @@ class TestHeaderPatcher(unittest.TestCase):
             format="%(levelname)-5s - %(message)s",
             force=True,
         )
-        cls.updater = MCUpdater(
-            "ARCH", get_path("{MCUPDATER_TEST_DIR}"), [r".*\.cs"], None
+
+    def test_test_case_gen(self):
+        """
+        To enforce sequential execution of the tests, we execute them in here.
+        And don't make them a separated test.
+        """
+        self.assertTrue(self.unified_test_cases(), "Failed: unified_test_cases")
+        self.assertTrue(self.separated_test_cases(), "Failed: separated_test_cases")
+        self.assertTrue(
+            self.multi_mode_unified_test_cases(),
+            "Failed: multi_mode_unified_test_cases",
+        )
+        self.assertTrue(
+            self.multi_mode_separated_test_cases(),
+            "Failed: multi_mode_separated_test_cases",
         )
 
-    def test_parsing(self):
-        self.updater.included.append("test_a.txt")
-        self.updater.gen_tests_in_dir(self.updater.mc_dir)
-        self.assertEqual(len(self.updater.test_files), 1)
-        self.assertListEqual(
-            self.updater.test_files["test_a.txt"].mattrs, ["mattr=+v8.1a", "mattr=+crc"]
+    def unified_test_cases(self):
+        out_dir = Path(
+            get_path("{MCUPDATER_TEST_OUT_DIR}").joinpath("merged").joinpath("unified")
         )
-        self.assertEqual(len(self.updater.test_files["test_a.txt"].tests), 24)
-        self.assertEqual(
-            self.updater.test_files["test_a.txt"].manager.get_num_incomplete(), 0
-        )
-        with open(get_path("{MCUPDATER_TEST_DIR}").joinpath("test_a.txt.cs")) as f:
-            correct = f.read()
-        self.assertEqual(
-            correct, self.updater.test_files["test_a.txt"].get_cs_testfile_content()
+        if not out_dir.exists():
+            out_dir.mkdir(parents=True)
+        for file in out_dir.iterdir():
+            logging.debug(f"Delete old file: {file}")
+            os.remove(file)
+        test_only_overwrite_path_var(
+            "{MCUPDATER_OUT_DIR}",
+            out_dir,
         )
+        self.updater = MCUpdater("ARCH", get_path("{MCUPDATER_TEST_DIR}"), [], [], True)
+        self.updater.gen_all()
+        return self.compare_files(out_dir, ["test_a.txt.yaml", "test_b.txt.yaml"])
 
-    def test_adding_header_from_mc(self):
+    def separated_test_cases(self):
+        out_dir = Path(
+            get_path("{MCUPDATER_TEST_OUT_DIR}")
+            .joinpath("merged")
+            .joinpath("separated")
+        )
+        if not out_dir.exists():
+            out_dir.mkdir(parents=True)
+        for file in out_dir.iterdir():
+            logging.debug(f"Delete old file: {file}")
+            os.remove(file)
+        test_only_overwrite_path_var(
+            "{MCUPDATER_OUT_DIR}",
+            out_dir,
+        )
         self.updater = MCUpdater(
-            arch="ARM",
-            mc_dir=get_path("{MCUPDATER_TEST_DIR}"),
-            excluded=[r".*\.cs"],
-            included=None,
+            "ARCH", get_path("{MCUPDATER_TEST_DIR}"), [], [], False
         )
-        self.updater.gen_tests_in_dir(self.updater.mc_dir)
-        self.assertEqual(len(self.updater.test_files), 3)
-        self.assertListEqual(self.updater.test_files["cps.s"].mattrs, [])
-        self.assertEqual(len(self.updater.test_files["cps.s"].tests), 1)
-        self.assertEqual(
-            self.updater.test_files["cps.s"].manager.get_num_incomplete(), 0
+        self.updater.gen_all()
+        return self.compare_files(out_dir, ["test_a.txt.yaml", "test_b.txt.yaml"])
+
+    def multi_mode_unified_test_cases(self):
+        out_dir = Path(
+            get_path("{MCUPDATER_TEST_OUT_DIR}").joinpath("multi").joinpath("unified")
         )
-        with open(get_path("{MCUPDATER_TEST_DIR}").joinpath("cps.s.cs")) as f:
-            correct = f.read()
-        self.assertEqual(
-            correct, self.updater.test_files["cps.s"].get_cs_testfile_content()
+        if not out_dir.exists():
+            out_dir.mkdir(parents=True)
+        for file in out_dir.iterdir():
+            logging.debug(f"Delete old file: {file}")
+            os.remove(file)
+        test_only_overwrite_path_var(
+            "{MCUPDATER_OUT_DIR}",
+            out_dir,
         )
+        self.updater = MCUpdater(
+            "ARCH", get_path("{MCUPDATER_TEST_DIR}"), [], [], True, multi_mode=True
+        )
+        self.updater.gen_all()
+        return self.compare_files(
+            out_dir,
+            [
+                "test_a_aarch64_v8a__fp_armv8.txt.yaml",
+                "test_a_arm64_v8.2a.txt.yaml",
+                "test_b_arm64.txt.yaml",
+            ],
+        )
+
+    def multi_mode_separated_test_cases(self):
+        out_dir = Path(
+            get_path("{MCUPDATER_TEST_OUT_DIR}").joinpath("multi").joinpath("separated")
+        )
+        if not out_dir.exists():
+            out_dir.mkdir(parents=True)
+        for file in out_dir.iterdir():
+            logging.debug(f"Delete old file: {file}")
+            os.remove(file)
+        test_only_overwrite_path_var(
+            "{MCUPDATER_OUT_DIR}",
+            out_dir,
+        )
+        self.updater = MCUpdater(
+            "ARCH", get_path("{MCUPDATER_TEST_DIR}"), [], [], False, multi_mode=True
+        )
+        self.updater.gen_all()
+        return self.compare_files(
+            out_dir,
+            [
+                "test_a_aarch64_v8a__fp_armv8.txt.yaml",
+                "test_a_arm64_v8.2a.txt.yaml",
+                "test_b_arm64.txt.yaml",
+            ],
+        )
+
+    def test_no_symbol_tests(self):
+        out_dir = Path(get_path("{MCUPDATER_TEST_OUT_DIR}").joinpath("no_symbol"))
+        if not out_dir.exists():
+            out_dir.mkdir(parents=True)
+        for file in out_dir.iterdir():
+            logging.debug(f"Delete old file: {file}")
+            os.remove(file)
+        test_only_overwrite_path_var(
+            "{MCUPDATER_OUT_DIR}",
+            out_dir,
+        )
+        self.updater = MCUpdater(
+            "ARCH",
+            get_path("{MCUPDATER_TEST_DIR}"),
+            [],
+            [],
+            False,
+        )
+        self.updater.gen_all()
+        self.assertFalse(
+            out_dir.joinpath("test_no_symbol.s.txt.yaml").exists(),
+            "File should not exist",
+        )
+
+    def compare_files(self, out_dir: Path, filenames: list[str]) -> bool:
+        if not out_dir.is_dir():
+            logging.error(f"{out_dir} is not a directory.")
+            return False
+
+        parent_name = out_dir.parent.name
+        expected_dir = (
+            get_path("{MCUPDATER_TEST_DIR_EXPECTED}")
+            .joinpath(parent_name)
+            .joinpath(out_dir.name)
+        )
+        if not expected_dir.exists() or not expected_dir.is_dir():
+            logging.error(f"{expected_dir} is not a directory.")
+            return False
+        for file in filenames:
+            efile = expected_dir.joinpath(file)
+            if not efile.exists():
+                logging.error(f"{efile} does not exist")
+                return False
+            with open(efile) as f:
+                logging.debug(f"Read {efile}")
+                expected = f.read()
+
+            afile = out_dir.joinpath(file)
+            if not afile.exists():
+                logging.error(f"{afile} does not exist")
+                return False
+            with open(afile) as f:
+                logging.debug(f"Read {afile}")
+                actual = f.read()
+            if expected != actual:
+                logging.error("Files mismatch")
+                print(f"Expected: {efile}")
+                print(f"Actual: {afile}\n")
+                print(f"Expected:\n\n{expected}\n")
+                print(f"Actual:\n\n{actual}\n")
+                return False
+            logging.debug(f"OK: actual == expected")
+        return True
diff --git a/suite/auto-sync/src/autosync/cpptranslator/Differ.py b/suite/auto-sync/src/autosync/cpptranslator/Differ.py
index 03aef025e..8cc2a39ad 100755
--- a/suite/auto-sync/src/autosync/cpptranslator/Differ.py
+++ b/suite/auto-sync/src/autosync/cpptranslator/Differ.py
@@ -851,6 +851,10 @@ class Differ:
             filename, node_id = self.all_choices_saved(
                 old_filepath, new_file[k]["nodes"], old_file[k]["nodes"]
             )
+            if not node_id:
+                # Edge case of file has all nodes matching. And therefore has
+                # no decision saved because the user never was asked.
+                continue
             if filename or node_id:
                 print(
                     f"{get_path('{DIFFER_PERSISTENCE_FILE}').name} is not up-to-date!\n"
@@ -918,7 +922,7 @@ def parse_args() -> argparse.Namespace:
         "-a",
         dest="arch",
         help="Name of target architecture (ignored with -t option)",
-        choices=["ARM", "PPC", "AArch64", "Alpha"],
+        choices=["ARM", "PPC", "AArch64", "Alpha", "LoongArch"],
         required=True,
     )
     parser.add_argument(
diff --git a/suite/auto-sync/src/autosync/cpptranslator/saved_patches.json b/suite/auto-sync/src/autosync/cpptranslator/saved_patches.json
index 8fe03810d..ba5380dd0 100644
--- a/suite/auto-sync/src/autosync/cpptranslator/saved_patches.json
+++ b/suite/auto-sync/src/autosync/cpptranslator/saved_patches.json
@@ -1,1506 +1,4 @@
 {
-  "ARMDisassembler.c": {
-    "AddThumb1SBit": {
-      "apply_type": "OLD",
-      "old_hash": "e16fd83b02dc4539a153f003f89ecd789699e8c689212e8a051fd7dfd71515be",
-      "new_hash": "0b07623e68389bb5cadccad8f9bbf609da2cb3290bb0eda48d70fb272dd24740",
-      "edit": ""
-    },
-    "AddThumbPredicate": {
-      "apply_type": "OLD",
-      "old_hash": "8f80910dc0f93f0228e5146baca8edf6da72a6b57594938ed637b0a23b0a4225",
-      "new_hash": "268bc4f2284655b632d6465e28e0ccb698089b9ca8d31ac4e003de3271b0959c",
-      "edit": ""
-    },
-    "DecodeBankedReg": {
-      "apply_type": "OLD",
-      "old_hash": "591ff78f00921ed414fa6a59f4f6640077bded5d091aaefc5b70cf0aa78467b4",
-      "new_hash": "c7683990b16d1e08d33b257943b9367942ff633782e2a435e761c55bc5287a2d",
-      "edit": ""
-    },
-    "DecodeCoprocessor": {
-      "apply_type": "OLD",
-      "old_hash": "cc712cea5428075692669b3710f0b09e5310a455f92256436a4bdaf6e151b57e",
-      "new_hash": "daa85b7f91aac75ff19cb6d86ae64dd250607267385e6b14739f150b74d5aef2",
-      "edit": ""
-    },
-    "DecodeDPRRegListOperand": {
-      "apply_type": "OLD",
-      "old_hash": "a7a204c5f5526cfafedf94d7a190357289b1429029f9a04f43512bd452a4c13d",
-      "new_hash": "873fd7c40cbe345fface74171973599c7ebdd88f1d10639a4c38c36d8925531d",
-      "edit": ""
-    },
-    "DecodeLOLoop": {
-      "apply_type": "OLD",
-      "old_hash": "6d19cf244c1ad61065307dcee6d83f242687335a904c6f5e48b99d7a43821300",
-      "new_hash": "92d03993387cb3f2a89a487f41c7a1eda1e7c712489ed82d10e4cfbd730d672f",
-      "edit": ""
-    },
-    "DecodeMVEOverlappingLongShift": {
-      "apply_type": "OLD",
-      "old_hash": "a54bdf2f7e6acc5c897ceda54d9e06b38280031fa5affab7f7342a090b8149a9",
-      "new_hash": "ce92360c0070cb0bb6d3141e7da1aad93def0c89d0a1bc6956666b86932eaef0",
-      "edit": ""
-    },
-    "DecodeNEONComplexLane64Instruction": {
-      "apply_type": "OLD",
-      "old_hash": "385087526ea2f96921c0acdc5031e58289b362dc879617d67b6ad360f5f6650c",
-      "new_hash": "d515a9bf62f84f761c87038d4ef8dd524ce5f1732c27c571ca34eb24df553a01",
-      "edit": ""
-    },
-    "DecodePredicateOperand": {
-      "apply_type": "OLD",
-      "old_hash": "11c75b2eebe14a12b404685d28e860efc317ba3ec3a2fe1be690768bb6dcdd74",
-      "new_hash": "25af886f52628b188c04f49c943dabd4fdeb7cc2f36b1996fe23c46538dec630",
-      "edit": ""
-    },
-    "DecodeRegListOperand": {
-      "apply_type": "OLD",
-      "old_hash": "03b7f5eb4616cb71b6cab451cc206d209c24f72af691111a5a0e8d928249f34f",
-      "new_hash": "c6385d9305c219139648b25b6ad565efb632fe98eb240e74ef2505a54def59df",
-      "edit": ""
-    },
-    "DecodeSORegMemOperand": {
-      "apply_type": "OLD",
-      "old_hash": "29550703c82a70275340d930c4b810b77a2cb31acde412321b7a12368de866d5",
-      "new_hash": "da86338e5af47615570d63e8871bc85786cc666af3cca282e748afaca30092e4",
-      "edit": ""
-    },
-    "DecodeSPRRegListOperand": {
-      "apply_type": "OLD",
-      "old_hash": "62f44fc1ce2dd99a384cafc88b548db13f72c1ad570c1b78170acc92c358a8f0",
-      "new_hash": "e735b1996fa4e46588f0eda8053f703889f2450bbfa9e3d68a4949e6a34ceb1f",
-      "edit": ""
-    },
-    "DecodeVpredNOperand": {
-      "apply_type": "OLD",
-      "old_hash": "",
-      "new_hash": "f75ffc6297941d5b99c59b80e4541d09d8dfd2aa579300a349bd59f284c0c368",
-      "edit": ""
-    },
-    "UpdateThumbVFPPredicate": {
-      "apply_type": "OLD",
-      "old_hash": "e7ddf147351b4f50ec9873669ca873383beb837dd9b487bcc095e68cf82d61a5",
-      "new_hash": "0e92a16b350185abea1aa073bff5fe5a03b3394dd842700b5f11251b50605a4a",
-      "edit": ""
-    },
-    "checkDecodedInstruction": {
-      "apply_type": "OLD",
-      "old_hash": "69e2594d21a456a8c4278918d9a61e48dc9f72a4a1f6ab4036d076122397c7f1",
-      "new_hash": "afc0e9b79bb308fe0bc83e43b45f194bb3586b8b22e0f35db27dbd5aac5ee6c6",
-      "edit": ""
-    },
-    "createARMDisassembler": {
-      "apply_type": "OLD",
-      "old_hash": "",
-      "new_hash": "606ce64d2ffb7388277a2167d951b14bec44db29d7fcba17c19c5eea0f6e4f58",
-      "edit": ""
-    },
-    "endianSensitiveOpcode16": {
-      "apply_type": "OLD",
-      "old_hash": "62d92f7c8bac5715e5d6b4a5f24d9db2bf4bbe65908df8db065f21d6acc9f3b3",
-      "new_hash": "",
-      "edit": ""
-    },
-    "endianSensitiveOpcode32": {
-      "apply_type": "OLD",
-      "old_hash": "cc04456b7311c419f71f4e3df699d268a757f44b74107c89319b6a5f33f94202",
-      "new_hash": "",
-      "edit": ""
-    },
-    "getARMInstruction": {
-      "apply_type": "OLD",
-      "old_hash": "991fe5885c6cba420d46d0b0b6365612116c091b6afd03e08af86620b5ae054e",
-      "new_hash": "77a9a2ccf0ff001ba8b7a767b4fb724c13ecf98157b20b16da6e4b29e0a8a741",
-      "edit": ""
-    },
-    "getInstruction": {
-      "apply_type": "OLD",
-      "old_hash": "103b8e5e79d3f02012e777e72620ccb3b4ebfb9ca4046cf3ab3f0d0aa741c397",
-      "new_hash": "2ca1ebf16c1a881f4baf7521655027af1dce0139c29a6bc36e32472d522994d3",
-      "edit": ""
-    },
-    "getThumbInstruction": {
-      "apply_type": "OLD",
-      "old_hash": "81b172eabb79001c03f54cab171241da27e59939f42b89245bc1aca01372ac5b",
-      "new_hash": "73763b1aa82f419f2ab35287b5258b172f7d5aaab50a0830745a64aeda26adf3",
-      "edit": ""
-    },
-    "suggestBytesToSkip": {
-      "apply_type": "OLD",
-      "old_hash": "",
-      "new_hash": "0aa21749305ce0d629fc521ce34f2e0b37aa6c3df7adbbbdfefd68d2d9aa902b",
-      "edit": ""
-    },
-    "tryAddingPcLoadReferenceComment": {
-      "apply_type": "OLD",
-      "old_hash": "bd518e25602001178dcc1d96c4f087f726060909fe6ae4ab0bfa56caf6bcf5d0",
-      "new_hash": "dfe5eeae157c1dfe6ac79e5145e573b744e64c5ed743240bf3979722e152f35b",
-      "edit": ""
-    },
-    "tryAddingSymbolicOperand": {
-      "apply_type": "OLD",
-      "old_hash": "f87c74198ad758f08700947dccf281ba1d068a31290cd921e70b0653893d2d44",
-      "new_hash": "acf81a43081f705ad92fd9f2e295eb0c5b983d67793d03490f1aeb9776ff65aa",
-      "edit": ""
-    },
-    "isVectorPredicable": {
-      "apply_type": "OLD",
-      "old_hash": "e0025f215966ee66db69bb0a71f1376707c17f753b1dc77f6ca4853db9fadc2f",
-      "new_hash": "1fde7ed766d751e64cbea32d32b42f4162c8d58cfe997ed17060f425f5c89eb7",
-      "edit": ""
-    },
-    "\"../../MathExtras.h\"": {
-      "apply_type": "OLD",
-      "old_hash": "c6ce14448320faf6eb6a6386c8917b014947f3ffe02d3741941e3acbb23f408d",
-      "new_hash": "",
-      "edit": ""
-    },
-    "\"ARMDisassemblerExtension.h\"": {
-      "apply_type": "OLD",
-      "old_hash": "851288252991845820ca25879f96f74e61c35f315acea1453f88d6622e1d4303",
-      "new_hash": "",
-      "edit": ""
-    },
-    "\"ARMGenInstrInfo.inc\"": {
-      "apply_type": "OLD",
-      "old_hash": "ca97dd129bda8d7161b6732f2c1b80c70e1d64be483c824f46f54ce4e1f172a3",
-      "new_hash": "",
-      "edit": ""
-    },
-    "/* Capstone's C++ file translator: */": {
-      "apply_type": "NEW",
-      "old_hash": "",
-      "new_hash": "b1ea27f4adc10229946cced84510362e2b8561030cfe6dee4df30b1fa8df4458",
-      "edit": ""
-    },
-    "/* For multiple similiar edits, please create a Patch for the translator. */": {
-      "apply_type": "NEW",
-      "old_hash": "",
-      "new_hash": "31b4c019cfb61410081d33444965f1c2fffd36d91105400ac4ed3325e9092a25",
-      "edit": ""
-    },
-    "/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */": {
-      "apply_type": "NEW",
-      "old_hash": "",
-      "new_hash": "98bc99aadc54580ddc91940c36e2b15287de7946ca6d731b81e2b56f40a2c0a0",
-      "edit": ""
-    },
-    "// end namespace llvm": {
-      "apply_type": "NEW",
-      "old_hash": "11db4f68c44ac574388a19898cbd3a0df9f6058e57c1b137e91cc7f591087353",
-      "new_hash": "",
-      "edit": ""
-    },
-    "/// ARM disassembler for all ARM platforms.": {
-      "apply_type": "NEW",
-      "old_hash": "",
-      "new_hash": "3c4bb90e3955714234a70a4478737cd7fc9199907554d722d53a1667e5ae9266",
-      "edit": ""
-    },
-    "DecodeT2AddSubSPImm": {
-      "apply_type": "OLD",
-      "old_hash": "9892c4f47a1d4e935970a08e09ba7d1f0010f23b54248142b4add2c8b3e66ea7",
-      "new_hash": "6f5bac5b333965df6a2fdf0ef49141651dd5203966ea221d6b4744ceb034bdc3",
-      "edit": ""
-    }
-  },
-  "ARMInstPrinter.c": {
-    "DEFINE_printAddrMode3Operand": {
-      "apply_type": "OLD",
-      "old_hash": "af7ea9416ba2cc6ede4f38fd7ed7a3c2ae5b4fa3e4baf64c066e0c7934f8f47b",
-      "new_hash": "2b9a93b6041a6835b40560d21110f72ba75bfc587e21dfe455b558c03eefb75f",
-      "edit": ""
-    },
-    "DEFINE_printAddrMode5FP16Operand": {
-      "apply_type": "OLD",
-      "old_hash": "fd9d633a61805162dd594a75960f7249f29f0860d1282fdeb86c5ec61751106a",
-      "new_hash": "83a3a526a1062a3c9b44b8e0d1e90be9814a46ed82e7bc5430b9cb0ea06e6137",
-      "edit": ""
-    },
-    "DEFINE_printAddrMode5Operand": {
-      "apply_type": "OLD",
-      "old_hash": "846db22d9ffd5b6a2880560f2024b31fff69a7cccc7a7bec960bb15db2e1a44a",
-      "new_hash": "4c2e9a485f7656e68350e2c0ddaccb533bf2f735de1a6959e5b4b5f9088d097d",
-      "edit": ""
-    },
-    "DEFINE_printAddrModeImm12Operand": {
-      "apply_type": "OLD",
-      "old_hash": "ec820754ffb1f31c0fb40486c6f3bb3b5c7069010ad95ca0ba7c76cae7af2847",
-      "new_hash": "c24bc49c480c4cd7cb9c704c90fcb47e19526a5f3b5f5467277dcd4116197273",
-      "edit": ""
-    },
-    "DEFINE_printAdrLabelOperand": {
-      "apply_type": "OLD",
-      "old_hash": "3080ddb15e84c493c4971cbdf6d3347a478d75f6452598650676a77cf1a9990f",
-      "new_hash": "5c0576e89fbddaf5b3565960fbafb124a15febd98aa787a4ede5322976e4090f",
-      "edit": ""
-    },
-    "DEFINE_printComplexRotationOp": {
-      "apply_type": "OLD",
-      "old_hash": "7c8fb93bbc82f8691d638671a0e547b26c39864a57f5afcf1fad8bd992374752",
-      "new_hash": "637fed4e607334f94c4820d71b56d38e6d917c1fd8809855b2520c19ecc3d233",
-      "edit": ""
-    },
-    "DEFINE_printMVEVectorList": {
-      "apply_type": "OLD",
-      "old_hash": "9dfb1a71d6d828c919c6bc217a346c37d622fa56d369f22f51c7889fb5285158",
-      "new_hash": "92fbf764f6efefb68befc890dca5cb5b3ea3a97d68ac43ffa2f7ec0bfda5e422",
-      "edit": ""
-    },
-    "DEFINE_printMveAddrModeRQOperand": {
-      "apply_type": "OLD",
-      "old_hash": "6abd4b1369876754b5c0662f7064a9d9ca77a2fcc55565e000ad017fbc1c5056",
-      "new_hash": "e68fef2691a4b1183c3ff98be9feb65525df46b8de61757c3656f6e9ef9f4fb0",
-      "edit": ""
-    },
-    "DEFINE_printT2AddrModeImm8Operand": {
-      "apply_type": "OLD",
-      "old_hash": "eff8301730a686100632b69f02afdeb56035114ffa080ffc61621153b27338d3",
-      "new_hash": "cb5d2159ce8fe5213ccbc6445c68c8a5ca6592523a5c863a512600d6db4dedba",
-      "edit": ""
-    },
-    "DEFINE_printT2AddrModeImm8s4Operand": {
-      "apply_type": "OLD",
-      "old_hash": "df809120708a14ea78e4327720d45508f651896b2b5682d8bb91190b75b75e30",
-      "new_hash": "c6d55fdc81a855db87090c4bf75cf2148f168af3db14d2913b28bc1bec0f3145",
-      "edit": ""
-    },
-    "applyTargetSpecificCLOption": {
-      "apply_type": "OLD",
-      "old_hash": "",
-      "new_hash": "1939abc1c7e369df85230bae9d6cb351140861961d09a79108b648a1bf7d4670",
-      "edit": ""
-    },
-    "printAM2PreOrOffsetIndexOp": {
-      "apply_type": "OLD",
-      "old_hash": "1fdbd48631dbcf8f626c4f0b51ed7305717eeca7f7e003c13b8903b635661a59",
-      "new_hash": "58d6e2fdbe27f1d3bce462d33f9d5055f679ef3d2409f2e8c316bf7ba6f7eb18",
-      "edit": ""
-    },
-    "printAM3PreOrOffsetIndexOp": {
-      "apply_type": "OLD",
-      "old_hash": "a26eb2f383267adea6ccf73a9135cedcf76224aed297546697a9bc91e02a6726",
-      "new_hash": "74ea21a49410da52792d905187f111b2006f09fe6d564d32f5771b4f085cb54c",
-      "edit": ""
-    },
-    "printAddrMode2OffsetOperand": {
-      "apply_type": "OLD",
-      "old_hash": "c1b30a543967f380b19268c183b0e27c9dd1ba3df757eb2d8b791a4a3a0f1e7f",
-      "new_hash": "4a63705970d00ae5433afb7e2052e6fac649565c37ca0130422c2449ff9b528e",
-      "edit": ""
-    },
-    "printAddrMode2Operand": {
-      "apply_type": "OLD",
-      "old_hash": "230d465ca69ac5473beb0f4a6f1d5c10889f6e641fee285a827efe060d00a6ef",
-      "new_hash": "0cf0e43712f47bdc9f27da66f6f4d27c81a7780f1ad545d8b0e7927df7688ef3",
-      "edit": ""
-    },
-    "printAddrMode3OffsetOperand": {
-      "apply_type": "OLD",
-      "old_hash": "09c12dd52372078a4b40c9f1ac5307de4483835682d0dc0d6ef34178ec8176d8",
-      "new_hash": "3d334ad4d88b692b83860225d494bde88b55e6b9c1aa21d0361ff91448c2ea6c",
-      "edit": ""
-    },
-    "printAddrMode6Operand": {
-      "apply_type": "OLD",
-      "old_hash": "b4fe0818f81a87e7846492b6e4b0e940cc7a7754c68294bc84edf74f8d605a9d",
-      "new_hash": "812ef2e29246185246fad917ba3e563ca354b7df63d06add221a906442ccbf74",
-      "edit": ""
-    },
-    "printAddrModeTBB": {
-      "apply_type": "OLD",
-      "old_hash": "2b6af4d44046ed26cc4907bbdbce871f58be9306031974e75118bb06873c94f4",
-      "new_hash": "86e68e07e3e39fa03f166aef4b8c159535eefcbb1208dd10da93c18e3c4ad990",
-      "edit": ""
-    },
-    "printAddrModeTBH": {
-      "apply_type": "OLD",
-      "old_hash": "585f957d549eee873ba6b63c87e578c52039c1195bd75b773063e61bef23ed2d",
-      "new_hash": "c4c65926f574a9e53965a9e1cbe722c216eb4d3003a1e65aaa10d69d580ceeb8",
-      "edit": ""
-    },
-    "printBankedRegOperand": {
-      "apply_type": "OLD",
-      "old_hash": "43743a8b9716df5836df06c6152617cf3cc990c4fc9d0bb3b28d78f35f8fdfa5",
-      "new_hash": "b01a60a479b0d736ff85868dc7abc5835f2465c0b9f019f79337f23171779cb9",
-      "edit": ""
-    },
-    "printBitfieldInvMaskImmOperand": {
-      "apply_type": "OLD",
-      "old_hash": "69a5a2c342bbd121ec05acc8449754f5e4156ac71a1258c69e5002c03ee75a34",
-      "new_hash": "e4969f0b3649a32e96d2067b4b7fe34e84cb116d91559ec9e716dc2b58502d45",
-      "edit": ""
-    },
-    "printCImmediate": {
-      "apply_type": "OLD",
-      "old_hash": "afcb089aad56b5fa5f0be84f20c1211982a20b90b29cc7f38cd3ad02ba6e3cff",
-      "new_hash": "18189a16121e22d13f068b9e5c854fdaf7b093a03899f363320b21d115e6a802",
-      "edit": ""
-    },
-    "printCoprocOptionImm": {
-      "apply_type": "OLD",
-      "old_hash": "d8022789f9bce2fed4423f14122462a11ae1044a7bd8d05b8722ff1e86823c99",
-      "new_hash": "7535754b2a47fae26076816d8a5a9d68a5270b328454ce0d39e9067eceabca0e",
-      "edit": ""
-    },
-    "printFBits16": {
-      "apply_type": "OLD",
-      "old_hash": "d786587739a17c72c7ddf969ace7912bd5d7f15f10d34efbf106bb163f10aa5a",
-      "new_hash": "056e4db3f03d21c832f867cc7e07e61f0f212d0faec8ea530d9c04c97bc703ac",
-      "edit": ""
-    },
-    "printFBits32": {
-      "apply_type": "OLD",
-      "old_hash": "cf8b1fbec5f2523b933028dd0ed39912d4783035d79522e79c718fd05639a67d",
-      "new_hash": "0b4c176919da4632010afd57004125c958e5ad6ec467cdaf4245c178aab8eb3e",
-      "edit": ""
-    },
-    "printFPImmOperand": {
-      "apply_type": "OLD",
-      "old_hash": "f145952b34b4c7651b5ec4b42e5ca351f39f386d5cb7bc31e238b50626fd089c",
-      "new_hash": "14deaa47743b68acb3f5dbc260cc7815e2bb4d4fb37ebd112d9c2b0555592219",
-      "edit": ""
-    },
-    "printImmPlusOneOperand": {
-      "apply_type": "OLD",
-      "old_hash": "ec1dafafd60de21c0a274d68812f99e12f0baaff5067f184e4374ff2b37a28f7",
-      "new_hash": "7700056069222c71a5a6bce4723ab8e5192e903269fe8cbb7dbcb948c1b3b746",
-      "edit": ""
-    },
-    "printInst": {
-      "apply_type": "OLD",
-      "old_hash": "c751d526f6b3f56656df1f7744b52770d5e59e14c03c32f1eb82f8f2a3640d0c",
-      "new_hash": "679cadb26bb1e0e1980c949417ddf015ea1cbc2b72faf149ffe1757c431e8a9a",
-      "edit": ""
-    },
-    "printLdStmModeOperand": {
-      "apply_type": "OLD",
-      "old_hash": "4990300d297524408a55bc945388d4ce6465b1585ad2bf4b6493a0d7e3dc3e20",
-      "new_hash": "15fec9399f83d47d8ced75d1e71de628c0ec1b6a94aac0dabfeea17a2d6130f4",
-      "edit": ""
-    },
-    "printMSRMaskOperand": {
-      "apply_type": "OLD",
-      "old_hash": "96bc50d1f859e84eaced0bae7d072df9dcd3682ea3440d0ad3604fba59105cc2",
-      "new_hash": "1188aa817281efe36d31cb4b71d01880bff211cec256e679605c9d49c265f440",
-      "edit": ""
-    },
-    "printMandatoryInvertedPredicateOperand": {
-      "apply_type": "OLD",
-      "old_hash": "d89595b75c7ce86a7c9a4d1e9cb8813ea3b16624294c7e82251f42a74e0573c9",
-      "new_hash": "f466f0aef159a8585b8f819ac7ec81801f23ed8a87b32fa8565fd04ff5f60d7c",
-      "edit": ""
-    },
-    "printMandatoryPredicateOperand": {
-      "apply_type": "OLD",
-      "old_hash": "f055949e40ea6e2c156fb2666a1286884eefefd2c5ffda513d3a651fab437928",
-      "new_hash": "869c0a7b9cff8b6e49c4d1a831497d30fff928f406d16b5d319f830b5167a71c",
-      "edit": ""
-    },
-    "printMandatoryRestrictedPredicateOperand": {
-      "apply_type": "OLD",
-      "old_hash": "5cb657d162c7f209b211ff648f78d81207139da616ee2525f355f88bef392c07",
-      "new_hash": "264a03894fbecaa1905c0e813d8d97b6bb1750c4c317a6fd9e392658bcbc3576",
-      "edit": ""
-    },
-    "printMemBOption": {
-      "apply_type": "OLD",
-      "old_hash": "84e89538daa5f2372cf30aee9380570c55d1889e26e65976c5fc283e5c3989db",
-      "new_hash": "03464e08ad25c3e5d89e7196ea07f068879813ff803a96fe7a29b240e6a87370",
-      "edit": ""
-    },
-    "printModImmOperand": {
-      "apply_type": "OLD",
-      "old_hash": "08e8cec6f9b66f2b1abb8df29785fee3a3592c8df7f8b8fb03ff1412fc4fba37",
-      "new_hash": "68ed77cd5ddb655c1772c47a4574cbb921b6fb952f8cec394cd75cef50545b2e",
-      "edit": ""
-    },
-    "printMveSaturateOp": {
-      "apply_type": "OLD",
-      "old_hash": "19041125e884b3bcfdebd4a88c316dbff6ed17637baac100fc35681db10f3346",
-      "new_hash": "8daaad36c055497f8ba1ebb559fd65c427fec3c74576d6c216a9fac73e784835",
-      "edit": ""
-    },
-    "printNoHashImmediate": {
-      "apply_type": "OLD",
-      "old_hash": "5eca0dcad4b6a9556639c1e27d56eafd7148cc22ff5c44dcb86d39b322cae69e",
-      "new_hash": "6ba021d35466d081b88b56b2e6d8920533c77885bb8b7eaa8185b0c026c00396",
-      "edit": ""
-    },
-    "printOperand": {
-      "apply_type": "OLD",
-      "old_hash": "e66c45ad0c409969e9df95f5044663751e871c72e460db73e7e98f3065f640dd",
-      "new_hash": "",
-      "edit": ""
-    },
-    "printOperandAddr": {
-      "apply_type": "OLD",
-      "old_hash": "9abb796cd4753e9deb86185c4759f625230c278f01b23bbb9ab689fed7cebd48",
-      "new_hash": "",
-      "edit": ""
-    },
-    "printPCLabel": {
-      "apply_type": "OLD",
-      "old_hash": "9fed7969e83fad1c33bee6c48ecf4c24d475d84e8cb42858f6bddc6237c951e1",
-      "new_hash": "ade84eb1a15afb848ef6613ecc22dd9635c287961d68284954e0d80da13af5bb",
-      "edit": ""
-    },
-    "printPImmediate": {
-      "apply_type": "OLD",
-      "old_hash": "d306e15c1f370997604e282277bffad5f9b8130895b9feaadaa9e52aaed900ac",
-      "new_hash": "682ddf037f5302a3a5b0b0b84181f1a90ed7ccf475e68142f11a6496624238fc",
-      "edit": ""
-    },
-    "printPKHASRShiftImm": {
-      "apply_type": "OLD",
-      "old_hash": "71d2c4b54a4593979975483eb0b1235c7e98ff8279b2bb0e10628b5323021062",
-      "new_hash": "cb379ce7f93eeca3e7a0e26f0de9eb38a85a37c7c912e7dd04b9c5fd3aa00001",
-      "edit": ""
-    },
-    "printPKHLSLShiftImm": {
-      "apply_type": "OLD",
-      "old_hash": "bdf1d8a29f6ba423b1e5e2aa8ecb75025135cc9e0b00afc03bf8cbfa91c3bbed",
-      "new_hash": "ea18ff49154d6e98e64b070c14539b1cb9bf2605fc1b54c6b584d0cef4472511",
-      "edit": ""
-    },
-    "printPostIdxImm8Operand": {
-      "apply_type": "OLD",
-      "old_hash": "19577955ef15d0ffd3f4da5d6250103256997f30603326a3a900ca344f66999a",
-      "new_hash": "fd5fb966072ff39e9e69f0bbf1413bda4f67782c62f0b67cec3365ef9be19808",
-      "edit": ""
-    },
-    "printPostIdxImm8s4Operand": {
-      "apply_type": "OLD",
-      "old_hash": "d86795b49368c0085fdce9d3b0d225a737f9371a8c3b63b560d6e47de1886350",
-      "new_hash": "64d50dfbcb48d7ec0c160d63d319f58e6b7fbd70eb9815759a00a3b5a7453f80",
-      "edit": ""
-    },
-    "printRegImmShift": {
-      "apply_type": "OLD",
-      "old_hash": "fe387d2307f0afa1258d838a38fc0e3a1cec278589ea533d4dbe47b30b61022e",
-      "new_hash": "f5f9e7d13397f41b16bc8ae9c6fb4e22340b9f234cb73e5e6ea583066e33a8b3",
-      "edit": ""
-    },
-    "printRegName": {
-      "apply_type": "OLD",
-      "old_hash": "b1fe3d90fb876baaa30fd192924db576307c2dfe15401763eefff652d893d58c",
-      "new_hash": "4f610d8d53df44717b9d6afc902b095e02f0ba8b71b2f0921f9a8c6a9a7335a7",
-      "edit": ""
-    },
-    "printRotImmOperand": {
-      "apply_type": "OLD",
-      "old_hash": "2be39b4db0740667261692917852504071b882d16aa5afe0de54f2ff44fcf134",
-      "new_hash": "1cc162cba6dc29942e357504feb012c509522eed4e15fcb1a36050055c84f03b",
-      "edit": ""
-    },
-    "printShiftImmOperand": {
-      "apply_type": "OLD",
-      "old_hash": "7f1299f202c7103edbe37fa729326c7da3c76b98d000d7b3adc5245bd72ba955",
-      "new_hash": "125bdf3ca38df9d7e9b43ae20e14b132fba0342da474841b6bd8918e79e87fa9",
-      "edit": ""
-    },
-    "printT2AddrModeImm0_1020s4Operand": {
-      "apply_type": "OLD",
-      "old_hash": "cbba19c1ef758dade62a56e6b33dd89923859ae113673d252c42af9075537e76",
-      "new_hash": "861508ab43ce5a3433b663effb73c99804534ab3dad51f852ed2fb79a8264b71",
-      "edit": ""
-    },
-    "printT2AddrModeImm8OffsetOperand": {
-      "apply_type": "OLD",
-      "old_hash": "57b6bebfa994d0e9154b232a5fa13283bb37f070ec0f12f24cc5c22510f35500",
-      "new_hash": "4d29e3fe51efc7bdb28aff362c42277bb8db59363a7261fe4766bcc5b2e13020",
-      "edit": ""
-    },
-    "printT2AddrModeImm8s4OffsetOperand": {
-      "apply_type": "OLD",
-      "old_hash": "f2069b50e98d4faf11b5200b418abac998deda28baf95f0be081a8e8449b4528",
-      "new_hash": "92d3a1dcdd32cffd03ababb2a0b10c0605f74900f2bb3ab304c81967be6a82ed",
-      "edit": ""
-    },
-    "printT2AddrModeSoRegOperand": {
-      "apply_type": "OLD",
-      "old_hash": "43172bb3484e3751a2f7e258bb29db0d7c6d37a6ce375749b1829efb713dd36f",
-      "new_hash": "d5defc297c3ebaaf74c7dc8ba35003437964c40ca3683d7bb685a6ae42b49e06",
-      "edit": ""
-    },
-    "printThumbAddrModeImm5S1Operand": {
-      "apply_type": "OLD",
-      "old_hash": "4a2e4e03452e1916fa2ec0aa0c9db3041c675e681d3e349b5d0436eeb3a3849d",
-      "new_hash": "1269c0298774c8eb4ce5a6c0a27dc5a80c323c3f6e70b7c9faabf575ef1a9249",
-      "edit": ""
-    },
-    "printThumbAddrModeImm5S2Operand": {
-      "apply_type": "OLD",
-      "old_hash": "c1828a2e08a01240583f68c9d59bde99ca4555d65490dc547029cae94299a83a",
-      "new_hash": "517873dc4755e3bc6d7ce50a80bd716e03fef549b344295ad908bc84e6101c41",
-      "edit": ""
-    },
-    "printThumbAddrModeImm5S4Operand": {
-      "apply_type": "OLD",
-      "old_hash": "196c943ec78b1aad2ad8377c1ed245074f8d0c4cb2f875a5ed5a83a9b2b60bb2",
-      "new_hash": "083d4bdec37438584a608c2daeea1fa1589bd3de77f156bce608007aad0e2d16",
-      "edit": ""
-    },
-    "printThumbAddrModeImm5SOperand": {
-      "apply_type": "OLD",
-      "old_hash": "7c394c550f612ae896f6a179f428c815c5c4b1e004974f7221f6e2ed92633657",
-      "new_hash": "2a6214e2cced1ff113efd71b57aa9ff1ccc81aa85ce30e9a47e6940594f40181",
-      "edit": ""
-    },
-    "printThumbAddrModeRROperand": {
-      "apply_type": "OLD",
-      "old_hash": "8be022d793139b99a3190c02d70ab975d611db6c92a5b569aff7081ffd9c353c",
-      "new_hash": "458751b418c22e394ba712f940a93e2733206f3d393f4b46c366e6743a96dd2d",
-      "edit": ""
-    },
-    "printThumbAddrModeSPOperand": {
-      "apply_type": "OLD",
-      "old_hash": "6396900cc18ff022f337ea572ae44f924a42c63f584abe6ff49c4a726749da4b",
-      "new_hash": "82705b397763b51819a79f609e5c58f8ff8d0995ae0c6d1e402a5d4bd3e79fcd",
-      "edit": ""
-    },
-    "printThumbITMask": {
-      "apply_type": "OLD",
-      "old_hash": "fbf9c241234cee08381e20204ed20b51e46781b78ba5a2feb8c680901ae8d86a",
-      "new_hash": "1f94d7de8502624ac21e03f2a2f1d7aab0964ada2b0a8a218297fccbe39f2f86",
-      "edit": ""
-    },
-    "printThumbLdrLabelOperand": {
-      "apply_type": "OLD",
-      "old_hash": "efb84da0302610393d6a7e5391241239b647a5b4c82668326d0e9a47a47a18bb",
-      "new_hash": "74199ee6f3a0679c738ee863b7e09fdbdf54c3a82076db1a08f9f9f64f1e80d1",
-      "edit": ""
-    },
-    "printThumbS4ImmOperand": {
-      "apply_type": "OLD",
-      "old_hash": "a054fa53c071d5adda4eaba8d6f58a6bc3b155347b2bad91436ad9934fab6168",
-      "new_hash": "4a2059ff0c2ad62de628c31faa4fd2bf2ca6939b70e619f670ab53f9da2cc890",
-      "edit": ""
-    },
-    "printThumbSRImm": {
-      "apply_type": "OLD",
-      "old_hash": "a4e8c585111cfca9eb24e81f14e27ae0a5d9332393409760ee53f167e97dc3e3",
-      "new_hash": "cd1ea350e2f17cc235668020500af30b565471033f22be9a5b673ffd2deb5a10",
-      "edit": ""
-    },
-    "printVMOVModImmOperand": {
-      "apply_type": "OLD",
-      "old_hash": "3a12f73636ba9a968615b9ac0da5e66b1abc84170c125bb726f6af923be610ee",
-      "new_hash": "ee434466ac232cdadfba36ed4a6f70559e2fc751b99bad3a9b53924582823269",
-      "edit": ""
-    },
-    "printVPTMask": {
-      "apply_type": "OLD",
-      "old_hash": "3ac3e6830271fad2e5b3099916a92aa352c3f411fedf56fa5a2ee3fc8cad44f5",
-      "new_hash": "dcb3d8c40afce2cb58af848c0a0c7681aadd5f45cf6f4b0f7d0a8a2f829862c5",
-      "edit": ""
-    },
-    "printVPTPredicateOperand": {
-      "apply_type": "OLD",
-      "old_hash": "c7495070d9b75c99d7200b7e4933e8736894ebb44337795a43f22de9761689e7",
-      "new_hash": "1e9e98d0348bd3a0b49bea58b760dcf74a5c7c5db59660109cfe83d89ddd8ff7",
-      "edit": ""
-    },
-    "printVectorIndex": {
-      "apply_type": "OLD",
-      "old_hash": "a22263974ee3716ee63ec009f792b8fefc477637a8a258ddeb4981773dce20a4",
-      "new_hash": "2b260e8edaf33bd8ff81391d55f851862feaae945edb454c64ee20aa97a684c4",
-      "edit": ""
-    },
-    "printVectorListFourSpacedAllLanes": {
-      "apply_type": "OLD",
-      "old_hash": "166e91fa105bcd4dd30e9152264eb6f717ae115aebd2db19d264349b044dc7eb",
-      "new_hash": "d9fdf29c55985c5585fa6ae9e5b5e76f77a6a5460c150e3a10628f03688b5493",
-      "edit": ""
-    },
-    "printVectorListThreeSpacedAllLanes": {
-      "apply_type": "OLD",
-      "old_hash": "c9d6f66f03052ffa94279e30ac20f9cfccdfb02dd37c270c7011c153f66ebbe9",
-      "new_hash": "9eea9d7a79fa7aeeec57d7d1e7be829eaf856b745b6b8cd71b2cc35d25074409",
-      "edit": ""
-    },
-    "printVectorListTwoSpacedAllLanes": {
-      "apply_type": "OLD",
-      "old_hash": "aae283e427412d233ba2d783ad6c999958de2615bbd21c1543c7862398f61d15",
-      "new_hash": "0e4b72ae6eee17618fc9f66af493dd3b3c1e4e6bdf8796ccc2773b12544c74a8",
-      "edit": ""
-    },
-    "translateShiftImm": {
-      "apply_type": "OLD",
-      "old_hash": "e2d84d0521152490aae8ba013d5d06a3bec5fdf1b85dae03a7dab85a37c1486b",
-      "new_hash": "80629627e546f6a8623e75f101abd4c645a020a308c756b4e5393b7d033686aa",
-      "edit": ""
-    }
-  },
-  "ARMInstPrinter.h": {
-    "DECLARE_printAddrMode3Operand": {
-      "apply_type": "OLD",
-      "old_hash": "393fbcbfa8dd4028f0407d9f2488e2e9199007fe5f4cac8bdb53783cd853bcda",
-      "new_hash": "c666d706dc70ef935ea3ce3a0b3a926dfe46aff3aceb842d125ce35f55392ca4",
-      "edit": ""
-    },
-    "DECLARE_printAddrMode5FP16Operand": {
-      "apply_type": "OLD",
-      "old_hash": "b5f19a03bfd519a25e63c3a0915288088d8c013cf3072889f27bd7f78a150f8e",
-      "new_hash": "b4f43c435aa48a3a96f11c991e2cfffbb1e86797d35ae5c3df677c71d9629bfb",
-      "edit": ""
-    },
-    "DECLARE_printAddrMode5Operand": {
-      "apply_type": "OLD",
-      "old_hash": "8e1d447e8a0a0c1d079060007fa977b19f0315ad23f051fc6268cb47a02b5a6a",
-      "new_hash": "167c618729c81f7b5d0c113f999cb0b5b18c96a8ad36bb5524269307f9b478ba",
-      "edit": ""
-    },
-    "DECLARE_printAddrModeImm12Operand": {
-      "apply_type": "OLD",
-      "old_hash": "8db80cc06b17150e50e63f8763fdfa8d47d60675d023e3a9574db7f366e31ac7",
-      "new_hash": "d5396e68a91b970a4be8ccfcb3ea144007b57118aa6a381f6433fa54074dff44",
-      "edit": ""
-    },
-    "DECLARE_printAdrLabelOperand": {
-      "apply_type": "OLD",
-      "old_hash": "d8823baab85bbfe957433207e6618fdf5ad9e7cfa03856b376da2f55d64fff74",
-      "new_hash": "6169de4fca56dcf4c28a0dcff06bfc547066b7e4507e897d2c4fa3be3cb71574",
-      "edit": ""
-    },
-    "DECLARE_printComplexRotationOp": {
-      "apply_type": "OLD",
-      "old_hash": "7edf22601536c2da376f23cf87130dd1eb1da0516564ae9500ca14eec2804b45",
-      "new_hash": "a6cf8af8f48a60260428625c56741fb44b619634b5d5bfc41a680ca9a98e029d",
-      "edit": ""
-    },
-    "DECLARE_printMVEVectorList": {
-      "apply_type": "OLD",
-      "old_hash": "184ca6b74e9475ea9c496562d8ae4514fe6fd596adff6c0043d6669d93bd8d0d",
-      "new_hash": "34fecb1960b6b89daeee285fb724612592432c9107283895ec9de129db8ede58",
-      "edit": ""
-    },
-    "DECLARE_printMveAddrModeRQOperand": {
-      "apply_type": "OLD",
-      "old_hash": "7e6b18b04bbde182ddb08f39c308cdf25f608de9d1c1869650141f71d53fc40f",
-      "new_hash": "ba7d3a23c12149f6997aecc64062daf91e137573e1ebb275a98e16c96c2cf6c6",
-      "edit": ""
-    },
-    "DECLARE_printT2AddrModeImm8Operand": {
-      "apply_type": "OLD",
-      "old_hash": "55b5d1e3f38b9373f08b1bb272c0f3591c0b5081053d3b967a84b249a2a96e83",
-      "new_hash": "678a07ac256780dc77c035939a5b1f0205ab5648d298f7612a612fe662de9f4c",
-      "edit": ""
-    },
-    "DECLARE_printT2AddrModeImm8s4Operand": {
-      "apply_type": "OLD",
-      "old_hash": "354ba33df5106d0e03225fd041c7c20304659f303bdfffa5974101d10ea91f6f",
-      "new_hash": "6eb210b770604d8c08e65896aee289e91f82b846d4efd4e0fefc697b23cd18ec",
-      "edit": ""
-    },
-    "DEFINE_printAdrLabelOperand": {
-      "apply_type": "OLD",
-      "old_hash": "",
-      "new_hash": "bbb96db98eb56e5934b6c7197e48afcbc1cd275b3f92c36c57db28b5045cae40",
-      "edit": ""
-    },
-    "DEFINE_printAdrLabelOperandAddr": {
-      "apply_type": "OLD",
-      "old_hash": "c42f5abbe91823ee78ab4413e71564f67e83fa2bb542bf7c088124d67d4cce77",
-      "new_hash": "",
-      "edit": ""
-    },
-    "\"../../utils.h\"": {
-      "apply_type": "OLD",
-      "old_hash": "bba3ceddc5b6ca88f7f5a17acc4d2545a08e4011ca8224462a64a30eff35e9eb",
-      "new_hash": "cb41b18c2131c68da16a903ae7b7d7172f7883ab3494e3f89480c09e6c218da4",
-      "edit": ""
-    },
-    "\"ARMMapping.h\"": {
-      "apply_type": "OLD",
-      "old_hash": "",
-      "new_hash": "e010fe7fc5dbf57e7bdcec6beec5538edecf8fa40f2426bf12d2b37fff5cde57",
-      "edit": ""
-    }
-  },
-  "ARMAddressingModes.h": {
-    "ARM_AM_createVMOVModImm": {
-      "apply_type": "OLD",
-      "old_hash": "9fdfe761698ec14ee8ec8d867175327cde1b29ac01653bef157568f00a380094",
-      "new_hash": "2d67792843d1ccbace90c0861da72fd30785dcc30e24824ebebf5ed5e1874fc6",
-      "edit": ""
-    },
-    "ARM_AM_decodeVMOVModImm": {
-      "apply_type": "OLD",
-      "old_hash": "993ce2cf247ceedceee63d2cbdd2573632860111577fa226a56cbeb049aa0eb9",
-      "new_hash": "0f40d66f524e9c77f58eb74427a3344acf7b50c946f2b6a8bcb3287bde206463",
-      "edit": ""
-    },
-    "ARM_AM_encodeNEONi16splat": {
-      "apply_type": "OLD",
-      "old_hash": "05a8c9026d52566a444ca430a3b625485ee00e7726e8f60f5987b2eaa10810c6",
-      "new_hash": "e3ef8dc6988f2c7f32df2de20d0939134765e5f4cfa25844b3cae2add946b17f",
-      "edit": ""
-    },
-    "ARM_AM_encodeNEONi32splat": {
-      "apply_type": "OLD",
-      "old_hash": "8a4fb58682368d6b5a303a882e30a80a9f3530bb5bfb0d667bdabed48ec2f987",
-      "new_hash": "9c8b757326264d8b6a107c9c877550ec459622aabc8612825e71243ca3cb435b",
-      "edit": ""
-    },
-    "ARM_AM_getAM2IdxMode": {
-      "apply_type": "OLD",
-      "old_hash": "59c09986a56e7e775072e34fb51efaecb0272920b85d2c9422f75342ae00610c",
-      "new_hash": "e5e5ff685e501cac90b08d0dca399739546ce0423b935da83ef1ef1a41ae7498",
-      "edit": ""
-    },
-    "ARM_AM_getAM2Offset": {
-      "apply_type": "OLD",
-      "old_hash": "eb69c387b7a7c48c974bc63a110256aff086046ddb6f1a8b315d55813f5f40bf",
-      "new_hash": "374b3176223a2d1b5f1bbb0b97b671bd91b2d97f56cf42e953c63e692ecf5509",
-      "edit": ""
-    },
-    "ARM_AM_getAM2Op": {
-      "apply_type": "OLD",
-      "old_hash": "8eacd33cf973cd4c388a67967d0ccb1571c1f5acd7a96b01c21a7c9d22b1b3e3",
-      "new_hash": "9170286ed54ad2096bece239299246e09e2d1c4c0207d9bf67045c3c2e6760b0",
-      "edit": ""
-    },
-    "ARM_AM_getAM2Opc": {
-      "apply_type": "OLD",
-      "old_hash": "d0bc64e4b232db82001dea523aab12f38b2324c0f0bb9b994cc937918831fdfb",
-      "new_hash": "950183b6fe310411a92b84e91218b9cc0b142220ae54045d6f30b93efe1269a7",
-      "edit": ""
-    },
-    "ARM_AM_getAM2ShiftOpc": {
-      "apply_type": "OLD",
-      "old_hash": "c8948f4fcc5c119e386121c1001a9054fed8defbee9061cd72f2ba0365d5979d",
-      "new_hash": "65b0f515e542d325a16a79bfbcca1879f34d116bd36ee72210b399e875a9e804",
-      "edit": ""
-    },
-    "ARM_AM_getAM3IdxMode": {
-      "apply_type": "OLD",
-      "old_hash": "dd2adc35fe94347c445c80fa60e4840d3ceca15439d143ad6a0f5cc250f70f26",
-      "new_hash": "d87713cc6706e0acadaa0088c23726caefb0a2f6aeb54fe8a07696cb2058af76",
-      "edit": ""
-    },
-    "ARM_AM_getAM3Offset": {
-      "apply_type": "OLD",
-      "old_hash": "968fa24b564182bb2c961214bc8700c12f498b6555af347b69e7d8f92bec19cf",
-      "new_hash": "8349811ce80fb52f135d10ec018d4374d67a4ea77256dc0a9de93f8b5d2dc6f2",
-      "edit": ""
-    },
-    "ARM_AM_getAM3Op": {
-      "apply_type": "OLD",
-      "old_hash": "313f8eef19d721a770f3d18494d35101a59c102aa226ee8ecb0c7e2a2ad8b59e",
-      "new_hash": "30bd50d0368d2d9a87dfc7649d5e55855efdd0e1c6f153e4d1cb4ffb88cfee4b",
-      "edit": ""
-    },
-    "ARM_AM_getAM3Opc": {
-      "apply_type": "OLD",
-      "old_hash": "5ca20ce5d2ed07dcdd912965c02c5323ddd36a6f7712e7fcbe15711c3d4ee8f3",
-      "new_hash": "4d5e5d1d60bf680c9d87c30fbaf4d5ee8d9b781071ea35edf9969357ccdb8969",
-      "edit": ""
-    },
-    "ARM_AM_getAM4ModeImm": {
-      "apply_type": "OLD",
-      "old_hash": "39dd93dc2516d2babe9cf9b1b22c6d6358e0887ac691d3a8210c7def682c1d99",
-      "new_hash": "057f0b69b8885126db65609d61d7861e745f70678fc0b4cdd547517cf3781bf9",
-      "edit": ""
-    },
-    "ARM_AM_getAM4SubMode": {
-      "apply_type": "OLD",
-      "old_hash": "8e23306f176900bf3b9ce26172465532d65485eeb57757b32323fd76a72b157c",
-      "new_hash": "8ae0289c976949aab7de97549fb8655e285e3dd8f39b5b0077fbeacfc1ddd6cb",
-      "edit": ""
-    },
-    "ARM_AM_getAM5FP16Offset": {
-      "apply_type": "OLD",
-      "old_hash": "54e6ff39be8d31e9198ce0a58a34f6be2d6f79f30d4b9708eac808bc9522ffc7",
-      "new_hash": "e81b4c7f1f316ec048c33a8b8bb11acde25e1f6517095d39a8346fa7f72cd73c",
-      "edit": ""
-    },
-    "ARM_AM_getAM5FP16Op": {
-      "apply_type": "OLD",
-      "old_hash": "cfa02ca36fbe0391ea693aaf88673e0808d025312e887dbedfefec315fc09090",
-      "new_hash": "1200c63f8b75d7dd7088822ed94f2c30449655fce6e5043433ed9694b7c5752d",
-      "edit": ""
-    },
-    "ARM_AM_getAM5FP16Opc": {
-      "apply_type": "OLD",
-      "old_hash": "31ab00e2e5ca6d7e6f6558cc797badf547e2cb1d4e420c156ab33a2c9ad36dc5",
-      "new_hash": "1cfbde6a8ae285af27337b536b83521fc8ecd6cec0ccbd3e93e4e5811fbbb804",
-      "edit": ""
-    },
-    "ARM_AM_getAM5Offset": {
-      "apply_type": "OLD",
-      "old_hash": "39753b85a04c603500cd241e51b6051ab1f1161c5751f9cc9943feba8a933604",
-      "new_hash": "bc79a25f4f45a320661960582232f93d05aa139685fe5407dad5091f8b7dc018",
-      "edit": ""
-    },
-    "ARM_AM_getAM5Op": {
-      "apply_type": "OLD",
-      "old_hash": "8cb5b71316ea64e4d1397cc83b338ffdf03db131e8800f4a28c1453b04da6354",
-      "new_hash": "147ac382e3d1542f09f972885ee58c519b1df96ce0c8bdc6448f070a08963d68",
-      "edit": ""
-    },
-    "ARM_AM_getAM5Opc": {
-      "apply_type": "OLD",
-      "old_hash": "db8343f2a60ac06405d6dd9407f19060f0e208e578dbcccbbb812c327f9ed152",
-      "new_hash": "096cfd20c543e9c5d47a76bad44ab0fea7c1770f56fe2722e49aec1f820e12ad",
-      "edit": ""
-    },
-    "ARM_AM_getAMSubModeStr": {
-      "apply_type": "OLD",
-      "old_hash": "ce74d91930ae0836a39773acc93f9d9af3d176fb386c03045fdce659ddafc93a",
-      "new_hash": "2e559b4426dcacb7193a54663ba3e5fe0a9bb460e69538d19862c8e80c14a8c5",
-      "edit": ""
-    },
-    "ARM_AM_getAddrOpcStr": {
-      "apply_type": "OLD",
-      "old_hash": "874cd615fbae834cb493ec7e6c12497df8f71144d1d5f73863e24b2688a86a06",
-      "new_hash": "43f7343aed1cdd5e7d91231393e2298bafc9985ab1171603da4dab017231e3e4",
-      "edit": ""
-    },
-    "ARM_AM_getFPImmFloat": {
-      "apply_type": "OLD",
-      "old_hash": "b701b7192bbf232f992fb75f6b025609b6243881c56decaf3a3ec789e26b75c1",
-      "new_hash": "2c1787344950c82894a99240d9214aabab60924844b1c2eef4938c7ec0019e16",
-      "edit": ""
-    },
-    "ARM_AM_getSOImmTwoPartFirst": {
-      "apply_type": "OLD",
-      "old_hash": "dc859c73453011a9165e6511738df1809f61d9939cb0e98097cab241d307ad68",
-      "new_hash": "b85e8d0b0218afddef20b20796ac641eaec59cae58aefb4262ad09d7922de7c2",
-      "edit": ""
-    },
-    "ARM_AM_getSOImmTwoPartSecond": {
-      "apply_type": "OLD",
-      "old_hash": "2a4827167b657ea2b42aad88488e0d8c6e1c8eb76c92b26556e511244220ade0",
-      "new_hash": "543a85d41852c18f79d9987bdfbe869f9ae885426fc97ef61b9110ac878e43ce",
-      "edit": ""
-    },
-    "ARM_AM_getSOImmVal": {
-      "apply_type": "OLD",
-      "old_hash": "43428220c58b44e2c989b3cc8c0f13cacda3bf53a49276ee6953db163a2c453b",
-      "new_hash": "dbe694b9859c85f70fad45da59df204321688105c7a0327084a9f9a7750f37e4",
-      "edit": ""
-    },
-    "ARM_AM_getSOImmValImm": {
-      "apply_type": "OLD",
-      "old_hash": "bb0e902aa755a8d041eee1d7798bf0087a57f6beeb17e9d93a0370d62e0c1f14",
-      "new_hash": "86aaaf11a33a1b7f71aa58824675fac2c52fc017031ade13f595964cfbdd0231",
-      "edit": ""
-    },
-    "ARM_AM_getSOImmValRot": {
-      "apply_type": "OLD",
-      "old_hash": "e922391e2bcc7bacc4df2b7fb70bbb1ebfe21f0604ab8c2898b24a231a3eadce",
-      "new_hash": "c9b1eda0b78fee9cbc5e1c7ccbf85be0eb9f67517fc6febcf3820d122add2fc9",
-      "edit": ""
-    },
-    "ARM_AM_getSOImmValRotate": {
-      "apply_type": "OLD",
-      "old_hash": "093636bc78707389262f3f4fc443333ad996c7618ce4e8bd79a654d67ff8a940",
-      "new_hash": "01ba2494a7d43a8623095d2cffa039fdbd5edab4da984fe68a2dc8124f031d71",
-      "edit": ""
-    },
-    "ARM_AM_getSORegOffset": {
-      "apply_type": "OLD",
-      "old_hash": "a1f9f169b6579833d965db979941ee0b72d322f651df219222ca45d0ca24f6e7",
-      "new_hash": "bbae7e4abeadd5577b7df0dad8b72ada71db2ad23334e252b08b58cb0a8a384c",
-      "edit": ""
-    },
-    "ARM_AM_getSORegOpc": {
-      "apply_type": "OLD",
-      "old_hash": "86f5d2f46956379d3bcd34a438f4e3c0b5ae9220e21d029ddc073577cbf58427",
-      "new_hash": "4a31bcbc12e3920187297ef75306c1504548c87fb703223bb2de59aece89a109",
-      "edit": ""
-    },
-    "ARM_AM_getSORegShOp": {
-      "apply_type": "OLD",
-      "old_hash": "1a394d97f642a946279b28f8e7f12e5dd567c5a6d09ec02da795bc42960a5a87",
-      "new_hash": "221f5b7b8f4633174f8f9b856fa71dbe9c1929320c30c505d02926c5a8a1fe0e",
-      "edit": ""
-    },
-    "ARM_AM_getShiftOpcEncoding": {
-      "apply_type": "OLD",
-      "old_hash": "111fc0a3953dcf8e371a38bf178569b5e4b68e34e3b902a6b16cfbbc29e240a3",
-      "new_hash": "aa29dc3a4d73dbba90ce12de56d1fbc8eb78b9b124cd1b2e6f4fbddcb156e404",
-      "edit": ""
-    },
-    "ARM_AM_getShiftOpcStr": {
-      "apply_type": "OLD",
-      "old_hash": "feba37bca7fc4dedcc0727e4c0f0f46e01c0dc005589d3a60e8fbbf918d31485",
-      "new_hash": "164aee3544ec40e08408e599f8c287e7755e2e26de333d78f07b803fb4a8282a",
-      "edit": ""
-    },
-    "ARM_AM_getT2SOImmTwoPartFirst": {
-      "apply_type": "OLD",
-      "old_hash": "aaae88603b39401c81c249b7c0335cfac95d3e34211e4b73cf0f18b75a792ad8",
-      "new_hash": "9471fecfeed2cc1bfea9194e36fe8107f413f9d91927b1fb8c463725e0bfa1e6",
-      "edit": ""
-    },
-    "ARM_AM_getT2SOImmTwoPartSecond": {
-      "apply_type": "OLD",
-      "old_hash": "28f2af7ddacdf2b78e988b62fe5008a9f40ce64a06303022f126c5a146dc178d",
-      "new_hash": "da03c0d957937e69d618bea142f5615e911650b8df0d82e9ec58bd6572efffcc",
-      "edit": ""
-    },
-    "ARM_AM_getT2SOImmVal": {
-      "apply_type": "OLD",
-      "old_hash": "0169fc2c1a915a598f8d2844353b80ea10374675156fd83960a01f37c74a3940",
-      "new_hash": "f078fa9fadd3ea56aa317feef8c80fb99dc8bb0b3687b2627911015f5182f5cb",
-      "edit": ""
-    },
-    "ARM_AM_getT2SOImmValRotate": {
-      "apply_type": "OLD",
-      "old_hash": "7d5e9489c3ef1a80f452f4b6bd8b290c853a7e10a34fab6d891988d7cf0c8df8",
-      "new_hash": "19522b7e9d857a2dbb99f1673a595bf0da9007db078b3f6c7e2085a31df6fd1a",
-      "edit": ""
-    },
-    "ARM_AM_getT2SOImmValRotateVal": {
-      "apply_type": "OLD",
-      "old_hash": "5e2aa248184c27af379dbfc1bafe403e3f0367de297d49beb893afc875362866",
-      "new_hash": "3c969521da0444705ed23cb50c36a073b754dd4f8eec04c8087b476ec5cf1b07",
-      "edit": ""
-    },
-    "ARM_AM_getT2SOImmValSplatVal": {
-      "apply_type": "OLD",
-      "old_hash": "8646ff69d711508d3a895b5e403f41adf8ac1d884bd8db53d43276d41d3709d6",
-      "new_hash": "d65aeb9204ec89f72cfc31ea7928d9a88e3db93bfe6585136d2f9d8ddfe4b06e",
-      "edit": ""
-    },
-    "ARM_AM_getThumbImm16ValShift": {
-      "apply_type": "OLD",
-      "old_hash": "cb2d3b9c433f847b3c5a45439aad7c917af46fbaa34d738663cab1e96bbb88e4",
-      "new_hash": "8d90a8b8b4f91d5ab7a1a9f866a40446f89890f67baccc58a885933e9d9217eb",
-      "edit": ""
-    },
-    "ARM_AM_getThumbImmNonShiftedVal": {
-      "apply_type": "OLD",
-      "old_hash": "3822416499583204306abfa37f6af89e8e00e0f492c29aca032335238d134fd7",
-      "new_hash": "41e3c78bc92aad095de33b88c1a9400997804d2ad69344184f701b264fdbaa00",
-      "edit": ""
-    },
-    "ARM_AM_getThumbImmValShift": {
-      "apply_type": "OLD",
-      "old_hash": "64e51398dde6bdb03c645425557944517740dad87f7f3acd3a132529a6d88f5c",
-      "new_hash": "62072076bcef753b21752e6e1f27e3b93909eb197e208d09866aa6e4dd02ed99",
-      "edit": ""
-    },
-    "ARM_AM_getVMOVModImmOpCmode": {
-      "apply_type": "OLD",
-      "old_hash": "3dc201029cbfc7eaf84bc2778c2d677a0906da9b0378f50d0a4499e19e2eccdc",
-      "new_hash": "6713eccf00c4127a96b8147da41c2eb7d8d91896dedd7ff01f97b6b8c91ab492",
-      "edit": ""
-    },
-    "ARM_AM_getVMOVModImmVal": {
-      "apply_type": "OLD",
-      "old_hash": "b7e474123c49f78fc16b20a129d160ebd473d5a5e00a0ca8dd91834e94d602f8",
-      "new_hash": "cb1525c3552784d93be28f8330c116273df1685eb7ed974edb744d32621a1dee",
-      "edit": ""
-    },
-    "ARM_AM_isNEONBytesplat": {
-      "apply_type": "OLD",
-      "old_hash": "8332f2fd86baed5a2427550d62ee833cd3c6054a99a4cef38e7fba2e2d889c6b",
-      "new_hash": "53190f9c11fc5a7e0c1e38474b72156d69c5b3893d538a4c76d090e6f6034a0a",
-      "edit": ""
-    },
-    "ARM_AM_isNEONi16splat": {
-      "apply_type": "OLD",
-      "old_hash": "a0938026315cc63cb531a85471e6d45f58eb50a4058a622c25472f453b2b8619",
-      "new_hash": "2a3a64ccb9a6155cfe4e5a9ad67ee16f1d5dd45f1cd3b1564600c1b28c0d6c01",
-      "edit": ""
-    },
-    "ARM_AM_isNEONi32splat": {
-      "apply_type": "OLD",
-      "old_hash": "e82588ad097f60ed35e179264ba1e3e7644ea64a7162622f944692bd9adab37e",
-      "new_hash": "9bef85dfdb0e7f6309eaac91a55697d410a950abe7e8e24098b64c4faca89f33",
-      "edit": ""
-    },
-    "ARM_AM_isSOImmTwoPartVal": {
-      "apply_type": "OLD",
-      "old_hash": "8239a5ed54d74daa8eb26ee113f07c2de10b04e50c13a2b982a8b11fd675ea66",
-      "new_hash": "ce0c930874ec6803d2b171e516218178cccde91a19577887ae5c021a123440db",
-      "edit": ""
-    },
-    "ARM_AM_isSOImmTwoPartValNeg": {
-      "apply_type": "OLD",
-      "old_hash": "caa5671e598be177e85348dc91e7750ba7b04655689c17a9351a298b6a23a34e",
-      "new_hash": "c00be464bbfac51e71628c71bdd8d2e5d775f14911b5556b7f926e7b3f3a59d1",
-      "edit": ""
-    },
-    "ARM_AM_isT2SOImmTwoPartVal": {
-      "apply_type": "OLD",
-      "old_hash": "6cb24668a4e3d4946703eb15695547429008f5a85e9dcc7b909684cdc29e6913",
-      "new_hash": "9e98720bcb01546e795c8ceb52d3b1167eaa5c9e43a9671dc52797529e71d0ef",
-      "edit": ""
-    },
-    "ARM_AM_isThumbImm16ShiftedVal": {
-      "apply_type": "OLD",
-      "old_hash": "465b428de9df7274b97fe809f14d9daaf182980700aa88178a021716848215cb",
-      "new_hash": "d56f0a8e4dd0f7105405ab3543784572b669abbd542b40f9b1fae0dc05fccd9b",
-      "edit": ""
-    },
-    "ARM_AM_isThumbImmShiftedVal": {
-      "apply_type": "OLD",
-      "old_hash": "cf9a79c66fbc0cdc23188e8fae364995e78bbbb80e7f232c02c9e706b806e059",
-      "new_hash": "a79c7bfcab2471647f1a471f6cfaa8456050c67144b53477ea5b90a3e1d9c590",
-      "edit": ""
-    },
-    "ARM_AM_rotl32": {
-      "apply_type": "OLD",
-      "old_hash": "49814ded27d6461862f6fe0c61f1ea90e34e8e384295fafeba8d3798698c8836",
-      "new_hash": "1c4e01d119292eea41f99f0d876e8cfce8fa817837b2b8a0ca93da1aae775b3c",
-      "edit": ""
-    },
-    "ARM_AM_rotr32": {
-      "apply_type": "OLD",
-      "old_hash": "0d1d02c7bc72b178174913e3a39a36d680a83234954a6018b54102b9a8ca7f0a",
-      "new_hash": "7372b1713eac46155f82a51f57ca7fc8dee71efda6b88f36693d57c30552570d",
-      "edit": ""
-    },
-    "CONCAT": {
-      "apply_type": "OLD",
-      "old_hash": "9d54def8e6c2e86efddf81ae412925c77492de8e619f178600b2b92cb8294a44",
-      "new_hash": "e4820f6346c51882017758424dbd39c22bb34a7c43a2aa02295c421e610963dc",
-      "edit": ""
-    }
-  },
-  "ARMBaseInfo.c": {
-    "ARMSysReg_lookupMClassSysRegAPSRNonDeprecated": {
-      "apply_type": "OLD",
-      "old_hash": "",
-      "new_hash": "46a413e3efb1147c7f53e9bfca46a008b1e674743af943a919aa9da3a621a24e",
-      "edit": ""
-    },
-    "ARMSysReg_lookupMClassSysRegBy12bitSYSmValue": {
-      "apply_type": "OLD",
-      "old_hash": "",
-      "new_hash": "faa313843f323f690e2b7d068f4c73ddfd02a855c6929b974cfe5619ac5bf77f",
-      "edit": ""
-    },
-    "ARMSysReg_lookupMClassSysRegBy8bitSYSmValue": {
-      "apply_type": "OLD",
-      "old_hash": "",
-      "new_hash": "a742d04516ad454bbae24b897a8446be964c2fe94d69c8bfd70e1049042c990b",
-      "edit": ""
-    },
-    "CONCAT": {
-      "apply_type": "OLD",
-      "old_hash": "9d54def8e6c2e86efddf81ae412925c77492de8e619f178600b2b92cb8294a44",
-      "new_hash": "e4820f6346c51882017758424dbd39c22bb34a7c43a2aa02295c421e610963dc",
-      "edit": ""
-    },
-    "expandPredBlockMask": {
-      "apply_type": "OLD",
-      "old_hash": "",
-      "new_hash": "d438f752cf47f9ce9b5c86ecb0f5c533967e669d722b10bca5f7b8bb9438c3a1",
-      "edit": ""
-    },
-    "get_pred_mask": {
-      "apply_type": "OLD",
-      "old_hash": "2df9f0a4b700c0018e11b43f128edf5e56ca51994895f573ba372657f1b42ac3",
-      "new_hash": "",
-      "edit": ""
-    },
-    "lookupMClassSysRegAPSRNonDeprecated": {
-      "apply_type": "OLD",
-      "old_hash": "b424a3c3bb4fd75e9e0cdb11fd783c942519fa25fe31e930fde1e033bc7c695a",
-      "new_hash": "",
-      "edit": ""
-    },
-    "lookupMClassSysRegBy12bitSYSmValue": {
-      "apply_type": "OLD",
-      "old_hash": "eea213a2863c54ffa542d667b376919e4a1b8094f3f41cf950e9a1cc2fd73b1c",
-      "new_hash": "",
-      "edit": ""
-    },
-    "lookupMClassSysRegBy8bitSYSmValue": {
-      "apply_type": "OLD",
-      "old_hash": "544a8a7ac86577daa605ad976141d8166491017176b0e3a73d2e79581dff8501",
-      "new_hash": "",
-      "edit": ""
-    },
-    "\"ARMBaseInfo.h\"": {
-      "apply_type": "OLD",
-      "old_hash": "c2628208478c4f7d6c48f4657e7cf14e1f896657f8370938b8c438ca5517c45f",
-      "new_hash": "2be2e93095820dd9bd4b4974e4568fb2c45c8f7401a92553fc0e222812889efa",
-      "edit": ""
-    },
-    "\"ARMGenSystemRegister.inc\"": {
-      "apply_type": "OLD",
-      "old_hash": "76a3d513fb74a9c14aaf369a2e41e6692dcb2ea64984e6430e7be44b72c8cbc3",
-      "new_hash": "",
-      "edit": ""
-    },
-    "\"ARMMapping.h\"": {
-      "apply_type": "OLD",
-      "old_hash": "e010fe7fc5dbf57e7bdcec6beec5538edecf8fa40f2426bf12d2b37fff5cde57",
-      "new_hash": "",
-      "edit": ""
-    }
-  },
-  "PPCDisassembler.c": {
-    "DEFINE_decodeSImmOperand": {
-      "apply_type": "OLD",
-      "old_hash": "f82506a3702d696d8550d29eb9381c63cb493c6668705b8717563b353c61199d",
-      "new_hash": "6ef5acbc7cb8f9ca5194b0ac8fd7aecceeb820180598e19964081f00136648bf",
-      "edit": ""
-    },
-    "DecodeQFRCRegisterClass": {
-      "apply_type": "OLD",
-      "old_hash": "8a27cd3e61e6668c274cab496a5fa7041b19fa728e9243d985a73da4de93f675",
-      "new_hash": "",
-      "edit": ""
-    },
-    "PPC_LLVM_getInstruction": {
-      "apply_type": "OLD",
-      "old_hash": "9826020ad71dc7e08c2986de1b30ad57ab2f62bf03c0faae937261ca4593c62e",
-      "new_hash": "",
-      "edit": ""
-    },
-    "createPPCDisassembler": {
-      "apply_type": "OLD",
-      "old_hash": "",
-      "new_hash": "2ae1fe9fd435afc31a3abf84fa2de4a89d312ba76553e7fc389323947fcd2de9",
-      "edit": ""
-    },
-    "createPPCLEDisassembler": {
-      "apply_type": "OLD",
-      "old_hash": "",
-      "new_hash": "d33eda9c5bea015d3f34f8225fa7180f7328c1384a0ac0d3cfdd85c606c4e800",
-      "edit": ""
-    },
-    "decodeCRBitMOperand": {
-      "apply_type": "OLD",
-      "old_hash": "538401e469720e3ac9ce55f34e2f6e762ad66c17c45e5ae5b4905326dc2896ed",
-      "new_hash": "69c4ad313c16df1f9c2a259238c5334ac3e2335df388da56141d369dc3fc38ca",
-      "edit": ""
-    },
-    "decodeCondBrTarget": {
-      "apply_type": "OLD",
-      "old_hash": "261b9e2aaab3b50a7970b2340fff8020ca8d0492c7e6bc85660d4b041e4531cc",
-      "new_hash": "7ae0f4d64f0a0cc924d0396a6a61ff931cc32d285199814282b3521110fe80f5",
-      "edit": ""
-    },
-    "decodeDirectBrTarget": {
-      "apply_type": "OLD",
-      "old_hash": "fb76cf3c7d4631f8af953f0e02cde0a94efd340200bdbb6575db746153c87c91",
-      "new_hash": "fa78611f6a232add4f09e2078d81d0090c36c15d27dbbfe846f1634797775a39",
-      "edit": ""
-    },
-    "decodeMemRI34Operands": {
-      "apply_type": "OLD",
-      "old_hash": "ea10510a6ac9056c48a257d542255e712decd8155e5546186b4bc1c418a1e12a",
-      "new_hash": "4fb4317b5ae8125c06f49c72603d1a2141c1e5bbdf3c7fb4412aebd466597cb0",
-      "edit": ""
-    },
-    "decodeMemRI34PCRelOperands": {
-      "apply_type": "OLD",
-      "old_hash": "aa0ce09c12e3731de4de6033be0ebbd23cad956407842692f2f1c18f152231e7",
-      "new_hash": "cc26575564cfef71ff8295defedf98099581d548a70138f15cb77f9c5bfb1574",
-      "edit": ""
-    },
-    "decodeMemRIHashOperands": {
-      "apply_type": "OLD",
-      "old_hash": "09bdbc09038bde4f727b135a502e728c165092ea66f6d0170e4977f5dcc51efa",
-      "new_hash": "cb2ba1ce242b1006de920c940f2affa273c8b5a403b69f7b82756a34a9ca09f6",
-      "edit": ""
-    },
-    "decodeMemRIOperands": {
-      "apply_type": "OLD",
-      "old_hash": "d0a7c2eaa61823699af1b145e61d7007b2f5b4424f9c902924194915615aec0c",
-      "new_hash": "9e1c4d52d7e40f1c7d336ee81928fe049a50b214c12b8dca3237b54b86afd11f",
-      "edit": ""
-    },
-    "decodeMemRIX16Operands": {
-      "apply_type": "OLD",
-      "old_hash": "ce7dcbc54111f3203f2ab3adc9091bacc50ad44902edca54e395339a0403273d",
-      "new_hash": "096448a38fc7c370b7916a9436ce990b2f03048dc80b2e4ff10d49492723f512",
-      "edit": ""
-    },
-    "decodeMemRIXOperands": {
-      "apply_type": "OLD",
-      "old_hash": "cd1530f7deb02c1c1620de1957cef20469305d17e09459de1dbb8bdf8cacca7b",
-      "new_hash": "f3ea45a82f9b581cdbd0d84f143b18d0c3d8aca77c1f4ec310fb574ba91153c2",
-      "edit": ""
-    },
-    "decodeRegisterClass": {
-      "apply_type": "OLD",
-      "old_hash": "4ca0ebc438967e02e92894acc96766f5d34d7f58d9c3ed689c447ef68ae0ef9c",
-      "new_hash": "d10b11110bf060fbe9e8e97d2d60b19122b86c19a26ef44c7f8bf8880897381d",
-      "edit": ""
-    },
-    "getInstruction": {
-      "apply_type": "OLD",
-      "old_hash": "d3b1f48506ef1ef84f8296fc2699b7635c1837bfbdbd7f884ef6556971d5caf1",
-      "new_hash": "ce604b0b86a537157f2d91bbb231907d88d96a3ad8c068a507beb34bd142f95d",
-      "edit": ""
-    }
-  },
-  "PPCInstPrinter.c": {
-    "\"PPCPredicates.h\"": {
-      "apply_type": "OLD",
-      "old_hash": "7bf251193ea8db3ddfe401f154f582588278003d2c6c0b754098ff6b5ed9e535",
-      "new_hash": "1306971fdc94a76e7c1cc0ab8880527ecd9d1c0d4c1a8aba36f76c18bafccdfb",
-      "edit": ""
-    },
-    "PPC_LLVM_getRegisterName": {
-      "apply_type": "OLD",
-      "old_hash": "eb1bebab7834d085add1e768da37a2e44e42096fd4713132b805fc818b27bdbc",
-      "new_hash": "",
-      "edit": ""
-    },
-    "PPC_LLVM_printInst": {
-      "apply_type": "OLD",
-      "old_hash": "f4650b12cb105a20c4d5cfdef55ac84d8be18940ddd5679cabd173e2e2905823",
-      "new_hash": "",
-      "edit": ""
-    },
-    "getVerboseConditionRegName": {
-      "apply_type": "OLD",
-      "old_hash": "0e1b94bc68a8a0b7b4cfed66babb349f22c2b46fa2499c1a6a78f6be49b7162c",
-      "new_hash": "17c123d967550047473e948ee42e4c1a26d9316f1fd2c75524c070ca8d13b776",
-      "edit": ""
-    },
-    "printAbsBranchOperand": {
-      "apply_type": "OLD",
-      "old_hash": "1964f29e02888bd03d35fc9e1c345881aa3c54d3c5a1334d6e1333926fc272f0",
-      "new_hash": "7a260c704755ea9457fcaeb37eec6ce14d98b608053d82f2383ef6d2c0b81c18",
-      "edit": ""
-    },
-    "printBranchOperand": {
-      "apply_type": "OLD",
-      "old_hash": "8c5fc2e488f421daf6a7d74404dd18cff5b3f1ddf83ba1b5d5e0832f4cf91872",
-      "new_hash": "1fc3dc7f0bafd7f12bff3bf81fd43ac25eeb5edcb606f46274a245eb1b109c87",
-      "edit": ""
-    },
-    "printImmZeroOperand": {
-      "apply_type": "OLD",
-      "old_hash": "cbacd7e6f47c813e31eeb35797001aff4fc5e5491c51bd8359dfd9bc082df986",
-      "new_hash": "46036217bb3043cf754e707dd98e37e7d2c62fe08bd8a75456e6232e68a9a0f0",
-      "edit": ""
-    },
-    "printInst": {
-      "apply_type": "OLD",
-      "old_hash": "cd2acc260cefdf11d7c315ca5c43e08081ad827ef8feb179d075f8ed7b691578",
-      "new_hash": "7ff1bba150eef14244e72b87078e99fa1b5b55bebcb9fda7e2b8b1f24a9d14fd",
-      "edit": ""
-    },
-    "printMemRegImm": {
-      "apply_type": "OLD",
-      "old_hash": "6154062a675a628b76a2b597c1ae9736a847979d193f1bfaa3eba0451d948268",
-      "new_hash": "4aafa39c3f666d0c4399738b3c6ae26eea315e76a66d4e469f95b118b68f8c30",
-      "edit": ""
-    },
-    "printMemRegImm34": {
-      "apply_type": "OLD",
-      "old_hash": "acbb291f1ce2460c87f65c91a6feec097552f881aebfdb92b68ffdaf2d5fc17f",
-      "new_hash": "8d2c17803c40c03176c0edcc73bcd27811d9d6ac2cad82fd52595e5c6ec64725",
-      "edit": ""
-    },
-    "printMemRegImm34PCRel": {
-      "apply_type": "OLD",
-      "old_hash": "bf6d163a150ec63552e6605a24114f205145bb62b8fb5a5bc840eecaf1ddd57f",
-      "new_hash": "19db96e5505fb3d5f7ca7bbd759d8bf0b8d246ddbf9dd61dc6371ff8aaa9a7aa",
-      "edit": ""
-    },
-    "printMemRegImmHash": {
-      "apply_type": "OLD",
-      "old_hash": "64166ed92b08a9de7a502289f22e14b25c163d9b479ae2d989e1b5c63c911e13",
-      "new_hash": "f0c950be663103fce9dfc95fde04586f88a471c0cebb4195cb25373978c176bc",
-      "edit": ""
-    },
-    "printMemRegReg": {
-      "apply_type": "OLD",
-      "old_hash": "6e9453d0abd21a9e7b54da5e5115b50ebd56a4757d28bdb4066a37d74527c5bf",
-      "new_hash": "c0ec7eb1d4dce4b6e005970a885336115a8236b49a50bb44f45967a14f37a0eb",
-      "edit": ""
-    },
-    "printOperand": {
-      "apply_type": "OLD",
-      "old_hash": "a92183d6ee3eea5362893fa4024b247e962e394dea3e8d963838107ded9c99c5",
-      "new_hash": "9fb3290ba87aac15ef58a6a0a1c27eef04adb712069d2932fa5044942649a11e",
-      "edit": ""
-    },
-    "printPredicateOperand": {
-      "apply_type": "OLD",
-      "old_hash": "1cda2b4ab653f4dae8812abe8571528d3eb2b8b879d9ab4b748c5e3114fc8387",
-      "new_hash": "0d37b796946b66883adbfb5eb6d6d2715fd7d4dcc01e76415f98cfe932487c23",
-      "edit": ""
-    },
-    "printRegName": {
-      "apply_type": "OLD",
-      "old_hash": "",
-      "new_hash": "2e6aa7c41501e7b57c53b5fdaa886ca86ebd7089891301c0f24b7dcd8a3324c5",
-      "edit": ""
-    },
-    "printS16ImmOperand": {
-      "apply_type": "OLD",
-      "old_hash": "7bb511aaf66903dcf0d422a5433b8e0385d94c05bba7d9590395f7b4dc0a960d",
-      "new_hash": "80a96647da269e5d76890646da3593042d06814dbfc0a6f26e64ac4b8520e80a",
-      "edit": ""
-    },
-    "printS34ImmOperand": {
-      "apply_type": "OLD",
-      "old_hash": "0e2c6c90e88151fcb7053a0d3f7c1f23adbee8e5a61b3188cac94baf52dd80a3",
-      "new_hash": "2480e6a4e0d08563af523f8334ab03fee719defbc60987bd22e9f8b6792899b9",
-      "edit": ""
-    },
-    "printS5ImmOperand": {
-      "apply_type": "OLD",
-      "old_hash": "0f03fa5b16ca7fd0059b0efd8faf0a9cf275108bdd743d84f65cec51dfcb4ea1",
-      "new_hash": "7bccae4841222be92a822afc8b4a862419d1557737f6f31e7c8d72d4d26c6734",
-      "edit": ""
-    },
-    "printTLSCall": {
-      "apply_type": "OLD",
-      "old_hash": "ccfbd2f093b02dcf3132a3f0f8dbd31b553ac6844f201a036ac00ee5d38c0bd9",
-      "new_hash": "572500b0b7d547b2f0627c6bf25d2f0aed27271234d8afe0c8159be075a13bf8",
-      "edit": ""
-    },
-    "printU10ImmOperand": {
-      "apply_type": "OLD",
-      "old_hash": "329c2bb4576258a16cde9a6bddb56c6c2aab830af5ef81685e13d780c5d718a8",
-      "new_hash": "efed5cb256c3fd8ad1da010aa116f265b5af3c0395b48a685bed05208664f84e",
-      "edit": ""
-    },
-    "printU12ImmOperand": {
-      "apply_type": "OLD",
-      "old_hash": "d2c328eca98550f32ee46a015308f0ab5d1d7bffaebe26e14397654db9bfaa56",
-      "new_hash": "a1157724f4d2a16a74034a724ce3da71386c8b6bcb1aec3107a85bc9b070499e",
-      "edit": ""
-    },
-    "printU16ImmOperand": {
-      "apply_type": "OLD",
-      "old_hash": "1ccae5f6b81085142313d7b34cb3b8d76b727143846aa09dea1be7996165ebcd",
-      "new_hash": "96b3c068fcc34315cb98869940c52b7fcc53c4ab97db7d8e6d04a0bc28f49494",
-      "edit": ""
-    },
-    "printU1ImmOperand": {
-      "apply_type": "OLD",
-      "old_hash": "2ec13a0fa3a425f9318c6e66f81d0a4b1311926b3b47f26b797c983abb8e9b06",
-      "new_hash": "14add063ba02ca135e9ab95af77248c9410c0ed05ae40d1d9da36c5a895017d1",
-      "edit": ""
-    },
-    "printU2ImmOperand": {
-      "apply_type": "OLD",
-      "old_hash": "b5b1fab385df93dc26707cae3815f59d5f5613f79477c0ea28e049683a6326f2",
-      "new_hash": "1bdd4fc7273c4fa743ba3332d3f45460150b89bf2da7c5c5f57ce4e7aa7d7ce0",
-      "edit": ""
-    },
-    "printU3ImmOperand": {
-      "apply_type": "OLD",
-      "old_hash": "31a78dedd0eab05c4ccc59c2d7473b6e19a220e29e39c0b6970277c9da597ed3",
-      "new_hash": "4a985f3277a9233344b93606a6ff52730ffaf7b39917b9ac4bba5caabedcaaf6",
-      "edit": ""
-    },
-    "printU4ImmOperand": {
-      "apply_type": "OLD",
-      "old_hash": "b5da847a59417586de4c4dd58690c5a4d8e23db832994e8ac22e52c419d1d99f",
-      "new_hash": "784c9cd8868d7ad6b227fbe0ff91924862ffdb29af2f39ad89f48efeb78b91e3",
-      "edit": ""
-    },
-    "printU5ImmOperand": {
-      "apply_type": "OLD",
-      "old_hash": "04fc13f1ccfb0b361c17ed3eed0f4a188d580eb02e9cf533c60e0f902c9d5308",
-      "new_hash": "a082ee91177d93645b19098fda0c2a34110f4b54253f2050fe2558eef44135e8",
-      "edit": ""
-    },
-    "printU6ImmOperand": {
-      "apply_type": "OLD",
-      "old_hash": "85cf7076d9a8cca621968d357d4b77f0f3836a9bf032e3e2ae9f68c444931607",
-      "new_hash": "7819971c0d52699284edfed676084e9aa48c7e693b949edaae936feafeb5f832",
-      "edit": ""
-    },
-    "printU7ImmOperand": {
-      "apply_type": "OLD",
-      "old_hash": "3bda685d7d6ed4f550dd02d0b8b098687e66ff3ed9151328ec8362b9deed7bfe",
-      "new_hash": "c13555c7693c7aa52a0edc3e7af16f82ace9a13dd4fa8c8ccdba49c94a6193ed",
-      "edit": ""
-    },
-    "printU8ImmOperand": {
-      "apply_type": "OLD",
-      "old_hash": "a38744403d5221940825b10a5f6c42d430c5be4ef1d2f49d82231893a0239f31",
-      "new_hash": "76830ed242e9f7ec8d48f4119f14350016bf43378015821af6be3f9452bd29dd",
-      "edit": ""
-    },
-    "printcrbitm": {
-      "apply_type": "OLD",
-      "old_hash": "ed93ddcf6f973cc7eb12d1b898e5a9299a2885dbe53f73f63672b793d7c18bde",
-      "new_hash": "6aef7937ccfd4055a6af7f1ca9851761a6173c9be62204340bb70830bd1bb326",
-      "edit": ""
-    },
-    "showRegistersWithPercentPrefix": {
-      "apply_type": "OLD",
-      "old_hash": "8f5d37257fdb23ebaeff1baa4877a074baa8208c6ec6e08d9dcc99c3cba87248",
-      "new_hash": "e8454aec44c50d6a4fa18cbdc38d5d2b49a7d0a8f35ab64a826127b90decb818",
-      "edit": ""
-    },
-    "showRegistersWithPrefix": {
-      "apply_type": "OLD",
-      "old_hash": "4d9a4c310c0f65f5266028c8ba3efed35e25397b53028dafa87032ab16c5e4e6",
-      "new_hash": "823ac915ff5e36aef0221553c4251b4e0ea96a896587b79b3f3394893ee82bed",
-      "edit": ""
-    }
-  },
-  "PPCInstPrinter.h": {
-    "\"PPCMCTargetDesc.h\"": {
-      "apply_type": "OLD",
-      "old_hash": "321933e4a3b33bab5e97c6c12212d63428777290b52cfde3ea7089f2d11edd10",
-      "new_hash": "c00944cd062db89032103615e00d70bcc12d9ee37f4a5df8109d7e25881c7967",
-      "edit": ""
-    }
-  },
-  "PPCMCTargetDesc.h": {
-    "\"PPCGenInstrInfo.inc\"": {
-      "apply_type": "OLD",
-      "old_hash": "ec36362bfa2667dd75c36bf9dbf9da9ae58fde9414045ed779f2da859b86f90f",
-      "new_hash": "",
-      "edit": ""
-    },
-    "\"PPCGenRegisterInfo.inc\"": {
-      "apply_type": "OLD",
-      "old_hash": "ae8b462c1a17f021435477f80cb5003126e3176688674ecae32ea1ad0cd86f2a",
-      "new_hash": "",
-      "edit": ""
-    },
-    "\"PPCGenSubtargetInfo.inc\"": {
-      "apply_type": "OLD",
-      "old_hash": "e4f3e0f7dc2b54037b0a9cb2540e8d03ed3cab84775ff96fee93a09ba0dd77d1",
-      "new_hash": "",
-      "edit": ""
-    },
-    "isRunOfOnes": {
-      "apply_type": "OLD",
-      "old_hash": "c3de3de94ebba955e03feb016ca0aed64716eb14a2e89ba46fa56af6f2dd7401",
-      "new_hash": "f2134b05f922fb4eeddbd97be9e2312fdfdab4457e742ec1d15054b6e32f87c7",
-      "edit": ""
-    },
-    "isRunOfOnes64": {
-      "apply_type": "OLD",
-      "old_hash": "93f39dbf36c667d3a320e4d3ea81765ad08950cba0f53fb0f7bc9272c4b57828",
-      "new_hash": "8defa0b1fce2eaf346f4be645281dffe4cb67fb4ff367dd2ed34c37f7205897f",
-      "edit": ""
-    }
-  },
-  "PPCPredicates.h": {
-    "PPC_getPredicate": {
-      "apply_type": "OLD",
-      "old_hash": "16e2de8b27885d9216adae987eea4a12a4e6a1395d5f44462049e6a2aa53fd54",
-      "new_hash": "2745cb11387ee4c9fa7c692356ec2ef778870f08428df3666ae218a23a02927f",
-      "edit": ""
-    },
-    "PPC_getPredicateCondition": {
-      "apply_type": "OLD",
-      "old_hash": "6680b6f42d3644d2ed656077554c6c34a403a62b47d2226810d6ad9f25ef30a8",
-      "new_hash": "96ae9e8cc826c5da2bddd91c8d109856c7234749c064ef9e1d4ec77ddfb2efdc",
-      "edit": ""
-    },
-    "PPC_getPredicateHint": {
-      "apply_type": "OLD",
-      "old_hash": "f51873e40d9a5bc6f49f1cde2418a111b356a438fdb9f20f13b625142f16dbcf",
-      "new_hash": "02eaaa869cf975da8203666135470c113ad9246dd2f73061dbf6ee1706683299",
-      "edit": ""
-    }
-  },
   "AArch64Disassembler.c": {
     "\"AArch64GenInstrInfo.inc\"": {
       "apply_type": "OLD",
@@ -1662,7 +160,7 @@
     },
     "DEFINE_isSignedType": {
       "apply_type": "OLD",
-      "old_hash": "3ea732e1f2870a592203da725a279d1cb48e1486220c3cb0f91c6e331e53eacf",
+      "old_hash": "92a72f34956adf456f2dc66f336295c197cfc197c0d5b8fc39ec1f854129aa05",
       "new_hash": "",
       "edit": ""
     },
@@ -1722,7 +220,7 @@
     },
     "DEFINE_printPredicateAsCounter": {
       "apply_type": "OLD",
-      "old_hash": "2bd81a63a0efdbb2ca9178d9fa559cabf1e672091edd134ebd85f9ab7c73df59",
+      "old_hash": "b891eb7edae008517ca47dbd3af904da42e3eda0991b3f7c17449e55f917190f",
       "new_hash": "1d3e76fdff415cd4e730d4aae0a027d83db300df36cc93bb61c72c43956242f7",
       "edit": ""
     },
@@ -1758,7 +256,7 @@
     },
     "DEFINE_printTypedVectorList": {
       "apply_type": "OLD",
-      "old_hash": "3cb6fe1ac61c6849eb71265509c85cd1a7d0dade63b4163481ce3eb75c6dcbdc",
+      "old_hash": "f5f115e45c282c02ab85f5a70b936a541e740483f3031377ffb426ecfa1240c2",
       "new_hash": "3c37c4f9484dbd2582a793960ef98b79a5e4079b5771842a7be02fdf1929c3b7",
       "edit": ""
     },
@@ -1812,7 +310,7 @@
     },
     "printAMIndexedWB": {
       "apply_type": "OLD",
-      "old_hash": "3008a6b5f16e522f302e09cd7e05514fb448944fac7372808078671c466c3bf0",
+      "old_hash": "266ea1c9a9084ecbd7495fc6c31f56c99786a8f1c734f479d55c244e19cfb4a4",
       "new_hash": "3e918783209f6e82f4bcdf5b8065d44c2b1b904c895d02c7ff0268001b0ad9df",
       "edit": ""
     },
@@ -1824,25 +322,25 @@
     },
     "printAdrAdrpLabel": {
       "apply_type": "OLD",
-      "old_hash": "829d64eeb61dcbe2fbbb12176ac0f6c0724de4d77f476285d86118b00bae3ba8",
+      "old_hash": "c669e2aa867a552417c584c64d9e29a649b55d27f17c7d9e5a518d6629e14b02",
       "new_hash": "5a1292b01d3afb61a40b2d1b7361dd45e9b0e63fd3a7033af1f81b30d08dbdaa",
       "edit": ""
     },
     "printAdrLabel": {
       "apply_type": "OLD",
-      "old_hash": "49da07f14e94a89fee05ef8f91f4a9df664be744a62233da8e2fccf728c455f5",
+      "old_hash": "6a111c958a8f627b4769b9a08e848f8b1888baaeecbbb60f4ca4febdec971c9f",
       "new_hash": "",
       "edit": ""
     },
     "printAdrpLabel": {
       "apply_type": "OLD",
-      "old_hash": "907918a2a10d59d0a16e48ff9571da49891e6c84b91410930996a9d8ead53c69",
+      "old_hash": "79c1148eb6b6000a093458a5f578b281fd96bbae9e59de56213dd4d95fff3616",
       "new_hash": "",
       "edit": ""
     },
     "printAlignedLabel": {
       "apply_type": "OLD",
-      "old_hash": "318bd3c83e1624766efc40367ba62f3549ef2999e736fc72a06e12d67c9ca71e",
+      "old_hash": "b16d0638e88e327c4a3c4491f6a6270b24a54dc2af4f667b58f9e4c90d59b218",
       "new_hash": "099a55007ceaa4286a7f3ef43e14493e3e9825d7df13e8941c102e33864915b3",
       "edit": ""
     },
@@ -1896,7 +394,7 @@
     },
     "printInst": {
       "apply_type": "OLD",
-      "old_hash": "d10c9bd536e404847c2e40bce4e3da86b891fbb66b15d868c0be57f485f3f1ac",
+      "old_hash": "4bbe09edf0ffb2abf534ac3c5572eccbc3baa941cc8047d76dab0fdd1dd72781",
       "new_hash": "",
       "edit": ""
     },
@@ -1926,7 +424,7 @@
     },
     "printOperand": {
       "apply_type": "OLD",
-      "old_hash": "bad0223bc0b3d47705fcf1a3de6294040f41e619bb88baf7622f79f4a9c196fb",
+      "old_hash": "18ebc42e35394951a9935853f326113613ad0ec6f67804920cd2d2a3cbc21a51",
       "new_hash": "5794b32405e7d6a5c51b058e086cd978553996fe7395ddf9c046b4879620512d",
       "edit": ""
     },
@@ -1980,7 +478,7 @@
     },
     "printSVEPattern": {
       "apply_type": "OLD",
-      "old_hash": "fa41064f8852c15334745f29f622a606cb341be16eb4959b340417b0a682eff7",
+      "old_hash": "96472134489811a13945b6cf97a975fa86ed0ab5e6cf9f3df445bd1b3eb566b4",
       "new_hash": "77aef0a120cc4fb1cdd668113cfb6f8dfbc5018bcf375ee745d2f415e6ea1717",
       "edit": ""
     },
@@ -2028,7 +526,7 @@
     },
     "printUImm12Offset": {
       "apply_type": "OLD",
-      "old_hash": "4eac20c0c67389228d78bdae46a29e5f32df7ad2202dd5893dabffba49319b7d",
+      "old_hash": "83a656ad8e9b9f949d4ce486839d75bd6beef10308737c49d89230ae117a1184",
       "new_hash": "47363cd6a2686d6a9e73271238c087d86d9d6ecf32757caf60004151785270f1",
       "edit": ""
     },
@@ -2376,5 +874,1539 @@
       "new_hash": "b148e4b22d7b4797a64a9a818430da372d8224dee020bf5ec049c07677bff5cc",
       "edit": ""
     }
+  },
+  "LoongArchDisassembler.c": {
+    "DEFINE_decodeSImmOperand": {
+      "apply_type": "OLD",
+      "old_hash": "978e6fa02e483da973e1a2db8364412bb35bedd7ec3d706c34d69fa0be4662da",
+      "new_hash": "2e0923888ce2b3d1d8232f58de6b8b4a2e8389a8cb01ad2ad23537816ed94058",
+      "edit": ""
+    },
+    "DEFINE_decodeUImmOperand": {
+      "apply_type": "OLD",
+      "old_hash": "261990e19755ad200968a5d65db5ee4d6b092d600191863bd6aeb0e91d2c26cd",
+      "new_hash": "3477f349c15b42a931c82bc7a0ad7a731a897ae50ed4b68dd427bc6a059a1a34",
+      "edit": ""
+    },
+    "LoongArch_LLVM_getInstruction": {
+      "apply_type": "OLD",
+      "old_hash": "04624c9db019dd020e82ee41334a8d0e4c352abe1785235d213bac04f7253d89",
+      "new_hash": "",
+      "edit": ""
+    },
+    "createLoongArchDisassembler": {
+      "apply_type": "OLD",
+      "old_hash": "",
+      "new_hash": "1ee83eca800bbf0a9ccc6f995cec889d7e6e7831ab3a7abd40d680061acf582e",
+      "edit": ""
+    },
+    "getInstruction": {
+      "apply_type": "OLD",
+      "old_hash": "86404384397abcca883dbe08a53730bfa21828b8a85a50c9e947f3bbb04cb025",
+      "new_hash": "dbb085f16ddc2167cb45c4809c52150f5b395c74296a943d2e4087a32d998d4d",
+      "edit": ""
+    }
+  },
+  "LoongArchInstPrinter.c": {
+    "LoongArch_LLVM_getRegisterName": {
+      "apply_type": "OLD",
+      "old_hash": "8d67a45de9adf396250154cbbc8edd20734147f0e1988e94930c0ffc36a8e3bd",
+      "new_hash": "",
+      "edit": ""
+    },
+    "LoongArch_LLVM_printInst": {
+      "apply_type": "OLD",
+      "old_hash": "c4a9f9e88a68f78af97c420932473c8e6dd1ee09f40b1cc714150f3b3132b9b0",
+      "new_hash": "",
+      "edit": ""
+    },
+    "applyTargetSpecificCLOption": {
+      "apply_type": "OLD",
+      "old_hash": "",
+      "new_hash": "62221b1ff079f7e38026a1de3c17102af8086e365775e60f4ec1b2f1b13b0714",
+      "edit": ""
+    },
+    "getRegisterName": {
+      "apply_type": "OLD",
+      "old_hash": "",
+      "new_hash": "a721269763ab9f073702b44cba0ad17cffb7d1f7fda22cc9b76846053db5fda6",
+      "edit": ""
+    },
+    "printAtomicMemOp": {
+      "apply_type": "OLD",
+      "old_hash": "bc97ae2773231ada9f54fdbb90bb4cf14e017d917b67a8aac0d4f298fdf71065",
+      "new_hash": "f2023da6a98e0c5ae41ebc05cc5a6a1ea8e008bdcb41c2bc9601b0927a95828b",
+      "edit": ""
+    },
+    "printInst": {
+      "apply_type": "OLD",
+      "old_hash": "8e9fea3b8e6b482af249093432a58476b128f910b1ea60c501ede3ffccbaf369",
+      "new_hash": "a3d4481cb3205d752d78020f85e84241043b94817daf3e46a0a31b22d3a57821",
+      "edit": ""
+    },
+    "printOperand": {
+      "apply_type": "OLD",
+      "old_hash": "52d1dd52aec106561e920f62a120012517f3fe6eb4e608d8997c1e02f0fc58b3",
+      "new_hash": "71818dce3c22706e9ae2dc4a966c3c5f8ab2d41c85054c8bd91766410a3678c3",
+      "edit": ""
+    },
+    "printRegName": {
+      "apply_type": "OLD",
+      "old_hash": "20556696f9576066c8ef8a3e12d642d2aabf2cbc1c8d23615cf3ea66ec5cfa7a",
+      "new_hash": "c909306f23247ee039798cfc651686956874a047f43099acfa46ed26dc0c1bae",
+      "edit": ""
+    }
+  },
+  "ARMDisassembler.c": {
+    "\"ARMInstPrinter.h\"": {
+      "apply_type": "OLD",
+      "old_hash": "",
+      "new_hash": "95ad79a83ba298934f23d4a96d7df51fc1aa4640f1219d6200ec3d960ef25ee4",
+      "edit": ""
+    },
+    "ARM_LLVM_getInstruction": {
+      "apply_type": "OLD",
+      "old_hash": "a0821460ef53746eb5067e94b6cf5edfa595c94e9b83fb3721370d27f9972d7e",
+      "new_hash": "",
+      "edit": ""
+    },
+    "AddThumb1SBit": {
+      "apply_type": "OLD",
+      "old_hash": "95f5f496c0cefdcd9ca0ef2260b36141ff6ad153125180909894d2b7acf98ae0",
+      "new_hash": "ee6273e09d4452f66e159e234a5b3b5a950c28435b5d3b10dbeabeee4caea53c",
+      "edit": ""
+    },
+    "AddThumbPredicate": {
+      "apply_type": "OLD",
+      "old_hash": "5573de6fcc4afa52a96154e8f0bcfba9a2244a5468a374df23f90dc02fddb9ae",
+      "new_hash": "36ed8f8dd4be8be3154ba0539568d7ece70994a67b35766a27c0e19cea11513c",
+      "edit": ""
+    },
+    "DecodeAddrMode2IdxInstruction": {
+      "apply_type": "OLD",
+      "old_hash": "4b432ecc5029e249ab41b6bec82de9aa4a79b1cb59b661d6cafa66e76c4ff324",
+      "new_hash": "3344be502aba63804c6f8c04abddc1f1b9c46e8ec0edc65b9e24f2ad2d08eed5",
+      "edit": ""
+    },
+    "DecodeBFAfterTargetOperand": {
+      "apply_type": "OLD",
+      "old_hash": "08109600525dbe56f3fa90e7f30d6b489b889f650efcc158378f952bd5cb1531",
+      "new_hash": "d5b6473a7ae44c2b6b4719e02496312eec0a8943814c9ba6fc6f3ef363e054c0",
+      "edit": ""
+    },
+    "DecodeBankedReg": {
+      "apply_type": "OLD",
+      "old_hash": "8f0dc5c9b1ebbe5d34e7e49d3d298951885bc05583ec16cf6e6ecdd96d0ce12e",
+      "new_hash": "09fe278cb0491368bd73c4947277f95b0432d61f47f5ad082615414159149212",
+      "edit": ""
+    },
+    "DecodeCopMemInstruction": {
+      "apply_type": "OLD",
+      "old_hash": "de10bfb4efaf077a24827f5e6437c4b5478c8916c064a392ea697c8361eacd07",
+      "new_hash": "c68d236650331f6a54cc6100c3f48ee5f8908e9b10897a8af794817b01f8a2a5",
+      "edit": ""
+    },
+    "DecodeCoprocessor": {
+      "apply_type": "OLD",
+      "old_hash": "dd23121fec4ee0dcc23db2e4007c3ebb65921ae31e69f3e1cba61501499d0875",
+      "new_hash": "8200b70f2852a622b3364e1aec801fc1ad61a5c759db9eb4817d923af641ad50",
+      "edit": ""
+    },
+    "DecodeDPRRegListOperand": {
+      "apply_type": "OLD",
+      "old_hash": "b9a80c3cbe364f1505960bf05f06bbfe54506e479e77b61e5afcc08b483e5da1",
+      "new_hash": "a569c1edaeca19998e49308e3e7560b8d15f790633f8cf7b5cfcd6976d4e3f8c",
+      "edit": ""
+    },
+    "DecodeHINTInstruction": {
+      "apply_type": "OLD",
+      "old_hash": "180d1dbe33f8c7a769107babc9bffabe63d4d3f39a52fad3b2555e81a3b8f7a8",
+      "new_hash": "d2920fd5b23d29750da4d56af19b549104169700e447847a1a826567b5ee384b",
+      "edit": ""
+    },
+    "DecodeLOLoop": {
+      "apply_type": "OLD",
+      "old_hash": "afd1c96bc5cae0a0392e030092a61bbe678fa23398a2ff4ac0b0d0a20382f208",
+      "new_hash": "db8c5550e17168233d96d96059c1e09f1148f354878ffe42119ce874565fdf0b",
+      "edit": ""
+    },
+    "DecodeMSRMask": {
+      "apply_type": "OLD",
+      "old_hash": "a4a37d481c70610187f77726f44a3338812a639906854f8aa25cbf0900058d77",
+      "new_hash": "5016e36d7b50485d4357f36dff0c206506619a661ea3f7a0ebb1a117165d8a79",
+      "edit": ""
+    },
+    "DecodeMVEOverlappingLongShift": {
+      "apply_type": "OLD",
+      "old_hash": "eb0dcaf10302271dbcfa2d5567b91a3546e68722591fbf36679b5354a3cf78cd",
+      "new_hash": "73fed3628164afc0cdafa7c0c5c29e2c2230223a822d368189b85ce002106469",
+      "edit": ""
+    },
+    "DecodeMVEVMOVQtoDReg": {
+      "apply_type": "OLD",
+      "old_hash": "25c166bd52da11c5883ac9856c24473cabf31794bc8c5b7a354daaac52ee3325",
+      "new_hash": "e01dfe2c1db3ab028db911c5bd886f76b55c24d7bbc0b3e897a2bbaa0ce6744a",
+      "edit": ""
+    },
+    "DecodeMVE_MEM_pre": {
+      "apply_type": "OLD",
+      "old_hash": "6e47cb7601c1e4eac9ea75a8d1dab9c8635432f049f0ab287a8ce5adbd5685b6",
+      "new_hash": "a11705666d438ebd1f9c7e3fa9f3a189012e9cc93ede549921e6f3c837a23ada",
+      "edit": ""
+    },
+    "DecodeMveVCTP": {
+      "apply_type": "OLD",
+      "old_hash": "12ee3772daf26268463bdf02cf025d2992c7f384809b62a7d987e7d0c4ff2db0",
+      "new_hash": "a76198f25e5e0f9ff481fd9d3c9abb87670315a913f9f7e40d9c6857ed7537d9",
+      "edit": ""
+    },
+    "DecodeNEONComplexLane64Instruction": {
+      "apply_type": "OLD",
+      "old_hash": "0eef7137074640d37a31557ed8cb71396f96ff66d23f0c101c9951e4110fffb0",
+      "new_hash": "049e1682961590f4ca4d4d5294a5a3f6ae6010368b2941ea5ae82243d6632853",
+      "edit": ""
+    },
+    "DecodePredicateOperand": {
+      "apply_type": "OLD",
+      "old_hash": "58ddc2d7f52d45ea3ccd0856bbcd7f32d136a24c8196b258be92c4eed6a0bd28",
+      "new_hash": "777e16b280bf44870e23e1c841318c7e5482f4f5461ecff030757652bbcf4e2a",
+      "edit": ""
+    },
+    "DecodeRegListOperand": {
+      "apply_type": "OLD",
+      "old_hash": "98f3f08ea7ab1be3c3bd753dd28f5f99976881c5abc5df88bb694bc1a3804c22",
+      "new_hash": "198f27e7978abc81e58089e9fb5b5bb3cf74e183cd46bbe7d86f831aa7f66adf",
+      "edit": ""
+    },
+    "DecodeSORegMemOperand": {
+      "apply_type": "OLD",
+      "old_hash": "b2227c76cd763f0dc348043ade36236489c8997d988f73ee86b6a4e7cfa406e1",
+      "new_hash": "5b48e3c244940fd13918bd34ac445a4054088259e4a6fd891a95afbaabd717f4",
+      "edit": ""
+    },
+    "DecodeSPRRegListOperand": {
+      "apply_type": "OLD",
+      "old_hash": "1dfb41e49a57b18d07b2ff38e5debf8aa98323e1052f4d14398535f042939216",
+      "new_hash": "a15e99e571c06dc8245187dad8eed767dcd01a2d970cba5e40e9f763665fffef",
+      "edit": ""
+    },
+    "DecodeT2AddrModeImm8": {
+      "apply_type": "OLD",
+      "old_hash": "c32f40c9944df86d036abaf2d86e22b5e2eac10a27ae0231f66ff2d48ef7f4b3",
+      "new_hash": "f6a83cd75add959dad18d34f1e8e7a04bd2650efae8d1fd6af1e4f35bc98b5d9",
+      "edit": ""
+    },
+    "DecodeT2LdStPre": {
+      "apply_type": "OLD",
+      "old_hash": "f00e174f356e62d422a96826bb0db03c50f9036b8d880f8ccb9961d3cc31888c",
+      "new_hash": "7bb42b837b8b3d24a36f060d4a6f1452e395bfa934f28c156be8411ddc9f11d3",
+      "edit": ""
+    },
+    "DecodeT2SOImm": {
+      "apply_type": "OLD",
+      "old_hash": "47594759546172ee88b4ce5b088bff8d315903e0d4068196c5869eda95bb6a3a",
+      "new_hash": "cbe6d50c0c012cee271bfede1bce414d73851440d87fb71a3790e91ae759e039",
+      "edit": ""
+    },
+    "DecodeThumbBLXOffset": {
+      "apply_type": "OLD",
+      "old_hash": "de0f984972ddfaa3edf04e8347315b6624525522d85885f689afc8fa5c3239ee",
+      "new_hash": "e42325ddadd6f84c7a56277fc61e6f879160c0a250a19601d58ff48fb2afc9e2",
+      "edit": ""
+    },
+    "DecodeVPTMaskOperand": {
+      "apply_type": "OLD",
+      "old_hash": "9e9be3cb7845da6d4c5336797421aa92210188b23ee73cf5154e4d851a2ffd49",
+      "new_hash": "5f831a1b9cee232e5c667e2b95bcada8f5d2e10e56e5f27cfe904a9830f7f339",
+      "edit": ""
+    },
+    "DecodeVpredNOperand": {
+      "apply_type": "OLD",
+      "old_hash": "",
+      "new_hash": "a84ee46adfefbc0d1fdab9c6f5324a9bb324c1a122ac4ac502827240a6230e86",
+      "edit": ""
+    },
+    "DecoderForMRRC2AndMCRR2": {
+      "apply_type": "OLD",
+      "old_hash": "6951fd79b5390c810eedaaf7b903b3b29eb212d155791af226e47c8478c50a21",
+      "new_hash": "dc9e397cd6b2d69c635e535a753364c3d43507bc5c7410fb2246df10ff4d0c1d",
+      "edit": ""
+    },
+    "UpdateThumbVFPPredicate": {
+      "apply_type": "OLD",
+      "old_hash": "f3c01f859c405a12b7db109afe3a70854a923a9b7473fbd6fbed0248feea74fa",
+      "new_hash": "0e92a16b350185abea1aa073bff5fe5a03b3394dd842700b5f11251b50605a4a",
+      "edit": ""
+    },
+    "checkDecodedInstruction": {
+      "apply_type": "OLD",
+      "old_hash": "89be7681c295f7309a4d4840f3d651a1cd8c0ae47930aa38ddf31cbcac09cc31",
+      "new_hash": "5ac65fb3a6939b724f963c7a0f1fd196ce91b82972b1b4e6754bf626ca7db83d",
+      "edit": ""
+    },
+    "createARMDisassembler": {
+      "apply_type": "OLD",
+      "old_hash": "",
+      "new_hash": "606ce64d2ffb7388277a2167d951b14bec44db29d7fcba17c19c5eea0f6e4f58",
+      "edit": ""
+    },
+    "endianSensitiveOpcode16": {
+      "apply_type": "OLD",
+      "old_hash": "62d92f7c8bac5715e5d6b4a5f24d9db2bf4bbe65908df8db065f21d6acc9f3b3",
+      "new_hash": "",
+      "edit": ""
+    },
+    "endianSensitiveOpcode32": {
+      "apply_type": "OLD",
+      "old_hash": "32c2bb4855de0fc02246b118ad5b307089de909de2cc6dbc2cbe237b97bb1722",
+      "new_hash": "",
+      "edit": ""
+    },
+    "getARMInstruction": {
+      "apply_type": "OLD",
+      "old_hash": "3cfa847b96daa603bd65c8366c84c6b2cdbb1a2160fd67d86ac92418937cf594",
+      "new_hash": "c012b9181a088d143379d4256f211e62d5c2b8178cf0a9d18431d1f84c99d656",
+      "edit": ""
+    },
+    "getInstruction": {
+      "apply_type": "OLD",
+      "old_hash": "e2ed90511c2d65ff5dffeaf8508959e3c4957813b7ca68f55c669573e47ef3d7",
+      "new_hash": "d4bd83004cec8ebba0d20fe9612754fb8f08265655a91530cb519fc431538e9a",
+      "edit": ""
+    },
+    "getThumbInstruction": {
+      "apply_type": "OLD",
+      "old_hash": "4f8582b2c8b4f69f7e89aa082837ed6569e047a73cb71d3b160a035f0e944ceb",
+      "new_hash": "49694b8dee4cf98ca41560638e4bfb29f0f7fcf5ed687735d3ef4e8a6862964c",
+      "edit": ""
+    },
+    "isVectorPredicable": {
+      "apply_type": "OLD",
+      "old_hash": "e0025f215966ee66db69bb0a71f1376707c17f753b1dc77f6ca4853db9fadc2f",
+      "new_hash": "1fde7ed766d751e64cbea32d32b42f4162c8d58cfe997ed17060f425f5c89eb7",
+      "edit": ""
+    },
+    "suggestBytesToSkip": {
+      "apply_type": "OLD",
+      "old_hash": "",
+      "new_hash": "b77ec89cd8678b3d6730afb7dfcfc6ee6d9e912a23d935f9df6ec0b863f5c392",
+      "edit": ""
+    },
+    "tryAddingPcLoadReferenceComment": {
+      "apply_type": "OLD",
+      "old_hash": "751df9714b84ffda1c97fc4b8acae9b044ca3acf28e6d831f2b523414b42a68a",
+      "new_hash": "0de15de8e60f76f9e940a4b2dabecfdfdc815682b8ae8646ff30397bb7082e05",
+      "edit": ""
+    },
+    "tryAddingSymbolicOperand": {
+      "apply_type": "OLD",
+      "old_hash": "861b30637780e686b35e431dd52e74e2667c86c845fbd4bbf770d2c41f61791b",
+      "new_hash": "b63ac0e4c46e6a5e7f7a25316f96338ea2260422377025e03888178a8bab3fbc",
+      "edit": ""
+    }
+  },
+  "ARMInstPrinter.c": {
+    "ARM_LLVM_getRegisterName": {
+      "apply_type": "OLD",
+      "old_hash": "9da8c4a5357828238434cbe7a985c4cf190dffa539358d0262b3d3dd5075dc64",
+      "new_hash": "",
+      "edit": ""
+    },
+    "ARM_LLVM_printInstruction": {
+      "apply_type": "OLD",
+      "old_hash": "48dced0ebb11e7013d8aaf2f0192acc1552f659e6f6fdc6f51092c72f724d696",
+      "new_hash": "",
+      "edit": ""
+    },
+    "DEFINE_printAddrMode3Operand": {
+      "apply_type": "OLD",
+      "old_hash": "3465467d84e4f6b405e5cbfca431db06595cd842ea061c545ca33a3d0d67ebac",
+      "new_hash": "5ebf44366c8f7c61f7552e5dcfcf83e911cbed44b2ea87f33a077d0bf25ada16",
+      "edit": ""
+    },
+    "DEFINE_printAddrMode5FP16Operand": {
+      "apply_type": "OLD",
+      "old_hash": "7f6c12957efdfca8ce6c659be247266d4cef75b0363c8bb17498c05ef5ac9996",
+      "new_hash": "f1bd495e5f78affe912d3a6588669d7c64d3d535298bb8905c43e1aca67bcc61",
+      "edit": ""
+    },
+    "DEFINE_printAddrMode5Operand": {
+      "apply_type": "OLD",
+      "old_hash": "3298f3b54199bd91540681c8a6f5097374c0c092f622bc11e3ec7dcea655b73d",
+      "new_hash": "fe53f899c5ae94df4584a32966ca4cbf168d6c17aa512c93c887a86f68edeedf",
+      "edit": ""
+    },
+    "DEFINE_printAddrModeImm12Operand": {
+      "apply_type": "OLD",
+      "old_hash": "9c56875cc128b4de2039c01f4ae4a4f83899ae91fe67db1d919aa1577d74585d",
+      "new_hash": "8f849a538609074c063005143e2b98d8504e0bfa381f8e7efba20c38d999f631",
+      "edit": ""
+    },
+    "DEFINE_printAdrLabelOperand": {
+      "apply_type": "OLD",
+      "old_hash": "d708ba7a37f44b88633ea4dd3af38b3477c2481b634ecd2b12eba41c42a03b96",
+      "new_hash": "fde2c077357e7b7d03e9deccbba6171466391cdf977c51c18646939962f622af",
+      "edit": ""
+    },
+    "DEFINE_printComplexRotationOp": {
+      "apply_type": "OLD",
+      "old_hash": "2eec8c4c5f5e3815a6b04486be92bf7816d3bf4ecdda898f3e121e4070f3c994",
+      "new_hash": "6f4d6c4a3ed3ced4aca25e43e23e6fe0f2956ddf484cc84d745b9d22411e4167",
+      "edit": ""
+    },
+    "DEFINE_printMveAddrModeRQOperand": {
+      "apply_type": "OLD",
+      "old_hash": "f705b307f2b2f7eed1a3b50ad049ae6192e6fac2674328401d0777fd27d48507",
+      "new_hash": "7c98aa8d66ac67235f60c36d74234ee5300cb3f092adf82c4ea23c8108b2e5e3",
+      "edit": ""
+    },
+    "DEFINE_printT2AddrModeImm8Operand": {
+      "apply_type": "OLD",
+      "old_hash": "c7384049db5536c34de4b632b5dcfe91821359ba0ef99be0a01fc8aa0ccb37b4",
+      "new_hash": "57ea242ad83c19a6e2a91c3212f362daa3c2c5e9e467596834d67f82cc548123",
+      "edit": ""
+    },
+    "DEFINE_printT2AddrModeImm8s4Operand": {
+      "apply_type": "OLD",
+      "old_hash": "84ff913b6dc420f1cf555c572618f623d9e918cfa01aefd94bfc18d8d44b9bc8",
+      "new_hash": "7ba528b783aa0d5633a9d60568918fce10f9d9271c501f857ba9b5be5a850793",
+      "edit": ""
+    },
+    "applyTargetSpecificCLOption": {
+      "apply_type": "OLD",
+      "old_hash": "",
+      "new_hash": "1939abc1c7e369df85230bae9d6cb351140861961d09a79108b648a1bf7d4670",
+      "edit": ""
+    },
+    "printAM2PreOrOffsetIndexOp": {
+      "apply_type": "OLD",
+      "old_hash": "b2b577f301678cda8d99cd55ab30710c96595ac9d29450ae8e3e14804017ff9f",
+      "new_hash": "48cae61a4b7583a9ee9edbbc73e11555138907b449e423dea8f66dda1214e502",
+      "edit": ""
+    },
+    "printAM3PreOrOffsetIndexOp": {
+      "apply_type": "OLD",
+      "old_hash": "61d2c8c5dc606854a7c9da04158afd139e31d95153529390129fe9ea0f224249",
+      "new_hash": "c4b87cb2e09ec47c9e7dc4e754a2e8c0da72251cd79912ec6cd0b479df2cd202",
+      "edit": ""
+    },
+    "printAddrMode2OffsetOperand": {
+      "apply_type": "OLD",
+      "old_hash": "d4f2d7d0c119a886ac2bf5190e453d420603cb7d84c41e96f58729d322cc29fd",
+      "new_hash": "88e0b86d7f70719d972df62ae8e037d2391866f98fbc7d83646ef12b4eabbe70",
+      "edit": ""
+    },
+    "printAddrMode2Operand": {
+      "apply_type": "OLD",
+      "old_hash": "56d54efabe4b1d0b8cfc5d5a049e901ed9a320f2613d23168cee7937b8dc1da5",
+      "new_hash": "436b9367908381ac37cc8963124f2480d6ece9b489c780c17f86b22649e8ed50",
+      "edit": ""
+    },
+    "printAddrMode3OffsetOperand": {
+      "apply_type": "OLD",
+      "old_hash": "40aba1dc4d59f036fa5b612d8c52f8d762f987d95c9cd8a988493d5cc784b8e0",
+      "new_hash": "96766b1cd7f68f3fa10b91049638360d82fa05fedadba1467ae795fb0edf0abe",
+      "edit": ""
+    },
+    "printAddrMode6Operand": {
+      "apply_type": "OLD",
+      "old_hash": "10f92c18bb1110e9da2666b6c5322eefd983c1aab4b9aa52062b3b583b2388fc",
+      "new_hash": "e503d666f1f4932fcc444fcc19eebccdca754b706c28bba1d2f3abff729905bd",
+      "edit": ""
+    },
+    "printAddrMode7Operand": {
+      "apply_type": "OLD",
+      "old_hash": "0fac2b9e920cd89ee18f646ce4686cc18d65414486f06caae89bf35f0cc48f65",
+      "new_hash": "18126aa815e29c9c0c21184a324e06a3ab7b45be85e8a88e77af25e1d1d5234d",
+      "edit": ""
+    },
+    "printAddrModeTBB": {
+      "apply_type": "OLD",
+      "old_hash": "2b6af4d44046ed26cc4907bbdbce871f58be9306031974e75118bb06873c94f4",
+      "new_hash": "e0e3aa06f473ddbb5e9d8681c73ff2b3484ed6b4d9bf5e67160dd694f020be25",
+      "edit": ""
+    },
+    "printAddrModeTBH": {
+      "apply_type": "OLD",
+      "old_hash": "625ea2b46f1ef5dbd9c1fe363d9bf334d138628c3ce79293f2b4650321bab7aa",
+      "new_hash": "142ae5db1e6c741a6bd93b85e6581e2bc4b39ed5fe53f3285bc00584576acfb8",
+      "edit": ""
+    },
+    "printBankedRegOperand": {
+      "apply_type": "OLD",
+      "old_hash": "b789ca0fc06aac2a10ceb57a2e00b8492c587aa59499cf69ea8b2baf74ca5973",
+      "new_hash": "b01a60a479b0d736ff85868dc7abc5835f2465c0b9f019f79337f23171779cb9",
+      "edit": ""
+    },
+    "printBitfieldInvMaskImmOperand": {
+      "apply_type": "OLD",
+      "old_hash": "69a5a2c342bbd121ec05acc8449754f5e4156ac71a1258c69e5002c03ee75a34",
+      "new_hash": "4aefbf0f1181fc0ad7e33dc2fc21aa2ef29dd90407d691d7a1f29dc1bb1a5b16",
+      "edit": ""
+    },
+    "printCImmediate": {
+      "apply_type": "OLD",
+      "old_hash": "652fa22eb596c91f03f369f646886723a854bf32abed58d6df3a83cde6e95384",
+      "new_hash": "18189a16121e22d13f068b9e5c854fdaf7b093a03899f363320b21d115e6a802",
+      "edit": ""
+    },
+    "printCoprocOptionImm": {
+      "apply_type": "OLD",
+      "old_hash": "d8022789f9bce2fed4423f14122462a11ae1044a7bd8d05b8722ff1e86823c99",
+      "new_hash": "b3a402dce4d1153bfb2a5f0b847d836e4cb99da6344c9423cf1ab0f51751f104",
+      "edit": ""
+    },
+    "printFBits16": {
+      "apply_type": "OLD",
+      "old_hash": "b0482329e694f34c699bbd6e464417fbdd348fd7a000ab375411c8fac5f01b95",
+      "new_hash": "5d67d2312505ebb26c996b8ad69103ab68d95553c58d1121781bf06b4f1c7127",
+      "edit": ""
+    },
+    "printFBits32": {
+      "apply_type": "OLD",
+      "old_hash": "cf8b1fbec5f2523b933028dd0ed39912d4783035d79522e79c718fd05639a67d",
+      "new_hash": "a5fd6f698da980b74803e7d70e9e34a67a02037c6f784f7df361f04eba2b58ba",
+      "edit": ""
+    },
+    "printFPImmOperand": {
+      "apply_type": "OLD",
+      "old_hash": "f145952b34b4c7651b5ec4b42e5ca351f39f386d5cb7bc31e238b50626fd089c",
+      "new_hash": "d8e1d8d1c222437dc7ef4fecb2d8e810923871ca819c73fe63cc4db2de8e3b6f",
+      "edit": ""
+    },
+    "printImmPlusOneOperand": {
+      "apply_type": "OLD",
+      "old_hash": "ec1dafafd60de21c0a274d68812f99e12f0baaff5067f184e4374ff2b37a28f7",
+      "new_hash": "eb5a91897ddd33f62104f816588f84282aa3d90fa8a69d38ef345a861c7e497e",
+      "edit": ""
+    },
+    "printInst": {
+      "apply_type": "OLD",
+      "old_hash": "3032c82a512aee24413d9ea498609749ff006cbc3a4ca5fd38141b221c34c61a",
+      "new_hash": "ed5337f98a7ad8a23ff50efc09fb1d937af30124d5489524fec3855015d831b2",
+      "edit": ""
+    },
+    "printLdStmModeOperand": {
+      "apply_type": "OLD",
+      "old_hash": "e0915e25965812eeba03a18b081c60a258b0b8009af3d98774da71324a26a91f",
+      "new_hash": "a6f788b71bc47f9aabcc567c2d00777e2725732f07a5b515bca08501fde9c796",
+      "edit": ""
+    },
+    "printMSRMaskOperand": {
+      "apply_type": "OLD",
+      "old_hash": "36b8784994fcdbcf324f7d85f58656adacbb82e53406de60cc8dccb0da757b50",
+      "new_hash": "fe94465767c783435dcd121e8f84437a67a7c1219daf566178059567e9d295b6",
+      "edit": ""
+    },
+    "printMemBOption": {
+      "apply_type": "OLD",
+      "old_hash": "d2ac567c8e4947b8a7189783a6b1d4659f8186471c2f8458801af60ccea51240",
+      "new_hash": "83efbcd369ce2d8abce14dabbe6b9620c7a7bde228f15955718cb41c168c353c",
+      "edit": ""
+    },
+    "printModImmOperand": {
+      "apply_type": "OLD",
+      "old_hash": "1788c640009cc9e48d624b96019c445aeb1346e5d8ce7f5cd9376bf03ce84d7a",
+      "new_hash": "03c0c913a770fd7dabc604d8c1c6dc8a06fe2afaa3fdf9c798d521c6c99f3948",
+      "edit": ""
+    },
+    "printMveSaturateOp": {
+      "apply_type": "OLD",
+      "old_hash": "19041125e884b3bcfdebd4a88c316dbff6ed17637baac100fc35681db10f3346",
+      "new_hash": "8daaad36c055497f8ba1ebb559fd65c427fec3c74576d6c216a9fac73e784835",
+      "edit": ""
+    },
+    "printNoHashImmediate": {
+      "apply_type": "OLD",
+      "old_hash": "5eca0dcad4b6a9556639c1e27d56eafd7148cc22ff5c44dcb86d39b322cae69e",
+      "new_hash": "6ba021d35466d081b88b56b2e6d8920533c77885bb8b7eaa8185b0c026c00396",
+      "edit": ""
+    },
+    "printOperand": {
+      "apply_type": "OLD",
+      "old_hash": "40455b1543c1df57c63397d1f01e955be51c97a10149ee4ad3c4e982833d89f4",
+      "new_hash": "",
+      "edit": ""
+    },
+    "printOperandAddr": {
+      "apply_type": "OLD",
+      "old_hash": "6731ee5b725c31f0ffa5bd0efd912c031f18e5407c4161ff972f17c4c9d797b7",
+      "new_hash": "",
+      "edit": ""
+    },
+    "printPCLabel": {
+      "apply_type": "OLD",
+      "old_hash": "9fed7969e83fad1c33bee6c48ecf4c24d475d84e8cb42858f6bddc6237c951e1",
+      "new_hash": "ade84eb1a15afb848ef6613ecc22dd9635c287961d68284954e0d80da13af5bb",
+      "edit": ""
+    },
+    "printPImmediate": {
+      "apply_type": "OLD",
+      "old_hash": "f0aeba64412d7ace872e047ebc9e674415f5a5828d0b131b4ad0b51746165b6c",
+      "new_hash": "682ddf037f5302a3a5b0b0b84181f1a90ed7ccf475e68142f11a6496624238fc",
+      "edit": ""
+    },
+    "printPKHASRShiftImm": {
+      "apply_type": "OLD",
+      "old_hash": "71d2c4b54a4593979975483eb0b1235c7e98ff8279b2bb0e10628b5323021062",
+      "new_hash": "f810bcad5c2a91153bb142e6d4a89c7ce5c33b8296179e8e0f16cee6bb656670",
+      "edit": ""
+    },
+    "printPKHLSLShiftImm": {
+      "apply_type": "OLD",
+      "old_hash": "bdf1d8a29f6ba423b1e5e2aa8ecb75025135cc9e0b00afc03bf8cbfa91c3bbed",
+      "new_hash": "e34539b6c5f59574f671e1456bd2f260b784e5e32a8f27b1343589543b41c9b1",
+      "edit": ""
+    },
+    "printPostIdxImm8Operand": {
+      "apply_type": "OLD",
+      "old_hash": "19577955ef15d0ffd3f4da5d6250103256997f30603326a3a900ca344f66999a",
+      "new_hash": "5ea82276e26da933866ac05a2c4d578d5dfea56121d4c83861683ef9cf6e626f",
+      "edit": ""
+    },
+    "printPostIdxImm8s4Operand": {
+      "apply_type": "OLD",
+      "old_hash": "d86795b49368c0085fdce9d3b0d225a737f9371a8c3b63b560d6e47de1886350",
+      "new_hash": "bdcbc4287c441472f3b7a5af9a5fd263d58bf5d506b6cd6d65d5c9f78bd1f58f",
+      "edit": ""
+    },
+    "printPredicateOperand": {
+      "apply_type": "OLD",
+      "old_hash": "3932565457d2a4af42da2ab2d7447d855aac9764df70370d9cd1878f8382e9c3",
+      "new_hash": "5b19fb63c4e2ac199d61b4c3330df297566142adcce15a7f2e50caad22e33ac8",
+      "edit": ""
+    },
+    "printRegImmShift": {
+      "apply_type": "OLD",
+      "old_hash": "5f0717b8c6b8adf379dc0fce2f7ebae5a90403ca92a446f6574334304e5b3442",
+      "new_hash": "70f7f28dda0dac5e056d6020610064c1690ab444185131a825bc8d8952f82286",
+      "edit": ""
+    },
+    "printRegName": {
+      "apply_type": "OLD",
+      "old_hash": "c1eb60a0d7d33b057623433b82571a760df70ad3154db7b0b19946d35089f1b2",
+      "new_hash": "76093e8d5ef4e71ae65ad578dadfb11aae8344a58ea6d7a8b3c745707ef9e6e2",
+      "edit": ""
+    },
+    "printRotImmOperand": {
+      "apply_type": "OLD",
+      "old_hash": "449126f378f30164371e523d6eaba8d5459456ce4db01b32b01a83a263a541dd",
+      "new_hash": "0aece7379e3e2437fe6ac740d551bf1ceea0c3dc8a0bebf0ffab0d657057adf8",
+      "edit": ""
+    },
+    "printSORegImmOperand": {
+      "apply_type": "OLD",
+      "old_hash": "a1fe068c5ceba67576ab8258cc219873407977d389a13013b4667acbf5f98961",
+      "new_hash": "ee6be5af2d248114795e4aa984aff8f7d84d9b458dc64a4365ee49565f12bea9",
+      "edit": ""
+    },
+    "printShiftImmOperand": {
+      "apply_type": "OLD",
+      "old_hash": "7f1299f202c7103edbe37fa729326c7da3c76b98d000d7b3adc5245bd72ba955",
+      "new_hash": "5ac17ae57aefe4888c045a8959afe9ad3cfbc1b6a451962551a9cadd4522f024",
+      "edit": ""
+    },
+    "printT2AddrModeImm0_1020s4Operand": {
+      "apply_type": "OLD",
+      "old_hash": "b20a6c57a7acdbf382d69329f956b48f7728189bf1a9ff25b109ae59b2efaf44",
+      "new_hash": "375142b95895fa4e40df63f164ba24d5f7b45466779ce08d7324eb97d47636d8",
+      "edit": ""
+    },
+    "printT2AddrModeImm8OffsetOperand": {
+      "apply_type": "OLD",
+      "old_hash": "57b6bebfa994d0e9154b232a5fa13283bb37f070ec0f12f24cc5c22510f35500",
+      "new_hash": "4ffba0d957ef4da97aed16b02e59e68252d56028a64759c37d199076a356823b",
+      "edit": ""
+    },
+    "printT2AddrModeImm8s4OffsetOperand": {
+      "apply_type": "OLD",
+      "old_hash": "f2069b50e98d4faf11b5200b418abac998deda28baf95f0be081a8e8449b4528",
+      "new_hash": "8e5a320189ab6ea0220f3ccfa4c0aef459fd7f1e28ed8fab1f92f80131d09f66",
+      "edit": ""
+    },
+    "printT2AddrModeSoRegOperand": {
+      "apply_type": "OLD",
+      "old_hash": "372d09aa8ca5127a899bf03bf87031b50705fa61678a32411edb9712e513275b",
+      "new_hash": "7dcfd09bf690d4b9047c31ea82e4663bb487d90088cd3d21cd800594c3e2ede3",
+      "edit": ""
+    },
+    "printT2SOOperand": {
+      "apply_type": "OLD",
+      "old_hash": "cacb7922056310358a81fd5de43f9841dc11d08e934d03c103216e914e97d494",
+      "new_hash": "281ee4c32e2a20a895429462b150ae3a96367137dd7c4e059fe8d5c7c99858df",
+      "edit": ""
+    },
+    "printThumbAddrModeImm5S1Operand": {
+      "apply_type": "OLD",
+      "old_hash": "4a2e4e03452e1916fa2ec0aa0c9db3041c675e681d3e349b5d0436eeb3a3849d",
+      "new_hash": "1269c0298774c8eb4ce5a6c0a27dc5a80c323c3f6e70b7c9faabf575ef1a9249",
+      "edit": ""
+    },
+    "printThumbAddrModeImm5S2Operand": {
+      "apply_type": "OLD",
+      "old_hash": "c1828a2e08a01240583f68c9d59bde99ca4555d65490dc547029cae94299a83a",
+      "new_hash": "517873dc4755e3bc6d7ce50a80bd716e03fef549b344295ad908bc84e6101c41",
+      "edit": ""
+    },
+    "printThumbAddrModeImm5S4Operand": {
+      "apply_type": "OLD",
+      "old_hash": "196c943ec78b1aad2ad8377c1ed245074f8d0c4cb2f875a5ed5a83a9b2b60bb2",
+      "new_hash": "083d4bdec37438584a608c2daeea1fa1589bd3de77f156bce608007aad0e2d16",
+      "edit": ""
+    },
+    "printThumbAddrModeImm5SOperand": {
+      "apply_type": "OLD",
+      "old_hash": "91b395438f499de10e6f7f9ba38fda923813576a0a206124f782ae80b8ef0b05",
+      "new_hash": "aeece3e380bcec4560cae7de6f35aa37093a9664980c80d30ca4f5f054163351",
+      "edit": ""
+    },
+    "printThumbAddrModeRROperand": {
+      "apply_type": "OLD",
+      "old_hash": "f05d41333a6d52cc0cd93521f3d86224bf08173e1b59ec1680b77cfbc48bb1ee",
+      "new_hash": "b37f7e16714aacade4e87b8a472f4a99de32d975e4e4e715f36415319008ef15",
+      "edit": ""
+    },
+    "printThumbAddrModeSPOperand": {
+      "apply_type": "OLD",
+      "old_hash": "6396900cc18ff022f337ea572ae44f924a42c63f584abe6ff49c4a726749da4b",
+      "new_hash": "82705b397763b51819a79f609e5c58f8ff8d0995ae0c6d1e402a5d4bd3e79fcd",
+      "edit": ""
+    },
+    "printThumbITMask": {
+      "apply_type": "OLD",
+      "old_hash": "fbf9c241234cee08381e20204ed20b51e46781b78ba5a2feb8c680901ae8d86a",
+      "new_hash": "d840be6fb149b94819dfcadb91d686e4b2b5b6d1a56ff0ef427e2824a0e8ffb0",
+      "edit": ""
+    },
+    "printThumbLdrLabelOperand": {
+      "apply_type": "OLD",
+      "old_hash": "efb84da0302610393d6a7e5391241239b647a5b4c82668326d0e9a47a47a18bb",
+      "new_hash": "6c0914fc07a5d286d912e8ec53ca5c13f7b1330deefd26c900bc4f5047be5ceb",
+      "edit": ""
+    },
+    "printThumbS4ImmOperand": {
+      "apply_type": "OLD",
+      "old_hash": "a054fa53c071d5adda4eaba8d6f58a6bc3b155347b2bad91436ad9934fab6168",
+      "new_hash": "053e98d9c3cba58ddf877ec26dbc34490dc95ea615749226098a5758daa7f261",
+      "edit": ""
+    },
+    "printThumbSRImm": {
+      "apply_type": "OLD",
+      "old_hash": "a4e8c585111cfca9eb24e81f14e27ae0a5d9332393409760ee53f167e97dc3e3",
+      "new_hash": "1e33c1fe19fea806cb8c76fef4532afc3c8df6a76f42e340cea2be9109bcce25",
+      "edit": ""
+    },
+    "printVMOVModImmOperand": {
+      "apply_type": "OLD",
+      "old_hash": "3a12f73636ba9a968615b9ac0da5e66b1abc84170c125bb726f6af923be610ee",
+      "new_hash": "a91d176beaa643dc5bae5210b55bf9d00a01ce000b9bda69e613a927846c5081",
+      "edit": ""
+    },
+    "printVPTMask": {
+      "apply_type": "OLD",
+      "old_hash": "3ac3e6830271fad2e5b3099916a92aa352c3f411fedf56fa5a2ee3fc8cad44f5",
+      "new_hash": "f30385dde558c3b5a6335cd8647e1c7c769e43e764198d342ebe01a5005ce2fb",
+      "edit": ""
+    },
+    "printVPTPredicateOperand": {
+      "apply_type": "OLD",
+      "old_hash": "3e4359bfa82a70e102217ff7ce1d02b633c1a9d2d2d92752debc7992c021ae56",
+      "new_hash": "ca714c322ed9bfffaed6715fceea4bf29a757df4e58d9aa78be4bcf88e8197a7",
+      "edit": ""
+    },
+    "printVectorIndex": {
+      "apply_type": "OLD",
+      "old_hash": "9d1a0fd44c688be5cbdd38ad6c62b469a986bd8a09fff9efe69072a143fb68f8",
+      "new_hash": "26c0129a9fa8ec3a0ad10b96a75b06a09690addbaab8d7553308c676c4ab332d",
+      "edit": ""
+    },
+    "translateShiftImm": {
+      "apply_type": "OLD",
+      "old_hash": "e2d84d0521152490aae8ba013d5d06a3bec5fdf1b85dae03a7dab85a37c1486b",
+      "new_hash": "80629627e546f6a8623e75f101abd4c645a020a308c756b4e5393b7d033686aa",
+      "edit": ""
+    }
+  },
+  "ARMInstPrinter.h": {
+    "\"ARMMapping.h\"": {
+      "apply_type": "OLD",
+      "old_hash": "",
+      "new_hash": "7e136c6321358f6fb1f52dc60972a530c1acd41ce85722ce17e009532d007439",
+      "edit": ""
+    },
+    "DEFINE_printAdrLabelOperandAddr": {
+      "apply_type": "OLD",
+      "old_hash": "4c0cb0fd1dc5de3c1f633ae4d96decb51223124bbc2638016f4d253221fc9b95",
+      "new_hash": "",
+      "edit": ""
+    }
+  },
+  "ARMAddressingModes.h": {
+    "ARM_AM_decodeVMOVModImm": {
+      "apply_type": "OLD",
+      "old_hash": "f2bd9aa4139457459f6f8af0a9e2071bd7ebe3d33436ef2b733cd083b386ab18",
+      "new_hash": "7c6060fb6a0a3d22dfc65177be0ccb50e270c775d19c6082ffceb25eeed6c638",
+      "edit": ""
+    },
+    "ARM_AM_getAM2Op": {
+      "apply_type": "OLD",
+      "old_hash": "8eacd33cf973cd4c388a67967d0ccb1571c1f5acd7a96b01c21a7c9d22b1b3e3",
+      "new_hash": "9170286ed54ad2096bece239299246e09e2d1c4c0207d9bf67045c3c2e6760b0",
+      "edit": ""
+    },
+    "ARM_AM_getAM2Opc": {
+      "apply_type": "OLD",
+      "old_hash": "719e806a9604b17f261317b4fb62fa0f4c1d94a4fc9dc30454679048ab416c1b",
+      "new_hash": "07459ce041a74256bdcf89218f9bd9cfb642adc9c8719e9214f9c46e59cec4c1",
+      "edit": ""
+    },
+    "ARM_AM_getAM2ShiftOpc": {
+      "apply_type": "OLD",
+      "old_hash": "c8948f4fcc5c119e386121c1001a9054fed8defbee9061cd72f2ba0365d5979d",
+      "new_hash": "65b0f515e542d325a16a79bfbcca1879f34d116bd36ee72210b399e875a9e804",
+      "edit": ""
+    },
+    "ARM_AM_getAM3Op": {
+      "apply_type": "OLD",
+      "old_hash": "313f8eef19d721a770f3d18494d35101a59c102aa226ee8ecb0c7e2a2ad8b59e",
+      "new_hash": "30bd50d0368d2d9a87dfc7649d5e55855efdd0e1c6f153e4d1cb4ffb88cfee4b",
+      "edit": ""
+    },
+    "ARM_AM_getAM3Opc": {
+      "apply_type": "OLD",
+      "old_hash": "d0da97672b47a209c135b81accb75758bf12741684c378e9f85fe3fd6ea27260",
+      "new_hash": "ac68c111a3ade97bf36fc35a13f99aab6c52781d75cbfd59f216e4b84adafd9a",
+      "edit": ""
+    },
+    "ARM_AM_getAM4ModeImm": {
+      "apply_type": "OLD",
+      "old_hash": "39dd93dc2516d2babe9cf9b1b22c6d6358e0887ac691d3a8210c7def682c1d99",
+      "new_hash": "057f0b69b8885126db65609d61d7861e745f70678fc0b4cdd547517cf3781bf9",
+      "edit": ""
+    },
+    "ARM_AM_getAM4SubMode": {
+      "apply_type": "OLD",
+      "old_hash": "8e23306f176900bf3b9ce26172465532d65485eeb57757b32323fd76a72b157c",
+      "new_hash": "8ae0289c976949aab7de97549fb8655e285e3dd8f39b5b0077fbeacfc1ddd6cb",
+      "edit": ""
+    },
+    "ARM_AM_getAM5FP16Op": {
+      "apply_type": "OLD",
+      "old_hash": "cfa02ca36fbe0391ea693aaf88673e0808d025312e887dbedfefec315fc09090",
+      "new_hash": "1200c63f8b75d7dd7088822ed94f2c30449655fce6e5043433ed9694b7c5752d",
+      "edit": ""
+    },
+    "ARM_AM_getAM5FP16Opc": {
+      "apply_type": "OLD",
+      "old_hash": "e9c1391774fa221b13ce72e42bf3752f445f36ebd00bcede91133634834bbd54",
+      "new_hash": "1cfbde6a8ae285af27337b536b83521fc8ecd6cec0ccbd3e93e4e5811fbbb804",
+      "edit": ""
+    },
+    "ARM_AM_getAM5Op": {
+      "apply_type": "OLD",
+      "old_hash": "8cb5b71316ea64e4d1397cc83b338ffdf03db131e8800f4a28c1453b04da6354",
+      "new_hash": "147ac382e3d1542f09f972885ee58c519b1df96ce0c8bdc6448f070a08963d68",
+      "edit": ""
+    },
+    "ARM_AM_getAM5Opc": {
+      "apply_type": "OLD",
+      "old_hash": "8387c3a7eba8fda8f0fa30a24374f85ced2d0f74e3370331178a310d6161411d",
+      "new_hash": "096cfd20c543e9c5d47a76bad44ab0fea7c1770f56fe2722e49aec1f820e12ad",
+      "edit": ""
+    },
+    "ARM_AM_getAMSubModeStr": {
+      "apply_type": "OLD",
+      "old_hash": "ce74d91930ae0836a39773acc93f9d9af3d176fb386c03045fdce659ddafc93a",
+      "new_hash": "2e559b4426dcacb7193a54663ba3e5fe0a9bb460e69538d19862c8e80c14a8c5",
+      "edit": ""
+    },
+    "ARM_AM_getAddrOpcStr": {
+      "apply_type": "OLD",
+      "old_hash": "874cd615fbae834cb493ec7e6c12497df8f71144d1d5f73863e24b2688a86a06",
+      "new_hash": "43f7343aed1cdd5e7d91231393e2298bafc9985ab1171603da4dab017231e3e4",
+      "edit": ""
+    },
+    "ARM_AM_getFPImmFloat": {
+      "apply_type": "OLD",
+      "old_hash": "b701b7192bbf232f992fb75f6b025609b6243881c56decaf3a3ec789e26b75c1",
+      "new_hash": "2c1787344950c82894a99240d9214aabab60924844b1c2eef4938c7ec0019e16",
+      "edit": ""
+    },
+    "ARM_AM_getSOImmTwoPartFirst": {
+      "apply_type": "OLD",
+      "old_hash": "dc859c73453011a9165e6511738df1809f61d9939cb0e98097cab241d307ad68",
+      "new_hash": "c802023d1ef9d46ca4bbbea0375bfa8562af77c7f7b2909be34fa21fa700ec84",
+      "edit": ""
+    },
+    "ARM_AM_getSOImmTwoPartSecond": {
+      "apply_type": "OLD",
+      "old_hash": "2a4827167b657ea2b42aad88488e0d8c6e1c8eb76c92b26556e511244220ade0",
+      "new_hash": "aad56b0d0657f31d9992be135511bfcc455516b2e56924da7290a29896ce5220",
+      "edit": ""
+    },
+    "ARM_AM_getSOImmVal": {
+      "apply_type": "OLD",
+      "old_hash": "43428220c58b44e2c989b3cc8c0f13cacda3bf53a49276ee6953db163a2c453b",
+      "new_hash": "c5c5f016caa0c517a9a3dc42f0813dd9785612aa8712d63a8da570b7918f1aef",
+      "edit": ""
+    },
+    "ARM_AM_getSOImmValRotate": {
+      "apply_type": "OLD",
+      "old_hash": "9ca6e82eb086794a2de472eb222b63a8e6c1870a19ce40b52b8aa5ccecff6c2f",
+      "new_hash": "c3bfbdecc23ed56fe3a2df7237a0597abf67f730d9723d97ff7a6580fdac5875",
+      "edit": ""
+    },
+    "ARM_AM_getSORegOpc": {
+      "apply_type": "OLD",
+      "old_hash": "86f5d2f46956379d3bcd34a438f4e3c0b5ae9220e21d029ddc073577cbf58427",
+      "new_hash": "4a31bcbc12e3920187297ef75306c1504548c87fb703223bb2de59aece89a109",
+      "edit": ""
+    },
+    "ARM_AM_getSORegShOp": {
+      "apply_type": "OLD",
+      "old_hash": "1a394d97f642a946279b28f8e7f12e5dd567c5a6d09ec02da795bc42960a5a87",
+      "new_hash": "221f5b7b8f4633174f8f9b856fa71dbe9c1929320c30c505d02926c5a8a1fe0e",
+      "edit": ""
+    },
+    "ARM_AM_getShiftOpcEncoding": {
+      "apply_type": "OLD",
+      "old_hash": "111fc0a3953dcf8e371a38bf178569b5e4b68e34e3b902a6b16cfbbc29e240a3",
+      "new_hash": "aa29dc3a4d73dbba90ce12de56d1fbc8eb78b9b124cd1b2e6f4fbddcb156e404",
+      "edit": ""
+    },
+    "ARM_AM_getShiftOpcStr": {
+      "apply_type": "OLD",
+      "old_hash": "feba37bca7fc4dedcc0727e4c0f0f46e01c0dc005589d3a60e8fbbf918d31485",
+      "new_hash": "164aee3544ec40e08408e599f8c287e7755e2e26de333d78f07b803fb4a8282a",
+      "edit": ""
+    },
+    "ARM_AM_getT2SOImmTwoPartFirst": {
+      "apply_type": "OLD",
+      "old_hash": "aee14080be9d38f4f68ab997b5e147e064200553e46e4c7fd1813bbfa7e10393",
+      "new_hash": "35c3f4bcd0a4170c4f6f870cf7e1e964093aa208e29896f79cc136edbfb89677",
+      "edit": ""
+    },
+    "ARM_AM_getT2SOImmTwoPartSecond": {
+      "apply_type": "OLD",
+      "old_hash": "28f2af7ddacdf2b78e988b62fe5008a9f40ce64a06303022f126c5a146dc178d",
+      "new_hash": "da03c0d957937e69d618bea142f5615e911650b8df0d82e9ec58bd6572efffcc",
+      "edit": ""
+    },
+    "ARM_AM_getT2SOImmValRotate": {
+      "apply_type": "OLD",
+      "old_hash": "7d5e9489c3ef1a80f452f4b6bd8b290c853a7e10a34fab6d891988d7cf0c8df8",
+      "new_hash": "302c68a414d6e3dd25c3b9929b55ad810ad02aa152b20d71ee92d22b509bf13a",
+      "edit": ""
+    },
+    "ARM_AM_getT2SOImmValRotateVal": {
+      "apply_type": "OLD",
+      "old_hash": "0337cedbb80a2b5904b1053061c8140de508c081923074f996624f1fef3a817f",
+      "new_hash": "94ebe6ed65d73047d4700a1c534b6a271ee79840f676539e7cf82cacb420ee65",
+      "edit": ""
+    },
+    "ARM_AM_getThumbImm16ValShift": {
+      "apply_type": "OLD",
+      "old_hash": "cb2d3b9c433f847b3c5a45439aad7c917af46fbaa34d738663cab1e96bbb88e4",
+      "new_hash": "9fd586516e4e5eaebbe2c5d055dfa24ac68cf28201d3167e4f97019a48daa599",
+      "edit": ""
+    },
+    "ARM_AM_getThumbImmNonShiftedVal": {
+      "apply_type": "OLD",
+      "old_hash": "3822416499583204306abfa37f6af89e8e00e0f492c29aca032335238d134fd7",
+      "new_hash": "41e3c78bc92aad095de33b88c1a9400997804d2ad69344184f701b264fdbaa00",
+      "edit": ""
+    },
+    "ARM_AM_getThumbImmValShift": {
+      "apply_type": "OLD",
+      "old_hash": "64e51398dde6bdb03c645425557944517740dad87f7f3acd3a132529a6d88f5c",
+      "new_hash": "1ce0908b4762fbec214b1f2e2ba8beaf4e955ae6ca03a027743057ed784ed493",
+      "edit": ""
+    },
+    "ARM_AM_isNEONi16splat": {
+      "apply_type": "OLD",
+      "old_hash": "a0938026315cc63cb531a85471e6d45f58eb50a4058a622c25472f453b2b8619",
+      "new_hash": "2a3a64ccb9a6155cfe4e5a9ad67ee16f1d5dd45f1cd3b1564600c1b28c0d6c01",
+      "edit": ""
+    },
+    "ARM_AM_isNEONi32splat": {
+      "apply_type": "OLD",
+      "old_hash": "e82588ad097f60ed35e179264ba1e3e7644ea64a7162622f944692bd9adab37e",
+      "new_hash": "9bef85dfdb0e7f6309eaac91a55697d410a950abe7e8e24098b64c4faca89f33",
+      "edit": ""
+    },
+    "ARM_AM_isSOImmTwoPartVal": {
+      "apply_type": "OLD",
+      "old_hash": "8239a5ed54d74daa8eb26ee113f07c2de10b04e50c13a2b982a8b11fd675ea66",
+      "new_hash": "e4efd3dc86afa01f2162f8a98674ce030ee858115eef03db80c0e6da8dc16d22",
+      "edit": ""
+    },
+    "ARM_AM_isSOImmTwoPartValNeg": {
+      "apply_type": "OLD",
+      "old_hash": "caa5671e598be177e85348dc91e7750ba7b04655689c17a9351a298b6a23a34e",
+      "new_hash": "c115e1fa5b5b73f76400f2ea1c6248118827ed2563cc1ef6076fd94d966b260a",
+      "edit": ""
+    },
+    "ARM_AM_isT2SOImmTwoPartVal": {
+      "apply_type": "OLD",
+      "old_hash": "6cb24668a4e3d4946703eb15695547429008f5a85e9dcc7b909684cdc29e6913",
+      "new_hash": "8ee0f1bc2d8bf511fcf2fc334511627e4e86d7b78ac6239dd4b01de387b7d868",
+      "edit": ""
+    },
+    "ARM_AM_isThumbImm16ShiftedVal": {
+      "apply_type": "OLD",
+      "old_hash": "465b428de9df7274b97fe809f14d9daaf182980700aa88178a021716848215cb",
+      "new_hash": "d56f0a8e4dd0f7105405ab3543784572b669abbd542b40f9b1fae0dc05fccd9b",
+      "edit": ""
+    },
+    "ARM_AM_isThumbImmShiftedVal": {
+      "apply_type": "OLD",
+      "old_hash": "cf9a79c66fbc0cdc23188e8fae364995e78bbbb80e7f232c02c9e706b806e059",
+      "new_hash": "a79c7bfcab2471647f1a471f6cfaa8456050c67144b53477ea5b90a3e1d9c590",
+      "edit": ""
+    },
+    "ARM_AM_rotl32": {
+      "apply_type": "OLD",
+      "old_hash": "48f2d2746fd487352496dda41f6353c90dcb8f560938e6af61f803b258c88971",
+      "new_hash": "",
+      "edit": ""
+    },
+    "ARM_AM_rotr32": {
+      "apply_type": "OLD",
+      "old_hash": "26357e0793c8a388525a7e4fcb5d8b245f02f94cf7574de23b1324f5567c8bef",
+      "new_hash": "",
+      "edit": ""
+    }
+  },
+  "ARMBaseInfo.c": {
+    "\"ARMGenSystemRegister.inc\"": {
+      "apply_type": "OLD",
+      "old_hash": "a8f353bf160930fb2246d51af19e660f51c206e2d1eab2870332338b0f744c32",
+      "new_hash": "",
+      "edit": ""
+    },
+    "\"ARMMapping.h\"": {
+      "apply_type": "OLD",
+      "old_hash": "7e136c6321358f6fb1f52dc60972a530c1acd41ce85722ce17e009532d007439",
+      "new_hash": "",
+      "edit": ""
+    },
+    "ARMSysReg_lookupMClassSysRegAPSRNonDeprecated": {
+      "apply_type": "OLD",
+      "old_hash": "91202d18d7abc1b3c9d2a94e5824256cf8e0d021346f04cb22586b3f5bcef9a3",
+      "new_hash": "46a413e3efb1147c7f53e9bfca46a008b1e674743af943a919aa9da3a621a24e",
+      "edit": ""
+    },
+    "ARMSysReg_lookupMClassSysRegBy12bitSYSmValue": {
+      "apply_type": "OLD",
+      "old_hash": "a0fcb310f3825ebb0f271a497e85ee5901b1f194fa82413bb07063aa37e8045c",
+      "new_hash": "faa313843f323f690e2b7d068f4c73ddfd02a855c6929b974cfe5619ac5bf77f",
+      "edit": ""
+    },
+    "ARMSysReg_lookupMClassSysRegBy8bitSYSmValue": {
+      "apply_type": "OLD",
+      "old_hash": "cca0521b90363af593700ae24af1bda4e62c87f9b5a8f7b046837cf19dd8f4f6",
+      "new_hash": "039f71e35e9dff93dc1281ecac746296b59b2d060322cc5d7f6c7769745e8751",
+      "edit": ""
+    },
+    "expandPredBlockMask": {
+      "apply_type": "OLD",
+      "old_hash": "",
+      "new_hash": "9d4583a739027b735bb212ad8c93184e8ffa74f7581994ec5a4bf8574be0d4ee",
+      "edit": ""
+    },
+    "get_pred_mask": {
+      "apply_type": "OLD",
+      "old_hash": "2df9f0a4b700c0018e11b43f128edf5e56ca51994895f573ba372657f1b42ac3",
+      "new_hash": "",
+      "edit": ""
+    }
+  },
+  "PPCDisassembler.c": {
+    "DEFINE_decodeSImmOperand": {
+      "apply_type": "OLD",
+      "old_hash": "895a10bd0a661672b26b8d30b1e2674d0ddba7edebf44d9b7c6fe79141aacfd2",
+      "new_hash": "935407b09926874e1608901373c2bdf6ff1747972a83ce26f67d50dcb970e997",
+      "edit": ""
+    },
+    "DEFINE_decodeUImmOperand": {
+      "apply_type": "OLD",
+      "old_hash": "9fe7a12ce22509a76a8ee2137d8fcd6d0c34a04b6bf0233fb065e3c9ee52afaa",
+      "new_hash": "f3aed7c3c5b5dba3fedb5e859f6f10b28b71a112388efb975647dcd26975b5ee",
+      "edit": ""
+    },
+    "DecodeFpRCRegisterClass": {
+      "apply_type": "OLD",
+      "old_hash": "",
+      "new_hash": "37d5c95babff4cdbb0d06edd5e6f1ba016ba85269c4bc85705a452aa0d447429",
+      "edit": ""
+    },
+    "DecodeQFRCRegisterClass": {
+      "apply_type": "OLD",
+      "old_hash": "e74d70b3ada80d08a9fcf4955f35e8b121fde81f48b833f6c2ce99af45ea5348",
+      "new_hash": "",
+      "edit": ""
+    },
+    "PPC_LLVM_getInstruction": {
+      "apply_type": "OLD",
+      "old_hash": "631c72acfb15f6e02cf364113002dc716fe7a58abfafeeb0770904db254a9707",
+      "new_hash": "",
+      "edit": ""
+    },
+    "createPPCDisassembler": {
+      "apply_type": "OLD",
+      "old_hash": "",
+      "new_hash": "2ae1fe9fd435afc31a3abf84fa2de4a89d312ba76553e7fc389323947fcd2de9",
+      "edit": ""
+    },
+    "createPPCLEDisassembler": {
+      "apply_type": "OLD",
+      "old_hash": "",
+      "new_hash": "d33eda9c5bea015d3f34f8225fa7180f7328c1384a0ac0d3cfdd85c606c4e800",
+      "edit": ""
+    },
+    "decodeCRBitMOperand": {
+      "apply_type": "OLD",
+      "old_hash": "fb18241cd88deb19fbe3f4376a6d48f072342793ab3db2dd3fc727a9ef4b4aa9",
+      "new_hash": "7c74af36ff0b1822e4f495be05a034aa5bb1f8415cedfa0eb2d673edff2eb593",
+      "edit": ""
+    },
+    "decodeCondBrTarget": {
+      "apply_type": "OLD",
+      "old_hash": "ea9e32f678a855e1d192e49f0f98c6ab634a03e7527a72bd604f5df888f16f55",
+      "new_hash": "94fd8dbfbb0cb0fcd90e0efddac51f17ca56ef5140486db9a6c8accee4a539d1",
+      "edit": ""
+    },
+    "decodeDirectBrTarget": {
+      "apply_type": "OLD",
+      "old_hash": "bf49afc5f8e9131ae1a4852c330bb5214b0fb96218dc90a348aade8dc702044e",
+      "new_hash": "b47373f0a20d809a0aa38ba059045b33ff88c8338dfe72cbcd3c14b599abbf9a",
+      "edit": ""
+    },
+    "decodeDispRIHashOperand": {
+      "apply_type": "OLD",
+      "old_hash": "",
+      "new_hash": "1b34b98bab88ce771f50ae9f966ef78bb389eb6b281266597e9cbffc6a908cb0",
+      "edit": ""
+    },
+    "decodeDispRIX16Operand": {
+      "apply_type": "OLD",
+      "old_hash": "",
+      "new_hash": "1f2dc28c5f981f7ac9212932f00a18a09e382bef532376bb9db4ae6382408d68",
+      "edit": ""
+    },
+    "decodeDispRIXOperand": {
+      "apply_type": "OLD",
+      "old_hash": "",
+      "new_hash": "d185c48343d6ad885a7c40927ffc4e4f36899ca97dce00886e3117c0eaeeef65",
+      "edit": ""
+    },
+    "decodeDispSPE2Operand": {
+      "apply_type": "OLD",
+      "old_hash": "",
+      "new_hash": "c0e01d088225db6729f5bb24bdb62ddd73899cce78ceb984d7dc879682509202",
+      "edit": ""
+    },
+    "decodeDispSPE4Operand": {
+      "apply_type": "OLD",
+      "old_hash": "",
+      "new_hash": "5d757df8ba53c9ba8568fdc8fedc8cfbfddfdca8806fa8ea900f9137386fa05f",
+      "edit": ""
+    },
+    "decodeDispSPE8Operand": {
+      "apply_type": "OLD",
+      "old_hash": "",
+      "new_hash": "e90312c2af9fc2efe1b7574ea405bba70e211083f93c6be73445aa7177de7fa2",
+      "edit": ""
+    },
+    "decodeImmZeroOperand": {
+      "apply_type": "OLD",
+      "old_hash": "dc7192c8dcca845a50fd1a775df9a79a883c4eea71f20e5042457d15b2936799",
+      "new_hash": "a1d6b9c56142dfbedd08f0c73862248d1fc5924032cafe131979e3b774c6117d",
+      "edit": ""
+    },
+    "decodeMemRI34Operands": {
+      "apply_type": "OLD",
+      "old_hash": "effea0efbf97b8d4b039d52b3b30e883cf88acf25503026853925c9e09ba57f5",
+      "new_hash": "",
+      "edit": ""
+    },
+    "decodeMemRI34PCRelOperands": {
+      "apply_type": "OLD",
+      "old_hash": "191f7e082fe3fffb28957b3a0eff5682ff4476e8977ca4aa2699adc280ea6f9f",
+      "new_hash": "",
+      "edit": ""
+    },
+    "decodeMemRIHashOperands": {
+      "apply_type": "OLD",
+      "old_hash": "b905a8557bbc5385950d74035e77c858fb5c1af03c10d752768fbfe71d944095",
+      "new_hash": "",
+      "edit": ""
+    },
+    "decodeMemRIOperands": {
+      "apply_type": "OLD",
+      "old_hash": "4c7e8eddca16ab5048e12c82347534d5e08271adbb0acc1ed2ac1c391cbeec4b",
+      "new_hash": "",
+      "edit": ""
+    },
+    "decodeMemRIX16Operands": {
+      "apply_type": "OLD",
+      "old_hash": "a7e0eea11e3e73a38957a633fbb4c8bf2a3b1aadf10a2646064803a95093f0ef",
+      "new_hash": "",
+      "edit": ""
+    },
+    "decodeMemRIXOperands": {
+      "apply_type": "OLD",
+      "old_hash": "24e7c72ebcf794efd16d38c9f37102f7fd892ec5a7ff1e456ba096e2728c083b",
+      "new_hash": "",
+      "edit": ""
+    },
+    "decodeRegisterClass": {
+      "apply_type": "OLD",
+      "old_hash": "35e25f6cc24d1a13cb7235a901496bebf7a1f9d082282495bb56de652a2ef1f3",
+      "new_hash": "c4ae91d25883a1d6d95c647fb2bbbf9d01781689c1a3c4488badb9245ffc2317",
+      "edit": ""
+    },
+    "decodeSPE2Operands": {
+      "apply_type": "OLD",
+      "old_hash": "126fcb6277e4a2fc967e74990ebfdfe3ab83adf1a58a3290e5fdf17085a3c8b2",
+      "new_hash": "",
+      "edit": ""
+    },
+    "decodeSPE4Operands": {
+      "apply_type": "OLD",
+      "old_hash": "fd80f242361764a6dc69b7a612b68edfe6ded7714b5d32727c7181d6dc5e5b2c",
+      "new_hash": "",
+      "edit": ""
+    },
+    "decodeSPE8Operands": {
+      "apply_type": "OLD",
+      "old_hash": "58d0b69eb70dbc98d21c0ae8025b4e3f176be9119c7848fe536be3dcef0d86c2",
+      "new_hash": "",
+      "edit": ""
+    },
+    "getInstruction": {
+      "apply_type": "OLD",
+      "old_hash": "bf6afd23ac43a419c4fe562edaaf08373b831b96e4318b7e281f5c7ca132a598",
+      "new_hash": "6124d5bd062f28f910fa50b1d63e8a45b8dde3065a59da859237d97742f4dbfe",
+      "edit": ""
+    }
+  },
+  "PPCInstPrinter.c": {
+    "\"../../Mapping.h\"": {
+      "apply_type": "OLD",
+      "old_hash": "204ac68dcb32024c325b99a0843719c321ab57c60c41b12adbea497c20b7d436",
+      "new_hash": "",
+      "edit": ""
+    },
+    "PPC_LLVM_getRegisterName": {
+      "apply_type": "OLD",
+      "old_hash": "83384bb6920ca435750803566108eff77442720a35423c0f5b6bfebca4466b5f",
+      "new_hash": "",
+      "edit": ""
+    },
+    "PPC_LLVM_printInst": {
+      "apply_type": "OLD",
+      "old_hash": "bc6df651b2a5f3810df3f9b77c29ac7f9e92013d4cbc3f3187b3ea6e237a1ae6",
+      "new_hash": "",
+      "edit": ""
+    },
+    "getVerboseConditionRegName": {
+      "apply_type": "OLD",
+      "old_hash": "c014e2d8b222be07d6fb574a3d9b2c0bd5f7084044a3bad372980efd5931e9d7",
+      "new_hash": "7686715daa951f40105c858a2a6962d56a255bfd3919ae995f3136e40d50358b",
+      "edit": ""
+    },
+    "printAbsBranchOperand": {
+      "apply_type": "OLD",
+      "old_hash": "1157d42eb9a1920fb0b6a448fda5168a217c706732869b9b1bdb4ae9aecf8495",
+      "new_hash": "d04a7678c4c21e3df33cc039143fb700f9416932ac11a18c95ed40ba8ea08841",
+      "edit": ""
+    },
+    "printBranchOperand": {
+      "apply_type": "OLD",
+      "old_hash": "c20e1c20fae0bcf418c30c3a06302936e823bb04ee8060d84715d7dd9a460810",
+      "new_hash": "dbd988ddfe9f9e9bfaf86d57347950c0b7cbac68625e8a67e4e5b38369f0136f",
+      "edit": ""
+    },
+    "printImmZeroOperand": {
+      "apply_type": "OLD",
+      "old_hash": "cbacd7e6f47c813e31eeb35797001aff4fc5e5491c51bd8359dfd9bc082df986",
+      "new_hash": "46036217bb3043cf754e707dd98e37e7d2c62fe08bd8a75456e6232e68a9a0f0",
+      "edit": ""
+    },
+    "printInst": {
+      "apply_type": "OLD",
+      "old_hash": "3f3f6e26181e91a6a98bc893a05404413797db9b7ddf3e77ea5b6c7cb1760919",
+      "new_hash": "576c2e923095863e98ea4255f512049421dc7d10b42459904f03a480c9c724f9",
+      "edit": ""
+    },
+    "printMemRegImm": {
+      "apply_type": "OLD",
+      "old_hash": "6154062a675a628b76a2b597c1ae9736a847979d193f1bfaa3eba0451d948268",
+      "new_hash": "4aafa39c3f666d0c4399738b3c6ae26eea315e76a66d4e469f95b118b68f8c30",
+      "edit": ""
+    },
+    "printMemRegImm34": {
+      "apply_type": "OLD",
+      "old_hash": "acbb291f1ce2460c87f65c91a6feec097552f881aebfdb92b68ffdaf2d5fc17f",
+      "new_hash": "8d2c17803c40c03176c0edcc73bcd27811d9d6ac2cad82fd52595e5c6ec64725",
+      "edit": ""
+    },
+    "printMemRegImm34PCRel": {
+      "apply_type": "OLD",
+      "old_hash": "bf6d163a150ec63552e6605a24114f205145bb62b8fb5a5bc840eecaf1ddd57f",
+      "new_hash": "19db96e5505fb3d5f7ca7bbd759d8bf0b8d246ddbf9dd61dc6371ff8aaa9a7aa",
+      "edit": ""
+    },
+    "printMemRegImmHash": {
+      "apply_type": "OLD",
+      "old_hash": "64166ed92b08a9de7a502289f22e14b25c163d9b479ae2d989e1b5c63c911e13",
+      "new_hash": "f0c950be663103fce9dfc95fde04586f88a471c0cebb4195cb25373978c176bc",
+      "edit": ""
+    },
+    "printMemRegImmPS": {
+      "apply_type": "OLD",
+      "old_hash": "8ce3e5a6e3b2b79046d7dfaaf9b5d5084f06116ca83fc8352b1e4483266ac636",
+      "new_hash": "",
+      "edit": ""
+    },
+    "printMemRegReg": {
+      "apply_type": "OLD",
+      "old_hash": "6e9453d0abd21a9e7b54da5e5115b50ebd56a4757d28bdb4066a37d74527c5bf",
+      "new_hash": "c0ec7eb1d4dce4b6e005970a885336115a8236b49a50bb44f45967a14f37a0eb",
+      "edit": ""
+    },
+    "printOperand": {
+      "apply_type": "OLD",
+      "old_hash": "f393056053f78ab794c9b19cb807406c245bd36e126f346f6c45ce5cdbde3d8e",
+      "new_hash": "b7bf63f107761990a32fd3aeb5f5fdd899078149907dbb91292532bf0340feff",
+      "edit": ""
+    },
+    "printPredicateOperand": {
+      "apply_type": "OLD",
+      "old_hash": "ab23ad40a217c71f43ff6c8ec8f19784ed37033a19d04ad301b320f8924fac80",
+      "new_hash": "8b0ddb39294f147701574e065b8c319a4e8309e834343f3c1ce4c66088c329c0",
+      "edit": ""
+    },
+    "printRegName": {
+      "apply_type": "OLD",
+      "old_hash": "",
+      "new_hash": "2e6aa7c41501e7b57c53b5fdaa886ca86ebd7089891301c0f24b7dcd8a3324c5",
+      "edit": ""
+    },
+    "printS12ImmOperand": {
+      "apply_type": "OLD",
+      "old_hash": "b785dfec0c79e171ce0cba13557a3f73632548508fd4b39a25018a63b06a5439",
+      "new_hash": "",
+      "edit": ""
+    },
+    "printS16ImmOperand": {
+      "apply_type": "OLD",
+      "old_hash": "6997c0380ea4f5e13ac857cccd1ab5794b8e9eba0411e36619bcb1be1ff10b0e",
+      "new_hash": "877da29cf2a5747f9af9924a4742f17c35c6f24f76b6fdac45923f5bc6f6a85b",
+      "edit": ""
+    },
+    "printS34ImmOperand": {
+      "apply_type": "OLD",
+      "old_hash": "4edac38294a85c6b9bc38a882b0943ae995065badb9897ca2f208be0a31c8881",
+      "new_hash": "4a5279dd26edb54158e602a41001d8f9505a76841ee836a4db33d99fe65cf4e1",
+      "edit": ""
+    },
+    "printS5ImmOperand": {
+      "apply_type": "OLD",
+      "old_hash": "0f03fa5b16ca7fd0059b0efd8faf0a9cf275108bdd743d84f65cec51dfcb4ea1",
+      "new_hash": "7bccae4841222be92a822afc8b4a862419d1557737f6f31e7c8d72d4d26c6734",
+      "edit": ""
+    },
+    "printTLSCall": {
+      "apply_type": "OLD",
+      "old_hash": "298367f6794901685afb2a692ef06236613534872878049537128fa0a81326c2",
+      "new_hash": "0066d2ae3dd12a0cdc201cb21ac30a8890f47514e569b7432523cdcc1775c583",
+      "edit": ""
+    },
+    "printU10ImmOperand": {
+      "apply_type": "OLD",
+      "old_hash": "329c2bb4576258a16cde9a6bddb56c6c2aab830af5ef81685e13d780c5d718a8",
+      "new_hash": "efed5cb256c3fd8ad1da010aa116f265b5af3c0395b48a685bed05208664f84e",
+      "edit": ""
+    },
+    "printU12ImmOperand": {
+      "apply_type": "OLD",
+      "old_hash": "d2c328eca98550f32ee46a015308f0ab5d1d7bffaebe26e14397654db9bfaa56",
+      "new_hash": "a1157724f4d2a16a74034a724ce3da71386c8b6bcb1aec3107a85bc9b070499e",
+      "edit": ""
+    },
+    "printU16ImmOperand": {
+      "apply_type": "OLD",
+      "old_hash": "6bf9c2cabf43daa0a7b5eeb132270715346b530f9dca20e15319ed2bffc4e383",
+      "new_hash": "4df279d97d074554226b43489fd205bf45d3cb4124af54231096594906a0e976",
+      "edit": ""
+    },
+    "printU1ImmOperand": {
+      "apply_type": "OLD",
+      "old_hash": "2ec13a0fa3a425f9318c6e66f81d0a4b1311926b3b47f26b797c983abb8e9b06",
+      "new_hash": "14add063ba02ca135e9ab95af77248c9410c0ed05ae40d1d9da36c5a895017d1",
+      "edit": ""
+    },
+    "printU2ImmOperand": {
+      "apply_type": "OLD",
+      "old_hash": "b5b1fab385df93dc26707cae3815f59d5f5613f79477c0ea28e049683a6326f2",
+      "new_hash": "1bdd4fc7273c4fa743ba3332d3f45460150b89bf2da7c5c5f57ce4e7aa7d7ce0",
+      "edit": ""
+    },
+    "printU3ImmOperand": {
+      "apply_type": "OLD",
+      "old_hash": "31a78dedd0eab05c4ccc59c2d7473b6e19a220e29e39c0b6970277c9da597ed3",
+      "new_hash": "4a985f3277a9233344b93606a6ff52730ffaf7b39917b9ac4bba5caabedcaaf6",
+      "edit": ""
+    },
+    "printU4ImmOperand": {
+      "apply_type": "OLD",
+      "old_hash": "b5da847a59417586de4c4dd58690c5a4d8e23db832994e8ac22e52c419d1d99f",
+      "new_hash": "784c9cd8868d7ad6b227fbe0ff91924862ffdb29af2f39ad89f48efeb78b91e3",
+      "edit": ""
+    },
+    "printU5ImmOperand": {
+      "apply_type": "OLD",
+      "old_hash": "04fc13f1ccfb0b361c17ed3eed0f4a188d580eb02e9cf533c60e0f902c9d5308",
+      "new_hash": "a082ee91177d93645b19098fda0c2a34110f4b54253f2050fe2558eef44135e8",
+      "edit": ""
+    },
+    "printU6ImmOperand": {
+      "apply_type": "OLD",
+      "old_hash": "85cf7076d9a8cca621968d357d4b77f0f3836a9bf032e3e2ae9f68c444931607",
+      "new_hash": "7819971c0d52699284edfed676084e9aa48c7e693b949edaae936feafeb5f832",
+      "edit": ""
+    },
+    "printU7ImmOperand": {
+      "apply_type": "OLD",
+      "old_hash": "3bda685d7d6ed4f550dd02d0b8b098687e66ff3ed9151328ec8362b9deed7bfe",
+      "new_hash": "c13555c7693c7aa52a0edc3e7af16f82ace9a13dd4fa8c8ccdba49c94a6193ed",
+      "edit": ""
+    },
+    "printU8ImmOperand": {
+      "apply_type": "OLD",
+      "old_hash": "a38744403d5221940825b10a5f6c42d430c5be4ef1d2f49d82231893a0239f31",
+      "new_hash": "76830ed242e9f7ec8d48f4119f14350016bf43378015821af6be3f9452bd29dd",
+      "edit": ""
+    },
+    "printcrbitm": {
+      "apply_type": "OLD",
+      "old_hash": "ed93ddcf6f973cc7eb12d1b898e5a9299a2885dbe53f73f63672b793d7c18bde",
+      "new_hash": "6aef7937ccfd4055a6af7f1ca9851761a6173c9be62204340bb70830bd1bb326",
+      "edit": ""
+    },
+    "showRegistersWithPercentPrefix": {
+      "apply_type": "OLD",
+      "old_hash": "10af995c53656d9202bab14d45dc4024b2ccfb9b4b8dbc47dee15633d20e68e4",
+      "new_hash": "b71d92c25b97a9064d798bedf3c4f27c5b73999cfaf0a32e36796f78e2c8e548",
+      "edit": ""
+    },
+    "showRegistersWithPrefix": {
+      "apply_type": "OLD",
+      "old_hash": "6e5e1997204591e35a474917159cce4df3221b14a46b75ed92836143620f49ec",
+      "new_hash": "6fc1608e6228661595af3817db3dcb37449fc5449ece56aac3da9e082c728b74",
+      "edit": ""
+    }
+  },
+  "PPCMCTargetDesc.h": {
+    "\"PPCGenInstrInfo.inc\"": {
+      "apply_type": "OLD",
+      "old_hash": "2e11a9c93cb8e961721b772e8b4c12e0dbccde962493297122c8d5d0091666a6",
+      "new_hash": "",
+      "edit": ""
+    },
+    "\"PPCGenRegisterInfo.inc\"": {
+      "apply_type": "OLD",
+      "old_hash": "17baf9b5639b3c9ccffc175f4eecd0ad8b476b3e70a1e058b831d667f0f8925b",
+      "new_hash": "",
+      "edit": ""
+    },
+    "\"PPCGenSubtargetInfo.inc\"": {
+      "apply_type": "OLD",
+      "old_hash": "8d8a0517a0abda49a0e1216d5ee937ad53edfcb1b16c39bde413f47299810a9e",
+      "new_hash": "",
+      "edit": ""
+    },
+    "PPC_REGS0_3": {
+      "apply_type": "OLD",
+      "old_hash": "670a9482e4a7518f7379a61b1c95f5557ebdf7c792fb240cd52b654bb2af4492",
+      "new_hash": "3bea6b9a2ae77106e599851aa16d7b97788437ddaf9b3e371e63dc6c0ce76d4d",
+      "edit": ""
+    },
+    "PPC_REGS0_31": {
+      "apply_type": "OLD",
+      "old_hash": "a11527756275205974313d4a1ec150414cf0d0a2d03296fbc164dae3cb1bb271",
+      "new_hash": "f0f99e942526700de9acc6d0b92c2d26348a7c05dc23c0b0d40cd679d293b604",
+      "edit": ""
+    },
+    "PPC_REGS0_63": {
+      "apply_type": "OLD",
+      "old_hash": "46f904feba2344f52f73d0a9ab84dcd31803dc2d7abcc36d9d078445d3715b63",
+      "new_hash": "5bf18f1540567ed86747e69bdc08ce8925ab557e4c795968729848bc14480b84",
+      "edit": ""
+    },
+    "PPC_REGS_EVEN0_30": {
+      "apply_type": "OLD",
+      "old_hash": "",
+      "new_hash": "434dc025c1310b8021e3189e1986edc817b72f65652cb4b0b2799d3c2e2c7fe2",
+      "edit": ""
+    },
+    "PPC_REGS_LO_HI": {
+      "apply_type": "OLD",
+      "old_hash": "4498a6ba97d4c9b4036512a1de81617e4102e3fe8f804c84772fabad0863b9ab",
+      "new_hash": "1039f69f06c93987e08905828820b91f59dcee53aebc36d6ac1a8cff15407741",
+      "edit": ""
+    },
+    "PPC_REGS_NO0_31": {
+      "apply_type": "OLD",
+      "old_hash": "dc0fbd1adb37235418db0a17c15f4c4c7433167c87fc09022e8cabecfdbce305",
+      "new_hash": "921202b70a23bbce4dfd988e0009eb64f6e144d65b31914579bdbb7bfba65c6a",
+      "edit": ""
+    },
+    "PPC_isVFRegister": {
+      "apply_type": "OLD",
+      "old_hash": "",
+      "new_hash": "dd0155e96436a14f7f9ec0eaa6b7ce5dd02d0ac043218c4a8e3b0acbeb1dc870",
+      "edit": ""
+    },
+    "PPC_isVRRegister": {
+      "apply_type": "OLD",
+      "old_hash": "",
+      "new_hash": "185000864ca617ffbb1aff2d44b7012a98f910b9ebf13b0d118f660f16b4b456",
+      "edit": ""
+    },
+    "isRunOfOnes": {
+      "apply_type": "OLD",
+      "old_hash": "c3de3de94ebba955e03feb016ca0aed64716eb14a2e89ba46fa56af6f2dd7401",
+      "new_hash": "a4322b7beab54963e82d9a862f3f2bc9caeeaa466920f25aa5d9dd0f02827982",
+      "edit": ""
+    },
+    "isRunOfOnes64": {
+      "apply_type": "OLD",
+      "old_hash": "93f39dbf36c667d3a320e4d3ea81765ad08950cba0f53fb0f7bc9272c4b57828",
+      "new_hash": "aff8f4f512a8ed3833f77f93a593273f1be418b42e2bec3ddb03871c1e6b357f",
+      "edit": ""
+    }
+  },
+  "PPCPredicates.h": {
+    "PPC_getPredicate": {
+      "apply_type": "OLD",
+      "old_hash": "6f4f982013d06b5c60da73f24c019eada34abeafa46d6849b726f75849b0b73b",
+      "new_hash": "2745cb11387ee4c9fa7c692356ec2ef778870f08428df3666ae218a23a02927f",
+      "edit": ""
+    },
+    "PPC_getPredicateCondition": {
+      "apply_type": "OLD",
+      "old_hash": "6680b6f42d3644d2ed656077554c6c34a403a62b47d2226810d6ad9f25ef30a8",
+      "new_hash": "96ae9e8cc826c5da2bddd91c8d109856c7234749c064ef9e1d4ec77ddfb2efdc",
+      "edit": ""
+    },
+    "PPC_getPredicateHint": {
+      "apply_type": "OLD",
+      "old_hash": "f51873e40d9a5bc6f49f1cde2418a111b356a438fdb9f20f13b625142f16dbcf",
+      "new_hash": "02eaaa869cf975da8203666135470c113ad9246dd2f73061dbf6ee1706683299",
+      "edit": ""
+    }
   }
 }
\ No newline at end of file
diff --git a/suite/auto-sync/src/autosync/lit_config/README.md b/suite/auto-sync/src/autosync/lit_config/README.md
new file mode 100644
index 000000000..b5c253464
--- /dev/null
+++ b/suite/auto-sync/src/autosync/lit_config/README.md
@@ -0,0 +1,7 @@
+<!--
+Copyright © 2024 Rot127 <unisono@quyllur.org>
+SPDX-License-Identifier: BSD-3
+-->
+
+lit configurations for MC regression test generation.
+As an introduction see: https://medium.com/@mshockwave/using-llvm-lit-out-of-tree-5cddada85a78 ([archived](https://web.archive.org/web/20240421091240/https://medium.com/@mshockwave/using-llvm-lit-out-of-tree-5cddada85a78))
diff --git a/suite/auto-sync/src/autosync/lit_config/lit.cfg.py b/suite/auto-sync/src/autosync/lit_config/lit.cfg.py
new file mode 100644
index 000000000..837216c83
--- /dev/null
+++ b/suite/auto-sync/src/autosync/lit_config/lit.cfg.py
@@ -0,0 +1,14 @@
+# Copyright © 2024 Rot127 <unisono@quyllur.org>
+# SPDX-License-Identifier: BSD-3
+
+from autosync.PathVarHandler import PathVarHandler
+import lit.formats
+
+config.name = "Generate Capstone MC regression tests"
+config.test_format = lit.formats.ShTest(True)
+
+config.suffixes = [".txt", ".s"]
+
+config.excludes = ["Inputs", "CMakeLists.txt", "README.txt", "LICENSE.txt"]
+
+config.test_source_root = PathVarHandler().get_path("{LLVM_LIT_TEST_DIR}")
diff --git a/suite/auto-sync/src/autosync/lit_config/lit.site.cfg.py b/suite/auto-sync/src/autosync/lit_config/lit.site.cfg.py
new file mode 100644
index 000000000..5685955f3
--- /dev/null
+++ b/suite/auto-sync/src/autosync/lit_config/lit.site.cfg.py
@@ -0,0 +1,16 @@
+# Copyright © 2024 Rot127 <unisono@quyllur.org>
+# SPDX-License-Identifier: BSD-3
+
+from autosync.Targets import TARGETS_LLVM_NAMING
+from autosync.PathVarHandler import PathVarHandler
+from pathlib import Path
+
+import lit.llvm
+
+lit.llvm.initialize(lit_config, config)
+
+config.llvm_src_root = str(PathVarHandler().get_path("{LLVM_ROOT}").absolute())
+config.root.targets = " ".join(TARGETS_LLVM_NAMING)
+
+lit_cfg_dir = PathVarHandler().get_path("{LLVM_LIT_TEST_DIR}")
+lit_config.load_config(config, lit_cfg_dir.joinpath("lit.cfg.py"))
diff --git a/suite/auto-sync/src/autosync/mcupdater.json b/suite/auto-sync/src/autosync/mcupdater.json
new file mode 100644
index 000000000..5e0e26618
--- /dev/null
+++ b/suite/auto-sync/src/autosync/mcupdater.json
@@ -0,0 +1,10 @@
+{
+  "additional_mattr":
+  {
+    "AArch64": [ "+all" ]
+  },
+  "mandatory_options":
+  {
+    "SystemZ": [ "CS_MODE_BIG_ENDIAN" ]
+  }
+}
diff --git a/suite/auto-sync/src/autosync/path_vars.json b/suite/auto-sync/src/autosync/path_vars.json
index 26ac90e4b..8f51c14bb 100644
--- a/suite/auto-sync/src/autosync/path_vars.json
+++ b/suite/auto-sync/src/autosync/path_vars.json
@@ -4,6 +4,7 @@
     "{LLVM_TARGET_DIR}": "{LLVM_ROOT}/llvm/lib/Target/",
     "{LLVM_MC_TEST_DIR}": "{LLVM_ROOT}/llvm/test/MC/",
     "{LLVM_TBLGEN_BIN}": "{LLVM_ROOT}/build/bin/llvm-tblgen",
+    "{LLVM_LIT_TEST_DIR}": "{AUTO_SYNC_SRC}/lit_config/",
     "{LLVM_INCLUDE_DIR}": "{LLVM_ROOT}/llvm/include/",
     "{VENDOR_DIR}": "{AUTO_SYNC_ROOT}/vendor/",
     "{BUILD_DIR}": "{AUTO_SYNC_ROOT}/build/",
@@ -32,9 +33,12 @@
     "{DIFFER_TEST_NEW_SRC_DIR}": "{DIFFER_TEST_DIR}/new_src/",
     "{DIFFER_TEST_PERSISTENCE_FILE}": "{DIFFER_TEST_DIR}/test_saved_patches.json",
     "{AUTO_SYNC_TEST_DIR}": "{AUTO_SYNC_SRC}/Tests/",
+    "{MCUPDATER_CONFIG_FILE}": "{AUTO_SYNC_SRC}/mcupdater.json",
     "{MCUPDATER_TEST_DIR}": "{AUTO_SYNC_TEST_DIR}/MCUpdaterTests/",
+    "{MCUPDATER_TEST_DIR_EXPECTED}": "{AUTO_SYNC_TEST_DIR}/MCUpdaterTests/expected",
     "{MCUPDATER_OUT_DIR}": "{BUILD_DIR}/mc_out/",
-    "{MC_DIR}": "{CS_ROOT}/suite/MC/"
+    "{MCUPDATER_TEST_OUT_DIR}": "{MCUPDATER_TEST_DIR}/test_output/",
+    "{MC_DIR}": "{CS_ROOT}/tests/MC/"
   },
   "create_during_runtime": [
     "{BUILD_DIR}",
@@ -43,7 +47,8 @@
     "{CPP_TRANSLATOR_TRANSLATION_OUT_DIR}",
     "{CPP_TRANSLATOR_DIFF_OUT_DIR}",
     "{HEADER_GEN_TEST_ARM64_OUT_FILE}",
-    "{MCUPDATER_OUT_DIR}"
+    "{MCUPDATER_OUT_DIR}",
+    "{MCUPDATER_TEST_OUT_DIR}"
   ],
   "ignore_missing": [
     "{DIFFER_TEST_PERSISTENCE_FILE}"
diff --git a/suite/compile_all.sh b/suite/compile_all.sh
deleted file mode 100755
index 8360f2b1e..000000000
--- a/suite/compile_all.sh
+++ /dev/null
@@ -1,30 +0,0 @@
-#! /bin/bash
-# By Daniel Godas-Lopez.
-
-export LD_LIBRARY_PATH=.
-
-for x in default nix32 cross-win32 cross-win64 cygwin-mingw32 cygwin-mingw64 bsd clang gcc; do
-	echo -n "Compiling: $x ... "
-	./compile.sh $x &> /dev/null
-
-	if [ $? == 0 ]; then
-		echo "-> PASS"
-	else
-		echo -e "-> FAILED\n"
-		continue
-	fi
-
-	for t in test test_arm test_aarch64 test_detail test_mips test_x86 test_ppc; do
-		./tests/$t &> /dev/null
-
-		if [ $? -eq 0 ]; then
-			echo "  Run $t -> PASS"
-		else
-			echo "  Run $t -> FAIL"
-		fi
-	done
-
-	echo
-done
-
-make clean &> /dev/null
diff --git a/suite/cstest/CMakeLists.txt b/suite/cstest/CMakeLists.txt
new file mode 100644
index 000000000..637ae9067
--- /dev/null
+++ b/suite/cstest/CMakeLists.txt
@@ -0,0 +1,88 @@
+cmake_minimum_required(VERSION 3.15)
+
+include(ExternalProject)
+find_library(libyaml
+    NAMES libyaml yaml
+    REQUIRED)
+ExternalProject_Add(cmocka_ext
+    PREFIX extern
+    URL "https://cmocka.org/files/1.1/cmocka-1.1.7.tar.xz"
+    URL_HASH SHA256=810570eb0b8d64804331f82b29ff47c790ce9cd6b163e98d47a4807047ecad82
+    DOWNLOAD_EXTRACT_TIMESTAMP true
+    CONFIGURE_COMMAND cmake -DBUILD_SHARED_LIBS=OFF -DCMAKE_BUILD_TYPE=${CMAKE_BUILD_TYPE} ../cmocka_ext/
+    BUILD_COMMAND cmake --build . --config Release
+    INSTALL_COMMAND ""
+)
+
+if ("${CMAKE_BUILD_TYPE}" STREQUAL "Debug")
+    set(LIBCYAML_VARIANT "debug")
+else()
+    set(LIBCYAML_VARIANT "release")
+endif()
+
+ExternalProject_Add(libcyaml_ext
+    PREFIX extern
+    URL "https://github.com/tlsa/libcyaml/archive/refs/tags/v1.4.1.tar.gz"
+    URL_HASH SHA256=8dbd216e1fce90f9f7cca341e5178710adc76ee360a7793ef867edb28f3e4130
+    DOWNLOAD_EXTRACT_TIMESTAMP true
+    CONFIGURE_COMMAND ""
+    BUILD_COMMAND make VARIANT=${LIBCYAML_VARIANT}
+    BUILD_IN_SOURCE true
+    INSTALL_COMMAND ""
+)
+set(CMOCKA_INCLUDE_DIR ${CMAKE_CURRENT_BINARY_DIR}/extern/src/cmocka_ext/include)
+set(CMOCKA_LIB_DIR ${CMAKE_CURRENT_BINARY_DIR}/extern/src/cmocka_ext-build/src/)
+set(LIBCYAML_INCLUDE_DIR ${CMAKE_CURRENT_BINARY_DIR}/extern/src/libcyaml_ext/include)
+set(LIBCYAML_LIB_DIR ${CMAKE_CURRENT_BINARY_DIR}/extern/src/libcyaml_ext/build/${LIBCYAML_VARIANT}/)
+add_library(cmocka STATIC IMPORTED)
+add_library(libcyaml STATIC IMPORTED)
+set_target_properties(cmocka PROPERTIES IMPORTED_LOCATION ${CMOCKA_LIB_DIR}/libcmocka.a)
+set_target_properties(libcyaml PROPERTIES IMPORTED_LOCATION ${LIBCYAML_LIB_DIR}/libcyaml.a)
+
+set(CSTEST_INCLUDE_DIR ${CSTEST_DIR}/include)
+file(GLOB CSTEST_SRC ${CSTEST_DIR}/src/*.c)
+add_executable(cstest ${CSTEST_SRC})
+add_library(libcstest STATIC ${CSTEST_SRC})
+add_dependencies(cstest cmocka_ext)
+add_dependencies(cstest libcyaml_ext)
+target_link_libraries(cstest PUBLIC capstone cmocka libcyaml yaml)
+target_link_libraries(libcstest PUBLIC capstone cmocka libcyaml yaml)
+target_include_directories(cstest PRIVATE
+        ${PROJECT_SOURCE_DIR}/include>
+        ${CSTEST_INCLUDE_DIR}
+        ${CMOCKA_INCLUDE_DIR}
+        ${LIBCYAML_INCLUDE_DIR}
+        )
+target_include_directories(libcstest PRIVATE
+        ${PROJECT_SOURCE_DIR}/include>
+        ${CSTEST_INCLUDE_DIR}
+        ${CMOCKA_INCLUDE_DIR}
+        ${LIBCYAML_INCLUDE_DIR}
+        )
+
+# Unit tests for cstest
+set(CSTEST_TEST_DIR ${CSTEST_DIR}/test/)
+add_subdirectory(${CSTEST_TEST_DIR})
+
+# Test targets
+add_test(MCTests
+    cstest ${PROJECT_SOURCE_DIR}/tests/MC
+    WORKING_DIRECTORY ${PROJECT_SOURCE_DIR}
+)
+add_test(DetailTests
+    cstest ${PROJECT_SOURCE_DIR}/tests/details
+    WORKING_DIRECTORY ${PROJECT_SOURCE_DIR}
+)
+add_test(IssueTests
+    cstest ${PROJECT_SOURCE_DIR}/tests/issues
+    WORKING_DIRECTORY ${PROJECT_SOURCE_DIR}
+)
+add_test(FeaturesTests
+    cstest ${PROJECT_SOURCE_DIR}/tests/features
+    WORKING_DIRECTORY ${PROJECT_SOURCE_DIR}
+)
+
+
+if(CAPSTONE_INSTALL)
+    install(TARGETS cstest EXPORT capstone-targets DESTINATION ${CMAKE_INSTALL_BINDIR})
+endif()
diff --git a/suite/cstest/Makefile b/suite/cstest/Makefile
deleted file mode 100644
index ae8059780..000000000
--- a/suite/cstest/Makefile
+++ /dev/null
@@ -1,13 +0,0 @@
-SOURCE = src
-INCLUDE = include ../../include
-BUILD = build
-LIBRARY = -lcmocka -lcapstone -L../..
-
-all:
-	rm -rf $(BUILD)
-	mkdir $(BUILD)
-	$(CC) $(SOURCE)/*.c $(INCLUDE:%=-I %) ${CMAKE_C_FLAGS} -g -o $(BUILD)/cstest $(LIBRARY)
-cstest:
-	$(BUILD)/cstest -d ../MC	
-clean:
-	rm -rf $(BUILD)
diff --git a/suite/cstest/README.md b/suite/cstest/README.md
index dfc31cdea..d2893aedd 100644
--- a/suite/cstest/README.md
+++ b/suite/cstest/README.md
@@ -1,67 +1,16 @@
-# Regression testing
-This directory contains a tool for regression testing core of Capstone
+<!--
+Copyright © 2024 Rot127 <unisono@quyllur.org>
+SPDX-License-Identifier: BSD-3
+-->
 
-## Dependency
+## Building
 
-- MacOS users can install cmocka with:
+`cstest` is build together with Capstone by adding the flag `-DCAPSTONE_BUILD_CSTEST`.
 
-```
-brew install cmocka
-```
+The build requires `libyaml`. It is a fairly common package and should be provided by your package manager.
 
-- Or download & build from source code [Cmocka](https://git.cryptomilk.org/projects/cmocka.git)
+## Testing
 
-- Build Cmocka
-
-## Build
-
-You can build `cstest` with `cmake` when building Capstone. Just pass the `CAPSTONE_BUILD_CSTEST` flag
-during configuration.
-
-Alternatively you can use the `build_cstest.sh` file in this directory.
-
-## Usage
-
-- Usage: `cstest [-e] [-f <file_name.cs>] [-d <directory>]`
-	- `-e` : test all commented test
-
-- Test for all closed issues
-
-```
-cd suite/cstest
-./build/cstest -f ./issues.cs
-```
-
-- Test for some input from LLVM
-
-```
-cd suite/cstest
-./build/cstest -f ../MC/AArch64/basic-a64-instructions.s.cs
-```
-
-- Test for all cs file in a folder
-
-```
-cd suite/cstest
-./build/cstest -d ../MC
-```
-
-- Test all
-
-```
-cd suite/cstest
-make cstest
-```
-
-## Report tool
-
-- Usage `cstest_report.py [-Dc] -t <cstest_path> [-f <file_name.cs>] [-d <directory>]`
-	- `-D` : print details
-	- `-c` : auto comment out failed test
-
-- Example: 
-
-```
-./cstest_report.py -t build/cstest -d ../MC/PowerPC/
-./cstest_report.py -t build/cstest -f issues.cs
-```
+Files to test `cstest` itself are located in `suite/cstest/test`.
+And yes, testing with a shell script is not nice. But I have time constraints, and
+for integration testing it does pretty much exactly what it should.
diff --git a/suite/cstest/build_cstest.sh b/suite/cstest/build_cstest.sh
deleted file mode 100755
index ba3c81d81..000000000
--- a/suite/cstest/build_cstest.sh
+++ /dev/null
@@ -1,21 +0,0 @@
-#!/bin/sh -x
-
-cd cmocka
-mkdir build
-cd build
-
-if [ "$(uname)" = Darwin ]; then
-  cmake -DCMAKE_INSTALL_PREFIX=/usr/local .. && make -j2 && sudo make install
-elif [ "$asan" = "ON" ]; then
-  CMAKE_C_FLAGS="-fsanitize=address" CMAKE_LINK_FLAGS="-fsanitize=address" cmake -DCMAKE_INSTALL_PREFIX=/usr/local .. && make -j2 && sudo make install
-else  # Linux
-  cmake -DCMAKE_INSTALL_PREFIX=/usr .. && make -j2 && sudo make install
-fi
-
-cd ../..
-
-if [ "$asan" = "ON" ]; then
-  CMAKE_C_FLAGS="-fsanitize=address" make
-else
-  make
-fi
diff --git a/suite/cstest/cstest_report.py b/suite/cstest/cstest_report.py
deleted file mode 100755
index 45254c65c..000000000
--- a/suite/cstest/cstest_report.py
+++ /dev/null
@@ -1,114 +0,0 @@
-#!/usr/bin/python
-
-import re
-import sys
-import getopt
-from subprocess import Popen, PIPE
-from pprint import pprint as ppr
-import os
-
-_python3 = sys.version_info.major == 3
-
-
-def Usage(s):
-	print('Usage: {} -t <cstest_path> [-f <file_name.cs>] [-d <directory>]'.format(s))
-	sys.exit(-1)
-
-def get_report_file(toolpath, filepath, getDetails, cmt_out):
-	cmd = [toolpath if toolpath else "cstest", '-f', filepath]
-	process = Popen(cmd, stdout=PIPE, stderr=PIPE)
-	stdout, stderr = process.communicate()
-	if process.returncode != 0:
-		print('[-] Failed to run cstest on {}'.format(filepath))
-		print('[-] stdout:')
-		print(stdout)
-		print('[-] stderr:')
-		print(stderr)
-		return 0
-
-#	stdout
-	failed_tests = []
-	if _python3:
-		stdout = bytes.decode(stdout)
-		stderr = bytes.decode(stderr)
-	# print('---> stdout\n', stdout)
-	# print('---> stderr\n', stderr)
-	matches = re.finditer(r'\[\s+RUN\s+\]\s+(.*)\n\[\s+FAILED\s+\]', stdout)
-	for match in matches:
-		failed_tests.append(match.group(1))
-#	stderr
-	counter = 0
-	details = []
-	for line in stderr.split('\n'):
-		if '[  PASSED  ] 0 test(s).' in line:
-			break
-		elif 'LINE' in line:
-			continue
-		elif 'ERROR' in line and ' --- ' in line:
-			parts = line.split(' --- ')
-			try:
-				details.append((parts[1], failed_tests[counter], parts[2]))
-			except IndexError:
-				details.append(('', 'Unknown test', line.split(' --- ')[1]))
-			counter += 1
-		else:
-			continue
-	print('\n[-] There are/is {} failed test(s)'.format(len(details)))
-	if len(details) > 0 and getDetails:
-		print('[-] Detailed report for {}:\n'.format(filepath))
-		for c, f, d in details:
-			print('\t[+] {}: {}\n\t\t{}\n'.format(f, c, d))
-		print('\n')
-		return 0
-	elif len(details) > 0:
-		for c, f, d in details:
-			if len(f) > 0 and cmt_out is True:
-				tmp_cmd = ['sed', '-E', '-i.bak', 's/({})(.*)/\/\/ \\1\\2/g'.format(c), filepath]
-				sed_proc = Popen(tmp_cmd, stdout=PIPE, stderr=PIPE)
-				sed_proc.communicate()
-				tmp_cmd2 = ['rm', '-f', filepath + '.bak']
-				rm_proc = Popen(tmp_cmd2, stdout=PIPE, stderr=PIPE)
-				rm_proc.communicate()
-
-		return 0
-	return 1
-
-def get_report_folder(toolpath, folderpath, details, cmt_out):
-	result = 1
-	for root, dirs, files in os.walk(folderpath):
-		path = root.split(os.sep)
-		for f in files:
-			if f.split('.')[-1] == 'cs':
-				print('[-] Target:', f,)
-				result *= get_report_file(toolpath, os.sep.join(x for x in path) + os.sep + f, details, cmt_out)
-	
-	sys.exit(result ^ 1)
-
-if __name__ == '__main__':
-	Done = False
-	details = False
-	toolpath = ''
-	cmt_out = False
-	try:
-		opts, args = getopt.getopt(sys.argv[1:], "ct:f:d:D")
-		for opt, arg in opts:
-			if opt == '-f':
-				result = get_report_file(toolpath, arg, details, cmt_out)
-				if result == 0:
-					sys.exit(1)
-				Done = True
-			elif opt == '-d':
-				get_report_folder(toolpath, arg, details, cmt_out)
-				Done = True
-			elif opt == '-t':
-				toolpath = arg
-			elif opt == '-D':
-				details = True
-			elif opt == '-c':
-				cmt_out = True
-
-	except getopt.GetoptError:
-		Usage(sys.argv[0])
-
-	if Done is False:
-		Usage(sys.argv[0])
diff --git a/suite/cstest/include/capstone_test.h b/suite/cstest/include/capstone_test.h
deleted file mode 100644
index 45901af89..000000000
--- a/suite/cstest/include/capstone_test.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/* Capstone testing regression */
-/* By Do Minh Tuan <tuanit96@gmail.com>, 02-2019 */
-
-
-#ifndef CAPSTONE_TEST_H
-#define CAPSTONE_TEST_H
-
-#include <stdarg.h>
-#include <stddef.h>
-#include <setjmp.h>
-#include <stdint.h>
-#include <cmocka.h>
-#include <stdlib.h>
-#include <string.h>
-#include <capstone/capstone.h>
-#include "helper.h"
-#include "factory.h"
-
-#define cs_assert_err(expect, err)									\
-	do {																\
-		cs_err __err = err;												\
-		if (__err != expect) {											\
-			fail_msg("%s",cs_strerror(__err));							\
-		}																\
-	} while (0)
-
-
-#define cs_assert_success(err) cs_assert_err(CS_ERR_OK, err)
-
-
-#define cs_assert_fail(err)											\
-	do {																\
-		cs_err __err = err;												\
-		if (__err == CS_ERR_OK) {										\
-			fail_msg("%s",cs_strerror(__err));							\
-		}																\
-	} while (0)
-
-#define NUMARCH 10
-#define NUMMODE 35
-#define NUMOPTION 41
-#define MAXMEM 1024
-
-typedef struct {
-	const char *str;
-	unsigned int value;
-} single_dict;
-
-typedef struct {
-	const char *str;
-	unsigned int first_value;
-	unsigned int second_value;
-} double_dict;
-
-extern char *(*function)(csh *, cs_mode, cs_insn*);
-
-int get_index(double_dict d[], unsigned size, const char *str);
-int get_value(single_dict d[], unsigned size, const char *str);
-void test_single_MC(csh *handle, int mc_mode, char *line);
-void test_single_issue(csh *handle, cs_mode mode, char *line, int detail);
-int set_function(int arch);
-
-#endif /* CAPSTONE_TEST_H */
diff --git a/suite/cstest/include/factory.h b/suite/cstest/include/factory.h
deleted file mode 100644
index d3c36dba7..000000000
--- a/suite/cstest/include/factory.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/* Capstone testing regression */
-/* By Do Minh Tuan <tuanit96@gmail.com>, 02-2019 */
-
-
-#ifndef FACTORY_H
-#define FACTORY_H
-
-#include <capstone/capstone.h>
-#include "helper.h"
-
-char *get_detail_evm(csh *handle, cs_mode mode, cs_insn *ins);
-char *get_detail_arm(csh *handle, cs_mode mode, cs_insn *ins);
-char *get_detail_aarch64(csh *handle, cs_mode mode, cs_insn *ins);
-char *get_detail_m680x(csh *handle, cs_mode mode, cs_insn *ins);
-char *get_detail_mips(csh *handle, cs_mode mode, cs_insn *ins);
-char *get_detail_ppc(csh *handle, cs_mode mode, cs_insn *ins);
-char *get_detail_sparc(csh *handle, cs_mode mode, cs_insn *ins);
-char *get_detail_sysz(csh *handle, cs_mode mode, cs_insn *ins);
-char *get_detail_x86(csh *handle, cs_mode mode, cs_insn *ins);
-char *get_detail_xcore(csh *handle, cs_mode mode, cs_insn *ins);
-char *get_detail_riscv(csh *handle, cs_mode mode, cs_insn *ins);
-char *get_detail_m68k(csh *handle, cs_mode mode, cs_insn *ins);
-char *get_detail_mos65xx(csh *handle, cs_mode mode, cs_insn *ins);
-char *get_detail_tms320c64x(csh *handle, cs_mode mode, cs_insn *ins);
-char *get_detail_bpf(csh *handle, cs_mode mode, cs_insn *ins);
-char *get_detail_tricore(csh *handle, cs_mode mode, cs_insn *ins);
-char *get_detail_alpha(csh *handle, cs_mode mode, cs_insn *ins);
-char *get_detail_hppa(csh *handle, cs_mode mode, cs_insn *ins);
-char *get_detail_loongarch(csh *handle, cs_mode mode, cs_insn *ins);
-
-#endif /* FACTORY_H */
diff --git a/suite/cstest/include/helper.h b/suite/cstest/include/helper.h
index a20dcca13..b9b89773f 100644
--- a/suite/cstest/include/helper.h
+++ b/suite/cstest/include/helper.h
@@ -1,33 +1,21 @@
 /* Capstone testing regression */
 /* By Do Minh Tuan <tuanit96@gmail.com>, 02-2019 */
 
-
 #ifndef HELPER_H
 #define HELPER_H
 
-#include <string.h>
-#include <stdlib.h>
-#include <stdio.h>
-#include <stdarg.h>
-#include <ctype.h>
-#include <dirent.h>
-#include "capstone_test.h"
+#include <stddef.h>
 
+#define MAX_ASM_TXT_MEM 1024
 #define X86_16 0
 #define X86_32 1
 #define X86_64 2
 
-char **split(const char *str, const char *delim, int *size);
-void print_strs(char **list_str, int size);
-void free_strs(char **list_str, int size);
+void trim_str(char *str);
 void add_str(char **src, const char *format, ...);
-void trim_str(char *src);
-void replace_hex(char *src);
-void replace_negative(char *src, int mode);
-void replace_tabs(char *str);
-const char *get_filename_ext(const char *filename);
-
-char *readfile(const char *filename);
-void listdir(const char *name, char ***files, int *num_files);
+void replace_hex(char *src, size_t src_len);
+void replace_negative(char *src, size_t src_len, size_t arch_bits);
+void norm_spaces(char *str);
+void str_to_lower(char *str);
 
 #endif /* HELPER_H */
diff --git a/suite/cstest/include/test_case.h b/suite/cstest/include/test_case.h
new file mode 100644
index 000000000..b5f7657a0
--- /dev/null
+++ b/suite/cstest/include/test_case.h
@@ -0,0 +1,175 @@
+// Copyright © 2024 Rot127 <unisono@quyllur.org>
+// SPDX-License-Identifier: BSD-3
+
+#ifndef TESTCASE_H
+#define TESTCASE_H
+
+#include "test_detail.h"
+#include <cyaml/cyaml.h>
+#include <capstone/capstone.h>
+#include <stdbool.h>
+#include <stdint.h>
+
+/// Input data for a test case.
+typedef struct {
+	char *name;
+	uint8_t *bytes;		// mandatory
+	uint32_t bytes_count;	// Filled by cyaml
+	char *arch;		// mandatory
+	uint64_t address;
+	char **options;		// mandatory
+	uint32_t options_count; // Filled by cyaml
+} TestInput;
+
+TestInput *test_input_new();
+void test_input_free(TestInput *test_input);
+TestInput *test_input_clone(TestInput *test_input);
+char *test_input_stringify(const TestInput *test_input, const char *postfix);
+cs_arch test_input_get_cs_arch(const TestInput *test_input);
+cs_mode test_input_get_cs_mode(const TestInput *test_input);
+void test_input_get_cs_option(const TestInput *test_input, cs_opt_type *otype,
+			      cs_opt_value *oval);
+
+/// A single byte
+static const cyaml_schema_value_t byte_schema = {
+	CYAML_VALUE_UINT(CYAML_FLAG_DEFAULT, uint8_t),
+};
+
+/// A single option string
+static const cyaml_schema_value_t option_schema = {
+	CYAML_VALUE_STRING(CYAML_FLAG_POINTER, char, 0, CYAML_UNLIMITED),
+};
+
+static const cyaml_schema_field_t test_input_mapping_schema[] = {
+	CYAML_FIELD_STRING_PTR("name", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, TestInput, name,
+			     0, CYAML_UNLIMITED),
+	CYAML_FIELD_SEQUENCE("bytes", CYAML_FLAG_POINTER, TestInput, bytes,
+			     &byte_schema, 0, CYAML_UNLIMITED), // 0-MAX bytes
+	CYAML_FIELD_STRING_PTR("arch", CYAML_FLAG_POINTER, TestInput, arch, 0,
+			       CYAML_UNLIMITED),
+	CYAML_FIELD_UINT("address",
+			 CYAML_FLAG_SCALAR_PLAIN | CYAML_FLAG_OPTIONAL,
+			 TestInput, address),
+	CYAML_FIELD_SEQUENCE("options", CYAML_FLAG_POINTER, TestInput, options,
+			     &option_schema, 0,
+			     CYAML_UNLIMITED), // 0-MAX options
+	CYAML_FIELD_END
+};
+
+/// Data compared to the produced cs_insn.
+typedef struct {
+	uint32_t id;
+	char *asm_text;	  // mandatory
+	char *op_str;
+	int32_t is_alias; ///< 0 == not given, >0 == true, <0 == false
+	uint64_t alias_id;
+	char *mnemonic;
+	TestDetail *details;
+} TestInsnData;
+
+TestInsnData *test_insn_data_new();
+void test_insn_data_free(TestInsnData *test_insn_data);
+TestInsnData *test_insn_data_clone(TestInsnData *test_insn_data);
+
+static const cyaml_schema_field_t test_insn_data_mapping_schema[] = {
+	CYAML_FIELD_UINT("id", CYAML_FLAG_SCALAR_PLAIN | CYAML_FLAG_OPTIONAL,
+			 TestInsnData, id),
+	CYAML_FIELD_STRING_PTR("asm_text", CYAML_FLAG_POINTER, TestInsnData,
+			       asm_text, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_STRING_PTR(
+		"op_str", CYAML_FLAG_POINTER_NULL_STR | CYAML_FLAG_OPTIONAL,
+		TestInsnData, op_str, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_UINT("is_alias", CYAML_FLAG_OPTIONAL, TestInsnData,
+			 is_alias),
+	CYAML_FIELD_INT("alias_id",
+			CYAML_FLAG_SCALAR_PLAIN | CYAML_FLAG_OPTIONAL,
+			TestInsnData, alias_id),
+	CYAML_FIELD_STRING_PTR(
+		"mnemonic", CYAML_FLAG_POINTER_NULL_STR | CYAML_FLAG_OPTIONAL,
+		TestInsnData, mnemonic, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_MAPPING_PTR(
+		"details", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+		TestInsnData, details, test_detail_mapping_schema),
+	CYAML_FIELD_END
+};
+
+/// The expected data for a test. This can hold multiple instructions
+/// if enough bytes were given.
+typedef struct {
+	TestInsnData **insns; ///< Zero to N disassembled instructions.
+	uint32_t insns_count; ///< Filled by cyaml.
+} TestExpected;
+
+TestExpected *test_expected_new();
+void test_expected_free(TestExpected *test_expected);
+TestExpected *test_expected_clone(TestExpected *test_expected);
+void test_expected_compare(csh *handle, TestExpected *expected, cs_insn *insns,
+			   size_t insns_count, size_t arch_bits);
+
+static const cyaml_schema_value_t insn_schema = {
+	CYAML_VALUE_MAPPING(CYAML_FLAG_POINTER, TestInsnData,
+			    test_insn_data_mapping_schema),
+};
+
+static const cyaml_schema_field_t test_expected_mapping_schema[] = {
+	CYAML_FIELD_SEQUENCE("insns", CYAML_FLAG_POINTER, TestExpected, insns,
+			     &insn_schema, 0, CYAML_UNLIMITED), // 0-MAX options
+	CYAML_FIELD_END
+};
+
+/// A single test case.
+typedef struct {
+	TestInput *input;	///< Input data for a test case
+	TestExpected *expected; ///< Expected data of the test case.
+	bool skip;		///< If set, the test is skipped
+	char *skip_reason;	///< Reason this test is skipped.
+} TestCase;
+
+TestCase *test_case_new();
+void test_case_free(TestCase *test_case);
+TestCase *test_case_clone(TestCase *test_case);
+
+static const cyaml_schema_field_t test_case_mapping_schema[] = {
+	CYAML_FIELD_MAPPING_PTR("input", CYAML_FLAG_POINTER, TestCase, input,
+				test_input_mapping_schema),
+	CYAML_FIELD_MAPPING_PTR("expected", CYAML_FLAG_POINTER, TestCase,
+				expected, test_expected_mapping_schema),
+	CYAML_FIELD_BOOL("skip", CYAML_FLAG_OPTIONAL, TestCase, skip),
+	CYAML_FIELD_STRING_PTR("skip_reason",
+			       CYAML_FLAG_POINTER_NULL_STR |
+				       CYAML_FLAG_OPTIONAL,
+			       TestCase, skip_reason, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_END
+};
+
+static const cyaml_schema_value_t test_case_schema = {
+	CYAML_VALUE_MAPPING(CYAML_FLAG_POINTER, TestCase,
+			    test_case_mapping_schema),
+};
+
+typedef struct {
+	char *filename; ///< Filename. NOT filled by cyaml.
+	TestCase **test_cases;
+	uint32_t test_cases_count;
+} TestFile;
+
+TestFile *test_file_new();
+void test_file_free(TestFile *test_file);
+TestFile *test_file_clone(TestFile *test_file);
+
+static const cyaml_schema_field_t test_file_mapping_schema[] = {
+	CYAML_FIELD_STRING_PTR(
+		"filename", CYAML_FLAG_OPTIONAL | CYAML_FLAG_POINTER_NULL_STR,
+		TestFile, filename, 0, 0),
+	CYAML_FIELD_SEQUENCE("test_cases", CYAML_FLAG_POINTER, TestFile,
+			     test_cases, &test_case_schema, 1,
+			     CYAML_UNLIMITED), // 1-MAX options
+	CYAML_FIELD_END
+};
+
+static const cyaml_schema_value_t test_file_schema = {
+	CYAML_VALUE_MAPPING(CYAML_FLAG_POINTER, TestFile,
+			    test_file_mapping_schema),
+};
+
+#endif // TESTCASE_H
diff --git a/suite/cstest/include/test_compare.h b/suite/cstest/include/test_compare.h
new file mode 100644
index 000000000..8850d2c1b
--- /dev/null
+++ b/suite/cstest/include/test_compare.h
@@ -0,0 +1,230 @@
+// Copyright © 2024 Rot127 <unisono@quyllur.org>
+// SPDX-License-Identifier: BSD-3
+
+#ifndef TEST_COMPARE_H
+#define TEST_COMPARE_H
+
+#include <stdint.h>
+#include "test_mapping.h"
+#include "../../../utils.h"
+
+/// An integer encoding a boolean value from the test files.
+/// libcyaml saves 0 by default, if an optional value was not set.
+/// Due to that, boolean values are represented as integer with the
+/// interpretation:
+///
+/// = 0 => unset
+/// < 0 => false
+/// > 0 => true
+typedef int32_t tbool;
+
+/// Compares the @actual bool against the @expected tbool:
+/// It returns with @ret_val, if expected is set but the values mismatch.
+#define compare_tbool_ret(actual, expected, ret_val) \
+	if (expected != 0 && \
+	    ((actual && expected <= 0) || (!actual && expected >= 0))) { \
+		fprintf(stderr, \
+			#actual " is %s but expected is %" PRId32 \
+				" (=0 unset, >0 true, <0 false)\n", \
+			actual ? "true" : "false", expected); \
+		return ret_val; \
+	}
+
+/// Compares two unsigned int values.
+/// It returns with @ret_val if they mismatch.
+#define compare_uint_ret(actual, expected, ret_val) \
+	if (((unsigned int)actual) != ((unsigned int)expected)) { \
+		fprintf(stderr, \
+			#actual " != " #expected ": 0x%" PRIx32 \
+				" != 0x%" PRIx32 "\n", \
+			actual, expected); \
+		return ret_val; \
+	}
+
+/// Compares two uint8_t values.
+/// It returns with @ret_val if they mismatch.
+#define compare_uint8_ret(actual, expected, ret_val) \
+	if (((uint8_t)actual) != ((uint8_t)expected)) { \
+		fprintf(stderr, \
+			#actual " != " #expected ": %" PRId8 " != %" PRId8 \
+				"\n", \
+			actual, expected); \
+		return ret_val; \
+	}
+
+/// Compares two uint16_t values.
+/// It returns with @ret_val if they mismatch.
+#define compare_uint16_ret(actual, expected, ret_val) \
+	if (((uint16_t)actual) != ((uint16_t)expected)) { \
+		fprintf(stderr, \
+			#actual " != " #expected ": 0x%" PRIx16 \
+				" != 0x%" PRIx16 "\n", \
+			actual, expected); \
+		return ret_val; \
+	}
+
+/// Compares two uint32_t values.
+/// It returns with @ret_val if they mismatch.
+#define compare_uint32_ret(actual, expected, ret_val) \
+	if (((uint32_t)actual) != ((uint32_t)expected)) { \
+		fprintf(stderr, \
+			#actual " != " #expected ": 0x%" PRIx32 \
+				" != 0x%" PRIx32 "\n", \
+			actual, expected); \
+		return ret_val; \
+	}
+
+/// Compares two uint64_t values.
+/// It returns with @ret_val if they mismatch.
+#define compare_uint64_ret(actual, expected, ret_val) \
+	if (((uint64_t)actual) != ((uint64_t)expected)) { \
+		fprintf(stderr, \
+			#actual " != " #expected ": 0x%" PRIx64 \
+				" != 0x%" PRIx64 "\n", \
+			actual, expected); \
+		return ret_val; \
+	}
+
+/// Compares two int values.
+/// It returns with @ret_val if they mismatch.
+#define compare_int_ret(actual, expected, ret_val) \
+	if (((int)actual) != ((int)expected)) { \
+		fprintf(stderr, \
+			#actual " != " #expected ": 0x%" PRIx32 \
+				" != 0x%" PRIx32 "\n", \
+			actual, expected); \
+		return ret_val; \
+	}
+
+/// Compares two int8_t values.
+/// It returns with @ret_val if they mismatch.
+#define compare_int8_ret(actual, expected, ret_val) \
+	if (((int8_t)actual) != ((int8_t)expected)) { \
+		fprintf(stderr, \
+			#actual " != " #expected ": 0x%" PRIx8 " != 0x%" PRIx8 \
+				"\n", \
+			actual, expected); \
+		return ret_val; \
+	}
+
+/// Compares two int16_t values.
+/// It returns with @ret_val if they mismatch.
+#define compare_int16_ret(actual, expected, ret_val) \
+	if (((int16_t)actual) != ((int16_t)expected)) { \
+		fprintf(stderr, \
+			#actual " != " #expected ": 0x%" PRIx16 \
+				" != 0x%" PRIx16 "\n", \
+			actual, expected); \
+		return ret_val; \
+	}
+
+/// Compares two int32_t values.
+/// It returns with @ret_val if they mismatch.
+#define compare_int32_ret(actual, expected, ret_val) \
+	if (((int32_t)actual) != ((int32_t)expected)) { \
+		fprintf(stderr, \
+			#actual " != " #expected ": 0x%" PRIx32 \
+				" != 0x%" PRIx32 "\n", \
+			actual, expected); \
+		return ret_val; \
+	}
+
+/// Compares two int64_t values.
+/// It returns with @ret_val if they mismatch.
+#define compare_int64_ret(actual, expected, ret_val) \
+	if (((int64_t)actual) != ((int64_t)expected)) { \
+		fprintf(stderr, \
+			#actual " != " #expected ": 0x%" PRIx64 \
+				" != 0x%" PRIx64 "\n", \
+			actual, expected); \
+		return ret_val; \
+	}
+
+/// Compares two floating point values.
+/// It returns with @ret_val if they mismatch.
+#define compare_fp_ret(actual, expected, ret_val) \
+	if (actual != expected) { \
+		fprintf(stderr, #actual " != " #expected ": %f != %f\n", \
+			actual, expected); \
+		return ret_val; \
+	}
+
+/// Compares enum id.
+/// Actual is the value, expected is the enum idetifer as string.
+/// It returns with @ret_val if they mismatch.
+#define compare_enum_ret(actual, expected, ret_val) \
+	if (expected) { \
+		bool found = false; \
+		uint32_t eval = enum_map_bin_search( \
+			cs_enum_map, ARR_SIZE(cs_enum_map), expected, &found); \
+		if (expected && (actual != eval || !found)) { \
+			fprintf(stderr, \
+				#actual " != " #expected ": %" PRId32 \
+					" != %s%s\n", \
+				actual, expected, \
+				found ? "" : " <== id not found"); \
+			return ret_val; \
+		} \
+	}
+
+/// Checks if all bit flags in @expected are set in @actual.
+/// Actual is the value with all bits set.
+/// @expected is a list the @len enum identifiers as string.
+/// It returns with @ret_val if they mismatch.
+#define compare_bit_flags_ret(actual, expected, len, ret_val) \
+	if (expected) { \
+		for (size_t cmp_i = 0; cmp_i < len; ++cmp_i) { \
+			bool found = false; \
+			uint32_t eval = enum_map_bin_search( \
+				cs_enum_map, ARR_SIZE(cs_enum_map), \
+				expected[cmp_i], &found); \
+			if (!(actual & eval) || !found) { \
+				fprintf(stderr, \
+					#actual " != " #expected ": %" PRId32 \
+						" != %s%s\n", \
+					actual, expected[cmp_i], \
+					found ? " <== Flag not set" : \
+						" <== id not found"); \
+				return ret_val; \
+			} \
+		} \
+	}
+
+/// Checks if all bit flags in @expected are set in @actual.
+/// Actual is the value with all bits set.
+/// @expected is a list the @len enum identifiers as string.
+/// It returns with @ret_val if they mismatch.
+#define compare_bit_flags_64_ret(actual, expected, len, ret_val) \
+	if (expected) { \
+		for (size_t cmp_i = 0; cmp_i < len; ++cmp_i) { \
+			bool found = false; \
+			uint64_t eval = enum_map_bin_search( \
+				cs_enum_map, ARR_SIZE(cs_enum_map), \
+				expected[cmp_i], &found); \
+			if (!(actual & eval) || !found) { \
+				fprintf(stderr, \
+					#actual " != " #expected ": %" PRId64 \
+						" != %s%s\n", \
+					actual, expected[cmp_i], \
+					found ? " <== Flag not set" : \
+						" <== id not found"); \
+				return ret_val; \
+			} \
+		} \
+	}
+
+/// Compares register names.
+/// Actual is the register id, expected is name as string.
+/// It returns with @ret_val if they mismatch.
+#define compare_reg_ret(handle, actual, expected, ret_val) \
+	if (expected) { \
+		const char *reg_name = cs_reg_name(handle, actual); \
+		if (expected && !strings_match(reg_name, expected)) { \
+			fprintf(stderr, \
+				#actual " != " #expected ": '%s' != '%s'\n", \
+				reg_name, expected); \
+			return ret_val; \
+		} \
+	}
+
+#endif // TEST_COMPARE_H
diff --git a/suite/cstest/include/test_detail.h b/suite/cstest/include/test_detail.h
new file mode 100644
index 000000000..fe682f089
--- /dev/null
+++ b/suite/cstest/include/test_detail.h
@@ -0,0 +1,174 @@
+// Copyright © 2024 Rot127 <unisono@quyllur.org>
+// SPDX-License-Identifier: BSD-3
+
+/// @file Defines all detail structures to test against and their yaml schemas.
+/// The structs currently need to be partially redefined, if they contain unions.
+/// And they won't be supported until libcyaml v2:
+/// https://github.com/tlsa/libcyaml/issues/186
+
+#ifndef TEST_DETAIL_H
+#define TEST_DETAIL_H
+
+#include "test_detail_aarch64.h"
+#include "test_detail_arm.h"
+#include "test_detail_evm.h"
+#include "test_detail_loongarch.h"
+#include "test_detail_mos65xx.h"
+#include "test_detail_ppc.h"
+#include "test_detail_riscv.h"
+#include "test_detail_tricore.h"
+#include "test_detail_systemz.h"
+#include "test_detail_sh.h"
+#include "test_detail_sparc.h"
+#include "test_detail_alpha.h"
+#include "test_detail_bpf.h"
+#include "test_detail_hppa.h"
+#include "test_detail_xcore.h"
+#include "test_detail_mips.h"
+#include "test_detail_riscv.h"
+#include "test_detail_m680x.h"
+#include "test_detail_tms320c64x.h"
+#include "test_detail_wasm.h"
+#include "test_detail_x86.h"
+#include "test_detail_m68k.h"
+#include "test_compare.h"
+#include <capstone/capstone.h>
+#include <cyaml/cyaml.h>
+
+/// The equivalent to cs_detail in capstone.h
+/// but with pointers and no unions. Because cyaml does not support them.
+typedef struct {
+	TestDetailAArch64 *aarch64;
+	TestDetailARM *arm;
+	TestDetailPPC *ppc;
+	TestDetailTriCore *tricore;
+	TestDetailAlpha *alpha;
+	TestDetailHPPA *hppa;
+	TestDetailBPF *bpf;
+	TestDetailSystemZ *systemz;
+	TestDetailSparc *sparc;
+	TestDetailXCore *xcore;
+	TestDetailSH *sh;
+	TestDetailMips *mips;
+	TestDetailRISCV *riscv;
+	TestDetailM680x *m680x;
+	TestDetailTMS320c64x *tms320c64x;
+	TestDetailMos65xx *mos65xx;
+	TestDetailEVM *evm;
+	TestDetailLoongArch *loongarch;
+	TestDetailWASM *wasm;
+	TestDetailX86 *x86;
+	TestDetailM68K *m68k;
+
+	char **regs_read;
+	uint8_t regs_read_count;
+
+	char **regs_write;
+	uint8_t regs_write_count;
+
+	// Implicit read/writes only
+	char **regs_impl_read;
+	uint8_t regs_impl_read_count;
+	char **regs_impl_write;
+	uint8_t regs_impl_write_count;
+
+	char **groups;
+	uint8_t groups_count;
+
+	tbool writeback;
+} TestDetail;
+
+static const cyaml_schema_value_t single_string_schema = {
+	CYAML_VALUE_STRING(CYAML_FLAG_POINTER, char, 0, CYAML_UNLIMITED),
+};
+
+static const cyaml_schema_field_t test_detail_mapping_schema[] = {
+	CYAML_FIELD_MAPPING_PTR(
+		"aarch64", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, TestDetail,
+		aarch64, test_detail_aarch64_mapping_schema),
+	CYAML_FIELD_MAPPING_PTR("arm", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+				TestDetail, arm,
+				test_detail_arm_mapping_schema),
+	CYAML_FIELD_MAPPING_PTR("ppc", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+				TestDetail, ppc,
+				test_detail_ppc_mapping_schema),
+	CYAML_FIELD_MAPPING_PTR(
+		"tricore", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, TestDetail,
+		tricore, test_detail_tricore_mapping_schema),
+	CYAML_FIELD_MAPPING_PTR(
+		"alpha", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, TestDetail,
+		alpha, test_detail_alpha_mapping_schema),
+	CYAML_FIELD_MAPPING_PTR(
+		"hppa", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, TestDetail,
+		hppa, test_detail_hppa_mapping_schema),
+	CYAML_FIELD_MAPPING_PTR("bpf", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+				TestDetail, bpf,
+				test_detail_bpf_mapping_schema),
+	CYAML_FIELD_MAPPING_PTR(
+		"systemz", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, TestDetail,
+		systemz, test_detail_systemz_mapping_schema),
+	CYAML_FIELD_MAPPING_PTR(
+		"sparc", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, TestDetail,
+		sparc, test_detail_sparc_mapping_schema),
+	CYAML_FIELD_MAPPING_PTR(
+		"xcore", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, TestDetail,
+		xcore, test_detail_xcore_mapping_schema),
+	CYAML_FIELD_MAPPING_PTR("sh", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+				TestDetail, sh, test_detail_sh_mapping_schema),
+	CYAML_FIELD_MAPPING_PTR(
+		"mips", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, TestDetail,
+		mips, test_detail_mips_mapping_schema),
+	CYAML_FIELD_MAPPING_PTR(
+		"riscv", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, TestDetail,
+		riscv, test_detail_riscv_mapping_schema),
+	CYAML_FIELD_MAPPING_PTR(
+		"m680x", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, TestDetail,
+		m680x, test_detail_m680x_mapping_schema),
+	CYAML_FIELD_MAPPING_PTR(
+		"tms320c64x", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+		TestDetail, tms320c64x, test_detail_tms320c64x_mapping_schema),
+	CYAML_FIELD_MAPPING_PTR(
+		"mos65xx", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, TestDetail,
+		mos65xx, test_detail_mos65xx_mapping_schema),
+	CYAML_FIELD_MAPPING_PTR("evm", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+				TestDetail, evm,
+				test_detail_evm_mapping_schema),
+	CYAML_FIELD_MAPPING_PTR(
+		"loongarch", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+		TestDetail, loongarch, test_detail_loongarch_mapping_schema),
+	CYAML_FIELD_MAPPING_PTR(
+		"wasm", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, TestDetail,
+		wasm, test_detail_wasm_mapping_schema),
+	CYAML_FIELD_MAPPING_PTR("x86", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+				TestDetail, x86,
+				test_detail_x86_mapping_schema),
+	CYAML_FIELD_MAPPING_PTR(
+		"m68k", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL, TestDetail,
+		m68k, test_detail_m68k_mapping_schema),
+	CYAML_FIELD_SEQUENCE("regs_read",
+			     CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			     TestDetail, regs_read, &single_string_schema, 0, 255),
+	CYAML_FIELD_SEQUENCE("regs_write",
+			     CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			     TestDetail, regs_write, &single_string_schema, 0, 255),
+	CYAML_FIELD_SEQUENCE(
+		"regs_impl_read", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+		TestDetail, regs_impl_read, &single_string_schema, 0, 255),
+	CYAML_FIELD_SEQUENCE(
+		"regs_impl_write", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+		TestDetail, regs_impl_write, &single_string_schema, 0, 255),
+	CYAML_FIELD_SEQUENCE("groups", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			     TestDetail, groups, &single_string_schema, 0, 255),
+	CYAML_FIELD_INT("writeback", CYAML_FLAG_OPTIONAL, TestDetail,
+			writeback),
+	CYAML_FIELD_END
+};
+
+TestDetail *test_detail_new();
+TestDetail *test_detail_clone(TestDetail *detail);
+void test_detail_free(TestDetail *detail);
+
+bool test_expected_detail(csh *handle, const cs_insn *insn,
+			  TestDetail *expected);
+
+#endif // TEST_DETAIL_H
diff --git a/suite/cstest/include/test_detail_aarch64.h b/suite/cstest/include/test_detail_aarch64.h
new file mode 100644
index 000000000..3df113c4d
--- /dev/null
+++ b/suite/cstest/include/test_detail_aarch64.h
@@ -0,0 +1,182 @@
+// Copyright © 2024 Rot127 <unisono@quyllur.org>
+// SPDX-License-Identifier: BSD-3
+
+#ifndef TEST_DETAIL_AARCH64_H
+#define TEST_DETAIL_AARCH64_H
+
+#include "test_compare.h"
+#include <cyaml/cyaml.h>
+#include <capstone/capstone.h>
+
+typedef struct {
+	char *type;
+	char *tile;
+	char *slice_reg;
+	int8_t slice_offset_imm;
+	int8_t slice_offset_ir_first;
+	int8_t slice_offset_ir_offset;
+	bool slice_offset_ir_set;
+	tbool has_range_offset;
+	tbool is_vertical;
+} TestDetailAArch64SME;
+
+static const cyaml_schema_field_t test_detail_aarch64_sme_mapping_schema[] = {
+	CYAML_FIELD_STRING_PTR("type", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			       TestDetailAArch64SME, type, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_STRING_PTR("tile", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			       TestDetailAArch64SME, tile, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_STRING_PTR(
+		"slice_reg", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+		TestDetailAArch64SME, slice_reg, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_INT("slice_offset_imm", CYAML_FLAG_OPTIONAL,
+			TestDetailAArch64SME, slice_offset_imm),
+	CYAML_FIELD_INT("slice_offset_ir_first", CYAML_FLAG_OPTIONAL,
+			TestDetailAArch64SME, slice_offset_ir_first),
+	CYAML_FIELD_INT("slice_offset_ir_offset", CYAML_FLAG_OPTIONAL,
+			TestDetailAArch64SME, slice_offset_ir_offset),
+	CYAML_FIELD_BOOL("slice_offset_ir_set", CYAML_FLAG_OPTIONAL,
+			TestDetailAArch64SME, slice_offset_ir_set),
+	CYAML_FIELD_INT("has_range_offset", CYAML_FLAG_OPTIONAL,
+			TestDetailAArch64SME, has_range_offset),
+	CYAML_FIELD_INT("is_vertical", CYAML_FLAG_OPTIONAL,
+			TestDetailAArch64SME, is_vertical),
+	CYAML_FIELD_END
+};
+
+typedef struct {
+	char *type;
+	char *sub_type;
+	char *access;
+
+	char *reg;
+	int64_t imm;
+	char *mem_base;
+	char *mem_index;
+	int32_t mem_disp;
+
+	int8_t imm_range_first;
+	int8_t imm_range_offset;
+	double fp;
+	uint64_t sys_raw_val;
+
+	TestDetailAArch64SME *sme;
+
+	char *pred_reg;
+	char *pred_vec_select;
+	int32_t pred_imm_index;
+	bool pred_imm_index_set;
+
+	char *shift_type;
+	uint32_t shift_value;
+	char *ext;
+
+	char *vas;
+	tbool is_vreg;
+	int vector_index;
+	bool vector_index_is_set;
+
+	tbool is_list_member;
+} TestDetailAArch64Op;
+
+static const cyaml_schema_field_t test_detail_aarch64_op_mapping_schema[] = {
+	CYAML_FIELD_STRING_PTR("type", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			       TestDetailAArch64Op, type, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_STRING_PTR(
+		"sub_type", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+		TestDetailAArch64Op, sub_type, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_STRING_PTR("access",
+			       CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			       TestDetailAArch64Op, access, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_STRING_PTR("reg", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			       TestDetailAArch64Op, reg, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_INT("imm", CYAML_FLAG_OPTIONAL, TestDetailAArch64Op, imm),
+	CYAML_FIELD_STRING_PTR(
+		"mem_base", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+		TestDetailAArch64Op, mem_base, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_STRING_PTR(
+		"mem_index", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+		TestDetailAArch64Op, mem_index, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_INT("mem_disp", CYAML_FLAG_OPTIONAL, TestDetailAArch64Op,
+			mem_disp),
+	CYAML_FIELD_INT("imm_range_first", CYAML_FLAG_OPTIONAL,
+			TestDetailAArch64Op, imm_range_first),
+	CYAML_FIELD_INT("imm_range_offset", CYAML_FLAG_OPTIONAL,
+			TestDetailAArch64Op, imm_range_offset),
+	CYAML_FIELD_FLOAT("fp", CYAML_FLAG_OPTIONAL, TestDetailAArch64Op, fp),
+	CYAML_FIELD_UINT("sys_raw_val", CYAML_FLAG_OPTIONAL,
+			 TestDetailAArch64Op, sys_raw_val),
+	CYAML_FIELD_MAPPING_PTR("sme", CYAML_FLAG_OPTIONAL, TestDetailAArch64Op,
+				sme, test_detail_aarch64_sme_mapping_schema),
+	CYAML_FIELD_STRING_PTR(
+		"pred_reg", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+		TestDetailAArch64Op, pred_reg, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_STRING_PTR(
+		"pred_vec_select", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+		TestDetailAArch64Op, pred_vec_select, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_INT("pred_imm_index", CYAML_FLAG_OPTIONAL,
+			TestDetailAArch64Op, pred_imm_index),
+	CYAML_FIELD_BOOL("pred_imm_index_set", CYAML_FLAG_OPTIONAL,
+			TestDetailAArch64Op, pred_imm_index_set),
+	CYAML_FIELD_STRING_PTR(
+		"shift_type", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+		TestDetailAArch64Op, shift_type, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_UINT("shift_value", CYAML_FLAG_OPTIONAL,
+			 TestDetailAArch64Op, shift_value),
+	CYAML_FIELD_STRING_PTR("ext", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			       TestDetailAArch64Op, ext, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_STRING_PTR("vas", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			       TestDetailAArch64Op, vas, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_INT("is_vreg", CYAML_FLAG_OPTIONAL, TestDetailAArch64Op,
+			is_vreg),
+	CYAML_FIELD_INT("vector_index", CYAML_FLAG_OPTIONAL,
+			TestDetailAArch64Op, vector_index),
+	CYAML_FIELD_BOOL("vector_index_is_set", CYAML_FLAG_OPTIONAL,
+			 TestDetailAArch64Op, vector_index_is_set),
+	CYAML_FIELD_INT("is_list_member", CYAML_FLAG_OPTIONAL,
+			TestDetailAArch64Op, is_list_member),
+	CYAML_FIELD_END
+};
+
+static const cyaml_schema_value_t test_detail_aarch64_op_schema = {
+	CYAML_VALUE_MAPPING(CYAML_FLAG_POINTER, TestDetailAArch64Op,
+			    test_detail_aarch64_op_mapping_schema),
+};
+
+typedef struct {
+	char *cc;
+	tbool update_flags;
+	tbool post_indexed;
+	TestDetailAArch64Op **operands;
+	uint32_t operands_count;
+} TestDetailAArch64;
+
+static const cyaml_schema_field_t test_detail_aarch64_mapping_schema[] = {
+	CYAML_FIELD_STRING_PTR("cc", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			       TestDetailAArch64, cc, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_INT("update_flags", CYAML_FLAG_OPTIONAL, TestDetailAArch64,
+			update_flags),
+	CYAML_FIELD_INT("post_indexed", CYAML_FLAG_OPTIONAL, TestDetailAArch64,
+			post_indexed),
+	CYAML_FIELD_SEQUENCE(
+		"operands", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+		TestDetailAArch64, operands, &test_detail_aarch64_op_schema, 0,
+		CYAML_UNLIMITED), // 0-MAX options
+	CYAML_FIELD_END
+};
+
+TestDetailAArch64 *test_detail_aarch64_new();
+TestDetailAArch64 *test_detail_aarch64_clone(TestDetailAArch64 *detail);
+void test_detail_aarch64_free(TestDetailAArch64 *detail);
+
+TestDetailAArch64Op *test_detail_aarch64_op_new();
+TestDetailAArch64Op *test_detail_aarch64_op_clone(TestDetailAArch64Op *detail);
+void test_detail_aarch64_op_free(TestDetailAArch64Op *detail);
+
+TestDetailAArch64SME *test_detail_aarch64_op_sme_new();
+TestDetailAArch64SME *test_detail_aarch64_op_sme_clone(TestDetailAArch64SME *sme);
+void test_detail_aarch64_op_sme_free(TestDetailAArch64SME *sme);
+
+bool test_expected_aarch64(csh *handle, cs_aarch64 *actual,
+			   TestDetailAArch64 *expected);
+
+#endif // TEST_DETAIL_AARCH64_H
diff --git a/suite/cstest/include/test_detail_alpha.h b/suite/cstest/include/test_detail_alpha.h
new file mode 100644
index 000000000..2b105c330
--- /dev/null
+++ b/suite/cstest/include/test_detail_alpha.h
@@ -0,0 +1,60 @@
+// Copyright © 2024 Rot127 <unisono@quyllur.org>
+// SPDX-License-Identifier: BSD-3
+
+#ifndef TEST_DETAIL_ALPHA_H
+#define TEST_DETAIL_ALPHA_H
+
+#include "test_compare.h"
+#include <cyaml/cyaml.h>
+#include <capstone/capstone.h>
+
+typedef struct {
+	char *type;
+	char *access;
+
+	char *reg;
+	int32_t imm;
+} TestDetailAlphaOp;
+
+static const cyaml_schema_field_t test_detail_alpha_op_mapping_schema[] = {
+	CYAML_FIELD_STRING_PTR("type", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			       TestDetailAlphaOp, type, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_STRING_PTR("access",
+			       CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			       TestDetailAlphaOp, access, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_STRING_PTR("reg", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			       TestDetailAlphaOp, reg, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_INT("imm", CYAML_FLAG_OPTIONAL, TestDetailAlphaOp, imm),
+	CYAML_FIELD_END
+};
+
+static const cyaml_schema_value_t test_detail_alpha_op_schema = {
+	CYAML_VALUE_MAPPING(CYAML_FLAG_POINTER, TestDetailAlphaOp,
+			    test_detail_alpha_op_mapping_schema),
+};
+
+typedef struct {
+	TestDetailAlphaOp **operands;
+	uint32_t operands_count;
+} TestDetailAlpha;
+
+static const cyaml_schema_field_t test_detail_alpha_mapping_schema[] = {
+	CYAML_FIELD_SEQUENCE(
+		"operands", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+		TestDetailAlpha, operands, &test_detail_alpha_op_schema, 0,
+		CYAML_UNLIMITED), // 0-MAX options
+	CYAML_FIELD_END
+};
+
+TestDetailAlpha *test_detail_alpha_new();
+TestDetailAlpha *test_detail_alpha_clone(const TestDetailAlpha *detail);
+void test_detail_alpha_free(TestDetailAlpha *detail);
+
+TestDetailAlphaOp *test_detail_alpha_op_new();
+TestDetailAlphaOp *test_detail_alpha_op_clone(const TestDetailAlphaOp *detail);
+void test_detail_alpha_op_free(TestDetailAlphaOp *detail);
+
+bool test_expected_alpha(csh *handle, const cs_alpha *actual,
+			 const TestDetailAlpha *expected);
+
+#endif // TEST_DETAIL_ALPHA_H
diff --git a/suite/cstest/include/test_detail_arm.h b/suite/cstest/include/test_detail_arm.h
new file mode 100644
index 000000000..5828258bb
--- /dev/null
+++ b/suite/cstest/include/test_detail_arm.h
@@ -0,0 +1,165 @@
+// Copyright © 2024 Rot127 <unisono@quyllur.org>
+// SPDX-License-Identifier: BSD-3
+
+#ifndef TEST_DETAIL_ARM_H
+#define TEST_DETAIL_ARM_H
+
+#include "test_compare.h"
+#include <cyaml/cyaml.h>
+#include <capstone/capstone.h>
+
+typedef struct {
+	char *type;
+	char *access;
+
+	char *reg;
+	int64_t imm;
+	char *setend;
+	int pred;
+	double fp;
+	char *mem_base;
+	char *mem_index;
+	int32_t mem_scale;
+	int32_t mem_disp;
+	uint32_t mem_align;
+	char *sys_reg;
+	char **sys_psr_bits;
+	uint32_t sys_psr_bits_count;
+	int sys_sysm;
+	int sys_msr_mask;
+
+	char *shift_type;
+	uint32_t shift_value;
+
+	int8_t neon_lane;
+	int vector_index;
+	bool vector_index_is_set;
+
+	tbool subtracted;
+} TestDetailARMOp;
+
+static const cyaml_schema_value_t test_detail_arm_op_sys_psr_schema = {
+	CYAML_VALUE_STRING(CYAML_FLAG_POINTER, char, 0, CYAML_UNLIMITED),
+};
+
+static const cyaml_schema_field_t test_detail_arm_op_mapping_schema[] = {
+	CYAML_FIELD_STRING_PTR("type", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			       TestDetailARMOp, type, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_STRING_PTR("access",
+			       CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			       TestDetailARMOp, access, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_STRING_PTR("reg", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			       TestDetailARMOp, reg, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_INT("imm", CYAML_FLAG_OPTIONAL, TestDetailARMOp, imm),
+	CYAML_FIELD_STRING_PTR("setend",
+			       CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			       TestDetailARMOp, setend, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_INT("pred", CYAML_FLAG_OPTIONAL, TestDetailARMOp, pred),
+	CYAML_FIELD_FLOAT("fp", CYAML_FLAG_OPTIONAL, TestDetailARMOp, fp),
+	CYAML_FIELD_STRING_PTR("mem_base",
+			       CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			       TestDetailARMOp, mem_base, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_STRING_PTR("mem_index",
+			       CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			       TestDetailARMOp, mem_index, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_INT("mem_disp", CYAML_FLAG_OPTIONAL, TestDetailARMOp,
+			mem_disp),
+	CYAML_FIELD_INT("mem_scale", CYAML_FLAG_OPTIONAL, TestDetailARMOp,
+			mem_scale),
+	CYAML_FIELD_UINT("mem_align", CYAML_FLAG_OPTIONAL, TestDetailARMOp,
+			 mem_align),
+	CYAML_FIELD_STRING_PTR("sys_reg",
+			       CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			       TestDetailARMOp, sys_reg, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_SEQUENCE(
+		"sys_psr_bits", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+		TestDetailARMOp, sys_psr_bits,
+		&test_detail_arm_op_sys_psr_schema, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_INT("sys_sysm", CYAML_FLAG_OPTIONAL, TestDetailARMOp,
+			sys_sysm),
+	CYAML_FIELD_INT("sys_msr_mask", CYAML_FLAG_OPTIONAL, TestDetailARMOp,
+			sys_msr_mask),
+	CYAML_FIELD_STRING_PTR("shift_type",
+			       CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			       TestDetailARMOp, shift_type, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_UINT("shift_value", CYAML_FLAG_OPTIONAL, TestDetailARMOp,
+			 shift_value),
+	CYAML_FIELD_INT("neon_lane", CYAML_FLAG_OPTIONAL, TestDetailARMOp,
+			neon_lane),
+	CYAML_FIELD_INT("vector_index", CYAML_FLAG_OPTIONAL, TestDetailARMOp,
+			vector_index),
+	CYAML_FIELD_BOOL("vector_index_is_set", CYAML_FLAG_OPTIONAL,
+			 TestDetailARMOp, vector_index_is_set),
+	CYAML_FIELD_INT("subtracted", CYAML_FLAG_OPTIONAL, TestDetailARMOp,
+			subtracted),
+	CYAML_FIELD_END
+};
+
+static const cyaml_schema_value_t test_detail_arm_op_schema = {
+	CYAML_VALUE_MAPPING(CYAML_FLAG_POINTER, TestDetailARMOp,
+			    test_detail_arm_op_mapping_schema),
+};
+
+typedef struct {
+	int vector_size;
+	char *vector_data;
+	char *cps_mode;
+	char *cps_flag;
+	char *cc;
+	char *vcc;
+	char *mem_barrier;
+	uint8_t pred_mask;
+
+	tbool usermode;
+	tbool update_flags;
+	tbool post_indexed;
+
+	TestDetailARMOp **operands;
+	uint32_t operands_count;
+} TestDetailARM;
+
+static const cyaml_schema_field_t test_detail_arm_mapping_schema[] = {
+	CYAML_FIELD_INT("vector_size", CYAML_FLAG_OPTIONAL, TestDetailARM,
+			vector_size),
+	CYAML_FIELD_STRING_PTR("vector_data",
+			       CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			       TestDetailARM, vector_data, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_STRING_PTR("cps_mode",
+			       CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			       TestDetailARM, cps_mode, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_STRING_PTR("cps_flag",
+			       CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			       TestDetailARM, cps_flag, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_STRING_PTR("cc", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			       TestDetailARM, cc, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_STRING_PTR("vcc", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			       TestDetailARM, vcc, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_STRING_PTR("mem_barrier",
+			       CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			       TestDetailARM, mem_barrier, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_UINT("pred_mask", CYAML_FLAG_OPTIONAL, TestDetailARM,
+			 pred_mask),
+	CYAML_FIELD_INT("usermode", CYAML_FLAG_OPTIONAL, TestDetailARM,
+			usermode),
+	CYAML_FIELD_INT("update_flags", CYAML_FLAG_OPTIONAL, TestDetailARM,
+			update_flags),
+	CYAML_FIELD_INT("post_indexed", CYAML_FLAG_OPTIONAL, TestDetailARM,
+			post_indexed),
+	CYAML_FIELD_SEQUENCE(
+		"operands", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+		TestDetailARM, operands, &test_detail_arm_op_schema, 0,
+		CYAML_UNLIMITED), // 0-MAX options
+	CYAML_FIELD_END
+};
+
+TestDetailARM *test_detail_arm_new();
+TestDetailARM *test_detail_arm_clone(TestDetailARM *detail);
+void test_detail_arm_free(TestDetailARM *detail);
+
+TestDetailARMOp *test_detail_arm_op_new();
+TestDetailARMOp *test_detail_arm_op_clone(TestDetailARMOp *detail);
+void test_detail_arm_op_free(TestDetailARMOp *detail);
+
+bool test_expected_arm(csh *handle, cs_arm *actual, TestDetailARM *expected);
+
+#endif // TEST_DETAIL_ARM_H
diff --git a/suite/cstest/include/test_detail_bpf.h b/suite/cstest/include/test_detail_bpf.h
new file mode 100644
index 000000000..2dd3658d5
--- /dev/null
+++ b/suite/cstest/include/test_detail_bpf.h
@@ -0,0 +1,76 @@
+// Copyright © 2024 Rot127 <unisono@quyllur.org>
+// SPDX-License-Identifier: BSD-3
+
+#ifndef TEST_DETAIL_BPF_H
+#define TEST_DETAIL_BPF_H
+
+#include "test_compare.h"
+#include <cyaml/cyaml.h>
+#include <capstone/capstone.h>
+
+typedef struct {
+	char *type;
+	char *access;
+
+	char *reg;
+	uint64_t imm;
+	uint32_t off;
+	uint32_t mmem;
+	uint32_t msh;
+	char *ext;
+	char *mem_base;
+	uint32_t mem_disp;
+} TestDetailBPFOp;
+
+static const cyaml_schema_field_t test_detail_bpf_op_mapping_schema[] = {
+	CYAML_FIELD_STRING_PTR("type", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			       TestDetailBPFOp, type, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_STRING_PTR("access",
+			       CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			       TestDetailBPFOp, access, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_STRING_PTR("reg", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			       TestDetailBPFOp, reg, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_INT("imm", CYAML_FLAG_OPTIONAL, TestDetailBPFOp, imm),
+	CYAML_FIELD_INT("off", CYAML_FLAG_OPTIONAL, TestDetailBPFOp, off),
+	CYAML_FIELD_INT("mmem", CYAML_FLAG_OPTIONAL, TestDetailBPFOp, mmem),
+	CYAML_FIELD_INT("msh", CYAML_FLAG_OPTIONAL, TestDetailBPFOp, msh),
+	CYAML_FIELD_STRING_PTR("ext", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			       TestDetailBPFOp, ext, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_STRING_PTR("mem_base",
+			       CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			       TestDetailBPFOp, mem_base, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_INT("mem_disp", CYAML_FLAG_OPTIONAL, TestDetailBPFOp,
+			mem_disp),
+	CYAML_FIELD_END
+};
+
+static const cyaml_schema_value_t test_detail_bpf_op_schema = {
+	CYAML_VALUE_MAPPING(CYAML_FLAG_POINTER, TestDetailBPFOp,
+			    test_detail_bpf_op_mapping_schema),
+};
+
+typedef struct {
+	TestDetailBPFOp **operands;
+	uint32_t operands_count;
+} TestDetailBPF;
+
+static const cyaml_schema_field_t test_detail_bpf_mapping_schema[] = {
+	CYAML_FIELD_SEQUENCE(
+		"operands", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+		TestDetailBPF, operands, &test_detail_bpf_op_schema, 0,
+		CYAML_UNLIMITED), // 0-MAX options
+	CYAML_FIELD_END
+};
+
+TestDetailBPF *test_detail_bpf_new();
+TestDetailBPF *test_detail_bpf_clone(const TestDetailBPF *detail);
+void test_detail_bpf_free(TestDetailBPF *detail);
+
+TestDetailBPFOp *test_detail_bpf_op_new();
+TestDetailBPFOp *test_detail_bpf_op_clone(const TestDetailBPFOp *detail);
+void test_detail_bpf_op_free(TestDetailBPFOp *detail);
+
+bool test_expected_bpf(csh *handle, const cs_bpf *actual,
+		       const TestDetailBPF *expected);
+
+#endif // TEST_DETAIL_BPF_H
diff --git a/suite/cstest/include/test_detail_evm.h b/suite/cstest/include/test_detail_evm.h
new file mode 100644
index 000000000..e6c8a59d6
--- /dev/null
+++ b/suite/cstest/include/test_detail_evm.h
@@ -0,0 +1,30 @@
+// Copyright © 2024 Rot127 <unisono@quyllur.org>
+// SPDX-License-Identifier: BSD-3
+
+#ifndef TEST_DETAIL_EVM_H
+#define TEST_DETAIL_EVM_H
+
+#include <cyaml/cyaml.h>
+#include <capstone/capstone.h>
+
+typedef struct {
+	unsigned char pop;
+	unsigned char push;
+	unsigned int fee;
+} TestDetailEVM;
+
+static const cyaml_schema_field_t test_detail_evm_mapping_schema[] = {
+	CYAML_FIELD_UINT("pop", CYAML_FLAG_OPTIONAL, TestDetailEVM, pop),
+	CYAML_FIELD_UINT("push", CYAML_FLAG_OPTIONAL, TestDetailEVM, push),
+	CYAML_FIELD_UINT("fee", CYAML_FLAG_OPTIONAL, TestDetailEVM, fee),
+	CYAML_FIELD_END
+};
+
+TestDetailEVM *test_detail_evm_new();
+TestDetailEVM *test_detail_evm_clone(const TestDetailEVM *detail);
+void test_detail_evm_free(TestDetailEVM *detail);
+
+bool test_expected_evm(csh *handle, const cs_evm *actual,
+		       const TestDetailEVM *expected);
+
+#endif // TEST_DETAIL_EVM_H
diff --git a/suite/cstest/include/test_detail_hppa.h b/suite/cstest/include/test_detail_hppa.h
new file mode 100644
index 000000000..83a95027d
--- /dev/null
+++ b/suite/cstest/include/test_detail_hppa.h
@@ -0,0 +1,72 @@
+// Copyright © 2024 Rot127 <unisono@quyllur.org>
+// SPDX-License-Identifier: BSD-3
+
+#ifndef TEST_DETAIL_HPPA_H
+#define TEST_DETAIL_HPPA_H
+
+#include "test_compare.h"
+#include <cyaml/cyaml.h>
+#include <capstone/capstone.h>
+
+typedef struct {
+	char *type;
+	char *access;
+
+	char *reg;
+	int64_t imm;
+	char *mem_base;
+	char *mem_space;
+	char *mem_base_access;
+} TestDetailHPPAOp;
+
+static const cyaml_schema_field_t test_detail_hppa_op_mapping_schema[] = {
+	CYAML_FIELD_STRING_PTR("type", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			       TestDetailHPPAOp, type, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_STRING_PTR("access",
+			       CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			       TestDetailHPPAOp, access, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_STRING_PTR("reg", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			       TestDetailHPPAOp, reg, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_INT("imm", CYAML_FLAG_OPTIONAL, TestDetailHPPAOp, imm),
+	CYAML_FIELD_STRING_PTR("mem_base",
+			       CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			       TestDetailHPPAOp, mem_base, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_STRING_PTR("mem_space",
+			       CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			       TestDetailHPPAOp, mem_space, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_STRING_PTR(
+		"mem_base_access", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+		TestDetailHPPAOp, mem_base_access, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_END
+};
+
+static const cyaml_schema_value_t test_detail_hppa_op_schema = {
+	CYAML_VALUE_MAPPING(CYAML_FLAG_POINTER, TestDetailHPPAOp,
+			    test_detail_hppa_op_mapping_schema),
+};
+
+typedef struct {
+	TestDetailHPPAOp **operands;
+	uint32_t operands_count;
+} TestDetailHPPA;
+
+static const cyaml_schema_field_t test_detail_hppa_mapping_schema[] = {
+	CYAML_FIELD_SEQUENCE(
+		"operands", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+		TestDetailHPPA, operands, &test_detail_hppa_op_schema, 0,
+		CYAML_UNLIMITED), // 0-MAX options
+	CYAML_FIELD_END
+};
+
+TestDetailHPPA *test_detail_hppa_new();
+TestDetailHPPA *test_detail_hppa_clone(const TestDetailHPPA *detail);
+void test_detail_hppa_free(TestDetailHPPA *detail);
+
+TestDetailHPPAOp *test_detail_hppa_op_new();
+TestDetailHPPAOp *test_detail_hppa_op_clone(const TestDetailHPPAOp *detail);
+void test_detail_hppa_op_free(TestDetailHPPAOp *detail);
+
+bool test_expected_hppa(csh *handle, const cs_hppa *actual,
+			const TestDetailHPPA *expected);
+
+#endif // TEST_DETAIL_HPPA_H
diff --git a/suite/cstest/include/test_detail_loongarch.h b/suite/cstest/include/test_detail_loongarch.h
new file mode 100644
index 000000000..204220059
--- /dev/null
+++ b/suite/cstest/include/test_detail_loongarch.h
@@ -0,0 +1,77 @@
+// Copyright © 2024 Rot127 <unisono@quyllur.org>
+// SPDX-License-Identifier: BSD-3
+
+#ifndef TEST_DETAIL_LOONGARCH_H
+#define TEST_DETAIL_LOONGARCH_H
+
+#include <cyaml/cyaml.h>
+#include <capstone/capstone.h>
+
+typedef struct {
+	char *type;
+	char *access;
+
+	char *reg;
+	uint64_t imm;
+	char *mem_base;
+	char *mem_index;
+	int64_t mem_disp;
+} TestDetailLoongArchOp;
+
+static const cyaml_schema_field_t test_detail_loongarch_op_mapping_schema[] = {
+	CYAML_FIELD_STRING_PTR("type", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			       TestDetailLoongArchOp, type, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_STRING_PTR(
+		"access", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+		TestDetailLoongArchOp, access, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_STRING_PTR("reg", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			       TestDetailLoongArchOp, reg, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_INT("imm", CYAML_FLAG_OPTIONAL, TestDetailLoongArchOp, imm),
+	CYAML_FIELD_STRING_PTR(
+		"mem_base", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+		TestDetailLoongArchOp, mem_base, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_STRING_PTR(
+		"mem_index", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+		TestDetailLoongArchOp, mem_index, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_INT("mem_disp", CYAML_FLAG_OPTIONAL, TestDetailLoongArchOp,
+			mem_disp),
+	CYAML_FIELD_END
+};
+
+static const cyaml_schema_value_t test_detail_loongarch_op_schema = {
+	CYAML_VALUE_MAPPING(CYAML_FLAG_POINTER, TestDetailLoongArchOp,
+			    test_detail_loongarch_op_mapping_schema),
+};
+
+typedef struct {
+	char *format;
+	TestDetailLoongArchOp **operands;
+	uint32_t operands_count;
+} TestDetailLoongArch;
+
+static const cyaml_schema_field_t test_detail_loongarch_mapping_schema[] = {
+	CYAML_FIELD_STRING_PTR("format",
+			       CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			       TestDetailLoongArch, format, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_SEQUENCE("operands",
+			     CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			     TestDetailLoongArch, operands,
+			     &test_detail_loongarch_op_schema, 0,
+			     CYAML_UNLIMITED), // 0-MAX options
+	CYAML_FIELD_END
+};
+
+TestDetailLoongArch *test_detail_loongarch_new();
+TestDetailLoongArch *
+test_detail_loongarch_clone(const TestDetailLoongArch *detail);
+void test_detail_loongarch_free(TestDetailLoongArch *detail);
+
+TestDetailLoongArchOp *test_detail_loongarch_op_new();
+TestDetailLoongArchOp *
+test_detail_loongarch_op_clone(const TestDetailLoongArchOp *detail);
+void test_detail_loongarch_op_free(TestDetailLoongArchOp *detail);
+
+bool test_expected_loongarch(csh *handle, const cs_loongarch *actual,
+			     const TestDetailLoongArch *expected);
+
+#endif // TEST_DETAIL_LOONGARCH_H
diff --git a/suite/cstest/include/test_detail_m680x.h b/suite/cstest/include/test_detail_m680x.h
new file mode 100644
index 000000000..c68054a8a
--- /dev/null
+++ b/suite/cstest/include/test_detail_m680x.h
@@ -0,0 +1,133 @@
+// Copyright © 2024 Rot127 <unisono@quyllur.org>
+// SPDX-License-Identifier: BSD-3
+
+#ifndef TEST_DETAIL_M680X_H
+#define TEST_DETAIL_M680X_H
+
+#include "test_compare.h"
+#include <cyaml/cyaml.h>
+#include <capstone/capstone.h>
+
+typedef struct {
+	char *base_reg;
+	char *offset_reg;
+	int16_t offset;
+	uint16_t offset_addr;
+	uint8_t offset_bits;
+	int8_t inc_dec;
+	char **flags;
+	uint32_t flags_count;
+} TestDetailM680xIdx;
+
+static const cyaml_schema_value_t flag_schema = {
+	CYAML_VALUE_STRING(CYAML_FLAG_POINTER, char, 0, CYAML_UNLIMITED),
+};
+
+static const cyaml_schema_field_t test_detail_m680x_idx_mapping_schema[] = {
+	CYAML_FIELD_STRING_PTR(
+		"base_reg", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+		TestDetailM680xIdx, base_reg, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_STRING_PTR(
+		"offset_reg", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+		TestDetailM680xIdx, offset_reg, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_INT("offset", CYAML_FLAG_OPTIONAL, TestDetailM680xIdx,
+			offset),
+	CYAML_FIELD_UINT("offset_addr", CYAML_FLAG_OPTIONAL, TestDetailM680xIdx,
+			offset_addr),
+	CYAML_FIELD_UINT("offset_bits", CYAML_FLAG_OPTIONAL, TestDetailM680xIdx,
+			offset_bits),
+	CYAML_FIELD_INT("inc_dec", CYAML_FLAG_OPTIONAL, TestDetailM680xIdx,
+			inc_dec),
+	CYAML_FIELD_SEQUENCE("flags", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			     TestDetailM680xIdx, flags, &flag_schema, 0,
+			     CYAML_UNLIMITED), // 0-MAX flags
+	CYAML_FIELD_END
+};
+
+typedef struct {
+	char *type;
+	char *access;
+
+	TestDetailM680xIdx *idx;
+	char *reg;
+	int32_t imm;
+	uint16_t rel_address;
+	uint16_t ext_address;
+	int16_t rel_offset;
+	tbool ext_indirect;
+	uint8_t direct_addr;
+	bool direct_addr_set;
+	uint8_t const_val;
+	uint8_t size;
+} TestDetailM680xOp;
+
+static const cyaml_schema_field_t test_detail_m680x_op_mapping_schema[] = {
+	CYAML_FIELD_STRING_PTR("type", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			       TestDetailM680xOp, type, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_STRING_PTR("access",
+			       CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			       TestDetailM680xOp, access, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_MAPPING_PTR("idx", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+				TestDetailM680xOp, idx,
+				test_detail_m680x_idx_mapping_schema),
+	CYAML_FIELD_STRING_PTR("reg", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			       TestDetailM680xOp, reg, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_INT("imm", CYAML_FLAG_OPTIONAL, TestDetailM680xOp, imm),
+	CYAML_FIELD_UINT("rel_address", CYAML_FLAG_OPTIONAL, TestDetailM680xOp,
+			 rel_address),
+	CYAML_FIELD_UINT("ext_address", CYAML_FLAG_OPTIONAL, TestDetailM680xOp,
+			 ext_address),
+	CYAML_FIELD_INT("rel_offset", CYAML_FLAG_OPTIONAL, TestDetailM680xOp,
+			rel_offset),
+	CYAML_FIELD_INT("ext_indirect", CYAML_FLAG_OPTIONAL, TestDetailM680xOp,
+			ext_indirect),
+	CYAML_FIELD_UINT("direct_addr", CYAML_FLAG_OPTIONAL, TestDetailM680xOp,
+			 direct_addr),
+	CYAML_FIELD_BOOL("direct_addr_set", CYAML_FLAG_OPTIONAL,
+			 TestDetailM680xOp, direct_addr_set),
+	CYAML_FIELD_UINT("const_val", CYAML_FLAG_OPTIONAL, TestDetailM680xOp,
+			 const_val),
+	CYAML_FIELD_UINT("size", CYAML_FLAG_OPTIONAL, TestDetailM680xOp, size),
+	CYAML_FIELD_END
+};
+
+static const cyaml_schema_value_t test_detail_m680x_op_schema = {
+	CYAML_VALUE_MAPPING(CYAML_FLAG_POINTER, TestDetailM680xOp,
+			    test_detail_m680x_op_mapping_schema),
+};
+
+typedef struct {
+	char **flags;
+	size_t flags_count;
+	TestDetailM680xOp **operands;
+	uint32_t operands_count;
+} TestDetailM680x;
+
+static const cyaml_schema_field_t test_detail_m680x_mapping_schema[] = {
+	CYAML_FIELD_SEQUENCE("flags", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			     TestDetailM680x, flags, &flag_schema, 0,
+			     CYAML_UNLIMITED), // 0-MAX flags
+	CYAML_FIELD_SEQUENCE(
+		"operands", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+		TestDetailM680x, operands, &test_detail_m680x_op_schema, 0,
+		CYAML_UNLIMITED), // 0-MAX options
+	CYAML_FIELD_END
+};
+
+TestDetailM680x *test_detail_m680x_new();
+TestDetailM680x *test_detail_m680x_clone(const TestDetailM680x *detail);
+void test_detail_m680x_free(TestDetailM680x *detail);
+
+TestDetailM680xOp *test_detail_m680x_op_new();
+TestDetailM680xOp *test_detail_m680x_op_clone(const TestDetailM680xOp *detail);
+void test_detail_m680x_op_free(TestDetailM680xOp *detail);
+
+TestDetailM680xIdx *test_detail_m680x_idx_new();
+TestDetailM680xIdx *
+test_detail_m680x_idx_clone(const TestDetailM680xIdx *detail);
+void test_detail_m680x_idx_free(TestDetailM680xIdx *detail);
+
+bool test_expected_m680x(csh *handle, const cs_m680x *actual,
+			 const TestDetailM680x *expected);
+
+#endif // TEST_DETAIL_M680X_H
diff --git a/suite/cstest/include/test_detail_m68k.h b/suite/cstest/include/test_detail_m68k.h
new file mode 100644
index 000000000..78fd1a18c
--- /dev/null
+++ b/suite/cstest/include/test_detail_m68k.h
@@ -0,0 +1,151 @@
+// Copyright © 2024 Rot127 <unisono@quyllur.org>
+// SPDX-License-Identifier: BSD-3
+
+#ifndef TEST_DETAIL_M68K_H
+#define TEST_DETAIL_M68K_H
+
+#include "test_compare.h"
+#include <cyaml/cyaml.h>
+#include <capstone/capstone.h>
+
+typedef struct {
+	char *base_reg;
+	char *index_reg;
+	char *in_base_reg;
+	tbool index_size; // -1 == word, 1 == long
+	int16_t disp;
+	uint32_t in_disp;
+	uint32_t out_disp;
+	uint8_t scale;
+	uint8_t bitfield;
+	uint8_t width;
+	uint8_t offset;
+} TestDetailM68KOpMem;
+
+static const cyaml_schema_field_t test_detail_m68k_op_mem_mapping_schema[] = {
+	CYAML_FIELD_INT("disp", CYAML_FLAG_OPTIONAL, TestDetailM68KOpMem, disp),
+	CYAML_FIELD_STRING_PTR(
+		"base_reg", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+		TestDetailM68KOpMem, base_reg, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_STRING_PTR(
+		"index_reg", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+		TestDetailM68KOpMem, index_reg, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_STRING_PTR(
+		"in_base_reg", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+		TestDetailM68KOpMem, in_base_reg, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_INT("index_size", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			TestDetailM68KOpMem, index_size),
+	CYAML_FIELD_INT("disp", CYAML_FLAG_OPTIONAL, TestDetailM68KOpMem, disp),
+	CYAML_FIELD_UINT("in_disp", CYAML_FLAG_OPTIONAL, TestDetailM68KOpMem,
+			 in_disp),
+	CYAML_FIELD_UINT("out_disp", CYAML_FLAG_OPTIONAL, TestDetailM68KOpMem,
+			 out_disp),
+	CYAML_FIELD_UINT("scale", CYAML_FLAG_OPTIONAL, TestDetailM68KOpMem,
+			 scale),
+	CYAML_FIELD_UINT("bitfield", CYAML_FLAG_OPTIONAL, TestDetailM68KOpMem,
+			 bitfield),
+	CYAML_FIELD_UINT("width", CYAML_FLAG_OPTIONAL, TestDetailM68KOpMem,
+			 width),
+	CYAML_FIELD_UINT("offset", CYAML_FLAG_OPTIONAL, TestDetailM68KOpMem,
+			 offset),
+	CYAML_FIELD_END
+};
+
+typedef struct {
+	char *type;
+	char *address_mode;
+
+	char *reg;
+	char *reg_pair_0;
+	char *reg_pair_1;
+
+	uint64_t imm;
+	int32_t br_disp;
+	uint8_t br_disp_size;
+
+	uint32_t register_bits;
+
+	double dimm;
+	float simm;
+
+	TestDetailM68KOpMem *mem;
+} TestDetailM68KOp;
+
+static const cyaml_schema_value_t test_detail_m68k_op_sys_psr_schema = {
+	CYAML_VALUE_STRING(CYAML_FLAG_POINTER, char, 0, CYAML_UNLIMITED),
+};
+
+static const cyaml_schema_field_t test_detail_m68k_op_mapping_schema[] = {
+	CYAML_FIELD_STRING_PTR("type", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			       TestDetailM68KOp, type, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_STRING_PTR(
+		"address_mode", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+		TestDetailM68KOp, address_mode, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_STRING_PTR("reg", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			       TestDetailM68KOp, reg, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_STRING_PTR(
+		"reg_pair_0", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+		TestDetailM68KOp, reg_pair_0, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_STRING_PTR(
+		"reg_pair_1", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+		TestDetailM68KOp, reg_pair_1, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_INT("imm", CYAML_FLAG_OPTIONAL, TestDetailM68KOp, imm),
+	CYAML_FIELD_INT("br_disp", CYAML_FLAG_OPTIONAL, TestDetailM68KOp,
+			br_disp),
+	CYAML_FIELD_UINT("br_disp_size", CYAML_FLAG_OPTIONAL, TestDetailM68KOp,
+			 br_disp_size),
+	CYAML_FIELD_UINT("register_bits", CYAML_FLAG_OPTIONAL, TestDetailM68KOp,
+			 register_bits),
+	CYAML_FIELD_FLOAT("dimm", CYAML_FLAG_OPTIONAL, TestDetailM68KOp, dimm),
+	CYAML_FIELD_FLOAT("simm", CYAML_FLAG_OPTIONAL, TestDetailM68KOp, simm),
+	CYAML_FIELD_MAPPING_PTR("mem", CYAML_FLAG_OPTIONAL, TestDetailM68KOp,
+				mem, test_detail_m68k_op_mem_mapping_schema),
+	CYAML_FIELD_END
+};
+
+static const cyaml_schema_value_t test_detail_m68k_op_schema = {
+	CYAML_VALUE_MAPPING(CYAML_FLAG_POINTER, TestDetailM68KOp,
+			    test_detail_m68k_op_mapping_schema),
+};
+
+typedef struct {
+	char *op_size_type;
+	char *op_size_fpu;
+	char *op_size_cpu;
+
+	TestDetailM68KOp **operands;
+	uint32_t operands_count;
+} TestDetailM68K;
+
+static const cyaml_schema_field_t test_detail_m68k_mapping_schema[] = {
+	CYAML_FIELD_STRING_PTR(
+		"op_size_type", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+		TestDetailM68K, op_size_type, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_STRING_PTR("op_size_fpu",
+			       CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			       TestDetailM68K, op_size_fpu, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_STRING_PTR("op_size_cpu",
+			       CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			       TestDetailM68K, op_size_cpu, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_SEQUENCE(
+		"operands", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+		TestDetailM68K, operands, &test_detail_m68k_op_schema, 0,
+		CYAML_UNLIMITED), // 0-MAX options
+	CYAML_FIELD_END
+};
+
+TestDetailM68K *test_detail_m68k_new();
+TestDetailM68K *test_detail_m68k_clone(TestDetailM68K *detail);
+void test_detail_m68k_free(TestDetailM68K *detail);
+
+TestDetailM68KOp *test_detail_m68k_op_new();
+TestDetailM68KOp *test_detail_m68k_op_clone(TestDetailM68KOp *detail);
+void test_detail_m68k_op_free(TestDetailM68KOp *detail);
+
+TestDetailM68KOpMem *test_detail_m68k_op_mem_new();
+TestDetailM68KOpMem *test_detail_m68k_op_mem_clone(TestDetailM68KOpMem *detail);
+void test_detail_m68k_op_mem_free(TestDetailM68KOpMem *detail);
+
+bool test_expected_m68k(csh *handle, cs_m68k *actual, TestDetailM68K *expected);
+
+#endif // TEST_DETAIL_M68K_H
diff --git a/suite/cstest/include/test_detail_mips.h b/suite/cstest/include/test_detail_mips.h
new file mode 100644
index 000000000..c5491e346
--- /dev/null
+++ b/suite/cstest/include/test_detail_mips.h
@@ -0,0 +1,63 @@
+// Copyright © 2024 Rot127 <unisono@quyllur.org>
+// SPDX-License-Identifier: BSD-3
+
+#ifndef TEST_DETAIL_MIPS_H
+#define TEST_DETAIL_MIPS_H
+
+#include "test_compare.h"
+#include <cyaml/cyaml.h>
+#include <capstone/capstone.h>
+
+typedef struct {
+	char *type;
+
+	char *reg;
+	uint64_t imm;
+	char *mem_base;
+	int64_t mem_disp;
+} TestDetailMipsOp;
+
+static const cyaml_schema_field_t test_detail_mips_op_mapping_schema[] = {
+	CYAML_FIELD_STRING_PTR("type", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			       TestDetailMipsOp, type, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_STRING_PTR("reg", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			       TestDetailMipsOp, reg, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_INT("imm", CYAML_FLAG_OPTIONAL, TestDetailMipsOp, imm),
+	CYAML_FIELD_STRING_PTR("mem_base",
+			       CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			       TestDetailMipsOp, mem_base, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_INT("mem_disp", CYAML_FLAG_OPTIONAL, TestDetailMipsOp,
+			mem_disp),
+	CYAML_FIELD_END
+};
+
+static const cyaml_schema_value_t test_detail_mips_op_schema = {
+	CYAML_VALUE_MAPPING(CYAML_FLAG_POINTER, TestDetailMipsOp,
+			    test_detail_mips_op_mapping_schema),
+};
+
+typedef struct {
+	TestDetailMipsOp **operands;
+	uint32_t operands_count;
+} TestDetailMips;
+
+static const cyaml_schema_field_t test_detail_mips_mapping_schema[] = {
+	CYAML_FIELD_SEQUENCE(
+		"operands", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+		TestDetailMips, operands, &test_detail_mips_op_schema, 0,
+		CYAML_UNLIMITED), // 0-MAX options
+	CYAML_FIELD_END
+};
+
+TestDetailMips *test_detail_mips_new();
+TestDetailMips *test_detail_mips_clone(const TestDetailMips *detail);
+void test_detail_mips_free(TestDetailMips *detail);
+
+TestDetailMipsOp *test_detail_mips_op_new();
+TestDetailMipsOp *test_detail_mips_op_clone(const TestDetailMipsOp *detail);
+void test_detail_mips_op_free(TestDetailMipsOp *detail);
+
+bool test_expected_mips(csh *handle, const cs_mips *actual,
+			const TestDetailMips *expected);
+
+#endif // TEST_DETAIL_MIPS_H
diff --git a/suite/cstest/include/test_detail_mos65xx.h b/suite/cstest/include/test_detail_mos65xx.h
new file mode 100644
index 000000000..f18fe030a
--- /dev/null
+++ b/suite/cstest/include/test_detail_mos65xx.h
@@ -0,0 +1,66 @@
+// Copyright © 2024 Rot127 <unisono@quyllur.org>
+// SPDX-License-Identifier: BSD-3
+
+#ifndef TEST_DETAIL_MOS65XX_H
+#define TEST_DETAIL_MOS65XX_H
+
+#include "test_compare.h"
+#include <cyaml/cyaml.h>
+#include <capstone/capstone.h>
+
+typedef struct {
+	char *type;
+
+	char *reg;
+	uint16_t imm;
+	uint32_t mem;
+} TestDetailMos65xxOp;
+
+static const cyaml_schema_field_t test_detail_mos65xx_op_mapping_schema[] = {
+	CYAML_FIELD_STRING_PTR("type", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			       TestDetailMos65xxOp, type, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_STRING_PTR("reg", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			       TestDetailMos65xxOp, reg, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_UINT("imm", CYAML_FLAG_OPTIONAL, TestDetailMos65xxOp, imm),
+	CYAML_FIELD_UINT("mem", CYAML_FLAG_OPTIONAL, TestDetailMos65xxOp, mem),
+	CYAML_FIELD_END
+};
+
+static const cyaml_schema_value_t test_detail_mos65xx_op_schema = {
+	CYAML_VALUE_MAPPING(CYAML_FLAG_POINTER, TestDetailMos65xxOp,
+			    test_detail_mos65xx_op_mapping_schema),
+};
+
+typedef struct {
+	char *am;
+	tbool modifies_flags;
+
+	TestDetailMos65xxOp **operands;
+	uint32_t operands_count;
+} TestDetailMos65xx;
+
+static const cyaml_schema_field_t test_detail_mos65xx_mapping_schema[] = {
+	CYAML_FIELD_STRING_PTR("am", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			       TestDetailMos65xx, am, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_INT("modifies_flags", CYAML_FLAG_OPTIONAL,
+			TestDetailMos65xx, modifies_flags),
+	CYAML_FIELD_SEQUENCE(
+		"operands", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+		TestDetailMos65xx, operands, &test_detail_mos65xx_op_schema, 0,
+		CYAML_UNLIMITED), // 0-MAX options
+	CYAML_FIELD_END
+};
+
+TestDetailMos65xx *test_detail_mos65xx_new();
+TestDetailMos65xx *test_detail_mos65xx_clone(const TestDetailMos65xx *detail);
+void test_detail_mos65xx_free(TestDetailMos65xx *detail);
+
+TestDetailMos65xxOp *test_detail_mos65xx_op_new();
+TestDetailMos65xxOp *
+test_detail_mos65xx_op_clone(const TestDetailMos65xxOp *detail);
+void test_detail_mos65xx_op_free(TestDetailMos65xxOp *detail);
+
+bool test_expected_mos65xx(csh *handle, const cs_mos65xx *actual,
+			   const TestDetailMos65xx *expected);
+
+#endif // TEST_DETAIL_MOS65XX_H
diff --git a/suite/cstest/include/test_detail_ppc.h b/suite/cstest/include/test_detail_ppc.h
new file mode 100644
index 000000000..1c242a029
--- /dev/null
+++ b/suite/cstest/include/test_detail_ppc.h
@@ -0,0 +1,124 @@
+// Copyright © 2024 Rot127 <unisono@quyllur.org>
+// SPDX-License-Identifier: BSD-3
+
+#ifndef TEST_DETAIL_PPC_H
+#define TEST_DETAIL_PPC_H
+
+#include "test_compare.h"
+#include <cyaml/cyaml.h>
+#include <capstone/capstone.h>
+
+typedef struct {
+	char *type;
+	char *access;
+
+	char *reg;
+	int64_t imm;
+	char *mem_base;
+	char *mem_offset;
+	int32_t mem_disp;
+} TestDetailPPCOp;
+
+static const cyaml_schema_field_t test_detail_ppc_op_mapping_schema[] = {
+	CYAML_FIELD_STRING_PTR("type", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			       TestDetailPPCOp, type, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_STRING_PTR("access",
+			       CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			       TestDetailPPCOp, access, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_STRING_PTR("reg", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			       TestDetailPPCOp, reg, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_INT("imm", CYAML_FLAG_OPTIONAL, TestDetailPPCOp, imm),
+	CYAML_FIELD_STRING_PTR("mem_base",
+			       CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			       TestDetailPPCOp, mem_base, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_STRING_PTR("mem_offset",
+			       CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			       TestDetailPPCOp, mem_offset, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_INT("mem_disp", CYAML_FLAG_OPTIONAL, TestDetailPPCOp,
+			mem_disp),
+	CYAML_FIELD_END
+};
+
+static const cyaml_schema_value_t test_detail_ppc_op_schema = {
+	CYAML_VALUE_MAPPING(CYAML_FLAG_POINTER, TestDetailPPCOp,
+			    test_detail_ppc_op_mapping_schema),
+};
+
+typedef struct {
+	uint8_t bo;
+	bool bo_set;
+	uint8_t bi;
+	bool bi_set;
+
+	char *crX_bit;
+	char *crX;
+	char *hint;
+	char *pred_cr;
+	char *pred_ctr;
+	char *bh;
+} TestDetailPPCBC;
+
+static const cyaml_schema_field_t test_detail_ppc_bc_mapping_schema[] = {
+	CYAML_FIELD_INT("bi", CYAML_FLAG_OPTIONAL, TestDetailPPCBC, bi),
+	CYAML_FIELD_BOOL("bi_set", CYAML_FLAG_OPTIONAL, TestDetailPPCBC,
+			 bi_set),
+	CYAML_FIELD_INT("bo", CYAML_FLAG_OPTIONAL, TestDetailPPCBC, bo),
+	CYAML_FIELD_BOOL("bo_set", CYAML_FLAG_OPTIONAL, TestDetailPPCBC,
+			 bo_set),
+	CYAML_FIELD_STRING_PTR("crX_bit",
+			       CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			       TestDetailPPCBC, crX_bit, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_STRING_PTR("crX", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			       TestDetailPPCBC, crX, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_STRING_PTR("hint", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			       TestDetailPPCBC, hint, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_STRING_PTR("pred_cr",
+			       CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			       TestDetailPPCBC, pred_cr, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_STRING_PTR("pred_ctr",
+			       CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			       TestDetailPPCBC, pred_ctr, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_STRING_PTR("bh", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			       TestDetailPPCBC, bh, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_END
+};
+
+typedef struct {
+	TestDetailPPCBC *bc;
+	tbool update_cr0;
+	char *format;
+	TestDetailPPCOp **operands;
+	uint32_t operands_count;
+} TestDetailPPC;
+
+static const cyaml_schema_field_t test_detail_ppc_mapping_schema[] = {
+	CYAML_FIELD_MAPPING_PTR("bc", CYAML_FLAG_OPTIONAL, TestDetailPPC, bc,
+				test_detail_ppc_bc_mapping_schema),
+	CYAML_FIELD_STRING_PTR("format",
+			       CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			       TestDetailPPC, format, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_INT("update_cr0", CYAML_FLAG_OPTIONAL, TestDetailPPC,
+			update_cr0),
+	CYAML_FIELD_SEQUENCE(
+		"operands", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+		TestDetailPPC, operands, &test_detail_ppc_op_schema, 0,
+		CYAML_UNLIMITED), // 0-MAX options
+	CYAML_FIELD_END
+};
+
+TestDetailPPC *test_detail_ppc_new();
+TestDetailPPC *test_detail_ppc_clone(const TestDetailPPC *detail);
+void test_detail_ppc_free(TestDetailPPC *detail);
+
+TestDetailPPCOp *test_detail_ppc_op_new();
+TestDetailPPCOp *test_detail_ppc_op_clone(const TestDetailPPCOp *detail);
+void test_detail_ppc_op_free(TestDetailPPCOp *detail);
+
+TestDetailPPCBC *test_detail_ppc_bc_new();
+TestDetailPPCBC *test_detail_ppc_bc_clone(const TestDetailPPCBC *detail);
+void test_detail_ppc_bc_free(TestDetailPPCBC *detail);
+
+bool test_expected_ppc(csh *handle, const cs_ppc *actual,
+		       const TestDetailPPC *expected);
+
+#endif // TEST_DETAIL_PPC_H
diff --git a/suite/cstest/include/test_detail_riscv.h b/suite/cstest/include/test_detail_riscv.h
new file mode 100644
index 000000000..0ba4d98e0
--- /dev/null
+++ b/suite/cstest/include/test_detail_riscv.h
@@ -0,0 +1,67 @@
+// Copyright © 2024 Rot127 <unisono@quyllur.org>
+// SPDX-License-Identifier: BSD-3
+
+#ifndef TEST_DETAIL_RISCV_H
+#define TEST_DETAIL_RISCV_H
+
+#include "test_compare.h"
+#include <cyaml/cyaml.h>
+#include <capstone/capstone.h>
+
+typedef struct {
+	char *type;
+	char *access;
+
+	char *reg;
+	uint64_t imm;
+	char *mem_base;
+	int64_t mem_disp;
+} TestDetailRISCVOp;
+
+static const cyaml_schema_field_t test_detail_riscv_op_mapping_schema[] = {
+	CYAML_FIELD_STRING_PTR("type", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			       TestDetailRISCVOp, type, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_STRING_PTR("access",
+			       CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			       TestDetailRISCVOp, access, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_STRING_PTR("reg", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			       TestDetailRISCVOp, reg, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_INT("imm", CYAML_FLAG_OPTIONAL, TestDetailRISCVOp, imm),
+	CYAML_FIELD_STRING_PTR("mem_base",
+			       CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			       TestDetailRISCVOp, mem_base, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_INT("mem_disp", CYAML_FLAG_OPTIONAL, TestDetailRISCVOp,
+			mem_disp),
+	CYAML_FIELD_END
+};
+
+static const cyaml_schema_value_t test_detail_riscv_op_schema = {
+	CYAML_VALUE_MAPPING(CYAML_FLAG_POINTER, TestDetailRISCVOp,
+			    test_detail_riscv_op_mapping_schema),
+};
+
+typedef struct {
+	TestDetailRISCVOp **operands;
+	uint32_t operands_count;
+} TestDetailRISCV;
+
+static const cyaml_schema_field_t test_detail_riscv_mapping_schema[] = {
+	CYAML_FIELD_SEQUENCE(
+		"operands", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+		TestDetailRISCV, operands, &test_detail_riscv_op_schema, 0,
+		CYAML_UNLIMITED), // 0-MAX options
+	CYAML_FIELD_END
+};
+
+TestDetailRISCV *test_detail_riscv_new();
+TestDetailRISCV *test_detail_riscv_clone(const TestDetailRISCV *detail);
+void test_detail_riscv_free(TestDetailRISCV *detail);
+
+TestDetailRISCVOp *test_detail_riscv_op_new();
+TestDetailRISCVOp *test_detail_riscv_op_clone(const TestDetailRISCVOp *detail);
+void test_detail_riscv_op_free(TestDetailRISCVOp *detail);
+
+bool test_expected_riscv(csh *handle, const cs_riscv *actual,
+			 const TestDetailRISCV *expected);
+
+#endif // TEST_DETAIL_RISCV_H
diff --git a/suite/cstest/include/test_detail_sh.h b/suite/cstest/include/test_detail_sh.h
new file mode 100644
index 000000000..3e6dea96b
--- /dev/null
+++ b/suite/cstest/include/test_detail_sh.h
@@ -0,0 +1,67 @@
+// Copyright © 2024 Rot127 <unisono@quyllur.org>
+// SPDX-License-Identifier: BSD-3
+
+#ifndef TEST_DETAIL_SH_H
+#define TEST_DETAIL_SH_H
+
+#include "test_compare.h"
+#include <cyaml/cyaml.h>
+#include <capstone/capstone.h>
+
+typedef struct {
+	char *type;
+
+	char *reg;
+	uint64_t imm;
+	char *mem_reg;
+	char *mem_address;
+	int32_t mem_disp;
+} TestDetailSHOp;
+
+static const cyaml_schema_field_t test_detail_sh_op_mapping_schema[] = {
+	CYAML_FIELD_STRING_PTR("type", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			       TestDetailSHOp, type, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_STRING_PTR("reg", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			       TestDetailSHOp, reg, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_INT("imm", CYAML_FLAG_OPTIONAL, TestDetailSHOp, imm),
+	CYAML_FIELD_STRING_PTR("mem_reg",
+			       CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			       TestDetailSHOp, mem_reg, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_STRING_PTR("mem_address",
+			       CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			       TestDetailSHOp, mem_address, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_INT("mem_disp", CYAML_FLAG_OPTIONAL, TestDetailSHOp,
+			mem_disp),
+	CYAML_FIELD_END
+};
+
+static const cyaml_schema_value_t test_detail_sh_op_schema = {
+	CYAML_VALUE_MAPPING(CYAML_FLAG_POINTER, TestDetailSHOp,
+			    test_detail_sh_op_mapping_schema),
+};
+
+typedef struct {
+	TestDetailSHOp **operands;
+	uint32_t operands_count;
+} TestDetailSH;
+
+static const cyaml_schema_field_t test_detail_sh_mapping_schema[] = {
+	CYAML_FIELD_SEQUENCE(
+		"operands", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+		TestDetailSH, operands, &test_detail_sh_op_schema, 0,
+		CYAML_UNLIMITED), // 0-MAX options
+	CYAML_FIELD_END
+};
+
+TestDetailSH *test_detail_sh_new();
+TestDetailSH *test_detail_sh_clone(const TestDetailSH *detail);
+void test_detail_sh_free(TestDetailSH *detail);
+
+TestDetailSHOp *test_detail_sh_op_new();
+TestDetailSHOp *test_detail_sh_op_clone(const TestDetailSHOp *detail);
+void test_detail_sh_op_free(TestDetailSHOp *detail);
+
+bool test_expected_sh(csh *handle, const cs_sh *actual,
+		      const TestDetailSH *expected);
+
+#endif // TEST_DETAIL_SH_H
diff --git a/suite/cstest/include/test_detail_sparc.h b/suite/cstest/include/test_detail_sparc.h
new file mode 100644
index 000000000..8008d94db
--- /dev/null
+++ b/suite/cstest/include/test_detail_sparc.h
@@ -0,0 +1,73 @@
+// Copyright © 2024 Rot127 <unisono@quyllur.org>
+// SPDX-License-Identifier: BSD-3
+
+#ifndef TEST_DETAIL_SPARC_H
+#define TEST_DETAIL_SPARC_H
+
+#include "test_compare.h"
+#include <cyaml/cyaml.h>
+#include <capstone/capstone.h>
+
+typedef struct {
+	char *type;
+
+	char *reg;
+	int64_t imm;
+	char *mem_base;
+	char *mem_index;
+	int32_t mem_disp;
+} TestDetailSparcOp;
+
+static const cyaml_schema_field_t test_detail_sparc_op_mapping_schema[] = {
+	CYAML_FIELD_STRING_PTR("type", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			       TestDetailSparcOp, type, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_STRING_PTR("reg", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			       TestDetailSparcOp, reg, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_INT("imm", CYAML_FLAG_OPTIONAL, TestDetailSparcOp, imm),
+	CYAML_FIELD_STRING_PTR("mem_base",
+			       CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			       TestDetailSparcOp, mem_base, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_STRING_PTR(
+		"mem_index", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+		TestDetailSparcOp, mem_index, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_INT("mem_disp", CYAML_FLAG_OPTIONAL, TestDetailSparcOp,
+			mem_disp),
+	CYAML_FIELD_END
+};
+
+static const cyaml_schema_value_t test_detail_sparc_op_schema = {
+	CYAML_VALUE_MAPPING(CYAML_FLAG_POINTER, TestDetailSparcOp,
+			    test_detail_sparc_op_mapping_schema),
+};
+
+typedef struct {
+	char *cc;
+	char *hint;
+	TestDetailSparcOp **operands;
+	uint32_t operands_count;
+} TestDetailSparc;
+
+static const cyaml_schema_field_t test_detail_sparc_mapping_schema[] = {
+	CYAML_FIELD_STRING_PTR("cc", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			       TestDetailSparc, cc, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_STRING_PTR("hint", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			       TestDetailSparc, hint, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_SEQUENCE(
+		"operands", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+		TestDetailSparc, operands, &test_detail_sparc_op_schema, 0,
+		CYAML_UNLIMITED), // 0-MAX options
+	CYAML_FIELD_END
+};
+
+TestDetailSparc *test_detail_sparc_new();
+TestDetailSparc *test_detail_sparc_clone(const TestDetailSparc *detail);
+void test_detail_sparc_free(TestDetailSparc *detail);
+
+TestDetailSparcOp *test_detail_sparc_op_new();
+TestDetailSparcOp *test_detail_sparc_op_clone(const TestDetailSparcOp *detail);
+void test_detail_sparc_op_free(TestDetailSparcOp *detail);
+
+bool test_expected_sparc(csh *handle, const cs_sparc *actual,
+			 const TestDetailSparc *expected);
+
+#endif // TEST_DETAIL_SPARC_H
diff --git a/suite/cstest/include/test_detail_systemz.h b/suite/cstest/include/test_detail_systemz.h
new file mode 100644
index 000000000..d7c0231a0
--- /dev/null
+++ b/suite/cstest/include/test_detail_systemz.h
@@ -0,0 +1,71 @@
+// Copyright © 2024 Rot127 <unisono@quyllur.org>
+// SPDX-License-Identifier: BSD-3
+
+#ifndef TEST_DETAIL_SYSTEMZ_H
+#define TEST_DETAIL_SYSTEMZ_H
+
+#include "test_compare.h"
+#include <cyaml/cyaml.h>
+#include <capstone/capstone.h>
+
+typedef struct {
+	char *type;
+
+	char *reg;
+	int64_t imm;
+	char *mem_base;
+	char *mem_index;
+	int64_t mem_disp;
+	uint64_t mem_length;
+} TestDetailSystemZOp;
+
+static const cyaml_schema_field_t test_detail_systemz_op_mapping_schema[] = {
+	CYAML_FIELD_STRING_PTR("type", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			       TestDetailSystemZOp, type, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_STRING_PTR("reg", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			       TestDetailSystemZOp, reg, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_INT("imm", CYAML_FLAG_OPTIONAL, TestDetailSystemZOp, imm),
+	CYAML_FIELD_STRING_PTR(
+		"mem_base", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+		TestDetailSystemZOp, mem_base, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_STRING_PTR(
+		"mem_index", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+		TestDetailSystemZOp, mem_index, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_INT("mem_disp", CYAML_FLAG_OPTIONAL, TestDetailSystemZOp,
+			mem_disp),
+	CYAML_FIELD_INT("mem_length", CYAML_FLAG_OPTIONAL, TestDetailSystemZOp,
+			mem_length),
+	CYAML_FIELD_END
+};
+
+static const cyaml_schema_value_t test_detail_systemz_op_schema = {
+	CYAML_VALUE_MAPPING(CYAML_FLAG_POINTER, TestDetailSystemZOp,
+			    test_detail_systemz_op_mapping_schema),
+};
+
+typedef struct {
+	TestDetailSystemZOp **operands;
+	uint32_t operands_count;
+} TestDetailSystemZ;
+
+static const cyaml_schema_field_t test_detail_systemz_mapping_schema[] = {
+	CYAML_FIELD_SEQUENCE(
+		"operands", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+		TestDetailSystemZ, operands, &test_detail_systemz_op_schema, 0,
+		CYAML_UNLIMITED), // 0-MAX options
+	CYAML_FIELD_END
+};
+
+TestDetailSystemZ *test_detail_systemz_new();
+TestDetailSystemZ *test_detail_systemz_clone(const TestDetailSystemZ *detail);
+void test_detail_systemz_free(TestDetailSystemZ *detail);
+
+TestDetailSystemZOp *test_detail_systemz_op_new();
+TestDetailSystemZOp *
+test_detail_systemz_op_clone(const TestDetailSystemZOp *detail);
+void test_detail_systemz_op_free(TestDetailSystemZOp *detail);
+
+bool test_expected_systemz(csh *handle, const cs_sysz *actual,
+			   const TestDetailSystemZ *expected);
+
+#endif // TEST_DETAIL_SYSTEMZ_H
diff --git a/suite/cstest/include/test_detail_tms320c64x.h b/suite/cstest/include/test_detail_tms320c64x.h
new file mode 100644
index 000000000..b5fa96e1e
--- /dev/null
+++ b/suite/cstest/include/test_detail_tms320c64x.h
@@ -0,0 +1,134 @@
+// Copyright © 2024 Rot127 <unisono@quyllur.org>
+// SPDX-License-Identifier: BSD-3
+
+#ifndef TEST_DETAIL_TMS320C64X_H
+#define TEST_DETAIL_TMS320C64X_H
+
+#include "test_compare.h"
+#include <cyaml/cyaml.h>
+#include <capstone/capstone.h>
+
+typedef struct {
+	char *type;
+
+	char *reg;
+	char *reg_pair_0;
+	char *reg_pair_1;
+	int32_t imm;
+	char *mem_base;
+	tbool mem_scaled;
+	char *mem_disptype;
+	char *mem_direction;
+	char *mem_modify;
+	char *mem_disp_reg;
+	unsigned int mem_disp_const;
+	unsigned int mem_unit;
+} TestDetailTMS320c64xOp;
+
+static const cyaml_schema_value_t test_detail_tms320c64x_op_sys_psr_schema = {
+	CYAML_VALUE_STRING(CYAML_FLAG_POINTER, char, 0, CYAML_UNLIMITED),
+};
+
+static const cyaml_schema_field_t test_detail_tms320c64x_op_mapping_schema[] = {
+	CYAML_FIELD_STRING_PTR("type", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			       TestDetailTMS320c64xOp, type, 0,
+			       CYAML_UNLIMITED),
+	CYAML_FIELD_STRING_PTR("reg", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			       TestDetailTMS320c64xOp, reg, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_STRING_PTR(
+		"reg_pair_0", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+		TestDetailTMS320c64xOp, reg_pair_0, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_STRING_PTR(
+		"reg_pair_1", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+		TestDetailTMS320c64xOp, reg_pair_1, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_INT("imm", CYAML_FLAG_OPTIONAL, TestDetailTMS320c64xOp,
+			imm),
+	CYAML_FIELD_INT("mem_scaled", CYAML_FLAG_OPTIONAL,
+			TestDetailTMS320c64xOp, mem_scaled),
+	CYAML_FIELD_STRING_PTR(
+		"mem_base", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+		TestDetailTMS320c64xOp, mem_base, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_STRING_PTR(
+		"mem_disptype", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+		TestDetailTMS320c64xOp, mem_disptype, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_STRING_PTR(
+		"mem_direction", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+		TestDetailTMS320c64xOp, mem_direction, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_STRING_PTR(
+		"mem_modify", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+		TestDetailTMS320c64xOp, mem_modify, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_UINT("mem_disp_const", CYAML_FLAG_OPTIONAL,
+			 TestDetailTMS320c64xOp, mem_disp_const),
+	CYAML_FIELD_STRING_PTR(
+		"mem_disp_reg", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+		TestDetailTMS320c64xOp, mem_disp_reg, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_UINT("mem_unit", CYAML_FLAG_OPTIONAL,
+			 TestDetailTMS320c64xOp, mem_unit),
+	CYAML_FIELD_END
+};
+
+static const cyaml_schema_value_t test_detail_tms320c64x_op_schema = {
+	CYAML_VALUE_MAPPING(CYAML_FLAG_POINTER, TestDetailTMS320c64xOp,
+			    test_detail_tms320c64x_op_mapping_schema),
+};
+
+typedef struct {
+	char *cond_reg;
+	tbool cond_zero;
+
+	char *funit_unit;
+	uint8_t funit_side;
+	bool funit_side_set;
+	uint8_t funit_crosspath;
+	bool funit_crosspath_set;
+
+	int8_t parallel;
+	bool parallel_set;
+
+	TestDetailTMS320c64xOp **operands;
+	uint32_t operands_count;
+} TestDetailTMS320c64x;
+
+static const cyaml_schema_field_t test_detail_tms320c64x_mapping_schema[] = {
+	CYAML_FIELD_STRING_PTR(
+		"cond_reg", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+		TestDetailTMS320c64x, cond_reg, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_INT("cond_zero", CYAML_FLAG_OPTIONAL, TestDetailTMS320c64x,
+			cond_zero),
+	CYAML_FIELD_STRING_PTR(
+		"funit_unit", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+		TestDetailTMS320c64x, funit_unit, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_UINT("funit_side", CYAML_FLAG_OPTIONAL,
+			 TestDetailTMS320c64x, funit_side),
+	CYAML_FIELD_BOOL("funit_side_set", CYAML_FLAG_OPTIONAL,
+			 TestDetailTMS320c64x, funit_side_set),
+	CYAML_FIELD_UINT("funit_crosspath", CYAML_FLAG_OPTIONAL,
+			 TestDetailTMS320c64x, funit_crosspath),
+	CYAML_FIELD_BOOL("funit_crosspath_set", CYAML_FLAG_OPTIONAL,
+			 TestDetailTMS320c64x, funit_crosspath_set),
+	CYAML_FIELD_INT("parallel", CYAML_FLAG_OPTIONAL, TestDetailTMS320c64x,
+			parallel),
+	CYAML_FIELD_BOOL("parallel_set", CYAML_FLAG_OPTIONAL,
+			 TestDetailTMS320c64x, parallel_set),
+	CYAML_FIELD_SEQUENCE("operands",
+			     CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			     TestDetailTMS320c64x, operands,
+			     &test_detail_tms320c64x_op_schema, 0,
+			     CYAML_UNLIMITED), // 0-MAX options
+	CYAML_FIELD_END
+};
+
+TestDetailTMS320c64x *test_detail_tms320c64x_new();
+TestDetailTMS320c64x *
+test_detail_tms320c64x_clone(TestDetailTMS320c64x *detail);
+void test_detail_tms320c64x_free(TestDetailTMS320c64x *detail);
+
+TestDetailTMS320c64xOp *test_detail_tms320c64x_op_new();
+TestDetailTMS320c64xOp *
+test_detail_tms320c64x_op_clone(TestDetailTMS320c64xOp *detail);
+void test_detail_tms320c64x_op_free(TestDetailTMS320c64xOp *detail);
+
+bool test_expected_tms320c64x(csh *handle, cs_tms320c64x *actual,
+			      TestDetailTMS320c64x *expected);
+
+#endif // TEST_DETAIL_TMS320C64X_H
diff --git a/suite/cstest/include/test_detail_tricore.h b/suite/cstest/include/test_detail_tricore.h
new file mode 100644
index 000000000..a31e6f816
--- /dev/null
+++ b/suite/cstest/include/test_detail_tricore.h
@@ -0,0 +1,71 @@
+// Copyright © 2024 Rot127 <unisono@quyllur.org>
+// SPDX-License-Identifier: BSD-3
+
+#ifndef TEST_DETAIL_TRICORE_H
+#define TEST_DETAIL_TRICORE_H
+
+#include "test_compare.h"
+#include <cyaml/cyaml.h>
+#include <capstone/capstone.h>
+
+typedef struct {
+	char *type;
+	char *access;
+
+	char *reg;
+	int64_t imm;
+	char *mem_base;
+	int64_t mem_disp;
+} TestDetailTriCoreOp;
+
+static const cyaml_schema_field_t test_detail_tricore_op_mapping_schema[] = {
+	CYAML_FIELD_STRING_PTR("type", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			       TestDetailTriCoreOp, type, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_STRING_PTR("access",
+			       CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			       TestDetailTriCoreOp, access, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_STRING_PTR("reg", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			       TestDetailTriCoreOp, reg, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_INT("imm", CYAML_FLAG_OPTIONAL, TestDetailTriCoreOp, imm),
+	CYAML_FIELD_STRING_PTR(
+		"mem_base", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+		TestDetailTriCoreOp, mem_base, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_INT("mem_disp", CYAML_FLAG_OPTIONAL, TestDetailTriCoreOp,
+			mem_disp),
+	CYAML_FIELD_END
+};
+
+static const cyaml_schema_value_t test_detail_tricore_op_schema = {
+	CYAML_VALUE_MAPPING(CYAML_FLAG_POINTER, TestDetailTriCoreOp,
+			    test_detail_tricore_op_mapping_schema),
+};
+
+typedef struct {
+	tbool update_flags;
+	TestDetailTriCoreOp **operands;
+	uint32_t operands_count;
+} TestDetailTriCore;
+
+static const cyaml_schema_field_t test_detail_tricore_mapping_schema[] = {
+	CYAML_FIELD_INT("update_flags", CYAML_FLAG_OPTIONAL, TestDetailTriCore,
+			update_flags),
+	CYAML_FIELD_SEQUENCE(
+		"operands", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+		TestDetailTriCore, operands, &test_detail_tricore_op_schema, 0,
+		CYAML_UNLIMITED), // 0-MAX options
+	CYAML_FIELD_END
+};
+
+TestDetailTriCore *test_detail_tricore_new();
+TestDetailTriCore *test_detail_tricore_clone(const TestDetailTriCore *detail);
+void test_detail_tricore_free(TestDetailTriCore *detail);
+
+TestDetailTriCoreOp *test_detail_tricore_op_new();
+TestDetailTriCoreOp *
+test_detail_tricore_op_clone(const TestDetailTriCoreOp *detail);
+void test_detail_tricore_op_free(TestDetailTriCoreOp *detail);
+
+bool test_expected_tricore(csh *handle, const cs_tricore *actual,
+			   const TestDetailTriCore *expected);
+
+#endif // TEST_DETAIL_TRICORE_H
diff --git a/suite/cstest/include/test_detail_wasm.h b/suite/cstest/include/test_detail_wasm.h
new file mode 100644
index 000000000..814fe95a8
--- /dev/null
+++ b/suite/cstest/include/test_detail_wasm.h
@@ -0,0 +1,82 @@
+// Copyright © 2024 Rot127 <unisono@quyllur.org>
+// SPDX-License-Identifier: BSD-3
+
+#ifndef TEST_DETAIL_WASM_H
+#define TEST_DETAIL_WASM_H
+
+#include "test_compare.h"
+#include <cyaml/cyaml.h>
+#include <capstone/capstone.h>
+
+typedef struct {
+	char *type;
+
+	uint32_t size;
+	int8_t int7;
+	uint32_t varuint32;
+	uint64_t varuint64;
+	uint32_t uint32;
+	uint64_t uint64;
+	uint32_t immediate_0;
+	uint32_t immediate_1;
+	uint32_t brt_length;
+	uint64_t brt_address;
+	uint32_t brt_default_target;
+} TestDetailWASMOp;
+
+static const cyaml_schema_field_t test_detail_wasm_op_mapping_schema[] = {
+	CYAML_FIELD_STRING_PTR("type", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			       TestDetailWASMOp, type, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_UINT("size", CYAML_FLAG_OPTIONAL, TestDetailWASMOp, size),
+	CYAML_FIELD_INT("int7", CYAML_FLAG_OPTIONAL, TestDetailWASMOp, int7),
+	CYAML_FIELD_UINT("varuint32", CYAML_FLAG_OPTIONAL, TestDetailWASMOp,
+			 varuint32),
+	CYAML_FIELD_UINT("varuint64", CYAML_FLAG_OPTIONAL, TestDetailWASMOp,
+			 varuint64),
+	CYAML_FIELD_UINT("uint64", CYAML_FLAG_OPTIONAL, TestDetailWASMOp,
+			 uint64),
+	CYAML_FIELD_UINT("uint32", CYAML_FLAG_OPTIONAL, TestDetailWASMOp,
+			 uint32),
+	CYAML_FIELD_UINT("immediate_0", CYAML_FLAG_OPTIONAL, TestDetailWASMOp,
+			 immediate_0),
+	CYAML_FIELD_UINT("immediate_1", CYAML_FLAG_OPTIONAL, TestDetailWASMOp,
+			 immediate_1),
+	CYAML_FIELD_UINT("brt_length", CYAML_FLAG_OPTIONAL, TestDetailWASMOp,
+			 brt_length),
+	CYAML_FIELD_UINT("brt_address", CYAML_FLAG_OPTIONAL, TestDetailWASMOp,
+			 brt_address),
+	CYAML_FIELD_UINT("brt_default_target", CYAML_FLAG_OPTIONAL,
+			 TestDetailWASMOp, brt_default_target),
+	CYAML_FIELD_END
+};
+
+static const cyaml_schema_value_t test_detail_wasm_op_schema = {
+	CYAML_VALUE_MAPPING(CYAML_FLAG_POINTER, TestDetailWASMOp,
+			    test_detail_wasm_op_mapping_schema),
+};
+
+typedef struct {
+	TestDetailWASMOp **operands;
+	uint32_t operands_count;
+} TestDetailWASM;
+
+static const cyaml_schema_field_t test_detail_wasm_mapping_schema[] = {
+	CYAML_FIELD_SEQUENCE(
+		"operands", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+		TestDetailWASM, operands, &test_detail_wasm_op_schema, 0,
+		CYAML_UNLIMITED), // 0-MAX options
+	CYAML_FIELD_END
+};
+
+TestDetailWASM *test_detail_wasm_new();
+TestDetailWASM *test_detail_wasm_clone(const TestDetailWASM *detail);
+void test_detail_wasm_free(TestDetailWASM *detail);
+
+TestDetailWASMOp *test_detail_wasm_op_new();
+TestDetailWASMOp *test_detail_wasm_op_clone(const TestDetailWASMOp *detail);
+void test_detail_wasm_op_free(TestDetailWASMOp *detail);
+
+bool test_expected_wasm(csh *handle, const cs_wasm *actual,
+			const TestDetailWASM *expected);
+
+#endif // TEST_DETAIL_WASM_H
diff --git a/suite/cstest/include/test_detail_x86.h b/suite/cstest/include/test_detail_x86.h
new file mode 100644
index 000000000..3dd51b833
--- /dev/null
+++ b/suite/cstest/include/test_detail_x86.h
@@ -0,0 +1,178 @@
+// Copyright © 2024 Rot127 <unisono@quyllur.org>
+// SPDX-License-Identifier: BSD-3
+
+#ifndef TEST_DETAIL_X86_H
+#define TEST_DETAIL_X86_H
+
+#include "test_compare.h"
+#include <cyaml/cyaml.h>
+#include <capstone/capstone.h>
+#include <stdint.h>
+
+typedef struct {
+	char *type;
+	char *access;
+	uint8_t size;
+
+	char *reg;
+	int64_t imm;
+	char *mem_segment;
+	char *mem_base;
+	char *mem_index;
+	int mem_scale;
+	int64_t mem_disp;
+
+	char *avx_bcast;
+	tbool avx_zero_opmask;
+} TestDetailX86Op;
+
+static const cyaml_schema_value_t test_detail_x86_op_sys_psr_schema = {
+	CYAML_VALUE_STRING(CYAML_FLAG_POINTER, char, 0, CYAML_UNLIMITED),
+};
+
+static const cyaml_schema_field_t test_detail_x86_op_mapping_schema[] = {
+	CYAML_FIELD_STRING_PTR("type", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			       TestDetailX86Op, type, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_STRING_PTR("access",
+			       CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			       TestDetailX86Op, access, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_UINT("size", CYAML_FLAG_OPTIONAL, TestDetailX86Op, size),
+	CYAML_FIELD_STRING_PTR("reg", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			       TestDetailX86Op, reg, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_INT("imm", CYAML_FLAG_OPTIONAL, TestDetailX86Op, imm),
+	CYAML_FIELD_STRING_PTR(
+		"mem_segment", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+		TestDetailX86Op, mem_segment, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_STRING_PTR("mem_base",
+			       CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			       TestDetailX86Op, mem_base, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_STRING_PTR("mem_index",
+			       CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			       TestDetailX86Op, mem_index, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_INT("mem_disp", CYAML_FLAG_OPTIONAL, TestDetailX86Op,
+			mem_disp),
+	CYAML_FIELD_INT("mem_scale", CYAML_FLAG_OPTIONAL, TestDetailX86Op,
+			mem_scale),
+	CYAML_FIELD_INT("avx_zero_opmask", CYAML_FLAG_OPTIONAL, TestDetailX86Op,
+			avx_zero_opmask),
+	CYAML_FIELD_STRING_PTR("avx_bcast",
+			       CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			       TestDetailX86Op, avx_bcast, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_END
+};
+
+static const cyaml_schema_value_t test_detail_x86_op_schema = {
+	CYAML_VALUE_MAPPING(CYAML_FLAG_POINTER, TestDetailX86Op,
+			    test_detail_x86_op_mapping_schema),
+};
+
+static const cyaml_schema_value_t test_detail_x86_opcode_schema = {
+	CYAML_VALUE_UINT(CYAML_FLAG_DEFAULT, uint8_t),
+};
+
+static const cyaml_schema_value_t test_detail_x86_string_schema = {
+	CYAML_VALUE_STRING(CYAML_FLAG_POINTER, char, 0, CYAML_UNLIMITED),
+};
+
+typedef struct {
+	char *sib_index;
+	char *sib_base;
+	char *xop_cc;
+	char *sse_cc;
+	char *avx_cc;
+	char *avx_rm;
+
+	char *prefix[4];
+	uint8_t opcode[4];
+
+	uint8_t rex;
+	uint8_t addr_size;
+	uint8_t modrm;
+	uint8_t sib;
+	int64_t disp;
+	int8_t sib_scale;
+	tbool avx_sae;
+
+	char **eflags;
+	size_t eflags_count;
+	char **fpu_flags;
+	size_t fpu_flags_count;
+
+	uint8_t enc_modrm_offset;
+	uint8_t enc_disp_offset;
+	uint8_t enc_disp_size;
+	uint8_t enc_imm_offset;
+	uint8_t enc_imm_size;
+
+	TestDetailX86Op **operands;
+	uint32_t operands_count;
+} TestDetailX86;
+
+static const cyaml_schema_field_t test_detail_x86_mapping_schema[] = {
+	CYAML_FIELD_STRING_PTR("sib_index",
+			       CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			       TestDetailX86, sib_index, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_STRING_PTR("sib_base",
+			       CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			       TestDetailX86, sib_base, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_STRING_PTR("xop_cc",
+			       CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			       TestDetailX86, xop_cc, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_STRING_PTR("sse_cc",
+			       CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			       TestDetailX86, sse_cc, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_STRING_PTR("avx_cc",
+			       CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			       TestDetailX86, avx_cc, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_STRING_PTR("avx_rm",
+			       CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			       TestDetailX86, avx_rm, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_SEQUENCE_FIXED("prefix", CYAML_FLAG_OPTIONAL, TestDetailX86,
+				   prefix, &test_detail_x86_string_schema, 4),
+	CYAML_FIELD_SEQUENCE_FIXED("opcode", CYAML_FLAG_OPTIONAL, TestDetailX86,
+				   opcode, &test_detail_x86_opcode_schema, 4),
+	CYAML_FIELD_UINT("rex", CYAML_FLAG_OPTIONAL, TestDetailX86, rex),
+	CYAML_FIELD_UINT("addr_size", CYAML_FLAG_OPTIONAL, TestDetailX86,
+			 addr_size),
+	CYAML_FIELD_UINT("modrm", CYAML_FLAG_OPTIONAL, TestDetailX86, modrm),
+	CYAML_FIELD_UINT("sib", CYAML_FLAG_OPTIONAL, TestDetailX86, sib),
+	CYAML_FIELD_INT("disp", CYAML_FLAG_OPTIONAL, TestDetailX86, disp),
+	CYAML_FIELD_INT("sib_scale", CYAML_FLAG_OPTIONAL, TestDetailX86,
+			sib_scale),
+	CYAML_FIELD_INT("avx_sae", CYAML_FLAG_OPTIONAL, TestDetailX86, avx_sae),
+	CYAML_FIELD_SEQUENCE("eflags", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			     TestDetailX86, eflags,
+			     &test_detail_x86_string_schema, 0,
+			     CYAML_UNLIMITED),
+	CYAML_FIELD_SEQUENCE(
+		"fpu_flags", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+		TestDetailX86, fpu_flags, &test_detail_x86_string_schema, 0,
+		CYAML_UNLIMITED),
+	CYAML_FIELD_UINT("enc_modrm_offset", CYAML_FLAG_OPTIONAL, TestDetailX86,
+			 enc_modrm_offset),
+	CYAML_FIELD_UINT("enc_disp_offset", CYAML_FLAG_OPTIONAL, TestDetailX86,
+			 enc_disp_offset),
+	CYAML_FIELD_UINT("enc_disp_size", CYAML_FLAG_OPTIONAL, TestDetailX86,
+			 enc_disp_size),
+	CYAML_FIELD_UINT("enc_imm_offset", CYAML_FLAG_OPTIONAL, TestDetailX86,
+			 enc_imm_offset),
+	CYAML_FIELD_UINT("enc_imm_size", CYAML_FLAG_OPTIONAL, TestDetailX86,
+			 enc_imm_size),
+	CYAML_FIELD_SEQUENCE(
+		"operands", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+		TestDetailX86, operands, &test_detail_x86_op_schema, 0,
+		CYAML_UNLIMITED), // 0-MAX options
+	CYAML_FIELD_END
+};
+
+TestDetailX86 *test_detail_x86_new();
+TestDetailX86 *test_detail_x86_clone(TestDetailX86 *detail);
+void test_detail_x86_free(TestDetailX86 *detail);
+
+TestDetailX86Op *test_detail_x86_op_new();
+TestDetailX86Op *test_detail_x86_op_clone(TestDetailX86Op *detail);
+void test_detail_x86_op_free(TestDetailX86Op *detail);
+
+bool test_expected_x86(csh *handle, cs_x86 *actual, TestDetailX86 *expected);
+
+#endif // TEST_DETAIL_X86_H
diff --git a/suite/cstest/include/test_detail_xcore.h b/suite/cstest/include/test_detail_xcore.h
new file mode 100644
index 000000000..9a8976726
--- /dev/null
+++ b/suite/cstest/include/test_detail_xcore.h
@@ -0,0 +1,70 @@
+// Copyright © 2024 Rot127 <unisono@quyllur.org>
+// SPDX-License-Identifier: BSD-3
+
+#ifndef TEST_DETAIL_XCORE_H
+#define TEST_DETAIL_XCORE_H
+
+#include "test_compare.h"
+#include <cyaml/cyaml.h>
+#include <capstone/capstone.h>
+
+typedef struct {
+	char *type;
+
+	char *reg;
+	int32_t imm;
+	char *mem_base;
+	char *mem_index;
+	int32_t mem_disp;
+	int32_t mem_direct;
+} TestDetailXCoreOp;
+
+static const cyaml_schema_field_t test_detail_xcore_op_mapping_schema[] = {
+	CYAML_FIELD_STRING_PTR("type", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			       TestDetailXCoreOp, type, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_STRING_PTR("reg", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			       TestDetailXCoreOp, reg, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_INT("imm", CYAML_FLAG_OPTIONAL, TestDetailXCoreOp, imm),
+	CYAML_FIELD_STRING_PTR("mem_base",
+			       CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+			       TestDetailXCoreOp, mem_base, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_STRING_PTR(
+		"mem_index", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+		TestDetailXCoreOp, mem_index, 0, CYAML_UNLIMITED),
+	CYAML_FIELD_INT("mem_disp", CYAML_FLAG_OPTIONAL, TestDetailXCoreOp,
+			mem_disp),
+	CYAML_FIELD_INT("mem_direct", CYAML_FLAG_OPTIONAL, TestDetailXCoreOp,
+			mem_direct),
+	CYAML_FIELD_END
+};
+
+static const cyaml_schema_value_t test_detail_xcore_op_schema = {
+	CYAML_VALUE_MAPPING(CYAML_FLAG_POINTER, TestDetailXCoreOp,
+			    test_detail_xcore_op_mapping_schema),
+};
+
+typedef struct {
+	TestDetailXCoreOp **operands;
+	uint32_t operands_count;
+} TestDetailXCore;
+
+static const cyaml_schema_field_t test_detail_xcore_mapping_schema[] = {
+	CYAML_FIELD_SEQUENCE(
+		"operands", CYAML_FLAG_POINTER | CYAML_FLAG_OPTIONAL,
+		TestDetailXCore, operands, &test_detail_xcore_op_schema, 0,
+		CYAML_UNLIMITED), // 0-MAX options
+	CYAML_FIELD_END
+};
+
+TestDetailXCore *test_detail_xcore_new();
+TestDetailXCore *test_detail_xcore_clone(const TestDetailXCore *detail);
+void test_detail_xcore_free(TestDetailXCore *detail);
+
+TestDetailXCoreOp *test_detail_xcore_op_new();
+TestDetailXCoreOp *test_detail_xcore_op_clone(const TestDetailXCoreOp *detail);
+void test_detail_xcore_op_free(TestDetailXCoreOp *detail);
+
+bool test_expected_xcore(csh *handle, const cs_xcore *actual,
+			 const TestDetailXCore *expected);
+
+#endif // TEST_DETAIL_XCORE_H
diff --git a/suite/cstest/include/test_mapping.h b/suite/cstest/include/test_mapping.h
new file mode 100644
index 000000000..7ef546b52
--- /dev/null
+++ b/suite/cstest/include/test_mapping.h
@@ -0,0 +1,1348 @@
+// Copyright © 2024 Rot127 <unisono@quyllur.org>
+// SPDX-License-Identifier: BSD-3
+
+#ifndef TEST_MAPPING_H
+#define TEST_MAPPING_H
+
+#include "../../../Mapping.h"
+#include <capstone/capstone.h>
+
+/// Maps a string to an option
+typedef struct {
+	const char *str;
+	cs_opt opt;
+} TestOptionMapEntry;
+
+/// REMEMBER TO SORT AFTER EDIT
+static const cs_enum_id_map test_arch_map[] = {
+	{ .str = "AArch64", .val = CS_ARCH_AARCH64 },
+	{ .str = "CS_ARCH_AARCH64", .val = CS_ARCH_AARCH64 },
+	{ .str = "CS_ARCH_ALPHA", .val = CS_ARCH_ALPHA },
+	{ .str = "CS_ARCH_ARM", .val = CS_ARCH_ARM },
+	{ .str = "CS_ARCH_BPF", .val = CS_ARCH_BPF },
+	{ .str = "CS_ARCH_EVM", .val = CS_ARCH_EVM },
+	{ .str = "CS_ARCH_HPPA", .val = CS_ARCH_HPPA },
+	{ .str = "CS_ARCH_LOONGARCH", .val = CS_ARCH_LOONGARCH },
+	{ .str = "CS_ARCH_M680X", .val = CS_ARCH_M680X },
+	{ .str = "CS_ARCH_M68K", .val = CS_ARCH_M68K },
+	{ .str = "CS_ARCH_MIPS", .val = CS_ARCH_MIPS },
+	{ .str = "CS_ARCH_MOS65XX", .val = CS_ARCH_MOS65XX },
+	{ .str = "CS_ARCH_PPC", .val = CS_ARCH_PPC },
+	{ .str = "CS_ARCH_RISCV", .val = CS_ARCH_RISCV },
+	{ .str = "CS_ARCH_SH", .val = CS_ARCH_SH },
+	{ .str = "CS_ARCH_SPARC", .val = CS_ARCH_SPARC },
+	{ .str = "CS_ARCH_SYSZ", .val = CS_ARCH_SYSZ },
+	{ .str = "CS_ARCH_TMS320C64X", .val = CS_ARCH_TMS320C64X },
+	{ .str = "CS_ARCH_TRICORE", .val = CS_ARCH_TRICORE },
+	{ .str = "CS_ARCH_WASM", .val = CS_ARCH_WASM },
+	{ .str = "CS_ARCH_X86", .val = CS_ARCH_X86 },
+	{ .str = "CS_ARCH_XCORE", .val = CS_ARCH_XCORE },
+	{ .str = "aarch64", .val = CS_ARCH_AARCH64 },
+	{ .str = "alpha", .val = CS_ARCH_ALPHA },
+	{ .str = "arm", .val = CS_ARCH_ARM },
+	{ .str = "bpf", .val = CS_ARCH_BPF },
+	{ .str = "evm", .val = CS_ARCH_EVM },
+	{ .str = "hppa", .val = CS_ARCH_HPPA },
+	{ .str = "loongarch", .val = CS_ARCH_LOONGARCH },
+	{ .str = "m680x", .val = CS_ARCH_M680X },
+	{ .str = "m68k", .val = CS_ARCH_M68K },
+	{ .str = "mips", .val = CS_ARCH_MIPS },
+	{ .str = "mos65xx", .val = CS_ARCH_MOS65XX },
+	{ .str = "ppc", .val = CS_ARCH_PPC },
+	{ .str = "riscv", .val = CS_ARCH_RISCV },
+	{ .str = "sh", .val = CS_ARCH_SH },
+	{ .str = "sparc", .val = CS_ARCH_SPARC },
+	{ .str = "systemz", .val = CS_ARCH_SYSZ },
+	{ .str = "tms320c64x", .val = CS_ARCH_TMS320C64X },
+	{ .str = "tricore", .val = CS_ARCH_TRICORE },
+	{ .str = "wasm", .val = CS_ARCH_WASM },
+	{ .str = "x86", .val = CS_ARCH_X86 },
+	{ .str = "xcore", .val = CS_ARCH_XCORE },
+};
+
+/// REMEMBER TO SORT AFTER EDIT
+static const cs_enum_id_map test_mode_map[] = {
+	{ .str = "CS_MODE_16", .val = CS_MODE_16 },
+	{ .str = "CS_MODE_32", .val = CS_MODE_32 },
+	{ .str = "CS_MODE_64", .val = CS_MODE_64 },
+	{ .str = "CS_MODE_ARM", .val = CS_MODE_ARM },
+	{ .str = "CS_MODE_BIG_ENDIAN", .val = CS_MODE_BIG_ENDIAN },
+	{ .str = "CS_MODE_BOOKE", .val = CS_MODE_BOOKE },
+	{ .str = "CS_MODE_BPF_CLASSIC", .val = CS_MODE_BPF_CLASSIC },
+	{ .str = "CS_MODE_BPF_EXTENDED", .val = CS_MODE_BPF_EXTENDED },
+	{ .str = "CS_MODE_HPPA_11", .val = CS_MODE_HPPA_11 },
+	{ .str = "CS_MODE_HPPA_20", .val = CS_MODE_HPPA_20 },
+	{ .str = "CS_MODE_HPPA_20W", .val = CS_MODE_HPPA_20W },
+	{ .str = "CS_MODE_LITTLE_ENDIAN", .val = CS_MODE_LITTLE_ENDIAN },
+	{ .str = "CS_MODE_LOONGARCH32", .val = CS_MODE_LOONGARCH32 },
+	{ .str = "CS_MODE_LOONGARCH64", .val = CS_MODE_LOONGARCH64 },
+	{ .str = "CS_MODE_M680X_6301", .val = CS_MODE_M680X_6301 },
+	{ .str = "CS_MODE_M680X_6309", .val = CS_MODE_M680X_6309 },
+	{ .str = "CS_MODE_M680X_6800", .val = CS_MODE_M680X_6800 },
+	{ .str = "CS_MODE_M680X_6801", .val = CS_MODE_M680X_6801 },
+	{ .str = "CS_MODE_M680X_6805", .val = CS_MODE_M680X_6805 },
+	{ .str = "CS_MODE_M680X_6808", .val = CS_MODE_M680X_6808 },
+	{ .str = "CS_MODE_M680X_6809", .val = CS_MODE_M680X_6809 },
+	{ .str = "CS_MODE_M680X_6811", .val = CS_MODE_M680X_6811 },
+	{ .str = "CS_MODE_M680X_CPU12", .val = CS_MODE_M680X_CPU12 },
+	{ .str = "CS_MODE_M680X_HCS08", .val = CS_MODE_M680X_HCS08 },
+	{ .str = "CS_MODE_M68K_000", .val = CS_MODE_M68K_000 },
+	{ .str = "CS_MODE_M68K_010", .val = CS_MODE_M68K_010 },
+	{ .str = "CS_MODE_M68K_020", .val = CS_MODE_M68K_020 },
+	{ .str = "CS_MODE_M68K_030", .val = CS_MODE_M68K_030 },
+	{ .str = "CS_MODE_M68K_040", .val = CS_MODE_M68K_040 },
+	{ .str = "CS_MODE_M68K_060", .val = CS_MODE_M68K_060 },
+	{ .str = "CS_MODE_MCLASS", .val = CS_MODE_MCLASS },
+	{ .str = "CS_MODE_MICRO", .val = CS_MODE_MICRO },
+	{ .str = "CS_MODE_MIPS2", .val = CS_MODE_MIPS2 },
+	{ .str = "CS_MODE_MIPS3", .val = CS_MODE_MIPS3 },
+	{ .str = "CS_MODE_MIPS32", .val = CS_MODE_MIPS32 },
+	{ .str = "CS_MODE_MIPS32R6", .val = CS_MODE_MIPS32R6 },
+	{ .str = "CS_MODE_MIPS64", .val = CS_MODE_MIPS64 },
+	{ .str = "CS_MODE_MOS65XX_6502", .val = CS_MODE_MOS65XX_6502 },
+	{ .str = "CS_MODE_MOS65XX_65816", .val = CS_MODE_MOS65XX_65816 },
+	{ .str = "CS_MODE_MOS65XX_65816_LONG_M",
+	  .val = CS_MODE_MOS65XX_65816_LONG_M },
+	{ .str = "CS_MODE_MOS65XX_65816_LONG_MX",
+	  .val = CS_MODE_MOS65XX_65816_LONG_M | CS_MODE_MOS65XX_65816_LONG_X },
+	{ .str = "CS_MODE_MOS65XX_65816_LONG_X",
+	  .val = CS_MODE_MOS65XX_65816_LONG_X },
+	{ .str = "CS_MODE_MOS65XX_65C02", .val = CS_MODE_MOS65XX_65C02 },
+	{ .str = "CS_MODE_MOS65XX_W65C02", .val = CS_MODE_MOS65XX_W65C02 },
+	{ .str = "CS_MODE_PS", .val = CS_MODE_PS },
+	{ .str = "CS_MODE_QPX", .val = CS_MODE_QPX },
+	{ .str = "CS_MODE_RISCV32", .val = CS_MODE_RISCV32 },
+	{ .str = "CS_MODE_RISCV64", .val = CS_MODE_RISCV64 },
+	{ .str = "CS_MODE_RISCVC", .val = CS_MODE_RISCVC },
+	{ .str = "CS_MODE_SH2", .val = CS_MODE_SH2 },
+	{ .str = "CS_MODE_SH2A", .val = CS_MODE_SH2A },
+	{ .str = "CS_MODE_SH3", .val = CS_MODE_SH3 },
+	{ .str = "CS_MODE_SH4", .val = CS_MODE_SH4 },
+	{ .str = "CS_MODE_SH4A", .val = CS_MODE_SH4A },
+	{ .str = "CS_MODE_SHDSP", .val = CS_MODE_SHDSP },
+	{ .str = "CS_MODE_SHFPU", .val = CS_MODE_SHFPU },
+	{ .str = "CS_MODE_SPE", .val = CS_MODE_SPE },
+	{ .str = "CS_MODE_THUMB", .val = CS_MODE_THUMB },
+	{ .str = "CS_MODE_TRICORE_110", .val = CS_MODE_TRICORE_110 },
+	{ .str = "CS_MODE_TRICORE_120", .val = CS_MODE_TRICORE_120 },
+	{ .str = "CS_MODE_TRICORE_130", .val = CS_MODE_TRICORE_130 },
+	{ .str = "CS_MODE_TRICORE_131", .val = CS_MODE_TRICORE_131 },
+	{ .str = "CS_MODE_TRICORE_160", .val = CS_MODE_TRICORE_160 },
+	{ .str = "CS_MODE_TRICORE_161", .val = CS_MODE_TRICORE_161 },
+	{ .str = "CS_MODE_TRICORE_162", .val = CS_MODE_TRICORE_162 },
+	{ .str = "CS_MODE_V8", .val = CS_MODE_V8 },
+	{ .str = "CS_MODE_V9", .val = CS_MODE_V9 },
+};
+
+static const TestOptionMapEntry test_option_map[] = {
+	{ .str = "CS_OPT_DETAIL",
+	  .opt = { .type = CS_OPT_DETAIL, .val = CS_OPT_ON } },
+	{ .str = "CS_OPT_DETAIL_REAL",
+	  .opt = { .type = CS_OPT_DETAIL,
+		   .val = CS_OPT_DETAIL_REAL | CS_OPT_ON } },
+	{ .str = "CS_OPT_SKIPDATA",
+	  .opt = { .type = CS_OPT_SKIPDATA, .val = CS_OPT_ON } },
+	{ .str = "CS_OPT_UNSIGNED",
+	  .opt = { .type = CS_OPT_UNSIGNED, .val = CS_OPT_ON } },
+	{ .str = "CS_OPT_NO_BRANCH_OFFSET",
+	  .opt = { .type = CS_OPT_NO_BRANCH_OFFSET, .val = CS_OPT_ON } },
+	{ .str = "CS_OPT_SYNTAX_DEFAULT",
+	  .opt = { .type = CS_OPT_SYNTAX, .val = CS_OPT_SYNTAX_DEFAULT } },
+	{ .str = "CS_OPT_SYNTAX_INTEL",
+	  .opt = { .type = CS_OPT_SYNTAX, .val = CS_OPT_SYNTAX_INTEL } },
+	{ .str = "CS_OPT_SYNTAX_ATT",
+	  .opt = { .type = CS_OPT_SYNTAX, .val = CS_OPT_SYNTAX_ATT } },
+	{ .str = "CS_OPT_SYNTAX_NOREGNAME",
+	  .opt = { .type = CS_OPT_SYNTAX, .val = CS_OPT_SYNTAX_NOREGNAME } },
+	{ .str = "CS_OPT_SYNTAX_MASM",
+	  .opt = { .type = CS_OPT_SYNTAX, .val = CS_OPT_SYNTAX_MASM } },
+	{ .str = "CS_OPT_SYNTAX_MOTOROLA",
+	  .opt = { .type = CS_OPT_SYNTAX, .val = CS_OPT_SYNTAX_MOTOROLA } },
+	{ .str = "CS_OPT_SYNTAX_CS_REG_ALIAS",
+	  .opt = { .type = CS_OPT_SYNTAX, .val = CS_OPT_SYNTAX_CS_REG_ALIAS } },
+	{ .str = "CS_OPT_SYNTAX_PERCENT",
+	  .opt = { .type = CS_OPT_SYNTAX, .val = CS_OPT_SYNTAX_PERCENT } },
+};
+
+static const cs_enum_id_map cs_enum_map[] = {
+	{ .str = "AAAAAAAAAAAAAAAAAAAAAAAAAA", .val = 0xffffff }, // For testing
+	{ .str = "AARCH64LAYOUT_INVALID", .val = AARCH64LAYOUT_INVALID },
+	{ .str = "AARCH64LAYOUT_VL_16B", .val = AARCH64LAYOUT_VL_16B },
+	{ .str = "AARCH64LAYOUT_VL_16S", .val = AARCH64LAYOUT_VL_16S },
+	{ .str = "AARCH64LAYOUT_VL_1D", .val = AARCH64LAYOUT_VL_1D },
+	{ .str = "AARCH64LAYOUT_VL_1Q", .val = AARCH64LAYOUT_VL_1Q },
+	{ .str = "AARCH64LAYOUT_VL_1S", .val = AARCH64LAYOUT_VL_1S },
+	{ .str = "AARCH64LAYOUT_VL_2D", .val = AARCH64LAYOUT_VL_2D },
+	{ .str = "AARCH64LAYOUT_VL_2H", .val = AARCH64LAYOUT_VL_2H },
+	{ .str = "AARCH64LAYOUT_VL_2S", .val = AARCH64LAYOUT_VL_2S },
+	{ .str = "AARCH64LAYOUT_VL_32H", .val = AARCH64LAYOUT_VL_32H },
+	{ .str = "AARCH64LAYOUT_VL_4B", .val = AARCH64LAYOUT_VL_4B },
+	{ .str = "AARCH64LAYOUT_VL_4H", .val = AARCH64LAYOUT_VL_4H },
+	{ .str = "AARCH64LAYOUT_VL_4S", .val = AARCH64LAYOUT_VL_4S },
+	{ .str = "AARCH64LAYOUT_VL_64B", .val = AARCH64LAYOUT_VL_64B },
+	{ .str = "AARCH64LAYOUT_VL_8B", .val = AARCH64LAYOUT_VL_8B },
+	{ .str = "AARCH64LAYOUT_VL_8D", .val = AARCH64LAYOUT_VL_8D },
+	{ .str = "AARCH64LAYOUT_VL_8H", .val = AARCH64LAYOUT_VL_8H },
+	{ .str = "AARCH64LAYOUT_VL_B", .val = AARCH64LAYOUT_VL_B },
+	{ .str = "AARCH64LAYOUT_VL_COMPLETE",
+	  .val = AARCH64LAYOUT_VL_COMPLETE },
+	{ .str = "AARCH64LAYOUT_VL_D", .val = AARCH64LAYOUT_VL_D },
+	{ .str = "AARCH64LAYOUT_VL_H", .val = AARCH64LAYOUT_VL_H },
+	{ .str = "AARCH64LAYOUT_VL_Q", .val = AARCH64LAYOUT_VL_Q },
+	{ .str = "AARCH64LAYOUT_VL_S", .val = AARCH64LAYOUT_VL_S },
+	{ .str = "AARCH64_EXT_INVALID", .val = AARCH64_EXT_INVALID },
+	{ .str = "AARCH64_EXT_SXTB", .val = AARCH64_EXT_SXTB },
+	{ .str = "AARCH64_EXT_SXTH", .val = AARCH64_EXT_SXTH },
+	{ .str = "AARCH64_EXT_SXTW", .val = AARCH64_EXT_SXTW },
+	{ .str = "AARCH64_EXT_SXTX", .val = AARCH64_EXT_SXTX },
+	{ .str = "AARCH64_EXT_UXTB", .val = AARCH64_EXT_UXTB },
+	{ .str = "AARCH64_EXT_UXTH", .val = AARCH64_EXT_UXTH },
+	{ .str = "AARCH64_EXT_UXTW", .val = AARCH64_EXT_UXTW },
+	{ .str = "AARCH64_EXT_UXTX", .val = AARCH64_EXT_UXTX },
+	{ .str = "AARCH64_OP_AT", .val = AARCH64_OP_AT },
+	{ .str = "AARCH64_OP_BTI", .val = AARCH64_OP_BTI },
+	{ .str = "AARCH64_OP_CIMM", .val = AARCH64_OP_CIMM },
+	{ .str = "AARCH64_OP_DB", .val = AARCH64_OP_DB },
+	{ .str = "AARCH64_OP_DBNXS", .val = AARCH64_OP_DBNXS },
+	{ .str = "AARCH64_OP_DC", .val = AARCH64_OP_DC },
+	{ .str = "AARCH64_OP_EXACTFPIMM", .val = AARCH64_OP_EXACTFPIMM },
+	{ .str = "AARCH64_OP_FP", .val = AARCH64_OP_FP },
+	{ .str = "AARCH64_OP_IC", .val = AARCH64_OP_IC },
+	{ .str = "AARCH64_OP_IMM", .val = AARCH64_OP_IMM },
+	{ .str = "AARCH64_OP_IMM_RANGE", .val = AARCH64_OP_IMM_RANGE },
+	{ .str = "AARCH64_OP_IMPLICIT_IMM_0",
+	  .val = AARCH64_OP_IMPLICIT_IMM_0 },
+	{ .str = "AARCH64_OP_ISB", .val = AARCH64_OP_ISB },
+	{ .str = "AARCH64_OP_MEM", .val = AARCH64_OP_MEM },
+	{ .str = "AARCH64_OP_MEM_IMM", .val = AARCH64_OP_MEM_IMM },
+	{ .str = "AARCH64_OP_MEM_REG", .val = AARCH64_OP_MEM_REG },
+	{ .str = "AARCH64_OP_PRED", .val = AARCH64_OP_PRED },
+	{ .str = "AARCH64_OP_PRFM", .val = AARCH64_OP_PRFM },
+	{ .str = "AARCH64_OP_PSB", .val = AARCH64_OP_PSB },
+	{ .str = "AARCH64_OP_PSTATEIMM0_1", .val = AARCH64_OP_PSTATEIMM0_1 },
+	{ .str = "AARCH64_OP_PSTATEIMM0_15", .val = AARCH64_OP_PSTATEIMM0_15 },
+	{ .str = "AARCH64_OP_REG", .val = AARCH64_OP_REG },
+	{ .str = "AARCH64_OP_REG_MRS", .val = AARCH64_OP_REG_MRS },
+	{ .str = "AARCH64_OP_REG_MSR", .val = AARCH64_OP_REG_MSR },
+	{ .str = "AARCH64_OP_RPRFM", .val = AARCH64_OP_RPRFM },
+	{ .str = "AARCH64_OP_SME", .val = AARCH64_OP_SME },
+	{ .str = "AARCH64_OP_SVCR", .val = AARCH64_OP_SVCR },
+	{ .str = "AARCH64_OP_SVEPREDPAT", .val = AARCH64_OP_SVEPREDPAT },
+	{ .str = "AARCH64_OP_SVEPRFM", .val = AARCH64_OP_SVEPRFM },
+	{ .str = "AARCH64_OP_SVEVECLENSPECIFIER",
+	  .val = AARCH64_OP_SVEVECLENSPECIFIER },
+	{ .str = "AARCH64_OP_SYSALIAS", .val = AARCH64_OP_SYSALIAS },
+	{ .str = "AARCH64_OP_SYSIMM", .val = AARCH64_OP_SYSIMM },
+	{ .str = "AARCH64_OP_SYSREG", .val = AARCH64_OP_SYSREG },
+	{ .str = "AARCH64_OP_TLBI", .val = AARCH64_OP_TLBI },
+	{ .str = "AARCH64_OP_TSB", .val = AARCH64_OP_TSB },
+	{ .str = "AARCH64_SFT_ASR", .val = AARCH64_SFT_ASR },
+	{ .str = "AARCH64_SFT_INVALID", .val = AARCH64_SFT_INVALID },
+	{ .str = "AARCH64_SFT_LSL", .val = AARCH64_SFT_LSL },
+	{ .str = "AARCH64_SFT_LSR", .val = AARCH64_SFT_LSR },
+	{ .str = "AARCH64_SFT_MSL", .val = AARCH64_SFT_MSL },
+	{ .str = "AARCH64_SFT_ROR", .val = AARCH64_SFT_ROR },
+	{ .str = "AARCH64_SME_MATRIX_SLICE_OFF",
+	  .val = AARCH64_SME_MATRIX_SLICE_OFF },
+	{ .str = "AARCH64_SME_MATRIX_SLICE_OFF_RANGE",
+	  .val = AARCH64_SME_MATRIX_SLICE_OFF_RANGE },
+	{ .str = "AARCH64_SME_MATRIX_SLICE_REG",
+	  .val = AARCH64_SME_MATRIX_SLICE_REG },
+	{ .str = "AARCH64_SME_MATRIX_TILE", .val = AARCH64_SME_MATRIX_TILE },
+	{ .str = "AARCH64_SME_MATRIX_TILE_LIST",
+	  .val = AARCH64_SME_MATRIX_TILE_LIST },
+	{ .str = "AARCH64_SME_OP_INVALID", .val = AARCH64_SME_OP_INVALID },
+	{ .str = "AARCH64_SME_OP_TILE", .val = AARCH64_SME_OP_TILE },
+	{ .str = "AARCH64_SME_OP_TILE_VEC", .val = AARCH64_SME_OP_TILE_VEC },
+	{ .str = "AArch64CC_AL", .val = AArch64CC_AL },
+	{ .str = "AArch64CC_EQ", .val = AArch64CC_EQ },
+	{ .str = "AArch64CC_GE", .val = AArch64CC_GE },
+	{ .str = "AArch64CC_GT", .val = AArch64CC_GT },
+	{ .str = "AArch64CC_HI", .val = AArch64CC_HI },
+	{ .str = "AArch64CC_HS", .val = AArch64CC_HS },
+	{ .str = "AArch64CC_Invalid", .val = AArch64CC_Invalid },
+	{ .str = "AArch64CC_LE", .val = AArch64CC_LE },
+	{ .str = "AArch64CC_LO", .val = AArch64CC_LO },
+	{ .str = "AArch64CC_LS", .val = AArch64CC_LS },
+	{ .str = "AArch64CC_LT", .val = AArch64CC_LT },
+	{ .str = "AArch64CC_MI", .val = AArch64CC_MI },
+	{ .str = "AArch64CC_NE", .val = AArch64CC_NE },
+	{ .str = "AArch64CC_NV", .val = AArch64CC_NV },
+	{ .str = "AArch64CC_PL", .val = AArch64CC_PL },
+	{ .str = "AArch64CC_VC", .val = AArch64CC_VC },
+	{ .str = "AArch64CC_VS", .val = AArch64CC_VS },
+	{ .str = "ALPHA_OP_IMM", .val = ALPHA_OP_IMM },
+	{ .str = "ALPHA_OP_REG", .val = ALPHA_OP_REG },
+	{ .str = "ARMCC_AL", .val = ARMCC_AL },
+	{ .str = "ARMCC_EQ", .val = ARMCC_EQ },
+	{ .str = "ARMCC_GE", .val = ARMCC_GE },
+	{ .str = "ARMCC_GT", .val = ARMCC_GT },
+	{ .str = "ARMCC_HI", .val = ARMCC_HI },
+	{ .str = "ARMCC_HS", .val = ARMCC_HS },
+	{ .str = "ARMCC_LE", .val = ARMCC_LE },
+	{ .str = "ARMCC_LO", .val = ARMCC_LO },
+	{ .str = "ARMCC_LS", .val = ARMCC_LS },
+	{ .str = "ARMCC_LT", .val = ARMCC_LT },
+	{ .str = "ARMCC_MI", .val = ARMCC_MI },
+	{ .str = "ARMCC_NE", .val = ARMCC_NE },
+	{ .str = "ARMCC_PL", .val = ARMCC_PL },
+	{ .str = "ARMCC_UNDEF", .val = ARMCC_UNDEF },
+	{ .str = "ARMCC_VC", .val = ARMCC_VC },
+	{ .str = "ARMCC_VS", .val = ARMCC_VS },
+	{ .str = "ARMVCC_Else", .val = ARMVCC_Else },
+	{ .str = "ARMVCC_None", .val = ARMVCC_None },
+	{ .str = "ARMVCC_Then", .val = ARMVCC_Then },
+	{ .str = "ARM_CPSFLAG_A", .val = ARM_CPSFLAG_A },
+	{ .str = "ARM_CPSFLAG_F", .val = ARM_CPSFLAG_F },
+	{ .str = "ARM_CPSFLAG_I", .val = ARM_CPSFLAG_I },
+	{ .str = "ARM_CPSFLAG_INVALID", .val = ARM_CPSFLAG_INVALID },
+	{ .str = "ARM_CPSFLAG_NONE", .val = ARM_CPSFLAG_NONE },
+	{ .str = "ARM_CPSMODE_ID", .val = ARM_CPSMODE_ID },
+	{ .str = "ARM_CPSMODE_IE", .val = ARM_CPSMODE_IE },
+	{ .str = "ARM_CPSMODE_INVALID", .val = ARM_CPSMODE_INVALID },
+	{ .str = "ARM_FIELD_CPSR_C", .val = ARM_FIELD_CPSR_C },
+	{ .str = "ARM_FIELD_CPSR_F", .val = ARM_FIELD_CPSR_F },
+	{ .str = "ARM_FIELD_CPSR_S", .val = ARM_FIELD_CPSR_S },
+	{ .str = "ARM_FIELD_CPSR_X", .val = ARM_FIELD_CPSR_X },
+	{ .str = "ARM_FIELD_SPSR_C", .val = ARM_FIELD_SPSR_C },
+	{ .str = "ARM_FIELD_SPSR_F", .val = ARM_FIELD_SPSR_F },
+	{ .str = "ARM_FIELD_SPSR_S", .val = ARM_FIELD_SPSR_S },
+	{ .str = "ARM_FIELD_SPSR_X", .val = ARM_FIELD_SPSR_X },
+	{ .str = "ARM_MB_ISH", .val = ARM_MB_ISH },
+	{ .str = "ARM_MB_ISHLD", .val = ARM_MB_ISHLD },
+	{ .str = "ARM_MB_ISHST", .val = ARM_MB_ISHST },
+	{ .str = "ARM_MB_LD", .val = ARM_MB_LD },
+	{ .str = "ARM_MB_NSH", .val = ARM_MB_NSH },
+	{ .str = "ARM_MB_NSHLD", .val = ARM_MB_NSHLD },
+	{ .str = "ARM_MB_NSHST", .val = ARM_MB_NSHST },
+	{ .str = "ARM_MB_OSH", .val = ARM_MB_OSH },
+	{ .str = "ARM_MB_OSHLD", .val = ARM_MB_OSHLD },
+	{ .str = "ARM_MB_OSHST", .val = ARM_MB_OSHST },
+	{ .str = "ARM_MB_RESERVED_0", .val = ARM_MB_RESERVED_0 },
+	{ .str = "ARM_MB_RESERVED_12", .val = ARM_MB_RESERVED_12 },
+	{ .str = "ARM_MB_RESERVED_4", .val = ARM_MB_RESERVED_4 },
+	{ .str = "ARM_MB_RESERVED_8", .val = ARM_MB_RESERVED_8 },
+	{ .str = "ARM_MB_ST", .val = ARM_MB_ST },
+	{ .str = "ARM_MB_SY", .val = ARM_MB_SY },
+	{ .str = "ARM_OP_BANKEDREG", .val = ARM_OP_BANKEDREG },
+	{ .str = "ARM_OP_CIMM", .val = ARM_OP_CIMM },
+	{ .str = "ARM_OP_CPSR", .val = ARM_OP_CPSR },
+	{ .str = "ARM_OP_FP", .val = ARM_OP_FP },
+	{ .str = "ARM_OP_IMM", .val = ARM_OP_IMM },
+	{ .str = "ARM_OP_MEM", .val = ARM_OP_MEM },
+	{ .str = "ARM_OP_PIMM", .val = ARM_OP_PIMM },
+	{ .str = "ARM_OP_PRED", .val = ARM_OP_PRED },
+	{ .str = "ARM_OP_REG", .val = ARM_OP_REG },
+	{ .str = "ARM_OP_SETEND", .val = ARM_OP_SETEND },
+	{ .str = "ARM_OP_SPSR", .val = ARM_OP_SPSR },
+	{ .str = "ARM_OP_SYSM", .val = ARM_OP_SYSM },
+	{ .str = "ARM_OP_SYSREG", .val = ARM_OP_SYSREG },
+	{ .str = "ARM_OP_VPRED_N", .val = ARM_OP_VPRED_N },
+	{ .str = "ARM_OP_VPRED_R", .val = ARM_OP_VPRED_R },
+	{ .str = "ARM_SETEND_BE", .val = ARM_SETEND_BE },
+	{ .str = "ARM_SETEND_INVALID", .val = ARM_SETEND_INVALID },
+	{ .str = "ARM_SETEND_LE", .val = ARM_SETEND_LE },
+	{ .str = "ARM_SFT_ASR", .val = ARM_SFT_ASR },
+	{ .str = "ARM_SFT_ASR_REG", .val = ARM_SFT_ASR_REG },
+	{ .str = "ARM_SFT_INVALID", .val = ARM_SFT_INVALID },
+	{ .str = "ARM_SFT_LSL", .val = ARM_SFT_LSL },
+	{ .str = "ARM_SFT_LSL_REG", .val = ARM_SFT_LSL_REG },
+	{ .str = "ARM_SFT_LSR", .val = ARM_SFT_LSR },
+	{ .str = "ARM_SFT_LSR_REG", .val = ARM_SFT_LSR_REG },
+	{ .str = "ARM_SFT_ROR", .val = ARM_SFT_ROR },
+	{ .str = "ARM_SFT_ROR_REG", .val = ARM_SFT_ROR_REG },
+	{ .str = "ARM_SFT_RRX", .val = ARM_SFT_RRX },
+	{ .str = "ARM_SFT_RRX_REG", .val = ARM_SFT_RRX_REG },
+	{ .str = "ARM_T", .val = ARM_T },
+	{ .str = "ARM_TE", .val = ARM_TE },
+	{ .str = "ARM_TEE", .val = ARM_TEE },
+	{ .str = "ARM_TEEE", .val = ARM_TEEE },
+	{ .str = "ARM_TEET", .val = ARM_TEET },
+	{ .str = "ARM_TET", .val = ARM_TET },
+	{ .str = "ARM_TETE", .val = ARM_TETE },
+	{ .str = "ARM_TETT", .val = ARM_TETT },
+	{ .str = "ARM_TT", .val = ARM_TT },
+	{ .str = "ARM_TTE", .val = ARM_TTE },
+	{ .str = "ARM_TTEE", .val = ARM_TTEE },
+	{ .str = "ARM_TTET", .val = ARM_TTET },
+	{ .str = "ARM_TTT", .val = ARM_TTT },
+	{ .str = "ARM_TTTE", .val = ARM_TTTE },
+	{ .str = "ARM_TTTT", .val = ARM_TTTT },
+	{ .str = "ARM_VECTORDATA_F16", .val = ARM_VECTORDATA_F16 },
+	{ .str = "ARM_VECTORDATA_F16F32", .val = ARM_VECTORDATA_F16F32 },
+	{ .str = "ARM_VECTORDATA_F16F64", .val = ARM_VECTORDATA_F16F64 },
+	{ .str = "ARM_VECTORDATA_F16S16", .val = ARM_VECTORDATA_F16S16 },
+	{ .str = "ARM_VECTORDATA_F16S32", .val = ARM_VECTORDATA_F16S32 },
+	{ .str = "ARM_VECTORDATA_F16U16", .val = ARM_VECTORDATA_F16U16 },
+	{ .str = "ARM_VECTORDATA_F16U32", .val = ARM_VECTORDATA_F16U32 },
+	{ .str = "ARM_VECTORDATA_F32", .val = ARM_VECTORDATA_F32 },
+	{ .str = "ARM_VECTORDATA_F32F16", .val = ARM_VECTORDATA_F32F16 },
+	{ .str = "ARM_VECTORDATA_F32F64", .val = ARM_VECTORDATA_F32F64 },
+	{ .str = "ARM_VECTORDATA_F32S16", .val = ARM_VECTORDATA_F32S16 },
+	{ .str = "ARM_VECTORDATA_F32S32", .val = ARM_VECTORDATA_F32S32 },
+	{ .str = "ARM_VECTORDATA_F32U16", .val = ARM_VECTORDATA_F32U16 },
+	{ .str = "ARM_VECTORDATA_F32U32", .val = ARM_VECTORDATA_F32U32 },
+	{ .str = "ARM_VECTORDATA_F64", .val = ARM_VECTORDATA_F64 },
+	{ .str = "ARM_VECTORDATA_F64F16", .val = ARM_VECTORDATA_F64F16 },
+	{ .str = "ARM_VECTORDATA_F64F32", .val = ARM_VECTORDATA_F64F32 },
+	{ .str = "ARM_VECTORDATA_F64S16", .val = ARM_VECTORDATA_F64S16 },
+	{ .str = "ARM_VECTORDATA_F64S32", .val = ARM_VECTORDATA_F64S32 },
+	{ .str = "ARM_VECTORDATA_F64U16", .val = ARM_VECTORDATA_F64U16 },
+	{ .str = "ARM_VECTORDATA_F64U32", .val = ARM_VECTORDATA_F64U32 },
+	{ .str = "ARM_VECTORDATA_I16", .val = ARM_VECTORDATA_I16 },
+	{ .str = "ARM_VECTORDATA_I32", .val = ARM_VECTORDATA_I32 },
+	{ .str = "ARM_VECTORDATA_I64", .val = ARM_VECTORDATA_I64 },
+	{ .str = "ARM_VECTORDATA_I8", .val = ARM_VECTORDATA_I8 },
+	{ .str = "ARM_VECTORDATA_INVALID", .val = ARM_VECTORDATA_INVALID },
+	{ .str = "ARM_VECTORDATA_P16", .val = ARM_VECTORDATA_P16 },
+	{ .str = "ARM_VECTORDATA_P8", .val = ARM_VECTORDATA_P8 },
+	{ .str = "ARM_VECTORDATA_S16", .val = ARM_VECTORDATA_S16 },
+	{ .str = "ARM_VECTORDATA_S16F16", .val = ARM_VECTORDATA_S16F16 },
+	{ .str = "ARM_VECTORDATA_S16F32", .val = ARM_VECTORDATA_S16F32 },
+	{ .str = "ARM_VECTORDATA_S16F64", .val = ARM_VECTORDATA_S16F64 },
+	{ .str = "ARM_VECTORDATA_S32", .val = ARM_VECTORDATA_S32 },
+	{ .str = "ARM_VECTORDATA_S32F16", .val = ARM_VECTORDATA_S32F16 },
+	{ .str = "ARM_VECTORDATA_S32F32", .val = ARM_VECTORDATA_S32F32 },
+	{ .str = "ARM_VECTORDATA_S32F64", .val = ARM_VECTORDATA_S32F64 },
+	{ .str = "ARM_VECTORDATA_S64", .val = ARM_VECTORDATA_S64 },
+	{ .str = "ARM_VECTORDATA_S8", .val = ARM_VECTORDATA_S8 },
+	{ .str = "ARM_VECTORDATA_U16", .val = ARM_VECTORDATA_U16 },
+	{ .str = "ARM_VECTORDATA_U16F16", .val = ARM_VECTORDATA_U16F16 },
+	{ .str = "ARM_VECTORDATA_U16F32", .val = ARM_VECTORDATA_U16F32 },
+	{ .str = "ARM_VECTORDATA_U16F64", .val = ARM_VECTORDATA_U16F64 },
+	{ .str = "ARM_VECTORDATA_U32", .val = ARM_VECTORDATA_U32 },
+	{ .str = "ARM_VECTORDATA_U32F16", .val = ARM_VECTORDATA_U32F16 },
+	{ .str = "ARM_VECTORDATA_U32F32", .val = ARM_VECTORDATA_U32F32 },
+	{ .str = "ARM_VECTORDATA_U32F64", .val = ARM_VECTORDATA_U32F64 },
+	{ .str = "ARM_VECTORDATA_U64", .val = ARM_VECTORDATA_U64 },
+	{ .str = "ARM_VECTORDATA_U8", .val = ARM_VECTORDATA_U8 },
+	{ .str = "Alpha_GRP_BRANCH_RELATIVE",
+	  .val = Alpha_GRP_BRANCH_RELATIVE },
+	{ .str = "Alpha_GRP_CALL", .val = Alpha_GRP_CALL },
+	{ .str = "Alpha_GRP_ENDING", .val = Alpha_GRP_ENDING },
+	{ .str = "Alpha_GRP_JUMP", .val = Alpha_GRP_JUMP },
+	{ .str = "BPF_EXT_LEN", .val = BPF_EXT_LEN },
+	{ .str = "BPF_GRP_ALU", .val = BPF_GRP_ALU },
+	{ .str = "BPF_GRP_CALL", .val = BPF_GRP_CALL },
+	{ .str = "BPF_GRP_JUMP", .val = BPF_GRP_JUMP },
+	{ .str = "BPF_GRP_LOAD", .val = BPF_GRP_LOAD },
+	{ .str = "BPF_GRP_MISC", .val = BPF_GRP_MISC },
+	{ .str = "BPF_GRP_RETURN", .val = BPF_GRP_RETURN },
+	{ .str = "BPF_GRP_STORE", .val = BPF_GRP_STORE },
+	{ .str = "BPF_OP_EXT", .val = BPF_OP_EXT },
+	{ .str = "BPF_OP_IMM", .val = BPF_OP_IMM },
+	{ .str = "BPF_OP_MEM", .val = BPF_OP_MEM },
+	{ .str = "BPF_OP_MMEM", .val = BPF_OP_MMEM },
+	{ .str = "BPF_OP_MSH", .val = BPF_OP_MSH },
+	{ .str = "BPF_OP_OFF", .val = BPF_OP_OFF },
+	{ .str = "BPF_OP_REG", .val = BPF_OP_REG },
+	{ .str = "CS_AC_READ", .val = CS_AC_READ },
+	{ .str = "CS_AC_READ_WRITE", .val = CS_AC_READ_WRITE },
+	{ .str = "CS_AC_WRITE", .val = CS_AC_WRITE },
+	{ .str = "EVM_GRP_HALT", .val = EVM_GRP_HALT },
+	{ .str = "EVM_GRP_JUMP", .val = EVM_GRP_JUMP },
+	{ .str = "EVM_GRP_MATH", .val = EVM_GRP_MATH },
+	{ .str = "EVM_GRP_MEM_READ", .val = EVM_GRP_MEM_READ },
+	{ .str = "EVM_GRP_MEM_WRITE", .val = EVM_GRP_MEM_WRITE },
+	{ .str = "EVM_GRP_STACK_READ", .val = EVM_GRP_STACK_READ },
+	{ .str = "EVM_GRP_STACK_WRITE", .val = EVM_GRP_STACK_WRITE },
+	{ .str = "EVM_GRP_STORE_READ", .val = EVM_GRP_STORE_READ },
+	{ .str = "EVM_GRP_STORE_WRITE", .val = EVM_GRP_STORE_WRITE },
+	{ .str = "HPPA_GRP_ASSIST", .val = HPPA_GRP_ASSIST },
+	{ .str = "HPPA_GRP_BRANCH", .val = HPPA_GRP_BRANCH },
+	{ .str = "HPPA_GRP_COMPUTATION", .val = HPPA_GRP_COMPUTATION },
+	{ .str = "HPPA_GRP_FLOAT", .val = HPPA_GRP_FLOAT },
+	{ .str = "HPPA_GRP_LONG_IMM", .val = HPPA_GRP_LONG_IMM },
+	{ .str = "HPPA_GRP_MEM_REF", .val = HPPA_GRP_MEM_REF },
+	{ .str = "HPPA_GRP_MULTIMEDIA", .val = HPPA_GRP_MULTIMEDIA },
+	{ .str = "HPPA_GRP_PERFMON", .val = HPPA_GRP_PERFMON },
+	{ .str = "HPPA_GRP_SYSCTRL", .val = HPPA_GRP_SYSCTRL },
+	{ .str = "HPPA_OP_DISP", .val = HPPA_OP_DISP },
+	{ .str = "HPPA_OP_IDX_REG", .val = HPPA_OP_IDX_REG },
+	{ .str = "HPPA_OP_IMM", .val = HPPA_OP_IMM },
+	{ .str = "HPPA_OP_MEM", .val = HPPA_OP_MEM },
+	{ .str = "HPPA_OP_REG", .val = HPPA_OP_REG },
+	{ .str = "HPPA_OP_TARGET", .val = HPPA_OP_TARGET },
+	{ .str = "LOONGARCH_FEATURE_HASLAGLOBALWITHABS",
+	  .val = LOONGARCH_FEATURE_HASLAGLOBALWITHABS },
+	{ .str = "LOONGARCH_FEATURE_HASLAGLOBALWITHPCREL",
+	  .val = LOONGARCH_FEATURE_HASLAGLOBALWITHPCREL },
+	{ .str = "LOONGARCH_FEATURE_HASLALOCALWITHABS",
+	  .val = LOONGARCH_FEATURE_HASLALOCALWITHABS },
+	{ .str = "LOONGARCH_FEATURE_ISLA32", .val = LOONGARCH_FEATURE_ISLA32 },
+	{ .str = "LOONGARCH_FEATURE_ISLA64", .val = LOONGARCH_FEATURE_ISLA64 },
+	{ .str = "LOONGARCH_GRP_BRANCH_RELATIVE",
+	  .val = LOONGARCH_GRP_BRANCH_RELATIVE },
+	{ .str = "LOONGARCH_GRP_CALL", .val = LOONGARCH_GRP_CALL },
+	{ .str = "LOONGARCH_GRP_INT", .val = LOONGARCH_GRP_INT },
+	{ .str = "LOONGARCH_GRP_IRET", .val = LOONGARCH_GRP_IRET },
+	{ .str = "LOONGARCH_GRP_JUMP", .val = LOONGARCH_GRP_JUMP },
+	{ .str = "LOONGARCH_GRP_PRIVILEGE", .val = LOONGARCH_GRP_PRIVILEGE },
+	{ .str = "LOONGARCH_GRP_RET", .val = LOONGARCH_GRP_RET },
+	{ .str = "LOONGARCH_INSN_FORM_FMT1RI13_VI",
+	  .val = LOONGARCH_INSN_FORM_FMT1RI13_VI },
+	{ .str = "LOONGARCH_INSN_FORM_FMT1RI13_XI",
+	  .val = LOONGARCH_INSN_FORM_FMT1RI13_XI },
+	{ .str = "LOONGARCH_INSN_FORM_FMT1RI20",
+	  .val = LOONGARCH_INSN_FORM_FMT1RI20 },
+	{ .str = "LOONGARCH_INSN_FORM_FMT1RI21",
+	  .val = LOONGARCH_INSN_FORM_FMT1RI21 },
+	{ .str = "LOONGARCH_INSN_FORM_FMT1RI4",
+	  .val = LOONGARCH_INSN_FORM_FMT1RI4 },
+	{ .str = "LOONGARCH_INSN_FORM_FMT1RI5I8",
+	  .val = LOONGARCH_INSN_FORM_FMT1RI5I8 },
+	{ .str = "LOONGARCH_INSN_FORM_FMT1RI8",
+	  .val = LOONGARCH_INSN_FORM_FMT1RI8 },
+	{ .str = "LOONGARCH_INSN_FORM_FMT2R",
+	  .val = LOONGARCH_INSN_FORM_FMT2R },
+	{ .str = "LOONGARCH_INSN_FORM_FMT2RI10_VRI",
+	  .val = LOONGARCH_INSN_FORM_FMT2RI10_VRI },
+	{ .str = "LOONGARCH_INSN_FORM_FMT2RI10_XRI",
+	  .val = LOONGARCH_INSN_FORM_FMT2RI10_XRI },
+	{ .str = "LOONGARCH_INSN_FORM_FMT2RI11_VRI",
+	  .val = LOONGARCH_INSN_FORM_FMT2RI11_VRI },
+	{ .str = "LOONGARCH_INSN_FORM_FMT2RI11_XRI",
+	  .val = LOONGARCH_INSN_FORM_FMT2RI11_XRI },
+	{ .str = "LOONGARCH_INSN_FORM_FMT2RI12",
+	  .val = LOONGARCH_INSN_FORM_FMT2RI12 },
+	{ .str = "LOONGARCH_INSN_FORM_FMT2RI12_VRI",
+	  .val = LOONGARCH_INSN_FORM_FMT2RI12_VRI },
+	{ .str = "LOONGARCH_INSN_FORM_FMT2RI12_XRI",
+	  .val = LOONGARCH_INSN_FORM_FMT2RI12_XRI },
+	{ .str = "LOONGARCH_INSN_FORM_FMT2RI14",
+	  .val = LOONGARCH_INSN_FORM_FMT2RI14 },
+	{ .str = "LOONGARCH_INSN_FORM_FMT2RI16",
+	  .val = LOONGARCH_INSN_FORM_FMT2RI16 },
+	{ .str = "LOONGARCH_INSN_FORM_FMT2RI1_RVI",
+	  .val = LOONGARCH_INSN_FORM_FMT2RI1_RVI },
+	{ .str = "LOONGARCH_INSN_FORM_FMT2RI1_VRI",
+	  .val = LOONGARCH_INSN_FORM_FMT2RI1_VRI },
+	{ .str = "LOONGARCH_INSN_FORM_FMT2RI1_VVI",
+	  .val = LOONGARCH_INSN_FORM_FMT2RI1_VVI },
+	{ .str = "LOONGARCH_INSN_FORM_FMT2RI1_XXI",
+	  .val = LOONGARCH_INSN_FORM_FMT2RI1_XXI },
+	{ .str = "LOONGARCH_INSN_FORM_FMT2RI2_RVI",
+	  .val = LOONGARCH_INSN_FORM_FMT2RI2_RVI },
+	{ .str = "LOONGARCH_INSN_FORM_FMT2RI2_RXI",
+	  .val = LOONGARCH_INSN_FORM_FMT2RI2_RXI },
+	{ .str = "LOONGARCH_INSN_FORM_FMT2RI2_VRI",
+	  .val = LOONGARCH_INSN_FORM_FMT2RI2_VRI },
+	{ .str = "LOONGARCH_INSN_FORM_FMT2RI2_VVI",
+	  .val = LOONGARCH_INSN_FORM_FMT2RI2_VVI },
+	{ .str = "LOONGARCH_INSN_FORM_FMT2RI2_XRI",
+	  .val = LOONGARCH_INSN_FORM_FMT2RI2_XRI },
+	{ .str = "LOONGARCH_INSN_FORM_FMT2RI2_XXI",
+	  .val = LOONGARCH_INSN_FORM_FMT2RI2_XXI },
+	{ .str = "LOONGARCH_INSN_FORM_FMT2RI3",
+	  .val = LOONGARCH_INSN_FORM_FMT2RI3 },
+	{ .str = "LOONGARCH_INSN_FORM_FMT2RI3_RVI",
+	  .val = LOONGARCH_INSN_FORM_FMT2RI3_RVI },
+	{ .str = "LOONGARCH_INSN_FORM_FMT2RI3_RXI",
+	  .val = LOONGARCH_INSN_FORM_FMT2RI3_RXI },
+	{ .str = "LOONGARCH_INSN_FORM_FMT2RI3_VRI",
+	  .val = LOONGARCH_INSN_FORM_FMT2RI3_VRI },
+	{ .str = "LOONGARCH_INSN_FORM_FMT2RI3_VVI",
+	  .val = LOONGARCH_INSN_FORM_FMT2RI3_VVI },
+	{ .str = "LOONGARCH_INSN_FORM_FMT2RI3_XRI",
+	  .val = LOONGARCH_INSN_FORM_FMT2RI3_XRI },
+	{ .str = "LOONGARCH_INSN_FORM_FMT2RI3_XXI",
+	  .val = LOONGARCH_INSN_FORM_FMT2RI3_XXI },
+	{ .str = "LOONGARCH_INSN_FORM_FMT2RI4",
+	  .val = LOONGARCH_INSN_FORM_FMT2RI4 },
+	{ .str = "LOONGARCH_INSN_FORM_FMT2RI4_RVI",
+	  .val = LOONGARCH_INSN_FORM_FMT2RI4_RVI },
+	{ .str = "LOONGARCH_INSN_FORM_FMT2RI4_VRI",
+	  .val = LOONGARCH_INSN_FORM_FMT2RI4_VRI },
+	{ .str = "LOONGARCH_INSN_FORM_FMT2RI4_VVI",
+	  .val = LOONGARCH_INSN_FORM_FMT2RI4_VVI },
+	{ .str = "LOONGARCH_INSN_FORM_FMT2RI4_XXI",
+	  .val = LOONGARCH_INSN_FORM_FMT2RI4_XXI },
+	{ .str = "LOONGARCH_INSN_FORM_FMT2RI5",
+	  .val = LOONGARCH_INSN_FORM_FMT2RI5 },
+	{ .str = "LOONGARCH_INSN_FORM_FMT2RI5_VVI",
+	  .val = LOONGARCH_INSN_FORM_FMT2RI5_VVI },
+	{ .str = "LOONGARCH_INSN_FORM_FMT2RI5_XXI",
+	  .val = LOONGARCH_INSN_FORM_FMT2RI5_XXI },
+	{ .str = "LOONGARCH_INSN_FORM_FMT2RI6",
+	  .val = LOONGARCH_INSN_FORM_FMT2RI6 },
+	{ .str = "LOONGARCH_INSN_FORM_FMT2RI6_VVI",
+	  .val = LOONGARCH_INSN_FORM_FMT2RI6_VVI },
+	{ .str = "LOONGARCH_INSN_FORM_FMT2RI6_XXI",
+	  .val = LOONGARCH_INSN_FORM_FMT2RI6_XXI },
+	{ .str = "LOONGARCH_INSN_FORM_FMT2RI7_VVI",
+	  .val = LOONGARCH_INSN_FORM_FMT2RI7_VVI },
+	{ .str = "LOONGARCH_INSN_FORM_FMT2RI7_XXI",
+	  .val = LOONGARCH_INSN_FORM_FMT2RI7_XXI },
+	{ .str = "LOONGARCH_INSN_FORM_FMT2RI8",
+	  .val = LOONGARCH_INSN_FORM_FMT2RI8 },
+	{ .str = "LOONGARCH_INSN_FORM_FMT2RI8I1_VRII",
+	  .val = LOONGARCH_INSN_FORM_FMT2RI8I1_VRII },
+	{ .str = "LOONGARCH_INSN_FORM_FMT2RI8I2_VRII",
+	  .val = LOONGARCH_INSN_FORM_FMT2RI8I2_VRII },
+	{ .str = "LOONGARCH_INSN_FORM_FMT2RI8I2_XRII",
+	  .val = LOONGARCH_INSN_FORM_FMT2RI8I2_XRII },
+	{ .str = "LOONGARCH_INSN_FORM_FMT2RI8I3_VRII",
+	  .val = LOONGARCH_INSN_FORM_FMT2RI8I3_VRII },
+	{ .str = "LOONGARCH_INSN_FORM_FMT2RI8I3_XRII",
+	  .val = LOONGARCH_INSN_FORM_FMT2RI8I3_XRII },
+	{ .str = "LOONGARCH_INSN_FORM_FMT2RI8I4_VRII",
+	  .val = LOONGARCH_INSN_FORM_FMT2RI8I4_VRII },
+	{ .str = "LOONGARCH_INSN_FORM_FMT2RI8I4_XRII",
+	  .val = LOONGARCH_INSN_FORM_FMT2RI8I4_XRII },
+	{ .str = "LOONGARCH_INSN_FORM_FMT2RI8I5_XRII",
+	  .val = LOONGARCH_INSN_FORM_FMT2RI8I5_XRII },
+	{ .str = "LOONGARCH_INSN_FORM_FMT2RI8_VVI",
+	  .val = LOONGARCH_INSN_FORM_FMT2RI8_VVI },
+	{ .str = "LOONGARCH_INSN_FORM_FMT2RI8_XXI",
+	  .val = LOONGARCH_INSN_FORM_FMT2RI8_XXI },
+	{ .str = "LOONGARCH_INSN_FORM_FMT2RI9_VRI",
+	  .val = LOONGARCH_INSN_FORM_FMT2RI9_VRI },
+	{ .str = "LOONGARCH_INSN_FORM_FMT2RI9_XRI",
+	  .val = LOONGARCH_INSN_FORM_FMT2RI9_XRI },
+	{ .str = "LOONGARCH_INSN_FORM_FMT2R_CV",
+	  .val = LOONGARCH_INSN_FORM_FMT2R_CV },
+	{ .str = "LOONGARCH_INSN_FORM_FMT2R_CX",
+	  .val = LOONGARCH_INSN_FORM_FMT2R_CX },
+	{ .str = "LOONGARCH_INSN_FORM_FMT2R_VR",
+	  .val = LOONGARCH_INSN_FORM_FMT2R_VR },
+	{ .str = "LOONGARCH_INSN_FORM_FMT2R_VV",
+	  .val = LOONGARCH_INSN_FORM_FMT2R_VV },
+	{ .str = "LOONGARCH_INSN_FORM_FMT2R_XR",
+	  .val = LOONGARCH_INSN_FORM_FMT2R_XR },
+	{ .str = "LOONGARCH_INSN_FORM_FMT2R_XX",
+	  .val = LOONGARCH_INSN_FORM_FMT2R_XX },
+	{ .str = "LOONGARCH_INSN_FORM_FMT3R",
+	  .val = LOONGARCH_INSN_FORM_FMT3R },
+	{ .str = "LOONGARCH_INSN_FORM_FMT3RI2",
+	  .val = LOONGARCH_INSN_FORM_FMT3RI2 },
+	{ .str = "LOONGARCH_INSN_FORM_FMT3RI3",
+	  .val = LOONGARCH_INSN_FORM_FMT3RI3 },
+	{ .str = "LOONGARCH_INSN_FORM_FMT3R_VRR",
+	  .val = LOONGARCH_INSN_FORM_FMT3R_VRR },
+	{ .str = "LOONGARCH_INSN_FORM_FMT3R_VVR",
+	  .val = LOONGARCH_INSN_FORM_FMT3R_VVR },
+	{ .str = "LOONGARCH_INSN_FORM_FMT3R_VVV",
+	  .val = LOONGARCH_INSN_FORM_FMT3R_VVV },
+	{ .str = "LOONGARCH_INSN_FORM_FMT3R_XRR",
+	  .val = LOONGARCH_INSN_FORM_FMT3R_XRR },
+	{ .str = "LOONGARCH_INSN_FORM_FMT3R_XXR",
+	  .val = LOONGARCH_INSN_FORM_FMT3R_XXR },
+	{ .str = "LOONGARCH_INSN_FORM_FMT3R_XXX",
+	  .val = LOONGARCH_INSN_FORM_FMT3R_XXX },
+	{ .str = "LOONGARCH_INSN_FORM_FMT4R_VVVV",
+	  .val = LOONGARCH_INSN_FORM_FMT4R_VVVV },
+	{ .str = "LOONGARCH_INSN_FORM_FMT4R_XXXX",
+	  .val = LOONGARCH_INSN_FORM_FMT4R_XXXX },
+	{ .str = "LOONGARCH_INSN_FORM_FMTASRT",
+	  .val = LOONGARCH_INSN_FORM_FMTASRT },
+	{ .str = "LOONGARCH_INSN_FORM_FMTBSTR_D",
+	  .val = LOONGARCH_INSN_FORM_FMTBSTR_D },
+	{ .str = "LOONGARCH_INSN_FORM_FMTBSTR_W",
+	  .val = LOONGARCH_INSN_FORM_FMTBSTR_W },
+	{ .str = "LOONGARCH_INSN_FORM_FMTCACOP",
+	  .val = LOONGARCH_INSN_FORM_FMTCACOP },
+	{ .str = "LOONGARCH_INSN_FORM_FMTCSR",
+	  .val = LOONGARCH_INSN_FORM_FMTCSR },
+	{ .str = "LOONGARCH_INSN_FORM_FMTCSRXCHG",
+	  .val = LOONGARCH_INSN_FORM_FMTCSRXCHG },
+	{ .str = "LOONGARCH_INSN_FORM_FMTGR2SCR",
+	  .val = LOONGARCH_INSN_FORM_FMTGR2SCR },
+	{ .str = "LOONGARCH_INSN_FORM_FMTI15",
+	  .val = LOONGARCH_INSN_FORM_FMTI15 },
+	{ .str = "LOONGARCH_INSN_FORM_FMTI26",
+	  .val = LOONGARCH_INSN_FORM_FMTI26 },
+	{ .str = "LOONGARCH_INSN_FORM_FMTI32",
+	  .val = LOONGARCH_INSN_FORM_FMTI32 },
+	{ .str = "LOONGARCH_INSN_FORM_FMTINVTLB",
+	  .val = LOONGARCH_INSN_FORM_FMTINVTLB },
+	{ .str = "LOONGARCH_INSN_FORM_FMTJISCR",
+	  .val = LOONGARCH_INSN_FORM_FMTJISCR },
+	{ .str = "LOONGARCH_INSN_FORM_FMTLDPTE",
+	  .val = LOONGARCH_INSN_FORM_FMTLDPTE },
+	{ .str = "LOONGARCH_INSN_FORM_FMTMFTOP",
+	  .val = LOONGARCH_INSN_FORM_FMTMFTOP },
+	{ .str = "LOONGARCH_INSN_FORM_FMTMTTOP",
+	  .val = LOONGARCH_INSN_FORM_FMTMTTOP },
+	{ .str = "LOONGARCH_INSN_FORM_FMTPRELD",
+	  .val = LOONGARCH_INSN_FORM_FMTPRELD },
+	{ .str = "LOONGARCH_INSN_FORM_FMTPRELDX",
+	  .val = LOONGARCH_INSN_FORM_FMTPRELDX },
+	{ .str = "LOONGARCH_INSN_FORM_FMTSCR2GR",
+	  .val = LOONGARCH_INSN_FORM_FMTSCR2GR },
+	{ .str = "LOONGARCH_INSN_FORM_FPFMT2R",
+	  .val = LOONGARCH_INSN_FORM_FPFMT2R },
+	{ .str = "LOONGARCH_INSN_FORM_FPFMT2RI12",
+	  .val = LOONGARCH_INSN_FORM_FPFMT2RI12 },
+	{ .str = "LOONGARCH_INSN_FORM_FPFMT3R",
+	  .val = LOONGARCH_INSN_FORM_FPFMT3R },
+	{ .str = "LOONGARCH_INSN_FORM_FPFMT4R",
+	  .val = LOONGARCH_INSN_FORM_FPFMT4R },
+	{ .str = "LOONGARCH_INSN_FORM_FPFMTBR",
+	  .val = LOONGARCH_INSN_FORM_FPFMTBR },
+	{ .str = "LOONGARCH_INSN_FORM_FPFMTFCMP",
+	  .val = LOONGARCH_INSN_FORM_FPFMTFCMP },
+	{ .str = "LOONGARCH_INSN_FORM_FPFMTFSEL",
+	  .val = LOONGARCH_INSN_FORM_FPFMTFSEL },
+	{ .str = "LOONGARCH_INSN_FORM_FPFMTMEM",
+	  .val = LOONGARCH_INSN_FORM_FPFMTMEM },
+	{ .str = "LOONGARCH_INSN_FORM_FPFMTMOV",
+	  .val = LOONGARCH_INSN_FORM_FPFMTMOV },
+	{ .str = "LOONGARCH_INSN_FORM_NODSTFMT1R",
+	  .val = LOONGARCH_INSN_FORM_NODSTFMT1R },
+	{ .str = "LOONGARCH_INSN_FORM_NODSTFMT1RI3",
+	  .val = LOONGARCH_INSN_FORM_NODSTFMT1RI3 },
+	{ .str = "LOONGARCH_INSN_FORM_NODSTFMT1RI4",
+	  .val = LOONGARCH_INSN_FORM_NODSTFMT1RI4 },
+	{ .str = "LOONGARCH_INSN_FORM_NODSTFMT1RI5",
+	  .val = LOONGARCH_INSN_FORM_NODSTFMT1RI5 },
+	{ .str = "LOONGARCH_INSN_FORM_NODSTFMT1RI5I4",
+	  .val = LOONGARCH_INSN_FORM_NODSTFMT1RI5I4 },
+	{ .str = "LOONGARCH_INSN_FORM_NODSTFMT1RI6",
+	  .val = LOONGARCH_INSN_FORM_NODSTFMT1RI6 },
+	{ .str = "LOONGARCH_INSN_FORM_NODSTFMT2R",
+	  .val = LOONGARCH_INSN_FORM_NODSTFMT2R },
+	{ .str = "LOONGARCH_INSN_FORM_NODSTFMT2RI4",
+	  .val = LOONGARCH_INSN_FORM_NODSTFMT2RI4 },
+	{ .str = "LOONGARCH_INSN_FORM_PSEUDO",
+	  .val = LOONGARCH_INSN_FORM_PSEUDO },
+	{ .str = "LOONGARCH_OP_IMM", .val = LOONGARCH_OP_IMM },
+	{ .str = "LOONGARCH_OP_MEM", .val = LOONGARCH_OP_MEM },
+	{ .str = "LOONGARCH_OP_REG", .val = LOONGARCH_OP_REG },
+	{ .str = "M680X_FIRST_OP_IN_MNEM", .val = M680X_FIRST_OP_IN_MNEM },
+	{ .str = "M680X_GRP_BRAREL", .val = M680X_GRP_BRAREL },
+	{ .str = "M680X_GRP_CALL", .val = M680X_GRP_CALL },
+	{ .str = "M680X_GRP_INT", .val = M680X_GRP_INT },
+	{ .str = "M680X_GRP_IRET", .val = M680X_GRP_IRET },
+	{ .str = "M680X_GRP_JUMP", .val = M680X_GRP_JUMP },
+	{ .str = "M680X_GRP_PRIV", .val = M680X_GRP_PRIV },
+	{ .str = "M680X_GRP_RET", .val = M680X_GRP_RET },
+	{ .str = "M680X_IDX_INDIRECT", .val = M680X_IDX_INDIRECT },
+	{ .str = "M680X_IDX_NO_COMMA", .val = M680X_IDX_NO_COMMA },
+	{ .str = "M680X_IDX_POST_INC_DEC", .val = M680X_IDX_POST_INC_DEC },
+	{ .str = "M680X_OFFSET_BITS_16", .val = M680X_OFFSET_BITS_16 },
+	{ .str = "M680X_OFFSET_BITS_5", .val = M680X_OFFSET_BITS_5 },
+	{ .str = "M680X_OFFSET_BITS_8", .val = M680X_OFFSET_BITS_8 },
+	{ .str = "M680X_OFFSET_BITS_9", .val = M680X_OFFSET_BITS_9 },
+	{ .str = "M680X_OFFSET_NONE", .val = M680X_OFFSET_NONE },
+	{ .str = "M680X_OP_CONSTANT", .val = M680X_OP_CONSTANT },
+	{ .str = "M680X_OP_DIRECT", .val = M680X_OP_DIRECT },
+	{ .str = "M680X_OP_EXTENDED", .val = M680X_OP_EXTENDED },
+	{ .str = "M680X_OP_IMMEDIATE", .val = M680X_OP_IMMEDIATE },
+	{ .str = "M680X_OP_INDEXED", .val = M680X_OP_INDEXED },
+	{ .str = "M680X_OP_REGISTER", .val = M680X_OP_REGISTER },
+	{ .str = "M680X_OP_RELATIVE", .val = M680X_OP_RELATIVE },
+	{ .str = "M680X_SECOND_OP_IN_MNEM", .val = M680X_SECOND_OP_IN_MNEM },
+	{ .str = "M68K_AM_ABSOLUTE_DATA_LONG",
+	  .val = M68K_AM_ABSOLUTE_DATA_LONG },
+	{ .str = "M68K_AM_ABSOLUTE_DATA_SHORT",
+	  .val = M68K_AM_ABSOLUTE_DATA_SHORT },
+	{ .str = "M68K_AM_AREGI_INDEX_8_BIT_DISP",
+	  .val = M68K_AM_AREGI_INDEX_8_BIT_DISP },
+	{ .str = "M68K_AM_AREGI_INDEX_BASE_DISP",
+	  .val = M68K_AM_AREGI_INDEX_BASE_DISP },
+	{ .str = "M68K_AM_BRANCH_DISPLACEMENT",
+	  .val = M68K_AM_BRANCH_DISPLACEMENT },
+	{ .str = "M68K_AM_IMMEDIATE", .val = M68K_AM_IMMEDIATE },
+	{ .str = "M68K_AM_MEMI_POST_INDEX", .val = M68K_AM_MEMI_POST_INDEX },
+	{ .str = "M68K_AM_MEMI_PRE_INDEX", .val = M68K_AM_MEMI_PRE_INDEX },
+	{ .str = "M68K_AM_NONE", .val = M68K_AM_NONE },
+	{ .str = "M68K_AM_PCI_DISP", .val = M68K_AM_PCI_DISP },
+	{ .str = "M68K_AM_PCI_INDEX_8_BIT_DISP",
+	  .val = M68K_AM_PCI_INDEX_8_BIT_DISP },
+	{ .str = "M68K_AM_PCI_INDEX_BASE_DISP",
+	  .val = M68K_AM_PCI_INDEX_BASE_DISP },
+	{ .str = "M68K_AM_PC_MEMI_POST_INDEX",
+	  .val = M68K_AM_PC_MEMI_POST_INDEX },
+	{ .str = "M68K_AM_PC_MEMI_PRE_INDEX",
+	  .val = M68K_AM_PC_MEMI_PRE_INDEX },
+	{ .str = "M68K_AM_REGI_ADDR", .val = M68K_AM_REGI_ADDR },
+	{ .str = "M68K_AM_REGI_ADDR_DISP", .val = M68K_AM_REGI_ADDR_DISP },
+	{ .str = "M68K_AM_REGI_ADDR_POST_INC",
+	  .val = M68K_AM_REGI_ADDR_POST_INC },
+	{ .str = "M68K_AM_REGI_ADDR_PRE_DEC",
+	  .val = M68K_AM_REGI_ADDR_PRE_DEC },
+	{ .str = "M68K_AM_REG_DIRECT_ADDR", .val = M68K_AM_REG_DIRECT_ADDR },
+	{ .str = "M68K_AM_REG_DIRECT_DATA", .val = M68K_AM_REG_DIRECT_DATA },
+	{ .str = "M68K_CPU_SIZE_BYTE", .val = M68K_CPU_SIZE_BYTE },
+	{ .str = "M68K_CPU_SIZE_LONG", .val = M68K_CPU_SIZE_LONG },
+	{ .str = "M68K_CPU_SIZE_NONE", .val = M68K_CPU_SIZE_NONE },
+	{ .str = "M68K_CPU_SIZE_WORD", .val = M68K_CPU_SIZE_WORD },
+	{ .str = "M68K_FPU_SIZE_DOUBLE", .val = M68K_FPU_SIZE_DOUBLE },
+	{ .str = "M68K_FPU_SIZE_EXTENDED", .val = M68K_FPU_SIZE_EXTENDED },
+	{ .str = "M68K_FPU_SIZE_NONE", .val = M68K_FPU_SIZE_NONE },
+	{ .str = "M68K_FPU_SIZE_SINGLE", .val = M68K_FPU_SIZE_SINGLE },
+	{ .str = "M68K_GRP_BRANCH_RELATIVE", .val = M68K_GRP_BRANCH_RELATIVE },
+	{ .str = "M68K_GRP_IRET", .val = M68K_GRP_IRET },
+	{ .str = "M68K_GRP_JUMP", .val = M68K_GRP_JUMP },
+	{ .str = "M68K_GRP_RET", .val = M68K_GRP_RET },
+	{ .str = "M68K_OP_BR_DISP", .val = M68K_OP_BR_DISP },
+	{ .str = "M68K_OP_BR_DISP_SIZE_BYTE",
+	  .val = M68K_OP_BR_DISP_SIZE_BYTE },
+	{ .str = "M68K_OP_BR_DISP_SIZE_LONG",
+	  .val = M68K_OP_BR_DISP_SIZE_LONG },
+	{ .str = "M68K_OP_BR_DISP_SIZE_WORD",
+	  .val = M68K_OP_BR_DISP_SIZE_WORD },
+	{ .str = "M68K_OP_FP_DOUBLE", .val = M68K_OP_FP_DOUBLE },
+	{ .str = "M68K_OP_FP_SINGLE", .val = M68K_OP_FP_SINGLE },
+	{ .str = "M68K_OP_IMM", .val = M68K_OP_IMM },
+	{ .str = "M68K_OP_MEM", .val = M68K_OP_MEM },
+	{ .str = "M68K_OP_REG", .val = M68K_OP_REG },
+	{ .str = "M68K_OP_REG_BITS", .val = M68K_OP_REG_BITS },
+	{ .str = "M68K_OP_REG_PAIR", .val = M68K_OP_REG_PAIR },
+	{ .str = "M68K_SIZE_TYPE_CPU", .val = M68K_SIZE_TYPE_CPU },
+	{ .str = "M68K_SIZE_TYPE_FPU", .val = M68K_SIZE_TYPE_FPU },
+	{ .str = "MIPS_OP_IMM", .val = MIPS_OP_IMM },
+	{ .str = "MIPS_OP_MEM", .val = MIPS_OP_MEM },
+	{ .str = "MIPS_OP_REG", .val = MIPS_OP_REG },
+	{ .str = "MOS65XX_AM_ABS", .val = MOS65XX_AM_ABS },
+	{ .str = "MOS65XX_AM_ABS_IND", .val = MOS65XX_AM_ABS_IND },
+	{ .str = "MOS65XX_AM_ABS_IND_LONG", .val = MOS65XX_AM_ABS_IND_LONG },
+	{ .str = "MOS65XX_AM_ABS_LONG", .val = MOS65XX_AM_ABS_LONG },
+	{ .str = "MOS65XX_AM_ABS_LONG_X", .val = MOS65XX_AM_ABS_LONG_X },
+	{ .str = "MOS65XX_AM_ABS_X", .val = MOS65XX_AM_ABS_X },
+	{ .str = "MOS65XX_AM_ABS_X_IND", .val = MOS65XX_AM_ABS_X_IND },
+	{ .str = "MOS65XX_AM_ABS_Y", .val = MOS65XX_AM_ABS_Y },
+	{ .str = "MOS65XX_AM_ACC", .val = MOS65XX_AM_ACC },
+	{ .str = "MOS65XX_AM_BLOCK", .val = MOS65XX_AM_BLOCK },
+	{ .str = "MOS65XX_AM_IMM", .val = MOS65XX_AM_IMM },
+	{ .str = "MOS65XX_AM_IMP", .val = MOS65XX_AM_IMP },
+	{ .str = "MOS65XX_AM_INT", .val = MOS65XX_AM_INT },
+	{ .str = "MOS65XX_AM_REL", .val = MOS65XX_AM_REL },
+	{ .str = "MOS65XX_AM_SR", .val = MOS65XX_AM_SR },
+	{ .str = "MOS65XX_AM_SR_IND_Y", .val = MOS65XX_AM_SR_IND_Y },
+	{ .str = "MOS65XX_AM_ZP", .val = MOS65XX_AM_ZP },
+	{ .str = "MOS65XX_AM_ZP_IND", .val = MOS65XX_AM_ZP_IND },
+	{ .str = "MOS65XX_AM_ZP_IND_LONG", .val = MOS65XX_AM_ZP_IND_LONG },
+	{ .str = "MOS65XX_AM_ZP_IND_LONG_Y", .val = MOS65XX_AM_ZP_IND_LONG_Y },
+	{ .str = "MOS65XX_AM_ZP_IND_Y", .val = MOS65XX_AM_ZP_IND_Y },
+	{ .str = "MOS65XX_AM_ZP_REL", .val = MOS65XX_AM_ZP_REL },
+	{ .str = "MOS65XX_AM_ZP_X", .val = MOS65XX_AM_ZP_X },
+	{ .str = "MOS65XX_AM_ZP_X_IND", .val = MOS65XX_AM_ZP_X_IND },
+	{ .str = "MOS65XX_AM_ZP_Y", .val = MOS65XX_AM_ZP_Y },
+	{ .str = "MOS65XX_GRP_BRANCH_RELATIVE",
+	  .val = MOS65XX_GRP_BRANCH_RELATIVE },
+	{ .str = "MOS65XX_GRP_CALL", .val = MOS65XX_GRP_CALL },
+	{ .str = "MOS65XX_GRP_INT", .val = MOS65XX_GRP_INT },
+	{ .str = "MOS65XX_GRP_IRET", .val = MOS65XX_GRP_IRET },
+	{ .str = "MOS65XX_GRP_JUMP", .val = MOS65XX_GRP_JUMP },
+	{ .str = "MOS65XX_GRP_RET", .val = MOS65XX_GRP_RET },
+	{ .str = "MOS65XX_OP_IMM", .val = MOS65XX_OP_IMM },
+	{ .str = "MOS65XX_OP_MEM", .val = MOS65XX_OP_MEM },
+	{ .str = "MOS65XX_OP_REG", .val = MOS65XX_OP_REG },
+	{ .str = "PPC_BH_INVALID", .val = PPC_BH_INVALID },
+	{ .str = "PPC_BH_NOT_PREDICTABLE", .val = PPC_BH_NOT_PREDICTABLE },
+	{ .str = "PPC_BH_NO_SUBROUTINE_RET", .val = PPC_BH_NO_SUBROUTINE_RET },
+	{ .str = "PPC_BH_RESERVED", .val = PPC_BH_RESERVED },
+	{ .str = "PPC_BH_SUBROUTINE_RET", .val = PPC_BH_SUBROUTINE_RET },
+	{ .str = "PPC_BI_GT", .val = PPC_BI_GT },
+	{ .str = "PPC_BI_LT", .val = PPC_BI_LT },
+	{ .str = "PPC_BI_SO", .val = PPC_BI_SO },
+	{ .str = "PPC_BI_Z", .val = PPC_BI_Z },
+	{ .str = "PPC_BO_CR_CMP", .val = PPC_BO_CR_CMP },
+	{ .str = "PPC_BO_CTR_CMP", .val = PPC_BO_CTR_CMP },
+	{ .str = "PPC_BO_DECR_CTR", .val = PPC_BO_DECR_CTR },
+	{ .str = "PPC_BO_T", .val = PPC_BO_T },
+	{ .str = "PPC_BO_TEST_CR", .val = PPC_BO_TEST_CR },
+	{ .str = "PPC_BR_HINT_MASK", .val = PPC_BR_HINT_MASK },
+	{ .str = "PPC_BR_NOT_GIVEN", .val = PPC_BR_NOT_GIVEN },
+	{ .str = "PPC_BR_NOT_TAKEN", .val = PPC_BR_NOT_TAKEN },
+	{ .str = "PPC_BR_RESERVED", .val = PPC_BR_RESERVED },
+	{ .str = "PPC_BR_TAKEN", .val = PPC_BR_TAKEN },
+	{ .str = "PPC_INSN_FORM_AFORM_1", .val = PPC_INSN_FORM_AFORM_1 },
+	{ .str = "PPC_INSN_FORM_AFORM_4", .val = PPC_INSN_FORM_AFORM_4 },
+	{ .str = "PPC_INSN_FORM_BFORM", .val = PPC_INSN_FORM_BFORM },
+	{ .str = "PPC_INSN_FORM_BFORM_3", .val = PPC_INSN_FORM_BFORM_3 },
+	{ .str = "PPC_INSN_FORM_BFORM_3_AT", .val = PPC_INSN_FORM_BFORM_3_AT },
+	{ .str = "PPC_INSN_FORM_DCBZL_FORM", .val = PPC_INSN_FORM_DCBZL_FORM },
+	{ .str = "PPC_INSN_FORM_DCB_FORM", .val = PPC_INSN_FORM_DCB_FORM },
+	{ .str = "PPC_INSN_FORM_DCB_FORM_HINT",
+	  .val = PPC_INSN_FORM_DCB_FORM_HINT },
+	{ .str = "PPC_INSN_FORM_DFORM_1", .val = PPC_INSN_FORM_DFORM_1 },
+	{ .str = "PPC_INSN_FORM_DFORM_2_R0", .val = PPC_INSN_FORM_DFORM_2_R0 },
+	{ .str = "PPC_INSN_FORM_DFORM_4", .val = PPC_INSN_FORM_DFORM_4 },
+	{ .str = "PPC_INSN_FORM_DFORM_5", .val = PPC_INSN_FORM_DFORM_5 },
+	{ .str = "PPC_INSN_FORM_DFORM_BASE", .val = PPC_INSN_FORM_DFORM_BASE },
+	{ .str = "PPC_INSN_FORM_DQFORM_RTP5_RA17_MEM",
+	  .val = PPC_INSN_FORM_DQFORM_RTP5_RA17_MEM },
+	{ .str = "PPC_INSN_FORM_DQFORM_XTP5_RA17_MEM",
+	  .val = PPC_INSN_FORM_DQFORM_XTP5_RA17_MEM },
+	{ .str = "PPC_INSN_FORM_DQ_RD6_RS5_DQ12",
+	  .val = PPC_INSN_FORM_DQ_RD6_RS5_DQ12 },
+	{ .str = "PPC_INSN_FORM_DSFORM_1", .val = PPC_INSN_FORM_DSFORM_1 },
+	{ .str = "PPC_INSN_FORM_DSS_FORM", .val = PPC_INSN_FORM_DSS_FORM },
+	{ .str = "PPC_INSN_FORM_DXFORM", .val = PPC_INSN_FORM_DXFORM },
+	{ .str = "PPC_INSN_FORM_EFXFORM_1", .val = PPC_INSN_FORM_EFXFORM_1 },
+	{ .str = "PPC_INSN_FORM_EFXFORM_3", .val = PPC_INSN_FORM_EFXFORM_3 },
+	{ .str = "PPC_INSN_FORM_EVXFORM_1", .val = PPC_INSN_FORM_EVXFORM_1 },
+	{ .str = "PPC_INSN_FORM_EVXFORM_3", .val = PPC_INSN_FORM_EVXFORM_3 },
+	{ .str = "PPC_INSN_FORM_EVXFORM_4", .val = PPC_INSN_FORM_EVXFORM_4 },
+	{ .str = "PPC_INSN_FORM_EVXFORM_D", .val = PPC_INSN_FORM_EVXFORM_D },
+	{ .str = "PPC_INSN_FORM_IFORM", .val = PPC_INSN_FORM_IFORM },
+	{ .str = "PPC_INSN_FORM_MDFORM_1", .val = PPC_INSN_FORM_MDFORM_1 },
+	{ .str = "PPC_INSN_FORM_MDSFORM_1", .val = PPC_INSN_FORM_MDSFORM_1 },
+	{ .str = "PPC_INSN_FORM_MFORM_1", .val = PPC_INSN_FORM_MFORM_1 },
+	{ .str = "PPC_INSN_FORM_PSFORM_C", .val = PPC_INSN_FORM_PSFORM_C },
+	{ .str = "PPC_INSN_FORM_PSFORM_QD", .val = PPC_INSN_FORM_PSFORM_QD },
+	{ .str = "PPC_INSN_FORM_PSFORM_QI", .val = PPC_INSN_FORM_PSFORM_QI },
+	{ .str = "PPC_INSN_FORM_PSFORM_X", .val = PPC_INSN_FORM_PSFORM_X },
+	{ .str = "PPC_INSN_FORM_PSFORM_Y", .val = PPC_INSN_FORM_PSFORM_Y },
+	{ .str = "PPC_INSN_FORM_REQUIRES", .val = PPC_INSN_FORM_REQUIRES },
+	{ .str = "PPC_INSN_FORM_SCFORM", .val = PPC_INSN_FORM_SCFORM },
+	{ .str = "PPC_INSN_FORM_VAFORM_1", .val = PPC_INSN_FORM_VAFORM_1 },
+	{ .str = "PPC_INSN_FORM_VAFORM_1A", .val = PPC_INSN_FORM_VAFORM_1A },
+	{ .str = "PPC_INSN_FORM_VAFORM_2", .val = PPC_INSN_FORM_VAFORM_2 },
+	{ .str = "PPC_INSN_FORM_VNFORM_VTAB5_SD3",
+	  .val = PPC_INSN_FORM_VNFORM_VTAB5_SD3 },
+	{ .str = "PPC_INSN_FORM_VXFORM_1", .val = PPC_INSN_FORM_VXFORM_1 },
+	{ .str = "PPC_INSN_FORM_VXFORM_2", .val = PPC_INSN_FORM_VXFORM_2 },
+	{ .str = "PPC_INSN_FORM_VXFORM_3", .val = PPC_INSN_FORM_VXFORM_3 },
+	{ .str = "PPC_INSN_FORM_VXFORM_4", .val = PPC_INSN_FORM_VXFORM_4 },
+	{ .str = "PPC_INSN_FORM_VXFORM_5", .val = PPC_INSN_FORM_VXFORM_5 },
+	{ .str = "PPC_INSN_FORM_VXFORM_BF3_VAB5",
+	  .val = PPC_INSN_FORM_VXFORM_BF3_VAB5 },
+	{ .str = "PPC_INSN_FORM_VXFORM_BX", .val = PPC_INSN_FORM_VXFORM_BX },
+	{ .str = "PPC_INSN_FORM_VXFORM_CR", .val = PPC_INSN_FORM_VXFORM_CR },
+	{ .str = "PPC_INSN_FORM_VXFORM_RD5_MP_VB5",
+	  .val = PPC_INSN_FORM_VXFORM_RD5_MP_VB5 },
+	{ .str = "PPC_INSN_FORM_VXFORM_RD5_N3_VB5",
+	  .val = PPC_INSN_FORM_VXFORM_RD5_N3_VB5 },
+	{ .str = "PPC_INSN_FORM_VXFORM_RD5_XO5_RS5",
+	  .val = PPC_INSN_FORM_VXFORM_RD5_XO5_RS5 },
+	{ .str = "PPC_INSN_FORM_VXFORM_VTB5_RC",
+	  .val = PPC_INSN_FORM_VXFORM_VTB5_RC },
+	{ .str = "PPC_INSN_FORM_VXRFORM_1", .val = PPC_INSN_FORM_VXRFORM_1 },
+	{ .str = "PPC_INSN_FORM_VX_RD5_EO5_RS5_PS1_XO9",
+	  .val = PPC_INSN_FORM_VX_RD5_EO5_RS5_PS1_XO9 },
+	{ .str = "PPC_INSN_FORM_VX_RD5_RSP5_PS1_XO9",
+	  .val = PPC_INSN_FORM_VX_RD5_RSP5_PS1_XO9 },
+	{ .str = "PPC_INSN_FORM_XFLFORM_1", .val = PPC_INSN_FORM_XFLFORM_1 },
+	{ .str = "PPC_INSN_FORM_XFORMMEMOP", .val = PPC_INSN_FORM_XFORMMEMOP },
+	{ .str = "PPC_INSN_FORM_XFORM_16", .val = PPC_INSN_FORM_XFORM_16 },
+	{ .str = "PPC_INSN_FORM_XFORM_17", .val = PPC_INSN_FORM_XFORM_17 },
+	{ .str = "PPC_INSN_FORM_XFORM_18", .val = PPC_INSN_FORM_XFORM_18 },
+	{ .str = "PPC_INSN_FORM_XFORM_20", .val = PPC_INSN_FORM_XFORM_20 },
+	{ .str = "PPC_INSN_FORM_XFORM_24", .val = PPC_INSN_FORM_XFORM_24 },
+	{ .str = "PPC_INSN_FORM_XFORM_24_SYNC",
+	  .val = PPC_INSN_FORM_XFORM_24_SYNC },
+	{ .str = "PPC_INSN_FORM_XFORM_44", .val = PPC_INSN_FORM_XFORM_44 },
+	{ .str = "PPC_INSN_FORM_XFORM_45", .val = PPC_INSN_FORM_XFORM_45 },
+	{ .str = "PPC_INSN_FORM_XFORM_AT3", .val = PPC_INSN_FORM_XFORM_AT3 },
+	{ .str = "PPC_INSN_FORM_XFORM_ATB3", .val = PPC_INSN_FORM_XFORM_ATB3 },
+	{ .str = "PPC_INSN_FORM_XFORM_ATTN", .val = PPC_INSN_FORM_XFORM_ATTN },
+	{ .str = "PPC_INSN_FORM_XFORM_BASE_R3XO",
+	  .val = PPC_INSN_FORM_XFORM_BASE_R3XO },
+	{ .str = "PPC_INSN_FORM_XFORM_BASE_R3XO_SWAPPED",
+	  .val = PPC_INSN_FORM_XFORM_BASE_R3XO_SWAPPED },
+	{ .str = "PPC_INSN_FORM_XFORM_HTM0", .val = PPC_INSN_FORM_XFORM_HTM0 },
+	{ .str = "PPC_INSN_FORM_XFORM_HTM1", .val = PPC_INSN_FORM_XFORM_HTM1 },
+	{ .str = "PPC_INSN_FORM_XFORM_HTM2", .val = PPC_INSN_FORM_XFORM_HTM2 },
+	{ .str = "PPC_INSN_FORM_XFORM_HTM3", .val = PPC_INSN_FORM_XFORM_HTM3 },
+	{ .str = "PPC_INSN_FORM_XFORM_ICBT", .val = PPC_INSN_FORM_XFORM_ICBT },
+	{ .str = "PPC_INSN_FORM_XFORM_MBAR", .val = PPC_INSN_FORM_XFORM_MBAR },
+	{ .str = "PPC_INSN_FORM_XFORM_MTMSR",
+	  .val = PPC_INSN_FORM_XFORM_MTMSR },
+	{ .str = "PPC_INSN_FORM_XFORM_SR", .val = PPC_INSN_FORM_XFORM_SR },
+	{ .str = "PPC_INSN_FORM_XFORM_SRIN", .val = PPC_INSN_FORM_XFORM_SRIN },
+	{ .str = "PPC_INSN_FORM_XFORM_TLBWS",
+	  .val = PPC_INSN_FORM_XFORM_TLBWS },
+	{ .str = "PPC_INSN_FORM_XFORM_XD6_RA5_RB5",
+	  .val = PPC_INSN_FORM_XFORM_XD6_RA5_RB5 },
+	{ .str = "PPC_INSN_FORM_XFORM_XT6_IMM5",
+	  .val = PPC_INSN_FORM_XFORM_XT6_IMM5 },
+	{ .str = "PPC_INSN_FORM_XFORM_XT6_IMM5_VB5",
+	  .val = PPC_INSN_FORM_XFORM_XT6_IMM5_VB5 },
+	{ .str = "PPC_INSN_FORM_XFXFORM_1", .val = PPC_INSN_FORM_XFXFORM_1 },
+	{ .str = "PPC_INSN_FORM_XFXFORM_3", .val = PPC_INSN_FORM_XFXFORM_3 },
+	{ .str = "PPC_INSN_FORM_XFXFORM_3P", .val = PPC_INSN_FORM_XFXFORM_3P },
+	{ .str = "PPC_INSN_FORM_XFXFORM_5", .val = PPC_INSN_FORM_XFXFORM_5 },
+	{ .str = "PPC_INSN_FORM_XFXFORM_5A", .val = PPC_INSN_FORM_XFXFORM_5A },
+	{ .str = "PPC_INSN_FORM_XLFORM_1", .val = PPC_INSN_FORM_XLFORM_1 },
+	{ .str = "PPC_INSN_FORM_XLFORM_2", .val = PPC_INSN_FORM_XLFORM_2 },
+	{ .str = "PPC_INSN_FORM_XLFORM_3", .val = PPC_INSN_FORM_XLFORM_3 },
+	{ .str = "PPC_INSN_FORM_XLFORM_4", .val = PPC_INSN_FORM_XLFORM_4 },
+	{ .str = "PPC_INSN_FORM_XLFORM_S", .val = PPC_INSN_FORM_XLFORM_S },
+	{ .str = "PPC_INSN_FORM_XOFORM_1", .val = PPC_INSN_FORM_XOFORM_1 },
+	{ .str = "PPC_INSN_FORM_XOFORM_RTAB5_L1",
+	  .val = PPC_INSN_FORM_XOFORM_RTAB5_L1 },
+	{ .str = "PPC_INSN_FORM_XSFORM_1", .val = PPC_INSN_FORM_XSFORM_1 },
+	{ .str = "PPC_INSN_FORM_XX1FORM", .val = PPC_INSN_FORM_XX1FORM },
+	{ .str = "PPC_INSN_FORM_XX2FORM", .val = PPC_INSN_FORM_XX2FORM },
+	{ .str = "PPC_INSN_FORM_XX2FORM_1", .val = PPC_INSN_FORM_XX2FORM_1 },
+	{ .str = "PPC_INSN_FORM_XX2FORM_2", .val = PPC_INSN_FORM_XX2FORM_2 },
+	{ .str = "PPC_INSN_FORM_XX2FORM_AT3_XBP5_P2",
+	  .val = PPC_INSN_FORM_XX2FORM_AT3_XBP5_P2 },
+	{ .str = "PPC_INSN_FORM_XX2_BF3_DCMX7_RS6",
+	  .val = PPC_INSN_FORM_XX2_BF3_DCMX7_RS6 },
+	{ .str = "PPC_INSN_FORM_XX2_BF3_XO5_XB6_XO9",
+	  .val = PPC_INSN_FORM_XX2_BF3_XO5_XB6_XO9 },
+	{ .str = "PPC_INSN_FORM_XX2_RD5_XO5_RS6",
+	  .val = PPC_INSN_FORM_XX2_RD5_XO5_RS6 },
+	{ .str = "PPC_INSN_FORM_XX2_RD6_DCMX7_RS6",
+	  .val = PPC_INSN_FORM_XX2_RD6_DCMX7_RS6 },
+	{ .str = "PPC_INSN_FORM_XX2_RD6_UIM5_RS6",
+	  .val = PPC_INSN_FORM_XX2_RD6_UIM5_RS6 },
+	{ .str = "PPC_INSN_FORM_XX2_RD6_XO5_RS6",
+	  .val = PPC_INSN_FORM_XX2_RD6_XO5_RS6 },
+	{ .str = "PPC_INSN_FORM_XX3FORM", .val = PPC_INSN_FORM_XX3FORM },
+	{ .str = "PPC_INSN_FORM_XX3FORM_1", .val = PPC_INSN_FORM_XX3FORM_1 },
+	{ .str = "PPC_INSN_FORM_XX3FORM_2", .val = PPC_INSN_FORM_XX3FORM_2 },
+	{ .str = "PPC_INSN_FORM_XX3FORM_AT3_XAB6",
+	  .val = PPC_INSN_FORM_XX3FORM_AT3_XAB6 },
+	{ .str = "PPC_INSN_FORM_XX3FORM_AT3_XABP5_P1",
+	  .val = PPC_INSN_FORM_XX3FORM_AT3_XABP5_P1 },
+	{ .str = "PPC_INSN_FORM_XX3FORM_RC", .val = PPC_INSN_FORM_XX3FORM_RC },
+	{ .str = "PPC_INSN_FORM_XX4FORM", .val = PPC_INSN_FORM_XX4FORM },
+	{ .str = "PPC_INSN_FORM_X_BF3_DCMX7_RS5",
+	  .val = PPC_INSN_FORM_X_BF3_DCMX7_RS5 },
+	{ .str = "PPC_INSN_FORM_X_BF3_L1_RS5_RS5",
+	  .val = PPC_INSN_FORM_X_BF3_L1_RS5_RS5 },
+	{ .str = "PPC_INSN_FORM_X_BF3_RS5_RS5",
+	  .val = PPC_INSN_FORM_X_BF3_RS5_RS5 },
+	{ .str = "PPC_INSN_FORM_X_RD6_IMM8", .val = PPC_INSN_FORM_X_RD6_IMM8 },
+	{ .str = "PPC_INSN_FORM_Z23FORM_1", .val = PPC_INSN_FORM_Z23FORM_1 },
+	{ .str = "PPC_INSN_FORM_Z23FORM_3", .val = PPC_INSN_FORM_Z23FORM_3 },
+	{ .str = "PPC_INSN_FORM_Z23FORM_8", .val = PPC_INSN_FORM_Z23FORM_8 },
+	{ .str = "PPC_INSN_FORM_Z23FORM_RTAB5_CY2",
+	  .val = PPC_INSN_FORM_Z23FORM_RTAB5_CY2 },
+	{ .str = "PPC_OP_IMM", .val = PPC_OP_IMM },
+	{ .str = "PPC_OP_MEM", .val = PPC_OP_MEM },
+	{ .str = "PPC_OP_REG", .val = PPC_OP_REG },
+	{ .str = "PPC_PRED_BIT_SET", .val = PPC_PRED_BIT_SET },
+	{ .str = "PPC_PRED_BIT_UNSET", .val = PPC_PRED_BIT_UNSET },
+	{ .str = "PPC_PRED_EQ", .val = PPC_PRED_EQ },
+	{ .str = "PPC_PRED_EQ_MINUS", .val = PPC_PRED_EQ_MINUS },
+	{ .str = "PPC_PRED_EQ_PLUS", .val = PPC_PRED_EQ_PLUS },
+	{ .str = "PPC_PRED_EQ_RESERVED", .val = PPC_PRED_EQ_RESERVED },
+	{ .str = "PPC_PRED_GE", .val = PPC_PRED_GE },
+	{ .str = "PPC_PRED_GE_MINUS", .val = PPC_PRED_GE_MINUS },
+	{ .str = "PPC_PRED_GE_PLUS", .val = PPC_PRED_GE_PLUS },
+	{ .str = "PPC_PRED_GE_RESERVED", .val = PPC_PRED_GE_RESERVED },
+	{ .str = "PPC_PRED_GT", .val = PPC_PRED_GT },
+	{ .str = "PPC_PRED_GT_MINUS", .val = PPC_PRED_GT_MINUS },
+	{ .str = "PPC_PRED_GT_PLUS", .val = PPC_PRED_GT_PLUS },
+	{ .str = "PPC_PRED_GT_RESERVED", .val = PPC_PRED_GT_RESERVED },
+	{ .str = "PPC_PRED_LE", .val = PPC_PRED_LE },
+	{ .str = "PPC_PRED_LE_MINUS", .val = PPC_PRED_LE_MINUS },
+	{ .str = "PPC_PRED_LE_PLUS", .val = PPC_PRED_LE_PLUS },
+	{ .str = "PPC_PRED_LE_RESERVED", .val = PPC_PRED_LE_RESERVED },
+	{ .str = "PPC_PRED_LT", .val = PPC_PRED_LT },
+	{ .str = "PPC_PRED_LT_MINUS", .val = PPC_PRED_LT_MINUS },
+	{ .str = "PPC_PRED_LT_PLUS", .val = PPC_PRED_LT_PLUS },
+	{ .str = "PPC_PRED_LT_RESERVED", .val = PPC_PRED_LT_RESERVED },
+	{ .str = "PPC_PRED_NE", .val = PPC_PRED_NE },
+	{ .str = "PPC_PRED_NE_MINUS", .val = PPC_PRED_NE_MINUS },
+	{ .str = "PPC_PRED_NE_PLUS", .val = PPC_PRED_NE_PLUS },
+	{ .str = "PPC_PRED_NE_RESERVED", .val = PPC_PRED_NE_RESERVED },
+	{ .str = "PPC_PRED_NS", .val = PPC_PRED_NS },
+	{ .str = "PPC_PRED_NU", .val = PPC_PRED_NU },
+	{ .str = "PPC_PRED_NU_MINUS", .val = PPC_PRED_NU_MINUS },
+	{ .str = "PPC_PRED_NU_PLUS", .val = PPC_PRED_NU_PLUS },
+	{ .str = "PPC_PRED_NU_RESERVED", .val = PPC_PRED_NU_RESERVED },
+	{ .str = "PPC_PRED_NZ", .val = PPC_PRED_NZ },
+	{ .str = "PPC_PRED_NZ_MINUS", .val = PPC_PRED_NZ_MINUS },
+	{ .str = "PPC_PRED_NZ_PLUS", .val = PPC_PRED_NZ_PLUS },
+	{ .str = "PPC_PRED_NZ_RESERVED", .val = PPC_PRED_NZ_RESERVED },
+	{ .str = "PPC_PRED_SO", .val = PPC_PRED_SO },
+	{ .str = "PPC_PRED_SPE", .val = PPC_PRED_SPE },
+	{ .str = "PPC_PRED_UN", .val = PPC_PRED_UN },
+	{ .str = "PPC_PRED_UN_MINUS", .val = PPC_PRED_UN_MINUS },
+	{ .str = "PPC_PRED_UN_PLUS", .val = PPC_PRED_UN_PLUS },
+	{ .str = "PPC_PRED_UN_RESERVED", .val = PPC_PRED_UN_RESERVED },
+	{ .str = "PPC_PRED_Z", .val = PPC_PRED_Z },
+	{ .str = "PPC_PRED_Z_MINUS", .val = PPC_PRED_Z_MINUS },
+	{ .str = "PPC_PRED_Z_PLUS", .val = PPC_PRED_Z_PLUS },
+	{ .str = "PPC_PRED_Z_RESERVED", .val = PPC_PRED_Z_RESERVED },
+	{ .str = "RISCV_GRP_BRANCH_RELATIVE",
+	  .val = RISCV_GRP_BRANCH_RELATIVE },
+	{ .str = "RISCV_GRP_CALL", .val = RISCV_GRP_CALL },
+	{ .str = "RISCV_GRP_HASSTDEXTA", .val = RISCV_GRP_HASSTDEXTA },
+	{ .str = "RISCV_GRP_HASSTDEXTC", .val = RISCV_GRP_HASSTDEXTC },
+	{ .str = "RISCV_GRP_HASSTDEXTD", .val = RISCV_GRP_HASSTDEXTD },
+	{ .str = "RISCV_GRP_HASSTDEXTF", .val = RISCV_GRP_HASSTDEXTF },
+	{ .str = "RISCV_GRP_HASSTDEXTM", .val = RISCV_GRP_HASSTDEXTM },
+	{ .str = "RISCV_GRP_INT", .val = RISCV_GRP_INT },
+	{ .str = "RISCV_GRP_IRET", .val = RISCV_GRP_IRET },
+	{ .str = "RISCV_GRP_ISRV32", .val = RISCV_GRP_ISRV32 },
+	{ .str = "RISCV_GRP_ISRV64", .val = RISCV_GRP_ISRV64 },
+	{ .str = "RISCV_GRP_JUMP", .val = RISCV_GRP_JUMP },
+	{ .str = "RISCV_GRP_PRIVILEGE", .val = RISCV_GRP_PRIVILEGE },
+	{ .str = "RISCV_GRP_RET", .val = RISCV_GRP_RET },
+	{ .str = "RISCV_OP_IMM", .val = RISCV_OP_IMM },
+	{ .str = "RISCV_OP_MEM", .val = RISCV_OP_MEM },
+	{ .str = "RISCV_OP_REG", .val = RISCV_OP_REG },
+	{ .str = "SH_GRP_BRANCH_RELATIVE", .val = SH_GRP_BRANCH_RELATIVE },
+	{ .str = "SH_GRP_CALL", .val = SH_GRP_CALL },
+	{ .str = "SH_GRP_INT", .val = SH_GRP_INT },
+	{ .str = "SH_GRP_IRET", .val = SH_GRP_IRET },
+	{ .str = "SH_GRP_JUMP", .val = SH_GRP_JUMP },
+	{ .str = "SH_GRP_PRIVILEGE", .val = SH_GRP_PRIVILEGE },
+	{ .str = "SH_GRP_RET", .val = SH_GRP_RET },
+	{ .str = "SH_GRP_SH1", .val = SH_GRP_SH1 },
+	{ .str = "SH_GRP_SH2", .val = SH_GRP_SH2 },
+	{ .str = "SH_GRP_SH2A", .val = SH_GRP_SH2A },
+	{ .str = "SH_GRP_SH2AFPU", .val = SH_GRP_SH2AFPU },
+	{ .str = "SH_GRP_SH2DSP", .val = SH_GRP_SH2DSP },
+	{ .str = "SH_GRP_SH2E", .val = SH_GRP_SH2E },
+	{ .str = "SH_GRP_SH3", .val = SH_GRP_SH3 },
+	{ .str = "SH_GRP_SH3DSP", .val = SH_GRP_SH3DSP },
+	{ .str = "SH_GRP_SH4", .val = SH_GRP_SH4 },
+	{ .str = "SH_GRP_SH4A", .val = SH_GRP_SH4A },
+	{ .str = "SH_OP_IMM", .val = SH_OP_IMM },
+	{ .str = "SH_OP_MEM", .val = SH_OP_MEM },
+	{ .str = "SH_OP_MEM_GBR_DISP", .val = SH_OP_MEM_GBR_DISP },
+	{ .str = "SH_OP_MEM_GBR_R0", .val = SH_OP_MEM_GBR_R0 },
+	{ .str = "SH_OP_MEM_PCR", .val = SH_OP_MEM_PCR },
+	{ .str = "SH_OP_MEM_REG_DISP", .val = SH_OP_MEM_REG_DISP },
+	{ .str = "SH_OP_MEM_REG_IND", .val = SH_OP_MEM_REG_IND },
+	{ .str = "SH_OP_MEM_REG_POST", .val = SH_OP_MEM_REG_POST },
+	{ .str = "SH_OP_MEM_REG_PRE", .val = SH_OP_MEM_REG_PRE },
+	{ .str = "SH_OP_MEM_REG_R0", .val = SH_OP_MEM_REG_R0 },
+	{ .str = "SH_OP_MEM_TBR_DISP", .val = SH_OP_MEM_TBR_DISP },
+	{ .str = "SH_OP_REG", .val = SH_OP_REG },
+	{ .str = "SPARC_CC_FCC_A", .val = SPARC_CC_FCC_A },
+	{ .str = "SPARC_CC_FCC_E", .val = SPARC_CC_FCC_E },
+	{ .str = "SPARC_CC_FCC_G", .val = SPARC_CC_FCC_G },
+	{ .str = "SPARC_CC_FCC_GE", .val = SPARC_CC_FCC_GE },
+	{ .str = "SPARC_CC_FCC_L", .val = SPARC_CC_FCC_L },
+	{ .str = "SPARC_CC_FCC_LE", .val = SPARC_CC_FCC_LE },
+	{ .str = "SPARC_CC_FCC_LG", .val = SPARC_CC_FCC_LG },
+	{ .str = "SPARC_CC_FCC_N", .val = SPARC_CC_FCC_N },
+	{ .str = "SPARC_CC_FCC_NE", .val = SPARC_CC_FCC_NE },
+	{ .str = "SPARC_CC_FCC_O", .val = SPARC_CC_FCC_O },
+	{ .str = "SPARC_CC_FCC_U", .val = SPARC_CC_FCC_U },
+	{ .str = "SPARC_CC_FCC_UE", .val = SPARC_CC_FCC_UE },
+	{ .str = "SPARC_CC_FCC_UG", .val = SPARC_CC_FCC_UG },
+	{ .str = "SPARC_CC_FCC_UGE", .val = SPARC_CC_FCC_UGE },
+	{ .str = "SPARC_CC_FCC_UL", .val = SPARC_CC_FCC_UL },
+	{ .str = "SPARC_CC_FCC_ULE", .val = SPARC_CC_FCC_ULE },
+	{ .str = "SPARC_CC_ICC_A", .val = SPARC_CC_ICC_A },
+	{ .str = "SPARC_CC_ICC_CC", .val = SPARC_CC_ICC_CC },
+	{ .str = "SPARC_CC_ICC_CS", .val = SPARC_CC_ICC_CS },
+	{ .str = "SPARC_CC_ICC_E", .val = SPARC_CC_ICC_E },
+	{ .str = "SPARC_CC_ICC_G", .val = SPARC_CC_ICC_G },
+	{ .str = "SPARC_CC_ICC_GE", .val = SPARC_CC_ICC_GE },
+	{ .str = "SPARC_CC_ICC_GU", .val = SPARC_CC_ICC_GU },
+	{ .str = "SPARC_CC_ICC_L", .val = SPARC_CC_ICC_L },
+	{ .str = "SPARC_CC_ICC_LE", .val = SPARC_CC_ICC_LE },
+	{ .str = "SPARC_CC_ICC_LEU", .val = SPARC_CC_ICC_LEU },
+	{ .str = "SPARC_CC_ICC_N", .val = SPARC_CC_ICC_N },
+	{ .str = "SPARC_CC_ICC_NE", .val = SPARC_CC_ICC_NE },
+	{ .str = "SPARC_CC_ICC_NEG", .val = SPARC_CC_ICC_NEG },
+	{ .str = "SPARC_CC_ICC_POS", .val = SPARC_CC_ICC_POS },
+	{ .str = "SPARC_CC_ICC_VC", .val = SPARC_CC_ICC_VC },
+	{ .str = "SPARC_CC_ICC_VS", .val = SPARC_CC_ICC_VS },
+	{ .str = "SPARC_HINT_A", .val = SPARC_HINT_A },
+	{ .str = "SPARC_HINT_A_PN", .val = SPARC_HINT_A_PN },
+	{ .str = "SPARC_HINT_A_PT", .val = SPARC_HINT_A_PT },
+	{ .str = "SPARC_HINT_PN", .val = SPARC_HINT_PN },
+	{ .str = "SPARC_HINT_PT", .val = SPARC_HINT_PT },
+	{ .str = "SPARC_OP_IMM", .val = SPARC_OP_IMM },
+	{ .str = "SPARC_OP_MEM", .val = SPARC_OP_MEM },
+	{ .str = "SPARC_OP_REG", .val = SPARC_OP_REG },
+	{ .str = "SYSZ_OP_ACREG", .val = SYSZ_OP_ACREG },
+	{ .str = "SYSZ_OP_IMM", .val = SYSZ_OP_IMM },
+	{ .str = "SYSZ_OP_MEM", .val = SYSZ_OP_MEM },
+	{ .str = "SYSZ_OP_REG", .val = SYSZ_OP_REG },
+	{ .str = "TMS320C64X_FUNIT_D", .val = TMS320C64X_FUNIT_D },
+	{ .str = "TMS320C64X_FUNIT_L", .val = TMS320C64X_FUNIT_L },
+	{ .str = "TMS320C64X_FUNIT_M", .val = TMS320C64X_FUNIT_M },
+	{ .str = "TMS320C64X_FUNIT_NO", .val = TMS320C64X_FUNIT_NO },
+	{ .str = "TMS320C64X_FUNIT_S", .val = TMS320C64X_FUNIT_S },
+	{ .str = "TMS320C64X_GRP_FUNIT_D", .val = TMS320C64X_GRP_FUNIT_D },
+	{ .str = "TMS320C64X_GRP_FUNIT_L", .val = TMS320C64X_GRP_FUNIT_L },
+	{ .str = "TMS320C64X_GRP_FUNIT_M", .val = TMS320C64X_GRP_FUNIT_M },
+	{ .str = "TMS320C64X_GRP_FUNIT_NO", .val = TMS320C64X_GRP_FUNIT_NO },
+	{ .str = "TMS320C64X_GRP_FUNIT_S", .val = TMS320C64X_GRP_FUNIT_S },
+	{ .str = "TMS320C64X_GRP_JUMP", .val = TMS320C64X_GRP_JUMP },
+	{ .str = "TMS320C64X_MEM_DIR_BW", .val = TMS320C64X_MEM_DIR_BW },
+	{ .str = "TMS320C64X_MEM_DIR_FW", .val = TMS320C64X_MEM_DIR_FW },
+	{ .str = "TMS320C64X_MEM_DISP_CONSTANT",
+	  .val = TMS320C64X_MEM_DISP_CONSTANT },
+	{ .str = "TMS320C64X_MEM_DISP_REGISTER",
+	  .val = TMS320C64X_MEM_DISP_REGISTER },
+	{ .str = "TMS320C64X_MEM_MOD_NO", .val = TMS320C64X_MEM_MOD_NO },
+	{ .str = "TMS320C64X_MEM_MOD_POST", .val = TMS320C64X_MEM_MOD_POST },
+	{ .str = "TMS320C64X_MEM_MOD_PRE", .val = TMS320C64X_MEM_MOD_PRE },
+	{ .str = "TMS320C64X_OP_IMM", .val = TMS320C64X_OP_IMM },
+	{ .str = "TMS320C64X_OP_MEM", .val = TMS320C64X_OP_MEM },
+	{ .str = "TMS320C64X_OP_REG", .val = TMS320C64X_OP_REG },
+	{ .str = "TMS320C64X_OP_REGPAIR", .val = TMS320C64X_OP_REGPAIR },
+	{ .str = "TRICORE_OP_IMM", .val = TRICORE_OP_IMM },
+	{ .str = "TRICORE_OP_MEM", .val = TRICORE_OP_MEM },
+	{ .str = "TRICORE_OP_REG", .val = TRICORE_OP_REG },
+	{ .str = "WASM_GRP_CONTROL", .val = WASM_GRP_CONTROL },
+	{ .str = "WASM_GRP_MEMORY", .val = WASM_GRP_MEMORY },
+	{ .str = "WASM_GRP_NUMBERIC", .val = WASM_GRP_NUMBERIC },
+	{ .str = "WASM_GRP_PARAMETRIC", .val = WASM_GRP_PARAMETRIC },
+	{ .str = "WASM_GRP_VARIABLE", .val = WASM_GRP_VARIABLE },
+	{ .str = "WASM_OP_BRTABLE", .val = WASM_OP_BRTABLE },
+	{ .str = "WASM_OP_IMM", .val = WASM_OP_IMM },
+	{ .str = "WASM_OP_INT7", .val = WASM_OP_INT7 },
+	{ .str = "WASM_OP_NONE", .val = WASM_OP_NONE },
+	{ .str = "WASM_OP_UINT32", .val = WASM_OP_UINT32 },
+	{ .str = "WASM_OP_UINT64", .val = WASM_OP_UINT64 },
+	{ .str = "WASM_OP_VARUINT32", .val = WASM_OP_VARUINT32 },
+	{ .str = "WASM_OP_VARUINT64", .val = WASM_OP_VARUINT64 },
+	{ .str = "X86_AVX_BCAST_16", .val = X86_AVX_BCAST_16 },
+	{ .str = "X86_AVX_BCAST_2", .val = X86_AVX_BCAST_2 },
+	{ .str = "X86_AVX_BCAST_4", .val = X86_AVX_BCAST_4 },
+	{ .str = "X86_AVX_BCAST_8", .val = X86_AVX_BCAST_8 },
+	{ .str = "X86_AVX_CC_EQ", .val = X86_AVX_CC_EQ },
+	{ .str = "X86_AVX_CC_EQ_OS", .val = X86_AVX_CC_EQ_OS },
+	{ .str = "X86_AVX_CC_EQ_UQ", .val = X86_AVX_CC_EQ_UQ },
+	{ .str = "X86_AVX_CC_EQ_US", .val = X86_AVX_CC_EQ_US },
+	{ .str = "X86_AVX_CC_FALSE", .val = X86_AVX_CC_FALSE },
+	{ .str = "X86_AVX_CC_FALSE_OS", .val = X86_AVX_CC_FALSE_OS },
+	{ .str = "X86_AVX_CC_GE", .val = X86_AVX_CC_GE },
+	{ .str = "X86_AVX_CC_GE_OQ", .val = X86_AVX_CC_GE_OQ },
+	{ .str = "X86_AVX_CC_GT", .val = X86_AVX_CC_GT },
+	{ .str = "X86_AVX_CC_GT_OQ", .val = X86_AVX_CC_GT_OQ },
+	{ .str = "X86_AVX_CC_LE", .val = X86_AVX_CC_LE },
+	{ .str = "X86_AVX_CC_LE_OQ", .val = X86_AVX_CC_LE_OQ },
+	{ .str = "X86_AVX_CC_LT", .val = X86_AVX_CC_LT },
+	{ .str = "X86_AVX_CC_LT_OQ", .val = X86_AVX_CC_LT_OQ },
+	{ .str = "X86_AVX_CC_NEQ", .val = X86_AVX_CC_NEQ },
+	{ .str = "X86_AVX_CC_NEQ_OQ", .val = X86_AVX_CC_NEQ_OQ },
+	{ .str = "X86_AVX_CC_NEQ_OS", .val = X86_AVX_CC_NEQ_OS },
+	{ .str = "X86_AVX_CC_NEQ_US", .val = X86_AVX_CC_NEQ_US },
+	{ .str = "X86_AVX_CC_NGE", .val = X86_AVX_CC_NGE },
+	{ .str = "X86_AVX_CC_NGE_UQ", .val = X86_AVX_CC_NGE_UQ },
+	{ .str = "X86_AVX_CC_NGT", .val = X86_AVX_CC_NGT },
+	{ .str = "X86_AVX_CC_NGT_UQ", .val = X86_AVX_CC_NGT_UQ },
+	{ .str = "X86_AVX_CC_NLE", .val = X86_AVX_CC_NLE },
+	{ .str = "X86_AVX_CC_NLE_UQ", .val = X86_AVX_CC_NLE_UQ },
+	{ .str = "X86_AVX_CC_NLT", .val = X86_AVX_CC_NLT },
+	{ .str = "X86_AVX_CC_NLT_UQ", .val = X86_AVX_CC_NLT_UQ },
+	{ .str = "X86_AVX_CC_ORD", .val = X86_AVX_CC_ORD },
+	{ .str = "X86_AVX_CC_ORD_S", .val = X86_AVX_CC_ORD_S },
+	{ .str = "X86_AVX_CC_TRUE", .val = X86_AVX_CC_TRUE },
+	{ .str = "X86_AVX_CC_TRUE_US", .val = X86_AVX_CC_TRUE_US },
+	{ .str = "X86_AVX_CC_UNORD", .val = X86_AVX_CC_UNORD },
+	{ .str = "X86_AVX_CC_UNORD_S", .val = X86_AVX_CC_UNORD_S },
+	{ .str = "X86_AVX_RM_RD", .val = X86_AVX_RM_RD },
+	{ .str = "X86_AVX_RM_RN", .val = X86_AVX_RM_RN },
+	{ .str = "X86_AVX_RM_RU", .val = X86_AVX_RM_RU },
+	{ .str = "X86_AVX_RM_RZ", .val = X86_AVX_RM_RZ },
+	{ .str = "X86_EFLAGS_MODIFY_AF", .val = X86_EFLAGS_MODIFY_AF },
+	{ .str = "X86_EFLAGS_MODIFY_CF", .val = X86_EFLAGS_MODIFY_CF },
+	{ .str = "X86_EFLAGS_MODIFY_DF", .val = X86_EFLAGS_MODIFY_DF },
+	{ .str = "X86_EFLAGS_MODIFY_IF", .val = X86_EFLAGS_MODIFY_IF },
+	{ .str = "X86_EFLAGS_MODIFY_NT", .val = X86_EFLAGS_MODIFY_NT },
+	{ .str = "X86_EFLAGS_MODIFY_OF", .val = X86_EFLAGS_MODIFY_OF },
+	{ .str = "X86_EFLAGS_MODIFY_PF", .val = X86_EFLAGS_MODIFY_PF },
+	{ .str = "X86_EFLAGS_MODIFY_RF", .val = X86_EFLAGS_MODIFY_RF },
+	{ .str = "X86_EFLAGS_MODIFY_SF", .val = X86_EFLAGS_MODIFY_SF },
+	{ .str = "X86_EFLAGS_MODIFY_TF", .val = X86_EFLAGS_MODIFY_TF },
+	{ .str = "X86_EFLAGS_MODIFY_ZF", .val = X86_EFLAGS_MODIFY_ZF },
+	{ .str = "X86_EFLAGS_PRIOR_AF", .val = X86_EFLAGS_PRIOR_AF },
+	{ .str = "X86_EFLAGS_PRIOR_CF", .val = X86_EFLAGS_PRIOR_CF },
+	{ .str = "X86_EFLAGS_PRIOR_DF", .val = X86_EFLAGS_PRIOR_DF },
+	{ .str = "X86_EFLAGS_PRIOR_IF", .val = X86_EFLAGS_PRIOR_IF },
+	{ .str = "X86_EFLAGS_PRIOR_NT", .val = X86_EFLAGS_PRIOR_NT },
+	{ .str = "X86_EFLAGS_PRIOR_OF", .val = X86_EFLAGS_PRIOR_OF },
+	{ .str = "X86_EFLAGS_PRIOR_PF", .val = X86_EFLAGS_PRIOR_PF },
+	{ .str = "X86_EFLAGS_PRIOR_SF", .val = X86_EFLAGS_PRIOR_SF },
+	{ .str = "X86_EFLAGS_PRIOR_TF", .val = X86_EFLAGS_PRIOR_TF },
+	{ .str = "X86_EFLAGS_PRIOR_ZF", .val = X86_EFLAGS_PRIOR_ZF },
+	{ .str = "X86_EFLAGS_RESET_0F", .val = X86_EFLAGS_RESET_0F },
+	{ .str = "X86_EFLAGS_RESET_AC", .val = X86_EFLAGS_RESET_AC },
+	{ .str = "X86_EFLAGS_RESET_AF", .val = X86_EFLAGS_RESET_AF },
+	{ .str = "X86_EFLAGS_RESET_CF", .val = X86_EFLAGS_RESET_CF },
+	{ .str = "X86_EFLAGS_RESET_DF", .val = X86_EFLAGS_RESET_DF },
+	{ .str = "X86_EFLAGS_RESET_IF", .val = X86_EFLAGS_RESET_IF },
+	{ .str = "X86_EFLAGS_RESET_NT", .val = X86_EFLAGS_RESET_NT },
+	{ .str = "X86_EFLAGS_RESET_OF", .val = X86_EFLAGS_RESET_OF },
+	{ .str = "X86_EFLAGS_RESET_PF", .val = X86_EFLAGS_RESET_PF },
+	{ .str = "X86_EFLAGS_RESET_RF", .val = X86_EFLAGS_RESET_RF },
+	{ .str = "X86_EFLAGS_RESET_SF", .val = X86_EFLAGS_RESET_SF },
+	{ .str = "X86_EFLAGS_RESET_TF", .val = X86_EFLAGS_RESET_TF },
+	{ .str = "X86_EFLAGS_RESET_ZF", .val = X86_EFLAGS_RESET_ZF },
+	{ .str = "X86_EFLAGS_SET_AF", .val = X86_EFLAGS_SET_AF },
+	{ .str = "X86_EFLAGS_SET_CF", .val = X86_EFLAGS_SET_CF },
+	{ .str = "X86_EFLAGS_SET_DF", .val = X86_EFLAGS_SET_DF },
+	{ .str = "X86_EFLAGS_SET_IF", .val = X86_EFLAGS_SET_IF },
+	{ .str = "X86_EFLAGS_SET_OF", .val = X86_EFLAGS_SET_OF },
+	{ .str = "X86_EFLAGS_SET_PF", .val = X86_EFLAGS_SET_PF },
+	{ .str = "X86_EFLAGS_SET_SF", .val = X86_EFLAGS_SET_SF },
+	{ .str = "X86_EFLAGS_SET_ZF", .val = X86_EFLAGS_SET_ZF },
+	{ .str = "X86_EFLAGS_TEST_AF", .val = X86_EFLAGS_TEST_AF },
+	{ .str = "X86_EFLAGS_TEST_CF", .val = X86_EFLAGS_TEST_CF },
+	{ .str = "X86_EFLAGS_TEST_DF", .val = X86_EFLAGS_TEST_DF },
+	{ .str = "X86_EFLAGS_TEST_IF", .val = X86_EFLAGS_TEST_IF },
+	{ .str = "X86_EFLAGS_TEST_NT", .val = X86_EFLAGS_TEST_NT },
+	{ .str = "X86_EFLAGS_TEST_OF", .val = X86_EFLAGS_TEST_OF },
+	{ .str = "X86_EFLAGS_TEST_PF", .val = X86_EFLAGS_TEST_PF },
+	{ .str = "X86_EFLAGS_TEST_RF", .val = X86_EFLAGS_TEST_RF },
+	{ .str = "X86_EFLAGS_TEST_SF", .val = X86_EFLAGS_TEST_SF },
+	{ .str = "X86_EFLAGS_TEST_TF", .val = X86_EFLAGS_TEST_TF },
+	{ .str = "X86_EFLAGS_TEST_ZF", .val = X86_EFLAGS_TEST_ZF },
+	{ .str = "X86_EFLAGS_UNDEFINED_AF", .val = X86_EFLAGS_UNDEFINED_AF },
+	{ .str = "X86_EFLAGS_UNDEFINED_CF", .val = X86_EFLAGS_UNDEFINED_CF },
+	{ .str = "X86_EFLAGS_UNDEFINED_OF", .val = X86_EFLAGS_UNDEFINED_OF },
+	{ .str = "X86_EFLAGS_UNDEFINED_PF", .val = X86_EFLAGS_UNDEFINED_PF },
+	{ .str = "X86_EFLAGS_UNDEFINED_SF", .val = X86_EFLAGS_UNDEFINED_SF },
+	{ .str = "X86_EFLAGS_UNDEFINED_ZF", .val = X86_EFLAGS_UNDEFINED_ZF },
+	{ .str = "X86_FPU_FLAGS_MODIFY_C0", .val = X86_FPU_FLAGS_MODIFY_C0 },
+	{ .str = "X86_FPU_FLAGS_MODIFY_C1", .val = X86_FPU_FLAGS_MODIFY_C1 },
+	{ .str = "X86_FPU_FLAGS_MODIFY_C2", .val = X86_FPU_FLAGS_MODIFY_C2 },
+	{ .str = "X86_FPU_FLAGS_MODIFY_C3", .val = X86_FPU_FLAGS_MODIFY_C3 },
+	{ .str = "X86_FPU_FLAGS_RESET_C0", .val = X86_FPU_FLAGS_RESET_C0 },
+	{ .str = "X86_FPU_FLAGS_RESET_C1", .val = X86_FPU_FLAGS_RESET_C1 },
+	{ .str = "X86_FPU_FLAGS_RESET_C2", .val = X86_FPU_FLAGS_RESET_C2 },
+	{ .str = "X86_FPU_FLAGS_RESET_C3", .val = X86_FPU_FLAGS_RESET_C3 },
+	{ .str = "X86_FPU_FLAGS_SET_C0", .val = X86_FPU_FLAGS_SET_C0 },
+	{ .str = "X86_FPU_FLAGS_SET_C1", .val = X86_FPU_FLAGS_SET_C1 },
+	{ .str = "X86_FPU_FLAGS_SET_C2", .val = X86_FPU_FLAGS_SET_C2 },
+	{ .str = "X86_FPU_FLAGS_SET_C3", .val = X86_FPU_FLAGS_SET_C3 },
+	{ .str = "X86_FPU_FLAGS_TEST_C0", .val = X86_FPU_FLAGS_TEST_C0 },
+	{ .str = "X86_FPU_FLAGS_TEST_C1", .val = X86_FPU_FLAGS_TEST_C1 },
+	{ .str = "X86_FPU_FLAGS_TEST_C2", .val = X86_FPU_FLAGS_TEST_C2 },
+	{ .str = "X86_FPU_FLAGS_TEST_C3", .val = X86_FPU_FLAGS_TEST_C3 },
+	{ .str = "X86_FPU_FLAGS_UNDEFINED_C0",
+	  .val = X86_FPU_FLAGS_UNDEFINED_C0 },
+	{ .str = "X86_FPU_FLAGS_UNDEFINED_C1",
+	  .val = X86_FPU_FLAGS_UNDEFINED_C1 },
+	{ .str = "X86_FPU_FLAGS_UNDEFINED_C2",
+	  .val = X86_FPU_FLAGS_UNDEFINED_C2 },
+	{ .str = "X86_FPU_FLAGS_UNDEFINED_C3",
+	  .val = X86_FPU_FLAGS_UNDEFINED_C3 },
+	{ .str = "X86_OP_IMM", .val = X86_OP_IMM },
+	{ .str = "X86_OP_MEM", .val = X86_OP_MEM },
+	{ .str = "X86_OP_REG", .val = X86_OP_REG },
+	{ .str = "X86_PREFIX_0", .val = 0 },
+	{ .str = "X86_PREFIX_ADDRSIZE", .val = X86_PREFIX_ADDRSIZE },
+	{ .str = "X86_PREFIX_CS", .val = X86_PREFIX_CS },
+	{ .str = "X86_PREFIX_DS", .val = X86_PREFIX_DS },
+	{ .str = "X86_PREFIX_ES", .val = X86_PREFIX_ES },
+	{ .str = "X86_PREFIX_FS", .val = X86_PREFIX_FS },
+	{ .str = "X86_PREFIX_GS", .val = X86_PREFIX_GS },
+	{ .str = "X86_PREFIX_LOCK", .val = X86_PREFIX_LOCK },
+	{ .str = "X86_PREFIX_OPSIZE", .val = X86_PREFIX_OPSIZE },
+	{ .str = "X86_PREFIX_REP", .val = X86_PREFIX_REP },
+	{ .str = "X86_PREFIX_REPE", .val = X86_PREFIX_REPE },
+	{ .str = "X86_PREFIX_REPNE", .val = X86_PREFIX_REPNE },
+	{ .str = "X86_PREFIX_SS", .val = X86_PREFIX_SS },
+	{ .str = "X86_SSE_CC_EQ", .val = X86_SSE_CC_EQ },
+	{ .str = "X86_SSE_CC_LE", .val = X86_SSE_CC_LE },
+	{ .str = "X86_SSE_CC_LT", .val = X86_SSE_CC_LT },
+	{ .str = "X86_SSE_CC_NEQ", .val = X86_SSE_CC_NEQ },
+	{ .str = "X86_SSE_CC_NLE", .val = X86_SSE_CC_NLE },
+	{ .str = "X86_SSE_CC_NLT", .val = X86_SSE_CC_NLT },
+	{ .str = "X86_SSE_CC_ORD", .val = X86_SSE_CC_ORD },
+	{ .str = "X86_SSE_CC_UNORD", .val = X86_SSE_CC_UNORD },
+	{ .str = "X86_XOP_CC_EQ", .val = X86_XOP_CC_EQ },
+	{ .str = "X86_XOP_CC_FALSE", .val = X86_XOP_CC_FALSE },
+	{ .str = "X86_XOP_CC_GE", .val = X86_XOP_CC_GE },
+	{ .str = "X86_XOP_CC_GT", .val = X86_XOP_CC_GT },
+	{ .str = "X86_XOP_CC_LE", .val = X86_XOP_CC_LE },
+	{ .str = "X86_XOP_CC_LT", .val = X86_XOP_CC_LT },
+	{ .str = "X86_XOP_CC_NEQ", .val = X86_XOP_CC_NEQ },
+	{ .str = "X86_XOP_CC_TRUE", .val = X86_XOP_CC_TRUE },
+	{ .str = "XCORE_OP_IMM", .val = XCORE_OP_IMM },
+	{ .str = "XCORE_OP_MEM", .val = XCORE_OP_MEM },
+	{ .str = "XCORE_OP_REG", .val = XCORE_OP_REG },
+	{ .str = "zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz",
+	  .val = 0xffffff }, // For testing
+};
+
+#endif			     // TEST_MAPPING_H
diff --git a/suite/cstest/include/test_run.h b/suite/cstest/include/test_run.h
new file mode 100644
index 000000000..c21700cf2
--- /dev/null
+++ b/suite/cstest/include/test_run.h
@@ -0,0 +1,47 @@
+// Copyright © 2024 Rot127 <unisono@quyllur.org>
+// SPDX-License-Identifier: BSD-3
+
+#ifndef TESTRUN_H
+#define TESTRUN_H
+
+#include "test_case.h"
+#include <stdint.h>
+
+typedef enum {
+	TEST_RUN_SUCCESS = 0, ///< All test cases succeeded.
+	TEST_RUN_FAILURE = 1, ///< At least one test case failed.
+	TEST_RUN_ERROR = 2,   ///< Test run had errors.
+} TestRunResult;
+
+typedef struct {
+	uint32_t valid_test_files; ///< Total number of test files.
+	uint32_t invalid_files;	   ///< Number of invalid files.
+	uint32_t tc_total;	   ///< Total number of test cases.
+	uint32_t successful;	   ///< Number of successful test cases.
+	uint32_t failed;	   ///< Number of failed test cases.
+	uint32_t errors;	   ///< Number errors (parsing errors etc).
+	uint32_t skipped;	   ///< Number skipped test cases.
+} TestRunStats;
+
+typedef struct {
+	uint32_t case_cnt;
+	TestCase *cases;
+} TestRun;
+
+/* CYAML configuration. */
+static const cyaml_config_t cyaml_config = {
+	.log_fn = cyaml_log,		/* Use the default logging function. */
+	.mem_fn = cyaml_mem,		/* Use the default memory allocator. */
+	.log_level = CYAML_LOG_WARNING, /* Logging errors and warnings only. */
+};
+
+typedef struct {
+	size_t arch_bits; ///< Bits of the architecture.
+	TestCase *tcase;  ///< The test case to check.
+	csh handle; ///< The Capstone instance for this test. Setup and teared down by the cmocka handlers.
+} UnitTestState;
+
+TestRunResult cstest_run_tests(char **test_file_paths, uint32_t path_count,
+			       TestRunStats *stats);
+
+#endif // TESTRUN_H
diff --git a/suite/cstest/issues.cs b/suite/cstest/issues.cs
deleted file mode 100644
index 189f397bf..000000000
--- a/suite/cstest/issues.cs
+++ /dev/null
@@ -1,1132 +0,0 @@
-!# issue 2323 eBPF bswap16 instruction
-!# CS_ARCH_BPF, CS_MODE_LITTLE_ENDIAN+CS_MODE_BPF_EXTENDED, CS_OPT_DETAIL
-0xd7,0x53,0x3f,0x0c,0x10,0x00,0x00,0x00 == bswap16 r3
-
-!# issue 2323 eBPF bswap32 instruction
-!# CS_ARCH_BPF, CS_MODE_LITTLE_ENDIAN+CS_MODE_BPF_EXTENDED, CS_OPT_DETAIL
-0xd7,0x53,0x3f,0x0c,0x20,0x00,0x00,0x00 == bswap32 r3
-
-!# issue 2323 eBPF bswap64 instruction
-!# CS_ARCH_BPF, CS_MODE_LITTLE_ENDIAN+CS_MODE_BPF_EXTENDED, CS_OPT_DETAIL
-0xd7,0x53,0x3f,0x0c,0x40,0x00,0x00,0x00 == bswap64 r3
-
-!# issue 2258 vcmpunordss incorrect read/modified register
-!# CS_ARCH_X86, CS_MODE_64, CS_OPT_DETAIL
-0x62,0xd1,0x56,0x08,0xc2,0xca,0x03 == vcmpunordss k1, xmm5, xmm10 ; operands[0].access: WRITE ; operands[1].access: READ ; operands[2].access: READ
-
-!# issue 2062 repz Prefix
-!# CS_ARCH_X86, CS_MODE_64, CS_OPT_DETAIL
-0xf3,0xc3 == repz ret ; Prefix:0xf3 0x00 0x00 0x00
-
-!# issue 2007 RISCV64 instruction groups
-!# CS_ARCH_RISCV, CS_MODE_RISCV64, CS_OPT_DETAIL
-0x63,0x04,0x03,0x00 == beqz t1, 8 ; op_count: 2 ; operands[0].type: REG = t1 ; operands[1].type: IMM = 0x8 ; Groups: branch_relative jump
-
-!# issue 2007 RISCV64 instruction groups
-!# CS_ARCH_RISCV, CS_MODE_RISCV64, CS_OPT_DETAIL
-0x73,0x00,0x00,0x00 == ecall ; Groups: int
-
-!# issue 2007 RISCV64 instruction groups
-!# CS_ARCH_RISCV, CS_MODE_RISCV64, CS_OPT_DETAIL
-0xef,0x00,0x40,0x00 == jal 4 ; op_count: 1 ; operands[0].type: IMM = 0x4 ; Groups: call
-
-!# issue 2007 RISCV32 instruction groups
-!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL
-0x63,0x04,0x03,0x00 == beqz t1, 8 ; op_count: 2 ; operands[0].type: REG = t1 ; operands[1].type: IMM = 0x8 ; Groups: branch_relative jump
-
-!# issue 2007 RISCV32 instruction groups
-!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL
-0x73,0x00,0x00,0x00 == ecall ; Groups: int
-
-!# issue 2007 RISCV32 instruction groups
-!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL
-0xef,0x00,0x40,0x00 == jal 4 ; op_count: 1 ; operands[0].type: IMM = 0x4 ; Groups: call
-
-!# issue 2007 RISCV32 instruction groups
-!# CS_ARCH_RISCV, CS_MODE_RISCV32 CS_MODE_RISCVC, CS_OPT_DETAIL
-0x11,0x20 == c.jal 4 ; op_count: 1 ; operands[0].type: IMM = 0x4 ; Groups: hasStdExtC isrv32 call
-
-!# issue 2007 RISCV32 instruction groups
-!# CS_ARCH_RISCV, CS_MODE_RISCV32 CS_MODE_RISCVC, CS_OPT_DETAIL
-0x91,0xc1 == c.beqz a1, 4 ; op_count: 2 ; operands[0].type: REG = a1 ; operands[1].type: IMM = 0x4 ; Groups: hasStdExtC branch_relative jump
-
-!# issue 1997 notrack jmp
-!# CS_ARCH_X86, CS_MODE_64, None
-0x3e,0xff,0xe0 == notrack jmp rax
-
-!# issue 1997 notrack call
-!# CS_ARCH_X86, CS_MODE_64, None
-0x3e,0xff,0xd0 == notrack call rax
-
-!# issue 1924 SME Index instruction alias printing is not always valid
-!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL
-0x02,0x00,0x9f,0xe0 == ld1w {za0h.s[w12, 2]}, p0/z, [x0] ; op_count: 3 ; operands[0].type: SME_MATRIX ; operands[0].sme.type: 2 ; operands[0].sme.tile: za0.s ; operands[0].sme.slice_reg: w12 ; operands[0].sme.slice_offset: 2 ; operands[0].sme.is_vertical: false ; operands[0].access: WRITE ; operands[0].vas: 0x20 ; operands[1].type: PREDICATE ; operands[1].pred.reg: p0 ; operands[1].access: READ ; operands[2].type: MEM ; operands[2].mem.base: REG = x0 ; operands[2].access: READ ; Registers read: w12 p0 x0 ; Registers modified: za0.s ; Groups: HasSME
-
-!# issue 1912 PPC register name
-!# CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, None
-0x2d,0x03,0x00,0x80 == cmpwi cr2, r3, 0x80
-
-!# issue 1912 PPC no register name
-!# CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, CS_OPT_SYNTAX_NOREGNAME
-0x2d,0x03,0x00,0x80 == cmpwi 2, 3, 0x80
-
-!# issue 1902 PPC psq_st negative displacement
-!# CS_ARCH_PPC, CS_MODE_32 | CS_MODE_BIG_ENDIAN | CS_MODE_PS, CS_OPT_DETAIL
-0xf3,0xec,0x0f,0xf8 == psq_st f31, -8(r12), 0, 0 ; op_count: 4 ; operands[0].type: REG = f31 ; operands[1].type: MEM ; operands[1].mem.base: REG = r12 ; operands[1].mem.disp: 0xfffffff8 ; operands[2].type: IMM = 0x0 ; operands[3].type: IMM = 0x0
-
-!# issue 1873 AArch64 missing VAS specifiers in aliased instructions
-!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL
-0x21,0x04,0x03,0x5e == mov b1, v1.b[1] ; operands[1].vas: 0x8 ; operands[1].vector_index: 1
-
-!# issue 1873 AArch64 missing VAS specifiers in aliased instructions
-!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL
-0xc0,0x1e,0x03,0x4e == mov v0.b[1], w22 ; operands[0].vas: 0x8 ; operands[0].vector_index: 1
-
-!# issue 1873 AArch64 missing VAS specifiers in aliased instructions
-!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL
-0xc0,0x1e,0x06,0x4e == mov v0.h[1], w22 ; operands[0].vas: 0x10 ; operands[0].vector_index: 1
-
-!# issue 1873 AArch64 missing VAS specifiers in aliased instructions
-!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL
-0xc0,0x1e,0x0c,0x4e == mov v0.s[1], w22 ; operands[0].vas: 0x20 ; operands[0].vector_index: 1
-
-!# issue 1873 AArch64 missing VAS specifiers in aliased instructions
-!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL
-0xc0,0x1e,0x18,0x4e == mov v0.d[1], x22 ; operands[0].vas: 0x40 ; operands[0].vector_index: 1
-
-!# issue 1873 AArch64 missing VAS specifiers in aliased instructions
-!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL
-0x20,0x0c,0x03,0x6e == mov v0.b[1], v1.b[1] ; operands[0].vas: 0x8 ; operands[0].vector_index: 1 ; operands[1].vas: 0x8 ; operands[1].vector_index: 1
-
-!# issue 1873 AArch64 missing VAS specifiers in aliased instructions
-!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL
-0x20,0x14,0x06,0x6e == mov v0.h[1], v1.h[1] ; operands[0].vas: 0x10 ; operands[0].vector_index: 1 ; operands[1].vas: 0x10 ; operands[1].vector_index: 1
-
-!# issue 1873 AArch64 missing VAS specifiers in aliased instructions
-!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL
-0x20,0x24,0x0c,0x6e == mov v0.s[1], v1.s[1] ; operands[0].vas: 0x20 ; operands[0].vector_index: 1 ; operands[1].vas: 0x20 ; operands[1].vector_index: 1
-
-!# issue 1873 AArch64 missing VAS specifiers in aliased instructions
-!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL
-0x20,0x44,0x18,0x6e == mov v0.d[1], v1.d[1] ; operands[0].vas: 0x40 ; operands[0].vector_index: 1 ; operands[1].vas: 0x40 ; operands[1].vector_index: 1
-
-!# issue 1873 AArch64 missing VAS specifiers in aliased instructions
-!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL
-0x20,0x3c,0x0c,0x0e == mov w0, v1.s[1] ; operands[1].vas: 0x20 ; operands[1].vector_index: 1
-
-!# issue 1873 AArch64 missing VAS specifiers in aliased instructions
-!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL
-0x20,0x3c,0x0c,0x0e == mov w0, v1.s[1] ; operands[1].vas: 0x20 ; operands[1].vector_index: 1
-
-!# issue 1873 AArch64 missing VAS specifiers in aliased instructions
-!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL
-0x20,0x3c,0x18,0x4e == mov x0, v1.d[1] ; operands[1].vas: 0x40 ; operands[1].vector_index: 1
-
-!# issue 1873 AArch64 missing VAS specifiers in aliased instructions
-!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL
-0x20,0x3c,0x18,0x4e == mov x0, v1.d[1] ; operands[1].vas: 0x40 ; operands[1].vector_index: 1
-
-!# issue 1873 AArch64 missing VAS specifiers in aliased instructions
-!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL
-0x00,0xc0,0x50,0x05 == fmov z0.h, p0/m, #2.00000000 ; operands[0].vas: 0x10
-
-!# issue 1873 AArch64 missing VAS specifiers in aliased instructions
-!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL
-0x00,0xc0,0x79,0x25 == fmov z0.h, #2.00000000 ; operands[0].vas: 0x10
-
-!# issue 1873 AArch64 missing VAS specifiers in aliased instructions
-!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL
-0xa1,0xca,0xf8,0x25 == mov z1.d, #0x55 ; operands[0].vas: 0x40
-
-!# issue 1873 AArch64 missing VAS specifiers in aliased instructions
-!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL
-0x21,0x44,0x81,0x25 == mov p1.b, p1.b ; operands[0].vas: 0x8 ; operands[1].vas: 0x8
-
-!# issue 1873 AArch64 missing VAS specifiers in aliased instructions
-!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL
-0x21,0x40,0x51,0x05 == mov z1.h, p1/m, #1 ; operands[0].vas: 0x10
-
-!# issue 1873 AArch64 missing VAS specifiers in aliased instructions
-!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL
-0x21,0x00,0x51,0x05 == mov z1.h, p1/z, #1 ; operands[0].vas: 0x10
-
-!# issue 1873 AArch64 missing VAS specifiers in aliased instructions
-!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL
-0x20,0xc0,0x38,0x25 == mov z0.b, #1 ; operands[0].vas: 0x8
-
-!# issue 1873 AArch64 missing VAS specifiers in aliased instructions
-!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL
-0x71,0x4a,0x01,0x25 == mov p1.b, p2/m, p3.b ; operands[0].vas: 0x8 ; operands[2].vas: 0x8
-
-!# issue 1873 AArch64 missing VAS specifiers in aliased instructions
-!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL
-0x61,0x48,0x03,0x25 == mov p1.b, p2/z, p3.b ; operands[0].vas: 0x8 ; operands[2].vas: 0x8
-
-!# issue 1873 AArch64 missing VAS specifiers in aliased instructions
-!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL
-0x21,0xa8,0x28,0x05 == mov z1.b, p2/m, w1 ; operands[0].vas: 0x8
-
-!# issue 1873 AArch64 missing VAS specifiers in aliased instructions
-!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL
-0x21,0x38,0x20,0x05 == mov z1.b, w1 ; operands[0].vas: 0x8
-
-!# issue 1873 AArch64 missing VAS specifiers in aliased instructions
-!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL
-0x01,0x88,0x20,0x05 == mov z1.b, p2/m, b0 ; operands[0].vas: 0x8
-
-!# issue 1873 AArch64 missing VAS specifiers in aliased instructions
-!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL
-0x00,0x20,0x21,0x05 == mov z0.b, b0 ; operands[0].vas: 0x8
-
-!# issue 1873 AArch64 missing VAS specifiers in aliased instructions
-!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL
-0x00,0x20,0x23,0x05 == mov z0.b, z0.b[1] ; operands[0].vas: 0x8 ; operands[1].vas: 0x8 ; operands[1].vector_index: 1
-
-!# issue 1873 AArch64 missing VAS specifiers in aliased instructions
-!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL
-0x20,0xc4,0x20,0x05 == mov z0.b, p1/m, z1.b ; operands[0].vas: 0x8 ; operands[2].vas: 0x8
-
-!# issue 1873 AArch64 missing VAS specifiers in aliased instructions
-!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL
-0x20,0x30,0x61,0x04 == mov z0.d, z1.d ; operands[0].vas: 0x40 ; operands[1].vas: 0x40
-
-!# issue 1873 AArch64 missing VAS specifiers in aliased instructions
-!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL
-0x40,0x44,0x42,0x25 == movs p0.b, p1/z, p2.b ; operands[0].vas: 0x8 ; operands[2].vas: 0x8
-
-!# issue 1873 AArch64 missing VAS specifiers in aliased instructions
-!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL
-0x20,0x44,0xc1,0x25 == movs p0.b, p1.b ; operands[0].vas: 0x8 ; operands[1].vas: 0x8
-
-!# issue 1873 AArch64 missing VAS specifiers in aliased instructions
-!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL
-0x40,0x46,0x01,0x25 == not p0.b, p1/z, p2.b ; operands[0].vas: 0x8 ; operands[2].vas: 0x8
-
-!# issue 1873 AArch64 missing VAS specifiers in aliased instructions
-!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL
-0x40,0x46,0x41,0x25 == nots p0.b, p1/z, p2.b ; operands[0].vas: 0x8 ; operands[2].vas: 0x8
-
-!# issue 1856 AArch64 SYS instruction operands: tlbi 1 op
-!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL
-0x1f,0x83,0x08,0xd5 == tlbi vmalle1is ; op_count: 1 ; operands[0].subtype TLBI = 0x418
-
-!# issue 1856 AArch64 SYS instruction operands: tlbi 2 op
-!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL
-0x22,0x87,0x08,0xd5 == tlbi vae1, x2 ; op_count: 2 ; operands[0].subtype TLBI = 0x439
-
-!# issue 1856 AArch64 SYS instruction operands: at
-!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL
-0xc0,0x78,0x0c,0xd5 == at s12e0r, x0 ; op_count: 2 ; operands[0].subtype AT = 0x23c6
-
-!# issue 1856 AArch64 SYS instruction operands: dc
-!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL
-0x22,0x7b,0x0b,0xd5 == dc cvau, x2 ; op_count: 2 ; operands[0].subtype DC = 0x1bd9
-
-!# issue 1856 AArch64 SYS instruction operands: ic
-!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL
-0x20,0x75,0x0b,0xd5 == ic ivau, x0 ; op_count: 2 ; operands[0].subtype IC = 0x1ba9
-
-!# issue 1843 AArch64 missing VAS specifiers in aliased instructions: mov 16b
-!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL
-0x40,0x1e,0xb2,0x4e == mov v0.16b, v18.16b ; operands[0].type: REG = q0 (vreg) ; operands[0].vas: 0x1008 ; operands[1].type: REG = q18 (vreg) ; operands[1].vas: 0x1008
-
-!# issue 1843 AArch64 missing VAS specifiers in aliased instructions: mov 8b
-!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL
-0x40,0x1e,0xb2,0x0e == mov v0.8b, v18.8b ; operands[0].type: REG = d0 (vreg) ; operands[0].vas: 0x808 ; operands[1].type: REG = d18 (vreg) ; operands[1].vas: 0x808
-
-!# issue 1843 AArch64 missing VAS specifiers in aliased instructions: mvn 16b
-!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL
-0x40,0x5a,0x20,0x6e == mvn v0.16b, v18.16b ; operands[0].type: REG = q0 (vreg) ; operands[0].vas: 0x1008 ; operands[1].type: REG = q18 (vreg) ; operands[1].vas: 0x1008
-
-!# issue 1843 AArch64 missing VAS specifiers in aliased instructions: mvn 8b
-!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL
-0x40,0x5a,0x20,0x2e == mvn v0.8b, v18.8b ; operands[0].type: REG = d0 (vreg) ; operands[0].vas: 0x808 ; operands[1].type: REG = d18 (vreg) ; operands[1].vas: 0x808
-
-!# issue 1839 AArch64 Incorrect detailed disassembly of ldr
-!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL
-0x41,0x00,0x40,0xf9 == ldr x1, [x2] ; operands[0].access: WRITE ; operands[1].access: READ
-
-// !# issue 1827 x86-16 lcall 0:0xd
-// !# CS_ARCH_X86, CS_MODE_16, CS_OPT_DETAIL
-// 0x9a,0x0d,0x00,0x00,0x00 == lcall 0:0xd
-
-!# issue 1827 x16 lcall seg:off format
-!# CS_ARCH_X86, CS_MODE_32, CS_OPT_DETAIL
-0xb8,0x01,0x00,0x00,0x00 == mov eax, 1
-0xb9,0x00,0x00,0x00,0x00 == mov ecx, 0
-0x80,0xb8,0x01,0x00,0x00,0x00,0xb9 == cmp byte ptr [eax + 1], 0xb9
-0x00,0x00 == add byte ptr [eax], al
-0x01,0x00 == add dword ptr [eax], eax
-
-!# issue 1827 x16 lcall seg:off format
-!# CS_ARCH_X86, CS_MODE_16, CS_OPT_DETAIL
-0x33,0xc0 == xor ax, ax
-0xba,0x5a,0xff == mov dx, 0xff5a
-
-!# issue 1710 M68K floating point immediates broken on big endian hosts
-!# CS_ARCH_M68K, CS_MODE_BIG_ENDIAN | CS_MODE_M68K_040, None
-0xf2,0x3c,0x44,0x22,0x40,0x49,0x0e,0x56 == fadd.s #3.141500, fp0
-
-!# issue 1708 M68K floating point loads and stores generate the same op_str
-!# CS_ARCH_M68K, CS_MODE_BIG_ENDIAN | CS_MODE_M68K_040, None
-0xf2,0x27,0x74,0x00 == fmove.d fp0, -(a7)
-0xf2,0x1f,0x54,0x80 == fmove.d (a7)+, fp1
-0x4e,0x75 == rts
-
-!# issue 1661 M68K invalid transfer direction in MOVEC instruction
-!# CS_ARCH_M68K, CS_MODE_BIG_ENDIAN | CS_MODE_M68K_040, None
-0x4E,0x7A,0x00,0x02 == movec cacr, d0
-
-// !# issue 1653 AArch64 wrong register access read/write flags on cmp instruction
-// !# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL
-// 0x3F,0x00,0x02,0xEB == cmp x1, x2 ; operands[0].access: READ
-
-!# issue 1643 M68K incorrect read of 32-bit imm for bsr
-!# CS_ARCH_M68K, CS_MODE_BIG_ENDIAN | CS_MODE_M68K_040 , None
-0x61,0xff,0x00,0x00,0x0b,0xea == bsr.l $bec
-
-!# issue 1627 Arm64 LD1 missing immediate operand
-!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL
-0xe0,0x73,0xdf,0x0c == ld1 { v0.8b }, [sp], #8 ; operands[0].vas: 0x808 ; operands[1].type: MEM ; operands[1].mem.base: REG = sp ; operands[1].mem.disp: 0x8 ; operands[1].access: READ
-
-!# issue 1587 ARM thumb pushed registers write
-!# CS_ARCH_ARM, CS_MODE_THUMB, CS_OPT_DETAIL
-0x2d,0xe9,0xf0,0x47 == push.w {r4, r5, r6, r7, r8, r9, r10, lr} ; operands[0].access: READ
-
-!# issue 1504 movhps qword ptr
-!# CS_ARCH_X86, CS_MODE_64, CS_OPT_DETAIL
-0x0f,0x16,0x08 == movhps xmm1, qword ptr [rax] ; Opcode:0x0f 0x16 0x00 0x00
-
-!# issue 1505 opcode 0f
-!# CS_ARCH_X86, CS_MODE_64, CS_OPT_DETAIL
-0x0f,0xa5,0xc2 == shld edx, eax, cl ; Opcode:0x0f 0xa5 0x00 0x00
-
-!# issue 1478 tbegin.
-!# CS_ARCH_PPC, CS_MODE_64 | CS_MODE_BIG_ENDIAN, CS_OPT_DETAIL
-0x7c,0x20,0x05,0x1d == tbegin. 1 ; Update-CR0: True
-
-!# issue 970 PPC bdnzt lt
-!# CS_ARCH_PPC, CS_MODE_64 | CS_MODE_BIG_ENDIAN, CS_OPT_DETAIL
-0x41,0x00,0xff,0xac == bdnzt lt, 0xffffffffffffffac ; operands[0].type: REG = 0
-
-!# issue 970 PPC bdnzt eq
-!# CS_ARCH_PPC, CS_MODE_64 | CS_MODE_BIG_ENDIAN, CS_OPT_DETAIL
-0x41,0x02,0xff,0xac == bdnzt eq, 0xffffffffffffffac ; operands[0].type: REG = 2
-
-!# issue 969 PPC bdnzflr operand 2
-!# CS_ARCH_PPC, CS_MODE_64 | CS_MODE_BIG_ENDIAN, CS_OPT_DETAIL
-0x4c,0x10,0x00,0x20 == bdnzflr 4*cr4+lt ; operands[0].type: REG = 16
-
-0x41,0x82,0x00,0x10 == bt eq, 0x10 ; Groups: jump
-
-!# issue 1481 AARCH64 LDR operand2
-!# CS_ARCH_AARCH64, CS_MODE_LITTLE_ENDIAN, CS_OPT_DETAIL
-0xe9,0x03,0x40,0xf9 == ldr x9, [sp] ; operands[1].mem.base: REG = sp
-
-!# issue 968 PPC absolute branch: bdnzla
-!# CS_ARCH_PPC, CS_MODE_64 | CS_MODE_BIG_ENDIAN, None
-0x1000: 0x42,0x00,0x12,0x37 == bcla 0x10, lt, 0x1234
-
-!# issue 968 PPC absolute branch: bdzla
-!# CS_ARCH_PPC, CS_MODE_64 | CS_MODE_BIG_ENDIAN, None
-0x1000: 0x42,0x40,0x12,0x37 == bcla	0x12, lt, 0x1234
-
-!# issue X86 xrelease xchg
-!# CS_ARCH_X86, CS_MODE_32, None
-0xf3,0x87,0x03 == xrelease xchg dword ptr [ebx], eax
-
-!# issue X86 xacquire xchg
-!# CS_ARCH_X86, CS_MODE_32, None
-0xf2,0x87,0x03 == xacquire xchg dword ptr [ebx], eax
-
-!# issue X86 xrelease
-!# CS_ARCH_X86, CS_MODE_64, None
-0xf3,0xf0,0x31,0x1f == xrelease lock xor dword ptr [rdi], ebx
-
-!# issue 1477 X86 xacquire
-!# CS_ARCH_X86, CS_MODE_64, None
-0xf2,0xf0,0x31,0x1f == xacquire lock xor dword ptr [rdi], ebx
-
-!# issue PPC JUMP group
-!# CS_ARCH_PPC, CS_MODE_64 | CS_MODE_BIG_ENDIAN, CS_OPT_DETAIL
-0x41,0x82,0x00,0x10 == bt eq, 0x10 ; Groups: jump branch_relative
-
-!# issue 1468 PPC bdnz
-!# CS_ARCH_PPC, CS_MODE_64 | CS_MODE_BIG_ENDIAN, None
-0x101086c: 0x42,0x00,0xff,0xf8 == bc 0x10, lt, 0x1010864
-
-!# issue PPC bdnzt
-!# CS_ARCH_PPC, CS_MODE_64 | CS_MODE_BIG_ENDIAN, None
-0x1000: 0x41,0x00,0xff,0xac == bdnzt lt, 0xfac
-
-!# issue 1469 PPC CRx
-!# CS_ARCH_PPC, CS_MODE_64 | CS_MODE_BIG_ENDIAN, CS_OPT_DETAIL
-0x4c,0x02,0x39,0x82 == crxor lt, eq, 4*cr1+un ; operands[0].type: REG = 0 ; operands[1].type: REG = 2 ; operands[2].type: REG = 7
-
-!# issue 1468 B target
-!# CS_ARCH_PPC, CS_MODE_64 | CS_MODE_BIG_ENDIAN, None
-0x1000: 0x4b,0xff,0xf8,0x00 == b 0x800
-
-!# issue 1456 test alt 1
-!# CS_ARCH_X86, CS_MODE_32, None
-0xf6,0x08,0x00 == test byte ptr [eax], 0
-
-!# issue 1456 test alt 2
-!# CS_ARCH_X86, CS_MODE_32, None
-0xf7,0x08,0x00,0x00,0x00,0x00 == test dword ptr [eax], 0
-
-!# issue 1472 lock sub
-!# CS_ARCH_X86, CS_MODE_32, None
-0xF0,0x2B,0x45,0x08 == lock sub eax, dword ptr [ebp + 8]
-
-!# issue 1472 lock or
-!# CS_ARCH_X86, CS_MODE_32, None
-0xF0,0x0B,0x45,0x08 == lock or eax, dword ptr [ebp + 8]
-
-!# issue 1472 lock and
-!# CS_ARCH_X86, CS_MODE_32, None
-0xF0,0x23,0x45,0x08 == lock and eax, dword ptr [ebp + 8]
-
-!# issue 1472 lock add
-!# CS_ARCH_X86, CS_MODE_32, None
-0xF0,0x03,0x45,0x08 == lock add eax, dword ptr [ebp + 8]
-
-!# issue 1456 MOV dr
-!# CS_ARCH_X86, CS_MODE_32, None
-0x0f,0x23,0x00 == mov dr0, eax
-
-!# issue 1456 MOV dr
-!# CS_ARCH_X86, CS_MODE_32, None
-0x0f,0x21,0x00 == mov eax, dr0
-
-!# issue 1456 MOV cr
-!# CS_ARCH_X86, CS_MODE_32, None
-0x0f,0x22,0x00 == mov cr0, eax
-
-!# issue 1472 lock adc
-!# CS_ARCH_X86, CS_MODE_32, None
-0xf0,0x12,0x45,0x08 == lock adc al, byte ptr [ebp + 8]
-
-!# issue 1456 xmmword
-!# CS_ARCH_X86, CS_MODE_32, None
-0x66,0x0f,0x2f,0x00 == comisd xmm0, xmmword ptr [eax]
-
-!# issue 1456 ARM printPKHASRShiftImm
-!# CS_ARCH_ARM, CS_MODE_THUMB, None
-0xca,0xea,0x21,0x06 == pkhtb r6, r10, r1, asr #0x20
-
-!# issue 1456 EIZ
-!# CS_ARCH_X86, CS_MODE_32, None
-0x8d,0xb4,0x26,0x00,0x00,0x00,0x00 == lea esi, [esi]
-
-!# issue 1456 ARM POP
-!# CS_ARCH_ARM, CS_MODE_LITTLE_ENDIAN, None
-0x04,0x10,0x9d,0xe4 == pop {r1}
-
-!# issue 1456
-!# CS_ARCH_ARM, CS_MODE_LITTLE_ENDIAN, CS_OPT_DETAIL
-0x31,0x02,0xa0,0xe1 == lsr r0, r1, r2 ; operands[2].type: REG = r2
-
-!# issue 1456
-!# CS_ARCH_AARCH64, CS_MODE_LITTLE_ENDIAN, CS_OPT_DETAIL
-0x0c,0x00,0x80,0x12 == mov w12, #-1 ; operands[1].type: IMM = 0xffffffffffffffff
-
-0xb8,0x00,0x00,0x00,0x00 == movl $0, %eax
-
-!# issue 1456
-!# CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_ATT
-0xb8,0x00,0x00,0x00,0x00 == movl $0, %eax
-
-0xd1,0x5e,0x48 == rcrl $1, 0x48(%esi)
-
-!# issue 1456
-!# CS_ARCH_X86, CS_MODE_32, None
-0xd1,0x5e,0x48 == rcr dword ptr [esi + 0x48], 1
-
-!# issue 1456
-!# CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_ATT
-0xd1,0x5e,0x48 == rcrl $1, 0x48(%esi)
-
-!# issue 1456
-!# CS_ARCH_X86, CS_MODE_32, None
-0x62,0x00 == bound eax, qword ptr [eax]
-
-!# issue 1454
-!# CS_ARCH_X86, CS_MODE_32, CS_OPT_DETAIL
-0xf0,0x0f,0xb1,0x1e == lock cmpxchg dword ptr [esi], ebx ; Registers read: eax esi ebx
-
-!# issue 1452
-!# CS_ARCH_AARCH64, CS_MODE_LITTLE_ENDIAN, CS_OPT_DETAIL
-0x20,0x3c,0x0c,0x0e == mov w0, v1.s[1] ; operands[1].vas: 0x20
-
-!# issue 1452
-!# CS_ARCH_AARCH64, CS_MODE_LITTLE_ENDIAN, CS_OPT_DETAIL
-0x20,0x3c,0x18,0x4e == mov x0, v1.d[1] ; operands[1].vas: 0x40
-
-!# issue 1452
-!# CS_ARCH_AARCH64, CS_MODE_LITTLE_ENDIAN, CS_OPT_DETAIL
-0x20,0x3c,0x03,0x0e == umov w0, v1.b[1] ; operands[1].vas: 0x8
-
-!# issue 1452
-!# CS_ARCH_AARCH64, CS_MODE_LITTLE_ENDIAN, CS_OPT_DETAIL
-0x20,0x3c,0x06,0x0e == umov w0, v1.h[1] ; operands[1].vas: 0x10
-
-!# issue 1211
-!# CS_ARCH_X86, CS_MODE_64, None
-0xc4,0xe1,0xf8,0x90,0xc0 == kmovq k0, k0
-
-!# issue 1211
-!# CS_ARCH_X86, CS_MODE_64, None
-0xc4,0xe1,0xfb,0x92,0xc3 == kmovq k0, rbx
-
-!# issue 1211
-!# CS_ARCH_X86, CS_MODE_64, None
-0x62,0xf1,0x7d,0x48,0x74,0x83,0x12,0x00,0x00,0x00 == vpcmpeqb k0, zmm0, zmmword ptr [rbx + 0x12]
-
-!# issue 1211
-!# CS_ARCH_X86, CS_MODE_64, None
-0x62,0xf2,0x7d,0x48,0x30,0x43,0x08 == vpmovzxbw zmm0, ymmword ptr [rbx + 0x100]
-
-!# issue x86 BND register (OSS-fuzz #13467)
-!# CS_ARCH_X86, CS_MODE_32, CS_OPT_DETAIL
-0x0f,0x1a,0x1a == bndldx bnd3, [edx] ; operands[0].type: REG = bnd3
-
-!# issue 1335
-!# CS_ARCH_X86, CS_MODE_32, None
-0x0f,0x1f,0xc0 == nop eax
-
-!# issue 1335
-!# CS_ARCH_X86, CS_MODE_64, None
-0x48,0x0f,0x1f,0x00 == nop qword ptr [rax]
-
-!# issue 1259
-!# CS_ARCH_X86, CS_MODE_64, None
-0x0f,0x0d,0x44,0x11,0x40 == prefetch byte ptr [rcx + rdx + 0x40]
-
-!# issue 1259
-!# CS_ARCH_X86, CS_MODE_64, None
-0x41,0x0f,0x0d,0x44,0x12,0x40 == prefetch byte ptr [r10 + rdx + 0x40]
-
-!# issue 1304
-!# CS_ARCH_X86, CS_MODE_64, CS_OPT_DETAIL
-0x66,0x0f,0x7f,0x4c,0x24,0x40 == movdqa xmmword ptr [rsp + 0x40], xmm1 ; operands[0].access: WRITE
-
-!# issue 1304
-!# CS_ARCH_X86, CS_MODE_64, CS_OPT_DETAIL
-0x66,0x0f,0x7e,0x04,0x24 == movd dword ptr [rsp], xmm0 ; operands[0].access: WRITE
-
-!# issue 1304
-!# CS_ARCH_X86, CS_MODE_64, CS_OPT_DETAIL
-0xf3,0x41,0x0f,0x7f,0x4d,0x00 == movdqu xmmword ptr [r13], xmm1 ; operands[0].access: WRITE
-
-!# issue 1346
-!# CS_ARCH_X86, CS_MODE_64, None
-0xf3,0x48,0x0f,0x1e,0xc8 == rdsspq rax
-
-!# issue 1346
-!# CS_ARCH_X86, CS_MODE_64, None
-0xf3,0x0f,0x1e,0xc8 == rdsspd eax
-
-!# issue 1346
-!# CS_ARCH_X86, CS_MODE_64, None
-0xf3,0x48,0x0f,0xae,0xe8 == incsspq rax
-
-!# issue 1346
-!# CS_ARCH_X86, CS_MODE_64, None
-0xf3,0x0f,0xae,0xe8 == incsspd eax
-
-!# issue 1346
-!# CS_ARCH_X86, CS_MODE_64, None
-0xf3,0x0f,0x01,0xea == saveprevssp
-
-!# issue 1346
-!# CS_ARCH_X86, CS_MODE_64, None
-0xf3,0x0f,0x01,0x28 == rstorssp dword ptr [rax]
-
-!# issue 1346
-!# CS_ARCH_X86, CS_MODE_64, None
-0x67,0xf3,0x0f,0x01,0x28 == rstorssp dword ptr [eax]
-
-!# issue 1346
-!# CS_ARCH_X86, CS_MODE_64, None
-0x48,0x0f,0x38,0xf6,0x00 == wrssq qword ptr [rax], rax
-
-!# issue 1346
-!# CS_ARCH_X86, CS_MODE_64, None
-0x67,0x0f,0x38,0xf6,0x00 == wrssd dword ptr [eax], eax
-
-!# issue 1346
-!# CS_ARCH_X86, CS_MODE_64, None
-0xf3,0x0f,0x01,0xe8 == setssbsy
-
-!# issue 1346
-!# CS_ARCH_X86, CS_MODE_64, None
-0xf3,0x0f,0xae,0x30 == clrssbsy dword ptr [rax]
-
-!# issue 1346
-!# CS_ARCH_X86, CS_MODE_64, None
-0x67,0xf3,0x0f,0xae,0x30 == clrssbsy dword ptr [eax]
-
-!# issue 1206
-!# CS_ARCH_X86, CS_MODE_64, None
-0xc4,0xe2,0x7d,0x5a,0x0c,0x0e == vbroadcasti128 ymm1, xmmword ptr [rsi + rcx]
-
-!# issue xchg 16bit
-!# CS_ARCH_X86, CS_MODE_16, None
-0x91 == xchg cx, ax
-
-!# issue ROL 1, ATT syntax
-!# CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_ATT
-0x66,0x48,0xf3,0xd1,0xc0 == rolw $1, %ax
-
-!# issue 1129
-!# CS_ARCH_X86, CS_MODE_64, None
-0xf3,0x0f,0x1e,0xfa == endbr64
-
-!# issue 1129
-!# CS_ARCH_X86, CS_MODE_32, None
-0xf3,0x0f,0x1e,0xfa == endbr64
-
-!# issue 1129
-!# CS_ARCH_X86, CS_MODE_64, None
-0xf3,0x0f,0x1e,0xfb == endbr32
-
-!# issue 1129
-!# CS_ARCH_X86, CS_MODE_32, None
-0xf3,0x0f,0x1e,0xfb == endbr32
-
-!# issue x64 jmp
-!# CS_ARCH_X86, CS_MODE_64, None
-0x1000: 0xeb,0xfe == jmp 0x1000
-
-!# issue x64att jmp
-!# CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_ATT
-0x1000: 0xeb,0xfe == jmp 0x1000
-
-!# issue x32 jmp
-!# CS_ARCH_X86, CS_MODE_32, None
-0x1000: 0xeb,0xfe == jmp 0x1000
-
-!# issue x32att jmp
-!# CS_ARCH_X86, CS_MODE_32, CS_OPT_SYNTAX_ATT
-0x1000: 0xeb,0xfe == jmp 0x1000
-
-!# issue 1389
-!# CS_ARCH_X86, CS_MODE_64, CS_OPT_DETAIL
-0x66,0x0f,0x73,0xf9,0x01 == pslldq xmm1, 1 ; operands[1].size: 1
-
-!# issue 1389
-!# CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_ATT | CS_OPT_DETAIL
-0x66,0x0f,0x73,0xf9,0x01 == pslldq $1, %xmm1 ; operands[0].size: 1
-
-!# issue x64 unsigned
-!# CS_ARCH_X86, CS_MODE_64, CS_OPT_UNSIGNED
-0x66,0x83,0xc0,0x80 == add ax, 0xff80
-
-!# issue x64att unsigned
-!# CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_ATT | CS_OPT_UNSIGNED
-0x66,0x83,0xc0,0x80 == addw $0xff80, %ax
-
-!# issue 1323
-!# CS_ARCH_ARM, CS_MODE_THUMB, CS_OPT_DETAIL
-0x0: 0x70,0x47,0x00 == bx lr ; op_count: 1 ; operands[0].type: REG = r14 ; operands[0].access: READ ; Registers read: r14 ; Groups: jump IsThumb
-
-!# issue 1317
-!# CS_ARCH_ARM, CS_MODE_THUMB, CS_OPT_DETAIL
-0x0: 0xd0,0xe8,0x11,0xf0 == tbh [r0, r1, lsl #1] ; op_count: 1 ; operands[0].type: MEM ; operands[0].mem.base: REG = r0 ; operands[0].mem.index: REG = r1 ; operands[0].mem.lshift: 0x1 ; operands[0].access: READ ; Shift: 2 = 1 ; Registers read: r0 r1 ; Groups: jump IsThumb2
-
-!# issue 1308
-!# CS_ARCH_X86, CS_MODE_64, CS_OPT_DETAIL
-0x0: 0x83,0x3d,0xa1,0x75,0x21,0x00,0x04 == cmp dword ptr [rip + 0x2175a1], 4 ; Prefix:0x00 0x00 0x00 0x00  ; Opcode:0x83 0x00 0x00 0x00  ; rex: 0x0 ; addr_size: 8 ; modrm: 0x3d ; disp: 0x2175a1 ; sib: 0x0 ; imm_count: 1 ; imms[1]: 0x4 ; op_count: 2 ; operands[0].type: MEM ; operands[0].mem.base: REG = rip ; operands[0].mem.disp: 0x2175a1 ; operands[0].size: 4 ; operands[0].access: READ ; operands[1].type: IMM = 0x4 ; operands[1].size: 4 ; Registers read: rip ; Registers modified: rflags ; EFLAGS: MOD_AF MOD_CF MOD_SF MOD_ZF MOD_PF MOD_OF
-
-!# issue 1262
-!# CS_ARCH_X86, CS_MODE_64, CS_OPT_DETAIL
-0x0: 0x0f,0x95,0x44,0x24,0x5e == setne byte ptr [rsp + 0x5e] ; Prefix:0x00 0x00 0x00 0x00  ; Opcode:0x0f 0x95 0x00 0x00  ; rex: 0x0 ; addr_size: 8 ; modrm: 0x44 ; disp: 0x5e ; sib: 0x24 ; sib_base: rsp ; sib_scale: 1 ; op_count: 1 ; operands[0].type: MEM ; operands[0].mem.base: REG = rsp ; operands[0].mem.disp: 0x5e ; operands[0].size: 1 ; operands[0].access: WRITE ; Registers read: rflags rsp ; EFLAGS: TEST_ZF
-
-!# issue 1262
-!# CS_ARCH_X86, CS_MODE_64, CS_OPT_DETAIL
-0x0: 0x0f,0x94,0x44,0x24,0x1f == sete byte ptr [rsp + 0x1f] ; Prefix:0x00 0x00 0x00 0x00  ; Opcode:0x0f 0x94 0x00 0x00  ; rex: 0x0 ; addr_size: 8 ; modrm: 0x44 ; disp: 0x1f ; sib: 0x24 ; sib_base: rsp ; sib_scale: 1 ; op_count: 1 ; operands[0].type: MEM ; operands[0].mem.base: REG = rsp ; operands[0].mem.disp: 0x1f ; operands[0].size: 1 ; operands[0].access: WRITE ; Registers read: rflags rsp ; EFLAGS: TEST_ZF
-
-!# issue 1263
-!# CS_ARCH_X86, CS_MODE_64, None
-0x0: 0x67,0x48,0x89,0x18 == mov qword ptr [eax], rbx
-
-!# issue 1263
-!# CS_ARCH_X86, CS_MODE_64, None
-0x0: 0x67,0x48,0x8b,0x03 == mov rax, qword ptr [ebx]
-
-!# issue 1255
-!# CS_ARCH_X86, CS_MODE_64, CS_OPT_DETAIL
-0x0: 0xdb,0x7c,0x24,0x40 == fstp xword ptr [rsp + 0x40] ; Prefix:0x00 0x00 0x00 0x00  ; Opcode:0xdb 0x00 0x00 0x00  ; rex: 0x0 ; addr_size: 8 ; modrm: 0x7c ; disp: 0x40 ; sib: 0x24 ; sib_base: rsp ; sib_scale: 1 ; op_count: 1 ; operands[0].type: MEM ; operands[0].mem.base: REG = rsp ; operands[0].mem.disp: 0x40 ; operands[0].size: 10 ; operands[0].access: WRITE ; Registers read: rsp ; Registers modified: fpsw ; FPU_FLAGS: MOD_C1 UNDEF_C0 UNDEF_C2 UNDEF_C3 ; Groups: fpu 
-
-!# issue 1255
-!# CS_ARCH_X86, CS_MODE_64, CS_OPT_DETAIL
-0x0: 0xdd,0xd9 == fstp st(1) ; Prefix:0x00 0x00 0x00 0x00  ; Opcode:0xdd 0x00 0x00 0x00  ; rex: 0x0 ; addr_size: 8 ; modrm: 0xd9 ; disp: 0x0 ; sib: 0x0 ; op_count: 1 ; operands[0].type: REG = st(1) ; operands[0].size: 10 ; operands[0].access: WRITE ; Registers modified: fpsw st(1) ; EFLAGS: MOD_CF PRIOR_SF PRIOR_AF PRIOR_PF
-
-!# issue 1255
-!# CS_ARCH_X86, CS_MODE_64, CS_OPT_DETAIL
-0x0: 0xdf,0x7c,0x24,0x68 == fistp qword ptr [rsp + 0x68] ; Prefix:0x00 0x00 0x00 0x00  ; Opcode:0xdf 0x00 0x00 0x00  ; rex: 0x0 ; addr_size: 8 ; modrm: 0x7c ; disp: 0x68 ; sib: 0x24 ; sib_base: rsp ; sib_scale: 1 ; op_count: 1 ; operands[0].type: MEM ; operands[0].mem.base: REG = rsp ; operands[0].mem.disp: 0x68 ; operands[0].size: 8 ; operands[0].access: WRITE ; Registers read: rsp ; Registers modified: fpsw ; FPU_FLAGS: RESET_C1 UNDEF_C0 UNDEF_C2 UNDEF_C3 ; Groups: fpu 
-
-!# issue 1221
-!# CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN, None
-0x0: 0x55,0x48,0x89,0xe5 == call 0x55222794
-
-!# issue 1144
-!# CS_ARCH_AARCH64, CS_MODE_LITTLE_ENDIAN, None
-0x0: 0x00,0x00,0x02,0xb6 == tbz x0, #0x20, 0x4000
-
-!# issue 1144
-!# CS_ARCH_AARCH64, CS_MODE_LITTLE_ENDIAN, None
-0x0: 0x00,0x00,0x04,0xb6 == tbz x0, #0x20, 0xffffffffffff8000
-
-!# issue 1144
-!# CS_ARCH_AARCH64, CS_MODE_LITTLE_ENDIAN, None
-0x0: 0x00,0x00,0x02,0xb7 == tbnz x0, #0x20, 0x4000
-
-!# issue 1144
-!# CS_ARCH_AARCH64, CS_MODE_LITTLE_ENDIAN, None
-0x0: 0x00,0x00,0x04,0xb7 == tbnz x0, #0x20, 0xffffffffffff8000
-
-!# issue 826
-!# CS_ARCH_ARM, CS_MODE_ARM, CS_OPT_DETAIL
-0x0: 0x0b,0x00,0x00,0x0a == beq 0x34 ; op_count: 1 ; operands[0].type: IMM = 0x34 ; Code condition: 0 ; Registers read: cpsr ; Groups: jump branch_relative IsARM
-
-!# issue 1047
-!# CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_ATT
-0x0: 0x48,0x83,0xe4,0xf0 == andq $0xfffffffffffffff0, %rsp
-
-!# issue 959
-!# CS_ARCH_X86, CS_MODE_32, None
-0x0: 0xa0,0x28,0x57,0x88,0x7c == mov al, byte ptr [0x7c885728]
-
-!# issue 950
-!# CS_ARCH_X86, CS_MODE_32, CS_OPT_DETAIL
-0x0: 0x66,0xa3,0x94,0x90,0x04,0x08 == mov word ptr [0x8049094], ax ; Prefix:0x00 0x00 0x66 0x00  ; Opcode:0xa3 0x00 0x00 0x00  ; rex: 0x0 ; addr_size: 4 ; modrm: 0x0 ; disp: 0x8049094 ; sib: 0x0 ; op_count: 2 ; operands[0].type: MEM ; operands[0].mem.disp: 0x8049094 ; operands[0].size: 2 ; operands[0].access: WRITE ; operands[1].type: REG = ax ; operands[1].size: 2 ; operands[1].access: READ ; Registers read: ax
-
-!# issue 938
-!# CS_ARCH_MIPS, CS_MODE_MIPS64+CS_MODE_LITTLE_ENDIAN, None
-0x0: 0x70,0x00,0xb2,0xff == sd $s2, 0x70($sp)
-
-!# issue 915
-!# CS_ARCH_X86, CS_MODE_64, None
-0x0: 0xf0,0x0f,0x1f,0x00 == lock nop dword ptr [rax]
-
-// !# issue 913
-// !# CS_ARCH_ARM, CS_MODE_ARM, CS_OPT_DETAIL
-0x0: 0x04,0x10,0x9d,0xe4 == pop {r1} ; op_count: 1 ; operands[0].type: REG = r1 ; operands[0].access: WRITE ; Write-back: True ; Registers read: sp ; Registers modified: sp r1 ; Groups: arm 
-
-!# issue 884
-!# CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_ATT
-0x0: 0x64,0x48,0x03,0x04,0x25,0x00,0x00,0x00,0x00 == addq %fs:0, %rax
-
-!# issue 872
-!# CS_ARCH_X86, CS_MODE_32, None
-0x0: 0xf2,0xeb,0x3e == bnd jmp 0x41
-
-!# issue 861
-!# CS_ARCH_ARM, CS_MODE_ARM, CS_OPT_DETAIL
-0x0: 0x01,0x81,0xa0,0xfc == stc2 p1, c8, [r0], #4 ; op_count: 3 ; operands[0].type: P-IMM = 1 ; operands[0].access: READ ; operands[1].type: C-IMM = 8 ; operands[1].access: READ ; operands[2].type: MEM ; operands[2].mem.base: REG = r0 ; operands[2].mem.disp: 0x4 ; operands[2].access: WRITE ; Registers read: r0 ; Groups: IsARM PreV8
-
-!# issue 852
-!# CS_ARCH_X86, CS_MODE_32, CS_OPT_DETAIL
-0x0: 0x64,0xa3,0x00,0x00,0x00,0x00 == mov dword ptr fs:[0], eax ; Prefix:0x00 0x64 0x00 0x00  ; Opcode:0xa3 0x00 0x00 0x00  ; rex: 0x0 ; addr_size: 4 ; modrm: 0x0 ; disp: 0x0 ; sib: 0x0 ; op_count: 2 ; operands[0].type: MEM ; operands[0].mem.segment: REG = fs ; operands[0].size: 4 ; operands[0].access: WRITE ; operands[1].type: REG = eax ; operands[1].size: 4 ; operands[1].access: READ ; Registers read: fs eax
-
-!# issue 825
-!# CS_ARCH_ARM, CS_MODE_ARM, CS_OPT_DETAIL
-0x0: 0x0e,0xf0,0xa0,0xe1 == mov pc, lr ; op_count: 2 ; operands[0].type: REG = r15 ; operands[0].access: WRITE ; operands[1].type: REG = r14 ; operands[1].access: READ ; Registers read: r14 ; Registers modified: r15 ; Groups: jump return IsARM
-
-!# issue 813
-!# CS_ARCH_ARM, CS_MODE_THUMB | CS_MODE_BIG_ENDIAN, None
-0x0: 0xF6,0xC0,0x04,0x01 == movt r4, #0x801
-
-!# issue 809
-!# CS_ARCH_X86, CS_MODE_64, CS_OPT_DETAIL
-0x0: 0x0f,0x29,0x8d,0xf0,0xfd,0xff,0xff == movaps xmmword ptr [rbp - 0x210], xmm1 ; Prefix:0x00 0x00 0x00 0x00  ; Opcode:0x0f 0x29 0x00 0x00  ; rex: 0x0 ; addr_size: 8 ; modrm: 0x8d ; disp: 0xfffffffffffffdf0 ; sib: 0x0 ; op_count: 2 ; operands[0].type: MEM ; operands[0].mem.base: REG = rbp ; operands[0].mem.disp: 0xfffffffffffffdf0 ; operands[0].size: 16 ; operands[0].access: WRITE ; operands[1].type: REG = xmm1 ; operands[1].size: 16 ; operands[1].access: READ ; Registers read: rbp xmm1 ; Groups: sse1 
-
-!# issue 807
-!# CS_ARCH_X86, CS_MODE_64, None
-0x0: 0x4c,0x0f,0x00,0x80,0x16,0x76,0x8a,0xfe == sldt word ptr [rax - 0x17589ea]
-
-!# issue 806
-!# CS_ARCH_X86, CS_MODE_64, None
-0x0: 0x0f,0x35 == sysexit 
-
-!# issue 805
-!# CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_ATT
-0x0: 0x48,0x4c,0x0f,0xb5,0x80,0x16,0x76,0x8a,0xfe == lgs -0x17589ea(%rax), %r8
-
-!# issue 804
-!# CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_ATT
-0x0: 0x66,0x48,0xf3,0xd1,0xc0 == rolw $1, %ax
-
-!# issue 789
-!# CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_ATT
-0x0: 0x8e,0x1e == movw (%rsi), %ds
-
-!# issue 767
-!# CS_ARCH_ARM, CS_MODE_THUMB, CS_OPT_DETAIL
-0x0: 0xb1,0xe8,0xfc,0x07 == ldm.w r1!, {r2, r3, r4, r5, r6, r7, r8, r9, r10} ; ldm.w r1!, {r2, r3, r4, r5, r6, r7, r8, r9, r10} ; op_count: 10 ; operands[0].type: REG = r1 ; operands[0].access: READ | WRITE ; operands[1].type: REG = r2 ; operands[1].access: WRITE ; operands[2].type: REG = r3 ; operands[2].access: WRITE ; operands[3].type: REG = r4 ; operands[3].access: WRITE ; operands[4].type: REG = r5 ; operands[4].access: WRITE ; operands[5].type: REG = r6 ; operands[5].access: WRITE ; operands[6].type: REG = r7 ; operands[6].access: WRITE ; operands[7].type: REG = r8 ; operands[7].access: WRITE ; operands[8].type: REG = r9 ; operands[8].access: WRITE ; operands[9].type: REG = r10 ; operands[9].access: WRITE ; Write-back: True ; Registers read: r1 ; Registers modified: r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 ; Groups: IsThumb2
-
-!# issue 760
-!# CS_ARCH_ARM, CS_MODE_ARM, CS_OPT_DETAIL
-0x0: 0x02,0x80,0xbd,0xe8 == pop {r1, pc} ; op_count: 2 ; operands[0].type: REG = r1 ; operands[0].access: WRITE ; operands[1].type: REG = r15 ; operands[1].access: WRITE ; Write-back: True ; Registers read: r13 ; Registers modified: r13 r1 r15 ; Groups: IsARM return jump
-
-!# issue 750
-!# CS_ARCH_ARM, CS_MODE_ARM, CS_OPT_DETAIL
-0x0: 0x0e,0x00,0x20,0xe9 == stmdb r0!, {r1, r2, r3} ; op_count: 4 ; operands[0].type: REG = r0 ; operands[0].access: READ | WRITE ; operands[1].type: REG = r1 ; operands[1].access: READ ; operands[2].type: REG = r2 ; operands[2].access: READ ; operands[3].type: REG = r3 ; operands[3].access: READ ; Write-back: True ; Registers read: r0 r1 r2 r3 ; Registers modified: r0 ; Groups: IsARM
-
-!# issue 747
-!# CS_ARCH_ARM, CS_MODE_ARM, CS_OPT_DETAIL
-0x0: 0x0e,0x00,0xb0,0xe8 == ldm r0!, {r1, r2, r3} ; op_count: 4 ; operands[0].type: REG = r0 ; operands[0].access: READ | WRITE ; operands[1].type: REG = r1 ; operands[1].access: WRITE ; operands[2].type: REG = r2 ; operands[2].access: WRITE ; operands[3].type: REG = r3 ; operands[3].access: WRITE ; Write-back: True ; Registers read: r0 ; Registers modified: r0 r1 r2 r3 ; Groups: IsARM
-
-!# issue 747
-!# CS_ARCH_ARM, CS_MODE_THUMB, CS_OPT_DETAIL
-0x0: 0x0e,0xc8 == ldm r0!, {r1, r2, r3} ; op_count: 4 ; operands[0].type: REG = r0 ; operands[0].access: READ | WRITE ; operands[1].type: REG = r1 ; operands[1].access: WRITE ; operands[2].type: REG = r2 ; operands[2].access: WRITE ; operands[3].type: REG = r3 ; operands[3].access: WRITE ; Write-back: True ; Registers read: r0 ; Registers modified: r0 r1 r2 r3 ; Groups: IsThumb
-
-!# issue 746
-!# CS_ARCH_ARM, CS_MODE_ARM, CS_OPT_DETAIL
-0x0: 0x89,0x00,0x2d,0xe9 == push {r0, r3, r7} ; op_count: 3 ; operands[0].type: REG = r0 ; operands[0].access: READ ; operands[1].type: REG = r3 ; operands[1].access: READ ; operands[2].type: REG = r7 ; operands[2].access: READ ; Write-back: True ; Registers read: r13 r0 r3 r7 ; Registers modified: r13 ; Groups: IsARM
-
-!# issue 744
-!# CS_ARCH_ARM, CS_MODE_ARM, CS_OPT_DETAIL
-0x0: 0x02,0x80,0xbd,0xe8 == pop {r1, pc} ; op_count: 2 ; operands[0].type: REG = r1 ; operands[0].access: WRITE ; operands[1].type: REG = r15 ; operands[1].access: WRITE ; Write-back: True ; Registers read: r13 ; Registers modified: r13 r1 r15 ; Groups: IsARM return jump
-
-!# issue 741
-!# CS_ARCH_X86, CS_MODE_32, None
-0x0: 0x83,0xff,0xf7 == cmp edi, -9
-
-!# issue 717
-!# CS_ARCH_X86, CS_MODE_64, CS_OPT_SYNTAX_ATT
-0x0: 0x48,0x8b,0x04,0x25,0x00,0x00,0x00,0x00 == movq 0, %rax
-
-!# issue 711
-!# CS_ARCH_X86, CS_MODE_32, CS_OPT_DETAIL
-0x0: 0xa3,0x44,0xb0,0x00,0x10 == mov dword ptr [0x1000b044], eax ; Prefix:0x00 0x00 0x00 0x00  ; Opcode:0xa3 0x00 0x00 0x00  ; rex: 0x0 ; addr_size: 4 ; modrm: 0x0 ; disp: 0x1000b044 ; sib: 0x0 ; op_count: 2 ; operands[0].type: MEM ; operands[0].mem.disp: 0x1000b044 ; operands[0].size: 4 ; operands[0].access: WRITE ; operands[1].type: REG = eax ; operands[1].size: 4 ; operands[1].access: READ ; Registers read: eax
-
-!# issue 613
-!# CS_ARCH_X86, CS_MODE_64, None
-0x0: 0xd9,0x74,0x24,0xd8 == fnstenv [rsp - 0x28]
-
-!# issue 554
-!# CS_ARCH_X86, CS_MODE_32, None
-0x0: 0xe7,0x84 == out 0x84, eax
-
-!# issue 554
-!# CS_ARCH_X86, CS_MODE_32, None
-0x0: 0xe5,0x8c == in eax, 0x8c
-
-!# issue 545
-!# CS_ARCH_X86, CS_MODE_32, CS_OPT_DETAIL
-0x0: 0x95 == xchg ebp, eax ; Prefix:0x00 0x00 0x00 0x00  ; Opcode:0x95 0x00 0x00 0x00  ; rex: 0x0 ; addr_size: 4 ; modrm: 0x0 ; disp: 0x0 ; sib: 0x0 ; op_count: 2 ; operands[0].type: REG = ebp ; operands[0].size: 4 ; operands[0].access: READ | WRITE ; operands[1].type: REG = eax ; operands[1].size: 4 ; operands[1].access: READ | WRITE ; Registers read: ebp eax ; Registers modified: ebp eax ; Groups: not64bitmode 
-
-!# issue 544
-!# CS_ARCH_X86, CS_MODE_32, None
-0x0: 0xdf,0x30 == fbstp tbyte ptr [eax]
-
-!# issue 544
-!# CS_ARCH_X86, CS_MODE_32, None
-0x0: 0xdf,0x20 == fbld tbyte ptr [eax]
-
-!# issue 541
-!# CS_ARCH_X86, CS_MODE_64, None
-0x0: 0x48,0xb8,0x00,0x00,0x00,0x00,0x80,0xf8,0xff,0xff == movabs rax, 0xfffff88000000000
-
-!# issue 499
-!# CS_ARCH_X86, CS_MODE_64, None
-0x0: 0x48,0xb8,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80 == movabs rax, 0x8000000000000000
-
-!# issue 492
-!# CS_ARCH_X86, CS_MODE_32, None
-0x0: 0xff,0x18 == call ptr [eax]
-
-!# issue 492
-!# CS_ARCH_X86, CS_MODE_32, None
-0x0: 0xff,0x28 == jmp ptr [eax]
-
-!# issue 492
-!# CS_ARCH_X86, CS_MODE_32, None
-0x0: 0x0f,0xae,0x04,0x24 == fxsave [esp]
-
-!# issue 492
-!# CS_ARCH_X86, CS_MODE_32, None
-0x0: 0x0f,0xae,0x0c,0x24 == fxrstor [esp]
-
-!# issue 470
-!# CS_ARCH_X86, CS_MODE_32, None
-0x0: 0x0f,0x01,0x05,0xa0,0x90,0x04,0x08 == sgdt [0x80490a0]
-
-!# issue 470
-!# CS_ARCH_X86, CS_MODE_32, None
-0x0: 0x0f,0x01,0x0d,0xa7,0x90,0x04,0x08 == sidt [0x80490a7]
-
-!# issue 470
-!# CS_ARCH_X86, CS_MODE_32, None
-0x0: 0x0f,0x01,0x15,0xa0,0x90,0x04,0x08 == lgdt [0x80490a0]
-
-!# issue 470
-!# CS_ARCH_X86, CS_MODE_32, None
-0x0: 0x0f,0x01,0x1d,0xa7,0x90,0x04,0x08 == lidt [0x80490a7]
-
-!# issue 459
-!# CS_ARCH_ARM, CS_MODE_ARM, CS_OPT_DETAIL
-0x0: 0xd3,0x20,0x11,0xe1 == ldrsb r2, [r1, -r3] ; op_count: 2 ; operands[0].type: REG = r2 ; operands[0].access: WRITE ; operands[1].type: MEM ; operands[1].mem.base: REG = r1 ; operands[1].mem.index: REG = r3 ; operands[1].mem.scale: 0 ; operands[1].access: READ ; Subtracted: True ; Registers read: r1 r3 ; Registers modified: r2 ; Groups: IsARM
-
-!# issue 456
-!# CS_ARCH_X86, CS_MODE_16, None
-0x0: 0xe8,0x35,0x64 == call 0x6438
-
-!# issue 456
-!# CS_ARCH_X86, CS_MODE_16, None
-0x0: 0xe9,0x35,0x64 == jmp 0x6438
-
-!# issue 456
-!# CS_ARCH_X86, CS_MODE_16, None
-0x0: 0x66,0xe9,0x35,0x64,0x93,0x53 == jmp 0x5393643b
-
-!# issue 456
-!# CS_ARCH_X86, CS_MODE_16, None
-0x0: 0x66,0xe8,0x35,0x64,0x93,0x53 == call 0x5393643b
-
-!# issue 456
-!# CS_ARCH_X86, CS_MODE_16, None
-0x0: 0x66,0xe9,0x35,0x64,0x93,0x53 == jmp 0x5393643b
-
-!# issue 456
-!# CS_ARCH_X86, CS_MODE_32, None
-0x0: 0x66,0xe8,0x35,0x64 == call 0x6439
-
-!# issue 456
-!# CS_ARCH_X86, CS_MODE_32, None
-0x0: 0xe9,0x35,0x64,0x93,0x53 == jmp 0x5393643a
-
-!# issue 456
-!# CS_ARCH_X86, CS_MODE_32, None
-0x0: 0x66,0xe9,0x35,0x64 == jmp 0x6439
-
-!# issue 458
-!# CS_ARCH_X86, CS_MODE_32, CS_OPT_DETAIL
-0x0: 0xA1,0x12,0x34,0x90,0x90 == mov eax, dword ptr [0x90903412] ; Prefix:0x00 0x00 0x00 0x00  ; Opcode:0xa1 0x00 0x00 0x00  ; rex: 0x0 ; addr_size: 4 ; modrm: 0x0 ; disp: 0x90903412 ; sib: 0x0 ; op_count: 2 ; operands[0].type: REG = eax ; operands[0].size: 4 ; operands[0].access: WRITE ; operands[1].type: MEM ; operands[1].mem.disp: 0x90903412 ; operands[1].size: 4 ; operands[1].access: READ ; Registers modified: eax
-
-!# issue 454
-!# CS_ARCH_X86, CS_MODE_32, None
-0x0: 0xf2,0x6c == repne insb byte ptr es:[edi], dx
-
-!# issue 454
-!# CS_ARCH_X86, CS_MODE_32, None
-0x0: 0xf2,0x6d == repne insd dword ptr es:[edi], dx
-
-!# issue 454
-!# CS_ARCH_X86, CS_MODE_32, None
-0x0: 0xf2,0x6e == repne outsb dx, byte ptr [esi]
-
-!# issue 454
-!# CS_ARCH_X86, CS_MODE_32, None
-0x0: 0xf2,0x6f == repne outsd dx, dword ptr [esi]
-
-!# issue 454
-!# CS_ARCH_X86, CS_MODE_32, None
-0x0: 0xf2,0xac == repne lodsb al, byte ptr [esi]
-
-!# issue 454
-!# CS_ARCH_X86, CS_MODE_32, None
-0x0: 0xf2,0xad == repne lodsd eax, dword ptr [esi]
-
-!# issue 450
-!# CS_ARCH_X86, CS_MODE_32, CS_OPT_DETAIL
-0x0: 0xff,0x2d,0x34,0x35,0x23,0x01 == jmp ptr [0x1233534] ; Prefix:0x00 0x00 0x00 0x00  ; Opcode:0xff 0x00 0x00 0x00  ; rex: 0x0 ; addr_size: 4 ; modrm: 0x2d ; disp: 0x1233534 ; sib: 0x0 ; op_count: 1 ; operands[0].type: MEM ; operands[0].mem.disp: 0x1233534 ; operands[0].size: 6 ; Groups: jump 
-
-!# issue 448
-!# CS_ARCH_X86, CS_MODE_32, CS_OPT_DETAIL
-0x0: 0xea,0x12,0x34,0x56,0x78,0x9a,0xbc == ljmp 0xbc9a:0x78563412 ; Prefix:0x00 0x00 0x00 0x00  ; Opcode:0xea 0x00 0x00 0x00  ; rex: 0x0 ; addr_size: 4 ; modrm: 0x0 ; disp: 0x0 ; sib: 0x0 ; imm_count: 2 ; imms[1]: 0xbc9a ; imms[2]: 0x78563412 ; op_count: 2 ; operands[0].type: IMM = 0xbc9a ; operands[0].size: 2 ; operands[1].type: IMM = 0x78563412 ; operands[1].size: 4 ; Groups: not64bitmode jump 
-
-!# issue 426
-!# CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN, None
-0x0: 0xbb,0x70,0x00,0x00 == popc %g0, %i5
-
-!# issue 358
-!# CS_ARCH_X86, CS_MODE_32, CS_OPT_DETAIL
-0x0: 0xe8,0xe3,0xf6,0xff,0xff == call 0xfffff6e8 ; Prefix:0x00 0x00 0x00 0x00  ; Opcode:0xe8 0x00 0x00 0x00  ; rex: 0x0 ; addr_size: 4 ; modrm: 0x0 ; disp: 0x0 ; sib: 0x0 ; imm_count: 1 ; imms[1]: 0xfffff6e8 ; op_count: 1 ; operands[0].type: IMM = 0xfffff6e8 ; operands[0].size: 4 ; Registers read: esp eip ; Registers modified: esp ; Groups: call branch_relative not64bitmode 
-
-!# issue 353
-!# CS_ARCH_X86, CS_MODE_32, CS_OPT_DETAIL
-0x0: 0xe6,0xa2 == out 0xa2, al ; Prefix:0x00 0x00 0x00 0x00  ; Opcode:0xe6 0x00 0x00 0x00  ; rex: 0x0 ; addr_size: 4 ; modrm: 0x0 ; disp: 0x0 ; sib: 0x0 ; imm_count: 1 ; imms[1]: 0xa2 ; op_count: 2 ; operands[0].type: IMM = 0xa2 ; operands[0].size: 1 ; operands[1].type: REG = al ; operands[1].size: 1 ; operands[1].access: READ ; Registers read: al
-
-!# issue 305
-!# CS_ARCH_X86, CS_MODE_32, None
-0x0: 0x34,0x8b == xor al, 0x8b
-
-!# issue 298
-!# CS_ARCH_X86, CS_MODE_32, None
-0x0: 0xf3,0x90 == pause 
-
-!# issue 298
-!# CS_ARCH_X86, CS_MODE_32, None
-0x0: 0x66,0xf3,0xf2,0x0f,0x59,0xff == mulsd xmm7, xmm7
-
-// !# issue 298
-// !# CS_ARCH_X86, CS_MODE_32, None
-// 0x0: 0xf2,0x66,0x0f,0x59,0xff == mulpd xmm7, xmm7
-
-!# issue 294
-!# CS_ARCH_X86, CS_MODE_32, CS_OPT_DETAIL
-0x0: 0xc1,0xe6,0x08 == shl esi, 8 ; Prefix:0x00 0x00 0x00 0x00  ; Opcode:0xc1 0x00 0x00 0x00  ; rex: 0x0 ; addr_size: 4 ; modrm: 0xe6 ; disp: 0x0 ; sib: 0x0 ; imm_count: 1 ; imms[1]: 0x8 ; op_count: 2 ; operands[0].type: REG = esi ; operands[0].size: 4 ; operands[0].access: READ | WRITE ; operands[1].type: IMM = 0x8 ; operands[1].size: 1 ; Registers read: esi ; Registers modified: eflags esi ; EFLAGS: MOD_CF MOD_SF MOD_ZF MOD_PF MOD_OF UNDEF_AF
-
-!# issue 285
-!# CS_ARCH_X86, CS_MODE_32, CS_OPT_DETAIL
-0x0: 0x3c,0x12,0x80 == cmp al, 0x12 ; Prefix:0x00 0x00 0x00 0x00  ; Opcode:0x3c 0x00 0x00 0x00  ; rex: 0x0 ; addr_size: 4 ; modrm: 0x0 ; disp: 0x0 ; sib: 0x0 ; imm_count: 1 ; imms[1]: 0x12 ; op_count: 2 ; operands[0].type: REG = al ; operands[0].size: 1 ; operands[0].access: READ ; operands[1].type: IMM = 0x12 ; operands[1].size: 1 ; Registers read: al ; Registers modified: eflags ; EFLAGS: MOD_AF MOD_CF MOD_SF MOD_ZF MOD_PF MOD_OF
-
-!# issue 265
-!# CS_ARCH_ARM, CS_MODE_THUMB, CS_OPT_DETAIL
-0x0: 0x52,0xf8,0x23,0x30 == dr.w r3, [r2, r3, lsl #2] ; op_count: 2 ; operands[0].type: REG = r3 ; operands[0].access: WRITE ; operands[1].type: MEM ; operands[1].mem.base: REG = r2 ; operands[1].mem.index: REG = r3 ; operands[1].mem.scale: 0 ; Shift: 2 = 2 ; Registers read: r2 r3 ; Registers modified: r3 ; Groups: IsThumb2
-
-!# issue 264
-!# CS_ARCH_ARM, CS_MODE_THUMB, None
-0x0: 0x0c,0xbf == ite eq
-
-!# issue 264
-!# CS_ARCH_ARM, CS_MODE_THUMB, None
-0x0: 0x17,0x20 == movs r0, #0x17
-
-!# issue 264
-!# CS_ARCH_ARM, CS_MODE_THUMB, None
-0x0: 0x4f,0xf0,0xff,0x30 == mov.w r0, #0xffffffff
-
-!# issue 246
-!# CS_ARCH_ARM, CS_MODE_THUMB, None
-0x0: 0x52,0xf8,0x23,0xf0 == ldr.w pc, [r2, r3, lsl #2]
-
-!# issue 232
-!# CS_ARCH_X86, CS_MODE_32, CS_OPT_DETAIL
-0x0: 0x8e,0x10 == mov ss, word ptr [eax] ; Prefix:0x00 0x00 0x00 0x00  ; Opcode:0x8e 0x00 0x00 0x00  ; rex: 0x0 ; addr_size: 4 ; modrm: 0x10 ; disp: 0x0 ; sib: 0x0 ; op_count: 2 ; operands[0].type: REG = ss ; operands[0].size: 2 ; operands[0].access: WRITE ; operands[1].type: MEM ; operands[1].mem.base: REG = eax ; operands[1].size: 2 ; operands[1].access: READ ; Registers read: eax ; Registers modified: ss ; Groups: privilege 
-
-!# issue 231
-!# CS_ARCH_X86, CS_MODE_32, CS_OPT_DETAIL
-0x0: 0x66,0x6b,0xc0,0x02 == imul ax, ax, 2 ; Prefix:0x00 0x00 0x66 0x00  ; Opcode:0x6b 0x00 0x00 0x00  ; rex: 0x0 ; addr_size: 4 ; modrm: 0xc0 ; disp: 0x0 ; sib: 0x0 ; imm_count: 1 ; imms[1]: 0x2 ; op_count: 3 ; operands[0].type: REG = ax ; operands[0].size: 2 ; operands[0].access: WRITE ; operands[1].type: REG = ax ; operands[1].size: 2 ; operands[1].access: READ ; operands[2].type: IMM = 0x2 ; operands[2].size: 2 ; Registers read: ax ; Registers modified: eflags ax ; EFLAGS: MOD_CF MOD_SF MOD_OF UNDEF_ZF UNDEF_PF UNDEF_AF
-
-!# issue 230
-!# CS_ARCH_X86, CS_MODE_32, CS_OPT_DETAIL
-0x0: 0xec == in al, dx ; Prefix:0x00 0x00 0x00 0x00  ; Opcode:0xec 0x00 0x00 0x00  ; rex: 0x0 ; addr_size: 4 ; modrm: 0x0 ; disp: 0x0 ; sib: 0x0 ; op_count: 2 ; operands[0].type: REG = al ; operands[0].size: 1 ; operands[0].access: WRITE ; operands[1].type: REG = dx ; operands[1].size: 2 ; operands[1].access: READ ; Registers read: dx ; Registers modified: al
-
-!# issue 213
-!# CS_ARCH_X86, CS_MODE_16, None
-0x0: 0xea,0xaa,0xff,0x00,0xf0 == ljmp 0xf000:0xffaa
-
-!# issue 191
-!# CS_ARCH_X86, CS_MODE_64, None
-0x0: 0xc5,0xe8,0xc2,0x33,0x9b == vcmpps xmm6, xmm2, xmmword ptr [rbx], 0x9b
-
-!# issue 176
-!# CS_ARCH_ARM, CS_MODE_ARM, None
-0x0: 0xfd,0xff,0xff,0x1a == bne 0xfffffffc
-
-!# issue 151
-!# CS_ARCH_X86, CS_MODE_64, None
-0x0: 0x4d,0x8d,0x3d,0x02,0x00,0x00,0x00 == lea r15, [rip + 2]
-
-!# issue 151
-!# CS_ARCH_X86, CS_MODE_64, None
-0x0: 0xeb,0xb0 == jmp 0xffffffffffffffb2
-
-!# issue 134
-!# CS_ARCH_ARM, CS_MODE_BIG_ENDIAN, CS_OPT_DETAIL
-0x0: 0xe7,0x92,0x11,0x80 == ldr r1, [r2, r0, lsl #3] ; op_count: 2 ; operands[0].type: REG = r1 ; operands[0].access: WRITE ; operands[1].type: MEM ; operands[1].mem.base: REG = r2 ; operands[1].mem.index: REG = r0 ; operands[1].access: READ ; Shift: 2 = 3 ; Registers read: r2 r0 ; Registers modified: r1 ; Groups: IsARM
-
-!# issue 133
-!# CS_ARCH_ARM, CS_MODE_BIG_ENDIAN, CS_OPT_DETAIL
-0x0: 0xed,0xdf,0x2b,0x1b == vldr d18, [pc, #0x6c] ; op_count: 2 ; operands[0].type: REG = d18 ; operands[0].access: WRITE ; operands[1].type: MEM ; operands[1].mem.base: REG = r15 ; operands[1].mem.disp: 0x6c ; operands[1].access: READ ; Registers read: r15 ; Registers modified: d18 ; Groups: HasFPRegs
-
-!# issue 132
-!# CS_ARCH_ARM, CS_MODE_THUMB | CS_MODE_BIG_ENDIAN, CS_OPT_DETAIL
-0x0: 0x49,0x19 == ldr r1, [pc, #0x64] ; op_count: 2 ; operands[0].type: REG = r1 ; operands[0].access: WRITE ; operands[1].type: MEM ; operands[1].mem.base: REG = r15 ; operands[1].mem.disp: 0x64 ; operands[1].access: READ ; Registers read: r15 ; Registers modified: r1 ; Groups: IsThumb
-
-!# issue 130
-!# CS_ARCH_ARM, CS_MODE_BIG_ENDIAN, CS_OPT_DETAIL
-0x0: 0xe1,0xa0,0xf0,0x0e == mov pc, lr ; op_count: 2 ; operands[0].type: REG = r15 ; operands[0].access: WRITE ; operands[1].type: REG = r14 ; operands[1].access: READ ; Registers read: r14 ; Registers modified: r15 ; Groups: jump return IsARM
-
-!# issue 85
-!# CS_ARCH_AARCH64, CS_MODE_LITTLE_ENDIAN, None
-0x0: 0xee,0x3f,0xbf,0x29 == stp w14, w15, [sp, #-8]!
-
-!# issue 82
-!# CS_ARCH_X86, CS_MODE_64, None
-0x0: 0xf2,0x66,0xaf == repne scasw ax, word ptr [rdi]
-
-!# issue 35
-!# CS_ARCH_X86, CS_MODE_32, None
-0x0: 0xe8,0xc6,0x02,0x00,0x00 == call 0x2cb
-
-!# issue 8
-!# CS_ARCH_X86, CS_MODE_32, None
-0x0: 0xff,0x8c,0xf9,0xff,0xff,0x9b,0xf9 == dec dword ptr [ecx + edi*8 - 0x6640001]
-
-!# issue 29
-!# CS_ARCH_AARCH64, CS_MODE_ARM, None
-0x0: 0x00,0x00,0x00,0x4c == st4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x0]
-
-!# issue 2233 ARM write to PC is branch
-!# CS_ARCH_ARM, CS_MODE_THUMB, CS_OPT_DETAIL
-0x87,0x46 == mov pc, r0 ; Groups: IsThumb jump 
-
-!# issue 2128
-!# CS_ARCH_X86, CS_MODE_64, CS_OPT_DETAIL
-0x0: 0x4c,0x85,0x7d,0x30 == test	qword ptr [rbp + 0x30], r15 ; operands[1].type: REG = r15 ; operands[1].access: READ ; Registers read: rbp r15 ; Registers modified: rflags
-
-!# issue 2079
-!# CS_ARCH_X86, CS_MODE_32, CS_OPT_DETAIL
-0x0: 0xd1,0x10 == rcl	dword ptr [eax] ; operands[1].type: IMM = 0x1
-
-!# issue 2244
-!# CS_ARCH_X86, CS_MODE_64, CS_OPT_DETAIL
-0x0: 0xc5,0xfb,0xc2,0xda,0x06 == vcmpnlesd	xmm3, xmm0, xmm2 ; ID: 797
-
-!# issue 2349
-!# CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, CS_OPT_DETAIL
-0x0: 0xcf, 0x41, 0xd0, 0x28 == ld.d $t3, $t2, 0x410 ; operands[1].type: MEM ; operands[1].mem.base: REG = t2 ; operands[1].mem.disp: 0x410
-
-!# issue 2349
-!# CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, CS_OPT_DETAIL
-0x0: 0x8d, 0x59, 0x10, 0x27 == stptr.d $t1, $t0, 0x1058 ; operands[1].type: MEM ; operands[1].mem.base: REG = t0 ; operands[1].mem.disp: 0x1058
-
-!# issue 2349
-!# CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, CS_OPT_DETAIL
-0x0: 0xa4, 0x15, 0x20, 0x30 == vldrepl.w $vr4, $t1, 0x14 ; operands[1].type: MEM ; operands[1].mem.base: REG = t1 ; operands[1].mem.disp: 0x14
-
-!# issue 2349
-!# CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, CS_OPT_DETAIL
-0x0: 0x68, 0x22, 0xc2, 0x2a == preld 8, $t7, 0x88 ; operands[1].type: MEM ; operands[1].mem.base: REG = t7 ; operands[1].mem.disp: 0x88
-
-!# issue 2349
-!# CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, CS_OPT_DETAIL
-0x0: 0xe1, 0x2c, 0x30, 0x38 == fldx.s $fa1, $a3, $a7 ; operands[1].type: MEM ; operands[1].mem.base: REG = a3 ; operands[1].mem.index: REG = a7
-
-!# issue 2349
-!# CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, CS_OPT_DETAIL
-0x0: 0xc4, 0x14, 0x57, 0x38 == sc.q $a0, $a1, $a2 ; operands[2].type: MEM ; operands[2].mem.base: REG = a2
-
-!# issue 2349
-!# CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, CS_OPT_DETAIL
-0x0: 0xc4, 0x14, 0x61, 0x38 == amadd.w $a0, $a1, $a2 ; operands[2].type: MEM ; operands[2].mem.base: REG = a2
-
-!# issue 2349
-!# CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64, CS_OPT_DETAIL
-0x0: 0xa4, 0x18, 0x78, 0x38 == ldgt.b $a0, $a1, $a2 ; operands[1].type: MEM ; operands[1].mem.base: REG = a1 ; operands[2].type: REG = a2
-
-!# issue 2268
-!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL
-0x0: 0x00,0x80,0x58,0x65 == fadd z0.h, p0/m, z0.h, #0.5 ; operands[3].subtype EXACTFPIMM = 1
-
-!# issue 2268
-!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL
-0x0: 0x20,0x80,0x58,0x65 == fadd z0.h, p0/m, z0.h, #1.0 ; operands[3].subtype EXACTFPIMM = 2
-
-!# issue 2268
-!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL
-0x0: 0x3f,0x9c,0xda,0x65 == fmul z31.d, p7/m, z31.d, #2.0 ; operands[3].subtype EXACTFPIMM = 3
-
-!# issue 2268
-!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL
-0x0: 0x6a,0xd9,0xf8,0x7e == fcmle h10, h11, #0.0 ; operands[2].subtype EXACTFPIMM = 0
-
-!# issue 2419
-!# CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN, CS_OPT_DETAIL
-0x0: 0x12,0xbf,0xff,0xff == bne -4 ; Code condition: 265
diff --git a/suite/cstest/src/aarch64_detail.c b/suite/cstest/src/aarch64_detail.c
deleted file mode 100644
index e6cafa143..000000000
--- a/suite/cstest/src/aarch64_detail.c
+++ /dev/null
@@ -1,245 +0,0 @@
-/* Capstone testing regression */
-/* By Do Minh Tuan <tuanit96@gmail.com>, 02-2019 */
-
-
-#include "factory.h"
-
-char *get_detail_aarch64(csh *handle, cs_mode mode, cs_insn *ins)
-{
-	cs_aarch64 *aarch64;
-	int i;
-	cs_regs regs_read, regs_write;
-	uint8_t regs_read_count, regs_write_count;
-	uint8_t access;
-	char *result;
-
-	result = (char *)malloc(sizeof(char));
-	result[0] = '\0';
-
-	// detail can be NULL if SKIPDATA option is turned ON
-	if (ins->detail == NULL)
-		return result;
-
-	aarch64 = &(ins->detail->aarch64);
-	if (aarch64->op_count)
-		add_str(&result, " ; op_count: %u", aarch64->op_count);
-
-	for (i = 0; i < aarch64->op_count; i++) {
-		cs_aarch64_op *op = &(aarch64->operands[i]);
-		switch(op->type) {
-			default:
-				break;
-			case AARCH64_OP_REG:
-				add_str(&result, " ; operands[%u].type: REG = %s%s", i, cs_reg_name(*handle, op->reg), op->is_vreg ? " (vreg)" : "");
-			if (op->is_list_member) {
-				add_str(&result, " ; operands[%u].is_list_member: true", i);
-			}
-				break;
-			case AARCH64_OP_IMM:
-				add_str(&result, " ; operands[%u].type: IMM = 0x%" PRIx64, i, op->imm);
-				break;
-			case AARCH64_OP_FP:
-#if defined(_KERNEL_MODE)
-				// Issue #681: Windows kernel does not support formatting float point
-				add_str(&result, " ; operands[%u].type: FP = <float_point_unsupported>", i);
-#else
-				add_str(&result, " ; operands[%u].type: FP = %f", i, op->fp);
-#endif
-				break;
-			case AARCH64_OP_MEM:
-				add_str(&result, " ; operands[%u].type: MEM", i);
-				if (op->mem.base != AARCH64_REG_INVALID)
-					add_str(&result, " ; operands[%u].mem.base: REG = %s", i, cs_reg_name(*handle, op->mem.base));
-				if (op->mem.index != AARCH64_REG_INVALID)
-					add_str(&result, " ; operands[%u].mem.index: REG = %s", i, cs_reg_name(*handle, op->mem.index));
-				if (op->mem.disp != 0)
-					add_str(&result, " ; operands[%u].mem.disp: 0x%x", i, op->mem.disp);
-
-				break;
-			case AARCH64_OP_CIMM:
-				add_str(&result, " ; operands[%u].type: C-IMM = %u", i, (int)op->imm);
-				break;
-			case AARCH64_OP_REG_MRS:
-				add_str(&result, " ; operands[%u].type: REG_MRS = 0x%x", i, op->reg);
-				break;
-			case AARCH64_OP_REG_MSR:
-				add_str(&result, " ; operands[%u].type: REG_MSR = 0x%x", i, op->reg);
-				break;
-			case AARCH64_OP_SME:
-				add_str(&result, " ; operands[%u].type: SME_MATRIX", i);
-				add_str(&result, " ; operands[%u].sme.type: %d", i, op->sme.type);
-
-				if (op->sme.tile != AARCH64_REG_INVALID)
-					add_str(&result, " ; operands[%u].sme.tile: %s", i, cs_reg_name(*handle, op->sme.tile));
-				if (op->sme.slice_reg != AARCH64_REG_INVALID)
-					add_str(&result, " ; operands[%u].sme.slice_reg: %s", i, cs_reg_name(*handle, op->sme.slice_reg));
-				if (op->sme.slice_offset.imm != -1 || op->sme.slice_offset.imm_range.first != -1) {
-					add_str(&result, " ; operands[%u].sme.slice_offset: ", i);
-					if (op->sme.has_range_offset)
-						add_str(&result, "%hhd:%hhd", op->sme.slice_offset.imm_range.first, op->sme.slice_offset.imm_range.offset);
-					else
-						add_str(&result, "%d", op->sme.slice_offset.imm);
-				}
-				if (op->sme.slice_reg != AARCH64_REG_INVALID || op->sme.slice_offset.imm != -1)
-					add_str(&result, " ; operands[%u].sme.is_vertical: %s", i, (op->sme.is_vertical ? "true" : "false"));
-			break;
-		case AARCH64_OP_PRED:
-			add_str(&result, " ; operands[%u].type: PREDICATE", i);
-			if (op->pred.reg != AARCH64_REG_INVALID)
-				add_str(&result, " ; operands[%u].pred.reg: %s", i, cs_reg_name(*handle, op->pred.reg));
-			if (op->pred.vec_select != AARCH64_REG_INVALID)
-				add_str(&result, " ; operands[%u].pred.vec_select: %s", i, cs_reg_name(*handle, op->pred.vec_select));
-			if (op->pred.imm_index != -1)
-				add_str(&result, " ; operands[%u].pred.imm_index: %d", i, op->pred.imm_index);
-			break;
-		case AARCH64_OP_SYSREG:
-			add_str(&result, " ; operands[%u].type: SYS REG:", i);
-			switch (op->sysop.sub_type) {
-			default:
-				break;
-			case AARCH64_OP_REG_MRS:
-				add_str(&result, " ; operands[%u].subtype: REG_MRS = 0x%x", i, op->sysop.reg.sysreg);
-				break;
-			case AARCH64_OP_REG_MSR:
-				add_str(&result, " ; operands[%u].subtype: REG_MSR = 0x%x", i, op->sysop.reg.sysreg);
-				break;
-			case AARCH64_OP_TLBI:
-				add_str(&result, " ; operands[%u].subtype TLBI = 0x%x", i, op->sysop.reg.tlbi);
-				break;
-			case AARCH64_OP_IC:
-				add_str(&result, " ; operands[%u].subtype IC = 0x%x", i, op->sysop.reg.ic);
-				break;
-			}
-			break;
-		case AARCH64_OP_SYSALIAS:
-			add_str(&result, " ; operands[%u].type: SYS ALIAS:", i);
-			switch (op->sysop.sub_type) {
-			default:
-				break;
-			case AARCH64_OP_SVCR:
-				if(op->sysop.alias.svcr == AARCH64_SVCR_SVCRSM)
-					add_str(&result, " ; operands[%u].svcr: BIT = SM", i);
-				else if(op->sysop.alias.svcr == AARCH64_SVCR_SVCRZA)
-					add_str(&result, " ; operands[%u].svcr: BIT = ZA", i);
-				else if(op->sysop.alias.svcr == AARCH64_SVCR_SVCRSMZA)
-					add_str(&result, " ; operands[%u].svcr: BIT = SM & ZA", i);
-				break;
-			case AARCH64_OP_AT:
-				add_str(&result, " ; operands[%u].subtype AT = 0x%x", i, op->sysop.alias.at);
-				break;
-			case AARCH64_OP_DB:
-				add_str(&result, " ; operands[%u].subtype DB = 0x%x", i, op->sysop.alias.db);
-				break;
-			case AARCH64_OP_DC:
-				add_str(&result, " ; operands[%u].subtype DC = 0x%x", i, op->sysop.alias.dc);
-				break;
-			case AARCH64_OP_ISB:
-				add_str(&result, " ; operands[%u].subtype ISB = 0x%x", i, op->sysop.alias.isb);
-				break;
-			case AARCH64_OP_TSB:
-				add_str(&result, " ; operands[%u].subtype TSB = 0x%x", i, op->sysop.alias.tsb);
-				break;
-			case AARCH64_OP_PRFM:
-				add_str(&result, " ; operands[%u].subtype PRFM = 0x%x", i, op->sysop.alias.prfm);
-				break;
-			case AARCH64_OP_SVEPRFM:
-				add_str(&result, " ; operands[%u].subtype SVEPRFM = 0x%x", i, op->sysop.alias.sveprfm);
-				break;
-			case AARCH64_OP_RPRFM:
-				add_str(&result, " ; operands[%u].subtype RPRFM = 0x%x", i, op->sysop.alias.rprfm);
-				break;
-			case AARCH64_OP_PSTATEIMM0_15:
-				add_str(&result, " ; operands[%u].subtype PSTATEIMM0_15 = 0x%x", i, op->sysop.alias.pstateimm0_15);
-				break;
-			case AARCH64_OP_PSTATEIMM0_1:
-				add_str(&result, " ; operands[%u].subtype PSTATEIMM0_1 = 0x%x", i, op->sysop.alias.pstateimm0_1);
-				break;
-			case AARCH64_OP_PSB:
-				add_str(&result, " ; operands[%u].subtype PSB = 0x%x", i, op->sysop.alias.psb);
-				break;
-			case AARCH64_OP_BTI:
-				add_str(&result, " ; operands[%u].subtype BTI = 0x%x", i, op->sysop.alias.bti);
-				break;
-			case AARCH64_OP_SVEPREDPAT:
-				add_str(&result, " ; operands[%u].subtype SVEPREDPAT = 0x%x", i, op->sysop.alias.svepredpat);
-				break;
-			case AARCH64_OP_SVEVECLENSPECIFIER:
-				add_str(&result, " ; operands[%u].subtype SVEVECLENSPECIFIER = 0x%x", i, op->sysop.alias.sveveclenspecifier);
-				break;
-			}
-			break;
-		case AARCH64_OP_SYSIMM:
-			add_str(&result, " ; operands[%u].type: SYS IMM:", i);
-			switch(op->sysop.sub_type) {
-			default:
-				break;
-			case AARCH64_OP_EXACTFPIMM:
-				add_str(&result, " ; operands[%u].subtype EXACTFPIMM = %d", i, op->sysop.imm.exactfpimm);
-				break;
-			case AARCH64_OP_DBNXS:
-				add_str(&result, " ; operands[%u].subtype DBNXS = %d", i, op->sysop.imm.dbnxs);
-				break;
-			}
-			break;
-		}
-		
-		access = op->access;
-		switch(access) {
-			default:
-				break;
-			case CS_AC_READ:
-				add_str(&result, " ; operands[%u].access: READ", i);
-				break;
-			case CS_AC_WRITE:
-				add_str(&result, " ; operands[%u].access: WRITE", i);
-				break;
-			case CS_AC_READ | CS_AC_WRITE:
-				add_str(&result, " ; operands[%u].access: READ | WRITE", i);
-				break;
-		}
-		
-		if (op->shift.type != AARCH64_SFT_INVALID &&
-			op->shift.value)
-			add_str(&result, " ; Shift: type = %u, value = %u",
-				   op->shift.type, op->shift.value);
-
-		if (op->ext != AARCH64_EXT_INVALID)
-			add_str(&result, " ; Ext: %u", op->ext);
-
-		if (op->vas != AARCH64LAYOUT_INVALID)
-			add_str(&result, " ; operands[%u].vas: 0x%x", i, op->vas);
-
-		if (op->vector_index != -1)
-			add_str(&result, " ; operands[%u].vector_index: %u", i, op->vector_index);
-	}
-
-	if (aarch64->update_flags)
-		add_str(&result, " ; Update-flags: True");
-
-	if (ins->detail->writeback)
-		add_str(&result, " ; Write-back: True");
-
-	if (aarch64->cc)
-		add_str(&result, " ; Code-condition: %u", aarch64->cc);
-
-	// Print out all registers accessed by this instruction (either implicit or explicit)
-	if (!cs_regs_access(*handle, ins,
-						regs_read, &regs_read_count,
-						regs_write, &regs_write_count)) {
-		if (regs_read_count) {
-			add_str(&result, " ; Registers read:");
-			for(i = 0; i < regs_read_count; i++) {
-				add_str(&result, " %s", cs_reg_name(*handle, regs_read[i]));
-			}
-		}
-		
-		if (regs_write_count) {
-			add_str(&result, " ; Registers modified:");
-			for(i = 0; i < regs_write_count; i++) {
-				add_str(&result, " %s", cs_reg_name(*handle, regs_write[i]));
-			}
-		}
-	}
-
-	return result;
-}
diff --git a/suite/cstest/src/alpha_detail.c b/suite/cstest/src/alpha_detail.c
deleted file mode 100644
index 4f4178337..000000000
--- a/suite/cstest/src/alpha_detail.c
+++ /dev/null
@@ -1,69 +0,0 @@
-/* Capstone testing regression */
-/* By Dmitry Sibirtsev <sibirtsevdl@gmail.com>, 2023 */
-
-#include "factory.h"
-
-char *get_detail_alpha(csh *p_handle, cs_mode mode, cs_insn *ins)
-{
-	cs_alpha *alpha;
-	int i;
-	cs_regs regs_read, regs_write;
-	uint8_t regs_read_count, regs_write_count;
-
-	char *result;
-	result = (char *)malloc(sizeof(char));
-	result[0] = '\0';
-
-	if (ins->detail == NULL)
-		return result;
-
-	csh handle = *p_handle;
-
-	alpha = &(ins->detail->alpha);
-
-	if (alpha->op_count)
-		add_str(&result, "\top_count: %u\n", alpha->op_count);
-
-	for (i = 0; i < alpha->op_count; i++) {
-		cs_alpha_op *op = &(alpha->operands[i]);
-		switch ((int)op->type) {
-		default:
-			break;
-		case ALPHA_OP_REG:
-			add_str(&result, "\t\toperands[%u].type: REG = %s\n", i,
-				cs_reg_name(handle, op->reg));
-			break;
-		case ALPHA_OP_IMM:
-			add_str(&result, "\t\toperands[%u].type: IMM = 0x%x\n",
-				i, op->imm);
-			break;
-		}
-
-		// Print out all registers accessed by this instruction (either implicit or
-		// explicit)
-		if (!cs_regs_access(handle, ins, regs_read, &regs_read_count,
-				    regs_write, &regs_write_count)) {
-			if (regs_read_count) {
-				add_str(&result, "\tRegisters read:");
-				for (i = 0; i < regs_read_count; i++) {
-					add_str(&result, " %s",
-						cs_reg_name(handle,
-							    regs_read[i]));
-				}
-				add_str(&result, "\n");
-			}
-
-			if (regs_write_count) {
-				add_str(&result, "\tRegisters modified:");
-				for (i = 0; i < regs_write_count; i++) {
-					add_str(&result, " %s",
-						cs_reg_name(handle,
-							    regs_write[i]));
-				}
-				add_str(&result, "\n");
-			}
-		}
-	}
-
-	return result;
-}
diff --git a/suite/cstest/src/arm_detail.c b/suite/cstest/src/arm_detail.c
deleted file mode 100644
index 42ac67e5e..000000000
--- a/suite/cstest/src/arm_detail.c
+++ /dev/null
@@ -1,185 +0,0 @@
-/* Capstone testing regression */
-/* By Do Minh Tuan <tuanit96@gmail.com>, 02-2019 */
-
-
-#include "factory.h" 
-
-char *get_detail_arm(csh *handle, cs_mode mode, cs_insn *ins)
-{
-	cs_arm *arm;
-	int i;
-	cs_regs regs_read, regs_write;
-	uint8_t regs_read_count, regs_write_count;
-	char *result;
-
-	result = (char *)malloc(sizeof(char));
-	result[0] = '\0';
-
-	if (ins->detail == NULL)
-		return result;
-
-	arm = &(ins->detail->arm);
-
-	if (arm->op_count)
-		add_str(&result, " ; op_count: %u", arm->op_count);
-
-	for (i = 0; i < arm->op_count; i++) {
-		cs_arm_op *op = &(arm->operands[i]);
-		switch((int)op->type) {
-			default:
-				break;
-			case ARM_OP_REG:
-				add_str(&result, " ; operands[%u].type: REG = %s", i, cs_reg_name(*handle, op->reg));
-				break;
-			case ARM_OP_IMM:
-				add_str(&result, " ; operands[%u].type: IMM = 0x%x", i, op->imm);
-				break;
-			case ARM_OP_FP:
-#if defined(_KERNEL_MODE)
-				// Issue #681: Windows kernel does not support formatting float point
-				add_str(&result, " ; operands[%u].type: FP = <float_point_unsupported>", i);
-#else
-				add_str(&result, " ; operands[%u].type: FP = %f", i, op->fp);
-#endif
-				break;
-			case ARM_OP_MEM:
-				add_str(&result, " ; operands[%u].type: MEM", i);
-				if (op->mem.base != ARM_REG_INVALID)
-					add_str(&result, " ; operands[%u].mem.base: REG = %s", i, cs_reg_name(*handle, op->mem.base));
-				if (op->mem.index != ARM_REG_INVALID)
-					add_str(&result, " ; operands[%u].mem.index: REG = %s", i, cs_reg_name(*handle, op->mem.index));
-				if (op->mem.scale != 1)
-					add_str(&result, " ; operands[%u].mem.scale: %d", i, op->mem.scale);
-				if (op->mem.disp != 0)
-					add_str(&result, " ; operands[%u].mem.disp: 0x%x", i, op->mem.disp);
-				if (op->mem.align != 0)
-					add_str(&result, " ; operands[%u].mem.align: 0x%x", i, op->mem.align);
-				if (op->mem.lshift != 0)
-					add_str(&result, " ; operands[%u].mem.lshift: 0x%x", i, op->mem.lshift);
-
-				break;
-			case ARM_OP_PIMM:
-				add_str(&result, " ; operands[%u].type: P-IMM = %u", i, op->imm);
-				break;
-			case ARM_OP_CIMM:
-				add_str(&result, " ; operands[%u].type: C-IMM = %u", i, op->imm);
-				break;
-			case ARM_OP_SETEND:
-				add_str(&result, " ; operands[%u].type: SETEND = %s", i, op->setend == ARM_SETEND_BE? "be" : "le");
-				break;
-			case ARM_OP_SYSM:
-				add_str(&result, " ; operands[%u].type: SYSM = 0x%" PRIx16 "\n", i, op->sysop.sysm);
-				add_str(&result, " ; operands[%u].type: MASK = %" PRIu8 "\n", i, op->sysop.msr_mask);
-				break;
-			case ARM_OP_SYSREG:
-				add_str(&result, " ; operands[%u].type: SYSREG = %s", i, cs_reg_name(*handle, (uint32_t) op->sysop.reg.mclasssysreg));
-				add_str(&result, " ; operands[%u].type: MASK = %" PRIu8, i, op->sysop.msr_mask);
-				break;
-			case ARM_OP_BANKEDREG:
-				// FIXME: Printing the name is currenliy not supported if the encodings overlap
-				// with system registers.
-				add_str(&result, " ; operands[%u].type: BANKEDREG = %" PRIu32, i, (uint32_t) op->sysop.reg.bankedreg);
-				if (op->sysop.msr_mask != UINT8_MAX)
-					add_str(&result, " ; operands[%u].type: MASK = %" PRIu8, i, op->sysop.msr_mask);
-			case ARM_OP_SPSR:
-			case ARM_OP_CPSR: {
-				const char type = op->type == ARM_OP_SPSR ? 'S' : 'C';
-				add_str(&result, " ; operands[%u].type: %cPSR = ", i, type);
-				uint16_t field = op->sysop.psr_bits;
-				if ((field & ARM_FIELD_SPSR_F) || (field & ARM_FIELD_CPSR_F))
-					add_str(&result, "f");
-				if ((field & ARM_FIELD_SPSR_S) || (field & ARM_FIELD_CPSR_S))
-					add_str(&result, "s");
-				if ((field & ARM_FIELD_SPSR_X) || (field & ARM_FIELD_CPSR_X))
-					add_str(&result, "x");
-				if ((field & ARM_FIELD_SPSR_C) || (field & ARM_FIELD_CPSR_C))
-					add_str(&result, "c");
-				add_str(&result, " ; operands[%u].type: MASK = %" PRIu8, i, op->sysop.msr_mask);
-				break;
-			}
-		}
-
-		if (op->neon_lane != -1) {
-			add_str(&result, " ; operands[%u].neon_lane = %u", i, op->neon_lane);
-		}
-
-		switch(op->access) {
-			default:
-				break;
-			case CS_AC_READ:
-				add_str(&result, " ; operands[%u].access: READ", i);
-				break;
-			case CS_AC_WRITE:
-				add_str(&result, " ; operands[%u].access: WRITE", i);
-				break;
-			case CS_AC_READ | CS_AC_WRITE:
-				add_str(&result, " ; operands[%u].access: READ | WRITE", i);
-				break;
-		}
-
-		if (op->shift.type != ARM_SFT_INVALID && op->shift.value) {
-			if (op->shift.type < ARM_SFT_ASR_REG)
-				add_str(&result, " ; Shift: %u = %u", op->shift.type, op->shift.value);
-			else
-				add_str(&result, " ; Shift: %u = %s", op->shift.type, cs_reg_name(*handle, op->shift.value));
-		}
-
-		if (op->vector_index != -1) {
-			add_str(&result, " ; operands[%u].vector_index = %u", i, op->vector_index);
-		}
-
-		if (op->subtracted)
-			add_str(&result, " ; Subtracted: True");
-	}
-
-	if (arm->cc != ARMCC_AL && arm->cc != ARMCC_UNDEF)
-		add_str(&result, " ; Code condition: %u", arm->cc);
-
-	if (arm->pred_mask)
-		add_str(&result, " ; Predicate Mask: 0x%x", arm->pred_mask);
-
-	if (arm->vcc != ARMVCC_None)
-		add_str(&result, " ; Vector code condition: %u", arm->vcc);
-
-	if (arm->update_flags)
-		add_str(&result, " ; Update-flags: True");
-
-	if (ins->detail->writeback)
-		add_str(&result, " ; Write-back: True");
-
-	if (arm->cps_mode)
-		add_str(&result, " ; CPSI-mode: %u", arm->cps_mode);
-
-	if (arm->cps_flag)
-		add_str(&result, " ; CPSI-flag: %u", arm->cps_flag);
-
-	if (arm->vector_data)
-		add_str(&result, " ; Vector-data: %u", arm->vector_data);
-
-	if (arm->vector_size)
-		add_str(&result, " ; Vector-size: %u", arm->vector_size);
-
-	if (arm->usermode)
-		add_str(&result, " ; User-mode: True");
-
-	if (arm->mem_barrier)
-		add_str(&result, " ; Memory-barrier: %u", arm->mem_barrier);
-
-	if (!cs_regs_access(*handle, ins, regs_read, &regs_read_count, regs_write, &regs_write_count)) {
-		if (regs_read_count) {
-			add_str(&result, " ; Registers read:");
-			for(i = 0; i < regs_read_count; i++) {
-				add_str(&result, " %s", cs_reg_name(*handle, regs_read[i]));
-			}
-		}
-
-		if (regs_write_count) {
-			add_str(&result, " ; Registers modified:");
-			for(i = 0; i < regs_write_count; i++) {
-				add_str(&result, " %s", cs_reg_name(*handle, regs_write[i]));
-			}
-		}
-	}
-
-	return result;
-}
diff --git a/suite/cstest/src/bpf_detail.c b/suite/cstest/src/bpf_detail.c
deleted file mode 100644
index d72332f79..000000000
--- a/suite/cstest/src/bpf_detail.c
+++ /dev/null
@@ -1,77 +0,0 @@
-/* Capstone testing regression */
-/* By david942j <david942j@gmail.com>, 2019 */
-
-#include <capstone/platform.h>
-
-#include "factory.h"
-
-static char * ext_name[] = {
-	[BPF_EXT_LEN] = "#len",
-};
-
-char *get_detail_bpf(csh *handle, cs_mode mode, cs_insn *ins)
-{
-	cs_bpf *bpf;
-	unsigned int i;
-	cs_regs regs_read, regs_write;
-	uint8_t regs_read_count, regs_write_count;
-	char *result;
-
-	result = (char *)malloc(sizeof(char));
-	result[0] = '\0';
-	if (ins->detail == NULL)
-		return result;
-
-	bpf = &(ins->detail->bpf);
-
-	if (bpf->op_count)
-		add_str(&result, " ; op_count: %u", bpf->op_count);
-	for (i = 0; i < bpf->op_count; i++) {
-		cs_bpf_op *op = &(bpf->operands[i]);
-		add_str(&result, " ; operands[%u].type: ", i);
-		switch (op->type) {
-		case BPF_OP_INVALID:
-			add_str(&result, "INVALID");
-			break;
-		case BPF_OP_REG:
-			add_str(&result, "REG = %s", cs_reg_name(*handle, op->reg));
-			break;
-		case BPF_OP_IMM:
-			add_str(&result, "IMM = 0x%" PRIx64, op->imm);
-			break;
-		case BPF_OP_OFF:
-			add_str(&result, "OFF = +0x%x", op->off);
-			break;
-		case BPF_OP_MEM:
-			add_str(&result, "MEM [base=%s, disp=0x%x]", 
-				cs_reg_name(*handle, op->mem.base), op->mem.disp);
-			break;
-		case BPF_OP_MMEM:
-			add_str(&result, "MMEM = M[0x%x]", op->mmem);
-			break;
-		case BPF_OP_MSH:
-			add_str(&result, "MSH = 4*([0x%x]&0xf)", op->msh);
-			break;
-		case BPF_OP_EXT:
-			add_str(&result, "EXT = %s", ext_name[op->ext]);
-			break;
-		}
-	}
-
-	if (!cs_regs_access(*handle, ins,
-			regs_read, &regs_read_count,
-			regs_write, &regs_write_count)) {
-		if (regs_read_count) {
-			add_str(&result, " ; Registers read:");
-			for(i = 0; i < regs_read_count; i++)
-				add_str(&result, " %s", cs_reg_name(*handle, regs_read[i]));
-		}
-
-		if (regs_write_count) {
-			add_str(&result, " ; Registers modified:");
-			for(i = 0; i < regs_write_count; i++)
-				add_str(&result, " %s", cs_reg_name(*handle, regs_write[i]));
-		}
-	}
-	return result;
-}
diff --git a/suite/cstest/src/capstone_test.c b/suite/cstest/src/capstone_test.c
deleted file mode 100644
index 3cf3c0f88..000000000
--- a/suite/cstest/src/capstone_test.c
+++ /dev/null
@@ -1,307 +0,0 @@
-/* Capstone testing regression */
-/* By Do Minh Tuan <tuanit96@gmail.com>, 02-2019 */
-
-
-#include "../../../cs_priv.h"
-#include "capstone_test.h"
-
-char *(*function)(csh *, cs_mode, cs_insn*) = NULL;
-
-void test_single_MC(csh *handle, int mc_mode, char *line)
-{
-	char **list_part, **list_byte;
-	int size_part, size_byte;
-	int i, count;
-	unsigned char *code;
-	cs_insn *insn;
-	char tmp[MAXMEM], tmp_mc[MAXMEM], origin[MAXMEM], tmp_noreg[MAXMEM];
-	char **offset_opcode;
-	int size_offset_opcode;
-	unsigned long offset;
-	char *p;
-
-	list_part = split(line, " = ", &size_part);
-	if (size_part <= 1) {
-		free_strs(list_part, size_part);
-		return;
-	}
-
-	offset_opcode = split(list_part[0], ": ", &size_offset_opcode);
-	if (size_offset_opcode > 1) {
-		offset = (unsigned int)strtol(offset_opcode[0], NULL, 16);
-		list_byte = split(offset_opcode[1], ",", &size_byte);
-	} else {
-		offset = 0;
-		list_byte = split(offset_opcode[0], ",", &size_byte);
-	}
-
-	code = (unsigned char *)malloc(size_byte * sizeof(char));
-	for (i = 0; i < size_byte; ++i) {
-		code[i] = (unsigned char)strtol(list_byte[i], NULL, 16);
-	}
-
-	((struct cs_struct *)(uintptr_t)*handle)->PrintBranchImmNotAsAddress = true;
-	count = cs_disasm(*handle, code, size_byte, offset, 0, &insn);
-	if (count == 0) {
-		fprintf(stderr, "[  ERROR   ] --- %s --- Failed to disassemble given code!\n", list_part[0]);
-		free_strs(list_part, size_part);
-		free_strs(offset_opcode, size_offset_opcode);
-		free_strs(list_byte, size_byte);
-		free(code);
-		_fail(__FILE__, __LINE__);
-	}
-	if (count > 1) {
-		fprintf(stderr, "[  ERROR   ] --- %s --- Multiple instructions(%d) disassembling doesn't support!\n", list_part[0], count);
-		free_strs(list_part, size_part);
-		free_strs(offset_opcode, size_offset_opcode);
-		free_strs(list_byte, size_byte);
-		free(code);
-		_fail(__FILE__, __LINE__);
-	}
-
-	for (p = list_part[1]; *p; ++p) *p = tolower(*p);
-	for (p = list_part[1]; *p; ++p)
-		if (*p == '\t') *p = ' ';
-	trim_str(list_part[1]);
-	strcpy(tmp_mc, list_part[1]);
-	replace_hex(tmp_mc);
-	replace_negative(tmp_mc, mc_mode);
-	replace_tabs(tmp_mc);
-
-	strcpy(tmp, insn[0].mnemonic);
-	if (strlen(insn[0].op_str) > 0) {
-		tmp[strlen(insn[0].mnemonic)] = ' ';
-		strcpy(tmp + strlen(insn[0].mnemonic) + 1, insn[0].op_str);
-	}
-
-	trim_str(tmp);
-	strcpy(origin, tmp);
-	replace_hex(tmp);
-	replace_negative(tmp, mc_mode);
-	replace_tabs(tmp);
-	for (p = tmp; *p; ++p) *p = tolower(*p);
-
-	// Skip ARM because the duplicate disassembly messes with the IT/VPT states
-	// and laeds to wrong results.
-	cs_arch arch = ((struct cs_struct *)(uintptr_t)*handle)->arch;
-	if (arch != CS_ARCH_ARM) {
-		if (insn->detail) {
-			free(insn->detail);
-		}
-		free(insn);
-		cs_disasm(*handle, code, size_byte, offset, 0, &insn);
-
-		strcpy(tmp_noreg, insn[0].mnemonic);
-		if (strlen(insn[0].op_str) > 0) {
-			tmp_noreg[strlen(insn[0].mnemonic)] = ' ';
-			strcpy(tmp_noreg + strlen(insn[0].mnemonic) + 1, insn[0].op_str);
-		}
-
-		trim_str(tmp_noreg);
-		replace_hex(tmp_noreg);
-		replace_negative(tmp_noreg, mc_mode);
-
-		if (strcmp(tmp, tmp_mc) && strcmp(tmp_noreg, tmp_mc)) {
-			fprintf(stderr, "[  ERROR   ] --- %s --- \"%s\" != \"%s\" ( \"%s\" != \"%s\" and \"%s\" != \"%s\" )\n", list_part[0], origin, list_part[1], tmp, tmp_mc, tmp_noreg, tmp_mc);
-			free_strs(list_part, size_part);
-			free_strs(offset_opcode, size_offset_opcode);
-			free_strs(list_byte, size_byte);
-			free(code);
-			cs_free(insn, count);
-			_fail(__FILE__, __LINE__);
-		}
-	} else if (strcmp(tmp, tmp_mc)) {
-		fprintf(stderr, "[  ERROR   ] --- %s --- \"%s\" != \"%s\" ( \"%s\" != \"%s\" )\n", list_part[0], origin, list_part[1], tmp, tmp_mc);
-		free_strs(list_part, size_part);
-		free_strs(offset_opcode, size_offset_opcode);
-		free_strs(list_byte, size_byte);
-		free(code);
-		cs_free(insn, count);
-		_fail(__FILE__, __LINE__);
-	}
-
-	free_strs(list_part, size_part);
-	free_strs(offset_opcode, size_offset_opcode);
-	free_strs(list_byte, size_byte);
-	free(code);
-	cs_free(insn, count);
-}
-
-int get_value(single_dict d[], unsigned int size, const char *str)
-{
-	int i;
-
-	for (i = 0; i < size; ++i)
-		if (!strcmp(d[i].str, str))
-			return d[i].value;
-	return -1;
-}
-
-int get_index(double_dict d[], unsigned int size, const char *s)
-{
-	int i;
-
-	for (i = 0; i < size; ++i) {
-		if (!strcmp(s, d[i].str))
-			return i;
-	}
-	return -1;
-}
-
-int set_function(int arch)
-{
-	switch(arch) {
-		case CS_ARCH_ARM:
-			function = get_detail_arm;
-			break;
-		case CS_ARCH_AARCH64:
-			function = get_detail_aarch64;
-			break;
-		case CS_ARCH_MIPS:
-			function = get_detail_mips;
-			break;
-		case CS_ARCH_PPC:
-			function = get_detail_ppc;
-			break;
-		case CS_ARCH_SPARC:
-			function = get_detail_sparc;
-			break;
-		case CS_ARCH_SYSZ:
-			function = get_detail_sysz;
-			break;
-		case CS_ARCH_X86:
-			function = get_detail_x86;
-			break;
-		case CS_ARCH_XCORE:
-			function = get_detail_xcore;
-			break;
-		case CS_ARCH_M68K:
-			function = get_detail_m68k;
-			break;
-		case CS_ARCH_M680X:
-			function = get_detail_m680x;
-			break;
-		case CS_ARCH_EVM:
-			function = get_detail_evm;
-			break;
-		case CS_ARCH_MOS65XX:
-			function = get_detail_mos65xx;
-			break;
-		case CS_ARCH_TMS320C64X:
-			function = get_detail_tms320c64x;
-			break;
-		case CS_ARCH_BPF:
-			function = get_detail_bpf;
-			break;
-		case CS_ARCH_RISCV:
-			function = get_detail_riscv;
-			break;
-		case CS_ARCH_TRICORE:
-			function = get_detail_tricore;
-			break;
-		case CS_ARCH_ALPHA:
-			function = get_detail_alpha;
-			break;
-		case CS_ARCH_HPPA:
-			function = get_detail_hppa;
-			break;
-		case CS_ARCH_LOONGARCH:
-			function = get_detail_loongarch;
-			break;
-		default:
-			return -1;
-	}
-	return 0;
-}
-
-void test_single_issue(csh *handle, cs_mode mode, char *line, int detail)
-{
-	char **list_part, **list_byte, **list_part_issue_result;
-	int size_part, size_byte, size_part_issue_result;
-	int i, count, j;
-	unsigned char *code;
-	cs_insn *insn;
-	char *cs_result, *tmp, *p;
-	char **offset_opcode;
-	int size_offset_opcode;
-	unsigned long offset;
-
-	cs_result = (char *)malloc(sizeof(char));
-	cs_result[0] = '\0';
-
-	list_part = split(line, " == ", &size_part);
-
-	offset_opcode = split(list_part[0], ": ", &size_offset_opcode);
-	if (size_offset_opcode > 1) {
-		offset = (unsigned int)strtol(offset_opcode[0], NULL, 16);
-		list_byte = split(offset_opcode[1], ",", &size_byte);
-	} else {
-		offset = 0;
-		list_byte = split(offset_opcode[0], ",", &size_byte);
-	}
-	free_strs(offset_opcode, size_offset_opcode);
-
-	code = (unsigned char *)malloc(sizeof(char) * size_byte);
-	for (i = 0; i < size_byte; ++i) {
-		code[i] = (unsigned char)strtol(list_byte[i], NULL, 16);
-	}
-
-	count = cs_disasm(*handle, code, size_byte, offset, 0, &insn);
-	free_strs(list_byte, size_byte);
-	free(code);
-	for (i = 0; i < count; ++i) {
-		tmp = (char *)malloc(strlen(insn[i].mnemonic) + strlen(insn[i].op_str) + 100);
-		strcpy(tmp, insn[i].mnemonic);
-		if (strlen(insn[i].op_str) > 0) {
-			tmp[strlen(insn[i].mnemonic)] = ' ';
-			strcpy(tmp + strlen(insn[i].mnemonic) + 1, insn[i].op_str);
-		}
-		add_str(&cs_result, "%s", tmp);
-		free(tmp);
-	}
-
-	if (detail == 1) {
-		tmp = (*function)(handle, mode, insn);
-		add_str(&cs_result, "%s", tmp);
-		free(tmp);
-
-		if (insn->detail->groups_count) {
-			add_str(&cs_result, " ; Groups: ");
-			for (j = 0; j < insn->detail->groups_count; j++) {
-				add_str(&cs_result, "%s ", cs_group_name(*handle, insn->detail->groups[j]));
-			}
-		}
-	}
-
-	trim_str(cs_result);
-	add_str(&cs_result, " ;");
-	//	list_part_cs_result = split(cs_result, " ; ", &size_part_cs_result);
-	for (p = list_part[1]; *p; ++p) if (*p == '\t') *p = ' ';
-	list_part_issue_result = split(list_part[1], " ; ", &size_part_issue_result);
-
-	for (i = 0; i < size_part_issue_result; ++i) {
-		trim_str(list_part_issue_result[i]);
-		char *tmptmp = (char *)malloc(sizeof(char));
-		tmptmp[0] = '\0';
-		add_str(&tmptmp, "%s", list_part_issue_result[i]);
-		add_str(&tmptmp, " ;");
-
-		if ((strstr(cs_result, tmptmp)) == NULL) {
-			fprintf(stderr, "[  ERROR   ] --- %s --- \"%s\" not in \"%s\"\n", list_part[0], list_part_issue_result[i], cs_result);
-			cs_free(insn, count);
-			free_strs(list_part, size_part);
-			free(cs_result);
-			//	free_strs(list_part_cs_result, size_part_cs_result);
-			free_strs(list_part_issue_result, size_part_issue_result);
-			free(tmptmp);
-			_fail(__FILE__, __LINE__);
-		}
-		free(tmptmp);
-	}
-
-	cs_free(insn, count);
-	free_strs(list_part, size_part);
-	free(cs_result);
-	//	free_strs(list_part_cs_result, size_part_cs_result);
-	free_strs(list_part_issue_result, size_part_issue_result);
-}
diff --git a/suite/cstest/src/cstest.c b/suite/cstest/src/cstest.c
new file mode 100644
index 000000000..6c25f5db9
--- /dev/null
+++ b/suite/cstest/src/cstest.c
@@ -0,0 +1,111 @@
+// Copyright © 2024 Rot127 <unisono@quyllur.org>
+// SPDX-License-Identifier: BSD-3
+
+#define _XOPEN_SOURCE 500
+#include "../../../utils.h"
+#include "test_run.h"
+#include <capstone/platform.h>
+#include <ftw.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <time.h>
+
+// Pointer to the file list table
+// Must be a thread local, because we cannot pass arguments to `nftw`.
+// So the found test files can only be saved, very annoyingly,
+// to a global/thread-local mutable variables.
+char ***test_files = NULL;
+uint32_t file_count = 0;
+
+static void help(const char *self)
+{
+	fprintf(stderr, "%s <test-file-dir>/<test-file.yml> ...\n", self);
+}
+
+static int handle_ftree_entry(const char *fpath, const struct stat *sb,
+			      int typeflag, struct FTW *ftwbuf)
+{
+	if (typeflag != FTW_F) {
+		return 0;
+	}
+	const char *suffix = strstr(fpath, ".yaml");
+	if (!suffix || suffix - fpath != strlen(fpath) - 5) {
+		// Misses the .yaml suffix.
+		return 0;
+	}
+
+	file_count++;
+	*test_files = cs_mem_realloc(*test_files, sizeof(char *) * file_count);
+	if (!*test_files) {
+		fprintf(stderr, "[!] realloc failed\n");
+		return -1;
+	}
+	test_files[0][file_count - 1] = cs_strdup(fpath);
+	return 0;
+}
+
+/// Parses the test file paths from the @argv array.
+static void get_tfiles(int argc, const char **argv)
+{
+	for (size_t i = 1; i < argc; ++i) {
+		if (nftw(argv[i], handle_ftree_entry, 20,
+			 FTW_DEPTH | FTW_PHYS) == -1) {
+			fprintf(stderr, "[!] nftw failed.\n");
+			return;
+		}
+	}
+}
+
+void print_test_run_stats(const TestRunStats *stats)
+{
+	printf("\n-----------------------------------------\n");
+	printf("Test run statistics\n\n");
+	printf("Valid files: %" PRId32 "\n", stats->valid_test_files);
+	printf("Invalid files: %" PRId32 "\n", stats->invalid_files);
+	printf("Errors: %" PRId32 "\n\n", stats->errors);
+	printf("Test cases:\n");
+	printf("\tTotal: %" PRId32 "\n", stats->tc_total);
+	printf("\tSuccessful: %" PRId32 "\n", stats->successful);
+	printf("\tSkipped: %" PRId32 "\n", stats->skipped);
+	printf("\tFailed: %" PRId32 "\n", stats->failed);
+	printf("-----------------------------------------\n");
+	printf("\n");
+}
+
+int main(int argc, const char **argv)
+{
+	if (argc < 2 || strcmp(argv[1], "-h") == 0 ||
+	    strcmp(argv[1], "--help") == 0) {
+		help(argv[0]);
+		exit(EXIT_FAILURE);
+	}
+	test_files = malloc(sizeof(char **));
+	*test_files = NULL;
+
+	get_tfiles(argc, argv);
+	if (!*test_files || file_count == 0) {
+		fprintf(stderr, "Arguments are invalid. No files found.\n");
+		exit(EXIT_FAILURE);
+	}
+
+	printf("Test files found: %" PRId32 "\n", file_count);
+	TestRunStats stats = { 0 };
+	TestRunResult res = cstest_run_tests(*test_files, file_count, &stats);
+
+	print_test_run_stats(&stats);
+	if (res == TEST_RUN_ERROR) {
+		fprintf(stderr, "[!] An error occured.\n");
+		exit(EXIT_FAILURE);
+	} else if (res == TEST_RUN_SUCCESS) {
+		printf("[o] All tests succeeded.\n");
+		exit(EXIT_SUCCESS);
+	} else if (res == TEST_RUN_FAILURE) {
+		printf("\nNOTE: Asserts have the actual data on the left side: 'actual' != 'expected'\n\n");
+		fprintf(stderr, "[!] Some tests failed.\n");
+		exit(EXIT_FAILURE);
+	}
+
+	fprintf(stderr, "[!] Unhandled Test Run result\n");
+	exit(EXIT_FAILURE);
+}
diff --git a/suite/cstest/src/evm_detail.c b/suite/cstest/src/evm_detail.c
deleted file mode 100644
index 635d309e3..000000000
--- a/suite/cstest/src/evm_detail.c
+++ /dev/null
@@ -1,30 +0,0 @@
-/* Capstone testing regression */
-/* By Do Minh Tuan <tuanit96@gmail.com>, 02-2019 */
-
-
-#include "factory.h"
-
-char *get_detail_evm(csh *handle, cs_mode mode, cs_insn *ins)
-{
-	cs_evm *evm;
-	char *result;
-
-	result = (char *)malloc(sizeof(char));
-	result[0] = '\0';
-
-	if (ins->detail == NULL)
-		return result;
-
-	evm = &(ins->detail->evm);
-
-	if (evm->pop)
-		add_str(&result, " ; Pop: %u", evm->pop);
-
-	if (evm->push)
-		add_str(&result, " ; Push: %u", evm->push);
-
-	if (evm->fee)
-		add_str(&result, " ; Gas fee: %u", evm->fee);
-
-	return result;
-}
diff --git a/suite/cstest/src/helper.c b/suite/cstest/src/helper.c
index 6c3080e7f..f3eccd550 100644
--- a/suite/cstest/src/helper.c
+++ b/suite/cstest/src/helper.c
@@ -1,88 +1,20 @@
 /* Capstone testing regression */
 /* By Do Minh Tuan <tuanit96@gmail.com>, 02-2019 */
 
-
+#include <assert.h>
+#include <stdbool.h>
+#include <stdarg.h>
+#include <stdint.h>
+#include <capstone/platform.h>
+#include <stddef.h>
+#include <string.h>
+#include <stdlib.h>
+#include <stdio.h>
+#include <ctype.h>
+#include <setjmp.h>
+#include "cmocka.h"
 #include "helper.h"
 
-char **split(const char *str, const char *delim, int *size)
-{
-	char **result = NULL;
-	char *token = NULL;
-	const char *src = str;
-	int cnt = 0;
-
-	while ((token = strstr(src, delim)) != NULL) {
-		result = (char **)realloc(result, sizeof(char *) * (cnt + 1));
-		result[cnt] = (char *)calloc(1, sizeof(char) * (int)(token - src + 10));
-		memcpy(result[cnt], src, token - src);
-		result[cnt][token - src] = '\0';
-		src = token + strlen(delim);
-		cnt ++;
-	}
-
-	if (strlen(src) > 0) {
-		result = (char **)realloc(result, sizeof(char *) * (cnt + 1));
-		result[cnt] = strdup(src);
-		cnt ++;
-	}
-
-	*size = cnt;
-	return result;
-}
-
-void print_strs(char **list_str, int size)
-{
-	int i;
-
-	printf("[+] Debug %d strings:\n", size);
-	for (i = 0; i < size; ++i)
-		printf("String %d'th: %s\n", i+1, list_str[i]);
-}
-
-void free_strs(char **list_str, int size)
-{
-	int i;
-	for (i = 0; i < size; ++i)
-		free(list_str[i]);
-
-	free(list_str);
-}
-
-const char *get_filename_ext(const char *filename)
-{
-	const char *dot;
-
-	dot = strrchr(filename, '.');
-	if (!dot || dot == filename)
-		return "";
-
-	return dot + 1;
-}
-
-char *readfile(const char *filename)
-{
-	char *result;
-	FILE *fp;
-	int size;
-
-	fp = fopen(filename, "r");
-	if (fp == NULL) {
-		puts("No such file");
-		exit(-1);
-	}
-
-	fseek(fp, 0, SEEK_END);
-	size = ftell(fp);
-	rewind(fp);
-
-	result = (char *)calloc(1, sizeof(char) * size + 1);
-	fread(result, size, 1, fp);
-	result[size] = '\0';
-
-	fclose(fp);
-	return result;
-}
-
 void add_str(char **src, const char *format, ...)
 {
 	char *tmp;
@@ -94,7 +26,7 @@ void add_str(char **src, const char *format, ...)
 	vsprintf(tmp, format, args);
 	va_end(args);
 
-	len1 = strlen(*src);	
+	len1 = strlen(*src);
 	len2 = strlen(tmp);
 
 	*src = (char *)realloc(*src, sizeof(char) * (len1 + len2 + 10));
@@ -102,7 +34,7 @@ void add_str(char **src, const char *format, ...)
 	free(tmp);
 }
 
-void replace_hex(char *src)
+void replace_hex(char *src, size_t src_len)
 {
 	char *tmp, *result, *found, *origin, *orig_found;
 	int valid;
@@ -123,24 +55,29 @@ void replace_hex(char *src)
 		tmp_tmp = strndup(tmp, orig_found - tmp);
 		while (*found != '\0' && isxdigit(*found)) {
 			valid = 1;
-			if (*found >= 'a' && *found <='f')
-				value = value*0x10 + (*found - 'a' + 10);
+			if (*found >= 'a' && *found <= 'f')
+				value = value * 0x10 + (*found - 'a' + 10);
+			else if (*found >= 'A' && *found <= 'F')
+				value = value * 0x10 + (*found - 'A' + 10);
 			else
-				value = value*0x10 + (*found - '0');
+				value = value * 0x10 + (*found - '0');
 			found++;
 		}
 
-		if (valid == 1) add_str(&result, "%s%llu", tmp_tmp, value);
-		else add_str(&result, "%s0x", tmp_tmp);
+		if (valid == 1)
+			add_str(&result, "%s%llu", tmp_tmp, value);
+		else
+			add_str(&result, "%s0x", tmp_tmp);
 		tmp = found;
 		free(tmp_tmp);
 	}
 
 	add_str(&result, "%s", tmp);
-	if (strlen(result) >= MAXMEM) {
-		fprintf(stderr, "[  Error   ] --- Buffer Overflow in replace_hex()\n");
+	if (strlen(result) >= src_len) {
 		free(result);
 		free(origin);
+		fprintf(stderr,
+			"[  Error   ] --- Buffer Overflow in replace_hex()\n");
 		_fail(__FILE__, __LINE__);
 	}
 
@@ -149,7 +86,7 @@ void replace_hex(char *src)
 	free(origin);
 }
 
-void replace_negative(char *src, int mode)
+void replace_negative(char *src, size_t src_len, size_t arch_bits)
 {
 	char *tmp, *result, *found, *origin, *orig_found;
 	int cnt, valid;
@@ -165,9 +102,9 @@ void replace_negative(char *src, int mode)
 
 	while ((found = strstr(tmp, "-")) != NULL) {
 		orig_found = found;
-		found ++;
+		found++;
 		valid = 0;
-		
+
 		value = strdup("-");
 		cnt = 2;
 
@@ -176,25 +113,26 @@ void replace_negative(char *src, int mode)
 			value = (char *)realloc(value, cnt + 1);
 			value[cnt - 1] = *found;
 			value[cnt] = '\0';
-			cnt ++;
+			cnt++;
 			found++;
 		}
 
 		tmp_tmp = strndup(tmp, orig_found - tmp);
 		if (valid == 1) {
 			*orig_found = '\0';
-			if (mode == X86_16) {
+			if (arch_bits == 16) {
 				sscanf(value, "%hu", &tmp_short);
 				add_str(&result, "%s%hu", tmp_tmp, tmp_short);
-			} else if (mode == X86_32) {
+			} else if (arch_bits == 32) {
 				sscanf(value, "%u", &tmp_int);
 				add_str(&result, "%s%u", tmp_tmp, tmp_int);
-			} else if (mode == X86_64) {
+			} else if (arch_bits == 64) {
 				sscanf(value, "%lu", &tmp_long);
 				add_str(&result, "%s%lu", tmp_tmp, tmp_long);
 			}
-		}
-		else add_str(&result, "%s-", tmp_tmp);
+
+		} else
+			add_str(&result, "%s-", tmp_tmp);
 
 		tmp = found;
 		free(value);
@@ -202,8 +140,9 @@ void replace_negative(char *src, int mode)
 	}
 
 	add_str(&result, "%s", tmp);
-	if (strlen(result) >= MAXMEM) {
-		fprintf(stderr, "[  Error   ] --- Buffer Overflow in replace_negative()\n");
+	if (strlen(result) >= src_len) {
+		fprintf(stderr,
+			"[  Error   ] --- Buffer Overflow in replace_negative()\n");
 		free(result);
 		free(origin);
 		_fail(__FILE__, __LINE__);
@@ -214,45 +153,18 @@ void replace_negative(char *src, int mode)
 	free(origin);
 }
 
-void listdir(const char *name, char ***files, int *num_files)
-{
-	DIR *dir;
-	struct dirent *entry;
-	int cnt;
-
-	if (!(dir = opendir(name)))
-		return;
-
-	while ((entry = readdir(dir)) != NULL) {
-		if (entry->d_type == DT_DIR) {
-			char path[1024];
-			if (strcmp(entry->d_name, ".") == 0 || strcmp(entry->d_name, "..") == 0)
-				continue;
-			snprintf(path, sizeof(path), "%s/%s", name, entry->d_name);
-			listdir(path, files, num_files);
-		} else {
-			cnt = *num_files;
-			*files = (char **)realloc(*files, sizeof(char *) * (cnt + 1));
-			(*files)[cnt] = (char *)malloc(sizeof(char) * ( strlen(name) + 1 + strlen(entry->d_name) + 10));
-			sprintf((*files)[cnt], "%s/%s", name, entry->d_name);
-			cnt ++;
-			*num_files = cnt;
-		}
-	}
-
-	closedir(dir);
-}
-
 void trim_str(char *str)
 {
-	char tmp[MAXMEM];
+	char tmp[MAX_ASM_TXT_MEM];
 	int start, end, j, i;
 
 	start = 0;
 	end = strlen(str) - 1;
 	j = 0;
-	while (start < strlen(str) && isspace(str[start])) start++;
-	while (end >= 0 && isspace(str[end])) end--;
+	while (start < strlen(str) && isspace(str[start]))
+		start++;
+	while (end >= 0 && isspace(str[end]))
+		end--;
 
 	for (i = start; i <= end; ++i)
 		tmp[j++] = str[i];
@@ -263,27 +175,26 @@ void trim_str(char *str)
 	return;
 }
 
-void replace_tabs(char *str)
+/// Normalizes the usage of spaces in the given string.
+/// It does:
+/// - Replaces '\t' with '\s'
+/// - Replace '\s\s+' with a single space.
+void norm_spaces(char *str)
 {
-	char tmp[MAXMEM];
-	bool space_char = false;
-
-	int j = 0;
-	for (int i = 0; i <= strlen(str); ++i) {
-		if (str[i] == ' ' || str[i] == '\t') {
-			space_char = true;
-			continue;
-		}
-		if (space_char) {
-			space_char = false;
-			tmp[j++] = ' ';
-		}
-
-		tmp[j++] = str[i];
+	assert(str);
+	char *space_ptr = NULL;
+	while ((space_ptr = strstr(str, "\t")) != NULL) {
+		*space_ptr = ' ';
+	}
+	while ((space_ptr = strstr(str, "  ")) != NULL) {
+		memmove(space_ptr, space_ptr + 1, strlen(space_ptr));
 	}
-
-	tmp[j] = '\0';
-	strcpy(str, tmp);
-
 	return;
 }
+
+void str_to_lower(char *str)
+{
+	assert(str);
+	for (size_t i = 0; i < strlen(str); ++i)
+		str[i] = tolower(str[i]);
+}
diff --git a/suite/cstest/src/hppa_detail.c b/suite/cstest/src/hppa_detail.c
deleted file mode 100644
index 213a73c4f..000000000
--- a/suite/cstest/src/hppa_detail.c
+++ /dev/null
@@ -1,96 +0,0 @@
-/* Capstone testing regression */
-/* By Dmitry Sibirtsev <sibirtsevdl@gmail.com>, 2023 */
-
-#include "factory.h"
-
-char *get_detail_hppa(csh *p_handle, cs_mode mode, cs_insn *ins)
-{
-	cs_hppa *hppa;
-	int i;
-	cs_regs regs_read, regs_write;
-	uint8_t regs_read_count, regs_write_count;
-
-	char *result;
-	result = (char *)malloc(sizeof(char));
-	result[0] = '\0';
-
-	if (ins->detail == NULL)
-		return result;
-
-	csh handle = *p_handle;
-
-	hppa = &(ins->detail->hppa);
-
-	if (hppa->op_count)
-		add_str(&result, "\top_count: %u\n", hppa->op_count);
-
-	for (i = 0; i < hppa->op_count; i++) {
-		cs_hppa_op *op = &(hppa->operands[i]);
-		switch ((int)op->type) {
-		default:
-			break;
-		case HPPA_OP_REG:
-			add_str(&result, "\t\toperands[%u].type: REG = %s\n", i,
-				cs_reg_name(handle, op->reg));
-			break;
-		case HPPA_OP_IMM:
-			add_str(&result, "\t\toperands[%u].type: IMM = 0x%x\n",
-				i, op->imm);
-			break;
-		case HPPA_OP_IDX_REG:
-			add_str(&result,
-				"\t\toperands[%u].type: IDX_REG = %s\n", i,
-				cs_reg_name(handle, op->reg));
-			break;
-		case HPPA_OP_DISP:
-			add_str(&result, "\t\toperands[%u].type: DISP = 0x%x\n",
-				i, op->imm);
-			break;
-		case HPPA_OP_MEM:
-			add_str(&result, "\t\toperands[%u].type:  MEM\n", i);
-			if (op->mem.space != HPPA_REG_INVALID) {
-				add_str(&result,
-					"\t\t\toperands[%u].mem.space: REG = %s\n",
-					i, cs_reg_name(handle, op->mem.space));
-			}
-			add_str(&result,
-				"\t\t\toperands[%u].mem.base: REG = %s\n", i,
-				cs_reg_name(handle, op->mem.base));
-			break;
-		case HPPA_OP_TARGET:
-			add_str(&result, "\t\toperands[%u].type: ", i);
-			if (op->imm >= 0x8000000000000000)
-				add_str(&result, "TARGET = -0x%lx\n", -op->imm);
-			else
-				add_str(&result, "TARGET = 0x%lx\n", op->imm);
-			break;
-		}
-
-		// Print out all registers accessed by this instruction (either implicit or
-		// explicit)
-		if (!cs_regs_access(handle, ins, regs_read, &regs_read_count,
-				    regs_write, &regs_write_count)) {
-			if (regs_read_count) {
-				add_str(&result, "\tRegisters read:");
-				for (i = 0; i < regs_read_count; i++) {
-					add_str(&result, " %s",
-						cs_reg_name(handle,
-							    regs_read[i]));
-				}
-				add_str(&result, "\n");
-			}
-
-			if (regs_write_count) {
-				add_str(&result, "\tRegisters modified:");
-				for (i = 0; i < regs_write_count; i++) {
-					add_str(&result, " %s",
-						cs_reg_name(handle,
-							    regs_write[i]));
-				}
-				add_str(&result, "\n");
-			}
-		}
-	}
-
-	return result;
-}
diff --git a/suite/cstest/src/loongarch_detail.c b/suite/cstest/src/loongarch_detail.c
deleted file mode 100644
index c96d7dc87..000000000
--- a/suite/cstest/src/loongarch_detail.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/* Capstone testing regression */
-/* By Do Minh Tuan <tuanit96@gmail.com>, 02-2019 */
-/*    Jiajie Chen <c@jia.je>, 2024 */
-
-
-#include "factory.h"
-
-char *get_detail_loongarch(csh *handle, cs_mode mode, cs_insn *ins)
-{
-	cs_loongarch *loongarch;
-	int i;
-	char *result;
-
-	result = (char *)malloc(sizeof(char));
-	result[0] = '\0';
-
-	if (ins->detail == NULL)
-		return result;
-
-	loongarch = &(ins->detail->loongarch);
-	if (loongarch->op_count)
-		add_str(&result, " ; op_count: %u", loongarch->op_count);
-
-	for (i = 0; i < loongarch->op_count; i++) {
-		cs_loongarch_op *op = &(loongarch->operands[i]);
-		switch((int)op->type) {
-			default:
-				break;
-			case LOONGARCH_OP_REG:
-				add_str(&result, " ; operands[%u].type: REG = %s", i, cs_reg_name(*handle, op->reg));
-				break;
-			case LOONGARCH_OP_IMM:
-				add_str(&result, " ; operands[%u].type: IMM = 0x%x", i, op->imm);
-				break;
-			case LOONGARCH_OP_MEM:
-				add_str(&result, " ; operands[%u].type: MEM", i);
-				if (op->mem.base != LOONGARCH_REG_INVALID)
-					add_str(&result, " ; operands[%u].mem.base: REG = %s",
-							i, cs_reg_name(*handle, op->mem.base));
-				if (op->mem.index != LOONGARCH_REG_INVALID)
-					add_str(&result, " ; operands[%u].mem.index: REG = %s",
-							i, cs_reg_name(*handle, op->mem.index));
-				if (op->mem.disp != 0)
-					add_str(&result, " ; operands[%u].mem.disp: 0x%x", i, op->mem.disp);
-				break;
-		}
-	}
-
-	return result;
-}
-
diff --git a/suite/cstest/src/m680x_detail.c b/suite/cstest/src/m680x_detail.c
deleted file mode 100644
index 62c429812..000000000
--- a/suite/cstest/src/m680x_detail.c
+++ /dev/null
@@ -1,137 +0,0 @@
-/* Capstone testing regression */
-/* By Do Minh Tuan <tuanit96@gmail.com>, 02-2019 */
-
-
-#include "factory.h"
-
-static const char *s_access[] = {
-	"UNCHANGED", "READ", "WRITE", "READ ; WRITE",
-};
-
-static void print_read_write_regs(char *result, csh *handle, cs_detail *detail)
-{
-	int i;
-
-	if (detail->regs_read_count > 0) {
-		add_str(&result, "\treading from regs: ");
-
-		for (i = 0; i < detail->regs_read_count; ++i) {
-			if (i > 0)
-				add_str(&result, ", ");
-
-			add_str(&result, "%s", cs_reg_name(*handle, detail->regs_read[i]));
-		}
-	}
-
-	if (detail->regs_write_count > 0) {
-		add_str(&result, "\twriting to regs: ");
-
-		for (i = 0; i < detail->regs_write_count; ++i) {
-			if (i > 0)
-				add_str(&result, ", ");
-
-			add_str(&result, "%s", cs_reg_name(*handle, detail->regs_write[i]));
-		}
-	}
-}
-
-char *get_detail_m680x(csh *handle, cs_mode mode, cs_insn *insn)
-{
-	cs_detail *detail = insn->detail;
-	cs_m680x *m680x = NULL;
-	int i;
-	char *result;
-
-	result = (char *)malloc(sizeof(char));
-	result[0] = '\0';
-
-	if (detail == NULL)
-		return result;
-
-	m680x = &detail->m680x;
-
-	if (m680x->op_count)
-		add_str(&result, " ; op_count: %u", m680x->op_count);
-
-	for (i = 0; i < m680x->op_count; i++) {
-		cs_m680x_op *op = &(m680x->operands[i]);
-		const char *comment;
-
-		switch ((int)op->type) {
-			default:
-				break;
-
-			case M680X_OP_REGISTER:
-				comment = "";
-
-				if ((i == 0 && m680x->flags & M680X_FIRST_OP_IN_MNEM) ||
-						(i == 1 && m680x->flags &
-						 M680X_SECOND_OP_IN_MNEM))
-					comment = " (in mnemonic)";
-
-				add_str(&result, " ; operands[%u].type: REGISTER = %s%s", i, cs_reg_name(*handle, op->reg), comment);
-				break;
-
-			case M680X_OP_CONSTANT:
-				add_str(&result, " ; operands[%u].type: CONSTANT = %u", i, op->const_val);
-				break;
-
-			case M680X_OP_IMMEDIATE:
-				add_str(&result, " ; operands[%u].type: IMMEDIATE = #%d", i, op->imm);
-				break;
-
-			case M680X_OP_DIRECT:
-				add_str(&result, " ; operands[%u].type: DIRECT = 0x%02x", i, op->direct_addr);
-				break;
-
-			case M680X_OP_EXTENDED:
-				add_str(&result, " ; operands[%u].type: EXTENDED %s = 0x%04x", i, op->ext.indirect ? "INDIRECT" : "", op->ext.address);
-				break;
-
-			case M680X_OP_RELATIVE:
-				add_str(&result, " ; operands[%u].type: RELATIVE = 0x%04x", i, op->rel.address);
-				break;
-
-			case M680X_OP_INDEXED:
-				add_str(&result, " ; operands[%u].type: INDEXED%s", i, (op->idx.flags & M680X_IDX_INDIRECT) ? " INDIRECT" : "");
-
-				if (op->idx.base_reg != M680X_REG_INVALID)
-					add_str(&result, " ; base register: %s", cs_reg_name(*handle, op->idx.base_reg));
-
-				if (op->idx.offset_reg != M680X_REG_INVALID)
-					add_str(&result, " ; offset register: %s", cs_reg_name(*handle, op->idx.offset_reg));
-
-				if ((op->idx.offset_bits != 0) &&
-						(op->idx.offset_reg == M680X_REG_INVALID) &&
-						!op->idx.inc_dec) {
-					add_str(&result, " ; offset: %d", op->idx.offset);
-
-					if (op->idx.base_reg == M680X_REG_PC)
-						add_str(&result, " ; offset address: 0x%x", op->idx.offset_addr);
-
-					add_str(&result, " ; offset bits: %u", op->idx.offset_bits);
-				}
-
-				if (op->idx.inc_dec) {
-					const char *post_pre = op->idx.flags &
-						M680X_IDX_POST_INC_DEC ? "post" : "pre";
-					const char *inc_dec = (op->idx.inc_dec > 0) ?
-						"increment" : "decrement";
-
-					add_str(&result, " ; %s %s: %d", post_pre, inc_dec, abs(op->idx.inc_dec));
-				}
-
-				break;
-		}
-
-		if (op->size != 0)
-			add_str(&result, " ; size: %u", op->size);
-
-		if (op->access != CS_AC_INVALID)
-			add_str(&result, " ; access: %s", s_access[op->access]);
-	}
-
-	print_read_write_regs(result, handle, detail);
-
-	return result;
-}
diff --git a/suite/cstest/src/m68k_detail.c b/suite/cstest/src/m68k_detail.c
deleted file mode 100644
index a3dfc7491..000000000
--- a/suite/cstest/src/m68k_detail.c
+++ /dev/null
@@ -1,116 +0,0 @@
-/* Capstone testing regression */
-/* By Do Minh Tuan <tuanit96@gmail.com>, 02-2019 */
-
-
-#include "factory.h"
-
-static const char* s_addressing_modes[] = {
-	"<invalid mode>",
-
-	"Register Direct - Data",
-	"Register Direct - Address",
-
-	"Register Indirect - Address",
-	"Register Indirect - Address with Postincrement",
-	"Register Indirect - Address with Predecrement",
-	"Register Indirect - Address with Displacement",
-
-	"Address Register Indirect With Index - 8-bit displacement",
-	"Address Register Indirect With Index - Base displacement",
-
-	"Memory indirect - Postindex",
-	"Memory indirect - Preindex",
-
-	"Program Counter Indirect - with Displacement",
-
-	"Program Counter Indirect with Index - with 8-Bit Displacement",
-	"Program Counter Indirect with Index - with Base Displacement",
-
-	"Program Counter Memory Indirect - Postindexed",
-	"Program Counter Memory Indirect - Preindexed",
-
-	"Absolute Data Addressing  - Short",
-	"Absolute Data Addressing  - Long",
-	"Immediate value",
-};
-
-static void print_read_write_regs(char *result, cs_detail* detail, csh *handle)
-{
-	int i;
-
-	for (i = 0; i < detail->regs_read_count; ++i) {
-		uint16_t reg_id = detail->regs_read[i];
-		const char* reg_name = cs_reg_name(*handle, reg_id);
-		add_str(&result, " ; reading from reg: %s", reg_name);
-	}
-
-	for (i = 0; i < detail->regs_write_count; ++i) {
-		uint16_t reg_id = detail->regs_write[i];
-		const char* reg_name = cs_reg_name(*handle, reg_id);
-		add_str(&result, " ; writing to reg:   %s", reg_name);
-	}
-}
-
-char *get_detail_m68k(csh *handle, cs_mode mode, cs_insn *ins)
-{
-	cs_m68k* m68k;
-	cs_detail* detail;
-	int i;
-	char *result;
-
-	result = (char *)malloc(sizeof(char));
-	result[0] = '\0';
-
-	if (ins->detail == NULL)
-		return result;
-
-
-	detail = ins->detail;
-	m68k = &detail->m68k;
-	if (m68k->op_count)
-		add_str(&result, " ; op_count: %u", m68k->op_count);
-
-	print_read_write_regs(result, detail, handle);
-
-	add_str(&result, " ; groups_count: %u", detail->groups_count);
-
-	for (i = 0; i < m68k->op_count; i++) {
-		cs_m68k_op* op = &(m68k->operands[i]);
-
-		switch((int)op->type) {
-			default:
-				break;
-			case M68K_OP_REG:
-				add_str(&result, " ; operands[%u].type: REG = %s", i, cs_reg_name(*handle, op->reg));
-				break;
-			case M68K_OP_IMM:
-				add_str(&result, " ; operands[%u].type: IMM = 0x%x", i, (int)op->imm);
-				break;
-			case M68K_OP_MEM:
-				add_str(&result, " ; operands[%u].type: MEM", i);
-				if (op->mem.base_reg != M68K_REG_INVALID)
-					add_str(&result, " ; operands[%u].mem.base: REG = %s", i, cs_reg_name(*handle, op->mem.base_reg));
-				if (op->mem.index_reg != M68K_REG_INVALID) {
-					add_str(&result, " ; operands[%u].mem.index: REG = %s", i, cs_reg_name(*handle, op->mem.index_reg));
-					add_str(&result, " ; operands[%u].mem.index: size = %c", i, op->mem.index_size ? 'l' : 'w');
-				}
-				if (op->mem.disp != 0)
-					add_str(&result, " ; operands[%u].mem.disp: 0x%x", i, op->mem.disp);
-				if (op->mem.scale != 0)
-					add_str(&result, " ; operands[%u].mem.scale: %d", i, op->mem.scale);
-
-				add_str(&result, " ; address mode: %s", s_addressing_modes[op->address_mode]);
-				break;
-			case M68K_OP_FP_SINGLE:
-				add_str(&result, " ; operands[%u].type: FP_SINGLE", i);
-				add_str(&result, " ; operands[%u].simm: %f", i, op->simm);
-				break;
-			case M68K_OP_FP_DOUBLE:
-				add_str(&result, " ; operands[%u].type: FP_DOUBLE", i);
-				add_str(&result, " ; operands[%u].dimm: %lf", i, op->dimm);
-				break;
-		}
-	}
-
-	return result;
-}
diff --git a/suite/cstest/src/main.c b/suite/cstest/src/main.c
deleted file mode 100644
index 5da0e4998..000000000
--- a/suite/cstest/src/main.c
+++ /dev/null
@@ -1,493 +0,0 @@
-/* Capstone testing regression */
-/* By Do Minh Tuan <tuanit96@gmail.com>, 02-2019 */
-
-
-#include "helper.h"
-#include "capstone_test.h"
-#include <unistd.h>
-
-#define ARR_SIZE(a) (sizeof(a)/sizeof(a[0]))
-
-static single_dict arches[] = {
-	{"CS_ARCH_ARM", CS_ARCH_ARM},
-	{"CS_ARCH_AARCH64", CS_ARCH_AARCH64},
-	{"CS_ARCH_MIPS", CS_ARCH_MIPS},
-	{"CS_ARCH_PPC", CS_ARCH_PPC},
-	{"CS_ARCH_SPARC", CS_ARCH_SPARC},
-	{"CS_ARCH_SYSZ", CS_ARCH_SYSZ},
-	{"CS_ARCH_X86", CS_ARCH_X86},
-	{"CS_ARCH_XCORE", CS_ARCH_XCORE},
-	{"CS_ARCH_M68K", CS_ARCH_M68K},
-	{"CS_ARCH_BPF", CS_ARCH_BPF},
-	{"CS_ARCH_RISCV", CS_ARCH_RISCV},
-	{"CS_ARCH_TRICORE", CS_ARCH_TRICORE},
-	{"CS_ARCH_ALPHA", CS_ARCH_ALPHA},
-	{"CS_ARCH_HPPA", CS_ARCH_HPPA},
-	{"CS_ARCH_LOONGARCH", CS_ARCH_LOONGARCH},
-};
-
- static single_dict modes[] = {
-	{"CS_MODE_LITTLE_ENDIAN", CS_MODE_LITTLE_ENDIAN},
-	{"CS_MODE_ARM", CS_MODE_ARM},
-	{"CS_MODE_16", CS_MODE_16},
-	{"CS_MODE_32", CS_MODE_32},
-	{"CS_MODE_64", CS_MODE_64},
-	{"CS_MODE_THUMB", CS_MODE_THUMB},
-	{"CS_MODE_MCLASS", CS_MODE_MCLASS},
-	{"CS_MODE_V8", CS_MODE_V8},
-	{"CS_MODE_MICRO", CS_MODE_MICRO},
-	{"CS_MODE_MIPS3", CS_MODE_MIPS3},
-	{"CS_MODE_MIPS32R6", CS_MODE_MIPS32R6},
-	{"CS_MODE_MIPS2", CS_MODE_MIPS2},
-	{"CS_MODE_V9", CS_MODE_V9},
-	{"CS_MODE_QPX", CS_MODE_QPX},
-	{"CS_MODE_PS", CS_MODE_PS},
-	{"CS_MODE_M68K_000", CS_MODE_M68K_000},
-	{"CS_MODE_M68K_010", CS_MODE_M68K_010},
-	{"CS_MODE_M68K_020", CS_MODE_M68K_020},
-	{"CS_MODE_M68K_030", CS_MODE_M68K_030},
-	{"CS_MODE_M68K_040", CS_MODE_M68K_040},
-	{"CS_MODE_M68K_060", CS_MODE_M68K_060},
-	{"CS_MODE_BIG_ENDIAN", CS_MODE_BIG_ENDIAN},
-	{"CS_MODE_MIPS32", CS_MODE_MIPS32},
-	{"CS_MODE_MIPS64", CS_MODE_MIPS64},
-	{"CS_MODE_M680X_6301", CS_MODE_M680X_6301},
-	{"CS_MODE_M680X_6309", CS_MODE_M680X_6309},
-	{"CS_MODE_M680X_6800", CS_MODE_M680X_6800},
-	{"CS_MODE_M680X_6801", CS_MODE_M680X_6801},
-	{"CS_MODE_M680X_6805", CS_MODE_M680X_6805},
-	{"CS_MODE_M680X_6808", CS_MODE_M680X_6808},
-	{"CS_MODE_M680X_6809", CS_MODE_M680X_6809},
-	{"CS_MODE_M680X_6811", CS_MODE_M680X_6811},
-	{"CS_MODE_M680X_CPU12", CS_MODE_M680X_CPU12},
-	{"CS_MODE_M680X_HCS08", CS_MODE_M680X_HCS08},
-	{"CS_MODE_BPF_CLASSIC", CS_MODE_BPF_CLASSIC},
-	{"CS_MODE_BPF_EXTENDED", CS_MODE_BPF_EXTENDED},
-	{"CS_MODE_RISCV32", CS_MODE_RISCV32},
-	{"CS_MODE_RISCV64", CS_MODE_RISCV64},
-	{"CS_MODE_RISCVC", CS_MODE_RISCVC},
-	{"CS_MODE_TRICORE_110", CS_MODE_TRICORE_110},
-	{"CS_MODE_TRICORE_120", CS_MODE_TRICORE_120},
-	{"CS_MODE_TRICORE_130", CS_MODE_TRICORE_130},
-	{"CS_MODE_TRICORE_131", CS_MODE_TRICORE_131},
-	{"CS_MODE_TRICORE_160", CS_MODE_TRICORE_160},
-	{"CS_MODE_TRICORE_161", CS_MODE_TRICORE_161},
-	{"CS_MODE_TRICORE_162", CS_MODE_TRICORE_162},
-	{"CS_MODE_HPPA_20", CS_MODE_HPPA_20},
-	{"CS_MODE_HPPA_20W", CS_MODE_HPPA_20W},
-	{"CS_MODE_HPPA_11", CS_MODE_HPPA_11},
-	{"CS_MODE_LOONGARCH32", CS_MODE_LOONGARCH32},
-	{"CS_MODE_LOONGARCH64", CS_MODE_LOONGARCH64},
-};
-
- static double_dict options[] = {
-	{"CS_OPT_DETAIL", CS_OPT_DETAIL, CS_OPT_ON},
-	{"CS_OPT_SKIPDATA", CS_OPT_SKIPDATA, CS_OPT_ON},
-	{"CS_OPT_SYNTAX_DEFAULT", CS_OPT_SYNTAX, CS_OPT_SYNTAX_DEFAULT},
-	{"CS_OPT_SYNTAX_INTEL", CS_OPT_SYNTAX, CS_OPT_SYNTAX_INTEL},
-	{"CS_OPT_SYNTAX_ATT", CS_OPT_SYNTAX, CS_OPT_SYNTAX_ATT},
-	{"CS_OPT_SYNTAX_NOREGNAME", CS_OPT_SYNTAX, CS_OPT_SYNTAX_NOREGNAME},
-	{"CS_OPT_SYNTAX_MASM", CS_OPT_SYNTAX, CS_OPT_SYNTAX_MASM},
-	{"CS_OPT_BRANCH_OFFSET", CS_OPT_NO_BRANCH_OFFSET, CS_OPT_NO_BRANCH_OFFSET},
-	{"CS_MODE_LITTLE_ENDIAN", CS_OPT_MODE, CS_MODE_LITTLE_ENDIAN},
-	{"CS_MODE_ARM", CS_OPT_MODE, CS_MODE_ARM},
-	{"CS_MODE_16", CS_OPT_MODE, CS_MODE_16},
-	{"CS_MODE_32", CS_OPT_MODE, CS_MODE_32},
-	{"CS_MODE_64", CS_OPT_MODE, CS_MODE_64},
-	{"CS_MODE_THUMB", CS_OPT_MODE, CS_MODE_THUMB},
-	{"CS_MODE_MCLASS", CS_OPT_MODE, CS_MODE_MCLASS},
-	{"CS_MODE_V8", CS_OPT_MODE, CS_MODE_V8},
-	{"CS_MODE_MICRO", CS_OPT_MODE, CS_MODE_MICRO},
-	{"CS_MODE_MIPS3", CS_OPT_MODE, CS_MODE_MIPS3},
-	{"CS_MODE_MIPS32R6", CS_OPT_MODE, CS_MODE_MIPS32R6},
-	{"CS_MODE_MIPS2", CS_OPT_MODE, CS_MODE_MIPS2},
-	{"CS_MODE_V9", CS_OPT_MODE, CS_MODE_V9},
-	{"CS_MODE_QPX", CS_OPT_MODE, CS_MODE_QPX},
-	{"CS_MODE_PS", CS_OPT_MODE, CS_MODE_PS},
-	{"CS_MODE_BOOKE", CS_OPT_MODE, CS_MODE_BOOKE},
-	{"CS_MODE_M68K_000", CS_OPT_MODE, CS_MODE_M68K_000},
-	{"CS_MODE_M68K_010", CS_OPT_MODE, CS_MODE_M68K_010},
-	{"CS_MODE_M68K_020", CS_OPT_MODE, CS_MODE_M68K_020},
-	{"CS_MODE_M68K_030", CS_OPT_MODE, CS_MODE_M68K_030},
-	{"CS_MODE_M68K_040", CS_OPT_MODE, CS_MODE_M68K_040},
-	{"CS_MODE_M68K_060", CS_OPT_MODE, CS_MODE_M68K_060},
-	{"CS_MODE_BIG_ENDIAN", CS_OPT_MODE, CS_MODE_BIG_ENDIAN},
-	{"CS_MODE_MIPS32", CS_OPT_MODE, CS_MODE_MIPS32},
-	{"CS_MODE_MIPS64", CS_OPT_MODE, CS_MODE_MIPS64},
-	{"CS_MODE_M680X_6301", CS_OPT_MODE, CS_MODE_M680X_6301},
-	{"CS_MODE_M680X_6309", CS_OPT_MODE, CS_MODE_M680X_6309},
-	{"CS_MODE_M680X_6800", CS_OPT_MODE, CS_MODE_M680X_6800},
-	{"CS_MODE_M680X_6801", CS_OPT_MODE, CS_MODE_M680X_6801},
-	{"CS_MODE_M680X_6805", CS_OPT_MODE, CS_MODE_M680X_6805},
-	{"CS_MODE_M680X_6808", CS_OPT_MODE, CS_MODE_M680X_6808},
-	{"CS_MODE_M680X_6809", CS_OPT_MODE, CS_MODE_M680X_6809},
-	{"CS_MODE_M680X_6811", CS_OPT_MODE, CS_MODE_M680X_6811},
-	{"CS_MODE_M680X_CPU12", CS_OPT_MODE, CS_MODE_M680X_CPU12},
-	{"CS_MODE_M680X_HCS08", CS_OPT_MODE, CS_MODE_M680X_HCS08},
-	{"CS_MODE_RISCV32", CS_OPT_MODE, CS_MODE_RISCV32},
-	{"CS_MODE_RISCV64", CS_OPT_MODE, CS_MODE_RISCV64},
-	{"CS_MODE_TRICORE_110", CS_OPT_MODE, CS_MODE_TRICORE_110},
-	{"CS_MODE_TRICORE_120", CS_OPT_MODE, CS_MODE_TRICORE_120},
-	{"CS_MODE_TRICORE_130", CS_OPT_MODE, CS_MODE_TRICORE_130},
-	{"CS_MODE_TRICORE_131", CS_OPT_MODE, CS_MODE_TRICORE_131},
-	{"CS_MODE_TRICORE_160", CS_OPT_MODE, CS_MODE_TRICORE_160},
-	{"CS_MODE_TRICORE_161", CS_OPT_MODE, CS_MODE_TRICORE_161},
-	{"CS_MODE_TRICORE_162", CS_OPT_MODE, CS_MODE_TRICORE_162},
-	{"CS_OPT_UNSIGNED", CS_OPT_UNSIGNED, CS_OPT_ON},
-	{"CS_MODE_HPPA_20", CS_OPT_MODE, CS_MODE_HPPA_20},
-	{"CS_MODE_HPPA_20W", CS_OPT_MODE, CS_MODE_HPPA_20W},
-	{"CS_MODE_HPPA_11", CS_OPT_MODE, CS_MODE_HPPA_11},
-	{"CS_MODE_LOONGARCH32", CS_OPT_MODE, CS_MODE_LOONGARCH32},
-	{"CS_MODE_LOONGARCH64", CS_OPT_MODE, CS_MODE_LOONGARCH64},
-};
-
-static int counter;
-static char **list_lines;
-static int failed_setup;
-static int size_lines;
-static cs_mode issue_mode;
-static int getDetail;
-static int mc_mode;
-static int e_flag;
-
-static int setup_state(void **state) {
-	csh *handle;
-	char **list_params;	
-	int size_params;
-	int arch, mode;
-	int i, tmp_counter;
-
-	if (failed_setup) {
-		fprintf(stderr, "[  ERROR   ] --- Invalid file to setup\n");
-		return -1;
-	}
-
-	tmp_counter = 0;
-	while (tmp_counter < size_lines && list_lines[tmp_counter][0] != '#')
-		tmp_counter++;
-
-	list_params = split(list_lines[tmp_counter] + 2, ", ", &size_params);
-	if (size_params != 3) {
-		fprintf(stderr, "[  ERROR   ] --- Invalid options ( arch, mode, option )\n");
-		failed_setup = 1;
-		return -1;
-	}
-
-	arch = get_value(arches, ARR_SIZE(arches), list_params[0]);
-	if (arch == -1) {
-		fprintf(stderr, "[  ERROR   ] --- Arch is not supported!\n");
-		failed_setup = 1;
-		return -1;
-	}
-
-	if (!strcmp(list_params[0], "CS_ARCH_AARCH64"))
-		mc_mode = 2;
-	else 
-		mc_mode = 1;
-
-	mode = 0;
-	for (i = 0; i < ARR_SIZE(modes); ++i) {
-		if (strstr(list_params[1], modes[i].str)) {
-			mode += modes[i].value;
-			switch (modes[i].value) {
-				case CS_MODE_16:
-					mc_mode = 0;
-					break;
-				case CS_MODE_64:
-					mc_mode = 2;
-					break;
-				case CS_MODE_THUMB:
-					mc_mode = 1;
-					break;
-				default:
-					break;
-			}
-		}
-	}
-
-	handle = (csh *)malloc(sizeof(csh));
-	if(cs_open(arch, mode, handle) != CS_ERR_OK) {
-		fprintf(stderr, "[  ERROR   ] --- Cannot initialize capstone\n");
-		failed_setup = 1;
-		return -1;
-	}
-
-	for (i = 0; i < ARR_SIZE(options); ++i) {
-		if (strstr(list_params[2], options[i].str)) {
-			if (cs_option(*handle, options[i].first_value, options[i].second_value) != CS_ERR_OK) {
-				fprintf(stderr, "[  ERROR   ] --- Option is not supported for this arch/mode\n");
-				failed_setup = 1;
-				return -1;
-			}
-		}
-	}
-	*state = (void *)handle;
-	free_strs(list_params, size_params);
-	return 0;
-}
-
-static int setup_MC(void **state)
-{
-	counter++;
-	if (e_flag == 0)
-		while (counter < size_lines && strncmp(list_lines[counter], "0x", 2))
-			counter++;
-	else
-		while (counter < size_lines && strncmp(list_lines[counter], "// 0x", 5))
-			counter++;
-
-	return 0;
-}
-
-static void test_MC(void **state)
-{
-	if (e_flag == 1)
-		test_single_MC((csh *)*state, mc_mode, list_lines[counter] + 3);
-	else
-		test_single_MC((csh *)*state, mc_mode, list_lines[counter]);
-}
-
-static int teardown_state(void **state)
-{
-	cs_close(*state);
-	free(*state);
-	return 0;
-}
-
-static int setup_issue(void **state)
-{
-	csh *handle;
-	char **list_params;	
-	int size_params;
-	int arch, mode;
-	int i, result;
-
-	getDetail = 0;
-	failed_setup = 0;
-
-	if (e_flag == 0)
-		while (counter < size_lines && strncmp(list_lines[counter], "!# ", 3))
-			counter++; // get issue line
-	else
-		while (counter < size_lines && strncmp(list_lines[counter], "// !# ", 6))
-			counter++;
-
-	counter++;
-	if (e_flag == 0)
-		while (counter < size_lines && strncmp(list_lines[counter], "!#", 2))
-			counter++; // get arch line
-	else
-		while (counter < size_lines && strncmp(list_lines[counter], "// !# ", 6))
-			counter++;
-
-	if (e_flag == 0)
-		list_params = split(list_lines[counter] + 3, ", ", &size_params);
-	else
-		list_params = split(list_lines[counter] + 6, ", ", &size_params);
-
-	arch = get_value(arches, ARR_SIZE(arches), list_params[0]);
-
-	if (!strcmp(list_params[0], "CS_ARCH_AARCH64"))
-		mc_mode = 2;
-	else
-		mc_mode = 1;
-
-	mode = 0;
-	for (i = 0; i < ARR_SIZE(modes); ++i) {
-		if (strstr(list_params[1], modes[i].str)) {
-			mode += modes[i].value;
-			switch (modes[i].value) {
-				case CS_MODE_16:
-					mc_mode = 0;
-					break;
-				case CS_MODE_64:
-					mc_mode = 2;
-					break;
-				case CS_MODE_THUMB:
-					mc_mode = 1;
-					break;
-				default:
-					break;
-			}
-		}
-	}
-
-	if (arch == -1) {
-		fprintf(stderr, "[  ERROR   ] --- Arch is not supported!\n");
-		failed_setup = 1;
-		return -1;
-	}
-
-	handle = (csh *)calloc(1, sizeof(csh));
-	if(cs_open(arch, mode, handle) != CS_ERR_OK) {
-		fprintf(stderr, "[  ERROR   ] --- Cannot initialize capstone\n");
-		failed_setup = 1;
-		return -1;
-	}
-	
-	for (i = 0; i < ARR_SIZE(options); ++i) {
-		if (strstr(list_params[2], options[i].str)) {
-			if (cs_option(*handle, options[i].first_value, options[i].second_value) != CS_ERR_OK) {
-				fprintf(stderr, "[  ERROR   ] --- Option is not supported for this arch/mode\n");
-				failed_setup = 1;
-				return -1;
-			}
-
-			if (i == 0) {
-				result = set_function(arch);
-				if (result == -1) {
-					fprintf(stderr, "[  ERROR   ] --- Cannot get details\n");
-					failed_setup = 1;
-					return -1;
-				}
-
-				getDetail = 1;
-			}
-		}
-	}
-
-	*state = (void *)handle;
-	issue_mode = mode;
-
-	if (e_flag == 0)
-		while (counter < size_lines && strncmp(list_lines[counter], "0x", 2))
-			counter++;
-	else
-		while (counter < size_lines && strncmp(list_lines[counter], "// 0x", 5))
-			counter++;
-
-	free_strs(list_params, size_params);
-	return 0;
-}
-
-static void test_issue(void **state)
-{
-	if (e_flag == 0)
-		test_single_issue((csh *)*state, issue_mode, list_lines[counter], getDetail);
-	else
-		test_single_issue((csh *)*state, issue_mode, list_lines[counter] + 3, getDetail);
-
-	return;
-}
-
-static int teardown_issue(void **state)
-{
-	if (e_flag == 0)
-		while (counter < size_lines && strncmp(list_lines[counter], "!# ", 3))
-			counter++;
-	else
-		while (counter < size_lines && strncmp(list_lines[counter], "// !# ", 6))
-			counter++;
-
-	cs_close(*state);
-	free(*state);
-	function = NULL;
-	return 0;
-}
-
-static void test_file(const char *filename)
-{
-	int i;
-	char *content, *tmp;
-	struct CMUnitTest *tests;
-	int number_of_tests;
-
-	printf("[+] TARGET: %s\n", filename);
-	content = readfile(filename);
-	counter = 0;
-	failed_setup = 0;
-	function = NULL;		
-
-	if (strstr(filename, "issue")) {
-		number_of_tests = 0;
-		list_lines = split(content, "\n", &size_lines);	
-		tests = NULL;
-		for (i = 0; i < size_lines; ++i) {
-			if ((!strncmp(list_lines[i], "// !# issue", 11) && e_flag == 1) || 
-					(!strncmp(list_lines[i], "!# issue", 8) && e_flag == 0)) {
-				tests = (struct CMUnitTest *)realloc(tests, sizeof(struct CMUnitTest) * (number_of_tests + 1));
-				tests[number_of_tests] = (struct CMUnitTest)cmocka_unit_test_setup_teardown(test_issue, setup_issue, teardown_issue);
-				tests[number_of_tests].name = strdup(list_lines[i]);
-				number_of_tests ++;
-			}
-		}
-
-		_cmocka_run_group_tests("Testing issues", tests, number_of_tests, NULL, NULL);
-	} else {
-		list_lines = split(content, "\n", &size_lines);
-		number_of_tests = 0;
-
-		tests = NULL;
-		for (i = 1; i < size_lines; ++i) {
-			if ((!strncmp(list_lines[i], "// 0x", 5) && e_flag == 1) || (!strncmp(list_lines[i], "0x", 2) && e_flag == 0)) {
-				tmp = (char *)malloc(sizeof(char) * 100);
-				sprintf(tmp, "Line %d", i+1);
-				tests = (struct CMUnitTest *)realloc(tests, sizeof(struct CMUnitTest) * (number_of_tests + 1));
-				tests[number_of_tests] = (struct CMUnitTest)cmocka_unit_test_setup_teardown(test_MC, setup_MC, NULL);
-				tests[number_of_tests].name = tmp;
-				number_of_tests ++;
-			}
-		}
-
-		_cmocka_run_group_tests("Testing MC", tests, number_of_tests, setup_state, teardown_state);
-	}
-
-	printf("[+] DONE: %s\n", filename);
-	printf("[!] Noted:\n[  ERROR   ] --- \"<capstone result>\" != \"<user result>\"\n");	
-	printf("\n\n");
-	free_strs(list_lines, size_lines);
-	for (int k = 0; tests && k < number_of_tests; k++) {
-		free((char *)tests[k].name);
-	}
-	free(tests);
-	free(content);
-}
-
-static void test_folder(const char *folder)
-{
-	char **files;
-	int num_files, i;
-
-	files = NULL;
-	num_files = 0;
-	listdir(folder, &files, &num_files);
-	for (i = 0; i < num_files; ++i) {
-		if (strcmp("cs", get_filename_ext(files[i])))
-			continue;
-		test_file(files[i]);
-	}
-}
-
-int main(int argc, char *argv[])
-{
-	int opt, flag;
-
-	flag = 0;
-	e_flag = 0;
-
-	while ((opt = getopt(argc, argv, "ef:d:")) > 0) {
-		switch (opt) {
-			case 'f':
-				test_file(optarg);
-				flag = 1;
-				break;
-			case 'd':
-				test_folder(optarg);
-				flag = 1;
-				break;
-			case 'e':
-				e_flag = 1;
-				break;
-			default:
-				printf("Usage: %s [-e] [-f <file_name.cs>] [-d <directory>]\n", argv[0]);
-				exit(-1);
-		}
-	}
-
-	if (flag == 0) {
-		printf("Usage: %s [-e] [-f <file_name.cs>] [-d <directory>]\n", argv[0]);
-		exit(-1);
-	}
-
-	return 0;
-}
diff --git a/suite/cstest/src/mips_detail.c b/suite/cstest/src/mips_detail.c
deleted file mode 100644
index c859ab6d7..000000000
--- a/suite/cstest/src/mips_detail.c
+++ /dev/null
@@ -1,48 +0,0 @@
-/* Capstone testing regression */
-/* By Do Minh Tuan <tuanit96@gmail.com>, 02-2019 */
-
-
-#include "factory.h"
-
-char *get_detail_mips(csh *handle, cs_mode mode, cs_insn *ins)
-{
-	int i;
-	cs_mips *mips;
-	char *result;
-
-	result = (char *)malloc(sizeof(char));
-	result[0] = '\0';
-
-	if (ins->detail == NULL)
-		return result;
-
-	mips = &(ins->detail->mips);
-	if (mips->op_count)
-		add_str(&result, " ; op_count: %u", mips->op_count);
-
-	for (i = 0; i < mips->op_count; i++) {
-		cs_mips_op *op = &(mips->operands[i]);
-		switch((int)op->type) {
-			default:
-				break;
-			case MIPS_OP_REG:
-				add_str(&result, " ; operands[%u].type: REG = %s", i, cs_reg_name(*handle, op->reg));
-				break;
-			case MIPS_OP_IMM:
-				add_str(&result, " ; operands[%u].type: IMM = 0x%" PRIx64 "", i, op->imm);
-				break;
-			case MIPS_OP_MEM:
-				add_str(&result, " ; operands[%u].type: MEM", i);
-				if (op->mem.base != MIPS_REG_INVALID)
-					add_str(&result, " ; operands[%u].mem.base: REG = %s", i, cs_reg_name(*handle, op->mem.base));
-				if (op->mem.disp != 0)
-					add_str(&result, " ; operands[%u].mem.disp: 0x%" PRIx64 "", i, op->mem.disp);
-
-				break;
-		}
-
-	}
-
-	return result;
-}
-
diff --git a/suite/cstest/src/mos65xx_detail.c b/suite/cstest/src/mos65xx_detail.c
deleted file mode 100644
index b039f2e76..000000000
--- a/suite/cstest/src/mos65xx_detail.c
+++ /dev/null
@@ -1,103 +0,0 @@
-/* Capstone testing regression */
-/* By Do Minh Tuan <tuanit96@gmail.com>, 02-2019 */
-
-
-#include "factory.h"
-
-static const char *get_am_name(mos65xx_address_mode mode)
-{
-	switch(mode) {
-		default:
-		case MOS65XX_AM_NONE:
-			return "No address mode";
-		case MOS65XX_AM_IMP:
-			return "implied";
-		case MOS65XX_AM_ACC:
-			return "accumulator";
-		case MOS65XX_AM_IMM:
-			return "immediate value";
-		case MOS65XX_AM_REL:
-			return "relative";
-		case MOS65XX_AM_INT:
-			return "interrupt signature";
-		case MOS65XX_AM_BLOCK:
-			return "block move";
-		case MOS65XX_AM_ZP:
-			return "zero page";
-		case MOS65XX_AM_ZP_X:
-			return "zero page indexed with x";
-		case MOS65XX_AM_ZP_Y:
-			return "zero page indexed with y";
-		case MOS65XX_AM_ZP_REL:
-			return "relative bit branch";
-		case MOS65XX_AM_ZP_IND:
-			return "zero page indirect";
-		case MOS65XX_AM_ZP_X_IND:
-			return "zero page indexed with x indirect";
-		case MOS65XX_AM_ZP_IND_Y:
-			return "zero page indirect indexed with y";
-		case MOS65XX_AM_ZP_IND_LONG:
-			return "zero page indirect long";
-		case MOS65XX_AM_ZP_IND_LONG_Y:
-			return "zero page indirect long indexed with y";
-		case MOS65XX_AM_ABS:
-			return "absolute";
-		case MOS65XX_AM_ABS_X:
-			return "absolute indexed with x";
-		case MOS65XX_AM_ABS_Y:
-			return "absolute indexed with y";
-		case MOS65XX_AM_ABS_IND:
-			return "absolute indirect";
-		case MOS65XX_AM_ABS_X_IND:
-			return "absolute indexed with x indirect";
-		case MOS65XX_AM_ABS_IND_LONG:
-			return "absolute indirect long";
-		case MOS65XX_AM_ABS_LONG:
-			return "absolute long";
-		case MOS65XX_AM_ABS_LONG_X:
-			return "absolute long indexed with x";
-		case MOS65XX_AM_SR:
-			return "stack relative";
-		case MOS65XX_AM_SR_IND_Y:
-			return "stack relative indirect indexed with y";
-	}
-}
-
-
-char *get_detail_mos65xx(csh *handle, cs_mode mode, cs_insn *ins)
-{
-	int i;
-	cs_mos65xx *mos65xx;
-	char *result;
-
-	result = (char *)malloc(sizeof(char));
-	result[0] = '\0';
-
-	if (ins->detail == NULL)
-		return result;
-
-	mos65xx = &(ins->detail->mos65xx);
-	add_str(&result, " ; address mode: %s", get_am_name(mos65xx->am));
-	add_str(&result, " ; modifies flags: %s", mos65xx->modifies_flags ? "true": "false");
-
-	if (mos65xx->op_count)
-		add_str(&result, " ; op_count: %u", mos65xx->op_count);
-
-	for (i = 0; i < mos65xx->op_count; i++) {
-		cs_mos65xx_op *op = &(mos65xx->operands[i]);
-		switch((int)op->type) {
-			default:
-				break;
-			case MOS65XX_OP_REG:
-				add_str(&result, " ; operands[%u].type: REG = %s", i, cs_reg_name(*handle, op->reg));
-				break;
-			case MOS65XX_OP_IMM:
-				add_str(&result, " ; operands[%u].type: IMM = 0x%x", i, op->imm);
-				break;
-			case MOS65XX_OP_MEM:
-				add_str(&result, " ; operands[%u].type: MEM = 0x%x", i, op->mem);
-				break;
-		}
-	}
-	return result;
-}
diff --git a/suite/cstest/src/ppc_detail.c b/suite/cstest/src/ppc_detail.c
deleted file mode 100644
index 53660e50f..000000000
--- a/suite/cstest/src/ppc_detail.c
+++ /dev/null
@@ -1,96 +0,0 @@
-/* Capstone testing regression */
-/* By Do Minh Tuan <tuanit96@gmail.com>, 02-2019 */
-
-
-#include "factory.h"
-
-static const char* get_pred_name(int bc)
-{
-	switch(bc) {
-		default:
-		case PPC_PRED_LT:
-			return ("lt");
-		case PPC_PRED_LE:
-			return ("le");
-		case PPC_PRED_EQ:
-			return ("eq");
-		case PPC_PRED_GE:
-			return ("ge");
-		case PPC_PRED_GT:
-			return ("gt");
-		case PPC_PRED_NE:
-			return ("ne");
-		case PPC_PRED_UN:
-			return ("so/un");
-		case PPC_PRED_NU:
-			return ("ns/nu");
-	}
-}
-
-char *get_detail_ppc(csh *handle, cs_mode mode, cs_insn *ins)
-{
-	cs_ppc *ppc;
-	int i;
-	char *result;
-
-	result = (char *)malloc(sizeof(char));
-	result[0] = '\0';
-
-	if (ins->detail == NULL)
-		return result;
-
-	ppc = &(ins->detail->ppc);
-	if (ppc->op_count)
-		add_str(&result, " ; op_count: %u", ppc->op_count);
-
-	for (i = 0; i < ppc->op_count; i++) {
-		cs_ppc_op *op = &(ppc->operands[i]);
-		switch((int)op->type) {
-			default:
-				break;
-			case PPC_OP_REG:
-				add_str(&result, " ; operands[%u].type: REG = %s", i, cs_reg_name(*handle, op->reg));
-				break;
-			case PPC_OP_IMM:
-				add_str(&result, " ; operands[%u].type: IMM = 0x%"PRIx64"", i, op->imm);
-				break;
-			case PPC_OP_MEM:
-				add_str(&result, " ; operands[%u].type: MEM", i);
-				if (op->mem.base != PPC_REG_INVALID)
-					add_str(&result, " ; operands[%u].mem.base: REG = %s", i, cs_reg_name(*handle, op->mem.base));
-				if (op->mem.disp != 0)
-					add_str(&result, " ; operands[%u].mem.disp: 0x%x", i, op->mem.disp);
-
-				break;
-		}
-	}
-
-	if (ppc->bc.pred_cr != PPC_PRED_INVALID ||
-			ppc->bc.pred_ctr != PPC_PRED_INVALID) {
-		printf("\tBranch:\n");
-		printf("\t\tbi: %u\n", ppc->bc.bi);
-		printf("\t\tbo: %u\n", ppc->bc.bo);
-		if (ppc->bc.bh != PPC_BH_INVALID)
-			printf("\t\tbh: %u\n", ppc->bc.bh);
-		if (ppc->bc.pred_cr != PPC_PRED_INVALID) {
-			printf("\t\tcrX: %s\n", cs_reg_name(*handle, ppc->bc.crX));
-			printf("\t\tpred CR-bit: %s\n", get_pred_name(ppc->bc.pred_cr));
-		}
-		if (ppc->bc.pred_ctr != PPC_PRED_INVALID)
-			printf("\t\tpred CTR: %s\n", get_pred_name(ppc->bc.pred_ctr));
-		if (ppc->bc.hint != PPC_BR_NOT_GIVEN)
-			printf("\t\thint: %u\n", ppc->bc.hint);
-	}
-
-	if (ppc->bc.hint != PPC_BR_NOT_GIVEN)
-		printf("\tBranch hint: %u\n", ppc->bc.hint);
-
-	if (ppc->bc.hint != PPC_BR_NOT_GIVEN)
-		add_str(&result, " ; Branch hint: %u", ppc->bc.hint);
-
-	if (ppc->update_cr0)
-		add_str(&result, " ; Update-CR0: True");
-
-	return result;
-}
-
diff --git a/suite/cstest/src/riscv_detail.c b/suite/cstest/src/riscv_detail.c
deleted file mode 100644
index ac9ea03d8..000000000
--- a/suite/cstest/src/riscv_detail.c
+++ /dev/null
@@ -1,61 +0,0 @@
-/* Capstone testing regression */
-/* By Do Minh Tuan <tuanit96@gmail.com>, 02-2019 */
-
-
-#include "factory.h"
-
-char *get_detail_riscv(csh *handle, cs_mode mode, cs_insn *ins)
-{
-	cs_riscv *riscv;
-	int i;
-	char *result;
-
-	result = (char *)malloc(sizeof(char));
-	result[0] = '\0';
-
-	if (ins->detail == NULL)
-		return result;
-
-	riscv = &(ins->detail->riscv);
-	if (riscv->op_count)
-		add_str(&result, " ; op_count: %u", riscv->op_count);
-
-	for (i = 0; i < riscv->op_count; i++) {
-		cs_riscv_op *op = &(riscv->operands[i]);
-		switch((int)op->type) {
-			default:
-				break;
-			case RISCV_OP_REG:
-				add_str(&result, " ; operands[%u].type: REG = %s", i, cs_reg_name(*handle, op->reg));
-				break;
-			case RISCV_OP_IMM:
-				add_str(&result, " ; operands[%u].type: IMM = 0x%x", i, op->imm);
-				break;
-			case RISCV_OP_MEM:
-				add_str(&result, " ; operands[%u].type: MEM", i);
-				if (op->mem.base != RISCV_REG_INVALID)
-					add_str(&result, " ; operands[%u].mem.base: REG = %s",
-							i, cs_reg_name(*handle, op->mem.base));
-				if (op->mem.disp != 0)
-					add_str(&result, " ; operands[%u].mem.disp: 0x%x", i, op->mem.disp);
-				break;
-		}
-
-		switch(op->access) {
-			default:
-				break;
-			case CS_AC_READ:
-				add_str(&result, " ; operands[%u].access: READ", i);
-				break;
-			case CS_AC_WRITE:
-				add_str(&result, " ; operands[%u].access: WRITE", i);
-				break;
-			case CS_AC_READ | CS_AC_WRITE:
-				add_str(&result, " ; operands[%u].access: READ | WRITE", i);
-				break;
-		}
-	}
-
-	return result;
-}
-
diff --git a/suite/cstest/src/sparc_detail.c b/suite/cstest/src/sparc_detail.c
deleted file mode 100644
index 54c6bb483..000000000
--- a/suite/cstest/src/sparc_detail.c
+++ /dev/null
@@ -1,55 +0,0 @@
-/* Capstone testing regression */
-/* By Do Minh Tuan <tuanit96@gmail.com>, 02-2019 */
-
-
-#include "factory.h"
-
-char *get_detail_sparc(csh *handle, cs_mode mode, cs_insn *ins)
-{
-	cs_sparc *sparc;
-	int i;
-	char *result;
-
-	result = (char *)malloc(sizeof(char));
-	result[0] = '\0';
-
-	if (ins->detail == NULL)
-		return result;
-
-	sparc = &(ins->detail->sparc);
-	if (sparc->op_count)
-		add_str(&result, " ; op_count: %u", sparc->op_count);
-
-	for (i = 0; i < sparc->op_count; i++) {
-		cs_sparc_op *op = &(sparc->operands[i]);
-		switch((int)op->type) {
-			default:
-				break;
-			case SPARC_OP_REG:
-				add_str(&result, " ; operands[%u].type: REG = %s", i, cs_reg_name(*handle, op->reg));
-				break;
-			case SPARC_OP_IMM:
-				add_str(&result, " ; operands[%u].type: IMM = 0x%" PRIx64 "", i, op->imm);
-				break;
-			case SPARC_OP_MEM:
-				add_str(&result, " ; operands[%u].type: MEM", i);
-				if (op->mem.base != X86_REG_INVALID)
-					add_str(&result, " ; operands[%u].mem.base: REG = %s", i, cs_reg_name(*handle, op->mem.base));
-				if (op->mem.index != X86_REG_INVALID)
-					add_str(&result, " ; operands[%u].mem.index: REG = %s", i, cs_reg_name(*handle, op->mem.index));
-				if (op->mem.disp != 0)
-					add_str(&result, " ; operands[%u].mem.disp: 0x%x", i, op->mem.disp);
-
-				break;
-		}
-	}
-
-	if (sparc->cc != 0)
-		add_str(&result, " ; Code condition: %u", sparc->cc);
-
-	if (sparc->hint != 0)
-		add_str(&result, " ; Hint code: %u", sparc->hint);
-
-	return result;
-}
-
diff --git a/suite/cstest/src/systemz_detail.c b/suite/cstest/src/systemz_detail.c
deleted file mode 100644
index b9d24a055..000000000
--- a/suite/cstest/src/systemz_detail.c
+++ /dev/null
@@ -1,57 +0,0 @@
-/* Capstone testing regression */
-/* By Do Minh Tuan <tuanit96@gmail.com>, 02-2019 */
-
-
-#include "factory.h"
-
-char *get_detail_sysz(csh *handle, cs_mode mode, cs_insn *ins)
-{
-	cs_sysz *sysz;
-	int i;
-	char *result;
-
-	result = (char *)malloc(sizeof(char));
-	result[0] = '\0';
-
-	if (ins->detail == NULL)
-		return result;
-
-	sysz = &(ins->detail->sysz);
-	if (sysz->op_count)
-		add_str(&result, " ; op_count: %u", sysz->op_count);
-
-	for (i = 0; i < sysz->op_count; i++) {
-		cs_sysz_op *op = &(sysz->operands[i]);
-		switch((int)op->type) {
-			default:
-				break;
-			case SYSZ_OP_REG:
-				add_str(&result, " ; operands[%u].type: REG = %s", i, cs_reg_name(*handle, op->reg));
-				break;
-			case SYSZ_OP_ACREG:
-				add_str(&result, " ; operands[%u].type: ACREG = %u", i, op->reg);
-				break;
-			case SYSZ_OP_IMM:
-				add_str(&result, " ; operands[%u].type: IMM = 0x%" PRIx64 "", i, op->imm);
-				break;
-			case SYSZ_OP_MEM:
-				add_str(&result, " ; operands[%u].type: MEM", i);
-				if (op->mem.base != SYSZ_REG_INVALID)
-					add_str(&result, " ; operands[%u].mem.base: REG = %s", i, cs_reg_name(*handle, op->mem.base));
-				if (op->mem.index != SYSZ_REG_INVALID)
-					add_str(&result, " ; operands[%u].mem.index: REG = %s", i, cs_reg_name(*handle, op->mem.index));
-				if (op->mem.length != 0)
-					add_str(&result, " ; operands[%u].mem.length: 0x%" PRIx64 "", i, op->mem.length);
-				if (op->mem.disp != 0)
-					add_str(&result, " ; operands[%u].mem.disp: 0x%" PRIx64 "", i, op->mem.disp);
-
-				break;
-		}
-	}
-
-	if (sysz->cc != 0)
-		add_str(&result, " ; Code condition: %u", sysz->cc);
-
-	return result;
-}
-
diff --git a/suite/cstest/src/test_case.c b/suite/cstest/src/test_case.c
new file mode 100644
index 000000000..cd1ece6bb
--- /dev/null
+++ b/suite/cstest/src/test_case.c
@@ -0,0 +1,330 @@
+// Copyright © 2024 Rot127 <unisono@quyllur.org>
+// SPDX-License-Identifier: BSD-3
+
+#include <stdarg.h>
+#include <stddef.h>
+#include <setjmp.h>
+#include "cmocka.h"
+#include "test_detail.h"
+#include "test_case.h"
+#include "helper.h"
+#include "../../../utils.h"
+#include <stdio.h>
+#include <string.h>
+
+TestInput *test_input_new()
+{
+	TestInput *p = cs_mem_calloc(sizeof(TestInput), 1);
+	assert(p);
+	return p;
+}
+
+void test_input_free(TestInput *test_input)
+{
+	if (!test_input) {
+		return;
+	}
+	cs_mem_free(test_input->name);
+	cs_mem_free(test_input->bytes);
+	cs_mem_free(test_input->arch);
+	for (size_t i = 0; i < test_input->options_count; i++) {
+		cs_mem_free(test_input->options[i]);
+	}
+	cs_mem_free(test_input->options);
+	cs_mem_free(test_input);
+}
+
+TestInput *test_input_clone(TestInput *test_input)
+{
+	assert(test_input);
+	TestInput *ti = test_input_new();
+	ti->address = test_input->address;
+
+	for (size_t i = 0; i < test_input->options_count; i++) {
+		ti->options = cs_mem_realloc(
+			ti->options, sizeof(char *) * (ti->options_count + 1));
+		ti->options[i] = cs_strdup(test_input->options[i]);
+		ti->options_count++;
+	}
+	ti->name = test_input->name ? cs_strdup(test_input->name) : NULL;
+	ti->arch = cs_strdup(test_input->arch);
+	ti->bytes = cs_mem_calloc(sizeof(uint8_t), test_input->bytes_count);
+	ti->bytes_count = test_input->bytes_count;
+	memcpy(ti->bytes, test_input->bytes, test_input->bytes_count);
+	return ti;
+}
+
+char *test_input_stringify(const TestInput *test_input, const char *postfix)
+{
+	size_t msg_len = 2048;
+	char *msg = cs_mem_calloc(sizeof(char), msg_len);
+	char *byte_seq =
+		byte_seq_to_str(test_input->bytes, test_input->bytes_count);
+	if (!msg) {
+		return NULL;
+	}
+	char opt_seq[128] = { 0 };
+	append_to_str(opt_seq, sizeof(opt_seq), "[");
+	for (size_t i = 0; i < test_input->options_count; ++i) {
+		append_to_str(opt_seq, sizeof(opt_seq), test_input->options[i]);
+		if (i < test_input->options_count - 1) {
+			append_to_str(opt_seq, sizeof(opt_seq), ", ");
+		}
+	}
+	append_to_str(opt_seq, sizeof(opt_seq), "]");
+	cs_snprintf(msg, msg_len,
+		    "%sTestInput { arch: %s, options: %s, addr: 0x%" PRIx64
+		    ", bytes: %s }",
+		    postfix, test_input->arch, opt_seq, test_input->address,
+		    byte_seq);
+	cs_mem_free(byte_seq);
+	return msg;
+}
+
+TestInsnData *test_insn_data_new()
+{
+	TestInsnData *p = cs_mem_calloc(sizeof(TestInsnData), 1);
+	assert(p);
+	return p;
+}
+
+void test_insn_data_free(TestInsnData *test_insn_data)
+{
+	if (!test_insn_data) {
+		return;
+	}
+	cs_mem_free(test_insn_data->asm_text);
+	cs_mem_free(test_insn_data->op_str);
+	cs_mem_free(test_insn_data->mnemonic);
+	test_detail_free(test_insn_data->details);
+	cs_mem_free(test_insn_data);
+}
+
+TestInsnData *test_insn_data_clone(TestInsnData *test_insn_data)
+{
+	assert(test_insn_data);
+	TestInsnData *tid = test_insn_data_new();
+	tid->alias_id = test_insn_data->alias_id;
+	tid->is_alias = test_insn_data->is_alias;
+	tid->id = test_insn_data->id;
+	tid->mnemonic = test_insn_data->mnemonic ?
+				cs_strdup(test_insn_data->mnemonic) :
+				NULL;
+	tid->op_str = test_insn_data->op_str ?
+			      cs_strdup(test_insn_data->op_str) :
+			      NULL;
+	tid->asm_text = test_insn_data->asm_text ?
+				cs_strdup(test_insn_data->asm_text) :
+				NULL;
+	if (test_insn_data->details) {
+		tid->details = test_detail_clone(test_insn_data->details);
+	}
+	return tid;
+}
+
+TestExpected *test_expected_new()
+{
+	TestExpected *p = cs_mem_calloc(sizeof(TestExpected), 1);
+	assert(p);
+	return p;
+}
+
+void test_expected_free(TestExpected *test_expected)
+{
+	if (!test_expected) {
+		return;
+	}
+	for (size_t i = 0; i < test_expected->insns_count; i++) {
+		test_insn_data_free(test_expected->insns[i]);
+	}
+	cs_mem_free(test_expected->insns);
+	cs_mem_free(test_expected);
+}
+
+TestExpected *test_expected_clone(TestExpected *test_expected)
+{
+	assert(test_expected);
+	TestExpected *te = test_expected_new();
+	te->insns = cs_mem_calloc(sizeof(TestInsnData *),
+				  test_expected->insns_count);
+	for (size_t i = 0; i < test_expected->insns_count; i++) {
+		te->insns[i] = test_insn_data_clone(test_expected->insns[i]);
+		te->insns_count++;
+	}
+	return te;
+}
+
+/// Compares the given @asm_text to the @expected one.
+/// Because Capstone sometimes deviates from the LLVM syntax
+/// the strings don't need to be the same to be considered a valid match.
+/// E.g. Capstone sometimes prints decimal numbers instead of hexadecimal
+/// for readability.
+static bool compare_asm_text(const char *asm_text, const char *expected,
+			     size_t arch_bits)
+{
+	if (!asm_text || !expected) {
+		fprintf(stderr, "[!] asm_text or expected was NULL\n");
+		return false;
+	}
+	if (strcmp(asm_text, expected) == 0) {
+		return true;
+	}
+	// Normalize both strings
+	char asm_copy[MAX_ASM_TXT_MEM] = { 0 };
+	strncpy(asm_copy, asm_text, MAX_ASM_TXT_MEM - 1);
+	trim_str(asm_copy);
+	replace_hex(asm_copy, sizeof(asm_copy));
+	replace_negative(asm_copy, sizeof(asm_copy), arch_bits);
+	norm_spaces(asm_copy);
+	str_to_lower(asm_copy);
+
+	char expected_copy[MAX_ASM_TXT_MEM] = { 0 };
+	strncpy(expected_copy, expected, MAX_ASM_TXT_MEM - 1);
+	trim_str(expected_copy);
+	replace_hex(expected_copy, sizeof(expected_copy));
+	replace_negative(expected_copy, sizeof(expected_copy), arch_bits);
+	norm_spaces(expected_copy);
+	str_to_lower(expected_copy);
+
+	if (strcmp(asm_copy, expected_copy) == 0) {
+		return true;
+	}
+
+	fprintf(stderr,
+		"Normalized asm-text doesn't match:\n"
+		"decoded:  '%s'\n"
+		"expected: '%s'\n",
+		asm_copy, expected_copy);
+	return false;
+}
+
+/// Compares the decoded instructions @insns against the @expected values and returns the result.
+void test_expected_compare(csh *handle, TestExpected *expected, cs_insn *insns,
+			   size_t insns_count, size_t arch_bits)
+{
+	assert_int_equal(insns_count, expected->insns_count);
+	for (size_t i = 0; i < insns_count; ++i) {
+		TestInsnData *expec_data = expected->insns[i];
+		// Test mandatory fields first
+		// The asm text is saved differently for different architectures.
+		// Either all in op_str or split in mnemonic and op_str
+		char asm_text[256] = { 0 };
+		if (insns[i].mnemonic[0] != '\0') {
+			append_to_str(asm_text, sizeof(asm_text),
+				      insns[i].mnemonic);
+			append_to_str(asm_text, sizeof(asm_text), " ");
+		}
+		if (insns[i].op_str[0] != '\0') {
+			append_to_str(asm_text, sizeof(asm_text),
+				      insns[i].op_str);
+		}
+		if (!compare_asm_text(asm_text, expec_data->asm_text,
+				      arch_bits)) {
+			fail_msg("asm-text mismatch\n");
+		}
+
+		// Not mandatory fields. If not initialized they should still match.
+		if (expec_data->id != 0) {
+			assert_int_equal(insns[i].id, expec_data->id);
+		}
+		if (expec_data->is_alias != 0) {
+			if (expec_data->is_alias > 0) {
+				assert_true(insns[i].is_alias);
+			} else {
+				assert_false(insns[i].is_alias);
+			}
+		}
+		if (expec_data->alias_id != 0) {
+			assert_int_equal(insns[i].alias_id,
+					 expec_data->alias_id);
+		}
+		if (expec_data->mnemonic) {
+			assert_string_equal(insns[i].mnemonic,
+					    expec_data->mnemonic);
+		}
+		if (expec_data->op_str) {
+			assert_string_equal(insns[i].op_str,
+					    expec_data->op_str);
+		}
+		if (expec_data->details) {
+			if (!insns[i].detail) {
+				fprintf(stderr, "detail is NULL\n");
+				assert_non_null(insns[i].detail);
+			}
+			assert_true(test_expected_detail(handle, &insns[i],
+							 expec_data->details));
+		}
+	}
+}
+
+TestCase *test_case_new()
+{
+	TestCase *p = cs_mem_calloc(sizeof(TestCase), 1);
+	assert(p);
+	return p;
+}
+
+void test_case_free(TestCase *test_case)
+{
+	if (!test_case) {
+		return;
+	}
+	test_input_free(test_case->input);
+	test_expected_free(test_case->expected);
+	cs_mem_free(test_case->skip_reason);
+	cs_mem_free(test_case);
+}
+
+TestCase *test_case_clone(TestCase *test_case)
+{
+	assert(test_case);
+	TestCase *tc = test_case_new();
+	TestInput *ti = test_input_clone(test_case->input);
+	tc->input = ti;
+	TestExpected *te = test_expected_clone(test_case->expected);
+	tc->expected = te;
+	tc->skip = test_case->skip;
+	if (tc->skip) {
+		tc->skip_reason = strdup(test_case->skip_reason);
+	}
+	return tc;
+}
+
+TestFile *test_file_new()
+{
+	TestFile *p = cs_mem_calloc(sizeof(TestFile), 1);
+	assert(p);
+	return p;
+}
+
+void test_file_free(TestFile *test_file)
+{
+	if (!test_file) {
+		return;
+	}
+
+	for (size_t i = 0; i < test_file->test_cases_count; ++i) {
+		test_case_free(test_file->test_cases[i]);
+	}
+
+	cs_mem_free(test_file->test_cases);
+	cs_mem_free(test_file->filename);
+	test_file->filename = NULL;
+	cs_mem_free(test_file);
+}
+
+TestFile *test_file_clone(TestFile *test_file)
+{
+	assert(test_file);
+	TestFile *tf = test_file_new();
+	tf->filename = test_file->filename ? strdup(test_file->filename) : NULL;
+	tf->test_cases =
+		cs_mem_calloc(sizeof(TestCase *), test_file->test_cases_count);
+
+	for (size_t i = 0; i < test_file->test_cases_count;
+	     i++, tf->test_cases_count++) {
+		TestCase *tc = test_case_clone(test_file->test_cases[i]);
+		tf->test_cases[i] = tc;
+	}
+	return tf;
+}
diff --git a/suite/cstest/src/test_detail.c b/suite/cstest/src/test_detail.c
new file mode 100644
index 000000000..0128217ae
--- /dev/null
+++ b/suite/cstest/src/test_detail.c
@@ -0,0 +1,408 @@
+// Copyright © 2024 Rot127 <unisono@quyllur.org>
+// SPDX-License-Identifier: BSD-3
+
+#include "test_detail.h"
+#include "test_compare.h"
+#include <capstone/capstone.h>
+
+TestDetail *test_detail_new()
+{
+	return cs_mem_calloc(sizeof(TestDetail), 1);
+}
+
+TestDetail *test_detail_clone(TestDetail *detail)
+{
+	assert(detail);
+	TestDetail *clone = test_detail_new();
+
+	clone->regs_read =
+		detail->regs_read_count > 0 ?
+			cs_mem_calloc(sizeof(char *), detail->regs_read_count) :
+			NULL;
+	clone->regs_read_count = detail->regs_read_count;
+	for (size_t i = 0; i < detail->regs_read_count; ++i) {
+		clone->regs_read[i] = strdup(detail->regs_read[i]);
+	}
+
+	clone->regs_write = detail->regs_write_count > 0 ?
+				    cs_mem_calloc(sizeof(char *),
+						  detail->regs_write_count) :
+				    NULL;
+	clone->regs_write_count = detail->regs_write_count;
+	for (size_t i = 0; i < detail->regs_write_count; ++i) {
+		clone->regs_write[i] = strdup(detail->regs_write[i]);
+	}
+
+	clone->regs_impl_read =
+		detail->regs_impl_read_count > 0 ?
+			cs_mem_calloc(sizeof(char *),
+				      detail->regs_impl_read_count) :
+			NULL;
+	clone->regs_impl_read_count = detail->regs_impl_read_count;
+	for (size_t i = 0; i < detail->regs_impl_read_count; ++i) {
+		clone->regs_impl_read[i] = strdup(detail->regs_impl_read[i]);
+	}
+
+	clone->regs_impl_write =
+		detail->regs_impl_write_count > 0 ?
+			cs_mem_calloc(sizeof(char *),
+				      detail->regs_impl_write_count) :
+			NULL;
+	clone->regs_impl_write_count = detail->regs_impl_write_count;
+	for (size_t i = 0; i < detail->regs_impl_write_count; ++i) {
+		clone->regs_impl_write[i] = strdup(detail->regs_impl_write[i]);
+	}
+
+	clone->groups =
+		detail->groups_count > 0 ?
+			cs_mem_calloc(sizeof(char *), detail->groups_count) :
+			NULL;
+	clone->groups_count = detail->groups_count;
+	for (size_t i = 0; i < detail->groups_count; ++i) {
+		clone->groups[i] = strdup(detail->groups[i]);
+	}
+
+	if (detail->aarch64) {
+		clone->aarch64 = test_detail_aarch64_clone(detail->aarch64);
+	}
+	if (detail->arm) {
+		clone->arm = test_detail_arm_clone(detail->arm);
+	}
+	if (detail->ppc) {
+		clone->ppc = test_detail_ppc_clone(detail->ppc);
+	}
+	if (detail->tricore) {
+		clone->tricore = test_detail_tricore_clone(detail->tricore);
+	}
+	if (detail->alpha) {
+		clone->alpha = test_detail_alpha_clone(detail->alpha);
+	}
+	if (detail->bpf) {
+		clone->bpf = test_detail_bpf_clone(detail->bpf);
+	}
+	if (detail->hppa) {
+		clone->hppa = test_detail_hppa_clone(detail->hppa);
+	}
+	if (detail->xcore) {
+		clone->xcore = test_detail_xcore_clone(detail->xcore);
+	}
+	if (detail->systemz) {
+		clone->systemz = test_detail_systemz_clone(detail->systemz);
+	}
+	if (detail->sparc) {
+		clone->sparc = test_detail_sparc_clone(detail->sparc);
+	}
+	if (detail->sh) {
+		clone->sh = test_detail_sh_clone(detail->sh);
+	}
+	if (detail->mips) {
+		clone->mips = test_detail_mips_clone(detail->mips);
+	}
+	if (detail->riscv) {
+		clone->riscv = test_detail_riscv_clone(detail->riscv);
+	}
+	if (detail->m680x) {
+		clone->m680x = test_detail_m680x_clone(detail->m680x);
+	}
+	if (detail->tms320c64x) {
+		clone->tms320c64x =
+			test_detail_tms320c64x_clone(detail->tms320c64x);
+	}
+	if (detail->mos65xx) {
+		clone->mos65xx = test_detail_mos65xx_clone(detail->mos65xx);
+	}
+	if (detail->evm) {
+		clone->evm = test_detail_evm_clone(detail->evm);
+	}
+	if (detail->loongarch) {
+		clone->loongarch =
+			test_detail_loongarch_clone(detail->loongarch);
+	}
+	if (detail->wasm) {
+		clone->wasm = test_detail_wasm_clone(detail->wasm);
+	}
+	if (detail->x86) {
+		clone->x86 = test_detail_x86_clone(detail->x86);
+	}
+	if (detail->m68k) {
+		clone->m68k = test_detail_m68k_clone(detail->m68k);
+	}
+
+	return clone;
+}
+
+void test_detail_free(TestDetail *detail)
+{
+	if (!detail) {
+		return;
+	}
+
+	for (size_t i = 0; i < detail->regs_read_count; ++i) {
+		cs_mem_free(detail->regs_read[i]);
+	}
+	cs_mem_free(detail->regs_read);
+
+	for (size_t i = 0; i < detail->regs_write_count; ++i) {
+		cs_mem_free(detail->regs_write[i]);
+	}
+	cs_mem_free(detail->regs_write);
+
+	for (size_t i = 0; i < detail->regs_impl_read_count; ++i) {
+		cs_mem_free(detail->regs_impl_read[i]);
+	}
+	cs_mem_free(detail->regs_impl_read);
+
+	for (size_t i = 0; i < detail->regs_impl_write_count; ++i) {
+		cs_mem_free(detail->regs_impl_write[i]);
+	}
+	cs_mem_free(detail->regs_impl_write);
+
+	for (size_t i = 0; i < detail->groups_count; ++i) {
+		cs_mem_free(detail->groups[i]);
+	}
+	cs_mem_free(detail->groups);
+
+	if (detail->aarch64) {
+		test_detail_aarch64_free(detail->aarch64);
+	}
+	if (detail->arm) {
+		test_detail_arm_free(detail->arm);
+	}
+	if (detail->ppc) {
+		test_detail_ppc_free(detail->ppc);
+	}
+	if (detail->tricore) {
+		test_detail_tricore_free(detail->tricore);
+	}
+	if (detail->alpha) {
+		test_detail_alpha_free(detail->alpha);
+	}
+	if (detail->hppa) {
+		test_detail_hppa_free(detail->hppa);
+	}
+	if (detail->bpf) {
+		test_detail_bpf_free(detail->bpf);
+	}
+	if (detail->xcore) {
+		test_detail_xcore_free(detail->xcore);
+	}
+	if (detail->systemz) {
+		test_detail_systemz_free(detail->systemz);
+	}
+	if (detail->sparc) {
+		test_detail_sparc_free(detail->sparc);
+	}
+	if (detail->sh) {
+		test_detail_sh_free(detail->sh);
+	}
+	if (detail->mips) {
+		test_detail_mips_free(detail->mips);
+	}
+	if (detail->riscv) {
+		test_detail_riscv_free(detail->riscv);
+	}
+	if (detail->m680x) {
+		test_detail_m680x_free(detail->m680x);
+	}
+	if (detail->tms320c64x) {
+		test_detail_tms320c64x_free(detail->tms320c64x);
+	}
+	if (detail->mos65xx) {
+		test_detail_mos65xx_free(detail->mos65xx);
+	}
+	if (detail->evm) {
+		test_detail_evm_free(detail->evm);
+	}
+	if (detail->loongarch) {
+		test_detail_loongarch_free(detail->loongarch);
+	}
+	if (detail->wasm) {
+		test_detail_wasm_free(detail->wasm);
+	}
+	if (detail->x86) {
+		test_detail_x86_free(detail->x86);
+	}
+	if (detail->m68k) {
+		test_detail_m68k_free(detail->m68k);
+	}
+
+	cs_mem_free(detail);
+}
+
+static bool test_reg_rw_access(csh *handle, const cs_insn *insn,
+			       TestDetail *expected)
+{
+	assert(handle && insn && expected);
+	if (expected->regs_read_count <= 0 && expected->regs_write_count <= 0) {
+		return true;
+	}
+
+	cs_regs regs_read, regs_write;
+	uint8_t regs_read_count, regs_write_count;
+	cs_err err = cs_regs_access(*handle, insn, regs_read, &regs_read_count,
+				    regs_write, &regs_write_count);
+	if (err != CS_ERR_OK) {
+		fprintf(stderr, "cs_regs_access() failed with '%s'\n",
+			cs_strerror(err));
+		return false;
+	}
+
+	if (expected->regs_read_count > 0) {
+		compare_uint32_ret(regs_read_count, expected->regs_read_count,
+				   false);
+		for (size_t i = 0; i < regs_read_count; ++i) {
+			compare_reg_ret(*handle, regs_read[i],
+					expected->regs_read[i], false);
+		}
+	}
+
+	if (expected->regs_write_count > 0) {
+		compare_uint32_ret(regs_write_count, expected->regs_write_count,
+				   false);
+		for (size_t i = 0; i < regs_write_count; ++i) {
+			compare_reg_ret(*handle, regs_write[i],
+					expected->regs_write[i], false);
+		}
+	}
+	return true;
+}
+
+static bool test_impl_reg_rw_access(csh *handle, const cs_insn *insn,
+				    TestDetail *expected)
+{
+	assert(handle && insn && expected);
+	if (expected->regs_impl_read_count <= 0 &&
+	    expected->regs_impl_write_count <= 0) {
+		return true;
+	}
+	cs_detail *actual = insn->detail;
+
+	// Test exclusively the implicitly read or written register.
+	if (expected->regs_impl_read_count > 0) {
+		compare_uint32_ret(actual->regs_read_count,
+				   expected->regs_impl_read_count, false);
+		for (size_t i = 0; i < actual->regs_read_count; ++i) {
+			compare_reg_ret(*handle, actual->regs_read[i],
+					expected->regs_impl_read[i], false);
+		}
+	}
+
+	if (expected->regs_impl_write_count > 0) {
+		compare_uint32_ret(actual->regs_write_count,
+				   expected->regs_impl_write_count, false);
+		for (size_t i = 0; i < actual->regs_write_count; ++i) {
+			compare_reg_ret(*handle, actual->regs_write[i],
+					expected->regs_impl_write[i], false);
+		}
+	}
+	return true;
+}
+
+bool test_expected_detail(csh *handle, const cs_insn *insn,
+			  TestDetail *expected)
+{
+	assert(handle && insn && insn->detail && expected);
+	cs_detail *actual = insn->detail;
+
+	if (!test_reg_rw_access(handle, insn, expected)) {
+		return false;
+	}
+
+	if (!test_impl_reg_rw_access(handle, insn, expected)) {
+		return false;
+	}
+
+	if (expected->groups_count > 0) {
+		compare_uint32_ret(actual->groups_count, expected->groups_count,
+				   false);
+		for (size_t i = 0; i < actual->groups_count; ++i) {
+			if (strings_match(cs_group_name(*handle,
+							actual->groups[i]),
+					  expected->groups[i])) {
+				continue;
+			}
+			compare_enum_ret(actual->groups[i], expected->groups[i],
+					 false);
+		}
+	}
+
+	if (expected->aarch64) {
+		return test_expected_aarch64(handle, &actual->aarch64,
+					     expected->aarch64);
+	}
+	if (expected->arm) {
+		return test_expected_arm(handle, &actual->arm, expected->arm);
+	}
+	if (expected->ppc) {
+		return test_expected_ppc(handle, &actual->ppc, expected->ppc);
+	}
+	if (expected->tricore) {
+		return test_expected_tricore(handle, &actual->tricore,
+					     expected->tricore);
+	}
+	if (expected->alpha) {
+		return test_expected_alpha(handle, &actual->alpha,
+					   expected->alpha);
+	}
+	if (expected->bpf) {
+		return test_expected_bpf(handle, &actual->bpf, expected->bpf);
+	}
+	if (expected->hppa) {
+		return test_expected_hppa(handle, &actual->hppa,
+					  expected->hppa);
+	}
+	if (expected->xcore) {
+		return test_expected_xcore(handle, &actual->xcore,
+					   expected->xcore);
+	}
+	if (expected->systemz) {
+		return test_expected_systemz(handle, &actual->sysz,
+					     expected->systemz);
+	}
+	if (expected->sparc) {
+		return test_expected_sparc(handle, &actual->sparc,
+					   expected->sparc);
+	}
+	if (expected->sh) {
+		return test_expected_sh(handle, &actual->sh, expected->sh);
+	}
+	if (expected->mips) {
+		return test_expected_mips(handle, &actual->mips,
+					  expected->mips);
+	}
+	if (expected->riscv) {
+		return test_expected_riscv(handle, &actual->riscv,
+					   expected->riscv);
+	}
+	if (expected->m680x) {
+		return test_expected_m680x(handle, &actual->m680x,
+					   expected->m680x);
+	}
+	if (expected->tms320c64x) {
+		return test_expected_tms320c64x(handle, &actual->tms320c64x,
+						expected->tms320c64x);
+	}
+	if (expected->mos65xx) {
+		return test_expected_mos65xx(handle, &actual->mos65xx,
+					     expected->mos65xx);
+	}
+	if (expected->evm) {
+		return test_expected_evm(handle, &actual->evm, expected->evm);
+	}
+	if (expected->loongarch) {
+		return test_expected_loongarch(handle, &actual->loongarch,
+					       expected->loongarch);
+	}
+	if (expected->wasm) {
+		return test_expected_wasm(handle, &actual->wasm,
+					  expected->wasm);
+	}
+	if (expected->x86) {
+		return test_expected_x86(handle, &actual->x86, expected->x86);
+	}
+	if (expected->m68k) {
+		return test_expected_m68k(handle, &actual->m68k,
+					  expected->m68k);
+	}
+	return true;
+}
diff --git a/suite/cstest/src/test_detail_aarch64.c b/suite/cstest/src/test_detail_aarch64.c
new file mode 100644
index 000000000..d87e1ec77
--- /dev/null
+++ b/suite/cstest/src/test_detail_aarch64.c
@@ -0,0 +1,256 @@
+// Copyright © 2024 Rot127 <unisono@quyllur.org>
+// SPDX-License-Identifier: BSD-3
+
+#include "test_compare.h"
+#include "test_detail_aarch64.h"
+#include <capstone/capstone.h>
+#include <stdio.h>
+#include <string.h>
+
+TestDetailAArch64 *test_detail_aarch64_new()
+{
+	return cs_mem_calloc(sizeof(TestDetailAArch64), 1);
+}
+
+void test_detail_aarch64_free(TestDetailAArch64 *detail)
+{
+	if (!detail) {
+		return;
+	}
+	for (size_t i = 0; i < detail->operands_count; ++i) {
+		test_detail_aarch64_op_free(detail->operands[i]);
+	}
+	cs_mem_free(detail->operands);
+	cs_mem_free(detail->cc);
+	cs_mem_free(detail);
+}
+
+TestDetailAArch64 *test_detail_aarch64_clone(TestDetailAArch64 *detail)
+{
+	TestDetailAArch64 *clone = test_detail_aarch64_new();
+	clone->cc = detail->cc ? strdup(detail->cc) : NULL;
+	clone->update_flags = detail->update_flags;
+	clone->post_indexed = detail->post_indexed;
+
+	clone->operands_count = detail->operands_count;
+	if (detail->operands_count > 0) {
+		clone->operands = cs_mem_calloc(sizeof(TestDetailAArch64Op *),
+						detail->operands_count);
+	}
+	for (size_t i = 0; i < detail->operands_count; ++i) {
+		clone->operands[i] =
+			test_detail_aarch64_op_clone(detail->operands[i]);
+	}
+
+	return clone;
+}
+
+TestDetailAArch64Op *test_detail_aarch64_op_new()
+{
+	return cs_mem_calloc(sizeof(TestDetailAArch64Op), 1);
+}
+
+TestDetailAArch64Op *test_detail_aarch64_op_clone(TestDetailAArch64Op *op)
+{
+	TestDetailAArch64Op *clone = test_detail_aarch64_op_new();
+
+	clone->type = op->type ? strdup(op->type) : NULL;
+	clone->sub_type = op->sub_type ? strdup(op->sub_type) : NULL;
+	clone->access = op->access ? strdup(op->access) : NULL;
+	clone->reg = op->reg ? strdup(op->reg) : NULL;
+	clone->mem_base = op->mem_base ? strdup(op->mem_base) : NULL;
+	clone->mem_index = op->mem_index ? strdup(op->mem_index) : NULL;
+	clone->shift_type = op->shift_type ? strdup(op->shift_type) : NULL;
+	clone->ext = op->ext ? strdup(op->ext) : NULL;
+	clone->vas = op->vas ? strdup(op->vas) : NULL;
+	clone->imm = op->imm;
+	clone->sme = op->sme ? test_detail_aarch64_op_sme_clone(op->sme) : NULL;
+	clone->pred_reg = op->pred_reg ? strdup(op->pred_reg) : NULL;
+	clone->pred_vec_select =
+		op->pred_vec_select ? strdup(op->pred_vec_select) : NULL;
+	clone->pred_imm_index = op->pred_imm_index;
+	clone->pred_imm_index_set = op->pred_imm_index_set;
+	clone->mem_disp = op->mem_disp;
+	clone->imm_range_first = op->imm_range_first;
+	clone->imm_range_offset = op->imm_range_offset;
+	clone->fp = op->fp;
+	clone->sys_raw_val = op->sys_raw_val;
+	clone->shift_value = op->shift_value;
+	clone->is_vreg = op->is_vreg;
+	clone->vector_index = op->vector_index;
+	clone->vector_index_is_set = op->vector_index_is_set;
+	clone->is_list_member = op->is_list_member;
+
+	return clone;
+}
+
+void test_detail_aarch64_op_free(TestDetailAArch64Op *op)
+{
+	if (!op) {
+		return;
+	}
+	test_detail_aarch64_op_sme_free(op->sme);
+	cs_mem_free(op->type);
+	cs_mem_free(op->sub_type);
+	cs_mem_free(op->access);
+	cs_mem_free(op->reg);
+	cs_mem_free(op->mem_base);
+	cs_mem_free(op->mem_index);
+	cs_mem_free(op->shift_type);
+	cs_mem_free(op->ext);
+	cs_mem_free(op->vas);
+	cs_mem_free(op->pred_reg);
+	cs_mem_free(op->pred_vec_select);
+	cs_mem_free(op);
+}
+
+TestDetailAArch64SME *test_detail_aarch64_op_sme_new()
+{
+	return cs_mem_calloc(sizeof(TestDetailAArch64SME), 1);
+}
+
+TestDetailAArch64SME *test_detail_aarch64_op_sme_clone(TestDetailAArch64SME *sme)
+{
+	TestDetailAArch64SME *clone = test_detail_aarch64_op_sme_new();
+
+	clone->type = sme->type ? strdup(sme->type) : NULL;
+	clone->tile = sme->tile ? strdup(sme->tile) : NULL;
+	clone->slice_reg = sme->slice_reg ? strdup(sme->slice_reg) : NULL;
+	clone->slice_offset_imm = sme->slice_offset_imm;
+	clone->slice_offset_ir_first = sme->slice_offset_ir_first;
+	clone->slice_offset_ir_offset = sme->slice_offset_ir_offset;
+	clone->slice_offset_ir_set = sme->slice_offset_ir_set;
+	clone->has_range_offset = sme->has_range_offset;
+	clone->is_vertical = sme->is_vertical;
+
+	return clone;
+}
+
+void test_detail_aarch64_op_sme_free(TestDetailAArch64SME *sme)
+{
+	if (!sme) {
+		return;
+	}
+	cs_mem_free(sme->type);
+	cs_mem_free(sme->tile);
+	cs_mem_free(sme->slice_reg);
+	cs_mem_free(sme);
+}
+
+bool test_expected_aarch64(csh *handle, cs_aarch64 *actual,
+			   TestDetailAArch64 *expected)
+{
+	assert(handle && actual && expected);
+
+	compare_enum_ret(actual->cc, expected->cc, false);
+	compare_tbool_ret(actual->update_flags, expected->update_flags, false);
+	compare_tbool_ret(actual->post_index, expected->post_indexed, false);
+
+	if (expected->operands_count == 0) {
+		return true;
+	}
+	compare_uint8_ret(actual->op_count, expected->operands_count, false);
+	for (size_t i = 0; i < actual->op_count; ++i) {
+		cs_aarch64_op *op = &actual->operands[i];
+		TestDetailAArch64Op *eop = expected->operands[i];
+		compare_enum_ret(op->type, eop->type, false);
+		compare_enum_ret(op->access, eop->access, false);
+		switch (op->type) {
+		default:
+			fprintf(stderr,
+				"AArch64 op type %" PRId32 " not handled.\n",
+				op->type);
+			return false;
+		case AARCH64_OP_REG:
+			compare_reg_ret(*handle, op->reg, eop->reg, false);
+			break;
+		case AARCH64_OP_IMM:
+			compare_int64_ret(op->imm, eop->imm, false);
+			break;
+		case AARCH64_OP_IMM_RANGE:
+			compare_int8_ret(op->imm_range.first,
+					 eop->imm_range_first, false);
+			compare_int8_ret(op->imm_range.offset,
+					 eop->imm_range_offset, false);
+			break;
+		case AARCH64_OP_FP:
+			compare_fp_ret(op->fp, eop->fp, false);
+			break;
+		case AARCH64_OP_SYSREG:
+			compare_enum_ret(op->sysop.sub_type, eop->sub_type,
+					 false);
+			compare_uint64_ret(op->sysop.reg.raw_val,
+					   eop->sys_raw_val, false);
+			break;
+		case AARCH64_OP_SYSIMM:
+			compare_enum_ret(op->sysop.sub_type, eop->sub_type,
+					 false);
+			compare_uint64_ret(op->sysop.imm.raw_val,
+					   eop->sys_raw_val, false);
+			break;
+		case AARCH64_OP_SYSALIAS:
+			compare_enum_ret(op->sysop.sub_type, eop->sub_type,
+					 false);
+			compare_uint64_ret(op->sysop.alias.raw_val,
+					   eop->sys_raw_val, false);
+			break;
+		case AARCH64_OP_MEM:
+			compare_reg_ret(*handle, op->mem.base, eop->mem_base,
+					false);
+			compare_reg_ret(*handle, op->mem.index, eop->mem_index,
+					false);
+			compare_int32_ret(op->mem.disp, eop->mem_disp, false);
+			break;
+		case AARCH64_OP_PRED:
+			compare_reg_ret(*handle, op->pred.reg, eop->pred_reg,
+					false);
+			compare_reg_ret(*handle, op->pred.vec_select, eop->pred_vec_select,
+					false);
+			if (eop->pred_imm_index_set) {
+				compare_int32_ret(op->pred.imm_index, eop->pred_imm_index, false);
+			} else {
+				assert(eop->pred_imm_index == 0);
+			}
+			break;
+		case AARCH64_OP_SME:
+			compare_enum_ret(op->sme.type, eop->sme->type,
+					false);
+			compare_reg_ret(*handle, op->sme.tile, eop->sme->tile,
+					false);
+			compare_reg_ret(*handle, op->sme.slice_reg, eop->sme->slice_reg,
+					false);
+			compare_tbool_ret(op->sme.has_range_offset, eop->sme->has_range_offset,
+					false);
+			compare_tbool_ret(op->sme.is_vertical, eop->sme->is_vertical,
+					false);
+			if (eop->sme->slice_offset_imm) {
+				compare_int32_ret(op->sme.slice_offset.imm, eop->sme->slice_offset_imm, false);
+			}
+			if (eop->sme->slice_offset_ir_set) {
+				compare_int32_ret(op->sme.slice_offset.imm_range.first, eop->sme->slice_offset_ir_first, false);
+				compare_int32_ret(op->sme.slice_offset.imm_range.offset, eop->sme->slice_offset_ir_offset, false);
+			} else {
+				assert(eop->sme->slice_offset_ir_first == 0 && eop->sme->slice_offset_ir_offset == 0);
+			}
+			break;
+		}
+
+		compare_enum_ret(op->shift.type, eop->shift_type, false);
+		compare_uint32_ret(op->shift.value, eop->shift_value, false);
+		compare_enum_ret(op->ext, eop->ext, false);
+
+		compare_enum_ret(op->vas, eop->vas, false);
+		compare_tbool_ret(op->is_vreg, eop->is_vreg, false);
+		if (eop->vector_index_is_set) {
+			compare_int32_ret(op->vector_index, eop->vector_index,
+					  false);
+		} else {
+			assert(eop->vector_index == 0);
+		}
+
+		compare_tbool_ret(op->is_list_member, eop->is_list_member,
+				  false);
+	}
+
+	return true;
+}
diff --git a/suite/cstest/src/test_detail_alpha.c b/suite/cstest/src/test_detail_alpha.c
new file mode 100644
index 000000000..0fce65a27
--- /dev/null
+++ b/suite/cstest/src/test_detail_alpha.c
@@ -0,0 +1,99 @@
+// Copyright © 2024 Rot127 <unisono@quyllur.org>
+// SPDX-License-Identifier: BSD-3
+
+#include "test_compare.h"
+#include "test_detail_alpha.h"
+#include <capstone/capstone.h>
+#include <stdio.h>
+#include <string.h>
+
+TestDetailAlpha *test_detail_alpha_new()
+{
+	return cs_mem_calloc(sizeof(TestDetailAlpha), 1);
+}
+
+void test_detail_alpha_free(TestDetailAlpha *detail)
+{
+	if (!detail) {
+		return;
+	}
+	for (size_t i = 0; i < detail->operands_count; ++i) {
+		test_detail_alpha_op_free(detail->operands[i]);
+	}
+	cs_mem_free(detail->operands);
+	cs_mem_free(detail);
+}
+
+TestDetailAlpha *test_detail_alpha_clone(const TestDetailAlpha *detail)
+{
+	TestDetailAlpha *clone = test_detail_alpha_new();
+
+	clone->operands_count = detail->operands_count;
+	if (detail->operands_count > 0) {
+		clone->operands = cs_mem_calloc(sizeof(TestDetailAlphaOp *),
+						detail->operands_count);
+	}
+	for (size_t i = 0; i < detail->operands_count; ++i) {
+		clone->operands[i] =
+			test_detail_alpha_op_clone(detail->operands[i]);
+	}
+
+	return clone;
+}
+
+TestDetailAlphaOp *test_detail_alpha_op_new()
+{
+	return cs_mem_calloc(sizeof(TestDetailAlphaOp), 1);
+}
+
+TestDetailAlphaOp *test_detail_alpha_op_clone(const TestDetailAlphaOp *op)
+{
+	TestDetailAlphaOp *clone = test_detail_alpha_op_new();
+
+	clone->type = op->type ? strdup(op->type) : NULL;
+	clone->access = op->access ? strdup(op->access) : NULL;
+	clone->reg = op->reg ? strdup(op->reg) : NULL;
+	clone->imm = op->imm;
+
+	return clone;
+}
+
+void test_detail_alpha_op_free(TestDetailAlphaOp *op)
+{
+	if (!op) {
+		return;
+	}
+	cs_mem_free(op->type);
+	cs_mem_free(op->access);
+	cs_mem_free(op->reg);
+	cs_mem_free(op);
+}
+
+bool test_expected_alpha(csh *handle, const cs_alpha *actual,
+			 const TestDetailAlpha *expected)
+{
+	assert(handle && actual && expected);
+
+	compare_uint8_ret(actual->op_count, expected->operands_count, false);
+	for (size_t i = 0; i < actual->op_count; ++i) {
+		const cs_alpha_op *op = &actual->operands[i];
+		TestDetailAlphaOp *eop = expected->operands[i];
+		compare_enum_ret(op->type, eop->type, false);
+		compare_enum_ret(op->access, eop->access, false);
+		switch (op->type) {
+		default:
+			fprintf(stderr,
+				"alpha op type %" PRId32 " not handled.\n",
+				op->type);
+			return false;
+		case ALPHA_OP_REG:
+			compare_reg_ret(*handle, op->reg, eop->reg, false);
+			break;
+		case ALPHA_OP_IMM:
+			compare_int32_ret(op->imm, eop->imm, false);
+			break;
+		}
+	}
+
+	return true;
+}
diff --git a/suite/cstest/src/test_detail_arm.c b/suite/cstest/src/test_detail_arm.c
new file mode 100644
index 000000000..090cafeaa
--- /dev/null
+++ b/suite/cstest/src/test_detail_arm.c
@@ -0,0 +1,256 @@
+// Copyright © 2024 Rot127 <unisono@quyllur.org>
+// SPDX-License-Identifier: BSD-3
+
+#include "test_compare.h"
+#include "test_detail_arm.h"
+#include <capstone/capstone.h>
+#include <stdio.h>
+#include <string.h>
+
+TestDetailARM *test_detail_arm_new()
+{
+	return cs_mem_calloc(sizeof(TestDetailARM), 1);
+}
+
+void test_detail_arm_free(TestDetailARM *detail)
+{
+	if (!detail) {
+		return;
+	}
+	for (size_t i = 0; i < detail->operands_count; ++i) {
+		test_detail_arm_op_free(detail->operands[i]);
+	}
+	cs_mem_free(detail->operands);
+	cs_mem_free(detail->vector_data);
+	cs_mem_free(detail->cps_mode);
+	cs_mem_free(detail->cps_flag);
+	cs_mem_free(detail->cc);
+	cs_mem_free(detail->vcc);
+	cs_mem_free(detail->mem_barrier);
+	cs_mem_free(detail);
+}
+
+TestDetailARM *test_detail_arm_clone(TestDetailARM *detail)
+{
+	TestDetailARM *clone = test_detail_arm_new();
+	clone->update_flags = detail->update_flags;
+	clone->post_indexed = detail->post_indexed;
+	clone->vector_data = detail->vector_data ? strdup(detail->vector_data) : NULL;
+	clone->cps_mode = detail->cps_mode ? strdup(detail->cps_mode) : NULL;
+	clone->cps_flag = detail->cps_flag ? strdup(detail->cps_flag) : NULL;
+	clone->cc = detail->cc ? strdup(detail->cc) : NULL;
+	clone->vcc = detail->vcc ? strdup(detail->vcc) : NULL;
+	clone->mem_barrier = detail->mem_barrier ? strdup(detail->mem_barrier) : NULL;
+
+	clone->operands_count = detail->operands_count;
+	if (detail->operands_count > 0) {
+		clone->operands = cs_mem_calloc(sizeof(TestDetailARMOp *),
+						detail->operands_count);
+	}
+	for (size_t i = 0; i < detail->operands_count; ++i) {
+		clone->operands[i] =
+			test_detail_arm_op_clone(detail->operands[i]);
+	}
+
+	return clone;
+}
+
+TestDetailARMOp *test_detail_arm_op_new()
+{
+	return cs_mem_calloc(sizeof(TestDetailARMOp), 1);
+}
+
+TestDetailARMOp *test_detail_arm_op_clone(TestDetailARMOp *op)
+{
+	TestDetailARMOp *clone = test_detail_arm_op_new();
+
+	clone->type = op->type ? strdup(op->type) : NULL;
+	clone->access = op->access ? strdup(op->access) : NULL;
+	clone->reg = op->reg ? strdup(op->reg) : NULL;
+	clone->imm = op->imm;
+	clone->setend = op->setend ? strdup(op->setend) : NULL;
+	clone->pred = op->pred;
+	clone->fp = op->fp;
+	clone->mem_base = op->mem_base ? strdup(op->mem_base) : NULL;
+	clone->mem_index = op->mem_index ? strdup(op->mem_index) : NULL;
+	clone->mem_scale = op->mem_scale;
+	clone->mem_disp = op->mem_disp;
+	clone->mem_align = op->mem_align;
+	clone->sys_reg = op->sys_reg ? strdup(op->sys_reg) : NULL;
+	clone->sys_psr_bits_count = op->sys_psr_bits_count;
+	clone->sys_psr_bits =
+		op->sys_psr_bits_count == 0 ?
+			NULL :
+			cs_mem_calloc(sizeof(char *), op->sys_psr_bits_count);
+	for (size_t i = 0; i < op->sys_psr_bits_count; ++i) {
+		clone->sys_psr_bits[i] = strdup(op->sys_psr_bits[i]);
+	}
+	clone->sys_sysm = op->sys_sysm;
+	clone->sys_msr_mask = op->sys_msr_mask;
+	clone->shift_type = op->shift_type ? strdup(op->shift_type) : NULL;
+	clone->shift_value = op->shift_value;
+	clone->neon_lane = op->neon_lane;
+	clone->vector_index = op->vector_index;
+	clone->vector_index_is_set = op->vector_index_is_set;
+	clone->subtracted = op->subtracted;
+
+	return clone;
+}
+
+void test_detail_arm_op_free(TestDetailARMOp *op)
+{
+	if (!op) {
+		return;
+	}
+	cs_mem_free(op->type);
+	cs_mem_free(op->access);
+	cs_mem_free(op->reg);
+	cs_mem_free(op->setend);
+	cs_mem_free(op->mem_base);
+	cs_mem_free(op->mem_index);
+	cs_mem_free(op->shift_type);
+	cs_mem_free(op->sys_reg);
+	if (op->sys_psr_bits_count != 0) {
+		for (size_t i = 0; i < op->sys_psr_bits_count; ++i) {
+			cs_mem_free(op->sys_psr_bits[i]);
+		}
+		cs_mem_free(op->sys_psr_bits);
+	}
+	cs_mem_free(op);
+}
+
+bool test_expected_arm(csh *handle, cs_arm *actual, TestDetailARM *expected)
+{
+	assert(handle && actual && expected);
+
+	if (expected->vector_size) {
+		compare_int_ret(actual->vector_size, expected->vector_size,
+				false);
+	}
+	compare_enum_ret(actual->vector_data, expected->vector_data, false);
+	compare_enum_ret(actual->cps_flag, expected->cps_flag, false);
+	compare_enum_ret(actual->cps_mode, expected->cps_mode, false);
+	compare_enum_ret(actual->cc, expected->cc, false);
+	compare_enum_ret(actual->vcc, expected->vcc, false);
+	compare_enum_ret(actual->mem_barrier, expected->mem_barrier, false);
+	if (expected->pred_mask) {
+		compare_uint8_ret(actual->pred_mask, expected->pred_mask,
+				  false);
+	}
+	compare_tbool_ret(actual->usermode, expected->usermode, false);
+	compare_tbool_ret(actual->update_flags, expected->update_flags, false);
+	compare_tbool_ret(actual->post_index, expected->post_indexed, false);
+
+	if (expected->operands_count == 0) {
+		return true;
+	}
+	compare_uint8_ret(actual->op_count, expected->operands_count, false);
+	for (size_t i = 0; i < actual->op_count; ++i) {
+		cs_arm_op *op = &actual->operands[i];
+		TestDetailARMOp *eop = expected->operands[i];
+		compare_enum_ret(op->type, eop->type, false);
+		compare_enum_ret(op->access, eop->access, false);
+		switch (op->type) {
+		default:
+			fprintf(stderr,
+				"arm op type %" PRId32 " not handled.\n",
+				op->type);
+			return false;
+		case ARM_OP_REG:
+			compare_reg_ret(*handle, op->reg, eop->reg, false);
+			break;
+		case ARM_OP_IMM:
+		case ARM_OP_PIMM:
+		case ARM_OP_CIMM:
+			compare_int64_ret(op->imm, eop->imm, false);
+			break;
+		case ARM_OP_PRED:
+			compare_int_ret(op->pred, eop->pred, false);
+			break;
+		case ARM_OP_SETEND:
+			compare_enum_ret(op->setend, eop->setend, false);
+			break;
+		case ARM_OP_FP:
+			compare_fp_ret(op->fp, eop->fp, false);
+			break;
+		case ARM_OP_SYSREG:
+			compare_enum_ret(op->sysop.reg.mclasssysreg,
+					 eop->sys_reg, false);
+			if (eop->sys_sysm) {
+				compare_uint16_ret(op->sysop.sysm,
+						   eop->sys_sysm, false);
+			}
+			if (eop->sys_msr_mask) {
+				compare_uint8_ret(op->sysop.msr_mask,
+						  eop->sys_msr_mask, false);
+			}
+			break;
+		case ARM_OP_BANKEDREG:
+			compare_enum_ret(op->sysop.reg.bankedreg, eop->sys_reg,
+					 false);
+			if (eop->sys_sysm) {
+				compare_uint16_ret(op->sysop.sysm,
+						   eop->sys_sysm, false);
+			}
+			if (eop->sys_msr_mask) {
+				compare_uint8_ret(op->sysop.msr_mask,
+						  eop->sys_msr_mask, false);
+			}
+			break;
+		case ARM_OP_SPSR:
+		case ARM_OP_CPSR:
+			compare_bit_flags_ret(op->sysop.psr_bits,
+					      eop->sys_psr_bits,
+					      eop->sys_psr_bits_count, false);
+			if (eop->sys_sysm) {
+				compare_uint16_ret(op->sysop.sysm,
+						   eop->sys_sysm, false);
+			}
+			if (eop->sys_msr_mask) {
+				compare_uint8_ret(op->sysop.msr_mask,
+						  eop->sys_msr_mask, false);
+			}
+			break;
+		case ARM_OP_SYSM:
+			if (eop->sys_sysm) {
+				compare_uint16_ret(op->sysop.sysm,
+						   eop->sys_sysm, false);
+			}
+			if (eop->sys_msr_mask) {
+				compare_uint8_ret(op->sysop.msr_mask,
+						  eop->sys_msr_mask, false);
+			}
+			break;
+		case ARM_OP_MEM:
+			compare_reg_ret(*handle, op->mem.base, eop->mem_base,
+					false);
+			compare_reg_ret(*handle, op->mem.index, eop->mem_index,
+					false);
+			compare_int_ret(op->mem.disp, eop->mem_disp, false);
+			compare_uint_ret(op->mem.align, eop->mem_align, false);
+			if (eop->mem_scale) {
+				compare_int_ret(op->mem.scale, eop->mem_scale, false);
+			}
+			break;
+		}
+
+		compare_enum_ret(op->shift.type, eop->shift_type, false);
+		if (eop->shift_value) {
+			compare_uint32_ret(op->shift.value, eop->shift_value,
+					   false);
+		}
+		if (eop->neon_lane) {
+			compare_uint8_ret(op->neon_lane, eop->neon_lane, false);
+		}
+
+		if (eop->vector_index_is_set) {
+			compare_int32_ret(op->vector_index, eop->vector_index,
+					  false);
+		} else {
+			assert(eop->vector_index == 0);
+		}
+		compare_tbool_ret(op->subtracted, eop->subtracted, false);
+	}
+
+	return true;
+}
diff --git a/suite/cstest/src/test_detail_bpf.c b/suite/cstest/src/test_detail_bpf.c
new file mode 100644
index 000000000..e84ee541b
--- /dev/null
+++ b/suite/cstest/src/test_detail_bpf.c
@@ -0,0 +1,125 @@
+// Copyright © 2024 Rot127 <unisono@quyllur.org>
+// SPDX-License-Identifier: BSD-3
+
+#include "capstone/bpf.h"
+#include "test_compare.h"
+#include "test_detail_bpf.h"
+#include <capstone/capstone.h>
+#include <stdio.h>
+#include <string.h>
+
+TestDetailBPF *test_detail_bpf_new()
+{
+	return cs_mem_calloc(sizeof(TestDetailBPF), 1);
+}
+
+void test_detail_bpf_free(TestDetailBPF *detail)
+{
+	if (!detail) {
+		return;
+	}
+	for (size_t i = 0; i < detail->operands_count; ++i) {
+		test_detail_bpf_op_free(detail->operands[i]);
+	}
+	cs_mem_free(detail->operands);
+	cs_mem_free(detail);
+}
+
+TestDetailBPF *test_detail_bpf_clone(const TestDetailBPF *detail)
+{
+	TestDetailBPF *clone = test_detail_bpf_new();
+
+	clone->operands_count = detail->operands_count;
+	if (detail->operands_count > 0) {
+		clone->operands = cs_mem_calloc(sizeof(TestDetailBPFOp *),
+						detail->operands_count);
+	}
+	for (size_t i = 0; i < detail->operands_count; ++i) {
+		clone->operands[i] =
+			test_detail_bpf_op_clone(detail->operands[i]);
+	}
+
+	return clone;
+}
+
+TestDetailBPFOp *test_detail_bpf_op_new()
+{
+	return cs_mem_calloc(sizeof(TestDetailBPFOp), 1);
+}
+
+TestDetailBPFOp *test_detail_bpf_op_clone(const TestDetailBPFOp *op)
+{
+	TestDetailBPFOp *clone = test_detail_bpf_op_new();
+
+	clone->type = op->type ? strdup(op->type) : NULL;
+	clone->access = op->access ? strdup(op->access) : NULL;
+	clone->reg = op->reg ? strdup(op->reg) : NULL;
+	clone->imm = op->imm;
+	clone->off = op->off;
+	clone->mmem = op->mmem;
+	clone->msh = op->msh;
+	clone->ext = op->ext ? strdup(op->ext) : NULL;
+	clone->mem_base = op->mem_base ? strdup(op->mem_base) : NULL;
+	clone->mem_disp = op->mem_disp;
+
+	return clone;
+}
+
+void test_detail_bpf_op_free(TestDetailBPFOp *op)
+{
+	if (!op) {
+		return;
+	}
+	cs_mem_free(op->type);
+	cs_mem_free(op->access);
+	cs_mem_free(op->reg);
+	cs_mem_free(op->ext);
+	cs_mem_free(op->mem_base);
+	cs_mem_free(op);
+}
+
+bool test_expected_bpf(csh *handle, const cs_bpf *actual,
+		       const TestDetailBPF *expected)
+{
+	assert(handle && actual && expected);
+
+	compare_uint8_ret(actual->op_count, expected->operands_count, false);
+	for (size_t i = 0; i < actual->op_count; ++i) {
+		const cs_bpf_op *op = &actual->operands[i];
+		TestDetailBPFOp *eop = expected->operands[i];
+		compare_enum_ret(op->type, eop->type, false);
+		compare_enum_ret(op->access, eop->access, false);
+		switch (op->type) {
+		default:
+			fprintf(stderr,
+				"bpf op type %" PRId32 " not handled.\n",
+				op->type);
+			return false;
+		case BPF_OP_REG:
+			compare_reg_ret(*handle, op->reg, eop->reg, false);
+			break;
+		case BPF_OP_IMM:
+			compare_uint64_ret(op->imm, eop->imm, false);
+			break;
+		case BPF_OP_OFF:
+			compare_uint32_ret(op->off, eop->off, false);
+			break;
+		case BPF_OP_MMEM:
+			compare_uint32_ret(op->mmem, eop->mmem, false);
+			break;
+		case BPF_OP_MSH:
+			compare_uint32_ret(op->msh, eop->msh, false);
+			break;
+		case BPF_OP_EXT:
+			compare_enum_ret(op->ext, eop->ext, false);
+			break;
+		case BPF_OP_MEM:
+			compare_reg_ret(*handle, op->mem.base, eop->mem_base,
+					false);
+			compare_uint32_ret(op->mem.disp, eop->mem_disp, false);
+			break;
+		}
+	}
+
+	return true;
+}
diff --git a/suite/cstest/src/test_detail_evm.c b/suite/cstest/src/test_detail_evm.c
new file mode 100644
index 000000000..53a14da2a
--- /dev/null
+++ b/suite/cstest/src/test_detail_evm.c
@@ -0,0 +1,40 @@
+// Copyright © 2024 Rot127 <unisono@quyllur.org>
+// SPDX-License-Identifier: BSD-3
+
+#include "test_compare.h"
+#include "test_detail_evm.h"
+#include <capstone/capstone.h>
+
+TestDetailEVM *test_detail_evm_new()
+{
+	return cs_mem_calloc(sizeof(TestDetailEVM), 1);
+}
+
+void test_detail_evm_free(TestDetailEVM *detail)
+{
+	if (!detail) {
+		return;
+	}
+	cs_mem_free(detail);
+}
+
+TestDetailEVM *test_detail_evm_clone(const TestDetailEVM *detail)
+{
+	TestDetailEVM *clone = test_detail_evm_new();
+	clone->fee = detail->fee;
+	clone->pop = detail->pop;
+	clone->push = detail->push;
+	return clone;
+}
+
+bool test_expected_evm(csh *handle, const cs_evm *actual,
+		       const TestDetailEVM *expected)
+{
+	assert(handle && actual && expected);
+
+	compare_uint8_ret(actual->fee, expected->fee, false);
+	compare_uint8_ret(actual->pop, expected->pop, false);
+	compare_uint8_ret(actual->push, expected->push, false);
+
+	return true;
+}
diff --git a/suite/cstest/src/test_detail_hppa.c b/suite/cstest/src/test_detail_hppa.c
new file mode 100644
index 000000000..6a9a1410e
--- /dev/null
+++ b/suite/cstest/src/test_detail_hppa.c
@@ -0,0 +1,118 @@
+// Copyright © 2024 Rot127 <unisono@quyllur.org>
+// SPDX-License-Identifier: BSD-3
+
+#include "capstone/hppa.h"
+#include "test_compare.h"
+#include "test_detail_hppa.h"
+#include <capstone/capstone.h>
+#include <stdio.h>
+#include <string.h>
+
+TestDetailHPPA *test_detail_hppa_new()
+{
+	return cs_mem_calloc(sizeof(TestDetailHPPA), 1);
+}
+
+void test_detail_hppa_free(TestDetailHPPA *detail)
+{
+	if (!detail) {
+		return;
+	}
+	for (size_t i = 0; i < detail->operands_count; ++i) {
+		test_detail_hppa_op_free(detail->operands[i]);
+	}
+	cs_mem_free(detail->operands);
+	cs_mem_free(detail);
+}
+
+TestDetailHPPA *test_detail_hppa_clone(const TestDetailHPPA *detail)
+{
+	TestDetailHPPA *clone = test_detail_hppa_new();
+
+	clone->operands_count = detail->operands_count;
+	if (detail->operands_count > 0) {
+		clone->operands = cs_mem_calloc(sizeof(TestDetailHPPAOp *),
+						detail->operands_count);
+	}
+	for (size_t i = 0; i < detail->operands_count; ++i) {
+		clone->operands[i] =
+			test_detail_hppa_op_clone(detail->operands[i]);
+	}
+
+	return clone;
+}
+
+TestDetailHPPAOp *test_detail_hppa_op_new()
+{
+	return cs_mem_calloc(sizeof(TestDetailHPPAOp), 1);
+}
+
+TestDetailHPPAOp *test_detail_hppa_op_clone(const TestDetailHPPAOp *op)
+{
+	TestDetailHPPAOp *clone = test_detail_hppa_op_new();
+
+	clone->type = op->type ? strdup(op->type) : NULL;
+	clone->access = op->access ? strdup(op->access) : NULL;
+	clone->reg = op->reg ? strdup(op->reg) : NULL;
+	clone->imm = op->imm;
+	clone->mem_base = op->mem_base ? strdup(op->mem_base) : NULL;
+	clone->mem_space = op->mem_space ? strdup(op->mem_space) : NULL;
+	clone->mem_base_access =
+		op->mem_base_access ? strdup(op->mem_base_access) : NULL;
+
+	return clone;
+}
+
+void test_detail_hppa_op_free(TestDetailHPPAOp *op)
+{
+	if (!op) {
+		return;
+	}
+	cs_mem_free(op->type);
+	cs_mem_free(op->access);
+	cs_mem_free(op->reg);
+	cs_mem_free(op->mem_base);
+	cs_mem_free(op->mem_base_access);
+	cs_mem_free(op->mem_space);
+	cs_mem_free(op);
+}
+
+bool test_expected_hppa(csh *handle, const cs_hppa *actual,
+			const TestDetailHPPA *expected)
+{
+	assert(handle && actual && expected);
+
+	compare_uint8_ret(actual->op_count, expected->operands_count, false);
+	for (size_t i = 0; i < actual->op_count; ++i) {
+		const cs_hppa_op *op = &actual->operands[i];
+		TestDetailHPPAOp *eop = expected->operands[i];
+		compare_enum_ret(op->type, eop->type, false);
+		compare_enum_ret(op->access, eop->access, false);
+		switch (op->type) {
+		default:
+			fprintf(stderr,
+				"hppa op type %" PRId32 " not handled.\n",
+				op->type);
+			return false;
+		case HPPA_OP_REG:
+		case HPPA_OP_IDX_REG:
+			compare_reg_ret(*handle, op->reg, eop->reg, false);
+			break;
+		case HPPA_OP_DISP:
+		case HPPA_OP_IMM:
+		case HPPA_OP_TARGET:
+			compare_int64_ret(op->imm, eop->imm, false);
+			break;
+		case HPPA_OP_MEM:
+			compare_reg_ret(*handle, op->mem.base, eop->mem_base,
+					false);
+			compare_reg_ret(*handle, op->mem.space, eop->mem_space,
+					false);
+			compare_enum_ret(op->mem.base_access,
+					 eop->mem_base_access, false);
+			break;
+		}
+	}
+
+	return true;
+}
diff --git a/suite/cstest/src/test_detail_loongarch.c b/suite/cstest/src/test_detail_loongarch.c
new file mode 100644
index 000000000..3a86bbcf6
--- /dev/null
+++ b/suite/cstest/src/test_detail_loongarch.c
@@ -0,0 +1,114 @@
+// Copyright © 2024 Rot127 <unisono@quyllur.org>
+// SPDX-License-Identifier: BSD-3
+
+#include "test_compare.h"
+#include "test_detail_loongarch.h"
+#include <capstone/capstone.h>
+#include <stdio.h>
+#include <string.h>
+
+TestDetailLoongArch *test_detail_loongarch_new()
+{
+	return cs_mem_calloc(sizeof(TestDetailLoongArch), 1);
+}
+
+void test_detail_loongarch_free(TestDetailLoongArch *detail)
+{
+	if (!detail) {
+		return;
+	}
+	for (size_t i = 0; i < detail->operands_count; ++i) {
+		test_detail_loongarch_op_free(detail->operands[i]);
+	}
+	cs_mem_free(detail->operands);
+	cs_mem_free(detail->format);
+	cs_mem_free(detail);
+}
+
+TestDetailLoongArch *
+test_detail_loongarch_clone(const TestDetailLoongArch *detail)
+{
+	TestDetailLoongArch *clone = test_detail_loongarch_new();
+
+	clone->format = detail->format ? strdup(detail->format) : NULL;
+	clone->operands_count = detail->operands_count;
+	if (detail->operands_count > 0) {
+		clone->operands = cs_mem_calloc(sizeof(TestDetailLoongArchOp *),
+						detail->operands_count);
+	}
+	for (size_t i = 0; i < detail->operands_count; ++i) {
+		clone->operands[i] =
+			test_detail_loongarch_op_clone(detail->operands[i]);
+	}
+
+	return clone;
+}
+
+TestDetailLoongArchOp *test_detail_loongarch_op_new()
+{
+	return cs_mem_calloc(sizeof(TestDetailLoongArchOp), 1);
+}
+
+TestDetailLoongArchOp *
+test_detail_loongarch_op_clone(const TestDetailLoongArchOp *op)
+{
+	TestDetailLoongArchOp *clone = test_detail_loongarch_op_new();
+
+	clone->type = op->type ? strdup(op->type) : NULL;
+	clone->access = op->access ? strdup(op->access) : NULL;
+	clone->reg = op->reg ? strdup(op->reg) : NULL;
+	clone->imm = op->imm;
+	clone->mem_base = op->mem_base ? strdup(op->mem_base) : NULL;
+	clone->mem_disp = op->mem_disp;
+
+	return clone;
+}
+
+void test_detail_loongarch_op_free(TestDetailLoongArchOp *op)
+{
+	if (!op) {
+		return;
+	}
+	cs_mem_free(op->type);
+	cs_mem_free(op->access);
+	cs_mem_free(op->reg);
+	cs_mem_free(op->mem_base);
+	cs_mem_free(op);
+}
+
+bool test_expected_loongarch(csh *handle, const cs_loongarch *actual,
+			     const TestDetailLoongArch *expected)
+{
+	assert(handle && actual && expected);
+
+	compare_uint8_ret(actual->op_count, expected->operands_count, false);
+	compare_enum_ret(actual->format, expected->format, false);
+	for (size_t i = 0; i < actual->op_count; ++i) {
+		const cs_loongarch_op *op = &actual->operands[i];
+		TestDetailLoongArchOp *eop = expected->operands[i];
+		compare_enum_ret(op->type, eop->type, false);
+		compare_enum_ret(op->access, eop->access, false);
+		switch (op->type) {
+		default:
+			fprintf(stderr,
+				"loongarch op type %" PRId32 " not handled.\n",
+				op->type);
+			return false;
+		case LOONGARCH_OP_REG:
+			compare_reg_ret(*handle, op->reg, eop->reg, false);
+			break;
+		case LOONGARCH_OP_IMM:
+			compare_uint64_ret(op->imm, eop->imm, false);
+			break;
+		case LOONGARCH_OP_MEM:
+			compare_reg_ret(*handle, op->mem.base, eop->mem_base,
+					false);
+			compare_reg_ret(*handle, op->mem.index, eop->mem_index,
+					false);
+			compare_int64_ret(op->mem.disp, eop->mem_disp, false);
+			break;
+		}
+	}
+
+	return true;
+}
diff --git a/suite/cstest/src/test_detail_m680x.c b/suite/cstest/src/test_detail_m680x.c
new file mode 100644
index 000000000..c2d748ff4
--- /dev/null
+++ b/suite/cstest/src/test_detail_m680x.c
@@ -0,0 +1,215 @@
+// Copyright © 2024 Rot127 <unisono@quyllur.org>
+// SPDX-License-Identifier: BSD-3
+
+#include "test_compare.h"
+#include "test_detail_m680x.h"
+#include <capstone/capstone.h>
+#include <stdio.h>
+#include <string.h>
+
+TestDetailM680xIdx *test_detail_m680x_idx_new()
+{
+	return cs_mem_calloc(sizeof(TestDetailM680xIdx), 1);
+}
+
+TestDetailM680xIdx *test_detail_m680x_idx_clone(const TestDetailM680xIdx *idx)
+{
+	assert(idx);
+	TestDetailM680xIdx *clone = test_detail_m680x_idx_new();
+	clone->base_reg = idx->base_reg ? strdup(idx->base_reg) : NULL;
+	clone->offset_reg = idx->offset_reg ? strdup(idx->offset_reg) : NULL;
+	clone->flags = idx->flags_count > 0 ?
+			       cs_mem_calloc(sizeof(char *), idx->flags_count) :
+			       NULL;
+	clone->flags_count = idx->flags_count;
+	for (size_t i = 0; i < clone->flags_count; ++i) {
+		clone->flags[i] = idx->flags[i] ? strdup(idx->flags[i]) : NULL;
+	}
+	clone->offset = idx->offset;
+	clone->offset_addr = idx->offset_addr;
+	clone->offset_bits = idx->offset_bits;
+	clone->inc_dec = idx->inc_dec;
+	return clone;
+}
+
+void test_detail_m680x_idx_free(TestDetailM680xIdx *idx)
+{
+	if (!idx) {
+		return;
+	}
+	cs_mem_free(idx->base_reg);
+	cs_mem_free(idx->offset_reg);
+	for (size_t i = 0; i < idx->flags_count; ++i) {
+		cs_mem_free(idx->flags[i]);
+	}
+	cs_mem_free(idx->flags);
+	cs_mem_free(idx);
+}
+
+TestDetailM680x *test_detail_m680x_new()
+{
+	return cs_mem_calloc(sizeof(TestDetailM680x), 1);
+}
+
+void test_detail_m680x_free(TestDetailM680x *detail)
+{
+	if (!detail) {
+		return;
+	}
+	for (size_t i = 0; i < detail->operands_count; ++i) {
+		test_detail_m680x_op_free(detail->operands[i]);
+	}
+	cs_mem_free(detail->operands);
+	for (size_t i = 0; i < detail->flags_count; ++i) {
+		cs_mem_free(detail->flags[i]);
+	}
+	cs_mem_free(detail->flags);
+	cs_mem_free(detail);
+}
+
+TestDetailM680x *test_detail_m680x_clone(const TestDetailM680x *detail)
+{
+	TestDetailM680x *clone = test_detail_m680x_new();
+
+	clone->flags_count = detail->flags_count;
+	if (detail->flags_count > 0) {
+		clone->flags =
+			cs_mem_calloc(sizeof(char *), detail->flags_count);
+	}
+	for (size_t i = 0; i < detail->flags_count; ++i) {
+		clone->flags[i] = detail->flags[i] ? strdup(detail->flags[i]) :
+						     NULL;
+	}
+	clone->operands_count = detail->operands_count;
+	if (detail->operands_count > 0) {
+		clone->operands = cs_mem_calloc(sizeof(TestDetailM680xOp *),
+						detail->operands_count);
+	}
+	for (size_t i = 0; i < detail->operands_count; ++i) {
+		clone->operands[i] =
+			test_detail_m680x_op_clone(detail->operands[i]);
+	}
+
+	return clone;
+}
+
+TestDetailM680xOp *test_detail_m680x_op_new()
+{
+	return cs_mem_calloc(sizeof(TestDetailM680xOp), 1);
+}
+
+TestDetailM680xOp *test_detail_m680x_op_clone(const TestDetailM680xOp *op)
+{
+	TestDetailM680xOp *clone = test_detail_m680x_op_new();
+
+	clone->type = op->type ? strdup(op->type) : NULL;
+	clone->access = op->access ? strdup(op->access) : NULL;
+	clone->reg = op->reg ? strdup(op->reg) : NULL;
+	clone->idx = op->idx ? test_detail_m680x_idx_clone(op->idx) : NULL;
+	clone->imm = op->imm;
+	clone->rel_address = op->rel_address;
+	clone->rel_offset = op->rel_offset;
+	clone->ext_address = op->ext_address;
+	clone->ext_indirect = op->ext_indirect;
+	clone->direct_addr = op->direct_addr;
+	clone->direct_addr_set = op->direct_addr_set;
+	clone->const_val = op->const_val;
+	clone->size = op->size;
+
+	return clone;
+}
+
+void test_detail_m680x_op_free(TestDetailM680xOp *op)
+{
+	if (!op) {
+		return;
+	}
+	cs_mem_free(op->type);
+	cs_mem_free(op->access);
+	cs_mem_free(op->reg);
+	test_detail_m680x_idx_free(op->idx);
+	cs_mem_free(op);
+}
+
+bool test_expected_m680x(csh *handle, const cs_m680x *actual,
+			 const TestDetailM680x *expected)
+{
+	assert(handle && actual && expected);
+
+	compare_uint8_ret(actual->op_count, expected->operands_count, false);
+	for (size_t i = 0; i < actual->op_count; ++i) {
+		const cs_m680x_op *op = &actual->operands[i];
+		TestDetailM680xOp *eop = expected->operands[i];
+		compare_enum_ret(op->type, eop->type, false);
+		compare_enum_ret(op->access, eop->access, false);
+		if (eop->size > 0) {
+			compare_uint8_ret(op->size, eop->size, false);
+		}
+		switch (op->type) {
+		default:
+			fprintf(stderr,
+				"m680x op type %" PRId32 " not handled.\n",
+				op->type);
+			return false;
+		case M680X_OP_REGISTER:
+			compare_reg_ret(*handle, op->reg, eop->reg, false);
+			break;
+		case M680X_OP_IMMEDIATE:
+			compare_int32_ret(op->imm, eop->imm, false);
+			break;
+		case M680X_OP_EXTENDED:
+			compare_uint16_ret(op->ext.address, eop->ext_address,
+					   false);
+			compare_tbool_ret(op->ext.indirect, eop->ext_indirect,
+					  false);
+			break;
+		case M680X_OP_DIRECT:
+			if (eop->direct_addr_set) {
+				compare_uint8_ret(op->direct_addr,
+						  eop->direct_addr, false);
+			} else {
+				assert(eop->direct_addr == 0);
+			}
+			break;
+		case M680X_OP_RELATIVE:
+			compare_uint16_ret(op->rel.address, eop->rel_address,
+					   false);
+			compare_int16_ret(op->rel.offset, eop->rel_offset,
+					  false);
+			break;
+		case M680X_OP_CONSTANT:
+			compare_uint8_ret(op->const_val, eop->const_val, false);
+			break;
+		case M680X_OP_INDEXED:
+			if (!eop->idx) {
+				break;
+			}
+			compare_reg_ret(*handle, op->idx.base_reg,
+					eop->idx->base_reg, false);
+			compare_reg_ret(*handle, op->idx.offset_reg,
+					eop->idx->offset_reg, false);
+			if (eop->idx->offset) {
+				compare_int16_ret(op->idx.offset,
+						  eop->idx->offset, false);
+			}
+			if (eop->idx->offset_addr) {
+				compare_uint16_ret(op->idx.offset_addr,
+						   eop->idx->offset_addr,
+						   false);
+			}
+			if (eop->idx->offset_bits) {
+				compare_uint8_ret(op->idx.offset_bits,
+						  eop->idx->offset_bits, false);
+			}
+			if (eop->idx->inc_dec) {
+				compare_int8_ret(op->idx.inc_dec,
+						 eop->idx->inc_dec, false);
+			}
+			compare_bit_flags_ret(op->idx.flags, eop->idx->flags,
+					      eop->idx->flags_count, false);
+			break;
+		}
+	}
+
+	return true;
+}
diff --git a/suite/cstest/src/test_detail_m68k.c b/suite/cstest/src/test_detail_m68k.c
new file mode 100644
index 000000000..028b71d94
--- /dev/null
+++ b/suite/cstest/src/test_detail_m68k.c
@@ -0,0 +1,226 @@
+// Copyright © 2024 Rot127 <unisono@quyllur.org>
+// SPDX-License-Identifier: BSD-3
+
+#include "capstone/m68k.h"
+#include "test_compare.h"
+#include "test_detail_m68k.h"
+#include <capstone/capstone.h>
+#include <stdio.h>
+#include <string.h>
+
+TestDetailM68KOpMem *test_detail_m68k_op_mem_new()
+{
+	return cs_mem_calloc(sizeof(TestDetailM68KOpMem), 1);
+}
+
+TestDetailM68KOpMem *test_detail_m68k_op_mem_clone(TestDetailM68KOpMem *mem)
+{
+	assert(mem);
+	TestDetailM68KOpMem *clone = test_detail_m68k_op_mem_new();
+
+	clone->base_reg = mem->base_reg ? strdup(mem->base_reg) : NULL;
+	clone->index_reg = mem->index_reg ? strdup(mem->index_reg) : NULL;
+	clone->in_base_reg = mem->in_base_reg ? strdup(mem->in_base_reg) : NULL;
+	clone->index_size = mem->index_size;
+	clone->disp = mem->disp;
+	clone->in_disp = mem->in_disp;
+	clone->out_disp = mem->out_disp;
+	clone->scale = mem->scale;
+	clone->bitfield = mem->bitfield;
+	clone->width = mem->width;
+	clone->offset = mem->offset;
+
+	return clone;
+}
+
+void test_detail_m68k_op_mem_free(TestDetailM68KOpMem *mem)
+{
+	if (!mem) {
+		return;
+	}
+	cs_mem_free(mem->base_reg);
+	cs_mem_free(mem->index_reg);
+	cs_mem_free(mem->in_base_reg);
+	cs_mem_free(mem);
+}
+
+TestDetailM68K *test_detail_m68k_new()
+{
+	return cs_mem_calloc(sizeof(TestDetailM68K), 1);
+}
+
+void test_detail_m68k_free(TestDetailM68K *detail)
+{
+	if (!detail) {
+		return;
+	}
+	for (size_t i = 0; i < detail->operands_count; ++i) {
+		test_detail_m68k_op_free(detail->operands[i]);
+	}
+	cs_mem_free(detail->operands);
+	cs_mem_free(detail->op_size_type);
+	cs_mem_free(detail->op_size_fpu);
+	cs_mem_free(detail->op_size_cpu);
+	cs_mem_free(detail);
+}
+
+TestDetailM68K *test_detail_m68k_clone(TestDetailM68K *detail)
+{
+	TestDetailM68K *clone = test_detail_m68k_new();
+	clone->op_size_type =
+		detail->op_size_type ? strdup(detail->op_size_type) : NULL;
+	clone->op_size_fpu = detail->op_size_fpu ? strdup(detail->op_size_fpu) :
+						   NULL;
+	clone->op_size_cpu = detail->op_size_cpu ? strdup(detail->op_size_cpu) :
+						   NULL;
+
+	clone->operands_count = detail->operands_count;
+	if (detail->operands_count > 0) {
+		clone->operands = cs_mem_calloc(sizeof(TestDetailM68KOp *),
+						detail->operands_count);
+	}
+	for (size_t i = 0; i < detail->operands_count; ++i) {
+		clone->operands[i] =
+			test_detail_m68k_op_clone(detail->operands[i]);
+	}
+
+	return clone;
+}
+
+TestDetailM68KOp *test_detail_m68k_op_new()
+{
+	return cs_mem_calloc(sizeof(TestDetailM68KOp), 1);
+}
+
+TestDetailM68KOp *test_detail_m68k_op_clone(TestDetailM68KOp *op)
+{
+	TestDetailM68KOp *clone = test_detail_m68k_op_new();
+
+	clone->type = op->type ? strdup(op->type) : NULL;
+	clone->reg = op->reg ? strdup(op->reg) : NULL;
+	clone->reg_pair_0 = op->reg_pair_0 ? strdup(op->reg_pair_0) : NULL;
+	clone->reg_pair_1 = op->reg_pair_1 ? strdup(op->reg_pair_1) : NULL;
+	clone->address_mode = op->address_mode ? strdup(op->address_mode) :
+						 NULL;
+
+	clone->imm = op->imm;
+	clone->dimm = op->dimm;
+	clone->simm = op->simm;
+	clone->br_disp = op->br_disp;
+	clone->br_disp_size = op->br_disp_size;
+	clone->register_bits = op->register_bits;
+
+	clone->mem = op->mem ? test_detail_m68k_op_mem_clone(op->mem) : NULL;
+	return clone;
+}
+
+void test_detail_m68k_op_free(TestDetailM68KOp *op)
+{
+	if (!op) {
+		return;
+	}
+	cs_mem_free(op->type);
+	cs_mem_free(op->reg);
+	cs_mem_free(op->reg_pair_0);
+	cs_mem_free(op->reg_pair_1);
+	cs_mem_free(op->address_mode);
+	test_detail_m68k_op_mem_free(op->mem);
+	cs_mem_free(op);
+}
+
+bool test_expected_m68k(csh *handle, cs_m68k *actual, TestDetailM68K *expected)
+{
+	assert(handle && actual && expected);
+
+	compare_uint8_ret(actual->op_count, expected->operands_count, false);
+	compare_enum_ret(actual->op_size.type, expected->op_size_type, false);
+	compare_enum_ret(actual->op_size.fpu_size, expected->op_size_fpu,
+			 false);
+	compare_enum_ret(actual->op_size.cpu_size, expected->op_size_cpu,
+			 false);
+
+	for (size_t i = 0; i < actual->op_count; ++i) {
+		cs_m68k_op *op = &actual->operands[i];
+		TestDetailM68KOp *eop = expected->operands[i];
+		compare_enum_ret(op->type, eop->type, false);
+		compare_enum_ret(op->address_mode, eop->address_mode, false);
+		switch (op->type) {
+		default:
+			fprintf(stderr,
+				"M68K op type %" PRId32 " not handled.\n",
+				op->type);
+			return false;
+		case M68K_OP_REG:
+			compare_reg_ret(*handle, op->reg, eop->reg, false);
+			break;
+		case M68K_OP_REG_PAIR:
+			compare_reg_ret(*handle, op->reg_pair.reg_0,
+					eop->reg_pair_0, false);
+			compare_reg_ret(*handle, op->reg_pair.reg_1,
+					eop->reg_pair_1, false);
+			break;
+		case M68K_OP_IMM:
+			compare_uint64_ret(op->imm, eop->imm, false);
+			break;
+		case M68K_OP_FP_SINGLE:
+			compare_fp_ret(op->simm, eop->simm, false);
+			break;
+		case M68K_OP_FP_DOUBLE:
+			compare_fp_ret(op->dimm, eop->dimm, false);
+			break;
+		case M68K_OP_REG_BITS:
+			compare_uint32_ret(op->register_bits,
+					   eop->register_bits, false);
+			break;
+		case M68K_OP_BR_DISP:
+			compare_int32_ret(op->br_disp.disp, eop->br_disp,
+					  false);
+			compare_uint8_ret(op->br_disp.disp_size,
+					  eop->br_disp_size, false);
+			break;
+		case M68K_OP_MEM:
+			if (!eop->mem) {
+				break;
+			}
+			compare_reg_ret(*handle, op->mem.base_reg,
+					eop->mem->base_reg, false);
+			compare_reg_ret(*handle, op->mem.index_reg,
+					eop->mem->index_reg, false);
+			compare_reg_ret(*handle, op->mem.in_base_reg,
+					eop->mem->in_base_reg, false);
+			compare_tbool_ret(op->mem.index_size,
+					  eop->mem->index_size, false);
+			if (eop->mem->in_disp) {
+				compare_uint32_ret(op->mem.in_disp,
+						   eop->mem->in_disp, false);
+			}
+			if (eop->mem->out_disp) {
+				compare_uint32_ret(op->mem.out_disp,
+						   eop->mem->out_disp, false);
+			}
+			if (eop->mem->disp) {
+				compare_int16_ret(op->mem.disp, eop->mem->disp,
+						  false);
+			}
+			if (eop->mem->scale) {
+				compare_uint8_ret(op->mem.scale,
+						  eop->mem->scale, false);
+			}
+			if (eop->mem->bitfield) {
+				compare_uint8_ret(op->mem.bitfield,
+						  eop->mem->bitfield, false);
+			}
+			if (eop->mem->width) {
+				compare_uint8_ret(op->mem.width,
+						  eop->mem->width, false);
+			}
+			if (eop->mem->offset) {
+				compare_uint8_ret(op->mem.offset,
+						  eop->mem->offset, false);
+			}
+			break;
+		}
+	}
+
+	return true;
+}
diff --git a/suite/cstest/src/test_detail_mips.c b/suite/cstest/src/test_detail_mips.c
new file mode 100644
index 000000000..a1b8836e9
--- /dev/null
+++ b/suite/cstest/src/test_detail_mips.c
@@ -0,0 +1,103 @@
+// Copyright © 2024 Rot127 <unisono@quyllur.org>
+// SPDX-License-Identifier: BSD-3
+
+#include "test_compare.h"
+#include "test_detail_mips.h"
+#include <capstone/capstone.h>
+#include <stdio.h>
+#include <string.h>
+
+TestDetailMips *test_detail_mips_new()
+{
+	return cs_mem_calloc(sizeof(TestDetailMips), 1);
+}
+
+void test_detail_mips_free(TestDetailMips *detail)
+{
+	if (!detail) {
+		return;
+	}
+	for (size_t i = 0; i < detail->operands_count; ++i) {
+		test_detail_mips_op_free(detail->operands[i]);
+	}
+	cs_mem_free(detail->operands);
+	cs_mem_free(detail);
+}
+
+TestDetailMips *test_detail_mips_clone(const TestDetailMips *detail)
+{
+	TestDetailMips *clone = test_detail_mips_new();
+
+	clone->operands_count = detail->operands_count;
+	if (detail->operands_count > 0) {
+		clone->operands = cs_mem_calloc(sizeof(TestDetailMipsOp *),
+						detail->operands_count);
+	}
+	for (size_t i = 0; i < detail->operands_count; ++i) {
+		clone->operands[i] =
+			test_detail_mips_op_clone(detail->operands[i]);
+	}
+
+	return clone;
+}
+
+TestDetailMipsOp *test_detail_mips_op_new()
+{
+	return cs_mem_calloc(sizeof(TestDetailMipsOp), 1);
+}
+
+TestDetailMipsOp *test_detail_mips_op_clone(const TestDetailMipsOp *op)
+{
+	TestDetailMipsOp *clone = test_detail_mips_op_new();
+
+	clone->type = op->type ? strdup(op->type) : NULL;
+	clone->reg = op->reg ? strdup(op->reg) : NULL;
+	clone->imm = op->imm;
+	clone->mem_base = op->mem_base ? strdup(op->mem_base) : NULL;
+	clone->mem_disp = op->mem_disp;
+
+	return clone;
+}
+
+void test_detail_mips_op_free(TestDetailMipsOp *op)
+{
+	if (!op) {
+		return;
+	}
+	cs_mem_free(op->type);
+	cs_mem_free(op->reg);
+	cs_mem_free(op->mem_base);
+	cs_mem_free(op);
+}
+
+bool test_expected_mips(csh *handle, const cs_mips *actual,
+			const TestDetailMips *expected)
+{
+	assert(handle && actual && expected);
+
+	compare_uint8_ret(actual->op_count, expected->operands_count, false);
+	for (size_t i = 0; i < actual->op_count; ++i) {
+		const cs_mips_op *op = &actual->operands[i];
+		TestDetailMipsOp *eop = expected->operands[i];
+		compare_enum_ret(op->type, eop->type, false);
+		switch (op->type) {
+		default:
+			fprintf(stderr, "sh op type %" PRId32 " not handled.\n",
+				op->type);
+			return false;
+		case MIPS_OP_REG:
+			compare_reg_ret(*handle, op->reg, eop->reg, false);
+			break;
+		case MIPS_OP_IMM:
+			compare_uint64_ret(op->imm, eop->imm, false);
+			break;
+		case MIPS_OP_MEM:
+			compare_reg_ret(*handle, op->mem.base, eop->mem_base,
+					false);
+			compare_int64_ret(op->mem.disp, eop->mem_disp, false);
+			break;
+		}
+	}
+
+	return true;
+}
diff --git a/suite/cstest/src/test_detail_mos65xx.c b/suite/cstest/src/test_detail_mos65xx.c
new file mode 100644
index 000000000..8cf859b63
--- /dev/null
+++ b/suite/cstest/src/test_detail_mos65xx.c
@@ -0,0 +1,105 @@
+// Copyright © 2024 Rot127 <unisono@quyllur.org>
+// SPDX-License-Identifier: BSD-3
+
+#include "test_compare.h"
+#include "test_detail_mos65xx.h"
+#include <capstone/capstone.h>
+#include <stdio.h>
+#include <string.h>
+
+TestDetailMos65xx *test_detail_mos65xx_new()
+{
+	return cs_mem_calloc(sizeof(TestDetailMos65xx), 1);
+}
+
+void test_detail_mos65xx_free(TestDetailMos65xx *detail)
+{
+	if (!detail) {
+		return;
+	}
+	for (size_t i = 0; i < detail->operands_count; ++i) {
+		test_detail_mos65xx_op_free(detail->operands[i]);
+	}
+	cs_mem_free(detail->operands);
+	cs_mem_free(detail->am);
+	cs_mem_free(detail);
+}
+
+TestDetailMos65xx *test_detail_mos65xx_clone(const TestDetailMos65xx *detail)
+{
+	TestDetailMos65xx *clone = test_detail_mos65xx_new();
+
+	clone->operands_count = detail->operands_count;
+	if (detail->operands_count > 0) {
+		clone->operands = cs_mem_calloc(sizeof(TestDetailMos65xxOp *),
+						detail->operands_count);
+	}
+	for (size_t i = 0; i < detail->operands_count; ++i) {
+		clone->operands[i] =
+			test_detail_mos65xx_op_clone(detail->operands[i]);
+	}
+	clone->am = detail->am ? strdup(detail->am) : NULL;
+	clone->modifies_flags = detail->modifies_flags;
+
+	return clone;
+}
+
+TestDetailMos65xxOp *test_detail_mos65xx_op_new()
+{
+	return cs_mem_calloc(sizeof(TestDetailMos65xxOp), 1);
+}
+
+TestDetailMos65xxOp *test_detail_mos65xx_op_clone(const TestDetailMos65xxOp *op)
+{
+	TestDetailMos65xxOp *clone = test_detail_mos65xx_op_new();
+
+	clone->type = op->type ? strdup(op->type) : NULL;
+	clone->reg = op->reg ? strdup(op->reg) : NULL;
+	clone->imm = op->imm;
+	clone->mem = op->mem;
+
+	return clone;
+}
+
+void test_detail_mos65xx_op_free(TestDetailMos65xxOp *op)
+{
+	if (!op) {
+		return;
+	}
+	cs_mem_free(op->type);
+	cs_mem_free(op->reg);
+	cs_mem_free(op);
+}
+
+bool test_expected_mos65xx(csh *handle, const cs_mos65xx *actual,
+			   const TestDetailMos65xx *expected)
+{
+	assert(handle && actual && expected);
+
+	compare_uint8_ret(actual->op_count, expected->operands_count, false);
+	compare_enum_ret(actual->am, expected->am, false);
+	compare_tbool_ret(actual->modifies_flags, expected->modifies_flags,
+			  false);
+	for (size_t i = 0; i < actual->op_count; ++i) {
+		const cs_mos65xx_op *op = &actual->operands[i];
+		TestDetailMos65xxOp *eop = expected->operands[i];
+		compare_enum_ret(op->type, eop->type, false);
+		switch (op->type) {
+		default:
+			fprintf(stderr, "sh op type %" PRId32 " not handled.\n",
+				op->type);
+			return false;
+		case MOS65XX_OP_REG:
+			compare_reg_ret(*handle, op->reg, eop->reg, false);
+			break;
+		case MOS65XX_OP_IMM:
+			compare_uint16_ret(op->imm, eop->imm, false);
+			break;
+		case MOS65XX_OP_MEM:
+			compare_uint16_ret(op->mem, eop->mem, false);
+			break;
+		}
+	}
+
+	return true;
+}
diff --git a/suite/cstest/src/test_detail_ppc.c b/suite/cstest/src/test_detail_ppc.c
new file mode 100644
index 000000000..17dc33122
--- /dev/null
+++ b/suite/cstest/src/test_detail_ppc.c
@@ -0,0 +1,185 @@
+// Copyright © 2024 Rot127 <unisono@quyllur.org>
+// SPDX-License-Identifier: BSD-3
+
+#include "test_compare.h"
+#include "test_detail_ppc.h"
+#include <capstone/capstone.h>
+#include <stdio.h>
+#include <string.h>
+
+TestDetailPPCBC *test_detail_ppc_bc_new()
+{
+	return cs_mem_calloc(sizeof(TestDetailPPCBC), 1);
+}
+
+TestDetailPPCBC *test_detail_ppc_bc_clone(const TestDetailPPCBC *bc)
+{
+	assert(bc);
+	TestDetailPPCBC *clone = test_detail_ppc_bc_new();
+	clone->bh = bc->bh ? strdup(bc->bh) : NULL;
+	clone->crX = bc->crX ? strdup(bc->crX) : NULL;
+	clone->crX_bit = bc->crX_bit ? strdup(bc->crX_bit) : NULL;
+	clone->hint = bc->hint ? strdup(bc->hint) : NULL;
+	clone->pred_cr = bc->pred_cr ? strdup(bc->pred_cr) : NULL;
+	clone->pred_ctr = bc->pred_ctr ? strdup(bc->pred_ctr) : NULL;
+	clone->bi = bc->bi;
+	clone->bi_set = bc->bi_set;
+	clone->bo = bc->bo;
+	clone->bo_set = bc->bo_set;
+	return clone;
+}
+
+void test_detail_ppc_bc_free(TestDetailPPCBC *bc)
+{
+	if (!bc) {
+		return;
+	}
+	cs_mem_free(bc->bh);
+	cs_mem_free(bc->crX);
+	cs_mem_free(bc->crX_bit);
+	cs_mem_free(bc->hint);
+	cs_mem_free(bc->pred_cr);
+	cs_mem_free(bc->pred_ctr);
+	cs_mem_free(bc);
+}
+
+TestDetailPPC *test_detail_ppc_new()
+{
+	return cs_mem_calloc(sizeof(TestDetailPPC), 1);
+}
+
+void test_detail_ppc_free(TestDetailPPC *detail)
+{
+	if (!detail) {
+		return;
+	}
+	test_detail_ppc_bc_free(detail->bc);
+	for (size_t i = 0; i < detail->operands_count; ++i) {
+		test_detail_ppc_op_free(detail->operands[i]);
+	}
+	cs_mem_free(detail->operands);
+	cs_mem_free(detail->format);
+	cs_mem_free(detail);
+}
+
+TestDetailPPC *test_detail_ppc_clone(const TestDetailPPC *detail)
+{
+	TestDetailPPC *clone = test_detail_ppc_new();
+	clone->format = detail->format ? strdup(detail->format) : NULL;
+	clone->update_cr0 = detail->update_cr0;
+	clone->bc = detail->bc ? test_detail_ppc_bc_clone(detail->bc) : NULL;
+
+	clone->operands_count = detail->operands_count;
+	if (detail->operands_count > 0) {
+		clone->operands = cs_mem_calloc(sizeof(TestDetailPPCOp *),
+						detail->operands_count);
+	}
+	for (size_t i = 0; i < detail->operands_count; ++i) {
+		clone->operands[i] =
+			test_detail_ppc_op_clone(detail->operands[i]);
+	}
+
+	return clone;
+}
+
+TestDetailPPCOp *test_detail_ppc_op_new()
+{
+	return cs_mem_calloc(sizeof(TestDetailPPCOp), 1);
+}
+
+TestDetailPPCOp *test_detail_ppc_op_clone(const TestDetailPPCOp *op)
+{
+	TestDetailPPCOp *clone = test_detail_ppc_op_new();
+
+	clone->type = op->type ? strdup(op->type) : NULL;
+	clone->access = op->access ? strdup(op->access) : NULL;
+	clone->reg = op->reg ? strdup(op->reg) : NULL;
+	clone->imm = op->imm;
+	clone->mem_base = op->mem_base ? strdup(op->mem_base) : NULL;
+	clone->mem_offset = op->mem_offset ? strdup(op->mem_offset) : NULL;
+	clone->mem_disp = op->mem_disp;
+
+	return clone;
+}
+
+void test_detail_ppc_op_free(TestDetailPPCOp *op)
+{
+	if (!op) {
+		return;
+	}
+	cs_mem_free(op->type);
+	cs_mem_free(op->access);
+	cs_mem_free(op->reg);
+	cs_mem_free(op->mem_base);
+	cs_mem_free(op->mem_offset);
+	cs_mem_free(op);
+}
+
+bool test_expected_ppc(csh *handle, const cs_ppc *actual,
+		       const TestDetailPPC *expected)
+{
+	assert(handle && actual && expected);
+
+	compare_enum_ret(actual->format, expected->format, false);
+	compare_tbool_ret(actual->update_cr0, expected->update_cr0, false);
+
+	if (expected->operands_count == 0) {
+		return true;
+	}
+	compare_uint8_ret(actual->op_count, expected->operands_count, false);
+	for (size_t i = 0; i < actual->op_count; ++i) {
+		const cs_ppc_op *op = &actual->operands[i];
+		TestDetailPPCOp *eop = expected->operands[i];
+		compare_enum_ret(op->type, eop->type, false);
+		compare_enum_ret(op->access, eop->access, false);
+		switch (op->type) {
+		default:
+			fprintf(stderr,
+				"arm op type %" PRId32 " not handled.\n",
+				op->type);
+			return false;
+		case PPC_OP_REG:
+			compare_reg_ret(*handle, op->reg, eop->reg, false);
+			break;
+		case PPC_OP_IMM:
+			compare_int64_ret(op->imm, eop->imm, false);
+			break;
+		case PPC_OP_MEM:
+			compare_reg_ret(*handle, op->mem.base, eop->mem_base,
+					false);
+			compare_reg_ret(*handle, op->mem.offset,
+					eop->mem_offset, false);
+			compare_int_ret(op->mem.disp, eop->mem_disp, false);
+			break;
+		}
+
+		if (expected->bc) {
+			if (expected->bc->bi_set) {
+				compare_uint8_ret(actual->bc.bi,
+						  expected->bc->bi, false);
+			} else {
+				assert(expected->bc->bi == 0);
+			}
+			if (expected->bc->bo_set) {
+				compare_uint8_ret(actual->bc.bo,
+						  expected->bc->bo, false);
+			} else {
+				assert(expected->bc->bo == 0);
+			}
+			compare_enum_ret(actual->bc.bh, expected->bc->bh,
+					 false);
+			compare_reg_ret(*handle, actual->bc.crX,
+					expected->bc->crX, false);
+			compare_enum_ret(actual->bc.crX_bit,
+					 expected->bc->crX_bit, false);
+			compare_enum_ret(actual->bc.hint, expected->bc->hint,
+					 false);
+			compare_enum_ret(actual->bc.pred_cr,
+					 expected->bc->pred_cr, false);
+			compare_enum_ret(actual->bc.pred_ctr,
+					 expected->bc->pred_ctr, false);
+		}
+	}
+
+	return true;
+}
diff --git a/suite/cstest/src/test_detail_riscv.c b/suite/cstest/src/test_detail_riscv.c
new file mode 100644
index 000000000..ef3a59e69
--- /dev/null
+++ b/suite/cstest/src/test_detail_riscv.c
@@ -0,0 +1,106 @@
+// Copyright © 2024 Rot127 <unisono@quyllur.org>
+// SPDX-License-Identifier: BSD-3
+
+#include "test_compare.h"
+#include "test_detail_riscv.h"
+#include <capstone/capstone.h>
+#include <stdio.h>
+#include <string.h>
+
+TestDetailRISCV *test_detail_riscv_new()
+{
+	return cs_mem_calloc(sizeof(TestDetailRISCV), 1);
+}
+
+void test_detail_riscv_free(TestDetailRISCV *detail)
+{
+	if (!detail) {
+		return;
+	}
+	for (size_t i = 0; i < detail->operands_count; ++i) {
+		test_detail_riscv_op_free(detail->operands[i]);
+	}
+	cs_mem_free(detail->operands);
+	cs_mem_free(detail);
+}
+
+TestDetailRISCV *test_detail_riscv_clone(const TestDetailRISCV *detail)
+{
+	TestDetailRISCV *clone = test_detail_riscv_new();
+
+	clone->operands_count = detail->operands_count;
+	if (detail->operands_count > 0) {
+		clone->operands = cs_mem_calloc(sizeof(TestDetailRISCVOp *),
+						detail->operands_count);
+	}
+	for (size_t i = 0; i < detail->operands_count; ++i) {
+		clone->operands[i] =
+			test_detail_riscv_op_clone(detail->operands[i]);
+	}
+
+	return clone;
+}
+
+TestDetailRISCVOp *test_detail_riscv_op_new()
+{
+	return cs_mem_calloc(sizeof(TestDetailRISCVOp), 1);
+}
+
+TestDetailRISCVOp *test_detail_riscv_op_clone(const TestDetailRISCVOp *op)
+{
+	TestDetailRISCVOp *clone = test_detail_riscv_op_new();
+
+	clone->type = op->type ? strdup(op->type) : NULL;
+	clone->access = op->access ? strdup(op->access) : NULL;
+	clone->reg = op->reg ? strdup(op->reg) : NULL;
+	clone->imm = op->imm;
+	clone->mem_base = op->mem_base ? strdup(op->mem_base) : NULL;
+	clone->mem_disp = op->mem_disp;
+
+	return clone;
+}
+
+void test_detail_riscv_op_free(TestDetailRISCVOp *op)
+{
+	if (!op) {
+		return;
+	}
+	cs_mem_free(op->type);
+	cs_mem_free(op->access);
+	cs_mem_free(op->reg);
+	cs_mem_free(op->mem_base);
+	cs_mem_free(op);
+}
+
+bool test_expected_riscv(csh *handle, const cs_riscv *actual,
+			 const TestDetailRISCV *expected)
+{
+	assert(handle && actual && expected);
+
+	compare_uint8_ret(actual->op_count, expected->operands_count, false);
+	for (size_t i = 0; i < actual->op_count; ++i) {
+		const cs_riscv_op *op = &actual->operands[i];
+		TestDetailRISCVOp *eop = expected->operands[i];
+		compare_enum_ret(op->type, eop->type, false);
+		compare_enum_ret(op->access, eop->access, false);
+		switch (op->type) {
+		default:
+			fprintf(stderr, "sh op type %" PRId32 " not handled.\n",
+				op->type);
+			return false;
+		case RISCV_OP_REG:
+			compare_reg_ret(*handle, op->reg, eop->reg, false);
+			break;
+		case RISCV_OP_IMM:
+			compare_uint64_ret(op->imm, eop->imm, false);
+			break;
+		case RISCV_OP_MEM:
+			compare_reg_ret(*handle, op->mem.base, eop->mem_base,
+					false);
+			compare_int64_ret(op->mem.disp, eop->mem_disp, false);
+			break;
+		}
+	}
+
+	return true;
+}
diff --git a/suite/cstest/src/test_detail_sh.c b/suite/cstest/src/test_detail_sh.c
new file mode 100644
index 000000000..c86ab57ce
--- /dev/null
+++ b/suite/cstest/src/test_detail_sh.c
@@ -0,0 +1,107 @@
+// Copyright © 2024 Rot127 <unisono@quyllur.org>
+// SPDX-License-Identifier: BSD-3
+
+#include "test_compare.h"
+#include "test_detail_sh.h"
+#include <capstone/capstone.h>
+#include <stdio.h>
+#include <string.h>
+
+TestDetailSH *test_detail_sh_new()
+{
+	return cs_mem_calloc(sizeof(TestDetailSH), 1);
+}
+
+void test_detail_sh_free(TestDetailSH *detail)
+{
+	if (!detail) {
+		return;
+	}
+	for (size_t i = 0; i < detail->operands_count; ++i) {
+		test_detail_sh_op_free(detail->operands[i]);
+	}
+	cs_mem_free(detail->operands);
+	cs_mem_free(detail);
+}
+
+TestDetailSH *test_detail_sh_clone(const TestDetailSH *detail)
+{
+	TestDetailSH *clone = test_detail_sh_new();
+
+	clone->operands_count = detail->operands_count;
+	if (detail->operands_count > 0) {
+		clone->operands = cs_mem_calloc(sizeof(TestDetailSHOp *),
+						detail->operands_count);
+	}
+	for (size_t i = 0; i < detail->operands_count; ++i) {
+		clone->operands[i] =
+			test_detail_sh_op_clone(detail->operands[i]);
+	}
+
+	return clone;
+}
+
+TestDetailSHOp *test_detail_sh_op_new()
+{
+	return cs_mem_calloc(sizeof(TestDetailSHOp), 1);
+}
+
+TestDetailSHOp *test_detail_sh_op_clone(const TestDetailSHOp *op)
+{
+	TestDetailSHOp *clone = test_detail_sh_op_new();
+
+	clone->type = op->type ? strdup(op->type) : NULL;
+	clone->reg = op->reg ? strdup(op->reg) : NULL;
+	clone->imm = op->imm;
+	clone->mem_reg = op->mem_reg ? strdup(op->mem_reg) : NULL;
+	clone->mem_address = op->mem_address ? strdup(op->mem_address) : NULL;
+	clone->mem_disp = op->mem_disp;
+
+	return clone;
+}
+
+void test_detail_sh_op_free(TestDetailSHOp *op)
+{
+	if (!op) {
+		return;
+	}
+	cs_mem_free(op->type);
+	cs_mem_free(op->reg);
+	cs_mem_free(op->mem_reg);
+	cs_mem_free(op->mem_address);
+	cs_mem_free(op);
+}
+
+bool test_expected_sh(csh *handle, const cs_sh *actual,
+		      const TestDetailSH *expected)
+{
+	assert(handle && actual && expected);
+
+	compare_uint8_ret(actual->op_count, expected->operands_count, false);
+	for (size_t i = 0; i < actual->op_count; ++i) {
+		const cs_sh_op *op = &actual->operands[i];
+		TestDetailSHOp *eop = expected->operands[i];
+		compare_enum_ret(op->type, eop->type, false);
+		switch (op->type) {
+		default:
+			fprintf(stderr, "sh op type %" PRId32 " not handled.\n",
+				op->type);
+			return false;
+		case SH_OP_REG:
+			compare_reg_ret(*handle, op->reg, eop->reg, false);
+			break;
+		case SH_OP_IMM:
+			compare_uint64_ret(op->imm, eop->imm, false);
+			break;
+		case SH_OP_MEM:
+			compare_reg_ret(*handle, op->mem.reg, eop->mem_reg,
+					false);
+			compare_reg_ret(*handle, op->mem.address,
+					eop->mem_address, false);
+			compare_int_ret(op->mem.disp, eop->mem_disp, false);
+			break;
+		}
+	}
+
+	return true;
+}
diff --git a/suite/cstest/src/test_detail_sparc.c b/suite/cstest/src/test_detail_sparc.c
new file mode 100644
index 000000000..1f929cc69
--- /dev/null
+++ b/suite/cstest/src/test_detail_sparc.c
@@ -0,0 +1,123 @@
+// Copyright © 2024 Rot127 <unisono@quyllur.org>
+// SPDX-License-Identifier: BSD-3
+
+#include "test_compare.h"
+#include "test_detail_sparc.h"
+#include <capstone/capstone.h>
+#include <stdio.h>
+#include <string.h>
+
+TestDetailSparc *test_detail_sparc_new()
+{
+	return cs_mem_calloc(sizeof(TestDetailSparc), 1);
+}
+
+void test_detail_sparc_free(TestDetailSparc *detail)
+{
+	if (!detail) {
+		return;
+	}
+	for (size_t i = 0; i < detail->operands_count; ++i) {
+		test_detail_sparc_op_free(detail->operands[i]);
+	}
+	cs_mem_free(detail->operands);
+	cs_mem_free(detail->cc);
+	cs_mem_free(detail->hint);
+	cs_mem_free(detail);
+}
+
+TestDetailSparc *test_detail_sparc_clone(const TestDetailSparc *detail)
+{
+	TestDetailSparc *clone = test_detail_sparc_new();
+
+	clone->operands_count = detail->operands_count;
+	clone->cc = detail->cc ? strdup(detail->cc) : NULL;
+	clone->hint = detail->hint ? strdup(detail->hint) : NULL;
+	if (detail->operands_count > 0) {
+		clone->operands = cs_mem_calloc(sizeof(TestDetailSparcOp *),
+						detail->operands_count);
+	}
+	for (size_t i = 0; i < detail->operands_count; ++i) {
+		clone->operands[i] =
+			test_detail_sparc_op_clone(detail->operands[i]);
+	}
+
+	return clone;
+}
+
+TestDetailSparcOp *test_detail_sparc_op_new()
+{
+	return cs_mem_calloc(sizeof(TestDetailSparcOp), 1);
+}
+
+TestDetailSparcOp *test_detail_sparc_op_clone(const TestDetailSparcOp *op)
+{
+	TestDetailSparcOp *clone = test_detail_sparc_op_new();
+
+	clone->type = op->type ? strdup(op->type) : NULL;
+	clone->reg = op->reg ? strdup(op->reg) : NULL;
+	clone->imm = op->imm;
+	clone->mem_base = op->mem_base ? strdup(op->mem_base) : NULL;
+	clone->mem_index = op->mem_index ? strdup(op->mem_index) : NULL;
+	clone->mem_disp = op->mem_disp;
+
+	return clone;
+}
+
+void test_detail_sparc_op_free(TestDetailSparcOp *op)
+{
+	if (!op) {
+		return;
+	}
+	cs_mem_free(op->type);
+	cs_mem_free(op->reg);
+	cs_mem_free(op->mem_base);
+	cs_mem_free(op->mem_index);
+	cs_mem_free(op);
+}
+
+bool test_expected_sparc(csh *handle, const cs_sparc *actual,
+			 const TestDetailSparc *expected)
+{
+	assert(handle && actual && expected);
+
+	if (expected->cc) {
+		compare_enum_ret(actual->cc, expected->cc, false);
+	}
+	if (expected->hint) {
+		compare_enum_ret(actual->hint, expected->hint, false);
+	}
+
+	if (expected->operands_count == 0) {
+		return true;
+	}
+	compare_uint8_ret(actual->op_count, expected->operands_count, false);
+
+	for (size_t i = 0; i < expected->operands_count; ++i) {
+		const cs_sparc_op *op = &actual->operands[i];
+		TestDetailSparcOp *eop = expected->operands[i];
+		compare_enum_ret(op->type, eop->type, false);
+		switch (op->type) {
+		default:
+			fprintf(stderr,
+				"arm op type %" PRId32 " not handled.\n",
+				op->type);
+			return false;
+		case SPARC_OP_REG:
+			compare_reg_ret(*handle, op->reg, eop->reg, false);
+			break;
+		case SPARC_OP_IMM:
+			compare_int64_ret(op->imm, eop->imm, false);
+			break;
+		case SPARC_OP_MEM:
+			compare_reg_ret(*handle, op->mem.base, eop->mem_base,
+					false);
+			compare_reg_ret(*handle, op->mem.index, eop->mem_index,
+					false);
+			compare_int32_ret(op->mem.disp, eop->mem_disp, false);
+			break;
+		}
+	}
+
+	return true;
+}
diff --git a/suite/cstest/src/test_detail_systemz.c b/suite/cstest/src/test_detail_systemz.c
new file mode 100644
index 000000000..a15fbca63
--- /dev/null
+++ b/suite/cstest/src/test_detail_systemz.c
@@ -0,0 +1,112 @@
+// Copyright © 2024 Rot127 <unisono@quyllur.org>
+// SPDX-License-Identifier: BSD-3
+
+#include "test_compare.h"
+#include "test_detail_systemz.h"
+#include <capstone/capstone.h>
+#include <stdio.h>
+#include <string.h>
+
+TestDetailSystemZ *test_detail_systemz_new()
+{
+	return cs_mem_calloc(sizeof(TestDetailSystemZ), 1);
+}
+
+void test_detail_systemz_free(TestDetailSystemZ *detail)
+{
+	if (!detail) {
+		return;
+	}
+	for (size_t i = 0; i < detail->operands_count; ++i) {
+		test_detail_systemz_op_free(detail->operands[i]);
+	}
+	cs_mem_free(detail->operands);
+	cs_mem_free(detail);
+}
+
+TestDetailSystemZ *test_detail_systemz_clone(const TestDetailSystemZ *detail)
+{
+	TestDetailSystemZ *clone = test_detail_systemz_new();
+
+	clone->operands_count = detail->operands_count;
+	if (detail->operands_count > 0) {
+		clone->operands = cs_mem_calloc(sizeof(TestDetailSystemZOp *),
+						detail->operands_count);
+	}
+	for (size_t i = 0; i < detail->operands_count; ++i) {
+		clone->operands[i] =
+			test_detail_systemz_op_clone(detail->operands[i]);
+	}
+
+	return clone;
+}
+
+TestDetailSystemZOp *test_detail_systemz_op_new()
+{
+	return cs_mem_calloc(sizeof(TestDetailSystemZOp), 1);
+}
+
+TestDetailSystemZOp *test_detail_systemz_op_clone(const TestDetailSystemZOp *op)
+{
+	TestDetailSystemZOp *clone = test_detail_systemz_op_new();
+
+	clone->type = op->type ? strdup(op->type) : NULL;
+	clone->reg = op->reg ? strdup(op->reg) : NULL;
+	clone->imm = op->imm;
+	clone->mem_base = op->mem_base ? strdup(op->mem_base) : NULL;
+	clone->mem_index = op->mem_index ? strdup(op->mem_index) : NULL;
+	clone->mem_disp = op->mem_disp;
+	clone->mem_length = op->mem_length;
+
+	return clone;
+}
+
+void test_detail_systemz_op_free(TestDetailSystemZOp *op)
+{
+	if (!op) {
+		return;
+	}
+	cs_mem_free(op->type);
+	cs_mem_free(op->reg);
+	cs_mem_free(op->mem_base);
+	cs_mem_free(op->mem_index);
+	cs_mem_free(op);
+}
+
+bool test_expected_systemz(csh *handle, const cs_sysz *actual,
+			   const TestDetailSystemZ *expected)
+{
+	assert(handle && actual && expected);
+
+	compare_uint8_ret(actual->op_count, expected->operands_count, false);
+	for (size_t i = 0; i < actual->op_count; ++i) {
+		const cs_sysz_op *op = &actual->operands[i];
+		TestDetailSystemZOp *eop = expected->operands[i];
+		compare_enum_ret(op->type, eop->type, false);
+		switch (op->type) {
+		default:
+			fprintf(stderr,
+				"arm op type %" PRId32 " not handled.\n",
+				op->type);
+			return false;
+		case SYSZ_OP_REG:
+		case SYSZ_OP_ACREG:
+			compare_reg_ret(*handle, op->reg, eop->reg, false);
+			break;
+		case SYSZ_OP_IMM:
+			compare_int64_ret(op->imm, eop->imm, false);
+			break;
+		case SYSZ_OP_MEM:
+			compare_reg_ret(*handle, op->mem.base, eop->mem_base,
+					false);
+			compare_reg_ret(*handle, op->mem.index, eop->mem_index,
+					false);
+			compare_int64_ret(op->mem.disp, eop->mem_disp, false);
+			compare_uint64_ret(op->mem.length, eop->mem_length,
+					   false);
+			break;
+		}
+	}
+
+	return true;
+}
diff --git a/suite/cstest/src/test_detail_tms320c64x.c b/suite/cstest/src/test_detail_tms320c64x.c
new file mode 100644
index 000000000..99d8cd829
--- /dev/null
+++ b/suite/cstest/src/test_detail_tms320c64x.c
@@ -0,0 +1,179 @@
+// Copyright © 2024 Rot127 <unisono@quyllur.org>
+// SPDX-License-Identifier: BSD-3
+
+#include "capstone/tms320c64x.h"
+#include "test_compare.h"
+#include "test_detail_tms320c64x.h"
+#include <capstone/capstone.h>
+#include <stdio.h>
+#include <string.h>
+
+TestDetailTMS320c64x *test_detail_tms320c64x_new()
+{
+	return cs_mem_calloc(sizeof(TestDetailTMS320c64x), 1);
+}
+
+void test_detail_tms320c64x_free(TestDetailTMS320c64x *detail)
+{
+	if (!detail) {
+		return;
+	}
+	for (size_t i = 0; i < detail->operands_count; ++i) {
+		test_detail_tms320c64x_op_free(detail->operands[i]);
+	}
+	cs_mem_free(detail->operands);
+	cs_mem_free(detail->cond_reg);
+	cs_mem_free(detail->funit_unit);
+	cs_mem_free(detail);
+}
+
+TestDetailTMS320c64x *test_detail_tms320c64x_clone(TestDetailTMS320c64x *detail)
+{
+	TestDetailTMS320c64x *clone = test_detail_tms320c64x_new();
+	clone->cond_reg = detail->cond_reg ? strdup(detail->cond_reg) : NULL;
+	clone->cond_zero = detail->cond_zero;
+	clone->funit_unit = detail->funit_unit ? strdup(detail->funit_unit) :
+						 NULL;
+	clone->funit_side = detail->funit_side;
+	clone->funit_side_set = detail->funit_side_set;
+	clone->funit_crosspath = detail->funit_crosspath;
+	clone->funit_crosspath_set = detail->funit_crosspath_set;
+
+	clone->parallel = detail->parallel;
+	clone->parallel_set = detail->parallel_set;
+
+	clone->operands_count = detail->operands_count;
+	if (detail->operands_count > 0) {
+		clone->operands =
+			cs_mem_calloc(sizeof(TestDetailTMS320c64xOp *),
+				      detail->operands_count);
+	}
+	for (size_t i = 0; i < detail->operands_count; ++i) {
+		clone->operands[i] =
+			test_detail_tms320c64x_op_clone(detail->operands[i]);
+	}
+
+	return clone;
+}
+
+TestDetailTMS320c64xOp *test_detail_tms320c64x_op_new()
+{
+	return cs_mem_calloc(sizeof(TestDetailTMS320c64xOp), 1);
+}
+
+TestDetailTMS320c64xOp *
+test_detail_tms320c64x_op_clone(TestDetailTMS320c64xOp *op)
+{
+	TestDetailTMS320c64xOp *clone = test_detail_tms320c64x_op_new();
+
+	clone->type = op->type ? strdup(op->type) : NULL;
+	clone->reg = op->reg ? strdup(op->reg) : NULL;
+	clone->reg_pair_0 = op->reg_pair_0 ? strdup(op->reg_pair_0) : NULL;
+	clone->reg_pair_1 = op->reg_pair_1 ? strdup(op->reg_pair_1) : NULL;
+	clone->imm = op->imm;
+	clone->mem_base = op->mem_base ? strdup(op->mem_base) : NULL;
+	clone->mem_scaled = op->mem_scaled;
+	clone->mem_disptype = op->mem_disptype ? strdup(op->mem_disptype) :
+						 NULL;
+	clone->mem_direction = op->mem_direction ? strdup(op->mem_direction) :
+						   NULL;
+	clone->mem_modify = op->mem_modify ? strdup(op->mem_modify) : NULL;
+	clone->mem_disp_const = op->mem_disp_const;
+	clone->mem_disp_reg = op->mem_disp_reg ? strdup(op->mem_disp_reg) :
+						 NULL;
+	clone->mem_unit = op->mem_unit;
+
+	return clone;
+}
+
+void test_detail_tms320c64x_op_free(TestDetailTMS320c64xOp *op)
+{
+	if (!op) {
+		return;
+	}
+	cs_mem_free(op->type);
+	cs_mem_free(op->mem_base);
+	cs_mem_free(op->mem_disp_reg);
+	cs_mem_free(op->mem_disptype);
+	cs_mem_free(op->mem_direction);
+	cs_mem_free(op->mem_modify);
+	cs_mem_free(op->reg);
+	cs_mem_free(op->reg_pair_0);
+	cs_mem_free(op->reg_pair_1);
+	cs_mem_free(op);
+}
+
+bool test_expected_tms320c64x(csh *handle, cs_tms320c64x *actual,
+			      TestDetailTMS320c64x *expected)
+{
+	assert(handle && actual && expected);
+
+	compare_uint8_ret(actual->op_count, expected->operands_count, false);
+	compare_reg_ret(*handle, actual->condition.reg, expected->cond_reg,
+			false);
+	compare_tbool_ret(actual->condition.zero, expected->cond_zero, false);
+	compare_enum_ret(actual->funit.unit, expected->funit_unit, false);
+	if (expected->funit_side_set) {
+		compare_uint8_ret(actual->funit.side, expected->funit_side,
+				  false);
+	} else {
+		assert(expected->funit_side == 0);
+	}
+	if (expected->funit_crosspath_set) {
+		compare_uint8_ret(actual->funit.crosspath,
+				  expected->funit_crosspath, false);
+	} else {
+		assert(expected->funit_crosspath == 0);
+	}
+	if (expected->parallel_set) {
+		compare_uint8_ret(actual->parallel, expected->parallel, false);
+	} else {
+		assert(expected->parallel == 0);
+	}
+	for (size_t i = 0; i < actual->op_count; ++i) {
+		cs_tms320c64x_op *op = &actual->operands[i];
+		TestDetailTMS320c64xOp *eop = expected->operands[i];
+		compare_enum_ret(op->type, eop->type, false);
+		switch (op->type) {
+		default:
+			fprintf(stderr,
+				"tms320c64x op type %" PRId32 " not handled.\n",
+				op->type);
+			return false;
+		case TMS320C64X_OP_REG:
+			compare_reg_ret(*handle, op->reg, eop->reg, false);
+			break;
+		case TMS320C64X_OP_REGPAIR:
+			compare_reg_ret(*handle, op->reg + 1, eop->reg_pair_0,
+					false);
+			compare_reg_ret(*handle, op->reg, eop->reg_pair_1,
+					false);
+			break;
+		case TMS320C64X_OP_IMM:
+			compare_int32_ret(op->imm, eop->imm, false);
+			break;
+		case TMS320C64X_OP_MEM:
+			compare_reg_ret(*handle, op->mem.base, eop->mem_base,
+					false);
+			compare_enum_ret(op->mem.direction, eop->mem_direction,
+					 false);
+			compare_tbool_ret(op->mem.scaled, eop->mem_scaled,
+					  false);
+			compare_enum_ret(op->mem.disptype, eop->mem_disptype,
+					 false);
+			if (op->mem.disptype == TMS320C64X_MEM_DISP_REGISTER) {
+				compare_reg_ret(*handle, op->mem.disp,
+						eop->mem_disp_reg, false);
+			} else {
+				compare_uint_ret(op->mem.disp,
+						 eop->mem_disp_const, false);
+			}
+			compare_enum_ret(op->mem.modify, eop->mem_modify,
+					 false);
+			compare_uint_ret(op->mem.unit, eop->mem_unit, false);
+			break;
+		}
+	}
+
+	return true;
+}
diff --git a/suite/cstest/src/test_detail_tricore.c b/suite/cstest/src/test_detail_tricore.c
new file mode 100644
index 000000000..899cff548
--- /dev/null
+++ b/suite/cstest/src/test_detail_tricore.c
@@ -0,0 +1,109 @@
+// Copyright © 2024 Rot127 <unisono@quyllur.org>
+// SPDX-License-Identifier: BSD-3
+
+#include "test_compare.h"
+#include "test_detail_tricore.h"
+#include <capstone/capstone.h>
+#include <stdio.h>
+#include <string.h>
+
+TestDetailTriCore *test_detail_tricore_new()
+{
+	return cs_mem_calloc(sizeof(TestDetailTriCore), 1);
+}
+
+void test_detail_tricore_free(TestDetailTriCore *detail)
+{
+	if (!detail) {
+		return;
+	}
+	for (size_t i = 0; i < detail->operands_count; ++i) {
+		test_detail_tricore_op_free(detail->operands[i]);
+	}
+	cs_mem_free(detail->operands);
+	cs_mem_free(detail);
+}
+
+TestDetailTriCore *test_detail_tricore_clone(const TestDetailTriCore *detail)
+{
+	TestDetailTriCore *clone = test_detail_tricore_new();
+	clone->update_flags = detail->update_flags;
+
+	clone->operands_count = detail->operands_count;
+	if (detail->operands_count > 0) {
+		clone->operands = cs_mem_calloc(sizeof(TestDetailTriCoreOp *),
+						detail->operands_count);
+	}
+	for (size_t i = 0; i < detail->operands_count; ++i) {
+		clone->operands[i] =
+			test_detail_tricore_op_clone(detail->operands[i]);
+	}
+
+	return clone;
+}
+
+TestDetailTriCoreOp *test_detail_tricore_op_new()
+{
+	return cs_mem_calloc(sizeof(TestDetailTriCoreOp), 1);
+}
+
+TestDetailTriCoreOp *test_detail_tricore_op_clone(const TestDetailTriCoreOp *op)
+{
+	TestDetailTriCoreOp *clone = test_detail_tricore_op_new();
+
+	clone->type = op->type ? strdup(op->type) : NULL;
+	clone->access = op->access ? strdup(op->access) : NULL;
+	clone->reg = op->reg ? strdup(op->reg) : NULL;
+	clone->imm = op->imm;
+	clone->mem_base = op->mem_base ? strdup(op->mem_base) : NULL;
+	clone->mem_disp = op->mem_disp;
+
+	return clone;
+}
+
+void test_detail_tricore_op_free(TestDetailTriCoreOp *op)
+{
+	if (!op) {
+		return;
+	}
+	cs_mem_free(op->type);
+	cs_mem_free(op->access);
+	cs_mem_free(op->reg);
+	cs_mem_free(op->mem_base);
+	cs_mem_free(op);
+}
+
+bool test_expected_tricore(csh *handle, const cs_tricore *actual,
+			   const TestDetailTriCore *expected)
+{
+	assert(handle && actual && expected);
+
+	compare_uint8_ret(actual->op_count, expected->operands_count, false);
+	compare_tbool_ret(actual->update_flags, expected->update_flags, false);
+	for (size_t i = 0; i < actual->op_count; ++i) {
+		const cs_tricore_op *op = &actual->operands[i];
+		TestDetailTriCoreOp *eop = expected->operands[i];
+		compare_enum_ret(op->type, eop->type, false);
+		compare_enum_ret(op->access, eop->access, false);
+		switch (op->type) {
+		default:
+			fprintf(stderr,
+				"tricore op type %" PRId32 " not handled.\n",
+				op->type);
+			return false;
+		case TRICORE_OP_REG:
+			compare_reg_ret(*handle, op->reg, eop->reg, false);
+			break;
+		case TRICORE_OP_IMM:
+			compare_int64_ret(op->imm, eop->imm, false);
+			break;
+		case TRICORE_OP_MEM:
+			compare_reg_ret(*handle, op->mem.base, eop->mem_base,
+					false);
+			compare_int64_ret(op->mem.disp, eop->mem_disp, false);
+			break;
+		}
+	}
+
+	return true;
+}
diff --git a/suite/cstest/src/test_detail_wasm.c b/suite/cstest/src/test_detail_wasm.c
new file mode 100644
index 000000000..a5dcd9381
--- /dev/null
+++ b/suite/cstest/src/test_detail_wasm.c
@@ -0,0 +1,128 @@
+// Copyright © 2024 Rot127 <unisono@quyllur.org>
+// SPDX-License-Identifier: BSD-3
+
+#include "test_compare.h"
+#include "test_detail_wasm.h"
+#include <capstone/capstone.h>
+#include <stdio.h>
+#include <string.h>
+
+TestDetailWASM *test_detail_wasm_new()
+{
+	return cs_mem_calloc(sizeof(TestDetailWASM), 1);
+}
+
+void test_detail_wasm_free(TestDetailWASM *detail)
+{
+	if (!detail) {
+		return;
+	}
+	for (size_t i = 0; i < detail->operands_count; ++i) {
+		test_detail_wasm_op_free(detail->operands[i]);
+	}
+	cs_mem_free(detail->operands);
+	cs_mem_free(detail);
+}
+
+TestDetailWASM *test_detail_wasm_clone(const TestDetailWASM *detail)
+{
+	TestDetailWASM *clone = test_detail_wasm_new();
+
+	clone->operands_count = detail->operands_count;
+	if (detail->operands_count > 0) {
+		clone->operands = cs_mem_calloc(sizeof(TestDetailWASMOp *),
+						detail->operands_count);
+	}
+	for (size_t i = 0; i < detail->operands_count; ++i) {
+		clone->operands[i] =
+			test_detail_wasm_op_clone(detail->operands[i]);
+	}
+
+	return clone;
+}
+
+TestDetailWASMOp *test_detail_wasm_op_new()
+{
+	return cs_mem_calloc(sizeof(TestDetailWASMOp), 1);
+}
+
+TestDetailWASMOp *test_detail_wasm_op_clone(const TestDetailWASMOp *op)
+{
+	TestDetailWASMOp *clone = test_detail_wasm_op_new();
+
+	clone->type = op->type ? strdup(op->type) : NULL;
+	clone->size = op->size;
+	clone->int7 = op->int7;
+	clone->varuint32 = op->varuint32;
+	clone->varuint64 = op->varuint64;
+	clone->uint32 = op->uint32;
+	clone->uint64 = op->uint64;
+	clone->immediate_0 = op->immediate_0;
+	clone->immediate_1 = op->immediate_1;
+	clone->brt_length = op->brt_length;
+	clone->brt_address = op->brt_address;
+	clone->brt_default_target = op->brt_default_target;
+	return clone;
+}
+
+void test_detail_wasm_op_free(TestDetailWASMOp *op)
+{
+	if (!op) {
+		return;
+	}
+	cs_mem_free(op->type);
+	cs_mem_free(op);
+}
+
+bool test_expected_wasm(csh *handle, const cs_wasm *actual,
+			const TestDetailWASM *expected)
+{
+	assert(handle && actual && expected);
+
+	compare_uint8_ret(actual->op_count, expected->operands_count, false);
+	for (size_t i = 0; i < actual->op_count; ++i) {
+		const cs_wasm_op *op = &actual->operands[i];
+		TestDetailWASMOp *eop = expected->operands[i];
+		compare_enum_ret(op->type, eop->type, false);
+		switch (op->type) {
+		default:
+			fprintf(stderr,
+				"WASM op type %" PRId32 " not handled.\n",
+				op->type);
+			return false;
+		case WASM_OP_INT7:
+			compare_int8_ret(op->int7, eop->int7, false);
+			break;
+		case WASM_OP_VARUINT32:
+			compare_uint32_ret(op->varuint32, eop->varuint32,
+					   false);
+			break;
+		case WASM_OP_VARUINT64:
+			compare_uint64_ret(op->varuint64, eop->varuint64,
+					   false);
+			break;
+		case WASM_OP_UINT32:
+			compare_uint32_ret(op->uint32, eop->uint32, false);
+			break;
+		case WASM_OP_UINT64:
+			compare_uint64_ret(op->uint64, eop->uint64, false);
+			break;
+		case WASM_OP_IMM:
+			compare_uint32_ret(op->immediate[0], eop->immediate_0,
+					   false);
+			compare_uint32_ret(op->immediate[1], eop->immediate_1,
+					   false);
+			break;
+		case WASM_OP_BRTABLE:
+			compare_uint32_ret(op->brtable.length, eop->brt_length,
+					   false);
+			compare_uint32_ret(op->brtable.default_target,
+					   eop->brt_default_target, false);
+			compare_uint64_ret(op->brtable.address,
+					   eop->brt_address, false);
+			break;
+		}
+	}
+
+	return true;
+}
diff --git a/suite/cstest/src/test_detail_x86.c b/suite/cstest/src/test_detail_x86.c
new file mode 100644
index 000000000..b7a383651
--- /dev/null
+++ b/suite/cstest/src/test_detail_x86.c
@@ -0,0 +1,264 @@
+// Copyright © 2024 Rot127 <unisono@quyllur.org>
+// SPDX-License-Identifier: BSD-3
+
+#include "test_compare.h"
+#include "test_detail_x86.h"
+#include <capstone/capstone.h>
+#include <stdio.h>
+#include <string.h>
+
+TestDetailX86 *test_detail_x86_new()
+{
+	return cs_mem_calloc(sizeof(TestDetailX86), 1);
+}
+
+void test_detail_x86_free(TestDetailX86 *detail)
+{
+	if (!detail) {
+		return;
+	}
+	if (detail->prefix[0]) {
+		for (size_t i = 0; i < ARR_SIZE(detail->prefix); ++i) {
+			cs_mem_free(detail->prefix[i]);
+		}
+	}
+	for (size_t i = 0; i < detail->eflags_count; ++i) {
+		cs_mem_free(detail->eflags[i]);
+	}
+	cs_mem_free(detail->eflags);
+	for (size_t i = 0; i < detail->fpu_flags_count; ++i) {
+		cs_mem_free(detail->fpu_flags[i]);
+	}
+	cs_mem_free(detail->fpu_flags);
+	for (size_t i = 0; i < detail->operands_count; ++i) {
+		test_detail_x86_op_free(detail->operands[i]);
+	}
+	cs_mem_free(detail->operands);
+
+	cs_mem_free(detail->sib_index);
+	cs_mem_free(detail->sib_base);
+	cs_mem_free(detail->xop_cc);
+	cs_mem_free(detail->sse_cc);
+	cs_mem_free(detail->avx_cc);
+	cs_mem_free(detail->avx_rm);
+	cs_mem_free(detail);
+}
+
+TestDetailX86 *test_detail_x86_clone(TestDetailX86 *detail)
+{
+	TestDetailX86 *clone = test_detail_x86_new();
+	clone->sib_index = detail->sib_index ? strdup(detail->sib_index) : NULL;
+	clone->sib_base = detail->sib_base ? strdup(detail->sib_base) : NULL;
+	clone->xop_cc = detail->xop_cc ? strdup(detail->xop_cc) : NULL;
+	clone->sse_cc = detail->sse_cc ? strdup(detail->sse_cc) : NULL;
+	clone->avx_cc = detail->avx_cc ? strdup(detail->avx_cc) : NULL;
+	clone->avx_rm = detail->avx_rm ? strdup(detail->avx_rm) : NULL;
+
+	if (detail->prefix[0]) {
+		for (size_t i = 0; i < ARR_SIZE(clone->prefix); ++i) {
+			clone->prefix[i] = strdup(detail->prefix[i]);
+		}
+	}
+	memcpy(clone->opcode, detail->opcode, sizeof(clone->opcode));
+
+	clone->rex = detail->rex;
+	clone->addr_size = detail->addr_size;
+	clone->modrm = detail->modrm;
+	clone->sib = detail->sib;
+	clone->disp = detail->disp;
+	clone->sib_scale = detail->sib_scale;
+	clone->avx_sae = detail->avx_sae;
+
+	clone->enc_modrm_offset = detail->enc_modrm_offset;
+	clone->enc_disp_offset = detail->enc_disp_offset;
+	clone->enc_disp_size = detail->enc_disp_size;
+	clone->enc_imm_offset = detail->enc_imm_offset;
+	clone->enc_imm_size = detail->enc_imm_size;
+
+	clone->eflags_count = detail->eflags_count;
+	clone->eflags = detail->eflags ? cs_mem_calloc(sizeof(char *),
+						       detail->eflags_count) :
+					 NULL;
+	for (size_t i = 0; i < detail->eflags_count; ++i) {
+		clone->eflags[i] =
+			detail->eflags[i] ? strdup(detail->eflags[i]) : NULL;
+	}
+
+	clone->fpu_flags_count = detail->fpu_flags_count;
+	clone->fpu_flags =
+		detail->fpu_flags ?
+			cs_mem_calloc(sizeof(char *), detail->fpu_flags_count) :
+			NULL;
+	for (size_t i = 0; i < detail->fpu_flags_count; ++i) {
+		clone->fpu_flags[i] = detail->fpu_flags[i] ?
+					      strdup(detail->fpu_flags[i]) :
+					      NULL;
+	}
+
+	clone->operands_count = detail->operands_count;
+	clone->operands = detail->operands_count > 0 ?
+				  cs_mem_calloc(sizeof(TestDetailX86Op *),
+						detail->operands_count) :
+				  NULL;
+	for (size_t i = 0; i < detail->operands_count; ++i) {
+		clone->operands[i] =
+			test_detail_x86_op_clone(detail->operands[i]);
+	}
+
+	return clone;
+}
+
+TestDetailX86Op *test_detail_x86_op_new()
+{
+	return cs_mem_calloc(sizeof(TestDetailX86Op), 1);
+}
+
+TestDetailX86Op *test_detail_x86_op_clone(TestDetailX86Op *op)
+{
+	TestDetailX86Op *clone = test_detail_x86_op_new();
+
+	clone->size = op->size;
+	clone->type = op->type ? strdup(op->type) : NULL;
+	clone->access = op->access ? strdup(op->access) : NULL;
+	clone->reg = op->reg ? strdup(op->reg) : NULL;
+	clone->imm = op->imm;
+	clone->mem_segment = op->mem_segment ? strdup(op->mem_segment) : NULL;
+	clone->mem_base = op->mem_base ? strdup(op->mem_base) : NULL;
+	clone->mem_index = op->mem_index ? strdup(op->mem_index) : NULL;
+	clone->mem_scale = op->mem_scale;
+	clone->mem_disp = op->mem_disp;
+	clone->avx_bcast = op->avx_bcast ? strdup(op->avx_bcast) : NULL;
+	clone->avx_zero_opmask = op->avx_zero_opmask;
+
+	return clone;
+}
+
+void test_detail_x86_op_free(TestDetailX86Op *op)
+{
+	if (!op) {
+		return;
+	}
+	cs_mem_free(op->type);
+	cs_mem_free(op->access);
+	cs_mem_free(op->reg);
+	cs_mem_free(op->mem_segment);
+	cs_mem_free(op->mem_base);
+	cs_mem_free(op->mem_index);
+	cs_mem_free(op->avx_bcast);
+	cs_mem_free(op);
+}
+
+bool test_expected_x86(csh *handle, cs_x86 *actual, TestDetailX86 *expected)
+{
+	assert(handle && actual && expected);
+
+	compare_reg_ret(*handle, actual->sib_index, expected->sib_index, false);
+	compare_reg_ret(*handle, actual->sib_base, expected->sib_base, false);
+
+	compare_enum_ret(actual->xop_cc, expected->xop_cc, false);
+	compare_enum_ret(actual->sse_cc, expected->sse_cc, false);
+	compare_enum_ret(actual->avx_cc, expected->avx_cc, false);
+	compare_enum_ret(actual->avx_rm, expected->avx_rm, false);
+
+	if (expected->rex) {
+		compare_uint8_ret(actual->rex, expected->rex, false);
+	}
+	if (expected->addr_size) {
+		compare_uint8_ret(actual->addr_size, expected->addr_size, false);
+	}
+	if (expected->modrm) {
+		compare_uint8_ret(actual->modrm, expected->modrm, false);
+	}
+	if (expected->sib) {
+		compare_uint8_ret(actual->sib, expected->sib, false);
+	}
+	if (expected->disp) {
+		compare_int64_ret(actual->disp, expected->disp, false);
+	}
+	if (expected->sib_scale) {
+		compare_int8_ret(actual->sib_scale, expected->sib_scale, false);
+	}
+	compare_tbool_ret(actual->avx_sae, expected->avx_sae, false);
+
+	for (size_t i = 0; i < ARR_SIZE(actual->prefix); ++i) {
+		compare_enum_ret(actual->prefix[i], expected->prefix[i],
+				  false);
+	}
+	for (size_t i = 0; i < ARR_SIZE(actual->opcode); ++i) {
+		if (expected->opcode[i] != 0) {
+			compare_uint8_ret(actual->opcode[i], expected->opcode[i],
+					  false);
+		}
+	}
+
+	compare_bit_flags_64_ret(actual->eflags, expected->eflags,
+				 expected->eflags_count, false);
+	compare_bit_flags_64_ret(actual->fpu_flags, expected->fpu_flags,
+				 expected->fpu_flags_count, false);
+
+	if (expected->enc_modrm_offset) {
+		compare_uint8_ret(actual->encoding.modrm_offset,
+				  expected->enc_modrm_offset, false);
+	}
+	if (expected->enc_disp_offset) {
+		compare_uint8_ret(actual->encoding.disp_offset,
+				  expected->enc_disp_offset, false);
+	}
+	if (expected->enc_disp_size) {
+		compare_uint8_ret(actual->encoding.disp_size,
+				  expected->enc_disp_size, false);
+	}
+	if (expected->enc_imm_offset) {
+		compare_uint8_ret(actual->encoding.imm_offset,
+				  expected->enc_imm_offset, false);
+	}
+	if (expected->enc_imm_size) {
+		compare_uint8_ret(actual->encoding.imm_size,
+				  expected->enc_imm_size, false);
+	}
+
+	if (expected->operands_count == 0) {
+		return true;
+	}
+	compare_uint8_ret(actual->op_count, expected->operands_count, false);
+
+	for (size_t i = 0; i < actual->op_count; ++i) {
+		cs_x86_op *op = &actual->operands[i];
+		TestDetailX86Op *eop = expected->operands[i];
+		compare_enum_ret(op->type, eop->type, false);
+		compare_enum_ret(op->access, eop->access, false);
+		compare_enum_ret(op->avx_bcast, eop->avx_bcast, false);
+		compare_tbool_ret(op->avx_zero_opmask, eop->avx_zero_opmask,
+				  false);
+		switch (op->type) {
+		default:
+			fprintf(stderr,
+				"arm op type %" PRId32 " not handled.\n",
+				op->type);
+			return false;
+		case X86_OP_REG:
+			compare_reg_ret(*handle, op->reg, eop->reg, false);
+			break;
+		case X86_OP_IMM:
+			compare_int64_ret(op->imm, eop->imm, false);
+			break;
+		case X86_OP_MEM:
+			compare_reg_ret(*handle, op->mem.segment,
+					eop->mem_segment, false);
+			compare_reg_ret(*handle, op->mem.base, eop->mem_base,
+					false);
+			compare_reg_ret(*handle, op->mem.index, eop->mem_index,
+					false);
+			if (eop->mem_disp) {
+				compare_int64_ret(op->mem.disp, eop->mem_disp, false);
+			}
+			if (eop->mem_scale) {
+				compare_int_ret(op->mem.scale, eop->mem_scale,
+						false);
+			}
+			break;
+		}
+	}
+
+	return true;
+}
diff --git a/suite/cstest/src/test_detail_xcore.c b/suite/cstest/src/test_detail_xcore.c
new file mode 100644
index 000000000..2eda4d306
--- /dev/null
+++ b/suite/cstest/src/test_detail_xcore.c
@@ -0,0 +1,113 @@
+// Copyright © 2024 Rot127 <unisono@quyllur.org>
+// SPDX-License-Identifier: BSD-3
+
+#include "test_compare.h"
+#include "test_detail_xcore.h"
+#include <capstone/capstone.h>
+#include <stdio.h>
+#include <string.h>
+
+TestDetailXCore *test_detail_xcore_new()
+{
+	return cs_mem_calloc(sizeof(TestDetailXCore), 1);
+}
+
+void test_detail_xcore_free(TestDetailXCore *detail)
+{
+	if (!detail) {
+		return;
+	}
+	for (size_t i = 0; i < detail->operands_count; ++i) {
+		test_detail_xcore_op_free(detail->operands[i]);
+	}
+	cs_mem_free(detail->operands);
+	cs_mem_free(detail);
+}
+
+TestDetailXCore *test_detail_xcore_clone(const TestDetailXCore *detail)
+{
+	TestDetailXCore *clone = test_detail_xcore_new();
+
+	clone->operands_count = detail->operands_count;
+	if (detail->operands_count > 0) {
+		clone->operands = cs_mem_calloc(sizeof(TestDetailXCoreOp *),
+						detail->operands_count);
+	}
+	for (size_t i = 0; i < detail->operands_count; ++i) {
+		clone->operands[i] =
+			test_detail_xcore_op_clone(detail->operands[i]);
+	}
+
+	return clone;
+}
+
+TestDetailXCoreOp *test_detail_xcore_op_new()
+{
+	return cs_mem_calloc(sizeof(TestDetailXCoreOp), 1);
+}
+
+TestDetailXCoreOp *test_detail_xcore_op_clone(const TestDetailXCoreOp *op)
+{
+	TestDetailXCoreOp *clone = test_detail_xcore_op_new();
+
+	clone->type = op->type ? strdup(op->type) : NULL;
+	clone->reg = op->reg ? strdup(op->reg) : NULL;
+	clone->imm = op->imm;
+	clone->mem_base = op->mem_base ? strdup(op->mem_base) : NULL;
+	clone->mem_index = op->mem_index ? strdup(op->mem_index) : NULL;
+	clone->mem_disp = op->mem_disp;
+	clone->mem_direct = op->mem_direct;
+
+	return clone;
+}
+
+void test_detail_xcore_op_free(TestDetailXCoreOp *op)
+{
+	if (!op) {
+		return;
+	}
+	cs_mem_free(op->type);
+	cs_mem_free(op->reg);
+	cs_mem_free(op->mem_base);
+	cs_mem_free(op->mem_index);
+	cs_mem_free(op);
+}
+
+bool test_expected_xcore(csh *handle, const cs_xcore *actual,
+			 const TestDetailXCore *expected)
+{
+	assert(handle && actual && expected);
+
+	compare_uint8_ret(actual->op_count, expected->operands_count, false);
+	for (size_t i = 0; i < actual->op_count; ++i) {
+		const cs_xcore_op *op = &actual->operands[i];
+		TestDetailXCoreOp *eop = expected->operands[i];
+		compare_enum_ret(op->type, eop->type, false);
+		switch (op->type) {
+		default:
+			fprintf(stderr,
+				"arm op type %" PRId32 " not handled.\n",
+				op->type);
+			return false;
+		case XCORE_OP_REG:
+			compare_reg_ret(*handle, op->reg, eop->reg, false);
+			break;
+		case XCORE_OP_IMM:
+			compare_int32_ret(op->imm, eop->imm, false);
+			break;
+		case XCORE_OP_MEM:
+			compare_reg_ret(*handle, op->mem.base, eop->mem_base,
+					false);
+			compare_reg_ret(*handle, op->mem.index, eop->mem_index,
+					false);
+			compare_int_ret(op->mem.disp, eop->mem_disp, false);
+			if (eop->mem_direct) {
+				compare_int_ret(op->mem.direct, eop->mem_direct,
+						false);
+			}
+			break;
+		}
+	}
+
+	return true;
+}
diff --git a/suite/cstest/src/test_run.c b/suite/cstest/src/test_run.c
new file mode 100644
index 000000000..36e2b0a59
--- /dev/null
+++ b/suite/cstest/src/test_run.c
@@ -0,0 +1,323 @@
+// Copyright © 2024 Rot127 <unisono@quyllur.org>
+// SPDX-License-Identifier: BSD-3
+
+#include "test_run.h"
+#include "test_case.h"
+#include "test_mapping.h"
+#include "../../../utils.h"
+#include <stdarg.h>
+#include <stddef.h>
+#include <setjmp.h>
+#include "cmocka.h"
+#include <capstone/capstone.h>
+#include <stdbool.h>
+#include <stdio.h>
+
+static TestRunResult get_test_run_result(TestRunStats *stats)
+{
+	if (stats->tc_total !=
+	    stats->successful + stats->failed + stats->skipped) {
+		fprintf(stderr,
+			"[!] Inconsistent statistics: total != successful + failed + skipped\n");
+		stats->errors++;
+		return TEST_RUN_ERROR;
+	}
+
+	if (stats->errors != 0) {
+		return TEST_RUN_ERROR;
+	} else if (stats->failed != 0) {
+		return TEST_RUN_FAILURE;
+	}
+	return TEST_RUN_SUCCESS;
+}
+
+/// Extract all test cases from the given test files.
+static TestFile **parse_test_files(char **tf_paths, uint32_t path_count,
+				   TestRunStats *stats)
+{
+	TestFile **files = NULL;
+	stats->tc_total = 0;
+
+	for (size_t i = 0; i < path_count; ++i) {
+		TestFile *test_file_data = NULL;
+		cyaml_err_t err = cyaml_load_file(
+			tf_paths[i], &cyaml_config, &test_file_schema,
+			(cyaml_data_t **)&test_file_data, NULL);
+
+		if (err != CYAML_OK || !test_file_data) {
+			fprintf(stderr, "[!] Failed to parse test file '%s'\n",
+				tf_paths[i]);
+			fprintf(stderr, "[!] Error: '%s'\n",
+				!test_file_data && err == CYAML_OK ?
+					"Empty file" :
+					cyaml_strerror(err));
+			stats->invalid_files++;
+			stats->errors++;
+			continue;
+		}
+
+		size_t k = stats->valid_test_files++;
+		// Copy all test cases of a test file
+		files = cs_mem_realloc(files, sizeof(TestFile *) *
+						      stats->valid_test_files);
+
+		files[k] = test_file_clone(test_file_data);
+		assert(files[k]);
+		stats->tc_total += files[k]->test_cases_count;
+		files[k]->filename = strrchr(tf_paths[i], '/') ?
+					     strdup(strrchr(tf_paths[i], '/')) :
+					     strdup(tf_paths[i]);
+
+		err = cyaml_free(&cyaml_config, &test_file_schema,
+				 test_file_data, 0);
+		if (err != CYAML_OK) {
+			fprintf(stderr, "[!] Error: '%s'\n",
+				cyaml_strerror(err));
+			stats->errors++;
+			continue;
+		}
+	}
+
+	return files;
+}
+
+/// Parses the @input and saves the results in the other arguments.
+static bool parse_input_options(const TestInput *input, cs_arch *arch,
+				cs_mode *mode, cs_opt *opt_arr,
+				size_t opt_arr_size, size_t *opt_set)
+{
+	assert(input && arch && mode && opt_arr);
+	bool arch_found = false;
+	const char *opt_str = input->arch;
+
+	int val = enum_map_bin_search(test_arch_map, ARR_SIZE(test_arch_map),
+				      opt_str, &arch_found);
+	if (arch_found) {
+		*arch = val;
+	} else {
+		fprintf(stderr,
+			"[!] '%s' is not mapped to a capstone architecture.\n",
+			input->arch);
+		return false;
+	}
+
+	*mode = 0;
+	bool mode_found = false;
+	size_t opt_idx = 0;
+	char **options = input->options;
+	for (size_t i = 0; i < input->options_count; ++i) {
+		opt_str = options[i];
+		val = enum_map_bin_search(test_mode_map,
+					  ARR_SIZE(test_mode_map), opt_str,
+					  &mode_found);
+		if (mode_found) {
+			*mode |= val;
+			goto next_option;
+		}
+
+		// Might be an option descriptor
+		for (size_t k = 0; k < ARR_SIZE(test_option_map); k++) {
+			if (strings_match(opt_str, test_option_map[k].str)) {
+				if (opt_idx >= opt_arr_size) {
+					fprintf(stderr,
+						"Too many options given in: '%s'. Maximum is: %" PRId64
+						"\n",
+						opt_str, opt_arr_size);
+					return false;
+				}
+				opt_arr[opt_idx++] = test_option_map[k].opt;
+				goto next_option;
+			}
+		}
+		fprintf(stderr, "[!] Option: '%s' not used\n", opt_str);
+next_option:
+		continue;
+	}
+	*opt_set = opt_idx;
+	return true;
+}
+
+/// Parses the options for cs_open/cs_option and initializes the handle.
+/// Returns true for success and false otherwise.
+static bool open_cs_handle(UnitTestState *ustate)
+{
+	cs_arch arch = 0;
+	cs_mode mode = 0;
+	cs_opt options[8] = { 0 };
+	size_t options_set = 0;
+
+	if (!parse_input_options(ustate->tcase->input, &arch, &mode, options, 8,
+				 &options_set)) {
+		char *tc_str = test_input_stringify(ustate->tcase->input, "");
+		fprintf(stderr, "Could not parse options: %s\n", tc_str);
+		cs_mem_free(tc_str);
+		return false;
+	}
+
+	cs_err err = cs_open(arch, mode, &ustate->handle);
+	if (err != CS_ERR_OK) {
+		char *tc_str = test_input_stringify(ustate->tcase->input, "");
+		fprintf(stderr,
+			"[!] cs_open() failed with: '%s'. TestInput: %s\n",
+			cs_strerror(err), tc_str);
+		cs_mem_free(tc_str);
+		return false;
+	}
+
+	// The bit mode must be set, otherwise the numbers are
+	// not normalized correctly in the asm-test comparison step.
+	if (arch == CS_ARCH_AARCH64 || mode & CS_MODE_64) {
+		ustate->arch_bits = 64;
+	} else if (mode & CS_MODE_16) {
+		ustate->arch_bits = 16;
+	} else {
+		ustate->arch_bits = 32;
+	}
+	if (err != CS_ERR_OK) {
+		goto option_error;
+	}
+
+	if (err != CS_ERR_OK) {
+		goto option_error;
+	}
+	for (size_t i = 0; i < options_set; ++i) {
+		err = cs_option(ustate->handle, options[i].type,
+				options[i].val);
+		if (err != CS_ERR_OK) {
+			goto option_error;
+		}
+	}
+	return true;
+
+option_error: {
+	char *tc_str = test_input_stringify(ustate->tcase->input, "");
+	fprintf(stderr, "[!] cs_option() failed with: '%s'. TestInput: %s\n",
+		cs_strerror(err), tc_str);
+	cs_mem_free(tc_str);
+	cs_close(&ustate->handle);
+	return false;
+}
+}
+
+static int cstest_unit_test_setup(void **state)
+{
+	assert(state);
+	UnitTestState *ustate = *state;
+	assert(ustate->tcase);
+	if (!open_cs_handle(ustate)) {
+		fail_msg("Failed to initialize Capstone with given options.");
+		return -1;
+	}
+	return 0;
+}
+
+static int cstest_unit_test_teardown(void **state)
+{
+	if (!state) {
+		return 0;
+	}
+	UnitTestState *ustate = *state;
+	if (ustate->handle) {
+		cs_err err = cs_close(&ustate->handle);
+		if (err != CS_ERR_OK) {
+			fail_msg("cs_close() failed with: '%s'.",
+				 cs_strerror(err));
+			return -1;
+		}
+	}
+	return 0;
+}
+
+static void cstest_unit_test(void **state)
+{
+	assert(state);
+	UnitTestState *ustate = *state;
+	assert(ustate);
+	assert(ustate->handle);
+	assert(ustate->tcase);
+	csh handle = ustate->handle;
+	TestCase *tcase = ustate->tcase;
+
+	cs_insn *insns = NULL;
+	size_t insns_count = cs_disasm(handle, tcase->input->bytes,
+				       tcase->input->bytes_count,
+				       tcase->input->address, 0, &insns);
+	test_expected_compare(&ustate->handle, tcase->expected, insns,
+			      insns_count, ustate->arch_bits);
+	cs_free(insns, insns_count);
+}
+
+static void eval_test_cases(TestFile **test_files, TestRunStats *stats)
+{
+	assert(test_files && stats);
+	// CMocka's API doesn't allow to init a CMUnitTest with a partially initialized state
+	// (which is later initialized in the test setup).
+	// So we do it manually here.
+	struct CMUnitTest *utest_table =
+		cs_mem_calloc(sizeof(struct CMUnitTest),
+			      stats->tc_total); // Number of test cases.
+
+	char utest_id[128] = { 0 };
+
+	size_t tci = 0;
+	for (size_t i = 0; i < stats->valid_test_files; ++i) {
+		TestCase **test_cases = test_files[i]->test_cases;
+		const char *filename = test_files[i]->filename ?
+					       test_files[i]->filename :
+					       NULL;
+
+		for (size_t k = 0; k < test_files[i]->test_cases_count;
+		     ++k, ++tci) {
+			cs_snprintf(utest_id, sizeof(utest_id),
+				    "%s - TC #%" PRIx32 ": ", filename, k);
+			if (test_cases[k]->skip) {
+				char *tc_name = test_input_stringify(
+					test_cases[k]->input, utest_id);
+				fprintf(stderr, "SKIP: %s\nReason: %s\n",
+					tc_name, test_cases[k]->skip_reason);
+				cs_mem_free(tc_name);
+				stats->skipped++;
+				continue;
+			}
+
+			UnitTestState *ut_state =
+				cs_mem_calloc(sizeof(UnitTestState), 1);
+			ut_state->tcase = test_cases[k];
+			utest_table[tci].name = test_input_stringify(
+				ut_state->tcase->input, utest_id);
+			utest_table[tci].initial_state = ut_state;
+			utest_table[tci].setup_func = cstest_unit_test_setup;
+			utest_table[tci].teardown_func =
+				cstest_unit_test_teardown;
+			utest_table[tci].test_func = cstest_unit_test;
+		}
+	}
+	// Use private function here, because the API takes only constant tables.
+	int failed_tests = _cmocka_run_group_tests(
+		"All test cases", utest_table, stats->tc_total, NULL, NULL);
+	for (size_t i = 0; i < stats->tc_total; ++i) {
+		cs_mem_free((char *)utest_table[i].name);
+		cs_mem_free(utest_table[i].initial_state);
+	}
+	cs_mem_free(utest_table);
+	stats->failed += failed_tests;
+	stats->successful += stats->tc_total - failed_tests - stats->skipped;
+}
+
+/// Runs runs all valid tests in the given @test_files
+/// and returns the result as well as statistics in @stats.
+TestRunResult cstest_run_tests(char **test_file_paths, uint32_t path_count,
+			       TestRunStats *stats)
+{
+	TestFile **files = parse_test_files(test_file_paths, path_count, stats);
+	if (!files) {
+		return get_test_run_result(stats);
+	}
+	eval_test_cases(files, stats);
+	for (size_t i = 0; i < stats->valid_test_files; ++i) {
+		test_file_free(files[i]);
+	}
+	cs_mem_free(files);
+
+	return get_test_run_result(stats);
+}
diff --git a/suite/cstest/src/tms320c64x_detail.c b/suite/cstest/src/tms320c64x_detail.c
deleted file mode 100644
index f6b0b9185..000000000
--- a/suite/cstest/src/tms320c64x_detail.c
+++ /dev/null
@@ -1,107 +0,0 @@
-/* Capstone testing regression */
-/* By Do Minh Tuan <tuanit96@gmail.com>, 02-2019 */
-
-
-#include "factory.h"
-
-char *get_detail_tms320c64x(csh *handle, cs_mode mode, cs_insn *ins)
-{
-	cs_tms320c64x *tms320c64x;
-	int i;
-	char *result;
-
-	result = (char *)malloc(sizeof(char));
-	result[0] = '\0';
-
-	if (ins->detail == NULL)
-		return result;
-
-	tms320c64x = &(ins->detail->tms320c64x);
-	if (tms320c64x->op_count)
-		add_str(&result, " ; op_count: %u", tms320c64x->op_count);
-
-	for (i = 0; i < tms320c64x->op_count; i++) {
-		cs_tms320c64x_op *op = &(tms320c64x->operands[i]);
-		switch((int)op->type) {
-			default:
-				break;
-			case TMS320C64X_OP_REG:
-				add_str(&result, " ; operands[%u].type: REG = %s", i, cs_reg_name(*handle, op->reg));
-				break;
-			case TMS320C64X_OP_IMM:
-				add_str(&result, " ; operands[%u].type: IMM = 0x%x", i, op->imm);
-				break;
-			case TMS320C64X_OP_MEM:
-				add_str(&result, " ; operands[%u].type: MEM", i);
-				if (op->mem.base != TMS320C64X_REG_INVALID)
-					add_str(&result, " ; operands[%u].mem.base: REG = %s", i, cs_reg_name(*handle, op->mem.base));
-				add_str(&result, " ; operands[%u].mem.disptype: ", i);
-				if (op->mem.disptype == TMS320C64X_MEM_DISP_INVALID) {
-					add_str(&result, "Invalid");
-					add_str(&result, " ; operands[%u].mem.disp: %u", i, op->mem.disp);
-				}
-				if (op->mem.disptype == TMS320C64X_MEM_DISP_CONSTANT) {
-					add_str(&result, "Constant");
-					add_str(&result, " ; operands[%u].mem.disp: %u", i, op->mem.disp);
-				}
-				if (op->mem.disptype == TMS320C64X_MEM_DISP_REGISTER) {
-					add_str(&result, "Register");
-					add_str(&result, " ; operands[%u].mem.disp: %s", i, cs_reg_name(*handle, op->mem.disp));
-				}
-				add_str(&result, " ; operands[%u].mem.unit: %u", i, op->mem.unit);
-				add_str(&result, " ; operands[%u].mem.direction: ", i);
-				if (op->mem.direction == TMS320C64X_MEM_DIR_INVALID)
-					add_str(&result, "Invalid");
-				if (op->mem.direction == TMS320C64X_MEM_DIR_FW)
-					add_str(&result, "Forward");
-				if (op->mem.direction == TMS320C64X_MEM_DIR_BW)
-					add_str(&result, "Backward");
-				add_str(&result, " ; operands[%u].mem.modify: ", i);
-				if (op->mem.modify == TMS320C64X_MEM_MOD_INVALID)
-					add_str(&result, "Invalid");
-				if (op->mem.modify == TMS320C64X_MEM_MOD_NO)
-					add_str(&result, "No");
-				if (op->mem.modify == TMS320C64X_MEM_MOD_PRE)
-					add_str(&result, "Pre");
-				if (op->mem.modify == TMS320C64X_MEM_MOD_POST)
-					add_str(&result, "Post");
-				add_str(&result, " ; operands[%u].mem.scaled: %u", i, op->mem.scaled);
-
-				break;
-			case TMS320C64X_OP_REGPAIR:
-				add_str(&result, " ; operands[%u].type: REGPAIR = %s:%s", i, cs_reg_name(*handle, op->reg + 1), cs_reg_name(*handle, op->reg));
-				break;
-		}
-	}
-
-	add_str(&result, " ; Functional unit: ");
-	switch(tms320c64x->funit.unit) {
-		case TMS320C64X_FUNIT_D:
-			add_str(&result, "D%u", tms320c64x->funit.side);
-			break;
-		case TMS320C64X_FUNIT_L:
-			add_str(&result, "L%u", tms320c64x->funit.side);
-			break;
-		case TMS320C64X_FUNIT_M:
-			add_str(&result, "M%u", tms320c64x->funit.side);
-			break;
-		case TMS320C64X_FUNIT_S:
-			add_str(&result, "S%u", tms320c64x->funit.side);
-			break;
-		case TMS320C64X_FUNIT_NO:
-			add_str(&result, "No Functional Unit");
-			break;
-		default:
-			add_str(&result, "Unknown (Unit %u, Side %u)", tms320c64x->funit.unit, tms320c64x->funit.side);
-			break;
-	}
-	if (tms320c64x->funit.crosspath == 1)
-		add_str(&result, " ; Crosspath: 1");
-
-	if (tms320c64x->condition.reg != TMS320C64X_REG_INVALID)
-		add_str(&result, " ; Condition: [%c%s]", (tms320c64x->condition.zero == 1) ? '!' : ' ', cs_reg_name(*handle, tms320c64x->condition.reg));
-	add_str(&result, " ; Parallel: %s", (tms320c64x->parallel == 1) ? "true" : "false");
-
-	return result;
-}
-
diff --git a/suite/cstest/src/tricore_detail.c b/suite/cstest/src/tricore_detail.c
deleted file mode 100644
index 462d64aea..000000000
--- a/suite/cstest/src/tricore_detail.c
+++ /dev/null
@@ -1,81 +0,0 @@
-//
-// Created by aya on 3/24/23.
-//
-
-#include "factory.h"
-
-char *get_detail_tricore(csh *p_handle, cs_mode mode, cs_insn *ins)
-{
-	cs_tricore *tricore;
-	int i;
-	cs_regs regs_read, regs_write;
-	uint8_t regs_read_count, regs_write_count;
-
-	char *result;
-	result = (char *)malloc(sizeof(char));
-	result[0] = '\0';
-
-	if (ins->detail == NULL)
-		return result;
-
-	csh handle = *p_handle;
-
-	tricore = &(ins->detail->tricore);
-
-	if (tricore->op_count)
-		add_str(&result, "\top_count: %u\n", tricore->op_count);
-
-	for (i = 0; i < tricore->op_count; i++) {
-		cs_tricore_op *op = &(tricore->operands[i]);
-		switch ((int)op->type) {
-		default:
-			break;
-		case TRICORE_OP_REG:
-			add_str(&result, "\t\toperands[%u].type: REG = %s\n", i,
-				cs_reg_name(handle, op->reg));
-			break;
-		case TRICORE_OP_IMM:
-			add_str(&result, "\t\toperands[%u].type: IMM = 0x%x\n",
-				i, op->imm);
-			break;
-		case TRICORE_OP_MEM:
-			add_str(&result, "\t\toperands[%u].type: MEM\n", i);
-			if (op->mem.base != TRICORE_REG_INVALID)
-				add_str(&result,
-					"\t\t\toperands[%u].mem.base: REG = %s\n",
-					i, cs_reg_name(handle, op->mem.base));
-			if (op->mem.disp != 0)
-				add_str(&result,
-					"\t\t\toperands[%u].mem.disp: 0x%x\n",
-					i, op->mem.disp);
-			break;
-		}
-
-		// Print out all registers accessed by this instruction (either implicit or
-		// explicit)
-		if (!cs_regs_access(handle, ins, regs_read, &regs_read_count,
-				    regs_write, &regs_write_count)) {
-			if (regs_read_count) {
-				add_str(&result, "\tRegisters read:");
-				for (i = 0; i < regs_read_count; i++) {
-					add_str(&result, " %s",
-						cs_reg_name(handle,
-							    regs_read[i]));
-				}
-				add_str(&result, "\n");
-			}
-
-			if (regs_write_count) {
-				add_str(&result, "\tRegisters modified:");
-				for (i = 0; i < regs_write_count; i++) {
-					add_str(&result, " %s",
-						cs_reg_name(handle,
-							    regs_write[i]));
-				}
-				add_str(&result, "\n");
-			}
-		}
-	}
-
-	return result;
-}
diff --git a/suite/cstest/src/x86_detail.c b/suite/cstest/src/x86_detail.c
deleted file mode 100644
index 9d02bf7cc..000000000
--- a/suite/cstest/src/x86_detail.c
+++ /dev/null
@@ -1,345 +0,0 @@
-/* Capstone testing regression */
-/* By Do Minh Tuan <tuanit96@gmail.com>, 02-2019 */
-
-
-#include "factory.h"
-
-static void print_string_hex(char **result, const char *comment, unsigned char *str, size_t len)
-{
-	unsigned char *c;
-
-	add_str(result, "%s", comment);
-	for (c = str; c < str + len; c++) {
-		add_str(result, "0x%02x", *c & 0xff);
-		if (c < str + len - 1)
-			add_str(result, " ");
-	}
-
-}
-
-static const char *get_eflag_name(uint64_t flag)
-{
-	switch(flag) {
-		default:
-			return NULL;
-		case X86_EFLAGS_UNDEFINED_OF:
-			return "UNDEF_OF";
-		case X86_EFLAGS_UNDEFINED_SF:
-			return "UNDEF_SF";
-		case X86_EFLAGS_UNDEFINED_ZF:
-			return "UNDEF_ZF";
-		case X86_EFLAGS_MODIFY_AF:
-			return "MOD_AF";
-		case X86_EFLAGS_UNDEFINED_PF:
-			return "UNDEF_PF";
-		case X86_EFLAGS_MODIFY_CF:
-			return "MOD_CF";
-		case X86_EFLAGS_MODIFY_SF:
-			return "MOD_SF";
-		case X86_EFLAGS_MODIFY_ZF:
-			return "MOD_ZF";
-		case X86_EFLAGS_UNDEFINED_AF:
-			return "UNDEF_AF";
-		case X86_EFLAGS_MODIFY_PF:
-			return "MOD_PF";
-		case X86_EFLAGS_UNDEFINED_CF:
-			return "UNDEF_CF";
-		case X86_EFLAGS_MODIFY_OF:
-			return "MOD_OF";
-		case X86_EFLAGS_RESET_OF:
-			return "RESET_OF";
-		case X86_EFLAGS_RESET_CF:
-			return "RESET_CF";
-		case X86_EFLAGS_RESET_DF:
-			return "RESET_DF";
-		case X86_EFLAGS_RESET_IF:
-			return "RESET_IF";
-		case X86_EFLAGS_RESET_ZF:
-			return "RESET_ZF";
-		case X86_EFLAGS_TEST_OF:
-			return "TEST_OF";
-		case X86_EFLAGS_TEST_SF:
-			return "TEST_SF";
-		case X86_EFLAGS_TEST_ZF:
-			return "TEST_ZF";
-		case X86_EFLAGS_TEST_PF:
-			return "TEST_PF";
-		case X86_EFLAGS_TEST_CF:
-			return "TEST_CF";
-		case X86_EFLAGS_RESET_SF:
-			return "RESET_SF";
-		case X86_EFLAGS_RESET_AF:
-			return "RESET_AF";
-		case X86_EFLAGS_RESET_TF:
-			return "RESET_TF";
-		case X86_EFLAGS_RESET_NT:
-			return "RESET_NT";
-		case X86_EFLAGS_PRIOR_OF:
-			return "PRIOR_OF";
-		case X86_EFLAGS_PRIOR_SF:
-			return "PRIOR_SF";
-		case X86_EFLAGS_PRIOR_ZF:
-			return "PRIOR_ZF";
-		case X86_EFLAGS_PRIOR_AF:
-			return "PRIOR_AF";
-		case X86_EFLAGS_PRIOR_PF:
-			return "PRIOR_PF";
-		case X86_EFLAGS_PRIOR_CF:
-			return "PRIOR_CF";
-		case X86_EFLAGS_PRIOR_TF:
-			return "PRIOR_TF";
-		case X86_EFLAGS_PRIOR_IF:
-			return "PRIOR_IF";
-		case X86_EFLAGS_PRIOR_DF:
-			return "PRIOR_DF";
-		case X86_EFLAGS_TEST_NT:
-			return "TEST_NT";
-		case X86_EFLAGS_TEST_DF:
-			return "TEST_DF";
-		case X86_EFLAGS_RESET_PF:
-			return "RESET_PF";
-		case X86_EFLAGS_PRIOR_NT:
-			return "PRIOR_NT";
-		case X86_EFLAGS_MODIFY_TF:
-			return "MOD_TF";
-		case X86_EFLAGS_MODIFY_IF:
-			return "MOD_IF";
-		case X86_EFLAGS_MODIFY_DF:
-			return "MOD_DF";
-		case X86_EFLAGS_MODIFY_NT:
-			return "MOD_NT";
-		case X86_EFLAGS_MODIFY_RF:
-			return "MOD_RF";
-		case X86_EFLAGS_SET_CF:
-			return "SET_CF";
-		case X86_EFLAGS_SET_DF:
-			return "SET_DF";
-		case X86_EFLAGS_SET_IF:
-			return "SET_IF";
-		case X86_EFLAGS_SET_OF:
-			return "SET_OF";
-		case X86_EFLAGS_SET_SF:
-			return "SET_SF";
-		case X86_EFLAGS_SET_ZF:
-			return "SET_ZF";
-		case X86_EFLAGS_SET_AF:
-			return "SET_AF";
-		case X86_EFLAGS_SET_PF:
-			return "SET_PF";
-		case X86_EFLAGS_TEST_AF:
-			return "TEST_AF";
-		case X86_EFLAGS_TEST_TF:
-			return "TEST_TF";
-		case X86_EFLAGS_TEST_RF:
-			return "TEST_RF";
-		case X86_EFLAGS_RESET_0F:
-			return "RESET_0F";
-		case X86_EFLAGS_RESET_AC:
-			return "RESET_AC";
-	}
-}
-
-static const char *get_fpu_flag_name(uint64_t flag)
-{
-	switch (flag) {
-		default:
-			return NULL;
-		case X86_FPU_FLAGS_MODIFY_C0:
-			return "MOD_C0";
-		case X86_FPU_FLAGS_MODIFY_C1:
-			return "MOD_C1";
-		case X86_FPU_FLAGS_MODIFY_C2:
-			return "MOD_C2";
-		case X86_FPU_FLAGS_MODIFY_C3:
-			return "MOD_C3";
-		case X86_FPU_FLAGS_RESET_C0:
-			return "RESET_C0";
-		case X86_FPU_FLAGS_RESET_C1:
-			return "RESET_C1";
-		case X86_FPU_FLAGS_RESET_C2:
-			return "RESET_C2";
-		case X86_FPU_FLAGS_RESET_C3:
-			return "RESET_C3";
-		case X86_FPU_FLAGS_SET_C0:
-			return "SET_C0";
-		case X86_FPU_FLAGS_SET_C1:
-			return "SET_C1";
-		case X86_FPU_FLAGS_SET_C2:
-			return "SET_C2";
-		case X86_FPU_FLAGS_SET_C3:
-			return "SET_C3";
-		case X86_FPU_FLAGS_UNDEFINED_C0:
-			return "UNDEF_C0";
-		case X86_FPU_FLAGS_UNDEFINED_C1:
-			return "UNDEF_C1";
-		case X86_FPU_FLAGS_UNDEFINED_C2:
-			return "UNDEF_C2";
-		case X86_FPU_FLAGS_UNDEFINED_C3:
-			return "UNDEF_C3";
-		case X86_FPU_FLAGS_TEST_C0:
-			return "TEST_C0";
-		case X86_FPU_FLAGS_TEST_C1:
-			return "TEST_C1";
-		case X86_FPU_FLAGS_TEST_C2:
-			return "TEST_C2";
-		case X86_FPU_FLAGS_TEST_C3:
-			return "TEST_C3";
-	}
-}
-
-char *get_detail_x86(csh *ud, cs_mode mode, cs_insn *ins)
-{
-	int count, i;
-	cs_x86 *x86;
-	cs_regs regs_read, regs_write;
-	uint8_t regs_read_count, regs_write_count;
-	char *result;
-
-	result = (char *)malloc(sizeof(char));
-	result[0] = '\0';
-
-	if (ins->detail == NULL)
-		return result;
-
-	x86 = &(ins->detail->x86);
-
-	add_str(&result, " ; ID: %" PRIu32 , ins->id);
-	print_string_hex(&result, " ; Prefix:", x86->prefix, 4);
-	print_string_hex(&result, " ; Opcode:", x86->opcode, 4);
-	add_str(&result, " ; rex: 0x%x", x86->rex);
-	add_str(&result, " ; addr_size: %u", x86->addr_size);
-	add_str(&result, " ; modrm: 0x%x", x86->modrm);
-	add_str(&result, " ; disp: 0x%" PRIx64 "", x86->disp);
-
-	if ((mode & CS_MODE_16) == 0) {
-		add_str(&result, " ; sib: 0x%x", x86->sib);
-		if (x86->sib_base != X86_REG_INVALID)
-			add_str(&result, " ; sib_base: %s", cs_reg_name(*ud, x86->sib_base));
-		if (x86->sib_index != X86_REG_INVALID)
-			add_str(&result, " ; sib_index: %s", cs_reg_name(*ud, x86->sib_index));
-		if (x86->sib_scale != 0)
-			add_str(&result, " ; sib_scale: %d", x86->sib_scale);
-	}
-
-	if (x86->xop_cc != X86_XOP_CC_INVALID) {
-		add_str(&result, " ; xop_cc: %u", x86->xop_cc);
-	}
-
-	if (x86->sse_cc != X86_SSE_CC_INVALID) {
-		add_str(&result, " ; sse_cc: %u", x86->sse_cc);
-	}
-
-	if (x86->avx_cc != X86_AVX_CC_INVALID) {
-		add_str(&result, " ; avx_cc: %u", x86->avx_cc);
-	}
-
-	if (x86->avx_sae) {
-		add_str(&result, " ; avx_sae: %u", x86->avx_sae);
-	}
-
-	if (x86->avx_rm != X86_AVX_RM_INVALID) {
-		add_str(&result, " ; avx_rm: %u", x86->avx_rm);
-	}
-
-	count = cs_op_count(*ud, ins, X86_OP_IMM);
-	if (count > 0) {
-		add_str(&result, " ; imm_count: %u", count);
-		for (i = 1; i < count + 1; i++) {
-			int index = cs_op_index(*ud, ins, X86_OP_IMM, i);
-			add_str(&result, " ; imms[%u]: 0x%" PRIx64 "", i, x86->operands[index].imm);
-		}
-	}
-
-	if (x86->op_count)
-		add_str(&result, " ; op_count: %u", x86->op_count);
-
-	for (i = 0; i < x86->op_count; i++) {
-		cs_x86_op *op = &(x86->operands[i]);
-
-		switch((int)op->type) {
-			case X86_OP_REG:
-				add_str(&result, " ; operands[%u].type: REG = %s", i, cs_reg_name(*ud, op->reg));
-				break;
-			case X86_OP_IMM:
-				add_str(&result, " ; operands[%u].type: IMM = 0x%" PRIx64 "", i, op->imm);
-				break;
-			case X86_OP_MEM:
-				add_str(&result, " ; operands[%u].type: MEM", i);
-				if (op->mem.segment != X86_REG_INVALID)
-					add_str(&result, " ; operands[%u].mem.segment: REG = %s", i, cs_reg_name(*ud, op->mem.segment));
-				if (op->mem.base != X86_REG_INVALID)
-					add_str(&result, " ; operands[%u].mem.base: REG = %s", i, cs_reg_name(*ud, op->mem.base));
-				if (op->mem.index != X86_REG_INVALID)
-					add_str(&result, " ; operands[%u].mem.index: REG = %s", i, cs_reg_name(*ud, op->mem.index));
-				if (op->mem.scale != 1)
-					add_str(&result, " ; operands[%u].mem.scale: %u", i, op->mem.scale);
-				if (op->mem.disp != 0)
-					add_str(&result, " ; operands[%u].mem.disp: 0x%" PRIx64 "", i, op->mem.disp);
-				break;
-			default:
-				break;
-		}
-
-		if (op->avx_bcast != X86_AVX_BCAST_INVALID)
-			add_str(&result, " ; operands[%u].avx_bcast: %u", i, op->avx_bcast);
-
-		if (op->avx_zero_opmask != false)
-			add_str(&result, " ; operands[%u].avx_zero_opmask: TRUE", i);
-
-		add_str(&result, " ; operands[%u].size: %u", i, op->size);
-
-		switch(op->access) {
-			default:
-				break;
-			case CS_AC_READ:
-				add_str(&result, " ; operands[%u].access: READ", i);
-				break;
-			case CS_AC_WRITE:
-				add_str(&result, " ; operands[%u].access: WRITE", i);
-				break;
-			case CS_AC_READ | CS_AC_WRITE:
-				add_str(&result, " ; operands[%u].access: READ | WRITE", i);
-				break;
-		}
-	}
-
-	if (!cs_regs_access(*ud, ins, regs_read, &regs_read_count, regs_write, &regs_write_count)) {
-		if (regs_read_count) {
-			add_str(&result, " ; Registers read:");
-			for(i = 0; i < regs_read_count; i++) {
-				add_str(&result, " %s", cs_reg_name(*ud, regs_read[i]));
-			}
-		}
-
-		if (regs_write_count) {
-			add_str(&result, " ; Registers modified:");
-			for(i = 0; i < regs_write_count; i++) {
-				add_str(&result, " %s", cs_reg_name(*ud, regs_write[i]));
-			}
-		}
-	}
-
-	if (x86->eflags || x86->fpu_flags) {
-		for(i = 0; i < ins->detail->groups_count; i++) {
-			if (ins->detail->groups[i] == X86_GRP_FPU) {
-				add_str(&result, " ; FPU_FLAGS:");
-				for(i = 0; i <= 63; i++)
-					if (x86->fpu_flags & ((uint64_t)1 << i)) {
-						add_str(&result, " %s", get_fpu_flag_name((uint64_t)1 << i));
-					}
-				break;
-			}
-		}
-
-		if (i == ins->detail->groups_count) {
-			add_str(&result, " ; EFLAGS:");
-			for(i = 0; i <= 63; i++)
-				if (x86->eflags & ((uint64_t)1 << i)) {
-					add_str(&result, " %s", get_eflag_name((uint64_t)1 << i));
-				}
-		}
-	}
-
-	return result;
-}
-
diff --git a/suite/cstest/src/xcore_detail.c b/suite/cstest/src/xcore_detail.c
deleted file mode 100644
index d4f51f818..000000000
--- a/suite/cstest/src/xcore_detail.c
+++ /dev/null
@@ -1,52 +0,0 @@
-/* Capstone testing regression */
-/* By Do Minh Tuan <tuanit96@gmail.com>, 02-2019 */
-
-
-#include "factory.h"
-
-char *get_detail_xcore(csh *handle, cs_mode mode, cs_insn *ins)
-{
-	cs_xcore *xcore;
-	int i;
-	char *result;
-
-	result = (char *)malloc(sizeof(char));
-	result[0] = '\0';
-
-	if (ins->detail == NULL)
-		return result;
-
-	xcore = &(ins->detail->xcore);
-	if (xcore->op_count)
-		add_str(&result, " ; op_count: %u", xcore->op_count);
-
-	for (i = 0; i < xcore->op_count; i++) {
-		cs_xcore_op *op = &(xcore->operands[i]);
-		switch((int)op->type) {
-			default:
-				break;
-			case XCORE_OP_REG:
-				add_str(&result, " ; operands[%u].type: REG = %s", i, cs_reg_name(*handle, op->reg));
-				break;
-			case XCORE_OP_IMM:
-				add_str(&result, " ; operands[%u].type: IMM = 0x%x", i, op->imm);
-				break;
-			case XCORE_OP_MEM:
-				add_str(&result, " ; operands[%u].type: MEM", i);
-				if (op->mem.base != XCORE_REG_INVALID)
-					add_str(&result, " ; operands[%u].mem.base: REG = %s", i, cs_reg_name(*handle, op->mem.base));
-				if (op->mem.index != XCORE_REG_INVALID)
-					add_str(&result, " ; operands[%u].mem.index: REG = %s", i, cs_reg_name(*handle, op->mem.index));
-				if (op->mem.disp != 0)
-					add_str(&result, " ; operands[%u].mem.disp: 0x%x", i, op->mem.disp);
-				if (op->mem.direct != 1)
-					add_str(&result, " ; operands[%u].mem.direct: -1", i);
-
-
-				break;
-		}
-	}
-
-	return result;
-}
-
diff --git a/suite/cstest/test/CMakeLists.txt b/suite/cstest/test/CMakeLists.txt
new file mode 100644
index 000000000..b1c56cf59
--- /dev/null
+++ b/suite/cstest/test/CMakeLists.txt
@@ -0,0 +1,23 @@
+cmake_minimum_required(VERSION 3.15)
+
+set(CSTEST_TEST_SRC_DIR ${CSTEST_TEST_DIR}/src)
+set(CSTEST_TEST_INC_DIR ${CSTEST_TEST_DIR}/include)
+
+include_directories(${CSTEST_TEST_INC_DIR}
+  ${CSTEST_INCLUDE_DIR}
+  ${PROJECT_SOURCE_DIR}
+  ${PROJECT_SOURCE_DIR}/include)
+
+file(GLOB CSTEST_TEST_SRC ${CSTEST_TEST_SRC_DIR}/*.c)
+add_executable(unit_test ${CSTEST_TEST_SRC})
+add_dependencies(unit_test libcstest)
+target_link_libraries(unit_test PUBLIC libcstest)
+
+add_test(NAME UnitCSTest
+  COMMAND unit_test
+  WORKING_DIRECTORY ${CSTEST_TEST_DIR}
+)
+add_test(NAME IntegrationCSTest
+  COMMAND python3 ${CSTEST_TEST_DIR}/integration_tests.py cstest
+  WORKING_DIRECTORY ${CSTEST_TEST_DIR}
+)
diff --git a/suite/cstest/test/README.md b/suite/cstest/test/README.md
new file mode 100644
index 000000000..eb169ab5c
--- /dev/null
+++ b/suite/cstest/test/README.md
@@ -0,0 +1 @@
+Integration tests of cstest
diff --git a/suite/auto-sync/src/autosync/Tests/MCUpdaterTests/test_c.txt b/suite/cstest/test/empty_test_file.yaml
similarity index 100%
rename from suite/auto-sync/src/autosync/Tests/MCUpdaterTests/test_c.txt
rename to suite/cstest/test/empty_test_file.yaml
diff --git a/suite/cstest/test/integration_tests.py b/suite/cstest/test/integration_tests.py
new file mode 100755
index 000000000..6ca6d5711
--- /dev/null
+++ b/suite/cstest/test/integration_tests.py
@@ -0,0 +1,134 @@
+#!/usr/bin/env python3
+
+# Copyright © 2024 Rot127 <unisono@quyllur.org>
+# SPDX-License-Identifier: BSD-3
+
+# Typing for Python3.8
+from __future__ import annotations
+
+import sys
+import subprocess as sp
+
+from pathlib import Path
+
+
+def check(cmd: list[str], expected_stdout: str, expected_stderr: str, fail_msg: str):
+    print(f"Run: {' '.join(cmd)}")
+    result = sp.run(cmd, capture_output=True)
+    stderr = result.stderr.decode("utf8")
+    stdout = result.stdout.decode("utf8")
+    if expected_stderr and expected_stderr not in stderr:
+        print(f"STDERR mismatch: '{expected_stderr}' not in stderr")
+        print("\n###################### STDERR ######################\n")
+        print(stderr)
+        print("####################################################\n")
+        print(fail_msg)
+        exit(1)
+    if expected_stdout and expected_stdout not in stdout:
+        print(f"STDOUT mismatch: '{expected_stdout}' not in stdout")
+        print("\n###################### STDOUT ######################\n")
+        print(stdout)
+        print("####################################################\n")
+        print(fail_msg)
+        exit(1)
+
+
+def run_tests(cmd: str):
+    p = (
+        sp.run(["git", "rev-parse", "--show-toplevel"], check=True, capture_output=True)
+        .stdout.decode("utf8")
+        .strip()
+    )
+    path = Path(p).joinpath("suite").joinpath("cstest").joinpath("test")
+
+    cmd = cmd.split(" ")
+    check(
+        cmd + [f"{path.joinpath('empty_test_file.yaml')}"],
+        expected_stderr="Failed to parse test file ",
+        expected_stdout="",
+        fail_msg="Failed the empty file test",
+    )
+
+    check(
+        cmd + [f"{path.joinpath('missing_madatory_field.yaml')}"],
+        expected_stderr="Error: 'Missing required mapping field'",
+        expected_stdout="",
+        fail_msg="Failed the mandatory field test",
+    )
+
+    check(
+        cmd + [f"{path.joinpath('invalid_test_file.yaml')}"],
+        expected_stderr="Error: 'libyaml parser error'",
+        expected_stdout="",
+        fail_msg="Failed the invalid test file test",
+    )
+
+    check(
+        cmd + [f"{path.joinpath('min_valid_test_file.yaml')}"],
+        expected_stdout="All tests succeeded.",
+        expected_stderr="",
+        fail_msg="Failed the minimal valid parsing test",
+    )
+
+    check(
+        cmd + [f"{path.joinpath('invalid_cs_input.yaml')}"],
+        expected_stderr="'ar' is not mapped to a capstone architecture.",
+        expected_stdout="",
+        fail_msg="Test: Invalid CS option failed",
+    )
+
+    check(
+        cmd + [f"{path.joinpath('invalid_cs_input.yaml')}"],
+        expected_stderr="0 != 0x1",
+        expected_stdout="",
+        fail_msg="Test: Wrong number of instruction disassembled failed",
+    )
+
+    check(
+        cmd + [f"{path.joinpath('invalid_cs_input.yaml')}"],
+        expected_stderr="Option: 'thum' not used",
+        expected_stdout="",
+        fail_msg="Test: Invalid disassembly due to wrong option failed",
+    )
+
+    check(
+        cmd + [f"{path}"],
+        expected_stdout="Test files found: 6",
+        expected_stderr="",
+        fail_msg="Test: Detecting file in directory failed.",
+    )
+
+    if "cstest_py" in cmd:
+        check(
+            cmd
+            + [
+                f"{path}",
+                "-e",
+                "invalid_cs_input.yaml",
+                "-i",
+                "invalid_cs_input.yaml",
+                "min_valid_test_file.yaml",
+                "-v",
+                "debug",
+            ],
+            expected_stdout="Test files found: 2",
+            expected_stderr="",
+            fail_msg="Test: Detecting file in directory failed.",
+        )
+
+
+def print_usage_exit():
+    print(f'{sys.argv[0]} "cstest_command"')
+    print('"cstest_command" examples:')
+    print('\t"python3 ../../bindings/python/cstest.py"')
+    print("\tcstest")
+    exit(1)
+
+
+if __name__ == "__main__":
+    if len(sys.argv) != 2:
+        print_usage_exit()
+
+    run_tests(sys.argv[1])
+    print("All tests passed")
+    exit(0)
diff --git a/suite/cstest/test/invalid_cs_input.yaml b/suite/cstest/test/invalid_cs_input.yaml
new file mode 100644
index 000000000..62f760d29
--- /dev/null
+++ b/suite/cstest/test/invalid_cs_input.yaml
@@ -0,0 +1,29 @@
+test_cases:
+ -
+  input:
+    bytes: [ 0x05, 0xb0, 0xa0, 0xe1 ]
+    arch: "ar" # Wrong arch
+    options: ["arm"]
+  expected:
+    insns:
+      -
+        asm_text: "mov r11, r5"
+ -
+  input:
+    bytes: [ 0x06 ] # Wrong number of bytes.
+    arch: "aarch64"
+    options: []
+  expected:
+    insns:
+      -
+        asm_text: "mov r1, r6"
+ -
+  input:
+    bytes: [ 0xc2, 0xf3, 0x00, 0x8f ]
+    arch: "arm"
+    options: ["thum"] # Wrong mode
+  expected:
+    insns:
+      -
+          asm_text: "bxj r2"
+
diff --git a/suite/cstest/test/invalid_test_file.yaml b/suite/cstest/test/invalid_test_file.yaml
new file mode 100644
index 000000000..075cd4078
--- /dev/null
+++ b/suite/cstest/test/invalid_test_file.yaml
@@ -0,0 +1,11 @@
+test_cases:
+ -
+  input:
+    bytes: [ 0x05, 0xb0, 0xa0, 0xe1 ]
+    arch: "arm"
+    options: ["arm"]
+  expected:
+    insns:
+      -
+        op_str: "mov r11, r5"
+	# Invisble tab
diff --git a/suite/cstest/test/min_valid_test_file.yaml b/suite/cstest/test/min_valid_test_file.yaml
new file mode 100644
index 000000000..c67c1f6c7
--- /dev/null
+++ b/suite/cstest/test/min_valid_test_file.yaml
@@ -0,0 +1,31 @@
+test_cases:
+ -
+  input:
+    bytes: [ 0x05, 0xb0, 0xa0, 0xe1 ]
+    arch: "arm"
+    options: ["arm"]
+  expected:
+    insns:
+      -
+        asm_text: "mov r11, r5"
+ -
+  input:
+    bytes: [ 0x06, 0x10, 0xa0, 0xe1 ]
+    arch: "arm"
+    options: ["arm"]
+  expected:
+    insns:
+      -
+        asm_text: "mov r1, r6"
+ -
+  input:
+    bytes: [ 0x06, 0x10, 0xa0, 0xe1, 0x05, 0xb0, 0xa0, 0xe1 ]
+    arch: "arm"
+    options: ["arm"]
+  expected:
+    insns:
+      -
+        asm_text: "mov r1, r6"
+      -
+        asm_text: "mov r11, r5"
+
diff --git a/suite/cstest/test/missing_madatory_field.yaml b/suite/cstest/test/missing_madatory_field.yaml
new file mode 100644
index 000000000..5778dbf25
--- /dev/null
+++ b/suite/cstest/test/missing_madatory_field.yaml
@@ -0,0 +1,8 @@
+test_cases:
+ -
+  input:
+    arch: "arm"
+  expected:
+    insns:
+      -
+        op_str: "mov r11, r5"
diff --git a/suite/cstest/test/some_dir/some_other_dir/min_valid_test_file.yaml b/suite/cstest/test/some_dir/some_other_dir/min_valid_test_file.yaml
new file mode 100644
index 000000000..c67c1f6c7
--- /dev/null
+++ b/suite/cstest/test/some_dir/some_other_dir/min_valid_test_file.yaml
@@ -0,0 +1,31 @@
+test_cases:
+ -
+  input:
+    bytes: [ 0x05, 0xb0, 0xa0, 0xe1 ]
+    arch: "arm"
+    options: ["arm"]
+  expected:
+    insns:
+      -
+        asm_text: "mov r11, r5"
+ -
+  input:
+    bytes: [ 0x06, 0x10, 0xa0, 0xe1 ]
+    arch: "arm"
+    options: ["arm"]
+  expected:
+    insns:
+      -
+        asm_text: "mov r1, r6"
+ -
+  input:
+    bytes: [ 0x06, 0x10, 0xa0, 0xe1, 0x05, 0xb0, 0xa0, 0xe1 ]
+    arch: "arm"
+    options: ["arm"]
+  expected:
+    insns:
+      -
+        asm_text: "mov r1, r6"
+      -
+        asm_text: "mov r11, r5"
+
diff --git a/suite/cstest/test/src/unit_tests.c b/suite/cstest/test/src/unit_tests.c
new file mode 100644
index 000000000..fcc34e4be
--- /dev/null
+++ b/suite/cstest/test/src/unit_tests.c
@@ -0,0 +1,74 @@
+// Copyright © 2024 Rot127 <unisono@quyllur.org>
+// SPDX-License-Identifier: BSD-3
+
+#include "../../../utils.h"
+#include "../../../Mapping.h"
+#include "test_mapping.h"
+#include <stdint.h>
+
+bool test_cs_enum_get_val()
+{
+	bool found = false;
+	// Get first value
+	uint32_t val = enum_map_bin_search(cs_enum_map, ARR_SIZE(cs_enum_map),
+					   "AAAAAAAAAAAAAAAAAAAAAAAAAA",
+					   &found);
+	if (!found || val != 0xffffff) {
+		fprintf(stderr,
+			"enum_map_bin_search(cs_enum_map, ARR_SIZE(cs_enum_map), AAAAAAAAAAAAAAAAAAAAAAAAAA) failed is %d.\n",
+			val);
+		return false;
+	}
+
+	// Get last value
+	val = enum_map_bin_search(cs_enum_map, ARR_SIZE(cs_enum_map),
+				  "zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz", &found);
+	if (!found || val != 0xffffff) {
+		fprintf(stderr,
+			"enum_map_bin_search(cs_enum_map, ARR_SIZE(cs_enum_map), zzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzzz) failed is %d.\n",
+			val);
+		return false;
+	}
+
+	// Some values
+	val = enum_map_bin_search(cs_enum_map, ARR_SIZE(cs_enum_map),
+				  "AArch64CC_EQ", &found);
+	if (!found || val != AArch64CC_EQ) {
+		fprintf(stderr,
+			"enum_map_bin_search(cs_enum_map, ARR_SIZE(cs_enum_map), AArch64CC_EQ) failed is %d.\n",
+			val);
+		return false;
+	}
+	val = enum_map_bin_search(cs_enum_map, ARR_SIZE(cs_enum_map),
+				  "AArch64CC_Invalid", &found);
+	if (!found || val != AArch64CC_Invalid) {
+		fprintf(stderr,
+			"enum_map_bin_search(cs_enum_map, ARR_SIZE(cs_enum_map), AArch64CC_In) failed is %d.\n",
+			val);
+		return false;
+	}
+
+	enum_map_bin_search(cs_enum_map, ARR_SIZE(cs_enum_map), "\0", &found);
+	if (found) {
+		fprintf(stderr, "Out of bounds failed.\n");
+		return false;
+	}
+
+	enum_map_bin_search(cs_enum_map, ARR_SIZE(cs_enum_map),
+			    "~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~",
+			    &found);
+	if (found) {
+		fprintf(stderr, "Out of bounds failed.\n");
+		return false;
+	}
+
+	return true;
+}
+
+int main()
+{
+	bool success = true;
+	success &= test_cs_enum_get_val();
+	printf("test_cs_enum_get_val: %s\n", success ? "ok" : "fail");
+	return success ? 0 : 1;
+}
diff --git a/suite/disasm_mc.py b/suite/disasm_mc.py
deleted file mode 100755
index d0ad2caf5..000000000
--- a/suite/disasm_mc.py
+++ /dev/null
@@ -1,193 +0,0 @@
-#!/usr/bin/python
-# Test tool to disassemble MC files. By Nguyen Anh Quynh, 2017
-import array, os.path, sys
-from capstone import *
-
-
-# convert all hex numbers to decimal numbers in a text
-def normalize_hex(a):
-    while(True):
-        i = a.find('0x')
-        if i == -1: # no more hex number
-            break
-        hexnum = '0x'
-        for c in a[i + 2:]:
-            if c in '0123456789abcdefABCDEF':
-                hexnum += c
-            else:
-                break
-        num = int(hexnum, 16)
-        a = a.replace(hexnum, str(num))
-    return a
-
-
-def test_file(fname):
-    print("Test %s" %fname);
-    f = open(fname)
-    lines = f.readlines()
-    f.close()
-
-    if not lines[0].startswith('# '):
-        print("ERROR: decoding information is missing")
-        return
-
-    # skip '# ' at the front, then split line to get out hexcode
-    # Note: option can be '', or 'None'
-    #print lines[0]
-    #print lines[0][2:].split(', ')
-    (arch, mode, option) = lines[0][2:].split(', ')
-    mode = mode.replace(' ', '')
-    option = option.strip()
-
-    archs = {
-        "CS_ARCH_ARM": CS_ARCH_ARM,
-        "CS_ARCH_AARCH64": CS_ARCH_AARCH64,
-        "CS_ARCH_MIPS": CS_ARCH_MIPS,
-        "CS_ARCH_PPC": CS_ARCH_PPC,
-        "CS_ARCH_SPARC": CS_ARCH_SPARC,
-        "CS_ARCH_SYSZ": CS_ARCH_SYSZ,
-        "CS_ARCH_X86": CS_ARCH_X86,
-        "CS_ARCH_XCORE": CS_ARCH_XCORE,
-        "CS_ARCH_M68K": CS_ARCH_M68K,
-        "CS_ARCH_RISCV": CS_ARCH_RISCV,
-    }
-    
-    modes = {
-        "CS_MODE_16": CS_MODE_16,
-        "CS_MODE_32": CS_MODE_32,
-        "CS_MODE_64": CS_MODE_64,
-        "CS_MODE_MIPS32": CS_MODE_MIPS32,
-        "CS_MODE_MIPS64": CS_MODE_MIPS64,
-        "0": CS_MODE_ARM,
-        "CS_MODE_ARM": CS_MODE_ARM,
-        "CS_MODE_THUMB": CS_MODE_THUMB,
-        "CS_MODE_ARM+CS_MODE_V8": CS_MODE_ARM+CS_MODE_V8,
-        "CS_MODE_THUMB+CS_MODE_V8": CS_MODE_THUMB+CS_MODE_V8,
-        "CS_MODE_THUMB+CS_MODE_MCLASS": CS_MODE_THUMB+CS_MODE_MCLASS,
-        "CS_MODE_LITTLE_ENDIAN": CS_MODE_LITTLE_ENDIAN,
-        "CS_MODE_BIG_ENDIAN": CS_MODE_BIG_ENDIAN,
-        "CS_MODE_64+CS_MODE_LITTLE_ENDIAN": CS_MODE_64+CS_MODE_LITTLE_ENDIAN,
-        "CS_MODE_64+CS_MODE_BIG_ENDIAN": CS_MODE_64+CS_MODE_BIG_ENDIAN,
-        "CS_MODE_MIPS32+CS_MODE_MICRO": CS_MODE_MIPS32+CS_MODE_MICRO,
-        "CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN": CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN,
-        "CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN+CS_MODE_MICRO": CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN,
-        "CS_MODE_BIG_ENDIAN+CS_MODE_V9": CS_MODE_BIG_ENDIAN + CS_MODE_V9,
-        "CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN": CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN,
-        "CS_MODE_MIPS32+CS_MODE_LITTLE_ENDIAN": CS_MODE_MIPS32+CS_MODE_LITTLE_ENDIAN,
-        "CS_MODE_MIPS64+CS_MODE_LITTLE_ENDIAN": CS_MODE_MIPS64+CS_MODE_LITTLE_ENDIAN,
-        "CS_MODE_MIPS64+CS_MODE_BIG_ENDIAN": CS_MODE_MIPS64+CS_MODE_BIG_ENDIAN,
-        "CS_MODE_RISCV32": CS_MODE_RISCV32,
-        "CS_MODE_RISCV64": CS_MODE_RISCV64,
-    }
-    
-    options = {
-        "CS_OPT_SYNTAX_ATT": CS_OPT_SYNTAX_ATT,
-        "CS_OPT_SYNTAX_NOREGNAME": CS_OPT_SYNTAX_NOREGNAME,
-    }
-
-    mc_modes = {
-        ("CS_ARCH_X86", "CS_MODE_32"): ['-triple=i386'],
-        ("CS_ARCH_X86", "CS_MODE_64"): ['-triple=x86_64'],
-        ("CS_ARCH_ARM", "CS_MODE_ARM"): ['-triple=armv7'],
-        ("CS_ARCH_ARM", "CS_MODE_THUMB"): ['-triple=thumbv7'],
-        ("CS_ARCH_ARM", "CS_MODE_ARM+CS_MODE_V8"): ['-triple=armv8'],
-        ("CS_ARCH_ARM", "CS_MODE_THUMB+CS_MODE_V8"): ['-triple=thumbv8'],
-        ("CS_ARCH_ARM", "CS_MODE_THUMB+CS_MODE_MCLASS"): ['-triple=thumbv7m'],
-        ("CS_ARCH_AARCH64", "0"): ['-triple=aarch64'],
-        ("CS_ARCH_MIPS", "CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN"): ['-triple=mips'],
-        ("CS_ARCH_MIPS", "CS_MODE_MIPS32+CS_MODE_MICRO"): ['-triple=mipsel', '-mattr=+micromips'],
-        ("CS_ARCH_MIPS", "CS_MODE_MIPS64"): ['-triple=mips64el'],
-        ("CS_ARCH_MIPS", "CS_MODE_MIPS32"): ['-triple=mipsel'],
-        ("CS_ARCH_MIPS", "CS_MODE_MIPS64+CS_MODE_BIG_ENDIAN"): ['-triple=mips64'],
-        ("CS_ARCH_MIPS", "CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN"): ['-triple=mips', '-mattr=+micromips'],
-        ("CS_ARCH_MIPS", "CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN+CS_MODE_MICRO"): ['-triple=mips', '-mattr=+micromips'],
-        ("CS_ARCH_PPC", "CS_MODE_BIG_ENDIAN"): ['-triple=powerpc64'],
-        ('CS_ARCH_SPARC', 'CS_MODE_BIG_ENDIAN'): ['-triple=sparc'],
-        ('CS_ARCH_SPARC', 'CS_MODE_BIG_ENDIAN+CS_MODE_V9'): ['-triple=sparcv9'],
-        ('CS_ARCH_SYSZ', '0'): ['-triple=s390x', '-mcpu=z196'],
-        ('CS_ARCH_RISCV', 'CS_MODE_RISCV32'): ['-triple=riscv32'],
-        ('CS_ARCH_RISCV', 'CS_MODE_RISCV64'): ['-triple=riscv64'],
-    }
-
-    #if not option in ('', 'None'):
-    #    print archs[arch], modes[mode], options[option]
-    
-    #print(arch, mode, option)
-    md = Cs(archs[arch], modes[mode])
-
-    if arch == 'CS_ARCH_ARM' or arch == 'CS_ARCH_PPC' :
-        md.syntax = CS_OPT_SYNTAX_NOREGNAME
-
-    if fname.endswith('3DNow.s.cs'):
-        md.syntax = CS_OPT_SYNTAX_ATT
-
-    for line in lines[1:]:
-        # ignore all the input lines having # in front.
-        if line.startswith('#'):
-            continue
-        #print("Check %s" %line)
-        code = line.split(' = ')[0]
-        asm  = ''.join(line.split(' = ')[1:])
-        hex_code = code.replace('0x', '')
-        hex_code = hex_code.replace(',', '')
-        hex_data = hex_code.decode('hex')
-        #hex_bytes = array.array('B', hex_data)
-
-        x = list(md.disasm(hex_data, 0))
-        if len(x) > 0:
-            if x[0].op_str != '':
-                cs_output = "%s %s" %(x[0].mnemonic, x[0].op_str)
-            else:
-                cs_output = x[0].mnemonic
-        else:
-            cs_output = 'FAILED to disassemble'
-
-        cs_output2 = normalize_hex(cs_output)
-        cs_output2 = cs_output2.replace(' ', '')
-
-        if arch == 'CS_ARCH_MIPS':
-            # normalize register alias names
-            cs_output2 = cs_output2.replace('$at', '$1')
-            cs_output2 = cs_output2.replace('$v0', '$2')
-            cs_output2 = cs_output2.replace('$v1', '$3')
-
-            cs_output2 = cs_output2.replace('$a0', '$4')
-            cs_output2 = cs_output2.replace('$a1', '$5')
-            cs_output2 = cs_output2.replace('$a2', '$6')
-            cs_output2 = cs_output2.replace('$a3', '$7')
-
-            cs_output2 = cs_output2.replace('$t0', '$8')
-            cs_output2 = cs_output2.replace('$t1', '$9')
-            cs_output2 = cs_output2.replace('$t2', '$10')
-            cs_output2 = cs_output2.replace('$t3', '$11')
-            cs_output2 = cs_output2.replace('$t4', '$12')
-            cs_output2 = cs_output2.replace('$t5', '$13')
-            cs_output2 = cs_output2.replace('$t6', '$14')
-            cs_output2 = cs_output2.replace('$t7', '$15')
-            cs_output2 = cs_output2.replace('$t8', '$24')
-            cs_output2 = cs_output2.replace('$t9', '$25')
-
-            cs_output2 = cs_output2.replace('$s0', '$16')
-            cs_output2 = cs_output2.replace('$s1', '$17')
-            cs_output2 = cs_output2.replace('$s2', '$18')
-            cs_output2 = cs_output2.replace('$s3', '$19')
-            cs_output2 = cs_output2.replace('$s4', '$20')
-            cs_output2 = cs_output2.replace('$s5', '$21')
-            cs_output2 = cs_output2.replace('$s6', '$22')
-            cs_output2 = cs_output2.replace('$s7', '$23')
-
-            cs_output2 = cs_output2.replace('$k0', '$26')
-            cs_output2 = cs_output2.replace('$k1', '$27')
-
-        print("\t%s = %s" %(hex_code, cs_output))
-
-
-if __name__ == '__main__':
-    if len(sys.argv) == 1:
-        fnames = sys.stdin.readlines()
-        for fname in fnames:
-            test_file(fname.strip())
-    else:
-        #print("Usage: ./test_mc.py <input-file.s.cs>")
-        test_file(sys.argv[1])
-
diff --git a/suite/disasm_mc.sh b/suite/disasm_mc.sh
deleted file mode 100755
index 6b8936cd2..000000000
--- a/suite/disasm_mc.sh
+++ /dev/null
@@ -1,11 +0,0 @@
-#!/bin/sh
-
-# This script test all architectures by default.
-
-find MC/ -name *.cs | ./disasm_mc.py
-
-# To test just one architecture, specify the corresponding dir:
-# $ find MC/X86 -name *.cs | ./disasm_mc.py
-
-# To test just one input file, run disasm_mc.py with that file:
-# $ ./disasm_mc.py MC/X86/x86-32-fma3.s.cs
diff --git a/suite/fuzz/Makefile b/suite/fuzz/Makefile
index 99f910632..4c8468149 100644
--- a/suite/fuzz/Makefile
+++ b/suite/fuzz/Makefile
@@ -81,7 +81,7 @@ else
 	$(link-static)
 endif
 
-$(FUZZERBIN): FUZZLDFLAGS="-fsanitize=fuzzer"
+$(FUZZERBIN): FUZZLDFLAGS="-fsanitize=fuzzer -fno-sanitize-coverage=stack-depth"
 
 $(FUZZERBIN): fuzz_disasm.o platform.o
 	@mkdir -p $(@D)
diff --git a/suite/gencstest.py b/suite/gencstest.py
deleted file mode 100755
index 50618ded7..000000000
--- a/suite/gencstest.py
+++ /dev/null
@@ -1,145 +0,0 @@
-#!/usr/bin/env python3
-
-import sys
-import re
-import argparse
-from pathlib import Path
-
-# 80001c1a <IfxVadc_disableAccess>:
-# 80001c1a:	40 4f       	mov.aa %a15,%a4
-# 80001c1c:	02 48       	mov %d8,%d4
-# 80001c1e:	6d ff 9d ff 	call 80001b58 <IfxScuWdt_getSafetyWatchdogPassword>
-
-unique_set = set()
-
-
-def num2prefix_hex(x, prefix="#"):
-    if x.startswith("0x") or x.startswith("-0x") or x == "0":
-        x = prefix + x
-    if x.isdigit() or (x.startswith("-") and x[1:].isdigit()):
-        x = prefix + hex(int(x))
-    return x
-
-def op2prefix_hex(x):
-    x = num2prefix_hex(x)
-    if "]" in x:
-        xs = x.split("]")
-        if xs[1].isdigit() or xs[1].startswith('-'):
-            x = xs[0] + "]" + num2prefix_hex(xs[1])
-    return x
-
-def gen(filename):
-    with open(filename, "r") as f:
-        for line in f:
-            caps = re.findall(
-                r"([0-9a-f]+):\s+([0-9a-f]+) ([0-9a-f]+) ([0-9a-f]+)? ([0-9a-f]+)?\s+"
-                r"(\S+) (\S+)",
-                line,
-            )
-            if not caps:
-                continue
-            caps = caps[0]
-            addr = int(caps[0], 16)
-            hexstr = caps[1:5]
-            mnemonic: str = caps[5]
-            operands = caps[6]
-
-            def try_dedisp(x):
-                try:
-                    disp = int(x, 16)
-                    if disp > 0x80000000:
-                        x = hex(disp - addr)
-                    return x
-                except ValueError:
-                    pass
-                return x
-
-            def is_hex_string(s: str) -> bool:
-                if not s.isalnum():
-                    return False
-                return all(c.isdigit() or c.lower() in "abcdef" for c in s) and any(
-                    c.lower() in "abcdef" for c in s
-                )
-
-            hexstr = ",".join(f"0x{x}" for x in hexstr if x)
-            fun = re.match(r"\s*<.+>\s*", operands)
-            # print(hex(addr), hexstr, mnemonic, operands)
-            if any(
-                [
-                    mnemonic.startswith(pre)
-                    for pre in [
-                        "mtcr",
-                        "mfcr",
-                        "st.a",
-                        "st.b",
-                        "st.d",
-                        "st.w",
-                        "ld.a",
-                        "ld.b",
-                        "ld.d",
-                        "ld.w",
-                    ]
-                ]
-            ):
-                # unique_set.add(f"# {hexstr.ljust(19)} = {mnemonic}\t{operands}")
-                continue
-
-            ops = operands.split(",")
-            if (
-                any(
-                    [mnemonic.startswith(pre) for pre in ["j", "call", "loop", "fcall"]]
-                )
-                or fun
-            ):
-                re.sub(r"\s*<.+>\s*", "", operands)
-                # de relative addressing
-                ops = list(map(try_dedisp, ops))
-
-            for i, x in enumerate(ops):
-                if is_hex_string(x) and not x.startswith("0x"):
-                    x = "#0x" + x
-                x = op2prefix_hex(x)
-                ops[i] = x
-
-            operands = ", ".join(ops)
-            operands = operands.replace("%", "")
-            unique_set.add(f"{hexstr.ljust(19)} = {mnemonic}\t{operands}")
-
-    print("# CS_ARCH_TRICORE, CS_MODE_TRICORE_162, None")
-    print("\n".join(unique_set))
-
-def att2intel(filename):
-    with open(filename, "r") as fp:
-        lines = []
-        for line in fp.readlines():
-            if not '=' in line:
-                lines.append(line)
-                continue
-            insn = line.split('=')
-            hexstr = insn[0]
-            insn = insn[1]
-            ops = insn.strip().split(', ')
-            ops = ops[0].split('\t') + ops[1:]
-            mnemonic = ops[0]
-            ops = ops[1:]
-            for i,op in enumerate(ops):
-                op = op.strip()
-                op = op2prefix_hex(op)
-                ops[i] = op
-            operands = ", ".join(ops)
-            lines.append(f"{hexstr.ljust(19)} = {mnemonic}\t{operands}")
-        print('\n'.join(lines))
-
-def main():
-    parser = argparse.ArgumentParser(description="Convert objdump's output to .s.cs test file")
-    parser.add_argument('input', type=Path, help='input file path')
-    parser.add_argument('--intel', action='store_true', help='convert .s.cs file to intel syntax')
-    args = parser.parse_args()
-    if not args.intel:
-        gen(args.input)
-    else:
-        att2intel(args.input)
-
-
-if __name__ == "__main__":
-    main()
diff --git a/suite/regress/LICENSE b/suite/regress/LICENSE
deleted file mode 100644
index dd85900f2..000000000
--- a/suite/regress/LICENSE
+++ /dev/null
@@ -1,30 +0,0 @@
-This is the software license for Unicorn regression tests. The regression tests
-are written by several Unicorn contributors (See CREDITS.TXT) and maintained by
-Hoang-Vu Dang <dang.hvu@gmail.com>
-
-Copyright (c) 2015, Unicorn contributors
-All rights reserved.
-
-Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions are met:
-
-* Redistributions of source code must retain the above copyright notice,
-  this list of conditions and the following disclaimer.
-* Redistributions in binary form must reproduce the above copyright notice,
-  this list of conditions and the following disclaimer in the documentation
-  and/or other materials provided with the distribution.
-* Neither the name of the developer(s) nor the names of its
-  contributors may be used to endorse or promote products derived from this
-  software without specific prior written permission.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-POSSIBILITY OF SUCH DAMAGE.
diff --git a/suite/regress/Makefile b/suite/regress/Makefile
deleted file mode 100644
index bbc73c74a..000000000
--- a/suite/regress/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
-LIBNAME = capstone
-
-invalid_read_in_print_operand: invalid_read_in_print_operand.o
-	${CC} $< -O3 -Wall -l$(LIBNAME) -o $@
-
-%.o: %.c
-	${CC} -c -I../../include $< -o $@
-
-clean:
-	rm -rf *.o invalid_read_in_print_operand
diff --git a/suite/regress/invalid_read_in_print_operand.c b/suite/regress/invalid_read_in_print_operand.c
deleted file mode 100644
index 144ae9411..000000000
--- a/suite/regress/invalid_read_in_print_operand.c
+++ /dev/null
@@ -1,14 +0,0 @@
-#include <capstone.h>
-
-#define BINARY "\x3b\x30\x62\x93\x5d\x61\x03\xe8"
-
-int main(int argc, char **argv, char **envp) {
-  csh handle;
-  if (cs_open(CS_ARCH_X86, CS_MODE_64, &handle)) {
-    printf("cs_open(…) failed\n");
-    return 1;
-  }
-  cs_insn *insn;
-  cs_disasm(handle, (uint8_t *)BINARY, sizeof(BINARY) - 1, 0x1000, 0, &insn);
-  return 0;
-}
diff --git a/suite/regress/regress.py b/suite/regress/regress.py
deleted file mode 100755
index 2e4f2536b..000000000
--- a/suite/regress/regress.py
+++ /dev/null
@@ -1,34 +0,0 @@
-#!/usr/bin/python
-
-import unittest
-
-from os.path import dirname, basename, isfile
-import glob
-
-# Find all unittest type in this directory and run it.
-
-class RegressTest(unittest.TestCase):
-    pass
-
-def main():
-    unittest.main()
-
-if __name__ == '__main__':
-    directory = dirname(__file__)
-    if directory == '':
-        directory = '.'
-    modules = glob.glob(directory+"/*.py")
-    __all__ = [ basename(f)[:-3] for f in modules if isfile(f)]
-    suite = unittest.TestSuite()
-
-    for module in __all__:
-        m = __import__(module)
-        for cl in dir(m):
-            try:
-                realcl = getattr(m,cl)
-                if issubclass(realcl, unittest.TestCase):
-                    suite.addTest(realcl())
-            except Exception as e:
-                pass
-
-    unittest.TextTestRunner().run(suite)
diff --git a/suite/regress/test_arm64_bra.py b/suite/regress/test_arm64_bra.py
deleted file mode 100644
index e16764170..000000000
--- a/suite/regress/test_arm64_bra.py
+++ /dev/null
@@ -1,57 +0,0 @@
-import unittest
-from capstone import *
-from capstone.arm64 import *
-
-class ARM64BRAARegAccessTest(unittest.TestCase):
-
-    # These instructions should all have all their register operands being READ.
-    # https://developer.arm.com/documentation/ddi0596/2021-12/Base-Instructions/BRAA--BRAAZ--BRAB--BRABZ--Branch-to-Register--with-pointer-authentication-
-    PATTERNS = [
-        ("5F 08 1F D6", "braaz x2"),
-        ("11 0A 1F D7", "braa x16, x17"),
-        ("1F 0C 1F D6", "brabz x0"),
-        ("11 0E 1F D7", "brab x16, x17"),
-        ]
-
-    def setUp(self):
-        self.insts = []
-        self.cs = Cs(CS_ARCH_ARM64, CS_MODE_LITTLE_ENDIAN)
-        self.cs.detail = True
-
-        for pattern, asm in self.PATTERNS:
-            # Disassemble the instruction. Any error here means Capstone doesn't handle the instruction (maybe the wrong branch)
-            inst = next(self.cs.disasm(bytes.fromhex(pattern), 0))
-
-            expected_regs_read = list(map(lambda r: r.strip(', '), asm.split()[1:]))
-            expected_regs_written = [] # nothing written
-            expected_regs = [expected_regs_read, expected_regs_written]
-
-            self.insts.append((inst, asm, expected_regs))
-
-
-    def test_regs_access(self):
-        """Check that the `regs_access` API provides correct data"""
-        
-        for inst, asm, expected_regs in self.insts:
-
-            # Check that the instruction writes the first register operand and reads the second
-            for i, decoded_regs in enumerate(map(lambda l: list(map(self.cs.reg_name, l)), inst.regs_access())):
-                self.assertEqual(decoded_regs, expected_regs[i], "%s has %r %s registers instead of %r" % (asm, decoded_regs, ["read", "written"][i], expected_regs[i]))
-
-
-    def test_operands(self):
-        """Check that the `operands` API provides correct data"""
-        for inst, asm, expected_regs in self.insts:
-            ops = inst.operands
-
-            expected_regs_read, expected_regs_written = expected_regs
-            self.assertEqual(len(expected_regs_written), 0)
-            #print("Ensuring %s has the following read registers: %r" % (asm, expected_regs_read))
-            self.assertEqual(len(ops), len(expected_regs_read))
-            
-            for i, op in enumerate(ops):
-                self.assertEqual(op.type, CS_OP_REG, "%s has operand %d with invalid type" % (asm, i))
-                self.assertEqual(op.access, CS_AC_READ, "%s has operand %d with invalid access" % (asm, i))
-            
-if __name__ == '__main__':
-    unittest.main()
diff --git a/suite/regress/test_arm64_ldr_registers.py b/suite/regress/test_arm64_ldr_registers.py
deleted file mode 100644
index fded0ae89..000000000
--- a/suite/regress/test_arm64_ldr_registers.py
+++ /dev/null
@@ -1,63 +0,0 @@
-import unittest
-from capstone import *
-from capstone.arm64 import *
-
-_python3 = sys.version_info.major == 3
-
-
-class SubRegTest(unittest.TestCase):
-
-    PATTERNS = [
-        ("41 00 40 F9", "ldr x1, [x2]"),
-        ("41 00 40 39", "ldrb w1, [x2]"),
-        ("41 00 C0 39", "ldrsb w1, [x2]"),
-        ("41 00 40 79", "ldrh w1, [x2]"),
-        ("88 c2 bf f8", "ldapr x8, [x20]"),
-        ]
-
-    def setUp(self):
-        self.insts = []
-        self.cs = Cs(CS_ARCH_ARM64, CS_MODE_LITTLE_ENDIAN)
-        self.cs.detail = True
-
-        for pattern, asm in self.PATTERNS:
-            if _python3:
-                l = list(self.cs.disasm(bytes.fromhex(pattern), 0))
-            else:
-                l = list(self.cs.disasm(bytearray.fromhex(pattern), 0))
-            self.assertTrue(len(l) == 1)
-
-            _, expected_reg_written, expected_reg_read = asm.split()
-            # strip comma and []
-            expected_reg_written = expected_reg_written[:-1]
-            expected_reg_read = expected_reg_read[1:-1]
-            expected_regs = [expected_reg_read, expected_reg_written]
-
-            self.insts.append((l[0], asm, expected_regs))
-
-
-    def test_registers(self):
-        """Check that the `regs_access` API provides correct data"""
-        
-        for inst, asm, expected_regs in self.insts:
-
-            # Check that the instruction writes the first register operand and reads the second
-            for i, decoded_regs in enumerate(map(lambda l: list(map(self.cs.reg_name, l)), inst.regs_access())):
-                self.assertEqual(len(decoded_regs), 1, "%s has %d %s registers instead of 1" % (asm, len(decoded_regs), ["read", "written"][i]))
-                decoded_reg = decoded_regs[0]
-                self.assertEqual(expected_regs[i], decoded_reg, "%s test"%i)
-
-    def test_operands(self):
-        """Check that the `operands` API provides correct data"""
-        for inst, asm, expected_regs in self.insts:
-            ops = inst.operands
-            self.assertEqual(len(ops), 2)
-            
-            self.assertEqual(ops[0].type, CS_OP_REG, "%s has operand 0 with invalid type" % asm)
-            self.assertEqual(ops[0].access, CS_AC_WRITE, "%s has operand 0 with invalid access" % asm)
-            self.assertEqual(ops[1].type, CS_OP_MEM, "%s has operand 0 with invalid type" % asm)
-            self.assertEqual(self.cs.reg_name(ops[1].mem.base), expected_regs[0], "%s has operand 1 with invalid reg" % asm)
-            self.assertEqual(ops[1].access, CS_AC_READ, "%s has operand 1 with invalid access" % asm)
-
-if __name__ == '__main__':
-    unittest.main()
diff --git a/suite/regress/test_arm64_mov.py b/suite/regress/test_arm64_mov.py
deleted file mode 100755
index 4ef4a5f52..000000000
--- a/suite/regress/test_arm64_mov.py
+++ /dev/null
@@ -1,76 +0,0 @@
-import unittest
-from capstone import *
-from capstone.arm64 import *
-
-# By Stevie Lavern <stevie.lavern@gmail.com>, 2023.
-class ARM64MovRegAccessTest(unittest.TestCase):
-    # These instructions should all have their 1st operand register being WRITTEN and not READ.
-    PATTERNS_IMM = [
-        ("00 00 80 D2", "mov x0, #0"),
-        ("E2 66 82 52", "movz w2, #0x1337"),
-        ("A3 D5 9B 92", "movn x3, #0xdead"),
-        ("E4 DD 97 12", "movn w4, #0xbeef"),
-        ("03 40 A0 D2", "mov x3, #0x2000000") # aliased to MOVZXi.
-    ]
-
-    PATTERNS_REG = [
-        ("00 20 18 D5", "msr ttbr0_el1, x0"),
-        ("20 20 38 D5", "mrs x0, ttbr1_el1")
-    ]
-
-    def setUp(self):
-        self.insts = []
-        self.cs = Cs(CS_ARCH_ARM64, CS_MODE_LITTLE_ENDIAN)
-        self.cs.detail = True
-
-        for pattern, asm in self.PATTERNS_IMM:
-            l = list(self.cs.disasm(bytes.fromhex(pattern), 0))
-            self.assertTrue(len(l) == 1)
-
-            _, expected_reg_written, _ = asm.split()
-            # strip comma and [].
-            expected_reg_written = [expected_reg_written[:-1]]
-            expected_reg_read = [] # nothing should be read.
-            expected_regs = [expected_reg_read, expected_reg_written]
-
-            self.insts.append((l[0], asm, expected_regs, False))
-
-        for pattern, asm in self.PATTERNS_REG:
-            l = list(self.cs.disasm(bytes.fromhex(pattern), 0))
-            self.assertTrue(len(l) == 1)
-
-            _, expected_reg_written, expected_reg_read = asm.split()
-            # strip comma and [], only keep general purpose registers.
-            expected_reg_written = expected_reg_written[:-1]
-            expected_reg_written = [expected_reg_written] if expected_reg_written[0].lower() == 'x' else []
-            expected_reg_read = [expected_reg_read] if expected_reg_read[0].lower() == 'x' else []
-            expected_regs = [expected_reg_read, expected_reg_written]
-
-            self.insts.append((l[0], asm, expected_regs, True))
-
-    def test_regs_access(self):
-        """Check that the `regs_access` API provides correct data"""
-
-        for inst, asm, expected_regs, pattern_reg in self.insts:
-            # Check that the instruction writes the first register operand and reads the second.
-            for i, decoded_regs in enumerate(map(lambda l: list(map(self.cs.reg_name, l)), inst.regs_access())):
-                self.assertEqual(decoded_regs, expected_regs[i], "%s has %r %s registers instead of %r" % (asm, decoded_regs, ["read", "written"][i], expected_regs[i]))
-
-    def test_operands(self):
-        """Check that the `operands` API provides correct data"""
-        for inst, asm, expected_regs, pattern_reg in self.insts:
-            ops = inst.operands
-            self.assertEqual(len(ops), 2)
-
-            reg_types = [CS_OP_REG, ARM64_OP_SYS] if pattern_reg else [CS_OP_REG]
-
-            self.assertIn(ops[0].type, reg_types, "%s has operand 0 with invalid type" % asm)
-            self.assertEqual(ops[0].access, CS_AC_WRITE, "%s has operand 0 with invalid access" % asm)
-            if pattern_reg:
-                self.assertIn(ops[1].type, reg_types, "%s has operand 0 with invalid type" % asm)
-            else:
-                self.assertEqual(ops[1].type, CS_OP_IMM, "%s has operand 0 with invalid type" % asm)
-
-if __name__ == '__main__':
-    unittest.main()
-
diff --git a/suite/regress/test_arm64_pac.py b/suite/regress/test_arm64_pac.py
deleted file mode 100644
index 33f169fd0..000000000
--- a/suite/regress/test_arm64_pac.py
+++ /dev/null
@@ -1,97 +0,0 @@
-import unittest
-from capstone import *
-from capstone.arm64 import *
-from collections import defaultdict
-
-class ARM64PACRegAccessTest(unittest.TestCase):
-
-    PATTERNS = [
-        ("41 00 C1 DA", "pacia x1, x2"),
-        ("3F 23 03 D5", "paciasp"),
-        ("E1 23 C1 DA", "paciza x1"),
-        ("41 04 C1 DA", "pacib x1, x2"),
-        ("7F 23 03 D5", "pacibsp"),
-        ("E1 27 C1 DA", "pacizb x1"),
-        ("41 08 C1 DA", "pacda x1, x2"),
-        ("E1 2B C1 DA", "pacdza x1"),
-        ("41 0C C1 DA", "pacdb x1, x2"),
-        ("E1 2F C1 DA", "pacdzb x1"),
-        ("41 18 C1 DA", "autda x1, x2"),
-        ("E1 3B C1 DA", "autdza x1"),
-        ("41 1C C1 DA", "autdb x1, x2"),
-        ("E1 3F C1 DA", "autdzb x1"),
-        ("41 10 C1 DA", "autia x1, x2"),
-        ("BF 23 03 D5", "autiasp"),
-        ("E1 33 C1 DA", "autiza x1"),
-        ("9F 23 03 D5", "autiaz"),
-        ("41 14 C1 DA", "autib x1, x2"),
-        ("FF 23 03 D5", "autibsp"),
-        ("E1 37 C1 DA", "autizb x1"),
-        ("DF 23 03 D5", "autibz"),
-        ("E1 47 C1 DA", "xpacd x1"),
-        ("E1 43 C1 DA", "xpaci x1"),
-        ("FF 20 03 D5", "xpaclri"),
-        ]
-
-    def setUp(self):
-        self.insts = []
-        self.cs = Cs(CS_ARCH_ARM64, CS_MODE_LITTLE_ENDIAN)
-        self.cs.detail = True
-
-        for pattern, asm in self.PATTERNS:
-            # Disassemble the instruction. Any error here means Capstone doesn't handle the instruction (maybe the wrong branch)
-            inst = next(self.cs.disasm(bytes.fromhex(pattern), 0))
-
-            # Build the lists of expected read and written registers
-            regs = list(map(lambda r: r.strip(', '), asm.split()[1:]))
-            expected_regs_read = []
-            n = len(regs)
-            if(n == 0):
-                expected_regs_written = ["lr"]
-                expected_regs_read = ["lr"]
-                if(asm.endswith("sp")):
-                    expected_regs_read += ["sp"]
-            elif(n == 1):
-                expected_regs_written = [regs[0]]
-                expected_regs_read = [regs[0]]
-            elif(n == 2):
-                expected_regs_written = [regs[0]]
-                expected_regs_read = regs
-            
-            expected_regs = [expected_regs_read, expected_regs_written]
-            #print((inst, asm, expected_regs))
-
-            self.insts.append((inst, asm, expected_regs))
-
-
-    def test_regs_access(self):
-        """Check that the `regs_access` API provides correct data"""
-        
-        for inst, asm, expected_regs in self.insts:
-            for i, decoded_regs in enumerate(map(lambda l: list(map(self.cs.reg_name, l)), inst.regs_access())):
-                self.assertEqual(set(decoded_regs), set(expected_regs[i]), "%s has %r %s registers instead of %r" % (asm, decoded_regs, ["read", "written"][i], expected_regs[i]))
-
-
-    def test_operands(self):
-        """Check that the `operands` API provides correct data"""
-        for inst, asm, expected_regs in self.insts:
-            ops = inst.operands
-            asm_regs = list(map(lambda r: r.strip(', '), asm.split()[1:]))
-            self.assertEqual(len(ops), len(asm_regs))
-
-            expected_regs_accesses = defaultdict(int)
-            
-            expected_regs_read, expected_regs_written = expected_regs
-            for reg in expected_regs_written:
-                expected_regs_accesses[reg] |= CS_AC_WRITE
-            for reg in expected_regs_read:
-                expected_regs_accesses[reg] |= CS_AC_READ
-            
-            for i, op in enumerate(ops):
-                self.assertEqual(op.type, CS_OP_REG, "%s has operand %d with invalid type" % (asm, i))
-                regname = self.cs.reg_name(op.reg)
-                self.assertEqual(op.access, expected_regs_accesses[regname], "%s has operand %d (%s) with invalid access (%d != %d)" % (asm, i, regname, op.access, expected_regs_accesses[regname]))
-
-            
-if __name__ == '__main__':
-    unittest.main()
diff --git a/suite/test_all.sh b/suite/test_all.sh
deleted file mode 100755
index 1c68bc862..000000000
--- a/suite/test_all.sh
+++ /dev/null
@@ -1,9 +0,0 @@
-#!/bin/sh
-
-# dump test output to /tmp/<name> for diffing
-# this is useful to detect if a change modifies any disasm output
-
-# syntax: test_all.sh <name>
-
-# ./test_archs.py > /tmp/$1_arch
-./test_c.sh $1_c
diff --git a/suite/test_c.sh b/suite/test_c.sh
deleted file mode 100755
index 3ba937650..000000000
--- a/suite/test_c.sh
+++ /dev/null
@@ -1,28 +0,0 @@
-#!/bin/bash
-
-# Run all the Python tests, and send the output that to a file to be compared later
-# This is useful when we want to verify if a commit (wrongly) changes the disassemble result.
-
-../tests/test_arm > /tmp/$1
-../tests/test_aarch64 > /tmp/$1
-../tests/test_basic > /tmp/$1
-../tests/test_bpf > /tmp/$1
-../tests/test_customized_mnem > /tmp/$1
-../tests/test_detail > /tmp/$1
-../tests/test_evm > /tmp/$1
-../tests/test_iter > /tmp/$1
-../tests/test_m680x > /tmp/$1
-../tests/test_m68k > /tmp/$1
-../tests/test_mips > /tmp/$1
-../tests/test_mos65xx > /tmp/$1
-../tests/test_ppc > /tmp/$1
-../tests/test_skipdata > /tmp/$1
-../tests/test_sparc > /tmp/$1
-../tests/test_systemz > /tmp/$1
-../tests/test_tms320c64x > /tmp/$1
-../tests/test_wasm > /tmp/$1
-../tests/test_winkernel > /tmp/$1
-../tests/test_x86 > /tmp/$1
-../tests/test_xcore > /tmp/$1
-../tests/test_alpha > /tmp/$1
-../tests/test_hppa > /tmp/$1
\ No newline at end of file
diff --git a/suite/test_group_name.py b/suite/test_group_name.py
deleted file mode 100755
index 7f6be5110..000000000
--- a/suite/test_group_name.py
+++ /dev/null
@@ -1,283 +0,0 @@
-#!/usr/bin/python
-
-from capstone import *
-from capstone.arm import *
-from capstone.arm64 import *
-from capstone.mips import *
-from capstone.ppc import *
-from capstone.sparc import *
-from capstone.systemz import *
-from capstone.x86 import *
-from capstone.xcore import *
-from capstone.riscv import *
-import sys
-
-class GroupTest:
-    def __init__(self, name, arch, mode, data):
-        self.name = name
-        self.arch = arch
-        self.mode = mode
-        self.data = data
-
-    def run(self):
-        print('Testing %s' %self.name)
-        cap = Cs(self.arch, self.mode)
-        for group_id in xrange(0,255):
-            name = self.data.get(group_id)
-            res = cap.group_name(group_id)
-            if res != name:
-                print("ERROR: id = %u expected '%s', but got '%s'" %(group_id, name, res))
-        print("")
-
-arm_dict = {
-    ARM_GRP_JUMP: "jump",
-    ARM_GRP_CALL: "call",
-    ARM_GRP_INT: "int",
-    ARM_GRP_PRIVILEGE: "privilege",
-
-    ARM_GRP_CRYPTO: "crypto",
-    ARM_GRP_DATABARRIER: "databarrier",
-    ARM_GRP_DIVIDE: "divide",
-    ARM_GRP_FPARMV8: "fparmv8",
-    ARM_GRP_MULTPRO: "multpro",
-    ARM_GRP_NEON: "neon",
-    ARM_GRP_T2EXTRACTPACK: "T2EXTRACTPACK",
-    ARM_GRP_THUMB2DSP: "THUMB2DSP",
-    ARM_GRP_TRUSTZONE: "TRUSTZONE",
-    ARM_GRP_V4T: "v4t",
-    ARM_GRP_V5T: "v5t",
-    ARM_GRP_V5TE: "v5te",
-    ARM_GRP_V6: "v6",
-    ARM_GRP_V6T2: "v6t2",
-    ARM_GRP_V7: "v7",
-    ARM_GRP_V8: "v8",
-    ARM_GRP_VFP2: "vfp2",
-    ARM_GRP_VFP3: "vfp3",
-    ARM_GRP_VFP4: "vfp4",
-    ARM_GRP_ARM: "arm",
-    ARM_GRP_MCLASS: "mclass",
-    ARM_GRP_NOTMCLASS: "notmclass",
-    ARM_GRP_THUMB: "thumb",
-    ARM_GRP_THUMB1ONLY: "thumb1only",
-    ARM_GRP_THUMB2: "thumb2",
-    ARM_GRP_PREV8: "prev8",
-    ARM_GRP_FPVMLX: "fpvmlx",
-    ARM_GRP_MULOPS: "mulops",
-    ARM_GRP_CRC: "crc",
-    ARM_GRP_DPVFP: "dpvfp",
-    ARM_GRP_V6M: "v6m",
-    ARM_GRP_VIRTUALIZATION: "virtualization",
-}
-
-arm64_dict = {
-    AARCH64_GRP_JUMP: "jump",
-    AARCH64_GRP_CALL: "call",
-    AARCH64_GRP_RET: "return",
-    AARCH64_GRP_INT: "int",
-    AARCH64_GRP_PRIVILEGE: "privilege",
-
-    AARCH64_GRP_CRYPTO: "crypto",
-    AARCH64_GRP_FPARMV8: "fparmv8",
-    AARCH64_GRP_NEON: "neon",
-    AARCH64_GRP_CRC: "crc"
-}
-
-mips_dict = {
-    MIPS_GRP_JUMP: "jump",
-    MIPS_GRP_CALL: "call",
-    MIPS_GRP_RET: "ret",
-    MIPS_GRP_INT: "int",
-    MIPS_GRP_IRET: "iret",
-    MIPS_GRP_PRIVILEGE: "privilege",
-    MIPS_GRP_BITCOUNT: "bitcount",
-    MIPS_GRP_DSP: "dsp",
-    MIPS_GRP_DSPR2: "dspr2",
-    MIPS_GRP_FPIDX: "fpidx",
-    MIPS_GRP_MSA: "msa",
-    MIPS_GRP_MIPS32R2: "mips32r2",
-    MIPS_GRP_MIPS64: "mips64",
-    MIPS_GRP_MIPS64R2: "mips64r2",
-    MIPS_GRP_SEINREG: "seinreg",
-    MIPS_GRP_STDENC: "stdenc",
-    MIPS_GRP_SWAP: "swap",
-    MIPS_GRP_MICROMIPS: "micromips",
-    MIPS_GRP_MIPS16MODE: "mips16mode",
-    MIPS_GRP_FP64BIT: "fp64bit",
-    MIPS_GRP_NONANSFPMATH: "nonansfpmath",
-    MIPS_GRP_NOTFP64BIT: "notfp64bit",
-    MIPS_GRP_NOTINMICROMIPS: "notinmicromips",
-    MIPS_GRP_NOTNACL: "notnacl",
-
-    MIPS_GRP_NOTMIPS32R6: "notmips32r6",
-    MIPS_GRP_NOTMIPS64R6: "notmips64r6",
-    MIPS_GRP_CNMIPS: "cnmips",
-
-    MIPS_GRP_MIPS32: "mips32",
-    MIPS_GRP_MIPS32R6: "mips32r6",
-    MIPS_GRP_MIPS64R6: "mips64r6",
-
-    MIPS_GRP_MIPS2: "mips2",
-    MIPS_GRP_MIPS3: "mips3",
-    MIPS_GRP_MIPS3_32: "mips3_32",
-    MIPS_GRP_MIPS3_32R2: "mips3_32r2",
-
-    MIPS_GRP_MIPS4_32: "mips4_32",
-    MIPS_GRP_MIPS4_32R2: "mips4_32r2",
-    MIPS_GRP_MIPS5_32R2: "mips5_32r2",
-
-    MIPS_GRP_GP32BIT: "gp32bit",
-    MIPS_GRP_GP64BIT: "gp64bit",
-}
-
-ppc_dict = {
-    PPC_GRP_JUMP: "jump",
-
-    PPC_GRP_ALTIVEC: "altivec",
-    PPC_GRP_MODE32: "mode32",
-    PPC_GRP_MODE64: "mode64",
-    PPC_GRP_BOOKE: "booke",
-    PPC_GRP_NOTBOOKE: "notbooke",
-    PPC_GRP_SPE: "spe",
-    PPC_GRP_VSX: "vsx",
-    PPC_GRP_E500: "e500",
-    PPC_GRP_PPC4XX: "ppc4xx",
-    PPC_GRP_PPC6XX: "ppc6xx",
-    PPC_GRP_ICBT: "icbt",
-    PPC_GRP_P8ALTIVEC: "p8altivec",
-    PPC_GRP_P8VECTOR: "p8vector",
-    PPC_GRP_QPX: "qpx",
-    PPC_GRP_PS: "ps",
-}
-
-sparc_dict = {
-    SPARC_GRP_JUMP: "jump",
-
-    SPARC_GRP_HARDQUAD: "hardquad",
-    SPARC_GRP_V9: "v9",
-    SPARC_GRP_VIS: "vis",
-    SPARC_GRP_VIS2: "vis2",
-    SPARC_GRP_VIS3: "vis3",
-    SPARC_GRP_32BIT: "32bit",
-    SPARC_GRP_64BIT: "64bit",
-}
-
-sysz_dict = {
-    SYSZ_GRP_JUMP: "jump",
-
-    SYSZ_GRP_DISTINCTOPS: "distinctops",
-    SYSZ_GRP_FPEXTENSION: "fpextension",
-    SYSZ_GRP_HIGHWORD: "highword",
-    SYSZ_GRP_INTERLOCKEDACCESS1: "interlockedaccess1",
-    SYSZ_GRP_LOADSTOREONCOND: "loadstoreoncond",
-}
-
-x86_dict = {
-    X86_GRP_JUMP: "jump",
-    X86_GRP_CALL: "call",
-    X86_GRP_RET: "ret",
-    X86_GRP_INT: "int",
-    X86_GRP_IRET: "iret",
-    X86_GRP_PRIVILEGE: "privilege",
-
-    X86_GRP_VM: "vm",
-    X86_GRP_3DNOW: "3dnow",
-    X86_GRP_AES: "aes",
-    X86_GRP_ADX: "adx",
-    X86_GRP_AVX: "avx",
-    X86_GRP_AVX2: "avx2",
-    X86_GRP_AVX512: "avx512",
-    X86_GRP_BMI: "bmi",
-    X86_GRP_BMI2: "bmi2",
-    X86_GRP_CMOV: "cmov",
-    X86_GRP_F16C: "fc16",
-    X86_GRP_FMA: "fma",
-    X86_GRP_FMA4: "fma4",
-    X86_GRP_FSGSBASE: "fsgsbase",
-    X86_GRP_HLE: "hle",
-    X86_GRP_MMX: "mmx",
-    X86_GRP_MODE32: "mode32",
-    X86_GRP_MODE64: "mode64",
-    X86_GRP_RTM: "rtm",
-    X86_GRP_SHA: "sha",
-    X86_GRP_SSE1: "sse1",
-    X86_GRP_SSE2: "sse2",
-    X86_GRP_SSE3: "sse3",
-    X86_GRP_SSE41: "sse41",
-    X86_GRP_SSE42: "sse42",
-    X86_GRP_SSE4A: "sse4a",
-    X86_GRP_SSSE3: "ssse3",
-    X86_GRP_PCLMUL: "pclmul",
-    X86_GRP_XOP: "xop",
-    X86_GRP_CDI: "cdi",
-    X86_GRP_ERI: "eri",
-    X86_GRP_TBM: "tbm",
-    X86_GRP_16BITMODE: "16bitmode",
-    X86_GRP_NOT64BITMODE: "not64bitmode",
-    X86_GRP_SGX: "sgx",
-    X86_GRP_DQI: "dqi",
-    X86_GRP_BWI: "bwi",
-    X86_GRP_PFI: "pfi",
-    X86_GRP_VLX: "vlx",
-    X86_GRP_SMAP: "smap",
-    X86_GRP_NOVLX: "novlx",
-}
-
-xcore_dict = {
-    XCORE_GRP_JUMP: "jump",
-}
-
-riscv32_dict = {
-    RISCV_GRP_JUMP       : "jump",
-    RISCV_GRP_CALL       : "call",
-    RISCV_GRP_RET        : "ret",
-    RISCV_GRP_INT        : "int",
-    RISCV_GRP_IRET       : "iret",
-    RISCV_GRP_PRIVILEGE  : "privileged",
-    RISCV_GRP_BRANCH_RELATIVE: "branch_relative",
-    RISCV_GRP_ISRV32     : "isrv32",
-    RISCV_GRP_HASSTDEXTA : "hasstdexta",
-    RISCV_GRP_HASSTDEXTC : "hasstdextc",
-    RISCV_GRP_HASSTDEXTD : "hasstdextd",
-    RISCV_GRP_HASSTDEXTF : "hasstdextf",
-    RISCV_GRP_HASSTDEXTM : "hasstdextm",    
-}
-
-riscv64_dict = {    
-    RISCV_GRP_JUMP       : "jump",
-    RISCV_GRP_CALL       : "call",
-    RISCV_GRP_RET        : "ret",
-    RISCV_GRP_INT        : "int",
-    RISCV_GRP_IRET       : "iret",
-    RISCV_GRP_PRIVILEGE  : "privileged",
-    RISCV_GRP_BRANCH_RELATIVE: "branch_relative",
-    RISCV_GRP_ISRV64     : "isrv64",
-    RISCV_GRP_HASSTDEXTA : "hasstdexta",
-    RISCV_GRP_HASSTDEXTC : "hasstdextc",
-    RISCV_GRP_HASSTDEXTD : "hasstdextd",
-    RISCV_GRP_HASSTDEXTF : "hasstdextf",
-    RISCV_GRP_HASSTDEXTM : "hasstdextm",    
-}
-
-tests = [
-    GroupTest('arm', CS_ARCH_ARM, CS_MODE_THUMB, arm_dict),
-    GroupTest('arm64', CS_ARCH_AARCH64, CS_MODE_ARM, arm64_dict),
-    GroupTest('mips', CS_ARCH_MIPS, CS_MODE_MIPS32 | CS_MODE_BIG_ENDIAN, mips_dict),
-    GroupTest('ppc', CS_ARCH_PPC, CS_MODE_BIG_ENDIAN, ppc_dict),
-    GroupTest('sparc', CS_ARCH_SPARC, CS_MODE_BIG_ENDIAN, sparc_dict),
-    GroupTest('sysz', CS_ARCH_SYSZ, CS_MODE_BIG_ENDIAN, sysz_dict),
-    GroupTest('x86', CS_ARCH_X86, CS_MODE_32, x86_dict),
-    GroupTest('xcore', CS_ARCH_XCORE, CS_MODE_BIG_ENDIAN, xcore_dict),
-    GroupTest('m68k', CS_ARCH_M68K, CS_MODE_BIG_ENDIAN, xcore_dict),
-    GroupTest('riscv32', CS_ARCH_RISCV, CS_MODE_RISCV32, riscv32_dict),
-    GroupTest('riscv64', CS_ARCH_RISCV, CS_MODE_RISCV64, riscv64_dict),
-]
-
-if __name__ == '__main__':
-    args = sys.argv[1:]
-    all = len(args) == 0 or 'all' in args
-    for t in tests:
-        if all or t.name in args:
-            t.run()
-        else:
-            print('Skipping %s' %t.name)
-
diff --git a/suite/test_mc.py b/suite/test_mc.py
deleted file mode 100755
index c895814b1..000000000
--- a/suite/test_mc.py
+++ /dev/null
@@ -1,267 +0,0 @@
-#!/usr/bin/python
-# Test tool to compare Capstone output with llvm-mc. By Nguyen Anh Quynh, 2014
-import array, os.path, sys
-from subprocess import Popen, PIPE, STDOUT
-from capstone import *
-
-
-# convert all hex numbers to decimal numbers in a text
-def normalize_hex(a):
-    while(True):
-        i = a.find('0x')
-        if i == -1: # no more hex number
-            break
-        hexnum = '0x'
-        for c in a[i + 2:]:
-            if c in '0123456789abcdefABCDEF':
-                hexnum += c
-            else:
-                break
-        num = int(hexnum, 16)
-        a = a.replace(hexnum, str(num))
-    return a
-
-
-def run_mc(arch, hexcode, option, syntax=None):
-    def normalize(text):
-        # remove tabs
-        text = text.lower()
-        items = text.split()
-        text = ' '.join(items)
-        if arch == CS_ARCH_X86:
-            # remove comment after #
-            i = text.find('# ')
-            if i != -1:
-                return text[:i].strip()
-        if arch == CS_ARCH_AARCH64:
-            # remove comment after #
-            i = text.find('// ')
-            if i != -1:
-                return text[:i].strip()
-        # remove some redundant spaces
-        text = text.replace('{ ', '{')
-        text = text.replace(' }', '}')
-        return text.strip()
-
-    #print("Trying to decode: %s" %hexcode)
-    if syntax:
-        if arch == CS_ARCH_MIPS:
-            p = Popen(['llvm-mc', '-disassemble', '-print-imm-hex', '-mattr=+msa', syntax] + option, stdout=PIPE, stdin=PIPE, stderr=STDOUT)
-        else:
-            p = Popen(['llvm-mc', '-disassemble', '-print-imm-hex', syntax] + option, stdout=PIPE, stdin=PIPE, stderr=STDOUT)
-    else:
-        if arch == CS_ARCH_MIPS:
-            p = Popen(['llvm-mc', '-disassemble', '-print-imm-hex', '-mattr=+msa'] + option, stdout=PIPE, stdin=PIPE, stderr=STDOUT)
-        else:
-            p = Popen(['llvm-mc', '-disassemble', '-print-imm-hex'] + option, stdout=PIPE, stdin=PIPE, stderr=STDOUT)
-    output = p.communicate(input=hexcode)[0]
-    lines = output.split('\n')
-    #print lines
-    if 'invalid' in lines[0]:
-        #print 'invalid ----'
-        return 'FAILED to disassemble (MC)'
-    else:
-        #print 'OK:', lines[1]
-        return normalize(lines[1].strip())
-
-def test_file(fname):
-    print("Test %s" %fname);
-    f = open(fname)
-    lines = f.readlines()
-    f.close()
-
-    if not lines[0].startswith('# '):
-        print("ERROR: decoding information is missing")
-        return
-
-    # skip '# ' at the front, then split line to get out hexcode
-    # Note: option can be '', or 'None'
-    #print lines[0]
-    #print lines[0][2:].split(', ')
-    (arch, mode, option) = lines[0][2:].split(', ')
-    mode = mode.replace(' ', '')
-    option = option.strip()
-
-    archs = {
-        "CS_ARCH_ARM": CS_ARCH_ARM,
-        "CS_ARCH_AARCH64": CS_ARCH_AARCH64,
-        "CS_ARCH_MIPS": CS_ARCH_MIPS,
-        "CS_ARCH_PPC": CS_ARCH_PPC,
-        "CS_ARCH_SPARC": CS_ARCH_SPARC,
-        "CS_ARCH_SYSZ": CS_ARCH_SYSZ,
-        "CS_ARCH_X86": CS_ARCH_X86,
-        "CS_ARCH_XCORE": CS_ARCH_XCORE,
-        "CS_ARCH_RISCV": CS_ARCH_RISCV
-        # "CS_ARCH_M68K": CS_ARCH_M68K,
-    }
-    
-    modes = {
-        "CS_MODE_16": CS_MODE_16,
-        "CS_MODE_32": CS_MODE_32,
-        "CS_MODE_64": CS_MODE_64,
-        "CS_MODE_MIPS32": CS_MODE_MIPS32,
-        "CS_MODE_MIPS64": CS_MODE_MIPS64,
-        "0": CS_MODE_ARM,
-        "CS_MODE_ARM": CS_MODE_ARM,
-        "CS_MODE_THUMB": CS_MODE_THUMB,
-        "CS_MODE_ARM+CS_MODE_V8": CS_MODE_ARM+CS_MODE_V8,
-        "CS_MODE_THUMB+CS_MODE_V8": CS_MODE_THUMB+CS_MODE_V8,
-        "CS_MODE_THUMB+CS_MODE_MCLASS": CS_MODE_THUMB+CS_MODE_MCLASS,
-        "CS_MODE_LITTLE_ENDIAN": CS_MODE_LITTLE_ENDIAN,
-        "CS_MODE_BIG_ENDIAN": CS_MODE_BIG_ENDIAN,
-        "CS_MODE_64+CS_MODE_LITTLE_ENDIAN": CS_MODE_64+CS_MODE_LITTLE_ENDIAN,
-        "CS_MODE_64+CS_MODE_BIG_ENDIAN": CS_MODE_64+CS_MODE_BIG_ENDIAN,
-        "CS_MODE_MIPS32+CS_MODE_MICRO": CS_MODE_MIPS32+CS_MODE_MICRO,
-        "CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN": CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN,
-        "CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN+CS_MODE_MICRO": CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN,
-        "CS_MODE_BIG_ENDIAN+CS_MODE_V9": CS_MODE_BIG_ENDIAN + CS_MODE_V9,
-        "CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN": CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN,
-        "CS_MODE_MIPS32+CS_MODE_LITTLE_ENDIAN": CS_MODE_MIPS32+CS_MODE_LITTLE_ENDIAN,
-        "CS_MODE_MIPS64+CS_MODE_LITTLE_ENDIAN": CS_MODE_MIPS64+CS_MODE_LITTLE_ENDIAN,
-        "CS_MODE_MIPS64+CS_MODE_BIG_ENDIAN": CS_MODE_MIPS64+CS_MODE_BIG_ENDIAN,
-        "CS_MODE_RISCV32": CS_MODE_RISCV32,
-        "CS_MODE_RISCV64": CS_MODE_RISCV64,
-    }
-    
-    options = {
-        "CS_OPT_SYNTAX_ATT": CS_OPT_SYNTAX_ATT,
-        "CS_OPT_SYNTAX_NOREGNAME": CS_OPT_SYNTAX_NOREGNAME,
-    }
-
-    mc_modes = {
-        ("CS_ARCH_X86", "CS_MODE_32"): ['-triple=i386'],
-        ("CS_ARCH_X86", "CS_MODE_64"): ['-triple=x86_64'],
-        ("CS_ARCH_ARM", "CS_MODE_ARM"): ['-triple=armv7'],
-        ("CS_ARCH_ARM", "CS_MODE_THUMB"): ['-triple=thumbv7'],
-        ("CS_ARCH_ARM", "CS_MODE_ARM+CS_MODE_V8"): ['-triple=armv8'],
-        ("CS_ARCH_ARM", "CS_MODE_THUMB+CS_MODE_V8"): ['-triple=thumbv8'],
-        ("CS_ARCH_ARM", "CS_MODE_THUMB+CS_MODE_MCLASS"): ['-triple=thumbv7m'],
-        ("CS_ARCH_AARCH64", "0"): ['-triple=aarch64'],
-        ("CS_ARCH_MIPS", "CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN"): ['-triple=mips'],
-        ("CS_ARCH_MIPS", "CS_MODE_MIPS32+CS_MODE_MICRO"): ['-triple=mipsel', '-mattr=+micromips'],
-        ("CS_ARCH_MIPS", "CS_MODE_MIPS64"): ['-triple=mips64el'],
-        ("CS_ARCH_MIPS", "CS_MODE_MIPS32"): ['-triple=mipsel'],
-        ("CS_ARCH_MIPS", "CS_MODE_MIPS64+CS_MODE_BIG_ENDIAN"): ['-triple=mips64'],
-        ("CS_ARCH_MIPS", "CS_MODE_MIPS32+CS_MODE_MICRO+CS_MODE_BIG_ENDIAN"): ['-triple=mips', '-mattr=+micromips'],
-        ("CS_ARCH_MIPS", "CS_MODE_MIPS32+CS_MODE_BIG_ENDIAN+CS_MODE_MICRO"): ['-triple=mips', '-mattr=+micromips'],
-        ("CS_ARCH_PPC", "CS_MODE_BIG_ENDIAN"): ['-triple=powerpc64'],
-        ('CS_ARCH_SPARC', 'CS_MODE_BIG_ENDIAN'): ['-triple=sparc'],
-        ('CS_ARCH_SPARC', 'CS_MODE_BIG_ENDIAN+CS_MODE_V9'): ['-triple=sparcv9'],
-        ('CS_ARCH_SYSZ', '0'): ['-triple=s390x', '-mcpu=z196'],
-        ('CS_ARCH_RISCV', 'CS_MODE_RISCV32'): ['-triple=riscv32'],
-        ('CS_ARCH_RISCV', 'CS_MODE_RISCV64'): ['-triple=riscv64'],
-    }
-
-    #if not option in ('', 'None'):
-    #    print archs[arch], modes[mode], options[option]
-    
-    #print(arch, mode, option)
-    md = Cs(archs[arch], modes[mode])
-
-    mc_option = None
-    if arch == 'CS_ARCH_X86':
-        # tell llvm-mc to use Intel syntax
-        mc_option = '-output-asm-variant=1'
-
-    if arch == 'CS_ARCH_ARM' or arch == 'CS_ARCH_PPC' :
-        md.syntax = CS_OPT_SYNTAX_NOREGNAME
-
-    if fname.endswith('3DNow.s.cs'):
-        md.syntax = CS_OPT_SYNTAX_ATT
-
-    for line in lines[1:]:
-        # ignore all the input lines having # in front.
-        if line.startswith('#'):
-            continue
-        #print("Check %s" %line)
-        code = line.split(' = ')[0]
-        asm  = ''.join(line.split(' = ')[1:])
-        hex_code = code.replace('0x', '')
-        hex_code = hex_code.replace(',', '')
-        hex_data = hex_code.decode('hex')
-        #hex_bytes = array.array('B', hex_data)
-
-        x = list(md.disasm(hex_data, 0))
-        if len(x) > 0:
-            if x[0].op_str != '':
-                cs_output = "%s %s" %(x[0].mnemonic, x[0].op_str)
-            else:
-                cs_output = x[0].mnemonic
-        else:
-            cs_output = 'FAILED to disassemble'
-
-        cs_output2 = normalize_hex(cs_output)
-        cs_output2 = cs_output2.replace(' ', '')
-
-        if arch == 'CS_ARCH_MIPS':
-            # normalize register alias names
-            cs_output2 = cs_output2.replace('$at', '$1')
-            cs_output2 = cs_output2.replace('$v0', '$2')
-            cs_output2 = cs_output2.replace('$v1', '$3')
-
-            cs_output2 = cs_output2.replace('$a0', '$4')
-            cs_output2 = cs_output2.replace('$a1', '$5')
-            cs_output2 = cs_output2.replace('$a2', '$6')
-            cs_output2 = cs_output2.replace('$a3', '$7')
-
-            cs_output2 = cs_output2.replace('$t0', '$8')
-            cs_output2 = cs_output2.replace('$t1', '$9')
-            cs_output2 = cs_output2.replace('$t2', '$10')
-            cs_output2 = cs_output2.replace('$t3', '$11')
-            cs_output2 = cs_output2.replace('$t4', '$12')
-            cs_output2 = cs_output2.replace('$t5', '$13')
-            cs_output2 = cs_output2.replace('$t6', '$14')
-            cs_output2 = cs_output2.replace('$t7', '$15')
-            cs_output2 = cs_output2.replace('$t8', '$24')
-            cs_output2 = cs_output2.replace('$t9', '$25')
-
-            cs_output2 = cs_output2.replace('$s0', '$16')
-            cs_output2 = cs_output2.replace('$s1', '$17')
-            cs_output2 = cs_output2.replace('$s2', '$18')
-            cs_output2 = cs_output2.replace('$s3', '$19')
-            cs_output2 = cs_output2.replace('$s4', '$20')
-            cs_output2 = cs_output2.replace('$s5', '$21')
-            cs_output2 = cs_output2.replace('$s6', '$22')
-            cs_output2 = cs_output2.replace('$s7', '$23')
-
-            cs_output2 = cs_output2.replace('$k0', '$26')
-            cs_output2 = cs_output2.replace('$k1', '$27')
-
-        #print("Running MC ...")
-        if fname.endswith('thumb-fp-armv8.s.cs'):
-            mc_output = run_mc(archs[arch], code, ['-triple=thumbv8'], mc_option)
-        elif fname.endswith('mips64-alu-instructions.s.cs'):
-            mc_output = run_mc(archs[arch], code, ['-triple=mips64el', '-mcpu=mips64r2'], mc_option)
-        else:
-            mc_output = run_mc(archs[arch], code, mc_modes[(arch, mode)], mc_option)
-        mc_output2 = normalize_hex(mc_output)
-
-        if arch == 'CS_ARCH_MIPS':
-            mc_output2 = mc_output2.replace(' 0(', '(')
-
-        if arch == 'CS_ARCH_PPC':
-            mc_output2 = mc_output2.replace('.+', '')
-            mc_output2 = mc_output2.replace('.', '')
-            mc_output2 = mc_output2.replace(' 0(', '(')
-
-        mc_output2 = mc_output2.replace(' ', '')
-        mc_output2 = mc_output2.replace('opaque', '')
-
-
-        if (cs_output2 != mc_output2):
-            asm = asm.replace(' ', '').strip().lower()
-            if asm != cs_output2:
-                print("Mismatch: %s" %line.strip())
-                print("\tMC = %s" %mc_output)
-                print("\tCS = %s" %cs_output)
-
-
-if __name__ == '__main__':
-    if len(sys.argv) == 1:
-        fnames = sys.stdin.readlines()
-        for fname in fnames:
-            test_file(fname.strip())
-    else:
-        #print("Usage: ./test_mc.py <input-file.s.cs>")
-        test_file(sys.argv[1])
-
diff --git a/suite/test_mc.sh b/suite/test_mc.sh
deleted file mode 100755
index b4552aeda..000000000
--- a/suite/test_mc.sh
+++ /dev/null
@@ -1,15 +0,0 @@
-#!/bin/sh
-
-# This script test all architectures by default.
-# At the output are all the mismatches between Capstone (CS) & LLVM (MC).
-# While most differences coming from the fact that Capstone uses more friendly
-# number format, some mismatches might be because Capstone is based on older
-# version of LLVM (which should be fixed in the next release)
-
-find MC/ -name *.cs | ./test_mc.py
-
-# To test just one architecture, specify the corresponding dir:
-# $ find MC/X86 -name *.cs | ./test_mc.py
-
-# To test just one input file, run test_mc.py with that file:
-# $ ./test_mc.py MC/X86/x86-32-fma3.s.cs
diff --git a/suite/test_python.sh b/suite/test_python.sh
deleted file mode 100755
index 5445eb227..000000000
--- a/suite/test_python.sh
+++ /dev/null
@@ -1,15 +0,0 @@
-#!/bin/bash
-
-# Run all the Python tests, and send the output that to a file to be compared later
-# This is useful when we want to verify if a commit (wrongly) changes the disassemble result.
-
-../bindings/python/test.py > /tmp/$1
-../bindings/python/test_detail.py >> /tmp/$1
-../bindings/python/test_arm.py >> /tmp/$1
-../bindings/python/test_aarch64.py >> /tmp/$1
-../bindings/python/test_mips.py >> /tmp/$1
-../bindings/python/test_ppc.py >> /tmp/$1
-../bindings/python/test_sparc.py >> /tmp/$1
-../bindings/python/test_x86.py >> /tmp/$1
-../bindings/python/test_alpha.py >> /tmp/$1
-../bindings/python/test_hppa.py >> /tmp/$1
\ No newline at end of file
diff --git a/tests/MC/AArch64/CSSC/abs_32.s.yaml b/tests/MC/AArch64/CSSC/abs_32.s.yaml
new file mode 100644
index 000000000..789beaeda
--- /dev/null
+++ b/tests/MC/AArch64/CSSC/abs_32.s.yaml
@@ -0,0 +1,40 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0xc0, 0x5a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "abs w0, w0"
+
+  -
+    input:
+      bytes: [ 0x55, 0x21, 0xc0, 0x5a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "abs w21, w10"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x21, 0xc0, 0x5a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "abs w23, w13"
+
+  -
+    input:
+      bytes: [ 0xff, 0x23, 0xc0, 0x5a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "abs wzr, wzr"
diff --git a/tests/MC/AArch64/CSSC/abs_64.s.yaml b/tests/MC/AArch64/CSSC/abs_64.s.yaml
new file mode 100644
index 000000000..1a24d25b7
--- /dev/null
+++ b/tests/MC/AArch64/CSSC/abs_64.s.yaml
@@ -0,0 +1,40 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0xc0, 0xda ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "abs x0, x0"
+
+  -
+    input:
+      bytes: [ 0x55, 0x21, 0xc0, 0xda ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "abs x21, x10"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x21, 0xc0, 0xda ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "abs x23, x13"
+
+  -
+    input:
+      bytes: [ 0xff, 0x23, 0xc0, 0xda ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "abs xzr, xzr"
diff --git a/tests/MC/AArch64/CSSC/cnt_32.s.yaml b/tests/MC/AArch64/CSSC/cnt_32.s.yaml
new file mode 100644
index 000000000..138541f34
--- /dev/null
+++ b/tests/MC/AArch64/CSSC/cnt_32.s.yaml
@@ -0,0 +1,40 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x1c, 0xc0, 0x5a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "cnt w0, w0"
+
+  -
+    input:
+      bytes: [ 0x55, 0x1d, 0xc0, 0x5a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "cnt w21, w10"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x1d, 0xc0, 0x5a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "cnt w23, w13"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0xc0, 0x5a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "cnt wzr, wzr"
diff --git a/tests/MC/AArch64/CSSC/cnt_64.s.yaml b/tests/MC/AArch64/CSSC/cnt_64.s.yaml
new file mode 100644
index 000000000..b02122c84
--- /dev/null
+++ b/tests/MC/AArch64/CSSC/cnt_64.s.yaml
@@ -0,0 +1,40 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x1c, 0xc0, 0xda ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "cnt x0, x0"
+
+  -
+    input:
+      bytes: [ 0x55, 0x1d, 0xc0, 0xda ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "cnt x21, x10"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x1d, 0xc0, 0xda ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "cnt x23, x13"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0xc0, 0xda ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "cnt xzr, xzr"
diff --git a/tests/MC/AArch64/CSSC/ctz_32.s.yaml b/tests/MC/AArch64/CSSC/ctz_32.s.yaml
new file mode 100644
index 000000000..5c5fff367
--- /dev/null
+++ b/tests/MC/AArch64/CSSC/ctz_32.s.yaml
@@ -0,0 +1,40 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x18, 0xc0, 0x5a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "ctz w0, w0"
+
+  -
+    input:
+      bytes: [ 0x55, 0x19, 0xc0, 0x5a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "ctz w21, w10"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x19, 0xc0, 0x5a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "ctz w23, w13"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1b, 0xc0, 0x5a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "ctz wzr, wzr"
diff --git a/tests/MC/AArch64/CSSC/ctz_64.s.yaml b/tests/MC/AArch64/CSSC/ctz_64.s.yaml
new file mode 100644
index 000000000..14f2eff38
--- /dev/null
+++ b/tests/MC/AArch64/CSSC/ctz_64.s.yaml
@@ -0,0 +1,40 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x18, 0xc0, 0xda ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "ctz x0, x0"
+
+  -
+    input:
+      bytes: [ 0x55, 0x19, 0xc0, 0xda ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "ctz x21, x10"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x19, 0xc0, 0xda ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "ctz x23, x13"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1b, 0xc0, 0xda ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "ctz xzr, xzr"
diff --git a/tests/MC/AArch64/CSSC/smax_32_imm.s.yaml b/tests/MC/AArch64/CSSC/smax_32_imm.s.yaml
new file mode 100644
index 000000000..4d774a946
--- /dev/null
+++ b/tests/MC/AArch64/CSSC/smax_32_imm.s.yaml
@@ -0,0 +1,40 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0xc0, 0x11 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax w0, w0, #0"
+
+  -
+    input:
+      bytes: [ 0x55, 0x55, 0xc1, 0x11 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax w21, w10, #85"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0xc0, 0x11 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax w23, w13, #59"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xc3, 0x11 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax wzr, wzr, #-1"
diff --git a/tests/MC/AArch64/CSSC/smax_32_reg.s.yaml b/tests/MC/AArch64/CSSC/smax_32_reg.s.yaml
new file mode 100644
index 000000000..061ab8725
--- /dev/null
+++ b/tests/MC/AArch64/CSSC/smax_32_reg.s.yaml
@@ -0,0 +1,40 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0xc0, 0x1a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax w0, w0, w0"
+
+  -
+    input:
+      bytes: [ 0x55, 0x61, 0xd5, 0x1a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax w21, w10, w21"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x61, 0xc8, 0x1a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax w23, w13, w8"
+
+  -
+    input:
+      bytes: [ 0xff, 0x63, 0xdf, 0x1a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax wzr, wzr, wzr"
diff --git a/tests/MC/AArch64/CSSC/smax_64_imm.s.yaml b/tests/MC/AArch64/CSSC/smax_64_imm.s.yaml
new file mode 100644
index 000000000..09a6bd83f
--- /dev/null
+++ b/tests/MC/AArch64/CSSC/smax_64_imm.s.yaml
@@ -0,0 +1,40 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0xc0, 0x91 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax x0, x0, #0"
+
+  -
+    input:
+      bytes: [ 0x55, 0x55, 0xc1, 0x91 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax x21, x10, #85"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0xc0, 0x91 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax x23, x13, #59"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xc3, 0x91 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax xzr, xzr, #-1"
diff --git a/tests/MC/AArch64/CSSC/smax_64_reg.s.yaml b/tests/MC/AArch64/CSSC/smax_64_reg.s.yaml
new file mode 100644
index 000000000..eeed9baa8
--- /dev/null
+++ b/tests/MC/AArch64/CSSC/smax_64_reg.s.yaml
@@ -0,0 +1,40 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0xc0, 0x9a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax x0, x0, x0"
+
+  -
+    input:
+      bytes: [ 0x55, 0x61, 0xd5, 0x9a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax x21, x10, x21"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x61, 0xc8, 0x9a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax x23, x13, x8"
+
+  -
+    input:
+      bytes: [ 0xff, 0x63, 0xdf, 0x9a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax xzr, xzr, xzr"
diff --git a/tests/MC/AArch64/CSSC/smin_32_imm.s.yaml b/tests/MC/AArch64/CSSC/smin_32_imm.s.yaml
new file mode 100644
index 000000000..e9f490ccd
--- /dev/null
+++ b/tests/MC/AArch64/CSSC/smin_32_imm.s.yaml
@@ -0,0 +1,40 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0xc8, 0x11 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin w0, w0, #0"
+
+  -
+    input:
+      bytes: [ 0x55, 0x55, 0xc9, 0x11 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin w21, w10, #85"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0xc8, 0x11 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin w23, w13, #59"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xcb, 0x11 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin wzr, wzr, #-1"
diff --git a/tests/MC/AArch64/CSSC/smin_32_reg.s.yaml b/tests/MC/AArch64/CSSC/smin_32_reg.s.yaml
new file mode 100644
index 000000000..0188ef1a8
--- /dev/null
+++ b/tests/MC/AArch64/CSSC/smin_32_reg.s.yaml
@@ -0,0 +1,40 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x68, 0xc0, 0x1a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin w0, w0, w0"
+
+  -
+    input:
+      bytes: [ 0x55, 0x69, 0xd5, 0x1a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin w21, w10, w21"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x69, 0xc8, 0x1a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin w23, w13, w8"
+
+  -
+    input:
+      bytes: [ 0xff, 0x6b, 0xdf, 0x1a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin wzr, wzr, wzr"
diff --git a/tests/MC/AArch64/CSSC/smin_64_imm.s.yaml b/tests/MC/AArch64/CSSC/smin_64_imm.s.yaml
new file mode 100644
index 000000000..a71477310
--- /dev/null
+++ b/tests/MC/AArch64/CSSC/smin_64_imm.s.yaml
@@ -0,0 +1,40 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0xc8, 0x91 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin x0, x0, #0"
+
+  -
+    input:
+      bytes: [ 0x55, 0x55, 0xc9, 0x91 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin x21, x10, #85"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0xc8, 0x91 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin x23, x13, #59"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xcb, 0x91 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin xzr, xzr, #-1"
diff --git a/tests/MC/AArch64/CSSC/smin_64_reg.s.yaml b/tests/MC/AArch64/CSSC/smin_64_reg.s.yaml
new file mode 100644
index 000000000..614883b4d
--- /dev/null
+++ b/tests/MC/AArch64/CSSC/smin_64_reg.s.yaml
@@ -0,0 +1,40 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x68, 0xc0, 0x9a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin x0, x0, x0"
+
+  -
+    input:
+      bytes: [ 0x55, 0x69, 0xd5, 0x9a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin x21, x10, x21"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x69, 0xc8, 0x9a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin x23, x13, x8"
+
+  -
+    input:
+      bytes: [ 0xff, 0x6b, 0xdf, 0x9a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin xzr, xzr, xzr"
diff --git a/tests/MC/AArch64/CSSC/umax_32_imm.s.yaml b/tests/MC/AArch64/CSSC/umax_32_imm.s.yaml
new file mode 100644
index 000000000..6d64938c4
--- /dev/null
+++ b/tests/MC/AArch64/CSSC/umax_32_imm.s.yaml
@@ -0,0 +1,40 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0xc4, 0x11 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax w0, w0, #0"
+
+  -
+    input:
+      bytes: [ 0x55, 0x55, 0xc5, 0x11 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax w21, w10, #85"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0xc4, 0x11 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax w23, w13, #59"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xc7, 0x11 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax wzr, wzr, #255"
diff --git a/tests/MC/AArch64/CSSC/umax_32_reg.s.yaml b/tests/MC/AArch64/CSSC/umax_32_reg.s.yaml
new file mode 100644
index 000000000..7e76f6ada
--- /dev/null
+++ b/tests/MC/AArch64/CSSC/umax_32_reg.s.yaml
@@ -0,0 +1,40 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x64, 0xc0, 0x1a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax w0, w0, w0"
+
+  -
+    input:
+      bytes: [ 0x55, 0x65, 0xd5, 0x1a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax w21, w10, w21"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x65, 0xc8, 0x1a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax w23, w13, w8"
+
+  -
+    input:
+      bytes: [ 0xff, 0x67, 0xdf, 0x1a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax wzr, wzr, wzr"
diff --git a/tests/MC/AArch64/CSSC/umax_64_imm.s.yaml b/tests/MC/AArch64/CSSC/umax_64_imm.s.yaml
new file mode 100644
index 000000000..a7d12d27c
--- /dev/null
+++ b/tests/MC/AArch64/CSSC/umax_64_imm.s.yaml
@@ -0,0 +1,40 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0xc4, 0x91 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax x0, x0, #0"
+
+  -
+    input:
+      bytes: [ 0x55, 0x55, 0xc5, 0x91 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax x21, x10, #85"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0xc4, 0x91 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax x23, x13, #59"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xc7, 0x91 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax xzr, xzr, #255"
diff --git a/tests/MC/AArch64/CSSC/umax_64_reg.s.yaml b/tests/MC/AArch64/CSSC/umax_64_reg.s.yaml
new file mode 100644
index 000000000..57c722eb2
--- /dev/null
+++ b/tests/MC/AArch64/CSSC/umax_64_reg.s.yaml
@@ -0,0 +1,40 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x64, 0xc0, 0x9a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax x0, x0, x0"
+
+  -
+    input:
+      bytes: [ 0x55, 0x65, 0xd5, 0x9a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax x21, x10, x21"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x65, 0xc8, 0x9a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax x23, x13, x8"
+
+  -
+    input:
+      bytes: [ 0xff, 0x67, 0xdf, 0x9a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax xzr, xzr, xzr"
diff --git a/tests/MC/AArch64/CSSC/umin_32_imm.s.yaml b/tests/MC/AArch64/CSSC/umin_32_imm.s.yaml
new file mode 100644
index 000000000..0173a5101
--- /dev/null
+++ b/tests/MC/AArch64/CSSC/umin_32_imm.s.yaml
@@ -0,0 +1,40 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0xcc, 0x11 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin w0, w0, #0"
+
+  -
+    input:
+      bytes: [ 0x55, 0x55, 0xcd, 0x11 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin w21, w10, #85"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0xcc, 0x11 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin w23, w13, #59"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xcf, 0x11 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin wzr, wzr, #255"
diff --git a/tests/MC/AArch64/CSSC/umin_32_reg.s.yaml b/tests/MC/AArch64/CSSC/umin_32_reg.s.yaml
new file mode 100644
index 000000000..9e321eefc
--- /dev/null
+++ b/tests/MC/AArch64/CSSC/umin_32_reg.s.yaml
@@ -0,0 +1,40 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x6c, 0xc0, 0x1a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin w0, w0, w0"
+
+  -
+    input:
+      bytes: [ 0x55, 0x6d, 0xd5, 0x1a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin w21, w10, w21"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x6d, 0xc8, 0x1a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin w23, w13, w8"
+
+  -
+    input:
+      bytes: [ 0xff, 0x6f, 0xdf, 0x1a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin wzr, wzr, wzr"
diff --git a/tests/MC/AArch64/CSSC/umin_64_imm.s.yaml b/tests/MC/AArch64/CSSC/umin_64_imm.s.yaml
new file mode 100644
index 000000000..c73be6c47
--- /dev/null
+++ b/tests/MC/AArch64/CSSC/umin_64_imm.s.yaml
@@ -0,0 +1,40 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0xcc, 0x91 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin x0, x0, #0"
+
+  -
+    input:
+      bytes: [ 0x55, 0x55, 0xcd, 0x91 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin x21, x10, #85"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0xcc, 0x91 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin x23, x13, #59"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xcf, 0x91 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin xzr, xzr, #255"
diff --git a/tests/MC/AArch64/CSSC/umin_64_reg.s.yaml b/tests/MC/AArch64/CSSC/umin_64_reg.s.yaml
new file mode 100644
index 000000000..8e3e58d9e
--- /dev/null
+++ b/tests/MC/AArch64/CSSC/umin_64_reg.s.yaml
@@ -0,0 +1,40 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x6c, 0xc0, 0x9a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin x0, x0, x0"
+
+  -
+    input:
+      bytes: [ 0x55, 0x6d, 0xd5, 0x9a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin x21, x10, x21"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x6d, 0xc8, 0x9a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin x23, x13, x8"
+
+  -
+    input:
+      bytes: [ 0xff, 0x6f, 0xdf, 0x9a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin xzr, xzr, xzr"
diff --git a/tests/MC/AArch64/FP8/dot.s.yaml b/tests/MC/AArch64/FP8/dot.s.yaml
new file mode 100644
index 000000000..7a2716fdc
--- /dev/null
+++ b/tests/MC/AArch64/FP8/dot.s.yaml
@@ -0,0 +1,90 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x1f, 0xfc, 0x40, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8dot2", "+fp8dot4" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot v31.4h, v0.8b, v0.8b"
+
+  -
+    input:
+      bytes: [ 0x1f, 0xfc, 0x5f, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8dot2", "+fp8dot4" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot v31.8h, v0.16b, v31.16b"
+
+  -
+    input:
+      bytes: [ 0x00, 0xfc, 0x1f, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8dot2", "+fp8dot4" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot v0.2s, v0.8b, v31.8b"
+
+  -
+    input:
+      bytes: [ 0x1f, 0xfc, 0x1f, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8dot2", "+fp8dot4" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot v31.4s, v0.16b, v31.16b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x03, 0x4f, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8dot2", "+fp8dot4" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot v31.4h, v31.8b, v15.2b[0]"
+
+  -
+    input:
+      bytes: [ 0xda, 0x02, 0x49, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8dot2", "+fp8dot4" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot v26.8h, v22.16b, v9.2b[0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x08, 0x7f, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8dot2", "+fp8dot4" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot v0.8h, v0.16b, v15.2b[7]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x1f, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8dot2", "+fp8dot4" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot v0.2s, v0.8b, v31.4b[0]"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x0b, 0x20, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8dot2", "+fp8dot4" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot v0.4s, v31.16b, v0.4b[3]"
diff --git a/tests/MC/AArch64/FP8/faminmax.s.yaml b/tests/MC/AArch64/FP8/faminmax.s.yaml
new file mode 100644
index 000000000..25292d895
--- /dev/null
+++ b/tests/MC/AArch64/FP8/faminmax.s.yaml
@@ -0,0 +1,300 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0xdf, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "faminmax" ]
+    expected:
+      insns:
+        -
+          asm_text: "famax v31.4h, v31.4h, v31.4h"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x1c, 0xdf, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "faminmax" ]
+    expected:
+      insns:
+        -
+          asm_text: "famax v31.4h, v0.4h, v31.4h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x1c, 0xc0, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "faminmax" ]
+    expected:
+      insns:
+        -
+          asm_text: "famax v0.4h, v0.4h, v0.4h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0xdf, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "faminmax" ]
+    expected:
+      insns:
+        -
+          asm_text: "famax v31.8h, v31.8h, v31.8h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0xc0, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "faminmax" ]
+    expected:
+      insns:
+        -
+          asm_text: "famax v31.8h, v31.8h, v0.8h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x1c, 0xc0, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "faminmax" ]
+    expected:
+      insns:
+        -
+          asm_text: "famax v0.8h, v0.8h, v0.8h"
+
+  -
+    input:
+      bytes: [ 0xff, 0xdf, 0xbf, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "faminmax" ]
+    expected:
+      insns:
+        -
+          asm_text: "famax v31.2s, v31.2s, v31.2s"
+
+  -
+    input:
+      bytes: [ 0x1f, 0xdc, 0xa0, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "faminmax" ]
+    expected:
+      insns:
+        -
+          asm_text: "famax v31.2s, v0.2s, v0.2s"
+
+  -
+    input:
+      bytes: [ 0x00, 0xdc, 0xa0, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "faminmax" ]
+    expected:
+      insns:
+        -
+          asm_text: "famax v0.2s, v0.2s, v0.2s"
+
+  -
+    input:
+      bytes: [ 0xff, 0xdf, 0xbf, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "faminmax" ]
+    expected:
+      insns:
+        -
+          asm_text: "famax v31.4s, v31.4s, v31.4s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xdf, 0xbf, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "faminmax" ]
+    expected:
+      insns:
+        -
+          asm_text: "famax v0.4s, v31.4s, v31.4s"
+
+  -
+    input:
+      bytes: [ 0x00, 0xdc, 0xa0, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "faminmax" ]
+    expected:
+      insns:
+        -
+          asm_text: "famax v0.4s, v0.4s, v0.4s"
+
+  -
+    input:
+      bytes: [ 0xff, 0xdf, 0xff, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "faminmax" ]
+    expected:
+      insns:
+        -
+          asm_text: "famax v31.2d, v31.2d, v31.2d"
+
+  -
+    input:
+      bytes: [ 0x00, 0xdc, 0xff, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "faminmax" ]
+    expected:
+      insns:
+        -
+          asm_text: "famax v0.2d, v0.2d, v31.2d"
+
+  -
+    input:
+      bytes: [ 0x00, 0xdc, 0xe0, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "faminmax" ]
+    expected:
+      insns:
+        -
+          asm_text: "famax v0.2d, v0.2d, v0.2d"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0xdf, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "faminmax" ]
+    expected:
+      insns:
+        -
+          asm_text: "famin v31.4h, v31.4h, v31.4h"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x1c, 0xdf, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "faminmax" ]
+    expected:
+      insns:
+        -
+          asm_text: "famin v31.4h, v0.4h, v31.4h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x1c, 0xc0, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "faminmax" ]
+    expected:
+      insns:
+        -
+          asm_text: "famin v0.4h, v0.4h, v0.4h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0xdf, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "faminmax" ]
+    expected:
+      insns:
+        -
+          asm_text: "famin v31.8h, v31.8h, v31.8h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0xc0, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "faminmax" ]
+    expected:
+      insns:
+        -
+          asm_text: "famin v31.8h, v31.8h, v0.8h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x1c, 0xc0, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "faminmax" ]
+    expected:
+      insns:
+        -
+          asm_text: "famin v0.8h, v0.8h, v0.8h"
+
+  -
+    input:
+      bytes: [ 0xff, 0xdf, 0xbf, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "faminmax" ]
+    expected:
+      insns:
+        -
+          asm_text: "famin v31.2s, v31.2s, v31.2s"
+
+  -
+    input:
+      bytes: [ 0x1f, 0xdc, 0xa0, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "faminmax" ]
+    expected:
+      insns:
+        -
+          asm_text: "famin v31.2s, v0.2s, v0.2s"
+
+  -
+    input:
+      bytes: [ 0x00, 0xdc, 0xa0, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "faminmax" ]
+    expected:
+      insns:
+        -
+          asm_text: "famin v0.2s, v0.2s, v0.2s"
+
+  -
+    input:
+      bytes: [ 0xff, 0xdf, 0xbf, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "faminmax" ]
+    expected:
+      insns:
+        -
+          asm_text: "famin v31.4s, v31.4s, v31.4s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xdf, 0xbf, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "faminmax" ]
+    expected:
+      insns:
+        -
+          asm_text: "famin v0.4s, v31.4s, v31.4s"
+
+  -
+    input:
+      bytes: [ 0x00, 0xdc, 0xa0, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "faminmax" ]
+    expected:
+      insns:
+        -
+          asm_text: "famin v0.4s, v0.4s, v0.4s"
+
+  -
+    input:
+      bytes: [ 0xff, 0xdf, 0xff, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "faminmax" ]
+    expected:
+      insns:
+        -
+          asm_text: "famin v31.2d, v31.2d, v31.2d"
+
+  -
+    input:
+      bytes: [ 0x00, 0xdc, 0xff, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "faminmax" ]
+    expected:
+      insns:
+        -
+          asm_text: "famin v0.2d, v0.2d, v31.2d"
+
+  -
+    input:
+      bytes: [ 0x00, 0xdc, 0xe0, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "faminmax" ]
+    expected:
+      insns:
+        -
+          asm_text: "famin v0.2d, v0.2d, v0.2d"
diff --git a/tests/MC/AArch64/FP8/luti2.s.yaml b/tests/MC/AArch64/FP8/luti2.s.yaml
new file mode 100644
index 000000000..59b52d412
--- /dev/null
+++ b/tests/MC/AArch64/FP8/luti2.s.yaml
@@ -0,0 +1,40 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x41, 0x10, 0x80, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "lut" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti2 v1.16b, { v2.16b }, v0[0]"
+
+  -
+    input:
+      bytes: [ 0x9e, 0x72, 0x9f, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "lut" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti2 v30.16b, { v20.16b }, v31[3]"
+
+  -
+    input:
+      bytes: [ 0x41, 0x00, 0xc0, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "lut" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti2 v1.8h, { v2.8h }, v0[0]"
+
+  -
+    input:
+      bytes: [ 0x9e, 0x72, 0xdf, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "lut" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti2 v30.8h, { v20.8h }, v31[7]"
diff --git a/tests/MC/AArch64/FP8/luti4.s.yaml b/tests/MC/AArch64/FP8/luti4.s.yaml
new file mode 100644
index 000000000..ecd19031a
--- /dev/null
+++ b/tests/MC/AArch64/FP8/luti4.s.yaml
@@ -0,0 +1,40 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x41, 0x20, 0x40, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "lut" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti4 v1.16b, { v2.16b }, v0[0]"
+
+  -
+    input:
+      bytes: [ 0x9e, 0x62, 0x5f, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "lut" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti4 v30.16b, { v20.16b }, v31[1]"
+
+  -
+    input:
+      bytes: [ 0x41, 0x10, 0x40, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "lut" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti4 v1.8h, { v2.8h, v3.8h }, v0[0]"
+
+  -
+    input:
+      bytes: [ 0x9e, 0x72, 0x5f, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "lut" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti4 v30.8h, { v20.8h, v21.8h }, v31[3]"
diff --git a/tests/MC/AArch64/FP8/miscellaneous-fp8.s.yaml b/tests/MC/AArch64/FP8/miscellaneous-fp8.s.yaml
new file mode 100644
index 000000000..35e095d29
--- /dev/null
+++ b/tests/MC/AArch64/FP8/miscellaneous-fp8.s.yaml
@@ -0,0 +1,510 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x78, 0xa1, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "bf1cvtl v0.8h, v0.8b"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x7b, 0xa1, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "bf1cvtl v0.8h, v31.8b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x7b, 0xa1, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "bf1cvtl v31.8h, v31.8b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x78, 0xa1, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "bf1cvtl2 v0.8h, v0.16b"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x7b, 0xa1, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "bf1cvtl2 v0.8h, v31.16b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x7b, 0xa1, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "bf1cvtl2 v31.8h, v31.16b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x78, 0xe1, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "bf2cvtl v0.8h, v0.8b"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x7b, 0xe1, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "bf2cvtl v0.8h, v31.8b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x7b, 0xe1, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "bf2cvtl v31.8h, v31.8b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x78, 0xe1, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "bf2cvtl2 v0.8h, v0.16b"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x7b, 0xe1, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "bf2cvtl2 v0.8h, v31.16b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x7b, 0xe1, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "bf2cvtl2 v31.8h, v31.16b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x78, 0x21, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "f1cvtl v0.8h, v0.8b"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x7b, 0x21, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "f1cvtl v0.8h, v31.8b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x7b, 0x21, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "f1cvtl v31.8h, v31.8b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x78, 0x21, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "f1cvtl2 v0.8h, v0.16b"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x7b, 0x21, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "f1cvtl2 v0.8h, v31.16b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x7b, 0x21, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "f1cvtl2 v31.8h, v31.16b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x78, 0x61, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "f2cvtl v0.8h, v0.8b"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x7b, 0x61, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "f2cvtl v0.8h, v31.8b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x7b, 0x61, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "f2cvtl v31.8h, v31.8b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x78, 0x61, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "f2cvtl2 v0.8h, v0.16b"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x7b, 0x61, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "f2cvtl2 v0.8h, v31.16b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x7b, 0x61, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "f2cvtl2 v31.8h, v31.16b"
+
+  -
+    input:
+      bytes: [ 0xff, 0xf7, 0x5f, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtn v31.8b, v31.4h, v31.4h"
+
+  -
+    input:
+      bytes: [ 0x1f, 0xf4, 0x40, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtn v31.8b, v0.4h, v0.4h"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf4, 0x40, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtn v0.8b, v0.4h, v0.4h"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf4, 0x40, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtn v0.16b, v0.8h, v0.8h"
+
+  -
+    input:
+      bytes: [ 0x1f, 0xf4, 0x40, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtn v31.16b, v0.8h, v0.8h"
+
+  -
+    input:
+      bytes: [ 0xff, 0xf7, 0x5f, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtn v31.16b, v31.8h, v31.8h"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf4, 0x00, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtn v0.8b, v0.4s, v0.4s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf7, 0x1f, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtn v0.8b, v31.4s, v31.4s"
+
+  -
+    input:
+      bytes: [ 0xff, 0xf7, 0x1f, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtn v31.8b, v31.4s, v31.4s"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf4, 0x00, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtn2 v0.16b, v0.4s, v0.4s"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf4, 0x1f, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtn2 v0.16b, v0.4s, v31.4s"
+
+  -
+    input:
+      bytes: [ 0xff, 0xf7, 0x1f, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtn2 v31.16b, v31.4s, v31.4s"
+
+  -
+    input:
+      bytes: [ 0x00, 0x3c, 0xc0, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fscale v0.4h, v0.4h, v0.4h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3f, 0xdf, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fscale v0.4h, v31.4h, v31.4h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0xdf, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fscale v31.4h, v31.4h, v31.4h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x3c, 0xc0, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fscale v0.8h, v0.8h, v0.8h"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x3c, 0xc0, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fscale v31.8h, v0.8h, v0.8h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0xdf, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fscale v31.8h, v31.8h, v31.8h"
+
+  -
+    input:
+      bytes: [ 0x00, 0xfc, 0xa0, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fscale v0.2s, v0.2s, v0.2s"
+
+  -
+    input:
+      bytes: [ 0x00, 0xfc, 0xbf, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fscale v0.2s, v0.2s, v31.2s"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xbf, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fscale v31.2s, v31.2s, v31.2s"
+
+  -
+    input:
+      bytes: [ 0x00, 0xfc, 0xa0, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fscale v0.4s, v0.4s, v0.4s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xff, 0xa0, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fscale v0.4s, v31.4s, v0.4s"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xbf, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fscale v31.4s, v31.4s, v31.4s"
+
+  -
+    input:
+      bytes: [ 0x00, 0xfc, 0xe0, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fscale v0.2d, v0.2d, v0.2d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xff, 0xe0, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fscale v0.2d, v31.2d, v0.2d"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xff, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fscale v31.2d, v31.2d, v31.2d"
diff --git a/tests/MC/AArch64/FP8/mla.s.yaml b/tests/MC/AArch64/FP8/mla.s.yaml
new file mode 100644
index 000000000..cae0c6538
--- /dev/null
+++ b/tests/MC/AArch64/FP8/mla.s.yaml
@@ -0,0 +1,130 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xfc, 0xc0, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8fma" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlalb v0.8h, v0.16b, v0.16b"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xdf, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8fma" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlalt v31.8h, v31.16b, v31.16b"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc4, 0x1f, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8fma" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlallbb v0.4s, v0.16b, v31.16b"
+
+  -
+    input:
+      bytes: [ 0xff, 0xc7, 0x40, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8fma" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlallbt v31.4s, v31.16b, v0.16b"
+
+  -
+    input:
+      bytes: [ 0xff, 0xc7, 0x00, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8fma" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlalltb v31.4s, v31.16b, v0.16b"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc4, 0x5f, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8fma" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlalltt v0.4s, v0.16b, v31.16b"
+
+  -
+    input:
+      bytes: [ 0xff, 0xc7, 0x5f, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8fma" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlalltt v31.4s, v31.16b, v31.16b"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x00, 0xc0, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8fma" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlalb v31.8h, v0.16b, v0.b[0]"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x08, 0xf8, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8fma" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlalt v31.8h, v0.16b, v0.b[15]"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x80, 0x07, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8fma" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlallbb v31.4s, v0.16b, v7.b[0]"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x80, 0x47, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8fma" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlalltt v31.4s, v0.16b, v7.b[0]"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x8b, 0x3f, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8fma" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlalltb v0.4s, v31.16b, v7.b[15]"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x8b, 0x78, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp8fma" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlallbt v0.4s, v31.16b, v0.b[15]"
diff --git a/tests/MC/AArch64/FP8/system-regs.s.yaml b/tests/MC/AArch64/FP8/system-regs.s.yaml
new file mode 100644
index 000000000..4acc7a828
--- /dev/null
+++ b/tests/MC/AArch64/FP8/system-regs.s.yaml
@@ -0,0 +1,30 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x43, 0x44, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fpmr" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, FPMR"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x04, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fpmr" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, ID_AA64FPFR0_EL1"
+
+  -
+    input:
+      bytes: [ 0x43, 0x44, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fpmr" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr FPMR, x3"
diff --git a/tests/MC/AArch64/FP8_SME2/cvt.s.yaml b/tests/MC/AArch64/FP8_SME2/cvt.s.yaml
new file mode 100644
index 000000000..89b871cf8
--- /dev/null
+++ b/tests/MC/AArch64/FP8_SME2/cvt.s.yaml
@@ -0,0 +1,240 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x26, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "f1cvt { z0.h, z1.h }, z0.b"
+
+  -
+    input:
+      bytes: [ 0xfe, 0xe3, 0x26, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "f1cvt { z30.h, z31.h }, z31.b"
+
+  -
+    input:
+      bytes: [ 0x01, 0xe0, 0x26, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "f1cvtl { z0.h, z1.h }, z0.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0xe3, 0x26, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "f1cvtl { z30.h, z31.h }, z31.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x66, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "bf1cvt { z0.h, z1.h }, z0.b"
+
+  -
+    input:
+      bytes: [ 0xfe, 0xe3, 0x66, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "bf1cvt { z30.h, z31.h }, z31.b"
+
+  -
+    input:
+      bytes: [ 0x01, 0xe0, 0x66, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "bf1cvtl { z0.h, z1.h }, z0.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0xe3, 0x66, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "bf1cvtl { z30.h, z31.h }, z31.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xe6, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "bf2cvt { z0.h, z1.h }, z0.b"
+
+  -
+    input:
+      bytes: [ 0xfe, 0xe3, 0xe6, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "bf2cvt { z30.h, z31.h }, z31.b"
+
+  -
+    input:
+      bytes: [ 0x01, 0xe0, 0xe6, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "bf2cvtl { z0.h, z1.h }, z0.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0xe3, 0xe6, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "bf2cvtl { z30.h, z31.h }, z31.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xa6, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "f2cvt { z0.h, z1.h }, z0.b"
+
+  -
+    input:
+      bytes: [ 0xfe, 0xe3, 0xa6, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "f2cvt { z30.h, z31.h }, z31.b"
+
+  -
+    input:
+      bytes: [ 0x01, 0xe0, 0xa6, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "f2cvtl { z0.h, z1.h }, z0.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0xe3, 0xa6, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "f2cvtl { z30.h, z31.h }, z31.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x24, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvt z0.b, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xe3, 0x24, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvt z31.b, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x34, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvt z0.b, { z0.s - z3.s }"
+
+  -
+    input:
+      bytes: [ 0x9f, 0xe3, 0x34, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvt z31.b, { z28.s - z31.s }"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe0, 0x34, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtn z0.b, { z0.s - z3.s }"
+
+  -
+    input:
+      bytes: [ 0xbf, 0xe3, 0x34, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtn z31.b, { z28.s - z31.s }"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x64, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfcvt z0.b, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xe3, 0x64, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfcvt z31.b, { z30.h, z31.h }"
diff --git a/tests/MC/AArch64/FP8_SME2/dot.s.yaml b/tests/MC/AArch64/FP8_SME2/dot.s.yaml
new file mode 100644
index 000000000..e762d7cc8
--- /dev/null
+++ b/tests/MC/AArch64/FP8_SME2/dot.s.yaml
@@ -0,0 +1,560 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x08, 0x10, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.h[w8, 0, vgx2], { z0.b, z1.b }, z0.b"
+
+  -
+    input:
+      bytes: [ 0x08, 0x10, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.h[w8, 0, vgx2], { z0.b, z1.b }, z0.b"
+
+  -
+    input:
+      bytes: [ 0xaf, 0x71, 0x28, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.h[w11, 7, vgx2], { z13.b, z14.b }, z8.b"
+
+  -
+    input:
+      bytes: [ 0xef, 0x73, 0x2f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.h[w11, 7, vgx2], { z31.b, z0.b }, z15.b"
+
+  -
+    input:
+      bytes: [ 0x18, 0x10, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w8, 0, vgx2], { z0.b, z1.b }, z0.b"
+
+  -
+    input:
+      bytes: [ 0x18, 0x10, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w8, 0, vgx2], { z0.b, z1.b }, z0.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x73, 0x2f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w11, 7, vgx2], { z31.b, z0.b }, z15.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x73, 0x2f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w11, 7, vgx2], { z31.b, z0.b }, z15.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x10, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.h[w8, 0, vgx2], { z0.b, z1.b }, { z0.b, z1.b }"
+
+  -
+    input:
+      bytes: [ 0x20, 0x10, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.h[w8, 0, vgx2], { z0.b, z1.b }, { z0.b, z1.b }"
+
+  -
+    input:
+      bytes: [ 0xe7, 0x73, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.h[w11, 7, vgx2], { z30.b, z31.b }, { z30.b, z31.b }"
+
+  -
+    input:
+      bytes: [ 0xe7, 0x73, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.h[w11, 7, vgx2], { z30.b, z31.b }, { z30.b, z31.b }"
+
+  -
+    input:
+      bytes: [ 0x30, 0x10, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w8, 0, vgx2], { z0.b, z1.b }, { z0.b, z1.b }"
+
+  -
+    input:
+      bytes: [ 0x30, 0x10, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w8, 0, vgx2], { z0.b, z1.b }, { z0.b, z1.b }"
+
+  -
+    input:
+      bytes: [ 0xf7, 0x73, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w11, 7, vgx2], { z30.b, z31.b }, { z30.b, z31.b }"
+
+  -
+    input:
+      bytes: [ 0xf7, 0x73, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w11, 7, vgx2], { z30.b, z31.b }, { z30.b, z31.b }"
+
+  -
+    input:
+      bytes: [ 0x20, 0x00, 0xd0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.h[w8, 0, vgx2], { z0.b, z1.b }, z0.b[0]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x00, 0xd0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.h[w8, 0, vgx2], { z0.b, z1.b }, z0.b[0]"
+
+  -
+    input:
+      bytes: [ 0xef, 0x6f, 0xdf, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.h[w11, 7, vgx2], { z30.b, z31.b }, z15.b[7]"
+
+  -
+    input:
+      bytes: [ 0xef, 0x6f, 0xdf, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.h[w11, 7, vgx2], { z30.b, z31.b }, z15.b[7]"
+
+  -
+    input:
+      bytes: [ 0x38, 0x00, 0x50, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w8, 0, vgx2], { z0.b, z1.b }, z0.b[0]"
+
+  -
+    input:
+      bytes: [ 0x38, 0x00, 0x50, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w8, 0, vgx2], { z0.b, z1.b }, z0.b[0]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x6f, 0x5f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w11, 7, vgx2], { z30.b, z31.b }, z15.b[3]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x6f, 0x5f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w11, 7, vgx2], { z30.b, z31.b }, z15.b[3]"
+
+  -
+    input:
+      bytes: [ 0x08, 0x10, 0x30, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.h[w8, 0, vgx4], { z0.b - z3.b }, z0.b"
+
+  -
+    input:
+      bytes: [ 0x08, 0x10, 0x30, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.h[w8, 0, vgx4], { z0.b - z3.b }, z0.b"
+
+  -
+    input:
+      bytes: [ 0xef, 0x73, 0x3f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.h[w11, 7, vgx4], { z31.b, z0.b, z1.b, z2.b }, z15.b"
+
+  -
+    input:
+      bytes: [ 0xef, 0x73, 0x3f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.h[w11, 7, vgx4], { z31.b, z0.b, z1.b, z2.b }, z15.b"
+
+  -
+    input:
+      bytes: [ 0x18, 0x10, 0x30, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w8, 0, vgx4], { z0.b - z3.b }, z0.b"
+
+  -
+    input:
+      bytes: [ 0x18, 0x10, 0x30, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w8, 0, vgx4], { z0.b - z3.b }, z0.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x73, 0x3f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w11, 7, vgx4], { z31.b, z0.b, z1.b, z2.b }, z15.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x73, 0x3f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w11, 7, vgx4], { z31.b, z0.b, z1.b, z2.b }, z15.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x10, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.h[w8, 0, vgx4], { z0.b - z3.b }, { z0.b - z3.b }"
+
+  -
+    input:
+      bytes: [ 0x20, 0x10, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.h[w8, 0, vgx4], { z0.b - z3.b }, { z0.b - z3.b }"
+
+  -
+    input:
+      bytes: [ 0xa7, 0x73, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.h[w11, 7, vgx4], { z28.b - z31.b }, { z28.b - z31.b }"
+
+  -
+    input:
+      bytes: [ 0xa7, 0x73, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.h[w11, 7, vgx4], { z28.b - z31.b }, { z28.b - z31.b }"
+
+  -
+    input:
+      bytes: [ 0x40, 0x90, 0x10, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.h[w8, 0, vgx4], { z0.b - z3.b }, z0.b[0]"
+
+  -
+    input:
+      bytes: [ 0x30, 0x10, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w8, 0, vgx4], { z0.b - z3.b }, { z0.b - z3.b }"
+
+  -
+    input:
+      bytes: [ 0x30, 0x10, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w8, 0, vgx4], { z0.b - z3.b }, { z0.b - z3.b }"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x73, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w11, 7, vgx4], { z28.b - z31.b }, { z28.b - z31.b }"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x73, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w11, 7, vgx4], { z28.b - z31.b }, { z28.b - z31.b }"
+
+  -
+    input:
+      bytes: [ 0x40, 0x90, 0x10, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.h[w8, 0, vgx4], { z0.b - z3.b }, z0.b[0]"
+
+  -
+    input:
+      bytes: [ 0xcf, 0xff, 0x1f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.h[w11, 7, vgx4], { z28.b - z31.b }, z15.b[7]"
+
+  -
+    input:
+      bytes: [ 0xcf, 0xff, 0x1f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.h[w11, 7, vgx4], { z28.b - z31.b }, z15.b[7]"
+
+  -
+    input:
+      bytes: [ 0x08, 0x80, 0x50, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w8, 0, vgx4], { z0.b - z3.b }, z0.b[0]"
+
+  -
+    input:
+      bytes: [ 0x08, 0x80, 0x50, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w8, 0, vgx4], { z0.b - z3.b }, z0.b[0]"
+
+  -
+    input:
+      bytes: [ 0x8f, 0xef, 0x5f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w11, 7, vgx4], { z28.b - z31.b }, z15.b[3]"
+
+  -
+    input:
+      bytes: [ 0x8f, 0xef, 0x5f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w11, 7, vgx4], { z28.b - z31.b }, z15.b[3]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x10, 0xd0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fvdot za.h[w8, 0, vgx2], { z0.b, z1.b }, z0.b[0]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x10, 0xd0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fvdot za.h[w8, 0, vgx2], { z0.b, z1.b }, z0.b[0]"
+
+  -
+    input:
+      bytes: [ 0xef, 0x7f, 0xdf, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fvdot za.h[w11, 7, vgx2], { z30.b, z31.b }, z15.b[7]"
+
+  -
+    input:
+      bytes: [ 0xef, 0x7f, 0xdf, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fvdot za.h[w11, 7, vgx2], { z30.b, z31.b }, z15.b[7]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x08, 0xd0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fvdotb za.s[w8, 0, vgx4], { z0.b, z1.b }, z0.b[0]"
+
+  -
+    input:
+      bytes: [ 0xcf, 0x6f, 0xdf, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fvdotb za.s[w11, 7, vgx4], { z30.b, z31.b }, z15.b[3]"
+
+  -
+    input:
+      bytes: [ 0x10, 0x08, 0xd0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fvdott za.s[w8, 0, vgx4], { z0.b, z1.b }, z0.b[0]"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x6f, 0xdf, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fvdott za.s[w11, 7, vgx4], { z30.b, z31.b }, z15.b[3]"
diff --git a/tests/MC/AArch64/FP8_SME2/faminmax.s.yaml b/tests/MC/AArch64/FP8_SME2/faminmax.s.yaml
new file mode 100644
index 000000000..c678bcbf6
--- /dev/null
+++ b/tests/MC/AArch64/FP8_SME2/faminmax.s.yaml
@@ -0,0 +1,240 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x40, 0xb1, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+faminmax" ]
+    expected:
+      insns:
+        -
+          asm_text: "famax { z0.h, z1.h }, { z0.h, z1.h }, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x5e, 0xb1, 0x7e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+faminmax" ]
+    expected:
+      insns:
+        -
+          asm_text: "famax { z30.h, z31.h }, { z30.h, z31.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x40, 0xb1, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+faminmax" ]
+    expected:
+      insns:
+        -
+          asm_text: "famax { z0.s, z1.s }, { z0.s, z1.s }, { z0.s, z1.s }"
+
+  -
+    input:
+      bytes: [ 0x5e, 0xb1, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+faminmax" ]
+    expected:
+      insns:
+        -
+          asm_text: "famax { z30.s, z31.s }, { z30.s, z31.s }, { z30.s, z31.s }"
+
+  -
+    input:
+      bytes: [ 0x40, 0xb1, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+faminmax" ]
+    expected:
+      insns:
+        -
+          asm_text: "famax { z0.d, z1.d }, { z0.d, z1.d }, { z0.d, z1.d }"
+
+  -
+    input:
+      bytes: [ 0x5e, 0xb1, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+faminmax" ]
+    expected:
+      insns:
+        -
+          asm_text: "famax { z30.d, z31.d }, { z30.d, z31.d }, { z30.d, z31.d }"
+
+  -
+    input:
+      bytes: [ 0x40, 0xb9, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+faminmax" ]
+    expected:
+      insns:
+        -
+          asm_text: "famax { z0.h - z3.h }, { z0.h - z3.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x5c, 0xb9, 0x7c, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+faminmax" ]
+    expected:
+      insns:
+        -
+          asm_text: "famax { z28.h - z31.h }, { z28.h - z31.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x40, 0xb9, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+faminmax" ]
+    expected:
+      insns:
+        -
+          asm_text: "famax { z0.s - z3.s }, { z0.s - z3.s }, { z0.s - z3.s }"
+
+  -
+    input:
+      bytes: [ 0x5c, 0xb9, 0xbc, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+faminmax" ]
+    expected:
+      insns:
+        -
+          asm_text: "famax { z28.s - z31.s }, { z28.s - z31.s }, { z28.s - z31.s }"
+
+  -
+    input:
+      bytes: [ 0x40, 0xb9, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+faminmax" ]
+    expected:
+      insns:
+        -
+          asm_text: "famax { z0.h - z3.h }, { z0.h - z3.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x5c, 0xb9, 0x7c, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+faminmax" ]
+    expected:
+      insns:
+        -
+          asm_text: "famax { z28.h - z31.h }, { z28.h - z31.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x41, 0xb1, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+faminmax" ]
+    expected:
+      insns:
+        -
+          asm_text: "famin { z0.h, z1.h }, { z0.h, z1.h }, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x5f, 0xb1, 0x7e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+faminmax" ]
+    expected:
+      insns:
+        -
+          asm_text: "famin { z30.h, z31.h }, { z30.h, z31.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x41, 0xb1, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+faminmax" ]
+    expected:
+      insns:
+        -
+          asm_text: "famin { z0.s, z1.s }, { z0.s, z1.s }, { z0.s, z1.s }"
+
+  -
+    input:
+      bytes: [ 0x5f, 0xb1, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+faminmax" ]
+    expected:
+      insns:
+        -
+          asm_text: "famin { z30.s, z31.s }, { z30.s, z31.s }, { z30.s, z31.s }"
+
+  -
+    input:
+      bytes: [ 0x41, 0xb1, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+faminmax" ]
+    expected:
+      insns:
+        -
+          asm_text: "famin { z0.d, z1.d }, { z0.d, z1.d }, { z0.d, z1.d }"
+
+  -
+    input:
+      bytes: [ 0x5f, 0xb1, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+faminmax" ]
+    expected:
+      insns:
+        -
+          asm_text: "famin { z30.d, z31.d }, { z30.d, z31.d }, { z30.d, z31.d }"
+
+  -
+    input:
+      bytes: [ 0x41, 0xb9, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+faminmax" ]
+    expected:
+      insns:
+        -
+          asm_text: "famin { z0.h - z3.h }, { z0.h - z3.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x5d, 0xb9, 0x7c, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+faminmax" ]
+    expected:
+      insns:
+        -
+          asm_text: "famin { z28.h - z31.h }, { z28.h - z31.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x41, 0xb9, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+faminmax" ]
+    expected:
+      insns:
+        -
+          asm_text: "famin { z0.s - z3.s }, { z0.s - z3.s }, { z0.s - z3.s }"
+
+  -
+    input:
+      bytes: [ 0x5d, 0xb9, 0xbc, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+faminmax" ]
+    expected:
+      insns:
+        -
+          asm_text: "famin { z28.s - z31.s }, { z28.s - z31.s }, { z28.s - z31.s }"
+
+  -
+    input:
+      bytes: [ 0x41, 0xb9, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+faminmax" ]
+    expected:
+      insns:
+        -
+          asm_text: "famin { z0.d - z3.d }, { z0.d - z3.d }, { z0.d - z3.d }"
+
+  -
+    input:
+      bytes: [ 0x5d, 0xb9, 0xfc, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+faminmax" ]
+    expected:
+      insns:
+        -
+          asm_text: "famin { z28.d - z31.d }, { z28.d - z31.d }, { z28.d - z31.d }"
diff --git a/tests/MC/AArch64/FP8_SME2/fscale.s.yaml b/tests/MC/AArch64/FP8_SME2/fscale.s.yaml
new file mode 100644
index 000000000..ed662e0d1
--- /dev/null
+++ b/tests/MC/AArch64/FP8_SME2/fscale.s.yaml
@@ -0,0 +1,240 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x80, 0xa1, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fscale { z0.h, z1.h }, { z0.h, z1.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x9e, 0xa1, 0x6f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fscale { z30.h, z31.h }, { z30.h, z31.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0x80, 0xa1, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fscale { z0.s, z1.s }, { z0.s, z1.s }, z0.s"
+
+  -
+    input:
+      bytes: [ 0x9e, 0xa1, 0xaf, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fscale { z30.s, z31.s }, { z30.s, z31.s }, z15.s"
+
+  -
+    input:
+      bytes: [ 0x80, 0xa1, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fscale { z0.d, z1.d }, { z0.d, z1.d }, z0.d"
+
+  -
+    input:
+      bytes: [ 0x9e, 0xa1, 0xef, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fscale { z30.d, z31.d }, { z30.d, z31.d }, z15.d"
+
+  -
+    input:
+      bytes: [ 0x80, 0xb1, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fscale { z0.h, z1.h }, { z0.h, z1.h }, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x9e, 0xb1, 0x7e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fscale { z30.h, z31.h }, { z30.h, z31.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x80, 0xb1, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fscale { z0.s, z1.s }, { z0.s, z1.s }, { z0.s, z1.s }"
+
+  -
+    input:
+      bytes: [ 0x9e, 0xb1, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fscale { z30.s, z31.s }, { z30.s, z31.s }, { z30.s, z31.s }"
+
+  -
+    input:
+      bytes: [ 0x80, 0xb1, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fscale { z0.d, z1.d }, { z0.d, z1.d }, { z0.d, z1.d }"
+
+  -
+    input:
+      bytes: [ 0x9e, 0xb1, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fscale { z30.d, z31.d }, { z30.d, z31.d }, { z30.d, z31.d }"
+
+  -
+    input:
+      bytes: [ 0x80, 0xa9, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fscale { z0.h - z3.h }, { z0.h - z3.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x9c, 0xa9, 0x6f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fscale { z28.h - z31.h }, { z28.h - z31.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0x80, 0xa9, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fscale { z0.s - z3.s }, { z0.s - z3.s }, z0.s"
+
+  -
+    input:
+      bytes: [ 0x9c, 0xa9, 0xaf, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fscale { z28.s - z31.s }, { z28.s - z31.s }, z15.s"
+
+  -
+    input:
+      bytes: [ 0x80, 0xa9, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fscale { z0.d - z3.d }, { z0.d - z3.d }, z0.d"
+
+  -
+    input:
+      bytes: [ 0x9c, 0xa9, 0xef, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fscale { z28.d - z31.d }, { z28.d - z31.d }, z15.d"
+
+  -
+    input:
+      bytes: [ 0x80, 0xb9, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fscale { z0.h - z3.h }, { z0.h - z3.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x9c, 0xb9, 0x7c, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fscale { z28.h - z31.h }, { z28.h - z31.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x80, 0xb9, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fscale { z0.s - z3.s }, { z0.s - z3.s }, { z0.s - z3.s }"
+
+  -
+    input:
+      bytes: [ 0x9c, 0xb9, 0xbc, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fscale { z28.s - z31.s }, { z28.s - z31.s }, { z28.s - z31.s }"
+
+  -
+    input:
+      bytes: [ 0x80, 0xb9, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fscale { z0.d - z3.d }, { z0.d - z3.d }, { z0.d - z3.d }"
+
+  -
+    input:
+      bytes: [ 0x9c, 0xb9, 0xfc, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fscale { z28.d - z31.d }, { z28.d - z31.d }, { z28.d - z31.d }"
diff --git a/tests/MC/AArch64/FP8_SME2/lut.s.yaml b/tests/MC/AArch64/FP8_SME2/lut.s.yaml
new file mode 100644
index 000000000..271782a4b
--- /dev/null
+++ b/tests/MC/AArch64/FP8_SME2/lut.s.yaml
@@ -0,0 +1,40 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x8b, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme2p1", "+sme-lutv2" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti4 { z0.b - z3.b }, zt0, { z0, z1 }"
+
+  -
+    input:
+      bytes: [ 0xdc, 0x03, 0x8b, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme2p1", "+sme-lutv2" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti4 { z28.b - z31.b }, zt0, { z30, z31 }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x9b, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme2p1", "+sme-lutv2" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti4 { z0.b, z4.b, z8.b, z12.b }, zt0, { z0, z1 }"
+
+  -
+    input:
+      bytes: [ 0xd3, 0x03, 0x9b, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme2p1", "+sme-lutv2" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti4 { z19.b, z23.b, z27.b, z31.b }, zt0, { z30, z31 }"
diff --git a/tests/MC/AArch64/FP8_SME2/mla.s.yaml b/tests/MC/AArch64/FP8_SME2/mla.s.yaml
new file mode 100644
index 000000000..7b0f23e79
--- /dev/null
+++ b/tests/MC/AArch64/FP8_SME2/mla.s.yaml
@@ -0,0 +1,560 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x0c, 0x30, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.h[w8, 0:1], z0.b, z0.b"
+
+  -
+    input:
+      bytes: [ 0xe7, 0x6f, 0x3f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.h[w11, 14:15], z31.b, z15.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0xc0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.h[w8, 0:1], z0.b, z0.b[0]"
+
+  -
+    input:
+      bytes: [ 0xef, 0xef, 0xcf, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.h[w11, 14:15], z31.b, z15.b[15]"
+
+  -
+    input:
+      bytes: [ 0x04, 0x08, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.h[w8, 0:1, vgx2], { z0.b, z1.b }, z0.b"
+
+  -
+    input:
+      bytes: [ 0x04, 0x08, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.h[w8, 0:1, vgx2], { z0.b, z1.b }, z0.b"
+
+  -
+    input:
+      bytes: [ 0xe7, 0x6b, 0x2f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.h[w11, 6:7, vgx2], { z31.b, z0.b }, z15.b"
+
+  -
+    input:
+      bytes: [ 0xe7, 0x6b, 0x2f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.h[w11, 6:7, vgx2], { z31.b, z0.b }, z15.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x08, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.h[w8, 0:1, vgx2], { z0.b, z1.b }, { z0.b, z1.b }"
+
+  -
+    input:
+      bytes: [ 0x20, 0x08, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.h[w8, 0:1, vgx2], { z0.b, z1.b }, { z0.b, z1.b }"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x6b, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.h[w11, 6:7, vgx2], { z30.b, z31.b }, { z30.b, z31.b }"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x6b, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.h[w11, 6:7, vgx2], { z30.b, z31.b }, { z30.b, z31.b }"
+
+  -
+    input:
+      bytes: [ 0x30, 0x10, 0x90, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.h[w8, 0:1, vgx2], { z0.b, z1.b }, z0.b[0]"
+
+  -
+    input:
+      bytes: [ 0x30, 0x10, 0x90, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.h[w8, 0:1, vgx2], { z0.b, z1.b }, z0.b[0]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x7f, 0x9f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.h[w11, 6:7, vgx2], { z30.b, z31.b }, z15.b[15]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x7f, 0x9f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.h[w11, 6:7, vgx2], { z30.b, z31.b }, z15.b[15]"
+
+  -
+    input:
+      bytes: [ 0x04, 0x08, 0x30, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.h[w8, 0:1, vgx4], { z0.b - z3.b }, z0.b"
+
+  -
+    input:
+      bytes: [ 0x04, 0x08, 0x30, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.h[w8, 0:1, vgx4], { z0.b - z3.b }, z0.b"
+
+  -
+    input:
+      bytes: [ 0xe7, 0x6b, 0x3f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.h[w11, 6:7, vgx4], { z31.b, z0.b, z1.b, z2.b }, z15.b"
+
+  -
+    input:
+      bytes: [ 0xe7, 0x6b, 0x3f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.h[w11, 6:7, vgx4], { z31.b, z0.b, z1.b, z2.b }, z15.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x08, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.h[w8, 0:1, vgx4], { z0.b - z3.b }, { z0.b - z3.b }"
+
+  -
+    input:
+      bytes: [ 0x20, 0x08, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.h[w8, 0:1, vgx4], { z0.b - z3.b }, { z0.b - z3.b }"
+
+  -
+    input:
+      bytes: [ 0xa3, 0x6b, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.h[w11, 6:7, vgx4], { z28.b - z31.b }, { z28.b - z31.b }"
+
+  -
+    input:
+      bytes: [ 0xa3, 0x6b, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.h[w11, 6:7, vgx4], { z28.b - z31.b }, { z28.b - z31.b }"
+
+  -
+    input:
+      bytes: [ 0x20, 0x90, 0x90, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.h[w8, 0:1, vgx4], { z0.b - z3.b }, z0.b[0]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x90, 0x90, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.h[w8, 0:1, vgx4], { z0.b - z3.b }, z0.b[0]"
+
+  -
+    input:
+      bytes: [ 0xaf, 0xff, 0x9f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.h[w11, 6:7, vgx4], { z28.b - z31.b }, z15.b[15]"
+
+  -
+    input:
+      bytes: [ 0xaf, 0xff, 0x9f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.h[w11, 6:7, vgx4], { z28.b - z31.b }, z15.b[15]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x04, 0x30, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlall za.s[w8, 0:3], z0.b, z0.b"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x67, 0x3f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlall za.s[w11, 12:15], z31.b, z15.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x40, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlall za.s[w8, 0:3], z0.b, z0.b[0]"
+
+  -
+    input:
+      bytes: [ 0xe3, 0xff, 0x4f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlall za.s[w11, 12:15], z31.b, z15.b[15]"
+
+  -
+    input:
+      bytes: [ 0x02, 0x00, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlall za.s[w8, 0:3,  vgx2], { z0.b, z1.b }, z0.b"
+
+  -
+    input:
+      bytes: [ 0x02, 0x00, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlall za.s[w8, 0:3,  vgx2], { z0.b, z1.b }, z0.b"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x63, 0x2f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlall za.s[w11, 4:7,  vgx2], { z31.b, z0.b }, z15.b"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x63, 0x2f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlall za.s[w11, 4:7,  vgx2], { z31.b, z0.b }, z15.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x00, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlall za.s[w8, 0:3, vgx2], { z0.b, z1.b }, { z0.b, z1.b }"
+
+  -
+    input:
+      bytes: [ 0x20, 0x00, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlall za.s[w8, 0:3, vgx2], { z0.b, z1.b }, { z0.b, z1.b }"
+
+  -
+    input:
+      bytes: [ 0xe1, 0x63, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlall za.s[w11, 4:7, vgx2], { z30.b, z31.b }, { z30.b, z31.b }"
+
+  -
+    input:
+      bytes: [ 0xe1, 0x63, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlall za.s[w11, 4:7, vgx2], { z30.b, z31.b }, { z30.b, z31.b }"
+
+  -
+    input:
+      bytes: [ 0x20, 0x00, 0x90, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlall za.s[w8, 0:3, vgx2], { z0.b, z1.b }, z0.b[0]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x00, 0x90, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlall za.s[w8, 0:3, vgx2], { z0.b, z1.b }, z0.b[0]"
+
+  -
+    input:
+      bytes: [ 0xe7, 0x6f, 0x9f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlall za.s[w11, 4:7, vgx2], { z30.b, z31.b }, z15.b[15]"
+
+  -
+    input:
+      bytes: [ 0xe7, 0x6f, 0x9f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlall za.s[w11, 4:7, vgx2], { z30.b, z31.b }, z15.b[15]"
+
+  -
+    input:
+      bytes: [ 0x02, 0x00, 0x30, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlall za.s[w8, 0:3,  vgx4], { z0.b - z3.b }, z0.b"
+
+  -
+    input:
+      bytes: [ 0x02, 0x00, 0x30, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlall za.s[w8, 0:3,  vgx4], { z0.b - z3.b }, z0.b"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x63, 0x3f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlall za.s[w11, 4:7,  vgx4], { z31.b, z0.b, z1.b, z2.b }, z15.b"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x63, 0x3f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlall za.s[w11, 4:7,  vgx4], { z31.b, z0.b, z1.b, z2.b }, z15.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x00, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlall za.s[w8, 0:3, vgx4], { z0.b - z3.b }, { z0.b - z3.b }"
+
+  -
+    input:
+      bytes: [ 0x20, 0x00, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlall za.s[w8, 0:3, vgx4], { z0.b - z3.b }, { z0.b - z3.b }"
+
+  -
+    input:
+      bytes: [ 0xa1, 0x63, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlall za.s[w11, 4:7, vgx4], { z28.b - z31.b }, { z28.b - z31.b }"
+
+  -
+    input:
+      bytes: [ 0xa1, 0x63, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlall za.s[w11, 4:7, vgx4], { z28.b - z31.b }, { z28.b - z31.b }"
+
+  -
+    input:
+      bytes: [ 0x40, 0x80, 0x10, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlall za.s[w8, 0:3, vgx4], { z0.b - z3.b }, z0.b[0]"
+
+  -
+    input:
+      bytes: [ 0x40, 0x80, 0x10, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlall za.s[w8, 0:3, vgx4], { z0.b - z3.b }, z0.b[0]"
+
+  -
+    input:
+      bytes: [ 0xc7, 0xef, 0x1f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlall za.s[w11, 4:7, vgx4], { z28.b - z31.b }, z15.b[15]"
+
+  -
+    input:
+      bytes: [ 0xc7, 0xef, 0x1f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlall za.s[w11, 4:7, vgx4], { z28.b - z31.b }, z15.b[15]"
diff --git a/tests/MC/AArch64/FP8_SME2/mopa.s.yaml b/tests/MC/AArch64/FP8_SME2/mopa.s.yaml
new file mode 100644
index 000000000..7f831e83d
--- /dev/null
+++ b/tests/MC/AArch64/FP8_SME2/mopa.s.yaml
@@ -0,0 +1,40 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x08, 0x00, 0xa0, 0x80 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmopa za0.h, p0/m, p0/m, z0.b, z0.b"
+
+  -
+    input:
+      bytes: [ 0xe9, 0xff, 0xbf, 0x80 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmopa za1.h, p7/m, p7/m, z31.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0xa0, 0x80 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmopa za0.s, p0/m, p0/m, z0.b, z0.b"
+
+  -
+    input:
+      bytes: [ 0xe3, 0xff, 0xbf, 0x80 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f8f16", "+sme-f8f32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmopa za3.s, p7/m, p7/m, z31.b, z31.b"
diff --git a/tests/MC/AArch64/FP8_SME2/movt.s.yaml b/tests/MC/AArch64/FP8_SME2/movt.s.yaml
new file mode 100644
index 000000000..f8364b7a6
--- /dev/null
+++ b/tests/MC/AArch64/FP8_SME2/movt.s.yaml
@@ -0,0 +1,20 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xe0, 0x03, 0x4f, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-lutv2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movt zt0, z0"
+
+  -
+    input:
+      bytes: [ 0xff, 0x33, 0x4f, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-lutv2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movt zt0[3, mul vl], z31"
diff --git a/tests/MC/AArch64/FP8_SVE2/faminmax.s.yaml b/tests/MC/AArch64/FP8_SVE2/faminmax.s.yaml
new file mode 100644
index 000000000..63e32a4f5
--- /dev/null
+++ b/tests/MC/AArch64/FP8_SVE2/faminmax.s.yaml
@@ -0,0 +1,480 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x4f, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+faminmax" ]
+    expected:
+      insns:
+        -
+          asm_text: "famin z0.h, p0/m, z0.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0xf7, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+faminmax" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z23, z31"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x8d, 0x4f, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+faminmax" ]
+    expected:
+      insns:
+        -
+          asm_text: "famin z23.h, p3/m, z23.h, z13.h"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0x4f, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+faminmax" ]
+    expected:
+      insns:
+        -
+          asm_text: "famin z31.h, p7/m, z31.h, z30.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x8f, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+faminmax" ]
+    expected:
+      insns:
+        -
+          asm_text: "famin z0.s, p0/m, z0.s, z1.s"
+
+  -
+    input:
+      bytes: [ 0xf7, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+faminmax" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z23, z31"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x8d, 0x8f, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+faminmax" ]
+    expected:
+      insns:
+        -
+          asm_text: "famin z23.s, p3/m, z23.s, z13.s"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0x8f, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+faminmax" ]
+    expected:
+      insns:
+        -
+          asm_text: "famin z31.s, p7/m, z31.s, z30.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0xcf, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+faminmax" ]
+    expected:
+      insns:
+        -
+          asm_text: "famin z0.d, p0/m, z0.d, z1.d"
+
+  -
+    input:
+      bytes: [ 0xf7, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+faminmax" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z23, z31"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x8d, 0xcf, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+faminmax" ]
+    expected:
+      insns:
+        -
+          asm_text: "famin z23.d, p3/m, z23.d, z13.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xcf, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+faminmax" ]
+    expected:
+      insns:
+        -
+          asm_text: "famin z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x4e, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+faminmax" ]
+    expected:
+      insns:
+        -
+          asm_text: "famax z0.h, p0/m, z0.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0xf7, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+faminmax" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z23, z31"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x8d, 0x4e, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+faminmax" ]
+    expected:
+      insns:
+        -
+          asm_text: "famax z23.h, p3/m, z23.h, z13.h"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0x4e, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+faminmax" ]
+    expected:
+      insns:
+        -
+          asm_text: "famax z31.h, p7/m, z31.h, z30.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x8e, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+faminmax" ]
+    expected:
+      insns:
+        -
+          asm_text: "famax z0.s, p0/m, z0.s, z1.s"
+
+  -
+    input:
+      bytes: [ 0xf7, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+faminmax" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z23, z31"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x8d, 0x8e, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+faminmax" ]
+    expected:
+      insns:
+        -
+          asm_text: "famax z23.s, p3/m, z23.s, z13.s"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0x8e, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+faminmax" ]
+    expected:
+      insns:
+        -
+          asm_text: "famax z31.s, p7/m, z31.s, z30.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0xce, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+faminmax" ]
+    expected:
+      insns:
+        -
+          asm_text: "famax z0.d, p0/m, z0.d, z1.d"
+
+  -
+    input:
+      bytes: [ 0xf7, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+faminmax" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z23, z31"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x8d, 0xce, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+faminmax" ]
+    expected:
+      insns:
+        -
+          asm_text: "famax z23.d, p3/m, z23.d, z13.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xce, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+faminmax" ]
+    expected:
+      insns:
+        -
+          asm_text: "famax z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x4f, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+faminmax" ]
+    expected:
+      insns:
+        -
+          asm_text: "famin z0.h, p0/m, z0.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0xf7, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+faminmax" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z23, z31"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x8d, 0x4f, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+faminmax" ]
+    expected:
+      insns:
+        -
+          asm_text: "famin z23.h, p3/m, z23.h, z13.h"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0x4f, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+faminmax" ]
+    expected:
+      insns:
+        -
+          asm_text: "famin z31.h, p7/m, z31.h, z30.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x8f, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+faminmax" ]
+    expected:
+      insns:
+        -
+          asm_text: "famin z0.s, p0/m, z0.s, z1.s"
+
+  -
+    input:
+      bytes: [ 0xf7, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+faminmax" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z23, z31"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x8d, 0x8f, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+faminmax" ]
+    expected:
+      insns:
+        -
+          asm_text: "famin z23.s, p3/m, z23.s, z13.s"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0x8f, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+faminmax" ]
+    expected:
+      insns:
+        -
+          asm_text: "famin z31.s, p7/m, z31.s, z30.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0xcf, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+faminmax" ]
+    expected:
+      insns:
+        -
+          asm_text: "famin z0.d, p0/m, z0.d, z1.d"
+
+  -
+    input:
+      bytes: [ 0xf7, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+faminmax" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z23, z31"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x8d, 0xcf, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+faminmax" ]
+    expected:
+      insns:
+        -
+          asm_text: "famin z23.d, p3/m, z23.d, z13.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xcf, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+faminmax" ]
+    expected:
+      insns:
+        -
+          asm_text: "famin z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x4e, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+faminmax" ]
+    expected:
+      insns:
+        -
+          asm_text: "famax z0.h, p0/m, z0.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0xf7, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+faminmax" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z23, z31"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x8d, 0x4e, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+faminmax" ]
+    expected:
+      insns:
+        -
+          asm_text: "famax z23.h, p3/m, z23.h, z13.h"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0x4e, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+faminmax" ]
+    expected:
+      insns:
+        -
+          asm_text: "famax z31.h, p7/m, z31.h, z30.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x8e, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+faminmax" ]
+    expected:
+      insns:
+        -
+          asm_text: "famax z0.s, p0/m, z0.s, z1.s"
+
+  -
+    input:
+      bytes: [ 0xf7, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+faminmax" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z23, z31"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x8d, 0x8e, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+faminmax" ]
+    expected:
+      insns:
+        -
+          asm_text: "famax z23.s, p3/m, z23.s, z13.s"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0x8e, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+faminmax" ]
+    expected:
+      insns:
+        -
+          asm_text: "famax z31.s, p7/m, z31.s, z30.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0xce, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+faminmax" ]
+    expected:
+      insns:
+        -
+          asm_text: "famax z0.d, p0/m, z0.d, z1.d"
+
+  -
+    input:
+      bytes: [ 0xf7, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+faminmax" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z23, z31"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x8d, 0xce, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+faminmax" ]
+    expected:
+      insns:
+        -
+          asm_text: "famax z23.d, p3/m, z23.d, z13.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xce, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+faminmax" ]
+    expected:
+      insns:
+        -
+          asm_text: "famax z31.d, p7/m, z31.d, z30.d"
diff --git a/tests/MC/AArch64/FP8_SVE2/fcvt.s.yaml b/tests/MC/AArch64/FP8_SVE2/fcvt.s.yaml
new file mode 100644
index 000000000..2da807e2d
--- /dev/null
+++ b/tests/MC/AArch64/FP8_SVE2/fcvt.s.yaml
@@ -0,0 +1,640 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x30, 0x08, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "f1cvt z0.h, z0.b"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x33, 0x08, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "f1cvt z0.h, z31.b"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x30, 0x08, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "f1cvt z31.h, z0.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x33, 0x08, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "f1cvt z31.h, z31.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x34, 0x08, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "f2cvt z0.h, z0.b"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x37, 0x08, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "f2cvt z0.h, z31.b"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x34, 0x08, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "f2cvt z31.h, z0.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x37, 0x08, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "f2cvt z31.h, z31.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x38, 0x08, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "bf1cvt z0.h, z0.b"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3b, 0x08, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "bf1cvt z0.h, z31.b"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x38, 0x08, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "bf1cvt z31.h, z0.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3b, 0x08, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "bf1cvt z31.h, z31.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x3c, 0x08, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "bf2cvt z0.h, z0.b"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3f, 0x08, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "bf2cvt z0.h, z31.b"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x3c, 0x08, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "bf2cvt z31.h, z0.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0x08, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "bf2cvt z31.h, z31.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x30, 0x09, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "f1cvtlt z0.h, z0.b"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x33, 0x09, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "f1cvtlt z0.h, z31.b"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x30, 0x09, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "f1cvtlt z31.h, z0.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x33, 0x09, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "f1cvtlt z31.h, z31.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x34, 0x09, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "f2cvtlt z0.h, z0.b"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x37, 0x09, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "f2cvtlt z0.h, z31.b"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x34, 0x09, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "f2cvtlt z31.h, z0.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x37, 0x09, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "f2cvtlt z31.h, z31.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x38, 0x09, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "bf1cvtlt z0.h, z0.b"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3b, 0x09, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "bf1cvtlt z0.h, z31.b"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x38, 0x09, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "bf1cvtlt z31.h, z0.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3b, 0x09, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "bf1cvtlt z31.h, z31.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x3c, 0x09, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "bf2cvtlt z0.h, z0.b"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3f, 0x09, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "bf2cvtlt z0.h, z31.b"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x3c, 0x09, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "bf2cvtlt z31.h, z0.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0x09, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "bf2cvtlt z31.h, z31.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x30, 0x08, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "f1cvt z0.h, z0.b"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x33, 0x08, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "f1cvt z0.h, z31.b"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x30, 0x08, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "f1cvt z31.h, z0.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x33, 0x08, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "f1cvt z31.h, z31.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x34, 0x08, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "f2cvt z0.h, z0.b"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x37, 0x08, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "f2cvt z0.h, z31.b"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x34, 0x08, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "f2cvt z31.h, z0.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x37, 0x08, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "f2cvt z31.h, z31.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x38, 0x08, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "bf1cvt z0.h, z0.b"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3b, 0x08, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "bf1cvt z0.h, z31.b"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x38, 0x08, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "bf1cvt z31.h, z0.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3b, 0x08, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "bf1cvt z31.h, z31.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x3c, 0x08, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "bf2cvt z0.h, z0.b"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3f, 0x08, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "bf2cvt z0.h, z31.b"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x3c, 0x08, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "bf2cvt z31.h, z0.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0x08, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "bf2cvt z31.h, z31.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x30, 0x09, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "f1cvtlt z0.h, z0.b"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x33, 0x09, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "f1cvtlt z0.h, z31.b"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x30, 0x09, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "f1cvtlt z31.h, z0.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x33, 0x09, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "f1cvtlt z31.h, z31.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x34, 0x09, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "f2cvtlt z0.h, z0.b"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x37, 0x09, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "f2cvtlt z0.h, z31.b"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x34, 0x09, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "f2cvtlt z31.h, z0.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x37, 0x09, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "f2cvtlt z31.h, z31.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x38, 0x09, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "bf1cvtlt z0.h, z0.b"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3b, 0x09, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "bf1cvtlt z0.h, z31.b"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x38, 0x09, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "bf1cvtlt z31.h, z0.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3b, 0x09, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "bf1cvtlt z31.h, z31.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x3c, 0x09, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "bf2cvtlt z0.h, z0.b"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3f, 0x09, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "bf2cvtlt z0.h, z31.b"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x3c, 0x09, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "bf2cvtlt z31.h, z0.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0x09, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "bf2cvtlt z31.h, z31.b"
diff --git a/tests/MC/AArch64/FP8_SVE2/fcvtn.s.yaml b/tests/MC/AArch64/FP8_SVE2/fcvtn.s.yaml
new file mode 100644
index 000000000..c3bacb5f4
--- /dev/null
+++ b/tests/MC/AArch64/FP8_SVE2/fcvtn.s.yaml
@@ -0,0 +1,320 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x30, 0x0a, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtn z0.b, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0xc0, 0x33, 0x0a, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtn z0.b, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x30, 0x0a, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtn z31.b, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x33, 0x0a, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtn z31.b, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x34, 0x0a, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtnb z0.b, { z0.s, z1.s }"
+
+  -
+    input:
+      bytes: [ 0xc0, 0x37, 0x0a, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtnb z0.b, { z30.s, z31.s }"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x34, 0x0a, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtnb z31.b, { z0.s, z1.s }"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x37, 0x0a, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtnb z31.b, { z30.s, z31.s }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x38, 0x0a, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfcvtn z0.b, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0xc0, 0x3b, 0x0a, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfcvtn z0.b, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x38, 0x0a, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfcvtn z31.b, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x3b, 0x0a, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfcvtn z31.b, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x3c, 0x0a, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtnt z0.b, { z0.s, z1.s }"
+
+  -
+    input:
+      bytes: [ 0xc0, 0x3f, 0x0a, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtnt z0.b, { z30.s, z31.s }"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x3c, 0x0a, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtnt z31.b, { z0.s, z1.s }"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x3f, 0x0a, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtnt z31.b, { z30.s, z31.s }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x30, 0x0a, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtn z0.b, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0xc0, 0x33, 0x0a, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtn z0.b, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x30, 0x0a, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtn z31.b, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x33, 0x0a, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtn z31.b, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x34, 0x0a, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtnb z0.b, { z0.s, z1.s }"
+
+  -
+    input:
+      bytes: [ 0xc0, 0x37, 0x0a, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtnb z0.b, { z30.s, z31.s }"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x34, 0x0a, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtnb z31.b, { z0.s, z1.s }"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x37, 0x0a, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtnb z31.b, { z30.s, z31.s }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x38, 0x0a, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfcvtn z0.b, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0xc0, 0x3b, 0x0a, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfcvtn z0.b, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x38, 0x0a, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfcvtn z31.b, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x3b, 0x0a, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfcvtn z31.b, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x3c, 0x0a, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtnt z0.b, { z0.s, z1.s }"
+
+  -
+    input:
+      bytes: [ 0xc0, 0x3f, 0x0a, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtnt z0.b, { z30.s, z31.s }"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x3c, 0x0a, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtnt z31.b, { z0.s, z1.s }"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x3f, 0x0a, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+fp8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtnt z31.b, { z30.s, z31.s }"
diff --git a/tests/MC/AArch64/FP8_SVE2/fdot.s.yaml b/tests/MC/AArch64/FP8_SVE2/fdot.s.yaml
new file mode 100644
index 000000000..1eefeab3e
--- /dev/null
+++ b/tests/MC/AArch64/FP8_SVE2/fdot.s.yaml
@@ -0,0 +1,160 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x44, 0x20, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8dot2", "+ssve-fp8dot4" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot z0.h, z0.b, z0.b[0]"
+
+  -
+    input:
+      bytes: [ 0xf7, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8dot2", "+ssve-fp8dot4" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z23, z31"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x4d, 0x28, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8dot2", "+ssve-fp8dot4" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot z23.h, z13.b, z0.b[3]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x4f, 0x3f, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8dot2", "+ssve-fp8dot4" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot z31.h, z31.b, z7.b[7]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x84, 0x20, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8dot2", "+ssve-fp8dot4" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot z0.h, z0.b, z0.b"
+
+  -
+    input:
+      bytes: [ 0xf7, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8dot2", "+ssve-fp8dot4" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z23, z31"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x85, 0x28, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8dot2", "+ssve-fp8dot4" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot z23.h, z13.b, z8.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x87, 0x3f, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8dot2", "+ssve-fp8dot4" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot z31.h, z31.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x44, 0x60, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8dot2", "+ssve-fp8dot4" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot z0.s, z0.b, z0.b[0]"
+
+  -
+    input:
+      bytes: [ 0xf7, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8dot2", "+ssve-fp8dot4" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z23, z31"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x45, 0x68, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8dot2", "+ssve-fp8dot4" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot z23.s, z13.b, z0.b[1]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x47, 0x7f, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8dot2", "+ssve-fp8dot4" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot z31.s, z31.b, z7.b[3]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x84, 0x60, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8dot2", "+ssve-fp8dot4" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot z0.s, z0.b, z0.b"
+
+  -
+    input:
+      bytes: [ 0xf7, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8dot2", "+ssve-fp8dot4" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z23, z31"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x85, 0x68, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8dot2", "+ssve-fp8dot4" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot z23.s, z13.b, z8.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x87, 0x7f, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8dot2", "+ssve-fp8dot4" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot z31.s, z31.b, z31.b"
diff --git a/tests/MC/AArch64/FP8_SVE2/fmlal.s.yaml b/tests/MC/AArch64/FP8_SVE2/fmlal.s.yaml
new file mode 100644
index 000000000..dd9dadc10
--- /dev/null
+++ b/tests/MC/AArch64/FP8_SVE2/fmlal.s.yaml
@@ -0,0 +1,160 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x50, 0x20, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8fma" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlalb z0.h, z0.b, z0.b[0]"
+
+  -
+    input:
+      bytes: [ 0xf7, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8fma" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z23, z31"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x5d, 0x28, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8fma" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlalb z23.h, z13.b, z0.b[7]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x5f, 0x3f, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8fma" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlalb z31.h, z31.b, z7.b[15]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x88, 0xa0, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8fma" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlalb z0.h, z0.b, z0.b"
+
+  -
+    input:
+      bytes: [ 0xf7, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8fma" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z23, z31"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x89, 0xa8, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8fma" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlalb z23.h, z13.b, z8.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x8b, 0xbf, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8fma" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlalb z31.h, z31.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x50, 0xa0, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8fma" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlalt z0.h, z0.b, z0.b[0]"
+
+  -
+    input:
+      bytes: [ 0xf7, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8fma" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z23, z31"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x5d, 0xa8, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8fma" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlalt z23.h, z13.b, z0.b[7]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x5f, 0xbf, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8fma" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlalt z31.h, z31.b, z7.b[15]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x98, 0xa0, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8fma" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlalt z0.h, z0.b, z0.b"
+
+  -
+    input:
+      bytes: [ 0xf7, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8fma" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z23, z31"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x99, 0xa8, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8fma" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlalt z23.h, z13.b, z8.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x9b, 0xbf, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8fma" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlalt z31.h, z31.b, z31.b"
diff --git a/tests/MC/AArch64/FP8_SVE2/fmlall.s.yaml b/tests/MC/AArch64/FP8_SVE2/fmlall.s.yaml
new file mode 100644
index 000000000..1df1a4227
--- /dev/null
+++ b/tests/MC/AArch64/FP8_SVE2/fmlall.s.yaml
@@ -0,0 +1,320 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x20, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8fma" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlallbb z0.s, z0.b, z0.b[0]"
+
+  -
+    input:
+      bytes: [ 0xf7, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8fma" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z23, z31"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xcd, 0x28, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8fma" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlallbb z23.s, z13.b, z0.b[7]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xcf, 0x3f, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8fma" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlallbb z31.s, z31.b, z7.b[15]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x88, 0x20, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8fma" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlallbb z0.s, z0.b, z0.b"
+
+  -
+    input:
+      bytes: [ 0xf7, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8fma" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z23, z31"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x89, 0x28, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8fma" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlallbb z23.s, z13.b, z8.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x8b, 0x3f, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8fma" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlallbb z31.s, z31.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x60, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8fma" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlallbt z0.s, z0.b, z0.b[0]"
+
+  -
+    input:
+      bytes: [ 0xf7, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8fma" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z23, z31"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xcd, 0x68, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8fma" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlallbt z23.s, z13.b, z0.b[7]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xcf, 0x7f, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8fma" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlallbt z31.s, z31.b, z7.b[15]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x98, 0x20, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8fma" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlallbt z0.s, z0.b, z0.b"
+
+  -
+    input:
+      bytes: [ 0xf7, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8fma" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z23, z31"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x99, 0x28, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8fma" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlallbt z23.s, z13.b, z8.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x9b, 0x3f, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8fma" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlallbt z31.s, z31.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0xa0, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8fma" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlalltb z0.s, z0.b, z0.b[0]"
+
+  -
+    input:
+      bytes: [ 0xf7, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8fma" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z23, z31"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xcd, 0xa8, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8fma" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlalltb z23.s, z13.b, z0.b[7]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xcf, 0xbf, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8fma" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlalltb z31.s, z31.b, z7.b[15]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa8, 0x20, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8fma" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlalltb z0.s, z0.b, z0.b"
+
+  -
+    input:
+      bytes: [ 0xf7, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8fma" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z23, z31"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xa9, 0x28, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8fma" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlalltb z23.s, z13.b, z8.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0xab, 0x3f, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8fma" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlalltb z31.s, z31.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0xe0, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8fma" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlalltt z0.s, z0.b, z0.b[0]"
+
+  -
+    input:
+      bytes: [ 0xf7, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8fma" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z23, z31"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xcd, 0xe8, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8fma" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlalltt z23.s, z13.b, z0.b[7]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xcf, 0xff, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8fma" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlalltt z31.s, z31.b, z7.b[15]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xb8, 0x20, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8fma" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlalltt z0.s, z0.b, z0.b"
+
+  -
+    input:
+      bytes: [ 0xf7, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8fma" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z23, z31"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xb9, 0x28, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8fma" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlalltt z23.s, z13.b, z8.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbb, 0x3f, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssve-fp8fma" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlalltt z31.s, z31.b, z31.b"
diff --git a/tests/MC/AArch64/FP8_SVE2/luti2.s.yaml b/tests/MC/AArch64/FP8_SVE2/luti2.s.yaml
new file mode 100644
index 000000000..69f78b8eb
--- /dev/null
+++ b/tests/MC/AArch64/FP8_SVE2/luti2.s.yaml
@@ -0,0 +1,60 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xb0, 0x20, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+lut" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti2 z0.b, { z0.b }, z0[0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xb1, 0x75, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+lut" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti2 z21.b, { z10.b }, z21[1]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xb3, 0xff, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+lut" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti2 z31.b, { z31.b }, z31[3]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa8, 0x20, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+lut" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti2 z0.h, { z0.h }, z0[0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xb9, 0x75, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+lut" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti2 z21.h, { z10.h }, z21[3]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbb, 0xff, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+lut" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti2 z31.h, { z31.h }, z31[7]"
diff --git a/tests/MC/AArch64/FP8_SVE2/luti4.s.yaml b/tests/MC/AArch64/FP8_SVE2/luti4.s.yaml
new file mode 100644
index 000000000..c7fba9196
--- /dev/null
+++ b/tests/MC/AArch64/FP8_SVE2/luti4.s.yaml
@@ -0,0 +1,80 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xa4, 0x60, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+lut" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti4 z0.b, { z0.b }, z0[0]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xa7, 0xff, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+lut" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti4 z31.b, { z31.b }, z31[1]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xbc, 0x20, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+lut" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti4 z0.h, { z0.h }, z0[0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xbd, 0x75, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+lut" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti4 z21.h, { z10.h }, z21[1]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0xff, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+lut" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti4 z31.h, { z31.h }, z31[3]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xb4, 0x20, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+lut" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti4 z0.h, { z0.h, z1.h }, z0[0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xb5, 0x75, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+lut" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti4 z21.h, { z10.h, z11.h }, z21[1]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xb7, 0xff, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+lut" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti4 z31.h, { z31.h, z0.h }, z31[3]"
diff --git a/tests/MC/AArch64/SME/addha-u32.s.yaml b/tests/MC/AArch64/SME/addha-u32.s.yaml
new file mode 100644
index 000000000..38bb8db8b
--- /dev/null
+++ b/tests/MC/AArch64/SME/addha-u32.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x90, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "addha za0.s, p0/m, p0/m, z0.s"
+
+  -
+    input:
+      bytes: [ 0x41, 0x55, 0x90, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "addha za1.s, p5/m, p2/m, z10.s"
+
+  -
+    input:
+      bytes: [ 0xa3, 0xed, 0x90, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "addha za3.s, p3/m, p7/m, z13.s"
+
+  -
+    input:
+      bytes: [ 0xe3, 0xff, 0x90, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "addha za3.s, p7/m, p7/m, z31.s"
+
+  -
+    input:
+      bytes: [ 0x21, 0x0e, 0x90, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "addha za1.s, p3/m, p0/m, z17.s"
+
+  -
+    input:
+      bytes: [ 0x21, 0x84, 0x90, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "addha za1.s, p1/m, p4/m, z1.s"
+
+  -
+    input:
+      bytes: [ 0x60, 0x56, 0x90, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "addha za0.s, p5/m, p2/m, z19.s"
+
+  -
+    input:
+      bytes: [ 0x80, 0x19, 0x90, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "addha za0.s, p6/m, p0/m, z12.s"
+
+  -
+    input:
+      bytes: [ 0x21, 0xc8, 0x90, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "addha za1.s, p2/m, p6/m, z1.s"
+
+  -
+    input:
+      bytes: [ 0xc1, 0x0a, 0x90, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "addha za1.s, p2/m, p0/m, z22.s"
+
+  -
+    input:
+      bytes: [ 0x22, 0xf5, 0x90, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "addha za2.s, p5/m, p7/m, z9.s"
+
+  -
+    input:
+      bytes: [ 0x83, 0xa9, 0x90, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "addha za3.s, p2/m, p5/m, z12.s"
diff --git a/tests/MC/AArch64/SME/addha-u64.s.yaml b/tests/MC/AArch64/SME/addha-u64.s.yaml
new file mode 100644
index 000000000..f90e1332b
--- /dev/null
+++ b/tests/MC/AArch64/SME/addha-u64.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0xd0, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "addha za0.d, p0/m, p0/m, z0.d"
+
+  -
+    input:
+      bytes: [ 0x45, 0x55, 0xd0, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "addha za5.d, p5/m, p2/m, z10.d"
+
+  -
+    input:
+      bytes: [ 0xa7, 0xed, 0xd0, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "addha za7.d, p3/m, p7/m, z13.d"
+
+  -
+    input:
+      bytes: [ 0xe7, 0xff, 0xd0, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "addha za7.d, p7/m, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0x25, 0x0e, 0xd0, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "addha za5.d, p3/m, p0/m, z17.d"
+
+  -
+    input:
+      bytes: [ 0x21, 0x84, 0xd0, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "addha za1.d, p1/m, p4/m, z1.d"
+
+  -
+    input:
+      bytes: [ 0x60, 0x56, 0xd0, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "addha za0.d, p5/m, p2/m, z19.d"
+
+  -
+    input:
+      bytes: [ 0x80, 0x19, 0xd0, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "addha za0.d, p6/m, p0/m, z12.d"
+
+  -
+    input:
+      bytes: [ 0x21, 0xc8, 0xd0, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "addha za1.d, p2/m, p6/m, z1.d"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x0a, 0xd0, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "addha za5.d, p2/m, p0/m, z22.d"
+
+  -
+    input:
+      bytes: [ 0x22, 0xf5, 0xd0, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "addha za2.d, p5/m, p7/m, z9.d"
+
+  -
+    input:
+      bytes: [ 0x87, 0xa9, 0xd0, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "addha za7.d, p2/m, p5/m, z12.d"
diff --git a/tests/MC/AArch64/SME/addspl.s.yaml b/tests/MC/AArch64/SME/addspl.s.yaml
new file mode 100644
index 000000000..802b02849
--- /dev/null
+++ b/tests/MC/AArch64/SME/addspl.s.yaml
@@ -0,0 +1,40 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x15, 0x58, 0x75, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "addspl x21, x21, #0"
+
+  -
+    input:
+      bytes: [ 0xf7, 0x5f, 0x68, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "addspl x23, x8, #-1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x5b, 0x7f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "addspl sp, sp, #31"
+
+  -
+    input:
+      bytes: [ 0x00, 0x5c, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "addspl x0, x0, #-32"
diff --git a/tests/MC/AArch64/SME/addsvl.s.yaml b/tests/MC/AArch64/SME/addsvl.s.yaml
new file mode 100644
index 000000000..89b8462fe
--- /dev/null
+++ b/tests/MC/AArch64/SME/addsvl.s.yaml
@@ -0,0 +1,40 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x15, 0x58, 0x35, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "addsvl x21, x21, #0"
+
+  -
+    input:
+      bytes: [ 0xf7, 0x5f, 0x28, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "addsvl x23, x8, #-1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x5b, 0x3f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "addsvl sp, sp, #31"
+
+  -
+    input:
+      bytes: [ 0x00, 0x5c, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "addsvl x0, x0, #-32"
diff --git a/tests/MC/AArch64/SME/addva-u32.s.yaml b/tests/MC/AArch64/SME/addva-u32.s.yaml
new file mode 100644
index 000000000..6de617480
--- /dev/null
+++ b/tests/MC/AArch64/SME/addva-u32.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x91, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "addva za0.s, p0/m, p0/m, z0.s"
+
+  -
+    input:
+      bytes: [ 0x41, 0x55, 0x91, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "addva za1.s, p5/m, p2/m, z10.s"
+
+  -
+    input:
+      bytes: [ 0xa3, 0xed, 0x91, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "addva za3.s, p3/m, p7/m, z13.s"
+
+  -
+    input:
+      bytes: [ 0xe3, 0xff, 0x91, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "addva za3.s, p7/m, p7/m, z31.s"
+
+  -
+    input:
+      bytes: [ 0x21, 0x0e, 0x91, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "addva za1.s, p3/m, p0/m, z17.s"
+
+  -
+    input:
+      bytes: [ 0x21, 0x84, 0x91, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "addva za1.s, p1/m, p4/m, z1.s"
+
+  -
+    input:
+      bytes: [ 0x60, 0x56, 0x91, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "addva za0.s, p5/m, p2/m, z19.s"
+
+  -
+    input:
+      bytes: [ 0x80, 0x19, 0x91, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "addva za0.s, p6/m, p0/m, z12.s"
+
+  -
+    input:
+      bytes: [ 0x21, 0xc8, 0x91, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "addva za1.s, p2/m, p6/m, z1.s"
+
+  -
+    input:
+      bytes: [ 0xc1, 0x0a, 0x91, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "addva za1.s, p2/m, p0/m, z22.s"
+
+  -
+    input:
+      bytes: [ 0x22, 0xf5, 0x91, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "addva za2.s, p5/m, p7/m, z9.s"
+
+  -
+    input:
+      bytes: [ 0x83, 0xa9, 0x91, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "addva za3.s, p2/m, p5/m, z12.s"
diff --git a/tests/MC/AArch64/SME/addva-u64.s.yaml b/tests/MC/AArch64/SME/addva-u64.s.yaml
new file mode 100644
index 000000000..25db5ab3e
--- /dev/null
+++ b/tests/MC/AArch64/SME/addva-u64.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0xd1, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "addva za0.d, p0/m, p0/m, z0.d"
+
+  -
+    input:
+      bytes: [ 0x45, 0x55, 0xd1, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "addva za5.d, p5/m, p2/m, z10.d"
+
+  -
+    input:
+      bytes: [ 0xa7, 0xed, 0xd1, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "addva za7.d, p3/m, p7/m, z13.d"
+
+  -
+    input:
+      bytes: [ 0xe7, 0xff, 0xd1, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "addva za7.d, p7/m, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0x25, 0x0e, 0xd1, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "addva za5.d, p3/m, p0/m, z17.d"
+
+  -
+    input:
+      bytes: [ 0x21, 0x84, 0xd1, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "addva za1.d, p1/m, p4/m, z1.d"
+
+  -
+    input:
+      bytes: [ 0x60, 0x56, 0xd1, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "addva za0.d, p5/m, p2/m, z19.d"
+
+  -
+    input:
+      bytes: [ 0x80, 0x19, 0xd1, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "addva za0.d, p6/m, p0/m, z12.d"
+
+  -
+    input:
+      bytes: [ 0x21, 0xc8, 0xd1, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "addva za1.d, p2/m, p6/m, z1.d"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x0a, 0xd1, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "addva za5.d, p2/m, p0/m, z22.d"
+
+  -
+    input:
+      bytes: [ 0x22, 0xf5, 0xd1, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "addva za2.d, p5/m, p7/m, z9.d"
+
+  -
+    input:
+      bytes: [ 0x87, 0xa9, 0xd1, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "addva za7.d, p2/m, p5/m, z12.d"
diff --git a/tests/MC/AArch64/SME/bfmopa.s.yaml b/tests/MC/AArch64/SME/bfmopa.s.yaml
new file mode 100644
index 000000000..c608593db
--- /dev/null
+++ b/tests/MC/AArch64/SME/bfmopa.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x80, 0x81 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmopa za0.s, p0/m, p0/m, z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x41, 0x55, 0x95, 0x81 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmopa za1.s, p5/m, p2/m, z10.h, z21.h"
+
+  -
+    input:
+      bytes: [ 0xa3, 0xed, 0x88, 0x81 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmopa za3.s, p3/m, p7/m, z13.h, z8.h"
+
+  -
+    input:
+      bytes: [ 0xe3, 0xff, 0x9f, 0x81 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmopa za3.s, p7/m, p7/m, z31.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x21, 0x0e, 0x90, 0x81 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmopa za1.s, p3/m, p0/m, z17.h, z16.h"
+
+  -
+    input:
+      bytes: [ 0x21, 0x84, 0x9e, 0x81 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmopa za1.s, p1/m, p4/m, z1.h, z30.h"
+
+  -
+    input:
+      bytes: [ 0x60, 0x56, 0x94, 0x81 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmopa za0.s, p5/m, p2/m, z19.h, z20.h"
+
+  -
+    input:
+      bytes: [ 0x80, 0x19, 0x82, 0x81 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmopa za0.s, p6/m, p0/m, z12.h, z2.h"
+
+  -
+    input:
+      bytes: [ 0x21, 0xc8, 0x9a, 0x81 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmopa za1.s, p2/m, p6/m, z1.h, z26.h"
+
+  -
+    input:
+      bytes: [ 0xc1, 0x0a, 0x9e, 0x81 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmopa za1.s, p2/m, p0/m, z22.h, z30.h"
+
+  -
+    input:
+      bytes: [ 0x22, 0xf5, 0x81, 0x81 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmopa za2.s, p5/m, p7/m, z9.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0x83, 0xa9, 0x8b, 0x81 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmopa za3.s, p2/m, p5/m, z12.h, z11.h"
diff --git a/tests/MC/AArch64/SME/bfmops.s.yaml b/tests/MC/AArch64/SME/bfmops.s.yaml
new file mode 100644
index 000000000..972e298fd
--- /dev/null
+++ b/tests/MC/AArch64/SME/bfmops.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x10, 0x00, 0x80, 0x81 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmops za0.s, p0/m, p0/m, z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x51, 0x55, 0x95, 0x81 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmops za1.s, p5/m, p2/m, z10.h, z21.h"
+
+  -
+    input:
+      bytes: [ 0xb3, 0xed, 0x88, 0x81 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmops za3.s, p3/m, p7/m, z13.h, z8.h"
+
+  -
+    input:
+      bytes: [ 0xf3, 0xff, 0x9f, 0x81 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmops za3.s, p7/m, p7/m, z31.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x31, 0x0e, 0x90, 0x81 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmops za1.s, p3/m, p0/m, z17.h, z16.h"
+
+  -
+    input:
+      bytes: [ 0x31, 0x84, 0x9e, 0x81 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmops za1.s, p1/m, p4/m, z1.h, z30.h"
+
+  -
+    input:
+      bytes: [ 0x70, 0x56, 0x94, 0x81 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmops za0.s, p5/m, p2/m, z19.h, z20.h"
+
+  -
+    input:
+      bytes: [ 0x90, 0x19, 0x82, 0x81 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmops za0.s, p6/m, p0/m, z12.h, z2.h"
+
+  -
+    input:
+      bytes: [ 0x31, 0xc8, 0x9a, 0x81 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmops za1.s, p2/m, p6/m, z1.h, z26.h"
+
+  -
+    input:
+      bytes: [ 0xd1, 0x0a, 0x9e, 0x81 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmops za1.s, p2/m, p0/m, z22.h, z30.h"
+
+  -
+    input:
+      bytes: [ 0x32, 0xf5, 0x81, 0x81 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmops za2.s, p5/m, p7/m, z9.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0x93, 0xa9, 0x8b, 0x81 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmops za3.s, p2/m, p5/m, z12.h, z11.h"
diff --git a/tests/MC/AArch64/SME/fa64-implies-sve2.s.yaml b/tests/MC/AArch64/SME/fa64-implies-sve2.s.yaml
new file mode 100644
index 000000000..90bdc92ee
--- /dev/null
+++ b/tests/MC/AArch64/SME/fa64-implies-sve2.s.yaml
@@ -0,0 +1,10 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x9f, 0x84 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "sme-fa64" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1sh { z0.s }, p0/z, [z1.s]"
diff --git a/tests/MC/AArch64/SME/feature.s.yaml b/tests/MC/AArch64/SME/feature.s.yaml
new file mode 100644
index 000000000..b57e03145
--- /dev/null
+++ b/tests/MC/AArch64/SME/feature.s.yaml
@@ -0,0 +1,60 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x2c, 0x22, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "tbx z0.b, z1.b, z2.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x62, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot z0.s, z1.h, z2.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x2c, 0x22, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "tbx z0.b, z1.b, z2.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x62, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot z0.s, z1.h, z2.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x2c, 0x22, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "tbx z0.b, z1.b, z2.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x62, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot z0.s, z1.h, z2.h"
diff --git a/tests/MC/AArch64/SME/fmopa-fp64.s.yaml b/tests/MC/AArch64/SME/fmopa-fp64.s.yaml
new file mode 100644
index 000000000..534d98679
--- /dev/null
+++ b/tests/MC/AArch64/SME/fmopa-fp64.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0xc0, 0x80 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmopa za0.d, p0/m, p0/m, z0.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0x45, 0x55, 0xd5, 0x80 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmopa za5.d, p5/m, p2/m, z10.d, z21.d"
+
+  -
+    input:
+      bytes: [ 0xa7, 0xed, 0xc8, 0x80 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmopa za7.d, p3/m, p7/m, z13.d, z8.d"
+
+  -
+    input:
+      bytes: [ 0xe7, 0xff, 0xdf, 0x80 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmopa za7.d, p7/m, p7/m, z31.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0x25, 0x0e, 0xd0, 0x80 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmopa za5.d, p3/m, p0/m, z17.d, z16.d"
+
+  -
+    input:
+      bytes: [ 0x21, 0x84, 0xde, 0x80 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmopa za1.d, p1/m, p4/m, z1.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0x60, 0x56, 0xd4, 0x80 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmopa za0.d, p5/m, p2/m, z19.d, z20.d"
+
+  -
+    input:
+      bytes: [ 0x80, 0x19, 0xc2, 0x80 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmopa za0.d, p6/m, p0/m, z12.d, z2.d"
+
+  -
+    input:
+      bytes: [ 0x21, 0xc8, 0xda, 0x80 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmopa za1.d, p2/m, p6/m, z1.d, z26.d"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x0a, 0xde, 0x80 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmopa za5.d, p2/m, p0/m, z22.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0x22, 0xf5, 0xc1, 0x80 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmopa za2.d, p5/m, p7/m, z9.d, z1.d"
+
+  -
+    input:
+      bytes: [ 0x87, 0xa9, 0xcb, 0x80 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmopa za7.d, p2/m, p5/m, z12.d, z11.d"
diff --git a/tests/MC/AArch64/SME/fmopa.s.yaml b/tests/MC/AArch64/SME/fmopa.s.yaml
new file mode 100644
index 000000000..f12e64073
--- /dev/null
+++ b/tests/MC/AArch64/SME/fmopa.s.yaml
@@ -0,0 +1,240 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0xa0, 0x81 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmopa za0.s, p0/m, p0/m, z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x41, 0x55, 0xb5, 0x81 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmopa za1.s, p5/m, p2/m, z10.h, z21.h"
+
+  -
+    input:
+      bytes: [ 0xa3, 0xed, 0xa8, 0x81 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmopa za3.s, p3/m, p7/m, z13.h, z8.h"
+
+  -
+    input:
+      bytes: [ 0xe3, 0xff, 0xbf, 0x81 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmopa za3.s, p7/m, p7/m, z31.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x21, 0x0e, 0xb0, 0x81 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmopa za1.s, p3/m, p0/m, z17.h, z16.h"
+
+  -
+    input:
+      bytes: [ 0x21, 0x84, 0xbe, 0x81 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmopa za1.s, p1/m, p4/m, z1.h, z30.h"
+
+  -
+    input:
+      bytes: [ 0x60, 0x56, 0xb4, 0x81 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmopa za0.s, p5/m, p2/m, z19.h, z20.h"
+
+  -
+    input:
+      bytes: [ 0x80, 0x19, 0xa2, 0x81 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmopa za0.s, p6/m, p0/m, z12.h, z2.h"
+
+  -
+    input:
+      bytes: [ 0x21, 0xc8, 0xba, 0x81 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmopa za1.s, p2/m, p6/m, z1.h, z26.h"
+
+  -
+    input:
+      bytes: [ 0xc1, 0x0a, 0xbe, 0x81 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmopa za1.s, p2/m, p0/m, z22.h, z30.h"
+
+  -
+    input:
+      bytes: [ 0x22, 0xf5, 0xa1, 0x81 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmopa za2.s, p5/m, p7/m, z9.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0x83, 0xa9, 0xab, 0x81 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmopa za3.s, p2/m, p5/m, z12.h, z11.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x80, 0x80 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmopa za0.s, p0/m, p0/m, z0.s, z0.s"
+
+  -
+    input:
+      bytes: [ 0x41, 0x55, 0x95, 0x80 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmopa za1.s, p5/m, p2/m, z10.s, z21.s"
+
+  -
+    input:
+      bytes: [ 0xa3, 0xed, 0x88, 0x80 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmopa za3.s, p3/m, p7/m, z13.s, z8.s"
+
+  -
+    input:
+      bytes: [ 0xe3, 0xff, 0x9f, 0x80 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmopa za3.s, p7/m, p7/m, z31.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x21, 0x0e, 0x90, 0x80 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmopa za1.s, p3/m, p0/m, z17.s, z16.s"
+
+  -
+    input:
+      bytes: [ 0x21, 0x84, 0x9e, 0x80 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmopa za1.s, p1/m, p4/m, z1.s, z30.s"
+
+  -
+    input:
+      bytes: [ 0x60, 0x56, 0x94, 0x80 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmopa za0.s, p5/m, p2/m, z19.s, z20.s"
+
+  -
+    input:
+      bytes: [ 0x80, 0x19, 0x82, 0x80 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmopa za0.s, p6/m, p0/m, z12.s, z2.s"
+
+  -
+    input:
+      bytes: [ 0x21, 0xc8, 0x9a, 0x80 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmopa za1.s, p2/m, p6/m, z1.s, z26.s"
+
+  -
+    input:
+      bytes: [ 0xc1, 0x0a, 0x9e, 0x80 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmopa za1.s, p2/m, p0/m, z22.s, z30.s"
+
+  -
+    input:
+      bytes: [ 0x22, 0xf5, 0x81, 0x80 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmopa za2.s, p5/m, p7/m, z9.s, z1.s"
+
+  -
+    input:
+      bytes: [ 0x83, 0xa9, 0x8b, 0x80 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmopa za3.s, p2/m, p5/m, z12.s, z11.s"
diff --git a/tests/MC/AArch64/SME/fmops-fp64.s.yaml b/tests/MC/AArch64/SME/fmops-fp64.s.yaml
new file mode 100644
index 000000000..2d8918aa1
--- /dev/null
+++ b/tests/MC/AArch64/SME/fmops-fp64.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x10, 0x00, 0xc0, 0x80 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmops za0.d, p0/m, p0/m, z0.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0x55, 0x55, 0xd5, 0x80 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmops za5.d, p5/m, p2/m, z10.d, z21.d"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0xc8, 0x80 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmops za7.d, p3/m, p7/m, z13.d, z8.d"
+
+  -
+    input:
+      bytes: [ 0xf7, 0xff, 0xdf, 0x80 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmops za7.d, p7/m, p7/m, z31.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0x35, 0x0e, 0xd0, 0x80 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmops za5.d, p3/m, p0/m, z17.d, z16.d"
+
+  -
+    input:
+      bytes: [ 0x31, 0x84, 0xde, 0x80 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmops za1.d, p1/m, p4/m, z1.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0x70, 0x56, 0xd4, 0x80 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmops za0.d, p5/m, p2/m, z19.d, z20.d"
+
+  -
+    input:
+      bytes: [ 0x90, 0x19, 0xc2, 0x80 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmops za0.d, p6/m, p0/m, z12.d, z2.d"
+
+  -
+    input:
+      bytes: [ 0x31, 0xc8, 0xda, 0x80 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmops za1.d, p2/m, p6/m, z1.d, z26.d"
+
+  -
+    input:
+      bytes: [ 0xd5, 0x0a, 0xde, 0x80 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmops za5.d, p2/m, p0/m, z22.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0x32, 0xf5, 0xc1, 0x80 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmops za2.d, p5/m, p7/m, z9.d, z1.d"
+
+  -
+    input:
+      bytes: [ 0x97, 0xa9, 0xcb, 0x80 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmops za7.d, p2/m, p5/m, z12.d, z11.d"
diff --git a/tests/MC/AArch64/SME/fmops.s.yaml b/tests/MC/AArch64/SME/fmops.s.yaml
new file mode 100644
index 000000000..e5f3eef75
--- /dev/null
+++ b/tests/MC/AArch64/SME/fmops.s.yaml
@@ -0,0 +1,240 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x10, 0x00, 0xa0, 0x81 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmops za0.s, p0/m, p0/m, z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x51, 0x55, 0xb5, 0x81 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmops za1.s, p5/m, p2/m, z10.h, z21.h"
+
+  -
+    input:
+      bytes: [ 0xb3, 0xed, 0xa8, 0x81 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmops za3.s, p3/m, p7/m, z13.h, z8.h"
+
+  -
+    input:
+      bytes: [ 0xf3, 0xff, 0xbf, 0x81 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmops za3.s, p7/m, p7/m, z31.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x31, 0x0e, 0xb0, 0x81 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmops za1.s, p3/m, p0/m, z17.h, z16.h"
+
+  -
+    input:
+      bytes: [ 0x31, 0x84, 0xbe, 0x81 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmops za1.s, p1/m, p4/m, z1.h, z30.h"
+
+  -
+    input:
+      bytes: [ 0x70, 0x56, 0xb4, 0x81 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmops za0.s, p5/m, p2/m, z19.h, z20.h"
+
+  -
+    input:
+      bytes: [ 0x90, 0x19, 0xa2, 0x81 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmops za0.s, p6/m, p0/m, z12.h, z2.h"
+
+  -
+    input:
+      bytes: [ 0x31, 0xc8, 0xba, 0x81 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmops za1.s, p2/m, p6/m, z1.h, z26.h"
+
+  -
+    input:
+      bytes: [ 0xd1, 0x0a, 0xbe, 0x81 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmops za1.s, p2/m, p0/m, z22.h, z30.h"
+
+  -
+    input:
+      bytes: [ 0x32, 0xf5, 0xa1, 0x81 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmops za2.s, p5/m, p7/m, z9.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0x93, 0xa9, 0xab, 0x81 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmops za3.s, p2/m, p5/m, z12.h, z11.h"
+
+  -
+    input:
+      bytes: [ 0x10, 0x00, 0x80, 0x80 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmops za0.s, p0/m, p0/m, z0.s, z0.s"
+
+  -
+    input:
+      bytes: [ 0x51, 0x55, 0x95, 0x80 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmops za1.s, p5/m, p2/m, z10.s, z21.s"
+
+  -
+    input:
+      bytes: [ 0xb3, 0xed, 0x88, 0x80 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmops za3.s, p3/m, p7/m, z13.s, z8.s"
+
+  -
+    input:
+      bytes: [ 0xf3, 0xff, 0x9f, 0x80 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmops za3.s, p7/m, p7/m, z31.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x31, 0x0e, 0x90, 0x80 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmops za1.s, p3/m, p0/m, z17.s, z16.s"
+
+  -
+    input:
+      bytes: [ 0x31, 0x84, 0x9e, 0x80 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmops za1.s, p1/m, p4/m, z1.s, z30.s"
+
+  -
+    input:
+      bytes: [ 0x70, 0x56, 0x94, 0x80 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmops za0.s, p5/m, p2/m, z19.s, z20.s"
+
+  -
+    input:
+      bytes: [ 0x90, 0x19, 0x82, 0x80 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmops za0.s, p6/m, p0/m, z12.s, z2.s"
+
+  -
+    input:
+      bytes: [ 0x31, 0xc8, 0x9a, 0x80 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmops za1.s, p2/m, p6/m, z1.s, z26.s"
+
+  -
+    input:
+      bytes: [ 0xd1, 0x0a, 0x9e, 0x80 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmops za1.s, p2/m, p0/m, z22.s, z30.s"
+
+  -
+    input:
+      bytes: [ 0x32, 0xf5, 0x81, 0x80 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmops za2.s, p5/m, p7/m, z9.s, z1.s"
+
+  -
+    input:
+      bytes: [ 0x93, 0xa9, 0x8b, 0x80 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmops za3.s, p2/m, p5/m, z12.s, z11.s"
diff --git a/tests/MC/AArch64/SME/ld1b.s.yaml b/tests/MC/AArch64/SME/ld1b.s.yaml
new file mode 100644
index 000000000..bfd7653f7
--- /dev/null
+++ b/tests/MC/AArch64/SME/ld1b.s.yaml
@@ -0,0 +1,500 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x00, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b {za0h.b[w12, 0]}, p0/z, [x0, x0]"
+
+  -
+    input:
+      bytes: [ 0x45, 0x55, 0x15, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b {za0h.b[w14, 5]}, p5/z, [x10, x21]"
+
+  -
+    input:
+      bytes: [ 0xa7, 0x6d, 0x08, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b {za0h.b[w15, 7]}, p3/z, [x13, x8]"
+
+  -
+    input:
+      bytes: [ 0xef, 0x7f, 0x1f, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b {za0h.b[w15, 15]}, p7/z, [sp]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x0e, 0x10, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b {za0h.b[w12, 5]}, p3/z, [x17, x16]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x04, 0x1e, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b {za0h.b[w12, 1]}, p1/z, [x1, x30]"
+
+  -
+    input:
+      bytes: [ 0x68, 0x56, 0x14, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b {za0h.b[w14, 8]}, p5/z, [x19, x20]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x19, 0x02, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b {za0h.b[w12, 0]}, p6/z, [x12, x2]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x48, 0x1a, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b {za0h.b[w14, 1]}, p2/z, [x1, x26]"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x0a, 0x1e, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b {za0h.b[w12, 13]}, p2/z, [x22, x30]"
+
+  -
+    input:
+      bytes: [ 0x22, 0x75, 0x01, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b {za0h.b[w15, 2]}, p5/z, [x9, x1]"
+
+  -
+    input:
+      bytes: [ 0x87, 0x29, 0x0b, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b {za0h.b[w13, 7]}, p2/z, [x12, x11]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x00, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b {za0h.b[w12, 0]}, p0/z, [x0, x0]"
+
+  -
+    input:
+      bytes: [ 0x45, 0x55, 0x15, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b {za0h.b[w14, 5]}, p5/z, [x10, x21]"
+
+  -
+    input:
+      bytes: [ 0xa7, 0x6d, 0x08, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b {za0h.b[w15, 7]}, p3/z, [x13, x8]"
+
+  -
+    input:
+      bytes: [ 0xef, 0x7f, 0x1f, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b {za0h.b[w15, 15]}, p7/z, [sp]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x0e, 0x10, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b {za0h.b[w12, 5]}, p3/z, [x17, x16]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x04, 0x1e, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b {za0h.b[w12, 1]}, p1/z, [x1, x30]"
+
+  -
+    input:
+      bytes: [ 0x68, 0x56, 0x14, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b {za0h.b[w14, 8]}, p5/z, [x19, x20]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x19, 0x02, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b {za0h.b[w12, 0]}, p6/z, [x12, x2]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x48, 0x1a, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b {za0h.b[w14, 1]}, p2/z, [x1, x26]"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x0a, 0x1e, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b {za0h.b[w12, 13]}, p2/z, [x22, x30]"
+
+  -
+    input:
+      bytes: [ 0x22, 0x75, 0x01, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b {za0h.b[w15, 2]}, p5/z, [x9, x1]"
+
+  -
+    input:
+      bytes: [ 0x87, 0x29, 0x0b, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b {za0h.b[w13, 7]}, p2/z, [x12, x11]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x00, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b {za0v.b[w12, 0]}, p0/z, [x0, x0]"
+
+  -
+    input:
+      bytes: [ 0x45, 0xd5, 0x15, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b {za0v.b[w14, 5]}, p5/z, [x10, x21]"
+
+  -
+    input:
+      bytes: [ 0xa7, 0xed, 0x08, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b {za0v.b[w15, 7]}, p3/z, [x13, x8]"
+
+  -
+    input:
+      bytes: [ 0xef, 0xff, 0x1f, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b {za0v.b[w15, 15]}, p7/z, [sp]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x8e, 0x10, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b {za0v.b[w12, 5]}, p3/z, [x17, x16]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x84, 0x1e, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b {za0v.b[w12, 1]}, p1/z, [x1, x30]"
+
+  -
+    input:
+      bytes: [ 0x68, 0xd6, 0x14, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b {za0v.b[w14, 8]}, p5/z, [x19, x20]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x99, 0x02, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b {za0v.b[w12, 0]}, p6/z, [x12, x2]"
+
+  -
+    input:
+      bytes: [ 0x21, 0xc8, 0x1a, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b {za0v.b[w14, 1]}, p2/z, [x1, x26]"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x8a, 0x1e, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b {za0v.b[w12, 13]}, p2/z, [x22, x30]"
+
+  -
+    input:
+      bytes: [ 0x22, 0xf5, 0x01, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b {za0v.b[w15, 2]}, p5/z, [x9, x1]"
+
+  -
+    input:
+      bytes: [ 0x87, 0xa9, 0x0b, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b {za0v.b[w13, 7]}, p2/z, [x12, x11]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x00, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b {za0v.b[w12, 0]}, p0/z, [x0, x0]"
+
+  -
+    input:
+      bytes: [ 0x45, 0xd5, 0x15, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b {za0v.b[w14, 5]}, p5/z, [x10, x21]"
+
+  -
+    input:
+      bytes: [ 0xa7, 0xed, 0x08, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b {za0v.b[w15, 7]}, p3/z, [x13, x8]"
+
+  -
+    input:
+      bytes: [ 0xef, 0xff, 0x1f, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b {za0v.b[w15, 15]}, p7/z, [sp]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x8e, 0x10, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b {za0v.b[w12, 5]}, p3/z, [x17, x16]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x84, 0x1e, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b {za0v.b[w12, 1]}, p1/z, [x1, x30]"
+
+  -
+    input:
+      bytes: [ 0x68, 0xd6, 0x14, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b {za0v.b[w14, 8]}, p5/z, [x19, x20]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x99, 0x02, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b {za0v.b[w12, 0]}, p6/z, [x12, x2]"
+
+  -
+    input:
+      bytes: [ 0x21, 0xc8, 0x1a, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b {za0v.b[w14, 1]}, p2/z, [x1, x26]"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x8a, 0x1e, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b {za0v.b[w12, 13]}, p2/z, [x22, x30]"
+
+  -
+    input:
+      bytes: [ 0x22, 0xf5, 0x01, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b {za0v.b[w15, 2]}, p5/z, [x9, x1]"
+
+  -
+    input:
+      bytes: [ 0x87, 0xa9, 0x0b, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b {za0v.b[w13, 7]}, p2/z, [x12, x11]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x00, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b {za0h.b[w12, 0]}, p0/z, [x0, x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x00, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b {za0v.b[w12, 0]}, p0/z, [x0, x0]"
diff --git a/tests/MC/AArch64/SME/ld1d.s.yaml b/tests/MC/AArch64/SME/ld1d.s.yaml
new file mode 100644
index 000000000..1f50c896b
--- /dev/null
+++ b/tests/MC/AArch64/SME/ld1d.s.yaml
@@ -0,0 +1,480 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0xc0, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d {za0h.d[w12, 0]}, p0/z, [x0, x0, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x45, 0x55, 0xd5, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d {za2h.d[w14, 1]}, p5/z, [x10, x21, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0xa7, 0x6d, 0xc8, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d {za3h.d[w15, 1]}, p3/z, [x13, x8, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0xef, 0x7f, 0xdf, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d {za7h.d[w15, 1]}, p7/z, [sp]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x0e, 0xd0, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d {za2h.d[w12, 1]}, p3/z, [x17, x16, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x04, 0xde, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d {za0h.d[w12, 1]}, p1/z, [x1, x30, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x68, 0x56, 0xd4, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d {za4h.d[w14, 0]}, p5/z, [x19, x20, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x19, 0xc2, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d {za0h.d[w12, 0]}, p6/z, [x12, x2, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x48, 0xda, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d {za0h.d[w14, 1]}, p2/z, [x1, x26, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x0a, 0xde, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d {za6h.d[w12, 1]}, p2/z, [x22, x30, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x22, 0x75, 0xc1, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d {za1h.d[w15, 0]}, p5/z, [x9, x1, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x87, 0x29, 0xcb, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d {za3h.d[w13, 1]}, p2/z, [x12, x11, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0xc0, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d {za0h.d[w12, 0]}, p0/z, [x0, x0, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x45, 0x55, 0xd5, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d {za2h.d[w14, 1]}, p5/z, [x10, x21, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0xa7, 0x6d, 0xc8, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d {za3h.d[w15, 1]}, p3/z, [x13, x8, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0xef, 0x7f, 0xdf, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d {za7h.d[w15, 1]}, p7/z, [sp]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x0e, 0xd0, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d {za2h.d[w12, 1]}, p3/z, [x17, x16, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x04, 0xde, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d {za0h.d[w12, 1]}, p1/z, [x1, x30, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x68, 0x56, 0xd4, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d {za4h.d[w14, 0]}, p5/z, [x19, x20, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x19, 0xc2, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d {za0h.d[w12, 0]}, p6/z, [x12, x2, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x48, 0xda, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d {za0h.d[w14, 1]}, p2/z, [x1, x26, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x0a, 0xde, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d {za6h.d[w12, 1]}, p2/z, [x22, x30, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x22, 0x75, 0xc1, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d {za1h.d[w15, 0]}, p5/z, [x9, x1, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x87, 0x29, 0xcb, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d {za3h.d[w13, 1]}, p2/z, [x12, x11, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xc0, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d {za0v.d[w12, 0]}, p0/z, [x0, x0, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x45, 0xd5, 0xd5, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d {za2v.d[w14, 1]}, p5/z, [x10, x21, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0xa7, 0xed, 0xc8, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d {za3v.d[w15, 1]}, p3/z, [x13, x8, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0xef, 0xff, 0xdf, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d {za7v.d[w15, 1]}, p7/z, [sp]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x8e, 0xd0, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d {za2v.d[w12, 1]}, p3/z, [x17, x16, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x84, 0xde, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d {za0v.d[w12, 1]}, p1/z, [x1, x30, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x68, 0xd6, 0xd4, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d {za4v.d[w14, 0]}, p5/z, [x19, x20, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x99, 0xc2, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d {za0v.d[w12, 0]}, p6/z, [x12, x2, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x21, 0xc8, 0xda, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d {za0v.d[w14, 1]}, p2/z, [x1, x26, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x8a, 0xde, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d {za6v.d[w12, 1]}, p2/z, [x22, x30, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x22, 0xf5, 0xc1, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d {za1v.d[w15, 0]}, p5/z, [x9, x1, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x87, 0xa9, 0xcb, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d {za3v.d[w13, 1]}, p2/z, [x12, x11, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xc0, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d {za0v.d[w12, 0]}, p0/z, [x0, x0, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x45, 0xd5, 0xd5, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d {za2v.d[w14, 1]}, p5/z, [x10, x21, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0xa7, 0xed, 0xc8, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d {za3v.d[w15, 1]}, p3/z, [x13, x8, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0xef, 0xff, 0xdf, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d {za7v.d[w15, 1]}, p7/z, [sp]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x8e, 0xd0, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d {za2v.d[w12, 1]}, p3/z, [x17, x16, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x84, 0xde, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d {za0v.d[w12, 1]}, p1/z, [x1, x30, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x68, 0xd6, 0xd4, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d {za4v.d[w14, 0]}, p5/z, [x19, x20, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x99, 0xc2, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d {za0v.d[w12, 0]}, p6/z, [x12, x2, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x21, 0xc8, 0xda, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d {za0v.d[w14, 1]}, p2/z, [x1, x26, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x8a, 0xde, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d {za6v.d[w12, 1]}, p2/z, [x22, x30, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x22, 0xf5, 0xc1, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d {za1v.d[w15, 0]}, p5/z, [x9, x1, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x87, 0xa9, 0xcb, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d {za3v.d[w13, 1]}, p2/z, [x12, x11, lsl #3]"
diff --git a/tests/MC/AArch64/SME/ld1h.s.yaml b/tests/MC/AArch64/SME/ld1h.s.yaml
new file mode 100644
index 000000000..5b24eeed8
--- /dev/null
+++ b/tests/MC/AArch64/SME/ld1h.s.yaml
@@ -0,0 +1,480 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x40, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h {za0h.h[w12, 0]}, p0/z, [x0, x0, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x45, 0x55, 0x55, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h {za0h.h[w14, 5]}, p5/z, [x10, x21, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0xa7, 0x6d, 0x48, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h {za0h.h[w15, 7]}, p3/z, [x13, x8, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0xef, 0x7f, 0x5f, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h {za1h.h[w15, 7]}, p7/z, [sp]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x0e, 0x50, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h {za0h.h[w12, 5]}, p3/z, [x17, x16, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x04, 0x5e, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h {za0h.h[w12, 1]}, p1/z, [x1, x30, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x68, 0x56, 0x54, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h {za1h.h[w14, 0]}, p5/z, [x19, x20, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x19, 0x42, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h {za0h.h[w12, 0]}, p6/z, [x12, x2, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x48, 0x5a, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h {za0h.h[w14, 1]}, p2/z, [x1, x26, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x0a, 0x5e, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h {za1h.h[w12, 5]}, p2/z, [x22, x30, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x22, 0x75, 0x41, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h {za0h.h[w15, 2]}, p5/z, [x9, x1, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x87, 0x29, 0x4b, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h {za0h.h[w13, 7]}, p2/z, [x12, x11, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x40, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h {za0h.h[w12, 0]}, p0/z, [x0, x0, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x45, 0x55, 0x55, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h {za0h.h[w14, 5]}, p5/z, [x10, x21, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0xa7, 0x6d, 0x48, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h {za0h.h[w15, 7]}, p3/z, [x13, x8, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0xef, 0x7f, 0x5f, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h {za1h.h[w15, 7]}, p7/z, [sp]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x0e, 0x50, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h {za0h.h[w12, 5]}, p3/z, [x17, x16, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x04, 0x5e, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h {za0h.h[w12, 1]}, p1/z, [x1, x30, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x68, 0x56, 0x54, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h {za1h.h[w14, 0]}, p5/z, [x19, x20, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x19, 0x42, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h {za0h.h[w12, 0]}, p6/z, [x12, x2, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x48, 0x5a, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h {za0h.h[w14, 1]}, p2/z, [x1, x26, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x0a, 0x5e, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h {za1h.h[w12, 5]}, p2/z, [x22, x30, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x22, 0x75, 0x41, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h {za0h.h[w15, 2]}, p5/z, [x9, x1, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x87, 0x29, 0x4b, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h {za0h.h[w13, 7]}, p2/z, [x12, x11, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x40, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h {za0v.h[w12, 0]}, p0/z, [x0, x0, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x45, 0xd5, 0x55, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h {za0v.h[w14, 5]}, p5/z, [x10, x21, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0xa7, 0xed, 0x48, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h {za0v.h[w15, 7]}, p3/z, [x13, x8, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0xef, 0xff, 0x5f, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h {za1v.h[w15, 7]}, p7/z, [sp]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x8e, 0x50, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h {za0v.h[w12, 5]}, p3/z, [x17, x16, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x84, 0x5e, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h {za0v.h[w12, 1]}, p1/z, [x1, x30, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x68, 0xd6, 0x54, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h {za1v.h[w14, 0]}, p5/z, [x19, x20, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x99, 0x42, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h {za0v.h[w12, 0]}, p6/z, [x12, x2, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x21, 0xc8, 0x5a, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h {za0v.h[w14, 1]}, p2/z, [x1, x26, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x8a, 0x5e, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h {za1v.h[w12, 5]}, p2/z, [x22, x30, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x22, 0xf5, 0x41, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h {za0v.h[w15, 2]}, p5/z, [x9, x1, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x87, 0xa9, 0x4b, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h {za0v.h[w13, 7]}, p2/z, [x12, x11, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x40, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h {za0v.h[w12, 0]}, p0/z, [x0, x0, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x45, 0xd5, 0x55, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h {za0v.h[w14, 5]}, p5/z, [x10, x21, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0xa7, 0xed, 0x48, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h {za0v.h[w15, 7]}, p3/z, [x13, x8, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0xef, 0xff, 0x5f, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h {za1v.h[w15, 7]}, p7/z, [sp]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x8e, 0x50, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h {za0v.h[w12, 5]}, p3/z, [x17, x16, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x84, 0x5e, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h {za0v.h[w12, 1]}, p1/z, [x1, x30, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x68, 0xd6, 0x54, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h {za1v.h[w14, 0]}, p5/z, [x19, x20, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x99, 0x42, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h {za0v.h[w12, 0]}, p6/z, [x12, x2, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x21, 0xc8, 0x5a, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h {za0v.h[w14, 1]}, p2/z, [x1, x26, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x8a, 0x5e, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h {za1v.h[w12, 5]}, p2/z, [x22, x30, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x22, 0xf5, 0x41, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h {za0v.h[w15, 2]}, p5/z, [x9, x1, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x87, 0xa9, 0x4b, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h {za0v.h[w13, 7]}, p2/z, [x12, x11, lsl #1]"
diff --git a/tests/MC/AArch64/SME/ld1q.s.yaml b/tests/MC/AArch64/SME/ld1q.s.yaml
new file mode 100644
index 000000000..addbe4279
--- /dev/null
+++ b/tests/MC/AArch64/SME/ld1q.s.yaml
@@ -0,0 +1,480 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0xc0, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1q {za0h.q[w12, 0]}, p0/z, [x0, x0, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0x45, 0x55, 0xd5, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1q {za5h.q[w14, 0]}, p5/z, [x10, x21, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0xa7, 0x6d, 0xc8, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1q {za7h.q[w15, 0]}, p3/z, [x13, x8, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0xef, 0x7f, 0xdf, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1q {za15h.q[w15, 0]}, p7/z, [sp]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x0e, 0xd0, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1q {za5h.q[w12, 0]}, p3/z, [x17, x16, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x04, 0xde, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1q {za1h.q[w12, 0]}, p1/z, [x1, x30, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0x68, 0x56, 0xd4, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1q {za8h.q[w14, 0]}, p5/z, [x19, x20, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x19, 0xc2, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1q {za0h.q[w12, 0]}, p6/z, [x12, x2, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x48, 0xda, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1q {za1h.q[w14, 0]}, p2/z, [x1, x26, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x0a, 0xde, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1q {za13h.q[w12, 0]}, p2/z, [x22, x30, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0x22, 0x75, 0xc1, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1q {za2h.q[w15, 0]}, p5/z, [x9, x1, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0x87, 0x29, 0xcb, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1q {za7h.q[w13, 0]}, p2/z, [x12, x11, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0xc0, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1q {za0h.q[w12, 0]}, p0/z, [x0, x0, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0x45, 0x55, 0xd5, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1q {za5h.q[w14, 0]}, p5/z, [x10, x21, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0xa7, 0x6d, 0xc8, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1q {za7h.q[w15, 0]}, p3/z, [x13, x8, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0xef, 0x7f, 0xdf, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1q {za15h.q[w15, 0]}, p7/z, [sp]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x0e, 0xd0, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1q {za5h.q[w12, 0]}, p3/z, [x17, x16, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x04, 0xde, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1q {za1h.q[w12, 0]}, p1/z, [x1, x30, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0x68, 0x56, 0xd4, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1q {za8h.q[w14, 0]}, p5/z, [x19, x20, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x19, 0xc2, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1q {za0h.q[w12, 0]}, p6/z, [x12, x2, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x48, 0xda, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1q {za1h.q[w14, 0]}, p2/z, [x1, x26, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x0a, 0xde, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1q {za13h.q[w12, 0]}, p2/z, [x22, x30, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0x22, 0x75, 0xc1, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1q {za2h.q[w15, 0]}, p5/z, [x9, x1, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0x87, 0x29, 0xcb, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1q {za7h.q[w13, 0]}, p2/z, [x12, x11, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xc0, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1q {za0v.q[w12, 0]}, p0/z, [x0, x0, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0x45, 0xd5, 0xd5, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1q {za5v.q[w14, 0]}, p5/z, [x10, x21, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0xa7, 0xed, 0xc8, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1q {za7v.q[w15, 0]}, p3/z, [x13, x8, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0xef, 0xff, 0xdf, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1q {za15v.q[w15, 0]}, p7/z, [sp]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x8e, 0xd0, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1q {za5v.q[w12, 0]}, p3/z, [x17, x16, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x84, 0xde, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1q {za1v.q[w12, 0]}, p1/z, [x1, x30, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0x68, 0xd6, 0xd4, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1q {za8v.q[w14, 0]}, p5/z, [x19, x20, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x99, 0xc2, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1q {za0v.q[w12, 0]}, p6/z, [x12, x2, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0x21, 0xc8, 0xda, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1q {za1v.q[w14, 0]}, p2/z, [x1, x26, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x8a, 0xde, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1q {za13v.q[w12, 0]}, p2/z, [x22, x30, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0x22, 0xf5, 0xc1, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1q {za2v.q[w15, 0]}, p5/z, [x9, x1, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0x87, 0xa9, 0xcb, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1q {za7v.q[w13, 0]}, p2/z, [x12, x11, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xc0, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1q {za0v.q[w12, 0]}, p0/z, [x0, x0, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0x45, 0xd5, 0xd5, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1q {za5v.q[w14, 0]}, p5/z, [x10, x21, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0xa7, 0xed, 0xc8, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1q {za7v.q[w15, 0]}, p3/z, [x13, x8, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0xef, 0xff, 0xdf, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1q {za15v.q[w15, 0]}, p7/z, [sp]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x8e, 0xd0, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1q {za5v.q[w12, 0]}, p3/z, [x17, x16, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x84, 0xde, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1q {za1v.q[w12, 0]}, p1/z, [x1, x30, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0x68, 0xd6, 0xd4, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1q {za8v.q[w14, 0]}, p5/z, [x19, x20, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x99, 0xc2, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1q {za0v.q[w12, 0]}, p6/z, [x12, x2, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0x21, 0xc8, 0xda, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1q {za1v.q[w14, 0]}, p2/z, [x1, x26, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x8a, 0xde, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1q {za13v.q[w12, 0]}, p2/z, [x22, x30, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0x22, 0xf5, 0xc1, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1q {za2v.q[w15, 0]}, p5/z, [x9, x1, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0x87, 0xa9, 0xcb, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1q {za7v.q[w13, 0]}, p2/z, [x12, x11, lsl #4]"
diff --git a/tests/MC/AArch64/SME/ld1w.s.yaml b/tests/MC/AArch64/SME/ld1w.s.yaml
new file mode 100644
index 000000000..02aaa0755
--- /dev/null
+++ b/tests/MC/AArch64/SME/ld1w.s.yaml
@@ -0,0 +1,480 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x80, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w {za0h.s[w12, 0]}, p0/z, [x0, x0, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x45, 0x55, 0x95, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w {za1h.s[w14, 1]}, p5/z, [x10, x21, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0xa7, 0x6d, 0x88, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w {za1h.s[w15, 3]}, p3/z, [x13, x8, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0xef, 0x7f, 0x9f, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w {za3h.s[w15, 3]}, p7/z, [sp]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x0e, 0x90, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w {za1h.s[w12, 1]}, p3/z, [x17, x16, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x04, 0x9e, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w {za0h.s[w12, 1]}, p1/z, [x1, x30, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x68, 0x56, 0x94, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w {za2h.s[w14, 0]}, p5/z, [x19, x20, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x19, 0x82, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w {za0h.s[w12, 0]}, p6/z, [x12, x2, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x48, 0x9a, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w {za0h.s[w14, 1]}, p2/z, [x1, x26, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x0a, 0x9e, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w {za3h.s[w12, 1]}, p2/z, [x22, x30, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x22, 0x75, 0x81, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w {za0h.s[w15, 2]}, p5/z, [x9, x1, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x87, 0x29, 0x8b, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w {za1h.s[w13, 3]}, p2/z, [x12, x11, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x80, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w {za0h.s[w12, 0]}, p0/z, [x0, x0, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x45, 0x55, 0x95, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w {za1h.s[w14, 1]}, p5/z, [x10, x21, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0xa7, 0x6d, 0x88, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w {za1h.s[w15, 3]}, p3/z, [x13, x8, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0xef, 0x7f, 0x9f, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w {za3h.s[w15, 3]}, p7/z, [sp]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x0e, 0x90, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w {za1h.s[w12, 1]}, p3/z, [x17, x16, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x04, 0x9e, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w {za0h.s[w12, 1]}, p1/z, [x1, x30, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x68, 0x56, 0x94, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w {za2h.s[w14, 0]}, p5/z, [x19, x20, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x19, 0x82, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w {za0h.s[w12, 0]}, p6/z, [x12, x2, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x48, 0x9a, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w {za0h.s[w14, 1]}, p2/z, [x1, x26, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x0a, 0x9e, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w {za3h.s[w12, 1]}, p2/z, [x22, x30, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x22, 0x75, 0x81, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w {za0h.s[w15, 2]}, p5/z, [x9, x1, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x87, 0x29, 0x8b, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w {za1h.s[w13, 3]}, p2/z, [x12, x11, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x80, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w {za0v.s[w12, 0]}, p0/z, [x0, x0, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x45, 0xd5, 0x95, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w {za1v.s[w14, 1]}, p5/z, [x10, x21, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0xa7, 0xed, 0x88, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w {za1v.s[w15, 3]}, p3/z, [x13, x8, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0xef, 0xff, 0x9f, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w {za3v.s[w15, 3]}, p7/z, [sp]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x8e, 0x90, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w {za1v.s[w12, 1]}, p3/z, [x17, x16, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x84, 0x9e, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w {za0v.s[w12, 1]}, p1/z, [x1, x30, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x68, 0xd6, 0x94, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w {za2v.s[w14, 0]}, p5/z, [x19, x20, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x99, 0x82, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w {za0v.s[w12, 0]}, p6/z, [x12, x2, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x21, 0xc8, 0x9a, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w {za0v.s[w14, 1]}, p2/z, [x1, x26, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x8a, 0x9e, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w {za3v.s[w12, 1]}, p2/z, [x22, x30, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x22, 0xf5, 0x81, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w {za0v.s[w15, 2]}, p5/z, [x9, x1, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x87, 0xa9, 0x8b, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w {za1v.s[w13, 3]}, p2/z, [x12, x11, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x80, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w {za0v.s[w12, 0]}, p0/z, [x0, x0, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x45, 0xd5, 0x95, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w {za1v.s[w14, 1]}, p5/z, [x10, x21, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0xa7, 0xed, 0x88, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w {za1v.s[w15, 3]}, p3/z, [x13, x8, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0xef, 0xff, 0x9f, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w {za3v.s[w15, 3]}, p7/z, [sp]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x8e, 0x90, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w {za1v.s[w12, 1]}, p3/z, [x17, x16, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x84, 0x9e, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w {za0v.s[w12, 1]}, p1/z, [x1, x30, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x68, 0xd6, 0x94, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w {za2v.s[w14, 0]}, p5/z, [x19, x20, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x99, 0x82, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w {za0v.s[w12, 0]}, p6/z, [x12, x2, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x21, 0xc8, 0x9a, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w {za0v.s[w14, 1]}, p2/z, [x1, x26, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x8a, 0x9e, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w {za3v.s[w12, 1]}, p2/z, [x22, x30, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x22, 0xf5, 0x81, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w {za0v.s[w15, 2]}, p5/z, [x9, x1, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x87, 0xa9, 0x8b, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w {za1v.s[w13, 3]}, p2/z, [x12, x11, lsl #2]"
diff --git a/tests/MC/AArch64/SME/ldr.s.yaml b/tests/MC/AArch64/SME/ldr.s.yaml
new file mode 100644
index 000000000..1122e7ccf
--- /dev/null
+++ b/tests/MC/AArch64/SME/ldr.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x00, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr za[w12, 0], [x0]"
+
+  -
+    input:
+      bytes: [ 0x45, 0x41, 0x00, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr za[w14, 5], [x10, #5, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xa7, 0x61, 0x00, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr za[w15, 7], [x13, #7, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xef, 0x63, 0x00, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr za[w15, 15], [sp, #15, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x02, 0x00, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr za[w12, 5], [x17, #5, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x00, 0x00, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr za[w12, 1], [x1, #1, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x68, 0x42, 0x00, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr za[w14, 8], [x19, #8, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x01, 0x00, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr za[w12, 0], [x12]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x40, 0x00, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr za[w14, 1], [x1, #1, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x02, 0x00, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr za[w12, 13], [x22, #13, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x22, 0x61, 0x00, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr za[w15, 2], [x9, #2, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x87, 0x21, 0x00, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr za[w13, 7], [x12, #7, mul vl]"
diff --git a/tests/MC/AArch64/SME/mova.s.yaml b/tests/MC/AArch64/SME/mova.s.yaml
new file mode 100644
index 000000000..628c83c2c
--- /dev/null
+++ b/tests/MC/AArch64/SME/mova.s.yaml
@@ -0,0 +1,4800 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x02, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.b, p0/m, za0h.b[w12, 0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x55, 0x02, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.b, p5/m, za0h.b[w14, 10]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x6d, 0x02, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z23.b, p3/m, za0h.b[w15, 13]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x7d, 0x02, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z31.b, p7/m, za0h.b[w15, 15]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x0c, 0x02, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z5.b, p3/m, za0h.b[w12, 1]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x04, 0x02, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z1.b, p1/m, za0h.b[w12, 1]"
+
+  -
+    input:
+      bytes: [ 0x78, 0x54, 0x02, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z24.b, p5/m, za0h.b[w14, 3]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x19, 0x02, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.b, p6/m, za0h.b[w12, 12]"
+
+  -
+    input:
+      bytes: [ 0x31, 0x48, 0x02, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z17.b, p2/m, za0h.b[w14, 1]"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x08, 0x02, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z29.b, p2/m, za0h.b[w12, 6]"
+
+  -
+    input:
+      bytes: [ 0x22, 0x75, 0x02, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z2.b, p5/m, za0h.b[w15, 9]"
+
+  -
+    input:
+      bytes: [ 0x87, 0x29, 0x02, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z7.b, p2/m, za0h.b[w13, 12]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x02, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.b, p0/m, za0h.b[w12, 0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x55, 0x02, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.b, p5/m, za0h.b[w14, 10]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x6d, 0x02, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z23.b, p3/m, za0h.b[w15, 13]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x7d, 0x02, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z31.b, p7/m, za0h.b[w15, 15]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x0c, 0x02, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z5.b, p3/m, za0h.b[w12, 1]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x04, 0x02, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z1.b, p1/m, za0h.b[w12, 1]"
+
+  -
+    input:
+      bytes: [ 0x78, 0x54, 0x02, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z24.b, p5/m, za0h.b[w14, 3]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x19, 0x02, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.b, p6/m, za0h.b[w12, 12]"
+
+  -
+    input:
+      bytes: [ 0x31, 0x48, 0x02, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z17.b, p2/m, za0h.b[w14, 1]"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x08, 0x02, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z29.b, p2/m, za0h.b[w12, 6]"
+
+  -
+    input:
+      bytes: [ 0x22, 0x75, 0x02, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z2.b, p5/m, za0h.b[w15, 9]"
+
+  -
+    input:
+      bytes: [ 0x87, 0x29, 0x02, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z7.b, p2/m, za0h.b[w13, 12]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x02, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.b, p0/m, za0v.b[w12, 0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xd5, 0x02, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.b, p5/m, za0v.b[w14, 10]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0x02, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z23.b, p3/m, za0v.b[w15, 13]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xfd, 0x02, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z31.b, p7/m, za0v.b[w15, 15]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x8c, 0x02, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z5.b, p3/m, za0v.b[w12, 1]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x84, 0x02, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z1.b, p1/m, za0v.b[w12, 1]"
+
+  -
+    input:
+      bytes: [ 0x78, 0xd4, 0x02, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z24.b, p5/m, za0v.b[w14, 3]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x99, 0x02, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.b, p6/m, za0v.b[w12, 12]"
+
+  -
+    input:
+      bytes: [ 0x31, 0xc8, 0x02, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z17.b, p2/m, za0v.b[w14, 1]"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x88, 0x02, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z29.b, p2/m, za0v.b[w12, 6]"
+
+  -
+    input:
+      bytes: [ 0x22, 0xf5, 0x02, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z2.b, p5/m, za0v.b[w15, 9]"
+
+  -
+    input:
+      bytes: [ 0x87, 0xa9, 0x02, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z7.b, p2/m, za0v.b[w13, 12]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x02, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.b, p0/m, za0v.b[w12, 0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xd5, 0x02, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.b, p5/m, za0v.b[w14, 10]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0x02, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z23.b, p3/m, za0v.b[w15, 13]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xfd, 0x02, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z31.b, p7/m, za0v.b[w15, 15]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x8c, 0x02, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z5.b, p3/m, za0v.b[w12, 1]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x84, 0x02, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z1.b, p1/m, za0v.b[w12, 1]"
+
+  -
+    input:
+      bytes: [ 0x78, 0xd4, 0x02, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z24.b, p5/m, za0v.b[w14, 3]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x99, 0x02, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.b, p6/m, za0v.b[w12, 12]"
+
+  -
+    input:
+      bytes: [ 0x31, 0xc8, 0x02, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z17.b, p2/m, za0v.b[w14, 1]"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x88, 0x02, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z29.b, p2/m, za0v.b[w12, 6]"
+
+  -
+    input:
+      bytes: [ 0x22, 0xf5, 0x02, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z2.b, p5/m, za0v.b[w15, 9]"
+
+  -
+    input:
+      bytes: [ 0x87, 0xa9, 0x02, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z7.b, p2/m, za0v.b[w13, 12]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x42, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.h, p0/m, za0h.h[w12, 0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x55, 0x42, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.h, p5/m, za1h.h[w14, 2]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x6d, 0x42, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z23.h, p3/m, za1h.h[w15, 5]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x7d, 0x42, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z31.h, p7/m, za1h.h[w15, 7]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x0c, 0x42, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z5.h, p3/m, za0h.h[w12, 1]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x04, 0x42, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z1.h, p1/m, za0h.h[w12, 1]"
+
+  -
+    input:
+      bytes: [ 0x78, 0x54, 0x42, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z24.h, p5/m, za0h.h[w14, 3]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x19, 0x42, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.h, p6/m, za1h.h[w12, 4]"
+
+  -
+    input:
+      bytes: [ 0x31, 0x48, 0x42, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z17.h, p2/m, za0h.h[w14, 1]"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x08, 0x42, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z29.h, p2/m, za0h.h[w12, 6]"
+
+  -
+    input:
+      bytes: [ 0x22, 0x75, 0x42, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z2.h, p5/m, za1h.h[w15, 1]"
+
+  -
+    input:
+      bytes: [ 0x87, 0x29, 0x42, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z7.h, p2/m, za1h.h[w13, 4]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x42, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.h, p0/m, za0h.h[w12, 0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x55, 0x42, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.h, p5/m, za1h.h[w14, 2]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x6d, 0x42, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z23.h, p3/m, za1h.h[w15, 5]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x7d, 0x42, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z31.h, p7/m, za1h.h[w15, 7]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x0c, 0x42, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z5.h, p3/m, za0h.h[w12, 1]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x04, 0x42, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z1.h, p1/m, za0h.h[w12, 1]"
+
+  -
+    input:
+      bytes: [ 0x78, 0x54, 0x42, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z24.h, p5/m, za0h.h[w14, 3]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x19, 0x42, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.h, p6/m, za1h.h[w12, 4]"
+
+  -
+    input:
+      bytes: [ 0x31, 0x48, 0x42, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z17.h, p2/m, za0h.h[w14, 1]"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x08, 0x42, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z29.h, p2/m, za0h.h[w12, 6]"
+
+  -
+    input:
+      bytes: [ 0x22, 0x75, 0x42, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z2.h, p5/m, za1h.h[w15, 1]"
+
+  -
+    input:
+      bytes: [ 0x87, 0x29, 0x42, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z7.h, p2/m, za1h.h[w13, 4]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x42, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.h, p0/m, za0v.h[w12, 0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xd5, 0x42, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.h, p5/m, za1v.h[w14, 2]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0x42, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z23.h, p3/m, za1v.h[w15, 5]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xfd, 0x42, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z31.h, p7/m, za1v.h[w15, 7]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x8c, 0x42, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z5.h, p3/m, za0v.h[w12, 1]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x84, 0x42, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z1.h, p1/m, za0v.h[w12, 1]"
+
+  -
+    input:
+      bytes: [ 0x78, 0xd4, 0x42, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z24.h, p5/m, za0v.h[w14, 3]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x99, 0x42, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.h, p6/m, za1v.h[w12, 4]"
+
+  -
+    input:
+      bytes: [ 0x31, 0xc8, 0x42, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z17.h, p2/m, za0v.h[w14, 1]"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x88, 0x42, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z29.h, p2/m, za0v.h[w12, 6]"
+
+  -
+    input:
+      bytes: [ 0x22, 0xf5, 0x42, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z2.h, p5/m, za1v.h[w15, 1]"
+
+  -
+    input:
+      bytes: [ 0x87, 0xa9, 0x42, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z7.h, p2/m, za1v.h[w13, 4]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x42, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.h, p0/m, za0v.h[w12, 0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xd5, 0x42, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.h, p5/m, za1v.h[w14, 2]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0x42, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z23.h, p3/m, za1v.h[w15, 5]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xfd, 0x42, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z31.h, p7/m, za1v.h[w15, 7]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x8c, 0x42, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z5.h, p3/m, za0v.h[w12, 1]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x84, 0x42, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z1.h, p1/m, za0v.h[w12, 1]"
+
+  -
+    input:
+      bytes: [ 0x78, 0xd4, 0x42, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z24.h, p5/m, za0v.h[w14, 3]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x99, 0x42, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.h, p6/m, za1v.h[w12, 4]"
+
+  -
+    input:
+      bytes: [ 0x31, 0xc8, 0x42, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z17.h, p2/m, za0v.h[w14, 1]"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x88, 0x42, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z29.h, p2/m, za0v.h[w12, 6]"
+
+  -
+    input:
+      bytes: [ 0x22, 0xf5, 0x42, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z2.h, p5/m, za1v.h[w15, 1]"
+
+  -
+    input:
+      bytes: [ 0x87, 0xa9, 0x42, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z7.h, p2/m, za1v.h[w13, 4]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x82, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.s, p0/m, za0h.s[w12, 0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x55, 0x82, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.s, p5/m, za2h.s[w14, 2]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x6d, 0x82, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z23.s, p3/m, za3h.s[w15, 1]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x7d, 0x82, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z31.s, p7/m, za3h.s[w15, 3]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x0c, 0x82, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z5.s, p3/m, za0h.s[w12, 1]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x04, 0x82, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z1.s, p1/m, za0h.s[w12, 1]"
+
+  -
+    input:
+      bytes: [ 0x78, 0x54, 0x82, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z24.s, p5/m, za0h.s[w14, 3]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x19, 0x82, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.s, p6/m, za3h.s[w12, 0]"
+
+  -
+    input:
+      bytes: [ 0x31, 0x48, 0x82, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z17.s, p2/m, za0h.s[w14, 1]"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x08, 0x82, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z29.s, p2/m, za1h.s[w12, 2]"
+
+  -
+    input:
+      bytes: [ 0x22, 0x75, 0x82, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z2.s, p5/m, za2h.s[w15, 1]"
+
+  -
+    input:
+      bytes: [ 0x87, 0x29, 0x82, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z7.s, p2/m, za3h.s[w13, 0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x82, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.s, p0/m, za0h.s[w12, 0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x55, 0x82, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.s, p5/m, za2h.s[w14, 2]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x6d, 0x82, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z23.s, p3/m, za3h.s[w15, 1]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x7d, 0x82, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z31.s, p7/m, za3h.s[w15, 3]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x0c, 0x82, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z5.s, p3/m, za0h.s[w12, 1]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x04, 0x82, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z1.s, p1/m, za0h.s[w12, 1]"
+
+  -
+    input:
+      bytes: [ 0x78, 0x54, 0x82, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z24.s, p5/m, za0h.s[w14, 3]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x19, 0x82, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.s, p6/m, za3h.s[w12, 0]"
+
+  -
+    input:
+      bytes: [ 0x31, 0x48, 0x82, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z17.s, p2/m, za0h.s[w14, 1]"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x08, 0x82, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z29.s, p2/m, za1h.s[w12, 2]"
+
+  -
+    input:
+      bytes: [ 0x22, 0x75, 0x82, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z2.s, p5/m, za2h.s[w15, 1]"
+
+  -
+    input:
+      bytes: [ 0x87, 0x29, 0x82, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z7.s, p2/m, za3h.s[w13, 0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x82, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.s, p0/m, za0v.s[w12, 0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xd5, 0x82, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.s, p5/m, za2v.s[w14, 2]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0x82, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z23.s, p3/m, za3v.s[w15, 1]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xfd, 0x82, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z31.s, p7/m, za3v.s[w15, 3]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x8c, 0x82, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z5.s, p3/m, za0v.s[w12, 1]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x84, 0x82, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z1.s, p1/m, za0v.s[w12, 1]"
+
+  -
+    input:
+      bytes: [ 0x78, 0xd4, 0x82, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z24.s, p5/m, za0v.s[w14, 3]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x99, 0x82, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.s, p6/m, za3v.s[w12, 0]"
+
+  -
+    input:
+      bytes: [ 0x31, 0xc8, 0x82, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z17.s, p2/m, za0v.s[w14, 1]"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x88, 0x82, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z29.s, p2/m, za1v.s[w12, 2]"
+
+  -
+    input:
+      bytes: [ 0x22, 0xf5, 0x82, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z2.s, p5/m, za2v.s[w15, 1]"
+
+  -
+    input:
+      bytes: [ 0x87, 0xa9, 0x82, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z7.s, p2/m, za3v.s[w13, 0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x82, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.s, p0/m, za0v.s[w12, 0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xd5, 0x82, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.s, p5/m, za2v.s[w14, 2]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0x82, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z23.s, p3/m, za3v.s[w15, 1]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xfd, 0x82, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z31.s, p7/m, za3v.s[w15, 3]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x8c, 0x82, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z5.s, p3/m, za0v.s[w12, 1]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x84, 0x82, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z1.s, p1/m, za0v.s[w12, 1]"
+
+  -
+    input:
+      bytes: [ 0x78, 0xd4, 0x82, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z24.s, p5/m, za0v.s[w14, 3]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x99, 0x82, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.s, p6/m, za3v.s[w12, 0]"
+
+  -
+    input:
+      bytes: [ 0x31, 0xc8, 0x82, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z17.s, p2/m, za0v.s[w14, 1]"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x88, 0x82, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z29.s, p2/m, za1v.s[w12, 2]"
+
+  -
+    input:
+      bytes: [ 0x22, 0xf5, 0x82, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z2.s, p5/m, za2v.s[w15, 1]"
+
+  -
+    input:
+      bytes: [ 0x87, 0xa9, 0x82, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z7.s, p2/m, za3v.s[w13, 0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0xc2, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.d, p0/m, za0h.d[w12, 0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x55, 0xc2, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.d, p5/m, za5h.d[w14, 0]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x6d, 0xc2, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z23.d, p3/m, za6h.d[w15, 1]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x7d, 0xc2, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z31.d, p7/m, za7h.d[w15, 1]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x0c, 0xc2, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z5.d, p3/m, za0h.d[w12, 1]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x04, 0xc2, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z1.d, p1/m, za0h.d[w12, 1]"
+
+  -
+    input:
+      bytes: [ 0x78, 0x54, 0xc2, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z24.d, p5/m, za1h.d[w14, 1]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x19, 0xc2, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.d, p6/m, za6h.d[w12, 0]"
+
+  -
+    input:
+      bytes: [ 0x31, 0x48, 0xc2, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z17.d, p2/m, za0h.d[w14, 1]"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x08, 0xc2, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z29.d, p2/m, za3h.d[w12, 0]"
+
+  -
+    input:
+      bytes: [ 0x22, 0x75, 0xc2, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z2.d, p5/m, za4h.d[w15, 1]"
+
+  -
+    input:
+      bytes: [ 0x87, 0x29, 0xc2, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z7.d, p2/m, za6h.d[w13, 0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0xc2, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.d, p0/m, za0h.d[w12, 0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x55, 0xc2, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.d, p5/m, za5h.d[w14, 0]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x6d, 0xc2, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z23.d, p3/m, za6h.d[w15, 1]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x7d, 0xc2, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z31.d, p7/m, za7h.d[w15, 1]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x0c, 0xc2, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z5.d, p3/m, za0h.d[w12, 1]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x04, 0xc2, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z1.d, p1/m, za0h.d[w12, 1]"
+
+  -
+    input:
+      bytes: [ 0x78, 0x54, 0xc2, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z24.d, p5/m, za1h.d[w14, 1]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x19, 0xc2, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.d, p6/m, za6h.d[w12, 0]"
+
+  -
+    input:
+      bytes: [ 0x31, 0x48, 0xc2, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z17.d, p2/m, za0h.d[w14, 1]"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x08, 0xc2, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z29.d, p2/m, za3h.d[w12, 0]"
+
+  -
+    input:
+      bytes: [ 0x22, 0x75, 0xc2, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z2.d, p5/m, za4h.d[w15, 1]"
+
+  -
+    input:
+      bytes: [ 0x87, 0x29, 0xc2, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z7.d, p2/m, za6h.d[w13, 0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xc2, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.d, p0/m, za0v.d[w12, 0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xd5, 0xc2, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.d, p5/m, za5v.d[w14, 0]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0xc2, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z23.d, p3/m, za6v.d[w15, 1]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xfd, 0xc2, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z31.d, p7/m, za7v.d[w15, 1]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x8c, 0xc2, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z5.d, p3/m, za0v.d[w12, 1]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x84, 0xc2, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z1.d, p1/m, za0v.d[w12, 1]"
+
+  -
+    input:
+      bytes: [ 0x78, 0xd4, 0xc2, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z24.d, p5/m, za1v.d[w14, 1]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x99, 0xc2, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.d, p6/m, za6v.d[w12, 0]"
+
+  -
+    input:
+      bytes: [ 0x31, 0xc8, 0xc2, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z17.d, p2/m, za0v.d[w14, 1]"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x88, 0xc2, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z29.d, p2/m, za3v.d[w12, 0]"
+
+  -
+    input:
+      bytes: [ 0x22, 0xf5, 0xc2, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z2.d, p5/m, za4v.d[w15, 1]"
+
+  -
+    input:
+      bytes: [ 0x87, 0xa9, 0xc2, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z7.d, p2/m, za6v.d[w13, 0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xc2, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.d, p0/m, za0v.d[w12, 0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xd5, 0xc2, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.d, p5/m, za5v.d[w14, 0]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0xc2, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z23.d, p3/m, za6v.d[w15, 1]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xfd, 0xc2, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z31.d, p7/m, za7v.d[w15, 1]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x8c, 0xc2, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z5.d, p3/m, za0v.d[w12, 1]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x84, 0xc2, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z1.d, p1/m, za0v.d[w12, 1]"
+
+  -
+    input:
+      bytes: [ 0x78, 0xd4, 0xc2, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z24.d, p5/m, za1v.d[w14, 1]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x99, 0xc2, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.d, p6/m, za6v.d[w12, 0]"
+
+  -
+    input:
+      bytes: [ 0x31, 0xc8, 0xc2, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z17.d, p2/m, za0v.d[w14, 1]"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x88, 0xc2, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z29.d, p2/m, za3v.d[w12, 0]"
+
+  -
+    input:
+      bytes: [ 0x22, 0xf5, 0xc2, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z2.d, p5/m, za4v.d[w15, 1]"
+
+  -
+    input:
+      bytes: [ 0x87, 0xa9, 0xc2, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z7.d, p2/m, za6v.d[w13, 0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0xc3, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.q, p0/m, za0h.q[w12, 0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x55, 0xc3, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.q, p5/m, za10h.q[w14, 0]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x6d, 0xc3, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z23.q, p3/m, za13h.q[w15, 0]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x7d, 0xc3, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z31.q, p7/m, za15h.q[w15, 0]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x0c, 0xc3, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z5.q, p3/m, za1h.q[w12, 0]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x04, 0xc3, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z1.q, p1/m, za1h.q[w12, 0]"
+
+  -
+    input:
+      bytes: [ 0x78, 0x54, 0xc3, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z24.q, p5/m, za3h.q[w14, 0]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x19, 0xc3, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.q, p6/m, za12h.q[w12, 0]"
+
+  -
+    input:
+      bytes: [ 0x31, 0x48, 0xc3, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z17.q, p2/m, za1h.q[w14, 0]"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x08, 0xc3, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z29.q, p2/m, za6h.q[w12, 0]"
+
+  -
+    input:
+      bytes: [ 0x22, 0x75, 0xc3, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z2.q, p5/m, za9h.q[w15, 0]"
+
+  -
+    input:
+      bytes: [ 0x87, 0x29, 0xc3, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z7.q, p2/m, za12h.q[w13, 0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0xc3, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.q, p0/m, za0h.q[w12, 0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x55, 0xc3, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.q, p5/m, za10h.q[w14, 0]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x6d, 0xc3, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z23.q, p3/m, za13h.q[w15, 0]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x7d, 0xc3, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z31.q, p7/m, za15h.q[w15, 0]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x0c, 0xc3, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z5.q, p3/m, za1h.q[w12, 0]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x04, 0xc3, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z1.q, p1/m, za1h.q[w12, 0]"
+
+  -
+    input:
+      bytes: [ 0x78, 0x54, 0xc3, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z24.q, p5/m, za3h.q[w14, 0]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x19, 0xc3, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.q, p6/m, za12h.q[w12, 0]"
+
+  -
+    input:
+      bytes: [ 0x31, 0x48, 0xc3, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z17.q, p2/m, za1h.q[w14, 0]"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x08, 0xc3, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z29.q, p2/m, za6h.q[w12, 0]"
+
+  -
+    input:
+      bytes: [ 0x22, 0x75, 0xc3, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z2.q, p5/m, za9h.q[w15, 0]"
+
+  -
+    input:
+      bytes: [ 0x87, 0x29, 0xc3, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z7.q, p2/m, za12h.q[w13, 0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xc3, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.q, p0/m, za0v.q[w12, 0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xd5, 0xc3, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.q, p5/m, za10v.q[w14, 0]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0xc3, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z23.q, p3/m, za13v.q[w15, 0]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xfd, 0xc3, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z31.q, p7/m, za15v.q[w15, 0]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x8c, 0xc3, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z5.q, p3/m, za1v.q[w12, 0]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x84, 0xc3, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z1.q, p1/m, za1v.q[w12, 0]"
+
+  -
+    input:
+      bytes: [ 0x78, 0xd4, 0xc3, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z24.q, p5/m, za3v.q[w14, 0]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x99, 0xc3, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.q, p6/m, za12v.q[w12, 0]"
+
+  -
+    input:
+      bytes: [ 0x31, 0xc8, 0xc3, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z17.q, p2/m, za1v.q[w14, 0]"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x88, 0xc3, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z29.q, p2/m, za6v.q[w12, 0]"
+
+  -
+    input:
+      bytes: [ 0x22, 0xf5, 0xc3, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z2.q, p5/m, za9v.q[w15, 0]"
+
+  -
+    input:
+      bytes: [ 0x87, 0xa9, 0xc3, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z7.q, p2/m, za12v.q[w13, 0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xc3, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.q, p0/m, za0v.q[w12, 0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xd5, 0xc3, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.q, p5/m, za10v.q[w14, 0]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0xc3, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z23.q, p3/m, za13v.q[w15, 0]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xfd, 0xc3, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z31.q, p7/m, za15v.q[w15, 0]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x8c, 0xc3, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z5.q, p3/m, za1v.q[w12, 0]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x84, 0xc3, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z1.q, p1/m, za1v.q[w12, 0]"
+
+  -
+    input:
+      bytes: [ 0x78, 0xd4, 0xc3, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z24.q, p5/m, za3v.q[w14, 0]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x99, 0xc3, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.q, p6/m, za12v.q[w12, 0]"
+
+  -
+    input:
+      bytes: [ 0x31, 0xc8, 0xc3, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z17.q, p2/m, za1v.q[w14, 0]"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x88, 0xc3, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z29.q, p2/m, za6v.q[w12, 0]"
+
+  -
+    input:
+      bytes: [ 0x22, 0xf5, 0xc3, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z2.q, p5/m, za9v.q[w15, 0]"
+
+  -
+    input:
+      bytes: [ 0x87, 0xa9, 0xc3, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z7.q, p2/m, za12v.q[w13, 0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x00, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.b[w12, 0], p0/m, z0.b"
+
+  -
+    input:
+      bytes: [ 0x45, 0x55, 0x00, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.b[w14, 5], p5/m, z10.b"
+
+  -
+    input:
+      bytes: [ 0xa7, 0x6d, 0x00, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.b[w15, 7], p3/m, z13.b"
+
+  -
+    input:
+      bytes: [ 0xef, 0x7f, 0x00, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.b[w15, 15], p7/m, z31.b"
+
+  -
+    input:
+      bytes: [ 0x25, 0x0e, 0x00, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.b[w12, 5], p3/m, z17.b"
+
+  -
+    input:
+      bytes: [ 0x21, 0x04, 0x00, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.b[w12, 1], p1/m, z1.b"
+
+  -
+    input:
+      bytes: [ 0x68, 0x56, 0x00, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.b[w14, 8], p5/m, z19.b"
+
+  -
+    input:
+      bytes: [ 0x80, 0x19, 0x00, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.b[w12, 0], p6/m, z12.b"
+
+  -
+    input:
+      bytes: [ 0x21, 0x48, 0x00, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.b[w14, 1], p2/m, z1.b"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x0a, 0x00, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.b[w12, 13], p2/m, z22.b"
+
+  -
+    input:
+      bytes: [ 0x22, 0x75, 0x00, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.b[w15, 2], p5/m, z9.b"
+
+  -
+    input:
+      bytes: [ 0x87, 0x29, 0x00, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.b[w13, 7], p2/m, z12.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x00, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.b[w12, 0], p0/m, z0.b"
+
+  -
+    input:
+      bytes: [ 0x45, 0x55, 0x00, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.b[w14, 5], p5/m, z10.b"
+
+  -
+    input:
+      bytes: [ 0xa7, 0x6d, 0x00, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.b[w15, 7], p3/m, z13.b"
+
+  -
+    input:
+      bytes: [ 0xef, 0x7f, 0x00, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.b[w15, 15], p7/m, z31.b"
+
+  -
+    input:
+      bytes: [ 0x25, 0x0e, 0x00, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.b[w12, 5], p3/m, z17.b"
+
+  -
+    input:
+      bytes: [ 0x21, 0x04, 0x00, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.b[w12, 1], p1/m, z1.b"
+
+  -
+    input:
+      bytes: [ 0x68, 0x56, 0x00, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.b[w14, 8], p5/m, z19.b"
+
+  -
+    input:
+      bytes: [ 0x80, 0x19, 0x00, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.b[w12, 0], p6/m, z12.b"
+
+  -
+    input:
+      bytes: [ 0x21, 0x48, 0x00, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.b[w14, 1], p2/m, z1.b"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x0a, 0x00, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.b[w12, 13], p2/m, z22.b"
+
+  -
+    input:
+      bytes: [ 0x22, 0x75, 0x00, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.b[w15, 2], p5/m, z9.b"
+
+  -
+    input:
+      bytes: [ 0x87, 0x29, 0x00, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.b[w13, 7], p2/m, z12.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x00, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.b[w12, 0], p0/m, z0.b"
+
+  -
+    input:
+      bytes: [ 0x45, 0xd5, 0x00, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.b[w14, 5], p5/m, z10.b"
+
+  -
+    input:
+      bytes: [ 0xa7, 0xed, 0x00, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.b[w15, 7], p3/m, z13.b"
+
+  -
+    input:
+      bytes: [ 0xef, 0xff, 0x00, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.b[w15, 15], p7/m, z31.b"
+
+  -
+    input:
+      bytes: [ 0x25, 0x8e, 0x00, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.b[w12, 5], p3/m, z17.b"
+
+  -
+    input:
+      bytes: [ 0x21, 0x84, 0x00, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.b[w12, 1], p1/m, z1.b"
+
+  -
+    input:
+      bytes: [ 0x68, 0xd6, 0x00, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.b[w14, 8], p5/m, z19.b"
+
+  -
+    input:
+      bytes: [ 0x80, 0x99, 0x00, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.b[w12, 0], p6/m, z12.b"
+
+  -
+    input:
+      bytes: [ 0x21, 0xc8, 0x00, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.b[w14, 1], p2/m, z1.b"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x8a, 0x00, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.b[w12, 13], p2/m, z22.b"
+
+  -
+    input:
+      bytes: [ 0x22, 0xf5, 0x00, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.b[w15, 2], p5/m, z9.b"
+
+  -
+    input:
+      bytes: [ 0x87, 0xa9, 0x00, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.b[w13, 7], p2/m, z12.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x00, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.b[w12, 0], p0/m, z0.b"
+
+  -
+    input:
+      bytes: [ 0x45, 0xd5, 0x00, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.b[w14, 5], p5/m, z10.b"
+
+  -
+    input:
+      bytes: [ 0xa7, 0xed, 0x00, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.b[w15, 7], p3/m, z13.b"
+
+  -
+    input:
+      bytes: [ 0xef, 0xff, 0x00, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.b[w15, 15], p7/m, z31.b"
+
+  -
+    input:
+      bytes: [ 0x25, 0x8e, 0x00, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.b[w12, 5], p3/m, z17.b"
+
+  -
+    input:
+      bytes: [ 0x21, 0x84, 0x00, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.b[w12, 1], p1/m, z1.b"
+
+  -
+    input:
+      bytes: [ 0x68, 0xd6, 0x00, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.b[w14, 8], p5/m, z19.b"
+
+  -
+    input:
+      bytes: [ 0x80, 0x99, 0x00, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.b[w12, 0], p6/m, z12.b"
+
+  -
+    input:
+      bytes: [ 0x21, 0xc8, 0x00, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.b[w14, 1], p2/m, z1.b"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x8a, 0x00, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.b[w12, 13], p2/m, z22.b"
+
+  -
+    input:
+      bytes: [ 0x22, 0xf5, 0x00, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.b[w15, 2], p5/m, z9.b"
+
+  -
+    input:
+      bytes: [ 0x87, 0xa9, 0x00, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.b[w13, 7], p2/m, z12.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x40, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.h[w12, 0], p0/m, z0.h"
+
+  -
+    input:
+      bytes: [ 0x45, 0x55, 0x40, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.h[w14, 5], p5/m, z10.h"
+
+  -
+    input:
+      bytes: [ 0xa7, 0x6d, 0x40, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.h[w15, 7], p3/m, z13.h"
+
+  -
+    input:
+      bytes: [ 0xef, 0x7f, 0x40, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1h.h[w15, 7], p7/m, z31.h"
+
+  -
+    input:
+      bytes: [ 0x25, 0x0e, 0x40, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.h[w12, 5], p3/m, z17.h"
+
+  -
+    input:
+      bytes: [ 0x21, 0x04, 0x40, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.h[w12, 1], p1/m, z1.h"
+
+  -
+    input:
+      bytes: [ 0x68, 0x56, 0x40, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1h.h[w14, 0], p5/m, z19.h"
+
+  -
+    input:
+      bytes: [ 0x80, 0x19, 0x40, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.h[w12, 0], p6/m, z12.h"
+
+  -
+    input:
+      bytes: [ 0x21, 0x48, 0x40, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.h[w14, 1], p2/m, z1.h"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x0a, 0x40, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1h.h[w12, 5], p2/m, z22.h"
+
+  -
+    input:
+      bytes: [ 0x22, 0x75, 0x40, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.h[w15, 2], p5/m, z9.h"
+
+  -
+    input:
+      bytes: [ 0x87, 0x29, 0x40, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.h[w13, 7], p2/m, z12.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x40, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.h[w12, 0], p0/m, z0.h"
+
+  -
+    input:
+      bytes: [ 0x45, 0x55, 0x40, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.h[w14, 5], p5/m, z10.h"
+
+  -
+    input:
+      bytes: [ 0xa7, 0x6d, 0x40, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.h[w15, 7], p3/m, z13.h"
+
+  -
+    input:
+      bytes: [ 0xef, 0x7f, 0x40, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1h.h[w15, 7], p7/m, z31.h"
+
+  -
+    input:
+      bytes: [ 0x25, 0x0e, 0x40, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.h[w12, 5], p3/m, z17.h"
+
+  -
+    input:
+      bytes: [ 0x21, 0x04, 0x40, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.h[w12, 1], p1/m, z1.h"
+
+  -
+    input:
+      bytes: [ 0x68, 0x56, 0x40, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1h.h[w14, 0], p5/m, z19.h"
+
+  -
+    input:
+      bytes: [ 0x80, 0x19, 0x40, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.h[w12, 0], p6/m, z12.h"
+
+  -
+    input:
+      bytes: [ 0x21, 0x48, 0x40, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.h[w14, 1], p2/m, z1.h"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x0a, 0x40, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1h.h[w12, 5], p2/m, z22.h"
+
+  -
+    input:
+      bytes: [ 0x22, 0x75, 0x40, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.h[w15, 2], p5/m, z9.h"
+
+  -
+    input:
+      bytes: [ 0x87, 0x29, 0x40, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.h[w13, 7], p2/m, z12.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x40, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.h[w12, 0], p0/m, z0.h"
+
+  -
+    input:
+      bytes: [ 0x45, 0xd5, 0x40, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.h[w14, 5], p5/m, z10.h"
+
+  -
+    input:
+      bytes: [ 0xa7, 0xed, 0x40, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.h[w15, 7], p3/m, z13.h"
+
+  -
+    input:
+      bytes: [ 0xef, 0xff, 0x40, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1v.h[w15, 7], p7/m, z31.h"
+
+  -
+    input:
+      bytes: [ 0x25, 0x8e, 0x40, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.h[w12, 5], p3/m, z17.h"
+
+  -
+    input:
+      bytes: [ 0x21, 0x84, 0x40, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.h[w12, 1], p1/m, z1.h"
+
+  -
+    input:
+      bytes: [ 0x68, 0xd6, 0x40, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1v.h[w14, 0], p5/m, z19.h"
+
+  -
+    input:
+      bytes: [ 0x80, 0x99, 0x40, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.h[w12, 0], p6/m, z12.h"
+
+  -
+    input:
+      bytes: [ 0x21, 0xc8, 0x40, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.h[w14, 1], p2/m, z1.h"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x8a, 0x40, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1v.h[w12, 5], p2/m, z22.h"
+
+  -
+    input:
+      bytes: [ 0x22, 0xf5, 0x40, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.h[w15, 2], p5/m, z9.h"
+
+  -
+    input:
+      bytes: [ 0x87, 0xa9, 0x40, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.h[w13, 7], p2/m, z12.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x40, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.h[w12, 0], p0/m, z0.h"
+
+  -
+    input:
+      bytes: [ 0x45, 0xd5, 0x40, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.h[w14, 5], p5/m, z10.h"
+
+  -
+    input:
+      bytes: [ 0xa7, 0xed, 0x40, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.h[w15, 7], p3/m, z13.h"
+
+  -
+    input:
+      bytes: [ 0xef, 0xff, 0x40, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1v.h[w15, 7], p7/m, z31.h"
+
+  -
+    input:
+      bytes: [ 0x25, 0x8e, 0x40, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.h[w12, 5], p3/m, z17.h"
+
+  -
+    input:
+      bytes: [ 0x21, 0x84, 0x40, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.h[w12, 1], p1/m, z1.h"
+
+  -
+    input:
+      bytes: [ 0x68, 0xd6, 0x40, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1v.h[w14, 0], p5/m, z19.h"
+
+  -
+    input:
+      bytes: [ 0x80, 0x99, 0x40, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.h[w12, 0], p6/m, z12.h"
+
+  -
+    input:
+      bytes: [ 0x21, 0xc8, 0x40, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.h[w14, 1], p2/m, z1.h"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x8a, 0x40, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1v.h[w12, 5], p2/m, z22.h"
+
+  -
+    input:
+      bytes: [ 0x22, 0xf5, 0x40, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.h[w15, 2], p5/m, z9.h"
+
+  -
+    input:
+      bytes: [ 0x87, 0xa9, 0x40, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.h[w13, 7], p2/m, z12.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x80, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.s[w12, 0], p0/m, z0.s"
+
+  -
+    input:
+      bytes: [ 0x45, 0x55, 0x80, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1h.s[w14, 1], p5/m, z10.s"
+
+  -
+    input:
+      bytes: [ 0xa7, 0x6d, 0x80, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1h.s[w15, 3], p3/m, z13.s"
+
+  -
+    input:
+      bytes: [ 0xef, 0x7f, 0x80, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za3h.s[w15, 3], p7/m, z31.s"
+
+  -
+    input:
+      bytes: [ 0x25, 0x0e, 0x80, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1h.s[w12, 1], p3/m, z17.s"
+
+  -
+    input:
+      bytes: [ 0x21, 0x04, 0x80, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.s[w12, 1], p1/m, z1.s"
+
+  -
+    input:
+      bytes: [ 0x68, 0x56, 0x80, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za2h.s[w14, 0], p5/m, z19.s"
+
+  -
+    input:
+      bytes: [ 0x80, 0x19, 0x80, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.s[w12, 0], p6/m, z12.s"
+
+  -
+    input:
+      bytes: [ 0x21, 0x48, 0x80, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.s[w14, 1], p2/m, z1.s"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x0a, 0x80, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za3h.s[w12, 1], p2/m, z22.s"
+
+  -
+    input:
+      bytes: [ 0x22, 0x75, 0x80, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.s[w15, 2], p5/m, z9.s"
+
+  -
+    input:
+      bytes: [ 0x87, 0x29, 0x80, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1h.s[w13, 3], p2/m, z12.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x80, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.s[w12, 0], p0/m, z0.s"
+
+  -
+    input:
+      bytes: [ 0x45, 0x55, 0x80, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1h.s[w14, 1], p5/m, z10.s"
+
+  -
+    input:
+      bytes: [ 0xa7, 0x6d, 0x80, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1h.s[w15, 3], p3/m, z13.s"
+
+  -
+    input:
+      bytes: [ 0xef, 0x7f, 0x80, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za3h.s[w15, 3], p7/m, z31.s"
+
+  -
+    input:
+      bytes: [ 0x25, 0x0e, 0x80, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1h.s[w12, 1], p3/m, z17.s"
+
+  -
+    input:
+      bytes: [ 0x21, 0x04, 0x80, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.s[w12, 1], p1/m, z1.s"
+
+  -
+    input:
+      bytes: [ 0x68, 0x56, 0x80, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za2h.s[w14, 0], p5/m, z19.s"
+
+  -
+    input:
+      bytes: [ 0x80, 0x19, 0x80, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.s[w12, 0], p6/m, z12.s"
+
+  -
+    input:
+      bytes: [ 0x21, 0x48, 0x80, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.s[w14, 1], p2/m, z1.s"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x0a, 0x80, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za3h.s[w12, 1], p2/m, z22.s"
+
+  -
+    input:
+      bytes: [ 0x22, 0x75, 0x80, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.s[w15, 2], p5/m, z9.s"
+
+  -
+    input:
+      bytes: [ 0x87, 0x29, 0x80, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1h.s[w13, 3], p2/m, z12.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x80, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.s[w12, 0], p0/m, z0.s"
+
+  -
+    input:
+      bytes: [ 0x45, 0xd5, 0x80, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1v.s[w14, 1], p5/m, z10.s"
+
+  -
+    input:
+      bytes: [ 0xa7, 0xed, 0x80, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1v.s[w15, 3], p3/m, z13.s"
+
+  -
+    input:
+      bytes: [ 0xef, 0xff, 0x80, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za3v.s[w15, 3], p7/m, z31.s"
+
+  -
+    input:
+      bytes: [ 0x25, 0x8e, 0x80, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1v.s[w12, 1], p3/m, z17.s"
+
+  -
+    input:
+      bytes: [ 0x21, 0x84, 0x80, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.s[w12, 1], p1/m, z1.s"
+
+  -
+    input:
+      bytes: [ 0x68, 0xd6, 0x80, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za2v.s[w14, 0], p5/m, z19.s"
+
+  -
+    input:
+      bytes: [ 0x80, 0x99, 0x80, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.s[w12, 0], p6/m, z12.s"
+
+  -
+    input:
+      bytes: [ 0x21, 0xc8, 0x80, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.s[w14, 1], p2/m, z1.s"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x8a, 0x80, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za3v.s[w12, 1], p2/m, z22.s"
+
+  -
+    input:
+      bytes: [ 0x22, 0xf5, 0x80, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.s[w15, 2], p5/m, z9.s"
+
+  -
+    input:
+      bytes: [ 0x87, 0xa9, 0x80, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1v.s[w13, 3], p2/m, z12.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x80, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.s[w12, 0], p0/m, z0.s"
+
+  -
+    input:
+      bytes: [ 0x45, 0xd5, 0x80, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1v.s[w14, 1], p5/m, z10.s"
+
+  -
+    input:
+      bytes: [ 0xa7, 0xed, 0x80, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1v.s[w15, 3], p3/m, z13.s"
+
+  -
+    input:
+      bytes: [ 0xef, 0xff, 0x80, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za3v.s[w15, 3], p7/m, z31.s"
+
+  -
+    input:
+      bytes: [ 0x25, 0x8e, 0x80, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1v.s[w12, 1], p3/m, z17.s"
+
+  -
+    input:
+      bytes: [ 0x21, 0x84, 0x80, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.s[w12, 1], p1/m, z1.s"
+
+  -
+    input:
+      bytes: [ 0x68, 0xd6, 0x80, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za2v.s[w14, 0], p5/m, z19.s"
+
+  -
+    input:
+      bytes: [ 0x80, 0x99, 0x80, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.s[w12, 0], p6/m, z12.s"
+
+  -
+    input:
+      bytes: [ 0x21, 0xc8, 0x80, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.s[w14, 1], p2/m, z1.s"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x8a, 0x80, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za3v.s[w12, 1], p2/m, z22.s"
+
+  -
+    input:
+      bytes: [ 0x22, 0xf5, 0x80, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.s[w15, 2], p5/m, z9.s"
+
+  -
+    input:
+      bytes: [ 0x87, 0xa9, 0x80, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1v.s[w13, 3], p2/m, z12.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0xc0, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.d[w12, 0], p0/m, z0.d"
+
+  -
+    input:
+      bytes: [ 0x45, 0x55, 0xc0, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za2h.d[w14, 1], p5/m, z10.d"
+
+  -
+    input:
+      bytes: [ 0xa7, 0x6d, 0xc0, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za3h.d[w15, 1], p3/m, z13.d"
+
+  -
+    input:
+      bytes: [ 0xef, 0x7f, 0xc0, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za7h.d[w15, 1], p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0x25, 0x0e, 0xc0, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za2h.d[w12, 1], p3/m, z17.d"
+
+  -
+    input:
+      bytes: [ 0x21, 0x04, 0xc0, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.d[w12, 1], p1/m, z1.d"
+
+  -
+    input:
+      bytes: [ 0x68, 0x56, 0xc0, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za4h.d[w14, 0], p5/m, z19.d"
+
+  -
+    input:
+      bytes: [ 0x80, 0x19, 0xc0, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.d[w12, 0], p6/m, z12.d"
+
+  -
+    input:
+      bytes: [ 0x21, 0x48, 0xc0, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.d[w14, 1], p2/m, z1.d"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x0a, 0xc0, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za6h.d[w12, 1], p2/m, z22.d"
+
+  -
+    input:
+      bytes: [ 0x22, 0x75, 0xc0, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1h.d[w15, 0], p5/m, z9.d"
+
+  -
+    input:
+      bytes: [ 0x87, 0x29, 0xc0, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za3h.d[w13, 1], p2/m, z12.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0xc0, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.d[w12, 0], p0/m, z0.d"
+
+  -
+    input:
+      bytes: [ 0x45, 0x55, 0xc0, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za2h.d[w14, 1], p5/m, z10.d"
+
+  -
+    input:
+      bytes: [ 0xa7, 0x6d, 0xc0, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za3h.d[w15, 1], p3/m, z13.d"
+
+  -
+    input:
+      bytes: [ 0xef, 0x7f, 0xc0, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za7h.d[w15, 1], p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0x25, 0x0e, 0xc0, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za2h.d[w12, 1], p3/m, z17.d"
+
+  -
+    input:
+      bytes: [ 0x21, 0x04, 0xc0, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.d[w12, 1], p1/m, z1.d"
+
+  -
+    input:
+      bytes: [ 0x68, 0x56, 0xc0, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za4h.d[w14, 0], p5/m, z19.d"
+
+  -
+    input:
+      bytes: [ 0x80, 0x19, 0xc0, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.d[w12, 0], p6/m, z12.d"
+
+  -
+    input:
+      bytes: [ 0x21, 0x48, 0xc0, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.d[w14, 1], p2/m, z1.d"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x0a, 0xc0, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za6h.d[w12, 1], p2/m, z22.d"
+
+  -
+    input:
+      bytes: [ 0x22, 0x75, 0xc0, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1h.d[w15, 0], p5/m, z9.d"
+
+  -
+    input:
+      bytes: [ 0x87, 0x29, 0xc0, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za3h.d[w13, 1], p2/m, z12.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xc0, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.d[w12, 0], p0/m, z0.d"
+
+  -
+    input:
+      bytes: [ 0x45, 0xd5, 0xc0, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za2v.d[w14, 1], p5/m, z10.d"
+
+  -
+    input:
+      bytes: [ 0xa7, 0xed, 0xc0, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za3v.d[w15, 1], p3/m, z13.d"
+
+  -
+    input:
+      bytes: [ 0xef, 0xff, 0xc0, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za7v.d[w15, 1], p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0x25, 0x8e, 0xc0, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za2v.d[w12, 1], p3/m, z17.d"
+
+  -
+    input:
+      bytes: [ 0x21, 0x84, 0xc0, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.d[w12, 1], p1/m, z1.d"
+
+  -
+    input:
+      bytes: [ 0x68, 0xd6, 0xc0, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za4v.d[w14, 0], p5/m, z19.d"
+
+  -
+    input:
+      bytes: [ 0x80, 0x99, 0xc0, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.d[w12, 0], p6/m, z12.d"
+
+  -
+    input:
+      bytes: [ 0x21, 0xc8, 0xc0, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.d[w14, 1], p2/m, z1.d"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x8a, 0xc0, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za6v.d[w12, 1], p2/m, z22.d"
+
+  -
+    input:
+      bytes: [ 0x22, 0xf5, 0xc0, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1v.d[w15, 0], p5/m, z9.d"
+
+  -
+    input:
+      bytes: [ 0x87, 0xa9, 0xc0, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za3v.d[w13, 1], p2/m, z12.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xc0, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.d[w12, 0], p0/m, z0.d"
+
+  -
+    input:
+      bytes: [ 0x45, 0xd5, 0xc0, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za2v.d[w14, 1], p5/m, z10.d"
+
+  -
+    input:
+      bytes: [ 0xa7, 0xed, 0xc0, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za3v.d[w15, 1], p3/m, z13.d"
+
+  -
+    input:
+      bytes: [ 0xef, 0xff, 0xc0, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za7v.d[w15, 1], p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0x25, 0x8e, 0xc0, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za2v.d[w12, 1], p3/m, z17.d"
+
+  -
+    input:
+      bytes: [ 0x21, 0x84, 0xc0, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.d[w12, 1], p1/m, z1.d"
+
+  -
+    input:
+      bytes: [ 0x68, 0xd6, 0xc0, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za4v.d[w14, 0], p5/m, z19.d"
+
+  -
+    input:
+      bytes: [ 0x80, 0x99, 0xc0, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.d[w12, 0], p6/m, z12.d"
+
+  -
+    input:
+      bytes: [ 0x21, 0xc8, 0xc0, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.d[w14, 1], p2/m, z1.d"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x8a, 0xc0, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za6v.d[w12, 1], p2/m, z22.d"
+
+  -
+    input:
+      bytes: [ 0x22, 0xf5, 0xc0, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1v.d[w15, 0], p5/m, z9.d"
+
+  -
+    input:
+      bytes: [ 0x87, 0xa9, 0xc0, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za3v.d[w13, 1], p2/m, z12.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0xc1, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.q[w12, 0], p0/m, z0.q"
+
+  -
+    input:
+      bytes: [ 0x45, 0x55, 0xc1, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za5h.q[w14, 0], p5/m, z10.q"
+
+  -
+    input:
+      bytes: [ 0xa7, 0x6d, 0xc1, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za7h.q[w15, 0], p3/m, z13.q"
+
+  -
+    input:
+      bytes: [ 0xef, 0x7f, 0xc1, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za15h.q[w15, 0], p7/m, z31.q"
+
+  -
+    input:
+      bytes: [ 0x25, 0x0e, 0xc1, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za5h.q[w12, 0], p3/m, z17.q"
+
+  -
+    input:
+      bytes: [ 0x21, 0x04, 0xc1, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1h.q[w12, 0], p1/m, z1.q"
+
+  -
+    input:
+      bytes: [ 0x68, 0x56, 0xc1, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za8h.q[w14, 0], p5/m, z19.q"
+
+  -
+    input:
+      bytes: [ 0x80, 0x19, 0xc1, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.q[w12, 0], p6/m, z12.q"
+
+  -
+    input:
+      bytes: [ 0x21, 0x48, 0xc1, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1h.q[w14, 0], p2/m, z1.q"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x0a, 0xc1, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za13h.q[w12, 0], p2/m, z22.q"
+
+  -
+    input:
+      bytes: [ 0x22, 0x75, 0xc1, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za2h.q[w15, 0], p5/m, z9.q"
+
+  -
+    input:
+      bytes: [ 0x87, 0x29, 0xc1, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za7h.q[w13, 0], p2/m, z12.q"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0xc1, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.q[w12, 0], p0/m, z0.q"
+
+  -
+    input:
+      bytes: [ 0x45, 0x55, 0xc1, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za5h.q[w14, 0], p5/m, z10.q"
+
+  -
+    input:
+      bytes: [ 0xa7, 0x6d, 0xc1, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za7h.q[w15, 0], p3/m, z13.q"
+
+  -
+    input:
+      bytes: [ 0xef, 0x7f, 0xc1, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za15h.q[w15, 0], p7/m, z31.q"
+
+  -
+    input:
+      bytes: [ 0x25, 0x0e, 0xc1, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za5h.q[w12, 0], p3/m, z17.q"
+
+  -
+    input:
+      bytes: [ 0x21, 0x04, 0xc1, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1h.q[w12, 0], p1/m, z1.q"
+
+  -
+    input:
+      bytes: [ 0x68, 0x56, 0xc1, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za8h.q[w14, 0], p5/m, z19.q"
+
+  -
+    input:
+      bytes: [ 0x80, 0x19, 0xc1, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.q[w12, 0], p6/m, z12.q"
+
+  -
+    input:
+      bytes: [ 0x21, 0x48, 0xc1, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1h.q[w14, 0], p2/m, z1.q"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x0a, 0xc1, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za13h.q[w12, 0], p2/m, z22.q"
+
+  -
+    input:
+      bytes: [ 0x22, 0x75, 0xc1, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za2h.q[w15, 0], p5/m, z9.q"
+
+  -
+    input:
+      bytes: [ 0x87, 0x29, 0xc1, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za7h.q[w13, 0], p2/m, z12.q"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xc1, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.q[w12, 0], p0/m, z0.q"
+
+  -
+    input:
+      bytes: [ 0x45, 0xd5, 0xc1, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za5v.q[w14, 0], p5/m, z10.q"
+
+  -
+    input:
+      bytes: [ 0xa7, 0xed, 0xc1, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za7v.q[w15, 0], p3/m, z13.q"
+
+  -
+    input:
+      bytes: [ 0xef, 0xff, 0xc1, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za15v.q[w15, 0], p7/m, z31.q"
+
+  -
+    input:
+      bytes: [ 0x25, 0x8e, 0xc1, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za5v.q[w12, 0], p3/m, z17.q"
+
+  -
+    input:
+      bytes: [ 0x21, 0x84, 0xc1, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1v.q[w12, 0], p1/m, z1.q"
+
+  -
+    input:
+      bytes: [ 0x68, 0xd6, 0xc1, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za8v.q[w14, 0], p5/m, z19.q"
+
+  -
+    input:
+      bytes: [ 0x80, 0x99, 0xc1, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.q[w12, 0], p6/m, z12.q"
+
+  -
+    input:
+      bytes: [ 0x21, 0xc8, 0xc1, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1v.q[w14, 0], p2/m, z1.q"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x8a, 0xc1, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za13v.q[w12, 0], p2/m, z22.q"
+
+  -
+    input:
+      bytes: [ 0x22, 0xf5, 0xc1, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za2v.q[w15, 0], p5/m, z9.q"
+
+  -
+    input:
+      bytes: [ 0x87, 0xa9, 0xc1, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za7v.q[w13, 0], p2/m, z12.q"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xc1, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.q[w12, 0], p0/m, z0.q"
+
+  -
+    input:
+      bytes: [ 0x45, 0xd5, 0xc1, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za5v.q[w14, 0], p5/m, z10.q"
+
+  -
+    input:
+      bytes: [ 0xa7, 0xed, 0xc1, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za7v.q[w15, 0], p3/m, z13.q"
+
+  -
+    input:
+      bytes: [ 0xef, 0xff, 0xc1, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za15v.q[w15, 0], p7/m, z31.q"
+
+  -
+    input:
+      bytes: [ 0x25, 0x8e, 0xc1, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za5v.q[w12, 0], p3/m, z17.q"
+
+  -
+    input:
+      bytes: [ 0x21, 0x84, 0xc1, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1v.q[w12, 0], p1/m, z1.q"
+
+  -
+    input:
+      bytes: [ 0x68, 0xd6, 0xc1, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za8v.q[w14, 0], p5/m, z19.q"
+
+  -
+    input:
+      bytes: [ 0x80, 0x99, 0xc1, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.q[w12, 0], p6/m, z12.q"
+
+  -
+    input:
+      bytes: [ 0x21, 0xc8, 0xc1, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1v.q[w14, 0], p2/m, z1.q"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x8a, 0xc1, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za13v.q[w12, 0], p2/m, z22.q"
+
+  -
+    input:
+      bytes: [ 0x22, 0xf5, 0xc1, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za2v.q[w15, 0], p5/m, z9.q"
+
+  -
+    input:
+      bytes: [ 0x87, 0xa9, 0xc1, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za7v.q[w13, 0], p2/m, z12.q"
diff --git a/tests/MC/AArch64/SME/psel.s.yaml b/tests/MC/AArch64/SME/psel.s.yaml
new file mode 100644
index 000000000..abb202ca3
--- /dev/null
+++ b/tests/MC/AArch64/SME/psel.s.yaml
@@ -0,0 +1,200 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0x24, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "psel p0, p0, p0.b[w12, 0]"
+
+  -
+    input:
+      bytes: [ 0x45, 0x55, 0x75, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "psel p5, p5, p10.b[w13, 6]"
+
+  -
+    input:
+      bytes: [ 0xa7, 0x6d, 0x6c, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "psel p7, p11, p13.b[w12, 5]"
+
+  -
+    input:
+      bytes: [ 0xef, 0x7d, 0xff, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "psel p15, p15, p15.b[w15, 15]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0x28, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "psel p0, p0, p0.h[w12, 0]"
+
+  -
+    input:
+      bytes: [ 0x45, 0x55, 0x79, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "psel p5, p5, p10.h[w13, 3]"
+
+  -
+    input:
+      bytes: [ 0xa7, 0x6d, 0x68, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "psel p7, p11, p13.h[w12, 2]"
+
+  -
+    input:
+      bytes: [ 0xef, 0x7d, 0xfb, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "psel p15, p15, p15.h[w15, 7]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0x30, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "psel p0, p0, p0.s[w12, 0]"
+
+  -
+    input:
+      bytes: [ 0x45, 0x55, 0x71, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "psel p5, p5, p10.s[w13, 1]"
+
+  -
+    input:
+      bytes: [ 0xa7, 0x6d, 0x70, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "psel p7, p11, p13.s[w12, 1]"
+
+  -
+    input:
+      bytes: [ 0xef, 0x7d, 0xf3, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "psel p15, p15, p15.s[w15, 3]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0x60, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "psel p0, p0, p0.d[w12, 0]"
+
+  -
+    input:
+      bytes: [ 0x45, 0x55, 0x61, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "psel p5, p5, p10.d[w13, 0]"
+
+  -
+    input:
+      bytes: [ 0xa7, 0x6d, 0x60, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "psel p7, p11, p13.d[w12, 0]"
+
+  -
+    input:
+      bytes: [ 0xef, 0x7d, 0xe3, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "psel p15, p15, p15.d[w15, 1]"
+
+  -
+    input:
+      bytes: [ 0xef, 0x7d, 0xff, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "psel p15, p15, p15.b[w15, 15]"
+
+  -
+    input:
+      bytes: [ 0xef, 0x7d, 0xfb, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "psel p15, p15, p15.h[w15, 7]"
+
+  -
+    input:
+      bytes: [ 0xef, 0x7d, 0xf3, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "psel p15, p15, p15.s[w15, 3]"
+
+  -
+    input:
+      bytes: [ 0xef, 0x7d, 0xe3, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "psel p15, p15, p15.d[w15, 1]"
diff --git a/tests/MC/AArch64/SME/rdsvl.s.yaml b/tests/MC/AArch64/SME/rdsvl.s.yaml
new file mode 100644
index 000000000..9487686b8
--- /dev/null
+++ b/tests/MC/AArch64/SME/rdsvl.s.yaml
@@ -0,0 +1,40 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x58, 0xbf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "rdsvl x0, #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0x5f, 0xbf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "rdsvl xzr, #-1"
+
+  -
+    input:
+      bytes: [ 0xf7, 0x5b, 0xbf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "rdsvl x23, #31"
+
+  -
+    input:
+      bytes: [ 0x15, 0x5c, 0xbf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "rdsvl x21, #-32"
diff --git a/tests/MC/AArch64/SME/revd.s.yaml b/tests/MC/AArch64/SME/revd.s.yaml
new file mode 100644
index 000000000..75d396791
--- /dev/null
+++ b/tests/MC/AArch64/SME/revd.s.yaml
@@ -0,0 +1,60 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x2e, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "revd z0.q, p0/m, z0.q"
+
+  -
+    input:
+      bytes: [ 0x55, 0x95, 0x2e, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "revd z21.q, p5/m, z10.q"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x8d, 0x2e, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "revd z23.q, p3/m, z13.q"
+
+  -
+    input:
+      bytes: [ 0xff, 0x9f, 0x2e, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "revd z31.q, p7/m, z31.q"
+
+  -
+    input:
+      bytes: [ 0x35, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z21, z25"
+
+  -
+    input:
+      bytes: [ 0x55, 0x95, 0x2e, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "revd z21.q, p5/m, z10.q"
diff --git a/tests/MC/AArch64/SME/sclamp.s.yaml b/tests/MC/AArch64/SME/sclamp.s.yaml
new file mode 100644
index 000000000..a84fbe1f9
--- /dev/null
+++ b/tests/MC/AArch64/SME/sclamp.s.yaml
@@ -0,0 +1,240 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x00, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sclamp z0.b, z0.b, z0.b"
+
+  -
+    input:
+      bytes: [ 0x55, 0xc1, 0x15, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sclamp z21.b, z10.b, z21.b"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xc1, 0x08, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sclamp z23.b, z13.b, z8.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0xc3, 0x1f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sclamp z31.b, z31.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x40, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sclamp z0.h, z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x55, 0xc1, 0x55, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sclamp z21.h, z10.h, z21.h"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xc1, 0x48, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sclamp z23.h, z13.h, z8.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0xc3, 0x5f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sclamp z31.h, z31.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x80, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sclamp z0.s, z0.s, z0.s"
+
+  -
+    input:
+      bytes: [ 0x55, 0xc1, 0x95, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sclamp z21.s, z10.s, z21.s"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xc1, 0x88, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sclamp z23.s, z13.s, z8.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0xc3, 0x9f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sclamp z31.s, z31.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0xc0, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sclamp z0.d, z0.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0x55, 0xc1, 0xd5, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sclamp z21.d, z10.d, z21.d"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xc1, 0xc8, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sclamp z23.d, z13.d, z8.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0xc3, 0xdf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sclamp z31.d, z31.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0x77, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z23, z27"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xc1, 0x08, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sclamp z23.b, z13.b, z8.b"
+
+  -
+    input:
+      bytes: [ 0x77, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z23, z27"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xc1, 0x48, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sclamp z23.h, z13.h, z8.h"
+
+  -
+    input:
+      bytes: [ 0x77, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z23, z27"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xc1, 0x88, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sclamp z23.s, z13.s, z8.s"
+
+  -
+    input:
+      bytes: [ 0x77, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z23, z27"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xc1, 0xc8, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sclamp z23.d, z13.d, z8.d"
diff --git a/tests/MC/AArch64/SME/smopa-32.s.yaml b/tests/MC/AArch64/SME/smopa-32.s.yaml
new file mode 100644
index 000000000..18283aec5
--- /dev/null
+++ b/tests/MC/AArch64/SME/smopa-32.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x80, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smopa za0.s, p0/m, p0/m, z0.b, z0.b"
+
+  -
+    input:
+      bytes: [ 0x41, 0x55, 0x95, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smopa za1.s, p5/m, p2/m, z10.b, z21.b"
+
+  -
+    input:
+      bytes: [ 0xa3, 0xed, 0x88, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smopa za3.s, p3/m, p7/m, z13.b, z8.b"
+
+  -
+    input:
+      bytes: [ 0xe3, 0xff, 0x9f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smopa za3.s, p7/m, p7/m, z31.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0x21, 0x0e, 0x90, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smopa za1.s, p3/m, p0/m, z17.b, z16.b"
+
+  -
+    input:
+      bytes: [ 0x21, 0x84, 0x9e, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smopa za1.s, p1/m, p4/m, z1.b, z30.b"
+
+  -
+    input:
+      bytes: [ 0x60, 0x56, 0x94, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smopa za0.s, p5/m, p2/m, z19.b, z20.b"
+
+  -
+    input:
+      bytes: [ 0x80, 0x19, 0x82, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smopa za0.s, p6/m, p0/m, z12.b, z2.b"
+
+  -
+    input:
+      bytes: [ 0x21, 0xc8, 0x9a, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smopa za1.s, p2/m, p6/m, z1.b, z26.b"
+
+  -
+    input:
+      bytes: [ 0xc1, 0x0a, 0x9e, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smopa za1.s, p2/m, p0/m, z22.b, z30.b"
+
+  -
+    input:
+      bytes: [ 0x22, 0xf5, 0x81, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smopa za2.s, p5/m, p7/m, z9.b, z1.b"
+
+  -
+    input:
+      bytes: [ 0x83, 0xa9, 0x8b, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smopa za3.s, p2/m, p5/m, z12.b, z11.b"
diff --git a/tests/MC/AArch64/SME/smopa-64.s.yaml b/tests/MC/AArch64/SME/smopa-64.s.yaml
new file mode 100644
index 000000000..9c538c3d7
--- /dev/null
+++ b/tests/MC/AArch64/SME/smopa-64.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0xc0, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smopa za0.d, p0/m, p0/m, z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x45, 0x55, 0xd5, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smopa za5.d, p5/m, p2/m, z10.h, z21.h"
+
+  -
+    input:
+      bytes: [ 0xa7, 0xed, 0xc8, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smopa za7.d, p3/m, p7/m, z13.h, z8.h"
+
+  -
+    input:
+      bytes: [ 0xe7, 0xff, 0xdf, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smopa za7.d, p7/m, p7/m, z31.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x25, 0x0e, 0xd0, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smopa za5.d, p3/m, p0/m, z17.h, z16.h"
+
+  -
+    input:
+      bytes: [ 0x21, 0x84, 0xde, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smopa za1.d, p1/m, p4/m, z1.h, z30.h"
+
+  -
+    input:
+      bytes: [ 0x60, 0x56, 0xd4, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smopa za0.d, p5/m, p2/m, z19.h, z20.h"
+
+  -
+    input:
+      bytes: [ 0x80, 0x19, 0xc2, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smopa za0.d, p6/m, p0/m, z12.h, z2.h"
+
+  -
+    input:
+      bytes: [ 0x21, 0xc8, 0xda, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smopa za1.d, p2/m, p6/m, z1.h, z26.h"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x0a, 0xde, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smopa za5.d, p2/m, p0/m, z22.h, z30.h"
+
+  -
+    input:
+      bytes: [ 0x22, 0xf5, 0xc1, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smopa za2.d, p5/m, p7/m, z9.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0x87, 0xa9, 0xcb, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smopa za7.d, p2/m, p5/m, z12.h, z11.h"
diff --git a/tests/MC/AArch64/SME/smops-32.s.yaml b/tests/MC/AArch64/SME/smops-32.s.yaml
new file mode 100644
index 000000000..e7d3d8bd6
--- /dev/null
+++ b/tests/MC/AArch64/SME/smops-32.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x10, 0x00, 0x80, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smops za0.s, p0/m, p0/m, z0.b, z0.b"
+
+  -
+    input:
+      bytes: [ 0x51, 0x55, 0x95, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smops za1.s, p5/m, p2/m, z10.b, z21.b"
+
+  -
+    input:
+      bytes: [ 0xb3, 0xed, 0x88, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smops za3.s, p3/m, p7/m, z13.b, z8.b"
+
+  -
+    input:
+      bytes: [ 0xf3, 0xff, 0x9f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smops za3.s, p7/m, p7/m, z31.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0x31, 0x0e, 0x90, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smops za1.s, p3/m, p0/m, z17.b, z16.b"
+
+  -
+    input:
+      bytes: [ 0x31, 0x84, 0x9e, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smops za1.s, p1/m, p4/m, z1.b, z30.b"
+
+  -
+    input:
+      bytes: [ 0x70, 0x56, 0x94, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smops za0.s, p5/m, p2/m, z19.b, z20.b"
+
+  -
+    input:
+      bytes: [ 0x90, 0x19, 0x82, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smops za0.s, p6/m, p0/m, z12.b, z2.b"
+
+  -
+    input:
+      bytes: [ 0x31, 0xc8, 0x9a, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smops za1.s, p2/m, p6/m, z1.b, z26.b"
+
+  -
+    input:
+      bytes: [ 0xd1, 0x0a, 0x9e, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smops za1.s, p2/m, p0/m, z22.b, z30.b"
+
+  -
+    input:
+      bytes: [ 0x32, 0xf5, 0x81, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smops za2.s, p5/m, p7/m, z9.b, z1.b"
+
+  -
+    input:
+      bytes: [ 0x93, 0xa9, 0x8b, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smops za3.s, p2/m, p5/m, z12.b, z11.b"
diff --git a/tests/MC/AArch64/SME/smops-64.s.yaml b/tests/MC/AArch64/SME/smops-64.s.yaml
new file mode 100644
index 000000000..689e3c89d
--- /dev/null
+++ b/tests/MC/AArch64/SME/smops-64.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x10, 0x00, 0xc0, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smops za0.d, p0/m, p0/m, z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x55, 0x55, 0xd5, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smops za5.d, p5/m, p2/m, z10.h, z21.h"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0xc8, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smops za7.d, p3/m, p7/m, z13.h, z8.h"
+
+  -
+    input:
+      bytes: [ 0xf7, 0xff, 0xdf, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smops za7.d, p7/m, p7/m, z31.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x35, 0x0e, 0xd0, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smops za5.d, p3/m, p0/m, z17.h, z16.h"
+
+  -
+    input:
+      bytes: [ 0x31, 0x84, 0xde, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smops za1.d, p1/m, p4/m, z1.h, z30.h"
+
+  -
+    input:
+      bytes: [ 0x70, 0x56, 0xd4, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smops za0.d, p5/m, p2/m, z19.h, z20.h"
+
+  -
+    input:
+      bytes: [ 0x90, 0x19, 0xc2, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smops za0.d, p6/m, p0/m, z12.h, z2.h"
+
+  -
+    input:
+      bytes: [ 0x31, 0xc8, 0xda, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smops za1.d, p2/m, p6/m, z1.h, z26.h"
+
+  -
+    input:
+      bytes: [ 0xd5, 0x0a, 0xde, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smops za5.d, p2/m, p0/m, z22.h, z30.h"
+
+  -
+    input:
+      bytes: [ 0x32, 0xf5, 0xc1, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smops za2.d, p5/m, p7/m, z9.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0x97, 0xa9, 0xcb, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smops za7.d, p2/m, p5/m, z12.h, z11.h"
diff --git a/tests/MC/AArch64/SME/smstart.s.yaml b/tests/MC/AArch64/SME/smstart.s.yaml
new file mode 100644
index 000000000..f2c0eaf6d
--- /dev/null
+++ b/tests/MC/AArch64/SME/smstart.s.yaml
@@ -0,0 +1,100 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x7f, 0x47, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smstart"
+
+  -
+    input:
+      bytes: [ 0x7f, 0x43, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smstart sm"
+
+  -
+    input:
+      bytes: [ 0x7f, 0x45, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smstart za"
+
+  -
+    input:
+      bytes: [ 0x7f, 0x43, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smstart sm"
+
+  -
+    input:
+      bytes: [ 0x7f, 0x45, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smstart za"
+
+  -
+    input:
+      bytes: [ 0x7f, 0x47, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smstart"
+
+  -
+    input:
+      bytes: [ 0x7f, 0x43, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smstart sm"
+
+  -
+    input:
+      bytes: [ 0x7f, 0x45, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smstart za"
+
+  -
+    input:
+      bytes: [ 0x7f, 0x43, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smstart sm"
+
+  -
+    input:
+      bytes: [ 0x7f, 0x45, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smstart za"
diff --git a/tests/MC/AArch64/SME/smstop.s.yaml b/tests/MC/AArch64/SME/smstop.s.yaml
new file mode 100644
index 000000000..54d880a8c
--- /dev/null
+++ b/tests/MC/AArch64/SME/smstop.s.yaml
@@ -0,0 +1,100 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x7f, 0x46, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smstop"
+
+  -
+    input:
+      bytes: [ 0x7f, 0x42, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smstop sm"
+
+  -
+    input:
+      bytes: [ 0x7f, 0x44, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smstop za"
+
+  -
+    input:
+      bytes: [ 0x7f, 0x42, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smstop sm"
+
+  -
+    input:
+      bytes: [ 0x7f, 0x44, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smstop za"
+
+  -
+    input:
+      bytes: [ 0x7f, 0x46, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smstop"
+
+  -
+    input:
+      bytes: [ 0x7f, 0x42, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smstop sm"
+
+  -
+    input:
+      bytes: [ 0x7f, 0x44, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smstop za"
+
+  -
+    input:
+      bytes: [ 0x7f, 0x42, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smstop sm"
+
+  -
+    input:
+      bytes: [ 0x7f, 0x44, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smstop za"
diff --git a/tests/MC/AArch64/SME/st1b.s.yaml b/tests/MC/AArch64/SME/st1b.s.yaml
new file mode 100644
index 000000000..733d8b8bc
--- /dev/null
+++ b/tests/MC/AArch64/SME/st1b.s.yaml
@@ -0,0 +1,480 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x20, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b {za0h.b[w12, 0]}, p0, [x0, x0]"
+
+  -
+    input:
+      bytes: [ 0x45, 0x55, 0x35, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b {za0h.b[w14, 5]}, p5, [x10, x21]"
+
+  -
+    input:
+      bytes: [ 0xa7, 0x6d, 0x28, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b {za0h.b[w15, 7]}, p3, [x13, x8]"
+
+  -
+    input:
+      bytes: [ 0xef, 0x7f, 0x3f, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b {za0h.b[w15, 15]}, p7, [sp]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x0e, 0x30, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b {za0h.b[w12, 5]}, p3, [x17, x16]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x04, 0x3e, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b {za0h.b[w12, 1]}, p1, [x1, x30]"
+
+  -
+    input:
+      bytes: [ 0x68, 0x56, 0x34, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b {za0h.b[w14, 8]}, p5, [x19, x20]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x19, 0x22, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b {za0h.b[w12, 0]}, p6, [x12, x2]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x48, 0x3a, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b {za0h.b[w14, 1]}, p2, [x1, x26]"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x0a, 0x3e, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b {za0h.b[w12, 13]}, p2, [x22, x30]"
+
+  -
+    input:
+      bytes: [ 0x22, 0x75, 0x21, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b {za0h.b[w15, 2]}, p5, [x9, x1]"
+
+  -
+    input:
+      bytes: [ 0x87, 0x29, 0x2b, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b {za0h.b[w13, 7]}, p2, [x12, x11]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x20, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b {za0h.b[w12, 0]}, p0, [x0, x0]"
+
+  -
+    input:
+      bytes: [ 0x45, 0x55, 0x35, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b {za0h.b[w14, 5]}, p5, [x10, x21]"
+
+  -
+    input:
+      bytes: [ 0xa7, 0x6d, 0x28, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b {za0h.b[w15, 7]}, p3, [x13, x8]"
+
+  -
+    input:
+      bytes: [ 0xef, 0x7f, 0x3f, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b {za0h.b[w15, 15]}, p7, [sp]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x0e, 0x30, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b {za0h.b[w12, 5]}, p3, [x17, x16]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x04, 0x3e, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b {za0h.b[w12, 1]}, p1, [x1, x30]"
+
+  -
+    input:
+      bytes: [ 0x68, 0x56, 0x34, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b {za0h.b[w14, 8]}, p5, [x19, x20]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x19, 0x22, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b {za0h.b[w12, 0]}, p6, [x12, x2]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x48, 0x3a, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b {za0h.b[w14, 1]}, p2, [x1, x26]"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x0a, 0x3e, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b {za0h.b[w12, 13]}, p2, [x22, x30]"
+
+  -
+    input:
+      bytes: [ 0x22, 0x75, 0x21, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b {za0h.b[w15, 2]}, p5, [x9, x1]"
+
+  -
+    input:
+      bytes: [ 0x87, 0x29, 0x2b, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b {za0h.b[w13, 7]}, p2, [x12, x11]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x20, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b {za0v.b[w12, 0]}, p0, [x0, x0]"
+
+  -
+    input:
+      bytes: [ 0x45, 0xd5, 0x35, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b {za0v.b[w14, 5]}, p5, [x10, x21]"
+
+  -
+    input:
+      bytes: [ 0xa7, 0xed, 0x28, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b {za0v.b[w15, 7]}, p3, [x13, x8]"
+
+  -
+    input:
+      bytes: [ 0xef, 0xff, 0x3f, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b {za0v.b[w15, 15]}, p7, [sp]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x8e, 0x30, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b {za0v.b[w12, 5]}, p3, [x17, x16]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x84, 0x3e, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b {za0v.b[w12, 1]}, p1, [x1, x30]"
+
+  -
+    input:
+      bytes: [ 0x68, 0xd6, 0x34, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b {za0v.b[w14, 8]}, p5, [x19, x20]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x99, 0x22, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b {za0v.b[w12, 0]}, p6, [x12, x2]"
+
+  -
+    input:
+      bytes: [ 0x21, 0xc8, 0x3a, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b {za0v.b[w14, 1]}, p2, [x1, x26]"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x8a, 0x3e, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b {za0v.b[w12, 13]}, p2, [x22, x30]"
+
+  -
+    input:
+      bytes: [ 0x22, 0xf5, 0x21, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b {za0v.b[w15, 2]}, p5, [x9, x1]"
+
+  -
+    input:
+      bytes: [ 0x87, 0xa9, 0x2b, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b {za0v.b[w13, 7]}, p2, [x12, x11]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x20, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b {za0v.b[w12, 0]}, p0, [x0, x0]"
+
+  -
+    input:
+      bytes: [ 0x45, 0xd5, 0x35, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b {za0v.b[w14, 5]}, p5, [x10, x21]"
+
+  -
+    input:
+      bytes: [ 0xa7, 0xed, 0x28, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b {za0v.b[w15, 7]}, p3, [x13, x8]"
+
+  -
+    input:
+      bytes: [ 0xef, 0xff, 0x3f, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b {za0v.b[w15, 15]}, p7, [sp]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x8e, 0x30, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b {za0v.b[w12, 5]}, p3, [x17, x16]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x84, 0x3e, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b {za0v.b[w12, 1]}, p1, [x1, x30]"
+
+  -
+    input:
+      bytes: [ 0x68, 0xd6, 0x34, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b {za0v.b[w14, 8]}, p5, [x19, x20]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x99, 0x22, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b {za0v.b[w12, 0]}, p6, [x12, x2]"
+
+  -
+    input:
+      bytes: [ 0x21, 0xc8, 0x3a, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b {za0v.b[w14, 1]}, p2, [x1, x26]"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x8a, 0x3e, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b {za0v.b[w12, 13]}, p2, [x22, x30]"
+
+  -
+    input:
+      bytes: [ 0x22, 0xf5, 0x21, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b {za0v.b[w15, 2]}, p5, [x9, x1]"
+
+  -
+    input:
+      bytes: [ 0x87, 0xa9, 0x2b, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b {za0v.b[w13, 7]}, p2, [x12, x11]"
diff --git a/tests/MC/AArch64/SME/st1d.s.yaml b/tests/MC/AArch64/SME/st1d.s.yaml
new file mode 100644
index 000000000..edbdfdca0
--- /dev/null
+++ b/tests/MC/AArch64/SME/st1d.s.yaml
@@ -0,0 +1,480 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0xe0, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d {za0h.d[w12, 0]}, p0, [x0, x0, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x45, 0x55, 0xf5, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d {za2h.d[w14, 1]}, p5, [x10, x21, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0xa7, 0x6d, 0xe8, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d {za3h.d[w15, 1]}, p3, [x13, x8, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0xef, 0x7f, 0xff, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d {za7h.d[w15, 1]}, p7, [sp]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x0e, 0xf0, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d {za2h.d[w12, 1]}, p3, [x17, x16, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x04, 0xfe, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d {za0h.d[w12, 1]}, p1, [x1, x30, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x68, 0x56, 0xf4, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d {za4h.d[w14, 0]}, p5, [x19, x20, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x19, 0xe2, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d {za0h.d[w12, 0]}, p6, [x12, x2, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x48, 0xfa, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d {za0h.d[w14, 1]}, p2, [x1, x26, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x0a, 0xfe, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d {za6h.d[w12, 1]}, p2, [x22, x30, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x22, 0x75, 0xe1, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d {za1h.d[w15, 0]}, p5, [x9, x1, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x87, 0x29, 0xeb, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d {za3h.d[w13, 1]}, p2, [x12, x11, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0xe0, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d {za0h.d[w12, 0]}, p0, [x0, x0, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x45, 0x55, 0xf5, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d {za2h.d[w14, 1]}, p5, [x10, x21, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0xa7, 0x6d, 0xe8, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d {za3h.d[w15, 1]}, p3, [x13, x8, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0xef, 0x7f, 0xff, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d {za7h.d[w15, 1]}, p7, [sp]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x0e, 0xf0, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d {za2h.d[w12, 1]}, p3, [x17, x16, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x04, 0xfe, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d {za0h.d[w12, 1]}, p1, [x1, x30, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x68, 0x56, 0xf4, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d {za4h.d[w14, 0]}, p5, [x19, x20, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x19, 0xe2, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d {za0h.d[w12, 0]}, p6, [x12, x2, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x48, 0xfa, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d {za0h.d[w14, 1]}, p2, [x1, x26, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x0a, 0xfe, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d {za6h.d[w12, 1]}, p2, [x22, x30, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x22, 0x75, 0xe1, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d {za1h.d[w15, 0]}, p5, [x9, x1, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x87, 0x29, 0xeb, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d {za3h.d[w13, 1]}, p2, [x12, x11, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xe0, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d {za0v.d[w12, 0]}, p0, [x0, x0, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x45, 0xd5, 0xf5, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d {za2v.d[w14, 1]}, p5, [x10, x21, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0xa7, 0xed, 0xe8, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d {za3v.d[w15, 1]}, p3, [x13, x8, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0xef, 0xff, 0xff, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d {za7v.d[w15, 1]}, p7, [sp]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x8e, 0xf0, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d {za2v.d[w12, 1]}, p3, [x17, x16, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x84, 0xfe, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d {za0v.d[w12, 1]}, p1, [x1, x30, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x68, 0xd6, 0xf4, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d {za4v.d[w14, 0]}, p5, [x19, x20, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x99, 0xe2, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d {za0v.d[w12, 0]}, p6, [x12, x2, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x21, 0xc8, 0xfa, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d {za0v.d[w14, 1]}, p2, [x1, x26, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x8a, 0xfe, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d {za6v.d[w12, 1]}, p2, [x22, x30, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x22, 0xf5, 0xe1, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d {za1v.d[w15, 0]}, p5, [x9, x1, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x87, 0xa9, 0xeb, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d {za3v.d[w13, 1]}, p2, [x12, x11, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xe0, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d {za0v.d[w12, 0]}, p0, [x0, x0, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x45, 0xd5, 0xf5, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d {za2v.d[w14, 1]}, p5, [x10, x21, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0xa7, 0xed, 0xe8, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d {za3v.d[w15, 1]}, p3, [x13, x8, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0xef, 0xff, 0xff, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d {za7v.d[w15, 1]}, p7, [sp]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x8e, 0xf0, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d {za2v.d[w12, 1]}, p3, [x17, x16, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x84, 0xfe, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d {za0v.d[w12, 1]}, p1, [x1, x30, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x68, 0xd6, 0xf4, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d {za4v.d[w14, 0]}, p5, [x19, x20, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x99, 0xe2, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d {za0v.d[w12, 0]}, p6, [x12, x2, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x21, 0xc8, 0xfa, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d {za0v.d[w14, 1]}, p2, [x1, x26, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x8a, 0xfe, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d {za6v.d[w12, 1]}, p2, [x22, x30, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x22, 0xf5, 0xe1, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d {za1v.d[w15, 0]}, p5, [x9, x1, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x87, 0xa9, 0xeb, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d {za3v.d[w13, 1]}, p2, [x12, x11, lsl #3]"
diff --git a/tests/MC/AArch64/SME/st1h.s.yaml b/tests/MC/AArch64/SME/st1h.s.yaml
new file mode 100644
index 000000000..012fe6fc9
--- /dev/null
+++ b/tests/MC/AArch64/SME/st1h.s.yaml
@@ -0,0 +1,480 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x60, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h {za0h.h[w12, 0]}, p0, [x0, x0, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x45, 0x55, 0x75, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h {za0h.h[w14, 5]}, p5, [x10, x21, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0xa7, 0x6d, 0x68, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h {za0h.h[w15, 7]}, p3, [x13, x8, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0xef, 0x7f, 0x7f, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h {za1h.h[w15, 7]}, p7, [sp]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x0e, 0x70, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h {za0h.h[w12, 5]}, p3, [x17, x16, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x04, 0x7e, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h {za0h.h[w12, 1]}, p1, [x1, x30, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x68, 0x56, 0x74, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h {za1h.h[w14, 0]}, p5, [x19, x20, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x19, 0x62, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h {za0h.h[w12, 0]}, p6, [x12, x2, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x48, 0x7a, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h {za0h.h[w14, 1]}, p2, [x1, x26, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x0a, 0x7e, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h {za1h.h[w12, 5]}, p2, [x22, x30, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x22, 0x75, 0x61, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h {za0h.h[w15, 2]}, p5, [x9, x1, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x87, 0x29, 0x6b, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h {za0h.h[w13, 7]}, p2, [x12, x11, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x60, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h {za0h.h[w12, 0]}, p0, [x0, x0, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x45, 0x55, 0x75, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h {za0h.h[w14, 5]}, p5, [x10, x21, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0xa7, 0x6d, 0x68, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h {za0h.h[w15, 7]}, p3, [x13, x8, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0xef, 0x7f, 0x7f, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h {za1h.h[w15, 7]}, p7, [sp]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x0e, 0x70, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h {za0h.h[w12, 5]}, p3, [x17, x16, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x04, 0x7e, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h {za0h.h[w12, 1]}, p1, [x1, x30, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x68, 0x56, 0x74, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h {za1h.h[w14, 0]}, p5, [x19, x20, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x19, 0x62, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h {za0h.h[w12, 0]}, p6, [x12, x2, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x48, 0x7a, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h {za0h.h[w14, 1]}, p2, [x1, x26, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x0a, 0x7e, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h {za1h.h[w12, 5]}, p2, [x22, x30, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x22, 0x75, 0x61, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h {za0h.h[w15, 2]}, p5, [x9, x1, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x87, 0x29, 0x6b, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h {za0h.h[w13, 7]}, p2, [x12, x11, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x60, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h {za0v.h[w12, 0]}, p0, [x0, x0, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x45, 0xd5, 0x75, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h {za0v.h[w14, 5]}, p5, [x10, x21, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0xa7, 0xed, 0x68, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h {za0v.h[w15, 7]}, p3, [x13, x8, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0xef, 0xff, 0x7f, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h {za1v.h[w15, 7]}, p7, [sp]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x8e, 0x70, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h {za0v.h[w12, 5]}, p3, [x17, x16, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x84, 0x7e, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h {za0v.h[w12, 1]}, p1, [x1, x30, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x68, 0xd6, 0x74, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h {za1v.h[w14, 0]}, p5, [x19, x20, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x99, 0x62, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h {za0v.h[w12, 0]}, p6, [x12, x2, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x21, 0xc8, 0x7a, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h {za0v.h[w14, 1]}, p2, [x1, x26, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x8a, 0x7e, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h {za1v.h[w12, 5]}, p2, [x22, x30, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x22, 0xf5, 0x61, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h {za0v.h[w15, 2]}, p5, [x9, x1, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x87, 0xa9, 0x6b, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h {za0v.h[w13, 7]}, p2, [x12, x11, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x60, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h {za0v.h[w12, 0]}, p0, [x0, x0, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x45, 0xd5, 0x75, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h {za0v.h[w14, 5]}, p5, [x10, x21, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0xa7, 0xed, 0x68, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h {za0v.h[w15, 7]}, p3, [x13, x8, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0xef, 0xff, 0x7f, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h {za1v.h[w15, 7]}, p7, [sp]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x8e, 0x70, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h {za0v.h[w12, 5]}, p3, [x17, x16, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x84, 0x7e, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h {za0v.h[w12, 1]}, p1, [x1, x30, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x68, 0xd6, 0x74, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h {za1v.h[w14, 0]}, p5, [x19, x20, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x99, 0x62, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h {za0v.h[w12, 0]}, p6, [x12, x2, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x21, 0xc8, 0x7a, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h {za0v.h[w14, 1]}, p2, [x1, x26, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x8a, 0x7e, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h {za1v.h[w12, 5]}, p2, [x22, x30, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x22, 0xf5, 0x61, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h {za0v.h[w15, 2]}, p5, [x9, x1, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x87, 0xa9, 0x6b, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h {za0v.h[w13, 7]}, p2, [x12, x11, lsl #1]"
diff --git a/tests/MC/AArch64/SME/st1q.s.yaml b/tests/MC/AArch64/SME/st1q.s.yaml
new file mode 100644
index 000000000..ff8344c52
--- /dev/null
+++ b/tests/MC/AArch64/SME/st1q.s.yaml
@@ -0,0 +1,480 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0xe0, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1q {za0h.q[w12, 0]}, p0, [x0, x0, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0x45, 0x55, 0xf5, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1q {za5h.q[w14, 0]}, p5, [x10, x21, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0xa7, 0x6d, 0xe8, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1q {za7h.q[w15, 0]}, p3, [x13, x8, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0xef, 0x7f, 0xff, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1q {za15h.q[w15, 0]}, p7, [sp]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x0e, 0xf0, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1q {za5h.q[w12, 0]}, p3, [x17, x16, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x04, 0xfe, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1q {za1h.q[w12, 0]}, p1, [x1, x30, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0x68, 0x56, 0xf4, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1q {za8h.q[w14, 0]}, p5, [x19, x20, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x19, 0xe2, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1q {za0h.q[w12, 0]}, p6, [x12, x2, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x48, 0xfa, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1q {za1h.q[w14, 0]}, p2, [x1, x26, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x0a, 0xfe, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1q {za13h.q[w12, 0]}, p2, [x22, x30, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0x22, 0x75, 0xe1, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1q {za2h.q[w15, 0]}, p5, [x9, x1, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0x87, 0x29, 0xeb, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1q {za7h.q[w13, 0]}, p2, [x12, x11, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0xe0, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1q {za0h.q[w12, 0]}, p0, [x0, x0, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0x45, 0x55, 0xf5, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1q {za5h.q[w14, 0]}, p5, [x10, x21, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0xa7, 0x6d, 0xe8, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1q {za7h.q[w15, 0]}, p3, [x13, x8, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0xef, 0x7f, 0xff, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1q {za15h.q[w15, 0]}, p7, [sp]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x0e, 0xf0, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1q {za5h.q[w12, 0]}, p3, [x17, x16, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x04, 0xfe, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1q {za1h.q[w12, 0]}, p1, [x1, x30, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0x68, 0x56, 0xf4, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1q {za8h.q[w14, 0]}, p5, [x19, x20, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x19, 0xe2, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1q {za0h.q[w12, 0]}, p6, [x12, x2, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x48, 0xfa, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1q {za1h.q[w14, 0]}, p2, [x1, x26, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x0a, 0xfe, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1q {za13h.q[w12, 0]}, p2, [x22, x30, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0x22, 0x75, 0xe1, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1q {za2h.q[w15, 0]}, p5, [x9, x1, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0x87, 0x29, 0xeb, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1q {za7h.q[w13, 0]}, p2, [x12, x11, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xe0, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1q {za0v.q[w12, 0]}, p0, [x0, x0, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0x45, 0xd5, 0xf5, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1q {za5v.q[w14, 0]}, p5, [x10, x21, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0xa7, 0xed, 0xe8, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1q {za7v.q[w15, 0]}, p3, [x13, x8, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0xef, 0xff, 0xff, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1q {za15v.q[w15, 0]}, p7, [sp]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x8e, 0xf0, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1q {za5v.q[w12, 0]}, p3, [x17, x16, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x84, 0xfe, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1q {za1v.q[w12, 0]}, p1, [x1, x30, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0x68, 0xd6, 0xf4, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1q {za8v.q[w14, 0]}, p5, [x19, x20, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x99, 0xe2, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1q {za0v.q[w12, 0]}, p6, [x12, x2, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0x21, 0xc8, 0xfa, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1q {za1v.q[w14, 0]}, p2, [x1, x26, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x8a, 0xfe, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1q {za13v.q[w12, 0]}, p2, [x22, x30, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0x22, 0xf5, 0xe1, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1q {za2v.q[w15, 0]}, p5, [x9, x1, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0x87, 0xa9, 0xeb, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1q {za7v.q[w13, 0]}, p2, [x12, x11, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xe0, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1q {za0v.q[w12, 0]}, p0, [x0, x0, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0x45, 0xd5, 0xf5, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1q {za5v.q[w14, 0]}, p5, [x10, x21, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0xa7, 0xed, 0xe8, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1q {za7v.q[w15, 0]}, p3, [x13, x8, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0xef, 0xff, 0xff, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1q {za15v.q[w15, 0]}, p7, [sp]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x8e, 0xf0, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1q {za5v.q[w12, 0]}, p3, [x17, x16, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x84, 0xfe, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1q {za1v.q[w12, 0]}, p1, [x1, x30, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0x68, 0xd6, 0xf4, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1q {za8v.q[w14, 0]}, p5, [x19, x20, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x99, 0xe2, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1q {za0v.q[w12, 0]}, p6, [x12, x2, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0x21, 0xc8, 0xfa, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1q {za1v.q[w14, 0]}, p2, [x1, x26, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x8a, 0xfe, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1q {za13v.q[w12, 0]}, p2, [x22, x30, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0x22, 0xf5, 0xe1, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1q {za2v.q[w15, 0]}, p5, [x9, x1, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0x87, 0xa9, 0xeb, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1q {za7v.q[w13, 0]}, p2, [x12, x11, lsl #4]"
diff --git a/tests/MC/AArch64/SME/st1w.s.yaml b/tests/MC/AArch64/SME/st1w.s.yaml
new file mode 100644
index 000000000..75d270c02
--- /dev/null
+++ b/tests/MC/AArch64/SME/st1w.s.yaml
@@ -0,0 +1,480 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0xa0, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w {za0h.s[w12, 0]}, p0, [x0, x0, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x45, 0x55, 0xb5, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w {za1h.s[w14, 1]}, p5, [x10, x21, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0xa7, 0x6d, 0xa8, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w {za1h.s[w15, 3]}, p3, [x13, x8, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0xef, 0x7f, 0xbf, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w {za3h.s[w15, 3]}, p7, [sp]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x0e, 0xb0, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w {za1h.s[w12, 1]}, p3, [x17, x16, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x04, 0xbe, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w {za0h.s[w12, 1]}, p1, [x1, x30, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x68, 0x56, 0xb4, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w {za2h.s[w14, 0]}, p5, [x19, x20, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x19, 0xa2, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w {za0h.s[w12, 0]}, p6, [x12, x2, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x48, 0xba, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w {za0h.s[w14, 1]}, p2, [x1, x26, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x0a, 0xbe, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w {za3h.s[w12, 1]}, p2, [x22, x30, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x22, 0x75, 0xa1, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w {za0h.s[w15, 2]}, p5, [x9, x1, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x87, 0x29, 0xab, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w {za1h.s[w13, 3]}, p2, [x12, x11, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0xa0, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w {za0h.s[w12, 0]}, p0, [x0, x0, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x45, 0x55, 0xb5, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w {za1h.s[w14, 1]}, p5, [x10, x21, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0xa7, 0x6d, 0xa8, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w {za1h.s[w15, 3]}, p3, [x13, x8, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0xef, 0x7f, 0xbf, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w {za3h.s[w15, 3]}, p7, [sp]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x0e, 0xb0, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w {za1h.s[w12, 1]}, p3, [x17, x16, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x04, 0xbe, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w {za0h.s[w12, 1]}, p1, [x1, x30, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x68, 0x56, 0xb4, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w {za2h.s[w14, 0]}, p5, [x19, x20, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x19, 0xa2, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w {za0h.s[w12, 0]}, p6, [x12, x2, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x48, 0xba, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w {za0h.s[w14, 1]}, p2, [x1, x26, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x0a, 0xbe, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w {za3h.s[w12, 1]}, p2, [x22, x30, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x22, 0x75, 0xa1, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w {za0h.s[w15, 2]}, p5, [x9, x1, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x87, 0x29, 0xab, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w {za1h.s[w13, 3]}, p2, [x12, x11, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xa0, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w {za0v.s[w12, 0]}, p0, [x0, x0, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x45, 0xd5, 0xb5, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w {za1v.s[w14, 1]}, p5, [x10, x21, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0xa7, 0xed, 0xa8, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w {za1v.s[w15, 3]}, p3, [x13, x8, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0xef, 0xff, 0xbf, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w {za3v.s[w15, 3]}, p7, [sp]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x8e, 0xb0, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w {za1v.s[w12, 1]}, p3, [x17, x16, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x84, 0xbe, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w {za0v.s[w12, 1]}, p1, [x1, x30, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x68, 0xd6, 0xb4, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w {za2v.s[w14, 0]}, p5, [x19, x20, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x99, 0xa2, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w {za0v.s[w12, 0]}, p6, [x12, x2, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x21, 0xc8, 0xba, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w {za0v.s[w14, 1]}, p2, [x1, x26, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x8a, 0xbe, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w {za3v.s[w12, 1]}, p2, [x22, x30, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x22, 0xf5, 0xa1, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w {za0v.s[w15, 2]}, p5, [x9, x1, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x87, 0xa9, 0xab, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w {za1v.s[w13, 3]}, p2, [x12, x11, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xa0, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w {za0v.s[w12, 0]}, p0, [x0, x0, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x45, 0xd5, 0xb5, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w {za1v.s[w14, 1]}, p5, [x10, x21, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0xa7, 0xed, 0xa8, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w {za1v.s[w15, 3]}, p3, [x13, x8, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0xef, 0xff, 0xbf, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w {za3v.s[w15, 3]}, p7, [sp]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x8e, 0xb0, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w {za1v.s[w12, 1]}, p3, [x17, x16, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x84, 0xbe, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w {za0v.s[w12, 1]}, p1, [x1, x30, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x68, 0xd6, 0xb4, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w {za2v.s[w14, 0]}, p5, [x19, x20, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x99, 0xa2, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w {za0v.s[w12, 0]}, p6, [x12, x2, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x21, 0xc8, 0xba, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w {za0v.s[w14, 1]}, p2, [x1, x26, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x8a, 0xbe, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w {za3v.s[w12, 1]}, p2, [x22, x30, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x22, 0xf5, 0xa1, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w {za0v.s[w15, 2]}, p5, [x9, x1, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x87, 0xa9, 0xab, 0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w {za1v.s[w13, 3]}, p2, [x12, x11, lsl #2]"
diff --git a/tests/MC/AArch64/SME/str.s.yaml b/tests/MC/AArch64/SME/str.s.yaml
new file mode 100644
index 000000000..3652fbc11
--- /dev/null
+++ b/tests/MC/AArch64/SME/str.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x20, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "str za[w12, 0], [x0]"
+
+  -
+    input:
+      bytes: [ 0x45, 0x41, 0x20, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "str za[w14, 5], [x10, #5, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xa7, 0x61, 0x20, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "str za[w15, 7], [x13, #7, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xef, 0x63, 0x20, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "str za[w15, 15], [sp, #15, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x02, 0x20, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "str za[w12, 5], [x17, #5, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x00, 0x20, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "str za[w12, 1], [x1, #1, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x68, 0x42, 0x20, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "str za[w14, 8], [x19, #8, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x01, 0x20, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "str za[w12, 0], [x12]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x40, 0x20, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "str za[w14, 1], [x1, #1, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x02, 0x20, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "str za[w12, 13], [x22, #13, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x22, 0x61, 0x20, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "str za[w15, 2], [x9, #2, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x87, 0x21, 0x20, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "str za[w13, 7], [x12, #7, mul vl]"
diff --git a/tests/MC/AArch64/SME/streaming-mode-neon-bf16.s.yaml b/tests/MC/AArch64/SME/streaming-mode-neon-bf16.s.yaml
new file mode 100644
index 000000000..71fa19e0b
--- /dev/null
+++ b/tests/MC/AArch64/SME/streaming-mode-neon-bf16.s.yaml
@@ -0,0 +1,10 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x65, 0x40, 0x63, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "-neon", "+sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfcvt h5, s3"
diff --git a/tests/MC/AArch64/SME/streaming-mode-neon-fp16.s.yaml b/tests/MC/AArch64/SME/streaming-mode-neon-fp16.s.yaml
new file mode 100644
index 000000000..1847441e8
--- /dev/null
+++ b/tests/MC/AArch64/SME/streaming-mode-neon-fp16.s.yaml
@@ -0,0 +1,60 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x1c, 0x42, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmulx h0, h1, h2"
+
+  -
+    input:
+      bytes: [ 0x20, 0x3c, 0x42, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "frecps h0, h1, h2"
+
+  -
+    input:
+      bytes: [ 0x20, 0x3c, 0xc2, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "frsqrts h0, h1, h2"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd8, 0xf9, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "frecpe h0, h1"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf8, 0xf9, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "frecpx h0, h1"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd8, 0xf9, 0x7e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "frsqrte h0, h1"
diff --git a/tests/MC/AArch64/SME/streaming-mode-neon.s.yaml b/tests/MC/AArch64/SME/streaming-mode-neon.s.yaml
new file mode 100644
index 000000000..f6addaab3
--- /dev/null
+++ b/tests/MC/AArch64/SME/streaming-mode-neon.s.yaml
@@ -0,0 +1,230 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0xdc, 0x22, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "-neon", "+sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmulx s0, s1, s2"
+
+  -
+    input:
+      bytes: [ 0x20, 0xdc, 0x62, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "-neon", "+sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmulx d0, d1, d2"
+
+  -
+    input:
+      bytes: [ 0x20, 0xfc, 0x22, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "-neon", "+sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "frecps s0, s1, s2"
+
+  -
+    input:
+      bytes: [ 0x20, 0xfc, 0x62, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "-neon", "+sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "frecps d0, d1, d2"
+
+  -
+    input:
+      bytes: [ 0x20, 0xfc, 0xa2, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "-neon", "+sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "frsqrts s0, s1, s2"
+
+  -
+    input:
+      bytes: [ 0x20, 0xfc, 0xe2, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "-neon", "+sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "frsqrts d0, d1, d2"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd8, 0xa1, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "-neon", "+sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "frecpe s0, s1"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd8, 0xe1, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "-neon", "+sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "frecpe d0, d1"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf8, 0xa1, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "-neon", "+sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "frecpx s0, s1"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf8, 0xe1, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "-neon", "+sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "frecpx d0, d1"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd8, 0xa1, 0x7e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "-neon", "+sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "frsqrte s0, s1"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd8, 0xe1, 0x7e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "-neon", "+sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "frsqrte d0, d1"
+
+  -
+    input:
+      bytes: [ 0x00, 0x2c, 0x01, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "-neon", "+sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smov w0, v0.b[0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x2c, 0x01, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "-neon", "+sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smov x0, v0.b[0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x2c, 0x02, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "-neon", "+sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smov w0, v0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x2c, 0x02, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "-neon", "+sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smov x0, v0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x2c, 0x04, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "-neon", "+sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smov x0, v0.s[0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x3c, 0x01, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "-neon", "+sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "umov w0, v0.b[0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x3c, 0x02, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "-neon", "+sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "umov w0, v0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x3c, 0x04, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "-neon", "+sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov w0, v0.s[0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x3c, 0x08, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "-neon", "+sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov x0, v0.d[0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x3c, 0x04, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "-neon", "+sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov w0, v0.s[0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x3c, 0x08, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "-neon", "+sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov x0, v0.d[0]"
diff --git a/tests/MC/AArch64/SME/sumopa-32.s.yaml b/tests/MC/AArch64/SME/sumopa-32.s.yaml
new file mode 100644
index 000000000..52c5a05e6
--- /dev/null
+++ b/tests/MC/AArch64/SME/sumopa-32.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0xa0, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumopa za0.s, p0/m, p0/m, z0.b, z0.b"
+
+  -
+    input:
+      bytes: [ 0x41, 0x55, 0xb5, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumopa za1.s, p5/m, p2/m, z10.b, z21.b"
+
+  -
+    input:
+      bytes: [ 0xa3, 0xed, 0xa8, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumopa za3.s, p3/m, p7/m, z13.b, z8.b"
+
+  -
+    input:
+      bytes: [ 0xe3, 0xff, 0xbf, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumopa za3.s, p7/m, p7/m, z31.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0x21, 0x0e, 0xb0, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumopa za1.s, p3/m, p0/m, z17.b, z16.b"
+
+  -
+    input:
+      bytes: [ 0x21, 0x84, 0xbe, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumopa za1.s, p1/m, p4/m, z1.b, z30.b"
+
+  -
+    input:
+      bytes: [ 0x60, 0x56, 0xb4, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumopa za0.s, p5/m, p2/m, z19.b, z20.b"
+
+  -
+    input:
+      bytes: [ 0x80, 0x19, 0xa2, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumopa za0.s, p6/m, p0/m, z12.b, z2.b"
+
+  -
+    input:
+      bytes: [ 0x21, 0xc8, 0xba, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumopa za1.s, p2/m, p6/m, z1.b, z26.b"
+
+  -
+    input:
+      bytes: [ 0xc1, 0x0a, 0xbe, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumopa za1.s, p2/m, p0/m, z22.b, z30.b"
+
+  -
+    input:
+      bytes: [ 0x22, 0xf5, 0xa1, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumopa za2.s, p5/m, p7/m, z9.b, z1.b"
+
+  -
+    input:
+      bytes: [ 0x83, 0xa9, 0xab, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumopa za3.s, p2/m, p5/m, z12.b, z11.b"
diff --git a/tests/MC/AArch64/SME/sumopa-64.s.yaml b/tests/MC/AArch64/SME/sumopa-64.s.yaml
new file mode 100644
index 000000000..5b69c39e4
--- /dev/null
+++ b/tests/MC/AArch64/SME/sumopa-64.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0xe0, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumopa za0.d, p0/m, p0/m, z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x45, 0x55, 0xf5, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumopa za5.d, p5/m, p2/m, z10.h, z21.h"
+
+  -
+    input:
+      bytes: [ 0xa7, 0xed, 0xe8, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumopa za7.d, p3/m, p7/m, z13.h, z8.h"
+
+  -
+    input:
+      bytes: [ 0xe7, 0xff, 0xff, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumopa za7.d, p7/m, p7/m, z31.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x25, 0x0e, 0xf0, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumopa za5.d, p3/m, p0/m, z17.h, z16.h"
+
+  -
+    input:
+      bytes: [ 0x21, 0x84, 0xfe, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumopa za1.d, p1/m, p4/m, z1.h, z30.h"
+
+  -
+    input:
+      bytes: [ 0x60, 0x56, 0xf4, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumopa za0.d, p5/m, p2/m, z19.h, z20.h"
+
+  -
+    input:
+      bytes: [ 0x80, 0x19, 0xe2, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumopa za0.d, p6/m, p0/m, z12.h, z2.h"
+
+  -
+    input:
+      bytes: [ 0x21, 0xc8, 0xfa, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumopa za1.d, p2/m, p6/m, z1.h, z26.h"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x0a, 0xfe, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumopa za5.d, p2/m, p0/m, z22.h, z30.h"
+
+  -
+    input:
+      bytes: [ 0x22, 0xf5, 0xe1, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumopa za2.d, p5/m, p7/m, z9.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0x87, 0xa9, 0xeb, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumopa za7.d, p2/m, p5/m, z12.h, z11.h"
diff --git a/tests/MC/AArch64/SME/sumops-32.s.yaml b/tests/MC/AArch64/SME/sumops-32.s.yaml
new file mode 100644
index 000000000..bf4019d86
--- /dev/null
+++ b/tests/MC/AArch64/SME/sumops-32.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x10, 0x00, 0xa0, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumops za0.s, p0/m, p0/m, z0.b, z0.b"
+
+  -
+    input:
+      bytes: [ 0x51, 0x55, 0xb5, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumops za1.s, p5/m, p2/m, z10.b, z21.b"
+
+  -
+    input:
+      bytes: [ 0xb3, 0xed, 0xa8, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumops za3.s, p3/m, p7/m, z13.b, z8.b"
+
+  -
+    input:
+      bytes: [ 0xf3, 0xff, 0xbf, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumops za3.s, p7/m, p7/m, z31.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0x31, 0x0e, 0xb0, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumops za1.s, p3/m, p0/m, z17.b, z16.b"
+
+  -
+    input:
+      bytes: [ 0x31, 0x84, 0xbe, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumops za1.s, p1/m, p4/m, z1.b, z30.b"
+
+  -
+    input:
+      bytes: [ 0x70, 0x56, 0xb4, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumops za0.s, p5/m, p2/m, z19.b, z20.b"
+
+  -
+    input:
+      bytes: [ 0x90, 0x19, 0xa2, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumops za0.s, p6/m, p0/m, z12.b, z2.b"
+
+  -
+    input:
+      bytes: [ 0x31, 0xc8, 0xba, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumops za1.s, p2/m, p6/m, z1.b, z26.b"
+
+  -
+    input:
+      bytes: [ 0xd1, 0x0a, 0xbe, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumops za1.s, p2/m, p0/m, z22.b, z30.b"
+
+  -
+    input:
+      bytes: [ 0x32, 0xf5, 0xa1, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumops za2.s, p5/m, p7/m, z9.b, z1.b"
+
+  -
+    input:
+      bytes: [ 0x93, 0xa9, 0xab, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumops za3.s, p2/m, p5/m, z12.b, z11.b"
diff --git a/tests/MC/AArch64/SME/sumops-64.s.yaml b/tests/MC/AArch64/SME/sumops-64.s.yaml
new file mode 100644
index 000000000..e4af650b6
--- /dev/null
+++ b/tests/MC/AArch64/SME/sumops-64.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x10, 0x00, 0xe0, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumops za0.d, p0/m, p0/m, z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x55, 0x55, 0xf5, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumops za5.d, p5/m, p2/m, z10.h, z21.h"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0xe8, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumops za7.d, p3/m, p7/m, z13.h, z8.h"
+
+  -
+    input:
+      bytes: [ 0xf7, 0xff, 0xff, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumops za7.d, p7/m, p7/m, z31.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x35, 0x0e, 0xf0, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumops za5.d, p3/m, p0/m, z17.h, z16.h"
+
+  -
+    input:
+      bytes: [ 0x31, 0x84, 0xfe, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumops za1.d, p1/m, p4/m, z1.h, z30.h"
+
+  -
+    input:
+      bytes: [ 0x70, 0x56, 0xf4, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumops za0.d, p5/m, p2/m, z19.h, z20.h"
+
+  -
+    input:
+      bytes: [ 0x90, 0x19, 0xe2, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumops za0.d, p6/m, p0/m, z12.h, z2.h"
+
+  -
+    input:
+      bytes: [ 0x31, 0xc8, 0xfa, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumops za1.d, p2/m, p6/m, z1.h, z26.h"
+
+  -
+    input:
+      bytes: [ 0xd5, 0x0a, 0xfe, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumops za5.d, p2/m, p0/m, z22.h, z30.h"
+
+  -
+    input:
+      bytes: [ 0x32, 0xf5, 0xe1, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumops za2.d, p5/m, p7/m, z9.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0x97, 0xa9, 0xeb, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumops za7.d, p2/m, p5/m, z12.h, z11.h"
diff --git a/tests/MC/AArch64/SME/system-regs-mpam.s.yaml b/tests/MC/AArch64/SME/system-regs-mpam.s.yaml
new file mode 100644
index 000000000..0310094cf
--- /dev/null
+++ b/tests/MC/AArch64/SME/system-regs-mpam.s.yaml
@@ -0,0 +1,20 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x63, 0xa5, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme", "+mpam" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, MPAMSM_EL1"
+
+  -
+    input:
+      bytes: [ 0x63, 0xa5, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme", "+mpam" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr MPAMSM_EL1, x3"
diff --git a/tests/MC/AArch64/SME/system-regs.s.yaml b/tests/MC/AArch64/SME/system-regs.s.yaml
new file mode 100644
index 000000000..23e8847e6
--- /dev/null
+++ b/tests/MC/AArch64/SME/system-regs.s.yaml
@@ -0,0 +1,240 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xa3, 0x04, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, ID_AA64SMFR0_EL1"
+
+  -
+    input:
+      bytes: [ 0xc3, 0x12, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SMCR_EL1"
+
+  -
+    input:
+      bytes: [ 0xc3, 0x12, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SMCR_EL2"
+
+  -
+    input:
+      bytes: [ 0xc3, 0x12, 0x3e, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SMCR_EL3"
+
+  -
+    input:
+      bytes: [ 0xc3, 0x12, 0x3d, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SMCR_EL12"
+
+  -
+    input:
+      bytes: [ 0x43, 0x42, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SVCR"
+
+  -
+    input:
+      bytes: [ 0x83, 0x12, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SMPRI_EL1"
+
+  -
+    input:
+      bytes: [ 0xa3, 0x12, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SMPRIMAP_EL2"
+
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0x39, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SMIDR_EL1"
+
+  -
+    input:
+      bytes: [ 0xa3, 0xd0, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, TPIDR2_EL0"
+
+  -
+    input:
+      bytes: [ 0xc3, 0x12, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SMCR_EL1, x3"
+
+  -
+    input:
+      bytes: [ 0xc3, 0x12, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SMCR_EL2, x3"
+
+  -
+    input:
+      bytes: [ 0xc3, 0x12, 0x1e, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SMCR_EL3, x3"
+
+  -
+    input:
+      bytes: [ 0xc3, 0x12, 0x1d, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SMCR_EL12, x3"
+
+  -
+    input:
+      bytes: [ 0x43, 0x42, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SVCR, x3"
+
+  -
+    input:
+      bytes: [ 0x83, 0x12, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SMPRI_EL1, x3"
+
+  -
+    input:
+      bytes: [ 0xa3, 0x12, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SMPRIMAP_EL2, x3"
+
+  -
+    input:
+      bytes: [ 0x7f, 0x42, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smstop sm"
+
+  -
+    input:
+      bytes: [ 0x7f, 0x43, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smstart sm"
+
+  -
+    input:
+      bytes: [ 0x7f, 0x44, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smstop za"
+
+  -
+    input:
+      bytes: [ 0x7f, 0x45, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smstart za"
+
+  -
+    input:
+      bytes: [ 0x7f, 0x46, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smstop"
+
+  -
+    input:
+      bytes: [ 0x7f, 0x47, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smstart"
+
+  -
+    input:
+      bytes: [ 0xa3, 0xd0, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TPIDR2_EL0, x3"
diff --git a/tests/MC/AArch64/SME/uclamp.s.yaml b/tests/MC/AArch64/SME/uclamp.s.yaml
new file mode 100644
index 000000000..629c08ce6
--- /dev/null
+++ b/tests/MC/AArch64/SME/uclamp.s.yaml
@@ -0,0 +1,240 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xc4, 0x00, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uclamp z0.b, z0.b, z0.b"
+
+  -
+    input:
+      bytes: [ 0x55, 0xc5, 0x15, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uclamp z21.b, z10.b, z21.b"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xc5, 0x08, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uclamp z23.b, z13.b, z8.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0xc7, 0x1f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uclamp z31.b, z31.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc4, 0x40, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uclamp z0.h, z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x55, 0xc5, 0x55, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uclamp z21.h, z10.h, z21.h"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xc5, 0x48, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uclamp z23.h, z13.h, z8.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0xc7, 0x5f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uclamp z31.h, z31.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc4, 0x80, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uclamp z0.s, z0.s, z0.s"
+
+  -
+    input:
+      bytes: [ 0x55, 0xc5, 0x95, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uclamp z21.s, z10.s, z21.s"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xc5, 0x88, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uclamp z23.s, z13.s, z8.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0xc7, 0x9f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uclamp z31.s, z31.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc4, 0xc0, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uclamp z0.d, z0.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0x55, 0xc5, 0xd5, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uclamp z21.d, z10.d, z21.d"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xc5, 0xc8, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uclamp z23.d, z13.d, z8.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0xc7, 0xdf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uclamp z31.d, z31.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0x77, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z23, z27"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xc5, 0x08, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uclamp z23.b, z13.b, z8.b"
+
+  -
+    input:
+      bytes: [ 0x77, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z23, z27"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xc5, 0x48, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uclamp z23.h, z13.h, z8.h"
+
+  -
+    input:
+      bytes: [ 0x77, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z23, z27"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xc5, 0x88, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uclamp z23.s, z13.s, z8.s"
+
+  -
+    input:
+      bytes: [ 0x77, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z23, z27"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xc5, 0xc8, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uclamp z23.d, z13.d, z8.d"
diff --git a/tests/MC/AArch64/SME/umopa-32.s.yaml b/tests/MC/AArch64/SME/umopa-32.s.yaml
new file mode 100644
index 000000000..8bc7af7bd
--- /dev/null
+++ b/tests/MC/AArch64/SME/umopa-32.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0xa0, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "umopa za0.s, p0/m, p0/m, z0.b, z0.b"
+
+  -
+    input:
+      bytes: [ 0x41, 0x55, 0xb5, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "umopa za1.s, p5/m, p2/m, z10.b, z21.b"
+
+  -
+    input:
+      bytes: [ 0xa3, 0xed, 0xa8, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "umopa za3.s, p3/m, p7/m, z13.b, z8.b"
+
+  -
+    input:
+      bytes: [ 0xe3, 0xff, 0xbf, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "umopa za3.s, p7/m, p7/m, z31.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0x21, 0x0e, 0xb0, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "umopa za1.s, p3/m, p0/m, z17.b, z16.b"
+
+  -
+    input:
+      bytes: [ 0x21, 0x84, 0xbe, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "umopa za1.s, p1/m, p4/m, z1.b, z30.b"
+
+  -
+    input:
+      bytes: [ 0x60, 0x56, 0xb4, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "umopa za0.s, p5/m, p2/m, z19.b, z20.b"
+
+  -
+    input:
+      bytes: [ 0x80, 0x19, 0xa2, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "umopa za0.s, p6/m, p0/m, z12.b, z2.b"
+
+  -
+    input:
+      bytes: [ 0x21, 0xc8, 0xba, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "umopa za1.s, p2/m, p6/m, z1.b, z26.b"
+
+  -
+    input:
+      bytes: [ 0xc1, 0x0a, 0xbe, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "umopa za1.s, p2/m, p0/m, z22.b, z30.b"
+
+  -
+    input:
+      bytes: [ 0x22, 0xf5, 0xa1, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "umopa za2.s, p5/m, p7/m, z9.b, z1.b"
+
+  -
+    input:
+      bytes: [ 0x83, 0xa9, 0xab, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "umopa za3.s, p2/m, p5/m, z12.b, z11.b"
diff --git a/tests/MC/AArch64/SME/umopa-64.s.yaml b/tests/MC/AArch64/SME/umopa-64.s.yaml
new file mode 100644
index 000000000..dd12efabc
--- /dev/null
+++ b/tests/MC/AArch64/SME/umopa-64.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0xe0, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umopa za0.d, p0/m, p0/m, z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x45, 0x55, 0xf5, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umopa za5.d, p5/m, p2/m, z10.h, z21.h"
+
+  -
+    input:
+      bytes: [ 0xa7, 0xed, 0xe8, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umopa za7.d, p3/m, p7/m, z13.h, z8.h"
+
+  -
+    input:
+      bytes: [ 0xe7, 0xff, 0xff, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umopa za7.d, p7/m, p7/m, z31.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x25, 0x0e, 0xf0, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umopa za5.d, p3/m, p0/m, z17.h, z16.h"
+
+  -
+    input:
+      bytes: [ 0x21, 0x84, 0xfe, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umopa za1.d, p1/m, p4/m, z1.h, z30.h"
+
+  -
+    input:
+      bytes: [ 0x60, 0x56, 0xf4, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umopa za0.d, p5/m, p2/m, z19.h, z20.h"
+
+  -
+    input:
+      bytes: [ 0x80, 0x19, 0xe2, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umopa za0.d, p6/m, p0/m, z12.h, z2.h"
+
+  -
+    input:
+      bytes: [ 0x21, 0xc8, 0xfa, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umopa za1.d, p2/m, p6/m, z1.h, z26.h"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x0a, 0xfe, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umopa za5.d, p2/m, p0/m, z22.h, z30.h"
+
+  -
+    input:
+      bytes: [ 0x22, 0xf5, 0xe1, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umopa za2.d, p5/m, p7/m, z9.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0x87, 0xa9, 0xeb, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umopa za7.d, p2/m, p5/m, z12.h, z11.h"
diff --git a/tests/MC/AArch64/SME/umops-32.s.yaml b/tests/MC/AArch64/SME/umops-32.s.yaml
new file mode 100644
index 000000000..d92c8230f
--- /dev/null
+++ b/tests/MC/AArch64/SME/umops-32.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x10, 0x00, 0xa0, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "umops za0.s, p0/m, p0/m, z0.b, z0.b"
+
+  -
+    input:
+      bytes: [ 0x51, 0x55, 0xb5, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "umops za1.s, p5/m, p2/m, z10.b, z21.b"
+
+  -
+    input:
+      bytes: [ 0xb3, 0xed, 0xa8, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "umops za3.s, p3/m, p7/m, z13.b, z8.b"
+
+  -
+    input:
+      bytes: [ 0xf3, 0xff, 0xbf, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "umops za3.s, p7/m, p7/m, z31.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0x31, 0x0e, 0xb0, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "umops za1.s, p3/m, p0/m, z17.b, z16.b"
+
+  -
+    input:
+      bytes: [ 0x31, 0x84, 0xbe, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "umops za1.s, p1/m, p4/m, z1.b, z30.b"
+
+  -
+    input:
+      bytes: [ 0x70, 0x56, 0xb4, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "umops za0.s, p5/m, p2/m, z19.b, z20.b"
+
+  -
+    input:
+      bytes: [ 0x90, 0x19, 0xa2, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "umops za0.s, p6/m, p0/m, z12.b, z2.b"
+
+  -
+    input:
+      bytes: [ 0x31, 0xc8, 0xba, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "umops za1.s, p2/m, p6/m, z1.b, z26.b"
+
+  -
+    input:
+      bytes: [ 0xd1, 0x0a, 0xbe, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "umops za1.s, p2/m, p0/m, z22.b, z30.b"
+
+  -
+    input:
+      bytes: [ 0x32, 0xf5, 0xa1, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "umops za2.s, p5/m, p7/m, z9.b, z1.b"
+
+  -
+    input:
+      bytes: [ 0x93, 0xa9, 0xab, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "umops za3.s, p2/m, p5/m, z12.b, z11.b"
diff --git a/tests/MC/AArch64/SME/umops-64.s.yaml b/tests/MC/AArch64/SME/umops-64.s.yaml
new file mode 100644
index 000000000..347449d0c
--- /dev/null
+++ b/tests/MC/AArch64/SME/umops-64.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x10, 0x00, 0xe0, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umops za0.d, p0/m, p0/m, z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x55, 0x55, 0xf5, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umops za5.d, p5/m, p2/m, z10.h, z21.h"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0xe8, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umops za7.d, p3/m, p7/m, z13.h, z8.h"
+
+  -
+    input:
+      bytes: [ 0xf7, 0xff, 0xff, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umops za7.d, p7/m, p7/m, z31.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x35, 0x0e, 0xf0, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umops za5.d, p3/m, p0/m, z17.h, z16.h"
+
+  -
+    input:
+      bytes: [ 0x31, 0x84, 0xfe, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umops za1.d, p1/m, p4/m, z1.h, z30.h"
+
+  -
+    input:
+      bytes: [ 0x70, 0x56, 0xf4, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umops za0.d, p5/m, p2/m, z19.h, z20.h"
+
+  -
+    input:
+      bytes: [ 0x90, 0x19, 0xe2, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umops za0.d, p6/m, p0/m, z12.h, z2.h"
+
+  -
+    input:
+      bytes: [ 0x31, 0xc8, 0xfa, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umops za1.d, p2/m, p6/m, z1.h, z26.h"
+
+  -
+    input:
+      bytes: [ 0xd5, 0x0a, 0xfe, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umops za5.d, p2/m, p0/m, z22.h, z30.h"
+
+  -
+    input:
+      bytes: [ 0x32, 0xf5, 0xe1, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umops za2.d, p5/m, p7/m, z9.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0x97, 0xa9, 0xeb, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umops za7.d, p2/m, p5/m, z12.h, z11.h"
diff --git a/tests/MC/AArch64/SME/usmopa-32.s.yaml b/tests/MC/AArch64/SME/usmopa-32.s.yaml
new file mode 100644
index 000000000..62a3437be
--- /dev/null
+++ b/tests/MC/AArch64/SME/usmopa-32.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x80, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmopa za0.s, p0/m, p0/m, z0.b, z0.b"
+
+  -
+    input:
+      bytes: [ 0x41, 0x55, 0x95, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmopa za1.s, p5/m, p2/m, z10.b, z21.b"
+
+  -
+    input:
+      bytes: [ 0xa3, 0xed, 0x88, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmopa za3.s, p3/m, p7/m, z13.b, z8.b"
+
+  -
+    input:
+      bytes: [ 0xe3, 0xff, 0x9f, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmopa za3.s, p7/m, p7/m, z31.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0x21, 0x0e, 0x90, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmopa za1.s, p3/m, p0/m, z17.b, z16.b"
+
+  -
+    input:
+      bytes: [ 0x21, 0x84, 0x9e, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmopa za1.s, p1/m, p4/m, z1.b, z30.b"
+
+  -
+    input:
+      bytes: [ 0x60, 0x56, 0x94, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmopa za0.s, p5/m, p2/m, z19.b, z20.b"
+
+  -
+    input:
+      bytes: [ 0x80, 0x19, 0x82, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmopa za0.s, p6/m, p0/m, z12.b, z2.b"
+
+  -
+    input:
+      bytes: [ 0x21, 0xc8, 0x9a, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmopa za1.s, p2/m, p6/m, z1.b, z26.b"
+
+  -
+    input:
+      bytes: [ 0xc1, 0x0a, 0x9e, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmopa za1.s, p2/m, p0/m, z22.b, z30.b"
+
+  -
+    input:
+      bytes: [ 0x22, 0xf5, 0x81, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmopa za2.s, p5/m, p7/m, z9.b, z1.b"
+
+  -
+    input:
+      bytes: [ 0x83, 0xa9, 0x8b, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmopa za3.s, p2/m, p5/m, z12.b, z11.b"
diff --git a/tests/MC/AArch64/SME/usmopa-64.s.yaml b/tests/MC/AArch64/SME/usmopa-64.s.yaml
new file mode 100644
index 000000000..0e8f364b6
--- /dev/null
+++ b/tests/MC/AArch64/SME/usmopa-64.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0xc0, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmopa za0.d, p0/m, p0/m, z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x45, 0x55, 0xd5, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmopa za5.d, p5/m, p2/m, z10.h, z21.h"
+
+  -
+    input:
+      bytes: [ 0xa7, 0xed, 0xc8, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmopa za7.d, p3/m, p7/m, z13.h, z8.h"
+
+  -
+    input:
+      bytes: [ 0xe7, 0xff, 0xdf, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmopa za7.d, p7/m, p7/m, z31.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x25, 0x0e, 0xd0, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmopa za5.d, p3/m, p0/m, z17.h, z16.h"
+
+  -
+    input:
+      bytes: [ 0x21, 0x84, 0xde, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmopa za1.d, p1/m, p4/m, z1.h, z30.h"
+
+  -
+    input:
+      bytes: [ 0x60, 0x56, 0xd4, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmopa za0.d, p5/m, p2/m, z19.h, z20.h"
+
+  -
+    input:
+      bytes: [ 0x80, 0x19, 0xc2, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmopa za0.d, p6/m, p0/m, z12.h, z2.h"
+
+  -
+    input:
+      bytes: [ 0x21, 0xc8, 0xda, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmopa za1.d, p2/m, p6/m, z1.h, z26.h"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x0a, 0xde, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmopa za5.d, p2/m, p0/m, z22.h, z30.h"
+
+  -
+    input:
+      bytes: [ 0x22, 0xf5, 0xc1, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmopa za2.d, p5/m, p7/m, z9.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0x87, 0xa9, 0xcb, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmopa za7.d, p2/m, p5/m, z12.h, z11.h"
diff --git a/tests/MC/AArch64/SME/usmops-32.s.yaml b/tests/MC/AArch64/SME/usmops-32.s.yaml
new file mode 100644
index 000000000..0d52f8bef
--- /dev/null
+++ b/tests/MC/AArch64/SME/usmops-32.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x10, 0x00, 0x80, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmops za0.s, p0/m, p0/m, z0.b, z0.b"
+
+  -
+    input:
+      bytes: [ 0x51, 0x55, 0x95, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmops za1.s, p5/m, p2/m, z10.b, z21.b"
+
+  -
+    input:
+      bytes: [ 0xb3, 0xed, 0x88, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmops za3.s, p3/m, p7/m, z13.b, z8.b"
+
+  -
+    input:
+      bytes: [ 0xf3, 0xff, 0x9f, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmops za3.s, p7/m, p7/m, z31.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0x31, 0x0e, 0x90, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmops za1.s, p3/m, p0/m, z17.b, z16.b"
+
+  -
+    input:
+      bytes: [ 0x31, 0x84, 0x9e, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmops za1.s, p1/m, p4/m, z1.b, z30.b"
+
+  -
+    input:
+      bytes: [ 0x70, 0x56, 0x94, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmops za0.s, p5/m, p2/m, z19.b, z20.b"
+
+  -
+    input:
+      bytes: [ 0x90, 0x19, 0x82, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmops za0.s, p6/m, p0/m, z12.b, z2.b"
+
+  -
+    input:
+      bytes: [ 0x31, 0xc8, 0x9a, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmops za1.s, p2/m, p6/m, z1.b, z26.b"
+
+  -
+    input:
+      bytes: [ 0xd1, 0x0a, 0x9e, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmops za1.s, p2/m, p0/m, z22.b, z30.b"
+
+  -
+    input:
+      bytes: [ 0x32, 0xf5, 0x81, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmops za2.s, p5/m, p7/m, z9.b, z1.b"
+
+  -
+    input:
+      bytes: [ 0x93, 0xa9, 0x8b, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmops za3.s, p2/m, p5/m, z12.b, z11.b"
diff --git a/tests/MC/AArch64/SME/usmops-64.s.yaml b/tests/MC/AArch64/SME/usmops-64.s.yaml
new file mode 100644
index 000000000..e6cc96e0b
--- /dev/null
+++ b/tests/MC/AArch64/SME/usmops-64.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x10, 0x00, 0xc0, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmops za0.d, p0/m, p0/m, z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x55, 0x55, 0xd5, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmops za5.d, p5/m, p2/m, z10.h, z21.h"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0xc8, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmops za7.d, p3/m, p7/m, z13.h, z8.h"
+
+  -
+    input:
+      bytes: [ 0xf7, 0xff, 0xdf, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmops za7.d, p7/m, p7/m, z31.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x35, 0x0e, 0xd0, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmops za5.d, p3/m, p0/m, z17.h, z16.h"
+
+  -
+    input:
+      bytes: [ 0x31, 0x84, 0xde, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmops za1.d, p1/m, p4/m, z1.h, z30.h"
+
+  -
+    input:
+      bytes: [ 0x70, 0x56, 0xd4, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmops za0.d, p5/m, p2/m, z19.h, z20.h"
+
+  -
+    input:
+      bytes: [ 0x90, 0x19, 0xc2, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmops za0.d, p6/m, p0/m, z12.h, z2.h"
+
+  -
+    input:
+      bytes: [ 0x31, 0xc8, 0xda, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmops za1.d, p2/m, p6/m, z1.h, z26.h"
+
+  -
+    input:
+      bytes: [ 0xd5, 0x0a, 0xde, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmops za5.d, p2/m, p0/m, z22.h, z30.h"
+
+  -
+    input:
+      bytes: [ 0x32, 0xf5, 0xc1, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmops za2.d, p5/m, p7/m, z9.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0x97, 0xa9, 0xcb, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmops za7.d, p2/m, p5/m, z12.h, z11.h"
diff --git a/tests/MC/AArch64/SME/zero.s.yaml b/tests/MC/AArch64/SME/zero.s.yaml
new file mode 100644
index 000000000..299fe3c39
--- /dev/null
+++ b/tests/MC/AArch64/SME/zero.s.yaml
@@ -0,0 +1,390 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x08, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "zero {}"
+
+  -
+    input:
+      bytes: [ 0x55, 0x00, 0x08, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "zero {za0.h}"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x00, 0x08, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "zero {za0.d, za1.d, za2.d, za4.d, za5.d, za7.d}"
+
+  -
+    input:
+      bytes: [ 0xff, 0x00, 0x08, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "zero {za}"
+
+  -
+    input:
+      bytes: [ 0xff, 0x00, 0x08, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "zero {za}"
+
+  -
+    input:
+      bytes: [ 0xff, 0x00, 0x08, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "zero {za}"
+
+  -
+    input:
+      bytes: [ 0x55, 0x00, 0x08, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "zero {za0.h}"
+
+  -
+    input:
+      bytes: [ 0xaa, 0x00, 0x08, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "zero {za1.h}"
+
+  -
+    input:
+      bytes: [ 0xff, 0x00, 0x08, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "zero {za}"
+
+  -
+    input:
+      bytes: [ 0x11, 0x00, 0x08, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "zero {za0.s}"
+
+  -
+    input:
+      bytes: [ 0x22, 0x00, 0x08, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "zero {za1.s}"
+
+  -
+    input:
+      bytes: [ 0x44, 0x00, 0x08, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "zero {za2.s}"
+
+  -
+    input:
+      bytes: [ 0x88, 0x00, 0x08, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "zero {za3.s}"
+
+  -
+    input:
+      bytes: [ 0x33, 0x00, 0x08, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "zero {za0.s,za1.s}"
+
+  -
+    input:
+      bytes: [ 0x55, 0x00, 0x08, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "zero {za0.h}"
+
+  -
+    input:
+      bytes: [ 0x99, 0x00, 0x08, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "zero {za0.s,za3.s}"
+
+  -
+    input:
+      bytes: [ 0x66, 0x00, 0x08, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "zero {za1.s,za2.s}"
+
+  -
+    input:
+      bytes: [ 0xaa, 0x00, 0x08, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "zero {za1.h}"
+
+  -
+    input:
+      bytes: [ 0xcc, 0x00, 0x08, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "zero {za2.s,za3.s}"
+
+  -
+    input:
+      bytes: [ 0x77, 0x00, 0x08, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "zero {za0.s,za1.s,za2.s}"
+
+  -
+    input:
+      bytes: [ 0xbb, 0x00, 0x08, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "zero {za0.s,za1.s,za3.s}"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x00, 0x08, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "zero {za0.s,za2.s,za3.s}"
+
+  -
+    input:
+      bytes: [ 0xee, 0x00, 0x08, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "zero {za1.s,za2.s,za3.s}"
+
+  -
+    input:
+      bytes: [ 0xff, 0x00, 0x08, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "zero {za}"
+
+  -
+    input:
+      bytes: [ 0xff, 0x00, 0x08, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "zero {za}"
+
+  -
+    input:
+      bytes: [ 0x55, 0x00, 0x08, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "zero {za0.h}"
+
+  -
+    input:
+      bytes: [ 0xaa, 0x00, 0x08, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "zero {za1.h}"
+
+  -
+    input:
+      bytes: [ 0x11, 0x00, 0x08, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "zero {za0.s}"
+
+  -
+    input:
+      bytes: [ 0x22, 0x00, 0x08, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "zero {za1.s}"
+
+  -
+    input:
+      bytes: [ 0x44, 0x00, 0x08, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "zero {za2.s}"
+
+  -
+    input:
+      bytes: [ 0x88, 0x00, 0x08, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "zero {za3.s}"
+
+  -
+    input:
+      bytes: [ 0x33, 0x00, 0x08, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "zero {za0.s,za1.s}"
+
+  -
+    input:
+      bytes: [ 0x99, 0x00, 0x08, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "zero {za0.s,za3.s}"
+
+  -
+    input:
+      bytes: [ 0x66, 0x00, 0x08, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "zero {za1.s,za2.s}"
+
+  -
+    input:
+      bytes: [ 0xcc, 0x00, 0x08, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "zero {za2.s,za3.s}"
+
+  -
+    input:
+      bytes: [ 0x77, 0x00, 0x08, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "zero {za0.s,za1.s,za2.s}"
+
+  -
+    input:
+      bytes: [ 0xbb, 0x00, 0x08, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "zero {za0.s,za1.s,za3.s}"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x00, 0x08, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "zero {za0.s,za2.s,za3.s}"
+
+  -
+    input:
+      bytes: [ 0xee, 0x00, 0x08, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "zero {za1.s,za2.s,za3.s}"
diff --git a/tests/MC/AArch64/SME2/add.s.yaml b/tests/MC/AArch64/SME2/add.s.yaml
new file mode 100644
index 000000000..23235b57c
--- /dev/null
+++ b/tests/MC/AArch64/SME2/add.s.yaml
@@ -0,0 +1,3430 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xa3, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add { z0.h, z1.h }, { z0.h, z1.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x14, 0xa3, 0x65, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add { z20.h, z21.h }, { z20.h, z21.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0x16, 0xa3, 0x68, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add { z22.h, z23.h }, { z22.h, z23.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0x1e, 0xa3, 0x6f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add { z30.h, z31.h }, { z30.h, z31.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0x10, 0x1c, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w8, 0, vgx2], { z0.s, z1.s }"
+
+  -
+    input:
+      bytes: [ 0x10, 0x1c, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w8, 0, vgx2], { z0.s, z1.s }"
+
+  -
+    input:
+      bytes: [ 0x55, 0x5d, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w10, 5, vgx2], { z10.s, z11.s }"
+
+  -
+    input:
+      bytes: [ 0x55, 0x5d, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w10, 5, vgx2], { z10.s, z11.s }"
+
+  -
+    input:
+      bytes: [ 0x97, 0x7d, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w11, 7, vgx2], { z12.s, z13.s }"
+
+  -
+    input:
+      bytes: [ 0x97, 0x7d, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w11, 7, vgx2], { z12.s, z13.s }"
+
+  -
+    input:
+      bytes: [ 0xd7, 0x7f, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w11, 7, vgx2], { z30.s, z31.s }"
+
+  -
+    input:
+      bytes: [ 0xd7, 0x7f, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w11, 7, vgx2], { z30.s, z31.s }"
+
+  -
+    input:
+      bytes: [ 0x15, 0x1e, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w8, 5, vgx2], { z16.s, z17.s }"
+
+  -
+    input:
+      bytes: [ 0x15, 0x1e, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w8, 5, vgx2], { z16.s, z17.s }"
+
+  -
+    input:
+      bytes: [ 0x11, 0x1c, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w8, 1, vgx2], { z0.s, z1.s }"
+
+  -
+    input:
+      bytes: [ 0x11, 0x1c, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w8, 1, vgx2], { z0.s, z1.s }"
+
+  -
+    input:
+      bytes: [ 0x50, 0x5e, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w10, 0, vgx2], { z18.s, z19.s }"
+
+  -
+    input:
+      bytes: [ 0x50, 0x5e, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w10, 0, vgx2], { z18.s, z19.s }"
+
+  -
+    input:
+      bytes: [ 0x90, 0x1d, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w8, 0, vgx2], { z12.s, z13.s }"
+
+  -
+    input:
+      bytes: [ 0x11, 0x5c, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w10, 1, vgx2], { z0.s, z1.s }"
+
+  -
+    input:
+      bytes: [ 0x11, 0x5c, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w10, 1, vgx2], { z0.s, z1.s }"
+
+  -
+    input:
+      bytes: [ 0xd5, 0x1e, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w8, 5, vgx2], { z22.s, z23.s }"
+
+  -
+    input:
+      bytes: [ 0xd5, 0x1e, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w8, 5, vgx2], { z22.s, z23.s }"
+
+  -
+    input:
+      bytes: [ 0x12, 0x7d, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w11, 2, vgx2], { z8.s, z9.s }"
+
+  -
+    input:
+      bytes: [ 0x12, 0x7d, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w11, 2, vgx2], { z8.s, z9.s }"
+
+  -
+    input:
+      bytes: [ 0x97, 0x3d, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w9, 7, vgx2], { z12.s, z13.s }"
+
+  -
+    input:
+      bytes: [ 0x97, 0x3d, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w9, 7, vgx2], { z12.s, z13.s }"
+
+  -
+    input:
+      bytes: [ 0x10, 0x18, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w8, 0, vgx2], { z0.s, z1.s }, z0.s"
+
+  -
+    input:
+      bytes: [ 0x10, 0x18, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w8, 0, vgx2], { z0.s, z1.s }, z0.s"
+
+  -
+    input:
+      bytes: [ 0x55, 0x59, 0x25, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w10, 5, vgx2], { z10.s, z11.s }, z5.s"
+
+  -
+    input:
+      bytes: [ 0x55, 0x59, 0x25, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w10, 5, vgx2], { z10.s, z11.s }, z5.s"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x79, 0x28, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w11, 7, vgx2], { z13.s, z14.s }, z8.s"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x79, 0x28, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w11, 7, vgx2], { z13.s, z14.s }, z8.s"
+
+  -
+    input:
+      bytes: [ 0xf7, 0x7b, 0x2f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w11, 7, vgx2], { z31.s, z0.s }, z15.s"
+
+  -
+    input:
+      bytes: [ 0xf7, 0x7b, 0x2f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w11, 7, vgx2], { z31.s, z0.s }, z15.s"
+
+  -
+    input:
+      bytes: [ 0x35, 0x1a, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w8, 5, vgx2], { z17.s, z18.s }, z0.s"
+
+  -
+    input:
+      bytes: [ 0x35, 0x1a, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w8, 5, vgx2], { z17.s, z18.s }, z0.s"
+
+  -
+    input:
+      bytes: [ 0x31, 0x18, 0x2e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w8, 1, vgx2], { z1.s, z2.s }, z14.s"
+
+  -
+    input:
+      bytes: [ 0x31, 0x18, 0x2e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w8, 1, vgx2], { z1.s, z2.s }, z14.s"
+
+  -
+    input:
+      bytes: [ 0x70, 0x5a, 0x24, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w10, 0, vgx2], { z19.s, z20.s }, z4.s"
+
+  -
+    input:
+      bytes: [ 0x70, 0x5a, 0x24, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w10, 0, vgx2], { z19.s, z20.s }, z4.s"
+
+  -
+    input:
+      bytes: [ 0x90, 0x19, 0x22, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w8, 0, vgx2], { z12.s, z13.s }, z2.s"
+
+  -
+    input:
+      bytes: [ 0x90, 0x19, 0x22, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w8, 0, vgx2], { z12.s, z13.s }, z2.s"
+
+  -
+    input:
+      bytes: [ 0x31, 0x58, 0x2a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w10, 1, vgx2], { z1.s, z2.s }, z10.s"
+
+  -
+    input:
+      bytes: [ 0x31, 0x58, 0x2a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w10, 1, vgx2], { z1.s, z2.s }, z10.s"
+
+  -
+    input:
+      bytes: [ 0xd5, 0x1a, 0x2e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w8, 5, vgx2], { z22.s, z23.s }, z14.s"
+
+  -
+    input:
+      bytes: [ 0xd5, 0x1a, 0x2e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w8, 5, vgx2], { z22.s, z23.s }, z14.s"
+
+  -
+    input:
+      bytes: [ 0x32, 0x79, 0x21, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w11, 2, vgx2], { z9.s, z10.s }, z1.s"
+
+  -
+    input:
+      bytes: [ 0x32, 0x79, 0x21, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w11, 2, vgx2], { z9.s, z10.s }, z1.s"
+
+  -
+    input:
+      bytes: [ 0x97, 0x39, 0x2b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w9, 7, vgx2], { z12.s, z13.s }, z11.s"
+
+  -
+    input:
+      bytes: [ 0x97, 0x39, 0x2b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w9, 7, vgx2], { z12.s, z13.s }, z11.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa3, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add { z0.s, z1.s }, { z0.s, z1.s }, z0.s"
+
+  -
+    input:
+      bytes: [ 0x14, 0xa3, 0xa5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add { z20.s, z21.s }, { z20.s, z21.s }, z5.s"
+
+  -
+    input:
+      bytes: [ 0x16, 0xa3, 0xa8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add { z22.s, z23.s }, { z22.s, z23.s }, z8.s"
+
+  -
+    input:
+      bytes: [ 0x1e, 0xa3, 0xaf, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add { z30.s, z31.s }, { z30.s, z31.s }, z15.s"
+
+  -
+    input:
+      bytes: [ 0x10, 0x18, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w8, 0, vgx2], { z0.s, z1.s }, { z0.s, z1.s }"
+
+  -
+    input:
+      bytes: [ 0x10, 0x18, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w8, 0, vgx2], { z0.s, z1.s }, { z0.s, z1.s }"
+
+  -
+    input:
+      bytes: [ 0x55, 0x59, 0xb4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w10, 5, vgx2], { z10.s, z11.s }, { z20.s, z21.s }"
+
+  -
+    input:
+      bytes: [ 0x55, 0x59, 0xb4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w10, 5, vgx2], { z10.s, z11.s }, { z20.s, z21.s }"
+
+  -
+    input:
+      bytes: [ 0x97, 0x79, 0xa8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w11, 7, vgx2], { z12.s, z13.s }, { z8.s, z9.s }"
+
+  -
+    input:
+      bytes: [ 0x97, 0x79, 0xa8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w11, 7, vgx2], { z12.s, z13.s }, { z8.s, z9.s }"
+
+  -
+    input:
+      bytes: [ 0xd7, 0x7b, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w11, 7, vgx2], { z30.s, z31.s }, { z30.s, z31.s }"
+
+  -
+    input:
+      bytes: [ 0xd7, 0x7b, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w11, 7, vgx2], { z30.s, z31.s }, { z30.s, z31.s }"
+
+  -
+    input:
+      bytes: [ 0x15, 0x1a, 0xb0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w8, 5, vgx2], { z16.s, z17.s }, { z16.s, z17.s }"
+
+  -
+    input:
+      bytes: [ 0x15, 0x1a, 0xb0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w8, 5, vgx2], { z16.s, z17.s }, { z16.s, z17.s }"
+
+  -
+    input:
+      bytes: [ 0x11, 0x18, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w8, 1, vgx2], { z0.s, z1.s }, { z30.s, z31.s }"
+
+  -
+    input:
+      bytes: [ 0x11, 0x18, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w8, 1, vgx2], { z0.s, z1.s }, { z30.s, z31.s }"
+
+  -
+    input:
+      bytes: [ 0x50, 0x5a, 0xb4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w10, 0, vgx2], { z18.s, z19.s }, { z20.s, z21.s }"
+
+  -
+    input:
+      bytes: [ 0x50, 0x5a, 0xb4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w10, 0, vgx2], { z18.s, z19.s }, { z20.s, z21.s }"
+
+  -
+    input:
+      bytes: [ 0x90, 0x19, 0xa2, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w8, 0, vgx2], { z12.s, z13.s }, { z2.s, z3.s }"
+
+  -
+    input:
+      bytes: [ 0x90, 0x19, 0xa2, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w8, 0, vgx2], { z12.s, z13.s }, { z2.s, z3.s }"
+
+  -
+    input:
+      bytes: [ 0x11, 0x58, 0xba, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w10, 1, vgx2], { z0.s, z1.s }, { z26.s, z27.s }"
+
+  -
+    input:
+      bytes: [ 0x11, 0x58, 0xba, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w10, 1, vgx2], { z0.s, z1.s }, { z26.s, z27.s }"
+
+  -
+    input:
+      bytes: [ 0xd5, 0x1a, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w8, 5, vgx2], { z22.s, z23.s }, { z30.s, z31.s }"
+
+  -
+    input:
+      bytes: [ 0xd5, 0x1a, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w8, 5, vgx2], { z22.s, z23.s }, { z30.s, z31.s }"
+
+  -
+    input:
+      bytes: [ 0x12, 0x79, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w11, 2, vgx2], { z8.s, z9.s }, { z0.s, z1.s }"
+
+  -
+    input:
+      bytes: [ 0x12, 0x79, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w11, 2, vgx2], { z8.s, z9.s }, { z0.s, z1.s }"
+
+  -
+    input:
+      bytes: [ 0x97, 0x39, 0xaa, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w9, 7, vgx2], { z12.s, z13.s }, { z10.s, z11.s }"
+
+  -
+    input:
+      bytes: [ 0x97, 0x39, 0xaa, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w9, 7, vgx2], { z12.s, z13.s }, { z10.s, z11.s }"
+
+  -
+    input:
+      bytes: [ 0x10, 0x1c, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w8, 0, vgx2], { z0.d, z1.d }"
+
+  -
+    input:
+      bytes: [ 0x10, 0x1c, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w8, 0, vgx2], { z0.d, z1.d }"
+
+  -
+    input:
+      bytes: [ 0x55, 0x5d, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w10, 5, vgx2], { z10.d, z11.d }"
+
+  -
+    input:
+      bytes: [ 0x55, 0x5d, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w10, 5, vgx2], { z10.d, z11.d }"
+
+  -
+    input:
+      bytes: [ 0x97, 0x7d, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w11, 7, vgx2], { z12.d, z13.d }"
+
+  -
+    input:
+      bytes: [ 0x97, 0x7d, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w11, 7, vgx2], { z12.d, z13.d }"
+
+  -
+    input:
+      bytes: [ 0xd7, 0x7f, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w11, 7, vgx2], { z30.d, z31.d }"
+
+  -
+    input:
+      bytes: [ 0xd7, 0x7f, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w11, 7, vgx2], { z30.d, z31.d }"
+
+  -
+    input:
+      bytes: [ 0x15, 0x1e, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w8, 5, vgx2], { z16.d, z17.d }"
+
+  -
+    input:
+      bytes: [ 0x15, 0x1e, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w8, 5, vgx2], { z16.d, z17.d }"
+
+  -
+    input:
+      bytes: [ 0x11, 0x1c, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w8, 1, vgx2], { z0.d, z1.d }"
+
+  -
+    input:
+      bytes: [ 0x11, 0x1c, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w8, 1, vgx2], { z0.d, z1.d }"
+
+  -
+    input:
+      bytes: [ 0x50, 0x5e, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w10, 0, vgx2], { z18.d, z19.d }"
+
+  -
+    input:
+      bytes: [ 0x50, 0x5e, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w10, 0, vgx2], { z18.d, z19.d }"
+
+  -
+    input:
+      bytes: [ 0x90, 0x1d, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w8, 0, vgx2], { z12.d, z13.d }"
+
+  -
+    input:
+      bytes: [ 0x90, 0x1d, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w8, 0, vgx2], { z12.d, z13.d }"
+
+  -
+    input:
+      bytes: [ 0x11, 0x5c, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w10, 1, vgx2], { z0.d, z1.d }"
+
+  -
+    input:
+      bytes: [ 0x11, 0x5c, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w10, 1, vgx2], { z0.d, z1.d }"
+
+  -
+    input:
+      bytes: [ 0xd5, 0x1e, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w8, 5, vgx2], { z22.d, z23.d }"
+
+  -
+    input:
+      bytes: [ 0xd5, 0x1e, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w8, 5, vgx2], { z22.d, z23.d }"
+
+  -
+    input:
+      bytes: [ 0x12, 0x7d, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w11, 2, vgx2], { z8.d, z9.d }"
+
+  -
+    input:
+      bytes: [ 0x12, 0x7d, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w11, 2, vgx2], { z8.d, z9.d }"
+
+  -
+    input:
+      bytes: [ 0x97, 0x3d, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w9, 7, vgx2], { z12.d, z13.d }"
+
+  -
+    input:
+      bytes: [ 0x97, 0x3d, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w9, 7, vgx2], { z12.d, z13.d }"
+
+  -
+    input:
+      bytes: [ 0x10, 0x18, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w8, 0, vgx2], { z0.d, z1.d }, z0.d"
+
+  -
+    input:
+      bytes: [ 0x10, 0x18, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w8, 0, vgx2], { z0.d, z1.d }, z0.d"
+
+  -
+    input:
+      bytes: [ 0x55, 0x59, 0x65, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w10, 5, vgx2], { z10.d, z11.d }, z5.d"
+
+  -
+    input:
+      bytes: [ 0x55, 0x59, 0x65, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w10, 5, vgx2], { z10.d, z11.d }, z5.d"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x79, 0x68, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w11, 7, vgx2], { z13.d, z14.d }, z8.d"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x79, 0x68, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w11, 7, vgx2], { z13.d, z14.d }, z8.d"
+
+  -
+    input:
+      bytes: [ 0xf7, 0x7b, 0x6f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w11, 7, vgx2], { z31.d, z0.d }, z15.d"
+
+  -
+    input:
+      bytes: [ 0xf7, 0x7b, 0x6f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w11, 7, vgx2], { z31.d, z0.d }, z15.d"
+
+  -
+    input:
+      bytes: [ 0x35, 0x1a, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w8, 5, vgx2], { z17.d, z18.d }, z0.d"
+
+  -
+    input:
+      bytes: [ 0x35, 0x1a, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w8, 5, vgx2], { z17.d, z18.d }, z0.d"
+
+  -
+    input:
+      bytes: [ 0x31, 0x18, 0x6e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w8, 1, vgx2], { z1.d, z2.d }, z14.d"
+
+  -
+    input:
+      bytes: [ 0x31, 0x18, 0x6e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w8, 1, vgx2], { z1.d, z2.d }, z14.d"
+
+  -
+    input:
+      bytes: [ 0x70, 0x5a, 0x64, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w10, 0, vgx2], { z19.d, z20.d }, z4.d"
+
+  -
+    input:
+      bytes: [ 0x70, 0x5a, 0x64, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w10, 0, vgx2], { z19.d, z20.d }, z4.d"
+
+  -
+    input:
+      bytes: [ 0x90, 0x19, 0x62, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w8, 0, vgx2], { z12.d, z13.d }, z2.d"
+
+  -
+    input:
+      bytes: [ 0x90, 0x19, 0x62, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w8, 0, vgx2], { z12.d, z13.d }, z2.d"
+
+  -
+    input:
+      bytes: [ 0x31, 0x58, 0x6a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w10, 1, vgx2], { z1.d, z2.d }, z10.d"
+
+  -
+    input:
+      bytes: [ 0x31, 0x58, 0x6a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w10, 1, vgx2], { z1.d, z2.d }, z10.d"
+
+  -
+    input:
+      bytes: [ 0xd5, 0x1a, 0x6e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w8, 5, vgx2], { z22.d, z23.d }, z14.d"
+
+  -
+    input:
+      bytes: [ 0xd5, 0x1a, 0x6e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w8, 5, vgx2], { z22.d, z23.d }, z14.d"
+
+  -
+    input:
+      bytes: [ 0x32, 0x79, 0x61, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w11, 2, vgx2], { z9.d, z10.d }, z1.d"
+
+  -
+    input:
+      bytes: [ 0x32, 0x79, 0x61, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w11, 2, vgx2], { z9.d, z10.d }, z1.d"
+
+  -
+    input:
+      bytes: [ 0x97, 0x39, 0x6b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w9, 7, vgx2], { z12.d, z13.d }, z11.d"
+
+  -
+    input:
+      bytes: [ 0x97, 0x39, 0x6b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w9, 7, vgx2], { z12.d, z13.d }, z11.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa3, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add { z0.d, z1.d }, { z0.d, z1.d }, z0.d"
+
+  -
+    input:
+      bytes: [ 0x14, 0xa3, 0xe5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add { z20.d, z21.d }, { z20.d, z21.d }, z5.d"
+
+  -
+    input:
+      bytes: [ 0x16, 0xa3, 0xe8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add { z22.d, z23.d }, { z22.d, z23.d }, z8.d"
+
+  -
+    input:
+      bytes: [ 0x1e, 0xa3, 0xef, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add { z30.d, z31.d }, { z30.d, z31.d }, z15.d"
+
+  -
+    input:
+      bytes: [ 0x10, 0x18, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w8, 0, vgx2], { z0.d, z1.d }, { z0.d, z1.d }"
+
+  -
+    input:
+      bytes: [ 0x10, 0x18, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w8, 0, vgx2], { z0.d, z1.d }, { z0.d, z1.d }"
+
+  -
+    input:
+      bytes: [ 0x55, 0x59, 0xf4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w10, 5, vgx2], { z10.d, z11.d }, { z20.d, z21.d }"
+
+  -
+    input:
+      bytes: [ 0x55, 0x59, 0xf4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w10, 5, vgx2], { z10.d, z11.d }, { z20.d, z21.d }"
+
+  -
+    input:
+      bytes: [ 0x97, 0x79, 0xe8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w11, 7, vgx2], { z12.d, z13.d }, { z8.d, z9.d }"
+
+  -
+    input:
+      bytes: [ 0x97, 0x79, 0xe8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w11, 7, vgx2], { z12.d, z13.d }, { z8.d, z9.d }"
+
+  -
+    input:
+      bytes: [ 0xd7, 0x7b, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w11, 7, vgx2], { z30.d, z31.d }, { z30.d, z31.d }"
+
+  -
+    input:
+      bytes: [ 0xd7, 0x7b, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w11, 7, vgx2], { z30.d, z31.d }, { z30.d, z31.d }"
+
+  -
+    input:
+      bytes: [ 0x15, 0x1a, 0xf0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w8, 5, vgx2], { z16.d, z17.d }, { z16.d, z17.d }"
+
+  -
+    input:
+      bytes: [ 0x15, 0x1a, 0xf0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w8, 5, vgx2], { z16.d, z17.d }, { z16.d, z17.d }"
+
+  -
+    input:
+      bytes: [ 0x11, 0x18, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w8, 1, vgx2], { z0.d, z1.d }, { z30.d, z31.d }"
+
+  -
+    input:
+      bytes: [ 0x11, 0x18, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w8, 1, vgx2], { z0.d, z1.d }, { z30.d, z31.d }"
+
+  -
+    input:
+      bytes: [ 0x50, 0x5a, 0xf4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w10, 0, vgx2], { z18.d, z19.d }, { z20.d, z21.d }"
+
+  -
+    input:
+      bytes: [ 0x50, 0x5a, 0xf4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w10, 0, vgx2], { z18.d, z19.d }, { z20.d, z21.d }"
+
+  -
+    input:
+      bytes: [ 0x90, 0x19, 0xe2, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w8, 0, vgx2], { z12.d, z13.d }, { z2.d, z3.d }"
+
+  -
+    input:
+      bytes: [ 0x90, 0x19, 0xe2, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w8, 0, vgx2], { z12.d, z13.d }, { z2.d, z3.d }"
+
+  -
+    input:
+      bytes: [ 0x11, 0x58, 0xfa, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w10, 1, vgx2], { z0.d, z1.d }, { z26.d, z27.d }"
+
+  -
+    input:
+      bytes: [ 0x11, 0x58, 0xfa, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w10, 1, vgx2], { z0.d, z1.d }, { z26.d, z27.d }"
+
+  -
+    input:
+      bytes: [ 0xd5, 0x1a, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w8, 5, vgx2], { z22.d, z23.d }, { z30.d, z31.d }"
+
+  -
+    input:
+      bytes: [ 0xd5, 0x1a, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w8, 5, vgx2], { z22.d, z23.d }, { z30.d, z31.d }"
+
+  -
+    input:
+      bytes: [ 0x12, 0x79, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w11, 2, vgx2], { z8.d, z9.d }, { z0.d, z1.d }"
+
+  -
+    input:
+      bytes: [ 0x12, 0x79, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w11, 2, vgx2], { z8.d, z9.d }, { z0.d, z1.d }"
+
+  -
+    input:
+      bytes: [ 0x97, 0x39, 0xea, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w9, 7, vgx2], { z12.d, z13.d }, { z10.d, z11.d }"
+
+  -
+    input:
+      bytes: [ 0x97, 0x39, 0xea, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w9, 7, vgx2], { z12.d, z13.d }, { z10.d, z11.d }"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa3, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add { z0.b, z1.b }, { z0.b, z1.b }, z0.b"
+
+  -
+    input:
+      bytes: [ 0x14, 0xa3, 0x25, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add { z20.b, z21.b }, { z20.b, z21.b }, z5.b"
+
+  -
+    input:
+      bytes: [ 0x16, 0xa3, 0x28, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add { z22.b, z23.b }, { z22.b, z23.b }, z8.b"
+
+  -
+    input:
+      bytes: [ 0x1e, 0xa3, 0x2f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add { z30.b, z31.b }, { z30.b, z31.b }, z15.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0xab, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add { z0.h - z3.h }, { z0.h - z3.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x14, 0xab, 0x65, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add { z20.h - z23.h }, { z20.h - z23.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0x14, 0xab, 0x68, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add { z20.h - z23.h }, { z20.h - z23.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0x1c, 0xab, 0x6f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add { z28.h - z31.h }, { z28.h - z31.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0x10, 0x1c, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w8, 0, vgx4], { z0.s - z3.s }"
+
+  -
+    input:
+      bytes: [ 0x10, 0x1c, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w8, 0, vgx4], { z0.s - z3.s }"
+
+  -
+    input:
+      bytes: [ 0x15, 0x5d, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w10, 5, vgx4], { z8.s - z11.s }"
+
+  -
+    input:
+      bytes: [ 0x15, 0x5d, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w10, 5, vgx4], { z8.s - z11.s }"
+
+  -
+    input:
+      bytes: [ 0x97, 0x7d, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w11, 7, vgx4], { z12.s - z15.s }"
+
+  -
+    input:
+      bytes: [ 0x97, 0x7d, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w11, 7, vgx4], { z12.s - z15.s }"
+
+  -
+    input:
+      bytes: [ 0x97, 0x7f, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w11, 7, vgx4], { z28.s - z31.s }"
+
+  -
+    input:
+      bytes: [ 0x97, 0x7f, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w11, 7, vgx4], { z28.s - z31.s }"
+
+  -
+    input:
+      bytes: [ 0x15, 0x1e, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w8, 5, vgx4], { z16.s - z19.s }"
+
+  -
+    input:
+      bytes: [ 0x15, 0x1e, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w8, 5, vgx4], { z16.s - z19.s }"
+
+  -
+    input:
+      bytes: [ 0x11, 0x1c, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w8, 1, vgx4], { z0.s - z3.s }"
+
+  -
+    input:
+      bytes: [ 0x11, 0x1c, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w8, 1, vgx4], { z0.s - z3.s }"
+
+  -
+    input:
+      bytes: [ 0x10, 0x5e, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w10, 0, vgx4], { z16.s - z19.s }"
+
+  -
+    input:
+      bytes: [ 0x10, 0x5e, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w10, 0, vgx4], { z16.s - z19.s }"
+
+  -
+    input:
+      bytes: [ 0x90, 0x1d, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w8, 0, vgx4], { z12.s - z15.s }"
+
+  -
+    input:
+      bytes: [ 0x90, 0x1d, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w8, 0, vgx4], { z12.s - z15.s }"
+
+  -
+    input:
+      bytes: [ 0x11, 0x5c, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w10, 1, vgx4], { z0.s - z3.s }"
+
+  -
+    input:
+      bytes: [ 0x11, 0x5c, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w10, 1, vgx4], { z0.s - z3.s }"
+
+  -
+    input:
+      bytes: [ 0x95, 0x1e, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w8, 5, vgx4], { z20.s - z23.s }"
+
+  -
+    input:
+      bytes: [ 0x95, 0x1e, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w8, 5, vgx4], { z20.s - z23.s }"
+
+  -
+    input:
+      bytes: [ 0x12, 0x7d, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w11, 2, vgx4], { z8.s - z11.s }"
+
+  -
+    input:
+      bytes: [ 0x12, 0x7d, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w11, 2, vgx4], { z8.s - z11.s }"
+
+  -
+    input:
+      bytes: [ 0x97, 0x3d, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w9, 7, vgx4], { z12.s - z15.s }"
+
+  -
+    input:
+      bytes: [ 0x97, 0x3d, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w9, 7, vgx4], { z12.s - z15.s }"
+
+  -
+    input:
+      bytes: [ 0x10, 0x18, 0x30, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w8, 0, vgx4], { z0.s - z3.s }, z0.s"
+
+  -
+    input:
+      bytes: [ 0x10, 0x18, 0x30, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w8, 0, vgx4], { z0.s - z3.s }, z0.s"
+
+  -
+    input:
+      bytes: [ 0x55, 0x59, 0x35, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w10, 5, vgx4], { z10.s - z13.s }, z5.s"
+
+  -
+    input:
+      bytes: [ 0x55, 0x59, 0x35, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w10, 5, vgx4], { z10.s - z13.s }, z5.s"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x79, 0x38, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w11, 7, vgx4], { z13.s - z16.s }, z8.s"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x79, 0x38, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w11, 7, vgx4], { z13.s - z16.s }, z8.s"
+
+  -
+    input:
+      bytes: [ 0xf7, 0x7b, 0x3f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w11, 7, vgx4], { z31.s, z0.s, z1.s, z2.s }, z15.s"
+
+  -
+    input:
+      bytes: [ 0xf7, 0x7b, 0x3f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w11, 7, vgx4], { z31.s, z0.s, z1.s, z2.s }, z15.s"
+
+  -
+    input:
+      bytes: [ 0x35, 0x1a, 0x30, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w8, 5, vgx4], { z17.s - z20.s }, z0.s"
+
+  -
+    input:
+      bytes: [ 0x35, 0x1a, 0x30, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w8, 5, vgx4], { z17.s - z20.s }, z0.s"
+
+  -
+    input:
+      bytes: [ 0x31, 0x18, 0x3e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w8, 1, vgx4], { z1.s - z4.s }, z14.s"
+
+  -
+    input:
+      bytes: [ 0x31, 0x18, 0x3e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w8, 1, vgx4], { z1.s - z4.s }, z14.s"
+
+  -
+    input:
+      bytes: [ 0x70, 0x5a, 0x34, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w10, 0, vgx4], { z19.s - z22.s }, z4.s"
+
+  -
+    input:
+      bytes: [ 0x70, 0x5a, 0x34, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w10, 0, vgx4], { z19.s - z22.s }, z4.s"
+
+  -
+    input:
+      bytes: [ 0x90, 0x19, 0x32, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w8, 0, vgx4], { z12.s - z15.s }, z2.s"
+
+  -
+    input:
+      bytes: [ 0x90, 0x19, 0x32, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w8, 0, vgx4], { z12.s - z15.s }, z2.s"
+
+  -
+    input:
+      bytes: [ 0x31, 0x58, 0x3a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w10, 1, vgx4], { z1.s - z4.s }, z10.s"
+
+  -
+    input:
+      bytes: [ 0x31, 0x58, 0x3a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w10, 1, vgx4], { z1.s - z4.s }, z10.s"
+
+  -
+    input:
+      bytes: [ 0xd5, 0x1a, 0x3e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w8, 5, vgx4], { z22.s - z25.s }, z14.s"
+
+  -
+    input:
+      bytes: [ 0xd5, 0x1a, 0x3e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w8, 5, vgx4], { z22.s - z25.s }, z14.s"
+
+  -
+    input:
+      bytes: [ 0x32, 0x79, 0x31, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w11, 2, vgx4], { z9.s - z12.s }, z1.s"
+
+  -
+    input:
+      bytes: [ 0x32, 0x79, 0x31, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w11, 2, vgx4], { z9.s - z12.s }, z1.s"
+
+  -
+    input:
+      bytes: [ 0x97, 0x39, 0x3b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w9, 7, vgx4], { z12.s - z15.s }, z11.s"
+
+  -
+    input:
+      bytes: [ 0x97, 0x39, 0x3b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w9, 7, vgx4], { z12.s - z15.s }, z11.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0xab, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add { z0.s - z3.s }, { z0.s - z3.s }, z0.s"
+
+  -
+    input:
+      bytes: [ 0x14, 0xab, 0xa5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add { z20.s - z23.s }, { z20.s - z23.s }, z5.s"
+
+  -
+    input:
+      bytes: [ 0x14, 0xab, 0xa8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add { z20.s - z23.s }, { z20.s - z23.s }, z8.s"
+
+  -
+    input:
+      bytes: [ 0x1c, 0xab, 0xaf, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add { z28.s - z31.s }, { z28.s - z31.s }, z15.s"
+
+  -
+    input:
+      bytes: [ 0x10, 0x18, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w8, 0, vgx4], { z0.s - z3.s }, { z0.s - z3.s }"
+
+  -
+    input:
+      bytes: [ 0x10, 0x18, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w8, 0, vgx4], { z0.s - z3.s }, { z0.s - z3.s }"
+
+  -
+    input:
+      bytes: [ 0x15, 0x59, 0xb5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w10, 5, vgx4], { z8.s - z11.s }, { z20.s - z23.s }"
+
+  -
+    input:
+      bytes: [ 0x15, 0x59, 0xb5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w10, 5, vgx4], { z8.s - z11.s }, { z20.s - z23.s }"
+
+  -
+    input:
+      bytes: [ 0x97, 0x79, 0xa9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w11, 7, vgx4], { z12.s - z15.s }, { z8.s - z11.s }"
+
+  -
+    input:
+      bytes: [ 0x97, 0x79, 0xa9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w11, 7, vgx4], { z12.s - z15.s }, { z8.s - z11.s }"
+
+  -
+    input:
+      bytes: [ 0x97, 0x7b, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w11, 7, vgx4], { z28.s - z31.s }, { z28.s - z31.s }"
+
+  -
+    input:
+      bytes: [ 0x97, 0x7b, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w11, 7, vgx4], { z28.s - z31.s }, { z28.s - z31.s }"
+
+  -
+    input:
+      bytes: [ 0x15, 0x1a, 0xb1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w8, 5, vgx4], { z16.s - z19.s }, { z16.s - z19.s }"
+
+  -
+    input:
+      bytes: [ 0x15, 0x1a, 0xb1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w8, 5, vgx4], { z16.s - z19.s }, { z16.s - z19.s }"
+
+  -
+    input:
+      bytes: [ 0x11, 0x18, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w8, 1, vgx4], { z0.s - z3.s }, { z28.s - z31.s }"
+
+  -
+    input:
+      bytes: [ 0x11, 0x18, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w8, 1, vgx4], { z0.s - z3.s }, { z28.s - z31.s }"
+
+  -
+    input:
+      bytes: [ 0x10, 0x5a, 0xb5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w10, 0, vgx4], { z16.s - z19.s }, { z20.s - z23.s }"
+
+  -
+    input:
+      bytes: [ 0x10, 0x5a, 0xb5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w10, 0, vgx4], { z16.s - z19.s }, { z20.s - z23.s }"
+
+  -
+    input:
+      bytes: [ 0x90, 0x19, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w8, 0, vgx4], { z12.s - z15.s }, { z0.s - z3.s }"
+
+  -
+    input:
+      bytes: [ 0x90, 0x19, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w8, 0, vgx4], { z12.s - z15.s }, { z0.s - z3.s }"
+
+  -
+    input:
+      bytes: [ 0x11, 0x58, 0xb9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w10, 1, vgx4], { z0.s - z3.s }, { z24.s - z27.s }"
+
+  -
+    input:
+      bytes: [ 0x11, 0x58, 0xb9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w10, 1, vgx4], { z0.s - z3.s }, { z24.s - z27.s }"
+
+  -
+    input:
+      bytes: [ 0x95, 0x1a, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w8, 5, vgx4], { z20.s - z23.s }, { z28.s - z31.s }"
+
+  -
+    input:
+      bytes: [ 0x95, 0x1a, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w8, 5, vgx4], { z20.s - z23.s }, { z28.s - z31.s }"
+
+  -
+    input:
+      bytes: [ 0x12, 0x79, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w11, 2, vgx4], { z8.s - z11.s }, { z0.s - z3.s }"
+
+  -
+    input:
+      bytes: [ 0x12, 0x79, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w11, 2, vgx4], { z8.s - z11.s }, { z0.s - z3.s }"
+
+  -
+    input:
+      bytes: [ 0x97, 0x39, 0xa9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w9, 7, vgx4], { z12.s - z15.s }, { z8.s - z11.s }"
+
+  -
+    input:
+      bytes: [ 0x97, 0x39, 0xa9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.s[w9, 7, vgx4], { z12.s - z15.s }, { z8.s - z11.s }"
+
+  -
+    input:
+      bytes: [ 0x10, 0x1c, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w8, 0, vgx4], { z0.d - z3.d }"
+
+  -
+    input:
+      bytes: [ 0x10, 0x1c, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w8, 0, vgx4], { z0.d - z3.d }"
+
+  -
+    input:
+      bytes: [ 0x15, 0x5d, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w10, 5, vgx4], { z8.d - z11.d }"
+
+  -
+    input:
+      bytes: [ 0x15, 0x5d, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w10, 5, vgx4], { z8.d - z11.d }"
+
+  -
+    input:
+      bytes: [ 0x97, 0x7d, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w11, 7, vgx4], { z12.d - z15.d }"
+
+  -
+    input:
+      bytes: [ 0x97, 0x7d, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w11, 7, vgx4], { z12.d - z15.d }"
+
+  -
+    input:
+      bytes: [ 0x97, 0x7f, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w11, 7, vgx4], { z28.d - z31.d }"
+
+  -
+    input:
+      bytes: [ 0x97, 0x7f, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w11, 7, vgx4], { z28.d - z31.d }"
+
+  -
+    input:
+      bytes: [ 0x15, 0x1e, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w8, 5, vgx4], { z16.d - z19.d }"
+
+  -
+    input:
+      bytes: [ 0x15, 0x1e, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w8, 5, vgx4], { z16.d - z19.d }"
+
+  -
+    input:
+      bytes: [ 0x11, 0x1c, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w8, 1, vgx4], { z0.d - z3.d }"
+
+  -
+    input:
+      bytes: [ 0x11, 0x1c, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w8, 1, vgx4], { z0.d - z3.d }"
+
+  -
+    input:
+      bytes: [ 0x10, 0x5e, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w10, 0, vgx4], { z16.d - z19.d }"
+
+  -
+    input:
+      bytes: [ 0x10, 0x5e, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w10, 0, vgx4], { z16.d - z19.d }"
+
+  -
+    input:
+      bytes: [ 0x90, 0x1d, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w8, 0, vgx4], { z12.d - z15.d }"
+
+  -
+    input:
+      bytes: [ 0x90, 0x1d, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w8, 0, vgx4], { z12.d - z15.d }"
+
+  -
+    input:
+      bytes: [ 0x11, 0x5c, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w10, 1, vgx4], { z0.d - z3.d }"
+
+  -
+    input:
+      bytes: [ 0x11, 0x5c, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w10, 1, vgx4], { z0.d - z3.d }"
+
+  -
+    input:
+      bytes: [ 0x95, 0x1e, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w8, 5, vgx4], { z20.d - z23.d }"
+
+  -
+    input:
+      bytes: [ 0x95, 0x1e, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w8, 5, vgx4], { z20.d - z23.d }"
+
+  -
+    input:
+      bytes: [ 0x12, 0x7d, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w11, 2, vgx4], { z8.d - z11.d }"
+
+  -
+    input:
+      bytes: [ 0x12, 0x7d, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w11, 2, vgx4], { z8.d - z11.d }"
+
+  -
+    input:
+      bytes: [ 0x97, 0x3d, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w9, 7, vgx4], { z12.d - z15.d }"
+
+  -
+    input:
+      bytes: [ 0x97, 0x3d, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w9, 7, vgx4], { z12.d - z15.d }"
+
+  -
+    input:
+      bytes: [ 0x10, 0x18, 0x70, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w8, 0, vgx4], { z0.d - z3.d }, z0.d"
+
+  -
+    input:
+      bytes: [ 0x10, 0x18, 0x70, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w8, 0, vgx4], { z0.d - z3.d }, z0.d"
+
+  -
+    input:
+      bytes: [ 0x55, 0x59, 0x75, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w10, 5, vgx4], { z10.d - z13.d }, z5.d"
+
+  -
+    input:
+      bytes: [ 0x55, 0x59, 0x75, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w10, 5, vgx4], { z10.d - z13.d }, z5.d"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x79, 0x78, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w11, 7, vgx4], { z13.d - z16.d }, z8.d"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x79, 0x78, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w11, 7, vgx4], { z13.d - z16.d }, z8.d"
+
+  -
+    input:
+      bytes: [ 0xf7, 0x7b, 0x7f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w11, 7, vgx4], { z31.d, z0.d, z1.d, z2.d }, z15.d"
+
+  -
+    input:
+      bytes: [ 0xf7, 0x7b, 0x7f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w11, 7, vgx4], { z31.d, z0.d, z1.d, z2.d }, z15.d"
+
+  -
+    input:
+      bytes: [ 0x35, 0x1a, 0x70, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w8, 5, vgx4], { z17.d - z20.d }, z0.d"
+
+  -
+    input:
+      bytes: [ 0x35, 0x1a, 0x70, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w8, 5, vgx4], { z17.d - z20.d }, z0.d"
+
+  -
+    input:
+      bytes: [ 0x31, 0x18, 0x7e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w8, 1, vgx4], { z1.d - z4.d }, z14.d"
+
+  -
+    input:
+      bytes: [ 0x31, 0x18, 0x7e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w8, 1, vgx4], { z1.d - z4.d }, z14.d"
+
+  -
+    input:
+      bytes: [ 0x70, 0x5a, 0x74, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w10, 0, vgx4], { z19.d - z22.d }, z4.d"
+
+  -
+    input:
+      bytes: [ 0x70, 0x5a, 0x74, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w10, 0, vgx4], { z19.d - z22.d }, z4.d"
+
+  -
+    input:
+      bytes: [ 0x90, 0x19, 0x72, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w8, 0, vgx4], { z12.d - z15.d }, z2.d"
+
+  -
+    input:
+      bytes: [ 0x90, 0x19, 0x72, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w8, 0, vgx4], { z12.d - z15.d }, z2.d"
+
+  -
+    input:
+      bytes: [ 0x31, 0x58, 0x7a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w10, 1, vgx4], { z1.d - z4.d }, z10.d"
+
+  -
+    input:
+      bytes: [ 0x31, 0x58, 0x7a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w10, 1, vgx4], { z1.d - z4.d }, z10.d"
+
+  -
+    input:
+      bytes: [ 0xd5, 0x1a, 0x7e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w8, 5, vgx4], { z22.d - z25.d }, z14.d"
+
+  -
+    input:
+      bytes: [ 0xd5, 0x1a, 0x7e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w8, 5, vgx4], { z22.d - z25.d }, z14.d"
+
+  -
+    input:
+      bytes: [ 0x32, 0x79, 0x71, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w11, 2, vgx4], { z9.d - z12.d }, z1.d"
+
+  -
+    input:
+      bytes: [ 0x32, 0x79, 0x71, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w11, 2, vgx4], { z9.d - z12.d }, z1.d"
+
+  -
+    input:
+      bytes: [ 0x97, 0x39, 0x7b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w9, 7, vgx4], { z12.d - z15.d }, z11.d"
+
+  -
+    input:
+      bytes: [ 0x97, 0x39, 0x7b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w9, 7, vgx4], { z12.d - z15.d }, z11.d"
+
+  -
+    input:
+      bytes: [ 0x10, 0x18, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w8, 0, vgx4], { z0.d - z3.d }, { z0.d - z3.d }"
+
+  -
+    input:
+      bytes: [ 0x10, 0x18, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w8, 0, vgx4], { z0.d - z3.d }, { z0.d - z3.d }"
+
+  -
+    input:
+      bytes: [ 0x15, 0x59, 0xf5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w10, 5, vgx4], { z8.d - z11.d }, { z20.d - z23.d }"
+
+  -
+    input:
+      bytes: [ 0x15, 0x59, 0xf5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w10, 5, vgx4], { z8.d - z11.d }, { z20.d - z23.d }"
+
+  -
+    input:
+      bytes: [ 0x97, 0x79, 0xe9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w11, 7, vgx4], { z12.d - z15.d }, { z8.d - z11.d }"
+
+  -
+    input:
+      bytes: [ 0x97, 0x79, 0xe9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w11, 7, vgx4], { z12.d - z15.d }, { z8.d - z11.d }"
+
+  -
+    input:
+      bytes: [ 0x97, 0x7b, 0xfd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w11, 7, vgx4], { z28.d - z31.d }, { z28.d - z31.d }"
+
+  -
+    input:
+      bytes: [ 0x97, 0x7b, 0xfd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w11, 7, vgx4], { z28.d - z31.d }, { z28.d - z31.d }"
+
+  -
+    input:
+      bytes: [ 0x15, 0x1a, 0xf1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w8, 5, vgx4], { z16.d - z19.d }, { z16.d - z19.d }"
+
+  -
+    input:
+      bytes: [ 0x15, 0x1a, 0xf1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w8, 5, vgx4], { z16.d - z19.d }, { z16.d - z19.d }"
+
+  -
+    input:
+      bytes: [ 0x11, 0x18, 0xfd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w8, 1, vgx4], { z0.d - z3.d }, { z28.d - z31.d }"
+
+  -
+    input:
+      bytes: [ 0x11, 0x18, 0xfd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w8, 1, vgx4], { z0.d - z3.d }, { z28.d - z31.d }"
+
+  -
+    input:
+      bytes: [ 0x10, 0x5a, 0xf5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w10, 0, vgx4], { z16.d - z19.d }, { z20.d - z23.d }"
+
+  -
+    input:
+      bytes: [ 0x10, 0x5a, 0xf5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w10, 0, vgx4], { z16.d - z19.d }, { z20.d - z23.d }"
+
+  -
+    input:
+      bytes: [ 0x90, 0x19, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w8, 0, vgx4], { z12.d - z15.d }, { z0.d - z3.d }"
+
+  -
+    input:
+      bytes: [ 0x90, 0x19, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w8, 0, vgx4], { z12.d - z15.d }, { z0.d - z3.d }"
+
+  -
+    input:
+      bytes: [ 0x11, 0x58, 0xf9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w10, 1, vgx4], { z0.d - z3.d }, { z24.d - z27.d }"
+
+  -
+    input:
+      bytes: [ 0x11, 0x58, 0xf9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w10, 1, vgx4], { z0.d - z3.d }, { z24.d - z27.d }"
+
+  -
+    input:
+      bytes: [ 0x95, 0x1a, 0xfd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w8, 5, vgx4], { z20.d - z23.d }, { z28.d - z31.d }"
+
+  -
+    input:
+      bytes: [ 0x95, 0x1a, 0xfd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w8, 5, vgx4], { z20.d - z23.d }, { z28.d - z31.d }"
+
+  -
+    input:
+      bytes: [ 0x12, 0x79, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w11, 2, vgx4], { z8.d - z11.d }, { z0.d - z3.d }"
+
+  -
+    input:
+      bytes: [ 0x12, 0x79, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w11, 2, vgx4], { z8.d - z11.d }, { z0.d - z3.d }"
+
+  -
+    input:
+      bytes: [ 0x97, 0x39, 0xe9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w9, 7, vgx4], { z12.d - z15.d }, { z8.d - z11.d }"
+
+  -
+    input:
+      bytes: [ 0x97, 0x39, 0xe9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w9, 7, vgx4], { z12.d - z15.d }, { z8.d - z11.d }"
+
+  -
+    input:
+      bytes: [ 0x00, 0xab, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add { z0.d - z3.d }, { z0.d - z3.d }, z0.d"
+
+  -
+    input:
+      bytes: [ 0x14, 0xab, 0xe5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add { z20.d - z23.d }, { z20.d - z23.d }, z5.d"
+
+  -
+    input:
+      bytes: [ 0x14, 0xab, 0xe8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add { z20.d - z23.d }, { z20.d - z23.d }, z8.d"
+
+  -
+    input:
+      bytes: [ 0x1c, 0xab, 0xef, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add { z28.d - z31.d }, { z28.d - z31.d }, z15.d"
+
+  -
+    input:
+      bytes: [ 0x10, 0x18, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w8, 0, vgx4], { z0.d - z3.d }, { z0.d - z3.d }"
+
+  -
+    input:
+      bytes: [ 0x10, 0x18, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w8, 0, vgx4], { z0.d - z3.d }, { z0.d - z3.d }"
+
+  -
+    input:
+      bytes: [ 0x15, 0x59, 0xf5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w10, 5, vgx4], { z8.d - z11.d }, { z20.d - z23.d }"
+
+  -
+    input:
+      bytes: [ 0x15, 0x59, 0xf5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w10, 5, vgx4], { z8.d - z11.d }, { z20.d - z23.d }"
+
+  -
+    input:
+      bytes: [ 0x97, 0x79, 0xe9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w11, 7, vgx4], { z12.d - z15.d }, { z8.d - z11.d }"
+
+  -
+    input:
+      bytes: [ 0x97, 0x79, 0xe9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w11, 7, vgx4], { z12.d - z15.d }, { z8.d - z11.d }"
+
+  -
+    input:
+      bytes: [ 0x97, 0x7b, 0xfd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w11, 7, vgx4], { z28.d - z31.d }, { z28.d - z31.d }"
+
+  -
+    input:
+      bytes: [ 0x97, 0x7b, 0xfd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w11, 7, vgx4], { z28.d - z31.d }, { z28.d - z31.d }"
+
+  -
+    input:
+      bytes: [ 0x15, 0x1a, 0xf1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w8, 5, vgx4], { z16.d - z19.d }, { z16.d - z19.d }"
+
+  -
+    input:
+      bytes: [ 0x15, 0x1a, 0xf1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w8, 5, vgx4], { z16.d - z19.d }, { z16.d - z19.d }"
+
+  -
+    input:
+      bytes: [ 0x11, 0x18, 0xfd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w8, 1, vgx4], { z0.d - z3.d }, { z28.d - z31.d }"
+
+  -
+    input:
+      bytes: [ 0x11, 0x18, 0xfd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w8, 1, vgx4], { z0.d - z3.d }, { z28.d - z31.d }"
+
+  -
+    input:
+      bytes: [ 0x10, 0x5a, 0xf5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w10, 0, vgx4], { z16.d - z19.d }, { z20.d - z23.d }"
+
+  -
+    input:
+      bytes: [ 0x10, 0x5a, 0xf5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w10, 0, vgx4], { z16.d - z19.d }, { z20.d - z23.d }"
+
+  -
+    input:
+      bytes: [ 0x90, 0x19, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w8, 0, vgx4], { z12.d - z15.d }, { z0.d - z3.d }"
+
+  -
+    input:
+      bytes: [ 0x90, 0x19, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w8, 0, vgx4], { z12.d - z15.d }, { z0.d - z3.d }"
+
+  -
+    input:
+      bytes: [ 0x11, 0x58, 0xf9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w10, 1, vgx4], { z0.d - z3.d }, { z24.d - z27.d }"
+
+  -
+    input:
+      bytes: [ 0x11, 0x58, 0xf9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w10, 1, vgx4], { z0.d - z3.d }, { z24.d - z27.d }"
+
+  -
+    input:
+      bytes: [ 0x95, 0x1a, 0xfd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w8, 5, vgx4], { z20.d - z23.d }, { z28.d - z31.d }"
+
+  -
+    input:
+      bytes: [ 0x95, 0x1a, 0xfd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w8, 5, vgx4], { z20.d - z23.d }, { z28.d - z31.d }"
+
+  -
+    input:
+      bytes: [ 0x12, 0x79, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w11, 2, vgx4], { z8.d - z11.d }, { z0.d - z3.d }"
+
+  -
+    input:
+      bytes: [ 0x12, 0x79, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w11, 2, vgx4], { z8.d - z11.d }, { z0.d - z3.d }"
+
+  -
+    input:
+      bytes: [ 0x97, 0x39, 0xe9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w9, 7, vgx4], { z12.d - z15.d }, { z8.d - z11.d }"
+
+  -
+    input:
+      bytes: [ 0x97, 0x39, 0xe9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add za.d[w9, 7, vgx4], { z12.d - z15.d }, { z8.d - z11.d }"
+
+  -
+    input:
+      bytes: [ 0x00, 0xab, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add { z0.b - z3.b }, { z0.b - z3.b }, z0.b"
+
+  -
+    input:
+      bytes: [ 0x14, 0xab, 0x25, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add { z20.b - z23.b }, { z20.b - z23.b }, z5.b"
+
+  -
+    input:
+      bytes: [ 0x14, 0xab, 0x28, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add { z20.b - z23.b }, { z20.b - z23.b }, z8.b"
+
+  -
+    input:
+      bytes: [ 0x1c, 0xab, 0x2f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add { z28.b - z31.b }, { z28.b - z31.b }, z15.b"
diff --git a/tests/MC/AArch64/SME2/bfadd.s.yaml b/tests/MC/AArch64/SME2/bfadd.s.yaml
new file mode 100644
index 000000000..81131eac3
--- /dev/null
+++ b/tests/MC/AArch64/SME2/bfadd.s.yaml
@@ -0,0 +1,480 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x1c, 0xe4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfadd za.h[w8, 0, vgx2], { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x1c, 0xe4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfadd za.h[w8, 0, vgx2], { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x45, 0x5d, 0xe4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfadd za.h[w10, 5, vgx2], { z10.h, z11.h }"
+
+  -
+    input:
+      bytes: [ 0x45, 0x5d, 0xe4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfadd za.h[w10, 5, vgx2], { z10.h, z11.h }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x7d, 0xe4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfadd za.h[w11, 7, vgx2], { z12.h, z13.h }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x7d, 0xe4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfadd za.h[w11, 7, vgx2], { z12.h, z13.h }"
+
+  -
+    input:
+      bytes: [ 0xc7, 0x7f, 0xe4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfadd za.h[w11, 7, vgx2], { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0xc7, 0x7f, 0xe4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfadd za.h[w11, 7, vgx2], { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x05, 0x1e, 0xe4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfadd za.h[w8, 5, vgx2], { z16.h, z17.h }"
+
+  -
+    input:
+      bytes: [ 0x05, 0x1e, 0xe4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfadd za.h[w8, 5, vgx2], { z16.h, z17.h }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x1c, 0xe4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfadd za.h[w8, 1, vgx2], { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x1c, 0xe4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfadd za.h[w8, 1, vgx2], { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x40, 0x5e, 0xe4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfadd za.h[w10, 0, vgx2], { z18.h, z19.h }"
+
+  -
+    input:
+      bytes: [ 0x40, 0x5e, 0xe4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfadd za.h[w10, 0, vgx2], { z18.h, z19.h }"
+
+  -
+    input:
+      bytes: [ 0x80, 0x1d, 0xe4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfadd za.h[w8, 0, vgx2], { z12.h, z13.h }"
+
+  -
+    input:
+      bytes: [ 0x80, 0x1d, 0xe4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfadd za.h[w8, 0, vgx2], { z12.h, z13.h }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x5c, 0xe4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfadd za.h[w10, 1, vgx2], { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x5c, 0xe4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfadd za.h[w10, 1, vgx2], { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x1e, 0xe4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfadd za.h[w8, 5, vgx2], { z22.h, z23.h }"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x1e, 0xe4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfadd za.h[w8, 5, vgx2], { z22.h, z23.h }"
+
+  -
+    input:
+      bytes: [ 0x02, 0x7d, 0xe4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfadd za.h[w11, 2, vgx2], { z8.h, z9.h }"
+
+  -
+    input:
+      bytes: [ 0x02, 0x7d, 0xe4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfadd za.h[w11, 2, vgx2], { z8.h, z9.h }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x3d, 0xe4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfadd za.h[w9, 7, vgx2], { z12.h, z13.h }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x3d, 0xe4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfadd za.h[w9, 7, vgx2], { z12.h, z13.h }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x1c, 0xe5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfadd za.h[w8, 0, vgx4], { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x1c, 0xe5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfadd za.h[w8, 0, vgx4], { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x05, 0x5d, 0xe5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfadd za.h[w10, 5, vgx4], { z8.h - z11.h }"
+
+  -
+    input:
+      bytes: [ 0x05, 0x5d, 0xe5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfadd za.h[w10, 5, vgx4], { z8.h - z11.h }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x7d, 0xe5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfadd za.h[w11, 7, vgx4], { z12.h - z15.h }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x7d, 0xe5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfadd za.h[w11, 7, vgx4], { z12.h - z15.h }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x7f, 0xe5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfadd za.h[w11, 7, vgx4], { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x7f, 0xe5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfadd za.h[w11, 7, vgx4], { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x05, 0x1e, 0xe5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfadd za.h[w8, 5, vgx4], { z16.h - z19.h }"
+
+  -
+    input:
+      bytes: [ 0x05, 0x1e, 0xe5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfadd za.h[w8, 5, vgx4], { z16.h - z19.h }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x1c, 0xe5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfadd za.h[w8, 1, vgx4], { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x1c, 0xe5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfadd za.h[w8, 1, vgx4], { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x5e, 0xe5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfadd za.h[w10, 0, vgx4], { z16.h - z19.h }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x5e, 0xe5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfadd za.h[w10, 0, vgx4], { z16.h - z19.h }"
+
+  -
+    input:
+      bytes: [ 0x80, 0x1d, 0xe5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfadd za.h[w8, 0, vgx4], { z12.h - z15.h }"
+
+  -
+    input:
+      bytes: [ 0x80, 0x1d, 0xe5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfadd za.h[w8, 0, vgx4], { z12.h - z15.h }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x5c, 0xe5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfadd za.h[w10, 1, vgx4], { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x5c, 0xe5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfadd za.h[w10, 1, vgx4], { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x85, 0x1e, 0xe5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfadd za.h[w8, 5, vgx4], { z20.h - z23.h }"
+
+  -
+    input:
+      bytes: [ 0x85, 0x1e, 0xe5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfadd za.h[w8, 5, vgx4], { z20.h - z23.h }"
+
+  -
+    input:
+      bytes: [ 0x02, 0x7d, 0xe5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfadd za.h[w11, 2, vgx4], { z8.h - z11.h }"
+
+  -
+    input:
+      bytes: [ 0x02, 0x7d, 0xe5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfadd za.h[w11, 2, vgx4], { z8.h - z11.h }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x3d, 0xe5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfadd za.h[w9, 7, vgx4], { z12.h - z15.h }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x3d, 0xe5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfadd za.h[w9, 7, vgx4], { z12.h - z15.h }"
diff --git a/tests/MC/AArch64/SME2/bfclamp.s.yaml b/tests/MC/AArch64/SME2/bfclamp.s.yaml
new file mode 100644
index 000000000..55e2467cc
--- /dev/null
+++ b/tests/MC/AArch64/SME2/bfclamp.s.yaml
@@ -0,0 +1,80 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfclamp { z0.h, z1.h }, z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x54, 0xc1, 0x35, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfclamp { z20.h, z21.h }, z10.h, z21.h"
+
+  -
+    input:
+      bytes: [ 0xb6, 0xc1, 0x28, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfclamp { z22.h, z23.h }, z13.h, z8.h"
+
+  -
+    input:
+      bytes: [ 0xfe, 0xc3, 0x3f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfclamp { z30.h, z31.h }, z31.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc8, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfclamp { z0.h - z3.h }, z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x54, 0xc9, 0x35, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfclamp { z20.h - z23.h }, z10.h, z21.h"
+
+  -
+    input:
+      bytes: [ 0xb4, 0xc9, 0x28, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfclamp { z20.h - z23.h }, z13.h, z8.h"
+
+  -
+    input:
+      bytes: [ 0xfc, 0xcb, 0x3f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfclamp { z28.h - z31.h }, z31.h, z31.h"
diff --git a/tests/MC/AArch64/SME2/bfcvt.s.yaml b/tests/MC/AArch64/SME2/bfcvt.s.yaml
new file mode 100644
index 000000000..d7a6cff81
--- /dev/null
+++ b/tests/MC/AArch64/SME2/bfcvt.s.yaml
@@ -0,0 +1,40 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfcvt z0.h, { z0.s, z1.s }"
+
+  -
+    input:
+      bytes: [ 0x55, 0xe1, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfcvt z21.h, { z10.s, z11.s }"
+
+  -
+    input:
+      bytes: [ 0x97, 0xe1, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfcvt z23.h, { z12.s, z13.s }"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xe3, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfcvt z31.h, { z30.s, z31.s }"
diff --git a/tests/MC/AArch64/SME2/bfcvtn.s.yaml b/tests/MC/AArch64/SME2/bfcvtn.s.yaml
new file mode 100644
index 000000000..4b62a4b0e
--- /dev/null
+++ b/tests/MC/AArch64/SME2/bfcvtn.s.yaml
@@ -0,0 +1,40 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0xe0, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfcvtn z0.h, { z0.s, z1.s }"
+
+  -
+    input:
+      bytes: [ 0x75, 0xe1, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfcvtn z21.h, { z10.s, z11.s }"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xe1, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfcvtn z23.h, { z12.s, z13.s }"
+
+  -
+    input:
+      bytes: [ 0xff, 0xe3, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfcvtn z31.h, { z30.s, z31.s }"
diff --git a/tests/MC/AArch64/SME2/bfdot.s.yaml b/tests/MC/AArch64/SME2/bfdot.s.yaml
new file mode 100644
index 000000000..1d178868d
--- /dev/null
+++ b/tests/MC/AArch64/SME2/bfdot.s.yaml
@@ -0,0 +1,1440 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x10, 0x10, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w8, 0, vgx2], { z0.h, z1.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x10, 0x10, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w8, 0, vgx2], { z0.h, z1.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x55, 0x51, 0x25, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w10, 5, vgx2], { z10.h, z11.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0x55, 0x51, 0x25, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w10, 5, vgx2], { z10.h, z11.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x71, 0x28, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w11, 7, vgx2], { z13.h, z14.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x71, 0x28, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w11, 7, vgx2], { z13.h, z14.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0xf7, 0x73, 0x2f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w11, 7, vgx2], { z31.h, z0.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0xf7, 0x73, 0x2f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w11, 7, vgx2], { z31.h, z0.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0x35, 0x12, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w8, 5, vgx2], { z17.h, z18.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x35, 0x12, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w8, 5, vgx2], { z17.h, z18.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x31, 0x10, 0x2e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w8, 1, vgx2], { z1.h, z2.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x31, 0x10, 0x2e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w8, 1, vgx2], { z1.h, z2.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x70, 0x52, 0x24, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w10, 0, vgx2], { z19.h, z20.h }, z4.h"
+
+  -
+    input:
+      bytes: [ 0x70, 0x52, 0x24, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w10, 0, vgx2], { z19.h, z20.h }, z4.h"
+
+  -
+    input:
+      bytes: [ 0x90, 0x11, 0x22, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w8, 0, vgx2], { z12.h, z13.h }, z2.h"
+
+  -
+    input:
+      bytes: [ 0x90, 0x11, 0x22, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w8, 0, vgx2], { z12.h, z13.h }, z2.h"
+
+  -
+    input:
+      bytes: [ 0x31, 0x50, 0x2a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w10, 1, vgx2], { z1.h, z2.h }, z10.h"
+
+  -
+    input:
+      bytes: [ 0x31, 0x50, 0x2a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w10, 1, vgx2], { z1.h, z2.h }, z10.h"
+
+  -
+    input:
+      bytes: [ 0xd5, 0x12, 0x2e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w8, 5, vgx2], { z22.h, z23.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0xd5, 0x12, 0x2e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w8, 5, vgx2], { z22.h, z23.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x32, 0x71, 0x21, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w11, 2, vgx2], { z9.h, z10.h }, z1.h"
+
+  -
+    input:
+      bytes: [ 0x32, 0x71, 0x21, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w11, 2, vgx2], { z9.h, z10.h }, z1.h"
+
+  -
+    input:
+      bytes: [ 0x97, 0x31, 0x2b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w9, 7, vgx2], { z12.h, z13.h }, z11.h"
+
+  -
+    input:
+      bytes: [ 0x97, 0x31, 0x2b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w9, 7, vgx2], { z12.h, z13.h }, z11.h"
+
+  -
+    input:
+      bytes: [ 0x18, 0x10, 0x50, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w8, 0, vgx2], { z0.h, z1.h }, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x18, 0x10, 0x50, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w8, 0, vgx2], { z0.h, z1.h }, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x5d, 0x55, 0x55, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w10, 5, vgx2], { z10.h, z11.h }, z5.h[1]"
+
+  -
+    input:
+      bytes: [ 0x5d, 0x55, 0x55, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w10, 5, vgx2], { z10.h, z11.h }, z5.h[1]"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x7d, 0x58, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w11, 7, vgx2], { z12.h, z13.h }, z8.h[3]"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x7d, 0x58, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w11, 7, vgx2], { z12.h, z13.h }, z8.h[3]"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x7f, 0x5f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w11, 7, vgx2], { z30.h, z31.h }, z15.h[3]"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x7f, 0x5f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w11, 7, vgx2], { z30.h, z31.h }, z15.h[3]"
+
+  -
+    input:
+      bytes: [ 0x1d, 0x1e, 0x50, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w8, 5, vgx2], { z16.h, z17.h }, z0.h[3]"
+
+  -
+    input:
+      bytes: [ 0x1d, 0x1e, 0x50, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w8, 5, vgx2], { z16.h, z17.h }, z0.h[3]"
+
+  -
+    input:
+      bytes: [ 0x19, 0x14, 0x5e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w8, 1, vgx2], { z0.h, z1.h }, z14.h[1]"
+
+  -
+    input:
+      bytes: [ 0x19, 0x14, 0x5e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w8, 1, vgx2], { z0.h, z1.h }, z14.h[1]"
+
+  -
+    input:
+      bytes: [ 0x58, 0x56, 0x54, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w10, 0, vgx2], { z18.h, z19.h }, z4.h[1]"
+
+  -
+    input:
+      bytes: [ 0x58, 0x56, 0x54, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w10, 0, vgx2], { z18.h, z19.h }, z4.h[1]"
+
+  -
+    input:
+      bytes: [ 0x98, 0x19, 0x52, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w8, 0, vgx2], { z12.h, z13.h }, z2.h[2]"
+
+  -
+    input:
+      bytes: [ 0x98, 0x19, 0x52, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w8, 0, vgx2], { z12.h, z13.h }, z2.h[2]"
+
+  -
+    input:
+      bytes: [ 0x19, 0x58, 0x5a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w10, 1, vgx2], { z0.h, z1.h }, z10.h[2]"
+
+  -
+    input:
+      bytes: [ 0x19, 0x58, 0x5a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w10, 1, vgx2], { z0.h, z1.h }, z10.h[2]"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x1a, 0x5e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w8, 5, vgx2], { z22.h, z23.h }, z14.h[2]"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x1a, 0x5e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w8, 5, vgx2], { z22.h, z23.h }, z14.h[2]"
+
+  -
+    input:
+      bytes: [ 0x1a, 0x75, 0x51, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w11, 2, vgx2], { z8.h, z9.h }, z1.h[1]"
+
+  -
+    input:
+      bytes: [ 0x1a, 0x75, 0x51, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w11, 2, vgx2], { z8.h, z9.h }, z1.h[1]"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x39, 0x5b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w9, 7, vgx2], { z12.h, z13.h }, z11.h[2]"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x39, 0x5b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w9, 7, vgx2], { z12.h, z13.h }, z11.h[2]"
+
+  -
+    input:
+      bytes: [ 0x10, 0x10, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w8, 0, vgx2], { z0.h, z1.h }, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x10, 0x10, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w8, 0, vgx2], { z0.h, z1.h }, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x55, 0x51, 0xb4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w10, 5, vgx2], { z10.h, z11.h }, { z20.h, z21.h }"
+
+  -
+    input:
+      bytes: [ 0x55, 0x51, 0xb4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w10, 5, vgx2], { z10.h, z11.h }, { z20.h, z21.h }"
+
+  -
+    input:
+      bytes: [ 0x97, 0x71, 0xa8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w11, 7, vgx2], { z12.h, z13.h }, { z8.h, z9.h }"
+
+  -
+    input:
+      bytes: [ 0x97, 0x71, 0xa8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w11, 7, vgx2], { z12.h, z13.h }, { z8.h, z9.h }"
+
+  -
+    input:
+      bytes: [ 0xd7, 0x73, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w11, 7, vgx2], { z30.h, z31.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0xd7, 0x73, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w11, 7, vgx2], { z30.h, z31.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x15, 0x12, 0xb0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w8, 5, vgx2], { z16.h, z17.h }, { z16.h, z17.h }"
+
+  -
+    input:
+      bytes: [ 0x15, 0x12, 0xb0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w8, 5, vgx2], { z16.h, z17.h }, { z16.h, z17.h }"
+
+  -
+    input:
+      bytes: [ 0x11, 0x10, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w8, 1, vgx2], { z0.h, z1.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x11, 0x10, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w8, 1, vgx2], { z0.h, z1.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x50, 0x52, 0xb4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w10, 0, vgx2], { z18.h, z19.h }, { z20.h, z21.h }"
+
+  -
+    input:
+      bytes: [ 0x50, 0x52, 0xb4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w10, 0, vgx2], { z18.h, z19.h }, { z20.h, z21.h }"
+
+  -
+    input:
+      bytes: [ 0x90, 0x11, 0xa2, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w8, 0, vgx2], { z12.h, z13.h }, { z2.h, z3.h }"
+
+  -
+    input:
+      bytes: [ 0x90, 0x11, 0xa2, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w8, 0, vgx2], { z12.h, z13.h }, { z2.h, z3.h }"
+
+  -
+    input:
+      bytes: [ 0x11, 0x50, 0xba, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w10, 1, vgx2], { z0.h, z1.h }, { z26.h, z27.h }"
+
+  -
+    input:
+      bytes: [ 0x11, 0x50, 0xba, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w10, 1, vgx2], { z0.h, z1.h }, { z26.h, z27.h }"
+
+  -
+    input:
+      bytes: [ 0xd5, 0x12, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w8, 5, vgx2], { z22.h, z23.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0xd5, 0x12, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w8, 5, vgx2], { z22.h, z23.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x12, 0x71, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w11, 2, vgx2], { z8.h, z9.h }, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x12, 0x71, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w11, 2, vgx2], { z8.h, z9.h }, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x97, 0x31, 0xaa, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w9, 7, vgx2], { z12.h, z13.h }, { z10.h, z11.h }"
+
+  -
+    input:
+      bytes: [ 0x97, 0x31, 0xaa, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w9, 7, vgx2], { z12.h, z13.h }, { z10.h, z11.h }"
+
+  -
+    input:
+      bytes: [ 0x10, 0x10, 0x30, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w8, 0, vgx4], { z0.h - z3.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x10, 0x10, 0x30, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w8, 0, vgx4], { z0.h - z3.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x55, 0x51, 0x35, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w10, 5, vgx4], { z10.h - z13.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0x55, 0x51, 0x35, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w10, 5, vgx4], { z10.h - z13.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x71, 0x38, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w11, 7, vgx4], { z13.h - z16.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x71, 0x38, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w11, 7, vgx4], { z13.h - z16.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0xf7, 0x73, 0x3f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w11, 7, vgx4], { z31.h, z0.h, z1.h, z2.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0xf7, 0x73, 0x3f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w11, 7, vgx4], { z31.h, z0.h, z1.h, z2.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0x35, 0x12, 0x30, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w8, 5, vgx4], { z17.h - z20.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x35, 0x12, 0x30, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w8, 5, vgx4], { z17.h - z20.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x31, 0x10, 0x3e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w8, 1, vgx4], { z1.h - z4.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x31, 0x10, 0x3e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w8, 1, vgx4], { z1.h - z4.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x70, 0x52, 0x34, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w10, 0, vgx4], { z19.h - z22.h }, z4.h"
+
+  -
+    input:
+      bytes: [ 0x70, 0x52, 0x34, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w10, 0, vgx4], { z19.h - z22.h }, z4.h"
+
+  -
+    input:
+      bytes: [ 0x90, 0x11, 0x32, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w8, 0, vgx4], { z12.h - z15.h }, z2.h"
+
+  -
+    input:
+      bytes: [ 0x90, 0x11, 0x32, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w8, 0, vgx4], { z12.h - z15.h }, z2.h"
+
+  -
+    input:
+      bytes: [ 0x31, 0x50, 0x3a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w10, 1, vgx4], { z1.h - z4.h }, z10.h"
+
+  -
+    input:
+      bytes: [ 0x31, 0x50, 0x3a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w10, 1, vgx4], { z1.h - z4.h }, z10.h"
+
+  -
+    input:
+      bytes: [ 0xd5, 0x12, 0x3e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w8, 5, vgx4], { z22.h - z25.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0xd5, 0x12, 0x3e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w8, 5, vgx4], { z22.h - z25.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x32, 0x71, 0x31, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w11, 2, vgx4], { z9.h - z12.h }, z1.h"
+
+  -
+    input:
+      bytes: [ 0x32, 0x71, 0x31, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w11, 2, vgx4], { z9.h - z12.h }, z1.h"
+
+  -
+    input:
+      bytes: [ 0x97, 0x31, 0x3b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w9, 7, vgx4], { z12.h - z15.h }, z11.h"
+
+  -
+    input:
+      bytes: [ 0x97, 0x31, 0x3b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w9, 7, vgx4], { z12.h - z15.h }, z11.h"
+
+  -
+    input:
+      bytes: [ 0x18, 0x90, 0x50, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w8, 0, vgx4], { z0.h - z3.h }, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x18, 0x90, 0x50, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w8, 0, vgx4], { z0.h - z3.h }, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x1d, 0xd5, 0x55, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w10, 5, vgx4], { z8.h - z11.h }, z5.h[1]"
+
+  -
+    input:
+      bytes: [ 0x1d, 0xd5, 0x55, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w10, 5, vgx4], { z8.h - z11.h }, z5.h[1]"
+
+  -
+    input:
+      bytes: [ 0x9f, 0xfd, 0x58, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w11, 7, vgx4], { z12.h - z15.h }, z8.h[3]"
+
+  -
+    input:
+      bytes: [ 0x9f, 0xfd, 0x58, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w11, 7, vgx4], { z12.h - z15.h }, z8.h[3]"
+
+  -
+    input:
+      bytes: [ 0x9f, 0xff, 0x5f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w11, 7, vgx4], { z28.h - z31.h }, z15.h[3]"
+
+  -
+    input:
+      bytes: [ 0x9f, 0xff, 0x5f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w11, 7, vgx4], { z28.h - z31.h }, z15.h[3]"
+
+  -
+    input:
+      bytes: [ 0x1d, 0x9e, 0x50, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w8, 5, vgx4], { z16.h - z19.h }, z0.h[3]"
+
+  -
+    input:
+      bytes: [ 0x1d, 0x9e, 0x50, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w8, 5, vgx4], { z16.h - z19.h }, z0.h[3]"
+
+  -
+    input:
+      bytes: [ 0x19, 0x94, 0x5e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w8, 1, vgx4], { z0.h - z3.h }, z14.h[1]"
+
+  -
+    input:
+      bytes: [ 0x19, 0x94, 0x5e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w8, 1, vgx4], { z0.h - z3.h }, z14.h[1]"
+
+  -
+    input:
+      bytes: [ 0x18, 0xd6, 0x54, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w10, 0, vgx4], { z16.h - z19.h }, z4.h[1]"
+
+  -
+    input:
+      bytes: [ 0x18, 0xd6, 0x54, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w10, 0, vgx4], { z16.h - z19.h }, z4.h[1]"
+
+  -
+    input:
+      bytes: [ 0x98, 0x99, 0x52, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w8, 0, vgx4], { z12.h - z15.h }, z2.h[2]"
+
+  -
+    input:
+      bytes: [ 0x98, 0x99, 0x52, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w8, 0, vgx4], { z12.h - z15.h }, z2.h[2]"
+
+  -
+    input:
+      bytes: [ 0x19, 0xd8, 0x5a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w10, 1, vgx4], { z0.h - z3.h }, z10.h[2]"
+
+  -
+    input:
+      bytes: [ 0x19, 0xd8, 0x5a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w10, 1, vgx4], { z0.h - z3.h }, z10.h[2]"
+
+  -
+    input:
+      bytes: [ 0x9d, 0x9a, 0x5e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w8, 5, vgx4], { z20.h - z23.h }, z14.h[2]"
+
+  -
+    input:
+      bytes: [ 0x9d, 0x9a, 0x5e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w8, 5, vgx4], { z20.h - z23.h }, z14.h[2]"
+
+  -
+    input:
+      bytes: [ 0x1a, 0xf5, 0x51, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w11, 2, vgx4], { z8.h - z11.h }, z1.h[1]"
+
+  -
+    input:
+      bytes: [ 0x1a, 0xf5, 0x51, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w11, 2, vgx4], { z8.h - z11.h }, z1.h[1]"
+
+  -
+    input:
+      bytes: [ 0x9f, 0xb9, 0x5b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w9, 7, vgx4], { z12.h - z15.h }, z11.h[2]"
+
+  -
+    input:
+      bytes: [ 0x9f, 0xb9, 0x5b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w9, 7, vgx4], { z12.h - z15.h }, z11.h[2]"
+
+  -
+    input:
+      bytes: [ 0x10, 0x10, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w8, 0, vgx4], { z0.h - z3.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x10, 0x10, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w8, 0, vgx4], { z0.h - z3.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x15, 0x51, 0xb5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w10, 5, vgx4], { z8.h - z11.h }, { z20.h - z23.h }"
+
+  -
+    input:
+      bytes: [ 0x15, 0x51, 0xb5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w10, 5, vgx4], { z8.h - z11.h }, { z20.h - z23.h }"
+
+  -
+    input:
+      bytes: [ 0x97, 0x71, 0xa9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w11, 7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }"
+
+  -
+    input:
+      bytes: [ 0x97, 0x71, 0xa9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w11, 7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }"
+
+  -
+    input:
+      bytes: [ 0x97, 0x73, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w11, 7, vgx4], { z28.h - z31.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x97, 0x73, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w11, 7, vgx4], { z28.h - z31.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x15, 0x12, 0xb1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w8, 5, vgx4], { z16.h - z19.h }, { z16.h - z19.h }"
+
+  -
+    input:
+      bytes: [ 0x15, 0x12, 0xb1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w8, 5, vgx4], { z16.h - z19.h }, { z16.h - z19.h }"
+
+  -
+    input:
+      bytes: [ 0x11, 0x10, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w8, 1, vgx4], { z0.h - z3.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x11, 0x10, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w8, 1, vgx4], { z0.h - z3.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x10, 0x52, 0xb5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w10, 0, vgx4], { z16.h - z19.h }, { z20.h - z23.h }"
+
+  -
+    input:
+      bytes: [ 0x10, 0x52, 0xb5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w10, 0, vgx4], { z16.h - z19.h }, { z20.h - z23.h }"
+
+  -
+    input:
+      bytes: [ 0x90, 0x11, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w8, 0, vgx4], { z12.h - z15.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x90, 0x11, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w8, 0, vgx4], { z12.h - z15.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x11, 0x50, 0xb9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w10, 1, vgx4], { z0.h - z3.h }, { z24.h - z27.h }"
+
+  -
+    input:
+      bytes: [ 0x11, 0x50, 0xb9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w10, 1, vgx4], { z0.h - z3.h }, { z24.h - z27.h }"
+
+  -
+    input:
+      bytes: [ 0x95, 0x12, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w8, 5, vgx4], { z20.h - z23.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x95, 0x12, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w8, 5, vgx4], { z20.h - z23.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x12, 0x71, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w11, 2, vgx4], { z8.h - z11.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x12, 0x71, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w11, 2, vgx4], { z8.h - z11.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x97, 0x31, 0xa9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w9, 7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }"
+
+  -
+    input:
+      bytes: [ 0x97, 0x31, 0xa9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot za.s[w9, 7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }"
diff --git a/tests/MC/AArch64/SME2/bfmax.s.yaml b/tests/MC/AArch64/SME2/bfmax.s.yaml
new file mode 100644
index 000000000..b35009278
--- /dev/null
+++ b/tests/MC/AArch64/SME2/bfmax.s.yaml
@@ -0,0 +1,160 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xa1, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmax { z0.h, z1.h }, { z0.h, z1.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x14, 0xa1, 0x25, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmax { z20.h, z21.h }, { z20.h, z21.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0x16, 0xa1, 0x28, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmax { z22.h, z23.h }, { z22.h, z23.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0x1e, 0xa1, 0x2f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmax { z30.h, z31.h }, { z30.h, z31.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0xb1, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmax { z0.h, z1.h }, { z0.h, z1.h }, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x14, 0xb1, 0x34, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmax { z20.h, z21.h }, { z20.h, z21.h }, { z20.h, z21.h }"
+
+  -
+    input:
+      bytes: [ 0x16, 0xb1, 0x28, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmax { z22.h, z23.h }, { z22.h, z23.h }, { z8.h, z9.h }"
+
+  -
+    input:
+      bytes: [ 0x1e, 0xb1, 0x3e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmax { z30.h, z31.h }, { z30.h, z31.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa9, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmax { z0.h - z3.h }, { z0.h - z3.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x14, 0xa9, 0x25, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmax { z20.h - z23.h }, { z20.h - z23.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0x14, 0xa9, 0x28, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmax { z20.h - z23.h }, { z20.h - z23.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0x1c, 0xa9, 0x2f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmax { z28.h - z31.h }, { z28.h - z31.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0xb9, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmax { z0.h - z3.h }, { z0.h - z3.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x14, 0xb9, 0x34, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmax { z20.h - z23.h }, { z20.h - z23.h }, { z20.h - z23.h }"
+
+  -
+    input:
+      bytes: [ 0x14, 0xb9, 0x28, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmax { z20.h - z23.h }, { z20.h - z23.h }, { z8.h - z11.h }"
+
+  -
+    input:
+      bytes: [ 0x1c, 0xb9, 0x3c, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmax { z28.h - z31.h }, { z28.h - z31.h }, { z28.h - z31.h }"
diff --git a/tests/MC/AArch64/SME2/bfmaxnm.s.yaml b/tests/MC/AArch64/SME2/bfmaxnm.s.yaml
new file mode 100644
index 000000000..4311bd5e8
--- /dev/null
+++ b/tests/MC/AArch64/SME2/bfmaxnm.s.yaml
@@ -0,0 +1,160 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0xa1, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmaxnm { z0.h, z1.h }, { z0.h, z1.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x34, 0xa1, 0x25, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmaxnm { z20.h, z21.h }, { z20.h, z21.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0x36, 0xa1, 0x28, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmaxnm { z22.h, z23.h }, { z22.h, z23.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0x3e, 0xa1, 0x2f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmaxnm { z30.h, z31.h }, { z30.h, z31.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0xb1, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmaxnm { z0.h, z1.h }, { z0.h, z1.h }, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x34, 0xb1, 0x34, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmaxnm { z20.h, z21.h }, { z20.h, z21.h }, { z20.h, z21.h }"
+
+  -
+    input:
+      bytes: [ 0x36, 0xb1, 0x28, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmaxnm { z22.h, z23.h }, { z22.h, z23.h }, { z8.h, z9.h }"
+
+  -
+    input:
+      bytes: [ 0x3e, 0xb1, 0x3e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmaxnm { z30.h, z31.h }, { z30.h, z31.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa9, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmaxnm { z0.h - z3.h }, { z0.h - z3.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x34, 0xa9, 0x25, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmaxnm { z20.h - z23.h }, { z20.h - z23.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0x34, 0xa9, 0x28, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmaxnm { z20.h - z23.h }, { z20.h - z23.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0x3c, 0xa9, 0x2f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmaxnm { z28.h - z31.h }, { z28.h - z31.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0xb9, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmaxnm { z0.h - z3.h }, { z0.h - z3.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x34, 0xb9, 0x34, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmaxnm { z20.h - z23.h }, { z20.h - z23.h }, { z20.h - z23.h }"
+
+  -
+    input:
+      bytes: [ 0x34, 0xb9, 0x28, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmaxnm { z20.h - z23.h }, { z20.h - z23.h }, { z8.h - z11.h }"
+
+  -
+    input:
+      bytes: [ 0x3c, 0xb9, 0x3c, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmaxnm { z28.h - z31.h }, { z28.h - z31.h }, { z28.h - z31.h }"
diff --git a/tests/MC/AArch64/SME2/bfmin.s.yaml b/tests/MC/AArch64/SME2/bfmin.s.yaml
new file mode 100644
index 000000000..82added9d
--- /dev/null
+++ b/tests/MC/AArch64/SME2/bfmin.s.yaml
@@ -0,0 +1,160 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x01, 0xa1, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmin { z0.h, z1.h }, { z0.h, z1.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x15, 0xa1, 0x25, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmin { z20.h, z21.h }, { z20.h, z21.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0x17, 0xa1, 0x28, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmin { z22.h, z23.h }, { z22.h, z23.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0x1f, 0xa1, 0x2f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmin { z30.h, z31.h }, { z30.h, z31.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0x01, 0xb1, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmin { z0.h, z1.h }, { z0.h, z1.h }, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x15, 0xb1, 0x34, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmin { z20.h, z21.h }, { z20.h, z21.h }, { z20.h, z21.h }"
+
+  -
+    input:
+      bytes: [ 0x17, 0xb1, 0x28, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmin { z22.h, z23.h }, { z22.h, z23.h }, { z8.h, z9.h }"
+
+  -
+    input:
+      bytes: [ 0x1f, 0xb1, 0x3e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmin { z30.h, z31.h }, { z30.h, z31.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x01, 0xa9, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmin { z0.h - z3.h }, { z0.h - z3.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x15, 0xa9, 0x25, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmin { z20.h - z23.h }, { z20.h - z23.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0x15, 0xa9, 0x28, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmin { z20.h - z23.h }, { z20.h - z23.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0x1d, 0xa9, 0x2f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmin { z28.h - z31.h }, { z28.h - z31.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0x01, 0xb9, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmin { z0.h - z3.h }, { z0.h - z3.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x15, 0xb9, 0x34, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmin { z20.h - z23.h }, { z20.h - z23.h }, { z20.h - z23.h }"
+
+  -
+    input:
+      bytes: [ 0x15, 0xb9, 0x28, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmin { z20.h - z23.h }, { z20.h - z23.h }, { z8.h - z11.h }"
+
+  -
+    input:
+      bytes: [ 0x1d, 0xb9, 0x3c, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmin { z28.h - z31.h }, { z28.h - z31.h }, { z28.h - z31.h }"
diff --git a/tests/MC/AArch64/SME2/bfminnm.s.yaml b/tests/MC/AArch64/SME2/bfminnm.s.yaml
new file mode 100644
index 000000000..366144caf
--- /dev/null
+++ b/tests/MC/AArch64/SME2/bfminnm.s.yaml
@@ -0,0 +1,160 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x21, 0xa1, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfminnm { z0.h, z1.h }, { z0.h, z1.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x35, 0xa1, 0x25, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfminnm { z20.h, z21.h }, { z20.h, z21.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0x37, 0xa1, 0x28, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfminnm { z22.h, z23.h }, { z22.h, z23.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0x3f, 0xa1, 0x2f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfminnm { z30.h, z31.h }, { z30.h, z31.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0x21, 0xb1, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfminnm { z0.h, z1.h }, { z0.h, z1.h }, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x35, 0xb1, 0x34, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfminnm { z20.h, z21.h }, { z20.h, z21.h }, { z20.h, z21.h }"
+
+  -
+    input:
+      bytes: [ 0x37, 0xb1, 0x28, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfminnm { z22.h, z23.h }, { z22.h, z23.h }, { z8.h, z9.h }"
+
+  -
+    input:
+      bytes: [ 0x3f, 0xb1, 0x3e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfminnm { z30.h, z31.h }, { z30.h, z31.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x21, 0xa9, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfminnm { z0.h - z3.h }, { z0.h - z3.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x35, 0xa9, 0x25, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfminnm { z20.h - z23.h }, { z20.h - z23.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0x35, 0xa9, 0x28, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfminnm { z20.h - z23.h }, { z20.h - z23.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0x3d, 0xa9, 0x2f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfminnm { z28.h - z31.h }, { z28.h - z31.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0x21, 0xb9, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfminnm { z0.h - z3.h }, { z0.h - z3.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x35, 0xb9, 0x34, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfminnm { z20.h - z23.h }, { z20.h - z23.h }, { z20.h - z23.h }"
+
+  -
+    input:
+      bytes: [ 0x35, 0xb9, 0x28, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfminnm { z20.h - z23.h }, { z20.h - z23.h }, { z8.h - z11.h }"
+
+  -
+    input:
+      bytes: [ 0x3d, 0xb9, 0x3c, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfminnm { z28.h - z31.h }, { z28.h - z31.h }, { z28.h - z31.h }"
diff --git a/tests/MC/AArch64/SME2/bfmla.s.yaml b/tests/MC/AArch64/SME2/bfmla.s.yaml
new file mode 100644
index 000000000..2e16e02b1
--- /dev/null
+++ b/tests/MC/AArch64/SME2/bfmla.s.yaml
@@ -0,0 +1,1440 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x1c, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w8, 0, vgx2], { z0.h, z1.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x1c, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w8, 0, vgx2], { z0.h, z1.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x45, 0x5d, 0x65, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w10, 5, vgx2], { z10.h, z11.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0x45, 0x5d, 0x65, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w10, 5, vgx2], { z10.h, z11.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0xa7, 0x7d, 0x68, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w11, 7, vgx2], { z13.h, z14.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0xa7, 0x7d, 0x68, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w11, 7, vgx2], { z13.h, z14.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0xe7, 0x7f, 0x6f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w11, 7, vgx2], { z31.h, z0.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0xe7, 0x7f, 0x6f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w11, 7, vgx2], { z31.h, z0.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0x25, 0x1e, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w8, 5, vgx2], { z17.h, z18.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x25, 0x1e, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w8, 5, vgx2], { z17.h, z18.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x21, 0x1c, 0x6e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w8, 1, vgx2], { z1.h, z2.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x21, 0x1c, 0x6e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w8, 1, vgx2], { z1.h, z2.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x60, 0x5e, 0x64, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w10, 0, vgx2], { z19.h, z20.h }, z4.h"
+
+  -
+    input:
+      bytes: [ 0x60, 0x5e, 0x64, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w10, 0, vgx2], { z19.h, z20.h }, z4.h"
+
+  -
+    input:
+      bytes: [ 0x80, 0x1d, 0x62, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w8, 0, vgx2], { z12.h, z13.h }, z2.h"
+
+  -
+    input:
+      bytes: [ 0x80, 0x1d, 0x62, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w8, 0, vgx2], { z12.h, z13.h }, z2.h"
+
+  -
+    input:
+      bytes: [ 0x21, 0x5c, 0x6a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w10, 1, vgx2], { z1.h, z2.h }, z10.h"
+
+  -
+    input:
+      bytes: [ 0x21, 0x5c, 0x6a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w10, 1, vgx2], { z1.h, z2.h }, z10.h"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x1e, 0x6e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w8, 5, vgx2], { z22.h, z23.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x1e, 0x6e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w8, 5, vgx2], { z22.h, z23.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x22, 0x7d, 0x61, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w11, 2, vgx2], { z9.h, z10.h }, z1.h"
+
+  -
+    input:
+      bytes: [ 0x22, 0x7d, 0x61, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w11, 2, vgx2], { z9.h, z10.h }, z1.h"
+
+  -
+    input:
+      bytes: [ 0x87, 0x3d, 0x6b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w9, 7, vgx2], { z12.h, z13.h }, z11.h"
+
+  -
+    input:
+      bytes: [ 0x87, 0x3d, 0x6b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w9, 7, vgx2], { z12.h, z13.h }, z11.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x10, 0x10, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w8, 0, vgx2], { z0.h, z1.h }, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x10, 0x10, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w8, 0, vgx2], { z0.h, z1.h }, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x65, 0x55, 0x15, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w10, 5, vgx2], { z10.h, z11.h }, z5.h[2]"
+
+  -
+    input:
+      bytes: [ 0x65, 0x55, 0x15, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w10, 5, vgx2], { z10.h, z11.h }, z5.h[2]"
+
+  -
+    input:
+      bytes: [ 0xa7, 0x7d, 0x18, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w11, 7, vgx2], { z12.h, z13.h }, z8.h[6]"
+
+  -
+    input:
+      bytes: [ 0xa7, 0x7d, 0x18, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w11, 7, vgx2], { z12.h, z13.h }, z8.h[6]"
+
+  -
+    input:
+      bytes: [ 0xef, 0x7f, 0x1f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w11, 7, vgx2], { z30.h, z31.h }, z15.h[7]"
+
+  -
+    input:
+      bytes: [ 0xef, 0x7f, 0x1f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w11, 7, vgx2], { z30.h, z31.h }, z15.h[7]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x1e, 0x10, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w8, 5, vgx2], { z16.h, z17.h }, z0.h[6]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x1e, 0x10, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w8, 5, vgx2], { z16.h, z17.h }, z0.h[6]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x14, 0x1e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w8, 1, vgx2], { z0.h, z1.h }, z14.h[2]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x14, 0x1e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w8, 1, vgx2], { z0.h, z1.h }, z14.h[2]"
+
+  -
+    input:
+      bytes: [ 0x68, 0x56, 0x14, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w10, 0, vgx2], { z18.h, z19.h }, z4.h[3]"
+
+  -
+    input:
+      bytes: [ 0x68, 0x56, 0x14, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w10, 0, vgx2], { z18.h, z19.h }, z4.h[3]"
+
+  -
+    input:
+      bytes: [ 0xa0, 0x19, 0x12, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w8, 0, vgx2], { z12.h, z13.h }, z2.h[4]"
+
+  -
+    input:
+      bytes: [ 0xa0, 0x19, 0x12, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w8, 0, vgx2], { z12.h, z13.h }, z2.h[4]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x58, 0x1a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w10, 1, vgx2], { z0.h, z1.h }, z10.h[4]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x58, 0x1a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w10, 1, vgx2], { z0.h, z1.h }, z10.h[4]"
+
+  -
+    input:
+      bytes: [ 0xed, 0x1a, 0x1e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w8, 5, vgx2], { z22.h, z23.h }, z14.h[5]"
+
+  -
+    input:
+      bytes: [ 0xed, 0x1a, 0x1e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w8, 5, vgx2], { z22.h, z23.h }, z14.h[5]"
+
+  -
+    input:
+      bytes: [ 0x22, 0x75, 0x11, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w11, 2, vgx2], { z8.h, z9.h }, z1.h[2]"
+
+  -
+    input:
+      bytes: [ 0x22, 0x75, 0x11, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w11, 2, vgx2], { z8.h, z9.h }, z1.h[2]"
+
+  -
+    input:
+      bytes: [ 0xa7, 0x39, 0x1b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w9, 7, vgx2], { z12.h, z13.h }, z11.h[4]"
+
+  -
+    input:
+      bytes: [ 0xa7, 0x39, 0x1b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w9, 7, vgx2], { z12.h, z13.h }, z11.h[4]"
+
+  -
+    input:
+      bytes: [ 0x08, 0x10, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w8, 0, vgx2], { z0.h, z1.h }, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x08, 0x10, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w8, 0, vgx2], { z0.h, z1.h }, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x4d, 0x51, 0xf4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w10, 5, vgx2], { z10.h, z11.h }, { z20.h, z21.h }"
+
+  -
+    input:
+      bytes: [ 0x4d, 0x51, 0xf4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w10, 5, vgx2], { z10.h, z11.h }, { z20.h, z21.h }"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x71, 0xe8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w11, 7, vgx2], { z12.h, z13.h }, { z8.h, z9.h }"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x71, 0xe8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w11, 7, vgx2], { z12.h, z13.h }, { z8.h, z9.h }"
+
+  -
+    input:
+      bytes: [ 0xcf, 0x73, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w11, 7, vgx2], { z30.h, z31.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0xcf, 0x73, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w11, 7, vgx2], { z30.h, z31.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x0d, 0x12, 0xf0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w8, 5, vgx2], { z16.h, z17.h }, { z16.h, z17.h }"
+
+  -
+    input:
+      bytes: [ 0x0d, 0x12, 0xf0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w8, 5, vgx2], { z16.h, z17.h }, { z16.h, z17.h }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x10, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w8, 1, vgx2], { z0.h, z1.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x10, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w8, 1, vgx2], { z0.h, z1.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x48, 0x52, 0xf4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w10, 0, vgx2], { z18.h, z19.h }, { z20.h, z21.h }"
+
+  -
+    input:
+      bytes: [ 0x48, 0x52, 0xf4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w10, 0, vgx2], { z18.h, z19.h }, { z20.h, z21.h }"
+
+  -
+    input:
+      bytes: [ 0x88, 0x11, 0xe2, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w8, 0, vgx2], { z12.h, z13.h }, { z2.h, z3.h }"
+
+  -
+    input:
+      bytes: [ 0x88, 0x11, 0xe2, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w8, 0, vgx2], { z12.h, z13.h }, { z2.h, z3.h }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x50, 0xfa, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w10, 1, vgx2], { z0.h, z1.h }, { z26.h, z27.h }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x50, 0xfa, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w10, 1, vgx2], { z0.h, z1.h }, { z26.h, z27.h }"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x12, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w8, 5, vgx2], { z22.h, z23.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x12, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w8, 5, vgx2], { z22.h, z23.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x0a, 0x71, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w11, 2, vgx2], { z8.h, z9.h }, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x0a, 0x71, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w11, 2, vgx2], { z8.h, z9.h }, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x31, 0xea, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w9, 7, vgx2], { z12.h, z13.h }, { z10.h, z11.h }"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x31, 0xea, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w9, 7, vgx2], { z12.h, z13.h }, { z10.h, z11.h }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x1c, 0x70, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w8, 0, vgx4], { z0.h - z3.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x1c, 0x70, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w8, 0, vgx4], { z0.h - z3.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x45, 0x5d, 0x75, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w10, 5, vgx4], { z10.h - z13.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0x45, 0x5d, 0x75, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w10, 5, vgx4], { z10.h - z13.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0xa7, 0x7d, 0x78, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w11, 7, vgx4], { z13.h - z16.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0xa7, 0x7d, 0x78, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w11, 7, vgx4], { z13.h - z16.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0xe7, 0x7f, 0x7f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w11, 7, vgx4], { z31.h, z0.h, z1.h, z2.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0xe7, 0x7f, 0x7f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w11, 7, vgx4], { z31.h, z0.h, z1.h, z2.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0x25, 0x1e, 0x70, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w8, 5, vgx4], { z17.h - z20.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x25, 0x1e, 0x70, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w8, 5, vgx4], { z17.h - z20.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x21, 0x1c, 0x7e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w8, 1, vgx4], { z1.h - z4.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x21, 0x1c, 0x7e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w8, 1, vgx4], { z1.h - z4.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x60, 0x5e, 0x74, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w10, 0, vgx4], { z19.h - z22.h }, z4.h"
+
+  -
+    input:
+      bytes: [ 0x60, 0x5e, 0x74, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w10, 0, vgx4], { z19.h - z22.h }, z4.h"
+
+  -
+    input:
+      bytes: [ 0x80, 0x1d, 0x72, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w8, 0, vgx4], { z12.h - z15.h }, z2.h"
+
+  -
+    input:
+      bytes: [ 0x80, 0x1d, 0x72, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w8, 0, vgx4], { z12.h - z15.h }, z2.h"
+
+  -
+    input:
+      bytes: [ 0x21, 0x5c, 0x7a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w10, 1, vgx4], { z1.h - z4.h }, z10.h"
+
+  -
+    input:
+      bytes: [ 0x21, 0x5c, 0x7a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w10, 1, vgx4], { z1.h - z4.h }, z10.h"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x1e, 0x7e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w8, 5, vgx4], { z22.h - z25.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x1e, 0x7e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w8, 5, vgx4], { z22.h - z25.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x22, 0x7d, 0x71, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w11, 2, vgx4], { z9.h - z12.h }, z1.h"
+
+  -
+    input:
+      bytes: [ 0x22, 0x7d, 0x71, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w11, 2, vgx4], { z9.h - z12.h }, z1.h"
+
+  -
+    input:
+      bytes: [ 0x87, 0x3d, 0x7b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w9, 7, vgx4], { z12.h - z15.h }, z11.h"
+
+  -
+    input:
+      bytes: [ 0x87, 0x3d, 0x7b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w9, 7, vgx4], { z12.h - z15.h }, z11.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x90, 0x10, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w8, 0, vgx4], { z0.h - z3.h }, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x90, 0x10, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w8, 0, vgx4], { z0.h - z3.h }, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x25, 0xd5, 0x15, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w10, 5, vgx4], { z8.h - z11.h }, z5.h[2]"
+
+  -
+    input:
+      bytes: [ 0x25, 0xd5, 0x15, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w10, 5, vgx4], { z8.h - z11.h }, z5.h[2]"
+
+  -
+    input:
+      bytes: [ 0xa7, 0xfd, 0x18, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w11, 7, vgx4], { z12.h - z15.h }, z8.h[6]"
+
+  -
+    input:
+      bytes: [ 0xa7, 0xfd, 0x18, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w11, 7, vgx4], { z12.h - z15.h }, z8.h[6]"
+
+  -
+    input:
+      bytes: [ 0xaf, 0xff, 0x1f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w11, 7, vgx4], { z28.h - z31.h }, z15.h[7]"
+
+  -
+    input:
+      bytes: [ 0xaf, 0xff, 0x1f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w11, 7, vgx4], { z28.h - z31.h }, z15.h[7]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x9e, 0x10, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w8, 5, vgx4], { z16.h - z19.h }, z0.h[6]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x9e, 0x10, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w8, 5, vgx4], { z16.h - z19.h }, z0.h[6]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x94, 0x1e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w8, 1, vgx4], { z0.h - z3.h }, z14.h[2]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x94, 0x1e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w8, 1, vgx4], { z0.h - z3.h }, z14.h[2]"
+
+  -
+    input:
+      bytes: [ 0x28, 0xd6, 0x14, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w10, 0, vgx4], { z16.h - z19.h }, z4.h[3]"
+
+  -
+    input:
+      bytes: [ 0x28, 0xd6, 0x14, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w10, 0, vgx4], { z16.h - z19.h }, z4.h[3]"
+
+  -
+    input:
+      bytes: [ 0xa0, 0x99, 0x12, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w8, 0, vgx4], { z12.h - z15.h }, z2.h[4]"
+
+  -
+    input:
+      bytes: [ 0xa0, 0x99, 0x12, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w8, 0, vgx4], { z12.h - z15.h }, z2.h[4]"
+
+  -
+    input:
+      bytes: [ 0x21, 0xd8, 0x1a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w10, 1, vgx4], { z0.h - z3.h }, z10.h[4]"
+
+  -
+    input:
+      bytes: [ 0x21, 0xd8, 0x1a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w10, 1, vgx4], { z0.h - z3.h }, z10.h[4]"
+
+  -
+    input:
+      bytes: [ 0xad, 0x9a, 0x1e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w8, 5, vgx4], { z20.h - z23.h }, z14.h[5]"
+
+  -
+    input:
+      bytes: [ 0xad, 0x9a, 0x1e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w8, 5, vgx4], { z20.h - z23.h }, z14.h[5]"
+
+  -
+    input:
+      bytes: [ 0x22, 0xf5, 0x11, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w11, 2, vgx4], { z8.h - z11.h }, z1.h[2]"
+
+  -
+    input:
+      bytes: [ 0x22, 0xf5, 0x11, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w11, 2, vgx4], { z8.h - z11.h }, z1.h[2]"
+
+  -
+    input:
+      bytes: [ 0xa7, 0xb9, 0x1b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w9, 7, vgx4], { z12.h - z15.h }, z11.h[4]"
+
+  -
+    input:
+      bytes: [ 0xa7, 0xb9, 0x1b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w9, 7, vgx4], { z12.h - z15.h }, z11.h[4]"
+
+  -
+    input:
+      bytes: [ 0x08, 0x10, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w8, 0, vgx4], { z0.h - z3.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x08, 0x10, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w8, 0, vgx4], { z0.h - z3.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x0d, 0x51, 0xf5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w10, 5, vgx4], { z8.h - z11.h }, { z20.h - z23.h }"
+
+  -
+    input:
+      bytes: [ 0x0d, 0x51, 0xf5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w10, 5, vgx4], { z8.h - z11.h }, { z20.h - z23.h }"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x71, 0xe9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w11, 7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x71, 0xe9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w11, 7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x73, 0xfd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w11, 7, vgx4], { z28.h - z31.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x73, 0xfd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w11, 7, vgx4], { z28.h - z31.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x0d, 0x12, 0xf1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w8, 5, vgx4], { z16.h - z19.h }, { z16.h - z19.h }"
+
+  -
+    input:
+      bytes: [ 0x0d, 0x12, 0xf1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w8, 5, vgx4], { z16.h - z19.h }, { z16.h - z19.h }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x10, 0xfd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w8, 1, vgx4], { z0.h - z3.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x10, 0xfd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w8, 1, vgx4], { z0.h - z3.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x08, 0x52, 0xf5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w10, 0, vgx4], { z16.h - z19.h }, { z20.h - z23.h }"
+
+  -
+    input:
+      bytes: [ 0x08, 0x52, 0xf5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w10, 0, vgx4], { z16.h - z19.h }, { z20.h - z23.h }"
+
+  -
+    input:
+      bytes: [ 0x88, 0x11, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w8, 0, vgx4], { z12.h - z15.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x88, 0x11, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w8, 0, vgx4], { z12.h - z15.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x50, 0xf9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w10, 1, vgx4], { z0.h - z3.h }, { z24.h - z27.h }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x50, 0xf9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w10, 1, vgx4], { z0.h - z3.h }, { z24.h - z27.h }"
+
+  -
+    input:
+      bytes: [ 0x8d, 0x12, 0xfd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w8, 5, vgx4], { z20.h - z23.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x8d, 0x12, 0xfd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w8, 5, vgx4], { z20.h - z23.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x0a, 0x71, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w11, 2, vgx4], { z8.h - z11.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x0a, 0x71, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w11, 2, vgx4], { z8.h - z11.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x31, 0xe9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w9, 7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x31, 0xe9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla za.h[w9, 7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }"
diff --git a/tests/MC/AArch64/SME2/bfmlal.s.yaml b/tests/MC/AArch64/SME2/bfmlal.s.yaml
new file mode 100644
index 000000000..1ca16cdb9
--- /dev/null
+++ b/tests/MC/AArch64/SME2/bfmlal.s.yaml
@@ -0,0 +1,1680 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x10, 0x0c, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w8, 0:1], z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x55, 0x4d, 0x25, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w10, 10:11], z10.h, z5.h"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x6d, 0x28, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w11, 14:15], z13.h, z8.h"
+
+  -
+    input:
+      bytes: [ 0xf7, 0x6f, 0x2f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w11, 14:15], z31.h, z15.h"
+
+  -
+    input:
+      bytes: [ 0x35, 0x0e, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w8, 10:11], z17.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x31, 0x0c, 0x2e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w8, 2:3], z1.h, z14.h"
+
+  -
+    input:
+      bytes: [ 0x70, 0x4e, 0x24, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w10, 0:1], z19.h, z4.h"
+
+  -
+    input:
+      bytes: [ 0x90, 0x0d, 0x22, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w8, 0:1], z12.h, z2.h"
+
+  -
+    input:
+      bytes: [ 0x31, 0x4c, 0x2a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w10, 2:3], z1.h, z10.h"
+
+  -
+    input:
+      bytes: [ 0xd5, 0x0e, 0x2e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w8, 10:11], z22.h, z14.h"
+
+  -
+    input:
+      bytes: [ 0x32, 0x6d, 0x21, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w11, 4:5], z9.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0x97, 0x2d, 0x2b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w9, 14:15], z12.h, z11.h"
+
+  -
+    input:
+      bytes: [ 0x10, 0x10, 0x80, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w8, 0:1], z0.h, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x55, 0x85, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w10, 10:11], z10.h, z5.h[1]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xfd, 0x88, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w11, 14:15], z13.h, z8.h[7]"
+
+  -
+    input:
+      bytes: [ 0xf7, 0xff, 0x8f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w11, 14:15], z31.h, z15.h[7]"
+
+  -
+    input:
+      bytes: [ 0x35, 0x1e, 0x80, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w8, 10:11], z17.h, z0.h[3]"
+
+  -
+    input:
+      bytes: [ 0x31, 0x94, 0x8e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w8, 2:3], z1.h, z14.h[5]"
+
+  -
+    input:
+      bytes: [ 0x70, 0x56, 0x84, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w10, 0:1], z19.h, z4.h[1]"
+
+  -
+    input:
+      bytes: [ 0x90, 0x19, 0x82, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w8, 0:1], z12.h, z2.h[2]"
+
+  -
+    input:
+      bytes: [ 0x31, 0xd8, 0x8a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w10, 2:3], z1.h, z10.h[6]"
+
+  -
+    input:
+      bytes: [ 0xd5, 0x1a, 0x8e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w8, 10:11], z22.h, z14.h[2]"
+
+  -
+    input:
+      bytes: [ 0x32, 0xf5, 0x81, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w11, 4:5], z9.h, z1.h[5]"
+
+  -
+    input:
+      bytes: [ 0x97, 0xb9, 0x8b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w9, 14:15], z12.h, z11.h[6]"
+
+  -
+    input:
+      bytes: [ 0x10, 0x08, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w8, 0:1, vgx2], { z0.h, z1.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x10, 0x08, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w8, 0:1, vgx2], { z0.h, z1.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x51, 0x49, 0x25, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w10, 2:3, vgx2], { z10.h, z11.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0x51, 0x49, 0x25, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w10, 2:3, vgx2], { z10.h, z11.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0xb3, 0x69, 0x28, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w11, 6:7, vgx2], { z13.h, z14.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0xb3, 0x69, 0x28, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w11, 6:7, vgx2], { z13.h, z14.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0xf3, 0x6b, 0x2f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w11, 6:7, vgx2], { z31.h, z0.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0xf3, 0x6b, 0x2f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w11, 6:7, vgx2], { z31.h, z0.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0x31, 0x0a, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w8, 2:3, vgx2], { z17.h, z18.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x31, 0x0a, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w8, 2:3, vgx2], { z17.h, z18.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x31, 0x08, 0x2e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w8, 2:3, vgx2], { z1.h, z2.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x31, 0x08, 0x2e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w8, 2:3, vgx2], { z1.h, z2.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x70, 0x4a, 0x24, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w10, 0:1, vgx2], { z19.h, z20.h }, z4.h"
+
+  -
+    input:
+      bytes: [ 0x70, 0x4a, 0x24, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w10, 0:1, vgx2], { z19.h, z20.h }, z4.h"
+
+  -
+    input:
+      bytes: [ 0x90, 0x09, 0x22, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w8, 0:1, vgx2], { z12.h, z13.h }, z2.h"
+
+  -
+    input:
+      bytes: [ 0x90, 0x09, 0x22, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w8, 0:1, vgx2], { z12.h, z13.h }, z2.h"
+
+  -
+    input:
+      bytes: [ 0x31, 0x48, 0x2a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w10, 2:3, vgx2], { z1.h, z2.h }, z10.h"
+
+  -
+    input:
+      bytes: [ 0x31, 0x48, 0x2a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w10, 2:3, vgx2], { z1.h, z2.h }, z10.h"
+
+  -
+    input:
+      bytes: [ 0xd1, 0x0a, 0x2e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w8, 2:3, vgx2], { z22.h, z23.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0xd1, 0x0a, 0x2e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w8, 2:3, vgx2], { z22.h, z23.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x32, 0x69, 0x21, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w11, 4:5, vgx2], { z9.h, z10.h }, z1.h"
+
+  -
+    input:
+      bytes: [ 0x32, 0x69, 0x21, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w11, 4:5, vgx2], { z9.h, z10.h }, z1.h"
+
+  -
+    input:
+      bytes: [ 0x93, 0x29, 0x2b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w9, 6:7, vgx2], { z12.h, z13.h }, z11.h"
+
+  -
+    input:
+      bytes: [ 0x93, 0x29, 0x2b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w9, 6:7, vgx2], { z12.h, z13.h }, z11.h"
+
+  -
+    input:
+      bytes: [ 0x10, 0x10, 0x90, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w8, 0:1, vgx2], { z0.h, z1.h }, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x10, 0x10, 0x90, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w8, 0:1, vgx2], { z0.h, z1.h }, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x55, 0x95, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w10, 2:3, vgx2], { z10.h, z11.h }, z5.h[3]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x55, 0x95, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w10, 2:3, vgx2], { z10.h, z11.h }, z5.h[3]"
+
+  -
+    input:
+      bytes: [ 0x97, 0x7d, 0x98, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w11, 6:7, vgx2], { z12.h, z13.h }, z8.h[7]"
+
+  -
+    input:
+      bytes: [ 0x97, 0x7d, 0x98, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w11, 6:7, vgx2], { z12.h, z13.h }, z8.h[7]"
+
+  -
+    input:
+      bytes: [ 0xd7, 0x7f, 0x9f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w11, 6:7, vgx2], { z30.h, z31.h }, z15.h[7]"
+
+  -
+    input:
+      bytes: [ 0xd7, 0x7f, 0x9f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w11, 6:7, vgx2], { z30.h, z31.h }, z15.h[7]"
+
+  -
+    input:
+      bytes: [ 0x15, 0x1e, 0x90, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w8, 2:3, vgx2], { z16.h, z17.h }, z0.h[7]"
+
+  -
+    input:
+      bytes: [ 0x15, 0x1e, 0x90, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w8, 2:3, vgx2], { z16.h, z17.h }, z0.h[7]"
+
+  -
+    input:
+      bytes: [ 0x11, 0x14, 0x9e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w8, 2:3, vgx2], { z0.h, z1.h }, z14.h[2]"
+
+  -
+    input:
+      bytes: [ 0x11, 0x14, 0x9e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w8, 2:3, vgx2], { z0.h, z1.h }, z14.h[2]"
+
+  -
+    input:
+      bytes: [ 0x50, 0x56, 0x94, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w10, 0:1, vgx2], { z18.h, z19.h }, z4.h[2]"
+
+  -
+    input:
+      bytes: [ 0x50, 0x56, 0x94, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w10, 0:1, vgx2], { z18.h, z19.h }, z4.h[2]"
+
+  -
+    input:
+      bytes: [ 0x90, 0x19, 0x92, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w8, 0:1, vgx2], { z12.h, z13.h }, z2.h[4]"
+
+  -
+    input:
+      bytes: [ 0x90, 0x19, 0x92, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w8, 0:1, vgx2], { z12.h, z13.h }, z2.h[4]"
+
+  -
+    input:
+      bytes: [ 0x11, 0x58, 0x9a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w10, 2:3, vgx2], { z0.h, z1.h }, z10.h[4]"
+
+  -
+    input:
+      bytes: [ 0x11, 0x58, 0x9a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w10, 2:3, vgx2], { z0.h, z1.h }, z10.h[4]"
+
+  -
+    input:
+      bytes: [ 0xd5, 0x1a, 0x9e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w8, 2:3, vgx2], { z22.h, z23.h }, z14.h[5]"
+
+  -
+    input:
+      bytes: [ 0xd5, 0x1a, 0x9e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w8, 2:3, vgx2], { z22.h, z23.h }, z14.h[5]"
+
+  -
+    input:
+      bytes: [ 0x12, 0x75, 0x91, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w11, 4:5, vgx2], { z8.h, z9.h }, z1.h[2]"
+
+  -
+    input:
+      bytes: [ 0x12, 0x75, 0x91, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w11, 4:5, vgx2], { z8.h, z9.h }, z1.h[2]"
+
+  -
+    input:
+      bytes: [ 0x97, 0x39, 0x9b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w9, 6:7, vgx2], { z12.h, z13.h }, z11.h[5]"
+
+  -
+    input:
+      bytes: [ 0x97, 0x39, 0x9b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w9, 6:7, vgx2], { z12.h, z13.h }, z11.h[5]"
+
+  -
+    input:
+      bytes: [ 0x10, 0x08, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w8, 0:1, vgx2], { z0.h, z1.h }, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x10, 0x08, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w8, 0:1, vgx2], { z0.h, z1.h }, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x51, 0x49, 0xb4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w10, 2:3, vgx2], { z10.h, z11.h }, { z20.h, z21.h }"
+
+  -
+    input:
+      bytes: [ 0x51, 0x49, 0xb4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w10, 2:3, vgx2], { z10.h, z11.h }, { z20.h, z21.h }"
+
+  -
+    input:
+      bytes: [ 0x93, 0x69, 0xa8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w11, 6:7, vgx2], { z12.h, z13.h }, { z8.h, z9.h }"
+
+  -
+    input:
+      bytes: [ 0x93, 0x69, 0xa8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w11, 6:7, vgx2], { z12.h, z13.h }, { z8.h, z9.h }"
+
+  -
+    input:
+      bytes: [ 0xd3, 0x6b, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w11, 6:7, vgx2], { z30.h, z31.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0xd3, 0x6b, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w11, 6:7, vgx2], { z30.h, z31.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x11, 0x0a, 0xb0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w8, 2:3, vgx2], { z16.h, z17.h }, { z16.h, z17.h }"
+
+  -
+    input:
+      bytes: [ 0x11, 0x0a, 0xb0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w8, 2:3, vgx2], { z16.h, z17.h }, { z16.h, z17.h }"
+
+  -
+    input:
+      bytes: [ 0x11, 0x08, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w8, 2:3, vgx2], { z0.h, z1.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x11, 0x08, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w8, 2:3, vgx2], { z0.h, z1.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x50, 0x4a, 0xb4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w10, 0:1, vgx2], { z18.h, z19.h }, { z20.h, z21.h }"
+
+  -
+    input:
+      bytes: [ 0x50, 0x4a, 0xb4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w10, 0:1, vgx2], { z18.h, z19.h }, { z20.h, z21.h }"
+
+  -
+    input:
+      bytes: [ 0x90, 0x09, 0xa2, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w8, 0:1, vgx2], { z12.h, z13.h }, { z2.h, z3.h }"
+
+  -
+    input:
+      bytes: [ 0x90, 0x09, 0xa2, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w8, 0:1, vgx2], { z12.h, z13.h }, { z2.h, z3.h }"
+
+  -
+    input:
+      bytes: [ 0x11, 0x48, 0xba, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w10, 2:3, vgx2], { z0.h, z1.h }, { z26.h, z27.h }"
+
+  -
+    input:
+      bytes: [ 0x11, 0x48, 0xba, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w10, 2:3, vgx2], { z0.h, z1.h }, { z26.h, z27.h }"
+
+  -
+    input:
+      bytes: [ 0xd1, 0x0a, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w8, 2:3, vgx2], { z22.h, z23.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0xd1, 0x0a, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w8, 2:3, vgx2], { z22.h, z23.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x12, 0x69, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w11, 4:5, vgx2], { z8.h, z9.h }, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x12, 0x69, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w11, 4:5, vgx2], { z8.h, z9.h }, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x93, 0x29, 0xaa, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w9, 6:7, vgx2], { z12.h, z13.h }, { z10.h, z11.h }"
+
+  -
+    input:
+      bytes: [ 0x93, 0x29, 0xaa, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w9, 6:7, vgx2], { z12.h, z13.h }, { z10.h, z11.h }"
+
+  -
+    input:
+      bytes: [ 0x10, 0x08, 0x30, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w8, 0:1, vgx4], { z0.h - z3.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x10, 0x08, 0x30, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w8, 0:1, vgx4], { z0.h - z3.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x51, 0x49, 0x35, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w10, 2:3, vgx4], { z10.h - z13.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0x51, 0x49, 0x35, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w10, 2:3, vgx4], { z10.h - z13.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0xb3, 0x69, 0x38, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w11, 6:7, vgx4], { z13.h - z16.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0xb3, 0x69, 0x38, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w11, 6:7, vgx4], { z13.h - z16.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0xf3, 0x6b, 0x3f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w11, 6:7, vgx4], { z31.h, z0.h, z1.h, z2.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0xf3, 0x6b, 0x3f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w11, 6:7, vgx4], { z31.h, z0.h, z1.h, z2.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0x31, 0x0a, 0x30, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w8, 2:3, vgx4], { z17.h - z20.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x31, 0x0a, 0x30, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w8, 2:3, vgx4], { z17.h - z20.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x31, 0x08, 0x3e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w8, 2:3, vgx4], { z1.h - z4.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x31, 0x08, 0x3e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w8, 2:3, vgx4], { z1.h - z4.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x70, 0x4a, 0x34, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w10, 0:1, vgx4], { z19.h - z22.h }, z4.h"
+
+  -
+    input:
+      bytes: [ 0x70, 0x4a, 0x34, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w10, 0:1, vgx4], { z19.h - z22.h }, z4.h"
+
+  -
+    input:
+      bytes: [ 0x90, 0x09, 0x32, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w8, 0:1, vgx4], { z12.h - z15.h }, z2.h"
+
+  -
+    input:
+      bytes: [ 0x90, 0x09, 0x32, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w8, 0:1, vgx4], { z12.h - z15.h }, z2.h"
+
+  -
+    input:
+      bytes: [ 0x31, 0x48, 0x3a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w10, 2:3, vgx4], { z1.h - z4.h }, z10.h"
+
+  -
+    input:
+      bytes: [ 0x31, 0x48, 0x3a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w10, 2:3, vgx4], { z1.h - z4.h }, z10.h"
+
+  -
+    input:
+      bytes: [ 0xd1, 0x0a, 0x3e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w8, 2:3, vgx4], { z22.h - z25.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0xd1, 0x0a, 0x3e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w8, 2:3, vgx4], { z22.h - z25.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x32, 0x69, 0x31, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w11, 4:5, vgx4], { z9.h - z12.h }, z1.h"
+
+  -
+    input:
+      bytes: [ 0x32, 0x69, 0x31, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w11, 4:5, vgx4], { z9.h - z12.h }, z1.h"
+
+  -
+    input:
+      bytes: [ 0x93, 0x29, 0x3b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w9, 6:7, vgx4], { z12.h - z15.h }, z11.h"
+
+  -
+    input:
+      bytes: [ 0x93, 0x29, 0x3b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w9, 6:7, vgx4], { z12.h - z15.h }, z11.h"
+
+  -
+    input:
+      bytes: [ 0x10, 0x90, 0x90, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w8, 0:1, vgx4], { z0.h - z3.h }, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x10, 0x90, 0x90, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w8, 0:1, vgx4], { z0.h - z3.h }, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x15, 0xd5, 0x95, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w10, 2:3, vgx4], { z8.h - z11.h }, z5.h[3]"
+
+  -
+    input:
+      bytes: [ 0x15, 0xd5, 0x95, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w10, 2:3, vgx4], { z8.h - z11.h }, z5.h[3]"
+
+  -
+    input:
+      bytes: [ 0x97, 0xfd, 0x98, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w11, 6:7, vgx4], { z12.h - z15.h }, z8.h[7]"
+
+  -
+    input:
+      bytes: [ 0x97, 0xfd, 0x98, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w11, 6:7, vgx4], { z12.h - z15.h }, z8.h[7]"
+
+  -
+    input:
+      bytes: [ 0x97, 0xff, 0x9f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w11, 6:7, vgx4], { z28.h - z31.h }, z15.h[7]"
+
+  -
+    input:
+      bytes: [ 0x97, 0xff, 0x9f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w11, 6:7, vgx4], { z28.h - z31.h }, z15.h[7]"
+
+  -
+    input:
+      bytes: [ 0x15, 0x9e, 0x90, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w8, 2:3, vgx4], { z16.h - z19.h }, z0.h[7]"
+
+  -
+    input:
+      bytes: [ 0x15, 0x9e, 0x90, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w8, 2:3, vgx4], { z16.h - z19.h }, z0.h[7]"
+
+  -
+    input:
+      bytes: [ 0x11, 0x94, 0x9e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w8, 2:3, vgx4], { z0.h - z3.h }, z14.h[2]"
+
+  -
+    input:
+      bytes: [ 0x11, 0x94, 0x9e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w8, 2:3, vgx4], { z0.h - z3.h }, z14.h[2]"
+
+  -
+    input:
+      bytes: [ 0x10, 0xd6, 0x94, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w10, 0:1, vgx4], { z16.h - z19.h }, z4.h[2]"
+
+  -
+    input:
+      bytes: [ 0x10, 0xd6, 0x94, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w10, 0:1, vgx4], { z16.h - z19.h }, z4.h[2]"
+
+  -
+    input:
+      bytes: [ 0x90, 0x99, 0x92, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w8, 0:1, vgx4], { z12.h - z15.h }, z2.h[4]"
+
+  -
+    input:
+      bytes: [ 0x90, 0x99, 0x92, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w8, 0:1, vgx4], { z12.h - z15.h }, z2.h[4]"
+
+  -
+    input:
+      bytes: [ 0x11, 0xd8, 0x9a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w10, 2:3, vgx4], { z0.h - z3.h }, z10.h[4]"
+
+  -
+    input:
+      bytes: [ 0x11, 0xd8, 0x9a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w10, 2:3, vgx4], { z0.h - z3.h }, z10.h[4]"
+
+  -
+    input:
+      bytes: [ 0x95, 0x9a, 0x9e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w8, 2:3, vgx4], { z20.h - z23.h }, z14.h[5]"
+
+  -
+    input:
+      bytes: [ 0x95, 0x9a, 0x9e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w8, 2:3, vgx4], { z20.h - z23.h }, z14.h[5]"
+
+  -
+    input:
+      bytes: [ 0x12, 0xf5, 0x91, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w11, 4:5, vgx4], { z8.h - z11.h }, z1.h[2]"
+
+  -
+    input:
+      bytes: [ 0x12, 0xf5, 0x91, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w11, 4:5, vgx4], { z8.h - z11.h }, z1.h[2]"
+
+  -
+    input:
+      bytes: [ 0x97, 0xb9, 0x9b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w9, 6:7, vgx4], { z12.h - z15.h }, z11.h[5]"
+
+  -
+    input:
+      bytes: [ 0x97, 0xb9, 0x9b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w9, 6:7, vgx4], { z12.h - z15.h }, z11.h[5]"
+
+  -
+    input:
+      bytes: [ 0x10, 0x08, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w8, 0:1, vgx4], { z0.h - z3.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x10, 0x08, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w8, 0:1, vgx4], { z0.h - z3.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x11, 0x49, 0xb5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w10, 2:3, vgx4], { z8.h - z11.h }, { z20.h - z23.h }"
+
+  -
+    input:
+      bytes: [ 0x11, 0x49, 0xb5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w10, 2:3, vgx4], { z8.h - z11.h }, { z20.h - z23.h }"
+
+  -
+    input:
+      bytes: [ 0x93, 0x69, 0xa9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w11, 6:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }"
+
+  -
+    input:
+      bytes: [ 0x93, 0x69, 0xa9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w11, 6:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }"
+
+  -
+    input:
+      bytes: [ 0x93, 0x6b, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w11, 6:7, vgx4], { z28.h - z31.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x93, 0x6b, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w11, 6:7, vgx4], { z28.h - z31.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x11, 0x0a, 0xb1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w8, 2:3, vgx4], { z16.h - z19.h }, { z16.h - z19.h }"
+
+  -
+    input:
+      bytes: [ 0x11, 0x0a, 0xb1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w8, 2:3, vgx4], { z16.h - z19.h }, { z16.h - z19.h }"
+
+  -
+    input:
+      bytes: [ 0x11, 0x08, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w8, 2:3, vgx4], { z0.h - z3.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x11, 0x08, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w8, 2:3, vgx4], { z0.h - z3.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x10, 0x4a, 0xb5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w10, 0:1, vgx4], { z16.h - z19.h }, { z20.h - z23.h }"
+
+  -
+    input:
+      bytes: [ 0x10, 0x4a, 0xb5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w10, 0:1, vgx4], { z16.h - z19.h }, { z20.h - z23.h }"
+
+  -
+    input:
+      bytes: [ 0x90, 0x09, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w8, 0:1, vgx4], { z12.h - z15.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x90, 0x09, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w8, 0:1, vgx4], { z12.h - z15.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x11, 0x48, 0xb9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w10, 2:3, vgx4], { z0.h - z3.h }, { z24.h - z27.h }"
+
+  -
+    input:
+      bytes: [ 0x11, 0x48, 0xb9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w10, 2:3, vgx4], { z0.h - z3.h }, { z24.h - z27.h }"
+
+  -
+    input:
+      bytes: [ 0x91, 0x0a, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w8, 2:3, vgx4], { z20.h - z23.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x91, 0x0a, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w8, 2:3, vgx4], { z20.h - z23.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x12, 0x69, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w11, 4:5, vgx4], { z8.h - z11.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x12, 0x69, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w11, 4:5, vgx4], { z8.h - z11.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x93, 0x29, 0xa9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w9, 6:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }"
+
+  -
+    input:
+      bytes: [ 0x93, 0x29, 0xa9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlal za.s[w9, 6:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }"
diff --git a/tests/MC/AArch64/SME2/bfmls.s.yaml b/tests/MC/AArch64/SME2/bfmls.s.yaml
new file mode 100644
index 000000000..101b7433c
--- /dev/null
+++ b/tests/MC/AArch64/SME2/bfmls.s.yaml
@@ -0,0 +1,1440 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x08, 0x1c, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w8, 0, vgx2], { z0.h, z1.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x08, 0x1c, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w8, 0, vgx2], { z0.h, z1.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x4d, 0x5d, 0x65, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w10, 5, vgx2], { z10.h, z11.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0x4d, 0x5d, 0x65, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w10, 5, vgx2], { z10.h, z11.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0xaf, 0x7d, 0x68, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w11, 7, vgx2], { z13.h, z14.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0xaf, 0x7d, 0x68, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w11, 7, vgx2], { z13.h, z14.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0xef, 0x7f, 0x6f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w11, 7, vgx2], { z31.h, z0.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0xef, 0x7f, 0x6f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w11, 7, vgx2], { z31.h, z0.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0x2d, 0x1e, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w8, 5, vgx2], { z17.h, z18.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x2d, 0x1e, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w8, 5, vgx2], { z17.h, z18.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x29, 0x1c, 0x6e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w8, 1, vgx2], { z1.h, z2.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x29, 0x1c, 0x6e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w8, 1, vgx2], { z1.h, z2.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x68, 0x5e, 0x64, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w10, 0, vgx2], { z19.h, z20.h }, z4.h"
+
+  -
+    input:
+      bytes: [ 0x68, 0x5e, 0x64, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w10, 0, vgx2], { z19.h, z20.h }, z4.h"
+
+  -
+    input:
+      bytes: [ 0x88, 0x1d, 0x62, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w8, 0, vgx2], { z12.h, z13.h }, z2.h"
+
+  -
+    input:
+      bytes: [ 0x88, 0x1d, 0x62, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w8, 0, vgx2], { z12.h, z13.h }, z2.h"
+
+  -
+    input:
+      bytes: [ 0x29, 0x5c, 0x6a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w10, 1, vgx2], { z1.h, z2.h }, z10.h"
+
+  -
+    input:
+      bytes: [ 0x29, 0x5c, 0x6a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w10, 1, vgx2], { z1.h, z2.h }, z10.h"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x1e, 0x6e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w8, 5, vgx2], { z22.h, z23.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x1e, 0x6e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w8, 5, vgx2], { z22.h, z23.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x2a, 0x7d, 0x61, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w11, 2, vgx2], { z9.h, z10.h }, z1.h"
+
+  -
+    input:
+      bytes: [ 0x2a, 0x7d, 0x61, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w11, 2, vgx2], { z9.h, z10.h }, z1.h"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x3d, 0x6b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w9, 7, vgx2], { z12.h, z13.h }, z11.h"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x3d, 0x6b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w9, 7, vgx2], { z12.h, z13.h }, z11.h"
+
+  -
+    input:
+      bytes: [ 0x30, 0x10, 0x10, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w8, 0, vgx2], { z0.h, z1.h }, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x30, 0x10, 0x10, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w8, 0, vgx2], { z0.h, z1.h }, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x75, 0x55, 0x15, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w10, 5, vgx2], { z10.h, z11.h }, z5.h[2]"
+
+  -
+    input:
+      bytes: [ 0x75, 0x55, 0x15, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w10, 5, vgx2], { z10.h, z11.h }, z5.h[2]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x7d, 0x18, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w11, 7, vgx2], { z12.h, z13.h }, z8.h[6]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x7d, 0x18, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w11, 7, vgx2], { z12.h, z13.h }, z8.h[6]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x7f, 0x1f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w11, 7, vgx2], { z30.h, z31.h }, z15.h[7]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x7f, 0x1f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w11, 7, vgx2], { z30.h, z31.h }, z15.h[7]"
+
+  -
+    input:
+      bytes: [ 0x35, 0x1e, 0x10, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w8, 5, vgx2], { z16.h, z17.h }, z0.h[6]"
+
+  -
+    input:
+      bytes: [ 0x35, 0x1e, 0x10, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w8, 5, vgx2], { z16.h, z17.h }, z0.h[6]"
+
+  -
+    input:
+      bytes: [ 0x31, 0x14, 0x1e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w8, 1, vgx2], { z0.h, z1.h }, z14.h[2]"
+
+  -
+    input:
+      bytes: [ 0x31, 0x14, 0x1e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w8, 1, vgx2], { z0.h, z1.h }, z14.h[2]"
+
+  -
+    input:
+      bytes: [ 0x78, 0x56, 0x14, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w10, 0, vgx2], { z18.h, z19.h }, z4.h[3]"
+
+  -
+    input:
+      bytes: [ 0x78, 0x56, 0x14, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w10, 0, vgx2], { z18.h, z19.h }, z4.h[3]"
+
+  -
+    input:
+      bytes: [ 0xb0, 0x19, 0x12, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w8, 0, vgx2], { z12.h, z13.h }, z2.h[4]"
+
+  -
+    input:
+      bytes: [ 0xb0, 0x19, 0x12, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w8, 0, vgx2], { z12.h, z13.h }, z2.h[4]"
+
+  -
+    input:
+      bytes: [ 0x31, 0x58, 0x1a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w10, 1, vgx2], { z0.h, z1.h }, z10.h[4]"
+
+  -
+    input:
+      bytes: [ 0x31, 0x58, 0x1a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w10, 1, vgx2], { z0.h, z1.h }, z10.h[4]"
+
+  -
+    input:
+      bytes: [ 0xfd, 0x1a, 0x1e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w8, 5, vgx2], { z22.h, z23.h }, z14.h[5]"
+
+  -
+    input:
+      bytes: [ 0xfd, 0x1a, 0x1e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w8, 5, vgx2], { z22.h, z23.h }, z14.h[5]"
+
+  -
+    input:
+      bytes: [ 0x32, 0x75, 0x11, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w11, 2, vgx2], { z8.h, z9.h }, z1.h[2]"
+
+  -
+    input:
+      bytes: [ 0x32, 0x75, 0x11, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w11, 2, vgx2], { z8.h, z9.h }, z1.h[2]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x39, 0x1b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w9, 7, vgx2], { z12.h, z13.h }, z11.h[4]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x39, 0x1b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w9, 7, vgx2], { z12.h, z13.h }, z11.h[4]"
+
+  -
+    input:
+      bytes: [ 0x18, 0x10, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w8, 0, vgx2], { z0.h, z1.h }, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x18, 0x10, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w8, 0, vgx2], { z0.h, z1.h }, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x5d, 0x51, 0xf4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w10, 5, vgx2], { z10.h, z11.h }, { z20.h, z21.h }"
+
+  -
+    input:
+      bytes: [ 0x5d, 0x51, 0xf4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w10, 5, vgx2], { z10.h, z11.h }, { z20.h, z21.h }"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x71, 0xe8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w11, 7, vgx2], { z12.h, z13.h }, { z8.h, z9.h }"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x71, 0xe8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w11, 7, vgx2], { z12.h, z13.h }, { z8.h, z9.h }"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x73, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w11, 7, vgx2], { z30.h, z31.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x73, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w11, 7, vgx2], { z30.h, z31.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x1d, 0x12, 0xf0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w8, 5, vgx2], { z16.h, z17.h }, { z16.h, z17.h }"
+
+  -
+    input:
+      bytes: [ 0x1d, 0x12, 0xf0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w8, 5, vgx2], { z16.h, z17.h }, { z16.h, z17.h }"
+
+  -
+    input:
+      bytes: [ 0x19, 0x10, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w8, 1, vgx2], { z0.h, z1.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x19, 0x10, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w8, 1, vgx2], { z0.h, z1.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x58, 0x52, 0xf4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w10, 0, vgx2], { z18.h, z19.h }, { z20.h, z21.h }"
+
+  -
+    input:
+      bytes: [ 0x58, 0x52, 0xf4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w10, 0, vgx2], { z18.h, z19.h }, { z20.h, z21.h }"
+
+  -
+    input:
+      bytes: [ 0x98, 0x11, 0xe2, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w8, 0, vgx2], { z12.h, z13.h }, { z2.h, z3.h }"
+
+  -
+    input:
+      bytes: [ 0x98, 0x11, 0xe2, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w8, 0, vgx2], { z12.h, z13.h }, { z2.h, z3.h }"
+
+  -
+    input:
+      bytes: [ 0x19, 0x50, 0xfa, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w10, 1, vgx2], { z0.h, z1.h }, { z26.h, z27.h }"
+
+  -
+    input:
+      bytes: [ 0x19, 0x50, 0xfa, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w10, 1, vgx2], { z0.h, z1.h }, { z26.h, z27.h }"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x12, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w8, 5, vgx2], { z22.h, z23.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x12, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w8, 5, vgx2], { z22.h, z23.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x1a, 0x71, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w11, 2, vgx2], { z8.h, z9.h }, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x1a, 0x71, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w11, 2, vgx2], { z8.h, z9.h }, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x31, 0xea, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w9, 7, vgx2], { z12.h, z13.h }, { z10.h, z11.h }"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x31, 0xea, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w9, 7, vgx2], { z12.h, z13.h }, { z10.h, z11.h }"
+
+  -
+    input:
+      bytes: [ 0x08, 0x1c, 0x70, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w8, 0, vgx4], { z0.h - z3.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x08, 0x1c, 0x70, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w8, 0, vgx4], { z0.h - z3.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x4d, 0x5d, 0x75, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w10, 5, vgx4], { z10.h - z13.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0x4d, 0x5d, 0x75, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w10, 5, vgx4], { z10.h - z13.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0xaf, 0x7d, 0x78, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w11, 7, vgx4], { z13.h - z16.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0xaf, 0x7d, 0x78, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w11, 7, vgx4], { z13.h - z16.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0xef, 0x7f, 0x7f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w11, 7, vgx4], { z31.h, z0.h, z1.h, z2.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0xef, 0x7f, 0x7f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w11, 7, vgx4], { z31.h, z0.h, z1.h, z2.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0x2d, 0x1e, 0x70, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w8, 5, vgx4], { z17.h - z20.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x2d, 0x1e, 0x70, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w8, 5, vgx4], { z17.h - z20.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x29, 0x1c, 0x7e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w8, 1, vgx4], { z1.h - z4.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x29, 0x1c, 0x7e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w8, 1, vgx4], { z1.h - z4.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x68, 0x5e, 0x74, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w10, 0, vgx4], { z19.h - z22.h }, z4.h"
+
+  -
+    input:
+      bytes: [ 0x68, 0x5e, 0x74, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w10, 0, vgx4], { z19.h - z22.h }, z4.h"
+
+  -
+    input:
+      bytes: [ 0x88, 0x1d, 0x72, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w8, 0, vgx4], { z12.h - z15.h }, z2.h"
+
+  -
+    input:
+      bytes: [ 0x88, 0x1d, 0x72, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w8, 0, vgx4], { z12.h - z15.h }, z2.h"
+
+  -
+    input:
+      bytes: [ 0x29, 0x5c, 0x7a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w10, 1, vgx4], { z1.h - z4.h }, z10.h"
+
+  -
+    input:
+      bytes: [ 0x29, 0x5c, 0x7a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w10, 1, vgx4], { z1.h - z4.h }, z10.h"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x1e, 0x7e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w8, 5, vgx4], { z22.h - z25.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x1e, 0x7e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w8, 5, vgx4], { z22.h - z25.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x2a, 0x7d, 0x71, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w11, 2, vgx4], { z9.h - z12.h }, z1.h"
+
+  -
+    input:
+      bytes: [ 0x2a, 0x7d, 0x71, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w11, 2, vgx4], { z9.h - z12.h }, z1.h"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x3d, 0x7b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w9, 7, vgx4], { z12.h - z15.h }, z11.h"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x3d, 0x7b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w9, 7, vgx4], { z12.h - z15.h }, z11.h"
+
+  -
+    input:
+      bytes: [ 0x30, 0x90, 0x10, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w8, 0, vgx4], { z0.h - z3.h }, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x30, 0x90, 0x10, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w8, 0, vgx4], { z0.h - z3.h }, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x35, 0xd5, 0x15, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w10, 5, vgx4], { z8.h - z11.h }, z5.h[2]"
+
+  -
+    input:
+      bytes: [ 0x35, 0xd5, 0x15, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w10, 5, vgx4], { z8.h - z11.h }, z5.h[2]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xfd, 0x18, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w11, 7, vgx4], { z12.h - z15.h }, z8.h[6]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xfd, 0x18, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w11, 7, vgx4], { z12.h - z15.h }, z8.h[6]"
+
+  -
+    input:
+      bytes: [ 0xbf, 0xff, 0x1f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w11, 7, vgx4], { z28.h - z31.h }, z15.h[7]"
+
+  -
+    input:
+      bytes: [ 0xbf, 0xff, 0x1f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w11, 7, vgx4], { z28.h - z31.h }, z15.h[7]"
+
+  -
+    input:
+      bytes: [ 0x35, 0x9e, 0x10, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w8, 5, vgx4], { z16.h - z19.h }, z0.h[6]"
+
+  -
+    input:
+      bytes: [ 0x35, 0x9e, 0x10, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w8, 5, vgx4], { z16.h - z19.h }, z0.h[6]"
+
+  -
+    input:
+      bytes: [ 0x31, 0x94, 0x1e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w8, 1, vgx4], { z0.h - z3.h }, z14.h[2]"
+
+  -
+    input:
+      bytes: [ 0x31, 0x94, 0x1e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w8, 1, vgx4], { z0.h - z3.h }, z14.h[2]"
+
+  -
+    input:
+      bytes: [ 0x38, 0xd6, 0x14, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w10, 0, vgx4], { z16.h - z19.h }, z4.h[3]"
+
+  -
+    input:
+      bytes: [ 0x38, 0xd6, 0x14, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w10, 0, vgx4], { z16.h - z19.h }, z4.h[3]"
+
+  -
+    input:
+      bytes: [ 0xb0, 0x99, 0x12, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w8, 0, vgx4], { z12.h - z15.h }, z2.h[4]"
+
+  -
+    input:
+      bytes: [ 0xb0, 0x99, 0x12, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w8, 0, vgx4], { z12.h - z15.h }, z2.h[4]"
+
+  -
+    input:
+      bytes: [ 0x31, 0xd8, 0x1a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w10, 1, vgx4], { z0.h - z3.h }, z10.h[4]"
+
+  -
+    input:
+      bytes: [ 0x31, 0xd8, 0x1a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w10, 1, vgx4], { z0.h - z3.h }, z10.h[4]"
+
+  -
+    input:
+      bytes: [ 0xbd, 0x9a, 0x1e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w8, 5, vgx4], { z20.h - z23.h }, z14.h[5]"
+
+  -
+    input:
+      bytes: [ 0xbd, 0x9a, 0x1e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w8, 5, vgx4], { z20.h - z23.h }, z14.h[5]"
+
+  -
+    input:
+      bytes: [ 0x32, 0xf5, 0x11, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w11, 2, vgx4], { z8.h - z11.h }, z1.h[2]"
+
+  -
+    input:
+      bytes: [ 0x32, 0xf5, 0x11, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w11, 2, vgx4], { z8.h - z11.h }, z1.h[2]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xb9, 0x1b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w9, 7, vgx4], { z12.h - z15.h }, z11.h[4]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xb9, 0x1b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w9, 7, vgx4], { z12.h - z15.h }, z11.h[4]"
+
+  -
+    input:
+      bytes: [ 0x18, 0x10, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w8, 0, vgx4], { z0.h - z3.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x18, 0x10, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w8, 0, vgx4], { z0.h - z3.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x1d, 0x51, 0xf5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w10, 5, vgx4], { z8.h - z11.h }, { z20.h - z23.h }"
+
+  -
+    input:
+      bytes: [ 0x1d, 0x51, 0xf5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w10, 5, vgx4], { z8.h - z11.h }, { z20.h - z23.h }"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x71, 0xe9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w11, 7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x71, 0xe9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w11, 7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x73, 0xfd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w11, 7, vgx4], { z28.h - z31.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x73, 0xfd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w11, 7, vgx4], { z28.h - z31.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x1d, 0x12, 0xf1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w8, 5, vgx4], { z16.h - z19.h }, { z16.h - z19.h }"
+
+  -
+    input:
+      bytes: [ 0x1d, 0x12, 0xf1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w8, 5, vgx4], { z16.h - z19.h }, { z16.h - z19.h }"
+
+  -
+    input:
+      bytes: [ 0x19, 0x10, 0xfd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w8, 1, vgx4], { z0.h - z3.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x19, 0x10, 0xfd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w8, 1, vgx4], { z0.h - z3.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x18, 0x52, 0xf5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w10, 0, vgx4], { z16.h - z19.h }, { z20.h - z23.h }"
+
+  -
+    input:
+      bytes: [ 0x18, 0x52, 0xf5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w10, 0, vgx4], { z16.h - z19.h }, { z20.h - z23.h }"
+
+  -
+    input:
+      bytes: [ 0x98, 0x11, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w8, 0, vgx4], { z12.h - z15.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x98, 0x11, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w8, 0, vgx4], { z12.h - z15.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x19, 0x50, 0xf9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w10, 1, vgx4], { z0.h - z3.h }, { z24.h - z27.h }"
+
+  -
+    input:
+      bytes: [ 0x19, 0x50, 0xf9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w10, 1, vgx4], { z0.h - z3.h }, { z24.h - z27.h }"
+
+  -
+    input:
+      bytes: [ 0x9d, 0x12, 0xfd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w8, 5, vgx4], { z20.h - z23.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x9d, 0x12, 0xfd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w8, 5, vgx4], { z20.h - z23.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x1a, 0x71, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w11, 2, vgx4], { z8.h - z11.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x1a, 0x71, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w11, 2, vgx4], { z8.h - z11.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x31, 0xe9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w9, 7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x31, 0xe9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls za.h[w9, 7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }"
diff --git a/tests/MC/AArch64/SME2/bfmlsl.s.yaml b/tests/MC/AArch64/SME2/bfmlsl.s.yaml
new file mode 100644
index 000000000..8e07472f1
--- /dev/null
+++ b/tests/MC/AArch64/SME2/bfmlsl.s.yaml
@@ -0,0 +1,1680 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x18, 0x0c, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w8, 0:1], z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x5d, 0x4d, 0x25, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w10, 10:11], z10.h, z5.h"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x6d, 0x28, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w11, 14:15], z13.h, z8.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x6f, 0x2f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w11, 14:15], z31.h, z15.h"
+
+  -
+    input:
+      bytes: [ 0x3d, 0x0e, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w8, 10:11], z17.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x39, 0x0c, 0x2e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w8, 2:3], z1.h, z14.h"
+
+  -
+    input:
+      bytes: [ 0x78, 0x4e, 0x24, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w10, 0:1], z19.h, z4.h"
+
+  -
+    input:
+      bytes: [ 0x98, 0x0d, 0x22, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w8, 0:1], z12.h, z2.h"
+
+  -
+    input:
+      bytes: [ 0x39, 0x4c, 0x2a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w10, 2:3], z1.h, z10.h"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x0e, 0x2e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w8, 10:11], z22.h, z14.h"
+
+  -
+    input:
+      bytes: [ 0x3a, 0x6d, 0x21, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w11, 4:5], z9.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x2d, 0x2b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w9, 14:15], z12.h, z11.h"
+
+  -
+    input:
+      bytes: [ 0x18, 0x10, 0x80, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w8, 0:1], z0.h, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x5d, 0x55, 0x85, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w10, 10:11], z10.h, z5.h[1]"
+
+  -
+    input:
+      bytes: [ 0xbf, 0xfd, 0x88, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w11, 14:15], z13.h, z8.h[7]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0x8f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w11, 14:15], z31.h, z15.h[7]"
+
+  -
+    input:
+      bytes: [ 0x3d, 0x1e, 0x80, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w8, 10:11], z17.h, z0.h[3]"
+
+  -
+    input:
+      bytes: [ 0x39, 0x94, 0x8e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w8, 2:3], z1.h, z14.h[5]"
+
+  -
+    input:
+      bytes: [ 0x78, 0x56, 0x84, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w10, 0:1], z19.h, z4.h[1]"
+
+  -
+    input:
+      bytes: [ 0x98, 0x19, 0x82, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w8, 0:1], z12.h, z2.h[2]"
+
+  -
+    input:
+      bytes: [ 0x39, 0xd8, 0x8a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w10, 2:3], z1.h, z10.h[6]"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x1a, 0x8e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w8, 10:11], z22.h, z14.h[2]"
+
+  -
+    input:
+      bytes: [ 0x3a, 0xf5, 0x81, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w11, 4:5], z9.h, z1.h[5]"
+
+  -
+    input:
+      bytes: [ 0x9f, 0xb9, 0x8b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w9, 14:15], z12.h, z11.h[6]"
+
+  -
+    input:
+      bytes: [ 0x18, 0x08, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w8, 0:1, vgx2], { z0.h, z1.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x18, 0x08, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w8, 0:1, vgx2], { z0.h, z1.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x59, 0x49, 0x25, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w10, 2:3, vgx2], { z10.h, z11.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0x59, 0x49, 0x25, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w10, 2:3, vgx2], { z10.h, z11.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0xbb, 0x69, 0x28, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w11, 6:7, vgx2], { z13.h, z14.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0xbb, 0x69, 0x28, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w11, 6:7, vgx2], { z13.h, z14.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0xfb, 0x6b, 0x2f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w11, 6:7, vgx2], { z31.h, z0.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0xfb, 0x6b, 0x2f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w11, 6:7, vgx2], { z31.h, z0.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0x39, 0x0a, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w8, 2:3, vgx2], { z17.h, z18.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x39, 0x0a, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w8, 2:3, vgx2], { z17.h, z18.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x39, 0x08, 0x2e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w8, 2:3, vgx2], { z1.h, z2.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x39, 0x08, 0x2e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w8, 2:3, vgx2], { z1.h, z2.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x78, 0x4a, 0x24, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w10, 0:1, vgx2], { z19.h, z20.h }, z4.h"
+
+  -
+    input:
+      bytes: [ 0x78, 0x4a, 0x24, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w10, 0:1, vgx2], { z19.h, z20.h }, z4.h"
+
+  -
+    input:
+      bytes: [ 0x98, 0x09, 0x22, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w8, 0:1, vgx2], { z12.h, z13.h }, z2.h"
+
+  -
+    input:
+      bytes: [ 0x98, 0x09, 0x22, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w8, 0:1, vgx2], { z12.h, z13.h }, z2.h"
+
+  -
+    input:
+      bytes: [ 0x39, 0x48, 0x2a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w10, 2:3, vgx2], { z1.h, z2.h }, z10.h"
+
+  -
+    input:
+      bytes: [ 0x39, 0x48, 0x2a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w10, 2:3, vgx2], { z1.h, z2.h }, z10.h"
+
+  -
+    input:
+      bytes: [ 0xd9, 0x0a, 0x2e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w8, 2:3, vgx2], { z22.h, z23.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0xd9, 0x0a, 0x2e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w8, 2:3, vgx2], { z22.h, z23.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x3a, 0x69, 0x21, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w11, 4:5, vgx2], { z9.h, z10.h }, z1.h"
+
+  -
+    input:
+      bytes: [ 0x3a, 0x69, 0x21, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w11, 4:5, vgx2], { z9.h, z10.h }, z1.h"
+
+  -
+    input:
+      bytes: [ 0x9b, 0x29, 0x2b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w9, 6:7, vgx2], { z12.h, z13.h }, z11.h"
+
+  -
+    input:
+      bytes: [ 0x9b, 0x29, 0x2b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w9, 6:7, vgx2], { z12.h, z13.h }, z11.h"
+
+  -
+    input:
+      bytes: [ 0x18, 0x10, 0x90, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w8, 0:1, vgx2], { z0.h, z1.h }, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x18, 0x10, 0x90, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w8, 0:1, vgx2], { z0.h, z1.h }, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x5d, 0x55, 0x95, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w10, 2:3, vgx2], { z10.h, z11.h }, z5.h[3]"
+
+  -
+    input:
+      bytes: [ 0x5d, 0x55, 0x95, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w10, 2:3, vgx2], { z10.h, z11.h }, z5.h[3]"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x7d, 0x98, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w11, 6:7, vgx2], { z12.h, z13.h }, z8.h[7]"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x7d, 0x98, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w11, 6:7, vgx2], { z12.h, z13.h }, z8.h[7]"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x7f, 0x9f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w11, 6:7, vgx2], { z30.h, z31.h }, z15.h[7]"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x7f, 0x9f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w11, 6:7, vgx2], { z30.h, z31.h }, z15.h[7]"
+
+  -
+    input:
+      bytes: [ 0x1d, 0x1e, 0x90, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w8, 2:3, vgx2], { z16.h, z17.h }, z0.h[7]"
+
+  -
+    input:
+      bytes: [ 0x1d, 0x1e, 0x90, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w8, 2:3, vgx2], { z16.h, z17.h }, z0.h[7]"
+
+  -
+    input:
+      bytes: [ 0x19, 0x14, 0x9e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w8, 2:3, vgx2], { z0.h, z1.h }, z14.h[2]"
+
+  -
+    input:
+      bytes: [ 0x19, 0x14, 0x9e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w8, 2:3, vgx2], { z0.h, z1.h }, z14.h[2]"
+
+  -
+    input:
+      bytes: [ 0x58, 0x56, 0x94, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w10, 0:1, vgx2], { z18.h, z19.h }, z4.h[2]"
+
+  -
+    input:
+      bytes: [ 0x58, 0x56, 0x94, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w10, 0:1, vgx2], { z18.h, z19.h }, z4.h[2]"
+
+  -
+    input:
+      bytes: [ 0x98, 0x19, 0x92, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w8, 0:1, vgx2], { z12.h, z13.h }, z2.h[4]"
+
+  -
+    input:
+      bytes: [ 0x98, 0x19, 0x92, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w8, 0:1, vgx2], { z12.h, z13.h }, z2.h[4]"
+
+  -
+    input:
+      bytes: [ 0x19, 0x58, 0x9a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w10, 2:3, vgx2], { z0.h, z1.h }, z10.h[4]"
+
+  -
+    input:
+      bytes: [ 0x19, 0x58, 0x9a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w10, 2:3, vgx2], { z0.h, z1.h }, z10.h[4]"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x1a, 0x9e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w8, 2:3, vgx2], { z22.h, z23.h }, z14.h[5]"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x1a, 0x9e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w8, 2:3, vgx2], { z22.h, z23.h }, z14.h[5]"
+
+  -
+    input:
+      bytes: [ 0x1a, 0x75, 0x91, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w11, 4:5, vgx2], { z8.h, z9.h }, z1.h[2]"
+
+  -
+    input:
+      bytes: [ 0x1a, 0x75, 0x91, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w11, 4:5, vgx2], { z8.h, z9.h }, z1.h[2]"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x39, 0x9b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w9, 6:7, vgx2], { z12.h, z13.h }, z11.h[5]"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x39, 0x9b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w9, 6:7, vgx2], { z12.h, z13.h }, z11.h[5]"
+
+  -
+    input:
+      bytes: [ 0x18, 0x08, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w8, 0:1, vgx2], { z0.h, z1.h }, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x18, 0x08, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w8, 0:1, vgx2], { z0.h, z1.h }, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x59, 0x49, 0xb4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w10, 2:3, vgx2], { z10.h, z11.h }, { z20.h, z21.h }"
+
+  -
+    input:
+      bytes: [ 0x59, 0x49, 0xb4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w10, 2:3, vgx2], { z10.h, z11.h }, { z20.h, z21.h }"
+
+  -
+    input:
+      bytes: [ 0x9b, 0x69, 0xa8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w11, 6:7, vgx2], { z12.h, z13.h }, { z8.h, z9.h }"
+
+  -
+    input:
+      bytes: [ 0x9b, 0x69, 0xa8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w11, 6:7, vgx2], { z12.h, z13.h }, { z8.h, z9.h }"
+
+  -
+    input:
+      bytes: [ 0xdb, 0x6b, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w11, 6:7, vgx2], { z30.h, z31.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0xdb, 0x6b, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w11, 6:7, vgx2], { z30.h, z31.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x19, 0x0a, 0xb0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w8, 2:3, vgx2], { z16.h, z17.h }, { z16.h, z17.h }"
+
+  -
+    input:
+      bytes: [ 0x19, 0x0a, 0xb0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w8, 2:3, vgx2], { z16.h, z17.h }, { z16.h, z17.h }"
+
+  -
+    input:
+      bytes: [ 0x19, 0x08, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w8, 2:3, vgx2], { z0.h, z1.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x19, 0x08, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w8, 2:3, vgx2], { z0.h, z1.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x58, 0x4a, 0xb4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w10, 0:1, vgx2], { z18.h, z19.h }, { z20.h, z21.h }"
+
+  -
+    input:
+      bytes: [ 0x58, 0x4a, 0xb4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w10, 0:1, vgx2], { z18.h, z19.h }, { z20.h, z21.h }"
+
+  -
+    input:
+      bytes: [ 0x98, 0x09, 0xa2, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w8, 0:1, vgx2], { z12.h, z13.h }, { z2.h, z3.h }"
+
+  -
+    input:
+      bytes: [ 0x98, 0x09, 0xa2, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w8, 0:1, vgx2], { z12.h, z13.h }, { z2.h, z3.h }"
+
+  -
+    input:
+      bytes: [ 0x19, 0x48, 0xba, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w10, 2:3, vgx2], { z0.h, z1.h }, { z26.h, z27.h }"
+
+  -
+    input:
+      bytes: [ 0x19, 0x48, 0xba, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w10, 2:3, vgx2], { z0.h, z1.h }, { z26.h, z27.h }"
+
+  -
+    input:
+      bytes: [ 0xd9, 0x0a, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w8, 2:3, vgx2], { z22.h, z23.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0xd9, 0x0a, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w8, 2:3, vgx2], { z22.h, z23.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x1a, 0x69, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w11, 4:5, vgx2], { z8.h, z9.h }, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x1a, 0x69, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w11, 4:5, vgx2], { z8.h, z9.h }, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x9b, 0x29, 0xaa, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w9, 6:7, vgx2], { z12.h, z13.h }, { z10.h, z11.h }"
+
+  -
+    input:
+      bytes: [ 0x9b, 0x29, 0xaa, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w9, 6:7, vgx2], { z12.h, z13.h }, { z10.h, z11.h }"
+
+  -
+    input:
+      bytes: [ 0x18, 0x08, 0x30, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w8, 0:1, vgx4], { z0.h - z3.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x18, 0x08, 0x30, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w8, 0:1, vgx4], { z0.h - z3.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x59, 0x49, 0x35, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w10, 2:3, vgx4], { z10.h - z13.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0x59, 0x49, 0x35, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w10, 2:3, vgx4], { z10.h - z13.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0xbb, 0x69, 0x38, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w11, 6:7, vgx4], { z13.h - z16.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0xbb, 0x69, 0x38, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w11, 6:7, vgx4], { z13.h - z16.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0xfb, 0x6b, 0x3f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w11, 6:7, vgx4], { z31.h, z0.h, z1.h, z2.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0xfb, 0x6b, 0x3f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w11, 6:7, vgx4], { z31.h, z0.h, z1.h, z2.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0x39, 0x0a, 0x30, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w8, 2:3, vgx4], { z17.h - z20.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x39, 0x0a, 0x30, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w8, 2:3, vgx4], { z17.h - z20.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x39, 0x08, 0x3e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w8, 2:3, vgx4], { z1.h - z4.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x39, 0x08, 0x3e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w8, 2:3, vgx4], { z1.h - z4.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x78, 0x4a, 0x34, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w10, 0:1, vgx4], { z19.h - z22.h }, z4.h"
+
+  -
+    input:
+      bytes: [ 0x78, 0x4a, 0x34, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w10, 0:1, vgx4], { z19.h - z22.h }, z4.h"
+
+  -
+    input:
+      bytes: [ 0x98, 0x09, 0x32, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w8, 0:1, vgx4], { z12.h - z15.h }, z2.h"
+
+  -
+    input:
+      bytes: [ 0x98, 0x09, 0x32, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w8, 0:1, vgx4], { z12.h - z15.h }, z2.h"
+
+  -
+    input:
+      bytes: [ 0x39, 0x48, 0x3a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w10, 2:3, vgx4], { z1.h - z4.h }, z10.h"
+
+  -
+    input:
+      bytes: [ 0x39, 0x48, 0x3a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w10, 2:3, vgx4], { z1.h - z4.h }, z10.h"
+
+  -
+    input:
+      bytes: [ 0xd9, 0x0a, 0x3e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w8, 2:3, vgx4], { z22.h - z25.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0xd9, 0x0a, 0x3e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w8, 2:3, vgx4], { z22.h - z25.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x3a, 0x69, 0x31, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w11, 4:5, vgx4], { z9.h - z12.h }, z1.h"
+
+  -
+    input:
+      bytes: [ 0x3a, 0x69, 0x31, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w11, 4:5, vgx4], { z9.h - z12.h }, z1.h"
+
+  -
+    input:
+      bytes: [ 0x9b, 0x29, 0x3b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w9, 6:7, vgx4], { z12.h - z15.h }, z11.h"
+
+  -
+    input:
+      bytes: [ 0x9b, 0x29, 0x3b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w9, 6:7, vgx4], { z12.h - z15.h }, z11.h"
+
+  -
+    input:
+      bytes: [ 0x18, 0x90, 0x90, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w8, 0:1, vgx4], { z0.h - z3.h }, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x18, 0x90, 0x90, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w8, 0:1, vgx4], { z0.h - z3.h }, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x1d, 0xd5, 0x95, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w10, 2:3, vgx4], { z8.h - z11.h }, z5.h[3]"
+
+  -
+    input:
+      bytes: [ 0x1d, 0xd5, 0x95, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w10, 2:3, vgx4], { z8.h - z11.h }, z5.h[3]"
+
+  -
+    input:
+      bytes: [ 0x9f, 0xfd, 0x98, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w11, 6:7, vgx4], { z12.h - z15.h }, z8.h[7]"
+
+  -
+    input:
+      bytes: [ 0x9f, 0xfd, 0x98, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w11, 6:7, vgx4], { z12.h - z15.h }, z8.h[7]"
+
+  -
+    input:
+      bytes: [ 0x9f, 0xff, 0x9f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w11, 6:7, vgx4], { z28.h - z31.h }, z15.h[7]"
+
+  -
+    input:
+      bytes: [ 0x9f, 0xff, 0x9f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w11, 6:7, vgx4], { z28.h - z31.h }, z15.h[7]"
+
+  -
+    input:
+      bytes: [ 0x1d, 0x9e, 0x90, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w8, 2:3, vgx4], { z16.h - z19.h }, z0.h[7]"
+
+  -
+    input:
+      bytes: [ 0x1d, 0x9e, 0x90, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w8, 2:3, vgx4], { z16.h - z19.h }, z0.h[7]"
+
+  -
+    input:
+      bytes: [ 0x19, 0x94, 0x9e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w8, 2:3, vgx4], { z0.h - z3.h }, z14.h[2]"
+
+  -
+    input:
+      bytes: [ 0x19, 0x94, 0x9e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w8, 2:3, vgx4], { z0.h - z3.h }, z14.h[2]"
+
+  -
+    input:
+      bytes: [ 0x18, 0xd6, 0x94, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w10, 0:1, vgx4], { z16.h - z19.h }, z4.h[2]"
+
+  -
+    input:
+      bytes: [ 0x18, 0xd6, 0x94, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w10, 0:1, vgx4], { z16.h - z19.h }, z4.h[2]"
+
+  -
+    input:
+      bytes: [ 0x98, 0x99, 0x92, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w8, 0:1, vgx4], { z12.h - z15.h }, z2.h[4]"
+
+  -
+    input:
+      bytes: [ 0x98, 0x99, 0x92, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w8, 0:1, vgx4], { z12.h - z15.h }, z2.h[4]"
+
+  -
+    input:
+      bytes: [ 0x19, 0xd8, 0x9a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w10, 2:3, vgx4], { z0.h - z3.h }, z10.h[4]"
+
+  -
+    input:
+      bytes: [ 0x19, 0xd8, 0x9a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w10, 2:3, vgx4], { z0.h - z3.h }, z10.h[4]"
+
+  -
+    input:
+      bytes: [ 0x9d, 0x9a, 0x9e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w8, 2:3, vgx4], { z20.h - z23.h }, z14.h[5]"
+
+  -
+    input:
+      bytes: [ 0x9d, 0x9a, 0x9e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w8, 2:3, vgx4], { z20.h - z23.h }, z14.h[5]"
+
+  -
+    input:
+      bytes: [ 0x1a, 0xf5, 0x91, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w11, 4:5, vgx4], { z8.h - z11.h }, z1.h[2]"
+
+  -
+    input:
+      bytes: [ 0x1a, 0xf5, 0x91, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w11, 4:5, vgx4], { z8.h - z11.h }, z1.h[2]"
+
+  -
+    input:
+      bytes: [ 0x9f, 0xb9, 0x9b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w9, 6:7, vgx4], { z12.h - z15.h }, z11.h[5]"
+
+  -
+    input:
+      bytes: [ 0x9f, 0xb9, 0x9b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w9, 6:7, vgx4], { z12.h - z15.h }, z11.h[5]"
+
+  -
+    input:
+      bytes: [ 0x18, 0x08, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w8, 0:1, vgx4], { z0.h - z3.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x18, 0x08, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w8, 0:1, vgx4], { z0.h - z3.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x19, 0x49, 0xb5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w10, 2:3, vgx4], { z8.h - z11.h }, { z20.h - z23.h }"
+
+  -
+    input:
+      bytes: [ 0x19, 0x49, 0xb5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w10, 2:3, vgx4], { z8.h - z11.h }, { z20.h - z23.h }"
+
+  -
+    input:
+      bytes: [ 0x9b, 0x69, 0xa9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w11, 6:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }"
+
+  -
+    input:
+      bytes: [ 0x9b, 0x69, 0xa9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w11, 6:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }"
+
+  -
+    input:
+      bytes: [ 0x9b, 0x6b, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w11, 6:7, vgx4], { z28.h - z31.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x9b, 0x6b, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w11, 6:7, vgx4], { z28.h - z31.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x19, 0x0a, 0xb1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w8, 2:3, vgx4], { z16.h - z19.h }, { z16.h - z19.h }"
+
+  -
+    input:
+      bytes: [ 0x19, 0x0a, 0xb1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w8, 2:3, vgx4], { z16.h - z19.h }, { z16.h - z19.h }"
+
+  -
+    input:
+      bytes: [ 0x19, 0x08, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w8, 2:3, vgx4], { z0.h - z3.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x19, 0x08, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w8, 2:3, vgx4], { z0.h - z3.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x18, 0x4a, 0xb5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w10, 0:1, vgx4], { z16.h - z19.h }, { z20.h - z23.h }"
+
+  -
+    input:
+      bytes: [ 0x18, 0x4a, 0xb5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w10, 0:1, vgx4], { z16.h - z19.h }, { z20.h - z23.h }"
+
+  -
+    input:
+      bytes: [ 0x98, 0x09, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w8, 0:1, vgx4], { z12.h - z15.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x98, 0x09, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w8, 0:1, vgx4], { z12.h - z15.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x19, 0x48, 0xb9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w10, 2:3, vgx4], { z0.h - z3.h }, { z24.h - z27.h }"
+
+  -
+    input:
+      bytes: [ 0x19, 0x48, 0xb9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w10, 2:3, vgx4], { z0.h - z3.h }, { z24.h - z27.h }"
+
+  -
+    input:
+      bytes: [ 0x99, 0x0a, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w8, 2:3, vgx4], { z20.h - z23.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x99, 0x0a, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w8, 2:3, vgx4], { z20.h - z23.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x1a, 0x69, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w11, 4:5, vgx4], { z8.h - z11.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x1a, 0x69, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w11, 4:5, vgx4], { z8.h - z11.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x9b, 0x29, 0xa9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w9, 6:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }"
+
+  -
+    input:
+      bytes: [ 0x9b, 0x29, 0xa9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlsl za.s[w9, 6:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }"
diff --git a/tests/MC/AArch64/SME2/bfmopa.s.yaml b/tests/MC/AArch64/SME2/bfmopa.s.yaml
new file mode 100644
index 000000000..1b930d773
--- /dev/null
+++ b/tests/MC/AArch64/SME2/bfmopa.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x08, 0x00, 0xa0, 0x81 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmopa za0.h, p0/m, p0/m, z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x49, 0x55, 0xb5, 0x81 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmopa za1.h, p5/m, p2/m, z10.h, z21.h"
+
+  -
+    input:
+      bytes: [ 0xa9, 0xed, 0xa8, 0x81 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmopa za1.h, p3/m, p7/m, z13.h, z8.h"
+
+  -
+    input:
+      bytes: [ 0xe9, 0xff, 0xbf, 0x81 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmopa za1.h, p7/m, p7/m, z31.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x29, 0x0e, 0xb0, 0x81 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmopa za1.h, p3/m, p0/m, z17.h, z16.h"
+
+  -
+    input:
+      bytes: [ 0x29, 0x84, 0xbe, 0x81 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmopa za1.h, p1/m, p4/m, z1.h, z30.h"
+
+  -
+    input:
+      bytes: [ 0x68, 0x56, 0xb4, 0x81 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmopa za0.h, p5/m, p2/m, z19.h, z20.h"
+
+  -
+    input:
+      bytes: [ 0x88, 0x19, 0xa2, 0x81 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmopa za0.h, p6/m, p0/m, z12.h, z2.h"
+
+  -
+    input:
+      bytes: [ 0x29, 0xc8, 0xba, 0x81 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmopa za1.h, p2/m, p6/m, z1.h, z26.h"
+
+  -
+    input:
+      bytes: [ 0xc9, 0x0a, 0xbe, 0x81 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmopa za1.h, p2/m, p0/m, z22.h, z30.h"
+
+  -
+    input:
+      bytes: [ 0x28, 0xf5, 0xa1, 0x81 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmopa za0.h, p5/m, p7/m, z9.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0x89, 0xa9, 0xab, 0x81 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmopa za1.h, p2/m, p5/m, z12.h, z11.h"
diff --git a/tests/MC/AArch64/SME2/bfmops.s.yaml b/tests/MC/AArch64/SME2/bfmops.s.yaml
new file mode 100644
index 000000000..dd40d3e60
--- /dev/null
+++ b/tests/MC/AArch64/SME2/bfmops.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x18, 0x00, 0xa0, 0x81 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmops za0.h, p0/m, p0/m, z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x59, 0x55, 0xb5, 0x81 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmops za1.h, p5/m, p2/m, z10.h, z21.h"
+
+  -
+    input:
+      bytes: [ 0xb9, 0xed, 0xa8, 0x81 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmops za1.h, p3/m, p7/m, z13.h, z8.h"
+
+  -
+    input:
+      bytes: [ 0xf9, 0xff, 0xbf, 0x81 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmops za1.h, p7/m, p7/m, z31.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x39, 0x0e, 0xb0, 0x81 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmops za1.h, p3/m, p0/m, z17.h, z16.h"
+
+  -
+    input:
+      bytes: [ 0x39, 0x84, 0xbe, 0x81 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmops za1.h, p1/m, p4/m, z1.h, z30.h"
+
+  -
+    input:
+      bytes: [ 0x78, 0x56, 0xb4, 0x81 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmops za0.h, p5/m, p2/m, z19.h, z20.h"
+
+  -
+    input:
+      bytes: [ 0x98, 0x19, 0xa2, 0x81 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmops za0.h, p6/m, p0/m, z12.h, z2.h"
+
+  -
+    input:
+      bytes: [ 0x39, 0xc8, 0xba, 0x81 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmops za1.h, p2/m, p6/m, z1.h, z26.h"
+
+  -
+    input:
+      bytes: [ 0xd9, 0x0a, 0xbe, 0x81 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmops za1.h, p2/m, p0/m, z22.h, z30.h"
+
+  -
+    input:
+      bytes: [ 0x38, 0xf5, 0xa1, 0x81 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmops za0.h, p5/m, p7/m, z9.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0x99, 0xa9, 0xab, 0x81 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmops za1.h, p2/m, p5/m, z12.h, z11.h"
diff --git a/tests/MC/AArch64/SME2/bfsub.s.yaml b/tests/MC/AArch64/SME2/bfsub.s.yaml
new file mode 100644
index 000000000..48ebb3c43
--- /dev/null
+++ b/tests/MC/AArch64/SME2/bfsub.s.yaml
@@ -0,0 +1,480 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x08, 0x1c, 0xe4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfsub za.h[w8, 0, vgx2], { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x08, 0x1c, 0xe4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfsub za.h[w8, 0, vgx2], { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x4d, 0x5d, 0xe4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfsub za.h[w10, 5, vgx2], { z10.h, z11.h }"
+
+  -
+    input:
+      bytes: [ 0x4d, 0x5d, 0xe4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfsub za.h[w10, 5, vgx2], { z10.h, z11.h }"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x7d, 0xe4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfsub za.h[w11, 7, vgx2], { z12.h, z13.h }"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x7d, 0xe4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfsub za.h[w11, 7, vgx2], { z12.h, z13.h }"
+
+  -
+    input:
+      bytes: [ 0xcf, 0x7f, 0xe4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfsub za.h[w11, 7, vgx2], { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0xcf, 0x7f, 0xe4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfsub za.h[w11, 7, vgx2], { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x0d, 0x1e, 0xe4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfsub za.h[w8, 5, vgx2], { z16.h, z17.h }"
+
+  -
+    input:
+      bytes: [ 0x0d, 0x1e, 0xe4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfsub za.h[w8, 5, vgx2], { z16.h, z17.h }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x1c, 0xe4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfsub za.h[w8, 1, vgx2], { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x1c, 0xe4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfsub za.h[w8, 1, vgx2], { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x48, 0x5e, 0xe4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfsub za.h[w10, 0, vgx2], { z18.h, z19.h }"
+
+  -
+    input:
+      bytes: [ 0x48, 0x5e, 0xe4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfsub za.h[w10, 0, vgx2], { z18.h, z19.h }"
+
+  -
+    input:
+      bytes: [ 0x88, 0x1d, 0xe4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfsub za.h[w8, 0, vgx2], { z12.h, z13.h }"
+
+  -
+    input:
+      bytes: [ 0x88, 0x1d, 0xe4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfsub za.h[w8, 0, vgx2], { z12.h, z13.h }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x5c, 0xe4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfsub za.h[w10, 1, vgx2], { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x5c, 0xe4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfsub za.h[w10, 1, vgx2], { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x1e, 0xe4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfsub za.h[w8, 5, vgx2], { z22.h, z23.h }"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x1e, 0xe4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfsub za.h[w8, 5, vgx2], { z22.h, z23.h }"
+
+  -
+    input:
+      bytes: [ 0x0a, 0x7d, 0xe4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfsub za.h[w11, 2, vgx2], { z8.h, z9.h }"
+
+  -
+    input:
+      bytes: [ 0x0a, 0x7d, 0xe4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfsub za.h[w11, 2, vgx2], { z8.h, z9.h }"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x3d, 0xe4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfsub za.h[w9, 7, vgx2], { z12.h, z13.h }"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x3d, 0xe4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfsub za.h[w9, 7, vgx2], { z12.h, z13.h }"
+
+  -
+    input:
+      bytes: [ 0x08, 0x1c, 0xe5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfsub za.h[w8, 0, vgx4], { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x08, 0x1c, 0xe5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfsub za.h[w8, 0, vgx4], { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x0d, 0x5d, 0xe5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfsub za.h[w10, 5, vgx4], { z8.h - z11.h }"
+
+  -
+    input:
+      bytes: [ 0x0d, 0x5d, 0xe5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfsub za.h[w10, 5, vgx4], { z8.h - z11.h }"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x7d, 0xe5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfsub za.h[w11, 7, vgx4], { z12.h - z15.h }"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x7d, 0xe5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfsub za.h[w11, 7, vgx4], { z12.h - z15.h }"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x7f, 0xe5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfsub za.h[w11, 7, vgx4], { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x7f, 0xe5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfsub za.h[w11, 7, vgx4], { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x0d, 0x1e, 0xe5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfsub za.h[w8, 5, vgx4], { z16.h - z19.h }"
+
+  -
+    input:
+      bytes: [ 0x0d, 0x1e, 0xe5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfsub za.h[w8, 5, vgx4], { z16.h - z19.h }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x1c, 0xe5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfsub za.h[w8, 1, vgx4], { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x1c, 0xe5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfsub za.h[w8, 1, vgx4], { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x08, 0x5e, 0xe5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfsub za.h[w10, 0, vgx4], { z16.h - z19.h }"
+
+  -
+    input:
+      bytes: [ 0x08, 0x5e, 0xe5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfsub za.h[w10, 0, vgx4], { z16.h - z19.h }"
+
+  -
+    input:
+      bytes: [ 0x88, 0x1d, 0xe5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfsub za.h[w8, 0, vgx4], { z12.h - z15.h }"
+
+  -
+    input:
+      bytes: [ 0x88, 0x1d, 0xe5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfsub za.h[w8, 0, vgx4], { z12.h - z15.h }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x5c, 0xe5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfsub za.h[w10, 1, vgx4], { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x5c, 0xe5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfsub za.h[w10, 1, vgx4], { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x8d, 0x1e, 0xe5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfsub za.h[w8, 5, vgx4], { z20.h - z23.h }"
+
+  -
+    input:
+      bytes: [ 0x8d, 0x1e, 0xe5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfsub za.h[w8, 5, vgx4], { z20.h - z23.h }"
+
+  -
+    input:
+      bytes: [ 0x0a, 0x7d, 0xe5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfsub za.h[w11, 2, vgx4], { z8.h - z11.h }"
+
+  -
+    input:
+      bytes: [ 0x0a, 0x7d, 0xe5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfsub za.h[w11, 2, vgx4], { z8.h - z11.h }"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x3d, 0xe5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfsub za.h[w9, 7, vgx4], { z12.h - z15.h }"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x3d, 0xe5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfsub za.h[w9, 7, vgx4], { z12.h - z15.h }"
diff --git a/tests/MC/AArch64/SME2/bfvdot.s.yaml b/tests/MC/AArch64/SME2/bfvdot.s.yaml
new file mode 100644
index 000000000..f068776e9
--- /dev/null
+++ b/tests/MC/AArch64/SME2/bfvdot.s.yaml
@@ -0,0 +1,240 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x18, 0x00, 0x50, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfvdot za.s[w8, 0, vgx2], { z0.h, z1.h }, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x18, 0x00, 0x50, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfvdot za.s[w8, 0, vgx2], { z0.h, z1.h }, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x5d, 0x45, 0x55, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfvdot za.s[w10, 5, vgx2], { z10.h, z11.h }, z5.h[1]"
+
+  -
+    input:
+      bytes: [ 0x5d, 0x45, 0x55, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfvdot za.s[w10, 5, vgx2], { z10.h, z11.h }, z5.h[1]"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x6d, 0x58, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfvdot za.s[w11, 7, vgx2], { z12.h, z13.h }, z8.h[3]"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x6d, 0x58, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfvdot za.s[w11, 7, vgx2], { z12.h, z13.h }, z8.h[3]"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x6f, 0x5f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfvdot za.s[w11, 7, vgx2], { z30.h, z31.h }, z15.h[3]"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x6f, 0x5f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfvdot za.s[w11, 7, vgx2], { z30.h, z31.h }, z15.h[3]"
+
+  -
+    input:
+      bytes: [ 0x1d, 0x0e, 0x50, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfvdot za.s[w8, 5, vgx2], { z16.h, z17.h }, z0.h[3]"
+
+  -
+    input:
+      bytes: [ 0x1d, 0x0e, 0x50, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfvdot za.s[w8, 5, vgx2], { z16.h, z17.h }, z0.h[3]"
+
+  -
+    input:
+      bytes: [ 0x19, 0x04, 0x5e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfvdot za.s[w8, 1, vgx2], { z0.h, z1.h }, z14.h[1]"
+
+  -
+    input:
+      bytes: [ 0x19, 0x04, 0x5e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfvdot za.s[w8, 1, vgx2], { z0.h, z1.h }, z14.h[1]"
+
+  -
+    input:
+      bytes: [ 0x58, 0x46, 0x54, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfvdot za.s[w10, 0, vgx2], { z18.h, z19.h }, z4.h[1]"
+
+  -
+    input:
+      bytes: [ 0x58, 0x46, 0x54, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfvdot za.s[w10, 0, vgx2], { z18.h, z19.h }, z4.h[1]"
+
+  -
+    input:
+      bytes: [ 0x98, 0x09, 0x52, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfvdot za.s[w8, 0, vgx2], { z12.h, z13.h }, z2.h[2]"
+
+  -
+    input:
+      bytes: [ 0x98, 0x09, 0x52, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfvdot za.s[w8, 0, vgx2], { z12.h, z13.h }, z2.h[2]"
+
+  -
+    input:
+      bytes: [ 0x19, 0x48, 0x5a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfvdot za.s[w10, 1, vgx2], { z0.h, z1.h }, z10.h[2]"
+
+  -
+    input:
+      bytes: [ 0x19, 0x48, 0x5a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfvdot za.s[w10, 1, vgx2], { z0.h, z1.h }, z10.h[2]"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x0a, 0x5e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfvdot za.s[w8, 5, vgx2], { z22.h, z23.h }, z14.h[2]"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x0a, 0x5e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfvdot za.s[w8, 5, vgx2], { z22.h, z23.h }, z14.h[2]"
+
+  -
+    input:
+      bytes: [ 0x1a, 0x65, 0x51, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfvdot za.s[w11, 2, vgx2], { z8.h, z9.h }, z1.h[1]"
+
+  -
+    input:
+      bytes: [ 0x1a, 0x65, 0x51, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfvdot za.s[w11, 2, vgx2], { z8.h, z9.h }, z1.h[1]"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x29, 0x5b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfvdot za.s[w9, 7, vgx2], { z12.h, z13.h }, z11.h[2]"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x29, 0x5b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfvdot za.s[w9, 7, vgx2], { z12.h, z13.h }, z11.h[2]"
diff --git a/tests/MC/AArch64/SME2/bmopa.s.yaml b/tests/MC/AArch64/SME2/bmopa.s.yaml
new file mode 100644
index 000000000..e257e4fc5
--- /dev/null
+++ b/tests/MC/AArch64/SME2/bmopa.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x08, 0x00, 0x80, 0x80 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bmopa za0.s, p0/m, p0/m, z0.s, z0.s"
+
+  -
+    input:
+      bytes: [ 0x49, 0x55, 0x95, 0x80 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bmopa za1.s, p5/m, p2/m, z10.s, z21.s"
+
+  -
+    input:
+      bytes: [ 0xab, 0xed, 0x88, 0x80 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bmopa za3.s, p3/m, p7/m, z13.s, z8.s"
+
+  -
+    input:
+      bytes: [ 0xeb, 0xff, 0x9f, 0x80 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bmopa za3.s, p7/m, p7/m, z31.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x29, 0x0e, 0x90, 0x80 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bmopa za1.s, p3/m, p0/m, z17.s, z16.s"
+
+  -
+    input:
+      bytes: [ 0x29, 0x84, 0x9e, 0x80 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bmopa za1.s, p1/m, p4/m, z1.s, z30.s"
+
+  -
+    input:
+      bytes: [ 0x68, 0x56, 0x94, 0x80 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bmopa za0.s, p5/m, p2/m, z19.s, z20.s"
+
+  -
+    input:
+      bytes: [ 0x88, 0x19, 0x82, 0x80 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bmopa za0.s, p6/m, p0/m, z12.s, z2.s"
+
+  -
+    input:
+      bytes: [ 0x29, 0xc8, 0x9a, 0x80 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bmopa za1.s, p2/m, p6/m, z1.s, z26.s"
+
+  -
+    input:
+      bytes: [ 0xc9, 0x0a, 0x9e, 0x80 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bmopa za1.s, p2/m, p0/m, z22.s, z30.s"
+
+  -
+    input:
+      bytes: [ 0x2a, 0xf5, 0x81, 0x80 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bmopa za2.s, p5/m, p7/m, z9.s, z1.s"
+
+  -
+    input:
+      bytes: [ 0x8b, 0xa9, 0x8b, 0x80 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bmopa za3.s, p2/m, p5/m, z12.s, z11.s"
diff --git a/tests/MC/AArch64/SME2/bmops.s.yaml b/tests/MC/AArch64/SME2/bmops.s.yaml
new file mode 100644
index 000000000..b38bff822
--- /dev/null
+++ b/tests/MC/AArch64/SME2/bmops.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x18, 0x00, 0x80, 0x80 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bmops za0.s, p0/m, p0/m, z0.s, z0.s"
+
+  -
+    input:
+      bytes: [ 0x59, 0x55, 0x95, 0x80 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bmops za1.s, p5/m, p2/m, z10.s, z21.s"
+
+  -
+    input:
+      bytes: [ 0xbb, 0xed, 0x88, 0x80 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bmops za3.s, p3/m, p7/m, z13.s, z8.s"
+
+  -
+    input:
+      bytes: [ 0xfb, 0xff, 0x9f, 0x80 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bmops za3.s, p7/m, p7/m, z31.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x39, 0x0e, 0x90, 0x80 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bmops za1.s, p3/m, p0/m, z17.s, z16.s"
+
+  -
+    input:
+      bytes: [ 0x39, 0x84, 0x9e, 0x80 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bmops za1.s, p1/m, p4/m, z1.s, z30.s"
+
+  -
+    input:
+      bytes: [ 0x78, 0x56, 0x94, 0x80 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bmops za0.s, p5/m, p2/m, z19.s, z20.s"
+
+  -
+    input:
+      bytes: [ 0x98, 0x19, 0x82, 0x80 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bmops za0.s, p6/m, p0/m, z12.s, z2.s"
+
+  -
+    input:
+      bytes: [ 0x39, 0xc8, 0x9a, 0x80 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bmops za1.s, p2/m, p6/m, z1.s, z26.s"
+
+  -
+    input:
+      bytes: [ 0xd9, 0x0a, 0x9e, 0x80 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bmops za1.s, p2/m, p0/m, z22.s, z30.s"
+
+  -
+    input:
+      bytes: [ 0x3a, 0xf5, 0x81, 0x80 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bmops za2.s, p5/m, p7/m, z9.s, z1.s"
+
+  -
+    input:
+      bytes: [ 0x9b, 0xa9, 0x8b, 0x80 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bmops za3.s, p2/m, p5/m, z12.s, z11.s"
diff --git a/tests/MC/AArch64/SME2/fadd.s.yaml b/tests/MC/AArch64/SME2/fadd.s.yaml
new file mode 100644
index 000000000..d829bb48e
--- /dev/null
+++ b/tests/MC/AArch64/SME2/fadd.s.yaml
@@ -0,0 +1,960 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x1c, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.d[w8, 0, vgx2], { z0.d, z1.d }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x1c, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.d[w8, 0, vgx2], { z0.d, z1.d }"
+
+  -
+    input:
+      bytes: [ 0x45, 0x5d, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.d[w10, 5, vgx2], { z10.d, z11.d }"
+
+  -
+    input:
+      bytes: [ 0x45, 0x5d, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.d[w10, 5, vgx2], { z10.d, z11.d }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x7d, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.d[w11, 7, vgx2], { z12.d, z13.d }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x7d, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.d[w11, 7, vgx2], { z12.d, z13.d }"
+
+  -
+    input:
+      bytes: [ 0xc7, 0x7f, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.d[w11, 7, vgx2], { z30.d, z31.d }"
+
+  -
+    input:
+      bytes: [ 0xc7, 0x7f, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.d[w11, 7, vgx2], { z30.d, z31.d }"
+
+  -
+    input:
+      bytes: [ 0x05, 0x1e, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.d[w8, 5, vgx2], { z16.d, z17.d }"
+
+  -
+    input:
+      bytes: [ 0x05, 0x1e, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.d[w8, 5, vgx2], { z16.d, z17.d }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x1c, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.d[w8, 1, vgx2], { z0.d, z1.d }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x1c, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.d[w8, 1, vgx2], { z0.d, z1.d }"
+
+  -
+    input:
+      bytes: [ 0x40, 0x5e, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.d[w10, 0, vgx2], { z18.d, z19.d }"
+
+  -
+    input:
+      bytes: [ 0x40, 0x5e, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.d[w10, 0, vgx2], { z18.d, z19.d }"
+
+  -
+    input:
+      bytes: [ 0x80, 0x1d, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.d[w8, 0, vgx2], { z12.d, z13.d }"
+
+  -
+    input:
+      bytes: [ 0x80, 0x1d, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.d[w8, 0, vgx2], { z12.d, z13.d }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x5c, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.d[w10, 1, vgx2], { z0.d, z1.d }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x5c, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.d[w10, 1, vgx2], { z0.d, z1.d }"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x1e, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.d[w8, 5, vgx2], { z22.d, z23.d }"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x1e, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.d[w8, 5, vgx2], { z22.d, z23.d }"
+
+  -
+    input:
+      bytes: [ 0x02, 0x7d, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.d[w11, 2, vgx2], { z8.d, z9.d }"
+
+  -
+    input:
+      bytes: [ 0x02, 0x7d, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.d[w11, 2, vgx2], { z8.d, z9.d }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x3d, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.d[w9, 7, vgx2], { z12.d, z13.d }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x3d, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.d[w9, 7, vgx2], { z12.d, z13.d }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x1c, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.s[w8, 0, vgx2], { z0.s, z1.s }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x1c, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.s[w8, 0, vgx2], { z0.s, z1.s }"
+
+  -
+    input:
+      bytes: [ 0x45, 0x5d, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.s[w10, 5, vgx2], { z10.s, z11.s }"
+
+  -
+    input:
+      bytes: [ 0x45, 0x5d, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.s[w10, 5, vgx2], { z10.s, z11.s }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x7d, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.s[w11, 7, vgx2], { z12.s, z13.s }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x7d, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.s[w11, 7, vgx2], { z12.s, z13.s }"
+
+  -
+    input:
+      bytes: [ 0xc7, 0x7f, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.s[w11, 7, vgx2], { z30.s, z31.s }"
+
+  -
+    input:
+      bytes: [ 0xc7, 0x7f, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.s[w11, 7, vgx2], { z30.s, z31.s }"
+
+  -
+    input:
+      bytes: [ 0x05, 0x1e, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.s[w8, 5, vgx2], { z16.s, z17.s }"
+
+  -
+    input:
+      bytes: [ 0x05, 0x1e, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.s[w8, 5, vgx2], { z16.s, z17.s }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x1c, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.s[w8, 1, vgx2], { z0.s, z1.s }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x1c, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.s[w8, 1, vgx2], { z0.s, z1.s }"
+
+  -
+    input:
+      bytes: [ 0x40, 0x5e, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.s[w10, 0, vgx2], { z18.s, z19.s }"
+
+  -
+    input:
+      bytes: [ 0x40, 0x5e, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.s[w10, 0, vgx2], { z18.s, z19.s }"
+
+  -
+    input:
+      bytes: [ 0x80, 0x1d, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.s[w8, 0, vgx2], { z12.s, z13.s }"
+
+  -
+    input:
+      bytes: [ 0x80, 0x1d, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.s[w8, 0, vgx2], { z12.s, z13.s }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x5c, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.s[w10, 1, vgx2], { z0.s, z1.s }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x5c, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.s[w10, 1, vgx2], { z0.s, z1.s }"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x1e, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.s[w8, 5, vgx2], { z22.s, z23.s }"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x1e, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.s[w8, 5, vgx2], { z22.s, z23.s }"
+
+  -
+    input:
+      bytes: [ 0x02, 0x7d, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.s[w11, 2, vgx2], { z8.s, z9.s }"
+
+  -
+    input:
+      bytes: [ 0x02, 0x7d, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.s[w11, 2, vgx2], { z8.s, z9.s }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x3d, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.s[w9, 7, vgx2], { z12.s, z13.s }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x3d, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.s[w9, 7, vgx2], { z12.s, z13.s }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x1c, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.d[w8, 0, vgx4], { z0.d - z3.d }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x1c, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.d[w8, 0, vgx4], { z0.d - z3.d }"
+
+  -
+    input:
+      bytes: [ 0x05, 0x5d, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.d[w10, 5, vgx4], { z8.d - z11.d }"
+
+  -
+    input:
+      bytes: [ 0x05, 0x5d, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.d[w10, 5, vgx4], { z8.d - z11.d }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x7d, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.d[w11, 7, vgx4], { z12.d - z15.d }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x7d, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.d[w11, 7, vgx4], { z12.d - z15.d }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x7f, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.d[w11, 7, vgx4], { z28.d - z31.d }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x7f, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.d[w11, 7, vgx4], { z28.d - z31.d }"
+
+  -
+    input:
+      bytes: [ 0x05, 0x1e, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.d[w8, 5, vgx4], { z16.d - z19.d }"
+
+  -
+    input:
+      bytes: [ 0x05, 0x1e, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.d[w8, 5, vgx4], { z16.d - z19.d }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x1c, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.d[w8, 1, vgx4], { z0.d - z3.d }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x1c, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.d[w8, 1, vgx4], { z0.d - z3.d }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x5e, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.d[w10, 0, vgx4], { z16.d - z19.d }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x5e, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.d[w10, 0, vgx4], { z16.d - z19.d }"
+
+  -
+    input:
+      bytes: [ 0x80, 0x1d, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.d[w8, 0, vgx4], { z12.d - z15.d }"
+
+  -
+    input:
+      bytes: [ 0x80, 0x1d, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.d[w8, 0, vgx4], { z12.d - z15.d }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x5c, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.d[w10, 1, vgx4], { z0.d - z3.d }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x5c, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.d[w10, 1, vgx4], { z0.d - z3.d }"
+
+  -
+    input:
+      bytes: [ 0x85, 0x1e, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.d[w8, 5, vgx4], { z20.d - z23.d }"
+
+  -
+    input:
+      bytes: [ 0x85, 0x1e, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.d[w8, 5, vgx4], { z20.d - z23.d }"
+
+  -
+    input:
+      bytes: [ 0x02, 0x7d, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.d[w11, 2, vgx4], { z8.d - z11.d }"
+
+  -
+    input:
+      bytes: [ 0x02, 0x7d, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.d[w11, 2, vgx4], { z8.d - z11.d }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x3d, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.d[w9, 7, vgx4], { z12.d - z15.d }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x3d, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.d[w9, 7, vgx4], { z12.d - z15.d }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x1c, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.s[w8, 0, vgx4], { z0.s - z3.s }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x1c, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.s[w8, 0, vgx4], { z0.s - z3.s }"
+
+  -
+    input:
+      bytes: [ 0x05, 0x5d, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.s[w10, 5, vgx4], { z8.s - z11.s }"
+
+  -
+    input:
+      bytes: [ 0x05, 0x5d, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.s[w10, 5, vgx4], { z8.s - z11.s }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x7d, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.s[w11, 7, vgx4], { z12.s - z15.s }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x7d, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.s[w11, 7, vgx4], { z12.s - z15.s }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x7f, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.s[w11, 7, vgx4], { z28.s - z31.s }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x7f, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.s[w11, 7, vgx4], { z28.s - z31.s }"
+
+  -
+    input:
+      bytes: [ 0x05, 0x1e, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.s[w8, 5, vgx4], { z16.s - z19.s }"
+
+  -
+    input:
+      bytes: [ 0x05, 0x1e, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.s[w8, 5, vgx4], { z16.s - z19.s }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x1c, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.s[w8, 1, vgx4], { z0.s - z3.s }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x1c, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.s[w8, 1, vgx4], { z0.s - z3.s }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x5e, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.s[w10, 0, vgx4], { z16.s - z19.s }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x5e, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.s[w10, 0, vgx4], { z16.s - z19.s }"
+
+  -
+    input:
+      bytes: [ 0x80, 0x1d, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.s[w8, 0, vgx4], { z12.s - z15.s }"
+
+  -
+    input:
+      bytes: [ 0x80, 0x1d, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.s[w8, 0, vgx4], { z12.s - z15.s }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x5c, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.s[w10, 1, vgx4], { z0.s - z3.s }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x5c, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.s[w10, 1, vgx4], { z0.s - z3.s }"
+
+  -
+    input:
+      bytes: [ 0x85, 0x1e, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.s[w8, 5, vgx4], { z20.s - z23.s }"
+
+  -
+    input:
+      bytes: [ 0x85, 0x1e, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.s[w8, 5, vgx4], { z20.s - z23.s }"
+
+  -
+    input:
+      bytes: [ 0x02, 0x7d, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.s[w11, 2, vgx4], { z8.s - z11.s }"
+
+  -
+    input:
+      bytes: [ 0x02, 0x7d, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.s[w11, 2, vgx4], { z8.s - z11.s }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x3d, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.s[w9, 7, vgx4], { z12.s - z15.s }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x3d, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.s[w9, 7, vgx4], { z12.s - z15.s }"
diff --git a/tests/MC/AArch64/SME2/fclamp.s.yaml b/tests/MC/AArch64/SME2/fclamp.s.yaml
new file mode 100644
index 000000000..5c4d8d3cb
--- /dev/null
+++ b/tests/MC/AArch64/SME2/fclamp.s.yaml
@@ -0,0 +1,240 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fclamp { z0.d, z1.d }, z0.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0x54, 0xc1, 0xf5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fclamp { z20.d, z21.d }, z10.d, z21.d"
+
+  -
+    input:
+      bytes: [ 0xb6, 0xc1, 0xe8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fclamp { z22.d, z23.d }, z13.d, z8.d"
+
+  -
+    input:
+      bytes: [ 0xfe, 0xc3, 0xff, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fclamp { z30.d, z31.d }, z31.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fclamp { z0.h, z1.h }, z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x54, 0xc1, 0x75, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fclamp { z20.h, z21.h }, z10.h, z21.h"
+
+  -
+    input:
+      bytes: [ 0xb6, 0xc1, 0x68, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fclamp { z22.h, z23.h }, z13.h, z8.h"
+
+  -
+    input:
+      bytes: [ 0xfe, 0xc3, 0x7f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fclamp { z30.h, z31.h }, z31.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fclamp { z0.s, z1.s }, z0.s, z0.s"
+
+  -
+    input:
+      bytes: [ 0x54, 0xc1, 0xb5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fclamp { z20.s, z21.s }, z10.s, z21.s"
+
+  -
+    input:
+      bytes: [ 0xb6, 0xc1, 0xa8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fclamp { z22.s, z23.s }, z13.s, z8.s"
+
+  -
+    input:
+      bytes: [ 0xfe, 0xc3, 0xbf, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fclamp { z30.s, z31.s }, z31.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc8, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fclamp { z0.d - z3.d }, z0.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0x54, 0xc9, 0xf5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fclamp { z20.d - z23.d }, z10.d, z21.d"
+
+  -
+    input:
+      bytes: [ 0xb4, 0xc9, 0xe8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fclamp { z20.d - z23.d }, z13.d, z8.d"
+
+  -
+    input:
+      bytes: [ 0xfc, 0xcb, 0xff, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fclamp { z28.d - z31.d }, z31.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc8, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fclamp { z0.h - z3.h }, z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x54, 0xc9, 0x75, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fclamp { z20.h - z23.h }, z10.h, z21.h"
+
+  -
+    input:
+      bytes: [ 0xb4, 0xc9, 0x68, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fclamp { z20.h - z23.h }, z13.h, z8.h"
+
+  -
+    input:
+      bytes: [ 0xfc, 0xcb, 0x7f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fclamp { z28.h - z31.h }, z31.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc8, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fclamp { z0.s - z3.s }, z0.s, z0.s"
+
+  -
+    input:
+      bytes: [ 0x54, 0xc9, 0xb5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fclamp { z20.s - z23.s }, z10.s, z21.s"
+
+  -
+    input:
+      bytes: [ 0xb4, 0xc9, 0xa8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fclamp { z20.s - z23.s }, z13.s, z8.s"
+
+  -
+    input:
+      bytes: [ 0xfc, 0xcb, 0xbf, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fclamp { z28.s - z31.s }, z31.s, z31.s"
diff --git a/tests/MC/AArch64/SME2/fcvt.s.yaml b/tests/MC/AArch64/SME2/fcvt.s.yaml
new file mode 100644
index 000000000..a6c87c625
--- /dev/null
+++ b/tests/MC/AArch64/SME2/fcvt.s.yaml
@@ -0,0 +1,40 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvt z0.h, { z0.s, z1.s }"
+
+  -
+    input:
+      bytes: [ 0x55, 0xe1, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvt z21.h, { z10.s, z11.s }"
+
+  -
+    input:
+      bytes: [ 0x97, 0xe1, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvt z23.h, { z12.s, z13.s }"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xe3, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvt z31.h, { z30.s, z31.s }"
diff --git a/tests/MC/AArch64/SME2/fcvtn.s.yaml b/tests/MC/AArch64/SME2/fcvtn.s.yaml
new file mode 100644
index 000000000..58214af16
--- /dev/null
+++ b/tests/MC/AArch64/SME2/fcvtn.s.yaml
@@ -0,0 +1,40 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0xe0, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtn z0.h, { z0.s, z1.s }"
+
+  -
+    input:
+      bytes: [ 0x75, 0xe1, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtn z21.h, { z10.s, z11.s }"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xe1, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtn z23.h, { z12.s, z13.s }"
+
+  -
+    input:
+      bytes: [ 0xff, 0xe3, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtn z31.h, { z30.s, z31.s }"
diff --git a/tests/MC/AArch64/SME2/fcvtzs.s.yaml b/tests/MC/AArch64/SME2/fcvtzs.s.yaml
new file mode 100644
index 000000000..873341955
--- /dev/null
+++ b/tests/MC/AArch64/SME2/fcvtzs.s.yaml
@@ -0,0 +1,80 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x21, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtzs { z0.s, z1.s }, { z0.s, z1.s }"
+
+  -
+    input:
+      bytes: [ 0x54, 0xe1, 0x21, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtzs { z20.s, z21.s }, { z10.s, z11.s }"
+
+  -
+    input:
+      bytes: [ 0x96, 0xe1, 0x21, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtzs { z22.s, z23.s }, { z12.s, z13.s }"
+
+  -
+    input:
+      bytes: [ 0xde, 0xe3, 0x21, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtzs { z30.s, z31.s }, { z30.s, z31.s }"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x31, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtzs { z0.s - z3.s }, { z0.s - z3.s }"
+
+  -
+    input:
+      bytes: [ 0x14, 0xe1, 0x31, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtzs { z20.s - z23.s }, { z8.s - z11.s }"
+
+  -
+    input:
+      bytes: [ 0x94, 0xe1, 0x31, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtzs { z20.s - z23.s }, { z12.s - z15.s }"
+
+  -
+    input:
+      bytes: [ 0x9c, 0xe3, 0x31, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtzs { z28.s - z31.s }, { z28.s - z31.s }"
diff --git a/tests/MC/AArch64/SME2/fcvtzu.s.yaml b/tests/MC/AArch64/SME2/fcvtzu.s.yaml
new file mode 100644
index 000000000..2c6b4a3d3
--- /dev/null
+++ b/tests/MC/AArch64/SME2/fcvtzu.s.yaml
@@ -0,0 +1,80 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0xe0, 0x21, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtzu { z0.s, z1.s }, { z0.s, z1.s }"
+
+  -
+    input:
+      bytes: [ 0x74, 0xe1, 0x21, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtzu { z20.s, z21.s }, { z10.s, z11.s }"
+
+  -
+    input:
+      bytes: [ 0xb6, 0xe1, 0x21, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtzu { z22.s, z23.s }, { z12.s, z13.s }"
+
+  -
+    input:
+      bytes: [ 0xfe, 0xe3, 0x21, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtzu { z30.s, z31.s }, { z30.s, z31.s }"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe0, 0x31, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtzu { z0.s - z3.s }, { z0.s - z3.s }"
+
+  -
+    input:
+      bytes: [ 0x34, 0xe1, 0x31, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtzu { z20.s - z23.s }, { z8.s - z11.s }"
+
+  -
+    input:
+      bytes: [ 0xb4, 0xe1, 0x31, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtzu { z20.s - z23.s }, { z12.s - z15.s }"
+
+  -
+    input:
+      bytes: [ 0xbc, 0xe3, 0x31, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtzu { z28.s - z31.s }, { z28.s - z31.s }"
diff --git a/tests/MC/AArch64/SME2/fdot.s.yaml b/tests/MC/AArch64/SME2/fdot.s.yaml
new file mode 100644
index 000000000..8a069140a
--- /dev/null
+++ b/tests/MC/AArch64/SME2/fdot.s.yaml
@@ -0,0 +1,1440 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x10, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w8, 0, vgx2], { z0.h, z1.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x10, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w8, 0, vgx2], { z0.h, z1.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x45, 0x51, 0x25, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w10, 5, vgx2], { z10.h, z11.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0x45, 0x51, 0x25, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w10, 5, vgx2], { z10.h, z11.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0xa7, 0x71, 0x28, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w11, 7, vgx2], { z13.h, z14.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0xa7, 0x71, 0x28, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w11, 7, vgx2], { z13.h, z14.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0xe7, 0x73, 0x2f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w11, 7, vgx2], { z31.h, z0.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0xe7, 0x73, 0x2f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w11, 7, vgx2], { z31.h, z0.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0x25, 0x12, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w8, 5, vgx2], { z17.h, z18.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x25, 0x12, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w8, 5, vgx2], { z17.h, z18.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x21, 0x10, 0x2e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w8, 1, vgx2], { z1.h, z2.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x21, 0x10, 0x2e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w8, 1, vgx2], { z1.h, z2.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x60, 0x52, 0x24, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w10, 0, vgx2], { z19.h, z20.h }, z4.h"
+
+  -
+    input:
+      bytes: [ 0x60, 0x52, 0x24, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w10, 0, vgx2], { z19.h, z20.h }, z4.h"
+
+  -
+    input:
+      bytes: [ 0x80, 0x11, 0x22, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w8, 0, vgx2], { z12.h, z13.h }, z2.h"
+
+  -
+    input:
+      bytes: [ 0x80, 0x11, 0x22, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w8, 0, vgx2], { z12.h, z13.h }, z2.h"
+
+  -
+    input:
+      bytes: [ 0x21, 0x50, 0x2a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w10, 1, vgx2], { z1.h, z2.h }, z10.h"
+
+  -
+    input:
+      bytes: [ 0x21, 0x50, 0x2a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w10, 1, vgx2], { z1.h, z2.h }, z10.h"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x12, 0x2e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w8, 5, vgx2], { z22.h, z23.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x12, 0x2e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w8, 5, vgx2], { z22.h, z23.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x22, 0x71, 0x21, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w11, 2, vgx2], { z9.h, z10.h }, z1.h"
+
+  -
+    input:
+      bytes: [ 0x22, 0x71, 0x21, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w11, 2, vgx2], { z9.h, z10.h }, z1.h"
+
+  -
+    input:
+      bytes: [ 0x87, 0x31, 0x2b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w9, 7, vgx2], { z12.h, z13.h }, z11.h"
+
+  -
+    input:
+      bytes: [ 0x87, 0x31, 0x2b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w9, 7, vgx2], { z12.h, z13.h }, z11.h"
+
+  -
+    input:
+      bytes: [ 0x08, 0x10, 0x50, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w8, 0, vgx2], { z0.h, z1.h }, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x08, 0x10, 0x50, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w8, 0, vgx2], { z0.h, z1.h }, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x4d, 0x55, 0x55, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w10, 5, vgx2], { z10.h, z11.h }, z5.h[1]"
+
+  -
+    input:
+      bytes: [ 0x4d, 0x55, 0x55, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w10, 5, vgx2], { z10.h, z11.h }, z5.h[1]"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x7d, 0x58, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w11, 7, vgx2], { z12.h, z13.h }, z8.h[3]"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x7d, 0x58, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w11, 7, vgx2], { z12.h, z13.h }, z8.h[3]"
+
+  -
+    input:
+      bytes: [ 0xcf, 0x7f, 0x5f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w11, 7, vgx2], { z30.h, z31.h }, z15.h[3]"
+
+  -
+    input:
+      bytes: [ 0xcf, 0x7f, 0x5f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w11, 7, vgx2], { z30.h, z31.h }, z15.h[3]"
+
+  -
+    input:
+      bytes: [ 0x0d, 0x1e, 0x50, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w8, 5, vgx2], { z16.h, z17.h }, z0.h[3]"
+
+  -
+    input:
+      bytes: [ 0x0d, 0x1e, 0x50, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w8, 5, vgx2], { z16.h, z17.h }, z0.h[3]"
+
+  -
+    input:
+      bytes: [ 0x09, 0x14, 0x5e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w8, 1, vgx2], { z0.h, z1.h }, z14.h[1]"
+
+  -
+    input:
+      bytes: [ 0x09, 0x14, 0x5e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w8, 1, vgx2], { z0.h, z1.h }, z14.h[1]"
+
+  -
+    input:
+      bytes: [ 0x48, 0x56, 0x54, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w10, 0, vgx2], { z18.h, z19.h }, z4.h[1]"
+
+  -
+    input:
+      bytes: [ 0x48, 0x56, 0x54, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w10, 0, vgx2], { z18.h, z19.h }, z4.h[1]"
+
+  -
+    input:
+      bytes: [ 0x88, 0x19, 0x52, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w8, 0, vgx2], { z12.h, z13.h }, z2.h[2]"
+
+  -
+    input:
+      bytes: [ 0x88, 0x19, 0x52, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w8, 0, vgx2], { z12.h, z13.h }, z2.h[2]"
+
+  -
+    input:
+      bytes: [ 0x09, 0x58, 0x5a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w10, 1, vgx2], { z0.h, z1.h }, z10.h[2]"
+
+  -
+    input:
+      bytes: [ 0x09, 0x58, 0x5a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w10, 1, vgx2], { z0.h, z1.h }, z10.h[2]"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x1a, 0x5e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w8, 5, vgx2], { z22.h, z23.h }, z14.h[2]"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x1a, 0x5e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w8, 5, vgx2], { z22.h, z23.h }, z14.h[2]"
+
+  -
+    input:
+      bytes: [ 0x0a, 0x75, 0x51, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w11, 2, vgx2], { z8.h, z9.h }, z1.h[1]"
+
+  -
+    input:
+      bytes: [ 0x0a, 0x75, 0x51, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w11, 2, vgx2], { z8.h, z9.h }, z1.h[1]"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x39, 0x5b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w9, 7, vgx2], { z12.h, z13.h }, z11.h[2]"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x39, 0x5b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w9, 7, vgx2], { z12.h, z13.h }, z11.h[2]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x10, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w8, 0, vgx2], { z0.h, z1.h }, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x10, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w8, 0, vgx2], { z0.h, z1.h }, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x45, 0x51, 0xb4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w10, 5, vgx2], { z10.h, z11.h }, { z20.h, z21.h }"
+
+  -
+    input:
+      bytes: [ 0x45, 0x51, 0xb4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w10, 5, vgx2], { z10.h, z11.h }, { z20.h, z21.h }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x71, 0xa8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w11, 7, vgx2], { z12.h, z13.h }, { z8.h, z9.h }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x71, 0xa8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w11, 7, vgx2], { z12.h, z13.h }, { z8.h, z9.h }"
+
+  -
+    input:
+      bytes: [ 0xc7, 0x73, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w11, 7, vgx2], { z30.h, z31.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0xc7, 0x73, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w11, 7, vgx2], { z30.h, z31.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x05, 0x12, 0xb0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w8, 5, vgx2], { z16.h, z17.h }, { z16.h, z17.h }"
+
+  -
+    input:
+      bytes: [ 0x05, 0x12, 0xb0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w8, 5, vgx2], { z16.h, z17.h }, { z16.h, z17.h }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x10, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w8, 1, vgx2], { z0.h, z1.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x10, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w8, 1, vgx2], { z0.h, z1.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x40, 0x52, 0xb4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w10, 0, vgx2], { z18.h, z19.h }, { z20.h, z21.h }"
+
+  -
+    input:
+      bytes: [ 0x40, 0x52, 0xb4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w10, 0, vgx2], { z18.h, z19.h }, { z20.h, z21.h }"
+
+  -
+    input:
+      bytes: [ 0x80, 0x11, 0xa2, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w8, 0, vgx2], { z12.h, z13.h }, { z2.h, z3.h }"
+
+  -
+    input:
+      bytes: [ 0x80, 0x11, 0xa2, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w8, 0, vgx2], { z12.h, z13.h }, { z2.h, z3.h }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x50, 0xba, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w10, 1, vgx2], { z0.h, z1.h }, { z26.h, z27.h }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x50, 0xba, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w10, 1, vgx2], { z0.h, z1.h }, { z26.h, z27.h }"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x12, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w8, 5, vgx2], { z22.h, z23.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x12, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w8, 5, vgx2], { z22.h, z23.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x02, 0x71, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w11, 2, vgx2], { z8.h, z9.h }, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x02, 0x71, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w11, 2, vgx2], { z8.h, z9.h }, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x31, 0xaa, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w9, 7, vgx2], { z12.h, z13.h }, { z10.h, z11.h }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x31, 0xaa, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w9, 7, vgx2], { z12.h, z13.h }, { z10.h, z11.h }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x10, 0x30, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w8, 0, vgx4], { z0.h - z3.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x10, 0x30, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w8, 0, vgx4], { z0.h - z3.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x45, 0x51, 0x35, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w10, 5, vgx4], { z10.h - z13.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0x45, 0x51, 0x35, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w10, 5, vgx4], { z10.h - z13.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0xa7, 0x71, 0x38, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w11, 7, vgx4], { z13.h - z16.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0xa7, 0x71, 0x38, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w11, 7, vgx4], { z13.h - z16.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0xe7, 0x73, 0x3f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w11, 7, vgx4], { z31.h, z0.h, z1.h, z2.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0xe7, 0x73, 0x3f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w11, 7, vgx4], { z31.h, z0.h, z1.h, z2.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0x25, 0x12, 0x30, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w8, 5, vgx4], { z17.h - z20.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x25, 0x12, 0x30, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w8, 5, vgx4], { z17.h - z20.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x21, 0x10, 0x3e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w8, 1, vgx4], { z1.h - z4.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x21, 0x10, 0x3e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w8, 1, vgx4], { z1.h - z4.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x60, 0x52, 0x34, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w10, 0, vgx4], { z19.h - z22.h }, z4.h"
+
+  -
+    input:
+      bytes: [ 0x60, 0x52, 0x34, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w10, 0, vgx4], { z19.h - z22.h }, z4.h"
+
+  -
+    input:
+      bytes: [ 0x80, 0x11, 0x32, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w8, 0, vgx4], { z12.h - z15.h }, z2.h"
+
+  -
+    input:
+      bytes: [ 0x80, 0x11, 0x32, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w8, 0, vgx4], { z12.h - z15.h }, z2.h"
+
+  -
+    input:
+      bytes: [ 0x21, 0x50, 0x3a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w10, 1, vgx4], { z1.h - z4.h }, z10.h"
+
+  -
+    input:
+      bytes: [ 0x21, 0x50, 0x3a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w10, 1, vgx4], { z1.h - z4.h }, z10.h"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x12, 0x3e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w8, 5, vgx4], { z22.h - z25.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x12, 0x3e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w8, 5, vgx4], { z22.h - z25.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x22, 0x71, 0x31, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w11, 2, vgx4], { z9.h - z12.h }, z1.h"
+
+  -
+    input:
+      bytes: [ 0x22, 0x71, 0x31, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w11, 2, vgx4], { z9.h - z12.h }, z1.h"
+
+  -
+    input:
+      bytes: [ 0x87, 0x31, 0x3b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w9, 7, vgx4], { z12.h - z15.h }, z11.h"
+
+  -
+    input:
+      bytes: [ 0x87, 0x31, 0x3b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w9, 7, vgx4], { z12.h - z15.h }, z11.h"
+
+  -
+    input:
+      bytes: [ 0x08, 0x90, 0x50, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w8, 0, vgx4], { z0.h - z3.h }, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x08, 0x90, 0x50, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w8, 0, vgx4], { z0.h - z3.h }, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x0d, 0xd5, 0x55, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w10, 5, vgx4], { z8.h - z11.h }, z5.h[1]"
+
+  -
+    input:
+      bytes: [ 0x0d, 0xd5, 0x55, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w10, 5, vgx4], { z8.h - z11.h }, z5.h[1]"
+
+  -
+    input:
+      bytes: [ 0x8f, 0xfd, 0x58, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w11, 7, vgx4], { z12.h - z15.h }, z8.h[3]"
+
+  -
+    input:
+      bytes: [ 0x8f, 0xfd, 0x58, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w11, 7, vgx4], { z12.h - z15.h }, z8.h[3]"
+
+  -
+    input:
+      bytes: [ 0x8f, 0xff, 0x5f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w11, 7, vgx4], { z28.h - z31.h }, z15.h[3]"
+
+  -
+    input:
+      bytes: [ 0x8f, 0xff, 0x5f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w11, 7, vgx4], { z28.h - z31.h }, z15.h[3]"
+
+  -
+    input:
+      bytes: [ 0x0d, 0x9e, 0x50, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w8, 5, vgx4], { z16.h - z19.h }, z0.h[3]"
+
+  -
+    input:
+      bytes: [ 0x0d, 0x9e, 0x50, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w8, 5, vgx4], { z16.h - z19.h }, z0.h[3]"
+
+  -
+    input:
+      bytes: [ 0x09, 0x94, 0x5e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w8, 1, vgx4], { z0.h - z3.h }, z14.h[1]"
+
+  -
+    input:
+      bytes: [ 0x09, 0x94, 0x5e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w8, 1, vgx4], { z0.h - z3.h }, z14.h[1]"
+
+  -
+    input:
+      bytes: [ 0x08, 0xd6, 0x54, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w10, 0, vgx4], { z16.h - z19.h }, z4.h[1]"
+
+  -
+    input:
+      bytes: [ 0x08, 0xd6, 0x54, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w10, 0, vgx4], { z16.h - z19.h }, z4.h[1]"
+
+  -
+    input:
+      bytes: [ 0x88, 0x99, 0x52, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w8, 0, vgx4], { z12.h - z15.h }, z2.h[2]"
+
+  -
+    input:
+      bytes: [ 0x88, 0x99, 0x52, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w8, 0, vgx4], { z12.h - z15.h }, z2.h[2]"
+
+  -
+    input:
+      bytes: [ 0x09, 0xd8, 0x5a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w10, 1, vgx4], { z0.h - z3.h }, z10.h[2]"
+
+  -
+    input:
+      bytes: [ 0x09, 0xd8, 0x5a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w10, 1, vgx4], { z0.h - z3.h }, z10.h[2]"
+
+  -
+    input:
+      bytes: [ 0x8d, 0x9a, 0x5e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w8, 5, vgx4], { z20.h - z23.h }, z14.h[2]"
+
+  -
+    input:
+      bytes: [ 0x8d, 0x9a, 0x5e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w8, 5, vgx4], { z20.h - z23.h }, z14.h[2]"
+
+  -
+    input:
+      bytes: [ 0x0a, 0xf5, 0x51, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w11, 2, vgx4], { z8.h - z11.h }, z1.h[1]"
+
+  -
+    input:
+      bytes: [ 0x0a, 0xf5, 0x51, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w11, 2, vgx4], { z8.h - z11.h }, z1.h[1]"
+
+  -
+    input:
+      bytes: [ 0x8f, 0xb9, 0x5b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w9, 7, vgx4], { z12.h - z15.h }, z11.h[2]"
+
+  -
+    input:
+      bytes: [ 0x8f, 0xb9, 0x5b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w9, 7, vgx4], { z12.h - z15.h }, z11.h[2]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x10, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w8, 0, vgx4], { z0.h - z3.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x10, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w8, 0, vgx4], { z0.h - z3.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x05, 0x51, 0xb5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w10, 5, vgx4], { z8.h - z11.h }, { z20.h - z23.h }"
+
+  -
+    input:
+      bytes: [ 0x05, 0x51, 0xb5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w10, 5, vgx4], { z8.h - z11.h }, { z20.h - z23.h }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x71, 0xa9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w11, 7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x71, 0xa9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w11, 7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x73, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w11, 7, vgx4], { z28.h - z31.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x73, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w11, 7, vgx4], { z28.h - z31.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x05, 0x12, 0xb1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w8, 5, vgx4], { z16.h - z19.h }, { z16.h - z19.h }"
+
+  -
+    input:
+      bytes: [ 0x05, 0x12, 0xb1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w8, 5, vgx4], { z16.h - z19.h }, { z16.h - z19.h }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x10, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w8, 1, vgx4], { z0.h - z3.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x10, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w8, 1, vgx4], { z0.h - z3.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x52, 0xb5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w10, 0, vgx4], { z16.h - z19.h }, { z20.h - z23.h }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x52, 0xb5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w10, 0, vgx4], { z16.h - z19.h }, { z20.h - z23.h }"
+
+  -
+    input:
+      bytes: [ 0x80, 0x11, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w8, 0, vgx4], { z12.h - z15.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x80, 0x11, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w8, 0, vgx4], { z12.h - z15.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x50, 0xb9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w10, 1, vgx4], { z0.h - z3.h }, { z24.h - z27.h }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x50, 0xb9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w10, 1, vgx4], { z0.h - z3.h }, { z24.h - z27.h }"
+
+  -
+    input:
+      bytes: [ 0x85, 0x12, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w8, 5, vgx4], { z20.h - z23.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x85, 0x12, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w8, 5, vgx4], { z20.h - z23.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x02, 0x71, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w11, 2, vgx4], { z8.h - z11.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x02, 0x71, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w11, 2, vgx4], { z8.h - z11.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x31, 0xa9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w9, 7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x31, 0xa9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot za.s[w9, 7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }"
diff --git a/tests/MC/AArch64/SME2/feature-sme2-implies-sme.s.yaml b/tests/MC/AArch64/SME2/feature-sme2-implies-sme.s.yaml
new file mode 100644
index 000000000..14e92c0c2
--- /dev/null
+++ b/tests/MC/AArch64/SME2/feature-sme2-implies-sme.s.yaml
@@ -0,0 +1,10 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x90, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "addha za0.s, p0/m, p0/m, z0.s"
diff --git a/tests/MC/AArch64/SME2/fmax.s.yaml b/tests/MC/AArch64/SME2/fmax.s.yaml
new file mode 100644
index 000000000..fbf7b486d
--- /dev/null
+++ b/tests/MC/AArch64/SME2/fmax.s.yaml
@@ -0,0 +1,480 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xa1, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmax { z0.d, z1.d }, { z0.d, z1.d }, z0.d"
+
+  -
+    input:
+      bytes: [ 0x14, 0xa1, 0xe5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmax { z20.d, z21.d }, { z20.d, z21.d }, z5.d"
+
+  -
+    input:
+      bytes: [ 0x16, 0xa1, 0xe8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmax { z22.d, z23.d }, { z22.d, z23.d }, z8.d"
+
+  -
+    input:
+      bytes: [ 0x1e, 0xa1, 0xef, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmax { z30.d, z31.d }, { z30.d, z31.d }, z15.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0xb1, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmax { z0.d, z1.d }, { z0.d, z1.d }, { z0.d, z1.d }"
+
+  -
+    input:
+      bytes: [ 0x14, 0xb1, 0xf4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmax { z20.d, z21.d }, { z20.d, z21.d }, { z20.d, z21.d }"
+
+  -
+    input:
+      bytes: [ 0x16, 0xb1, 0xe8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmax { z22.d, z23.d }, { z22.d, z23.d }, { z8.d, z9.d }"
+
+  -
+    input:
+      bytes: [ 0x1e, 0xb1, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmax { z30.d, z31.d }, { z30.d, z31.d }, { z30.d, z31.d }"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa1, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmax { z0.h, z1.h }, { z0.h, z1.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x14, 0xa1, 0x65, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmax { z20.h, z21.h }, { z20.h, z21.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0x16, 0xa1, 0x68, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmax { z22.h, z23.h }, { z22.h, z23.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0x1e, 0xa1, 0x6f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmax { z30.h, z31.h }, { z30.h, z31.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0xb1, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmax { z0.h, z1.h }, { z0.h, z1.h }, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x14, 0xb1, 0x74, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmax { z20.h, z21.h }, { z20.h, z21.h }, { z20.h, z21.h }"
+
+  -
+    input:
+      bytes: [ 0x16, 0xb1, 0x68, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmax { z22.h, z23.h }, { z22.h, z23.h }, { z8.h, z9.h }"
+
+  -
+    input:
+      bytes: [ 0x1e, 0xb1, 0x7e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmax { z30.h, z31.h }, { z30.h, z31.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa1, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmax { z0.s, z1.s }, { z0.s, z1.s }, z0.s"
+
+  -
+    input:
+      bytes: [ 0x14, 0xa1, 0xa5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmax { z20.s, z21.s }, { z20.s, z21.s }, z5.s"
+
+  -
+    input:
+      bytes: [ 0x16, 0xa1, 0xa8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmax { z22.s, z23.s }, { z22.s, z23.s }, z8.s"
+
+  -
+    input:
+      bytes: [ 0x1e, 0xa1, 0xaf, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmax { z30.s, z31.s }, { z30.s, z31.s }, z15.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0xb1, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmax { z0.s, z1.s }, { z0.s, z1.s }, { z0.s, z1.s }"
+
+  -
+    input:
+      bytes: [ 0x14, 0xb1, 0xb4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmax { z20.s, z21.s }, { z20.s, z21.s }, { z20.s, z21.s }"
+
+  -
+    input:
+      bytes: [ 0x16, 0xb1, 0xa8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmax { z22.s, z23.s }, { z22.s, z23.s }, { z8.s, z9.s }"
+
+  -
+    input:
+      bytes: [ 0x1e, 0xb1, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmax { z30.s, z31.s }, { z30.s, z31.s }, { z30.s, z31.s }"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa9, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmax { z0.d - z3.d }, { z0.d - z3.d }, z0.d"
+
+  -
+    input:
+      bytes: [ 0x14, 0xa9, 0xe5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmax { z20.d - z23.d }, { z20.d - z23.d }, z5.d"
+
+  -
+    input:
+      bytes: [ 0x14, 0xa9, 0xe8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmax { z20.d - z23.d }, { z20.d - z23.d }, z8.d"
+
+  -
+    input:
+      bytes: [ 0x1c, 0xa9, 0xef, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmax { z28.d - z31.d }, { z28.d - z31.d }, z15.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0xb9, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmax { z0.d - z3.d }, { z0.d - z3.d }, { z0.d - z3.d }"
+
+  -
+    input:
+      bytes: [ 0x14, 0xb9, 0xf4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmax { z20.d - z23.d }, { z20.d - z23.d }, { z20.d - z23.d }"
+
+  -
+    input:
+      bytes: [ 0x14, 0xb9, 0xe8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmax { z20.d - z23.d }, { z20.d - z23.d }, { z8.d - z11.d }"
+
+  -
+    input:
+      bytes: [ 0x1c, 0xb9, 0xfc, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmax { z28.d - z31.d }, { z28.d - z31.d }, { z28.d - z31.d }"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa9, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmax { z0.h - z3.h }, { z0.h - z3.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x14, 0xa9, 0x65, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmax { z20.h - z23.h }, { z20.h - z23.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0x14, 0xa9, 0x68, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmax { z20.h - z23.h }, { z20.h - z23.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0x1c, 0xa9, 0x6f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmax { z28.h - z31.h }, { z28.h - z31.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0xb9, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmax { z0.h - z3.h }, { z0.h - z3.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x14, 0xb9, 0x74, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmax { z20.h - z23.h }, { z20.h - z23.h }, { z20.h - z23.h }"
+
+  -
+    input:
+      bytes: [ 0x14, 0xb9, 0x68, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmax { z20.h - z23.h }, { z20.h - z23.h }, { z8.h - z11.h }"
+
+  -
+    input:
+      bytes: [ 0x1c, 0xb9, 0x7c, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmax { z28.h - z31.h }, { z28.h - z31.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa9, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmax { z0.s - z3.s }, { z0.s - z3.s }, z0.s"
+
+  -
+    input:
+      bytes: [ 0x14, 0xa9, 0xa5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmax { z20.s - z23.s }, { z20.s - z23.s }, z5.s"
+
+  -
+    input:
+      bytes: [ 0x14, 0xa9, 0xa8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmax { z20.s - z23.s }, { z20.s - z23.s }, z8.s"
+
+  -
+    input:
+      bytes: [ 0x1c, 0xa9, 0xaf, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmax { z28.s - z31.s }, { z28.s - z31.s }, z15.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0xb9, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmax { z0.s - z3.s }, { z0.s - z3.s }, { z0.s - z3.s }"
+
+  -
+    input:
+      bytes: [ 0x14, 0xb9, 0xb4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmax { z20.s - z23.s }, { z20.s - z23.s }, { z20.s - z23.s }"
+
+  -
+    input:
+      bytes: [ 0x14, 0xb9, 0xa8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmax { z20.s - z23.s }, { z20.s - z23.s }, { z8.s - z11.s }"
+
+  -
+    input:
+      bytes: [ 0x1c, 0xb9, 0xbc, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmax { z28.s - z31.s }, { z28.s - z31.s }, { z28.s - z31.s }"
diff --git a/tests/MC/AArch64/SME2/fmaxnm.s.yaml b/tests/MC/AArch64/SME2/fmaxnm.s.yaml
new file mode 100644
index 000000000..4e7ab3660
--- /dev/null
+++ b/tests/MC/AArch64/SME2/fmaxnm.s.yaml
@@ -0,0 +1,480 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0xa1, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnm { z0.d, z1.d }, { z0.d, z1.d }, z0.d"
+
+  -
+    input:
+      bytes: [ 0x34, 0xa1, 0xe5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnm { z20.d, z21.d }, { z20.d, z21.d }, z5.d"
+
+  -
+    input:
+      bytes: [ 0x36, 0xa1, 0xe8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnm { z22.d, z23.d }, { z22.d, z23.d }, z8.d"
+
+  -
+    input:
+      bytes: [ 0x3e, 0xa1, 0xef, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnm { z30.d, z31.d }, { z30.d, z31.d }, z15.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0xb1, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnm { z0.d, z1.d }, { z0.d, z1.d }, { z0.d, z1.d }"
+
+  -
+    input:
+      bytes: [ 0x34, 0xb1, 0xf4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnm { z20.d, z21.d }, { z20.d, z21.d }, { z20.d, z21.d }"
+
+  -
+    input:
+      bytes: [ 0x36, 0xb1, 0xe8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnm { z22.d, z23.d }, { z22.d, z23.d }, { z8.d, z9.d }"
+
+  -
+    input:
+      bytes: [ 0x3e, 0xb1, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnm { z30.d, z31.d }, { z30.d, z31.d }, { z30.d, z31.d }"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa1, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnm { z0.h, z1.h }, { z0.h, z1.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x34, 0xa1, 0x65, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnm { z20.h, z21.h }, { z20.h, z21.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0x36, 0xa1, 0x68, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnm { z22.h, z23.h }, { z22.h, z23.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0x3e, 0xa1, 0x6f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnm { z30.h, z31.h }, { z30.h, z31.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0xb1, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnm { z0.h, z1.h }, { z0.h, z1.h }, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x34, 0xb1, 0x74, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnm { z20.h, z21.h }, { z20.h, z21.h }, { z20.h, z21.h }"
+
+  -
+    input:
+      bytes: [ 0x36, 0xb1, 0x68, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnm { z22.h, z23.h }, { z22.h, z23.h }, { z8.h, z9.h }"
+
+  -
+    input:
+      bytes: [ 0x3e, 0xb1, 0x7e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnm { z30.h, z31.h }, { z30.h, z31.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa1, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnm { z0.s, z1.s }, { z0.s, z1.s }, z0.s"
+
+  -
+    input:
+      bytes: [ 0x34, 0xa1, 0xa5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnm { z20.s, z21.s }, { z20.s, z21.s }, z5.s"
+
+  -
+    input:
+      bytes: [ 0x36, 0xa1, 0xa8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnm { z22.s, z23.s }, { z22.s, z23.s }, z8.s"
+
+  -
+    input:
+      bytes: [ 0x3e, 0xa1, 0xaf, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnm { z30.s, z31.s }, { z30.s, z31.s }, z15.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0xb1, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnm { z0.s, z1.s }, { z0.s, z1.s }, { z0.s, z1.s }"
+
+  -
+    input:
+      bytes: [ 0x34, 0xb1, 0xb4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnm { z20.s, z21.s }, { z20.s, z21.s }, { z20.s, z21.s }"
+
+  -
+    input:
+      bytes: [ 0x36, 0xb1, 0xa8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnm { z22.s, z23.s }, { z22.s, z23.s }, { z8.s, z9.s }"
+
+  -
+    input:
+      bytes: [ 0x3e, 0xb1, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnm { z30.s, z31.s }, { z30.s, z31.s }, { z30.s, z31.s }"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa9, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnm { z0.d - z3.d }, { z0.d - z3.d }, z0.d"
+
+  -
+    input:
+      bytes: [ 0x34, 0xa9, 0xe5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnm { z20.d - z23.d }, { z20.d - z23.d }, z5.d"
+
+  -
+    input:
+      bytes: [ 0x34, 0xa9, 0xe8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnm { z20.d - z23.d }, { z20.d - z23.d }, z8.d"
+
+  -
+    input:
+      bytes: [ 0x3c, 0xa9, 0xef, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnm { z28.d - z31.d }, { z28.d - z31.d }, z15.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0xb9, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnm { z0.d - z3.d }, { z0.d - z3.d }, { z0.d - z3.d }"
+
+  -
+    input:
+      bytes: [ 0x34, 0xb9, 0xf4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnm { z20.d - z23.d }, { z20.d - z23.d }, { z20.d - z23.d }"
+
+  -
+    input:
+      bytes: [ 0x34, 0xb9, 0xe8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnm { z20.d - z23.d }, { z20.d - z23.d }, { z8.d - z11.d }"
+
+  -
+    input:
+      bytes: [ 0x3c, 0xb9, 0xfc, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnm { z28.d - z31.d }, { z28.d - z31.d }, { z28.d - z31.d }"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa9, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnm { z0.h - z3.h }, { z0.h - z3.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x34, 0xa9, 0x65, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnm { z20.h - z23.h }, { z20.h - z23.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0x34, 0xa9, 0x68, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnm { z20.h - z23.h }, { z20.h - z23.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0x3c, 0xa9, 0x6f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnm { z28.h - z31.h }, { z28.h - z31.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0xb9, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnm { z0.h - z3.h }, { z0.h - z3.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x34, 0xb9, 0x74, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnm { z20.h - z23.h }, { z20.h - z23.h }, { z20.h - z23.h }"
+
+  -
+    input:
+      bytes: [ 0x34, 0xb9, 0x68, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnm { z20.h - z23.h }, { z20.h - z23.h }, { z8.h - z11.h }"
+
+  -
+    input:
+      bytes: [ 0x3c, 0xb9, 0x7c, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnm { z28.h - z31.h }, { z28.h - z31.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa9, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnm { z0.s - z3.s }, { z0.s - z3.s }, z0.s"
+
+  -
+    input:
+      bytes: [ 0x34, 0xa9, 0xa5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnm { z20.s - z23.s }, { z20.s - z23.s }, z5.s"
+
+  -
+    input:
+      bytes: [ 0x34, 0xa9, 0xa8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnm { z20.s - z23.s }, { z20.s - z23.s }, z8.s"
+
+  -
+    input:
+      bytes: [ 0x3c, 0xa9, 0xaf, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnm { z28.s - z31.s }, { z28.s - z31.s }, z15.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0xb9, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnm { z0.s - z3.s }, { z0.s - z3.s }, { z0.s - z3.s }"
+
+  -
+    input:
+      bytes: [ 0x34, 0xb9, 0xb4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnm { z20.s - z23.s }, { z20.s - z23.s }, { z20.s - z23.s }"
+
+  -
+    input:
+      bytes: [ 0x34, 0xb9, 0xa8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnm { z20.s - z23.s }, { z20.s - z23.s }, { z8.s - z11.s }"
+
+  -
+    input:
+      bytes: [ 0x3c, 0xb9, 0xbc, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnm { z28.s - z31.s }, { z28.s - z31.s }, { z28.s - z31.s }"
diff --git a/tests/MC/AArch64/SME2/fmin.s.yaml b/tests/MC/AArch64/SME2/fmin.s.yaml
new file mode 100644
index 000000000..b5db8d479
--- /dev/null
+++ b/tests/MC/AArch64/SME2/fmin.s.yaml
@@ -0,0 +1,480 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x01, 0xa1, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmin { z0.d, z1.d }, { z0.d, z1.d }, z0.d"
+
+  -
+    input:
+      bytes: [ 0x15, 0xa1, 0xe5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmin { z20.d, z21.d }, { z20.d, z21.d }, z5.d"
+
+  -
+    input:
+      bytes: [ 0x17, 0xa1, 0xe8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmin { z22.d, z23.d }, { z22.d, z23.d }, z8.d"
+
+  -
+    input:
+      bytes: [ 0x1f, 0xa1, 0xef, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmin { z30.d, z31.d }, { z30.d, z31.d }, z15.d"
+
+  -
+    input:
+      bytes: [ 0x01, 0xb1, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmin { z0.d, z1.d }, { z0.d, z1.d }, { z0.d, z1.d }"
+
+  -
+    input:
+      bytes: [ 0x15, 0xb1, 0xf4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmin { z20.d, z21.d }, { z20.d, z21.d }, { z20.d, z21.d }"
+
+  -
+    input:
+      bytes: [ 0x17, 0xb1, 0xe8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmin { z22.d, z23.d }, { z22.d, z23.d }, { z8.d, z9.d }"
+
+  -
+    input:
+      bytes: [ 0x1f, 0xb1, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmin { z30.d, z31.d }, { z30.d, z31.d }, { z30.d, z31.d }"
+
+  -
+    input:
+      bytes: [ 0x01, 0xa1, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmin { z0.h, z1.h }, { z0.h, z1.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x15, 0xa1, 0x65, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmin { z20.h, z21.h }, { z20.h, z21.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0x17, 0xa1, 0x68, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmin { z22.h, z23.h }, { z22.h, z23.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0x1f, 0xa1, 0x6f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmin { z30.h, z31.h }, { z30.h, z31.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0x01, 0xb1, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmin { z0.h, z1.h }, { z0.h, z1.h }, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x15, 0xb1, 0x74, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmin { z20.h, z21.h }, { z20.h, z21.h }, { z20.h, z21.h }"
+
+  -
+    input:
+      bytes: [ 0x17, 0xb1, 0x68, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmin { z22.h, z23.h }, { z22.h, z23.h }, { z8.h, z9.h }"
+
+  -
+    input:
+      bytes: [ 0x1f, 0xb1, 0x7e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmin { z30.h, z31.h }, { z30.h, z31.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x01, 0xa1, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmin { z0.s, z1.s }, { z0.s, z1.s }, z0.s"
+
+  -
+    input:
+      bytes: [ 0x15, 0xa1, 0xa5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmin { z20.s, z21.s }, { z20.s, z21.s }, z5.s"
+
+  -
+    input:
+      bytes: [ 0x17, 0xa1, 0xa8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmin { z22.s, z23.s }, { z22.s, z23.s }, z8.s"
+
+  -
+    input:
+      bytes: [ 0x1f, 0xa1, 0xaf, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmin { z30.s, z31.s }, { z30.s, z31.s }, z15.s"
+
+  -
+    input:
+      bytes: [ 0x01, 0xb1, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmin { z0.s, z1.s }, { z0.s, z1.s }, { z0.s, z1.s }"
+
+  -
+    input:
+      bytes: [ 0x15, 0xb1, 0xb4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmin { z20.s, z21.s }, { z20.s, z21.s }, { z20.s, z21.s }"
+
+  -
+    input:
+      bytes: [ 0x17, 0xb1, 0xa8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmin { z22.s, z23.s }, { z22.s, z23.s }, { z8.s, z9.s }"
+
+  -
+    input:
+      bytes: [ 0x1f, 0xb1, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmin { z30.s, z31.s }, { z30.s, z31.s }, { z30.s, z31.s }"
+
+  -
+    input:
+      bytes: [ 0x01, 0xa9, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmin { z0.d - z3.d }, { z0.d - z3.d }, z0.d"
+
+  -
+    input:
+      bytes: [ 0x15, 0xa9, 0xe5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmin { z20.d - z23.d }, { z20.d - z23.d }, z5.d"
+
+  -
+    input:
+      bytes: [ 0x15, 0xa9, 0xe8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmin { z20.d - z23.d }, { z20.d - z23.d }, z8.d"
+
+  -
+    input:
+      bytes: [ 0x1d, 0xa9, 0xef, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmin { z28.d - z31.d }, { z28.d - z31.d }, z15.d"
+
+  -
+    input:
+      bytes: [ 0x01, 0xb9, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmin { z0.d - z3.d }, { z0.d - z3.d }, { z0.d - z3.d }"
+
+  -
+    input:
+      bytes: [ 0x15, 0xb9, 0xf4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmin { z20.d - z23.d }, { z20.d - z23.d }, { z20.d - z23.d }"
+
+  -
+    input:
+      bytes: [ 0x15, 0xb9, 0xe8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmin { z20.d - z23.d }, { z20.d - z23.d }, { z8.d - z11.d }"
+
+  -
+    input:
+      bytes: [ 0x1d, 0xb9, 0xfc, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmin { z28.d - z31.d }, { z28.d - z31.d }, { z28.d - z31.d }"
+
+  -
+    input:
+      bytes: [ 0x01, 0xa9, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmin { z0.h - z3.h }, { z0.h - z3.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x15, 0xa9, 0x65, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmin { z20.h - z23.h }, { z20.h - z23.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0x15, 0xa9, 0x68, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmin { z20.h - z23.h }, { z20.h - z23.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0x1d, 0xa9, 0x6f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmin { z28.h - z31.h }, { z28.h - z31.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0x01, 0xb9, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmin { z0.h - z3.h }, { z0.h - z3.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x15, 0xb9, 0x74, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmin { z20.h - z23.h }, { z20.h - z23.h }, { z20.h - z23.h }"
+
+  -
+    input:
+      bytes: [ 0x15, 0xb9, 0x68, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmin { z20.h - z23.h }, { z20.h - z23.h }, { z8.h - z11.h }"
+
+  -
+    input:
+      bytes: [ 0x1d, 0xb9, 0x7c, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmin { z28.h - z31.h }, { z28.h - z31.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x01, 0xa9, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmin { z0.s - z3.s }, { z0.s - z3.s }, z0.s"
+
+  -
+    input:
+      bytes: [ 0x15, 0xa9, 0xa5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmin { z20.s - z23.s }, { z20.s - z23.s }, z5.s"
+
+  -
+    input:
+      bytes: [ 0x15, 0xa9, 0xa8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmin { z20.s - z23.s }, { z20.s - z23.s }, z8.s"
+
+  -
+    input:
+      bytes: [ 0x1d, 0xa9, 0xaf, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmin { z28.s - z31.s }, { z28.s - z31.s }, z15.s"
+
+  -
+    input:
+      bytes: [ 0x01, 0xb9, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmin { z0.s - z3.s }, { z0.s - z3.s }, { z0.s - z3.s }"
+
+  -
+    input:
+      bytes: [ 0x15, 0xb9, 0xb4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmin { z20.s - z23.s }, { z20.s - z23.s }, { z20.s - z23.s }"
+
+  -
+    input:
+      bytes: [ 0x15, 0xb9, 0xa8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmin { z20.s - z23.s }, { z20.s - z23.s }, { z8.s - z11.s }"
+
+  -
+    input:
+      bytes: [ 0x1d, 0xb9, 0xbc, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmin { z28.s - z31.s }, { z28.s - z31.s }, { z28.s - z31.s }"
diff --git a/tests/MC/AArch64/SME2/fminnm.s.yaml b/tests/MC/AArch64/SME2/fminnm.s.yaml
new file mode 100644
index 000000000..9c332ef6a
--- /dev/null
+++ b/tests/MC/AArch64/SME2/fminnm.s.yaml
@@ -0,0 +1,480 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x21, 0xa1, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnm { z0.d, z1.d }, { z0.d, z1.d }, z0.d"
+
+  -
+    input:
+      bytes: [ 0x35, 0xa1, 0xe5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnm { z20.d, z21.d }, { z20.d, z21.d }, z5.d"
+
+  -
+    input:
+      bytes: [ 0x37, 0xa1, 0xe8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnm { z22.d, z23.d }, { z22.d, z23.d }, z8.d"
+
+  -
+    input:
+      bytes: [ 0x3f, 0xa1, 0xef, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnm { z30.d, z31.d }, { z30.d, z31.d }, z15.d"
+
+  -
+    input:
+      bytes: [ 0x21, 0xb1, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnm { z0.d, z1.d }, { z0.d, z1.d }, { z0.d, z1.d }"
+
+  -
+    input:
+      bytes: [ 0x35, 0xb1, 0xf4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnm { z20.d, z21.d }, { z20.d, z21.d }, { z20.d, z21.d }"
+
+  -
+    input:
+      bytes: [ 0x37, 0xb1, 0xe8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnm { z22.d, z23.d }, { z22.d, z23.d }, { z8.d, z9.d }"
+
+  -
+    input:
+      bytes: [ 0x3f, 0xb1, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnm { z30.d, z31.d }, { z30.d, z31.d }, { z30.d, z31.d }"
+
+  -
+    input:
+      bytes: [ 0x21, 0xa1, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnm { z0.h, z1.h }, { z0.h, z1.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x35, 0xa1, 0x65, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnm { z20.h, z21.h }, { z20.h, z21.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0x37, 0xa1, 0x68, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnm { z22.h, z23.h }, { z22.h, z23.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0x3f, 0xa1, 0x6f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnm { z30.h, z31.h }, { z30.h, z31.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0x21, 0xb1, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnm { z0.h, z1.h }, { z0.h, z1.h }, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x35, 0xb1, 0x74, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnm { z20.h, z21.h }, { z20.h, z21.h }, { z20.h, z21.h }"
+
+  -
+    input:
+      bytes: [ 0x37, 0xb1, 0x68, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnm { z22.h, z23.h }, { z22.h, z23.h }, { z8.h, z9.h }"
+
+  -
+    input:
+      bytes: [ 0x3f, 0xb1, 0x7e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnm { z30.h, z31.h }, { z30.h, z31.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x21, 0xa1, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnm { z0.s, z1.s }, { z0.s, z1.s }, z0.s"
+
+  -
+    input:
+      bytes: [ 0x35, 0xa1, 0xa5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnm { z20.s, z21.s }, { z20.s, z21.s }, z5.s"
+
+  -
+    input:
+      bytes: [ 0x37, 0xa1, 0xa8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnm { z22.s, z23.s }, { z22.s, z23.s }, z8.s"
+
+  -
+    input:
+      bytes: [ 0x3f, 0xa1, 0xaf, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnm { z30.s, z31.s }, { z30.s, z31.s }, z15.s"
+
+  -
+    input:
+      bytes: [ 0x21, 0xb1, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnm { z0.s, z1.s }, { z0.s, z1.s }, { z0.s, z1.s }"
+
+  -
+    input:
+      bytes: [ 0x35, 0xb1, 0xb4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnm { z20.s, z21.s }, { z20.s, z21.s }, { z20.s, z21.s }"
+
+  -
+    input:
+      bytes: [ 0x37, 0xb1, 0xa8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnm { z22.s, z23.s }, { z22.s, z23.s }, { z8.s, z9.s }"
+
+  -
+    input:
+      bytes: [ 0x3f, 0xb1, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnm { z30.s, z31.s }, { z30.s, z31.s }, { z30.s, z31.s }"
+
+  -
+    input:
+      bytes: [ 0x21, 0xa9, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnm { z0.d - z3.d }, { z0.d - z3.d }, z0.d"
+
+  -
+    input:
+      bytes: [ 0x35, 0xa9, 0xe5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnm { z20.d - z23.d }, { z20.d - z23.d }, z5.d"
+
+  -
+    input:
+      bytes: [ 0x35, 0xa9, 0xe8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnm { z20.d - z23.d }, { z20.d - z23.d }, z8.d"
+
+  -
+    input:
+      bytes: [ 0x3d, 0xa9, 0xef, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnm { z28.d - z31.d }, { z28.d - z31.d }, z15.d"
+
+  -
+    input:
+      bytes: [ 0x21, 0xb9, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnm { z0.d - z3.d }, { z0.d - z3.d }, { z0.d - z3.d }"
+
+  -
+    input:
+      bytes: [ 0x35, 0xb9, 0xf4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnm { z20.d - z23.d }, { z20.d - z23.d }, { z20.d - z23.d }"
+
+  -
+    input:
+      bytes: [ 0x35, 0xb9, 0xe8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnm { z20.d - z23.d }, { z20.d - z23.d }, { z8.d - z11.d }"
+
+  -
+    input:
+      bytes: [ 0x3d, 0xb9, 0xfc, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnm { z28.d - z31.d }, { z28.d - z31.d }, { z28.d - z31.d }"
+
+  -
+    input:
+      bytes: [ 0x21, 0xa9, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnm { z0.h - z3.h }, { z0.h - z3.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x35, 0xa9, 0x65, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnm { z20.h - z23.h }, { z20.h - z23.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0x35, 0xa9, 0x68, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnm { z20.h - z23.h }, { z20.h - z23.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0x3d, 0xa9, 0x6f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnm { z28.h - z31.h }, { z28.h - z31.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0x21, 0xb9, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnm { z0.h - z3.h }, { z0.h - z3.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x35, 0xb9, 0x74, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnm { z20.h - z23.h }, { z20.h - z23.h }, { z20.h - z23.h }"
+
+  -
+    input:
+      bytes: [ 0x35, 0xb9, 0x68, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnm { z20.h - z23.h }, { z20.h - z23.h }, { z8.h - z11.h }"
+
+  -
+    input:
+      bytes: [ 0x3d, 0xb9, 0x7c, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnm { z28.h - z31.h }, { z28.h - z31.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x21, 0xa9, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnm { z0.s - z3.s }, { z0.s - z3.s }, z0.s"
+
+  -
+    input:
+      bytes: [ 0x35, 0xa9, 0xa5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnm { z20.s - z23.s }, { z20.s - z23.s }, z5.s"
+
+  -
+    input:
+      bytes: [ 0x35, 0xa9, 0xa8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnm { z20.s - z23.s }, { z20.s - z23.s }, z8.s"
+
+  -
+    input:
+      bytes: [ 0x3d, 0xa9, 0xaf, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnm { z28.s - z31.s }, { z28.s - z31.s }, z15.s"
+
+  -
+    input:
+      bytes: [ 0x21, 0xb9, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnm { z0.s - z3.s }, { z0.s - z3.s }, { z0.s - z3.s }"
+
+  -
+    input:
+      bytes: [ 0x35, 0xb9, 0xb4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnm { z20.s - z23.s }, { z20.s - z23.s }, { z20.s - z23.s }"
+
+  -
+    input:
+      bytes: [ 0x35, 0xb9, 0xa8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnm { z20.s - z23.s }, { z20.s - z23.s }, { z8.s - z11.s }"
+
+  -
+    input:
+      bytes: [ 0x3d, 0xb9, 0xbc, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnm { z28.s - z31.s }, { z28.s - z31.s }, { z28.s - z31.s }"
diff --git a/tests/MC/AArch64/SME2/fmla.s.yaml b/tests/MC/AArch64/SME2/fmla.s.yaml
new file mode 100644
index 000000000..1849c203a
--- /dev/null
+++ b/tests/MC/AArch64/SME2/fmla.s.yaml
@@ -0,0 +1,2880 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x18, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w8, 0, vgx2], { z0.d, z1.d }, z0.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x18, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w8, 0, vgx2], { z0.d, z1.d }, z0.d"
+
+  -
+    input:
+      bytes: [ 0x45, 0x59, 0x65, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w10, 5, vgx2], { z10.d, z11.d }, z5.d"
+
+  -
+    input:
+      bytes: [ 0x45, 0x59, 0x65, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w10, 5, vgx2], { z10.d, z11.d }, z5.d"
+
+  -
+    input:
+      bytes: [ 0xa7, 0x79, 0x68, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w11, 7, vgx2], { z13.d, z14.d }, z8.d"
+
+  -
+    input:
+      bytes: [ 0xa7, 0x79, 0x68, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w11, 7, vgx2], { z13.d, z14.d }, z8.d"
+
+  -
+    input:
+      bytes: [ 0xe7, 0x7b, 0x6f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w11, 7, vgx2], { z31.d, z0.d }, z15.d"
+
+  -
+    input:
+      bytes: [ 0xe7, 0x7b, 0x6f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w11, 7, vgx2], { z31.d, z0.d }, z15.d"
+
+  -
+    input:
+      bytes: [ 0x25, 0x1a, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w8, 5, vgx2], { z17.d, z18.d }, z0.d"
+
+  -
+    input:
+      bytes: [ 0x25, 0x1a, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w8, 5, vgx2], { z17.d, z18.d }, z0.d"
+
+  -
+    input:
+      bytes: [ 0x21, 0x18, 0x6e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w8, 1, vgx2], { z1.d, z2.d }, z14.d"
+
+  -
+    input:
+      bytes: [ 0x21, 0x18, 0x6e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w8, 1, vgx2], { z1.d, z2.d }, z14.d"
+
+  -
+    input:
+      bytes: [ 0x60, 0x5a, 0x64, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w10, 0, vgx2], { z19.d, z20.d }, z4.d"
+
+  -
+    input:
+      bytes: [ 0x60, 0x5a, 0x64, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w10, 0, vgx2], { z19.d, z20.d }, z4.d"
+
+  -
+    input:
+      bytes: [ 0x80, 0x19, 0x62, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w8, 0, vgx2], { z12.d, z13.d }, z2.d"
+
+  -
+    input:
+      bytes: [ 0x80, 0x19, 0x62, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w8, 0, vgx2], { z12.d, z13.d }, z2.d"
+
+  -
+    input:
+      bytes: [ 0x21, 0x58, 0x6a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w10, 1, vgx2], { z1.d, z2.d }, z10.d"
+
+  -
+    input:
+      bytes: [ 0x21, 0x58, 0x6a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w10, 1, vgx2], { z1.d, z2.d }, z10.d"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x1a, 0x6e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w8, 5, vgx2], { z22.d, z23.d }, z14.d"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x1a, 0x6e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w8, 5, vgx2], { z22.d, z23.d }, z14.d"
+
+  -
+    input:
+      bytes: [ 0x22, 0x79, 0x61, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w11, 2, vgx2], { z9.d, z10.d }, z1.d"
+
+  -
+    input:
+      bytes: [ 0x22, 0x79, 0x61, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w11, 2, vgx2], { z9.d, z10.d }, z1.d"
+
+  -
+    input:
+      bytes: [ 0x87, 0x39, 0x6b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w9, 7, vgx2], { z12.d, z13.d }, z11.d"
+
+  -
+    input:
+      bytes: [ 0x87, 0x39, 0x6b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w9, 7, vgx2], { z12.d, z13.d }, z11.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0xd0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w8, 0, vgx2], { z0.d, z1.d }, z0.d[0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0xd0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w8, 0, vgx2], { z0.d, z1.d }, z0.d[0]"
+
+  -
+    input:
+      bytes: [ 0x45, 0x45, 0xd5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w10, 5, vgx2], { z10.d, z11.d }, z5.d[1]"
+
+  -
+    input:
+      bytes: [ 0x45, 0x45, 0xd5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w10, 5, vgx2], { z10.d, z11.d }, z5.d[1]"
+
+  -
+    input:
+      bytes: [ 0x87, 0x65, 0xd8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w11, 7, vgx2], { z12.d, z13.d }, z8.d[1]"
+
+  -
+    input:
+      bytes: [ 0x87, 0x65, 0xd8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w11, 7, vgx2], { z12.d, z13.d }, z8.d[1]"
+
+  -
+    input:
+      bytes: [ 0xc7, 0x67, 0xdf, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w11, 7, vgx2], { z30.d, z31.d }, z15.d[1]"
+
+  -
+    input:
+      bytes: [ 0xc7, 0x67, 0xdf, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w11, 7, vgx2], { z30.d, z31.d }, z15.d[1]"
+
+  -
+    input:
+      bytes: [ 0x05, 0x06, 0xd0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w8, 5, vgx2], { z16.d, z17.d }, z0.d[1]"
+
+  -
+    input:
+      bytes: [ 0x05, 0x06, 0xd0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w8, 5, vgx2], { z16.d, z17.d }, z0.d[1]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x04, 0xde, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w8, 1, vgx2], { z0.d, z1.d }, z14.d[1]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x04, 0xde, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w8, 1, vgx2], { z0.d, z1.d }, z14.d[1]"
+
+  -
+    input:
+      bytes: [ 0x40, 0x46, 0xd4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w10, 0, vgx2], { z18.d, z19.d }, z4.d[1]"
+
+  -
+    input:
+      bytes: [ 0x40, 0x46, 0xd4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w10, 0, vgx2], { z18.d, z19.d }, z4.d[1]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x01, 0xd2, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w8, 0, vgx2], { z12.d, z13.d }, z2.d[0]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x01, 0xd2, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w8, 0, vgx2], { z12.d, z13.d }, z2.d[0]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x40, 0xda, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w10, 1, vgx2], { z0.d, z1.d }, z10.d[0]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x40, 0xda, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w10, 1, vgx2], { z0.d, z1.d }, z10.d[0]"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x02, 0xde, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w8, 5, vgx2], { z22.d, z23.d }, z14.d[0]"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x02, 0xde, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w8, 5, vgx2], { z22.d, z23.d }, z14.d[0]"
+
+  -
+    input:
+      bytes: [ 0x02, 0x65, 0xd1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w11, 2, vgx2], { z8.d, z9.d }, z1.d[1]"
+
+  -
+    input:
+      bytes: [ 0x02, 0x65, 0xd1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w11, 2, vgx2], { z8.d, z9.d }, z1.d[1]"
+
+  -
+    input:
+      bytes: [ 0x87, 0x21, 0xdb, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w9, 7, vgx2], { z12.d, z13.d }, z11.d[0]"
+
+  -
+    input:
+      bytes: [ 0x87, 0x21, 0xdb, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w9, 7, vgx2], { z12.d, z13.d }, z11.d[0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x18, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w8, 0, vgx2], { z0.d, z1.d }, { z0.d, z1.d }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x18, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w8, 0, vgx2], { z0.d, z1.d }, { z0.d, z1.d }"
+
+  -
+    input:
+      bytes: [ 0x45, 0x59, 0xf4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w10, 5, vgx2], { z10.d, z11.d }, { z20.d, z21.d }"
+
+  -
+    input:
+      bytes: [ 0x45, 0x59, 0xf4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w10, 5, vgx2], { z10.d, z11.d }, { z20.d, z21.d }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x79, 0xe8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w11, 7, vgx2], { z12.d, z13.d }, { z8.d, z9.d }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x79, 0xe8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w11, 7, vgx2], { z12.d, z13.d }, { z8.d, z9.d }"
+
+  -
+    input:
+      bytes: [ 0xc7, 0x7b, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w11, 7, vgx2], { z30.d, z31.d }, { z30.d, z31.d }"
+
+  -
+    input:
+      bytes: [ 0xc7, 0x7b, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w11, 7, vgx2], { z30.d, z31.d }, { z30.d, z31.d }"
+
+  -
+    input:
+      bytes: [ 0x05, 0x1a, 0xf0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w8, 5, vgx2], { z16.d, z17.d }, { z16.d, z17.d }"
+
+  -
+    input:
+      bytes: [ 0x05, 0x1a, 0xf0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w8, 5, vgx2], { z16.d, z17.d }, { z16.d, z17.d }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x18, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w8, 1, vgx2], { z0.d, z1.d }, { z30.d, z31.d }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x18, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w8, 1, vgx2], { z0.d, z1.d }, { z30.d, z31.d }"
+
+  -
+    input:
+      bytes: [ 0x40, 0x5a, 0xf4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w10, 0, vgx2], { z18.d, z19.d }, { z20.d, z21.d }"
+
+  -
+    input:
+      bytes: [ 0x40, 0x5a, 0xf4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w10, 0, vgx2], { z18.d, z19.d }, { z20.d, z21.d }"
+
+  -
+    input:
+      bytes: [ 0x80, 0x19, 0xe2, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w8, 0, vgx2], { z12.d, z13.d }, { z2.d, z3.d }"
+
+  -
+    input:
+      bytes: [ 0x80, 0x19, 0xe2, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w8, 0, vgx2], { z12.d, z13.d }, { z2.d, z3.d }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x58, 0xfa, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w10, 1, vgx2], { z0.d, z1.d }, { z26.d, z27.d }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x58, 0xfa, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w10, 1, vgx2], { z0.d, z1.d }, { z26.d, z27.d }"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x1a, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w8, 5, vgx2], { z22.d, z23.d }, { z30.d, z31.d }"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x1a, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w8, 5, vgx2], { z22.d, z23.d }, { z30.d, z31.d }"
+
+  -
+    input:
+      bytes: [ 0x02, 0x79, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w11, 2, vgx2], { z8.d, z9.d }, { z0.d, z1.d }"
+
+  -
+    input:
+      bytes: [ 0x02, 0x79, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w11, 2, vgx2], { z8.d, z9.d }, { z0.d, z1.d }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x39, 0xea, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w9, 7, vgx2], { z12.d, z13.d }, { z10.d, z11.d }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x39, 0xea, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w9, 7, vgx2], { z12.d, z13.d }, { z10.d, z11.d }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x18, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w8, 0, vgx2], { z0.s, z1.s }, z0.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0x18, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w8, 0, vgx2], { z0.s, z1.s }, z0.s"
+
+  -
+    input:
+      bytes: [ 0x45, 0x59, 0x25, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w10, 5, vgx2], { z10.s, z11.s }, z5.s"
+
+  -
+    input:
+      bytes: [ 0x45, 0x59, 0x25, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w10, 5, vgx2], { z10.s, z11.s }, z5.s"
+
+  -
+    input:
+      bytes: [ 0xa7, 0x79, 0x28, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w11, 7, vgx2], { z13.s, z14.s }, z8.s"
+
+  -
+    input:
+      bytes: [ 0xa7, 0x79, 0x28, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w11, 7, vgx2], { z13.s, z14.s }, z8.s"
+
+  -
+    input:
+      bytes: [ 0xe7, 0x7b, 0x2f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w11, 7, vgx2], { z31.s, z0.s }, z15.s"
+
+  -
+    input:
+      bytes: [ 0xe7, 0x7b, 0x2f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w11, 7, vgx2], { z31.s, z0.s }, z15.s"
+
+  -
+    input:
+      bytes: [ 0x25, 0x1a, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w8, 5, vgx2], { z17.s, z18.s }, z0.s"
+
+  -
+    input:
+      bytes: [ 0x25, 0x1a, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w8, 5, vgx2], { z17.s, z18.s }, z0.s"
+
+  -
+    input:
+      bytes: [ 0x21, 0x18, 0x2e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w8, 1, vgx2], { z1.s, z2.s }, z14.s"
+
+  -
+    input:
+      bytes: [ 0x21, 0x18, 0x2e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w8, 1, vgx2], { z1.s, z2.s }, z14.s"
+
+  -
+    input:
+      bytes: [ 0x60, 0x5a, 0x24, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w10, 0, vgx2], { z19.s, z20.s }, z4.s"
+
+  -
+    input:
+      bytes: [ 0x60, 0x5a, 0x24, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w10, 0, vgx2], { z19.s, z20.s }, z4.s"
+
+  -
+    input:
+      bytes: [ 0x80, 0x19, 0x22, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w8, 0, vgx2], { z12.s, z13.s }, z2.s"
+
+  -
+    input:
+      bytes: [ 0x80, 0x19, 0x22, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w8, 0, vgx2], { z12.s, z13.s }, z2.s"
+
+  -
+    input:
+      bytes: [ 0x21, 0x58, 0x2a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w10, 1, vgx2], { z1.s, z2.s }, z10.s"
+
+  -
+    input:
+      bytes: [ 0x21, 0x58, 0x2a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w10, 1, vgx2], { z1.s, z2.s }, z10.s"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x1a, 0x2e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w8, 5, vgx2], { z22.s, z23.s }, z14.s"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x1a, 0x2e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w8, 5, vgx2], { z22.s, z23.s }, z14.s"
+
+  -
+    input:
+      bytes: [ 0x22, 0x79, 0x21, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w11, 2, vgx2], { z9.s, z10.s }, z1.s"
+
+  -
+    input:
+      bytes: [ 0x22, 0x79, 0x21, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w11, 2, vgx2], { z9.s, z10.s }, z1.s"
+
+  -
+    input:
+      bytes: [ 0x87, 0x39, 0x2b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w9, 7, vgx2], { z12.s, z13.s }, z11.s"
+
+  -
+    input:
+      bytes: [ 0x87, 0x39, 0x2b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w9, 7, vgx2], { z12.s, z13.s }, z11.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x50, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w8, 0, vgx2], { z0.s, z1.s }, z0.s[0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x50, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w8, 0, vgx2], { z0.s, z1.s }, z0.s[0]"
+
+  -
+    input:
+      bytes: [ 0x45, 0x45, 0x55, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w10, 5, vgx2], { z10.s, z11.s }, z5.s[1]"
+
+  -
+    input:
+      bytes: [ 0x45, 0x45, 0x55, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w10, 5, vgx2], { z10.s, z11.s }, z5.s[1]"
+
+  -
+    input:
+      bytes: [ 0x87, 0x6d, 0x58, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w11, 7, vgx2], { z12.s, z13.s }, z8.s[3]"
+
+  -
+    input:
+      bytes: [ 0x87, 0x6d, 0x58, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w11, 7, vgx2], { z12.s, z13.s }, z8.s[3]"
+
+  -
+    input:
+      bytes: [ 0xc7, 0x6f, 0x5f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w11, 7, vgx2], { z30.s, z31.s }, z15.s[3]"
+
+  -
+    input:
+      bytes: [ 0xc7, 0x6f, 0x5f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w11, 7, vgx2], { z30.s, z31.s }, z15.s[3]"
+
+  -
+    input:
+      bytes: [ 0x05, 0x0e, 0x50, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w8, 5, vgx2], { z16.s, z17.s }, z0.s[3]"
+
+  -
+    input:
+      bytes: [ 0x05, 0x0e, 0x50, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w8, 5, vgx2], { z16.s, z17.s }, z0.s[3]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x04, 0x5e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w8, 1, vgx2], { z0.s, z1.s }, z14.s[1]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x04, 0x5e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w8, 1, vgx2], { z0.s, z1.s }, z14.s[1]"
+
+  -
+    input:
+      bytes: [ 0x40, 0x46, 0x54, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w10, 0, vgx2], { z18.s, z19.s }, z4.s[1]"
+
+  -
+    input:
+      bytes: [ 0x40, 0x46, 0x54, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w10, 0, vgx2], { z18.s, z19.s }, z4.s[1]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x09, 0x52, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w8, 0, vgx2], { z12.s, z13.s }, z2.s[2]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x09, 0x52, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w8, 0, vgx2], { z12.s, z13.s }, z2.s[2]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x48, 0x5a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w10, 1, vgx2], { z0.s, z1.s }, z10.s[2]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x48, 0x5a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w10, 1, vgx2], { z0.s, z1.s }, z10.s[2]"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x0a, 0x5e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w8, 5, vgx2], { z22.s, z23.s }, z14.s[2]"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x0a, 0x5e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w8, 5, vgx2], { z22.s, z23.s }, z14.s[2]"
+
+  -
+    input:
+      bytes: [ 0x02, 0x65, 0x51, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w11, 2, vgx2], { z8.s, z9.s }, z1.s[1]"
+
+  -
+    input:
+      bytes: [ 0x02, 0x65, 0x51, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w11, 2, vgx2], { z8.s, z9.s }, z1.s[1]"
+
+  -
+    input:
+      bytes: [ 0x87, 0x29, 0x5b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w9, 7, vgx2], { z12.s, z13.s }, z11.s[2]"
+
+  -
+    input:
+      bytes: [ 0x87, 0x29, 0x5b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w9, 7, vgx2], { z12.s, z13.s }, z11.s[2]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x18, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w8, 0, vgx2], { z0.s, z1.s }, { z0.s, z1.s }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x18, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w8, 0, vgx2], { z0.s, z1.s }, { z0.s, z1.s }"
+
+  -
+    input:
+      bytes: [ 0x45, 0x59, 0xb4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w10, 5, vgx2], { z10.s, z11.s }, { z20.s, z21.s }"
+
+  -
+    input:
+      bytes: [ 0x45, 0x59, 0xb4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w10, 5, vgx2], { z10.s, z11.s }, { z20.s, z21.s }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x79, 0xa8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w11, 7, vgx2], { z12.s, z13.s }, { z8.s, z9.s }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x79, 0xa8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w11, 7, vgx2], { z12.s, z13.s }, { z8.s, z9.s }"
+
+  -
+    input:
+      bytes: [ 0xc7, 0x7b, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w11, 7, vgx2], { z30.s, z31.s }, { z30.s, z31.s }"
+
+  -
+    input:
+      bytes: [ 0xc7, 0x7b, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w11, 7, vgx2], { z30.s, z31.s }, { z30.s, z31.s }"
+
+  -
+    input:
+      bytes: [ 0x05, 0x1a, 0xb0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w8, 5, vgx2], { z16.s, z17.s }, { z16.s, z17.s }"
+
+  -
+    input:
+      bytes: [ 0x05, 0x1a, 0xb0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w8, 5, vgx2], { z16.s, z17.s }, { z16.s, z17.s }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x18, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w8, 1, vgx2], { z0.s, z1.s }, { z30.s, z31.s }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x18, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w8, 1, vgx2], { z0.s, z1.s }, { z30.s, z31.s }"
+
+  -
+    input:
+      bytes: [ 0x40, 0x5a, 0xb4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w10, 0, vgx2], { z18.s, z19.s }, { z20.s, z21.s }"
+
+  -
+    input:
+      bytes: [ 0x40, 0x5a, 0xb4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w10, 0, vgx2], { z18.s, z19.s }, { z20.s, z21.s }"
+
+  -
+    input:
+      bytes: [ 0x80, 0x19, 0xa2, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w8, 0, vgx2], { z12.s, z13.s }, { z2.s, z3.s }"
+
+  -
+    input:
+      bytes: [ 0x80, 0x19, 0xa2, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w8, 0, vgx2], { z12.s, z13.s }, { z2.s, z3.s }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x58, 0xba, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w10, 1, vgx2], { z0.s, z1.s }, { z26.s, z27.s }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x58, 0xba, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w10, 1, vgx2], { z0.s, z1.s }, { z26.s, z27.s }"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x1a, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w8, 5, vgx2], { z22.s, z23.s }, { z30.s, z31.s }"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x1a, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w8, 5, vgx2], { z22.s, z23.s }, { z30.s, z31.s }"
+
+  -
+    input:
+      bytes: [ 0x02, 0x79, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w11, 2, vgx2], { z8.s, z9.s }, { z0.s, z1.s }"
+
+  -
+    input:
+      bytes: [ 0x02, 0x79, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w11, 2, vgx2], { z8.s, z9.s }, { z0.s, z1.s }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x39, 0xaa, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w9, 7, vgx2], { z12.s, z13.s }, { z10.s, z11.s }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x39, 0xaa, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w9, 7, vgx2], { z12.s, z13.s }, { z10.s, z11.s }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x18, 0x70, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w8, 0, vgx4], { z0.d - z3.d }, z0.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x18, 0x70, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w8, 0, vgx4], { z0.d - z3.d }, z0.d"
+
+  -
+    input:
+      bytes: [ 0x45, 0x59, 0x75, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w10, 5, vgx4], { z10.d - z13.d }, z5.d"
+
+  -
+    input:
+      bytes: [ 0x45, 0x59, 0x75, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w10, 5, vgx4], { z10.d - z13.d }, z5.d"
+
+  -
+    input:
+      bytes: [ 0xa7, 0x79, 0x78, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w11, 7, vgx4], { z13.d - z16.d }, z8.d"
+
+  -
+    input:
+      bytes: [ 0xa7, 0x79, 0x78, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w11, 7, vgx4], { z13.d - z16.d }, z8.d"
+
+  -
+    input:
+      bytes: [ 0xe7, 0x7b, 0x7f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w11, 7, vgx4], { z31.d, z0.d, z1.d, z2.d }, z15.d"
+
+  -
+    input:
+      bytes: [ 0xe7, 0x7b, 0x7f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w11, 7, vgx4], { z31.d, z0.d, z1.d, z2.d }, z15.d"
+
+  -
+    input:
+      bytes: [ 0x25, 0x1a, 0x70, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w8, 5, vgx4], { z17.d - z20.d }, z0.d"
+
+  -
+    input:
+      bytes: [ 0x25, 0x1a, 0x70, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w8, 5, vgx4], { z17.d - z20.d }, z0.d"
+
+  -
+    input:
+      bytes: [ 0x21, 0x18, 0x7e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w8, 1, vgx4], { z1.d - z4.d }, z14.d"
+
+  -
+    input:
+      bytes: [ 0x21, 0x18, 0x7e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w8, 1, vgx4], { z1.d - z4.d }, z14.d"
+
+  -
+    input:
+      bytes: [ 0x60, 0x5a, 0x74, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w10, 0, vgx4], { z19.d - z22.d }, z4.d"
+
+  -
+    input:
+      bytes: [ 0x60, 0x5a, 0x74, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w10, 0, vgx4], { z19.d - z22.d }, z4.d"
+
+  -
+    input:
+      bytes: [ 0x80, 0x19, 0x72, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w8, 0, vgx4], { z12.d - z15.d }, z2.d"
+
+  -
+    input:
+      bytes: [ 0x80, 0x19, 0x72, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w8, 0, vgx4], { z12.d - z15.d }, z2.d"
+
+  -
+    input:
+      bytes: [ 0x21, 0x58, 0x7a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w10, 1, vgx4], { z1.d - z4.d }, z10.d"
+
+  -
+    input:
+      bytes: [ 0x21, 0x58, 0x7a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w10, 1, vgx4], { z1.d - z4.d }, z10.d"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x1a, 0x7e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w8, 5, vgx4], { z22.d - z25.d }, z14.d"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x1a, 0x7e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w8, 5, vgx4], { z22.d - z25.d }, z14.d"
+
+  -
+    input:
+      bytes: [ 0x22, 0x79, 0x71, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w11, 2, vgx4], { z9.d - z12.d }, z1.d"
+
+  -
+    input:
+      bytes: [ 0x22, 0x79, 0x71, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w11, 2, vgx4], { z9.d - z12.d }, z1.d"
+
+  -
+    input:
+      bytes: [ 0x87, 0x39, 0x7b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w9, 7, vgx4], { z12.d - z15.d }, z11.d"
+
+  -
+    input:
+      bytes: [ 0x87, 0x39, 0x7b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w9, 7, vgx4], { z12.d - z15.d }, z11.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xd0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w8, 0, vgx4], { z0.d - z3.d }, z0.d[0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xd0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w8, 0, vgx4], { z0.d - z3.d }, z0.d[0]"
+
+  -
+    input:
+      bytes: [ 0x05, 0xc5, 0xd5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w10, 5, vgx4], { z8.d - z11.d }, z5.d[1]"
+
+  -
+    input:
+      bytes: [ 0x05, 0xc5, 0xd5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w10, 5, vgx4], { z8.d - z11.d }, z5.d[1]"
+
+  -
+    input:
+      bytes: [ 0x87, 0xe5, 0xd8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w11, 7, vgx4], { z12.d - z15.d }, z8.d[1]"
+
+  -
+    input:
+      bytes: [ 0x87, 0xe5, 0xd8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w11, 7, vgx4], { z12.d - z15.d }, z8.d[1]"
+
+  -
+    input:
+      bytes: [ 0x87, 0xe7, 0xdf, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w11, 7, vgx4], { z28.d - z31.d }, z15.d[1]"
+
+  -
+    input:
+      bytes: [ 0x87, 0xe7, 0xdf, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w11, 7, vgx4], { z28.d - z31.d }, z15.d[1]"
+
+  -
+    input:
+      bytes: [ 0x05, 0x86, 0xd0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w8, 5, vgx4], { z16.d - z19.d }, z0.d[1]"
+
+  -
+    input:
+      bytes: [ 0x05, 0x86, 0xd0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w8, 5, vgx4], { z16.d - z19.d }, z0.d[1]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x84, 0xde, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w8, 1, vgx4], { z0.d - z3.d }, z14.d[1]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x84, 0xde, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w8, 1, vgx4], { z0.d - z3.d }, z14.d[1]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc6, 0xd4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w10, 0, vgx4], { z16.d - z19.d }, z4.d[1]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc6, 0xd4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w10, 0, vgx4], { z16.d - z19.d }, z4.d[1]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x81, 0xd2, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w8, 0, vgx4], { z12.d - z15.d }, z2.d[0]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x81, 0xd2, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w8, 0, vgx4], { z12.d - z15.d }, z2.d[0]"
+
+  -
+    input:
+      bytes: [ 0x01, 0xc0, 0xda, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w10, 1, vgx4], { z0.d - z3.d }, z10.d[0]"
+
+  -
+    input:
+      bytes: [ 0x01, 0xc0, 0xda, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w10, 1, vgx4], { z0.d - z3.d }, z10.d[0]"
+
+  -
+    input:
+      bytes: [ 0x85, 0x82, 0xde, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w8, 5, vgx4], { z20.d - z23.d }, z14.d[0]"
+
+  -
+    input:
+      bytes: [ 0x85, 0x82, 0xde, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w8, 5, vgx4], { z20.d - z23.d }, z14.d[0]"
+
+  -
+    input:
+      bytes: [ 0x02, 0xe5, 0xd1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w11, 2, vgx4], { z8.d - z11.d }, z1.d[1]"
+
+  -
+    input:
+      bytes: [ 0x02, 0xe5, 0xd1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w11, 2, vgx4], { z8.d - z11.d }, z1.d[1]"
+
+  -
+    input:
+      bytes: [ 0x87, 0xa1, 0xdb, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w9, 7, vgx4], { z12.d - z15.d }, z11.d[0]"
+
+  -
+    input:
+      bytes: [ 0x87, 0xa1, 0xdb, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w9, 7, vgx4], { z12.d - z15.d }, z11.d[0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x18, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w8, 0, vgx4], { z0.d - z3.d }, { z0.d - z3.d }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x18, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w8, 0, vgx4], { z0.d - z3.d }, { z0.d - z3.d }"
+
+  -
+    input:
+      bytes: [ 0x05, 0x59, 0xf5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w10, 5, vgx4], { z8.d - z11.d }, { z20.d - z23.d }"
+
+  -
+    input:
+      bytes: [ 0x05, 0x59, 0xf5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w10, 5, vgx4], { z8.d - z11.d }, { z20.d - z23.d }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x79, 0xe9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w11, 7, vgx4], { z12.d - z15.d }, { z8.d - z11.d }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x79, 0xe9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w11, 7, vgx4], { z12.d - z15.d }, { z8.d - z11.d }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x7b, 0xfd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w11, 7, vgx4], { z28.d - z31.d }, { z28.d - z31.d }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x7b, 0xfd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w11, 7, vgx4], { z28.d - z31.d }, { z28.d - z31.d }"
+
+  -
+    input:
+      bytes: [ 0x05, 0x1a, 0xf1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w8, 5, vgx4], { z16.d - z19.d }, { z16.d - z19.d }"
+
+  -
+    input:
+      bytes: [ 0x05, 0x1a, 0xf1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w8, 5, vgx4], { z16.d - z19.d }, { z16.d - z19.d }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x18, 0xfd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w8, 1, vgx4], { z0.d - z3.d }, { z28.d - z31.d }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x18, 0xfd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w8, 1, vgx4], { z0.d - z3.d }, { z28.d - z31.d }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x5a, 0xf5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w10, 0, vgx4], { z16.d - z19.d }, { z20.d - z23.d }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x5a, 0xf5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w10, 0, vgx4], { z16.d - z19.d }, { z20.d - z23.d }"
+
+  -
+    input:
+      bytes: [ 0x80, 0x19, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w8, 0, vgx4], { z12.d - z15.d }, { z0.d - z3.d }"
+
+  -
+    input:
+      bytes: [ 0x80, 0x19, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w8, 0, vgx4], { z12.d - z15.d }, { z0.d - z3.d }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x58, 0xf9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w10, 1, vgx4], { z0.d - z3.d }, { z24.d - z27.d }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x58, 0xf9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w10, 1, vgx4], { z0.d - z3.d }, { z24.d - z27.d }"
+
+  -
+    input:
+      bytes: [ 0x85, 0x1a, 0xfd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w8, 5, vgx4], { z20.d - z23.d }, { z28.d - z31.d }"
+
+  -
+    input:
+      bytes: [ 0x85, 0x1a, 0xfd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w8, 5, vgx4], { z20.d - z23.d }, { z28.d - z31.d }"
+
+  -
+    input:
+      bytes: [ 0x02, 0x79, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w11, 2, vgx4], { z8.d - z11.d }, { z0.d - z3.d }"
+
+  -
+    input:
+      bytes: [ 0x02, 0x79, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w11, 2, vgx4], { z8.d - z11.d }, { z0.d - z3.d }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x39, 0xe9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w9, 7, vgx4], { z12.d - z15.d }, { z8.d - z11.d }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x39, 0xe9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.d[w9, 7, vgx4], { z12.d - z15.d }, { z8.d - z11.d }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x18, 0x30, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w8, 0, vgx4], { z0.s - z3.s }, z0.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0x18, 0x30, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w8, 0, vgx4], { z0.s - z3.s }, z0.s"
+
+  -
+    input:
+      bytes: [ 0x45, 0x59, 0x35, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w10, 5, vgx4], { z10.s - z13.s }, z5.s"
+
+  -
+    input:
+      bytes: [ 0x45, 0x59, 0x35, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w10, 5, vgx4], { z10.s - z13.s }, z5.s"
+
+  -
+    input:
+      bytes: [ 0xa7, 0x79, 0x38, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w11, 7, vgx4], { z13.s - z16.s }, z8.s"
+
+  -
+    input:
+      bytes: [ 0xa7, 0x79, 0x38, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w11, 7, vgx4], { z13.s - z16.s }, z8.s"
+
+  -
+    input:
+      bytes: [ 0xe7, 0x7b, 0x3f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w11, 7, vgx4], { z31.s, z0.s, z1.s, z2.s }, z15.s"
+
+  -
+    input:
+      bytes: [ 0xe7, 0x7b, 0x3f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w11, 7, vgx4], { z31.s, z0.s, z1.s, z2.s }, z15.s"
+
+  -
+    input:
+      bytes: [ 0x25, 0x1a, 0x30, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w8, 5, vgx4], { z17.s - z20.s }, z0.s"
+
+  -
+    input:
+      bytes: [ 0x25, 0x1a, 0x30, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w8, 5, vgx4], { z17.s - z20.s }, z0.s"
+
+  -
+    input:
+      bytes: [ 0x21, 0x18, 0x3e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w8, 1, vgx4], { z1.s - z4.s }, z14.s"
+
+  -
+    input:
+      bytes: [ 0x21, 0x18, 0x3e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w8, 1, vgx4], { z1.s - z4.s }, z14.s"
+
+  -
+    input:
+      bytes: [ 0x60, 0x5a, 0x34, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w10, 0, vgx4], { z19.s - z22.s }, z4.s"
+
+  -
+    input:
+      bytes: [ 0x60, 0x5a, 0x34, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w10, 0, vgx4], { z19.s - z22.s }, z4.s"
+
+  -
+    input:
+      bytes: [ 0x80, 0x19, 0x32, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w8, 0, vgx4], { z12.s - z15.s }, z2.s"
+
+  -
+    input:
+      bytes: [ 0x80, 0x19, 0x32, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w8, 0, vgx4], { z12.s - z15.s }, z2.s"
+
+  -
+    input:
+      bytes: [ 0x21, 0x58, 0x3a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w10, 1, vgx4], { z1.s - z4.s }, z10.s"
+
+  -
+    input:
+      bytes: [ 0x21, 0x58, 0x3a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w10, 1, vgx4], { z1.s - z4.s }, z10.s"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x1a, 0x3e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w8, 5, vgx4], { z22.s - z25.s }, z14.s"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x1a, 0x3e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w8, 5, vgx4], { z22.s - z25.s }, z14.s"
+
+  -
+    input:
+      bytes: [ 0x22, 0x79, 0x31, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w11, 2, vgx4], { z9.s - z12.s }, z1.s"
+
+  -
+    input:
+      bytes: [ 0x22, 0x79, 0x31, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w11, 2, vgx4], { z9.s - z12.s }, z1.s"
+
+  -
+    input:
+      bytes: [ 0x87, 0x39, 0x3b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w9, 7, vgx4], { z12.s - z15.s }, z11.s"
+
+  -
+    input:
+      bytes: [ 0x87, 0x39, 0x3b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w9, 7, vgx4], { z12.s - z15.s }, z11.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x50, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w8, 0, vgx4], { z0.s - z3.s }, z0.s[0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x50, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w8, 0, vgx4], { z0.s - z3.s }, z0.s[0]"
+
+  -
+    input:
+      bytes: [ 0x05, 0xc5, 0x55, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w10, 5, vgx4], { z8.s - z11.s }, z5.s[1]"
+
+  -
+    input:
+      bytes: [ 0x05, 0xc5, 0x55, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w10, 5, vgx4], { z8.s - z11.s }, z5.s[1]"
+
+  -
+    input:
+      bytes: [ 0x87, 0xed, 0x58, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w11, 7, vgx4], { z12.s - z15.s }, z8.s[3]"
+
+  -
+    input:
+      bytes: [ 0x87, 0xed, 0x58, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w11, 7, vgx4], { z12.s - z15.s }, z8.s[3]"
+
+  -
+    input:
+      bytes: [ 0x87, 0xef, 0x5f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w11, 7, vgx4], { z28.s - z31.s }, z15.s[3]"
+
+  -
+    input:
+      bytes: [ 0x87, 0xef, 0x5f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w11, 7, vgx4], { z28.s - z31.s }, z15.s[3]"
+
+  -
+    input:
+      bytes: [ 0x05, 0x8e, 0x50, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w8, 5, vgx4], { z16.s - z19.s }, z0.s[3]"
+
+  -
+    input:
+      bytes: [ 0x05, 0x8e, 0x50, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w8, 5, vgx4], { z16.s - z19.s }, z0.s[3]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x84, 0x5e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w8, 1, vgx4], { z0.s - z3.s }, z14.s[1]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x84, 0x5e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w8, 1, vgx4], { z0.s - z3.s }, z14.s[1]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc6, 0x54, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w10, 0, vgx4], { z16.s - z19.s }, z4.s[1]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc6, 0x54, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w10, 0, vgx4], { z16.s - z19.s }, z4.s[1]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x89, 0x52, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w8, 0, vgx4], { z12.s - z15.s }, z2.s[2]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x89, 0x52, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w8, 0, vgx4], { z12.s - z15.s }, z2.s[2]"
+
+  -
+    input:
+      bytes: [ 0x01, 0xc8, 0x5a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w10, 1, vgx4], { z0.s - z3.s }, z10.s[2]"
+
+  -
+    input:
+      bytes: [ 0x01, 0xc8, 0x5a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w10, 1, vgx4], { z0.s - z3.s }, z10.s[2]"
+
+  -
+    input:
+      bytes: [ 0x85, 0x8a, 0x5e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w8, 5, vgx4], { z20.s - z23.s }, z14.s[2]"
+
+  -
+    input:
+      bytes: [ 0x85, 0x8a, 0x5e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w8, 5, vgx4], { z20.s - z23.s }, z14.s[2]"
+
+  -
+    input:
+      bytes: [ 0x02, 0xe5, 0x51, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w11, 2, vgx4], { z8.s - z11.s }, z1.s[1]"
+
+  -
+    input:
+      bytes: [ 0x02, 0xe5, 0x51, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w11, 2, vgx4], { z8.s - z11.s }, z1.s[1]"
+
+  -
+    input:
+      bytes: [ 0x87, 0xa9, 0x5b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w9, 7, vgx4], { z12.s - z15.s }, z11.s[2]"
+
+  -
+    input:
+      bytes: [ 0x87, 0xa9, 0x5b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w9, 7, vgx4], { z12.s - z15.s }, z11.s[2]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x18, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w8, 0, vgx4], { z0.s - z3.s }, { z0.s - z3.s }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x18, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w8, 0, vgx4], { z0.s - z3.s }, { z0.s - z3.s }"
+
+  -
+    input:
+      bytes: [ 0x05, 0x59, 0xb5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w10, 5, vgx4], { z8.s - z11.s }, { z20.s - z23.s }"
+
+  -
+    input:
+      bytes: [ 0x05, 0x59, 0xb5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w10, 5, vgx4], { z8.s - z11.s }, { z20.s - z23.s }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x79, 0xa9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w11, 7, vgx4], { z12.s - z15.s }, { z8.s - z11.s }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x79, 0xa9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w11, 7, vgx4], { z12.s - z15.s }, { z8.s - z11.s }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x7b, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w11, 7, vgx4], { z28.s - z31.s }, { z28.s - z31.s }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x7b, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w11, 7, vgx4], { z28.s - z31.s }, { z28.s - z31.s }"
+
+  -
+    input:
+      bytes: [ 0x05, 0x1a, 0xb1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w8, 5, vgx4], { z16.s - z19.s }, { z16.s - z19.s }"
+
+  -
+    input:
+      bytes: [ 0x05, 0x1a, 0xb1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w8, 5, vgx4], { z16.s - z19.s }, { z16.s - z19.s }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x18, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w8, 1, vgx4], { z0.s - z3.s }, { z28.s - z31.s }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x18, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w8, 1, vgx4], { z0.s - z3.s }, { z28.s - z31.s }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x5a, 0xb5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w10, 0, vgx4], { z16.s - z19.s }, { z20.s - z23.s }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x5a, 0xb5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w10, 0, vgx4], { z16.s - z19.s }, { z20.s - z23.s }"
+
+  -
+    input:
+      bytes: [ 0x80, 0x19, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w8, 0, vgx4], { z12.s - z15.s }, { z0.s - z3.s }"
+
+  -
+    input:
+      bytes: [ 0x80, 0x19, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w8, 0, vgx4], { z12.s - z15.s }, { z0.s - z3.s }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x58, 0xb9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w10, 1, vgx4], { z0.s - z3.s }, { z24.s - z27.s }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x58, 0xb9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w10, 1, vgx4], { z0.s - z3.s }, { z24.s - z27.s }"
+
+  -
+    input:
+      bytes: [ 0x85, 0x1a, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w8, 5, vgx4], { z20.s - z23.s }, { z28.s - z31.s }"
+
+  -
+    input:
+      bytes: [ 0x85, 0x1a, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w8, 5, vgx4], { z20.s - z23.s }, { z28.s - z31.s }"
+
+  -
+    input:
+      bytes: [ 0x02, 0x79, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w11, 2, vgx4], { z8.s - z11.s }, { z0.s - z3.s }"
+
+  -
+    input:
+      bytes: [ 0x02, 0x79, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w11, 2, vgx4], { z8.s - z11.s }, { z0.s - z3.s }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x39, 0xa9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w9, 7, vgx4], { z12.s - z15.s }, { z8.s - z11.s }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x39, 0xa9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.s[w9, 7, vgx4], { z12.s - z15.s }, { z8.s - z11.s }"
diff --git a/tests/MC/AArch64/SME2/fmlal.s.yaml b/tests/MC/AArch64/SME2/fmlal.s.yaml
new file mode 100644
index 000000000..0919a252f
--- /dev/null
+++ b/tests/MC/AArch64/SME2/fmlal.s.yaml
@@ -0,0 +1,1680 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x0c, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w8, 0:1], z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x45, 0x4d, 0x25, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w10, 10:11], z10.h, z5.h"
+
+  -
+    input:
+      bytes: [ 0xa7, 0x6d, 0x28, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w11, 14:15], z13.h, z8.h"
+
+  -
+    input:
+      bytes: [ 0xe7, 0x6f, 0x2f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w11, 14:15], z31.h, z15.h"
+
+  -
+    input:
+      bytes: [ 0x25, 0x0e, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w8, 10:11], z17.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x21, 0x0c, 0x2e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w8, 2:3], z1.h, z14.h"
+
+  -
+    input:
+      bytes: [ 0x60, 0x4e, 0x24, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w10, 0:1], z19.h, z4.h"
+
+  -
+    input:
+      bytes: [ 0x80, 0x0d, 0x22, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w8, 0:1], z12.h, z2.h"
+
+  -
+    input:
+      bytes: [ 0x21, 0x4c, 0x2a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w10, 2:3], z1.h, z10.h"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x0e, 0x2e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w8, 10:11], z22.h, z14.h"
+
+  -
+    input:
+      bytes: [ 0x22, 0x6d, 0x21, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w11, 4:5], z9.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0x87, 0x2d, 0x2b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w9, 14:15], z12.h, z11.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x10, 0x80, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w8, 0:1], z0.h, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x45, 0x55, 0x85, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w10, 10:11], z10.h, z5.h[1]"
+
+  -
+    input:
+      bytes: [ 0xa7, 0xfd, 0x88, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w11, 14:15], z13.h, z8.h[7]"
+
+  -
+    input:
+      bytes: [ 0xe7, 0xff, 0x8f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w11, 14:15], z31.h, z15.h[7]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x1e, 0x80, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w8, 10:11], z17.h, z0.h[3]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x94, 0x8e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w8, 2:3], z1.h, z14.h[5]"
+
+  -
+    input:
+      bytes: [ 0x60, 0x56, 0x84, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w10, 0:1], z19.h, z4.h[1]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x19, 0x82, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w8, 0:1], z12.h, z2.h[2]"
+
+  -
+    input:
+      bytes: [ 0x21, 0xd8, 0x8a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w10, 2:3], z1.h, z10.h[6]"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x1a, 0x8e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w8, 10:11], z22.h, z14.h[2]"
+
+  -
+    input:
+      bytes: [ 0x22, 0xf5, 0x81, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w11, 4:5], z9.h, z1.h[5]"
+
+  -
+    input:
+      bytes: [ 0x87, 0xb9, 0x8b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w9, 14:15], z12.h, z11.h[6]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x08, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w8, 0:1, vgx2], { z0.h, z1.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x08, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w8, 0:1, vgx2], { z0.h, z1.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x41, 0x49, 0x25, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w10, 2:3, vgx2], { z10.h, z11.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0x41, 0x49, 0x25, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w10, 2:3, vgx2], { z10.h, z11.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0xa3, 0x69, 0x28, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w11, 6:7, vgx2], { z13.h, z14.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0xa3, 0x69, 0x28, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w11, 6:7, vgx2], { z13.h, z14.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x6b, 0x2f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w11, 6:7, vgx2], { z31.h, z0.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x6b, 0x2f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w11, 6:7, vgx2], { z31.h, z0.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0x21, 0x0a, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w8, 2:3, vgx2], { z17.h, z18.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x21, 0x0a, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w8, 2:3, vgx2], { z17.h, z18.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x21, 0x08, 0x2e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w8, 2:3, vgx2], { z1.h, z2.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x21, 0x08, 0x2e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w8, 2:3, vgx2], { z1.h, z2.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x60, 0x4a, 0x24, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w10, 0:1, vgx2], { z19.h, z20.h }, z4.h"
+
+  -
+    input:
+      bytes: [ 0x60, 0x4a, 0x24, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w10, 0:1, vgx2], { z19.h, z20.h }, z4.h"
+
+  -
+    input:
+      bytes: [ 0x80, 0x09, 0x22, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w8, 0:1, vgx2], { z12.h, z13.h }, z2.h"
+
+  -
+    input:
+      bytes: [ 0x80, 0x09, 0x22, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w8, 0:1, vgx2], { z12.h, z13.h }, z2.h"
+
+  -
+    input:
+      bytes: [ 0x21, 0x48, 0x2a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w10, 2:3, vgx2], { z1.h, z2.h }, z10.h"
+
+  -
+    input:
+      bytes: [ 0x21, 0x48, 0x2a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w10, 2:3, vgx2], { z1.h, z2.h }, z10.h"
+
+  -
+    input:
+      bytes: [ 0xc1, 0x0a, 0x2e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w8, 2:3, vgx2], { z22.h, z23.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0xc1, 0x0a, 0x2e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w8, 2:3, vgx2], { z22.h, z23.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x22, 0x69, 0x21, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w11, 4:5, vgx2], { z9.h, z10.h }, z1.h"
+
+  -
+    input:
+      bytes: [ 0x22, 0x69, 0x21, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w11, 4:5, vgx2], { z9.h, z10.h }, z1.h"
+
+  -
+    input:
+      bytes: [ 0x83, 0x29, 0x2b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w9, 6:7, vgx2], { z12.h, z13.h }, z11.h"
+
+  -
+    input:
+      bytes: [ 0x83, 0x29, 0x2b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w9, 6:7, vgx2], { z12.h, z13.h }, z11.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x10, 0x90, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w8, 0:1, vgx2], { z0.h, z1.h }, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x10, 0x90, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w8, 0:1, vgx2], { z0.h, z1.h }, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x45, 0x55, 0x95, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w10, 2:3, vgx2], { z10.h, z11.h }, z5.h[3]"
+
+  -
+    input:
+      bytes: [ 0x45, 0x55, 0x95, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w10, 2:3, vgx2], { z10.h, z11.h }, z5.h[3]"
+
+  -
+    input:
+      bytes: [ 0x87, 0x7d, 0x98, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w11, 6:7, vgx2], { z12.h, z13.h }, z8.h[7]"
+
+  -
+    input:
+      bytes: [ 0x87, 0x7d, 0x98, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w11, 6:7, vgx2], { z12.h, z13.h }, z8.h[7]"
+
+  -
+    input:
+      bytes: [ 0xc7, 0x7f, 0x9f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w11, 6:7, vgx2], { z30.h, z31.h }, z15.h[7]"
+
+  -
+    input:
+      bytes: [ 0xc7, 0x7f, 0x9f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w11, 6:7, vgx2], { z30.h, z31.h }, z15.h[7]"
+
+  -
+    input:
+      bytes: [ 0x05, 0x1e, 0x90, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w8, 2:3, vgx2], { z16.h, z17.h }, z0.h[7]"
+
+  -
+    input:
+      bytes: [ 0x05, 0x1e, 0x90, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w8, 2:3, vgx2], { z16.h, z17.h }, z0.h[7]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x14, 0x9e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w8, 2:3, vgx2], { z0.h, z1.h }, z14.h[2]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x14, 0x9e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w8, 2:3, vgx2], { z0.h, z1.h }, z14.h[2]"
+
+  -
+    input:
+      bytes: [ 0x40, 0x56, 0x94, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w10, 0:1, vgx2], { z18.h, z19.h }, z4.h[2]"
+
+  -
+    input:
+      bytes: [ 0x40, 0x56, 0x94, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w10, 0:1, vgx2], { z18.h, z19.h }, z4.h[2]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x19, 0x92, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w8, 0:1, vgx2], { z12.h, z13.h }, z2.h[4]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x19, 0x92, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w8, 0:1, vgx2], { z12.h, z13.h }, z2.h[4]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x58, 0x9a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w10, 2:3, vgx2], { z0.h, z1.h }, z10.h[4]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x58, 0x9a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w10, 2:3, vgx2], { z0.h, z1.h }, z10.h[4]"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x1a, 0x9e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w8, 2:3, vgx2], { z22.h, z23.h }, z14.h[5]"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x1a, 0x9e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w8, 2:3, vgx2], { z22.h, z23.h }, z14.h[5]"
+
+  -
+    input:
+      bytes: [ 0x02, 0x75, 0x91, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w11, 4:5, vgx2], { z8.h, z9.h }, z1.h[2]"
+
+  -
+    input:
+      bytes: [ 0x02, 0x75, 0x91, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w11, 4:5, vgx2], { z8.h, z9.h }, z1.h[2]"
+
+  -
+    input:
+      bytes: [ 0x87, 0x39, 0x9b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w9, 6:7, vgx2], { z12.h, z13.h }, z11.h[5]"
+
+  -
+    input:
+      bytes: [ 0x87, 0x39, 0x9b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w9, 6:7, vgx2], { z12.h, z13.h }, z11.h[5]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x08, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w8, 0:1, vgx2], { z0.h, z1.h }, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x08, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w8, 0:1, vgx2], { z0.h, z1.h }, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x41, 0x49, 0xb4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w10, 2:3, vgx2], { z10.h, z11.h }, { z20.h, z21.h }"
+
+  -
+    input:
+      bytes: [ 0x41, 0x49, 0xb4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w10, 2:3, vgx2], { z10.h, z11.h }, { z20.h, z21.h }"
+
+  -
+    input:
+      bytes: [ 0x83, 0x69, 0xa8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w11, 6:7, vgx2], { z12.h, z13.h }, { z8.h, z9.h }"
+
+  -
+    input:
+      bytes: [ 0x83, 0x69, 0xa8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w11, 6:7, vgx2], { z12.h, z13.h }, { z8.h, z9.h }"
+
+  -
+    input:
+      bytes: [ 0xc3, 0x6b, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w11, 6:7, vgx2], { z30.h, z31.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0xc3, 0x6b, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w11, 6:7, vgx2], { z30.h, z31.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x0a, 0xb0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w8, 2:3, vgx2], { z16.h, z17.h }, { z16.h, z17.h }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x0a, 0xb0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w8, 2:3, vgx2], { z16.h, z17.h }, { z16.h, z17.h }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x08, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w8, 2:3, vgx2], { z0.h, z1.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x08, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w8, 2:3, vgx2], { z0.h, z1.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x40, 0x4a, 0xb4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w10, 0:1, vgx2], { z18.h, z19.h }, { z20.h, z21.h }"
+
+  -
+    input:
+      bytes: [ 0x40, 0x4a, 0xb4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w10, 0:1, vgx2], { z18.h, z19.h }, { z20.h, z21.h }"
+
+  -
+    input:
+      bytes: [ 0x80, 0x09, 0xa2, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w8, 0:1, vgx2], { z12.h, z13.h }, { z2.h, z3.h }"
+
+  -
+    input:
+      bytes: [ 0x80, 0x09, 0xa2, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w8, 0:1, vgx2], { z12.h, z13.h }, { z2.h, z3.h }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x48, 0xba, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w10, 2:3, vgx2], { z0.h, z1.h }, { z26.h, z27.h }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x48, 0xba, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w10, 2:3, vgx2], { z0.h, z1.h }, { z26.h, z27.h }"
+
+  -
+    input:
+      bytes: [ 0xc1, 0x0a, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w8, 2:3, vgx2], { z22.h, z23.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0xc1, 0x0a, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w8, 2:3, vgx2], { z22.h, z23.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x02, 0x69, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w11, 4:5, vgx2], { z8.h, z9.h }, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x02, 0x69, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w11, 4:5, vgx2], { z8.h, z9.h }, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x83, 0x29, 0xaa, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w9, 6:7, vgx2], { z12.h, z13.h }, { z10.h, z11.h }"
+
+  -
+    input:
+      bytes: [ 0x83, 0x29, 0xaa, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w9, 6:7, vgx2], { z12.h, z13.h }, { z10.h, z11.h }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x08, 0x30, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w8, 0:1, vgx4], { z0.h - z3.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x08, 0x30, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w8, 0:1, vgx4], { z0.h - z3.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x41, 0x49, 0x35, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w10, 2:3, vgx4], { z10.h - z13.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0x41, 0x49, 0x35, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w10, 2:3, vgx4], { z10.h - z13.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0xa3, 0x69, 0x38, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w11, 6:7, vgx4], { z13.h - z16.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0xa3, 0x69, 0x38, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w11, 6:7, vgx4], { z13.h - z16.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x6b, 0x3f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w11, 6:7, vgx4], { z31.h, z0.h, z1.h, z2.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x6b, 0x3f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w11, 6:7, vgx4], { z31.h, z0.h, z1.h, z2.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0x21, 0x0a, 0x30, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w8, 2:3, vgx4], { z17.h - z20.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x21, 0x0a, 0x30, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w8, 2:3, vgx4], { z17.h - z20.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x21, 0x08, 0x3e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w8, 2:3, vgx4], { z1.h - z4.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x21, 0x08, 0x3e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w8, 2:3, vgx4], { z1.h - z4.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x60, 0x4a, 0x34, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w10, 0:1, vgx4], { z19.h - z22.h }, z4.h"
+
+  -
+    input:
+      bytes: [ 0x60, 0x4a, 0x34, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w10, 0:1, vgx4], { z19.h - z22.h }, z4.h"
+
+  -
+    input:
+      bytes: [ 0x80, 0x09, 0x32, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w8, 0:1, vgx4], { z12.h - z15.h }, z2.h"
+
+  -
+    input:
+      bytes: [ 0x80, 0x09, 0x32, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w8, 0:1, vgx4], { z12.h - z15.h }, z2.h"
+
+  -
+    input:
+      bytes: [ 0x21, 0x48, 0x3a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w10, 2:3, vgx4], { z1.h - z4.h }, z10.h"
+
+  -
+    input:
+      bytes: [ 0x21, 0x48, 0x3a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w10, 2:3, vgx4], { z1.h - z4.h }, z10.h"
+
+  -
+    input:
+      bytes: [ 0xc1, 0x0a, 0x3e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w8, 2:3, vgx4], { z22.h - z25.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0xc1, 0x0a, 0x3e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w8, 2:3, vgx4], { z22.h - z25.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x22, 0x69, 0x31, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w11, 4:5, vgx4], { z9.h - z12.h }, z1.h"
+
+  -
+    input:
+      bytes: [ 0x22, 0x69, 0x31, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w11, 4:5, vgx4], { z9.h - z12.h }, z1.h"
+
+  -
+    input:
+      bytes: [ 0x83, 0x29, 0x3b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w9, 6:7, vgx4], { z12.h - z15.h }, z11.h"
+
+  -
+    input:
+      bytes: [ 0x83, 0x29, 0x3b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w9, 6:7, vgx4], { z12.h - z15.h }, z11.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x90, 0x90, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w8, 0:1, vgx4], { z0.h - z3.h }, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x90, 0x90, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w8, 0:1, vgx4], { z0.h - z3.h }, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x05, 0xd5, 0x95, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w10, 2:3, vgx4], { z8.h - z11.h }, z5.h[3]"
+
+  -
+    input:
+      bytes: [ 0x05, 0xd5, 0x95, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w10, 2:3, vgx4], { z8.h - z11.h }, z5.h[3]"
+
+  -
+    input:
+      bytes: [ 0x87, 0xfd, 0x98, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w11, 6:7, vgx4], { z12.h - z15.h }, z8.h[7]"
+
+  -
+    input:
+      bytes: [ 0x87, 0xfd, 0x98, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w11, 6:7, vgx4], { z12.h - z15.h }, z8.h[7]"
+
+  -
+    input:
+      bytes: [ 0x87, 0xff, 0x9f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w11, 6:7, vgx4], { z28.h - z31.h }, z15.h[7]"
+
+  -
+    input:
+      bytes: [ 0x87, 0xff, 0x9f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w11, 6:7, vgx4], { z28.h - z31.h }, z15.h[7]"
+
+  -
+    input:
+      bytes: [ 0x05, 0x9e, 0x90, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w8, 2:3, vgx4], { z16.h - z19.h }, z0.h[7]"
+
+  -
+    input:
+      bytes: [ 0x05, 0x9e, 0x90, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w8, 2:3, vgx4], { z16.h - z19.h }, z0.h[7]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x94, 0x9e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w8, 2:3, vgx4], { z0.h - z3.h }, z14.h[2]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x94, 0x9e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w8, 2:3, vgx4], { z0.h - z3.h }, z14.h[2]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd6, 0x94, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w10, 0:1, vgx4], { z16.h - z19.h }, z4.h[2]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd6, 0x94, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w10, 0:1, vgx4], { z16.h - z19.h }, z4.h[2]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x99, 0x92, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w8, 0:1, vgx4], { z12.h - z15.h }, z2.h[4]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x99, 0x92, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w8, 0:1, vgx4], { z12.h - z15.h }, z2.h[4]"
+
+  -
+    input:
+      bytes: [ 0x01, 0xd8, 0x9a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w10, 2:3, vgx4], { z0.h - z3.h }, z10.h[4]"
+
+  -
+    input:
+      bytes: [ 0x01, 0xd8, 0x9a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w10, 2:3, vgx4], { z0.h - z3.h }, z10.h[4]"
+
+  -
+    input:
+      bytes: [ 0x85, 0x9a, 0x9e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w8, 2:3, vgx4], { z20.h - z23.h }, z14.h[5]"
+
+  -
+    input:
+      bytes: [ 0x85, 0x9a, 0x9e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w8, 2:3, vgx4], { z20.h - z23.h }, z14.h[5]"
+
+  -
+    input:
+      bytes: [ 0x02, 0xf5, 0x91, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w11, 4:5, vgx4], { z8.h - z11.h }, z1.h[2]"
+
+  -
+    input:
+      bytes: [ 0x02, 0xf5, 0x91, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w11, 4:5, vgx4], { z8.h - z11.h }, z1.h[2]"
+
+  -
+    input:
+      bytes: [ 0x87, 0xb9, 0x9b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w9, 6:7, vgx4], { z12.h - z15.h }, z11.h[5]"
+
+  -
+    input:
+      bytes: [ 0x87, 0xb9, 0x9b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w9, 6:7, vgx4], { z12.h - z15.h }, z11.h[5]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x08, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w8, 0:1, vgx4], { z0.h - z3.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x08, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w8, 0:1, vgx4], { z0.h - z3.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x49, 0xb5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w10, 2:3, vgx4], { z8.h - z11.h }, { z20.h - z23.h }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x49, 0xb5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w10, 2:3, vgx4], { z8.h - z11.h }, { z20.h - z23.h }"
+
+  -
+    input:
+      bytes: [ 0x83, 0x69, 0xa9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w11, 6:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }"
+
+  -
+    input:
+      bytes: [ 0x83, 0x69, 0xa9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w11, 6:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }"
+
+  -
+    input:
+      bytes: [ 0x83, 0x6b, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w11, 6:7, vgx4], { z28.h - z31.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x83, 0x6b, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w11, 6:7, vgx4], { z28.h - z31.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x0a, 0xb1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w8, 2:3, vgx4], { z16.h - z19.h }, { z16.h - z19.h }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x0a, 0xb1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w8, 2:3, vgx4], { z16.h - z19.h }, { z16.h - z19.h }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x08, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w8, 2:3, vgx4], { z0.h - z3.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x08, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w8, 2:3, vgx4], { z0.h - z3.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x4a, 0xb5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w10, 0:1, vgx4], { z16.h - z19.h }, { z20.h - z23.h }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x4a, 0xb5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w10, 0:1, vgx4], { z16.h - z19.h }, { z20.h - z23.h }"
+
+  -
+    input:
+      bytes: [ 0x80, 0x09, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w8, 0:1, vgx4], { z12.h - z15.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x80, 0x09, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w8, 0:1, vgx4], { z12.h - z15.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x48, 0xb9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w10, 2:3, vgx4], { z0.h - z3.h }, { z24.h - z27.h }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x48, 0xb9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w10, 2:3, vgx4], { z0.h - z3.h }, { z24.h - z27.h }"
+
+  -
+    input:
+      bytes: [ 0x81, 0x0a, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w8, 2:3, vgx4], { z20.h - z23.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x81, 0x0a, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w8, 2:3, vgx4], { z20.h - z23.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x02, 0x69, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w11, 4:5, vgx4], { z8.h - z11.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x02, 0x69, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w11, 4:5, vgx4], { z8.h - z11.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x83, 0x29, 0xa9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w9, 6:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }"
+
+  -
+    input:
+      bytes: [ 0x83, 0x29, 0xa9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal za.s[w9, 6:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }"
diff --git a/tests/MC/AArch64/SME2/fmls.s.yaml b/tests/MC/AArch64/SME2/fmls.s.yaml
new file mode 100644
index 000000000..05764aed6
--- /dev/null
+++ b/tests/MC/AArch64/SME2/fmls.s.yaml
@@ -0,0 +1,2880 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x08, 0x18, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w8, 0, vgx2], { z0.d, z1.d }, z0.d"
+
+  -
+    input:
+      bytes: [ 0x08, 0x18, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w8, 0, vgx2], { z0.d, z1.d }, z0.d"
+
+  -
+    input:
+      bytes: [ 0x4d, 0x59, 0x65, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w10, 5, vgx2], { z10.d, z11.d }, z5.d"
+
+  -
+    input:
+      bytes: [ 0x4d, 0x59, 0x65, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w10, 5, vgx2], { z10.d, z11.d }, z5.d"
+
+  -
+    input:
+      bytes: [ 0xaf, 0x79, 0x68, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w11, 7, vgx2], { z13.d, z14.d }, z8.d"
+
+  -
+    input:
+      bytes: [ 0xaf, 0x79, 0x68, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w11, 7, vgx2], { z13.d, z14.d }, z8.d"
+
+  -
+    input:
+      bytes: [ 0xef, 0x7b, 0x6f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w11, 7, vgx2], { z31.d, z0.d }, z15.d"
+
+  -
+    input:
+      bytes: [ 0xef, 0x7b, 0x6f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w11, 7, vgx2], { z31.d, z0.d }, z15.d"
+
+  -
+    input:
+      bytes: [ 0x2d, 0x1a, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w8, 5, vgx2], { z17.d, z18.d }, z0.d"
+
+  -
+    input:
+      bytes: [ 0x2d, 0x1a, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w8, 5, vgx2], { z17.d, z18.d }, z0.d"
+
+  -
+    input:
+      bytes: [ 0x29, 0x18, 0x6e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w8, 1, vgx2], { z1.d, z2.d }, z14.d"
+
+  -
+    input:
+      bytes: [ 0x29, 0x18, 0x6e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w8, 1, vgx2], { z1.d, z2.d }, z14.d"
+
+  -
+    input:
+      bytes: [ 0x68, 0x5a, 0x64, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w10, 0, vgx2], { z19.d, z20.d }, z4.d"
+
+  -
+    input:
+      bytes: [ 0x68, 0x5a, 0x64, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w10, 0, vgx2], { z19.d, z20.d }, z4.d"
+
+  -
+    input:
+      bytes: [ 0x88, 0x19, 0x62, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w8, 0, vgx2], { z12.d, z13.d }, z2.d"
+
+  -
+    input:
+      bytes: [ 0x88, 0x19, 0x62, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w8, 0, vgx2], { z12.d, z13.d }, z2.d"
+
+  -
+    input:
+      bytes: [ 0x29, 0x58, 0x6a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w10, 1, vgx2], { z1.d, z2.d }, z10.d"
+
+  -
+    input:
+      bytes: [ 0x29, 0x58, 0x6a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w10, 1, vgx2], { z1.d, z2.d }, z10.d"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x1a, 0x6e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w8, 5, vgx2], { z22.d, z23.d }, z14.d"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x1a, 0x6e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w8, 5, vgx2], { z22.d, z23.d }, z14.d"
+
+  -
+    input:
+      bytes: [ 0x2a, 0x79, 0x61, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w11, 2, vgx2], { z9.d, z10.d }, z1.d"
+
+  -
+    input:
+      bytes: [ 0x2a, 0x79, 0x61, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w11, 2, vgx2], { z9.d, z10.d }, z1.d"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x39, 0x6b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w9, 7, vgx2], { z12.d, z13.d }, z11.d"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x39, 0x6b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w9, 7, vgx2], { z12.d, z13.d }, z11.d"
+
+  -
+    input:
+      bytes: [ 0x10, 0x00, 0xd0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w8, 0, vgx2], { z0.d, z1.d }, z0.d[0]"
+
+  -
+    input:
+      bytes: [ 0x10, 0x00, 0xd0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w8, 0, vgx2], { z0.d, z1.d }, z0.d[0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x45, 0xd5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w10, 5, vgx2], { z10.d, z11.d }, z5.d[1]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x45, 0xd5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w10, 5, vgx2], { z10.d, z11.d }, z5.d[1]"
+
+  -
+    input:
+      bytes: [ 0x97, 0x65, 0xd8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w11, 7, vgx2], { z12.d, z13.d }, z8.d[1]"
+
+  -
+    input:
+      bytes: [ 0x97, 0x65, 0xd8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w11, 7, vgx2], { z12.d, z13.d }, z8.d[1]"
+
+  -
+    input:
+      bytes: [ 0xd7, 0x67, 0xdf, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w11, 7, vgx2], { z30.d, z31.d }, z15.d[1]"
+
+  -
+    input:
+      bytes: [ 0xd7, 0x67, 0xdf, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w11, 7, vgx2], { z30.d, z31.d }, z15.d[1]"
+
+  -
+    input:
+      bytes: [ 0x15, 0x06, 0xd0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w8, 5, vgx2], { z16.d, z17.d }, z0.d[1]"
+
+  -
+    input:
+      bytes: [ 0x15, 0x06, 0xd0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w8, 5, vgx2], { z16.d, z17.d }, z0.d[1]"
+
+  -
+    input:
+      bytes: [ 0x11, 0x04, 0xde, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w8, 1, vgx2], { z0.d, z1.d }, z14.d[1]"
+
+  -
+    input:
+      bytes: [ 0x11, 0x04, 0xde, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w8, 1, vgx2], { z0.d, z1.d }, z14.d[1]"
+
+  -
+    input:
+      bytes: [ 0x50, 0x46, 0xd4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w10, 0, vgx2], { z18.d, z19.d }, z4.d[1]"
+
+  -
+    input:
+      bytes: [ 0x50, 0x46, 0xd4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w10, 0, vgx2], { z18.d, z19.d }, z4.d[1]"
+
+  -
+    input:
+      bytes: [ 0x90, 0x01, 0xd2, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w8, 0, vgx2], { z12.d, z13.d }, z2.d[0]"
+
+  -
+    input:
+      bytes: [ 0x90, 0x01, 0xd2, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w8, 0, vgx2], { z12.d, z13.d }, z2.d[0]"
+
+  -
+    input:
+      bytes: [ 0x11, 0x40, 0xda, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w10, 1, vgx2], { z0.d, z1.d }, z10.d[0]"
+
+  -
+    input:
+      bytes: [ 0x11, 0x40, 0xda, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w10, 1, vgx2], { z0.d, z1.d }, z10.d[0]"
+
+  -
+    input:
+      bytes: [ 0xd5, 0x02, 0xde, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w8, 5, vgx2], { z22.d, z23.d }, z14.d[0]"
+
+  -
+    input:
+      bytes: [ 0xd5, 0x02, 0xde, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w8, 5, vgx2], { z22.d, z23.d }, z14.d[0]"
+
+  -
+    input:
+      bytes: [ 0x12, 0x65, 0xd1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w11, 2, vgx2], { z8.d, z9.d }, z1.d[1]"
+
+  -
+    input:
+      bytes: [ 0x12, 0x65, 0xd1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w11, 2, vgx2], { z8.d, z9.d }, z1.d[1]"
+
+  -
+    input:
+      bytes: [ 0x97, 0x21, 0xdb, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w9, 7, vgx2], { z12.d, z13.d }, z11.d[0]"
+
+  -
+    input:
+      bytes: [ 0x97, 0x21, 0xdb, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w9, 7, vgx2], { z12.d, z13.d }, z11.d[0]"
+
+  -
+    input:
+      bytes: [ 0x08, 0x18, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w8, 0, vgx2], { z0.d, z1.d }, { z0.d, z1.d }"
+
+  -
+    input:
+      bytes: [ 0x08, 0x18, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w8, 0, vgx2], { z0.d, z1.d }, { z0.d, z1.d }"
+
+  -
+    input:
+      bytes: [ 0x4d, 0x59, 0xf4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w10, 5, vgx2], { z10.d, z11.d }, { z20.d, z21.d }"
+
+  -
+    input:
+      bytes: [ 0x4d, 0x59, 0xf4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w10, 5, vgx2], { z10.d, z11.d }, { z20.d, z21.d }"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x79, 0xe8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w11, 7, vgx2], { z12.d, z13.d }, { z8.d, z9.d }"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x79, 0xe8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w11, 7, vgx2], { z12.d, z13.d }, { z8.d, z9.d }"
+
+  -
+    input:
+      bytes: [ 0xcf, 0x7b, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w11, 7, vgx2], { z30.d, z31.d }, { z30.d, z31.d }"
+
+  -
+    input:
+      bytes: [ 0xcf, 0x7b, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w11, 7, vgx2], { z30.d, z31.d }, { z30.d, z31.d }"
+
+  -
+    input:
+      bytes: [ 0x0d, 0x1a, 0xf0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w8, 5, vgx2], { z16.d, z17.d }, { z16.d, z17.d }"
+
+  -
+    input:
+      bytes: [ 0x0d, 0x1a, 0xf0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w8, 5, vgx2], { z16.d, z17.d }, { z16.d, z17.d }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x18, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w8, 1, vgx2], { z0.d, z1.d }, { z30.d, z31.d }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x18, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w8, 1, vgx2], { z0.d, z1.d }, { z30.d, z31.d }"
+
+  -
+    input:
+      bytes: [ 0x48, 0x5a, 0xf4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w10, 0, vgx2], { z18.d, z19.d }, { z20.d, z21.d }"
+
+  -
+    input:
+      bytes: [ 0x48, 0x5a, 0xf4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w10, 0, vgx2], { z18.d, z19.d }, { z20.d, z21.d }"
+
+  -
+    input:
+      bytes: [ 0x88, 0x19, 0xe2, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w8, 0, vgx2], { z12.d, z13.d }, { z2.d, z3.d }"
+
+  -
+    input:
+      bytes: [ 0x88, 0x19, 0xe2, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w8, 0, vgx2], { z12.d, z13.d }, { z2.d, z3.d }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x58, 0xfa, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w10, 1, vgx2], { z0.d, z1.d }, { z26.d, z27.d }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x58, 0xfa, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w10, 1, vgx2], { z0.d, z1.d }, { z26.d, z27.d }"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x1a, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w8, 5, vgx2], { z22.d, z23.d }, { z30.d, z31.d }"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x1a, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w8, 5, vgx2], { z22.d, z23.d }, { z30.d, z31.d }"
+
+  -
+    input:
+      bytes: [ 0x0a, 0x79, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w11, 2, vgx2], { z8.d, z9.d }, { z0.d, z1.d }"
+
+  -
+    input:
+      bytes: [ 0x0a, 0x79, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w11, 2, vgx2], { z8.d, z9.d }, { z0.d, z1.d }"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x39, 0xea, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w9, 7, vgx2], { z12.d, z13.d }, { z10.d, z11.d }"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x39, 0xea, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w9, 7, vgx2], { z12.d, z13.d }, { z10.d, z11.d }"
+
+  -
+    input:
+      bytes: [ 0x08, 0x18, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w8, 0, vgx2], { z0.s, z1.s }, z0.s"
+
+  -
+    input:
+      bytes: [ 0x08, 0x18, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w8, 0, vgx2], { z0.s, z1.s }, z0.s"
+
+  -
+    input:
+      bytes: [ 0x4d, 0x59, 0x25, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w10, 5, vgx2], { z10.s, z11.s }, z5.s"
+
+  -
+    input:
+      bytes: [ 0x4d, 0x59, 0x25, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w10, 5, vgx2], { z10.s, z11.s }, z5.s"
+
+  -
+    input:
+      bytes: [ 0xaf, 0x79, 0x28, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w11, 7, vgx2], { z13.s, z14.s }, z8.s"
+
+  -
+    input:
+      bytes: [ 0xaf, 0x79, 0x28, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w11, 7, vgx2], { z13.s, z14.s }, z8.s"
+
+  -
+    input:
+      bytes: [ 0xef, 0x7b, 0x2f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w11, 7, vgx2], { z31.s, z0.s }, z15.s"
+
+  -
+    input:
+      bytes: [ 0xef, 0x7b, 0x2f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w11, 7, vgx2], { z31.s, z0.s }, z15.s"
+
+  -
+    input:
+      bytes: [ 0x2d, 0x1a, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w8, 5, vgx2], { z17.s, z18.s }, z0.s"
+
+  -
+    input:
+      bytes: [ 0x2d, 0x1a, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w8, 5, vgx2], { z17.s, z18.s }, z0.s"
+
+  -
+    input:
+      bytes: [ 0x29, 0x18, 0x2e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w8, 1, vgx2], { z1.s, z2.s }, z14.s"
+
+  -
+    input:
+      bytes: [ 0x29, 0x18, 0x2e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w8, 1, vgx2], { z1.s, z2.s }, z14.s"
+
+  -
+    input:
+      bytes: [ 0x68, 0x5a, 0x24, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w10, 0, vgx2], { z19.s, z20.s }, z4.s"
+
+  -
+    input:
+      bytes: [ 0x68, 0x5a, 0x24, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w10, 0, vgx2], { z19.s, z20.s }, z4.s"
+
+  -
+    input:
+      bytes: [ 0x88, 0x19, 0x22, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w8, 0, vgx2], { z12.s, z13.s }, z2.s"
+
+  -
+    input:
+      bytes: [ 0x88, 0x19, 0x22, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w8, 0, vgx2], { z12.s, z13.s }, z2.s"
+
+  -
+    input:
+      bytes: [ 0x29, 0x58, 0x2a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w10, 1, vgx2], { z1.s, z2.s }, z10.s"
+
+  -
+    input:
+      bytes: [ 0x29, 0x58, 0x2a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w10, 1, vgx2], { z1.s, z2.s }, z10.s"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x1a, 0x2e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w8, 5, vgx2], { z22.s, z23.s }, z14.s"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x1a, 0x2e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w8, 5, vgx2], { z22.s, z23.s }, z14.s"
+
+  -
+    input:
+      bytes: [ 0x2a, 0x79, 0x21, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w11, 2, vgx2], { z9.s, z10.s }, z1.s"
+
+  -
+    input:
+      bytes: [ 0x2a, 0x79, 0x21, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w11, 2, vgx2], { z9.s, z10.s }, z1.s"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x39, 0x2b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w9, 7, vgx2], { z12.s, z13.s }, z11.s"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x39, 0x2b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w9, 7, vgx2], { z12.s, z13.s }, z11.s"
+
+  -
+    input:
+      bytes: [ 0x10, 0x00, 0x50, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w8, 0, vgx2], { z0.s, z1.s }, z0.s[0]"
+
+  -
+    input:
+      bytes: [ 0x10, 0x00, 0x50, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w8, 0, vgx2], { z0.s, z1.s }, z0.s[0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x45, 0x55, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w10, 5, vgx2], { z10.s, z11.s }, z5.s[1]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x45, 0x55, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w10, 5, vgx2], { z10.s, z11.s }, z5.s[1]"
+
+  -
+    input:
+      bytes: [ 0x97, 0x6d, 0x58, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w11, 7, vgx2], { z12.s, z13.s }, z8.s[3]"
+
+  -
+    input:
+      bytes: [ 0x97, 0x6d, 0x58, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w11, 7, vgx2], { z12.s, z13.s }, z8.s[3]"
+
+  -
+    input:
+      bytes: [ 0xd7, 0x6f, 0x5f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w11, 7, vgx2], { z30.s, z31.s }, z15.s[3]"
+
+  -
+    input:
+      bytes: [ 0xd7, 0x6f, 0x5f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w11, 7, vgx2], { z30.s, z31.s }, z15.s[3]"
+
+  -
+    input:
+      bytes: [ 0x15, 0x0e, 0x50, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w8, 5, vgx2], { z16.s, z17.s }, z0.s[3]"
+
+  -
+    input:
+      bytes: [ 0x15, 0x0e, 0x50, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w8, 5, vgx2], { z16.s, z17.s }, z0.s[3]"
+
+  -
+    input:
+      bytes: [ 0x11, 0x04, 0x5e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w8, 1, vgx2], { z0.s, z1.s }, z14.s[1]"
+
+  -
+    input:
+      bytes: [ 0x11, 0x04, 0x5e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w8, 1, vgx2], { z0.s, z1.s }, z14.s[1]"
+
+  -
+    input:
+      bytes: [ 0x50, 0x46, 0x54, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w10, 0, vgx2], { z18.s, z19.s }, z4.s[1]"
+
+  -
+    input:
+      bytes: [ 0x50, 0x46, 0x54, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w10, 0, vgx2], { z18.s, z19.s }, z4.s[1]"
+
+  -
+    input:
+      bytes: [ 0x90, 0x09, 0x52, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w8, 0, vgx2], { z12.s, z13.s }, z2.s[2]"
+
+  -
+    input:
+      bytes: [ 0x90, 0x09, 0x52, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w8, 0, vgx2], { z12.s, z13.s }, z2.s[2]"
+
+  -
+    input:
+      bytes: [ 0x11, 0x48, 0x5a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w10, 1, vgx2], { z0.s, z1.s }, z10.s[2]"
+
+  -
+    input:
+      bytes: [ 0x11, 0x48, 0x5a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w10, 1, vgx2], { z0.s, z1.s }, z10.s[2]"
+
+  -
+    input:
+      bytes: [ 0xd5, 0x0a, 0x5e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w8, 5, vgx2], { z22.s, z23.s }, z14.s[2]"
+
+  -
+    input:
+      bytes: [ 0xd5, 0x0a, 0x5e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w8, 5, vgx2], { z22.s, z23.s }, z14.s[2]"
+
+  -
+    input:
+      bytes: [ 0x12, 0x65, 0x51, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w11, 2, vgx2], { z8.s, z9.s }, z1.s[1]"
+
+  -
+    input:
+      bytes: [ 0x12, 0x65, 0x51, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w11, 2, vgx2], { z8.s, z9.s }, z1.s[1]"
+
+  -
+    input:
+      bytes: [ 0x97, 0x29, 0x5b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w9, 7, vgx2], { z12.s, z13.s }, z11.s[2]"
+
+  -
+    input:
+      bytes: [ 0x97, 0x29, 0x5b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w9, 7, vgx2], { z12.s, z13.s }, z11.s[2]"
+
+  -
+    input:
+      bytes: [ 0x08, 0x18, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w8, 0, vgx2], { z0.s, z1.s }, { z0.s, z1.s }"
+
+  -
+    input:
+      bytes: [ 0x08, 0x18, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w8, 0, vgx2], { z0.s, z1.s }, { z0.s, z1.s }"
+
+  -
+    input:
+      bytes: [ 0x4d, 0x59, 0xb4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w10, 5, vgx2], { z10.s, z11.s }, { z20.s, z21.s }"
+
+  -
+    input:
+      bytes: [ 0x4d, 0x59, 0xb4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w10, 5, vgx2], { z10.s, z11.s }, { z20.s, z21.s }"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x79, 0xa8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w11, 7, vgx2], { z12.s, z13.s }, { z8.s, z9.s }"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x79, 0xa8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w11, 7, vgx2], { z12.s, z13.s }, { z8.s, z9.s }"
+
+  -
+    input:
+      bytes: [ 0xcf, 0x7b, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w11, 7, vgx2], { z30.s, z31.s }, { z30.s, z31.s }"
+
+  -
+    input:
+      bytes: [ 0xcf, 0x7b, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w11, 7, vgx2], { z30.s, z31.s }, { z30.s, z31.s }"
+
+  -
+    input:
+      bytes: [ 0x0d, 0x1a, 0xb0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w8, 5, vgx2], { z16.s, z17.s }, { z16.s, z17.s }"
+
+  -
+    input:
+      bytes: [ 0x0d, 0x1a, 0xb0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w8, 5, vgx2], { z16.s, z17.s }, { z16.s, z17.s }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x18, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w8, 1, vgx2], { z0.s, z1.s }, { z30.s, z31.s }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x18, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w8, 1, vgx2], { z0.s, z1.s }, { z30.s, z31.s }"
+
+  -
+    input:
+      bytes: [ 0x48, 0x5a, 0xb4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w10, 0, vgx2], { z18.s, z19.s }, { z20.s, z21.s }"
+
+  -
+    input:
+      bytes: [ 0x48, 0x5a, 0xb4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w10, 0, vgx2], { z18.s, z19.s }, { z20.s, z21.s }"
+
+  -
+    input:
+      bytes: [ 0x88, 0x19, 0xa2, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w8, 0, vgx2], { z12.s, z13.s }, { z2.s, z3.s }"
+
+  -
+    input:
+      bytes: [ 0x88, 0x19, 0xa2, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w8, 0, vgx2], { z12.s, z13.s }, { z2.s, z3.s }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x58, 0xba, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w10, 1, vgx2], { z0.s, z1.s }, { z26.s, z27.s }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x58, 0xba, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w10, 1, vgx2], { z0.s, z1.s }, { z26.s, z27.s }"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x1a, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w8, 5, vgx2], { z22.s, z23.s }, { z30.s, z31.s }"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x1a, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w8, 5, vgx2], { z22.s, z23.s }, { z30.s, z31.s }"
+
+  -
+    input:
+      bytes: [ 0x0a, 0x79, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w11, 2, vgx2], { z8.s, z9.s }, { z0.s, z1.s }"
+
+  -
+    input:
+      bytes: [ 0x0a, 0x79, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w11, 2, vgx2], { z8.s, z9.s }, { z0.s, z1.s }"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x39, 0xaa, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w9, 7, vgx2], { z12.s, z13.s }, { z10.s, z11.s }"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x39, 0xaa, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w9, 7, vgx2], { z12.s, z13.s }, { z10.s, z11.s }"
+
+  -
+    input:
+      bytes: [ 0x08, 0x18, 0x70, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w8, 0, vgx4], { z0.d - z3.d }, z0.d"
+
+  -
+    input:
+      bytes: [ 0x08, 0x18, 0x70, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w8, 0, vgx4], { z0.d - z3.d }, z0.d"
+
+  -
+    input:
+      bytes: [ 0x4d, 0x59, 0x75, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w10, 5, vgx4], { z10.d - z13.d }, z5.d"
+
+  -
+    input:
+      bytes: [ 0x4d, 0x59, 0x75, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w10, 5, vgx4], { z10.d - z13.d }, z5.d"
+
+  -
+    input:
+      bytes: [ 0xaf, 0x79, 0x78, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w11, 7, vgx4], { z13.d - z16.d }, z8.d"
+
+  -
+    input:
+      bytes: [ 0xaf, 0x79, 0x78, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w11, 7, vgx4], { z13.d - z16.d }, z8.d"
+
+  -
+    input:
+      bytes: [ 0xef, 0x7b, 0x7f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w11, 7, vgx4], { z31.d, z0.d, z1.d, z2.d }, z15.d"
+
+  -
+    input:
+      bytes: [ 0xef, 0x7b, 0x7f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w11, 7, vgx4], { z31.d, z0.d, z1.d, z2.d }, z15.d"
+
+  -
+    input:
+      bytes: [ 0x2d, 0x1a, 0x70, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w8, 5, vgx4], { z17.d - z20.d }, z0.d"
+
+  -
+    input:
+      bytes: [ 0x2d, 0x1a, 0x70, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w8, 5, vgx4], { z17.d - z20.d }, z0.d"
+
+  -
+    input:
+      bytes: [ 0x29, 0x18, 0x7e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w8, 1, vgx4], { z1.d - z4.d }, z14.d"
+
+  -
+    input:
+      bytes: [ 0x29, 0x18, 0x7e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w8, 1, vgx4], { z1.d - z4.d }, z14.d"
+
+  -
+    input:
+      bytes: [ 0x68, 0x5a, 0x74, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w10, 0, vgx4], { z19.d - z22.d }, z4.d"
+
+  -
+    input:
+      bytes: [ 0x68, 0x5a, 0x74, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w10, 0, vgx4], { z19.d - z22.d }, z4.d"
+
+  -
+    input:
+      bytes: [ 0x88, 0x19, 0x72, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w8, 0, vgx4], { z12.d - z15.d }, z2.d"
+
+  -
+    input:
+      bytes: [ 0x88, 0x19, 0x72, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w8, 0, vgx4], { z12.d - z15.d }, z2.d"
+
+  -
+    input:
+      bytes: [ 0x29, 0x58, 0x7a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w10, 1, vgx4], { z1.d - z4.d }, z10.d"
+
+  -
+    input:
+      bytes: [ 0x29, 0x58, 0x7a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w10, 1, vgx4], { z1.d - z4.d }, z10.d"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x1a, 0x7e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w8, 5, vgx4], { z22.d - z25.d }, z14.d"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x1a, 0x7e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w8, 5, vgx4], { z22.d - z25.d }, z14.d"
+
+  -
+    input:
+      bytes: [ 0x2a, 0x79, 0x71, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w11, 2, vgx4], { z9.d - z12.d }, z1.d"
+
+  -
+    input:
+      bytes: [ 0x2a, 0x79, 0x71, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w11, 2, vgx4], { z9.d - z12.d }, z1.d"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x39, 0x7b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w9, 7, vgx4], { z12.d - z15.d }, z11.d"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x39, 0x7b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w9, 7, vgx4], { z12.d - z15.d }, z11.d"
+
+  -
+    input:
+      bytes: [ 0x10, 0x80, 0xd0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w8, 0, vgx4], { z0.d - z3.d }, z0.d[0]"
+
+  -
+    input:
+      bytes: [ 0x10, 0x80, 0xd0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w8, 0, vgx4], { z0.d - z3.d }, z0.d[0]"
+
+  -
+    input:
+      bytes: [ 0x15, 0xc5, 0xd5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w10, 5, vgx4], { z8.d - z11.d }, z5.d[1]"
+
+  -
+    input:
+      bytes: [ 0x15, 0xc5, 0xd5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w10, 5, vgx4], { z8.d - z11.d }, z5.d[1]"
+
+  -
+    input:
+      bytes: [ 0x97, 0xe5, 0xd8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w11, 7, vgx4], { z12.d - z15.d }, z8.d[1]"
+
+  -
+    input:
+      bytes: [ 0x97, 0xe5, 0xd8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w11, 7, vgx4], { z12.d - z15.d }, z8.d[1]"
+
+  -
+    input:
+      bytes: [ 0x97, 0xe7, 0xdf, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w11, 7, vgx4], { z28.d - z31.d }, z15.d[1]"
+
+  -
+    input:
+      bytes: [ 0x97, 0xe7, 0xdf, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w11, 7, vgx4], { z28.d - z31.d }, z15.d[1]"
+
+  -
+    input:
+      bytes: [ 0x15, 0x86, 0xd0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w8, 5, vgx4], { z16.d - z19.d }, z0.d[1]"
+
+  -
+    input:
+      bytes: [ 0x15, 0x86, 0xd0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w8, 5, vgx4], { z16.d - z19.d }, z0.d[1]"
+
+  -
+    input:
+      bytes: [ 0x11, 0x84, 0xde, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w8, 1, vgx4], { z0.d - z3.d }, z14.d[1]"
+
+  -
+    input:
+      bytes: [ 0x11, 0x84, 0xde, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w8, 1, vgx4], { z0.d - z3.d }, z14.d[1]"
+
+  -
+    input:
+      bytes: [ 0x10, 0xc6, 0xd4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w10, 0, vgx4], { z16.d - z19.d }, z4.d[1]"
+
+  -
+    input:
+      bytes: [ 0x10, 0xc6, 0xd4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w10, 0, vgx4], { z16.d - z19.d }, z4.d[1]"
+
+  -
+    input:
+      bytes: [ 0x90, 0x81, 0xd2, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w8, 0, vgx4], { z12.d - z15.d }, z2.d[0]"
+
+  -
+    input:
+      bytes: [ 0x90, 0x81, 0xd2, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w8, 0, vgx4], { z12.d - z15.d }, z2.d[0]"
+
+  -
+    input:
+      bytes: [ 0x11, 0xc0, 0xda, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w10, 1, vgx4], { z0.d - z3.d }, z10.d[0]"
+
+  -
+    input:
+      bytes: [ 0x11, 0xc0, 0xda, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w10, 1, vgx4], { z0.d - z3.d }, z10.d[0]"
+
+  -
+    input:
+      bytes: [ 0x95, 0x82, 0xde, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w8, 5, vgx4], { z20.d - z23.d }, z14.d[0]"
+
+  -
+    input:
+      bytes: [ 0x95, 0x82, 0xde, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w8, 5, vgx4], { z20.d - z23.d }, z14.d[0]"
+
+  -
+    input:
+      bytes: [ 0x12, 0xe5, 0xd1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w11, 2, vgx4], { z8.d - z11.d }, z1.d[1]"
+
+  -
+    input:
+      bytes: [ 0x12, 0xe5, 0xd1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w11, 2, vgx4], { z8.d - z11.d }, z1.d[1]"
+
+  -
+    input:
+      bytes: [ 0x97, 0xa1, 0xdb, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w9, 7, vgx4], { z12.d - z15.d }, z11.d[0]"
+
+  -
+    input:
+      bytes: [ 0x97, 0xa1, 0xdb, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w9, 7, vgx4], { z12.d - z15.d }, z11.d[0]"
+
+  -
+    input:
+      bytes: [ 0x08, 0x18, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w8, 0, vgx4], { z0.d - z3.d }, { z0.d - z3.d }"
+
+  -
+    input:
+      bytes: [ 0x08, 0x18, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w8, 0, vgx4], { z0.d - z3.d }, { z0.d - z3.d }"
+
+  -
+    input:
+      bytes: [ 0x0d, 0x59, 0xf5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w10, 5, vgx4], { z8.d - z11.d }, { z20.d - z23.d }"
+
+  -
+    input:
+      bytes: [ 0x0d, 0x59, 0xf5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w10, 5, vgx4], { z8.d - z11.d }, { z20.d - z23.d }"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x79, 0xe9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w11, 7, vgx4], { z12.d - z15.d }, { z8.d - z11.d }"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x79, 0xe9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w11, 7, vgx4], { z12.d - z15.d }, { z8.d - z11.d }"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x7b, 0xfd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w11, 7, vgx4], { z28.d - z31.d }, { z28.d - z31.d }"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x7b, 0xfd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w11, 7, vgx4], { z28.d - z31.d }, { z28.d - z31.d }"
+
+  -
+    input:
+      bytes: [ 0x0d, 0x1a, 0xf1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w8, 5, vgx4], { z16.d - z19.d }, { z16.d - z19.d }"
+
+  -
+    input:
+      bytes: [ 0x0d, 0x1a, 0xf1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w8, 5, vgx4], { z16.d - z19.d }, { z16.d - z19.d }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x18, 0xfd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w8, 1, vgx4], { z0.d - z3.d }, { z28.d - z31.d }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x18, 0xfd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w8, 1, vgx4], { z0.d - z3.d }, { z28.d - z31.d }"
+
+  -
+    input:
+      bytes: [ 0x08, 0x5a, 0xf5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w10, 0, vgx4], { z16.d - z19.d }, { z20.d - z23.d }"
+
+  -
+    input:
+      bytes: [ 0x08, 0x5a, 0xf5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w10, 0, vgx4], { z16.d - z19.d }, { z20.d - z23.d }"
+
+  -
+    input:
+      bytes: [ 0x88, 0x19, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w8, 0, vgx4], { z12.d - z15.d }, { z0.d - z3.d }"
+
+  -
+    input:
+      bytes: [ 0x88, 0x19, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w8, 0, vgx4], { z12.d - z15.d }, { z0.d - z3.d }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x58, 0xf9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w10, 1, vgx4], { z0.d - z3.d }, { z24.d - z27.d }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x58, 0xf9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w10, 1, vgx4], { z0.d - z3.d }, { z24.d - z27.d }"
+
+  -
+    input:
+      bytes: [ 0x8d, 0x1a, 0xfd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w8, 5, vgx4], { z20.d - z23.d }, { z28.d - z31.d }"
+
+  -
+    input:
+      bytes: [ 0x8d, 0x1a, 0xfd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w8, 5, vgx4], { z20.d - z23.d }, { z28.d - z31.d }"
+
+  -
+    input:
+      bytes: [ 0x0a, 0x79, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w11, 2, vgx4], { z8.d - z11.d }, { z0.d - z3.d }"
+
+  -
+    input:
+      bytes: [ 0x0a, 0x79, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w11, 2, vgx4], { z8.d - z11.d }, { z0.d - z3.d }"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x39, 0xe9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w9, 7, vgx4], { z12.d - z15.d }, { z8.d - z11.d }"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x39, 0xe9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.d[w9, 7, vgx4], { z12.d - z15.d }, { z8.d - z11.d }"
+
+  -
+    input:
+      bytes: [ 0x08, 0x18, 0x30, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w8, 0, vgx4], { z0.s - z3.s }, z0.s"
+
+  -
+    input:
+      bytes: [ 0x08, 0x18, 0x30, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w8, 0, vgx4], { z0.s - z3.s }, z0.s"
+
+  -
+    input:
+      bytes: [ 0x4d, 0x59, 0x35, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w10, 5, vgx4], { z10.s - z13.s }, z5.s"
+
+  -
+    input:
+      bytes: [ 0x4d, 0x59, 0x35, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w10, 5, vgx4], { z10.s - z13.s }, z5.s"
+
+  -
+    input:
+      bytes: [ 0xaf, 0x79, 0x38, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w11, 7, vgx4], { z13.s - z16.s }, z8.s"
+
+  -
+    input:
+      bytes: [ 0xaf, 0x79, 0x38, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w11, 7, vgx4], { z13.s - z16.s }, z8.s"
+
+  -
+    input:
+      bytes: [ 0xef, 0x7b, 0x3f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w11, 7, vgx4], { z31.s, z0.s, z1.s, z2.s }, z15.s"
+
+  -
+    input:
+      bytes: [ 0xef, 0x7b, 0x3f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w11, 7, vgx4], { z31.s, z0.s, z1.s, z2.s }, z15.s"
+
+  -
+    input:
+      bytes: [ 0x2d, 0x1a, 0x30, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w8, 5, vgx4], { z17.s - z20.s }, z0.s"
+
+  -
+    input:
+      bytes: [ 0x2d, 0x1a, 0x30, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w8, 5, vgx4], { z17.s - z20.s }, z0.s"
+
+  -
+    input:
+      bytes: [ 0x29, 0x18, 0x3e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w8, 1, vgx4], { z1.s - z4.s }, z14.s"
+
+  -
+    input:
+      bytes: [ 0x29, 0x18, 0x3e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w8, 1, vgx4], { z1.s - z4.s }, z14.s"
+
+  -
+    input:
+      bytes: [ 0x68, 0x5a, 0x34, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w10, 0, vgx4], { z19.s - z22.s }, z4.s"
+
+  -
+    input:
+      bytes: [ 0x68, 0x5a, 0x34, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w10, 0, vgx4], { z19.s - z22.s }, z4.s"
+
+  -
+    input:
+      bytes: [ 0x88, 0x19, 0x32, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w8, 0, vgx4], { z12.s - z15.s }, z2.s"
+
+  -
+    input:
+      bytes: [ 0x88, 0x19, 0x32, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w8, 0, vgx4], { z12.s - z15.s }, z2.s"
+
+  -
+    input:
+      bytes: [ 0x29, 0x58, 0x3a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w10, 1, vgx4], { z1.s - z4.s }, z10.s"
+
+  -
+    input:
+      bytes: [ 0x29, 0x58, 0x3a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w10, 1, vgx4], { z1.s - z4.s }, z10.s"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x1a, 0x3e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w8, 5, vgx4], { z22.s - z25.s }, z14.s"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x1a, 0x3e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w8, 5, vgx4], { z22.s - z25.s }, z14.s"
+
+  -
+    input:
+      bytes: [ 0x2a, 0x79, 0x31, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w11, 2, vgx4], { z9.s - z12.s }, z1.s"
+
+  -
+    input:
+      bytes: [ 0x2a, 0x79, 0x31, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w11, 2, vgx4], { z9.s - z12.s }, z1.s"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x39, 0x3b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w9, 7, vgx4], { z12.s - z15.s }, z11.s"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x39, 0x3b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w9, 7, vgx4], { z12.s - z15.s }, z11.s"
+
+  -
+    input:
+      bytes: [ 0x10, 0x80, 0x50, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w8, 0, vgx4], { z0.s - z3.s }, z0.s[0]"
+
+  -
+    input:
+      bytes: [ 0x10, 0x80, 0x50, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w8, 0, vgx4], { z0.s - z3.s }, z0.s[0]"
+
+  -
+    input:
+      bytes: [ 0x15, 0xc5, 0x55, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w10, 5, vgx4], { z8.s - z11.s }, z5.s[1]"
+
+  -
+    input:
+      bytes: [ 0x15, 0xc5, 0x55, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w10, 5, vgx4], { z8.s - z11.s }, z5.s[1]"
+
+  -
+    input:
+      bytes: [ 0x97, 0xed, 0x58, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w11, 7, vgx4], { z12.s - z15.s }, z8.s[3]"
+
+  -
+    input:
+      bytes: [ 0x97, 0xed, 0x58, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w11, 7, vgx4], { z12.s - z15.s }, z8.s[3]"
+
+  -
+    input:
+      bytes: [ 0x97, 0xef, 0x5f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w11, 7, vgx4], { z28.s - z31.s }, z15.s[3]"
+
+  -
+    input:
+      bytes: [ 0x97, 0xef, 0x5f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w11, 7, vgx4], { z28.s - z31.s }, z15.s[3]"
+
+  -
+    input:
+      bytes: [ 0x15, 0x8e, 0x50, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w8, 5, vgx4], { z16.s - z19.s }, z0.s[3]"
+
+  -
+    input:
+      bytes: [ 0x15, 0x8e, 0x50, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w8, 5, vgx4], { z16.s - z19.s }, z0.s[3]"
+
+  -
+    input:
+      bytes: [ 0x11, 0x84, 0x5e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w8, 1, vgx4], { z0.s - z3.s }, z14.s[1]"
+
+  -
+    input:
+      bytes: [ 0x11, 0x84, 0x5e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w8, 1, vgx4], { z0.s - z3.s }, z14.s[1]"
+
+  -
+    input:
+      bytes: [ 0x10, 0xc6, 0x54, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w10, 0, vgx4], { z16.s - z19.s }, z4.s[1]"
+
+  -
+    input:
+      bytes: [ 0x10, 0xc6, 0x54, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w10, 0, vgx4], { z16.s - z19.s }, z4.s[1]"
+
+  -
+    input:
+      bytes: [ 0x90, 0x89, 0x52, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w8, 0, vgx4], { z12.s - z15.s }, z2.s[2]"
+
+  -
+    input:
+      bytes: [ 0x90, 0x89, 0x52, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w8, 0, vgx4], { z12.s - z15.s }, z2.s[2]"
+
+  -
+    input:
+      bytes: [ 0x11, 0xc8, 0x5a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w10, 1, vgx4], { z0.s - z3.s }, z10.s[2]"
+
+  -
+    input:
+      bytes: [ 0x11, 0xc8, 0x5a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w10, 1, vgx4], { z0.s - z3.s }, z10.s[2]"
+
+  -
+    input:
+      bytes: [ 0x95, 0x8a, 0x5e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w8, 5, vgx4], { z20.s - z23.s }, z14.s[2]"
+
+  -
+    input:
+      bytes: [ 0x95, 0x8a, 0x5e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w8, 5, vgx4], { z20.s - z23.s }, z14.s[2]"
+
+  -
+    input:
+      bytes: [ 0x12, 0xe5, 0x51, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w11, 2, vgx4], { z8.s - z11.s }, z1.s[1]"
+
+  -
+    input:
+      bytes: [ 0x12, 0xe5, 0x51, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w11, 2, vgx4], { z8.s - z11.s }, z1.s[1]"
+
+  -
+    input:
+      bytes: [ 0x97, 0xa9, 0x5b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w9, 7, vgx4], { z12.s - z15.s }, z11.s[2]"
+
+  -
+    input:
+      bytes: [ 0x97, 0xa9, 0x5b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w9, 7, vgx4], { z12.s - z15.s }, z11.s[2]"
+
+  -
+    input:
+      bytes: [ 0x08, 0x18, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w8, 0, vgx4], { z0.s - z3.s }, { z0.s - z3.s }"
+
+  -
+    input:
+      bytes: [ 0x08, 0x18, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w8, 0, vgx4], { z0.s - z3.s }, { z0.s - z3.s }"
+
+  -
+    input:
+      bytes: [ 0x0d, 0x59, 0xb5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w10, 5, vgx4], { z8.s - z11.s }, { z20.s - z23.s }"
+
+  -
+    input:
+      bytes: [ 0x0d, 0x59, 0xb5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w10, 5, vgx4], { z8.s - z11.s }, { z20.s - z23.s }"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x79, 0xa9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w11, 7, vgx4], { z12.s - z15.s }, { z8.s - z11.s }"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x79, 0xa9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w11, 7, vgx4], { z12.s - z15.s }, { z8.s - z11.s }"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x7b, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w11, 7, vgx4], { z28.s - z31.s }, { z28.s - z31.s }"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x7b, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w11, 7, vgx4], { z28.s - z31.s }, { z28.s - z31.s }"
+
+  -
+    input:
+      bytes: [ 0x0d, 0x1a, 0xb1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w8, 5, vgx4], { z16.s - z19.s }, { z16.s - z19.s }"
+
+  -
+    input:
+      bytes: [ 0x0d, 0x1a, 0xb1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w8, 5, vgx4], { z16.s - z19.s }, { z16.s - z19.s }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x18, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w8, 1, vgx4], { z0.s - z3.s }, { z28.s - z31.s }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x18, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w8, 1, vgx4], { z0.s - z3.s }, { z28.s - z31.s }"
+
+  -
+    input:
+      bytes: [ 0x08, 0x5a, 0xb5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w10, 0, vgx4], { z16.s - z19.s }, { z20.s - z23.s }"
+
+  -
+    input:
+      bytes: [ 0x08, 0x5a, 0xb5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w10, 0, vgx4], { z16.s - z19.s }, { z20.s - z23.s }"
+
+  -
+    input:
+      bytes: [ 0x88, 0x19, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w8, 0, vgx4], { z12.s - z15.s }, { z0.s - z3.s }"
+
+  -
+    input:
+      bytes: [ 0x88, 0x19, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w8, 0, vgx4], { z12.s - z15.s }, { z0.s - z3.s }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x58, 0xb9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w10, 1, vgx4], { z0.s - z3.s }, { z24.s - z27.s }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x58, 0xb9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w10, 1, vgx4], { z0.s - z3.s }, { z24.s - z27.s }"
+
+  -
+    input:
+      bytes: [ 0x8d, 0x1a, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w8, 5, vgx4], { z20.s - z23.s }, { z28.s - z31.s }"
+
+  -
+    input:
+      bytes: [ 0x8d, 0x1a, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w8, 5, vgx4], { z20.s - z23.s }, { z28.s - z31.s }"
+
+  -
+    input:
+      bytes: [ 0x0a, 0x79, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w11, 2, vgx4], { z8.s - z11.s }, { z0.s - z3.s }"
+
+  -
+    input:
+      bytes: [ 0x0a, 0x79, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w11, 2, vgx4], { z8.s - z11.s }, { z0.s - z3.s }"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x39, 0xa9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w9, 7, vgx4], { z12.s - z15.s }, { z8.s - z11.s }"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x39, 0xa9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.s[w9, 7, vgx4], { z12.s - z15.s }, { z8.s - z11.s }"
diff --git a/tests/MC/AArch64/SME2/fmlsl.s.yaml b/tests/MC/AArch64/SME2/fmlsl.s.yaml
new file mode 100644
index 000000000..7281de675
--- /dev/null
+++ b/tests/MC/AArch64/SME2/fmlsl.s.yaml
@@ -0,0 +1,1680 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x08, 0x0c, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w8, 0:1], z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x4d, 0x4d, 0x25, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w10, 10:11], z10.h, z5.h"
+
+  -
+    input:
+      bytes: [ 0xaf, 0x6d, 0x28, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w11, 14:15], z13.h, z8.h"
+
+  -
+    input:
+      bytes: [ 0xef, 0x6f, 0x2f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w11, 14:15], z31.h, z15.h"
+
+  -
+    input:
+      bytes: [ 0x2d, 0x0e, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w8, 10:11], z17.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x29, 0x0c, 0x2e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w8, 2:3], z1.h, z14.h"
+
+  -
+    input:
+      bytes: [ 0x68, 0x4e, 0x24, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w10, 0:1], z19.h, z4.h"
+
+  -
+    input:
+      bytes: [ 0x88, 0x0d, 0x22, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w8, 0:1], z12.h, z2.h"
+
+  -
+    input:
+      bytes: [ 0x29, 0x4c, 0x2a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w10, 2:3], z1.h, z10.h"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x0e, 0x2e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w8, 10:11], z22.h, z14.h"
+
+  -
+    input:
+      bytes: [ 0x2a, 0x6d, 0x21, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w11, 4:5], z9.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x2d, 0x2b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w9, 14:15], z12.h, z11.h"
+
+  -
+    input:
+      bytes: [ 0x08, 0x10, 0x80, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w8, 0:1], z0.h, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x4d, 0x55, 0x85, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w10, 10:11], z10.h, z5.h[1]"
+
+  -
+    input:
+      bytes: [ 0xaf, 0xfd, 0x88, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w11, 14:15], z13.h, z8.h[7]"
+
+  -
+    input:
+      bytes: [ 0xef, 0xff, 0x8f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w11, 14:15], z31.h, z15.h[7]"
+
+  -
+    input:
+      bytes: [ 0x2d, 0x1e, 0x80, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w8, 10:11], z17.h, z0.h[3]"
+
+  -
+    input:
+      bytes: [ 0x29, 0x94, 0x8e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w8, 2:3], z1.h, z14.h[5]"
+
+  -
+    input:
+      bytes: [ 0x68, 0x56, 0x84, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w10, 0:1], z19.h, z4.h[1]"
+
+  -
+    input:
+      bytes: [ 0x88, 0x19, 0x82, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w8, 0:1], z12.h, z2.h[2]"
+
+  -
+    input:
+      bytes: [ 0x29, 0xd8, 0x8a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w10, 2:3], z1.h, z10.h[6]"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x1a, 0x8e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w8, 10:11], z22.h, z14.h[2]"
+
+  -
+    input:
+      bytes: [ 0x2a, 0xf5, 0x81, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w11, 4:5], z9.h, z1.h[5]"
+
+  -
+    input:
+      bytes: [ 0x8f, 0xb9, 0x8b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w9, 14:15], z12.h, z11.h[6]"
+
+  -
+    input:
+      bytes: [ 0x08, 0x08, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w8, 0:1, vgx2], { z0.h, z1.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x08, 0x08, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w8, 0:1, vgx2], { z0.h, z1.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x49, 0x49, 0x25, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w10, 2:3, vgx2], { z10.h, z11.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0x49, 0x49, 0x25, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w10, 2:3, vgx2], { z10.h, z11.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0xab, 0x69, 0x28, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w11, 6:7, vgx2], { z13.h, z14.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0xab, 0x69, 0x28, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w11, 6:7, vgx2], { z13.h, z14.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0xeb, 0x6b, 0x2f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w11, 6:7, vgx2], { z31.h, z0.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0xeb, 0x6b, 0x2f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w11, 6:7, vgx2], { z31.h, z0.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0x29, 0x0a, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w8, 2:3, vgx2], { z17.h, z18.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x29, 0x0a, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w8, 2:3, vgx2], { z17.h, z18.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x29, 0x08, 0x2e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w8, 2:3, vgx2], { z1.h, z2.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x29, 0x08, 0x2e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w8, 2:3, vgx2], { z1.h, z2.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x68, 0x4a, 0x24, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w10, 0:1, vgx2], { z19.h, z20.h }, z4.h"
+
+  -
+    input:
+      bytes: [ 0x68, 0x4a, 0x24, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w10, 0:1, vgx2], { z19.h, z20.h }, z4.h"
+
+  -
+    input:
+      bytes: [ 0x88, 0x09, 0x22, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w8, 0:1, vgx2], { z12.h, z13.h }, z2.h"
+
+  -
+    input:
+      bytes: [ 0x88, 0x09, 0x22, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w8, 0:1, vgx2], { z12.h, z13.h }, z2.h"
+
+  -
+    input:
+      bytes: [ 0x29, 0x48, 0x2a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w10, 2:3, vgx2], { z1.h, z2.h }, z10.h"
+
+  -
+    input:
+      bytes: [ 0x29, 0x48, 0x2a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w10, 2:3, vgx2], { z1.h, z2.h }, z10.h"
+
+  -
+    input:
+      bytes: [ 0xc9, 0x0a, 0x2e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w8, 2:3, vgx2], { z22.h, z23.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0xc9, 0x0a, 0x2e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w8, 2:3, vgx2], { z22.h, z23.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x2a, 0x69, 0x21, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w11, 4:5, vgx2], { z9.h, z10.h }, z1.h"
+
+  -
+    input:
+      bytes: [ 0x2a, 0x69, 0x21, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w11, 4:5, vgx2], { z9.h, z10.h }, z1.h"
+
+  -
+    input:
+      bytes: [ 0x8b, 0x29, 0x2b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w9, 6:7, vgx2], { z12.h, z13.h }, z11.h"
+
+  -
+    input:
+      bytes: [ 0x8b, 0x29, 0x2b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w9, 6:7, vgx2], { z12.h, z13.h }, z11.h"
+
+  -
+    input:
+      bytes: [ 0x08, 0x10, 0x90, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w8, 0:1, vgx2], { z0.h, z1.h }, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x08, 0x10, 0x90, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w8, 0:1, vgx2], { z0.h, z1.h }, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x4d, 0x55, 0x95, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w10, 2:3, vgx2], { z10.h, z11.h }, z5.h[3]"
+
+  -
+    input:
+      bytes: [ 0x4d, 0x55, 0x95, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w10, 2:3, vgx2], { z10.h, z11.h }, z5.h[3]"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x7d, 0x98, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w11, 6:7, vgx2], { z12.h, z13.h }, z8.h[7]"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x7d, 0x98, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w11, 6:7, vgx2], { z12.h, z13.h }, z8.h[7]"
+
+  -
+    input:
+      bytes: [ 0xcf, 0x7f, 0x9f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w11, 6:7, vgx2], { z30.h, z31.h }, z15.h[7]"
+
+  -
+    input:
+      bytes: [ 0xcf, 0x7f, 0x9f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w11, 6:7, vgx2], { z30.h, z31.h }, z15.h[7]"
+
+  -
+    input:
+      bytes: [ 0x0d, 0x1e, 0x90, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w8, 2:3, vgx2], { z16.h, z17.h }, z0.h[7]"
+
+  -
+    input:
+      bytes: [ 0x0d, 0x1e, 0x90, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w8, 2:3, vgx2], { z16.h, z17.h }, z0.h[7]"
+
+  -
+    input:
+      bytes: [ 0x09, 0x14, 0x9e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w8, 2:3, vgx2], { z0.h, z1.h }, z14.h[2]"
+
+  -
+    input:
+      bytes: [ 0x09, 0x14, 0x9e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w8, 2:3, vgx2], { z0.h, z1.h }, z14.h[2]"
+
+  -
+    input:
+      bytes: [ 0x48, 0x56, 0x94, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w10, 0:1, vgx2], { z18.h, z19.h }, z4.h[2]"
+
+  -
+    input:
+      bytes: [ 0x48, 0x56, 0x94, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w10, 0:1, vgx2], { z18.h, z19.h }, z4.h[2]"
+
+  -
+    input:
+      bytes: [ 0x88, 0x19, 0x92, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w8, 0:1, vgx2], { z12.h, z13.h }, z2.h[4]"
+
+  -
+    input:
+      bytes: [ 0x88, 0x19, 0x92, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w8, 0:1, vgx2], { z12.h, z13.h }, z2.h[4]"
+
+  -
+    input:
+      bytes: [ 0x09, 0x58, 0x9a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w10, 2:3, vgx2], { z0.h, z1.h }, z10.h[4]"
+
+  -
+    input:
+      bytes: [ 0x09, 0x58, 0x9a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w10, 2:3, vgx2], { z0.h, z1.h }, z10.h[4]"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x1a, 0x9e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w8, 2:3, vgx2], { z22.h, z23.h }, z14.h[5]"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x1a, 0x9e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w8, 2:3, vgx2], { z22.h, z23.h }, z14.h[5]"
+
+  -
+    input:
+      bytes: [ 0x0a, 0x75, 0x91, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w11, 4:5, vgx2], { z8.h, z9.h }, z1.h[2]"
+
+  -
+    input:
+      bytes: [ 0x0a, 0x75, 0x91, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w11, 4:5, vgx2], { z8.h, z9.h }, z1.h[2]"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x39, 0x9b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w9, 6:7, vgx2], { z12.h, z13.h }, z11.h[5]"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x39, 0x9b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w9, 6:7, vgx2], { z12.h, z13.h }, z11.h[5]"
+
+  -
+    input:
+      bytes: [ 0x08, 0x08, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w8, 0:1, vgx2], { z0.h, z1.h }, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x08, 0x08, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w8, 0:1, vgx2], { z0.h, z1.h }, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x49, 0x49, 0xb4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w10, 2:3, vgx2], { z10.h, z11.h }, { z20.h, z21.h }"
+
+  -
+    input:
+      bytes: [ 0x49, 0x49, 0xb4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w10, 2:3, vgx2], { z10.h, z11.h }, { z20.h, z21.h }"
+
+  -
+    input:
+      bytes: [ 0x8b, 0x69, 0xa8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w11, 6:7, vgx2], { z12.h, z13.h }, { z8.h, z9.h }"
+
+  -
+    input:
+      bytes: [ 0x8b, 0x69, 0xa8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w11, 6:7, vgx2], { z12.h, z13.h }, { z8.h, z9.h }"
+
+  -
+    input:
+      bytes: [ 0xcb, 0x6b, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w11, 6:7, vgx2], { z30.h, z31.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0xcb, 0x6b, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w11, 6:7, vgx2], { z30.h, z31.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x0a, 0xb0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w8, 2:3, vgx2], { z16.h, z17.h }, { z16.h, z17.h }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x0a, 0xb0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w8, 2:3, vgx2], { z16.h, z17.h }, { z16.h, z17.h }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x08, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w8, 2:3, vgx2], { z0.h, z1.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x08, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w8, 2:3, vgx2], { z0.h, z1.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x48, 0x4a, 0xb4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w10, 0:1, vgx2], { z18.h, z19.h }, { z20.h, z21.h }"
+
+  -
+    input:
+      bytes: [ 0x48, 0x4a, 0xb4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w10, 0:1, vgx2], { z18.h, z19.h }, { z20.h, z21.h }"
+
+  -
+    input:
+      bytes: [ 0x88, 0x09, 0xa2, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w8, 0:1, vgx2], { z12.h, z13.h }, { z2.h, z3.h }"
+
+  -
+    input:
+      bytes: [ 0x88, 0x09, 0xa2, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w8, 0:1, vgx2], { z12.h, z13.h }, { z2.h, z3.h }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x48, 0xba, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w10, 2:3, vgx2], { z0.h, z1.h }, { z26.h, z27.h }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x48, 0xba, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w10, 2:3, vgx2], { z0.h, z1.h }, { z26.h, z27.h }"
+
+  -
+    input:
+      bytes: [ 0xc9, 0x0a, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w8, 2:3, vgx2], { z22.h, z23.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0xc9, 0x0a, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w8, 2:3, vgx2], { z22.h, z23.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x0a, 0x69, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w11, 4:5, vgx2], { z8.h, z9.h }, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x0a, 0x69, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w11, 4:5, vgx2], { z8.h, z9.h }, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x8b, 0x29, 0xaa, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w9, 6:7, vgx2], { z12.h, z13.h }, { z10.h, z11.h }"
+
+  -
+    input:
+      bytes: [ 0x8b, 0x29, 0xaa, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w9, 6:7, vgx2], { z12.h, z13.h }, { z10.h, z11.h }"
+
+  -
+    input:
+      bytes: [ 0x08, 0x08, 0x30, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w8, 0:1, vgx4], { z0.h - z3.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x08, 0x08, 0x30, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w8, 0:1, vgx4], { z0.h - z3.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x49, 0x49, 0x35, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w10, 2:3, vgx4], { z10.h - z13.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0x49, 0x49, 0x35, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w10, 2:3, vgx4], { z10.h - z13.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0xab, 0x69, 0x38, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w11, 6:7, vgx4], { z13.h - z16.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0xab, 0x69, 0x38, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w11, 6:7, vgx4], { z13.h - z16.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0xeb, 0x6b, 0x3f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w11, 6:7, vgx4], { z31.h, z0.h, z1.h, z2.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0xeb, 0x6b, 0x3f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w11, 6:7, vgx4], { z31.h, z0.h, z1.h, z2.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0x29, 0x0a, 0x30, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w8, 2:3, vgx4], { z17.h - z20.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x29, 0x0a, 0x30, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w8, 2:3, vgx4], { z17.h - z20.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x29, 0x08, 0x3e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w8, 2:3, vgx4], { z1.h - z4.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x29, 0x08, 0x3e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w8, 2:3, vgx4], { z1.h - z4.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x68, 0x4a, 0x34, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w10, 0:1, vgx4], { z19.h - z22.h }, z4.h"
+
+  -
+    input:
+      bytes: [ 0x68, 0x4a, 0x34, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w10, 0:1, vgx4], { z19.h - z22.h }, z4.h"
+
+  -
+    input:
+      bytes: [ 0x88, 0x09, 0x32, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w8, 0:1, vgx4], { z12.h - z15.h }, z2.h"
+
+  -
+    input:
+      bytes: [ 0x88, 0x09, 0x32, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w8, 0:1, vgx4], { z12.h - z15.h }, z2.h"
+
+  -
+    input:
+      bytes: [ 0x29, 0x48, 0x3a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w10, 2:3, vgx4], { z1.h - z4.h }, z10.h"
+
+  -
+    input:
+      bytes: [ 0x29, 0x48, 0x3a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w10, 2:3, vgx4], { z1.h - z4.h }, z10.h"
+
+  -
+    input:
+      bytes: [ 0xc9, 0x0a, 0x3e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w8, 2:3, vgx4], { z22.h - z25.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0xc9, 0x0a, 0x3e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w8, 2:3, vgx4], { z22.h - z25.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x2a, 0x69, 0x31, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w11, 4:5, vgx4], { z9.h - z12.h }, z1.h"
+
+  -
+    input:
+      bytes: [ 0x2a, 0x69, 0x31, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w11, 4:5, vgx4], { z9.h - z12.h }, z1.h"
+
+  -
+    input:
+      bytes: [ 0x8b, 0x29, 0x3b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w9, 6:7, vgx4], { z12.h - z15.h }, z11.h"
+
+  -
+    input:
+      bytes: [ 0x8b, 0x29, 0x3b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w9, 6:7, vgx4], { z12.h - z15.h }, z11.h"
+
+  -
+    input:
+      bytes: [ 0x08, 0x90, 0x90, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w8, 0:1, vgx4], { z0.h - z3.h }, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x08, 0x90, 0x90, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w8, 0:1, vgx4], { z0.h - z3.h }, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x0d, 0xd5, 0x95, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w10, 2:3, vgx4], { z8.h - z11.h }, z5.h[3]"
+
+  -
+    input:
+      bytes: [ 0x0d, 0xd5, 0x95, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w10, 2:3, vgx4], { z8.h - z11.h }, z5.h[3]"
+
+  -
+    input:
+      bytes: [ 0x8f, 0xfd, 0x98, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w11, 6:7, vgx4], { z12.h - z15.h }, z8.h[7]"
+
+  -
+    input:
+      bytes: [ 0x8f, 0xfd, 0x98, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w11, 6:7, vgx4], { z12.h - z15.h }, z8.h[7]"
+
+  -
+    input:
+      bytes: [ 0x8f, 0xff, 0x9f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w11, 6:7, vgx4], { z28.h - z31.h }, z15.h[7]"
+
+  -
+    input:
+      bytes: [ 0x8f, 0xff, 0x9f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w11, 6:7, vgx4], { z28.h - z31.h }, z15.h[7]"
+
+  -
+    input:
+      bytes: [ 0x0d, 0x9e, 0x90, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w8, 2:3, vgx4], { z16.h - z19.h }, z0.h[7]"
+
+  -
+    input:
+      bytes: [ 0x0d, 0x9e, 0x90, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w8, 2:3, vgx4], { z16.h - z19.h }, z0.h[7]"
+
+  -
+    input:
+      bytes: [ 0x09, 0x94, 0x9e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w8, 2:3, vgx4], { z0.h - z3.h }, z14.h[2]"
+
+  -
+    input:
+      bytes: [ 0x09, 0x94, 0x9e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w8, 2:3, vgx4], { z0.h - z3.h }, z14.h[2]"
+
+  -
+    input:
+      bytes: [ 0x08, 0xd6, 0x94, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w10, 0:1, vgx4], { z16.h - z19.h }, z4.h[2]"
+
+  -
+    input:
+      bytes: [ 0x08, 0xd6, 0x94, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w10, 0:1, vgx4], { z16.h - z19.h }, z4.h[2]"
+
+  -
+    input:
+      bytes: [ 0x88, 0x99, 0x92, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w8, 0:1, vgx4], { z12.h - z15.h }, z2.h[4]"
+
+  -
+    input:
+      bytes: [ 0x88, 0x99, 0x92, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w8, 0:1, vgx4], { z12.h - z15.h }, z2.h[4]"
+
+  -
+    input:
+      bytes: [ 0x09, 0xd8, 0x9a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w10, 2:3, vgx4], { z0.h - z3.h }, z10.h[4]"
+
+  -
+    input:
+      bytes: [ 0x09, 0xd8, 0x9a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w10, 2:3, vgx4], { z0.h - z3.h }, z10.h[4]"
+
+  -
+    input:
+      bytes: [ 0x8d, 0x9a, 0x9e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w8, 2:3, vgx4], { z20.h - z23.h }, z14.h[5]"
+
+  -
+    input:
+      bytes: [ 0x8d, 0x9a, 0x9e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w8, 2:3, vgx4], { z20.h - z23.h }, z14.h[5]"
+
+  -
+    input:
+      bytes: [ 0x0a, 0xf5, 0x91, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w11, 4:5, vgx4], { z8.h - z11.h }, z1.h[2]"
+
+  -
+    input:
+      bytes: [ 0x0a, 0xf5, 0x91, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w11, 4:5, vgx4], { z8.h - z11.h }, z1.h[2]"
+
+  -
+    input:
+      bytes: [ 0x8f, 0xb9, 0x9b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w9, 6:7, vgx4], { z12.h - z15.h }, z11.h[5]"
+
+  -
+    input:
+      bytes: [ 0x8f, 0xb9, 0x9b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w9, 6:7, vgx4], { z12.h - z15.h }, z11.h[5]"
+
+  -
+    input:
+      bytes: [ 0x08, 0x08, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w8, 0:1, vgx4], { z0.h - z3.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x08, 0x08, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w8, 0:1, vgx4], { z0.h - z3.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x49, 0xb5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w10, 2:3, vgx4], { z8.h - z11.h }, { z20.h - z23.h }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x49, 0xb5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w10, 2:3, vgx4], { z8.h - z11.h }, { z20.h - z23.h }"
+
+  -
+    input:
+      bytes: [ 0x8b, 0x69, 0xa9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w11, 6:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }"
+
+  -
+    input:
+      bytes: [ 0x8b, 0x69, 0xa9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w11, 6:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }"
+
+  -
+    input:
+      bytes: [ 0x8b, 0x6b, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w11, 6:7, vgx4], { z28.h - z31.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x8b, 0x6b, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w11, 6:7, vgx4], { z28.h - z31.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x0a, 0xb1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w8, 2:3, vgx4], { z16.h - z19.h }, { z16.h - z19.h }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x0a, 0xb1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w8, 2:3, vgx4], { z16.h - z19.h }, { z16.h - z19.h }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x08, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w8, 2:3, vgx4], { z0.h - z3.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x08, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w8, 2:3, vgx4], { z0.h - z3.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x08, 0x4a, 0xb5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w10, 0:1, vgx4], { z16.h - z19.h }, { z20.h - z23.h }"
+
+  -
+    input:
+      bytes: [ 0x08, 0x4a, 0xb5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w10, 0:1, vgx4], { z16.h - z19.h }, { z20.h - z23.h }"
+
+  -
+    input:
+      bytes: [ 0x88, 0x09, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w8, 0:1, vgx4], { z12.h - z15.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x88, 0x09, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w8, 0:1, vgx4], { z12.h - z15.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x48, 0xb9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w10, 2:3, vgx4], { z0.h - z3.h }, { z24.h - z27.h }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x48, 0xb9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w10, 2:3, vgx4], { z0.h - z3.h }, { z24.h - z27.h }"
+
+  -
+    input:
+      bytes: [ 0x89, 0x0a, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w8, 2:3, vgx4], { z20.h - z23.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x89, 0x0a, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w8, 2:3, vgx4], { z20.h - z23.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x0a, 0x69, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w11, 4:5, vgx4], { z8.h - z11.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x0a, 0x69, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w11, 4:5, vgx4], { z8.h - z11.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x8b, 0x29, 0xa9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w9, 6:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }"
+
+  -
+    input:
+      bytes: [ 0x8b, 0x29, 0xa9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl za.s[w9, 6:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }"
diff --git a/tests/MC/AArch64/SME2/frinta.s.yaml b/tests/MC/AArch64/SME2/frinta.s.yaml
new file mode 100644
index 000000000..828b21eb8
--- /dev/null
+++ b/tests/MC/AArch64/SME2/frinta.s.yaml
@@ -0,0 +1,80 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xac, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "frinta { z0.s, z1.s }, { z0.s, z1.s }"
+
+  -
+    input:
+      bytes: [ 0x54, 0xe1, 0xac, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "frinta { z20.s, z21.s }, { z10.s, z11.s }"
+
+  -
+    input:
+      bytes: [ 0x96, 0xe1, 0xac, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "frinta { z22.s, z23.s }, { z12.s, z13.s }"
+
+  -
+    input:
+      bytes: [ 0xde, 0xe3, 0xac, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "frinta { z30.s, z31.s }, { z30.s, z31.s }"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xbc, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "frinta { z0.s - z3.s }, { z0.s - z3.s }"
+
+  -
+    input:
+      bytes: [ 0x14, 0xe1, 0xbc, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "frinta { z20.s - z23.s }, { z8.s - z11.s }"
+
+  -
+    input:
+      bytes: [ 0x94, 0xe1, 0xbc, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "frinta { z20.s - z23.s }, { z12.s - z15.s }"
+
+  -
+    input:
+      bytes: [ 0x9c, 0xe3, 0xbc, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "frinta { z28.s - z31.s }, { z28.s - z31.s }"
diff --git a/tests/MC/AArch64/SME2/frintm.s.yaml b/tests/MC/AArch64/SME2/frintm.s.yaml
new file mode 100644
index 000000000..ea63de599
--- /dev/null
+++ b/tests/MC/AArch64/SME2/frintm.s.yaml
@@ -0,0 +1,80 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xaa, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "frintm { z0.s, z1.s }, { z0.s, z1.s }"
+
+  -
+    input:
+      bytes: [ 0x54, 0xe1, 0xaa, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "frintm { z20.s, z21.s }, { z10.s, z11.s }"
+
+  -
+    input:
+      bytes: [ 0x96, 0xe1, 0xaa, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "frintm { z22.s, z23.s }, { z12.s, z13.s }"
+
+  -
+    input:
+      bytes: [ 0xde, 0xe3, 0xaa, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "frintm { z30.s, z31.s }, { z30.s, z31.s }"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xba, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "frintm { z0.s - z3.s }, { z0.s - z3.s }"
+
+  -
+    input:
+      bytes: [ 0x14, 0xe1, 0xba, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "frintm { z20.s - z23.s }, { z8.s - z11.s }"
+
+  -
+    input:
+      bytes: [ 0x94, 0xe1, 0xba, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "frintm { z20.s - z23.s }, { z12.s - z15.s }"
+
+  -
+    input:
+      bytes: [ 0x9c, 0xe3, 0xba, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "frintm { z28.s - z31.s }, { z28.s - z31.s }"
diff --git a/tests/MC/AArch64/SME2/frintn.s.yaml b/tests/MC/AArch64/SME2/frintn.s.yaml
new file mode 100644
index 000000000..cd9e755a8
--- /dev/null
+++ b/tests/MC/AArch64/SME2/frintn.s.yaml
@@ -0,0 +1,80 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xa8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "frintn { z0.s, z1.s }, { z0.s, z1.s }"
+
+  -
+    input:
+      bytes: [ 0x54, 0xe1, 0xa8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "frintn { z20.s, z21.s }, { z10.s, z11.s }"
+
+  -
+    input:
+      bytes: [ 0x96, 0xe1, 0xa8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "frintn { z22.s, z23.s }, { z12.s, z13.s }"
+
+  -
+    input:
+      bytes: [ 0xde, 0xe3, 0xa8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "frintn { z30.s, z31.s }, { z30.s, z31.s }"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xb8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "frintn { z0.s - z3.s }, { z0.s - z3.s }"
+
+  -
+    input:
+      bytes: [ 0x14, 0xe1, 0xb8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "frintn { z20.s - z23.s }, { z8.s - z11.s }"
+
+  -
+    input:
+      bytes: [ 0x94, 0xe1, 0xb8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "frintn { z20.s - z23.s }, { z12.s - z15.s }"
+
+  -
+    input:
+      bytes: [ 0x9c, 0xe3, 0xb8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "frintn { z28.s - z31.s }, { z28.s - z31.s }"
diff --git a/tests/MC/AArch64/SME2/frintp.s.yaml b/tests/MC/AArch64/SME2/frintp.s.yaml
new file mode 100644
index 000000000..1b63b5610
--- /dev/null
+++ b/tests/MC/AArch64/SME2/frintp.s.yaml
@@ -0,0 +1,80 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xa9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "frintp { z0.s, z1.s }, { z0.s, z1.s }"
+
+  -
+    input:
+      bytes: [ 0x54, 0xe1, 0xa9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "frintp { z20.s, z21.s }, { z10.s, z11.s }"
+
+  -
+    input:
+      bytes: [ 0x96, 0xe1, 0xa9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "frintp { z22.s, z23.s }, { z12.s, z13.s }"
+
+  -
+    input:
+      bytes: [ 0xde, 0xe3, 0xa9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "frintp { z30.s, z31.s }, { z30.s, z31.s }"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xb9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "frintp { z0.s - z3.s }, { z0.s - z3.s }"
+
+  -
+    input:
+      bytes: [ 0x14, 0xe1, 0xb9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "frintp { z20.s - z23.s }, { z8.s - z11.s }"
+
+  -
+    input:
+      bytes: [ 0x94, 0xe1, 0xb9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "frintp { z20.s - z23.s }, { z12.s - z15.s }"
+
+  -
+    input:
+      bytes: [ 0x9c, 0xe3, 0xb9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "frintp { z28.s - z31.s }, { z28.s - z31.s }"
diff --git a/tests/MC/AArch64/SME2/fsub.s.yaml b/tests/MC/AArch64/SME2/fsub.s.yaml
new file mode 100644
index 000000000..9e508d6e3
--- /dev/null
+++ b/tests/MC/AArch64/SME2/fsub.s.yaml
@@ -0,0 +1,960 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x08, 0x1c, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.d[w8, 0, vgx2], { z0.d, z1.d }"
+
+  -
+    input:
+      bytes: [ 0x08, 0x1c, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.d[w8, 0, vgx2], { z0.d, z1.d }"
+
+  -
+    input:
+      bytes: [ 0x4d, 0x5d, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.d[w10, 5, vgx2], { z10.d, z11.d }"
+
+  -
+    input:
+      bytes: [ 0x4d, 0x5d, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.d[w10, 5, vgx2], { z10.d, z11.d }"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x7d, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.d[w11, 7, vgx2], { z12.d, z13.d }"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x7d, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.d[w11, 7, vgx2], { z12.d, z13.d }"
+
+  -
+    input:
+      bytes: [ 0xcf, 0x7f, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.d[w11, 7, vgx2], { z30.d, z31.d }"
+
+  -
+    input:
+      bytes: [ 0xcf, 0x7f, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.d[w11, 7, vgx2], { z30.d, z31.d }"
+
+  -
+    input:
+      bytes: [ 0x0d, 0x1e, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.d[w8, 5, vgx2], { z16.d, z17.d }"
+
+  -
+    input:
+      bytes: [ 0x0d, 0x1e, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.d[w8, 5, vgx2], { z16.d, z17.d }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x1c, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.d[w8, 1, vgx2], { z0.d, z1.d }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x1c, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.d[w8, 1, vgx2], { z0.d, z1.d }"
+
+  -
+    input:
+      bytes: [ 0x48, 0x5e, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.d[w10, 0, vgx2], { z18.d, z19.d }"
+
+  -
+    input:
+      bytes: [ 0x48, 0x5e, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.d[w10, 0, vgx2], { z18.d, z19.d }"
+
+  -
+    input:
+      bytes: [ 0x88, 0x1d, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.d[w8, 0, vgx2], { z12.d, z13.d }"
+
+  -
+    input:
+      bytes: [ 0x88, 0x1d, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.d[w8, 0, vgx2], { z12.d, z13.d }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x5c, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.d[w10, 1, vgx2], { z0.d, z1.d }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x5c, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.d[w10, 1, vgx2], { z0.d, z1.d }"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x1e, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.d[w8, 5, vgx2], { z22.d, z23.d }"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x1e, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.d[w8, 5, vgx2], { z22.d, z23.d }"
+
+  -
+    input:
+      bytes: [ 0x0a, 0x7d, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.d[w11, 2, vgx2], { z8.d, z9.d }"
+
+  -
+    input:
+      bytes: [ 0x0a, 0x7d, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.d[w11, 2, vgx2], { z8.d, z9.d }"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x3d, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.d[w9, 7, vgx2], { z12.d, z13.d }"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x3d, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.d[w9, 7, vgx2], { z12.d, z13.d }"
+
+  -
+    input:
+      bytes: [ 0x08, 0x1c, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.s[w8, 0, vgx2], { z0.s, z1.s }"
+
+  -
+    input:
+      bytes: [ 0x08, 0x1c, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.s[w8, 0, vgx2], { z0.s, z1.s }"
+
+  -
+    input:
+      bytes: [ 0x4d, 0x5d, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.s[w10, 5, vgx2], { z10.s, z11.s }"
+
+  -
+    input:
+      bytes: [ 0x4d, 0x5d, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.s[w10, 5, vgx2], { z10.s, z11.s }"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x7d, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.s[w11, 7, vgx2], { z12.s, z13.s }"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x7d, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.s[w11, 7, vgx2], { z12.s, z13.s }"
+
+  -
+    input:
+      bytes: [ 0xcf, 0x7f, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.s[w11, 7, vgx2], { z30.s, z31.s }"
+
+  -
+    input:
+      bytes: [ 0xcf, 0x7f, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.s[w11, 7, vgx2], { z30.s, z31.s }"
+
+  -
+    input:
+      bytes: [ 0x0d, 0x1e, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.s[w8, 5, vgx2], { z16.s, z17.s }"
+
+  -
+    input:
+      bytes: [ 0x0d, 0x1e, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.s[w8, 5, vgx2], { z16.s, z17.s }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x1c, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.s[w8, 1, vgx2], { z0.s, z1.s }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x1c, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.s[w8, 1, vgx2], { z0.s, z1.s }"
+
+  -
+    input:
+      bytes: [ 0x48, 0x5e, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.s[w10, 0, vgx2], { z18.s, z19.s }"
+
+  -
+    input:
+      bytes: [ 0x48, 0x5e, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.s[w10, 0, vgx2], { z18.s, z19.s }"
+
+  -
+    input:
+      bytes: [ 0x88, 0x1d, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.s[w8, 0, vgx2], { z12.s, z13.s }"
+
+  -
+    input:
+      bytes: [ 0x88, 0x1d, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.s[w8, 0, vgx2], { z12.s, z13.s }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x5c, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.s[w10, 1, vgx2], { z0.s, z1.s }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x5c, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.s[w10, 1, vgx2], { z0.s, z1.s }"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x1e, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.s[w8, 5, vgx2], { z22.s, z23.s }"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x1e, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.s[w8, 5, vgx2], { z22.s, z23.s }"
+
+  -
+    input:
+      bytes: [ 0x0a, 0x7d, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.s[w11, 2, vgx2], { z8.s, z9.s }"
+
+  -
+    input:
+      bytes: [ 0x0a, 0x7d, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.s[w11, 2, vgx2], { z8.s, z9.s }"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x3d, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.s[w9, 7, vgx2], { z12.s, z13.s }"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x3d, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.s[w9, 7, vgx2], { z12.s, z13.s }"
+
+  -
+    input:
+      bytes: [ 0x08, 0x1c, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.d[w8, 0, vgx4], { z0.d - z3.d }"
+
+  -
+    input:
+      bytes: [ 0x08, 0x1c, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.d[w8, 0, vgx4], { z0.d - z3.d }"
+
+  -
+    input:
+      bytes: [ 0x0d, 0x5d, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.d[w10, 5, vgx4], { z8.d - z11.d }"
+
+  -
+    input:
+      bytes: [ 0x0d, 0x5d, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.d[w10, 5, vgx4], { z8.d - z11.d }"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x7d, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.d[w11, 7, vgx4], { z12.d - z15.d }"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x7d, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.d[w11, 7, vgx4], { z12.d - z15.d }"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x7f, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.d[w11, 7, vgx4], { z28.d - z31.d }"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x7f, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.d[w11, 7, vgx4], { z28.d - z31.d }"
+
+  -
+    input:
+      bytes: [ 0x0d, 0x1e, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.d[w8, 5, vgx4], { z16.d - z19.d }"
+
+  -
+    input:
+      bytes: [ 0x0d, 0x1e, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.d[w8, 5, vgx4], { z16.d - z19.d }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x1c, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.d[w8, 1, vgx4], { z0.d - z3.d }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x1c, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.d[w8, 1, vgx4], { z0.d - z3.d }"
+
+  -
+    input:
+      bytes: [ 0x08, 0x5e, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.d[w10, 0, vgx4], { z16.d - z19.d }"
+
+  -
+    input:
+      bytes: [ 0x08, 0x5e, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.d[w10, 0, vgx4], { z16.d - z19.d }"
+
+  -
+    input:
+      bytes: [ 0x88, 0x1d, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.d[w8, 0, vgx4], { z12.d - z15.d }"
+
+  -
+    input:
+      bytes: [ 0x88, 0x1d, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.d[w8, 0, vgx4], { z12.d - z15.d }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x5c, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.d[w10, 1, vgx4], { z0.d - z3.d }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x5c, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.d[w10, 1, vgx4], { z0.d - z3.d }"
+
+  -
+    input:
+      bytes: [ 0x8d, 0x1e, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.d[w8, 5, vgx4], { z20.d - z23.d }"
+
+  -
+    input:
+      bytes: [ 0x8d, 0x1e, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.d[w8, 5, vgx4], { z20.d - z23.d }"
+
+  -
+    input:
+      bytes: [ 0x0a, 0x7d, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.d[w11, 2, vgx4], { z8.d - z11.d }"
+
+  -
+    input:
+      bytes: [ 0x0a, 0x7d, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.d[w11, 2, vgx4], { z8.d - z11.d }"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x3d, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.d[w9, 7, vgx4], { z12.d - z15.d }"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x3d, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.d[w9, 7, vgx4], { z12.d - z15.d }"
+
+  -
+    input:
+      bytes: [ 0x08, 0x1c, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.s[w8, 0, vgx4], { z0.s - z3.s }"
+
+  -
+    input:
+      bytes: [ 0x08, 0x1c, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.s[w8, 0, vgx4], { z0.s - z3.s }"
+
+  -
+    input:
+      bytes: [ 0x0d, 0x5d, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.s[w10, 5, vgx4], { z8.s - z11.s }"
+
+  -
+    input:
+      bytes: [ 0x0d, 0x5d, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.s[w10, 5, vgx4], { z8.s - z11.s }"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x7d, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.s[w11, 7, vgx4], { z12.s - z15.s }"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x7d, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.s[w11, 7, vgx4], { z12.s - z15.s }"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x7f, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.s[w11, 7, vgx4], { z28.s - z31.s }"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x7f, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.s[w11, 7, vgx4], { z28.s - z31.s }"
+
+  -
+    input:
+      bytes: [ 0x0d, 0x1e, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.s[w8, 5, vgx4], { z16.s - z19.s }"
+
+  -
+    input:
+      bytes: [ 0x0d, 0x1e, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.s[w8, 5, vgx4], { z16.s - z19.s }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x1c, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.s[w8, 1, vgx4], { z0.s - z3.s }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x1c, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.s[w8, 1, vgx4], { z0.s - z3.s }"
+
+  -
+    input:
+      bytes: [ 0x08, 0x5e, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.s[w10, 0, vgx4], { z16.s - z19.s }"
+
+  -
+    input:
+      bytes: [ 0x08, 0x5e, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.s[w10, 0, vgx4], { z16.s - z19.s }"
+
+  -
+    input:
+      bytes: [ 0x88, 0x1d, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.s[w8, 0, vgx4], { z12.s - z15.s }"
+
+  -
+    input:
+      bytes: [ 0x88, 0x1d, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.s[w8, 0, vgx4], { z12.s - z15.s }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x5c, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.s[w10, 1, vgx4], { z0.s - z3.s }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x5c, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.s[w10, 1, vgx4], { z0.s - z3.s }"
+
+  -
+    input:
+      bytes: [ 0x8d, 0x1e, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.s[w8, 5, vgx4], { z20.s - z23.s }"
+
+  -
+    input:
+      bytes: [ 0x8d, 0x1e, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.s[w8, 5, vgx4], { z20.s - z23.s }"
+
+  -
+    input:
+      bytes: [ 0x0a, 0x7d, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.s[w11, 2, vgx4], { z8.s - z11.s }"
+
+  -
+    input:
+      bytes: [ 0x0a, 0x7d, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.s[w11, 2, vgx4], { z8.s - z11.s }"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x3d, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.s[w9, 7, vgx4], { z12.s - z15.s }"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x3d, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-f64f64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.s[w9, 7, vgx4], { z12.s - z15.s }"
diff --git a/tests/MC/AArch64/SME2/fvdot.s.yaml b/tests/MC/AArch64/SME2/fvdot.s.yaml
new file mode 100644
index 000000000..eafd23ef8
--- /dev/null
+++ b/tests/MC/AArch64/SME2/fvdot.s.yaml
@@ -0,0 +1,240 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x08, 0x00, 0x50, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fvdot za.s[w8, 0, vgx2], { z0.h, z1.h }, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x08, 0x00, 0x50, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fvdot za.s[w8, 0, vgx2], { z0.h, z1.h }, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x4d, 0x45, 0x55, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fvdot za.s[w10, 5, vgx2], { z10.h, z11.h }, z5.h[1]"
+
+  -
+    input:
+      bytes: [ 0x4d, 0x45, 0x55, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fvdot za.s[w10, 5, vgx2], { z10.h, z11.h }, z5.h[1]"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x6d, 0x58, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fvdot za.s[w11, 7, vgx2], { z12.h, z13.h }, z8.h[3]"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x6d, 0x58, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fvdot za.s[w11, 7, vgx2], { z12.h, z13.h }, z8.h[3]"
+
+  -
+    input:
+      bytes: [ 0xcf, 0x6f, 0x5f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fvdot za.s[w11, 7, vgx2], { z30.h, z31.h }, z15.h[3]"
+
+  -
+    input:
+      bytes: [ 0xcf, 0x6f, 0x5f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fvdot za.s[w11, 7, vgx2], { z30.h, z31.h }, z15.h[3]"
+
+  -
+    input:
+      bytes: [ 0x0d, 0x0e, 0x50, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fvdot za.s[w8, 5, vgx2], { z16.h, z17.h }, z0.h[3]"
+
+  -
+    input:
+      bytes: [ 0x0d, 0x0e, 0x50, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fvdot za.s[w8, 5, vgx2], { z16.h, z17.h }, z0.h[3]"
+
+  -
+    input:
+      bytes: [ 0x09, 0x04, 0x5e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fvdot za.s[w8, 1, vgx2], { z0.h, z1.h }, z14.h[1]"
+
+  -
+    input:
+      bytes: [ 0x09, 0x04, 0x5e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fvdot za.s[w8, 1, vgx2], { z0.h, z1.h }, z14.h[1]"
+
+  -
+    input:
+      bytes: [ 0x48, 0x46, 0x54, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fvdot za.s[w10, 0, vgx2], { z18.h, z19.h }, z4.h[1]"
+
+  -
+    input:
+      bytes: [ 0x48, 0x46, 0x54, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fvdot za.s[w10, 0, vgx2], { z18.h, z19.h }, z4.h[1]"
+
+  -
+    input:
+      bytes: [ 0x88, 0x09, 0x52, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fvdot za.s[w8, 0, vgx2], { z12.h, z13.h }, z2.h[2]"
+
+  -
+    input:
+      bytes: [ 0x88, 0x09, 0x52, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fvdot za.s[w8, 0, vgx2], { z12.h, z13.h }, z2.h[2]"
+
+  -
+    input:
+      bytes: [ 0x09, 0x48, 0x5a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fvdot za.s[w10, 1, vgx2], { z0.h, z1.h }, z10.h[2]"
+
+  -
+    input:
+      bytes: [ 0x09, 0x48, 0x5a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fvdot za.s[w10, 1, vgx2], { z0.h, z1.h }, z10.h[2]"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x0a, 0x5e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fvdot za.s[w8, 5, vgx2], { z22.h, z23.h }, z14.h[2]"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x0a, 0x5e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fvdot za.s[w8, 5, vgx2], { z22.h, z23.h }, z14.h[2]"
+
+  -
+    input:
+      bytes: [ 0x0a, 0x65, 0x51, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fvdot za.s[w11, 2, vgx2], { z8.h, z9.h }, z1.h[1]"
+
+  -
+    input:
+      bytes: [ 0x0a, 0x65, 0x51, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fvdot za.s[w11, 2, vgx2], { z8.h, z9.h }, z1.h[1]"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x29, 0x5b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fvdot za.s[w9, 7, vgx2], { z12.h, z13.h }, z11.h[2]"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x29, 0x5b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fvdot za.s[w9, 7, vgx2], { z12.h, z13.h }, z11.h[2]"
diff --git a/tests/MC/AArch64/SME2/ld1b.s.yaml b/tests/MC/AArch64/SME2/ld1b.s.yaml
new file mode 100644
index 000000000..ea9b2ab9c
--- /dev/null
+++ b/tests/MC/AArch64/SME2/ld1b.s.yaml
@@ -0,0 +1,160 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x00, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b { z0.b, z8.b }, pn8/z, [x0, x0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x15, 0x15, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b { z21.b, z29.b }, pn13/z, [x10, x21]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x0d, 0x08, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b { z23.b, z31.b }, pn11/z, [x13, x8]"
+
+  -
+    input:
+      bytes: [ 0xf7, 0x1f, 0x1f, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b { z23.b, z31.b }, pn15/z, [sp, xzr]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x40, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b { z0.b, z8.b }, pn8/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x15, 0x45, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b { z21.b, z29.b }, pn13/z, [x10, #10, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x0d, 0x48, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b { z23.b, z31.b }, pn11/z, [x13, #-16, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xf7, 0x1f, 0x4f, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b { z23.b, z31.b }, pn15/z, [sp, #-2, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x00, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b { z0.b, z4.b, z8.b, z12.b }, pn8/z, [x0, x0]"
+
+  -
+    input:
+      bytes: [ 0x51, 0x95, 0x15, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b { z17.b, z21.b, z25.b, z29.b }, pn13/z, [x10, x21]"
+
+  -
+    input:
+      bytes: [ 0xb3, 0x8d, 0x08, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b { z19.b, z23.b, z27.b, z31.b }, pn11/z, [x13, x8]"
+
+  -
+    input:
+      bytes: [ 0xf3, 0x9f, 0x1f, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b { z19.b, z23.b, z27.b, z31.b }, pn15/z, [sp, xzr]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x40, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b { z0.b, z4.b, z8.b, z12.b }, pn8/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x51, 0x95, 0x45, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b { z17.b, z21.b, z25.b, z29.b }, pn13/z, [x10, #20, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xb3, 0x8d, 0x48, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b { z19.b, z23.b, z27.b, z31.b }, pn11/z, [x13, #-32, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xf3, 0x9f, 0x4f, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b { z19.b, z23.b, z27.b, z31.b }, pn15/z, [sp, #-4, mul vl]"
diff --git a/tests/MC/AArch64/SME2/ld1d.s.yaml b/tests/MC/AArch64/SME2/ld1d.s.yaml
new file mode 100644
index 000000000..b2ad76bd5
--- /dev/null
+++ b/tests/MC/AArch64/SME2/ld1d.s.yaml
@@ -0,0 +1,160 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0x00, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d { z0.d, z8.d }, pn8/z, [x0, x0, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x75, 0x15, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d { z21.d, z29.d }, pn13/z, [x10, x21, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x6d, 0x08, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d { z23.d, z31.d }, pn11/z, [x13, x8, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0xf7, 0x7f, 0x1f, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d { z23.d, z31.d }, pn15/z, [sp, xzr, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0x40, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d { z0.d, z8.d }, pn8/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x75, 0x45, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d { z21.d, z29.d }, pn13/z, [x10, #10, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x6d, 0x48, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d { z23.d, z31.d }, pn11/z, [x13, #-16, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xf7, 0x7f, 0x4f, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d { z23.d, z31.d }, pn15/z, [sp, #-2, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x00, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d { z0.d, z4.d, z8.d, z12.d }, pn8/z, [x0, x0, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x51, 0xf5, 0x15, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d { z17.d, z21.d, z25.d, z29.d }, pn13/z, [x10, x21, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0xb3, 0xed, 0x08, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d { z19.d, z23.d, z27.d, z31.d }, pn11/z, [x13, x8, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0xf3, 0xff, 0x1f, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d { z19.d, z23.d, z27.d, z31.d }, pn15/z, [sp, xzr, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x40, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d { z0.d, z4.d, z8.d, z12.d }, pn8/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x51, 0xf5, 0x45, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d { z17.d, z21.d, z25.d, z29.d }, pn13/z, [x10, #20, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xb3, 0xed, 0x48, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d { z19.d, z23.d, z27.d, z31.d }, pn11/z, [x13, #-32, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xf3, 0xff, 0x4f, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d { z19.d, z23.d, z27.d, z31.d }, pn15/z, [sp, #-4, mul vl]"
diff --git a/tests/MC/AArch64/SME2/ld1h.s.yaml b/tests/MC/AArch64/SME2/ld1h.s.yaml
new file mode 100644
index 000000000..72fe95b13
--- /dev/null
+++ b/tests/MC/AArch64/SME2/ld1h.s.yaml
@@ -0,0 +1,160 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x00, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h { z0.h, z8.h }, pn8/z, [x0, x0, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x35, 0x15, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h { z21.h, z29.h }, pn13/z, [x10, x21, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x2d, 0x08, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h { z23.h, z31.h }, pn11/z, [x13, x8, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0xf7, 0x3f, 0x1f, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h { z23.h, z31.h }, pn15/z, [sp, xzr, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x40, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h { z0.h, z8.h }, pn8/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x35, 0x45, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h { z21.h, z29.h }, pn13/z, [x10, #10, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x2d, 0x48, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h { z23.h, z31.h }, pn11/z, [x13, #-16, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xf7, 0x3f, 0x4f, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h { z23.h, z31.h }, pn15/z, [sp, #-2, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x00, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h { z0.h, z4.h, z8.h, z12.h }, pn8/z, [x0, x0, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x51, 0xb5, 0x15, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h { z17.h, z21.h, z25.h, z29.h }, pn13/z, [x10, x21, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0xb3, 0xad, 0x08, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h { z19.h, z23.h, z27.h, z31.h }, pn11/z, [x13, x8, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0xf3, 0xbf, 0x1f, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h { z19.h, z23.h, z27.h, z31.h }, pn15/z, [sp, xzr, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x40, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h { z0.h, z4.h, z8.h, z12.h }, pn8/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x51, 0xb5, 0x45, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h { z17.h, z21.h, z25.h, z29.h }, pn13/z, [x10, #20, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xb3, 0xad, 0x48, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h { z19.h, z23.h, z27.h, z31.h }, pn11/z, [x13, #-32, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xf3, 0xbf, 0x4f, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h { z19.h, z23.h, z27.h, z31.h }, pn15/z, [sp, #-4, mul vl]"
diff --git a/tests/MC/AArch64/SME2/ld1w.s.yaml b/tests/MC/AArch64/SME2/ld1w.s.yaml
new file mode 100644
index 000000000..3704d0098
--- /dev/null
+++ b/tests/MC/AArch64/SME2/ld1w.s.yaml
@@ -0,0 +1,160 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0x00, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w { z0.s, z8.s }, pn8/z, [x0, x0, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x55, 0x15, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w { z21.s, z29.s }, pn13/z, [x10, x21, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x4d, 0x08, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w { z23.s, z31.s }, pn11/z, [x13, x8, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0xf7, 0x5f, 0x1f, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w { z23.s, z31.s }, pn15/z, [sp, xzr, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0x40, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w { z0.s, z8.s }, pn8/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x55, 0x45, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w { z21.s, z29.s }, pn13/z, [x10, #10, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x4d, 0x48, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w { z23.s, z31.s }, pn11/z, [x13, #-16, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xf7, 0x5f, 0x4f, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w { z23.s, z31.s }, pn15/z, [sp, #-2, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x00, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w { z0.s, z4.s, z8.s, z12.s }, pn8/z, [x0, x0, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x51, 0xd5, 0x15, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w { z17.s, z21.s, z25.s, z29.s }, pn13/z, [x10, x21, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0xb3, 0xcd, 0x08, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w { z19.s, z23.s, z27.s, z31.s }, pn11/z, [x13, x8, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0xf3, 0xdf, 0x1f, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w { z19.s, z23.s, z27.s, z31.s }, pn15/z, [sp, xzr, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x40, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w { z0.s, z4.s, z8.s, z12.s }, pn8/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x51, 0xd5, 0x45, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w { z17.s, z21.s, z25.s, z29.s }, pn13/z, [x10, #20, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xb3, 0xcd, 0x48, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w { z19.s, z23.s, z27.s, z31.s }, pn11/z, [x13, #-32, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xf3, 0xdf, 0x4f, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w { z19.s, z23.s, z27.s, z31.s }, pn15/z, [sp, #-4, mul vl]"
diff --git a/tests/MC/AArch64/SME2/ldnt1b.s.yaml b/tests/MC/AArch64/SME2/ldnt1b.s.yaml
new file mode 100644
index 000000000..786d373bb
--- /dev/null
+++ b/tests/MC/AArch64/SME2/ldnt1b.s.yaml
@@ -0,0 +1,160 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x08, 0x00, 0x00, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1b { z0.b, z8.b }, pn8/z, [x0, x0]"
+
+  -
+    input:
+      bytes: [ 0x5d, 0x15, 0x15, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1b { z21.b, z29.b }, pn13/z, [x10, x21]"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x0d, 0x08, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1b { z23.b, z31.b }, pn11/z, [x13, x8]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0x1f, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1b { z23.b, z31.b }, pn15/z, [sp, xzr]"
+
+  -
+    input:
+      bytes: [ 0x08, 0x00, 0x40, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1b { z0.b, z8.b }, pn8/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x5d, 0x15, 0x45, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1b { z21.b, z29.b }, pn13/z, [x10, #10, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x0d, 0x48, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1b { z23.b, z31.b }, pn11/z, [x13, #-16, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0x4f, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1b { z23.b, z31.b }, pn15/z, [sp, #-2, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x08, 0x80, 0x00, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1b { z0.b, z4.b, z8.b, z12.b }, pn8/z, [x0, x0]"
+
+  -
+    input:
+      bytes: [ 0x59, 0x95, 0x15, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1b { z17.b, z21.b, z25.b, z29.b }, pn13/z, [x10, x21]"
+
+  -
+    input:
+      bytes: [ 0xbb, 0x8d, 0x08, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1b { z19.b, z23.b, z27.b, z31.b }, pn11/z, [x13, x8]"
+
+  -
+    input:
+      bytes: [ 0xfb, 0x9f, 0x1f, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1b { z19.b, z23.b, z27.b, z31.b }, pn15/z, [sp, xzr]"
+
+  -
+    input:
+      bytes: [ 0x08, 0x80, 0x40, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1b { z0.b, z4.b, z8.b, z12.b }, pn8/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x59, 0x95, 0x45, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1b { z17.b, z21.b, z25.b, z29.b }, pn13/z, [x10, #20, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xbb, 0x8d, 0x48, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1b { z19.b, z23.b, z27.b, z31.b }, pn11/z, [x13, #-32, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xfb, 0x9f, 0x4f, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1b { z19.b, z23.b, z27.b, z31.b }, pn15/z, [sp, #-4, mul vl]"
diff --git a/tests/MC/AArch64/SME2/ldnt1d.s.yaml b/tests/MC/AArch64/SME2/ldnt1d.s.yaml
new file mode 100644
index 000000000..f2f638347
--- /dev/null
+++ b/tests/MC/AArch64/SME2/ldnt1d.s.yaml
@@ -0,0 +1,160 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x08, 0x60, 0x00, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1d { z0.d, z8.d }, pn8/z, [x0, x0, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x5d, 0x75, 0x15, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1d { z21.d, z29.d }, pn13/z, [x10, x21, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x6d, 0x08, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1d { z23.d, z31.d }, pn11/z, [x13, x8, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x7f, 0x1f, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1d { z23.d, z31.d }, pn15/z, [sp, xzr, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x08, 0x60, 0x40, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1d { z0.d, z8.d }, pn8/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x5d, 0x75, 0x45, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1d { z21.d, z29.d }, pn13/z, [x10, #10, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x6d, 0x48, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1d { z23.d, z31.d }, pn11/z, [x13, #-16, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x7f, 0x4f, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1d { z23.d, z31.d }, pn15/z, [sp, #-2, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x08, 0xe0, 0x00, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1d { z0.d, z4.d, z8.d, z12.d }, pn8/z, [x0, x0, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x59, 0xf5, 0x15, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1d { z17.d, z21.d, z25.d, z29.d }, pn13/z, [x10, x21, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0xbb, 0xed, 0x08, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1d { z19.d, z23.d, z27.d, z31.d }, pn11/z, [x13, x8, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0xfb, 0xff, 0x1f, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1d { z19.d, z23.d, z27.d, z31.d }, pn15/z, [sp, xzr, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x08, 0xe0, 0x40, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1d { z0.d, z4.d, z8.d, z12.d }, pn8/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x59, 0xf5, 0x45, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1d { z17.d, z21.d, z25.d, z29.d }, pn13/z, [x10, #20, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xbb, 0xed, 0x48, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1d { z19.d, z23.d, z27.d, z31.d }, pn11/z, [x13, #-32, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xfb, 0xff, 0x4f, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1d { z19.d, z23.d, z27.d, z31.d }, pn15/z, [sp, #-4, mul vl]"
diff --git a/tests/MC/AArch64/SME2/ldnt1h.s.yaml b/tests/MC/AArch64/SME2/ldnt1h.s.yaml
new file mode 100644
index 000000000..42ebce721
--- /dev/null
+++ b/tests/MC/AArch64/SME2/ldnt1h.s.yaml
@@ -0,0 +1,160 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x08, 0x20, 0x00, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1h { z0.h, z8.h }, pn8/z, [x0, x0, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x5d, 0x35, 0x15, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1h { z21.h, z29.h }, pn13/z, [x10, x21, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x2d, 0x08, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1h { z23.h, z31.h }, pn11/z, [x13, x8, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0x1f, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1h { z23.h, z31.h }, pn15/z, [sp, xzr, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x08, 0x20, 0x40, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1h { z0.h, z8.h }, pn8/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x5d, 0x35, 0x45, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1h { z21.h, z29.h }, pn13/z, [x10, #10, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x2d, 0x48, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1h { z23.h, z31.h }, pn11/z, [x13, #-16, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0x4f, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1h { z23.h, z31.h }, pn15/z, [sp, #-2, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x08, 0xa0, 0x00, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1h { z0.h, z4.h, z8.h, z12.h }, pn8/z, [x0, x0, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x59, 0xb5, 0x15, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1h { z17.h, z21.h, z25.h, z29.h }, pn13/z, [x10, x21, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0xbb, 0xad, 0x08, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1h { z19.h, z23.h, z27.h, z31.h }, pn11/z, [x13, x8, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0xfb, 0xbf, 0x1f, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1h { z19.h, z23.h, z27.h, z31.h }, pn15/z, [sp, xzr, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x08, 0xa0, 0x40, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1h { z0.h, z4.h, z8.h, z12.h }, pn8/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x59, 0xb5, 0x45, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1h { z17.h, z21.h, z25.h, z29.h }, pn13/z, [x10, #20, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xbb, 0xad, 0x48, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1h { z19.h, z23.h, z27.h, z31.h }, pn11/z, [x13, #-32, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xfb, 0xbf, 0x4f, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1h { z19.h, z23.h, z27.h, z31.h }, pn15/z, [sp, #-4, mul vl]"
diff --git a/tests/MC/AArch64/SME2/ldnt1w.s.yaml b/tests/MC/AArch64/SME2/ldnt1w.s.yaml
new file mode 100644
index 000000000..2861ee921
--- /dev/null
+++ b/tests/MC/AArch64/SME2/ldnt1w.s.yaml
@@ -0,0 +1,160 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x08, 0x40, 0x00, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1w { z0.s, z8.s }, pn8/z, [x0, x0, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x5d, 0x55, 0x15, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1w { z21.s, z29.s }, pn13/z, [x10, x21, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x4d, 0x08, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1w { z23.s, z31.s }, pn11/z, [x13, x8, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x5f, 0x1f, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1w { z23.s, z31.s }, pn15/z, [sp, xzr, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x08, 0x40, 0x40, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1w { z0.s, z8.s }, pn8/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x5d, 0x55, 0x45, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1w { z21.s, z29.s }, pn13/z, [x10, #10, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x4d, 0x48, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1w { z23.s, z31.s }, pn11/z, [x13, #-16, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x5f, 0x4f, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1w { z23.s, z31.s }, pn15/z, [sp, #-2, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x08, 0xc0, 0x00, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1w { z0.s, z4.s, z8.s, z12.s }, pn8/z, [x0, x0, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x59, 0xd5, 0x15, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1w { z17.s, z21.s, z25.s, z29.s }, pn13/z, [x10, x21, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0xbb, 0xcd, 0x08, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1w { z19.s, z23.s, z27.s, z31.s }, pn11/z, [x13, x8, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0xfb, 0xdf, 0x1f, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1w { z19.s, z23.s, z27.s, z31.s }, pn15/z, [sp, xzr, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x08, 0xc0, 0x40, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1w { z0.s, z4.s, z8.s, z12.s }, pn8/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x59, 0xd5, 0x45, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1w { z17.s, z21.s, z25.s, z29.s }, pn13/z, [x10, #20, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xbb, 0xcd, 0x48, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1w { z19.s, z23.s, z27.s, z31.s }, pn11/z, [x13, #-32, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xfb, 0xdf, 0x4f, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1w { z19.s, z23.s, z27.s, z31.s }, pn15/z, [sp, #-4, mul vl]"
diff --git a/tests/MC/AArch64/SME2/ldr.s.yaml b/tests/MC/AArch64/SME2/ldr.s.yaml
new file mode 100644
index 000000000..bbaa3c0bc
--- /dev/null
+++ b/tests/MC/AArch64/SME2/ldr.s.yaml
@@ -0,0 +1,40 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x1f, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr zt0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x40, 0x81, 0x1f, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr zt0, [x10]"
+
+  -
+    input:
+      bytes: [ 0xa0, 0x81, 0x1f, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr zt0, [x13]"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x83, 0x1f, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr zt0, [sp]"
diff --git a/tests/MC/AArch64/SME2/luti2.s.yaml b/tests/MC/AArch64/SME2/luti2.s.yaml
new file mode 100644
index 000000000..e4eacd904
--- /dev/null
+++ b/tests/MC/AArch64/SME2/luti2.s.yaml
@@ -0,0 +1,360 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x10, 0xcc, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti2 z0.h, zt0, z0[0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x51, 0xcd, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti2 z21.h, zt0, z10[5]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xd1, 0xcc, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti2 z23.h, zt0, z13[3]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xd3, 0xcf, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti2 z31.h, zt0, z31[15]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0xcc, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti2 z0.s, zt0, z0[0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x61, 0xcd, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti2 z21.s, zt0, z10[5]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xe1, 0xcc, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti2 z23.s, zt0, z13[3]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xe3, 0xcf, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti2 z31.s, zt0, z31[15]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0xcc, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti2 z0.b, zt0, z0[0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x41, 0xcd, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti2 z21.b, zt0, z10[5]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xc1, 0xcc, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti2 z23.b, zt0, z13[3]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xc3, 0xcf, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti2 z31.b, zt0, z31[15]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x50, 0x8c, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti2 { z0.h, z1.h }, zt0, z0[0]"
+
+  -
+    input:
+      bytes: [ 0x54, 0x51, 0x8d, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti2 { z20.h, z21.h }, zt0, z10[2]"
+
+  -
+    input:
+      bytes: [ 0xb6, 0xd1, 0x8c, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti2 { z22.h, z23.h }, zt0, z13[1]"
+
+  -
+    input:
+      bytes: [ 0xfe, 0xd3, 0x8f, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti2 { z30.h, z31.h }, zt0, z31[7]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0x8c, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti2 { z0.s, z1.s }, zt0, z0[0]"
+
+  -
+    input:
+      bytes: [ 0x54, 0x61, 0x8d, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti2 { z20.s, z21.s }, zt0, z10[2]"
+
+  -
+    input:
+      bytes: [ 0xb6, 0xe1, 0x8c, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti2 { z22.s, z23.s }, zt0, z13[1]"
+
+  -
+    input:
+      bytes: [ 0xfe, 0xe3, 0x8f, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti2 { z30.s, z31.s }, zt0, z31[7]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0x8c, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti2 { z0.b, z1.b }, zt0, z0[0]"
+
+  -
+    input:
+      bytes: [ 0x54, 0x41, 0x8d, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti2 { z20.b, z21.b }, zt0, z10[2]"
+
+  -
+    input:
+      bytes: [ 0xb6, 0xc1, 0x8c, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti2 { z22.b, z23.b }, zt0, z13[1]"
+
+  -
+    input:
+      bytes: [ 0xfe, 0xc3, 0x8f, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti2 { z30.b, z31.b }, zt0, z31[7]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x90, 0x8c, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti2 { z0.h - z3.h }, zt0, z0[0]"
+
+  -
+    input:
+      bytes: [ 0x54, 0x91, 0x8d, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti2 { z20.h - z23.h }, zt0, z10[1]"
+
+  -
+    input:
+      bytes: [ 0xb4, 0x91, 0x8c, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti2 { z20.h - z23.h }, zt0, z13[0]"
+
+  -
+    input:
+      bytes: [ 0xfc, 0x93, 0x8f, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti2 { z28.h - z31.h }, zt0, z31[3]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x8c, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti2 { z0.s - z3.s }, zt0, z0[0]"
+
+  -
+    input:
+      bytes: [ 0x54, 0xa1, 0x8d, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti2 { z20.s - z23.s }, zt0, z10[1]"
+
+  -
+    input:
+      bytes: [ 0xb4, 0xa1, 0x8c, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti2 { z20.s - z23.s }, zt0, z13[0]"
+
+  -
+    input:
+      bytes: [ 0xfc, 0xa3, 0x8f, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti2 { z28.s - z31.s }, zt0, z31[3]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x8c, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti2 { z0.b - z3.b }, zt0, z0[0]"
+
+  -
+    input:
+      bytes: [ 0x54, 0x81, 0x8d, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti2 { z20.b - z23.b }, zt0, z10[1]"
+
+  -
+    input:
+      bytes: [ 0xb4, 0x81, 0x8c, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti2 { z20.b - z23.b }, zt0, z13[0]"
+
+  -
+    input:
+      bytes: [ 0xfc, 0x83, 0x8f, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti2 { z28.b - z31.b }, zt0, z31[3]"
diff --git a/tests/MC/AArch64/SME2/luti4.s.yaml b/tests/MC/AArch64/SME2/luti4.s.yaml
new file mode 100644
index 000000000..f49adc8cf
--- /dev/null
+++ b/tests/MC/AArch64/SME2/luti4.s.yaml
@@ -0,0 +1,320 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x10, 0xca, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti4 z0.h, zt0, z0[0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x51, 0xcb, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti4 z21.h, zt0, z10[5]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xd1, 0xca, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti4 z23.h, zt0, z13[3]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xd3, 0xcb, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti4 z31.h, zt0, z31[7]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0xca, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti4 z0.s, zt0, z0[0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x61, 0xcb, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti4 z21.s, zt0, z10[5]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xe1, 0xca, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti4 z23.s, zt0, z13[3]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xe3, 0xcb, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti4 z31.s, zt0, z31[7]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0xca, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti4 z0.b, zt0, z0[0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x41, 0xcb, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti4 z21.b, zt0, z10[5]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xc1, 0xca, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti4 z23.b, zt0, z13[3]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xc3, 0xcb, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti4 z31.b, zt0, z31[7]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x50, 0x8a, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti4 { z0.h, z1.h }, zt0, z0[0]"
+
+  -
+    input:
+      bytes: [ 0x54, 0x51, 0x8b, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti4 { z20.h, z21.h }, zt0, z10[2]"
+
+  -
+    input:
+      bytes: [ 0xb6, 0xd1, 0x8a, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti4 { z22.h, z23.h }, zt0, z13[1]"
+
+  -
+    input:
+      bytes: [ 0xfe, 0xd3, 0x8b, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti4 { z30.h, z31.h }, zt0, z31[3]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0x8a, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti4 { z0.s, z1.s }, zt0, z0[0]"
+
+  -
+    input:
+      bytes: [ 0x54, 0x61, 0x8b, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti4 { z20.s, z21.s }, zt0, z10[2]"
+
+  -
+    input:
+      bytes: [ 0xb6, 0xe1, 0x8a, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti4 { z22.s, z23.s }, zt0, z13[1]"
+
+  -
+    input:
+      bytes: [ 0xfe, 0xe3, 0x8b, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti4 { z30.s, z31.s }, zt0, z31[3]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0x8a, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti4 { z0.b, z1.b }, zt0, z0[0]"
+
+  -
+    input:
+      bytes: [ 0x54, 0x41, 0x8b, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti4 { z20.b, z21.b }, zt0, z10[2]"
+
+  -
+    input:
+      bytes: [ 0xb6, 0xc1, 0x8a, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti4 { z22.b, z23.b }, zt0, z13[1]"
+
+  -
+    input:
+      bytes: [ 0xfe, 0xc3, 0x8b, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti4 { z30.b, z31.b }, zt0, z31[3]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x90, 0x8a, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti4 { z0.h - z3.h }, zt0, z0[0]"
+
+  -
+    input:
+      bytes: [ 0x54, 0x91, 0x8b, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti4 { z20.h - z23.h }, zt0, z10[1]"
+
+  -
+    input:
+      bytes: [ 0xb4, 0x91, 0x8a, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti4 { z20.h - z23.h }, zt0, z13[0]"
+
+  -
+    input:
+      bytes: [ 0xfc, 0x93, 0x8b, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti4 { z28.h - z31.h }, zt0, z31[1]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x8a, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti4 { z0.s - z3.s }, zt0, z0[0]"
+
+  -
+    input:
+      bytes: [ 0x54, 0xa1, 0x8b, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti4 { z20.s - z23.s }, zt0, z10[1]"
+
+  -
+    input:
+      bytes: [ 0xb4, 0xa1, 0x8a, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti4 { z20.s - z23.s }, zt0, z13[0]"
+
+  -
+    input:
+      bytes: [ 0xfc, 0xa3, 0x8b, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti4 { z28.s - z31.s }, zt0, z31[1]"
diff --git a/tests/MC/AArch64/SME2/mova.s.yaml b/tests/MC/AArch64/SME2/mova.s.yaml
new file mode 100644
index 000000000..a5bcb1605
--- /dev/null
+++ b/tests/MC/AArch64/SME2/mova.s.yaml
@@ -0,0 +1,9000 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x46, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.h, z1.h }, za0h.h[w12, 0:1]"
+
+  -
+    input:
+      bytes: [ 0x54, 0x40, 0x46, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z20.h, z21.h }, za0h.h[w14, 4:5]"
+
+  -
+    input:
+      bytes: [ 0xb6, 0x60, 0x46, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z22.h, z23.h }, za1h.h[w15, 2:3]"
+
+  -
+    input:
+      bytes: [ 0xfe, 0x60, 0x46, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z30.h, z31.h }, za1h.h[w15, 6:7]"
+
+  -
+    input:
+      bytes: [ 0x24, 0x00, 0x46, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z4.h, z5.h }, za0h.h[w12, 2:3]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x00, 0x46, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.h, z1.h }, za0h.h[w12, 2:3]"
+
+  -
+    input:
+      bytes: [ 0x78, 0x40, 0x46, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z24.h, z25.h }, za0h.h[w14, 6:7]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x00, 0x46, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.h, z1.h }, za1h.h[w12, 0:1]"
+
+  -
+    input:
+      bytes: [ 0x30, 0x40, 0x46, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z16.h, z17.h }, za0h.h[w14, 2:3]"
+
+  -
+    input:
+      bytes: [ 0xdc, 0x00, 0x46, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z28.h, z29.h }, za1h.h[w12, 4:5]"
+
+  -
+    input:
+      bytes: [ 0x22, 0x60, 0x46, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z2.h, z3.h }, za0h.h[w15, 2:3]"
+
+  -
+    input:
+      bytes: [ 0x86, 0x20, 0x46, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z6.h, z7.h }, za1h.h[w13, 0:1]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x46, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.h, z1.h }, za0h.h[w12, 0:1]"
+
+  -
+    input:
+      bytes: [ 0x54, 0x40, 0x46, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z20.h, z21.h }, za0h.h[w14, 4:5]"
+
+  -
+    input:
+      bytes: [ 0xb6, 0x60, 0x46, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z22.h, z23.h }, za1h.h[w15, 2:3]"
+
+  -
+    input:
+      bytes: [ 0xfe, 0x60, 0x46, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z30.h, z31.h }, za1h.h[w15, 6:7]"
+
+  -
+    input:
+      bytes: [ 0x24, 0x00, 0x46, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z4.h, z5.h }, za0h.h[w12, 2:3]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x00, 0x46, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.h, z1.h }, za0h.h[w12, 2:3]"
+
+  -
+    input:
+      bytes: [ 0x78, 0x40, 0x46, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z24.h, z25.h }, za0h.h[w14, 6:7]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x00, 0x46, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.h, z1.h }, za1h.h[w12, 0:1]"
+
+  -
+    input:
+      bytes: [ 0x30, 0x40, 0x46, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z16.h, z17.h }, za0h.h[w14, 2:3]"
+
+  -
+    input:
+      bytes: [ 0xdc, 0x00, 0x46, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z28.h, z29.h }, za1h.h[w12, 4:5]"
+
+  -
+    input:
+      bytes: [ 0x22, 0x60, 0x46, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z2.h, z3.h }, za0h.h[w15, 2:3]"
+
+  -
+    input:
+      bytes: [ 0x86, 0x20, 0x46, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z6.h, z7.h }, za1h.h[w13, 0:1]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x46, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.h, z1.h }, za0v.h[w12, 0:1]"
+
+  -
+    input:
+      bytes: [ 0x54, 0xc0, 0x46, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z20.h, z21.h }, za0v.h[w14, 4:5]"
+
+  -
+    input:
+      bytes: [ 0xb6, 0xe0, 0x46, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z22.h, z23.h }, za1v.h[w15, 2:3]"
+
+  -
+    input:
+      bytes: [ 0xfe, 0xe0, 0x46, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z30.h, z31.h }, za1v.h[w15, 6:7]"
+
+  -
+    input:
+      bytes: [ 0x24, 0x80, 0x46, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z4.h, z5.h }, za0v.h[w12, 2:3]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x46, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.h, z1.h }, za0v.h[w12, 2:3]"
+
+  -
+    input:
+      bytes: [ 0x78, 0xc0, 0x46, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z24.h, z25.h }, za0v.h[w14, 6:7]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x80, 0x46, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.h, z1.h }, za1v.h[w12, 0:1]"
+
+  -
+    input:
+      bytes: [ 0x30, 0xc0, 0x46, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z16.h, z17.h }, za0v.h[w14, 2:3]"
+
+  -
+    input:
+      bytes: [ 0xdc, 0x80, 0x46, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z28.h, z29.h }, za1v.h[w12, 4:5]"
+
+  -
+    input:
+      bytes: [ 0x22, 0xe0, 0x46, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z2.h, z3.h }, za0v.h[w15, 2:3]"
+
+  -
+    input:
+      bytes: [ 0x86, 0xa0, 0x46, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z6.h, z7.h }, za1v.h[w13, 0:1]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x46, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.h, z1.h }, za0v.h[w12, 0:1]"
+
+  -
+    input:
+      bytes: [ 0x54, 0xc0, 0x46, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z20.h, z21.h }, za0v.h[w14, 4:5]"
+
+  -
+    input:
+      bytes: [ 0xb6, 0xe0, 0x46, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z22.h, z23.h }, za1v.h[w15, 2:3]"
+
+  -
+    input:
+      bytes: [ 0xfe, 0xe0, 0x46, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z30.h, z31.h }, za1v.h[w15, 6:7]"
+
+  -
+    input:
+      bytes: [ 0x24, 0x80, 0x46, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z4.h, z5.h }, za0v.h[w12, 2:3]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x46, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.h, z1.h }, za0v.h[w12, 2:3]"
+
+  -
+    input:
+      bytes: [ 0x78, 0xc0, 0x46, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z24.h, z25.h }, za0v.h[w14, 6:7]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x80, 0x46, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.h, z1.h }, za1v.h[w12, 0:1]"
+
+  -
+    input:
+      bytes: [ 0x30, 0xc0, 0x46, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z16.h, z17.h }, za0v.h[w14, 2:3]"
+
+  -
+    input:
+      bytes: [ 0xdc, 0x80, 0x46, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z28.h, z29.h }, za1v.h[w12, 4:5]"
+
+  -
+    input:
+      bytes: [ 0x22, 0xe0, 0x46, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z2.h, z3.h }, za0v.h[w15, 2:3]"
+
+  -
+    input:
+      bytes: [ 0x86, 0xa0, 0x46, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z6.h, z7.h }, za1v.h[w13, 0:1]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x44, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.h[w12, 0:1], { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x45, 0x41, 0x44, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1h.h[w14, 2:3], { z10.h, z11.h }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x61, 0x44, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1h.h[w15, 6:7], { z12.h, z13.h }"
+
+  -
+    input:
+      bytes: [ 0xc7, 0x63, 0x44, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1h.h[w15, 6:7], { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x05, 0x02, 0x44, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1h.h[w12, 2:3], { z16.h, z17.h }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0x44, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.h[w12, 2:3], { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x40, 0x42, 0x44, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.h[w14, 0:1], { z18.h, z19.h }"
+
+  -
+    input:
+      bytes: [ 0x80, 0x01, 0x44, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.h[w12, 0:1], { z12.h, z13.h }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x40, 0x44, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.h[w14, 2:3], { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x02, 0x44, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1h.h[w12, 2:3], { z22.h, z23.h }"
+
+  -
+    input:
+      bytes: [ 0x02, 0x61, 0x44, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.h[w15, 4:5], { z8.h, z9.h }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x21, 0x44, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1h.h[w13, 6:7], { z12.h, z13.h }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x44, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.h[w12, 0:1], { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x45, 0x41, 0x44, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1h.h[w14, 2:3], { z10.h, z11.h }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x61, 0x44, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1h.h[w15, 6:7], { z12.h, z13.h }"
+
+  -
+    input:
+      bytes: [ 0xc7, 0x63, 0x44, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1h.h[w15, 6:7], { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x05, 0x02, 0x44, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1h.h[w12, 2:3], { z16.h, z17.h }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0x44, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.h[w12, 2:3], { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x40, 0x42, 0x44, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.h[w14, 0:1], { z18.h, z19.h }"
+
+  -
+    input:
+      bytes: [ 0x80, 0x01, 0x44, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.h[w12, 0:1], { z12.h, z13.h }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x40, 0x44, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.h[w14, 2:3], { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x02, 0x44, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1h.h[w12, 2:3], { z22.h, z23.h }"
+
+  -
+    input:
+      bytes: [ 0x02, 0x61, 0x44, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.h[w15, 4:5], { z8.h, z9.h }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x21, 0x44, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1h.h[w13, 6:7], { z12.h, z13.h }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x44, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.h[w12, 0:1], { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x45, 0xc1, 0x44, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1v.h[w14, 2:3], { z10.h, z11.h }"
+
+  -
+    input:
+      bytes: [ 0x87, 0xe1, 0x44, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1v.h[w15, 6:7], { z12.h, z13.h }"
+
+  -
+    input:
+      bytes: [ 0xc7, 0xe3, 0x44, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1v.h[w15, 6:7], { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x05, 0x82, 0x44, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1v.h[w12, 2:3], { z16.h, z17.h }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x80, 0x44, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.h[w12, 2:3], { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x40, 0xc2, 0x44, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.h[w14, 0:1], { z18.h, z19.h }"
+
+  -
+    input:
+      bytes: [ 0x80, 0x81, 0x44, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.h[w12, 0:1], { z12.h, z13.h }"
+
+  -
+    input:
+      bytes: [ 0x01, 0xc0, 0x44, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.h[w14, 2:3], { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x82, 0x44, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1v.h[w12, 2:3], { z22.h, z23.h }"
+
+  -
+    input:
+      bytes: [ 0x02, 0xe1, 0x44, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.h[w15, 4:5], { z8.h, z9.h }"
+
+  -
+    input:
+      bytes: [ 0x87, 0xa1, 0x44, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1v.h[w13, 6:7], { z12.h, z13.h }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x44, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.h[w12, 0:1], { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x45, 0xc1, 0x44, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1v.h[w14, 2:3], { z10.h, z11.h }"
+
+  -
+    input:
+      bytes: [ 0x87, 0xe1, 0x44, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1v.h[w15, 6:7], { z12.h, z13.h }"
+
+  -
+    input:
+      bytes: [ 0xc7, 0xe3, 0x44, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1v.h[w15, 6:7], { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x05, 0x82, 0x44, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1v.h[w12, 2:3], { z16.h, z17.h }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x80, 0x44, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.h[w12, 2:3], { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x40, 0xc2, 0x44, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.h[w14, 0:1], { z18.h, z19.h }"
+
+  -
+    input:
+      bytes: [ 0x80, 0x81, 0x44, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.h[w12, 0:1], { z12.h, z13.h }"
+
+  -
+    input:
+      bytes: [ 0x01, 0xc0, 0x44, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.h[w14, 2:3], { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x82, 0x44, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1v.h[w12, 2:3], { z22.h, z23.h }"
+
+  -
+    input:
+      bytes: [ 0x02, 0xe1, 0x44, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.h[w15, 4:5], { z8.h, z9.h }"
+
+  -
+    input:
+      bytes: [ 0x87, 0xa1, 0x44, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1v.h[w13, 6:7], { z12.h, z13.h }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x86, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.s, z1.s }, za0h.s[w12, 0:1]"
+
+  -
+    input:
+      bytes: [ 0x54, 0x40, 0x86, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z20.s, z21.s }, za1h.s[w14, 0:1]"
+
+  -
+    input:
+      bytes: [ 0xb6, 0x60, 0x86, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z22.s, z23.s }, za2h.s[w15, 2:3]"
+
+  -
+    input:
+      bytes: [ 0xfe, 0x60, 0x86, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z30.s, z31.s }, za3h.s[w15, 2:3]"
+
+  -
+    input:
+      bytes: [ 0x24, 0x00, 0x86, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z4.s, z5.s }, za0h.s[w12, 2:3]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x00, 0x86, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.s, z1.s }, za0h.s[w12, 2:3]"
+
+  -
+    input:
+      bytes: [ 0x78, 0x40, 0x86, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z24.s, z25.s }, za1h.s[w14, 2:3]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x00, 0x86, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.s, z1.s }, za2h.s[w12, 0:1]"
+
+  -
+    input:
+      bytes: [ 0x30, 0x40, 0x86, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z16.s, z17.s }, za0h.s[w14, 2:3]"
+
+  -
+    input:
+      bytes: [ 0xdc, 0x00, 0x86, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z28.s, z29.s }, za3h.s[w12, 0:1]"
+
+  -
+    input:
+      bytes: [ 0x22, 0x60, 0x86, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z2.s, z3.s }, za0h.s[w15, 2:3]"
+
+  -
+    input:
+      bytes: [ 0x86, 0x20, 0x86, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z6.s, z7.s }, za2h.s[w13, 0:1]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x86, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.s, z1.s }, za0h.s[w12, 0:1]"
+
+  -
+    input:
+      bytes: [ 0x54, 0x40, 0x86, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z20.s, z21.s }, za1h.s[w14, 0:1]"
+
+  -
+    input:
+      bytes: [ 0xb6, 0x60, 0x86, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z22.s, z23.s }, za2h.s[w15, 2:3]"
+
+  -
+    input:
+      bytes: [ 0xfe, 0x60, 0x86, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z30.s, z31.s }, za3h.s[w15, 2:3]"
+
+  -
+    input:
+      bytes: [ 0x24, 0x00, 0x86, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z4.s, z5.s }, za0h.s[w12, 2:3]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x00, 0x86, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.s, z1.s }, za0h.s[w12, 2:3]"
+
+  -
+    input:
+      bytes: [ 0x78, 0x40, 0x86, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z24.s, z25.s }, za1h.s[w14, 2:3]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x00, 0x86, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.s, z1.s }, za2h.s[w12, 0:1]"
+
+  -
+    input:
+      bytes: [ 0x30, 0x40, 0x86, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z16.s, z17.s }, za0h.s[w14, 2:3]"
+
+  -
+    input:
+      bytes: [ 0xdc, 0x00, 0x86, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z28.s, z29.s }, za3h.s[w12, 0:1]"
+
+  -
+    input:
+      bytes: [ 0x22, 0x60, 0x86, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z2.s, z3.s }, za0h.s[w15, 2:3]"
+
+  -
+    input:
+      bytes: [ 0x86, 0x20, 0x86, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z6.s, z7.s }, za2h.s[w13, 0:1]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x86, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.s, z1.s }, za0v.s[w12, 0:1]"
+
+  -
+    input:
+      bytes: [ 0x54, 0xc0, 0x86, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z20.s, z21.s }, za1v.s[w14, 0:1]"
+
+  -
+    input:
+      bytes: [ 0xb6, 0xe0, 0x86, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z22.s, z23.s }, za2v.s[w15, 2:3]"
+
+  -
+    input:
+      bytes: [ 0xfe, 0xe0, 0x86, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z30.s, z31.s }, za3v.s[w15, 2:3]"
+
+  -
+    input:
+      bytes: [ 0x24, 0x80, 0x86, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z4.s, z5.s }, za0v.s[w12, 2:3]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x86, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.s, z1.s }, za0v.s[w12, 2:3]"
+
+  -
+    input:
+      bytes: [ 0x78, 0xc0, 0x86, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z24.s, z25.s }, za1v.s[w14, 2:3]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x80, 0x86, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.s, z1.s }, za2v.s[w12, 0:1]"
+
+  -
+    input:
+      bytes: [ 0x30, 0xc0, 0x86, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z16.s, z17.s }, za0v.s[w14, 2:3]"
+
+  -
+    input:
+      bytes: [ 0xdc, 0x80, 0x86, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z28.s, z29.s }, za3v.s[w12, 0:1]"
+
+  -
+    input:
+      bytes: [ 0x22, 0xe0, 0x86, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z2.s, z3.s }, za0v.s[w15, 2:3]"
+
+  -
+    input:
+      bytes: [ 0x86, 0xa0, 0x86, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z6.s, z7.s }, za2v.s[w13, 0:1]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x86, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.s, z1.s }, za0v.s[w12, 0:1]"
+
+  -
+    input:
+      bytes: [ 0x54, 0xc0, 0x86, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z20.s, z21.s }, za1v.s[w14, 0:1]"
+
+  -
+    input:
+      bytes: [ 0xb6, 0xe0, 0x86, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z22.s, z23.s }, za2v.s[w15, 2:3]"
+
+  -
+    input:
+      bytes: [ 0xfe, 0xe0, 0x86, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z30.s, z31.s }, za3v.s[w15, 2:3]"
+
+  -
+    input:
+      bytes: [ 0x24, 0x80, 0x86, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z4.s, z5.s }, za0v.s[w12, 2:3]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x86, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.s, z1.s }, za0v.s[w12, 2:3]"
+
+  -
+    input:
+      bytes: [ 0x78, 0xc0, 0x86, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z24.s, z25.s }, za1v.s[w14, 2:3]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x80, 0x86, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.s, z1.s }, za2v.s[w12, 0:1]"
+
+  -
+    input:
+      bytes: [ 0x30, 0xc0, 0x86, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z16.s, z17.s }, za0v.s[w14, 2:3]"
+
+  -
+    input:
+      bytes: [ 0xdc, 0x80, 0x86, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z28.s, z29.s }, za3v.s[w12, 0:1]"
+
+  -
+    input:
+      bytes: [ 0x22, 0xe0, 0x86, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z2.s, z3.s }, za0v.s[w15, 2:3]"
+
+  -
+    input:
+      bytes: [ 0x86, 0xa0, 0x86, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z6.s, z7.s }, za2v.s[w13, 0:1]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x84, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.s[w12, 0:1], { z0.s, z1.s }"
+
+  -
+    input:
+      bytes: [ 0x45, 0x41, 0x84, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za2h.s[w14, 2:3], { z10.s, z11.s }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x61, 0x84, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za3h.s[w15, 2:3], { z12.s, z13.s }"
+
+  -
+    input:
+      bytes: [ 0xc7, 0x63, 0x84, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za3h.s[w15, 2:3], { z30.s, z31.s }"
+
+  -
+    input:
+      bytes: [ 0x05, 0x02, 0x84, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za2h.s[w12, 2:3], { z16.s, z17.s }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0x84, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.s[w12, 2:3], { z0.s, z1.s }"
+
+  -
+    input:
+      bytes: [ 0x40, 0x42, 0x84, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.s[w14, 0:1], { z18.s, z19.s }"
+
+  -
+    input:
+      bytes: [ 0x80, 0x01, 0x84, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.s[w12, 0:1], { z12.s, z13.s }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x40, 0x84, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.s[w14, 2:3], { z0.s, z1.s }"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x02, 0x84, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za2h.s[w12, 2:3], { z22.s, z23.s }"
+
+  -
+    input:
+      bytes: [ 0x02, 0x61, 0x84, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1h.s[w15, 0:1], { z8.s, z9.s }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x21, 0x84, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za3h.s[w13, 2:3], { z12.s, z13.s }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x84, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.s[w12, 0:1], { z0.s, z1.s }"
+
+  -
+    input:
+      bytes: [ 0x45, 0x41, 0x84, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za2h.s[w14, 2:3], { z10.s, z11.s }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x61, 0x84, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za3h.s[w15, 2:3], { z12.s, z13.s }"
+
+  -
+    input:
+      bytes: [ 0xc7, 0x63, 0x84, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za3h.s[w15, 2:3], { z30.s, z31.s }"
+
+  -
+    input:
+      bytes: [ 0x05, 0x02, 0x84, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za2h.s[w12, 2:3], { z16.s, z17.s }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0x84, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.s[w12, 2:3], { z0.s, z1.s }"
+
+  -
+    input:
+      bytes: [ 0x40, 0x42, 0x84, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.s[w14, 0:1], { z18.s, z19.s }"
+
+  -
+    input:
+      bytes: [ 0x80, 0x01, 0x84, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.s[w12, 0:1], { z12.s, z13.s }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x40, 0x84, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.s[w14, 2:3], { z0.s, z1.s }"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x02, 0x84, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za2h.s[w12, 2:3], { z22.s, z23.s }"
+
+  -
+    input:
+      bytes: [ 0x02, 0x61, 0x84, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1h.s[w15, 0:1], { z8.s, z9.s }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x21, 0x84, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za3h.s[w13, 2:3], { z12.s, z13.s }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x84, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.s[w12, 0:1], { z0.s, z1.s }"
+
+  -
+    input:
+      bytes: [ 0x45, 0xc1, 0x84, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za2v.s[w14, 2:3], { z10.s, z11.s }"
+
+  -
+    input:
+      bytes: [ 0x87, 0xe1, 0x84, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za3v.s[w15, 2:3], { z12.s, z13.s }"
+
+  -
+    input:
+      bytes: [ 0xc7, 0xe3, 0x84, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za3v.s[w15, 2:3], { z30.s, z31.s }"
+
+  -
+    input:
+      bytes: [ 0x05, 0x82, 0x84, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za2v.s[w12, 2:3], { z16.s, z17.s }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x80, 0x84, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.s[w12, 2:3], { z0.s, z1.s }"
+
+  -
+    input:
+      bytes: [ 0x40, 0xc2, 0x84, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.s[w14, 0:1], { z18.s, z19.s }"
+
+  -
+    input:
+      bytes: [ 0x80, 0x81, 0x84, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.s[w12, 0:1], { z12.s, z13.s }"
+
+  -
+    input:
+      bytes: [ 0x01, 0xc0, 0x84, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.s[w14, 2:3], { z0.s, z1.s }"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x82, 0x84, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za2v.s[w12, 2:3], { z22.s, z23.s }"
+
+  -
+    input:
+      bytes: [ 0x02, 0xe1, 0x84, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1v.s[w15, 0:1], { z8.s, z9.s }"
+
+  -
+    input:
+      bytes: [ 0x87, 0xa1, 0x84, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za3v.s[w13, 2:3], { z12.s, z13.s }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x84, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.s[w12, 0:1], { z0.s, z1.s }"
+
+  -
+    input:
+      bytes: [ 0x45, 0xc1, 0x84, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za2v.s[w14, 2:3], { z10.s, z11.s }"
+
+  -
+    input:
+      bytes: [ 0x87, 0xe1, 0x84, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za3v.s[w15, 2:3], { z12.s, z13.s }"
+
+  -
+    input:
+      bytes: [ 0xc7, 0xe3, 0x84, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za3v.s[w15, 2:3], { z30.s, z31.s }"
+
+  -
+    input:
+      bytes: [ 0x05, 0x82, 0x84, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za2v.s[w12, 2:3], { z16.s, z17.s }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x80, 0x84, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.s[w12, 2:3], { z0.s, z1.s }"
+
+  -
+    input:
+      bytes: [ 0x40, 0xc2, 0x84, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.s[w14, 0:1], { z18.s, z19.s }"
+
+  -
+    input:
+      bytes: [ 0x80, 0x81, 0x84, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.s[w12, 0:1], { z12.s, z13.s }"
+
+  -
+    input:
+      bytes: [ 0x01, 0xc0, 0x84, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.s[w14, 2:3], { z0.s, z1.s }"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x82, 0x84, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za2v.s[w12, 2:3], { z22.s, z23.s }"
+
+  -
+    input:
+      bytes: [ 0x02, 0xe1, 0x84, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1v.s[w15, 0:1], { z8.s, z9.s }"
+
+  -
+    input:
+      bytes: [ 0x87, 0xa1, 0x84, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za3v.s[w13, 2:3], { z12.s, z13.s }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0xc6, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.d, z1.d }, za0h.d[w12, 0:1]"
+
+  -
+    input:
+      bytes: [ 0x54, 0x40, 0xc6, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z20.d, z21.d }, za2h.d[w14, 0:1]"
+
+  -
+    input:
+      bytes: [ 0xb6, 0x60, 0xc6, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z22.d, z23.d }, za5h.d[w15, 0:1]"
+
+  -
+    input:
+      bytes: [ 0xfe, 0x60, 0xc6, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z30.d, z31.d }, za7h.d[w15, 0:1]"
+
+  -
+    input:
+      bytes: [ 0x24, 0x00, 0xc6, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z4.d, z5.d }, za1h.d[w12, 0:1]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x00, 0xc6, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.d, z1.d }, za1h.d[w12, 0:1]"
+
+  -
+    input:
+      bytes: [ 0x78, 0x40, 0xc6, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z24.d, z25.d }, za3h.d[w14, 0:1]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x00, 0xc6, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.d, z1.d }, za4h.d[w12, 0:1]"
+
+  -
+    input:
+      bytes: [ 0x30, 0x40, 0xc6, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z16.d, z17.d }, za1h.d[w14, 0:1]"
+
+  -
+    input:
+      bytes: [ 0xdc, 0x00, 0xc6, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z28.d, z29.d }, za6h.d[w12, 0:1]"
+
+  -
+    input:
+      bytes: [ 0x22, 0x60, 0xc6, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z2.d, z3.d }, za1h.d[w15, 0:1]"
+
+  -
+    input:
+      bytes: [ 0x86, 0x20, 0xc6, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z6.d, z7.d }, za4h.d[w13, 0:1]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0xc6, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.d, z1.d }, za0h.d[w12, 0:1]"
+
+  -
+    input:
+      bytes: [ 0x54, 0x40, 0xc6, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z20.d, z21.d }, za2h.d[w14, 0:1]"
+
+  -
+    input:
+      bytes: [ 0xb6, 0x60, 0xc6, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z22.d, z23.d }, za5h.d[w15, 0:1]"
+
+  -
+    input:
+      bytes: [ 0xfe, 0x60, 0xc6, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z30.d, z31.d }, za7h.d[w15, 0:1]"
+
+  -
+    input:
+      bytes: [ 0x24, 0x00, 0xc6, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z4.d, z5.d }, za1h.d[w12, 0:1]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x00, 0xc6, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.d, z1.d }, za1h.d[w12, 0:1]"
+
+  -
+    input:
+      bytes: [ 0x78, 0x40, 0xc6, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z24.d, z25.d }, za3h.d[w14, 0:1]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x00, 0xc6, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.d, z1.d }, za4h.d[w12, 0:1]"
+
+  -
+    input:
+      bytes: [ 0x30, 0x40, 0xc6, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z16.d, z17.d }, za1h.d[w14, 0:1]"
+
+  -
+    input:
+      bytes: [ 0xdc, 0x00, 0xc6, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z28.d, z29.d }, za6h.d[w12, 0:1]"
+
+  -
+    input:
+      bytes: [ 0x22, 0x60, 0xc6, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z2.d, z3.d }, za1h.d[w15, 0:1]"
+
+  -
+    input:
+      bytes: [ 0x86, 0x20, 0xc6, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z6.d, z7.d }, za4h.d[w13, 0:1]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xc6, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.d, z1.d }, za0v.d[w12, 0:1]"
+
+  -
+    input:
+      bytes: [ 0x54, 0xc0, 0xc6, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z20.d, z21.d }, za2v.d[w14, 0:1]"
+
+  -
+    input:
+      bytes: [ 0xb6, 0xe0, 0xc6, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z22.d, z23.d }, za5v.d[w15, 0:1]"
+
+  -
+    input:
+      bytes: [ 0xfe, 0xe0, 0xc6, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z30.d, z31.d }, za7v.d[w15, 0:1]"
+
+  -
+    input:
+      bytes: [ 0x24, 0x80, 0xc6, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z4.d, z5.d }, za1v.d[w12, 0:1]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0xc6, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.d, z1.d }, za1v.d[w12, 0:1]"
+
+  -
+    input:
+      bytes: [ 0x78, 0xc0, 0xc6, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z24.d, z25.d }, za3v.d[w14, 0:1]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x80, 0xc6, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.d, z1.d }, za4v.d[w12, 0:1]"
+
+  -
+    input:
+      bytes: [ 0x30, 0xc0, 0xc6, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z16.d, z17.d }, za1v.d[w14, 0:1]"
+
+  -
+    input:
+      bytes: [ 0xdc, 0x80, 0xc6, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z28.d, z29.d }, za6v.d[w12, 0:1]"
+
+  -
+    input:
+      bytes: [ 0x22, 0xe0, 0xc6, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z2.d, z3.d }, za1v.d[w15, 0:1]"
+
+  -
+    input:
+      bytes: [ 0x86, 0xa0, 0xc6, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z6.d, z7.d }, za4v.d[w13, 0:1]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xc6, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.d, z1.d }, za0v.d[w12, 0:1]"
+
+  -
+    input:
+      bytes: [ 0x54, 0xc0, 0xc6, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z20.d, z21.d }, za2v.d[w14, 0:1]"
+
+  -
+    input:
+      bytes: [ 0xb6, 0xe0, 0xc6, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z22.d, z23.d }, za5v.d[w15, 0:1]"
+
+  -
+    input:
+      bytes: [ 0xfe, 0xe0, 0xc6, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z30.d, z31.d }, za7v.d[w15, 0:1]"
+
+  -
+    input:
+      bytes: [ 0x24, 0x80, 0xc6, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z4.d, z5.d }, za1v.d[w12, 0:1]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0xc6, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.d, z1.d }, za1v.d[w12, 0:1]"
+
+  -
+    input:
+      bytes: [ 0x78, 0xc0, 0xc6, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z24.d, z25.d }, za3v.d[w14, 0:1]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x80, 0xc6, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.d, z1.d }, za4v.d[w12, 0:1]"
+
+  -
+    input:
+      bytes: [ 0x30, 0xc0, 0xc6, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z16.d, z17.d }, za1v.d[w14, 0:1]"
+
+  -
+    input:
+      bytes: [ 0xdc, 0x80, 0xc6, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z28.d, z29.d }, za6v.d[w12, 0:1]"
+
+  -
+    input:
+      bytes: [ 0x22, 0xe0, 0xc6, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z2.d, z3.d }, za1v.d[w15, 0:1]"
+
+  -
+    input:
+      bytes: [ 0x86, 0xa0, 0xc6, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z6.d, z7.d }, za4v.d[w13, 0:1]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x08, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.d, z1.d }, za.d[w8, 0, vgx2]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x08, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.d, z1.d }, za.d[w8, 0, vgx2]"
+
+  -
+    input:
+      bytes: [ 0x54, 0x48, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z20.d, z21.d }, za.d[w10, 2, vgx2]"
+
+  -
+    input:
+      bytes: [ 0x54, 0x48, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z20.d, z21.d }, za.d[w10, 2, vgx2]"
+
+  -
+    input:
+      bytes: [ 0xb6, 0x68, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z22.d, z23.d }, za.d[w11, 5, vgx2]"
+
+  -
+    input:
+      bytes: [ 0xb6, 0x68, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z22.d, z23.d }, za.d[w11, 5, vgx2]"
+
+  -
+    input:
+      bytes: [ 0xfe, 0x68, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z30.d, z31.d }, za.d[w11, 7, vgx2]"
+
+  -
+    input:
+      bytes: [ 0xfe, 0x68, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z30.d, z31.d }, za.d[w11, 7, vgx2]"
+
+  -
+    input:
+      bytes: [ 0x24, 0x08, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z4.d, z5.d }, za.d[w8, 1, vgx2]"
+
+  -
+    input:
+      bytes: [ 0x24, 0x08, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z4.d, z5.d }, za.d[w8, 1, vgx2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x08, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.d, z1.d }, za.d[w8, 1, vgx2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x08, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.d, z1.d }, za.d[w8, 1, vgx2]"
+
+  -
+    input:
+      bytes: [ 0x78, 0x48, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z24.d, z25.d }, za.d[w10, 3, vgx2]"
+
+  -
+    input:
+      bytes: [ 0x78, 0x48, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z24.d, z25.d }, za.d[w10, 3, vgx2]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x08, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.d, z1.d }, za.d[w8, 4, vgx2]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x08, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.d, z1.d }, za.d[w8, 4, vgx2]"
+
+  -
+    input:
+      bytes: [ 0x30, 0x48, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z16.d, z17.d }, za.d[w10, 1, vgx2]"
+
+  -
+    input:
+      bytes: [ 0x30, 0x48, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z16.d, z17.d }, za.d[w10, 1, vgx2]"
+
+  -
+    input:
+      bytes: [ 0xdc, 0x08, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z28.d, z29.d }, za.d[w8, 6, vgx2]"
+
+  -
+    input:
+      bytes: [ 0xdc, 0x08, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z28.d, z29.d }, za.d[w8, 6, vgx2]"
+
+  -
+    input:
+      bytes: [ 0x22, 0x68, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z2.d, z3.d }, za.d[w11, 1, vgx2]"
+
+  -
+    input:
+      bytes: [ 0x22, 0x68, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z2.d, z3.d }, za.d[w11, 1, vgx2]"
+
+  -
+    input:
+      bytes: [ 0x86, 0x28, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z6.d, z7.d }, za.d[w9, 4, vgx2]"
+
+  -
+    input:
+      bytes: [ 0x86, 0x28, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z6.d, z7.d }, za.d[w9, 4, vgx2]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x08, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.d, z1.d }, za.d[w8, 0, vgx2]"
+
+  -
+    input:
+      bytes: [ 0x54, 0x48, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z20.d, z21.d }, za.d[w10, 2, vgx2]"
+
+  -
+    input:
+      bytes: [ 0xb6, 0x68, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z22.d, z23.d }, za.d[w11, 5, vgx2]"
+
+  -
+    input:
+      bytes: [ 0xfe, 0x68, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z30.d, z31.d }, za.d[w11, 7, vgx2]"
+
+  -
+    input:
+      bytes: [ 0x24, 0x08, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z4.d, z5.d }, za.d[w8, 1, vgx2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x08, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.d, z1.d }, za.d[w8, 1, vgx2]"
+
+  -
+    input:
+      bytes: [ 0x78, 0x48, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z24.d, z25.d }, za.d[w10, 3, vgx2]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x08, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.d, z1.d }, za.d[w8, 4, vgx2]"
+
+  -
+    input:
+      bytes: [ 0x30, 0x48, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z16.d, z17.d }, za.d[w10, 1, vgx2]"
+
+  -
+    input:
+      bytes: [ 0xdc, 0x08, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z28.d, z29.d }, za.d[w8, 6, vgx2]"
+
+  -
+    input:
+      bytes: [ 0x22, 0x68, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z2.d, z3.d }, za.d[w11, 1, vgx2]"
+
+  -
+    input:
+      bytes: [ 0x86, 0x28, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z6.d, z7.d }, za.d[w9, 4, vgx2]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0xc4, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.d[w12, 0:1], { z0.d, z1.d }"
+
+  -
+    input:
+      bytes: [ 0x45, 0x41, 0xc4, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za5h.d[w14, 0:1], { z10.d, z11.d }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x61, 0xc4, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za7h.d[w15, 0:1], { z12.d, z13.d }"
+
+  -
+    input:
+      bytes: [ 0xc7, 0x63, 0xc4, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za7h.d[w15, 0:1], { z30.d, z31.d }"
+
+  -
+    input:
+      bytes: [ 0x05, 0x02, 0xc4, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za5h.d[w12, 0:1], { z16.d, z17.d }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0xc4, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1h.d[w12, 0:1], { z0.d, z1.d }"
+
+  -
+    input:
+      bytes: [ 0x40, 0x42, 0xc4, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.d[w14, 0:1], { z18.d, z19.d }"
+
+  -
+    input:
+      bytes: [ 0x80, 0x01, 0xc4, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.d[w12, 0:1], { z12.d, z13.d }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x40, 0xc4, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1h.d[w14, 0:1], { z0.d, z1.d }"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x02, 0xc4, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za5h.d[w12, 0:1], { z22.d, z23.d }"
+
+  -
+    input:
+      bytes: [ 0x02, 0x61, 0xc4, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za2h.d[w15, 0:1], { z8.d, z9.d }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x21, 0xc4, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za7h.d[w13, 0:1], { z12.d, z13.d }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0xc4, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.d[w12, 0:1], { z0.d, z1.d }"
+
+  -
+    input:
+      bytes: [ 0x45, 0x41, 0xc4, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za5h.d[w14, 0:1], { z10.d, z11.d }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x61, 0xc4, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za7h.d[w15, 0:1], { z12.d, z13.d }"
+
+  -
+    input:
+      bytes: [ 0xc7, 0x63, 0xc4, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za7h.d[w15, 0:1], { z30.d, z31.d }"
+
+  -
+    input:
+      bytes: [ 0x05, 0x02, 0xc4, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za5h.d[w12, 0:1], { z16.d, z17.d }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0xc4, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1h.d[w12, 0:1], { z0.d, z1.d }"
+
+  -
+    input:
+      bytes: [ 0x40, 0x42, 0xc4, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.d[w14, 0:1], { z18.d, z19.d }"
+
+  -
+    input:
+      bytes: [ 0x80, 0x01, 0xc4, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.d[w12, 0:1], { z12.d, z13.d }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x40, 0xc4, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1h.d[w14, 0:1], { z0.d, z1.d }"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x02, 0xc4, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za5h.d[w12, 0:1], { z22.d, z23.d }"
+
+  -
+    input:
+      bytes: [ 0x02, 0x61, 0xc4, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za2h.d[w15, 0:1], { z8.d, z9.d }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x21, 0xc4, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za7h.d[w13, 0:1], { z12.d, z13.d }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xc4, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.d[w12, 0:1], { z0.d, z1.d }"
+
+  -
+    input:
+      bytes: [ 0x45, 0xc1, 0xc4, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za5v.d[w14, 0:1], { z10.d, z11.d }"
+
+  -
+    input:
+      bytes: [ 0x87, 0xe1, 0xc4, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za7v.d[w15, 0:1], { z12.d, z13.d }"
+
+  -
+    input:
+      bytes: [ 0xc7, 0xe3, 0xc4, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za7v.d[w15, 0:1], { z30.d, z31.d }"
+
+  -
+    input:
+      bytes: [ 0x05, 0x82, 0xc4, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za5v.d[w12, 0:1], { z16.d, z17.d }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x80, 0xc4, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1v.d[w12, 0:1], { z0.d, z1.d }"
+
+  -
+    input:
+      bytes: [ 0x40, 0xc2, 0xc4, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.d[w14, 0:1], { z18.d, z19.d }"
+
+  -
+    input:
+      bytes: [ 0x80, 0x81, 0xc4, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.d[w12, 0:1], { z12.d, z13.d }"
+
+  -
+    input:
+      bytes: [ 0x01, 0xc0, 0xc4, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1v.d[w14, 0:1], { z0.d, z1.d }"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x82, 0xc4, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za5v.d[w12, 0:1], { z22.d, z23.d }"
+
+  -
+    input:
+      bytes: [ 0x02, 0xe1, 0xc4, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za2v.d[w15, 0:1], { z8.d, z9.d }"
+
+  -
+    input:
+      bytes: [ 0x87, 0xa1, 0xc4, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za7v.d[w13, 0:1], { z12.d, z13.d }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xc4, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.d[w12, 0:1], { z0.d, z1.d }"
+
+  -
+    input:
+      bytes: [ 0x45, 0xc1, 0xc4, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za5v.d[w14, 0:1], { z10.d, z11.d }"
+
+  -
+    input:
+      bytes: [ 0x87, 0xe1, 0xc4, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za7v.d[w15, 0:1], { z12.d, z13.d }"
+
+  -
+    input:
+      bytes: [ 0xc7, 0xe3, 0xc4, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za7v.d[w15, 0:1], { z30.d, z31.d }"
+
+  -
+    input:
+      bytes: [ 0x05, 0x82, 0xc4, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za5v.d[w12, 0:1], { z16.d, z17.d }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x80, 0xc4, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1v.d[w12, 0:1], { z0.d, z1.d }"
+
+  -
+    input:
+      bytes: [ 0x40, 0xc2, 0xc4, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.d[w14, 0:1], { z18.d, z19.d }"
+
+  -
+    input:
+      bytes: [ 0x80, 0x81, 0xc4, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.d[w12, 0:1], { z12.d, z13.d }"
+
+  -
+    input:
+      bytes: [ 0x01, 0xc0, 0xc4, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1v.d[w14, 0:1], { z0.d, z1.d }"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x82, 0xc4, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za5v.d[w12, 0:1], { z22.d, z23.d }"
+
+  -
+    input:
+      bytes: [ 0x02, 0xe1, 0xc4, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za2v.d[w15, 0:1], { z8.d, z9.d }"
+
+  -
+    input:
+      bytes: [ 0x87, 0xa1, 0xc4, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za7v.d[w13, 0:1], { z12.d, z13.d }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x08, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za.d[w8, 0, vgx2], { z0.d, z1.d }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x08, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za.d[w8, 0, vgx2], { z0.d, z1.d }"
+
+  -
+    input:
+      bytes: [ 0x45, 0x49, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za.d[w10, 5, vgx2], { z10.d, z11.d }"
+
+  -
+    input:
+      bytes: [ 0x45, 0x49, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za.d[w10, 5, vgx2], { z10.d, z11.d }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x69, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za.d[w11, 7, vgx2], { z12.d, z13.d }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x69, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za.d[w11, 7, vgx2], { z12.d, z13.d }"
+
+  -
+    input:
+      bytes: [ 0xc7, 0x6b, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za.d[w11, 7, vgx2], { z30.d, z31.d }"
+
+  -
+    input:
+      bytes: [ 0xc7, 0x6b, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za.d[w11, 7, vgx2], { z30.d, z31.d }"
+
+  -
+    input:
+      bytes: [ 0x05, 0x0a, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za.d[w8, 5, vgx2], { z16.d, z17.d }"
+
+  -
+    input:
+      bytes: [ 0x05, 0x0a, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za.d[w8, 5, vgx2], { z16.d, z17.d }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x08, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za.d[w8, 1, vgx2], { z0.d, z1.d }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x08, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za.d[w8, 1, vgx2], { z0.d, z1.d }"
+
+  -
+    input:
+      bytes: [ 0x40, 0x4a, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za.d[w10, 0, vgx2], { z18.d, z19.d }"
+
+  -
+    input:
+      bytes: [ 0x40, 0x4a, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za.d[w10, 0, vgx2], { z18.d, z19.d }"
+
+  -
+    input:
+      bytes: [ 0x80, 0x09, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za.d[w8, 0, vgx2], { z12.d, z13.d }"
+
+  -
+    input:
+      bytes: [ 0x80, 0x09, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za.d[w8, 0, vgx2], { z12.d, z13.d }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x48, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za.d[w10, 1, vgx2], { z0.d, z1.d }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x48, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za.d[w10, 1, vgx2], { z0.d, z1.d }"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x0a, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za.d[w8, 5, vgx2], { z22.d, z23.d }"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x0a, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za.d[w8, 5, vgx2], { z22.d, z23.d }"
+
+  -
+    input:
+      bytes: [ 0x02, 0x69, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za.d[w11, 2, vgx2], { z8.d, z9.d }"
+
+  -
+    input:
+      bytes: [ 0x02, 0x69, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za.d[w11, 2, vgx2], { z8.d, z9.d }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x29, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za.d[w9, 7, vgx2], { z12.d, z13.d }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x29, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za.d[w9, 7, vgx2], { z12.d, z13.d }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x08, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za.d[w8, 0, vgx2], { z0.d, z1.d }"
+
+  -
+    input:
+      bytes: [ 0x45, 0x49, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za.d[w10, 5, vgx2], { z10.d, z11.d }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x69, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za.d[w11, 7, vgx2], { z12.d, z13.d }"
+
+  -
+    input:
+      bytes: [ 0xc7, 0x6b, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za.d[w11, 7, vgx2], { z30.d, z31.d }"
+
+  -
+    input:
+      bytes: [ 0x05, 0x0a, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za.d[w8, 5, vgx2], { z16.d, z17.d }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x08, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za.d[w8, 1, vgx2], { z0.d, z1.d }"
+
+  -
+    input:
+      bytes: [ 0x40, 0x4a, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za.d[w10, 0, vgx2], { z18.d, z19.d }"
+
+  -
+    input:
+      bytes: [ 0x80, 0x09, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za.d[w8, 0, vgx2], { z12.d, z13.d }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x48, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za.d[w10, 1, vgx2], { z0.d, z1.d }"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x0a, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za.d[w8, 5, vgx2], { z22.d, z23.d }"
+
+  -
+    input:
+      bytes: [ 0x02, 0x69, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za.d[w11, 2, vgx2], { z8.d, z9.d }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x29, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za.d[w9, 7, vgx2], { z12.d, z13.d }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.b, z1.b }, za0h.b[w12, 0:1]"
+
+  -
+    input:
+      bytes: [ 0x54, 0x40, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z20.b, z21.b }, za0h.b[w14, 4:5]"
+
+  -
+    input:
+      bytes: [ 0xb6, 0x60, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z22.b, z23.b }, za0h.b[w15, 10:11]"
+
+  -
+    input:
+      bytes: [ 0xfe, 0x60, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z30.b, z31.b }, za0h.b[w15, 14:15]"
+
+  -
+    input:
+      bytes: [ 0x24, 0x00, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z4.b, z5.b }, za0h.b[w12, 2:3]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x00, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.b, z1.b }, za0h.b[w12, 2:3]"
+
+  -
+    input:
+      bytes: [ 0x78, 0x40, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z24.b, z25.b }, za0h.b[w14, 6:7]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x00, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.b, z1.b }, za0h.b[w12, 8:9]"
+
+  -
+    input:
+      bytes: [ 0x30, 0x40, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z16.b, z17.b }, za0h.b[w14, 2:3]"
+
+  -
+    input:
+      bytes: [ 0xdc, 0x00, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z28.b, z29.b }, za0h.b[w12, 12:13]"
+
+  -
+    input:
+      bytes: [ 0x22, 0x60, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z2.b, z3.b }, za0h.b[w15, 2:3]"
+
+  -
+    input:
+      bytes: [ 0x86, 0x20, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z6.b, z7.b }, za0h.b[w13, 8:9]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.b, z1.b }, za0h.b[w12, 0:1]"
+
+  -
+    input:
+      bytes: [ 0x54, 0x40, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z20.b, z21.b }, za0h.b[w14, 4:5]"
+
+  -
+    input:
+      bytes: [ 0xb6, 0x60, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z22.b, z23.b }, za0h.b[w15, 10:11]"
+
+  -
+    input:
+      bytes: [ 0xfe, 0x60, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z30.b, z31.b }, za0h.b[w15, 14:15]"
+
+  -
+    input:
+      bytes: [ 0x24, 0x00, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z4.b, z5.b }, za0h.b[w12, 2:3]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x00, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.b, z1.b }, za0h.b[w12, 2:3]"
+
+  -
+    input:
+      bytes: [ 0x78, 0x40, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z24.b, z25.b }, za0h.b[w14, 6:7]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x00, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.b, z1.b }, za0h.b[w12, 8:9]"
+
+  -
+    input:
+      bytes: [ 0x30, 0x40, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z16.b, z17.b }, za0h.b[w14, 2:3]"
+
+  -
+    input:
+      bytes: [ 0xdc, 0x00, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z28.b, z29.b }, za0h.b[w12, 12:13]"
+
+  -
+    input:
+      bytes: [ 0x22, 0x60, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z2.b, z3.b }, za0h.b[w15, 2:3]"
+
+  -
+    input:
+      bytes: [ 0x86, 0x20, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z6.b, z7.b }, za0h.b[w13, 8:9]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.b, z1.b }, za0v.b[w12, 0:1]"
+
+  -
+    input:
+      bytes: [ 0x54, 0xc0, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z20.b, z21.b }, za0v.b[w14, 4:5]"
+
+  -
+    input:
+      bytes: [ 0xb6, 0xe0, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z22.b, z23.b }, za0v.b[w15, 10:11]"
+
+  -
+    input:
+      bytes: [ 0xfe, 0xe0, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z30.b, z31.b }, za0v.b[w15, 14:15]"
+
+  -
+    input:
+      bytes: [ 0x24, 0x80, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z4.b, z5.b }, za0v.b[w12, 2:3]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.b, z1.b }, za0v.b[w12, 2:3]"
+
+  -
+    input:
+      bytes: [ 0x78, 0xc0, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z24.b, z25.b }, za0v.b[w14, 6:7]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x80, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.b, z1.b }, za0v.b[w12, 8:9]"
+
+  -
+    input:
+      bytes: [ 0x30, 0xc0, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z16.b, z17.b }, za0v.b[w14, 2:3]"
+
+  -
+    input:
+      bytes: [ 0xdc, 0x80, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z28.b, z29.b }, za0v.b[w12, 12:13]"
+
+  -
+    input:
+      bytes: [ 0x22, 0xe0, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z2.b, z3.b }, za0v.b[w15, 2:3]"
+
+  -
+    input:
+      bytes: [ 0x86, 0xa0, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z6.b, z7.b }, za0v.b[w13, 8:9]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.b, z1.b }, za0v.b[w12, 0:1]"
+
+  -
+    input:
+      bytes: [ 0x54, 0xc0, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z20.b, z21.b }, za0v.b[w14, 4:5]"
+
+  -
+    input:
+      bytes: [ 0xb6, 0xe0, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z22.b, z23.b }, za0v.b[w15, 10:11]"
+
+  -
+    input:
+      bytes: [ 0xfe, 0xe0, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z30.b, z31.b }, za0v.b[w15, 14:15]"
+
+  -
+    input:
+      bytes: [ 0x24, 0x80, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z4.b, z5.b }, za0v.b[w12, 2:3]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.b, z1.b }, za0v.b[w12, 2:3]"
+
+  -
+    input:
+      bytes: [ 0x78, 0xc0, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z24.b, z25.b }, za0v.b[w14, 6:7]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x80, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.b, z1.b }, za0v.b[w12, 8:9]"
+
+  -
+    input:
+      bytes: [ 0x30, 0xc0, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z16.b, z17.b }, za0v.b[w14, 2:3]"
+
+  -
+    input:
+      bytes: [ 0xdc, 0x80, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z28.b, z29.b }, za0v.b[w12, 12:13]"
+
+  -
+    input:
+      bytes: [ 0x22, 0xe0, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z2.b, z3.b }, za0v.b[w15, 2:3]"
+
+  -
+    input:
+      bytes: [ 0x86, 0xa0, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z6.b, z7.b }, za0v.b[w13, 8:9]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.b[w12, 0:1], { z0.b, z1.b }"
+
+  -
+    input:
+      bytes: [ 0x45, 0x41, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.b[w14, 10:11], { z10.b, z11.b }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x61, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.b[w15, 14:15], { z12.b, z13.b }"
+
+  -
+    input:
+      bytes: [ 0xc7, 0x63, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.b[w15, 14:15], { z30.b, z31.b }"
+
+  -
+    input:
+      bytes: [ 0x05, 0x02, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.b[w12, 10:11], { z16.b, z17.b }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.b[w12, 2:3], { z0.b, z1.b }"
+
+  -
+    input:
+      bytes: [ 0x40, 0x42, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.b[w14, 0:1], { z18.b, z19.b }"
+
+  -
+    input:
+      bytes: [ 0x80, 0x01, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.b[w12, 0:1], { z12.b, z13.b }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x40, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.b[w14, 2:3], { z0.b, z1.b }"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x02, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.b[w12, 10:11], { z22.b, z23.b }"
+
+  -
+    input:
+      bytes: [ 0x02, 0x61, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.b[w15, 4:5], { z8.b, z9.b }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x21, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.b[w13, 14:15], { z12.b, z13.b }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.b[w12, 0:1], { z0.b, z1.b }"
+
+  -
+    input:
+      bytes: [ 0x45, 0x41, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.b[w14, 10:11], { z10.b, z11.b }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x61, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.b[w15, 14:15], { z12.b, z13.b }"
+
+  -
+    input:
+      bytes: [ 0xc7, 0x63, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.b[w15, 14:15], { z30.b, z31.b }"
+
+  -
+    input:
+      bytes: [ 0x05, 0x02, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.b[w12, 10:11], { z16.b, z17.b }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.b[w12, 2:3], { z0.b, z1.b }"
+
+  -
+    input:
+      bytes: [ 0x40, 0x42, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.b[w14, 0:1], { z18.b, z19.b }"
+
+  -
+    input:
+      bytes: [ 0x80, 0x01, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.b[w12, 0:1], { z12.b, z13.b }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x40, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.b[w14, 2:3], { z0.b, z1.b }"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x02, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.b[w12, 10:11], { z22.b, z23.b }"
+
+  -
+    input:
+      bytes: [ 0x02, 0x61, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.b[w15, 4:5], { z8.b, z9.b }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x21, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.b[w13, 14:15], { z12.b, z13.b }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.b[w12, 0:1], { z0.b, z1.b }"
+
+  -
+    input:
+      bytes: [ 0x45, 0xc1, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.b[w14, 10:11], { z10.b, z11.b }"
+
+  -
+    input:
+      bytes: [ 0x87, 0xe1, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.b[w15, 14:15], { z12.b, z13.b }"
+
+  -
+    input:
+      bytes: [ 0xc7, 0xe3, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.b[w15, 14:15], { z30.b, z31.b }"
+
+  -
+    input:
+      bytes: [ 0x05, 0x82, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.b[w12, 10:11], { z16.b, z17.b }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x80, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.b[w12, 2:3], { z0.b, z1.b }"
+
+  -
+    input:
+      bytes: [ 0x40, 0xc2, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.b[w14, 0:1], { z18.b, z19.b }"
+
+  -
+    input:
+      bytes: [ 0x80, 0x81, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.b[w12, 0:1], { z12.b, z13.b }"
+
+  -
+    input:
+      bytes: [ 0x01, 0xc0, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.b[w14, 2:3], { z0.b, z1.b }"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x82, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.b[w12, 10:11], { z22.b, z23.b }"
+
+  -
+    input:
+      bytes: [ 0x02, 0xe1, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.b[w15, 4:5], { z8.b, z9.b }"
+
+  -
+    input:
+      bytes: [ 0x87, 0xa1, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.b[w13, 14:15], { z12.b, z13.b }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.b[w12, 0:1], { z0.b, z1.b }"
+
+  -
+    input:
+      bytes: [ 0x45, 0xc1, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.b[w14, 10:11], { z10.b, z11.b }"
+
+  -
+    input:
+      bytes: [ 0x87, 0xe1, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.b[w15, 14:15], { z12.b, z13.b }"
+
+  -
+    input:
+      bytes: [ 0xc7, 0xe3, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.b[w15, 14:15], { z30.b, z31.b }"
+
+  -
+    input:
+      bytes: [ 0x05, 0x82, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.b[w12, 10:11], { z16.b, z17.b }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x80, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.b[w12, 2:3], { z0.b, z1.b }"
+
+  -
+    input:
+      bytes: [ 0x40, 0xc2, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.b[w14, 0:1], { z18.b, z19.b }"
+
+  -
+    input:
+      bytes: [ 0x80, 0x81, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.b[w12, 0:1], { z12.b, z13.b }"
+
+  -
+    input:
+      bytes: [ 0x01, 0xc0, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.b[w14, 2:3], { z0.b, z1.b }"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x82, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.b[w12, 10:11], { z22.b, z23.b }"
+
+  -
+    input:
+      bytes: [ 0x02, 0xe1, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.b[w15, 4:5], { z8.b, z9.b }"
+
+  -
+    input:
+      bytes: [ 0x87, 0xa1, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.b[w13, 14:15], { z12.b, z13.b }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x04, 0x46, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.h - z3.h }, za0h.h[w12, 0:3]"
+
+  -
+    input:
+      bytes: [ 0x54, 0x44, 0x46, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z20.h - z23.h }, za1h.h[w14, 0:3]"
+
+  -
+    input:
+      bytes: [ 0x34, 0x64, 0x46, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z20.h - z23.h }, za0h.h[w15, 4:7]"
+
+  -
+    input:
+      bytes: [ 0x7c, 0x64, 0x46, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z28.h - z31.h }, za1h.h[w15, 4:7]"
+
+  -
+    input:
+      bytes: [ 0x24, 0x04, 0x46, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z4.h - z7.h }, za0h.h[w12, 4:7]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x04, 0x46, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.h - z3.h }, za0h.h[w12, 4:7]"
+
+  -
+    input:
+      bytes: [ 0x78, 0x44, 0x46, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z24.h - z27.h }, za1h.h[w14, 4:7]"
+
+  -
+    input:
+      bytes: [ 0x30, 0x44, 0x46, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z16.h - z19.h }, za0h.h[w14, 4:7]"
+
+  -
+    input:
+      bytes: [ 0x5c, 0x04, 0x46, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z28.h - z31.h }, za1h.h[w12, 0:3]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x64, 0x46, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.h - z3.h }, za0h.h[w15, 4:7]"
+
+  -
+    input:
+      bytes: [ 0x04, 0x24, 0x46, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z4.h - z7.h }, za0h.h[w13, 0:3]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x04, 0x46, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.h - z3.h }, za0h.h[w12, 0:3]"
+
+  -
+    input:
+      bytes: [ 0x54, 0x44, 0x46, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z20.h - z23.h }, za1h.h[w14, 0:3]"
+
+  -
+    input:
+      bytes: [ 0x34, 0x64, 0x46, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z20.h - z23.h }, za0h.h[w15, 4:7]"
+
+  -
+    input:
+      bytes: [ 0x7c, 0x64, 0x46, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z28.h - z31.h }, za1h.h[w15, 4:7]"
+
+  -
+    input:
+      bytes: [ 0x24, 0x04, 0x46, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z4.h - z7.h }, za0h.h[w12, 4:7]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x04, 0x46, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.h - z3.h }, za0h.h[w12, 4:7]"
+
+  -
+    input:
+      bytes: [ 0x78, 0x44, 0x46, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z24.h - z27.h }, za1h.h[w14, 4:7]"
+
+  -
+    input:
+      bytes: [ 0x30, 0x44, 0x46, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z16.h - z19.h }, za0h.h[w14, 4:7]"
+
+  -
+    input:
+      bytes: [ 0x5c, 0x04, 0x46, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z28.h - z31.h }, za1h.h[w12, 0:3]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x64, 0x46, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.h - z3.h }, za0h.h[w15, 4:7]"
+
+  -
+    input:
+      bytes: [ 0x04, 0x24, 0x46, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z4.h - z7.h }, za0h.h[w13, 0:3]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x84, 0x46, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.h - z3.h }, za0v.h[w12, 0:3]"
+
+  -
+    input:
+      bytes: [ 0x54, 0xc4, 0x46, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z20.h - z23.h }, za1v.h[w14, 0:3]"
+
+  -
+    input:
+      bytes: [ 0x34, 0xe4, 0x46, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z20.h - z23.h }, za0v.h[w15, 4:7]"
+
+  -
+    input:
+      bytes: [ 0x7c, 0xe4, 0x46, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z28.h - z31.h }, za1v.h[w15, 4:7]"
+
+  -
+    input:
+      bytes: [ 0x24, 0x84, 0x46, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z4.h - z7.h }, za0v.h[w12, 4:7]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x84, 0x46, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.h - z3.h }, za0v.h[w12, 4:7]"
+
+  -
+    input:
+      bytes: [ 0x78, 0xc4, 0x46, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z24.h - z27.h }, za1v.h[w14, 4:7]"
+
+  -
+    input:
+      bytes: [ 0x30, 0xc4, 0x46, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z16.h - z19.h }, za0v.h[w14, 4:7]"
+
+  -
+    input:
+      bytes: [ 0x5c, 0x84, 0x46, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z28.h - z31.h }, za1v.h[w12, 0:3]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe4, 0x46, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.h - z3.h }, za0v.h[w15, 4:7]"
+
+  -
+    input:
+      bytes: [ 0x04, 0xa4, 0x46, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z4.h - z7.h }, za0v.h[w13, 0:3]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x84, 0x46, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.h - z3.h }, za0v.h[w12, 0:3]"
+
+  -
+    input:
+      bytes: [ 0x54, 0xc4, 0x46, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z20.h - z23.h }, za1v.h[w14, 0:3]"
+
+  -
+    input:
+      bytes: [ 0x34, 0xe4, 0x46, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z20.h - z23.h }, za0v.h[w15, 4:7]"
+
+  -
+    input:
+      bytes: [ 0x7c, 0xe4, 0x46, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z28.h - z31.h }, za1v.h[w15, 4:7]"
+
+  -
+    input:
+      bytes: [ 0x24, 0x84, 0x46, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z4.h - z7.h }, za0v.h[w12, 4:7]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x84, 0x46, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.h - z3.h }, za0v.h[w12, 4:7]"
+
+  -
+    input:
+      bytes: [ 0x78, 0xc4, 0x46, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z24.h - z27.h }, za1v.h[w14, 4:7]"
+
+  -
+    input:
+      bytes: [ 0x30, 0xc4, 0x46, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z16.h - z19.h }, za0v.h[w14, 4:7]"
+
+  -
+    input:
+      bytes: [ 0x5c, 0x84, 0x46, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z28.h - z31.h }, za1v.h[w12, 0:3]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe4, 0x46, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.h - z3.h }, za0v.h[w15, 4:7]"
+
+  -
+    input:
+      bytes: [ 0x04, 0xa4, 0x46, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z4.h - z7.h }, za0v.h[w13, 0:3]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x04, 0x44, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.h[w12, 0:3], { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x45, 0x44, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.h[w14, 4:7], { z8.h - z11.h }"
+
+  -
+    input:
+      bytes: [ 0x83, 0x65, 0x44, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1h.h[w15, 4:7], { z12.h - z15.h }"
+
+  -
+    input:
+      bytes: [ 0x83, 0x67, 0x44, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1h.h[w15, 4:7], { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x06, 0x44, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.h[w12, 4:7], { z16.h - z19.h }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x04, 0x44, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.h[w12, 4:7], { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x46, 0x44, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.h[w14, 0:3], { z16.h - z19.h }"
+
+  -
+    input:
+      bytes: [ 0x80, 0x05, 0x44, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.h[w12, 0:3], { z12.h - z15.h }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x44, 0x44, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.h[w14, 4:7], { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x81, 0x06, 0x44, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.h[w12, 4:7], { z20.h - z23.h }"
+
+  -
+    input:
+      bytes: [ 0x02, 0x65, 0x44, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1h.h[w15, 0:3], { z8.h - z11.h }"
+
+  -
+    input:
+      bytes: [ 0x83, 0x25, 0x44, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1h.h[w13, 4:7], { z12.h - z15.h }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x04, 0x44, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.h[w12, 0:3], { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x45, 0x44, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.h[w14, 4:7], { z8.h - z11.h }"
+
+  -
+    input:
+      bytes: [ 0x83, 0x65, 0x44, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1h.h[w15, 4:7], { z12.h - z15.h }"
+
+  -
+    input:
+      bytes: [ 0x83, 0x67, 0x44, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1h.h[w15, 4:7], { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x06, 0x44, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.h[w12, 4:7], { z16.h - z19.h }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x04, 0x44, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.h[w12, 4:7], { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x46, 0x44, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.h[w14, 0:3], { z16.h - z19.h }"
+
+  -
+    input:
+      bytes: [ 0x80, 0x05, 0x44, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.h[w12, 0:3], { z12.h - z15.h }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x44, 0x44, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.h[w14, 4:7], { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x81, 0x06, 0x44, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.h[w12, 4:7], { z20.h - z23.h }"
+
+  -
+    input:
+      bytes: [ 0x02, 0x65, 0x44, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1h.h[w15, 0:3], { z8.h - z11.h }"
+
+  -
+    input:
+      bytes: [ 0x83, 0x25, 0x44, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1h.h[w13, 4:7], { z12.h - z15.h }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x84, 0x44, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.h[w12, 0:3], { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x01, 0xc5, 0x44, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.h[w14, 4:7], { z8.h - z11.h }"
+
+  -
+    input:
+      bytes: [ 0x83, 0xe5, 0x44, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1v.h[w15, 4:7], { z12.h - z15.h }"
+
+  -
+    input:
+      bytes: [ 0x83, 0xe7, 0x44, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1v.h[w15, 4:7], { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x86, 0x44, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.h[w12, 4:7], { z16.h - z19.h }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x84, 0x44, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.h[w12, 4:7], { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc6, 0x44, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.h[w14, 0:3], { z16.h - z19.h }"
+
+  -
+    input:
+      bytes: [ 0x80, 0x85, 0x44, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.h[w12, 0:3], { z12.h - z15.h }"
+
+  -
+    input:
+      bytes: [ 0x01, 0xc4, 0x44, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.h[w14, 4:7], { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x81, 0x86, 0x44, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.h[w12, 4:7], { z20.h - z23.h }"
+
+  -
+    input:
+      bytes: [ 0x02, 0xe5, 0x44, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1v.h[w15, 0:3], { z8.h - z11.h }"
+
+  -
+    input:
+      bytes: [ 0x83, 0xa5, 0x44, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1v.h[w13, 4:7], { z12.h - z15.h }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x84, 0x44, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.h[w12, 0:3], { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x01, 0xc5, 0x44, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.h[w14, 4:7], { z8.h - z11.h }"
+
+  -
+    input:
+      bytes: [ 0x83, 0xe5, 0x44, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1v.h[w15, 4:7], { z12.h - z15.h }"
+
+  -
+    input:
+      bytes: [ 0x83, 0xe7, 0x44, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1v.h[w15, 4:7], { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x86, 0x44, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.h[w12, 4:7], { z16.h - z19.h }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x84, 0x44, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.h[w12, 4:7], { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc6, 0x44, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.h[w14, 0:3], { z16.h - z19.h }"
+
+  -
+    input:
+      bytes: [ 0x80, 0x85, 0x44, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.h[w12, 0:3], { z12.h - z15.h }"
+
+  -
+    input:
+      bytes: [ 0x01, 0xc4, 0x44, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.h[w14, 4:7], { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x81, 0x86, 0x44, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.h[w12, 4:7], { z20.h - z23.h }"
+
+  -
+    input:
+      bytes: [ 0x02, 0xe5, 0x44, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1v.h[w15, 0:3], { z8.h - z11.h }"
+
+  -
+    input:
+      bytes: [ 0x83, 0xa5, 0x44, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1v.h[w13, 4:7], { z12.h - z15.h }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x04, 0x86, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.s - z3.s }, za0h.s[w12, 0:3]"
+
+  -
+    input:
+      bytes: [ 0x54, 0x44, 0x86, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z20.s - z23.s }, za2h.s[w14, 0:3]"
+
+  -
+    input:
+      bytes: [ 0x34, 0x64, 0x86, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z20.s - z23.s }, za1h.s[w15, 0:3]"
+
+  -
+    input:
+      bytes: [ 0x7c, 0x64, 0x86, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z28.s - z31.s }, za3h.s[w15, 0:3]"
+
+  -
+    input:
+      bytes: [ 0x24, 0x04, 0x86, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z4.s - z7.s }, za1h.s[w12, 0:3]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x04, 0x86, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.s - z3.s }, za1h.s[w12, 0:3]"
+
+  -
+    input:
+      bytes: [ 0x78, 0x44, 0x86, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z24.s - z27.s }, za3h.s[w14, 0:3]"
+
+  -
+    input:
+      bytes: [ 0x30, 0x44, 0x86, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z16.s - z19.s }, za1h.s[w14, 0:3]"
+
+  -
+    input:
+      bytes: [ 0x5c, 0x04, 0x86, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z28.s - z31.s }, za2h.s[w12, 0:3]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x64, 0x86, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.s - z3.s }, za1h.s[w15, 0:3]"
+
+  -
+    input:
+      bytes: [ 0x04, 0x24, 0x86, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z4.s - z7.s }, za0h.s[w13, 0:3]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x04, 0x86, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.s - z3.s }, za0h.s[w12, 0:3]"
+
+  -
+    input:
+      bytes: [ 0x54, 0x44, 0x86, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z20.s - z23.s }, za2h.s[w14, 0:3]"
+
+  -
+    input:
+      bytes: [ 0x34, 0x64, 0x86, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z20.s - z23.s }, za1h.s[w15, 0:3]"
+
+  -
+    input:
+      bytes: [ 0x7c, 0x64, 0x86, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z28.s - z31.s }, za3h.s[w15, 0:3]"
+
+  -
+    input:
+      bytes: [ 0x24, 0x04, 0x86, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z4.s - z7.s }, za1h.s[w12, 0:3]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x04, 0x86, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.s - z3.s }, za1h.s[w12, 0:3]"
+
+  -
+    input:
+      bytes: [ 0x78, 0x44, 0x86, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z24.s - z27.s }, za3h.s[w14, 0:3]"
+
+  -
+    input:
+      bytes: [ 0x30, 0x44, 0x86, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z16.s - z19.s }, za1h.s[w14, 0:3]"
+
+  -
+    input:
+      bytes: [ 0x5c, 0x04, 0x86, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z28.s - z31.s }, za2h.s[w12, 0:3]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x64, 0x86, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.s - z3.s }, za1h.s[w15, 0:3]"
+
+  -
+    input:
+      bytes: [ 0x04, 0x24, 0x86, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z4.s - z7.s }, za0h.s[w13, 0:3]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x84, 0x86, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.s - z3.s }, za0v.s[w12, 0:3]"
+
+  -
+    input:
+      bytes: [ 0x54, 0xc4, 0x86, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z20.s - z23.s }, za2v.s[w14, 0:3]"
+
+  -
+    input:
+      bytes: [ 0x34, 0xe4, 0x86, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z20.s - z23.s }, za1v.s[w15, 0:3]"
+
+  -
+    input:
+      bytes: [ 0x7c, 0xe4, 0x86, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z28.s - z31.s }, za3v.s[w15, 0:3]"
+
+  -
+    input:
+      bytes: [ 0x24, 0x84, 0x86, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z4.s - z7.s }, za1v.s[w12, 0:3]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x84, 0x86, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.s - z3.s }, za1v.s[w12, 0:3]"
+
+  -
+    input:
+      bytes: [ 0x78, 0xc4, 0x86, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z24.s - z27.s }, za3v.s[w14, 0:3]"
+
+  -
+    input:
+      bytes: [ 0x30, 0xc4, 0x86, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z16.s - z19.s }, za1v.s[w14, 0:3]"
+
+  -
+    input:
+      bytes: [ 0x5c, 0x84, 0x86, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z28.s - z31.s }, za2v.s[w12, 0:3]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe4, 0x86, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.s - z3.s }, za1v.s[w15, 0:3]"
+
+  -
+    input:
+      bytes: [ 0x04, 0xa4, 0x86, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z4.s - z7.s }, za0v.s[w13, 0:3]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x84, 0x86, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.s - z3.s }, za0v.s[w12, 0:3]"
+
+  -
+    input:
+      bytes: [ 0x54, 0xc4, 0x86, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z20.s - z23.s }, za2v.s[w14, 0:3]"
+
+  -
+    input:
+      bytes: [ 0x34, 0xe4, 0x86, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z20.s - z23.s }, za1v.s[w15, 0:3]"
+
+  -
+    input:
+      bytes: [ 0x7c, 0xe4, 0x86, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z28.s - z31.s }, za3v.s[w15, 0:3]"
+
+  -
+    input:
+      bytes: [ 0x24, 0x84, 0x86, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z4.s - z7.s }, za1v.s[w12, 0:3]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x84, 0x86, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.s - z3.s }, za1v.s[w12, 0:3]"
+
+  -
+    input:
+      bytes: [ 0x78, 0xc4, 0x86, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z24.s - z27.s }, za3v.s[w14, 0:3]"
+
+  -
+    input:
+      bytes: [ 0x30, 0xc4, 0x86, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z16.s - z19.s }, za1v.s[w14, 0:3]"
+
+  -
+    input:
+      bytes: [ 0x5c, 0x84, 0x86, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z28.s - z31.s }, za2v.s[w12, 0:3]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe4, 0x86, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.s - z3.s }, za1v.s[w15, 0:3]"
+
+  -
+    input:
+      bytes: [ 0x04, 0xa4, 0x86, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z4.s - z7.s }, za0v.s[w13, 0:3]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x04, 0x84, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.s[w12, 0:3], { z0.s - z3.s }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x45, 0x84, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1h.s[w14, 0:3], { z8.s - z11.s }"
+
+  -
+    input:
+      bytes: [ 0x83, 0x65, 0x84, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za3h.s[w15, 0:3], { z12.s - z15.s }"
+
+  -
+    input:
+      bytes: [ 0x83, 0x67, 0x84, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za3h.s[w15, 0:3], { z28.s - z31.s }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x06, 0x84, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1h.s[w12, 0:3], { z16.s - z19.s }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x04, 0x84, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1h.s[w12, 0:3], { z0.s - z3.s }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x46, 0x84, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.s[w14, 0:3], { z16.s - z19.s }"
+
+  -
+    input:
+      bytes: [ 0x80, 0x05, 0x84, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.s[w12, 0:3], { z12.s - z15.s }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x44, 0x84, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1h.s[w14, 0:3], { z0.s - z3.s }"
+
+  -
+    input:
+      bytes: [ 0x81, 0x06, 0x84, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1h.s[w12, 0:3], { z20.s - z23.s }"
+
+  -
+    input:
+      bytes: [ 0x02, 0x65, 0x84, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za2h.s[w15, 0:3], { z8.s - z11.s }"
+
+  -
+    input:
+      bytes: [ 0x83, 0x25, 0x84, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za3h.s[w13, 0:3], { z12.s - z15.s }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x04, 0x84, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.s[w12, 0:3], { z0.s - z3.s }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x45, 0x84, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1h.s[w14, 0:3], { z8.s - z11.s }"
+
+  -
+    input:
+      bytes: [ 0x83, 0x65, 0x84, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za3h.s[w15, 0:3], { z12.s - z15.s }"
+
+  -
+    input:
+      bytes: [ 0x83, 0x67, 0x84, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za3h.s[w15, 0:3], { z28.s - z31.s }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x06, 0x84, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1h.s[w12, 0:3], { z16.s - z19.s }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x04, 0x84, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1h.s[w12, 0:3], { z0.s - z3.s }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x46, 0x84, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.s[w14, 0:3], { z16.s - z19.s }"
+
+  -
+    input:
+      bytes: [ 0x80, 0x05, 0x84, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.s[w12, 0:3], { z12.s - z15.s }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x44, 0x84, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1h.s[w14, 0:3], { z0.s - z3.s }"
+
+  -
+    input:
+      bytes: [ 0x81, 0x06, 0x84, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1h.s[w12, 0:3], { z20.s - z23.s }"
+
+  -
+    input:
+      bytes: [ 0x02, 0x65, 0x84, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za2h.s[w15, 0:3], { z8.s - z11.s }"
+
+  -
+    input:
+      bytes: [ 0x83, 0x25, 0x84, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za3h.s[w13, 0:3], { z12.s - z15.s }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x84, 0x84, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.s[w12, 0:3], { z0.s - z3.s }"
+
+  -
+    input:
+      bytes: [ 0x01, 0xc5, 0x84, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1v.s[w14, 0:3], { z8.s - z11.s }"
+
+  -
+    input:
+      bytes: [ 0x83, 0xe5, 0x84, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za3v.s[w15, 0:3], { z12.s - z15.s }"
+
+  -
+    input:
+      bytes: [ 0x83, 0xe7, 0x84, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za3v.s[w15, 0:3], { z28.s - z31.s }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x86, 0x84, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1v.s[w12, 0:3], { z16.s - z19.s }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x84, 0x84, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1v.s[w12, 0:3], { z0.s - z3.s }"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc6, 0x84, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.s[w14, 0:3], { z16.s - z19.s }"
+
+  -
+    input:
+      bytes: [ 0x80, 0x85, 0x84, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.s[w12, 0:3], { z12.s - z15.s }"
+
+  -
+    input:
+      bytes: [ 0x01, 0xc4, 0x84, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1v.s[w14, 0:3], { z0.s - z3.s }"
+
+  -
+    input:
+      bytes: [ 0x81, 0x86, 0x84, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1v.s[w12, 0:3], { z20.s - z23.s }"
+
+  -
+    input:
+      bytes: [ 0x02, 0xe5, 0x84, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za2v.s[w15, 0:3], { z8.s - z11.s }"
+
+  -
+    input:
+      bytes: [ 0x83, 0xa5, 0x84, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za3v.s[w13, 0:3], { z12.s - z15.s }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x84, 0x84, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.s[w12, 0:3], { z0.s - z3.s }"
+
+  -
+    input:
+      bytes: [ 0x01, 0xc5, 0x84, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1v.s[w14, 0:3], { z8.s - z11.s }"
+
+  -
+    input:
+      bytes: [ 0x83, 0xe5, 0x84, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za3v.s[w15, 0:3], { z12.s - z15.s }"
+
+  -
+    input:
+      bytes: [ 0x83, 0xe7, 0x84, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za3v.s[w15, 0:3], { z28.s - z31.s }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x86, 0x84, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1v.s[w12, 0:3], { z16.s - z19.s }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x84, 0x84, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1v.s[w12, 0:3], { z0.s - z3.s }"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc6, 0x84, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.s[w14, 0:3], { z16.s - z19.s }"
+
+  -
+    input:
+      bytes: [ 0x80, 0x85, 0x84, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.s[w12, 0:3], { z12.s - z15.s }"
+
+  -
+    input:
+      bytes: [ 0x01, 0xc4, 0x84, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1v.s[w14, 0:3], { z0.s - z3.s }"
+
+  -
+    input:
+      bytes: [ 0x81, 0x86, 0x84, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1v.s[w12, 0:3], { z20.s - z23.s }"
+
+  -
+    input:
+      bytes: [ 0x02, 0xe5, 0x84, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za2v.s[w15, 0:3], { z8.s - z11.s }"
+
+  -
+    input:
+      bytes: [ 0x83, 0xa5, 0x84, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za3v.s[w13, 0:3], { z12.s - z15.s }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x04, 0xc6, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.d - z3.d }, za0h.d[w12, 0:3]"
+
+  -
+    input:
+      bytes: [ 0x54, 0x44, 0xc6, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z20.d - z23.d }, za2h.d[w14, 0:3]"
+
+  -
+    input:
+      bytes: [ 0xb4, 0x64, 0xc6, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z20.d - z23.d }, za5h.d[w15, 0:3]"
+
+  -
+    input:
+      bytes: [ 0xfc, 0x64, 0xc6, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z28.d - z31.d }, za7h.d[w15, 0:3]"
+
+  -
+    input:
+      bytes: [ 0x24, 0x04, 0xc6, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z4.d - z7.d }, za1h.d[w12, 0:3]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x04, 0xc6, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.d - z3.d }, za1h.d[w12, 0:3]"
+
+  -
+    input:
+      bytes: [ 0x78, 0x44, 0xc6, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z24.d - z27.d }, za3h.d[w14, 0:3]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x04, 0xc6, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.d - z3.d }, za4h.d[w12, 0:3]"
+
+  -
+    input:
+      bytes: [ 0x30, 0x44, 0xc6, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z16.d - z19.d }, za1h.d[w14, 0:3]"
+
+  -
+    input:
+      bytes: [ 0xdc, 0x04, 0xc6, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z28.d - z31.d }, za6h.d[w12, 0:3]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x64, 0xc6, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.d - z3.d }, za1h.d[w15, 0:3]"
+
+  -
+    input:
+      bytes: [ 0x84, 0x24, 0xc6, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z4.d - z7.d }, za4h.d[w13, 0:3]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x04, 0xc6, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.d - z3.d }, za0h.d[w12, 0:3]"
+
+  -
+    input:
+      bytes: [ 0x54, 0x44, 0xc6, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z20.d - z23.d }, za2h.d[w14, 0:3]"
+
+  -
+    input:
+      bytes: [ 0xb4, 0x64, 0xc6, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z20.d - z23.d }, za5h.d[w15, 0:3]"
+
+  -
+    input:
+      bytes: [ 0xfc, 0x64, 0xc6, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z28.d - z31.d }, za7h.d[w15, 0:3]"
+
+  -
+    input:
+      bytes: [ 0x24, 0x04, 0xc6, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z4.d - z7.d }, za1h.d[w12, 0:3]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x04, 0xc6, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.d - z3.d }, za1h.d[w12, 0:3]"
+
+  -
+    input:
+      bytes: [ 0x78, 0x44, 0xc6, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z24.d - z27.d }, za3h.d[w14, 0:3]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x04, 0xc6, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.d - z3.d }, za4h.d[w12, 0:3]"
+
+  -
+    input:
+      bytes: [ 0x30, 0x44, 0xc6, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z16.d - z19.d }, za1h.d[w14, 0:3]"
+
+  -
+    input:
+      bytes: [ 0xdc, 0x04, 0xc6, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z28.d - z31.d }, za6h.d[w12, 0:3]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x64, 0xc6, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.d - z3.d }, za1h.d[w15, 0:3]"
+
+  -
+    input:
+      bytes: [ 0x84, 0x24, 0xc6, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z4.d - z7.d }, za4h.d[w13, 0:3]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x84, 0xc6, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.d - z3.d }, za0v.d[w12, 0:3]"
+
+  -
+    input:
+      bytes: [ 0x54, 0xc4, 0xc6, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z20.d - z23.d }, za2v.d[w14, 0:3]"
+
+  -
+    input:
+      bytes: [ 0xb4, 0xe4, 0xc6, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z20.d - z23.d }, za5v.d[w15, 0:3]"
+
+  -
+    input:
+      bytes: [ 0xfc, 0xe4, 0xc6, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z28.d - z31.d }, za7v.d[w15, 0:3]"
+
+  -
+    input:
+      bytes: [ 0x24, 0x84, 0xc6, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z4.d - z7.d }, za1v.d[w12, 0:3]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x84, 0xc6, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.d - z3.d }, za1v.d[w12, 0:3]"
+
+  -
+    input:
+      bytes: [ 0x78, 0xc4, 0xc6, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z24.d - z27.d }, za3v.d[w14, 0:3]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x84, 0xc6, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.d - z3.d }, za4v.d[w12, 0:3]"
+
+  -
+    input:
+      bytes: [ 0x30, 0xc4, 0xc6, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z16.d - z19.d }, za1v.d[w14, 0:3]"
+
+  -
+    input:
+      bytes: [ 0xdc, 0x84, 0xc6, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z28.d - z31.d }, za6v.d[w12, 0:3]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe4, 0xc6, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.d - z3.d }, za1v.d[w15, 0:3]"
+
+  -
+    input:
+      bytes: [ 0x84, 0xa4, 0xc6, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z4.d - z7.d }, za4v.d[w13, 0:3]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x84, 0xc6, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.d - z3.d }, za0v.d[w12, 0:3]"
+
+  -
+    input:
+      bytes: [ 0x54, 0xc4, 0xc6, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z20.d - z23.d }, za2v.d[w14, 0:3]"
+
+  -
+    input:
+      bytes: [ 0xb4, 0xe4, 0xc6, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z20.d - z23.d }, za5v.d[w15, 0:3]"
+
+  -
+    input:
+      bytes: [ 0xfc, 0xe4, 0xc6, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z28.d - z31.d }, za7v.d[w15, 0:3]"
+
+  -
+    input:
+      bytes: [ 0x24, 0x84, 0xc6, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z4.d - z7.d }, za1v.d[w12, 0:3]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x84, 0xc6, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.d - z3.d }, za1v.d[w12, 0:3]"
+
+  -
+    input:
+      bytes: [ 0x78, 0xc4, 0xc6, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z24.d - z27.d }, za3v.d[w14, 0:3]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x84, 0xc6, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.d - z3.d }, za4v.d[w12, 0:3]"
+
+  -
+    input:
+      bytes: [ 0x30, 0xc4, 0xc6, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z16.d - z19.d }, za1v.d[w14, 0:3]"
+
+  -
+    input:
+      bytes: [ 0xdc, 0x84, 0xc6, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z28.d - z31.d }, za6v.d[w12, 0:3]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe4, 0xc6, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.d - z3.d }, za1v.d[w15, 0:3]"
+
+  -
+    input:
+      bytes: [ 0x84, 0xa4, 0xc6, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z4.d - z7.d }, za4v.d[w13, 0:3]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x0c, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.d - z3.d }, za.d[w8, 0, vgx4]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x0c, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.d - z3.d }, za.d[w8, 0, vgx4]"
+
+  -
+    input:
+      bytes: [ 0x54, 0x4c, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z20.d - z23.d }, za.d[w10, 2, vgx4]"
+
+  -
+    input:
+      bytes: [ 0x54, 0x4c, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z20.d - z23.d }, za.d[w10, 2, vgx4]"
+
+  -
+    input:
+      bytes: [ 0xb4, 0x6c, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z20.d - z23.d }, za.d[w11, 5, vgx4]"
+
+  -
+    input:
+      bytes: [ 0xb4, 0x6c, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z20.d - z23.d }, za.d[w11, 5, vgx4]"
+
+  -
+    input:
+      bytes: [ 0xfc, 0x6c, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z28.d - z31.d }, za.d[w11, 7, vgx4]"
+
+  -
+    input:
+      bytes: [ 0xfc, 0x6c, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z28.d - z31.d }, za.d[w11, 7, vgx4]"
+
+  -
+    input:
+      bytes: [ 0x24, 0x0c, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z4.d - z7.d }, za.d[w8, 1, vgx4]"
+
+  -
+    input:
+      bytes: [ 0x24, 0x0c, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z4.d - z7.d }, za.d[w8, 1, vgx4]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x0c, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.d - z3.d }, za.d[w8, 1, vgx4]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x0c, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.d - z3.d }, za.d[w8, 1, vgx4]"
+
+  -
+    input:
+      bytes: [ 0x78, 0x4c, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z24.d - z27.d }, za.d[w10, 3, vgx4]"
+
+  -
+    input:
+      bytes: [ 0x78, 0x4c, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z24.d - z27.d }, za.d[w10, 3, vgx4]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x0c, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.d - z3.d }, za.d[w8, 4, vgx4]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x0c, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.d - z3.d }, za.d[w8, 4, vgx4]"
+
+  -
+    input:
+      bytes: [ 0x30, 0x4c, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z16.d - z19.d }, za.d[w10, 1, vgx4]"
+
+  -
+    input:
+      bytes: [ 0x30, 0x4c, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z16.d - z19.d }, za.d[w10, 1, vgx4]"
+
+  -
+    input:
+      bytes: [ 0xdc, 0x0c, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z28.d - z31.d }, za.d[w8, 6, vgx4]"
+
+  -
+    input:
+      bytes: [ 0xdc, 0x0c, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z28.d - z31.d }, za.d[w8, 6, vgx4]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x6c, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.d - z3.d }, za.d[w11, 1, vgx4]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x6c, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.d - z3.d }, za.d[w11, 1, vgx4]"
+
+  -
+    input:
+      bytes: [ 0x84, 0x2c, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z4.d - z7.d }, za.d[w9, 4, vgx4]"
+
+  -
+    input:
+      bytes: [ 0x84, 0x2c, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z4.d - z7.d }, za.d[w9, 4, vgx4]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x0c, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.d - z3.d }, za.d[w8, 0, vgx4]"
+
+  -
+    input:
+      bytes: [ 0x54, 0x4c, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z20.d - z23.d }, za.d[w10, 2, vgx4]"
+
+  -
+    input:
+      bytes: [ 0xb4, 0x6c, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z20.d - z23.d }, za.d[w11, 5, vgx4]"
+
+  -
+    input:
+      bytes: [ 0xfc, 0x6c, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z28.d - z31.d }, za.d[w11, 7, vgx4]"
+
+  -
+    input:
+      bytes: [ 0x24, 0x0c, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z4.d - z7.d }, za.d[w8, 1, vgx4]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x0c, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.d - z3.d }, za.d[w8, 1, vgx4]"
+
+  -
+    input:
+      bytes: [ 0x78, 0x4c, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z24.d - z27.d }, za.d[w10, 3, vgx4]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x0c, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.d - z3.d }, za.d[w8, 4, vgx4]"
+
+  -
+    input:
+      bytes: [ 0x30, 0x4c, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z16.d - z19.d }, za.d[w10, 1, vgx4]"
+
+  -
+    input:
+      bytes: [ 0xdc, 0x0c, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z28.d - z31.d }, za.d[w8, 6, vgx4]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x6c, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.d - z3.d }, za.d[w11, 1, vgx4]"
+
+  -
+    input:
+      bytes: [ 0x84, 0x2c, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z4.d - z7.d }, za.d[w9, 4, vgx4]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x04, 0xc4, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.d[w12, 0:3], { z0.d - z3.d }"
+
+  -
+    input:
+      bytes: [ 0x05, 0x45, 0xc4, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za5h.d[w14, 0:3], { z8.d - z11.d }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x65, 0xc4, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za7h.d[w15, 0:3], { z12.d - z15.d }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x67, 0xc4, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za7h.d[w15, 0:3], { z28.d - z31.d }"
+
+  -
+    input:
+      bytes: [ 0x05, 0x06, 0xc4, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za5h.d[w12, 0:3], { z16.d - z19.d }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x04, 0xc4, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1h.d[w12, 0:3], { z0.d - z3.d }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x46, 0xc4, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.d[w14, 0:3], { z16.d - z19.d }"
+
+  -
+    input:
+      bytes: [ 0x80, 0x05, 0xc4, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.d[w12, 0:3], { z12.d - z15.d }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x44, 0xc4, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1h.d[w14, 0:3], { z0.d - z3.d }"
+
+  -
+    input:
+      bytes: [ 0x85, 0x06, 0xc4, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za5h.d[w12, 0:3], { z20.d - z23.d }"
+
+  -
+    input:
+      bytes: [ 0x02, 0x65, 0xc4, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za2h.d[w15, 0:3], { z8.d - z11.d }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x25, 0xc4, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za7h.d[w13, 0:3], { z12.d - z15.d }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x04, 0xc4, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.d[w12, 0:3], { z0.d - z3.d }"
+
+  -
+    input:
+      bytes: [ 0x05, 0x45, 0xc4, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za5h.d[w14, 0:3], { z8.d - z11.d }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x65, 0xc4, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za7h.d[w15, 0:3], { z12.d - z15.d }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x67, 0xc4, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za7h.d[w15, 0:3], { z28.d - z31.d }"
+
+  -
+    input:
+      bytes: [ 0x05, 0x06, 0xc4, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za5h.d[w12, 0:3], { z16.d - z19.d }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x04, 0xc4, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1h.d[w12, 0:3], { z0.d - z3.d }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x46, 0xc4, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.d[w14, 0:3], { z16.d - z19.d }"
+
+  -
+    input:
+      bytes: [ 0x80, 0x05, 0xc4, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.d[w12, 0:3], { z12.d - z15.d }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x44, 0xc4, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1h.d[w14, 0:3], { z0.d - z3.d }"
+
+  -
+    input:
+      bytes: [ 0x85, 0x06, 0xc4, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za5h.d[w12, 0:3], { z20.d - z23.d }"
+
+  -
+    input:
+      bytes: [ 0x02, 0x65, 0xc4, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za2h.d[w15, 0:3], { z8.d - z11.d }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x25, 0xc4, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za7h.d[w13, 0:3], { z12.d - z15.d }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x84, 0xc4, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.d[w12, 0:3], { z0.d - z3.d }"
+
+  -
+    input:
+      bytes: [ 0x05, 0xc5, 0xc4, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za5v.d[w14, 0:3], { z8.d - z11.d }"
+
+  -
+    input:
+      bytes: [ 0x87, 0xe5, 0xc4, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za7v.d[w15, 0:3], { z12.d - z15.d }"
+
+  -
+    input:
+      bytes: [ 0x87, 0xe7, 0xc4, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za7v.d[w15, 0:3], { z28.d - z31.d }"
+
+  -
+    input:
+      bytes: [ 0x05, 0x86, 0xc4, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za5v.d[w12, 0:3], { z16.d - z19.d }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x84, 0xc4, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1v.d[w12, 0:3], { z0.d - z3.d }"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc6, 0xc4, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.d[w14, 0:3], { z16.d - z19.d }"
+
+  -
+    input:
+      bytes: [ 0x80, 0x85, 0xc4, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.d[w12, 0:3], { z12.d - z15.d }"
+
+  -
+    input:
+      bytes: [ 0x01, 0xc4, 0xc4, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1v.d[w14, 0:3], { z0.d - z3.d }"
+
+  -
+    input:
+      bytes: [ 0x85, 0x86, 0xc4, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za5v.d[w12, 0:3], { z20.d - z23.d }"
+
+  -
+    input:
+      bytes: [ 0x02, 0xe5, 0xc4, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za2v.d[w15, 0:3], { z8.d - z11.d }"
+
+  -
+    input:
+      bytes: [ 0x87, 0xa5, 0xc4, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za7v.d[w13, 0:3], { z12.d - z15.d }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x84, 0xc4, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.d[w12, 0:3], { z0.d - z3.d }"
+
+  -
+    input:
+      bytes: [ 0x05, 0xc5, 0xc4, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za5v.d[w14, 0:3], { z8.d - z11.d }"
+
+  -
+    input:
+      bytes: [ 0x87, 0xe5, 0xc4, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za7v.d[w15, 0:3], { z12.d - z15.d }"
+
+  -
+    input:
+      bytes: [ 0x87, 0xe7, 0xc4, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za7v.d[w15, 0:3], { z28.d - z31.d }"
+
+  -
+    input:
+      bytes: [ 0x05, 0x86, 0xc4, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za5v.d[w12, 0:3], { z16.d - z19.d }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x84, 0xc4, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1v.d[w12, 0:3], { z0.d - z3.d }"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc6, 0xc4, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.d[w14, 0:3], { z16.d - z19.d }"
+
+  -
+    input:
+      bytes: [ 0x80, 0x85, 0xc4, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.d[w12, 0:3], { z12.d - z15.d }"
+
+  -
+    input:
+      bytes: [ 0x01, 0xc4, 0xc4, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za1v.d[w14, 0:3], { z0.d - z3.d }"
+
+  -
+    input:
+      bytes: [ 0x85, 0x86, 0xc4, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za5v.d[w12, 0:3], { z20.d - z23.d }"
+
+  -
+    input:
+      bytes: [ 0x02, 0xe5, 0xc4, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za2v.d[w15, 0:3], { z8.d - z11.d }"
+
+  -
+    input:
+      bytes: [ 0x87, 0xa5, 0xc4, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za7v.d[w13, 0:3], { z12.d - z15.d }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x0c, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za.d[w8, 0, vgx4], { z0.d - z3.d }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x0c, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za.d[w8, 0, vgx4], { z0.d - z3.d }"
+
+  -
+    input:
+      bytes: [ 0x05, 0x4d, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za.d[w10, 5, vgx4], { z8.d - z11.d }"
+
+  -
+    input:
+      bytes: [ 0x05, 0x4d, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za.d[w10, 5, vgx4], { z8.d - z11.d }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x6d, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za.d[w11, 7, vgx4], { z12.d - z15.d }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x6d, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za.d[w11, 7, vgx4], { z12.d - z15.d }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x6f, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za.d[w11, 7, vgx4], { z28.d - z31.d }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x6f, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za.d[w11, 7, vgx4], { z28.d - z31.d }"
+
+  -
+    input:
+      bytes: [ 0x05, 0x0e, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za.d[w8, 5, vgx4], { z16.d - z19.d }"
+
+  -
+    input:
+      bytes: [ 0x05, 0x0e, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za.d[w8, 5, vgx4], { z16.d - z19.d }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x0c, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za.d[w8, 1, vgx4], { z0.d - z3.d }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x0c, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za.d[w8, 1, vgx4], { z0.d - z3.d }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x4e, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za.d[w10, 0, vgx4], { z16.d - z19.d }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x4e, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za.d[w10, 0, vgx4], { z16.d - z19.d }"
+
+  -
+    input:
+      bytes: [ 0x80, 0x0d, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za.d[w8, 0, vgx4], { z12.d - z15.d }"
+
+  -
+    input:
+      bytes: [ 0x80, 0x0d, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za.d[w8, 0, vgx4], { z12.d - z15.d }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x4c, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za.d[w10, 1, vgx4], { z0.d - z3.d }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x4c, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za.d[w10, 1, vgx4], { z0.d - z3.d }"
+
+  -
+    input:
+      bytes: [ 0x85, 0x0e, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za.d[w8, 5, vgx4], { z20.d - z23.d }"
+
+  -
+    input:
+      bytes: [ 0x85, 0x0e, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za.d[w8, 5, vgx4], { z20.d - z23.d }"
+
+  -
+    input:
+      bytes: [ 0x02, 0x6d, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za.d[w11, 2, vgx4], { z8.d - z11.d }"
+
+  -
+    input:
+      bytes: [ 0x02, 0x6d, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za.d[w11, 2, vgx4], { z8.d - z11.d }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x2d, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za.d[w9, 7, vgx4], { z12.d - z15.d }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x2d, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za.d[w9, 7, vgx4], { z12.d - z15.d }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x0c, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za.d[w8, 0, vgx4], { z0.d - z3.d }"
+
+  -
+    input:
+      bytes: [ 0x05, 0x4d, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za.d[w10, 5, vgx4], { z8.d - z11.d }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x6d, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za.d[w11, 7, vgx4], { z12.d - z15.d }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x6f, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za.d[w11, 7, vgx4], { z28.d - z31.d }"
+
+  -
+    input:
+      bytes: [ 0x05, 0x0e, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za.d[w8, 5, vgx4], { z16.d - z19.d }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x0c, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za.d[w8, 1, vgx4], { z0.d - z3.d }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x4e, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za.d[w10, 0, vgx4], { z16.d - z19.d }"
+
+  -
+    input:
+      bytes: [ 0x80, 0x0d, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za.d[w8, 0, vgx4], { z12.d - z15.d }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x4c, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za.d[w10, 1, vgx4], { z0.d - z3.d }"
+
+  -
+    input:
+      bytes: [ 0x85, 0x0e, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za.d[w8, 5, vgx4], { z20.d - z23.d }"
+
+  -
+    input:
+      bytes: [ 0x02, 0x6d, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za.d[w11, 2, vgx4], { z8.d - z11.d }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x2d, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za.d[w9, 7, vgx4], { z12.d - z15.d }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x04, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.b - z3.b }, za0h.b[w12, 0:3]"
+
+  -
+    input:
+      bytes: [ 0x54, 0x44, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z20.b - z23.b }, za0h.b[w14, 8:11]"
+
+  -
+    input:
+      bytes: [ 0x34, 0x64, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z20.b - z23.b }, za0h.b[w15, 4:7]"
+
+  -
+    input:
+      bytes: [ 0x7c, 0x64, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z28.b - z31.b }, za0h.b[w15, 12:15]"
+
+  -
+    input:
+      bytes: [ 0x24, 0x04, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z4.b - z7.b }, za0h.b[w12, 4:7]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x04, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.b - z3.b }, za0h.b[w12, 4:7]"
+
+  -
+    input:
+      bytes: [ 0x78, 0x44, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z24.b - z27.b }, za0h.b[w14, 12:15]"
+
+  -
+    input:
+      bytes: [ 0x30, 0x44, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z16.b - z19.b }, za0h.b[w14, 4:7]"
+
+  -
+    input:
+      bytes: [ 0x5c, 0x04, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z28.b - z31.b }, za0h.b[w12, 8:11]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x64, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.b - z3.b }, za0h.b[w15, 4:7]"
+
+  -
+    input:
+      bytes: [ 0x04, 0x24, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z4.b - z7.b }, za0h.b[w13, 0:3]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x04, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.b - z3.b }, za0h.b[w12, 0:3]"
+
+  -
+    input:
+      bytes: [ 0x54, 0x44, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z20.b - z23.b }, za0h.b[w14, 8:11]"
+
+  -
+    input:
+      bytes: [ 0x34, 0x64, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z20.b - z23.b }, za0h.b[w15, 4:7]"
+
+  -
+    input:
+      bytes: [ 0x7c, 0x64, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z28.b - z31.b }, za0h.b[w15, 12:15]"
+
+  -
+    input:
+      bytes: [ 0x24, 0x04, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z4.b - z7.b }, za0h.b[w12, 4:7]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x04, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.b - z3.b }, za0h.b[w12, 4:7]"
+
+  -
+    input:
+      bytes: [ 0x78, 0x44, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z24.b - z27.b }, za0h.b[w14, 12:15]"
+
+  -
+    input:
+      bytes: [ 0x30, 0x44, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z16.b - z19.b }, za0h.b[w14, 4:7]"
+
+  -
+    input:
+      bytes: [ 0x5c, 0x04, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z28.b - z31.b }, za0h.b[w12, 8:11]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x64, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.b - z3.b }, za0h.b[w15, 4:7]"
+
+  -
+    input:
+      bytes: [ 0x04, 0x24, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z4.b - z7.b }, za0h.b[w13, 0:3]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x84, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.b - z3.b }, za0v.b[w12, 0:3]"
+
+  -
+    input:
+      bytes: [ 0x54, 0xc4, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z20.b - z23.b }, za0v.b[w14, 8:11]"
+
+  -
+    input:
+      bytes: [ 0x34, 0xe4, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z20.b - z23.b }, za0v.b[w15, 4:7]"
+
+  -
+    input:
+      bytes: [ 0x7c, 0xe4, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z28.b - z31.b }, za0v.b[w15, 12:15]"
+
+  -
+    input:
+      bytes: [ 0x24, 0x84, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z4.b - z7.b }, za0v.b[w12, 4:7]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x84, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.b - z3.b }, za0v.b[w12, 4:7]"
+
+  -
+    input:
+      bytes: [ 0x78, 0xc4, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z24.b - z27.b }, za0v.b[w14, 12:15]"
+
+  -
+    input:
+      bytes: [ 0x30, 0xc4, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z16.b - z19.b }, za0v.b[w14, 4:7]"
+
+  -
+    input:
+      bytes: [ 0x5c, 0x84, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z28.b - z31.b }, za0v.b[w12, 8:11]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe4, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.b - z3.b }, za0v.b[w15, 4:7]"
+
+  -
+    input:
+      bytes: [ 0x04, 0xa4, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z4.b - z7.b }, za0v.b[w13, 0:3]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x84, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.b - z3.b }, za0v.b[w12, 0:3]"
+
+  -
+    input:
+      bytes: [ 0x54, 0xc4, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z20.b - z23.b }, za0v.b[w14, 8:11]"
+
+  -
+    input:
+      bytes: [ 0x34, 0xe4, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z20.b - z23.b }, za0v.b[w15, 4:7]"
+
+  -
+    input:
+      bytes: [ 0x7c, 0xe4, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z28.b - z31.b }, za0v.b[w15, 12:15]"
+
+  -
+    input:
+      bytes: [ 0x24, 0x84, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z4.b - z7.b }, za0v.b[w12, 4:7]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x84, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.b - z3.b }, za0v.b[w12, 4:7]"
+
+  -
+    input:
+      bytes: [ 0x78, 0xc4, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z24.b - z27.b }, za0v.b[w14, 12:15]"
+
+  -
+    input:
+      bytes: [ 0x30, 0xc4, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z16.b - z19.b }, za0v.b[w14, 4:7]"
+
+  -
+    input:
+      bytes: [ 0x5c, 0x84, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z28.b - z31.b }, za0v.b[w12, 8:11]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe4, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z0.b - z3.b }, za0v.b[w15, 4:7]"
+
+  -
+    input:
+      bytes: [ 0x04, 0xa4, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov { z4.b - z7.b }, za0v.b[w13, 0:3]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x04, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.b[w12, 0:3], { z0.b - z3.b }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x45, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.b[w14, 4:7], { z8.b - z11.b }"
+
+  -
+    input:
+      bytes: [ 0x83, 0x65, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.b[w15, 12:15], { z12.b - z15.b }"
+
+  -
+    input:
+      bytes: [ 0x83, 0x67, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.b[w15, 12:15], { z28.b - z31.b }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x06, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.b[w12, 4:7], { z16.b - z19.b }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x04, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.b[w12, 4:7], { z0.b - z3.b }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x46, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.b[w14, 0:3], { z16.b - z19.b }"
+
+  -
+    input:
+      bytes: [ 0x80, 0x05, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.b[w12, 0:3], { z12.b - z15.b }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x44, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.b[w14, 4:7], { z0.b - z3.b }"
+
+  -
+    input:
+      bytes: [ 0x81, 0x06, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.b[w12, 4:7], { z20.b - z23.b }"
+
+  -
+    input:
+      bytes: [ 0x02, 0x65, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.b[w15, 8:11], { z8.b - z11.b }"
+
+  -
+    input:
+      bytes: [ 0x83, 0x25, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.b[w13, 12:15], { z12.b - z15.b }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x04, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.b[w12, 0:3], { z0.b - z3.b }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x45, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.b[w14, 4:7], { z8.b - z11.b }"
+
+  -
+    input:
+      bytes: [ 0x83, 0x65, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.b[w15, 12:15], { z12.b - z15.b }"
+
+  -
+    input:
+      bytes: [ 0x83, 0x67, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.b[w15, 12:15], { z28.b - z31.b }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x06, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.b[w12, 4:7], { z16.b - z19.b }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x04, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.b[w12, 4:7], { z0.b - z3.b }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x46, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.b[w14, 0:3], { z16.b - z19.b }"
+
+  -
+    input:
+      bytes: [ 0x80, 0x05, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.b[w12, 0:3], { z12.b - z15.b }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x44, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.b[w14, 4:7], { z0.b - z3.b }"
+
+  -
+    input:
+      bytes: [ 0x81, 0x06, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.b[w12, 4:7], { z20.b - z23.b }"
+
+  -
+    input:
+      bytes: [ 0x02, 0x65, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.b[w15, 8:11], { z8.b - z11.b }"
+
+  -
+    input:
+      bytes: [ 0x83, 0x25, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0h.b[w13, 12:15], { z12.b - z15.b }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x84, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.b[w12, 0:3], { z0.b - z3.b }"
+
+  -
+    input:
+      bytes: [ 0x01, 0xc5, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.b[w14, 4:7], { z8.b - z11.b }"
+
+  -
+    input:
+      bytes: [ 0x83, 0xe5, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.b[w15, 12:15], { z12.b - z15.b }"
+
+  -
+    input:
+      bytes: [ 0x83, 0xe7, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.b[w15, 12:15], { z28.b - z31.b }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x86, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.b[w12, 4:7], { z16.b - z19.b }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x84, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.b[w12, 4:7], { z0.b - z3.b }"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc6, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.b[w14, 0:3], { z16.b - z19.b }"
+
+  -
+    input:
+      bytes: [ 0x80, 0x85, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.b[w12, 0:3], { z12.b - z15.b }"
+
+  -
+    input:
+      bytes: [ 0x01, 0xc4, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.b[w14, 4:7], { z0.b - z3.b }"
+
+  -
+    input:
+      bytes: [ 0x81, 0x86, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.b[w12, 4:7], { z20.b - z23.b }"
+
+  -
+    input:
+      bytes: [ 0x02, 0xe5, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.b[w15, 8:11], { z8.b - z11.b }"
+
+  -
+    input:
+      bytes: [ 0x83, 0xa5, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.b[w13, 12:15], { z12.b - z15.b }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x84, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.b[w12, 0:3], { z0.b - z3.b }"
+
+  -
+    input:
+      bytes: [ 0x01, 0xc5, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.b[w14, 4:7], { z8.b - z11.b }"
+
+  -
+    input:
+      bytes: [ 0x83, 0xe5, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.b[w15, 12:15], { z12.b - z15.b }"
+
+  -
+    input:
+      bytes: [ 0x83, 0xe7, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.b[w15, 12:15], { z28.b - z31.b }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x86, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.b[w12, 4:7], { z16.b - z19.b }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x84, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.b[w12, 4:7], { z0.b - z3.b }"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc6, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.b[w14, 0:3], { z16.b - z19.b }"
+
+  -
+    input:
+      bytes: [ 0x80, 0x85, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.b[w12, 0:3], { z12.b - z15.b }"
+
+  -
+    input:
+      bytes: [ 0x01, 0xc4, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.b[w14, 4:7], { z0.b - z3.b }"
+
+  -
+    input:
+      bytes: [ 0x81, 0x86, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.b[w12, 4:7], { z20.b - z23.b }"
+
+  -
+    input:
+      bytes: [ 0x02, 0xe5, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.b[w15, 8:11], { z8.b - z11.b }"
+
+  -
+    input:
+      bytes: [ 0x83, 0xa5, 0x04, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov za0v.b[w13, 12:15], { z12.b - z15.b }"
diff --git a/tests/MC/AArch64/SME2/movt.s.yaml b/tests/MC/AArch64/SME2/movt.s.yaml
new file mode 100644
index 000000000..73b6b0bbd
--- /dev/null
+++ b/tests/MC/AArch64/SME2/movt.s.yaml
@@ -0,0 +1,80 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xe0, 0x03, 0x4c, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movt x0, zt0[0]"
+
+  -
+    input:
+      bytes: [ 0xf5, 0x53, 0x4c, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movt x21, zt0[40]"
+
+  -
+    input:
+      bytes: [ 0xf7, 0x63, 0x4c, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movt x23, zt0[48]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x73, 0x4c, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movt xzr, zt0[56]"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x03, 0x4e, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movt zt0[0], x0"
+
+  -
+    input:
+      bytes: [ 0xf5, 0x53, 0x4e, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movt zt0[40], x21"
+
+  -
+    input:
+      bytes: [ 0xf7, 0x63, 0x4e, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movt zt0[48], x23"
+
+  -
+    input:
+      bytes: [ 0xff, 0x73, 0x4e, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movt zt0[56], xzr"
diff --git a/tests/MC/AArch64/SME2/sclamp.s.yaml b/tests/MC/AArch64/SME2/sclamp.s.yaml
new file mode 100644
index 000000000..4b6a488be
--- /dev/null
+++ b/tests/MC/AArch64/SME2/sclamp.s.yaml
@@ -0,0 +1,320 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xc4, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sclamp { z0.h, z1.h }, z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x54, 0xc5, 0x75, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sclamp { z20.h, z21.h }, z10.h, z21.h"
+
+  -
+    input:
+      bytes: [ 0xb6, 0xc5, 0x68, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sclamp { z22.h, z23.h }, z13.h, z8.h"
+
+  -
+    input:
+      bytes: [ 0xfe, 0xc7, 0x7f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sclamp { z30.h, z31.h }, z31.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc4, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sclamp { z0.s, z1.s }, z0.s, z0.s"
+
+  -
+    input:
+      bytes: [ 0x54, 0xc5, 0xb5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sclamp { z20.s, z21.s }, z10.s, z21.s"
+
+  -
+    input:
+      bytes: [ 0xb6, 0xc5, 0xa8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sclamp { z22.s, z23.s }, z13.s, z8.s"
+
+  -
+    input:
+      bytes: [ 0xfe, 0xc7, 0xbf, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sclamp { z30.s, z31.s }, z31.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc4, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sclamp { z0.d, z1.d }, z0.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0x54, 0xc5, 0xf5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sclamp { z20.d, z21.d }, z10.d, z21.d"
+
+  -
+    input:
+      bytes: [ 0xb6, 0xc5, 0xe8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sclamp { z22.d, z23.d }, z13.d, z8.d"
+
+  -
+    input:
+      bytes: [ 0xfe, 0xc7, 0xff, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sclamp { z30.d, z31.d }, z31.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc4, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sclamp { z0.b, z1.b }, z0.b, z0.b"
+
+  -
+    input:
+      bytes: [ 0x54, 0xc5, 0x35, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sclamp { z20.b, z21.b }, z10.b, z21.b"
+
+  -
+    input:
+      bytes: [ 0xb6, 0xc5, 0x28, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sclamp { z22.b, z23.b }, z13.b, z8.b"
+
+  -
+    input:
+      bytes: [ 0xfe, 0xc7, 0x3f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sclamp { z30.b, z31.b }, z31.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0xcc, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sclamp { z0.h - z3.h }, z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x54, 0xcd, 0x75, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sclamp { z20.h - z23.h }, z10.h, z21.h"
+
+  -
+    input:
+      bytes: [ 0xb4, 0xcd, 0x68, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sclamp { z20.h - z23.h }, z13.h, z8.h"
+
+  -
+    input:
+      bytes: [ 0xfc, 0xcf, 0x7f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sclamp { z28.h - z31.h }, z31.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0xcc, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sclamp { z0.s - z3.s }, z0.s, z0.s"
+
+  -
+    input:
+      bytes: [ 0x54, 0xcd, 0xb5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sclamp { z20.s - z23.s }, z10.s, z21.s"
+
+  -
+    input:
+      bytes: [ 0xb4, 0xcd, 0xa8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sclamp { z20.s - z23.s }, z13.s, z8.s"
+
+  -
+    input:
+      bytes: [ 0xfc, 0xcf, 0xbf, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sclamp { z28.s - z31.s }, z31.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0xcc, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sclamp { z0.d - z3.d }, z0.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0x54, 0xcd, 0xf5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sclamp { z20.d - z23.d }, z10.d, z21.d"
+
+  -
+    input:
+      bytes: [ 0xb4, 0xcd, 0xe8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sclamp { z20.d - z23.d }, z13.d, z8.d"
+
+  -
+    input:
+      bytes: [ 0xfc, 0xcf, 0xff, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sclamp { z28.d - z31.d }, z31.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0xcc, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sclamp { z0.b - z3.b }, z0.b, z0.b"
+
+  -
+    input:
+      bytes: [ 0x54, 0xcd, 0x35, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sclamp { z20.b - z23.b }, z10.b, z21.b"
+
+  -
+    input:
+      bytes: [ 0xb4, 0xcd, 0x28, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sclamp { z20.b - z23.b }, z13.b, z8.b"
+
+  -
+    input:
+      bytes: [ 0xfc, 0xcf, 0x3f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sclamp { z28.b - z31.b }, z31.b, z31.b"
diff --git a/tests/MC/AArch64/SME2/scvtf.s.yaml b/tests/MC/AArch64/SME2/scvtf.s.yaml
new file mode 100644
index 000000000..3e85a643c
--- /dev/null
+++ b/tests/MC/AArch64/SME2/scvtf.s.yaml
@@ -0,0 +1,80 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x22, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "scvtf { z0.s, z1.s }, { z0.s, z1.s }"
+
+  -
+    input:
+      bytes: [ 0x54, 0xe1, 0x22, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "scvtf { z20.s, z21.s }, { z10.s, z11.s }"
+
+  -
+    input:
+      bytes: [ 0x96, 0xe1, 0x22, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "scvtf { z22.s, z23.s }, { z12.s, z13.s }"
+
+  -
+    input:
+      bytes: [ 0xde, 0xe3, 0x22, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "scvtf { z30.s, z31.s }, { z30.s, z31.s }"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x32, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "scvtf { z0.s - z3.s }, { z0.s - z3.s }"
+
+  -
+    input:
+      bytes: [ 0x14, 0xe1, 0x32, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "scvtf { z20.s - z23.s }, { z8.s - z11.s }"
+
+  -
+    input:
+      bytes: [ 0x94, 0xe1, 0x32, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "scvtf { z20.s - z23.s }, { z12.s - z15.s }"
+
+  -
+    input:
+      bytes: [ 0x9c, 0xe3, 0x32, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "scvtf { z28.s - z31.s }, { z28.s - z31.s }"
diff --git a/tests/MC/AArch64/SME2/sdot.s.yaml b/tests/MC/AArch64/SME2/sdot.s.yaml
new file mode 100644
index 000000000..6d623c6cf
--- /dev/null
+++ b/tests/MC/AArch64/SME2/sdot.s.yaml
@@ -0,0 +1,4320 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x08, 0x14, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 0, vgx2], { z0.h, z1.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x08, 0x14, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 0, vgx2], { z0.h, z1.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x4d, 0x55, 0x65, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w10, 5, vgx2], { z10.h, z11.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0x4d, 0x55, 0x65, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w10, 5, vgx2], { z10.h, z11.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0xaf, 0x75, 0x68, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w11, 7, vgx2], { z13.h, z14.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0xaf, 0x75, 0x68, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w11, 7, vgx2], { z13.h, z14.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0xef, 0x77, 0x6f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w11, 7, vgx2], { z31.h, z0.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0xef, 0x77, 0x6f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w11, 7, vgx2], { z31.h, z0.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0x2d, 0x16, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 5, vgx2], { z17.h, z18.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x2d, 0x16, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 5, vgx2], { z17.h, z18.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x29, 0x14, 0x6e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 1, vgx2], { z1.h, z2.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x29, 0x14, 0x6e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 1, vgx2], { z1.h, z2.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x68, 0x56, 0x64, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w10, 0, vgx2], { z19.h, z20.h }, z4.h"
+
+  -
+    input:
+      bytes: [ 0x68, 0x56, 0x64, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w10, 0, vgx2], { z19.h, z20.h }, z4.h"
+
+  -
+    input:
+      bytes: [ 0x88, 0x15, 0x62, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 0, vgx2], { z12.h, z13.h }, z2.h"
+
+  -
+    input:
+      bytes: [ 0x88, 0x15, 0x62, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 0, vgx2], { z12.h, z13.h }, z2.h"
+
+  -
+    input:
+      bytes: [ 0x29, 0x54, 0x6a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w10, 1, vgx2], { z1.h, z2.h }, z10.h"
+
+  -
+    input:
+      bytes: [ 0x29, 0x54, 0x6a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w10, 1, vgx2], { z1.h, z2.h }, z10.h"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x16, 0x6e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 5, vgx2], { z22.h, z23.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x16, 0x6e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 5, vgx2], { z22.h, z23.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x2a, 0x75, 0x61, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w11, 2, vgx2], { z9.h, z10.h }, z1.h"
+
+  -
+    input:
+      bytes: [ 0x2a, 0x75, 0x61, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w11, 2, vgx2], { z9.h, z10.h }, z1.h"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x35, 0x6b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w9, 7, vgx2], { z12.h, z13.h }, z11.h"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x35, 0x6b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w9, 7, vgx2], { z12.h, z13.h }, z11.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x10, 0x50, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 0, vgx2], { z0.h, z1.h }, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x10, 0x50, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 0, vgx2], { z0.h, z1.h }, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x45, 0x55, 0x55, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w10, 5, vgx2], { z10.h, z11.h }, z5.h[1]"
+
+  -
+    input:
+      bytes: [ 0x45, 0x55, 0x55, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w10, 5, vgx2], { z10.h, z11.h }, z5.h[1]"
+
+  -
+    input:
+      bytes: [ 0x87, 0x7d, 0x58, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w11, 7, vgx2], { z12.h, z13.h }, z8.h[3]"
+
+  -
+    input:
+      bytes: [ 0x87, 0x7d, 0x58, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w11, 7, vgx2], { z12.h, z13.h }, z8.h[3]"
+
+  -
+    input:
+      bytes: [ 0xc7, 0x7f, 0x5f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w11, 7, vgx2], { z30.h, z31.h }, z15.h[3]"
+
+  -
+    input:
+      bytes: [ 0xc7, 0x7f, 0x5f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w11, 7, vgx2], { z30.h, z31.h }, z15.h[3]"
+
+  -
+    input:
+      bytes: [ 0x05, 0x1e, 0x50, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 5, vgx2], { z16.h, z17.h }, z0.h[3]"
+
+  -
+    input:
+      bytes: [ 0x05, 0x1e, 0x50, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 5, vgx2], { z16.h, z17.h }, z0.h[3]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x14, 0x5e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 1, vgx2], { z0.h, z1.h }, z14.h[1]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x14, 0x5e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 1, vgx2], { z0.h, z1.h }, z14.h[1]"
+
+  -
+    input:
+      bytes: [ 0x40, 0x56, 0x54, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w10, 0, vgx2], { z18.h, z19.h }, z4.h[1]"
+
+  -
+    input:
+      bytes: [ 0x40, 0x56, 0x54, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w10, 0, vgx2], { z18.h, z19.h }, z4.h[1]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x19, 0x52, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 0, vgx2], { z12.h, z13.h }, z2.h[2]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x19, 0x52, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 0, vgx2], { z12.h, z13.h }, z2.h[2]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x58, 0x5a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w10, 1, vgx2], { z0.h, z1.h }, z10.h[2]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x58, 0x5a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w10, 1, vgx2], { z0.h, z1.h }, z10.h[2]"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x1a, 0x5e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 5, vgx2], { z22.h, z23.h }, z14.h[2]"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x1a, 0x5e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 5, vgx2], { z22.h, z23.h }, z14.h[2]"
+
+  -
+    input:
+      bytes: [ 0x02, 0x75, 0x51, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w11, 2, vgx2], { z8.h, z9.h }, z1.h[1]"
+
+  -
+    input:
+      bytes: [ 0x02, 0x75, 0x51, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w11, 2, vgx2], { z8.h, z9.h }, z1.h[1]"
+
+  -
+    input:
+      bytes: [ 0x87, 0x39, 0x5b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w9, 7, vgx2], { z12.h, z13.h }, z11.h[2]"
+
+  -
+    input:
+      bytes: [ 0x87, 0x39, 0x5b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w9, 7, vgx2], { z12.h, z13.h }, z11.h[2]"
+
+  -
+    input:
+      bytes: [ 0x08, 0x14, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 0, vgx2], { z0.h, z1.h }, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x08, 0x14, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 0, vgx2], { z0.h, z1.h }, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x4d, 0x55, 0xf4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w10, 5, vgx2], { z10.h, z11.h }, { z20.h, z21.h }"
+
+  -
+    input:
+      bytes: [ 0x4d, 0x55, 0xf4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w10, 5, vgx2], { z10.h, z11.h }, { z20.h, z21.h }"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x75, 0xe8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w11, 7, vgx2], { z12.h, z13.h }, { z8.h, z9.h }"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x75, 0xe8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w11, 7, vgx2], { z12.h, z13.h }, { z8.h, z9.h }"
+
+  -
+    input:
+      bytes: [ 0xcf, 0x77, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w11, 7, vgx2], { z30.h, z31.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0xcf, 0x77, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w11, 7, vgx2], { z30.h, z31.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x0d, 0x16, 0xf0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 5, vgx2], { z16.h, z17.h }, { z16.h, z17.h }"
+
+  -
+    input:
+      bytes: [ 0x0d, 0x16, 0xf0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 5, vgx2], { z16.h, z17.h }, { z16.h, z17.h }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x14, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 1, vgx2], { z0.h, z1.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x14, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 1, vgx2], { z0.h, z1.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x48, 0x56, 0xf4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w10, 0, vgx2], { z18.h, z19.h }, { z20.h, z21.h }"
+
+  -
+    input:
+      bytes: [ 0x48, 0x56, 0xf4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w10, 0, vgx2], { z18.h, z19.h }, { z20.h, z21.h }"
+
+  -
+    input:
+      bytes: [ 0x88, 0x15, 0xe2, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 0, vgx2], { z12.h, z13.h }, { z2.h, z3.h }"
+
+  -
+    input:
+      bytes: [ 0x88, 0x15, 0xe2, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 0, vgx2], { z12.h, z13.h }, { z2.h, z3.h }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x54, 0xfa, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w10, 1, vgx2], { z0.h, z1.h }, { z26.h, z27.h }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x54, 0xfa, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w10, 1, vgx2], { z0.h, z1.h }, { z26.h, z27.h }"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x16, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 5, vgx2], { z22.h, z23.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x16, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 5, vgx2], { z22.h, z23.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x0a, 0x75, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w11, 2, vgx2], { z8.h, z9.h }, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x0a, 0x75, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w11, 2, vgx2], { z8.h, z9.h }, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x35, 0xea, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w9, 7, vgx2], { z12.h, z13.h }, { z10.h, z11.h }"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x35, 0xea, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w9, 7, vgx2], { z12.h, z13.h }, { z10.h, z11.h }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x14, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 0, vgx2], { z0.b, z1.b }, z0.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x14, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 0, vgx2], { z0.b, z1.b }, z0.b"
+
+  -
+    input:
+      bytes: [ 0x45, 0x55, 0x25, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w10, 5, vgx2], { z10.b, z11.b }, z5.b"
+
+  -
+    input:
+      bytes: [ 0x45, 0x55, 0x25, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w10, 5, vgx2], { z10.b, z11.b }, z5.b"
+
+  -
+    input:
+      bytes: [ 0xa7, 0x75, 0x28, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w11, 7, vgx2], { z13.b, z14.b }, z8.b"
+
+  -
+    input:
+      bytes: [ 0xa7, 0x75, 0x28, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w11, 7, vgx2], { z13.b, z14.b }, z8.b"
+
+  -
+    input:
+      bytes: [ 0xe7, 0x77, 0x2f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w11, 7, vgx2], { z31.b, z0.b }, z15.b"
+
+  -
+    input:
+      bytes: [ 0xe7, 0x77, 0x2f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w11, 7, vgx2], { z31.b, z0.b }, z15.b"
+
+  -
+    input:
+      bytes: [ 0x25, 0x16, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 5, vgx2], { z17.b, z18.b }, z0.b"
+
+  -
+    input:
+      bytes: [ 0x25, 0x16, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 5, vgx2], { z17.b, z18.b }, z0.b"
+
+  -
+    input:
+      bytes: [ 0x21, 0x14, 0x2e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 1, vgx2], { z1.b, z2.b }, z14.b"
+
+  -
+    input:
+      bytes: [ 0x21, 0x14, 0x2e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 1, vgx2], { z1.b, z2.b }, z14.b"
+
+  -
+    input:
+      bytes: [ 0x60, 0x56, 0x24, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w10, 0, vgx2], { z19.b, z20.b }, z4.b"
+
+  -
+    input:
+      bytes: [ 0x60, 0x56, 0x24, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w10, 0, vgx2], { z19.b, z20.b }, z4.b"
+
+  -
+    input:
+      bytes: [ 0x80, 0x15, 0x22, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 0, vgx2], { z12.b, z13.b }, z2.b"
+
+  -
+    input:
+      bytes: [ 0x80, 0x15, 0x22, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 0, vgx2], { z12.b, z13.b }, z2.b"
+
+  -
+    input:
+      bytes: [ 0x21, 0x54, 0x2a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w10, 1, vgx2], { z1.b, z2.b }, z10.b"
+
+  -
+    input:
+      bytes: [ 0x21, 0x54, 0x2a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w10, 1, vgx2], { z1.b, z2.b }, z10.b"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x16, 0x2e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 5, vgx2], { z22.b, z23.b }, z14.b"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x16, 0x2e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 5, vgx2], { z22.b, z23.b }, z14.b"
+
+  -
+    input:
+      bytes: [ 0x22, 0x75, 0x21, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w11, 2, vgx2], { z9.b, z10.b }, z1.b"
+
+  -
+    input:
+      bytes: [ 0x22, 0x75, 0x21, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w11, 2, vgx2], { z9.b, z10.b }, z1.b"
+
+  -
+    input:
+      bytes: [ 0x87, 0x35, 0x2b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w9, 7, vgx2], { z12.b, z13.b }, z11.b"
+
+  -
+    input:
+      bytes: [ 0x87, 0x35, 0x2b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w9, 7, vgx2], { z12.b, z13.b }, z11.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x10, 0x50, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 0, vgx2], { z0.b, z1.b }, z0.b[0]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x10, 0x50, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 0, vgx2], { z0.b, z1.b }, z0.b[0]"
+
+  -
+    input:
+      bytes: [ 0x65, 0x55, 0x55, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w10, 5, vgx2], { z10.b, z11.b }, z5.b[1]"
+
+  -
+    input:
+      bytes: [ 0x65, 0x55, 0x55, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w10, 5, vgx2], { z10.b, z11.b }, z5.b[1]"
+
+  -
+    input:
+      bytes: [ 0xa7, 0x7d, 0x58, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w11, 7, vgx2], { z12.b, z13.b }, z8.b[3]"
+
+  -
+    input:
+      bytes: [ 0xa7, 0x7d, 0x58, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w11, 7, vgx2], { z12.b, z13.b }, z8.b[3]"
+
+  -
+    input:
+      bytes: [ 0xe7, 0x7f, 0x5f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w11, 7, vgx2], { z30.b, z31.b }, z15.b[3]"
+
+  -
+    input:
+      bytes: [ 0xe7, 0x7f, 0x5f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w11, 7, vgx2], { z30.b, z31.b }, z15.b[3]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x1e, 0x50, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 5, vgx2], { z16.b, z17.b }, z0.b[3]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x1e, 0x50, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 5, vgx2], { z16.b, z17.b }, z0.b[3]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x14, 0x5e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 1, vgx2], { z0.b, z1.b }, z14.b[1]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x14, 0x5e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 1, vgx2], { z0.b, z1.b }, z14.b[1]"
+
+  -
+    input:
+      bytes: [ 0x60, 0x56, 0x54, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w10, 0, vgx2], { z18.b, z19.b }, z4.b[1]"
+
+  -
+    input:
+      bytes: [ 0x60, 0x56, 0x54, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w10, 0, vgx2], { z18.b, z19.b }, z4.b[1]"
+
+  -
+    input:
+      bytes: [ 0xa0, 0x19, 0x52, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 0, vgx2], { z12.b, z13.b }, z2.b[2]"
+
+  -
+    input:
+      bytes: [ 0xa0, 0x19, 0x52, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 0, vgx2], { z12.b, z13.b }, z2.b[2]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x58, 0x5a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w10, 1, vgx2], { z0.b, z1.b }, z10.b[2]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x58, 0x5a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w10, 1, vgx2], { z0.b, z1.b }, z10.b[2]"
+
+  -
+    input:
+      bytes: [ 0xe5, 0x1a, 0x5e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 5, vgx2], { z22.b, z23.b }, z14.b[2]"
+
+  -
+    input:
+      bytes: [ 0xe5, 0x1a, 0x5e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 5, vgx2], { z22.b, z23.b }, z14.b[2]"
+
+  -
+    input:
+      bytes: [ 0x22, 0x75, 0x51, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w11, 2, vgx2], { z8.b, z9.b }, z1.b[1]"
+
+  -
+    input:
+      bytes: [ 0x22, 0x75, 0x51, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w11, 2, vgx2], { z8.b, z9.b }, z1.b[1]"
+
+  -
+    input:
+      bytes: [ 0xa7, 0x39, 0x5b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w9, 7, vgx2], { z12.b, z13.b }, z11.b[2]"
+
+  -
+    input:
+      bytes: [ 0xa7, 0x39, 0x5b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w9, 7, vgx2], { z12.b, z13.b }, z11.b[2]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x14, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 0, vgx2], { z0.b, z1.b }, { z0.b, z1.b }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x14, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 0, vgx2], { z0.b, z1.b }, { z0.b, z1.b }"
+
+  -
+    input:
+      bytes: [ 0x45, 0x55, 0xb4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w10, 5, vgx2], { z10.b, z11.b }, { z20.b, z21.b }"
+
+  -
+    input:
+      bytes: [ 0x45, 0x55, 0xb4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w10, 5, vgx2], { z10.b, z11.b }, { z20.b, z21.b }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x75, 0xa8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w11, 7, vgx2], { z12.b, z13.b }, { z8.b, z9.b }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x75, 0xa8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w11, 7, vgx2], { z12.b, z13.b }, { z8.b, z9.b }"
+
+  -
+    input:
+      bytes: [ 0xc7, 0x77, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w11, 7, vgx2], { z30.b, z31.b }, { z30.b, z31.b }"
+
+  -
+    input:
+      bytes: [ 0xc7, 0x77, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w11, 7, vgx2], { z30.b, z31.b }, { z30.b, z31.b }"
+
+  -
+    input:
+      bytes: [ 0x05, 0x16, 0xb0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 5, vgx2], { z16.b, z17.b }, { z16.b, z17.b }"
+
+  -
+    input:
+      bytes: [ 0x05, 0x16, 0xb0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 5, vgx2], { z16.b, z17.b }, { z16.b, z17.b }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x14, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 1, vgx2], { z0.b, z1.b }, { z30.b, z31.b }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x14, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 1, vgx2], { z0.b, z1.b }, { z30.b, z31.b }"
+
+  -
+    input:
+      bytes: [ 0x40, 0x56, 0xb4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w10, 0, vgx2], { z18.b, z19.b }, { z20.b, z21.b }"
+
+  -
+    input:
+      bytes: [ 0x40, 0x56, 0xb4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w10, 0, vgx2], { z18.b, z19.b }, { z20.b, z21.b }"
+
+  -
+    input:
+      bytes: [ 0x80, 0x15, 0xa2, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 0, vgx2], { z12.b, z13.b }, { z2.b, z3.b }"
+
+  -
+    input:
+      bytes: [ 0x80, 0x15, 0xa2, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 0, vgx2], { z12.b, z13.b }, { z2.b, z3.b }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x54, 0xba, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w10, 1, vgx2], { z0.b, z1.b }, { z26.b, z27.b }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x54, 0xba, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w10, 1, vgx2], { z0.b, z1.b }, { z26.b, z27.b }"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x16, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 5, vgx2], { z22.b, z23.b }, { z30.b, z31.b }"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x16, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 5, vgx2], { z22.b, z23.b }, { z30.b, z31.b }"
+
+  -
+    input:
+      bytes: [ 0x02, 0x75, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w11, 2, vgx2], { z8.b, z9.b }, { z0.b, z1.b }"
+
+  -
+    input:
+      bytes: [ 0x02, 0x75, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w11, 2, vgx2], { z8.b, z9.b }, { z0.b, z1.b }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x35, 0xaa, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w9, 7, vgx2], { z12.b, z13.b }, { z10.b, z11.b }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x35, 0xaa, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w9, 7, vgx2], { z12.b, z13.b }, { z10.b, z11.b }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x14, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w8, 0, vgx2], { z0.h, z1.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x14, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w8, 0, vgx2], { z0.h, z1.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x45, 0x55, 0x65, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w10, 5, vgx2], { z10.h, z11.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0x45, 0x55, 0x65, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w10, 5, vgx2], { z10.h, z11.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0xa7, 0x75, 0x68, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w11, 7, vgx2], { z13.h, z14.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0xa7, 0x75, 0x68, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w11, 7, vgx2], { z13.h, z14.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0xe7, 0x77, 0x6f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w11, 7, vgx2], { z31.h, z0.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0xe7, 0x77, 0x6f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w11, 7, vgx2], { z31.h, z0.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0x25, 0x16, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w8, 5, vgx2], { z17.h, z18.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x25, 0x16, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w8, 5, vgx2], { z17.h, z18.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x21, 0x14, 0x6e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w8, 1, vgx2], { z1.h, z2.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x21, 0x14, 0x6e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w8, 1, vgx2], { z1.h, z2.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x60, 0x56, 0x64, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w10, 0, vgx2], { z19.h, z20.h }, z4.h"
+
+  -
+    input:
+      bytes: [ 0x60, 0x56, 0x64, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w10, 0, vgx2], { z19.h, z20.h }, z4.h"
+
+  -
+    input:
+      bytes: [ 0x80, 0x15, 0x62, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w8, 0, vgx2], { z12.h, z13.h }, z2.h"
+
+  -
+    input:
+      bytes: [ 0x80, 0x15, 0x62, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w8, 0, vgx2], { z12.h, z13.h }, z2.h"
+
+  -
+    input:
+      bytes: [ 0x21, 0x54, 0x6a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w10, 1, vgx2], { z1.h, z2.h }, z10.h"
+
+  -
+    input:
+      bytes: [ 0x21, 0x54, 0x6a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w10, 1, vgx2], { z1.h, z2.h }, z10.h"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x16, 0x6e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w8, 5, vgx2], { z22.h, z23.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x16, 0x6e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w8, 5, vgx2], { z22.h, z23.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x22, 0x75, 0x61, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w11, 2, vgx2], { z9.h, z10.h }, z1.h"
+
+  -
+    input:
+      bytes: [ 0x22, 0x75, 0x61, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w11, 2, vgx2], { z9.h, z10.h }, z1.h"
+
+  -
+    input:
+      bytes: [ 0x87, 0x35, 0x6b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w9, 7, vgx2], { z12.h, z13.h }, z11.h"
+
+  -
+    input:
+      bytes: [ 0x87, 0x35, 0x6b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w9, 7, vgx2], { z12.h, z13.h }, z11.h"
+
+  -
+    input:
+      bytes: [ 0x08, 0x00, 0xd0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w8, 0, vgx2], { z0.h, z1.h }, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x08, 0x00, 0xd0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w8, 0, vgx2], { z0.h, z1.h }, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x4d, 0x45, 0xd5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w10, 5, vgx2], { z10.h, z11.h }, z5.h[1]"
+
+  -
+    input:
+      bytes: [ 0x4d, 0x45, 0xd5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w10, 5, vgx2], { z10.h, z11.h }, z5.h[1]"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x65, 0xd8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w11, 7, vgx2], { z12.h, z13.h }, z8.h[1]"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x65, 0xd8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w11, 7, vgx2], { z12.h, z13.h }, z8.h[1]"
+
+  -
+    input:
+      bytes: [ 0xcf, 0x67, 0xdf, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w11, 7, vgx2], { z30.h, z31.h }, z15.h[1]"
+
+  -
+    input:
+      bytes: [ 0xcf, 0x67, 0xdf, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w11, 7, vgx2], { z30.h, z31.h }, z15.h[1]"
+
+  -
+    input:
+      bytes: [ 0x0d, 0x06, 0xd0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w8, 5, vgx2], { z16.h, z17.h }, z0.h[1]"
+
+  -
+    input:
+      bytes: [ 0x0d, 0x06, 0xd0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w8, 5, vgx2], { z16.h, z17.h }, z0.h[1]"
+
+  -
+    input:
+      bytes: [ 0x09, 0x04, 0xde, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w8, 1, vgx2], { z0.h, z1.h }, z14.h[1]"
+
+  -
+    input:
+      bytes: [ 0x09, 0x04, 0xde, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w8, 1, vgx2], { z0.h, z1.h }, z14.h[1]"
+
+  -
+    input:
+      bytes: [ 0x48, 0x46, 0xd4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w10, 0, vgx2], { z18.h, z19.h }, z4.h[1]"
+
+  -
+    input:
+      bytes: [ 0x48, 0x46, 0xd4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w10, 0, vgx2], { z18.h, z19.h }, z4.h[1]"
+
+  -
+    input:
+      bytes: [ 0x88, 0x01, 0xd2, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w8, 0, vgx2], { z12.h, z13.h }, z2.h[0]"
+
+  -
+    input:
+      bytes: [ 0x88, 0x01, 0xd2, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w8, 0, vgx2], { z12.h, z13.h }, z2.h[0]"
+
+  -
+    input:
+      bytes: [ 0x09, 0x40, 0xda, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w10, 1, vgx2], { z0.h, z1.h }, z10.h[0]"
+
+  -
+    input:
+      bytes: [ 0x09, 0x40, 0xda, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w10, 1, vgx2], { z0.h, z1.h }, z10.h[0]"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x02, 0xde, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w8, 5, vgx2], { z22.h, z23.h }, z14.h[0]"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x02, 0xde, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w8, 5, vgx2], { z22.h, z23.h }, z14.h[0]"
+
+  -
+    input:
+      bytes: [ 0x0a, 0x65, 0xd1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w11, 2, vgx2], { z8.h, z9.h }, z1.h[1]"
+
+  -
+    input:
+      bytes: [ 0x0a, 0x65, 0xd1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w11, 2, vgx2], { z8.h, z9.h }, z1.h[1]"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x21, 0xdb, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w9, 7, vgx2], { z12.h, z13.h }, z11.h[0]"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x21, 0xdb, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w9, 7, vgx2], { z12.h, z13.h }, z11.h[0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x14, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w8, 0, vgx2], { z0.h, z1.h }, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x14, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w8, 0, vgx2], { z0.h, z1.h }, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x45, 0x55, 0xf4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w10, 5, vgx2], { z10.h, z11.h }, { z20.h, z21.h }"
+
+  -
+    input:
+      bytes: [ 0x45, 0x55, 0xf4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w10, 5, vgx2], { z10.h, z11.h }, { z20.h, z21.h }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x75, 0xe8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w11, 7, vgx2], { z12.h, z13.h }, { z8.h, z9.h }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x75, 0xe8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w11, 7, vgx2], { z12.h, z13.h }, { z8.h, z9.h }"
+
+  -
+    input:
+      bytes: [ 0xc7, 0x77, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w11, 7, vgx2], { z30.h, z31.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0xc7, 0x77, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w11, 7, vgx2], { z30.h, z31.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x05, 0x16, 0xf0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w8, 5, vgx2], { z16.h, z17.h }, { z16.h, z17.h }"
+
+  -
+    input:
+      bytes: [ 0x05, 0x16, 0xf0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w8, 5, vgx2], { z16.h, z17.h }, { z16.h, z17.h }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x14, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w8, 1, vgx2], { z0.h, z1.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x14, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w8, 1, vgx2], { z0.h, z1.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x40, 0x56, 0xf4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w10, 0, vgx2], { z18.h, z19.h }, { z20.h, z21.h }"
+
+  -
+    input:
+      bytes: [ 0x40, 0x56, 0xf4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w10, 0, vgx2], { z18.h, z19.h }, { z20.h, z21.h }"
+
+  -
+    input:
+      bytes: [ 0x80, 0x15, 0xe2, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w8, 0, vgx2], { z12.h, z13.h }, { z2.h, z3.h }"
+
+  -
+    input:
+      bytes: [ 0x80, 0x15, 0xe2, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w8, 0, vgx2], { z12.h, z13.h }, { z2.h, z3.h }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x54, 0xfa, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w10, 1, vgx2], { z0.h, z1.h }, { z26.h, z27.h }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x54, 0xfa, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w10, 1, vgx2], { z0.h, z1.h }, { z26.h, z27.h }"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x16, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w8, 5, vgx2], { z22.h, z23.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x16, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w8, 5, vgx2], { z22.h, z23.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x02, 0x75, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w11, 2, vgx2], { z8.h, z9.h }, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x02, 0x75, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w11, 2, vgx2], { z8.h, z9.h }, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x35, 0xea, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w9, 7, vgx2], { z12.h, z13.h }, { z10.h, z11.h }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x35, 0xea, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w9, 7, vgx2], { z12.h, z13.h }, { z10.h, z11.h }"
+
+  -
+    input:
+      bytes: [ 0x08, 0x14, 0x70, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 0, vgx4], { z0.h - z3.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x08, 0x14, 0x70, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 0, vgx4], { z0.h - z3.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x4d, 0x55, 0x75, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w10, 5, vgx4], { z10.h - z13.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0x4d, 0x55, 0x75, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w10, 5, vgx4], { z10.h - z13.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0xaf, 0x75, 0x78, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w11, 7, vgx4], { z13.h - z16.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0xaf, 0x75, 0x78, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w11, 7, vgx4], { z13.h - z16.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0xef, 0x77, 0x7f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w11, 7, vgx4], { z31.h, z0.h, z1.h, z2.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0xef, 0x77, 0x7f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w11, 7, vgx4], { z31.h, z0.h, z1.h, z2.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0x2d, 0x16, 0x70, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 5, vgx4], { z17.h - z20.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x2d, 0x16, 0x70, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 5, vgx4], { z17.h - z20.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x29, 0x14, 0x7e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 1, vgx4], { z1.h - z4.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x29, 0x14, 0x7e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 1, vgx4], { z1.h - z4.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x68, 0x56, 0x74, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w10, 0, vgx4], { z19.h - z22.h }, z4.h"
+
+  -
+    input:
+      bytes: [ 0x68, 0x56, 0x74, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w10, 0, vgx4], { z19.h - z22.h }, z4.h"
+
+  -
+    input:
+      bytes: [ 0x88, 0x15, 0x72, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 0, vgx4], { z12.h - z15.h }, z2.h"
+
+  -
+    input:
+      bytes: [ 0x88, 0x15, 0x72, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 0, vgx4], { z12.h - z15.h }, z2.h"
+
+  -
+    input:
+      bytes: [ 0x29, 0x54, 0x7a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w10, 1, vgx4], { z1.h - z4.h }, z10.h"
+
+  -
+    input:
+      bytes: [ 0x29, 0x54, 0x7a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w10, 1, vgx4], { z1.h - z4.h }, z10.h"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x16, 0x7e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 5, vgx4], { z22.h - z25.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x16, 0x7e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 5, vgx4], { z22.h - z25.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x2a, 0x75, 0x71, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w11, 2, vgx4], { z9.h - z12.h }, z1.h"
+
+  -
+    input:
+      bytes: [ 0x2a, 0x75, 0x71, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w11, 2, vgx4], { z9.h - z12.h }, z1.h"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x35, 0x7b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w9, 7, vgx4], { z12.h - z15.h }, z11.h"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x35, 0x7b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w9, 7, vgx4], { z12.h - z15.h }, z11.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x90, 0x50, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 0, vgx4], { z0.h - z3.h }, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x90, 0x50, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 0, vgx4], { z0.h - z3.h }, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x05, 0xd5, 0x55, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w10, 5, vgx4], { z8.h - z11.h }, z5.h[1]"
+
+  -
+    input:
+      bytes: [ 0x05, 0xd5, 0x55, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w10, 5, vgx4], { z8.h - z11.h }, z5.h[1]"
+
+  -
+    input:
+      bytes: [ 0x87, 0xfd, 0x58, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w11, 7, vgx4], { z12.h - z15.h }, z8.h[3]"
+
+  -
+    input:
+      bytes: [ 0x87, 0xfd, 0x58, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w11, 7, vgx4], { z12.h - z15.h }, z8.h[3]"
+
+  -
+    input:
+      bytes: [ 0x87, 0xff, 0x5f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w11, 7, vgx4], { z28.h - z31.h }, z15.h[3]"
+
+  -
+    input:
+      bytes: [ 0x87, 0xff, 0x5f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w11, 7, vgx4], { z28.h - z31.h }, z15.h[3]"
+
+  -
+    input:
+      bytes: [ 0x05, 0x9e, 0x50, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 5, vgx4], { z16.h - z19.h }, z0.h[3]"
+
+  -
+    input:
+      bytes: [ 0x05, 0x9e, 0x50, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 5, vgx4], { z16.h - z19.h }, z0.h[3]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x94, 0x5e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 1, vgx4], { z0.h - z3.h }, z14.h[1]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x94, 0x5e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 1, vgx4], { z0.h - z3.h }, z14.h[1]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd6, 0x54, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w10, 0, vgx4], { z16.h - z19.h }, z4.h[1]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd6, 0x54, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w10, 0, vgx4], { z16.h - z19.h }, z4.h[1]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x99, 0x52, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 0, vgx4], { z12.h - z15.h }, z2.h[2]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x99, 0x52, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 0, vgx4], { z12.h - z15.h }, z2.h[2]"
+
+  -
+    input:
+      bytes: [ 0x01, 0xd8, 0x5a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w10, 1, vgx4], { z0.h - z3.h }, z10.h[2]"
+
+  -
+    input:
+      bytes: [ 0x01, 0xd8, 0x5a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w10, 1, vgx4], { z0.h - z3.h }, z10.h[2]"
+
+  -
+    input:
+      bytes: [ 0x85, 0x9a, 0x5e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 5, vgx4], { z20.h - z23.h }, z14.h[2]"
+
+  -
+    input:
+      bytes: [ 0x85, 0x9a, 0x5e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 5, vgx4], { z20.h - z23.h }, z14.h[2]"
+
+  -
+    input:
+      bytes: [ 0x02, 0xf5, 0x51, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w11, 2, vgx4], { z8.h - z11.h }, z1.h[1]"
+
+  -
+    input:
+      bytes: [ 0x02, 0xf5, 0x51, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w11, 2, vgx4], { z8.h - z11.h }, z1.h[1]"
+
+  -
+    input:
+      bytes: [ 0x87, 0xb9, 0x5b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w9, 7, vgx4], { z12.h - z15.h }, z11.h[2]"
+
+  -
+    input:
+      bytes: [ 0x87, 0xb9, 0x5b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w9, 7, vgx4], { z12.h - z15.h }, z11.h[2]"
+
+  -
+    input:
+      bytes: [ 0x08, 0x14, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 0, vgx4], { z0.h - z3.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x08, 0x14, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 0, vgx4], { z0.h - z3.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x0d, 0x55, 0xf5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w10, 5, vgx4], { z8.h - z11.h }, { z20.h - z23.h }"
+
+  -
+    input:
+      bytes: [ 0x0d, 0x55, 0xf5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w10, 5, vgx4], { z8.h - z11.h }, { z20.h - z23.h }"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x75, 0xe9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w11, 7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x75, 0xe9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w11, 7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x77, 0xfd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w11, 7, vgx4], { z28.h - z31.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x77, 0xfd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w11, 7, vgx4], { z28.h - z31.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x0d, 0x16, 0xf1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 5, vgx4], { z16.h - z19.h }, { z16.h - z19.h }"
+
+  -
+    input:
+      bytes: [ 0x0d, 0x16, 0xf1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 5, vgx4], { z16.h - z19.h }, { z16.h - z19.h }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x14, 0xfd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 1, vgx4], { z0.h - z3.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x14, 0xfd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 1, vgx4], { z0.h - z3.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x08, 0x56, 0xf5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w10, 0, vgx4], { z16.h - z19.h }, { z20.h - z23.h }"
+
+  -
+    input:
+      bytes: [ 0x08, 0x56, 0xf5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w10, 0, vgx4], { z16.h - z19.h }, { z20.h - z23.h }"
+
+  -
+    input:
+      bytes: [ 0x88, 0x15, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 0, vgx4], { z12.h - z15.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x88, 0x15, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 0, vgx4], { z12.h - z15.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x54, 0xf9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w10, 1, vgx4], { z0.h - z3.h }, { z24.h - z27.h }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x54, 0xf9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w10, 1, vgx4], { z0.h - z3.h }, { z24.h - z27.h }"
+
+  -
+    input:
+      bytes: [ 0x8d, 0x16, 0xfd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 5, vgx4], { z20.h - z23.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x8d, 0x16, 0xfd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 5, vgx4], { z20.h - z23.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x0a, 0x75, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w11, 2, vgx4], { z8.h - z11.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x0a, 0x75, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w11, 2, vgx4], { z8.h - z11.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x35, 0xe9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w9, 7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x35, 0xe9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w9, 7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x14, 0x30, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 0, vgx4], { z0.b - z3.b }, z0.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x14, 0x30, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 0, vgx4], { z0.b - z3.b }, z0.b"
+
+  -
+    input:
+      bytes: [ 0x45, 0x55, 0x35, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w10, 5, vgx4], { z10.b - z13.b }, z5.b"
+
+  -
+    input:
+      bytes: [ 0x45, 0x55, 0x35, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w10, 5, vgx4], { z10.b - z13.b }, z5.b"
+
+  -
+    input:
+      bytes: [ 0xa7, 0x75, 0x38, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w11, 7, vgx4], { z13.b - z16.b }, z8.b"
+
+  -
+    input:
+      bytes: [ 0xa7, 0x75, 0x38, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w11, 7, vgx4], { z13.b - z16.b }, z8.b"
+
+  -
+    input:
+      bytes: [ 0xe7, 0x77, 0x3f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w11, 7, vgx4], { z31.b, z0.b, z1.b, z2.b }, z15.b"
+
+  -
+    input:
+      bytes: [ 0xe7, 0x77, 0x3f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w11, 7, vgx4], { z31.b, z0.b, z1.b, z2.b }, z15.b"
+
+  -
+    input:
+      bytes: [ 0x25, 0x16, 0x30, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 5, vgx4], { z17.b - z20.b }, z0.b"
+
+  -
+    input:
+      bytes: [ 0x25, 0x16, 0x30, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 5, vgx4], { z17.b - z20.b }, z0.b"
+
+  -
+    input:
+      bytes: [ 0x21, 0x14, 0x3e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 1, vgx4], { z1.b - z4.b }, z14.b"
+
+  -
+    input:
+      bytes: [ 0x21, 0x14, 0x3e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 1, vgx4], { z1.b - z4.b }, z14.b"
+
+  -
+    input:
+      bytes: [ 0x60, 0x56, 0x34, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w10, 0, vgx4], { z19.b - z22.b }, z4.b"
+
+  -
+    input:
+      bytes: [ 0x60, 0x56, 0x34, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w10, 0, vgx4], { z19.b - z22.b }, z4.b"
+
+  -
+    input:
+      bytes: [ 0x80, 0x15, 0x32, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 0, vgx4], { z12.b - z15.b }, z2.b"
+
+  -
+    input:
+      bytes: [ 0x80, 0x15, 0x32, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 0, vgx4], { z12.b - z15.b }, z2.b"
+
+  -
+    input:
+      bytes: [ 0x21, 0x54, 0x3a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w10, 1, vgx4], { z1.b - z4.b }, z10.b"
+
+  -
+    input:
+      bytes: [ 0x21, 0x54, 0x3a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w10, 1, vgx4], { z1.b - z4.b }, z10.b"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x16, 0x3e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 5, vgx4], { z22.b - z25.b }, z14.b"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x16, 0x3e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 5, vgx4], { z22.b - z25.b }, z14.b"
+
+  -
+    input:
+      bytes: [ 0x22, 0x75, 0x31, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w11, 2, vgx4], { z9.b - z12.b }, z1.b"
+
+  -
+    input:
+      bytes: [ 0x22, 0x75, 0x31, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w11, 2, vgx4], { z9.b - z12.b }, z1.b"
+
+  -
+    input:
+      bytes: [ 0x87, 0x35, 0x3b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w9, 7, vgx4], { z12.b - z15.b }, z11.b"
+
+  -
+    input:
+      bytes: [ 0x87, 0x35, 0x3b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w9, 7, vgx4], { z12.b - z15.b }, z11.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x90, 0x50, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 0, vgx4], { z0.b - z3.b }, z0.b[0]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x90, 0x50, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 0, vgx4], { z0.b - z3.b }, z0.b[0]"
+
+  -
+    input:
+      bytes: [ 0x25, 0xd5, 0x55, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w10, 5, vgx4], { z8.b - z11.b }, z5.b[1]"
+
+  -
+    input:
+      bytes: [ 0x25, 0xd5, 0x55, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w10, 5, vgx4], { z8.b - z11.b }, z5.b[1]"
+
+  -
+    input:
+      bytes: [ 0xa7, 0xfd, 0x58, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w11, 7, vgx4], { z12.b - z15.b }, z8.b[3]"
+
+  -
+    input:
+      bytes: [ 0xa7, 0xfd, 0x58, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w11, 7, vgx4], { z12.b - z15.b }, z8.b[3]"
+
+  -
+    input:
+      bytes: [ 0xa7, 0xff, 0x5f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w11, 7, vgx4], { z28.b - z31.b }, z15.b[3]"
+
+  -
+    input:
+      bytes: [ 0xa7, 0xff, 0x5f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w11, 7, vgx4], { z28.b - z31.b }, z15.b[3]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x9e, 0x50, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 5, vgx4], { z16.b - z19.b }, z0.b[3]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x9e, 0x50, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 5, vgx4], { z16.b - z19.b }, z0.b[3]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x94, 0x5e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 1, vgx4], { z0.b - z3.b }, z14.b[1]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x94, 0x5e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 1, vgx4], { z0.b - z3.b }, z14.b[1]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd6, 0x54, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w10, 0, vgx4], { z16.b - z19.b }, z4.b[1]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd6, 0x54, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w10, 0, vgx4], { z16.b - z19.b }, z4.b[1]"
+
+  -
+    input:
+      bytes: [ 0xa0, 0x99, 0x52, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 0, vgx4], { z12.b - z15.b }, z2.b[2]"
+
+  -
+    input:
+      bytes: [ 0xa0, 0x99, 0x52, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 0, vgx4], { z12.b - z15.b }, z2.b[2]"
+
+  -
+    input:
+      bytes: [ 0x21, 0xd8, 0x5a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w10, 1, vgx4], { z0.b - z3.b }, z10.b[2]"
+
+  -
+    input:
+      bytes: [ 0x21, 0xd8, 0x5a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w10, 1, vgx4], { z0.b - z3.b }, z10.b[2]"
+
+  -
+    input:
+      bytes: [ 0xa5, 0x9a, 0x5e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 5, vgx4], { z20.b - z23.b }, z14.b[2]"
+
+  -
+    input:
+      bytes: [ 0xa5, 0x9a, 0x5e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 5, vgx4], { z20.b - z23.b }, z14.b[2]"
+
+  -
+    input:
+      bytes: [ 0x22, 0xf5, 0x51, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w11, 2, vgx4], { z8.b - z11.b }, z1.b[1]"
+
+  -
+    input:
+      bytes: [ 0x22, 0xf5, 0x51, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w11, 2, vgx4], { z8.b - z11.b }, z1.b[1]"
+
+  -
+    input:
+      bytes: [ 0xa7, 0xb9, 0x5b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w9, 7, vgx4], { z12.b - z15.b }, z11.b[2]"
+
+  -
+    input:
+      bytes: [ 0xa7, 0xb9, 0x5b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w9, 7, vgx4], { z12.b - z15.b }, z11.b[2]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x14, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 0, vgx4], { z0.b - z3.b }, { z0.b - z3.b }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x14, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 0, vgx4], { z0.b - z3.b }, { z0.b - z3.b }"
+
+  -
+    input:
+      bytes: [ 0x05, 0x55, 0xb5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w10, 5, vgx4], { z8.b - z11.b }, { z20.b - z23.b }"
+
+  -
+    input:
+      bytes: [ 0x05, 0x55, 0xb5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w10, 5, vgx4], { z8.b - z11.b }, { z20.b - z23.b }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x75, 0xa9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w11, 7, vgx4], { z12.b - z15.b }, { z8.b - z11.b }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x75, 0xa9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w11, 7, vgx4], { z12.b - z15.b }, { z8.b - z11.b }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x77, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w11, 7, vgx4], { z28.b - z31.b }, { z28.b - z31.b }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x77, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w11, 7, vgx4], { z28.b - z31.b }, { z28.b - z31.b }"
+
+  -
+    input:
+      bytes: [ 0x05, 0x16, 0xb1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 5, vgx4], { z16.b - z19.b }, { z16.b - z19.b }"
+
+  -
+    input:
+      bytes: [ 0x05, 0x16, 0xb1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 5, vgx4], { z16.b - z19.b }, { z16.b - z19.b }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x14, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 1, vgx4], { z0.b - z3.b }, { z28.b - z31.b }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x14, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 1, vgx4], { z0.b - z3.b }, { z28.b - z31.b }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x56, 0xb5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w10, 0, vgx4], { z16.b - z19.b }, { z20.b - z23.b }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x56, 0xb5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w10, 0, vgx4], { z16.b - z19.b }, { z20.b - z23.b }"
+
+  -
+    input:
+      bytes: [ 0x80, 0x15, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 0, vgx4], { z12.b - z15.b }, { z0.b - z3.b }"
+
+  -
+    input:
+      bytes: [ 0x80, 0x15, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 0, vgx4], { z12.b - z15.b }, { z0.b - z3.b }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x54, 0xb9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w10, 1, vgx4], { z0.b - z3.b }, { z24.b - z27.b }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x54, 0xb9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w10, 1, vgx4], { z0.b - z3.b }, { z24.b - z27.b }"
+
+  -
+    input:
+      bytes: [ 0x85, 0x16, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 5, vgx4], { z20.b - z23.b }, { z28.b - z31.b }"
+
+  -
+    input:
+      bytes: [ 0x85, 0x16, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w8, 5, vgx4], { z20.b - z23.b }, { z28.b - z31.b }"
+
+  -
+    input:
+      bytes: [ 0x02, 0x75, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w11, 2, vgx4], { z8.b - z11.b }, { z0.b - z3.b }"
+
+  -
+    input:
+      bytes: [ 0x02, 0x75, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w11, 2, vgx4], { z8.b - z11.b }, { z0.b - z3.b }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x35, 0xa9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w9, 7, vgx4], { z12.b - z15.b }, { z8.b - z11.b }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x35, 0xa9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.s[w9, 7, vgx4], { z12.b - z15.b }, { z8.b - z11.b }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x14, 0x70, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w8, 0, vgx4], { z0.h - z3.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x14, 0x70, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w8, 0, vgx4], { z0.h - z3.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x45, 0x55, 0x75, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w10, 5, vgx4], { z10.h - z13.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0x45, 0x55, 0x75, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w10, 5, vgx4], { z10.h - z13.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0xa7, 0x75, 0x78, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w11, 7, vgx4], { z13.h - z16.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0xa7, 0x75, 0x78, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w11, 7, vgx4], { z13.h - z16.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0xe7, 0x77, 0x7f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w11, 7, vgx4], { z31.h, z0.h, z1.h, z2.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0xe7, 0x77, 0x7f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w11, 7, vgx4], { z31.h, z0.h, z1.h, z2.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0x25, 0x16, 0x70, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w8, 5, vgx4], { z17.h - z20.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x25, 0x16, 0x70, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w8, 5, vgx4], { z17.h - z20.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x21, 0x14, 0x7e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w8, 1, vgx4], { z1.h - z4.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x21, 0x14, 0x7e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w8, 1, vgx4], { z1.h - z4.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x60, 0x56, 0x74, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w10, 0, vgx4], { z19.h - z22.h }, z4.h"
+
+  -
+    input:
+      bytes: [ 0x60, 0x56, 0x74, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w10, 0, vgx4], { z19.h - z22.h }, z4.h"
+
+  -
+    input:
+      bytes: [ 0x80, 0x15, 0x72, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w8, 0, vgx4], { z12.h - z15.h }, z2.h"
+
+  -
+    input:
+      bytes: [ 0x80, 0x15, 0x72, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w8, 0, vgx4], { z12.h - z15.h }, z2.h"
+
+  -
+    input:
+      bytes: [ 0x21, 0x54, 0x7a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w10, 1, vgx4], { z1.h - z4.h }, z10.h"
+
+  -
+    input:
+      bytes: [ 0x21, 0x54, 0x7a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w10, 1, vgx4], { z1.h - z4.h }, z10.h"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x16, 0x7e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w8, 5, vgx4], { z22.h - z25.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x16, 0x7e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w8, 5, vgx4], { z22.h - z25.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x22, 0x75, 0x71, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w11, 2, vgx4], { z9.h - z12.h }, z1.h"
+
+  -
+    input:
+      bytes: [ 0x22, 0x75, 0x71, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w11, 2, vgx4], { z9.h - z12.h }, z1.h"
+
+  -
+    input:
+      bytes: [ 0x87, 0x35, 0x7b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w9, 7, vgx4], { z12.h - z15.h }, z11.h"
+
+  -
+    input:
+      bytes: [ 0x87, 0x35, 0x7b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w9, 7, vgx4], { z12.h - z15.h }, z11.h"
+
+  -
+    input:
+      bytes: [ 0x08, 0x80, 0xd0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w8, 0, vgx4], { z0.h - z3.h }, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x08, 0x80, 0xd0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w8, 0, vgx4], { z0.h - z3.h }, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x0d, 0xc5, 0xd5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w10, 5, vgx4], { z8.h - z11.h }, z5.h[1]"
+
+  -
+    input:
+      bytes: [ 0x0d, 0xc5, 0xd5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w10, 5, vgx4], { z8.h - z11.h }, z5.h[1]"
+
+  -
+    input:
+      bytes: [ 0x8f, 0xe5, 0xd8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w11, 7, vgx4], { z12.h - z15.h }, z8.h[1]"
+
+  -
+    input:
+      bytes: [ 0x8f, 0xe5, 0xd8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w11, 7, vgx4], { z12.h - z15.h }, z8.h[1]"
+
+  -
+    input:
+      bytes: [ 0x8f, 0xe7, 0xdf, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w11, 7, vgx4], { z28.h - z31.h }, z15.h[1]"
+
+  -
+    input:
+      bytes: [ 0x8f, 0xe7, 0xdf, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w11, 7, vgx4], { z28.h - z31.h }, z15.h[1]"
+
+  -
+    input:
+      bytes: [ 0x0d, 0x86, 0xd0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w8, 5, vgx4], { z16.h - z19.h }, z0.h[1]"
+
+  -
+    input:
+      bytes: [ 0x0d, 0x86, 0xd0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w8, 5, vgx4], { z16.h - z19.h }, z0.h[1]"
+
+  -
+    input:
+      bytes: [ 0x09, 0x84, 0xde, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w8, 1, vgx4], { z0.h - z3.h }, z14.h[1]"
+
+  -
+    input:
+      bytes: [ 0x09, 0x84, 0xde, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w8, 1, vgx4], { z0.h - z3.h }, z14.h[1]"
+
+  -
+    input:
+      bytes: [ 0x08, 0xc6, 0xd4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w10, 0, vgx4], { z16.h - z19.h }, z4.h[1]"
+
+  -
+    input:
+      bytes: [ 0x08, 0xc6, 0xd4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w10, 0, vgx4], { z16.h - z19.h }, z4.h[1]"
+
+  -
+    input:
+      bytes: [ 0x88, 0x81, 0xd2, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w8, 0, vgx4], { z12.h - z15.h }, z2.h[0]"
+
+  -
+    input:
+      bytes: [ 0x88, 0x81, 0xd2, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w8, 0, vgx4], { z12.h - z15.h }, z2.h[0]"
+
+  -
+    input:
+      bytes: [ 0x09, 0xc0, 0xda, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w10, 1, vgx4], { z0.h - z3.h }, z10.h[0]"
+
+  -
+    input:
+      bytes: [ 0x09, 0xc0, 0xda, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w10, 1, vgx4], { z0.h - z3.h }, z10.h[0]"
+
+  -
+    input:
+      bytes: [ 0x8d, 0x82, 0xde, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w8, 5, vgx4], { z20.h - z23.h }, z14.h[0]"
+
+  -
+    input:
+      bytes: [ 0x8d, 0x82, 0xde, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w8, 5, vgx4], { z20.h - z23.h }, z14.h[0]"
+
+  -
+    input:
+      bytes: [ 0x0a, 0xe5, 0xd1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w11, 2, vgx4], { z8.h - z11.h }, z1.h[1]"
+
+  -
+    input:
+      bytes: [ 0x0a, 0xe5, 0xd1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w11, 2, vgx4], { z8.h - z11.h }, z1.h[1]"
+
+  -
+    input:
+      bytes: [ 0x8f, 0xa1, 0xdb, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w9, 7, vgx4], { z12.h - z15.h }, z11.h[0]"
+
+  -
+    input:
+      bytes: [ 0x8f, 0xa1, 0xdb, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w9, 7, vgx4], { z12.h - z15.h }, z11.h[0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x14, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w8, 0, vgx4], { z0.h - z3.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x14, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w8, 0, vgx4], { z0.h - z3.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x05, 0x55, 0xf5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w10, 5, vgx4], { z8.h - z11.h }, { z20.h - z23.h }"
+
+  -
+    input:
+      bytes: [ 0x05, 0x55, 0xf5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w10, 5, vgx4], { z8.h - z11.h }, { z20.h - z23.h }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x75, 0xe9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w11, 7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x75, 0xe9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w11, 7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x77, 0xfd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w11, 7, vgx4], { z28.h - z31.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x77, 0xfd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w11, 7, vgx4], { z28.h - z31.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x05, 0x16, 0xf1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w8, 5, vgx4], { z16.h - z19.h }, { z16.h - z19.h }"
+
+  -
+    input:
+      bytes: [ 0x05, 0x16, 0xf1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w8, 5, vgx4], { z16.h - z19.h }, { z16.h - z19.h }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x14, 0xfd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w8, 1, vgx4], { z0.h - z3.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x14, 0xfd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w8, 1, vgx4], { z0.h - z3.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x56, 0xf5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w10, 0, vgx4], { z16.h - z19.h }, { z20.h - z23.h }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x56, 0xf5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w10, 0, vgx4], { z16.h - z19.h }, { z20.h - z23.h }"
+
+  -
+    input:
+      bytes: [ 0x80, 0x15, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w8, 0, vgx4], { z12.h - z15.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x80, 0x15, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w8, 0, vgx4], { z12.h - z15.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x54, 0xf9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w10, 1, vgx4], { z0.h - z3.h }, { z24.h - z27.h }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x54, 0xf9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w10, 1, vgx4], { z0.h - z3.h }, { z24.h - z27.h }"
+
+  -
+    input:
+      bytes: [ 0x85, 0x16, 0xfd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w8, 5, vgx4], { z20.h - z23.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x85, 0x16, 0xfd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w8, 5, vgx4], { z20.h - z23.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x02, 0x75, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w11, 2, vgx4], { z8.h - z11.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x02, 0x75, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w11, 2, vgx4], { z8.h - z11.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x35, 0xe9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w9, 7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x35, 0xe9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot za.d[w9, 7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }"
diff --git a/tests/MC/AArch64/SME2/sel.s.yaml b/tests/MC/AArch64/SME2/sel.s.yaml
new file mode 100644
index 000000000..ef347776b
--- /dev/null
+++ b/tests/MC/AArch64/SME2/sel.s.yaml
@@ -0,0 +1,320 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sel { z0.h, z1.h }, pn8, { z0.h, z1.h }, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x54, 0x95, 0x74, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sel { z20.h, z21.h }, pn13, { z10.h, z11.h }, { z20.h, z21.h }"
+
+  -
+    input:
+      bytes: [ 0x96, 0x8d, 0x68, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sel { z22.h, z23.h }, pn11, { z12.h, z13.h }, { z8.h, z9.h }"
+
+  -
+    input:
+      bytes: [ 0xde, 0x9f, 0x7e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sel { z30.h, z31.h }, pn15, { z30.h, z31.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sel { z0.s, z1.s }, pn8, { z0.s, z1.s }, { z0.s, z1.s }"
+
+  -
+    input:
+      bytes: [ 0x54, 0x95, 0xb4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sel { z20.s, z21.s }, pn13, { z10.s, z11.s }, { z20.s, z21.s }"
+
+  -
+    input:
+      bytes: [ 0x96, 0x8d, 0xa8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sel { z22.s, z23.s }, pn11, { z12.s, z13.s }, { z8.s, z9.s }"
+
+  -
+    input:
+      bytes: [ 0xde, 0x9f, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sel { z30.s, z31.s }, pn15, { z30.s, z31.s }, { z30.s, z31.s }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sel { z0.d, z1.d }, pn8, { z0.d, z1.d }, { z0.d, z1.d }"
+
+  -
+    input:
+      bytes: [ 0x54, 0x95, 0xf4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sel { z20.d, z21.d }, pn13, { z10.d, z11.d }, { z20.d, z21.d }"
+
+  -
+    input:
+      bytes: [ 0x96, 0x8d, 0xe8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sel { z22.d, z23.d }, pn11, { z12.d, z13.d }, { z8.d, z9.d }"
+
+  -
+    input:
+      bytes: [ 0xde, 0x9f, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sel { z30.d, z31.d }, pn15, { z30.d, z31.d }, { z30.d, z31.d }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sel { z0.b, z1.b }, pn8, { z0.b, z1.b }, { z0.b, z1.b }"
+
+  -
+    input:
+      bytes: [ 0x54, 0x95, 0x34, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sel { z20.b, z21.b }, pn13, { z10.b, z11.b }, { z20.b, z21.b }"
+
+  -
+    input:
+      bytes: [ 0x96, 0x8d, 0x28, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sel { z22.b, z23.b }, pn11, { z12.b, z13.b }, { z8.b, z9.b }"
+
+  -
+    input:
+      bytes: [ 0xde, 0x9f, 0x3e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sel { z30.b, z31.b }, pn15, { z30.b, z31.b }, { z30.b, z31.b }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x61, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sel { z0.h - z3.h }, pn8, { z0.h - z3.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x14, 0x95, 0x75, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sel { z20.h - z23.h }, pn13, { z8.h - z11.h }, { z20.h - z23.h }"
+
+  -
+    input:
+      bytes: [ 0x94, 0x8d, 0x69, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sel { z20.h - z23.h }, pn11, { z12.h - z15.h }, { z8.h - z11.h }"
+
+  -
+    input:
+      bytes: [ 0x9c, 0x9f, 0x7d, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sel { z28.h - z31.h }, pn15, { z28.h - z31.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sel { z0.s - z3.s }, pn8, { z0.s - z3.s }, { z0.s - z3.s }"
+
+  -
+    input:
+      bytes: [ 0x14, 0x95, 0xb5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sel { z20.s - z23.s }, pn13, { z8.s - z11.s }, { z20.s - z23.s }"
+
+  -
+    input:
+      bytes: [ 0x94, 0x8d, 0xa9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sel { z20.s - z23.s }, pn11, { z12.s - z15.s }, { z8.s - z11.s }"
+
+  -
+    input:
+      bytes: [ 0x9c, 0x9f, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sel { z28.s - z31.s }, pn15, { z28.s - z31.s }, { z28.s - z31.s }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sel { z0.d - z3.d }, pn8, { z0.d - z3.d }, { z0.d - z3.d }"
+
+  -
+    input:
+      bytes: [ 0x14, 0x95, 0xf5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sel { z20.d - z23.d }, pn13, { z8.d - z11.d }, { z20.d - z23.d }"
+
+  -
+    input:
+      bytes: [ 0x94, 0x8d, 0xe9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sel { z20.d - z23.d }, pn11, { z12.d - z15.d }, { z8.d - z11.d }"
+
+  -
+    input:
+      bytes: [ 0x9c, 0x9f, 0xfd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sel { z28.d - z31.d }, pn15, { z28.d - z31.d }, { z28.d - z31.d }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x21, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sel { z0.b - z3.b }, pn8, { z0.b - z3.b }, { z0.b - z3.b }"
+
+  -
+    input:
+      bytes: [ 0x14, 0x95, 0x35, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sel { z20.b - z23.b }, pn13, { z8.b - z11.b }, { z20.b - z23.b }"
+
+  -
+    input:
+      bytes: [ 0x94, 0x8d, 0x29, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sel { z20.b - z23.b }, pn11, { z12.b - z15.b }, { z8.b - z11.b }"
+
+  -
+    input:
+      bytes: [ 0x9c, 0x9f, 0x3d, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sel { z28.b - z31.b }, pn15, { z28.b - z31.b }, { z28.b - z31.b }"
diff --git a/tests/MC/AArch64/SME2/smax.s.yaml b/tests/MC/AArch64/SME2/smax.s.yaml
new file mode 100644
index 000000000..e83c6e731
--- /dev/null
+++ b/tests/MC/AArch64/SME2/smax.s.yaml
@@ -0,0 +1,640 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax { z0.h, z1.h }, { z0.h, z1.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x14, 0xa0, 0x65, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax { z20.h, z21.h }, { z20.h, z21.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0x16, 0xa0, 0x68, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax { z22.h, z23.h }, { z22.h, z23.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0x1e, 0xa0, 0x6f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax { z30.h, z31.h }, { z30.h, z31.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0xb0, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax { z0.h, z1.h }, { z0.h, z1.h }, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x14, 0xb0, 0x74, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax { z20.h, z21.h }, { z20.h, z21.h }, { z20.h, z21.h }"
+
+  -
+    input:
+      bytes: [ 0x16, 0xb0, 0x68, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax { z22.h, z23.h }, { z22.h, z23.h }, { z8.h, z9.h }"
+
+  -
+    input:
+      bytes: [ 0x1e, 0xb0, 0x7e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax { z30.h, z31.h }, { z30.h, z31.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax { z0.s, z1.s }, { z0.s, z1.s }, z0.s"
+
+  -
+    input:
+      bytes: [ 0x14, 0xa0, 0xa5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax { z20.s, z21.s }, { z20.s, z21.s }, z5.s"
+
+  -
+    input:
+      bytes: [ 0x16, 0xa0, 0xa8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax { z22.s, z23.s }, { z22.s, z23.s }, z8.s"
+
+  -
+    input:
+      bytes: [ 0x1e, 0xa0, 0xaf, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax { z30.s, z31.s }, { z30.s, z31.s }, z15.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0xb0, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax { z0.s, z1.s }, { z0.s, z1.s }, { z0.s, z1.s }"
+
+  -
+    input:
+      bytes: [ 0x14, 0xb0, 0xb4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax { z20.s, z21.s }, { z20.s, z21.s }, { z20.s, z21.s }"
+
+  -
+    input:
+      bytes: [ 0x16, 0xb0, 0xa8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax { z22.s, z23.s }, { z22.s, z23.s }, { z8.s, z9.s }"
+
+  -
+    input:
+      bytes: [ 0x1e, 0xb0, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax { z30.s, z31.s }, { z30.s, z31.s }, { z30.s, z31.s }"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax { z0.d, z1.d }, { z0.d, z1.d }, z0.d"
+
+  -
+    input:
+      bytes: [ 0x14, 0xa0, 0xe5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax { z20.d, z21.d }, { z20.d, z21.d }, z5.d"
+
+  -
+    input:
+      bytes: [ 0x16, 0xa0, 0xe8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax { z22.d, z23.d }, { z22.d, z23.d }, z8.d"
+
+  -
+    input:
+      bytes: [ 0x1e, 0xa0, 0xef, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax { z30.d, z31.d }, { z30.d, z31.d }, z15.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0xb0, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax { z0.d, z1.d }, { z0.d, z1.d }, { z0.d, z1.d }"
+
+  -
+    input:
+      bytes: [ 0x14, 0xb0, 0xf4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax { z20.d, z21.d }, { z20.d, z21.d }, { z20.d, z21.d }"
+
+  -
+    input:
+      bytes: [ 0x16, 0xb0, 0xe8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax { z22.d, z23.d }, { z22.d, z23.d }, { z8.d, z9.d }"
+
+  -
+    input:
+      bytes: [ 0x1e, 0xb0, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax { z30.d, z31.d }, { z30.d, z31.d }, { z30.d, z31.d }"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax { z0.b, z1.b }, { z0.b, z1.b }, z0.b"
+
+  -
+    input:
+      bytes: [ 0x14, 0xa0, 0x25, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax { z20.b, z21.b }, { z20.b, z21.b }, z5.b"
+
+  -
+    input:
+      bytes: [ 0x16, 0xa0, 0x28, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax { z22.b, z23.b }, { z22.b, z23.b }, z8.b"
+
+  -
+    input:
+      bytes: [ 0x1e, 0xa0, 0x2f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax { z30.b, z31.b }, { z30.b, z31.b }, z15.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0xb0, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax { z0.b, z1.b }, { z0.b, z1.b }, { z0.b, z1.b }"
+
+  -
+    input:
+      bytes: [ 0x14, 0xb0, 0x34, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax { z20.b, z21.b }, { z20.b, z21.b }, { z20.b, z21.b }"
+
+  -
+    input:
+      bytes: [ 0x16, 0xb0, 0x28, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax { z22.b, z23.b }, { z22.b, z23.b }, { z8.b, z9.b }"
+
+  -
+    input:
+      bytes: [ 0x1e, 0xb0, 0x3e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax { z30.b, z31.b }, { z30.b, z31.b }, { z30.b, z31.b }"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa8, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax { z0.h - z3.h }, { z0.h - z3.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x14, 0xa8, 0x65, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax { z20.h - z23.h }, { z20.h - z23.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0x14, 0xa8, 0x68, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax { z20.h - z23.h }, { z20.h - z23.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0x1c, 0xa8, 0x6f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax { z28.h - z31.h }, { z28.h - z31.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0xb8, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax { z0.h - z3.h }, { z0.h - z3.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x14, 0xb8, 0x74, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax { z20.h - z23.h }, { z20.h - z23.h }, { z20.h - z23.h }"
+
+  -
+    input:
+      bytes: [ 0x14, 0xb8, 0x68, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax { z20.h - z23.h }, { z20.h - z23.h }, { z8.h - z11.h }"
+
+  -
+    input:
+      bytes: [ 0x1c, 0xb8, 0x7c, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax { z28.h - z31.h }, { z28.h - z31.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa8, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax { z0.s - z3.s }, { z0.s - z3.s }, z0.s"
+
+  -
+    input:
+      bytes: [ 0x14, 0xa8, 0xa5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax { z20.s - z23.s }, { z20.s - z23.s }, z5.s"
+
+  -
+    input:
+      bytes: [ 0x14, 0xa8, 0xa8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax { z20.s - z23.s }, { z20.s - z23.s }, z8.s"
+
+  -
+    input:
+      bytes: [ 0x1c, 0xa8, 0xaf, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax { z28.s - z31.s }, { z28.s - z31.s }, z15.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0xb8, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax { z0.s - z3.s }, { z0.s - z3.s }, { z0.s - z3.s }"
+
+  -
+    input:
+      bytes: [ 0x14, 0xb8, 0xb4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax { z20.s - z23.s }, { z20.s - z23.s }, { z20.s - z23.s }"
+
+  -
+    input:
+      bytes: [ 0x14, 0xb8, 0xa8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax { z20.s - z23.s }, { z20.s - z23.s }, { z8.s - z11.s }"
+
+  -
+    input:
+      bytes: [ 0x1c, 0xb8, 0xbc, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax { z28.s - z31.s }, { z28.s - z31.s }, { z28.s - z31.s }"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa8, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax { z0.d - z3.d }, { z0.d - z3.d }, z0.d"
+
+  -
+    input:
+      bytes: [ 0x14, 0xa8, 0xe5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax { z20.d - z23.d }, { z20.d - z23.d }, z5.d"
+
+  -
+    input:
+      bytes: [ 0x14, 0xa8, 0xe8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax { z20.d - z23.d }, { z20.d - z23.d }, z8.d"
+
+  -
+    input:
+      bytes: [ 0x1c, 0xa8, 0xef, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax { z28.d - z31.d }, { z28.d - z31.d }, z15.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0xb8, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax { z0.d - z3.d }, { z0.d - z3.d }, { z0.d - z3.d }"
+
+  -
+    input:
+      bytes: [ 0x14, 0xb8, 0xf4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax { z20.d - z23.d }, { z20.d - z23.d }, { z20.d - z23.d }"
+
+  -
+    input:
+      bytes: [ 0x14, 0xb8, 0xe8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax { z20.d - z23.d }, { z20.d - z23.d }, { z8.d - z11.d }"
+
+  -
+    input:
+      bytes: [ 0x1c, 0xb8, 0xfc, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax { z28.d - z31.d }, { z28.d - z31.d }, { z28.d - z31.d }"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa8, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax { z0.b - z3.b }, { z0.b - z3.b }, z0.b"
+
+  -
+    input:
+      bytes: [ 0x14, 0xa8, 0x25, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax { z20.b - z23.b }, { z20.b - z23.b }, z5.b"
+
+  -
+    input:
+      bytes: [ 0x14, 0xa8, 0x28, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax { z20.b - z23.b }, { z20.b - z23.b }, z8.b"
+
+  -
+    input:
+      bytes: [ 0x1c, 0xa8, 0x2f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax { z28.b - z31.b }, { z28.b - z31.b }, z15.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0xb8, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax { z0.b - z3.b }, { z0.b - z3.b }, { z0.b - z3.b }"
+
+  -
+    input:
+      bytes: [ 0x14, 0xb8, 0x34, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax { z20.b - z23.b }, { z20.b - z23.b }, { z20.b - z23.b }"
+
+  -
+    input:
+      bytes: [ 0x14, 0xb8, 0x28, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax { z20.b - z23.b }, { z20.b - z23.b }, { z8.b - z11.b }"
+
+  -
+    input:
+      bytes: [ 0x1c, 0xb8, 0x3c, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax { z28.b - z31.b }, { z28.b - z31.b }, { z28.b - z31.b }"
diff --git a/tests/MC/AArch64/SME2/smin.s.yaml b/tests/MC/AArch64/SME2/smin.s.yaml
new file mode 100644
index 000000000..0a14a8b48
--- /dev/null
+++ b/tests/MC/AArch64/SME2/smin.s.yaml
@@ -0,0 +1,640 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0xa0, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin { z0.h, z1.h }, { z0.h, z1.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x34, 0xa0, 0x65, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin { z20.h, z21.h }, { z20.h, z21.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0x36, 0xa0, 0x68, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin { z22.h, z23.h }, { z22.h, z23.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0x3e, 0xa0, 0x6f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin { z30.h, z31.h }, { z30.h, z31.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0xb0, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin { z0.h, z1.h }, { z0.h, z1.h }, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x34, 0xb0, 0x74, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin { z20.h, z21.h }, { z20.h, z21.h }, { z20.h, z21.h }"
+
+  -
+    input:
+      bytes: [ 0x36, 0xb0, 0x68, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin { z22.h, z23.h }, { z22.h, z23.h }, { z8.h, z9.h }"
+
+  -
+    input:
+      bytes: [ 0x3e, 0xb0, 0x7e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin { z30.h, z31.h }, { z30.h, z31.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa0, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin { z0.s, z1.s }, { z0.s, z1.s }, z0.s"
+
+  -
+    input:
+      bytes: [ 0x34, 0xa0, 0xa5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin { z20.s, z21.s }, { z20.s, z21.s }, z5.s"
+
+  -
+    input:
+      bytes: [ 0x36, 0xa0, 0xa8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin { z22.s, z23.s }, { z22.s, z23.s }, z8.s"
+
+  -
+    input:
+      bytes: [ 0x3e, 0xa0, 0xaf, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin { z30.s, z31.s }, { z30.s, z31.s }, z15.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0xb0, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin { z0.s, z1.s }, { z0.s, z1.s }, { z0.s, z1.s }"
+
+  -
+    input:
+      bytes: [ 0x34, 0xb0, 0xb4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin { z20.s, z21.s }, { z20.s, z21.s }, { z20.s, z21.s }"
+
+  -
+    input:
+      bytes: [ 0x36, 0xb0, 0xa8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin { z22.s, z23.s }, { z22.s, z23.s }, { z8.s, z9.s }"
+
+  -
+    input:
+      bytes: [ 0x3e, 0xb0, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin { z30.s, z31.s }, { z30.s, z31.s }, { z30.s, z31.s }"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa0, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin { z0.d, z1.d }, { z0.d, z1.d }, z0.d"
+
+  -
+    input:
+      bytes: [ 0x34, 0xa0, 0xe5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin { z20.d, z21.d }, { z20.d, z21.d }, z5.d"
+
+  -
+    input:
+      bytes: [ 0x36, 0xa0, 0xe8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin { z22.d, z23.d }, { z22.d, z23.d }, z8.d"
+
+  -
+    input:
+      bytes: [ 0x3e, 0xa0, 0xef, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin { z30.d, z31.d }, { z30.d, z31.d }, z15.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0xb0, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin { z0.d, z1.d }, { z0.d, z1.d }, { z0.d, z1.d }"
+
+  -
+    input:
+      bytes: [ 0x34, 0xb0, 0xf4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin { z20.d, z21.d }, { z20.d, z21.d }, { z20.d, z21.d }"
+
+  -
+    input:
+      bytes: [ 0x36, 0xb0, 0xe8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin { z22.d, z23.d }, { z22.d, z23.d }, { z8.d, z9.d }"
+
+  -
+    input:
+      bytes: [ 0x3e, 0xb0, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin { z30.d, z31.d }, { z30.d, z31.d }, { z30.d, z31.d }"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa0, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin { z0.b, z1.b }, { z0.b, z1.b }, z0.b"
+
+  -
+    input:
+      bytes: [ 0x34, 0xa0, 0x25, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin { z20.b, z21.b }, { z20.b, z21.b }, z5.b"
+
+  -
+    input:
+      bytes: [ 0x36, 0xa0, 0x28, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin { z22.b, z23.b }, { z22.b, z23.b }, z8.b"
+
+  -
+    input:
+      bytes: [ 0x3e, 0xa0, 0x2f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin { z30.b, z31.b }, { z30.b, z31.b }, z15.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0xb0, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin { z0.b, z1.b }, { z0.b, z1.b }, { z0.b, z1.b }"
+
+  -
+    input:
+      bytes: [ 0x34, 0xb0, 0x34, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin { z20.b, z21.b }, { z20.b, z21.b }, { z20.b, z21.b }"
+
+  -
+    input:
+      bytes: [ 0x36, 0xb0, 0x28, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin { z22.b, z23.b }, { z22.b, z23.b }, { z8.b, z9.b }"
+
+  -
+    input:
+      bytes: [ 0x3e, 0xb0, 0x3e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin { z30.b, z31.b }, { z30.b, z31.b }, { z30.b, z31.b }"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa8, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin { z0.h - z3.h }, { z0.h - z3.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x34, 0xa8, 0x65, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin { z20.h - z23.h }, { z20.h - z23.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0x34, 0xa8, 0x68, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin { z20.h - z23.h }, { z20.h - z23.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0x3c, 0xa8, 0x6f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin { z28.h - z31.h }, { z28.h - z31.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0xb8, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin { z0.h - z3.h }, { z0.h - z3.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x34, 0xb8, 0x74, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin { z20.h - z23.h }, { z20.h - z23.h }, { z20.h - z23.h }"
+
+  -
+    input:
+      bytes: [ 0x34, 0xb8, 0x68, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin { z20.h - z23.h }, { z20.h - z23.h }, { z8.h - z11.h }"
+
+  -
+    input:
+      bytes: [ 0x3c, 0xb8, 0x7c, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin { z28.h - z31.h }, { z28.h - z31.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa8, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin { z0.s - z3.s }, { z0.s - z3.s }, z0.s"
+
+  -
+    input:
+      bytes: [ 0x34, 0xa8, 0xa5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin { z20.s - z23.s }, { z20.s - z23.s }, z5.s"
+
+  -
+    input:
+      bytes: [ 0x34, 0xa8, 0xa8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin { z20.s - z23.s }, { z20.s - z23.s }, z8.s"
+
+  -
+    input:
+      bytes: [ 0x3c, 0xa8, 0xaf, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin { z28.s - z31.s }, { z28.s - z31.s }, z15.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0xb8, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin { z0.s - z3.s }, { z0.s - z3.s }, { z0.s - z3.s }"
+
+  -
+    input:
+      bytes: [ 0x34, 0xb8, 0xb4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin { z20.s - z23.s }, { z20.s - z23.s }, { z20.s - z23.s }"
+
+  -
+    input:
+      bytes: [ 0x34, 0xb8, 0xa8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin { z20.s - z23.s }, { z20.s - z23.s }, { z8.s - z11.s }"
+
+  -
+    input:
+      bytes: [ 0x3c, 0xb8, 0xbc, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin { z28.s - z31.s }, { z28.s - z31.s }, { z28.s - z31.s }"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa8, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin { z0.d - z3.d }, { z0.d - z3.d }, z0.d"
+
+  -
+    input:
+      bytes: [ 0x34, 0xa8, 0xe5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin { z20.d - z23.d }, { z20.d - z23.d }, z5.d"
+
+  -
+    input:
+      bytes: [ 0x34, 0xa8, 0xe8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin { z20.d - z23.d }, { z20.d - z23.d }, z8.d"
+
+  -
+    input:
+      bytes: [ 0x3c, 0xa8, 0xef, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin { z28.d - z31.d }, { z28.d - z31.d }, z15.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0xb8, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin { z0.d - z3.d }, { z0.d - z3.d }, { z0.d - z3.d }"
+
+  -
+    input:
+      bytes: [ 0x34, 0xb8, 0xf4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin { z20.d - z23.d }, { z20.d - z23.d }, { z20.d - z23.d }"
+
+  -
+    input:
+      bytes: [ 0x34, 0xb8, 0xe8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin { z20.d - z23.d }, { z20.d - z23.d }, { z8.d - z11.d }"
+
+  -
+    input:
+      bytes: [ 0x3c, 0xb8, 0xfc, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin { z28.d - z31.d }, { z28.d - z31.d }, { z28.d - z31.d }"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa8, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin { z0.b - z3.b }, { z0.b - z3.b }, z0.b"
+
+  -
+    input:
+      bytes: [ 0x34, 0xa8, 0x25, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin { z20.b - z23.b }, { z20.b - z23.b }, z5.b"
+
+  -
+    input:
+      bytes: [ 0x34, 0xa8, 0x28, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin { z20.b - z23.b }, { z20.b - z23.b }, z8.b"
+
+  -
+    input:
+      bytes: [ 0x3c, 0xa8, 0x2f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin { z28.b - z31.b }, { z28.b - z31.b }, z15.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0xb8, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin { z0.b - z3.b }, { z0.b - z3.b }, { z0.b - z3.b }"
+
+  -
+    input:
+      bytes: [ 0x34, 0xb8, 0x34, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin { z20.b - z23.b }, { z20.b - z23.b }, { z20.b - z23.b }"
+
+  -
+    input:
+      bytes: [ 0x34, 0xb8, 0x28, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin { z20.b - z23.b }, { z20.b - z23.b }, { z8.b - z11.b }"
+
+  -
+    input:
+      bytes: [ 0x3c, 0xb8, 0x3c, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin { z28.b - z31.b }, { z28.b - z31.b }, { z28.b - z31.b }"
diff --git a/tests/MC/AArch64/SME2/smlal.s.yaml b/tests/MC/AArch64/SME2/smlal.s.yaml
new file mode 100644
index 000000000..dabcedc50
--- /dev/null
+++ b/tests/MC/AArch64/SME2/smlal.s.yaml
@@ -0,0 +1,1680 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x0c, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w8, 0:1], z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x45, 0x4d, 0x65, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w10, 10:11], z10.h, z5.h"
+
+  -
+    input:
+      bytes: [ 0xa7, 0x6d, 0x68, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w11, 14:15], z13.h, z8.h"
+
+  -
+    input:
+      bytes: [ 0xe7, 0x6f, 0x6f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w11, 14:15], z31.h, z15.h"
+
+  -
+    input:
+      bytes: [ 0x25, 0x0e, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w8, 10:11], z17.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x21, 0x0c, 0x6e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w8, 2:3], z1.h, z14.h"
+
+  -
+    input:
+      bytes: [ 0x60, 0x4e, 0x64, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w10, 0:1], z19.h, z4.h"
+
+  -
+    input:
+      bytes: [ 0x80, 0x0d, 0x62, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w8, 0:1], z12.h, z2.h"
+
+  -
+    input:
+      bytes: [ 0x21, 0x4c, 0x6a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w10, 2:3], z1.h, z10.h"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x0e, 0x6e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w8, 10:11], z22.h, z14.h"
+
+  -
+    input:
+      bytes: [ 0x22, 0x6d, 0x61, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w11, 4:5], z9.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0x87, 0x2d, 0x6b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w9, 14:15], z12.h, z11.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x10, 0xc0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w8, 0:1], z0.h, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x45, 0x55, 0xc5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w10, 10:11], z10.h, z5.h[1]"
+
+  -
+    input:
+      bytes: [ 0xa7, 0xfd, 0xc8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w11, 14:15], z13.h, z8.h[7]"
+
+  -
+    input:
+      bytes: [ 0xe7, 0xff, 0xcf, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w11, 14:15], z31.h, z15.h[7]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x1e, 0xc0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w8, 10:11], z17.h, z0.h[3]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x94, 0xce, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w8, 2:3], z1.h, z14.h[5]"
+
+  -
+    input:
+      bytes: [ 0x60, 0x56, 0xc4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w10, 0:1], z19.h, z4.h[1]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x19, 0xc2, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w8, 0:1], z12.h, z2.h[2]"
+
+  -
+    input:
+      bytes: [ 0x21, 0xd8, 0xca, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w10, 2:3], z1.h, z10.h[6]"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x1a, 0xce, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w8, 10:11], z22.h, z14.h[2]"
+
+  -
+    input:
+      bytes: [ 0x22, 0xf5, 0xc1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w11, 4:5], z9.h, z1.h[5]"
+
+  -
+    input:
+      bytes: [ 0x87, 0xb9, 0xcb, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w9, 14:15], z12.h, z11.h[6]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x08, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w8, 0:1, vgx2], { z0.h, z1.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x08, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w8, 0:1, vgx2], { z0.h, z1.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x41, 0x49, 0x65, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w10, 2:3, vgx2], { z10.h, z11.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0x41, 0x49, 0x65, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w10, 2:3, vgx2], { z10.h, z11.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0xa3, 0x69, 0x68, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w11, 6:7, vgx2], { z13.h, z14.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0xa3, 0x69, 0x68, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w11, 6:7, vgx2], { z13.h, z14.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x6b, 0x6f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w11, 6:7, vgx2], { z31.h, z0.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x6b, 0x6f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w11, 6:7, vgx2], { z31.h, z0.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0x21, 0x0a, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w8, 2:3, vgx2], { z17.h, z18.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x21, 0x0a, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w8, 2:3, vgx2], { z17.h, z18.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x21, 0x08, 0x6e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w8, 2:3, vgx2], { z1.h, z2.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x21, 0x08, 0x6e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w8, 2:3, vgx2], { z1.h, z2.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x60, 0x4a, 0x64, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w10, 0:1, vgx2], { z19.h, z20.h }, z4.h"
+
+  -
+    input:
+      bytes: [ 0x60, 0x4a, 0x64, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w10, 0:1, vgx2], { z19.h, z20.h }, z4.h"
+
+  -
+    input:
+      bytes: [ 0x80, 0x09, 0x62, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w8, 0:1, vgx2], { z12.h, z13.h }, z2.h"
+
+  -
+    input:
+      bytes: [ 0x80, 0x09, 0x62, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w8, 0:1, vgx2], { z12.h, z13.h }, z2.h"
+
+  -
+    input:
+      bytes: [ 0x21, 0x48, 0x6a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w10, 2:3, vgx2], { z1.h, z2.h }, z10.h"
+
+  -
+    input:
+      bytes: [ 0x21, 0x48, 0x6a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w10, 2:3, vgx2], { z1.h, z2.h }, z10.h"
+
+  -
+    input:
+      bytes: [ 0xc1, 0x0a, 0x6e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w8, 2:3, vgx2], { z22.h, z23.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0xc1, 0x0a, 0x6e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w8, 2:3, vgx2], { z22.h, z23.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x22, 0x69, 0x61, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w11, 4:5, vgx2], { z9.h, z10.h }, z1.h"
+
+  -
+    input:
+      bytes: [ 0x22, 0x69, 0x61, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w11, 4:5, vgx2], { z9.h, z10.h }, z1.h"
+
+  -
+    input:
+      bytes: [ 0x83, 0x29, 0x6b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w9, 6:7, vgx2], { z12.h, z13.h }, z11.h"
+
+  -
+    input:
+      bytes: [ 0x83, 0x29, 0x6b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w9, 6:7, vgx2], { z12.h, z13.h }, z11.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x10, 0xd0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w8, 0:1, vgx2], { z0.h, z1.h }, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x10, 0xd0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w8, 0:1, vgx2], { z0.h, z1.h }, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x45, 0x55, 0xd5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w10, 2:3, vgx2], { z10.h, z11.h }, z5.h[3]"
+
+  -
+    input:
+      bytes: [ 0x45, 0x55, 0xd5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w10, 2:3, vgx2], { z10.h, z11.h }, z5.h[3]"
+
+  -
+    input:
+      bytes: [ 0x87, 0x7d, 0xd8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w11, 6:7, vgx2], { z12.h, z13.h }, z8.h[7]"
+
+  -
+    input:
+      bytes: [ 0x87, 0x7d, 0xd8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w11, 6:7, vgx2], { z12.h, z13.h }, z8.h[7]"
+
+  -
+    input:
+      bytes: [ 0xc7, 0x7f, 0xdf, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w11, 6:7, vgx2], { z30.h, z31.h }, z15.h[7]"
+
+  -
+    input:
+      bytes: [ 0xc7, 0x7f, 0xdf, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w11, 6:7, vgx2], { z30.h, z31.h }, z15.h[7]"
+
+  -
+    input:
+      bytes: [ 0x05, 0x1e, 0xd0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w8, 2:3, vgx2], { z16.h, z17.h }, z0.h[7]"
+
+  -
+    input:
+      bytes: [ 0x05, 0x1e, 0xd0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w8, 2:3, vgx2], { z16.h, z17.h }, z0.h[7]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x14, 0xde, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w8, 2:3, vgx2], { z0.h, z1.h }, z14.h[2]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x14, 0xde, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w8, 2:3, vgx2], { z0.h, z1.h }, z14.h[2]"
+
+  -
+    input:
+      bytes: [ 0x40, 0x56, 0xd4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w10, 0:1, vgx2], { z18.h, z19.h }, z4.h[2]"
+
+  -
+    input:
+      bytes: [ 0x40, 0x56, 0xd4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w10, 0:1, vgx2], { z18.h, z19.h }, z4.h[2]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x19, 0xd2, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w8, 0:1, vgx2], { z12.h, z13.h }, z2.h[4]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x19, 0xd2, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w8, 0:1, vgx2], { z12.h, z13.h }, z2.h[4]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x58, 0xda, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w10, 2:3, vgx2], { z0.h, z1.h }, z10.h[4]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x58, 0xda, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w10, 2:3, vgx2], { z0.h, z1.h }, z10.h[4]"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x1a, 0xde, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w8, 2:3, vgx2], { z22.h, z23.h }, z14.h[5]"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x1a, 0xde, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w8, 2:3, vgx2], { z22.h, z23.h }, z14.h[5]"
+
+  -
+    input:
+      bytes: [ 0x02, 0x75, 0xd1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w11, 4:5, vgx2], { z8.h, z9.h }, z1.h[2]"
+
+  -
+    input:
+      bytes: [ 0x02, 0x75, 0xd1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w11, 4:5, vgx2], { z8.h, z9.h }, z1.h[2]"
+
+  -
+    input:
+      bytes: [ 0x87, 0x39, 0xdb, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w9, 6:7, vgx2], { z12.h, z13.h }, z11.h[5]"
+
+  -
+    input:
+      bytes: [ 0x87, 0x39, 0xdb, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w9, 6:7, vgx2], { z12.h, z13.h }, z11.h[5]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x08, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w8, 0:1, vgx2], { z0.h, z1.h }, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x08, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w8, 0:1, vgx2], { z0.h, z1.h }, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x41, 0x49, 0xf4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w10, 2:3, vgx2], { z10.h, z11.h }, { z20.h, z21.h }"
+
+  -
+    input:
+      bytes: [ 0x41, 0x49, 0xf4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w10, 2:3, vgx2], { z10.h, z11.h }, { z20.h, z21.h }"
+
+  -
+    input:
+      bytes: [ 0x83, 0x69, 0xe8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w11, 6:7, vgx2], { z12.h, z13.h }, { z8.h, z9.h }"
+
+  -
+    input:
+      bytes: [ 0x83, 0x69, 0xe8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w11, 6:7, vgx2], { z12.h, z13.h }, { z8.h, z9.h }"
+
+  -
+    input:
+      bytes: [ 0xc3, 0x6b, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w11, 6:7, vgx2], { z30.h, z31.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0xc3, 0x6b, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w11, 6:7, vgx2], { z30.h, z31.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x0a, 0xf0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w8, 2:3, vgx2], { z16.h, z17.h }, { z16.h, z17.h }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x0a, 0xf0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w8, 2:3, vgx2], { z16.h, z17.h }, { z16.h, z17.h }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x08, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w8, 2:3, vgx2], { z0.h, z1.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x08, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w8, 2:3, vgx2], { z0.h, z1.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x40, 0x4a, 0xf4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w10, 0:1, vgx2], { z18.h, z19.h }, { z20.h, z21.h }"
+
+  -
+    input:
+      bytes: [ 0x40, 0x4a, 0xf4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w10, 0:1, vgx2], { z18.h, z19.h }, { z20.h, z21.h }"
+
+  -
+    input:
+      bytes: [ 0x80, 0x09, 0xe2, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w8, 0:1, vgx2], { z12.h, z13.h }, { z2.h, z3.h }"
+
+  -
+    input:
+      bytes: [ 0x80, 0x09, 0xe2, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w8, 0:1, vgx2], { z12.h, z13.h }, { z2.h, z3.h }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x48, 0xfa, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w10, 2:3, vgx2], { z0.h, z1.h }, { z26.h, z27.h }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x48, 0xfa, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w10, 2:3, vgx2], { z0.h, z1.h }, { z26.h, z27.h }"
+
+  -
+    input:
+      bytes: [ 0xc1, 0x0a, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w8, 2:3, vgx2], { z22.h, z23.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0xc1, 0x0a, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w8, 2:3, vgx2], { z22.h, z23.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x02, 0x69, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w11, 4:5, vgx2], { z8.h, z9.h }, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x02, 0x69, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w11, 4:5, vgx2], { z8.h, z9.h }, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x83, 0x29, 0xea, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w9, 6:7, vgx2], { z12.h, z13.h }, { z10.h, z11.h }"
+
+  -
+    input:
+      bytes: [ 0x83, 0x29, 0xea, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w9, 6:7, vgx2], { z12.h, z13.h }, { z10.h, z11.h }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x08, 0x70, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w8, 0:1, vgx4], { z0.h - z3.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x08, 0x70, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w8, 0:1, vgx4], { z0.h - z3.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x41, 0x49, 0x75, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w10, 2:3, vgx4], { z10.h - z13.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0x41, 0x49, 0x75, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w10, 2:3, vgx4], { z10.h - z13.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0xa3, 0x69, 0x78, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w11, 6:7, vgx4], { z13.h - z16.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0xa3, 0x69, 0x78, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w11, 6:7, vgx4], { z13.h - z16.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x6b, 0x7f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w11, 6:7, vgx4], { z31.h, z0.h, z1.h, z2.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x6b, 0x7f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w11, 6:7, vgx4], { z31.h, z0.h, z1.h, z2.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0x21, 0x0a, 0x70, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w8, 2:3, vgx4], { z17.h - z20.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x21, 0x0a, 0x70, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w8, 2:3, vgx4], { z17.h - z20.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x21, 0x08, 0x7e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w8, 2:3, vgx4], { z1.h - z4.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x21, 0x08, 0x7e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w8, 2:3, vgx4], { z1.h - z4.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x60, 0x4a, 0x74, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w10, 0:1, vgx4], { z19.h - z22.h }, z4.h"
+
+  -
+    input:
+      bytes: [ 0x60, 0x4a, 0x74, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w10, 0:1, vgx4], { z19.h - z22.h }, z4.h"
+
+  -
+    input:
+      bytes: [ 0x80, 0x09, 0x72, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w8, 0:1, vgx4], { z12.h - z15.h }, z2.h"
+
+  -
+    input:
+      bytes: [ 0x80, 0x09, 0x72, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w8, 0:1, vgx4], { z12.h - z15.h }, z2.h"
+
+  -
+    input:
+      bytes: [ 0x21, 0x48, 0x7a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w10, 2:3, vgx4], { z1.h - z4.h }, z10.h"
+
+  -
+    input:
+      bytes: [ 0x21, 0x48, 0x7a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w10, 2:3, vgx4], { z1.h - z4.h }, z10.h"
+
+  -
+    input:
+      bytes: [ 0xc1, 0x0a, 0x7e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w8, 2:3, vgx4], { z22.h - z25.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0xc1, 0x0a, 0x7e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w8, 2:3, vgx4], { z22.h - z25.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x22, 0x69, 0x71, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w11, 4:5, vgx4], { z9.h - z12.h }, z1.h"
+
+  -
+    input:
+      bytes: [ 0x22, 0x69, 0x71, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w11, 4:5, vgx4], { z9.h - z12.h }, z1.h"
+
+  -
+    input:
+      bytes: [ 0x83, 0x29, 0x7b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w9, 6:7, vgx4], { z12.h - z15.h }, z11.h"
+
+  -
+    input:
+      bytes: [ 0x83, 0x29, 0x7b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w9, 6:7, vgx4], { z12.h - z15.h }, z11.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x90, 0xd0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w8, 0:1, vgx4], { z0.h - z3.h }, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x90, 0xd0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w8, 0:1, vgx4], { z0.h - z3.h }, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x05, 0xd5, 0xd5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w10, 2:3, vgx4], { z8.h - z11.h }, z5.h[3]"
+
+  -
+    input:
+      bytes: [ 0x05, 0xd5, 0xd5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w10, 2:3, vgx4], { z8.h - z11.h }, z5.h[3]"
+
+  -
+    input:
+      bytes: [ 0x87, 0xfd, 0xd8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w11, 6:7, vgx4], { z12.h - z15.h }, z8.h[7]"
+
+  -
+    input:
+      bytes: [ 0x87, 0xfd, 0xd8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w11, 6:7, vgx4], { z12.h - z15.h }, z8.h[7]"
+
+  -
+    input:
+      bytes: [ 0x87, 0xff, 0xdf, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w11, 6:7, vgx4], { z28.h - z31.h }, z15.h[7]"
+
+  -
+    input:
+      bytes: [ 0x87, 0xff, 0xdf, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w11, 6:7, vgx4], { z28.h - z31.h }, z15.h[7]"
+
+  -
+    input:
+      bytes: [ 0x05, 0x9e, 0xd0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w8, 2:3, vgx4], { z16.h - z19.h }, z0.h[7]"
+
+  -
+    input:
+      bytes: [ 0x05, 0x9e, 0xd0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w8, 2:3, vgx4], { z16.h - z19.h }, z0.h[7]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x94, 0xde, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w8, 2:3, vgx4], { z0.h - z3.h }, z14.h[2]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x94, 0xde, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w8, 2:3, vgx4], { z0.h - z3.h }, z14.h[2]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd6, 0xd4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w10, 0:1, vgx4], { z16.h - z19.h }, z4.h[2]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd6, 0xd4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w10, 0:1, vgx4], { z16.h - z19.h }, z4.h[2]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x99, 0xd2, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w8, 0:1, vgx4], { z12.h - z15.h }, z2.h[4]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x99, 0xd2, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w8, 0:1, vgx4], { z12.h - z15.h }, z2.h[4]"
+
+  -
+    input:
+      bytes: [ 0x01, 0xd8, 0xda, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w10, 2:3, vgx4], { z0.h - z3.h }, z10.h[4]"
+
+  -
+    input:
+      bytes: [ 0x01, 0xd8, 0xda, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w10, 2:3, vgx4], { z0.h - z3.h }, z10.h[4]"
+
+  -
+    input:
+      bytes: [ 0x85, 0x9a, 0xde, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w8, 2:3, vgx4], { z20.h - z23.h }, z14.h[5]"
+
+  -
+    input:
+      bytes: [ 0x85, 0x9a, 0xde, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w8, 2:3, vgx4], { z20.h - z23.h }, z14.h[5]"
+
+  -
+    input:
+      bytes: [ 0x02, 0xf5, 0xd1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w11, 4:5, vgx4], { z8.h - z11.h }, z1.h[2]"
+
+  -
+    input:
+      bytes: [ 0x02, 0xf5, 0xd1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w11, 4:5, vgx4], { z8.h - z11.h }, z1.h[2]"
+
+  -
+    input:
+      bytes: [ 0x87, 0xb9, 0xdb, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w9, 6:7, vgx4], { z12.h - z15.h }, z11.h[5]"
+
+  -
+    input:
+      bytes: [ 0x87, 0xb9, 0xdb, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w9, 6:7, vgx4], { z12.h - z15.h }, z11.h[5]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x08, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w8, 0:1, vgx4], { z0.h - z3.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x08, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w8, 0:1, vgx4], { z0.h - z3.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x49, 0xf5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w10, 2:3, vgx4], { z8.h - z11.h }, { z20.h - z23.h }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x49, 0xf5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w10, 2:3, vgx4], { z8.h - z11.h }, { z20.h - z23.h }"
+
+  -
+    input:
+      bytes: [ 0x83, 0x69, 0xe9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w11, 6:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }"
+
+  -
+    input:
+      bytes: [ 0x83, 0x69, 0xe9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w11, 6:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }"
+
+  -
+    input:
+      bytes: [ 0x83, 0x6b, 0xfd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w11, 6:7, vgx4], { z28.h - z31.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x83, 0x6b, 0xfd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w11, 6:7, vgx4], { z28.h - z31.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x0a, 0xf1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w8, 2:3, vgx4], { z16.h - z19.h }, { z16.h - z19.h }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x0a, 0xf1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w8, 2:3, vgx4], { z16.h - z19.h }, { z16.h - z19.h }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x08, 0xfd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w8, 2:3, vgx4], { z0.h - z3.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x08, 0xfd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w8, 2:3, vgx4], { z0.h - z3.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x4a, 0xf5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w10, 0:1, vgx4], { z16.h - z19.h }, { z20.h - z23.h }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x4a, 0xf5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w10, 0:1, vgx4], { z16.h - z19.h }, { z20.h - z23.h }"
+
+  -
+    input:
+      bytes: [ 0x80, 0x09, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w8, 0:1, vgx4], { z12.h - z15.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x80, 0x09, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w8, 0:1, vgx4], { z12.h - z15.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x48, 0xf9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w10, 2:3, vgx4], { z0.h - z3.h }, { z24.h - z27.h }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x48, 0xf9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w10, 2:3, vgx4], { z0.h - z3.h }, { z24.h - z27.h }"
+
+  -
+    input:
+      bytes: [ 0x81, 0x0a, 0xfd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w8, 2:3, vgx4], { z20.h - z23.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x81, 0x0a, 0xfd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w8, 2:3, vgx4], { z20.h - z23.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x02, 0x69, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w11, 4:5, vgx4], { z8.h - z11.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x02, 0x69, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w11, 4:5, vgx4], { z8.h - z11.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x83, 0x29, 0xe9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w9, 6:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }"
+
+  -
+    input:
+      bytes: [ 0x83, 0x29, 0xe9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal za.s[w9, 6:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }"
diff --git a/tests/MC/AArch64/SME2/smlall.s.yaml b/tests/MC/AArch64/SME2/smlall.s.yaml
new file mode 100644
index 000000000..af6de474f
--- /dev/null
+++ b/tests/MC/AArch64/SME2/smlall.s.yaml
@@ -0,0 +1,3360 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x04, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w8, 0:3], z0.b, z0.b"
+
+  -
+    input:
+      bytes: [ 0x41, 0x45, 0x25, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w10, 4:7], z10.b, z5.b"
+
+  -
+    input:
+      bytes: [ 0xa3, 0x65, 0x28, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w11, 12:15], z13.b, z8.b"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x67, 0x2f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w11, 12:15], z31.b, z15.b"
+
+  -
+    input:
+      bytes: [ 0x21, 0x06, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w8, 4:7], z17.b, z0.b"
+
+  -
+    input:
+      bytes: [ 0x21, 0x04, 0x2e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w8, 4:7], z1.b, z14.b"
+
+  -
+    input:
+      bytes: [ 0x60, 0x46, 0x24, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w10, 0:3], z19.b, z4.b"
+
+  -
+    input:
+      bytes: [ 0x80, 0x05, 0x22, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w8, 0:3], z12.b, z2.b"
+
+  -
+    input:
+      bytes: [ 0x21, 0x44, 0x2a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w10, 4:7], z1.b, z10.b"
+
+  -
+    input:
+      bytes: [ 0xc1, 0x06, 0x2e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w8, 4:7], z22.b, z14.b"
+
+  -
+    input:
+      bytes: [ 0x22, 0x65, 0x21, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w11, 8:11], z9.b, z1.b"
+
+  -
+    input:
+      bytes: [ 0x83, 0x25, 0x2b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w9, 12:15], z12.b, z11.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x00, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w8, 0:3], z0.b, z0.b[0]"
+
+  -
+    input:
+      bytes: [ 0x41, 0x55, 0x05, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w10, 4:7], z10.b, z5.b[5]"
+
+  -
+    input:
+      bytes: [ 0xa3, 0xed, 0x08, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w11, 12:15], z13.b, z8.b[11]"
+
+  -
+    input:
+      bytes: [ 0xe3, 0xff, 0x0f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w11, 12:15], z31.b, z15.b[15]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x0e, 0x00, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w8, 4:7], z17.b, z0.b[3]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x84, 0x0e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w8, 4:7], z1.b, z14.b[9]"
+
+  -
+    input:
+      bytes: [ 0x60, 0x56, 0x04, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w10, 0:3], z19.b, z4.b[5]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x19, 0x02, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w8, 0:3], z12.b, z2.b[6]"
+
+  -
+    input:
+      bytes: [ 0x21, 0xc8, 0x0a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w10, 4:7], z1.b, z10.b[10]"
+
+  -
+    input:
+      bytes: [ 0xc1, 0x0a, 0x0e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w8, 4:7], z22.b, z14.b[2]"
+
+  -
+    input:
+      bytes: [ 0x22, 0xf5, 0x01, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w11, 8:11], z9.b, z1.b[13]"
+
+  -
+    input:
+      bytes: [ 0x83, 0xa9, 0x0b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w9, 12:15], z12.b, z11.b[10]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x04, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w8, 0:3], z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x41, 0x45, 0x65, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w10, 4:7], z10.h, z5.h"
+
+  -
+    input:
+      bytes: [ 0xa3, 0x65, 0x68, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w11, 12:15], z13.h, z8.h"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x67, 0x6f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w11, 12:15], z31.h, z15.h"
+
+  -
+    input:
+      bytes: [ 0x21, 0x06, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w8, 4:7], z17.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x21, 0x04, 0x6e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w8, 4:7], z1.h, z14.h"
+
+  -
+    input:
+      bytes: [ 0x60, 0x46, 0x64, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w10, 0:3], z19.h, z4.h"
+
+  -
+    input:
+      bytes: [ 0x80, 0x05, 0x62, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w8, 0:3], z12.h, z2.h"
+
+  -
+    input:
+      bytes: [ 0x21, 0x44, 0x6a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w10, 4:7], z1.h, z10.h"
+
+  -
+    input:
+      bytes: [ 0xc1, 0x06, 0x6e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w8, 4:7], z22.h, z14.h"
+
+  -
+    input:
+      bytes: [ 0x22, 0x65, 0x61, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w11, 8:11], z9.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0x83, 0x25, 0x6b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w9, 12:15], z12.h, z11.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x80, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w8, 0:3], z0.h, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x41, 0x45, 0x85, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w10, 4:7], z10.h, z5.h[1]"
+
+  -
+    input:
+      bytes: [ 0xa3, 0xed, 0x88, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w11, 12:15], z13.h, z8.h[7]"
+
+  -
+    input:
+      bytes: [ 0xe3, 0xef, 0x8f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w11, 12:15], z31.h, z15.h[7]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x0e, 0x80, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w8, 4:7], z17.h, z0.h[3]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x84, 0x8e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w8, 4:7], z1.h, z14.h[5]"
+
+  -
+    input:
+      bytes: [ 0x60, 0x46, 0x84, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w10, 0:3], z19.h, z4.h[1]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x09, 0x82, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w8, 0:3], z12.h, z2.h[2]"
+
+  -
+    input:
+      bytes: [ 0x21, 0xc8, 0x8a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w10, 4:7], z1.h, z10.h[6]"
+
+  -
+    input:
+      bytes: [ 0xc1, 0x0a, 0x8e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w8, 4:7], z22.h, z14.h[2]"
+
+  -
+    input:
+      bytes: [ 0x22, 0xe5, 0x81, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w11, 8:11], z9.h, z1.h[5]"
+
+  -
+    input:
+      bytes: [ 0x83, 0xa9, 0x8b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w9, 12:15], z12.h, z11.h[6]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w8, 0:3,  vgx2], { z0.b, z1.b }, z0.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w8, 0:3,  vgx2], { z0.b, z1.b }, z0.b"
+
+  -
+    input:
+      bytes: [ 0x41, 0x41, 0x25, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w10, 4:7,  vgx2], { z10.b, z11.b }, z5.b"
+
+  -
+    input:
+      bytes: [ 0x41, 0x41, 0x25, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w10, 4:7,  vgx2], { z10.b, z11.b }, z5.b"
+
+  -
+    input:
+      bytes: [ 0xa1, 0x61, 0x28, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w11, 4:7,  vgx2], { z13.b, z14.b }, z8.b"
+
+  -
+    input:
+      bytes: [ 0xa1, 0x61, 0x28, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w11, 4:7,  vgx2], { z13.b, z14.b }, z8.b"
+
+  -
+    input:
+      bytes: [ 0xe1, 0x63, 0x2f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w11, 4:7,  vgx2], { z31.b, z0.b }, z15.b"
+
+  -
+    input:
+      bytes: [ 0xe1, 0x63, 0x2f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w11, 4:7,  vgx2], { z31.b, z0.b }, z15.b"
+
+  -
+    input:
+      bytes: [ 0x21, 0x02, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w8, 4:7,  vgx2], { z17.b, z18.b }, z0.b"
+
+  -
+    input:
+      bytes: [ 0x21, 0x02, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w8, 4:7,  vgx2], { z17.b, z18.b }, z0.b"
+
+  -
+    input:
+      bytes: [ 0x21, 0x00, 0x2e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w8, 4:7,  vgx2], { z1.b, z2.b }, z14.b"
+
+  -
+    input:
+      bytes: [ 0x21, 0x00, 0x2e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w8, 4:7,  vgx2], { z1.b, z2.b }, z14.b"
+
+  -
+    input:
+      bytes: [ 0x60, 0x42, 0x24, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w10, 0:3,  vgx2], { z19.b, z20.b }, z4.b"
+
+  -
+    input:
+      bytes: [ 0x60, 0x42, 0x24, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w10, 0:3,  vgx2], { z19.b, z20.b }, z4.b"
+
+  -
+    input:
+      bytes: [ 0x80, 0x01, 0x22, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w8, 0:3,  vgx2], { z12.b, z13.b }, z2.b"
+
+  -
+    input:
+      bytes: [ 0x80, 0x01, 0x22, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w8, 0:3,  vgx2], { z12.b, z13.b }, z2.b"
+
+  -
+    input:
+      bytes: [ 0x21, 0x40, 0x2a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w10, 4:7,  vgx2], { z1.b, z2.b }, z10.b"
+
+  -
+    input:
+      bytes: [ 0x21, 0x40, 0x2a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w10, 4:7,  vgx2], { z1.b, z2.b }, z10.b"
+
+  -
+    input:
+      bytes: [ 0xc1, 0x02, 0x2e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w8, 4:7,  vgx2], { z22.b, z23.b }, z14.b"
+
+  -
+    input:
+      bytes: [ 0xc1, 0x02, 0x2e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w8, 4:7,  vgx2], { z22.b, z23.b }, z14.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x61, 0x21, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w11, 0:3,  vgx2], { z9.b, z10.b }, z1.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x61, 0x21, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w11, 0:3,  vgx2], { z9.b, z10.b }, z1.b"
+
+  -
+    input:
+      bytes: [ 0x81, 0x21, 0x2b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w9, 4:7,  vgx2], { z12.b, z13.b }, z11.b"
+
+  -
+    input:
+      bytes: [ 0x81, 0x21, 0x2b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w9, 4:7,  vgx2], { z12.b, z13.b }, z11.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x10, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w8, 0:3, vgx2], { z0.b, z1.b }, z0.b[0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x10, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w8, 0:3, vgx2], { z0.b, z1.b }, z0.b[0]"
+
+  -
+    input:
+      bytes: [ 0x45, 0x45, 0x15, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w10, 4:7, vgx2], { z10.b, z11.b }, z5.b[6]"
+
+  -
+    input:
+      bytes: [ 0x45, 0x45, 0x15, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w10, 4:7, vgx2], { z10.b, z11.b }, z5.b[6]"
+
+  -
+    input:
+      bytes: [ 0x87, 0x6d, 0x18, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w11, 4:7, vgx2], { z12.b, z13.b }, z8.b[15]"
+
+  -
+    input:
+      bytes: [ 0x87, 0x6d, 0x18, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w11, 4:7, vgx2], { z12.b, z13.b }, z8.b[15]"
+
+  -
+    input:
+      bytes: [ 0xc7, 0x6f, 0x1f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w11, 4:7, vgx2], { z30.b, z31.b }, z15.b[15]"
+
+  -
+    input:
+      bytes: [ 0xc7, 0x6f, 0x1f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w11, 4:7, vgx2], { z30.b, z31.b }, z15.b[15]"
+
+  -
+    input:
+      bytes: [ 0x05, 0x0e, 0x10, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w8, 4:7, vgx2], { z16.b, z17.b }, z0.b[14]"
+
+  -
+    input:
+      bytes: [ 0x05, 0x0e, 0x10, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w8, 4:7, vgx2], { z16.b, z17.b }, z0.b[14]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x04, 0x1e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w8, 4:7, vgx2], { z0.b, z1.b }, z14.b[4]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x04, 0x1e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w8, 4:7, vgx2], { z0.b, z1.b }, z14.b[4]"
+
+  -
+    input:
+      bytes: [ 0x40, 0x46, 0x14, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w10, 0:3, vgx2], { z18.b, z19.b }, z4.b[4]"
+
+  -
+    input:
+      bytes: [ 0x40, 0x46, 0x14, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w10, 0:3, vgx2], { z18.b, z19.b }, z4.b[4]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x09, 0x12, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w8, 0:3, vgx2], { z12.b, z13.b }, z2.b[8]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x09, 0x12, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w8, 0:3, vgx2], { z12.b, z13.b }, z2.b[8]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x48, 0x1a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w10, 4:7, vgx2], { z0.b, z1.b }, z10.b[8]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x48, 0x1a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w10, 4:7, vgx2], { z0.b, z1.b }, z10.b[8]"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x0a, 0x1e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w8, 4:7, vgx2], { z22.b, z23.b }, z14.b[10]"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x0a, 0x1e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w8, 4:7, vgx2], { z22.b, z23.b }, z14.b[10]"
+
+  -
+    input:
+      bytes: [ 0x02, 0x65, 0x11, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w11, 0:3, vgx2], { z8.b, z9.b }, z1.b[5]"
+
+  -
+    input:
+      bytes: [ 0x02, 0x65, 0x11, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w11, 0:3, vgx2], { z8.b, z9.b }, z1.b[5]"
+
+  -
+    input:
+      bytes: [ 0x87, 0x29, 0x1b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w9, 4:7, vgx2], { z12.b, z13.b }, z11.b[11]"
+
+  -
+    input:
+      bytes: [ 0x87, 0x29, 0x1b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w9, 4:7, vgx2], { z12.b, z13.b }, z11.b[11]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w8, 0:3, vgx2], { z0.b, z1.b }, { z0.b, z1.b }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w8, 0:3, vgx2], { z0.b, z1.b }, { z0.b, z1.b }"
+
+  -
+    input:
+      bytes: [ 0x41, 0x41, 0xb4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w10, 4:7, vgx2], { z10.b, z11.b }, { z20.b, z21.b }"
+
+  -
+    input:
+      bytes: [ 0x41, 0x41, 0xb4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w10, 4:7, vgx2], { z10.b, z11.b }, { z20.b, z21.b }"
+
+  -
+    input:
+      bytes: [ 0x81, 0x61, 0xa8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w11, 4:7, vgx2], { z12.b, z13.b }, { z8.b, z9.b }"
+
+  -
+    input:
+      bytes: [ 0x81, 0x61, 0xa8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w11, 4:7, vgx2], { z12.b, z13.b }, { z8.b, z9.b }"
+
+  -
+    input:
+      bytes: [ 0xc1, 0x63, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w11, 4:7, vgx2], { z30.b, z31.b }, { z30.b, z31.b }"
+
+  -
+    input:
+      bytes: [ 0xc1, 0x63, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w11, 4:7, vgx2], { z30.b, z31.b }, { z30.b, z31.b }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x02, 0xb0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w8, 4:7, vgx2], { z16.b, z17.b }, { z16.b, z17.b }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x02, 0xb0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w8, 4:7, vgx2], { z16.b, z17.b }, { z16.b, z17.b }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w8, 4:7, vgx2], { z0.b, z1.b }, { z30.b, z31.b }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w8, 4:7, vgx2], { z0.b, z1.b }, { z30.b, z31.b }"
+
+  -
+    input:
+      bytes: [ 0x40, 0x42, 0xb4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w10, 0:3, vgx2], { z18.b, z19.b }, { z20.b, z21.b }"
+
+  -
+    input:
+      bytes: [ 0x40, 0x42, 0xb4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w10, 0:3, vgx2], { z18.b, z19.b }, { z20.b, z21.b }"
+
+  -
+    input:
+      bytes: [ 0x80, 0x01, 0xa2, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w8, 0:3, vgx2], { z12.b, z13.b }, { z2.b, z3.b }"
+
+  -
+    input:
+      bytes: [ 0x80, 0x01, 0xa2, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w8, 0:3, vgx2], { z12.b, z13.b }, { z2.b, z3.b }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x40, 0xba, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w10, 4:7, vgx2], { z0.b, z1.b }, { z26.b, z27.b }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x40, 0xba, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w10, 4:7, vgx2], { z0.b, z1.b }, { z26.b, z27.b }"
+
+  -
+    input:
+      bytes: [ 0xc1, 0x02, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w8, 4:7, vgx2], { z22.b, z23.b }, { z30.b, z31.b }"
+
+  -
+    input:
+      bytes: [ 0xc1, 0x02, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w8, 4:7, vgx2], { z22.b, z23.b }, { z30.b, z31.b }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x61, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w11, 0:3, vgx2], { z8.b, z9.b }, { z0.b, z1.b }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x61, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w11, 0:3, vgx2], { z8.b, z9.b }, { z0.b, z1.b }"
+
+  -
+    input:
+      bytes: [ 0x81, 0x21, 0xaa, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w9, 4:7, vgx2], { z12.b, z13.b }, { z10.b, z11.b }"
+
+  -
+    input:
+      bytes: [ 0x81, 0x21, 0xaa, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w9, 4:7, vgx2], { z12.b, z13.b }, { z10.b, z11.b }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w8, 0:3,  vgx2], { z0.h, z1.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w8, 0:3,  vgx2], { z0.h, z1.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x41, 0x41, 0x65, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w10, 4:7,  vgx2], { z10.h, z11.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0x41, 0x41, 0x65, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w10, 4:7,  vgx2], { z10.h, z11.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0xa1, 0x61, 0x68, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w11, 4:7,  vgx2], { z13.h, z14.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0xa1, 0x61, 0x68, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w11, 4:7,  vgx2], { z13.h, z14.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0xe1, 0x63, 0x6f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w11, 4:7,  vgx2], { z31.h, z0.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0xe1, 0x63, 0x6f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w11, 4:7,  vgx2], { z31.h, z0.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0x21, 0x02, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w8, 4:7,  vgx2], { z17.h, z18.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x21, 0x02, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w8, 4:7,  vgx2], { z17.h, z18.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x21, 0x00, 0x6e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w8, 4:7,  vgx2], { z1.h, z2.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x21, 0x00, 0x6e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w8, 4:7,  vgx2], { z1.h, z2.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x60, 0x42, 0x64, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w10, 0:3,  vgx2], { z19.h, z20.h }, z4.h"
+
+  -
+    input:
+      bytes: [ 0x60, 0x42, 0x64, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w10, 0:3,  vgx2], { z19.h, z20.h }, z4.h"
+
+  -
+    input:
+      bytes: [ 0x80, 0x01, 0x62, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w8, 0:3,  vgx2], { z12.h, z13.h }, z2.h"
+
+  -
+    input:
+      bytes: [ 0x80, 0x01, 0x62, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w8, 0:3,  vgx2], { z12.h, z13.h }, z2.h"
+
+  -
+    input:
+      bytes: [ 0x21, 0x40, 0x6a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w10, 4:7,  vgx2], { z1.h, z2.h }, z10.h"
+
+  -
+    input:
+      bytes: [ 0x21, 0x40, 0x6a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w10, 4:7,  vgx2], { z1.h, z2.h }, z10.h"
+
+  -
+    input:
+      bytes: [ 0xc1, 0x02, 0x6e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w8, 4:7,  vgx2], { z22.h, z23.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0xc1, 0x02, 0x6e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w8, 4:7,  vgx2], { z22.h, z23.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x61, 0x61, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w11, 0:3,  vgx2], { z9.h, z10.h }, z1.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x61, 0x61, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w11, 0:3,  vgx2], { z9.h, z10.h }, z1.h"
+
+  -
+    input:
+      bytes: [ 0x81, 0x21, 0x6b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w9, 4:7,  vgx2], { z12.h, z13.h }, z11.h"
+
+  -
+    input:
+      bytes: [ 0x81, 0x21, 0x6b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w9, 4:7,  vgx2], { z12.h, z13.h }, z11.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x90, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w8, 0:3, vgx2], { z0.h, z1.h }, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x90, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w8, 0:3, vgx2], { z0.h, z1.h }, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x45, 0x45, 0x95, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w10, 4:7, vgx2], { z10.h, z11.h }, z5.h[6]"
+
+  -
+    input:
+      bytes: [ 0x45, 0x45, 0x95, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w10, 4:7, vgx2], { z10.h, z11.h }, z5.h[6]"
+
+  -
+    input:
+      bytes: [ 0x87, 0x65, 0x98, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w11, 4:7, vgx2], { z12.h, z13.h }, z8.h[7]"
+
+  -
+    input:
+      bytes: [ 0x87, 0x65, 0x98, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w11, 4:7, vgx2], { z12.h, z13.h }, z8.h[7]"
+
+  -
+    input:
+      bytes: [ 0xc7, 0x67, 0x9f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w11, 4:7, vgx2], { z30.h, z31.h }, z15.h[7]"
+
+  -
+    input:
+      bytes: [ 0xc7, 0x67, 0x9f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w11, 4:7, vgx2], { z30.h, z31.h }, z15.h[7]"
+
+  -
+    input:
+      bytes: [ 0x05, 0x06, 0x90, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w8, 4:7, vgx2], { z16.h, z17.h }, z0.h[6]"
+
+  -
+    input:
+      bytes: [ 0x05, 0x06, 0x90, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w8, 4:7, vgx2], { z16.h, z17.h }, z0.h[6]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x04, 0x9e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w8, 4:7, vgx2], { z0.h, z1.h }, z14.h[4]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x04, 0x9e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w8, 4:7, vgx2], { z0.h, z1.h }, z14.h[4]"
+
+  -
+    input:
+      bytes: [ 0x40, 0x46, 0x94, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w10, 0:3, vgx2], { z18.h, z19.h }, z4.h[4]"
+
+  -
+    input:
+      bytes: [ 0x40, 0x46, 0x94, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w10, 0:3, vgx2], { z18.h, z19.h }, z4.h[4]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x01, 0x92, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w8, 0:3, vgx2], { z12.h, z13.h }, z2.h[0]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x01, 0x92, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w8, 0:3, vgx2], { z12.h, z13.h }, z2.h[0]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x40, 0x9a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w10, 4:7, vgx2], { z0.h, z1.h }, z10.h[0]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x40, 0x9a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w10, 4:7, vgx2], { z0.h, z1.h }, z10.h[0]"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x02, 0x9e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w8, 4:7, vgx2], { z22.h, z23.h }, z14.h[2]"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x02, 0x9e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w8, 4:7, vgx2], { z22.h, z23.h }, z14.h[2]"
+
+  -
+    input:
+      bytes: [ 0x02, 0x65, 0x91, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w11, 0:3, vgx2], { z8.h, z9.h }, z1.h[5]"
+
+  -
+    input:
+      bytes: [ 0x02, 0x65, 0x91, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w11, 0:3, vgx2], { z8.h, z9.h }, z1.h[5]"
+
+  -
+    input:
+      bytes: [ 0x87, 0x21, 0x9b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w9, 4:7, vgx2], { z12.h, z13.h }, z11.h[3]"
+
+  -
+    input:
+      bytes: [ 0x87, 0x21, 0x9b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w9, 4:7, vgx2], { z12.h, z13.h }, z11.h[3]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w8, 0:3, vgx2], { z0.h, z1.h }, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w8, 0:3, vgx2], { z0.h, z1.h }, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x41, 0x41, 0xf4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w10, 4:7, vgx2], { z10.h, z11.h }, { z20.h, z21.h }"
+
+  -
+    input:
+      bytes: [ 0x41, 0x41, 0xf4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w10, 4:7, vgx2], { z10.h, z11.h }, { z20.h, z21.h }"
+
+  -
+    input:
+      bytes: [ 0x81, 0x61, 0xe8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w11, 4:7, vgx2], { z12.h, z13.h }, { z8.h, z9.h }"
+
+  -
+    input:
+      bytes: [ 0x81, 0x61, 0xe8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w11, 4:7, vgx2], { z12.h, z13.h }, { z8.h, z9.h }"
+
+  -
+    input:
+      bytes: [ 0xc1, 0x63, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w11, 4:7, vgx2], { z30.h, z31.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0xc1, 0x63, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w11, 4:7, vgx2], { z30.h, z31.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x02, 0xf0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w8, 4:7, vgx2], { z16.h, z17.h }, { z16.h, z17.h }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x02, 0xf0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w8, 4:7, vgx2], { z16.h, z17.h }, { z16.h, z17.h }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w8, 4:7, vgx2], { z0.h, z1.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w8, 4:7, vgx2], { z0.h, z1.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x40, 0x42, 0xf4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w10, 0:3, vgx2], { z18.h, z19.h }, { z20.h, z21.h }"
+
+  -
+    input:
+      bytes: [ 0x40, 0x42, 0xf4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w10, 0:3, vgx2], { z18.h, z19.h }, { z20.h, z21.h }"
+
+  -
+    input:
+      bytes: [ 0x80, 0x01, 0xe2, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w8, 0:3, vgx2], { z12.h, z13.h }, { z2.h, z3.h }"
+
+  -
+    input:
+      bytes: [ 0x80, 0x01, 0xe2, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w8, 0:3, vgx2], { z12.h, z13.h }, { z2.h, z3.h }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x40, 0xfa, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w10, 4:7, vgx2], { z0.h, z1.h }, { z26.h, z27.h }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x40, 0xfa, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w10, 4:7, vgx2], { z0.h, z1.h }, { z26.h, z27.h }"
+
+  -
+    input:
+      bytes: [ 0xc1, 0x02, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w8, 4:7, vgx2], { z22.h, z23.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0xc1, 0x02, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w8, 4:7, vgx2], { z22.h, z23.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x61, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w11, 0:3, vgx2], { z8.h, z9.h }, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x61, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w11, 0:3, vgx2], { z8.h, z9.h }, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x81, 0x21, 0xea, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w9, 4:7, vgx2], { z12.h, z13.h }, { z10.h, z11.h }"
+
+  -
+    input:
+      bytes: [ 0x81, 0x21, 0xea, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w9, 4:7, vgx2], { z12.h, z13.h }, { z10.h, z11.h }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x30, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w8, 0:3,  vgx4], { z0.b - z3.b }, z0.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x30, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w8, 0:3,  vgx4], { z0.b - z3.b }, z0.b"
+
+  -
+    input:
+      bytes: [ 0x41, 0x41, 0x35, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w10, 4:7,  vgx4], { z10.b - z13.b }, z5.b"
+
+  -
+    input:
+      bytes: [ 0x41, 0x41, 0x35, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w10, 4:7,  vgx4], { z10.b - z13.b }, z5.b"
+
+  -
+    input:
+      bytes: [ 0xa1, 0x61, 0x38, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w11, 4:7,  vgx4], { z13.b - z16.b }, z8.b"
+
+  -
+    input:
+      bytes: [ 0xa1, 0x61, 0x38, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w11, 4:7,  vgx4], { z13.b - z16.b }, z8.b"
+
+  -
+    input:
+      bytes: [ 0xe1, 0x63, 0x3f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w11, 4:7,  vgx4], { z31.b, z0.b, z1.b, z2.b }, z15.b"
+
+  -
+    input:
+      bytes: [ 0xe1, 0x63, 0x3f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w11, 4:7,  vgx4], { z31.b, z0.b, z1.b, z2.b }, z15.b"
+
+  -
+    input:
+      bytes: [ 0x21, 0x02, 0x30, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w8, 4:7,  vgx4], { z17.b - z20.b }, z0.b"
+
+  -
+    input:
+      bytes: [ 0x21, 0x02, 0x30, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w8, 4:7,  vgx4], { z17.b - z20.b }, z0.b"
+
+  -
+    input:
+      bytes: [ 0x21, 0x00, 0x3e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w8, 4:7,  vgx4], { z1.b - z4.b }, z14.b"
+
+  -
+    input:
+      bytes: [ 0x21, 0x00, 0x3e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w8, 4:7,  vgx4], { z1.b - z4.b }, z14.b"
+
+  -
+    input:
+      bytes: [ 0x60, 0x42, 0x34, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w10, 0:3,  vgx4], { z19.b - z22.b }, z4.b"
+
+  -
+    input:
+      bytes: [ 0x60, 0x42, 0x34, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w10, 0:3,  vgx4], { z19.b - z22.b }, z4.b"
+
+  -
+    input:
+      bytes: [ 0x80, 0x01, 0x32, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w8, 0:3,  vgx4], { z12.b - z15.b }, z2.b"
+
+  -
+    input:
+      bytes: [ 0x80, 0x01, 0x32, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w8, 0:3,  vgx4], { z12.b - z15.b }, z2.b"
+
+  -
+    input:
+      bytes: [ 0x21, 0x40, 0x3a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w10, 4:7,  vgx4], { z1.b - z4.b }, z10.b"
+
+  -
+    input:
+      bytes: [ 0x21, 0x40, 0x3a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w10, 4:7,  vgx4], { z1.b - z4.b }, z10.b"
+
+  -
+    input:
+      bytes: [ 0xc1, 0x02, 0x3e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w8, 4:7,  vgx4], { z22.b - z25.b }, z14.b"
+
+  -
+    input:
+      bytes: [ 0xc1, 0x02, 0x3e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w8, 4:7,  vgx4], { z22.b - z25.b }, z14.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x61, 0x31, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w11, 0:3,  vgx4], { z9.b - z12.b }, z1.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x61, 0x31, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w11, 0:3,  vgx4], { z9.b - z12.b }, z1.b"
+
+  -
+    input:
+      bytes: [ 0x81, 0x21, 0x3b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w9, 4:7,  vgx4], { z12.b - z15.b }, z11.b"
+
+  -
+    input:
+      bytes: [ 0x81, 0x21, 0x3b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w9, 4:7,  vgx4], { z12.b - z15.b }, z11.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x10, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w8, 0:3, vgx4], { z0.b - z3.b }, z0.b[0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x10, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w8, 0:3, vgx4], { z0.b - z3.b }, z0.b[0]"
+
+  -
+    input:
+      bytes: [ 0x05, 0xc5, 0x15, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w10, 4:7, vgx4], { z8.b - z11.b }, z5.b[6]"
+
+  -
+    input:
+      bytes: [ 0x05, 0xc5, 0x15, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w10, 4:7, vgx4], { z8.b - z11.b }, z5.b[6]"
+
+  -
+    input:
+      bytes: [ 0x87, 0xed, 0x18, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w11, 4:7, vgx4], { z12.b - z15.b }, z8.b[15]"
+
+  -
+    input:
+      bytes: [ 0x87, 0xed, 0x18, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w11, 4:7, vgx4], { z12.b - z15.b }, z8.b[15]"
+
+  -
+    input:
+      bytes: [ 0x87, 0xef, 0x1f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w11, 4:7, vgx4], { z28.b - z31.b }, z15.b[15]"
+
+  -
+    input:
+      bytes: [ 0x87, 0xef, 0x1f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w11, 4:7, vgx4], { z28.b - z31.b }, z15.b[15]"
+
+  -
+    input:
+      bytes: [ 0x05, 0x8e, 0x10, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w8, 4:7, vgx4], { z16.b - z19.b }, z0.b[14]"
+
+  -
+    input:
+      bytes: [ 0x05, 0x8e, 0x10, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w8, 4:7, vgx4], { z16.b - z19.b }, z0.b[14]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x84, 0x1e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w8, 4:7, vgx4], { z0.b - z3.b }, z14.b[4]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x84, 0x1e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w8, 4:7, vgx4], { z0.b - z3.b }, z14.b[4]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc6, 0x14, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w10, 0:3, vgx4], { z16.b - z19.b }, z4.b[4]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc6, 0x14, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w10, 0:3, vgx4], { z16.b - z19.b }, z4.b[4]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x89, 0x12, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w8, 0:3, vgx4], { z12.b - z15.b }, z2.b[8]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x89, 0x12, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w8, 0:3, vgx4], { z12.b - z15.b }, z2.b[8]"
+
+  -
+    input:
+      bytes: [ 0x01, 0xc8, 0x1a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w10, 4:7, vgx4], { z0.b - z3.b }, z10.b[8]"
+
+  -
+    input:
+      bytes: [ 0x01, 0xc8, 0x1a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w10, 4:7, vgx4], { z0.b - z3.b }, z10.b[8]"
+
+  -
+    input:
+      bytes: [ 0x85, 0x8a, 0x1e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w8, 4:7, vgx4], { z20.b - z23.b }, z14.b[10]"
+
+  -
+    input:
+      bytes: [ 0x85, 0x8a, 0x1e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w8, 4:7, vgx4], { z20.b - z23.b }, z14.b[10]"
+
+  -
+    input:
+      bytes: [ 0x02, 0xe5, 0x11, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w11, 0:3, vgx4], { z8.b - z11.b }, z1.b[5]"
+
+  -
+    input:
+      bytes: [ 0x02, 0xe5, 0x11, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w11, 0:3, vgx4], { z8.b - z11.b }, z1.b[5]"
+
+  -
+    input:
+      bytes: [ 0x87, 0xa9, 0x1b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w9, 4:7, vgx4], { z12.b - z15.b }, z11.b[11]"
+
+  -
+    input:
+      bytes: [ 0x87, 0xa9, 0x1b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w9, 4:7, vgx4], { z12.b - z15.b }, z11.b[11]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w8, 0:3, vgx4], { z0.b - z3.b }, { z0.b - z3.b }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w8, 0:3, vgx4], { z0.b - z3.b }, { z0.b - z3.b }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x41, 0xb5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w10, 4:7, vgx4], { z8.b - z11.b }, { z20.b - z23.b }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x41, 0xb5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w10, 4:7, vgx4], { z8.b - z11.b }, { z20.b - z23.b }"
+
+  -
+    input:
+      bytes: [ 0x81, 0x61, 0xa9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w11, 4:7, vgx4], { z12.b - z15.b }, { z8.b - z11.b }"
+
+  -
+    input:
+      bytes: [ 0x81, 0x61, 0xa9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w11, 4:7, vgx4], { z12.b - z15.b }, { z8.b - z11.b }"
+
+  -
+    input:
+      bytes: [ 0x81, 0x63, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w11, 4:7, vgx4], { z28.b - z31.b }, { z28.b - z31.b }"
+
+  -
+    input:
+      bytes: [ 0x81, 0x63, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w11, 4:7, vgx4], { z28.b - z31.b }, { z28.b - z31.b }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x02, 0xb1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w8, 4:7, vgx4], { z16.b - z19.b }, { z16.b - z19.b }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x02, 0xb1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w8, 4:7, vgx4], { z16.b - z19.b }, { z16.b - z19.b }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w8, 4:7, vgx4], { z0.b - z3.b }, { z28.b - z31.b }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w8, 4:7, vgx4], { z0.b - z3.b }, { z28.b - z31.b }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x42, 0xb5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w10, 0:3, vgx4], { z16.b - z19.b }, { z20.b - z23.b }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x42, 0xb5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w10, 0:3, vgx4], { z16.b - z19.b }, { z20.b - z23.b }"
+
+  -
+    input:
+      bytes: [ 0x80, 0x01, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w8, 0:3, vgx4], { z12.b - z15.b }, { z0.b - z3.b }"
+
+  -
+    input:
+      bytes: [ 0x80, 0x01, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w8, 0:3, vgx4], { z12.b - z15.b }, { z0.b - z3.b }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x40, 0xb9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w10, 4:7, vgx4], { z0.b - z3.b }, { z24.b - z27.b }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x40, 0xb9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w10, 4:7, vgx4], { z0.b - z3.b }, { z24.b - z27.b }"
+
+  -
+    input:
+      bytes: [ 0x81, 0x02, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w8, 4:7, vgx4], { z20.b - z23.b }, { z28.b - z31.b }"
+
+  -
+    input:
+      bytes: [ 0x81, 0x02, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w8, 4:7, vgx4], { z20.b - z23.b }, { z28.b - z31.b }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x61, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w11, 0:3, vgx4], { z8.b - z11.b }, { z0.b - z3.b }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x61, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w11, 0:3, vgx4], { z8.b - z11.b }, { z0.b - z3.b }"
+
+  -
+    input:
+      bytes: [ 0x81, 0x21, 0xa9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w9, 4:7, vgx4], { z12.b - z15.b }, { z8.b - z11.b }"
+
+  -
+    input:
+      bytes: [ 0x81, 0x21, 0xa9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.s[w9, 4:7, vgx4], { z12.b - z15.b }, { z8.b - z11.b }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x70, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w8, 0:3,  vgx4], { z0.h - z3.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x70, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w8, 0:3,  vgx4], { z0.h - z3.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x41, 0x41, 0x75, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w10, 4:7,  vgx4], { z10.h - z13.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0x41, 0x41, 0x75, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w10, 4:7,  vgx4], { z10.h - z13.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0xa1, 0x61, 0x78, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w11, 4:7,  vgx4], { z13.h - z16.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0xa1, 0x61, 0x78, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w11, 4:7,  vgx4], { z13.h - z16.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0xe1, 0x63, 0x7f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w11, 4:7,  vgx4], { z31.h, z0.h, z1.h, z2.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0xe1, 0x63, 0x7f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w11, 4:7,  vgx4], { z31.h, z0.h, z1.h, z2.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0x21, 0x02, 0x70, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w8, 4:7,  vgx4], { z17.h - z20.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x21, 0x02, 0x70, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w8, 4:7,  vgx4], { z17.h - z20.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x21, 0x00, 0x7e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w8, 4:7,  vgx4], { z1.h - z4.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x21, 0x00, 0x7e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w8, 4:7,  vgx4], { z1.h - z4.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x60, 0x42, 0x74, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w10, 0:3,  vgx4], { z19.h - z22.h }, z4.h"
+
+  -
+    input:
+      bytes: [ 0x60, 0x42, 0x74, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w10, 0:3,  vgx4], { z19.h - z22.h }, z4.h"
+
+  -
+    input:
+      bytes: [ 0x80, 0x01, 0x72, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w8, 0:3,  vgx4], { z12.h - z15.h }, z2.h"
+
+  -
+    input:
+      bytes: [ 0x80, 0x01, 0x72, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w8, 0:3,  vgx4], { z12.h - z15.h }, z2.h"
+
+  -
+    input:
+      bytes: [ 0x21, 0x40, 0x7a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w10, 4:7,  vgx4], { z1.h - z4.h }, z10.h"
+
+  -
+    input:
+      bytes: [ 0x21, 0x40, 0x7a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w10, 4:7,  vgx4], { z1.h - z4.h }, z10.h"
+
+  -
+    input:
+      bytes: [ 0xc1, 0x02, 0x7e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w8, 4:7,  vgx4], { z22.h - z25.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0xc1, 0x02, 0x7e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w8, 4:7,  vgx4], { z22.h - z25.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x61, 0x71, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w11, 0:3,  vgx4], { z9.h - z12.h }, z1.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x61, 0x71, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w11, 0:3,  vgx4], { z9.h - z12.h }, z1.h"
+
+  -
+    input:
+      bytes: [ 0x81, 0x21, 0x7b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w9, 4:7,  vgx4], { z12.h - z15.h }, z11.h"
+
+  -
+    input:
+      bytes: [ 0x81, 0x21, 0x7b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w9, 4:7,  vgx4], { z12.h - z15.h }, z11.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x90, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w8, 0:3, vgx4], { z0.h - z3.h }, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x90, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w8, 0:3, vgx4], { z0.h - z3.h }, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x05, 0xc5, 0x95, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w10, 4:7, vgx4], { z8.h - z11.h }, z5.h[6]"
+
+  -
+    input:
+      bytes: [ 0x05, 0xc5, 0x95, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w10, 4:7, vgx4], { z8.h - z11.h }, z5.h[6]"
+
+  -
+    input:
+      bytes: [ 0x87, 0xe5, 0x98, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w11, 4:7, vgx4], { z12.h - z15.h }, z8.h[7]"
+
+  -
+    input:
+      bytes: [ 0x87, 0xe5, 0x98, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w11, 4:7, vgx4], { z12.h - z15.h }, z8.h[7]"
+
+  -
+    input:
+      bytes: [ 0x87, 0xe7, 0x9f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w11, 4:7, vgx4], { z28.h - z31.h }, z15.h[7]"
+
+  -
+    input:
+      bytes: [ 0x87, 0xe7, 0x9f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w11, 4:7, vgx4], { z28.h - z31.h }, z15.h[7]"
+
+  -
+    input:
+      bytes: [ 0x05, 0x86, 0x90, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w8, 4:7, vgx4], { z16.h - z19.h }, z0.h[6]"
+
+  -
+    input:
+      bytes: [ 0x05, 0x86, 0x90, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w8, 4:7, vgx4], { z16.h - z19.h }, z0.h[6]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x84, 0x9e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w8, 4:7, vgx4], { z0.h - z3.h }, z14.h[4]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x84, 0x9e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w8, 4:7, vgx4], { z0.h - z3.h }, z14.h[4]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc6, 0x94, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w10, 0:3, vgx4], { z16.h - z19.h }, z4.h[4]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc6, 0x94, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w10, 0:3, vgx4], { z16.h - z19.h }, z4.h[4]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x81, 0x92, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w8, 0:3, vgx4], { z12.h - z15.h }, z2.h[0]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x81, 0x92, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w8, 0:3, vgx4], { z12.h - z15.h }, z2.h[0]"
+
+  -
+    input:
+      bytes: [ 0x01, 0xc0, 0x9a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w10, 4:7, vgx4], { z0.h - z3.h }, z10.h[0]"
+
+  -
+    input:
+      bytes: [ 0x01, 0xc0, 0x9a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w10, 4:7, vgx4], { z0.h - z3.h }, z10.h[0]"
+
+  -
+    input:
+      bytes: [ 0x85, 0x82, 0x9e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w8, 4:7, vgx4], { z20.h - z23.h }, z14.h[2]"
+
+  -
+    input:
+      bytes: [ 0x85, 0x82, 0x9e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w8, 4:7, vgx4], { z20.h - z23.h }, z14.h[2]"
+
+  -
+    input:
+      bytes: [ 0x02, 0xe5, 0x91, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w11, 0:3, vgx4], { z8.h - z11.h }, z1.h[5]"
+
+  -
+    input:
+      bytes: [ 0x02, 0xe5, 0x91, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w11, 0:3, vgx4], { z8.h - z11.h }, z1.h[5]"
+
+  -
+    input:
+      bytes: [ 0x87, 0xa1, 0x9b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w9, 4:7, vgx4], { z12.h - z15.h }, z11.h[3]"
+
+  -
+    input:
+      bytes: [ 0x87, 0xa1, 0x9b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w9, 4:7, vgx4], { z12.h - z15.h }, z11.h[3]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w8, 0:3, vgx4], { z0.h - z3.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w8, 0:3, vgx4], { z0.h - z3.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x41, 0xf5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w10, 4:7, vgx4], { z8.h - z11.h }, { z20.h - z23.h }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x41, 0xf5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w10, 4:7, vgx4], { z8.h - z11.h }, { z20.h - z23.h }"
+
+  -
+    input:
+      bytes: [ 0x81, 0x61, 0xe9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w11, 4:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }"
+
+  -
+    input:
+      bytes: [ 0x81, 0x61, 0xe9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w11, 4:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }"
+
+  -
+    input:
+      bytes: [ 0x81, 0x63, 0xfd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w11, 4:7, vgx4], { z28.h - z31.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x81, 0x63, 0xfd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w11, 4:7, vgx4], { z28.h - z31.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x02, 0xf1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w8, 4:7, vgx4], { z16.h - z19.h }, { z16.h - z19.h }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x02, 0xf1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w8, 4:7, vgx4], { z16.h - z19.h }, { z16.h - z19.h }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0xfd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w8, 4:7, vgx4], { z0.h - z3.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0xfd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w8, 4:7, vgx4], { z0.h - z3.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x42, 0xf5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w10, 0:3, vgx4], { z16.h - z19.h }, { z20.h - z23.h }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x42, 0xf5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w10, 0:3, vgx4], { z16.h - z19.h }, { z20.h - z23.h }"
+
+  -
+    input:
+      bytes: [ 0x80, 0x01, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w8, 0:3, vgx4], { z12.h - z15.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x80, 0x01, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w8, 0:3, vgx4], { z12.h - z15.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x40, 0xf9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w10, 4:7, vgx4], { z0.h - z3.h }, { z24.h - z27.h }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x40, 0xf9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w10, 4:7, vgx4], { z0.h - z3.h }, { z24.h - z27.h }"
+
+  -
+    input:
+      bytes: [ 0x81, 0x02, 0xfd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w8, 4:7, vgx4], { z20.h - z23.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x81, 0x02, 0xfd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w8, 4:7, vgx4], { z20.h - z23.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x61, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w11, 0:3, vgx4], { z8.h - z11.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x61, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w11, 0:3, vgx4], { z8.h - z11.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x81, 0x21, 0xe9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w9, 4:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }"
+
+  -
+    input:
+      bytes: [ 0x81, 0x21, 0xe9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlall za.d[w9, 4:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }"
diff --git a/tests/MC/AArch64/SME2/smlsl.s.yaml b/tests/MC/AArch64/SME2/smlsl.s.yaml
new file mode 100644
index 000000000..8a4515b77
--- /dev/null
+++ b/tests/MC/AArch64/SME2/smlsl.s.yaml
@@ -0,0 +1,1680 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x08, 0x0c, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w8, 0:1], z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x4d, 0x4d, 0x65, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w10, 10:11], z10.h, z5.h"
+
+  -
+    input:
+      bytes: [ 0xaf, 0x6d, 0x68, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w11, 14:15], z13.h, z8.h"
+
+  -
+    input:
+      bytes: [ 0xef, 0x6f, 0x6f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w11, 14:15], z31.h, z15.h"
+
+  -
+    input:
+      bytes: [ 0x2d, 0x0e, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w8, 10:11], z17.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x29, 0x0c, 0x6e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w8, 2:3], z1.h, z14.h"
+
+  -
+    input:
+      bytes: [ 0x68, 0x4e, 0x64, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w10, 0:1], z19.h, z4.h"
+
+  -
+    input:
+      bytes: [ 0x88, 0x0d, 0x62, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w8, 0:1], z12.h, z2.h"
+
+  -
+    input:
+      bytes: [ 0x29, 0x4c, 0x6a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w10, 2:3], z1.h, z10.h"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x0e, 0x6e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w8, 10:11], z22.h, z14.h"
+
+  -
+    input:
+      bytes: [ 0x2a, 0x6d, 0x61, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w11, 4:5], z9.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x2d, 0x6b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w9, 14:15], z12.h, z11.h"
+
+  -
+    input:
+      bytes: [ 0x08, 0x10, 0xc0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w8, 0:1], z0.h, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x4d, 0x55, 0xc5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w10, 10:11], z10.h, z5.h[1]"
+
+  -
+    input:
+      bytes: [ 0xaf, 0xfd, 0xc8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w11, 14:15], z13.h, z8.h[7]"
+
+  -
+    input:
+      bytes: [ 0xef, 0xff, 0xcf, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w11, 14:15], z31.h, z15.h[7]"
+
+  -
+    input:
+      bytes: [ 0x2d, 0x1e, 0xc0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w8, 10:11], z17.h, z0.h[3]"
+
+  -
+    input:
+      bytes: [ 0x29, 0x94, 0xce, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w8, 2:3], z1.h, z14.h[5]"
+
+  -
+    input:
+      bytes: [ 0x68, 0x56, 0xc4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w10, 0:1], z19.h, z4.h[1]"
+
+  -
+    input:
+      bytes: [ 0x88, 0x19, 0xc2, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w8, 0:1], z12.h, z2.h[2]"
+
+  -
+    input:
+      bytes: [ 0x29, 0xd8, 0xca, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w10, 2:3], z1.h, z10.h[6]"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x1a, 0xce, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w8, 10:11], z22.h, z14.h[2]"
+
+  -
+    input:
+      bytes: [ 0x2a, 0xf5, 0xc1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w11, 4:5], z9.h, z1.h[5]"
+
+  -
+    input:
+      bytes: [ 0x8f, 0xb9, 0xcb, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w9, 14:15], z12.h, z11.h[6]"
+
+  -
+    input:
+      bytes: [ 0x08, 0x08, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w8, 0:1, vgx2], { z0.h, z1.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x08, 0x08, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w8, 0:1, vgx2], { z0.h, z1.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x49, 0x49, 0x65, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w10, 2:3, vgx2], { z10.h, z11.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0x49, 0x49, 0x65, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w10, 2:3, vgx2], { z10.h, z11.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0xab, 0x69, 0x68, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w11, 6:7, vgx2], { z13.h, z14.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0xab, 0x69, 0x68, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w11, 6:7, vgx2], { z13.h, z14.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0xeb, 0x6b, 0x6f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w11, 6:7, vgx2], { z31.h, z0.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0xeb, 0x6b, 0x6f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w11, 6:7, vgx2], { z31.h, z0.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0x29, 0x0a, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w8, 2:3, vgx2], { z17.h, z18.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x29, 0x0a, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w8, 2:3, vgx2], { z17.h, z18.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x29, 0x08, 0x6e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w8, 2:3, vgx2], { z1.h, z2.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x29, 0x08, 0x6e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w8, 2:3, vgx2], { z1.h, z2.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x68, 0x4a, 0x64, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w10, 0:1, vgx2], { z19.h, z20.h }, z4.h"
+
+  -
+    input:
+      bytes: [ 0x68, 0x4a, 0x64, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w10, 0:1, vgx2], { z19.h, z20.h }, z4.h"
+
+  -
+    input:
+      bytes: [ 0x88, 0x09, 0x62, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w8, 0:1, vgx2], { z12.h, z13.h }, z2.h"
+
+  -
+    input:
+      bytes: [ 0x88, 0x09, 0x62, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w8, 0:1, vgx2], { z12.h, z13.h }, z2.h"
+
+  -
+    input:
+      bytes: [ 0x29, 0x48, 0x6a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w10, 2:3, vgx2], { z1.h, z2.h }, z10.h"
+
+  -
+    input:
+      bytes: [ 0x29, 0x48, 0x6a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w10, 2:3, vgx2], { z1.h, z2.h }, z10.h"
+
+  -
+    input:
+      bytes: [ 0xc9, 0x0a, 0x6e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w8, 2:3, vgx2], { z22.h, z23.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0xc9, 0x0a, 0x6e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w8, 2:3, vgx2], { z22.h, z23.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x2a, 0x69, 0x61, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w11, 4:5, vgx2], { z9.h, z10.h }, z1.h"
+
+  -
+    input:
+      bytes: [ 0x2a, 0x69, 0x61, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w11, 4:5, vgx2], { z9.h, z10.h }, z1.h"
+
+  -
+    input:
+      bytes: [ 0x8b, 0x29, 0x6b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w9, 6:7, vgx2], { z12.h, z13.h }, z11.h"
+
+  -
+    input:
+      bytes: [ 0x8b, 0x29, 0x6b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w9, 6:7, vgx2], { z12.h, z13.h }, z11.h"
+
+  -
+    input:
+      bytes: [ 0x08, 0x10, 0xd0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w8, 0:1, vgx2], { z0.h, z1.h }, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x08, 0x10, 0xd0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w8, 0:1, vgx2], { z0.h, z1.h }, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x4d, 0x55, 0xd5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w10, 2:3, vgx2], { z10.h, z11.h }, z5.h[3]"
+
+  -
+    input:
+      bytes: [ 0x4d, 0x55, 0xd5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w10, 2:3, vgx2], { z10.h, z11.h }, z5.h[3]"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x7d, 0xd8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w11, 6:7, vgx2], { z12.h, z13.h }, z8.h[7]"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x7d, 0xd8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w11, 6:7, vgx2], { z12.h, z13.h }, z8.h[7]"
+
+  -
+    input:
+      bytes: [ 0xcf, 0x7f, 0xdf, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w11, 6:7, vgx2], { z30.h, z31.h }, z15.h[7]"
+
+  -
+    input:
+      bytes: [ 0xcf, 0x7f, 0xdf, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w11, 6:7, vgx2], { z30.h, z31.h }, z15.h[7]"
+
+  -
+    input:
+      bytes: [ 0x0d, 0x1e, 0xd0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w8, 2:3, vgx2], { z16.h, z17.h }, z0.h[7]"
+
+  -
+    input:
+      bytes: [ 0x0d, 0x1e, 0xd0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w8, 2:3, vgx2], { z16.h, z17.h }, z0.h[7]"
+
+  -
+    input:
+      bytes: [ 0x09, 0x14, 0xde, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w8, 2:3, vgx2], { z0.h, z1.h }, z14.h[2]"
+
+  -
+    input:
+      bytes: [ 0x09, 0x14, 0xde, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w8, 2:3, vgx2], { z0.h, z1.h }, z14.h[2]"
+
+  -
+    input:
+      bytes: [ 0x48, 0x56, 0xd4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w10, 0:1, vgx2], { z18.h, z19.h }, z4.h[2]"
+
+  -
+    input:
+      bytes: [ 0x48, 0x56, 0xd4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w10, 0:1, vgx2], { z18.h, z19.h }, z4.h[2]"
+
+  -
+    input:
+      bytes: [ 0x88, 0x19, 0xd2, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w8, 0:1, vgx2], { z12.h, z13.h }, z2.h[4]"
+
+  -
+    input:
+      bytes: [ 0x88, 0x19, 0xd2, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w8, 0:1, vgx2], { z12.h, z13.h }, z2.h[4]"
+
+  -
+    input:
+      bytes: [ 0x09, 0x58, 0xda, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w10, 2:3, vgx2], { z0.h, z1.h }, z10.h[4]"
+
+  -
+    input:
+      bytes: [ 0x09, 0x58, 0xda, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w10, 2:3, vgx2], { z0.h, z1.h }, z10.h[4]"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x1a, 0xde, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w8, 2:3, vgx2], { z22.h, z23.h }, z14.h[5]"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x1a, 0xde, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w8, 2:3, vgx2], { z22.h, z23.h }, z14.h[5]"
+
+  -
+    input:
+      bytes: [ 0x0a, 0x75, 0xd1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w11, 4:5, vgx2], { z8.h, z9.h }, z1.h[2]"
+
+  -
+    input:
+      bytes: [ 0x0a, 0x75, 0xd1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w11, 4:5, vgx2], { z8.h, z9.h }, z1.h[2]"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x39, 0xdb, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w9, 6:7, vgx2], { z12.h, z13.h }, z11.h[5]"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x39, 0xdb, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w9, 6:7, vgx2], { z12.h, z13.h }, z11.h[5]"
+
+  -
+    input:
+      bytes: [ 0x08, 0x08, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w8, 0:1, vgx2], { z0.h, z1.h }, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x08, 0x08, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w8, 0:1, vgx2], { z0.h, z1.h }, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x49, 0x49, 0xf4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w10, 2:3, vgx2], { z10.h, z11.h }, { z20.h, z21.h }"
+
+  -
+    input:
+      bytes: [ 0x49, 0x49, 0xf4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w10, 2:3, vgx2], { z10.h, z11.h }, { z20.h, z21.h }"
+
+  -
+    input:
+      bytes: [ 0x8b, 0x69, 0xe8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w11, 6:7, vgx2], { z12.h, z13.h }, { z8.h, z9.h }"
+
+  -
+    input:
+      bytes: [ 0x8b, 0x69, 0xe8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w11, 6:7, vgx2], { z12.h, z13.h }, { z8.h, z9.h }"
+
+  -
+    input:
+      bytes: [ 0xcb, 0x6b, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w11, 6:7, vgx2], { z30.h, z31.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0xcb, 0x6b, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w11, 6:7, vgx2], { z30.h, z31.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x0a, 0xf0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w8, 2:3, vgx2], { z16.h, z17.h }, { z16.h, z17.h }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x0a, 0xf0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w8, 2:3, vgx2], { z16.h, z17.h }, { z16.h, z17.h }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x08, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w8, 2:3, vgx2], { z0.h, z1.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x08, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w8, 2:3, vgx2], { z0.h, z1.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x48, 0x4a, 0xf4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w10, 0:1, vgx2], { z18.h, z19.h }, { z20.h, z21.h }"
+
+  -
+    input:
+      bytes: [ 0x48, 0x4a, 0xf4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w10, 0:1, vgx2], { z18.h, z19.h }, { z20.h, z21.h }"
+
+  -
+    input:
+      bytes: [ 0x88, 0x09, 0xe2, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w8, 0:1, vgx2], { z12.h, z13.h }, { z2.h, z3.h }"
+
+  -
+    input:
+      bytes: [ 0x88, 0x09, 0xe2, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w8, 0:1, vgx2], { z12.h, z13.h }, { z2.h, z3.h }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x48, 0xfa, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w10, 2:3, vgx2], { z0.h, z1.h }, { z26.h, z27.h }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x48, 0xfa, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w10, 2:3, vgx2], { z0.h, z1.h }, { z26.h, z27.h }"
+
+  -
+    input:
+      bytes: [ 0xc9, 0x0a, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w8, 2:3, vgx2], { z22.h, z23.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0xc9, 0x0a, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w8, 2:3, vgx2], { z22.h, z23.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x0a, 0x69, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w11, 4:5, vgx2], { z8.h, z9.h }, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x0a, 0x69, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w11, 4:5, vgx2], { z8.h, z9.h }, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x8b, 0x29, 0xea, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w9, 6:7, vgx2], { z12.h, z13.h }, { z10.h, z11.h }"
+
+  -
+    input:
+      bytes: [ 0x8b, 0x29, 0xea, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w9, 6:7, vgx2], { z12.h, z13.h }, { z10.h, z11.h }"
+
+  -
+    input:
+      bytes: [ 0x08, 0x08, 0x70, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w8, 0:1, vgx4], { z0.h - z3.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x08, 0x08, 0x70, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w8, 0:1, vgx4], { z0.h - z3.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x49, 0x49, 0x75, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w10, 2:3, vgx4], { z10.h - z13.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0x49, 0x49, 0x75, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w10, 2:3, vgx4], { z10.h - z13.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0xab, 0x69, 0x78, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w11, 6:7, vgx4], { z13.h - z16.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0xab, 0x69, 0x78, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w11, 6:7, vgx4], { z13.h - z16.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0xeb, 0x6b, 0x7f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w11, 6:7, vgx4], { z31.h, z0.h, z1.h, z2.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0xeb, 0x6b, 0x7f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w11, 6:7, vgx4], { z31.h, z0.h, z1.h, z2.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0x29, 0x0a, 0x70, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w8, 2:3, vgx4], { z17.h - z20.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x29, 0x0a, 0x70, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w8, 2:3, vgx4], { z17.h - z20.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x29, 0x08, 0x7e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w8, 2:3, vgx4], { z1.h - z4.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x29, 0x08, 0x7e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w8, 2:3, vgx4], { z1.h - z4.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x68, 0x4a, 0x74, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w10, 0:1, vgx4], { z19.h - z22.h }, z4.h"
+
+  -
+    input:
+      bytes: [ 0x68, 0x4a, 0x74, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w10, 0:1, vgx4], { z19.h - z22.h }, z4.h"
+
+  -
+    input:
+      bytes: [ 0x88, 0x09, 0x72, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w8, 0:1, vgx4], { z12.h - z15.h }, z2.h"
+
+  -
+    input:
+      bytes: [ 0x88, 0x09, 0x72, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w8, 0:1, vgx4], { z12.h - z15.h }, z2.h"
+
+  -
+    input:
+      bytes: [ 0x29, 0x48, 0x7a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w10, 2:3, vgx4], { z1.h - z4.h }, z10.h"
+
+  -
+    input:
+      bytes: [ 0x29, 0x48, 0x7a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w10, 2:3, vgx4], { z1.h - z4.h }, z10.h"
+
+  -
+    input:
+      bytes: [ 0xc9, 0x0a, 0x7e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w8, 2:3, vgx4], { z22.h - z25.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0xc9, 0x0a, 0x7e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w8, 2:3, vgx4], { z22.h - z25.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x2a, 0x69, 0x71, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w11, 4:5, vgx4], { z9.h - z12.h }, z1.h"
+
+  -
+    input:
+      bytes: [ 0x2a, 0x69, 0x71, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w11, 4:5, vgx4], { z9.h - z12.h }, z1.h"
+
+  -
+    input:
+      bytes: [ 0x8b, 0x29, 0x7b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w9, 6:7, vgx4], { z12.h - z15.h }, z11.h"
+
+  -
+    input:
+      bytes: [ 0x8b, 0x29, 0x7b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w9, 6:7, vgx4], { z12.h - z15.h }, z11.h"
+
+  -
+    input:
+      bytes: [ 0x08, 0x90, 0xd0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w8, 0:1, vgx4], { z0.h - z3.h }, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x08, 0x90, 0xd0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w8, 0:1, vgx4], { z0.h - z3.h }, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x0d, 0xd5, 0xd5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w10, 2:3, vgx4], { z8.h - z11.h }, z5.h[3]"
+
+  -
+    input:
+      bytes: [ 0x0d, 0xd5, 0xd5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w10, 2:3, vgx4], { z8.h - z11.h }, z5.h[3]"
+
+  -
+    input:
+      bytes: [ 0x8f, 0xfd, 0xd8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w11, 6:7, vgx4], { z12.h - z15.h }, z8.h[7]"
+
+  -
+    input:
+      bytes: [ 0x8f, 0xfd, 0xd8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w11, 6:7, vgx4], { z12.h - z15.h }, z8.h[7]"
+
+  -
+    input:
+      bytes: [ 0x8f, 0xff, 0xdf, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w11, 6:7, vgx4], { z28.h - z31.h }, z15.h[7]"
+
+  -
+    input:
+      bytes: [ 0x8f, 0xff, 0xdf, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w11, 6:7, vgx4], { z28.h - z31.h }, z15.h[7]"
+
+  -
+    input:
+      bytes: [ 0x0d, 0x9e, 0xd0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w8, 2:3, vgx4], { z16.h - z19.h }, z0.h[7]"
+
+  -
+    input:
+      bytes: [ 0x0d, 0x9e, 0xd0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w8, 2:3, vgx4], { z16.h - z19.h }, z0.h[7]"
+
+  -
+    input:
+      bytes: [ 0x09, 0x94, 0xde, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w8, 2:3, vgx4], { z0.h - z3.h }, z14.h[2]"
+
+  -
+    input:
+      bytes: [ 0x09, 0x94, 0xde, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w8, 2:3, vgx4], { z0.h - z3.h }, z14.h[2]"
+
+  -
+    input:
+      bytes: [ 0x08, 0xd6, 0xd4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w10, 0:1, vgx4], { z16.h - z19.h }, z4.h[2]"
+
+  -
+    input:
+      bytes: [ 0x08, 0xd6, 0xd4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w10, 0:1, vgx4], { z16.h - z19.h }, z4.h[2]"
+
+  -
+    input:
+      bytes: [ 0x88, 0x99, 0xd2, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w8, 0:1, vgx4], { z12.h - z15.h }, z2.h[4]"
+
+  -
+    input:
+      bytes: [ 0x88, 0x99, 0xd2, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w8, 0:1, vgx4], { z12.h - z15.h }, z2.h[4]"
+
+  -
+    input:
+      bytes: [ 0x09, 0xd8, 0xda, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w10, 2:3, vgx4], { z0.h - z3.h }, z10.h[4]"
+
+  -
+    input:
+      bytes: [ 0x09, 0xd8, 0xda, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w10, 2:3, vgx4], { z0.h - z3.h }, z10.h[4]"
+
+  -
+    input:
+      bytes: [ 0x8d, 0x9a, 0xde, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w8, 2:3, vgx4], { z20.h - z23.h }, z14.h[5]"
+
+  -
+    input:
+      bytes: [ 0x8d, 0x9a, 0xde, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w8, 2:3, vgx4], { z20.h - z23.h }, z14.h[5]"
+
+  -
+    input:
+      bytes: [ 0x0a, 0xf5, 0xd1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w11, 4:5, vgx4], { z8.h - z11.h }, z1.h[2]"
+
+  -
+    input:
+      bytes: [ 0x0a, 0xf5, 0xd1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w11, 4:5, vgx4], { z8.h - z11.h }, z1.h[2]"
+
+  -
+    input:
+      bytes: [ 0x8f, 0xb9, 0xdb, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w9, 6:7, vgx4], { z12.h - z15.h }, z11.h[5]"
+
+  -
+    input:
+      bytes: [ 0x8f, 0xb9, 0xdb, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w9, 6:7, vgx4], { z12.h - z15.h }, z11.h[5]"
+
+  -
+    input:
+      bytes: [ 0x08, 0x08, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w8, 0:1, vgx4], { z0.h - z3.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x08, 0x08, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w8, 0:1, vgx4], { z0.h - z3.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x49, 0xf5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w10, 2:3, vgx4], { z8.h - z11.h }, { z20.h - z23.h }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x49, 0xf5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w10, 2:3, vgx4], { z8.h - z11.h }, { z20.h - z23.h }"
+
+  -
+    input:
+      bytes: [ 0x8b, 0x69, 0xe9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w11, 6:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }"
+
+  -
+    input:
+      bytes: [ 0x8b, 0x69, 0xe9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w11, 6:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }"
+
+  -
+    input:
+      bytes: [ 0x8b, 0x6b, 0xfd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w11, 6:7, vgx4], { z28.h - z31.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x8b, 0x6b, 0xfd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w11, 6:7, vgx4], { z28.h - z31.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x0a, 0xf1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w8, 2:3, vgx4], { z16.h - z19.h }, { z16.h - z19.h }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x0a, 0xf1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w8, 2:3, vgx4], { z16.h - z19.h }, { z16.h - z19.h }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x08, 0xfd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w8, 2:3, vgx4], { z0.h - z3.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x08, 0xfd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w8, 2:3, vgx4], { z0.h - z3.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x08, 0x4a, 0xf5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w10, 0:1, vgx4], { z16.h - z19.h }, { z20.h - z23.h }"
+
+  -
+    input:
+      bytes: [ 0x08, 0x4a, 0xf5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w10, 0:1, vgx4], { z16.h - z19.h }, { z20.h - z23.h }"
+
+  -
+    input:
+      bytes: [ 0x88, 0x09, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w8, 0:1, vgx4], { z12.h - z15.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x88, 0x09, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w8, 0:1, vgx4], { z12.h - z15.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x48, 0xf9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w10, 2:3, vgx4], { z0.h - z3.h }, { z24.h - z27.h }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x48, 0xf9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w10, 2:3, vgx4], { z0.h - z3.h }, { z24.h - z27.h }"
+
+  -
+    input:
+      bytes: [ 0x89, 0x0a, 0xfd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w8, 2:3, vgx4], { z20.h - z23.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x89, 0x0a, 0xfd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w8, 2:3, vgx4], { z20.h - z23.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x0a, 0x69, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w11, 4:5, vgx4], { z8.h - z11.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x0a, 0x69, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w11, 4:5, vgx4], { z8.h - z11.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x8b, 0x29, 0xe9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w9, 6:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }"
+
+  -
+    input:
+      bytes: [ 0x8b, 0x29, 0xe9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl za.s[w9, 6:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }"
diff --git a/tests/MC/AArch64/SME2/smlsll.s.yaml b/tests/MC/AArch64/SME2/smlsll.s.yaml
new file mode 100644
index 000000000..01b900310
--- /dev/null
+++ b/tests/MC/AArch64/SME2/smlsll.s.yaml
@@ -0,0 +1,3360 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x08, 0x04, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w8, 0:3], z0.b, z0.b"
+
+  -
+    input:
+      bytes: [ 0x49, 0x45, 0x25, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w10, 4:7], z10.b, z5.b"
+
+  -
+    input:
+      bytes: [ 0xab, 0x65, 0x28, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w11, 12:15], z13.b, z8.b"
+
+  -
+    input:
+      bytes: [ 0xeb, 0x67, 0x2f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w11, 12:15], z31.b, z15.b"
+
+  -
+    input:
+      bytes: [ 0x29, 0x06, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w8, 4:7], z17.b, z0.b"
+
+  -
+    input:
+      bytes: [ 0x29, 0x04, 0x2e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w8, 4:7], z1.b, z14.b"
+
+  -
+    input:
+      bytes: [ 0x68, 0x46, 0x24, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w10, 0:3], z19.b, z4.b"
+
+  -
+    input:
+      bytes: [ 0x88, 0x05, 0x22, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w8, 0:3], z12.b, z2.b"
+
+  -
+    input:
+      bytes: [ 0x29, 0x44, 0x2a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w10, 4:7], z1.b, z10.b"
+
+  -
+    input:
+      bytes: [ 0xc9, 0x06, 0x2e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w8, 4:7], z22.b, z14.b"
+
+  -
+    input:
+      bytes: [ 0x2a, 0x65, 0x21, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w11, 8:11], z9.b, z1.b"
+
+  -
+    input:
+      bytes: [ 0x8b, 0x25, 0x2b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w9, 12:15], z12.b, z11.b"
+
+  -
+    input:
+      bytes: [ 0x08, 0x00, 0x00, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w8, 0:3], z0.b, z0.b[0]"
+
+  -
+    input:
+      bytes: [ 0x49, 0x55, 0x05, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w10, 4:7], z10.b, z5.b[5]"
+
+  -
+    input:
+      bytes: [ 0xab, 0xed, 0x08, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w11, 12:15], z13.b, z8.b[11]"
+
+  -
+    input:
+      bytes: [ 0xeb, 0xff, 0x0f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w11, 12:15], z31.b, z15.b[15]"
+
+  -
+    input:
+      bytes: [ 0x29, 0x0e, 0x00, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w8, 4:7], z17.b, z0.b[3]"
+
+  -
+    input:
+      bytes: [ 0x29, 0x84, 0x0e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w8, 4:7], z1.b, z14.b[9]"
+
+  -
+    input:
+      bytes: [ 0x68, 0x56, 0x04, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w10, 0:3], z19.b, z4.b[5]"
+
+  -
+    input:
+      bytes: [ 0x88, 0x19, 0x02, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w8, 0:3], z12.b, z2.b[6]"
+
+  -
+    input:
+      bytes: [ 0x29, 0xc8, 0x0a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w10, 4:7], z1.b, z10.b[10]"
+
+  -
+    input:
+      bytes: [ 0xc9, 0x0a, 0x0e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w8, 4:7], z22.b, z14.b[2]"
+
+  -
+    input:
+      bytes: [ 0x2a, 0xf5, 0x01, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w11, 8:11], z9.b, z1.b[13]"
+
+  -
+    input:
+      bytes: [ 0x8b, 0xa9, 0x0b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w9, 12:15], z12.b, z11.b[10]"
+
+  -
+    input:
+      bytes: [ 0x08, 0x04, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w8, 0:3], z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x49, 0x45, 0x65, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w10, 4:7], z10.h, z5.h"
+
+  -
+    input:
+      bytes: [ 0xab, 0x65, 0x68, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w11, 12:15], z13.h, z8.h"
+
+  -
+    input:
+      bytes: [ 0xeb, 0x67, 0x6f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w11, 12:15], z31.h, z15.h"
+
+  -
+    input:
+      bytes: [ 0x29, 0x06, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w8, 4:7], z17.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x29, 0x04, 0x6e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w8, 4:7], z1.h, z14.h"
+
+  -
+    input:
+      bytes: [ 0x68, 0x46, 0x64, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w10, 0:3], z19.h, z4.h"
+
+  -
+    input:
+      bytes: [ 0x88, 0x05, 0x62, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w8, 0:3], z12.h, z2.h"
+
+  -
+    input:
+      bytes: [ 0x29, 0x44, 0x6a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w10, 4:7], z1.h, z10.h"
+
+  -
+    input:
+      bytes: [ 0xc9, 0x06, 0x6e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w8, 4:7], z22.h, z14.h"
+
+  -
+    input:
+      bytes: [ 0x2a, 0x65, 0x61, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w11, 8:11], z9.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0x8b, 0x25, 0x6b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w9, 12:15], z12.h, z11.h"
+
+  -
+    input:
+      bytes: [ 0x08, 0x00, 0x80, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w8, 0:3], z0.h, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x49, 0x45, 0x85, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w10, 4:7], z10.h, z5.h[1]"
+
+  -
+    input:
+      bytes: [ 0xab, 0xed, 0x88, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w11, 12:15], z13.h, z8.h[7]"
+
+  -
+    input:
+      bytes: [ 0xeb, 0xef, 0x8f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w11, 12:15], z31.h, z15.h[7]"
+
+  -
+    input:
+      bytes: [ 0x29, 0x0e, 0x80, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w8, 4:7], z17.h, z0.h[3]"
+
+  -
+    input:
+      bytes: [ 0x29, 0x84, 0x8e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w8, 4:7], z1.h, z14.h[5]"
+
+  -
+    input:
+      bytes: [ 0x68, 0x46, 0x84, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w10, 0:3], z19.h, z4.h[1]"
+
+  -
+    input:
+      bytes: [ 0x88, 0x09, 0x82, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w8, 0:3], z12.h, z2.h[2]"
+
+  -
+    input:
+      bytes: [ 0x29, 0xc8, 0x8a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w10, 4:7], z1.h, z10.h[6]"
+
+  -
+    input:
+      bytes: [ 0xc9, 0x0a, 0x8e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w8, 4:7], z22.h, z14.h[2]"
+
+  -
+    input:
+      bytes: [ 0x2a, 0xe5, 0x81, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w11, 8:11], z9.h, z1.h[5]"
+
+  -
+    input:
+      bytes: [ 0x8b, 0xa9, 0x8b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w9, 12:15], z12.h, z11.h[6]"
+
+  -
+    input:
+      bytes: [ 0x08, 0x00, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w8, 0:3,  vgx2], { z0.b, z1.b }, z0.b"
+
+  -
+    input:
+      bytes: [ 0x08, 0x00, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w8, 0:3,  vgx2], { z0.b, z1.b }, z0.b"
+
+  -
+    input:
+      bytes: [ 0x49, 0x41, 0x25, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w10, 4:7,  vgx2], { z10.b, z11.b }, z5.b"
+
+  -
+    input:
+      bytes: [ 0x49, 0x41, 0x25, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w10, 4:7,  vgx2], { z10.b, z11.b }, z5.b"
+
+  -
+    input:
+      bytes: [ 0xa9, 0x61, 0x28, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w11, 4:7,  vgx2], { z13.b, z14.b }, z8.b"
+
+  -
+    input:
+      bytes: [ 0xa9, 0x61, 0x28, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w11, 4:7,  vgx2], { z13.b, z14.b }, z8.b"
+
+  -
+    input:
+      bytes: [ 0xe9, 0x63, 0x2f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w11, 4:7,  vgx2], { z31.b, z0.b }, z15.b"
+
+  -
+    input:
+      bytes: [ 0xe9, 0x63, 0x2f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w11, 4:7,  vgx2], { z31.b, z0.b }, z15.b"
+
+  -
+    input:
+      bytes: [ 0x29, 0x02, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w8, 4:7,  vgx2], { z17.b, z18.b }, z0.b"
+
+  -
+    input:
+      bytes: [ 0x29, 0x02, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w8, 4:7,  vgx2], { z17.b, z18.b }, z0.b"
+
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0x2e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w8, 4:7,  vgx2], { z1.b, z2.b }, z14.b"
+
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0x2e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w8, 4:7,  vgx2], { z1.b, z2.b }, z14.b"
+
+  -
+    input:
+      bytes: [ 0x68, 0x42, 0x24, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w10, 0:3,  vgx2], { z19.b, z20.b }, z4.b"
+
+  -
+    input:
+      bytes: [ 0x68, 0x42, 0x24, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w10, 0:3,  vgx2], { z19.b, z20.b }, z4.b"
+
+  -
+    input:
+      bytes: [ 0x88, 0x01, 0x22, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w8, 0:3,  vgx2], { z12.b, z13.b }, z2.b"
+
+  -
+    input:
+      bytes: [ 0x88, 0x01, 0x22, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w8, 0:3,  vgx2], { z12.b, z13.b }, z2.b"
+
+  -
+    input:
+      bytes: [ 0x29, 0x40, 0x2a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w10, 4:7,  vgx2], { z1.b, z2.b }, z10.b"
+
+  -
+    input:
+      bytes: [ 0x29, 0x40, 0x2a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w10, 4:7,  vgx2], { z1.b, z2.b }, z10.b"
+
+  -
+    input:
+      bytes: [ 0xc9, 0x02, 0x2e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w8, 4:7,  vgx2], { z22.b, z23.b }, z14.b"
+
+  -
+    input:
+      bytes: [ 0xc9, 0x02, 0x2e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w8, 4:7,  vgx2], { z22.b, z23.b }, z14.b"
+
+  -
+    input:
+      bytes: [ 0x28, 0x61, 0x21, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w11, 0:3,  vgx2], { z9.b, z10.b }, z1.b"
+
+  -
+    input:
+      bytes: [ 0x28, 0x61, 0x21, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w11, 0:3,  vgx2], { z9.b, z10.b }, z1.b"
+
+  -
+    input:
+      bytes: [ 0x89, 0x21, 0x2b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w9, 4:7,  vgx2], { z12.b, z13.b }, z11.b"
+
+  -
+    input:
+      bytes: [ 0x89, 0x21, 0x2b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w9, 4:7,  vgx2], { z12.b, z13.b }, z11.b"
+
+  -
+    input:
+      bytes: [ 0x08, 0x00, 0x10, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w8, 0:3, vgx2], { z0.b, z1.b }, z0.b[0]"
+
+  -
+    input:
+      bytes: [ 0x08, 0x00, 0x10, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w8, 0:3, vgx2], { z0.b, z1.b }, z0.b[0]"
+
+  -
+    input:
+      bytes: [ 0x4d, 0x45, 0x15, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w10, 4:7, vgx2], { z10.b, z11.b }, z5.b[6]"
+
+  -
+    input:
+      bytes: [ 0x4d, 0x45, 0x15, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w10, 4:7, vgx2], { z10.b, z11.b }, z5.b[6]"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x6d, 0x18, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w11, 4:7, vgx2], { z12.b, z13.b }, z8.b[15]"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x6d, 0x18, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w11, 4:7, vgx2], { z12.b, z13.b }, z8.b[15]"
+
+  -
+    input:
+      bytes: [ 0xcf, 0x6f, 0x1f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w11, 4:7, vgx2], { z30.b, z31.b }, z15.b[15]"
+
+  -
+    input:
+      bytes: [ 0xcf, 0x6f, 0x1f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w11, 4:7, vgx2], { z30.b, z31.b }, z15.b[15]"
+
+  -
+    input:
+      bytes: [ 0x0d, 0x0e, 0x10, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w8, 4:7, vgx2], { z16.b, z17.b }, z0.b[14]"
+
+  -
+    input:
+      bytes: [ 0x0d, 0x0e, 0x10, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w8, 4:7, vgx2], { z16.b, z17.b }, z0.b[14]"
+
+  -
+    input:
+      bytes: [ 0x09, 0x04, 0x1e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w8, 4:7, vgx2], { z0.b, z1.b }, z14.b[4]"
+
+  -
+    input:
+      bytes: [ 0x09, 0x04, 0x1e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w8, 4:7, vgx2], { z0.b, z1.b }, z14.b[4]"
+
+  -
+    input:
+      bytes: [ 0x48, 0x46, 0x14, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w10, 0:3, vgx2], { z18.b, z19.b }, z4.b[4]"
+
+  -
+    input:
+      bytes: [ 0x48, 0x46, 0x14, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w10, 0:3, vgx2], { z18.b, z19.b }, z4.b[4]"
+
+  -
+    input:
+      bytes: [ 0x88, 0x09, 0x12, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w8, 0:3, vgx2], { z12.b, z13.b }, z2.b[8]"
+
+  -
+    input:
+      bytes: [ 0x88, 0x09, 0x12, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w8, 0:3, vgx2], { z12.b, z13.b }, z2.b[8]"
+
+  -
+    input:
+      bytes: [ 0x09, 0x48, 0x1a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w10, 4:7, vgx2], { z0.b, z1.b }, z10.b[8]"
+
+  -
+    input:
+      bytes: [ 0x09, 0x48, 0x1a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w10, 4:7, vgx2], { z0.b, z1.b }, z10.b[8]"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x0a, 0x1e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w8, 4:7, vgx2], { z22.b, z23.b }, z14.b[10]"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x0a, 0x1e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w8, 4:7, vgx2], { z22.b, z23.b }, z14.b[10]"
+
+  -
+    input:
+      bytes: [ 0x0a, 0x65, 0x11, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w11, 0:3, vgx2], { z8.b, z9.b }, z1.b[5]"
+
+  -
+    input:
+      bytes: [ 0x0a, 0x65, 0x11, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w11, 0:3, vgx2], { z8.b, z9.b }, z1.b[5]"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x29, 0x1b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w9, 4:7, vgx2], { z12.b, z13.b }, z11.b[11]"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x29, 0x1b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w9, 4:7, vgx2], { z12.b, z13.b }, z11.b[11]"
+
+  -
+    input:
+      bytes: [ 0x08, 0x00, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w8, 0:3, vgx2], { z0.b, z1.b }, { z0.b, z1.b }"
+
+  -
+    input:
+      bytes: [ 0x08, 0x00, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w8, 0:3, vgx2], { z0.b, z1.b }, { z0.b, z1.b }"
+
+  -
+    input:
+      bytes: [ 0x49, 0x41, 0xb4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w10, 4:7, vgx2], { z10.b, z11.b }, { z20.b, z21.b }"
+
+  -
+    input:
+      bytes: [ 0x49, 0x41, 0xb4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w10, 4:7, vgx2], { z10.b, z11.b }, { z20.b, z21.b }"
+
+  -
+    input:
+      bytes: [ 0x89, 0x61, 0xa8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w11, 4:7, vgx2], { z12.b, z13.b }, { z8.b, z9.b }"
+
+  -
+    input:
+      bytes: [ 0x89, 0x61, 0xa8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w11, 4:7, vgx2], { z12.b, z13.b }, { z8.b, z9.b }"
+
+  -
+    input:
+      bytes: [ 0xc9, 0x63, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w11, 4:7, vgx2], { z30.b, z31.b }, { z30.b, z31.b }"
+
+  -
+    input:
+      bytes: [ 0xc9, 0x63, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w11, 4:7, vgx2], { z30.b, z31.b }, { z30.b, z31.b }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x02, 0xb0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w8, 4:7, vgx2], { z16.b, z17.b }, { z16.b, z17.b }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x02, 0xb0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w8, 4:7, vgx2], { z16.b, z17.b }, { z16.b, z17.b }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w8, 4:7, vgx2], { z0.b, z1.b }, { z30.b, z31.b }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w8, 4:7, vgx2], { z0.b, z1.b }, { z30.b, z31.b }"
+
+  -
+    input:
+      bytes: [ 0x48, 0x42, 0xb4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w10, 0:3, vgx2], { z18.b, z19.b }, { z20.b, z21.b }"
+
+  -
+    input:
+      bytes: [ 0x48, 0x42, 0xb4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w10, 0:3, vgx2], { z18.b, z19.b }, { z20.b, z21.b }"
+
+  -
+    input:
+      bytes: [ 0x88, 0x01, 0xa2, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w8, 0:3, vgx2], { z12.b, z13.b }, { z2.b, z3.b }"
+
+  -
+    input:
+      bytes: [ 0x88, 0x01, 0xa2, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w8, 0:3, vgx2], { z12.b, z13.b }, { z2.b, z3.b }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x40, 0xba, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w10, 4:7, vgx2], { z0.b, z1.b }, { z26.b, z27.b }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x40, 0xba, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w10, 4:7, vgx2], { z0.b, z1.b }, { z26.b, z27.b }"
+
+  -
+    input:
+      bytes: [ 0xc9, 0x02, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w8, 4:7, vgx2], { z22.b, z23.b }, { z30.b, z31.b }"
+
+  -
+    input:
+      bytes: [ 0xc9, 0x02, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w8, 4:7, vgx2], { z22.b, z23.b }, { z30.b, z31.b }"
+
+  -
+    input:
+      bytes: [ 0x08, 0x61, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w11, 0:3, vgx2], { z8.b, z9.b }, { z0.b, z1.b }"
+
+  -
+    input:
+      bytes: [ 0x08, 0x61, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w11, 0:3, vgx2], { z8.b, z9.b }, { z0.b, z1.b }"
+
+  -
+    input:
+      bytes: [ 0x89, 0x21, 0xaa, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w9, 4:7, vgx2], { z12.b, z13.b }, { z10.b, z11.b }"
+
+  -
+    input:
+      bytes: [ 0x89, 0x21, 0xaa, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w9, 4:7, vgx2], { z12.b, z13.b }, { z10.b, z11.b }"
+
+  -
+    input:
+      bytes: [ 0x08, 0x00, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w8, 0:3,  vgx2], { z0.h, z1.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x08, 0x00, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w8, 0:3,  vgx2], { z0.h, z1.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x49, 0x41, 0x65, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w10, 4:7,  vgx2], { z10.h, z11.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0x49, 0x41, 0x65, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w10, 4:7,  vgx2], { z10.h, z11.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0xa9, 0x61, 0x68, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w11, 4:7,  vgx2], { z13.h, z14.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0xa9, 0x61, 0x68, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w11, 4:7,  vgx2], { z13.h, z14.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0xe9, 0x63, 0x6f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w11, 4:7,  vgx2], { z31.h, z0.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0xe9, 0x63, 0x6f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w11, 4:7,  vgx2], { z31.h, z0.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0x29, 0x02, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w8, 4:7,  vgx2], { z17.h, z18.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x29, 0x02, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w8, 4:7,  vgx2], { z17.h, z18.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0x6e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w8, 4:7,  vgx2], { z1.h, z2.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0x6e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w8, 4:7,  vgx2], { z1.h, z2.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x68, 0x42, 0x64, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w10, 0:3,  vgx2], { z19.h, z20.h }, z4.h"
+
+  -
+    input:
+      bytes: [ 0x68, 0x42, 0x64, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w10, 0:3,  vgx2], { z19.h, z20.h }, z4.h"
+
+  -
+    input:
+      bytes: [ 0x88, 0x01, 0x62, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w8, 0:3,  vgx2], { z12.h, z13.h }, z2.h"
+
+  -
+    input:
+      bytes: [ 0x88, 0x01, 0x62, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w8, 0:3,  vgx2], { z12.h, z13.h }, z2.h"
+
+  -
+    input:
+      bytes: [ 0x29, 0x40, 0x6a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w10, 4:7,  vgx2], { z1.h, z2.h }, z10.h"
+
+  -
+    input:
+      bytes: [ 0x29, 0x40, 0x6a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w10, 4:7,  vgx2], { z1.h, z2.h }, z10.h"
+
+  -
+    input:
+      bytes: [ 0xc9, 0x02, 0x6e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w8, 4:7,  vgx2], { z22.h, z23.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0xc9, 0x02, 0x6e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w8, 4:7,  vgx2], { z22.h, z23.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x28, 0x61, 0x61, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w11, 0:3,  vgx2], { z9.h, z10.h }, z1.h"
+
+  -
+    input:
+      bytes: [ 0x28, 0x61, 0x61, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w11, 0:3,  vgx2], { z9.h, z10.h }, z1.h"
+
+  -
+    input:
+      bytes: [ 0x89, 0x21, 0x6b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w9, 4:7,  vgx2], { z12.h, z13.h }, z11.h"
+
+  -
+    input:
+      bytes: [ 0x89, 0x21, 0x6b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w9, 4:7,  vgx2], { z12.h, z13.h }, z11.h"
+
+  -
+    input:
+      bytes: [ 0x08, 0x00, 0x90, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w8, 0:3, vgx2], { z0.h, z1.h }, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x08, 0x00, 0x90, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w8, 0:3, vgx2], { z0.h, z1.h }, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x4d, 0x45, 0x95, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w10, 4:7, vgx2], { z10.h, z11.h }, z5.h[6]"
+
+  -
+    input:
+      bytes: [ 0x4d, 0x45, 0x95, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w10, 4:7, vgx2], { z10.h, z11.h }, z5.h[6]"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x65, 0x98, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w11, 4:7, vgx2], { z12.h, z13.h }, z8.h[7]"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x65, 0x98, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w11, 4:7, vgx2], { z12.h, z13.h }, z8.h[7]"
+
+  -
+    input:
+      bytes: [ 0xcf, 0x67, 0x9f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w11, 4:7, vgx2], { z30.h, z31.h }, z15.h[7]"
+
+  -
+    input:
+      bytes: [ 0xcf, 0x67, 0x9f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w11, 4:7, vgx2], { z30.h, z31.h }, z15.h[7]"
+
+  -
+    input:
+      bytes: [ 0x0d, 0x06, 0x90, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w8, 4:7, vgx2], { z16.h, z17.h }, z0.h[6]"
+
+  -
+    input:
+      bytes: [ 0x0d, 0x06, 0x90, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w8, 4:7, vgx2], { z16.h, z17.h }, z0.h[6]"
+
+  -
+    input:
+      bytes: [ 0x09, 0x04, 0x9e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w8, 4:7, vgx2], { z0.h, z1.h }, z14.h[4]"
+
+  -
+    input:
+      bytes: [ 0x09, 0x04, 0x9e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w8, 4:7, vgx2], { z0.h, z1.h }, z14.h[4]"
+
+  -
+    input:
+      bytes: [ 0x48, 0x46, 0x94, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w10, 0:3, vgx2], { z18.h, z19.h }, z4.h[4]"
+
+  -
+    input:
+      bytes: [ 0x48, 0x46, 0x94, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w10, 0:3, vgx2], { z18.h, z19.h }, z4.h[4]"
+
+  -
+    input:
+      bytes: [ 0x88, 0x01, 0x92, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w8, 0:3, vgx2], { z12.h, z13.h }, z2.h[0]"
+
+  -
+    input:
+      bytes: [ 0x88, 0x01, 0x92, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w8, 0:3, vgx2], { z12.h, z13.h }, z2.h[0]"
+
+  -
+    input:
+      bytes: [ 0x09, 0x40, 0x9a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w10, 4:7, vgx2], { z0.h, z1.h }, z10.h[0]"
+
+  -
+    input:
+      bytes: [ 0x09, 0x40, 0x9a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w10, 4:7, vgx2], { z0.h, z1.h }, z10.h[0]"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x02, 0x9e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w8, 4:7, vgx2], { z22.h, z23.h }, z14.h[2]"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x02, 0x9e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w8, 4:7, vgx2], { z22.h, z23.h }, z14.h[2]"
+
+  -
+    input:
+      bytes: [ 0x0a, 0x65, 0x91, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w11, 0:3, vgx2], { z8.h, z9.h }, z1.h[5]"
+
+  -
+    input:
+      bytes: [ 0x0a, 0x65, 0x91, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w11, 0:3, vgx2], { z8.h, z9.h }, z1.h[5]"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x21, 0x9b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w9, 4:7, vgx2], { z12.h, z13.h }, z11.h[3]"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x21, 0x9b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w9, 4:7, vgx2], { z12.h, z13.h }, z11.h[3]"
+
+  -
+    input:
+      bytes: [ 0x08, 0x00, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w8, 0:3, vgx2], { z0.h, z1.h }, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x08, 0x00, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w8, 0:3, vgx2], { z0.h, z1.h }, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x49, 0x41, 0xf4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w10, 4:7, vgx2], { z10.h, z11.h }, { z20.h, z21.h }"
+
+  -
+    input:
+      bytes: [ 0x49, 0x41, 0xf4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w10, 4:7, vgx2], { z10.h, z11.h }, { z20.h, z21.h }"
+
+  -
+    input:
+      bytes: [ 0x89, 0x61, 0xe8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w11, 4:7, vgx2], { z12.h, z13.h }, { z8.h, z9.h }"
+
+  -
+    input:
+      bytes: [ 0x89, 0x61, 0xe8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w11, 4:7, vgx2], { z12.h, z13.h }, { z8.h, z9.h }"
+
+  -
+    input:
+      bytes: [ 0xc9, 0x63, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w11, 4:7, vgx2], { z30.h, z31.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0xc9, 0x63, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w11, 4:7, vgx2], { z30.h, z31.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x02, 0xf0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w8, 4:7, vgx2], { z16.h, z17.h }, { z16.h, z17.h }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x02, 0xf0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w8, 4:7, vgx2], { z16.h, z17.h }, { z16.h, z17.h }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w8, 4:7, vgx2], { z0.h, z1.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w8, 4:7, vgx2], { z0.h, z1.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x48, 0x42, 0xf4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w10, 0:3, vgx2], { z18.h, z19.h }, { z20.h, z21.h }"
+
+  -
+    input:
+      bytes: [ 0x48, 0x42, 0xf4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w10, 0:3, vgx2], { z18.h, z19.h }, { z20.h, z21.h }"
+
+  -
+    input:
+      bytes: [ 0x88, 0x01, 0xe2, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w8, 0:3, vgx2], { z12.h, z13.h }, { z2.h, z3.h }"
+
+  -
+    input:
+      bytes: [ 0x88, 0x01, 0xe2, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w8, 0:3, vgx2], { z12.h, z13.h }, { z2.h, z3.h }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x40, 0xfa, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w10, 4:7, vgx2], { z0.h, z1.h }, { z26.h, z27.h }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x40, 0xfa, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w10, 4:7, vgx2], { z0.h, z1.h }, { z26.h, z27.h }"
+
+  -
+    input:
+      bytes: [ 0xc9, 0x02, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w8, 4:7, vgx2], { z22.h, z23.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0xc9, 0x02, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w8, 4:7, vgx2], { z22.h, z23.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x08, 0x61, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w11, 0:3, vgx2], { z8.h, z9.h }, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x08, 0x61, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w11, 0:3, vgx2], { z8.h, z9.h }, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x89, 0x21, 0xea, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w9, 4:7, vgx2], { z12.h, z13.h }, { z10.h, z11.h }"
+
+  -
+    input:
+      bytes: [ 0x89, 0x21, 0xea, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w9, 4:7, vgx2], { z12.h, z13.h }, { z10.h, z11.h }"
+
+  -
+    input:
+      bytes: [ 0x08, 0x00, 0x30, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w8, 0:3,  vgx4], { z0.b - z3.b }, z0.b"
+
+  -
+    input:
+      bytes: [ 0x08, 0x00, 0x30, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w8, 0:3,  vgx4], { z0.b - z3.b }, z0.b"
+
+  -
+    input:
+      bytes: [ 0x49, 0x41, 0x35, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w10, 4:7,  vgx4], { z10.b - z13.b }, z5.b"
+
+  -
+    input:
+      bytes: [ 0x49, 0x41, 0x35, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w10, 4:7,  vgx4], { z10.b - z13.b }, z5.b"
+
+  -
+    input:
+      bytes: [ 0xa9, 0x61, 0x38, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w11, 4:7,  vgx4], { z13.b - z16.b }, z8.b"
+
+  -
+    input:
+      bytes: [ 0xa9, 0x61, 0x38, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w11, 4:7,  vgx4], { z13.b - z16.b }, z8.b"
+
+  -
+    input:
+      bytes: [ 0xe9, 0x63, 0x3f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w11, 4:7,  vgx4], { z31.b, z0.b, z1.b, z2.b }, z15.b"
+
+  -
+    input:
+      bytes: [ 0xe9, 0x63, 0x3f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w11, 4:7,  vgx4], { z31.b, z0.b, z1.b, z2.b }, z15.b"
+
+  -
+    input:
+      bytes: [ 0x29, 0x02, 0x30, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w8, 4:7,  vgx4], { z17.b - z20.b }, z0.b"
+
+  -
+    input:
+      bytes: [ 0x29, 0x02, 0x30, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w8, 4:7,  vgx4], { z17.b - z20.b }, z0.b"
+
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0x3e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w8, 4:7,  vgx4], { z1.b - z4.b }, z14.b"
+
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0x3e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w8, 4:7,  vgx4], { z1.b - z4.b }, z14.b"
+
+  -
+    input:
+      bytes: [ 0x68, 0x42, 0x34, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w10, 0:3,  vgx4], { z19.b - z22.b }, z4.b"
+
+  -
+    input:
+      bytes: [ 0x68, 0x42, 0x34, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w10, 0:3,  vgx4], { z19.b - z22.b }, z4.b"
+
+  -
+    input:
+      bytes: [ 0x88, 0x01, 0x32, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w8, 0:3,  vgx4], { z12.b - z15.b }, z2.b"
+
+  -
+    input:
+      bytes: [ 0x88, 0x01, 0x32, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w8, 0:3,  vgx4], { z12.b - z15.b }, z2.b"
+
+  -
+    input:
+      bytes: [ 0x29, 0x40, 0x3a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w10, 4:7,  vgx4], { z1.b - z4.b }, z10.b"
+
+  -
+    input:
+      bytes: [ 0x29, 0x40, 0x3a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w10, 4:7,  vgx4], { z1.b - z4.b }, z10.b"
+
+  -
+    input:
+      bytes: [ 0xc9, 0x02, 0x3e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w8, 4:7,  vgx4], { z22.b - z25.b }, z14.b"
+
+  -
+    input:
+      bytes: [ 0xc9, 0x02, 0x3e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w8, 4:7,  vgx4], { z22.b - z25.b }, z14.b"
+
+  -
+    input:
+      bytes: [ 0x28, 0x61, 0x31, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w11, 0:3,  vgx4], { z9.b - z12.b }, z1.b"
+
+  -
+    input:
+      bytes: [ 0x28, 0x61, 0x31, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w11, 0:3,  vgx4], { z9.b - z12.b }, z1.b"
+
+  -
+    input:
+      bytes: [ 0x89, 0x21, 0x3b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w9, 4:7,  vgx4], { z12.b - z15.b }, z11.b"
+
+  -
+    input:
+      bytes: [ 0x89, 0x21, 0x3b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w9, 4:7,  vgx4], { z12.b - z15.b }, z11.b"
+
+  -
+    input:
+      bytes: [ 0x08, 0x80, 0x10, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w8, 0:3, vgx4], { z0.b - z3.b }, z0.b[0]"
+
+  -
+    input:
+      bytes: [ 0x08, 0x80, 0x10, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w8, 0:3, vgx4], { z0.b - z3.b }, z0.b[0]"
+
+  -
+    input:
+      bytes: [ 0x0d, 0xc5, 0x15, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w10, 4:7, vgx4], { z8.b - z11.b }, z5.b[6]"
+
+  -
+    input:
+      bytes: [ 0x0d, 0xc5, 0x15, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w10, 4:7, vgx4], { z8.b - z11.b }, z5.b[6]"
+
+  -
+    input:
+      bytes: [ 0x8f, 0xed, 0x18, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w11, 4:7, vgx4], { z12.b - z15.b }, z8.b[15]"
+
+  -
+    input:
+      bytes: [ 0x8f, 0xed, 0x18, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w11, 4:7, vgx4], { z12.b - z15.b }, z8.b[15]"
+
+  -
+    input:
+      bytes: [ 0x8f, 0xef, 0x1f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w11, 4:7, vgx4], { z28.b - z31.b }, z15.b[15]"
+
+  -
+    input:
+      bytes: [ 0x8f, 0xef, 0x1f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w11, 4:7, vgx4], { z28.b - z31.b }, z15.b[15]"
+
+  -
+    input:
+      bytes: [ 0x0d, 0x8e, 0x10, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w8, 4:7, vgx4], { z16.b - z19.b }, z0.b[14]"
+
+  -
+    input:
+      bytes: [ 0x0d, 0x8e, 0x10, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w8, 4:7, vgx4], { z16.b - z19.b }, z0.b[14]"
+
+  -
+    input:
+      bytes: [ 0x09, 0x84, 0x1e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w8, 4:7, vgx4], { z0.b - z3.b }, z14.b[4]"
+
+  -
+    input:
+      bytes: [ 0x09, 0x84, 0x1e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w8, 4:7, vgx4], { z0.b - z3.b }, z14.b[4]"
+
+  -
+    input:
+      bytes: [ 0x08, 0xc6, 0x14, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w10, 0:3, vgx4], { z16.b - z19.b }, z4.b[4]"
+
+  -
+    input:
+      bytes: [ 0x08, 0xc6, 0x14, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w10, 0:3, vgx4], { z16.b - z19.b }, z4.b[4]"
+
+  -
+    input:
+      bytes: [ 0x88, 0x89, 0x12, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w8, 0:3, vgx4], { z12.b - z15.b }, z2.b[8]"
+
+  -
+    input:
+      bytes: [ 0x88, 0x89, 0x12, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w8, 0:3, vgx4], { z12.b - z15.b }, z2.b[8]"
+
+  -
+    input:
+      bytes: [ 0x09, 0xc8, 0x1a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w10, 4:7, vgx4], { z0.b - z3.b }, z10.b[8]"
+
+  -
+    input:
+      bytes: [ 0x09, 0xc8, 0x1a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w10, 4:7, vgx4], { z0.b - z3.b }, z10.b[8]"
+
+  -
+    input:
+      bytes: [ 0x8d, 0x8a, 0x1e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w8, 4:7, vgx4], { z20.b - z23.b }, z14.b[10]"
+
+  -
+    input:
+      bytes: [ 0x8d, 0x8a, 0x1e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w8, 4:7, vgx4], { z20.b - z23.b }, z14.b[10]"
+
+  -
+    input:
+      bytes: [ 0x0a, 0xe5, 0x11, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w11, 0:3, vgx4], { z8.b - z11.b }, z1.b[5]"
+
+  -
+    input:
+      bytes: [ 0x0a, 0xe5, 0x11, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w11, 0:3, vgx4], { z8.b - z11.b }, z1.b[5]"
+
+  -
+    input:
+      bytes: [ 0x8f, 0xa9, 0x1b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w9, 4:7, vgx4], { z12.b - z15.b }, z11.b[11]"
+
+  -
+    input:
+      bytes: [ 0x8f, 0xa9, 0x1b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w9, 4:7, vgx4], { z12.b - z15.b }, z11.b[11]"
+
+  -
+    input:
+      bytes: [ 0x08, 0x00, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w8, 0:3, vgx4], { z0.b - z3.b }, { z0.b - z3.b }"
+
+  -
+    input:
+      bytes: [ 0x08, 0x00, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w8, 0:3, vgx4], { z0.b - z3.b }, { z0.b - z3.b }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x41, 0xb5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w10, 4:7, vgx4], { z8.b - z11.b }, { z20.b - z23.b }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x41, 0xb5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w10, 4:7, vgx4], { z8.b - z11.b }, { z20.b - z23.b }"
+
+  -
+    input:
+      bytes: [ 0x89, 0x61, 0xa9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w11, 4:7, vgx4], { z12.b - z15.b }, { z8.b - z11.b }"
+
+  -
+    input:
+      bytes: [ 0x89, 0x61, 0xa9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w11, 4:7, vgx4], { z12.b - z15.b }, { z8.b - z11.b }"
+
+  -
+    input:
+      bytes: [ 0x89, 0x63, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w11, 4:7, vgx4], { z28.b - z31.b }, { z28.b - z31.b }"
+
+  -
+    input:
+      bytes: [ 0x89, 0x63, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w11, 4:7, vgx4], { z28.b - z31.b }, { z28.b - z31.b }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x02, 0xb1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w8, 4:7, vgx4], { z16.b - z19.b }, { z16.b - z19.b }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x02, 0xb1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w8, 4:7, vgx4], { z16.b - z19.b }, { z16.b - z19.b }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w8, 4:7, vgx4], { z0.b - z3.b }, { z28.b - z31.b }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w8, 4:7, vgx4], { z0.b - z3.b }, { z28.b - z31.b }"
+
+  -
+    input:
+      bytes: [ 0x08, 0x42, 0xb5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w10, 0:3, vgx4], { z16.b - z19.b }, { z20.b - z23.b }"
+
+  -
+    input:
+      bytes: [ 0x08, 0x42, 0xb5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w10, 0:3, vgx4], { z16.b - z19.b }, { z20.b - z23.b }"
+
+  -
+    input:
+      bytes: [ 0x88, 0x01, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w8, 0:3, vgx4], { z12.b - z15.b }, { z0.b - z3.b }"
+
+  -
+    input:
+      bytes: [ 0x88, 0x01, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w8, 0:3, vgx4], { z12.b - z15.b }, { z0.b - z3.b }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x40, 0xb9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w10, 4:7, vgx4], { z0.b - z3.b }, { z24.b - z27.b }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x40, 0xb9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w10, 4:7, vgx4], { z0.b - z3.b }, { z24.b - z27.b }"
+
+  -
+    input:
+      bytes: [ 0x89, 0x02, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w8, 4:7, vgx4], { z20.b - z23.b }, { z28.b - z31.b }"
+
+  -
+    input:
+      bytes: [ 0x89, 0x02, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w8, 4:7, vgx4], { z20.b - z23.b }, { z28.b - z31.b }"
+
+  -
+    input:
+      bytes: [ 0x08, 0x61, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w11, 0:3, vgx4], { z8.b - z11.b }, { z0.b - z3.b }"
+
+  -
+    input:
+      bytes: [ 0x08, 0x61, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w11, 0:3, vgx4], { z8.b - z11.b }, { z0.b - z3.b }"
+
+  -
+    input:
+      bytes: [ 0x89, 0x21, 0xa9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w9, 4:7, vgx4], { z12.b - z15.b }, { z8.b - z11.b }"
+
+  -
+    input:
+      bytes: [ 0x89, 0x21, 0xa9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.s[w9, 4:7, vgx4], { z12.b - z15.b }, { z8.b - z11.b }"
+
+  -
+    input:
+      bytes: [ 0x08, 0x00, 0x70, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w8, 0:3,  vgx4], { z0.h - z3.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x08, 0x00, 0x70, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w8, 0:3,  vgx4], { z0.h - z3.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x49, 0x41, 0x75, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w10, 4:7,  vgx4], { z10.h - z13.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0x49, 0x41, 0x75, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w10, 4:7,  vgx4], { z10.h - z13.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0xa9, 0x61, 0x78, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w11, 4:7,  vgx4], { z13.h - z16.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0xa9, 0x61, 0x78, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w11, 4:7,  vgx4], { z13.h - z16.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0xe9, 0x63, 0x7f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w11, 4:7,  vgx4], { z31.h, z0.h, z1.h, z2.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0xe9, 0x63, 0x7f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w11, 4:7,  vgx4], { z31.h, z0.h, z1.h, z2.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0x29, 0x02, 0x70, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w8, 4:7,  vgx4], { z17.h - z20.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x29, 0x02, 0x70, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w8, 4:7,  vgx4], { z17.h - z20.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0x7e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w8, 4:7,  vgx4], { z1.h - z4.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0x7e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w8, 4:7,  vgx4], { z1.h - z4.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x68, 0x42, 0x74, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w10, 0:3,  vgx4], { z19.h - z22.h }, z4.h"
+
+  -
+    input:
+      bytes: [ 0x68, 0x42, 0x74, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w10, 0:3,  vgx4], { z19.h - z22.h }, z4.h"
+
+  -
+    input:
+      bytes: [ 0x88, 0x01, 0x72, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w8, 0:3,  vgx4], { z12.h - z15.h }, z2.h"
+
+  -
+    input:
+      bytes: [ 0x88, 0x01, 0x72, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w8, 0:3,  vgx4], { z12.h - z15.h }, z2.h"
+
+  -
+    input:
+      bytes: [ 0x29, 0x40, 0x7a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w10, 4:7,  vgx4], { z1.h - z4.h }, z10.h"
+
+  -
+    input:
+      bytes: [ 0x29, 0x40, 0x7a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w10, 4:7,  vgx4], { z1.h - z4.h }, z10.h"
+
+  -
+    input:
+      bytes: [ 0xc9, 0x02, 0x7e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w8, 4:7,  vgx4], { z22.h - z25.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0xc9, 0x02, 0x7e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w8, 4:7,  vgx4], { z22.h - z25.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x28, 0x61, 0x71, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w11, 0:3,  vgx4], { z9.h - z12.h }, z1.h"
+
+  -
+    input:
+      bytes: [ 0x28, 0x61, 0x71, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w11, 0:3,  vgx4], { z9.h - z12.h }, z1.h"
+
+  -
+    input:
+      bytes: [ 0x89, 0x21, 0x7b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w9, 4:7,  vgx4], { z12.h - z15.h }, z11.h"
+
+  -
+    input:
+      bytes: [ 0x89, 0x21, 0x7b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w9, 4:7,  vgx4], { z12.h - z15.h }, z11.h"
+
+  -
+    input:
+      bytes: [ 0x08, 0x80, 0x90, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w8, 0:3, vgx4], { z0.h - z3.h }, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x08, 0x80, 0x90, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w8, 0:3, vgx4], { z0.h - z3.h }, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x0d, 0xc5, 0x95, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w10, 4:7, vgx4], { z8.h - z11.h }, z5.h[6]"
+
+  -
+    input:
+      bytes: [ 0x0d, 0xc5, 0x95, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w10, 4:7, vgx4], { z8.h - z11.h }, z5.h[6]"
+
+  -
+    input:
+      bytes: [ 0x8f, 0xe5, 0x98, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w11, 4:7, vgx4], { z12.h - z15.h }, z8.h[7]"
+
+  -
+    input:
+      bytes: [ 0x8f, 0xe5, 0x98, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w11, 4:7, vgx4], { z12.h - z15.h }, z8.h[7]"
+
+  -
+    input:
+      bytes: [ 0x8f, 0xe7, 0x9f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w11, 4:7, vgx4], { z28.h - z31.h }, z15.h[7]"
+
+  -
+    input:
+      bytes: [ 0x8f, 0xe7, 0x9f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w11, 4:7, vgx4], { z28.h - z31.h }, z15.h[7]"
+
+  -
+    input:
+      bytes: [ 0x0d, 0x86, 0x90, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w8, 4:7, vgx4], { z16.h - z19.h }, z0.h[6]"
+
+  -
+    input:
+      bytes: [ 0x0d, 0x86, 0x90, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w8, 4:7, vgx4], { z16.h - z19.h }, z0.h[6]"
+
+  -
+    input:
+      bytes: [ 0x09, 0x84, 0x9e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w8, 4:7, vgx4], { z0.h - z3.h }, z14.h[4]"
+
+  -
+    input:
+      bytes: [ 0x09, 0x84, 0x9e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w8, 4:7, vgx4], { z0.h - z3.h }, z14.h[4]"
+
+  -
+    input:
+      bytes: [ 0x08, 0xc6, 0x94, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w10, 0:3, vgx4], { z16.h - z19.h }, z4.h[4]"
+
+  -
+    input:
+      bytes: [ 0x08, 0xc6, 0x94, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w10, 0:3, vgx4], { z16.h - z19.h }, z4.h[4]"
+
+  -
+    input:
+      bytes: [ 0x88, 0x81, 0x92, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w8, 0:3, vgx4], { z12.h - z15.h }, z2.h[0]"
+
+  -
+    input:
+      bytes: [ 0x88, 0x81, 0x92, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w8, 0:3, vgx4], { z12.h - z15.h }, z2.h[0]"
+
+  -
+    input:
+      bytes: [ 0x09, 0xc0, 0x9a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w10, 4:7, vgx4], { z0.h - z3.h }, z10.h[0]"
+
+  -
+    input:
+      bytes: [ 0x09, 0xc0, 0x9a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w10, 4:7, vgx4], { z0.h - z3.h }, z10.h[0]"
+
+  -
+    input:
+      bytes: [ 0x8d, 0x82, 0x9e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w8, 4:7, vgx4], { z20.h - z23.h }, z14.h[2]"
+
+  -
+    input:
+      bytes: [ 0x8d, 0x82, 0x9e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w8, 4:7, vgx4], { z20.h - z23.h }, z14.h[2]"
+
+  -
+    input:
+      bytes: [ 0x0a, 0xe5, 0x91, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w11, 0:3, vgx4], { z8.h - z11.h }, z1.h[5]"
+
+  -
+    input:
+      bytes: [ 0x0a, 0xe5, 0x91, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w11, 0:3, vgx4], { z8.h - z11.h }, z1.h[5]"
+
+  -
+    input:
+      bytes: [ 0x8f, 0xa1, 0x9b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w9, 4:7, vgx4], { z12.h - z15.h }, z11.h[3]"
+
+  -
+    input:
+      bytes: [ 0x8f, 0xa1, 0x9b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w9, 4:7, vgx4], { z12.h - z15.h }, z11.h[3]"
+
+  -
+    input:
+      bytes: [ 0x08, 0x00, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w8, 0:3, vgx4], { z0.h - z3.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x08, 0x00, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w8, 0:3, vgx4], { z0.h - z3.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x41, 0xf5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w10, 4:7, vgx4], { z8.h - z11.h }, { z20.h - z23.h }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x41, 0xf5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w10, 4:7, vgx4], { z8.h - z11.h }, { z20.h - z23.h }"
+
+  -
+    input:
+      bytes: [ 0x89, 0x61, 0xe9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w11, 4:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }"
+
+  -
+    input:
+      bytes: [ 0x89, 0x61, 0xe9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w11, 4:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }"
+
+  -
+    input:
+      bytes: [ 0x89, 0x63, 0xfd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w11, 4:7, vgx4], { z28.h - z31.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x89, 0x63, 0xfd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w11, 4:7, vgx4], { z28.h - z31.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x02, 0xf1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w8, 4:7, vgx4], { z16.h - z19.h }, { z16.h - z19.h }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x02, 0xf1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w8, 4:7, vgx4], { z16.h - z19.h }, { z16.h - z19.h }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0xfd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w8, 4:7, vgx4], { z0.h - z3.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0xfd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w8, 4:7, vgx4], { z0.h - z3.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x08, 0x42, 0xf5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w10, 0:3, vgx4], { z16.h - z19.h }, { z20.h - z23.h }"
+
+  -
+    input:
+      bytes: [ 0x08, 0x42, 0xf5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w10, 0:3, vgx4], { z16.h - z19.h }, { z20.h - z23.h }"
+
+  -
+    input:
+      bytes: [ 0x88, 0x01, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w8, 0:3, vgx4], { z12.h - z15.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x88, 0x01, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w8, 0:3, vgx4], { z12.h - z15.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x40, 0xf9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w10, 4:7, vgx4], { z0.h - z3.h }, { z24.h - z27.h }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x40, 0xf9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w10, 4:7, vgx4], { z0.h - z3.h }, { z24.h - z27.h }"
+
+  -
+    input:
+      bytes: [ 0x89, 0x02, 0xfd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w8, 4:7, vgx4], { z20.h - z23.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x89, 0x02, 0xfd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w8, 4:7, vgx4], { z20.h - z23.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x08, 0x61, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w11, 0:3, vgx4], { z8.h - z11.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x08, 0x61, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w11, 0:3, vgx4], { z8.h - z11.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x89, 0x21, 0xe9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w9, 4:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }"
+
+  -
+    input:
+      bytes: [ 0x89, 0x21, 0xe9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsll za.d[w9, 4:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }"
diff --git a/tests/MC/AArch64/SME2/smopa.s.yaml b/tests/MC/AArch64/SME2/smopa.s.yaml
new file mode 100644
index 000000000..692bc9523
--- /dev/null
+++ b/tests/MC/AArch64/SME2/smopa.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x08, 0x00, 0x80, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smopa za0.s, p0/m, p0/m, z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x49, 0x55, 0x95, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smopa za1.s, p5/m, p2/m, z10.h, z21.h"
+
+  -
+    input:
+      bytes: [ 0xab, 0xed, 0x88, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smopa za3.s, p3/m, p7/m, z13.h, z8.h"
+
+  -
+    input:
+      bytes: [ 0xeb, 0xff, 0x9f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smopa za3.s, p7/m, p7/m, z31.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x29, 0x0e, 0x90, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smopa za1.s, p3/m, p0/m, z17.h, z16.h"
+
+  -
+    input:
+      bytes: [ 0x29, 0x84, 0x9e, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smopa za1.s, p1/m, p4/m, z1.h, z30.h"
+
+  -
+    input:
+      bytes: [ 0x68, 0x56, 0x94, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smopa za0.s, p5/m, p2/m, z19.h, z20.h"
+
+  -
+    input:
+      bytes: [ 0x88, 0x19, 0x82, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smopa za0.s, p6/m, p0/m, z12.h, z2.h"
+
+  -
+    input:
+      bytes: [ 0x29, 0xc8, 0x9a, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smopa za1.s, p2/m, p6/m, z1.h, z26.h"
+
+  -
+    input:
+      bytes: [ 0xc9, 0x0a, 0x9e, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smopa za1.s, p2/m, p0/m, z22.h, z30.h"
+
+  -
+    input:
+      bytes: [ 0x2a, 0xf5, 0x81, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smopa za2.s, p5/m, p7/m, z9.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0x8b, 0xa9, 0x8b, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smopa za3.s, p2/m, p5/m, z12.h, z11.h"
diff --git a/tests/MC/AArch64/SME2/smops.s.yaml b/tests/MC/AArch64/SME2/smops.s.yaml
new file mode 100644
index 000000000..7f649bfbf
--- /dev/null
+++ b/tests/MC/AArch64/SME2/smops.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x18, 0x00, 0x80, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smops za0.s, p0/m, p0/m, z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x59, 0x55, 0x95, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smops za1.s, p5/m, p2/m, z10.h, z21.h"
+
+  -
+    input:
+      bytes: [ 0xbb, 0xed, 0x88, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smops za3.s, p3/m, p7/m, z13.h, z8.h"
+
+  -
+    input:
+      bytes: [ 0xfb, 0xff, 0x9f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smops za3.s, p7/m, p7/m, z31.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x39, 0x0e, 0x90, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smops za1.s, p3/m, p0/m, z17.h, z16.h"
+
+  -
+    input:
+      bytes: [ 0x39, 0x84, 0x9e, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smops za1.s, p1/m, p4/m, z1.h, z30.h"
+
+  -
+    input:
+      bytes: [ 0x78, 0x56, 0x94, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smops za0.s, p5/m, p2/m, z19.h, z20.h"
+
+  -
+    input:
+      bytes: [ 0x98, 0x19, 0x82, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smops za0.s, p6/m, p0/m, z12.h, z2.h"
+
+  -
+    input:
+      bytes: [ 0x39, 0xc8, 0x9a, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smops za1.s, p2/m, p6/m, z1.h, z26.h"
+
+  -
+    input:
+      bytes: [ 0xd9, 0x0a, 0x9e, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smops za1.s, p2/m, p0/m, z22.h, z30.h"
+
+  -
+    input:
+      bytes: [ 0x3a, 0xf5, 0x81, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smops za2.s, p5/m, p7/m, z9.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0x9b, 0xa9, 0x8b, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smops za3.s, p2/m, p5/m, z12.h, z11.h"
diff --git a/tests/MC/AArch64/SME2/sqcvt.s.yaml b/tests/MC/AArch64/SME2/sqcvt.s.yaml
new file mode 100644
index 000000000..f27729306
--- /dev/null
+++ b/tests/MC/AArch64/SME2/sqcvt.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x23, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqcvt z0.h, { z0.s, z1.s }"
+
+  -
+    input:
+      bytes: [ 0x55, 0xe1, 0x23, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqcvt z21.h, { z10.s, z11.s }"
+
+  -
+    input:
+      bytes: [ 0x97, 0xe1, 0x23, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqcvt z23.h, { z12.s, z13.s }"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xe3, 0x23, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqcvt z31.h, { z30.s, z31.s }"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x33, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqcvt z0.b, { z0.s - z3.s }"
+
+  -
+    input:
+      bytes: [ 0x15, 0xe1, 0x33, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqcvt z21.b, { z8.s - z11.s }"
+
+  -
+    input:
+      bytes: [ 0x97, 0xe1, 0x33, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqcvt z23.b, { z12.s - z15.s }"
+
+  -
+    input:
+      bytes: [ 0x9f, 0xe3, 0x33, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqcvt z31.b, { z28.s - z31.s }"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xb3, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqcvt z0.h, { z0.d - z3.d }"
+
+  -
+    input:
+      bytes: [ 0x15, 0xe1, 0xb3, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqcvt z21.h, { z8.d - z11.d }"
+
+  -
+    input:
+      bytes: [ 0x97, 0xe1, 0xb3, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqcvt z23.h, { z12.d - z15.d }"
+
+  -
+    input:
+      bytes: [ 0x9f, 0xe3, 0xb3, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqcvt z31.h, { z28.d - z31.d }"
diff --git a/tests/MC/AArch64/SME2/sqcvtn.s.yaml b/tests/MC/AArch64/SME2/sqcvtn.s.yaml
new file mode 100644
index 000000000..3643e7f2e
--- /dev/null
+++ b/tests/MC/AArch64/SME2/sqcvtn.s.yaml
@@ -0,0 +1,80 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x40, 0xe0, 0x33, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqcvtn z0.b, { z0.s - z3.s }"
+
+  -
+    input:
+      bytes: [ 0x55, 0xe1, 0x33, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqcvtn z21.b, { z8.s - z11.s }"
+
+  -
+    input:
+      bytes: [ 0xd7, 0xe1, 0x33, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqcvtn z23.b, { z12.s - z15.s }"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xe3, 0x33, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqcvtn z31.b, { z28.s - z31.s }"
+
+  -
+    input:
+      bytes: [ 0x40, 0xe0, 0xb3, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqcvtn z0.h, { z0.d - z3.d }"
+
+  -
+    input:
+      bytes: [ 0x55, 0xe1, 0xb3, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqcvtn z21.h, { z8.d - z11.d }"
+
+  -
+    input:
+      bytes: [ 0xd7, 0xe1, 0xb3, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqcvtn z23.h, { z12.d - z15.d }"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xe3, 0xb3, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqcvtn z31.h, { z28.d - z31.d }"
diff --git a/tests/MC/AArch64/SME2/sqcvtu.s.yaml b/tests/MC/AArch64/SME2/sqcvtu.s.yaml
new file mode 100644
index 000000000..f5b6d03d6
--- /dev/null
+++ b/tests/MC/AArch64/SME2/sqcvtu.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x63, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqcvtu z0.h, { z0.s, z1.s }"
+
+  -
+    input:
+      bytes: [ 0x55, 0xe1, 0x63, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqcvtu z21.h, { z10.s, z11.s }"
+
+  -
+    input:
+      bytes: [ 0x97, 0xe1, 0x63, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqcvtu z23.h, { z12.s, z13.s }"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xe3, 0x63, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqcvtu z31.h, { z30.s, z31.s }"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x73, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqcvtu z0.b, { z0.s - z3.s }"
+
+  -
+    input:
+      bytes: [ 0x15, 0xe1, 0x73, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqcvtu z21.b, { z8.s - z11.s }"
+
+  -
+    input:
+      bytes: [ 0x97, 0xe1, 0x73, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqcvtu z23.b, { z12.s - z15.s }"
+
+  -
+    input:
+      bytes: [ 0x9f, 0xe3, 0x73, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqcvtu z31.b, { z28.s - z31.s }"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xf3, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqcvtu z0.h, { z0.d - z3.d }"
+
+  -
+    input:
+      bytes: [ 0x15, 0xe1, 0xf3, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqcvtu z21.h, { z8.d - z11.d }"
+
+  -
+    input:
+      bytes: [ 0x97, 0xe1, 0xf3, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqcvtu z23.h, { z12.d - z15.d }"
+
+  -
+    input:
+      bytes: [ 0x9f, 0xe3, 0xf3, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqcvtu z31.h, { z28.d - z31.d }"
diff --git a/tests/MC/AArch64/SME2/sqcvtun.s.yaml b/tests/MC/AArch64/SME2/sqcvtun.s.yaml
new file mode 100644
index 000000000..0de86e936
--- /dev/null
+++ b/tests/MC/AArch64/SME2/sqcvtun.s.yaml
@@ -0,0 +1,80 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x40, 0xe0, 0x73, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqcvtun z0.b, { z0.s - z3.s }"
+
+  -
+    input:
+      bytes: [ 0x55, 0xe1, 0x73, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqcvtun z21.b, { z8.s - z11.s }"
+
+  -
+    input:
+      bytes: [ 0xd7, 0xe1, 0x73, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqcvtun z23.b, { z12.s - z15.s }"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xe3, 0x73, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqcvtun z31.b, { z28.s - z31.s }"
+
+  -
+    input:
+      bytes: [ 0x40, 0xe0, 0xf3, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqcvtun z0.h, { z0.d - z3.d }"
+
+  -
+    input:
+      bytes: [ 0x55, 0xe1, 0xf3, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqcvtun z21.h, { z8.d - z11.d }"
+
+  -
+    input:
+      bytes: [ 0xd7, 0xe1, 0xf3, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqcvtun z23.h, { z12.d - z15.d }"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xe3, 0xf3, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqcvtun z31.h, { z28.d - z31.d }"
diff --git a/tests/MC/AArch64/SME2/sqdmulh.s.yaml b/tests/MC/AArch64/SME2/sqdmulh.s.yaml
new file mode 100644
index 000000000..a6dc4165e
--- /dev/null
+++ b/tests/MC/AArch64/SME2/sqdmulh.s.yaml
@@ -0,0 +1,640 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xa4, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmulh { z0.h, z1.h }, { z0.h, z1.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x14, 0xa4, 0x65, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmulh { z20.h, z21.h }, { z20.h, z21.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0x16, 0xa4, 0x68, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmulh { z22.h, z23.h }, { z22.h, z23.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0x1e, 0xa4, 0x6f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmulh { z30.h, z31.h }, { z30.h, z31.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0xb4, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmulh { z0.h, z1.h }, { z0.h, z1.h }, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x14, 0xb4, 0x74, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmulh { z20.h, z21.h }, { z20.h, z21.h }, { z20.h, z21.h }"
+
+  -
+    input:
+      bytes: [ 0x16, 0xb4, 0x68, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmulh { z22.h, z23.h }, { z22.h, z23.h }, { z8.h, z9.h }"
+
+  -
+    input:
+      bytes: [ 0x1e, 0xb4, 0x7e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmulh { z30.h, z31.h }, { z30.h, z31.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa4, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmulh { z0.s, z1.s }, { z0.s, z1.s }, z0.s"
+
+  -
+    input:
+      bytes: [ 0x14, 0xa4, 0xa5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmulh { z20.s, z21.s }, { z20.s, z21.s }, z5.s"
+
+  -
+    input:
+      bytes: [ 0x16, 0xa4, 0xa8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmulh { z22.s, z23.s }, { z22.s, z23.s }, z8.s"
+
+  -
+    input:
+      bytes: [ 0x1e, 0xa4, 0xaf, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmulh { z30.s, z31.s }, { z30.s, z31.s }, z15.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0xb4, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmulh { z0.s, z1.s }, { z0.s, z1.s }, { z0.s, z1.s }"
+
+  -
+    input:
+      bytes: [ 0x14, 0xb4, 0xb4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmulh { z20.s, z21.s }, { z20.s, z21.s }, { z20.s, z21.s }"
+
+  -
+    input:
+      bytes: [ 0x16, 0xb4, 0xa8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmulh { z22.s, z23.s }, { z22.s, z23.s }, { z8.s, z9.s }"
+
+  -
+    input:
+      bytes: [ 0x1e, 0xb4, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmulh { z30.s, z31.s }, { z30.s, z31.s }, { z30.s, z31.s }"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa4, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmulh { z0.d, z1.d }, { z0.d, z1.d }, z0.d"
+
+  -
+    input:
+      bytes: [ 0x14, 0xa4, 0xe5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmulh { z20.d, z21.d }, { z20.d, z21.d }, z5.d"
+
+  -
+    input:
+      bytes: [ 0x16, 0xa4, 0xe8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmulh { z22.d, z23.d }, { z22.d, z23.d }, z8.d"
+
+  -
+    input:
+      bytes: [ 0x1e, 0xa4, 0xef, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmulh { z30.d, z31.d }, { z30.d, z31.d }, z15.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0xb4, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmulh { z0.d, z1.d }, { z0.d, z1.d }, { z0.d, z1.d }"
+
+  -
+    input:
+      bytes: [ 0x14, 0xb4, 0xf4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmulh { z20.d, z21.d }, { z20.d, z21.d }, { z20.d, z21.d }"
+
+  -
+    input:
+      bytes: [ 0x16, 0xb4, 0xe8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmulh { z22.d, z23.d }, { z22.d, z23.d }, { z8.d, z9.d }"
+
+  -
+    input:
+      bytes: [ 0x1e, 0xb4, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmulh { z30.d, z31.d }, { z30.d, z31.d }, { z30.d, z31.d }"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa4, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmulh { z0.b, z1.b }, { z0.b, z1.b }, z0.b"
+
+  -
+    input:
+      bytes: [ 0x14, 0xa4, 0x25, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmulh { z20.b, z21.b }, { z20.b, z21.b }, z5.b"
+
+  -
+    input:
+      bytes: [ 0x16, 0xa4, 0x28, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmulh { z22.b, z23.b }, { z22.b, z23.b }, z8.b"
+
+  -
+    input:
+      bytes: [ 0x1e, 0xa4, 0x2f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmulh { z30.b, z31.b }, { z30.b, z31.b }, z15.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0xb4, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmulh { z0.b, z1.b }, { z0.b, z1.b }, { z0.b, z1.b }"
+
+  -
+    input:
+      bytes: [ 0x14, 0xb4, 0x34, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmulh { z20.b, z21.b }, { z20.b, z21.b }, { z20.b, z21.b }"
+
+  -
+    input:
+      bytes: [ 0x16, 0xb4, 0x28, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmulh { z22.b, z23.b }, { z22.b, z23.b }, { z8.b, z9.b }"
+
+  -
+    input:
+      bytes: [ 0x1e, 0xb4, 0x3e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmulh { z30.b, z31.b }, { z30.b, z31.b }, { z30.b, z31.b }"
+
+  -
+    input:
+      bytes: [ 0x00, 0xac, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmulh { z0.h - z3.h }, { z0.h - z3.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x14, 0xac, 0x65, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmulh { z20.h - z23.h }, { z20.h - z23.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0x14, 0xac, 0x68, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmulh { z20.h - z23.h }, { z20.h - z23.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0x1c, 0xac, 0x6f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmulh { z28.h - z31.h }, { z28.h - z31.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0xbc, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmulh { z0.h - z3.h }, { z0.h - z3.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x14, 0xbc, 0x74, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmulh { z20.h - z23.h }, { z20.h - z23.h }, { z20.h - z23.h }"
+
+  -
+    input:
+      bytes: [ 0x14, 0xbc, 0x68, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmulh { z20.h - z23.h }, { z20.h - z23.h }, { z8.h - z11.h }"
+
+  -
+    input:
+      bytes: [ 0x1c, 0xbc, 0x7c, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmulh { z28.h - z31.h }, { z28.h - z31.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x00, 0xac, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmulh { z0.s - z3.s }, { z0.s - z3.s }, z0.s"
+
+  -
+    input:
+      bytes: [ 0x14, 0xac, 0xa5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmulh { z20.s - z23.s }, { z20.s - z23.s }, z5.s"
+
+  -
+    input:
+      bytes: [ 0x14, 0xac, 0xa8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmulh { z20.s - z23.s }, { z20.s - z23.s }, z8.s"
+
+  -
+    input:
+      bytes: [ 0x1c, 0xac, 0xaf, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmulh { z28.s - z31.s }, { z28.s - z31.s }, z15.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0xbc, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmulh { z0.s - z3.s }, { z0.s - z3.s }, { z0.s - z3.s }"
+
+  -
+    input:
+      bytes: [ 0x14, 0xbc, 0xb4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmulh { z20.s - z23.s }, { z20.s - z23.s }, { z20.s - z23.s }"
+
+  -
+    input:
+      bytes: [ 0x14, 0xbc, 0xa8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmulh { z20.s - z23.s }, { z20.s - z23.s }, { z8.s - z11.s }"
+
+  -
+    input:
+      bytes: [ 0x1c, 0xbc, 0xbc, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmulh { z28.s - z31.s }, { z28.s - z31.s }, { z28.s - z31.s }"
+
+  -
+    input:
+      bytes: [ 0x00, 0xac, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmulh { z0.d - z3.d }, { z0.d - z3.d }, z0.d"
+
+  -
+    input:
+      bytes: [ 0x14, 0xac, 0xe5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmulh { z20.d - z23.d }, { z20.d - z23.d }, z5.d"
+
+  -
+    input:
+      bytes: [ 0x14, 0xac, 0xe8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmulh { z20.d - z23.d }, { z20.d - z23.d }, z8.d"
+
+  -
+    input:
+      bytes: [ 0x1c, 0xac, 0xef, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmulh { z28.d - z31.d }, { z28.d - z31.d }, z15.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0xbc, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmulh { z0.d - z3.d }, { z0.d - z3.d }, { z0.d - z3.d }"
+
+  -
+    input:
+      bytes: [ 0x14, 0xbc, 0xf4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmulh { z20.d - z23.d }, { z20.d - z23.d }, { z20.d - z23.d }"
+
+  -
+    input:
+      bytes: [ 0x14, 0xbc, 0xe8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmulh { z20.d - z23.d }, { z20.d - z23.d }, { z8.d - z11.d }"
+
+  -
+    input:
+      bytes: [ 0x1c, 0xbc, 0xfc, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmulh { z28.d - z31.d }, { z28.d - z31.d }, { z28.d - z31.d }"
+
+  -
+    input:
+      bytes: [ 0x00, 0xac, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmulh { z0.b - z3.b }, { z0.b - z3.b }, z0.b"
+
+  -
+    input:
+      bytes: [ 0x14, 0xac, 0x25, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmulh { z20.b - z23.b }, { z20.b - z23.b }, z5.b"
+
+  -
+    input:
+      bytes: [ 0x14, 0xac, 0x28, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmulh { z20.b - z23.b }, { z20.b - z23.b }, z8.b"
+
+  -
+    input:
+      bytes: [ 0x1c, 0xac, 0x2f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmulh { z28.b - z31.b }, { z28.b - z31.b }, z15.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0xbc, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmulh { z0.b - z3.b }, { z0.b - z3.b }, { z0.b - z3.b }"
+
+  -
+    input:
+      bytes: [ 0x14, 0xbc, 0x34, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmulh { z20.b - z23.b }, { z20.b - z23.b }, { z20.b - z23.b }"
+
+  -
+    input:
+      bytes: [ 0x14, 0xbc, 0x28, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmulh { z20.b - z23.b }, { z20.b - z23.b }, { z8.b - z11.b }"
+
+  -
+    input:
+      bytes: [ 0x1c, 0xbc, 0x3c, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmulh { z28.b - z31.b }, { z28.b - z31.b }, { z28.b - z31.b }"
diff --git a/tests/MC/AArch64/SME2/sqrshr.s.yaml b/tests/MC/AArch64/SME2/sqrshr.s.yaml
new file mode 100644
index 000000000..44bde4f57
--- /dev/null
+++ b/tests/MC/AArch64/SME2/sqrshr.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xd4, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshr z0.h, { z0.s, z1.s }, #16"
+
+  -
+    input:
+      bytes: [ 0x55, 0xd5, 0xe5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshr z21.h, { z10.s, z11.s }, #11"
+
+  -
+    input:
+      bytes: [ 0x97, 0xd5, 0xe8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshr z23.h, { z12.s, z13.s }, #8"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xd7, 0xef, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshr z31.h, { z30.s, z31.s }, #1"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd8, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshr z0.b, { z0.s - z3.s }, #32"
+
+  -
+    input:
+      bytes: [ 0x15, 0xd9, 0x75, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshr z21.b, { z8.s - z11.s }, #11"
+
+  -
+    input:
+      bytes: [ 0x97, 0xd9, 0x68, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshr z23.b, { z12.s - z15.s }, #24"
+
+  -
+    input:
+      bytes: [ 0x9f, 0xdb, 0x7f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshr z31.b, { z28.s - z31.s }, #1"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd8, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshr z0.h, { z0.d - z3.d }, #64"
+
+  -
+    input:
+      bytes: [ 0x15, 0xd9, 0xf5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshr z21.h, { z8.d - z11.d }, #11"
+
+  -
+    input:
+      bytes: [ 0x97, 0xd9, 0xe8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshr z23.h, { z12.d - z15.d }, #24"
+
+  -
+    input:
+      bytes: [ 0x9f, 0xdb, 0xff, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshr z31.h, { z28.d - z31.d }, #1"
diff --git a/tests/MC/AArch64/SME2/sqrshrn.s.yaml b/tests/MC/AArch64/SME2/sqrshrn.s.yaml
new file mode 100644
index 000000000..02799062f
--- /dev/null
+++ b/tests/MC/AArch64/SME2/sqrshrn.s.yaml
@@ -0,0 +1,80 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xdc, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshrn z0.b, { z0.s - z3.s }, #32"
+
+  -
+    input:
+      bytes: [ 0x15, 0xdd, 0x75, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshrn z21.b, { z8.s - z11.s }, #11"
+
+  -
+    input:
+      bytes: [ 0x97, 0xdd, 0x68, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshrn z23.b, { z12.s - z15.s }, #24"
+
+  -
+    input:
+      bytes: [ 0x9f, 0xdf, 0x7f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshrn z31.b, { z28.s - z31.s }, #1"
+
+  -
+    input:
+      bytes: [ 0x00, 0xdc, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshrn z0.h, { z0.d - z3.d }, #64"
+
+  -
+    input:
+      bytes: [ 0x15, 0xdd, 0xf5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshrn z21.h, { z8.d - z11.d }, #11"
+
+  -
+    input:
+      bytes: [ 0x97, 0xdd, 0xe8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshrn z23.h, { z12.d - z15.d }, #24"
+
+  -
+    input:
+      bytes: [ 0x9f, 0xdf, 0xff, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshrn z31.h, { z28.d - z31.d }, #1"
diff --git a/tests/MC/AArch64/SME2/sqrshru.s.yaml b/tests/MC/AArch64/SME2/sqrshru.s.yaml
new file mode 100644
index 000000000..3ef2d3056
--- /dev/null
+++ b/tests/MC/AArch64/SME2/sqrshru.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xd4, 0xf0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshru z0.h, { z0.s, z1.s }, #16"
+
+  -
+    input:
+      bytes: [ 0x55, 0xd5, 0xf5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshru z21.h, { z10.s, z11.s }, #11"
+
+  -
+    input:
+      bytes: [ 0x97, 0xd5, 0xf8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshru z23.h, { z12.s, z13.s }, #8"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xd7, 0xff, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshru z31.h, { z30.s, z31.s }, #1"
+
+  -
+    input:
+      bytes: [ 0x40, 0xd8, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshru z0.b, { z0.s - z3.s }, #32"
+
+  -
+    input:
+      bytes: [ 0x55, 0xd9, 0x75, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshru z21.b, { z8.s - z11.s }, #11"
+
+  -
+    input:
+      bytes: [ 0xd7, 0xd9, 0x68, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshru z23.b, { z12.s - z15.s }, #24"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xdb, 0x7f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshru z31.b, { z28.s - z31.s }, #1"
+
+  -
+    input:
+      bytes: [ 0x40, 0xd8, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshru z0.h, { z0.d - z3.d }, #64"
+
+  -
+    input:
+      bytes: [ 0x55, 0xd9, 0xf5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshru z21.h, { z8.d - z11.d }, #11"
+
+  -
+    input:
+      bytes: [ 0xd7, 0xd9, 0xe8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshru z23.h, { z12.d - z15.d }, #24"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xdb, 0xff, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshru z31.h, { z28.d - z31.d }, #1"
diff --git a/tests/MC/AArch64/SME2/sqrshrun.s.yaml b/tests/MC/AArch64/SME2/sqrshrun.s.yaml
new file mode 100644
index 000000000..fb734ad5d
--- /dev/null
+++ b/tests/MC/AArch64/SME2/sqrshrun.s.yaml
@@ -0,0 +1,80 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x40, 0xdc, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshrun z0.b, { z0.s - z3.s }, #32"
+
+  -
+    input:
+      bytes: [ 0x55, 0xdd, 0x75, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshrun z21.b, { z8.s - z11.s }, #11"
+
+  -
+    input:
+      bytes: [ 0xd7, 0xdd, 0x68, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshrun z23.b, { z12.s - z15.s }, #24"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xdf, 0x7f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshrun z31.b, { z28.s - z31.s }, #1"
+
+  -
+    input:
+      bytes: [ 0x40, 0xdc, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshrun z0.h, { z0.d - z3.d }, #64"
+
+  -
+    input:
+      bytes: [ 0x55, 0xdd, 0xf5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshrun z21.h, { z8.d - z11.d }, #11"
+
+  -
+    input:
+      bytes: [ 0xd7, 0xdd, 0xe8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshrun z23.h, { z12.d - z15.d }, #24"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xdf, 0xff, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshrun z31.h, { z28.d - z31.d }, #1"
diff --git a/tests/MC/AArch64/SME2/srshl.s.yaml b/tests/MC/AArch64/SME2/srshl.s.yaml
new file mode 100644
index 000000000..d240f149d
--- /dev/null
+++ b/tests/MC/AArch64/SME2/srshl.s.yaml
@@ -0,0 +1,640 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0xa2, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshl { z0.h, z1.h }, { z0.h, z1.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x34, 0xa2, 0x65, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshl { z20.h, z21.h }, { z20.h, z21.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0x36, 0xa2, 0x68, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshl { z22.h, z23.h }, { z22.h, z23.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0x3e, 0xa2, 0x6f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshl { z30.h, z31.h }, { z30.h, z31.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0xb2, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshl { z0.h, z1.h }, { z0.h, z1.h }, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x34, 0xb2, 0x74, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshl { z20.h, z21.h }, { z20.h, z21.h }, { z20.h, z21.h }"
+
+  -
+    input:
+      bytes: [ 0x36, 0xb2, 0x68, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshl { z22.h, z23.h }, { z22.h, z23.h }, { z8.h, z9.h }"
+
+  -
+    input:
+      bytes: [ 0x3e, 0xb2, 0x7e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshl { z30.h, z31.h }, { z30.h, z31.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa2, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshl { z0.s, z1.s }, { z0.s, z1.s }, z0.s"
+
+  -
+    input:
+      bytes: [ 0x34, 0xa2, 0xa5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshl { z20.s, z21.s }, { z20.s, z21.s }, z5.s"
+
+  -
+    input:
+      bytes: [ 0x36, 0xa2, 0xa8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshl { z22.s, z23.s }, { z22.s, z23.s }, z8.s"
+
+  -
+    input:
+      bytes: [ 0x3e, 0xa2, 0xaf, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshl { z30.s, z31.s }, { z30.s, z31.s }, z15.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0xb2, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshl { z0.s, z1.s }, { z0.s, z1.s }, { z0.s, z1.s }"
+
+  -
+    input:
+      bytes: [ 0x34, 0xb2, 0xb4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshl { z20.s, z21.s }, { z20.s, z21.s }, { z20.s, z21.s }"
+
+  -
+    input:
+      bytes: [ 0x36, 0xb2, 0xa8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshl { z22.s, z23.s }, { z22.s, z23.s }, { z8.s, z9.s }"
+
+  -
+    input:
+      bytes: [ 0x3e, 0xb2, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshl { z30.s, z31.s }, { z30.s, z31.s }, { z30.s, z31.s }"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa2, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshl { z0.d, z1.d }, { z0.d, z1.d }, z0.d"
+
+  -
+    input:
+      bytes: [ 0x34, 0xa2, 0xe5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshl { z20.d, z21.d }, { z20.d, z21.d }, z5.d"
+
+  -
+    input:
+      bytes: [ 0x36, 0xa2, 0xe8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshl { z22.d, z23.d }, { z22.d, z23.d }, z8.d"
+
+  -
+    input:
+      bytes: [ 0x3e, 0xa2, 0xef, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshl { z30.d, z31.d }, { z30.d, z31.d }, z15.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0xb2, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshl { z0.d, z1.d }, { z0.d, z1.d }, { z0.d, z1.d }"
+
+  -
+    input:
+      bytes: [ 0x34, 0xb2, 0xf4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshl { z20.d, z21.d }, { z20.d, z21.d }, { z20.d, z21.d }"
+
+  -
+    input:
+      bytes: [ 0x36, 0xb2, 0xe8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshl { z22.d, z23.d }, { z22.d, z23.d }, { z8.d, z9.d }"
+
+  -
+    input:
+      bytes: [ 0x3e, 0xb2, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshl { z30.d, z31.d }, { z30.d, z31.d }, { z30.d, z31.d }"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa2, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshl { z0.b, z1.b }, { z0.b, z1.b }, z0.b"
+
+  -
+    input:
+      bytes: [ 0x34, 0xa2, 0x25, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshl { z20.b, z21.b }, { z20.b, z21.b }, z5.b"
+
+  -
+    input:
+      bytes: [ 0x36, 0xa2, 0x28, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshl { z22.b, z23.b }, { z22.b, z23.b }, z8.b"
+
+  -
+    input:
+      bytes: [ 0x3e, 0xa2, 0x2f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshl { z30.b, z31.b }, { z30.b, z31.b }, z15.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0xb2, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshl { z0.b, z1.b }, { z0.b, z1.b }, { z0.b, z1.b }"
+
+  -
+    input:
+      bytes: [ 0x34, 0xb2, 0x34, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshl { z20.b, z21.b }, { z20.b, z21.b }, { z20.b, z21.b }"
+
+  -
+    input:
+      bytes: [ 0x36, 0xb2, 0x28, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshl { z22.b, z23.b }, { z22.b, z23.b }, { z8.b, z9.b }"
+
+  -
+    input:
+      bytes: [ 0x3e, 0xb2, 0x3e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshl { z30.b, z31.b }, { z30.b, z31.b }, { z30.b, z31.b }"
+
+  -
+    input:
+      bytes: [ 0x20, 0xaa, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshl { z0.h - z3.h }, { z0.h - z3.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x34, 0xaa, 0x65, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshl { z20.h - z23.h }, { z20.h - z23.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0x34, 0xaa, 0x68, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshl { z20.h - z23.h }, { z20.h - z23.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0x3c, 0xaa, 0x6f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshl { z28.h - z31.h }, { z28.h - z31.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0xba, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshl { z0.h - z3.h }, { z0.h - z3.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x34, 0xba, 0x74, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshl { z20.h - z23.h }, { z20.h - z23.h }, { z20.h - z23.h }"
+
+  -
+    input:
+      bytes: [ 0x34, 0xba, 0x68, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshl { z20.h - z23.h }, { z20.h - z23.h }, { z8.h - z11.h }"
+
+  -
+    input:
+      bytes: [ 0x3c, 0xba, 0x7c, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshl { z28.h - z31.h }, { z28.h - z31.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x20, 0xaa, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshl { z0.s - z3.s }, { z0.s - z3.s }, z0.s"
+
+  -
+    input:
+      bytes: [ 0x34, 0xaa, 0xa5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshl { z20.s - z23.s }, { z20.s - z23.s }, z5.s"
+
+  -
+    input:
+      bytes: [ 0x34, 0xaa, 0xa8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshl { z20.s - z23.s }, { z20.s - z23.s }, z8.s"
+
+  -
+    input:
+      bytes: [ 0x3c, 0xaa, 0xaf, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshl { z28.s - z31.s }, { z28.s - z31.s }, z15.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0xba, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshl { z0.s - z3.s }, { z0.s - z3.s }, { z0.s - z3.s }"
+
+  -
+    input:
+      bytes: [ 0x34, 0xba, 0xb4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshl { z20.s - z23.s }, { z20.s - z23.s }, { z20.s - z23.s }"
+
+  -
+    input:
+      bytes: [ 0x34, 0xba, 0xa8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshl { z20.s - z23.s }, { z20.s - z23.s }, { z8.s - z11.s }"
+
+  -
+    input:
+      bytes: [ 0x3c, 0xba, 0xbc, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshl { z28.s - z31.s }, { z28.s - z31.s }, { z28.s - z31.s }"
+
+  -
+    input:
+      bytes: [ 0x20, 0xaa, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshl { z0.d - z3.d }, { z0.d - z3.d }, z0.d"
+
+  -
+    input:
+      bytes: [ 0x34, 0xaa, 0xe5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshl { z20.d - z23.d }, { z20.d - z23.d }, z5.d"
+
+  -
+    input:
+      bytes: [ 0x34, 0xaa, 0xe8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshl { z20.d - z23.d }, { z20.d - z23.d }, z8.d"
+
+  -
+    input:
+      bytes: [ 0x3c, 0xaa, 0xef, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshl { z28.d - z31.d }, { z28.d - z31.d }, z15.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0xba, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshl { z0.d - z3.d }, { z0.d - z3.d }, { z0.d - z3.d }"
+
+  -
+    input:
+      bytes: [ 0x34, 0xba, 0xf4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshl { z20.d - z23.d }, { z20.d - z23.d }, { z20.d - z23.d }"
+
+  -
+    input:
+      bytes: [ 0x34, 0xba, 0xe8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshl { z20.d - z23.d }, { z20.d - z23.d }, { z8.d - z11.d }"
+
+  -
+    input:
+      bytes: [ 0x3c, 0xba, 0xfc, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshl { z28.d - z31.d }, { z28.d - z31.d }, { z28.d - z31.d }"
+
+  -
+    input:
+      bytes: [ 0x20, 0xaa, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshl { z0.b - z3.b }, { z0.b - z3.b }, z0.b"
+
+  -
+    input:
+      bytes: [ 0x34, 0xaa, 0x25, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshl { z20.b - z23.b }, { z20.b - z23.b }, z5.b"
+
+  -
+    input:
+      bytes: [ 0x34, 0xaa, 0x28, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshl { z20.b - z23.b }, { z20.b - z23.b }, z8.b"
+
+  -
+    input:
+      bytes: [ 0x3c, 0xaa, 0x2f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshl { z28.b - z31.b }, { z28.b - z31.b }, z15.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0xba, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshl { z0.b - z3.b }, { z0.b - z3.b }, { z0.b - z3.b }"
+
+  -
+    input:
+      bytes: [ 0x34, 0xba, 0x34, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshl { z20.b - z23.b }, { z20.b - z23.b }, { z20.b - z23.b }"
+
+  -
+    input:
+      bytes: [ 0x34, 0xba, 0x28, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshl { z20.b - z23.b }, { z20.b - z23.b }, { z8.b - z11.b }"
+
+  -
+    input:
+      bytes: [ 0x3c, 0xba, 0x3c, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshl { z28.b - z31.b }, { z28.b - z31.b }, { z28.b - z31.b }"
diff --git a/tests/MC/AArch64/SME2/st1b.s.yaml b/tests/MC/AArch64/SME2/st1b.s.yaml
new file mode 100644
index 000000000..0bd3aaac3
--- /dev/null
+++ b/tests/MC/AArch64/SME2/st1b.s.yaml
@@ -0,0 +1,160 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x20, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b { z0.b, z8.b }, pn8, [x0, x0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x15, 0x35, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b { z21.b, z29.b }, pn13, [x10, x21]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x0d, 0x28, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b { z23.b, z31.b }, pn11, [x13, x8]"
+
+  -
+    input:
+      bytes: [ 0xf7, 0x1f, 0x3f, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b { z23.b, z31.b }, pn15, [sp, xzr]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x60, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b { z0.b, z8.b }, pn8, [x0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x15, 0x65, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b { z21.b, z29.b }, pn13, [x10, #10, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x0d, 0x68, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b { z23.b, z31.b }, pn11, [x13, #-16, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xf7, 0x1f, 0x6f, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b { z23.b, z31.b }, pn15, [sp, #-2, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x20, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b { z0.b, z4.b, z8.b, z12.b }, pn8, [x0, x0]"
+
+  -
+    input:
+      bytes: [ 0x51, 0x95, 0x35, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b { z17.b, z21.b, z25.b, z29.b }, pn13, [x10, x21]"
+
+  -
+    input:
+      bytes: [ 0xb3, 0x8d, 0x28, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b { z19.b, z23.b, z27.b, z31.b }, pn11, [x13, x8]"
+
+  -
+    input:
+      bytes: [ 0xf3, 0x9f, 0x3f, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b { z19.b, z23.b, z27.b, z31.b }, pn15, [sp, xzr]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x60, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b { z0.b, z4.b, z8.b, z12.b }, pn8, [x0]"
+
+  -
+    input:
+      bytes: [ 0x51, 0x95, 0x65, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b { z17.b, z21.b, z25.b, z29.b }, pn13, [x10, #20, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xb3, 0x8d, 0x68, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b { z19.b, z23.b, z27.b, z31.b }, pn11, [x13, #-32, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xf3, 0x9f, 0x6f, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b { z19.b, z23.b, z27.b, z31.b }, pn15, [sp, #-4, mul vl]"
diff --git a/tests/MC/AArch64/SME2/st1d.s.yaml b/tests/MC/AArch64/SME2/st1d.s.yaml
new file mode 100644
index 000000000..c19ccf187
--- /dev/null
+++ b/tests/MC/AArch64/SME2/st1d.s.yaml
@@ -0,0 +1,160 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0x20, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d { z0.d, z8.d }, pn8, [x0, x0, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x75, 0x35, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d { z21.d, z29.d }, pn13, [x10, x21, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x6d, 0x28, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d { z23.d, z31.d }, pn11, [x13, x8, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0xf7, 0x7f, 0x3f, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d { z23.d, z31.d }, pn15, [sp, xzr, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0x60, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d { z0.d, z8.d }, pn8, [x0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x75, 0x65, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d { z21.d, z29.d }, pn13, [x10, #10, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x6d, 0x68, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d { z23.d, z31.d }, pn11, [x13, #-16, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xf7, 0x7f, 0x6f, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d { z23.d, z31.d }, pn15, [sp, #-2, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x20, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d { z0.d, z4.d, z8.d, z12.d }, pn8, [x0, x0, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x51, 0xf5, 0x35, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d { z17.d, z21.d, z25.d, z29.d }, pn13, [x10, x21, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0xb3, 0xed, 0x28, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d { z19.d, z23.d, z27.d, z31.d }, pn11, [x13, x8, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0xf3, 0xff, 0x3f, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d { z19.d, z23.d, z27.d, z31.d }, pn15, [sp, xzr, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x60, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d { z0.d, z4.d, z8.d, z12.d }, pn8, [x0]"
+
+  -
+    input:
+      bytes: [ 0x51, 0xf5, 0x65, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d { z17.d, z21.d, z25.d, z29.d }, pn13, [x10, #20, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xb3, 0xed, 0x68, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d { z19.d, z23.d, z27.d, z31.d }, pn11, [x13, #-32, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xf3, 0xff, 0x6f, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d { z19.d, z23.d, z27.d, z31.d }, pn15, [sp, #-4, mul vl]"
diff --git a/tests/MC/AArch64/SME2/st1h.s.yaml b/tests/MC/AArch64/SME2/st1h.s.yaml
new file mode 100644
index 000000000..17421ee43
--- /dev/null
+++ b/tests/MC/AArch64/SME2/st1h.s.yaml
@@ -0,0 +1,160 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x20, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h { z0.h, z8.h }, pn8, [x0, x0, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x35, 0x35, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h { z21.h, z29.h }, pn13, [x10, x21, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x2d, 0x28, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h { z23.h, z31.h }, pn11, [x13, x8, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0xf7, 0x3f, 0x3f, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h { z23.h, z31.h }, pn15, [sp, xzr, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x60, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h { z0.h, z8.h }, pn8, [x0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x35, 0x65, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h { z21.h, z29.h }, pn13, [x10, #10, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x2d, 0x68, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h { z23.h, z31.h }, pn11, [x13, #-16, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xf7, 0x3f, 0x6f, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h { z23.h, z31.h }, pn15, [sp, #-2, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x20, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h { z0.h, z4.h, z8.h, z12.h }, pn8, [x0, x0, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x51, 0xb5, 0x35, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h { z17.h, z21.h, z25.h, z29.h }, pn13, [x10, x21, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0xb3, 0xad, 0x28, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h { z19.h, z23.h, z27.h, z31.h }, pn11, [x13, x8, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0xf3, 0xbf, 0x3f, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h { z19.h, z23.h, z27.h, z31.h }, pn15, [sp, xzr, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x60, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h { z0.h, z4.h, z8.h, z12.h }, pn8, [x0]"
+
+  -
+    input:
+      bytes: [ 0x51, 0xb5, 0x65, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h { z17.h, z21.h, z25.h, z29.h }, pn13, [x10, #20, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xb3, 0xad, 0x68, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h { z19.h, z23.h, z27.h, z31.h }, pn11, [x13, #-32, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xf3, 0xbf, 0x6f, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h { z19.h, z23.h, z27.h, z31.h }, pn15, [sp, #-4, mul vl]"
diff --git a/tests/MC/AArch64/SME2/st1w.s.yaml b/tests/MC/AArch64/SME2/st1w.s.yaml
new file mode 100644
index 000000000..8fce0399e
--- /dev/null
+++ b/tests/MC/AArch64/SME2/st1w.s.yaml
@@ -0,0 +1,160 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0x20, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w { z0.s, z8.s }, pn8, [x0, x0, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x55, 0x35, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w { z21.s, z29.s }, pn13, [x10, x21, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x4d, 0x28, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w { z23.s, z31.s }, pn11, [x13, x8, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0xf7, 0x5f, 0x3f, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w { z23.s, z31.s }, pn15, [sp, xzr, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0x60, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w { z0.s, z8.s }, pn8, [x0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x55, 0x65, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w { z21.s, z29.s }, pn13, [x10, #10, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x4d, 0x68, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w { z23.s, z31.s }, pn11, [x13, #-16, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xf7, 0x5f, 0x6f, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w { z23.s, z31.s }, pn15, [sp, #-2, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x20, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w { z0.s, z4.s, z8.s, z12.s }, pn8, [x0, x0, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x51, 0xd5, 0x35, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w { z17.s, z21.s, z25.s, z29.s }, pn13, [x10, x21, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0xb3, 0xcd, 0x28, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w { z19.s, z23.s, z27.s, z31.s }, pn11, [x13, x8, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0xf3, 0xdf, 0x3f, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w { z19.s, z23.s, z27.s, z31.s }, pn15, [sp, xzr, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x60, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w { z0.s, z4.s, z8.s, z12.s }, pn8, [x0]"
+
+  -
+    input:
+      bytes: [ 0x51, 0xd5, 0x65, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w { z17.s, z21.s, z25.s, z29.s }, pn13, [x10, #20, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xb3, 0xcd, 0x68, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w { z19.s, z23.s, z27.s, z31.s }, pn11, [x13, #-32, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xf3, 0xdf, 0x6f, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w { z19.s, z23.s, z27.s, z31.s }, pn15, [sp, #-4, mul vl]"
diff --git a/tests/MC/AArch64/SME2/stnt1b.s.yaml b/tests/MC/AArch64/SME2/stnt1b.s.yaml
new file mode 100644
index 000000000..8c8263553
--- /dev/null
+++ b/tests/MC/AArch64/SME2/stnt1b.s.yaml
@@ -0,0 +1,160 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x08, 0x00, 0x20, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1b { z0.b, z8.b }, pn8, [x0, x0]"
+
+  -
+    input:
+      bytes: [ 0x5d, 0x15, 0x35, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1b { z21.b, z29.b }, pn13, [x10, x21]"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x0d, 0x28, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1b { z23.b, z31.b }, pn11, [x13, x8]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0x3f, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1b { z23.b, z31.b }, pn15, [sp, xzr]"
+
+  -
+    input:
+      bytes: [ 0x08, 0x00, 0x60, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1b { z0.b, z8.b }, pn8, [x0]"
+
+  -
+    input:
+      bytes: [ 0x5d, 0x15, 0x65, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1b { z21.b, z29.b }, pn13, [x10, #10, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x0d, 0x68, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1b { z23.b, z31.b }, pn11, [x13, #-16, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0x6f, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1b { z23.b, z31.b }, pn15, [sp, #-2, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x08, 0x80, 0x20, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1b { z0.b, z4.b, z8.b, z12.b }, pn8, [x0, x0]"
+
+  -
+    input:
+      bytes: [ 0x59, 0x95, 0x35, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1b { z17.b, z21.b, z25.b, z29.b }, pn13, [x10, x21]"
+
+  -
+    input:
+      bytes: [ 0xbb, 0x8d, 0x28, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1b { z19.b, z23.b, z27.b, z31.b }, pn11, [x13, x8]"
+
+  -
+    input:
+      bytes: [ 0xfb, 0x9f, 0x3f, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1b { z19.b, z23.b, z27.b, z31.b }, pn15, [sp, xzr]"
+
+  -
+    input:
+      bytes: [ 0x08, 0x80, 0x60, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1b { z0.b, z4.b, z8.b, z12.b }, pn8, [x0]"
+
+  -
+    input:
+      bytes: [ 0x59, 0x95, 0x65, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1b { z17.b, z21.b, z25.b, z29.b }, pn13, [x10, #20, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xbb, 0x8d, 0x68, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1b { z19.b, z23.b, z27.b, z31.b }, pn11, [x13, #-32, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xfb, 0x9f, 0x6f, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1b { z19.b, z23.b, z27.b, z31.b }, pn15, [sp, #-4, mul vl]"
diff --git a/tests/MC/AArch64/SME2/stnt1d.s.yaml b/tests/MC/AArch64/SME2/stnt1d.s.yaml
new file mode 100644
index 000000000..9b8589da8
--- /dev/null
+++ b/tests/MC/AArch64/SME2/stnt1d.s.yaml
@@ -0,0 +1,160 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x08, 0x60, 0x20, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1d { z0.d, z8.d }, pn8, [x0, x0, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x5d, 0x75, 0x35, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1d { z21.d, z29.d }, pn13, [x10, x21, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x6d, 0x28, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1d { z23.d, z31.d }, pn11, [x13, x8, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x7f, 0x3f, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1d { z23.d, z31.d }, pn15, [sp, xzr, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x08, 0x60, 0x60, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1d { z0.d, z8.d }, pn8, [x0]"
+
+  -
+    input:
+      bytes: [ 0x5d, 0x75, 0x65, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1d { z21.d, z29.d }, pn13, [x10, #10, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x6d, 0x68, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1d { z23.d, z31.d }, pn11, [x13, #-16, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x7f, 0x6f, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1d { z23.d, z31.d }, pn15, [sp, #-2, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x08, 0xe0, 0x20, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1d { z0.d, z4.d, z8.d, z12.d }, pn8, [x0, x0, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x59, 0xf5, 0x35, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1d { z17.d, z21.d, z25.d, z29.d }, pn13, [x10, x21, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0xbb, 0xed, 0x28, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1d { z19.d, z23.d, z27.d, z31.d }, pn11, [x13, x8, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0xfb, 0xff, 0x3f, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1d { z19.d, z23.d, z27.d, z31.d }, pn15, [sp, xzr, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x08, 0xe0, 0x60, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1d { z0.d, z4.d, z8.d, z12.d }, pn8, [x0]"
+
+  -
+    input:
+      bytes: [ 0x59, 0xf5, 0x65, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1d { z17.d, z21.d, z25.d, z29.d }, pn13, [x10, #20, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xbb, 0xed, 0x68, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1d { z19.d, z23.d, z27.d, z31.d }, pn11, [x13, #-32, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xfb, 0xff, 0x6f, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1d { z19.d, z23.d, z27.d, z31.d }, pn15, [sp, #-4, mul vl]"
diff --git a/tests/MC/AArch64/SME2/stnt1h.s.yaml b/tests/MC/AArch64/SME2/stnt1h.s.yaml
new file mode 100644
index 000000000..be809be3a
--- /dev/null
+++ b/tests/MC/AArch64/SME2/stnt1h.s.yaml
@@ -0,0 +1,160 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x08, 0x20, 0x20, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1h { z0.h, z8.h }, pn8, [x0, x0, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x5d, 0x35, 0x35, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1h { z21.h, z29.h }, pn13, [x10, x21, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x2d, 0x28, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1h { z23.h, z31.h }, pn11, [x13, x8, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0x3f, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1h { z23.h, z31.h }, pn15, [sp, xzr, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x08, 0x20, 0x60, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1h { z0.h, z8.h }, pn8, [x0]"
+
+  -
+    input:
+      bytes: [ 0x5d, 0x35, 0x65, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1h { z21.h, z29.h }, pn13, [x10, #10, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x2d, 0x68, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1h { z23.h, z31.h }, pn11, [x13, #-16, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0x6f, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1h { z23.h, z31.h }, pn15, [sp, #-2, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x08, 0xa0, 0x20, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1h { z0.h, z4.h, z8.h, z12.h }, pn8, [x0, x0, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x59, 0xb5, 0x35, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1h { z17.h, z21.h, z25.h, z29.h }, pn13, [x10, x21, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0xbb, 0xad, 0x28, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1h { z19.h, z23.h, z27.h, z31.h }, pn11, [x13, x8, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0xfb, 0xbf, 0x3f, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1h { z19.h, z23.h, z27.h, z31.h }, pn15, [sp, xzr, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x08, 0xa0, 0x60, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1h { z0.h, z4.h, z8.h, z12.h }, pn8, [x0]"
+
+  -
+    input:
+      bytes: [ 0x59, 0xb5, 0x65, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1h { z17.h, z21.h, z25.h, z29.h }, pn13, [x10, #20, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xbb, 0xad, 0x68, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1h { z19.h, z23.h, z27.h, z31.h }, pn11, [x13, #-32, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xfb, 0xbf, 0x6f, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1h { z19.h, z23.h, z27.h, z31.h }, pn15, [sp, #-4, mul vl]"
diff --git a/tests/MC/AArch64/SME2/stnt1w.s.yaml b/tests/MC/AArch64/SME2/stnt1w.s.yaml
new file mode 100644
index 000000000..80324e998
--- /dev/null
+++ b/tests/MC/AArch64/SME2/stnt1w.s.yaml
@@ -0,0 +1,160 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x08, 0x40, 0x20, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1w { z0.s, z8.s }, pn8, [x0, x0, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x5d, 0x55, 0x35, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1w { z21.s, z29.s }, pn13, [x10, x21, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x4d, 0x28, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1w { z23.s, z31.s }, pn11, [x13, x8, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x5f, 0x3f, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1w { z23.s, z31.s }, pn15, [sp, xzr, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x08, 0x40, 0x60, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1w { z0.s, z8.s }, pn8, [x0]"
+
+  -
+    input:
+      bytes: [ 0x5d, 0x55, 0x65, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1w { z21.s, z29.s }, pn13, [x10, #10, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x4d, 0x68, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1w { z23.s, z31.s }, pn11, [x13, #-16, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x5f, 0x6f, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1w { z23.s, z31.s }, pn15, [sp, #-2, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x08, 0xc0, 0x20, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1w { z0.s, z4.s, z8.s, z12.s }, pn8, [x0, x0, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x59, 0xd5, 0x35, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1w { z17.s, z21.s, z25.s, z29.s }, pn13, [x10, x21, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0xbb, 0xcd, 0x28, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1w { z19.s, z23.s, z27.s, z31.s }, pn11, [x13, x8, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0xfb, 0xdf, 0x3f, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1w { z19.s, z23.s, z27.s, z31.s }, pn15, [sp, xzr, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x08, 0xc0, 0x60, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1w { z0.s, z4.s, z8.s, z12.s }, pn8, [x0]"
+
+  -
+    input:
+      bytes: [ 0x59, 0xd5, 0x65, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1w { z17.s, z21.s, z25.s, z29.s }, pn13, [x10, #20, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xbb, 0xcd, 0x68, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1w { z19.s, z23.s, z27.s, z31.s }, pn11, [x13, #-32, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xfb, 0xdf, 0x6f, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1w { z19.s, z23.s, z27.s, z31.s }, pn15, [sp, #-4, mul vl]"
diff --git a/tests/MC/AArch64/SME2/str.s.yaml b/tests/MC/AArch64/SME2/str.s.yaml
new file mode 100644
index 000000000..b840c7304
--- /dev/null
+++ b/tests/MC/AArch64/SME2/str.s.yaml
@@ -0,0 +1,40 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x3f, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "str zt0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x40, 0x81, 0x3f, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "str zt0, [x10]"
+
+  -
+    input:
+      bytes: [ 0xa0, 0x81, 0x3f, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "str zt0, [x13]"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x83, 0x3f, 0xe1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "str zt0, [sp]"
diff --git a/tests/MC/AArch64/SME2/sub.s.yaml b/tests/MC/AArch64/SME2/sub.s.yaml
new file mode 100644
index 000000000..75bc549d2
--- /dev/null
+++ b/tests/MC/AArch64/SME2/sub.s.yaml
@@ -0,0 +1,2880 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x18, 0x1c, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w8, 0, vgx2], { z0.s, z1.s }"
+
+  -
+    input:
+      bytes: [ 0x18, 0x1c, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w8, 0, vgx2], { z0.s, z1.s }"
+
+  -
+    input:
+      bytes: [ 0x5d, 0x5d, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w10, 5, vgx2], { z10.s, z11.s }"
+
+  -
+    input:
+      bytes: [ 0x5d, 0x5d, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w10, 5, vgx2], { z10.s, z11.s }"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x7d, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w11, 7, vgx2], { z12.s, z13.s }"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x7d, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w11, 7, vgx2], { z12.s, z13.s }"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x7f, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w11, 7, vgx2], { z30.s, z31.s }"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x7f, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w11, 7, vgx2], { z30.s, z31.s }"
+
+  -
+    input:
+      bytes: [ 0x1d, 0x1e, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w8, 5, vgx2], { z16.s, z17.s }"
+
+  -
+    input:
+      bytes: [ 0x1d, 0x1e, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w8, 5, vgx2], { z16.s, z17.s }"
+
+  -
+    input:
+      bytes: [ 0x19, 0x1c, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w8, 1, vgx2], { z0.s, z1.s }"
+
+  -
+    input:
+      bytes: [ 0x19, 0x1c, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w8, 1, vgx2], { z0.s, z1.s }"
+
+  -
+    input:
+      bytes: [ 0x58, 0x5e, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w10, 0, vgx2], { z18.s, z19.s }"
+
+  -
+    input:
+      bytes: [ 0x58, 0x5e, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w10, 0, vgx2], { z18.s, z19.s }"
+
+  -
+    input:
+      bytes: [ 0x98, 0x1d, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w8, 0, vgx2], { z12.s, z13.s }"
+
+  -
+    input:
+      bytes: [ 0x98, 0x1d, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w8, 0, vgx2], { z12.s, z13.s }"
+
+  -
+    input:
+      bytes: [ 0x19, 0x5c, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w10, 1, vgx2], { z0.s, z1.s }"
+
+  -
+    input:
+      bytes: [ 0x19, 0x5c, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w10, 1, vgx2], { z0.s, z1.s }"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x1e, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w8, 5, vgx2], { z22.s, z23.s }"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x1e, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w8, 5, vgx2], { z22.s, z23.s }"
+
+  -
+    input:
+      bytes: [ 0x1a, 0x7d, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w11, 2, vgx2], { z8.s, z9.s }"
+
+  -
+    input:
+      bytes: [ 0x1a, 0x7d, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w11, 2, vgx2], { z8.s, z9.s }"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x3d, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w9, 7, vgx2], { z12.s, z13.s }"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x3d, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w9, 7, vgx2], { z12.s, z13.s }"
+
+  -
+    input:
+      bytes: [ 0x18, 0x18, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w8, 0, vgx2], { z0.s, z1.s }, z0.s"
+
+  -
+    input:
+      bytes: [ 0x18, 0x18, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w8, 0, vgx2], { z0.s, z1.s }, z0.s"
+
+  -
+    input:
+      bytes: [ 0x5d, 0x59, 0x25, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w10, 5, vgx2], { z10.s, z11.s }, z5.s"
+
+  -
+    input:
+      bytes: [ 0x5d, 0x59, 0x25, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w10, 5, vgx2], { z10.s, z11.s }, z5.s"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x79, 0x28, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w11, 7, vgx2], { z13.s, z14.s }, z8.s"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x79, 0x28, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w11, 7, vgx2], { z13.s, z14.s }, z8.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0x7b, 0x2f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w11, 7, vgx2], { z31.s, z0.s }, z15.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0x7b, 0x2f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w11, 7, vgx2], { z31.s, z0.s }, z15.s"
+
+  -
+    input:
+      bytes: [ 0x3d, 0x1a, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w8, 5, vgx2], { z17.s, z18.s }, z0.s"
+
+  -
+    input:
+      bytes: [ 0x3d, 0x1a, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w8, 5, vgx2], { z17.s, z18.s }, z0.s"
+
+  -
+    input:
+      bytes: [ 0x39, 0x18, 0x2e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w8, 1, vgx2], { z1.s, z2.s }, z14.s"
+
+  -
+    input:
+      bytes: [ 0x39, 0x18, 0x2e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w8, 1, vgx2], { z1.s, z2.s }, z14.s"
+
+  -
+    input:
+      bytes: [ 0x78, 0x5a, 0x24, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w10, 0, vgx2], { z19.s, z20.s }, z4.s"
+
+  -
+    input:
+      bytes: [ 0x78, 0x5a, 0x24, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w10, 0, vgx2], { z19.s, z20.s }, z4.s"
+
+  -
+    input:
+      bytes: [ 0x98, 0x19, 0x22, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w8, 0, vgx2], { z12.s, z13.s }, z2.s"
+
+  -
+    input:
+      bytes: [ 0x98, 0x19, 0x22, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w8, 0, vgx2], { z12.s, z13.s }, z2.s"
+
+  -
+    input:
+      bytes: [ 0x39, 0x58, 0x2a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w10, 1, vgx2], { z1.s, z2.s }, z10.s"
+
+  -
+    input:
+      bytes: [ 0x39, 0x58, 0x2a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w10, 1, vgx2], { z1.s, z2.s }, z10.s"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x1a, 0x2e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w8, 5, vgx2], { z22.s, z23.s }, z14.s"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x1a, 0x2e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w8, 5, vgx2], { z22.s, z23.s }, z14.s"
+
+  -
+    input:
+      bytes: [ 0x3a, 0x79, 0x21, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w11, 2, vgx2], { z9.s, z10.s }, z1.s"
+
+  -
+    input:
+      bytes: [ 0x3a, 0x79, 0x21, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w11, 2, vgx2], { z9.s, z10.s }, z1.s"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x39, 0x2b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w9, 7, vgx2], { z12.s, z13.s }, z11.s"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x39, 0x2b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w9, 7, vgx2], { z12.s, z13.s }, z11.s"
+
+  -
+    input:
+      bytes: [ 0x18, 0x18, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w8, 0, vgx2], { z0.s, z1.s }, { z0.s, z1.s }"
+
+  -
+    input:
+      bytes: [ 0x18, 0x18, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w8, 0, vgx2], { z0.s, z1.s }, { z0.s, z1.s }"
+
+  -
+    input:
+      bytes: [ 0x5d, 0x59, 0xb4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w10, 5, vgx2], { z10.s, z11.s }, { z20.s, z21.s }"
+
+  -
+    input:
+      bytes: [ 0x5d, 0x59, 0xb4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w10, 5, vgx2], { z10.s, z11.s }, { z20.s, z21.s }"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x79, 0xa8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w11, 7, vgx2], { z12.s, z13.s }, { z8.s, z9.s }"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x79, 0xa8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w11, 7, vgx2], { z12.s, z13.s }, { z8.s, z9.s }"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x7b, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w11, 7, vgx2], { z30.s, z31.s }, { z30.s, z31.s }"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x7b, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w11, 7, vgx2], { z30.s, z31.s }, { z30.s, z31.s }"
+
+  -
+    input:
+      bytes: [ 0x1d, 0x1a, 0xb0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w8, 5, vgx2], { z16.s, z17.s }, { z16.s, z17.s }"
+
+  -
+    input:
+      bytes: [ 0x1d, 0x1a, 0xb0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w8, 5, vgx2], { z16.s, z17.s }, { z16.s, z17.s }"
+
+  -
+    input:
+      bytes: [ 0x19, 0x18, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w8, 1, vgx2], { z0.s, z1.s }, { z30.s, z31.s }"
+
+  -
+    input:
+      bytes: [ 0x19, 0x18, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w8, 1, vgx2], { z0.s, z1.s }, { z30.s, z31.s }"
+
+  -
+    input:
+      bytes: [ 0x58, 0x5a, 0xb4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w10, 0, vgx2], { z18.s, z19.s }, { z20.s, z21.s }"
+
+  -
+    input:
+      bytes: [ 0x58, 0x5a, 0xb4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w10, 0, vgx2], { z18.s, z19.s }, { z20.s, z21.s }"
+
+  -
+    input:
+      bytes: [ 0x98, 0x19, 0xa2, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w8, 0, vgx2], { z12.s, z13.s }, { z2.s, z3.s }"
+
+  -
+    input:
+      bytes: [ 0x98, 0x19, 0xa2, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w8, 0, vgx2], { z12.s, z13.s }, { z2.s, z3.s }"
+
+  -
+    input:
+      bytes: [ 0x19, 0x58, 0xba, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w10, 1, vgx2], { z0.s, z1.s }, { z26.s, z27.s }"
+
+  -
+    input:
+      bytes: [ 0x19, 0x58, 0xba, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w10, 1, vgx2], { z0.s, z1.s }, { z26.s, z27.s }"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x1a, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w8, 5, vgx2], { z22.s, z23.s }, { z30.s, z31.s }"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x1a, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w8, 5, vgx2], { z22.s, z23.s }, { z30.s, z31.s }"
+
+  -
+    input:
+      bytes: [ 0x1a, 0x79, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w11, 2, vgx2], { z8.s, z9.s }, { z0.s, z1.s }"
+
+  -
+    input:
+      bytes: [ 0x1a, 0x79, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w11, 2, vgx2], { z8.s, z9.s }, { z0.s, z1.s }"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x39, 0xaa, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w9, 7, vgx2], { z12.s, z13.s }, { z10.s, z11.s }"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x39, 0xaa, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w9, 7, vgx2], { z12.s, z13.s }, { z10.s, z11.s }"
+
+  -
+    input:
+      bytes: [ 0x18, 0x1c, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w8, 0, vgx2], { z0.d, z1.d }"
+
+  -
+    input:
+      bytes: [ 0x18, 0x1c, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w8, 0, vgx2], { z0.d, z1.d }"
+
+  -
+    input:
+      bytes: [ 0x5d, 0x5d, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w10, 5, vgx2], { z10.d, z11.d }"
+
+  -
+    input:
+      bytes: [ 0x5d, 0x5d, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w10, 5, vgx2], { z10.d, z11.d }"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x7d, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w11, 7, vgx2], { z12.d, z13.d }"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x7d, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w11, 7, vgx2], { z12.d, z13.d }"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x7f, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w11, 7, vgx2], { z30.d, z31.d }"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x7f, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w11, 7, vgx2], { z30.d, z31.d }"
+
+  -
+    input:
+      bytes: [ 0x1d, 0x1e, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w8, 5, vgx2], { z16.d, z17.d }"
+
+  -
+    input:
+      bytes: [ 0x1d, 0x1e, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w8, 5, vgx2], { z16.d, z17.d }"
+
+  -
+    input:
+      bytes: [ 0x19, 0x1c, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w8, 1, vgx2], { z0.d, z1.d }"
+
+  -
+    input:
+      bytes: [ 0x19, 0x1c, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w8, 1, vgx2], { z0.d, z1.d }"
+
+  -
+    input:
+      bytes: [ 0x58, 0x5e, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w10, 0, vgx2], { z18.d, z19.d }"
+
+  -
+    input:
+      bytes: [ 0x58, 0x5e, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w10, 0, vgx2], { z18.d, z19.d }"
+
+  -
+    input:
+      bytes: [ 0x98, 0x1d, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w8, 0, vgx2], { z12.d, z13.d }"
+
+  -
+    input:
+      bytes: [ 0x98, 0x1d, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w8, 0, vgx2], { z12.d, z13.d }"
+
+  -
+    input:
+      bytes: [ 0x19, 0x5c, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w10, 1, vgx2], { z0.d, z1.d }"
+
+  -
+    input:
+      bytes: [ 0x19, 0x5c, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w10, 1, vgx2], { z0.d, z1.d }"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x1e, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w8, 5, vgx2], { z22.d, z23.d }"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x1e, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w8, 5, vgx2], { z22.d, z23.d }"
+
+  -
+    input:
+      bytes: [ 0x1a, 0x7d, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w11, 2, vgx2], { z8.d, z9.d }"
+
+  -
+    input:
+      bytes: [ 0x1a, 0x7d, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w11, 2, vgx2], { z8.d, z9.d }"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x3d, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w9, 7, vgx2], { z12.d, z13.d }"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x3d, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w9, 7, vgx2], { z12.d, z13.d }"
+
+  -
+    input:
+      bytes: [ 0x18, 0x18, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w8, 0, vgx2], { z0.d, z1.d }, z0.d"
+
+  -
+    input:
+      bytes: [ 0x18, 0x18, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w8, 0, vgx2], { z0.d, z1.d }, z0.d"
+
+  -
+    input:
+      bytes: [ 0x5d, 0x59, 0x65, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w10, 5, vgx2], { z10.d, z11.d }, z5.d"
+
+  -
+    input:
+      bytes: [ 0x5d, 0x59, 0x65, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w10, 5, vgx2], { z10.d, z11.d }, z5.d"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x79, 0x68, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w11, 7, vgx2], { z13.d, z14.d }, z8.d"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x79, 0x68, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w11, 7, vgx2], { z13.d, z14.d }, z8.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0x7b, 0x6f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w11, 7, vgx2], { z31.d, z0.d }, z15.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0x7b, 0x6f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w11, 7, vgx2], { z31.d, z0.d }, z15.d"
+
+  -
+    input:
+      bytes: [ 0x3d, 0x1a, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w8, 5, vgx2], { z17.d, z18.d }, z0.d"
+
+  -
+    input:
+      bytes: [ 0x3d, 0x1a, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w8, 5, vgx2], { z17.d, z18.d }, z0.d"
+
+  -
+    input:
+      bytes: [ 0x39, 0x18, 0x6e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w8, 1, vgx2], { z1.d, z2.d }, z14.d"
+
+  -
+    input:
+      bytes: [ 0x39, 0x18, 0x6e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w8, 1, vgx2], { z1.d, z2.d }, z14.d"
+
+  -
+    input:
+      bytes: [ 0x78, 0x5a, 0x64, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w10, 0, vgx2], { z19.d, z20.d }, z4.d"
+
+  -
+    input:
+      bytes: [ 0x78, 0x5a, 0x64, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w10, 0, vgx2], { z19.d, z20.d }, z4.d"
+
+  -
+    input:
+      bytes: [ 0x98, 0x19, 0x62, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w8, 0, vgx2], { z12.d, z13.d }, z2.d"
+
+  -
+    input:
+      bytes: [ 0x98, 0x19, 0x62, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w8, 0, vgx2], { z12.d, z13.d }, z2.d"
+
+  -
+    input:
+      bytes: [ 0x39, 0x58, 0x6a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w10, 1, vgx2], { z1.d, z2.d }, z10.d"
+
+  -
+    input:
+      bytes: [ 0x39, 0x58, 0x6a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w10, 1, vgx2], { z1.d, z2.d }, z10.d"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x1a, 0x6e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w8, 5, vgx2], { z22.d, z23.d }, z14.d"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x1a, 0x6e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w8, 5, vgx2], { z22.d, z23.d }, z14.d"
+
+  -
+    input:
+      bytes: [ 0x3a, 0x79, 0x61, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w11, 2, vgx2], { z9.d, z10.d }, z1.d"
+
+  -
+    input:
+      bytes: [ 0x3a, 0x79, 0x61, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w11, 2, vgx2], { z9.d, z10.d }, z1.d"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x39, 0x6b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w9, 7, vgx2], { z12.d, z13.d }, z11.d"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x39, 0x6b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w9, 7, vgx2], { z12.d, z13.d }, z11.d"
+
+  -
+    input:
+      bytes: [ 0x18, 0x18, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w8, 0, vgx2], { z0.d, z1.d }, { z0.d, z1.d }"
+
+  -
+    input:
+      bytes: [ 0x18, 0x18, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w8, 0, vgx2], { z0.d, z1.d }, { z0.d, z1.d }"
+
+  -
+    input:
+      bytes: [ 0x5d, 0x59, 0xf4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w10, 5, vgx2], { z10.d, z11.d }, { z20.d, z21.d }"
+
+  -
+    input:
+      bytes: [ 0x5d, 0x59, 0xf4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w10, 5, vgx2], { z10.d, z11.d }, { z20.d, z21.d }"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x79, 0xe8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w11, 7, vgx2], { z12.d, z13.d }, { z8.d, z9.d }"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x79, 0xe8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w11, 7, vgx2], { z12.d, z13.d }, { z8.d, z9.d }"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x7b, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w11, 7, vgx2], { z30.d, z31.d }, { z30.d, z31.d }"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x7b, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w11, 7, vgx2], { z30.d, z31.d }, { z30.d, z31.d }"
+
+  -
+    input:
+      bytes: [ 0x1d, 0x1a, 0xf0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w8, 5, vgx2], { z16.d, z17.d }, { z16.d, z17.d }"
+
+  -
+    input:
+      bytes: [ 0x1d, 0x1a, 0xf0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w8, 5, vgx2], { z16.d, z17.d }, { z16.d, z17.d }"
+
+  -
+    input:
+      bytes: [ 0x19, 0x18, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w8, 1, vgx2], { z0.d, z1.d }, { z30.d, z31.d }"
+
+  -
+    input:
+      bytes: [ 0x19, 0x18, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w8, 1, vgx2], { z0.d, z1.d }, { z30.d, z31.d }"
+
+  -
+    input:
+      bytes: [ 0x58, 0x5a, 0xf4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w10, 0, vgx2], { z18.d, z19.d }, { z20.d, z21.d }"
+
+  -
+    input:
+      bytes: [ 0x58, 0x5a, 0xf4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w10, 0, vgx2], { z18.d, z19.d }, { z20.d, z21.d }"
+
+  -
+    input:
+      bytes: [ 0x98, 0x19, 0xe2, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w8, 0, vgx2], { z12.d, z13.d }, { z2.d, z3.d }"
+
+  -
+    input:
+      bytes: [ 0x98, 0x19, 0xe2, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w8, 0, vgx2], { z12.d, z13.d }, { z2.d, z3.d }"
+
+  -
+    input:
+      bytes: [ 0x19, 0x58, 0xfa, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w10, 1, vgx2], { z0.d, z1.d }, { z26.d, z27.d }"
+
+  -
+    input:
+      bytes: [ 0x19, 0x58, 0xfa, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w10, 1, vgx2], { z0.d, z1.d }, { z26.d, z27.d }"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x1a, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w8, 5, vgx2], { z22.d, z23.d }, { z30.d, z31.d }"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x1a, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w8, 5, vgx2], { z22.d, z23.d }, { z30.d, z31.d }"
+
+  -
+    input:
+      bytes: [ 0x1a, 0x79, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w11, 2, vgx2], { z8.d, z9.d }, { z0.d, z1.d }"
+
+  -
+    input:
+      bytes: [ 0x1a, 0x79, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w11, 2, vgx2], { z8.d, z9.d }, { z0.d, z1.d }"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x39, 0xea, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w9, 7, vgx2], { z12.d, z13.d }, { z10.d, z11.d }"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x39, 0xea, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w9, 7, vgx2], { z12.d, z13.d }, { z10.d, z11.d }"
+
+  -
+    input:
+      bytes: [ 0x18, 0x1c, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w8, 0, vgx4], { z0.s - z3.s }"
+
+  -
+    input:
+      bytes: [ 0x18, 0x1c, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w8, 0, vgx4], { z0.s - z3.s }"
+
+  -
+    input:
+      bytes: [ 0x1d, 0x5d, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w10, 5, vgx4], { z8.s - z11.s }"
+
+  -
+    input:
+      bytes: [ 0x1d, 0x5d, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w10, 5, vgx4], { z8.s - z11.s }"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x7d, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w11, 7, vgx4], { z12.s - z15.s }"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x7d, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w11, 7, vgx4], { z12.s - z15.s }"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x7f, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w11, 7, vgx4], { z28.s - z31.s }"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x7f, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w11, 7, vgx4], { z28.s - z31.s }"
+
+  -
+    input:
+      bytes: [ 0x1d, 0x1e, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w8, 5, vgx4], { z16.s - z19.s }"
+
+  -
+    input:
+      bytes: [ 0x1d, 0x1e, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w8, 5, vgx4], { z16.s - z19.s }"
+
+  -
+    input:
+      bytes: [ 0x19, 0x1c, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w8, 1, vgx4], { z0.s - z3.s }"
+
+  -
+    input:
+      bytes: [ 0x19, 0x1c, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w8, 1, vgx4], { z0.s - z3.s }"
+
+  -
+    input:
+      bytes: [ 0x18, 0x5e, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w10, 0, vgx4], { z16.s - z19.s }"
+
+  -
+    input:
+      bytes: [ 0x18, 0x5e, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w10, 0, vgx4], { z16.s - z19.s }"
+
+  -
+    input:
+      bytes: [ 0x98, 0x1d, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w8, 0, vgx4], { z12.s - z15.s }"
+
+  -
+    input:
+      bytes: [ 0x98, 0x1d, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w8, 0, vgx4], { z12.s - z15.s }"
+
+  -
+    input:
+      bytes: [ 0x19, 0x5c, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w10, 1, vgx4], { z0.s - z3.s }"
+
+  -
+    input:
+      bytes: [ 0x19, 0x5c, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w10, 1, vgx4], { z0.s - z3.s }"
+
+  -
+    input:
+      bytes: [ 0x9d, 0x1e, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w8, 5, vgx4], { z20.s - z23.s }"
+
+  -
+    input:
+      bytes: [ 0x9d, 0x1e, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w8, 5, vgx4], { z20.s - z23.s }"
+
+  -
+    input:
+      bytes: [ 0x1a, 0x7d, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w11, 2, vgx4], { z8.s - z11.s }"
+
+  -
+    input:
+      bytes: [ 0x1a, 0x7d, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w11, 2, vgx4], { z8.s - z11.s }"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x3d, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w9, 7, vgx4], { z12.s - z15.s }"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x3d, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w9, 7, vgx4], { z12.s - z15.s }"
+
+  -
+    input:
+      bytes: [ 0x18, 0x18, 0x30, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w8, 0, vgx4], { z0.s - z3.s }, z0.s"
+
+  -
+    input:
+      bytes: [ 0x18, 0x18, 0x30, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w8, 0, vgx4], { z0.s - z3.s }, z0.s"
+
+  -
+    input:
+      bytes: [ 0x5d, 0x59, 0x35, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w10, 5, vgx4], { z10.s - z13.s }, z5.s"
+
+  -
+    input:
+      bytes: [ 0x5d, 0x59, 0x35, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w10, 5, vgx4], { z10.s - z13.s }, z5.s"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x79, 0x38, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w11, 7, vgx4], { z13.s - z16.s }, z8.s"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x79, 0x38, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w11, 7, vgx4], { z13.s - z16.s }, z8.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0x7b, 0x3f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w11, 7, vgx4], { z31.s, z0.s, z1.s, z2.s }, z15.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0x7b, 0x3f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w11, 7, vgx4], { z31.s, z0.s, z1.s, z2.s }, z15.s"
+
+  -
+    input:
+      bytes: [ 0x3d, 0x1a, 0x30, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w8, 5, vgx4], { z17.s - z20.s }, z0.s"
+
+  -
+    input:
+      bytes: [ 0x3d, 0x1a, 0x30, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w8, 5, vgx4], { z17.s - z20.s }, z0.s"
+
+  -
+    input:
+      bytes: [ 0x39, 0x18, 0x3e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w8, 1, vgx4], { z1.s - z4.s }, z14.s"
+
+  -
+    input:
+      bytes: [ 0x39, 0x18, 0x3e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w8, 1, vgx4], { z1.s - z4.s }, z14.s"
+
+  -
+    input:
+      bytes: [ 0x78, 0x5a, 0x34, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w10, 0, vgx4], { z19.s - z22.s }, z4.s"
+
+  -
+    input:
+      bytes: [ 0x78, 0x5a, 0x34, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w10, 0, vgx4], { z19.s - z22.s }, z4.s"
+
+  -
+    input:
+      bytes: [ 0x98, 0x19, 0x32, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w8, 0, vgx4], { z12.s - z15.s }, z2.s"
+
+  -
+    input:
+      bytes: [ 0x98, 0x19, 0x32, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w8, 0, vgx4], { z12.s - z15.s }, z2.s"
+
+  -
+    input:
+      bytes: [ 0x39, 0x58, 0x3a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w10, 1, vgx4], { z1.s - z4.s }, z10.s"
+
+  -
+    input:
+      bytes: [ 0x39, 0x58, 0x3a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w10, 1, vgx4], { z1.s - z4.s }, z10.s"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x1a, 0x3e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w8, 5, vgx4], { z22.s - z25.s }, z14.s"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x1a, 0x3e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w8, 5, vgx4], { z22.s - z25.s }, z14.s"
+
+  -
+    input:
+      bytes: [ 0x3a, 0x79, 0x31, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w11, 2, vgx4], { z9.s - z12.s }, z1.s"
+
+  -
+    input:
+      bytes: [ 0x3a, 0x79, 0x31, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w11, 2, vgx4], { z9.s - z12.s }, z1.s"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x39, 0x3b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w9, 7, vgx4], { z12.s - z15.s }, z11.s"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x39, 0x3b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w9, 7, vgx4], { z12.s - z15.s }, z11.s"
+
+  -
+    input:
+      bytes: [ 0x18, 0x18, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w8, 0, vgx4], { z0.s - z3.s }, { z0.s - z3.s }"
+
+  -
+    input:
+      bytes: [ 0x18, 0x18, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w8, 0, vgx4], { z0.s - z3.s }, { z0.s - z3.s }"
+
+  -
+    input:
+      bytes: [ 0x1d, 0x59, 0xb5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w10, 5, vgx4], { z8.s - z11.s }, { z20.s - z23.s }"
+
+  -
+    input:
+      bytes: [ 0x1d, 0x59, 0xb5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w10, 5, vgx4], { z8.s - z11.s }, { z20.s - z23.s }"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x79, 0xa9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w11, 7, vgx4], { z12.s - z15.s }, { z8.s - z11.s }"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x79, 0xa9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w11, 7, vgx4], { z12.s - z15.s }, { z8.s - z11.s }"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x7b, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w11, 7, vgx4], { z28.s - z31.s }, { z28.s - z31.s }"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x7b, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w11, 7, vgx4], { z28.s - z31.s }, { z28.s - z31.s }"
+
+  -
+    input:
+      bytes: [ 0x1d, 0x1a, 0xb1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w8, 5, vgx4], { z16.s - z19.s }, { z16.s - z19.s }"
+
+  -
+    input:
+      bytes: [ 0x1d, 0x1a, 0xb1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w8, 5, vgx4], { z16.s - z19.s }, { z16.s - z19.s }"
+
+  -
+    input:
+      bytes: [ 0x19, 0x18, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w8, 1, vgx4], { z0.s - z3.s }, { z28.s - z31.s }"
+
+  -
+    input:
+      bytes: [ 0x19, 0x18, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w8, 1, vgx4], { z0.s - z3.s }, { z28.s - z31.s }"
+
+  -
+    input:
+      bytes: [ 0x18, 0x5a, 0xb5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w10, 0, vgx4], { z16.s - z19.s }, { z20.s - z23.s }"
+
+  -
+    input:
+      bytes: [ 0x18, 0x5a, 0xb5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w10, 0, vgx4], { z16.s - z19.s }, { z20.s - z23.s }"
+
+  -
+    input:
+      bytes: [ 0x98, 0x19, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w8, 0, vgx4], { z12.s - z15.s }, { z0.s - z3.s }"
+
+  -
+    input:
+      bytes: [ 0x98, 0x19, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w8, 0, vgx4], { z12.s - z15.s }, { z0.s - z3.s }"
+
+  -
+    input:
+      bytes: [ 0x19, 0x58, 0xb9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w10, 1, vgx4], { z0.s - z3.s }, { z24.s - z27.s }"
+
+  -
+    input:
+      bytes: [ 0x19, 0x58, 0xb9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w10, 1, vgx4], { z0.s - z3.s }, { z24.s - z27.s }"
+
+  -
+    input:
+      bytes: [ 0x9d, 0x1a, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w8, 5, vgx4], { z20.s - z23.s }, { z28.s - z31.s }"
+
+  -
+    input:
+      bytes: [ 0x9d, 0x1a, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w8, 5, vgx4], { z20.s - z23.s }, { z28.s - z31.s }"
+
+  -
+    input:
+      bytes: [ 0x1a, 0x79, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w11, 2, vgx4], { z8.s - z11.s }, { z0.s - z3.s }"
+
+  -
+    input:
+      bytes: [ 0x1a, 0x79, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w11, 2, vgx4], { z8.s - z11.s }, { z0.s - z3.s }"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x39, 0xa9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w9, 7, vgx4], { z12.s - z15.s }, { z8.s - z11.s }"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x39, 0xa9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.s[w9, 7, vgx4], { z12.s - z15.s }, { z8.s - z11.s }"
+
+  -
+    input:
+      bytes: [ 0x18, 0x1c, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w8, 0, vgx4], { z0.d - z3.d }"
+
+  -
+    input:
+      bytes: [ 0x18, 0x1c, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w8, 0, vgx4], { z0.d - z3.d }"
+
+  -
+    input:
+      bytes: [ 0x1d, 0x5d, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w10, 5, vgx4], { z8.d - z11.d }"
+
+  -
+    input:
+      bytes: [ 0x1d, 0x5d, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w10, 5, vgx4], { z8.d - z11.d }"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x7d, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w11, 7, vgx4], { z12.d - z15.d }"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x7d, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w11, 7, vgx4], { z12.d - z15.d }"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x7f, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w11, 7, vgx4], { z28.d - z31.d }"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x7f, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w11, 7, vgx4], { z28.d - z31.d }"
+
+  -
+    input:
+      bytes: [ 0x1d, 0x1e, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w8, 5, vgx4], { z16.d - z19.d }"
+
+  -
+    input:
+      bytes: [ 0x1d, 0x1e, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w8, 5, vgx4], { z16.d - z19.d }"
+
+  -
+    input:
+      bytes: [ 0x19, 0x1c, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w8, 1, vgx4], { z0.d - z3.d }"
+
+  -
+    input:
+      bytes: [ 0x19, 0x1c, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w8, 1, vgx4], { z0.d - z3.d }"
+
+  -
+    input:
+      bytes: [ 0x18, 0x5e, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w10, 0, vgx4], { z16.d - z19.d }"
+
+  -
+    input:
+      bytes: [ 0x18, 0x5e, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w10, 0, vgx4], { z16.d - z19.d }"
+
+  -
+    input:
+      bytes: [ 0x98, 0x1d, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w8, 0, vgx4], { z12.d - z15.d }"
+
+  -
+    input:
+      bytes: [ 0x98, 0x1d, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w8, 0, vgx4], { z12.d - z15.d }"
+
+  -
+    input:
+      bytes: [ 0x19, 0x5c, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w10, 1, vgx4], { z0.d - z3.d }"
+
+  -
+    input:
+      bytes: [ 0x19, 0x5c, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w10, 1, vgx4], { z0.d - z3.d }"
+
+  -
+    input:
+      bytes: [ 0x9d, 0x1e, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w8, 5, vgx4], { z20.d - z23.d }"
+
+  -
+    input:
+      bytes: [ 0x9d, 0x1e, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w8, 5, vgx4], { z20.d - z23.d }"
+
+  -
+    input:
+      bytes: [ 0x1a, 0x7d, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w11, 2, vgx4], { z8.d - z11.d }"
+
+  -
+    input:
+      bytes: [ 0x1a, 0x7d, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w11, 2, vgx4], { z8.d - z11.d }"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x3d, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w9, 7, vgx4], { z12.d - z15.d }"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x3d, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w9, 7, vgx4], { z12.d - z15.d }"
+
+  -
+    input:
+      bytes: [ 0x18, 0x18, 0x70, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w8, 0, vgx4], { z0.d - z3.d }, z0.d"
+
+  -
+    input:
+      bytes: [ 0x18, 0x18, 0x70, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w8, 0, vgx4], { z0.d - z3.d }, z0.d"
+
+  -
+    input:
+      bytes: [ 0x5d, 0x59, 0x75, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w10, 5, vgx4], { z10.d - z13.d }, z5.d"
+
+  -
+    input:
+      bytes: [ 0x5d, 0x59, 0x75, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w10, 5, vgx4], { z10.d - z13.d }, z5.d"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x79, 0x78, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w11, 7, vgx4], { z13.d - z16.d }, z8.d"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x79, 0x78, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w11, 7, vgx4], { z13.d - z16.d }, z8.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0x7b, 0x7f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w11, 7, vgx4], { z31.d, z0.d, z1.d, z2.d }, z15.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0x7b, 0x7f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w11, 7, vgx4], { z31.d, z0.d, z1.d, z2.d }, z15.d"
+
+  -
+    input:
+      bytes: [ 0x3d, 0x1a, 0x70, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w8, 5, vgx4], { z17.d - z20.d }, z0.d"
+
+  -
+    input:
+      bytes: [ 0x3d, 0x1a, 0x70, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w8, 5, vgx4], { z17.d - z20.d }, z0.d"
+
+  -
+    input:
+      bytes: [ 0x39, 0x18, 0x7e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w8, 1, vgx4], { z1.d - z4.d }, z14.d"
+
+  -
+    input:
+      bytes: [ 0x39, 0x18, 0x7e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w8, 1, vgx4], { z1.d - z4.d }, z14.d"
+
+  -
+    input:
+      bytes: [ 0x78, 0x5a, 0x74, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w10, 0, vgx4], { z19.d - z22.d }, z4.d"
+
+  -
+    input:
+      bytes: [ 0x78, 0x5a, 0x74, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w10, 0, vgx4], { z19.d - z22.d }, z4.d"
+
+  -
+    input:
+      bytes: [ 0x98, 0x19, 0x72, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w8, 0, vgx4], { z12.d - z15.d }, z2.d"
+
+  -
+    input:
+      bytes: [ 0x98, 0x19, 0x72, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w8, 0, vgx4], { z12.d - z15.d }, z2.d"
+
+  -
+    input:
+      bytes: [ 0x39, 0x58, 0x7a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w10, 1, vgx4], { z1.d - z4.d }, z10.d"
+
+  -
+    input:
+      bytes: [ 0x39, 0x58, 0x7a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w10, 1, vgx4], { z1.d - z4.d }, z10.d"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x1a, 0x7e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w8, 5, vgx4], { z22.d - z25.d }, z14.d"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x1a, 0x7e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w8, 5, vgx4], { z22.d - z25.d }, z14.d"
+
+  -
+    input:
+      bytes: [ 0x3a, 0x79, 0x71, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w11, 2, vgx4], { z9.d - z12.d }, z1.d"
+
+  -
+    input:
+      bytes: [ 0x3a, 0x79, 0x71, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w11, 2, vgx4], { z9.d - z12.d }, z1.d"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x39, 0x7b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w9, 7, vgx4], { z12.d - z15.d }, z11.d"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x39, 0x7b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w9, 7, vgx4], { z12.d - z15.d }, z11.d"
+
+  -
+    input:
+      bytes: [ 0x18, 0x18, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w8, 0, vgx4], { z0.d - z3.d }, { z0.d - z3.d }"
+
+  -
+    input:
+      bytes: [ 0x18, 0x18, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w8, 0, vgx4], { z0.d - z3.d }, { z0.d - z3.d }"
+
+  -
+    input:
+      bytes: [ 0x1d, 0x59, 0xf5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w10, 5, vgx4], { z8.d - z11.d }, { z20.d - z23.d }"
+
+  -
+    input:
+      bytes: [ 0x1d, 0x59, 0xf5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w10, 5, vgx4], { z8.d - z11.d }, { z20.d - z23.d }"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x79, 0xe9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w11, 7, vgx4], { z12.d - z15.d }, { z8.d - z11.d }"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x79, 0xe9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w11, 7, vgx4], { z12.d - z15.d }, { z8.d - z11.d }"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x7b, 0xfd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w11, 7, vgx4], { z28.d - z31.d }, { z28.d - z31.d }"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x7b, 0xfd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w11, 7, vgx4], { z28.d - z31.d }, { z28.d - z31.d }"
+
+  -
+    input:
+      bytes: [ 0x1d, 0x1a, 0xf1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w8, 5, vgx4], { z16.d - z19.d }, { z16.d - z19.d }"
+
+  -
+    input:
+      bytes: [ 0x1d, 0x1a, 0xf1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w8, 5, vgx4], { z16.d - z19.d }, { z16.d - z19.d }"
+
+  -
+    input:
+      bytes: [ 0x19, 0x18, 0xfd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w8, 1, vgx4], { z0.d - z3.d }, { z28.d - z31.d }"
+
+  -
+    input:
+      bytes: [ 0x19, 0x18, 0xfd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w8, 1, vgx4], { z0.d - z3.d }, { z28.d - z31.d }"
+
+  -
+    input:
+      bytes: [ 0x18, 0x5a, 0xf5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w10, 0, vgx4], { z16.d - z19.d }, { z20.d - z23.d }"
+
+  -
+    input:
+      bytes: [ 0x18, 0x5a, 0xf5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w10, 0, vgx4], { z16.d - z19.d }, { z20.d - z23.d }"
+
+  -
+    input:
+      bytes: [ 0x98, 0x19, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w8, 0, vgx4], { z12.d - z15.d }, { z0.d - z3.d }"
+
+  -
+    input:
+      bytes: [ 0x98, 0x19, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w8, 0, vgx4], { z12.d - z15.d }, { z0.d - z3.d }"
+
+  -
+    input:
+      bytes: [ 0x19, 0x58, 0xf9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w10, 1, vgx4], { z0.d - z3.d }, { z24.d - z27.d }"
+
+  -
+    input:
+      bytes: [ 0x19, 0x58, 0xf9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w10, 1, vgx4], { z0.d - z3.d }, { z24.d - z27.d }"
+
+  -
+    input:
+      bytes: [ 0x9d, 0x1a, 0xfd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w8, 5, vgx4], { z20.d - z23.d }, { z28.d - z31.d }"
+
+  -
+    input:
+      bytes: [ 0x9d, 0x1a, 0xfd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w8, 5, vgx4], { z20.d - z23.d }, { z28.d - z31.d }"
+
+  -
+    input:
+      bytes: [ 0x1a, 0x79, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w11, 2, vgx4], { z8.d - z11.d }, { z0.d - z3.d }"
+
+  -
+    input:
+      bytes: [ 0x1a, 0x79, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w11, 2, vgx4], { z8.d - z11.d }, { z0.d - z3.d }"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x39, 0xe9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w9, 7, vgx4], { z12.d - z15.d }, { z8.d - z11.d }"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x39, 0xe9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub za.d[w9, 7, vgx4], { z12.d - z15.d }, { z8.d - z11.d }"
diff --git a/tests/MC/AArch64/SME2/sudot.s.yaml b/tests/MC/AArch64/SME2/sudot.s.yaml
new file mode 100644
index 000000000..16a6ba80b
--- /dev/null
+++ b/tests/MC/AArch64/SME2/sudot.s.yaml
@@ -0,0 +1,960 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x18, 0x14, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sudot za.s[w8, 0, vgx2], { z0.b, z1.b }, z0.b"
+
+  -
+    input:
+      bytes: [ 0x18, 0x14, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sudot za.s[w8, 0, vgx2], { z0.b, z1.b }, z0.b"
+
+  -
+    input:
+      bytes: [ 0x5d, 0x55, 0x25, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sudot za.s[w10, 5, vgx2], { z10.b, z11.b }, z5.b"
+
+  -
+    input:
+      bytes: [ 0x5d, 0x55, 0x25, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sudot za.s[w10, 5, vgx2], { z10.b, z11.b }, z5.b"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x75, 0x28, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sudot za.s[w11, 7, vgx2], { z13.b, z14.b }, z8.b"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x75, 0x28, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sudot za.s[w11, 7, vgx2], { z13.b, z14.b }, z8.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x77, 0x2f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sudot za.s[w11, 7, vgx2], { z31.b, z0.b }, z15.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x77, 0x2f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sudot za.s[w11, 7, vgx2], { z31.b, z0.b }, z15.b"
+
+  -
+    input:
+      bytes: [ 0x3d, 0x16, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sudot za.s[w8, 5, vgx2], { z17.b, z18.b }, z0.b"
+
+  -
+    input:
+      bytes: [ 0x3d, 0x16, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sudot za.s[w8, 5, vgx2], { z17.b, z18.b }, z0.b"
+
+  -
+    input:
+      bytes: [ 0x39, 0x14, 0x2e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sudot za.s[w8, 1, vgx2], { z1.b, z2.b }, z14.b"
+
+  -
+    input:
+      bytes: [ 0x39, 0x14, 0x2e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sudot za.s[w8, 1, vgx2], { z1.b, z2.b }, z14.b"
+
+  -
+    input:
+      bytes: [ 0x78, 0x56, 0x24, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sudot za.s[w10, 0, vgx2], { z19.b, z20.b }, z4.b"
+
+  -
+    input:
+      bytes: [ 0x78, 0x56, 0x24, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sudot za.s[w10, 0, vgx2], { z19.b, z20.b }, z4.b"
+
+  -
+    input:
+      bytes: [ 0x98, 0x15, 0x22, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sudot za.s[w8, 0, vgx2], { z12.b, z13.b }, z2.b"
+
+  -
+    input:
+      bytes: [ 0x98, 0x15, 0x22, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sudot za.s[w8, 0, vgx2], { z12.b, z13.b }, z2.b"
+
+  -
+    input:
+      bytes: [ 0x39, 0x54, 0x2a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sudot za.s[w10, 1, vgx2], { z1.b, z2.b }, z10.b"
+
+  -
+    input:
+      bytes: [ 0x39, 0x54, 0x2a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sudot za.s[w10, 1, vgx2], { z1.b, z2.b }, z10.b"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x16, 0x2e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sudot za.s[w8, 5, vgx2], { z22.b, z23.b }, z14.b"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x16, 0x2e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sudot za.s[w8, 5, vgx2], { z22.b, z23.b }, z14.b"
+
+  -
+    input:
+      bytes: [ 0x3a, 0x75, 0x21, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sudot za.s[w11, 2, vgx2], { z9.b, z10.b }, z1.b"
+
+  -
+    input:
+      bytes: [ 0x3a, 0x75, 0x21, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sudot za.s[w11, 2, vgx2], { z9.b, z10.b }, z1.b"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x35, 0x2b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sudot za.s[w9, 7, vgx2], { z12.b, z13.b }, z11.b"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x35, 0x2b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sudot za.s[w9, 7, vgx2], { z12.b, z13.b }, z11.b"
+
+  -
+    input:
+      bytes: [ 0x38, 0x10, 0x50, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sudot za.s[w8, 0, vgx2], { z0.b, z1.b }, z0.b[0]"
+
+  -
+    input:
+      bytes: [ 0x38, 0x10, 0x50, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sudot za.s[w8, 0, vgx2], { z0.b, z1.b }, z0.b[0]"
+
+  -
+    input:
+      bytes: [ 0x7d, 0x55, 0x55, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sudot za.s[w10, 5, vgx2], { z10.b, z11.b }, z5.b[1]"
+
+  -
+    input:
+      bytes: [ 0x7d, 0x55, 0x55, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sudot za.s[w10, 5, vgx2], { z10.b, z11.b }, z5.b[1]"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x7d, 0x58, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sudot za.s[w11, 7, vgx2], { z12.b, z13.b }, z8.b[3]"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x7d, 0x58, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sudot za.s[w11, 7, vgx2], { z12.b, z13.b }, z8.b[3]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x7f, 0x5f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sudot za.s[w11, 7, vgx2], { z30.b, z31.b }, z15.b[3]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x7f, 0x5f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sudot za.s[w11, 7, vgx2], { z30.b, z31.b }, z15.b[3]"
+
+  -
+    input:
+      bytes: [ 0x3d, 0x1e, 0x50, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sudot za.s[w8, 5, vgx2], { z16.b, z17.b }, z0.b[3]"
+
+  -
+    input:
+      bytes: [ 0x3d, 0x1e, 0x50, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sudot za.s[w8, 5, vgx2], { z16.b, z17.b }, z0.b[3]"
+
+  -
+    input:
+      bytes: [ 0x39, 0x14, 0x5e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sudot za.s[w8, 1, vgx2], { z0.b, z1.b }, z14.b[1]"
+
+  -
+    input:
+      bytes: [ 0x39, 0x14, 0x5e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sudot za.s[w8, 1, vgx2], { z0.b, z1.b }, z14.b[1]"
+
+  -
+    input:
+      bytes: [ 0x78, 0x56, 0x54, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sudot za.s[w10, 0, vgx2], { z18.b, z19.b }, z4.b[1]"
+
+  -
+    input:
+      bytes: [ 0x78, 0x56, 0x54, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sudot za.s[w10, 0, vgx2], { z18.b, z19.b }, z4.b[1]"
+
+  -
+    input:
+      bytes: [ 0xb8, 0x19, 0x52, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sudot za.s[w8, 0, vgx2], { z12.b, z13.b }, z2.b[2]"
+
+  -
+    input:
+      bytes: [ 0xb8, 0x19, 0x52, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sudot za.s[w8, 0, vgx2], { z12.b, z13.b }, z2.b[2]"
+
+  -
+    input:
+      bytes: [ 0x39, 0x58, 0x5a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sudot za.s[w10, 1, vgx2], { z0.b, z1.b }, z10.b[2]"
+
+  -
+    input:
+      bytes: [ 0x39, 0x58, 0x5a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sudot za.s[w10, 1, vgx2], { z0.b, z1.b }, z10.b[2]"
+
+  -
+    input:
+      bytes: [ 0xfd, 0x1a, 0x5e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sudot za.s[w8, 5, vgx2], { z22.b, z23.b }, z14.b[2]"
+
+  -
+    input:
+      bytes: [ 0xfd, 0x1a, 0x5e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sudot za.s[w8, 5, vgx2], { z22.b, z23.b }, z14.b[2]"
+
+  -
+    input:
+      bytes: [ 0x3a, 0x75, 0x51, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sudot za.s[w11, 2, vgx2], { z8.b, z9.b }, z1.b[1]"
+
+  -
+    input:
+      bytes: [ 0x3a, 0x75, 0x51, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sudot za.s[w11, 2, vgx2], { z8.b, z9.b }, z1.b[1]"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x39, 0x5b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sudot za.s[w9, 7, vgx2], { z12.b, z13.b }, z11.b[2]"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x39, 0x5b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sudot za.s[w9, 7, vgx2], { z12.b, z13.b }, z11.b[2]"
+
+  -
+    input:
+      bytes: [ 0x18, 0x14, 0x30, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sudot za.s[w8, 0, vgx4], { z0.b - z3.b }, z0.b"
+
+  -
+    input:
+      bytes: [ 0x18, 0x14, 0x30, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sudot za.s[w8, 0, vgx4], { z0.b - z3.b }, z0.b"
+
+  -
+    input:
+      bytes: [ 0x5d, 0x55, 0x35, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sudot za.s[w10, 5, vgx4], { z10.b - z13.b }, z5.b"
+
+  -
+    input:
+      bytes: [ 0x5d, 0x55, 0x35, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sudot za.s[w10, 5, vgx4], { z10.b - z13.b }, z5.b"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x75, 0x38, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sudot za.s[w11, 7, vgx4], { z13.b - z16.b }, z8.b"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x75, 0x38, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sudot za.s[w11, 7, vgx4], { z13.b - z16.b }, z8.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x77, 0x3f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sudot za.s[w11, 7, vgx4], { z31.b, z0.b, z1.b, z2.b }, z15.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x77, 0x3f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sudot za.s[w11, 7, vgx4], { z31.b, z0.b, z1.b, z2.b }, z15.b"
+
+  -
+    input:
+      bytes: [ 0x3d, 0x16, 0x30, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sudot za.s[w8, 5, vgx4], { z17.b - z20.b }, z0.b"
+
+  -
+    input:
+      bytes: [ 0x3d, 0x16, 0x30, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sudot za.s[w8, 5, vgx4], { z17.b - z20.b }, z0.b"
+
+  -
+    input:
+      bytes: [ 0x39, 0x14, 0x3e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sudot za.s[w8, 1, vgx4], { z1.b - z4.b }, z14.b"
+
+  -
+    input:
+      bytes: [ 0x39, 0x14, 0x3e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sudot za.s[w8, 1, vgx4], { z1.b - z4.b }, z14.b"
+
+  -
+    input:
+      bytes: [ 0x78, 0x56, 0x34, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sudot za.s[w10, 0, vgx4], { z19.b - z22.b }, z4.b"
+
+  -
+    input:
+      bytes: [ 0x78, 0x56, 0x34, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sudot za.s[w10, 0, vgx4], { z19.b - z22.b }, z4.b"
+
+  -
+    input:
+      bytes: [ 0x98, 0x15, 0x32, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sudot za.s[w8, 0, vgx4], { z12.b - z15.b }, z2.b"
+
+  -
+    input:
+      bytes: [ 0x98, 0x15, 0x32, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sudot za.s[w8, 0, vgx4], { z12.b - z15.b }, z2.b"
+
+  -
+    input:
+      bytes: [ 0x39, 0x54, 0x3a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sudot za.s[w10, 1, vgx4], { z1.b - z4.b }, z10.b"
+
+  -
+    input:
+      bytes: [ 0x39, 0x54, 0x3a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sudot za.s[w10, 1, vgx4], { z1.b - z4.b }, z10.b"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x16, 0x3e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sudot za.s[w8, 5, vgx4], { z22.b - z25.b }, z14.b"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x16, 0x3e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sudot za.s[w8, 5, vgx4], { z22.b - z25.b }, z14.b"
+
+  -
+    input:
+      bytes: [ 0x3a, 0x75, 0x31, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sudot za.s[w11, 2, vgx4], { z9.b - z12.b }, z1.b"
+
+  -
+    input:
+      bytes: [ 0x3a, 0x75, 0x31, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sudot za.s[w11, 2, vgx4], { z9.b - z12.b }, z1.b"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x35, 0x3b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sudot za.s[w9, 7, vgx4], { z12.b - z15.b }, z11.b"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x35, 0x3b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sudot za.s[w9, 7, vgx4], { z12.b - z15.b }, z11.b"
+
+  -
+    input:
+      bytes: [ 0x38, 0x90, 0x50, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sudot za.s[w8, 0, vgx4], { z0.b - z3.b }, z0.b[0]"
+
+  -
+    input:
+      bytes: [ 0x38, 0x90, 0x50, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sudot za.s[w8, 0, vgx4], { z0.b - z3.b }, z0.b[0]"
+
+  -
+    input:
+      bytes: [ 0x3d, 0xd5, 0x55, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sudot za.s[w10, 5, vgx4], { z8.b - z11.b }, z5.b[1]"
+
+  -
+    input:
+      bytes: [ 0x3d, 0xd5, 0x55, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sudot za.s[w10, 5, vgx4], { z8.b - z11.b }, z5.b[1]"
+
+  -
+    input:
+      bytes: [ 0xbf, 0xfd, 0x58, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sudot za.s[w11, 7, vgx4], { z12.b - z15.b }, z8.b[3]"
+
+  -
+    input:
+      bytes: [ 0xbf, 0xfd, 0x58, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sudot za.s[w11, 7, vgx4], { z12.b - z15.b }, z8.b[3]"
+
+  -
+    input:
+      bytes: [ 0xbf, 0xff, 0x5f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sudot za.s[w11, 7, vgx4], { z28.b - z31.b }, z15.b[3]"
+
+  -
+    input:
+      bytes: [ 0xbf, 0xff, 0x5f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sudot za.s[w11, 7, vgx4], { z28.b - z31.b }, z15.b[3]"
+
+  -
+    input:
+      bytes: [ 0x3d, 0x9e, 0x50, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sudot za.s[w8, 5, vgx4], { z16.b - z19.b }, z0.b[3]"
+
+  -
+    input:
+      bytes: [ 0x3d, 0x9e, 0x50, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sudot za.s[w8, 5, vgx4], { z16.b - z19.b }, z0.b[3]"
+
+  -
+    input:
+      bytes: [ 0x39, 0x94, 0x5e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sudot za.s[w8, 1, vgx4], { z0.b - z3.b }, z14.b[1]"
+
+  -
+    input:
+      bytes: [ 0x39, 0x94, 0x5e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sudot za.s[w8, 1, vgx4], { z0.b - z3.b }, z14.b[1]"
+
+  -
+    input:
+      bytes: [ 0x38, 0xd6, 0x54, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sudot za.s[w10, 0, vgx4], { z16.b - z19.b }, z4.b[1]"
+
+  -
+    input:
+      bytes: [ 0x38, 0xd6, 0x54, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sudot za.s[w10, 0, vgx4], { z16.b - z19.b }, z4.b[1]"
+
+  -
+    input:
+      bytes: [ 0xb8, 0x99, 0x52, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sudot za.s[w8, 0, vgx4], { z12.b - z15.b }, z2.b[2]"
+
+  -
+    input:
+      bytes: [ 0xb8, 0x99, 0x52, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sudot za.s[w8, 0, vgx4], { z12.b - z15.b }, z2.b[2]"
+
+  -
+    input:
+      bytes: [ 0x39, 0xd8, 0x5a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sudot za.s[w10, 1, vgx4], { z0.b - z3.b }, z10.b[2]"
+
+  -
+    input:
+      bytes: [ 0x39, 0xd8, 0x5a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sudot za.s[w10, 1, vgx4], { z0.b - z3.b }, z10.b[2]"
+
+  -
+    input:
+      bytes: [ 0xbd, 0x9a, 0x5e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sudot za.s[w8, 5, vgx4], { z20.b - z23.b }, z14.b[2]"
+
+  -
+    input:
+      bytes: [ 0xbd, 0x9a, 0x5e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sudot za.s[w8, 5, vgx4], { z20.b - z23.b }, z14.b[2]"
+
+  -
+    input:
+      bytes: [ 0x3a, 0xf5, 0x51, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sudot za.s[w11, 2, vgx4], { z8.b - z11.b }, z1.b[1]"
+
+  -
+    input:
+      bytes: [ 0x3a, 0xf5, 0x51, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sudot za.s[w11, 2, vgx4], { z8.b - z11.b }, z1.b[1]"
+
+  -
+    input:
+      bytes: [ 0xbf, 0xb9, 0x5b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sudot za.s[w9, 7, vgx4], { z12.b - z15.b }, z11.b[2]"
+
+  -
+    input:
+      bytes: [ 0xbf, 0xb9, 0x5b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sudot za.s[w9, 7, vgx4], { z12.b - z15.b }, z11.b[2]"
diff --git a/tests/MC/AArch64/SME2/sumlall.s.yaml b/tests/MC/AArch64/SME2/sumlall.s.yaml
new file mode 100644
index 000000000..56dec7af9
--- /dev/null
+++ b/tests/MC/AArch64/SME2/sumlall.s.yaml
@@ -0,0 +1,1080 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x14, 0x00, 0x00, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumlall za.s[w8, 0:3], z0.b, z0.b[0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x55, 0x05, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumlall za.s[w10, 4:7], z10.b, z5.b[5]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0x08, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumlall za.s[w11, 12:15], z13.b, z8.b[11]"
+
+  -
+    input:
+      bytes: [ 0xf7, 0xff, 0x0f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumlall za.s[w11, 12:15], z31.b, z15.b[15]"
+
+  -
+    input:
+      bytes: [ 0x35, 0x0e, 0x00, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumlall za.s[w8, 4:7], z17.b, z0.b[3]"
+
+  -
+    input:
+      bytes: [ 0x35, 0x84, 0x0e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumlall za.s[w8, 4:7], z1.b, z14.b[9]"
+
+  -
+    input:
+      bytes: [ 0x74, 0x56, 0x04, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumlall za.s[w10, 0:3], z19.b, z4.b[5]"
+
+  -
+    input:
+      bytes: [ 0x94, 0x19, 0x02, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumlall za.s[w8, 0:3], z12.b, z2.b[6]"
+
+  -
+    input:
+      bytes: [ 0x35, 0xc8, 0x0a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumlall za.s[w10, 4:7], z1.b, z10.b[10]"
+
+  -
+    input:
+      bytes: [ 0xd5, 0x0a, 0x0e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumlall za.s[w8, 4:7], z22.b, z14.b[2]"
+
+  -
+    input:
+      bytes: [ 0x36, 0xf5, 0x01, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumlall za.s[w11, 8:11], z9.b, z1.b[13]"
+
+  -
+    input:
+      bytes: [ 0x97, 0xa9, 0x0b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumlall za.s[w9, 12:15], z12.b, z11.b[10]"
+
+  -
+    input:
+      bytes: [ 0x14, 0x00, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumlall za.s[w8, 0:3,  vgx2], { z0.b, z1.b }, z0.b"
+
+  -
+    input:
+      bytes: [ 0x14, 0x00, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumlall za.s[w8, 0:3,  vgx2], { z0.b, z1.b }, z0.b"
+
+  -
+    input:
+      bytes: [ 0x55, 0x41, 0x25, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumlall za.s[w10, 4:7,  vgx2], { z10.b, z11.b }, z5.b"
+
+  -
+    input:
+      bytes: [ 0x55, 0x41, 0x25, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumlall za.s[w10, 4:7,  vgx2], { z10.b, z11.b }, z5.b"
+
+  -
+    input:
+      bytes: [ 0xb5, 0x61, 0x28, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumlall za.s[w11, 4:7,  vgx2], { z13.b, z14.b }, z8.b"
+
+  -
+    input:
+      bytes: [ 0xb5, 0x61, 0x28, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumlall za.s[w11, 4:7,  vgx2], { z13.b, z14.b }, z8.b"
+
+  -
+    input:
+      bytes: [ 0xf5, 0x63, 0x2f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumlall za.s[w11, 4:7,  vgx2], { z31.b, z0.b }, z15.b"
+
+  -
+    input:
+      bytes: [ 0xf5, 0x63, 0x2f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumlall za.s[w11, 4:7,  vgx2], { z31.b, z0.b }, z15.b"
+
+  -
+    input:
+      bytes: [ 0x35, 0x02, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumlall za.s[w8, 4:7,  vgx2], { z17.b, z18.b }, z0.b"
+
+  -
+    input:
+      bytes: [ 0x35, 0x02, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumlall za.s[w8, 4:7,  vgx2], { z17.b, z18.b }, z0.b"
+
+  -
+    input:
+      bytes: [ 0x35, 0x00, 0x2e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumlall za.s[w8, 4:7,  vgx2], { z1.b, z2.b }, z14.b"
+
+  -
+    input:
+      bytes: [ 0x35, 0x00, 0x2e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumlall za.s[w8, 4:7,  vgx2], { z1.b, z2.b }, z14.b"
+
+  -
+    input:
+      bytes: [ 0x74, 0x42, 0x24, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumlall za.s[w10, 0:3,  vgx2], { z19.b, z20.b }, z4.b"
+
+  -
+    input:
+      bytes: [ 0x74, 0x42, 0x24, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumlall za.s[w10, 0:3,  vgx2], { z19.b, z20.b }, z4.b"
+
+  -
+    input:
+      bytes: [ 0x94, 0x01, 0x22, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumlall za.s[w8, 0:3,  vgx2], { z12.b, z13.b }, z2.b"
+
+  -
+    input:
+      bytes: [ 0x94, 0x01, 0x22, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumlall za.s[w8, 0:3,  vgx2], { z12.b, z13.b }, z2.b"
+
+  -
+    input:
+      bytes: [ 0x35, 0x40, 0x2a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumlall za.s[w10, 4:7,  vgx2], { z1.b, z2.b }, z10.b"
+
+  -
+    input:
+      bytes: [ 0x35, 0x40, 0x2a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumlall za.s[w10, 4:7,  vgx2], { z1.b, z2.b }, z10.b"
+
+  -
+    input:
+      bytes: [ 0xd5, 0x02, 0x2e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumlall za.s[w8, 4:7,  vgx2], { z22.b, z23.b }, z14.b"
+
+  -
+    input:
+      bytes: [ 0xd5, 0x02, 0x2e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumlall za.s[w8, 4:7,  vgx2], { z22.b, z23.b }, z14.b"
+
+  -
+    input:
+      bytes: [ 0x34, 0x61, 0x21, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumlall za.s[w11, 0:3,  vgx2], { z9.b, z10.b }, z1.b"
+
+  -
+    input:
+      bytes: [ 0x34, 0x61, 0x21, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumlall za.s[w11, 0:3,  vgx2], { z9.b, z10.b }, z1.b"
+
+  -
+    input:
+      bytes: [ 0x95, 0x21, 0x2b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumlall za.s[w9, 4:7,  vgx2], { z12.b, z13.b }, z11.b"
+
+  -
+    input:
+      bytes: [ 0x95, 0x21, 0x2b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumlall za.s[w9, 4:7,  vgx2], { z12.b, z13.b }, z11.b"
+
+  -
+    input:
+      bytes: [ 0x30, 0x00, 0x10, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumlall za.s[w8, 0:3, vgx2], { z0.b, z1.b }, z0.b[0]"
+
+  -
+    input:
+      bytes: [ 0x30, 0x00, 0x10, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumlall za.s[w8, 0:3, vgx2], { z0.b, z1.b }, z0.b[0]"
+
+  -
+    input:
+      bytes: [ 0x75, 0x45, 0x15, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumlall za.s[w10, 4:7, vgx2], { z10.b, z11.b }, z5.b[6]"
+
+  -
+    input:
+      bytes: [ 0x75, 0x45, 0x15, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumlall za.s[w10, 4:7, vgx2], { z10.b, z11.b }, z5.b[6]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x6d, 0x18, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumlall za.s[w11, 4:7, vgx2], { z12.b, z13.b }, z8.b[15]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x6d, 0x18, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumlall za.s[w11, 4:7, vgx2], { z12.b, z13.b }, z8.b[15]"
+
+  -
+    input:
+      bytes: [ 0xf7, 0x6f, 0x1f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumlall za.s[w11, 4:7, vgx2], { z30.b, z31.b }, z15.b[15]"
+
+  -
+    input:
+      bytes: [ 0xf7, 0x6f, 0x1f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumlall za.s[w11, 4:7, vgx2], { z30.b, z31.b }, z15.b[15]"
+
+  -
+    input:
+      bytes: [ 0x35, 0x0e, 0x10, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumlall za.s[w8, 4:7, vgx2], { z16.b, z17.b }, z0.b[14]"
+
+  -
+    input:
+      bytes: [ 0x35, 0x0e, 0x10, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumlall za.s[w8, 4:7, vgx2], { z16.b, z17.b }, z0.b[14]"
+
+  -
+    input:
+      bytes: [ 0x31, 0x04, 0x1e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumlall za.s[w8, 4:7, vgx2], { z0.b, z1.b }, z14.b[4]"
+
+  -
+    input:
+      bytes: [ 0x31, 0x04, 0x1e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumlall za.s[w8, 4:7, vgx2], { z0.b, z1.b }, z14.b[4]"
+
+  -
+    input:
+      bytes: [ 0x70, 0x46, 0x14, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumlall za.s[w10, 0:3, vgx2], { z18.b, z19.b }, z4.b[4]"
+
+  -
+    input:
+      bytes: [ 0x70, 0x46, 0x14, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumlall za.s[w10, 0:3, vgx2], { z18.b, z19.b }, z4.b[4]"
+
+  -
+    input:
+      bytes: [ 0xb0, 0x09, 0x12, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumlall za.s[w8, 0:3, vgx2], { z12.b, z13.b }, z2.b[8]"
+
+  -
+    input:
+      bytes: [ 0xb0, 0x09, 0x12, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumlall za.s[w8, 0:3, vgx2], { z12.b, z13.b }, z2.b[8]"
+
+  -
+    input:
+      bytes: [ 0x31, 0x48, 0x1a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumlall za.s[w10, 4:7, vgx2], { z0.b, z1.b }, z10.b[8]"
+
+  -
+    input:
+      bytes: [ 0x31, 0x48, 0x1a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumlall za.s[w10, 4:7, vgx2], { z0.b, z1.b }, z10.b[8]"
+
+  -
+    input:
+      bytes: [ 0xf5, 0x0a, 0x1e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumlall za.s[w8, 4:7, vgx2], { z22.b, z23.b }, z14.b[10]"
+
+  -
+    input:
+      bytes: [ 0xf5, 0x0a, 0x1e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumlall za.s[w8, 4:7, vgx2], { z22.b, z23.b }, z14.b[10]"
+
+  -
+    input:
+      bytes: [ 0x32, 0x65, 0x11, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumlall za.s[w11, 0:3, vgx2], { z8.b, z9.b }, z1.b[5]"
+
+  -
+    input:
+      bytes: [ 0x32, 0x65, 0x11, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumlall za.s[w11, 0:3, vgx2], { z8.b, z9.b }, z1.b[5]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x29, 0x1b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumlall za.s[w9, 4:7, vgx2], { z12.b, z13.b }, z11.b[11]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x29, 0x1b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumlall za.s[w9, 4:7, vgx2], { z12.b, z13.b }, z11.b[11]"
+
+  -
+    input:
+      bytes: [ 0x14, 0x00, 0x30, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumlall za.s[w8, 0:3,  vgx4], { z0.b - z3.b }, z0.b"
+
+  -
+    input:
+      bytes: [ 0x14, 0x00, 0x30, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumlall za.s[w8, 0:3,  vgx4], { z0.b - z3.b }, z0.b"
+
+  -
+    input:
+      bytes: [ 0x55, 0x41, 0x35, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumlall za.s[w10, 4:7,  vgx4], { z10.b - z13.b }, z5.b"
+
+  -
+    input:
+      bytes: [ 0x55, 0x41, 0x35, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumlall za.s[w10, 4:7,  vgx4], { z10.b - z13.b }, z5.b"
+
+  -
+    input:
+      bytes: [ 0xb5, 0x61, 0x38, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumlall za.s[w11, 4:7,  vgx4], { z13.b - z16.b }, z8.b"
+
+  -
+    input:
+      bytes: [ 0xb5, 0x61, 0x38, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumlall za.s[w11, 4:7,  vgx4], { z13.b - z16.b }, z8.b"
+
+  -
+    input:
+      bytes: [ 0xf5, 0x63, 0x3f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumlall za.s[w11, 4:7,  vgx4], { z31.b, z0.b, z1.b, z2.b }, z15.b"
+
+  -
+    input:
+      bytes: [ 0xf5, 0x63, 0x3f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumlall za.s[w11, 4:7,  vgx4], { z31.b, z0.b, z1.b, z2.b }, z15.b"
+
+  -
+    input:
+      bytes: [ 0x35, 0x02, 0x30, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumlall za.s[w8, 4:7,  vgx4], { z17.b - z20.b }, z0.b"
+
+  -
+    input:
+      bytes: [ 0x35, 0x02, 0x30, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumlall za.s[w8, 4:7,  vgx4], { z17.b - z20.b }, z0.b"
+
+  -
+    input:
+      bytes: [ 0x35, 0x00, 0x3e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumlall za.s[w8, 4:7,  vgx4], { z1.b - z4.b }, z14.b"
+
+  -
+    input:
+      bytes: [ 0x35, 0x00, 0x3e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumlall za.s[w8, 4:7,  vgx4], { z1.b - z4.b }, z14.b"
+
+  -
+    input:
+      bytes: [ 0x74, 0x42, 0x34, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumlall za.s[w10, 0:3,  vgx4], { z19.b - z22.b }, z4.b"
+
+  -
+    input:
+      bytes: [ 0x74, 0x42, 0x34, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumlall za.s[w10, 0:3,  vgx4], { z19.b - z22.b }, z4.b"
+
+  -
+    input:
+      bytes: [ 0x94, 0x01, 0x32, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumlall za.s[w8, 0:3,  vgx4], { z12.b - z15.b }, z2.b"
+
+  -
+    input:
+      bytes: [ 0x94, 0x01, 0x32, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumlall za.s[w8, 0:3,  vgx4], { z12.b - z15.b }, z2.b"
+
+  -
+    input:
+      bytes: [ 0x35, 0x40, 0x3a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumlall za.s[w10, 4:7,  vgx4], { z1.b - z4.b }, z10.b"
+
+  -
+    input:
+      bytes: [ 0x35, 0x40, 0x3a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumlall za.s[w10, 4:7,  vgx4], { z1.b - z4.b }, z10.b"
+
+  -
+    input:
+      bytes: [ 0xd5, 0x02, 0x3e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumlall za.s[w8, 4:7,  vgx4], { z22.b - z25.b }, z14.b"
+
+  -
+    input:
+      bytes: [ 0xd5, 0x02, 0x3e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumlall za.s[w8, 4:7,  vgx4], { z22.b - z25.b }, z14.b"
+
+  -
+    input:
+      bytes: [ 0x34, 0x61, 0x31, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumlall za.s[w11, 0:3,  vgx4], { z9.b - z12.b }, z1.b"
+
+  -
+    input:
+      bytes: [ 0x34, 0x61, 0x31, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumlall za.s[w11, 0:3,  vgx4], { z9.b - z12.b }, z1.b"
+
+  -
+    input:
+      bytes: [ 0x95, 0x21, 0x3b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumlall za.s[w9, 4:7,  vgx4], { z12.b - z15.b }, z11.b"
+
+  -
+    input:
+      bytes: [ 0x95, 0x21, 0x3b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumlall za.s[w9, 4:7,  vgx4], { z12.b - z15.b }, z11.b"
+
+  -
+    input:
+      bytes: [ 0x30, 0x80, 0x10, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumlall za.s[w8, 0:3, vgx4], { z0.b - z3.b }, z0.b[0]"
+
+  -
+    input:
+      bytes: [ 0x30, 0x80, 0x10, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumlall za.s[w8, 0:3, vgx4], { z0.b - z3.b }, z0.b[0]"
+
+  -
+    input:
+      bytes: [ 0x35, 0xc5, 0x15, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumlall za.s[w10, 4:7, vgx4], { z8.b - z11.b }, z5.b[6]"
+
+  -
+    input:
+      bytes: [ 0x35, 0xc5, 0x15, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumlall za.s[w10, 4:7, vgx4], { z8.b - z11.b }, z5.b[6]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0x18, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumlall za.s[w11, 4:7, vgx4], { z12.b - z15.b }, z8.b[15]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0x18, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumlall za.s[w11, 4:7, vgx4], { z12.b - z15.b }, z8.b[15]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xef, 0x1f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumlall za.s[w11, 4:7, vgx4], { z28.b - z31.b }, z15.b[15]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xef, 0x1f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumlall za.s[w11, 4:7, vgx4], { z28.b - z31.b }, z15.b[15]"
+
+  -
+    input:
+      bytes: [ 0x35, 0x8e, 0x10, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumlall za.s[w8, 4:7, vgx4], { z16.b - z19.b }, z0.b[14]"
+
+  -
+    input:
+      bytes: [ 0x35, 0x8e, 0x10, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumlall za.s[w8, 4:7, vgx4], { z16.b - z19.b }, z0.b[14]"
+
+  -
+    input:
+      bytes: [ 0x31, 0x84, 0x1e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumlall za.s[w8, 4:7, vgx4], { z0.b - z3.b }, z14.b[4]"
+
+  -
+    input:
+      bytes: [ 0x31, 0x84, 0x1e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumlall za.s[w8, 4:7, vgx4], { z0.b - z3.b }, z14.b[4]"
+
+  -
+    input:
+      bytes: [ 0x30, 0xc6, 0x14, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumlall za.s[w10, 0:3, vgx4], { z16.b - z19.b }, z4.b[4]"
+
+  -
+    input:
+      bytes: [ 0x30, 0xc6, 0x14, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumlall za.s[w10, 0:3, vgx4], { z16.b - z19.b }, z4.b[4]"
+
+  -
+    input:
+      bytes: [ 0xb0, 0x89, 0x12, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumlall za.s[w8, 0:3, vgx4], { z12.b - z15.b }, z2.b[8]"
+
+  -
+    input:
+      bytes: [ 0xb0, 0x89, 0x12, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumlall za.s[w8, 0:3, vgx4], { z12.b - z15.b }, z2.b[8]"
+
+  -
+    input:
+      bytes: [ 0x31, 0xc8, 0x1a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumlall za.s[w10, 4:7, vgx4], { z0.b - z3.b }, z10.b[8]"
+
+  -
+    input:
+      bytes: [ 0x31, 0xc8, 0x1a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumlall za.s[w10, 4:7, vgx4], { z0.b - z3.b }, z10.b[8]"
+
+  -
+    input:
+      bytes: [ 0xb5, 0x8a, 0x1e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumlall za.s[w8, 4:7, vgx4], { z20.b - z23.b }, z14.b[10]"
+
+  -
+    input:
+      bytes: [ 0xb5, 0x8a, 0x1e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumlall za.s[w8, 4:7, vgx4], { z20.b - z23.b }, z14.b[10]"
+
+  -
+    input:
+      bytes: [ 0x32, 0xe5, 0x11, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumlall za.s[w11, 0:3, vgx4], { z8.b - z11.b }, z1.b[5]"
+
+  -
+    input:
+      bytes: [ 0x32, 0xe5, 0x11, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumlall za.s[w11, 0:3, vgx4], { z8.b - z11.b }, z1.b[5]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xa9, 0x1b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumlall za.s[w9, 4:7, vgx4], { z12.b - z15.b }, z11.b[11]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xa9, 0x1b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sumlall za.s[w9, 4:7, vgx4], { z12.b - z15.b }, z11.b[11]"
diff --git a/tests/MC/AArch64/SME2/sunpk.s.yaml b/tests/MC/AArch64/SME2/sunpk.s.yaml
new file mode 100644
index 000000000..0cb656eeb
--- /dev/null
+++ b/tests/MC/AArch64/SME2/sunpk.s.yaml
@@ -0,0 +1,240 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x65, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sunpk { z0.h, z1.h }, z0.b"
+
+  -
+    input:
+      bytes: [ 0x54, 0xe1, 0x65, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sunpk { z20.h, z21.h }, z10.b"
+
+  -
+    input:
+      bytes: [ 0xb6, 0xe1, 0x65, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sunpk { z22.h, z23.h }, z13.b"
+
+  -
+    input:
+      bytes: [ 0xfe, 0xe3, 0x65, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sunpk { z30.h, z31.h }, z31.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xa5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sunpk { z0.s, z1.s }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x54, 0xe1, 0xa5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sunpk { z20.s, z21.s }, z10.h"
+
+  -
+    input:
+      bytes: [ 0xb6, 0xe1, 0xa5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sunpk { z22.s, z23.s }, z13.h"
+
+  -
+    input:
+      bytes: [ 0xfe, 0xe3, 0xa5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sunpk { z30.s, z31.s }, z31.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xe5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sunpk { z0.d, z1.d }, z0.s"
+
+  -
+    input:
+      bytes: [ 0x54, 0xe1, 0xe5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sunpk { z20.d, z21.d }, z10.s"
+
+  -
+    input:
+      bytes: [ 0xb6, 0xe1, 0xe5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sunpk { z22.d, z23.d }, z13.s"
+
+  -
+    input:
+      bytes: [ 0xfe, 0xe3, 0xe5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sunpk { z30.d, z31.d }, z31.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x75, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sunpk { z0.h - z3.h }, { z0.b, z1.b }"
+
+  -
+    input:
+      bytes: [ 0x54, 0xe1, 0x75, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sunpk { z20.h - z23.h }, { z10.b, z11.b }"
+
+  -
+    input:
+      bytes: [ 0x94, 0xe1, 0x75, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sunpk { z20.h - z23.h }, { z12.b, z13.b }"
+
+  -
+    input:
+      bytes: [ 0xdc, 0xe3, 0x75, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sunpk { z28.h - z31.h }, { z30.b, z31.b }"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xb5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sunpk { z0.s - z3.s }, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x54, 0xe1, 0xb5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sunpk { z20.s - z23.s }, { z10.h, z11.h }"
+
+  -
+    input:
+      bytes: [ 0x94, 0xe1, 0xb5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sunpk { z20.s - z23.s }, { z12.h, z13.h }"
+
+  -
+    input:
+      bytes: [ 0xdc, 0xe3, 0xb5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sunpk { z28.s - z31.s }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xf5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sunpk { z0.d - z3.d }, { z0.s, z1.s }"
+
+  -
+    input:
+      bytes: [ 0x54, 0xe1, 0xf5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sunpk { z20.d - z23.d }, { z10.s, z11.s }"
+
+  -
+    input:
+      bytes: [ 0x94, 0xe1, 0xf5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sunpk { z20.d - z23.d }, { z12.s, z13.s }"
+
+  -
+    input:
+      bytes: [ 0xdc, 0xe3, 0xf5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sunpk { z28.d - z31.d }, { z30.s, z31.s }"
diff --git a/tests/MC/AArch64/SME2/suvdot.s.yaml b/tests/MC/AArch64/SME2/suvdot.s.yaml
new file mode 100644
index 000000000..f3170acf8
--- /dev/null
+++ b/tests/MC/AArch64/SME2/suvdot.s.yaml
@@ -0,0 +1,240 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x38, 0x80, 0x50, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "suvdot za.s[w8, 0, vgx4], { z0.b - z3.b }, z0.b[0]"
+
+  -
+    input:
+      bytes: [ 0x38, 0x80, 0x50, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "suvdot za.s[w8, 0, vgx4], { z0.b - z3.b }, z0.b[0]"
+
+  -
+    input:
+      bytes: [ 0x3d, 0xc5, 0x55, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "suvdot za.s[w10, 5, vgx4], { z8.b - z11.b }, z5.b[1]"
+
+  -
+    input:
+      bytes: [ 0x3d, 0xc5, 0x55, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "suvdot za.s[w10, 5, vgx4], { z8.b - z11.b }, z5.b[1]"
+
+  -
+    input:
+      bytes: [ 0xbf, 0xed, 0x58, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "suvdot za.s[w11, 7, vgx4], { z12.b - z15.b }, z8.b[3]"
+
+  -
+    input:
+      bytes: [ 0xbf, 0xed, 0x58, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "suvdot za.s[w11, 7, vgx4], { z12.b - z15.b }, z8.b[3]"
+
+  -
+    input:
+      bytes: [ 0xbf, 0xef, 0x5f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "suvdot za.s[w11, 7, vgx4], { z28.b - z31.b }, z15.b[3]"
+
+  -
+    input:
+      bytes: [ 0xbf, 0xef, 0x5f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "suvdot za.s[w11, 7, vgx4], { z28.b - z31.b }, z15.b[3]"
+
+  -
+    input:
+      bytes: [ 0x3d, 0x8e, 0x50, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "suvdot za.s[w8, 5, vgx4], { z16.b - z19.b }, z0.b[3]"
+
+  -
+    input:
+      bytes: [ 0x3d, 0x8e, 0x50, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "suvdot za.s[w8, 5, vgx4], { z16.b - z19.b }, z0.b[3]"
+
+  -
+    input:
+      bytes: [ 0x39, 0x84, 0x5e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "suvdot za.s[w8, 1, vgx4], { z0.b - z3.b }, z14.b[1]"
+
+  -
+    input:
+      bytes: [ 0x39, 0x84, 0x5e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "suvdot za.s[w8, 1, vgx4], { z0.b - z3.b }, z14.b[1]"
+
+  -
+    input:
+      bytes: [ 0x38, 0xc6, 0x54, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "suvdot za.s[w10, 0, vgx4], { z16.b - z19.b }, z4.b[1]"
+
+  -
+    input:
+      bytes: [ 0x38, 0xc6, 0x54, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "suvdot za.s[w10, 0, vgx4], { z16.b - z19.b }, z4.b[1]"
+
+  -
+    input:
+      bytes: [ 0xb8, 0x89, 0x52, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "suvdot za.s[w8, 0, vgx4], { z12.b - z15.b }, z2.b[2]"
+
+  -
+    input:
+      bytes: [ 0xb8, 0x89, 0x52, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "suvdot za.s[w8, 0, vgx4], { z12.b - z15.b }, z2.b[2]"
+
+  -
+    input:
+      bytes: [ 0x39, 0xc8, 0x5a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "suvdot za.s[w10, 1, vgx4], { z0.b - z3.b }, z10.b[2]"
+
+  -
+    input:
+      bytes: [ 0x39, 0xc8, 0x5a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "suvdot za.s[w10, 1, vgx4], { z0.b - z3.b }, z10.b[2]"
+
+  -
+    input:
+      bytes: [ 0xbd, 0x8a, 0x5e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "suvdot za.s[w8, 5, vgx4], { z20.b - z23.b }, z14.b[2]"
+
+  -
+    input:
+      bytes: [ 0xbd, 0x8a, 0x5e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "suvdot za.s[w8, 5, vgx4], { z20.b - z23.b }, z14.b[2]"
+
+  -
+    input:
+      bytes: [ 0x3a, 0xe5, 0x51, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "suvdot za.s[w11, 2, vgx4], { z8.b - z11.b }, z1.b[1]"
+
+  -
+    input:
+      bytes: [ 0x3a, 0xe5, 0x51, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "suvdot za.s[w11, 2, vgx4], { z8.b - z11.b }, z1.b[1]"
+
+  -
+    input:
+      bytes: [ 0xbf, 0xa9, 0x5b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "suvdot za.s[w9, 7, vgx4], { z12.b - z15.b }, z11.b[2]"
+
+  -
+    input:
+      bytes: [ 0xbf, 0xa9, 0x5b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "suvdot za.s[w9, 7, vgx4], { z12.b - z15.b }, z11.b[2]"
diff --git a/tests/MC/AArch64/SME2/svdot.s.yaml b/tests/MC/AArch64/SME2/svdot.s.yaml
new file mode 100644
index 000000000..0dec64a3f
--- /dev/null
+++ b/tests/MC/AArch64/SME2/svdot.s.yaml
@@ -0,0 +1,720 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x00, 0x50, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "svdot za.s[w8, 0, vgx2], { z0.h, z1.h }, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x00, 0x50, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "svdot za.s[w8, 0, vgx2], { z0.h, z1.h }, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x65, 0x45, 0x55, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "svdot za.s[w10, 5, vgx2], { z10.h, z11.h }, z5.h[1]"
+
+  -
+    input:
+      bytes: [ 0x65, 0x45, 0x55, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "svdot za.s[w10, 5, vgx2], { z10.h, z11.h }, z5.h[1]"
+
+  -
+    input:
+      bytes: [ 0xa7, 0x6d, 0x58, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "svdot za.s[w11, 7, vgx2], { z12.h, z13.h }, z8.h[3]"
+
+  -
+    input:
+      bytes: [ 0xa7, 0x6d, 0x58, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "svdot za.s[w11, 7, vgx2], { z12.h, z13.h }, z8.h[3]"
+
+  -
+    input:
+      bytes: [ 0xe7, 0x6f, 0x5f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "svdot za.s[w11, 7, vgx2], { z30.h, z31.h }, z15.h[3]"
+
+  -
+    input:
+      bytes: [ 0xe7, 0x6f, 0x5f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "svdot za.s[w11, 7, vgx2], { z30.h, z31.h }, z15.h[3]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x0e, 0x50, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "svdot za.s[w8, 5, vgx2], { z16.h, z17.h }, z0.h[3]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x0e, 0x50, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "svdot za.s[w8, 5, vgx2], { z16.h, z17.h }, z0.h[3]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x04, 0x5e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "svdot za.s[w8, 1, vgx2], { z0.h, z1.h }, z14.h[1]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x04, 0x5e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "svdot za.s[w8, 1, vgx2], { z0.h, z1.h }, z14.h[1]"
+
+  -
+    input:
+      bytes: [ 0x60, 0x46, 0x54, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "svdot za.s[w10, 0, vgx2], { z18.h, z19.h }, z4.h[1]"
+
+  -
+    input:
+      bytes: [ 0x60, 0x46, 0x54, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "svdot za.s[w10, 0, vgx2], { z18.h, z19.h }, z4.h[1]"
+
+  -
+    input:
+      bytes: [ 0xa0, 0x09, 0x52, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "svdot za.s[w8, 0, vgx2], { z12.h, z13.h }, z2.h[2]"
+
+  -
+    input:
+      bytes: [ 0xa0, 0x09, 0x52, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "svdot za.s[w8, 0, vgx2], { z12.h, z13.h }, z2.h[2]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x48, 0x5a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "svdot za.s[w10, 1, vgx2], { z0.h, z1.h }, z10.h[2]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x48, 0x5a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "svdot za.s[w10, 1, vgx2], { z0.h, z1.h }, z10.h[2]"
+
+  -
+    input:
+      bytes: [ 0xe5, 0x0a, 0x5e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "svdot za.s[w8, 5, vgx2], { z22.h, z23.h }, z14.h[2]"
+
+  -
+    input:
+      bytes: [ 0xe5, 0x0a, 0x5e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "svdot za.s[w8, 5, vgx2], { z22.h, z23.h }, z14.h[2]"
+
+  -
+    input:
+      bytes: [ 0x22, 0x65, 0x51, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "svdot za.s[w11, 2, vgx2], { z8.h, z9.h }, z1.h[1]"
+
+  -
+    input:
+      bytes: [ 0x22, 0x65, 0x51, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "svdot za.s[w11, 2, vgx2], { z8.h, z9.h }, z1.h[1]"
+
+  -
+    input:
+      bytes: [ 0xa7, 0x29, 0x5b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "svdot za.s[w9, 7, vgx2], { z12.h, z13.h }, z11.h[2]"
+
+  -
+    input:
+      bytes: [ 0xa7, 0x29, 0x5b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "svdot za.s[w9, 7, vgx2], { z12.h, z13.h }, z11.h[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x50, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "svdot za.s[w8, 0, vgx4], { z0.b - z3.b }, z0.b[0]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x50, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "svdot za.s[w8, 0, vgx4], { z0.b - z3.b }, z0.b[0]"
+
+  -
+    input:
+      bytes: [ 0x25, 0xc5, 0x55, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "svdot za.s[w10, 5, vgx4], { z8.b - z11.b }, z5.b[1]"
+
+  -
+    input:
+      bytes: [ 0x25, 0xc5, 0x55, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "svdot za.s[w10, 5, vgx4], { z8.b - z11.b }, z5.b[1]"
+
+  -
+    input:
+      bytes: [ 0xa7, 0xed, 0x58, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "svdot za.s[w11, 7, vgx4], { z12.b - z15.b }, z8.b[3]"
+
+  -
+    input:
+      bytes: [ 0xa7, 0xed, 0x58, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "svdot za.s[w11, 7, vgx4], { z12.b - z15.b }, z8.b[3]"
+
+  -
+    input:
+      bytes: [ 0xa7, 0xef, 0x5f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "svdot za.s[w11, 7, vgx4], { z28.b - z31.b }, z15.b[3]"
+
+  -
+    input:
+      bytes: [ 0xa7, 0xef, 0x5f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "svdot za.s[w11, 7, vgx4], { z28.b - z31.b }, z15.b[3]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x8e, 0x50, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "svdot za.s[w8, 5, vgx4], { z16.b - z19.b }, z0.b[3]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x8e, 0x50, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "svdot za.s[w8, 5, vgx4], { z16.b - z19.b }, z0.b[3]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x84, 0x5e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "svdot za.s[w8, 1, vgx4], { z0.b - z3.b }, z14.b[1]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x84, 0x5e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "svdot za.s[w8, 1, vgx4], { z0.b - z3.b }, z14.b[1]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc6, 0x54, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "svdot za.s[w10, 0, vgx4], { z16.b - z19.b }, z4.b[1]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc6, 0x54, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "svdot za.s[w10, 0, vgx4], { z16.b - z19.b }, z4.b[1]"
+
+  -
+    input:
+      bytes: [ 0xa0, 0x89, 0x52, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "svdot za.s[w8, 0, vgx4], { z12.b - z15.b }, z2.b[2]"
+
+  -
+    input:
+      bytes: [ 0xa0, 0x89, 0x52, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "svdot za.s[w8, 0, vgx4], { z12.b - z15.b }, z2.b[2]"
+
+  -
+    input:
+      bytes: [ 0x21, 0xc8, 0x5a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "svdot za.s[w10, 1, vgx4], { z0.b - z3.b }, z10.b[2]"
+
+  -
+    input:
+      bytes: [ 0x21, 0xc8, 0x5a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "svdot za.s[w10, 1, vgx4], { z0.b - z3.b }, z10.b[2]"
+
+  -
+    input:
+      bytes: [ 0xa5, 0x8a, 0x5e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "svdot za.s[w8, 5, vgx4], { z20.b - z23.b }, z14.b[2]"
+
+  -
+    input:
+      bytes: [ 0xa5, 0x8a, 0x5e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "svdot za.s[w8, 5, vgx4], { z20.b - z23.b }, z14.b[2]"
+
+  -
+    input:
+      bytes: [ 0x22, 0xe5, 0x51, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "svdot za.s[w11, 2, vgx4], { z8.b - z11.b }, z1.b[1]"
+
+  -
+    input:
+      bytes: [ 0x22, 0xe5, 0x51, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "svdot za.s[w11, 2, vgx4], { z8.b - z11.b }, z1.b[1]"
+
+  -
+    input:
+      bytes: [ 0xa7, 0xa9, 0x5b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "svdot za.s[w9, 7, vgx4], { z12.b - z15.b }, z11.b[2]"
+
+  -
+    input:
+      bytes: [ 0xa7, 0xa9, 0x5b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "svdot za.s[w9, 7, vgx4], { z12.b - z15.b }, z11.b[2]"
+
+  -
+    input:
+      bytes: [ 0x08, 0x88, 0xd0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "svdot za.d[w8, 0, vgx4], { z0.h - z3.h }, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x08, 0x88, 0xd0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "svdot za.d[w8, 0, vgx4], { z0.h - z3.h }, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x0d, 0xcd, 0xd5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "svdot za.d[w10, 5, vgx4], { z8.h - z11.h }, z5.h[1]"
+
+  -
+    input:
+      bytes: [ 0x0d, 0xcd, 0xd5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "svdot za.d[w10, 5, vgx4], { z8.h - z11.h }, z5.h[1]"
+
+  -
+    input:
+      bytes: [ 0x8f, 0xed, 0xd8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "svdot za.d[w11, 7, vgx4], { z12.h - z15.h }, z8.h[1]"
+
+  -
+    input:
+      bytes: [ 0x8f, 0xed, 0xd8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "svdot za.d[w11, 7, vgx4], { z12.h - z15.h }, z8.h[1]"
+
+  -
+    input:
+      bytes: [ 0x8f, 0xef, 0xdf, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "svdot za.d[w11, 7, vgx4], { z28.h - z31.h }, z15.h[1]"
+
+  -
+    input:
+      bytes: [ 0x8f, 0xef, 0xdf, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "svdot za.d[w11, 7, vgx4], { z28.h - z31.h }, z15.h[1]"
+
+  -
+    input:
+      bytes: [ 0x0d, 0x8e, 0xd0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "svdot za.d[w8, 5, vgx4], { z16.h - z19.h }, z0.h[1]"
+
+  -
+    input:
+      bytes: [ 0x0d, 0x8e, 0xd0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "svdot za.d[w8, 5, vgx4], { z16.h - z19.h }, z0.h[1]"
+
+  -
+    input:
+      bytes: [ 0x09, 0x8c, 0xde, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "svdot za.d[w8, 1, vgx4], { z0.h - z3.h }, z14.h[1]"
+
+  -
+    input:
+      bytes: [ 0x09, 0x8c, 0xde, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "svdot za.d[w8, 1, vgx4], { z0.h - z3.h }, z14.h[1]"
+
+  -
+    input:
+      bytes: [ 0x08, 0xce, 0xd4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "svdot za.d[w10, 0, vgx4], { z16.h - z19.h }, z4.h[1]"
+
+  -
+    input:
+      bytes: [ 0x08, 0xce, 0xd4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "svdot za.d[w10, 0, vgx4], { z16.h - z19.h }, z4.h[1]"
+
+  -
+    input:
+      bytes: [ 0x88, 0x89, 0xd2, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "svdot za.d[w8, 0, vgx4], { z12.h - z15.h }, z2.h[0]"
+
+  -
+    input:
+      bytes: [ 0x88, 0x89, 0xd2, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "svdot za.d[w8, 0, vgx4], { z12.h - z15.h }, z2.h[0]"
+
+  -
+    input:
+      bytes: [ 0x09, 0xc8, 0xda, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "svdot za.d[w10, 1, vgx4], { z0.h - z3.h }, z10.h[0]"
+
+  -
+    input:
+      bytes: [ 0x09, 0xc8, 0xda, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "svdot za.d[w10, 1, vgx4], { z0.h - z3.h }, z10.h[0]"
+
+  -
+    input:
+      bytes: [ 0x8d, 0x8a, 0xde, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "svdot za.d[w8, 5, vgx4], { z20.h - z23.h }, z14.h[0]"
+
+  -
+    input:
+      bytes: [ 0x8d, 0x8a, 0xde, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "svdot za.d[w8, 5, vgx4], { z20.h - z23.h }, z14.h[0]"
+
+  -
+    input:
+      bytes: [ 0x0a, 0xed, 0xd1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "svdot za.d[w11, 2, vgx4], { z8.h - z11.h }, z1.h[1]"
+
+  -
+    input:
+      bytes: [ 0x0a, 0xed, 0xd1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "svdot za.d[w11, 2, vgx4], { z8.h - z11.h }, z1.h[1]"
+
+  -
+    input:
+      bytes: [ 0x8f, 0xa9, 0xdb, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "svdot za.d[w9, 7, vgx4], { z12.h - z15.h }, z11.h[0]"
+
+  -
+    input:
+      bytes: [ 0x8f, 0xa9, 0xdb, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "svdot za.d[w9, 7, vgx4], { z12.h - z15.h }, z11.h[0]"
diff --git a/tests/MC/AArch64/SME2/uclamp.s.yaml b/tests/MC/AArch64/SME2/uclamp.s.yaml
new file mode 100644
index 000000000..2bf85823e
--- /dev/null
+++ b/tests/MC/AArch64/SME2/uclamp.s.yaml
@@ -0,0 +1,320 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x01, 0xc4, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uclamp { z0.h, z1.h }, z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x55, 0xc5, 0x75, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uclamp { z20.h, z21.h }, z10.h, z21.h"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xc5, 0x68, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uclamp { z22.h, z23.h }, z13.h, z8.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0xc7, 0x7f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uclamp { z30.h, z31.h }, z31.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x01, 0xc4, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uclamp { z0.s, z1.s }, z0.s, z0.s"
+
+  -
+    input:
+      bytes: [ 0x55, 0xc5, 0xb5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uclamp { z20.s, z21.s }, z10.s, z21.s"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xc5, 0xa8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uclamp { z22.s, z23.s }, z13.s, z8.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0xc7, 0xbf, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uclamp { z30.s, z31.s }, z31.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x01, 0xc4, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uclamp { z0.d, z1.d }, z0.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0x55, 0xc5, 0xf5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uclamp { z20.d, z21.d }, z10.d, z21.d"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xc5, 0xe8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uclamp { z22.d, z23.d }, z13.d, z8.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0xc7, 0xff, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uclamp { z30.d, z31.d }, z31.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0x01, 0xc4, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uclamp { z0.b, z1.b }, z0.b, z0.b"
+
+  -
+    input:
+      bytes: [ 0x55, 0xc5, 0x35, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uclamp { z20.b, z21.b }, z10.b, z21.b"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xc5, 0x28, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uclamp { z22.b, z23.b }, z13.b, z8.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0xc7, 0x3f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uclamp { z30.b, z31.b }, z31.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0x01, 0xcc, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uclamp { z0.h - z3.h }, z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x55, 0xcd, 0x75, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uclamp { z20.h - z23.h }, z10.h, z21.h"
+
+  -
+    input:
+      bytes: [ 0xb5, 0xcd, 0x68, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uclamp { z20.h - z23.h }, z13.h, z8.h"
+
+  -
+    input:
+      bytes: [ 0xfd, 0xcf, 0x7f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uclamp { z28.h - z31.h }, z31.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x01, 0xcc, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uclamp { z0.s - z3.s }, z0.s, z0.s"
+
+  -
+    input:
+      bytes: [ 0x55, 0xcd, 0xb5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uclamp { z20.s - z23.s }, z10.s, z21.s"
+
+  -
+    input:
+      bytes: [ 0xb5, 0xcd, 0xa8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uclamp { z20.s - z23.s }, z13.s, z8.s"
+
+  -
+    input:
+      bytes: [ 0xfd, 0xcf, 0xbf, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uclamp { z28.s - z31.s }, z31.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x01, 0xcc, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uclamp { z0.d - z3.d }, z0.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0x55, 0xcd, 0xf5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uclamp { z20.d - z23.d }, z10.d, z21.d"
+
+  -
+    input:
+      bytes: [ 0xb5, 0xcd, 0xe8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uclamp { z20.d - z23.d }, z13.d, z8.d"
+
+  -
+    input:
+      bytes: [ 0xfd, 0xcf, 0xff, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uclamp { z28.d - z31.d }, z31.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0x01, 0xcc, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uclamp { z0.b - z3.b }, z0.b, z0.b"
+
+  -
+    input:
+      bytes: [ 0x55, 0xcd, 0x35, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uclamp { z20.b - z23.b }, z10.b, z21.b"
+
+  -
+    input:
+      bytes: [ 0xb5, 0xcd, 0x28, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uclamp { z20.b - z23.b }, z13.b, z8.b"
+
+  -
+    input:
+      bytes: [ 0xfd, 0xcf, 0x3f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uclamp { z28.b - z31.b }, z31.b, z31.b"
diff --git a/tests/MC/AArch64/SME2/ucvtf.s.yaml b/tests/MC/AArch64/SME2/ucvtf.s.yaml
new file mode 100644
index 000000000..67ff91582
--- /dev/null
+++ b/tests/MC/AArch64/SME2/ucvtf.s.yaml
@@ -0,0 +1,80 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0xe0, 0x22, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ucvtf { z0.s, z1.s }, { z0.s, z1.s }"
+
+  -
+    input:
+      bytes: [ 0x74, 0xe1, 0x22, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ucvtf { z20.s, z21.s }, { z10.s, z11.s }"
+
+  -
+    input:
+      bytes: [ 0xb6, 0xe1, 0x22, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ucvtf { z22.s, z23.s }, { z12.s, z13.s }"
+
+  -
+    input:
+      bytes: [ 0xfe, 0xe3, 0x22, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ucvtf { z30.s, z31.s }, { z30.s, z31.s }"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe0, 0x32, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ucvtf { z0.s - z3.s }, { z0.s - z3.s }"
+
+  -
+    input:
+      bytes: [ 0x34, 0xe1, 0x32, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ucvtf { z20.s - z23.s }, { z8.s - z11.s }"
+
+  -
+    input:
+      bytes: [ 0xb4, 0xe1, 0x32, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ucvtf { z20.s - z23.s }, { z12.s - z15.s }"
+
+  -
+    input:
+      bytes: [ 0xbc, 0xe3, 0x32, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ucvtf { z28.s - z31.s }, { z28.s - z31.s }"
diff --git a/tests/MC/AArch64/SME2/udot.s.yaml b/tests/MC/AArch64/SME2/udot.s.yaml
new file mode 100644
index 000000000..3f62eebf1
--- /dev/null
+++ b/tests/MC/AArch64/SME2/udot.s.yaml
@@ -0,0 +1,4330 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x18, 0x14, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 0, vgx2], { z0.h, z1.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x18, 0x14, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 0, vgx2], { z0.h, z1.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x5d, 0x55, 0x65, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w10, 5, vgx2], { z10.h, z11.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0x5d, 0x55, 0x65, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w10, 5, vgx2], { z10.h, z11.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x75, 0x68, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w11, 7, vgx2], { z13.h, z14.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x75, 0x68, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w11, 7, vgx2], { z13.h, z14.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x77, 0x6f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w11, 7, vgx2], { z31.h, z0.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x77, 0x6f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w11, 7, vgx2], { z31.h, z0.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0x3d, 0x16, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 5, vgx2], { z17.h, z18.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x3d, 0x16, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 5, vgx2], { z17.h, z18.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x39, 0x14, 0x6e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 1, vgx2], { z1.h, z2.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x39, 0x14, 0x6e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 1, vgx2], { z1.h, z2.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x78, 0x56, 0x64, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w10, 0, vgx2], { z19.h, z20.h }, z4.h"
+
+  -
+    input:
+      bytes: [ 0x78, 0x56, 0x64, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w10, 0, vgx2], { z19.h, z20.h }, z4.h"
+
+  -
+    input:
+      bytes: [ 0x98, 0x15, 0x62, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 0, vgx2], { z12.h, z13.h }, z2.h"
+
+  -
+    input:
+      bytes: [ 0x98, 0x15, 0x62, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 0, vgx2], { z12.h, z13.h }, z2.h"
+
+  -
+    input:
+      bytes: [ 0x39, 0x54, 0x6a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w10, 1, vgx2], { z1.h, z2.h }, z10.h"
+
+  -
+    input:
+      bytes: [ 0x39, 0x54, 0x6a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w10, 1, vgx2], { z1.h, z2.h }, z10.h"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x16, 0x6e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 5, vgx2], { z22.h, z23.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x16, 0x6e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 5, vgx2], { z22.h, z23.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x3a, 0x75, 0x61, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w11, 2, vgx2], { z9.h, z10.h }, z1.h"
+
+  -
+    input:
+      bytes: [ 0x3a, 0x75, 0x61, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w11, 2, vgx2], { z9.h, z10.h }, z1.h"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x35, 0x6b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w9, 7, vgx2], { z12.h, z13.h }, z11.h"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x35, 0x6b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w9, 7, vgx2], { z12.h, z13.h }, z11.h"
+
+  -
+    input:
+      bytes: [ 0x10, 0x10, 0x50, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 0, vgx2], { z0.h, z1.h }, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x10, 0x10, 0x50, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 0, vgx2], { z0.h, z1.h }, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x55, 0x55, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w10, 5, vgx2], { z10.h, z11.h }, z5.h[1]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x55, 0x55, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w10, 5, vgx2], { z10.h, z11.h }, z5.h[1]"
+
+  -
+    input:
+      bytes: [ 0x97, 0x7d, 0x58, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w11, 7, vgx2], { z12.h, z13.h }, z8.h[3]"
+
+  -
+    input:
+      bytes: [ 0x97, 0x7d, 0x58, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w11, 7, vgx2], { z12.h, z13.h }, z8.h[3]"
+
+  -
+    input:
+      bytes: [ 0xd7, 0x7f, 0x5f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w11, 7, vgx2], { z30.h, z31.h }, z15.h[3]"
+
+  -
+    input:
+      bytes: [ 0xd7, 0x7f, 0x5f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w11, 7, vgx2], { z30.h, z31.h }, z15.h[3]"
+
+  -
+    input:
+      bytes: [ 0x15, 0x1e, 0x50, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 5, vgx2], { z16.h, z17.h }, z0.h[3]"
+
+  -
+    input:
+      bytes: [ 0x15, 0x1e, 0x50, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 5, vgx2], { z16.h, z17.h }, z0.h[3]"
+
+  -
+    input:
+      bytes: [ 0x11, 0x14, 0x5e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 1, vgx2], { z0.h, z1.h }, z14.h[1]"
+
+  -
+    input:
+      bytes: [ 0x11, 0x14, 0x5e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 1, vgx2], { z0.h, z1.h }, z14.h[1]"
+
+  -
+    input:
+      bytes: [ 0x50, 0x56, 0x54, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w10, 0, vgx2], { z18.h, z19.h }, z4.h[1]"
+
+  -
+    input:
+      bytes: [ 0x50, 0x56, 0x54, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w10, 0, vgx2], { z18.h, z19.h }, z4.h[1]"
+
+  -
+    input:
+      bytes: [ 0x90, 0x19, 0x52, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 0, vgx2], { z12.h, z13.h }, z2.h[2]"
+
+  -
+    input:
+      bytes: [ 0x90, 0x19, 0x52, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 0, vgx2], { z12.h, z13.h }, z2.h[2]"
+
+  -
+    input:
+      bytes: [ 0x11, 0x58, 0x5a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w10, 1, vgx2], { z0.h, z1.h }, z10.h[2]"
+
+  -
+    input:
+      bytes: [ 0x11, 0x58, 0x5a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w10, 1, vgx2], { z0.h, z1.h }, z10.h[2]"
+
+  -
+    input:
+      bytes: [ 0xd5, 0x1a, 0x5e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 5, vgx2], { z22.h, z23.h }, z14.h[2]"
+
+  -
+    input:
+      bytes: [ 0xd5, 0x1a, 0x5e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 5, vgx2], { z22.h, z23.h }, z14.h[2]"
+
+  -
+    input:
+      bytes: [ 0x12, 0x75, 0x51, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w11, 2, vgx2], { z8.h, z9.h }, z1.h[1]"
+
+  -
+    input:
+      bytes: [ 0x12, 0x75, 0x51, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w11, 2, vgx2], { z8.h, z9.h }, z1.h[1]"
+
+  -
+    input:
+      bytes: [ 0x97, 0x39, 0x5b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w9, 7, vgx2], { z12.h, z13.h }, z11.h[2]"
+
+  -
+    input:
+      bytes: [ 0x97, 0x39, 0x5b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w9, 7, vgx2], { z12.h, z13.h }, z11.h[2]"
+
+  -
+    input:
+      bytes: [ 0x18, 0x14, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 0, vgx2], { z0.h, z1.h }, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x18, 0x14, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 0, vgx2], { z0.h, z1.h }, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x5d, 0x55, 0xf4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w10, 5, vgx2], { z10.h, z11.h }, { z20.h, z21.h }"
+
+  -
+    input:
+      bytes: [ 0x5d, 0x55, 0xf4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w10, 5, vgx2], { z10.h, z11.h }, { z20.h, z21.h }"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x75, 0xe8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w11, 7, vgx2], { z12.h, z13.h }, { z8.h, z9.h }"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x75, 0xe8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w11, 7, vgx2], { z12.h, z13.h }, { z8.h, z9.h }"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x77, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w11, 7, vgx2], { z30.h, z31.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x77, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w11, 7, vgx2], { z30.h, z31.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x1d, 0x16, 0xf0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 5, vgx2], { z16.h, z17.h }, { z16.h, z17.h }"
+
+  -
+    input:
+      bytes: [ 0x1d, 0x16, 0xf0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 5, vgx2], { z16.h, z17.h }, { z16.h, z17.h }"
+
+  -
+    input:
+      bytes: [ 0x19, 0x14, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 1, vgx2], { z0.h, z1.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x19, 0x14, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 1, vgx2], { z0.h, z1.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x58, 0x56, 0xf4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w10, 0, vgx2], { z18.h, z19.h }, { z20.h, z21.h }"
+
+  -
+    input:
+      bytes: [ 0x58, 0x56, 0xf4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w10, 0, vgx2], { z18.h, z19.h }, { z20.h, z21.h }"
+
+  -
+    input:
+      bytes: [ 0x98, 0x15, 0xe2, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 0, vgx2], { z12.h, z13.h }, { z2.h, z3.h }"
+
+  -
+    input:
+      bytes: [ 0x98, 0x15, 0xe2, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 0, vgx2], { z12.h, z13.h }, { z2.h, z3.h }"
+
+  -
+    input:
+      bytes: [ 0x19, 0x54, 0xfa, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w10, 1, vgx2], { z0.h, z1.h }, { z26.h, z27.h }"
+
+  -
+    input:
+      bytes: [ 0x19, 0x54, 0xfa, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w10, 1, vgx2], { z0.h, z1.h }, { z26.h, z27.h }"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x16, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 5, vgx2], { z22.h, z23.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x16, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 5, vgx2], { z22.h, z23.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x1a, 0x75, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w11, 2, vgx2], { z8.h, z9.h }, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x1a, 0x75, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w11, 2, vgx2], { z8.h, z9.h }, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x35, 0xea, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w9, 7, vgx2], { z12.h, z13.h }, { z10.h, z11.h }"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x35, 0xea, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w9, 7, vgx2], { z12.h, z13.h }, { z10.h, z11.h }"
+
+  -
+    input:
+      bytes: [ 0x30, 0x10, 0x50, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 0, vgx2], { z0.b, z1.b }, z0.b[0]"
+
+  -
+    input:
+      bytes: [ 0x30, 0x10, 0x50, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 0, vgx2], { z0.b, z1.b }, z0.b[0]"
+
+  -
+    input:
+      bytes: [ 0x75, 0x55, 0x55, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w10, 5, vgx2], { z10.b, z11.b }, z5.b[1]"
+
+  -
+    input:
+      bytes: [ 0x75, 0x55, 0x55, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w10, 5, vgx2], { z10.b, z11.b }, z5.b[1]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x7d, 0x58, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w11, 7, vgx2], { z12.b, z13.b }, z8.b[3]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x7d, 0x58, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w11, 7, vgx2], { z12.b, z13.b }, z8.b[3]"
+
+  -
+    input:
+      bytes: [ 0xf7, 0x7f, 0x5f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w11, 7, vgx2], { z30.b, z31.b }, z15.b[3]"
+
+  -
+    input:
+      bytes: [ 0xf7, 0x7f, 0x5f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w11, 7, vgx2], { z30.b, z31.b }, z15.b[3]"
+
+  -
+    input:
+      bytes: [ 0x35, 0x1e, 0x50, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 5, vgx2], { z16.b, z17.b }, z0.b[3]"
+
+  -
+    input:
+      bytes: [ 0x35, 0x1e, 0x50, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 5, vgx2], { z16.b, z17.b }, z0.b[3]"
+
+  -
+    input:
+      bytes: [ 0x31, 0x14, 0x5e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 1, vgx2], { z0.b, z1.b }, z14.b[1]"
+
+  -
+    input:
+      bytes: [ 0x31, 0x14, 0x5e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 1, vgx2], { z0.b, z1.b }, z14.b[1]"
+
+  -
+    input:
+      bytes: [ 0x70, 0x56, 0x54, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w10, 0, vgx2], { z18.b, z19.b }, z4.b[1]"
+
+  -
+    input:
+      bytes: [ 0x70, 0x56, 0x54, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w10, 0, vgx2], { z18.b, z19.b }, z4.b[1]"
+
+  -
+    input:
+      bytes: [ 0xb0, 0x19, 0x52, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 0, vgx2], { z12.b, z13.b }, z2.b[2]"
+
+  -
+    input:
+      bytes: [ 0xb0, 0x19, 0x52, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 0, vgx2], { z12.b, z13.b }, z2.b[2]"
+
+  -
+    input:
+      bytes: [ 0x31, 0x58, 0x5a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w10, 1, vgx2], { z0.b, z1.b }, z10.b[2]"
+
+  -
+    input:
+      bytes: [ 0x31, 0x58, 0x5a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w10, 1, vgx2], { z0.b, z1.b }, z10.b[2]"
+
+  -
+    input:
+      bytes: [ 0xf5, 0x1a, 0x5e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 5, vgx2], { z22.b, z23.b }, z14.b[2]"
+
+  -
+    input:
+      bytes: [ 0xf5, 0x1a, 0x5e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 5, vgx2], { z22.b, z23.b }, z14.b[2]"
+
+  -
+    input:
+      bytes: [ 0x32, 0x75, 0x51, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w11, 2, vgx2], { z8.b, z9.b }, z1.b[1]"
+
+  -
+    input:
+      bytes: [ 0x32, 0x75, 0x51, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w11, 2, vgx2], { z8.b, z9.b }, z1.b[1]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x39, 0x5b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w9, 7, vgx2], { z12.b, z13.b }, z11.b[2]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x39, 0x5b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w9, 7, vgx2], { z12.b, z13.b }, z11.b[2]"
+
+  -
+    input:
+      bytes: [ 0x18, 0x00, 0xd0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w8, 0, vgx2], { z0.h, z1.h }, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x18, 0x00, 0xd0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w8, 0, vgx2], { z0.h, z1.h }, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x5d, 0x45, 0xd5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w10, 5, vgx2], { z10.h, z11.h }, z5.h[1]"
+
+  -
+    input:
+      bytes: [ 0x5d, 0x45, 0xd5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w10, 5, vgx2], { z10.h, z11.h }, z5.h[1]"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x65, 0xd8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w11, 7, vgx2], { z12.h, z13.h }, z8.h[1]"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x65, 0xd8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w11, 7, vgx2], { z12.h, z13.h }, z8.h[1]"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x67, 0xdf, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w11, 7, vgx2], { z30.h, z31.h }, z15.h[1]"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x67, 0xdf, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w11, 7, vgx2], { z30.h, z31.h }, z15.h[1]"
+
+  -
+    input:
+      bytes: [ 0x1d, 0x06, 0xd0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w8, 5, vgx2], { z16.h, z17.h }, z0.h[1]"
+
+  -
+    input:
+      bytes: [ 0x1d, 0x06, 0xd0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w8, 5, vgx2], { z16.h, z17.h }, z0.h[1]"
+
+  -
+    input:
+      bytes: [ 0x19, 0x04, 0xde, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w8, 1, vgx2], { z0.h, z1.h }, z14.h[1]"
+
+  -
+    input:
+      bytes: [ 0x19, 0x04, 0xde, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w8, 1, vgx2], { z0.h, z1.h }, z14.h[1]"
+
+  -
+    input:
+      bytes: [ 0x58, 0x46, 0xd4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w10, 0, vgx2], { z18.h, z19.h }, z4.h[1]"
+
+  -
+    input:
+      bytes: [ 0x58, 0x46, 0xd4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w10, 0, vgx2], { z18.h, z19.h }, z4.h[1]"
+
+  -
+    input:
+      bytes: [ 0x98, 0x01, 0xd2, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w8, 0, vgx2], { z12.h, z13.h }, z2.h[0]"
+
+  -
+    input:
+      bytes: [ 0x98, 0x01, 0xd2, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w8, 0, vgx2], { z12.h, z13.h }, z2.h[0]"
+
+  -
+    input:
+      bytes: [ 0x19, 0x40, 0xda, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w10, 1, vgx2], { z0.h, z1.h }, z10.h[0]"
+
+  -
+    input:
+      bytes: [ 0x19, 0x40, 0xda, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w10, 1, vgx2], { z0.h, z1.h }, z10.h[0]"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x02, 0xde, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w8, 5, vgx2], { z22.h, z23.h }, z14.h[0]"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x02, 0xde, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w8, 5, vgx2], { z22.h, z23.h }, z14.h[0]"
+
+  -
+    input:
+      bytes: [ 0x1a, 0x65, 0xd1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w11, 2, vgx2], { z8.h, z9.h }, z1.h[1]"
+
+  -
+    input:
+      bytes: [ 0x1a, 0x65, 0xd1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w11, 2, vgx2], { z8.h, z9.h }, z1.h[1]"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x21, 0xdb, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w9, 7, vgx2], { z12.h, z13.h }, z11.h[0]"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x21, 0xdb, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w9, 7, vgx2], { z12.h, z13.h }, z11.h[0]"
+
+  -
+    input:
+      bytes: [ 0x18, 0x14, 0x70, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 0, vgx4], { z0.h - z3.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x18, 0x14, 0x70, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 0, vgx4], { z0.h - z3.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x5d, 0x55, 0x75, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w10, 5, vgx4], { z10.h - z13.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0x5d, 0x55, 0x75, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w10, 5, vgx4], { z10.h - z13.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x75, 0x78, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w11, 7, vgx4], { z13.h - z16.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x75, 0x78, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w11, 7, vgx4], { z13.h - z16.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x77, 0x7f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w11, 7, vgx4], { z31.h, z0.h, z1.h, z2.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x77, 0x7f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w11, 7, vgx4], { z31.h, z0.h, z1.h, z2.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0x3d, 0x16, 0x70, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 5, vgx4], { z17.h - z20.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x3d, 0x16, 0x70, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 5, vgx4], { z17.h - z20.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x39, 0x14, 0x7e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 1, vgx4], { z1.h - z4.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x39, 0x14, 0x7e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 1, vgx4], { z1.h - z4.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x78, 0x56, 0x74, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w10, 0, vgx4], { z19.h - z22.h }, z4.h"
+
+  -
+    input:
+      bytes: [ 0x78, 0x56, 0x74, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w10, 0, vgx4], { z19.h - z22.h }, z4.h"
+
+  -
+    input:
+      bytes: [ 0x98, 0x15, 0x72, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 0, vgx4], { z12.h - z15.h }, z2.h"
+
+  -
+    input:
+      bytes: [ 0x98, 0x15, 0x72, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 0, vgx4], { z12.h - z15.h }, z2.h"
+
+  -
+    input:
+      bytes: [ 0x39, 0x54, 0x7a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w10, 1, vgx4], { z1.h - z4.h }, z10.h"
+
+  -
+    input:
+      bytes: [ 0x39, 0x54, 0x7a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w10, 1, vgx4], { z1.h - z4.h }, z10.h"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x16, 0x7e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 5, vgx4], { z22.h - z25.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x16, 0x7e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 5, vgx4], { z22.h - z25.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x3a, 0x75, 0x71, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w11, 2, vgx4], { z9.h - z12.h }, z1.h"
+
+  -
+    input:
+      bytes: [ 0x3a, 0x75, 0x71, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w11, 2, vgx4], { z9.h - z12.h }, z1.h"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x35, 0x7b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w9, 7, vgx4], { z12.h - z15.h }, z11.h"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x35, 0x7b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w9, 7, vgx4], { z12.h - z15.h }, z11.h"
+
+  -
+    input:
+      bytes: [ 0x10, 0x90, 0x50, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 0, vgx4], { z0.h - z3.h }, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x10, 0x90, 0x50, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 0, vgx4], { z0.h - z3.h }, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x15, 0xd5, 0x55, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w10, 5, vgx4], { z8.h - z11.h }, z5.h[1]"
+
+  -
+    input:
+      bytes: [ 0x15, 0xd5, 0x55, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w10, 5, vgx4], { z8.h - z11.h }, z5.h[1]"
+
+  -
+    input:
+      bytes: [ 0x97, 0xfd, 0x58, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w11, 7, vgx4], { z12.h - z15.h }, z8.h[3]"
+
+  -
+    input:
+      bytes: [ 0x97, 0xfd, 0x58, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w11, 7, vgx4], { z12.h - z15.h }, z8.h[3]"
+
+  -
+    input:
+      bytes: [ 0x97, 0xff, 0x5f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w11, 7, vgx4], { z28.h - z31.h }, z15.h[3]"
+
+  -
+    input:
+      bytes: [ 0x97, 0xff, 0x5f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w11, 7, vgx4], { z28.h - z31.h }, z15.h[3]"
+
+  -
+    input:
+      bytes: [ 0x15, 0x9e, 0x50, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 5, vgx4], { z16.h - z19.h }, z0.h[3]"
+
+  -
+    input:
+      bytes: [ 0x15, 0x9e, 0x50, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 5, vgx4], { z16.h - z19.h }, z0.h[3]"
+
+  -
+    input:
+      bytes: [ 0x11, 0x94, 0x5e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 1, vgx4], { z0.h - z3.h }, z14.h[1]"
+
+  -
+    input:
+      bytes: [ 0x11, 0x94, 0x5e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 1, vgx4], { z0.h - z3.h }, z14.h[1]"
+
+  -
+    input:
+      bytes: [ 0x10, 0xd6, 0x54, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w10, 0, vgx4], { z16.h - z19.h }, z4.h[1]"
+
+  -
+    input:
+      bytes: [ 0x10, 0xd6, 0x54, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w10, 0, vgx4], { z16.h - z19.h }, z4.h[1]"
+
+  -
+    input:
+      bytes: [ 0x90, 0x99, 0x52, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 0, vgx4], { z12.h - z15.h }, z2.h[2]"
+
+  -
+    input:
+      bytes: [ 0x90, 0x99, 0x52, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 0, vgx4], { z12.h - z15.h }, z2.h[2]"
+
+  -
+    input:
+      bytes: [ 0x11, 0xd8, 0x5a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w10, 1, vgx4], { z0.h - z3.h }, z10.h[2]"
+
+  -
+    input:
+      bytes: [ 0x11, 0xd8, 0x5a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w10, 1, vgx4], { z0.h - z3.h }, z10.h[2]"
+
+  -
+    input:
+      bytes: [ 0x95, 0x9a, 0x5e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 5, vgx4], { z20.h - z23.h }, z14.h[2]"
+
+  -
+    input:
+      bytes: [ 0x95, 0x9a, 0x5e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 5, vgx4], { z20.h - z23.h }, z14.h[2]"
+
+  -
+    input:
+      bytes: [ 0x12, 0xf5, 0x51, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w11, 2, vgx4], { z8.h - z11.h }, z1.h[1]"
+
+  -
+    input:
+      bytes: [ 0x12, 0xf5, 0x51, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w11, 2, vgx4], { z8.h - z11.h }, z1.h[1]"
+
+  -
+    input:
+      bytes: [ 0x97, 0xb9, 0x5b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w9, 7, vgx4], { z12.h - z15.h }, z11.h[2]"
+
+  -
+    input:
+      bytes: [ 0x97, 0xb9, 0x5b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w9, 7, vgx4], { z12.h - z15.h }, z11.h[2]"
+
+  -
+    input:
+      bytes: [ 0x18, 0x14, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 0, vgx4], { z0.h - z3.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x18, 0x14, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 0, vgx4], { z0.h - z3.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x1d, 0x55, 0xf5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w10, 5, vgx4], { z8.h - z11.h }, { z20.h - z23.h }"
+
+  -
+    input:
+      bytes: [ 0x1d, 0x55, 0xf5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w10, 5, vgx4], { z8.h - z11.h }, { z20.h - z23.h }"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x75, 0xe9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w11, 7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x75, 0xe9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w11, 7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x77, 0xfd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w11, 7, vgx4], { z28.h - z31.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x77, 0xfd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w11, 7, vgx4], { z28.h - z31.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x1d, 0x16, 0xf1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 5, vgx4], { z16.h - z19.h }, { z16.h - z19.h }"
+
+  -
+    input:
+      bytes: [ 0x1d, 0x16, 0xf1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 5, vgx4], { z16.h - z19.h }, { z16.h - z19.h }"
+
+  -
+    input:
+      bytes: [ 0x19, 0x14, 0xfd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 1, vgx4], { z0.h - z3.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x19, 0x14, 0xfd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 1, vgx4], { z0.h - z3.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x18, 0x56, 0xf5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w10, 0, vgx4], { z16.h - z19.h }, { z20.h - z23.h }"
+
+  -
+    input:
+      bytes: [ 0x18, 0x56, 0xf5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w10, 0, vgx4], { z16.h - z19.h }, { z20.h - z23.h }"
+
+  -
+    input:
+      bytes: [ 0x98, 0x15, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 0, vgx4], { z12.h - z15.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x98, 0x15, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 0, vgx4], { z12.h - z15.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x19, 0x54, 0xf9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w10, 1, vgx4], { z0.h - z3.h }, { z24.h - z27.h }"
+
+  -
+    input:
+      bytes: [ 0x19, 0x54, 0xf9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w10, 1, vgx4], { z0.h - z3.h }, { z24.h - z27.h }"
+
+  -
+    input:
+      bytes: [ 0x9d, 0x16, 0xfd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 5, vgx4], { z20.h - z23.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x9d, 0x16, 0xfd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 5, vgx4], { z20.h - z23.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x1a, 0x75, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w11, 2, vgx4], { z8.h - z11.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x1a, 0x75, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w11, 2, vgx4], { z8.h - z11.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x35, 0xe9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w9, 7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x35, 0xe9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w9, 7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }"
+
+  -
+    input:
+      bytes: [ 0x30, 0x90, 0x50, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 0, vgx4], { z0.b - z3.b }, z0.b[0]"
+
+  -
+    input:
+      bytes: [ 0x30, 0x90, 0x50, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 0, vgx4], { z0.b - z3.b }, z0.b[0]"
+
+  -
+    input:
+      bytes: [ 0x35, 0xd5, 0x55, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w10, 5, vgx4], { z8.b - z11.b }, z5.b[1]"
+
+  -
+    input:
+      bytes: [ 0x35, 0xd5, 0x55, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w10, 5, vgx4], { z8.b - z11.b }, z5.b[1]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xfd, 0x58, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w11, 7, vgx4], { z12.b - z15.b }, z8.b[3]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xfd, 0x58, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w11, 7, vgx4], { z12.b - z15.b }, z8.b[3]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xff, 0x5f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w11, 7, vgx4], { z28.b - z31.b }, z15.b[3]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xff, 0x5f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w11, 7, vgx4], { z28.b - z31.b }, z15.b[3]"
+
+  -
+    input:
+      bytes: [ 0x35, 0x9e, 0x50, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 5, vgx4], { z16.b - z19.b }, z0.b[3]"
+
+  -
+    input:
+      bytes: [ 0x35, 0x9e, 0x50, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 5, vgx4], { z16.b - z19.b }, z0.b[3]"
+
+  -
+    input:
+      bytes: [ 0x31, 0x94, 0x5e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 1, vgx4], { z0.b - z3.b }, z14.b[1]"
+
+  -
+    input:
+      bytes: [ 0x31, 0x94, 0x5e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 1, vgx4], { z0.b - z3.b }, z14.b[1]"
+
+  -
+    input:
+      bytes: [ 0x30, 0xd6, 0x54, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w10, 0, vgx4], { z16.b - z19.b }, z4.b[1]"
+
+  -
+    input:
+      bytes: [ 0x30, 0xd6, 0x54, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w10, 0, vgx4], { z16.b - z19.b }, z4.b[1]"
+
+  -
+    input:
+      bytes: [ 0xb0, 0x99, 0x52, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 0, vgx4], { z12.b - z15.b }, z2.b[2]"
+
+  -
+    input:
+      bytes: [ 0xb0, 0x99, 0x52, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 0, vgx4], { z12.b - z15.b }, z2.b[2]"
+
+  -
+    input:
+      bytes: [ 0x31, 0xd8, 0x5a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w10, 1, vgx4], { z0.b - z3.b }, z10.b[2]"
+
+  -
+    input:
+      bytes: [ 0x31, 0xd8, 0x5a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w10, 1, vgx4], { z0.b - z3.b }, z10.b[2]"
+
+  -
+    input:
+      bytes: [ 0xb5, 0x9a, 0x5e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 5, vgx4], { z20.b - z23.b }, z14.b[2]"
+
+  -
+    input:
+      bytes: [ 0xb5, 0x9a, 0x5e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 5, vgx4], { z20.b - z23.b }, z14.b[2]"
+
+  -
+    input:
+      bytes: [ 0x32, 0xf5, 0x51, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w11, 2, vgx4], { z8.b - z11.b }, z1.b[1]"
+
+  -
+    input:
+      bytes: [ 0x32, 0xf5, 0x51, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w11, 2, vgx4], { z8.b - z11.b }, z1.b[1]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xb9, 0x5b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w9, 7, vgx4], { z12.b - z15.b }, z11.b[2]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xb9, 0x5b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w9, 7, vgx4], { z12.b - z15.b }, z11.b[2]"
+
+  -
+    input:
+      bytes: [ 0x18, 0x80, 0xd0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w8, 0, vgx4], { z0.h - z3.h }, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x18, 0x80, 0xd0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w8, 0, vgx4], { z0.h - z3.h }, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x1d, 0xc5, 0xd5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w10, 5, vgx4], { z8.h - z11.h }, z5.h[1]"
+
+  -
+    input:
+      bytes: [ 0x1d, 0xc5, 0xd5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w10, 5, vgx4], { z8.h - z11.h }, z5.h[1]"
+
+  -
+    input:
+      bytes: [ 0x9f, 0xe5, 0xd8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w11, 7, vgx4], { z12.h - z15.h }, z8.h[1]"
+
+  -
+    input:
+      bytes: [ 0x9f, 0xe5, 0xd8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w11, 7, vgx4], { z12.h - z15.h }, z8.h[1]"
+
+  -
+    input:
+      bytes: [ 0x9f, 0xe7, 0xdf, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w11, 7, vgx4], { z28.h - z31.h }, z15.h[1]"
+
+  -
+    input:
+      bytes: [ 0x9f, 0xe7, 0xdf, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w11, 7, vgx4], { z28.h - z31.h }, z15.h[1]"
+
+  -
+    input:
+      bytes: [ 0x1d, 0x86, 0xd0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w8, 5, vgx4], { z16.h - z19.h }, z0.h[1]"
+
+  -
+    input:
+      bytes: [ 0x1d, 0x86, 0xd0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w8, 5, vgx4], { z16.h - z19.h }, z0.h[1]"
+
+  -
+    input:
+      bytes: [ 0x19, 0x84, 0xde, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w8, 1, vgx4], { z0.h - z3.h }, z14.h[1]"
+
+  -
+    input:
+      bytes: [ 0x19, 0x84, 0xde, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w8, 1, vgx4], { z0.h - z3.h }, z14.h[1]"
+
+  -
+    input:
+      bytes: [ 0x18, 0xc6, 0xd4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w10, 0, vgx4], { z16.h - z19.h }, z4.h[1]"
+
+  -
+    input:
+      bytes: [ 0x18, 0xc6, 0xd4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w10, 0, vgx4], { z16.h - z19.h }, z4.h[1]"
+
+  -
+    input:
+      bytes: [ 0x98, 0x81, 0xd2, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w8, 0, vgx4], { z12.h - z15.h }, z2.h[0]"
+
+  -
+    input:
+      bytes: [ 0x98, 0x81, 0xd2, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w8, 0, vgx4], { z12.h - z15.h }, z2.h[0]"
+
+  -
+    input:
+      bytes: [ 0x19, 0xc0, 0xda, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w10, 1, vgx4], { z0.h - z3.h }, z10.h[0]"
+
+  -
+    input:
+      bytes: [ 0x19, 0xc0, 0xda, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w10, 1, vgx4], { z0.h - z3.h }, z10.h[0]"
+
+  -
+    input:
+      bytes: [ 0x9d, 0x82, 0xde, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w8, 5, vgx4], { z20.h - z23.h }, z14.h[0]"
+
+  -
+    input:
+      bytes: [ 0x9d, 0x82, 0xde, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w8, 5, vgx4], { z20.h - z23.h }, z14.h[0]"
+
+  -
+    input:
+      bytes: [ 0x1a, 0xe5, 0xd1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w11, 2, vgx4], { z8.h - z11.h }, z1.h[1]"
+
+  -
+    input:
+      bytes: [ 0x1a, 0xe5, 0xd1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w11, 2, vgx4], { z8.h - z11.h }, z1.h[1]"
+
+  -
+    input:
+      bytes: [ 0x9f, 0xa1, 0xdb, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w9, 7, vgx4], { z12.h - z15.h }, z11.h[0]"
+
+  -
+    input:
+      bytes: [ 0x9f, 0xa1, 0xdb, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w9, 7, vgx4], { z12.h - z15.h }, z11.h[0]"
+
+  -
+    input:
+      bytes: [ 0x10, 0x14, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 0, vgx2], { z0.b, z1.b }, z0.b"
+
+  -
+    input:
+      bytes: [ 0x10, 0x14, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 0, vgx2], { z0.b, z1.b }, z0.b"
+
+  -
+    input:
+      bytes: [ 0x55, 0x55, 0x25, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w10, 5, vgx2], { z10.b, z11.b }, z5.b"
+
+  -
+    input:
+      bytes: [ 0x55, 0x55, 0x25, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w10, 5, vgx2], { z10.b, z11.b }, z5.b"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x75, 0x28, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w11, 7, vgx2], { z13.b, z14.b }, z8.b"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x75, 0x28, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w11, 7, vgx2], { z13.b, z14.b }, z8.b"
+
+  -
+    input:
+      bytes: [ 0xf7, 0x77, 0x2f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w11, 7, vgx2], { z31.b, z0.b }, z15.b"
+
+  -
+    input:
+      bytes: [ 0xf7, 0x77, 0x2f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w11, 7, vgx2], { z31.b, z0.b }, z15.b"
+
+  -
+    input:
+      bytes: [ 0x35, 0x16, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 5, vgx2], { z17.b, z18.b }, z0.b"
+
+  -
+    input:
+      bytes: [ 0x35, 0x16, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 5, vgx2], { z17.b, z18.b }, z0.b"
+
+  -
+    input:
+      bytes: [ 0x31, 0x14, 0x2e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 1, vgx2], { z1.b, z2.b }, z14.b"
+
+  -
+    input:
+      bytes: [ 0x31, 0x14, 0x2e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 1, vgx2], { z1.b, z2.b }, z14.b"
+
+  -
+    input:
+      bytes: [ 0x70, 0x56, 0x24, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w10, 0, vgx2], { z19.b, z20.b }, z4.b"
+
+  -
+    input:
+      bytes: [ 0x70, 0x56, 0x24, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w10, 0, vgx2], { z19.b, z20.b }, z4.b"
+
+  -
+    input:
+      bytes: [ 0x90, 0x15, 0x22, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 0, vgx2], { z12.b, z13.b }, z2.b"
+
+  -
+    input:
+      bytes: [ 0x90, 0x15, 0x22, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 0, vgx2], { z12.b, z13.b }, z2.b"
+
+  -
+    input:
+      bytes: [ 0x31, 0x54, 0x2a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w10, 1, vgx2], { z1.b, z2.b }, z10.b"
+
+  -
+    input:
+      bytes: [ 0x31, 0x54, 0x2a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w10, 1, vgx2], { z1.b, z2.b }, z10.b"
+
+  -
+    input:
+      bytes: [ 0xd5, 0x16, 0x2e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 5, vgx2], { z22.b, z23.b }, z14.b"
+
+  -
+    input:
+      bytes: [ 0xd5, 0x16, 0x2e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 5, vgx2], { z22.b, z23.b }, z14.b"
+
+  -
+    input:
+      bytes: [ 0x32, 0x75, 0x21, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w11, 2, vgx2], { z9.b, z10.b }, z1.b"
+
+  -
+    input:
+      bytes: [ 0x32, 0x75, 0x21, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w11, 2, vgx2], { z9.b, z10.b }, z1.b"
+
+  -
+    input:
+      bytes: [ 0x97, 0x35, 0x2b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w9, 7, vgx2], { z12.b, z13.b }, z11.b"
+
+  -
+    input:
+      bytes: [ 0x97, 0x35, 0x2b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w9, 7, vgx2], { z12.b, z13.b }, z11.b"
+
+  -
+    input:
+      bytes: [ 0x10, 0x14, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 0, vgx2], { z0.b, z1.b }, { z0.b, z1.b }"
+
+  -
+    input:
+      bytes: [ 0x10, 0x14, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 0, vgx2], { z0.b, z1.b }, { z0.b, z1.b }"
+
+  -
+    input:
+      bytes: [ 0x55, 0x55, 0xb4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w10, 5, vgx2], { z10.b, z11.b }, { z20.b, z21.b }"
+
+  -
+    input:
+      bytes: [ 0x55, 0x55, 0xb4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w10, 5, vgx2], { z10.b, z11.b }, { z20.b, z21.b }"
+
+  -
+    input:
+      bytes: [ 0x97, 0x75, 0xa8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w11, 7, vgx2], { z12.b, z13.b }, { z8.b, z9.b }"
+
+  -
+    input:
+      bytes: [ 0x97, 0x75, 0xa8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w11, 7, vgx2], { z12.b, z13.b }, { z8.b, z9.b }"
+
+  -
+    input:
+      bytes: [ 0xd7, 0x77, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w11, 7, vgx2], { z30.b, z31.b }, { z30.b, z31.b }"
+
+  -
+    input:
+      bytes: [ 0xd7, 0x77, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w11, 7, vgx2], { z30.b, z31.b }, { z30.b, z31.b }"
+
+  -
+    input:
+      bytes: [ 0x15, 0x16, 0xb0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 5, vgx2], { z16.b, z17.b }, { z16.b, z17.b }"
+
+  -
+    input:
+      bytes: [ 0x15, 0x16, 0xb0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 5, vgx2], { z16.b, z17.b }, { z16.b, z17.b }"
+
+  -
+    input:
+      bytes: [ 0x11, 0x14, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 1, vgx2], { z0.b, z1.b }, { z30.b, z31.b }"
+
+  -
+    input:
+      bytes: [ 0x11, 0x14, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 1, vgx2], { z0.b, z1.b }, { z30.b, z31.b }"
+
+  -
+    input:
+      bytes: [ 0x50, 0x56, 0xb4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w10, 0, vgx2], { z18.b, z19.b }, { z20.b, z21.b }"
+
+  -
+    input:
+      bytes: [ 0x50, 0x56, 0xb4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w10, 0, vgx2], { z18.b, z19.b }, { z20.b, z21.b }"
+
+  -
+    input:
+      bytes: [ 0x90, 0x15, 0xa2, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 0, vgx2], { z12.b, z13.b }, { z2.b, z3.b }"
+
+  -
+    input:
+      bytes: [ 0x90, 0x15, 0xa2, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 0, vgx2], { z12.b, z13.b }, { z2.b, z3.b }"
+
+  -
+    input:
+      bytes: [ 0x11, 0x54, 0xba, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w10, 1, vgx2], { z0.b, z1.b }, { z26.b, z27.b }"
+
+  -
+    input:
+      bytes: [ 0x11, 0x54, 0xba, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w10, 1, vgx2], { z0.b, z1.b }, { z26.b, z27.b }"
+
+  -
+    input:
+      bytes: [ 0xd5, 0x16, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 5, vgx2], { z22.b, z23.b }, { z30.b, z31.b }"
+
+  -
+    input:
+      bytes: [ 0xd5, 0x16, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 5, vgx2], { z22.b, z23.b }, { z30.b, z31.b }"
+
+  -
+    input:
+      bytes: [ 0x12, 0x75, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w11, 2, vgx2], { z8.b, z9.b }, { z0.b, z1.b }"
+
+  -
+    input:
+      bytes: [ 0x12, 0x75, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w11, 2, vgx2], { z8.b, z9.b }, { z0.b, z1.b }"
+
+  -
+    input:
+      bytes: [ 0x97, 0x35, 0xaa, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w9, 7, vgx2], { z12.b, z13.b }, { z10.b, z11.b }"
+
+  -
+    input:
+      bytes: [ 0x97, 0x35, 0xaa, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w9, 7, vgx2], { z12.b, z13.b }, { z10.b, z11.b }"
+
+  -
+    input:
+      bytes: [ 0x10, 0x14, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w8, 0, vgx2], { z0.h, z1.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x10, 0x14, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w8, 0, vgx2], { z0.h, z1.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x55, 0x55, 0x65, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w10, 5, vgx2], { z10.h, z11.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0x55, 0x55, 0x65, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w10, 5, vgx2], { z10.h, z11.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x75, 0x68, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w11, 7, vgx2], { z13.h, z14.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x75, 0x68, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w11, 7, vgx2], { z13.h, z14.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0xf7, 0x77, 0x6f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w11, 7, vgx2], { z31.h, z0.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0xf7, 0x77, 0x6f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w11, 7, vgx2], { z31.h, z0.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0x35, 0x16, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w8, 5, vgx2], { z17.h, z18.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x35, 0x16, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w8, 5, vgx2], { z17.h, z18.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x31, 0x14, 0x6e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w8, 1, vgx2], { z1.h, z2.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x31, 0x14, 0x6e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w8, 1, vgx2], { z1.h, z2.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x70, 0x56, 0x64, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w10, 0, vgx2], { z19.h, z20.h }, z4.h"
+
+  -
+    input:
+      bytes: [ 0x70, 0x56, 0x64, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w10, 0, vgx2], { z19.h, z20.h }, z4.h"
+
+  -
+    input:
+      bytes: [ 0x90, 0x15, 0x62, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w8, 0, vgx2], { z12.h, z13.h }, z2.h"
+
+  -
+    input:
+      bytes: [ 0x90, 0x15, 0x62, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w8, 0, vgx2], { z12.h, z13.h }, z2.h"
+
+  -
+    input:
+      bytes: [ 0x31, 0x54, 0x6a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w10, 1, vgx2], { z1.h, z2.h }, z10.h"
+
+  -
+    input:
+      bytes: [ 0x31, 0x54, 0x6a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w10, 1, vgx2], { z1.h, z2.h }, z10.h"
+
+  -
+    input:
+      bytes: [ 0xd5, 0x16, 0x6e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w8, 5, vgx2], { z22.h, z23.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0xd5, 0x16, 0x6e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w8, 5, vgx2], { z22.h, z23.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x32, 0x75, 0x61, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w11, 2, vgx2], { z9.h, z10.h }, z1.h"
+
+  -
+    input:
+      bytes: [ 0x32, 0x75, 0x61, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w11, 2, vgx2], { z9.h, z10.h }, z1.h"
+
+  -
+    input:
+      bytes: [ 0x97, 0x35, 0x6b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w9, 7, vgx2], { z12.h, z13.h }, z11.h"
+
+  -
+    input:
+      bytes: [ 0x97, 0x35, 0x6b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w9, 7, vgx2], { z12.h, z13.h }, z11.h"
+
+  -
+    input:
+      bytes: [ 0x97, 0x35, 0x6b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w9, 7, vgx2], { z12.h, z13.h }, z11.h"
+
+  -
+    input:
+      bytes: [ 0x10, 0x14, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w8, 0, vgx2], { z0.h, z1.h }, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x10, 0x14, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w8, 0, vgx2], { z0.h, z1.h }, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x55, 0x55, 0xf4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w10, 5, vgx2], { z10.h, z11.h }, { z20.h, z21.h }"
+
+  -
+    input:
+      bytes: [ 0x55, 0x55, 0xf4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w10, 5, vgx2], { z10.h, z11.h }, { z20.h, z21.h }"
+
+  -
+    input:
+      bytes: [ 0x97, 0x75, 0xe8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w11, 7, vgx2], { z12.h, z13.h }, { z8.h, z9.h }"
+
+  -
+    input:
+      bytes: [ 0x97, 0x75, 0xe8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w11, 7, vgx2], { z12.h, z13.h }, { z8.h, z9.h }"
+
+  -
+    input:
+      bytes: [ 0xd7, 0x77, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w11, 7, vgx2], { z30.h, z31.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0xd7, 0x77, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w11, 7, vgx2], { z30.h, z31.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x15, 0x16, 0xf0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w8, 5, vgx2], { z16.h, z17.h }, { z16.h, z17.h }"
+
+  -
+    input:
+      bytes: [ 0x15, 0x16, 0xf0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w8, 5, vgx2], { z16.h, z17.h }, { z16.h, z17.h }"
+
+  -
+    input:
+      bytes: [ 0x11, 0x14, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w8, 1, vgx2], { z0.h, z1.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x11, 0x14, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w8, 1, vgx2], { z0.h, z1.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x50, 0x56, 0xf4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w10, 0, vgx2], { z18.h, z19.h }, { z20.h, z21.h }"
+
+  -
+    input:
+      bytes: [ 0x50, 0x56, 0xf4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w10, 0, vgx2], { z18.h, z19.h }, { z20.h, z21.h }"
+
+  -
+    input:
+      bytes: [ 0x90, 0x15, 0xe2, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w8, 0, vgx2], { z12.h, z13.h }, { z2.h, z3.h }"
+
+  -
+    input:
+      bytes: [ 0x90, 0x15, 0xe2, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w8, 0, vgx2], { z12.h, z13.h }, { z2.h, z3.h }"
+
+  -
+    input:
+      bytes: [ 0x11, 0x54, 0xfa, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w10, 1, vgx2], { z0.h, z1.h }, { z26.h, z27.h }"
+
+  -
+    input:
+      bytes: [ 0x11, 0x54, 0xfa, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w10, 1, vgx2], { z0.h, z1.h }, { z26.h, z27.h }"
+
+  -
+    input:
+      bytes: [ 0xd5, 0x16, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w8, 5, vgx2], { z22.h, z23.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0xd5, 0x16, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w8, 5, vgx2], { z22.h, z23.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x12, 0x75, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w11, 2, vgx2], { z8.h, z9.h }, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x12, 0x75, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w11, 2, vgx2], { z8.h, z9.h }, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x97, 0x35, 0xea, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w9, 7, vgx2], { z12.h, z13.h }, { z10.h, z11.h }"
+
+  -
+    input:
+      bytes: [ 0x97, 0x35, 0xea, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w9, 7, vgx2], { z12.h, z13.h }, { z10.h, z11.h }"
+
+  -
+    input:
+      bytes: [ 0x10, 0x14, 0x30, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 0, vgx4], { z0.b - z3.b }, z0.b"
+
+  -
+    input:
+      bytes: [ 0x10, 0x14, 0x30, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 0, vgx4], { z0.b - z3.b }, z0.b"
+
+  -
+    input:
+      bytes: [ 0x55, 0x55, 0x35, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w10, 5, vgx4], { z10.b - z13.b }, z5.b"
+
+  -
+    input:
+      bytes: [ 0x55, 0x55, 0x35, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w10, 5, vgx4], { z10.b - z13.b }, z5.b"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x75, 0x38, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w11, 7, vgx4], { z13.b - z16.b }, z8.b"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x75, 0x38, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w11, 7, vgx4], { z13.b - z16.b }, z8.b"
+
+  -
+    input:
+      bytes: [ 0xf7, 0x77, 0x3f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w11, 7, vgx4], { z31.b, z0.b, z1.b, z2.b }, z15.b"
+
+  -
+    input:
+      bytes: [ 0xf7, 0x77, 0x3f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w11, 7, vgx4], { z31.b, z0.b, z1.b, z2.b }, z15.b"
+
+  -
+    input:
+      bytes: [ 0x35, 0x16, 0x30, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 5, vgx4], { z17.b - z20.b }, z0.b"
+
+  -
+    input:
+      bytes: [ 0x35, 0x16, 0x30, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 5, vgx4], { z17.b - z20.b }, z0.b"
+
+  -
+    input:
+      bytes: [ 0x31, 0x14, 0x3e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 1, vgx4], { z1.b - z4.b }, z14.b"
+
+  -
+    input:
+      bytes: [ 0x31, 0x14, 0x3e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 1, vgx4], { z1.b - z4.b }, z14.b"
+
+  -
+    input:
+      bytes: [ 0x70, 0x56, 0x34, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w10, 0, vgx4], { z19.b - z22.b }, z4.b"
+
+  -
+    input:
+      bytes: [ 0x70, 0x56, 0x34, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w10, 0, vgx4], { z19.b - z22.b }, z4.b"
+
+  -
+    input:
+      bytes: [ 0x90, 0x15, 0x32, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 0, vgx4], { z12.b - z15.b }, z2.b"
+
+  -
+    input:
+      bytes: [ 0x90, 0x15, 0x32, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 0, vgx4], { z12.b - z15.b }, z2.b"
+
+  -
+    input:
+      bytes: [ 0x31, 0x54, 0x3a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w10, 1, vgx4], { z1.b - z4.b }, z10.b"
+
+  -
+    input:
+      bytes: [ 0x31, 0x54, 0x3a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w10, 1, vgx4], { z1.b - z4.b }, z10.b"
+
+  -
+    input:
+      bytes: [ 0xd5, 0x16, 0x3e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 5, vgx4], { z22.b - z25.b }, z14.b"
+
+  -
+    input:
+      bytes: [ 0xd5, 0x16, 0x3e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 5, vgx4], { z22.b - z25.b }, z14.b"
+
+  -
+    input:
+      bytes: [ 0x32, 0x75, 0x31, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w11, 2, vgx4], { z9.b - z12.b }, z1.b"
+
+  -
+    input:
+      bytes: [ 0x32, 0x75, 0x31, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w11, 2, vgx4], { z9.b - z12.b }, z1.b"
+
+  -
+    input:
+      bytes: [ 0x97, 0x35, 0x3b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w9, 7, vgx4], { z12.b - z15.b }, z11.b"
+
+  -
+    input:
+      bytes: [ 0x97, 0x35, 0x3b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w9, 7, vgx4], { z12.b - z15.b }, z11.b"
+
+  -
+    input:
+      bytes: [ 0x10, 0x14, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 0, vgx4], { z0.b - z3.b }, { z0.b - z3.b }"
+
+  -
+    input:
+      bytes: [ 0x10, 0x14, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 0, vgx4], { z0.b - z3.b }, { z0.b - z3.b }"
+
+  -
+    input:
+      bytes: [ 0x15, 0x55, 0xb5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w10, 5, vgx4], { z8.b - z11.b }, { z20.b - z23.b }"
+
+  -
+    input:
+      bytes: [ 0x15, 0x55, 0xb5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w10, 5, vgx4], { z8.b - z11.b }, { z20.b - z23.b }"
+
+  -
+    input:
+      bytes: [ 0x97, 0x75, 0xa9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w11, 7, vgx4], { z12.b - z15.b }, { z8.b - z11.b }"
+
+  -
+    input:
+      bytes: [ 0x97, 0x75, 0xa9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w11, 7, vgx4], { z12.b - z15.b }, { z8.b - z11.b }"
+
+  -
+    input:
+      bytes: [ 0x97, 0x77, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w11, 7, vgx4], { z28.b - z31.b }, { z28.b - z31.b }"
+
+  -
+    input:
+      bytes: [ 0x97, 0x77, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w11, 7, vgx4], { z28.b - z31.b }, { z28.b - z31.b }"
+
+  -
+    input:
+      bytes: [ 0x15, 0x16, 0xb1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 5, vgx4], { z16.b - z19.b }, { z16.b - z19.b }"
+
+  -
+    input:
+      bytes: [ 0x15, 0x16, 0xb1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 5, vgx4], { z16.b - z19.b }, { z16.b - z19.b }"
+
+  -
+    input:
+      bytes: [ 0x11, 0x14, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 1, vgx4], { z0.b - z3.b }, { z28.b - z31.b }"
+
+  -
+    input:
+      bytes: [ 0x11, 0x14, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 1, vgx4], { z0.b - z3.b }, { z28.b - z31.b }"
+
+  -
+    input:
+      bytes: [ 0x10, 0x56, 0xb5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w10, 0, vgx4], { z16.b - z19.b }, { z20.b - z23.b }"
+
+  -
+    input:
+      bytes: [ 0x10, 0x56, 0xb5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w10, 0, vgx4], { z16.b - z19.b }, { z20.b - z23.b }"
+
+  -
+    input:
+      bytes: [ 0x90, 0x15, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 0, vgx4], { z12.b - z15.b }, { z0.b - z3.b }"
+
+  -
+    input:
+      bytes: [ 0x90, 0x15, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 0, vgx4], { z12.b - z15.b }, { z0.b - z3.b }"
+
+  -
+    input:
+      bytes: [ 0x11, 0x54, 0xb9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w10, 1, vgx4], { z0.b - z3.b }, { z24.b - z27.b }"
+
+  -
+    input:
+      bytes: [ 0x11, 0x54, 0xb9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w10, 1, vgx4], { z0.b - z3.b }, { z24.b - z27.b }"
+
+  -
+    input:
+      bytes: [ 0x95, 0x16, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 5, vgx4], { z20.b - z23.b }, { z28.b - z31.b }"
+
+  -
+    input:
+      bytes: [ 0x95, 0x16, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w8, 5, vgx4], { z20.b - z23.b }, { z28.b - z31.b }"
+
+  -
+    input:
+      bytes: [ 0x12, 0x75, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w11, 2, vgx4], { z8.b - z11.b }, { z0.b - z3.b }"
+
+  -
+    input:
+      bytes: [ 0x12, 0x75, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w11, 2, vgx4], { z8.b - z11.b }, { z0.b - z3.b }"
+
+  -
+    input:
+      bytes: [ 0x97, 0x35, 0xa9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w9, 7, vgx4], { z12.b - z15.b }, { z8.b - z11.b }"
+
+  -
+    input:
+      bytes: [ 0x97, 0x35, 0xa9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.s[w9, 7, vgx4], { z12.b - z15.b }, { z8.b - z11.b }"
+
+  -
+    input:
+      bytes: [ 0x10, 0x14, 0x70, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w8, 0, vgx4], { z0.h - z3.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x10, 0x14, 0x70, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w8, 0, vgx4], { z0.h - z3.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x55, 0x55, 0x75, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w10, 5, vgx4], { z10.h - z13.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0x55, 0x55, 0x75, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w10, 5, vgx4], { z10.h - z13.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x75, 0x78, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w11, 7, vgx4], { z13.h - z16.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x75, 0x78, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w11, 7, vgx4], { z13.h - z16.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0xf7, 0x77, 0x7f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w11, 7, vgx4], { z31.h, z0.h, z1.h, z2.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0xf7, 0x77, 0x7f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w11, 7, vgx4], { z31.h, z0.h, z1.h, z2.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0x35, 0x16, 0x70, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w8, 5, vgx4], { z17.h - z20.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x35, 0x16, 0x70, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w8, 5, vgx4], { z17.h - z20.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x31, 0x14, 0x7e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w8, 1, vgx4], { z1.h - z4.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x31, 0x14, 0x7e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w8, 1, vgx4], { z1.h - z4.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x70, 0x56, 0x74, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w10, 0, vgx4], { z19.h - z22.h }, z4.h"
+
+  -
+    input:
+      bytes: [ 0x70, 0x56, 0x74, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w10, 0, vgx4], { z19.h - z22.h }, z4.h"
+
+  -
+    input:
+      bytes: [ 0x90, 0x15, 0x72, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w8, 0, vgx4], { z12.h - z15.h }, z2.h"
+
+  -
+    input:
+      bytes: [ 0x90, 0x15, 0x72, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w8, 0, vgx4], { z12.h - z15.h }, z2.h"
+
+  -
+    input:
+      bytes: [ 0x31, 0x54, 0x7a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w10, 1, vgx4], { z1.h - z4.h }, z10.h"
+
+  -
+    input:
+      bytes: [ 0x31, 0x54, 0x7a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w10, 1, vgx4], { z1.h - z4.h }, z10.h"
+
+  -
+    input:
+      bytes: [ 0xd5, 0x16, 0x7e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w8, 5, vgx4], { z22.h - z25.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0xd5, 0x16, 0x7e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w8, 5, vgx4], { z22.h - z25.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x32, 0x75, 0x71, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w11, 2, vgx4], { z9.h - z12.h }, z1.h"
+
+  -
+    input:
+      bytes: [ 0x32, 0x75, 0x71, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w11, 2, vgx4], { z9.h - z12.h }, z1.h"
+
+  -
+    input:
+      bytes: [ 0x97, 0x35, 0x7b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w9, 7, vgx4], { z12.h - z15.h }, z11.h"
+
+  -
+    input:
+      bytes: [ 0x97, 0x35, 0x7b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w9, 7, vgx4], { z12.h - z15.h }, z11.h"
+
+  -
+    input:
+      bytes: [ 0x10, 0x14, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w8, 0, vgx4], { z0.h - z3.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x10, 0x14, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w8, 0, vgx4], { z0.h - z3.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x15, 0x55, 0xf5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w10, 5, vgx4], { z8.h - z11.h }, { z20.h - z23.h }"
+
+  -
+    input:
+      bytes: [ 0x15, 0x55, 0xf5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w10, 5, vgx4], { z8.h - z11.h }, { z20.h - z23.h }"
+
+  -
+    input:
+      bytes: [ 0x97, 0x75, 0xe9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w11, 7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }"
+
+  -
+    input:
+      bytes: [ 0x97, 0x75, 0xe9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w11, 7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }"
+
+  -
+    input:
+      bytes: [ 0x97, 0x77, 0xfd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w11, 7, vgx4], { z28.h - z31.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x97, 0x77, 0xfd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w11, 7, vgx4], { z28.h - z31.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x15, 0x16, 0xf1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w8, 5, vgx4], { z16.h - z19.h }, { z16.h - z19.h }"
+
+  -
+    input:
+      bytes: [ 0x15, 0x16, 0xf1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w8, 5, vgx4], { z16.h - z19.h }, { z16.h - z19.h }"
+
+  -
+    input:
+      bytes: [ 0x11, 0x14, 0xfd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w8, 1, vgx4], { z0.h - z3.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x11, 0x14, 0xfd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w8, 1, vgx4], { z0.h - z3.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x10, 0x56, 0xf5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w10, 0, vgx4], { z16.h - z19.h }, { z20.h - z23.h }"
+
+  -
+    input:
+      bytes: [ 0x10, 0x56, 0xf5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w10, 0, vgx4], { z16.h - z19.h }, { z20.h - z23.h }"
+
+  -
+    input:
+      bytes: [ 0x90, 0x15, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w8, 0, vgx4], { z12.h - z15.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x90, 0x15, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w8, 0, vgx4], { z12.h - z15.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x11, 0x54, 0xf9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w10, 1, vgx4], { z0.h - z3.h }, { z24.h - z27.h }"
+
+  -
+    input:
+      bytes: [ 0x11, 0x54, 0xf9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w10, 1, vgx4], { z0.h - z3.h }, { z24.h - z27.h }"
+
+  -
+    input:
+      bytes: [ 0x95, 0x16, 0xfd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w8, 5, vgx4], { z20.h - z23.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x95, 0x16, 0xfd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w8, 5, vgx4], { z20.h - z23.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x12, 0x75, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w11, 2, vgx4], { z8.h - z11.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x12, 0x75, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w11, 2, vgx4], { z8.h - z11.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x97, 0x35, 0xe9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w9, 7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }"
+
+  -
+    input:
+      bytes: [ 0x97, 0x35, 0xe9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot za.d[w9, 7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }"
diff --git a/tests/MC/AArch64/SME2/umax.s.yaml b/tests/MC/AArch64/SME2/umax.s.yaml
new file mode 100644
index 000000000..88edc9339
--- /dev/null
+++ b/tests/MC/AArch64/SME2/umax.s.yaml
@@ -0,0 +1,640 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x01, 0xa0, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax { z0.h, z1.h }, { z0.h, z1.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x15, 0xa0, 0x65, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax { z20.h, z21.h }, { z20.h, z21.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0x17, 0xa0, 0x68, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax { z22.h, z23.h }, { z22.h, z23.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0x1f, 0xa0, 0x6f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax { z30.h, z31.h }, { z30.h, z31.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0x01, 0xb0, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax { z0.h, z1.h }, { z0.h, z1.h }, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x15, 0xb0, 0x74, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax { z20.h, z21.h }, { z20.h, z21.h }, { z20.h, z21.h }"
+
+  -
+    input:
+      bytes: [ 0x17, 0xb0, 0x68, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax { z22.h, z23.h }, { z22.h, z23.h }, { z8.h, z9.h }"
+
+  -
+    input:
+      bytes: [ 0x1f, 0xb0, 0x7e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax { z30.h, z31.h }, { z30.h, z31.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x01, 0xa0, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax { z0.s, z1.s }, { z0.s, z1.s }, z0.s"
+
+  -
+    input:
+      bytes: [ 0x15, 0xa0, 0xa5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax { z20.s, z21.s }, { z20.s, z21.s }, z5.s"
+
+  -
+    input:
+      bytes: [ 0x17, 0xa0, 0xa8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax { z22.s, z23.s }, { z22.s, z23.s }, z8.s"
+
+  -
+    input:
+      bytes: [ 0x1f, 0xa0, 0xaf, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax { z30.s, z31.s }, { z30.s, z31.s }, z15.s"
+
+  -
+    input:
+      bytes: [ 0x01, 0xb0, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax { z0.s, z1.s }, { z0.s, z1.s }, { z0.s, z1.s }"
+
+  -
+    input:
+      bytes: [ 0x15, 0xb0, 0xb4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax { z20.s, z21.s }, { z20.s, z21.s }, { z20.s, z21.s }"
+
+  -
+    input:
+      bytes: [ 0x17, 0xb0, 0xa8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax { z22.s, z23.s }, { z22.s, z23.s }, { z8.s, z9.s }"
+
+  -
+    input:
+      bytes: [ 0x1f, 0xb0, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax { z30.s, z31.s }, { z30.s, z31.s }, { z30.s, z31.s }"
+
+  -
+    input:
+      bytes: [ 0x01, 0xa0, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax { z0.d, z1.d }, { z0.d, z1.d }, z0.d"
+
+  -
+    input:
+      bytes: [ 0x15, 0xa0, 0xe5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax { z20.d, z21.d }, { z20.d, z21.d }, z5.d"
+
+  -
+    input:
+      bytes: [ 0x17, 0xa0, 0xe8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax { z22.d, z23.d }, { z22.d, z23.d }, z8.d"
+
+  -
+    input:
+      bytes: [ 0x1f, 0xa0, 0xef, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax { z30.d, z31.d }, { z30.d, z31.d }, z15.d"
+
+  -
+    input:
+      bytes: [ 0x01, 0xb0, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax { z0.d, z1.d }, { z0.d, z1.d }, { z0.d, z1.d }"
+
+  -
+    input:
+      bytes: [ 0x15, 0xb0, 0xf4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax { z20.d, z21.d }, { z20.d, z21.d }, { z20.d, z21.d }"
+
+  -
+    input:
+      bytes: [ 0x17, 0xb0, 0xe8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax { z22.d, z23.d }, { z22.d, z23.d }, { z8.d, z9.d }"
+
+  -
+    input:
+      bytes: [ 0x1f, 0xb0, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax { z30.d, z31.d }, { z30.d, z31.d }, { z30.d, z31.d }"
+
+  -
+    input:
+      bytes: [ 0x01, 0xa0, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax { z0.b, z1.b }, { z0.b, z1.b }, z0.b"
+
+  -
+    input:
+      bytes: [ 0x15, 0xa0, 0x25, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax { z20.b, z21.b }, { z20.b, z21.b }, z5.b"
+
+  -
+    input:
+      bytes: [ 0x17, 0xa0, 0x28, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax { z22.b, z23.b }, { z22.b, z23.b }, z8.b"
+
+  -
+    input:
+      bytes: [ 0x1f, 0xa0, 0x2f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax { z30.b, z31.b }, { z30.b, z31.b }, z15.b"
+
+  -
+    input:
+      bytes: [ 0x01, 0xb0, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax { z0.b, z1.b }, { z0.b, z1.b }, { z0.b, z1.b }"
+
+  -
+    input:
+      bytes: [ 0x15, 0xb0, 0x34, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax { z20.b, z21.b }, { z20.b, z21.b }, { z20.b, z21.b }"
+
+  -
+    input:
+      bytes: [ 0x17, 0xb0, 0x28, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax { z22.b, z23.b }, { z22.b, z23.b }, { z8.b, z9.b }"
+
+  -
+    input:
+      bytes: [ 0x1f, 0xb0, 0x3e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax { z30.b, z31.b }, { z30.b, z31.b }, { z30.b, z31.b }"
+
+  -
+    input:
+      bytes: [ 0x01, 0xa8, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax { z0.h - z3.h }, { z0.h - z3.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x15, 0xa8, 0x65, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax { z20.h - z23.h }, { z20.h - z23.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0x15, 0xa8, 0x68, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax { z20.h - z23.h }, { z20.h - z23.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0x1d, 0xa8, 0x6f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax { z28.h - z31.h }, { z28.h - z31.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0x01, 0xb8, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax { z0.h - z3.h }, { z0.h - z3.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x15, 0xb8, 0x74, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax { z20.h - z23.h }, { z20.h - z23.h }, { z20.h - z23.h }"
+
+  -
+    input:
+      bytes: [ 0x15, 0xb8, 0x68, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax { z20.h - z23.h }, { z20.h - z23.h }, { z8.h - z11.h }"
+
+  -
+    input:
+      bytes: [ 0x1d, 0xb8, 0x7c, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax { z28.h - z31.h }, { z28.h - z31.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x01, 0xa8, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax { z0.s - z3.s }, { z0.s - z3.s }, z0.s"
+
+  -
+    input:
+      bytes: [ 0x15, 0xa8, 0xa5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax { z20.s - z23.s }, { z20.s - z23.s }, z5.s"
+
+  -
+    input:
+      bytes: [ 0x15, 0xa8, 0xa8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax { z20.s - z23.s }, { z20.s - z23.s }, z8.s"
+
+  -
+    input:
+      bytes: [ 0x1d, 0xa8, 0xaf, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax { z28.s - z31.s }, { z28.s - z31.s }, z15.s"
+
+  -
+    input:
+      bytes: [ 0x01, 0xb8, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax { z0.s - z3.s }, { z0.s - z3.s }, { z0.s - z3.s }"
+
+  -
+    input:
+      bytes: [ 0x15, 0xb8, 0xb4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax { z20.s - z23.s }, { z20.s - z23.s }, { z20.s - z23.s }"
+
+  -
+    input:
+      bytes: [ 0x15, 0xb8, 0xa8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax { z20.s - z23.s }, { z20.s - z23.s }, { z8.s - z11.s }"
+
+  -
+    input:
+      bytes: [ 0x1d, 0xb8, 0xbc, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax { z28.s - z31.s }, { z28.s - z31.s }, { z28.s - z31.s }"
+
+  -
+    input:
+      bytes: [ 0x01, 0xa8, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax { z0.d - z3.d }, { z0.d - z3.d }, z0.d"
+
+  -
+    input:
+      bytes: [ 0x15, 0xa8, 0xe5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax { z20.d - z23.d }, { z20.d - z23.d }, z5.d"
+
+  -
+    input:
+      bytes: [ 0x15, 0xa8, 0xe8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax { z20.d - z23.d }, { z20.d - z23.d }, z8.d"
+
+  -
+    input:
+      bytes: [ 0x1d, 0xa8, 0xef, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax { z28.d - z31.d }, { z28.d - z31.d }, z15.d"
+
+  -
+    input:
+      bytes: [ 0x01, 0xb8, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax { z0.d - z3.d }, { z0.d - z3.d }, { z0.d - z3.d }"
+
+  -
+    input:
+      bytes: [ 0x15, 0xb8, 0xf4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax { z20.d - z23.d }, { z20.d - z23.d }, { z20.d - z23.d }"
+
+  -
+    input:
+      bytes: [ 0x15, 0xb8, 0xe8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax { z20.d - z23.d }, { z20.d - z23.d }, { z8.d - z11.d }"
+
+  -
+    input:
+      bytes: [ 0x1d, 0xb8, 0xfc, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax { z28.d - z31.d }, { z28.d - z31.d }, { z28.d - z31.d }"
+
+  -
+    input:
+      bytes: [ 0x01, 0xa8, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax { z0.b - z3.b }, { z0.b - z3.b }, z0.b"
+
+  -
+    input:
+      bytes: [ 0x15, 0xa8, 0x25, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax { z20.b - z23.b }, { z20.b - z23.b }, z5.b"
+
+  -
+    input:
+      bytes: [ 0x15, 0xa8, 0x28, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax { z20.b - z23.b }, { z20.b - z23.b }, z8.b"
+
+  -
+    input:
+      bytes: [ 0x1d, 0xa8, 0x2f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax { z28.b - z31.b }, { z28.b - z31.b }, z15.b"
+
+  -
+    input:
+      bytes: [ 0x01, 0xb8, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax { z0.b - z3.b }, { z0.b - z3.b }, { z0.b - z3.b }"
+
+  -
+    input:
+      bytes: [ 0x15, 0xb8, 0x34, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax { z20.b - z23.b }, { z20.b - z23.b }, { z20.b - z23.b }"
+
+  -
+    input:
+      bytes: [ 0x15, 0xb8, 0x28, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax { z20.b - z23.b }, { z20.b - z23.b }, { z8.b - z11.b }"
+
+  -
+    input:
+      bytes: [ 0x1d, 0xb8, 0x3c, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax { z28.b - z31.b }, { z28.b - z31.b }, { z28.b - z31.b }"
diff --git a/tests/MC/AArch64/SME2/umin.s.yaml b/tests/MC/AArch64/SME2/umin.s.yaml
new file mode 100644
index 000000000..bf51a548a
--- /dev/null
+++ b/tests/MC/AArch64/SME2/umin.s.yaml
@@ -0,0 +1,640 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x21, 0xa0, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin { z0.h, z1.h }, { z0.h, z1.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x35, 0xa0, 0x65, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin { z20.h, z21.h }, { z20.h, z21.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0x37, 0xa0, 0x68, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin { z22.h, z23.h }, { z22.h, z23.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0x3f, 0xa0, 0x6f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin { z30.h, z31.h }, { z30.h, z31.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0x21, 0xb0, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin { z0.h, z1.h }, { z0.h, z1.h }, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x35, 0xb0, 0x74, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin { z20.h, z21.h }, { z20.h, z21.h }, { z20.h, z21.h }"
+
+  -
+    input:
+      bytes: [ 0x37, 0xb0, 0x68, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin { z22.h, z23.h }, { z22.h, z23.h }, { z8.h, z9.h }"
+
+  -
+    input:
+      bytes: [ 0x3f, 0xb0, 0x7e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin { z30.h, z31.h }, { z30.h, z31.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x21, 0xa0, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin { z0.s, z1.s }, { z0.s, z1.s }, z0.s"
+
+  -
+    input:
+      bytes: [ 0x35, 0xa0, 0xa5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin { z20.s, z21.s }, { z20.s, z21.s }, z5.s"
+
+  -
+    input:
+      bytes: [ 0x37, 0xa0, 0xa8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin { z22.s, z23.s }, { z22.s, z23.s }, z8.s"
+
+  -
+    input:
+      bytes: [ 0x3f, 0xa0, 0xaf, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin { z30.s, z31.s }, { z30.s, z31.s }, z15.s"
+
+  -
+    input:
+      bytes: [ 0x21, 0xb0, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin { z0.s, z1.s }, { z0.s, z1.s }, { z0.s, z1.s }"
+
+  -
+    input:
+      bytes: [ 0x35, 0xb0, 0xb4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin { z20.s, z21.s }, { z20.s, z21.s }, { z20.s, z21.s }"
+
+  -
+    input:
+      bytes: [ 0x37, 0xb0, 0xa8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin { z22.s, z23.s }, { z22.s, z23.s }, { z8.s, z9.s }"
+
+  -
+    input:
+      bytes: [ 0x3f, 0xb0, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin { z30.s, z31.s }, { z30.s, z31.s }, { z30.s, z31.s }"
+
+  -
+    input:
+      bytes: [ 0x21, 0xa0, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin { z0.d, z1.d }, { z0.d, z1.d }, z0.d"
+
+  -
+    input:
+      bytes: [ 0x35, 0xa0, 0xe5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin { z20.d, z21.d }, { z20.d, z21.d }, z5.d"
+
+  -
+    input:
+      bytes: [ 0x37, 0xa0, 0xe8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin { z22.d, z23.d }, { z22.d, z23.d }, z8.d"
+
+  -
+    input:
+      bytes: [ 0x3f, 0xa0, 0xef, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin { z30.d, z31.d }, { z30.d, z31.d }, z15.d"
+
+  -
+    input:
+      bytes: [ 0x21, 0xb0, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin { z0.d, z1.d }, { z0.d, z1.d }, { z0.d, z1.d }"
+
+  -
+    input:
+      bytes: [ 0x35, 0xb0, 0xf4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin { z20.d, z21.d }, { z20.d, z21.d }, { z20.d, z21.d }"
+
+  -
+    input:
+      bytes: [ 0x37, 0xb0, 0xe8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin { z22.d, z23.d }, { z22.d, z23.d }, { z8.d, z9.d }"
+
+  -
+    input:
+      bytes: [ 0x3f, 0xb0, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin { z30.d, z31.d }, { z30.d, z31.d }, { z30.d, z31.d }"
+
+  -
+    input:
+      bytes: [ 0x21, 0xa0, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin { z0.b, z1.b }, { z0.b, z1.b }, z0.b"
+
+  -
+    input:
+      bytes: [ 0x35, 0xa0, 0x25, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin { z20.b, z21.b }, { z20.b, z21.b }, z5.b"
+
+  -
+    input:
+      bytes: [ 0x37, 0xa0, 0x28, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin { z22.b, z23.b }, { z22.b, z23.b }, z8.b"
+
+  -
+    input:
+      bytes: [ 0x3f, 0xa0, 0x2f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin { z30.b, z31.b }, { z30.b, z31.b }, z15.b"
+
+  -
+    input:
+      bytes: [ 0x21, 0xb0, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin { z0.b, z1.b }, { z0.b, z1.b }, { z0.b, z1.b }"
+
+  -
+    input:
+      bytes: [ 0x35, 0xb0, 0x34, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin { z20.b, z21.b }, { z20.b, z21.b }, { z20.b, z21.b }"
+
+  -
+    input:
+      bytes: [ 0x37, 0xb0, 0x28, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin { z22.b, z23.b }, { z22.b, z23.b }, { z8.b, z9.b }"
+
+  -
+    input:
+      bytes: [ 0x3f, 0xb0, 0x3e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin { z30.b, z31.b }, { z30.b, z31.b }, { z30.b, z31.b }"
+
+  -
+    input:
+      bytes: [ 0x21, 0xa8, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin { z0.h - z3.h }, { z0.h - z3.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x35, 0xa8, 0x65, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin { z20.h - z23.h }, { z20.h - z23.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0x35, 0xa8, 0x68, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin { z20.h - z23.h }, { z20.h - z23.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0x3d, 0xa8, 0x6f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin { z28.h - z31.h }, { z28.h - z31.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0x21, 0xb8, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin { z0.h - z3.h }, { z0.h - z3.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x35, 0xb8, 0x74, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin { z20.h - z23.h }, { z20.h - z23.h }, { z20.h - z23.h }"
+
+  -
+    input:
+      bytes: [ 0x35, 0xb8, 0x68, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin { z20.h - z23.h }, { z20.h - z23.h }, { z8.h - z11.h }"
+
+  -
+    input:
+      bytes: [ 0x3d, 0xb8, 0x7c, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin { z28.h - z31.h }, { z28.h - z31.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x21, 0xa8, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin { z0.s - z3.s }, { z0.s - z3.s }, z0.s"
+
+  -
+    input:
+      bytes: [ 0x35, 0xa8, 0xa5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin { z20.s - z23.s }, { z20.s - z23.s }, z5.s"
+
+  -
+    input:
+      bytes: [ 0x35, 0xa8, 0xa8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin { z20.s - z23.s }, { z20.s - z23.s }, z8.s"
+
+  -
+    input:
+      bytes: [ 0x3d, 0xa8, 0xaf, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin { z28.s - z31.s }, { z28.s - z31.s }, z15.s"
+
+  -
+    input:
+      bytes: [ 0x21, 0xb8, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin { z0.s - z3.s }, { z0.s - z3.s }, { z0.s - z3.s }"
+
+  -
+    input:
+      bytes: [ 0x35, 0xb8, 0xb4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin { z20.s - z23.s }, { z20.s - z23.s }, { z20.s - z23.s }"
+
+  -
+    input:
+      bytes: [ 0x35, 0xb8, 0xa8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin { z20.s - z23.s }, { z20.s - z23.s }, { z8.s - z11.s }"
+
+  -
+    input:
+      bytes: [ 0x3d, 0xb8, 0xbc, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin { z28.s - z31.s }, { z28.s - z31.s }, { z28.s - z31.s }"
+
+  -
+    input:
+      bytes: [ 0x21, 0xa8, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin { z0.d - z3.d }, { z0.d - z3.d }, z0.d"
+
+  -
+    input:
+      bytes: [ 0x35, 0xa8, 0xe5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin { z20.d - z23.d }, { z20.d - z23.d }, z5.d"
+
+  -
+    input:
+      bytes: [ 0x35, 0xa8, 0xe8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin { z20.d - z23.d }, { z20.d - z23.d }, z8.d"
+
+  -
+    input:
+      bytes: [ 0x3d, 0xa8, 0xef, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin { z28.d - z31.d }, { z28.d - z31.d }, z15.d"
+
+  -
+    input:
+      bytes: [ 0x21, 0xb8, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin { z0.d - z3.d }, { z0.d - z3.d }, { z0.d - z3.d }"
+
+  -
+    input:
+      bytes: [ 0x35, 0xb8, 0xf4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin { z20.d - z23.d }, { z20.d - z23.d }, { z20.d - z23.d }"
+
+  -
+    input:
+      bytes: [ 0x35, 0xb8, 0xe8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin { z20.d - z23.d }, { z20.d - z23.d }, { z8.d - z11.d }"
+
+  -
+    input:
+      bytes: [ 0x3d, 0xb8, 0xfc, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin { z28.d - z31.d }, { z28.d - z31.d }, { z28.d - z31.d }"
+
+  -
+    input:
+      bytes: [ 0x21, 0xa8, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin { z0.b - z3.b }, { z0.b - z3.b }, z0.b"
+
+  -
+    input:
+      bytes: [ 0x35, 0xa8, 0x25, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin { z20.b - z23.b }, { z20.b - z23.b }, z5.b"
+
+  -
+    input:
+      bytes: [ 0x35, 0xa8, 0x28, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin { z20.b - z23.b }, { z20.b - z23.b }, z8.b"
+
+  -
+    input:
+      bytes: [ 0x3d, 0xa8, 0x2f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin { z28.b - z31.b }, { z28.b - z31.b }, z15.b"
+
+  -
+    input:
+      bytes: [ 0x21, 0xb8, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin { z0.b - z3.b }, { z0.b - z3.b }, { z0.b - z3.b }"
+
+  -
+    input:
+      bytes: [ 0x35, 0xb8, 0x34, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin { z20.b - z23.b }, { z20.b - z23.b }, { z20.b - z23.b }"
+
+  -
+    input:
+      bytes: [ 0x35, 0xb8, 0x28, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin { z20.b - z23.b }, { z20.b - z23.b }, { z8.b - z11.b }"
+
+  -
+    input:
+      bytes: [ 0x3d, 0xb8, 0x3c, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin { z28.b - z31.b }, { z28.b - z31.b }, { z28.b - z31.b }"
diff --git a/tests/MC/AArch64/SME2/umlal.s.yaml b/tests/MC/AArch64/SME2/umlal.s.yaml
new file mode 100644
index 000000000..3da9c6d53
--- /dev/null
+++ b/tests/MC/AArch64/SME2/umlal.s.yaml
@@ -0,0 +1,1680 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x10, 0x0c, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w8, 0:1], z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x55, 0x4d, 0x65, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w10, 10:11], z10.h, z5.h"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x6d, 0x68, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w11, 14:15], z13.h, z8.h"
+
+  -
+    input:
+      bytes: [ 0xf7, 0x6f, 0x6f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w11, 14:15], z31.h, z15.h"
+
+  -
+    input:
+      bytes: [ 0x35, 0x0e, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w8, 10:11], z17.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x31, 0x0c, 0x6e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w8, 2:3], z1.h, z14.h"
+
+  -
+    input:
+      bytes: [ 0x70, 0x4e, 0x64, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w10, 0:1], z19.h, z4.h"
+
+  -
+    input:
+      bytes: [ 0x90, 0x0d, 0x62, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w8, 0:1], z12.h, z2.h"
+
+  -
+    input:
+      bytes: [ 0x31, 0x4c, 0x6a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w10, 2:3], z1.h, z10.h"
+
+  -
+    input:
+      bytes: [ 0xd5, 0x0e, 0x6e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w8, 10:11], z22.h, z14.h"
+
+  -
+    input:
+      bytes: [ 0x32, 0x6d, 0x61, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w11, 4:5], z9.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0x97, 0x2d, 0x6b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w9, 14:15], z12.h, z11.h"
+
+  -
+    input:
+      bytes: [ 0x10, 0x10, 0xc0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w8, 0:1], z0.h, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x55, 0xc5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w10, 10:11], z10.h, z5.h[1]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xfd, 0xc8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w11, 14:15], z13.h, z8.h[7]"
+
+  -
+    input:
+      bytes: [ 0xf7, 0xff, 0xcf, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w11, 14:15], z31.h, z15.h[7]"
+
+  -
+    input:
+      bytes: [ 0x35, 0x1e, 0xc0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w8, 10:11], z17.h, z0.h[3]"
+
+  -
+    input:
+      bytes: [ 0x31, 0x94, 0xce, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w8, 2:3], z1.h, z14.h[5]"
+
+  -
+    input:
+      bytes: [ 0x70, 0x56, 0xc4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w10, 0:1], z19.h, z4.h[1]"
+
+  -
+    input:
+      bytes: [ 0x90, 0x19, 0xc2, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w8, 0:1], z12.h, z2.h[2]"
+
+  -
+    input:
+      bytes: [ 0x31, 0xd8, 0xca, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w10, 2:3], z1.h, z10.h[6]"
+
+  -
+    input:
+      bytes: [ 0xd5, 0x1a, 0xce, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w8, 10:11], z22.h, z14.h[2]"
+
+  -
+    input:
+      bytes: [ 0x32, 0xf5, 0xc1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w11, 4:5], z9.h, z1.h[5]"
+
+  -
+    input:
+      bytes: [ 0x97, 0xb9, 0xcb, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w9, 14:15], z12.h, z11.h[6]"
+
+  -
+    input:
+      bytes: [ 0x10, 0x08, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w8, 0:1, vgx2], { z0.h, z1.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x10, 0x08, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w8, 0:1, vgx2], { z0.h, z1.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x51, 0x49, 0x65, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w10, 2:3, vgx2], { z10.h, z11.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0x51, 0x49, 0x65, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w10, 2:3, vgx2], { z10.h, z11.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0xb3, 0x69, 0x68, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w11, 6:7, vgx2], { z13.h, z14.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0xb3, 0x69, 0x68, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w11, 6:7, vgx2], { z13.h, z14.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0xf3, 0x6b, 0x6f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w11, 6:7, vgx2], { z31.h, z0.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0xf3, 0x6b, 0x6f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w11, 6:7, vgx2], { z31.h, z0.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0x31, 0x0a, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w8, 2:3, vgx2], { z17.h, z18.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x31, 0x0a, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w8, 2:3, vgx2], { z17.h, z18.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x31, 0x08, 0x6e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w8, 2:3, vgx2], { z1.h, z2.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x31, 0x08, 0x6e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w8, 2:3, vgx2], { z1.h, z2.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x70, 0x4a, 0x64, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w10, 0:1, vgx2], { z19.h, z20.h }, z4.h"
+
+  -
+    input:
+      bytes: [ 0x70, 0x4a, 0x64, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w10, 0:1, vgx2], { z19.h, z20.h }, z4.h"
+
+  -
+    input:
+      bytes: [ 0x90, 0x09, 0x62, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w8, 0:1, vgx2], { z12.h, z13.h }, z2.h"
+
+  -
+    input:
+      bytes: [ 0x90, 0x09, 0x62, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w8, 0:1, vgx2], { z12.h, z13.h }, z2.h"
+
+  -
+    input:
+      bytes: [ 0x31, 0x48, 0x6a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w10, 2:3, vgx2], { z1.h, z2.h }, z10.h"
+
+  -
+    input:
+      bytes: [ 0x31, 0x48, 0x6a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w10, 2:3, vgx2], { z1.h, z2.h }, z10.h"
+
+  -
+    input:
+      bytes: [ 0xd1, 0x0a, 0x6e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w8, 2:3, vgx2], { z22.h, z23.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0xd1, 0x0a, 0x6e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w8, 2:3, vgx2], { z22.h, z23.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x32, 0x69, 0x61, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w11, 4:5, vgx2], { z9.h, z10.h }, z1.h"
+
+  -
+    input:
+      bytes: [ 0x32, 0x69, 0x61, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w11, 4:5, vgx2], { z9.h, z10.h }, z1.h"
+
+  -
+    input:
+      bytes: [ 0x93, 0x29, 0x6b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w9, 6:7, vgx2], { z12.h, z13.h }, z11.h"
+
+  -
+    input:
+      bytes: [ 0x93, 0x29, 0x6b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w9, 6:7, vgx2], { z12.h, z13.h }, z11.h"
+
+  -
+    input:
+      bytes: [ 0x10, 0x10, 0xd0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w8, 0:1, vgx2], { z0.h, z1.h }, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x10, 0x10, 0xd0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w8, 0:1, vgx2], { z0.h, z1.h }, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x55, 0xd5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w10, 2:3, vgx2], { z10.h, z11.h }, z5.h[3]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x55, 0xd5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w10, 2:3, vgx2], { z10.h, z11.h }, z5.h[3]"
+
+  -
+    input:
+      bytes: [ 0x97, 0x7d, 0xd8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w11, 6:7, vgx2], { z12.h, z13.h }, z8.h[7]"
+
+  -
+    input:
+      bytes: [ 0x97, 0x7d, 0xd8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w11, 6:7, vgx2], { z12.h, z13.h }, z8.h[7]"
+
+  -
+    input:
+      bytes: [ 0xd7, 0x7f, 0xdf, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w11, 6:7, vgx2], { z30.h, z31.h }, z15.h[7]"
+
+  -
+    input:
+      bytes: [ 0xd7, 0x7f, 0xdf, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w11, 6:7, vgx2], { z30.h, z31.h }, z15.h[7]"
+
+  -
+    input:
+      bytes: [ 0x15, 0x1e, 0xd0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w8, 2:3, vgx2], { z16.h, z17.h }, z0.h[7]"
+
+  -
+    input:
+      bytes: [ 0x15, 0x1e, 0xd0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w8, 2:3, vgx2], { z16.h, z17.h }, z0.h[7]"
+
+  -
+    input:
+      bytes: [ 0x11, 0x14, 0xde, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w8, 2:3, vgx2], { z0.h, z1.h }, z14.h[2]"
+
+  -
+    input:
+      bytes: [ 0x11, 0x14, 0xde, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w8, 2:3, vgx2], { z0.h, z1.h }, z14.h[2]"
+
+  -
+    input:
+      bytes: [ 0x50, 0x56, 0xd4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w10, 0:1, vgx2], { z18.h, z19.h }, z4.h[2]"
+
+  -
+    input:
+      bytes: [ 0x50, 0x56, 0xd4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w10, 0:1, vgx2], { z18.h, z19.h }, z4.h[2]"
+
+  -
+    input:
+      bytes: [ 0x90, 0x19, 0xd2, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w8, 0:1, vgx2], { z12.h, z13.h }, z2.h[4]"
+
+  -
+    input:
+      bytes: [ 0x90, 0x19, 0xd2, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w8, 0:1, vgx2], { z12.h, z13.h }, z2.h[4]"
+
+  -
+    input:
+      bytes: [ 0x11, 0x58, 0xda, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w10, 2:3, vgx2], { z0.h, z1.h }, z10.h[4]"
+
+  -
+    input:
+      bytes: [ 0x11, 0x58, 0xda, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w10, 2:3, vgx2], { z0.h, z1.h }, z10.h[4]"
+
+  -
+    input:
+      bytes: [ 0xd5, 0x1a, 0xde, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w8, 2:3, vgx2], { z22.h, z23.h }, z14.h[5]"
+
+  -
+    input:
+      bytes: [ 0xd5, 0x1a, 0xde, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w8, 2:3, vgx2], { z22.h, z23.h }, z14.h[5]"
+
+  -
+    input:
+      bytes: [ 0x12, 0x75, 0xd1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w11, 4:5, vgx2], { z8.h, z9.h }, z1.h[2]"
+
+  -
+    input:
+      bytes: [ 0x12, 0x75, 0xd1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w11, 4:5, vgx2], { z8.h, z9.h }, z1.h[2]"
+
+  -
+    input:
+      bytes: [ 0x97, 0x39, 0xdb, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w9, 6:7, vgx2], { z12.h, z13.h }, z11.h[5]"
+
+  -
+    input:
+      bytes: [ 0x97, 0x39, 0xdb, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w9, 6:7, vgx2], { z12.h, z13.h }, z11.h[5]"
+
+  -
+    input:
+      bytes: [ 0x10, 0x08, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w8, 0:1, vgx2], { z0.h, z1.h }, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x10, 0x08, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w8, 0:1, vgx2], { z0.h, z1.h }, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x51, 0x49, 0xf4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w10, 2:3, vgx2], { z10.h, z11.h }, { z20.h, z21.h }"
+
+  -
+    input:
+      bytes: [ 0x51, 0x49, 0xf4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w10, 2:3, vgx2], { z10.h, z11.h }, { z20.h, z21.h }"
+
+  -
+    input:
+      bytes: [ 0x93, 0x69, 0xe8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w11, 6:7, vgx2], { z12.h, z13.h }, { z8.h, z9.h }"
+
+  -
+    input:
+      bytes: [ 0x93, 0x69, 0xe8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w11, 6:7, vgx2], { z12.h, z13.h }, { z8.h, z9.h }"
+
+  -
+    input:
+      bytes: [ 0xd3, 0x6b, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w11, 6:7, vgx2], { z30.h, z31.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0xd3, 0x6b, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w11, 6:7, vgx2], { z30.h, z31.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x11, 0x0a, 0xf0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w8, 2:3, vgx2], { z16.h, z17.h }, { z16.h, z17.h }"
+
+  -
+    input:
+      bytes: [ 0x11, 0x0a, 0xf0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w8, 2:3, vgx2], { z16.h, z17.h }, { z16.h, z17.h }"
+
+  -
+    input:
+      bytes: [ 0x11, 0x08, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w8, 2:3, vgx2], { z0.h, z1.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x11, 0x08, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w8, 2:3, vgx2], { z0.h, z1.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x50, 0x4a, 0xf4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w10, 0:1, vgx2], { z18.h, z19.h }, { z20.h, z21.h }"
+
+  -
+    input:
+      bytes: [ 0x50, 0x4a, 0xf4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w10, 0:1, vgx2], { z18.h, z19.h }, { z20.h, z21.h }"
+
+  -
+    input:
+      bytes: [ 0x90, 0x09, 0xe2, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w8, 0:1, vgx2], { z12.h, z13.h }, { z2.h, z3.h }"
+
+  -
+    input:
+      bytes: [ 0x90, 0x09, 0xe2, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w8, 0:1, vgx2], { z12.h, z13.h }, { z2.h, z3.h }"
+
+  -
+    input:
+      bytes: [ 0x11, 0x48, 0xfa, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w10, 2:3, vgx2], { z0.h, z1.h }, { z26.h, z27.h }"
+
+  -
+    input:
+      bytes: [ 0x11, 0x48, 0xfa, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w10, 2:3, vgx2], { z0.h, z1.h }, { z26.h, z27.h }"
+
+  -
+    input:
+      bytes: [ 0xd1, 0x0a, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w8, 2:3, vgx2], { z22.h, z23.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0xd1, 0x0a, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w8, 2:3, vgx2], { z22.h, z23.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x12, 0x69, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w11, 4:5, vgx2], { z8.h, z9.h }, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x12, 0x69, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w11, 4:5, vgx2], { z8.h, z9.h }, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x93, 0x29, 0xea, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w9, 6:7, vgx2], { z12.h, z13.h }, { z10.h, z11.h }"
+
+  -
+    input:
+      bytes: [ 0x93, 0x29, 0xea, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w9, 6:7, vgx2], { z12.h, z13.h }, { z10.h, z11.h }"
+
+  -
+    input:
+      bytes: [ 0x10, 0x08, 0x70, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w8, 0:1, vgx4], { z0.h - z3.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x10, 0x08, 0x70, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w8, 0:1, vgx4], { z0.h - z3.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x51, 0x49, 0x75, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w10, 2:3, vgx4], { z10.h - z13.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0x51, 0x49, 0x75, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w10, 2:3, vgx4], { z10.h - z13.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0xb3, 0x69, 0x78, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w11, 6:7, vgx4], { z13.h - z16.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0xb3, 0x69, 0x78, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w11, 6:7, vgx4], { z13.h - z16.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0xf3, 0x6b, 0x7f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w11, 6:7, vgx4], { z31.h, z0.h, z1.h, z2.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0xf3, 0x6b, 0x7f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w11, 6:7, vgx4], { z31.h, z0.h, z1.h, z2.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0x31, 0x0a, 0x70, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w8, 2:3, vgx4], { z17.h - z20.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x31, 0x0a, 0x70, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w8, 2:3, vgx4], { z17.h - z20.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x31, 0x08, 0x7e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w8, 2:3, vgx4], { z1.h - z4.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x31, 0x08, 0x7e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w8, 2:3, vgx4], { z1.h - z4.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x70, 0x4a, 0x74, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w10, 0:1, vgx4], { z19.h - z22.h }, z4.h"
+
+  -
+    input:
+      bytes: [ 0x70, 0x4a, 0x74, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w10, 0:1, vgx4], { z19.h - z22.h }, z4.h"
+
+  -
+    input:
+      bytes: [ 0x90, 0x09, 0x72, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w8, 0:1, vgx4], { z12.h - z15.h }, z2.h"
+
+  -
+    input:
+      bytes: [ 0x90, 0x09, 0x72, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w8, 0:1, vgx4], { z12.h - z15.h }, z2.h"
+
+  -
+    input:
+      bytes: [ 0x31, 0x48, 0x7a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w10, 2:3, vgx4], { z1.h - z4.h }, z10.h"
+
+  -
+    input:
+      bytes: [ 0x31, 0x48, 0x7a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w10, 2:3, vgx4], { z1.h - z4.h }, z10.h"
+
+  -
+    input:
+      bytes: [ 0xd1, 0x0a, 0x7e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w8, 2:3, vgx4], { z22.h - z25.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0xd1, 0x0a, 0x7e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w8, 2:3, vgx4], { z22.h - z25.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x32, 0x69, 0x71, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w11, 4:5, vgx4], { z9.h - z12.h }, z1.h"
+
+  -
+    input:
+      bytes: [ 0x32, 0x69, 0x71, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w11, 4:5, vgx4], { z9.h - z12.h }, z1.h"
+
+  -
+    input:
+      bytes: [ 0x93, 0x29, 0x7b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w9, 6:7, vgx4], { z12.h - z15.h }, z11.h"
+
+  -
+    input:
+      bytes: [ 0x93, 0x29, 0x7b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w9, 6:7, vgx4], { z12.h - z15.h }, z11.h"
+
+  -
+    input:
+      bytes: [ 0x10, 0x90, 0xd0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w8, 0:1, vgx4], { z0.h - z3.h }, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x10, 0x90, 0xd0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w8, 0:1, vgx4], { z0.h - z3.h }, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x15, 0xd5, 0xd5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w10, 2:3, vgx4], { z8.h - z11.h }, z5.h[3]"
+
+  -
+    input:
+      bytes: [ 0x15, 0xd5, 0xd5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w10, 2:3, vgx4], { z8.h - z11.h }, z5.h[3]"
+
+  -
+    input:
+      bytes: [ 0x97, 0xfd, 0xd8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w11, 6:7, vgx4], { z12.h - z15.h }, z8.h[7]"
+
+  -
+    input:
+      bytes: [ 0x97, 0xfd, 0xd8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w11, 6:7, vgx4], { z12.h - z15.h }, z8.h[7]"
+
+  -
+    input:
+      bytes: [ 0x97, 0xff, 0xdf, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w11, 6:7, vgx4], { z28.h - z31.h }, z15.h[7]"
+
+  -
+    input:
+      bytes: [ 0x97, 0xff, 0xdf, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w11, 6:7, vgx4], { z28.h - z31.h }, z15.h[7]"
+
+  -
+    input:
+      bytes: [ 0x15, 0x9e, 0xd0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w8, 2:3, vgx4], { z16.h - z19.h }, z0.h[7]"
+
+  -
+    input:
+      bytes: [ 0x15, 0x9e, 0xd0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w8, 2:3, vgx4], { z16.h - z19.h }, z0.h[7]"
+
+  -
+    input:
+      bytes: [ 0x11, 0x94, 0xde, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w8, 2:3, vgx4], { z0.h - z3.h }, z14.h[2]"
+
+  -
+    input:
+      bytes: [ 0x11, 0x94, 0xde, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w8, 2:3, vgx4], { z0.h - z3.h }, z14.h[2]"
+
+  -
+    input:
+      bytes: [ 0x10, 0xd6, 0xd4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w10, 0:1, vgx4], { z16.h - z19.h }, z4.h[2]"
+
+  -
+    input:
+      bytes: [ 0x10, 0xd6, 0xd4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w10, 0:1, vgx4], { z16.h - z19.h }, z4.h[2]"
+
+  -
+    input:
+      bytes: [ 0x90, 0x99, 0xd2, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w8, 0:1, vgx4], { z12.h - z15.h }, z2.h[4]"
+
+  -
+    input:
+      bytes: [ 0x90, 0x99, 0xd2, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w8, 0:1, vgx4], { z12.h - z15.h }, z2.h[4]"
+
+  -
+    input:
+      bytes: [ 0x11, 0xd8, 0xda, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w10, 2:3, vgx4], { z0.h - z3.h }, z10.h[4]"
+
+  -
+    input:
+      bytes: [ 0x11, 0xd8, 0xda, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w10, 2:3, vgx4], { z0.h - z3.h }, z10.h[4]"
+
+  -
+    input:
+      bytes: [ 0x95, 0x9a, 0xde, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w8, 2:3, vgx4], { z20.h - z23.h }, z14.h[5]"
+
+  -
+    input:
+      bytes: [ 0x95, 0x9a, 0xde, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w8, 2:3, vgx4], { z20.h - z23.h }, z14.h[5]"
+
+  -
+    input:
+      bytes: [ 0x12, 0xf5, 0xd1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w11, 4:5, vgx4], { z8.h - z11.h }, z1.h[2]"
+
+  -
+    input:
+      bytes: [ 0x12, 0xf5, 0xd1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w11, 4:5, vgx4], { z8.h - z11.h }, z1.h[2]"
+
+  -
+    input:
+      bytes: [ 0x97, 0xb9, 0xdb, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w9, 6:7, vgx4], { z12.h - z15.h }, z11.h[5]"
+
+  -
+    input:
+      bytes: [ 0x97, 0xb9, 0xdb, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w9, 6:7, vgx4], { z12.h - z15.h }, z11.h[5]"
+
+  -
+    input:
+      bytes: [ 0x10, 0x08, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w8, 0:1, vgx4], { z0.h - z3.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x10, 0x08, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w8, 0:1, vgx4], { z0.h - z3.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x11, 0x49, 0xf5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w10, 2:3, vgx4], { z8.h - z11.h }, { z20.h - z23.h }"
+
+  -
+    input:
+      bytes: [ 0x11, 0x49, 0xf5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w10, 2:3, vgx4], { z8.h - z11.h }, { z20.h - z23.h }"
+
+  -
+    input:
+      bytes: [ 0x93, 0x69, 0xe9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w11, 6:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }"
+
+  -
+    input:
+      bytes: [ 0x93, 0x69, 0xe9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w11, 6:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }"
+
+  -
+    input:
+      bytes: [ 0x93, 0x6b, 0xfd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w11, 6:7, vgx4], { z28.h - z31.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x93, 0x6b, 0xfd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w11, 6:7, vgx4], { z28.h - z31.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x11, 0x0a, 0xf1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w8, 2:3, vgx4], { z16.h - z19.h }, { z16.h - z19.h }"
+
+  -
+    input:
+      bytes: [ 0x11, 0x0a, 0xf1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w8, 2:3, vgx4], { z16.h - z19.h }, { z16.h - z19.h }"
+
+  -
+    input:
+      bytes: [ 0x11, 0x08, 0xfd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w8, 2:3, vgx4], { z0.h - z3.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x11, 0x08, 0xfd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w8, 2:3, vgx4], { z0.h - z3.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x10, 0x4a, 0xf5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w10, 0:1, vgx4], { z16.h - z19.h }, { z20.h - z23.h }"
+
+  -
+    input:
+      bytes: [ 0x10, 0x4a, 0xf5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w10, 0:1, vgx4], { z16.h - z19.h }, { z20.h - z23.h }"
+
+  -
+    input:
+      bytes: [ 0x90, 0x09, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w8, 0:1, vgx4], { z12.h - z15.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x90, 0x09, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w8, 0:1, vgx4], { z12.h - z15.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x11, 0x48, 0xf9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w10, 2:3, vgx4], { z0.h - z3.h }, { z24.h - z27.h }"
+
+  -
+    input:
+      bytes: [ 0x11, 0x48, 0xf9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w10, 2:3, vgx4], { z0.h - z3.h }, { z24.h - z27.h }"
+
+  -
+    input:
+      bytes: [ 0x91, 0x0a, 0xfd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w8, 2:3, vgx4], { z20.h - z23.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x91, 0x0a, 0xfd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w8, 2:3, vgx4], { z20.h - z23.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x12, 0x69, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w11, 4:5, vgx4], { z8.h - z11.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x12, 0x69, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w11, 4:5, vgx4], { z8.h - z11.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x93, 0x29, 0xe9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w9, 6:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }"
+
+  -
+    input:
+      bytes: [ 0x93, 0x29, 0xe9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal za.s[w9, 6:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }"
diff --git a/tests/MC/AArch64/SME2/umlall.s.yaml b/tests/MC/AArch64/SME2/umlall.s.yaml
new file mode 100644
index 000000000..da4081576
--- /dev/null
+++ b/tests/MC/AArch64/SME2/umlall.s.yaml
@@ -0,0 +1,3360 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x10, 0x04, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w8, 0:3], z0.b, z0.b"
+
+  -
+    input:
+      bytes: [ 0x51, 0x45, 0x25, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w10, 4:7], z10.b, z5.b"
+
+  -
+    input:
+      bytes: [ 0xb3, 0x65, 0x28, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w11, 12:15], z13.b, z8.b"
+
+  -
+    input:
+      bytes: [ 0xf3, 0x67, 0x2f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w11, 12:15], z31.b, z15.b"
+
+  -
+    input:
+      bytes: [ 0x31, 0x06, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w8, 4:7], z17.b, z0.b"
+
+  -
+    input:
+      bytes: [ 0x31, 0x04, 0x2e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w8, 4:7], z1.b, z14.b"
+
+  -
+    input:
+      bytes: [ 0x70, 0x46, 0x24, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w10, 0:3], z19.b, z4.b"
+
+  -
+    input:
+      bytes: [ 0x90, 0x05, 0x22, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w8, 0:3], z12.b, z2.b"
+
+  -
+    input:
+      bytes: [ 0x31, 0x44, 0x2a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w10, 4:7], z1.b, z10.b"
+
+  -
+    input:
+      bytes: [ 0xd1, 0x06, 0x2e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w8, 4:7], z22.b, z14.b"
+
+  -
+    input:
+      bytes: [ 0x32, 0x65, 0x21, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w11, 8:11], z9.b, z1.b"
+
+  -
+    input:
+      bytes: [ 0x93, 0x25, 0x2b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w9, 12:15], z12.b, z11.b"
+
+  -
+    input:
+      bytes: [ 0x10, 0x00, 0x00, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w8, 0:3], z0.b, z0.b[0]"
+
+  -
+    input:
+      bytes: [ 0x51, 0x55, 0x05, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w10, 4:7], z10.b, z5.b[5]"
+
+  -
+    input:
+      bytes: [ 0xb3, 0xed, 0x08, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w11, 12:15], z13.b, z8.b[11]"
+
+  -
+    input:
+      bytes: [ 0xf3, 0xff, 0x0f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w11, 12:15], z31.b, z15.b[15]"
+
+  -
+    input:
+      bytes: [ 0x31, 0x0e, 0x00, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w8, 4:7], z17.b, z0.b[3]"
+
+  -
+    input:
+      bytes: [ 0x31, 0x84, 0x0e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w8, 4:7], z1.b, z14.b[9]"
+
+  -
+    input:
+      bytes: [ 0x70, 0x56, 0x04, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w10, 0:3], z19.b, z4.b[5]"
+
+  -
+    input:
+      bytes: [ 0x90, 0x19, 0x02, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w8, 0:3], z12.b, z2.b[6]"
+
+  -
+    input:
+      bytes: [ 0x31, 0xc8, 0x0a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w10, 4:7], z1.b, z10.b[10]"
+
+  -
+    input:
+      bytes: [ 0xd1, 0x0a, 0x0e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w8, 4:7], z22.b, z14.b[2]"
+
+  -
+    input:
+      bytes: [ 0x32, 0xf5, 0x01, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w11, 8:11], z9.b, z1.b[13]"
+
+  -
+    input:
+      bytes: [ 0x93, 0xa9, 0x0b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w9, 12:15], z12.b, z11.b[10]"
+
+  -
+    input:
+      bytes: [ 0x10, 0x04, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w8, 0:3], z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x51, 0x45, 0x65, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w10, 4:7], z10.h, z5.h"
+
+  -
+    input:
+      bytes: [ 0xb3, 0x65, 0x68, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w11, 12:15], z13.h, z8.h"
+
+  -
+    input:
+      bytes: [ 0xf3, 0x67, 0x6f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w11, 12:15], z31.h, z15.h"
+
+  -
+    input:
+      bytes: [ 0x31, 0x06, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w8, 4:7], z17.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x31, 0x04, 0x6e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w8, 4:7], z1.h, z14.h"
+
+  -
+    input:
+      bytes: [ 0x70, 0x46, 0x64, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w10, 0:3], z19.h, z4.h"
+
+  -
+    input:
+      bytes: [ 0x90, 0x05, 0x62, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w8, 0:3], z12.h, z2.h"
+
+  -
+    input:
+      bytes: [ 0x31, 0x44, 0x6a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w10, 4:7], z1.h, z10.h"
+
+  -
+    input:
+      bytes: [ 0xd1, 0x06, 0x6e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w8, 4:7], z22.h, z14.h"
+
+  -
+    input:
+      bytes: [ 0x32, 0x65, 0x61, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w11, 8:11], z9.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0x93, 0x25, 0x6b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w9, 12:15], z12.h, z11.h"
+
+  -
+    input:
+      bytes: [ 0x10, 0x00, 0x80, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w8, 0:3], z0.h, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x51, 0x45, 0x85, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w10, 4:7], z10.h, z5.h[1]"
+
+  -
+    input:
+      bytes: [ 0xb3, 0xed, 0x88, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w11, 12:15], z13.h, z8.h[7]"
+
+  -
+    input:
+      bytes: [ 0xf3, 0xef, 0x8f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w11, 12:15], z31.h, z15.h[7]"
+
+  -
+    input:
+      bytes: [ 0x31, 0x0e, 0x80, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w8, 4:7], z17.h, z0.h[3]"
+
+  -
+    input:
+      bytes: [ 0x31, 0x84, 0x8e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w8, 4:7], z1.h, z14.h[5]"
+
+  -
+    input:
+      bytes: [ 0x70, 0x46, 0x84, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w10, 0:3], z19.h, z4.h[1]"
+
+  -
+    input:
+      bytes: [ 0x90, 0x09, 0x82, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w8, 0:3], z12.h, z2.h[2]"
+
+  -
+    input:
+      bytes: [ 0x31, 0xc8, 0x8a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w10, 4:7], z1.h, z10.h[6]"
+
+  -
+    input:
+      bytes: [ 0xd1, 0x0a, 0x8e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w8, 4:7], z22.h, z14.h[2]"
+
+  -
+    input:
+      bytes: [ 0x32, 0xe5, 0x81, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w11, 8:11], z9.h, z1.h[5]"
+
+  -
+    input:
+      bytes: [ 0x93, 0xa9, 0x8b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w9, 12:15], z12.h, z11.h[6]"
+
+  -
+    input:
+      bytes: [ 0x10, 0x00, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w8, 0:3,  vgx2], { z0.b, z1.b }, z0.b"
+
+  -
+    input:
+      bytes: [ 0x10, 0x00, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w8, 0:3,  vgx2], { z0.b, z1.b }, z0.b"
+
+  -
+    input:
+      bytes: [ 0x51, 0x41, 0x25, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w10, 4:7,  vgx2], { z10.b, z11.b }, z5.b"
+
+  -
+    input:
+      bytes: [ 0x51, 0x41, 0x25, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w10, 4:7,  vgx2], { z10.b, z11.b }, z5.b"
+
+  -
+    input:
+      bytes: [ 0xb1, 0x61, 0x28, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w11, 4:7,  vgx2], { z13.b, z14.b }, z8.b"
+
+  -
+    input:
+      bytes: [ 0xb1, 0x61, 0x28, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w11, 4:7,  vgx2], { z13.b, z14.b }, z8.b"
+
+  -
+    input:
+      bytes: [ 0xf1, 0x63, 0x2f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w11, 4:7,  vgx2], { z31.b, z0.b }, z15.b"
+
+  -
+    input:
+      bytes: [ 0xf1, 0x63, 0x2f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w11, 4:7,  vgx2], { z31.b, z0.b }, z15.b"
+
+  -
+    input:
+      bytes: [ 0x31, 0x02, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w8, 4:7,  vgx2], { z17.b, z18.b }, z0.b"
+
+  -
+    input:
+      bytes: [ 0x31, 0x02, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w8, 4:7,  vgx2], { z17.b, z18.b }, z0.b"
+
+  -
+    input:
+      bytes: [ 0x31, 0x00, 0x2e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w8, 4:7,  vgx2], { z1.b, z2.b }, z14.b"
+
+  -
+    input:
+      bytes: [ 0x31, 0x00, 0x2e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w8, 4:7,  vgx2], { z1.b, z2.b }, z14.b"
+
+  -
+    input:
+      bytes: [ 0x70, 0x42, 0x24, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w10, 0:3,  vgx2], { z19.b, z20.b }, z4.b"
+
+  -
+    input:
+      bytes: [ 0x70, 0x42, 0x24, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w10, 0:3,  vgx2], { z19.b, z20.b }, z4.b"
+
+  -
+    input:
+      bytes: [ 0x90, 0x01, 0x22, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w8, 0:3,  vgx2], { z12.b, z13.b }, z2.b"
+
+  -
+    input:
+      bytes: [ 0x90, 0x01, 0x22, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w8, 0:3,  vgx2], { z12.b, z13.b }, z2.b"
+
+  -
+    input:
+      bytes: [ 0x31, 0x40, 0x2a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w10, 4:7,  vgx2], { z1.b, z2.b }, z10.b"
+
+  -
+    input:
+      bytes: [ 0x31, 0x40, 0x2a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w10, 4:7,  vgx2], { z1.b, z2.b }, z10.b"
+
+  -
+    input:
+      bytes: [ 0xd1, 0x02, 0x2e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w8, 4:7,  vgx2], { z22.b, z23.b }, z14.b"
+
+  -
+    input:
+      bytes: [ 0xd1, 0x02, 0x2e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w8, 4:7,  vgx2], { z22.b, z23.b }, z14.b"
+
+  -
+    input:
+      bytes: [ 0x30, 0x61, 0x21, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w11, 0:3,  vgx2], { z9.b, z10.b }, z1.b"
+
+  -
+    input:
+      bytes: [ 0x30, 0x61, 0x21, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w11, 0:3,  vgx2], { z9.b, z10.b }, z1.b"
+
+  -
+    input:
+      bytes: [ 0x91, 0x21, 0x2b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w9, 4:7,  vgx2], { z12.b, z13.b }, z11.b"
+
+  -
+    input:
+      bytes: [ 0x91, 0x21, 0x2b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w9, 4:7,  vgx2], { z12.b, z13.b }, z11.b"
+
+  -
+    input:
+      bytes: [ 0x10, 0x00, 0x10, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w8, 0:3, vgx2], { z0.b, z1.b }, z0.b[0]"
+
+  -
+    input:
+      bytes: [ 0x10, 0x00, 0x10, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w8, 0:3, vgx2], { z0.b, z1.b }, z0.b[0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x45, 0x15, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w10, 4:7, vgx2], { z10.b, z11.b }, z5.b[6]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x45, 0x15, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w10, 4:7, vgx2], { z10.b, z11.b }, z5.b[6]"
+
+  -
+    input:
+      bytes: [ 0x97, 0x6d, 0x18, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w11, 4:7, vgx2], { z12.b, z13.b }, z8.b[15]"
+
+  -
+    input:
+      bytes: [ 0x97, 0x6d, 0x18, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w11, 4:7, vgx2], { z12.b, z13.b }, z8.b[15]"
+
+  -
+    input:
+      bytes: [ 0xd7, 0x6f, 0x1f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w11, 4:7, vgx2], { z30.b, z31.b }, z15.b[15]"
+
+  -
+    input:
+      bytes: [ 0xd7, 0x6f, 0x1f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w11, 4:7, vgx2], { z30.b, z31.b }, z15.b[15]"
+
+  -
+    input:
+      bytes: [ 0x15, 0x0e, 0x10, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w8, 4:7, vgx2], { z16.b, z17.b }, z0.b[14]"
+
+  -
+    input:
+      bytes: [ 0x15, 0x0e, 0x10, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w8, 4:7, vgx2], { z16.b, z17.b }, z0.b[14]"
+
+  -
+    input:
+      bytes: [ 0x11, 0x04, 0x1e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w8, 4:7, vgx2], { z0.b, z1.b }, z14.b[4]"
+
+  -
+    input:
+      bytes: [ 0x11, 0x04, 0x1e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w8, 4:7, vgx2], { z0.b, z1.b }, z14.b[4]"
+
+  -
+    input:
+      bytes: [ 0x50, 0x46, 0x14, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w10, 0:3, vgx2], { z18.b, z19.b }, z4.b[4]"
+
+  -
+    input:
+      bytes: [ 0x50, 0x46, 0x14, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w10, 0:3, vgx2], { z18.b, z19.b }, z4.b[4]"
+
+  -
+    input:
+      bytes: [ 0x90, 0x09, 0x12, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w8, 0:3, vgx2], { z12.b, z13.b }, z2.b[8]"
+
+  -
+    input:
+      bytes: [ 0x90, 0x09, 0x12, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w8, 0:3, vgx2], { z12.b, z13.b }, z2.b[8]"
+
+  -
+    input:
+      bytes: [ 0x11, 0x48, 0x1a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w10, 4:7, vgx2], { z0.b, z1.b }, z10.b[8]"
+
+  -
+    input:
+      bytes: [ 0x11, 0x48, 0x1a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w10, 4:7, vgx2], { z0.b, z1.b }, z10.b[8]"
+
+  -
+    input:
+      bytes: [ 0xd5, 0x0a, 0x1e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w8, 4:7, vgx2], { z22.b, z23.b }, z14.b[10]"
+
+  -
+    input:
+      bytes: [ 0xd5, 0x0a, 0x1e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w8, 4:7, vgx2], { z22.b, z23.b }, z14.b[10]"
+
+  -
+    input:
+      bytes: [ 0x12, 0x65, 0x11, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w11, 0:3, vgx2], { z8.b, z9.b }, z1.b[5]"
+
+  -
+    input:
+      bytes: [ 0x12, 0x65, 0x11, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w11, 0:3, vgx2], { z8.b, z9.b }, z1.b[5]"
+
+  -
+    input:
+      bytes: [ 0x97, 0x29, 0x1b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w9, 4:7, vgx2], { z12.b, z13.b }, z11.b[11]"
+
+  -
+    input:
+      bytes: [ 0x97, 0x29, 0x1b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w9, 4:7, vgx2], { z12.b, z13.b }, z11.b[11]"
+
+  -
+    input:
+      bytes: [ 0x10, 0x00, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w8, 0:3, vgx2], { z0.b, z1.b }, { z0.b, z1.b }"
+
+  -
+    input:
+      bytes: [ 0x10, 0x00, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w8, 0:3, vgx2], { z0.b, z1.b }, { z0.b, z1.b }"
+
+  -
+    input:
+      bytes: [ 0x51, 0x41, 0xb4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w10, 4:7, vgx2], { z10.b, z11.b }, { z20.b, z21.b }"
+
+  -
+    input:
+      bytes: [ 0x51, 0x41, 0xb4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w10, 4:7, vgx2], { z10.b, z11.b }, { z20.b, z21.b }"
+
+  -
+    input:
+      bytes: [ 0x91, 0x61, 0xa8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w11, 4:7, vgx2], { z12.b, z13.b }, { z8.b, z9.b }"
+
+  -
+    input:
+      bytes: [ 0x91, 0x61, 0xa8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w11, 4:7, vgx2], { z12.b, z13.b }, { z8.b, z9.b }"
+
+  -
+    input:
+      bytes: [ 0xd1, 0x63, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w11, 4:7, vgx2], { z30.b, z31.b }, { z30.b, z31.b }"
+
+  -
+    input:
+      bytes: [ 0xd1, 0x63, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w11, 4:7, vgx2], { z30.b, z31.b }, { z30.b, z31.b }"
+
+  -
+    input:
+      bytes: [ 0x11, 0x02, 0xb0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w8, 4:7, vgx2], { z16.b, z17.b }, { z16.b, z17.b }"
+
+  -
+    input:
+      bytes: [ 0x11, 0x02, 0xb0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w8, 4:7, vgx2], { z16.b, z17.b }, { z16.b, z17.b }"
+
+  -
+    input:
+      bytes: [ 0x11, 0x00, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w8, 4:7, vgx2], { z0.b, z1.b }, { z30.b, z31.b }"
+
+  -
+    input:
+      bytes: [ 0x11, 0x00, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w8, 4:7, vgx2], { z0.b, z1.b }, { z30.b, z31.b }"
+
+  -
+    input:
+      bytes: [ 0x50, 0x42, 0xb4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w10, 0:3, vgx2], { z18.b, z19.b }, { z20.b, z21.b }"
+
+  -
+    input:
+      bytes: [ 0x50, 0x42, 0xb4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w10, 0:3, vgx2], { z18.b, z19.b }, { z20.b, z21.b }"
+
+  -
+    input:
+      bytes: [ 0x90, 0x01, 0xa2, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w8, 0:3, vgx2], { z12.b, z13.b }, { z2.b, z3.b }"
+
+  -
+    input:
+      bytes: [ 0x90, 0x01, 0xa2, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w8, 0:3, vgx2], { z12.b, z13.b }, { z2.b, z3.b }"
+
+  -
+    input:
+      bytes: [ 0x11, 0x40, 0xba, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w10, 4:7, vgx2], { z0.b, z1.b }, { z26.b, z27.b }"
+
+  -
+    input:
+      bytes: [ 0x11, 0x40, 0xba, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w10, 4:7, vgx2], { z0.b, z1.b }, { z26.b, z27.b }"
+
+  -
+    input:
+      bytes: [ 0xd1, 0x02, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w8, 4:7, vgx2], { z22.b, z23.b }, { z30.b, z31.b }"
+
+  -
+    input:
+      bytes: [ 0xd1, 0x02, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w8, 4:7, vgx2], { z22.b, z23.b }, { z30.b, z31.b }"
+
+  -
+    input:
+      bytes: [ 0x10, 0x61, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w11, 0:3, vgx2], { z8.b, z9.b }, { z0.b, z1.b }"
+
+  -
+    input:
+      bytes: [ 0x10, 0x61, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w11, 0:3, vgx2], { z8.b, z9.b }, { z0.b, z1.b }"
+
+  -
+    input:
+      bytes: [ 0x91, 0x21, 0xaa, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w9, 4:7, vgx2], { z12.b, z13.b }, { z10.b, z11.b }"
+
+  -
+    input:
+      bytes: [ 0x91, 0x21, 0xaa, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w9, 4:7, vgx2], { z12.b, z13.b }, { z10.b, z11.b }"
+
+  -
+    input:
+      bytes: [ 0x10, 0x00, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w8, 0:3,  vgx2], { z0.h, z1.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x10, 0x00, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w8, 0:3,  vgx2], { z0.h, z1.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x51, 0x41, 0x65, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w10, 4:7,  vgx2], { z10.h, z11.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0x51, 0x41, 0x65, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w10, 4:7,  vgx2], { z10.h, z11.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0xb1, 0x61, 0x68, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w11, 4:7,  vgx2], { z13.h, z14.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0xb1, 0x61, 0x68, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w11, 4:7,  vgx2], { z13.h, z14.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0xf1, 0x63, 0x6f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w11, 4:7,  vgx2], { z31.h, z0.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0xf1, 0x63, 0x6f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w11, 4:7,  vgx2], { z31.h, z0.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0x31, 0x02, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w8, 4:7,  vgx2], { z17.h, z18.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x31, 0x02, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w8, 4:7,  vgx2], { z17.h, z18.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x31, 0x00, 0x6e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w8, 4:7,  vgx2], { z1.h, z2.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x31, 0x00, 0x6e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w8, 4:7,  vgx2], { z1.h, z2.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x70, 0x42, 0x64, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w10, 0:3,  vgx2], { z19.h, z20.h }, z4.h"
+
+  -
+    input:
+      bytes: [ 0x70, 0x42, 0x64, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w10, 0:3,  vgx2], { z19.h, z20.h }, z4.h"
+
+  -
+    input:
+      bytes: [ 0x90, 0x01, 0x62, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w8, 0:3,  vgx2], { z12.h, z13.h }, z2.h"
+
+  -
+    input:
+      bytes: [ 0x90, 0x01, 0x62, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w8, 0:3,  vgx2], { z12.h, z13.h }, z2.h"
+
+  -
+    input:
+      bytes: [ 0x31, 0x40, 0x6a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w10, 4:7,  vgx2], { z1.h, z2.h }, z10.h"
+
+  -
+    input:
+      bytes: [ 0x31, 0x40, 0x6a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w10, 4:7,  vgx2], { z1.h, z2.h }, z10.h"
+
+  -
+    input:
+      bytes: [ 0xd1, 0x02, 0x6e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w8, 4:7,  vgx2], { z22.h, z23.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0xd1, 0x02, 0x6e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w8, 4:7,  vgx2], { z22.h, z23.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x30, 0x61, 0x61, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w11, 0:3,  vgx2], { z9.h, z10.h }, z1.h"
+
+  -
+    input:
+      bytes: [ 0x30, 0x61, 0x61, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w11, 0:3,  vgx2], { z9.h, z10.h }, z1.h"
+
+  -
+    input:
+      bytes: [ 0x91, 0x21, 0x6b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w9, 4:7,  vgx2], { z12.h, z13.h }, z11.h"
+
+  -
+    input:
+      bytes: [ 0x91, 0x21, 0x6b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w9, 4:7,  vgx2], { z12.h, z13.h }, z11.h"
+
+  -
+    input:
+      bytes: [ 0x10, 0x00, 0x90, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w8, 0:3, vgx2], { z0.h, z1.h }, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x10, 0x00, 0x90, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w8, 0:3, vgx2], { z0.h, z1.h }, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x45, 0x95, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w10, 4:7, vgx2], { z10.h, z11.h }, z5.h[6]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x45, 0x95, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w10, 4:7, vgx2], { z10.h, z11.h }, z5.h[6]"
+
+  -
+    input:
+      bytes: [ 0x97, 0x65, 0x98, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w11, 4:7, vgx2], { z12.h, z13.h }, z8.h[7]"
+
+  -
+    input:
+      bytes: [ 0x97, 0x65, 0x98, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w11, 4:7, vgx2], { z12.h, z13.h }, z8.h[7]"
+
+  -
+    input:
+      bytes: [ 0xd7, 0x67, 0x9f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w11, 4:7, vgx2], { z30.h, z31.h }, z15.h[7]"
+
+  -
+    input:
+      bytes: [ 0xd7, 0x67, 0x9f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w11, 4:7, vgx2], { z30.h, z31.h }, z15.h[7]"
+
+  -
+    input:
+      bytes: [ 0x15, 0x06, 0x90, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w8, 4:7, vgx2], { z16.h, z17.h }, z0.h[6]"
+
+  -
+    input:
+      bytes: [ 0x15, 0x06, 0x90, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w8, 4:7, vgx2], { z16.h, z17.h }, z0.h[6]"
+
+  -
+    input:
+      bytes: [ 0x11, 0x04, 0x9e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w8, 4:7, vgx2], { z0.h, z1.h }, z14.h[4]"
+
+  -
+    input:
+      bytes: [ 0x11, 0x04, 0x9e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w8, 4:7, vgx2], { z0.h, z1.h }, z14.h[4]"
+
+  -
+    input:
+      bytes: [ 0x50, 0x46, 0x94, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w10, 0:3, vgx2], { z18.h, z19.h }, z4.h[4]"
+
+  -
+    input:
+      bytes: [ 0x50, 0x46, 0x94, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w10, 0:3, vgx2], { z18.h, z19.h }, z4.h[4]"
+
+  -
+    input:
+      bytes: [ 0x90, 0x01, 0x92, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w8, 0:3, vgx2], { z12.h, z13.h }, z2.h[0]"
+
+  -
+    input:
+      bytes: [ 0x90, 0x01, 0x92, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w8, 0:3, vgx2], { z12.h, z13.h }, z2.h[0]"
+
+  -
+    input:
+      bytes: [ 0x11, 0x40, 0x9a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w10, 4:7, vgx2], { z0.h, z1.h }, z10.h[0]"
+
+  -
+    input:
+      bytes: [ 0x11, 0x40, 0x9a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w10, 4:7, vgx2], { z0.h, z1.h }, z10.h[0]"
+
+  -
+    input:
+      bytes: [ 0xd5, 0x02, 0x9e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w8, 4:7, vgx2], { z22.h, z23.h }, z14.h[2]"
+
+  -
+    input:
+      bytes: [ 0xd5, 0x02, 0x9e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w8, 4:7, vgx2], { z22.h, z23.h }, z14.h[2]"
+
+  -
+    input:
+      bytes: [ 0x12, 0x65, 0x91, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w11, 0:3, vgx2], { z8.h, z9.h }, z1.h[5]"
+
+  -
+    input:
+      bytes: [ 0x12, 0x65, 0x91, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w11, 0:3, vgx2], { z8.h, z9.h }, z1.h[5]"
+
+  -
+    input:
+      bytes: [ 0x97, 0x21, 0x9b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w9, 4:7, vgx2], { z12.h, z13.h }, z11.h[3]"
+
+  -
+    input:
+      bytes: [ 0x97, 0x21, 0x9b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w9, 4:7, vgx2], { z12.h, z13.h }, z11.h[3]"
+
+  -
+    input:
+      bytes: [ 0x10, 0x00, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w8, 0:3, vgx2], { z0.h, z1.h }, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x10, 0x00, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w8, 0:3, vgx2], { z0.h, z1.h }, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x51, 0x41, 0xf4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w10, 4:7, vgx2], { z10.h, z11.h }, { z20.h, z21.h }"
+
+  -
+    input:
+      bytes: [ 0x51, 0x41, 0xf4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w10, 4:7, vgx2], { z10.h, z11.h }, { z20.h, z21.h }"
+
+  -
+    input:
+      bytes: [ 0x91, 0x61, 0xe8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w11, 4:7, vgx2], { z12.h, z13.h }, { z8.h, z9.h }"
+
+  -
+    input:
+      bytes: [ 0x91, 0x61, 0xe8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w11, 4:7, vgx2], { z12.h, z13.h }, { z8.h, z9.h }"
+
+  -
+    input:
+      bytes: [ 0xd1, 0x63, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w11, 4:7, vgx2], { z30.h, z31.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0xd1, 0x63, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w11, 4:7, vgx2], { z30.h, z31.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x11, 0x02, 0xf0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w8, 4:7, vgx2], { z16.h, z17.h }, { z16.h, z17.h }"
+
+  -
+    input:
+      bytes: [ 0x11, 0x02, 0xf0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w8, 4:7, vgx2], { z16.h, z17.h }, { z16.h, z17.h }"
+
+  -
+    input:
+      bytes: [ 0x11, 0x00, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w8, 4:7, vgx2], { z0.h, z1.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x11, 0x00, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w8, 4:7, vgx2], { z0.h, z1.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x50, 0x42, 0xf4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w10, 0:3, vgx2], { z18.h, z19.h }, { z20.h, z21.h }"
+
+  -
+    input:
+      bytes: [ 0x50, 0x42, 0xf4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w10, 0:3, vgx2], { z18.h, z19.h }, { z20.h, z21.h }"
+
+  -
+    input:
+      bytes: [ 0x90, 0x01, 0xe2, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w8, 0:3, vgx2], { z12.h, z13.h }, { z2.h, z3.h }"
+
+  -
+    input:
+      bytes: [ 0x90, 0x01, 0xe2, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w8, 0:3, vgx2], { z12.h, z13.h }, { z2.h, z3.h }"
+
+  -
+    input:
+      bytes: [ 0x11, 0x40, 0xfa, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w10, 4:7, vgx2], { z0.h, z1.h }, { z26.h, z27.h }"
+
+  -
+    input:
+      bytes: [ 0x11, 0x40, 0xfa, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w10, 4:7, vgx2], { z0.h, z1.h }, { z26.h, z27.h }"
+
+  -
+    input:
+      bytes: [ 0xd1, 0x02, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w8, 4:7, vgx2], { z22.h, z23.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0xd1, 0x02, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w8, 4:7, vgx2], { z22.h, z23.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x10, 0x61, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w11, 0:3, vgx2], { z8.h, z9.h }, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x10, 0x61, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w11, 0:3, vgx2], { z8.h, z9.h }, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x91, 0x21, 0xea, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w9, 4:7, vgx2], { z12.h, z13.h }, { z10.h, z11.h }"
+
+  -
+    input:
+      bytes: [ 0x91, 0x21, 0xea, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w9, 4:7, vgx2], { z12.h, z13.h }, { z10.h, z11.h }"
+
+  -
+    input:
+      bytes: [ 0x10, 0x00, 0x30, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w8, 0:3,  vgx4], { z0.b - z3.b }, z0.b"
+
+  -
+    input:
+      bytes: [ 0x10, 0x00, 0x30, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w8, 0:3,  vgx4], { z0.b - z3.b }, z0.b"
+
+  -
+    input:
+      bytes: [ 0x51, 0x41, 0x35, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w10, 4:7,  vgx4], { z10.b - z13.b }, z5.b"
+
+  -
+    input:
+      bytes: [ 0x51, 0x41, 0x35, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w10, 4:7,  vgx4], { z10.b - z13.b }, z5.b"
+
+  -
+    input:
+      bytes: [ 0xb1, 0x61, 0x38, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w11, 4:7,  vgx4], { z13.b - z16.b }, z8.b"
+
+  -
+    input:
+      bytes: [ 0xb1, 0x61, 0x38, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w11, 4:7,  vgx4], { z13.b - z16.b }, z8.b"
+
+  -
+    input:
+      bytes: [ 0xf1, 0x63, 0x3f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w11, 4:7,  vgx4], { z31.b, z0.b, z1.b, z2.b }, z15.b"
+
+  -
+    input:
+      bytes: [ 0xf1, 0x63, 0x3f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w11, 4:7,  vgx4], { z31.b, z0.b, z1.b, z2.b }, z15.b"
+
+  -
+    input:
+      bytes: [ 0x31, 0x02, 0x30, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w8, 4:7,  vgx4], { z17.b - z20.b }, z0.b"
+
+  -
+    input:
+      bytes: [ 0x31, 0x02, 0x30, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w8, 4:7,  vgx4], { z17.b - z20.b }, z0.b"
+
+  -
+    input:
+      bytes: [ 0x31, 0x00, 0x3e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w8, 4:7,  vgx4], { z1.b - z4.b }, z14.b"
+
+  -
+    input:
+      bytes: [ 0x31, 0x00, 0x3e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w8, 4:7,  vgx4], { z1.b - z4.b }, z14.b"
+
+  -
+    input:
+      bytes: [ 0x70, 0x42, 0x34, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w10, 0:3,  vgx4], { z19.b - z22.b }, z4.b"
+
+  -
+    input:
+      bytes: [ 0x70, 0x42, 0x34, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w10, 0:3,  vgx4], { z19.b - z22.b }, z4.b"
+
+  -
+    input:
+      bytes: [ 0x90, 0x01, 0x32, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w8, 0:3,  vgx4], { z12.b - z15.b }, z2.b"
+
+  -
+    input:
+      bytes: [ 0x90, 0x01, 0x32, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w8, 0:3,  vgx4], { z12.b - z15.b }, z2.b"
+
+  -
+    input:
+      bytes: [ 0x31, 0x40, 0x3a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w10, 4:7,  vgx4], { z1.b - z4.b }, z10.b"
+
+  -
+    input:
+      bytes: [ 0x31, 0x40, 0x3a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w10, 4:7,  vgx4], { z1.b - z4.b }, z10.b"
+
+  -
+    input:
+      bytes: [ 0xd1, 0x02, 0x3e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w8, 4:7,  vgx4], { z22.b - z25.b }, z14.b"
+
+  -
+    input:
+      bytes: [ 0xd1, 0x02, 0x3e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w8, 4:7,  vgx4], { z22.b - z25.b }, z14.b"
+
+  -
+    input:
+      bytes: [ 0x30, 0x61, 0x31, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w11, 0:3,  vgx4], { z9.b - z12.b }, z1.b"
+
+  -
+    input:
+      bytes: [ 0x30, 0x61, 0x31, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w11, 0:3,  vgx4], { z9.b - z12.b }, z1.b"
+
+  -
+    input:
+      bytes: [ 0x91, 0x21, 0x3b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w9, 4:7,  vgx4], { z12.b - z15.b }, z11.b"
+
+  -
+    input:
+      bytes: [ 0x91, 0x21, 0x3b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w9, 4:7,  vgx4], { z12.b - z15.b }, z11.b"
+
+  -
+    input:
+      bytes: [ 0x10, 0x80, 0x10, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w8, 0:3, vgx4], { z0.b - z3.b }, z0.b[0]"
+
+  -
+    input:
+      bytes: [ 0x10, 0x80, 0x10, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w8, 0:3, vgx4], { z0.b - z3.b }, z0.b[0]"
+
+  -
+    input:
+      bytes: [ 0x15, 0xc5, 0x15, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w10, 4:7, vgx4], { z8.b - z11.b }, z5.b[6]"
+
+  -
+    input:
+      bytes: [ 0x15, 0xc5, 0x15, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w10, 4:7, vgx4], { z8.b - z11.b }, z5.b[6]"
+
+  -
+    input:
+      bytes: [ 0x97, 0xed, 0x18, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w11, 4:7, vgx4], { z12.b - z15.b }, z8.b[15]"
+
+  -
+    input:
+      bytes: [ 0x97, 0xed, 0x18, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w11, 4:7, vgx4], { z12.b - z15.b }, z8.b[15]"
+
+  -
+    input:
+      bytes: [ 0x97, 0xef, 0x1f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w11, 4:7, vgx4], { z28.b - z31.b }, z15.b[15]"
+
+  -
+    input:
+      bytes: [ 0x97, 0xef, 0x1f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w11, 4:7, vgx4], { z28.b - z31.b }, z15.b[15]"
+
+  -
+    input:
+      bytes: [ 0x15, 0x8e, 0x10, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w8, 4:7, vgx4], { z16.b - z19.b }, z0.b[14]"
+
+  -
+    input:
+      bytes: [ 0x15, 0x8e, 0x10, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w8, 4:7, vgx4], { z16.b - z19.b }, z0.b[14]"
+
+  -
+    input:
+      bytes: [ 0x11, 0x84, 0x1e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w8, 4:7, vgx4], { z0.b - z3.b }, z14.b[4]"
+
+  -
+    input:
+      bytes: [ 0x11, 0x84, 0x1e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w8, 4:7, vgx4], { z0.b - z3.b }, z14.b[4]"
+
+  -
+    input:
+      bytes: [ 0x10, 0xc6, 0x14, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w10, 0:3, vgx4], { z16.b - z19.b }, z4.b[4]"
+
+  -
+    input:
+      bytes: [ 0x10, 0xc6, 0x14, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w10, 0:3, vgx4], { z16.b - z19.b }, z4.b[4]"
+
+  -
+    input:
+      bytes: [ 0x90, 0x89, 0x12, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w8, 0:3, vgx4], { z12.b - z15.b }, z2.b[8]"
+
+  -
+    input:
+      bytes: [ 0x90, 0x89, 0x12, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w8, 0:3, vgx4], { z12.b - z15.b }, z2.b[8]"
+
+  -
+    input:
+      bytes: [ 0x11, 0xc8, 0x1a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w10, 4:7, vgx4], { z0.b - z3.b }, z10.b[8]"
+
+  -
+    input:
+      bytes: [ 0x11, 0xc8, 0x1a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w10, 4:7, vgx4], { z0.b - z3.b }, z10.b[8]"
+
+  -
+    input:
+      bytes: [ 0x95, 0x8a, 0x1e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w8, 4:7, vgx4], { z20.b - z23.b }, z14.b[10]"
+
+  -
+    input:
+      bytes: [ 0x95, 0x8a, 0x1e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w8, 4:7, vgx4], { z20.b - z23.b }, z14.b[10]"
+
+  -
+    input:
+      bytes: [ 0x12, 0xe5, 0x11, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w11, 0:3, vgx4], { z8.b - z11.b }, z1.b[5]"
+
+  -
+    input:
+      bytes: [ 0x12, 0xe5, 0x11, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w11, 0:3, vgx4], { z8.b - z11.b }, z1.b[5]"
+
+  -
+    input:
+      bytes: [ 0x97, 0xa9, 0x1b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w9, 4:7, vgx4], { z12.b - z15.b }, z11.b[11]"
+
+  -
+    input:
+      bytes: [ 0x97, 0xa9, 0x1b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w9, 4:7, vgx4], { z12.b - z15.b }, z11.b[11]"
+
+  -
+    input:
+      bytes: [ 0x10, 0x00, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w8, 0:3, vgx4], { z0.b - z3.b }, { z0.b - z3.b }"
+
+  -
+    input:
+      bytes: [ 0x10, 0x00, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w8, 0:3, vgx4], { z0.b - z3.b }, { z0.b - z3.b }"
+
+  -
+    input:
+      bytes: [ 0x11, 0x41, 0xb5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w10, 4:7, vgx4], { z8.b - z11.b }, { z20.b - z23.b }"
+
+  -
+    input:
+      bytes: [ 0x11, 0x41, 0xb5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w10, 4:7, vgx4], { z8.b - z11.b }, { z20.b - z23.b }"
+
+  -
+    input:
+      bytes: [ 0x91, 0x61, 0xa9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w11, 4:7, vgx4], { z12.b - z15.b }, { z8.b - z11.b }"
+
+  -
+    input:
+      bytes: [ 0x91, 0x61, 0xa9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w11, 4:7, vgx4], { z12.b - z15.b }, { z8.b - z11.b }"
+
+  -
+    input:
+      bytes: [ 0x91, 0x63, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w11, 4:7, vgx4], { z28.b - z31.b }, { z28.b - z31.b }"
+
+  -
+    input:
+      bytes: [ 0x91, 0x63, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w11, 4:7, vgx4], { z28.b - z31.b }, { z28.b - z31.b }"
+
+  -
+    input:
+      bytes: [ 0x11, 0x02, 0xb1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w8, 4:7, vgx4], { z16.b - z19.b }, { z16.b - z19.b }"
+
+  -
+    input:
+      bytes: [ 0x11, 0x02, 0xb1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w8, 4:7, vgx4], { z16.b - z19.b }, { z16.b - z19.b }"
+
+  -
+    input:
+      bytes: [ 0x11, 0x00, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w8, 4:7, vgx4], { z0.b - z3.b }, { z28.b - z31.b }"
+
+  -
+    input:
+      bytes: [ 0x11, 0x00, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w8, 4:7, vgx4], { z0.b - z3.b }, { z28.b - z31.b }"
+
+  -
+    input:
+      bytes: [ 0x10, 0x42, 0xb5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w10, 0:3, vgx4], { z16.b - z19.b }, { z20.b - z23.b }"
+
+  -
+    input:
+      bytes: [ 0x10, 0x42, 0xb5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w10, 0:3, vgx4], { z16.b - z19.b }, { z20.b - z23.b }"
+
+  -
+    input:
+      bytes: [ 0x90, 0x01, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w8, 0:3, vgx4], { z12.b - z15.b }, { z0.b - z3.b }"
+
+  -
+    input:
+      bytes: [ 0x90, 0x01, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w8, 0:3, vgx4], { z12.b - z15.b }, { z0.b - z3.b }"
+
+  -
+    input:
+      bytes: [ 0x11, 0x40, 0xb9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w10, 4:7, vgx4], { z0.b - z3.b }, { z24.b - z27.b }"
+
+  -
+    input:
+      bytes: [ 0x11, 0x40, 0xb9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w10, 4:7, vgx4], { z0.b - z3.b }, { z24.b - z27.b }"
+
+  -
+    input:
+      bytes: [ 0x91, 0x02, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w8, 4:7, vgx4], { z20.b - z23.b }, { z28.b - z31.b }"
+
+  -
+    input:
+      bytes: [ 0x91, 0x02, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w8, 4:7, vgx4], { z20.b - z23.b }, { z28.b - z31.b }"
+
+  -
+    input:
+      bytes: [ 0x10, 0x61, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w11, 0:3, vgx4], { z8.b - z11.b }, { z0.b - z3.b }"
+
+  -
+    input:
+      bytes: [ 0x10, 0x61, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w11, 0:3, vgx4], { z8.b - z11.b }, { z0.b - z3.b }"
+
+  -
+    input:
+      bytes: [ 0x91, 0x21, 0xa9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w9, 4:7, vgx4], { z12.b - z15.b }, { z8.b - z11.b }"
+
+  -
+    input:
+      bytes: [ 0x91, 0x21, 0xa9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.s[w9, 4:7, vgx4], { z12.b - z15.b }, { z8.b - z11.b }"
+
+  -
+    input:
+      bytes: [ 0x10, 0x00, 0x70, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w8, 0:3,  vgx4], { z0.h - z3.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x10, 0x00, 0x70, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w8, 0:3,  vgx4], { z0.h - z3.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x51, 0x41, 0x75, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w10, 4:7,  vgx4], { z10.h - z13.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0x51, 0x41, 0x75, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w10, 4:7,  vgx4], { z10.h - z13.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0xb1, 0x61, 0x78, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w11, 4:7,  vgx4], { z13.h - z16.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0xb1, 0x61, 0x78, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w11, 4:7,  vgx4], { z13.h - z16.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0xf1, 0x63, 0x7f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w11, 4:7,  vgx4], { z31.h, z0.h, z1.h, z2.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0xf1, 0x63, 0x7f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w11, 4:7,  vgx4], { z31.h, z0.h, z1.h, z2.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0x31, 0x02, 0x70, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w8, 4:7,  vgx4], { z17.h - z20.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x31, 0x02, 0x70, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w8, 4:7,  vgx4], { z17.h - z20.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x31, 0x00, 0x7e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w8, 4:7,  vgx4], { z1.h - z4.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x31, 0x00, 0x7e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w8, 4:7,  vgx4], { z1.h - z4.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x70, 0x42, 0x74, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w10, 0:3,  vgx4], { z19.h - z22.h }, z4.h"
+
+  -
+    input:
+      bytes: [ 0x70, 0x42, 0x74, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w10, 0:3,  vgx4], { z19.h - z22.h }, z4.h"
+
+  -
+    input:
+      bytes: [ 0x90, 0x01, 0x72, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w8, 0:3,  vgx4], { z12.h - z15.h }, z2.h"
+
+  -
+    input:
+      bytes: [ 0x90, 0x01, 0x72, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w8, 0:3,  vgx4], { z12.h - z15.h }, z2.h"
+
+  -
+    input:
+      bytes: [ 0x31, 0x40, 0x7a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w10, 4:7,  vgx4], { z1.h - z4.h }, z10.h"
+
+  -
+    input:
+      bytes: [ 0x31, 0x40, 0x7a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w10, 4:7,  vgx4], { z1.h - z4.h }, z10.h"
+
+  -
+    input:
+      bytes: [ 0xd1, 0x02, 0x7e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w8, 4:7,  vgx4], { z22.h - z25.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0xd1, 0x02, 0x7e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w8, 4:7,  vgx4], { z22.h - z25.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x30, 0x61, 0x71, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w11, 0:3,  vgx4], { z9.h - z12.h }, z1.h"
+
+  -
+    input:
+      bytes: [ 0x30, 0x61, 0x71, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w11, 0:3,  vgx4], { z9.h - z12.h }, z1.h"
+
+  -
+    input:
+      bytes: [ 0x91, 0x21, 0x7b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w9, 4:7,  vgx4], { z12.h - z15.h }, z11.h"
+
+  -
+    input:
+      bytes: [ 0x91, 0x21, 0x7b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w9, 4:7,  vgx4], { z12.h - z15.h }, z11.h"
+
+  -
+    input:
+      bytes: [ 0x10, 0x80, 0x90, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w8, 0:3, vgx4], { z0.h - z3.h }, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x10, 0x80, 0x90, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w8, 0:3, vgx4], { z0.h - z3.h }, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x15, 0xc5, 0x95, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w10, 4:7, vgx4], { z8.h - z11.h }, z5.h[6]"
+
+  -
+    input:
+      bytes: [ 0x15, 0xc5, 0x95, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w10, 4:7, vgx4], { z8.h - z11.h }, z5.h[6]"
+
+  -
+    input:
+      bytes: [ 0x97, 0xe5, 0x98, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w11, 4:7, vgx4], { z12.h - z15.h }, z8.h[7]"
+
+  -
+    input:
+      bytes: [ 0x97, 0xe5, 0x98, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w11, 4:7, vgx4], { z12.h - z15.h }, z8.h[7]"
+
+  -
+    input:
+      bytes: [ 0x97, 0xe7, 0x9f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w11, 4:7, vgx4], { z28.h - z31.h }, z15.h[7]"
+
+  -
+    input:
+      bytes: [ 0x97, 0xe7, 0x9f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w11, 4:7, vgx4], { z28.h - z31.h }, z15.h[7]"
+
+  -
+    input:
+      bytes: [ 0x15, 0x86, 0x90, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w8, 4:7, vgx4], { z16.h - z19.h }, z0.h[6]"
+
+  -
+    input:
+      bytes: [ 0x15, 0x86, 0x90, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w8, 4:7, vgx4], { z16.h - z19.h }, z0.h[6]"
+
+  -
+    input:
+      bytes: [ 0x11, 0x84, 0x9e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w8, 4:7, vgx4], { z0.h - z3.h }, z14.h[4]"
+
+  -
+    input:
+      bytes: [ 0x11, 0x84, 0x9e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w8, 4:7, vgx4], { z0.h - z3.h }, z14.h[4]"
+
+  -
+    input:
+      bytes: [ 0x10, 0xc6, 0x94, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w10, 0:3, vgx4], { z16.h - z19.h }, z4.h[4]"
+
+  -
+    input:
+      bytes: [ 0x10, 0xc6, 0x94, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w10, 0:3, vgx4], { z16.h - z19.h }, z4.h[4]"
+
+  -
+    input:
+      bytes: [ 0x90, 0x81, 0x92, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w8, 0:3, vgx4], { z12.h - z15.h }, z2.h[0]"
+
+  -
+    input:
+      bytes: [ 0x90, 0x81, 0x92, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w8, 0:3, vgx4], { z12.h - z15.h }, z2.h[0]"
+
+  -
+    input:
+      bytes: [ 0x11, 0xc0, 0x9a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w10, 4:7, vgx4], { z0.h - z3.h }, z10.h[0]"
+
+  -
+    input:
+      bytes: [ 0x11, 0xc0, 0x9a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w10, 4:7, vgx4], { z0.h - z3.h }, z10.h[0]"
+
+  -
+    input:
+      bytes: [ 0x95, 0x82, 0x9e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w8, 4:7, vgx4], { z20.h - z23.h }, z14.h[2]"
+
+  -
+    input:
+      bytes: [ 0x95, 0x82, 0x9e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w8, 4:7, vgx4], { z20.h - z23.h }, z14.h[2]"
+
+  -
+    input:
+      bytes: [ 0x12, 0xe5, 0x91, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w11, 0:3, vgx4], { z8.h - z11.h }, z1.h[5]"
+
+  -
+    input:
+      bytes: [ 0x12, 0xe5, 0x91, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w11, 0:3, vgx4], { z8.h - z11.h }, z1.h[5]"
+
+  -
+    input:
+      bytes: [ 0x97, 0xa1, 0x9b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w9, 4:7, vgx4], { z12.h - z15.h }, z11.h[3]"
+
+  -
+    input:
+      bytes: [ 0x97, 0xa1, 0x9b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w9, 4:7, vgx4], { z12.h - z15.h }, z11.h[3]"
+
+  -
+    input:
+      bytes: [ 0x10, 0x00, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w8, 0:3, vgx4], { z0.h - z3.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x10, 0x00, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w8, 0:3, vgx4], { z0.h - z3.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x11, 0x41, 0xf5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w10, 4:7, vgx4], { z8.h - z11.h }, { z20.h - z23.h }"
+
+  -
+    input:
+      bytes: [ 0x11, 0x41, 0xf5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w10, 4:7, vgx4], { z8.h - z11.h }, { z20.h - z23.h }"
+
+  -
+    input:
+      bytes: [ 0x91, 0x61, 0xe9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w11, 4:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }"
+
+  -
+    input:
+      bytes: [ 0x91, 0x61, 0xe9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w11, 4:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }"
+
+  -
+    input:
+      bytes: [ 0x91, 0x63, 0xfd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w11, 4:7, vgx4], { z28.h - z31.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x91, 0x63, 0xfd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w11, 4:7, vgx4], { z28.h - z31.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x11, 0x02, 0xf1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w8, 4:7, vgx4], { z16.h - z19.h }, { z16.h - z19.h }"
+
+  -
+    input:
+      bytes: [ 0x11, 0x02, 0xf1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w8, 4:7, vgx4], { z16.h - z19.h }, { z16.h - z19.h }"
+
+  -
+    input:
+      bytes: [ 0x11, 0x00, 0xfd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w8, 4:7, vgx4], { z0.h - z3.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x11, 0x00, 0xfd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w8, 4:7, vgx4], { z0.h - z3.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x10, 0x42, 0xf5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w10, 0:3, vgx4], { z16.h - z19.h }, { z20.h - z23.h }"
+
+  -
+    input:
+      bytes: [ 0x10, 0x42, 0xf5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w10, 0:3, vgx4], { z16.h - z19.h }, { z20.h - z23.h }"
+
+  -
+    input:
+      bytes: [ 0x90, 0x01, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w8, 0:3, vgx4], { z12.h - z15.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x90, 0x01, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w8, 0:3, vgx4], { z12.h - z15.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x11, 0x40, 0xf9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w10, 4:7, vgx4], { z0.h - z3.h }, { z24.h - z27.h }"
+
+  -
+    input:
+      bytes: [ 0x11, 0x40, 0xf9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w10, 4:7, vgx4], { z0.h - z3.h }, { z24.h - z27.h }"
+
+  -
+    input:
+      bytes: [ 0x91, 0x02, 0xfd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w8, 4:7, vgx4], { z20.h - z23.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x91, 0x02, 0xfd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w8, 4:7, vgx4], { z20.h - z23.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x10, 0x61, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w11, 0:3, vgx4], { z8.h - z11.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x10, 0x61, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w11, 0:3, vgx4], { z8.h - z11.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x91, 0x21, 0xe9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w9, 4:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }"
+
+  -
+    input:
+      bytes: [ 0x91, 0x21, 0xe9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlall za.d[w9, 4:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }"
diff --git a/tests/MC/AArch64/SME2/umlsl.s.yaml b/tests/MC/AArch64/SME2/umlsl.s.yaml
new file mode 100644
index 000000000..fd9b40421
--- /dev/null
+++ b/tests/MC/AArch64/SME2/umlsl.s.yaml
@@ -0,0 +1,1680 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x18, 0x0c, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w8, 0:1], z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x5d, 0x4d, 0x65, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w10, 10:11], z10.h, z5.h"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x6d, 0x68, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w11, 14:15], z13.h, z8.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x6f, 0x6f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w11, 14:15], z31.h, z15.h"
+
+  -
+    input:
+      bytes: [ 0x3d, 0x0e, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w8, 10:11], z17.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x39, 0x0c, 0x6e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w8, 2:3], z1.h, z14.h"
+
+  -
+    input:
+      bytes: [ 0x78, 0x4e, 0x64, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w10, 0:1], z19.h, z4.h"
+
+  -
+    input:
+      bytes: [ 0x98, 0x0d, 0x62, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w8, 0:1], z12.h, z2.h"
+
+  -
+    input:
+      bytes: [ 0x39, 0x4c, 0x6a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w10, 2:3], z1.h, z10.h"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x0e, 0x6e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w8, 10:11], z22.h, z14.h"
+
+  -
+    input:
+      bytes: [ 0x3a, 0x6d, 0x61, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w11, 4:5], z9.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x2d, 0x6b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w9, 14:15], z12.h, z11.h"
+
+  -
+    input:
+      bytes: [ 0x18, 0x10, 0xc0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w8, 0:1], z0.h, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x5d, 0x55, 0xc5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w10, 10:11], z10.h, z5.h[1]"
+
+  -
+    input:
+      bytes: [ 0xbf, 0xfd, 0xc8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w11, 14:15], z13.h, z8.h[7]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xcf, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w11, 14:15], z31.h, z15.h[7]"
+
+  -
+    input:
+      bytes: [ 0x3d, 0x1e, 0xc0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w8, 10:11], z17.h, z0.h[3]"
+
+  -
+    input:
+      bytes: [ 0x39, 0x94, 0xce, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w8, 2:3], z1.h, z14.h[5]"
+
+  -
+    input:
+      bytes: [ 0x78, 0x56, 0xc4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w10, 0:1], z19.h, z4.h[1]"
+
+  -
+    input:
+      bytes: [ 0x98, 0x19, 0xc2, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w8, 0:1], z12.h, z2.h[2]"
+
+  -
+    input:
+      bytes: [ 0x39, 0xd8, 0xca, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w10, 2:3], z1.h, z10.h[6]"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x1a, 0xce, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w8, 10:11], z22.h, z14.h[2]"
+
+  -
+    input:
+      bytes: [ 0x3a, 0xf5, 0xc1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w11, 4:5], z9.h, z1.h[5]"
+
+  -
+    input:
+      bytes: [ 0x9f, 0xb9, 0xcb, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w9, 14:15], z12.h, z11.h[6]"
+
+  -
+    input:
+      bytes: [ 0x18, 0x08, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w8, 0:1, vgx2], { z0.h, z1.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x18, 0x08, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w8, 0:1, vgx2], { z0.h, z1.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x59, 0x49, 0x65, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w10, 2:3, vgx2], { z10.h, z11.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0x59, 0x49, 0x65, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w10, 2:3, vgx2], { z10.h, z11.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0xbb, 0x69, 0x68, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w11, 6:7, vgx2], { z13.h, z14.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0xbb, 0x69, 0x68, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w11, 6:7, vgx2], { z13.h, z14.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0xfb, 0x6b, 0x6f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w11, 6:7, vgx2], { z31.h, z0.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0xfb, 0x6b, 0x6f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w11, 6:7, vgx2], { z31.h, z0.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0x39, 0x0a, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w8, 2:3, vgx2], { z17.h, z18.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x39, 0x0a, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w8, 2:3, vgx2], { z17.h, z18.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x39, 0x08, 0x6e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w8, 2:3, vgx2], { z1.h, z2.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x39, 0x08, 0x6e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w8, 2:3, vgx2], { z1.h, z2.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x78, 0x4a, 0x64, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w10, 0:1, vgx2], { z19.h, z20.h }, z4.h"
+
+  -
+    input:
+      bytes: [ 0x78, 0x4a, 0x64, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w10, 0:1, vgx2], { z19.h, z20.h }, z4.h"
+
+  -
+    input:
+      bytes: [ 0x98, 0x09, 0x62, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w8, 0:1, vgx2], { z12.h, z13.h }, z2.h"
+
+  -
+    input:
+      bytes: [ 0x98, 0x09, 0x62, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w8, 0:1, vgx2], { z12.h, z13.h }, z2.h"
+
+  -
+    input:
+      bytes: [ 0x39, 0x48, 0x6a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w10, 2:3, vgx2], { z1.h, z2.h }, z10.h"
+
+  -
+    input:
+      bytes: [ 0x39, 0x48, 0x6a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w10, 2:3, vgx2], { z1.h, z2.h }, z10.h"
+
+  -
+    input:
+      bytes: [ 0xd9, 0x0a, 0x6e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w8, 2:3, vgx2], { z22.h, z23.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0xd9, 0x0a, 0x6e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w8, 2:3, vgx2], { z22.h, z23.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x3a, 0x69, 0x61, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w11, 4:5, vgx2], { z9.h, z10.h }, z1.h"
+
+  -
+    input:
+      bytes: [ 0x3a, 0x69, 0x61, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w11, 4:5, vgx2], { z9.h, z10.h }, z1.h"
+
+  -
+    input:
+      bytes: [ 0x9b, 0x29, 0x6b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w9, 6:7, vgx2], { z12.h, z13.h }, z11.h"
+
+  -
+    input:
+      bytes: [ 0x9b, 0x29, 0x6b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w9, 6:7, vgx2], { z12.h, z13.h }, z11.h"
+
+  -
+    input:
+      bytes: [ 0x18, 0x10, 0xd0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w8, 0:1, vgx2], { z0.h, z1.h }, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x18, 0x10, 0xd0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w8, 0:1, vgx2], { z0.h, z1.h }, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x5d, 0x55, 0xd5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w10, 2:3, vgx2], { z10.h, z11.h }, z5.h[3]"
+
+  -
+    input:
+      bytes: [ 0x5d, 0x55, 0xd5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w10, 2:3, vgx2], { z10.h, z11.h }, z5.h[3]"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x7d, 0xd8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w11, 6:7, vgx2], { z12.h, z13.h }, z8.h[7]"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x7d, 0xd8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w11, 6:7, vgx2], { z12.h, z13.h }, z8.h[7]"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x7f, 0xdf, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w11, 6:7, vgx2], { z30.h, z31.h }, z15.h[7]"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x7f, 0xdf, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w11, 6:7, vgx2], { z30.h, z31.h }, z15.h[7]"
+
+  -
+    input:
+      bytes: [ 0x1d, 0x1e, 0xd0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w8, 2:3, vgx2], { z16.h, z17.h }, z0.h[7]"
+
+  -
+    input:
+      bytes: [ 0x1d, 0x1e, 0xd0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w8, 2:3, vgx2], { z16.h, z17.h }, z0.h[7]"
+
+  -
+    input:
+      bytes: [ 0x19, 0x14, 0xde, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w8, 2:3, vgx2], { z0.h, z1.h }, z14.h[2]"
+
+  -
+    input:
+      bytes: [ 0x19, 0x14, 0xde, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w8, 2:3, vgx2], { z0.h, z1.h }, z14.h[2]"
+
+  -
+    input:
+      bytes: [ 0x58, 0x56, 0xd4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w10, 0:1, vgx2], { z18.h, z19.h }, z4.h[2]"
+
+  -
+    input:
+      bytes: [ 0x58, 0x56, 0xd4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w10, 0:1, vgx2], { z18.h, z19.h }, z4.h[2]"
+
+  -
+    input:
+      bytes: [ 0x98, 0x19, 0xd2, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w8, 0:1, vgx2], { z12.h, z13.h }, z2.h[4]"
+
+  -
+    input:
+      bytes: [ 0x98, 0x19, 0xd2, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w8, 0:1, vgx2], { z12.h, z13.h }, z2.h[4]"
+
+  -
+    input:
+      bytes: [ 0x19, 0x58, 0xda, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w10, 2:3, vgx2], { z0.h, z1.h }, z10.h[4]"
+
+  -
+    input:
+      bytes: [ 0x19, 0x58, 0xda, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w10, 2:3, vgx2], { z0.h, z1.h }, z10.h[4]"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x1a, 0xde, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w8, 2:3, vgx2], { z22.h, z23.h }, z14.h[5]"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x1a, 0xde, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w8, 2:3, vgx2], { z22.h, z23.h }, z14.h[5]"
+
+  -
+    input:
+      bytes: [ 0x1a, 0x75, 0xd1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w11, 4:5, vgx2], { z8.h, z9.h }, z1.h[2]"
+
+  -
+    input:
+      bytes: [ 0x1a, 0x75, 0xd1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w11, 4:5, vgx2], { z8.h, z9.h }, z1.h[2]"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x39, 0xdb, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w9, 6:7, vgx2], { z12.h, z13.h }, z11.h[5]"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x39, 0xdb, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w9, 6:7, vgx2], { z12.h, z13.h }, z11.h[5]"
+
+  -
+    input:
+      bytes: [ 0x18, 0x08, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w8, 0:1, vgx2], { z0.h, z1.h }, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x18, 0x08, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w8, 0:1, vgx2], { z0.h, z1.h }, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x59, 0x49, 0xf4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w10, 2:3, vgx2], { z10.h, z11.h }, { z20.h, z21.h }"
+
+  -
+    input:
+      bytes: [ 0x59, 0x49, 0xf4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w10, 2:3, vgx2], { z10.h, z11.h }, { z20.h, z21.h }"
+
+  -
+    input:
+      bytes: [ 0x9b, 0x69, 0xe8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w11, 6:7, vgx2], { z12.h, z13.h }, { z8.h, z9.h }"
+
+  -
+    input:
+      bytes: [ 0x9b, 0x69, 0xe8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w11, 6:7, vgx2], { z12.h, z13.h }, { z8.h, z9.h }"
+
+  -
+    input:
+      bytes: [ 0xdb, 0x6b, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w11, 6:7, vgx2], { z30.h, z31.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0xdb, 0x6b, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w11, 6:7, vgx2], { z30.h, z31.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x19, 0x0a, 0xf0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w8, 2:3, vgx2], { z16.h, z17.h }, { z16.h, z17.h }"
+
+  -
+    input:
+      bytes: [ 0x19, 0x0a, 0xf0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w8, 2:3, vgx2], { z16.h, z17.h }, { z16.h, z17.h }"
+
+  -
+    input:
+      bytes: [ 0x19, 0x08, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w8, 2:3, vgx2], { z0.h, z1.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x19, 0x08, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w8, 2:3, vgx2], { z0.h, z1.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x58, 0x4a, 0xf4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w10, 0:1, vgx2], { z18.h, z19.h }, { z20.h, z21.h }"
+
+  -
+    input:
+      bytes: [ 0x58, 0x4a, 0xf4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w10, 0:1, vgx2], { z18.h, z19.h }, { z20.h, z21.h }"
+
+  -
+    input:
+      bytes: [ 0x98, 0x09, 0xe2, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w8, 0:1, vgx2], { z12.h, z13.h }, { z2.h, z3.h }"
+
+  -
+    input:
+      bytes: [ 0x98, 0x09, 0xe2, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w8, 0:1, vgx2], { z12.h, z13.h }, { z2.h, z3.h }"
+
+  -
+    input:
+      bytes: [ 0x19, 0x48, 0xfa, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w10, 2:3, vgx2], { z0.h, z1.h }, { z26.h, z27.h }"
+
+  -
+    input:
+      bytes: [ 0x19, 0x48, 0xfa, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w10, 2:3, vgx2], { z0.h, z1.h }, { z26.h, z27.h }"
+
+  -
+    input:
+      bytes: [ 0xd9, 0x0a, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w8, 2:3, vgx2], { z22.h, z23.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0xd9, 0x0a, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w8, 2:3, vgx2], { z22.h, z23.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x1a, 0x69, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w11, 4:5, vgx2], { z8.h, z9.h }, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x1a, 0x69, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w11, 4:5, vgx2], { z8.h, z9.h }, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x9b, 0x29, 0xea, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w9, 6:7, vgx2], { z12.h, z13.h }, { z10.h, z11.h }"
+
+  -
+    input:
+      bytes: [ 0x9b, 0x29, 0xea, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w9, 6:7, vgx2], { z12.h, z13.h }, { z10.h, z11.h }"
+
+  -
+    input:
+      bytes: [ 0x18, 0x08, 0x70, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w8, 0:1, vgx4], { z0.h - z3.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x18, 0x08, 0x70, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w8, 0:1, vgx4], { z0.h - z3.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x59, 0x49, 0x75, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w10, 2:3, vgx4], { z10.h - z13.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0x59, 0x49, 0x75, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w10, 2:3, vgx4], { z10.h - z13.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0xbb, 0x69, 0x78, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w11, 6:7, vgx4], { z13.h - z16.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0xbb, 0x69, 0x78, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w11, 6:7, vgx4], { z13.h - z16.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0xfb, 0x6b, 0x7f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w11, 6:7, vgx4], { z31.h, z0.h, z1.h, z2.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0xfb, 0x6b, 0x7f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w11, 6:7, vgx4], { z31.h, z0.h, z1.h, z2.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0x39, 0x0a, 0x70, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w8, 2:3, vgx4], { z17.h - z20.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x39, 0x0a, 0x70, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w8, 2:3, vgx4], { z17.h - z20.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x39, 0x08, 0x7e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w8, 2:3, vgx4], { z1.h - z4.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x39, 0x08, 0x7e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w8, 2:3, vgx4], { z1.h - z4.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x78, 0x4a, 0x74, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w10, 0:1, vgx4], { z19.h - z22.h }, z4.h"
+
+  -
+    input:
+      bytes: [ 0x78, 0x4a, 0x74, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w10, 0:1, vgx4], { z19.h - z22.h }, z4.h"
+
+  -
+    input:
+      bytes: [ 0x98, 0x09, 0x72, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w8, 0:1, vgx4], { z12.h - z15.h }, z2.h"
+
+  -
+    input:
+      bytes: [ 0x98, 0x09, 0x72, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w8, 0:1, vgx4], { z12.h - z15.h }, z2.h"
+
+  -
+    input:
+      bytes: [ 0x39, 0x48, 0x7a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w10, 2:3, vgx4], { z1.h - z4.h }, z10.h"
+
+  -
+    input:
+      bytes: [ 0x39, 0x48, 0x7a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w10, 2:3, vgx4], { z1.h - z4.h }, z10.h"
+
+  -
+    input:
+      bytes: [ 0xd9, 0x0a, 0x7e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w8, 2:3, vgx4], { z22.h - z25.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0xd9, 0x0a, 0x7e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w8, 2:3, vgx4], { z22.h - z25.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x3a, 0x69, 0x71, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w11, 4:5, vgx4], { z9.h - z12.h }, z1.h"
+
+  -
+    input:
+      bytes: [ 0x3a, 0x69, 0x71, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w11, 4:5, vgx4], { z9.h - z12.h }, z1.h"
+
+  -
+    input:
+      bytes: [ 0x9b, 0x29, 0x7b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w9, 6:7, vgx4], { z12.h - z15.h }, z11.h"
+
+  -
+    input:
+      bytes: [ 0x9b, 0x29, 0x7b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w9, 6:7, vgx4], { z12.h - z15.h }, z11.h"
+
+  -
+    input:
+      bytes: [ 0x18, 0x90, 0xd0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w8, 0:1, vgx4], { z0.h - z3.h }, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x18, 0x90, 0xd0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w8, 0:1, vgx4], { z0.h - z3.h }, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x1d, 0xd5, 0xd5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w10, 2:3, vgx4], { z8.h - z11.h }, z5.h[3]"
+
+  -
+    input:
+      bytes: [ 0x1d, 0xd5, 0xd5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w10, 2:3, vgx4], { z8.h - z11.h }, z5.h[3]"
+
+  -
+    input:
+      bytes: [ 0x9f, 0xfd, 0xd8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w11, 6:7, vgx4], { z12.h - z15.h }, z8.h[7]"
+
+  -
+    input:
+      bytes: [ 0x9f, 0xfd, 0xd8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w11, 6:7, vgx4], { z12.h - z15.h }, z8.h[7]"
+
+  -
+    input:
+      bytes: [ 0x9f, 0xff, 0xdf, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w11, 6:7, vgx4], { z28.h - z31.h }, z15.h[7]"
+
+  -
+    input:
+      bytes: [ 0x9f, 0xff, 0xdf, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w11, 6:7, vgx4], { z28.h - z31.h }, z15.h[7]"
+
+  -
+    input:
+      bytes: [ 0x1d, 0x9e, 0xd0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w8, 2:3, vgx4], { z16.h - z19.h }, z0.h[7]"
+
+  -
+    input:
+      bytes: [ 0x1d, 0x9e, 0xd0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w8, 2:3, vgx4], { z16.h - z19.h }, z0.h[7]"
+
+  -
+    input:
+      bytes: [ 0x19, 0x94, 0xde, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w8, 2:3, vgx4], { z0.h - z3.h }, z14.h[2]"
+
+  -
+    input:
+      bytes: [ 0x19, 0x94, 0xde, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w8, 2:3, vgx4], { z0.h - z3.h }, z14.h[2]"
+
+  -
+    input:
+      bytes: [ 0x18, 0xd6, 0xd4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w10, 0:1, vgx4], { z16.h - z19.h }, z4.h[2]"
+
+  -
+    input:
+      bytes: [ 0x18, 0xd6, 0xd4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w10, 0:1, vgx4], { z16.h - z19.h }, z4.h[2]"
+
+  -
+    input:
+      bytes: [ 0x98, 0x99, 0xd2, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w8, 0:1, vgx4], { z12.h - z15.h }, z2.h[4]"
+
+  -
+    input:
+      bytes: [ 0x98, 0x99, 0xd2, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w8, 0:1, vgx4], { z12.h - z15.h }, z2.h[4]"
+
+  -
+    input:
+      bytes: [ 0x19, 0xd8, 0xda, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w10, 2:3, vgx4], { z0.h - z3.h }, z10.h[4]"
+
+  -
+    input:
+      bytes: [ 0x19, 0xd8, 0xda, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w10, 2:3, vgx4], { z0.h - z3.h }, z10.h[4]"
+
+  -
+    input:
+      bytes: [ 0x9d, 0x9a, 0xde, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w8, 2:3, vgx4], { z20.h - z23.h }, z14.h[5]"
+
+  -
+    input:
+      bytes: [ 0x9d, 0x9a, 0xde, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w8, 2:3, vgx4], { z20.h - z23.h }, z14.h[5]"
+
+  -
+    input:
+      bytes: [ 0x1a, 0xf5, 0xd1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w11, 4:5, vgx4], { z8.h - z11.h }, z1.h[2]"
+
+  -
+    input:
+      bytes: [ 0x1a, 0xf5, 0xd1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w11, 4:5, vgx4], { z8.h - z11.h }, z1.h[2]"
+
+  -
+    input:
+      bytes: [ 0x9f, 0xb9, 0xdb, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w9, 6:7, vgx4], { z12.h - z15.h }, z11.h[5]"
+
+  -
+    input:
+      bytes: [ 0x9f, 0xb9, 0xdb, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w9, 6:7, vgx4], { z12.h - z15.h }, z11.h[5]"
+
+  -
+    input:
+      bytes: [ 0x18, 0x08, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w8, 0:1, vgx4], { z0.h - z3.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x18, 0x08, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w8, 0:1, vgx4], { z0.h - z3.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x19, 0x49, 0xf5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w10, 2:3, vgx4], { z8.h - z11.h }, { z20.h - z23.h }"
+
+  -
+    input:
+      bytes: [ 0x19, 0x49, 0xf5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w10, 2:3, vgx4], { z8.h - z11.h }, { z20.h - z23.h }"
+
+  -
+    input:
+      bytes: [ 0x9b, 0x69, 0xe9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w11, 6:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }"
+
+  -
+    input:
+      bytes: [ 0x9b, 0x69, 0xe9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w11, 6:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }"
+
+  -
+    input:
+      bytes: [ 0x9b, 0x6b, 0xfd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w11, 6:7, vgx4], { z28.h - z31.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x9b, 0x6b, 0xfd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w11, 6:7, vgx4], { z28.h - z31.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x19, 0x0a, 0xf1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w8, 2:3, vgx4], { z16.h - z19.h }, { z16.h - z19.h }"
+
+  -
+    input:
+      bytes: [ 0x19, 0x0a, 0xf1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w8, 2:3, vgx4], { z16.h - z19.h }, { z16.h - z19.h }"
+
+  -
+    input:
+      bytes: [ 0x19, 0x08, 0xfd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w8, 2:3, vgx4], { z0.h - z3.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x19, 0x08, 0xfd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w8, 2:3, vgx4], { z0.h - z3.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x18, 0x4a, 0xf5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w10, 0:1, vgx4], { z16.h - z19.h }, { z20.h - z23.h }"
+
+  -
+    input:
+      bytes: [ 0x18, 0x4a, 0xf5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w10, 0:1, vgx4], { z16.h - z19.h }, { z20.h - z23.h }"
+
+  -
+    input:
+      bytes: [ 0x98, 0x09, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w8, 0:1, vgx4], { z12.h - z15.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x98, 0x09, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w8, 0:1, vgx4], { z12.h - z15.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x19, 0x48, 0xf9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w10, 2:3, vgx4], { z0.h - z3.h }, { z24.h - z27.h }"
+
+  -
+    input:
+      bytes: [ 0x19, 0x48, 0xf9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w10, 2:3, vgx4], { z0.h - z3.h }, { z24.h - z27.h }"
+
+  -
+    input:
+      bytes: [ 0x99, 0x0a, 0xfd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w8, 2:3, vgx4], { z20.h - z23.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x99, 0x0a, 0xfd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w8, 2:3, vgx4], { z20.h - z23.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x1a, 0x69, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w11, 4:5, vgx4], { z8.h - z11.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x1a, 0x69, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w11, 4:5, vgx4], { z8.h - z11.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x9b, 0x29, 0xe9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w9, 6:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }"
+
+  -
+    input:
+      bytes: [ 0x9b, 0x29, 0xe9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl za.s[w9, 6:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }"
diff --git a/tests/MC/AArch64/SME2/umlsll.s.yaml b/tests/MC/AArch64/SME2/umlsll.s.yaml
new file mode 100644
index 000000000..df3a56844
--- /dev/null
+++ b/tests/MC/AArch64/SME2/umlsll.s.yaml
@@ -0,0 +1,3360 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x18, 0x04, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w8, 0:3], z0.b, z0.b"
+
+  -
+    input:
+      bytes: [ 0x59, 0x45, 0x25, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w10, 4:7], z10.b, z5.b"
+
+  -
+    input:
+      bytes: [ 0xbb, 0x65, 0x28, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w11, 12:15], z13.b, z8.b"
+
+  -
+    input:
+      bytes: [ 0xfb, 0x67, 0x2f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w11, 12:15], z31.b, z15.b"
+
+  -
+    input:
+      bytes: [ 0x39, 0x06, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w8, 4:7], z17.b, z0.b"
+
+  -
+    input:
+      bytes: [ 0x39, 0x04, 0x2e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w8, 4:7], z1.b, z14.b"
+
+  -
+    input:
+      bytes: [ 0x78, 0x46, 0x24, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w10, 0:3], z19.b, z4.b"
+
+  -
+    input:
+      bytes: [ 0x98, 0x05, 0x22, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w8, 0:3], z12.b, z2.b"
+
+  -
+    input:
+      bytes: [ 0x39, 0x44, 0x2a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w10, 4:7], z1.b, z10.b"
+
+  -
+    input:
+      bytes: [ 0xd9, 0x06, 0x2e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w8, 4:7], z22.b, z14.b"
+
+  -
+    input:
+      bytes: [ 0x3a, 0x65, 0x21, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w11, 8:11], z9.b, z1.b"
+
+  -
+    input:
+      bytes: [ 0x9b, 0x25, 0x2b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w9, 12:15], z12.b, z11.b"
+
+  -
+    input:
+      bytes: [ 0x18, 0x00, 0x00, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w8, 0:3], z0.b, z0.b[0]"
+
+  -
+    input:
+      bytes: [ 0x59, 0x55, 0x05, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w10, 4:7], z10.b, z5.b[5]"
+
+  -
+    input:
+      bytes: [ 0xbb, 0xed, 0x08, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w11, 12:15], z13.b, z8.b[11]"
+
+  -
+    input:
+      bytes: [ 0xfb, 0xff, 0x0f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w11, 12:15], z31.b, z15.b[15]"
+
+  -
+    input:
+      bytes: [ 0x39, 0x0e, 0x00, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w8, 4:7], z17.b, z0.b[3]"
+
+  -
+    input:
+      bytes: [ 0x39, 0x84, 0x0e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w8, 4:7], z1.b, z14.b[9]"
+
+  -
+    input:
+      bytes: [ 0x78, 0x56, 0x04, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w10, 0:3], z19.b, z4.b[5]"
+
+  -
+    input:
+      bytes: [ 0x98, 0x19, 0x02, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w8, 0:3], z12.b, z2.b[6]"
+
+  -
+    input:
+      bytes: [ 0x39, 0xc8, 0x0a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w10, 4:7], z1.b, z10.b[10]"
+
+  -
+    input:
+      bytes: [ 0xd9, 0x0a, 0x0e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w8, 4:7], z22.b, z14.b[2]"
+
+  -
+    input:
+      bytes: [ 0x3a, 0xf5, 0x01, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w11, 8:11], z9.b, z1.b[13]"
+
+  -
+    input:
+      bytes: [ 0x9b, 0xa9, 0x0b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w9, 12:15], z12.b, z11.b[10]"
+
+  -
+    input:
+      bytes: [ 0x18, 0x04, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w8, 0:3], z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x59, 0x45, 0x65, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w10, 4:7], z10.h, z5.h"
+
+  -
+    input:
+      bytes: [ 0xbb, 0x65, 0x68, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w11, 12:15], z13.h, z8.h"
+
+  -
+    input:
+      bytes: [ 0xfb, 0x67, 0x6f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w11, 12:15], z31.h, z15.h"
+
+  -
+    input:
+      bytes: [ 0x39, 0x06, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w8, 4:7], z17.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x39, 0x04, 0x6e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w8, 4:7], z1.h, z14.h"
+
+  -
+    input:
+      bytes: [ 0x78, 0x46, 0x64, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w10, 0:3], z19.h, z4.h"
+
+  -
+    input:
+      bytes: [ 0x98, 0x05, 0x62, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w8, 0:3], z12.h, z2.h"
+
+  -
+    input:
+      bytes: [ 0x39, 0x44, 0x6a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w10, 4:7], z1.h, z10.h"
+
+  -
+    input:
+      bytes: [ 0xd9, 0x06, 0x6e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w8, 4:7], z22.h, z14.h"
+
+  -
+    input:
+      bytes: [ 0x3a, 0x65, 0x61, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w11, 8:11], z9.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0x9b, 0x25, 0x6b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w9, 12:15], z12.h, z11.h"
+
+  -
+    input:
+      bytes: [ 0x18, 0x00, 0x80, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w8, 0:3], z0.h, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x59, 0x45, 0x85, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w10, 4:7], z10.h, z5.h[1]"
+
+  -
+    input:
+      bytes: [ 0xbb, 0xed, 0x88, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w11, 12:15], z13.h, z8.h[7]"
+
+  -
+    input:
+      bytes: [ 0xfb, 0xef, 0x8f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w11, 12:15], z31.h, z15.h[7]"
+
+  -
+    input:
+      bytes: [ 0x39, 0x0e, 0x80, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w8, 4:7], z17.h, z0.h[3]"
+
+  -
+    input:
+      bytes: [ 0x39, 0x84, 0x8e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w8, 4:7], z1.h, z14.h[5]"
+
+  -
+    input:
+      bytes: [ 0x78, 0x46, 0x84, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w10, 0:3], z19.h, z4.h[1]"
+
+  -
+    input:
+      bytes: [ 0x98, 0x09, 0x82, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w8, 0:3], z12.h, z2.h[2]"
+
+  -
+    input:
+      bytes: [ 0x39, 0xc8, 0x8a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w10, 4:7], z1.h, z10.h[6]"
+
+  -
+    input:
+      bytes: [ 0xd9, 0x0a, 0x8e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w8, 4:7], z22.h, z14.h[2]"
+
+  -
+    input:
+      bytes: [ 0x3a, 0xe5, 0x81, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w11, 8:11], z9.h, z1.h[5]"
+
+  -
+    input:
+      bytes: [ 0x9b, 0xa9, 0x8b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w9, 12:15], z12.h, z11.h[6]"
+
+  -
+    input:
+      bytes: [ 0x18, 0x00, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w8, 0:3,  vgx2], { z0.b, z1.b }, z0.b"
+
+  -
+    input:
+      bytes: [ 0x18, 0x00, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w8, 0:3,  vgx2], { z0.b, z1.b }, z0.b"
+
+  -
+    input:
+      bytes: [ 0x59, 0x41, 0x25, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w10, 4:7,  vgx2], { z10.b, z11.b }, z5.b"
+
+  -
+    input:
+      bytes: [ 0x59, 0x41, 0x25, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w10, 4:7,  vgx2], { z10.b, z11.b }, z5.b"
+
+  -
+    input:
+      bytes: [ 0xb9, 0x61, 0x28, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w11, 4:7,  vgx2], { z13.b, z14.b }, z8.b"
+
+  -
+    input:
+      bytes: [ 0xb9, 0x61, 0x28, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w11, 4:7,  vgx2], { z13.b, z14.b }, z8.b"
+
+  -
+    input:
+      bytes: [ 0xf9, 0x63, 0x2f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w11, 4:7,  vgx2], { z31.b, z0.b }, z15.b"
+
+  -
+    input:
+      bytes: [ 0xf9, 0x63, 0x2f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w11, 4:7,  vgx2], { z31.b, z0.b }, z15.b"
+
+  -
+    input:
+      bytes: [ 0x39, 0x02, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w8, 4:7,  vgx2], { z17.b, z18.b }, z0.b"
+
+  -
+    input:
+      bytes: [ 0x39, 0x02, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w8, 4:7,  vgx2], { z17.b, z18.b }, z0.b"
+
+  -
+    input:
+      bytes: [ 0x39, 0x00, 0x2e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w8, 4:7,  vgx2], { z1.b, z2.b }, z14.b"
+
+  -
+    input:
+      bytes: [ 0x39, 0x00, 0x2e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w8, 4:7,  vgx2], { z1.b, z2.b }, z14.b"
+
+  -
+    input:
+      bytes: [ 0x78, 0x42, 0x24, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w10, 0:3,  vgx2], { z19.b, z20.b }, z4.b"
+
+  -
+    input:
+      bytes: [ 0x78, 0x42, 0x24, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w10, 0:3,  vgx2], { z19.b, z20.b }, z4.b"
+
+  -
+    input:
+      bytes: [ 0x98, 0x01, 0x22, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w8, 0:3,  vgx2], { z12.b, z13.b }, z2.b"
+
+  -
+    input:
+      bytes: [ 0x98, 0x01, 0x22, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w8, 0:3,  vgx2], { z12.b, z13.b }, z2.b"
+
+  -
+    input:
+      bytes: [ 0x39, 0x40, 0x2a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w10, 4:7,  vgx2], { z1.b, z2.b }, z10.b"
+
+  -
+    input:
+      bytes: [ 0x39, 0x40, 0x2a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w10, 4:7,  vgx2], { z1.b, z2.b }, z10.b"
+
+  -
+    input:
+      bytes: [ 0xd9, 0x02, 0x2e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w8, 4:7,  vgx2], { z22.b, z23.b }, z14.b"
+
+  -
+    input:
+      bytes: [ 0xd9, 0x02, 0x2e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w8, 4:7,  vgx2], { z22.b, z23.b }, z14.b"
+
+  -
+    input:
+      bytes: [ 0x38, 0x61, 0x21, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w11, 0:3,  vgx2], { z9.b, z10.b }, z1.b"
+
+  -
+    input:
+      bytes: [ 0x38, 0x61, 0x21, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w11, 0:3,  vgx2], { z9.b, z10.b }, z1.b"
+
+  -
+    input:
+      bytes: [ 0x99, 0x21, 0x2b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w9, 4:7,  vgx2], { z12.b, z13.b }, z11.b"
+
+  -
+    input:
+      bytes: [ 0x99, 0x21, 0x2b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w9, 4:7,  vgx2], { z12.b, z13.b }, z11.b"
+
+  -
+    input:
+      bytes: [ 0x18, 0x00, 0x10, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w8, 0:3, vgx2], { z0.b, z1.b }, z0.b[0]"
+
+  -
+    input:
+      bytes: [ 0x18, 0x00, 0x10, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w8, 0:3, vgx2], { z0.b, z1.b }, z0.b[0]"
+
+  -
+    input:
+      bytes: [ 0x5d, 0x45, 0x15, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w10, 4:7, vgx2], { z10.b, z11.b }, z5.b[6]"
+
+  -
+    input:
+      bytes: [ 0x5d, 0x45, 0x15, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w10, 4:7, vgx2], { z10.b, z11.b }, z5.b[6]"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x6d, 0x18, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w11, 4:7, vgx2], { z12.b, z13.b }, z8.b[15]"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x6d, 0x18, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w11, 4:7, vgx2], { z12.b, z13.b }, z8.b[15]"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x6f, 0x1f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w11, 4:7, vgx2], { z30.b, z31.b }, z15.b[15]"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x6f, 0x1f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w11, 4:7, vgx2], { z30.b, z31.b }, z15.b[15]"
+
+  -
+    input:
+      bytes: [ 0x1d, 0x0e, 0x10, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w8, 4:7, vgx2], { z16.b, z17.b }, z0.b[14]"
+
+  -
+    input:
+      bytes: [ 0x1d, 0x0e, 0x10, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w8, 4:7, vgx2], { z16.b, z17.b }, z0.b[14]"
+
+  -
+    input:
+      bytes: [ 0x19, 0x04, 0x1e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w8, 4:7, vgx2], { z0.b, z1.b }, z14.b[4]"
+
+  -
+    input:
+      bytes: [ 0x19, 0x04, 0x1e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w8, 4:7, vgx2], { z0.b, z1.b }, z14.b[4]"
+
+  -
+    input:
+      bytes: [ 0x58, 0x46, 0x14, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w10, 0:3, vgx2], { z18.b, z19.b }, z4.b[4]"
+
+  -
+    input:
+      bytes: [ 0x58, 0x46, 0x14, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w10, 0:3, vgx2], { z18.b, z19.b }, z4.b[4]"
+
+  -
+    input:
+      bytes: [ 0x98, 0x09, 0x12, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w8, 0:3, vgx2], { z12.b, z13.b }, z2.b[8]"
+
+  -
+    input:
+      bytes: [ 0x98, 0x09, 0x12, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w8, 0:3, vgx2], { z12.b, z13.b }, z2.b[8]"
+
+  -
+    input:
+      bytes: [ 0x19, 0x48, 0x1a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w10, 4:7, vgx2], { z0.b, z1.b }, z10.b[8]"
+
+  -
+    input:
+      bytes: [ 0x19, 0x48, 0x1a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w10, 4:7, vgx2], { z0.b, z1.b }, z10.b[8]"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x0a, 0x1e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w8, 4:7, vgx2], { z22.b, z23.b }, z14.b[10]"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x0a, 0x1e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w8, 4:7, vgx2], { z22.b, z23.b }, z14.b[10]"
+
+  -
+    input:
+      bytes: [ 0x1a, 0x65, 0x11, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w11, 0:3, vgx2], { z8.b, z9.b }, z1.b[5]"
+
+  -
+    input:
+      bytes: [ 0x1a, 0x65, 0x11, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w11, 0:3, vgx2], { z8.b, z9.b }, z1.b[5]"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x29, 0x1b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w9, 4:7, vgx2], { z12.b, z13.b }, z11.b[11]"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x29, 0x1b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w9, 4:7, vgx2], { z12.b, z13.b }, z11.b[11]"
+
+  -
+    input:
+      bytes: [ 0x18, 0x00, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w8, 0:3, vgx2], { z0.b, z1.b }, { z0.b, z1.b }"
+
+  -
+    input:
+      bytes: [ 0x18, 0x00, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w8, 0:3, vgx2], { z0.b, z1.b }, { z0.b, z1.b }"
+
+  -
+    input:
+      bytes: [ 0x59, 0x41, 0xb4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w10, 4:7, vgx2], { z10.b, z11.b }, { z20.b, z21.b }"
+
+  -
+    input:
+      bytes: [ 0x59, 0x41, 0xb4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w10, 4:7, vgx2], { z10.b, z11.b }, { z20.b, z21.b }"
+
+  -
+    input:
+      bytes: [ 0x99, 0x61, 0xa8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w11, 4:7, vgx2], { z12.b, z13.b }, { z8.b, z9.b }"
+
+  -
+    input:
+      bytes: [ 0x99, 0x61, 0xa8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w11, 4:7, vgx2], { z12.b, z13.b }, { z8.b, z9.b }"
+
+  -
+    input:
+      bytes: [ 0xd9, 0x63, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w11, 4:7, vgx2], { z30.b, z31.b }, { z30.b, z31.b }"
+
+  -
+    input:
+      bytes: [ 0xd9, 0x63, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w11, 4:7, vgx2], { z30.b, z31.b }, { z30.b, z31.b }"
+
+  -
+    input:
+      bytes: [ 0x19, 0x02, 0xb0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w8, 4:7, vgx2], { z16.b, z17.b }, { z16.b, z17.b }"
+
+  -
+    input:
+      bytes: [ 0x19, 0x02, 0xb0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w8, 4:7, vgx2], { z16.b, z17.b }, { z16.b, z17.b }"
+
+  -
+    input:
+      bytes: [ 0x19, 0x00, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w8, 4:7, vgx2], { z0.b, z1.b }, { z30.b, z31.b }"
+
+  -
+    input:
+      bytes: [ 0x19, 0x00, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w8, 4:7, vgx2], { z0.b, z1.b }, { z30.b, z31.b }"
+
+  -
+    input:
+      bytes: [ 0x58, 0x42, 0xb4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w10, 0:3, vgx2], { z18.b, z19.b }, { z20.b, z21.b }"
+
+  -
+    input:
+      bytes: [ 0x58, 0x42, 0xb4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w10, 0:3, vgx2], { z18.b, z19.b }, { z20.b, z21.b }"
+
+  -
+    input:
+      bytes: [ 0x98, 0x01, 0xa2, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w8, 0:3, vgx2], { z12.b, z13.b }, { z2.b, z3.b }"
+
+  -
+    input:
+      bytes: [ 0x98, 0x01, 0xa2, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w8, 0:3, vgx2], { z12.b, z13.b }, { z2.b, z3.b }"
+
+  -
+    input:
+      bytes: [ 0x19, 0x40, 0xba, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w10, 4:7, vgx2], { z0.b, z1.b }, { z26.b, z27.b }"
+
+  -
+    input:
+      bytes: [ 0x19, 0x40, 0xba, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w10, 4:7, vgx2], { z0.b, z1.b }, { z26.b, z27.b }"
+
+  -
+    input:
+      bytes: [ 0xd9, 0x02, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w8, 4:7, vgx2], { z22.b, z23.b }, { z30.b, z31.b }"
+
+  -
+    input:
+      bytes: [ 0xd9, 0x02, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w8, 4:7, vgx2], { z22.b, z23.b }, { z30.b, z31.b }"
+
+  -
+    input:
+      bytes: [ 0x18, 0x61, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w11, 0:3, vgx2], { z8.b, z9.b }, { z0.b, z1.b }"
+
+  -
+    input:
+      bytes: [ 0x18, 0x61, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w11, 0:3, vgx2], { z8.b, z9.b }, { z0.b, z1.b }"
+
+  -
+    input:
+      bytes: [ 0x99, 0x21, 0xaa, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w9, 4:7, vgx2], { z12.b, z13.b }, { z10.b, z11.b }"
+
+  -
+    input:
+      bytes: [ 0x99, 0x21, 0xaa, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w9, 4:7, vgx2], { z12.b, z13.b }, { z10.b, z11.b }"
+
+  -
+    input:
+      bytes: [ 0x18, 0x00, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w8, 0:3,  vgx2], { z0.h, z1.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x18, 0x00, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w8, 0:3,  vgx2], { z0.h, z1.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x59, 0x41, 0x65, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w10, 4:7,  vgx2], { z10.h, z11.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0x59, 0x41, 0x65, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w10, 4:7,  vgx2], { z10.h, z11.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0xb9, 0x61, 0x68, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w11, 4:7,  vgx2], { z13.h, z14.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0xb9, 0x61, 0x68, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w11, 4:7,  vgx2], { z13.h, z14.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0xf9, 0x63, 0x6f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w11, 4:7,  vgx2], { z31.h, z0.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0xf9, 0x63, 0x6f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w11, 4:7,  vgx2], { z31.h, z0.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0x39, 0x02, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w8, 4:7,  vgx2], { z17.h, z18.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x39, 0x02, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w8, 4:7,  vgx2], { z17.h, z18.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x39, 0x00, 0x6e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w8, 4:7,  vgx2], { z1.h, z2.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x39, 0x00, 0x6e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w8, 4:7,  vgx2], { z1.h, z2.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x78, 0x42, 0x64, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w10, 0:3,  vgx2], { z19.h, z20.h }, z4.h"
+
+  -
+    input:
+      bytes: [ 0x78, 0x42, 0x64, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w10, 0:3,  vgx2], { z19.h, z20.h }, z4.h"
+
+  -
+    input:
+      bytes: [ 0x98, 0x01, 0x62, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w8, 0:3,  vgx2], { z12.h, z13.h }, z2.h"
+
+  -
+    input:
+      bytes: [ 0x98, 0x01, 0x62, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w8, 0:3,  vgx2], { z12.h, z13.h }, z2.h"
+
+  -
+    input:
+      bytes: [ 0x39, 0x40, 0x6a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w10, 4:7,  vgx2], { z1.h, z2.h }, z10.h"
+
+  -
+    input:
+      bytes: [ 0x39, 0x40, 0x6a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w10, 4:7,  vgx2], { z1.h, z2.h }, z10.h"
+
+  -
+    input:
+      bytes: [ 0xd9, 0x02, 0x6e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w8, 4:7,  vgx2], { z22.h, z23.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0xd9, 0x02, 0x6e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w8, 4:7,  vgx2], { z22.h, z23.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x38, 0x61, 0x61, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w11, 0:3,  vgx2], { z9.h, z10.h }, z1.h"
+
+  -
+    input:
+      bytes: [ 0x38, 0x61, 0x61, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w11, 0:3,  vgx2], { z9.h, z10.h }, z1.h"
+
+  -
+    input:
+      bytes: [ 0x99, 0x21, 0x6b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w9, 4:7,  vgx2], { z12.h, z13.h }, z11.h"
+
+  -
+    input:
+      bytes: [ 0x99, 0x21, 0x6b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w9, 4:7,  vgx2], { z12.h, z13.h }, z11.h"
+
+  -
+    input:
+      bytes: [ 0x18, 0x00, 0x90, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w8, 0:3, vgx2], { z0.h, z1.h }, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x18, 0x00, 0x90, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w8, 0:3, vgx2], { z0.h, z1.h }, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x5d, 0x45, 0x95, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w10, 4:7, vgx2], { z10.h, z11.h }, z5.h[6]"
+
+  -
+    input:
+      bytes: [ 0x5d, 0x45, 0x95, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w10, 4:7, vgx2], { z10.h, z11.h }, z5.h[6]"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x65, 0x98, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w11, 4:7, vgx2], { z12.h, z13.h }, z8.h[7]"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x65, 0x98, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w11, 4:7, vgx2], { z12.h, z13.h }, z8.h[7]"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x67, 0x9f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w11, 4:7, vgx2], { z30.h, z31.h }, z15.h[7]"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x67, 0x9f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w11, 4:7, vgx2], { z30.h, z31.h }, z15.h[7]"
+
+  -
+    input:
+      bytes: [ 0x1d, 0x06, 0x90, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w8, 4:7, vgx2], { z16.h, z17.h }, z0.h[6]"
+
+  -
+    input:
+      bytes: [ 0x1d, 0x06, 0x90, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w8, 4:7, vgx2], { z16.h, z17.h }, z0.h[6]"
+
+  -
+    input:
+      bytes: [ 0x19, 0x04, 0x9e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w8, 4:7, vgx2], { z0.h, z1.h }, z14.h[4]"
+
+  -
+    input:
+      bytes: [ 0x19, 0x04, 0x9e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w8, 4:7, vgx2], { z0.h, z1.h }, z14.h[4]"
+
+  -
+    input:
+      bytes: [ 0x58, 0x46, 0x94, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w10, 0:3, vgx2], { z18.h, z19.h }, z4.h[4]"
+
+  -
+    input:
+      bytes: [ 0x58, 0x46, 0x94, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w10, 0:3, vgx2], { z18.h, z19.h }, z4.h[4]"
+
+  -
+    input:
+      bytes: [ 0x98, 0x01, 0x92, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w8, 0:3, vgx2], { z12.h, z13.h }, z2.h[0]"
+
+  -
+    input:
+      bytes: [ 0x98, 0x01, 0x92, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w8, 0:3, vgx2], { z12.h, z13.h }, z2.h[0]"
+
+  -
+    input:
+      bytes: [ 0x19, 0x40, 0x9a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w10, 4:7, vgx2], { z0.h, z1.h }, z10.h[0]"
+
+  -
+    input:
+      bytes: [ 0x19, 0x40, 0x9a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w10, 4:7, vgx2], { z0.h, z1.h }, z10.h[0]"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x02, 0x9e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w8, 4:7, vgx2], { z22.h, z23.h }, z14.h[2]"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x02, 0x9e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w8, 4:7, vgx2], { z22.h, z23.h }, z14.h[2]"
+
+  -
+    input:
+      bytes: [ 0x1a, 0x65, 0x91, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w11, 0:3, vgx2], { z8.h, z9.h }, z1.h[5]"
+
+  -
+    input:
+      bytes: [ 0x1a, 0x65, 0x91, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w11, 0:3, vgx2], { z8.h, z9.h }, z1.h[5]"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x21, 0x9b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w9, 4:7, vgx2], { z12.h, z13.h }, z11.h[3]"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x21, 0x9b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w9, 4:7, vgx2], { z12.h, z13.h }, z11.h[3]"
+
+  -
+    input:
+      bytes: [ 0x18, 0x00, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w8, 0:3, vgx2], { z0.h, z1.h }, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x18, 0x00, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w8, 0:3, vgx2], { z0.h, z1.h }, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x59, 0x41, 0xf4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w10, 4:7, vgx2], { z10.h, z11.h }, { z20.h, z21.h }"
+
+  -
+    input:
+      bytes: [ 0x59, 0x41, 0xf4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w10, 4:7, vgx2], { z10.h, z11.h }, { z20.h, z21.h }"
+
+  -
+    input:
+      bytes: [ 0x99, 0x61, 0xe8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w11, 4:7, vgx2], { z12.h, z13.h }, { z8.h, z9.h }"
+
+  -
+    input:
+      bytes: [ 0x99, 0x61, 0xe8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w11, 4:7, vgx2], { z12.h, z13.h }, { z8.h, z9.h }"
+
+  -
+    input:
+      bytes: [ 0xd9, 0x63, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w11, 4:7, vgx2], { z30.h, z31.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0xd9, 0x63, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w11, 4:7, vgx2], { z30.h, z31.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x19, 0x02, 0xf0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w8, 4:7, vgx2], { z16.h, z17.h }, { z16.h, z17.h }"
+
+  -
+    input:
+      bytes: [ 0x19, 0x02, 0xf0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w8, 4:7, vgx2], { z16.h, z17.h }, { z16.h, z17.h }"
+
+  -
+    input:
+      bytes: [ 0x19, 0x00, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w8, 4:7, vgx2], { z0.h, z1.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x19, 0x00, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w8, 4:7, vgx2], { z0.h, z1.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x58, 0x42, 0xf4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w10, 0:3, vgx2], { z18.h, z19.h }, { z20.h, z21.h }"
+
+  -
+    input:
+      bytes: [ 0x58, 0x42, 0xf4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w10, 0:3, vgx2], { z18.h, z19.h }, { z20.h, z21.h }"
+
+  -
+    input:
+      bytes: [ 0x98, 0x01, 0xe2, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w8, 0:3, vgx2], { z12.h, z13.h }, { z2.h, z3.h }"
+
+  -
+    input:
+      bytes: [ 0x98, 0x01, 0xe2, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w8, 0:3, vgx2], { z12.h, z13.h }, { z2.h, z3.h }"
+
+  -
+    input:
+      bytes: [ 0x19, 0x40, 0xfa, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w10, 4:7, vgx2], { z0.h, z1.h }, { z26.h, z27.h }"
+
+  -
+    input:
+      bytes: [ 0x19, 0x40, 0xfa, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w10, 4:7, vgx2], { z0.h, z1.h }, { z26.h, z27.h }"
+
+  -
+    input:
+      bytes: [ 0xd9, 0x02, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w8, 4:7, vgx2], { z22.h, z23.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0xd9, 0x02, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w8, 4:7, vgx2], { z22.h, z23.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x18, 0x61, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w11, 0:3, vgx2], { z8.h, z9.h }, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x18, 0x61, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w11, 0:3, vgx2], { z8.h, z9.h }, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x99, 0x21, 0xea, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w9, 4:7, vgx2], { z12.h, z13.h }, { z10.h, z11.h }"
+
+  -
+    input:
+      bytes: [ 0x99, 0x21, 0xea, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w9, 4:7, vgx2], { z12.h, z13.h }, { z10.h, z11.h }"
+
+  -
+    input:
+      bytes: [ 0x18, 0x00, 0x30, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w8, 0:3,  vgx4], { z0.b - z3.b }, z0.b"
+
+  -
+    input:
+      bytes: [ 0x18, 0x00, 0x30, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w8, 0:3,  vgx4], { z0.b - z3.b }, z0.b"
+
+  -
+    input:
+      bytes: [ 0x59, 0x41, 0x35, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w10, 4:7,  vgx4], { z10.b - z13.b }, z5.b"
+
+  -
+    input:
+      bytes: [ 0x59, 0x41, 0x35, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w10, 4:7,  vgx4], { z10.b - z13.b }, z5.b"
+
+  -
+    input:
+      bytes: [ 0xb9, 0x61, 0x38, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w11, 4:7,  vgx4], { z13.b - z16.b }, z8.b"
+
+  -
+    input:
+      bytes: [ 0xb9, 0x61, 0x38, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w11, 4:7,  vgx4], { z13.b - z16.b }, z8.b"
+
+  -
+    input:
+      bytes: [ 0xf9, 0x63, 0x3f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w11, 4:7,  vgx4], { z31.b, z0.b, z1.b, z2.b }, z15.b"
+
+  -
+    input:
+      bytes: [ 0xf9, 0x63, 0x3f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w11, 4:7,  vgx4], { z31.b, z0.b, z1.b, z2.b }, z15.b"
+
+  -
+    input:
+      bytes: [ 0x39, 0x02, 0x30, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w8, 4:7,  vgx4], { z17.b - z20.b }, z0.b"
+
+  -
+    input:
+      bytes: [ 0x39, 0x02, 0x30, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w8, 4:7,  vgx4], { z17.b - z20.b }, z0.b"
+
+  -
+    input:
+      bytes: [ 0x39, 0x00, 0x3e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w8, 4:7,  vgx4], { z1.b - z4.b }, z14.b"
+
+  -
+    input:
+      bytes: [ 0x39, 0x00, 0x3e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w8, 4:7,  vgx4], { z1.b - z4.b }, z14.b"
+
+  -
+    input:
+      bytes: [ 0x78, 0x42, 0x34, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w10, 0:3,  vgx4], { z19.b - z22.b }, z4.b"
+
+  -
+    input:
+      bytes: [ 0x78, 0x42, 0x34, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w10, 0:3,  vgx4], { z19.b - z22.b }, z4.b"
+
+  -
+    input:
+      bytes: [ 0x98, 0x01, 0x32, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w8, 0:3,  vgx4], { z12.b - z15.b }, z2.b"
+
+  -
+    input:
+      bytes: [ 0x98, 0x01, 0x32, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w8, 0:3,  vgx4], { z12.b - z15.b }, z2.b"
+
+  -
+    input:
+      bytes: [ 0x39, 0x40, 0x3a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w10, 4:7,  vgx4], { z1.b - z4.b }, z10.b"
+
+  -
+    input:
+      bytes: [ 0x39, 0x40, 0x3a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w10, 4:7,  vgx4], { z1.b - z4.b }, z10.b"
+
+  -
+    input:
+      bytes: [ 0xd9, 0x02, 0x3e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w8, 4:7,  vgx4], { z22.b - z25.b }, z14.b"
+
+  -
+    input:
+      bytes: [ 0xd9, 0x02, 0x3e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w8, 4:7,  vgx4], { z22.b - z25.b }, z14.b"
+
+  -
+    input:
+      bytes: [ 0x38, 0x61, 0x31, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w11, 0:3,  vgx4], { z9.b - z12.b }, z1.b"
+
+  -
+    input:
+      bytes: [ 0x38, 0x61, 0x31, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w11, 0:3,  vgx4], { z9.b - z12.b }, z1.b"
+
+  -
+    input:
+      bytes: [ 0x99, 0x21, 0x3b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w9, 4:7,  vgx4], { z12.b - z15.b }, z11.b"
+
+  -
+    input:
+      bytes: [ 0x99, 0x21, 0x3b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w9, 4:7,  vgx4], { z12.b - z15.b }, z11.b"
+
+  -
+    input:
+      bytes: [ 0x18, 0x80, 0x10, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w8, 0:3, vgx4], { z0.b - z3.b }, z0.b[0]"
+
+  -
+    input:
+      bytes: [ 0x18, 0x80, 0x10, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w8, 0:3, vgx4], { z0.b - z3.b }, z0.b[0]"
+
+  -
+    input:
+      bytes: [ 0x1d, 0xc5, 0x15, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w10, 4:7, vgx4], { z8.b - z11.b }, z5.b[6]"
+
+  -
+    input:
+      bytes: [ 0x1d, 0xc5, 0x15, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w10, 4:7, vgx4], { z8.b - z11.b }, z5.b[6]"
+
+  -
+    input:
+      bytes: [ 0x9f, 0xed, 0x18, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w11, 4:7, vgx4], { z12.b - z15.b }, z8.b[15]"
+
+  -
+    input:
+      bytes: [ 0x9f, 0xed, 0x18, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w11, 4:7, vgx4], { z12.b - z15.b }, z8.b[15]"
+
+  -
+    input:
+      bytes: [ 0x9f, 0xef, 0x1f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w11, 4:7, vgx4], { z28.b - z31.b }, z15.b[15]"
+
+  -
+    input:
+      bytes: [ 0x9f, 0xef, 0x1f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w11, 4:7, vgx4], { z28.b - z31.b }, z15.b[15]"
+
+  -
+    input:
+      bytes: [ 0x1d, 0x8e, 0x10, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w8, 4:7, vgx4], { z16.b - z19.b }, z0.b[14]"
+
+  -
+    input:
+      bytes: [ 0x1d, 0x8e, 0x10, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w8, 4:7, vgx4], { z16.b - z19.b }, z0.b[14]"
+
+  -
+    input:
+      bytes: [ 0x19, 0x84, 0x1e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w8, 4:7, vgx4], { z0.b - z3.b }, z14.b[4]"
+
+  -
+    input:
+      bytes: [ 0x19, 0x84, 0x1e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w8, 4:7, vgx4], { z0.b - z3.b }, z14.b[4]"
+
+  -
+    input:
+      bytes: [ 0x18, 0xc6, 0x14, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w10, 0:3, vgx4], { z16.b - z19.b }, z4.b[4]"
+
+  -
+    input:
+      bytes: [ 0x18, 0xc6, 0x14, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w10, 0:3, vgx4], { z16.b - z19.b }, z4.b[4]"
+
+  -
+    input:
+      bytes: [ 0x98, 0x89, 0x12, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w8, 0:3, vgx4], { z12.b - z15.b }, z2.b[8]"
+
+  -
+    input:
+      bytes: [ 0x98, 0x89, 0x12, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w8, 0:3, vgx4], { z12.b - z15.b }, z2.b[8]"
+
+  -
+    input:
+      bytes: [ 0x19, 0xc8, 0x1a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w10, 4:7, vgx4], { z0.b - z3.b }, z10.b[8]"
+
+  -
+    input:
+      bytes: [ 0x19, 0xc8, 0x1a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w10, 4:7, vgx4], { z0.b - z3.b }, z10.b[8]"
+
+  -
+    input:
+      bytes: [ 0x9d, 0x8a, 0x1e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w8, 4:7, vgx4], { z20.b - z23.b }, z14.b[10]"
+
+  -
+    input:
+      bytes: [ 0x9d, 0x8a, 0x1e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w8, 4:7, vgx4], { z20.b - z23.b }, z14.b[10]"
+
+  -
+    input:
+      bytes: [ 0x1a, 0xe5, 0x11, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w11, 0:3, vgx4], { z8.b - z11.b }, z1.b[5]"
+
+  -
+    input:
+      bytes: [ 0x1a, 0xe5, 0x11, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w11, 0:3, vgx4], { z8.b - z11.b }, z1.b[5]"
+
+  -
+    input:
+      bytes: [ 0x9f, 0xa9, 0x1b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w9, 4:7, vgx4], { z12.b - z15.b }, z11.b[11]"
+
+  -
+    input:
+      bytes: [ 0x9f, 0xa9, 0x1b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w9, 4:7, vgx4], { z12.b - z15.b }, z11.b[11]"
+
+  -
+    input:
+      bytes: [ 0x18, 0x00, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w8, 0:3, vgx4], { z0.b - z3.b }, { z0.b - z3.b }"
+
+  -
+    input:
+      bytes: [ 0x18, 0x00, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w8, 0:3, vgx4], { z0.b - z3.b }, { z0.b - z3.b }"
+
+  -
+    input:
+      bytes: [ 0x19, 0x41, 0xb5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w10, 4:7, vgx4], { z8.b - z11.b }, { z20.b - z23.b }"
+
+  -
+    input:
+      bytes: [ 0x19, 0x41, 0xb5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w10, 4:7, vgx4], { z8.b - z11.b }, { z20.b - z23.b }"
+
+  -
+    input:
+      bytes: [ 0x99, 0x61, 0xa9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w11, 4:7, vgx4], { z12.b - z15.b }, { z8.b - z11.b }"
+
+  -
+    input:
+      bytes: [ 0x99, 0x61, 0xa9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w11, 4:7, vgx4], { z12.b - z15.b }, { z8.b - z11.b }"
+
+  -
+    input:
+      bytes: [ 0x99, 0x63, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w11, 4:7, vgx4], { z28.b - z31.b }, { z28.b - z31.b }"
+
+  -
+    input:
+      bytes: [ 0x99, 0x63, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w11, 4:7, vgx4], { z28.b - z31.b }, { z28.b - z31.b }"
+
+  -
+    input:
+      bytes: [ 0x19, 0x02, 0xb1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w8, 4:7, vgx4], { z16.b - z19.b }, { z16.b - z19.b }"
+
+  -
+    input:
+      bytes: [ 0x19, 0x02, 0xb1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w8, 4:7, vgx4], { z16.b - z19.b }, { z16.b - z19.b }"
+
+  -
+    input:
+      bytes: [ 0x19, 0x00, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w8, 4:7, vgx4], { z0.b - z3.b }, { z28.b - z31.b }"
+
+  -
+    input:
+      bytes: [ 0x19, 0x00, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w8, 4:7, vgx4], { z0.b - z3.b }, { z28.b - z31.b }"
+
+  -
+    input:
+      bytes: [ 0x18, 0x42, 0xb5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w10, 0:3, vgx4], { z16.b - z19.b }, { z20.b - z23.b }"
+
+  -
+    input:
+      bytes: [ 0x18, 0x42, 0xb5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w10, 0:3, vgx4], { z16.b - z19.b }, { z20.b - z23.b }"
+
+  -
+    input:
+      bytes: [ 0x98, 0x01, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w8, 0:3, vgx4], { z12.b - z15.b }, { z0.b - z3.b }"
+
+  -
+    input:
+      bytes: [ 0x98, 0x01, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w8, 0:3, vgx4], { z12.b - z15.b }, { z0.b - z3.b }"
+
+  -
+    input:
+      bytes: [ 0x19, 0x40, 0xb9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w10, 4:7, vgx4], { z0.b - z3.b }, { z24.b - z27.b }"
+
+  -
+    input:
+      bytes: [ 0x19, 0x40, 0xb9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w10, 4:7, vgx4], { z0.b - z3.b }, { z24.b - z27.b }"
+
+  -
+    input:
+      bytes: [ 0x99, 0x02, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w8, 4:7, vgx4], { z20.b - z23.b }, { z28.b - z31.b }"
+
+  -
+    input:
+      bytes: [ 0x99, 0x02, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w8, 4:7, vgx4], { z20.b - z23.b }, { z28.b - z31.b }"
+
+  -
+    input:
+      bytes: [ 0x18, 0x61, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w11, 0:3, vgx4], { z8.b - z11.b }, { z0.b - z3.b }"
+
+  -
+    input:
+      bytes: [ 0x18, 0x61, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w11, 0:3, vgx4], { z8.b - z11.b }, { z0.b - z3.b }"
+
+  -
+    input:
+      bytes: [ 0x99, 0x21, 0xa9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w9, 4:7, vgx4], { z12.b - z15.b }, { z8.b - z11.b }"
+
+  -
+    input:
+      bytes: [ 0x99, 0x21, 0xa9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.s[w9, 4:7, vgx4], { z12.b - z15.b }, { z8.b - z11.b }"
+
+  -
+    input:
+      bytes: [ 0x18, 0x00, 0x70, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w8, 0:3,  vgx4], { z0.h - z3.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x18, 0x00, 0x70, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w8, 0:3,  vgx4], { z0.h - z3.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x59, 0x41, 0x75, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w10, 4:7,  vgx4], { z10.h - z13.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0x59, 0x41, 0x75, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w10, 4:7,  vgx4], { z10.h - z13.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0xb9, 0x61, 0x78, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w11, 4:7,  vgx4], { z13.h - z16.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0xb9, 0x61, 0x78, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w11, 4:7,  vgx4], { z13.h - z16.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0xf9, 0x63, 0x7f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w11, 4:7,  vgx4], { z31.h, z0.h, z1.h, z2.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0xf9, 0x63, 0x7f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w11, 4:7,  vgx4], { z31.h, z0.h, z1.h, z2.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0x39, 0x02, 0x70, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w8, 4:7,  vgx4], { z17.h - z20.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x39, 0x02, 0x70, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w8, 4:7,  vgx4], { z17.h - z20.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x39, 0x00, 0x7e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w8, 4:7,  vgx4], { z1.h - z4.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x39, 0x00, 0x7e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w8, 4:7,  vgx4], { z1.h - z4.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x78, 0x42, 0x74, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w10, 0:3,  vgx4], { z19.h - z22.h }, z4.h"
+
+  -
+    input:
+      bytes: [ 0x78, 0x42, 0x74, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w10, 0:3,  vgx4], { z19.h - z22.h }, z4.h"
+
+  -
+    input:
+      bytes: [ 0x98, 0x01, 0x72, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w8, 0:3,  vgx4], { z12.h - z15.h }, z2.h"
+
+  -
+    input:
+      bytes: [ 0x98, 0x01, 0x72, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w8, 0:3,  vgx4], { z12.h - z15.h }, z2.h"
+
+  -
+    input:
+      bytes: [ 0x39, 0x40, 0x7a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w10, 4:7,  vgx4], { z1.h - z4.h }, z10.h"
+
+  -
+    input:
+      bytes: [ 0x39, 0x40, 0x7a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w10, 4:7,  vgx4], { z1.h - z4.h }, z10.h"
+
+  -
+    input:
+      bytes: [ 0xd9, 0x02, 0x7e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w8, 4:7,  vgx4], { z22.h - z25.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0xd9, 0x02, 0x7e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w8, 4:7,  vgx4], { z22.h - z25.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x38, 0x61, 0x71, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w11, 0:3,  vgx4], { z9.h - z12.h }, z1.h"
+
+  -
+    input:
+      bytes: [ 0x38, 0x61, 0x71, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w11, 0:3,  vgx4], { z9.h - z12.h }, z1.h"
+
+  -
+    input:
+      bytes: [ 0x99, 0x21, 0x7b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w9, 4:7,  vgx4], { z12.h - z15.h }, z11.h"
+
+  -
+    input:
+      bytes: [ 0x99, 0x21, 0x7b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w9, 4:7,  vgx4], { z12.h - z15.h }, z11.h"
+
+  -
+    input:
+      bytes: [ 0x18, 0x80, 0x90, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w8, 0:3, vgx4], { z0.h - z3.h }, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x18, 0x80, 0x90, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w8, 0:3, vgx4], { z0.h - z3.h }, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x1d, 0xc5, 0x95, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w10, 4:7, vgx4], { z8.h - z11.h }, z5.h[6]"
+
+  -
+    input:
+      bytes: [ 0x1d, 0xc5, 0x95, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w10, 4:7, vgx4], { z8.h - z11.h }, z5.h[6]"
+
+  -
+    input:
+      bytes: [ 0x9f, 0xe5, 0x98, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w11, 4:7, vgx4], { z12.h - z15.h }, z8.h[7]"
+
+  -
+    input:
+      bytes: [ 0x9f, 0xe5, 0x98, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w11, 4:7, vgx4], { z12.h - z15.h }, z8.h[7]"
+
+  -
+    input:
+      bytes: [ 0x9f, 0xe7, 0x9f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w11, 4:7, vgx4], { z28.h - z31.h }, z15.h[7]"
+
+  -
+    input:
+      bytes: [ 0x9f, 0xe7, 0x9f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w11, 4:7, vgx4], { z28.h - z31.h }, z15.h[7]"
+
+  -
+    input:
+      bytes: [ 0x1d, 0x86, 0x90, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w8, 4:7, vgx4], { z16.h - z19.h }, z0.h[6]"
+
+  -
+    input:
+      bytes: [ 0x1d, 0x86, 0x90, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w8, 4:7, vgx4], { z16.h - z19.h }, z0.h[6]"
+
+  -
+    input:
+      bytes: [ 0x19, 0x84, 0x9e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w8, 4:7, vgx4], { z0.h - z3.h }, z14.h[4]"
+
+  -
+    input:
+      bytes: [ 0x19, 0x84, 0x9e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w8, 4:7, vgx4], { z0.h - z3.h }, z14.h[4]"
+
+  -
+    input:
+      bytes: [ 0x18, 0xc6, 0x94, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w10, 0:3, vgx4], { z16.h - z19.h }, z4.h[4]"
+
+  -
+    input:
+      bytes: [ 0x18, 0xc6, 0x94, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w10, 0:3, vgx4], { z16.h - z19.h }, z4.h[4]"
+
+  -
+    input:
+      bytes: [ 0x98, 0x81, 0x92, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w8, 0:3, vgx4], { z12.h - z15.h }, z2.h[0]"
+
+  -
+    input:
+      bytes: [ 0x98, 0x81, 0x92, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w8, 0:3, vgx4], { z12.h - z15.h }, z2.h[0]"
+
+  -
+    input:
+      bytes: [ 0x19, 0xc0, 0x9a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w10, 4:7, vgx4], { z0.h - z3.h }, z10.h[0]"
+
+  -
+    input:
+      bytes: [ 0x19, 0xc0, 0x9a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w10, 4:7, vgx4], { z0.h - z3.h }, z10.h[0]"
+
+  -
+    input:
+      bytes: [ 0x9d, 0x82, 0x9e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w8, 4:7, vgx4], { z20.h - z23.h }, z14.h[2]"
+
+  -
+    input:
+      bytes: [ 0x9d, 0x82, 0x9e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w8, 4:7, vgx4], { z20.h - z23.h }, z14.h[2]"
+
+  -
+    input:
+      bytes: [ 0x1a, 0xe5, 0x91, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w11, 0:3, vgx4], { z8.h - z11.h }, z1.h[5]"
+
+  -
+    input:
+      bytes: [ 0x1a, 0xe5, 0x91, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w11, 0:3, vgx4], { z8.h - z11.h }, z1.h[5]"
+
+  -
+    input:
+      bytes: [ 0x9f, 0xa1, 0x9b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w9, 4:7, vgx4], { z12.h - z15.h }, z11.h[3]"
+
+  -
+    input:
+      bytes: [ 0x9f, 0xa1, 0x9b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w9, 4:7, vgx4], { z12.h - z15.h }, z11.h[3]"
+
+  -
+    input:
+      bytes: [ 0x18, 0x00, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w8, 0:3, vgx4], { z0.h - z3.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x18, 0x00, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w8, 0:3, vgx4], { z0.h - z3.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x19, 0x41, 0xf5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w10, 4:7, vgx4], { z8.h - z11.h }, { z20.h - z23.h }"
+
+  -
+    input:
+      bytes: [ 0x19, 0x41, 0xf5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w10, 4:7, vgx4], { z8.h - z11.h }, { z20.h - z23.h }"
+
+  -
+    input:
+      bytes: [ 0x99, 0x61, 0xe9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w11, 4:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }"
+
+  -
+    input:
+      bytes: [ 0x99, 0x61, 0xe9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w11, 4:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }"
+
+  -
+    input:
+      bytes: [ 0x99, 0x63, 0xfd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w11, 4:7, vgx4], { z28.h - z31.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x99, 0x63, 0xfd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w11, 4:7, vgx4], { z28.h - z31.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x19, 0x02, 0xf1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w8, 4:7, vgx4], { z16.h - z19.h }, { z16.h - z19.h }"
+
+  -
+    input:
+      bytes: [ 0x19, 0x02, 0xf1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w8, 4:7, vgx4], { z16.h - z19.h }, { z16.h - z19.h }"
+
+  -
+    input:
+      bytes: [ 0x19, 0x00, 0xfd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w8, 4:7, vgx4], { z0.h - z3.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x19, 0x00, 0xfd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w8, 4:7, vgx4], { z0.h - z3.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x18, 0x42, 0xf5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w10, 0:3, vgx4], { z16.h - z19.h }, { z20.h - z23.h }"
+
+  -
+    input:
+      bytes: [ 0x18, 0x42, 0xf5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w10, 0:3, vgx4], { z16.h - z19.h }, { z20.h - z23.h }"
+
+  -
+    input:
+      bytes: [ 0x98, 0x01, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w8, 0:3, vgx4], { z12.h - z15.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x98, 0x01, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w8, 0:3, vgx4], { z12.h - z15.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x19, 0x40, 0xf9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w10, 4:7, vgx4], { z0.h - z3.h }, { z24.h - z27.h }"
+
+  -
+    input:
+      bytes: [ 0x19, 0x40, 0xf9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w10, 4:7, vgx4], { z0.h - z3.h }, { z24.h - z27.h }"
+
+  -
+    input:
+      bytes: [ 0x99, 0x02, 0xfd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w8, 4:7, vgx4], { z20.h - z23.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x99, 0x02, 0xfd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w8, 4:7, vgx4], { z20.h - z23.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x18, 0x61, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w11, 0:3, vgx4], { z8.h - z11.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x18, 0x61, 0xe1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w11, 0:3, vgx4], { z8.h - z11.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x99, 0x21, 0xe9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w9, 4:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }"
+
+  -
+    input:
+      bytes: [ 0x99, 0x21, 0xe9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsll za.d[w9, 4:7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }"
diff --git a/tests/MC/AArch64/SME2/umopa.s.yaml b/tests/MC/AArch64/SME2/umopa.s.yaml
new file mode 100644
index 000000000..6a8ebc0f6
--- /dev/null
+++ b/tests/MC/AArch64/SME2/umopa.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x08, 0x00, 0x80, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umopa za0.s, p0/m, p0/m, z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x49, 0x55, 0x95, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umopa za1.s, p5/m, p2/m, z10.h, z21.h"
+
+  -
+    input:
+      bytes: [ 0xab, 0xed, 0x88, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umopa za3.s, p3/m, p7/m, z13.h, z8.h"
+
+  -
+    input:
+      bytes: [ 0xeb, 0xff, 0x9f, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umopa za3.s, p7/m, p7/m, z31.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x29, 0x0e, 0x90, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umopa za1.s, p3/m, p0/m, z17.h, z16.h"
+
+  -
+    input:
+      bytes: [ 0x29, 0x84, 0x9e, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umopa za1.s, p1/m, p4/m, z1.h, z30.h"
+
+  -
+    input:
+      bytes: [ 0x68, 0x56, 0x94, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umopa za0.s, p5/m, p2/m, z19.h, z20.h"
+
+  -
+    input:
+      bytes: [ 0x88, 0x19, 0x82, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umopa za0.s, p6/m, p0/m, z12.h, z2.h"
+
+  -
+    input:
+      bytes: [ 0x29, 0xc8, 0x9a, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umopa za1.s, p2/m, p6/m, z1.h, z26.h"
+
+  -
+    input:
+      bytes: [ 0xc9, 0x0a, 0x9e, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umopa za1.s, p2/m, p0/m, z22.h, z30.h"
+
+  -
+    input:
+      bytes: [ 0x2a, 0xf5, 0x81, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umopa za2.s, p5/m, p7/m, z9.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0x8b, 0xa9, 0x8b, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umopa za3.s, p2/m, p5/m, z12.h, z11.h"
diff --git a/tests/MC/AArch64/SME2/umops.s.yaml b/tests/MC/AArch64/SME2/umops.s.yaml
new file mode 100644
index 000000000..52dad4e1e
--- /dev/null
+++ b/tests/MC/AArch64/SME2/umops.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x18, 0x00, 0x80, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umops za0.s, p0/m, p0/m, z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x59, 0x55, 0x95, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umops za1.s, p5/m, p2/m, z10.h, z21.h"
+
+  -
+    input:
+      bytes: [ 0xbb, 0xed, 0x88, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umops za3.s, p3/m, p7/m, z13.h, z8.h"
+
+  -
+    input:
+      bytes: [ 0xfb, 0xff, 0x9f, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umops za3.s, p7/m, p7/m, z31.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x39, 0x0e, 0x90, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umops za1.s, p3/m, p0/m, z17.h, z16.h"
+
+  -
+    input:
+      bytes: [ 0x39, 0x84, 0x9e, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umops za1.s, p1/m, p4/m, z1.h, z30.h"
+
+  -
+    input:
+      bytes: [ 0x78, 0x56, 0x94, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umops za0.s, p5/m, p2/m, z19.h, z20.h"
+
+  -
+    input:
+      bytes: [ 0x98, 0x19, 0x82, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umops za0.s, p6/m, p0/m, z12.h, z2.h"
+
+  -
+    input:
+      bytes: [ 0x39, 0xc8, 0x9a, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umops za1.s, p2/m, p6/m, z1.h, z26.h"
+
+  -
+    input:
+      bytes: [ 0xd9, 0x0a, 0x9e, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umops za1.s, p2/m, p0/m, z22.h, z30.h"
+
+  -
+    input:
+      bytes: [ 0x3a, 0xf5, 0x81, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umops za2.s, p5/m, p7/m, z9.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0x9b, 0xa9, 0x8b, 0xa1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umops za3.s, p2/m, p5/m, z12.h, z11.h"
diff --git a/tests/MC/AArch64/SME2/uqcvt.s.yaml b/tests/MC/AArch64/SME2/uqcvt.s.yaml
new file mode 100644
index 000000000..ba22e4a7f
--- /dev/null
+++ b/tests/MC/AArch64/SME2/uqcvt.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0xe0, 0x23, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqcvt z0.h, { z0.s, z1.s }"
+
+  -
+    input:
+      bytes: [ 0x75, 0xe1, 0x23, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqcvt z21.h, { z10.s, z11.s }"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xe1, 0x23, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqcvt z23.h, { z12.s, z13.s }"
+
+  -
+    input:
+      bytes: [ 0xff, 0xe3, 0x23, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqcvt z31.h, { z30.s, z31.s }"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe0, 0x33, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqcvt z0.b, { z0.s - z3.s }"
+
+  -
+    input:
+      bytes: [ 0x35, 0xe1, 0x33, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqcvt z21.b, { z8.s - z11.s }"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xe1, 0x33, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqcvt z23.b, { z12.s - z15.s }"
+
+  -
+    input:
+      bytes: [ 0xbf, 0xe3, 0x33, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqcvt z31.b, { z28.s - z31.s }"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe0, 0xb3, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqcvt z0.h, { z0.d - z3.d }"
+
+  -
+    input:
+      bytes: [ 0x35, 0xe1, 0xb3, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqcvt z21.h, { z8.d - z11.d }"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xe1, 0xb3, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqcvt z23.h, { z12.d - z15.d }"
+
+  -
+    input:
+      bytes: [ 0xbf, 0xe3, 0xb3, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqcvt z31.h, { z28.d - z31.d }"
diff --git a/tests/MC/AArch64/SME2/uqcvtn.s.yaml b/tests/MC/AArch64/SME2/uqcvtn.s.yaml
new file mode 100644
index 000000000..528d74e1b
--- /dev/null
+++ b/tests/MC/AArch64/SME2/uqcvtn.s.yaml
@@ -0,0 +1,80 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x60, 0xe0, 0x33, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqcvtn z0.b, { z0.s - z3.s }"
+
+  -
+    input:
+      bytes: [ 0x75, 0xe1, 0x33, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqcvtn z21.b, { z8.s - z11.s }"
+
+  -
+    input:
+      bytes: [ 0xf7, 0xe1, 0x33, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqcvtn z23.b, { z12.s - z15.s }"
+
+  -
+    input:
+      bytes: [ 0xff, 0xe3, 0x33, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqcvtn z31.b, { z28.s - z31.s }"
+
+  -
+    input:
+      bytes: [ 0x60, 0xe0, 0xb3, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqcvtn z0.h, { z0.d - z3.d }"
+
+  -
+    input:
+      bytes: [ 0x75, 0xe1, 0xb3, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqcvtn z21.h, { z8.d - z11.d }"
+
+  -
+    input:
+      bytes: [ 0xf7, 0xe1, 0xb3, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqcvtn z23.h, { z12.d - z15.d }"
+
+  -
+    input:
+      bytes: [ 0xff, 0xe3, 0xb3, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqcvtn z31.h, { z28.d - z31.d }"
diff --git a/tests/MC/AArch64/SME2/uqrshr.s.yaml b/tests/MC/AArch64/SME2/uqrshr.s.yaml
new file mode 100644
index 000000000..3a85d8fcb
--- /dev/null
+++ b/tests/MC/AArch64/SME2/uqrshr.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0xd4, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqrshr z0.h, { z0.s, z1.s }, #16"
+
+  -
+    input:
+      bytes: [ 0x75, 0xd5, 0xe5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqrshr z21.h, { z10.s, z11.s }, #11"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xd5, 0xe8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqrshr z23.h, { z12.s, z13.s }, #8"
+
+  -
+    input:
+      bytes: [ 0xff, 0xd7, 0xef, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqrshr z31.h, { z30.s, z31.s }, #1"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd8, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqrshr z0.b, { z0.s - z3.s }, #32"
+
+  -
+    input:
+      bytes: [ 0x35, 0xd9, 0x75, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqrshr z21.b, { z8.s - z11.s }, #11"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xd9, 0x68, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqrshr z23.b, { z12.s - z15.s }, #24"
+
+  -
+    input:
+      bytes: [ 0xbf, 0xdb, 0x7f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqrshr z31.b, { z28.s - z31.s }, #1"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd8, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqrshr z0.h, { z0.d - z3.d }, #64"
+
+  -
+    input:
+      bytes: [ 0x35, 0xd9, 0xf5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqrshr z21.h, { z8.d - z11.d }, #11"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xd9, 0xe8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqrshr z23.h, { z12.d - z15.d }, #24"
+
+  -
+    input:
+      bytes: [ 0xbf, 0xdb, 0xff, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqrshr z31.h, { z28.d - z31.d }, #1"
diff --git a/tests/MC/AArch64/SME2/uqrshrn.s.yaml b/tests/MC/AArch64/SME2/uqrshrn.s.yaml
new file mode 100644
index 000000000..67b5e5c29
--- /dev/null
+++ b/tests/MC/AArch64/SME2/uqrshrn.s.yaml
@@ -0,0 +1,80 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0xdc, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqrshrn z0.b, { z0.s - z3.s }, #32"
+
+  -
+    input:
+      bytes: [ 0x35, 0xdd, 0x75, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqrshrn z21.b, { z8.s - z11.s }, #11"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xdd, 0x68, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqrshrn z23.b, { z12.s - z15.s }, #24"
+
+  -
+    input:
+      bytes: [ 0xbf, 0xdf, 0x7f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqrshrn z31.b, { z28.s - z31.s }, #1"
+
+  -
+    input:
+      bytes: [ 0x20, 0xdc, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqrshrn z0.h, { z0.d - z3.d }, #64"
+
+  -
+    input:
+      bytes: [ 0x35, 0xdd, 0xf5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqrshrn z21.h, { z8.d - z11.d }, #11"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xdd, 0xe8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqrshrn z23.h, { z12.d - z15.d }, #24"
+
+  -
+    input:
+      bytes: [ 0xbf, 0xdf, 0xff, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqrshrn z31.h, { z28.d - z31.d }, #1"
diff --git a/tests/MC/AArch64/SME2/urshl.s.yaml b/tests/MC/AArch64/SME2/urshl.s.yaml
new file mode 100644
index 000000000..b5396e983
--- /dev/null
+++ b/tests/MC/AArch64/SME2/urshl.s.yaml
@@ -0,0 +1,640 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x21, 0xa2, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshl { z0.h, z1.h }, { z0.h, z1.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x35, 0xa2, 0x65, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshl { z20.h, z21.h }, { z20.h, z21.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0x37, 0xa2, 0x68, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshl { z22.h, z23.h }, { z22.h, z23.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0x3f, 0xa2, 0x6f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshl { z30.h, z31.h }, { z30.h, z31.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0x21, 0xb2, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshl { z0.h, z1.h }, { z0.h, z1.h }, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x35, 0xb2, 0x74, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshl { z20.h, z21.h }, { z20.h, z21.h }, { z20.h, z21.h }"
+
+  -
+    input:
+      bytes: [ 0x37, 0xb2, 0x68, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshl { z22.h, z23.h }, { z22.h, z23.h }, { z8.h, z9.h }"
+
+  -
+    input:
+      bytes: [ 0x3f, 0xb2, 0x7e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshl { z30.h, z31.h }, { z30.h, z31.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x21, 0xa2, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshl { z0.s, z1.s }, { z0.s, z1.s }, z0.s"
+
+  -
+    input:
+      bytes: [ 0x35, 0xa2, 0xa5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshl { z20.s, z21.s }, { z20.s, z21.s }, z5.s"
+
+  -
+    input:
+      bytes: [ 0x37, 0xa2, 0xa8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshl { z22.s, z23.s }, { z22.s, z23.s }, z8.s"
+
+  -
+    input:
+      bytes: [ 0x3f, 0xa2, 0xaf, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshl { z30.s, z31.s }, { z30.s, z31.s }, z15.s"
+
+  -
+    input:
+      bytes: [ 0x21, 0xb2, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshl { z0.s, z1.s }, { z0.s, z1.s }, { z0.s, z1.s }"
+
+  -
+    input:
+      bytes: [ 0x35, 0xb2, 0xb4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshl { z20.s, z21.s }, { z20.s, z21.s }, { z20.s, z21.s }"
+
+  -
+    input:
+      bytes: [ 0x37, 0xb2, 0xa8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshl { z22.s, z23.s }, { z22.s, z23.s }, { z8.s, z9.s }"
+
+  -
+    input:
+      bytes: [ 0x3f, 0xb2, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshl { z30.s, z31.s }, { z30.s, z31.s }, { z30.s, z31.s }"
+
+  -
+    input:
+      bytes: [ 0x21, 0xa2, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshl { z0.d, z1.d }, { z0.d, z1.d }, z0.d"
+
+  -
+    input:
+      bytes: [ 0x35, 0xa2, 0xe5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshl { z20.d, z21.d }, { z20.d, z21.d }, z5.d"
+
+  -
+    input:
+      bytes: [ 0x37, 0xa2, 0xe8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshl { z22.d, z23.d }, { z22.d, z23.d }, z8.d"
+
+  -
+    input:
+      bytes: [ 0x3f, 0xa2, 0xef, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshl { z30.d, z31.d }, { z30.d, z31.d }, z15.d"
+
+  -
+    input:
+      bytes: [ 0x21, 0xb2, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshl { z0.d, z1.d }, { z0.d, z1.d }, { z0.d, z1.d }"
+
+  -
+    input:
+      bytes: [ 0x35, 0xb2, 0xf4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshl { z20.d, z21.d }, { z20.d, z21.d }, { z20.d, z21.d }"
+
+  -
+    input:
+      bytes: [ 0x37, 0xb2, 0xe8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshl { z22.d, z23.d }, { z22.d, z23.d }, { z8.d, z9.d }"
+
+  -
+    input:
+      bytes: [ 0x3f, 0xb2, 0xfe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshl { z30.d, z31.d }, { z30.d, z31.d }, { z30.d, z31.d }"
+
+  -
+    input:
+      bytes: [ 0x21, 0xa2, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshl { z0.b, z1.b }, { z0.b, z1.b }, z0.b"
+
+  -
+    input:
+      bytes: [ 0x35, 0xa2, 0x25, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshl { z20.b, z21.b }, { z20.b, z21.b }, z5.b"
+
+  -
+    input:
+      bytes: [ 0x37, 0xa2, 0x28, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshl { z22.b, z23.b }, { z22.b, z23.b }, z8.b"
+
+  -
+    input:
+      bytes: [ 0x3f, 0xa2, 0x2f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshl { z30.b, z31.b }, { z30.b, z31.b }, z15.b"
+
+  -
+    input:
+      bytes: [ 0x21, 0xb2, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshl { z0.b, z1.b }, { z0.b, z1.b }, { z0.b, z1.b }"
+
+  -
+    input:
+      bytes: [ 0x35, 0xb2, 0x34, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshl { z20.b, z21.b }, { z20.b, z21.b }, { z20.b, z21.b }"
+
+  -
+    input:
+      bytes: [ 0x37, 0xb2, 0x28, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshl { z22.b, z23.b }, { z22.b, z23.b }, { z8.b, z9.b }"
+
+  -
+    input:
+      bytes: [ 0x3f, 0xb2, 0x3e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshl { z30.b, z31.b }, { z30.b, z31.b }, { z30.b, z31.b }"
+
+  -
+    input:
+      bytes: [ 0x21, 0xaa, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshl { z0.h - z3.h }, { z0.h - z3.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x35, 0xaa, 0x65, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshl { z20.h - z23.h }, { z20.h - z23.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0x35, 0xaa, 0x68, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshl { z20.h - z23.h }, { z20.h - z23.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0x3d, 0xaa, 0x6f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshl { z28.h - z31.h }, { z28.h - z31.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0x21, 0xba, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshl { z0.h - z3.h }, { z0.h - z3.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x35, 0xba, 0x74, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshl { z20.h - z23.h }, { z20.h - z23.h }, { z20.h - z23.h }"
+
+  -
+    input:
+      bytes: [ 0x35, 0xba, 0x68, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshl { z20.h - z23.h }, { z20.h - z23.h }, { z8.h - z11.h }"
+
+  -
+    input:
+      bytes: [ 0x3d, 0xba, 0x7c, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshl { z28.h - z31.h }, { z28.h - z31.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x21, 0xaa, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshl { z0.s - z3.s }, { z0.s - z3.s }, z0.s"
+
+  -
+    input:
+      bytes: [ 0x35, 0xaa, 0xa5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshl { z20.s - z23.s }, { z20.s - z23.s }, z5.s"
+
+  -
+    input:
+      bytes: [ 0x35, 0xaa, 0xa8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshl { z20.s - z23.s }, { z20.s - z23.s }, z8.s"
+
+  -
+    input:
+      bytes: [ 0x3d, 0xaa, 0xaf, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshl { z28.s - z31.s }, { z28.s - z31.s }, z15.s"
+
+  -
+    input:
+      bytes: [ 0x21, 0xba, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshl { z0.s - z3.s }, { z0.s - z3.s }, { z0.s - z3.s }"
+
+  -
+    input:
+      bytes: [ 0x35, 0xba, 0xb4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshl { z20.s - z23.s }, { z20.s - z23.s }, { z20.s - z23.s }"
+
+  -
+    input:
+      bytes: [ 0x35, 0xba, 0xa8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshl { z20.s - z23.s }, { z20.s - z23.s }, { z8.s - z11.s }"
+
+  -
+    input:
+      bytes: [ 0x3d, 0xba, 0xbc, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshl { z28.s - z31.s }, { z28.s - z31.s }, { z28.s - z31.s }"
+
+  -
+    input:
+      bytes: [ 0x21, 0xaa, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshl { z0.d - z3.d }, { z0.d - z3.d }, z0.d"
+
+  -
+    input:
+      bytes: [ 0x35, 0xaa, 0xe5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshl { z20.d - z23.d }, { z20.d - z23.d }, z5.d"
+
+  -
+    input:
+      bytes: [ 0x35, 0xaa, 0xe8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshl { z20.d - z23.d }, { z20.d - z23.d }, z8.d"
+
+  -
+    input:
+      bytes: [ 0x3d, 0xaa, 0xef, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshl { z28.d - z31.d }, { z28.d - z31.d }, z15.d"
+
+  -
+    input:
+      bytes: [ 0x21, 0xba, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshl { z0.d - z3.d }, { z0.d - z3.d }, { z0.d - z3.d }"
+
+  -
+    input:
+      bytes: [ 0x35, 0xba, 0xf4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshl { z20.d - z23.d }, { z20.d - z23.d }, { z20.d - z23.d }"
+
+  -
+    input:
+      bytes: [ 0x35, 0xba, 0xe8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshl { z20.d - z23.d }, { z20.d - z23.d }, { z8.d - z11.d }"
+
+  -
+    input:
+      bytes: [ 0x3d, 0xba, 0xfc, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshl { z28.d - z31.d }, { z28.d - z31.d }, { z28.d - z31.d }"
+
+  -
+    input:
+      bytes: [ 0x21, 0xaa, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshl { z0.b - z3.b }, { z0.b - z3.b }, z0.b"
+
+  -
+    input:
+      bytes: [ 0x35, 0xaa, 0x25, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshl { z20.b - z23.b }, { z20.b - z23.b }, z5.b"
+
+  -
+    input:
+      bytes: [ 0x35, 0xaa, 0x28, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshl { z20.b - z23.b }, { z20.b - z23.b }, z8.b"
+
+  -
+    input:
+      bytes: [ 0x3d, 0xaa, 0x2f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshl { z28.b - z31.b }, { z28.b - z31.b }, z15.b"
+
+  -
+    input:
+      bytes: [ 0x21, 0xba, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshl { z0.b - z3.b }, { z0.b - z3.b }, { z0.b - z3.b }"
+
+  -
+    input:
+      bytes: [ 0x35, 0xba, 0x34, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshl { z20.b - z23.b }, { z20.b - z23.b }, { z20.b - z23.b }"
+
+  -
+    input:
+      bytes: [ 0x35, 0xba, 0x28, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshl { z20.b - z23.b }, { z20.b - z23.b }, { z8.b - z11.b }"
+
+  -
+    input:
+      bytes: [ 0x3d, 0xba, 0x3c, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshl { z28.b - z31.b }, { z28.b - z31.b }, { z28.b - z31.b }"
diff --git a/tests/MC/AArch64/SME2/usdot.s.yaml b/tests/MC/AArch64/SME2/usdot.s.yaml
new file mode 100644
index 000000000..67fd33e11
--- /dev/null
+++ b/tests/MC/AArch64/SME2/usdot.s.yaml
@@ -0,0 +1,1440 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x08, 0x14, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w8, 0, vgx2], { z0.b, z1.b }, z0.b"
+
+  -
+    input:
+      bytes: [ 0x08, 0x14, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w8, 0, vgx2], { z0.b, z1.b }, z0.b"
+
+  -
+    input:
+      bytes: [ 0x4d, 0x55, 0x25, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w10, 5, vgx2], { z10.b, z11.b }, z5.b"
+
+  -
+    input:
+      bytes: [ 0x4d, 0x55, 0x25, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w10, 5, vgx2], { z10.b, z11.b }, z5.b"
+
+  -
+    input:
+      bytes: [ 0xaf, 0x75, 0x28, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w11, 7, vgx2], { z13.b, z14.b }, z8.b"
+
+  -
+    input:
+      bytes: [ 0xaf, 0x75, 0x28, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w11, 7, vgx2], { z13.b, z14.b }, z8.b"
+
+  -
+    input:
+      bytes: [ 0xef, 0x77, 0x2f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w11, 7, vgx2], { z31.b, z0.b }, z15.b"
+
+  -
+    input:
+      bytes: [ 0xef, 0x77, 0x2f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w11, 7, vgx2], { z31.b, z0.b }, z15.b"
+
+  -
+    input:
+      bytes: [ 0x2d, 0x16, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w8, 5, vgx2], { z17.b, z18.b }, z0.b"
+
+  -
+    input:
+      bytes: [ 0x2d, 0x16, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w8, 5, vgx2], { z17.b, z18.b }, z0.b"
+
+  -
+    input:
+      bytes: [ 0x29, 0x14, 0x2e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w8, 1, vgx2], { z1.b, z2.b }, z14.b"
+
+  -
+    input:
+      bytes: [ 0x29, 0x14, 0x2e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w8, 1, vgx2], { z1.b, z2.b }, z14.b"
+
+  -
+    input:
+      bytes: [ 0x68, 0x56, 0x24, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w10, 0, vgx2], { z19.b, z20.b }, z4.b"
+
+  -
+    input:
+      bytes: [ 0x68, 0x56, 0x24, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w10, 0, vgx2], { z19.b, z20.b }, z4.b"
+
+  -
+    input:
+      bytes: [ 0x88, 0x15, 0x22, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w8, 0, vgx2], { z12.b, z13.b }, z2.b"
+
+  -
+    input:
+      bytes: [ 0x88, 0x15, 0x22, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w8, 0, vgx2], { z12.b, z13.b }, z2.b"
+
+  -
+    input:
+      bytes: [ 0x29, 0x54, 0x2a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w10, 1, vgx2], { z1.b, z2.b }, z10.b"
+
+  -
+    input:
+      bytes: [ 0x29, 0x54, 0x2a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w10, 1, vgx2], { z1.b, z2.b }, z10.b"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x16, 0x2e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w8, 5, vgx2], { z22.b, z23.b }, z14.b"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x16, 0x2e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w8, 5, vgx2], { z22.b, z23.b }, z14.b"
+
+  -
+    input:
+      bytes: [ 0x2a, 0x75, 0x21, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w11, 2, vgx2], { z9.b, z10.b }, z1.b"
+
+  -
+    input:
+      bytes: [ 0x2a, 0x75, 0x21, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w11, 2, vgx2], { z9.b, z10.b }, z1.b"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x35, 0x2b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w9, 7, vgx2], { z12.b, z13.b }, z11.b"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x35, 0x2b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w9, 7, vgx2], { z12.b, z13.b }, z11.b"
+
+  -
+    input:
+      bytes: [ 0x28, 0x10, 0x50, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w8, 0, vgx2], { z0.b, z1.b }, z0.b[0]"
+
+  -
+    input:
+      bytes: [ 0x28, 0x10, 0x50, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w8, 0, vgx2], { z0.b, z1.b }, z0.b[0]"
+
+  -
+    input:
+      bytes: [ 0x6d, 0x55, 0x55, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w10, 5, vgx2], { z10.b, z11.b }, z5.b[1]"
+
+  -
+    input:
+      bytes: [ 0x6d, 0x55, 0x55, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w10, 5, vgx2], { z10.b, z11.b }, z5.b[1]"
+
+  -
+    input:
+      bytes: [ 0xaf, 0x7d, 0x58, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w11, 7, vgx2], { z12.b, z13.b }, z8.b[3]"
+
+  -
+    input:
+      bytes: [ 0xaf, 0x7d, 0x58, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w11, 7, vgx2], { z12.b, z13.b }, z8.b[3]"
+
+  -
+    input:
+      bytes: [ 0xef, 0x7f, 0x5f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w11, 7, vgx2], { z30.b, z31.b }, z15.b[3]"
+
+  -
+    input:
+      bytes: [ 0xef, 0x7f, 0x5f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w11, 7, vgx2], { z30.b, z31.b }, z15.b[3]"
+
+  -
+    input:
+      bytes: [ 0x2d, 0x1e, 0x50, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w8, 5, vgx2], { z16.b, z17.b }, z0.b[3]"
+
+  -
+    input:
+      bytes: [ 0x2d, 0x1e, 0x50, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w8, 5, vgx2], { z16.b, z17.b }, z0.b[3]"
+
+  -
+    input:
+      bytes: [ 0x29, 0x14, 0x5e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w8, 1, vgx2], { z0.b, z1.b }, z14.b[1]"
+
+  -
+    input:
+      bytes: [ 0x29, 0x14, 0x5e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w8, 1, vgx2], { z0.b, z1.b }, z14.b[1]"
+
+  -
+    input:
+      bytes: [ 0x68, 0x56, 0x54, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w10, 0, vgx2], { z18.b, z19.b }, z4.b[1]"
+
+  -
+    input:
+      bytes: [ 0x68, 0x56, 0x54, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w10, 0, vgx2], { z18.b, z19.b }, z4.b[1]"
+
+  -
+    input:
+      bytes: [ 0xa8, 0x19, 0x52, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w8, 0, vgx2], { z12.b, z13.b }, z2.b[2]"
+
+  -
+    input:
+      bytes: [ 0xa8, 0x19, 0x52, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w8, 0, vgx2], { z12.b, z13.b }, z2.b[2]"
+
+  -
+    input:
+      bytes: [ 0x29, 0x58, 0x5a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w10, 1, vgx2], { z0.b, z1.b }, z10.b[2]"
+
+  -
+    input:
+      bytes: [ 0x29, 0x58, 0x5a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w10, 1, vgx2], { z0.b, z1.b }, z10.b[2]"
+
+  -
+    input:
+      bytes: [ 0xed, 0x1a, 0x5e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w8, 5, vgx2], { z22.b, z23.b }, z14.b[2]"
+
+  -
+    input:
+      bytes: [ 0xed, 0x1a, 0x5e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w8, 5, vgx2], { z22.b, z23.b }, z14.b[2]"
+
+  -
+    input:
+      bytes: [ 0x2a, 0x75, 0x51, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w11, 2, vgx2], { z8.b, z9.b }, z1.b[1]"
+
+  -
+    input:
+      bytes: [ 0x2a, 0x75, 0x51, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w11, 2, vgx2], { z8.b, z9.b }, z1.b[1]"
+
+  -
+    input:
+      bytes: [ 0xaf, 0x39, 0x5b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w9, 7, vgx2], { z12.b, z13.b }, z11.b[2]"
+
+  -
+    input:
+      bytes: [ 0xaf, 0x39, 0x5b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w9, 7, vgx2], { z12.b, z13.b }, z11.b[2]"
+
+  -
+    input:
+      bytes: [ 0x08, 0x14, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w8, 0, vgx2], { z0.b, z1.b }, { z0.b, z1.b }"
+
+  -
+    input:
+      bytes: [ 0x08, 0x14, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w8, 0, vgx2], { z0.b, z1.b }, { z0.b, z1.b }"
+
+  -
+    input:
+      bytes: [ 0x4d, 0x55, 0xb4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w10, 5, vgx2], { z10.b, z11.b }, { z20.b, z21.b }"
+
+  -
+    input:
+      bytes: [ 0x4d, 0x55, 0xb4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w10, 5, vgx2], { z10.b, z11.b }, { z20.b, z21.b }"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x75, 0xa8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w11, 7, vgx2], { z12.b, z13.b }, { z8.b, z9.b }"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x75, 0xa8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w11, 7, vgx2], { z12.b, z13.b }, { z8.b, z9.b }"
+
+  -
+    input:
+      bytes: [ 0xcf, 0x77, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w11, 7, vgx2], { z30.b, z31.b }, { z30.b, z31.b }"
+
+  -
+    input:
+      bytes: [ 0xcf, 0x77, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w11, 7, vgx2], { z30.b, z31.b }, { z30.b, z31.b }"
+
+  -
+    input:
+      bytes: [ 0x0d, 0x16, 0xb0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w8, 5, vgx2], { z16.b, z17.b }, { z16.b, z17.b }"
+
+  -
+    input:
+      bytes: [ 0x0d, 0x16, 0xb0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w8, 5, vgx2], { z16.b, z17.b }, { z16.b, z17.b }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x14, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w8, 1, vgx2], { z0.b, z1.b }, { z30.b, z31.b }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x14, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w8, 1, vgx2], { z0.b, z1.b }, { z30.b, z31.b }"
+
+  -
+    input:
+      bytes: [ 0x48, 0x56, 0xb4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w10, 0, vgx2], { z18.b, z19.b }, { z20.b, z21.b }"
+
+  -
+    input:
+      bytes: [ 0x48, 0x56, 0xb4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w10, 0, vgx2], { z18.b, z19.b }, { z20.b, z21.b }"
+
+  -
+    input:
+      bytes: [ 0x88, 0x15, 0xa2, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w8, 0, vgx2], { z12.b, z13.b }, { z2.b, z3.b }"
+
+  -
+    input:
+      bytes: [ 0x88, 0x15, 0xa2, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w8, 0, vgx2], { z12.b, z13.b }, { z2.b, z3.b }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x54, 0xba, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w10, 1, vgx2], { z0.b, z1.b }, { z26.b, z27.b }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x54, 0xba, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w10, 1, vgx2], { z0.b, z1.b }, { z26.b, z27.b }"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x16, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w8, 5, vgx2], { z22.b, z23.b }, { z30.b, z31.b }"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x16, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w8, 5, vgx2], { z22.b, z23.b }, { z30.b, z31.b }"
+
+  -
+    input:
+      bytes: [ 0x0a, 0x75, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w11, 2, vgx2], { z8.b, z9.b }, { z0.b, z1.b }"
+
+  -
+    input:
+      bytes: [ 0x0a, 0x75, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w11, 2, vgx2], { z8.b, z9.b }, { z0.b, z1.b }"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x35, 0xaa, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w9, 7, vgx2], { z12.b, z13.b }, { z10.b, z11.b }"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x35, 0xaa, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w9, 7, vgx2], { z12.b, z13.b }, { z10.b, z11.b }"
+
+  -
+    input:
+      bytes: [ 0x08, 0x14, 0x30, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w8, 0, vgx4], { z0.b - z3.b }, z0.b"
+
+  -
+    input:
+      bytes: [ 0x08, 0x14, 0x30, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w8, 0, vgx4], { z0.b - z3.b }, z0.b"
+
+  -
+    input:
+      bytes: [ 0x4d, 0x55, 0x35, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w10, 5, vgx4], { z10.b - z13.b }, z5.b"
+
+  -
+    input:
+      bytes: [ 0x4d, 0x55, 0x35, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w10, 5, vgx4], { z10.b - z13.b }, z5.b"
+
+  -
+    input:
+      bytes: [ 0xaf, 0x75, 0x38, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w11, 7, vgx4], { z13.b - z16.b }, z8.b"
+
+  -
+    input:
+      bytes: [ 0xaf, 0x75, 0x38, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w11, 7, vgx4], { z13.b - z16.b }, z8.b"
+
+  -
+    input:
+      bytes: [ 0xef, 0x77, 0x3f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w11, 7, vgx4], { z31.b, z0.b, z1.b, z2.b }, z15.b"
+
+  -
+    input:
+      bytes: [ 0xef, 0x77, 0x3f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w11, 7, vgx4], { z31.b, z0.b, z1.b, z2.b }, z15.b"
+
+  -
+    input:
+      bytes: [ 0x2d, 0x16, 0x30, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w8, 5, vgx4], { z17.b - z20.b }, z0.b"
+
+  -
+    input:
+      bytes: [ 0x2d, 0x16, 0x30, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w8, 5, vgx4], { z17.b - z20.b }, z0.b"
+
+  -
+    input:
+      bytes: [ 0x29, 0x14, 0x3e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w8, 1, vgx4], { z1.b - z4.b }, z14.b"
+
+  -
+    input:
+      bytes: [ 0x29, 0x14, 0x3e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w8, 1, vgx4], { z1.b - z4.b }, z14.b"
+
+  -
+    input:
+      bytes: [ 0x68, 0x56, 0x34, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w10, 0, vgx4], { z19.b - z22.b }, z4.b"
+
+  -
+    input:
+      bytes: [ 0x68, 0x56, 0x34, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w10, 0, vgx4], { z19.b - z22.b }, z4.b"
+
+  -
+    input:
+      bytes: [ 0x88, 0x15, 0x32, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w8, 0, vgx4], { z12.b - z15.b }, z2.b"
+
+  -
+    input:
+      bytes: [ 0x88, 0x15, 0x32, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w8, 0, vgx4], { z12.b - z15.b }, z2.b"
+
+  -
+    input:
+      bytes: [ 0x29, 0x54, 0x3a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w10, 1, vgx4], { z1.b - z4.b }, z10.b"
+
+  -
+    input:
+      bytes: [ 0x29, 0x54, 0x3a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w10, 1, vgx4], { z1.b - z4.b }, z10.b"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x16, 0x3e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w8, 5, vgx4], { z22.b - z25.b }, z14.b"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x16, 0x3e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w8, 5, vgx4], { z22.b - z25.b }, z14.b"
+
+  -
+    input:
+      bytes: [ 0x2a, 0x75, 0x31, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w11, 2, vgx4], { z9.b - z12.b }, z1.b"
+
+  -
+    input:
+      bytes: [ 0x2a, 0x75, 0x31, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w11, 2, vgx4], { z9.b - z12.b }, z1.b"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x35, 0x3b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w9, 7, vgx4], { z12.b - z15.b }, z11.b"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x35, 0x3b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w9, 7, vgx4], { z12.b - z15.b }, z11.b"
+
+  -
+    input:
+      bytes: [ 0x28, 0x90, 0x50, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w8, 0, vgx4], { z0.b - z3.b }, z0.b[0]"
+
+  -
+    input:
+      bytes: [ 0x28, 0x90, 0x50, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w8, 0, vgx4], { z0.b - z3.b }, z0.b[0]"
+
+  -
+    input:
+      bytes: [ 0x2d, 0xd5, 0x55, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w10, 5, vgx4], { z8.b - z11.b }, z5.b[1]"
+
+  -
+    input:
+      bytes: [ 0x2d, 0xd5, 0x55, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w10, 5, vgx4], { z8.b - z11.b }, z5.b[1]"
+
+  -
+    input:
+      bytes: [ 0xaf, 0xfd, 0x58, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w11, 7, vgx4], { z12.b - z15.b }, z8.b[3]"
+
+  -
+    input:
+      bytes: [ 0xaf, 0xfd, 0x58, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w11, 7, vgx4], { z12.b - z15.b }, z8.b[3]"
+
+  -
+    input:
+      bytes: [ 0xaf, 0xff, 0x5f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w11, 7, vgx4], { z28.b - z31.b }, z15.b[3]"
+
+  -
+    input:
+      bytes: [ 0xaf, 0xff, 0x5f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w11, 7, vgx4], { z28.b - z31.b }, z15.b[3]"
+
+  -
+    input:
+      bytes: [ 0x2d, 0x9e, 0x50, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w8, 5, vgx4], { z16.b - z19.b }, z0.b[3]"
+
+  -
+    input:
+      bytes: [ 0x2d, 0x9e, 0x50, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w8, 5, vgx4], { z16.b - z19.b }, z0.b[3]"
+
+  -
+    input:
+      bytes: [ 0x29, 0x94, 0x5e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w8, 1, vgx4], { z0.b - z3.b }, z14.b[1]"
+
+  -
+    input:
+      bytes: [ 0x29, 0x94, 0x5e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w8, 1, vgx4], { z0.b - z3.b }, z14.b[1]"
+
+  -
+    input:
+      bytes: [ 0x28, 0xd6, 0x54, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w10, 0, vgx4], { z16.b - z19.b }, z4.b[1]"
+
+  -
+    input:
+      bytes: [ 0x28, 0xd6, 0x54, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w10, 0, vgx4], { z16.b - z19.b }, z4.b[1]"
+
+  -
+    input:
+      bytes: [ 0xa8, 0x99, 0x52, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w8, 0, vgx4], { z12.b - z15.b }, z2.b[2]"
+
+  -
+    input:
+      bytes: [ 0xa8, 0x99, 0x52, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w8, 0, vgx4], { z12.b - z15.b }, z2.b[2]"
+
+  -
+    input:
+      bytes: [ 0x29, 0xd8, 0x5a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w10, 1, vgx4], { z0.b - z3.b }, z10.b[2]"
+
+  -
+    input:
+      bytes: [ 0x29, 0xd8, 0x5a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w10, 1, vgx4], { z0.b - z3.b }, z10.b[2]"
+
+  -
+    input:
+      bytes: [ 0xad, 0x9a, 0x5e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w8, 5, vgx4], { z20.b - z23.b }, z14.b[2]"
+
+  -
+    input:
+      bytes: [ 0xad, 0x9a, 0x5e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w8, 5, vgx4], { z20.b - z23.b }, z14.b[2]"
+
+  -
+    input:
+      bytes: [ 0x2a, 0xf5, 0x51, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w11, 2, vgx4], { z8.b - z11.b }, z1.b[1]"
+
+  -
+    input:
+      bytes: [ 0x2a, 0xf5, 0x51, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w11, 2, vgx4], { z8.b - z11.b }, z1.b[1]"
+
+  -
+    input:
+      bytes: [ 0xaf, 0xb9, 0x5b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w9, 7, vgx4], { z12.b - z15.b }, z11.b[2]"
+
+  -
+    input:
+      bytes: [ 0xaf, 0xb9, 0x5b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w9, 7, vgx4], { z12.b - z15.b }, z11.b[2]"
+
+  -
+    input:
+      bytes: [ 0x08, 0x14, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w8, 0, vgx4], { z0.b - z3.b }, { z0.b - z3.b }"
+
+  -
+    input:
+      bytes: [ 0x08, 0x14, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w8, 0, vgx4], { z0.b - z3.b }, { z0.b - z3.b }"
+
+  -
+    input:
+      bytes: [ 0x0d, 0x55, 0xb5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w10, 5, vgx4], { z8.b - z11.b }, { z20.b - z23.b }"
+
+  -
+    input:
+      bytes: [ 0x0d, 0x55, 0xb5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w10, 5, vgx4], { z8.b - z11.b }, { z20.b - z23.b }"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x75, 0xa9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w11, 7, vgx4], { z12.b - z15.b }, { z8.b - z11.b }"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x75, 0xa9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w11, 7, vgx4], { z12.b - z15.b }, { z8.b - z11.b }"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x77, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w11, 7, vgx4], { z28.b - z31.b }, { z28.b - z31.b }"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x77, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w11, 7, vgx4], { z28.b - z31.b }, { z28.b - z31.b }"
+
+  -
+    input:
+      bytes: [ 0x0d, 0x16, 0xb1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w8, 5, vgx4], { z16.b - z19.b }, { z16.b - z19.b }"
+
+  -
+    input:
+      bytes: [ 0x0d, 0x16, 0xb1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w8, 5, vgx4], { z16.b - z19.b }, { z16.b - z19.b }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x14, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w8, 1, vgx4], { z0.b - z3.b }, { z28.b - z31.b }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x14, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w8, 1, vgx4], { z0.b - z3.b }, { z28.b - z31.b }"
+
+  -
+    input:
+      bytes: [ 0x08, 0x56, 0xb5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w10, 0, vgx4], { z16.b - z19.b }, { z20.b - z23.b }"
+
+  -
+    input:
+      bytes: [ 0x08, 0x56, 0xb5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w10, 0, vgx4], { z16.b - z19.b }, { z20.b - z23.b }"
+
+  -
+    input:
+      bytes: [ 0x88, 0x15, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w8, 0, vgx4], { z12.b - z15.b }, { z0.b - z3.b }"
+
+  -
+    input:
+      bytes: [ 0x88, 0x15, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w8, 0, vgx4], { z12.b - z15.b }, { z0.b - z3.b }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x54, 0xb9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w10, 1, vgx4], { z0.b - z3.b }, { z24.b - z27.b }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x54, 0xb9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w10, 1, vgx4], { z0.b - z3.b }, { z24.b - z27.b }"
+
+  -
+    input:
+      bytes: [ 0x8d, 0x16, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w8, 5, vgx4], { z20.b - z23.b }, { z28.b - z31.b }"
+
+  -
+    input:
+      bytes: [ 0x8d, 0x16, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w8, 5, vgx4], { z20.b - z23.b }, { z28.b - z31.b }"
+
+  -
+    input:
+      bytes: [ 0x0a, 0x75, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w11, 2, vgx4], { z8.b - z11.b }, { z0.b - z3.b }"
+
+  -
+    input:
+      bytes: [ 0x0a, 0x75, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w11, 2, vgx4], { z8.b - z11.b }, { z0.b - z3.b }"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x35, 0xa9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w9, 7, vgx4], { z12.b - z15.b }, { z8.b - z11.b }"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x35, 0xa9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot za.s[w9, 7, vgx4], { z12.b - z15.b }, { z8.b - z11.b }"
diff --git a/tests/MC/AArch64/SME2/usmlall.s.yaml b/tests/MC/AArch64/SME2/usmlall.s.yaml
new file mode 100644
index 000000000..53a9109a0
--- /dev/null
+++ b/tests/MC/AArch64/SME2/usmlall.s.yaml
@@ -0,0 +1,1680 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x04, 0x04, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w8, 0:3], z0.b, z0.b"
+
+  -
+    input:
+      bytes: [ 0x45, 0x45, 0x25, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w10, 4:7], z10.b, z5.b"
+
+  -
+    input:
+      bytes: [ 0xa7, 0x65, 0x28, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w11, 12:15], z13.b, z8.b"
+
+  -
+    input:
+      bytes: [ 0xe7, 0x67, 0x2f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w11, 12:15], z31.b, z15.b"
+
+  -
+    input:
+      bytes: [ 0x25, 0x06, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w8, 4:7], z17.b, z0.b"
+
+  -
+    input:
+      bytes: [ 0x25, 0x04, 0x2e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w8, 4:7], z1.b, z14.b"
+
+  -
+    input:
+      bytes: [ 0x64, 0x46, 0x24, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w10, 0:3], z19.b, z4.b"
+
+  -
+    input:
+      bytes: [ 0x84, 0x05, 0x22, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w8, 0:3], z12.b, z2.b"
+
+  -
+    input:
+      bytes: [ 0x25, 0x44, 0x2a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w10, 4:7], z1.b, z10.b"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x06, 0x2e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w8, 4:7], z22.b, z14.b"
+
+  -
+    input:
+      bytes: [ 0x26, 0x65, 0x21, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w11, 8:11], z9.b, z1.b"
+
+  -
+    input:
+      bytes: [ 0x87, 0x25, 0x2b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w9, 12:15], z12.b, z11.b"
+
+  -
+    input:
+      bytes: [ 0x04, 0x00, 0x00, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w8, 0:3], z0.b, z0.b[0]"
+
+  -
+    input:
+      bytes: [ 0x45, 0x55, 0x05, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w10, 4:7], z10.b, z5.b[5]"
+
+  -
+    input:
+      bytes: [ 0xa7, 0xed, 0x08, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w11, 12:15], z13.b, z8.b[11]"
+
+  -
+    input:
+      bytes: [ 0xe7, 0xff, 0x0f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w11, 12:15], z31.b, z15.b[15]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x0e, 0x00, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w8, 4:7], z17.b, z0.b[3]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x84, 0x0e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w8, 4:7], z1.b, z14.b[9]"
+
+  -
+    input:
+      bytes: [ 0x64, 0x56, 0x04, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w10, 0:3], z19.b, z4.b[5]"
+
+  -
+    input:
+      bytes: [ 0x84, 0x19, 0x02, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w8, 0:3], z12.b, z2.b[6]"
+
+  -
+    input:
+      bytes: [ 0x25, 0xc8, 0x0a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w10, 4:7], z1.b, z10.b[10]"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x0a, 0x0e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w8, 4:7], z22.b, z14.b[2]"
+
+  -
+    input:
+      bytes: [ 0x26, 0xf5, 0x01, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w11, 8:11], z9.b, z1.b[13]"
+
+  -
+    input:
+      bytes: [ 0x87, 0xa9, 0x0b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w9, 12:15], z12.b, z11.b[10]"
+
+  -
+    input:
+      bytes: [ 0x04, 0x00, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w8, 0:3,  vgx2], { z0.b, z1.b }, z0.b"
+
+  -
+    input:
+      bytes: [ 0x04, 0x00, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w8, 0:3,  vgx2], { z0.b, z1.b }, z0.b"
+
+  -
+    input:
+      bytes: [ 0x45, 0x41, 0x25, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w10, 4:7,  vgx2], { z10.b, z11.b }, z5.b"
+
+  -
+    input:
+      bytes: [ 0x45, 0x41, 0x25, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w10, 4:7,  vgx2], { z10.b, z11.b }, z5.b"
+
+  -
+    input:
+      bytes: [ 0xa5, 0x61, 0x28, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w11, 4:7,  vgx2], { z13.b, z14.b }, z8.b"
+
+  -
+    input:
+      bytes: [ 0xa5, 0x61, 0x28, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w11, 4:7,  vgx2], { z13.b, z14.b }, z8.b"
+
+  -
+    input:
+      bytes: [ 0xe5, 0x63, 0x2f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w11, 4:7,  vgx2], { z31.b, z0.b }, z15.b"
+
+  -
+    input:
+      bytes: [ 0xe5, 0x63, 0x2f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w11, 4:7,  vgx2], { z31.b, z0.b }, z15.b"
+
+  -
+    input:
+      bytes: [ 0x25, 0x02, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w8, 4:7,  vgx2], { z17.b, z18.b }, z0.b"
+
+  -
+    input:
+      bytes: [ 0x25, 0x02, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w8, 4:7,  vgx2], { z17.b, z18.b }, z0.b"
+
+  -
+    input:
+      bytes: [ 0x25, 0x00, 0x2e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w8, 4:7,  vgx2], { z1.b, z2.b }, z14.b"
+
+  -
+    input:
+      bytes: [ 0x25, 0x00, 0x2e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w8, 4:7,  vgx2], { z1.b, z2.b }, z14.b"
+
+  -
+    input:
+      bytes: [ 0x64, 0x42, 0x24, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w10, 0:3,  vgx2], { z19.b, z20.b }, z4.b"
+
+  -
+    input:
+      bytes: [ 0x64, 0x42, 0x24, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w10, 0:3,  vgx2], { z19.b, z20.b }, z4.b"
+
+  -
+    input:
+      bytes: [ 0x84, 0x01, 0x22, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w8, 0:3,  vgx2], { z12.b, z13.b }, z2.b"
+
+  -
+    input:
+      bytes: [ 0x84, 0x01, 0x22, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w8, 0:3,  vgx2], { z12.b, z13.b }, z2.b"
+
+  -
+    input:
+      bytes: [ 0x25, 0x40, 0x2a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w10, 4:7,  vgx2], { z1.b, z2.b }, z10.b"
+
+  -
+    input:
+      bytes: [ 0x25, 0x40, 0x2a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w10, 4:7,  vgx2], { z1.b, z2.b }, z10.b"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x02, 0x2e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w8, 4:7,  vgx2], { z22.b, z23.b }, z14.b"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x02, 0x2e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w8, 4:7,  vgx2], { z22.b, z23.b }, z14.b"
+
+  -
+    input:
+      bytes: [ 0x24, 0x61, 0x21, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w11, 0:3,  vgx2], { z9.b, z10.b }, z1.b"
+
+  -
+    input:
+      bytes: [ 0x24, 0x61, 0x21, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w11, 0:3,  vgx2], { z9.b, z10.b }, z1.b"
+
+  -
+    input:
+      bytes: [ 0x85, 0x21, 0x2b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w9, 4:7,  vgx2], { z12.b, z13.b }, z11.b"
+
+  -
+    input:
+      bytes: [ 0x85, 0x21, 0x2b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w9, 4:7,  vgx2], { z12.b, z13.b }, z11.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x00, 0x10, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w8, 0:3, vgx2], { z0.b, z1.b }, z0.b[0]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x00, 0x10, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w8, 0:3, vgx2], { z0.b, z1.b }, z0.b[0]"
+
+  -
+    input:
+      bytes: [ 0x65, 0x45, 0x15, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w10, 4:7, vgx2], { z10.b, z11.b }, z5.b[6]"
+
+  -
+    input:
+      bytes: [ 0x65, 0x45, 0x15, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w10, 4:7, vgx2], { z10.b, z11.b }, z5.b[6]"
+
+  -
+    input:
+      bytes: [ 0xa7, 0x6d, 0x18, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w11, 4:7, vgx2], { z12.b, z13.b }, z8.b[15]"
+
+  -
+    input:
+      bytes: [ 0xa7, 0x6d, 0x18, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w11, 4:7, vgx2], { z12.b, z13.b }, z8.b[15]"
+
+  -
+    input:
+      bytes: [ 0xe7, 0x6f, 0x1f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w11, 4:7, vgx2], { z30.b, z31.b }, z15.b[15]"
+
+  -
+    input:
+      bytes: [ 0xe7, 0x6f, 0x1f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w11, 4:7, vgx2], { z30.b, z31.b }, z15.b[15]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x0e, 0x10, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w8, 4:7, vgx2], { z16.b, z17.b }, z0.b[14]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x0e, 0x10, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w8, 4:7, vgx2], { z16.b, z17.b }, z0.b[14]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x04, 0x1e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w8, 4:7, vgx2], { z0.b, z1.b }, z14.b[4]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x04, 0x1e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w8, 4:7, vgx2], { z0.b, z1.b }, z14.b[4]"
+
+  -
+    input:
+      bytes: [ 0x60, 0x46, 0x14, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w10, 0:3, vgx2], { z18.b, z19.b }, z4.b[4]"
+
+  -
+    input:
+      bytes: [ 0x60, 0x46, 0x14, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w10, 0:3, vgx2], { z18.b, z19.b }, z4.b[4]"
+
+  -
+    input:
+      bytes: [ 0xa0, 0x09, 0x12, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w8, 0:3, vgx2], { z12.b, z13.b }, z2.b[8]"
+
+  -
+    input:
+      bytes: [ 0xa0, 0x09, 0x12, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w8, 0:3, vgx2], { z12.b, z13.b }, z2.b[8]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x48, 0x1a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w10, 4:7, vgx2], { z0.b, z1.b }, z10.b[8]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x48, 0x1a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w10, 4:7, vgx2], { z0.b, z1.b }, z10.b[8]"
+
+  -
+    input:
+      bytes: [ 0xe5, 0x0a, 0x1e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w8, 4:7, vgx2], { z22.b, z23.b }, z14.b[10]"
+
+  -
+    input:
+      bytes: [ 0xe5, 0x0a, 0x1e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w8, 4:7, vgx2], { z22.b, z23.b }, z14.b[10]"
+
+  -
+    input:
+      bytes: [ 0x22, 0x65, 0x11, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w11, 0:3, vgx2], { z8.b, z9.b }, z1.b[5]"
+
+  -
+    input:
+      bytes: [ 0x22, 0x65, 0x11, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w11, 0:3, vgx2], { z8.b, z9.b }, z1.b[5]"
+
+  -
+    input:
+      bytes: [ 0xa7, 0x29, 0x1b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w9, 4:7, vgx2], { z12.b, z13.b }, z11.b[11]"
+
+  -
+    input:
+      bytes: [ 0xa7, 0x29, 0x1b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w9, 4:7, vgx2], { z12.b, z13.b }, z11.b[11]"
+
+  -
+    input:
+      bytes: [ 0x04, 0x00, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w8, 0:3, vgx2], { z0.b, z1.b }, { z0.b, z1.b }"
+
+  -
+    input:
+      bytes: [ 0x04, 0x00, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w8, 0:3, vgx2], { z0.b, z1.b }, { z0.b, z1.b }"
+
+  -
+    input:
+      bytes: [ 0x45, 0x41, 0xb4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w10, 4:7, vgx2], { z10.b, z11.b }, { z20.b, z21.b }"
+
+  -
+    input:
+      bytes: [ 0x45, 0x41, 0xb4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w10, 4:7, vgx2], { z10.b, z11.b }, { z20.b, z21.b }"
+
+  -
+    input:
+      bytes: [ 0x85, 0x61, 0xa8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w11, 4:7, vgx2], { z12.b, z13.b }, { z8.b, z9.b }"
+
+  -
+    input:
+      bytes: [ 0x85, 0x61, 0xa8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w11, 4:7, vgx2], { z12.b, z13.b }, { z8.b, z9.b }"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x63, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w11, 4:7, vgx2], { z30.b, z31.b }, { z30.b, z31.b }"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x63, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w11, 4:7, vgx2], { z30.b, z31.b }, { z30.b, z31.b }"
+
+  -
+    input:
+      bytes: [ 0x05, 0x02, 0xb0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w8, 4:7, vgx2], { z16.b, z17.b }, { z16.b, z17.b }"
+
+  -
+    input:
+      bytes: [ 0x05, 0x02, 0xb0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w8, 4:7, vgx2], { z16.b, z17.b }, { z16.b, z17.b }"
+
+  -
+    input:
+      bytes: [ 0x05, 0x00, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w8, 4:7, vgx2], { z0.b, z1.b }, { z30.b, z31.b }"
+
+  -
+    input:
+      bytes: [ 0x05, 0x00, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w8, 4:7, vgx2], { z0.b, z1.b }, { z30.b, z31.b }"
+
+  -
+    input:
+      bytes: [ 0x44, 0x42, 0xb4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w10, 0:3, vgx2], { z18.b, z19.b }, { z20.b, z21.b }"
+
+  -
+    input:
+      bytes: [ 0x44, 0x42, 0xb4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w10, 0:3, vgx2], { z18.b, z19.b }, { z20.b, z21.b }"
+
+  -
+    input:
+      bytes: [ 0x84, 0x01, 0xa2, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w8, 0:3, vgx2], { z12.b, z13.b }, { z2.b, z3.b }"
+
+  -
+    input:
+      bytes: [ 0x84, 0x01, 0xa2, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w8, 0:3, vgx2], { z12.b, z13.b }, { z2.b, z3.b }"
+
+  -
+    input:
+      bytes: [ 0x05, 0x40, 0xba, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w10, 4:7, vgx2], { z0.b, z1.b }, { z26.b, z27.b }"
+
+  -
+    input:
+      bytes: [ 0x05, 0x40, 0xba, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w10, 4:7, vgx2], { z0.b, z1.b }, { z26.b, z27.b }"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x02, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w8, 4:7, vgx2], { z22.b, z23.b }, { z30.b, z31.b }"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x02, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w8, 4:7, vgx2], { z22.b, z23.b }, { z30.b, z31.b }"
+
+  -
+    input:
+      bytes: [ 0x04, 0x61, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w11, 0:3, vgx2], { z8.b, z9.b }, { z0.b, z1.b }"
+
+  -
+    input:
+      bytes: [ 0x04, 0x61, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w11, 0:3, vgx2], { z8.b, z9.b }, { z0.b, z1.b }"
+
+  -
+    input:
+      bytes: [ 0x85, 0x21, 0xaa, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w9, 4:7, vgx2], { z12.b, z13.b }, { z10.b, z11.b }"
+
+  -
+    input:
+      bytes: [ 0x85, 0x21, 0xaa, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w9, 4:7, vgx2], { z12.b, z13.b }, { z10.b, z11.b }"
+
+  -
+    input:
+      bytes: [ 0x04, 0x00, 0x30, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w8, 0:3,  vgx4], { z0.b - z3.b }, z0.b"
+
+  -
+    input:
+      bytes: [ 0x04, 0x00, 0x30, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w8, 0:3,  vgx4], { z0.b - z3.b }, z0.b"
+
+  -
+    input:
+      bytes: [ 0x45, 0x41, 0x35, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w10, 4:7,  vgx4], { z10.b - z13.b }, z5.b"
+
+  -
+    input:
+      bytes: [ 0x45, 0x41, 0x35, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w10, 4:7,  vgx4], { z10.b - z13.b }, z5.b"
+
+  -
+    input:
+      bytes: [ 0xa5, 0x61, 0x38, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w11, 4:7,  vgx4], { z13.b - z16.b }, z8.b"
+
+  -
+    input:
+      bytes: [ 0xa5, 0x61, 0x38, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w11, 4:7,  vgx4], { z13.b - z16.b }, z8.b"
+
+  -
+    input:
+      bytes: [ 0xe5, 0x63, 0x3f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w11, 4:7,  vgx4], { z31.b, z0.b, z1.b, z2.b }, z15.b"
+
+  -
+    input:
+      bytes: [ 0xe5, 0x63, 0x3f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w11, 4:7,  vgx4], { z31.b, z0.b, z1.b, z2.b }, z15.b"
+
+  -
+    input:
+      bytes: [ 0x25, 0x02, 0x30, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w8, 4:7,  vgx4], { z17.b - z20.b }, z0.b"
+
+  -
+    input:
+      bytes: [ 0x25, 0x02, 0x30, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w8, 4:7,  vgx4], { z17.b - z20.b }, z0.b"
+
+  -
+    input:
+      bytes: [ 0x25, 0x00, 0x3e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w8, 4:7,  vgx4], { z1.b - z4.b }, z14.b"
+
+  -
+    input:
+      bytes: [ 0x25, 0x00, 0x3e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w8, 4:7,  vgx4], { z1.b - z4.b }, z14.b"
+
+  -
+    input:
+      bytes: [ 0x64, 0x42, 0x34, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w10, 0:3,  vgx4], { z19.b - z22.b }, z4.b"
+
+  -
+    input:
+      bytes: [ 0x64, 0x42, 0x34, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w10, 0:3,  vgx4], { z19.b - z22.b }, z4.b"
+
+  -
+    input:
+      bytes: [ 0x84, 0x01, 0x32, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w8, 0:3,  vgx4], { z12.b - z15.b }, z2.b"
+
+  -
+    input:
+      bytes: [ 0x84, 0x01, 0x32, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w8, 0:3,  vgx4], { z12.b - z15.b }, z2.b"
+
+  -
+    input:
+      bytes: [ 0x25, 0x40, 0x3a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w10, 4:7,  vgx4], { z1.b - z4.b }, z10.b"
+
+  -
+    input:
+      bytes: [ 0x25, 0x40, 0x3a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w10, 4:7,  vgx4], { z1.b - z4.b }, z10.b"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x02, 0x3e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w8, 4:7,  vgx4], { z22.b - z25.b }, z14.b"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x02, 0x3e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w8, 4:7,  vgx4], { z22.b - z25.b }, z14.b"
+
+  -
+    input:
+      bytes: [ 0x24, 0x61, 0x31, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w11, 0:3,  vgx4], { z9.b - z12.b }, z1.b"
+
+  -
+    input:
+      bytes: [ 0x24, 0x61, 0x31, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w11, 0:3,  vgx4], { z9.b - z12.b }, z1.b"
+
+  -
+    input:
+      bytes: [ 0x85, 0x21, 0x3b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w9, 4:7,  vgx4], { z12.b - z15.b }, z11.b"
+
+  -
+    input:
+      bytes: [ 0x85, 0x21, 0x3b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w9, 4:7,  vgx4], { z12.b - z15.b }, z11.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x10, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w8, 0:3, vgx4], { z0.b - z3.b }, z0.b[0]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x10, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w8, 0:3, vgx4], { z0.b - z3.b }, z0.b[0]"
+
+  -
+    input:
+      bytes: [ 0x25, 0xc5, 0x15, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w10, 4:7, vgx4], { z8.b - z11.b }, z5.b[6]"
+
+  -
+    input:
+      bytes: [ 0x25, 0xc5, 0x15, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w10, 4:7, vgx4], { z8.b - z11.b }, z5.b[6]"
+
+  -
+    input:
+      bytes: [ 0xa7, 0xed, 0x18, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w11, 4:7, vgx4], { z12.b - z15.b }, z8.b[15]"
+
+  -
+    input:
+      bytes: [ 0xa7, 0xed, 0x18, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w11, 4:7, vgx4], { z12.b - z15.b }, z8.b[15]"
+
+  -
+    input:
+      bytes: [ 0xa7, 0xef, 0x1f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w11, 4:7, vgx4], { z28.b - z31.b }, z15.b[15]"
+
+  -
+    input:
+      bytes: [ 0xa7, 0xef, 0x1f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w11, 4:7, vgx4], { z28.b - z31.b }, z15.b[15]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x8e, 0x10, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w8, 4:7, vgx4], { z16.b - z19.b }, z0.b[14]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x8e, 0x10, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w8, 4:7, vgx4], { z16.b - z19.b }, z0.b[14]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x84, 0x1e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w8, 4:7, vgx4], { z0.b - z3.b }, z14.b[4]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x84, 0x1e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w8, 4:7, vgx4], { z0.b - z3.b }, z14.b[4]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc6, 0x14, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w10, 0:3, vgx4], { z16.b - z19.b }, z4.b[4]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc6, 0x14, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w10, 0:3, vgx4], { z16.b - z19.b }, z4.b[4]"
+
+  -
+    input:
+      bytes: [ 0xa0, 0x89, 0x12, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w8, 0:3, vgx4], { z12.b - z15.b }, z2.b[8]"
+
+  -
+    input:
+      bytes: [ 0xa0, 0x89, 0x12, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w8, 0:3, vgx4], { z12.b - z15.b }, z2.b[8]"
+
+  -
+    input:
+      bytes: [ 0x21, 0xc8, 0x1a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w10, 4:7, vgx4], { z0.b - z3.b }, z10.b[8]"
+
+  -
+    input:
+      bytes: [ 0x21, 0xc8, 0x1a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w10, 4:7, vgx4], { z0.b - z3.b }, z10.b[8]"
+
+  -
+    input:
+      bytes: [ 0xa5, 0x8a, 0x1e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w8, 4:7, vgx4], { z20.b - z23.b }, z14.b[10]"
+
+  -
+    input:
+      bytes: [ 0xa5, 0x8a, 0x1e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w8, 4:7, vgx4], { z20.b - z23.b }, z14.b[10]"
+
+  -
+    input:
+      bytes: [ 0x22, 0xe5, 0x11, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w11, 0:3, vgx4], { z8.b - z11.b }, z1.b[5]"
+
+  -
+    input:
+      bytes: [ 0x22, 0xe5, 0x11, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w11, 0:3, vgx4], { z8.b - z11.b }, z1.b[5]"
+
+  -
+    input:
+      bytes: [ 0xa7, 0xa9, 0x1b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w9, 4:7, vgx4], { z12.b - z15.b }, z11.b[11]"
+
+  -
+    input:
+      bytes: [ 0xa7, 0xa9, 0x1b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w9, 4:7, vgx4], { z12.b - z15.b }, z11.b[11]"
+
+  -
+    input:
+      bytes: [ 0x04, 0x00, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w8, 0:3, vgx4], { z0.b - z3.b }, { z0.b - z3.b }"
+
+  -
+    input:
+      bytes: [ 0x04, 0x00, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w8, 0:3, vgx4], { z0.b - z3.b }, { z0.b - z3.b }"
+
+  -
+    input:
+      bytes: [ 0x05, 0x41, 0xb5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w10, 4:7, vgx4], { z8.b - z11.b }, { z20.b - z23.b }"
+
+  -
+    input:
+      bytes: [ 0x05, 0x41, 0xb5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w10, 4:7, vgx4], { z8.b - z11.b }, { z20.b - z23.b }"
+
+  -
+    input:
+      bytes: [ 0x85, 0x61, 0xa9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w11, 4:7, vgx4], { z12.b - z15.b }, { z8.b - z11.b }"
+
+  -
+    input:
+      bytes: [ 0x85, 0x61, 0xa9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w11, 4:7, vgx4], { z12.b - z15.b }, { z8.b - z11.b }"
+
+  -
+    input:
+      bytes: [ 0x85, 0x63, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w11, 4:7, vgx4], { z28.b - z31.b }, { z28.b - z31.b }"
+
+  -
+    input:
+      bytes: [ 0x85, 0x63, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w11, 4:7, vgx4], { z28.b - z31.b }, { z28.b - z31.b }"
+
+  -
+    input:
+      bytes: [ 0x05, 0x02, 0xb1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w8, 4:7, vgx4], { z16.b - z19.b }, { z16.b - z19.b }"
+
+  -
+    input:
+      bytes: [ 0x05, 0x02, 0xb1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w8, 4:7, vgx4], { z16.b - z19.b }, { z16.b - z19.b }"
+
+  -
+    input:
+      bytes: [ 0x05, 0x00, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w8, 4:7, vgx4], { z0.b - z3.b }, { z28.b - z31.b }"
+
+  -
+    input:
+      bytes: [ 0x05, 0x00, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w8, 4:7, vgx4], { z0.b - z3.b }, { z28.b - z31.b }"
+
+  -
+    input:
+      bytes: [ 0x04, 0x42, 0xb5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w10, 0:3, vgx4], { z16.b - z19.b }, { z20.b - z23.b }"
+
+  -
+    input:
+      bytes: [ 0x04, 0x42, 0xb5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w10, 0:3, vgx4], { z16.b - z19.b }, { z20.b - z23.b }"
+
+  -
+    input:
+      bytes: [ 0x84, 0x01, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w8, 0:3, vgx4], { z12.b - z15.b }, { z0.b - z3.b }"
+
+  -
+    input:
+      bytes: [ 0x84, 0x01, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w8, 0:3, vgx4], { z12.b - z15.b }, { z0.b - z3.b }"
+
+  -
+    input:
+      bytes: [ 0x05, 0x40, 0xb9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w10, 4:7, vgx4], { z0.b - z3.b }, { z24.b - z27.b }"
+
+  -
+    input:
+      bytes: [ 0x05, 0x40, 0xb9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w10, 4:7, vgx4], { z0.b - z3.b }, { z24.b - z27.b }"
+
+  -
+    input:
+      bytes: [ 0x85, 0x02, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w8, 4:7, vgx4], { z20.b - z23.b }, { z28.b - z31.b }"
+
+  -
+    input:
+      bytes: [ 0x85, 0x02, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w8, 4:7, vgx4], { z20.b - z23.b }, { z28.b - z31.b }"
+
+  -
+    input:
+      bytes: [ 0x04, 0x61, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w11, 0:3, vgx4], { z8.b - z11.b }, { z0.b - z3.b }"
+
+  -
+    input:
+      bytes: [ 0x04, 0x61, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w11, 0:3, vgx4], { z8.b - z11.b }, { z0.b - z3.b }"
+
+  -
+    input:
+      bytes: [ 0x85, 0x21, 0xa9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w9, 4:7, vgx4], { z12.b - z15.b }, { z8.b - z11.b }"
+
+  -
+    input:
+      bytes: [ 0x85, 0x21, 0xa9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmlall za.s[w9, 4:7, vgx4], { z12.b - z15.b }, { z8.b - z11.b }"
diff --git a/tests/MC/AArch64/SME2/usvdot.s.yaml b/tests/MC/AArch64/SME2/usvdot.s.yaml
new file mode 100644
index 000000000..63d318fc1
--- /dev/null
+++ b/tests/MC/AArch64/SME2/usvdot.s.yaml
@@ -0,0 +1,240 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x28, 0x80, 0x50, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usvdot za.s[w8, 0, vgx4], { z0.b - z3.b }, z0.b[0]"
+
+  -
+    input:
+      bytes: [ 0x28, 0x80, 0x50, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usvdot za.s[w8, 0, vgx4], { z0.b - z3.b }, z0.b[0]"
+
+  -
+    input:
+      bytes: [ 0x2d, 0xc5, 0x55, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usvdot za.s[w10, 5, vgx4], { z8.b - z11.b }, z5.b[1]"
+
+  -
+    input:
+      bytes: [ 0x2d, 0xc5, 0x55, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usvdot za.s[w10, 5, vgx4], { z8.b - z11.b }, z5.b[1]"
+
+  -
+    input:
+      bytes: [ 0xaf, 0xed, 0x58, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usvdot za.s[w11, 7, vgx4], { z12.b - z15.b }, z8.b[3]"
+
+  -
+    input:
+      bytes: [ 0xaf, 0xed, 0x58, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usvdot za.s[w11, 7, vgx4], { z12.b - z15.b }, z8.b[3]"
+
+  -
+    input:
+      bytes: [ 0xaf, 0xef, 0x5f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usvdot za.s[w11, 7, vgx4], { z28.b - z31.b }, z15.b[3]"
+
+  -
+    input:
+      bytes: [ 0xaf, 0xef, 0x5f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usvdot za.s[w11, 7, vgx4], { z28.b - z31.b }, z15.b[3]"
+
+  -
+    input:
+      bytes: [ 0x2d, 0x8e, 0x50, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usvdot za.s[w8, 5, vgx4], { z16.b - z19.b }, z0.b[3]"
+
+  -
+    input:
+      bytes: [ 0x2d, 0x8e, 0x50, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usvdot za.s[w8, 5, vgx4], { z16.b - z19.b }, z0.b[3]"
+
+  -
+    input:
+      bytes: [ 0x29, 0x84, 0x5e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usvdot za.s[w8, 1, vgx4], { z0.b - z3.b }, z14.b[1]"
+
+  -
+    input:
+      bytes: [ 0x29, 0x84, 0x5e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usvdot za.s[w8, 1, vgx4], { z0.b - z3.b }, z14.b[1]"
+
+  -
+    input:
+      bytes: [ 0x28, 0xc6, 0x54, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usvdot za.s[w10, 0, vgx4], { z16.b - z19.b }, z4.b[1]"
+
+  -
+    input:
+      bytes: [ 0x28, 0xc6, 0x54, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usvdot za.s[w10, 0, vgx4], { z16.b - z19.b }, z4.b[1]"
+
+  -
+    input:
+      bytes: [ 0xa8, 0x89, 0x52, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usvdot za.s[w8, 0, vgx4], { z12.b - z15.b }, z2.b[2]"
+
+  -
+    input:
+      bytes: [ 0xa8, 0x89, 0x52, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usvdot za.s[w8, 0, vgx4], { z12.b - z15.b }, z2.b[2]"
+
+  -
+    input:
+      bytes: [ 0x29, 0xc8, 0x5a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usvdot za.s[w10, 1, vgx4], { z0.b - z3.b }, z10.b[2]"
+
+  -
+    input:
+      bytes: [ 0x29, 0xc8, 0x5a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usvdot za.s[w10, 1, vgx4], { z0.b - z3.b }, z10.b[2]"
+
+  -
+    input:
+      bytes: [ 0xad, 0x8a, 0x5e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usvdot za.s[w8, 5, vgx4], { z20.b - z23.b }, z14.b[2]"
+
+  -
+    input:
+      bytes: [ 0xad, 0x8a, 0x5e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usvdot za.s[w8, 5, vgx4], { z20.b - z23.b }, z14.b[2]"
+
+  -
+    input:
+      bytes: [ 0x2a, 0xe5, 0x51, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usvdot za.s[w11, 2, vgx4], { z8.b - z11.b }, z1.b[1]"
+
+  -
+    input:
+      bytes: [ 0x2a, 0xe5, 0x51, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usvdot za.s[w11, 2, vgx4], { z8.b - z11.b }, z1.b[1]"
+
+  -
+    input:
+      bytes: [ 0xaf, 0xa9, 0x5b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usvdot za.s[w9, 7, vgx4], { z12.b - z15.b }, z11.b[2]"
+
+  -
+    input:
+      bytes: [ 0xaf, 0xa9, 0x5b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usvdot za.s[w9, 7, vgx4], { z12.b - z15.b }, z11.b[2]"
diff --git a/tests/MC/AArch64/SME2/uunpk.s.yaml b/tests/MC/AArch64/SME2/uunpk.s.yaml
new file mode 100644
index 000000000..fed048e1f
--- /dev/null
+++ b/tests/MC/AArch64/SME2/uunpk.s.yaml
@@ -0,0 +1,240 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x01, 0xe0, 0x65, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uunpk { z0.h, z1.h }, z0.b"
+
+  -
+    input:
+      bytes: [ 0x55, 0xe1, 0x65, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uunpk { z20.h, z21.h }, z10.b"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xe1, 0x65, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uunpk { z22.h, z23.h }, z13.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0xe3, 0x65, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uunpk { z30.h, z31.h }, z31.b"
+
+  -
+    input:
+      bytes: [ 0x01, 0xe0, 0xa5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uunpk { z0.s, z1.s }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x55, 0xe1, 0xa5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uunpk { z20.s, z21.s }, z10.h"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xe1, 0xa5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uunpk { z22.s, z23.s }, z13.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0xe3, 0xa5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uunpk { z30.s, z31.s }, z31.h"
+
+  -
+    input:
+      bytes: [ 0x01, 0xe0, 0xe5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uunpk { z0.d, z1.d }, z0.s"
+
+  -
+    input:
+      bytes: [ 0x55, 0xe1, 0xe5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uunpk { z20.d, z21.d }, z10.s"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xe1, 0xe5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uunpk { z22.d, z23.d }, z13.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0xe3, 0xe5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uunpk { z30.d, z31.d }, z31.s"
+
+  -
+    input:
+      bytes: [ 0x01, 0xe0, 0x75, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uunpk { z0.h - z3.h }, { z0.b, z1.b }"
+
+  -
+    input:
+      bytes: [ 0x55, 0xe1, 0x75, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uunpk { z20.h - z23.h }, { z10.b, z11.b }"
+
+  -
+    input:
+      bytes: [ 0x95, 0xe1, 0x75, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uunpk { z20.h - z23.h }, { z12.b, z13.b }"
+
+  -
+    input:
+      bytes: [ 0xdd, 0xe3, 0x75, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uunpk { z28.h - z31.h }, { z30.b, z31.b }"
+
+  -
+    input:
+      bytes: [ 0x01, 0xe0, 0xb5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uunpk { z0.s - z3.s }, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x55, 0xe1, 0xb5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uunpk { z20.s - z23.s }, { z10.h, z11.h }"
+
+  -
+    input:
+      bytes: [ 0x95, 0xe1, 0xb5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uunpk { z20.s - z23.s }, { z12.h, z13.h }"
+
+  -
+    input:
+      bytes: [ 0xdd, 0xe3, 0xb5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uunpk { z28.s - z31.s }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x01, 0xe0, 0xf5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uunpk { z0.d - z3.d }, { z0.s, z1.s }"
+
+  -
+    input:
+      bytes: [ 0x55, 0xe1, 0xf5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uunpk { z20.d - z23.d }, { z10.s, z11.s }"
+
+  -
+    input:
+      bytes: [ 0x95, 0xe1, 0xf5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uunpk { z20.d - z23.d }, { z12.s, z13.s }"
+
+  -
+    input:
+      bytes: [ 0xdd, 0xe3, 0xf5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uunpk { z28.d - z31.d }, { z30.s, z31.s }"
diff --git a/tests/MC/AArch64/SME2/uvdot.s.yaml b/tests/MC/AArch64/SME2/uvdot.s.yaml
new file mode 100644
index 000000000..23ad13806
--- /dev/null
+++ b/tests/MC/AArch64/SME2/uvdot.s.yaml
@@ -0,0 +1,720 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x30, 0x00, 0x50, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "uvdot za.s[w8, 0, vgx2], { z0.h, z1.h }, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x30, 0x00, 0x50, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "uvdot za.s[w8, 0, vgx2], { z0.h, z1.h }, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x75, 0x45, 0x55, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "uvdot za.s[w10, 5, vgx2], { z10.h, z11.h }, z5.h[1]"
+
+  -
+    input:
+      bytes: [ 0x75, 0x45, 0x55, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "uvdot za.s[w10, 5, vgx2], { z10.h, z11.h }, z5.h[1]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x6d, 0x58, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "uvdot za.s[w11, 7, vgx2], { z12.h, z13.h }, z8.h[3]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x6d, 0x58, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "uvdot za.s[w11, 7, vgx2], { z12.h, z13.h }, z8.h[3]"
+
+  -
+    input:
+      bytes: [ 0xf7, 0x6f, 0x5f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "uvdot za.s[w11, 7, vgx2], { z30.h, z31.h }, z15.h[3]"
+
+  -
+    input:
+      bytes: [ 0xf7, 0x6f, 0x5f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "uvdot za.s[w11, 7, vgx2], { z30.h, z31.h }, z15.h[3]"
+
+  -
+    input:
+      bytes: [ 0x35, 0x0e, 0x50, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "uvdot za.s[w8, 5, vgx2], { z16.h, z17.h }, z0.h[3]"
+
+  -
+    input:
+      bytes: [ 0x35, 0x0e, 0x50, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "uvdot za.s[w8, 5, vgx2], { z16.h, z17.h }, z0.h[3]"
+
+  -
+    input:
+      bytes: [ 0x31, 0x04, 0x5e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "uvdot za.s[w8, 1, vgx2], { z0.h, z1.h }, z14.h[1]"
+
+  -
+    input:
+      bytes: [ 0x31, 0x04, 0x5e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "uvdot za.s[w8, 1, vgx2], { z0.h, z1.h }, z14.h[1]"
+
+  -
+    input:
+      bytes: [ 0x70, 0x46, 0x54, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "uvdot za.s[w10, 0, vgx2], { z18.h, z19.h }, z4.h[1]"
+
+  -
+    input:
+      bytes: [ 0x70, 0x46, 0x54, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "uvdot za.s[w10, 0, vgx2], { z18.h, z19.h }, z4.h[1]"
+
+  -
+    input:
+      bytes: [ 0xb0, 0x09, 0x52, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "uvdot za.s[w8, 0, vgx2], { z12.h, z13.h }, z2.h[2]"
+
+  -
+    input:
+      bytes: [ 0xb0, 0x09, 0x52, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "uvdot za.s[w8, 0, vgx2], { z12.h, z13.h }, z2.h[2]"
+
+  -
+    input:
+      bytes: [ 0x31, 0x48, 0x5a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "uvdot za.s[w10, 1, vgx2], { z0.h, z1.h }, z10.h[2]"
+
+  -
+    input:
+      bytes: [ 0x31, 0x48, 0x5a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "uvdot za.s[w10, 1, vgx2], { z0.h, z1.h }, z10.h[2]"
+
+  -
+    input:
+      bytes: [ 0xf5, 0x0a, 0x5e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "uvdot za.s[w8, 5, vgx2], { z22.h, z23.h }, z14.h[2]"
+
+  -
+    input:
+      bytes: [ 0xf5, 0x0a, 0x5e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "uvdot za.s[w8, 5, vgx2], { z22.h, z23.h }, z14.h[2]"
+
+  -
+    input:
+      bytes: [ 0x32, 0x65, 0x51, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "uvdot za.s[w11, 2, vgx2], { z8.h, z9.h }, z1.h[1]"
+
+  -
+    input:
+      bytes: [ 0x32, 0x65, 0x51, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "uvdot za.s[w11, 2, vgx2], { z8.h, z9.h }, z1.h[1]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x29, 0x5b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "uvdot za.s[w9, 7, vgx2], { z12.h, z13.h }, z11.h[2]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x29, 0x5b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "uvdot za.s[w9, 7, vgx2], { z12.h, z13.h }, z11.h[2]"
+
+  -
+    input:
+      bytes: [ 0x30, 0x80, 0x50, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "uvdot za.s[w8, 0, vgx4], { z0.b - z3.b }, z0.b[0]"
+
+  -
+    input:
+      bytes: [ 0x30, 0x80, 0x50, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "uvdot za.s[w8, 0, vgx4], { z0.b - z3.b }, z0.b[0]"
+
+  -
+    input:
+      bytes: [ 0x35, 0xc5, 0x55, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "uvdot za.s[w10, 5, vgx4], { z8.b - z11.b }, z5.b[1]"
+
+  -
+    input:
+      bytes: [ 0x35, 0xc5, 0x55, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "uvdot za.s[w10, 5, vgx4], { z8.b - z11.b }, z5.b[1]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0x58, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "uvdot za.s[w11, 7, vgx4], { z12.b - z15.b }, z8.b[3]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0x58, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "uvdot za.s[w11, 7, vgx4], { z12.b - z15.b }, z8.b[3]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xef, 0x5f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "uvdot za.s[w11, 7, vgx4], { z28.b - z31.b }, z15.b[3]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xef, 0x5f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "uvdot za.s[w11, 7, vgx4], { z28.b - z31.b }, z15.b[3]"
+
+  -
+    input:
+      bytes: [ 0x35, 0x8e, 0x50, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "uvdot za.s[w8, 5, vgx4], { z16.b - z19.b }, z0.b[3]"
+
+  -
+    input:
+      bytes: [ 0x35, 0x8e, 0x50, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "uvdot za.s[w8, 5, vgx4], { z16.b - z19.b }, z0.b[3]"
+
+  -
+    input:
+      bytes: [ 0x31, 0x84, 0x5e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "uvdot za.s[w8, 1, vgx4], { z0.b - z3.b }, z14.b[1]"
+
+  -
+    input:
+      bytes: [ 0x31, 0x84, 0x5e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "uvdot za.s[w8, 1, vgx4], { z0.b - z3.b }, z14.b[1]"
+
+  -
+    input:
+      bytes: [ 0x30, 0xc6, 0x54, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "uvdot za.s[w10, 0, vgx4], { z16.b - z19.b }, z4.b[1]"
+
+  -
+    input:
+      bytes: [ 0x30, 0xc6, 0x54, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "uvdot za.s[w10, 0, vgx4], { z16.b - z19.b }, z4.b[1]"
+
+  -
+    input:
+      bytes: [ 0xb0, 0x89, 0x52, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "uvdot za.s[w8, 0, vgx4], { z12.b - z15.b }, z2.b[2]"
+
+  -
+    input:
+      bytes: [ 0xb0, 0x89, 0x52, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "uvdot za.s[w8, 0, vgx4], { z12.b - z15.b }, z2.b[2]"
+
+  -
+    input:
+      bytes: [ 0x31, 0xc8, 0x5a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "uvdot za.s[w10, 1, vgx4], { z0.b - z3.b }, z10.b[2]"
+
+  -
+    input:
+      bytes: [ 0x31, 0xc8, 0x5a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "uvdot za.s[w10, 1, vgx4], { z0.b - z3.b }, z10.b[2]"
+
+  -
+    input:
+      bytes: [ 0xb5, 0x8a, 0x5e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "uvdot za.s[w8, 5, vgx4], { z20.b - z23.b }, z14.b[2]"
+
+  -
+    input:
+      bytes: [ 0xb5, 0x8a, 0x5e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "uvdot za.s[w8, 5, vgx4], { z20.b - z23.b }, z14.b[2]"
+
+  -
+    input:
+      bytes: [ 0x32, 0xe5, 0x51, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "uvdot za.s[w11, 2, vgx4], { z8.b - z11.b }, z1.b[1]"
+
+  -
+    input:
+      bytes: [ 0x32, 0xe5, 0x51, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "uvdot za.s[w11, 2, vgx4], { z8.b - z11.b }, z1.b[1]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xa9, 0x5b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "uvdot za.s[w9, 7, vgx4], { z12.b - z15.b }, z11.b[2]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xa9, 0x5b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "uvdot za.s[w9, 7, vgx4], { z12.b - z15.b }, z11.b[2]"
+
+  -
+    input:
+      bytes: [ 0x18, 0x88, 0xd0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "uvdot za.d[w8, 0, vgx4], { z0.h - z3.h }, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x18, 0x88, 0xd0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "uvdot za.d[w8, 0, vgx4], { z0.h - z3.h }, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x1d, 0xcd, 0xd5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "uvdot za.d[w10, 5, vgx4], { z8.h - z11.h }, z5.h[1]"
+
+  -
+    input:
+      bytes: [ 0x1d, 0xcd, 0xd5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "uvdot za.d[w10, 5, vgx4], { z8.h - z11.h }, z5.h[1]"
+
+  -
+    input:
+      bytes: [ 0x9f, 0xed, 0xd8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "uvdot za.d[w11, 7, vgx4], { z12.h - z15.h }, z8.h[1]"
+
+  -
+    input:
+      bytes: [ 0x9f, 0xed, 0xd8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "uvdot za.d[w11, 7, vgx4], { z12.h - z15.h }, z8.h[1]"
+
+  -
+    input:
+      bytes: [ 0x9f, 0xef, 0xdf, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "uvdot za.d[w11, 7, vgx4], { z28.h - z31.h }, z15.h[1]"
+
+  -
+    input:
+      bytes: [ 0x9f, 0xef, 0xdf, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "uvdot za.d[w11, 7, vgx4], { z28.h - z31.h }, z15.h[1]"
+
+  -
+    input:
+      bytes: [ 0x1d, 0x8e, 0xd0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "uvdot za.d[w8, 5, vgx4], { z16.h - z19.h }, z0.h[1]"
+
+  -
+    input:
+      bytes: [ 0x1d, 0x8e, 0xd0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "uvdot za.d[w8, 5, vgx4], { z16.h - z19.h }, z0.h[1]"
+
+  -
+    input:
+      bytes: [ 0x19, 0x8c, 0xde, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "uvdot za.d[w8, 1, vgx4], { z0.h - z3.h }, z14.h[1]"
+
+  -
+    input:
+      bytes: [ 0x19, 0x8c, 0xde, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "uvdot za.d[w8, 1, vgx4], { z0.h - z3.h }, z14.h[1]"
+
+  -
+    input:
+      bytes: [ 0x18, 0xce, 0xd4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "uvdot za.d[w10, 0, vgx4], { z16.h - z19.h }, z4.h[1]"
+
+  -
+    input:
+      bytes: [ 0x18, 0xce, 0xd4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "uvdot za.d[w10, 0, vgx4], { z16.h - z19.h }, z4.h[1]"
+
+  -
+    input:
+      bytes: [ 0x98, 0x89, 0xd2, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "uvdot za.d[w8, 0, vgx4], { z12.h - z15.h }, z2.h[0]"
+
+  -
+    input:
+      bytes: [ 0x98, 0x89, 0xd2, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "uvdot za.d[w8, 0, vgx4], { z12.h - z15.h }, z2.h[0]"
+
+  -
+    input:
+      bytes: [ 0x19, 0xc8, 0xda, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "uvdot za.d[w10, 1, vgx4], { z0.h - z3.h }, z10.h[0]"
+
+  -
+    input:
+      bytes: [ 0x19, 0xc8, 0xda, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "uvdot za.d[w10, 1, vgx4], { z0.h - z3.h }, z10.h[0]"
+
+  -
+    input:
+      bytes: [ 0x9d, 0x8a, 0xde, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "uvdot za.d[w8, 5, vgx4], { z20.h - z23.h }, z14.h[0]"
+
+  -
+    input:
+      bytes: [ 0x9d, 0x8a, 0xde, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "uvdot za.d[w8, 5, vgx4], { z20.h - z23.h }, z14.h[0]"
+
+  -
+    input:
+      bytes: [ 0x1a, 0xed, 0xd1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "uvdot za.d[w11, 2, vgx4], { z8.h - z11.h }, z1.h[1]"
+
+  -
+    input:
+      bytes: [ 0x1a, 0xed, 0xd1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "uvdot za.d[w11, 2, vgx4], { z8.h - z11.h }, z1.h[1]"
+
+  -
+    input:
+      bytes: [ 0x9f, 0xa9, 0xdb, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "uvdot za.d[w9, 7, vgx4], { z12.h - z15.h }, z11.h[0]"
+
+  -
+    input:
+      bytes: [ 0x9f, 0xa9, 0xdb, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2", "+sme-i16i64" ]
+    expected:
+      insns:
+        -
+          asm_text: "uvdot za.d[w9, 7, vgx4], { z12.h - z15.h }, z11.h[0]"
diff --git a/tests/MC/AArch64/SME2/uzp.s.yaml b/tests/MC/AArch64/SME2/uzp.s.yaml
new file mode 100644
index 000000000..7195e82c9
--- /dev/null
+++ b/tests/MC/AArch64/SME2/uzp.s.yaml
@@ -0,0 +1,400 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x01, 0xd4, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzp { z0.q, z1.q }, z0.q, z0.q"
+
+  -
+    input:
+      bytes: [ 0x55, 0xd5, 0x35, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzp { z20.q, z21.q }, z10.q, z21.q"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xd5, 0x28, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzp { z22.q, z23.q }, z13.q, z8.q"
+
+  -
+    input:
+      bytes: [ 0xff, 0xd7, 0x3f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzp { z30.q, z31.q }, z31.q, z31.q"
+
+  -
+    input:
+      bytes: [ 0x01, 0xd0, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzp { z0.h, z1.h }, z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x55, 0xd1, 0x75, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzp { z20.h, z21.h }, z10.h, z21.h"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xd1, 0x68, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzp { z22.h, z23.h }, z13.h, z8.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0xd3, 0x7f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzp { z30.h, z31.h }, z31.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x01, 0xd0, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzp { z0.s, z1.s }, z0.s, z0.s"
+
+  -
+    input:
+      bytes: [ 0x55, 0xd1, 0xb5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzp { z20.s, z21.s }, z10.s, z21.s"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xd1, 0xa8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzp { z22.s, z23.s }, z13.s, z8.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0xd3, 0xbf, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzp { z30.s, z31.s }, z31.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x01, 0xd0, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzp { z0.d, z1.d }, z0.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0x55, 0xd1, 0xf5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzp { z20.d, z21.d }, z10.d, z21.d"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xd1, 0xe8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzp { z22.d, z23.d }, z13.d, z8.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0xd3, 0xff, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzp { z30.d, z31.d }, z31.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0x01, 0xd0, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzp { z0.b, z1.b }, z0.b, z0.b"
+
+  -
+    input:
+      bytes: [ 0x55, 0xd1, 0x35, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzp { z20.b, z21.b }, z10.b, z21.b"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xd1, 0x28, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzp { z22.b, z23.b }, z13.b, z8.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0xd3, 0x3f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzp { z30.b, z31.b }, z31.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0x02, 0xe0, 0x37, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzp { z0.q - z3.q }, { z0.q - z3.q }"
+
+  -
+    input:
+      bytes: [ 0x16, 0xe1, 0x37, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzp { z20.q - z23.q }, { z8.q - z11.q }"
+
+  -
+    input:
+      bytes: [ 0x96, 0xe1, 0x37, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzp { z20.q - z23.q }, { z12.q - z15.q }"
+
+  -
+    input:
+      bytes: [ 0x9e, 0xe3, 0x37, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzp { z28.q - z31.q }, { z28.q - z31.q }"
+
+  -
+    input:
+      bytes: [ 0x02, 0xe0, 0x76, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzp { z0.h - z3.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x16, 0xe1, 0x76, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzp { z20.h - z23.h }, { z8.h - z11.h }"
+
+  -
+    input:
+      bytes: [ 0x96, 0xe1, 0x76, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzp { z20.h - z23.h }, { z12.h - z15.h }"
+
+  -
+    input:
+      bytes: [ 0x9e, 0xe3, 0x76, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzp { z28.h - z31.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x02, 0xe0, 0xb6, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzp { z0.s - z3.s }, { z0.s - z3.s }"
+
+  -
+    input:
+      bytes: [ 0x16, 0xe1, 0xb6, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzp { z20.s - z23.s }, { z8.s - z11.s }"
+
+  -
+    input:
+      bytes: [ 0x96, 0xe1, 0xb6, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzp { z20.s - z23.s }, { z12.s - z15.s }"
+
+  -
+    input:
+      bytes: [ 0x9e, 0xe3, 0xb6, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzp { z28.s - z31.s }, { z28.s - z31.s }"
+
+  -
+    input:
+      bytes: [ 0x02, 0xe0, 0xf6, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzp { z0.d - z3.d }, { z0.d - z3.d }"
+
+  -
+    input:
+      bytes: [ 0x16, 0xe1, 0xf6, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzp { z20.d - z23.d }, { z8.d - z11.d }"
+
+  -
+    input:
+      bytes: [ 0x96, 0xe1, 0xf6, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzp { z20.d - z23.d }, { z12.d - z15.d }"
+
+  -
+    input:
+      bytes: [ 0x9e, 0xe3, 0xf6, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzp { z28.d - z31.d }, { z28.d - z31.d }"
+
+  -
+    input:
+      bytes: [ 0x02, 0xe0, 0x36, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzp { z0.b - z3.b }, { z0.b - z3.b }"
+
+  -
+    input:
+      bytes: [ 0x16, 0xe1, 0x36, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzp { z20.b - z23.b }, { z8.b - z11.b }"
+
+  -
+    input:
+      bytes: [ 0x96, 0xe1, 0x36, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzp { z20.b - z23.b }, { z12.b - z15.b }"
+
+  -
+    input:
+      bytes: [ 0x9e, 0xe3, 0x36, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzp { z28.b - z31.b }, { z28.b - z31.b }"
diff --git a/tests/MC/AArch64/SME2/zero.s.yaml b/tests/MC/AArch64/SME2/zero.s.yaml
new file mode 100644
index 000000000..c222c783c
--- /dev/null
+++ b/tests/MC/AArch64/SME2/zero.s.yaml
@@ -0,0 +1,10 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0x48, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "zero { zt0 }"
diff --git a/tests/MC/AArch64/SME2/zip.s.yaml b/tests/MC/AArch64/SME2/zip.s.yaml
new file mode 100644
index 000000000..8a43f41dd
--- /dev/null
+++ b/tests/MC/AArch64/SME2/zip.s.yaml
@@ -0,0 +1,400 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xd4, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip { z0.q, z1.q }, z0.q, z0.q"
+
+  -
+    input:
+      bytes: [ 0x54, 0xd5, 0x35, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip { z20.q, z21.q }, z10.q, z21.q"
+
+  -
+    input:
+      bytes: [ 0xb6, 0xd5, 0x28, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip { z22.q, z23.q }, z13.q, z8.q"
+
+  -
+    input:
+      bytes: [ 0xfe, 0xd7, 0x3f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip { z30.q, z31.q }, z31.q, z31.q"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd0, 0x60, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip { z0.h, z1.h }, z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x54, 0xd1, 0x75, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip { z20.h, z21.h }, z10.h, z21.h"
+
+  -
+    input:
+      bytes: [ 0xb6, 0xd1, 0x68, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip { z22.h, z23.h }, z13.h, z8.h"
+
+  -
+    input:
+      bytes: [ 0xfe, 0xd3, 0x7f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip { z30.h, z31.h }, z31.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd0, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip { z0.s, z1.s }, z0.s, z0.s"
+
+  -
+    input:
+      bytes: [ 0x54, 0xd1, 0xb5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip { z20.s, z21.s }, z10.s, z21.s"
+
+  -
+    input:
+      bytes: [ 0xb6, 0xd1, 0xa8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip { z22.s, z23.s }, z13.s, z8.s"
+
+  -
+    input:
+      bytes: [ 0xfe, 0xd3, 0xbf, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip { z30.s, z31.s }, z31.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd0, 0xe0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip { z0.d, z1.d }, z0.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0x54, 0xd1, 0xf5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip { z20.d, z21.d }, z10.d, z21.d"
+
+  -
+    input:
+      bytes: [ 0xb6, 0xd1, 0xe8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip { z22.d, z23.d }, z13.d, z8.d"
+
+  -
+    input:
+      bytes: [ 0xfe, 0xd3, 0xff, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip { z30.d, z31.d }, z31.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd0, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip { z0.b, z1.b }, z0.b, z0.b"
+
+  -
+    input:
+      bytes: [ 0x54, 0xd1, 0x35, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip { z20.b, z21.b }, z10.b, z21.b"
+
+  -
+    input:
+      bytes: [ 0xb6, 0xd1, 0x28, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip { z22.b, z23.b }, z13.b, z8.b"
+
+  -
+    input:
+      bytes: [ 0xfe, 0xd3, 0x3f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip { z30.b, z31.b }, z31.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x37, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip { z0.q - z3.q }, { z0.q - z3.q }"
+
+  -
+    input:
+      bytes: [ 0x14, 0xe1, 0x37, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip { z20.q - z23.q }, { z8.q - z11.q }"
+
+  -
+    input:
+      bytes: [ 0x94, 0xe1, 0x37, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip { z20.q - z23.q }, { z12.q - z15.q }"
+
+  -
+    input:
+      bytes: [ 0x9c, 0xe3, 0x37, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip { z28.q - z31.q }, { z28.q - z31.q }"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x76, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip { z0.h - z3.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x14, 0xe1, 0x76, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip { z20.h - z23.h }, { z8.h - z11.h }"
+
+  -
+    input:
+      bytes: [ 0x94, 0xe1, 0x76, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip { z20.h - z23.h }, { z12.h - z15.h }"
+
+  -
+    input:
+      bytes: [ 0x9c, 0xe3, 0x76, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip { z28.h - z31.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xb6, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip { z0.s - z3.s }, { z0.s - z3.s }"
+
+  -
+    input:
+      bytes: [ 0x14, 0xe1, 0xb6, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip { z20.s - z23.s }, { z8.s - z11.s }"
+
+  -
+    input:
+      bytes: [ 0x94, 0xe1, 0xb6, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip { z20.s - z23.s }, { z12.s - z15.s }"
+
+  -
+    input:
+      bytes: [ 0x9c, 0xe3, 0xb6, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip { z28.s - z31.s }, { z28.s - z31.s }"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xf6, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip { z0.d - z3.d }, { z0.d - z3.d }"
+
+  -
+    input:
+      bytes: [ 0x14, 0xe1, 0xf6, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip { z20.d - z23.d }, { z8.d - z11.d }"
+
+  -
+    input:
+      bytes: [ 0x94, 0xe1, 0xf6, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip { z20.d - z23.d }, { z12.d - z15.d }"
+
+  -
+    input:
+      bytes: [ 0x9c, 0xe3, 0xf6, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip { z28.d - z31.d }, { z28.d - z31.d }"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x36, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip { z0.b - z3.b }, { z0.b - z3.b }"
+
+  -
+    input:
+      bytes: [ 0x14, 0xe1, 0x36, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip { z20.b - z23.b }, { z8.b - z11.b }"
+
+  -
+    input:
+      bytes: [ 0x94, 0xe1, 0x36, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip { z20.b - z23.b }, { z12.b - z15.b }"
+
+  -
+    input:
+      bytes: [ 0x9c, 0xe3, 0x36, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip { z28.b - z31.b }, { z28.b - z31.b }"
diff --git a/tests/MC/AArch64/SME2p1/fadd.s.yaml b/tests/MC/AArch64/SME2p1/fadd.s.yaml
new file mode 100644
index 000000000..75e7cdb2f
--- /dev/null
+++ b/tests/MC/AArch64/SME2p1/fadd.s.yaml
@@ -0,0 +1,480 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x1c, 0xa4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.h[w8, 0, vgx2], { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x1c, 0xa4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.h[w8, 0, vgx2], { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x45, 0x5d, 0xa4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.h[w10, 5, vgx2], { z10.h, z11.h }"
+
+  -
+    input:
+      bytes: [ 0x45, 0x5d, 0xa4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.h[w10, 5, vgx2], { z10.h, z11.h }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x7d, 0xa4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.h[w11, 7, vgx2], { z12.h, z13.h }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x7d, 0xa4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.h[w11, 7, vgx2], { z12.h, z13.h }"
+
+  -
+    input:
+      bytes: [ 0xc7, 0x7f, 0xa4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.h[w11, 7, vgx2], { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0xc7, 0x7f, 0xa4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.h[w11, 7, vgx2], { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x05, 0x1e, 0xa4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.h[w8, 5, vgx2], { z16.h, z17.h }"
+
+  -
+    input:
+      bytes: [ 0x05, 0x1e, 0xa4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.h[w8, 5, vgx2], { z16.h, z17.h }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x1c, 0xa4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.h[w8, 1, vgx2], { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x1c, 0xa4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.h[w8, 1, vgx2], { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x40, 0x5e, 0xa4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.h[w10, 0, vgx2], { z18.h, z19.h }"
+
+  -
+    input:
+      bytes: [ 0x40, 0x5e, 0xa4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.h[w10, 0, vgx2], { z18.h, z19.h }"
+
+  -
+    input:
+      bytes: [ 0x80, 0x1d, 0xa4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.h[w8, 0, vgx2], { z12.h, z13.h }"
+
+  -
+    input:
+      bytes: [ 0x80, 0x1d, 0xa4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.h[w8, 0, vgx2], { z12.h, z13.h }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x5c, 0xa4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.h[w10, 1, vgx2], { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x5c, 0xa4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.h[w10, 1, vgx2], { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x1e, 0xa4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.h[w8, 5, vgx2], { z22.h, z23.h }"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x1e, 0xa4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.h[w8, 5, vgx2], { z22.h, z23.h }"
+
+  -
+    input:
+      bytes: [ 0x02, 0x7d, 0xa4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.h[w11, 2, vgx2], { z8.h, z9.h }"
+
+  -
+    input:
+      bytes: [ 0x02, 0x7d, 0xa4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.h[w11, 2, vgx2], { z8.h, z9.h }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x3d, 0xa4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.h[w9, 7, vgx2], { z12.h, z13.h }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x3d, 0xa4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.h[w9, 7, vgx2], { z12.h, z13.h }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x1c, 0xa5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.h[w8, 0, vgx4], { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x1c, 0xa5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.h[w8, 0, vgx4], { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x05, 0x5d, 0xa5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.h[w10, 5, vgx4], { z8.h - z11.h }"
+
+  -
+    input:
+      bytes: [ 0x05, 0x5d, 0xa5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.h[w10, 5, vgx4], { z8.h - z11.h }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x7d, 0xa5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.h[w11, 7, vgx4], { z12.h - z15.h }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x7d, 0xa5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.h[w11, 7, vgx4], { z12.h - z15.h }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x7f, 0xa5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.h[w11, 7, vgx4], { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x7f, 0xa5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.h[w11, 7, vgx4], { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x05, 0x1e, 0xa5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.h[w8, 5, vgx4], { z16.h - z19.h }"
+
+  -
+    input:
+      bytes: [ 0x05, 0x1e, 0xa5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.h[w8, 5, vgx4], { z16.h - z19.h }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x1c, 0xa5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.h[w8, 1, vgx4], { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x1c, 0xa5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.h[w8, 1, vgx4], { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x5e, 0xa5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.h[w10, 0, vgx4], { z16.h - z19.h }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x5e, 0xa5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.h[w10, 0, vgx4], { z16.h - z19.h }"
+
+  -
+    input:
+      bytes: [ 0x80, 0x1d, 0xa5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.h[w8, 0, vgx4], { z12.h - z15.h }"
+
+  -
+    input:
+      bytes: [ 0x80, 0x1d, 0xa5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.h[w8, 0, vgx4], { z12.h - z15.h }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x5c, 0xa5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.h[w10, 1, vgx4], { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x01, 0x5c, 0xa5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.h[w10, 1, vgx4], { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x85, 0x1e, 0xa5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.h[w8, 5, vgx4], { z20.h - z23.h }"
+
+  -
+    input:
+      bytes: [ 0x85, 0x1e, 0xa5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.h[w8, 5, vgx4], { z20.h - z23.h }"
+
+  -
+    input:
+      bytes: [ 0x02, 0x7d, 0xa5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.h[w11, 2, vgx4], { z8.h - z11.h }"
+
+  -
+    input:
+      bytes: [ 0x02, 0x7d, 0xa5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.h[w11, 2, vgx4], { z8.h - z11.h }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x3d, 0xa5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.h[w9, 7, vgx4], { z12.h - z15.h }"
+
+  -
+    input:
+      bytes: [ 0x87, 0x3d, 0xa5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd za.h[w9, 7, vgx4], { z12.h - z15.h }"
diff --git a/tests/MC/AArch64/SME2p1/fcvt.s.yaml b/tests/MC/AArch64/SME2p1/fcvt.s.yaml
new file mode 100644
index 000000000..394de62c9
--- /dev/null
+++ b/tests/MC/AArch64/SME2p1/fcvt.s.yaml
@@ -0,0 +1,40 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvt { z0.s, z1.s }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x54, 0xe1, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvt { z20.s, z21.s }, z10.h"
+
+  -
+    input:
+      bytes: [ 0xb6, 0xe1, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvt { z22.s, z23.s }, z13.h"
+
+  -
+    input:
+      bytes: [ 0xfe, 0xe3, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvt { z30.s, z31.s }, z31.h"
diff --git a/tests/MC/AArch64/SME2p1/fcvtl.s.yaml b/tests/MC/AArch64/SME2p1/fcvtl.s.yaml
new file mode 100644
index 000000000..23d28aa4c
--- /dev/null
+++ b/tests/MC/AArch64/SME2p1/fcvtl.s.yaml
@@ -0,0 +1,40 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x01, 0xe0, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtl { z0.s, z1.s }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x55, 0xe1, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtl { z20.s, z21.s }, z10.h"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xe1, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtl { z22.s, z23.s }, z13.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0xe3, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtl { z30.s, z31.s }, z31.h"
diff --git a/tests/MC/AArch64/SME2p1/fmla.s.yaml b/tests/MC/AArch64/SME2p1/fmla.s.yaml
new file mode 100644
index 000000000..38c335156
--- /dev/null
+++ b/tests/MC/AArch64/SME2p1/fmla.s.yaml
@@ -0,0 +1,1440 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x1c, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w8, 0, vgx2], { z0.h, z1.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x1c, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w8, 0, vgx2], { z0.h, z1.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x45, 0x5d, 0x25, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w10, 5, vgx2], { z10.h, z11.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0x45, 0x5d, 0x25, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w10, 5, vgx2], { z10.h, z11.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0xa7, 0x7d, 0x28, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w11, 7, vgx2], { z13.h, z14.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0xa7, 0x7d, 0x28, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w11, 7, vgx2], { z13.h, z14.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0xe7, 0x7f, 0x2f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w11, 7, vgx2], { z31.h, z0.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0xe7, 0x7f, 0x2f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w11, 7, vgx2], { z31.h, z0.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0x25, 0x1e, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w8, 5, vgx2], { z17.h, z18.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x25, 0x1e, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w8, 5, vgx2], { z17.h, z18.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x21, 0x1c, 0x2e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w8, 1, vgx2], { z1.h, z2.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x21, 0x1c, 0x2e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w8, 1, vgx2], { z1.h, z2.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x60, 0x5e, 0x24, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w10, 0, vgx2], { z19.h, z20.h }, z4.h"
+
+  -
+    input:
+      bytes: [ 0x60, 0x5e, 0x24, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w10, 0, vgx2], { z19.h, z20.h }, z4.h"
+
+  -
+    input:
+      bytes: [ 0x80, 0x1d, 0x22, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w8, 0, vgx2], { z12.h, z13.h }, z2.h"
+
+  -
+    input:
+      bytes: [ 0x80, 0x1d, 0x22, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w8, 0, vgx2], { z12.h, z13.h }, z2.h"
+
+  -
+    input:
+      bytes: [ 0x21, 0x5c, 0x2a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w10, 1, vgx2], { z1.h, z2.h }, z10.h"
+
+  -
+    input:
+      bytes: [ 0x21, 0x5c, 0x2a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w10, 1, vgx2], { z1.h, z2.h }, z10.h"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x1e, 0x2e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w8, 5, vgx2], { z22.h, z23.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x1e, 0x2e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w8, 5, vgx2], { z22.h, z23.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x22, 0x7d, 0x21, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w11, 2, vgx2], { z9.h, z10.h }, z1.h"
+
+  -
+    input:
+      bytes: [ 0x22, 0x7d, 0x21, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w11, 2, vgx2], { z9.h, z10.h }, z1.h"
+
+  -
+    input:
+      bytes: [ 0x87, 0x3d, 0x2b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w9, 7, vgx2], { z12.h, z13.h }, z11.h"
+
+  -
+    input:
+      bytes: [ 0x87, 0x3d, 0x2b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w9, 7, vgx2], { z12.h, z13.h }, z11.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x10, 0x10, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w8, 0, vgx2], { z0.h, z1.h }, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x10, 0x10, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w8, 0, vgx2], { z0.h, z1.h }, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x45, 0x55, 0x15, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w10, 5, vgx2], { z10.h, z11.h }, z5.h[2]"
+
+  -
+    input:
+      bytes: [ 0x45, 0x55, 0x15, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w10, 5, vgx2], { z10.h, z11.h }, z5.h[2]"
+
+  -
+    input:
+      bytes: [ 0x87, 0x7d, 0x18, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w11, 7, vgx2], { z12.h, z13.h }, z8.h[6]"
+
+  -
+    input:
+      bytes: [ 0x87, 0x7d, 0x18, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w11, 7, vgx2], { z12.h, z13.h }, z8.h[6]"
+
+  -
+    input:
+      bytes: [ 0xcf, 0x7f, 0x1f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w11, 7, vgx2], { z30.h, z31.h }, z15.h[7]"
+
+  -
+    input:
+      bytes: [ 0xcf, 0x7f, 0x1f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w11, 7, vgx2], { z30.h, z31.h }, z15.h[7]"
+
+  -
+    input:
+      bytes: [ 0x05, 0x1e, 0x10, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w8, 5, vgx2], { z16.h, z17.h }, z0.h[6]"
+
+  -
+    input:
+      bytes: [ 0x05, 0x1e, 0x10, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w8, 5, vgx2], { z16.h, z17.h }, z0.h[6]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x14, 0x1e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w8, 1, vgx2], { z0.h, z1.h }, z14.h[2]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x14, 0x1e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w8, 1, vgx2], { z0.h, z1.h }, z14.h[2]"
+
+  -
+    input:
+      bytes: [ 0x48, 0x56, 0x14, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w10, 0, vgx2], { z18.h, z19.h }, z4.h[3]"
+
+  -
+    input:
+      bytes: [ 0x48, 0x56, 0x14, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w10, 0, vgx2], { z18.h, z19.h }, z4.h[3]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x19, 0x12, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w8, 0, vgx2], { z12.h, z13.h }, z2.h[4]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x19, 0x12, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w8, 0, vgx2], { z12.h, z13.h }, z2.h[4]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x58, 0x1a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w10, 1, vgx2], { z0.h, z1.h }, z10.h[4]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x58, 0x1a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w10, 1, vgx2], { z0.h, z1.h }, z10.h[4]"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x1a, 0x1e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w8, 5, vgx2], { z22.h, z23.h }, z14.h[5]"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x1a, 0x1e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w8, 5, vgx2], { z22.h, z23.h }, z14.h[5]"
+
+  -
+    input:
+      bytes: [ 0x02, 0x75, 0x11, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w11, 2, vgx2], { z8.h, z9.h }, z1.h[2]"
+
+  -
+    input:
+      bytes: [ 0x02, 0x75, 0x11, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w11, 2, vgx2], { z8.h, z9.h }, z1.h[2]"
+
+  -
+    input:
+      bytes: [ 0x87, 0x39, 0x1b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w9, 7, vgx2], { z12.h, z13.h }, z11.h[4]"
+
+  -
+    input:
+      bytes: [ 0x87, 0x39, 0x1b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w9, 7, vgx2], { z12.h, z13.h }, z11.h[4]"
+
+  -
+    input:
+      bytes: [ 0x08, 0x10, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w8, 0, vgx2], { z0.h, z1.h }, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x08, 0x10, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w8, 0, vgx2], { z0.h, z1.h }, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x4d, 0x51, 0xb4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w10, 5, vgx2], { z10.h, z11.h }, { z20.h, z21.h }"
+
+  -
+    input:
+      bytes: [ 0x4d, 0x51, 0xb4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w10, 5, vgx2], { z10.h, z11.h }, { z20.h, z21.h }"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x71, 0xa8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w11, 7, vgx2], { z12.h, z13.h }, { z8.h, z9.h }"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x71, 0xa8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w11, 7, vgx2], { z12.h, z13.h }, { z8.h, z9.h }"
+
+  -
+    input:
+      bytes: [ 0xcf, 0x73, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w11, 7, vgx2], { z30.h, z31.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0xcf, 0x73, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w11, 7, vgx2], { z30.h, z31.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x0d, 0x12, 0xb0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w8, 5, vgx2], { z16.h, z17.h }, { z16.h, z17.h }"
+
+  -
+    input:
+      bytes: [ 0x0d, 0x12, 0xb0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w8, 5, vgx2], { z16.h, z17.h }, { z16.h, z17.h }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x10, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w8, 1, vgx2], { z0.h, z1.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x10, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w8, 1, vgx2], { z0.h, z1.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x48, 0x52, 0xb4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w10, 0, vgx2], { z18.h, z19.h }, { z20.h, z21.h }"
+
+  -
+    input:
+      bytes: [ 0x48, 0x52, 0xb4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w10, 0, vgx2], { z18.h, z19.h }, { z20.h, z21.h }"
+
+  -
+    input:
+      bytes: [ 0x88, 0x11, 0xa2, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w8, 0, vgx2], { z12.h, z13.h }, { z2.h, z3.h }"
+
+  -
+    input:
+      bytes: [ 0x88, 0x11, 0xa2, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w8, 0, vgx2], { z12.h, z13.h }, { z2.h, z3.h }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x50, 0xba, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w10, 1, vgx2], { z0.h, z1.h }, { z26.h, z27.h }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x50, 0xba, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w10, 1, vgx2], { z0.h, z1.h }, { z26.h, z27.h }"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x12, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w8, 5, vgx2], { z22.h, z23.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x12, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w8, 5, vgx2], { z22.h, z23.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x0a, 0x71, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w11, 2, vgx2], { z8.h, z9.h }, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x0a, 0x71, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w11, 2, vgx2], { z8.h, z9.h }, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x31, 0xaa, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w9, 7, vgx2], { z12.h, z13.h }, { z10.h, z11.h }"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x31, 0xaa, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w9, 7, vgx2], { z12.h, z13.h }, { z10.h, z11.h }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x1c, 0x30, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w8, 0, vgx4], { z0.h - z3.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x1c, 0x30, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w8, 0, vgx4], { z0.h - z3.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x45, 0x5d, 0x35, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w10, 5, vgx4], { z10.h - z13.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0x45, 0x5d, 0x35, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w10, 5, vgx4], { z10.h - z13.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0xa7, 0x7d, 0x38, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w11, 7, vgx4], { z13.h - z16.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0xa7, 0x7d, 0x38, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w11, 7, vgx4], { z13.h - z16.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0xe7, 0x7f, 0x3f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w11, 7, vgx4], { z31.h, z0.h, z1.h, z2.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0xe7, 0x7f, 0x3f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w11, 7, vgx4], { z31.h, z0.h, z1.h, z2.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0x25, 0x1e, 0x30, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w8, 5, vgx4], { z17.h - z20.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x25, 0x1e, 0x30, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w8, 5, vgx4], { z17.h - z20.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x21, 0x1c, 0x3e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w8, 1, vgx4], { z1.h - z4.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x21, 0x1c, 0x3e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w8, 1, vgx4], { z1.h - z4.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x60, 0x5e, 0x34, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w10, 0, vgx4], { z19.h - z22.h }, z4.h"
+
+  -
+    input:
+      bytes: [ 0x60, 0x5e, 0x34, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w10, 0, vgx4], { z19.h - z22.h }, z4.h"
+
+  -
+    input:
+      bytes: [ 0x80, 0x1d, 0x32, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w8, 0, vgx4], { z12.h - z15.h }, z2.h"
+
+  -
+    input:
+      bytes: [ 0x80, 0x1d, 0x32, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w8, 0, vgx4], { z12.h - z15.h }, z2.h"
+
+  -
+    input:
+      bytes: [ 0x21, 0x5c, 0x3a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w10, 1, vgx4], { z1.h - z4.h }, z10.h"
+
+  -
+    input:
+      bytes: [ 0x21, 0x5c, 0x3a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w10, 1, vgx4], { z1.h - z4.h }, z10.h"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x1e, 0x3e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w8, 5, vgx4], { z22.h - z25.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x1e, 0x3e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w8, 5, vgx4], { z22.h - z25.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x22, 0x7d, 0x31, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w11, 2, vgx4], { z9.h - z12.h }, z1.h"
+
+  -
+    input:
+      bytes: [ 0x22, 0x7d, 0x31, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w11, 2, vgx4], { z9.h - z12.h }, z1.h"
+
+  -
+    input:
+      bytes: [ 0x87, 0x3d, 0x3b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w9, 7, vgx4], { z12.h - z15.h }, z11.h"
+
+  -
+    input:
+      bytes: [ 0x87, 0x3d, 0x3b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w9, 7, vgx4], { z12.h - z15.h }, z11.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x90, 0x10, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w8, 0, vgx4], { z0.h - z3.h }, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x90, 0x10, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w8, 0, vgx4], { z0.h - z3.h }, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x05, 0xd5, 0x15, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w10, 5, vgx4], { z8.h - z11.h }, z5.h[2]"
+
+  -
+    input:
+      bytes: [ 0x05, 0xd5, 0x15, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w10, 5, vgx4], { z8.h - z11.h }, z5.h[2]"
+
+  -
+    input:
+      bytes: [ 0x87, 0xfd, 0x18, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w11, 7, vgx4], { z12.h - z15.h }, z8.h[6]"
+
+  -
+    input:
+      bytes: [ 0x87, 0xfd, 0x18, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w11, 7, vgx4], { z12.h - z15.h }, z8.h[6]"
+
+  -
+    input:
+      bytes: [ 0x8f, 0xff, 0x1f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w11, 7, vgx4], { z28.h - z31.h }, z15.h[7]"
+
+  -
+    input:
+      bytes: [ 0x8f, 0xff, 0x1f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w11, 7, vgx4], { z28.h - z31.h }, z15.h[7]"
+
+  -
+    input:
+      bytes: [ 0x05, 0x9e, 0x10, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w8, 5, vgx4], { z16.h - z19.h }, z0.h[6]"
+
+  -
+    input:
+      bytes: [ 0x05, 0x9e, 0x10, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w8, 5, vgx4], { z16.h - z19.h }, z0.h[6]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x94, 0x1e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w8, 1, vgx4], { z0.h - z3.h }, z14.h[2]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x94, 0x1e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w8, 1, vgx4], { z0.h - z3.h }, z14.h[2]"
+
+  -
+    input:
+      bytes: [ 0x08, 0xd6, 0x14, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w10, 0, vgx4], { z16.h - z19.h }, z4.h[3]"
+
+  -
+    input:
+      bytes: [ 0x08, 0xd6, 0x14, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w10, 0, vgx4], { z16.h - z19.h }, z4.h[3]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x99, 0x12, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w8, 0, vgx4], { z12.h - z15.h }, z2.h[4]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x99, 0x12, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w8, 0, vgx4], { z12.h - z15.h }, z2.h[4]"
+
+  -
+    input:
+      bytes: [ 0x01, 0xd8, 0x1a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w10, 1, vgx4], { z0.h - z3.h }, z10.h[4]"
+
+  -
+    input:
+      bytes: [ 0x01, 0xd8, 0x1a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w10, 1, vgx4], { z0.h - z3.h }, z10.h[4]"
+
+  -
+    input:
+      bytes: [ 0x8d, 0x9a, 0x1e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w8, 5, vgx4], { z20.h - z23.h }, z14.h[5]"
+
+  -
+    input:
+      bytes: [ 0x8d, 0x9a, 0x1e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w8, 5, vgx4], { z20.h - z23.h }, z14.h[5]"
+
+  -
+    input:
+      bytes: [ 0x02, 0xf5, 0x11, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w11, 2, vgx4], { z8.h - z11.h }, z1.h[2]"
+
+  -
+    input:
+      bytes: [ 0x02, 0xf5, 0x11, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w11, 2, vgx4], { z8.h - z11.h }, z1.h[2]"
+
+  -
+    input:
+      bytes: [ 0x87, 0xb9, 0x1b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w9, 7, vgx4], { z12.h - z15.h }, z11.h[4]"
+
+  -
+    input:
+      bytes: [ 0x87, 0xb9, 0x1b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w9, 7, vgx4], { z12.h - z15.h }, z11.h[4]"
+
+  -
+    input:
+      bytes: [ 0x08, 0x10, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w8, 0, vgx4], { z0.h - z3.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x08, 0x10, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w8, 0, vgx4], { z0.h - z3.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x0d, 0x51, 0xb5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w10, 5, vgx4], { z8.h - z11.h }, { z20.h - z23.h }"
+
+  -
+    input:
+      bytes: [ 0x0d, 0x51, 0xb5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w10, 5, vgx4], { z8.h - z11.h }, { z20.h - z23.h }"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x71, 0xa9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w11, 7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x71, 0xa9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w11, 7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x73, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w11, 7, vgx4], { z28.h - z31.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x73, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w11, 7, vgx4], { z28.h - z31.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x0d, 0x12, 0xb1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w8, 5, vgx4], { z16.h - z19.h }, { z16.h - z19.h }"
+
+  -
+    input:
+      bytes: [ 0x0d, 0x12, 0xb1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w8, 5, vgx4], { z16.h - z19.h }, { z16.h - z19.h }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x10, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w8, 1, vgx4], { z0.h - z3.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x10, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w8, 1, vgx4], { z0.h - z3.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x08, 0x52, 0xb5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w10, 0, vgx4], { z16.h - z19.h }, { z20.h - z23.h }"
+
+  -
+    input:
+      bytes: [ 0x08, 0x52, 0xb5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w10, 0, vgx4], { z16.h - z19.h }, { z20.h - z23.h }"
+
+  -
+    input:
+      bytes: [ 0x88, 0x11, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w8, 0, vgx4], { z12.h - z15.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x88, 0x11, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w8, 0, vgx4], { z12.h - z15.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x50, 0xb9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w10, 1, vgx4], { z0.h - z3.h }, { z24.h - z27.h }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x50, 0xb9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w10, 1, vgx4], { z0.h - z3.h }, { z24.h - z27.h }"
+
+  -
+    input:
+      bytes: [ 0x8d, 0x12, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w8, 5, vgx4], { z20.h - z23.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x8d, 0x12, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w8, 5, vgx4], { z20.h - z23.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x0a, 0x71, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w11, 2, vgx4], { z8.h - z11.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x0a, 0x71, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w11, 2, vgx4], { z8.h - z11.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x31, 0xa9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w9, 7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x31, 0xa9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla za.h[w9, 7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }"
diff --git a/tests/MC/AArch64/SME2p1/fmls.s.yaml b/tests/MC/AArch64/SME2p1/fmls.s.yaml
new file mode 100644
index 000000000..f5f463d9d
--- /dev/null
+++ b/tests/MC/AArch64/SME2p1/fmls.s.yaml
@@ -0,0 +1,1440 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x08, 0x1c, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w8, 0, vgx2], { z0.h, z1.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x08, 0x1c, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w8, 0, vgx2], { z0.h, z1.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x4d, 0x5d, 0x25, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w10, 5, vgx2], { z10.h, z11.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0x4d, 0x5d, 0x25, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w10, 5, vgx2], { z10.h, z11.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0xaf, 0x7d, 0x28, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w11, 7, vgx2], { z13.h, z14.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0xaf, 0x7d, 0x28, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w11, 7, vgx2], { z13.h, z14.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0xef, 0x7f, 0x2f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w11, 7, vgx2], { z31.h, z0.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0xef, 0x7f, 0x2f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w11, 7, vgx2], { z31.h, z0.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0x2d, 0x1e, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w8, 5, vgx2], { z17.h, z18.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x2d, 0x1e, 0x20, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w8, 5, vgx2], { z17.h, z18.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x29, 0x1c, 0x2e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w8, 1, vgx2], { z1.h, z2.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x29, 0x1c, 0x2e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w8, 1, vgx2], { z1.h, z2.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x68, 0x5e, 0x24, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w10, 0, vgx2], { z19.h, z20.h }, z4.h"
+
+  -
+    input:
+      bytes: [ 0x68, 0x5e, 0x24, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w10, 0, vgx2], { z19.h, z20.h }, z4.h"
+
+  -
+    input:
+      bytes: [ 0x88, 0x1d, 0x22, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w8, 0, vgx2], { z12.h, z13.h }, z2.h"
+
+  -
+    input:
+      bytes: [ 0x88, 0x1d, 0x22, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w8, 0, vgx2], { z12.h, z13.h }, z2.h"
+
+  -
+    input:
+      bytes: [ 0x29, 0x5c, 0x2a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w10, 1, vgx2], { z1.h, z2.h }, z10.h"
+
+  -
+    input:
+      bytes: [ 0x29, 0x5c, 0x2a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w10, 1, vgx2], { z1.h, z2.h }, z10.h"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x1e, 0x2e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w8, 5, vgx2], { z22.h, z23.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x1e, 0x2e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w8, 5, vgx2], { z22.h, z23.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x2a, 0x7d, 0x21, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w11, 2, vgx2], { z9.h, z10.h }, z1.h"
+
+  -
+    input:
+      bytes: [ 0x2a, 0x7d, 0x21, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w11, 2, vgx2], { z9.h, z10.h }, z1.h"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x3d, 0x2b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w9, 7, vgx2], { z12.h, z13.h }, z11.h"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x3d, 0x2b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w9, 7, vgx2], { z12.h, z13.h }, z11.h"
+
+  -
+    input:
+      bytes: [ 0x10, 0x10, 0x10, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w8, 0, vgx2], { z0.h, z1.h }, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x10, 0x10, 0x10, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w8, 0, vgx2], { z0.h, z1.h }, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x55, 0x15, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w10, 5, vgx2], { z10.h, z11.h }, z5.h[2]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x55, 0x15, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w10, 5, vgx2], { z10.h, z11.h }, z5.h[2]"
+
+  -
+    input:
+      bytes: [ 0x97, 0x7d, 0x18, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w11, 7, vgx2], { z12.h, z13.h }, z8.h[6]"
+
+  -
+    input:
+      bytes: [ 0x97, 0x7d, 0x18, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w11, 7, vgx2], { z12.h, z13.h }, z8.h[6]"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x7f, 0x1f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w11, 7, vgx2], { z30.h, z31.h }, z15.h[7]"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x7f, 0x1f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w11, 7, vgx2], { z30.h, z31.h }, z15.h[7]"
+
+  -
+    input:
+      bytes: [ 0x15, 0x1e, 0x10, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w8, 5, vgx2], { z16.h, z17.h }, z0.h[6]"
+
+  -
+    input:
+      bytes: [ 0x15, 0x1e, 0x10, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w8, 5, vgx2], { z16.h, z17.h }, z0.h[6]"
+
+  -
+    input:
+      bytes: [ 0x11, 0x14, 0x1e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w8, 1, vgx2], { z0.h, z1.h }, z14.h[2]"
+
+  -
+    input:
+      bytes: [ 0x11, 0x14, 0x1e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w8, 1, vgx2], { z0.h, z1.h }, z14.h[2]"
+
+  -
+    input:
+      bytes: [ 0x58, 0x56, 0x14, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w10, 0, vgx2], { z18.h, z19.h }, z4.h[3]"
+
+  -
+    input:
+      bytes: [ 0x58, 0x56, 0x14, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w10, 0, vgx2], { z18.h, z19.h }, z4.h[3]"
+
+  -
+    input:
+      bytes: [ 0x90, 0x19, 0x12, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w8, 0, vgx2], { z12.h, z13.h }, z2.h[4]"
+
+  -
+    input:
+      bytes: [ 0x90, 0x19, 0x12, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w8, 0, vgx2], { z12.h, z13.h }, z2.h[4]"
+
+  -
+    input:
+      bytes: [ 0x11, 0x58, 0x1a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w10, 1, vgx2], { z0.h, z1.h }, z10.h[4]"
+
+  -
+    input:
+      bytes: [ 0x11, 0x58, 0x1a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w10, 1, vgx2], { z0.h, z1.h }, z10.h[4]"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x1a, 0x1e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w8, 5, vgx2], { z22.h, z23.h }, z14.h[5]"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x1a, 0x1e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w8, 5, vgx2], { z22.h, z23.h }, z14.h[5]"
+
+  -
+    input:
+      bytes: [ 0x12, 0x75, 0x11, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w11, 2, vgx2], { z8.h, z9.h }, z1.h[2]"
+
+  -
+    input:
+      bytes: [ 0x12, 0x75, 0x11, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w11, 2, vgx2], { z8.h, z9.h }, z1.h[2]"
+
+  -
+    input:
+      bytes: [ 0x97, 0x39, 0x1b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w9, 7, vgx2], { z12.h, z13.h }, z11.h[4]"
+
+  -
+    input:
+      bytes: [ 0x97, 0x39, 0x1b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w9, 7, vgx2], { z12.h, z13.h }, z11.h[4]"
+
+  -
+    input:
+      bytes: [ 0x18, 0x10, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w8, 0, vgx2], { z0.h, z1.h }, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x18, 0x10, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w8, 0, vgx2], { z0.h, z1.h }, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x5d, 0x51, 0xb4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w10, 5, vgx2], { z10.h, z11.h }, { z20.h, z21.h }"
+
+  -
+    input:
+      bytes: [ 0x5d, 0x51, 0xb4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w10, 5, vgx2], { z10.h, z11.h }, { z20.h, z21.h }"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x71, 0xa8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w11, 7, vgx2], { z12.h, z13.h }, { z8.h, z9.h }"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x71, 0xa8, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w11, 7, vgx2], { z12.h, z13.h }, { z8.h, z9.h }"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x73, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w11, 7, vgx2], { z30.h, z31.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x73, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w11, 7, vgx2], { z30.h, z31.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x1d, 0x12, 0xb0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w8, 5, vgx2], { z16.h, z17.h }, { z16.h, z17.h }"
+
+  -
+    input:
+      bytes: [ 0x1d, 0x12, 0xb0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w8, 5, vgx2], { z16.h, z17.h }, { z16.h, z17.h }"
+
+  -
+    input:
+      bytes: [ 0x19, 0x10, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w8, 1, vgx2], { z0.h, z1.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x19, 0x10, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w8, 1, vgx2], { z0.h, z1.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x58, 0x52, 0xb4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w10, 0, vgx2], { z18.h, z19.h }, { z20.h, z21.h }"
+
+  -
+    input:
+      bytes: [ 0x58, 0x52, 0xb4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w10, 0, vgx2], { z18.h, z19.h }, { z20.h, z21.h }"
+
+  -
+    input:
+      bytes: [ 0x98, 0x11, 0xa2, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w8, 0, vgx2], { z12.h, z13.h }, { z2.h, z3.h }"
+
+  -
+    input:
+      bytes: [ 0x98, 0x11, 0xa2, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w8, 0, vgx2], { z12.h, z13.h }, { z2.h, z3.h }"
+
+  -
+    input:
+      bytes: [ 0x19, 0x50, 0xba, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w10, 1, vgx2], { z0.h, z1.h }, { z26.h, z27.h }"
+
+  -
+    input:
+      bytes: [ 0x19, 0x50, 0xba, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w10, 1, vgx2], { z0.h, z1.h }, { z26.h, z27.h }"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x12, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w8, 5, vgx2], { z22.h, z23.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x12, 0xbe, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w8, 5, vgx2], { z22.h, z23.h }, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x1a, 0x71, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w11, 2, vgx2], { z8.h, z9.h }, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x1a, 0x71, 0xa0, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w11, 2, vgx2], { z8.h, z9.h }, { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x31, 0xaa, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w9, 7, vgx2], { z12.h, z13.h }, { z10.h, z11.h }"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x31, 0xaa, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w9, 7, vgx2], { z12.h, z13.h }, { z10.h, z11.h }"
+
+  -
+    input:
+      bytes: [ 0x08, 0x1c, 0x30, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w8, 0, vgx4], { z0.h - z3.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x08, 0x1c, 0x30, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w8, 0, vgx4], { z0.h - z3.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x4d, 0x5d, 0x35, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w10, 5, vgx4], { z10.h - z13.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0x4d, 0x5d, 0x35, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w10, 5, vgx4], { z10.h - z13.h }, z5.h"
+
+  -
+    input:
+      bytes: [ 0xaf, 0x7d, 0x38, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w11, 7, vgx4], { z13.h - z16.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0xaf, 0x7d, 0x38, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w11, 7, vgx4], { z13.h - z16.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0xef, 0x7f, 0x3f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w11, 7, vgx4], { z31.h, z0.h, z1.h, z2.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0xef, 0x7f, 0x3f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w11, 7, vgx4], { z31.h, z0.h, z1.h, z2.h }, z15.h"
+
+  -
+    input:
+      bytes: [ 0x2d, 0x1e, 0x30, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w8, 5, vgx4], { z17.h - z20.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x2d, 0x1e, 0x30, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w8, 5, vgx4], { z17.h - z20.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x29, 0x1c, 0x3e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w8, 1, vgx4], { z1.h - z4.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x29, 0x1c, 0x3e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w8, 1, vgx4], { z1.h - z4.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x68, 0x5e, 0x34, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w10, 0, vgx4], { z19.h - z22.h }, z4.h"
+
+  -
+    input:
+      bytes: [ 0x68, 0x5e, 0x34, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w10, 0, vgx4], { z19.h - z22.h }, z4.h"
+
+  -
+    input:
+      bytes: [ 0x88, 0x1d, 0x32, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w8, 0, vgx4], { z12.h - z15.h }, z2.h"
+
+  -
+    input:
+      bytes: [ 0x88, 0x1d, 0x32, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w8, 0, vgx4], { z12.h - z15.h }, z2.h"
+
+  -
+    input:
+      bytes: [ 0x29, 0x5c, 0x3a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w10, 1, vgx4], { z1.h - z4.h }, z10.h"
+
+  -
+    input:
+      bytes: [ 0x29, 0x5c, 0x3a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w10, 1, vgx4], { z1.h - z4.h }, z10.h"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x1e, 0x3e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w8, 5, vgx4], { z22.h - z25.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x1e, 0x3e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w8, 5, vgx4], { z22.h - z25.h }, z14.h"
+
+  -
+    input:
+      bytes: [ 0x2a, 0x7d, 0x31, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w11, 2, vgx4], { z9.h - z12.h }, z1.h"
+
+  -
+    input:
+      bytes: [ 0x2a, 0x7d, 0x31, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w11, 2, vgx4], { z9.h - z12.h }, z1.h"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x3d, 0x3b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w9, 7, vgx4], { z12.h - z15.h }, z11.h"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x3d, 0x3b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w9, 7, vgx4], { z12.h - z15.h }, z11.h"
+
+  -
+    input:
+      bytes: [ 0x10, 0x90, 0x10, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w8, 0, vgx4], { z0.h - z3.h }, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x10, 0x90, 0x10, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w8, 0, vgx4], { z0.h - z3.h }, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x15, 0xd5, 0x15, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w10, 5, vgx4], { z8.h - z11.h }, z5.h[2]"
+
+  -
+    input:
+      bytes: [ 0x15, 0xd5, 0x15, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w10, 5, vgx4], { z8.h - z11.h }, z5.h[2]"
+
+  -
+    input:
+      bytes: [ 0x97, 0xfd, 0x18, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w11, 7, vgx4], { z12.h - z15.h }, z8.h[6]"
+
+  -
+    input:
+      bytes: [ 0x97, 0xfd, 0x18, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w11, 7, vgx4], { z12.h - z15.h }, z8.h[6]"
+
+  -
+    input:
+      bytes: [ 0x9f, 0xff, 0x1f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w11, 7, vgx4], { z28.h - z31.h }, z15.h[7]"
+
+  -
+    input:
+      bytes: [ 0x9f, 0xff, 0x1f, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w11, 7, vgx4], { z28.h - z31.h }, z15.h[7]"
+
+  -
+    input:
+      bytes: [ 0x15, 0x9e, 0x10, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w8, 5, vgx4], { z16.h - z19.h }, z0.h[6]"
+
+  -
+    input:
+      bytes: [ 0x15, 0x9e, 0x10, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w8, 5, vgx4], { z16.h - z19.h }, z0.h[6]"
+
+  -
+    input:
+      bytes: [ 0x11, 0x94, 0x1e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w8, 1, vgx4], { z0.h - z3.h }, z14.h[2]"
+
+  -
+    input:
+      bytes: [ 0x11, 0x94, 0x1e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w8, 1, vgx4], { z0.h - z3.h }, z14.h[2]"
+
+  -
+    input:
+      bytes: [ 0x18, 0xd6, 0x14, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w10, 0, vgx4], { z16.h - z19.h }, z4.h[3]"
+
+  -
+    input:
+      bytes: [ 0x18, 0xd6, 0x14, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w10, 0, vgx4], { z16.h - z19.h }, z4.h[3]"
+
+  -
+    input:
+      bytes: [ 0x90, 0x99, 0x12, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w8, 0, vgx4], { z12.h - z15.h }, z2.h[4]"
+
+  -
+    input:
+      bytes: [ 0x90, 0x99, 0x12, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w8, 0, vgx4], { z12.h - z15.h }, z2.h[4]"
+
+  -
+    input:
+      bytes: [ 0x11, 0xd8, 0x1a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w10, 1, vgx4], { z0.h - z3.h }, z10.h[4]"
+
+  -
+    input:
+      bytes: [ 0x11, 0xd8, 0x1a, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w10, 1, vgx4], { z0.h - z3.h }, z10.h[4]"
+
+  -
+    input:
+      bytes: [ 0x9d, 0x9a, 0x1e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w8, 5, vgx4], { z20.h - z23.h }, z14.h[5]"
+
+  -
+    input:
+      bytes: [ 0x9d, 0x9a, 0x1e, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w8, 5, vgx4], { z20.h - z23.h }, z14.h[5]"
+
+  -
+    input:
+      bytes: [ 0x12, 0xf5, 0x11, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w11, 2, vgx4], { z8.h - z11.h }, z1.h[2]"
+
+  -
+    input:
+      bytes: [ 0x12, 0xf5, 0x11, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w11, 2, vgx4], { z8.h - z11.h }, z1.h[2]"
+
+  -
+    input:
+      bytes: [ 0x97, 0xb9, 0x1b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w9, 7, vgx4], { z12.h - z15.h }, z11.h[4]"
+
+  -
+    input:
+      bytes: [ 0x97, 0xb9, 0x1b, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w9, 7, vgx4], { z12.h - z15.h }, z11.h[4]"
+
+  -
+    input:
+      bytes: [ 0x18, 0x10, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w8, 0, vgx4], { z0.h - z3.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x18, 0x10, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w8, 0, vgx4], { z0.h - z3.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x1d, 0x51, 0xb5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w10, 5, vgx4], { z8.h - z11.h }, { z20.h - z23.h }"
+
+  -
+    input:
+      bytes: [ 0x1d, 0x51, 0xb5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w10, 5, vgx4], { z8.h - z11.h }, { z20.h - z23.h }"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x71, 0xa9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w11, 7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x71, 0xa9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w11, 7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x73, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w11, 7, vgx4], { z28.h - z31.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x73, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w11, 7, vgx4], { z28.h - z31.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x1d, 0x12, 0xb1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w8, 5, vgx4], { z16.h - z19.h }, { z16.h - z19.h }"
+
+  -
+    input:
+      bytes: [ 0x1d, 0x12, 0xb1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w8, 5, vgx4], { z16.h - z19.h }, { z16.h - z19.h }"
+
+  -
+    input:
+      bytes: [ 0x19, 0x10, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w8, 1, vgx4], { z0.h - z3.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x19, 0x10, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w8, 1, vgx4], { z0.h - z3.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x18, 0x52, 0xb5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w10, 0, vgx4], { z16.h - z19.h }, { z20.h - z23.h }"
+
+  -
+    input:
+      bytes: [ 0x18, 0x52, 0xb5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w10, 0, vgx4], { z16.h - z19.h }, { z20.h - z23.h }"
+
+  -
+    input:
+      bytes: [ 0x98, 0x11, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w8, 0, vgx4], { z12.h - z15.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x98, 0x11, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w8, 0, vgx4], { z12.h - z15.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x19, 0x50, 0xb9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w10, 1, vgx4], { z0.h - z3.h }, { z24.h - z27.h }"
+
+  -
+    input:
+      bytes: [ 0x19, 0x50, 0xb9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w10, 1, vgx4], { z0.h - z3.h }, { z24.h - z27.h }"
+
+  -
+    input:
+      bytes: [ 0x9d, 0x12, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w8, 5, vgx4], { z20.h - z23.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x9d, 0x12, 0xbd, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w8, 5, vgx4], { z20.h - z23.h }, { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x1a, 0x71, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w11, 2, vgx4], { z8.h - z11.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x1a, 0x71, 0xa1, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w11, 2, vgx4], { z8.h - z11.h }, { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x31, 0xa9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w9, 7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x31, 0xa9, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls za.h[w9, 7, vgx4], { z12.h - z15.h }, { z8.h - z11.h }"
diff --git a/tests/MC/AArch64/SME2p1/fmopa.s.yaml b/tests/MC/AArch64/SME2p1/fmopa.s.yaml
new file mode 100644
index 000000000..b3b47b7f1
--- /dev/null
+++ b/tests/MC/AArch64/SME2p1/fmopa.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x08, 0x00, 0x80, 0x81 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmopa za0.h, p0/m, p0/m, z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x49, 0x55, 0x95, 0x81 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmopa za1.h, p5/m, p2/m, z10.h, z21.h"
+
+  -
+    input:
+      bytes: [ 0xa9, 0xed, 0x88, 0x81 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmopa za1.h, p3/m, p7/m, z13.h, z8.h"
+
+  -
+    input:
+      bytes: [ 0xe9, 0xff, 0x9f, 0x81 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmopa za1.h, p7/m, p7/m, z31.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x29, 0x0e, 0x90, 0x81 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmopa za1.h, p3/m, p0/m, z17.h, z16.h"
+
+  -
+    input:
+      bytes: [ 0x29, 0x84, 0x9e, 0x81 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmopa za1.h, p1/m, p4/m, z1.h, z30.h"
+
+  -
+    input:
+      bytes: [ 0x68, 0x56, 0x94, 0x81 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmopa za0.h, p5/m, p2/m, z19.h, z20.h"
+
+  -
+    input:
+      bytes: [ 0x88, 0x19, 0x82, 0x81 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmopa za0.h, p6/m, p0/m, z12.h, z2.h"
+
+  -
+    input:
+      bytes: [ 0x29, 0xc8, 0x9a, 0x81 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmopa za1.h, p2/m, p6/m, z1.h, z26.h"
+
+  -
+    input:
+      bytes: [ 0xc9, 0x0a, 0x9e, 0x81 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmopa za1.h, p2/m, p0/m, z22.h, z30.h"
+
+  -
+    input:
+      bytes: [ 0x28, 0xf5, 0x81, 0x81 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmopa za0.h, p5/m, p7/m, z9.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0x89, 0xa9, 0x8b, 0x81 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmopa za1.h, p2/m, p5/m, z12.h, z11.h"
diff --git a/tests/MC/AArch64/SME2p1/fmops.s.yaml b/tests/MC/AArch64/SME2p1/fmops.s.yaml
new file mode 100644
index 000000000..2c1f8f83a
--- /dev/null
+++ b/tests/MC/AArch64/SME2p1/fmops.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x18, 0x00, 0x80, 0x81 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmops za0.h, p0/m, p0/m, z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x59, 0x55, 0x95, 0x81 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmops za1.h, p5/m, p2/m, z10.h, z21.h"
+
+  -
+    input:
+      bytes: [ 0xb9, 0xed, 0x88, 0x81 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmops za1.h, p3/m, p7/m, z13.h, z8.h"
+
+  -
+    input:
+      bytes: [ 0xf9, 0xff, 0x9f, 0x81 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmops za1.h, p7/m, p7/m, z31.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x39, 0x0e, 0x90, 0x81 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmops za1.h, p3/m, p0/m, z17.h, z16.h"
+
+  -
+    input:
+      bytes: [ 0x39, 0x84, 0x9e, 0x81 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmops za1.h, p1/m, p4/m, z1.h, z30.h"
+
+  -
+    input:
+      bytes: [ 0x78, 0x56, 0x94, 0x81 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmops za0.h, p5/m, p2/m, z19.h, z20.h"
+
+  -
+    input:
+      bytes: [ 0x98, 0x19, 0x82, 0x81 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmops za0.h, p6/m, p0/m, z12.h, z2.h"
+
+  -
+    input:
+      bytes: [ 0x39, 0xc8, 0x9a, 0x81 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmops za1.h, p2/m, p6/m, z1.h, z26.h"
+
+  -
+    input:
+      bytes: [ 0xd9, 0x0a, 0x9e, 0x81 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmops za1.h, p2/m, p0/m, z22.h, z30.h"
+
+  -
+    input:
+      bytes: [ 0x38, 0xf5, 0x81, 0x81 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmops za0.h, p5/m, p7/m, z9.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0x99, 0xa9, 0x8b, 0x81 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmops za1.h, p2/m, p5/m, z12.h, z11.h"
diff --git a/tests/MC/AArch64/SME2p1/fsub.s.yaml b/tests/MC/AArch64/SME2p1/fsub.s.yaml
new file mode 100644
index 000000000..a9ee6d650
--- /dev/null
+++ b/tests/MC/AArch64/SME2p1/fsub.s.yaml
@@ -0,0 +1,470 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x08, 0x1c, 0xa4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.h[w8, 0, vgx2], { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x4d, 0x5d, 0xa4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.h[w10, 5, vgx2], { z10.h, z11.h }"
+
+  -
+    input:
+      bytes: [ 0x4d, 0x5d, 0xa4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.h[w10, 5, vgx2], { z10.h, z11.h }"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x7d, 0xa4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.h[w11, 7, vgx2], { z12.h, z13.h }"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x7d, 0xa4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.h[w11, 7, vgx2], { z12.h, z13.h }"
+
+  -
+    input:
+      bytes: [ 0xcf, 0x7f, 0xa4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.h[w11, 7, vgx2], { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0xcf, 0x7f, 0xa4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.h[w11, 7, vgx2], { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0x0d, 0x1e, 0xa4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.h[w8, 5, vgx2], { z16.h, z17.h }"
+
+  -
+    input:
+      bytes: [ 0x0d, 0x1e, 0xa4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.h[w8, 5, vgx2], { z16.h, z17.h }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x1c, 0xa4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.h[w8, 1, vgx2], { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x1c, 0xa4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.h[w8, 1, vgx2], { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x48, 0x5e, 0xa4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.h[w10, 0, vgx2], { z18.h, z19.h }"
+
+  -
+    input:
+      bytes: [ 0x48, 0x5e, 0xa4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.h[w10, 0, vgx2], { z18.h, z19.h }"
+
+  -
+    input:
+      bytes: [ 0x88, 0x1d, 0xa4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.h[w8, 0, vgx2], { z12.h, z13.h }"
+
+  -
+    input:
+      bytes: [ 0x88, 0x1d, 0xa4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.h[w8, 0, vgx2], { z12.h, z13.h }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x5c, 0xa4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.h[w10, 1, vgx2], { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x5c, 0xa4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.h[w10, 1, vgx2], { z0.h, z1.h }"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x1e, 0xa4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.h[w8, 5, vgx2], { z22.h, z23.h }"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x1e, 0xa4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.h[w8, 5, vgx2], { z22.h, z23.h }"
+
+  -
+    input:
+      bytes: [ 0x0a, 0x7d, 0xa4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.h[w11, 2, vgx2], { z8.h, z9.h }"
+
+  -
+    input:
+      bytes: [ 0x0a, 0x7d, 0xa4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.h[w11, 2, vgx2], { z8.h, z9.h }"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x3d, 0xa4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.h[w9, 7, vgx2], { z12.h, z13.h }"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x3d, 0xa4, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.h[w9, 7, vgx2], { z12.h, z13.h }"
+
+  -
+    input:
+      bytes: [ 0x08, 0x1c, 0xa5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.h[w8, 0, vgx4], { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x08, 0x1c, 0xa5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.h[w8, 0, vgx4], { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x0d, 0x5d, 0xa5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.h[w10, 5, vgx4], { z8.h - z11.h }"
+
+  -
+    input:
+      bytes: [ 0x0d, 0x5d, 0xa5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.h[w10, 5, vgx4], { z8.h - z11.h }"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x7d, 0xa5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.h[w11, 7, vgx4], { z12.h - z15.h }"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x7d, 0xa5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.h[w11, 7, vgx4], { z12.h - z15.h }"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x7f, 0xa5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.h[w11, 7, vgx4], { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x7f, 0xa5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.h[w11, 7, vgx4], { z28.h - z31.h }"
+
+  -
+    input:
+      bytes: [ 0x0d, 0x1e, 0xa5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.h[w8, 5, vgx4], { z16.h - z19.h }"
+
+  -
+    input:
+      bytes: [ 0x0d, 0x1e, 0xa5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.h[w8, 5, vgx4], { z16.h - z19.h }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x1c, 0xa5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.h[w8, 1, vgx4], { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x1c, 0xa5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.h[w8, 1, vgx4], { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x08, 0x5e, 0xa5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.h[w10, 0, vgx4], { z16.h - z19.h }"
+
+  -
+    input:
+      bytes: [ 0x08, 0x5e, 0xa5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.h[w10, 0, vgx4], { z16.h - z19.h }"
+
+  -
+    input:
+      bytes: [ 0x88, 0x1d, 0xa5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.h[w8, 0, vgx4], { z12.h - z15.h }"
+
+  -
+    input:
+      bytes: [ 0x88, 0x1d, 0xa5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.h[w8, 0, vgx4], { z12.h - z15.h }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x5c, 0xa5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.h[w10, 1, vgx4], { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x09, 0x5c, 0xa5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.h[w10, 1, vgx4], { z0.h - z3.h }"
+
+  -
+    input:
+      bytes: [ 0x8d, 0x1e, 0xa5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.h[w8, 5, vgx4], { z20.h - z23.h }"
+
+  -
+    input:
+      bytes: [ 0x8d, 0x1e, 0xa5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.h[w8, 5, vgx4], { z20.h - z23.h }"
+
+  -
+    input:
+      bytes: [ 0x0a, 0x7d, 0xa5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.h[w11, 2, vgx4], { z8.h - z11.h }"
+
+  -
+    input:
+      bytes: [ 0x0a, 0x7d, 0xa5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.h[w11, 2, vgx4], { z8.h - z11.h }"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x3d, 0xa5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.h[w9, 7, vgx4], { z12.h - z15.h }"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x3d, 0xa5, 0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1", "+sme-f16f16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub za.h[w9, 7, vgx4], { z12.h - z15.h }"
diff --git a/tests/MC/AArch64/SME2p1/luti2.s.yaml b/tests/MC/AArch64/SME2p1/luti2.s.yaml
new file mode 100644
index 000000000..f854edde0
--- /dev/null
+++ b/tests/MC/AArch64/SME2p1/luti2.s.yaml
@@ -0,0 +1,160 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x50, 0x9c, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti2 { z0.h, z8.h }, zt0, z0[0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x51, 0x9d, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti2 { z21.h, z29.h }, zt0, z10[2]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xd1, 0x9c, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti2 { z23.h, z31.h }, zt0, z13[1]"
+
+  -
+    input:
+      bytes: [ 0xf7, 0xd3, 0x9f, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti2 { z23.h, z31.h }, zt0, z31[7]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0x9c, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti2 { z0.b, z8.b }, zt0, z0[0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x41, 0x9d, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti2 { z21.b, z29.b }, zt0, z10[2]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xc1, 0x9c, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti2 { z23.b, z31.b }, zt0, z13[1]"
+
+  -
+    input:
+      bytes: [ 0xf7, 0xc3, 0x9f, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti2 { z23.b, z31.b }, zt0, z31[7]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x90, 0x9c, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti2 { z0.h, z4.h, z8.h, z12.h }, zt0, z0[0]"
+
+  -
+    input:
+      bytes: [ 0x51, 0x91, 0x9d, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti2 { z17.h, z21.h, z25.h, z29.h }, zt0, z10[1]"
+
+  -
+    input:
+      bytes: [ 0xb3, 0x91, 0x9c, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti2 { z19.h, z23.h, z27.h, z31.h }, zt0, z13[0]"
+
+  -
+    input:
+      bytes: [ 0xf3, 0x93, 0x9f, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti2 { z19.h, z23.h, z27.h, z31.h }, zt0, z31[3]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x9c, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti2 { z0.b, z4.b, z8.b, z12.b }, zt0, z0[0]"
+
+  -
+    input:
+      bytes: [ 0x51, 0x81, 0x9d, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti2 { z17.b, z21.b, z25.b, z29.b }, zt0, z10[1]"
+
+  -
+    input:
+      bytes: [ 0xb3, 0x81, 0x9c, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti2 { z19.b, z23.b, z27.b, z31.b }, zt0, z13[0]"
+
+  -
+    input:
+      bytes: [ 0xf3, 0x83, 0x9f, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti2 { z19.b, z23.b, z27.b, z31.b }, zt0, z31[3]"
diff --git a/tests/MC/AArch64/SME2p1/luti4.s.yaml b/tests/MC/AArch64/SME2p1/luti4.s.yaml
new file mode 100644
index 000000000..54c039688
--- /dev/null
+++ b/tests/MC/AArch64/SME2p1/luti4.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x50, 0x9a, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti4 { z0.h, z8.h }, zt0, z0[0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x51, 0x9b, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti4 { z21.h, z29.h }, zt0, z10[2]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xd1, 0x9a, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti4 { z23.h, z31.h }, zt0, z13[1]"
+
+  -
+    input:
+      bytes: [ 0xf7, 0xd3, 0x9b, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti4 { z23.h, z31.h }, zt0, z31[3]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0x9a, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti4 { z0.b, z8.b }, zt0, z0[0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x41, 0x9b, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti4 { z21.b, z29.b }, zt0, z10[2]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xc1, 0x9a, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti4 { z23.b, z31.b }, zt0, z13[1]"
+
+  -
+    input:
+      bytes: [ 0xf7, 0xc3, 0x9b, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti4 { z23.b, z31.b }, zt0, z31[3]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x90, 0x9a, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti4 { z0.h, z4.h, z8.h, z12.h }, zt0, z0[0]"
+
+  -
+    input:
+      bytes: [ 0x51, 0x91, 0x9b, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti4 { z17.h, z21.h, z25.h, z29.h }, zt0, z10[1]"
+
+  -
+    input:
+      bytes: [ 0xb3, 0x91, 0x9a, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti4 { z19.h, z23.h, z27.h, z31.h }, zt0, z13[0]"
+
+  -
+    input:
+      bytes: [ 0xf3, 0x93, 0x9b, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "luti4 { z19.h, z23.h, z27.h, z31.h }, zt0, z31[1]"
diff --git a/tests/MC/AArch64/SME2p1/movaz.s.yaml b/tests/MC/AArch64/SME2p1/movaz.s.yaml
new file mode 100644
index 000000000..58e85d561
--- /dev/null
+++ b/tests/MC/AArch64/SME2p1/movaz.s.yaml
@@ -0,0 +1,1680 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x0a, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz { z0.d, z1.d }, za.d[w8, 0, vgx2]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x0a, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz { z0.d, z1.d }, za.d[w8, 0, vgx2]"
+
+  -
+    input:
+      bytes: [ 0x54, 0x4a, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz { z20.d, z21.d }, za.d[w10, 2, vgx2]"
+
+  -
+    input:
+      bytes: [ 0x54, 0x4a, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz { z20.d, z21.d }, za.d[w10, 2, vgx2]"
+
+  -
+    input:
+      bytes: [ 0xb6, 0x6a, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz { z22.d, z23.d }, za.d[w11, 5, vgx2]"
+
+  -
+    input:
+      bytes: [ 0xb6, 0x6a, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz { z22.d, z23.d }, za.d[w11, 5, vgx2]"
+
+  -
+    input:
+      bytes: [ 0xfe, 0x6a, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz { z30.d, z31.d }, za.d[w11, 7, vgx2]"
+
+  -
+    input:
+      bytes: [ 0xfe, 0x6a, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz { z30.d, z31.d }, za.d[w11, 7, vgx2]"
+
+  -
+    input:
+      bytes: [ 0x24, 0x0a, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz { z4.d, z5.d }, za.d[w8, 1, vgx2]"
+
+  -
+    input:
+      bytes: [ 0x24, 0x0a, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz { z4.d, z5.d }, za.d[w8, 1, vgx2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x0a, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz { z0.d, z1.d }, za.d[w8, 1, vgx2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x0a, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz { z0.d, z1.d }, za.d[w8, 1, vgx2]"
+
+  -
+    input:
+      bytes: [ 0x78, 0x4a, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz { z24.d, z25.d }, za.d[w10, 3, vgx2]"
+
+  -
+    input:
+      bytes: [ 0x78, 0x4a, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz { z24.d, z25.d }, za.d[w10, 3, vgx2]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x0a, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz { z0.d, z1.d }, za.d[w8, 4, vgx2]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x0a, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz { z0.d, z1.d }, za.d[w8, 4, vgx2]"
+
+  -
+    input:
+      bytes: [ 0x30, 0x4a, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz { z16.d, z17.d }, za.d[w10, 1, vgx2]"
+
+  -
+    input:
+      bytes: [ 0x30, 0x4a, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz { z16.d, z17.d }, za.d[w10, 1, vgx2]"
+
+  -
+    input:
+      bytes: [ 0xdc, 0x0a, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz { z28.d, z29.d }, za.d[w8, 6, vgx2]"
+
+  -
+    input:
+      bytes: [ 0xdc, 0x0a, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz { z28.d, z29.d }, za.d[w8, 6, vgx2]"
+
+  -
+    input:
+      bytes: [ 0x22, 0x6a, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz { z2.d, z3.d }, za.d[w11, 1, vgx2]"
+
+  -
+    input:
+      bytes: [ 0x22, 0x6a, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz { z2.d, z3.d }, za.d[w11, 1, vgx2]"
+
+  -
+    input:
+      bytes: [ 0x86, 0x2a, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz { z6.d, z7.d }, za.d[w9, 4, vgx2]"
+
+  -
+    input:
+      bytes: [ 0x86, 0x2a, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz { z6.d, z7.d }, za.d[w9, 4, vgx2]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x0e, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz { z0.d - z3.d }, za.d[w8, 0, vgx4]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x0e, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz { z0.d - z3.d }, za.d[w8, 0, vgx4]"
+
+  -
+    input:
+      bytes: [ 0x54, 0x4e, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz { z20.d - z23.d }, za.d[w10, 2, vgx4]"
+
+  -
+    input:
+      bytes: [ 0x54, 0x4e, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz { z20.d - z23.d }, za.d[w10, 2, vgx4]"
+
+  -
+    input:
+      bytes: [ 0xb4, 0x6e, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz { z20.d - z23.d }, za.d[w11, 5, vgx4]"
+
+  -
+    input:
+      bytes: [ 0xb4, 0x6e, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz { z20.d - z23.d }, za.d[w11, 5, vgx4]"
+
+  -
+    input:
+      bytes: [ 0xfc, 0x6e, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz { z28.d - z31.d }, za.d[w11, 7, vgx4]"
+
+  -
+    input:
+      bytes: [ 0xfc, 0x6e, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz { z28.d - z31.d }, za.d[w11, 7, vgx4]"
+
+  -
+    input:
+      bytes: [ 0x24, 0x0e, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz { z4.d - z7.d }, za.d[w8, 1, vgx4]"
+
+  -
+    input:
+      bytes: [ 0x24, 0x0e, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz { z4.d - z7.d }, za.d[w8, 1, vgx4]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x0e, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz { z0.d - z3.d }, za.d[w8, 1, vgx4]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x0e, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz { z0.d - z3.d }, za.d[w8, 1, vgx4]"
+
+  -
+    input:
+      bytes: [ 0x78, 0x4e, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz { z24.d - z27.d }, za.d[w10, 3, vgx4]"
+
+  -
+    input:
+      bytes: [ 0x78, 0x4e, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz { z24.d - z27.d }, za.d[w10, 3, vgx4]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x0e, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz { z0.d - z3.d }, za.d[w8, 4, vgx4]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x0e, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz { z0.d - z3.d }, za.d[w8, 4, vgx4]"
+
+  -
+    input:
+      bytes: [ 0x30, 0x4e, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz { z16.d - z19.d }, za.d[w10, 1, vgx4]"
+
+  -
+    input:
+      bytes: [ 0x30, 0x4e, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz { z16.d - z19.d }, za.d[w10, 1, vgx4]"
+
+  -
+    input:
+      bytes: [ 0xdc, 0x0e, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz { z28.d - z31.d }, za.d[w8, 6, vgx4]"
+
+  -
+    input:
+      bytes: [ 0xdc, 0x0e, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz { z28.d - z31.d }, za.d[w8, 6, vgx4]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x6e, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz { z0.d - z3.d }, za.d[w11, 1, vgx4]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x6e, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz { z0.d - z3.d }, za.d[w11, 1, vgx4]"
+
+  -
+    input:
+      bytes: [ 0x84, 0x2e, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz { z4.d - z7.d }, za.d[w9, 4, vgx4]"
+
+  -
+    input:
+      bytes: [ 0x84, 0x2e, 0x06, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz { z4.d - z7.d }, za.d[w9, 4, vgx4]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x02, 0xc3, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z0.q, za0h.q[w12, 0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x43, 0xc3, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z21.q, za10h.q[w14, 0]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x63, 0xc3, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z23.q, za13h.q[w15, 0]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x63, 0xc3, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z31.q, za15h.q[w15, 0]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x02, 0xc3, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z5.q, za1h.q[w12, 0]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x02, 0xc3, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z1.q, za1h.q[w12, 0]"
+
+  -
+    input:
+      bytes: [ 0x78, 0x42, 0xc3, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z24.q, za3h.q[w14, 0]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x03, 0xc3, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z0.q, za12h.q[w12, 0]"
+
+  -
+    input:
+      bytes: [ 0x31, 0x42, 0xc3, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z17.q, za1h.q[w14, 0]"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x02, 0xc3, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z29.q, za6h.q[w12, 0]"
+
+  -
+    input:
+      bytes: [ 0x22, 0x63, 0xc3, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z2.q, za9h.q[w15, 0]"
+
+  -
+    input:
+      bytes: [ 0x87, 0x23, 0xc3, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z7.q, za12h.q[w13, 0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x82, 0xc3, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z0.q, za0v.q[w12, 0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xc3, 0xc3, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z21.q, za10v.q[w14, 0]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xe3, 0xc3, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z23.q, za13v.q[w15, 0]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xe3, 0xc3, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z31.q, za15v.q[w15, 0]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x82, 0xc3, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z5.q, za1v.q[w12, 0]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x82, 0xc3, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z1.q, za1v.q[w12, 0]"
+
+  -
+    input:
+      bytes: [ 0x78, 0xc2, 0xc3, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z24.q, za3v.q[w14, 0]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x83, 0xc3, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z0.q, za12v.q[w12, 0]"
+
+  -
+    input:
+      bytes: [ 0x31, 0xc2, 0xc3, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z17.q, za1v.q[w14, 0]"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x82, 0xc3, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z29.q, za6v.q[w12, 0]"
+
+  -
+    input:
+      bytes: [ 0x22, 0xe3, 0xc3, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z2.q, za9v.q[w15, 0]"
+
+  -
+    input:
+      bytes: [ 0x87, 0xa3, 0xc3, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z7.q, za12v.q[w13, 0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x02, 0x42, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z0.h, za0h.h[w12, 0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x43, 0x42, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z21.h, za1h.h[w14, 2]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x63, 0x42, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z23.h, za1h.h[w15, 5]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x63, 0x42, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z31.h, za1h.h[w15, 7]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x02, 0x42, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z5.h, za0h.h[w12, 1]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x02, 0x42, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z1.h, za0h.h[w12, 1]"
+
+  -
+    input:
+      bytes: [ 0x78, 0x42, 0x42, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z24.h, za0h.h[w14, 3]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x03, 0x42, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z0.h, za1h.h[w12, 4]"
+
+  -
+    input:
+      bytes: [ 0x31, 0x42, 0x42, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z17.h, za0h.h[w14, 1]"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x02, 0x42, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z29.h, za0h.h[w12, 6]"
+
+  -
+    input:
+      bytes: [ 0x22, 0x63, 0x42, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z2.h, za1h.h[w15, 1]"
+
+  -
+    input:
+      bytes: [ 0x87, 0x23, 0x42, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z7.h, za1h.h[w13, 4]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x82, 0x42, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z0.h, za0v.h[w12, 0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xc3, 0x42, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z21.h, za1v.h[w14, 2]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xe3, 0x42, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z23.h, za1v.h[w15, 5]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xe3, 0x42, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z31.h, za1v.h[w15, 7]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x82, 0x42, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z5.h, za0v.h[w12, 1]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x82, 0x42, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z1.h, za0v.h[w12, 1]"
+
+  -
+    input:
+      bytes: [ 0x78, 0xc2, 0x42, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z24.h, za0v.h[w14, 3]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x83, 0x42, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z0.h, za1v.h[w12, 4]"
+
+  -
+    input:
+      bytes: [ 0x31, 0xc2, 0x42, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z17.h, za0v.h[w14, 1]"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x82, 0x42, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z29.h, za0v.h[w12, 6]"
+
+  -
+    input:
+      bytes: [ 0x22, 0xe3, 0x42, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z2.h, za1v.h[w15, 1]"
+
+  -
+    input:
+      bytes: [ 0x87, 0xa3, 0x42, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z7.h, za1v.h[w13, 4]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x02, 0x82, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z0.s, za0h.s[w12, 0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x43, 0x82, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z21.s, za2h.s[w14, 2]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x63, 0x82, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z23.s, za3h.s[w15, 1]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x63, 0x82, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z31.s, za3h.s[w15, 3]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x02, 0x82, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z5.s, za0h.s[w12, 1]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x02, 0x82, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z1.s, za0h.s[w12, 1]"
+
+  -
+    input:
+      bytes: [ 0x78, 0x42, 0x82, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z24.s, za0h.s[w14, 3]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x03, 0x82, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z0.s, za3h.s[w12, 0]"
+
+  -
+    input:
+      bytes: [ 0x31, 0x42, 0x82, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z17.s, za0h.s[w14, 1]"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x02, 0x82, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z29.s, za1h.s[w12, 2]"
+
+  -
+    input:
+      bytes: [ 0x22, 0x63, 0x82, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z2.s, za2h.s[w15, 1]"
+
+  -
+    input:
+      bytes: [ 0x87, 0x23, 0x82, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z7.s, za3h.s[w13, 0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x82, 0x82, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z0.s, za0v.s[w12, 0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xc3, 0x82, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z21.s, za2v.s[w14, 2]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xe3, 0x82, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z23.s, za3v.s[w15, 1]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xe3, 0x82, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z31.s, za3v.s[w15, 3]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x82, 0x82, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z5.s, za0v.s[w12, 1]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x82, 0x82, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z1.s, za0v.s[w12, 1]"
+
+  -
+    input:
+      bytes: [ 0x78, 0xc2, 0x82, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z24.s, za0v.s[w14, 3]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x83, 0x82, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z0.s, za3v.s[w12, 0]"
+
+  -
+    input:
+      bytes: [ 0x31, 0xc2, 0x82, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z17.s, za0v.s[w14, 1]"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x82, 0x82, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z29.s, za1v.s[w12, 2]"
+
+  -
+    input:
+      bytes: [ 0x22, 0xe3, 0x82, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z2.s, za2v.s[w15, 1]"
+
+  -
+    input:
+      bytes: [ 0x87, 0xa3, 0x82, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z7.s, za3v.s[w13, 0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x02, 0xc2, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z0.d, za0h.d[w12, 0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x43, 0xc2, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z21.d, za5h.d[w14, 0]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x63, 0xc2, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z23.d, za6h.d[w15, 1]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x63, 0xc2, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z31.d, za7h.d[w15, 1]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x02, 0xc2, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z5.d, za0h.d[w12, 1]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x02, 0xc2, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z1.d, za0h.d[w12, 1]"
+
+  -
+    input:
+      bytes: [ 0x78, 0x42, 0xc2, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z24.d, za1h.d[w14, 1]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x03, 0xc2, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z0.d, za6h.d[w12, 0]"
+
+  -
+    input:
+      bytes: [ 0x31, 0x42, 0xc2, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z17.d, za0h.d[w14, 1]"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x02, 0xc2, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z29.d, za3h.d[w12, 0]"
+
+  -
+    input:
+      bytes: [ 0x22, 0x63, 0xc2, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z2.d, za4h.d[w15, 1]"
+
+  -
+    input:
+      bytes: [ 0x87, 0x23, 0xc2, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z7.d, za6h.d[w13, 0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x82, 0xc2, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z0.d, za0v.d[w12, 0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xc3, 0xc2, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z21.d, za5v.d[w14, 0]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xe3, 0xc2, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z23.d, za6v.d[w15, 1]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xe3, 0xc2, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z31.d, za7v.d[w15, 1]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x82, 0xc2, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z5.d, za0v.d[w12, 1]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x82, 0xc2, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z1.d, za0v.d[w12, 1]"
+
+  -
+    input:
+      bytes: [ 0x78, 0xc2, 0xc2, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z24.d, za1v.d[w14, 1]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x83, 0xc2, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z0.d, za6v.d[w12, 0]"
+
+  -
+    input:
+      bytes: [ 0x31, 0xc2, 0xc2, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z17.d, za0v.d[w14, 1]"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x82, 0xc2, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z29.d, za3v.d[w12, 0]"
+
+  -
+    input:
+      bytes: [ 0x22, 0xe3, 0xc2, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z2.d, za4v.d[w15, 1]"
+
+  -
+    input:
+      bytes: [ 0x87, 0xa3, 0xc2, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z7.d, za6v.d[w13, 0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x02, 0x02, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z0.b, za0h.b[w12, 0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x43, 0x02, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z21.b, za0h.b[w14, 10]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x63, 0x02, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z23.b, za0h.b[w15, 13]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x63, 0x02, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z31.b, za0h.b[w15, 15]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x02, 0x02, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z5.b, za0h.b[w12, 1]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x02, 0x02, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z1.b, za0h.b[w12, 1]"
+
+  -
+    input:
+      bytes: [ 0x78, 0x42, 0x02, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z24.b, za0h.b[w14, 3]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x03, 0x02, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z0.b, za0h.b[w12, 12]"
+
+  -
+    input:
+      bytes: [ 0x31, 0x42, 0x02, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z17.b, za0h.b[w14, 1]"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x02, 0x02, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z29.b, za0h.b[w12, 6]"
+
+  -
+    input:
+      bytes: [ 0x22, 0x63, 0x02, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z2.b, za0h.b[w15, 9]"
+
+  -
+    input:
+      bytes: [ 0x87, 0x23, 0x02, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z7.b, za0h.b[w13, 12]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x82, 0x02, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z0.b, za0v.b[w12, 0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xc3, 0x02, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z21.b, za0v.b[w14, 10]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xe3, 0x02, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z23.b, za0v.b[w15, 13]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xe3, 0x02, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z31.b, za0v.b[w15, 15]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x82, 0x02, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z5.b, za0v.b[w12, 1]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x82, 0x02, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z1.b, za0v.b[w12, 1]"
+
+  -
+    input:
+      bytes: [ 0x78, 0xc2, 0x02, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z24.b, za0v.b[w14, 3]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x83, 0x02, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z0.b, za0v.b[w12, 12]"
+
+  -
+    input:
+      bytes: [ 0x31, 0xc2, 0x02, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z17.b, za0v.b[w14, 1]"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x82, 0x02, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z29.b, za0v.b[w12, 6]"
+
+  -
+    input:
+      bytes: [ 0x22, 0xe3, 0x02, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z2.b, za0v.b[w15, 9]"
+
+  -
+    input:
+      bytes: [ 0x87, 0xa3, 0x02, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movaz z7.b, za0v.b[w13, 12]"
diff --git a/tests/MC/AArch64/SME2p1/zero.s.yaml b/tests/MC/AArch64/SME2p1/zero.s.yaml
new file mode 100644
index 000000000..72e49e717
--- /dev/null
+++ b/tests/MC/AArch64/SME2p1/zero.s.yaml
@@ -0,0 +1,620 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x0c, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zero za.d[w8, 0:1]"
+
+  -
+    input:
+      bytes: [ 0x05, 0xc0, 0x0c, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zero za.d[w10, 10:11]"
+
+  -
+    input:
+      bytes: [ 0x07, 0xe0, 0x0c, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zero za.d[w11, 14:15]"
+
+  -
+    input:
+      bytes: [ 0x05, 0x80, 0x0c, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zero za.d[w8, 10:11]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x80, 0x0c, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zero za.d[w8, 2:3]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x0c, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zero za.d[w10, 0:1]"
+
+  -
+    input:
+      bytes: [ 0x01, 0xc0, 0x0c, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zero za.d[w10, 2:3]"
+
+  -
+    input:
+      bytes: [ 0x02, 0xe0, 0x0c, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zero za.d[w11, 4:5]"
+
+  -
+    input:
+      bytes: [ 0x07, 0xa0, 0x0c, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zero za.d[w9, 14:15]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x0e, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zero za.d[w8, 0:3]"
+
+  -
+    input:
+      bytes: [ 0x01, 0xc0, 0x0e, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zero za.d[w10, 4:7]"
+
+  -
+    input:
+      bytes: [ 0x03, 0xe0, 0x0e, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zero za.d[w11, 12:15]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x80, 0x0e, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zero za.d[w8, 4:7]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x0e, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zero za.d[w10, 0:3]"
+
+  -
+    input:
+      bytes: [ 0x02, 0xe0, 0x0e, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zero za.d[w11, 8:11]"
+
+  -
+    input:
+      bytes: [ 0x03, 0xa0, 0x0e, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zero za.d[w9, 12:15]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x0c, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zero za.d[w8, 0, vgx2]"
+
+  -
+    input:
+      bytes: [ 0x05, 0x40, 0x0c, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zero za.d[w10, 5, vgx2]"
+
+  -
+    input:
+      bytes: [ 0x07, 0x60, 0x0c, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zero za.d[w11, 7, vgx2]"
+
+  -
+    input:
+      bytes: [ 0x05, 0x00, 0x0c, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zero za.d[w8, 5, vgx2]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0x0c, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zero za.d[w8, 1, vgx2]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0x0c, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zero za.d[w10, 0, vgx2]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x40, 0x0c, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zero za.d[w10, 1, vgx2]"
+
+  -
+    input:
+      bytes: [ 0x02, 0x60, 0x0c, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zero za.d[w11, 2, vgx2]"
+
+  -
+    input:
+      bytes: [ 0x07, 0x20, 0x0c, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zero za.d[w9, 7, vgx2]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x0d, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zero za.d[w8, 0:1, vgx2]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x40, 0x0d, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zero za.d[w10, 2:3, vgx2]"
+
+  -
+    input:
+      bytes: [ 0x03, 0x60, 0x0d, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zero za.d[w11, 6:7, vgx2]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0x0d, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zero za.d[w8, 2:3, vgx2]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0x0d, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zero za.d[w10, 0:1, vgx2]"
+
+  -
+    input:
+      bytes: [ 0x02, 0x60, 0x0d, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zero za.d[w11, 4:5, vgx2]"
+
+  -
+    input:
+      bytes: [ 0x03, 0x20, 0x0d, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zero za.d[w9, 6:7, vgx2]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x0f, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zero za.d[w8, 0:3, vgx2]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x40, 0x0f, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zero za.d[w10, 4:7, vgx2]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x60, 0x0f, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zero za.d[w11, 4:7, vgx2]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0x0f, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zero za.d[w8, 4:7, vgx2]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0x0f, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zero za.d[w10, 0:3, vgx2]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0x0f, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zero za.d[w11, 0:3, vgx2]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x20, 0x0f, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zero za.d[w9, 4:7, vgx2]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x0e, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zero za.d[w8, 0, vgx4]"
+
+  -
+    input:
+      bytes: [ 0x05, 0x40, 0x0e, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zero za.d[w10, 5, vgx4]"
+
+  -
+    input:
+      bytes: [ 0x07, 0x60, 0x0e, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zero za.d[w11, 7, vgx4]"
+
+  -
+    input:
+      bytes: [ 0x05, 0x00, 0x0e, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zero za.d[w8, 5, vgx4]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0x0e, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zero za.d[w8, 1, vgx4]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0x0e, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zero za.d[w10, 0, vgx4]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x40, 0x0e, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zero za.d[w10, 1, vgx4]"
+
+  -
+    input:
+      bytes: [ 0x02, 0x60, 0x0e, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zero za.d[w11, 2, vgx4]"
+
+  -
+    input:
+      bytes: [ 0x07, 0x20, 0x0e, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zero za.d[w9, 7, vgx4]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x0d, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zero za.d[w8, 0:1, vgx4]"
+
+  -
+    input:
+      bytes: [ 0x01, 0xc0, 0x0d, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zero za.d[w10, 2:3, vgx4]"
+
+  -
+    input:
+      bytes: [ 0x03, 0xe0, 0x0d, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zero za.d[w11, 6:7, vgx4]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x80, 0x0d, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zero za.d[w8, 2:3, vgx4]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x0d, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zero za.d[w10, 0:1, vgx4]"
+
+  -
+    input:
+      bytes: [ 0x02, 0xe0, 0x0d, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zero za.d[w11, 4:5, vgx4]"
+
+  -
+    input:
+      bytes: [ 0x03, 0xa0, 0x0d, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zero za.d[w9, 6:7, vgx4]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x0f, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zero za.d[w8, 0:3, vgx4]"
+
+  -
+    input:
+      bytes: [ 0x01, 0xc0, 0x0f, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zero za.d[w10, 4:7, vgx4]"
+
+  -
+    input:
+      bytes: [ 0x01, 0xe0, 0x0f, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zero za.d[w11, 4:7, vgx4]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x80, 0x0f, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zero za.d[w8, 4:7, vgx4]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x0f, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zero za.d[w10, 0:3, vgx4]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x0f, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zero za.d[w11, 0:3, vgx4]"
+
+  -
+    input:
+      bytes: [ 0x01, 0xa0, 0x0f, 0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zero za.d[w9, 4:7, vgx4]"
diff --git a/tests/MC/AArch64/SVE/abs.s.yaml b/tests/MC/AArch64/SVE/abs.s.yaml
new file mode 100644
index 000000000..37c56c133
--- /dev/null
+++ b/tests/MC/AArch64/SVE/abs.s.yaml
@@ -0,0 +1,240 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x16, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "abs z0.b, p0/m, z0.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x56, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "abs z0.h, p0/m, z0.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x96, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "abs z0.s, p0/m, z0.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xd6, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "abs z0.d, p0/m, z0.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x16, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "abs z31.b, p7/m, z31.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x56, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "abs z31.h, p7/m, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x96, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "abs z31.s, p7/m, z31.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0xd6, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "abs z31.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4.d, p7/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xbf, 0xd6, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "abs z4.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4, z6"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xbf, 0xd6, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "abs z4.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x16, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "abs z0.b, p0/m, z0.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x56, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "abs z0.h, p0/m, z0.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x96, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "abs z0.s, p0/m, z0.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xd6, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "abs z0.d, p0/m, z0.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x16, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "abs z31.b, p7/m, z31.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x56, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "abs z31.h, p7/m, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x96, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "abs z31.s, p7/m, z31.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0xd6, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "abs z31.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4.d, p7/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xbf, 0xd6, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "abs z4.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4, z6"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xbf, 0xd6, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "abs z4.d, p7/m, z31.d"
diff --git a/tests/MC/AArch64/SVE/add.s.yaml b/tests/MC/AArch64/SVE/add.s.yaml
new file mode 100644
index 000000000..6e8b3c61a
--- /dev/null
+++ b/tests/MC/AArch64/SVE/add.s.yaml
@@ -0,0 +1,1040 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xff, 0x03, 0xbf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "add z31.s, z31.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x01, 0xe8, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "add z23.d, z13.d, z8.d"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x0d, 0x00, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "add z23.b, p3/m, z23.b, z13.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "add z0.s, z0.s, z0.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0x03, 0xff, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "add z31.d, z31.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0x55, 0x01, 0x35, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "add z21.b, z10.b, z21.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x03, 0x3f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "add z31.b, z31.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x40, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "add z0.h, p0/m, z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "add z0.h, z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "add z0.b, p0/m, z0.b, z0.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x80, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "add z0.s, p0/m, z0.s, z0.s"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x01, 0x28, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "add z23.b, z13.b, z8.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "add z0.d, z0.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0xc0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "add z0.d, p0/m, z0.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0x03, 0x7f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "add z31.h, z31.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "add z0.b, z0.b, z0.b"
+
+  -
+    input:
+      bytes: [ 0x55, 0x01, 0xf5, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "add z21.d, z10.d, z21.d"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x0d, 0x40, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "add z23.h, p3/m, z23.h, z13.h"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x0d, 0x80, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "add z23.s, p3/m, z23.s, z13.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0x80, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "add z31.s, p7/m, z31.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x55, 0x01, 0x75, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "add z21.h, z10.h, z21.h"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x0d, 0xc0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "add z23.d, p3/m, z23.d, z13.d"
+
+  -
+    input:
+      bytes: [ 0x55, 0x15, 0xc0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "add z21.d, p5/m, z21.d, z10.d"
+
+  -
+    input:
+      bytes: [ 0x55, 0x15, 0x00, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "add z21.b, p5/m, z21.b, z10.b"
+
+  -
+    input:
+      bytes: [ 0x55, 0x01, 0xb5, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "add z21.s, z10.s, z21.s"
+
+  -
+    input:
+      bytes: [ 0x55, 0x15, 0x40, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "add z21.h, p5/m, z21.h, z10.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0x40, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "add z31.h, p7/m, z31.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x01, 0x68, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "add z23.h, z13.h, z8.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0xc0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "add z31.d, p7/m, z31.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0x55, 0x15, 0x80, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "add z21.s, p5/m, z21.s, z10.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0x00, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "add z31.b, p7/m, z31.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x01, 0xa8, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "add z23.s, z13.s, z8.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x20, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "add z0.b, z0.b, #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0xdf, 0x20, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "add z31.b, z31.b, #255"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x60, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "add z0.h, z0.h, #0"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x60, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "add z0.h, z0.h, #0, lsl #8"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0x60, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "add z31.h, z31.h, #65280"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0x60, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "add z31.h, z31.h, #65280"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0xa0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "add z0.s, z0.s, #0"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xa0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "add z0.s, z0.s, #0, lsl #8"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xa0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "add z31.s, z31.s, #65280"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xa0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "add z31.s, z31.s, #65280"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0xe0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "add z0.d, z0.d, #0"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xe0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "add z0.d, z0.d, #0, lsl #8"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xe0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "add z31.d, z31.d, #65280"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xe0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "add z31.d, z31.d, #65280"
+
+  -
+    input:
+      bytes: [ 0xc4, 0x3c, 0x10, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4.b, p7/z, z6.b"
+
+  -
+    input:
+      bytes: [ 0xe4, 0x1f, 0x00, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "add z4.b, p7/m, z4.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0xc4, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4, z6"
+
+  -
+    input:
+      bytes: [ 0xe4, 0x1f, 0x00, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "add z4.b, p7/m, z4.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xe0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "add z31.d, z31.d, #65280"
+
+  -
+    input:
+      bytes: [ 0xff, 0x03, 0xbf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "add z31.s, z31.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x01, 0xe8, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "add z23.d, z13.d, z8.d"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x0d, 0x00, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "add z23.b, p3/m, z23.b, z13.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "add z0.s, z0.s, z0.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0x03, 0xff, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "add z31.d, z31.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0x55, 0x01, 0x35, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "add z21.b, z10.b, z21.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x03, 0x3f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "add z31.b, z31.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x40, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "add z0.h, p0/m, z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "add z0.h, z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "add z0.b, p0/m, z0.b, z0.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x80, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "add z0.s, p0/m, z0.s, z0.s"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x01, 0x28, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "add z23.b, z13.b, z8.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "add z0.d, z0.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0xc0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "add z0.d, p0/m, z0.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0x03, 0x7f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "add z31.h, z31.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "add z0.b, z0.b, z0.b"
+
+  -
+    input:
+      bytes: [ 0x55, 0x01, 0xf5, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "add z21.d, z10.d, z21.d"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x0d, 0x40, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "add z23.h, p3/m, z23.h, z13.h"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x0d, 0x80, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "add z23.s, p3/m, z23.s, z13.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0x80, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "add z31.s, p7/m, z31.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x55, 0x01, 0x75, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "add z21.h, z10.h, z21.h"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x0d, 0xc0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "add z23.d, p3/m, z23.d, z13.d"
+
+  -
+    input:
+      bytes: [ 0x55, 0x15, 0xc0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "add z21.d, p5/m, z21.d, z10.d"
+
+  -
+    input:
+      bytes: [ 0x55, 0x15, 0x00, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "add z21.b, p5/m, z21.b, z10.b"
+
+  -
+    input:
+      bytes: [ 0x55, 0x01, 0xb5, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "add z21.s, z10.s, z21.s"
+
+  -
+    input:
+      bytes: [ 0x55, 0x15, 0x40, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "add z21.h, p5/m, z21.h, z10.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0x40, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "add z31.h, p7/m, z31.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x01, 0x68, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "add z23.h, z13.h, z8.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0xc0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "add z31.d, p7/m, z31.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0x55, 0x15, 0x80, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "add z21.s, p5/m, z21.s, z10.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0x00, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "add z31.b, p7/m, z31.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x01, 0xa8, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "add z23.s, z13.s, z8.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x20, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "add z0.b, z0.b, #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0xdf, 0x20, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "add z31.b, z31.b, #255"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x60, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "add z0.h, z0.h, #0"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x60, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "add z0.h, z0.h, #0, lsl #8"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0x60, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "add z31.h, z31.h, #65280"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0x60, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "add z31.h, z31.h, #65280"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0xa0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "add z0.s, z0.s, #0"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xa0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "add z0.s, z0.s, #0, lsl #8"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xa0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "add z31.s, z31.s, #65280"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xa0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "add z31.s, z31.s, #65280"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0xe0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "add z0.d, z0.d, #0"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xe0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "add z0.d, z0.d, #0, lsl #8"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xe0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "add z31.d, z31.d, #65280"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xe0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "add z31.d, z31.d, #65280"
+
+  -
+    input:
+      bytes: [ 0xc4, 0x3c, 0x10, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4.b, p7/z, z6.b"
+
+  -
+    input:
+      bytes: [ 0xe4, 0x1f, 0x00, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "add z4.b, p7/m, z4.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0xc4, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4, z6"
+
+  -
+    input:
+      bytes: [ 0xe4, 0x1f, 0x00, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "add z4.b, p7/m, z4.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xe0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "add z31.d, z31.d, #65280"
diff --git a/tests/MC/AArch64/SVE/addpl.s.yaml b/tests/MC/AArch64/SVE/addpl.s.yaml
new file mode 100644
index 000000000..413cec1fc
--- /dev/null
+++ b/tests/MC/AArch64/SVE/addpl.s.yaml
@@ -0,0 +1,80 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x15, 0x50, 0x75, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "addpl x21, x21, #0"
+
+  -
+    input:
+      bytes: [ 0xf7, 0x57, 0x68, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "addpl x23, x8, #-1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x53, 0x7f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "addpl sp, sp, #31"
+
+  -
+    input:
+      bytes: [ 0x00, 0x54, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "addpl x0, x0, #-32"
+
+  -
+    input:
+      bytes: [ 0x15, 0x50, 0x75, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "addpl x21, x21, #0"
+
+  -
+    input:
+      bytes: [ 0xf7, 0x57, 0x68, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "addpl x23, x8, #-1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x53, 0x7f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "addpl sp, sp, #31"
+
+  -
+    input:
+      bytes: [ 0x00, 0x54, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "addpl x0, x0, #-32"
diff --git a/tests/MC/AArch64/SVE/addvl.s.yaml b/tests/MC/AArch64/SVE/addvl.s.yaml
new file mode 100644
index 000000000..a3a1e6b01
--- /dev/null
+++ b/tests/MC/AArch64/SVE/addvl.s.yaml
@@ -0,0 +1,80 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x15, 0x50, 0x35, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "addvl x21, x21, #0"
+
+  -
+    input:
+      bytes: [ 0xf7, 0x57, 0x28, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "addvl x23, x8, #-1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x53, 0x3f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "addvl sp, sp, #31"
+
+  -
+    input:
+      bytes: [ 0x00, 0x54, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "addvl x0, x0, #-32"
+
+  -
+    input:
+      bytes: [ 0x15, 0x50, 0x35, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "addvl x21, x21, #0"
+
+  -
+    input:
+      bytes: [ 0xf7, 0x57, 0x28, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "addvl x23, x8, #-1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x53, 0x3f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "addvl sp, sp, #31"
+
+  -
+    input:
+      bytes: [ 0x00, 0x54, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "addvl x0, x0, #-32"
diff --git a/tests/MC/AArch64/SVE/adr.s.yaml b/tests/MC/AArch64/SVE/adr.s.yaml
new file mode 100644
index 000000000..6b13b0414
--- /dev/null
+++ b/tests/MC/AArch64/SVE/adr.s.yaml
@@ -0,0 +1,200 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "adr z0.s, [z0.s, z0.s]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "adr z0.s, [z0.s, z0.s]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa4, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "adr z0.s, [z0.s, z0.s, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa8, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "adr z0.s, [z0.s, z0.s, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xac, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "adr z0.s, [z0.s, z0.s, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "adr z0.d, [z0.d, z0.d]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "adr z0.d, [z0.d, z0.d]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa4, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "adr z0.d, [z0.d, z0.d, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa8, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "adr z0.d, [z0.d, z0.d, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xac, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "adr z0.d, [z0.d, z0.d, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "adr z0.d, [z0.d, z0.d, uxtw]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "adr z0.d, [z0.d, z0.d, uxtw]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa4, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "adr z0.d, [z0.d, z0.d, uxtw #1]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa8, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "adr z0.d, [z0.d, z0.d, uxtw #2]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xac, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "adr z0.d, [z0.d, z0.d, uxtw #3]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "adr z0.d, [z0.d, z0.d, sxtw]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "adr z0.d, [z0.d, z0.d, sxtw]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa4, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "adr z0.d, [z0.d, z0.d, sxtw #1]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa8, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "adr z0.d, [z0.d, z0.d, sxtw #2]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xac, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "adr z0.d, [z0.d, z0.d, sxtw #3]"
diff --git a/tests/MC/AArch64/SVE/and.s.yaml b/tests/MC/AArch64/SVE/and.s.yaml
new file mode 100644
index 000000000..cafa684d9
--- /dev/null
+++ b/tests/MC/AArch64/SVE/and.s.yaml
@@ -0,0 +1,520 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xa5, 0x2e, 0x80, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "and z5.b, z5.b, #0xf9"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x6d, 0x80, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "and z23.h, z23.h, #0xfff9"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xeb, 0x80, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "and z0.s, z0.s, #0xfffffff9"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xef, 0x83, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "and z0.d, z0.d, #0xfffffffffffffff9"
+
+  -
+    input:
+      bytes: [ 0x25, 0x3e, 0x80, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "and z5.b, z5.b, #0x6"
+
+  -
+    input:
+      bytes: [ 0x37, 0x7c, 0x80, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "and z23.h, z23.h, #0x6"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf8, 0x80, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "and z0.s, z0.s, #0x6"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf8, 0x83, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "and z0.d, z0.d, #0x6"
+
+  -
+    input:
+      bytes: [ 0x00, 0x30, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "and z0.d, z0.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x31, 0x28, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "and z23.d, z13.d, z8.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0x1a, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "and z31.b, p7/m, z31.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0x5a, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "and z31.h, p7/m, z31.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0x9a, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "and z31.s, p7/m, z31.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0xda, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "and z31.d, p7/m, z31.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0x01, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "and p0.b, p0/z, p0.b, p1.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0x00, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov p0.b, p0/z, p0.b"
+
+  -
+    input:
+      bytes: [ 0xef, 0x7d, 0x0f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov p15.b, p15/z, p15.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x30, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "and z0.d, z0.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x30, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "and z0.d, z0.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x30, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "and z0.d, z0.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4.d, p7/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xe4, 0x1f, 0xda, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "and z4.d, p7/m, z4.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4, z6"
+
+  -
+    input:
+      bytes: [ 0xe4, 0x1f, 0xda, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "and z4.d, p7/m, z4.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf8, 0x83, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "and z0.d, z0.d, #0x6"
+
+  -
+    input:
+      bytes: [ 0xa5, 0x2e, 0x80, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "and z5.b, z5.b, #0xf9"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x6d, 0x80, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "and z23.h, z23.h, #0xfff9"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xeb, 0x80, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "and z0.s, z0.s, #0xfffffff9"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xef, 0x83, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "and z0.d, z0.d, #0xfffffffffffffff9"
+
+  -
+    input:
+      bytes: [ 0x25, 0x3e, 0x80, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "and z5.b, z5.b, #0x6"
+
+  -
+    input:
+      bytes: [ 0x37, 0x7c, 0x80, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "and z23.h, z23.h, #0x6"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf8, 0x80, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "and z0.s, z0.s, #0x6"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf8, 0x83, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "and z0.d, z0.d, #0x6"
+
+  -
+    input:
+      bytes: [ 0x00, 0x30, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "and z0.d, z0.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x31, 0x28, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "and z23.d, z13.d, z8.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0x1a, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "and z31.b, p7/m, z31.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0x5a, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "and z31.h, p7/m, z31.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0x9a, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "and z31.s, p7/m, z31.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0xda, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "and z31.d, p7/m, z31.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0x01, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "and p0.b, p0/z, p0.b, p1.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0x00, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov p0.b, p0/z, p0.b"
+
+  -
+    input:
+      bytes: [ 0xef, 0x7d, 0x0f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov p15.b, p15/z, p15.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x30, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "and z0.d, z0.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x30, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "and z0.d, z0.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x30, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "and z0.d, z0.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4.d, p7/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xe4, 0x1f, 0xda, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "and z4.d, p7/m, z4.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4, z6"
+
+  -
+    input:
+      bytes: [ 0xe4, 0x1f, 0xda, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "and z4.d, p7/m, z4.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf8, 0x83, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "and z0.d, z0.d, #0x6"
diff --git a/tests/MC/AArch64/SVE/ands.s.yaml b/tests/MC/AArch64/SVE/ands.s.yaml
new file mode 100644
index 000000000..f48e492a1
--- /dev/null
+++ b/tests/MC/AArch64/SVE/ands.s.yaml
@@ -0,0 +1,60 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0x41, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ands p0.b, p0/z, p0.b, p1.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0x40, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movs p0.b, p0/z, p0.b"
+
+  -
+    input:
+      bytes: [ 0xef, 0x7d, 0x4f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movs p15.b, p15/z, p15.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0x41, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ands p0.b, p0/z, p0.b, p1.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0x40, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movs p0.b, p0/z, p0.b"
+
+  -
+    input:
+      bytes: [ 0xef, 0x7d, 0x4f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movs p15.b, p15/z, p15.b"
diff --git a/tests/MC/AArch64/SVE/andv.s.yaml b/tests/MC/AArch64/SVE/andv.s.yaml
new file mode 100644
index 000000000..eebf898e5
--- /dev/null
+++ b/tests/MC/AArch64/SVE/andv.s.yaml
@@ -0,0 +1,80 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xe0, 0x3f, 0x1a, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "andv b0, p7, z31.b"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3f, 0x5a, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "andv h0, p7, z31.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3f, 0x9a, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "andv s0, p7, z31.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3f, 0xda, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "andv d0, p7, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3f, 0x1a, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "andv b0, p7, z31.b"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3f, 0x5a, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "andv h0, p7, z31.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3f, 0x9a, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "andv s0, p7, z31.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3f, 0xda, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "andv d0, p7, z31.d"
diff --git a/tests/MC/AArch64/SVE/armv9.5a-cpa.s.yaml b/tests/MC/AArch64/SVE/armv9.5a-cpa.s.yaml
new file mode 100644
index 000000000..81de7a29e
--- /dev/null
+++ b/tests/MC/AArch64/SVE/armv9.5a-cpa.s.yaml
@@ -0,0 +1,60 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xb7, 0x09, 0xe8, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "cpa" ]
+    expected:
+      insns:
+        -
+          asm_text: "addpt z23.d, z13.d, z8.d"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x0d, 0xc4, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "cpa" ]
+    expected:
+      insns:
+        -
+          asm_text: "addpt z23.d, p3/m, z23.d, z13.d"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x0d, 0xe8, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "cpa" ]
+    expected:
+      insns:
+        -
+          asm_text: "subpt z23.d, z13.d, z8.d"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x0d, 0xc5, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "cpa" ]
+    expected:
+      insns:
+        -
+          asm_text: "subpt z23.d, p3/m, z23.d, z13.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xdb, 0xc1, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "cpa" ]
+    expected:
+      insns:
+        -
+          asm_text: "madpt z0.d, z1.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd0, 0xdf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "cpa" ]
+    expected:
+      insns:
+        -
+          asm_text: "mlapt z0.d, z1.d, z31.d"
diff --git a/tests/MC/AArch64/SVE/asr.s.yaml b/tests/MC/AArch64/SVE/asr.s.yaml
new file mode 100644
index 000000000..c515463ca
--- /dev/null
+++ b/tests/MC/AArch64/SVE/asr.s.yaml
@@ -0,0 +1,680 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x90, 0x2f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "asr z0.b, z0.b, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x93, 0x28, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "asr z31.b, z31.b, #8"
+
+  -
+    input:
+      bytes: [ 0x00, 0x90, 0x3f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "asr z0.h, z0.h, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x93, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "asr z31.h, z31.h, #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0x90, 0x7f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "asr z0.s, z0.s, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x93, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "asr z31.s, z31.s, #32"
+
+  -
+    input:
+      bytes: [ 0x00, 0x90, 0xff, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "asr z0.d, z0.d, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x93, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "asr z31.d, z31.d, #64"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x81, 0x00, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "asr z0.b, p0/m, z0.b, #1"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x81, 0x00, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "asr z31.b, p0/m, z31.b, #8"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x83, 0x00, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "asr z0.h, p0/m, z0.h, #1"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x82, 0x00, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "asr z31.h, p0/m, z31.h, #16"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x83, 0x40, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "asr z0.s, p0/m, z0.s, #1"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x80, 0x40, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "asr z31.s, p0/m, z31.s, #32"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x83, 0xc0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "asr z0.d, p0/m, z0.d, #1"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x80, 0x80, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "asr z31.d, p0/m, z31.d, #64"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x10, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "asr z0.b, p0/m, z0.b, z0.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x50, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "asr z0.h, p0/m, z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x90, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "asr z0.s, p0/m, z0.s, z0.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "asr z0.d, p0/m, z0.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x18, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "asr z0.b, p0/m, z0.b, z1.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x58, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "asr z0.h, p0/m, z0.h, z1.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x98, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "asr z0.s, p0/m, z0.s, z1.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x22, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "asr z0.b, z1.b, z2.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x62, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "asr z0.h, z1.h, z2.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0xa2, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "asr z0.s, z1.s, z2.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31.d, p0/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x80, 0x80, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "asr z31.d, p0/m, z31.d, #64"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x80, 0x80, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "asr z31.d, p0/m, z31.d, #64"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x20, 0x90, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0.s, p0/z, z7.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x98, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "asr z0.s, p0/m, z0.s, z1.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x98, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "asr z0.s, p0/m, z0.s, z1.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x90, 0x2f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "asr z0.b, z0.b, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x93, 0x28, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "asr z31.b, z31.b, #8"
+
+  -
+    input:
+      bytes: [ 0x00, 0x90, 0x3f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "asr z0.h, z0.h, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x93, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "asr z31.h, z31.h, #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0x90, 0x7f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "asr z0.s, z0.s, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x93, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "asr z31.s, z31.s, #32"
+
+  -
+    input:
+      bytes: [ 0x00, 0x90, 0xff, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "asr z0.d, z0.d, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x93, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "asr z31.d, z31.d, #64"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x81, 0x00, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "asr z0.b, p0/m, z0.b, #1"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x81, 0x00, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "asr z31.b, p0/m, z31.b, #8"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x83, 0x00, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "asr z0.h, p0/m, z0.h, #1"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x82, 0x00, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "asr z31.h, p0/m, z31.h, #16"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x83, 0x40, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "asr z0.s, p0/m, z0.s, #1"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x80, 0x40, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "asr z31.s, p0/m, z31.s, #32"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x83, 0xc0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "asr z0.d, p0/m, z0.d, #1"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x80, 0x80, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "asr z31.d, p0/m, z31.d, #64"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x10, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "asr z0.b, p0/m, z0.b, z0.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x50, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "asr z0.h, p0/m, z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x90, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "asr z0.s, p0/m, z0.s, z0.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "asr z0.d, p0/m, z0.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x18, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "asr z0.b, p0/m, z0.b, z1.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x58, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "asr z0.h, p0/m, z0.h, z1.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x98, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "asr z0.s, p0/m, z0.s, z1.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x22, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "asr z0.b, z1.b, z2.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x62, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "asr z0.h, z1.h, z2.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0xa2, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "asr z0.s, z1.s, z2.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31.d, p0/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x80, 0x80, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "asr z31.d, p0/m, z31.d, #64"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x80, 0x80, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "asr z31.d, p0/m, z31.d, #64"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x20, 0x90, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0.s, p0/z, z7.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x98, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "asr z0.s, p0/m, z0.s, z1.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x98, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "asr z0.s, p0/m, z0.s, z1.d"
diff --git a/tests/MC/AArch64/SVE/asrd.s.yaml b/tests/MC/AArch64/SVE/asrd.s.yaml
new file mode 100644
index 000000000..e8ae5ecf5
--- /dev/null
+++ b/tests/MC/AArch64/SVE/asrd.s.yaml
@@ -0,0 +1,240 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xe0, 0x81, 0x04, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "asrd z0.b, p0/m, z0.b, #1"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x81, 0x04, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "asrd z31.b, p0/m, z31.b, #8"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x83, 0x04, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "asrd z0.h, p0/m, z0.h, #1"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x82, 0x04, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "asrd z31.h, p0/m, z31.h, #16"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x83, 0x44, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "asrd z0.s, p0/m, z0.s, #1"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x80, 0x44, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "asrd z31.s, p0/m, z31.s, #32"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x83, 0xc4, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "asrd z0.d, p0/m, z0.d, #1"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x80, 0x84, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "asrd z31.d, p0/m, z31.d, #64"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31.d, p0/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x80, 0x84, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "asrd z31.d, p0/m, z31.d, #64"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x80, 0x84, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "asrd z31.d, p0/m, z31.d, #64"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x81, 0x04, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "asrd z0.b, p0/m, z0.b, #1"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x81, 0x04, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "asrd z31.b, p0/m, z31.b, #8"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x83, 0x04, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "asrd z0.h, p0/m, z0.h, #1"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x82, 0x04, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "asrd z31.h, p0/m, z31.h, #16"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x83, 0x44, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "asrd z0.s, p0/m, z0.s, #1"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x80, 0x44, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "asrd z31.s, p0/m, z31.s, #32"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x83, 0xc4, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "asrd z0.d, p0/m, z0.d, #1"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x80, 0x84, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "asrd z31.d, p0/m, z31.d, #64"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31.d, p0/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x80, 0x84, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "asrd z31.d, p0/m, z31.d, #64"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x80, 0x84, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "asrd z31.d, p0/m, z31.d, #64"
diff --git a/tests/MC/AArch64/SVE/asrr.s.yaml b/tests/MC/AArch64/SVE/asrr.s.yaml
new file mode 100644
index 000000000..df4911738
--- /dev/null
+++ b/tests/MC/AArch64/SVE/asrr.s.yaml
@@ -0,0 +1,160 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x14, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "asrr z0.b, p0/m, z0.b, z0.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x54, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "asrr z0.h, p0/m, z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x94, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "asrr z0.s, p0/m, z0.s, z0.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xd4, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "asrr z0.d, p0/m, z0.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0xe5, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z5.d, p0/z, z7.d"
+
+  -
+    input:
+      bytes: [ 0x05, 0x80, 0xd4, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "asrr z5.d, p0/m, z5.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0xe5, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z5, z7"
+
+  -
+    input:
+      bytes: [ 0x05, 0x80, 0xd4, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "asrr z5.d, p0/m, z5.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x14, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "asrr z0.b, p0/m, z0.b, z0.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x54, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "asrr z0.h, p0/m, z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x94, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "asrr z0.s, p0/m, z0.s, z0.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xd4, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "asrr z0.d, p0/m, z0.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0xe5, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z5.d, p0/z, z7.d"
+
+  -
+    input:
+      bytes: [ 0x05, 0x80, 0xd4, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "asrr z5.d, p0/m, z5.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0xe5, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z5, z7"
+
+  -
+    input:
+      bytes: [ 0x05, 0x80, 0xd4, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "asrr z5.d, p0/m, z5.d, z0.d"
diff --git a/tests/MC/AArch64/SVE/bfcvt.s.yaml b/tests/MC/AArch64/SVE/bfcvt.s.yaml
new file mode 100644
index 000000000..0288514d4
--- /dev/null
+++ b/tests/MC/AArch64/SVE/bfcvt.s.yaml
@@ -0,0 +1,100 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0xa0, 0x8a, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfcvt z0.h, p0/m, z1.s"
+
+  -
+    input:
+      bytes: [ 0x40, 0x20, 0x91, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0.s, p0/m, z2.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa0, 0x8a, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfcvt z0.h, p0/m, z1.s"
+
+  -
+    input:
+      bytes: [ 0x40, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z2"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa0, 0x8a, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfcvt z0.h, p0/m, z1.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa0, 0x8a, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme", "+bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfcvt z0.h, p0/m, z1.s"
+
+  -
+    input:
+      bytes: [ 0x40, 0x20, 0x91, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme", "+bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0.s, p0/m, z2.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa0, 0x8a, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme", "+bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfcvt z0.h, p0/m, z1.s"
+
+  -
+    input:
+      bytes: [ 0x40, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme", "+bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z2"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa0, 0x8a, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme", "+bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfcvt z0.h, p0/m, z1.s"
diff --git a/tests/MC/AArch64/SVE/bfcvtnt.s.yaml b/tests/MC/AArch64/SVE/bfcvtnt.s.yaml
new file mode 100644
index 000000000..e21e1d21a
--- /dev/null
+++ b/tests/MC/AArch64/SVE/bfcvtnt.s.yaml
@@ -0,0 +1,100 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0xa0, 0x8a, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfcvtnt z0.h, p0/m, z1.s"
+
+  -
+    input:
+      bytes: [ 0x40, 0x20, 0x91, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0.s, p0/m, z2.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa0, 0x8a, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfcvtnt z0.h, p0/m, z1.s"
+
+  -
+    input:
+      bytes: [ 0x40, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z2"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa0, 0x8a, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfcvtnt z0.h, p0/m, z1.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa0, 0x8a, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme", "+bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfcvtnt z0.h, p0/m, z1.s"
+
+  -
+    input:
+      bytes: [ 0x40, 0x20, 0x91, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme", "+bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0.s, p0/m, z2.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa0, 0x8a, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme", "+bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfcvtnt z0.h, p0/m, z1.s"
+
+  -
+    input:
+      bytes: [ 0x40, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme", "+bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z2"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa0, 0x8a, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme", "+bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfcvtnt z0.h, p0/m, z1.s"
diff --git a/tests/MC/AArch64/SVE/bfdot.s.yaml b/tests/MC/AArch64/SVE/bfdot.s.yaml
new file mode 100644
index 000000000..9da70342f
--- /dev/null
+++ b/tests/MC/AArch64/SVE/bfdot.s.yaml
@@ -0,0 +1,180 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x62, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot z0.s, z1.h, z2.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x40, 0x62, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot z0.s, z1.h, z2.h[0]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x40, 0x7a, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot z0.s, z1.h, z2.h[3]"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x62, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot z0.s, z1.h, z2.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x20, 0x40, 0x62, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot z0.s, z1.h, z2.h[0]"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x20, 0x40, 0x7a, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot z0.s, z1.h, z2.h[3]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x62, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme", "+bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot z0.s, z1.h, z2.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x40, 0x62, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme", "+bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot z0.s, z1.h, z2.h[0]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x40, 0x7a, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme", "+bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot z0.s, z1.h, z2.h[3]"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme", "+bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x62, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme", "+bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot z0.s, z1.h, z2.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme", "+bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x20, 0x40, 0x62, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme", "+bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot z0.s, z1.h, z2.h[0]"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme", "+bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x20, 0x40, 0x7a, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme", "+bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot z0.s, z1.h, z2.h[3]"
diff --git a/tests/MC/AArch64/SVE/bfmlal.s.yaml b/tests/MC/AArch64/SVE/bfmlal.s.yaml
new file mode 100644
index 000000000..819f7a7cf
--- /dev/null
+++ b/tests/MC/AArch64/SVE/bfmlal.s.yaml
@@ -0,0 +1,600 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0xe2, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlalb z0.s, z1.h, z2.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x84, 0xe2, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlalt z0.s, z1.h, z2.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x40, 0xe2, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlalb z0.s, z1.h, z2.h[0]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x44, 0xe2, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlalt z0.s, z1.h, z2.h[0]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x48, 0xfa, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlalb z0.s, z1.h, z2.h[7]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x4c, 0xfa, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlalt z0.s, z1.h, z2.h[7]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x4c, 0xff, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlalt z0.s, z1.h, z7.h[7]"
+
+  -
+    input:
+      bytes: [ 0xaa, 0x82, 0xee, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlalb z10.s, z21.h, z14.h"
+
+  -
+    input:
+      bytes: [ 0x4e, 0x85, 0xf5, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlalt z14.s, z10.h, z21.h"
+
+  -
+    input:
+      bytes: [ 0xd5, 0x41, 0xeb, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlalb z21.s, z14.h, z3.h[2]"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0xe2, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlalb z0.s, z1.h, z2.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x20, 0x84, 0xe2, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlalt z0.s, z1.h, z2.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x20, 0x40, 0xe2, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlalb z0.s, z1.h, z2.h[0]"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x20, 0x44, 0xe2, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlalt z0.s, z1.h, z2.h[0]"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x20, 0x48, 0xfa, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlalb z0.s, z1.h, z2.h[7]"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x20, 0x4c, 0xfa, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlalt z0.s, z1.h, z2.h[7]"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x20, 0x4c, 0xff, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlalt z0.s, z1.h, z7.h[7]"
+
+  -
+    input:
+      bytes: [ 0xea, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z10, z7"
+
+  -
+    input:
+      bytes: [ 0xaa, 0x82, 0xee, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlalb z10.s, z21.h, z14.h"
+
+  -
+    input:
+      bytes: [ 0xee, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z14, z7"
+
+  -
+    input:
+      bytes: [ 0x4e, 0x85, 0xf5, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlalt z14.s, z10.h, z21.h"
+
+  -
+    input:
+      bytes: [ 0xf5, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z21, z7"
+
+  -
+    input:
+      bytes: [ 0xd5, 0x41, 0xeb, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlalb z21.s, z14.h, z3.h[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0xe2, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme", "+bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlalb z0.s, z1.h, z2.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x84, 0xe2, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme", "+bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlalt z0.s, z1.h, z2.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x40, 0xe2, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme", "+bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlalb z0.s, z1.h, z2.h[0]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x44, 0xe2, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme", "+bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlalt z0.s, z1.h, z2.h[0]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x48, 0xfa, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme", "+bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlalb z0.s, z1.h, z2.h[7]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x4c, 0xfa, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme", "+bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlalt z0.s, z1.h, z2.h[7]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x4c, 0xff, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme", "+bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlalt z0.s, z1.h, z7.h[7]"
+
+  -
+    input:
+      bytes: [ 0xaa, 0x82, 0xee, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme", "+bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlalb z10.s, z21.h, z14.h"
+
+  -
+    input:
+      bytes: [ 0x4e, 0x85, 0xf5, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme", "+bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlalt z14.s, z10.h, z21.h"
+
+  -
+    input:
+      bytes: [ 0xd5, 0x41, 0xeb, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme", "+bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlalb z21.s, z14.h, z3.h[2]"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme", "+bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0xe2, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme", "+bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlalb z0.s, z1.h, z2.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme", "+bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x20, 0x84, 0xe2, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme", "+bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlalt z0.s, z1.h, z2.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme", "+bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x20, 0x40, 0xe2, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme", "+bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlalb z0.s, z1.h, z2.h[0]"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme", "+bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x20, 0x44, 0xe2, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme", "+bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlalt z0.s, z1.h, z2.h[0]"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme", "+bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x20, 0x48, 0xfa, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme", "+bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlalb z0.s, z1.h, z2.h[7]"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme", "+bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x20, 0x4c, 0xfa, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme", "+bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlalt z0.s, z1.h, z2.h[7]"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme", "+bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x20, 0x4c, 0xff, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme", "+bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlalt z0.s, z1.h, z7.h[7]"
+
+  -
+    input:
+      bytes: [ 0xea, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme", "+bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z10, z7"
+
+  -
+    input:
+      bytes: [ 0xaa, 0x82, 0xee, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme", "+bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlalb z10.s, z21.h, z14.h"
+
+  -
+    input:
+      bytes: [ 0xee, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme", "+bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z14, z7"
+
+  -
+    input:
+      bytes: [ 0x4e, 0x85, 0xf5, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme", "+bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlalt z14.s, z10.h, z21.h"
+
+  -
+    input:
+      bytes: [ 0xf5, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme", "+bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z21, z7"
+
+  -
+    input:
+      bytes: [ 0xd5, 0x41, 0xeb, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme", "+bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlalb z21.s, z14.h, z3.h[2]"
diff --git a/tests/MC/AArch64/SVE/bfmmla.s.yaml b/tests/MC/AArch64/SVE/bfmmla.s.yaml
new file mode 100644
index 000000000..b9c02cf58
--- /dev/null
+++ b/tests/MC/AArch64/SVE/bfmmla.s.yaml
@@ -0,0 +1,30 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0xe4, 0x62, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmmla z0.s, z1.h, z2.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe4, 0x62, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmmla z0.s, z1.h, z2.h"
diff --git a/tests/MC/AArch64/SVE/bic.s.yaml b/tests/MC/AArch64/SVE/bic.s.yaml
new file mode 100644
index 000000000..462983756
--- /dev/null
+++ b/tests/MC/AArch64/SVE/bic.s.yaml
@@ -0,0 +1,500 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x25, 0x3e, 0x80, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "and z5.b, z5.b, #0x6"
+
+  -
+    input:
+      bytes: [ 0x37, 0x7c, 0x80, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "and z23.h, z23.h, #0x6"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf8, 0x80, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "and z0.s, z0.s, #0x6"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf8, 0x83, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "and z0.d, z0.d, #0x6"
+
+  -
+    input:
+      bytes: [ 0xa5, 0x2e, 0x80, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "and z5.b, z5.b, #0xf9"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x6d, 0x80, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "and z23.h, z23.h, #0xfff9"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xeb, 0x80, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "and z0.s, z0.s, #0xfffffff9"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xef, 0x83, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "and z0.d, z0.d, #0xfffffffffffffff9"
+
+  -
+    input:
+      bytes: [ 0x00, 0x30, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "bic z0.d, z0.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x31, 0xe8, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "bic z23.d, z13.d, z8.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0x1b, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "bic z31.b, p7/m, z31.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0x5b, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "bic z31.h, p7/m, z31.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0x9b, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "bic z31.s, p7/m, z31.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0xdb, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "bic z31.d, p7/m, z31.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0x7d, 0x0f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "bic p15.b, p15/z, p15.b, p15.b"
+
+  -
+    input:
+      bytes: [ 0x10, 0x40, 0x00, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "bic p0.b, p0/z, p0.b, p0.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x30, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "bic z0.d, z0.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x30, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "bic z0.d, z0.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x30, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "bic z0.d, z0.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4.d, p7/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xe4, 0x1f, 0xdb, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "bic z4.d, p7/m, z4.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4, z6"
+
+  -
+    input:
+      bytes: [ 0xe4, 0x1f, 0xdb, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "bic z4.d, p7/m, z4.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xef, 0x83, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "and z0.d, z0.d, #0xfffffffffffffff9"
+
+  -
+    input:
+      bytes: [ 0x25, 0x3e, 0x80, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "and z5.b, z5.b, #0x6"
+
+  -
+    input:
+      bytes: [ 0x37, 0x7c, 0x80, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "and z23.h, z23.h, #0x6"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf8, 0x80, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "and z0.s, z0.s, #0x6"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf8, 0x83, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "and z0.d, z0.d, #0x6"
+
+  -
+    input:
+      bytes: [ 0xa5, 0x2e, 0x80, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "and z5.b, z5.b, #0xf9"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x6d, 0x80, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "and z23.h, z23.h, #0xfff9"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xeb, 0x80, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "and z0.s, z0.s, #0xfffffff9"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xef, 0x83, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "and z0.d, z0.d, #0xfffffffffffffff9"
+
+  -
+    input:
+      bytes: [ 0x00, 0x30, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "bic z0.d, z0.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x31, 0xe8, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "bic z23.d, z13.d, z8.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0x1b, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "bic z31.b, p7/m, z31.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0x5b, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "bic z31.h, p7/m, z31.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0x9b, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "bic z31.s, p7/m, z31.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0xdb, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "bic z31.d, p7/m, z31.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0x7d, 0x0f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "bic p15.b, p15/z, p15.b, p15.b"
+
+  -
+    input:
+      bytes: [ 0x10, 0x40, 0x00, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "bic p0.b, p0/z, p0.b, p0.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x30, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "bic z0.d, z0.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x30, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "bic z0.d, z0.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x30, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "bic z0.d, z0.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4.d, p7/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xe4, 0x1f, 0xdb, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "bic z4.d, p7/m, z4.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4, z6"
+
+  -
+    input:
+      bytes: [ 0xe4, 0x1f, 0xdb, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "bic z4.d, p7/m, z4.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xef, 0x83, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "and z0.d, z0.d, #0xfffffffffffffff9"
diff --git a/tests/MC/AArch64/SVE/bics.s.yaml b/tests/MC/AArch64/SVE/bics.s.yaml
new file mode 100644
index 000000000..747e13e78
--- /dev/null
+++ b/tests/MC/AArch64/SVE/bics.s.yaml
@@ -0,0 +1,40 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x10, 0x40, 0x40, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "bics p0.b, p0/z, p0.b, p0.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x7d, 0x4f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "bics p15.b, p15/z, p15.b, p15.b"
+
+  -
+    input:
+      bytes: [ 0x10, 0x40, 0x40, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "bics p0.b, p0/z, p0.b, p0.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x7d, 0x4f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "bics p15.b, p15/z, p15.b, p15.b"
diff --git a/tests/MC/AArch64/SVE/brka.s.yaml b/tests/MC/AArch64/SVE/brka.s.yaml
new file mode 100644
index 000000000..a5945fac4
--- /dev/null
+++ b/tests/MC/AArch64/SVE/brka.s.yaml
@@ -0,0 +1,40 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xf0, 0x7d, 0x10, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "brka p0.b, p15/m, p15.b"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x7d, 0x10, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "brka p0.b, p15/z, p15.b"
+
+  -
+    input:
+      bytes: [ 0xf0, 0x7d, 0x10, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "brka p0.b, p15/m, p15.b"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x7d, 0x10, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "brka p0.b, p15/z, p15.b"
diff --git a/tests/MC/AArch64/SVE/brkas.s.yaml b/tests/MC/AArch64/SVE/brkas.s.yaml
new file mode 100644
index 000000000..e6c08ffe7
--- /dev/null
+++ b/tests/MC/AArch64/SVE/brkas.s.yaml
@@ -0,0 +1,20 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xe0, 0x7d, 0x50, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "brkas p0.b, p15/z, p15.b"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x7d, 0x50, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "brkas p0.b, p15/z, p15.b"
diff --git a/tests/MC/AArch64/SVE/brkb.s.yaml b/tests/MC/AArch64/SVE/brkb.s.yaml
new file mode 100644
index 000000000..1d488fc23
--- /dev/null
+++ b/tests/MC/AArch64/SVE/brkb.s.yaml
@@ -0,0 +1,40 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xf0, 0x7d, 0x90, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "brkb p0.b, p15/m, p15.b"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x7d, 0x90, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "brkb p0.b, p15/z, p15.b"
+
+  -
+    input:
+      bytes: [ 0xf0, 0x7d, 0x90, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "brkb p0.b, p15/m, p15.b"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x7d, 0x90, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "brkb p0.b, p15/z, p15.b"
diff --git a/tests/MC/AArch64/SVE/brkbs.s.yaml b/tests/MC/AArch64/SVE/brkbs.s.yaml
new file mode 100644
index 000000000..22b47cde0
--- /dev/null
+++ b/tests/MC/AArch64/SVE/brkbs.s.yaml
@@ -0,0 +1,20 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xe0, 0x7d, 0xd0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "brkbs p0.b, p15/z, p15.b"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x7d, 0xd0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "brkbs p0.b, p15/z, p15.b"
diff --git a/tests/MC/AArch64/SVE/brkn.s.yaml b/tests/MC/AArch64/SVE/brkn.s.yaml
new file mode 100644
index 000000000..49bc07d78
--- /dev/null
+++ b/tests/MC/AArch64/SVE/brkn.s.yaml
@@ -0,0 +1,40 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x7c, 0x18, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "brkn p0.b, p15/z, p1.b, p0.b"
+
+  -
+    input:
+      bytes: [ 0xef, 0x7d, 0x18, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "brkn p15.b, p15/z, p15.b, p15.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x7c, 0x18, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "brkn p0.b, p15/z, p1.b, p0.b"
+
+  -
+    input:
+      bytes: [ 0xef, 0x7d, 0x18, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "brkn p15.b, p15/z, p15.b, p15.b"
diff --git a/tests/MC/AArch64/SVE/brkns.s.yaml b/tests/MC/AArch64/SVE/brkns.s.yaml
new file mode 100644
index 000000000..7789903cd
--- /dev/null
+++ b/tests/MC/AArch64/SVE/brkns.s.yaml
@@ -0,0 +1,40 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x7c, 0x58, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "brkns p0.b, p15/z, p1.b, p0.b"
+
+  -
+    input:
+      bytes: [ 0xef, 0x7d, 0x58, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "brkns p15.b, p15/z, p15.b, p15.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x7c, 0x58, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "brkns p0.b, p15/z, p1.b, p0.b"
+
+  -
+    input:
+      bytes: [ 0xef, 0x7d, 0x58, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "brkns p15.b, p15/z, p15.b, p15.b"
diff --git a/tests/MC/AArch64/SVE/brkpa.s.yaml b/tests/MC/AArch64/SVE/brkpa.s.yaml
new file mode 100644
index 000000000..612ee4d93
--- /dev/null
+++ b/tests/MC/AArch64/SVE/brkpa.s.yaml
@@ -0,0 +1,40 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0xfc, 0x02, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "brkpa p0.b, p15/z, p1.b, p2.b"
+
+  -
+    input:
+      bytes: [ 0xef, 0xfd, 0x0f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "brkpa p15.b, p15/z, p15.b, p15.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0xfc, 0x02, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "brkpa p0.b, p15/z, p1.b, p2.b"
+
+  -
+    input:
+      bytes: [ 0xef, 0xfd, 0x0f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "brkpa p15.b, p15/z, p15.b, p15.b"
diff --git a/tests/MC/AArch64/SVE/brkpas.s.yaml b/tests/MC/AArch64/SVE/brkpas.s.yaml
new file mode 100644
index 000000000..6f340336a
--- /dev/null
+++ b/tests/MC/AArch64/SVE/brkpas.s.yaml
@@ -0,0 +1,40 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0xfc, 0x42, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "brkpas p0.b, p15/z, p1.b, p2.b"
+
+  -
+    input:
+      bytes: [ 0xef, 0xfd, 0x4f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "brkpas p15.b, p15/z, p15.b, p15.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0xfc, 0x42, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "brkpas p0.b, p15/z, p1.b, p2.b"
+
+  -
+    input:
+      bytes: [ 0xef, 0xfd, 0x4f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "brkpas p15.b, p15/z, p15.b, p15.b"
diff --git a/tests/MC/AArch64/SVE/brkpb.s.yaml b/tests/MC/AArch64/SVE/brkpb.s.yaml
new file mode 100644
index 000000000..b7fabbcba
--- /dev/null
+++ b/tests/MC/AArch64/SVE/brkpb.s.yaml
@@ -0,0 +1,40 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x30, 0xfc, 0x02, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "brkpb p0.b, p15/z, p1.b, p2.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0xfd, 0x0f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "brkpb p15.b, p15/z, p15.b, p15.b"
+
+  -
+    input:
+      bytes: [ 0x30, 0xfc, 0x02, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "brkpb p0.b, p15/z, p1.b, p2.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0xfd, 0x0f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "brkpb p15.b, p15/z, p15.b, p15.b"
diff --git a/tests/MC/AArch64/SVE/brkpbs.s.yaml b/tests/MC/AArch64/SVE/brkpbs.s.yaml
new file mode 100644
index 000000000..1b21ad23c
--- /dev/null
+++ b/tests/MC/AArch64/SVE/brkpbs.s.yaml
@@ -0,0 +1,40 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x30, 0xfc, 0x42, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "brkpbs p0.b, p15/z, p1.b, p2.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0xfd, 0x4f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "brkpbs p15.b, p15/z, p15.b, p15.b"
+
+  -
+    input:
+      bytes: [ 0x30, 0xfc, 0x42, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "brkpbs p0.b, p15/z, p1.b, p2.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0xfd, 0x4f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "brkpbs p15.b, p15/z, p15.b, p15.b"
diff --git a/tests/MC/AArch64/SVE/clasta.s.yaml b/tests/MC/AArch64/SVE/clasta.s.yaml
new file mode 100644
index 000000000..039ac10b0
--- /dev/null
+++ b/tests/MC/AArch64/SVE/clasta.s.yaml
@@ -0,0 +1,280 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xe0, 0xbf, 0x30, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "clasta w0, p7, w0, z31.b"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbf, 0x70, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "clasta w0, p7, w0, z31.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbf, 0xb0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "clasta w0, p7, w0, z31.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbf, 0xf0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "clasta x0, p7, x0, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0x2a, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "clasta b0, p7, b0, z31.b"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0x6a, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "clasta h0, p7, h0, z31.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xaa, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "clasta s0, p7, s0, z31.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xea, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "clasta d0, p7, d0, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0x28, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "clasta z0.b, p7, z0.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0x68, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "clasta z0.h, p7, z0.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xa8, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "clasta z0.s, p7, z0.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xe8, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "clasta z0.d, p7, z0.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xe8, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "clasta z0.d, p7, z0.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbf, 0x30, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "clasta w0, p7, w0, z31.b"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbf, 0x70, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "clasta w0, p7, w0, z31.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbf, 0xb0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "clasta w0, p7, w0, z31.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbf, 0xf0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "clasta x0, p7, x0, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0x2a, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "clasta b0, p7, b0, z31.b"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0x6a, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "clasta h0, p7, h0, z31.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xaa, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "clasta s0, p7, s0, z31.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xea, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "clasta d0, p7, d0, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0x28, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "clasta z0.b, p7, z0.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0x68, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "clasta z0.h, p7, z0.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xa8, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "clasta z0.s, p7, z0.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xe8, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "clasta z0.d, p7, z0.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xe8, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "clasta z0.d, p7, z0.d, z31.d"
diff --git a/tests/MC/AArch64/SVE/clastb.s.yaml b/tests/MC/AArch64/SVE/clastb.s.yaml
new file mode 100644
index 000000000..43f588322
--- /dev/null
+++ b/tests/MC/AArch64/SVE/clastb.s.yaml
@@ -0,0 +1,280 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xe0, 0xbf, 0x31, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "clastb w0, p7, w0, z31.b"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbf, 0x71, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "clastb w0, p7, w0, z31.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbf, 0xb1, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "clastb w0, p7, w0, z31.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbf, 0xf1, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "clastb x0, p7, x0, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0x2b, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "clastb b0, p7, b0, z31.b"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0x6b, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "clastb h0, p7, h0, z31.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xab, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "clastb s0, p7, s0, z31.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xeb, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "clastb d0, p7, d0, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0x29, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "clastb z0.b, p7, z0.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0x69, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "clastb z0.h, p7, z0.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xa9, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "clastb z0.s, p7, z0.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xe9, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "clastb z0.d, p7, z0.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xe9, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "clastb z0.d, p7, z0.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbf, 0x31, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "clastb w0, p7, w0, z31.b"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbf, 0x71, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "clastb w0, p7, w0, z31.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbf, 0xb1, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "clastb w0, p7, w0, z31.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbf, 0xf1, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "clastb x0, p7, x0, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0x2b, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "clastb b0, p7, b0, z31.b"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0x6b, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "clastb h0, p7, h0, z31.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xab, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "clastb s0, p7, s0, z31.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xeb, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "clastb d0, p7, d0, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0x29, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "clastb z0.b, p7, z0.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0x69, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "clastb z0.h, p7, z0.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xa9, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "clastb z0.s, p7, z0.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xe9, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "clastb z0.d, p7, z0.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xe9, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "clastb z0.d, p7, z0.d, z31.d"
diff --git a/tests/MC/AArch64/SVE/cls.s.yaml b/tests/MC/AArch64/SVE/cls.s.yaml
new file mode 100644
index 000000000..bb4c10d0d
--- /dev/null
+++ b/tests/MC/AArch64/SVE/cls.s.yaml
@@ -0,0 +1,160 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x18, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cls z31.b, p7/m, z31.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x58, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cls z31.h, p7/m, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x98, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cls z31.s, p7/m, z31.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0xd8, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cls z31.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4.d, p7/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xbf, 0xd8, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cls z4.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4, z6"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xbf, 0xd8, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cls z4.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x18, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cls z31.b, p7/m, z31.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x58, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cls z31.h, p7/m, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x98, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cls z31.s, p7/m, z31.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0xd8, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cls z31.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4.d, p7/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xbf, 0xd8, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cls z4.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4, z6"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xbf, 0xd8, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cls z4.d, p7/m, z31.d"
diff --git a/tests/MC/AArch64/SVE/clz.s.yaml b/tests/MC/AArch64/SVE/clz.s.yaml
new file mode 100644
index 000000000..163f8959f
--- /dev/null
+++ b/tests/MC/AArch64/SVE/clz.s.yaml
@@ -0,0 +1,160 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x19, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "clz z31.b, p7/m, z31.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x59, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "clz z31.h, p7/m, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x99, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "clz z31.s, p7/m, z31.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0xd9, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "clz z31.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4.d, p7/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xbf, 0xd9, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "clz z4.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4, z6"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xbf, 0xd9, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "clz z4.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x19, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "clz z31.b, p7/m, z31.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x59, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "clz z31.h, p7/m, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x99, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "clz z31.s, p7/m, z31.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0xd9, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "clz z31.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4.d, p7/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xbf, 0xd9, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "clz z4.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4, z6"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xbf, 0xd9, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "clz z4.d, p7/m, z31.d"
diff --git a/tests/MC/AArch64/SVE/cmpeq.s.yaml b/tests/MC/AArch64/SVE/cmpeq.s.yaml
new file mode 100644
index 000000000..e0b8ba01d
--- /dev/null
+++ b/tests/MC/AArch64/SVE/cmpeq.s.yaml
@@ -0,0 +1,300 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x00, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpeq p0.b, p0/z, z0.b, z0.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x40, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpeq p0.h, p0/z, z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x80, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpeq p0.s, p0/z, z0.s, z0.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xc0, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpeq p0.d, p0/z, z0.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x00, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpeq p0.b, p0/z, z0.b, z0.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x40, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpeq p0.h, p0/z, z0.h, z0.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x80, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpeq p0.s, p0/z, z0.s, z0.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x10, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpeq p0.b, p0/z, z0.b, #-16"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x50, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpeq p0.h, p0/z, z0.h, #-16"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x90, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpeq p0.s, p0/z, z0.s, #-16"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xd0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpeq p0.d, p0/z, z0.d, #-16"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x0f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpeq p0.b, p0/z, z0.b, #15"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x4f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpeq p0.h, p0/z, z0.h, #15"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x8f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpeq p0.s, p0/z, z0.s, #15"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xcf, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpeq p0.d, p0/z, z0.d, #15"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x00, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpeq p0.b, p0/z, z0.b, z0.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x40, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpeq p0.h, p0/z, z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x80, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpeq p0.s, p0/z, z0.s, z0.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xc0, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpeq p0.d, p0/z, z0.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x00, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpeq p0.b, p0/z, z0.b, z0.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x40, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpeq p0.h, p0/z, z0.h, z0.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x80, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpeq p0.s, p0/z, z0.s, z0.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x10, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpeq p0.b, p0/z, z0.b, #-16"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x50, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpeq p0.h, p0/z, z0.h, #-16"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x90, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpeq p0.s, p0/z, z0.s, #-16"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xd0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpeq p0.d, p0/z, z0.d, #-16"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x0f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpeq p0.b, p0/z, z0.b, #15"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x4f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpeq p0.h, p0/z, z0.h, #15"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x8f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpeq p0.s, p0/z, z0.s, #15"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xcf, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpeq p0.d, p0/z, z0.d, #15"
diff --git a/tests/MC/AArch64/SVE/cmpge.s.yaml b/tests/MC/AArch64/SVE/cmpge.s.yaml
new file mode 100644
index 000000000..48ab38c29
--- /dev/null
+++ b/tests/MC/AArch64/SVE/cmpge.s.yaml
@@ -0,0 +1,300 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x00, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpge p0.b, p0/z, z0.b, z0.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x40, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpge p0.h, p0/z, z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x80, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpge p0.s, p0/z, z0.s, z0.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xc0, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpge p0.d, p0/z, z0.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0x00, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpge p0.b, p0/z, z0.b, z0.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0x40, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpge p0.h, p0/z, z0.h, z0.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0x80, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpge p0.s, p0/z, z0.s, z0.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x10, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpge p0.b, p0/z, z0.b, #-16"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x50, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpge p0.h, p0/z, z0.h, #-16"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x90, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpge p0.s, p0/z, z0.s, #-16"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0xd0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpge p0.d, p0/z, z0.d, #-16"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x0f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpge p0.b, p0/z, z0.b, #15"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x4f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpge p0.h, p0/z, z0.h, #15"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x8f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpge p0.s, p0/z, z0.s, #15"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0xcf, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpge p0.d, p0/z, z0.d, #15"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x00, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpge p0.b, p0/z, z0.b, z0.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x40, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpge p0.h, p0/z, z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x80, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpge p0.s, p0/z, z0.s, z0.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xc0, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpge p0.d, p0/z, z0.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0x00, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpge p0.b, p0/z, z0.b, z0.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0x40, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpge p0.h, p0/z, z0.h, z0.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0x80, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpge p0.s, p0/z, z0.s, z0.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x10, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpge p0.b, p0/z, z0.b, #-16"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x50, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpge p0.h, p0/z, z0.h, #-16"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x90, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpge p0.s, p0/z, z0.s, #-16"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0xd0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpge p0.d, p0/z, z0.d, #-16"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x0f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpge p0.b, p0/z, z0.b, #15"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x4f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpge p0.h, p0/z, z0.h, #15"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x8f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpge p0.s, p0/z, z0.s, #15"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0xcf, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpge p0.d, p0/z, z0.d, #15"
diff --git a/tests/MC/AArch64/SVE/cmpgt.s.yaml b/tests/MC/AArch64/SVE/cmpgt.s.yaml
new file mode 100644
index 000000000..a3dfe962f
--- /dev/null
+++ b/tests/MC/AArch64/SVE/cmpgt.s.yaml
@@ -0,0 +1,300 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x10, 0x80, 0x00, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpgt p0.b, p0/z, z0.b, z0.b"
+
+  -
+    input:
+      bytes: [ 0x10, 0x80, 0x40, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpgt p0.h, p0/z, z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x10, 0x80, 0x80, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpgt p0.s, p0/z, z0.s, z0.s"
+
+  -
+    input:
+      bytes: [ 0x10, 0x80, 0xc0, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpgt p0.d, p0/z, z0.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0x10, 0x40, 0x00, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpgt p0.b, p0/z, z0.b, z0.d"
+
+  -
+    input:
+      bytes: [ 0x10, 0x40, 0x40, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpgt p0.h, p0/z, z0.h, z0.d"
+
+  -
+    input:
+      bytes: [ 0x10, 0x40, 0x80, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpgt p0.s, p0/z, z0.s, z0.d"
+
+  -
+    input:
+      bytes: [ 0x10, 0x00, 0x10, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpgt p0.b, p0/z, z0.b, #-16"
+
+  -
+    input:
+      bytes: [ 0x10, 0x00, 0x50, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpgt p0.h, p0/z, z0.h, #-16"
+
+  -
+    input:
+      bytes: [ 0x10, 0x00, 0x90, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpgt p0.s, p0/z, z0.s, #-16"
+
+  -
+    input:
+      bytes: [ 0x10, 0x00, 0xd0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpgt p0.d, p0/z, z0.d, #-16"
+
+  -
+    input:
+      bytes: [ 0x10, 0x00, 0x0f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpgt p0.b, p0/z, z0.b, #15"
+
+  -
+    input:
+      bytes: [ 0x10, 0x00, 0x4f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpgt p0.h, p0/z, z0.h, #15"
+
+  -
+    input:
+      bytes: [ 0x10, 0x00, 0x8f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpgt p0.s, p0/z, z0.s, #15"
+
+  -
+    input:
+      bytes: [ 0x10, 0x00, 0xcf, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpgt p0.d, p0/z, z0.d, #15"
+
+  -
+    input:
+      bytes: [ 0x10, 0x80, 0x00, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpgt p0.b, p0/z, z0.b, z0.b"
+
+  -
+    input:
+      bytes: [ 0x10, 0x80, 0x40, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpgt p0.h, p0/z, z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x10, 0x80, 0x80, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpgt p0.s, p0/z, z0.s, z0.s"
+
+  -
+    input:
+      bytes: [ 0x10, 0x80, 0xc0, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpgt p0.d, p0/z, z0.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0x10, 0x40, 0x00, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpgt p0.b, p0/z, z0.b, z0.d"
+
+  -
+    input:
+      bytes: [ 0x10, 0x40, 0x40, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpgt p0.h, p0/z, z0.h, z0.d"
+
+  -
+    input:
+      bytes: [ 0x10, 0x40, 0x80, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpgt p0.s, p0/z, z0.s, z0.d"
+
+  -
+    input:
+      bytes: [ 0x10, 0x00, 0x10, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpgt p0.b, p0/z, z0.b, #-16"
+
+  -
+    input:
+      bytes: [ 0x10, 0x00, 0x50, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpgt p0.h, p0/z, z0.h, #-16"
+
+  -
+    input:
+      bytes: [ 0x10, 0x00, 0x90, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpgt p0.s, p0/z, z0.s, #-16"
+
+  -
+    input:
+      bytes: [ 0x10, 0x00, 0xd0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpgt p0.d, p0/z, z0.d, #-16"
+
+  -
+    input:
+      bytes: [ 0x10, 0x00, 0x0f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpgt p0.b, p0/z, z0.b, #15"
+
+  -
+    input:
+      bytes: [ 0x10, 0x00, 0x4f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpgt p0.h, p0/z, z0.h, #15"
+
+  -
+    input:
+      bytes: [ 0x10, 0x00, 0x8f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpgt p0.s, p0/z, z0.s, #15"
+
+  -
+    input:
+      bytes: [ 0x10, 0x00, 0xcf, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpgt p0.d, p0/z, z0.d, #15"
diff --git a/tests/MC/AArch64/SVE/cmphi.s.yaml b/tests/MC/AArch64/SVE/cmphi.s.yaml
new file mode 100644
index 000000000..7396400ac
--- /dev/null
+++ b/tests/MC/AArch64/SVE/cmphi.s.yaml
@@ -0,0 +1,300 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x10, 0x00, 0x00, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmphi p0.b, p0/z, z0.b, z0.b"
+
+  -
+    input:
+      bytes: [ 0x10, 0x00, 0x40, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmphi p0.h, p0/z, z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x10, 0x00, 0x80, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmphi p0.s, p0/z, z0.s, z0.s"
+
+  -
+    input:
+      bytes: [ 0x10, 0x00, 0xc0, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmphi p0.d, p0/z, z0.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0x10, 0xc0, 0x00, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmphi p0.b, p0/z, z0.b, z0.d"
+
+  -
+    input:
+      bytes: [ 0x10, 0xc0, 0x40, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmphi p0.h, p0/z, z0.h, z0.d"
+
+  -
+    input:
+      bytes: [ 0x10, 0xc0, 0x80, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmphi p0.s, p0/z, z0.s, z0.d"
+
+  -
+    input:
+      bytes: [ 0x10, 0x00, 0x20, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmphi p0.b, p0/z, z0.b, #0"
+
+  -
+    input:
+      bytes: [ 0x10, 0x00, 0x60, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmphi p0.h, p0/z, z0.h, #0"
+
+  -
+    input:
+      bytes: [ 0x10, 0x00, 0xa0, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmphi p0.s, p0/z, z0.s, #0"
+
+  -
+    input:
+      bytes: [ 0x10, 0x00, 0xe0, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmphi p0.d, p0/z, z0.d, #0"
+
+  -
+    input:
+      bytes: [ 0x10, 0xc0, 0x3f, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmphi p0.b, p0/z, z0.b, #127"
+
+  -
+    input:
+      bytes: [ 0x10, 0xc0, 0x7f, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmphi p0.h, p0/z, z0.h, #127"
+
+  -
+    input:
+      bytes: [ 0x10, 0xc0, 0xbf, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmphi p0.s, p0/z, z0.s, #127"
+
+  -
+    input:
+      bytes: [ 0x10, 0xc0, 0xff, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmphi p0.d, p0/z, z0.d, #127"
+
+  -
+    input:
+      bytes: [ 0x10, 0x00, 0x00, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmphi p0.b, p0/z, z0.b, z0.b"
+
+  -
+    input:
+      bytes: [ 0x10, 0x00, 0x40, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmphi p0.h, p0/z, z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x10, 0x00, 0x80, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmphi p0.s, p0/z, z0.s, z0.s"
+
+  -
+    input:
+      bytes: [ 0x10, 0x00, 0xc0, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmphi p0.d, p0/z, z0.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0x10, 0xc0, 0x00, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmphi p0.b, p0/z, z0.b, z0.d"
+
+  -
+    input:
+      bytes: [ 0x10, 0xc0, 0x40, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmphi p0.h, p0/z, z0.h, z0.d"
+
+  -
+    input:
+      bytes: [ 0x10, 0xc0, 0x80, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmphi p0.s, p0/z, z0.s, z0.d"
+
+  -
+    input:
+      bytes: [ 0x10, 0x00, 0x20, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmphi p0.b, p0/z, z0.b, #0"
+
+  -
+    input:
+      bytes: [ 0x10, 0x00, 0x60, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmphi p0.h, p0/z, z0.h, #0"
+
+  -
+    input:
+      bytes: [ 0x10, 0x00, 0xa0, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmphi p0.s, p0/z, z0.s, #0"
+
+  -
+    input:
+      bytes: [ 0x10, 0x00, 0xe0, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmphi p0.d, p0/z, z0.d, #0"
+
+  -
+    input:
+      bytes: [ 0x10, 0xc0, 0x3f, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmphi p0.b, p0/z, z0.b, #127"
+
+  -
+    input:
+      bytes: [ 0x10, 0xc0, 0x7f, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmphi p0.h, p0/z, z0.h, #127"
+
+  -
+    input:
+      bytes: [ 0x10, 0xc0, 0xbf, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmphi p0.s, p0/z, z0.s, #127"
+
+  -
+    input:
+      bytes: [ 0x10, 0xc0, 0xff, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmphi p0.d, p0/z, z0.d, #127"
diff --git a/tests/MC/AArch64/SVE/cmphs.s.yaml b/tests/MC/AArch64/SVE/cmphs.s.yaml
new file mode 100644
index 000000000..ef7f66121
--- /dev/null
+++ b/tests/MC/AArch64/SVE/cmphs.s.yaml
@@ -0,0 +1,300 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x00, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmphs p0.b, p0/z, z0.b, z0.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x40, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmphs p0.h, p0/z, z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x80, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmphs p0.s, p0/z, z0.s, z0.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0xc0, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmphs p0.d, p0/z, z0.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x00, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmphs p0.b, p0/z, z0.b, z0.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x40, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmphs p0.h, p0/z, z0.h, z0.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x80, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmphs p0.s, p0/z, z0.s, z0.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x20, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmphs p0.b, p0/z, z0.b, #0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x60, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmphs p0.h, p0/z, z0.h, #0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0xa0, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmphs p0.s, p0/z, z0.s, #0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0xe0, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmphs p0.d, p0/z, z0.d, #0"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x3f, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmphs p0.b, p0/z, z0.b, #127"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x7f, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmphs p0.h, p0/z, z0.h, #127"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0xbf, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmphs p0.s, p0/z, z0.s, #127"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0xff, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmphs p0.d, p0/z, z0.d, #127"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x00, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmphs p0.b, p0/z, z0.b, z0.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x40, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmphs p0.h, p0/z, z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x80, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmphs p0.s, p0/z, z0.s, z0.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0xc0, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmphs p0.d, p0/z, z0.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x00, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmphs p0.b, p0/z, z0.b, z0.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x40, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmphs p0.h, p0/z, z0.h, z0.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x80, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmphs p0.s, p0/z, z0.s, z0.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x20, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmphs p0.b, p0/z, z0.b, #0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x60, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmphs p0.h, p0/z, z0.h, #0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0xa0, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmphs p0.s, p0/z, z0.s, #0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0xe0, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmphs p0.d, p0/z, z0.d, #0"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x3f, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmphs p0.b, p0/z, z0.b, #127"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x7f, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmphs p0.h, p0/z, z0.h, #127"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0xbf, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmphs p0.s, p0/z, z0.s, #127"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0xff, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmphs p0.d, p0/z, z0.d, #127"
diff --git a/tests/MC/AArch64/SVE/cmple.s.yaml b/tests/MC/AArch64/SVE/cmple.s.yaml
new file mode 100644
index 000000000..6bca879ed
--- /dev/null
+++ b/tests/MC/AArch64/SVE/cmple.s.yaml
@@ -0,0 +1,300 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x00, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpge p0.b, p0/z, z1.b, z0.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x40, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpge p0.h, p0/z, z1.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x80, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpge p0.s, p0/z, z1.s, z0.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0xc0, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpge p0.d, p0/z, z1.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0x10, 0x60, 0x00, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmple p0.b, p0/z, z0.b, z0.d"
+
+  -
+    input:
+      bytes: [ 0x10, 0x60, 0x40, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmple p0.h, p0/z, z0.h, z0.d"
+
+  -
+    input:
+      bytes: [ 0x10, 0x60, 0x80, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmple p0.s, p0/z, z0.s, z0.d"
+
+  -
+    input:
+      bytes: [ 0x10, 0x20, 0x10, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmple p0.b, p0/z, z0.b, #-16"
+
+  -
+    input:
+      bytes: [ 0x10, 0x20, 0x50, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmple p0.h, p0/z, z0.h, #-16"
+
+  -
+    input:
+      bytes: [ 0x10, 0x20, 0x90, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmple p0.s, p0/z, z0.s, #-16"
+
+  -
+    input:
+      bytes: [ 0x10, 0x20, 0xd0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmple p0.d, p0/z, z0.d, #-16"
+
+  -
+    input:
+      bytes: [ 0x10, 0x20, 0x0f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmple p0.b, p0/z, z0.b, #15"
+
+  -
+    input:
+      bytes: [ 0x10, 0x20, 0x4f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmple p0.h, p0/z, z0.h, #15"
+
+  -
+    input:
+      bytes: [ 0x10, 0x20, 0x8f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmple p0.s, p0/z, z0.s, #15"
+
+  -
+    input:
+      bytes: [ 0x10, 0x20, 0xcf, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmple p0.d, p0/z, z0.d, #15"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x00, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpge p0.b, p0/z, z1.b, z0.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x40, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpge p0.h, p0/z, z1.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x80, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpge p0.s, p0/z, z1.s, z0.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0xc0, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpge p0.d, p0/z, z1.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0x10, 0x60, 0x00, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmple p0.b, p0/z, z0.b, z0.d"
+
+  -
+    input:
+      bytes: [ 0x10, 0x60, 0x40, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmple p0.h, p0/z, z0.h, z0.d"
+
+  -
+    input:
+      bytes: [ 0x10, 0x60, 0x80, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmple p0.s, p0/z, z0.s, z0.d"
+
+  -
+    input:
+      bytes: [ 0x10, 0x20, 0x10, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmple p0.b, p0/z, z0.b, #-16"
+
+  -
+    input:
+      bytes: [ 0x10, 0x20, 0x50, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmple p0.h, p0/z, z0.h, #-16"
+
+  -
+    input:
+      bytes: [ 0x10, 0x20, 0x90, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmple p0.s, p0/z, z0.s, #-16"
+
+  -
+    input:
+      bytes: [ 0x10, 0x20, 0xd0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmple p0.d, p0/z, z0.d, #-16"
+
+  -
+    input:
+      bytes: [ 0x10, 0x20, 0x0f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmple p0.b, p0/z, z0.b, #15"
+
+  -
+    input:
+      bytes: [ 0x10, 0x20, 0x4f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmple p0.h, p0/z, z0.h, #15"
+
+  -
+    input:
+      bytes: [ 0x10, 0x20, 0x8f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmple p0.s, p0/z, z0.s, #15"
+
+  -
+    input:
+      bytes: [ 0x10, 0x20, 0xcf, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmple p0.d, p0/z, z0.d, #15"
diff --git a/tests/MC/AArch64/SVE/cmplo.s.yaml b/tests/MC/AArch64/SVE/cmplo.s.yaml
new file mode 100644
index 000000000..b928dfa71
--- /dev/null
+++ b/tests/MC/AArch64/SVE/cmplo.s.yaml
@@ -0,0 +1,300 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x30, 0x00, 0x00, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmphi p0.b, p0/z, z1.b, z0.b"
+
+  -
+    input:
+      bytes: [ 0x30, 0x00, 0x40, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmphi p0.h, p0/z, z1.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x30, 0x00, 0x80, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmphi p0.s, p0/z, z1.s, z0.s"
+
+  -
+    input:
+      bytes: [ 0x30, 0x00, 0xc0, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmphi p0.d, p0/z, z1.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x00, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmplo p0.b, p0/z, z0.b, z0.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x40, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmplo p0.h, p0/z, z0.h, z0.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x80, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmplo p0.s, p0/z, z0.s, z0.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x20, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmplo p0.b, p0/z, z0.b, #0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x60, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmplo p0.h, p0/z, z0.h, #0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0xa0, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmplo p0.s, p0/z, z0.s, #0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0xe0, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmplo p0.d, p0/z, z0.d, #0"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x3f, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmplo p0.b, p0/z, z0.b, #127"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x7f, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmplo p0.h, p0/z, z0.h, #127"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xbf, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmplo p0.s, p0/z, z0.s, #127"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xff, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmplo p0.d, p0/z, z0.d, #127"
+
+  -
+    input:
+      bytes: [ 0x30, 0x00, 0x00, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmphi p0.b, p0/z, z1.b, z0.b"
+
+  -
+    input:
+      bytes: [ 0x30, 0x00, 0x40, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmphi p0.h, p0/z, z1.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x30, 0x00, 0x80, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmphi p0.s, p0/z, z1.s, z0.s"
+
+  -
+    input:
+      bytes: [ 0x30, 0x00, 0xc0, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmphi p0.d, p0/z, z1.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x00, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmplo p0.b, p0/z, z0.b, z0.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x40, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmplo p0.h, p0/z, z0.h, z0.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x80, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmplo p0.s, p0/z, z0.s, z0.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x20, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmplo p0.b, p0/z, z0.b, #0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x60, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmplo p0.h, p0/z, z0.h, #0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0xa0, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmplo p0.s, p0/z, z0.s, #0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0xe0, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmplo p0.d, p0/z, z0.d, #0"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x3f, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmplo p0.b, p0/z, z0.b, #127"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x7f, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmplo p0.h, p0/z, z0.h, #127"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xbf, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmplo p0.s, p0/z, z0.s, #127"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xff, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmplo p0.d, p0/z, z0.d, #127"
diff --git a/tests/MC/AArch64/SVE/cmpls.s.yaml b/tests/MC/AArch64/SVE/cmpls.s.yaml
new file mode 100644
index 000000000..ef0d933c9
--- /dev/null
+++ b/tests/MC/AArch64/SVE/cmpls.s.yaml
@@ -0,0 +1,300 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x00, 0x00, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmphs p0.b, p0/z, z1.b, z0.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x00, 0x40, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmphs p0.h, p0/z, z1.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x00, 0x80, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmphs p0.s, p0/z, z1.s, z0.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x00, 0xc0, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmphs p0.d, p0/z, z1.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0x10, 0xe0, 0x00, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpls p0.b, p0/z, z0.b, z0.d"
+
+  -
+    input:
+      bytes: [ 0x10, 0xe0, 0x40, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpls p0.h, p0/z, z0.h, z0.d"
+
+  -
+    input:
+      bytes: [ 0x10, 0xe0, 0x80, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpls p0.s, p0/z, z0.s, z0.d"
+
+  -
+    input:
+      bytes: [ 0x10, 0x20, 0x20, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpls p0.b, p0/z, z0.b, #0"
+
+  -
+    input:
+      bytes: [ 0x10, 0x20, 0x60, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpls p0.h, p0/z, z0.h, #0"
+
+  -
+    input:
+      bytes: [ 0x10, 0x20, 0xa0, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpls p0.s, p0/z, z0.s, #0"
+
+  -
+    input:
+      bytes: [ 0x10, 0x20, 0xe0, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpls p0.d, p0/z, z0.d, #0"
+
+  -
+    input:
+      bytes: [ 0x10, 0xe0, 0x3f, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpls p0.b, p0/z, z0.b, #127"
+
+  -
+    input:
+      bytes: [ 0x10, 0xe0, 0x7f, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpls p0.h, p0/z, z0.h, #127"
+
+  -
+    input:
+      bytes: [ 0x10, 0xe0, 0xbf, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpls p0.s, p0/z, z0.s, #127"
+
+  -
+    input:
+      bytes: [ 0x10, 0xe0, 0xff, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpls p0.d, p0/z, z0.d, #127"
+
+  -
+    input:
+      bytes: [ 0x20, 0x00, 0x00, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmphs p0.b, p0/z, z1.b, z0.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x00, 0x40, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmphs p0.h, p0/z, z1.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x00, 0x80, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmphs p0.s, p0/z, z1.s, z0.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x00, 0xc0, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmphs p0.d, p0/z, z1.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0x10, 0xe0, 0x00, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpls p0.b, p0/z, z0.b, z0.d"
+
+  -
+    input:
+      bytes: [ 0x10, 0xe0, 0x40, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpls p0.h, p0/z, z0.h, z0.d"
+
+  -
+    input:
+      bytes: [ 0x10, 0xe0, 0x80, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpls p0.s, p0/z, z0.s, z0.d"
+
+  -
+    input:
+      bytes: [ 0x10, 0x20, 0x20, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpls p0.b, p0/z, z0.b, #0"
+
+  -
+    input:
+      bytes: [ 0x10, 0x20, 0x60, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpls p0.h, p0/z, z0.h, #0"
+
+  -
+    input:
+      bytes: [ 0x10, 0x20, 0xa0, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpls p0.s, p0/z, z0.s, #0"
+
+  -
+    input:
+      bytes: [ 0x10, 0x20, 0xe0, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpls p0.d, p0/z, z0.d, #0"
+
+  -
+    input:
+      bytes: [ 0x10, 0xe0, 0x3f, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpls p0.b, p0/z, z0.b, #127"
+
+  -
+    input:
+      bytes: [ 0x10, 0xe0, 0x7f, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpls p0.h, p0/z, z0.h, #127"
+
+  -
+    input:
+      bytes: [ 0x10, 0xe0, 0xbf, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpls p0.s, p0/z, z0.s, #127"
+
+  -
+    input:
+      bytes: [ 0x10, 0xe0, 0xff, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpls p0.d, p0/z, z0.d, #127"
diff --git a/tests/MC/AArch64/SVE/cmplt.s.yaml b/tests/MC/AArch64/SVE/cmplt.s.yaml
new file mode 100644
index 000000000..40a15b06b
--- /dev/null
+++ b/tests/MC/AArch64/SVE/cmplt.s.yaml
@@ -0,0 +1,300 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x30, 0x80, 0x00, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpgt p0.b, p0/z, z1.b, z0.b"
+
+  -
+    input:
+      bytes: [ 0x30, 0x80, 0x40, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpgt p0.h, p0/z, z1.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x30, 0x80, 0x80, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpgt p0.s, p0/z, z1.s, z0.s"
+
+  -
+    input:
+      bytes: [ 0x30, 0x80, 0xc0, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpgt p0.d, p0/z, z1.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0x00, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmplt p0.b, p0/z, z0.b, z0.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0x40, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmplt p0.h, p0/z, z0.h, z0.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0x80, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmplt p0.s, p0/z, z0.s, z0.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x10, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmplt p0.b, p0/z, z0.b, #-16"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x50, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmplt p0.h, p0/z, z0.h, #-16"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x90, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmplt p0.s, p0/z, z0.s, #-16"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0xd0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmplt p0.d, p0/z, z0.d, #-16"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x0f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmplt p0.b, p0/z, z0.b, #15"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x4f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmplt p0.h, p0/z, z0.h, #15"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x8f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmplt p0.s, p0/z, z0.s, #15"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0xcf, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmplt p0.d, p0/z, z0.d, #15"
+
+  -
+    input:
+      bytes: [ 0x30, 0x80, 0x00, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpgt p0.b, p0/z, z1.b, z0.b"
+
+  -
+    input:
+      bytes: [ 0x30, 0x80, 0x40, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpgt p0.h, p0/z, z1.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x30, 0x80, 0x80, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpgt p0.s, p0/z, z1.s, z0.s"
+
+  -
+    input:
+      bytes: [ 0x30, 0x80, 0xc0, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpgt p0.d, p0/z, z1.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0x00, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmplt p0.b, p0/z, z0.b, z0.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0x40, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmplt p0.h, p0/z, z0.h, z0.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0x80, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmplt p0.s, p0/z, z0.s, z0.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x10, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmplt p0.b, p0/z, z0.b, #-16"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x50, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmplt p0.h, p0/z, z0.h, #-16"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x90, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmplt p0.s, p0/z, z0.s, #-16"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0xd0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmplt p0.d, p0/z, z0.d, #-16"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x0f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmplt p0.b, p0/z, z0.b, #15"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x4f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmplt p0.h, p0/z, z0.h, #15"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x8f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmplt p0.s, p0/z, z0.s, #15"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0xcf, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmplt p0.d, p0/z, z0.d, #15"
diff --git a/tests/MC/AArch64/SVE/cmpne.s.yaml b/tests/MC/AArch64/SVE/cmpne.s.yaml
new file mode 100644
index 000000000..0ec9f9783
--- /dev/null
+++ b/tests/MC/AArch64/SVE/cmpne.s.yaml
@@ -0,0 +1,300 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x10, 0xa0, 0x00, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpne p0.b, p0/z, z0.b, z0.b"
+
+  -
+    input:
+      bytes: [ 0x10, 0xa0, 0x40, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpne p0.h, p0/z, z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x10, 0xa0, 0x80, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpne p0.s, p0/z, z0.s, z0.s"
+
+  -
+    input:
+      bytes: [ 0x10, 0xa0, 0xc0, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpne p0.d, p0/z, z0.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0x10, 0x20, 0x00, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpne p0.b, p0/z, z0.b, z0.d"
+
+  -
+    input:
+      bytes: [ 0x10, 0x20, 0x40, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpne p0.h, p0/z, z0.h, z0.d"
+
+  -
+    input:
+      bytes: [ 0x10, 0x20, 0x80, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpne p0.s, p0/z, z0.s, z0.d"
+
+  -
+    input:
+      bytes: [ 0x10, 0x80, 0x10, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpne p0.b, p0/z, z0.b, #-16"
+
+  -
+    input:
+      bytes: [ 0x10, 0x80, 0x50, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpne p0.h, p0/z, z0.h, #-16"
+
+  -
+    input:
+      bytes: [ 0x10, 0x80, 0x90, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpne p0.s, p0/z, z0.s, #-16"
+
+  -
+    input:
+      bytes: [ 0x10, 0x80, 0xd0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpne p0.d, p0/z, z0.d, #-16"
+
+  -
+    input:
+      bytes: [ 0x10, 0x80, 0x0f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpne p0.b, p0/z, z0.b, #15"
+
+  -
+    input:
+      bytes: [ 0x10, 0x80, 0x4f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpne p0.h, p0/z, z0.h, #15"
+
+  -
+    input:
+      bytes: [ 0x10, 0x80, 0x8f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpne p0.s, p0/z, z0.s, #15"
+
+  -
+    input:
+      bytes: [ 0x10, 0x80, 0xcf, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpne p0.d, p0/z, z0.d, #15"
+
+  -
+    input:
+      bytes: [ 0x10, 0xa0, 0x00, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpne p0.b, p0/z, z0.b, z0.b"
+
+  -
+    input:
+      bytes: [ 0x10, 0xa0, 0x40, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpne p0.h, p0/z, z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x10, 0xa0, 0x80, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpne p0.s, p0/z, z0.s, z0.s"
+
+  -
+    input:
+      bytes: [ 0x10, 0xa0, 0xc0, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpne p0.d, p0/z, z0.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0x10, 0x20, 0x00, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpne p0.b, p0/z, z0.b, z0.d"
+
+  -
+    input:
+      bytes: [ 0x10, 0x20, 0x40, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpne p0.h, p0/z, z0.h, z0.d"
+
+  -
+    input:
+      bytes: [ 0x10, 0x20, 0x80, 0x24 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpne p0.s, p0/z, z0.s, z0.d"
+
+  -
+    input:
+      bytes: [ 0x10, 0x80, 0x10, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpne p0.b, p0/z, z0.b, #-16"
+
+  -
+    input:
+      bytes: [ 0x10, 0x80, 0x50, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpne p0.h, p0/z, z0.h, #-16"
+
+  -
+    input:
+      bytes: [ 0x10, 0x80, 0x90, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpne p0.s, p0/z, z0.s, #-16"
+
+  -
+    input:
+      bytes: [ 0x10, 0x80, 0xd0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpne p0.d, p0/z, z0.d, #-16"
+
+  -
+    input:
+      bytes: [ 0x10, 0x80, 0x0f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpne p0.b, p0/z, z0.b, #15"
+
+  -
+    input:
+      bytes: [ 0x10, 0x80, 0x4f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpne p0.h, p0/z, z0.h, #15"
+
+  -
+    input:
+      bytes: [ 0x10, 0x80, 0x8f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpne p0.s, p0/z, z0.s, #15"
+
+  -
+    input:
+      bytes: [ 0x10, 0x80, 0xcf, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpne p0.d, p0/z, z0.d, #15"
diff --git a/tests/MC/AArch64/SVE/cnot.s.yaml b/tests/MC/AArch64/SVE/cnot.s.yaml
new file mode 100644
index 000000000..bbce78642
--- /dev/null
+++ b/tests/MC/AArch64/SVE/cnot.s.yaml
@@ -0,0 +1,160 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x1b, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cnot z31.b, p7/m, z31.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x5b, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cnot z31.h, p7/m, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x9b, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cnot z31.s, p7/m, z31.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0xdb, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cnot z31.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4.d, p7/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xbf, 0xdb, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cnot z4.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4, z6"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xbf, 0xdb, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cnot z4.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x1b, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cnot z31.b, p7/m, z31.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x5b, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cnot z31.h, p7/m, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x9b, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cnot z31.s, p7/m, z31.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0xdb, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cnot z31.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4.d, p7/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xbf, 0xdb, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cnot z4.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4, z6"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xbf, 0xdb, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cnot z4.d, p7/m, z31.d"
diff --git a/tests/MC/AArch64/SVE/cnt.s.yaml b/tests/MC/AArch64/SVE/cnt.s.yaml
new file mode 100644
index 000000000..f602570e3
--- /dev/null
+++ b/tests/MC/AArch64/SVE/cnt.s.yaml
@@ -0,0 +1,160 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x1a, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cnt z31.b, p7/m, z31.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x5a, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cnt z31.h, p7/m, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x9a, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cnt z31.s, p7/m, z31.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0xda, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cnt z31.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4.d, p7/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xbf, 0xda, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cnt z4.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4, z6"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xbf, 0xda, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cnt z4.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x1a, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cnt z31.b, p7/m, z31.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x5a, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cnt z31.h, p7/m, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x9a, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cnt z31.s, p7/m, z31.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0xda, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cnt z31.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4.d, p7/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xbf, 0xda, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cnt z4.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4, z6"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xbf, 0xda, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cnt z4.d, p7/m, z31.d"
diff --git a/tests/MC/AArch64/SVE/cntb.s.yaml b/tests/MC/AArch64/SVE/cntb.s.yaml
new file mode 100644
index 000000000..89c2f042f
--- /dev/null
+++ b/tests/MC/AArch64/SVE/cntb.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xe0, 0xe3, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cntb x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xe3, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cntb x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xe3, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cntb x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xe3, 0x2f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cntb x0, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cntb x0, pow2"
+
+  -
+    input:
+      bytes: [ 0x80, 0xe3, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cntb x0, #28"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xe3, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cntb x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xe3, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cntb x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xe3, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cntb x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xe3, 0x2f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cntb x0, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cntb x0, pow2"
+
+  -
+    input:
+      bytes: [ 0x80, 0xe3, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cntb x0, #28"
diff --git a/tests/MC/AArch64/SVE/cntd.s.yaml b/tests/MC/AArch64/SVE/cntd.s.yaml
new file mode 100644
index 000000000..81897e9d0
--- /dev/null
+++ b/tests/MC/AArch64/SVE/cntd.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xe0, 0xe3, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cntd x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xe3, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cntd x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xe3, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cntd x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xe3, 0xef, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cntd x0, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cntd x0, pow2"
+
+  -
+    input:
+      bytes: [ 0x80, 0xe3, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cntd x0, #28"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xe3, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cntd x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xe3, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cntd x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xe3, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cntd x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xe3, 0xef, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cntd x0, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cntd x0, pow2"
+
+  -
+    input:
+      bytes: [ 0x80, 0xe3, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cntd x0, #28"
diff --git a/tests/MC/AArch64/SVE/cnth.s.yaml b/tests/MC/AArch64/SVE/cnth.s.yaml
new file mode 100644
index 000000000..4c33cde5e
--- /dev/null
+++ b/tests/MC/AArch64/SVE/cnth.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xe0, 0xe3, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cnth x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xe3, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cnth x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xe3, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cnth x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xe3, 0x6f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cnth x0, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cnth x0, pow2"
+
+  -
+    input:
+      bytes: [ 0x80, 0xe3, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cnth x0, #28"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xe3, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cnth x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xe3, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cnth x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xe3, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cnth x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xe3, 0x6f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cnth x0, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cnth x0, pow2"
+
+  -
+    input:
+      bytes: [ 0x80, 0xe3, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cnth x0, #28"
diff --git a/tests/MC/AArch64/SVE/cntp.s.yaml b/tests/MC/AArch64/SVE/cntp.s.yaml
new file mode 100644
index 000000000..b975138bd
--- /dev/null
+++ b/tests/MC/AArch64/SVE/cntp.s.yaml
@@ -0,0 +1,80 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xbc, 0x20, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cntp x0, p15, p0.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0xbc, 0x60, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cntp x0, p15, p0.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0xbc, 0xa0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cntp x0, p15, p0.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0xbc, 0xe0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cntp x0, p15, p0.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0xbc, 0x20, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cntp x0, p15, p0.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0xbc, 0x60, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cntp x0, p15, p0.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0xbc, 0xa0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cntp x0, p15, p0.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0xbc, 0xe0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cntp x0, p15, p0.d"
diff --git a/tests/MC/AArch64/SVE/cntw.s.yaml b/tests/MC/AArch64/SVE/cntw.s.yaml
new file mode 100644
index 000000000..0121bebf0
--- /dev/null
+++ b/tests/MC/AArch64/SVE/cntw.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xe0, 0xe3, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cntw x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xe3, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cntw x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xe3, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cntw x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xe3, 0xaf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cntw x0, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cntw x0, pow2"
+
+  -
+    input:
+      bytes: [ 0x80, 0xe3, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "cntw x0, #28"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xe3, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cntw x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xe3, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cntw x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xe3, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cntw x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xe3, 0xaf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cntw x0, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cntw x0, pow2"
+
+  -
+    input:
+      bytes: [ 0x80, 0xe3, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cntw x0, #28"
diff --git a/tests/MC/AArch64/SVE/compact.s.yaml b/tests/MC/AArch64/SVE/compact.s.yaml
new file mode 100644
index 000000000..4940661a1
--- /dev/null
+++ b/tests/MC/AArch64/SVE/compact.s.yaml
@@ -0,0 +1,20 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xff, 0x9f, 0xa1, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "compact z31.s, p7, z31.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0x9f, 0xe1, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "compact z31.d, p7, z31.d"
diff --git a/tests/MC/AArch64/SVE/cpy.s.yaml b/tests/MC/AArch64/SVE/cpy.s.yaml
new file mode 100644
index 000000000..4564c697d
--- /dev/null
+++ b/tests/MC/AArch64/SVE/cpy.s.yaml
@@ -0,0 +1,1180 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x28, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.b, p0/m, w0"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x68, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.h, p0/m, w0"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xa8, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.s, p0/m, w0"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xe8, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.d, p0/m, x0"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x28, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z31.b, p7/m, wsp"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x68, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z31.h, p7/m, wsp"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0xa8, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z31.s, p7/m, wsp"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0xe8, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z31.d, p7/m, sp"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x20, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.b, p0/m, b0"
+
+  -
+    input:
+      bytes: [ 0xff, 0x9f, 0x20, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z31.b, p7/m, b31"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x60, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.h, p0/m, h0"
+
+  -
+    input:
+      bytes: [ 0xff, 0x9f, 0x60, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z31.h, p7/m, h31"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xa0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.s, p0/m, s0"
+
+  -
+    input:
+      bytes: [ 0xff, 0x9f, 0xa0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z31.s, p7/m, s31"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xe0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.d, p0/m, d0"
+
+  -
+    input:
+      bytes: [ 0xff, 0x9f, 0xe0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z31.d, p7/m, d31"
+
+  -
+    input:
+      bytes: [ 0x05, 0x10, 0x10, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z5.b, p0/z, #-128"
+
+  -
+    input:
+      bytes: [ 0xe5, 0x0f, 0x10, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z5.b, p0/z, #127"
+
+  -
+    input:
+      bytes: [ 0xe5, 0x1f, 0x10, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z5.b, p0/z, #-1"
+
+  -
+    input:
+      bytes: [ 0x15, 0x10, 0x50, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.h, p0/z, #-128"
+
+  -
+    input:
+      bytes: [ 0x15, 0x30, 0x50, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.h, p0/z, #-32768"
+
+  -
+    input:
+      bytes: [ 0x15, 0x30, 0x50, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.h, p0/z, #-32768"
+
+  -
+    input:
+      bytes: [ 0xf5, 0x0f, 0x50, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.h, p0/z, #127"
+
+  -
+    input:
+      bytes: [ 0xf5, 0x2f, 0x50, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.h, p0/z, #32512"
+
+  -
+    input:
+      bytes: [ 0xf5, 0x2f, 0x50, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.h, p0/z, #32512"
+
+  -
+    input:
+      bytes: [ 0x15, 0x10, 0x90, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.s, p0/z, #-128"
+
+  -
+    input:
+      bytes: [ 0x15, 0x30, 0x90, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.s, p0/z, #-32768"
+
+  -
+    input:
+      bytes: [ 0x15, 0x30, 0x90, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.s, p0/z, #-32768"
+
+  -
+    input:
+      bytes: [ 0xf5, 0x0f, 0x90, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.s, p0/z, #127"
+
+  -
+    input:
+      bytes: [ 0xf5, 0x2f, 0x90, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.s, p0/z, #32512"
+
+  -
+    input:
+      bytes: [ 0xf5, 0x2f, 0x90, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.s, p0/z, #32512"
+
+  -
+    input:
+      bytes: [ 0x15, 0x10, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.d, p0/z, #-128"
+
+  -
+    input:
+      bytes: [ 0x15, 0x30, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.d, p0/z, #-32768"
+
+  -
+    input:
+      bytes: [ 0x15, 0x30, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.d, p0/z, #-32768"
+
+  -
+    input:
+      bytes: [ 0xf5, 0x0f, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.d, p0/z, #127"
+
+  -
+    input:
+      bytes: [ 0xf5, 0x2f, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.d, p0/z, #32512"
+
+  -
+    input:
+      bytes: [ 0xf5, 0x2f, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.d, p0/z, #32512"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x0f, 0x10, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.b, p0/z, #127"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x2f, 0x50, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.h, p0/z, #32512"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x2f, 0x50, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.h, p0/z, #32512"
+
+  -
+    input:
+      bytes: [ 0x05, 0x50, 0x1f, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z5.b, p15/m, #-128"
+
+  -
+    input:
+      bytes: [ 0x15, 0x50, 0x5f, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.h, p15/m, #-128"
+
+  -
+    input:
+      bytes: [ 0x15, 0x70, 0x5f, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.h, p15/m, #-32768"
+
+  -
+    input:
+      bytes: [ 0x15, 0x50, 0x9f, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.s, p15/m, #-128"
+
+  -
+    input:
+      bytes: [ 0x15, 0x70, 0x9f, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.s, p15/m, #-32768"
+
+  -
+    input:
+      bytes: [ 0x15, 0x50, 0xdf, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.d, p15/m, #-128"
+
+  -
+    input:
+      bytes: [ 0x15, 0x70, 0xdf, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.d, p15/m, #-32768"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31.d, p7/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0xe8, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z31.d, p7/m, sp"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0xe8, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z31.d, p7/m, sp"
+
+  -
+    input:
+      bytes: [ 0x95, 0x3f, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z21.d, p7/z, z28.d"
+
+  -
+    input:
+      bytes: [ 0x15, 0x70, 0xd7, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.d, p7/m, #-32768"
+
+  -
+    input:
+      bytes: [ 0x95, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z21, z28"
+
+  -
+    input:
+      bytes: [ 0x15, 0x70, 0xdf, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.d, p15/m, #-32768"
+
+  -
+    input:
+      bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4.d, p7/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xe4, 0x9f, 0xe0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z4.d, p7/m, d31"
+
+  -
+    input:
+      bytes: [ 0xc4, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4, z6"
+
+  -
+    input:
+      bytes: [ 0xe4, 0x9f, 0xe0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z4.d, p7/m, d31"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x28, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.b, p0/m, w0"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x68, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.h, p0/m, w0"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xa8, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.s, p0/m, w0"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xe8, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.d, p0/m, x0"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x28, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z31.b, p7/m, wsp"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x68, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z31.h, p7/m, wsp"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0xa8, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z31.s, p7/m, wsp"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0xe8, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z31.d, p7/m, sp"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x20, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.b, p0/m, b0"
+
+  -
+    input:
+      bytes: [ 0xff, 0x9f, 0x20, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z31.b, p7/m, b31"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x60, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.h, p0/m, h0"
+
+  -
+    input:
+      bytes: [ 0xff, 0x9f, 0x60, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z31.h, p7/m, h31"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xa0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.s, p0/m, s0"
+
+  -
+    input:
+      bytes: [ 0xff, 0x9f, 0xa0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z31.s, p7/m, s31"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xe0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.d, p0/m, d0"
+
+  -
+    input:
+      bytes: [ 0xff, 0x9f, 0xe0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z31.d, p7/m, d31"
+
+  -
+    input:
+      bytes: [ 0x05, 0x10, 0x10, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z5.b, p0/z, #-128"
+
+  -
+    input:
+      bytes: [ 0xe5, 0x0f, 0x10, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z5.b, p0/z, #127"
+
+  -
+    input:
+      bytes: [ 0xe5, 0x1f, 0x10, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z5.b, p0/z, #-1"
+
+  -
+    input:
+      bytes: [ 0x15, 0x10, 0x50, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.h, p0/z, #-128"
+
+  -
+    input:
+      bytes: [ 0x15, 0x30, 0x50, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.h, p0/z, #-32768"
+
+  -
+    input:
+      bytes: [ 0x15, 0x30, 0x50, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.h, p0/z, #-32768"
+
+  -
+    input:
+      bytes: [ 0xf5, 0x0f, 0x50, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.h, p0/z, #127"
+
+  -
+    input:
+      bytes: [ 0xf5, 0x2f, 0x50, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.h, p0/z, #32512"
+
+  -
+    input:
+      bytes: [ 0xf5, 0x2f, 0x50, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.h, p0/z, #32512"
+
+  -
+    input:
+      bytes: [ 0x15, 0x10, 0x90, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.s, p0/z, #-128"
+
+  -
+    input:
+      bytes: [ 0x15, 0x30, 0x90, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.s, p0/z, #-32768"
+
+  -
+    input:
+      bytes: [ 0x15, 0x30, 0x90, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.s, p0/z, #-32768"
+
+  -
+    input:
+      bytes: [ 0xf5, 0x0f, 0x90, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.s, p0/z, #127"
+
+  -
+    input:
+      bytes: [ 0xf5, 0x2f, 0x90, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.s, p0/z, #32512"
+
+  -
+    input:
+      bytes: [ 0xf5, 0x2f, 0x90, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.s, p0/z, #32512"
+
+  -
+    input:
+      bytes: [ 0x15, 0x10, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.d, p0/z, #-128"
+
+  -
+    input:
+      bytes: [ 0x15, 0x30, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.d, p0/z, #-32768"
+
+  -
+    input:
+      bytes: [ 0x15, 0x30, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.d, p0/z, #-32768"
+
+  -
+    input:
+      bytes: [ 0xf5, 0x0f, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.d, p0/z, #127"
+
+  -
+    input:
+      bytes: [ 0xf5, 0x2f, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.d, p0/z, #32512"
+
+  -
+    input:
+      bytes: [ 0xf5, 0x2f, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.d, p0/z, #32512"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x0f, 0x10, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.b, p0/z, #127"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x2f, 0x50, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.h, p0/z, #32512"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x2f, 0x50, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.h, p0/z, #32512"
+
+  -
+    input:
+      bytes: [ 0x05, 0x50, 0x1f, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z5.b, p15/m, #-128"
+
+  -
+    input:
+      bytes: [ 0x15, 0x50, 0x5f, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.h, p15/m, #-128"
+
+  -
+    input:
+      bytes: [ 0x15, 0x70, 0x5f, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.h, p15/m, #-32768"
+
+  -
+    input:
+      bytes: [ 0x15, 0x50, 0x9f, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.s, p15/m, #-128"
+
+  -
+    input:
+      bytes: [ 0x15, 0x70, 0x9f, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.s, p15/m, #-32768"
+
+  -
+    input:
+      bytes: [ 0x15, 0x50, 0xdf, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.d, p15/m, #-128"
+
+  -
+    input:
+      bytes: [ 0x15, 0x70, 0xdf, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.d, p15/m, #-32768"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31.d, p7/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0xe8, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z31.d, p7/m, sp"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0xe8, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z31.d, p7/m, sp"
+
+  -
+    input:
+      bytes: [ 0x95, 0x3f, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z21.d, p7/z, z28.d"
+
+  -
+    input:
+      bytes: [ 0x15, 0x70, 0xd7, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.d, p7/m, #-32768"
+
+  -
+    input:
+      bytes: [ 0x95, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z21, z28"
+
+  -
+    input:
+      bytes: [ 0x15, 0x70, 0xdf, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.d, p15/m, #-32768"
+
+  -
+    input:
+      bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4.d, p7/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xe4, 0x9f, 0xe0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z4.d, p7/m, d31"
+
+  -
+    input:
+      bytes: [ 0xc4, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4, z6"
+
+  -
+    input:
+      bytes: [ 0xe4, 0x9f, 0xe0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z4.d, p7/m, d31"
diff --git a/tests/MC/AArch64/SVE/ctermeq.s.yaml b/tests/MC/AArch64/SVE/ctermeq.s.yaml
new file mode 100644
index 000000000..bae5b91a5
--- /dev/null
+++ b/tests/MC/AArch64/SVE/ctermeq.s.yaml
@@ -0,0 +1,80 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xc0, 0x23, 0xbf, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ctermeq w30, wzr"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x23, 0xbe, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ctermeq wzr, w30"
+
+  -
+    input:
+      bytes: [ 0xc0, 0x23, 0xff, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ctermeq x30, xzr"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x23, 0xfe, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ctermeq xzr, x30"
+
+  -
+    input:
+      bytes: [ 0xc0, 0x23, 0xbf, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ctermeq w30, wzr"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x23, 0xbe, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ctermeq wzr, w30"
+
+  -
+    input:
+      bytes: [ 0xc0, 0x23, 0xff, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ctermeq x30, xzr"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x23, 0xfe, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ctermeq xzr, x30"
diff --git a/tests/MC/AArch64/SVE/ctermne.s.yaml b/tests/MC/AArch64/SVE/ctermne.s.yaml
new file mode 100644
index 000000000..845f178a4
--- /dev/null
+++ b/tests/MC/AArch64/SVE/ctermne.s.yaml
@@ -0,0 +1,80 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xd0, 0x23, 0xbf, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ctermne w30, wzr"
+
+  -
+    input:
+      bytes: [ 0xf0, 0x23, 0xbe, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ctermne wzr, w30"
+
+  -
+    input:
+      bytes: [ 0xd0, 0x23, 0xff, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ctermne x30, xzr"
+
+  -
+    input:
+      bytes: [ 0xf0, 0x23, 0xfe, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ctermne xzr, x30"
+
+  -
+    input:
+      bytes: [ 0xd0, 0x23, 0xbf, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ctermne w30, wzr"
+
+  -
+    input:
+      bytes: [ 0xf0, 0x23, 0xbe, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ctermne wzr, w30"
+
+  -
+    input:
+      bytes: [ 0xd0, 0x23, 0xff, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ctermne x30, xzr"
+
+  -
+    input:
+      bytes: [ 0xf0, 0x23, 0xfe, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ctermne xzr, x30"
diff --git a/tests/MC/AArch64/SVE/decb.s.yaml b/tests/MC/AArch64/SVE/decb.s.yaml
new file mode 100644
index 000000000..df9ede72d
--- /dev/null
+++ b/tests/MC/AArch64/SVE/decb.s.yaml
@@ -0,0 +1,400 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xe0, 0xe7, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "decb x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xe7, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "decb x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xe7, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "decb x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xe7, 0x3f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "decb x0, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe4, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "decb x0, pow2"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe4, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "decb x0, vl1"
+
+  -
+    input:
+      bytes: [ 0x40, 0xe4, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "decb x0, vl2"
+
+  -
+    input:
+      bytes: [ 0x60, 0xe4, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "decb x0, vl3"
+
+  -
+    input:
+      bytes: [ 0x80, 0xe4, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "decb x0, vl4"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xe4, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "decb x0, vl5"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xe4, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "decb x0, vl6"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xe4, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "decb x0, vl7"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe5, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "decb x0, vl8"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe5, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "decb x0, vl16"
+
+  -
+    input:
+      bytes: [ 0x40, 0xe5, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "decb x0, vl32"
+
+  -
+    input:
+      bytes: [ 0x60, 0xe5, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "decb x0, vl64"
+
+  -
+    input:
+      bytes: [ 0x80, 0xe5, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "decb x0, vl128"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xe5, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "decb x0, vl256"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xe5, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "decb x0, #14"
+
+  -
+    input:
+      bytes: [ 0x80, 0xe7, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "decb x0, #28"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xe7, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "decb x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xe7, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "decb x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xe7, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "decb x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xe7, 0x3f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "decb x0, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe4, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "decb x0, pow2"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe4, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "decb x0, vl1"
+
+  -
+    input:
+      bytes: [ 0x40, 0xe4, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "decb x0, vl2"
+
+  -
+    input:
+      bytes: [ 0x60, 0xe4, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "decb x0, vl3"
+
+  -
+    input:
+      bytes: [ 0x80, 0xe4, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "decb x0, vl4"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xe4, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "decb x0, vl5"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xe4, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "decb x0, vl6"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xe4, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "decb x0, vl7"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe5, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "decb x0, vl8"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe5, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "decb x0, vl16"
+
+  -
+    input:
+      bytes: [ 0x40, 0xe5, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "decb x0, vl32"
+
+  -
+    input:
+      bytes: [ 0x60, 0xe5, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "decb x0, vl64"
+
+  -
+    input:
+      bytes: [ 0x80, 0xe5, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "decb x0, vl128"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xe5, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "decb x0, vl256"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xe5, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "decb x0, #14"
+
+  -
+    input:
+      bytes: [ 0x80, 0xe7, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "decb x0, #28"
diff --git a/tests/MC/AArch64/SVE/decd.s.yaml b/tests/MC/AArch64/SVE/decd.s.yaml
new file mode 100644
index 000000000..c3ef0cc61
--- /dev/null
+++ b/tests/MC/AArch64/SVE/decd.s.yaml
@@ -0,0 +1,400 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xe0, 0xe7, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "decd x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xe7, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "decd x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xe7, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "decd x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xe7, 0xff, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "decd x0, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe4, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "decd x0, pow2"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe4, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "decd x0, vl1"
+
+  -
+    input:
+      bytes: [ 0x40, 0xe4, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "decd x0, vl2"
+
+  -
+    input:
+      bytes: [ 0x60, 0xe4, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "decd x0, vl3"
+
+  -
+    input:
+      bytes: [ 0x80, 0xe4, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "decd x0, vl4"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xe4, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "decd x0, vl5"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xe4, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "decd x0, vl6"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xe4, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "decd x0, vl7"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe5, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "decd x0, vl8"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe5, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "decd x0, vl16"
+
+  -
+    input:
+      bytes: [ 0x40, 0xe5, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "decd x0, vl32"
+
+  -
+    input:
+      bytes: [ 0x60, 0xe5, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "decd x0, vl64"
+
+  -
+    input:
+      bytes: [ 0x80, 0xe5, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "decd x0, vl128"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xe5, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "decd x0, vl256"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xe5, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "decd x0, #14"
+
+  -
+    input:
+      bytes: [ 0x80, 0xe7, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "decd x0, #28"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xe7, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "decd x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xe7, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "decd x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xe7, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "decd x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xe7, 0xff, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "decd x0, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe4, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "decd x0, pow2"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe4, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "decd x0, vl1"
+
+  -
+    input:
+      bytes: [ 0x40, 0xe4, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "decd x0, vl2"
+
+  -
+    input:
+      bytes: [ 0x60, 0xe4, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "decd x0, vl3"
+
+  -
+    input:
+      bytes: [ 0x80, 0xe4, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "decd x0, vl4"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xe4, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "decd x0, vl5"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xe4, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "decd x0, vl6"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xe4, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "decd x0, vl7"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe5, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "decd x0, vl8"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe5, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "decd x0, vl16"
+
+  -
+    input:
+      bytes: [ 0x40, 0xe5, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "decd x0, vl32"
+
+  -
+    input:
+      bytes: [ 0x60, 0xe5, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "decd x0, vl64"
+
+  -
+    input:
+      bytes: [ 0x80, 0xe5, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "decd x0, vl128"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xe5, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "decd x0, vl256"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xe5, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "decd x0, #14"
+
+  -
+    input:
+      bytes: [ 0x80, 0xe7, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "decd x0, #28"
diff --git a/tests/MC/AArch64/SVE/dech.s.yaml b/tests/MC/AArch64/SVE/dech.s.yaml
new file mode 100644
index 000000000..7a7184d38
--- /dev/null
+++ b/tests/MC/AArch64/SVE/dech.s.yaml
@@ -0,0 +1,400 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xe0, 0xe7, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "dech x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xe7, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "dech x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xe7, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "dech x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xe7, 0x7f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "dech x0, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe4, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "dech x0, pow2"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe4, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "dech x0, vl1"
+
+  -
+    input:
+      bytes: [ 0x40, 0xe4, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "dech x0, vl2"
+
+  -
+    input:
+      bytes: [ 0x60, 0xe4, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "dech x0, vl3"
+
+  -
+    input:
+      bytes: [ 0x80, 0xe4, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "dech x0, vl4"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xe4, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "dech x0, vl5"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xe4, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "dech x0, vl6"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xe4, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "dech x0, vl7"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe5, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "dech x0, vl8"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe5, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "dech x0, vl16"
+
+  -
+    input:
+      bytes: [ 0x40, 0xe5, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "dech x0, vl32"
+
+  -
+    input:
+      bytes: [ 0x60, 0xe5, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "dech x0, vl64"
+
+  -
+    input:
+      bytes: [ 0x80, 0xe5, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "dech x0, vl128"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xe5, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "dech x0, vl256"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xe5, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "dech x0, #14"
+
+  -
+    input:
+      bytes: [ 0x80, 0xe7, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "dech x0, #28"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xe7, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "dech x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xe7, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "dech x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xe7, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "dech x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xe7, 0x7f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "dech x0, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe4, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "dech x0, pow2"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe4, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "dech x0, vl1"
+
+  -
+    input:
+      bytes: [ 0x40, 0xe4, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "dech x0, vl2"
+
+  -
+    input:
+      bytes: [ 0x60, 0xe4, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "dech x0, vl3"
+
+  -
+    input:
+      bytes: [ 0x80, 0xe4, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "dech x0, vl4"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xe4, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "dech x0, vl5"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xe4, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "dech x0, vl6"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xe4, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "dech x0, vl7"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe5, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "dech x0, vl8"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe5, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "dech x0, vl16"
+
+  -
+    input:
+      bytes: [ 0x40, 0xe5, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "dech x0, vl32"
+
+  -
+    input:
+      bytes: [ 0x60, 0xe5, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "dech x0, vl64"
+
+  -
+    input:
+      bytes: [ 0x80, 0xe5, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "dech x0, vl128"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xe5, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "dech x0, vl256"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xe5, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "dech x0, #14"
+
+  -
+    input:
+      bytes: [ 0x80, 0xe7, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "dech x0, #28"
diff --git a/tests/MC/AArch64/SVE/decp.s.yaml b/tests/MC/AArch64/SVE/decp.s.yaml
new file mode 100644
index 000000000..b07fab209
--- /dev/null
+++ b/tests/MC/AArch64/SVE/decp.s.yaml
@@ -0,0 +1,320 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x88, 0x2d, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "decp x0, p0.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x88, 0x6d, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "decp x0, p0.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x88, 0xad, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "decp x0, p0.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0x88, 0xed, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "decp x0, p0.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0x89, 0x2d, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "decp xzr, p15.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x89, 0x6d, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "decp xzr, p15.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x89, 0xad, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "decp xzr, p15.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0x89, 0xed, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "decp xzr, p15.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0x81, 0x6d, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "decp z31.h, p15.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x81, 0x6d, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "decp z31.h, p15.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x81, 0xad, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "decp z31.s, p15.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0x81, 0xad, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "decp z31.s, p15.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0x81, 0xed, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "decp z31.d, p15.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0x81, 0xed, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "decp z31.d, p15.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xff, 0x81, 0xed, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "decp z31.d, p15.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x88, 0x2d, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "decp x0, p0.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x88, 0x6d, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "decp x0, p0.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x88, 0xad, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "decp x0, p0.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0x88, 0xed, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "decp x0, p0.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0x89, 0x2d, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "decp xzr, p15.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x89, 0x6d, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "decp xzr, p15.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x89, 0xad, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "decp xzr, p15.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0x89, 0xed, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "decp xzr, p15.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0x81, 0x6d, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "decp z31.h, p15.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x81, 0x6d, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "decp z31.h, p15.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x81, 0xad, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "decp z31.s, p15.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0x81, 0xad, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "decp z31.s, p15.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0x81, 0xed, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "decp z31.d, p15.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0x81, 0xed, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "decp z31.d, p15.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xff, 0x81, 0xed, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "decp z31.d, p15.d"
diff --git a/tests/MC/AArch64/SVE/decw.s.yaml b/tests/MC/AArch64/SVE/decw.s.yaml
new file mode 100644
index 000000000..6a1e7dbed
--- /dev/null
+++ b/tests/MC/AArch64/SVE/decw.s.yaml
@@ -0,0 +1,400 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xe0, 0xe7, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "decw x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xe7, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "decw x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xe7, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "decw x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xe7, 0xbf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "decw x0, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe4, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "decw x0, pow2"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe4, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "decw x0, vl1"
+
+  -
+    input:
+      bytes: [ 0x40, 0xe4, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "decw x0, vl2"
+
+  -
+    input:
+      bytes: [ 0x60, 0xe4, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "decw x0, vl3"
+
+  -
+    input:
+      bytes: [ 0x80, 0xe4, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "decw x0, vl4"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xe4, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "decw x0, vl5"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xe4, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "decw x0, vl6"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xe4, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "decw x0, vl7"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe5, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "decw x0, vl8"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe5, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "decw x0, vl16"
+
+  -
+    input:
+      bytes: [ 0x40, 0xe5, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "decw x0, vl32"
+
+  -
+    input:
+      bytes: [ 0x60, 0xe5, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "decw x0, vl64"
+
+  -
+    input:
+      bytes: [ 0x80, 0xe5, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "decw x0, vl128"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xe5, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "decw x0, vl256"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xe5, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "decw x0, #14"
+
+  -
+    input:
+      bytes: [ 0x80, 0xe7, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "decw x0, #28"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xe7, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "decw x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xe7, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "decw x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xe7, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "decw x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xe7, 0xbf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "decw x0, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe4, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "decw x0, pow2"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe4, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "decw x0, vl1"
+
+  -
+    input:
+      bytes: [ 0x40, 0xe4, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "decw x0, vl2"
+
+  -
+    input:
+      bytes: [ 0x60, 0xe4, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "decw x0, vl3"
+
+  -
+    input:
+      bytes: [ 0x80, 0xe4, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "decw x0, vl4"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xe4, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "decw x0, vl5"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xe4, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "decw x0, vl6"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xe4, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "decw x0, vl7"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe5, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "decw x0, vl8"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe5, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "decw x0, vl16"
+
+  -
+    input:
+      bytes: [ 0x40, 0xe5, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "decw x0, vl32"
+
+  -
+    input:
+      bytes: [ 0x60, 0xe5, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "decw x0, vl64"
+
+  -
+    input:
+      bytes: [ 0x80, 0xe5, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "decw x0, vl128"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xe5, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "decw x0, vl256"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xe5, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "decw x0, #14"
+
+  -
+    input:
+      bytes: [ 0x80, 0xe7, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "decw x0, #28"
diff --git a/tests/MC/AArch64/SVE/dot-req.s.yaml b/tests/MC/AArch64/SVE/dot-req.s.yaml
new file mode 100644
index 000000000..cb9e9d9df
--- /dev/null
+++ b/tests/MC/AArch64/SVE/dot-req.s.yaml
@@ -0,0 +1,10 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x00, 0xa2, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "add z0.s, z1.s, z2.s"
diff --git a/tests/MC/AArch64/SVE/dup.s.yaml b/tests/MC/AArch64/SVE/dup.s.yaml
new file mode 100644
index 000000000..c6455d225
--- /dev/null
+++ b/tests/MC/AArch64/SVE/dup.s.yaml
@@ -0,0 +1,840 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x38, 0x20, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.b, w0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x38, 0x60, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.h, w0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x38, 0xa0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.s, w0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x38, 0xe0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.d, x0"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3b, 0x60, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z31.h, wsp"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3b, 0xa0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z31.s, wsp"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3b, 0xe0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z31.d, sp"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3b, 0x20, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z31.b, wsp"
+
+  -
+    input:
+      bytes: [ 0x05, 0xd0, 0x38, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z5.b, #-128"
+
+  -
+    input:
+      bytes: [ 0xe5, 0xcf, 0x38, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z5.b, #127"
+
+  -
+    input:
+      bytes: [ 0xe5, 0xdf, 0x38, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z5.b, #-1"
+
+  -
+    input:
+      bytes: [ 0x15, 0xd0, 0x78, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.h, #-128"
+
+  -
+    input:
+      bytes: [ 0x15, 0xf0, 0x78, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.h, #-32768"
+
+  -
+    input:
+      bytes: [ 0x15, 0xf0, 0x78, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.h, #-32768"
+
+  -
+    input:
+      bytes: [ 0xf5, 0xcf, 0x78, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.h, #127"
+
+  -
+    input:
+      bytes: [ 0xf5, 0xef, 0x78, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.h, #32512"
+
+  -
+    input:
+      bytes: [ 0xf5, 0xef, 0x78, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.h, #32512"
+
+  -
+    input:
+      bytes: [ 0x15, 0xd0, 0xb8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.s, #-128"
+
+  -
+    input:
+      bytes: [ 0x15, 0xf0, 0xb8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.s, #-32768"
+
+  -
+    input:
+      bytes: [ 0x15, 0xf0, 0xb8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.s, #-32768"
+
+  -
+    input:
+      bytes: [ 0xf5, 0xcf, 0xb8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.s, #127"
+
+  -
+    input:
+      bytes: [ 0xf5, 0xef, 0xb8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.s, #32512"
+
+  -
+    input:
+      bytes: [ 0xf5, 0xef, 0xb8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.s, #32512"
+
+  -
+    input:
+      bytes: [ 0x15, 0xd0, 0xf8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.d, #-128"
+
+  -
+    input:
+      bytes: [ 0x15, 0xf0, 0xf8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.d, #-32768"
+
+  -
+    input:
+      bytes: [ 0x15, 0xf0, 0xf8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.d, #-32768"
+
+  -
+    input:
+      bytes: [ 0xf5, 0xcf, 0xf8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.d, #127"
+
+  -
+    input:
+      bytes: [ 0xf5, 0xef, 0xf8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.d, #32512"
+
+  -
+    input:
+      bytes: [ 0xf5, 0xef, 0xf8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.d, #32512"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x21, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.b, b0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x22, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.h, h0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x24, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.s, s0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x28, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.d, d0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x30, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.q, q0"
+
+  -
+    input:
+      bytes: [ 0xff, 0x23, 0xff, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z31.b, z31.b[63]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x23, 0xfe, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z31.h, z31.h[31]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x23, 0xfc, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z31.s, z31.s[15]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x23, 0xf8, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z31.d, z31.d[7]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x22, 0xf0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z5.q, z17.q[3]"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xcf, 0x38, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.b, #127"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xef, 0x78, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.h, #32512"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xef, 0x78, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.h, #32512"
+
+  -
+    input:
+      bytes: [ 0x00, 0x38, 0x20, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.b, w0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x38, 0x60, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.h, w0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x38, 0xa0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.s, w0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x38, 0xe0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.d, x0"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3b, 0x60, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z31.h, wsp"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3b, 0xa0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z31.s, wsp"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3b, 0xe0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z31.d, sp"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3b, 0x20, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z31.b, wsp"
+
+  -
+    input:
+      bytes: [ 0x05, 0xd0, 0x38, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z5.b, #-128"
+
+  -
+    input:
+      bytes: [ 0xe5, 0xcf, 0x38, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z5.b, #127"
+
+  -
+    input:
+      bytes: [ 0xe5, 0xdf, 0x38, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z5.b, #-1"
+
+  -
+    input:
+      bytes: [ 0x15, 0xd0, 0x78, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.h, #-128"
+
+  -
+    input:
+      bytes: [ 0x15, 0xf0, 0x78, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.h, #-32768"
+
+  -
+    input:
+      bytes: [ 0x15, 0xf0, 0x78, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.h, #-32768"
+
+  -
+    input:
+      bytes: [ 0xf5, 0xcf, 0x78, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.h, #127"
+
+  -
+    input:
+      bytes: [ 0xf5, 0xef, 0x78, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.h, #32512"
+
+  -
+    input:
+      bytes: [ 0xf5, 0xef, 0x78, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.h, #32512"
+
+  -
+    input:
+      bytes: [ 0x15, 0xd0, 0xb8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.s, #-128"
+
+  -
+    input:
+      bytes: [ 0x15, 0xf0, 0xb8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.s, #-32768"
+
+  -
+    input:
+      bytes: [ 0x15, 0xf0, 0xb8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.s, #-32768"
+
+  -
+    input:
+      bytes: [ 0xf5, 0xcf, 0xb8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.s, #127"
+
+  -
+    input:
+      bytes: [ 0xf5, 0xef, 0xb8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.s, #32512"
+
+  -
+    input:
+      bytes: [ 0xf5, 0xef, 0xb8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.s, #32512"
+
+  -
+    input:
+      bytes: [ 0x15, 0xd0, 0xf8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.d, #-128"
+
+  -
+    input:
+      bytes: [ 0x15, 0xf0, 0xf8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.d, #-32768"
+
+  -
+    input:
+      bytes: [ 0x15, 0xf0, 0xf8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.d, #-32768"
+
+  -
+    input:
+      bytes: [ 0xf5, 0xcf, 0xf8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.d, #127"
+
+  -
+    input:
+      bytes: [ 0xf5, 0xef, 0xf8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.d, #32512"
+
+  -
+    input:
+      bytes: [ 0xf5, 0xef, 0xf8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.d, #32512"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x21, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.b, b0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x22, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.h, h0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x24, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.s, s0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x28, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.d, d0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x30, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.q, q0"
+
+  -
+    input:
+      bytes: [ 0xff, 0x23, 0xff, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z31.b, z31.b[63]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x23, 0xfe, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z31.h, z31.h[31]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x23, 0xfc, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z31.s, z31.s[15]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x23, 0xf8, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z31.d, z31.d[7]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x22, 0xf0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z5.q, z17.q[3]"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xcf, 0x38, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.b, #127"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xef, 0x78, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.h, #32512"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xef, 0x78, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.h, #32512"
diff --git a/tests/MC/AArch64/SVE/dupm.s.yaml b/tests/MC/AArch64/SVE/dupm.s.yaml
new file mode 100644
index 000000000..3d841332f
--- /dev/null
+++ b/tests/MC/AArch64/SVE/dupm.s.yaml
@@ -0,0 +1,200 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xa5, 0x2e, 0xc0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "dupm z5.b, #0xf9"
+
+  -
+    input:
+      bytes: [ 0xa5, 0x2e, 0xc0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "dupm z5.b, #0xf9"
+
+  -
+    input:
+      bytes: [ 0xa5, 0x2e, 0xc0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "dupm z5.b, #0xf9"
+
+  -
+    input:
+      bytes: [ 0xa5, 0x2e, 0xc0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "dupm z5.b, #0xf9"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x6d, 0xc0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "dupm z23.h, #0xfff9"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x6d, 0xc0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "dupm z23.h, #0xfff9"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x6d, 0xc0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "dupm z23.h, #0xfff9"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xeb, 0xc0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "dupm z0.s, #0xfffffff9"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xeb, 0xc0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "dupm z0.s, #0xfffffff9"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xef, 0xc3, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "dupm z0.d, #0xfffffffffffffff9"
+
+  -
+    input:
+      bytes: [ 0xa5, 0x2e, 0xc0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "dupm z5.b, #0xf9"
+
+  -
+    input:
+      bytes: [ 0xa5, 0x2e, 0xc0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "dupm z5.b, #0xf9"
+
+  -
+    input:
+      bytes: [ 0xa5, 0x2e, 0xc0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "dupm z5.b, #0xf9"
+
+  -
+    input:
+      bytes: [ 0xa5, 0x2e, 0xc0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "dupm z5.b, #0xf9"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x6d, 0xc0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "dupm z23.h, #0xfff9"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x6d, 0xc0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "dupm z23.h, #0xfff9"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x6d, 0xc0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "dupm z23.h, #0xfff9"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xeb, 0xc0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "dupm z0.s, #0xfffffff9"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xeb, 0xc0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "dupm z0.s, #0xfffffff9"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xef, 0xc3, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "dupm z0.d, #0xfffffffffffffff9"
diff --git a/tests/MC/AArch64/SVE/eon.s.yaml b/tests/MC/AArch64/SVE/eon.s.yaml
new file mode 100644
index 000000000..ff6c9158b
--- /dev/null
+++ b/tests/MC/AArch64/SVE/eon.s.yaml
@@ -0,0 +1,200 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x25, 0x3e, 0x40, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "eor z5.b, z5.b, #0x6"
+
+  -
+    input:
+      bytes: [ 0x37, 0x7c, 0x40, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "eor z23.h, z23.h, #0x6"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf8, 0x40, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "eor z0.s, z0.s, #0x6"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf8, 0x43, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "eor z0.d, z0.d, #0x6"
+
+  -
+    input:
+      bytes: [ 0xa5, 0x2e, 0x40, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "eor z5.b, z5.b, #0xf9"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x6d, 0x40, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "eor z23.h, z23.h, #0xfff9"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xeb, 0x40, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "eor z0.s, z0.s, #0xfffffff9"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xef, 0x43, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "eor z0.d, z0.d, #0xfffffffffffffff9"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xef, 0x43, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "eor z0.d, z0.d, #0xfffffffffffffff9"
+
+  -
+    input:
+      bytes: [ 0x25, 0x3e, 0x40, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "eor z5.b, z5.b, #0x6"
+
+  -
+    input:
+      bytes: [ 0x37, 0x7c, 0x40, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "eor z23.h, z23.h, #0x6"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf8, 0x40, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "eor z0.s, z0.s, #0x6"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf8, 0x43, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "eor z0.d, z0.d, #0x6"
+
+  -
+    input:
+      bytes: [ 0xa5, 0x2e, 0x40, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "eor z5.b, z5.b, #0xf9"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x6d, 0x40, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "eor z23.h, z23.h, #0xfff9"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xeb, 0x40, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "eor z0.s, z0.s, #0xfffffff9"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xef, 0x43, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "eor z0.d, z0.d, #0xfffffffffffffff9"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xef, 0x43, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "eor z0.d, z0.d, #0xfffffffffffffff9"
diff --git a/tests/MC/AArch64/SVE/eor.s.yaml b/tests/MC/AArch64/SVE/eor.s.yaml
new file mode 100644
index 000000000..5bb2ce694
--- /dev/null
+++ b/tests/MC/AArch64/SVE/eor.s.yaml
@@ -0,0 +1,520 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xa5, 0x2e, 0x40, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "eor z5.b, z5.b, #0xf9"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x6d, 0x40, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "eor z23.h, z23.h, #0xfff9"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xeb, 0x40, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "eor z0.s, z0.s, #0xfffffff9"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xef, 0x43, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "eor z0.d, z0.d, #0xfffffffffffffff9"
+
+  -
+    input:
+      bytes: [ 0x25, 0x3e, 0x40, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "eor z5.b, z5.b, #0x6"
+
+  -
+    input:
+      bytes: [ 0x37, 0x7c, 0x40, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "eor z23.h, z23.h, #0x6"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf8, 0x40, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "eor z0.s, z0.s, #0x6"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf8, 0x43, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "eor z0.d, z0.d, #0x6"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x31, 0xa8, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "eor z23.d, z13.d, z8.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x30, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "eor z0.d, z0.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0x99, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "eor z31.s, p7/m, z31.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0x59, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "eor z31.h, p7/m, z31.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0xd9, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "eor z31.d, p7/m, z31.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0x19, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "eor z31.b, p7/m, z31.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x42, 0x01, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "eor p0.b, p0/z, p0.b, p1.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x42, 0x00, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "not p0.b, p0/z, p0.b"
+
+  -
+    input:
+      bytes: [ 0xef, 0x7f, 0x0f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "not p15.b, p15/z, p15.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x30, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "eor z0.d, z0.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x30, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "eor z0.d, z0.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x30, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "eor z0.d, z0.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0x3c, 0x10, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4.b, p7/z, z6.b"
+
+  -
+    input:
+      bytes: [ 0xe4, 0x1f, 0x19, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "eor z4.b, p7/m, z4.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0xc4, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4, z6"
+
+  -
+    input:
+      bytes: [ 0xe4, 0x1f, 0x19, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "eor z4.b, p7/m, z4.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf8, 0x43, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "eor z0.d, z0.d, #0x6"
+
+  -
+    input:
+      bytes: [ 0xa5, 0x2e, 0x40, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "eor z5.b, z5.b, #0xf9"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x6d, 0x40, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "eor z23.h, z23.h, #0xfff9"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xeb, 0x40, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "eor z0.s, z0.s, #0xfffffff9"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xef, 0x43, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "eor z0.d, z0.d, #0xfffffffffffffff9"
+
+  -
+    input:
+      bytes: [ 0x25, 0x3e, 0x40, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "eor z5.b, z5.b, #0x6"
+
+  -
+    input:
+      bytes: [ 0x37, 0x7c, 0x40, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "eor z23.h, z23.h, #0x6"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf8, 0x40, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "eor z0.s, z0.s, #0x6"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf8, 0x43, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "eor z0.d, z0.d, #0x6"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x31, 0xa8, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "eor z23.d, z13.d, z8.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x30, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "eor z0.d, z0.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0x99, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "eor z31.s, p7/m, z31.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0x59, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "eor z31.h, p7/m, z31.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0xd9, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "eor z31.d, p7/m, z31.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0x19, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "eor z31.b, p7/m, z31.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x42, 0x01, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "eor p0.b, p0/z, p0.b, p1.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x42, 0x00, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "not p0.b, p0/z, p0.b"
+
+  -
+    input:
+      bytes: [ 0xef, 0x7f, 0x0f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "not p15.b, p15/z, p15.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x30, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "eor z0.d, z0.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x30, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "eor z0.d, z0.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x30, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "eor z0.d, z0.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0x3c, 0x10, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4.b, p7/z, z6.b"
+
+  -
+    input:
+      bytes: [ 0xe4, 0x1f, 0x19, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "eor z4.b, p7/m, z4.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0xc4, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4, z6"
+
+  -
+    input:
+      bytes: [ 0xe4, 0x1f, 0x19, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "eor z4.b, p7/m, z4.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf8, 0x43, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "eor z0.d, z0.d, #0x6"
diff --git a/tests/MC/AArch64/SVE/eors.s.yaml b/tests/MC/AArch64/SVE/eors.s.yaml
new file mode 100644
index 000000000..1d0836884
--- /dev/null
+++ b/tests/MC/AArch64/SVE/eors.s.yaml
@@ -0,0 +1,60 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x42, 0x41, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "eors p0.b, p0/z, p0.b, p1.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x42, 0x40, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "nots p0.b, p0/z, p0.b"
+
+  -
+    input:
+      bytes: [ 0xef, 0x7f, 0x4f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "nots p15.b, p15/z, p15.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x42, 0x41, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "eors p0.b, p0/z, p0.b, p1.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x42, 0x40, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "nots p0.b, p0/z, p0.b"
+
+  -
+    input:
+      bytes: [ 0xef, 0x7f, 0x4f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "nots p15.b, p15/z, p15.b"
diff --git a/tests/MC/AArch64/SVE/eorv.s.yaml b/tests/MC/AArch64/SVE/eorv.s.yaml
new file mode 100644
index 000000000..df4e1b56d
--- /dev/null
+++ b/tests/MC/AArch64/SVE/eorv.s.yaml
@@ -0,0 +1,80 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xe0, 0x3f, 0x19, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "eorv b0, p7, z31.b"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3f, 0x59, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "eorv h0, p7, z31.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3f, 0x99, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "eorv s0, p7, z31.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3f, 0xd9, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "eorv d0, p7, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3f, 0x19, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "eorv b0, p7, z31.b"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3f, 0x59, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "eorv h0, p7, z31.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3f, 0x99, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "eorv s0, p7, z31.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3f, 0xd9, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "eorv d0, p7, z31.d"
diff --git a/tests/MC/AArch64/SVE/ext.s.yaml b/tests/MC/AArch64/SVE/ext.s.yaml
new file mode 100644
index 000000000..53e2c2871
--- /dev/null
+++ b/tests/MC/AArch64/SVE/ext.s.yaml
@@ -0,0 +1,80 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x1f, 0x00, 0x20, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ext z31.b, z31.b, z0.b, #0"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x1c, 0x3f, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ext z31.b, z31.b, z0.b, #255"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x1c, 0x3f, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ext z31.b, z31.b, z0.b, #255"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x00, 0x20, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ext z31.b, z31.b, z0.b, #0"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x1c, 0x3f, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ext z31.b, z31.b, z0.b, #255"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x1c, 0x3f, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ext z31.b, z31.b, z0.b, #255"
diff --git a/tests/MC/AArch64/SVE/fabd.s.yaml b/tests/MC/AArch64/SVE/fabd.s.yaml
new file mode 100644
index 000000000..70063a0ab
--- /dev/null
+++ b/tests/MC/AArch64/SVE/fabd.s.yaml
@@ -0,0 +1,140 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0x48, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fabd z0.h, p7/m, z0.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0x88, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fabd z0.s, p7/m, z0.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xc8, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fabd z0.d, p7/m, z0.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0.d, p7/z, z7.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xc8, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fabd z0.d, p7/m, z0.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xc8, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fabd z0.d, p7/m, z0.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0x48, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fabd z0.h, p7/m, z0.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0x88, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fabd z0.s, p7/m, z0.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xc8, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fabd z0.d, p7/m, z0.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0.d, p7/z, z7.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xc8, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fabd z0.d, p7/m, z0.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xc8, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fabd z0.d, p7/m, z0.d, z31.d"
diff --git a/tests/MC/AArch64/SVE/fabs.s.yaml b/tests/MC/AArch64/SVE/fabs.s.yaml
new file mode 100644
index 000000000..902954087
--- /dev/null
+++ b/tests/MC/AArch64/SVE/fabs.s.yaml
@@ -0,0 +1,140 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x5c, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fabs z31.h, p7/m, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x9c, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fabs z31.s, p7/m, z31.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0xdc, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fabs z31.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4.d, p7/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xbf, 0xdc, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fabs z4.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4, z6"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xbf, 0xdc, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fabs z4.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x5c, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fabs z31.h, p7/m, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x9c, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fabs z31.s, p7/m, z31.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0xdc, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fabs z31.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4.d, p7/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xbf, 0xdc, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fabs z4.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4, z6"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xbf, 0xdc, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fabs z4.d, p7/m, z31.d"
diff --git a/tests/MC/AArch64/SVE/facge.s.yaml b/tests/MC/AArch64/SVE/facge.s.yaml
new file mode 100644
index 000000000..e93a9b695
--- /dev/null
+++ b/tests/MC/AArch64/SVE/facge.s.yaml
@@ -0,0 +1,60 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x10, 0xc0, 0x41, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "facge p0.h, p0/z, z0.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0x10, 0xc0, 0x81, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "facge p0.s, p0/z, z0.s, z1.s"
+
+  -
+    input:
+      bytes: [ 0x10, 0xc0, 0xc1, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "facge p0.d, p0/z, z0.d, z1.d"
+
+  -
+    input:
+      bytes: [ 0x10, 0xc0, 0x41, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "facge p0.h, p0/z, z0.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0x10, 0xc0, 0x81, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "facge p0.s, p0/z, z0.s, z1.s"
+
+  -
+    input:
+      bytes: [ 0x10, 0xc0, 0xc1, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "facge p0.d, p0/z, z0.d, z1.d"
diff --git a/tests/MC/AArch64/SVE/facgt.s.yaml b/tests/MC/AArch64/SVE/facgt.s.yaml
new file mode 100644
index 000000000..10e11fcea
--- /dev/null
+++ b/tests/MC/AArch64/SVE/facgt.s.yaml
@@ -0,0 +1,60 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x10, 0xe0, 0x41, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "facgt p0.h, p0/z, z0.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0x10, 0xe0, 0x81, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "facgt p0.s, p0/z, z0.s, z1.s"
+
+  -
+    input:
+      bytes: [ 0x10, 0xe0, 0xc1, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "facgt p0.d, p0/z, z0.d, z1.d"
+
+  -
+    input:
+      bytes: [ 0x10, 0xe0, 0x41, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "facgt p0.h, p0/z, z0.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0x10, 0xe0, 0x81, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "facgt p0.s, p0/z, z0.s, z1.s"
+
+  -
+    input:
+      bytes: [ 0x10, 0xe0, 0xc1, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "facgt p0.d, p0/z, z0.d, z1.d"
diff --git a/tests/MC/AArch64/SVE/facle.s.yaml b/tests/MC/AArch64/SVE/facle.s.yaml
new file mode 100644
index 000000000..abce92552
--- /dev/null
+++ b/tests/MC/AArch64/SVE/facle.s.yaml
@@ -0,0 +1,60 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x30, 0xc0, 0x40, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "facge p0.h, p0/z, z1.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x30, 0xc0, 0x80, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "facge p0.s, p0/z, z1.s, z0.s"
+
+  -
+    input:
+      bytes: [ 0x30, 0xc0, 0xc0, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "facge p0.d, p0/z, z1.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0x30, 0xc0, 0x40, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "facge p0.h, p0/z, z1.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x30, 0xc0, 0x80, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "facge p0.s, p0/z, z1.s, z0.s"
+
+  -
+    input:
+      bytes: [ 0x30, 0xc0, 0xc0, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "facge p0.d, p0/z, z1.d, z0.d"
diff --git a/tests/MC/AArch64/SVE/faclt.s.yaml b/tests/MC/AArch64/SVE/faclt.s.yaml
new file mode 100644
index 000000000..54abcc3fc
--- /dev/null
+++ b/tests/MC/AArch64/SVE/faclt.s.yaml
@@ -0,0 +1,60 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x30, 0xe0, 0x40, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "facgt p0.h, p0/z, z1.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x30, 0xe0, 0x80, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "facgt p0.s, p0/z, z1.s, z0.s"
+
+  -
+    input:
+      bytes: [ 0x30, 0xe0, 0xc0, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "facgt p0.d, p0/z, z1.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0x30, 0xe0, 0x40, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "facgt p0.h, p0/z, z1.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x30, 0xe0, 0x80, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "facgt p0.s, p0/z, z1.s, z0.s"
+
+  -
+    input:
+      bytes: [ 0x30, 0xe0, 0xc0, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "facgt p0.d, p0/z, z1.d, z0.d"
diff --git a/tests/MC/AArch64/SVE/fadd.s.yaml b/tests/MC/AArch64/SVE/fadd.s.yaml
new file mode 100644
index 000000000..ea6793e05
--- /dev/null
+++ b/tests/MC/AArch64/SVE/fadd.s.yaml
@@ -0,0 +1,440 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x58, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd z0.h, p0/m, z0.h, #0.5"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x58, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd z0.h, p0/m, z0.h, #0.5"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x98, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd z0.s, p0/m, z0.s, #0.5"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xd8, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd z0.d, p0/m, z0.d, #0.5"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x9c, 0x58, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd z31.h, p7/m, z31.h, #1.0"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x9c, 0x58, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd z31.h, p7/m, z31.h, #1.0"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x9c, 0x98, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd z31.s, p7/m, z31.s, #1.0"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x9c, 0xd8, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd z31.d, p7/m, z31.d, #1.0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0x40, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd z0.h, p7/m, z0.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0x80, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd z0.s, p7/m, z0.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xc0, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd z0.d, p7/m, z0.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x00, 0x5f, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd z0.h, z1.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x00, 0x9f, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd z0.s, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x00, 0xdf, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd z0.d, z1.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31.d, p7/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x9c, 0xd8, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd z31.d, p7/m, z31.d, #1.0"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x9c, 0xd8, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd z31.d, p7/m, z31.d, #1.0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0.d, p7/z, z7.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xc0, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd z0.d, p7/m, z0.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xc0, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd z0.d, p7/m, z0.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x58, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd z0.h, p0/m, z0.h, #0.5"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x58, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd z0.h, p0/m, z0.h, #0.5"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x98, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd z0.s, p0/m, z0.s, #0.5"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xd8, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd z0.d, p0/m, z0.d, #0.5"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x9c, 0x58, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd z31.h, p7/m, z31.h, #1.0"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x9c, 0x58, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd z31.h, p7/m, z31.h, #1.0"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x9c, 0x98, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd z31.s, p7/m, z31.s, #1.0"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x9c, 0xd8, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd z31.d, p7/m, z31.d, #1.0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0x40, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd z0.h, p7/m, z0.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0x80, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd z0.s, p7/m, z0.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xc0, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd z0.d, p7/m, z0.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x00, 0x5f, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd z0.h, z1.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x00, 0x9f, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd z0.s, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x00, 0xdf, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd z0.d, z1.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31.d, p7/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x9c, 0xd8, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd z31.d, p7/m, z31.d, #1.0"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x9c, 0xd8, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd z31.d, p7/m, z31.d, #1.0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0.d, p7/z, z7.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xc0, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd z0.d, p7/m, z0.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xc0, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd z0.d, p7/m, z0.d, z31.d"
diff --git a/tests/MC/AArch64/SVE/fadda.s.yaml b/tests/MC/AArch64/SVE/fadda.s.yaml
new file mode 100644
index 000000000..d5552e608
--- /dev/null
+++ b/tests/MC/AArch64/SVE/fadda.s.yaml
@@ -0,0 +1,30 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xe0, 0x3f, 0x58, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadda h0, p7, h0, z31.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3f, 0x98, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadda s0, p7, s0, z31.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3f, 0xd8, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadda d0, p7, d0, z31.d"
diff --git a/tests/MC/AArch64/SVE/faddv.s.yaml b/tests/MC/AArch64/SVE/faddv.s.yaml
new file mode 100644
index 000000000..51216a137
--- /dev/null
+++ b/tests/MC/AArch64/SVE/faddv.s.yaml
@@ -0,0 +1,60 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xe0, 0x3f, 0x40, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "faddv h0, p7, z31.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3f, 0x80, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "faddv s0, p7, z31.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3f, 0xc0, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "faddv d0, p7, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3f, 0x40, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "faddv h0, p7, z31.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3f, 0x80, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "faddv s0, p7, z31.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3f, 0xc0, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "faddv d0, p7, z31.d"
diff --git a/tests/MC/AArch64/SVE/fcadd.s.yaml b/tests/MC/AArch64/SVE/fcadd.s.yaml
new file mode 100644
index 000000000..8921245f4
--- /dev/null
+++ b/tests/MC/AArch64/SVE/fcadd.s.yaml
@@ -0,0 +1,200 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x40, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcadd z0.h, p0/m, z0.h, z0.h, #90"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x80, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcadd z0.s, p0/m, z0.s, z0.s, #90"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xc0, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcadd z0.d, p0/m, z0.d, z0.d, #90"
+
+  -
+    input:
+      bytes: [ 0xff, 0x9f, 0x41, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcadd z31.h, p7/m, z31.h, z31.h, #270"
+
+  -
+    input:
+      bytes: [ 0xff, 0x9f, 0x81, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcadd z31.s, p7/m, z31.s, z31.s, #270"
+
+  -
+    input:
+      bytes: [ 0xff, 0x9f, 0xc1, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcadd z31.d, p7/m, z31.d, z31.d, #270"
+
+  -
+    input:
+      bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4.d, p7/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xe4, 0x9f, 0xc1, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcadd z4.d, p7/m, z4.d, z31.d, #270"
+
+  -
+    input:
+      bytes: [ 0xc4, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4, z6"
+
+  -
+    input:
+      bytes: [ 0xe4, 0x9f, 0xc1, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcadd z4.d, p7/m, z4.d, z31.d, #270"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x40, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcadd z0.h, p0/m, z0.h, z0.h, #90"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x80, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcadd z0.s, p0/m, z0.s, z0.s, #90"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xc0, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcadd z0.d, p0/m, z0.d, z0.d, #90"
+
+  -
+    input:
+      bytes: [ 0xff, 0x9f, 0x41, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcadd z31.h, p7/m, z31.h, z31.h, #270"
+
+  -
+    input:
+      bytes: [ 0xff, 0x9f, 0x81, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcadd z31.s, p7/m, z31.s, z31.s, #270"
+
+  -
+    input:
+      bytes: [ 0xff, 0x9f, 0xc1, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcadd z31.d, p7/m, z31.d, z31.d, #270"
+
+  -
+    input:
+      bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4.d, p7/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xe4, 0x9f, 0xc1, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcadd z4.d, p7/m, z4.d, z31.d, #270"
+
+  -
+    input:
+      bytes: [ 0xc4, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4, z6"
+
+  -
+    input:
+      bytes: [ 0xe4, 0x9f, 0xc1, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcadd z4.d, p7/m, z4.d, z31.d, #270"
diff --git a/tests/MC/AArch64/SVE/fcmeq.s.yaml b/tests/MC/AArch64/SVE/fcmeq.s.yaml
new file mode 100644
index 000000000..c035a0531
--- /dev/null
+++ b/tests/MC/AArch64/SVE/fcmeq.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x52, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmeq p0.h, p0/z, z0.h, #0.0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x92, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmeq p0.s, p0/z, z0.s, #0.0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0xd2, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmeq p0.d, p0/z, z0.d, #0.0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0x41, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmeq p0.h, p0/z, z0.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0x81, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmeq p0.s, p0/z, z0.s, z1.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0xc1, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmeq p0.d, p0/z, z0.d, z1.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x52, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmeq p0.h, p0/z, z0.h, #0.0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x92, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmeq p0.s, p0/z, z0.s, #0.0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0xd2, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmeq p0.d, p0/z, z0.d, #0.0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0x41, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmeq p0.h, p0/z, z0.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0x81, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmeq p0.s, p0/z, z0.s, z1.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0xc1, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmeq p0.d, p0/z, z0.d, z1.d"
diff --git a/tests/MC/AArch64/SVE/fcmge.s.yaml b/tests/MC/AArch64/SVE/fcmge.s.yaml
new file mode 100644
index 000000000..c8ed1a797
--- /dev/null
+++ b/tests/MC/AArch64/SVE/fcmge.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x50, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmge p0.h, p0/z, z0.h, #0.0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x90, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmge p0.s, p0/z, z0.s, #0.0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0xd0, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmge p0.d, p0/z, z0.d, #0.0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0x41, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmge p0.h, p0/z, z0.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0x81, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmge p0.s, p0/z, z0.s, z1.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0xc1, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmge p0.d, p0/z, z0.d, z1.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x50, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmge p0.h, p0/z, z0.h, #0.0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x90, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmge p0.s, p0/z, z0.s, #0.0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0xd0, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmge p0.d, p0/z, z0.d, #0.0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0x41, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmge p0.h, p0/z, z0.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0x81, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmge p0.s, p0/z, z0.s, z1.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0xc1, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmge p0.d, p0/z, z0.d, z1.d"
diff --git a/tests/MC/AArch64/SVE/fcmgt.s.yaml b/tests/MC/AArch64/SVE/fcmgt.s.yaml
new file mode 100644
index 000000000..5f1961e19
--- /dev/null
+++ b/tests/MC/AArch64/SVE/fcmgt.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x10, 0x20, 0x50, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmgt p0.h, p0/z, z0.h, #0.0"
+
+  -
+    input:
+      bytes: [ 0x10, 0x20, 0x90, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmgt p0.s, p0/z, z0.s, #0.0"
+
+  -
+    input:
+      bytes: [ 0x10, 0x20, 0xd0, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmgt p0.d, p0/z, z0.d, #0.0"
+
+  -
+    input:
+      bytes: [ 0x10, 0x40, 0x41, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmgt p0.h, p0/z, z0.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0x10, 0x40, 0x81, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmgt p0.s, p0/z, z0.s, z1.s"
+
+  -
+    input:
+      bytes: [ 0x10, 0x40, 0xc1, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmgt p0.d, p0/z, z0.d, z1.d"
+
+  -
+    input:
+      bytes: [ 0x10, 0x20, 0x50, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmgt p0.h, p0/z, z0.h, #0.0"
+
+  -
+    input:
+      bytes: [ 0x10, 0x20, 0x90, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmgt p0.s, p0/z, z0.s, #0.0"
+
+  -
+    input:
+      bytes: [ 0x10, 0x20, 0xd0, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmgt p0.d, p0/z, z0.d, #0.0"
+
+  -
+    input:
+      bytes: [ 0x10, 0x40, 0x41, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmgt p0.h, p0/z, z0.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0x10, 0x40, 0x81, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmgt p0.s, p0/z, z0.s, z1.s"
+
+  -
+    input:
+      bytes: [ 0x10, 0x40, 0xc1, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmgt p0.d, p0/z, z0.d, z1.d"
diff --git a/tests/MC/AArch64/SVE/fcmla.s.yaml b/tests/MC/AArch64/SVE/fcmla.s.yaml
new file mode 100644
index 000000000..caa51ef49
--- /dev/null
+++ b/tests/MC/AArch64/SVE/fcmla.s.yaml
@@ -0,0 +1,440 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x40, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmla z0.h, p0/m, z0.h, z0.h, #0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x80, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmla z0.s, p0/m, z0.s, z0.s, #0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0xc0, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmla z0.d, p0/m, z0.d, z0.d, #0"
+
+  -
+    input:
+      bytes: [ 0x20, 0x20, 0x42, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmla z0.h, p0/m, z1.h, z2.h, #90"
+
+  -
+    input:
+      bytes: [ 0x20, 0x20, 0x82, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmla z0.s, p0/m, z1.s, z2.s, #90"
+
+  -
+    input:
+      bytes: [ 0x20, 0x20, 0xc2, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmla z0.d, p0/m, z1.d, z2.d, #90"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x5f, 0x5f, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmla z29.h, p7/m, z30.h, z31.h, #180"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x5f, 0x9f, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmla z29.s, p7/m, z30.s, z31.s, #180"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x5f, 0xdf, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmla z29.d, p7/m, z30.d, z31.d, #180"
+
+  -
+    input:
+      bytes: [ 0xff, 0x7f, 0x5f, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmla z31.h, p7/m, z31.h, z31.h, #270"
+
+  -
+    input:
+      bytes: [ 0xff, 0x7f, 0x9f, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmla z31.s, p7/m, z31.s, z31.s, #270"
+
+  -
+    input:
+      bytes: [ 0xff, 0x7f, 0xdf, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmla z31.d, p7/m, z31.d, z31.d, #270"
+
+  -
+    input:
+      bytes: [ 0x00, 0x10, 0xa0, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmla z0.h, z0.h, z0.h[0], #0"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x1d, 0xe8, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmla z23.s, z13.s, z8.s[0], #270"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0xbf, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmla z31.h, z31.h, z7.h[3], #270"
+
+  -
+    input:
+      bytes: [ 0x55, 0x15, 0xf5, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmla z21.s, z10.s, z5.s[1], #90"
+
+  -
+    input:
+      bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4.d, p7/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xe4, 0x7f, 0xdf, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmla z4.d, p7/m, z31.d, z31.d, #270"
+
+  -
+    input:
+      bytes: [ 0xc4, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4, z6"
+
+  -
+    input:
+      bytes: [ 0xe4, 0x7f, 0xdf, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmla z4.d, p7/m, z31.d, z31.d, #270"
+
+  -
+    input:
+      bytes: [ 0x95, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z21, z28"
+
+  -
+    input:
+      bytes: [ 0x55, 0x15, 0xf5, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmla z21.s, z10.s, z5.s[1], #90"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x40, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmla z0.h, p0/m, z0.h, z0.h, #0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x80, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmla z0.s, p0/m, z0.s, z0.s, #0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0xc0, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmla z0.d, p0/m, z0.d, z0.d, #0"
+
+  -
+    input:
+      bytes: [ 0x20, 0x20, 0x42, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmla z0.h, p0/m, z1.h, z2.h, #90"
+
+  -
+    input:
+      bytes: [ 0x20, 0x20, 0x82, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmla z0.s, p0/m, z1.s, z2.s, #90"
+
+  -
+    input:
+      bytes: [ 0x20, 0x20, 0xc2, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmla z0.d, p0/m, z1.d, z2.d, #90"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x5f, 0x5f, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmla z29.h, p7/m, z30.h, z31.h, #180"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x5f, 0x9f, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmla z29.s, p7/m, z30.s, z31.s, #180"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x5f, 0xdf, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmla z29.d, p7/m, z30.d, z31.d, #180"
+
+  -
+    input:
+      bytes: [ 0xff, 0x7f, 0x5f, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmla z31.h, p7/m, z31.h, z31.h, #270"
+
+  -
+    input:
+      bytes: [ 0xff, 0x7f, 0x9f, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmla z31.s, p7/m, z31.s, z31.s, #270"
+
+  -
+    input:
+      bytes: [ 0xff, 0x7f, 0xdf, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmla z31.d, p7/m, z31.d, z31.d, #270"
+
+  -
+    input:
+      bytes: [ 0x00, 0x10, 0xa0, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmla z0.h, z0.h, z0.h[0], #0"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x1d, 0xe8, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmla z23.s, z13.s, z8.s[0], #270"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0xbf, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmla z31.h, z31.h, z7.h[3], #270"
+
+  -
+    input:
+      bytes: [ 0x55, 0x15, 0xf5, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmla z21.s, z10.s, z5.s[1], #90"
+
+  -
+    input:
+      bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4.d, p7/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xe4, 0x7f, 0xdf, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmla z4.d, p7/m, z31.d, z31.d, #270"
+
+  -
+    input:
+      bytes: [ 0xc4, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4, z6"
+
+  -
+    input:
+      bytes: [ 0xe4, 0x7f, 0xdf, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmla z4.d, p7/m, z31.d, z31.d, #270"
+
+  -
+    input:
+      bytes: [ 0x95, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z21, z28"
+
+  -
+    input:
+      bytes: [ 0x55, 0x15, 0xf5, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmla z21.s, z10.s, z5.s[1], #90"
diff --git a/tests/MC/AArch64/SVE/fcmle.s.yaml b/tests/MC/AArch64/SVE/fcmle.s.yaml
new file mode 100644
index 000000000..6bf5268fb
--- /dev/null
+++ b/tests/MC/AArch64/SVE/fcmle.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x10, 0x20, 0x51, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmle p0.h, p0/z, z0.h, #0.0"
+
+  -
+    input:
+      bytes: [ 0x10, 0x20, 0x91, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmle p0.s, p0/z, z0.s, #0.0"
+
+  -
+    input:
+      bytes: [ 0x10, 0x20, 0xd1, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmle p0.d, p0/z, z0.d, #0.0"
+
+  -
+    input:
+      bytes: [ 0x20, 0x40, 0x40, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmge p0.h, p0/z, z1.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x40, 0x80, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmge p0.s, p0/z, z1.s, z0.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x40, 0xc0, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmge p0.d, p0/z, z1.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0x10, 0x20, 0x51, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmle p0.h, p0/z, z0.h, #0.0"
+
+  -
+    input:
+      bytes: [ 0x10, 0x20, 0x91, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmle p0.s, p0/z, z0.s, #0.0"
+
+  -
+    input:
+      bytes: [ 0x10, 0x20, 0xd1, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmle p0.d, p0/z, z0.d, #0.0"
+
+  -
+    input:
+      bytes: [ 0x20, 0x40, 0x40, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmge p0.h, p0/z, z1.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x40, 0x80, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmge p0.s, p0/z, z1.s, z0.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x40, 0xc0, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmge p0.d, p0/z, z1.d, z0.d"
diff --git a/tests/MC/AArch64/SVE/fcmlt.s.yaml b/tests/MC/AArch64/SVE/fcmlt.s.yaml
new file mode 100644
index 000000000..56ba75b4b
--- /dev/null
+++ b/tests/MC/AArch64/SVE/fcmlt.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x51, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmlt p0.h, p0/z, z0.h, #0.0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x91, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmlt p0.s, p0/z, z0.s, #0.0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0xd1, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmlt p0.d, p0/z, z0.d, #0.0"
+
+  -
+    input:
+      bytes: [ 0x30, 0x40, 0x40, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmgt p0.h, p0/z, z1.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x30, 0x40, 0x80, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmgt p0.s, p0/z, z1.s, z0.s"
+
+  -
+    input:
+      bytes: [ 0x30, 0x40, 0xc0, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmgt p0.d, p0/z, z1.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x51, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmlt p0.h, p0/z, z0.h, #0.0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x91, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmlt p0.s, p0/z, z0.s, #0.0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0xd1, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmlt p0.d, p0/z, z0.d, #0.0"
+
+  -
+    input:
+      bytes: [ 0x30, 0x40, 0x40, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmgt p0.h, p0/z, z1.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x30, 0x40, 0x80, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmgt p0.s, p0/z, z1.s, z0.s"
+
+  -
+    input:
+      bytes: [ 0x30, 0x40, 0xc0, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmgt p0.d, p0/z, z1.d, z0.d"
diff --git a/tests/MC/AArch64/SVE/fcmne.s.yaml b/tests/MC/AArch64/SVE/fcmne.s.yaml
new file mode 100644
index 000000000..e6d42c53f
--- /dev/null
+++ b/tests/MC/AArch64/SVE/fcmne.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x53, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmne p0.h, p0/z, z0.h, #0.0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x93, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmne p0.s, p0/z, z0.s, #0.0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0xd3, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmne p0.d, p0/z, z0.d, #0.0"
+
+  -
+    input:
+      bytes: [ 0x10, 0x60, 0x41, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmne p0.h, p0/z, z0.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0x10, 0x60, 0x81, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmne p0.s, p0/z, z0.s, z1.s"
+
+  -
+    input:
+      bytes: [ 0x10, 0x60, 0xc1, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmne p0.d, p0/z, z0.d, z1.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x53, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmne p0.h, p0/z, z0.h, #0.0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x93, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmne p0.s, p0/z, z0.s, #0.0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0xd3, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmne p0.d, p0/z, z0.d, #0.0"
+
+  -
+    input:
+      bytes: [ 0x10, 0x60, 0x41, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmne p0.h, p0/z, z0.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0x10, 0x60, 0x81, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmne p0.s, p0/z, z0.s, z1.s"
+
+  -
+    input:
+      bytes: [ 0x10, 0x60, 0xc1, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmne p0.d, p0/z, z0.d, z1.d"
diff --git a/tests/MC/AArch64/SVE/fcmuo.s.yaml b/tests/MC/AArch64/SVE/fcmuo.s.yaml
new file mode 100644
index 000000000..db45ab38d
--- /dev/null
+++ b/tests/MC/AArch64/SVE/fcmuo.s.yaml
@@ -0,0 +1,60 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x41, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmuo p0.h, p0/z, z0.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x81, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmuo p0.s, p0/z, z0.s, z1.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0xc1, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmuo p0.d, p0/z, z0.d, z1.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x41, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmuo p0.h, p0/z, z0.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x81, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmuo p0.s, p0/z, z0.s, z1.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0xc1, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmuo p0.d, p0/z, z0.d, z1.d"
diff --git a/tests/MC/AArch64/SVE/fcpy.s.yaml b/tests/MC/AArch64/SVE/fcpy.s.yaml
new file mode 100644
index 000000000..ce2eec104
--- /dev/null
+++ b/tests/MC/AArch64/SVE/fcpy.s.yaml
@@ -0,0 +1,5240 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xd8, 0x50, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.h, p0/m, #-0.12500000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd8, 0x90, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.s, p0/m, #-0.12500000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd8, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.12500000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd8, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.13281250"
+
+  -
+    input:
+      bytes: [ 0x40, 0xd8, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.14062500"
+
+  -
+    input:
+      bytes: [ 0x60, 0xd8, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.14843750"
+
+  -
+    input:
+      bytes: [ 0x80, 0xd8, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.15625000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xd8, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.16406250"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xd8, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.17187500"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xd8, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.17968750"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd9, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.18750000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd9, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.19531250"
+
+  -
+    input:
+      bytes: [ 0x40, 0xd9, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.20312500"
+
+  -
+    input:
+      bytes: [ 0x60, 0xd9, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.21093750"
+
+  -
+    input:
+      bytes: [ 0x80, 0xd9, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.21875000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xd9, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.22656250"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xd9, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.23437500"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xd9, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.24218750"
+
+  -
+    input:
+      bytes: [ 0x00, 0xda, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.25000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xda, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.26562500"
+
+  -
+    input:
+      bytes: [ 0x40, 0xda, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.28125000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xda, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.29687500"
+
+  -
+    input:
+      bytes: [ 0x80, 0xda, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.31250000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xda, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.32812500"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xda, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.34375000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xda, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.35937500"
+
+  -
+    input:
+      bytes: [ 0x00, 0xdb, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.37500000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xdb, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.39062500"
+
+  -
+    input:
+      bytes: [ 0x40, 0xdb, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.40625000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xdb, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.42187500"
+
+  -
+    input:
+      bytes: [ 0x80, 0xdb, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.43750000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xdb, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.45312500"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xdb, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.46875000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xdb, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.48437500"
+
+  -
+    input:
+      bytes: [ 0x00, 0xdc, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.50000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xdc, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.53125000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xdc, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.56250000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xdc, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.59375000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xdc, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.62500000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xdc, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.65625000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xdc, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.68750000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xdc, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.71875000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xdd, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.75000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xdd, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.78125000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xdd, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.81250000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xdd, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.84375000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xdd, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.87500000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xdd, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.90625000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xdd, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.93750000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xdd, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.96875000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xde, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-1.00000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xde, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-1.06250000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xde, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-1.12500000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xde, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-1.18750000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xde, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-1.25000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xde, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-1.31250000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xde, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-1.37500000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xde, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-1.43750000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xdf, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-1.50000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xdf, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-1.56250000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xdf, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-1.62500000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xdf, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-1.68750000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xdf, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-1.75000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xdf, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-1.81250000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xdf, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-1.87500000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xdf, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-1.93750000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd0, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-2.00000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd0, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-2.12500000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xd0, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-2.25000000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xd0, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-2.37500000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xd0, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-2.50000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xd0, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-2.62500000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xd0, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-2.75000000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xd0, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-2.87500000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd1, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-3.00000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd1, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-3.12500000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xd1, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-3.25000000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xd1, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-3.37500000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xd1, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-3.50000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xd1, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-3.62500000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xd1, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-3.75000000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xd1, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-3.87500000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd2, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-4.00000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd2, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-4.25000000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xd2, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-4.50000000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xd2, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-4.75000000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xd2, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-5.00000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xd2, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-5.25000000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xd2, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-5.50000000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xd2, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-5.75000000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd3, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-6.00000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd3, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-6.25000000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xd3, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-6.50000000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xd3, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-6.75000000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xd3, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-7.00000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xd3, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-7.25000000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xd3, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-7.50000000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xd3, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-7.75000000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd4, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-8.00000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd4, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-8.50000000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xd4, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-9.00000000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xd4, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-9.50000000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xd4, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-10.00000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xd4, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-10.50000000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xd4, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-11.00000000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xd4, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-11.50000000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd5, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-12.00000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd5, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-12.50000000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xd5, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-13.00000000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xd5, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-13.50000000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xd5, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-14.00000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xd5, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-14.50000000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xd5, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-15.00000000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xd5, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-15.50000000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd6, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-16.00000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd6, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-17.00000000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xd6, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-18.00000000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xd6, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-19.00000000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xd6, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-20.00000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xd6, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-21.00000000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xd6, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-22.00000000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xd6, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-23.00000000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd7, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-24.00000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd7, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-25.00000000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xd7, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-26.00000000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xd7, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-27.00000000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xd7, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-28.00000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xd7, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-29.00000000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xd7, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-30.00000000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xd7, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-31.00000000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc8, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.12500000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc8, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.13281250"
+
+  -
+    input:
+      bytes: [ 0x40, 0xc8, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.14062500"
+
+  -
+    input:
+      bytes: [ 0x60, 0xc8, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.14843750"
+
+  -
+    input:
+      bytes: [ 0x80, 0xc8, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.15625000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xc8, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.16406250"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xc8, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.17187500"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc8, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.17968750"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc9, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.18750000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc9, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.19531250"
+
+  -
+    input:
+      bytes: [ 0x40, 0xc9, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.20312500"
+
+  -
+    input:
+      bytes: [ 0x60, 0xc9, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.21093750"
+
+  -
+    input:
+      bytes: [ 0x80, 0xc9, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.21875000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xc9, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.22656250"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xc9, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.23437500"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc9, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.24218750"
+
+  -
+    input:
+      bytes: [ 0x00, 0xca, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.25000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xca, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.26562500"
+
+  -
+    input:
+      bytes: [ 0x40, 0xca, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.28125000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xca, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.29687500"
+
+  -
+    input:
+      bytes: [ 0x80, 0xca, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.31250000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xca, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.32812500"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xca, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.34375000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xca, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.35937500"
+
+  -
+    input:
+      bytes: [ 0x00, 0xcb, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.37500000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xcb, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.39062500"
+
+  -
+    input:
+      bytes: [ 0x40, 0xcb, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.40625000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xcb, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.42187500"
+
+  -
+    input:
+      bytes: [ 0x80, 0xcb, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.43750000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xcb, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.45312500"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xcb, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.46875000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xcb, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.48437500"
+
+  -
+    input:
+      bytes: [ 0x00, 0xcc, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.50000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xcc, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.53125000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xcc, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.56250000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xcc, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.59375000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xcc, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.62500000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xcc, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.65625000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xcc, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.68750000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xcc, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.71875000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xcd, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.75000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xcd, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.78125000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xcd, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.81250000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xcd, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.84375000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xcd, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.87500000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xcd, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.90625000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xcd, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.93750000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xcd, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.96875000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xce, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #1.00000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xce, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #1.06250000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xce, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #1.12500000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xce, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #1.18750000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xce, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #1.25000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xce, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #1.31250000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xce, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #1.37500000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xce, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #1.43750000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xcf, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #1.50000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xcf, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #1.56250000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xcf, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #1.62500000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xcf, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #1.68750000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xcf, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #1.75000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xcf, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #1.81250000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xcf, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #1.87500000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xcf, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #1.93750000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #2.00000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc0, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #2.12500000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xc0, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #2.25000000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xc0, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #2.37500000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xc0, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #2.50000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xc0, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #2.62500000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xc0, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #2.75000000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc0, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #2.87500000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc1, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #3.00000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc1, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #3.12500000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xc1, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #3.25000000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xc1, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #3.37500000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xc1, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #3.50000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xc1, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #3.62500000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xc1, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #3.75000000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc1, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #3.87500000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc2, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #4.00000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc2, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #4.25000000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xc2, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #4.50000000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xc2, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #4.75000000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xc2, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #5.00000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xc2, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #5.25000000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xc2, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #5.50000000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc2, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #5.75000000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc3, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #6.00000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc3, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #6.25000000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xc3, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #6.50000000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xc3, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #6.75000000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xc3, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #7.00000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xc3, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #7.25000000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xc3, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #7.50000000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc3, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #7.75000000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc4, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #8.00000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc4, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #8.50000000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xc4, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #9.00000000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xc4, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #9.50000000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xc4, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #10.00000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xc4, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #10.50000000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xc4, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #11.00000000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc4, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #11.50000000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc5, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #12.00000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc5, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #12.50000000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xc5, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #13.00000000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xc5, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #13.50000000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xc5, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #14.00000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xc5, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #14.50000000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xc5, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #15.00000000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc5, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #15.50000000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc6, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #16.00000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc6, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #17.00000000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xc6, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #18.00000000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xc6, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #19.00000000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xc6, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #20.00000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xc6, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #21.00000000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xc6, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #22.00000000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc6, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #23.00000000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc7, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #24.00000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc7, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #25.00000000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xc7, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #26.00000000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xc7, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #27.00000000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xc7, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #28.00000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xc7, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #29.00000000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xc7, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #30.00000000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc7, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #31.00000000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0.d, p0/z, z7.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc7, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #31.00000000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc7, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #31.00000000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd8, 0x50, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.h, p0/m, #-0.12500000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd8, 0x90, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.s, p0/m, #-0.12500000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd8, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.12500000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd8, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.13281250"
+
+  -
+    input:
+      bytes: [ 0x40, 0xd8, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.14062500"
+
+  -
+    input:
+      bytes: [ 0x60, 0xd8, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.14843750"
+
+  -
+    input:
+      bytes: [ 0x80, 0xd8, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.15625000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xd8, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.16406250"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xd8, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.17187500"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xd8, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.17968750"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd9, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.18750000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd9, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.19531250"
+
+  -
+    input:
+      bytes: [ 0x40, 0xd9, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.20312500"
+
+  -
+    input:
+      bytes: [ 0x60, 0xd9, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.21093750"
+
+  -
+    input:
+      bytes: [ 0x80, 0xd9, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.21875000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xd9, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.22656250"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xd9, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.23437500"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xd9, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.24218750"
+
+  -
+    input:
+      bytes: [ 0x00, 0xda, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.25000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xda, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.26562500"
+
+  -
+    input:
+      bytes: [ 0x40, 0xda, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.28125000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xda, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.29687500"
+
+  -
+    input:
+      bytes: [ 0x80, 0xda, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.31250000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xda, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.32812500"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xda, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.34375000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xda, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.35937500"
+
+  -
+    input:
+      bytes: [ 0x00, 0xdb, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.37500000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xdb, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.39062500"
+
+  -
+    input:
+      bytes: [ 0x40, 0xdb, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.40625000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xdb, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.42187500"
+
+  -
+    input:
+      bytes: [ 0x80, 0xdb, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.43750000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xdb, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.45312500"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xdb, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.46875000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xdb, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.48437500"
+
+  -
+    input:
+      bytes: [ 0x00, 0xdc, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.50000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xdc, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.53125000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xdc, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.56250000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xdc, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.59375000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xdc, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.62500000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xdc, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.65625000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xdc, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.68750000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xdc, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.71875000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xdd, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.75000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xdd, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.78125000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xdd, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.81250000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xdd, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.84375000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xdd, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.87500000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xdd, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.90625000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xdd, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.93750000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xdd, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.96875000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xde, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-1.00000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xde, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-1.06250000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xde, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-1.12500000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xde, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-1.18750000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xde, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-1.25000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xde, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-1.31250000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xde, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-1.37500000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xde, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-1.43750000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xdf, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-1.50000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xdf, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-1.56250000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xdf, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-1.62500000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xdf, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-1.68750000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xdf, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-1.75000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xdf, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-1.81250000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xdf, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-1.87500000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xdf, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-1.93750000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd0, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-2.00000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd0, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-2.12500000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xd0, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-2.25000000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xd0, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-2.37500000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xd0, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-2.50000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xd0, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-2.62500000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xd0, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-2.75000000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xd0, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-2.87500000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd1, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-3.00000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd1, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-3.12500000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xd1, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-3.25000000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xd1, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-3.37500000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xd1, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-3.50000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xd1, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-3.62500000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xd1, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-3.75000000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xd1, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-3.87500000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd2, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-4.00000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd2, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-4.25000000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xd2, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-4.50000000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xd2, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-4.75000000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xd2, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-5.00000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xd2, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-5.25000000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xd2, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-5.50000000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xd2, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-5.75000000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd3, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-6.00000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd3, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-6.25000000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xd3, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-6.50000000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xd3, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-6.75000000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xd3, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-7.00000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xd3, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-7.25000000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xd3, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-7.50000000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xd3, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-7.75000000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd4, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-8.00000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd4, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-8.50000000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xd4, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-9.00000000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xd4, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-9.50000000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xd4, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-10.00000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xd4, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-10.50000000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xd4, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-11.00000000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xd4, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-11.50000000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd5, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-12.00000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd5, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-12.50000000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xd5, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-13.00000000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xd5, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-13.50000000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xd5, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-14.00000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xd5, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-14.50000000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xd5, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-15.00000000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xd5, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-15.50000000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd6, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-16.00000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd6, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-17.00000000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xd6, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-18.00000000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xd6, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-19.00000000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xd6, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-20.00000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xd6, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-21.00000000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xd6, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-22.00000000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xd6, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-23.00000000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd7, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-24.00000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd7, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-25.00000000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xd7, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-26.00000000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xd7, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-27.00000000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xd7, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-28.00000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xd7, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-29.00000000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xd7, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-30.00000000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xd7, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-31.00000000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc8, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.12500000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc8, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.13281250"
+
+  -
+    input:
+      bytes: [ 0x40, 0xc8, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.14062500"
+
+  -
+    input:
+      bytes: [ 0x60, 0xc8, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.14843750"
+
+  -
+    input:
+      bytes: [ 0x80, 0xc8, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.15625000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xc8, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.16406250"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xc8, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.17187500"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc8, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.17968750"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc9, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.18750000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc9, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.19531250"
+
+  -
+    input:
+      bytes: [ 0x40, 0xc9, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.20312500"
+
+  -
+    input:
+      bytes: [ 0x60, 0xc9, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.21093750"
+
+  -
+    input:
+      bytes: [ 0x80, 0xc9, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.21875000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xc9, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.22656250"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xc9, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.23437500"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc9, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.24218750"
+
+  -
+    input:
+      bytes: [ 0x00, 0xca, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.25000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xca, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.26562500"
+
+  -
+    input:
+      bytes: [ 0x40, 0xca, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.28125000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xca, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.29687500"
+
+  -
+    input:
+      bytes: [ 0x80, 0xca, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.31250000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xca, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.32812500"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xca, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.34375000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xca, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.35937500"
+
+  -
+    input:
+      bytes: [ 0x00, 0xcb, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.37500000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xcb, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.39062500"
+
+  -
+    input:
+      bytes: [ 0x40, 0xcb, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.40625000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xcb, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.42187500"
+
+  -
+    input:
+      bytes: [ 0x80, 0xcb, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.43750000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xcb, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.45312500"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xcb, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.46875000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xcb, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.48437500"
+
+  -
+    input:
+      bytes: [ 0x00, 0xcc, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.50000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xcc, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.53125000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xcc, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.56250000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xcc, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.59375000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xcc, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.62500000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xcc, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.65625000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xcc, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.68750000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xcc, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.71875000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xcd, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.75000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xcd, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.78125000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xcd, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.81250000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xcd, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.84375000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xcd, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.87500000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xcd, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.90625000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xcd, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.93750000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xcd, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.96875000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xce, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #1.00000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xce, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #1.06250000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xce, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #1.12500000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xce, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #1.18750000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xce, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #1.25000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xce, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #1.31250000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xce, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #1.37500000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xce, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #1.43750000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xcf, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #1.50000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xcf, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #1.56250000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xcf, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #1.62500000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xcf, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #1.68750000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xcf, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #1.75000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xcf, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #1.81250000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xcf, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #1.87500000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xcf, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #1.93750000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #2.00000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc0, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #2.12500000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xc0, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #2.25000000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xc0, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #2.37500000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xc0, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #2.50000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xc0, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #2.62500000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xc0, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #2.75000000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc0, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #2.87500000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc1, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #3.00000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc1, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #3.12500000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xc1, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #3.25000000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xc1, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #3.37500000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xc1, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #3.50000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xc1, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #3.62500000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xc1, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #3.75000000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc1, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #3.87500000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc2, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #4.00000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc2, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #4.25000000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xc2, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #4.50000000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xc2, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #4.75000000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xc2, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #5.00000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xc2, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #5.25000000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xc2, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #5.50000000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc2, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #5.75000000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc3, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #6.00000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc3, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #6.25000000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xc3, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #6.50000000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xc3, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #6.75000000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xc3, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #7.00000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xc3, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #7.25000000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xc3, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #7.50000000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc3, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #7.75000000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc4, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #8.00000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc4, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #8.50000000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xc4, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #9.00000000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xc4, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #9.50000000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xc4, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #10.00000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xc4, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #10.50000000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xc4, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #11.00000000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc4, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #11.50000000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc5, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #12.00000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc5, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #12.50000000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xc5, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #13.00000000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xc5, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #13.50000000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xc5, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #14.00000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xc5, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #14.50000000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xc5, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #15.00000000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc5, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #15.50000000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc6, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #16.00000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc6, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #17.00000000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xc6, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #18.00000000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xc6, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #19.00000000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xc6, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #20.00000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xc6, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #21.00000000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xc6, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #22.00000000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc6, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #23.00000000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc7, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #24.00000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc7, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #25.00000000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xc7, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #26.00000000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xc7, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #27.00000000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xc7, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #28.00000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xc7, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #29.00000000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xc7, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #30.00000000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc7, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #31.00000000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0.d, p0/z, z7.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc7, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #31.00000000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc7, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #31.00000000"
diff --git a/tests/MC/AArch64/SVE/fcvt.s.yaml b/tests/MC/AArch64/SVE/fcvt.s.yaml
new file mode 100644
index 000000000..c1ad59433
--- /dev/null
+++ b/tests/MC/AArch64/SVE/fcvt.s.yaml
@@ -0,0 +1,200 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x88, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvt z0.h, p0/m, z0.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xc8, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvt z0.h, p0/m, z0.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x89, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvt z0.s, p0/m, z0.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xca, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvt z0.s, p0/m, z0.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xc9, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvt z0.d, p0/m, z0.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xcb, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvt z0.d, p0/m, z0.s"
+
+  -
+    input:
+      bytes: [ 0xe5, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z5.d, p0/z, z7.d"
+
+  -
+    input:
+      bytes: [ 0x05, 0xa0, 0xcb, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvt z5.d, p0/m, z0.s"
+
+  -
+    input:
+      bytes: [ 0xe5, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z5, z7"
+
+  -
+    input:
+      bytes: [ 0x05, 0xa0, 0xcb, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvt z5.d, p0/m, z0.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x88, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvt z0.h, p0/m, z0.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xc8, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvt z0.h, p0/m, z0.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x89, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvt z0.s, p0/m, z0.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xca, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvt z0.s, p0/m, z0.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xc9, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvt z0.d, p0/m, z0.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xcb, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvt z0.d, p0/m, z0.s"
+
+  -
+    input:
+      bytes: [ 0xe5, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z5.d, p0/z, z7.d"
+
+  -
+    input:
+      bytes: [ 0x05, 0xa0, 0xcb, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvt z5.d, p0/m, z0.s"
+
+  -
+    input:
+      bytes: [ 0xe5, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z5, z7"
+
+  -
+    input:
+      bytes: [ 0x05, 0xa0, 0xcb, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvt z5.d, p0/m, z0.s"
diff --git a/tests/MC/AArch64/SVE/fcvtzs.s.yaml b/tests/MC/AArch64/SVE/fcvtzs.s.yaml
new file mode 100644
index 000000000..0d9fab205
--- /dev/null
+++ b/tests/MC/AArch64/SVE/fcvtzs.s.yaml
@@ -0,0 +1,220 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x5a, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtzs z0.h, p0/m, z0.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x5c, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtzs z0.s, p0/m, z0.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x9c, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtzs z0.s, p0/m, z0.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xd8, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtzs z0.s, p0/m, z0.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x5e, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtzs z0.d, p0/m, z0.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xdc, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtzs z0.d, p0/m, z0.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xde, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtzs z0.d, p0/m, z0.d"
+
+  -
+    input:
+      bytes: [ 0xe5, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z5.d, p0/z, z7.d"
+
+  -
+    input:
+      bytes: [ 0x05, 0xa0, 0xde, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtzs z5.d, p0/m, z0.d"
+
+  -
+    input:
+      bytes: [ 0xe5, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z5, z7"
+
+  -
+    input:
+      bytes: [ 0x05, 0xa0, 0xde, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtzs z5.d, p0/m, z0.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x5a, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtzs z0.h, p0/m, z0.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x5c, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtzs z0.s, p0/m, z0.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x9c, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtzs z0.s, p0/m, z0.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xd8, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtzs z0.s, p0/m, z0.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x5e, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtzs z0.d, p0/m, z0.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xdc, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtzs z0.d, p0/m, z0.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xde, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtzs z0.d, p0/m, z0.d"
+
+  -
+    input:
+      bytes: [ 0xe5, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z5.d, p0/z, z7.d"
+
+  -
+    input:
+      bytes: [ 0x05, 0xa0, 0xde, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtzs z5.d, p0/m, z0.d"
+
+  -
+    input:
+      bytes: [ 0xe5, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z5, z7"
+
+  -
+    input:
+      bytes: [ 0x05, 0xa0, 0xde, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtzs z5.d, p0/m, z0.d"
diff --git a/tests/MC/AArch64/SVE/fcvtzu.s.yaml b/tests/MC/AArch64/SVE/fcvtzu.s.yaml
new file mode 100644
index 000000000..0047f6ebc
--- /dev/null
+++ b/tests/MC/AArch64/SVE/fcvtzu.s.yaml
@@ -0,0 +1,220 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x5b, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtzu z0.h, p0/m, z0.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x5d, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtzu z0.s, p0/m, z0.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x9d, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtzu z0.s, p0/m, z0.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xd9, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtzu z0.s, p0/m, z0.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x5f, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtzu z0.d, p0/m, z0.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xdd, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtzu z0.d, p0/m, z0.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xdf, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtzu z0.d, p0/m, z0.d"
+
+  -
+    input:
+      bytes: [ 0xe5, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z5.d, p0/z, z7.d"
+
+  -
+    input:
+      bytes: [ 0x05, 0xa0, 0xdf, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtzu z5.d, p0/m, z0.d"
+
+  -
+    input:
+      bytes: [ 0xe5, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z5, z7"
+
+  -
+    input:
+      bytes: [ 0x05, 0xa0, 0xdf, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtzu z5.d, p0/m, z0.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x5b, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtzu z0.h, p0/m, z0.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x5d, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtzu z0.s, p0/m, z0.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x9d, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtzu z0.s, p0/m, z0.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xd9, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtzu z0.s, p0/m, z0.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x5f, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtzu z0.d, p0/m, z0.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xdd, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtzu z0.d, p0/m, z0.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xdf, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtzu z0.d, p0/m, z0.d"
+
+  -
+    input:
+      bytes: [ 0xe5, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z5.d, p0/z, z7.d"
+
+  -
+    input:
+      bytes: [ 0x05, 0xa0, 0xdf, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtzu z5.d, p0/m, z0.d"
+
+  -
+    input:
+      bytes: [ 0xe5, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z5, z7"
+
+  -
+    input:
+      bytes: [ 0x05, 0xa0, 0xdf, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtzu z5.d, p0/m, z0.d"
diff --git a/tests/MC/AArch64/SVE/fdiv.s.yaml b/tests/MC/AArch64/SVE/fdiv.s.yaml
new file mode 100644
index 000000000..1cf952788
--- /dev/null
+++ b/tests/MC/AArch64/SVE/fdiv.s.yaml
@@ -0,0 +1,140 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0x4d, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdiv z0.h, p7/m, z0.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0x8d, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdiv z0.s, p7/m, z0.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xcd, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdiv z0.d, p7/m, z0.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0.d, p7/z, z7.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xcd, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdiv z0.d, p7/m, z0.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xcd, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdiv z0.d, p7/m, z0.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0x4d, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdiv z0.h, p7/m, z0.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0x8d, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdiv z0.s, p7/m, z0.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xcd, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdiv z0.d, p7/m, z0.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0.d, p7/z, z7.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xcd, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdiv z0.d, p7/m, z0.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xcd, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdiv z0.d, p7/m, z0.d, z31.d"
diff --git a/tests/MC/AArch64/SVE/fdivr.s.yaml b/tests/MC/AArch64/SVE/fdivr.s.yaml
new file mode 100644
index 000000000..49e6b9286
--- /dev/null
+++ b/tests/MC/AArch64/SVE/fdivr.s.yaml
@@ -0,0 +1,140 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0x4c, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdivr z0.h, p7/m, z0.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0x8c, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdivr z0.s, p7/m, z0.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xcc, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdivr z0.d, p7/m, z0.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0.d, p7/z, z7.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xcc, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdivr z0.d, p7/m, z0.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xcc, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdivr z0.d, p7/m, z0.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0x4c, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdivr z0.h, p7/m, z0.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0x8c, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdivr z0.s, p7/m, z0.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xcc, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdivr z0.d, p7/m, z0.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0.d, p7/z, z7.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xcc, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdivr z0.d, p7/m, z0.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xcc, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdivr z0.d, p7/m, z0.d, z31.d"
diff --git a/tests/MC/AArch64/SVE/fdup.s.yaml b/tests/MC/AArch64/SVE/fdup.s.yaml
new file mode 100644
index 000000000..9195f8ee5
--- /dev/null
+++ b/tests/MC/AArch64/SVE/fdup.s.yaml
@@ -0,0 +1,5160 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xd8, 0x79, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.h, #-0.12500000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd8, 0xb9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.s, #-0.12500000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd8, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-0.12500000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd8, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-0.13281250"
+
+  -
+    input:
+      bytes: [ 0x40, 0xd8, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-0.14062500"
+
+  -
+    input:
+      bytes: [ 0x60, 0xd8, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-0.14843750"
+
+  -
+    input:
+      bytes: [ 0x80, 0xd8, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-0.15625000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xd8, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-0.16406250"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xd8, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-0.17187500"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xd8, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-0.17968750"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd9, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-0.18750000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd9, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-0.19531250"
+
+  -
+    input:
+      bytes: [ 0x40, 0xd9, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-0.20312500"
+
+  -
+    input:
+      bytes: [ 0x60, 0xd9, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-0.21093750"
+
+  -
+    input:
+      bytes: [ 0x80, 0xd9, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-0.21875000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xd9, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-0.22656250"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xd9, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-0.23437500"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xd9, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-0.24218750"
+
+  -
+    input:
+      bytes: [ 0x00, 0xda, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-0.25000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xda, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-0.26562500"
+
+  -
+    input:
+      bytes: [ 0x40, 0xda, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-0.28125000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xda, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-0.29687500"
+
+  -
+    input:
+      bytes: [ 0x80, 0xda, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-0.31250000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xda, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-0.32812500"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xda, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-0.34375000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xda, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-0.35937500"
+
+  -
+    input:
+      bytes: [ 0x00, 0xdb, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-0.37500000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xdb, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-0.39062500"
+
+  -
+    input:
+      bytes: [ 0x40, 0xdb, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-0.40625000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xdb, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-0.42187500"
+
+  -
+    input:
+      bytes: [ 0x80, 0xdb, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-0.43750000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xdb, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-0.45312500"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xdb, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-0.46875000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xdb, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-0.48437500"
+
+  -
+    input:
+      bytes: [ 0x00, 0xdc, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-0.50000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xdc, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-0.53125000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xdc, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-0.56250000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xdc, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-0.59375000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xdc, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-0.62500000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xdc, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-0.65625000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xdc, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-0.68750000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xdc, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-0.71875000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xdd, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-0.75000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xdd, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-0.78125000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xdd, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-0.81250000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xdd, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-0.84375000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xdd, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-0.87500000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xdd, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-0.90625000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xdd, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-0.93750000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xdd, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-0.96875000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xde, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-1.00000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xde, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-1.06250000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xde, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-1.12500000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xde, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-1.18750000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xde, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-1.25000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xde, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-1.31250000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xde, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-1.37500000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xde, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-1.43750000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xdf, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-1.50000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xdf, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-1.56250000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xdf, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-1.62500000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xdf, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-1.68750000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xdf, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-1.75000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xdf, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-1.81250000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xdf, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-1.87500000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xdf, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-1.93750000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd0, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-2.00000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd0, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-2.12500000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xd0, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-2.25000000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xd0, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-2.37500000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xd0, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-2.50000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xd0, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-2.62500000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xd0, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-2.75000000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xd0, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-2.87500000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd1, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-3.00000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd1, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-3.12500000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xd1, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-3.25000000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xd1, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-3.37500000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xd1, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-3.50000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xd1, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-3.62500000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xd1, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-3.75000000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xd1, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-3.87500000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd2, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-4.00000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd2, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-4.25000000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xd2, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-4.50000000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xd2, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-4.75000000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xd2, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-5.00000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xd2, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-5.25000000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xd2, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-5.50000000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xd2, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-5.75000000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd3, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-6.00000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd3, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-6.25000000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xd3, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-6.50000000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xd3, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-6.75000000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xd3, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-7.00000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xd3, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-7.25000000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xd3, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-7.50000000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xd3, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-7.75000000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd4, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-8.00000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd4, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-8.50000000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xd4, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-9.00000000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xd4, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-9.50000000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xd4, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-10.00000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xd4, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-10.50000000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xd4, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-11.00000000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xd4, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-11.50000000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd5, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-12.00000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd5, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-12.50000000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xd5, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-13.00000000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xd5, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-13.50000000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xd5, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-14.00000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xd5, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-14.50000000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xd5, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-15.00000000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xd5, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-15.50000000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd6, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-16.00000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd6, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-17.00000000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xd6, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-18.00000000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xd6, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-19.00000000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xd6, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-20.00000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xd6, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-21.00000000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xd6, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-22.00000000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xd6, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-23.00000000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd7, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-24.00000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd7, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-25.00000000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xd7, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-26.00000000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xd7, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-27.00000000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xd7, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-28.00000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xd7, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-29.00000000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xd7, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-30.00000000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xd7, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-31.00000000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc8, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #0.12500000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc8, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #0.13281250"
+
+  -
+    input:
+      bytes: [ 0x40, 0xc8, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #0.14062500"
+
+  -
+    input:
+      bytes: [ 0x60, 0xc8, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #0.14843750"
+
+  -
+    input:
+      bytes: [ 0x80, 0xc8, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #0.15625000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xc8, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #0.16406250"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xc8, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #0.17187500"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc8, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #0.17968750"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc9, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #0.18750000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc9, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #0.19531250"
+
+  -
+    input:
+      bytes: [ 0x40, 0xc9, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #0.20312500"
+
+  -
+    input:
+      bytes: [ 0x60, 0xc9, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #0.21093750"
+
+  -
+    input:
+      bytes: [ 0x80, 0xc9, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #0.21875000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xc9, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #0.22656250"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xc9, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #0.23437500"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc9, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #0.24218750"
+
+  -
+    input:
+      bytes: [ 0x00, 0xca, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #0.25000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xca, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #0.26562500"
+
+  -
+    input:
+      bytes: [ 0x40, 0xca, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #0.28125000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xca, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #0.29687500"
+
+  -
+    input:
+      bytes: [ 0x80, 0xca, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #0.31250000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xca, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #0.32812500"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xca, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #0.34375000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xca, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #0.35937500"
+
+  -
+    input:
+      bytes: [ 0x00, 0xcb, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #0.37500000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xcb, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #0.39062500"
+
+  -
+    input:
+      bytes: [ 0x40, 0xcb, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #0.40625000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xcb, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #0.42187500"
+
+  -
+    input:
+      bytes: [ 0x80, 0xcb, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #0.43750000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xcb, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #0.45312500"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xcb, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #0.46875000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xcb, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #0.48437500"
+
+  -
+    input:
+      bytes: [ 0x00, 0xcc, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #0.50000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xcc, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #0.53125000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xcc, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #0.56250000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xcc, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #0.59375000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xcc, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #0.62500000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xcc, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #0.65625000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xcc, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #0.68750000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xcc, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #0.71875000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xcd, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #0.75000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xcd, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #0.78125000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xcd, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #0.81250000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xcd, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #0.84375000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xcd, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #0.87500000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xcd, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #0.90625000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xcd, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #0.93750000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xcd, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #0.96875000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xce, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #1.00000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xce, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #1.06250000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xce, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #1.12500000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xce, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #1.18750000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xce, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #1.25000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xce, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #1.31250000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xce, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #1.37500000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xce, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #1.43750000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xcf, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #1.50000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xcf, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #1.56250000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xcf, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #1.62500000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xcf, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #1.68750000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xcf, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #1.75000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xcf, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #1.81250000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xcf, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #1.87500000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xcf, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #1.93750000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #2.00000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc0, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #2.12500000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xc0, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #2.25000000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xc0, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #2.37500000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xc0, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #2.50000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xc0, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #2.62500000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xc0, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #2.75000000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc0, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #2.87500000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc1, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #3.00000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc1, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #3.12500000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xc1, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #3.25000000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xc1, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #3.37500000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xc1, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #3.50000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xc1, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #3.62500000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xc1, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #3.75000000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc1, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #3.87500000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc2, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #4.00000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc2, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #4.25000000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xc2, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #4.50000000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xc2, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #4.75000000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xc2, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #5.00000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xc2, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #5.25000000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xc2, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #5.50000000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc2, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #5.75000000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc3, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #6.00000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc3, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #6.25000000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xc3, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #6.50000000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xc3, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #6.75000000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xc3, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #7.00000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xc3, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #7.25000000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xc3, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #7.50000000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc3, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #7.75000000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc4, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #8.00000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc4, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #8.50000000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xc4, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #9.00000000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xc4, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #9.50000000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xc4, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #10.00000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xc4, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #10.50000000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xc4, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #11.00000000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc4, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #11.50000000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc5, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #12.00000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc5, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #12.50000000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xc5, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #13.00000000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xc5, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #13.50000000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xc5, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #14.00000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xc5, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #14.50000000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xc5, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #15.00000000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc5, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #15.50000000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc6, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #16.00000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc6, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #17.00000000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xc6, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #18.00000000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xc6, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #19.00000000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xc6, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #20.00000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xc6, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #21.00000000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xc6, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #22.00000000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc6, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #23.00000000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc7, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #24.00000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc7, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #25.00000000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xc7, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #26.00000000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xc7, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #27.00000000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xc7, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #28.00000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xc7, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #29.00000000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xc7, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #30.00000000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc7, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #31.00000000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd8, 0x79, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.h, #-0.12500000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd8, 0xb9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.s, #-0.12500000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd8, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-0.12500000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd8, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-0.13281250"
+
+  -
+    input:
+      bytes: [ 0x40, 0xd8, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-0.14062500"
+
+  -
+    input:
+      bytes: [ 0x60, 0xd8, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-0.14843750"
+
+  -
+    input:
+      bytes: [ 0x80, 0xd8, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-0.15625000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xd8, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-0.16406250"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xd8, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-0.17187500"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xd8, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-0.17968750"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd9, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-0.18750000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd9, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-0.19531250"
+
+  -
+    input:
+      bytes: [ 0x40, 0xd9, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-0.20312500"
+
+  -
+    input:
+      bytes: [ 0x60, 0xd9, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-0.21093750"
+
+  -
+    input:
+      bytes: [ 0x80, 0xd9, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-0.21875000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xd9, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-0.22656250"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xd9, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-0.23437500"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xd9, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-0.24218750"
+
+  -
+    input:
+      bytes: [ 0x00, 0xda, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-0.25000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xda, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-0.26562500"
+
+  -
+    input:
+      bytes: [ 0x40, 0xda, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-0.28125000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xda, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-0.29687500"
+
+  -
+    input:
+      bytes: [ 0x80, 0xda, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-0.31250000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xda, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-0.32812500"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xda, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-0.34375000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xda, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-0.35937500"
+
+  -
+    input:
+      bytes: [ 0x00, 0xdb, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-0.37500000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xdb, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-0.39062500"
+
+  -
+    input:
+      bytes: [ 0x40, 0xdb, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-0.40625000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xdb, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-0.42187500"
+
+  -
+    input:
+      bytes: [ 0x80, 0xdb, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-0.43750000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xdb, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-0.45312500"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xdb, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-0.46875000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xdb, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-0.48437500"
+
+  -
+    input:
+      bytes: [ 0x00, 0xdc, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-0.50000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xdc, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-0.53125000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xdc, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-0.56250000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xdc, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-0.59375000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xdc, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-0.62500000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xdc, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-0.65625000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xdc, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-0.68750000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xdc, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-0.71875000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xdd, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-0.75000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xdd, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-0.78125000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xdd, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-0.81250000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xdd, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-0.84375000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xdd, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-0.87500000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xdd, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-0.90625000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xdd, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-0.93750000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xdd, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-0.96875000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xde, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-1.00000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xde, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-1.06250000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xde, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-1.12500000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xde, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-1.18750000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xde, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-1.25000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xde, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-1.31250000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xde, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-1.37500000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xde, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-1.43750000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xdf, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-1.50000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xdf, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-1.56250000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xdf, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-1.62500000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xdf, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-1.68750000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xdf, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-1.75000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xdf, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-1.81250000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xdf, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-1.87500000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xdf, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-1.93750000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd0, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-2.00000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd0, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-2.12500000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xd0, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-2.25000000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xd0, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-2.37500000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xd0, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-2.50000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xd0, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-2.62500000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xd0, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-2.75000000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xd0, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-2.87500000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd1, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-3.00000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd1, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-3.12500000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xd1, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-3.25000000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xd1, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-3.37500000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xd1, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-3.50000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xd1, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-3.62500000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xd1, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-3.75000000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xd1, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-3.87500000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd2, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-4.00000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd2, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-4.25000000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xd2, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-4.50000000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xd2, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-4.75000000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xd2, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-5.00000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xd2, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-5.25000000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xd2, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-5.50000000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xd2, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-5.75000000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd3, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-6.00000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd3, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-6.25000000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xd3, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-6.50000000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xd3, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-6.75000000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xd3, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-7.00000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xd3, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-7.25000000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xd3, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-7.50000000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xd3, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-7.75000000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd4, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-8.00000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd4, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-8.50000000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xd4, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-9.00000000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xd4, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-9.50000000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xd4, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-10.00000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xd4, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-10.50000000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xd4, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-11.00000000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xd4, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-11.50000000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd5, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-12.00000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd5, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-12.50000000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xd5, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-13.00000000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xd5, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-13.50000000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xd5, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-14.00000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xd5, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-14.50000000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xd5, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-15.00000000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xd5, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-15.50000000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd6, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-16.00000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd6, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-17.00000000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xd6, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-18.00000000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xd6, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-19.00000000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xd6, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-20.00000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xd6, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-21.00000000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xd6, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-22.00000000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xd6, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-23.00000000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd7, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-24.00000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd7, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-25.00000000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xd7, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-26.00000000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xd7, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-27.00000000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xd7, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-28.00000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xd7, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-29.00000000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xd7, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-30.00000000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xd7, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-31.00000000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc8, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #0.12500000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc8, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #0.13281250"
+
+  -
+    input:
+      bytes: [ 0x40, 0xc8, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #0.14062500"
+
+  -
+    input:
+      bytes: [ 0x60, 0xc8, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #0.14843750"
+
+  -
+    input:
+      bytes: [ 0x80, 0xc8, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #0.15625000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xc8, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #0.16406250"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xc8, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #0.17187500"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc8, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #0.17968750"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc9, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #0.18750000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc9, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #0.19531250"
+
+  -
+    input:
+      bytes: [ 0x40, 0xc9, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #0.20312500"
+
+  -
+    input:
+      bytes: [ 0x60, 0xc9, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #0.21093750"
+
+  -
+    input:
+      bytes: [ 0x80, 0xc9, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #0.21875000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xc9, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #0.22656250"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xc9, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #0.23437500"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc9, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #0.24218750"
+
+  -
+    input:
+      bytes: [ 0x00, 0xca, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #0.25000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xca, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #0.26562500"
+
+  -
+    input:
+      bytes: [ 0x40, 0xca, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #0.28125000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xca, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #0.29687500"
+
+  -
+    input:
+      bytes: [ 0x80, 0xca, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #0.31250000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xca, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #0.32812500"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xca, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #0.34375000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xca, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #0.35937500"
+
+  -
+    input:
+      bytes: [ 0x00, 0xcb, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #0.37500000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xcb, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #0.39062500"
+
+  -
+    input:
+      bytes: [ 0x40, 0xcb, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #0.40625000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xcb, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #0.42187500"
+
+  -
+    input:
+      bytes: [ 0x80, 0xcb, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #0.43750000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xcb, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #0.45312500"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xcb, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #0.46875000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xcb, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #0.48437500"
+
+  -
+    input:
+      bytes: [ 0x00, 0xcc, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #0.50000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xcc, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #0.53125000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xcc, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #0.56250000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xcc, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #0.59375000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xcc, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #0.62500000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xcc, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #0.65625000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xcc, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #0.68750000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xcc, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #0.71875000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xcd, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #0.75000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xcd, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #0.78125000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xcd, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #0.81250000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xcd, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #0.84375000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xcd, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #0.87500000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xcd, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #0.90625000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xcd, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #0.93750000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xcd, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #0.96875000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xce, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #1.00000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xce, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #1.06250000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xce, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #1.12500000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xce, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #1.18750000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xce, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #1.25000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xce, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #1.31250000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xce, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #1.37500000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xce, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #1.43750000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xcf, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #1.50000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xcf, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #1.56250000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xcf, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #1.62500000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xcf, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #1.68750000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xcf, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #1.75000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xcf, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #1.81250000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xcf, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #1.87500000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xcf, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #1.93750000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #2.00000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc0, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #2.12500000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xc0, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #2.25000000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xc0, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #2.37500000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xc0, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #2.50000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xc0, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #2.62500000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xc0, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #2.75000000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc0, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #2.87500000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc1, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #3.00000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc1, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #3.12500000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xc1, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #3.25000000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xc1, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #3.37500000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xc1, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #3.50000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xc1, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #3.62500000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xc1, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #3.75000000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc1, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #3.87500000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc2, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #4.00000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc2, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #4.25000000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xc2, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #4.50000000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xc2, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #4.75000000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xc2, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #5.00000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xc2, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #5.25000000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xc2, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #5.50000000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc2, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #5.75000000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc3, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #6.00000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc3, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #6.25000000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xc3, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #6.50000000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xc3, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #6.75000000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xc3, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #7.00000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xc3, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #7.25000000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xc3, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #7.50000000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc3, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #7.75000000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc4, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #8.00000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc4, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #8.50000000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xc4, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #9.00000000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xc4, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #9.50000000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xc4, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #10.00000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xc4, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #10.50000000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xc4, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #11.00000000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc4, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #11.50000000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc5, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #12.00000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc5, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #12.50000000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xc5, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #13.00000000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xc5, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #13.50000000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xc5, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #14.00000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xc5, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #14.50000000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xc5, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #15.00000000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc5, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #15.50000000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc6, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #16.00000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc6, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #17.00000000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xc6, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #18.00000000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xc6, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #19.00000000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xc6, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #20.00000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xc6, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #21.00000000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xc6, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #22.00000000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc6, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #23.00000000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc7, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #24.00000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc7, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #25.00000000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xc7, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #26.00000000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xc7, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #27.00000000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xc7, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #28.00000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xc7, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #29.00000000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xc7, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #30.00000000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc7, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #31.00000000"
diff --git a/tests/MC/AArch64/SVE/fexpa.s.yaml b/tests/MC/AArch64/SVE/fexpa.s.yaml
new file mode 100644
index 000000000..e1477c814
--- /dev/null
+++ b/tests/MC/AArch64/SVE/fexpa.s.yaml
@@ -0,0 +1,30 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xe0, 0xbb, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fexpa z0.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbb, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fexpa z0.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbb, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fexpa z0.d, z31.d"
diff --git a/tests/MC/AArch64/SVE/fmad.s.yaml b/tests/MC/AArch64/SVE/fmad.s.yaml
new file mode 100644
index 000000000..d28664c43
--- /dev/null
+++ b/tests/MC/AArch64/SVE/fmad.s.yaml
@@ -0,0 +1,140 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x9c, 0x7f, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmad z0.h, p7/m, z1.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x9c, 0xbf, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmad z0.s, p7/m, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x9c, 0xff, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmad z0.d, p7/m, z1.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0.d, p7/z, z7.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x9c, 0xff, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmad z0.d, p7/m, z1.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x20, 0x9c, 0xff, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmad z0.d, p7/m, z1.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x9c, 0x7f, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmad z0.h, p7/m, z1.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x9c, 0xbf, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmad z0.s, p7/m, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x9c, 0xff, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmad z0.d, p7/m, z1.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0.d, p7/z, z7.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x9c, 0xff, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmad z0.d, p7/m, z1.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x20, 0x9c, 0xff, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmad z0.d, p7/m, z1.d, z31.d"
diff --git a/tests/MC/AArch64/SVE/fmax.s.yaml b/tests/MC/AArch64/SVE/fmax.s.yaml
new file mode 100644
index 000000000..68997a329
--- /dev/null
+++ b/tests/MC/AArch64/SVE/fmax.s.yaml
@@ -0,0 +1,360 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x5e, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmax z0.h, p0/m, z0.h, #0.0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x5e, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmax z0.h, p0/m, z0.h, #0.0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x9e, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmax z0.s, p0/m, z0.s, #0.0"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x9c, 0xde, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmax z31.d, p7/m, z31.d, #1.0"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x9c, 0x5e, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmax z31.h, p7/m, z31.h, #1.0"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x9c, 0x9e, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmax z31.s, p7/m, z31.s, #1.0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xde, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmax z0.d, p0/m, z0.d, #0.0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0x46, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmax z0.h, p7/m, z0.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0x86, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmax z0.s, p7/m, z0.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xc6, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmax z0.d, p7/m, z0.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0.d, p0/z, z7.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xde, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmax z0.d, p0/m, z0.d, #0.0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xde, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmax z0.d, p0/m, z0.d, #0.0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0.d, p7/z, z7.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xc6, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmax z0.d, p7/m, z0.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xc6, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmax z0.d, p7/m, z0.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x5e, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmax z0.h, p0/m, z0.h, #0.0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x5e, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmax z0.h, p0/m, z0.h, #0.0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x9e, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmax z0.s, p0/m, z0.s, #0.0"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x9c, 0xde, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmax z31.d, p7/m, z31.d, #1.0"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x9c, 0x5e, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmax z31.h, p7/m, z31.h, #1.0"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x9c, 0x9e, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmax z31.s, p7/m, z31.s, #1.0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xde, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmax z0.d, p0/m, z0.d, #0.0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0x46, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmax z0.h, p7/m, z0.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0x86, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmax z0.s, p7/m, z0.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xc6, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmax z0.d, p7/m, z0.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0.d, p0/z, z7.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xde, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmax z0.d, p0/m, z0.d, #0.0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xde, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmax z0.d, p0/m, z0.d, #0.0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0.d, p7/z, z7.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xc6, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmax z0.d, p7/m, z0.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xc6, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmax z0.d, p7/m, z0.d, z31.d"
diff --git a/tests/MC/AArch64/SVE/fmaxnm.s.yaml b/tests/MC/AArch64/SVE/fmaxnm.s.yaml
new file mode 100644
index 000000000..bd3edffa3
--- /dev/null
+++ b/tests/MC/AArch64/SVE/fmaxnm.s.yaml
@@ -0,0 +1,380 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x5c, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnm z0.h, p0/m, z0.h, #0.0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x5c, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnm z0.h, p0/m, z0.h, #0.0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x9c, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnm z0.s, p0/m, z0.s, #0.0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xdc, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnm z0.d, p0/m, z0.d, #0.0"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x9c, 0x5c, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnm z31.h, p7/m, z31.h, #1.0"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x9c, 0x5c, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnm z31.h, p7/m, z31.h, #1.0"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x9c, 0x9c, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnm z31.s, p7/m, z31.s, #1.0"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x9c, 0xdc, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnm z31.d, p7/m, z31.d, #1.0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0x44, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnm z0.h, p7/m, z0.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0x84, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnm z0.s, p7/m, z0.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xc4, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnm z0.d, p7/m, z0.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31.d, p7/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x9c, 0xdc, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnm z31.d, p7/m, z31.d, #1.0"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x9c, 0xdc, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnm z31.d, p7/m, z31.d, #1.0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0.d, p7/z, z7.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xc4, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnm z0.d, p7/m, z0.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xc4, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnm z0.d, p7/m, z0.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x5c, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnm z0.h, p0/m, z0.h, #0.0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x5c, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnm z0.h, p0/m, z0.h, #0.0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x9c, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnm z0.s, p0/m, z0.s, #0.0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xdc, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnm z0.d, p0/m, z0.d, #0.0"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x9c, 0x5c, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnm z31.h, p7/m, z31.h, #1.0"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x9c, 0x5c, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnm z31.h, p7/m, z31.h, #1.0"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x9c, 0x9c, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnm z31.s, p7/m, z31.s, #1.0"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x9c, 0xdc, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnm z31.d, p7/m, z31.d, #1.0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0x44, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnm z0.h, p7/m, z0.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0x84, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnm z0.s, p7/m, z0.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xc4, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnm z0.d, p7/m, z0.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31.d, p7/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x9c, 0xdc, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnm z31.d, p7/m, z31.d, #1.0"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x9c, 0xdc, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnm z31.d, p7/m, z31.d, #1.0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0.d, p7/z, z7.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xc4, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnm z0.d, p7/m, z0.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xc4, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnm z0.d, p7/m, z0.d, z31.d"
diff --git a/tests/MC/AArch64/SVE/fmaxnmv.s.yaml b/tests/MC/AArch64/SVE/fmaxnmv.s.yaml
new file mode 100644
index 000000000..9780894f0
--- /dev/null
+++ b/tests/MC/AArch64/SVE/fmaxnmv.s.yaml
@@ -0,0 +1,60 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xe0, 0x3f, 0x44, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnmv h0, p7, z31.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3f, 0x84, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnmv s0, p7, z31.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3f, 0xc4, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnmv d0, p7, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3f, 0x44, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnmv h0, p7, z31.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3f, 0x84, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnmv s0, p7, z31.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3f, 0xc4, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnmv d0, p7, z31.d"
diff --git a/tests/MC/AArch64/SVE/fmaxv.s.yaml b/tests/MC/AArch64/SVE/fmaxv.s.yaml
new file mode 100644
index 000000000..4b3777d07
--- /dev/null
+++ b/tests/MC/AArch64/SVE/fmaxv.s.yaml
@@ -0,0 +1,60 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xe0, 0x3f, 0x46, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxv h0, p7, z31.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3f, 0x86, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxv s0, p7, z31.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3f, 0xc6, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxv d0, p7, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3f, 0x46, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxv h0, p7, z31.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3f, 0x86, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxv s0, p7, z31.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3f, 0xc6, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxv d0, p7, z31.d"
diff --git a/tests/MC/AArch64/SVE/fmin.s.yaml b/tests/MC/AArch64/SVE/fmin.s.yaml
new file mode 100644
index 000000000..e24c8d563
--- /dev/null
+++ b/tests/MC/AArch64/SVE/fmin.s.yaml
@@ -0,0 +1,380 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x5f, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmin z0.h, p0/m, z0.h, #0.0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x5f, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmin z0.h, p0/m, z0.h, #0.0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x9f, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmin z0.s, p0/m, z0.s, #0.0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xdf, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmin z0.d, p0/m, z0.d, #0.0"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x9c, 0x5f, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmin z31.h, p7/m, z31.h, #1.0"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x9c, 0x5f, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmin z31.h, p7/m, z31.h, #1.0"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x9c, 0x9f, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmin z31.s, p7/m, z31.s, #1.0"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x9c, 0xdf, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmin z31.d, p7/m, z31.d, #1.0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0x47, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmin z0.h, p7/m, z0.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0x87, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmin z0.s, p7/m, z0.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xc7, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmin z0.d, p7/m, z0.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31.d, p7/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x9c, 0xdf, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmin z31.d, p7/m, z31.d, #1.0"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x9c, 0xdf, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmin z31.d, p7/m, z31.d, #1.0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0.d, p7/z, z7.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xc7, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmin z0.d, p7/m, z0.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xc7, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmin z0.d, p7/m, z0.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x5f, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmin z0.h, p0/m, z0.h, #0.0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x5f, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmin z0.h, p0/m, z0.h, #0.0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x9f, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmin z0.s, p0/m, z0.s, #0.0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xdf, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmin z0.d, p0/m, z0.d, #0.0"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x9c, 0x5f, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmin z31.h, p7/m, z31.h, #1.0"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x9c, 0x5f, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmin z31.h, p7/m, z31.h, #1.0"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x9c, 0x9f, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmin z31.s, p7/m, z31.s, #1.0"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x9c, 0xdf, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmin z31.d, p7/m, z31.d, #1.0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0x47, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmin z0.h, p7/m, z0.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0x87, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmin z0.s, p7/m, z0.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xc7, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmin z0.d, p7/m, z0.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31.d, p7/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x9c, 0xdf, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmin z31.d, p7/m, z31.d, #1.0"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x9c, 0xdf, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmin z31.d, p7/m, z31.d, #1.0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0.d, p7/z, z7.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xc7, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmin z0.d, p7/m, z0.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xc7, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmin z0.d, p7/m, z0.d, z31.d"
diff --git a/tests/MC/AArch64/SVE/fminnm.s.yaml b/tests/MC/AArch64/SVE/fminnm.s.yaml
new file mode 100644
index 000000000..32349e7b6
--- /dev/null
+++ b/tests/MC/AArch64/SVE/fminnm.s.yaml
@@ -0,0 +1,380 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x5d, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnm z0.h, p0/m, z0.h, #0.0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x5d, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnm z0.h, p0/m, z0.h, #0.0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x9d, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnm z0.s, p0/m, z0.s, #0.0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xdd, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnm z0.d, p0/m, z0.d, #0.0"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x9c, 0x5d, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnm z31.h, p7/m, z31.h, #1.0"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x9c, 0x5d, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnm z31.h, p7/m, z31.h, #1.0"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x9c, 0x9d, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnm z31.s, p7/m, z31.s, #1.0"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x9c, 0xdd, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnm z31.d, p7/m, z31.d, #1.0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0x45, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnm z0.h, p7/m, z0.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0x85, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnm z0.s, p7/m, z0.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xc5, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnm z0.d, p7/m, z0.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31.d, p7/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x9c, 0xdd, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnm z31.d, p7/m, z31.d, #1.0"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x9c, 0xdd, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnm z31.d, p7/m, z31.d, #1.0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0.d, p7/z, z7.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xc5, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnm z0.d, p7/m, z0.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xc5, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnm z0.d, p7/m, z0.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x5d, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnm z0.h, p0/m, z0.h, #0.0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x5d, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnm z0.h, p0/m, z0.h, #0.0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x9d, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnm z0.s, p0/m, z0.s, #0.0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xdd, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnm z0.d, p0/m, z0.d, #0.0"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x9c, 0x5d, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnm z31.h, p7/m, z31.h, #1.0"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x9c, 0x5d, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnm z31.h, p7/m, z31.h, #1.0"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x9c, 0x9d, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnm z31.s, p7/m, z31.s, #1.0"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x9c, 0xdd, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnm z31.d, p7/m, z31.d, #1.0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0x45, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnm z0.h, p7/m, z0.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0x85, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnm z0.s, p7/m, z0.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xc5, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnm z0.d, p7/m, z0.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31.d, p7/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x9c, 0xdd, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnm z31.d, p7/m, z31.d, #1.0"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x9c, 0xdd, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnm z31.d, p7/m, z31.d, #1.0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0.d, p7/z, z7.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xc5, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnm z0.d, p7/m, z0.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xc5, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnm z0.d, p7/m, z0.d, z31.d"
diff --git a/tests/MC/AArch64/SVE/fminnmv.s.yaml b/tests/MC/AArch64/SVE/fminnmv.s.yaml
new file mode 100644
index 000000000..4fb08c51d
--- /dev/null
+++ b/tests/MC/AArch64/SVE/fminnmv.s.yaml
@@ -0,0 +1,60 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xe0, 0x3f, 0x45, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnmv h0, p7, z31.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3f, 0x85, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnmv s0, p7, z31.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3f, 0xc5, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnmv d0, p7, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3f, 0x45, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnmv h0, p7, z31.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3f, 0x85, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnmv s0, p7, z31.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3f, 0xc5, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnmv d0, p7, z31.d"
diff --git a/tests/MC/AArch64/SVE/fminv.s.yaml b/tests/MC/AArch64/SVE/fminv.s.yaml
new file mode 100644
index 000000000..926fe4f56
--- /dev/null
+++ b/tests/MC/AArch64/SVE/fminv.s.yaml
@@ -0,0 +1,60 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xe0, 0x3f, 0x47, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminv h0, p7, z31.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3f, 0x87, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminv s0, p7, z31.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3f, 0xc7, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminv d0, p7, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3f, 0x47, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminv h0, p7, z31.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3f, 0x87, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminv s0, p7, z31.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3f, 0xc7, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminv d0, p7, z31.d"
diff --git a/tests/MC/AArch64/SVE/fmla.s.yaml b/tests/MC/AArch64/SVE/fmla.s.yaml
new file mode 100644
index 000000000..cd0fc4f8c
--- /dev/null
+++ b/tests/MC/AArch64/SVE/fmla.s.yaml
@@ -0,0 +1,240 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x1c, 0x7f, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla z0.h, p7/m, z1.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x1c, 0xbf, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla z0.s, p7/m, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x1c, 0xff, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla z0.d, p7/m, z1.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x00, 0x7f, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla z0.h, z1.h, z7.h[7]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x00, 0xbf, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla z0.s, z1.s, z7.s[3]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x00, 0xf7, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla z0.d, z1.d, z7.d[1]"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0.d, p7/z, z7.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x1c, 0xff, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla z0.d, p7/m, z1.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x20, 0x1c, 0xff, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla z0.d, p7/m, z1.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x20, 0x00, 0xf7, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla z0.d, z1.d, z7.d[1]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x1c, 0x7f, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla z0.h, p7/m, z1.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x1c, 0xbf, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla z0.s, p7/m, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x1c, 0xff, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla z0.d, p7/m, z1.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x00, 0x7f, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla z0.h, z1.h, z7.h[7]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x00, 0xbf, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla z0.s, z1.s, z7.s[3]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x00, 0xf7, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla z0.d, z1.d, z7.d[1]"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0.d, p7/z, z7.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x1c, 0xff, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla z0.d, p7/m, z1.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x20, 0x1c, 0xff, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla z0.d, p7/m, z1.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x20, 0x00, 0xf7, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla z0.d, z1.d, z7.d[1]"
diff --git a/tests/MC/AArch64/SVE/fmls.s.yaml b/tests/MC/AArch64/SVE/fmls.s.yaml
new file mode 100644
index 000000000..0982d9663
--- /dev/null
+++ b/tests/MC/AArch64/SVE/fmls.s.yaml
@@ -0,0 +1,240 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x3c, 0x7f, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls z0.h, p7/m, z1.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x3c, 0xbf, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls z0.s, p7/m, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x3c, 0xff, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls z0.d, p7/m, z1.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x04, 0x7f, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls z0.h, z1.h, z7.h[7]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x04, 0xbf, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls z0.s, z1.s, z7.s[3]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x04, 0xf7, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls z0.d, z1.d, z7.d[1]"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0.d, p7/z, z7.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x3c, 0xff, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls z0.d, p7/m, z1.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x20, 0x3c, 0xff, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls z0.d, p7/m, z1.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x20, 0x04, 0xf7, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls z0.d, z1.d, z7.d[1]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x3c, 0x7f, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls z0.h, p7/m, z1.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x3c, 0xbf, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls z0.s, p7/m, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x3c, 0xff, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls z0.d, p7/m, z1.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x04, 0x7f, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls z0.h, z1.h, z7.h[7]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x04, 0xbf, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls z0.s, z1.s, z7.s[3]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x04, 0xf7, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls z0.d, z1.d, z7.d[1]"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0.d, p7/z, z7.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x3c, 0xff, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls z0.d, p7/m, z1.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x20, 0x3c, 0xff, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls z0.d, p7/m, z1.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x20, 0x04, 0xf7, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls z0.d, z1.d, z7.d[1]"
diff --git a/tests/MC/AArch64/SVE/fmov.s.yaml b/tests/MC/AArch64/SVE/fmov.s.yaml
new file mode 100644
index 000000000..e396ad5f6
--- /dev/null
+++ b/tests/MC/AArch64/SVE/fmov.s.yaml
@@ -0,0 +1,5380 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x78, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.h, #0"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0xb8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.s, #0"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0xf8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.d, #0"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd8, 0x79, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.h, #-0.12500000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd8, 0xb9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.s, #-0.12500000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd8, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-0.12500000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc7, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #31.00000000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd8, 0x50, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.h, p0/m, #-0.12500000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd8, 0x90, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.s, p0/m, #-0.12500000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd8, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.12500000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd8, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.13281250"
+
+  -
+    input:
+      bytes: [ 0x40, 0xd8, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.14062500"
+
+  -
+    input:
+      bytes: [ 0x60, 0xd8, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.14843750"
+
+  -
+    input:
+      bytes: [ 0x80, 0xd8, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.15625000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xd8, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.16406250"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xd8, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.17187500"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xd8, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.17968750"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd9, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.18750000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd9, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.19531250"
+
+  -
+    input:
+      bytes: [ 0x40, 0xd9, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.20312500"
+
+  -
+    input:
+      bytes: [ 0x60, 0xd9, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.21093750"
+
+  -
+    input:
+      bytes: [ 0x80, 0xd9, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.21875000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xd9, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.22656250"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xd9, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.23437500"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xd9, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.24218750"
+
+  -
+    input:
+      bytes: [ 0x00, 0xda, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.25000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xda, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.26562500"
+
+  -
+    input:
+      bytes: [ 0x40, 0xda, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.28125000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xda, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.29687500"
+
+  -
+    input:
+      bytes: [ 0x80, 0xda, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.31250000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xda, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.32812500"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xda, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.34375000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xda, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.35937500"
+
+  -
+    input:
+      bytes: [ 0x00, 0xdb, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.37500000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xdb, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.39062500"
+
+  -
+    input:
+      bytes: [ 0x40, 0xdb, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.40625000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xdb, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.42187500"
+
+  -
+    input:
+      bytes: [ 0x80, 0xdb, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.43750000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xdb, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.45312500"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xdb, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.46875000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xdb, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.48437500"
+
+  -
+    input:
+      bytes: [ 0x00, 0xdc, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.50000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xdc, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.53125000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xdc, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.56250000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xdc, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.59375000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xdc, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.62500000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xdc, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.65625000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xdc, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.68750000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xdc, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.71875000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xdd, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.75000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xdd, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.78125000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xdd, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.81250000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xdd, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.84375000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xdd, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.87500000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xdd, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.90625000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xdd, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.93750000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xdd, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.96875000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xde, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-1.00000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xde, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-1.06250000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xde, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-1.12500000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xde, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-1.18750000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xde, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-1.25000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xde, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-1.31250000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xde, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-1.37500000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xde, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-1.43750000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xdf, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-1.50000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xdf, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-1.56250000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xdf, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-1.62500000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xdf, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-1.68750000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xdf, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-1.75000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xdf, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-1.81250000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xdf, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-1.87500000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xdf, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-1.93750000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd0, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-2.00000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd0, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-2.12500000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xd0, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-2.25000000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xd0, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-2.37500000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xd0, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-2.50000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xd0, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-2.62500000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xd0, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-2.75000000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xd0, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-2.87500000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd1, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-3.00000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd1, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-3.12500000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xd1, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-3.25000000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xd1, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-3.37500000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xd1, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-3.50000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xd1, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-3.62500000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xd1, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-3.75000000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xd1, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-3.87500000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd2, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-4.00000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd2, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-4.25000000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xd2, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-4.50000000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xd2, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-4.75000000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xd2, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-5.00000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xd2, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-5.25000000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xd2, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-5.50000000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xd2, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-5.75000000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd3, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-6.00000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd3, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-6.25000000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xd3, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-6.50000000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xd3, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-6.75000000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xd3, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-7.00000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xd3, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-7.25000000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xd3, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-7.50000000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xd3, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-7.75000000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd4, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-8.00000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd4, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-8.50000000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xd4, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-9.00000000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xd4, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-9.50000000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xd4, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-10.00000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xd4, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-10.50000000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xd4, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-11.00000000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xd4, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-11.50000000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd5, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-12.00000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd5, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-12.50000000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xd5, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-13.00000000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xd5, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-13.50000000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xd5, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-14.00000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xd5, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-14.50000000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xd5, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-15.00000000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xd5, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-15.50000000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd6, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-16.00000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd6, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-17.00000000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xd6, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-18.00000000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xd6, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-19.00000000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xd6, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-20.00000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xd6, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-21.00000000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xd6, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-22.00000000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xd6, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-23.00000000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd7, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-24.00000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd7, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-25.00000000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xd7, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-26.00000000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xd7, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-27.00000000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xd7, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-28.00000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xd7, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-29.00000000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xd7, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-30.00000000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xd7, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-31.00000000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc8, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.12500000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc8, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.13281250"
+
+  -
+    input:
+      bytes: [ 0x40, 0xc8, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.14062500"
+
+  -
+    input:
+      bytes: [ 0x60, 0xc8, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.14843750"
+
+  -
+    input:
+      bytes: [ 0x80, 0xc8, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.15625000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xc8, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.16406250"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xc8, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.17187500"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc8, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.17968750"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc9, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.18750000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc9, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.19531250"
+
+  -
+    input:
+      bytes: [ 0x40, 0xc9, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.20312500"
+
+  -
+    input:
+      bytes: [ 0x60, 0xc9, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.21093750"
+
+  -
+    input:
+      bytes: [ 0x80, 0xc9, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.21875000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xc9, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.22656250"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xc9, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.23437500"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc9, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.24218750"
+
+  -
+    input:
+      bytes: [ 0x00, 0xca, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.25000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xca, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.26562500"
+
+  -
+    input:
+      bytes: [ 0x40, 0xca, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.28125000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xca, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.29687500"
+
+  -
+    input:
+      bytes: [ 0x80, 0xca, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.31250000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xca, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.32812500"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xca, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.34375000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xca, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.35937500"
+
+  -
+    input:
+      bytes: [ 0x00, 0xcb, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.37500000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xcb, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.39062500"
+
+  -
+    input:
+      bytes: [ 0x40, 0xcb, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.40625000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xcb, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.42187500"
+
+  -
+    input:
+      bytes: [ 0x80, 0xcb, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.43750000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xcb, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.45312500"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xcb, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.46875000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xcb, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.48437500"
+
+  -
+    input:
+      bytes: [ 0x00, 0xcc, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.50000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xcc, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.53125000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xcc, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.56250000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xcc, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.59375000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xcc, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.62500000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xcc, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.65625000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xcc, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.68750000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xcc, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.71875000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xcd, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.75000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xcd, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.78125000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xcd, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.81250000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xcd, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.84375000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xcd, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.87500000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xcd, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.90625000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xcd, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.93750000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xcd, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.96875000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xce, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #1.00000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xce, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #1.06250000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xce, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #1.12500000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xce, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #1.18750000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xce, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #1.25000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xce, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #1.31250000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xce, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #1.37500000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xce, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #1.43750000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xcf, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #1.50000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xcf, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #1.56250000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xcf, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #1.62500000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xcf, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #1.68750000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xcf, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #1.75000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xcf, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #1.81250000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xcf, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #1.87500000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xcf, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #1.93750000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #2.00000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc0, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #2.12500000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xc0, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #2.25000000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xc0, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #2.37500000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xc0, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #2.50000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xc0, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #2.62500000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xc0, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #2.75000000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc0, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #2.87500000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc1, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #3.00000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc1, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #3.12500000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xc1, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #3.25000000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xc1, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #3.37500000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xc1, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #3.50000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xc1, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #3.62500000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xc1, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #3.75000000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc1, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #3.87500000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc2, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #4.00000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc2, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #4.25000000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xc2, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #4.50000000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xc2, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #4.75000000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xc2, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #5.00000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xc2, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #5.25000000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xc2, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #5.50000000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc2, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #5.75000000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc3, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #6.00000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc3, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #6.25000000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xc3, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #6.50000000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xc3, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #6.75000000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xc3, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #7.00000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xc3, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #7.25000000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xc3, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #7.50000000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc3, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #7.75000000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc4, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #8.00000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc4, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #8.50000000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xc4, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #9.00000000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xc4, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #9.50000000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xc4, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #10.00000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xc4, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #10.50000000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xc4, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #11.00000000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc4, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #11.50000000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc5, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #12.00000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc5, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #12.50000000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xc5, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #13.00000000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xc5, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #13.50000000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xc5, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #14.00000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xc5, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #14.50000000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xc5, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #15.00000000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc5, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #15.50000000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc6, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #16.00000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc6, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #17.00000000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xc6, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #18.00000000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xc6, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #19.00000000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xc6, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #20.00000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xc6, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #21.00000000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xc6, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #22.00000000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc6, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #23.00000000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc7, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #24.00000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc7, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #25.00000000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xc7, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #26.00000000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xc7, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #27.00000000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xc7, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #28.00000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xc7, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #29.00000000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xc7, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #30.00000000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc7, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #31.00000000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0.d, p0/z, z7.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc7, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #31.00000000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc7, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #31.00000000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x78, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.h, #0"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0xb8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.s, #0"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0xf8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.d, #0"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd8, 0x79, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.h, #-0.12500000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd8, 0xb9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.s, #-0.12500000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd8, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #-0.12500000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc7, 0xf9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, #31.00000000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd8, 0x50, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.h, p0/m, #-0.12500000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd8, 0x90, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.s, p0/m, #-0.12500000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd8, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.12500000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd8, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.13281250"
+
+  -
+    input:
+      bytes: [ 0x40, 0xd8, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.14062500"
+
+  -
+    input:
+      bytes: [ 0x60, 0xd8, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.14843750"
+
+  -
+    input:
+      bytes: [ 0x80, 0xd8, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.15625000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xd8, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.16406250"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xd8, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.17187500"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xd8, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.17968750"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd9, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.18750000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd9, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.19531250"
+
+  -
+    input:
+      bytes: [ 0x40, 0xd9, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.20312500"
+
+  -
+    input:
+      bytes: [ 0x60, 0xd9, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.21093750"
+
+  -
+    input:
+      bytes: [ 0x80, 0xd9, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.21875000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xd9, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.22656250"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xd9, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.23437500"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xd9, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.24218750"
+
+  -
+    input:
+      bytes: [ 0x00, 0xda, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.25000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xda, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.26562500"
+
+  -
+    input:
+      bytes: [ 0x40, 0xda, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.28125000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xda, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.29687500"
+
+  -
+    input:
+      bytes: [ 0x80, 0xda, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.31250000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xda, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.32812500"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xda, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.34375000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xda, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.35937500"
+
+  -
+    input:
+      bytes: [ 0x00, 0xdb, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.37500000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xdb, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.39062500"
+
+  -
+    input:
+      bytes: [ 0x40, 0xdb, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.40625000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xdb, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.42187500"
+
+  -
+    input:
+      bytes: [ 0x80, 0xdb, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.43750000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xdb, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.45312500"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xdb, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.46875000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xdb, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.48437500"
+
+  -
+    input:
+      bytes: [ 0x00, 0xdc, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.50000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xdc, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.53125000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xdc, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.56250000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xdc, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.59375000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xdc, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.62500000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xdc, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.65625000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xdc, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.68750000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xdc, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.71875000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xdd, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.75000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xdd, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.78125000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xdd, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.81250000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xdd, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.84375000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xdd, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.87500000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xdd, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.90625000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xdd, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.93750000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xdd, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-0.96875000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xde, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-1.00000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xde, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-1.06250000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xde, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-1.12500000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xde, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-1.18750000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xde, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-1.25000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xde, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-1.31250000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xde, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-1.37500000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xde, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-1.43750000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xdf, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-1.50000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xdf, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-1.56250000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xdf, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-1.62500000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xdf, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-1.68750000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xdf, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-1.75000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xdf, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-1.81250000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xdf, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-1.87500000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xdf, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-1.93750000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd0, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-2.00000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd0, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-2.12500000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xd0, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-2.25000000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xd0, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-2.37500000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xd0, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-2.50000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xd0, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-2.62500000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xd0, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-2.75000000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xd0, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-2.87500000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd1, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-3.00000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd1, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-3.12500000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xd1, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-3.25000000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xd1, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-3.37500000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xd1, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-3.50000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xd1, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-3.62500000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xd1, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-3.75000000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xd1, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-3.87500000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd2, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-4.00000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd2, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-4.25000000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xd2, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-4.50000000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xd2, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-4.75000000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xd2, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-5.00000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xd2, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-5.25000000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xd2, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-5.50000000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xd2, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-5.75000000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd3, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-6.00000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd3, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-6.25000000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xd3, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-6.50000000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xd3, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-6.75000000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xd3, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-7.00000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xd3, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-7.25000000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xd3, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-7.50000000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xd3, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-7.75000000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd4, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-8.00000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd4, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-8.50000000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xd4, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-9.00000000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xd4, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-9.50000000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xd4, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-10.00000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xd4, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-10.50000000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xd4, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-11.00000000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xd4, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-11.50000000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd5, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-12.00000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd5, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-12.50000000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xd5, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-13.00000000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xd5, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-13.50000000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xd5, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-14.00000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xd5, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-14.50000000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xd5, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-15.00000000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xd5, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-15.50000000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd6, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-16.00000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd6, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-17.00000000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xd6, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-18.00000000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xd6, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-19.00000000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xd6, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-20.00000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xd6, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-21.00000000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xd6, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-22.00000000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xd6, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-23.00000000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd7, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-24.00000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd7, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-25.00000000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xd7, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-26.00000000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xd7, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-27.00000000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xd7, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-28.00000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xd7, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-29.00000000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xd7, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-30.00000000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xd7, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #-31.00000000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc8, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.12500000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc8, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.13281250"
+
+  -
+    input:
+      bytes: [ 0x40, 0xc8, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.14062500"
+
+  -
+    input:
+      bytes: [ 0x60, 0xc8, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.14843750"
+
+  -
+    input:
+      bytes: [ 0x80, 0xc8, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.15625000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xc8, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.16406250"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xc8, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.17187500"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc8, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.17968750"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc9, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.18750000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc9, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.19531250"
+
+  -
+    input:
+      bytes: [ 0x40, 0xc9, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.20312500"
+
+  -
+    input:
+      bytes: [ 0x60, 0xc9, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.21093750"
+
+  -
+    input:
+      bytes: [ 0x80, 0xc9, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.21875000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xc9, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.22656250"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xc9, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.23437500"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc9, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.24218750"
+
+  -
+    input:
+      bytes: [ 0x00, 0xca, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.25000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xca, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.26562500"
+
+  -
+    input:
+      bytes: [ 0x40, 0xca, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.28125000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xca, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.29687500"
+
+  -
+    input:
+      bytes: [ 0x80, 0xca, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.31250000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xca, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.32812500"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xca, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.34375000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xca, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.35937500"
+
+  -
+    input:
+      bytes: [ 0x00, 0xcb, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.37500000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xcb, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.39062500"
+
+  -
+    input:
+      bytes: [ 0x40, 0xcb, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.40625000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xcb, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.42187500"
+
+  -
+    input:
+      bytes: [ 0x80, 0xcb, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.43750000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xcb, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.45312500"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xcb, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.46875000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xcb, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.48437500"
+
+  -
+    input:
+      bytes: [ 0x00, 0xcc, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.50000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xcc, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.53125000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xcc, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.56250000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xcc, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.59375000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xcc, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.62500000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xcc, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.65625000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xcc, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.68750000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xcc, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.71875000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xcd, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.75000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xcd, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.78125000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xcd, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.81250000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xcd, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.84375000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xcd, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.87500000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xcd, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.90625000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xcd, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.93750000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xcd, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #0.96875000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xce, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #1.00000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xce, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #1.06250000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xce, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #1.12500000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xce, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #1.18750000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xce, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #1.25000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xce, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #1.31250000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xce, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #1.37500000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xce, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #1.43750000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xcf, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #1.50000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xcf, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #1.56250000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xcf, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #1.62500000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xcf, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #1.68750000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xcf, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #1.75000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xcf, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #1.81250000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xcf, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #1.87500000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xcf, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #1.93750000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #2.00000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc0, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #2.12500000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xc0, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #2.25000000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xc0, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #2.37500000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xc0, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #2.50000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xc0, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #2.62500000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xc0, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #2.75000000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc0, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #2.87500000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc1, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #3.00000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc1, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #3.12500000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xc1, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #3.25000000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xc1, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #3.37500000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xc1, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #3.50000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xc1, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #3.62500000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xc1, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #3.75000000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc1, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #3.87500000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc2, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #4.00000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc2, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #4.25000000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xc2, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #4.50000000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xc2, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #4.75000000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xc2, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #5.00000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xc2, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #5.25000000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xc2, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #5.50000000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc2, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #5.75000000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc3, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #6.00000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc3, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #6.25000000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xc3, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #6.50000000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xc3, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #6.75000000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xc3, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #7.00000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xc3, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #7.25000000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xc3, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #7.50000000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc3, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #7.75000000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc4, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #8.00000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc4, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #8.50000000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xc4, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #9.00000000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xc4, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #9.50000000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xc4, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #10.00000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xc4, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #10.50000000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xc4, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #11.00000000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc4, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #11.50000000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc5, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #12.00000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc5, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #12.50000000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xc5, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #13.00000000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xc5, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #13.50000000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xc5, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #14.00000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xc5, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #14.50000000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xc5, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #15.00000000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc5, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #15.50000000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc6, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #16.00000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc6, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #17.00000000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xc6, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #18.00000000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xc6, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #19.00000000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xc6, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #20.00000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xc6, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #21.00000000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xc6, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #22.00000000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc6, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #23.00000000"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc7, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #24.00000000"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc7, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #25.00000000"
+
+  -
+    input:
+      bytes: [ 0x40, 0xc7, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #26.00000000"
+
+  -
+    input:
+      bytes: [ 0x60, 0xc7, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #27.00000000"
+
+  -
+    input:
+      bytes: [ 0x80, 0xc7, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #28.00000000"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xc7, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #29.00000000"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xc7, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #30.00000000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc7, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #31.00000000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0.d, p0/z, z7.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc7, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #31.00000000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc7, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov z0.d, p0/m, #31.00000000"
diff --git a/tests/MC/AArch64/SVE/fmsb.s.yaml b/tests/MC/AArch64/SVE/fmsb.s.yaml
new file mode 100644
index 000000000..6232522df
--- /dev/null
+++ b/tests/MC/AArch64/SVE/fmsb.s.yaml
@@ -0,0 +1,140 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0xbc, 0x7f, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmsb z0.h, p7/m, z1.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0xbc, 0xbf, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmsb z0.s, p7/m, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0xbc, 0xff, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmsb z0.d, p7/m, z1.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0.d, p7/z, z7.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0xbc, 0xff, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmsb z0.d, p7/m, z1.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x20, 0xbc, 0xff, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmsb z0.d, p7/m, z1.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0xbc, 0x7f, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmsb z0.h, p7/m, z1.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0xbc, 0xbf, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmsb z0.s, p7/m, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0xbc, 0xff, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmsb z0.d, p7/m, z1.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0.d, p7/z, z7.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0xbc, 0xff, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmsb z0.d, p7/m, z1.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x20, 0xbc, 0xff, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmsb z0.d, p7/m, z1.d, z31.d"
diff --git a/tests/MC/AArch64/SVE/fmul.s.yaml b/tests/MC/AArch64/SVE/fmul.s.yaml
new file mode 100644
index 000000000..8eb012dd2
--- /dev/null
+++ b/tests/MC/AArch64/SVE/fmul.s.yaml
@@ -0,0 +1,540 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x5a, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmul z0.h, p0/m, z0.h, #0.5"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x5a, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmul z0.h, p0/m, z0.h, #0.5"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x9a, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmul z0.s, p0/m, z0.s, #0.5"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xda, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmul z0.d, p0/m, z0.d, #0.5"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x9c, 0x5a, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmul z31.h, p7/m, z31.h, #2.0"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x9c, 0x9a, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmul z31.s, p7/m, z31.s, #2.0"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x9c, 0xda, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmul z31.d, p7/m, z31.d, #2.0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x20, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmul z0.h, z0.h, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0xa0, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmul z0.s, z0.s, z0.s[0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0xe0, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmul z0.d, z0.d, z0.d[0]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x23, 0x7f, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmul z31.h, z31.h, z7.h[7]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x23, 0xbf, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmul z31.s, z31.s, z7.s[3]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x23, 0xff, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmul z31.d, z31.d, z15.d[1]"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0x42, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmul z0.h, p7/m, z0.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0x82, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmul z0.s, p7/m, z0.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xc2, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmul z0.d, p7/m, z0.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x08, 0x5f, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmul z0.h, z1.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x08, 0x9f, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmul z0.s, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x08, 0xdf, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmul z0.d, z1.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31.d, p7/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x9c, 0xda, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmul z31.d, p7/m, z31.d, #2.0"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x9c, 0xda, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmul z31.d, p7/m, z31.d, #2.0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0.d, p7/z, z7.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xc2, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmul z0.d, p7/m, z0.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xc2, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmul z0.d, p7/m, z0.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x5a, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmul z0.h, p0/m, z0.h, #0.5"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x5a, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmul z0.h, p0/m, z0.h, #0.5"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x9a, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmul z0.s, p0/m, z0.s, #0.5"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xda, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmul z0.d, p0/m, z0.d, #0.5"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x9c, 0x5a, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmul z31.h, p7/m, z31.h, #2.0"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x9c, 0x9a, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmul z31.s, p7/m, z31.s, #2.0"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x9c, 0xda, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmul z31.d, p7/m, z31.d, #2.0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x20, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmul z0.h, z0.h, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0xa0, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmul z0.s, z0.s, z0.s[0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0xe0, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmul z0.d, z0.d, z0.d[0]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x23, 0x7f, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmul z31.h, z31.h, z7.h[7]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x23, 0xbf, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmul z31.s, z31.s, z7.s[3]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x23, 0xff, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmul z31.d, z31.d, z15.d[1]"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0x42, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmul z0.h, p7/m, z0.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0x82, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmul z0.s, p7/m, z0.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xc2, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmul z0.d, p7/m, z0.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x08, 0x5f, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmul z0.h, z1.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x08, 0x9f, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmul z0.s, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x08, 0xdf, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmul z0.d, z1.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31.d, p7/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x9c, 0xda, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmul z31.d, p7/m, z31.d, #2.0"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x9c, 0xda, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmul z31.d, p7/m, z31.d, #2.0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0.d, p7/z, z7.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xc2, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmul z0.d, p7/m, z0.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xc2, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmul z0.d, p7/m, z0.d, z31.d"
diff --git a/tests/MC/AArch64/SVE/fmulx.s.yaml b/tests/MC/AArch64/SVE/fmulx.s.yaml
new file mode 100644
index 000000000..dc8b03652
--- /dev/null
+++ b/tests/MC/AArch64/SVE/fmulx.s.yaml
@@ -0,0 +1,140 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0x4a, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmulx z0.h, p7/m, z0.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0x8a, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmulx z0.s, p7/m, z0.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xca, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmulx z0.d, p7/m, z0.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0.d, p7/z, z7.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xca, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmulx z0.d, p7/m, z0.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xca, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmulx z0.d, p7/m, z0.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0x4a, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmulx z0.h, p7/m, z0.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0x8a, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmulx z0.s, p7/m, z0.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xca, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmulx z0.d, p7/m, z0.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0.d, p7/z, z7.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xca, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmulx z0.d, p7/m, z0.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xca, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmulx z0.d, p7/m, z0.d, z31.d"
diff --git a/tests/MC/AArch64/SVE/fneg.s.yaml b/tests/MC/AArch64/SVE/fneg.s.yaml
new file mode 100644
index 000000000..e2544a24e
--- /dev/null
+++ b/tests/MC/AArch64/SVE/fneg.s.yaml
@@ -0,0 +1,140 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x5d, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fneg z31.h, p7/m, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x9d, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fneg z31.s, p7/m, z31.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0xdd, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fneg z31.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4.d, p7/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xbf, 0xdd, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fneg z4.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4, z6"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xbf, 0xdd, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fneg z4.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x5d, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fneg z31.h, p7/m, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x9d, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fneg z31.s, p7/m, z31.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0xdd, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fneg z31.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4.d, p7/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xbf, 0xdd, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fneg z4.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4, z6"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xbf, 0xdd, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fneg z4.d, p7/m, z31.d"
diff --git a/tests/MC/AArch64/SVE/fnmad.s.yaml b/tests/MC/AArch64/SVE/fnmad.s.yaml
new file mode 100644
index 000000000..ce71c91ca
--- /dev/null
+++ b/tests/MC/AArch64/SVE/fnmad.s.yaml
@@ -0,0 +1,140 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0xdc, 0x7f, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fnmad z0.h, p7/m, z1.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0xdc, 0xbf, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fnmad z0.s, p7/m, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0xdc, 0xff, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fnmad z0.d, p7/m, z1.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0.d, p7/z, z7.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0xdc, 0xff, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fnmad z0.d, p7/m, z1.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x20, 0xdc, 0xff, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fnmad z0.d, p7/m, z1.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0xdc, 0x7f, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fnmad z0.h, p7/m, z1.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0xdc, 0xbf, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fnmad z0.s, p7/m, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0xdc, 0xff, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fnmad z0.d, p7/m, z1.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0.d, p7/z, z7.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0xdc, 0xff, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fnmad z0.d, p7/m, z1.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x20, 0xdc, 0xff, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fnmad z0.d, p7/m, z1.d, z31.d"
diff --git a/tests/MC/AArch64/SVE/fnmla.s.yaml b/tests/MC/AArch64/SVE/fnmla.s.yaml
new file mode 100644
index 000000000..302eb2fd0
--- /dev/null
+++ b/tests/MC/AArch64/SVE/fnmla.s.yaml
@@ -0,0 +1,140 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x5c, 0x7f, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fnmla z0.h, p7/m, z1.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x5c, 0xbf, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fnmla z0.s, p7/m, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x5c, 0xff, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fnmla z0.d, p7/m, z1.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0.d, p7/z, z7.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x5c, 0xff, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fnmla z0.d, p7/m, z1.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x20, 0x5c, 0xff, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fnmla z0.d, p7/m, z1.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x5c, 0x7f, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fnmla z0.h, p7/m, z1.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x5c, 0xbf, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fnmla z0.s, p7/m, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x5c, 0xff, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fnmla z0.d, p7/m, z1.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0.d, p7/z, z7.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x5c, 0xff, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fnmla z0.d, p7/m, z1.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x20, 0x5c, 0xff, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fnmla z0.d, p7/m, z1.d, z31.d"
diff --git a/tests/MC/AArch64/SVE/fnmls.s.yaml b/tests/MC/AArch64/SVE/fnmls.s.yaml
new file mode 100644
index 000000000..ffbbc6391
--- /dev/null
+++ b/tests/MC/AArch64/SVE/fnmls.s.yaml
@@ -0,0 +1,140 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x7c, 0x7f, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fnmls z0.h, p7/m, z1.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x7c, 0xbf, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fnmls z0.s, p7/m, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x7c, 0xff, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fnmls z0.d, p7/m, z1.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0.d, p7/z, z7.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x7c, 0xff, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fnmls z0.d, p7/m, z1.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x20, 0x7c, 0xff, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fnmls z0.d, p7/m, z1.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x7c, 0x7f, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fnmls z0.h, p7/m, z1.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x7c, 0xbf, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fnmls z0.s, p7/m, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x7c, 0xff, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fnmls z0.d, p7/m, z1.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0.d, p7/z, z7.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x7c, 0xff, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fnmls z0.d, p7/m, z1.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x20, 0x7c, 0xff, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fnmls z0.d, p7/m, z1.d, z31.d"
diff --git a/tests/MC/AArch64/SVE/fnmsb.s.yaml b/tests/MC/AArch64/SVE/fnmsb.s.yaml
new file mode 100644
index 000000000..9ec87bd97
--- /dev/null
+++ b/tests/MC/AArch64/SVE/fnmsb.s.yaml
@@ -0,0 +1,140 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0xfc, 0x7f, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fnmsb z0.h, p7/m, z1.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0xfc, 0xbf, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fnmsb z0.s, p7/m, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0xfc, 0xff, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fnmsb z0.d, p7/m, z1.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0.d, p7/z, z7.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0xfc, 0xff, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fnmsb z0.d, p7/m, z1.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x20, 0xfc, 0xff, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fnmsb z0.d, p7/m, z1.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0xfc, 0x7f, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fnmsb z0.h, p7/m, z1.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0xfc, 0xbf, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fnmsb z0.s, p7/m, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0xfc, 0xff, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fnmsb z0.d, p7/m, z1.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0.d, p7/z, z7.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0xfc, 0xff, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fnmsb z0.d, p7/m, z1.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x20, 0xfc, 0xff, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fnmsb z0.d, p7/m, z1.d, z31.d"
diff --git a/tests/MC/AArch64/SVE/frecpe.s.yaml b/tests/MC/AArch64/SVE/frecpe.s.yaml
new file mode 100644
index 000000000..fdf4124fa
--- /dev/null
+++ b/tests/MC/AArch64/SVE/frecpe.s.yaml
@@ -0,0 +1,60 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xe0, 0x33, 0x4e, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "frecpe z0.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x33, 0x8e, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "frecpe z0.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x33, 0xce, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "frecpe z0.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x33, 0x4e, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "frecpe z0.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x33, 0x8e, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "frecpe z0.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x33, 0xce, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "frecpe z0.d, z31.d"
diff --git a/tests/MC/AArch64/SVE/frecps.s.yaml b/tests/MC/AArch64/SVE/frecps.s.yaml
new file mode 100644
index 000000000..5f55d1e3b
--- /dev/null
+++ b/tests/MC/AArch64/SVE/frecps.s.yaml
@@ -0,0 +1,60 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x18, 0x5f, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "frecps z0.h, z1.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x18, 0x9f, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "frecps z0.s, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x18, 0xdf, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "frecps z0.d, z1.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x18, 0x5f, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "frecps z0.h, z1.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x18, 0x9f, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "frecps z0.s, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x18, 0xdf, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "frecps z0.d, z1.d, z31.d"
diff --git a/tests/MC/AArch64/SVE/frecpx.s.yaml b/tests/MC/AArch64/SVE/frecpx.s.yaml
new file mode 100644
index 000000000..44b19f816
--- /dev/null
+++ b/tests/MC/AArch64/SVE/frecpx.s.yaml
@@ -0,0 +1,140 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x4c, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "frecpx z31.h, p7/m, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x8c, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "frecpx z31.s, p7/m, z31.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0xcc, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "frecpx z31.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4.d, p7/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xbf, 0xcc, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "frecpx z4.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4, z6"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xbf, 0xcc, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "frecpx z4.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x4c, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "frecpx z31.h, p7/m, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x8c, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "frecpx z31.s, p7/m, z31.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0xcc, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "frecpx z31.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4.d, p7/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xbf, 0xcc, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "frecpx z4.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4, z6"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xbf, 0xcc, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "frecpx z4.d, p7/m, z31.d"
diff --git a/tests/MC/AArch64/SVE/frinta.s.yaml b/tests/MC/AArch64/SVE/frinta.s.yaml
new file mode 100644
index 000000000..9a59fabd1
--- /dev/null
+++ b/tests/MC/AArch64/SVE/frinta.s.yaml
@@ -0,0 +1,140 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x44, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "frinta z31.h, p7/m, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x84, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "frinta z31.s, p7/m, z31.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0xc4, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "frinta z31.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4.d, p7/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xbf, 0xc4, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "frinta z4.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4, z6"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xbf, 0xc4, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "frinta z4.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x44, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "frinta z31.h, p7/m, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x84, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "frinta z31.s, p7/m, z31.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0xc4, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "frinta z31.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4.d, p7/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xbf, 0xc4, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "frinta z4.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4, z6"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xbf, 0xc4, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "frinta z4.d, p7/m, z31.d"
diff --git a/tests/MC/AArch64/SVE/frinti.s.yaml b/tests/MC/AArch64/SVE/frinti.s.yaml
new file mode 100644
index 000000000..ada70be26
--- /dev/null
+++ b/tests/MC/AArch64/SVE/frinti.s.yaml
@@ -0,0 +1,140 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x47, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "frinti z31.h, p7/m, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x87, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "frinti z31.s, p7/m, z31.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0xc7, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "frinti z31.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4.d, p7/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xbf, 0xc7, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "frinti z4.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4, z6"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xbf, 0xc7, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "frinti z4.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x47, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "frinti z31.h, p7/m, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x87, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "frinti z31.s, p7/m, z31.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0xc7, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "frinti z31.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4.d, p7/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xbf, 0xc7, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "frinti z4.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4, z6"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xbf, 0xc7, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "frinti z4.d, p7/m, z31.d"
diff --git a/tests/MC/AArch64/SVE/frintm.s.yaml b/tests/MC/AArch64/SVE/frintm.s.yaml
new file mode 100644
index 000000000..79af7c0b1
--- /dev/null
+++ b/tests/MC/AArch64/SVE/frintm.s.yaml
@@ -0,0 +1,140 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x42, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "frintm z31.h, p7/m, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x82, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "frintm z31.s, p7/m, z31.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0xc2, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "frintm z31.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4.d, p7/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xbf, 0xc2, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "frintm z4.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4, z6"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xbf, 0xc2, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "frintm z4.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x42, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "frintm z31.h, p7/m, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x82, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "frintm z31.s, p7/m, z31.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0xc2, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "frintm z31.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4.d, p7/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xbf, 0xc2, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "frintm z4.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4, z6"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xbf, 0xc2, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "frintm z4.d, p7/m, z31.d"
diff --git a/tests/MC/AArch64/SVE/frintn.s.yaml b/tests/MC/AArch64/SVE/frintn.s.yaml
new file mode 100644
index 000000000..01107f179
--- /dev/null
+++ b/tests/MC/AArch64/SVE/frintn.s.yaml
@@ -0,0 +1,140 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x40, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "frintn z31.h, p7/m, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x80, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "frintn z31.s, p7/m, z31.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0xc0, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "frintn z31.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4.d, p7/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xbf, 0xc0, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "frintn z4.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4, z6"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xbf, 0xc0, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "frintn z4.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x40, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "frintn z31.h, p7/m, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x80, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "frintn z31.s, p7/m, z31.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0xc0, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "frintn z31.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4.d, p7/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xbf, 0xc0, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "frintn z4.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4, z6"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xbf, 0xc0, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "frintn z4.d, p7/m, z31.d"
diff --git a/tests/MC/AArch64/SVE/frintp.s.yaml b/tests/MC/AArch64/SVE/frintp.s.yaml
new file mode 100644
index 000000000..11f725b24
--- /dev/null
+++ b/tests/MC/AArch64/SVE/frintp.s.yaml
@@ -0,0 +1,140 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x41, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "frintp z31.h, p7/m, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x81, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "frintp z31.s, p7/m, z31.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0xc1, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "frintp z31.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4.d, p7/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xbf, 0xc1, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "frintp z4.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4, z6"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xbf, 0xc1, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "frintp z4.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x41, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "frintp z31.h, p7/m, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x81, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "frintp z31.s, p7/m, z31.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0xc1, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "frintp z31.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4.d, p7/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xbf, 0xc1, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "frintp z4.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4, z6"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xbf, 0xc1, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "frintp z4.d, p7/m, z31.d"
diff --git a/tests/MC/AArch64/SVE/frintx.s.yaml b/tests/MC/AArch64/SVE/frintx.s.yaml
new file mode 100644
index 000000000..aa0822791
--- /dev/null
+++ b/tests/MC/AArch64/SVE/frintx.s.yaml
@@ -0,0 +1,140 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x46, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "frintx z31.h, p7/m, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x86, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "frintx z31.s, p7/m, z31.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0xc6, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "frintx z31.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4.d, p7/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xbf, 0xc6, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "frintx z4.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4, z6"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xbf, 0xc6, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "frintx z4.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x46, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "frintx z31.h, p7/m, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x86, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "frintx z31.s, p7/m, z31.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0xc6, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "frintx z31.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4.d, p7/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xbf, 0xc6, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "frintx z4.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4, z6"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xbf, 0xc6, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "frintx z4.d, p7/m, z31.d"
diff --git a/tests/MC/AArch64/SVE/frintz.s.yaml b/tests/MC/AArch64/SVE/frintz.s.yaml
new file mode 100644
index 000000000..111787b72
--- /dev/null
+++ b/tests/MC/AArch64/SVE/frintz.s.yaml
@@ -0,0 +1,140 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x43, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "frintz z31.h, p7/m, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x83, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "frintz z31.s, p7/m, z31.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0xc3, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "frintz z31.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4.d, p7/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xbf, 0xc3, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "frintz z4.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4, z6"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xbf, 0xc3, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "frintz z4.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x43, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "frintz z31.h, p7/m, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x83, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "frintz z31.s, p7/m, z31.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0xc3, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "frintz z31.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4.d, p7/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xbf, 0xc3, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "frintz z4.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4, z6"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xbf, 0xc3, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "frintz z4.d, p7/m, z31.d"
diff --git a/tests/MC/AArch64/SVE/frsqrte.s.yaml b/tests/MC/AArch64/SVE/frsqrte.s.yaml
new file mode 100644
index 000000000..3ce84b3b8
--- /dev/null
+++ b/tests/MC/AArch64/SVE/frsqrte.s.yaml
@@ -0,0 +1,60 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xe0, 0x33, 0x4f, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "frsqrte z0.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x33, 0x8f, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "frsqrte z0.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x33, 0xcf, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "frsqrte z0.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x33, 0x4f, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "frsqrte z0.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x33, 0x8f, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "frsqrte z0.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x33, 0xcf, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "frsqrte z0.d, z31.d"
diff --git a/tests/MC/AArch64/SVE/frsqrts.s.yaml b/tests/MC/AArch64/SVE/frsqrts.s.yaml
new file mode 100644
index 000000000..5e697b092
--- /dev/null
+++ b/tests/MC/AArch64/SVE/frsqrts.s.yaml
@@ -0,0 +1,60 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x1c, 0x5f, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "frsqrts z0.h, z1.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x1c, 0x9f, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "frsqrts z0.s, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x1c, 0xdf, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "frsqrts z0.d, z1.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x1c, 0x5f, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "frsqrts z0.h, z1.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x1c, 0x9f, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "frsqrts z0.s, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x1c, 0xdf, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "frsqrts z0.d, z1.d, z31.d"
diff --git a/tests/MC/AArch64/SVE/fscale.s.yaml b/tests/MC/AArch64/SVE/fscale.s.yaml
new file mode 100644
index 000000000..7f8a8d563
--- /dev/null
+++ b/tests/MC/AArch64/SVE/fscale.s.yaml
@@ -0,0 +1,140 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0x49, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fscale z0.h, p7/m, z0.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0x89, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fscale z0.s, p7/m, z0.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xc9, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fscale z0.d, p7/m, z0.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0.d, p7/z, z7.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xc9, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fscale z0.d, p7/m, z0.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xc9, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fscale z0.d, p7/m, z0.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0x49, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fscale z0.h, p7/m, z0.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0x89, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fscale z0.s, p7/m, z0.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xc9, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fscale z0.d, p7/m, z0.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0.d, p7/z, z7.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xc9, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fscale z0.d, p7/m, z0.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xc9, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fscale z0.d, p7/m, z0.d, z31.d"
diff --git a/tests/MC/AArch64/SVE/fsqrt.s.yaml b/tests/MC/AArch64/SVE/fsqrt.s.yaml
new file mode 100644
index 000000000..846098c83
--- /dev/null
+++ b/tests/MC/AArch64/SVE/fsqrt.s.yaml
@@ -0,0 +1,140 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x4d, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsqrt z31.h, p7/m, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x8d, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsqrt z31.s, p7/m, z31.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0xcd, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsqrt z31.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4.d, p7/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xbf, 0xcd, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsqrt z4.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4, z6"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xbf, 0xcd, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsqrt z4.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x4d, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsqrt z31.h, p7/m, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x8d, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsqrt z31.s, p7/m, z31.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0xcd, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsqrt z31.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4.d, p7/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xbf, 0xcd, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsqrt z4.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4, z6"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xbf, 0xcd, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsqrt z4.d, p7/m, z31.d"
diff --git a/tests/MC/AArch64/SVE/fsub.s.yaml b/tests/MC/AArch64/SVE/fsub.s.yaml
new file mode 100644
index 000000000..60ea3f018
--- /dev/null
+++ b/tests/MC/AArch64/SVE/fsub.s.yaml
@@ -0,0 +1,440 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x59, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub z0.h, p0/m, z0.h, #0.5"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x59, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub z0.h, p0/m, z0.h, #0.5"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x99, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub z0.s, p0/m, z0.s, #0.5"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xd9, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub z0.d, p0/m, z0.d, #0.5"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x9c, 0x59, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub z31.h, p7/m, z31.h, #1.0"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x9c, 0x59, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub z31.h, p7/m, z31.h, #1.0"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x9c, 0x99, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub z31.s, p7/m, z31.s, #1.0"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x9c, 0xd9, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub z31.d, p7/m, z31.d, #1.0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0x41, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub z0.h, p7/m, z0.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0x81, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub z0.s, p7/m, z0.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xc1, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub z0.d, p7/m, z0.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x04, 0x5f, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub z0.h, z1.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x04, 0x9f, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub z0.s, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x04, 0xdf, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub z0.d, z1.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31.d, p7/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x9c, 0xd9, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub z31.d, p7/m, z31.d, #1.0"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x9c, 0xd9, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub z31.d, p7/m, z31.d, #1.0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0.d, p7/z, z7.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xc1, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub z0.d, p7/m, z0.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xc1, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub z0.d, p7/m, z0.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x59, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub z0.h, p0/m, z0.h, #0.5"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x59, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub z0.h, p0/m, z0.h, #0.5"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x99, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub z0.s, p0/m, z0.s, #0.5"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xd9, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub z0.d, p0/m, z0.d, #0.5"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x9c, 0x59, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub z31.h, p7/m, z31.h, #1.0"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x9c, 0x59, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub z31.h, p7/m, z31.h, #1.0"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x9c, 0x99, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub z31.s, p7/m, z31.s, #1.0"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x9c, 0xd9, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub z31.d, p7/m, z31.d, #1.0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0x41, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub z0.h, p7/m, z0.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0x81, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub z0.s, p7/m, z0.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xc1, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub z0.d, p7/m, z0.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x04, 0x5f, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub z0.h, z1.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x04, 0x9f, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub z0.s, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x04, 0xdf, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub z0.d, z1.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31.d, p7/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x9c, 0xd9, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub z31.d, p7/m, z31.d, #1.0"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x9c, 0xd9, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub z31.d, p7/m, z31.d, #1.0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0.d, p7/z, z7.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xc1, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub z0.d, p7/m, z0.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xc1, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub z0.d, p7/m, z0.d, z31.d"
diff --git a/tests/MC/AArch64/SVE/fsubr.s.yaml b/tests/MC/AArch64/SVE/fsubr.s.yaml
new file mode 100644
index 000000000..9d2636d4d
--- /dev/null
+++ b/tests/MC/AArch64/SVE/fsubr.s.yaml
@@ -0,0 +1,380 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x5b, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsubr z0.h, p0/m, z0.h, #0.5"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x5b, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsubr z0.h, p0/m, z0.h, #0.5"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x9b, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsubr z0.s, p0/m, z0.s, #0.5"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xdb, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsubr z0.d, p0/m, z0.d, #0.5"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x9c, 0x5b, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsubr z31.h, p7/m, z31.h, #1.0"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x9c, 0x5b, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsubr z31.h, p7/m, z31.h, #1.0"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x9c, 0x9b, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsubr z31.s, p7/m, z31.s, #1.0"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x9c, 0xdb, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsubr z31.d, p7/m, z31.d, #1.0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0x43, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsubr z0.h, p7/m, z0.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0x83, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsubr z0.s, p7/m, z0.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xc3, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsubr z0.d, p7/m, z0.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31.d, p7/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x9c, 0xdb, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsubr z31.d, p7/m, z31.d, #1.0"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x9c, 0xdb, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsubr z31.d, p7/m, z31.d, #1.0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0.d, p7/z, z7.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xc3, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsubr z0.d, p7/m, z0.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xc3, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsubr z0.d, p7/m, z0.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x5b, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsubr z0.h, p0/m, z0.h, #0.5"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x5b, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsubr z0.h, p0/m, z0.h, #0.5"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x9b, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsubr z0.s, p0/m, z0.s, #0.5"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xdb, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsubr z0.d, p0/m, z0.d, #0.5"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x9c, 0x5b, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsubr z31.h, p7/m, z31.h, #1.0"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x9c, 0x5b, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsubr z31.h, p7/m, z31.h, #1.0"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x9c, 0x9b, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsubr z31.s, p7/m, z31.s, #1.0"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x9c, 0xdb, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsubr z31.d, p7/m, z31.d, #1.0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0x43, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsubr z0.h, p7/m, z0.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0x83, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsubr z0.s, p7/m, z0.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xc3, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsubr z0.d, p7/m, z0.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31.d, p7/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x9c, 0xdb, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsubr z31.d, p7/m, z31.d, #1.0"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x9c, 0xdb, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsubr z31.d, p7/m, z31.d, #1.0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0.d, p7/z, z7.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xc3, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsubr z0.d, p7/m, z0.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xc3, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsubr z0.d, p7/m, z0.d, z31.d"
diff --git a/tests/MC/AArch64/SVE/ftmad.s.yaml b/tests/MC/AArch64/SVE/ftmad.s.yaml
new file mode 100644
index 000000000..5b9c74afe
--- /dev/null
+++ b/tests/MC/AArch64/SVE/ftmad.s.yaml
@@ -0,0 +1,50 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xe0, 0x83, 0x57, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ftmad z0.h, z0.h, z31.h, #7"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x83, 0x97, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ftmad z0.s, z0.s, z31.s, #7"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x83, 0xd7, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ftmad z0.d, z0.d, z31.d, #7"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x83, 0xd7, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ftmad z0.d, z0.d, z31.d, #7"
diff --git a/tests/MC/AArch64/SVE/ftsmul.s.yaml b/tests/MC/AArch64/SVE/ftsmul.s.yaml
new file mode 100644
index 000000000..27545c04b
--- /dev/null
+++ b/tests/MC/AArch64/SVE/ftsmul.s.yaml
@@ -0,0 +1,30 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x0c, 0x5f, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ftsmul z0.h, z1.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x0c, 0x9f, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ftsmul z0.s, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x0c, 0xdf, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ftsmul z0.d, z1.d, z31.d"
diff --git a/tests/MC/AArch64/SVE/ftssel.s.yaml b/tests/MC/AArch64/SVE/ftssel.s.yaml
new file mode 100644
index 000000000..767039ba8
--- /dev/null
+++ b/tests/MC/AArch64/SVE/ftssel.s.yaml
@@ -0,0 +1,30 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0xb0, 0x7f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ftssel z0.h, z1.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0xb0, 0xbf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ftssel z0.s, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0xb0, 0xff, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ftssel z0.d, z1.d, z31.d"
diff --git a/tests/MC/AArch64/SVE/incb.s.yaml b/tests/MC/AArch64/SVE/incb.s.yaml
new file mode 100644
index 000000000..fee45fb9a
--- /dev/null
+++ b/tests/MC/AArch64/SVE/incb.s.yaml
@@ -0,0 +1,660 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xe0, 0xe3, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "incb x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xe3, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "incb x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xe3, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "incb x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xe3, 0x3f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "incb x0, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "incb x0, pow2"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe0, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "incb x0, vl1"
+
+  -
+    input:
+      bytes: [ 0x40, 0xe0, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "incb x0, vl2"
+
+  -
+    input:
+      bytes: [ 0x60, 0xe0, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "incb x0, vl3"
+
+  -
+    input:
+      bytes: [ 0x80, 0xe0, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "incb x0, vl4"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xe0, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "incb x0, vl5"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xe0, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "incb x0, vl6"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xe0, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "incb x0, vl7"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe1, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "incb x0, vl8"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe1, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "incb x0, vl16"
+
+  -
+    input:
+      bytes: [ 0x40, 0xe1, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "incb x0, vl32"
+
+  -
+    input:
+      bytes: [ 0x60, 0xe1, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "incb x0, vl64"
+
+  -
+    input:
+      bytes: [ 0x80, 0xe1, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "incb x0, vl128"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xe1, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "incb x0, vl256"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xe1, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "incb x0, #14"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xe1, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "incb x0, #15"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe2, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "incb x0, #16"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe2, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "incb x0, #17"
+
+  -
+    input:
+      bytes: [ 0x40, 0xe2, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "incb x0, #18"
+
+  -
+    input:
+      bytes: [ 0x60, 0xe2, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "incb x0, #19"
+
+  -
+    input:
+      bytes: [ 0x80, 0xe2, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "incb x0, #20"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xe2, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "incb x0, #21"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xe2, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "incb x0, #22"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xe2, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "incb x0, #23"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe3, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "incb x0, #24"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe3, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "incb x0, #25"
+
+  -
+    input:
+      bytes: [ 0x40, 0xe3, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "incb x0, #26"
+
+  -
+    input:
+      bytes: [ 0x60, 0xe3, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "incb x0, #27"
+
+  -
+    input:
+      bytes: [ 0x80, 0xe3, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "incb x0, #28"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xe3, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "incb x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xe3, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "incb x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xe3, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "incb x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xe3, 0x3f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "incb x0, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "incb x0, pow2"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe0, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "incb x0, vl1"
+
+  -
+    input:
+      bytes: [ 0x40, 0xe0, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "incb x0, vl2"
+
+  -
+    input:
+      bytes: [ 0x60, 0xe0, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "incb x0, vl3"
+
+  -
+    input:
+      bytes: [ 0x80, 0xe0, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "incb x0, vl4"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xe0, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "incb x0, vl5"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xe0, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "incb x0, vl6"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xe0, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "incb x0, vl7"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe1, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "incb x0, vl8"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe1, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "incb x0, vl16"
+
+  -
+    input:
+      bytes: [ 0x40, 0xe1, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "incb x0, vl32"
+
+  -
+    input:
+      bytes: [ 0x60, 0xe1, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "incb x0, vl64"
+
+  -
+    input:
+      bytes: [ 0x80, 0xe1, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "incb x0, vl128"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xe1, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "incb x0, vl256"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xe1, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "incb x0, #14"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xe1, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "incb x0, #15"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe2, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "incb x0, #16"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe2, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "incb x0, #17"
+
+  -
+    input:
+      bytes: [ 0x40, 0xe2, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "incb x0, #18"
+
+  -
+    input:
+      bytes: [ 0x60, 0xe2, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "incb x0, #19"
+
+  -
+    input:
+      bytes: [ 0x80, 0xe2, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "incb x0, #20"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xe2, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "incb x0, #21"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xe2, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "incb x0, #22"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xe2, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "incb x0, #23"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe3, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "incb x0, #24"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe3, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "incb x0, #25"
+
+  -
+    input:
+      bytes: [ 0x40, 0xe3, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "incb x0, #26"
+
+  -
+    input:
+      bytes: [ 0x60, 0xe3, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "incb x0, #27"
+
+  -
+    input:
+      bytes: [ 0x80, 0xe3, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "incb x0, #28"
diff --git a/tests/MC/AArch64/SVE/incd.s.yaml b/tests/MC/AArch64/SVE/incd.s.yaml
new file mode 100644
index 000000000..9645847a0
--- /dev/null
+++ b/tests/MC/AArch64/SVE/incd.s.yaml
@@ -0,0 +1,600 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xe0, 0xc3, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "incd z0.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc3, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "incd z0.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc3, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "incd z0.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc3, 0xff, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "incd z0.d, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xe3, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "incd x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xe3, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "incd x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xe3, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "incd x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xe3, 0xff, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "incd x0, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "incd x0, pow2"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe0, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "incd x0, vl1"
+
+  -
+    input:
+      bytes: [ 0x40, 0xe0, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "incd x0, vl2"
+
+  -
+    input:
+      bytes: [ 0x60, 0xe0, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "incd x0, vl3"
+
+  -
+    input:
+      bytes: [ 0x80, 0xe0, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "incd x0, vl4"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xe0, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "incd x0, vl5"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xe0, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "incd x0, vl6"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xe0, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "incd x0, vl7"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe1, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "incd x0, vl8"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe1, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "incd x0, vl16"
+
+  -
+    input:
+      bytes: [ 0x40, 0xe1, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "incd x0, vl32"
+
+  -
+    input:
+      bytes: [ 0x60, 0xe1, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "incd x0, vl64"
+
+  -
+    input:
+      bytes: [ 0x80, 0xe1, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "incd x0, vl128"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xe1, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "incd x0, vl256"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xe1, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "incd x0, #14"
+
+  -
+    input:
+      bytes: [ 0x80, 0xe3, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "incd x0, #28"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc3, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "incd z0.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc3, 0xff, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "incd z0.d, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc3, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "incd z0.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc3, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "incd z0.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc3, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "incd z0.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc3, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "incd z0.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc3, 0xff, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "incd z0.d, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xe3, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "incd x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xe3, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "incd x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xe3, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "incd x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xe3, 0xff, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "incd x0, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "incd x0, pow2"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe0, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "incd x0, vl1"
+
+  -
+    input:
+      bytes: [ 0x40, 0xe0, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "incd x0, vl2"
+
+  -
+    input:
+      bytes: [ 0x60, 0xe0, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "incd x0, vl3"
+
+  -
+    input:
+      bytes: [ 0x80, 0xe0, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "incd x0, vl4"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xe0, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "incd x0, vl5"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xe0, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "incd x0, vl6"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xe0, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "incd x0, vl7"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe1, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "incd x0, vl8"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe1, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "incd x0, vl16"
+
+  -
+    input:
+      bytes: [ 0x40, 0xe1, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "incd x0, vl32"
+
+  -
+    input:
+      bytes: [ 0x60, 0xe1, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "incd x0, vl64"
+
+  -
+    input:
+      bytes: [ 0x80, 0xe1, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "incd x0, vl128"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xe1, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "incd x0, vl256"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xe1, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "incd x0, #14"
+
+  -
+    input:
+      bytes: [ 0x80, 0xe3, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "incd x0, #28"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc3, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "incd z0.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc3, 0xff, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "incd z0.d, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc3, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "incd z0.d"
diff --git a/tests/MC/AArch64/SVE/inch.s.yaml b/tests/MC/AArch64/SVE/inch.s.yaml
new file mode 100644
index 000000000..a5b87e350
--- /dev/null
+++ b/tests/MC/AArch64/SVE/inch.s.yaml
@@ -0,0 +1,600 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xe0, 0xc3, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "inch z0.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc3, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "inch z0.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc3, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "inch z0.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc3, 0x7f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "inch z0.h, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xe3, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "inch x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xe3, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "inch x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xe3, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "inch x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xe3, 0x7f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "inch x0, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "inch x0, pow2"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe0, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "inch x0, vl1"
+
+  -
+    input:
+      bytes: [ 0x40, 0xe0, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "inch x0, vl2"
+
+  -
+    input:
+      bytes: [ 0x60, 0xe0, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "inch x0, vl3"
+
+  -
+    input:
+      bytes: [ 0x80, 0xe0, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "inch x0, vl4"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xe0, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "inch x0, vl5"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xe0, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "inch x0, vl6"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xe0, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "inch x0, vl7"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe1, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "inch x0, vl8"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe1, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "inch x0, vl16"
+
+  -
+    input:
+      bytes: [ 0x40, 0xe1, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "inch x0, vl32"
+
+  -
+    input:
+      bytes: [ 0x60, 0xe1, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "inch x0, vl64"
+
+  -
+    input:
+      bytes: [ 0x80, 0xe1, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "inch x0, vl128"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xe1, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "inch x0, vl256"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xe1, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "inch x0, #14"
+
+  -
+    input:
+      bytes: [ 0x80, 0xe3, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "inch x0, #28"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc3, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "inch z0.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc3, 0x7f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "inch z0.h, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc3, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "inch z0.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc3, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "inch z0.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc3, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "inch z0.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc3, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "inch z0.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc3, 0x7f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "inch z0.h, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xe3, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "inch x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xe3, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "inch x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xe3, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "inch x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xe3, 0x7f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "inch x0, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "inch x0, pow2"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe0, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "inch x0, vl1"
+
+  -
+    input:
+      bytes: [ 0x40, 0xe0, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "inch x0, vl2"
+
+  -
+    input:
+      bytes: [ 0x60, 0xe0, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "inch x0, vl3"
+
+  -
+    input:
+      bytes: [ 0x80, 0xe0, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "inch x0, vl4"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xe0, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "inch x0, vl5"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xe0, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "inch x0, vl6"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xe0, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "inch x0, vl7"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe1, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "inch x0, vl8"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe1, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "inch x0, vl16"
+
+  -
+    input:
+      bytes: [ 0x40, 0xe1, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "inch x0, vl32"
+
+  -
+    input:
+      bytes: [ 0x60, 0xe1, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "inch x0, vl64"
+
+  -
+    input:
+      bytes: [ 0x80, 0xe1, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "inch x0, vl128"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xe1, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "inch x0, vl256"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xe1, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "inch x0, #14"
+
+  -
+    input:
+      bytes: [ 0x80, 0xe3, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "inch x0, #28"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc3, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "inch z0.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc3, 0x7f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "inch z0.h, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc3, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "inch z0.h"
diff --git a/tests/MC/AArch64/SVE/incp.s.yaml b/tests/MC/AArch64/SVE/incp.s.yaml
new file mode 100644
index 000000000..d2823f8db
--- /dev/null
+++ b/tests/MC/AArch64/SVE/incp.s.yaml
@@ -0,0 +1,320 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x88, 0x2c, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "incp x0, p0.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x88, 0x6c, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "incp x0, p0.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x88, 0xac, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "incp x0, p0.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0x88, 0xec, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "incp x0, p0.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0x89, 0x2c, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "incp xzr, p15.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x89, 0x6c, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "incp xzr, p15.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x89, 0xac, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "incp xzr, p15.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0x89, 0xec, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "incp xzr, p15.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0x81, 0x6c, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "incp z31.h, p15.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x81, 0x6c, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "incp z31.h, p15.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x81, 0xac, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "incp z31.s, p15.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0x81, 0xac, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "incp z31.s, p15.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0x81, 0xec, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "incp z31.d, p15.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0x81, 0xec, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "incp z31.d, p15.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xff, 0x81, 0xec, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "incp z31.d, p15.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x88, 0x2c, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "incp x0, p0.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x88, 0x6c, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "incp x0, p0.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x88, 0xac, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "incp x0, p0.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0x88, 0xec, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "incp x0, p0.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0x89, 0x2c, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "incp xzr, p15.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x89, 0x6c, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "incp xzr, p15.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x89, 0xac, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "incp xzr, p15.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0x89, 0xec, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "incp xzr, p15.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0x81, 0x6c, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "incp z31.h, p15.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x81, 0x6c, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "incp z31.h, p15.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x81, 0xac, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "incp z31.s, p15.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0x81, 0xac, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "incp z31.s, p15.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0x81, 0xec, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "incp z31.d, p15.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0x81, 0xec, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "incp z31.d, p15.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xff, 0x81, 0xec, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "incp z31.d, p15.d"
diff --git a/tests/MC/AArch64/SVE/incw.s.yaml b/tests/MC/AArch64/SVE/incw.s.yaml
new file mode 100644
index 000000000..db47d9966
--- /dev/null
+++ b/tests/MC/AArch64/SVE/incw.s.yaml
@@ -0,0 +1,600 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xe0, 0xc3, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "incw z0.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc3, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "incw z0.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc3, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "incw z0.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc3, 0xbf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "incw z0.s, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xe3, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "incw x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xe3, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "incw x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xe3, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "incw x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xe3, 0xbf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "incw x0, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "incw x0, pow2"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe0, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "incw x0, vl1"
+
+  -
+    input:
+      bytes: [ 0x40, 0xe0, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "incw x0, vl2"
+
+  -
+    input:
+      bytes: [ 0x60, 0xe0, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "incw x0, vl3"
+
+  -
+    input:
+      bytes: [ 0x80, 0xe0, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "incw x0, vl4"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xe0, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "incw x0, vl5"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xe0, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "incw x0, vl6"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xe0, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "incw x0, vl7"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe1, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "incw x0, vl8"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe1, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "incw x0, vl16"
+
+  -
+    input:
+      bytes: [ 0x40, 0xe1, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "incw x0, vl32"
+
+  -
+    input:
+      bytes: [ 0x60, 0xe1, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "incw x0, vl64"
+
+  -
+    input:
+      bytes: [ 0x80, 0xe1, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "incw x0, vl128"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xe1, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "incw x0, vl256"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xe1, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "incw x0, #14"
+
+  -
+    input:
+      bytes: [ 0x80, 0xe3, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "incw x0, #28"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc3, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "incw z0.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc3, 0xbf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "incw z0.s, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc3, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "incw z0.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc3, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "incw z0.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc3, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "incw z0.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc3, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "incw z0.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc3, 0xbf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "incw z0.s, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xe3, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "incw x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xe3, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "incw x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xe3, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "incw x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xe3, 0xbf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "incw x0, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "incw x0, pow2"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe0, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "incw x0, vl1"
+
+  -
+    input:
+      bytes: [ 0x40, 0xe0, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "incw x0, vl2"
+
+  -
+    input:
+      bytes: [ 0x60, 0xe0, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "incw x0, vl3"
+
+  -
+    input:
+      bytes: [ 0x80, 0xe0, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "incw x0, vl4"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xe0, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "incw x0, vl5"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xe0, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "incw x0, vl6"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xe0, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "incw x0, vl7"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe1, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "incw x0, vl8"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe1, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "incw x0, vl16"
+
+  -
+    input:
+      bytes: [ 0x40, 0xe1, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "incw x0, vl32"
+
+  -
+    input:
+      bytes: [ 0x60, 0xe1, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "incw x0, vl64"
+
+  -
+    input:
+      bytes: [ 0x80, 0xe1, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "incw x0, vl128"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xe1, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "incw x0, vl256"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xe1, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "incw x0, #14"
+
+  -
+    input:
+      bytes: [ 0x80, 0xe3, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "incw x0, #28"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc3, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "incw z0.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc3, 0xbf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "incw z0.s, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc3, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "incw z0.s"
diff --git a/tests/MC/AArch64/SVE/index.s.yaml b/tests/MC/AArch64/SVE/index.s.yaml
new file mode 100644
index 000000000..503e55273
--- /dev/null
+++ b/tests/MC/AArch64/SVE/index.s.yaml
@@ -0,0 +1,640 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "index z0.b, #0, #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0x43, 0x3f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "index z31.b, #-1, #-1"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "index z0.h, #0, #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0x43, 0x7f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "index z31.h, #-1, #-1"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "index z0.s, #0, #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0x43, 0xbf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "index z31.s, #-1, #-1"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "index z0.d, #0, #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0x43, 0xff, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "index z31.d, #-1, #-1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x4b, 0x3f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "index z31.b, #-1, wzr"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x49, 0x28, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "index z23.b, #13, w8"
+
+  -
+    input:
+      bytes: [ 0xff, 0x4b, 0x7f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "index z31.h, #-1, wzr"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x49, 0x68, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "index z23.h, #13, w8"
+
+  -
+    input:
+      bytes: [ 0xff, 0x4b, 0xbf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "index z31.s, #-1, wzr"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x49, 0xa8, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "index z23.s, #13, w8"
+
+  -
+    input:
+      bytes: [ 0xff, 0x4b, 0xff, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "index z31.d, #-1, xzr"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x49, 0xe8, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "index z23.d, #13, x8"
+
+  -
+    input:
+      bytes: [ 0xff, 0x47, 0x3f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "index z31.b, wzr, #-1"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x45, 0x28, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "index z23.b, w13, #8"
+
+  -
+    input:
+      bytes: [ 0xff, 0x47, 0x7f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "index z31.h, wzr, #-1"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x45, 0x68, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "index z23.h, w13, #8"
+
+  -
+    input:
+      bytes: [ 0xff, 0x47, 0xbf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "index z31.s, wzr, #-1"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x45, 0xa8, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "index z23.s, w13, #8"
+
+  -
+    input:
+      bytes: [ 0xff, 0x47, 0xff, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "index z31.d, xzr, #-1"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x45, 0xe8, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "index z23.d, x13, #8"
+
+  -
+    input:
+      bytes: [ 0xff, 0x4f, 0x3f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "index z31.b, wzr, wzr"
+
+  -
+    input:
+      bytes: [ 0x55, 0x4d, 0x35, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "index z21.b, w10, w21"
+
+  -
+    input:
+      bytes: [ 0xff, 0x4f, 0x7f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "index z31.h, wzr, wzr"
+
+  -
+    input:
+      bytes: [ 0x00, 0x4c, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "index z0.h, w0, w0"
+
+  -
+    input:
+      bytes: [ 0xff, 0x4f, 0xbf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "index z31.s, wzr, wzr"
+
+  -
+    input:
+      bytes: [ 0x55, 0x4d, 0xb5, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "index z21.s, w10, w21"
+
+  -
+    input:
+      bytes: [ 0xff, 0x4f, 0xff, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "index z31.d, xzr, xzr"
+
+  -
+    input:
+      bytes: [ 0x55, 0x4d, 0xf5, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "index z21.d, x10, x21"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "index z0.b, #0, #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0x43, 0x3f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "index z31.b, #-1, #-1"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "index z0.h, #0, #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0x43, 0x7f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "index z31.h, #-1, #-1"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "index z0.s, #0, #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0x43, 0xbf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "index z31.s, #-1, #-1"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "index z0.d, #0, #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0x43, 0xff, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "index z31.d, #-1, #-1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x4b, 0x3f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "index z31.b, #-1, wzr"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x49, 0x28, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "index z23.b, #13, w8"
+
+  -
+    input:
+      bytes: [ 0xff, 0x4b, 0x7f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "index z31.h, #-1, wzr"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x49, 0x68, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "index z23.h, #13, w8"
+
+  -
+    input:
+      bytes: [ 0xff, 0x4b, 0xbf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "index z31.s, #-1, wzr"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x49, 0xa8, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "index z23.s, #13, w8"
+
+  -
+    input:
+      bytes: [ 0xff, 0x4b, 0xff, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "index z31.d, #-1, xzr"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x49, 0xe8, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "index z23.d, #13, x8"
+
+  -
+    input:
+      bytes: [ 0xff, 0x47, 0x3f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "index z31.b, wzr, #-1"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x45, 0x28, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "index z23.b, w13, #8"
+
+  -
+    input:
+      bytes: [ 0xff, 0x47, 0x7f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "index z31.h, wzr, #-1"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x45, 0x68, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "index z23.h, w13, #8"
+
+  -
+    input:
+      bytes: [ 0xff, 0x47, 0xbf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "index z31.s, wzr, #-1"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x45, 0xa8, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "index z23.s, w13, #8"
+
+  -
+    input:
+      bytes: [ 0xff, 0x47, 0xff, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "index z31.d, xzr, #-1"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x45, 0xe8, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "index z23.d, x13, #8"
+
+  -
+    input:
+      bytes: [ 0xff, 0x4f, 0x3f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "index z31.b, wzr, wzr"
+
+  -
+    input:
+      bytes: [ 0x55, 0x4d, 0x35, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "index z21.b, w10, w21"
+
+  -
+    input:
+      bytes: [ 0xff, 0x4f, 0x7f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "index z31.h, wzr, wzr"
+
+  -
+    input:
+      bytes: [ 0x00, 0x4c, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "index z0.h, w0, w0"
+
+  -
+    input:
+      bytes: [ 0xff, 0x4f, 0xbf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "index z31.s, wzr, wzr"
+
+  -
+    input:
+      bytes: [ 0x55, 0x4d, 0xb5, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "index z21.s, w10, w21"
+
+  -
+    input:
+      bytes: [ 0xff, 0x4f, 0xff, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "index z31.d, xzr, xzr"
+
+  -
+    input:
+      bytes: [ 0x55, 0x4d, 0xf5, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "index z21.d, x10, x21"
diff --git a/tests/MC/AArch64/SVE/insr.s.yaml b/tests/MC/AArch64/SVE/insr.s.yaml
new file mode 100644
index 000000000..06fa3c4b5
--- /dev/null
+++ b/tests/MC/AArch64/SVE/insr.s.yaml
@@ -0,0 +1,320 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x38, 0x24, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "insr z0.b, w0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x38, 0x64, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "insr z0.h, w0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x38, 0xa4, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "insr z0.s, w0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x38, 0xe4, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "insr z0.d, x0"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3b, 0x24, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "insr z31.b, wzr"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3b, 0x64, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "insr z31.h, wzr"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3b, 0xa4, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "insr z31.s, wzr"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3b, 0xe4, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "insr z31.d, xzr"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3b, 0x34, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "insr z31.b, b31"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3b, 0x74, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "insr z31.h, h31"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3b, 0xb4, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "insr z31.s, s31"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3b, 0xf4, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "insr z31.d, d31"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3b, 0xe4, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "insr z31.d, xzr"
+
+  -
+    input:
+      bytes: [ 0xc4, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4, z6"
+
+  -
+    input:
+      bytes: [ 0xe4, 0x3b, 0xf4, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "insr z4.d, d31"
+
+  -
+    input:
+      bytes: [ 0x00, 0x38, 0x24, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "insr z0.b, w0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x38, 0x64, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "insr z0.h, w0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x38, 0xa4, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "insr z0.s, w0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x38, 0xe4, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "insr z0.d, x0"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3b, 0x24, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "insr z31.b, wzr"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3b, 0x64, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "insr z31.h, wzr"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3b, 0xa4, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "insr z31.s, wzr"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3b, 0xe4, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "insr z31.d, xzr"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3b, 0x34, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "insr z31.b, b31"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3b, 0x74, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "insr z31.h, h31"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3b, 0xb4, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "insr z31.s, s31"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3b, 0xf4, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "insr z31.d, d31"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3b, 0xe4, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "insr z31.d, xzr"
+
+  -
+    input:
+      bytes: [ 0xc4, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4, z6"
+
+  -
+    input:
+      bytes: [ 0xe4, 0x3b, 0xf4, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "insr z4.d, d31"
diff --git a/tests/MC/AArch64/SVE/lasta.s.yaml b/tests/MC/AArch64/SVE/lasta.s.yaml
new file mode 100644
index 000000000..e8d154686
--- /dev/null
+++ b/tests/MC/AArch64/SVE/lasta.s.yaml
@@ -0,0 +1,160 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xe0, 0xbf, 0x20, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "lasta w0, p7, z31.b"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbf, 0x60, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "lasta w0, p7, z31.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbf, 0xa0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "lasta w0, p7, z31.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbf, 0xe0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "lasta x0, p7, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0x22, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "lasta b0, p7, z31.b"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0x62, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "lasta h0, p7, z31.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xa2, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "lasta s0, p7, z31.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xe2, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "lasta d0, p7, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbf, 0x20, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "lasta w0, p7, z31.b"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbf, 0x60, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "lasta w0, p7, z31.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbf, 0xa0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "lasta w0, p7, z31.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbf, 0xe0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "lasta x0, p7, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0x22, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "lasta b0, p7, z31.b"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0x62, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "lasta h0, p7, z31.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xa2, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "lasta s0, p7, z31.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xe2, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "lasta d0, p7, z31.d"
diff --git a/tests/MC/AArch64/SVE/lastb.s.yaml b/tests/MC/AArch64/SVE/lastb.s.yaml
new file mode 100644
index 000000000..7f2f0afd2
--- /dev/null
+++ b/tests/MC/AArch64/SVE/lastb.s.yaml
@@ -0,0 +1,160 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xe0, 0xbf, 0x21, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "lastb w0, p7, z31.b"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbf, 0x61, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "lastb w0, p7, z31.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbf, 0xa1, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "lastb w0, p7, z31.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbf, 0xe1, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "lastb x0, p7, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0x23, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "lastb b0, p7, z31.b"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0x63, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "lastb h0, p7, z31.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xa3, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "lastb s0, p7, z31.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xe3, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "lastb d0, p7, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbf, 0x21, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "lastb w0, p7, z31.b"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbf, 0x61, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "lastb w0, p7, z31.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbf, 0xa1, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "lastb w0, p7, z31.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbf, 0xe1, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "lastb x0, p7, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0x23, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "lastb b0, p7, z31.b"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0x63, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "lastb h0, p7, z31.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xa3, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "lastb s0, p7, z31.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xe3, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "lastb d0, p7, z31.d"
diff --git a/tests/MC/AArch64/SVE/ld1b-sve-only.s.yaml b/tests/MC/AArch64/SVE/ld1b-sve-only.s.yaml
new file mode 100644
index 000000000..bbb93a96f
--- /dev/null
+++ b/tests/MC/AArch64/SVE/ld1b-sve-only.s.yaml
@@ -0,0 +1,90 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0x00, 0x84 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b { z0.s }, p0/z, [x0, z0.s, uxtw]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0x40, 0x84 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b { z0.s }, p0/z, [x0, z0.s, sxtw]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xdf, 0x5f, 0xc4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b { z31.d }, p7/z, [sp, z31.d]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x55, 0x15, 0xc4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b { z21.d }, p5/z, [x10, z21.d, uxtw]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x55, 0x55, 0xc4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b { z21.d }, p5/z, [x10, z21.d, sxtw]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xdf, 0x3f, 0x84 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b { z31.s }, p7/z, [z31.s, #31]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x20, 0x84 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b { z0.s }, p0/z, [z0.s]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xdf, 0x3f, 0xc4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b { z31.d }, p7/z, [z31.d, #31]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x20, 0xc4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b { z0.d }, p0/z, [z0.d]"
diff --git a/tests/MC/AArch64/SVE/ld1b.s.yaml b/tests/MC/AArch64/SVE/ld1b.s.yaml
new file mode 100644
index 000000000..7659eadff
--- /dev/null
+++ b/tests/MC/AArch64/SVE/ld1b.s.yaml
@@ -0,0 +1,440 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x00, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b { z0.b }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x20, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b { z0.h }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x40, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b { z0.s }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x60, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b { z0.d }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x00, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b { z0.b }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x20, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b { z0.h }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x40, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b { z0.s }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x60, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b { z0.d }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x0f, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b { z31.b }, p7/z, [sp, #-1, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xb5, 0x05, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b { z21.b }, p5/z, [x10, #5, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x2f, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b { z31.h }, p7/z, [sp, #-1, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xb5, 0x25, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b { z21.h }, p5/z, [x10, #5, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x4f, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b { z31.s }, p7/z, [sp, #-1, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xb5, 0x45, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b { z21.s }, p5/z, [x10, #5, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x6f, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b { z31.d }, p7/z, [sp, #-1, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xb5, 0x65, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b { z21.d }, p5/z, [x10, #5, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x43, 0x00, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b { z0.b }, p0/z, [sp, x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0x00, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b { z0.b }, p0/z, [x0, x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0x00, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b { z0.b }, p0/z, [x0, x0]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x4e, 0x30, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b { z5.h }, p3/z, [x17, x16]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x55, 0x55, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b { z21.s }, p5/z, [x10, x21]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x4d, 0x68, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b { z23.d }, p3/z, [x13, x8]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x00, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b { z0.b }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x20, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b { z0.h }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x40, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b { z0.s }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x60, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b { z0.d }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x00, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b { z0.b }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x20, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b { z0.h }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x40, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b { z0.s }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x60, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b { z0.d }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x0f, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b { z31.b }, p7/z, [sp, #-1, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xb5, 0x05, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b { z21.b }, p5/z, [x10, #5, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x2f, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b { z31.h }, p7/z, [sp, #-1, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xb5, 0x25, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b { z21.h }, p5/z, [x10, #5, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x4f, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b { z31.s }, p7/z, [sp, #-1, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xb5, 0x45, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b { z21.s }, p5/z, [x10, #5, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x6f, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b { z31.d }, p7/z, [sp, #-1, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xb5, 0x65, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b { z21.d }, p5/z, [x10, #5, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x43, 0x00, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b { z0.b }, p0/z, [sp, x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0x00, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b { z0.b }, p0/z, [x0, x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0x00, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b { z0.b }, p0/z, [x0, x0]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x4e, 0x30, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b { z5.h }, p3/z, [x17, x16]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x55, 0x55, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b { z21.s }, p5/z, [x10, x21]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x4d, 0x68, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b { z23.d }, p3/z, [x13, x8]"
diff --git a/tests/MC/AArch64/SVE/ld1d-sve-only.s.yaml b/tests/MC/AArch64/SVE/ld1d-sve-only.s.yaml
new file mode 100644
index 000000000..7dffb5bdf
--- /dev/null
+++ b/tests/MC/AArch64/SVE/ld1d-sve-only.s.yaml
@@ -0,0 +1,80 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xff, 0xdf, 0xdf, 0xc5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d { z31.d }, p7/z, [sp, z31.d]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xcd, 0xe8, 0xc5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d { z23.d }, p3/z, [x13, z8.d, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x55, 0x95, 0xc5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d { z21.d }, p5/z, [x10, z21.d, uxtw]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x55, 0xd5, 0xc5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d { z21.d }, p5/z, [x10, z21.d, sxtw]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0xa0, 0xc5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d { z0.d }, p0/z, [x0, z0.d, uxtw #3]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0xe0, 0xc5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d { z0.d }, p0/z, [x0, z0.d, sxtw #3]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xdf, 0xbf, 0xc5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d { z31.d }, p7/z, [z31.d, #248]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0xa0, 0xc5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d { z0.d }, p0/z, [z0.d]"
diff --git a/tests/MC/AArch64/SVE/ld1d.s.yaml b/tests/MC/AArch64/SVE/ld1d.s.yaml
new file mode 100644
index 000000000..bb40eb74c
--- /dev/null
+++ b/tests/MC/AArch64/SVE/ld1d.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xe0, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d { z0.d }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xe0, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d { z0.d }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0xef, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d { z31.d }, p7/z, [sp, #-1, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xb5, 0xe5, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d { z21.d }, p5/z, [x10, #5, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xf7, 0x4f, 0xe8, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d { z23.d }, p3/z, [sp, x8, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x4d, 0xe8, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d { z23.d }, p3/z, [x13, x8, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xe0, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d { z0.d }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xe0, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d { z0.d }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0xef, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d { z31.d }, p7/z, [sp, #-1, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xb5, 0xe5, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d { z21.d }, p5/z, [x10, #5, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xf7, 0x4f, 0xe8, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d { z23.d }, p3/z, [sp, x8, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x4d, 0xe8, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d { z23.d }, p3/z, [x13, x8, lsl #3]"
diff --git a/tests/MC/AArch64/SVE/ld1h-sve-only.s.yaml b/tests/MC/AArch64/SVE/ld1h-sve-only.s.yaml
new file mode 100644
index 000000000..e0e988981
--- /dev/null
+++ b/tests/MC/AArch64/SVE/ld1h-sve-only.s.yaml
@@ -0,0 +1,140 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0x80, 0x84 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h { z0.s }, p0/z, [x0, z0.s, uxtw]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0xc0, 0x84 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h { z0.s }, p0/z, [x0, z0.s, sxtw]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x5f, 0xbf, 0x84 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h { z31.s }, p7/z, [sp, z31.s, uxtw #1]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x5f, 0xff, 0x84 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h { z31.s }, p7/z, [sp, z31.s, sxtw #1]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xdf, 0xdf, 0xc4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h { z31.d }, p7/z, [sp, z31.d]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xcd, 0xe8, 0xc4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h { z23.d }, p3/z, [x13, z8.d, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x55, 0x95, 0xc4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h { z21.d }, p5/z, [x10, z21.d, uxtw]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x55, 0xd5, 0xc4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h { z21.d }, p5/z, [x10, z21.d, sxtw]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0xa0, 0xc4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h { z0.d }, p0/z, [x0, z0.d, uxtw #1]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0xe0, 0xc4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h { z0.d }, p0/z, [x0, z0.d, sxtw #1]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xdf, 0xbf, 0x84 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h { z31.s }, p7/z, [z31.s, #62]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0xa0, 0x84 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h { z0.s }, p0/z, [z0.s]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xdf, 0xbf, 0xc4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h { z31.d }, p7/z, [z31.d, #62]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0xa0, 0xc4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h { z0.d }, p0/z, [z0.d]"
diff --git a/tests/MC/AArch64/SVE/ld1h.s.yaml b/tests/MC/AArch64/SVE/ld1h.s.yaml
new file mode 100644
index 000000000..2606c1ae9
--- /dev/null
+++ b/tests/MC/AArch64/SVE/ld1h.s.yaml
@@ -0,0 +1,320 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xa0, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h { z0.h }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xc0, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h { z0.s }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xe0, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h { z0.d }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xa0, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h { z0.h }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xc0, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h { z0.s }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xe0, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h { z0.d }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0xaf, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h { z31.h }, p7/z, [sp, #-1, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xb5, 0xa5, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h { z21.h }, p5/z, [x10, #5, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0xcf, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h { z31.s }, p7/z, [sp, #-1, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xb5, 0xc5, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h { z21.s }, p5/z, [x10, #5, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0xef, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h { z31.d }, p7/z, [sp, #-1, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xb5, 0xe5, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h { z21.d }, p5/z, [x10, #5, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xe5, 0x4f, 0xb0, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h { z5.h }, p3/z, [sp, x16, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x4e, 0xb0, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h { z5.h }, p3/z, [x17, x16, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x55, 0xd5, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h { z21.s }, p5/z, [x10, x21, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x4d, 0xe8, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h { z23.d }, p3/z, [x13, x8, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xa0, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h { z0.h }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xc0, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h { z0.s }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xe0, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h { z0.d }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xa0, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h { z0.h }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xc0, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h { z0.s }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xe0, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h { z0.d }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0xaf, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h { z31.h }, p7/z, [sp, #-1, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xb5, 0xa5, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h { z21.h }, p5/z, [x10, #5, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0xcf, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h { z31.s }, p7/z, [sp, #-1, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xb5, 0xc5, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h { z21.s }, p5/z, [x10, #5, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0xef, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h { z31.d }, p7/z, [sp, #-1, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xb5, 0xe5, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h { z21.d }, p5/z, [x10, #5, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xe5, 0x4f, 0xb0, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h { z5.h }, p3/z, [sp, x16, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x4e, 0xb0, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h { z5.h }, p3/z, [x17, x16, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x55, 0xd5, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h { z21.s }, p5/z, [x10, x21, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x4d, 0xe8, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h { z23.d }, p3/z, [x13, x8, lsl #1]"
diff --git a/tests/MC/AArch64/SVE/ld1rb.s.yaml b/tests/MC/AArch64/SVE/ld1rb.s.yaml
new file mode 100644
index 000000000..1286a793e
--- /dev/null
+++ b/tests/MC/AArch64/SVE/ld1rb.s.yaml
@@ -0,0 +1,160 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x40, 0x84 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rb { z0.b }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x40, 0x84 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rb { z0.h }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x40, 0x84 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rb { z0.s }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x40, 0x84 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rb { z0.d }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x9f, 0x7f, 0x84 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rb { z31.b }, p7/z, [sp, #63]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x7f, 0x84 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rb { z31.h }, p7/z, [sp, #63]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xdf, 0x7f, 0x84 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rb { z31.s }, p7/z, [sp, #63]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0x7f, 0x84 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rb { z31.d }, p7/z, [sp, #63]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x40, 0x84 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rb { z0.b }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x40, 0x84 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rb { z0.h }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x40, 0x84 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rb { z0.s }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x40, 0x84 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rb { z0.d }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x9f, 0x7f, 0x84 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rb { z31.b }, p7/z, [sp, #63]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x7f, 0x84 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rb { z31.h }, p7/z, [sp, #63]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xdf, 0x7f, 0x84 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rb { z31.s }, p7/z, [sp, #63]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0x7f, 0x84 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rb { z31.d }, p7/z, [sp, #63]"
diff --git a/tests/MC/AArch64/SVE/ld1rd.s.yaml b/tests/MC/AArch64/SVE/ld1rd.s.yaml
new file mode 100644
index 000000000..211d429f6
--- /dev/null
+++ b/tests/MC/AArch64/SVE/ld1rd.s.yaml
@@ -0,0 +1,40 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rd { z0.d }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xff, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rd { z31.d }, p7/z, [sp, #504]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rd { z0.d }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xff, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rd { z31.d }, p7/z, [sp, #504]"
diff --git a/tests/MC/AArch64/SVE/ld1rh.s.yaml b/tests/MC/AArch64/SVE/ld1rh.s.yaml
new file mode 100644
index 000000000..83f18de92
--- /dev/null
+++ b/tests/MC/AArch64/SVE/ld1rh.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xc0, 0x84 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rh { z0.h }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0xc0, 0x84 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rh { z0.s }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xc0, 0x84 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rh { z0.d }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0xff, 0x84 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rh { z31.h }, p7/z, [sp, #126]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xdf, 0xff, 0x84 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rh { z31.s }, p7/z, [sp, #126]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xff, 0x84 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rh { z31.d }, p7/z, [sp, #126]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xc0, 0x84 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rh { z0.h }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0xc0, 0x84 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rh { z0.s }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xc0, 0x84 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rh { z0.d }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0xff, 0x84 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rh { z31.h }, p7/z, [sp, #126]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xdf, 0xff, 0x84 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rh { z31.s }, p7/z, [sp, #126]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xff, 0x84 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rh { z31.d }, p7/z, [sp, #126]"
diff --git a/tests/MC/AArch64/SVE/ld1rqb.s.yaml b/tests/MC/AArch64/SVE/ld1rqb.s.yaml
new file mode 100644
index 000000000..5645e8759
--- /dev/null
+++ b/tests/MC/AArch64/SVE/ld1rqb.s.yaml
@@ -0,0 +1,100 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x00, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rqb { z0.b }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x00, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rqb { z0.b }, p0/z, [x0, x0]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0x0f, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rqb { z31.b }, p7/z, [sp, #-16]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x2d, 0x08, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rqb { z23.b }, p3/z, [x13, #-128]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x35, 0x07, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rqb { z21.b }, p5/z, [x10, #112]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x00, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rqb { z0.b }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x00, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rqb { z0.b }, p0/z, [x0, x0]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0x0f, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rqb { z31.b }, p7/z, [sp, #-16]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x2d, 0x08, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rqb { z23.b }, p3/z, [x13, #-128]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x35, 0x07, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rqb { z21.b }, p5/z, [x10, #112]"
diff --git a/tests/MC/AArch64/SVE/ld1rqd.s.yaml b/tests/MC/AArch64/SVE/ld1rqd.s.yaml
new file mode 100644
index 000000000..534161021
--- /dev/null
+++ b/tests/MC/AArch64/SVE/ld1rqd.s.yaml
@@ -0,0 +1,100 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x80, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rqd { z0.d }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x80, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rqd { z0.d }, p0/z, [x0, x0, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0x8f, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rqd { z31.d }, p7/z, [sp, #-16]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x2d, 0x88, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rqd { z23.d }, p3/z, [x13, #-128]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x2d, 0x87, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rqd { z23.d }, p3/z, [x13, #112]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x80, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rqd { z0.d }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x80, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rqd { z0.d }, p0/z, [x0, x0, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0x8f, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rqd { z31.d }, p7/z, [sp, #-16]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x2d, 0x88, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rqd { z23.d }, p3/z, [x13, #-128]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x2d, 0x87, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rqd { z23.d }, p3/z, [x13, #112]"
diff --git a/tests/MC/AArch64/SVE/ld1rqh.s.yaml b/tests/MC/AArch64/SVE/ld1rqh.s.yaml
new file mode 100644
index 000000000..65a6347b2
--- /dev/null
+++ b/tests/MC/AArch64/SVE/ld1rqh.s.yaml
@@ -0,0 +1,100 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x80, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rqh { z0.h }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x80, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rqh { z0.h }, p0/z, [x0, x0, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0x8f, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rqh { z31.h }, p7/z, [sp, #-16]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x2d, 0x88, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rqh { z23.h }, p3/z, [x13, #-128]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x2d, 0x87, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rqh { z23.h }, p3/z, [x13, #112]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x80, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rqh { z0.h }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x80, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rqh { z0.h }, p0/z, [x0, x0, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0x8f, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rqh { z31.h }, p7/z, [sp, #-16]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x2d, 0x88, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rqh { z23.h }, p3/z, [x13, #-128]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x2d, 0x87, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rqh { z23.h }, p3/z, [x13, #112]"
diff --git a/tests/MC/AArch64/SVE/ld1rqw.s.yaml b/tests/MC/AArch64/SVE/ld1rqw.s.yaml
new file mode 100644
index 000000000..2dc1b6d0c
--- /dev/null
+++ b/tests/MC/AArch64/SVE/ld1rqw.s.yaml
@@ -0,0 +1,100 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x00, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rqw { z0.s }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x00, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rqw { z0.s }, p0/z, [x0, x0, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0x0f, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rqw { z31.s }, p7/z, [sp, #-16]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x2d, 0x08, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rqw { z23.s }, p3/z, [x13, #-128]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x2d, 0x07, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rqw { z23.s }, p3/z, [x13, #112]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x00, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rqw { z0.s }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x00, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rqw { z0.s }, p0/z, [x0, x0, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0x0f, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rqw { z31.s }, p7/z, [sp, #-16]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x2d, 0x08, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rqw { z23.s }, p3/z, [x13, #-128]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x2d, 0x07, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rqw { z23.s }, p3/z, [x13, #112]"
diff --git a/tests/MC/AArch64/SVE/ld1rsb.s.yaml b/tests/MC/AArch64/SVE/ld1rsb.s.yaml
new file mode 100644
index 000000000..2cf649571
--- /dev/null
+++ b/tests/MC/AArch64/SVE/ld1rsb.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rsb { z0.h }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rsb { z0.s }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rsb { z0.d }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xdf, 0xff, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rsb { z31.h }, p7/z, [sp, #63]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0xff, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rsb { z31.s }, p7/z, [sp, #63]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x9f, 0xff, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rsb { z31.d }, p7/z, [sp, #63]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rsb { z0.h }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rsb { z0.s }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rsb { z0.d }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xdf, 0xff, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rsb { z31.h }, p7/z, [sp, #63]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0xff, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rsb { z31.s }, p7/z, [sp, #63]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x9f, 0xff, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rsb { z31.d }, p7/z, [sp, #63]"
diff --git a/tests/MC/AArch64/SVE/ld1rsh.s.yaml b/tests/MC/AArch64/SVE/ld1rsh.s.yaml
new file mode 100644
index 000000000..1c0b2a4a2
--- /dev/null
+++ b/tests/MC/AArch64/SVE/ld1rsh.s.yaml
@@ -0,0 +1,80 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x40, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rsh { z0.s }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x40, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rsh { z0.d }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x7f, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rsh { z31.s }, p7/z, [sp, #126]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x9f, 0x7f, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rsh { z31.d }, p7/z, [sp, #126]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x40, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rsh { z0.s }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x40, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rsh { z0.d }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x7f, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rsh { z31.s }, p7/z, [sp, #126]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x9f, 0x7f, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rsh { z31.d }, p7/z, [sp, #126]"
diff --git a/tests/MC/AArch64/SVE/ld1rsw.s.yaml b/tests/MC/AArch64/SVE/ld1rsw.s.yaml
new file mode 100644
index 000000000..dd790bdc0
--- /dev/null
+++ b/tests/MC/AArch64/SVE/ld1rsw.s.yaml
@@ -0,0 +1,40 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xc0, 0x84 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rsw { z0.d }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x9f, 0xff, 0x84 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rsw { z31.d }, p7/z, [sp, #252]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xc0, 0x84 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rsw { z0.d }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x9f, 0xff, 0x84 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rsw { z31.d }, p7/z, [sp, #252]"
diff --git a/tests/MC/AArch64/SVE/ld1rw.s.yaml b/tests/MC/AArch64/SVE/ld1rw.s.yaml
new file mode 100644
index 000000000..59e35f387
--- /dev/null
+++ b/tests/MC/AArch64/SVE/ld1rw.s.yaml
@@ -0,0 +1,80 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x40, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rw { z0.s }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x40, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rw { z0.d }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xdf, 0x7f, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rw { z31.s }, p7/z, [sp, #252]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0x7f, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rw { z31.d }, p7/z, [sp, #252]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x40, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rw { z0.s }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x40, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rw { z0.d }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xdf, 0x7f, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rw { z31.s }, p7/z, [sp, #252]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0x7f, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rw { z31.d }, p7/z, [sp, #252]"
diff --git a/tests/MC/AArch64/SVE/ld1sb-sve-only.s.yaml b/tests/MC/AArch64/SVE/ld1sb-sve-only.s.yaml
new file mode 100644
index 000000000..07c65fb8d
--- /dev/null
+++ b/tests/MC/AArch64/SVE/ld1sb-sve-only.s.yaml
@@ -0,0 +1,80 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x40, 0x84 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1sb { z0.s }, p0/z, [x0, z0.s, sxtw]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x9f, 0x5f, 0xc4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1sb { z31.d }, p7/z, [sp, z31.d]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x15, 0x15, 0xc4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1sb { z21.d }, p5/z, [x10, z21.d, uxtw]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x15, 0x55, 0xc4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1sb { z21.d }, p5/z, [x10, z21.d, sxtw]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x9f, 0x3f, 0x84 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1sb { z31.s }, p7/z, [z31.s, #31]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x20, 0x84 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1sb { z0.s }, p0/z, [z0.s]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x9f, 0x3f, 0xc4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1sb { z31.d }, p7/z, [z31.d, #31]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x20, 0xc4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1sb { z0.d }, p0/z, [z0.d]"
diff --git a/tests/MC/AArch64/SVE/ld1sb.s.yaml b/tests/MC/AArch64/SVE/ld1sb.s.yaml
new file mode 100644
index 000000000..daeebb6e7
--- /dev/null
+++ b/tests/MC/AArch64/SVE/ld1sb.s.yaml
@@ -0,0 +1,340 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xc0, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1sb { z0.h }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xa0, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1sb { z0.s }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x80, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1sb { z0.d }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xc0, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1sb { z0.h }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xa0, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1sb { z0.s }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x80, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1sb { z0.d }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0xcf, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1sb { z31.h }, p7/z, [sp, #-1, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xb5, 0xc5, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1sb { z21.h }, p5/z, [x10, #5, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0xaf, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1sb { z31.s }, p7/z, [sp, #-1, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xb5, 0xa5, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1sb { z21.s }, p5/z, [x10, #5, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x8f, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1sb { z31.d }, p7/z, [sp, #-1, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xb5, 0x85, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1sb { z21.d }, p5/z, [x10, #5, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x43, 0xc0, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1sb { z0.h }, p0/z, [sp, x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0xc0, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1sb { z0.h }, p0/z, [x0, x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0xc0, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1sb { z0.h }, p0/z, [x0, x0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x55, 0xb5, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1sb { z21.s }, p5/z, [x10, x21]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x4d, 0x88, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1sb { z23.d }, p3/z, [x13, x8]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xc0, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1sb { z0.h }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xa0, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1sb { z0.s }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x80, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1sb { z0.d }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xc0, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1sb { z0.h }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xa0, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1sb { z0.s }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x80, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1sb { z0.d }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0xcf, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1sb { z31.h }, p7/z, [sp, #-1, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xb5, 0xc5, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1sb { z21.h }, p5/z, [x10, #5, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0xaf, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1sb { z31.s }, p7/z, [sp, #-1, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xb5, 0xa5, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1sb { z21.s }, p5/z, [x10, #5, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x8f, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1sb { z31.d }, p7/z, [sp, #-1, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xb5, 0x85, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1sb { z21.d }, p5/z, [x10, #5, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x43, 0xc0, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1sb { z0.h }, p0/z, [sp, x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0xc0, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1sb { z0.h }, p0/z, [x0, x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0xc0, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1sb { z0.h }, p0/z, [x0, x0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x55, 0xb5, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1sb { z21.s }, p5/z, [x10, x21]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x4d, 0x88, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1sb { z23.d }, p3/z, [x13, x8]"
diff --git a/tests/MC/AArch64/SVE/ld1sh-sve-only.s.yaml b/tests/MC/AArch64/SVE/ld1sh-sve-only.s.yaml
new file mode 100644
index 000000000..123b3c214
--- /dev/null
+++ b/tests/MC/AArch64/SVE/ld1sh-sve-only.s.yaml
@@ -0,0 +1,140 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x80, 0x84 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1sh { z0.s }, p0/z, [x0, z0.s, uxtw]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0xc0, 0x84 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1sh { z0.s }, p0/z, [x0, z0.s, sxtw]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0xbf, 0x84 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1sh { z31.s }, p7/z, [sp, z31.s, uxtw #1]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0xff, 0x84 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1sh { z31.s }, p7/z, [sp, z31.s, sxtw #1]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x9f, 0xdf, 0xc4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1sh { z31.d }, p7/z, [sp, z31.d]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x8d, 0xe8, 0xc4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1sh { z23.d }, p3/z, [x13, z8.d, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x15, 0x95, 0xc4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1sh { z21.d }, p5/z, [x10, z21.d, uxtw]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x15, 0xd5, 0xc4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1sh { z21.d }, p5/z, [x10, z21.d, sxtw]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0xa0, 0xc4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1sh { z0.d }, p0/z, [x0, z0.d, uxtw #1]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0xe0, 0xc4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1sh { z0.d }, p0/z, [x0, z0.d, sxtw #1]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x9f, 0xbf, 0x84 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1sh { z31.s }, p7/z, [z31.s, #62]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xa0, 0x84 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1sh { z0.s }, p0/z, [z0.s]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x9f, 0xbf, 0xc4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1sh { z31.d }, p7/z, [z31.d, #62]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xa0, 0xc4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1sh { z0.d }, p0/z, [z0.d]"
diff --git a/tests/MC/AArch64/SVE/ld1sh.s.yaml b/tests/MC/AArch64/SVE/ld1sh.s.yaml
new file mode 100644
index 000000000..9c00f9c58
--- /dev/null
+++ b/tests/MC/AArch64/SVE/ld1sh.s.yaml
@@ -0,0 +1,220 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x20, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1sh { z0.s }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x00, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1sh { z0.d }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x20, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1sh { z0.s }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x00, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1sh { z0.d }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x2f, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1sh { z31.s }, p7/z, [sp, #-1, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xb5, 0x25, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1sh { z21.s }, p5/z, [x10, #5, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x0f, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1sh { z31.d }, p7/z, [sp, #-1, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xb5, 0x05, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1sh { z21.d }, p5/z, [x10, #5, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xf5, 0x57, 0x35, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1sh { z21.s }, p5/z, [sp, x21, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x55, 0x35, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1sh { z21.s }, p5/z, [x10, x21, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x4d, 0x08, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1sh { z23.d }, p3/z, [x13, x8, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x20, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1sh { z0.s }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x00, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1sh { z0.d }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x20, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1sh { z0.s }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x00, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1sh { z0.d }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x2f, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1sh { z31.s }, p7/z, [sp, #-1, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xb5, 0x25, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1sh { z21.s }, p5/z, [x10, #5, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x0f, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1sh { z31.d }, p7/z, [sp, #-1, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xb5, 0x05, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1sh { z21.d }, p5/z, [x10, #5, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xf5, 0x57, 0x35, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1sh { z21.s }, p5/z, [sp, x21, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x55, 0x35, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1sh { z21.s }, p5/z, [x10, x21, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x4d, 0x08, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1sh { z23.d }, p3/z, [x13, x8, lsl #1]"
diff --git a/tests/MC/AArch64/SVE/ld1sw-sve-only.s.yaml b/tests/MC/AArch64/SVE/ld1sw-sve-only.s.yaml
new file mode 100644
index 000000000..be4491b01
--- /dev/null
+++ b/tests/MC/AArch64/SVE/ld1sw-sve-only.s.yaml
@@ -0,0 +1,80 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xff, 0x9f, 0x5f, 0xc5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1sw { z31.d }, p7/z, [sp, z31.d]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x8d, 0x68, 0xc5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1sw { z23.d }, p3/z, [x13, z8.d, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x15, 0x15, 0xc5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1sw { z21.d }, p5/z, [x10, z21.d, uxtw]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x15, 0x55, 0xc5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1sw { z21.d }, p5/z, [x10, z21.d, sxtw]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x20, 0xc5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1sw { z0.d }, p0/z, [x0, z0.d, uxtw #2]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x60, 0xc5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1sw { z0.d }, p0/z, [x0, z0.d, sxtw #2]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x9f, 0x3f, 0xc5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1sw { z31.d }, p7/z, [z31.d, #124]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x20, 0xc5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1sw { z0.d }, p0/z, [z0.d]"
diff --git a/tests/MC/AArch64/SVE/ld1sw.s.yaml b/tests/MC/AArch64/SVE/ld1sw.s.yaml
new file mode 100644
index 000000000..eaf94cb94
--- /dev/null
+++ b/tests/MC/AArch64/SVE/ld1sw.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x80, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1sw { z0.d }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x80, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1sw { z0.d }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x8f, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1sw { z31.d }, p7/z, [sp, #-1, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xb5, 0x85, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1sw { z21.d }, p5/z, [x10, #5, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xf7, 0x4f, 0x88, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1sw { z23.d }, p3/z, [sp, x8, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x4d, 0x88, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1sw { z23.d }, p3/z, [x13, x8, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x80, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1sw { z0.d }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x80, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1sw { z0.d }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x8f, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1sw { z31.d }, p7/z, [sp, #-1, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xb5, 0x85, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1sw { z21.d }, p5/z, [x10, #5, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xf7, 0x4f, 0x88, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1sw { z23.d }, p3/z, [sp, x8, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x4d, 0x88, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1sw { z23.d }, p3/z, [x13, x8, lsl #2]"
diff --git a/tests/MC/AArch64/SVE/ld1w-sve-only.s.yaml b/tests/MC/AArch64/SVE/ld1w-sve-only.s.yaml
new file mode 100644
index 000000000..4e0d52164
--- /dev/null
+++ b/tests/MC/AArch64/SVE/ld1w-sve-only.s.yaml
@@ -0,0 +1,140 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0x00, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w { z0.s }, p0/z, [x0, z0.s, uxtw]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0x40, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w { z0.s }, p0/z, [x0, z0.s, sxtw]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x5f, 0x3f, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w { z31.s }, p7/z, [sp, z31.s, uxtw #2]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x5f, 0x7f, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w { z31.s }, p7/z, [sp, z31.s, sxtw #2]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xdf, 0x5f, 0xc5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w { z31.d }, p7/z, [sp, z31.d]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xcd, 0x68, 0xc5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w { z23.d }, p3/z, [x13, z8.d, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x55, 0x15, 0xc5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w { z21.d }, p5/z, [x10, z21.d, uxtw]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x55, 0x55, 0xc5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w { z21.d }, p5/z, [x10, z21.d, sxtw]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0x20, 0xc5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w { z0.d }, p0/z, [x0, z0.d, uxtw #2]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0x60, 0xc5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w { z0.d }, p0/z, [x0, z0.d, sxtw #2]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xdf, 0x3f, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w { z31.s }, p7/z, [z31.s, #124]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x20, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w { z0.s }, p0/z, [z0.s]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xdf, 0x3f, 0xc5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w { z31.d }, p7/z, [z31.d, #124]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x20, 0xc5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w { z0.d }, p0/z, [z0.d]"
diff --git a/tests/MC/AArch64/SVE/ld1w.s.yaml b/tests/MC/AArch64/SVE/ld1w.s.yaml
new file mode 100644
index 000000000..021edeb2f
--- /dev/null
+++ b/tests/MC/AArch64/SVE/ld1w.s.yaml
@@ -0,0 +1,220 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x40, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w { z0.s }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x60, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w { z0.d }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x40, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w { z0.s }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x60, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w { z0.d }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x4f, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w { z31.s }, p7/z, [sp, #-1, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xb5, 0x45, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w { z21.s }, p5/z, [x10, #5, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x6f, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w { z31.d }, p7/z, [sp, #-1, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xb5, 0x65, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w { z21.d }, p5/z, [x10, #5, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xf5, 0x57, 0x55, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w { z21.s }, p5/z, [sp, x21, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x55, 0x55, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w { z21.s }, p5/z, [x10, x21, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x4d, 0x68, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w { z23.d }, p3/z, [x13, x8, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x40, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w { z0.s }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x60, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w { z0.d }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x40, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w { z0.s }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x60, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w { z0.d }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x4f, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w { z31.s }, p7/z, [sp, #-1, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xb5, 0x45, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w { z21.s }, p5/z, [x10, #5, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x6f, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w { z31.d }, p7/z, [sp, #-1, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xb5, 0x65, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w { z21.d }, p5/z, [x10, #5, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xf5, 0x57, 0x55, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w { z21.s }, p5/z, [sp, x21, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x55, 0x55, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w { z21.s }, p5/z, [x10, x21, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x4d, 0x68, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w { z23.d }, p3/z, [x13, x8, lsl #2]"
diff --git a/tests/MC/AArch64/SVE/ld2b.s.yaml b/tests/MC/AArch64/SVE/ld2b.s.yaml
new file mode 100644
index 000000000..bb1533b23
--- /dev/null
+++ b/tests/MC/AArch64/SVE/ld2b.s.yaml
@@ -0,0 +1,100 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x20, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld2b { z0.b, z1.b }, p0/z, [x0, x0]"
+
+  -
+    input:
+      bytes: [ 0x25, 0xce, 0x30, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld2b { z5.b, z6.b }, p3/z, [x17, x16]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x20, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld2b { z0.b, z1.b }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0x28, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld2b { z23.b, z24.b }, p3/z, [x13, #-16, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf5, 0x25, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld2b { z21.b, z22.b }, p5/z, [x10, #10, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x20, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld2b { z0.b, z1.b }, p0/z, [x0, x0]"
+
+  -
+    input:
+      bytes: [ 0x25, 0xce, 0x30, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld2b { z5.b, z6.b }, p3/z, [x17, x16]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x20, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld2b { z0.b, z1.b }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0x28, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld2b { z23.b, z24.b }, p3/z, [x13, #-16, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf5, 0x25, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld2b { z21.b, z22.b }, p5/z, [x10, #10, mul vl]"
diff --git a/tests/MC/AArch64/SVE/ld2d.s.yaml b/tests/MC/AArch64/SVE/ld2d.s.yaml
new file mode 100644
index 000000000..23202c403
--- /dev/null
+++ b/tests/MC/AArch64/SVE/ld2d.s.yaml
@@ -0,0 +1,100 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0xa0, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld2d { z0.d, z1.d }, p0/z, [x0, x0, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x25, 0xce, 0xb0, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld2d { z5.d, z6.d }, p3/z, [x17, x16, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xa0, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld2d { z0.d, z1.d }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0xa8, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld2d { z23.d, z24.d }, p3/z, [x13, #-16, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf5, 0xa5, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld2d { z21.d, z22.d }, p5/z, [x10, #10, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0xa0, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld2d { z0.d, z1.d }, p0/z, [x0, x0, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x25, 0xce, 0xb0, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld2d { z5.d, z6.d }, p3/z, [x17, x16, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xa0, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld2d { z0.d, z1.d }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0xa8, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld2d { z23.d, z24.d }, p3/z, [x13, #-16, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf5, 0xa5, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld2d { z21.d, z22.d }, p5/z, [x10, #10, mul vl]"
diff --git a/tests/MC/AArch64/SVE/ld2h.s.yaml b/tests/MC/AArch64/SVE/ld2h.s.yaml
new file mode 100644
index 000000000..8996bc2f7
--- /dev/null
+++ b/tests/MC/AArch64/SVE/ld2h.s.yaml
@@ -0,0 +1,100 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0xa0, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld2h { z0.h, z1.h }, p0/z, [x0, x0, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x25, 0xce, 0xb0, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld2h { z5.h, z6.h }, p3/z, [x17, x16, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xa0, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld2h { z0.h, z1.h }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0xa8, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld2h { z23.h, z24.h }, p3/z, [x13, #-16, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf5, 0xa5, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld2h { z21.h, z22.h }, p5/z, [x10, #10, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0xa0, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld2h { z0.h, z1.h }, p0/z, [x0, x0, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x25, 0xce, 0xb0, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld2h { z5.h, z6.h }, p3/z, [x17, x16, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xa0, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld2h { z0.h, z1.h }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0xa8, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld2h { z23.h, z24.h }, p3/z, [x13, #-16, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf5, 0xa5, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld2h { z21.h, z22.h }, p5/z, [x10, #10, mul vl]"
diff --git a/tests/MC/AArch64/SVE/ld2w.s.yaml b/tests/MC/AArch64/SVE/ld2w.s.yaml
new file mode 100644
index 000000000..12f41fb30
--- /dev/null
+++ b/tests/MC/AArch64/SVE/ld2w.s.yaml
@@ -0,0 +1,100 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x20, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld2w { z0.s, z1.s }, p0/z, [x0, x0, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x25, 0xce, 0x30, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld2w { z5.s, z6.s }, p3/z, [x17, x16, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x20, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld2w { z0.s, z1.s }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0x28, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld2w { z23.s, z24.s }, p3/z, [x13, #-16, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf5, 0x25, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld2w { z21.s, z22.s }, p5/z, [x10, #10, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x20, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld2w { z0.s, z1.s }, p0/z, [x0, x0, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x25, 0xce, 0x30, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld2w { z5.s, z6.s }, p3/z, [x17, x16, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x20, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld2w { z0.s, z1.s }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0x28, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld2w { z23.s, z24.s }, p3/z, [x13, #-16, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf5, 0x25, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld2w { z21.s, z22.s }, p5/z, [x10, #10, mul vl]"
diff --git a/tests/MC/AArch64/SVE/ld3b.s.yaml b/tests/MC/AArch64/SVE/ld3b.s.yaml
new file mode 100644
index 000000000..52f795ed0
--- /dev/null
+++ b/tests/MC/AArch64/SVE/ld3b.s.yaml
@@ -0,0 +1,100 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x40, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld3b { z0.b - z2.b }, p0/z, [x0, x0]"
+
+  -
+    input:
+      bytes: [ 0x25, 0xce, 0x50, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld3b { z5.b - z7.b }, p3/z, [x17, x16]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x40, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld3b { z0.b - z2.b }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0x48, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld3b { z23.b - z25.b }, p3/z, [x13, #-24, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf5, 0x45, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld3b { z21.b - z23.b }, p5/z, [x10, #15, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x40, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld3b { z0.b - z2.b }, p0/z, [x0, x0]"
+
+  -
+    input:
+      bytes: [ 0x25, 0xce, 0x50, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld3b { z5.b - z7.b }, p3/z, [x17, x16]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x40, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld3b { z0.b - z2.b }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0x48, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld3b { z23.b - z25.b }, p3/z, [x13, #-24, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf5, 0x45, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld3b { z21.b - z23.b }, p5/z, [x10, #15, mul vl]"
diff --git a/tests/MC/AArch64/SVE/ld3d.s.yaml b/tests/MC/AArch64/SVE/ld3d.s.yaml
new file mode 100644
index 000000000..829865772
--- /dev/null
+++ b/tests/MC/AArch64/SVE/ld3d.s.yaml
@@ -0,0 +1,100 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0xc0, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld3d { z0.d - z2.d }, p0/z, [x0, x0, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x25, 0xce, 0xd0, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld3d { z5.d - z7.d }, p3/z, [x17, x16, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xc0, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld3d { z0.d - z2.d }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0xc8, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld3d { z23.d - z25.d }, p3/z, [x13, #-24, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf5, 0xc5, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld3d { z21.d - z23.d }, p5/z, [x10, #15, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0xc0, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld3d { z0.d - z2.d }, p0/z, [x0, x0, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x25, 0xce, 0xd0, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld3d { z5.d - z7.d }, p3/z, [x17, x16, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xc0, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld3d { z0.d - z2.d }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0xc8, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld3d { z23.d - z25.d }, p3/z, [x13, #-24, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf5, 0xc5, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld3d { z21.d - z23.d }, p5/z, [x10, #15, mul vl]"
diff --git a/tests/MC/AArch64/SVE/ld3h.s.yaml b/tests/MC/AArch64/SVE/ld3h.s.yaml
new file mode 100644
index 000000000..2f44bcb3d
--- /dev/null
+++ b/tests/MC/AArch64/SVE/ld3h.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0xc0, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld3h { z0.h - z2.h }, p0/z, [x0, x0, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x25, 0xce, 0xd0, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld3h { z5.h - z7.h }, p3/z, [x17, x16, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xc0, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld3h { z0.h - z2.h }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0xc8, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld3h { z23.h - z25.h }, p3/z, [x13, #-24, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf5, 0xc5, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld3h { z21.h - z23.h }, p5/z, [x10, #15, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x5e, 0xf5, 0xc5, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld3h { z30.h, z31.h, z0.h }, p5/z, [x10, #15, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0xc0, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld3h { z0.h - z2.h }, p0/z, [x0, x0, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x25, 0xce, 0xd0, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld3h { z5.h - z7.h }, p3/z, [x17, x16, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xc0, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld3h { z0.h - z2.h }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0xc8, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld3h { z23.h - z25.h }, p3/z, [x13, #-24, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf5, 0xc5, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld3h { z21.h - z23.h }, p5/z, [x10, #15, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x5e, 0xf5, 0xc5, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld3h { z30.h, z31.h, z0.h }, p5/z, [x10, #15, mul vl]"
diff --git a/tests/MC/AArch64/SVE/ld3w.s.yaml b/tests/MC/AArch64/SVE/ld3w.s.yaml
new file mode 100644
index 000000000..eb7d1b354
--- /dev/null
+++ b/tests/MC/AArch64/SVE/ld3w.s.yaml
@@ -0,0 +1,100 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x40, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld3w { z0.s - z2.s }, p0/z, [x0, x0, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x25, 0xce, 0x50, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld3w { z5.s - z7.s }, p3/z, [x17, x16, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x40, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld3w { z0.s - z2.s }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0x48, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld3w { z23.s - z25.s }, p3/z, [x13, #-24, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf5, 0x45, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld3w { z21.s - z23.s }, p5/z, [x10, #15, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x40, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld3w { z0.s - z2.s }, p0/z, [x0, x0, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x25, 0xce, 0x50, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld3w { z5.s - z7.s }, p3/z, [x17, x16, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x40, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld3w { z0.s - z2.s }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0x48, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld3w { z23.s - z25.s }, p3/z, [x13, #-24, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf5, 0x45, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld3w { z21.s - z23.s }, p5/z, [x10, #15, mul vl]"
diff --git a/tests/MC/AArch64/SVE/ld4b.s.yaml b/tests/MC/AArch64/SVE/ld4b.s.yaml
new file mode 100644
index 000000000..e5539b67a
--- /dev/null
+++ b/tests/MC/AArch64/SVE/ld4b.s.yaml
@@ -0,0 +1,100 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x60, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld4b { z0.b - z3.b }, p0/z, [x0, x0]"
+
+  -
+    input:
+      bytes: [ 0x25, 0xce, 0x70, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld4b { z5.b - z8.b }, p3/z, [x17, x16]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x60, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld4b { z0.b - z3.b }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0x68, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld4b { z23.b - z26.b }, p3/z, [x13, #-32, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf5, 0x65, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld4b { z21.b - z24.b }, p5/z, [x10, #20, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x60, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld4b { z0.b - z3.b }, p0/z, [x0, x0]"
+
+  -
+    input:
+      bytes: [ 0x25, 0xce, 0x70, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld4b { z5.b - z8.b }, p3/z, [x17, x16]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x60, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld4b { z0.b - z3.b }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0x68, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld4b { z23.b - z26.b }, p3/z, [x13, #-32, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf5, 0x65, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld4b { z21.b - z24.b }, p5/z, [x10, #20, mul vl]"
diff --git a/tests/MC/AArch64/SVE/ld4d.s.yaml b/tests/MC/AArch64/SVE/ld4d.s.yaml
new file mode 100644
index 000000000..83a8f7635
--- /dev/null
+++ b/tests/MC/AArch64/SVE/ld4d.s.yaml
@@ -0,0 +1,100 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0xe0, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld4d { z0.d - z3.d }, p0/z, [x0, x0, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x25, 0xce, 0xf0, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld4d { z5.d - z8.d }, p3/z, [x17, x16, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xe0, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld4d { z0.d - z3.d }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0xe8, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld4d { z23.d - z26.d }, p3/z, [x13, #-32, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf5, 0xe5, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld4d { z21.d - z24.d }, p5/z, [x10, #20, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0xe0, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld4d { z0.d - z3.d }, p0/z, [x0, x0, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x25, 0xce, 0xf0, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld4d { z5.d - z8.d }, p3/z, [x17, x16, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xe0, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld4d { z0.d - z3.d }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0xe8, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld4d { z23.d - z26.d }, p3/z, [x13, #-32, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf5, 0xe5, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld4d { z21.d - z24.d }, p5/z, [x10, #20, mul vl]"
diff --git a/tests/MC/AArch64/SVE/ld4h.s.yaml b/tests/MC/AArch64/SVE/ld4h.s.yaml
new file mode 100644
index 000000000..3a9012bd8
--- /dev/null
+++ b/tests/MC/AArch64/SVE/ld4h.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0xe0, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld4h { z0.h - z3.h }, p0/z, [x0, x0, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x25, 0xce, 0xf0, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld4h { z5.h - z8.h }, p3/z, [x17, x16, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xe0, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld4h { z0.h - z3.h }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0xe8, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld4h { z23.h - z26.h }, p3/z, [x13, #-32, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf5, 0xe5, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld4h { z21.h - z24.h }, p5/z, [x10, #20, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x5f, 0xf5, 0xe5, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld4h { z31.h, z0.h, z1.h, z2.h }, p5/z, [x10, #20, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0xe0, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld4h { z0.h - z3.h }, p0/z, [x0, x0, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x25, 0xce, 0xf0, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld4h { z5.h - z8.h }, p3/z, [x17, x16, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xe0, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld4h { z0.h - z3.h }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0xe8, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld4h { z23.h - z26.h }, p3/z, [x13, #-32, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf5, 0xe5, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld4h { z21.h - z24.h }, p5/z, [x10, #20, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x5f, 0xf5, 0xe5, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld4h { z31.h, z0.h, z1.h, z2.h }, p5/z, [x10, #20, mul vl]"
diff --git a/tests/MC/AArch64/SVE/ld4w.s.yaml b/tests/MC/AArch64/SVE/ld4w.s.yaml
new file mode 100644
index 000000000..dea69b87f
--- /dev/null
+++ b/tests/MC/AArch64/SVE/ld4w.s.yaml
@@ -0,0 +1,100 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x60, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld4w { z0.s - z3.s }, p0/z, [x0, x0, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x25, 0xce, 0x70, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld4w { z5.s - z8.s }, p3/z, [x17, x16, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x60, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld4w { z0.s - z3.s }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0x68, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld4w { z23.s - z26.s }, p3/z, [x13, #-32, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf5, 0x65, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld4w { z21.s - z24.s }, p5/z, [x10, #20, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x60, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld4w { z0.s - z3.s }, p0/z, [x0, x0, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x25, 0xce, 0x70, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld4w { z5.s - z8.s }, p3/z, [x17, x16, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x60, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld4w { z0.s - z3.s }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0x68, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld4w { z23.s - z26.s }, p3/z, [x13, #-32, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf5, 0x65, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld4w { z21.s - z24.s }, p5/z, [x10, #20, mul vl]"
diff --git a/tests/MC/AArch64/SVE/ldff1b.s.yaml b/tests/MC/AArch64/SVE/ldff1b.s.yaml
new file mode 100644
index 000000000..41648e0bc
--- /dev/null
+++ b/tests/MC/AArch64/SVE/ldff1b.s.yaml
@@ -0,0 +1,200 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xff, 0x7f, 0x1f, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1b { z31.b }, p7/z, [sp]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x7f, 0x3f, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1b { z31.h }, p7/z, [sp]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x7f, 0x5f, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1b { z31.s }, p7/z, [sp]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x7f, 0x7f, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1b { z31.d }, p7/z, [sp]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x7f, 0x1f, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1b { z31.b }, p7/z, [sp]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x7f, 0x3f, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1b { z31.h }, p7/z, [sp]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x7f, 0x5f, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1b { z31.s }, p7/z, [sp]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x7f, 0x7f, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1b { z31.d }, p7/z, [sp]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0x20, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1b { z0.h }, p0/z, [x0, x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0x40, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1b { z0.s }, p0/z, [x0, x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0x60, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1b { z0.d }, p0/z, [x0, x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0x00, 0x84 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1b { z0.s }, p0/z, [x0, z0.s, uxtw]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0x40, 0x84 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1b { z0.s }, p0/z, [x0, z0.s, sxtw]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0x5f, 0xc4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1b { z31.d }, p7/z, [sp, z31.d]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x75, 0x15, 0xc4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1b { z21.d }, p5/z, [x10, z21.d, uxtw]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x75, 0x55, 0xc4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1b { z21.d }, p5/z, [x10, z21.d, sxtw]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0x3f, 0x84 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1b { z31.s }, p7/z, [z31.s, #31]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x20, 0x84 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1b { z0.s }, p0/z, [z0.s]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0x3f, 0xc4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1b { z31.d }, p7/z, [z31.d, #31]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x20, 0xc4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1b { z0.d }, p0/z, [z0.d]"
diff --git a/tests/MC/AArch64/SVE/ldff1d.s.yaml b/tests/MC/AArch64/SVE/ldff1d.s.yaml
new file mode 100644
index 000000000..64ea21371
--- /dev/null
+++ b/tests/MC/AArch64/SVE/ldff1d.s.yaml
@@ -0,0 +1,110 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xff, 0x7f, 0xff, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1d { z31.d }, p7/z, [sp]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x7f, 0xff, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1d { z31.d }, p7/z, [sp]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0xe0, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1d { z0.d }, p0/z, [x0, x0, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xdf, 0xc5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1d { z31.d }, p7/z, [sp, z31.d]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0xe8, 0xc5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1d { z23.d }, p3/z, [x13, z8.d, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x75, 0x95, 0xc5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1d { z21.d }, p5/z, [x10, z21.d, uxtw]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x75, 0xd5, 0xc5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1d { z21.d }, p5/z, [x10, z21.d, sxtw]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0xa0, 0xc5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1d { z0.d }, p0/z, [x0, z0.d, uxtw #3]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0xe0, 0xc5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1d { z0.d }, p0/z, [x0, z0.d, sxtw #3]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xbf, 0xc5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1d { z31.d }, p7/z, [z31.d, #248]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xa0, 0xc5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1d { z0.d }, p0/z, [z0.d]"
diff --git a/tests/MC/AArch64/SVE/ldff1h.s.yaml b/tests/MC/AArch64/SVE/ldff1h.s.yaml
new file mode 100644
index 000000000..378caa3fe
--- /dev/null
+++ b/tests/MC/AArch64/SVE/ldff1h.s.yaml
@@ -0,0 +1,230 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xff, 0x7f, 0xbf, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1h { z31.h }, p7/z, [sp]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x7f, 0xdf, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1h { z31.s }, p7/z, [sp]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x7f, 0xff, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1h { z31.d }, p7/z, [sp]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x7f, 0xbf, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1h { z31.h }, p7/z, [sp]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x7f, 0xdf, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1h { z31.s }, p7/z, [sp]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x7f, 0xff, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1h { z31.d }, p7/z, [sp]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0xa0, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1h { z0.h }, p0/z, [x0, x0, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0xc0, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1h { z0.s }, p0/z, [x0, x0, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0xe0, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1h { z0.d }, p0/z, [x0, x0, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0x80, 0x84 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1h { z0.s }, p0/z, [x0, z0.s, uxtw]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0xc0, 0x84 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1h { z0.s }, p0/z, [x0, z0.s, sxtw]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x7f, 0xbf, 0x84 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1h { z31.s }, p7/z, [sp, z31.s, uxtw #1]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x7f, 0xff, 0x84 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1h { z31.s }, p7/z, [sp, z31.s, sxtw #1]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xdf, 0xc4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1h { z31.d }, p7/z, [sp, z31.d]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0xe8, 0xc4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1h { z23.d }, p3/z, [x13, z8.d, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x75, 0x95, 0xc4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1h { z21.d }, p5/z, [x10, z21.d, uxtw]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x75, 0xd5, 0xc4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1h { z21.d }, p5/z, [x10, z21.d, sxtw]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0xa0, 0xc4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1h { z0.d }, p0/z, [x0, z0.d, uxtw #1]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0xe0, 0xc4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1h { z0.d }, p0/z, [x0, z0.d, sxtw #1]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xbf, 0x84 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1h { z31.s }, p7/z, [z31.s, #62]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xa0, 0x84 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1h { z0.s }, p0/z, [z0.s]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xbf, 0xc4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1h { z31.d }, p7/z, [z31.d, #62]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xa0, 0xc4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1h { z0.d }, p0/z, [z0.d]"
diff --git a/tests/MC/AArch64/SVE/ldff1sb.s.yaml b/tests/MC/AArch64/SVE/ldff1sb.s.yaml
new file mode 100644
index 000000000..031e71d8e
--- /dev/null
+++ b/tests/MC/AArch64/SVE/ldff1sb.s.yaml
@@ -0,0 +1,180 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xff, 0x7f, 0xdf, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1sb { z31.h }, p7/z, [sp]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x7f, 0xbf, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1sb { z31.s }, p7/z, [sp]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x7f, 0x9f, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1sb { z31.d }, p7/z, [sp]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x7f, 0xdf, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1sb { z31.h }, p7/z, [sp]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x7f, 0xbf, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1sb { z31.s }, p7/z, [sp]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x7f, 0x9f, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1sb { z31.d }, p7/z, [sp]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0xc0, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1sb { z0.h }, p0/z, [x0, x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0xa0, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1sb { z0.s }, p0/z, [x0, x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0x80, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1sb { z0.d }, p0/z, [x0, x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x00, 0x84 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1sb { z0.s }, p0/z, [x0, z0.s, uxtw]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x40, 0x84 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1sb { z0.s }, p0/z, [x0, z0.s, sxtw]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x5f, 0xc4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1sb { z31.d }, p7/z, [sp, z31.d]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x35, 0x15, 0xc4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1sb { z21.d }, p5/z, [x10, z21.d, uxtw]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x35, 0x55, 0xc4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1sb { z21.d }, p5/z, [x10, z21.d, sxtw]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x3f, 0x84 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1sb { z31.s }, p7/z, [z31.s, #31]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x20, 0x84 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1sb { z0.s }, p0/z, [z0.s]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x3f, 0xc4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1sb { z31.d }, p7/z, [z31.d, #31]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x20, 0xc4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1sb { z0.d }, p0/z, [z0.d]"
diff --git a/tests/MC/AArch64/SVE/ldff1sh.s.yaml b/tests/MC/AArch64/SVE/ldff1sh.s.yaml
new file mode 100644
index 000000000..88336fd35
--- /dev/null
+++ b/tests/MC/AArch64/SVE/ldff1sh.s.yaml
@@ -0,0 +1,200 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xff, 0x7f, 0x3f, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1sh { z31.s }, p7/z, [sp]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x7f, 0x1f, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1sh { z31.d }, p7/z, [sp]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x7f, 0x3f, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1sh { z31.s }, p7/z, [sp]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x7f, 0x1f, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1sh { z31.d }, p7/z, [sp]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0x20, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1sh { z0.s }, p0/z, [x0, x0, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0x00, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1sh { z0.d }, p0/z, [x0, x0, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x80, 0x84 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1sh { z0.s }, p0/z, [x0, z0.s, uxtw]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0xc0, 0x84 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1sh { z0.s }, p0/z, [x0, z0.s, sxtw]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0xbf, 0x84 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1sh { z31.s }, p7/z, [sp, z31.s, uxtw #1]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0xff, 0x84 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1sh { z31.s }, p7/z, [sp, z31.s, sxtw #1]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0xdf, 0xc4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1sh { z31.d }, p7/z, [sp, z31.d]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xad, 0xe8, 0xc4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1sh { z23.d }, p3/z, [x13, z8.d, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x35, 0x95, 0xc4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1sh { z21.d }, p5/z, [x10, z21.d, uxtw]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x35, 0xd5, 0xc4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1sh { z21.d }, p5/z, [x10, z21.d, sxtw]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0xa0, 0xc4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1sh { z0.d }, p0/z, [x0, z0.d, uxtw #1]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0xe0, 0xc4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1sh { z0.d }, p0/z, [x0, z0.d, sxtw #1]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0xbf, 0x84 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1sh { z31.s }, p7/z, [z31.s, #62]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xa0, 0x84 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1sh { z0.s }, p0/z, [z0.s]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0xbf, 0xc4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1sh { z31.d }, p7/z, [z31.d, #62]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xa0, 0xc4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1sh { z0.d }, p0/z, [z0.d]"
diff --git a/tests/MC/AArch64/SVE/ldff1sw.s.yaml b/tests/MC/AArch64/SVE/ldff1sw.s.yaml
new file mode 100644
index 000000000..0fff6a5fb
--- /dev/null
+++ b/tests/MC/AArch64/SVE/ldff1sw.s.yaml
@@ -0,0 +1,110 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xff, 0x7f, 0x9f, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1sw { z31.d }, p7/z, [sp]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x7f, 0x9f, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1sw { z31.d }, p7/z, [sp]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0x80, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1sw { z0.d }, p0/z, [x0, x0, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x5f, 0xc5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1sw { z31.d }, p7/z, [sp, z31.d]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xad, 0x68, 0xc5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1sw { z23.d }, p3/z, [x13, z8.d, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x35, 0x15, 0xc5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1sw { z21.d }, p5/z, [x10, z21.d, uxtw]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x35, 0x55, 0xc5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1sw { z21.d }, p5/z, [x10, z21.d, sxtw]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x20, 0xc5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1sw { z0.d }, p0/z, [x0, z0.d, uxtw #2]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x60, 0xc5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1sw { z0.d }, p0/z, [x0, z0.d, sxtw #2]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x3f, 0xc5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1sw { z31.d }, p7/z, [z31.d, #124]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x20, 0xc5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1sw { z0.d }, p0/z, [z0.d]"
diff --git a/tests/MC/AArch64/SVE/ldff1w.s.yaml b/tests/MC/AArch64/SVE/ldff1w.s.yaml
new file mode 100644
index 000000000..90dc3cb37
--- /dev/null
+++ b/tests/MC/AArch64/SVE/ldff1w.s.yaml
@@ -0,0 +1,200 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xff, 0x7f, 0x7f, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1w { z31.d }, p7/z, [sp]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x7f, 0x5f, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1w { z31.s }, p7/z, [sp]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x7f, 0x7f, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1w { z31.d }, p7/z, [sp]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x7f, 0x5f, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1w { z31.s }, p7/z, [sp]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0x40, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1w { z0.s }, p0/z, [x0, x0, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0x60, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1w { z0.d }, p0/z, [x0, x0, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0x00, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1w { z0.s }, p0/z, [x0, z0.s, uxtw]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0x40, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1w { z0.s }, p0/z, [x0, z0.s, sxtw]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x7f, 0x3f, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1w { z31.s }, p7/z, [sp, z31.s, uxtw #2]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x7f, 0x7f, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1w { z31.s }, p7/z, [sp, z31.s, sxtw #2]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0x5f, 0xc5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1w { z31.d }, p7/z, [sp, z31.d]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0x68, 0xc5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1w { z23.d }, p3/z, [x13, z8.d, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x75, 0x15, 0xc5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1w { z21.d }, p5/z, [x10, z21.d, uxtw]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x75, 0x55, 0xc5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1w { z21.d }, p5/z, [x10, z21.d, sxtw]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0x20, 0xc5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1w { z0.d }, p0/z, [x0, z0.d, uxtw #2]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0x60, 0xc5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1w { z0.d }, p0/z, [x0, z0.d, sxtw #2]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0x3f, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1w { z31.s }, p7/z, [z31.s, #124]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x20, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1w { z0.s }, p0/z, [z0.s]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0x3f, 0xc5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1w { z31.d }, p7/z, [z31.d, #124]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x20, 0xc5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldff1w { z0.d }, p0/z, [z0.d]"
diff --git a/tests/MC/AArch64/SVE/ldnf1b.s.yaml b/tests/MC/AArch64/SVE/ldnf1b.s.yaml
new file mode 100644
index 000000000..816545dfc
--- /dev/null
+++ b/tests/MC/AArch64/SVE/ldnf1b.s.yaml
@@ -0,0 +1,160 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x10, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnf1b { z0.b }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x30, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnf1b { z0.h }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x50, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnf1b { z0.s }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x70, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnf1b { z0.d }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x10, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnf1b { z0.b }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x30, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnf1b { z0.h }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x50, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnf1b { z0.s }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x70, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnf1b { z0.d }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x1f, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnf1b { z31.b }, p7/z, [sp, #-1, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xb5, 0x15, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnf1b { z21.b }, p5/z, [x10, #5, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x3f, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnf1b { z31.h }, p7/z, [sp, #-1, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xb5, 0x35, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnf1b { z21.h }, p5/z, [x10, #5, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x5f, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnf1b { z31.s }, p7/z, [sp, #-1, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xb5, 0x55, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnf1b { z21.s }, p5/z, [x10, #5, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x7f, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnf1b { z31.d }, p7/z, [sp, #-1, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xb5, 0x75, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnf1b { z21.d }, p5/z, [x10, #5, mul vl]"
diff --git a/tests/MC/AArch64/SVE/ldnf1d.s.yaml b/tests/MC/AArch64/SVE/ldnf1d.s.yaml
new file mode 100644
index 000000000..267310358
--- /dev/null
+++ b/tests/MC/AArch64/SVE/ldnf1d.s.yaml
@@ -0,0 +1,40 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xf0, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnf1d { z0.d }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xf0, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnf1d { z0.d }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0xff, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnf1d { z31.d }, p7/z, [sp, #-1, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xb5, 0xf5, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnf1d { z21.d }, p5/z, [x10, #5, mul vl]"
diff --git a/tests/MC/AArch64/SVE/ldnf1h.s.yaml b/tests/MC/AArch64/SVE/ldnf1h.s.yaml
new file mode 100644
index 000000000..90e241c16
--- /dev/null
+++ b/tests/MC/AArch64/SVE/ldnf1h.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xb0, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnf1h { z0.h }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xd0, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnf1h { z0.s }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xf0, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnf1h { z0.d }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xb0, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnf1h { z0.h }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xd0, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnf1h { z0.s }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xf0, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnf1h { z0.d }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0xbf, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnf1h { z31.h }, p7/z, [sp, #-1, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xb5, 0xb5, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnf1h { z21.h }, p5/z, [x10, #5, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0xdf, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnf1h { z31.s }, p7/z, [sp, #-1, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xb5, 0xd5, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnf1h { z21.s }, p5/z, [x10, #5, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0xff, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnf1h { z31.d }, p7/z, [sp, #-1, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xb5, 0xf5, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnf1h { z21.d }, p5/z, [x10, #5, mul vl]"
diff --git a/tests/MC/AArch64/SVE/ldnf1sb.s.yaml b/tests/MC/AArch64/SVE/ldnf1sb.s.yaml
new file mode 100644
index 000000000..b17778a73
--- /dev/null
+++ b/tests/MC/AArch64/SVE/ldnf1sb.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xd0, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnf1sb { z0.h }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xb0, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnf1sb { z0.s }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x90, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnf1sb { z0.d }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xd0, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnf1sb { z0.h }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xb0, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnf1sb { z0.s }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x90, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnf1sb { z0.d }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0xdf, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnf1sb { z31.h }, p7/z, [sp, #-1, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xb5, 0xd5, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnf1sb { z21.h }, p5/z, [x10, #5, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0xbf, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnf1sb { z31.s }, p7/z, [sp, #-1, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xb5, 0xb5, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnf1sb { z21.s }, p5/z, [x10, #5, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x9f, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnf1sb { z31.d }, p7/z, [sp, #-1, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xb5, 0x95, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnf1sb { z21.d }, p5/z, [x10, #5, mul vl]"
diff --git a/tests/MC/AArch64/SVE/ldnf1sh.s.yaml b/tests/MC/AArch64/SVE/ldnf1sh.s.yaml
new file mode 100644
index 000000000..2e89aac24
--- /dev/null
+++ b/tests/MC/AArch64/SVE/ldnf1sh.s.yaml
@@ -0,0 +1,80 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x30, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnf1sh { z0.s }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x10, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnf1sh { z0.d }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x30, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnf1sh { z0.s }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x10, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnf1sh { z0.d }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x3f, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnf1sh { z31.s }, p7/z, [sp, #-1, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xb5, 0x35, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnf1sh { z21.s }, p5/z, [x10, #5, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x1f, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnf1sh { z31.d }, p7/z, [sp, #-1, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xb5, 0x15, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnf1sh { z21.d }, p5/z, [x10, #5, mul vl]"
diff --git a/tests/MC/AArch64/SVE/ldnf1sw.s.yaml b/tests/MC/AArch64/SVE/ldnf1sw.s.yaml
new file mode 100644
index 000000000..c1ea10dd9
--- /dev/null
+++ b/tests/MC/AArch64/SVE/ldnf1sw.s.yaml
@@ -0,0 +1,40 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x90, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnf1sw { z0.d }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x90, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnf1sw { z0.d }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x9f, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnf1sw { z31.d }, p7/z, [sp, #-1, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xb5, 0x95, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnf1sw { z21.d }, p5/z, [x10, #5, mul vl]"
diff --git a/tests/MC/AArch64/SVE/ldnf1w.s.yaml b/tests/MC/AArch64/SVE/ldnf1w.s.yaml
new file mode 100644
index 000000000..8d2c3567a
--- /dev/null
+++ b/tests/MC/AArch64/SVE/ldnf1w.s.yaml
@@ -0,0 +1,80 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x50, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnf1w { z0.s }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x70, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnf1w { z0.d }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x50, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnf1w { z0.s }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x70, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnf1w { z0.d }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x5f, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnf1w { z31.s }, p7/z, [sp, #-1, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xb5, 0x55, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnf1w { z21.s }, p5/z, [x10, #5, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x7f, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnf1w { z31.d }, p7/z, [sp, #-1, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xb5, 0x75, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnf1w { z21.d }, p5/z, [x10, #5, mul vl]"
diff --git a/tests/MC/AArch64/SVE/ldnt1b.s.yaml b/tests/MC/AArch64/SVE/ldnt1b.s.yaml
new file mode 100644
index 000000000..61d5354e3
--- /dev/null
+++ b/tests/MC/AArch64/SVE/ldnt1b.s.yaml
@@ -0,0 +1,100 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x00, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1b { z0.b }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x00, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1b { z0.b }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0x08, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1b { z23.b }, p3/z, [x13, #-8, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf5, 0x07, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1b { z21.b }, p5/z, [x10, #7, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x00, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1b { z0.b }, p0/z, [x0, x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x00, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1b { z0.b }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x00, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1b { z0.b }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0x08, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1b { z23.b }, p3/z, [x13, #-8, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf5, 0x07, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1b { z21.b }, p5/z, [x10, #7, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x00, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1b { z0.b }, p0/z, [x0, x0]"
diff --git a/tests/MC/AArch64/SVE/ldnt1d.s.yaml b/tests/MC/AArch64/SVE/ldnt1d.s.yaml
new file mode 100644
index 000000000..4902dedfc
--- /dev/null
+++ b/tests/MC/AArch64/SVE/ldnt1d.s.yaml
@@ -0,0 +1,100 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x80, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1d { z0.d }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x80, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1d { z0.d }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0x88, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1d { z23.d }, p3/z, [x13, #-8, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf5, 0x87, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1d { z21.d }, p5/z, [x10, #7, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x80, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1d { z0.d }, p0/z, [x0, x0, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x80, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1d { z0.d }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x80, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1d { z0.d }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0x88, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1d { z23.d }, p3/z, [x13, #-8, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf5, 0x87, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1d { z21.d }, p5/z, [x10, #7, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x80, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1d { z0.d }, p0/z, [x0, x0, lsl #3]"
diff --git a/tests/MC/AArch64/SVE/ldnt1h.s.yaml b/tests/MC/AArch64/SVE/ldnt1h.s.yaml
new file mode 100644
index 000000000..98630dc2d
--- /dev/null
+++ b/tests/MC/AArch64/SVE/ldnt1h.s.yaml
@@ -0,0 +1,100 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x80, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1h { z0.h }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x80, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1h { z0.h }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0x88, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1h { z23.h }, p3/z, [x13, #-8, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf5, 0x87, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1h { z21.h }, p5/z, [x10, #7, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x80, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1h { z0.h }, p0/z, [x0, x0, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x80, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1h { z0.h }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x80, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1h { z0.h }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0x88, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1h { z23.h }, p3/z, [x13, #-8, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf5, 0x87, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1h { z21.h }, p5/z, [x10, #7, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x80, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1h { z0.h }, p0/z, [x0, x0, lsl #1]"
diff --git a/tests/MC/AArch64/SVE/ldnt1w.s.yaml b/tests/MC/AArch64/SVE/ldnt1w.s.yaml
new file mode 100644
index 000000000..2d8bfa11d
--- /dev/null
+++ b/tests/MC/AArch64/SVE/ldnt1w.s.yaml
@@ -0,0 +1,100 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x00, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1w { z0.s }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x00, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1w { z0.s }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0x08, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1w { z23.s }, p3/z, [x13, #-8, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf5, 0x07, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1w { z21.s }, p5/z, [x10, #7, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x00, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1w { z0.s }, p0/z, [x0, x0, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x00, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1w { z0.s }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x00, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1w { z0.s }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0x08, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1w { z23.s }, p3/z, [x13, #-8, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf5, 0x07, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1w { z21.s }, p5/z, [x10, #7, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x00, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1w { z0.s }, p0/z, [x0, x0, lsl #2]"
diff --git a/tests/MC/AArch64/SVE/ldr.s.yaml b/tests/MC/AArch64/SVE/ldr.s.yaml
new file mode 100644
index 000000000..357cf708e
--- /dev/null
+++ b/tests/MC/AArch64/SVE/ldr.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0x80, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr z0, [x0]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x43, 0xa0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr z31, [sp, #-256, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x5d, 0x9f, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr z23, [x13, #255, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x80, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0xa7, 0x01, 0xa0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr p7, [x13, #-256, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x45, 0x1d, 0x9f, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr p5, [x10, #255, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0x80, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr z0, [x0]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x43, 0xa0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr z31, [sp, #-256, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x5d, 0x9f, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr z23, [x13, #255, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x80, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0xa7, 0x01, 0xa0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr p7, [x13, #-256, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x45, 0x1d, 0x9f, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr p5, [x10, #255, mul vl]"
diff --git a/tests/MC/AArch64/SVE/lsl.s.yaml b/tests/MC/AArch64/SVE/lsl.s.yaml
new file mode 100644
index 000000000..162f2c6e3
--- /dev/null
+++ b/tests/MC/AArch64/SVE/lsl.s.yaml
@@ -0,0 +1,680 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x9c, 0x28, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsl z0.b, z0.b, #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0x9f, 0x2f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsl z31.b, z31.b, #7"
+
+  -
+    input:
+      bytes: [ 0x00, 0x9c, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsl z0.h, z0.h, #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0x9f, 0x3f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsl z31.h, z31.h, #15"
+
+  -
+    input:
+      bytes: [ 0x00, 0x9c, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsl z0.s, z0.s, #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0x9f, 0x7f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsl z31.s, z31.s, #31"
+
+  -
+    input:
+      bytes: [ 0x00, 0x9c, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsl z0.d, z0.d, #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0x9f, 0xff, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsl z31.d, z31.d, #63"
+
+  -
+    input:
+      bytes: [ 0x00, 0x81, 0x03, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsl z0.b, p0/m, z0.b, #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0x81, 0x03, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsl z31.b, p0/m, z31.b, #7"
+
+  -
+    input:
+      bytes: [ 0x00, 0x82, 0x03, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsl z0.h, p0/m, z0.h, #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0x83, 0x03, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsl z31.h, p0/m, z31.h, #15"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x43, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsl z0.s, p0/m, z0.s, #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0x83, 0x43, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsl z31.s, p0/m, z31.s, #31"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x83, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsl z0.d, p0/m, z0.d, #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0x83, 0xc3, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsl z31.d, p0/m, z31.d, #63"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x13, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsl z0.b, p0/m, z0.b, z0.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x53, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsl z0.h, p0/m, z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x93, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsl z0.s, p0/m, z0.s, z0.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xd3, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsl z0.d, p0/m, z0.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x1b, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsl z0.b, p0/m, z0.b, z1.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x5b, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsl z0.h, p0/m, z0.h, z1.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x9b, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsl z0.s, p0/m, z0.s, z1.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x8c, 0x22, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsl z0.b, z1.b, z2.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x8c, 0x62, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsl z0.h, z1.h, z2.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x8c, 0xa2, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsl z0.s, z1.s, z2.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31.d, p0/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0x83, 0xc3, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsl z31.d, p0/m, z31.d, #63"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xff, 0x83, 0xc3, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsl z31.d, p0/m, z31.d, #63"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x20, 0x90, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0.s, p0/z, z7.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x9b, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsl z0.s, p0/m, z0.s, z1.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x9b, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsl z0.s, p0/m, z0.s, z1.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x9c, 0x28, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsl z0.b, z0.b, #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0x9f, 0x2f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsl z31.b, z31.b, #7"
+
+  -
+    input:
+      bytes: [ 0x00, 0x9c, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsl z0.h, z0.h, #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0x9f, 0x3f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsl z31.h, z31.h, #15"
+
+  -
+    input:
+      bytes: [ 0x00, 0x9c, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsl z0.s, z0.s, #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0x9f, 0x7f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsl z31.s, z31.s, #31"
+
+  -
+    input:
+      bytes: [ 0x00, 0x9c, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsl z0.d, z0.d, #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0x9f, 0xff, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsl z31.d, z31.d, #63"
+
+  -
+    input:
+      bytes: [ 0x00, 0x81, 0x03, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsl z0.b, p0/m, z0.b, #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0x81, 0x03, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsl z31.b, p0/m, z31.b, #7"
+
+  -
+    input:
+      bytes: [ 0x00, 0x82, 0x03, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsl z0.h, p0/m, z0.h, #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0x83, 0x03, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsl z31.h, p0/m, z31.h, #15"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x43, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsl z0.s, p0/m, z0.s, #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0x83, 0x43, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsl z31.s, p0/m, z31.s, #31"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x83, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsl z0.d, p0/m, z0.d, #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0x83, 0xc3, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsl z31.d, p0/m, z31.d, #63"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x13, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsl z0.b, p0/m, z0.b, z0.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x53, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsl z0.h, p0/m, z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x93, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsl z0.s, p0/m, z0.s, z0.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xd3, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsl z0.d, p0/m, z0.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x1b, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsl z0.b, p0/m, z0.b, z1.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x5b, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsl z0.h, p0/m, z0.h, z1.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x9b, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsl z0.s, p0/m, z0.s, z1.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x8c, 0x22, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsl z0.b, z1.b, z2.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x8c, 0x62, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsl z0.h, z1.h, z2.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x8c, 0xa2, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsl z0.s, z1.s, z2.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31.d, p0/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0x83, 0xc3, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsl z31.d, p0/m, z31.d, #63"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xff, 0x83, 0xc3, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsl z31.d, p0/m, z31.d, #63"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x20, 0x90, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0.s, p0/z, z7.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x9b, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsl z0.s, p0/m, z0.s, z1.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x9b, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsl z0.s, p0/m, z0.s, z1.d"
diff --git a/tests/MC/AArch64/SVE/lslr.s.yaml b/tests/MC/AArch64/SVE/lslr.s.yaml
new file mode 100644
index 000000000..535d90492
--- /dev/null
+++ b/tests/MC/AArch64/SVE/lslr.s.yaml
@@ -0,0 +1,160 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x17, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "lslr z0.b, p0/m, z0.b, z0.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x57, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "lslr z0.h, p0/m, z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x97, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "lslr z0.s, p0/m, z0.s, z0.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xd7, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "lslr z0.d, p0/m, z0.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0xe5, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z5.d, p0/z, z7.d"
+
+  -
+    input:
+      bytes: [ 0x05, 0x80, 0xd7, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "lslr z5.d, p0/m, z5.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0xe5, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z5, z7"
+
+  -
+    input:
+      bytes: [ 0x05, 0x80, 0xd7, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "lslr z5.d, p0/m, z5.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x17, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "lslr z0.b, p0/m, z0.b, z0.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x57, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "lslr z0.h, p0/m, z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x97, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "lslr z0.s, p0/m, z0.s, z0.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xd7, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "lslr z0.d, p0/m, z0.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0xe5, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z5.d, p0/z, z7.d"
+
+  -
+    input:
+      bytes: [ 0x05, 0x80, 0xd7, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "lslr z5.d, p0/m, z5.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0xe5, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z5, z7"
+
+  -
+    input:
+      bytes: [ 0x05, 0x80, 0xd7, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "lslr z5.d, p0/m, z5.d, z0.d"
diff --git a/tests/MC/AArch64/SVE/lsr.s.yaml b/tests/MC/AArch64/SVE/lsr.s.yaml
new file mode 100644
index 000000000..a24fe6bb0
--- /dev/null
+++ b/tests/MC/AArch64/SVE/lsr.s.yaml
@@ -0,0 +1,680 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x94, 0x2f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsr z0.b, z0.b, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x97, 0x28, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsr z31.b, z31.b, #8"
+
+  -
+    input:
+      bytes: [ 0x00, 0x94, 0x3f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsr z0.h, z0.h, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x97, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsr z31.h, z31.h, #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0x94, 0x7f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsr z0.s, z0.s, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x97, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsr z31.s, z31.s, #32"
+
+  -
+    input:
+      bytes: [ 0x00, 0x94, 0xff, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsr z0.d, z0.d, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x97, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsr z31.d, z31.d, #64"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x81, 0x01, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsr z0.b, p0/m, z0.b, #1"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x81, 0x01, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsr z31.b, p0/m, z31.b, #8"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x83, 0x01, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsr z0.h, p0/m, z0.h, #1"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x82, 0x01, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsr z31.h, p0/m, z31.h, #16"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x83, 0x41, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsr z0.s, p0/m, z0.s, #1"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x80, 0x41, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsr z31.s, p0/m, z31.s, #32"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x83, 0xc1, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsr z0.d, p0/m, z0.d, #1"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x80, 0x81, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsr z31.d, p0/m, z31.d, #64"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x11, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsr z0.b, p0/m, z0.b, z0.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x51, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsr z0.h, p0/m, z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x91, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsr z0.s, p0/m, z0.s, z0.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xd1, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsr z0.d, p0/m, z0.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x19, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsr z0.b, p0/m, z0.b, z1.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x59, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsr z0.h, p0/m, z0.h, z1.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x99, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsr z0.s, p0/m, z0.s, z1.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x84, 0x22, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsr z0.b, z1.b, z2.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x84, 0x62, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsr z0.h, z1.h, z2.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x84, 0xa2, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsr z0.s, z1.s, z2.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31.d, p0/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x80, 0x81, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsr z31.d, p0/m, z31.d, #64"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x80, 0x81, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsr z31.d, p0/m, z31.d, #64"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x20, 0x90, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0.s, p0/z, z7.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x99, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsr z0.s, p0/m, z0.s, z1.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x99, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsr z0.s, p0/m, z0.s, z1.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x94, 0x2f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsr z0.b, z0.b, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x97, 0x28, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsr z31.b, z31.b, #8"
+
+  -
+    input:
+      bytes: [ 0x00, 0x94, 0x3f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsr z0.h, z0.h, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x97, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsr z31.h, z31.h, #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0x94, 0x7f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsr z0.s, z0.s, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x97, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsr z31.s, z31.s, #32"
+
+  -
+    input:
+      bytes: [ 0x00, 0x94, 0xff, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsr z0.d, z0.d, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x97, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsr z31.d, z31.d, #64"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x81, 0x01, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsr z0.b, p0/m, z0.b, #1"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x81, 0x01, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsr z31.b, p0/m, z31.b, #8"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x83, 0x01, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsr z0.h, p0/m, z0.h, #1"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x82, 0x01, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsr z31.h, p0/m, z31.h, #16"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x83, 0x41, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsr z0.s, p0/m, z0.s, #1"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x80, 0x41, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsr z31.s, p0/m, z31.s, #32"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x83, 0xc1, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsr z0.d, p0/m, z0.d, #1"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x80, 0x81, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsr z31.d, p0/m, z31.d, #64"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x11, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsr z0.b, p0/m, z0.b, z0.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x51, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsr z0.h, p0/m, z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x91, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsr z0.s, p0/m, z0.s, z0.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xd1, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsr z0.d, p0/m, z0.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x19, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsr z0.b, p0/m, z0.b, z1.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x59, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsr z0.h, p0/m, z0.h, z1.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x99, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsr z0.s, p0/m, z0.s, z1.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x84, 0x22, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsr z0.b, z1.b, z2.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x84, 0x62, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsr z0.h, z1.h, z2.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x84, 0xa2, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsr z0.s, z1.s, z2.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31.d, p0/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x80, 0x81, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsr z31.d, p0/m, z31.d, #64"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x80, 0x81, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsr z31.d, p0/m, z31.d, #64"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x20, 0x90, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0.s, p0/z, z7.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x99, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsr z0.s, p0/m, z0.s, z1.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x99, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsr z0.s, p0/m, z0.s, z1.d"
diff --git a/tests/MC/AArch64/SVE/lsrr.s.yaml b/tests/MC/AArch64/SVE/lsrr.s.yaml
new file mode 100644
index 000000000..0ea0f06d4
--- /dev/null
+++ b/tests/MC/AArch64/SVE/lsrr.s.yaml
@@ -0,0 +1,160 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x15, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsrr z0.b, p0/m, z0.b, z0.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x55, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsrr z0.h, p0/m, z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x95, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsrr z0.s, p0/m, z0.s, z0.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xd5, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsrr z0.d, p0/m, z0.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0xe5, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z5.d, p0/z, z7.d"
+
+  -
+    input:
+      bytes: [ 0x05, 0x80, 0xd5, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsrr z5.d, p0/m, z5.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0xe5, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z5, z7"
+
+  -
+    input:
+      bytes: [ 0x05, 0x80, 0xd5, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsrr z5.d, p0/m, z5.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x15, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsrr z0.b, p0/m, z0.b, z0.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x55, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsrr z0.h, p0/m, z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x95, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsrr z0.s, p0/m, z0.s, z0.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xd5, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsrr z0.d, p0/m, z0.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0xe5, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z5.d, p0/z, z7.d"
+
+  -
+    input:
+      bytes: [ 0x05, 0x80, 0xd5, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsrr z5.d, p0/m, z5.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0xe5, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z5, z7"
+
+  -
+    input:
+      bytes: [ 0x05, 0x80, 0xd5, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsrr z5.d, p0/m, z5.d, z0.d"
diff --git a/tests/MC/AArch64/SVE/mad.s.yaml b/tests/MC/AArch64/SVE/mad.s.yaml
new file mode 100644
index 000000000..75a3c986d
--- /dev/null
+++ b/tests/MC/AArch64/SVE/mad.s.yaml
@@ -0,0 +1,160 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xe0, 0xdf, 0x01, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mad z0.b, p7/m, z1.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xdf, 0x41, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mad z0.h, p7/m, z1.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xdf, 0x81, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mad z0.s, p7/m, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xdf, 0xc1, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mad z0.d, p7/m, z1.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0.d, p7/z, z7.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xdf, 0xc1, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mad z0.d, p7/m, z1.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xdf, 0xc1, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mad z0.d, p7/m, z1.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xdf, 0x01, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mad z0.b, p7/m, z1.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xdf, 0x41, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mad z0.h, p7/m, z1.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xdf, 0x81, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mad z0.s, p7/m, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xdf, 0xc1, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mad z0.d, p7/m, z1.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0.d, p7/z, z7.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xdf, 0xc1, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mad z0.d, p7/m, z1.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xdf, 0xc1, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mad z0.d, p7/m, z1.d, z31.d"
diff --git a/tests/MC/AArch64/SVE/matrix-multiply-fp32.s.yaml b/tests/MC/AArch64/SVE/matrix-multiply-fp32.s.yaml
new file mode 100644
index 000000000..c4b09f55b
--- /dev/null
+++ b/tests/MC/AArch64/SVE/matrix-multiply-fp32.s.yaml
@@ -0,0 +1,10 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0xe4, 0xa2, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+f32mm" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmmla z0.s, z1.s, z2.s"
diff --git a/tests/MC/AArch64/SVE/matrix-multiply-fp64.s.yaml b/tests/MC/AArch64/SVE/matrix-multiply-fp64.s.yaml
new file mode 100644
index 000000000..3235120c3
--- /dev/null
+++ b/tests/MC/AArch64/SVE/matrix-multiply-fp64.s.yaml
@@ -0,0 +1,390 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0xe4, 0xe2, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+f64mm" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmmla z0.d, z1.d, z2.d"
+
+  -
+    input:
+      bytes: [ 0x40, 0x24, 0x27, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+f64mm" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rob { z0.b }, p1/z, [x2, #224]"
+
+  -
+    input:
+      bytes: [ 0x40, 0x24, 0xa7, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+f64mm" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1roh { z0.h }, p1/z, [x2, #224]"
+
+  -
+    input:
+      bytes: [ 0x40, 0x24, 0x27, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+f64mm" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1row { z0.s }, p1/z, [x2, #224]"
+
+  -
+    input:
+      bytes: [ 0x40, 0x24, 0xa7, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+f64mm" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rod { z0.d }, p1/z, [x2, #224]"
+
+  -
+    input:
+      bytes: [ 0x40, 0x24, 0x28, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+f64mm" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rob { z0.b }, p1/z, [x2, #-256]"
+
+  -
+    input:
+      bytes: [ 0x40, 0x24, 0xa8, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+f64mm" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1roh { z0.h }, p1/z, [x2, #-256]"
+
+  -
+    input:
+      bytes: [ 0x40, 0x24, 0x28, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+f64mm" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1row { z0.s }, p1/z, [x2, #-256]"
+
+  -
+    input:
+      bytes: [ 0x40, 0x24, 0xa8, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+f64mm" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rod { z0.d }, p1/z, [x2, #-256]"
+
+  -
+    input:
+      bytes: [ 0x40, 0x24, 0x20, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+f64mm" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rob { z0.b }, p1/z, [x2]"
+
+  -
+    input:
+      bytes: [ 0x40, 0x24, 0xa0, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+f64mm" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1roh { z0.h }, p1/z, [x2]"
+
+  -
+    input:
+      bytes: [ 0x40, 0x24, 0x20, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+f64mm" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1row { z0.s }, p1/z, [x2]"
+
+  -
+    input:
+      bytes: [ 0x40, 0x24, 0xa0, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+f64mm" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rod { z0.d }, p1/z, [x2]"
+
+  -
+    input:
+      bytes: [ 0x40, 0x24, 0x20, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+f64mm" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rob { z0.b }, p1/z, [x2]"
+
+  -
+    input:
+      bytes: [ 0x40, 0x24, 0xa0, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+f64mm" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1roh { z0.h }, p1/z, [x2]"
+
+  -
+    input:
+      bytes: [ 0x40, 0x24, 0x20, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+f64mm" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1row { z0.s }, p1/z, [x2]"
+
+  -
+    input:
+      bytes: [ 0x40, 0x24, 0xa0, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+f64mm" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rod { z0.d }, p1/z, [x2]"
+
+  -
+    input:
+      bytes: [ 0x40, 0x24, 0x27, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+f64mm" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rob { z0.b }, p1/z, [x2, #224]"
+
+  -
+    input:
+      bytes: [ 0x40, 0x24, 0xa7, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+f64mm" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1roh { z0.h }, p1/z, [x2, #224]"
+
+  -
+    input:
+      bytes: [ 0x40, 0x24, 0x27, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+f64mm" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1row { z0.s }, p1/z, [x2, #224]"
+
+  -
+    input:
+      bytes: [ 0x40, 0x24, 0xa7, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+f64mm" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rod { z0.d }, p1/z, [x2, #224]"
+
+  -
+    input:
+      bytes: [ 0x40, 0x24, 0x28, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+f64mm" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rob { z0.b }, p1/z, [x2, #-256]"
+
+  -
+    input:
+      bytes: [ 0x40, 0x24, 0xa8, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+f64mm" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1roh { z0.h }, p1/z, [x2, #-256]"
+
+  -
+    input:
+      bytes: [ 0x40, 0x24, 0x28, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+f64mm" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1row { z0.s }, p1/z, [x2, #-256]"
+
+  -
+    input:
+      bytes: [ 0x40, 0x24, 0xa8, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+f64mm" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rod { z0.d }, p1/z, [x2, #-256]"
+
+  -
+    input:
+      bytes: [ 0x40, 0x04, 0x23, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+f64mm" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rob { z0.b }, p1/z, [x2, x3]"
+
+  -
+    input:
+      bytes: [ 0x40, 0x04, 0xa3, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+f64mm" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1roh { z0.h }, p1/z, [x2, x3, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x40, 0x04, 0x23, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+f64mm" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1row { z0.s }, p1/z, [x2, x3, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x40, 0x04, 0xa3, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+f64mm" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rod { z0.d }, p1/z, [x2, x3, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x40, 0x04, 0x23, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+f64mm" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rob { z0.b }, p1/z, [x2, x3]"
+
+  -
+    input:
+      bytes: [ 0x40, 0x04, 0xa3, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+f64mm" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1roh { z0.h }, p1/z, [x2, x3, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x40, 0x04, 0x23, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+f64mm" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1row { z0.s }, p1/z, [x2, x3, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x40, 0x04, 0xa3, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+f64mm" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1rod { z0.d }, p1/z, [x2, x3, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x00, 0xa2, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+f64mm" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip1 z0.q, z1.q, z2.q"
+
+  -
+    input:
+      bytes: [ 0x20, 0x04, 0xa2, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+f64mm" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip2 z0.q, z1.q, z2.q"
+
+  -
+    input:
+      bytes: [ 0x20, 0x08, 0xa2, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+f64mm" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzp1 z0.q, z1.q, z2.q"
+
+  -
+    input:
+      bytes: [ 0x20, 0x0c, 0xa2, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+f64mm" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzp2 z0.q, z1.q, z2.q"
+
+  -
+    input:
+      bytes: [ 0x20, 0x18, 0xa2, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+f64mm" ]
+    expected:
+      insns:
+        -
+          asm_text: "trn1 z0.q, z1.q, z2.q"
+
+  -
+    input:
+      bytes: [ 0x20, 0x1c, 0xa2, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+f64mm" ]
+    expected:
+      insns:
+        -
+          asm_text: "trn2 z0.q, z1.q, z2.q"
diff --git a/tests/MC/AArch64/SVE/matrix-multiply-int8.s.yaml b/tests/MC/AArch64/SVE/matrix-multiply-int8.s.yaml
new file mode 100644
index 000000000..729ee9650
--- /dev/null
+++ b/tests/MC/AArch64/SVE/matrix-multiply-int8.s.yaml
@@ -0,0 +1,180 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x98, 0xc2, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+i8mm" ]
+    expected:
+      insns:
+        -
+          asm_text: "ummla z0.s, z1.b, z2.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x98, 0x02, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+i8mm" ]
+    expected:
+      insns:
+        -
+          asm_text: "smmla z0.s, z1.b, z2.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x98, 0x82, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+i8mm" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmmla z0.s, z1.b, z2.b"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+i8mm" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x20, 0x98, 0xc2, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+i8mm" ]
+    expected:
+      insns:
+        -
+          asm_text: "ummla z0.s, z1.b, z2.b"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+i8mm" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x20, 0x98, 0x02, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+i8mm" ]
+    expected:
+      insns:
+        -
+          asm_text: "smmla z0.s, z1.b, z2.b"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+i8mm" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x20, 0x98, 0x82, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+i8mm" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmmla z0.s, z1.b, z2.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x78, 0x82, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+i8mm" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot z0.s, z1.b, z2.b"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+i8mm" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x20, 0x78, 0x82, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+i8mm" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot z0.s, z1.b, z2.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x18, 0xa2, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+i8mm" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot z0.s, z1.b, z2.b[0]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x1c, 0xba, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+i8mm" ]
+    expected:
+      insns:
+        -
+          asm_text: "sudot z0.s, z1.b, z2.b[3]"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+i8mm" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x20, 0x18, 0xa2, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+i8mm" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot z0.s, z1.b, z2.b[0]"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+i8mm" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x20, 0x1c, 0xa2, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve", "+i8mm" ]
+    expected:
+      insns:
+        -
+          asm_text: "sudot z0.s, z1.b, z2.b[0]"
diff --git a/tests/MC/AArch64/SVE/mla.s.yaml b/tests/MC/AArch64/SVE/mla.s.yaml
new file mode 100644
index 000000000..034a798e4
--- /dev/null
+++ b/tests/MC/AArch64/SVE/mla.s.yaml
@@ -0,0 +1,160 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x5c, 0x1f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mla z0.b, p7/m, z1.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x5c, 0x5f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mla z0.h, p7/m, z1.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x5c, 0x9f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mla z0.s, p7/m, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x5c, 0xdf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mla z0.d, p7/m, z1.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0.d, p7/z, z7.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x5c, 0xdf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mla z0.d, p7/m, z1.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x20, 0x5c, 0xdf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mla z0.d, p7/m, z1.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x5c, 0x1f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mla z0.b, p7/m, z1.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x5c, 0x5f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mla z0.h, p7/m, z1.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x5c, 0x9f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mla z0.s, p7/m, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x5c, 0xdf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mla z0.d, p7/m, z1.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0.d, p7/z, z7.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x5c, 0xdf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mla z0.d, p7/m, z1.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x20, 0x5c, 0xdf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mla z0.d, p7/m, z1.d, z31.d"
diff --git a/tests/MC/AArch64/SVE/mls.s.yaml b/tests/MC/AArch64/SVE/mls.s.yaml
new file mode 100644
index 000000000..1068ae7e3
--- /dev/null
+++ b/tests/MC/AArch64/SVE/mls.s.yaml
@@ -0,0 +1,160 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x7c, 0x1f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mls z0.b, p7/m, z1.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x7c, 0x5f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mls z0.h, p7/m, z1.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x7c, 0x9f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mls z0.s, p7/m, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x7c, 0xdf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mls z0.d, p7/m, z1.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0.d, p7/z, z7.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x7c, 0xdf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mls z0.d, p7/m, z1.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x20, 0x7c, 0xdf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mls z0.d, p7/m, z1.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x7c, 0x1f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mls z0.b, p7/m, z1.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x7c, 0x5f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mls z0.h, p7/m, z1.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x7c, 0x9f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mls z0.s, p7/m, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x7c, 0xdf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mls z0.d, p7/m, z1.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0.d, p7/z, z7.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x7c, 0xdf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mls z0.d, p7/m, z1.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x20, 0x7c, 0xdf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mls z0.d, p7/m, z1.d, z31.d"
diff --git a/tests/MC/AArch64/SVE/mov.s.yaml b/tests/MC/AArch64/SVE/mov.s.yaml
new file mode 100644
index 000000000..e2ca5060b
--- /dev/null
+++ b/tests/MC/AArch64/SVE/mov.s.yaml
@@ -0,0 +1,2580 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x38, 0x20, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.b, w0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x38, 0x60, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.h, w0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x38, 0xa0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.s, w0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x38, 0xe0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.d, x0"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3b, 0x60, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z31.h, wsp"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3b, 0xa0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z31.s, wsp"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3b, 0xe0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z31.d, sp"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3b, 0x20, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z31.b, wsp"
+
+  -
+    input:
+      bytes: [ 0x00, 0x30, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x30, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z31.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0x05, 0xd0, 0x38, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z5.b, #-128"
+
+  -
+    input:
+      bytes: [ 0xe5, 0xcf, 0x38, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z5.b, #127"
+
+  -
+    input:
+      bytes: [ 0xe5, 0xdf, 0x38, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z5.b, #-1"
+
+  -
+    input:
+      bytes: [ 0x15, 0xd0, 0x78, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.h, #-128"
+
+  -
+    input:
+      bytes: [ 0x15, 0xf0, 0x78, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.h, #-32768"
+
+  -
+    input:
+      bytes: [ 0x15, 0xf0, 0x78, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.h, #-32768"
+
+  -
+    input:
+      bytes: [ 0xf5, 0xcf, 0x78, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.h, #127"
+
+  -
+    input:
+      bytes: [ 0xf5, 0xef, 0x78, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.h, #32512"
+
+  -
+    input:
+      bytes: [ 0xf5, 0xef, 0x78, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.h, #32512"
+
+  -
+    input:
+      bytes: [ 0x15, 0xd0, 0xb8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.s, #-128"
+
+  -
+    input:
+      bytes: [ 0x15, 0xf0, 0xb8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.s, #-32768"
+
+  -
+    input:
+      bytes: [ 0x15, 0xf0, 0xb8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.s, #-32768"
+
+  -
+    input:
+      bytes: [ 0xf5, 0xcf, 0xb8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.s, #127"
+
+  -
+    input:
+      bytes: [ 0xf5, 0xef, 0xb8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.s, #32512"
+
+  -
+    input:
+      bytes: [ 0xf5, 0xef, 0xb8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.s, #32512"
+
+  -
+    input:
+      bytes: [ 0x15, 0xd0, 0xf8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.d, #-128"
+
+  -
+    input:
+      bytes: [ 0x15, 0xf0, 0xf8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.d, #-32768"
+
+  -
+    input:
+      bytes: [ 0x15, 0xf0, 0xf8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.d, #-32768"
+
+  -
+    input:
+      bytes: [ 0xf5, 0xcf, 0xf8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.d, #127"
+
+  -
+    input:
+      bytes: [ 0xf5, 0xef, 0xf8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.d, #32512"
+
+  -
+    input:
+      bytes: [ 0xf5, 0xef, 0xf8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.d, #32512"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf0, 0x78, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.h, #-32768"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xff, 0x78, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.h, #-256"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xef, 0x78, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.h, #32512"
+
+  -
+    input:
+      bytes: [ 0xc0, 0x05, 0xc0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.h, #32767"
+
+  -
+    input:
+      bytes: [ 0xc0, 0x83, 0xc0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.s, #0xffff7fff"
+
+  -
+    input:
+      bytes: [ 0x00, 0x88, 0xc0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.s, #32768"
+
+  -
+    input:
+      bytes: [ 0xc0, 0x87, 0xc3, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.d, #0xffffffffffff7fff"
+
+  -
+    input:
+      bytes: [ 0x00, 0x88, 0xc3, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.d, #32768"
+
+  -
+    input:
+      bytes: [ 0x80, 0x19, 0xc2, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.d, #0xe0000000000003ff"
+
+  -
+    input:
+      bytes: [ 0x05, 0x10, 0x10, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z5.b, p0/z, #-128"
+
+  -
+    input:
+      bytes: [ 0xe5, 0x0f, 0x10, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z5.b, p0/z, #127"
+
+  -
+    input:
+      bytes: [ 0xe5, 0x1f, 0x10, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z5.b, p0/z, #-1"
+
+  -
+    input:
+      bytes: [ 0x15, 0x10, 0x50, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.h, p0/z, #-128"
+
+  -
+    input:
+      bytes: [ 0x15, 0x30, 0x50, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.h, p0/z, #-32768"
+
+  -
+    input:
+      bytes: [ 0x15, 0x30, 0x50, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.h, p0/z, #-32768"
+
+  -
+    input:
+      bytes: [ 0xf5, 0x0f, 0x50, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.h, p0/z, #127"
+
+  -
+    input:
+      bytes: [ 0xf5, 0x2f, 0x50, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.h, p0/z, #32512"
+
+  -
+    input:
+      bytes: [ 0xf5, 0x2f, 0x50, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.h, p0/z, #32512"
+
+  -
+    input:
+      bytes: [ 0x15, 0x10, 0x90, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.s, p0/z, #-128"
+
+  -
+    input:
+      bytes: [ 0x15, 0x30, 0x90, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.s, p0/z, #-32768"
+
+  -
+    input:
+      bytes: [ 0x15, 0x30, 0x90, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.s, p0/z, #-32768"
+
+  -
+    input:
+      bytes: [ 0xf5, 0x0f, 0x90, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.s, p0/z, #127"
+
+  -
+    input:
+      bytes: [ 0xf5, 0x2f, 0x90, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.s, p0/z, #32512"
+
+  -
+    input:
+      bytes: [ 0xf5, 0x2f, 0x90, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.s, p0/z, #32512"
+
+  -
+    input:
+      bytes: [ 0x15, 0x10, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.d, p0/z, #-128"
+
+  -
+    input:
+      bytes: [ 0x15, 0x30, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.d, p0/z, #-32768"
+
+  -
+    input:
+      bytes: [ 0x15, 0x30, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.d, p0/z, #-32768"
+
+  -
+    input:
+      bytes: [ 0xf5, 0x0f, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.d, p0/z, #127"
+
+  -
+    input:
+      bytes: [ 0xf5, 0x2f, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.d, p0/z, #32512"
+
+  -
+    input:
+      bytes: [ 0xf5, 0x2f, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.d, p0/z, #32512"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xcf, 0x38, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.b, #127"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xef, 0x78, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.h, #32512"
+
+  -
+    input:
+      bytes: [ 0x45, 0xdf, 0x78, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z5.h, #-6"
+
+  -
+    input:
+      bytes: [ 0x45, 0xdf, 0xb8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z5.s, #-6"
+
+  -
+    input:
+      bytes: [ 0x45, 0xdf, 0xf8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z5.d, #-6"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x0f, 0x10, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.b, p0/z, #127"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x2f, 0x50, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.h, p0/z, #32512"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x2f, 0x50, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.h, p0/z, #32512"
+
+  -
+    input:
+      bytes: [ 0x05, 0x50, 0x1f, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z5.b, p15/m, #-128"
+
+  -
+    input:
+      bytes: [ 0x15, 0x50, 0x5f, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.h, p15/m, #-128"
+
+  -
+    input:
+      bytes: [ 0x15, 0x70, 0x5f, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.h, p15/m, #-32768"
+
+  -
+    input:
+      bytes: [ 0x15, 0x50, 0x9f, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.s, p15/m, #-128"
+
+  -
+    input:
+      bytes: [ 0x15, 0x70, 0x9f, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.s, p15/m, #-32768"
+
+  -
+    input:
+      bytes: [ 0x15, 0x50, 0xdf, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.d, p15/m, #-128"
+
+  -
+    input:
+      bytes: [ 0x15, 0x70, 0xdf, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.d, p15/m, #-32768"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x21, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.b, b0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x22, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.h, h0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x24, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.s, s0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x28, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.d, d0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x30, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.q, q0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x21, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.b, b0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x22, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.h, h0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x24, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.s, s0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x28, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.d, d0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x30, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.q, q0"
+
+  -
+    input:
+      bytes: [ 0xff, 0x23, 0xff, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z31.b, z31.b[63]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x23, 0xfe, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z31.h, z31.h[31]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x23, 0xfc, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z31.s, z31.s[15]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x23, 0xf8, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z31.d, z31.d[7]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x22, 0xf0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z5.q, z17.q[3]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x28, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.b, p0/m, w0"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x68, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.h, p0/m, w0"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xa8, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.s, p0/m, w0"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xe8, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.d, p0/m, x0"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x28, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z31.b, p7/m, wsp"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x68, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z31.h, p7/m, wsp"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0xa8, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z31.s, p7/m, wsp"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0xe8, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z31.d, p7/m, sp"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x20, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.b, p0/m, b0"
+
+  -
+    input:
+      bytes: [ 0xff, 0x9f, 0x20, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z31.b, p7/m, b31"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x60, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.h, p0/m, h0"
+
+  -
+    input:
+      bytes: [ 0xff, 0x9f, 0x60, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z31.h, p7/m, h31"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xa0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.s, p0/m, s0"
+
+  -
+    input:
+      bytes: [ 0xff, 0x9f, 0xa0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z31.s, p7/m, s31"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xe0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.d, p0/m, d0"
+
+  -
+    input:
+      bytes: [ 0xff, 0x9f, 0xe0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z31.d, p7/m, d31"
+
+  -
+    input:
+      bytes: [ 0x10, 0x42, 0x00, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov p0.b, p0/m, p0.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x7f, 0x0f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov p15.b, p15/m, p15.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0x3f, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z31.b, p15/m, z31.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0x7f, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z31.h, p15/m, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xbf, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z31.s, p15/m, z31.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xff, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z31.d, p15/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0x80, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov p0.b, p0.b"
+
+  -
+    input:
+      bytes: [ 0xef, 0x7d, 0x8f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov p15.b, p15.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0x00, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov p0.b, p0/z, p0.b"
+
+  -
+    input:
+      bytes: [ 0xef, 0x7d, 0x0f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov p15.b, p15/z, p15.b"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31.d, p7/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0xe8, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z31.d, p7/m, sp"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0xe8, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z31.d, p7/m, sp"
+
+  -
+    input:
+      bytes: [ 0x95, 0x3f, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z21.d, p7/z, z28.d"
+
+  -
+    input:
+      bytes: [ 0x15, 0x70, 0xd7, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.d, p7/m, #-32768"
+
+  -
+    input:
+      bytes: [ 0x95, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z21, z28"
+
+  -
+    input:
+      bytes: [ 0x15, 0x70, 0xdf, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.d, p15/m, #-32768"
+
+  -
+    input:
+      bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4.d, p7/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xe4, 0x9f, 0xe0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z4.d, p7/m, d31"
+
+  -
+    input:
+      bytes: [ 0xc4, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4, z6"
+
+  -
+    input:
+      bytes: [ 0xe4, 0x9f, 0xe0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z4.d, p7/m, d31"
+
+  -
+    input:
+      bytes: [ 0x00, 0x38, 0x20, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.b, w0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x38, 0x60, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.h, w0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x38, 0xa0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.s, w0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x38, 0xe0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.d, x0"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3b, 0x60, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z31.h, wsp"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3b, 0xa0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z31.s, wsp"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3b, 0xe0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z31.d, sp"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3b, 0x20, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z31.b, wsp"
+
+  -
+    input:
+      bytes: [ 0x00, 0x30, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x30, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z31.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0x05, 0xd0, 0x38, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z5.b, #-128"
+
+  -
+    input:
+      bytes: [ 0xe5, 0xcf, 0x38, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z5.b, #127"
+
+  -
+    input:
+      bytes: [ 0xe5, 0xdf, 0x38, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z5.b, #-1"
+
+  -
+    input:
+      bytes: [ 0x15, 0xd0, 0x78, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.h, #-128"
+
+  -
+    input:
+      bytes: [ 0x15, 0xf0, 0x78, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.h, #-32768"
+
+  -
+    input:
+      bytes: [ 0x15, 0xf0, 0x78, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.h, #-32768"
+
+  -
+    input:
+      bytes: [ 0xf5, 0xcf, 0x78, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.h, #127"
+
+  -
+    input:
+      bytes: [ 0xf5, 0xef, 0x78, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.h, #32512"
+
+  -
+    input:
+      bytes: [ 0xf5, 0xef, 0x78, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.h, #32512"
+
+  -
+    input:
+      bytes: [ 0x15, 0xd0, 0xb8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.s, #-128"
+
+  -
+    input:
+      bytes: [ 0x15, 0xf0, 0xb8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.s, #-32768"
+
+  -
+    input:
+      bytes: [ 0x15, 0xf0, 0xb8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.s, #-32768"
+
+  -
+    input:
+      bytes: [ 0xf5, 0xcf, 0xb8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.s, #127"
+
+  -
+    input:
+      bytes: [ 0xf5, 0xef, 0xb8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.s, #32512"
+
+  -
+    input:
+      bytes: [ 0xf5, 0xef, 0xb8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.s, #32512"
+
+  -
+    input:
+      bytes: [ 0x15, 0xd0, 0xf8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.d, #-128"
+
+  -
+    input:
+      bytes: [ 0x15, 0xf0, 0xf8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.d, #-32768"
+
+  -
+    input:
+      bytes: [ 0x15, 0xf0, 0xf8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.d, #-32768"
+
+  -
+    input:
+      bytes: [ 0xf5, 0xcf, 0xf8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.d, #127"
+
+  -
+    input:
+      bytes: [ 0xf5, 0xef, 0xf8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.d, #32512"
+
+  -
+    input:
+      bytes: [ 0xf5, 0xef, 0xf8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.d, #32512"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf0, 0x78, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.h, #-32768"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xff, 0x78, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.h, #-256"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xef, 0x78, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.h, #32512"
+
+  -
+    input:
+      bytes: [ 0xc0, 0x05, 0xc0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.h, #32767"
+
+  -
+    input:
+      bytes: [ 0xc0, 0x83, 0xc0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.s, #0xffff7fff"
+
+  -
+    input:
+      bytes: [ 0x00, 0x88, 0xc0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.s, #32768"
+
+  -
+    input:
+      bytes: [ 0xc0, 0x87, 0xc3, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.d, #0xffffffffffff7fff"
+
+  -
+    input:
+      bytes: [ 0x00, 0x88, 0xc3, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.d, #32768"
+
+  -
+    input:
+      bytes: [ 0x80, 0x19, 0xc2, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.d, #0xe0000000000003ff"
+
+  -
+    input:
+      bytes: [ 0x05, 0x10, 0x10, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z5.b, p0/z, #-128"
+
+  -
+    input:
+      bytes: [ 0xe5, 0x0f, 0x10, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z5.b, p0/z, #127"
+
+  -
+    input:
+      bytes: [ 0xe5, 0x1f, 0x10, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z5.b, p0/z, #-1"
+
+  -
+    input:
+      bytes: [ 0x15, 0x10, 0x50, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.h, p0/z, #-128"
+
+  -
+    input:
+      bytes: [ 0x15, 0x30, 0x50, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.h, p0/z, #-32768"
+
+  -
+    input:
+      bytes: [ 0x15, 0x30, 0x50, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.h, p0/z, #-32768"
+
+  -
+    input:
+      bytes: [ 0xf5, 0x0f, 0x50, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.h, p0/z, #127"
+
+  -
+    input:
+      bytes: [ 0xf5, 0x2f, 0x50, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.h, p0/z, #32512"
+
+  -
+    input:
+      bytes: [ 0xf5, 0x2f, 0x50, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.h, p0/z, #32512"
+
+  -
+    input:
+      bytes: [ 0x15, 0x10, 0x90, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.s, p0/z, #-128"
+
+  -
+    input:
+      bytes: [ 0x15, 0x30, 0x90, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.s, p0/z, #-32768"
+
+  -
+    input:
+      bytes: [ 0x15, 0x30, 0x90, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.s, p0/z, #-32768"
+
+  -
+    input:
+      bytes: [ 0xf5, 0x0f, 0x90, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.s, p0/z, #127"
+
+  -
+    input:
+      bytes: [ 0xf5, 0x2f, 0x90, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.s, p0/z, #32512"
+
+  -
+    input:
+      bytes: [ 0xf5, 0x2f, 0x90, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.s, p0/z, #32512"
+
+  -
+    input:
+      bytes: [ 0x15, 0x10, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.d, p0/z, #-128"
+
+  -
+    input:
+      bytes: [ 0x15, 0x30, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.d, p0/z, #-32768"
+
+  -
+    input:
+      bytes: [ 0x15, 0x30, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.d, p0/z, #-32768"
+
+  -
+    input:
+      bytes: [ 0xf5, 0x0f, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.d, p0/z, #127"
+
+  -
+    input:
+      bytes: [ 0xf5, 0x2f, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.d, p0/z, #32512"
+
+  -
+    input:
+      bytes: [ 0xf5, 0x2f, 0xd0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.d, p0/z, #32512"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xcf, 0x38, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.b, #127"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xef, 0x78, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.h, #32512"
+
+  -
+    input:
+      bytes: [ 0x45, 0xdf, 0x78, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z5.h, #-6"
+
+  -
+    input:
+      bytes: [ 0x45, 0xdf, 0xb8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z5.s, #-6"
+
+  -
+    input:
+      bytes: [ 0x45, 0xdf, 0xf8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z5.d, #-6"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x0f, 0x10, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.b, p0/z, #127"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x2f, 0x50, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.h, p0/z, #32512"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x2f, 0x50, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.h, p0/z, #32512"
+
+  -
+    input:
+      bytes: [ 0x05, 0x50, 0x1f, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z5.b, p15/m, #-128"
+
+  -
+    input:
+      bytes: [ 0x15, 0x50, 0x5f, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.h, p15/m, #-128"
+
+  -
+    input:
+      bytes: [ 0x15, 0x70, 0x5f, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.h, p15/m, #-32768"
+
+  -
+    input:
+      bytes: [ 0x15, 0x50, 0x9f, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.s, p15/m, #-128"
+
+  -
+    input:
+      bytes: [ 0x15, 0x70, 0x9f, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.s, p15/m, #-32768"
+
+  -
+    input:
+      bytes: [ 0x15, 0x50, 0xdf, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.d, p15/m, #-128"
+
+  -
+    input:
+      bytes: [ 0x15, 0x70, 0xdf, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.d, p15/m, #-32768"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x21, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.b, b0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x22, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.h, h0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x24, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.s, s0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x28, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.d, d0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x30, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.q, q0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x21, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.b, b0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x22, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.h, h0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x24, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.s, s0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x28, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.d, d0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x30, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.q, q0"
+
+  -
+    input:
+      bytes: [ 0xff, 0x23, 0xff, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z31.b, z31.b[63]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x23, 0xfe, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z31.h, z31.h[31]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x23, 0xfc, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z31.s, z31.s[15]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x23, 0xf8, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z31.d, z31.d[7]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x22, 0xf0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z5.q, z17.q[3]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x28, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.b, p0/m, w0"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x68, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.h, p0/m, w0"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xa8, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.s, p0/m, w0"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xe8, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.d, p0/m, x0"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x28, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z31.b, p7/m, wsp"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x68, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z31.h, p7/m, wsp"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0xa8, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z31.s, p7/m, wsp"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0xe8, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z31.d, p7/m, sp"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x20, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.b, p0/m, b0"
+
+  -
+    input:
+      bytes: [ 0xff, 0x9f, 0x20, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z31.b, p7/m, b31"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x60, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.h, p0/m, h0"
+
+  -
+    input:
+      bytes: [ 0xff, 0x9f, 0x60, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z31.h, p7/m, h31"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xa0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.s, p0/m, s0"
+
+  -
+    input:
+      bytes: [ 0xff, 0x9f, 0xa0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z31.s, p7/m, s31"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xe0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.d, p0/m, d0"
+
+  -
+    input:
+      bytes: [ 0xff, 0x9f, 0xe0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z31.d, p7/m, d31"
+
+  -
+    input:
+      bytes: [ 0x10, 0x42, 0x00, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov p0.b, p0/m, p0.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x7f, 0x0f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov p15.b, p15/m, p15.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0x3f, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z31.b, p15/m, z31.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0x7f, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z31.h, p15/m, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xbf, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z31.s, p15/m, z31.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xff, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z31.d, p15/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0x80, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov p0.b, p0.b"
+
+  -
+    input:
+      bytes: [ 0xef, 0x7d, 0x8f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov p15.b, p15.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0x00, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov p0.b, p0/z, p0.b"
+
+  -
+    input:
+      bytes: [ 0xef, 0x7d, 0x0f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov p15.b, p15/z, p15.b"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31.d, p7/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0xe8, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z31.d, p7/m, sp"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0xe8, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z31.d, p7/m, sp"
+
+  -
+    input:
+      bytes: [ 0x95, 0x3f, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z21.d, p7/z, z28.d"
+
+  -
+    input:
+      bytes: [ 0x15, 0x70, 0xd7, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.d, p7/m, #-32768"
+
+  -
+    input:
+      bytes: [ 0x95, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z21, z28"
+
+  -
+    input:
+      bytes: [ 0x15, 0x70, 0xdf, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z21.d, p15/m, #-32768"
+
+  -
+    input:
+      bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4.d, p7/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xe4, 0x9f, 0xe0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z4.d, p7/m, d31"
+
+  -
+    input:
+      bytes: [ 0xc4, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4, z6"
+
+  -
+    input:
+      bytes: [ 0xe4, 0x9f, 0xe0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z4.d, p7/m, d31"
diff --git a/tests/MC/AArch64/SVE/movprfx.s.yaml b/tests/MC/AArch64/SVE/movprfx.s.yaml
new file mode 100644
index 000000000..4be441473
--- /dev/null
+++ b/tests/MC/AArch64/SVE/movprfx.s.yaml
@@ -0,0 +1,220 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z1"
+
+  -
+    input:
+      bytes: [ 0x20, 0x00, 0x40, 0xd4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "hlt #0x1"
+
+  -
+    input:
+      bytes: [ 0x20, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0.d, p0/z, z1.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x00, 0x40, 0xd4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "hlt #0x1"
+
+  -
+    input:
+      bytes: [ 0x20, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z1"
+
+  -
+    input:
+      bytes: [ 0x20, 0x00, 0x20, 0xd4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "brk #0x1"
+
+  -
+    input:
+      bytes: [ 0x20, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0.d, p0/z, z1.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x00, 0x20, 0xd4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "brk #0x1"
+
+  -
+    input:
+      bytes: [ 0x20, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z1"
+
+  -
+    input:
+      bytes: [ 0x20, 0x00, 0xc0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "add z0.d, p0/m, z0.d, z1.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x00, 0xc0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "add z0.d, p0/m, z0.d, z1.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z1"
+
+  -
+    input:
+      bytes: [ 0x20, 0x00, 0x40, 0xd4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "hlt #0x1"
+
+  -
+    input:
+      bytes: [ 0x20, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0.d, p0/z, z1.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x00, 0x40, 0xd4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "hlt #0x1"
+
+  -
+    input:
+      bytes: [ 0x20, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z1"
+
+  -
+    input:
+      bytes: [ 0x20, 0x00, 0x20, 0xd4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "brk #0x1"
+
+  -
+    input:
+      bytes: [ 0x20, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0.d, p0/z, z1.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x00, 0x20, 0xd4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "brk #0x1"
+
+  -
+    input:
+      bytes: [ 0x20, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z1"
+
+  -
+    input:
+      bytes: [ 0x20, 0x00, 0xc0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "add z0.d, p0/m, z0.d, z1.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x00, 0xc0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "add z0.d, p0/m, z0.d, z1.d"
diff --git a/tests/MC/AArch64/SVE/movs.s.yaml b/tests/MC/AArch64/SVE/movs.s.yaml
new file mode 100644
index 000000000..fd777a6a5
--- /dev/null
+++ b/tests/MC/AArch64/SVE/movs.s.yaml
@@ -0,0 +1,80 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0xc0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movs p0.b, p0.b"
+
+  -
+    input:
+      bytes: [ 0xef, 0x7d, 0xcf, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movs p15.b, p15.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0x40, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movs p0.b, p0/z, p0.b"
+
+  -
+    input:
+      bytes: [ 0xef, 0x7d, 0x4f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movs p15.b, p15/z, p15.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0xc0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movs p0.b, p0.b"
+
+  -
+    input:
+      bytes: [ 0xef, 0x7d, 0xcf, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movs p15.b, p15.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0x40, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movs p0.b, p0/z, p0.b"
+
+  -
+    input:
+      bytes: [ 0xef, 0x7d, 0x4f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movs p15.b, p15/z, p15.b"
diff --git a/tests/MC/AArch64/SVE/msb.s.yaml b/tests/MC/AArch64/SVE/msb.s.yaml
new file mode 100644
index 000000000..961795773
--- /dev/null
+++ b/tests/MC/AArch64/SVE/msb.s.yaml
@@ -0,0 +1,160 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xe0, 0xff, 0x01, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "msb z0.b, p7/m, z1.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xff, 0x41, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "msb z0.h, p7/m, z1.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xff, 0x81, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "msb z0.s, p7/m, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xff, 0xc1, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "msb z0.d, p7/m, z1.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0.d, p7/z, z7.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xff, 0xc1, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "msb z0.d, p7/m, z1.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xff, 0xc1, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "msb z0.d, p7/m, z1.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xff, 0x01, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "msb z0.b, p7/m, z1.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xff, 0x41, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "msb z0.h, p7/m, z1.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xff, 0x81, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "msb z0.s, p7/m, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xff, 0xc1, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "msb z0.d, p7/m, z1.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0.d, p7/z, z7.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xff, 0xc1, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "msb z0.d, p7/m, z1.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xff, 0xc1, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "msb z0.d, p7/m, z1.d, z31.d"
diff --git a/tests/MC/AArch64/SVE/mul.s.yaml b/tests/MC/AArch64/SVE/mul.s.yaml
new file mode 100644
index 000000000..55ca513a8
--- /dev/null
+++ b/tests/MC/AArch64/SVE/mul.s.yaml
@@ -0,0 +1,360 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xe0, 0x1f, 0x10, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul z0.b, p7/m, z0.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x1f, 0x50, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul z0.h, p7/m, z0.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x1f, 0x90, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul z0.s, p7/m, z0.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x1f, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul z0.d, p7/m, z0.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0x1f, 0xd0, 0x30, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul z31.b, z31.b, #-128"
+
+  -
+    input:
+      bytes: [ 0xff, 0xcf, 0x30, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul z31.b, z31.b, #127"
+
+  -
+    input:
+      bytes: [ 0x1f, 0xd0, 0x70, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul z31.h, z31.h, #-128"
+
+  -
+    input:
+      bytes: [ 0xff, 0xcf, 0x70, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul z31.h, z31.h, #127"
+
+  -
+    input:
+      bytes: [ 0x1f, 0xd0, 0xb0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul z31.s, z31.s, #-128"
+
+  -
+    input:
+      bytes: [ 0xff, 0xcf, 0xb0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul z31.s, z31.s, #127"
+
+  -
+    input:
+      bytes: [ 0x1f, 0xd0, 0xf0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul z31.d, z31.d, #-128"
+
+  -
+    input:
+      bytes: [ 0xff, 0xcf, 0xf0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul z31.d, z31.d, #127"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0.d, p7/z, z7.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x1f, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul z0.d, p7/m, z0.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x1f, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul z0.d, p7/m, z0.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xff, 0xcf, 0xf0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul z31.d, z31.d, #127"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x1f, 0x10, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul z0.b, p7/m, z0.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x1f, 0x50, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul z0.h, p7/m, z0.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x1f, 0x90, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul z0.s, p7/m, z0.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x1f, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul z0.d, p7/m, z0.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0x1f, 0xd0, 0x30, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul z31.b, z31.b, #-128"
+
+  -
+    input:
+      bytes: [ 0xff, 0xcf, 0x30, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul z31.b, z31.b, #127"
+
+  -
+    input:
+      bytes: [ 0x1f, 0xd0, 0x70, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul z31.h, z31.h, #-128"
+
+  -
+    input:
+      bytes: [ 0xff, 0xcf, 0x70, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul z31.h, z31.h, #127"
+
+  -
+    input:
+      bytes: [ 0x1f, 0xd0, 0xb0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul z31.s, z31.s, #-128"
+
+  -
+    input:
+      bytes: [ 0xff, 0xcf, 0xb0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul z31.s, z31.s, #127"
+
+  -
+    input:
+      bytes: [ 0x1f, 0xd0, 0xf0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul z31.d, z31.d, #-128"
+
+  -
+    input:
+      bytes: [ 0xff, 0xcf, 0xf0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul z31.d, z31.d, #127"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0.d, p7/z, z7.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x1f, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul z0.d, p7/m, z0.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x1f, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul z0.d, p7/m, z0.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xff, 0xcf, 0xf0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul z31.d, z31.d, #127"
diff --git a/tests/MC/AArch64/SVE/nand.s.yaml b/tests/MC/AArch64/SVE/nand.s.yaml
new file mode 100644
index 000000000..683abfe69
--- /dev/null
+++ b/tests/MC/AArch64/SVE/nand.s.yaml
@@ -0,0 +1,40 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x10, 0x42, 0x80, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "nand p0.b, p0/z, p0.b, p0.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x7f, 0x8f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "nand p15.b, p15/z, p15.b, p15.b"
+
+  -
+    input:
+      bytes: [ 0x10, 0x42, 0x80, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "nand p0.b, p0/z, p0.b, p0.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x7f, 0x8f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "nand p15.b, p15/z, p15.b, p15.b"
diff --git a/tests/MC/AArch64/SVE/nands.s.yaml b/tests/MC/AArch64/SVE/nands.s.yaml
new file mode 100644
index 000000000..61b12c9e7
--- /dev/null
+++ b/tests/MC/AArch64/SVE/nands.s.yaml
@@ -0,0 +1,40 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x10, 0x42, 0xc0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "nands p0.b, p0/z, p0.b, p0.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x7f, 0xcf, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "nands p15.b, p15/z, p15.b, p15.b"
+
+  -
+    input:
+      bytes: [ 0x10, 0x42, 0xc0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "nands p0.b, p0/z, p0.b, p0.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x7f, 0xcf, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "nands p15.b, p15/z, p15.b, p15.b"
diff --git a/tests/MC/AArch64/SVE/neg.s.yaml b/tests/MC/AArch64/SVE/neg.s.yaml
new file mode 100644
index 000000000..139ac857f
--- /dev/null
+++ b/tests/MC/AArch64/SVE/neg.s.yaml
@@ -0,0 +1,240 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x17, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "neg z0.b, p0/m, z0.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x57, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "neg z0.h, p0/m, z0.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x97, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "neg z0.s, p0/m, z0.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xd7, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "neg z0.d, p0/m, z0.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x17, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "neg z31.b, p7/m, z31.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x57, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "neg z31.h, p7/m, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x97, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "neg z31.s, p7/m, z31.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0xd7, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "neg z31.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4.d, p7/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xbf, 0xd7, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "neg z4.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4, z6"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xbf, 0xd7, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "neg z4.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x17, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "neg z0.b, p0/m, z0.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x57, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "neg z0.h, p0/m, z0.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x97, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "neg z0.s, p0/m, z0.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xd7, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "neg z0.d, p0/m, z0.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x17, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "neg z31.b, p7/m, z31.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x57, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "neg z31.h, p7/m, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x97, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "neg z31.s, p7/m, z31.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0xd7, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "neg z31.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4.d, p7/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xbf, 0xd7, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "neg z4.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4, z6"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xbf, 0xd7, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "neg z4.d, p7/m, z31.d"
diff --git a/tests/MC/AArch64/SVE/nor.s.yaml b/tests/MC/AArch64/SVE/nor.s.yaml
new file mode 100644
index 000000000..54f5faff7
--- /dev/null
+++ b/tests/MC/AArch64/SVE/nor.s.yaml
@@ -0,0 +1,40 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x42, 0x80, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "nor p0.b, p0/z, p0.b, p0.b"
+
+  -
+    input:
+      bytes: [ 0xef, 0x7f, 0x8f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "nor p15.b, p15/z, p15.b, p15.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x42, 0x80, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "nor p0.b, p0/z, p0.b, p0.b"
+
+  -
+    input:
+      bytes: [ 0xef, 0x7f, 0x8f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "nor p15.b, p15/z, p15.b, p15.b"
diff --git a/tests/MC/AArch64/SVE/nors.s.yaml b/tests/MC/AArch64/SVE/nors.s.yaml
new file mode 100644
index 000000000..140a2ddbe
--- /dev/null
+++ b/tests/MC/AArch64/SVE/nors.s.yaml
@@ -0,0 +1,40 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x42, 0xc0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "nors p0.b, p0/z, p0.b, p0.b"
+
+  -
+    input:
+      bytes: [ 0xef, 0x7f, 0xcf, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "nors p15.b, p15/z, p15.b, p15.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x42, 0xc0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "nors p0.b, p0/z, p0.b, p0.b"
+
+  -
+    input:
+      bytes: [ 0xef, 0x7f, 0xcf, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "nors p15.b, p15/z, p15.b, p15.b"
diff --git a/tests/MC/AArch64/SVE/not.s.yaml b/tests/MC/AArch64/SVE/not.s.yaml
new file mode 100644
index 000000000..1a6a365f0
--- /dev/null
+++ b/tests/MC/AArch64/SVE/not.s.yaml
@@ -0,0 +1,200 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x1e, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "not z31.b, p7/m, z31.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x5e, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "not z31.h, p7/m, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x9e, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "not z31.s, p7/m, z31.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0xde, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "not z31.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x42, 0x00, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "not p0.b, p0/z, p0.b"
+
+  -
+    input:
+      bytes: [ 0xef, 0x7f, 0x0f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "not p15.b, p15/z, p15.b"
+
+  -
+    input:
+      bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4.d, p7/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xbf, 0xde, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "not z4.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4, z6"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xbf, 0xde, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "not z4.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x1e, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "not z31.b, p7/m, z31.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x5e, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "not z31.h, p7/m, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x9e, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "not z31.s, p7/m, z31.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0xde, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "not z31.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x42, 0x00, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "not p0.b, p0/z, p0.b"
+
+  -
+    input:
+      bytes: [ 0xef, 0x7f, 0x0f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "not p15.b, p15/z, p15.b"
+
+  -
+    input:
+      bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4.d, p7/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xbf, 0xde, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "not z4.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4, z6"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xbf, 0xde, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "not z4.d, p7/m, z31.d"
diff --git a/tests/MC/AArch64/SVE/nots.s.yaml b/tests/MC/AArch64/SVE/nots.s.yaml
new file mode 100644
index 000000000..1aa86ad61
--- /dev/null
+++ b/tests/MC/AArch64/SVE/nots.s.yaml
@@ -0,0 +1,40 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x42, 0x40, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "nots p0.b, p0/z, p0.b"
+
+  -
+    input:
+      bytes: [ 0xef, 0x7f, 0x4f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "nots p15.b, p15/z, p15.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x42, 0x40, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "nots p0.b, p0/z, p0.b"
+
+  -
+    input:
+      bytes: [ 0xef, 0x7f, 0x4f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "nots p15.b, p15/z, p15.b"
diff --git a/tests/MC/AArch64/SVE/orn.s.yaml b/tests/MC/AArch64/SVE/orn.s.yaml
new file mode 100644
index 000000000..1ea97978f
--- /dev/null
+++ b/tests/MC/AArch64/SVE/orn.s.yaml
@@ -0,0 +1,240 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x25, 0x3e, 0x00, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "orr z5.b, z5.b, #0x6"
+
+  -
+    input:
+      bytes: [ 0x37, 0x7c, 0x00, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "orr z23.h, z23.h, #0x6"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf8, 0x00, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "orr z0.s, z0.s, #0x6"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf8, 0x03, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "orr z0.d, z0.d, #0x6"
+
+  -
+    input:
+      bytes: [ 0xa5, 0x2e, 0x00, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "orr z5.b, z5.b, #0xf9"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x6d, 0x00, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "orr z23.h, z23.h, #0xfff9"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xeb, 0x00, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "orr z0.s, z0.s, #0xfffffff9"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xef, 0x03, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "orr z0.d, z0.d, #0xfffffffffffffff9"
+
+  -
+    input:
+      bytes: [ 0x10, 0x40, 0x80, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "orn p0.b, p0/z, p0.b, p0.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x7d, 0x8f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "orn p15.b, p15/z, p15.b, p15.b"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xef, 0x03, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "orr z0.d, z0.d, #0xfffffffffffffff9"
+
+  -
+    input:
+      bytes: [ 0x25, 0x3e, 0x00, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "orr z5.b, z5.b, #0x6"
+
+  -
+    input:
+      bytes: [ 0x37, 0x7c, 0x00, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "orr z23.h, z23.h, #0x6"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf8, 0x00, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "orr z0.s, z0.s, #0x6"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf8, 0x03, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "orr z0.d, z0.d, #0x6"
+
+  -
+    input:
+      bytes: [ 0xa5, 0x2e, 0x00, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "orr z5.b, z5.b, #0xf9"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x6d, 0x00, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "orr z23.h, z23.h, #0xfff9"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xeb, 0x00, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "orr z0.s, z0.s, #0xfffffff9"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xef, 0x03, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "orr z0.d, z0.d, #0xfffffffffffffff9"
+
+  -
+    input:
+      bytes: [ 0x10, 0x40, 0x80, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "orn p0.b, p0/z, p0.b, p0.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x7d, 0x8f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "orn p15.b, p15/z, p15.b, p15.b"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xef, 0x03, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "orr z0.d, z0.d, #0xfffffffffffffff9"
diff --git a/tests/MC/AArch64/SVE/orns.s.yaml b/tests/MC/AArch64/SVE/orns.s.yaml
new file mode 100644
index 000000000..3e9eb1aaf
--- /dev/null
+++ b/tests/MC/AArch64/SVE/orns.s.yaml
@@ -0,0 +1,40 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x10, 0x40, 0xc0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "orns p0.b, p0/z, p0.b, p0.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x7d, 0xcf, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "orns p15.b, p15/z, p15.b, p15.b"
+
+  -
+    input:
+      bytes: [ 0x10, 0x40, 0xc0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "orns p0.b, p0/z, p0.b, p0.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x7d, 0xcf, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "orns p15.b, p15/z, p15.b, p15.b"
diff --git a/tests/MC/AArch64/SVE/orr.s.yaml b/tests/MC/AArch64/SVE/orr.s.yaml
new file mode 100644
index 000000000..a700e1f34
--- /dev/null
+++ b/tests/MC/AArch64/SVE/orr.s.yaml
@@ -0,0 +1,580 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xa5, 0x2e, 0x00, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "orr z5.b, z5.b, #0xf9"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x6d, 0x00, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "orr z23.h, z23.h, #0xfff9"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xeb, 0x00, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "orr z0.s, z0.s, #0xfffffff9"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xef, 0x03, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "orr z0.d, z0.d, #0xfffffffffffffff9"
+
+  -
+    input:
+      bytes: [ 0x25, 0x3e, 0x00, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "orr z5.b, z5.b, #0x6"
+
+  -
+    input:
+      bytes: [ 0x37, 0x7c, 0x00, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "orr z23.h, z23.h, #0x6"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf8, 0x00, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "orr z0.s, z0.s, #0x6"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf8, 0x03, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "orr z0.d, z0.d, #0x6"
+
+  -
+    input:
+      bytes: [ 0x00, 0x30, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x31, 0x68, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "orr z23.d, z13.d, z8.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0x18, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "orr z31.b, p7/m, z31.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0x58, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "orr z31.h, p7/m, z31.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0x98, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "orr z31.s, p7/m, z31.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0xd8, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "orr z31.d, p7/m, z31.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0x81, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "orr p0.b, p0/z, p0.b, p1.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0x80, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov p0.b, p0.b"
+
+  -
+    input:
+      bytes: [ 0xef, 0x7d, 0x8f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov p15.b, p15.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x30, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x30, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x30, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x31, 0x68, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "orr z23.d, z13.d, z8.d"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x31, 0x68, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "orr z23.d, z13.d, z8.d"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x31, 0x68, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "orr z23.d, z13.d, z8.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4.d, p7/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xe4, 0x1f, 0xd8, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "orr z4.d, p7/m, z4.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4, z6"
+
+  -
+    input:
+      bytes: [ 0xe4, 0x1f, 0xd8, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "orr z4.d, p7/m, z4.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf8, 0x03, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "orr z0.d, z0.d, #0x6"
+
+  -
+    input:
+      bytes: [ 0xa5, 0x2e, 0x00, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "orr z5.b, z5.b, #0xf9"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x6d, 0x00, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "orr z23.h, z23.h, #0xfff9"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xeb, 0x00, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "orr z0.s, z0.s, #0xfffffff9"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xef, 0x03, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "orr z0.d, z0.d, #0xfffffffffffffff9"
+
+  -
+    input:
+      bytes: [ 0x25, 0x3e, 0x00, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "orr z5.b, z5.b, #0x6"
+
+  -
+    input:
+      bytes: [ 0x37, 0x7c, 0x00, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "orr z23.h, z23.h, #0x6"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf8, 0x00, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "orr z0.s, z0.s, #0x6"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf8, 0x03, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "orr z0.d, z0.d, #0x6"
+
+  -
+    input:
+      bytes: [ 0x00, 0x30, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x31, 0x68, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "orr z23.d, z13.d, z8.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0x18, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "orr z31.b, p7/m, z31.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0x58, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "orr z31.h, p7/m, z31.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0x98, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "orr z31.s, p7/m, z31.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0xd8, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "orr z31.d, p7/m, z31.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0x81, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "orr p0.b, p0/z, p0.b, p1.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0x80, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov p0.b, p0.b"
+
+  -
+    input:
+      bytes: [ 0xef, 0x7d, 0x8f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov p15.b, p15.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x30, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x30, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x30, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z0.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x31, 0x68, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "orr z23.d, z13.d, z8.d"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x31, 0x68, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "orr z23.d, z13.d, z8.d"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x31, 0x68, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "orr z23.d, z13.d, z8.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4.d, p7/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xe4, 0x1f, 0xd8, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "orr z4.d, p7/m, z4.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4, z6"
+
+  -
+    input:
+      bytes: [ 0xe4, 0x1f, 0xd8, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "orr z4.d, p7/m, z4.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf8, 0x03, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "orr z0.d, z0.d, #0x6"
diff --git a/tests/MC/AArch64/SVE/orrs.s.yaml b/tests/MC/AArch64/SVE/orrs.s.yaml
new file mode 100644
index 000000000..27ca41878
--- /dev/null
+++ b/tests/MC/AArch64/SVE/orrs.s.yaml
@@ -0,0 +1,60 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0xc1, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "orrs p0.b, p0/z, p0.b, p1.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0xc0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movs p0.b, p0.b"
+
+  -
+    input:
+      bytes: [ 0xef, 0x7d, 0xcf, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movs p15.b, p15.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0xc1, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "orrs p0.b, p0/z, p0.b, p1.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0xc0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movs p0.b, p0.b"
+
+  -
+    input:
+      bytes: [ 0xef, 0x7d, 0xcf, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movs p15.b, p15.b"
diff --git a/tests/MC/AArch64/SVE/orv.s.yaml b/tests/MC/AArch64/SVE/orv.s.yaml
new file mode 100644
index 000000000..5afb78af5
--- /dev/null
+++ b/tests/MC/AArch64/SVE/orv.s.yaml
@@ -0,0 +1,80 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xe0, 0x3f, 0x18, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "orv b0, p7, z31.b"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3f, 0x58, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "orv h0, p7, z31.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3f, 0x98, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "orv s0, p7, z31.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3f, 0xd8, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "orv d0, p7, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3f, 0x18, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "orv b0, p7, z31.b"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3f, 0x58, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "orv h0, p7, z31.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3f, 0x98, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "orv s0, p7, z31.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3f, 0xd8, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "orv d0, p7, z31.d"
diff --git a/tests/MC/AArch64/SVE/pfalse.s.yaml b/tests/MC/AArch64/SVE/pfalse.s.yaml
new file mode 100644
index 000000000..171c4a64a
--- /dev/null
+++ b/tests/MC/AArch64/SVE/pfalse.s.yaml
@@ -0,0 +1,20 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x0f, 0xe4, 0x18, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "pfalse p15.b"
+
+  -
+    input:
+      bytes: [ 0x0f, 0xe4, 0x18, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "pfalse p15.b"
diff --git a/tests/MC/AArch64/SVE/pfirst.s.yaml b/tests/MC/AArch64/SVE/pfirst.s.yaml
new file mode 100644
index 000000000..478d7f65a
--- /dev/null
+++ b/tests/MC/AArch64/SVE/pfirst.s.yaml
@@ -0,0 +1,40 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xe0, 0xc1, 0x58, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "pfirst p0.b, p15, p0.b"
+
+  -
+    input:
+      bytes: [ 0xef, 0xc1, 0x58, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "pfirst p15.b, p15, p15.b"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc1, 0x58, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "pfirst p0.b, p15, p0.b"
+
+  -
+    input:
+      bytes: [ 0xef, 0xc1, 0x58, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "pfirst p15.b, p15, p15.b"
diff --git a/tests/MC/AArch64/SVE/pnext.s.yaml b/tests/MC/AArch64/SVE/pnext.s.yaml
new file mode 100644
index 000000000..2375b4626
--- /dev/null
+++ b/tests/MC/AArch64/SVE/pnext.s.yaml
@@ -0,0 +1,100 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xef, 0xc5, 0x19, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "pnext p15.b, p15, p15.b"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc5, 0x19, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "pnext p0.b, p15, p0.b"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc5, 0x59, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "pnext p0.h, p15, p0.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc5, 0x99, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "pnext p0.s, p15, p0.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc5, 0xd9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "pnext p0.d, p15, p0.d"
+
+  -
+    input:
+      bytes: [ 0xef, 0xc5, 0x19, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "pnext p15.b, p15, p15.b"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc5, 0x19, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "pnext p0.b, p15, p0.b"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc5, 0x59, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "pnext p0.h, p15, p0.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc5, 0x99, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "pnext p0.s, p15, p0.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc5, 0xd9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "pnext p0.d, p15, p0.d"
diff --git a/tests/MC/AArch64/SVE/predicate-as-counter-aliases.s.yaml b/tests/MC/AArch64/SVE/predicate-as-counter-aliases.s.yaml
new file mode 100644
index 000000000..182e38881
--- /dev/null
+++ b/tests/MC/AArch64/SVE/predicate-as-counter-aliases.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x80, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x45, 0x1d, 0x9f, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr p5, [x10, #255, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x80, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "str p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x45, 0x1d, 0x9f, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "str p5, [x10, #255, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0x80, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov p0.b, p0.b"
+
+  -
+    input:
+      bytes: [ 0x0f, 0xe4, 0x18, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "pfalse p15.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x80, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x45, 0x1d, 0x9f, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr p5, [x10, #255, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x80, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "str p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x45, 0x1d, 0x9f, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "str p5, [x10, #255, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0x80, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov p0.b, p0.b"
+
+  -
+    input:
+      bytes: [ 0x0f, 0xe4, 0x18, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "pfalse p15.b"
diff --git a/tests/MC/AArch64/SVE/prfb-sve-only.s.yaml b/tests/MC/AArch64/SVE/prfb-sve-only.s.yaml
new file mode 100644
index 000000000..fbdd8bdce
--- /dev/null
+++ b/tests/MC/AArch64/SVE/prfb-sve-only.s.yaml
@@ -0,0 +1,90 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x20, 0x84 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfb pldl1keep, p0, [x0, z0.s, uxtw]"
+
+  -
+    input:
+      bytes: [ 0x45, 0x15, 0x35, 0x84 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfb pldl3strm, p5, [x10, z21.s, uxtw]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x20, 0xc4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfb pldl1keep, p0, [x0, z0.d, uxtw]"
+
+  -
+    input:
+      bytes: [ 0x45, 0x15, 0x75, 0xc4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfb pldl3strm, p5, [x10, z21.d, sxtw]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x60, 0xc4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfb pldl1keep, p0, [x0, z0.d]"
+
+  -
+    input:
+      bytes: [ 0xa7, 0xed, 0x00, 0x84 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfb #7, p3, [z13.s]"
+
+  -
+    input:
+      bytes: [ 0xa7, 0xed, 0x1f, 0x84 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfb #7, p3, [z13.s, #31]"
+
+  -
+    input:
+      bytes: [ 0x45, 0xf5, 0x00, 0xc4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfb pldl3strm, p5, [z10.d]"
+
+  -
+    input:
+      bytes: [ 0x45, 0xf5, 0x1f, 0xc4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfb pldl3strm, p5, [z10.d, #31]"
diff --git a/tests/MC/AArch64/SVE/prfb.s.yaml b/tests/MC/AArch64/SVE/prfb.s.yaml
new file mode 100644
index 000000000..24537c907
--- /dev/null
+++ b/tests/MC/AArch64/SVE/prfb.s.yaml
@@ -0,0 +1,600 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfb pldl1keep, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfb pldl1keep, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfb pldl1strm, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfb pldl1strm, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x02, 0x00, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfb pldl2keep, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x02, 0x00, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfb pldl2keep, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x03, 0x00, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfb pldl2strm, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x03, 0x00, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfb pldl2strm, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x04, 0x00, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfb pldl3keep, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x04, 0x00, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfb pldl3keep, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x05, 0x00, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfb pldl3strm, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x05, 0x00, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfb pldl3strm, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x06, 0x00, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfb #6, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x07, 0x00, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfb #7, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x08, 0x00, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfb pstl1keep, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x08, 0x00, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfb pstl1keep, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfb pstl1strm, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfb pstl1strm, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x0a, 0x00, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfb pstl2keep, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x0a, 0x00, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfb pstl2keep, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfb pstl2strm, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfb pstl2strm, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x0c, 0x00, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfb pstl3keep, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x0c, 0x00, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfb pstl3keep, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x0d, 0x00, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfb pstl3strm, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x0d, 0x00, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfb pstl3strm, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x0e, 0x00, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfb #14, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfb #15, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0xe0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfb pldl1strm, p0, [x0, #-32, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0xdf, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfb pldl1strm, p0, [x0, #31, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfb pldl1keep, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfb pldl1keep, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfb pldl1strm, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfb pldl1strm, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x02, 0x00, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfb pldl2keep, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x02, 0x00, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfb pldl2keep, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x03, 0x00, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfb pldl2strm, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x03, 0x00, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfb pldl2strm, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x04, 0x00, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfb pldl3keep, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x04, 0x00, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfb pldl3keep, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x05, 0x00, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfb pldl3strm, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x05, 0x00, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfb pldl3strm, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x06, 0x00, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfb #6, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x07, 0x00, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfb #7, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x08, 0x00, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfb pstl1keep, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x08, 0x00, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfb pstl1keep, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfb pstl1strm, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfb pstl1strm, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x0a, 0x00, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfb pstl2keep, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x0a, 0x00, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfb pstl2keep, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfb pstl2strm, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfb pstl2strm, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x0c, 0x00, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfb pstl3keep, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x0c, 0x00, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfb pstl3keep, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x0d, 0x00, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfb pstl3strm, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x0d, 0x00, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfb pstl3strm, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x0e, 0x00, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfb #14, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfb #15, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0xe0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfb pldl1strm, p0, [x0, #-32, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0xdf, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfb pldl1strm, p0, [x0, #31, mul vl]"
diff --git a/tests/MC/AArch64/SVE/prfd-sve-only.s.yaml b/tests/MC/AArch64/SVE/prfd-sve-only.s.yaml
new file mode 100644
index 000000000..a2a83b3ef
--- /dev/null
+++ b/tests/MC/AArch64/SVE/prfd-sve-only.s.yaml
@@ -0,0 +1,90 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0x20, 0x84 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfd pldl1keep, p0, [x0, z0.s, uxtw #3]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0x60, 0x84 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfd pldl1keep, p0, [x0, z0.s, sxtw #3]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0x20, 0xc4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfd pldl1keep, p0, [x0, z0.d, uxtw #3]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0x60, 0xc4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfd pldl1keep, p0, [x0, z0.d, sxtw #3]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x60, 0xc4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfd pldl1keep, p0, [x0, z0.d, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0xef, 0xff, 0x80, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfd #15, p7, [z31.s]"
+
+  -
+    input:
+      bytes: [ 0xef, 0xff, 0x9f, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfd #15, p7, [z31.s, #248]"
+
+  -
+    input:
+      bytes: [ 0xef, 0xff, 0x80, 0xc5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfd #15, p7, [z31.d]"
+
+  -
+    input:
+      bytes: [ 0xef, 0xff, 0x9f, 0xc5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfd #15, p7, [z31.d, #248]"
diff --git a/tests/MC/AArch64/SVE/prfd.s.yaml b/tests/MC/AArch64/SVE/prfd.s.yaml
new file mode 100644
index 000000000..c2b6bd380
--- /dev/null
+++ b/tests/MC/AArch64/SVE/prfd.s.yaml
@@ -0,0 +1,600 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfd pldl1keep, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfd pldl1keep, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x60, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfd pldl1strm, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x60, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfd pldl1strm, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x02, 0x60, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfd pldl2keep, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x02, 0x60, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfd pldl2keep, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x03, 0x60, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfd pldl2strm, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x03, 0x60, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfd pldl2strm, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x04, 0x60, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfd pldl3keep, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x04, 0x60, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfd pldl3keep, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x05, 0x60, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfd pldl3strm, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x05, 0x60, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfd pldl3strm, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x06, 0x60, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfd #6, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x07, 0x60, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfd #7, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x08, 0x60, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfd pstl1keep, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x08, 0x60, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfd pstl1keep, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x09, 0x60, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfd pstl1strm, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x09, 0x60, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfd pstl1strm, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x0a, 0x60, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfd pstl2keep, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x0a, 0x60, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfd pstl2keep, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x0b, 0x60, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfd pstl2strm, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x0b, 0x60, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfd pstl2strm, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x0c, 0x60, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfd pstl3keep, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x0c, 0x60, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfd pstl3keep, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x0d, 0x60, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfd pstl3strm, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x0d, 0x60, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfd pstl3strm, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x0e, 0x60, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfd #14, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x0f, 0x60, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfd #15, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x60, 0xe0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfd pldl1strm, p0, [x0, #-32, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x60, 0xdf, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfd pldl1strm, p0, [x0, #31, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfd pldl1keep, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfd pldl1keep, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x60, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfd pldl1strm, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x60, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfd pldl1strm, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x02, 0x60, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfd pldl2keep, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x02, 0x60, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfd pldl2keep, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x03, 0x60, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfd pldl2strm, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x03, 0x60, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfd pldl2strm, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x04, 0x60, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfd pldl3keep, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x04, 0x60, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfd pldl3keep, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x05, 0x60, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfd pldl3strm, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x05, 0x60, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfd pldl3strm, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x06, 0x60, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfd #6, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x07, 0x60, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfd #7, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x08, 0x60, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfd pstl1keep, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x08, 0x60, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfd pstl1keep, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x09, 0x60, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfd pstl1strm, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x09, 0x60, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfd pstl1strm, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x0a, 0x60, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfd pstl2keep, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x0a, 0x60, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfd pstl2keep, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x0b, 0x60, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfd pstl2strm, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x0b, 0x60, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfd pstl2strm, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x0c, 0x60, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfd pstl3keep, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x0c, 0x60, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfd pstl3keep, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x0d, 0x60, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfd pstl3strm, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x0d, 0x60, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfd pstl3strm, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x0e, 0x60, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfd #14, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x0f, 0x60, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfd #15, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x60, 0xe0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfd pldl1strm, p0, [x0, #-32, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x60, 0xdf, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfd pldl1strm, p0, [x0, #31, mul vl]"
diff --git a/tests/MC/AArch64/SVE/prfh-sve-only.s.yaml b/tests/MC/AArch64/SVE/prfh-sve-only.s.yaml
new file mode 100644
index 000000000..cd28e685d
--- /dev/null
+++ b/tests/MC/AArch64/SVE/prfh-sve-only.s.yaml
@@ -0,0 +1,90 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x45, 0x35, 0x35, 0x84 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfh pldl3strm, p5, [x10, z21.s, uxtw #1]"
+
+  -
+    input:
+      bytes: [ 0x45, 0x35, 0x75, 0x84 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfh pldl3strm, p5, [x10, z21.s, sxtw #1]"
+
+  -
+    input:
+      bytes: [ 0x45, 0x35, 0x35, 0xc4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfh pldl3strm, p5, [x10, z21.d, uxtw #1]"
+
+  -
+    input:
+      bytes: [ 0x45, 0x35, 0x75, 0xc4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfh pldl3strm, p5, [x10, z21.d, sxtw #1]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x60, 0xc4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfh pldl1keep, p0, [x0, z0.d, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0xef, 0xff, 0x80, 0x84 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfh #15, p7, [z31.s]"
+
+  -
+    input:
+      bytes: [ 0xef, 0xff, 0x9f, 0x84 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfh #15, p7, [z31.s, #62]"
+
+  -
+    input:
+      bytes: [ 0xef, 0xff, 0x80, 0xc4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfh #15, p7, [z31.d]"
+
+  -
+    input:
+      bytes: [ 0xef, 0xff, 0x9f, 0xc4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfh #15, p7, [z31.d, #62]"
diff --git a/tests/MC/AArch64/SVE/prfh.s.yaml b/tests/MC/AArch64/SVE/prfh.s.yaml
new file mode 100644
index 000000000..314fd1811
--- /dev/null
+++ b/tests/MC/AArch64/SVE/prfh.s.yaml
@@ -0,0 +1,600 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfh pldl1keep, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfh pldl1keep, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x20, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfh pldl1strm, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x20, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfh pldl1strm, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x02, 0x20, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfh pldl2keep, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x02, 0x20, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfh pldl2keep, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x03, 0x20, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfh pldl2strm, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x03, 0x20, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfh pldl2strm, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x04, 0x20, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfh pldl3keep, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x04, 0x20, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfh pldl3keep, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x05, 0x20, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfh pldl3strm, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x05, 0x20, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfh pldl3strm, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x06, 0x20, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfh #6, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x07, 0x20, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfh #7, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x08, 0x20, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfh pstl1keep, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x08, 0x20, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfh pstl1keep, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x09, 0x20, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfh pstl1strm, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x09, 0x20, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfh pstl1strm, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x0a, 0x20, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfh pstl2keep, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x0a, 0x20, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfh pstl2keep, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x0b, 0x20, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfh pstl2strm, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x0b, 0x20, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfh pstl2strm, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x0c, 0x20, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfh pstl3keep, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x0c, 0x20, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfh pstl3keep, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x0d, 0x20, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfh pstl3strm, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x0d, 0x20, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfh pstl3strm, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x0e, 0x20, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfh #14, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x0f, 0x20, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfh #15, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x20, 0xe0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfh pldl1strm, p0, [x0, #-32, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x20, 0xdf, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfh pldl1strm, p0, [x0, #31, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfh pldl1keep, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfh pldl1keep, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x20, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfh pldl1strm, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x20, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfh pldl1strm, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x02, 0x20, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfh pldl2keep, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x02, 0x20, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfh pldl2keep, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x03, 0x20, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfh pldl2strm, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x03, 0x20, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfh pldl2strm, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x04, 0x20, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfh pldl3keep, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x04, 0x20, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfh pldl3keep, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x05, 0x20, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfh pldl3strm, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x05, 0x20, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfh pldl3strm, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x06, 0x20, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfh #6, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x07, 0x20, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfh #7, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x08, 0x20, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfh pstl1keep, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x08, 0x20, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfh pstl1keep, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x09, 0x20, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfh pstl1strm, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x09, 0x20, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfh pstl1strm, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x0a, 0x20, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfh pstl2keep, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x0a, 0x20, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfh pstl2keep, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x0b, 0x20, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfh pstl2strm, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x0b, 0x20, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfh pstl2strm, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x0c, 0x20, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfh pstl3keep, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x0c, 0x20, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfh pstl3keep, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x0d, 0x20, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfh pstl3strm, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x0d, 0x20, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfh pstl3strm, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x0e, 0x20, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfh #14, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x0f, 0x20, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfh #15, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x20, 0xe0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfh pldl1strm, p0, [x0, #-32, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x20, 0xdf, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfh pldl1strm, p0, [x0, #31, mul vl]"
diff --git a/tests/MC/AArch64/SVE/prfw-sve-only.s.yaml b/tests/MC/AArch64/SVE/prfw-sve-only.s.yaml
new file mode 100644
index 000000000..f8fa7a5d4
--- /dev/null
+++ b/tests/MC/AArch64/SVE/prfw-sve-only.s.yaml
@@ -0,0 +1,90 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0x20, 0x84 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfw pldl1keep, p0, [x0, z0.s, uxtw #2]"
+
+  -
+    input:
+      bytes: [ 0x45, 0x55, 0x75, 0x84 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfw pldl3strm, p5, [x10, z21.s, sxtw #2]"
+
+  -
+    input:
+      bytes: [ 0xa7, 0x4d, 0x28, 0xc4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfw #7, p3, [x13, z8.d, uxtw #2]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0x60, 0xc4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfw pldl1keep, p0, [x0, z0.d, sxtw #2]"
+
+  -
+    input:
+      bytes: [ 0x45, 0xd5, 0x75, 0xc4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfw pldl3strm, p5, [x10, z21.d, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0xef, 0xff, 0x00, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfw #15, p7, [z31.s]"
+
+  -
+    input:
+      bytes: [ 0xef, 0xff, 0x1f, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfw #15, p7, [z31.s, #124]"
+
+  -
+    input:
+      bytes: [ 0xef, 0xff, 0x00, 0xc5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfw #15, p7, [z31.d]"
+
+  -
+    input:
+      bytes: [ 0xef, 0xff, 0x1f, 0xc5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfw #15, p7, [z31.d, #124]"
diff --git a/tests/MC/AArch64/SVE/prfw.s.yaml b/tests/MC/AArch64/SVE/prfw.s.yaml
new file mode 100644
index 000000000..5fafbf1c3
--- /dev/null
+++ b/tests/MC/AArch64/SVE/prfw.s.yaml
@@ -0,0 +1,600 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfw pldl1keep, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfw pldl1keep, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x40, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfw pldl1strm, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x40, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfw pldl1strm, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x02, 0x40, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfw pldl2keep, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x02, 0x40, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfw pldl2keep, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x03, 0x40, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfw pldl2strm, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x03, 0x40, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfw pldl2strm, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x04, 0x40, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfw pldl3keep, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x04, 0x40, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfw pldl3keep, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x05, 0x40, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfw pldl3strm, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x05, 0x40, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfw pldl3strm, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x06, 0x40, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfw #6, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x07, 0x40, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfw #7, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x08, 0x40, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfw pstl1keep, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x08, 0x40, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfw pstl1keep, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x09, 0x40, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfw pstl1strm, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x09, 0x40, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfw pstl1strm, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x0a, 0x40, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfw pstl2keep, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x0a, 0x40, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfw pstl2keep, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x0b, 0x40, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfw pstl2strm, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x0b, 0x40, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfw pstl2strm, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x0c, 0x40, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfw pstl3keep, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x0c, 0x40, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfw pstl3keep, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x0d, 0x40, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfw pstl3strm, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x0d, 0x40, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfw pstl3strm, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x0e, 0x40, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfw #14, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x0f, 0x40, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfw #15, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x40, 0xe0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfw pldl1strm, p0, [x0, #-32, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x40, 0xdf, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfw pldl1strm, p0, [x0, #31, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfw pldl1keep, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfw pldl1keep, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x40, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfw pldl1strm, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x40, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfw pldl1strm, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x02, 0x40, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfw pldl2keep, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x02, 0x40, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfw pldl2keep, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x03, 0x40, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfw pldl2strm, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x03, 0x40, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfw pldl2strm, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x04, 0x40, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfw pldl3keep, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x04, 0x40, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfw pldl3keep, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x05, 0x40, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfw pldl3strm, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x05, 0x40, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfw pldl3strm, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x06, 0x40, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfw #6, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x07, 0x40, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfw #7, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x08, 0x40, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfw pstl1keep, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x08, 0x40, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfw pstl1keep, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x09, 0x40, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfw pstl1strm, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x09, 0x40, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfw pstl1strm, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x0a, 0x40, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfw pstl2keep, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x0a, 0x40, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfw pstl2keep, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x0b, 0x40, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfw pstl2strm, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x0b, 0x40, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfw pstl2strm, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x0c, 0x40, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfw pstl3keep, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x0c, 0x40, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfw pstl3keep, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x0d, 0x40, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfw pstl3strm, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x0d, 0x40, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfw pstl3strm, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x0e, 0x40, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfw #14, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x0f, 0x40, 0xc0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfw #15, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x40, 0xe0, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfw pldl1strm, p0, [x0, #-32, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x40, 0xdf, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfw pldl1strm, p0, [x0, #31, mul vl]"
diff --git a/tests/MC/AArch64/SVE/ptest.s.yaml b/tests/MC/AArch64/SVE/ptest.s.yaml
new file mode 100644
index 000000000..e866915e9
--- /dev/null
+++ b/tests/MC/AArch64/SVE/ptest.s.yaml
@@ -0,0 +1,40 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xfc, 0x50, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptest p15, p0.b"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xfd, 0x50, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptest p15, p15.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0xfc, 0x50, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptest p15, p0.b"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xfd, 0x50, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptest p15, p15.b"
diff --git a/tests/MC/AArch64/SVE/ptrue.s.yaml b/tests/MC/AArch64/SVE/ptrue.s.yaml
new file mode 100644
index 000000000..ba23ba760
--- /dev/null
+++ b/tests/MC/AArch64/SVE/ptrue.s.yaml
@@ -0,0 +1,800 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x18, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrue p0.b, pow2"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x58, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrue p0.h, pow2"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x98, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrue p0.s, pow2"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xd8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrue p0.d, pow2"
+
+  -
+    input:
+      bytes: [ 0xef, 0xe3, 0x18, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrue p15.b"
+
+  -
+    input:
+      bytes: [ 0xef, 0xe3, 0x58, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrue p15.h"
+
+  -
+    input:
+      bytes: [ 0xef, 0xe3, 0x98, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrue p15.s"
+
+  -
+    input:
+      bytes: [ 0xef, 0xe3, 0xd8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrue p15.d"
+
+  -
+    input:
+      bytes: [ 0x27, 0xe0, 0x98, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrue p7.s, vl1"
+
+  -
+    input:
+      bytes: [ 0x27, 0xe0, 0x98, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrue p7.s, vl1"
+
+  -
+    input:
+      bytes: [ 0x47, 0xe0, 0x98, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrue p7.s, vl2"
+
+  -
+    input:
+      bytes: [ 0x67, 0xe0, 0x98, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrue p7.s, vl3"
+
+  -
+    input:
+      bytes: [ 0x87, 0xe0, 0x98, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrue p7.s, vl4"
+
+  -
+    input:
+      bytes: [ 0xa7, 0xe0, 0x98, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrue p7.s, vl5"
+
+  -
+    input:
+      bytes: [ 0xc7, 0xe0, 0x98, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrue p7.s, vl6"
+
+  -
+    input:
+      bytes: [ 0xe7, 0xe0, 0x98, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrue p7.s, vl7"
+
+  -
+    input:
+      bytes: [ 0x07, 0xe1, 0x98, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrue p7.s, vl8"
+
+  -
+    input:
+      bytes: [ 0x27, 0xe1, 0x98, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrue p7.s, vl16"
+
+  -
+    input:
+      bytes: [ 0x47, 0xe1, 0x98, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrue p7.s, vl32"
+
+  -
+    input:
+      bytes: [ 0x67, 0xe1, 0x98, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrue p7.s, vl64"
+
+  -
+    input:
+      bytes: [ 0x87, 0xe1, 0x98, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrue p7.s, vl128"
+
+  -
+    input:
+      bytes: [ 0xa7, 0xe1, 0x98, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrue p7.s, vl256"
+
+  -
+    input:
+      bytes: [ 0xa7, 0xe3, 0x98, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrue p7.s, mul4"
+
+  -
+    input:
+      bytes: [ 0xc7, 0xe3, 0x98, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrue p7.s, mul3"
+
+  -
+    input:
+      bytes: [ 0xe7, 0xe3, 0x98, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrue p7.s"
+
+  -
+    input:
+      bytes: [ 0xc7, 0xe1, 0x98, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrue p7.s, #14"
+
+  -
+    input:
+      bytes: [ 0xe7, 0xe1, 0x98, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrue p7.s, #15"
+
+  -
+    input:
+      bytes: [ 0x07, 0xe2, 0x98, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrue p7.s, #16"
+
+  -
+    input:
+      bytes: [ 0x27, 0xe2, 0x98, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrue p7.s, #17"
+
+  -
+    input:
+      bytes: [ 0x47, 0xe2, 0x98, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrue p7.s, #18"
+
+  -
+    input:
+      bytes: [ 0x67, 0xe2, 0x98, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrue p7.s, #19"
+
+  -
+    input:
+      bytes: [ 0x87, 0xe2, 0x98, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrue p7.s, #20"
+
+  -
+    input:
+      bytes: [ 0xa7, 0xe2, 0x98, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrue p7.s, #21"
+
+  -
+    input:
+      bytes: [ 0xc7, 0xe2, 0x98, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrue p7.s, #22"
+
+  -
+    input:
+      bytes: [ 0xe7, 0xe2, 0x98, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrue p7.s, #23"
+
+  -
+    input:
+      bytes: [ 0x07, 0xe3, 0x98, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrue p7.s, #24"
+
+  -
+    input:
+      bytes: [ 0x27, 0xe3, 0x98, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrue p7.s, #25"
+
+  -
+    input:
+      bytes: [ 0x47, 0xe3, 0x98, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrue p7.s, #26"
+
+  -
+    input:
+      bytes: [ 0x67, 0xe3, 0x98, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrue p7.s, #27"
+
+  -
+    input:
+      bytes: [ 0x87, 0xe3, 0x98, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrue p7.s, #28"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x18, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrue p0.b, pow2"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x58, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrue p0.h, pow2"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x98, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrue p0.s, pow2"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xd8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrue p0.d, pow2"
+
+  -
+    input:
+      bytes: [ 0xef, 0xe3, 0x18, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrue p15.b"
+
+  -
+    input:
+      bytes: [ 0xef, 0xe3, 0x58, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrue p15.h"
+
+  -
+    input:
+      bytes: [ 0xef, 0xe3, 0x98, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrue p15.s"
+
+  -
+    input:
+      bytes: [ 0xef, 0xe3, 0xd8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrue p15.d"
+
+  -
+    input:
+      bytes: [ 0x27, 0xe0, 0x98, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrue p7.s, vl1"
+
+  -
+    input:
+      bytes: [ 0x27, 0xe0, 0x98, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrue p7.s, vl1"
+
+  -
+    input:
+      bytes: [ 0x47, 0xe0, 0x98, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrue p7.s, vl2"
+
+  -
+    input:
+      bytes: [ 0x67, 0xe0, 0x98, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrue p7.s, vl3"
+
+  -
+    input:
+      bytes: [ 0x87, 0xe0, 0x98, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrue p7.s, vl4"
+
+  -
+    input:
+      bytes: [ 0xa7, 0xe0, 0x98, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrue p7.s, vl5"
+
+  -
+    input:
+      bytes: [ 0xc7, 0xe0, 0x98, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrue p7.s, vl6"
+
+  -
+    input:
+      bytes: [ 0xe7, 0xe0, 0x98, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrue p7.s, vl7"
+
+  -
+    input:
+      bytes: [ 0x07, 0xe1, 0x98, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrue p7.s, vl8"
+
+  -
+    input:
+      bytes: [ 0x27, 0xe1, 0x98, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrue p7.s, vl16"
+
+  -
+    input:
+      bytes: [ 0x47, 0xe1, 0x98, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrue p7.s, vl32"
+
+  -
+    input:
+      bytes: [ 0x67, 0xe1, 0x98, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrue p7.s, vl64"
+
+  -
+    input:
+      bytes: [ 0x87, 0xe1, 0x98, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrue p7.s, vl128"
+
+  -
+    input:
+      bytes: [ 0xa7, 0xe1, 0x98, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrue p7.s, vl256"
+
+  -
+    input:
+      bytes: [ 0xa7, 0xe3, 0x98, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrue p7.s, mul4"
+
+  -
+    input:
+      bytes: [ 0xc7, 0xe3, 0x98, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrue p7.s, mul3"
+
+  -
+    input:
+      bytes: [ 0xe7, 0xe3, 0x98, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrue p7.s"
+
+  -
+    input:
+      bytes: [ 0xc7, 0xe1, 0x98, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrue p7.s, #14"
+
+  -
+    input:
+      bytes: [ 0xe7, 0xe1, 0x98, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrue p7.s, #15"
+
+  -
+    input:
+      bytes: [ 0x07, 0xe2, 0x98, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrue p7.s, #16"
+
+  -
+    input:
+      bytes: [ 0x27, 0xe2, 0x98, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrue p7.s, #17"
+
+  -
+    input:
+      bytes: [ 0x47, 0xe2, 0x98, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrue p7.s, #18"
+
+  -
+    input:
+      bytes: [ 0x67, 0xe2, 0x98, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrue p7.s, #19"
+
+  -
+    input:
+      bytes: [ 0x87, 0xe2, 0x98, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrue p7.s, #20"
+
+  -
+    input:
+      bytes: [ 0xa7, 0xe2, 0x98, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrue p7.s, #21"
+
+  -
+    input:
+      bytes: [ 0xc7, 0xe2, 0x98, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrue p7.s, #22"
+
+  -
+    input:
+      bytes: [ 0xe7, 0xe2, 0x98, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrue p7.s, #23"
+
+  -
+    input:
+      bytes: [ 0x07, 0xe3, 0x98, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrue p7.s, #24"
+
+  -
+    input:
+      bytes: [ 0x27, 0xe3, 0x98, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrue p7.s, #25"
+
+  -
+    input:
+      bytes: [ 0x47, 0xe3, 0x98, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrue p7.s, #26"
+
+  -
+    input:
+      bytes: [ 0x67, 0xe3, 0x98, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrue p7.s, #27"
+
+  -
+    input:
+      bytes: [ 0x87, 0xe3, 0x98, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrue p7.s, #28"
diff --git a/tests/MC/AArch64/SVE/ptrues.s.yaml b/tests/MC/AArch64/SVE/ptrues.s.yaml
new file mode 100644
index 000000000..13583c8c4
--- /dev/null
+++ b/tests/MC/AArch64/SVE/ptrues.s.yaml
@@ -0,0 +1,800 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x19, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrues p0.b, pow2"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x59, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrues p0.h, pow2"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x99, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrues p0.s, pow2"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xd9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrues p0.d, pow2"
+
+  -
+    input:
+      bytes: [ 0xef, 0xe3, 0x19, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrues p15.b"
+
+  -
+    input:
+      bytes: [ 0xef, 0xe3, 0x59, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrues p15.h"
+
+  -
+    input:
+      bytes: [ 0xef, 0xe3, 0x99, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrues p15.s"
+
+  -
+    input:
+      bytes: [ 0xef, 0xe3, 0xd9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrues p15.d"
+
+  -
+    input:
+      bytes: [ 0x27, 0xe0, 0x99, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrues p7.s, vl1"
+
+  -
+    input:
+      bytes: [ 0x27, 0xe0, 0x99, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrues p7.s, vl1"
+
+  -
+    input:
+      bytes: [ 0x47, 0xe0, 0x99, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrues p7.s, vl2"
+
+  -
+    input:
+      bytes: [ 0x67, 0xe0, 0x99, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrues p7.s, vl3"
+
+  -
+    input:
+      bytes: [ 0x87, 0xe0, 0x99, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrues p7.s, vl4"
+
+  -
+    input:
+      bytes: [ 0xa7, 0xe0, 0x99, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrues p7.s, vl5"
+
+  -
+    input:
+      bytes: [ 0xc7, 0xe0, 0x99, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrues p7.s, vl6"
+
+  -
+    input:
+      bytes: [ 0xe7, 0xe0, 0x99, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrues p7.s, vl7"
+
+  -
+    input:
+      bytes: [ 0x07, 0xe1, 0x99, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrues p7.s, vl8"
+
+  -
+    input:
+      bytes: [ 0x27, 0xe1, 0x99, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrues p7.s, vl16"
+
+  -
+    input:
+      bytes: [ 0x47, 0xe1, 0x99, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrues p7.s, vl32"
+
+  -
+    input:
+      bytes: [ 0x67, 0xe1, 0x99, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrues p7.s, vl64"
+
+  -
+    input:
+      bytes: [ 0x87, 0xe1, 0x99, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrues p7.s, vl128"
+
+  -
+    input:
+      bytes: [ 0xa7, 0xe1, 0x99, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrues p7.s, vl256"
+
+  -
+    input:
+      bytes: [ 0xa7, 0xe3, 0x99, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrues p7.s, mul4"
+
+  -
+    input:
+      bytes: [ 0xc7, 0xe3, 0x99, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrues p7.s, mul3"
+
+  -
+    input:
+      bytes: [ 0xe7, 0xe3, 0x99, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrues p7.s"
+
+  -
+    input:
+      bytes: [ 0xc7, 0xe1, 0x99, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrues p7.s, #14"
+
+  -
+    input:
+      bytes: [ 0xe7, 0xe1, 0x99, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrues p7.s, #15"
+
+  -
+    input:
+      bytes: [ 0x07, 0xe2, 0x99, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrues p7.s, #16"
+
+  -
+    input:
+      bytes: [ 0x27, 0xe2, 0x99, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrues p7.s, #17"
+
+  -
+    input:
+      bytes: [ 0x47, 0xe2, 0x99, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrues p7.s, #18"
+
+  -
+    input:
+      bytes: [ 0x67, 0xe2, 0x99, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrues p7.s, #19"
+
+  -
+    input:
+      bytes: [ 0x87, 0xe2, 0x99, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrues p7.s, #20"
+
+  -
+    input:
+      bytes: [ 0xa7, 0xe2, 0x99, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrues p7.s, #21"
+
+  -
+    input:
+      bytes: [ 0xc7, 0xe2, 0x99, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrues p7.s, #22"
+
+  -
+    input:
+      bytes: [ 0xe7, 0xe2, 0x99, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrues p7.s, #23"
+
+  -
+    input:
+      bytes: [ 0x07, 0xe3, 0x99, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrues p7.s, #24"
+
+  -
+    input:
+      bytes: [ 0x27, 0xe3, 0x99, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrues p7.s, #25"
+
+  -
+    input:
+      bytes: [ 0x47, 0xe3, 0x99, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrues p7.s, #26"
+
+  -
+    input:
+      bytes: [ 0x67, 0xe3, 0x99, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrues p7.s, #27"
+
+  -
+    input:
+      bytes: [ 0x87, 0xe3, 0x99, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrues p7.s, #28"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x19, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrues p0.b, pow2"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x59, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrues p0.h, pow2"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x99, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrues p0.s, pow2"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xd9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrues p0.d, pow2"
+
+  -
+    input:
+      bytes: [ 0xef, 0xe3, 0x19, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrues p15.b"
+
+  -
+    input:
+      bytes: [ 0xef, 0xe3, 0x59, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrues p15.h"
+
+  -
+    input:
+      bytes: [ 0xef, 0xe3, 0x99, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrues p15.s"
+
+  -
+    input:
+      bytes: [ 0xef, 0xe3, 0xd9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrues p15.d"
+
+  -
+    input:
+      bytes: [ 0x27, 0xe0, 0x99, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrues p7.s, vl1"
+
+  -
+    input:
+      bytes: [ 0x27, 0xe0, 0x99, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrues p7.s, vl1"
+
+  -
+    input:
+      bytes: [ 0x47, 0xe0, 0x99, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrues p7.s, vl2"
+
+  -
+    input:
+      bytes: [ 0x67, 0xe0, 0x99, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrues p7.s, vl3"
+
+  -
+    input:
+      bytes: [ 0x87, 0xe0, 0x99, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrues p7.s, vl4"
+
+  -
+    input:
+      bytes: [ 0xa7, 0xe0, 0x99, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrues p7.s, vl5"
+
+  -
+    input:
+      bytes: [ 0xc7, 0xe0, 0x99, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrues p7.s, vl6"
+
+  -
+    input:
+      bytes: [ 0xe7, 0xe0, 0x99, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrues p7.s, vl7"
+
+  -
+    input:
+      bytes: [ 0x07, 0xe1, 0x99, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrues p7.s, vl8"
+
+  -
+    input:
+      bytes: [ 0x27, 0xe1, 0x99, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrues p7.s, vl16"
+
+  -
+    input:
+      bytes: [ 0x47, 0xe1, 0x99, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrues p7.s, vl32"
+
+  -
+    input:
+      bytes: [ 0x67, 0xe1, 0x99, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrues p7.s, vl64"
+
+  -
+    input:
+      bytes: [ 0x87, 0xe1, 0x99, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrues p7.s, vl128"
+
+  -
+    input:
+      bytes: [ 0xa7, 0xe1, 0x99, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrues p7.s, vl256"
+
+  -
+    input:
+      bytes: [ 0xa7, 0xe3, 0x99, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrues p7.s, mul4"
+
+  -
+    input:
+      bytes: [ 0xc7, 0xe3, 0x99, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrues p7.s, mul3"
+
+  -
+    input:
+      bytes: [ 0xe7, 0xe3, 0x99, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrues p7.s"
+
+  -
+    input:
+      bytes: [ 0xc7, 0xe1, 0x99, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrues p7.s, #14"
+
+  -
+    input:
+      bytes: [ 0xe7, 0xe1, 0x99, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrues p7.s, #15"
+
+  -
+    input:
+      bytes: [ 0x07, 0xe2, 0x99, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrues p7.s, #16"
+
+  -
+    input:
+      bytes: [ 0x27, 0xe2, 0x99, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrues p7.s, #17"
+
+  -
+    input:
+      bytes: [ 0x47, 0xe2, 0x99, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrues p7.s, #18"
+
+  -
+    input:
+      bytes: [ 0x67, 0xe2, 0x99, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrues p7.s, #19"
+
+  -
+    input:
+      bytes: [ 0x87, 0xe2, 0x99, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrues p7.s, #20"
+
+  -
+    input:
+      bytes: [ 0xa7, 0xe2, 0x99, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrues p7.s, #21"
+
+  -
+    input:
+      bytes: [ 0xc7, 0xe2, 0x99, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrues p7.s, #22"
+
+  -
+    input:
+      bytes: [ 0xe7, 0xe2, 0x99, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrues p7.s, #23"
+
+  -
+    input:
+      bytes: [ 0x07, 0xe3, 0x99, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrues p7.s, #24"
+
+  -
+    input:
+      bytes: [ 0x27, 0xe3, 0x99, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrues p7.s, #25"
+
+  -
+    input:
+      bytes: [ 0x47, 0xe3, 0x99, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrues p7.s, #26"
+
+  -
+    input:
+      bytes: [ 0x67, 0xe3, 0x99, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrues p7.s, #27"
+
+  -
+    input:
+      bytes: [ 0x87, 0xe3, 0x99, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrues p7.s, #28"
diff --git a/tests/MC/AArch64/SVE/punpkhi.s.yaml b/tests/MC/AArch64/SVE/punpkhi.s.yaml
new file mode 100644
index 000000000..a36338b2c
--- /dev/null
+++ b/tests/MC/AArch64/SVE/punpkhi.s.yaml
@@ -0,0 +1,40 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0x31, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "punpkhi p0.h, p0.b"
+
+  -
+    input:
+      bytes: [ 0xef, 0x41, 0x31, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "punpkhi p15.h, p15.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0x31, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "punpkhi p0.h, p0.b"
+
+  -
+    input:
+      bytes: [ 0xef, 0x41, 0x31, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "punpkhi p15.h, p15.b"
diff --git a/tests/MC/AArch64/SVE/punpklo.s.yaml b/tests/MC/AArch64/SVE/punpklo.s.yaml
new file mode 100644
index 000000000..57d2c99f5
--- /dev/null
+++ b/tests/MC/AArch64/SVE/punpklo.s.yaml
@@ -0,0 +1,40 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0x30, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "punpklo p0.h, p0.b"
+
+  -
+    input:
+      bytes: [ 0xef, 0x41, 0x30, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "punpklo p15.h, p15.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0x30, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "punpklo p0.h, p0.b"
+
+  -
+    input:
+      bytes: [ 0xef, 0x41, 0x30, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "punpklo p15.h, p15.b"
diff --git a/tests/MC/AArch64/SVE/rbit.s.yaml b/tests/MC/AArch64/SVE/rbit.s.yaml
new file mode 100644
index 000000000..3f8996115
--- /dev/null
+++ b/tests/MC/AArch64/SVE/rbit.s.yaml
@@ -0,0 +1,160 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0x27, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "rbit z0.b, p7/m, z31.b"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0x67, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "rbit z0.h, p7/m, z31.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xa7, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "rbit z0.s, p7/m, z31.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xe7, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "rbit z0.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0.d, p7/z, z7.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xe7, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "rbit z0.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xe7, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "rbit z0.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0x27, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "rbit z0.b, p7/m, z31.b"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0x67, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "rbit z0.h, p7/m, z31.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xa7, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "rbit z0.s, p7/m, z31.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xe7, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "rbit z0.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0.d, p7/z, z7.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xe7, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "rbit z0.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xe7, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "rbit z0.d, p7/m, z31.d"
diff --git a/tests/MC/AArch64/SVE/rdffr.s.yaml b/tests/MC/AArch64/SVE/rdffr.s.yaml
new file mode 100644
index 000000000..9493ff706
--- /dev/null
+++ b/tests/MC/AArch64/SVE/rdffr.s.yaml
@@ -0,0 +1,40 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xf0, 0x19, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "rdffr p0.b"
+
+  -
+    input:
+      bytes: [ 0x0f, 0xf0, 0x19, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "rdffr p15.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf0, 0x18, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "rdffr p0.b, p0/z"
+
+  -
+    input:
+      bytes: [ 0xef, 0xf1, 0x18, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "rdffr p15.b, p15/z"
diff --git a/tests/MC/AArch64/SVE/rdffrs.s.yaml b/tests/MC/AArch64/SVE/rdffrs.s.yaml
new file mode 100644
index 000000000..13a0705f3
--- /dev/null
+++ b/tests/MC/AArch64/SVE/rdffrs.s.yaml
@@ -0,0 +1,20 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xf0, 0x58, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "rdffrs p0.b, p0/z"
+
+  -
+    input:
+      bytes: [ 0xef, 0xf1, 0x58, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "rdffrs p15.b, p15/z"
diff --git a/tests/MC/AArch64/SVE/rdvl.s.yaml b/tests/MC/AArch64/SVE/rdvl.s.yaml
new file mode 100644
index 000000000..770fd096e
--- /dev/null
+++ b/tests/MC/AArch64/SVE/rdvl.s.yaml
@@ -0,0 +1,80 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x50, 0xbf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "rdvl x0, #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0x57, 0xbf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "rdvl xzr, #-1"
+
+  -
+    input:
+      bytes: [ 0xf7, 0x53, 0xbf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "rdvl x23, #31"
+
+  -
+    input:
+      bytes: [ 0x15, 0x54, 0xbf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "rdvl x21, #-32"
+
+  -
+    input:
+      bytes: [ 0x00, 0x50, 0xbf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "rdvl x0, #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0x57, 0xbf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "rdvl xzr, #-1"
+
+  -
+    input:
+      bytes: [ 0xf7, 0x53, 0xbf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "rdvl x23, #31"
+
+  -
+    input:
+      bytes: [ 0x15, 0x54, 0xbf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "rdvl x21, #-32"
diff --git a/tests/MC/AArch64/SVE/rev.s.yaml b/tests/MC/AArch64/SVE/rev.s.yaml
new file mode 100644
index 000000000..b1ec86e6b
--- /dev/null
+++ b/tests/MC/AArch64/SVE/rev.s.yaml
@@ -0,0 +1,80 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xe0, 0x3b, 0x38, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "rev z0.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3b, 0x78, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "rev z0.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3b, 0xb8, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "rev z0.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3b, 0xf8, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "rev z0.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3b, 0x38, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "rev z0.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3b, 0x78, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "rev z0.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3b, 0xb8, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "rev z0.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3b, 0xf8, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "rev z0.d, z31.d"
diff --git a/tests/MC/AArch64/SVE/revb.s.yaml b/tests/MC/AArch64/SVE/revb.s.yaml
new file mode 100644
index 000000000..94749e201
--- /dev/null
+++ b/tests/MC/AArch64/SVE/revb.s.yaml
@@ -0,0 +1,140 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0x64, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "revb z0.h, p7/m, z31.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xa4, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "revb z0.s, p7/m, z31.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xe4, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "revb z0.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0.d, p7/z, z7.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xe4, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "revb z0.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xe4, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "revb z0.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0x64, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "revb z0.h, p7/m, z31.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xa4, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "revb z0.s, p7/m, z31.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xe4, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "revb z0.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0.d, p7/z, z7.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xe4, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "revb z0.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xe4, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "revb z0.d, p7/m, z31.d"
diff --git a/tests/MC/AArch64/SVE/revh.s.yaml b/tests/MC/AArch64/SVE/revh.s.yaml
new file mode 100644
index 000000000..e1798344f
--- /dev/null
+++ b/tests/MC/AArch64/SVE/revh.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xa5, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "revh z0.s, p7/m, z31.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xe5, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "revh z0.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0.d, p7/z, z7.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xe5, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "revh z0.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xe5, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "revh z0.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xa5, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "revh z0.s, p7/m, z31.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xe5, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "revh z0.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0.d, p7/z, z7.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xe5, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "revh z0.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xe5, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "revh z0.d, p7/m, z31.d"
diff --git a/tests/MC/AArch64/SVE/revw.s.yaml b/tests/MC/AArch64/SVE/revw.s.yaml
new file mode 100644
index 000000000..751fa634c
--- /dev/null
+++ b/tests/MC/AArch64/SVE/revw.s.yaml
@@ -0,0 +1,100 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xe6, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "revw z0.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0.d, p7/z, z7.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xe6, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "revw z0.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xe6, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "revw z0.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xe6, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "revw z0.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0.d, p7/z, z7.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xe6, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "revw z0.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9f, 0xe6, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "revw z0.d, p7/m, z31.d"
diff --git a/tests/MC/AArch64/SVE/sabd.s.yaml b/tests/MC/AArch64/SVE/sabd.s.yaml
new file mode 100644
index 000000000..f74006645
--- /dev/null
+++ b/tests/MC/AArch64/SVE/sabd.s.yaml
@@ -0,0 +1,160 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0x0c, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sabd z31.b, p7/m, z31.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0x4c, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sabd z31.h, p7/m, z31.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0x8c, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sabd z31.s, p7/m, z31.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0xcc, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sabd z31.d, p7/m, z31.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4.d, p7/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xe4, 0x1f, 0xcc, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sabd z4.d, p7/m, z4.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4, z6"
+
+  -
+    input:
+      bytes: [ 0xe4, 0x1f, 0xcc, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sabd z4.d, p7/m, z4.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0x0c, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sabd z31.b, p7/m, z31.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0x4c, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sabd z31.h, p7/m, z31.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0x8c, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sabd z31.s, p7/m, z31.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0xcc, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sabd z31.d, p7/m, z31.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4.d, p7/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xe4, 0x1f, 0xcc, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sabd z4.d, p7/m, z4.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4, z6"
+
+  -
+    input:
+      bytes: [ 0xe4, 0x1f, 0xcc, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sabd z4.d, p7/m, z4.d, z31.d"
diff --git a/tests/MC/AArch64/SVE/saddv.s.yaml b/tests/MC/AArch64/SVE/saddv.s.yaml
new file mode 100644
index 000000000..43d64e9a0
--- /dev/null
+++ b/tests/MC/AArch64/SVE/saddv.s.yaml
@@ -0,0 +1,60 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xe0, 0x3f, 0x00, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "saddv d0, p7, z31.b"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3f, 0x40, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "saddv d0, p7, z31.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3f, 0x80, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "saddv d0, p7, z31.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3f, 0x00, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "saddv d0, p7, z31.b"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3f, 0x40, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "saddv d0, p7, z31.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3f, 0x80, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "saddv d0, p7, z31.s"
diff --git a/tests/MC/AArch64/SVE/scvtf.s.yaml b/tests/MC/AArch64/SVE/scvtf.s.yaml
new file mode 100644
index 000000000..5f2bc2b2a
--- /dev/null
+++ b/tests/MC/AArch64/SVE/scvtf.s.yaml
@@ -0,0 +1,220 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x52, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "scvtf z0.h, p0/m, z0.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x54, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "scvtf z0.h, p0/m, z0.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x56, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "scvtf z0.h, p0/m, z0.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x94, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "scvtf z0.s, p0/m, z0.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xd4, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "scvtf z0.s, p0/m, z0.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xd0, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "scvtf z0.d, p0/m, z0.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xd6, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "scvtf z0.d, p0/m, z0.d"
+
+  -
+    input:
+      bytes: [ 0xe5, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z5.d, p0/z, z7.d"
+
+  -
+    input:
+      bytes: [ 0x05, 0xa0, 0xd6, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "scvtf z5.d, p0/m, z0.d"
+
+  -
+    input:
+      bytes: [ 0xe5, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z5, z7"
+
+  -
+    input:
+      bytes: [ 0x05, 0xa0, 0xd6, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "scvtf z5.d, p0/m, z0.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x52, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "scvtf z0.h, p0/m, z0.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x54, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "scvtf z0.h, p0/m, z0.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x56, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "scvtf z0.h, p0/m, z0.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x94, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "scvtf z0.s, p0/m, z0.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xd4, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "scvtf z0.s, p0/m, z0.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xd0, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "scvtf z0.d, p0/m, z0.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xd6, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "scvtf z0.d, p0/m, z0.d"
+
+  -
+    input:
+      bytes: [ 0xe5, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z5.d, p0/z, z7.d"
+
+  -
+    input:
+      bytes: [ 0x05, 0xa0, 0xd6, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "scvtf z5.d, p0/m, z0.d"
+
+  -
+    input:
+      bytes: [ 0xe5, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z5, z7"
+
+  -
+    input:
+      bytes: [ 0x05, 0xa0, 0xd6, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "scvtf z5.d, p0/m, z0.d"
diff --git a/tests/MC/AArch64/SVE/sdiv.s.yaml b/tests/MC/AArch64/SVE/sdiv.s.yaml
new file mode 100644
index 000000000..9132d639a
--- /dev/null
+++ b/tests/MC/AArch64/SVE/sdiv.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xe0, 0x1f, 0x94, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdiv z0.s, p7/m, z0.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x1f, 0xd4, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdiv z0.d, p7/m, z0.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0.d, p7/z, z7.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x1f, 0xd4, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdiv z0.d, p7/m, z0.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x1f, 0xd4, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdiv z0.d, p7/m, z0.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x1f, 0x94, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdiv z0.s, p7/m, z0.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x1f, 0xd4, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdiv z0.d, p7/m, z0.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0.d, p7/z, z7.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x1f, 0xd4, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdiv z0.d, p7/m, z0.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x1f, 0xd4, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdiv z0.d, p7/m, z0.d, z31.d"
diff --git a/tests/MC/AArch64/SVE/sdivr.s.yaml b/tests/MC/AArch64/SVE/sdivr.s.yaml
new file mode 100644
index 000000000..848cecc8c
--- /dev/null
+++ b/tests/MC/AArch64/SVE/sdivr.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xe0, 0x1f, 0x96, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdivr z0.s, p7/m, z0.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x1f, 0xd6, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdivr z0.d, p7/m, z0.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0.d, p7/z, z7.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x1f, 0xd6, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdivr z0.d, p7/m, z0.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x1f, 0xd6, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdivr z0.d, p7/m, z0.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x1f, 0x96, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdivr z0.s, p7/m, z0.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x1f, 0xd6, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdivr z0.d, p7/m, z0.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0.d, p7/z, z7.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x1f, 0xd6, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdivr z0.d, p7/m, z0.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x1f, 0xd6, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdivr z0.d, p7/m, z0.d, z31.d"
diff --git a/tests/MC/AArch64/SVE/sdot.s.yaml b/tests/MC/AArch64/SVE/sdot.s.yaml
new file mode 100644
index 000000000..b9f065916
--- /dev/null
+++ b/tests/MC/AArch64/SVE/sdot.s.yaml
@@ -0,0 +1,160 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x00, 0x9f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot z0.s, z1.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x00, 0xdf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot z0.d, z1.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x00, 0xbf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot z0.s, z1.b, z7.b[3]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x00, 0xff, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot z0.d, z1.h, z15.h[1]"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x20, 0x00, 0xdf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot z0.d, z1.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x20, 0x00, 0xff, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot z0.d, z1.h, z15.h[1]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x00, 0x9f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot z0.s, z1.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x00, 0xdf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot z0.d, z1.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x00, 0xbf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot z0.s, z1.b, z7.b[3]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x00, 0xff, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot z0.d, z1.h, z15.h[1]"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x20, 0x00, 0xdf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot z0.d, z1.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x20, 0x00, 0xff, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot z0.d, z1.h, z15.h[1]"
diff --git a/tests/MC/AArch64/SVE/sel.s.yaml b/tests/MC/AArch64/SVE/sel.s.yaml
new file mode 100644
index 000000000..9dd075e26
--- /dev/null
+++ b/tests/MC/AArch64/SVE/sel.s.yaml
@@ -0,0 +1,200 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x10, 0x42, 0x00, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov p0.b, p0/m, p0.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x7f, 0x0f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov p15.b, p15/m, p15.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0x3f, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z31.b, p15/m, z31.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0x7f, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z31.h, p15/m, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xbf, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z31.s, p15/m, z31.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xff, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z31.d, p15/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0xa8, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sel z23.s, p11, z13.s, z8.s"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0xe8, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sel z23.d, p11, z13.d, z8.d"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0x68, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sel z23.h, p11, z13.h, z8.h"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0x28, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sel z23.b, p11, z13.b, z8.b"
+
+  -
+    input:
+      bytes: [ 0x10, 0x42, 0x00, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov p0.b, p0/m, p0.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x7f, 0x0f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov p15.b, p15/m, p15.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0x3f, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z31.b, p15/m, z31.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0x7f, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z31.h, p15/m, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xbf, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z31.s, p15/m, z31.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xff, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov z31.d, p15/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0xa8, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sel z23.s, p11, z13.s, z8.s"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0xe8, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sel z23.d, p11, z13.d, z8.d"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0x68, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sel z23.h, p11, z13.h, z8.h"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0x28, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sel z23.b, p11, z13.b, z8.b"
diff --git a/tests/MC/AArch64/SVE/setffr.s.yaml b/tests/MC/AArch64/SVE/setffr.s.yaml
new file mode 100644
index 000000000..98b9fbb02
--- /dev/null
+++ b/tests/MC/AArch64/SVE/setffr.s.yaml
@@ -0,0 +1,10 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x90, 0x2c, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "setffr"
diff --git a/tests/MC/AArch64/SVE/smax.s.yaml b/tests/MC/AArch64/SVE/smax.s.yaml
new file mode 100644
index 000000000..b331f946a
--- /dev/null
+++ b/tests/MC/AArch64/SVE/smax.s.yaml
@@ -0,0 +1,360 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xd0, 0x28, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax z0.b, z0.b, #-128"
+
+  -
+    input:
+      bytes: [ 0xff, 0xcf, 0x28, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax z31.b, z31.b, #127"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd0, 0x68, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax z0.h, z0.h, #-128"
+
+  -
+    input:
+      bytes: [ 0xff, 0xcf, 0x68, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax z31.h, z31.h, #127"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd0, 0xa8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax z0.s, z0.s, #-128"
+
+  -
+    input:
+      bytes: [ 0xff, 0xcf, 0xa8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax z31.s, z31.s, #127"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd0, 0xe8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax z0.d, z0.d, #-128"
+
+  -
+    input:
+      bytes: [ 0xff, 0xcf, 0xe8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax z31.d, z31.d, #127"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0x08, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax z31.b, p7/m, z31.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0x48, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax z31.h, p7/m, z31.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0x88, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax z31.s, p7/m, z31.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0xc8, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax z31.d, p7/m, z31.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4.d, p7/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xe4, 0x1f, 0xc8, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax z4.d, p7/m, z4.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4, z6"
+
+  -
+    input:
+      bytes: [ 0xe4, 0x1f, 0xc8, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax z4.d, p7/m, z4.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xff, 0xcf, 0xe8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax z31.d, z31.d, #127"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd0, 0x28, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax z0.b, z0.b, #-128"
+
+  -
+    input:
+      bytes: [ 0xff, 0xcf, 0x28, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax z31.b, z31.b, #127"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd0, 0x68, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax z0.h, z0.h, #-128"
+
+  -
+    input:
+      bytes: [ 0xff, 0xcf, 0x68, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax z31.h, z31.h, #127"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd0, 0xa8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax z0.s, z0.s, #-128"
+
+  -
+    input:
+      bytes: [ 0xff, 0xcf, 0xa8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax z31.s, z31.s, #127"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd0, 0xe8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax z0.d, z0.d, #-128"
+
+  -
+    input:
+      bytes: [ 0xff, 0xcf, 0xe8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax z31.d, z31.d, #127"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0x08, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax z31.b, p7/m, z31.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0x48, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax z31.h, p7/m, z31.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0x88, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax z31.s, p7/m, z31.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0xc8, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax z31.d, p7/m, z31.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4.d, p7/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xe4, 0x1f, 0xc8, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax z4.d, p7/m, z4.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4, z6"
+
+  -
+    input:
+      bytes: [ 0xe4, 0x1f, 0xc8, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax z4.d, p7/m, z4.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xff, 0xcf, 0xe8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax z31.d, z31.d, #127"
diff --git a/tests/MC/AArch64/SVE/smaxv.s.yaml b/tests/MC/AArch64/SVE/smaxv.s.yaml
new file mode 100644
index 000000000..4256fca55
--- /dev/null
+++ b/tests/MC/AArch64/SVE/smaxv.s.yaml
@@ -0,0 +1,80 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xe0, 0x3f, 0x08, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "smaxv b0, p7, z31.b"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3f, 0x48, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "smaxv h0, p7, z31.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3f, 0x88, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "smaxv s0, p7, z31.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3f, 0xc8, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "smaxv d0, p7, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3f, 0x08, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smaxv b0, p7, z31.b"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3f, 0x48, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smaxv h0, p7, z31.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3f, 0x88, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smaxv s0, p7, z31.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3f, 0xc8, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smaxv d0, p7, z31.d"
diff --git a/tests/MC/AArch64/SVE/smin.s.yaml b/tests/MC/AArch64/SVE/smin.s.yaml
new file mode 100644
index 000000000..f9289654d
--- /dev/null
+++ b/tests/MC/AArch64/SVE/smin.s.yaml
@@ -0,0 +1,360 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xd0, 0x2a, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin z0.b, z0.b, #-128"
+
+  -
+    input:
+      bytes: [ 0xff, 0xcf, 0x2a, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin z31.b, z31.b, #127"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd0, 0x6a, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin z0.h, z0.h, #-128"
+
+  -
+    input:
+      bytes: [ 0xff, 0xcf, 0x6a, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin z31.h, z31.h, #127"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd0, 0xaa, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin z0.s, z0.s, #-128"
+
+  -
+    input:
+      bytes: [ 0xff, 0xcf, 0xaa, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin z31.s, z31.s, #127"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd0, 0xea, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin z0.d, z0.d, #-128"
+
+  -
+    input:
+      bytes: [ 0xff, 0xcf, 0xea, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin z31.d, z31.d, #127"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0x0a, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin z31.b, p7/m, z31.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0x4a, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin z31.h, p7/m, z31.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0x8a, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin z31.s, p7/m, z31.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0xca, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin z31.d, p7/m, z31.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4.d, p7/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xe4, 0x1f, 0xca, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin z4.d, p7/m, z4.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4, z6"
+
+  -
+    input:
+      bytes: [ 0xe4, 0x1f, 0xca, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin z4.d, p7/m, z4.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xff, 0xcf, 0xea, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin z31.d, z31.d, #127"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd0, 0x2a, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin z0.b, z0.b, #-128"
+
+  -
+    input:
+      bytes: [ 0xff, 0xcf, 0x2a, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin z31.b, z31.b, #127"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd0, 0x6a, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin z0.h, z0.h, #-128"
+
+  -
+    input:
+      bytes: [ 0xff, 0xcf, 0x6a, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin z31.h, z31.h, #127"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd0, 0xaa, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin z0.s, z0.s, #-128"
+
+  -
+    input:
+      bytes: [ 0xff, 0xcf, 0xaa, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin z31.s, z31.s, #127"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd0, 0xea, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin z0.d, z0.d, #-128"
+
+  -
+    input:
+      bytes: [ 0xff, 0xcf, 0xea, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin z31.d, z31.d, #127"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0x0a, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin z31.b, p7/m, z31.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0x4a, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin z31.h, p7/m, z31.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0x8a, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin z31.s, p7/m, z31.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0xca, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin z31.d, p7/m, z31.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4.d, p7/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xe4, 0x1f, 0xca, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin z4.d, p7/m, z4.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4, z6"
+
+  -
+    input:
+      bytes: [ 0xe4, 0x1f, 0xca, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin z4.d, p7/m, z4.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xff, 0xcf, 0xea, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin z31.d, z31.d, #127"
diff --git a/tests/MC/AArch64/SVE/sminv.s.yaml b/tests/MC/AArch64/SVE/sminv.s.yaml
new file mode 100644
index 000000000..8cec85377
--- /dev/null
+++ b/tests/MC/AArch64/SVE/sminv.s.yaml
@@ -0,0 +1,80 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xe0, 0x3f, 0x0a, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sminv b0, p7, z31.b"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3f, 0x4a, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sminv h0, p7, z31.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3f, 0x8a, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sminv s0, p7, z31.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3f, 0xca, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sminv d0, p7, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3f, 0x0a, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sminv b0, p7, z31.b"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3f, 0x4a, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sminv h0, p7, z31.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3f, 0x8a, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sminv s0, p7, z31.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3f, 0xca, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sminv d0, p7, z31.d"
diff --git a/tests/MC/AArch64/SVE/smulh.s.yaml b/tests/MC/AArch64/SVE/smulh.s.yaml
new file mode 100644
index 000000000..f21e0e5f1
--- /dev/null
+++ b/tests/MC/AArch64/SVE/smulh.s.yaml
@@ -0,0 +1,160 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xe0, 0x1f, 0x12, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "smulh z0.b, p7/m, z0.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x1f, 0x52, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "smulh z0.h, p7/m, z0.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x1f, 0x92, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "smulh z0.s, p7/m, z0.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x1f, 0xd2, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "smulh z0.d, p7/m, z0.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0.d, p7/z, z7.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x1f, 0xd2, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "smulh z0.d, p7/m, z0.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x1f, 0xd2, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "smulh z0.d, p7/m, z0.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x1f, 0x12, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smulh z0.b, p7/m, z0.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x1f, 0x52, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smulh z0.h, p7/m, z0.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x1f, 0x92, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smulh z0.s, p7/m, z0.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x1f, 0xd2, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smulh z0.d, p7/m, z0.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0.d, p7/z, z7.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x1f, 0xd2, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smulh z0.d, p7/m, z0.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x1f, 0xd2, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smulh z0.d, p7/m, z0.d, z31.d"
diff --git a/tests/MC/AArch64/SVE/splice.s.yaml b/tests/MC/AArch64/SVE/splice.s.yaml
new file mode 100644
index 000000000..8585d45e7
--- /dev/null
+++ b/tests/MC/AArch64/SVE/splice.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xff, 0x9f, 0x2c, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "splice z31.b, p7, z31.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x9f, 0x6c, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "splice z31.h, p7, z31.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x9f, 0xac, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "splice z31.s, p7, z31.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0x9f, 0xec, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "splice z31.d, p7, z31.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4, z6"
+
+  -
+    input:
+      bytes: [ 0xe4, 0x9f, 0xec, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "splice z4.d, p7, z4.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0x9f, 0x2c, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "splice z31.b, p7, z31.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x9f, 0x6c, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "splice z31.h, p7, z31.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x9f, 0xac, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "splice z31.s, p7, z31.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0x9f, 0xec, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "splice z31.d, p7, z31.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4, z6"
+
+  -
+    input:
+      bytes: [ 0xe4, 0x9f, 0xec, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "splice z4.d, p7, z4.d, z31.d"
diff --git a/tests/MC/AArch64/SVE/sqadd.s.yaml b/tests/MC/AArch64/SVE/sqadd.s.yaml
new file mode 100644
index 000000000..ddc7fbe08
--- /dev/null
+++ b/tests/MC/AArch64/SVE/sqadd.s.yaml
@@ -0,0 +1,400 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x10, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqadd z0.b, z0.b, z0.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x10, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqadd z0.h, z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x10, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqadd z0.s, z0.s, z0.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0x10, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqadd z0.d, z0.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x24, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqadd z0.b, z0.b, #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0xdf, 0x24, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqadd z31.b, z31.b, #255"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x64, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqadd z0.h, z0.h, #0"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x64, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqadd z0.h, z0.h, #0, lsl #8"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0x64, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqadd z31.h, z31.h, #65280"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0x64, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqadd z31.h, z31.h, #65280"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0xa4, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqadd z0.s, z0.s, #0"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xa4, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqadd z0.s, z0.s, #0, lsl #8"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xa4, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqadd z31.s, z31.s, #65280"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xa4, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqadd z31.s, z31.s, #65280"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0xe4, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqadd z0.d, z0.d, #0"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xe4, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqadd z0.d, z0.d, #0, lsl #8"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xe4, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqadd z31.d, z31.d, #65280"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xe4, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqadd z31.d, z31.d, #65280"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xe4, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqadd z31.d, z31.d, #65280"
+
+  -
+    input:
+      bytes: [ 0x00, 0x10, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqadd z0.b, z0.b, z0.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x10, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqadd z0.h, z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x10, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqadd z0.s, z0.s, z0.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0x10, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqadd z0.d, z0.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x24, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqadd z0.b, z0.b, #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0xdf, 0x24, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqadd z31.b, z31.b, #255"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x64, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqadd z0.h, z0.h, #0"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x64, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqadd z0.h, z0.h, #0, lsl #8"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0x64, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqadd z31.h, z31.h, #65280"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0x64, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqadd z31.h, z31.h, #65280"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0xa4, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqadd z0.s, z0.s, #0"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xa4, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqadd z0.s, z0.s, #0, lsl #8"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xa4, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqadd z31.s, z31.s, #65280"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xa4, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqadd z31.s, z31.s, #65280"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0xe4, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqadd z0.d, z0.d, #0"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xe4, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqadd z0.d, z0.d, #0, lsl #8"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xe4, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqadd z31.d, z31.d, #65280"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xe4, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqadd z31.d, z31.d, #65280"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xe4, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqadd z31.d, z31.d, #65280"
diff --git a/tests/MC/AArch64/SVE/sqdecb.s.yaml b/tests/MC/AArch64/SVE/sqdecb.s.yaml
new file mode 100644
index 000000000..b7471bed6
--- /dev/null
+++ b/tests/MC/AArch64/SVE/sqdecb.s.yaml
@@ -0,0 +1,780 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xe0, 0xfb, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecb x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xfb, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecb x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xfb, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecb x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xfb, 0x3f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecb x0, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xfb, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecb x0, w0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xfb, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecb x0, w0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xfb, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecb x0, w0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xfb, 0x2f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecb x0, w0, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf8, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecb x0, w0, pow2"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf8, 0x2f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecb x0, w0, pow2, mul #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf8, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecb x0, pow2"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf8, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecb x0, vl1"
+
+  -
+    input:
+      bytes: [ 0x40, 0xf8, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecb x0, vl2"
+
+  -
+    input:
+      bytes: [ 0x60, 0xf8, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecb x0, vl3"
+
+  -
+    input:
+      bytes: [ 0x80, 0xf8, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecb x0, vl4"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xf8, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecb x0, vl5"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xf8, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecb x0, vl6"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf8, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecb x0, vl7"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf9, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecb x0, vl8"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf9, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecb x0, vl16"
+
+  -
+    input:
+      bytes: [ 0x40, 0xf9, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecb x0, vl32"
+
+  -
+    input:
+      bytes: [ 0x60, 0xf9, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecb x0, vl64"
+
+  -
+    input:
+      bytes: [ 0x80, 0xf9, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecb x0, vl128"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xf9, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecb x0, vl256"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xf9, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecb x0, #14"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf9, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecb x0, #15"
+
+  -
+    input:
+      bytes: [ 0x00, 0xfa, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecb x0, #16"
+
+  -
+    input:
+      bytes: [ 0x20, 0xfa, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecb x0, #17"
+
+  -
+    input:
+      bytes: [ 0x40, 0xfa, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecb x0, #18"
+
+  -
+    input:
+      bytes: [ 0x60, 0xfa, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecb x0, #19"
+
+  -
+    input:
+      bytes: [ 0x80, 0xfa, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecb x0, #20"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xfa, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecb x0, #21"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xfa, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecb x0, #22"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xfa, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecb x0, #23"
+
+  -
+    input:
+      bytes: [ 0x00, 0xfb, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecb x0, #24"
+
+  -
+    input:
+      bytes: [ 0x20, 0xfb, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecb x0, #25"
+
+  -
+    input:
+      bytes: [ 0x40, 0xfb, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecb x0, #26"
+
+  -
+    input:
+      bytes: [ 0x60, 0xfb, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecb x0, #27"
+
+  -
+    input:
+      bytes: [ 0x80, 0xfb, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecb x0, #28"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xfb, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecb x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xfb, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecb x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xfb, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecb x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xfb, 0x3f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecb x0, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xfb, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecb x0, w0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xfb, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecb x0, w0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xfb, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecb x0, w0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xfb, 0x2f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecb x0, w0, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf8, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecb x0, w0, pow2"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf8, 0x2f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecb x0, w0, pow2, mul #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf8, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecb x0, pow2"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf8, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecb x0, vl1"
+
+  -
+    input:
+      bytes: [ 0x40, 0xf8, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecb x0, vl2"
+
+  -
+    input:
+      bytes: [ 0x60, 0xf8, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecb x0, vl3"
+
+  -
+    input:
+      bytes: [ 0x80, 0xf8, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecb x0, vl4"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xf8, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecb x0, vl5"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xf8, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecb x0, vl6"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf8, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecb x0, vl7"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf9, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecb x0, vl8"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf9, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecb x0, vl16"
+
+  -
+    input:
+      bytes: [ 0x40, 0xf9, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecb x0, vl32"
+
+  -
+    input:
+      bytes: [ 0x60, 0xf9, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecb x0, vl64"
+
+  -
+    input:
+      bytes: [ 0x80, 0xf9, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecb x0, vl128"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xf9, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecb x0, vl256"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xf9, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecb x0, #14"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf9, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecb x0, #15"
+
+  -
+    input:
+      bytes: [ 0x00, 0xfa, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecb x0, #16"
+
+  -
+    input:
+      bytes: [ 0x20, 0xfa, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecb x0, #17"
+
+  -
+    input:
+      bytes: [ 0x40, 0xfa, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecb x0, #18"
+
+  -
+    input:
+      bytes: [ 0x60, 0xfa, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecb x0, #19"
+
+  -
+    input:
+      bytes: [ 0x80, 0xfa, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecb x0, #20"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xfa, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecb x0, #21"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xfa, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecb x0, #22"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xfa, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecb x0, #23"
+
+  -
+    input:
+      bytes: [ 0x00, 0xfb, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecb x0, #24"
+
+  -
+    input:
+      bytes: [ 0x20, 0xfb, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecb x0, #25"
+
+  -
+    input:
+      bytes: [ 0x40, 0xfb, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecb x0, #26"
+
+  -
+    input:
+      bytes: [ 0x60, 0xfb, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecb x0, #27"
+
+  -
+    input:
+      bytes: [ 0x80, 0xfb, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecb x0, #28"
diff --git a/tests/MC/AArch64/SVE/sqdecd.s.yaml b/tests/MC/AArch64/SVE/sqdecd.s.yaml
new file mode 100644
index 000000000..54b2df996
--- /dev/null
+++ b/tests/MC/AArch64/SVE/sqdecd.s.yaml
@@ -0,0 +1,1020 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xe0, 0xfb, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecd x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xfb, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecd x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xfb, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecd x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xfb, 0xff, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecd x0, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xfb, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecd x0, w0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xfb, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecd x0, w0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xfb, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecd x0, w0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xfb, 0xef, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecd x0, w0, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf8, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecd x0, w0, pow2"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf8, 0xef, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecd x0, w0, pow2, mul #16"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xcb, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecd z0.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xcb, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecd z0.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xcb, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecd z0.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xcb, 0xef, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecd z0.d, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc8, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecd z0.d, pow2"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc8, 0xef, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecd z0.d, pow2, mul #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf8, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecd x0, pow2"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf8, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecd x0, vl1"
+
+  -
+    input:
+      bytes: [ 0x40, 0xf8, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecd x0, vl2"
+
+  -
+    input:
+      bytes: [ 0x60, 0xf8, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecd x0, vl3"
+
+  -
+    input:
+      bytes: [ 0x80, 0xf8, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecd x0, vl4"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xf8, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecd x0, vl5"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xf8, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecd x0, vl6"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf8, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecd x0, vl7"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf9, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecd x0, vl8"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf9, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecd x0, vl16"
+
+  -
+    input:
+      bytes: [ 0x40, 0xf9, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecd x0, vl32"
+
+  -
+    input:
+      bytes: [ 0x60, 0xf9, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecd x0, vl64"
+
+  -
+    input:
+      bytes: [ 0x80, 0xf9, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecd x0, vl128"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xf9, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecd x0, vl256"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xf9, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecd x0, #14"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf9, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecd x0, #15"
+
+  -
+    input:
+      bytes: [ 0x00, 0xfa, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecd x0, #16"
+
+  -
+    input:
+      bytes: [ 0x20, 0xfa, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecd x0, #17"
+
+  -
+    input:
+      bytes: [ 0x40, 0xfa, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecd x0, #18"
+
+  -
+    input:
+      bytes: [ 0x60, 0xfa, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecd x0, #19"
+
+  -
+    input:
+      bytes: [ 0x80, 0xfa, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecd x0, #20"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xfa, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecd x0, #21"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xfa, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecd x0, #22"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xfa, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecd x0, #23"
+
+  -
+    input:
+      bytes: [ 0x00, 0xfb, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecd x0, #24"
+
+  -
+    input:
+      bytes: [ 0x20, 0xfb, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecd x0, #25"
+
+  -
+    input:
+      bytes: [ 0x40, 0xfb, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecd x0, #26"
+
+  -
+    input:
+      bytes: [ 0x60, 0xfb, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecd x0, #27"
+
+  -
+    input:
+      bytes: [ 0x80, 0xfb, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecd x0, #28"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xcb, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecd z0.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc8, 0xef, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecd z0.d, pow2, mul #16"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc8, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecd z0.d, pow2"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xfb, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecd x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xfb, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecd x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xfb, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecd x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xfb, 0xff, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecd x0, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xfb, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecd x0, w0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xfb, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecd x0, w0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xfb, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecd x0, w0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xfb, 0xef, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecd x0, w0, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf8, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecd x0, w0, pow2"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf8, 0xef, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecd x0, w0, pow2, mul #16"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xcb, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecd z0.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xcb, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecd z0.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xcb, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecd z0.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xcb, 0xef, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecd z0.d, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc8, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecd z0.d, pow2"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc8, 0xef, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecd z0.d, pow2, mul #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf8, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecd x0, pow2"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf8, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecd x0, vl1"
+
+  -
+    input:
+      bytes: [ 0x40, 0xf8, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecd x0, vl2"
+
+  -
+    input:
+      bytes: [ 0x60, 0xf8, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecd x0, vl3"
+
+  -
+    input:
+      bytes: [ 0x80, 0xf8, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecd x0, vl4"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xf8, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecd x0, vl5"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xf8, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecd x0, vl6"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf8, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecd x0, vl7"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf9, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecd x0, vl8"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf9, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecd x0, vl16"
+
+  -
+    input:
+      bytes: [ 0x40, 0xf9, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecd x0, vl32"
+
+  -
+    input:
+      bytes: [ 0x60, 0xf9, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecd x0, vl64"
+
+  -
+    input:
+      bytes: [ 0x80, 0xf9, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecd x0, vl128"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xf9, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecd x0, vl256"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xf9, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecd x0, #14"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf9, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecd x0, #15"
+
+  -
+    input:
+      bytes: [ 0x00, 0xfa, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecd x0, #16"
+
+  -
+    input:
+      bytes: [ 0x20, 0xfa, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecd x0, #17"
+
+  -
+    input:
+      bytes: [ 0x40, 0xfa, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecd x0, #18"
+
+  -
+    input:
+      bytes: [ 0x60, 0xfa, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecd x0, #19"
+
+  -
+    input:
+      bytes: [ 0x80, 0xfa, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecd x0, #20"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xfa, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecd x0, #21"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xfa, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecd x0, #22"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xfa, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecd x0, #23"
+
+  -
+    input:
+      bytes: [ 0x00, 0xfb, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecd x0, #24"
+
+  -
+    input:
+      bytes: [ 0x20, 0xfb, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecd x0, #25"
+
+  -
+    input:
+      bytes: [ 0x40, 0xfb, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecd x0, #26"
+
+  -
+    input:
+      bytes: [ 0x60, 0xfb, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecd x0, #27"
+
+  -
+    input:
+      bytes: [ 0x80, 0xfb, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecd x0, #28"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xcb, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecd z0.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc8, 0xef, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecd z0.d, pow2, mul #16"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc8, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecd z0.d, pow2"
diff --git a/tests/MC/AArch64/SVE/sqdech.s.yaml b/tests/MC/AArch64/SVE/sqdech.s.yaml
new file mode 100644
index 000000000..ec3a80efc
--- /dev/null
+++ b/tests/MC/AArch64/SVE/sqdech.s.yaml
@@ -0,0 +1,1020 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xe0, 0xfb, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdech x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xfb, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdech x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xfb, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdech x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xfb, 0x7f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdech x0, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xfb, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdech x0, w0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xfb, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdech x0, w0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xfb, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdech x0, w0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xfb, 0x6f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdech x0, w0, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf8, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdech x0, w0, pow2"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf8, 0x6f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdech x0, w0, pow2, mul #16"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xcb, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdech z0.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xcb, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdech z0.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xcb, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdech z0.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xcb, 0x6f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdech z0.h, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc8, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdech z0.h, pow2"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc8, 0x6f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdech z0.h, pow2, mul #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf8, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdech x0, pow2"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf8, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdech x0, vl1"
+
+  -
+    input:
+      bytes: [ 0x40, 0xf8, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdech x0, vl2"
+
+  -
+    input:
+      bytes: [ 0x60, 0xf8, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdech x0, vl3"
+
+  -
+    input:
+      bytes: [ 0x80, 0xf8, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdech x0, vl4"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xf8, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdech x0, vl5"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xf8, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdech x0, vl6"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf8, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdech x0, vl7"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf9, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdech x0, vl8"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf9, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdech x0, vl16"
+
+  -
+    input:
+      bytes: [ 0x40, 0xf9, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdech x0, vl32"
+
+  -
+    input:
+      bytes: [ 0x60, 0xf9, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdech x0, vl64"
+
+  -
+    input:
+      bytes: [ 0x80, 0xf9, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdech x0, vl128"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xf9, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdech x0, vl256"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xf9, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdech x0, #14"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf9, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdech x0, #15"
+
+  -
+    input:
+      bytes: [ 0x00, 0xfa, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdech x0, #16"
+
+  -
+    input:
+      bytes: [ 0x20, 0xfa, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdech x0, #17"
+
+  -
+    input:
+      bytes: [ 0x40, 0xfa, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdech x0, #18"
+
+  -
+    input:
+      bytes: [ 0x60, 0xfa, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdech x0, #19"
+
+  -
+    input:
+      bytes: [ 0x80, 0xfa, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdech x0, #20"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xfa, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdech x0, #21"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xfa, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdech x0, #22"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xfa, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdech x0, #23"
+
+  -
+    input:
+      bytes: [ 0x00, 0xfb, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdech x0, #24"
+
+  -
+    input:
+      bytes: [ 0x20, 0xfb, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdech x0, #25"
+
+  -
+    input:
+      bytes: [ 0x40, 0xfb, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdech x0, #26"
+
+  -
+    input:
+      bytes: [ 0x60, 0xfb, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdech x0, #27"
+
+  -
+    input:
+      bytes: [ 0x80, 0xfb, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdech x0, #28"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xcb, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdech z0.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc8, 0x6f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdech z0.h, pow2, mul #16"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc8, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdech z0.h, pow2"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xfb, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdech x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xfb, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdech x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xfb, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdech x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xfb, 0x7f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdech x0, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xfb, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdech x0, w0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xfb, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdech x0, w0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xfb, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdech x0, w0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xfb, 0x6f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdech x0, w0, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf8, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdech x0, w0, pow2"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf8, 0x6f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdech x0, w0, pow2, mul #16"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xcb, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdech z0.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xcb, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdech z0.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xcb, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdech z0.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xcb, 0x6f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdech z0.h, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc8, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdech z0.h, pow2"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc8, 0x6f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdech z0.h, pow2, mul #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf8, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdech x0, pow2"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf8, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdech x0, vl1"
+
+  -
+    input:
+      bytes: [ 0x40, 0xf8, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdech x0, vl2"
+
+  -
+    input:
+      bytes: [ 0x60, 0xf8, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdech x0, vl3"
+
+  -
+    input:
+      bytes: [ 0x80, 0xf8, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdech x0, vl4"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xf8, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdech x0, vl5"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xf8, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdech x0, vl6"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf8, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdech x0, vl7"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf9, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdech x0, vl8"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf9, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdech x0, vl16"
+
+  -
+    input:
+      bytes: [ 0x40, 0xf9, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdech x0, vl32"
+
+  -
+    input:
+      bytes: [ 0x60, 0xf9, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdech x0, vl64"
+
+  -
+    input:
+      bytes: [ 0x80, 0xf9, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdech x0, vl128"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xf9, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdech x0, vl256"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xf9, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdech x0, #14"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf9, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdech x0, #15"
+
+  -
+    input:
+      bytes: [ 0x00, 0xfa, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdech x0, #16"
+
+  -
+    input:
+      bytes: [ 0x20, 0xfa, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdech x0, #17"
+
+  -
+    input:
+      bytes: [ 0x40, 0xfa, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdech x0, #18"
+
+  -
+    input:
+      bytes: [ 0x60, 0xfa, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdech x0, #19"
+
+  -
+    input:
+      bytes: [ 0x80, 0xfa, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdech x0, #20"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xfa, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdech x0, #21"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xfa, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdech x0, #22"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xfa, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdech x0, #23"
+
+  -
+    input:
+      bytes: [ 0x00, 0xfb, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdech x0, #24"
+
+  -
+    input:
+      bytes: [ 0x20, 0xfb, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdech x0, #25"
+
+  -
+    input:
+      bytes: [ 0x40, 0xfb, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdech x0, #26"
+
+  -
+    input:
+      bytes: [ 0x60, 0xfb, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdech x0, #27"
+
+  -
+    input:
+      bytes: [ 0x80, 0xfb, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdech x0, #28"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xcb, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdech z0.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc8, 0x6f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdech z0.h, pow2, mul #16"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc8, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdech z0.h, pow2"
diff --git a/tests/MC/AArch64/SVE/sqdecp.s.yaml b/tests/MC/AArch64/SVE/sqdecp.s.yaml
new file mode 100644
index 000000000..4305c565c
--- /dev/null
+++ b/tests/MC/AArch64/SVE/sqdecp.s.yaml
@@ -0,0 +1,320 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x8c, 0x2a, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecp x0, p0.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x8c, 0x6a, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecp x0, p0.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x8c, 0xaa, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecp x0, p0.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0x8c, 0xea, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecp x0, p0.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0x89, 0x2a, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecp xzr, p15.b, wzr"
+
+  -
+    input:
+      bytes: [ 0xff, 0x89, 0x6a, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecp xzr, p15.h, wzr"
+
+  -
+    input:
+      bytes: [ 0xff, 0x89, 0xaa, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecp xzr, p15.s, wzr"
+
+  -
+    input:
+      bytes: [ 0xff, 0x89, 0xea, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecp xzr, p15.d, wzr"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x6a, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecp z0.h, p0.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x6a, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecp z0.h, p0.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xaa, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecp z0.s, p0.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xaa, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecp z0.s, p0.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xea, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecp z0.d, p0.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xea, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecp z0.d, p0.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xea, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecp z0.d, p0.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x8c, 0x2a, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecp x0, p0.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x8c, 0x6a, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecp x0, p0.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x8c, 0xaa, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecp x0, p0.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0x8c, 0xea, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecp x0, p0.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0x89, 0x2a, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecp xzr, p15.b, wzr"
+
+  -
+    input:
+      bytes: [ 0xff, 0x89, 0x6a, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecp xzr, p15.h, wzr"
+
+  -
+    input:
+      bytes: [ 0xff, 0x89, 0xaa, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecp xzr, p15.s, wzr"
+
+  -
+    input:
+      bytes: [ 0xff, 0x89, 0xea, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecp xzr, p15.d, wzr"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x6a, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecp z0.h, p0.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x6a, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecp z0.h, p0.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xaa, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecp z0.s, p0.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xaa, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecp z0.s, p0.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xea, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecp z0.d, p0.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xea, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecp z0.d, p0.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xea, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecp z0.d, p0.d"
diff --git a/tests/MC/AArch64/SVE/sqdecw.s.yaml b/tests/MC/AArch64/SVE/sqdecw.s.yaml
new file mode 100644
index 000000000..fa2f9c82c
--- /dev/null
+++ b/tests/MC/AArch64/SVE/sqdecw.s.yaml
@@ -0,0 +1,1020 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xe0, 0xfb, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecw x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xfb, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecw x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xfb, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecw x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xfb, 0xbf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecw x0, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xfb, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecw x0, w0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xfb, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecw x0, w0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xfb, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecw x0, w0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xfb, 0xaf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecw x0, w0, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf8, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecw x0, w0, pow2"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf8, 0xaf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecw x0, w0, pow2, mul #16"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xcb, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecw z0.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xcb, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecw z0.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xcb, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecw z0.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xcb, 0xaf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecw z0.s, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc8, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecw z0.s, pow2"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc8, 0xaf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecw z0.s, pow2, mul #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf8, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecw x0, pow2"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf8, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecw x0, vl1"
+
+  -
+    input:
+      bytes: [ 0x40, 0xf8, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecw x0, vl2"
+
+  -
+    input:
+      bytes: [ 0x60, 0xf8, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecw x0, vl3"
+
+  -
+    input:
+      bytes: [ 0x80, 0xf8, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecw x0, vl4"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xf8, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecw x0, vl5"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xf8, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecw x0, vl6"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf8, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecw x0, vl7"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf9, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecw x0, vl8"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf9, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecw x0, vl16"
+
+  -
+    input:
+      bytes: [ 0x40, 0xf9, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecw x0, vl32"
+
+  -
+    input:
+      bytes: [ 0x60, 0xf9, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecw x0, vl64"
+
+  -
+    input:
+      bytes: [ 0x80, 0xf9, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecw x0, vl128"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xf9, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecw x0, vl256"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xf9, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecw x0, #14"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf9, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecw x0, #15"
+
+  -
+    input:
+      bytes: [ 0x00, 0xfa, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecw x0, #16"
+
+  -
+    input:
+      bytes: [ 0x20, 0xfa, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecw x0, #17"
+
+  -
+    input:
+      bytes: [ 0x40, 0xfa, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecw x0, #18"
+
+  -
+    input:
+      bytes: [ 0x60, 0xfa, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecw x0, #19"
+
+  -
+    input:
+      bytes: [ 0x80, 0xfa, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecw x0, #20"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xfa, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecw x0, #21"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xfa, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecw x0, #22"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xfa, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecw x0, #23"
+
+  -
+    input:
+      bytes: [ 0x00, 0xfb, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecw x0, #24"
+
+  -
+    input:
+      bytes: [ 0x20, 0xfb, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecw x0, #25"
+
+  -
+    input:
+      bytes: [ 0x40, 0xfb, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecw x0, #26"
+
+  -
+    input:
+      bytes: [ 0x60, 0xfb, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecw x0, #27"
+
+  -
+    input:
+      bytes: [ 0x80, 0xfb, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecw x0, #28"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xcb, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecw z0.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc8, 0xaf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecw z0.s, pow2, mul #16"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc8, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecw z0.s, pow2"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xfb, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecw x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xfb, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecw x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xfb, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecw x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xfb, 0xbf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecw x0, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xfb, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecw x0, w0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xfb, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecw x0, w0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xfb, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecw x0, w0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xfb, 0xaf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecw x0, w0, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf8, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecw x0, w0, pow2"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf8, 0xaf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecw x0, w0, pow2, mul #16"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xcb, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecw z0.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xcb, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecw z0.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xcb, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecw z0.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xcb, 0xaf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecw z0.s, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc8, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecw z0.s, pow2"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc8, 0xaf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecw z0.s, pow2, mul #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf8, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecw x0, pow2"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf8, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecw x0, vl1"
+
+  -
+    input:
+      bytes: [ 0x40, 0xf8, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecw x0, vl2"
+
+  -
+    input:
+      bytes: [ 0x60, 0xf8, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecw x0, vl3"
+
+  -
+    input:
+      bytes: [ 0x80, 0xf8, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecw x0, vl4"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xf8, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecw x0, vl5"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xf8, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecw x0, vl6"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf8, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecw x0, vl7"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf9, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecw x0, vl8"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf9, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecw x0, vl16"
+
+  -
+    input:
+      bytes: [ 0x40, 0xf9, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecw x0, vl32"
+
+  -
+    input:
+      bytes: [ 0x60, 0xf9, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecw x0, vl64"
+
+  -
+    input:
+      bytes: [ 0x80, 0xf9, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecw x0, vl128"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xf9, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecw x0, vl256"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xf9, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecw x0, #14"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf9, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecw x0, #15"
+
+  -
+    input:
+      bytes: [ 0x00, 0xfa, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecw x0, #16"
+
+  -
+    input:
+      bytes: [ 0x20, 0xfa, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecw x0, #17"
+
+  -
+    input:
+      bytes: [ 0x40, 0xfa, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecw x0, #18"
+
+  -
+    input:
+      bytes: [ 0x60, 0xfa, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecw x0, #19"
+
+  -
+    input:
+      bytes: [ 0x80, 0xfa, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecw x0, #20"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xfa, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecw x0, #21"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xfa, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecw x0, #22"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xfa, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecw x0, #23"
+
+  -
+    input:
+      bytes: [ 0x00, 0xfb, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecw x0, #24"
+
+  -
+    input:
+      bytes: [ 0x20, 0xfb, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecw x0, #25"
+
+  -
+    input:
+      bytes: [ 0x40, 0xfb, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecw x0, #26"
+
+  -
+    input:
+      bytes: [ 0x60, 0xfb, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecw x0, #27"
+
+  -
+    input:
+      bytes: [ 0x80, 0xfb, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecw x0, #28"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xcb, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecw z0.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc8, 0xaf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecw z0.s, pow2, mul #16"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc8, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdecw z0.s, pow2"
diff --git a/tests/MC/AArch64/SVE/sqincb.s.yaml b/tests/MC/AArch64/SVE/sqincb.s.yaml
new file mode 100644
index 000000000..1d51c9139
--- /dev/null
+++ b/tests/MC/AArch64/SVE/sqincb.s.yaml
@@ -0,0 +1,780 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xe0, 0xf3, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincb x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf3, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincb x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf3, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincb x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf3, 0x3f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincb x0, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf3, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincb x0, w0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf3, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincb x0, w0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf3, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincb x0, w0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf3, 0x2f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincb x0, w0, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf0, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincb x0, w0, pow2"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf0, 0x2f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincb x0, w0, pow2, mul #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf0, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincb x0, pow2"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf0, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincb x0, vl1"
+
+  -
+    input:
+      bytes: [ 0x40, 0xf0, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincb x0, vl2"
+
+  -
+    input:
+      bytes: [ 0x60, 0xf0, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincb x0, vl3"
+
+  -
+    input:
+      bytes: [ 0x80, 0xf0, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincb x0, vl4"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xf0, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincb x0, vl5"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xf0, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincb x0, vl6"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf0, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincb x0, vl7"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf1, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincb x0, vl8"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf1, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincb x0, vl16"
+
+  -
+    input:
+      bytes: [ 0x40, 0xf1, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincb x0, vl32"
+
+  -
+    input:
+      bytes: [ 0x60, 0xf1, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincb x0, vl64"
+
+  -
+    input:
+      bytes: [ 0x80, 0xf1, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincb x0, vl128"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xf1, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincb x0, vl256"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xf1, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincb x0, #14"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf1, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincb x0, #15"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf2, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincb x0, #16"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf2, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincb x0, #17"
+
+  -
+    input:
+      bytes: [ 0x40, 0xf2, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincb x0, #18"
+
+  -
+    input:
+      bytes: [ 0x60, 0xf2, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincb x0, #19"
+
+  -
+    input:
+      bytes: [ 0x80, 0xf2, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincb x0, #20"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xf2, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincb x0, #21"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xf2, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincb x0, #22"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf2, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincb x0, #23"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf3, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincb x0, #24"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf3, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincb x0, #25"
+
+  -
+    input:
+      bytes: [ 0x40, 0xf3, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincb x0, #26"
+
+  -
+    input:
+      bytes: [ 0x60, 0xf3, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincb x0, #27"
+
+  -
+    input:
+      bytes: [ 0x80, 0xf3, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincb x0, #28"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf3, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincb x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf3, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincb x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf3, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincb x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf3, 0x3f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincb x0, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf3, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincb x0, w0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf3, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincb x0, w0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf3, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincb x0, w0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf3, 0x2f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincb x0, w0, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf0, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincb x0, w0, pow2"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf0, 0x2f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincb x0, w0, pow2, mul #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf0, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincb x0, pow2"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf0, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincb x0, vl1"
+
+  -
+    input:
+      bytes: [ 0x40, 0xf0, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincb x0, vl2"
+
+  -
+    input:
+      bytes: [ 0x60, 0xf0, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincb x0, vl3"
+
+  -
+    input:
+      bytes: [ 0x80, 0xf0, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincb x0, vl4"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xf0, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincb x0, vl5"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xf0, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincb x0, vl6"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf0, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincb x0, vl7"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf1, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincb x0, vl8"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf1, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincb x0, vl16"
+
+  -
+    input:
+      bytes: [ 0x40, 0xf1, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincb x0, vl32"
+
+  -
+    input:
+      bytes: [ 0x60, 0xf1, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincb x0, vl64"
+
+  -
+    input:
+      bytes: [ 0x80, 0xf1, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincb x0, vl128"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xf1, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincb x0, vl256"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xf1, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincb x0, #14"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf1, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincb x0, #15"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf2, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincb x0, #16"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf2, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincb x0, #17"
+
+  -
+    input:
+      bytes: [ 0x40, 0xf2, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincb x0, #18"
+
+  -
+    input:
+      bytes: [ 0x60, 0xf2, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincb x0, #19"
+
+  -
+    input:
+      bytes: [ 0x80, 0xf2, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincb x0, #20"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xf2, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincb x0, #21"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xf2, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincb x0, #22"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf2, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincb x0, #23"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf3, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincb x0, #24"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf3, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincb x0, #25"
+
+  -
+    input:
+      bytes: [ 0x40, 0xf3, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincb x0, #26"
+
+  -
+    input:
+      bytes: [ 0x60, 0xf3, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincb x0, #27"
+
+  -
+    input:
+      bytes: [ 0x80, 0xf3, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincb x0, #28"
diff --git a/tests/MC/AArch64/SVE/sqincd.s.yaml b/tests/MC/AArch64/SVE/sqincd.s.yaml
new file mode 100644
index 000000000..199de7327
--- /dev/null
+++ b/tests/MC/AArch64/SVE/sqincd.s.yaml
@@ -0,0 +1,1020 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xe0, 0xf3, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincd x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf3, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincd x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf3, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincd x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf3, 0xff, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincd x0, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf3, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincd x0, w0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf3, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincd x0, w0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf3, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincd x0, w0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf3, 0xef, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincd x0, w0, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf0, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincd x0, w0, pow2"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf0, 0xef, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincd x0, w0, pow2, mul #16"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc3, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincd z0.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc3, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincd z0.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc3, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincd z0.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc3, 0xef, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincd z0.d, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincd z0.d, pow2"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0xef, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincd z0.d, pow2, mul #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf0, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincd x0, pow2"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf0, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincd x0, vl1"
+
+  -
+    input:
+      bytes: [ 0x40, 0xf0, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincd x0, vl2"
+
+  -
+    input:
+      bytes: [ 0x60, 0xf0, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincd x0, vl3"
+
+  -
+    input:
+      bytes: [ 0x80, 0xf0, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincd x0, vl4"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xf0, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincd x0, vl5"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xf0, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincd x0, vl6"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf0, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincd x0, vl7"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf1, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincd x0, vl8"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf1, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincd x0, vl16"
+
+  -
+    input:
+      bytes: [ 0x40, 0xf1, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincd x0, vl32"
+
+  -
+    input:
+      bytes: [ 0x60, 0xf1, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincd x0, vl64"
+
+  -
+    input:
+      bytes: [ 0x80, 0xf1, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincd x0, vl128"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xf1, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincd x0, vl256"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xf1, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincd x0, #14"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf1, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincd x0, #15"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf2, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincd x0, #16"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf2, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincd x0, #17"
+
+  -
+    input:
+      bytes: [ 0x40, 0xf2, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincd x0, #18"
+
+  -
+    input:
+      bytes: [ 0x60, 0xf2, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincd x0, #19"
+
+  -
+    input:
+      bytes: [ 0x80, 0xf2, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincd x0, #20"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xf2, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincd x0, #21"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xf2, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincd x0, #22"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf2, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincd x0, #23"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf3, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincd x0, #24"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf3, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincd x0, #25"
+
+  -
+    input:
+      bytes: [ 0x40, 0xf3, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincd x0, #26"
+
+  -
+    input:
+      bytes: [ 0x60, 0xf3, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincd x0, #27"
+
+  -
+    input:
+      bytes: [ 0x80, 0xf3, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincd x0, #28"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc3, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincd z0.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0xef, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincd z0.d, pow2, mul #16"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincd z0.d, pow2"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf3, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincd x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf3, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincd x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf3, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincd x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf3, 0xff, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincd x0, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf3, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincd x0, w0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf3, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincd x0, w0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf3, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincd x0, w0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf3, 0xef, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincd x0, w0, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf0, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincd x0, w0, pow2"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf0, 0xef, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincd x0, w0, pow2, mul #16"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc3, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincd z0.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc3, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincd z0.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc3, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincd z0.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc3, 0xef, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincd z0.d, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincd z0.d, pow2"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0xef, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincd z0.d, pow2, mul #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf0, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincd x0, pow2"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf0, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincd x0, vl1"
+
+  -
+    input:
+      bytes: [ 0x40, 0xf0, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincd x0, vl2"
+
+  -
+    input:
+      bytes: [ 0x60, 0xf0, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincd x0, vl3"
+
+  -
+    input:
+      bytes: [ 0x80, 0xf0, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincd x0, vl4"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xf0, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincd x0, vl5"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xf0, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincd x0, vl6"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf0, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincd x0, vl7"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf1, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincd x0, vl8"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf1, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincd x0, vl16"
+
+  -
+    input:
+      bytes: [ 0x40, 0xf1, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincd x0, vl32"
+
+  -
+    input:
+      bytes: [ 0x60, 0xf1, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincd x0, vl64"
+
+  -
+    input:
+      bytes: [ 0x80, 0xf1, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincd x0, vl128"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xf1, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincd x0, vl256"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xf1, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincd x0, #14"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf1, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincd x0, #15"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf2, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincd x0, #16"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf2, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincd x0, #17"
+
+  -
+    input:
+      bytes: [ 0x40, 0xf2, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincd x0, #18"
+
+  -
+    input:
+      bytes: [ 0x60, 0xf2, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincd x0, #19"
+
+  -
+    input:
+      bytes: [ 0x80, 0xf2, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincd x0, #20"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xf2, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincd x0, #21"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xf2, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincd x0, #22"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf2, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincd x0, #23"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf3, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincd x0, #24"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf3, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincd x0, #25"
+
+  -
+    input:
+      bytes: [ 0x40, 0xf3, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincd x0, #26"
+
+  -
+    input:
+      bytes: [ 0x60, 0xf3, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincd x0, #27"
+
+  -
+    input:
+      bytes: [ 0x80, 0xf3, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincd x0, #28"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc3, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincd z0.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0xef, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincd z0.d, pow2, mul #16"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincd z0.d, pow2"
diff --git a/tests/MC/AArch64/SVE/sqinch.s.yaml b/tests/MC/AArch64/SVE/sqinch.s.yaml
new file mode 100644
index 000000000..ce85abb7f
--- /dev/null
+++ b/tests/MC/AArch64/SVE/sqinch.s.yaml
@@ -0,0 +1,1020 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xe0, 0xf3, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqinch x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf3, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqinch x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf3, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqinch x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf3, 0x7f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqinch x0, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf3, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqinch x0, w0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf3, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqinch x0, w0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf3, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqinch x0, w0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf3, 0x6f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqinch x0, w0, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf0, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqinch x0, w0, pow2"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf0, 0x6f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqinch x0, w0, pow2, mul #16"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc3, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqinch z0.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc3, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqinch z0.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc3, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqinch z0.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc3, 0x6f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqinch z0.h, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqinch z0.h, pow2"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x6f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqinch z0.h, pow2, mul #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf0, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqinch x0, pow2"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf0, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqinch x0, vl1"
+
+  -
+    input:
+      bytes: [ 0x40, 0xf0, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqinch x0, vl2"
+
+  -
+    input:
+      bytes: [ 0x60, 0xf0, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqinch x0, vl3"
+
+  -
+    input:
+      bytes: [ 0x80, 0xf0, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqinch x0, vl4"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xf0, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqinch x0, vl5"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xf0, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqinch x0, vl6"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf0, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqinch x0, vl7"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf1, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqinch x0, vl8"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf1, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqinch x0, vl16"
+
+  -
+    input:
+      bytes: [ 0x40, 0xf1, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqinch x0, vl32"
+
+  -
+    input:
+      bytes: [ 0x60, 0xf1, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqinch x0, vl64"
+
+  -
+    input:
+      bytes: [ 0x80, 0xf1, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqinch x0, vl128"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xf1, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqinch x0, vl256"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xf1, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqinch x0, #14"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf1, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqinch x0, #15"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf2, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqinch x0, #16"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf2, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqinch x0, #17"
+
+  -
+    input:
+      bytes: [ 0x40, 0xf2, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqinch x0, #18"
+
+  -
+    input:
+      bytes: [ 0x60, 0xf2, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqinch x0, #19"
+
+  -
+    input:
+      bytes: [ 0x80, 0xf2, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqinch x0, #20"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xf2, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqinch x0, #21"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xf2, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqinch x0, #22"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf2, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqinch x0, #23"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf3, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqinch x0, #24"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf3, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqinch x0, #25"
+
+  -
+    input:
+      bytes: [ 0x40, 0xf3, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqinch x0, #26"
+
+  -
+    input:
+      bytes: [ 0x60, 0xf3, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqinch x0, #27"
+
+  -
+    input:
+      bytes: [ 0x80, 0xf3, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqinch x0, #28"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc3, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqinch z0.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x6f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqinch z0.h, pow2, mul #16"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqinch z0.h, pow2"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf3, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqinch x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf3, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqinch x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf3, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqinch x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf3, 0x7f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqinch x0, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf3, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqinch x0, w0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf3, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqinch x0, w0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf3, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqinch x0, w0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf3, 0x6f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqinch x0, w0, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf0, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqinch x0, w0, pow2"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf0, 0x6f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqinch x0, w0, pow2, mul #16"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc3, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqinch z0.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc3, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqinch z0.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc3, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqinch z0.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc3, 0x6f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqinch z0.h, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqinch z0.h, pow2"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x6f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqinch z0.h, pow2, mul #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf0, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqinch x0, pow2"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf0, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqinch x0, vl1"
+
+  -
+    input:
+      bytes: [ 0x40, 0xf0, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqinch x0, vl2"
+
+  -
+    input:
+      bytes: [ 0x60, 0xf0, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqinch x0, vl3"
+
+  -
+    input:
+      bytes: [ 0x80, 0xf0, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqinch x0, vl4"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xf0, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqinch x0, vl5"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xf0, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqinch x0, vl6"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf0, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqinch x0, vl7"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf1, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqinch x0, vl8"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf1, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqinch x0, vl16"
+
+  -
+    input:
+      bytes: [ 0x40, 0xf1, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqinch x0, vl32"
+
+  -
+    input:
+      bytes: [ 0x60, 0xf1, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqinch x0, vl64"
+
+  -
+    input:
+      bytes: [ 0x80, 0xf1, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqinch x0, vl128"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xf1, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqinch x0, vl256"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xf1, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqinch x0, #14"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf1, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqinch x0, #15"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf2, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqinch x0, #16"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf2, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqinch x0, #17"
+
+  -
+    input:
+      bytes: [ 0x40, 0xf2, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqinch x0, #18"
+
+  -
+    input:
+      bytes: [ 0x60, 0xf2, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqinch x0, #19"
+
+  -
+    input:
+      bytes: [ 0x80, 0xf2, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqinch x0, #20"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xf2, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqinch x0, #21"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xf2, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqinch x0, #22"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf2, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqinch x0, #23"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf3, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqinch x0, #24"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf3, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqinch x0, #25"
+
+  -
+    input:
+      bytes: [ 0x40, 0xf3, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqinch x0, #26"
+
+  -
+    input:
+      bytes: [ 0x60, 0xf3, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqinch x0, #27"
+
+  -
+    input:
+      bytes: [ 0x80, 0xf3, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqinch x0, #28"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc3, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqinch z0.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x6f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqinch z0.h, pow2, mul #16"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqinch z0.h, pow2"
diff --git a/tests/MC/AArch64/SVE/sqincp.s.yaml b/tests/MC/AArch64/SVE/sqincp.s.yaml
new file mode 100644
index 000000000..d6b011f86
--- /dev/null
+++ b/tests/MC/AArch64/SVE/sqincp.s.yaml
@@ -0,0 +1,320 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x8c, 0x28, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincp x0, p0.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x8c, 0x68, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincp x0, p0.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x8c, 0xa8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincp x0, p0.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0x8c, 0xe8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincp x0, p0.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0x89, 0x28, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincp xzr, p15.b, wzr"
+
+  -
+    input:
+      bytes: [ 0xff, 0x89, 0x68, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincp xzr, p15.h, wzr"
+
+  -
+    input:
+      bytes: [ 0xff, 0x89, 0xa8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincp xzr, p15.s, wzr"
+
+  -
+    input:
+      bytes: [ 0xff, 0x89, 0xe8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincp xzr, p15.d, wzr"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x68, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincp z0.h, p0.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x68, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincp z0.h, p0.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xa8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincp z0.s, p0.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xa8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincp z0.s, p0.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xe8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincp z0.d, p0.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xe8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincp z0.d, p0.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xe8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincp z0.d, p0.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x8c, 0x28, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincp x0, p0.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x8c, 0x68, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincp x0, p0.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x8c, 0xa8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincp x0, p0.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0x8c, 0xe8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincp x0, p0.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0x89, 0x28, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincp xzr, p15.b, wzr"
+
+  -
+    input:
+      bytes: [ 0xff, 0x89, 0x68, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincp xzr, p15.h, wzr"
+
+  -
+    input:
+      bytes: [ 0xff, 0x89, 0xa8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincp xzr, p15.s, wzr"
+
+  -
+    input:
+      bytes: [ 0xff, 0x89, 0xe8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincp xzr, p15.d, wzr"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x68, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincp z0.h, p0.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x68, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincp z0.h, p0.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xa8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincp z0.s, p0.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xa8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincp z0.s, p0.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xe8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincp z0.d, p0.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xe8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincp z0.d, p0.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xe8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincp z0.d, p0.d"
diff --git a/tests/MC/AArch64/SVE/sqincw.s.yaml b/tests/MC/AArch64/SVE/sqincw.s.yaml
new file mode 100644
index 000000000..3ed69eb05
--- /dev/null
+++ b/tests/MC/AArch64/SVE/sqincw.s.yaml
@@ -0,0 +1,1020 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xe0, 0xf3, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincw x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf3, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincw x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf3, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincw x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf3, 0xbf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincw x0, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf3, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincw x0, w0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf3, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincw x0, w0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf3, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincw x0, w0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf3, 0xaf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincw x0, w0, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf0, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincw x0, w0, pow2"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf0, 0xaf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincw x0, w0, pow2, mul #16"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc3, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincw z0.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc3, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincw z0.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc3, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincw z0.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc3, 0xaf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincw z0.s, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincw z0.s, pow2"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0xaf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincw z0.s, pow2, mul #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf0, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincw x0, pow2"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf0, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincw x0, vl1"
+
+  -
+    input:
+      bytes: [ 0x40, 0xf0, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincw x0, vl2"
+
+  -
+    input:
+      bytes: [ 0x60, 0xf0, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincw x0, vl3"
+
+  -
+    input:
+      bytes: [ 0x80, 0xf0, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincw x0, vl4"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xf0, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincw x0, vl5"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xf0, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincw x0, vl6"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf0, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincw x0, vl7"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf1, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincw x0, vl8"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf1, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincw x0, vl16"
+
+  -
+    input:
+      bytes: [ 0x40, 0xf1, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincw x0, vl32"
+
+  -
+    input:
+      bytes: [ 0x60, 0xf1, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincw x0, vl64"
+
+  -
+    input:
+      bytes: [ 0x80, 0xf1, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincw x0, vl128"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xf1, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincw x0, vl256"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xf1, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincw x0, #14"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf1, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincw x0, #15"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf2, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincw x0, #16"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf2, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincw x0, #17"
+
+  -
+    input:
+      bytes: [ 0x40, 0xf2, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincw x0, #18"
+
+  -
+    input:
+      bytes: [ 0x60, 0xf2, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincw x0, #19"
+
+  -
+    input:
+      bytes: [ 0x80, 0xf2, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincw x0, #20"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xf2, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincw x0, #21"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xf2, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincw x0, #22"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf2, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincw x0, #23"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf3, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincw x0, #24"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf3, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincw x0, #25"
+
+  -
+    input:
+      bytes: [ 0x40, 0xf3, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincw x0, #26"
+
+  -
+    input:
+      bytes: [ 0x60, 0xf3, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincw x0, #27"
+
+  -
+    input:
+      bytes: [ 0x80, 0xf3, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincw x0, #28"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc3, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincw z0.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0xaf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincw z0.s, pow2, mul #16"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincw z0.s, pow2"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf3, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincw x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf3, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincw x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf3, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincw x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf3, 0xbf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincw x0, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf3, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincw x0, w0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf3, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincw x0, w0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf3, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincw x0, w0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf3, 0xaf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincw x0, w0, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf0, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincw x0, w0, pow2"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf0, 0xaf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincw x0, w0, pow2, mul #16"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc3, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincw z0.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc3, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincw z0.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc3, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincw z0.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc3, 0xaf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincw z0.s, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincw z0.s, pow2"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0xaf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincw z0.s, pow2, mul #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf0, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincw x0, pow2"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf0, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincw x0, vl1"
+
+  -
+    input:
+      bytes: [ 0x40, 0xf0, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincw x0, vl2"
+
+  -
+    input:
+      bytes: [ 0x60, 0xf0, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincw x0, vl3"
+
+  -
+    input:
+      bytes: [ 0x80, 0xf0, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincw x0, vl4"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xf0, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincw x0, vl5"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xf0, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincw x0, vl6"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf0, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincw x0, vl7"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf1, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincw x0, vl8"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf1, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincw x0, vl16"
+
+  -
+    input:
+      bytes: [ 0x40, 0xf1, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincw x0, vl32"
+
+  -
+    input:
+      bytes: [ 0x60, 0xf1, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincw x0, vl64"
+
+  -
+    input:
+      bytes: [ 0x80, 0xf1, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincw x0, vl128"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xf1, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincw x0, vl256"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xf1, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincw x0, #14"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf1, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincw x0, #15"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf2, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincw x0, #16"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf2, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincw x0, #17"
+
+  -
+    input:
+      bytes: [ 0x40, 0xf2, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincw x0, #18"
+
+  -
+    input:
+      bytes: [ 0x60, 0xf2, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincw x0, #19"
+
+  -
+    input:
+      bytes: [ 0x80, 0xf2, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincw x0, #20"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xf2, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincw x0, #21"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xf2, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincw x0, #22"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf2, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincw x0, #23"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf3, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincw x0, #24"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf3, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincw x0, #25"
+
+  -
+    input:
+      bytes: [ 0x40, 0xf3, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincw x0, #26"
+
+  -
+    input:
+      bytes: [ 0x60, 0xf3, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincw x0, #27"
+
+  -
+    input:
+      bytes: [ 0x80, 0xf3, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincw x0, #28"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc3, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincw z0.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0xaf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincw z0.s, pow2, mul #16"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqincw z0.s, pow2"
diff --git a/tests/MC/AArch64/SVE/sqsub.s.yaml b/tests/MC/AArch64/SVE/sqsub.s.yaml
new file mode 100644
index 000000000..2a9c7da21
--- /dev/null
+++ b/tests/MC/AArch64/SVE/sqsub.s.yaml
@@ -0,0 +1,400 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x18, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqsub z0.b, z0.b, z0.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x18, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqsub z0.h, z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x18, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqsub z0.s, z0.s, z0.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0x18, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqsub z0.d, z0.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x26, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqsub z0.b, z0.b, #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0xdf, 0x26, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqsub z31.b, z31.b, #255"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x66, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqsub z0.h, z0.h, #0"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x66, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqsub z0.h, z0.h, #0, lsl #8"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0x66, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqsub z31.h, z31.h, #65280"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0x66, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqsub z31.h, z31.h, #65280"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0xa6, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqsub z0.s, z0.s, #0"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xa6, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqsub z0.s, z0.s, #0, lsl #8"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xa6, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqsub z31.s, z31.s, #65280"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xa6, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqsub z31.s, z31.s, #65280"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0xe6, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqsub z0.d, z0.d, #0"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xe6, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqsub z0.d, z0.d, #0, lsl #8"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xe6, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqsub z31.d, z31.d, #65280"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xe6, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqsub z31.d, z31.d, #65280"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xe6, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqsub z31.d, z31.d, #65280"
+
+  -
+    input:
+      bytes: [ 0x00, 0x18, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqsub z0.b, z0.b, z0.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x18, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqsub z0.h, z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x18, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqsub z0.s, z0.s, z0.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0x18, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqsub z0.d, z0.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x26, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqsub z0.b, z0.b, #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0xdf, 0x26, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqsub z31.b, z31.b, #255"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x66, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqsub z0.h, z0.h, #0"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x66, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqsub z0.h, z0.h, #0, lsl #8"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0x66, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqsub z31.h, z31.h, #65280"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0x66, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqsub z31.h, z31.h, #65280"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0xa6, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqsub z0.s, z0.s, #0"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xa6, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqsub z0.s, z0.s, #0, lsl #8"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xa6, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqsub z31.s, z31.s, #65280"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xa6, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqsub z31.s, z31.s, #65280"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0xe6, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqsub z0.d, z0.d, #0"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xe6, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqsub z0.d, z0.d, #0, lsl #8"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xe6, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqsub z31.d, z31.d, #65280"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xe6, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqsub z31.d, z31.d, #65280"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xe6, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqsub z31.d, z31.d, #65280"
diff --git a/tests/MC/AArch64/SVE/st1b-sve-only.s.yaml b/tests/MC/AArch64/SVE/st1b-sve-only.s.yaml
new file mode 100644
index 000000000..9fd4257f1
--- /dev/null
+++ b/tests/MC/AArch64/SVE/st1b-sve-only.s.yaml
@@ -0,0 +1,110 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x40, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b { z0.s }, p0, [x0, z0.s, uxtw]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x40, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b { z0.s }, p0, [x0, z0.s, sxtw]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x00, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b { z0.d }, p0, [x0, z0.d, uxtw]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x00, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b { z0.d }, p0, [x0, z0.d, sxtw]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x00, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b { z0.d }, p0, [x0, z0.d]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x7f, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b { z31.s }, p7, [z31.s, #31]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x5f, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b { z31.d }, p7, [z31.d, #31]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xbc, 0x60, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b { z0.s }, p7, [z0.s]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xbc, 0x60, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b { z0.s }, p7, [z0.s]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xbc, 0x40, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b { z0.d }, p7, [z0.d]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xbc, 0x40, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b { z0.d }, p7, [z0.d]"
diff --git a/tests/MC/AArch64/SVE/st1b.s.yaml b/tests/MC/AArch64/SVE/st1b.s.yaml
new file mode 100644
index 000000000..8081f2ecb
--- /dev/null
+++ b/tests/MC/AArch64/SVE/st1b.s.yaml
@@ -0,0 +1,400 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x00, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b { z0.b }, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x20, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b { z0.h }, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x40, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b { z0.s }, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x60, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b { z0.d }, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x00, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b { z0.b }, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x20, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b { z0.h }, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x40, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b { z0.s }, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x60, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b { z0.d }, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0x0f, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b { z31.b }, p7, [sp, #-1, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf5, 0x05, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b { z21.b }, p5, [x10, #5, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0x2f, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b { z31.h }, p7, [sp, #-1, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf5, 0x25, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b { z21.h }, p5, [x10, #5, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0x4f, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b { z31.s }, p7, [sp, #-1, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf5, 0x45, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b { z21.s }, p5, [x10, #5, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0x6f, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b { z31.d }, p7, [sp, #-1, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf5, 0x65, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b { z21.d }, p5, [x10, #5, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0x00, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b { z0.b }, p0, [x0, x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0x20, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b { z0.h }, p0, [x0, x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0x40, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b { z0.s }, p0, [x0, x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0x60, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b { z0.d }, p0, [x0, x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x00, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b { z0.b }, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x20, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b { z0.h }, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x40, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b { z0.s }, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x60, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b { z0.d }, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x00, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b { z0.b }, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x20, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b { z0.h }, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x40, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b { z0.s }, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x60, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b { z0.d }, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0x0f, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b { z31.b }, p7, [sp, #-1, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf5, 0x05, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b { z21.b }, p5, [x10, #5, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0x2f, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b { z31.h }, p7, [sp, #-1, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf5, 0x25, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b { z21.h }, p5, [x10, #5, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0x4f, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b { z31.s }, p7, [sp, #-1, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf5, 0x45, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b { z21.s }, p5, [x10, #5, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0x6f, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b { z31.d }, p7, [sp, #-1, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf5, 0x65, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b { z21.d }, p5, [x10, #5, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0x00, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b { z0.b }, p0, [x0, x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0x20, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b { z0.h }, p0, [x0, x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0x40, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b { z0.s }, p0, [x0, x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0x60, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b { z0.d }, p0, [x0, x0]"
diff --git a/tests/MC/AArch64/SVE/st1d-sve-only.s.yaml b/tests/MC/AArch64/SVE/st1d-sve-only.s.yaml
new file mode 100644
index 000000000..13b16a929
--- /dev/null
+++ b/tests/MC/AArch64/SVE/st1d-sve-only.s.yaml
@@ -0,0 +1,90 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x80, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d { z0.d }, p0, [x0, z0.d, uxtw]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x80, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d { z0.d }, p0, [x0, z0.d, sxtw]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xa0, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d { z0.d }, p0, [x0, z0.d, uxtw #3]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0xa0, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d { z0.d }, p0, [x0, z0.d, sxtw #3]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x80, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d { z0.d }, p0, [x0, z0.d]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xa0, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d { z0.d }, p0, [x0, z0.d, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0xdf, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d { z31.d }, p7, [z31.d, #248]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xbc, 0xc0, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d { z0.d }, p7, [z0.d]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xbc, 0xc0, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d { z0.d }, p7, [z0.d]"
diff --git a/tests/MC/AArch64/SVE/st1d.s.yaml b/tests/MC/AArch64/SVE/st1d.s.yaml
new file mode 100644
index 000000000..5e99624e8
--- /dev/null
+++ b/tests/MC/AArch64/SVE/st1d.s.yaml
@@ -0,0 +1,100 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xe0, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d { z0.d }, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xe0, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d { z0.d }, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xef, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d { z31.d }, p7, [sp, #-1, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf5, 0xe5, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d { z21.d }, p5, [x10, #5, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0xe0, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d { z0.d }, p0, [x0, x0, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xe0, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d { z0.d }, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xe0, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d { z0.d }, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xef, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d { z31.d }, p7, [sp, #-1, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf5, 0xe5, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d { z21.d }, p5, [x10, #5, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0xe0, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d { z0.d }, p0, [x0, x0, lsl #3]"
diff --git a/tests/MC/AArch64/SVE/st1h-sve-only.s.yaml b/tests/MC/AArch64/SVE/st1h-sve-only.s.yaml
new file mode 100644
index 000000000..523c4f6b4
--- /dev/null
+++ b/tests/MC/AArch64/SVE/st1h-sve-only.s.yaml
@@ -0,0 +1,160 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xc0, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h { z0.s }, p0, [x0, z0.s, uxtw]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0xc0, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h { z0.s }, p0, [x0, z0.s, sxtw]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x80, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h { z0.d }, p0, [x0, z0.d, uxtw]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x80, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h { z0.d }, p0, [x0, z0.d, sxtw]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xe0, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h { z0.s }, p0, [x0, z0.s, uxtw #1]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0xe0, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h { z0.s }, p0, [x0, z0.s, sxtw #1]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xa0, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h { z0.d }, p0, [x0, z0.d, uxtw #1]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0xa0, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h { z0.d }, p0, [x0, z0.d, sxtw #1]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x80, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h { z0.d }, p0, [x0, z0.d]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xa0, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h { z0.d }, p0, [x0, z0.d, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0xff, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h { z31.s }, p7, [z31.s, #62]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0xdf, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h { z31.d }, p7, [z31.d, #62]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xbc, 0xe0, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h { z0.s }, p7, [z0.s]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xbc, 0xe0, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h { z0.s }, p7, [z0.s]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xbc, 0xc0, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h { z0.d }, p7, [z0.d]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xbc, 0xc0, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h { z0.d }, p7, [z0.d]"
diff --git a/tests/MC/AArch64/SVE/st1h.s.yaml b/tests/MC/AArch64/SVE/st1h.s.yaml
new file mode 100644
index 000000000..09594b6f3
--- /dev/null
+++ b/tests/MC/AArch64/SVE/st1h.s.yaml
@@ -0,0 +1,300 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xa0, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h { z0.h }, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xc0, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h { z0.s }, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xe0, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h { z0.d }, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xa0, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h { z0.h }, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xc0, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h { z0.s }, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xe0, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h { z0.d }, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xaf, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h { z31.h }, p7, [sp, #-1, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf5, 0xa5, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h { z21.h }, p5, [x10, #5, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xcf, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h { z31.s }, p7, [sp, #-1, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf5, 0xc5, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h { z21.s }, p5, [x10, #5, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf5, 0xe5, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h { z21.d }, p5, [x10, #5, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xef, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h { z31.d }, p7, [sp, #-1, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0xa0, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h { z0.h }, p0, [x0, x0, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0xc0, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h { z0.s }, p0, [x0, x0, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0xe0, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h { z0.d }, p0, [x0, x0, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xa0, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h { z0.h }, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xc0, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h { z0.s }, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xe0, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h { z0.d }, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xa0, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h { z0.h }, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xc0, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h { z0.s }, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xe0, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h { z0.d }, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xaf, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h { z31.h }, p7, [sp, #-1, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf5, 0xa5, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h { z21.h }, p5, [x10, #5, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xcf, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h { z31.s }, p7, [sp, #-1, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf5, 0xc5, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h { z21.s }, p5, [x10, #5, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf5, 0xe5, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h { z21.d }, p5, [x10, #5, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xef, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h { z31.d }, p7, [sp, #-1, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0xa0, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h { z0.h }, p0, [x0, x0, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0xc0, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h { z0.s }, p0, [x0, x0, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0xe0, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h { z0.d }, p0, [x0, x0, lsl #1]"
diff --git a/tests/MC/AArch64/SVE/st1w-sve-only.s.yaml b/tests/MC/AArch64/SVE/st1w-sve-only.s.yaml
new file mode 100644
index 000000000..4f1a8cbbb
--- /dev/null
+++ b/tests/MC/AArch64/SVE/st1w-sve-only.s.yaml
@@ -0,0 +1,160 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x40, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w { z0.s }, p0, [x0, z0.s, uxtw]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x40, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w { z0.s }, p0, [x0, z0.s, sxtw]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x00, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w { z0.d }, p0, [x0, z0.d, uxtw]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x00, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w { z0.d }, p0, [x0, z0.d, sxtw]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x60, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w { z0.s }, p0, [x0, z0.s, uxtw #2]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x60, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w { z0.s }, p0, [x0, z0.s, sxtw #2]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x20, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w { z0.d }, p0, [x0, z0.d, uxtw #2]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x20, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w { z0.d }, p0, [x0, z0.d, sxtw #2]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x00, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w { z0.d }, p0, [x0, z0.d]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x20, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w { z0.d }, p0, [x0, z0.d, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x7f, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w { z31.s }, p7, [z31.s, #124]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x5f, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w { z31.d }, p7, [z31.d, #124]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xbc, 0x60, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w { z0.s }, p7, [z0.s]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xbc, 0x60, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w { z0.s }, p7, [z0.s]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xbc, 0x40, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w { z0.d }, p7, [z0.d]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xbc, 0x40, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w { z0.d }, p7, [z0.d]"
diff --git a/tests/MC/AArch64/SVE/st1w.s.yaml b/tests/MC/AArch64/SVE/st1w.s.yaml
new file mode 100644
index 000000000..f9eba6447
--- /dev/null
+++ b/tests/MC/AArch64/SVE/st1w.s.yaml
@@ -0,0 +1,200 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x40, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w { z0.s }, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x60, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w { z0.d }, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x40, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w { z0.s }, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x60, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w { z0.d }, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0x4f, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w { z31.s }, p7, [sp, #-1, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf5, 0x45, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w { z21.s }, p5, [x10, #5, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0x6f, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w { z31.d }, p7, [sp, #-1, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf5, 0x65, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w { z21.d }, p5, [x10, #5, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0x40, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w { z0.s }, p0, [x0, x0, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0x60, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w { z0.d }, p0, [x0, x0, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x40, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w { z0.s }, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x60, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w { z0.d }, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x40, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w { z0.s }, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x60, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w { z0.d }, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0x4f, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w { z31.s }, p7, [sp, #-1, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf5, 0x45, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w { z21.s }, p5, [x10, #5, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0x6f, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w { z31.d }, p7, [sp, #-1, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf5, 0x65, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w { z21.d }, p5, [x10, #5, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0x40, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w { z0.s }, p0, [x0, x0, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0x60, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w { z0.d }, p0, [x0, x0, lsl #2]"
diff --git a/tests/MC/AArch64/SVE/st2b.s.yaml b/tests/MC/AArch64/SVE/st2b.s.yaml
new file mode 100644
index 000000000..41cd7fa59
--- /dev/null
+++ b/tests/MC/AArch64/SVE/st2b.s.yaml
@@ -0,0 +1,100 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0x20, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st2b { z0.b, z1.b }, p0, [x0, x0]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x6e, 0x30, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st2b { z5.b, z6.b }, p3, [x17, x16]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x30, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st2b { z0.b, z1.b }, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0x38, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st2b { z23.b, z24.b }, p3, [x13, #-16, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf5, 0x35, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st2b { z21.b, z22.b }, p5, [x10, #10, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0x20, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st2b { z0.b, z1.b }, p0, [x0, x0]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x6e, 0x30, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st2b { z5.b, z6.b }, p3, [x17, x16]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x30, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st2b { z0.b, z1.b }, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0x38, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st2b { z23.b, z24.b }, p3, [x13, #-16, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf5, 0x35, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st2b { z21.b, z22.b }, p5, [x10, #10, mul vl]"
diff --git a/tests/MC/AArch64/SVE/st2d.s.yaml b/tests/MC/AArch64/SVE/st2d.s.yaml
new file mode 100644
index 000000000..db3dd9c05
--- /dev/null
+++ b/tests/MC/AArch64/SVE/st2d.s.yaml
@@ -0,0 +1,100 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0xa0, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st2d { z0.d, z1.d }, p0, [x0, x0, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x6e, 0xb0, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st2d { z5.d, z6.d }, p3, [x17, x16, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xb0, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st2d { z0.d, z1.d }, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0xb8, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st2d { z23.d, z24.d }, p3, [x13, #-16, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf5, 0xb5, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st2d { z21.d, z22.d }, p5, [x10, #10, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0xa0, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st2d { z0.d, z1.d }, p0, [x0, x0, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x6e, 0xb0, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st2d { z5.d, z6.d }, p3, [x17, x16, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xb0, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st2d { z0.d, z1.d }, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0xb8, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st2d { z23.d, z24.d }, p3, [x13, #-16, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf5, 0xb5, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st2d { z21.d, z22.d }, p5, [x10, #10, mul vl]"
diff --git a/tests/MC/AArch64/SVE/st2h.s.yaml b/tests/MC/AArch64/SVE/st2h.s.yaml
new file mode 100644
index 000000000..a50a3d396
--- /dev/null
+++ b/tests/MC/AArch64/SVE/st2h.s.yaml
@@ -0,0 +1,100 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0xa0, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st2h { z0.h, z1.h }, p0, [x0, x0, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x6e, 0xb0, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st2h { z5.h, z6.h }, p3, [x17, x16, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xb0, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st2h { z0.h, z1.h }, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0xb8, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st2h { z23.h, z24.h }, p3, [x13, #-16, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf5, 0xb5, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st2h { z21.h, z22.h }, p5, [x10, #10, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0xa0, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st2h { z0.h, z1.h }, p0, [x0, x0, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x6e, 0xb0, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st2h { z5.h, z6.h }, p3, [x17, x16, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xb0, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st2h { z0.h, z1.h }, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0xb8, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st2h { z23.h, z24.h }, p3, [x13, #-16, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf5, 0xb5, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st2h { z21.h, z22.h }, p5, [x10, #10, mul vl]"
diff --git a/tests/MC/AArch64/SVE/st2w.s.yaml b/tests/MC/AArch64/SVE/st2w.s.yaml
new file mode 100644
index 000000000..86395a0c9
--- /dev/null
+++ b/tests/MC/AArch64/SVE/st2w.s.yaml
@@ -0,0 +1,100 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0x20, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st2w { z0.s, z1.s }, p0, [x0, x0, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x6e, 0x30, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st2w { z5.s, z6.s }, p3, [x17, x16, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x30, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st2w { z0.s, z1.s }, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0x38, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st2w { z23.s, z24.s }, p3, [x13, #-16, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf5, 0x35, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st2w { z21.s, z22.s }, p5, [x10, #10, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0x20, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st2w { z0.s, z1.s }, p0, [x0, x0, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x6e, 0x30, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st2w { z5.s, z6.s }, p3, [x17, x16, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x30, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st2w { z0.s, z1.s }, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0x38, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st2w { z23.s, z24.s }, p3, [x13, #-16, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf5, 0x35, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st2w { z21.s, z22.s }, p5, [x10, #10, mul vl]"
diff --git a/tests/MC/AArch64/SVE/st3b.s.yaml b/tests/MC/AArch64/SVE/st3b.s.yaml
new file mode 100644
index 000000000..f23d2d27a
--- /dev/null
+++ b/tests/MC/AArch64/SVE/st3b.s.yaml
@@ -0,0 +1,100 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0x40, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st3b { z0.b - z2.b }, p0, [x0, x0]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x6e, 0x50, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st3b { z5.b - z7.b }, p3, [x17, x16]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x50, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st3b { z0.b - z2.b }, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0x58, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st3b { z23.b - z25.b }, p3, [x13, #-24, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf5, 0x55, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st3b { z21.b - z23.b }, p5, [x10, #15, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0x40, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st3b { z0.b - z2.b }, p0, [x0, x0]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x6e, 0x50, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st3b { z5.b - z7.b }, p3, [x17, x16]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x50, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st3b { z0.b - z2.b }, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0x58, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st3b { z23.b - z25.b }, p3, [x13, #-24, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf5, 0x55, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st3b { z21.b - z23.b }, p5, [x10, #15, mul vl]"
diff --git a/tests/MC/AArch64/SVE/st3d.s.yaml b/tests/MC/AArch64/SVE/st3d.s.yaml
new file mode 100644
index 000000000..d45593cab
--- /dev/null
+++ b/tests/MC/AArch64/SVE/st3d.s.yaml
@@ -0,0 +1,100 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0xc0, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st3d { z0.d - z2.d }, p0, [x0, x0, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x6e, 0xd0, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st3d { z5.d - z7.d }, p3, [x17, x16, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xd0, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st3d { z0.d - z2.d }, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0xd8, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st3d { z23.d - z25.d }, p3, [x13, #-24, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf5, 0xd5, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st3d { z21.d - z23.d }, p5, [x10, #15, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0xc0, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st3d { z0.d - z2.d }, p0, [x0, x0, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x6e, 0xd0, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st3d { z5.d - z7.d }, p3, [x17, x16, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xd0, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st3d { z0.d - z2.d }, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0xd8, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st3d { z23.d - z25.d }, p3, [x13, #-24, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf5, 0xd5, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st3d { z21.d - z23.d }, p5, [x10, #15, mul vl]"
diff --git a/tests/MC/AArch64/SVE/st3h.s.yaml b/tests/MC/AArch64/SVE/st3h.s.yaml
new file mode 100644
index 000000000..d642f0c53
--- /dev/null
+++ b/tests/MC/AArch64/SVE/st3h.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0xc0, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st3h { z0.h - z2.h }, p0, [x0, x0, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x6e, 0xd0, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st3h { z5.h - z7.h }, p3, [x17, x16, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xd0, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st3h { z0.h - z2.h }, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0xd8, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st3h { z23.h - z25.h }, p3, [x13, #-24, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf5, 0xd5, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st3h { z21.h - z23.h }, p5, [x10, #15, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x5f, 0xf5, 0xd5, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st3h { z31.h, z0.h, z1.h }, p5, [x10, #15, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0xc0, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st3h { z0.h - z2.h }, p0, [x0, x0, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x6e, 0xd0, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st3h { z5.h - z7.h }, p3, [x17, x16, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xd0, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st3h { z0.h - z2.h }, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0xd8, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st3h { z23.h - z25.h }, p3, [x13, #-24, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf5, 0xd5, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st3h { z21.h - z23.h }, p5, [x10, #15, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x5f, 0xf5, 0xd5, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st3h { z31.h, z0.h, z1.h }, p5, [x10, #15, mul vl]"
diff --git a/tests/MC/AArch64/SVE/st3w.s.yaml b/tests/MC/AArch64/SVE/st3w.s.yaml
new file mode 100644
index 000000000..35203ba08
--- /dev/null
+++ b/tests/MC/AArch64/SVE/st3w.s.yaml
@@ -0,0 +1,100 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0x40, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st3w { z0.s - z2.s }, p0, [x0, x0, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x6e, 0x50, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st3w { z5.s - z7.s }, p3, [x17, x16, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x50, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st3w { z0.s - z2.s }, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0x58, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st3w { z23.s - z25.s }, p3, [x13, #-24, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf5, 0x55, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st3w { z21.s - z23.s }, p5, [x10, #15, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0x40, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st3w { z0.s - z2.s }, p0, [x0, x0, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x6e, 0x50, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st3w { z5.s - z7.s }, p3, [x17, x16, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x50, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st3w { z0.s - z2.s }, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0x58, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st3w { z23.s - z25.s }, p3, [x13, #-24, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf5, 0x55, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st3w { z21.s - z23.s }, p5, [x10, #15, mul vl]"
diff --git a/tests/MC/AArch64/SVE/st4b.s.yaml b/tests/MC/AArch64/SVE/st4b.s.yaml
new file mode 100644
index 000000000..2afb6cfff
--- /dev/null
+++ b/tests/MC/AArch64/SVE/st4b.s.yaml
@@ -0,0 +1,100 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0x60, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st4b { z0.b - z3.b }, p0, [x0, x0]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x6e, 0x70, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st4b { z5.b - z8.b }, p3, [x17, x16]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x70, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st4b { z0.b - z3.b }, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0x78, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st4b { z23.b - z26.b }, p3, [x13, #-32, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf5, 0x75, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st4b { z21.b - z24.b }, p5, [x10, #20, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0x60, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st4b { z0.b - z3.b }, p0, [x0, x0]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x6e, 0x70, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st4b { z5.b - z8.b }, p3, [x17, x16]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x70, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st4b { z0.b - z3.b }, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0x78, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st4b { z23.b - z26.b }, p3, [x13, #-32, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf5, 0x75, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st4b { z21.b - z24.b }, p5, [x10, #20, mul vl]"
diff --git a/tests/MC/AArch64/SVE/st4d.s.yaml b/tests/MC/AArch64/SVE/st4d.s.yaml
new file mode 100644
index 000000000..a2378dbdf
--- /dev/null
+++ b/tests/MC/AArch64/SVE/st4d.s.yaml
@@ -0,0 +1,100 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0xe0, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st4d { z0.d - z3.d }, p0, [x0, x0, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x6e, 0xf0, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st4d { z5.d - z8.d }, p3, [x17, x16, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xf0, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st4d { z0.d - z3.d }, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0xf8, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st4d { z23.d - z26.d }, p3, [x13, #-32, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf5, 0xf5, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st4d { z21.d - z24.d }, p5, [x10, #20, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0xe0, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st4d { z0.d - z3.d }, p0, [x0, x0, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x6e, 0xf0, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st4d { z5.d - z8.d }, p3, [x17, x16, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xf0, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st4d { z0.d - z3.d }, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0xf8, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st4d { z23.d - z26.d }, p3, [x13, #-32, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf5, 0xf5, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st4d { z21.d - z24.d }, p5, [x10, #20, mul vl]"
diff --git a/tests/MC/AArch64/SVE/st4h.s.yaml b/tests/MC/AArch64/SVE/st4h.s.yaml
new file mode 100644
index 000000000..ad2737dbb
--- /dev/null
+++ b/tests/MC/AArch64/SVE/st4h.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0xe0, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st4h { z0.h - z3.h }, p0, [x0, x0, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x6e, 0xf0, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st4h { z5.h - z8.h }, p3, [x17, x16, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xf0, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st4h { z0.h - z3.h }, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0xf8, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st4h { z23.h - z26.h }, p3, [x13, #-32, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf5, 0xf5, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st4h { z21.h - z24.h }, p5, [x10, #20, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x5d, 0xf5, 0xf5, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st4h { z29.h, z30.h, z31.h, z0.h }, p5, [x10, #20, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0xe0, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st4h { z0.h - z3.h }, p0, [x0, x0, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x6e, 0xf0, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st4h { z5.h - z8.h }, p3, [x17, x16, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xf0, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st4h { z0.h - z3.h }, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0xf8, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st4h { z23.h - z26.h }, p3, [x13, #-32, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf5, 0xf5, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st4h { z21.h - z24.h }, p5, [x10, #20, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x5d, 0xf5, 0xf5, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st4h { z29.h, z30.h, z31.h, z0.h }, p5, [x10, #20, mul vl]"
diff --git a/tests/MC/AArch64/SVE/st4w.s.yaml b/tests/MC/AArch64/SVE/st4w.s.yaml
new file mode 100644
index 000000000..d69426834
--- /dev/null
+++ b/tests/MC/AArch64/SVE/st4w.s.yaml
@@ -0,0 +1,100 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0x60, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st4w { z0.s - z3.s }, p0, [x0, x0, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x6e, 0x70, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st4w { z5.s - z8.s }, p3, [x17, x16, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x70, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st4w { z0.s - z3.s }, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0x78, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st4w { z23.s - z26.s }, p3, [x13, #-32, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf5, 0x75, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "st4w { z21.s - z24.s }, p5, [x10, #20, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0x60, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st4w { z0.s - z3.s }, p0, [x0, x0, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x6e, 0x70, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st4w { z5.s - z8.s }, p3, [x17, x16, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x70, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st4w { z0.s - z3.s }, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0x78, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st4w { z23.s - z26.s }, p3, [x13, #-32, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf5, 0x75, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "st4w { z21.s - z24.s }, p5, [x10, #20, mul vl]"
diff --git a/tests/MC/AArch64/SVE/stnt1b.s.yaml b/tests/MC/AArch64/SVE/stnt1b.s.yaml
new file mode 100644
index 000000000..f76be54df
--- /dev/null
+++ b/tests/MC/AArch64/SVE/stnt1b.s.yaml
@@ -0,0 +1,100 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x10, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1b { z0.b }, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x10, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1b { z0.b }, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0x18, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1b { z23.b }, p3, [x13, #-8, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf5, 0x17, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1b { z21.b }, p5, [x10, #7, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0x00, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1b { z0.b }, p0, [x0, x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x10, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1b { z0.b }, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x10, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1b { z0.b }, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0x18, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1b { z23.b }, p3, [x13, #-8, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf5, 0x17, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1b { z21.b }, p5, [x10, #7, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0x00, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1b { z0.b }, p0, [x0, x0]"
diff --git a/tests/MC/AArch64/SVE/stnt1d.s.yaml b/tests/MC/AArch64/SVE/stnt1d.s.yaml
new file mode 100644
index 000000000..d9b11f616
--- /dev/null
+++ b/tests/MC/AArch64/SVE/stnt1d.s.yaml
@@ -0,0 +1,100 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x90, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1d { z0.d }, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x90, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1d { z0.d }, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0x98, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1d { z23.d }, p3, [x13, #-8, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf5, 0x97, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1d { z21.d }, p5, [x10, #7, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0x80, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1d { z0.d }, p0, [x0, x0, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x90, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1d { z0.d }, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x90, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1d { z0.d }, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0x98, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1d { z23.d }, p3, [x13, #-8, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf5, 0x97, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1d { z21.d }, p5, [x10, #7, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0x80, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1d { z0.d }, p0, [x0, x0, lsl #3]"
diff --git a/tests/MC/AArch64/SVE/stnt1h.s.yaml b/tests/MC/AArch64/SVE/stnt1h.s.yaml
new file mode 100644
index 000000000..685b0fc48
--- /dev/null
+++ b/tests/MC/AArch64/SVE/stnt1h.s.yaml
@@ -0,0 +1,100 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x90, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1h { z0.h }, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x90, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1h { z0.h }, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0x98, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1h { z23.h }, p3, [x13, #-8, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf5, 0x97, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1h { z21.h }, p5, [x10, #7, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0x80, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1h { z0.h }, p0, [x0, x0, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x90, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1h { z0.h }, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x90, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1h { z0.h }, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0x98, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1h { z23.h }, p3, [x13, #-8, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf5, 0x97, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1h { z21.h }, p5, [x10, #7, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0x80, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1h { z0.h }, p0, [x0, x0, lsl #1]"
diff --git a/tests/MC/AArch64/SVE/stnt1w.s.yaml b/tests/MC/AArch64/SVE/stnt1w.s.yaml
new file mode 100644
index 000000000..89c111e9c
--- /dev/null
+++ b/tests/MC/AArch64/SVE/stnt1w.s.yaml
@@ -0,0 +1,100 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x10, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1w { z0.s }, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x10, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1w { z0.s }, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0x18, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1w { z23.s }, p3, [x13, #-8, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf5, 0x17, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1w { z21.s }, p5, [x10, #7, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0x00, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1w { z0.s }, p0, [x0, x0, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x10, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1w { z0.s }, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x10, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1w { z0.s }, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0x18, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1w { z23.s }, p3, [x13, #-8, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf5, 0x17, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1w { z21.s }, p5, [x10, #7, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0x00, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1w { z0.s }, p0, [x0, x0, lsl #2]"
diff --git a/tests/MC/AArch64/SVE/str.s.yaml b/tests/MC/AArch64/SVE/str.s.yaml
new file mode 100644
index 000000000..069ccca0a
--- /dev/null
+++ b/tests/MC/AArch64/SVE/str.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0x80, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "str z0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x41, 0xa0, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "str z21, [x10, #-256, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x5f, 0x9f, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "str z31, [sp, #255, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x80, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "str p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0xef, 0x03, 0xa0, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "str p15, [sp, #-256, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x45, 0x1d, 0x9f, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "str p5, [x10, #255, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0x80, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "str z0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x41, 0xa0, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "str z21, [x10, #-256, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x5f, 0x9f, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "str z31, [sp, #255, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x80, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "str p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0xef, 0x03, 0xa0, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "str p15, [sp, #-256, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x45, 0x1d, 0x9f, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "str p5, [x10, #255, mul vl]"
diff --git a/tests/MC/AArch64/SVE/sub.s.yaml b/tests/MC/AArch64/SVE/sub.s.yaml
new file mode 100644
index 000000000..03c233472
--- /dev/null
+++ b/tests/MC/AArch64/SVE/sub.s.yaml
@@ -0,0 +1,1040 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x04, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub z0.h, z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x55, 0x05, 0x35, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub z21.b, z10.b, z21.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0xc1, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub z31.d, p7/m, z31.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x0d, 0x41, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub z23.h, p3/m, z23.h, z13.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x07, 0x7f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub z31.h, z31.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x55, 0x05, 0x75, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub z21.h, z10.h, z21.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x07, 0x3f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub z31.b, z31.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x04, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub z0.s, z0.s, z0.s"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x0d, 0x81, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub z23.s, p3/m, z23.s, z13.s"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x05, 0x28, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub z23.b, z13.b, z8.b"
+
+  -
+    input:
+      bytes: [ 0x55, 0x05, 0xf5, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub z21.d, z10.d, z21.d"
+
+  -
+    input:
+      bytes: [ 0x55, 0x05, 0xb5, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub z21.s, z10.s, z21.s"
+
+  -
+    input:
+      bytes: [ 0x55, 0x15, 0x81, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub z21.s, p5/m, z21.s, z10.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0x81, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub z31.s, p7/m, z31.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0xc1, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub z0.d, p0/m, z0.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x04, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub z0.b, z0.b, z0.b"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x05, 0xe8, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub z23.d, z13.d, z8.d"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x0d, 0xc1, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub z23.d, p3/m, z23.d, z13.d"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x05, 0xa8, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub z23.s, z13.s, z8.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0x01, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub z31.b, p7/m, z31.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x41, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub z0.h, p0/m, z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x07, 0xff, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub z31.d, z31.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0x41, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub z31.h, p7/m, z31.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x05, 0x68, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub z23.h, z13.h, z8.h"
+
+  -
+    input:
+      bytes: [ 0x55, 0x15, 0x01, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub z21.b, p5/m, z21.b, z10.b"
+
+  -
+    input:
+      bytes: [ 0x55, 0x15, 0xc1, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub z21.d, p5/m, z21.d, z10.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x04, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub z0.d, z0.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0x07, 0xbf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub z31.s, z31.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x01, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub z0.b, p0/m, z0.b, z0.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x81, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub z0.s, p0/m, z0.s, z0.s"
+
+  -
+    input:
+      bytes: [ 0x55, 0x15, 0x41, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub z21.h, p5/m, z21.h, z10.h"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x0d, 0x01, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub z23.b, p3/m, z23.b, z13.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x21, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub z0.b, z0.b, #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0xdf, 0x21, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub z31.b, z31.b, #255"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x61, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub z0.h, z0.h, #0"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x61, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub z0.h, z0.h, #0, lsl #8"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0x61, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub z31.h, z31.h, #65280"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0x61, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub z31.h, z31.h, #65280"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0xa1, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub z0.s, z0.s, #0"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xa1, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub z0.s, z0.s, #0, lsl #8"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xa1, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub z31.s, z31.s, #65280"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xa1, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub z31.s, z31.s, #65280"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0xe1, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub z0.d, z0.d, #0"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xe1, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub z0.d, z0.d, #0, lsl #8"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xe1, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub z31.d, z31.d, #65280"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xe1, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub z31.d, z31.d, #65280"
+
+  -
+    input:
+      bytes: [ 0xd7, 0x2f, 0x10, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z23.b, p3/z, z30.b"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x0d, 0x01, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub z23.b, p3/m, z23.b, z13.b"
+
+  -
+    input:
+      bytes: [ 0xd7, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z23, z30"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x0d, 0x01, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub z23.b, p3/m, z23.b, z13.b"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xe1, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub z31.d, z31.d, #65280"
+
+  -
+    input:
+      bytes: [ 0x00, 0x04, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub z0.h, z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x55, 0x05, 0x35, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub z21.b, z10.b, z21.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0xc1, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub z31.d, p7/m, z31.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x0d, 0x41, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub z23.h, p3/m, z23.h, z13.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x07, 0x7f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub z31.h, z31.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x55, 0x05, 0x75, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub z21.h, z10.h, z21.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x07, 0x3f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub z31.b, z31.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x04, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub z0.s, z0.s, z0.s"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x0d, 0x81, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub z23.s, p3/m, z23.s, z13.s"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x05, 0x28, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub z23.b, z13.b, z8.b"
+
+  -
+    input:
+      bytes: [ 0x55, 0x05, 0xf5, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub z21.d, z10.d, z21.d"
+
+  -
+    input:
+      bytes: [ 0x55, 0x05, 0xb5, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub z21.s, z10.s, z21.s"
+
+  -
+    input:
+      bytes: [ 0x55, 0x15, 0x81, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub z21.s, p5/m, z21.s, z10.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0x81, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub z31.s, p7/m, z31.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0xc1, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub z0.d, p0/m, z0.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x04, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub z0.b, z0.b, z0.b"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x05, 0xe8, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub z23.d, z13.d, z8.d"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x0d, 0xc1, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub z23.d, p3/m, z23.d, z13.d"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x05, 0xa8, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub z23.s, z13.s, z8.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0x01, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub z31.b, p7/m, z31.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x41, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub z0.h, p0/m, z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x07, 0xff, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub z31.d, z31.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0x41, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub z31.h, p7/m, z31.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x05, 0x68, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub z23.h, z13.h, z8.h"
+
+  -
+    input:
+      bytes: [ 0x55, 0x15, 0x01, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub z21.b, p5/m, z21.b, z10.b"
+
+  -
+    input:
+      bytes: [ 0x55, 0x15, 0xc1, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub z21.d, p5/m, z21.d, z10.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x04, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub z0.d, z0.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0x07, 0xbf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub z31.s, z31.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x01, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub z0.b, p0/m, z0.b, z0.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x81, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub z0.s, p0/m, z0.s, z0.s"
+
+  -
+    input:
+      bytes: [ 0x55, 0x15, 0x41, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub z21.h, p5/m, z21.h, z10.h"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x0d, 0x01, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub z23.b, p3/m, z23.b, z13.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x21, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub z0.b, z0.b, #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0xdf, 0x21, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub z31.b, z31.b, #255"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x61, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub z0.h, z0.h, #0"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x61, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub z0.h, z0.h, #0, lsl #8"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0x61, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub z31.h, z31.h, #65280"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0x61, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub z31.h, z31.h, #65280"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0xa1, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub z0.s, z0.s, #0"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xa1, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub z0.s, z0.s, #0, lsl #8"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xa1, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub z31.s, z31.s, #65280"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xa1, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub z31.s, z31.s, #65280"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0xe1, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub z0.d, z0.d, #0"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xe1, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub z0.d, z0.d, #0, lsl #8"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xe1, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub z31.d, z31.d, #65280"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xe1, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub z31.d, z31.d, #65280"
+
+  -
+    input:
+      bytes: [ 0xd7, 0x2f, 0x10, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z23.b, p3/z, z30.b"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x0d, 0x01, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub z23.b, p3/m, z23.b, z13.b"
+
+  -
+    input:
+      bytes: [ 0xd7, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z23, z30"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x0d, 0x01, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub z23.b, p3/m, z23.b, z13.b"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xe1, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub z31.d, z31.d, #65280"
diff --git a/tests/MC/AArch64/SVE/subr.s.yaml b/tests/MC/AArch64/SVE/subr.s.yaml
new file mode 100644
index 000000000..af0727116
--- /dev/null
+++ b/tests/MC/AArch64/SVE/subr.s.yaml
@@ -0,0 +1,480 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x03, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "subr z0.b, p0/m, z0.b, z0.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x43, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "subr z0.h, p0/m, z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x83, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "subr z0.s, p0/m, z0.s, z0.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0xc3, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "subr z0.d, p0/m, z0.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x23, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "subr z0.b, z0.b, #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0xdf, 0x23, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "subr z31.b, z31.b, #255"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x63, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "subr z0.h, z0.h, #0"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x63, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "subr z0.h, z0.h, #0, lsl #8"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0x63, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "subr z31.h, z31.h, #65280"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0x63, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "subr z31.h, z31.h, #65280"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0xa3, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "subr z0.s, z0.s, #0"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xa3, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "subr z0.s, z0.s, #0, lsl #8"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xa3, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "subr z31.s, z31.s, #65280"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xa3, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "subr z31.s, z31.s, #65280"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0xe3, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "subr z0.d, z0.d, #0"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xe3, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "subr z0.d, z0.d, #0, lsl #8"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xe3, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "subr z31.d, z31.d, #65280"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xe3, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "subr z31.d, z31.d, #65280"
+
+  -
+    input:
+      bytes: [ 0xe5, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z5.d, p0/z, z7.d"
+
+  -
+    input:
+      bytes: [ 0x05, 0x00, 0xc3, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "subr z5.d, p0/m, z5.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0xe5, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z5, z7"
+
+  -
+    input:
+      bytes: [ 0x05, 0x00, 0xc3, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "subr z5.d, p0/m, z5.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xe3, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "subr z31.d, z31.d, #65280"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x03, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "subr z0.b, p0/m, z0.b, z0.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x43, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "subr z0.h, p0/m, z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x83, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "subr z0.s, p0/m, z0.s, z0.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0xc3, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "subr z0.d, p0/m, z0.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x23, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "subr z0.b, z0.b, #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0xdf, 0x23, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "subr z31.b, z31.b, #255"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x63, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "subr z0.h, z0.h, #0"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x63, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "subr z0.h, z0.h, #0, lsl #8"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0x63, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "subr z31.h, z31.h, #65280"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0x63, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "subr z31.h, z31.h, #65280"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0xa3, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "subr z0.s, z0.s, #0"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xa3, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "subr z0.s, z0.s, #0, lsl #8"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xa3, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "subr z31.s, z31.s, #65280"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xa3, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "subr z31.s, z31.s, #65280"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0xe3, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "subr z0.d, z0.d, #0"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xe3, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "subr z0.d, z0.d, #0, lsl #8"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xe3, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "subr z31.d, z31.d, #65280"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xe3, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "subr z31.d, z31.d, #65280"
+
+  -
+    input:
+      bytes: [ 0xe5, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z5.d, p0/z, z7.d"
+
+  -
+    input:
+      bytes: [ 0x05, 0x00, 0xc3, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "subr z5.d, p0/m, z5.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0xe5, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z5, z7"
+
+  -
+    input:
+      bytes: [ 0x05, 0x00, 0xc3, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "subr z5.d, p0/m, z5.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xe3, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "subr z31.d, z31.d, #65280"
diff --git a/tests/MC/AArch64/SVE/sunpkhi.s.yaml b/tests/MC/AArch64/SVE/sunpkhi.s.yaml
new file mode 100644
index 000000000..c11b23cb3
--- /dev/null
+++ b/tests/MC/AArch64/SVE/sunpkhi.s.yaml
@@ -0,0 +1,60 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xff, 0x3b, 0x71, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sunpkhi z31.h, z31.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3b, 0xb1, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sunpkhi z31.s, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3b, 0xf1, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sunpkhi z31.d, z31.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3b, 0x71, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sunpkhi z31.h, z31.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3b, 0xb1, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sunpkhi z31.s, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3b, 0xf1, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sunpkhi z31.d, z31.s"
diff --git a/tests/MC/AArch64/SVE/sunpklo.s.yaml b/tests/MC/AArch64/SVE/sunpklo.s.yaml
new file mode 100644
index 000000000..15c56f8c2
--- /dev/null
+++ b/tests/MC/AArch64/SVE/sunpklo.s.yaml
@@ -0,0 +1,60 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xff, 0x3b, 0x70, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sunpklo z31.h, z31.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3b, 0xb0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sunpklo z31.s, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3b, 0xf0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sunpklo z31.d, z31.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3b, 0x70, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sunpklo z31.h, z31.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3b, 0xb0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sunpklo z31.s, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3b, 0xf0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sunpklo z31.d, z31.s"
diff --git a/tests/MC/AArch64/SVE/sxtb.s.yaml b/tests/MC/AArch64/SVE/sxtb.s.yaml
new file mode 100644
index 000000000..201899f03
--- /dev/null
+++ b/tests/MC/AArch64/SVE/sxtb.s.yaml
@@ -0,0 +1,200 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x50, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sxtb z0.h, p0/m, z0.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x90, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sxtb z0.s, p0/m, z0.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sxtb z0.d, p0/m, z0.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x50, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sxtb z31.h, p7/m, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x90, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sxtb z31.s, p7/m, z31.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sxtb z31.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4.d, p7/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xbf, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sxtb z4.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4, z6"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xbf, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sxtb z4.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x50, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sxtb z0.h, p0/m, z0.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x90, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sxtb z0.s, p0/m, z0.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sxtb z0.d, p0/m, z0.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x50, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sxtb z31.h, p7/m, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x90, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sxtb z31.s, p7/m, z31.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sxtb z31.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4.d, p7/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xbf, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sxtb z4.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4, z6"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xbf, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sxtb z4.d, p7/m, z31.d"
diff --git a/tests/MC/AArch64/SVE/sxth.s.yaml b/tests/MC/AArch64/SVE/sxth.s.yaml
new file mode 100644
index 000000000..d4513c946
--- /dev/null
+++ b/tests/MC/AArch64/SVE/sxth.s.yaml
@@ -0,0 +1,160 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x92, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sxth z0.s, p0/m, z0.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xd2, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sxth z0.d, p0/m, z0.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x92, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sxth z31.s, p7/m, z31.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0xd2, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sxth z31.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4.d, p7/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xbf, 0xd2, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sxth z4.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4, z6"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xbf, 0xd2, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sxth z4.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x92, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sxth z0.s, p0/m, z0.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xd2, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sxth z0.d, p0/m, z0.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x92, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sxth z31.s, p7/m, z31.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0xd2, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sxth z31.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4.d, p7/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xbf, 0xd2, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sxth z4.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4, z6"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xbf, 0xd2, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sxth z4.d, p7/m, z31.d"
diff --git a/tests/MC/AArch64/SVE/sxtw.s.yaml b/tests/MC/AArch64/SVE/sxtw.s.yaml
new file mode 100644
index 000000000..299eea6c6
--- /dev/null
+++ b/tests/MC/AArch64/SVE/sxtw.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xd4, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sxtw z0.d, p0/m, z0.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0xd4, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sxtw z31.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4.d, p7/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xbf, 0xd4, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sxtw z4.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4, z6"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xbf, 0xd4, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "sxtw z4.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xd4, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sxtw z0.d, p0/m, z0.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0xd4, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sxtw z31.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4.d, p7/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xbf, 0xd4, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sxtw z4.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4, z6"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xbf, 0xd4, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sxtw z4.d, p7/m, z31.d"
diff --git a/tests/MC/AArch64/SVE/system-regs.s.yaml b/tests/MC/AArch64/SVE/system-regs.s.yaml
new file mode 100644
index 000000000..8f43ec024
--- /dev/null
+++ b/tests/MC/AArch64/SVE/system-regs.s.yaml
@@ -0,0 +1,90 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x83, 0x04, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, ID_AA64ZFR0_EL1"
+
+  -
+    input:
+      bytes: [ 0x03, 0x12, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, ZCR_EL1"
+
+  -
+    input:
+      bytes: [ 0x03, 0x12, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, ZCR_EL2"
+
+  -
+    input:
+      bytes: [ 0x03, 0x12, 0x3e, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, ZCR_EL3"
+
+  -
+    input:
+      bytes: [ 0x03, 0x12, 0x3d, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, ZCR_EL12"
+
+  -
+    input:
+      bytes: [ 0x03, 0x12, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ZCR_EL1, x3"
+
+  -
+    input:
+      bytes: [ 0x03, 0x12, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ZCR_EL2, x3"
+
+  -
+    input:
+      bytes: [ 0x03, 0x12, 0x1e, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ZCR_EL3, x3"
+
+  -
+    input:
+      bytes: [ 0x03, 0x12, 0x1d, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ZCR_EL12, x3"
diff --git a/tests/MC/AArch64/SVE/tbl.s.yaml b/tests/MC/AArch64/SVE/tbl.s.yaml
new file mode 100644
index 000000000..fab13ece2
--- /dev/null
+++ b/tests/MC/AArch64/SVE/tbl.s.yaml
@@ -0,0 +1,160 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xff, 0x33, 0x3f, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "tbl z31.b, { z31.b }, z31.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x33, 0x7f, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "tbl z31.h, { z31.h }, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x33, 0xbf, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "tbl z31.s, { z31.s }, z31.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0x33, 0xff, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "tbl z31.d, { z31.d }, z31.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0x33, 0x3f, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "tbl z31.b, { z31.b }, z31.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x33, 0x7f, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "tbl z31.h, { z31.h }, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x33, 0xbf, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "tbl z31.s, { z31.s }, z31.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0x33, 0xff, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "tbl z31.d, { z31.d }, z31.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0x33, 0x3f, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "tbl z31.b, { z31.b }, z31.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x33, 0x7f, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "tbl z31.h, { z31.h }, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x33, 0xbf, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "tbl z31.s, { z31.s }, z31.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0x33, 0xff, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "tbl z31.d, { z31.d }, z31.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0x33, 0x3f, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "tbl z31.b, { z31.b }, z31.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x33, 0x7f, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "tbl z31.h, { z31.h }, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x33, 0xbf, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "tbl z31.s, { z31.s }, z31.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0x33, 0xff, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "tbl z31.d, { z31.d }, z31.d"
diff --git a/tests/MC/AArch64/SVE/trn1.s.yaml b/tests/MC/AArch64/SVE/trn1.s.yaml
new file mode 100644
index 000000000..554e6fac5
--- /dev/null
+++ b/tests/MC/AArch64/SVE/trn1.s.yaml
@@ -0,0 +1,160 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xff, 0x73, 0x3f, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "trn1 z31.b, z31.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x73, 0x7f, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "trn1 z31.h, z31.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x73, 0xbf, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "trn1 z31.s, z31.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0x73, 0xff, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "trn1 z31.d, z31.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xef, 0x51, 0x2f, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "trn1 p15.b, p15.b, p15.b"
+
+  -
+    input:
+      bytes: [ 0xef, 0x51, 0xaf, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "trn1 p15.s, p15.s, p15.s"
+
+  -
+    input:
+      bytes: [ 0xef, 0x51, 0x6f, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "trn1 p15.h, p15.h, p15.h"
+
+  -
+    input:
+      bytes: [ 0xef, 0x51, 0xef, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "trn1 p15.d, p15.d, p15.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0x73, 0x3f, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "trn1 z31.b, z31.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x73, 0x7f, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "trn1 z31.h, z31.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x73, 0xbf, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "trn1 z31.s, z31.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0x73, 0xff, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "trn1 z31.d, z31.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xef, 0x51, 0x2f, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "trn1 p15.b, p15.b, p15.b"
+
+  -
+    input:
+      bytes: [ 0xef, 0x51, 0xaf, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "trn1 p15.s, p15.s, p15.s"
+
+  -
+    input:
+      bytes: [ 0xef, 0x51, 0x6f, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "trn1 p15.h, p15.h, p15.h"
+
+  -
+    input:
+      bytes: [ 0xef, 0x51, 0xef, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "trn1 p15.d, p15.d, p15.d"
diff --git a/tests/MC/AArch64/SVE/trn2.s.yaml b/tests/MC/AArch64/SVE/trn2.s.yaml
new file mode 100644
index 000000000..3916ba4fc
--- /dev/null
+++ b/tests/MC/AArch64/SVE/trn2.s.yaml
@@ -0,0 +1,160 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xff, 0x77, 0x3f, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "trn2 z31.b, z31.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x77, 0x7f, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "trn2 z31.h, z31.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x77, 0xbf, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "trn2 z31.s, z31.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0x77, 0xff, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "trn2 z31.d, z31.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xef, 0x55, 0x2f, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "trn2 p15.b, p15.b, p15.b"
+
+  -
+    input:
+      bytes: [ 0xef, 0x55, 0xaf, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "trn2 p15.s, p15.s, p15.s"
+
+  -
+    input:
+      bytes: [ 0xef, 0x55, 0x6f, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "trn2 p15.h, p15.h, p15.h"
+
+  -
+    input:
+      bytes: [ 0xef, 0x55, 0xef, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "trn2 p15.d, p15.d, p15.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0x77, 0x3f, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "trn2 z31.b, z31.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x77, 0x7f, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "trn2 z31.h, z31.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x77, 0xbf, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "trn2 z31.s, z31.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0x77, 0xff, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "trn2 z31.d, z31.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xef, 0x55, 0x2f, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "trn2 p15.b, p15.b, p15.b"
+
+  -
+    input:
+      bytes: [ 0xef, 0x55, 0xaf, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "trn2 p15.s, p15.s, p15.s"
+
+  -
+    input:
+      bytes: [ 0xef, 0x55, 0x6f, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "trn2 p15.h, p15.h, p15.h"
+
+  -
+    input:
+      bytes: [ 0xef, 0x55, 0xef, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "trn2 p15.d, p15.d, p15.d"
diff --git a/tests/MC/AArch64/SVE/uabd.s.yaml b/tests/MC/AArch64/SVE/uabd.s.yaml
new file mode 100644
index 000000000..ef4da413f
--- /dev/null
+++ b/tests/MC/AArch64/SVE/uabd.s.yaml
@@ -0,0 +1,160 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0x0d, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uabd z31.b, p7/m, z31.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0x4d, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uabd z31.h, p7/m, z31.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0x8d, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uabd z31.s, p7/m, z31.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0xcd, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uabd z31.d, p7/m, z31.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4.d, p7/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xe4, 0x1f, 0xcd, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uabd z4.d, p7/m, z4.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4, z6"
+
+  -
+    input:
+      bytes: [ 0xe4, 0x1f, 0xcd, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uabd z4.d, p7/m, z4.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0x0d, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uabd z31.b, p7/m, z31.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0x4d, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uabd z31.h, p7/m, z31.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0x8d, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uabd z31.s, p7/m, z31.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0xcd, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uabd z31.d, p7/m, z31.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4.d, p7/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xe4, 0x1f, 0xcd, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uabd z4.d, p7/m, z4.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4, z6"
+
+  -
+    input:
+      bytes: [ 0xe4, 0x1f, 0xcd, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uabd z4.d, p7/m, z4.d, z31.d"
diff --git a/tests/MC/AArch64/SVE/uaddv.s.yaml b/tests/MC/AArch64/SVE/uaddv.s.yaml
new file mode 100644
index 000000000..99d4a16e3
--- /dev/null
+++ b/tests/MC/AArch64/SVE/uaddv.s.yaml
@@ -0,0 +1,80 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xe0, 0x3f, 0x01, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uaddv d0, p7, z31.b"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3f, 0x41, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uaddv d0, p7, z31.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3f, 0x81, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uaddv d0, p7, z31.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3f, 0xc1, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uaddv d0, p7, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3f, 0x01, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uaddv d0, p7, z31.b"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3f, 0x41, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uaddv d0, p7, z31.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3f, 0x81, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uaddv d0, p7, z31.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3f, 0xc1, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uaddv d0, p7, z31.d"
diff --git a/tests/MC/AArch64/SVE/ucvtf.s.yaml b/tests/MC/AArch64/SVE/ucvtf.s.yaml
new file mode 100644
index 000000000..22cd34323
--- /dev/null
+++ b/tests/MC/AArch64/SVE/ucvtf.s.yaml
@@ -0,0 +1,220 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x53, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ucvtf z0.h, p0/m, z0.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x55, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ucvtf z0.h, p0/m, z0.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x57, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ucvtf z0.h, p0/m, z0.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x95, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ucvtf z0.s, p0/m, z0.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xd5, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ucvtf z0.s, p0/m, z0.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xd1, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ucvtf z0.d, p0/m, z0.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xd7, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ucvtf z0.d, p0/m, z0.d"
+
+  -
+    input:
+      bytes: [ 0xe5, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z5.d, p0/z, z7.d"
+
+  -
+    input:
+      bytes: [ 0x05, 0xa0, 0xd7, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ucvtf z5.d, p0/m, z0.d"
+
+  -
+    input:
+      bytes: [ 0xe5, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z5, z7"
+
+  -
+    input:
+      bytes: [ 0x05, 0xa0, 0xd7, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "ucvtf z5.d, p0/m, z0.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x53, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ucvtf z0.h, p0/m, z0.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x55, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ucvtf z0.h, p0/m, z0.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x57, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ucvtf z0.h, p0/m, z0.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x95, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ucvtf z0.s, p0/m, z0.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xd5, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ucvtf z0.s, p0/m, z0.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xd1, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ucvtf z0.d, p0/m, z0.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xd7, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ucvtf z0.d, p0/m, z0.d"
+
+  -
+    input:
+      bytes: [ 0xe5, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z5.d, p0/z, z7.d"
+
+  -
+    input:
+      bytes: [ 0x05, 0xa0, 0xd7, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ucvtf z5.d, p0/m, z0.d"
+
+  -
+    input:
+      bytes: [ 0xe5, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z5, z7"
+
+  -
+    input:
+      bytes: [ 0x05, 0xa0, 0xd7, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ucvtf z5.d, p0/m, z0.d"
diff --git a/tests/MC/AArch64/SVE/udiv.s.yaml b/tests/MC/AArch64/SVE/udiv.s.yaml
new file mode 100644
index 000000000..f6c1209dc
--- /dev/null
+++ b/tests/MC/AArch64/SVE/udiv.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xe0, 0x1f, 0x95, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "udiv z0.s, p7/m, z0.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x1f, 0xd5, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "udiv z0.d, p7/m, z0.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0.d, p7/z, z7.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x1f, 0xd5, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "udiv z0.d, p7/m, z0.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x1f, 0xd5, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "udiv z0.d, p7/m, z0.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x1f, 0x95, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "udiv z0.s, p7/m, z0.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x1f, 0xd5, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "udiv z0.d, p7/m, z0.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0.d, p7/z, z7.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x1f, 0xd5, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "udiv z0.d, p7/m, z0.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x1f, 0xd5, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "udiv z0.d, p7/m, z0.d, z31.d"
diff --git a/tests/MC/AArch64/SVE/udivr.s.yaml b/tests/MC/AArch64/SVE/udivr.s.yaml
new file mode 100644
index 000000000..91c47265e
--- /dev/null
+++ b/tests/MC/AArch64/SVE/udivr.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xe0, 0x1f, 0x97, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "udivr z0.s, p7/m, z0.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x1f, 0xd7, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "udivr z0.d, p7/m, z0.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0.d, p7/z, z7.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x1f, 0xd7, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "udivr z0.d, p7/m, z0.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x1f, 0xd7, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "udivr z0.d, p7/m, z0.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x1f, 0x97, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "udivr z0.s, p7/m, z0.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x1f, 0xd7, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "udivr z0.d, p7/m, z0.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0.d, p7/z, z7.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x1f, 0xd7, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "udivr z0.d, p7/m, z0.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x1f, 0xd7, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "udivr z0.d, p7/m, z0.d, z31.d"
diff --git a/tests/MC/AArch64/SVE/udot.s.yaml b/tests/MC/AArch64/SVE/udot.s.yaml
new file mode 100644
index 000000000..5e1e21ca5
--- /dev/null
+++ b/tests/MC/AArch64/SVE/udot.s.yaml
@@ -0,0 +1,160 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x04, 0x9f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot z0.s, z1.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x04, 0xdf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot z0.d, z1.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x04, 0xbf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot z0.s, z1.b, z7.b[3]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x04, 0xff, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot z0.d, z1.h, z15.h[1]"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x20, 0x04, 0xdf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot z0.d, z1.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x20, 0x04, 0xff, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot z0.d, z1.h, z15.h[1]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x04, 0x9f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot z0.s, z1.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x04, 0xdf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot z0.d, z1.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x04, 0xbf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot z0.s, z1.b, z7.b[3]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x04, 0xff, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot z0.d, z1.h, z15.h[1]"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x20, 0x04, 0xdf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot z0.d, z1.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x20, 0x04, 0xff, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot z0.d, z1.h, z15.h[1]"
diff --git a/tests/MC/AArch64/SVE/umax.s.yaml b/tests/MC/AArch64/SVE/umax.s.yaml
new file mode 100644
index 000000000..dabc96d71
--- /dev/null
+++ b/tests/MC/AArch64/SVE/umax.s.yaml
@@ -0,0 +1,360 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x29, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax z0.b, z0.b, #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0xdf, 0x29, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax z31.b, z31.b, #255"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x29, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax z0.b, z0.b, #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0xdf, 0x29, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax z31.b, z31.b, #255"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x29, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax z0.b, z0.b, #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0xdf, 0x29, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax z31.b, z31.b, #255"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x29, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax z0.b, z0.b, #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0xdf, 0x29, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax z31.b, z31.b, #255"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0x09, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax z31.b, p7/m, z31.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0x49, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax z31.h, p7/m, z31.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0x89, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax z31.s, p7/m, z31.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0xc9, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax z31.d, p7/m, z31.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4.d, p7/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xe4, 0x1f, 0xc9, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax z4.d, p7/m, z4.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4, z6"
+
+  -
+    input:
+      bytes: [ 0xe4, 0x1f, 0xc9, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax z4.d, p7/m, z4.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xff, 0xdf, 0x29, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax z31.b, z31.b, #255"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x29, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax z0.b, z0.b, #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0xdf, 0x29, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax z31.b, z31.b, #255"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x29, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax z0.b, z0.b, #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0xdf, 0x29, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax z31.b, z31.b, #255"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x29, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax z0.b, z0.b, #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0xdf, 0x29, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax z31.b, z31.b, #255"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x29, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax z0.b, z0.b, #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0xdf, 0x29, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax z31.b, z31.b, #255"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0x09, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax z31.b, p7/m, z31.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0x49, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax z31.h, p7/m, z31.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0x89, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax z31.s, p7/m, z31.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0xc9, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax z31.d, p7/m, z31.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4.d, p7/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xe4, 0x1f, 0xc9, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax z4.d, p7/m, z4.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4, z6"
+
+  -
+    input:
+      bytes: [ 0xe4, 0x1f, 0xc9, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax z4.d, p7/m, z4.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xff, 0xdf, 0x29, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax z31.b, z31.b, #255"
diff --git a/tests/MC/AArch64/SVE/umaxv.s.yaml b/tests/MC/AArch64/SVE/umaxv.s.yaml
new file mode 100644
index 000000000..d43352f9f
--- /dev/null
+++ b/tests/MC/AArch64/SVE/umaxv.s.yaml
@@ -0,0 +1,80 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xe0, 0x3f, 0x09, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "umaxv b0, p7, z31.b"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3f, 0x49, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "umaxv h0, p7, z31.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3f, 0x89, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "umaxv s0, p7, z31.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3f, 0xc9, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "umaxv d0, p7, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3f, 0x09, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "umaxv b0, p7, z31.b"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3f, 0x49, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "umaxv h0, p7, z31.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3f, 0x89, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "umaxv s0, p7, z31.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3f, 0xc9, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "umaxv d0, p7, z31.d"
diff --git a/tests/MC/AArch64/SVE/umin.s.yaml b/tests/MC/AArch64/SVE/umin.s.yaml
new file mode 100644
index 000000000..e69e2f97a
--- /dev/null
+++ b/tests/MC/AArch64/SVE/umin.s.yaml
@@ -0,0 +1,360 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x2b, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin z0.b, z0.b, #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0xdf, 0x2b, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin z31.b, z31.b, #255"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x2b, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin z0.b, z0.b, #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0xdf, 0x2b, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin z31.b, z31.b, #255"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x2b, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin z0.b, z0.b, #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0xdf, 0x2b, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin z31.b, z31.b, #255"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x2b, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin z0.b, z0.b, #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0xdf, 0x2b, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin z31.b, z31.b, #255"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0x0b, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin z31.b, p7/m, z31.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0x4b, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin z31.h, p7/m, z31.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0x8b, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin z31.s, p7/m, z31.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0xcb, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin z31.d, p7/m, z31.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4.d, p7/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xe4, 0x1f, 0xcb, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin z4.d, p7/m, z4.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4, z6"
+
+  -
+    input:
+      bytes: [ 0xe4, 0x1f, 0xcb, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin z4.d, p7/m, z4.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xff, 0xdf, 0x2b, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin z31.b, z31.b, #255"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x2b, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin z0.b, z0.b, #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0xdf, 0x2b, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin z31.b, z31.b, #255"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x2b, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin z0.b, z0.b, #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0xdf, 0x2b, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin z31.b, z31.b, #255"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x2b, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin z0.b, z0.b, #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0xdf, 0x2b, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin z31.b, z31.b, #255"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x2b, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin z0.b, z0.b, #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0xdf, 0x2b, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin z31.b, z31.b, #255"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0x0b, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin z31.b, p7/m, z31.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0x4b, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin z31.h, p7/m, z31.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0x8b, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin z31.s, p7/m, z31.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0xcb, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin z31.d, p7/m, z31.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4.d, p7/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xe4, 0x1f, 0xcb, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin z4.d, p7/m, z4.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4, z6"
+
+  -
+    input:
+      bytes: [ 0xe4, 0x1f, 0xcb, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin z4.d, p7/m, z4.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xff, 0xdf, 0x2b, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin z31.b, z31.b, #255"
diff --git a/tests/MC/AArch64/SVE/uminv.s.yaml b/tests/MC/AArch64/SVE/uminv.s.yaml
new file mode 100644
index 000000000..8b2d23a51
--- /dev/null
+++ b/tests/MC/AArch64/SVE/uminv.s.yaml
@@ -0,0 +1,80 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xe0, 0x3f, 0x0b, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uminv b0, p7, z31.b"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3f, 0x4b, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uminv h0, p7, z31.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3f, 0x8b, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uminv s0, p7, z31.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3f, 0xcb, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uminv d0, p7, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3f, 0x0b, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uminv b0, p7, z31.b"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3f, 0x4b, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uminv h0, p7, z31.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3f, 0x8b, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uminv s0, p7, z31.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3f, 0xcb, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uminv d0, p7, z31.d"
diff --git a/tests/MC/AArch64/SVE/umulh.s.yaml b/tests/MC/AArch64/SVE/umulh.s.yaml
new file mode 100644
index 000000000..ad883d4e2
--- /dev/null
+++ b/tests/MC/AArch64/SVE/umulh.s.yaml
@@ -0,0 +1,160 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xe0, 0x1f, 0x13, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "umulh z0.b, p7/m, z0.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x1f, 0x53, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "umulh z0.h, p7/m, z0.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x1f, 0x93, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "umulh z0.s, p7/m, z0.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x1f, 0xd3, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "umulh z0.d, p7/m, z0.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0.d, p7/z, z7.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x1f, 0xd3, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "umulh z0.d, p7/m, z0.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x1f, 0xd3, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "umulh z0.d, p7/m, z0.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x1f, 0x13, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "umulh z0.b, p7/m, z0.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x1f, 0x53, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "umulh z0.h, p7/m, z0.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x1f, 0x93, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "umulh z0.s, p7/m, z0.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x1f, 0xd3, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "umulh z0.d, p7/m, z0.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0.d, p7/z, z7.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x1f, 0xd3, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "umulh z0.d, p7/m, z0.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x1f, 0xd3, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "umulh z0.d, p7/m, z0.d, z31.d"
diff --git a/tests/MC/AArch64/SVE/uqadd.s.yaml b/tests/MC/AArch64/SVE/uqadd.s.yaml
new file mode 100644
index 000000000..50a6f664b
--- /dev/null
+++ b/tests/MC/AArch64/SVE/uqadd.s.yaml
@@ -0,0 +1,400 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x14, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqadd z0.b, z0.b, z0.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x14, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqadd z0.h, z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x14, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqadd z0.s, z0.s, z0.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0x14, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqadd z0.d, z0.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x25, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqadd z0.b, z0.b, #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0xdf, 0x25, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqadd z31.b, z31.b, #255"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x65, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqadd z0.h, z0.h, #0"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x65, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqadd z0.h, z0.h, #0, lsl #8"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0x65, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqadd z31.h, z31.h, #65280"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0x65, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqadd z31.h, z31.h, #65280"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0xa5, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqadd z0.s, z0.s, #0"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xa5, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqadd z0.s, z0.s, #0, lsl #8"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xa5, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqadd z31.s, z31.s, #65280"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xa5, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqadd z31.s, z31.s, #65280"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0xe5, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqadd z0.d, z0.d, #0"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xe5, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqadd z0.d, z0.d, #0, lsl #8"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xe5, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqadd z31.d, z31.d, #65280"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xe5, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqadd z31.d, z31.d, #65280"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xe5, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqadd z31.d, z31.d, #65280"
+
+  -
+    input:
+      bytes: [ 0x00, 0x14, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqadd z0.b, z0.b, z0.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x14, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqadd z0.h, z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x14, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqadd z0.s, z0.s, z0.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0x14, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqadd z0.d, z0.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x25, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqadd z0.b, z0.b, #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0xdf, 0x25, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqadd z31.b, z31.b, #255"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x65, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqadd z0.h, z0.h, #0"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x65, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqadd z0.h, z0.h, #0, lsl #8"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0x65, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqadd z31.h, z31.h, #65280"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0x65, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqadd z31.h, z31.h, #65280"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0xa5, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqadd z0.s, z0.s, #0"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xa5, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqadd z0.s, z0.s, #0, lsl #8"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xa5, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqadd z31.s, z31.s, #65280"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xa5, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqadd z31.s, z31.s, #65280"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0xe5, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqadd z0.d, z0.d, #0"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xe5, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqadd z0.d, z0.d, #0, lsl #8"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xe5, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqadd z31.d, z31.d, #65280"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xe5, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqadd z31.d, z31.d, #65280"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xe5, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqadd z31.d, z31.d, #65280"
diff --git a/tests/MC/AArch64/SVE/uqdecb.s.yaml b/tests/MC/AArch64/SVE/uqdecb.s.yaml
new file mode 100644
index 000000000..d6e6fec07
--- /dev/null
+++ b/tests/MC/AArch64/SVE/uqdecb.s.yaml
@@ -0,0 +1,780 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xe0, 0xff, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecb x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xff, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecb x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xff, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecb x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xff, 0x3f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecb x0, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xff, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecb w0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xff, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecb w0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xff, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecb w0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xff, 0x2f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecb w0, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xfc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecb w0, pow2"
+
+  -
+    input:
+      bytes: [ 0x00, 0xfc, 0x2f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecb w0, pow2, mul #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xfc, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecb x0, pow2"
+
+  -
+    input:
+      bytes: [ 0x20, 0xfc, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecb x0, vl1"
+
+  -
+    input:
+      bytes: [ 0x40, 0xfc, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecb x0, vl2"
+
+  -
+    input:
+      bytes: [ 0x60, 0xfc, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecb x0, vl3"
+
+  -
+    input:
+      bytes: [ 0x80, 0xfc, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecb x0, vl4"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xfc, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecb x0, vl5"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xfc, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecb x0, vl6"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xfc, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecb x0, vl7"
+
+  -
+    input:
+      bytes: [ 0x00, 0xfd, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecb x0, vl8"
+
+  -
+    input:
+      bytes: [ 0x20, 0xfd, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecb x0, vl16"
+
+  -
+    input:
+      bytes: [ 0x40, 0xfd, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecb x0, vl32"
+
+  -
+    input:
+      bytes: [ 0x60, 0xfd, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecb x0, vl64"
+
+  -
+    input:
+      bytes: [ 0x80, 0xfd, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecb x0, vl128"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xfd, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecb x0, vl256"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xfd, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecb x0, #14"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xfd, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecb x0, #15"
+
+  -
+    input:
+      bytes: [ 0x00, 0xfe, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecb x0, #16"
+
+  -
+    input:
+      bytes: [ 0x20, 0xfe, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecb x0, #17"
+
+  -
+    input:
+      bytes: [ 0x40, 0xfe, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecb x0, #18"
+
+  -
+    input:
+      bytes: [ 0x60, 0xfe, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecb x0, #19"
+
+  -
+    input:
+      bytes: [ 0x80, 0xfe, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecb x0, #20"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xfe, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecb x0, #21"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xfe, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecb x0, #22"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xfe, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecb x0, #23"
+
+  -
+    input:
+      bytes: [ 0x00, 0xff, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecb x0, #24"
+
+  -
+    input:
+      bytes: [ 0x20, 0xff, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecb x0, #25"
+
+  -
+    input:
+      bytes: [ 0x40, 0xff, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecb x0, #26"
+
+  -
+    input:
+      bytes: [ 0x60, 0xff, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecb x0, #27"
+
+  -
+    input:
+      bytes: [ 0x80, 0xff, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecb x0, #28"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xff, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecb x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xff, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecb x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xff, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecb x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xff, 0x3f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecb x0, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xff, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecb w0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xff, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecb w0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xff, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecb w0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xff, 0x2f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecb w0, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xfc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecb w0, pow2"
+
+  -
+    input:
+      bytes: [ 0x00, 0xfc, 0x2f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecb w0, pow2, mul #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xfc, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecb x0, pow2"
+
+  -
+    input:
+      bytes: [ 0x20, 0xfc, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecb x0, vl1"
+
+  -
+    input:
+      bytes: [ 0x40, 0xfc, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecb x0, vl2"
+
+  -
+    input:
+      bytes: [ 0x60, 0xfc, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecb x0, vl3"
+
+  -
+    input:
+      bytes: [ 0x80, 0xfc, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecb x0, vl4"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xfc, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecb x0, vl5"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xfc, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecb x0, vl6"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xfc, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecb x0, vl7"
+
+  -
+    input:
+      bytes: [ 0x00, 0xfd, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecb x0, vl8"
+
+  -
+    input:
+      bytes: [ 0x20, 0xfd, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecb x0, vl16"
+
+  -
+    input:
+      bytes: [ 0x40, 0xfd, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecb x0, vl32"
+
+  -
+    input:
+      bytes: [ 0x60, 0xfd, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecb x0, vl64"
+
+  -
+    input:
+      bytes: [ 0x80, 0xfd, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecb x0, vl128"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xfd, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecb x0, vl256"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xfd, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecb x0, #14"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xfd, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecb x0, #15"
+
+  -
+    input:
+      bytes: [ 0x00, 0xfe, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecb x0, #16"
+
+  -
+    input:
+      bytes: [ 0x20, 0xfe, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecb x0, #17"
+
+  -
+    input:
+      bytes: [ 0x40, 0xfe, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecb x0, #18"
+
+  -
+    input:
+      bytes: [ 0x60, 0xfe, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecb x0, #19"
+
+  -
+    input:
+      bytes: [ 0x80, 0xfe, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecb x0, #20"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xfe, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecb x0, #21"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xfe, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecb x0, #22"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xfe, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecb x0, #23"
+
+  -
+    input:
+      bytes: [ 0x00, 0xff, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecb x0, #24"
+
+  -
+    input:
+      bytes: [ 0x20, 0xff, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecb x0, #25"
+
+  -
+    input:
+      bytes: [ 0x40, 0xff, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecb x0, #26"
+
+  -
+    input:
+      bytes: [ 0x60, 0xff, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecb x0, #27"
+
+  -
+    input:
+      bytes: [ 0x80, 0xff, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecb x0, #28"
diff --git a/tests/MC/AArch64/SVE/uqdecd.s.yaml b/tests/MC/AArch64/SVE/uqdecd.s.yaml
new file mode 100644
index 000000000..22acaf0d6
--- /dev/null
+++ b/tests/MC/AArch64/SVE/uqdecd.s.yaml
@@ -0,0 +1,1020 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xe0, 0xff, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecd x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xff, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecd x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xff, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecd x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xff, 0xff, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecd x0, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xff, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecd w0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xff, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecd w0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xff, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecd w0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xff, 0xef, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecd w0, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xfc, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecd w0, pow2"
+
+  -
+    input:
+      bytes: [ 0x00, 0xfc, 0xef, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecd w0, pow2, mul #16"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xcf, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecd z0.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xcf, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecd z0.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xcf, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecd z0.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xcf, 0xef, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecd z0.d, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xcc, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecd z0.d, pow2"
+
+  -
+    input:
+      bytes: [ 0x00, 0xcc, 0xef, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecd z0.d, pow2, mul #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xfc, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecd x0, pow2"
+
+  -
+    input:
+      bytes: [ 0x20, 0xfc, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecd x0, vl1"
+
+  -
+    input:
+      bytes: [ 0x40, 0xfc, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecd x0, vl2"
+
+  -
+    input:
+      bytes: [ 0x60, 0xfc, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecd x0, vl3"
+
+  -
+    input:
+      bytes: [ 0x80, 0xfc, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecd x0, vl4"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xfc, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecd x0, vl5"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xfc, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecd x0, vl6"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xfc, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecd x0, vl7"
+
+  -
+    input:
+      bytes: [ 0x00, 0xfd, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecd x0, vl8"
+
+  -
+    input:
+      bytes: [ 0x20, 0xfd, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecd x0, vl16"
+
+  -
+    input:
+      bytes: [ 0x40, 0xfd, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecd x0, vl32"
+
+  -
+    input:
+      bytes: [ 0x60, 0xfd, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecd x0, vl64"
+
+  -
+    input:
+      bytes: [ 0x80, 0xfd, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecd x0, vl128"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xfd, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecd x0, vl256"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xfd, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecd x0, #14"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xfd, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecd x0, #15"
+
+  -
+    input:
+      bytes: [ 0x00, 0xfe, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecd x0, #16"
+
+  -
+    input:
+      bytes: [ 0x20, 0xfe, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecd x0, #17"
+
+  -
+    input:
+      bytes: [ 0x40, 0xfe, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecd x0, #18"
+
+  -
+    input:
+      bytes: [ 0x60, 0xfe, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecd x0, #19"
+
+  -
+    input:
+      bytes: [ 0x80, 0xfe, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecd x0, #20"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xfe, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecd x0, #21"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xfe, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecd x0, #22"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xfe, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecd x0, #23"
+
+  -
+    input:
+      bytes: [ 0x00, 0xff, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecd x0, #24"
+
+  -
+    input:
+      bytes: [ 0x20, 0xff, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecd x0, #25"
+
+  -
+    input:
+      bytes: [ 0x40, 0xff, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecd x0, #26"
+
+  -
+    input:
+      bytes: [ 0x60, 0xff, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecd x0, #27"
+
+  -
+    input:
+      bytes: [ 0x80, 0xff, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecd x0, #28"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xcf, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecd z0.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x00, 0xcc, 0xef, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecd z0.d, pow2, mul #16"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x00, 0xcc, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecd z0.d, pow2"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xff, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecd x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xff, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecd x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xff, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecd x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xff, 0xff, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecd x0, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xff, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecd w0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xff, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecd w0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xff, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecd w0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xff, 0xef, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecd w0, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xfc, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecd w0, pow2"
+
+  -
+    input:
+      bytes: [ 0x00, 0xfc, 0xef, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecd w0, pow2, mul #16"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xcf, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecd z0.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xcf, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecd z0.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xcf, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecd z0.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xcf, 0xef, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecd z0.d, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xcc, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecd z0.d, pow2"
+
+  -
+    input:
+      bytes: [ 0x00, 0xcc, 0xef, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecd z0.d, pow2, mul #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xfc, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecd x0, pow2"
+
+  -
+    input:
+      bytes: [ 0x20, 0xfc, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecd x0, vl1"
+
+  -
+    input:
+      bytes: [ 0x40, 0xfc, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecd x0, vl2"
+
+  -
+    input:
+      bytes: [ 0x60, 0xfc, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecd x0, vl3"
+
+  -
+    input:
+      bytes: [ 0x80, 0xfc, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecd x0, vl4"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xfc, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecd x0, vl5"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xfc, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecd x0, vl6"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xfc, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecd x0, vl7"
+
+  -
+    input:
+      bytes: [ 0x00, 0xfd, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecd x0, vl8"
+
+  -
+    input:
+      bytes: [ 0x20, 0xfd, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecd x0, vl16"
+
+  -
+    input:
+      bytes: [ 0x40, 0xfd, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecd x0, vl32"
+
+  -
+    input:
+      bytes: [ 0x60, 0xfd, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecd x0, vl64"
+
+  -
+    input:
+      bytes: [ 0x80, 0xfd, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecd x0, vl128"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xfd, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecd x0, vl256"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xfd, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecd x0, #14"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xfd, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecd x0, #15"
+
+  -
+    input:
+      bytes: [ 0x00, 0xfe, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecd x0, #16"
+
+  -
+    input:
+      bytes: [ 0x20, 0xfe, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecd x0, #17"
+
+  -
+    input:
+      bytes: [ 0x40, 0xfe, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecd x0, #18"
+
+  -
+    input:
+      bytes: [ 0x60, 0xfe, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecd x0, #19"
+
+  -
+    input:
+      bytes: [ 0x80, 0xfe, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecd x0, #20"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xfe, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecd x0, #21"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xfe, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecd x0, #22"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xfe, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecd x0, #23"
+
+  -
+    input:
+      bytes: [ 0x00, 0xff, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecd x0, #24"
+
+  -
+    input:
+      bytes: [ 0x20, 0xff, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecd x0, #25"
+
+  -
+    input:
+      bytes: [ 0x40, 0xff, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecd x0, #26"
+
+  -
+    input:
+      bytes: [ 0x60, 0xff, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecd x0, #27"
+
+  -
+    input:
+      bytes: [ 0x80, 0xff, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecd x0, #28"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xcf, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecd z0.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x00, 0xcc, 0xef, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecd z0.d, pow2, mul #16"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x00, 0xcc, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecd z0.d, pow2"
diff --git a/tests/MC/AArch64/SVE/uqdech.s.yaml b/tests/MC/AArch64/SVE/uqdech.s.yaml
new file mode 100644
index 000000000..90fcd31b4
--- /dev/null
+++ b/tests/MC/AArch64/SVE/uqdech.s.yaml
@@ -0,0 +1,1020 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xe0, 0xff, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdech x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xff, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdech x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xff, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdech x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xff, 0x7f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdech x0, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xff, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdech w0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xff, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdech w0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xff, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdech w0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xff, 0x6f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdech w0, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xfc, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdech w0, pow2"
+
+  -
+    input:
+      bytes: [ 0x00, 0xfc, 0x6f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdech w0, pow2, mul #16"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xcf, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdech z0.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xcf, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdech z0.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xcf, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdech z0.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xcf, 0x6f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdech z0.h, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xcc, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdech z0.h, pow2"
+
+  -
+    input:
+      bytes: [ 0x00, 0xcc, 0x6f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdech z0.h, pow2, mul #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xfc, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdech x0, pow2"
+
+  -
+    input:
+      bytes: [ 0x20, 0xfc, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdech x0, vl1"
+
+  -
+    input:
+      bytes: [ 0x40, 0xfc, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdech x0, vl2"
+
+  -
+    input:
+      bytes: [ 0x60, 0xfc, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdech x0, vl3"
+
+  -
+    input:
+      bytes: [ 0x80, 0xfc, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdech x0, vl4"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xfc, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdech x0, vl5"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xfc, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdech x0, vl6"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xfc, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdech x0, vl7"
+
+  -
+    input:
+      bytes: [ 0x00, 0xfd, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdech x0, vl8"
+
+  -
+    input:
+      bytes: [ 0x20, 0xfd, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdech x0, vl16"
+
+  -
+    input:
+      bytes: [ 0x40, 0xfd, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdech x0, vl32"
+
+  -
+    input:
+      bytes: [ 0x60, 0xfd, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdech x0, vl64"
+
+  -
+    input:
+      bytes: [ 0x80, 0xfd, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdech x0, vl128"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xfd, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdech x0, vl256"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xfd, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdech x0, #14"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xfd, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdech x0, #15"
+
+  -
+    input:
+      bytes: [ 0x00, 0xfe, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdech x0, #16"
+
+  -
+    input:
+      bytes: [ 0x20, 0xfe, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdech x0, #17"
+
+  -
+    input:
+      bytes: [ 0x40, 0xfe, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdech x0, #18"
+
+  -
+    input:
+      bytes: [ 0x60, 0xfe, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdech x0, #19"
+
+  -
+    input:
+      bytes: [ 0x80, 0xfe, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdech x0, #20"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xfe, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdech x0, #21"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xfe, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdech x0, #22"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xfe, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdech x0, #23"
+
+  -
+    input:
+      bytes: [ 0x00, 0xff, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdech x0, #24"
+
+  -
+    input:
+      bytes: [ 0x20, 0xff, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdech x0, #25"
+
+  -
+    input:
+      bytes: [ 0x40, 0xff, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdech x0, #26"
+
+  -
+    input:
+      bytes: [ 0x60, 0xff, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdech x0, #27"
+
+  -
+    input:
+      bytes: [ 0x80, 0xff, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdech x0, #28"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xcf, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdech z0.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x00, 0xcc, 0x6f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdech z0.h, pow2, mul #16"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x00, 0xcc, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdech z0.h, pow2"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xff, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdech x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xff, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdech x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xff, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdech x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xff, 0x7f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdech x0, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xff, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdech w0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xff, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdech w0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xff, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdech w0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xff, 0x6f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdech w0, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xfc, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdech w0, pow2"
+
+  -
+    input:
+      bytes: [ 0x00, 0xfc, 0x6f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdech w0, pow2, mul #16"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xcf, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdech z0.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xcf, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdech z0.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xcf, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdech z0.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xcf, 0x6f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdech z0.h, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xcc, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdech z0.h, pow2"
+
+  -
+    input:
+      bytes: [ 0x00, 0xcc, 0x6f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdech z0.h, pow2, mul #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xfc, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdech x0, pow2"
+
+  -
+    input:
+      bytes: [ 0x20, 0xfc, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdech x0, vl1"
+
+  -
+    input:
+      bytes: [ 0x40, 0xfc, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdech x0, vl2"
+
+  -
+    input:
+      bytes: [ 0x60, 0xfc, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdech x0, vl3"
+
+  -
+    input:
+      bytes: [ 0x80, 0xfc, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdech x0, vl4"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xfc, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdech x0, vl5"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xfc, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdech x0, vl6"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xfc, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdech x0, vl7"
+
+  -
+    input:
+      bytes: [ 0x00, 0xfd, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdech x0, vl8"
+
+  -
+    input:
+      bytes: [ 0x20, 0xfd, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdech x0, vl16"
+
+  -
+    input:
+      bytes: [ 0x40, 0xfd, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdech x0, vl32"
+
+  -
+    input:
+      bytes: [ 0x60, 0xfd, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdech x0, vl64"
+
+  -
+    input:
+      bytes: [ 0x80, 0xfd, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdech x0, vl128"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xfd, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdech x0, vl256"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xfd, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdech x0, #14"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xfd, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdech x0, #15"
+
+  -
+    input:
+      bytes: [ 0x00, 0xfe, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdech x0, #16"
+
+  -
+    input:
+      bytes: [ 0x20, 0xfe, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdech x0, #17"
+
+  -
+    input:
+      bytes: [ 0x40, 0xfe, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdech x0, #18"
+
+  -
+    input:
+      bytes: [ 0x60, 0xfe, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdech x0, #19"
+
+  -
+    input:
+      bytes: [ 0x80, 0xfe, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdech x0, #20"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xfe, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdech x0, #21"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xfe, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdech x0, #22"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xfe, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdech x0, #23"
+
+  -
+    input:
+      bytes: [ 0x00, 0xff, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdech x0, #24"
+
+  -
+    input:
+      bytes: [ 0x20, 0xff, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdech x0, #25"
+
+  -
+    input:
+      bytes: [ 0x40, 0xff, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdech x0, #26"
+
+  -
+    input:
+      bytes: [ 0x60, 0xff, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdech x0, #27"
+
+  -
+    input:
+      bytes: [ 0x80, 0xff, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdech x0, #28"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xcf, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdech z0.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x00, 0xcc, 0x6f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdech z0.h, pow2, mul #16"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x00, 0xcc, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdech z0.h, pow2"
diff --git a/tests/MC/AArch64/SVE/uqdecp.s.yaml b/tests/MC/AArch64/SVE/uqdecp.s.yaml
new file mode 100644
index 000000000..ab0c7c88d
--- /dev/null
+++ b/tests/MC/AArch64/SVE/uqdecp.s.yaml
@@ -0,0 +1,320 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x8c, 0x2b, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecp x0, p0.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x8c, 0x6b, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecp x0, p0.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x8c, 0xab, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecp x0, p0.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0x8c, 0xeb, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecp x0, p0.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0x89, 0x2b, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecp wzr, p15.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x89, 0x6b, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecp wzr, p15.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x89, 0xab, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecp wzr, p15.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0x89, 0xeb, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecp wzr, p15.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x6b, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecp z0.h, p0.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x6b, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecp z0.h, p0.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xab, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecp z0.s, p0.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xab, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecp z0.s, p0.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xeb, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecp z0.d, p0.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xeb, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecp z0.d, p0.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xeb, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecp z0.d, p0.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x8c, 0x2b, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecp x0, p0.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x8c, 0x6b, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecp x0, p0.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x8c, 0xab, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecp x0, p0.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0x8c, 0xeb, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecp x0, p0.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0x89, 0x2b, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecp wzr, p15.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x89, 0x6b, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecp wzr, p15.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x89, 0xab, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecp wzr, p15.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0x89, 0xeb, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecp wzr, p15.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x6b, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecp z0.h, p0.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x6b, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecp z0.h, p0.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xab, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecp z0.s, p0.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xab, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecp z0.s, p0.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xeb, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecp z0.d, p0.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xeb, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecp z0.d, p0.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xeb, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecp z0.d, p0.d"
diff --git a/tests/MC/AArch64/SVE/uqdecw.s.yaml b/tests/MC/AArch64/SVE/uqdecw.s.yaml
new file mode 100644
index 000000000..c8e9b6c01
--- /dev/null
+++ b/tests/MC/AArch64/SVE/uqdecw.s.yaml
@@ -0,0 +1,1020 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xe0, 0xff, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecw x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xff, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecw x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xff, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecw x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xff, 0xbf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecw x0, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xff, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecw w0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xff, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecw w0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xff, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecw w0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xff, 0xaf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecw w0, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xfc, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecw w0, pow2"
+
+  -
+    input:
+      bytes: [ 0x00, 0xfc, 0xaf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecw w0, pow2, mul #16"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xcf, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecw z0.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xcf, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecw z0.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xcf, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecw z0.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xcf, 0xaf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecw z0.s, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xcc, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecw z0.s, pow2"
+
+  -
+    input:
+      bytes: [ 0x00, 0xcc, 0xaf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecw z0.s, pow2, mul #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xfc, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecw x0, pow2"
+
+  -
+    input:
+      bytes: [ 0x20, 0xfc, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecw x0, vl1"
+
+  -
+    input:
+      bytes: [ 0x40, 0xfc, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecw x0, vl2"
+
+  -
+    input:
+      bytes: [ 0x60, 0xfc, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecw x0, vl3"
+
+  -
+    input:
+      bytes: [ 0x80, 0xfc, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecw x0, vl4"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xfc, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecw x0, vl5"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xfc, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecw x0, vl6"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xfc, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecw x0, vl7"
+
+  -
+    input:
+      bytes: [ 0x00, 0xfd, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecw x0, vl8"
+
+  -
+    input:
+      bytes: [ 0x20, 0xfd, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecw x0, vl16"
+
+  -
+    input:
+      bytes: [ 0x40, 0xfd, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecw x0, vl32"
+
+  -
+    input:
+      bytes: [ 0x60, 0xfd, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecw x0, vl64"
+
+  -
+    input:
+      bytes: [ 0x80, 0xfd, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecw x0, vl128"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xfd, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecw x0, vl256"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xfd, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecw x0, #14"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xfd, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecw x0, #15"
+
+  -
+    input:
+      bytes: [ 0x00, 0xfe, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecw x0, #16"
+
+  -
+    input:
+      bytes: [ 0x20, 0xfe, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecw x0, #17"
+
+  -
+    input:
+      bytes: [ 0x40, 0xfe, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecw x0, #18"
+
+  -
+    input:
+      bytes: [ 0x60, 0xfe, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecw x0, #19"
+
+  -
+    input:
+      bytes: [ 0x80, 0xfe, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecw x0, #20"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xfe, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecw x0, #21"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xfe, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecw x0, #22"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xfe, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecw x0, #23"
+
+  -
+    input:
+      bytes: [ 0x00, 0xff, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecw x0, #24"
+
+  -
+    input:
+      bytes: [ 0x20, 0xff, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecw x0, #25"
+
+  -
+    input:
+      bytes: [ 0x40, 0xff, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecw x0, #26"
+
+  -
+    input:
+      bytes: [ 0x60, 0xff, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecw x0, #27"
+
+  -
+    input:
+      bytes: [ 0x80, 0xff, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecw x0, #28"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xcf, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecw z0.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x00, 0xcc, 0xaf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecw z0.s, pow2, mul #16"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x00, 0xcc, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecw z0.s, pow2"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xff, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecw x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xff, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecw x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xff, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecw x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xff, 0xbf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecw x0, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xff, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecw w0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xff, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecw w0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xff, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecw w0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xff, 0xaf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecw w0, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xfc, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecw w0, pow2"
+
+  -
+    input:
+      bytes: [ 0x00, 0xfc, 0xaf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecw w0, pow2, mul #16"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xcf, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecw z0.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xcf, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecw z0.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xcf, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecw z0.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xcf, 0xaf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecw z0.s, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xcc, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecw z0.s, pow2"
+
+  -
+    input:
+      bytes: [ 0x00, 0xcc, 0xaf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecw z0.s, pow2, mul #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xfc, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecw x0, pow2"
+
+  -
+    input:
+      bytes: [ 0x20, 0xfc, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecw x0, vl1"
+
+  -
+    input:
+      bytes: [ 0x40, 0xfc, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecw x0, vl2"
+
+  -
+    input:
+      bytes: [ 0x60, 0xfc, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecw x0, vl3"
+
+  -
+    input:
+      bytes: [ 0x80, 0xfc, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecw x0, vl4"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xfc, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecw x0, vl5"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xfc, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecw x0, vl6"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xfc, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecw x0, vl7"
+
+  -
+    input:
+      bytes: [ 0x00, 0xfd, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecw x0, vl8"
+
+  -
+    input:
+      bytes: [ 0x20, 0xfd, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecw x0, vl16"
+
+  -
+    input:
+      bytes: [ 0x40, 0xfd, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecw x0, vl32"
+
+  -
+    input:
+      bytes: [ 0x60, 0xfd, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecw x0, vl64"
+
+  -
+    input:
+      bytes: [ 0x80, 0xfd, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecw x0, vl128"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xfd, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecw x0, vl256"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xfd, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecw x0, #14"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xfd, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecw x0, #15"
+
+  -
+    input:
+      bytes: [ 0x00, 0xfe, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecw x0, #16"
+
+  -
+    input:
+      bytes: [ 0x20, 0xfe, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecw x0, #17"
+
+  -
+    input:
+      bytes: [ 0x40, 0xfe, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecw x0, #18"
+
+  -
+    input:
+      bytes: [ 0x60, 0xfe, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecw x0, #19"
+
+  -
+    input:
+      bytes: [ 0x80, 0xfe, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecw x0, #20"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xfe, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecw x0, #21"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xfe, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecw x0, #22"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xfe, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecw x0, #23"
+
+  -
+    input:
+      bytes: [ 0x00, 0xff, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecw x0, #24"
+
+  -
+    input:
+      bytes: [ 0x20, 0xff, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecw x0, #25"
+
+  -
+    input:
+      bytes: [ 0x40, 0xff, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecw x0, #26"
+
+  -
+    input:
+      bytes: [ 0x60, 0xff, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecw x0, #27"
+
+  -
+    input:
+      bytes: [ 0x80, 0xff, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecw x0, #28"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xcf, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecw z0.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x00, 0xcc, 0xaf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecw z0.s, pow2, mul #16"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x00, 0xcc, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqdecw z0.s, pow2"
diff --git a/tests/MC/AArch64/SVE/uqincb.s.yaml b/tests/MC/AArch64/SVE/uqincb.s.yaml
new file mode 100644
index 000000000..0bdab165f
--- /dev/null
+++ b/tests/MC/AArch64/SVE/uqincb.s.yaml
@@ -0,0 +1,780 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xe0, 0xf7, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincb x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf7, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincb x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf7, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincb x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf7, 0x3f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincb x0, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf7, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincb w0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf7, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincb w0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf7, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincb w0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf7, 0x2f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincb w0, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf4, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincb w0, pow2"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf4, 0x2f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincb w0, pow2, mul #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf4, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincb x0, pow2"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf4, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincb x0, vl1"
+
+  -
+    input:
+      bytes: [ 0x40, 0xf4, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincb x0, vl2"
+
+  -
+    input:
+      bytes: [ 0x60, 0xf4, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincb x0, vl3"
+
+  -
+    input:
+      bytes: [ 0x80, 0xf4, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincb x0, vl4"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xf4, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincb x0, vl5"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xf4, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincb x0, vl6"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf4, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincb x0, vl7"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf5, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincb x0, vl8"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf5, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincb x0, vl16"
+
+  -
+    input:
+      bytes: [ 0x40, 0xf5, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincb x0, vl32"
+
+  -
+    input:
+      bytes: [ 0x60, 0xf5, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincb x0, vl64"
+
+  -
+    input:
+      bytes: [ 0x80, 0xf5, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincb x0, vl128"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xf5, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincb x0, vl256"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xf5, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincb x0, #14"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf5, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincb x0, #15"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf6, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincb x0, #16"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf6, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincb x0, #17"
+
+  -
+    input:
+      bytes: [ 0x40, 0xf6, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincb x0, #18"
+
+  -
+    input:
+      bytes: [ 0x60, 0xf6, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincb x0, #19"
+
+  -
+    input:
+      bytes: [ 0x80, 0xf6, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincb x0, #20"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xf6, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincb x0, #21"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xf6, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincb x0, #22"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf6, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincb x0, #23"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf7, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincb x0, #24"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf7, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincb x0, #25"
+
+  -
+    input:
+      bytes: [ 0x40, 0xf7, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincb x0, #26"
+
+  -
+    input:
+      bytes: [ 0x60, 0xf7, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincb x0, #27"
+
+  -
+    input:
+      bytes: [ 0x80, 0xf7, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincb x0, #28"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf7, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincb x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf7, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincb x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf7, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincb x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf7, 0x3f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincb x0, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf7, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincb w0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf7, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincb w0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf7, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincb w0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf7, 0x2f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincb w0, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf4, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincb w0, pow2"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf4, 0x2f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincb w0, pow2, mul #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf4, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincb x0, pow2"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf4, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincb x0, vl1"
+
+  -
+    input:
+      bytes: [ 0x40, 0xf4, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincb x0, vl2"
+
+  -
+    input:
+      bytes: [ 0x60, 0xf4, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincb x0, vl3"
+
+  -
+    input:
+      bytes: [ 0x80, 0xf4, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincb x0, vl4"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xf4, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincb x0, vl5"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xf4, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincb x0, vl6"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf4, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincb x0, vl7"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf5, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincb x0, vl8"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf5, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincb x0, vl16"
+
+  -
+    input:
+      bytes: [ 0x40, 0xf5, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincb x0, vl32"
+
+  -
+    input:
+      bytes: [ 0x60, 0xf5, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincb x0, vl64"
+
+  -
+    input:
+      bytes: [ 0x80, 0xf5, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincb x0, vl128"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xf5, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincb x0, vl256"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xf5, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincb x0, #14"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf5, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincb x0, #15"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf6, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincb x0, #16"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf6, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincb x0, #17"
+
+  -
+    input:
+      bytes: [ 0x40, 0xf6, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincb x0, #18"
+
+  -
+    input:
+      bytes: [ 0x60, 0xf6, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincb x0, #19"
+
+  -
+    input:
+      bytes: [ 0x80, 0xf6, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincb x0, #20"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xf6, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincb x0, #21"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xf6, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincb x0, #22"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf6, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincb x0, #23"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf7, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincb x0, #24"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf7, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincb x0, #25"
+
+  -
+    input:
+      bytes: [ 0x40, 0xf7, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincb x0, #26"
+
+  -
+    input:
+      bytes: [ 0x60, 0xf7, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincb x0, #27"
+
+  -
+    input:
+      bytes: [ 0x80, 0xf7, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincb x0, #28"
diff --git a/tests/MC/AArch64/SVE/uqincd.s.yaml b/tests/MC/AArch64/SVE/uqincd.s.yaml
new file mode 100644
index 000000000..dc0c7cc9e
--- /dev/null
+++ b/tests/MC/AArch64/SVE/uqincd.s.yaml
@@ -0,0 +1,1020 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xe0, 0xf7, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincd x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf7, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincd x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf7, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincd x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf7, 0xff, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincd x0, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf7, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincd w0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf7, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincd w0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf7, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincd w0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf7, 0xef, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincd w0, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf4, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincd w0, pow2"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf4, 0xef, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincd w0, pow2, mul #16"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc7, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincd z0.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc7, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincd z0.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc7, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincd z0.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc7, 0xef, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincd z0.d, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc4, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincd z0.d, pow2"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc4, 0xef, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincd z0.d, pow2, mul #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf4, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincd x0, pow2"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf4, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincd x0, vl1"
+
+  -
+    input:
+      bytes: [ 0x40, 0xf4, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincd x0, vl2"
+
+  -
+    input:
+      bytes: [ 0x60, 0xf4, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincd x0, vl3"
+
+  -
+    input:
+      bytes: [ 0x80, 0xf4, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincd x0, vl4"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xf4, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincd x0, vl5"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xf4, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincd x0, vl6"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf4, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincd x0, vl7"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf5, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincd x0, vl8"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf5, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincd x0, vl16"
+
+  -
+    input:
+      bytes: [ 0x40, 0xf5, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincd x0, vl32"
+
+  -
+    input:
+      bytes: [ 0x60, 0xf5, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincd x0, vl64"
+
+  -
+    input:
+      bytes: [ 0x80, 0xf5, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincd x0, vl128"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xf5, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincd x0, vl256"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xf5, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincd x0, #14"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf5, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincd x0, #15"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf6, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincd x0, #16"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf6, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincd x0, #17"
+
+  -
+    input:
+      bytes: [ 0x40, 0xf6, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincd x0, #18"
+
+  -
+    input:
+      bytes: [ 0x60, 0xf6, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincd x0, #19"
+
+  -
+    input:
+      bytes: [ 0x80, 0xf6, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincd x0, #20"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xf6, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincd x0, #21"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xf6, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincd x0, #22"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf6, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincd x0, #23"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf7, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincd x0, #24"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf7, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincd x0, #25"
+
+  -
+    input:
+      bytes: [ 0x40, 0xf7, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincd x0, #26"
+
+  -
+    input:
+      bytes: [ 0x60, 0xf7, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincd x0, #27"
+
+  -
+    input:
+      bytes: [ 0x80, 0xf7, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincd x0, #28"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc7, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincd z0.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc4, 0xef, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincd z0.d, pow2, mul #16"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc4, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincd z0.d, pow2"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf7, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincd x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf7, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincd x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf7, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincd x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf7, 0xff, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincd x0, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf7, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincd w0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf7, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincd w0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf7, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincd w0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf7, 0xef, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincd w0, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf4, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincd w0, pow2"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf4, 0xef, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincd w0, pow2, mul #16"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc7, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincd z0.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc7, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincd z0.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc7, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincd z0.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc7, 0xef, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincd z0.d, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc4, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincd z0.d, pow2"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc4, 0xef, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincd z0.d, pow2, mul #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf4, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincd x0, pow2"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf4, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincd x0, vl1"
+
+  -
+    input:
+      bytes: [ 0x40, 0xf4, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincd x0, vl2"
+
+  -
+    input:
+      bytes: [ 0x60, 0xf4, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincd x0, vl3"
+
+  -
+    input:
+      bytes: [ 0x80, 0xf4, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincd x0, vl4"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xf4, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincd x0, vl5"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xf4, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincd x0, vl6"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf4, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincd x0, vl7"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf5, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincd x0, vl8"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf5, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincd x0, vl16"
+
+  -
+    input:
+      bytes: [ 0x40, 0xf5, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincd x0, vl32"
+
+  -
+    input:
+      bytes: [ 0x60, 0xf5, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincd x0, vl64"
+
+  -
+    input:
+      bytes: [ 0x80, 0xf5, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincd x0, vl128"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xf5, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincd x0, vl256"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xf5, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincd x0, #14"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf5, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincd x0, #15"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf6, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincd x0, #16"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf6, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincd x0, #17"
+
+  -
+    input:
+      bytes: [ 0x40, 0xf6, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincd x0, #18"
+
+  -
+    input:
+      bytes: [ 0x60, 0xf6, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincd x0, #19"
+
+  -
+    input:
+      bytes: [ 0x80, 0xf6, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincd x0, #20"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xf6, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincd x0, #21"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xf6, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincd x0, #22"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf6, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincd x0, #23"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf7, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincd x0, #24"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf7, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincd x0, #25"
+
+  -
+    input:
+      bytes: [ 0x40, 0xf7, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincd x0, #26"
+
+  -
+    input:
+      bytes: [ 0x60, 0xf7, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincd x0, #27"
+
+  -
+    input:
+      bytes: [ 0x80, 0xf7, 0xf0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincd x0, #28"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc7, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincd z0.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc4, 0xef, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincd z0.d, pow2, mul #16"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc4, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincd z0.d, pow2"
diff --git a/tests/MC/AArch64/SVE/uqinch.s.yaml b/tests/MC/AArch64/SVE/uqinch.s.yaml
new file mode 100644
index 000000000..8a243e472
--- /dev/null
+++ b/tests/MC/AArch64/SVE/uqinch.s.yaml
@@ -0,0 +1,1020 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xe0, 0xf7, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqinch x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf7, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqinch x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf7, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqinch x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf7, 0x7f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqinch x0, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf7, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqinch w0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf7, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqinch w0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf7, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqinch w0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf7, 0x6f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqinch w0, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf4, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqinch w0, pow2"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf4, 0x6f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqinch w0, pow2, mul #16"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc7, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqinch z0.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc7, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqinch z0.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc7, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqinch z0.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc7, 0x6f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqinch z0.h, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc4, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqinch z0.h, pow2"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc4, 0x6f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqinch z0.h, pow2, mul #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf4, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqinch x0, pow2"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf4, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqinch x0, vl1"
+
+  -
+    input:
+      bytes: [ 0x40, 0xf4, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqinch x0, vl2"
+
+  -
+    input:
+      bytes: [ 0x60, 0xf4, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqinch x0, vl3"
+
+  -
+    input:
+      bytes: [ 0x80, 0xf4, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqinch x0, vl4"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xf4, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqinch x0, vl5"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xf4, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqinch x0, vl6"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf4, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqinch x0, vl7"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf5, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqinch x0, vl8"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf5, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqinch x0, vl16"
+
+  -
+    input:
+      bytes: [ 0x40, 0xf5, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqinch x0, vl32"
+
+  -
+    input:
+      bytes: [ 0x60, 0xf5, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqinch x0, vl64"
+
+  -
+    input:
+      bytes: [ 0x80, 0xf5, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqinch x0, vl128"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xf5, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqinch x0, vl256"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xf5, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqinch x0, #14"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf5, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqinch x0, #15"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf6, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqinch x0, #16"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf6, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqinch x0, #17"
+
+  -
+    input:
+      bytes: [ 0x40, 0xf6, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqinch x0, #18"
+
+  -
+    input:
+      bytes: [ 0x60, 0xf6, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqinch x0, #19"
+
+  -
+    input:
+      bytes: [ 0x80, 0xf6, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqinch x0, #20"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xf6, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqinch x0, #21"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xf6, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqinch x0, #22"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf6, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqinch x0, #23"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf7, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqinch x0, #24"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf7, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqinch x0, #25"
+
+  -
+    input:
+      bytes: [ 0x40, 0xf7, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqinch x0, #26"
+
+  -
+    input:
+      bytes: [ 0x60, 0xf7, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqinch x0, #27"
+
+  -
+    input:
+      bytes: [ 0x80, 0xf7, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqinch x0, #28"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc7, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqinch z0.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc4, 0x6f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqinch z0.h, pow2, mul #16"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc4, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqinch z0.h, pow2"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf7, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqinch x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf7, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqinch x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf7, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqinch x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf7, 0x7f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqinch x0, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf7, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqinch w0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf7, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqinch w0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf7, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqinch w0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf7, 0x6f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqinch w0, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf4, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqinch w0, pow2"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf4, 0x6f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqinch w0, pow2, mul #16"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc7, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqinch z0.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc7, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqinch z0.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc7, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqinch z0.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc7, 0x6f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqinch z0.h, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc4, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqinch z0.h, pow2"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc4, 0x6f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqinch z0.h, pow2, mul #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf4, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqinch x0, pow2"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf4, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqinch x0, vl1"
+
+  -
+    input:
+      bytes: [ 0x40, 0xf4, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqinch x0, vl2"
+
+  -
+    input:
+      bytes: [ 0x60, 0xf4, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqinch x0, vl3"
+
+  -
+    input:
+      bytes: [ 0x80, 0xf4, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqinch x0, vl4"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xf4, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqinch x0, vl5"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xf4, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqinch x0, vl6"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf4, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqinch x0, vl7"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf5, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqinch x0, vl8"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf5, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqinch x0, vl16"
+
+  -
+    input:
+      bytes: [ 0x40, 0xf5, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqinch x0, vl32"
+
+  -
+    input:
+      bytes: [ 0x60, 0xf5, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqinch x0, vl64"
+
+  -
+    input:
+      bytes: [ 0x80, 0xf5, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqinch x0, vl128"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xf5, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqinch x0, vl256"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xf5, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqinch x0, #14"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf5, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqinch x0, #15"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf6, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqinch x0, #16"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf6, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqinch x0, #17"
+
+  -
+    input:
+      bytes: [ 0x40, 0xf6, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqinch x0, #18"
+
+  -
+    input:
+      bytes: [ 0x60, 0xf6, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqinch x0, #19"
+
+  -
+    input:
+      bytes: [ 0x80, 0xf6, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqinch x0, #20"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xf6, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqinch x0, #21"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xf6, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqinch x0, #22"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf6, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqinch x0, #23"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf7, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqinch x0, #24"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf7, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqinch x0, #25"
+
+  -
+    input:
+      bytes: [ 0x40, 0xf7, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqinch x0, #26"
+
+  -
+    input:
+      bytes: [ 0x60, 0xf7, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqinch x0, #27"
+
+  -
+    input:
+      bytes: [ 0x80, 0xf7, 0x70, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqinch x0, #28"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc7, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqinch z0.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc4, 0x6f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqinch z0.h, pow2, mul #16"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc4, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqinch z0.h, pow2"
diff --git a/tests/MC/AArch64/SVE/uqincp.s.yaml b/tests/MC/AArch64/SVE/uqincp.s.yaml
new file mode 100644
index 000000000..1dcfeb7a7
--- /dev/null
+++ b/tests/MC/AArch64/SVE/uqincp.s.yaml
@@ -0,0 +1,320 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x8c, 0x29, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincp x0, p0.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x8c, 0x69, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincp x0, p0.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x8c, 0xa9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincp x0, p0.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0x8c, 0xe9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincp x0, p0.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0x89, 0x29, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincp wzr, p15.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x89, 0x69, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincp wzr, p15.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x89, 0xa9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincp wzr, p15.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0x89, 0xe9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincp wzr, p15.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x69, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincp z0.h, p0.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x69, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincp z0.h, p0.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xa9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincp z0.s, p0.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xa9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincp z0.s, p0.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xe9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincp z0.d, p0.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xe9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincp z0.d, p0.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xe9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincp z0.d, p0.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x8c, 0x29, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincp x0, p0.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x8c, 0x69, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincp x0, p0.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x8c, 0xa9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincp x0, p0.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0x8c, 0xe9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincp x0, p0.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0x89, 0x29, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincp wzr, p15.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x89, 0x69, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincp wzr, p15.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x89, 0xa9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincp wzr, p15.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0x89, 0xe9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincp wzr, p15.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x69, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincp z0.h, p0.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x69, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincp z0.h, p0.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xa9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincp z0.s, p0.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xa9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincp z0.s, p0.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xe9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincp z0.d, p0.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xe9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincp z0.d, p0.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xe9, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincp z0.d, p0.d"
diff --git a/tests/MC/AArch64/SVE/uqincw.s.yaml b/tests/MC/AArch64/SVE/uqincw.s.yaml
new file mode 100644
index 000000000..6ff7e4d36
--- /dev/null
+++ b/tests/MC/AArch64/SVE/uqincw.s.yaml
@@ -0,0 +1,1020 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xe0, 0xf7, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincw x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf7, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincw x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf7, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincw x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf7, 0xbf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincw x0, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf7, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincw w0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf7, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincw w0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf7, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincw w0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf7, 0xaf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincw w0, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf4, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincw w0, pow2"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf4, 0xaf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincw w0, pow2, mul #16"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc7, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincw z0.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc7, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincw z0.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc7, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincw z0.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc7, 0xaf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincw z0.s, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc4, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincw z0.s, pow2"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc4, 0xaf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincw z0.s, pow2, mul #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf4, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincw x0, pow2"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf4, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincw x0, vl1"
+
+  -
+    input:
+      bytes: [ 0x40, 0xf4, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincw x0, vl2"
+
+  -
+    input:
+      bytes: [ 0x60, 0xf4, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincw x0, vl3"
+
+  -
+    input:
+      bytes: [ 0x80, 0xf4, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincw x0, vl4"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xf4, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincw x0, vl5"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xf4, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincw x0, vl6"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf4, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincw x0, vl7"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf5, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincw x0, vl8"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf5, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincw x0, vl16"
+
+  -
+    input:
+      bytes: [ 0x40, 0xf5, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincw x0, vl32"
+
+  -
+    input:
+      bytes: [ 0x60, 0xf5, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincw x0, vl64"
+
+  -
+    input:
+      bytes: [ 0x80, 0xf5, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincw x0, vl128"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xf5, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincw x0, vl256"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xf5, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincw x0, #14"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf5, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincw x0, #15"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf6, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincw x0, #16"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf6, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincw x0, #17"
+
+  -
+    input:
+      bytes: [ 0x40, 0xf6, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincw x0, #18"
+
+  -
+    input:
+      bytes: [ 0x60, 0xf6, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincw x0, #19"
+
+  -
+    input:
+      bytes: [ 0x80, 0xf6, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincw x0, #20"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xf6, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincw x0, #21"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xf6, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincw x0, #22"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf6, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincw x0, #23"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf7, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincw x0, #24"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf7, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincw x0, #25"
+
+  -
+    input:
+      bytes: [ 0x40, 0xf7, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincw x0, #26"
+
+  -
+    input:
+      bytes: [ 0x60, 0xf7, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincw x0, #27"
+
+  -
+    input:
+      bytes: [ 0x80, 0xf7, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincw x0, #28"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc7, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincw z0.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc4, 0xaf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincw z0.s, pow2, mul #16"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc4, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincw z0.s, pow2"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf7, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincw x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf7, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincw x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf7, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincw x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf7, 0xbf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincw x0, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf7, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincw w0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf7, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincw w0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf7, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincw w0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf7, 0xaf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincw w0, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf4, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincw w0, pow2"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf4, 0xaf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincw w0, pow2, mul #16"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc7, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincw z0.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc7, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincw z0.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc7, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincw z0.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc7, 0xaf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincw z0.s, all, mul #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc4, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincw z0.s, pow2"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc4, 0xaf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincw z0.s, pow2, mul #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf4, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincw x0, pow2"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf4, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincw x0, vl1"
+
+  -
+    input:
+      bytes: [ 0x40, 0xf4, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincw x0, vl2"
+
+  -
+    input:
+      bytes: [ 0x60, 0xf4, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincw x0, vl3"
+
+  -
+    input:
+      bytes: [ 0x80, 0xf4, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincw x0, vl4"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xf4, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincw x0, vl5"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xf4, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincw x0, vl6"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf4, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincw x0, vl7"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf5, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincw x0, vl8"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf5, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincw x0, vl16"
+
+  -
+    input:
+      bytes: [ 0x40, 0xf5, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincw x0, vl32"
+
+  -
+    input:
+      bytes: [ 0x60, 0xf5, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincw x0, vl64"
+
+  -
+    input:
+      bytes: [ 0x80, 0xf5, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincw x0, vl128"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xf5, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincw x0, vl256"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xf5, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincw x0, #14"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf5, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincw x0, #15"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf6, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincw x0, #16"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf6, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincw x0, #17"
+
+  -
+    input:
+      bytes: [ 0x40, 0xf6, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincw x0, #18"
+
+  -
+    input:
+      bytes: [ 0x60, 0xf6, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincw x0, #19"
+
+  -
+    input:
+      bytes: [ 0x80, 0xf6, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincw x0, #20"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xf6, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincw x0, #21"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xf6, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincw x0, #22"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xf6, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincw x0, #23"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf7, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincw x0, #24"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf7, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincw x0, #25"
+
+  -
+    input:
+      bytes: [ 0x40, 0xf7, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincw x0, #26"
+
+  -
+    input:
+      bytes: [ 0x60, 0xf7, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincw x0, #27"
+
+  -
+    input:
+      bytes: [ 0x80, 0xf7, 0xb0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincw x0, #28"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc7, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincw z0.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc4, 0xaf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincw z0.s, pow2, mul #16"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc4, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqincw z0.s, pow2"
diff --git a/tests/MC/AArch64/SVE/uqsub.s.yaml b/tests/MC/AArch64/SVE/uqsub.s.yaml
new file mode 100644
index 000000000..490f6c12e
--- /dev/null
+++ b/tests/MC/AArch64/SVE/uqsub.s.yaml
@@ -0,0 +1,400 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x1c, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqsub z0.b, z0.b, z0.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x1c, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqsub z0.h, z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x1c, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqsub z0.s, z0.s, z0.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0x1c, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqsub z0.d, z0.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x27, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqsub z0.b, z0.b, #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0xdf, 0x27, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqsub z31.b, z31.b, #255"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x67, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqsub z0.h, z0.h, #0"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x67, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqsub z0.h, z0.h, #0, lsl #8"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0x67, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqsub z31.h, z31.h, #65280"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0x67, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqsub z31.h, z31.h, #65280"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0xa7, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqsub z0.s, z0.s, #0"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xa7, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqsub z0.s, z0.s, #0, lsl #8"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xa7, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqsub z31.s, z31.s, #65280"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xa7, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqsub z31.s, z31.s, #65280"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0xe7, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqsub z0.d, z0.d, #0"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xe7, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqsub z0.d, z0.d, #0, lsl #8"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xe7, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqsub z31.d, z31.d, #65280"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xe7, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqsub z31.d, z31.d, #65280"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xe7, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqsub z31.d, z31.d, #65280"
+
+  -
+    input:
+      bytes: [ 0x00, 0x1c, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqsub z0.b, z0.b, z0.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x1c, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqsub z0.h, z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x1c, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqsub z0.s, z0.s, z0.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0x1c, 0xe0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqsub z0.d, z0.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x27, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqsub z0.b, z0.b, #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0xdf, 0x27, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqsub z31.b, z31.b, #255"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x67, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqsub z0.h, z0.h, #0"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x67, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqsub z0.h, z0.h, #0, lsl #8"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0x67, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqsub z31.h, z31.h, #65280"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0x67, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqsub z31.h, z31.h, #65280"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0xa7, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqsub z0.s, z0.s, #0"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xa7, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqsub z0.s, z0.s, #0, lsl #8"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xa7, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqsub z31.s, z31.s, #65280"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xa7, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqsub z31.s, z31.s, #65280"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0xe7, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqsub z0.d, z0.d, #0"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xe7, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqsub z0.d, z0.d, #0, lsl #8"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xe7, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqsub z31.d, z31.d, #65280"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xe7, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqsub z31.d, z31.d, #65280"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xe7, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqsub z31.d, z31.d, #65280"
diff --git a/tests/MC/AArch64/SVE/uunpkhi.s.yaml b/tests/MC/AArch64/SVE/uunpkhi.s.yaml
new file mode 100644
index 000000000..b3fe26554
--- /dev/null
+++ b/tests/MC/AArch64/SVE/uunpkhi.s.yaml
@@ -0,0 +1,60 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xff, 0x3b, 0x73, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uunpkhi z31.h, z31.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3b, 0xb3, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uunpkhi z31.s, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3b, 0xf3, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uunpkhi z31.d, z31.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3b, 0x73, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uunpkhi z31.h, z31.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3b, 0xb3, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uunpkhi z31.s, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3b, 0xf3, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uunpkhi z31.d, z31.s"
diff --git a/tests/MC/AArch64/SVE/uunpklo.s.yaml b/tests/MC/AArch64/SVE/uunpklo.s.yaml
new file mode 100644
index 000000000..1e2a16413
--- /dev/null
+++ b/tests/MC/AArch64/SVE/uunpklo.s.yaml
@@ -0,0 +1,60 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xff, 0x3b, 0x72, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uunpklo z31.h, z31.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3b, 0xb2, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uunpklo z31.s, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3b, 0xf2, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uunpklo z31.d, z31.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3b, 0x72, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uunpklo z31.h, z31.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3b, 0xb2, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uunpklo z31.s, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3b, 0xf2, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uunpklo z31.d, z31.s"
diff --git a/tests/MC/AArch64/SVE/uxtb.s.yaml b/tests/MC/AArch64/SVE/uxtb.s.yaml
new file mode 100644
index 000000000..fd8ca8d2f
--- /dev/null
+++ b/tests/MC/AArch64/SVE/uxtb.s.yaml
@@ -0,0 +1,200 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x51, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uxtb z0.h, p0/m, z0.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x91, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uxtb z0.s, p0/m, z0.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xd1, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uxtb z0.d, p0/m, z0.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x51, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uxtb z31.h, p7/m, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x91, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uxtb z31.s, p7/m, z31.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0xd1, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uxtb z31.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4.d, p7/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xbf, 0xd1, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uxtb z4.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4, z6"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xbf, 0xd1, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uxtb z4.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x51, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uxtb z0.h, p0/m, z0.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x91, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uxtb z0.s, p0/m, z0.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xd1, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uxtb z0.d, p0/m, z0.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x51, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uxtb z31.h, p7/m, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x91, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uxtb z31.s, p7/m, z31.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0xd1, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uxtb z31.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4.d, p7/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xbf, 0xd1, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uxtb z4.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4, z6"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xbf, 0xd1, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uxtb z4.d, p7/m, z31.d"
diff --git a/tests/MC/AArch64/SVE/uxth.s.yaml b/tests/MC/AArch64/SVE/uxth.s.yaml
new file mode 100644
index 000000000..695af16cc
--- /dev/null
+++ b/tests/MC/AArch64/SVE/uxth.s.yaml
@@ -0,0 +1,160 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x93, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uxth z0.s, p0/m, z0.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xd3, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uxth z0.d, p0/m, z0.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x93, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uxth z31.s, p7/m, z31.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0xd3, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uxth z31.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4.d, p7/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xbf, 0xd3, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uxth z4.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4, z6"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xbf, 0xd3, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uxth z4.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x93, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uxth z0.s, p0/m, z0.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xd3, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uxth z0.d, p0/m, z0.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x93, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uxth z31.s, p7/m, z31.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0xd3, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uxth z31.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4.d, p7/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xbf, 0xd3, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uxth z4.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4, z6"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xbf, 0xd3, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uxth z4.d, p7/m, z31.d"
diff --git a/tests/MC/AArch64/SVE/uxtw.s.yaml b/tests/MC/AArch64/SVE/uxtw.s.yaml
new file mode 100644
index 000000000..2eefa1d0d
--- /dev/null
+++ b/tests/MC/AArch64/SVE/uxtw.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xd5, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uxtw z0.d, p0/m, z0.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0xd5, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uxtw z31.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4.d, p7/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xbf, 0xd5, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uxtw z4.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4, z6"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xbf, 0xd5, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uxtw z4.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xd5, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uxtw z0.d, p0/m, z0.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0xd5, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uxtw z31.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4.d, p7/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xbf, 0xd5, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uxtw z4.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4, z6"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xbf, 0xd5, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uxtw z4.d, p7/m, z31.d"
diff --git a/tests/MC/AArch64/SVE/uzp1.s.yaml b/tests/MC/AArch64/SVE/uzp1.s.yaml
new file mode 100644
index 000000000..5458b7ac6
--- /dev/null
+++ b/tests/MC/AArch64/SVE/uzp1.s.yaml
@@ -0,0 +1,160 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xff, 0x6b, 0x3f, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzp1 z31.b, z31.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x6b, 0x7f, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzp1 z31.h, z31.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x6b, 0xbf, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzp1 z31.s, z31.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0x6b, 0xff, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzp1 z31.d, z31.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xef, 0x49, 0x2f, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzp1 p15.b, p15.b, p15.b"
+
+  -
+    input:
+      bytes: [ 0xef, 0x49, 0xaf, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzp1 p15.s, p15.s, p15.s"
+
+  -
+    input:
+      bytes: [ 0xef, 0x49, 0x6f, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzp1 p15.h, p15.h, p15.h"
+
+  -
+    input:
+      bytes: [ 0xef, 0x49, 0xef, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzp1 p15.d, p15.d, p15.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0x6b, 0x3f, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzp1 z31.b, z31.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x6b, 0x7f, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzp1 z31.h, z31.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x6b, 0xbf, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzp1 z31.s, z31.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0x6b, 0xff, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzp1 z31.d, z31.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xef, 0x49, 0x2f, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzp1 p15.b, p15.b, p15.b"
+
+  -
+    input:
+      bytes: [ 0xef, 0x49, 0xaf, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzp1 p15.s, p15.s, p15.s"
+
+  -
+    input:
+      bytes: [ 0xef, 0x49, 0x6f, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzp1 p15.h, p15.h, p15.h"
+
+  -
+    input:
+      bytes: [ 0xef, 0x49, 0xef, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzp1 p15.d, p15.d, p15.d"
diff --git a/tests/MC/AArch64/SVE/uzp2.s.yaml b/tests/MC/AArch64/SVE/uzp2.s.yaml
new file mode 100644
index 000000000..506121c00
--- /dev/null
+++ b/tests/MC/AArch64/SVE/uzp2.s.yaml
@@ -0,0 +1,160 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xff, 0x6f, 0x3f, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzp2 z31.b, z31.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x6f, 0x7f, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzp2 z31.h, z31.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x6f, 0xbf, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzp2 z31.s, z31.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0x6f, 0xff, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzp2 z31.d, z31.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xef, 0x4d, 0x2f, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzp2 p15.b, p15.b, p15.b"
+
+  -
+    input:
+      bytes: [ 0xef, 0x4d, 0xaf, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzp2 p15.s, p15.s, p15.s"
+
+  -
+    input:
+      bytes: [ 0xef, 0x4d, 0x6f, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzp2 p15.h, p15.h, p15.h"
+
+  -
+    input:
+      bytes: [ 0xef, 0x4d, 0xef, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzp2 p15.d, p15.d, p15.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0x6f, 0x3f, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzp2 z31.b, z31.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x6f, 0x7f, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzp2 z31.h, z31.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x6f, 0xbf, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzp2 z31.s, z31.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0x6f, 0xff, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzp2 z31.d, z31.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xef, 0x4d, 0x2f, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzp2 p15.b, p15.b, p15.b"
+
+  -
+    input:
+      bytes: [ 0xef, 0x4d, 0xaf, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzp2 p15.s, p15.s, p15.s"
+
+  -
+    input:
+      bytes: [ 0xef, 0x4d, 0x6f, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzp2 p15.h, p15.h, p15.h"
+
+  -
+    input:
+      bytes: [ 0xef, 0x4d, 0xef, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzp2 p15.d, p15.d, p15.d"
diff --git a/tests/MC/AArch64/SVE/whilele.s.yaml b/tests/MC/AArch64/SVE/whilele.s.yaml
new file mode 100644
index 000000000..ad9f0898a
--- /dev/null
+++ b/tests/MC/AArch64/SVE/whilele.s.yaml
@@ -0,0 +1,200 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xff, 0x17, 0x20, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilele p15.b, xzr, x0"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x14, 0x3f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilele p15.b, x0, xzr"
+
+  -
+    input:
+      bytes: [ 0xff, 0x07, 0x20, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilele p15.b, wzr, w0"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x04, 0x3f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilele p15.b, w0, wzr"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x14, 0x7f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilele p15.h, x0, xzr"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x04, 0x7f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilele p15.h, w0, wzr"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x14, 0xbf, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilele p15.s, x0, xzr"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x04, 0xbf, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilele p15.s, w0, wzr"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x04, 0xff, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilele p15.d, w0, wzr"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x14, 0xff, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilele p15.d, x0, xzr"
+
+  -
+    input:
+      bytes: [ 0xff, 0x17, 0x20, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilele p15.b, xzr, x0"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x14, 0x3f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilele p15.b, x0, xzr"
+
+  -
+    input:
+      bytes: [ 0xff, 0x07, 0x20, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilele p15.b, wzr, w0"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x04, 0x3f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilele p15.b, w0, wzr"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x14, 0x7f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilele p15.h, x0, xzr"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x04, 0x7f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilele p15.h, w0, wzr"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x14, 0xbf, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilele p15.s, x0, xzr"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x04, 0xbf, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilele p15.s, w0, wzr"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x04, 0xff, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilele p15.d, w0, wzr"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x14, 0xff, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilele p15.d, x0, xzr"
diff --git a/tests/MC/AArch64/SVE/whilelo.s.yaml b/tests/MC/AArch64/SVE/whilelo.s.yaml
new file mode 100644
index 000000000..fc4c7b68c
--- /dev/null
+++ b/tests/MC/AArch64/SVE/whilelo.s.yaml
@@ -0,0 +1,200 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xef, 0x1f, 0x20, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelo p15.b, xzr, x0"
+
+  -
+    input:
+      bytes: [ 0x0f, 0x1c, 0x3f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelo p15.b, x0, xzr"
+
+  -
+    input:
+      bytes: [ 0xef, 0x0f, 0x20, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelo p15.b, wzr, w0"
+
+  -
+    input:
+      bytes: [ 0x0f, 0x0c, 0x3f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelo p15.b, w0, wzr"
+
+  -
+    input:
+      bytes: [ 0x0f, 0x1c, 0x7f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelo p15.h, x0, xzr"
+
+  -
+    input:
+      bytes: [ 0x0f, 0x0c, 0x7f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelo p15.h, w0, wzr"
+
+  -
+    input:
+      bytes: [ 0x0f, 0x1c, 0xbf, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelo p15.s, x0, xzr"
+
+  -
+    input:
+      bytes: [ 0x0f, 0x0c, 0xbf, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelo p15.s, w0, wzr"
+
+  -
+    input:
+      bytes: [ 0x0f, 0x0c, 0xff, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelo p15.d, w0, wzr"
+
+  -
+    input:
+      bytes: [ 0x0f, 0x1c, 0xff, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelo p15.d, x0, xzr"
+
+  -
+    input:
+      bytes: [ 0xef, 0x1f, 0x20, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelo p15.b, xzr, x0"
+
+  -
+    input:
+      bytes: [ 0x0f, 0x1c, 0x3f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelo p15.b, x0, xzr"
+
+  -
+    input:
+      bytes: [ 0xef, 0x0f, 0x20, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelo p15.b, wzr, w0"
+
+  -
+    input:
+      bytes: [ 0x0f, 0x0c, 0x3f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelo p15.b, w0, wzr"
+
+  -
+    input:
+      bytes: [ 0x0f, 0x1c, 0x7f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelo p15.h, x0, xzr"
+
+  -
+    input:
+      bytes: [ 0x0f, 0x0c, 0x7f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelo p15.h, w0, wzr"
+
+  -
+    input:
+      bytes: [ 0x0f, 0x1c, 0xbf, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelo p15.s, x0, xzr"
+
+  -
+    input:
+      bytes: [ 0x0f, 0x0c, 0xbf, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelo p15.s, w0, wzr"
+
+  -
+    input:
+      bytes: [ 0x0f, 0x0c, 0xff, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelo p15.d, w0, wzr"
+
+  -
+    input:
+      bytes: [ 0x0f, 0x1c, 0xff, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelo p15.d, x0, xzr"
diff --git a/tests/MC/AArch64/SVE/whilels.s.yaml b/tests/MC/AArch64/SVE/whilels.s.yaml
new file mode 100644
index 000000000..2e86a1f4a
--- /dev/null
+++ b/tests/MC/AArch64/SVE/whilels.s.yaml
@@ -0,0 +1,200 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0x20, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilels p15.b, xzr, x0"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x1c, 0x3f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilels p15.b, x0, xzr"
+
+  -
+    input:
+      bytes: [ 0xff, 0x0f, 0x20, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilels p15.b, wzr, w0"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x0c, 0x3f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilels p15.b, w0, wzr"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x1c, 0x7f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilels p15.h, x0, xzr"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x0c, 0x7f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilels p15.h, w0, wzr"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x1c, 0xbf, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilels p15.s, x0, xzr"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x0c, 0xbf, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilels p15.s, w0, wzr"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x0c, 0xff, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilels p15.d, w0, wzr"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x1c, 0xff, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilels p15.d, x0, xzr"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0x20, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilels p15.b, xzr, x0"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x1c, 0x3f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilels p15.b, x0, xzr"
+
+  -
+    input:
+      bytes: [ 0xff, 0x0f, 0x20, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilels p15.b, wzr, w0"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x0c, 0x3f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilels p15.b, w0, wzr"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x1c, 0x7f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilels p15.h, x0, xzr"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x0c, 0x7f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilels p15.h, w0, wzr"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x1c, 0xbf, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilels p15.s, x0, xzr"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x0c, 0xbf, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilels p15.s, w0, wzr"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x0c, 0xff, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilels p15.d, w0, wzr"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x1c, 0xff, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilels p15.d, x0, xzr"
diff --git a/tests/MC/AArch64/SVE/whilelt.s.yaml b/tests/MC/AArch64/SVE/whilelt.s.yaml
new file mode 100644
index 000000000..ea4cdc1bc
--- /dev/null
+++ b/tests/MC/AArch64/SVE/whilelt.s.yaml
@@ -0,0 +1,200 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xef, 0x17, 0x20, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelt p15.b, xzr, x0"
+
+  -
+    input:
+      bytes: [ 0x0f, 0x14, 0x3f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelt p15.b, x0, xzr"
+
+  -
+    input:
+      bytes: [ 0xef, 0x07, 0x20, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelt p15.b, wzr, w0"
+
+  -
+    input:
+      bytes: [ 0x0f, 0x04, 0x3f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelt p15.b, w0, wzr"
+
+  -
+    input:
+      bytes: [ 0x0f, 0x14, 0x7f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelt p15.h, x0, xzr"
+
+  -
+    input:
+      bytes: [ 0x0f, 0x04, 0x7f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelt p15.h, w0, wzr"
+
+  -
+    input:
+      bytes: [ 0x0f, 0x14, 0xbf, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelt p15.s, x0, xzr"
+
+  -
+    input:
+      bytes: [ 0x0f, 0x04, 0xbf, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelt p15.s, w0, wzr"
+
+  -
+    input:
+      bytes: [ 0x0f, 0x04, 0xff, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelt p15.d, w0, wzr"
+
+  -
+    input:
+      bytes: [ 0x0f, 0x14, 0xff, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelt p15.d, x0, xzr"
+
+  -
+    input:
+      bytes: [ 0xef, 0x17, 0x20, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelt p15.b, xzr, x0"
+
+  -
+    input:
+      bytes: [ 0x0f, 0x14, 0x3f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelt p15.b, x0, xzr"
+
+  -
+    input:
+      bytes: [ 0xef, 0x07, 0x20, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelt p15.b, wzr, w0"
+
+  -
+    input:
+      bytes: [ 0x0f, 0x04, 0x3f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelt p15.b, w0, wzr"
+
+  -
+    input:
+      bytes: [ 0x0f, 0x14, 0x7f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelt p15.h, x0, xzr"
+
+  -
+    input:
+      bytes: [ 0x0f, 0x04, 0x7f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelt p15.h, w0, wzr"
+
+  -
+    input:
+      bytes: [ 0x0f, 0x14, 0xbf, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelt p15.s, x0, xzr"
+
+  -
+    input:
+      bytes: [ 0x0f, 0x04, 0xbf, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelt p15.s, w0, wzr"
+
+  -
+    input:
+      bytes: [ 0x0f, 0x04, 0xff, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelt p15.d, w0, wzr"
+
+  -
+    input:
+      bytes: [ 0x0f, 0x14, 0xff, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelt p15.d, x0, xzr"
diff --git a/tests/MC/AArch64/SVE/wrffr.s.yaml b/tests/MC/AArch64/SVE/wrffr.s.yaml
new file mode 100644
index 000000000..7219e543c
--- /dev/null
+++ b/tests/MC/AArch64/SVE/wrffr.s.yaml
@@ -0,0 +1,20 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x90, 0x28, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "wrffr p0.b"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x91, 0x28, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "wrffr p15.b"
diff --git a/tests/MC/AArch64/SVE/zip1.s.yaml b/tests/MC/AArch64/SVE/zip1.s.yaml
new file mode 100644
index 000000000..9e823704f
--- /dev/null
+++ b/tests/MC/AArch64/SVE/zip1.s.yaml
@@ -0,0 +1,320 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0x20, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip1 z0.b, z0.b, z0.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0x60, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip1 z0.h, z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0xa0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip1 z0.s, z0.s, z0.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0xe0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip1 z0.d, z0.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0x63, 0x3f, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip1 z31.b, z31.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x63, 0x7f, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip1 z31.h, z31.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x63, 0xbf, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip1 z31.s, z31.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0x63, 0xff, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip1 z31.d, z31.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0x20, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip1 p0.b, p0.b, p0.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0x60, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip1 p0.h, p0.h, p0.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0xa0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip1 p0.s, p0.s, p0.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0xe0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip1 p0.d, p0.d, p0.d"
+
+  -
+    input:
+      bytes: [ 0xef, 0x41, 0x2f, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip1 p15.b, p15.b, p15.b"
+
+  -
+    input:
+      bytes: [ 0xef, 0x41, 0xaf, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip1 p15.s, p15.s, p15.s"
+
+  -
+    input:
+      bytes: [ 0xef, 0x41, 0x6f, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip1 p15.h, p15.h, p15.h"
+
+  -
+    input:
+      bytes: [ 0xef, 0x41, 0xef, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip1 p15.d, p15.d, p15.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0x20, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip1 z0.b, z0.b, z0.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0x60, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip1 z0.h, z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0xa0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip1 z0.s, z0.s, z0.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0xe0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip1 z0.d, z0.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0x63, 0x3f, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip1 z31.b, z31.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x63, 0x7f, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip1 z31.h, z31.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x63, 0xbf, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip1 z31.s, z31.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0x63, 0xff, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip1 z31.d, z31.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0x20, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip1 p0.b, p0.b, p0.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0x60, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip1 p0.h, p0.h, p0.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0xa0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip1 p0.s, p0.s, p0.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0xe0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip1 p0.d, p0.d, p0.d"
+
+  -
+    input:
+      bytes: [ 0xef, 0x41, 0x2f, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip1 p15.b, p15.b, p15.b"
+
+  -
+    input:
+      bytes: [ 0xef, 0x41, 0xaf, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip1 p15.s, p15.s, p15.s"
+
+  -
+    input:
+      bytes: [ 0xef, 0x41, 0x6f, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip1 p15.h, p15.h, p15.h"
+
+  -
+    input:
+      bytes: [ 0xef, 0x41, 0xef, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip1 p15.d, p15.d, p15.d"
diff --git a/tests/MC/AArch64/SVE/zip2.s.yaml b/tests/MC/AArch64/SVE/zip2.s.yaml
new file mode 100644
index 000000000..0e629d4de
--- /dev/null
+++ b/tests/MC/AArch64/SVE/zip2.s.yaml
@@ -0,0 +1,320 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x64, 0x20, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip2 z0.b, z0.b, z0.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x64, 0x60, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip2 z0.h, z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x64, 0xa0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip2 z0.s, z0.s, z0.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0x64, 0xe0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip2 z0.d, z0.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0x67, 0x3f, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip2 z31.b, z31.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x67, 0x7f, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip2 z31.h, z31.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x67, 0xbf, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip2 z31.s, z31.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0x67, 0xff, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip2 z31.d, z31.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x44, 0x20, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip2 p0.b, p0.b, p0.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x44, 0x60, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip2 p0.h, p0.h, p0.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x44, 0xa0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip2 p0.s, p0.s, p0.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0x44, 0xe0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip2 p0.d, p0.d, p0.d"
+
+  -
+    input:
+      bytes: [ 0xef, 0x45, 0x2f, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip2 p15.b, p15.b, p15.b"
+
+  -
+    input:
+      bytes: [ 0xef, 0x45, 0x6f, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip2 p15.h, p15.h, p15.h"
+
+  -
+    input:
+      bytes: [ 0xef, 0x45, 0xaf, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip2 p15.s, p15.s, p15.s"
+
+  -
+    input:
+      bytes: [ 0xef, 0x45, 0xef, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip2 p15.d, p15.d, p15.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x64, 0x20, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip2 z0.b, z0.b, z0.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x64, 0x60, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip2 z0.h, z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x64, 0xa0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip2 z0.s, z0.s, z0.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0x64, 0xe0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip2 z0.d, z0.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0x67, 0x3f, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip2 z31.b, z31.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x67, 0x7f, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip2 z31.h, z31.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x67, 0xbf, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip2 z31.s, z31.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0x67, 0xff, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip2 z31.d, z31.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x44, 0x20, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip2 p0.b, p0.b, p0.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x44, 0x60, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip2 p0.h, p0.h, p0.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x44, 0xa0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip2 p0.s, p0.s, p0.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0x44, 0xe0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip2 p0.d, p0.d, p0.d"
+
+  -
+    input:
+      bytes: [ 0xef, 0x45, 0x2f, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip2 p15.b, p15.b, p15.b"
+
+  -
+    input:
+      bytes: [ 0xef, 0x45, 0x6f, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip2 p15.h, p15.h, p15.h"
+
+  -
+    input:
+      bytes: [ 0xef, 0x45, 0xaf, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip2 p15.s, p15.s, p15.s"
+
+  -
+    input:
+      bytes: [ 0xef, 0x45, 0xef, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip2 p15.d, p15.d, p15.d"
diff --git a/tests/MC/AArch64/SVE2/adclb.s.yaml b/tests/MC/AArch64/SVE2/adclb.s.yaml
new file mode 100644
index 000000000..cb9ca5088
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/adclb.s.yaml
@@ -0,0 +1,80 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0xd0, 0x1f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "adclb z0.s, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd0, 0x5f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "adclb z0.d, z1.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd0, 0x5f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "adclb z0.d, z1.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd0, 0x1f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "adclb z0.s, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd0, 0x5f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "adclb z0.d, z1.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd0, 0x5f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "adclb z0.d, z1.d, z31.d"
diff --git a/tests/MC/AArch64/SVE2/adclt.s.yaml b/tests/MC/AArch64/SVE2/adclt.s.yaml
new file mode 100644
index 000000000..16ea9d006
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/adclt.s.yaml
@@ -0,0 +1,80 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0xd4, 0x1f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "adclt z0.s, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd4, 0x5f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "adclt z0.d, z1.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd4, 0x5f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "adclt z0.d, z1.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd4, 0x1f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "adclt z0.s, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd4, 0x5f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "adclt z0.d, z1.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd4, 0x5f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "adclt z0.d, z1.d, z31.d"
diff --git a/tests/MC/AArch64/SVE2/addhnb.s.yaml b/tests/MC/AArch64/SVE2/addhnb.s.yaml
new file mode 100644
index 000000000..ba4c6091a
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/addhnb.s.yaml
@@ -0,0 +1,60 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x60, 0x7f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "addhnb z0.b, z1.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x60, 0xbf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "addhnb z0.h, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x60, 0xff, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "addhnb z0.s, z1.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x60, 0x7f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "addhnb z0.b, z1.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x60, 0xbf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "addhnb z0.h, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x60, 0xff, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "addhnb z0.s, z1.d, z31.d"
diff --git a/tests/MC/AArch64/SVE2/addhnt.s.yaml b/tests/MC/AArch64/SVE2/addhnt.s.yaml
new file mode 100644
index 000000000..a226519c8
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/addhnt.s.yaml
@@ -0,0 +1,60 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x64, 0x7f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "addhnt z0.b, z1.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x64, 0xbf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "addhnt z0.h, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x64, 0xff, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "addhnt z0.s, z1.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x64, 0x7f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "addhnt z0.b, z1.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x64, 0xbf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "addhnt z0.h, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x64, 0xff, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "addhnt z0.s, z1.d, z31.d"
diff --git a/tests/MC/AArch64/SVE2/addp.s.yaml b/tests/MC/AArch64/SVE2/addp.s.yaml
new file mode 100644
index 000000000..5b11b5bd0
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/addp.s.yaml
@@ -0,0 +1,160 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0xa0, 0x11, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "addp z0.b, p0/m, z0.b, z1.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa0, 0x51, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "addp z0.h, p0/m, z0.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0xdd, 0xbf, 0x91, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "addp z29.s, p7/m, z29.s, z30.s"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbf, 0xd1, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "addp z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31.d, p0/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xa3, 0xd1, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "addp z31.d, p0/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbf, 0xd1, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "addp z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa0, 0x11, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "addp z0.b, p0/m, z0.b, z1.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa0, 0x51, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "addp z0.h, p0/m, z0.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0xdd, 0xbf, 0x91, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "addp z29.s, p7/m, z29.s, z30.s"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbf, 0xd1, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "addp z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31.d, p0/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xa3, 0xd1, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "addp z31.d, p0/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbf, 0xd1, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "addp z31.d, p7/m, z31.d, z30.d"
diff --git a/tests/MC/AArch64/SVE2/aesd.s.yaml b/tests/MC/AArch64/SVE2/aesd.s.yaml
new file mode 100644
index 000000000..e6fc76355
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/aesd.s.yaml
@@ -0,0 +1,10 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xe0, 0xe7, 0x22, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2-aes" ]
+    expected:
+      insns:
+        -
+          asm_text: "aesd z0.b, z0.b, z31.b"
diff --git a/tests/MC/AArch64/SVE2/aese.s.yaml b/tests/MC/AArch64/SVE2/aese.s.yaml
new file mode 100644
index 000000000..16e950ec1
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/aese.s.yaml
@@ -0,0 +1,10 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xe0, 0xe3, 0x22, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2-aes" ]
+    expected:
+      insns:
+        -
+          asm_text: "aese z0.b, z0.b, z31.b"
diff --git a/tests/MC/AArch64/SVE2/aesimc.s.yaml b/tests/MC/AArch64/SVE2/aesimc.s.yaml
new file mode 100644
index 000000000..82b860eda
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/aesimc.s.yaml
@@ -0,0 +1,20 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xe4, 0x20, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2-aes" ]
+    expected:
+      insns:
+        -
+          asm_text: "aesimc z0.b, z0.b"
+
+  -
+    input:
+      bytes: [ 0x1f, 0xe4, 0x20, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2-aes" ]
+    expected:
+      insns:
+        -
+          asm_text: "aesimc z31.b, z31.b"
diff --git a/tests/MC/AArch64/SVE2/aesmc.s.yaml b/tests/MC/AArch64/SVE2/aesmc.s.yaml
new file mode 100644
index 000000000..ed0f8f25e
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/aesmc.s.yaml
@@ -0,0 +1,20 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x20, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2-aes" ]
+    expected:
+      insns:
+        -
+          asm_text: "aesmc z0.b, z0.b"
+
+  -
+    input:
+      bytes: [ 0x1f, 0xe0, 0x20, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2-aes" ]
+    expected:
+      insns:
+        -
+          asm_text: "aesmc z31.b, z31.b"
diff --git a/tests/MC/AArch64/SVE2/bcax.s.yaml b/tests/MC/AArch64/SVE2/bcax.s.yaml
new file mode 100644
index 000000000..0e06a8453
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/bcax.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xfd, 0x3b, 0x7e, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bcax z29.d, z29.d, z30.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xfd, 0x3b, 0x7e, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bcax z29.d, z29.d, z30.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xfd, 0x3b, 0x7e, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bcax z29.d, z29.d, z30.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xfd, 0x3b, 0x7e, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bcax z29.d, z29.d, z30.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z7"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x3b, 0x7e, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bcax z31.d, z31.d, z30.d, z29.d"
+
+  -
+    input:
+      bytes: [ 0xfd, 0x3b, 0x7e, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "bcax z29.d, z29.d, z30.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xfd, 0x3b, 0x7e, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "bcax z29.d, z29.d, z30.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xfd, 0x3b, 0x7e, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "bcax z29.d, z29.d, z30.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xfd, 0x3b, 0x7e, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "bcax z29.d, z29.d, z30.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z7"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x3b, 0x7e, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "bcax z31.d, z31.d, z30.d, z29.d"
diff --git a/tests/MC/AArch64/SVE2/bdep.s.yaml b/tests/MC/AArch64/SVE2/bdep.s.yaml
new file mode 100644
index 000000000..47a2c8147
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/bdep.s.yaml
@@ -0,0 +1,40 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0xb4, 0x1f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2-bitperm" ]
+    expected:
+      insns:
+        -
+          asm_text: "bdep z0.b, z1.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0xb4, 0x5f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2-bitperm" ]
+    expected:
+      insns:
+        -
+          asm_text: "bdep z0.h, z1.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0xb4, 0x9f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2-bitperm" ]
+    expected:
+      insns:
+        -
+          asm_text: "bdep z0.s, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0xb4, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2-bitperm" ]
+    expected:
+      insns:
+        -
+          asm_text: "bdep z0.d, z1.d, z31.d"
diff --git a/tests/MC/AArch64/SVE2/bext.s.yaml b/tests/MC/AArch64/SVE2/bext.s.yaml
new file mode 100644
index 000000000..1e9e00767
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/bext.s.yaml
@@ -0,0 +1,40 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0xb0, 0x1f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2-bitperm" ]
+    expected:
+      insns:
+        -
+          asm_text: "bext z0.b, z1.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0xb0, 0x5f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2-bitperm" ]
+    expected:
+      insns:
+        -
+          asm_text: "bext z0.h, z1.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0xb0, 0x9f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2-bitperm" ]
+    expected:
+      insns:
+        -
+          asm_text: "bext z0.s, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0xb0, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2-bitperm" ]
+    expected:
+      insns:
+        -
+          asm_text: "bext z0.d, z1.d, z31.d"
diff --git a/tests/MC/AArch64/SVE2/bgrp.s.yaml b/tests/MC/AArch64/SVE2/bgrp.s.yaml
new file mode 100644
index 000000000..313af6498
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/bgrp.s.yaml
@@ -0,0 +1,40 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0xb8, 0x1f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2-bitperm" ]
+    expected:
+      insns:
+        -
+          asm_text: "bgrp z0.b, z1.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0xb8, 0x5f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2-bitperm" ]
+    expected:
+      insns:
+        -
+          asm_text: "bgrp z0.h, z1.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0xb8, 0x9f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2-bitperm" ]
+    expected:
+      insns:
+        -
+          asm_text: "bgrp z0.s, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0xb8, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2-bitperm" ]
+    expected:
+      insns:
+        -
+          asm_text: "bgrp z0.d, z1.d, z31.d"
diff --git a/tests/MC/AArch64/SVE2/bsl.s.yaml b/tests/MC/AArch64/SVE2/bsl.s.yaml
new file mode 100644
index 000000000..2418e8e0a
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/bsl.s.yaml
@@ -0,0 +1,60 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x40, 0x3c, 0x21, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bsl z0.d, z0.d, z1.d, z2.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z7"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x3f, 0x3e, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bsl z31.d, z31.d, z30.d, z29.d"
+
+  -
+    input:
+      bytes: [ 0x40, 0x3c, 0x21, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "bsl z0.d, z0.d, z1.d, z2.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z7"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x3f, 0x3e, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "bsl z31.d, z31.d, z30.d, z29.d"
diff --git a/tests/MC/AArch64/SVE2/bsl1n.s.yaml b/tests/MC/AArch64/SVE2/bsl1n.s.yaml
new file mode 100644
index 000000000..b26c075e9
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/bsl1n.s.yaml
@@ -0,0 +1,60 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x40, 0x3c, 0x61, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bsl1n z0.d, z0.d, z1.d, z2.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z7"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x3f, 0x7e, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bsl1n z31.d, z31.d, z30.d, z29.d"
+
+  -
+    input:
+      bytes: [ 0x40, 0x3c, 0x61, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "bsl1n z0.d, z0.d, z1.d, z2.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z7"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x3f, 0x7e, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "bsl1n z31.d, z31.d, z30.d, z29.d"
diff --git a/tests/MC/AArch64/SVE2/bsl2n.s.yaml b/tests/MC/AArch64/SVE2/bsl2n.s.yaml
new file mode 100644
index 000000000..eeb01b401
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/bsl2n.s.yaml
@@ -0,0 +1,60 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x40, 0x3c, 0xa1, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bsl2n z0.d, z0.d, z1.d, z2.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z7"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x3f, 0xbe, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bsl2n z31.d, z31.d, z30.d, z29.d"
+
+  -
+    input:
+      bytes: [ 0x40, 0x3c, 0xa1, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "bsl2n z0.d, z0.d, z1.d, z2.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z7"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x3f, 0xbe, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "bsl2n z31.d, z31.d, z30.d, z29.d"
diff --git a/tests/MC/AArch64/SVE2/cadd.s.yaml b/tests/MC/AArch64/SVE2/cadd.s.yaml
new file mode 100644
index 000000000..4e4efbcfb
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/cadd.s.yaml
@@ -0,0 +1,200 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xd8, 0x00, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "cadd z0.b, z0.b, z0.b, #90"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd8, 0x40, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "cadd z0.h, z0.h, z0.h, #90"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd8, 0x80, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "cadd z0.s, z0.s, z0.s, #90"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd8, 0xc0, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "cadd z0.d, z0.d, z0.d, #90"
+
+  -
+    input:
+      bytes: [ 0xff, 0xdf, 0x00, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "cadd z31.b, z31.b, z31.b, #270"
+
+  -
+    input:
+      bytes: [ 0xff, 0xdf, 0x40, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "cadd z31.h, z31.h, z31.h, #270"
+
+  -
+    input:
+      bytes: [ 0xff, 0xdf, 0x80, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "cadd z31.s, z31.s, z31.s, #270"
+
+  -
+    input:
+      bytes: [ 0xff, 0xdf, 0xc0, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "cadd z31.d, z31.d, z31.d, #270"
+
+  -
+    input:
+      bytes: [ 0xc4, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4, z6"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xdf, 0xc0, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "cadd z4.d, z4.d, z31.d, #270"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd8, 0x00, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cadd z0.b, z0.b, z0.b, #90"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd8, 0x40, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cadd z0.h, z0.h, z0.h, #90"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd8, 0x80, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cadd z0.s, z0.s, z0.s, #90"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd8, 0xc0, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cadd z0.d, z0.d, z0.d, #90"
+
+  -
+    input:
+      bytes: [ 0xff, 0xdf, 0x00, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cadd z31.b, z31.b, z31.b, #270"
+
+  -
+    input:
+      bytes: [ 0xff, 0xdf, 0x40, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cadd z31.h, z31.h, z31.h, #270"
+
+  -
+    input:
+      bytes: [ 0xff, 0xdf, 0x80, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cadd z31.s, z31.s, z31.s, #270"
+
+  -
+    input:
+      bytes: [ 0xff, 0xdf, 0xc0, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cadd z31.d, z31.d, z31.d, #270"
+
+  -
+    input:
+      bytes: [ 0xc4, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4, z6"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xdf, 0xc0, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cadd z4.d, z4.d, z31.d, #270"
diff --git a/tests/MC/AArch64/SVE2/cdot.s.yaml b/tests/MC/AArch64/SVE2/cdot.s.yaml
new file mode 100644
index 000000000..71b0432c1
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/cdot.s.yaml
@@ -0,0 +1,280 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x10, 0x9f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "cdot z0.s, z1.b, z31.b, #0"
+
+  -
+    input:
+      bytes: [ 0x20, 0x10, 0xdf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "cdot z0.d, z1.h, z31.h, #0"
+
+  -
+    input:
+      bytes: [ 0x20, 0x14, 0xdf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "cdot z0.d, z1.h, z31.h, #90"
+
+  -
+    input:
+      bytes: [ 0x20, 0x18, 0xdf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "cdot z0.d, z1.h, z31.h, #180"
+
+  -
+    input:
+      bytes: [ 0x20, 0x1c, 0xdf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "cdot z0.d, z1.h, z31.h, #270"
+
+  -
+    input:
+      bytes: [ 0x20, 0x40, 0xbf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "cdot z0.s, z1.b, z7.b[3], #0"
+
+  -
+    input:
+      bytes: [ 0x20, 0x40, 0xff, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "cdot z0.d, z1.h, z15.h[1], #0"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x44, 0xe3, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "cdot z5.d, z6.h, z3.h[0], #90"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x4b, 0xe0, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "cdot z29.d, z30.h, z0.h[0], #180"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x4f, 0xf7, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "cdot z31.d, z30.h, z7.h[1], #270"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x20, 0x10, 0xdf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "cdot z0.d, z1.h, z31.h, #0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x20, 0x40, 0xff, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "cdot z0.d, z1.h, z15.h[1], #0"
+
+  -
+    input:
+      bytes: [ 0x20, 0x10, 0x9f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cdot z0.s, z1.b, z31.b, #0"
+
+  -
+    input:
+      bytes: [ 0x20, 0x10, 0xdf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cdot z0.d, z1.h, z31.h, #0"
+
+  -
+    input:
+      bytes: [ 0x20, 0x14, 0xdf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cdot z0.d, z1.h, z31.h, #90"
+
+  -
+    input:
+      bytes: [ 0x20, 0x18, 0xdf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cdot z0.d, z1.h, z31.h, #180"
+
+  -
+    input:
+      bytes: [ 0x20, 0x1c, 0xdf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cdot z0.d, z1.h, z31.h, #270"
+
+  -
+    input:
+      bytes: [ 0x20, 0x40, 0xbf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cdot z0.s, z1.b, z7.b[3], #0"
+
+  -
+    input:
+      bytes: [ 0x20, 0x40, 0xff, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cdot z0.d, z1.h, z15.h[1], #0"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x44, 0xe3, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cdot z5.d, z6.h, z3.h[0], #90"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x4b, 0xe0, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cdot z29.d, z30.h, z0.h[0], #180"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x4f, 0xf7, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cdot z31.d, z30.h, z7.h[1], #270"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x20, 0x10, 0xdf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cdot z0.d, z1.h, z31.h, #0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x20, 0x40, 0xff, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cdot z0.d, z1.h, z15.h[1], #0"
diff --git a/tests/MC/AArch64/SVE2/cmla.s.yaml b/tests/MC/AArch64/SVE2/cmla.s.yaml
new file mode 100644
index 000000000..a89487f4a
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/cmla.s.yaml
@@ -0,0 +1,480 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x20, 0x02, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmla z0.b, z1.b, z2.b, #0"
+
+  -
+    input:
+      bytes: [ 0x20, 0x20, 0x42, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmla z0.h, z1.h, z2.h, #0"
+
+  -
+    input:
+      bytes: [ 0x20, 0x20, 0x82, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmla z0.s, z1.s, z2.s, #0"
+
+  -
+    input:
+      bytes: [ 0x20, 0x20, 0xc2, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmla z0.d, z1.d, z2.d, #0"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x27, 0x1f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmla z29.b, z30.b, z31.b, #90"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x27, 0x5f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmla z29.h, z30.h, z31.h, #90"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x27, 0x9f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmla z29.s, z30.s, z31.s, #90"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x27, 0xdf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmla z29.d, z30.d, z31.d, #90"
+
+  -
+    input:
+      bytes: [ 0xff, 0x2b, 0x1f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmla z31.b, z31.b, z31.b, #180"
+
+  -
+    input:
+      bytes: [ 0xff, 0x2b, 0x5f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmla z31.h, z31.h, z31.h, #180"
+
+  -
+    input:
+      bytes: [ 0xff, 0x2b, 0x9f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmla z31.s, z31.s, z31.s, #180"
+
+  -
+    input:
+      bytes: [ 0xff, 0x2b, 0xdf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmla z31.d, z31.d, z31.d, #180"
+
+  -
+    input:
+      bytes: [ 0x0f, 0x2e, 0x11, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmla z15.b, z16.b, z17.b, #270"
+
+  -
+    input:
+      bytes: [ 0x0f, 0x2e, 0x51, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmla z15.h, z16.h, z17.h, #270"
+
+  -
+    input:
+      bytes: [ 0x0f, 0x2e, 0x91, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmla z15.s, z16.s, z17.s, #270"
+
+  -
+    input:
+      bytes: [ 0x0f, 0x2e, 0xd1, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmla z15.d, z16.d, z17.d, #270"
+
+  -
+    input:
+      bytes: [ 0x20, 0x60, 0xa2, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmla z0.h, z1.h, z2.h[0], #0"
+
+  -
+    input:
+      bytes: [ 0x20, 0x60, 0xe2, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmla z0.s, z1.s, z2.s[0], #0"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x6b, 0xa7, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmla z31.h, z30.h, z7.h[0], #180"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x6b, 0xe7, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmla z31.s, z30.s, z7.s[0], #180"
+
+  -
+    input:
+      bytes: [ 0xc4, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4, z6"
+
+  -
+    input:
+      bytes: [ 0xe4, 0x2f, 0xdf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmla z4.d, z31.d, z31.d, #270"
+
+  -
+    input:
+      bytes: [ 0x95, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z21, z28"
+
+  -
+    input:
+      bytes: [ 0x55, 0x65, 0xf5, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmla z21.s, z10.s, z5.s[1], #90"
+
+  -
+    input:
+      bytes: [ 0x20, 0x20, 0x02, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmla z0.b, z1.b, z2.b, #0"
+
+  -
+    input:
+      bytes: [ 0x20, 0x20, 0x42, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmla z0.h, z1.h, z2.h, #0"
+
+  -
+    input:
+      bytes: [ 0x20, 0x20, 0x82, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmla z0.s, z1.s, z2.s, #0"
+
+  -
+    input:
+      bytes: [ 0x20, 0x20, 0xc2, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmla z0.d, z1.d, z2.d, #0"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x27, 0x1f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmla z29.b, z30.b, z31.b, #90"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x27, 0x5f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmla z29.h, z30.h, z31.h, #90"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x27, 0x9f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmla z29.s, z30.s, z31.s, #90"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x27, 0xdf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmla z29.d, z30.d, z31.d, #90"
+
+  -
+    input:
+      bytes: [ 0xff, 0x2b, 0x1f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmla z31.b, z31.b, z31.b, #180"
+
+  -
+    input:
+      bytes: [ 0xff, 0x2b, 0x5f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmla z31.h, z31.h, z31.h, #180"
+
+  -
+    input:
+      bytes: [ 0xff, 0x2b, 0x9f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmla z31.s, z31.s, z31.s, #180"
+
+  -
+    input:
+      bytes: [ 0xff, 0x2b, 0xdf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmla z31.d, z31.d, z31.d, #180"
+
+  -
+    input:
+      bytes: [ 0x0f, 0x2e, 0x11, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmla z15.b, z16.b, z17.b, #270"
+
+  -
+    input:
+      bytes: [ 0x0f, 0x2e, 0x51, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmla z15.h, z16.h, z17.h, #270"
+
+  -
+    input:
+      bytes: [ 0x0f, 0x2e, 0x91, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmla z15.s, z16.s, z17.s, #270"
+
+  -
+    input:
+      bytes: [ 0x0f, 0x2e, 0xd1, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmla z15.d, z16.d, z17.d, #270"
+
+  -
+    input:
+      bytes: [ 0x20, 0x60, 0xa2, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmla z0.h, z1.h, z2.h[0], #0"
+
+  -
+    input:
+      bytes: [ 0x20, 0x60, 0xe2, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmla z0.s, z1.s, z2.s[0], #0"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x6b, 0xa7, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmla z31.h, z30.h, z7.h[0], #180"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x6b, 0xe7, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmla z31.s, z30.s, z7.s[0], #180"
+
+  -
+    input:
+      bytes: [ 0xc4, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4, z6"
+
+  -
+    input:
+      bytes: [ 0xe4, 0x2f, 0xdf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmla z4.d, z31.d, z31.d, #270"
+
+  -
+    input:
+      bytes: [ 0x95, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z21, z28"
+
+  -
+    input:
+      bytes: [ 0x55, 0x65, 0xf5, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmla z21.s, z10.s, z5.s[1], #90"
diff --git a/tests/MC/AArch64/SVE2/eor3.s.yaml b/tests/MC/AArch64/SVE2/eor3.s.yaml
new file mode 100644
index 000000000..c964b323a
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/eor3.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xfd, 0x3b, 0x3e, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "eor3 z29.d, z29.d, z30.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xfd, 0x3b, 0x3e, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "eor3 z29.d, z29.d, z30.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xfd, 0x3b, 0x3e, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "eor3 z29.d, z29.d, z30.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xfd, 0x3b, 0x3e, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "eor3 z29.d, z29.d, z30.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z7"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x3b, 0x3e, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "eor3 z31.d, z31.d, z30.d, z29.d"
+
+  -
+    input:
+      bytes: [ 0xfd, 0x3b, 0x3e, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "eor3 z29.d, z29.d, z30.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xfd, 0x3b, 0x3e, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "eor3 z29.d, z29.d, z30.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xfd, 0x3b, 0x3e, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "eor3 z29.d, z29.d, z30.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xfd, 0x3b, 0x3e, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "eor3 z29.d, z29.d, z30.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z7"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x3b, 0x3e, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "eor3 z31.d, z31.d, z30.d, z29.d"
diff --git a/tests/MC/AArch64/SVE2/eorbt.s.yaml b/tests/MC/AArch64/SVE2/eorbt.s.yaml
new file mode 100644
index 000000000..982e68b50
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/eorbt.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x90, 0x1f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "eorbt z0.b, z1.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x90, 0x5f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "eorbt z0.h, z1.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x90, 0x9f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "eorbt z0.s, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x90, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "eorbt z0.d, z1.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x20, 0x90, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "eorbt z0.d, z1.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x90, 0x1f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "eorbt z0.b, z1.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x90, 0x5f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "eorbt z0.h, z1.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x90, 0x9f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "eorbt z0.s, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x90, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "eorbt z0.d, z1.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x20, 0x90, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "eorbt z0.d, z1.d, z31.d"
diff --git a/tests/MC/AArch64/SVE2/eortb.s.yaml b/tests/MC/AArch64/SVE2/eortb.s.yaml
new file mode 100644
index 000000000..a60ee99ec
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/eortb.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x94, 0x1f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "eortb z0.b, z1.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x94, 0x5f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "eortb z0.h, z1.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x94, 0x9f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "eortb z0.s, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x94, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "eortb z0.d, z1.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x20, 0x94, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "eortb z0.d, z1.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x94, 0x1f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "eortb z0.b, z1.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x94, 0x5f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "eortb z0.h, z1.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x94, 0x9f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "eortb z0.s, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x94, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "eortb z0.d, z1.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x20, 0x94, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "eortb z0.d, z1.d, z31.d"
diff --git a/tests/MC/AArch64/SVE2/ext.s.yaml b/tests/MC/AArch64/SVE2/ext.s.yaml
new file mode 100644
index 000000000..1a0f647e2
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/ext.s.yaml
@@ -0,0 +1,40 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x00, 0x60, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ext z0.b, { z1.b, z2.b }, #0"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x1f, 0x7f, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ext z31.b, { z30.b, z31.b }, #255"
+
+  -
+    input:
+      bytes: [ 0x20, 0x00, 0x60, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ext z0.b, { z1.b, z2.b }, #0"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x1f, 0x7f, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ext z31.b, { z30.b, z31.b }, #255"
diff --git a/tests/MC/AArch64/SVE2/faddp.s.yaml b/tests/MC/AArch64/SVE2/faddp.s.yaml
new file mode 100644
index 000000000..44392e50a
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/faddp.s.yaml
@@ -0,0 +1,140 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x50, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "faddp z0.h, p0/m, z0.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x8f, 0x90, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "faddp z29.s, p3/m, z29.s, z30.s"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xd0, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "faddp z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31.d, p0/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x83, 0xd0, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "faddp z31.d, p0/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xd0, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "faddp z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x50, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "faddp z0.h, p0/m, z0.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x8f, 0x90, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "faddp z29.s, p3/m, z29.s, z30.s"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xd0, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "faddp z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31.d, p0/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x83, 0xd0, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "faddp z31.d, p0/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xd0, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "faddp z31.d, p7/m, z31.d, z30.d"
diff --git a/tests/MC/AArch64/SVE2/fcvtlt.s.yaml b/tests/MC/AArch64/SVE2/fcvtlt.s.yaml
new file mode 100644
index 000000000..43bdb9807
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/fcvtlt.s.yaml
@@ -0,0 +1,40 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0xa0, 0x89, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtlt z0.s, p0/m, z1.h"
+
+  -
+    input:
+      bytes: [ 0xfe, 0xbf, 0xcb, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtlt z30.d, p7/m, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa0, 0x89, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtlt z0.s, p0/m, z1.h"
+
+  -
+    input:
+      bytes: [ 0xfe, 0xbf, 0xcb, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtlt z30.d, p7/m, z31.s"
diff --git a/tests/MC/AArch64/SVE2/fcvtnt.s.yaml b/tests/MC/AArch64/SVE2/fcvtnt.s.yaml
new file mode 100644
index 000000000..d89c1c160
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/fcvtnt.s.yaml
@@ -0,0 +1,40 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0xa0, 0x88, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtnt z0.h, p0/m, z1.s"
+
+  -
+    input:
+      bytes: [ 0xfe, 0xbf, 0xca, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtnt z30.s, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa0, 0x88, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtnt z0.h, p0/m, z1.s"
+
+  -
+    input:
+      bytes: [ 0xfe, 0xbf, 0xca, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtnt z30.s, p7/m, z31.d"
diff --git a/tests/MC/AArch64/SVE2/fcvtx.s.yaml b/tests/MC/AArch64/SVE2/fcvtx.s.yaml
new file mode 100644
index 000000000..ebdea6563
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/fcvtx.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x0a, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtx z0.s, p0/m, z0.d"
+
+  -
+    input:
+      bytes: [ 0xfe, 0xbf, 0x0a, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtx z30.s, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe5, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z5.d, p0/z, z7.d"
+
+  -
+    input:
+      bytes: [ 0x05, 0xa0, 0x0a, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtx z5.s, p0/m, z0.d"
+
+  -
+    input:
+      bytes: [ 0xe5, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z5, z7"
+
+  -
+    input:
+      bytes: [ 0x05, 0xa0, 0x0a, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtx z5.s, p0/m, z0.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x0a, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtx z0.s, p0/m, z0.d"
+
+  -
+    input:
+      bytes: [ 0xfe, 0xbf, 0x0a, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtx z30.s, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe5, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z5.d, p0/z, z7.d"
+
+  -
+    input:
+      bytes: [ 0x05, 0xa0, 0x0a, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtx z5.s, p0/m, z0.d"
+
+  -
+    input:
+      bytes: [ 0xe5, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z5, z7"
+
+  -
+    input:
+      bytes: [ 0x05, 0xa0, 0x0a, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtx z5.s, p0/m, z0.d"
diff --git a/tests/MC/AArch64/SVE2/fcvtxnt.s.yaml b/tests/MC/AArch64/SVE2/fcvtxnt.s.yaml
new file mode 100644
index 000000000..69be85bad
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/fcvtxnt.s.yaml
@@ -0,0 +1,40 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0xa0, 0x0a, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtxnt z0.s, p0/m, z1.d"
+
+  -
+    input:
+      bytes: [ 0xfe, 0xbf, 0x0a, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtxnt z30.s, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa0, 0x0a, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtxnt z0.s, p0/m, z1.d"
+
+  -
+    input:
+      bytes: [ 0xfe, 0xbf, 0x0a, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtxnt z30.s, p7/m, z31.d"
diff --git a/tests/MC/AArch64/SVE2/flogb.s.yaml b/tests/MC/AArch64/SVE2/flogb.s.yaml
new file mode 100644
index 000000000..a7dd8d5b1
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/flogb.s.yaml
@@ -0,0 +1,140 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x1a, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "flogb z31.h, p7/m, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x1c, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "flogb z31.s, p7/m, z31.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x1e, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "flogb z31.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4.d, p7/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xbf, 0x1e, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "flogb z4.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4, z6"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xbf, 0x1e, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "flogb z4.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x1a, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "flogb z31.h, p7/m, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x1c, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "flogb z31.s, p7/m, z31.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x1e, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "flogb z31.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0x3c, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4.d, p7/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xbf, 0x1e, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "flogb z4.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4, z6"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xbf, 0x1e, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "flogb z4.d, p7/m, z31.d"
diff --git a/tests/MC/AArch64/SVE2/fmaxnmp.s.yaml b/tests/MC/AArch64/SVE2/fmaxnmp.s.yaml
new file mode 100644
index 000000000..bf027df71
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/fmaxnmp.s.yaml
@@ -0,0 +1,140 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x54, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnmp z0.h, p0/m, z0.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x8f, 0x94, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnmp z29.s, p3/m, z29.s, z30.s"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xd4, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnmp z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31.d, p0/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x83, 0xd4, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnmp z31.d, p0/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xd4, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnmp z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x54, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnmp z0.h, p0/m, z0.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x8f, 0x94, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnmp z29.s, p3/m, z29.s, z30.s"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xd4, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnmp z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31.d, p0/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x83, 0xd4, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnmp z31.d, p0/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xd4, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnmp z31.d, p7/m, z31.d, z30.d"
diff --git a/tests/MC/AArch64/SVE2/fmaxp.s.yaml b/tests/MC/AArch64/SVE2/fmaxp.s.yaml
new file mode 100644
index 000000000..7c3d89fa9
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/fmaxp.s.yaml
@@ -0,0 +1,140 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x56, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxp z0.h, p0/m, z0.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x8f, 0x96, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxp z29.s, p3/m, z29.s, z30.s"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xd6, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxp z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31.d, p0/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x83, 0xd6, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxp z31.d, p0/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xd6, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxp z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x56, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxp z0.h, p0/m, z0.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x8f, 0x96, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxp z29.s, p3/m, z29.s, z30.s"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xd6, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxp z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31.d, p0/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x83, 0xd6, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxp z31.d, p0/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xd6, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxp z31.d, p7/m, z31.d, z30.d"
diff --git a/tests/MC/AArch64/SVE2/fminnmp.s.yaml b/tests/MC/AArch64/SVE2/fminnmp.s.yaml
new file mode 100644
index 000000000..0e17c4887
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/fminnmp.s.yaml
@@ -0,0 +1,140 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x55, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnmp z0.h, p0/m, z0.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x8f, 0x95, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnmp z29.s, p3/m, z29.s, z30.s"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xd5, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnmp z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31.d, p0/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x83, 0xd5, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnmp z31.d, p0/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xd5, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnmp z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x55, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnmp z0.h, p0/m, z0.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x8f, 0x95, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnmp z29.s, p3/m, z29.s, z30.s"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xd5, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnmp z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31.d, p0/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x83, 0xd5, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnmp z31.d, p0/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xd5, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnmp z31.d, p7/m, z31.d, z30.d"
diff --git a/tests/MC/AArch64/SVE2/fminp.s.yaml b/tests/MC/AArch64/SVE2/fminp.s.yaml
new file mode 100644
index 000000000..fac5dda79
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/fminp.s.yaml
@@ -0,0 +1,140 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x57, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminp z0.h, p0/m, z0.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x8f, 0x97, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminp z29.s, p3/m, z29.s, z30.s"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xd7, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminp z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31.d, p0/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x83, 0xd7, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminp z31.d, p0/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xd7, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminp z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x57, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminp z0.h, p0/m, z0.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x8f, 0x97, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminp z29.s, p3/m, z29.s, z30.s"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xd7, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminp z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31.d, p0/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x83, 0xd7, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminp z31.d, p0/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xd7, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminp z31.d, p7/m, z31.d, z30.d"
diff --git a/tests/MC/AArch64/SVE2/fmlalb.s.yaml b/tests/MC/AArch64/SVE2/fmlalb.s.yaml
new file mode 100644
index 000000000..f4507ee0e
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/fmlalb.s.yaml
@@ -0,0 +1,140 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xdd, 0x83, 0xbf, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlalb z29.s, z30.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x40, 0xa7, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlalb z0.s, z1.h, z7.h[0]"
+
+  -
+    input:
+      bytes: [ 0xfe, 0x4b, 0xbf, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlalb z30.s, z31.h, z7.h[7]"
+
+  -
+    input:
+      bytes: [ 0x9d, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z29, z28"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x83, 0xbf, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlalb z29.s, z30.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x95, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z21, z28"
+
+  -
+    input:
+      bytes: [ 0x35, 0x48, 0xbf, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlalb z21.s, z1.h, z7.h[7]"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x83, 0xbf, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlalb z29.s, z30.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x40, 0xa7, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlalb z0.s, z1.h, z7.h[0]"
+
+  -
+    input:
+      bytes: [ 0xfe, 0x4b, 0xbf, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlalb z30.s, z31.h, z7.h[7]"
+
+  -
+    input:
+      bytes: [ 0x9d, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z29, z28"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x83, 0xbf, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlalb z29.s, z30.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x95, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z21, z28"
+
+  -
+    input:
+      bytes: [ 0x35, 0x48, 0xbf, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlalb z21.s, z1.h, z7.h[7]"
diff --git a/tests/MC/AArch64/SVE2/fmlalt.s.yaml b/tests/MC/AArch64/SVE2/fmlalt.s.yaml
new file mode 100644
index 000000000..352c87da5
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/fmlalt.s.yaml
@@ -0,0 +1,140 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xdd, 0x87, 0xbf, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlalt z29.s, z30.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x44, 0xa7, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlalt z0.s, z1.h, z7.h[0]"
+
+  -
+    input:
+      bytes: [ 0xfe, 0x4f, 0xbf, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlalt z30.s, z31.h, z7.h[7]"
+
+  -
+    input:
+      bytes: [ 0x9d, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z29, z28"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x87, 0xbf, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlalt z29.s, z30.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x95, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z21, z28"
+
+  -
+    input:
+      bytes: [ 0x35, 0x4c, 0xbf, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlalt z21.s, z1.h, z7.h[7]"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x87, 0xbf, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlalt z29.s, z30.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x44, 0xa7, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlalt z0.s, z1.h, z7.h[0]"
+
+  -
+    input:
+      bytes: [ 0xfe, 0x4f, 0xbf, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlalt z30.s, z31.h, z7.h[7]"
+
+  -
+    input:
+      bytes: [ 0x9d, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z29, z28"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x87, 0xbf, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlalt z29.s, z30.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x95, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z21, z28"
+
+  -
+    input:
+      bytes: [ 0x35, 0x4c, 0xbf, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlalt z21.s, z1.h, z7.h[7]"
diff --git a/tests/MC/AArch64/SVE2/fmlslb.s.yaml b/tests/MC/AArch64/SVE2/fmlslb.s.yaml
new file mode 100644
index 000000000..3b43e7c34
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/fmlslb.s.yaml
@@ -0,0 +1,140 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xdd, 0xa3, 0xbf, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlslb z29.s, z30.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x60, 0xa7, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlslb z0.s, z1.h, z7.h[0]"
+
+  -
+    input:
+      bytes: [ 0xfe, 0x6b, 0xbf, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlslb z30.s, z31.h, z7.h[7]"
+
+  -
+    input:
+      bytes: [ 0x9d, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z29, z28"
+
+  -
+    input:
+      bytes: [ 0xdd, 0xa3, 0xbf, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlslb z29.s, z30.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x95, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z21, z28"
+
+  -
+    input:
+      bytes: [ 0x35, 0x68, 0xbf, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlslb z21.s, z1.h, z7.h[7]"
+
+  -
+    input:
+      bytes: [ 0xdd, 0xa3, 0xbf, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlslb z29.s, z30.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x60, 0xa7, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlslb z0.s, z1.h, z7.h[0]"
+
+  -
+    input:
+      bytes: [ 0xfe, 0x6b, 0xbf, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlslb z30.s, z31.h, z7.h[7]"
+
+  -
+    input:
+      bytes: [ 0x9d, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z29, z28"
+
+  -
+    input:
+      bytes: [ 0xdd, 0xa3, 0xbf, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlslb z29.s, z30.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x95, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z21, z28"
+
+  -
+    input:
+      bytes: [ 0x35, 0x68, 0xbf, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlslb z21.s, z1.h, z7.h[7]"
diff --git a/tests/MC/AArch64/SVE2/fmlslt.s.yaml b/tests/MC/AArch64/SVE2/fmlslt.s.yaml
new file mode 100644
index 000000000..328406a2f
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/fmlslt.s.yaml
@@ -0,0 +1,140 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xdd, 0xa7, 0xbf, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlslt z29.s, z30.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x64, 0xa7, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlslt z0.s, z1.h, z7.h[0]"
+
+  -
+    input:
+      bytes: [ 0xfe, 0x6f, 0xbf, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlslt z30.s, z31.h, z7.h[7]"
+
+  -
+    input:
+      bytes: [ 0x9d, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z29, z28"
+
+  -
+    input:
+      bytes: [ 0xdd, 0xa7, 0xbf, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlslt z29.s, z30.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x95, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z21, z28"
+
+  -
+    input:
+      bytes: [ 0x35, 0x6c, 0xbf, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlslt z21.s, z1.h, z7.h[7]"
+
+  -
+    input:
+      bytes: [ 0xdd, 0xa7, 0xbf, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlslt z29.s, z30.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x64, 0xa7, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlslt z0.s, z1.h, z7.h[0]"
+
+  -
+    input:
+      bytes: [ 0xfe, 0x6f, 0xbf, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlslt z30.s, z31.h, z7.h[7]"
+
+  -
+    input:
+      bytes: [ 0x9d, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z29, z28"
+
+  -
+    input:
+      bytes: [ 0xdd, 0xa7, 0xbf, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlslt z29.s, z30.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x95, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z21, z28"
+
+  -
+    input:
+      bytes: [ 0x35, 0x6c, 0xbf, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlslt z21.s, z1.h, z7.h[7]"
diff --git a/tests/MC/AArch64/SVE2/histcnt.s.yaml b/tests/MC/AArch64/SVE2/histcnt.s.yaml
new file mode 100644
index 000000000..dc9b9c36c
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/histcnt.s.yaml
@@ -0,0 +1,20 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0xc0, 0xa2, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "histcnt z0.s, p0/z, z1.s, z2.s"
+
+  -
+    input:
+      bytes: [ 0xdd, 0xdf, 0xff, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "histcnt z29.d, p7/z, z30.d, z31.d"
diff --git a/tests/MC/AArch64/SVE2/histseg.s.yaml b/tests/MC/AArch64/SVE2/histseg.s.yaml
new file mode 100644
index 000000000..ebb249852
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/histseg.s.yaml
@@ -0,0 +1,10 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0xa0, 0x3f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "histseg z0.b, z1.b, z31.b"
diff --git a/tests/MC/AArch64/SVE2/ldnt1b.s.yaml b/tests/MC/AArch64/SVE2/ldnt1b.s.yaml
new file mode 100644
index 000000000..334e40444
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/ldnt1b.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0xa0, 0x1f, 0x84 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1b { z0.s }, p0/z, [z1.s]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x1f, 0x84 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1b { z31.s }, p7/z, [z31.s]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x00, 0x84 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1b { z31.s }, p7/z, [z31.s, x0]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc0, 0x1f, 0xc4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1b { z0.d }, p0/z, [z1.d]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xdf, 0x1f, 0xc4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1b { z31.d }, p7/z, [z31.d]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xdf, 0x00, 0xc4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1b { z31.d }, p7/z, [z31.d, x0]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa0, 0x1f, 0x84 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1b { z0.s }, p0/z, [z1.s]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x1f, 0x84 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1b { z31.s }, p7/z, [z31.s]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x00, 0x84 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1b { z31.s }, p7/z, [z31.s, x0]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc0, 0x1f, 0xc4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1b { z0.d }, p0/z, [z1.d]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xdf, 0x1f, 0xc4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1b { z31.d }, p7/z, [z31.d]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xdf, 0x00, 0xc4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1b { z31.d }, p7/z, [z31.d, x0]"
diff --git a/tests/MC/AArch64/SVE2/ldnt1d.s.yaml b/tests/MC/AArch64/SVE2/ldnt1d.s.yaml
new file mode 100644
index 000000000..7b0cfefa2
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/ldnt1d.s.yaml
@@ -0,0 +1,60 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0xc0, 0x9f, 0xc5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1d { z0.d }, p0/z, [z1.d]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xdf, 0x9f, 0xc5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1d { z31.d }, p7/z, [z31.d]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xdf, 0x80, 0xc5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1d { z31.d }, p7/z, [z31.d, x0]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc0, 0x9f, 0xc5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1d { z0.d }, p0/z, [z1.d]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xdf, 0x9f, 0xc5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1d { z31.d }, p7/z, [z31.d]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xdf, 0x80, 0xc5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1d { z31.d }, p7/z, [z31.d, x0]"
diff --git a/tests/MC/AArch64/SVE2/ldnt1h.s.yaml b/tests/MC/AArch64/SVE2/ldnt1h.s.yaml
new file mode 100644
index 000000000..900a32ce9
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/ldnt1h.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0xa0, 0x9f, 0x84 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1h { z0.s }, p0/z, [z1.s]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x9f, 0x84 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1h { z31.s }, p7/z, [z31.s]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x80, 0x84 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1h { z31.s }, p7/z, [z31.s, x0]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc0, 0x9f, 0xc4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1h { z0.d }, p0/z, [z1.d]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xdf, 0x9f, 0xc4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1h { z31.d }, p7/z, [z31.d]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xdf, 0x80, 0xc4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1h { z31.d }, p7/z, [z31.d, x0]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa0, 0x9f, 0x84 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1h { z0.s }, p0/z, [z1.s]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x9f, 0x84 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1h { z31.s }, p7/z, [z31.s]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x80, 0x84 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1h { z31.s }, p7/z, [z31.s, x0]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc0, 0x9f, 0xc4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1h { z0.d }, p0/z, [z1.d]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xdf, 0x9f, 0xc4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1h { z31.d }, p7/z, [z31.d]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xdf, 0x80, 0xc4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1h { z31.d }, p7/z, [z31.d, x0]"
diff --git a/tests/MC/AArch64/SVE2/ldnt1sb.s.yaml b/tests/MC/AArch64/SVE2/ldnt1sb.s.yaml
new file mode 100644
index 000000000..3c2db793f
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/ldnt1sb.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x1f, 0x84 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1sb { z0.s }, p0/z, [z1.s]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x9f, 0x1f, 0x84 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1sb { z31.s }, p7/z, [z31.s]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x9f, 0x00, 0x84 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1sb { z31.s }, p7/z, [z31.s, x0]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x1f, 0xc4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1sb { z0.d }, p0/z, [z1.d]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x9f, 0x1f, 0xc4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1sb { z31.d }, p7/z, [z31.d]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x9f, 0x00, 0xc4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1sb { z31.d }, p7/z, [z31.d, x0]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x1f, 0x84 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1sb { z0.s }, p0/z, [z1.s]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x9f, 0x1f, 0x84 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1sb { z31.s }, p7/z, [z31.s]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x9f, 0x00, 0x84 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1sb { z31.s }, p7/z, [z31.s, x0]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x1f, 0xc4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1sb { z0.d }, p0/z, [z1.d]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x9f, 0x1f, 0xc4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1sb { z31.d }, p7/z, [z31.d]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x9f, 0x00, 0xc4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1sb { z31.d }, p7/z, [z31.d, x0]"
diff --git a/tests/MC/AArch64/SVE2/ldnt1sh.s.yaml b/tests/MC/AArch64/SVE2/ldnt1sh.s.yaml
new file mode 100644
index 000000000..4e665de6e
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/ldnt1sh.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x9f, 0x84 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1sh { z0.s }, p0/z, [z1.s]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x9f, 0x9f, 0x84 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1sh { z31.s }, p7/z, [z31.s]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x9f, 0x80, 0x84 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1sh { z31.s }, p7/z, [z31.s, x0]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x9f, 0xc4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1sh { z0.d }, p0/z, [z1.d]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x9f, 0x9f, 0xc4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1sh { z31.d }, p7/z, [z31.d]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x9f, 0x80, 0xc4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1sh { z31.d }, p7/z, [z31.d, x0]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x9f, 0x84 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1sh { z0.s }, p0/z, [z1.s]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x9f, 0x9f, 0x84 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1sh { z31.s }, p7/z, [z31.s]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x9f, 0x80, 0x84 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1sh { z31.s }, p7/z, [z31.s, x0]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x9f, 0xc4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1sh { z0.d }, p0/z, [z1.d]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x9f, 0x9f, 0xc4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1sh { z31.d }, p7/z, [z31.d]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x9f, 0x80, 0xc4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1sh { z31.d }, p7/z, [z31.d, x0]"
diff --git a/tests/MC/AArch64/SVE2/ldnt1sw.s.yaml b/tests/MC/AArch64/SVE2/ldnt1sw.s.yaml
new file mode 100644
index 000000000..aca6b0219
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/ldnt1sw.s.yaml
@@ -0,0 +1,60 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x1f, 0xc5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1sw { z0.d }, p0/z, [z1.d]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x9f, 0x1f, 0xc5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1sw { z31.d }, p7/z, [z31.d]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x9f, 0x00, 0xc5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1sw { z31.d }, p7/z, [z31.d, x0]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x1f, 0xc5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1sw { z0.d }, p0/z, [z1.d]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x9f, 0x1f, 0xc5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1sw { z31.d }, p7/z, [z31.d]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x9f, 0x00, 0xc5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1sw { z31.d }, p7/z, [z31.d, x0]"
diff --git a/tests/MC/AArch64/SVE2/ldnt1w.s.yaml b/tests/MC/AArch64/SVE2/ldnt1w.s.yaml
new file mode 100644
index 000000000..62bcd561e
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/ldnt1w.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0xa0, 0x1f, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1w { z0.s }, p0/z, [z1.s]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x1f, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1w { z31.s }, p7/z, [z31.s]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x00, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1w { z31.s }, p7/z, [z31.s, x0]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc0, 0x1f, 0xc5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1w { z0.d }, p0/z, [z1.d]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xdf, 0x1f, 0xc5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1w { z31.d }, p7/z, [z31.d]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xdf, 0x00, 0xc5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1w { z31.d }, p7/z, [z31.d, x0]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa0, 0x1f, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1w { z0.s }, p0/z, [z1.s]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x1f, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1w { z31.s }, p7/z, [z31.s]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x00, 0x85 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1w { z31.s }, p7/z, [z31.s, x0]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc0, 0x1f, 0xc5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1w { z0.d }, p0/z, [z1.d]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xdf, 0x1f, 0xc5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1w { z31.d }, p7/z, [z31.d]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xdf, 0x00, 0xc5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1w { z31.d }, p7/z, [z31.d, x0]"
diff --git a/tests/MC/AArch64/SVE2/match.s.yaml b/tests/MC/AArch64/SVE2/match.s.yaml
new file mode 100644
index 000000000..47746efb5
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/match.s.yaml
@@ -0,0 +1,40 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x20, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "match p0.b, p0/z, z0.b, z0.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x60, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "match p0.h, p0/z, z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0xcf, 0x9f, 0x3f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "match p15.b, p7/z, z30.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0xcf, 0x9f, 0x7f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "match p15.h, p7/z, z30.h, z31.h"
diff --git a/tests/MC/AArch64/SVE2/mla.s.yaml b/tests/MC/AArch64/SVE2/mla.s.yaml
new file mode 100644
index 000000000..36bd77cef
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/mla.s.yaml
@@ -0,0 +1,100 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x08, 0x7f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mla z0.h, z1.h, z7.h[7]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x08, 0xbf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mla z0.s, z1.s, z7.s[3]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x08, 0xf7, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mla z0.d, z1.d, z7.d[1]"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x20, 0x08, 0xf7, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mla z0.d, z1.d, z7.d[1]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x08, 0x7f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mla z0.h, z1.h, z7.h[7]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x08, 0xbf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mla z0.s, z1.s, z7.s[3]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x08, 0xf7, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mla z0.d, z1.d, z7.d[1]"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x20, 0x08, 0xf7, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mla z0.d, z1.d, z7.d[1]"
diff --git a/tests/MC/AArch64/SVE2/mls.s.yaml b/tests/MC/AArch64/SVE2/mls.s.yaml
new file mode 100644
index 000000000..c50b569b9
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/mls.s.yaml
@@ -0,0 +1,100 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x0c, 0x7f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mls z0.h, z1.h, z7.h[7]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x0c, 0xbf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mls z0.s, z1.s, z7.s[3]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x0c, 0xf7, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mls z0.d, z1.d, z7.d[1]"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x20, 0x0c, 0xf7, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mls z0.d, z1.d, z7.d[1]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x0c, 0x7f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mls z0.h, z1.h, z7.h[7]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x0c, 0xbf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mls z0.s, z1.s, z7.s[3]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x0c, 0xf7, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mls z0.d, z1.d, z7.d[1]"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x20, 0x0c, 0xf7, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mls z0.d, z1.d, z7.d[1]"
diff --git a/tests/MC/AArch64/SVE2/mul.s.yaml b/tests/MC/AArch64/SVE2/mul.s.yaml
new file mode 100644
index 000000000..b0bbba9f7
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/mul.s.yaml
@@ -0,0 +1,140 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x60, 0x22, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul z0.b, z1.b, z2.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x60, 0x62, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul z0.h, z1.h, z2.h"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x63, 0xbf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul z29.s, z30.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0x63, 0xff, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul z31.d, z31.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf8, 0x7f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul z0.h, z1.h, z7.h[7]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf8, 0xbf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul z0.s, z1.s, z7.s[3]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf8, 0xff, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul z0.d, z1.d, z15.d[1]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x60, 0x22, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul z0.b, z1.b, z2.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x60, 0x62, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul z0.h, z1.h, z2.h"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x63, 0xbf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul z29.s, z30.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0x63, 0xff, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul z31.d, z31.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf8, 0x7f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul z0.h, z1.h, z7.h[7]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf8, 0xbf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul z0.s, z1.s, z7.s[3]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf8, 0xff, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul z0.d, z1.d, z15.d[1]"
diff --git a/tests/MC/AArch64/SVE2/nbsl.s.yaml b/tests/MC/AArch64/SVE2/nbsl.s.yaml
new file mode 100644
index 000000000..7d43f7487
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/nbsl.s.yaml
@@ -0,0 +1,60 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x40, 0x3c, 0xe1, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "nbsl z0.d, z0.d, z1.d, z2.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z7"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x3f, 0xfe, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "nbsl z31.d, z31.d, z30.d, z29.d"
+
+  -
+    input:
+      bytes: [ 0x40, 0x3c, 0xe1, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "nbsl z0.d, z0.d, z1.d, z2.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z7"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x3f, 0xfe, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "nbsl z31.d, z31.d, z30.d, z29.d"
diff --git a/tests/MC/AArch64/SVE2/nmatch.s.yaml b/tests/MC/AArch64/SVE2/nmatch.s.yaml
new file mode 100644
index 000000000..e979ac174
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/nmatch.s.yaml
@@ -0,0 +1,40 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x10, 0x80, 0x20, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "nmatch p0.b, p0/z, z0.b, z0.b"
+
+  -
+    input:
+      bytes: [ 0x10, 0x80, 0x60, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "nmatch p0.h, p0/z, z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0x3f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "nmatch p15.b, p7/z, z30.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0x7f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "nmatch p15.h, p7/z, z30.h, z31.h"
diff --git a/tests/MC/AArch64/SVE2/pmul.s.yaml b/tests/MC/AArch64/SVE2/pmul.s.yaml
new file mode 100644
index 000000000..89e1bc0d3
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/pmul.s.yaml
@@ -0,0 +1,40 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x64, 0x22, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "pmul z0.b, z1.b, z2.b"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x67, 0x3f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "pmul z29.b, z30.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x64, 0x22, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "pmul z0.b, z1.b, z2.b"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x67, 0x3f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "pmul z29.b, z30.b, z31.b"
diff --git a/tests/MC/AArch64/SVE2/pmullb-128.s.yaml b/tests/MC/AArch64/SVE2/pmullb-128.s.yaml
new file mode 100644
index 000000000..0d57cb0cd
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/pmullb-128.s.yaml
@@ -0,0 +1,10 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xdd, 0x6b, 0x1f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2-aes" ]
+    expected:
+      insns:
+        -
+          asm_text: "pmullb z29.q, z30.d, z31.d"
diff --git a/tests/MC/AArch64/SVE2/pmullb.s.yaml b/tests/MC/AArch64/SVE2/pmullb.s.yaml
new file mode 100644
index 000000000..7a3cbe97c
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/pmullb.s.yaml
@@ -0,0 +1,40 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x68, 0x42, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "pmullb z0.h, z1.b, z2.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x6b, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "pmullb z31.d, z31.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x68, 0x42, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "pmullb z0.h, z1.b, z2.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x6b, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "pmullb z31.d, z31.s, z31.s"
diff --git a/tests/MC/AArch64/SVE2/pmullt-128.s.yaml b/tests/MC/AArch64/SVE2/pmullt-128.s.yaml
new file mode 100644
index 000000000..aa8aa4b5f
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/pmullt-128.s.yaml
@@ -0,0 +1,10 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xdd, 0x6f, 0x1f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2-aes" ]
+    expected:
+      insns:
+        -
+          asm_text: "pmullt z29.q, z30.d, z31.d"
diff --git a/tests/MC/AArch64/SVE2/pmullt.s.yaml b/tests/MC/AArch64/SVE2/pmullt.s.yaml
new file mode 100644
index 000000000..4155375a6
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/pmullt.s.yaml
@@ -0,0 +1,40 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x6c, 0x42, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "pmullt z0.h, z1.b, z2.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x6f, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "pmullt z31.d, z31.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x6c, 0x42, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "pmullt z0.h, z1.b, z2.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x6f, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "pmullt z31.d, z31.s, z31.s"
diff --git a/tests/MC/AArch64/SVE2/raddhnb.s.yaml b/tests/MC/AArch64/SVE2/raddhnb.s.yaml
new file mode 100644
index 000000000..a40f41000
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/raddhnb.s.yaml
@@ -0,0 +1,60 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x68, 0x7f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "raddhnb z0.b, z1.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x68, 0xbf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "raddhnb z0.h, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x68, 0xff, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "raddhnb z0.s, z1.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x68, 0x7f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "raddhnb z0.b, z1.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x68, 0xbf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "raddhnb z0.h, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x68, 0xff, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "raddhnb z0.s, z1.d, z31.d"
diff --git a/tests/MC/AArch64/SVE2/raddhnt.s.yaml b/tests/MC/AArch64/SVE2/raddhnt.s.yaml
new file mode 100644
index 000000000..2fb9572a5
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/raddhnt.s.yaml
@@ -0,0 +1,60 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x6c, 0x7f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "raddhnt z0.b, z1.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x6c, 0xbf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "raddhnt z0.h, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x6c, 0xff, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "raddhnt z0.s, z1.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x6c, 0x7f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "raddhnt z0.b, z1.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x6c, 0xbf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "raddhnt z0.h, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x6c, 0xff, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "raddhnt z0.s, z1.d, z31.d"
diff --git a/tests/MC/AArch64/SVE2/rax1.s.yaml b/tests/MC/AArch64/SVE2/rax1.s.yaml
new file mode 100644
index 000000000..1b9aea6fd
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/rax1.s.yaml
@@ -0,0 +1,10 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0xf4, 0x3f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2-sha3" ]
+    expected:
+      insns:
+        -
+          asm_text: "rax1 z0.d, z1.d, z31.d"
diff --git a/tests/MC/AArch64/SVE2/rshrnb.s.yaml b/tests/MC/AArch64/SVE2/rshrnb.s.yaml
new file mode 100644
index 000000000..9a7cfbdb5
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/rshrnb.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x18, 0x2f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "rshrnb z0.b, z0.h, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1b, 0x28, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "rshrnb z31.b, z31.h, #8"
+
+  -
+    input:
+      bytes: [ 0x00, 0x18, 0x3f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "rshrnb z0.h, z0.s, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1b, 0x30, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "rshrnb z31.h, z31.s, #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0x18, 0x7f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "rshrnb z0.s, z0.d, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1b, 0x60, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "rshrnb z31.s, z31.d, #32"
+
+  -
+    input:
+      bytes: [ 0x00, 0x18, 0x2f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "rshrnb z0.b, z0.h, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1b, 0x28, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "rshrnb z31.b, z31.h, #8"
+
+  -
+    input:
+      bytes: [ 0x00, 0x18, 0x3f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "rshrnb z0.h, z0.s, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1b, 0x30, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "rshrnb z31.h, z31.s, #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0x18, 0x7f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "rshrnb z0.s, z0.d, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1b, 0x60, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "rshrnb z31.s, z31.d, #32"
diff --git a/tests/MC/AArch64/SVE2/rshrnt.s.yaml b/tests/MC/AArch64/SVE2/rshrnt.s.yaml
new file mode 100644
index 000000000..4c30671e7
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/rshrnt.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x1c, 0x2f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "rshrnt z0.b, z0.h, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0x28, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "rshrnt z31.b, z31.h, #8"
+
+  -
+    input:
+      bytes: [ 0x00, 0x1c, 0x3f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "rshrnt z0.h, z0.s, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0x30, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "rshrnt z31.h, z31.s, #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0x1c, 0x7f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "rshrnt z0.s, z0.d, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0x60, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "rshrnt z31.s, z31.d, #32"
+
+  -
+    input:
+      bytes: [ 0x00, 0x1c, 0x2f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "rshrnt z0.b, z0.h, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0x28, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "rshrnt z31.b, z31.h, #8"
+
+  -
+    input:
+      bytes: [ 0x00, 0x1c, 0x3f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "rshrnt z0.h, z0.s, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0x30, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "rshrnt z31.h, z31.s, #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0x1c, 0x7f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "rshrnt z0.s, z0.d, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0x60, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "rshrnt z31.s, z31.d, #32"
diff --git a/tests/MC/AArch64/SVE2/rsubhnb.s.yaml b/tests/MC/AArch64/SVE2/rsubhnb.s.yaml
new file mode 100644
index 000000000..d25f08218
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/rsubhnb.s.yaml
@@ -0,0 +1,60 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x78, 0x7f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "rsubhnb z0.b, z1.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x78, 0xbf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "rsubhnb z0.h, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x78, 0xff, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "rsubhnb z0.s, z1.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x78, 0x7f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "rsubhnb z0.b, z1.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x78, 0xbf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "rsubhnb z0.h, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x78, 0xff, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "rsubhnb z0.s, z1.d, z31.d"
diff --git a/tests/MC/AArch64/SVE2/rsubhnt.s.yaml b/tests/MC/AArch64/SVE2/rsubhnt.s.yaml
new file mode 100644
index 000000000..9f5379186
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/rsubhnt.s.yaml
@@ -0,0 +1,60 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x7c, 0x7f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "rsubhnt z0.b, z1.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x7c, 0xbf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "rsubhnt z0.h, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x7c, 0xff, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "rsubhnt z0.s, z1.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x7c, 0x7f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "rsubhnt z0.b, z1.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x7c, 0xbf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "rsubhnt z0.h, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x7c, 0xff, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "rsubhnt z0.s, z1.d, z31.d"
diff --git a/tests/MC/AArch64/SVE2/saba.s.yaml b/tests/MC/AArch64/SVE2/saba.s.yaml
new file mode 100644
index 000000000..2ff994256
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/saba.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0xf8, 0x1f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "saba z0.b, z1.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf8, 0x5f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "saba z0.h, z1.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf8, 0x9f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "saba z0.s, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf8, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "saba z0.d, z1.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf8, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "saba z0.d, z1.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf8, 0x1f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "saba z0.b, z1.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf8, 0x5f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "saba z0.h, z1.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf8, 0x9f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "saba z0.s, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf8, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "saba z0.d, z1.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf8, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "saba z0.d, z1.d, z31.d"
diff --git a/tests/MC/AArch64/SVE2/sabalb.s.yaml b/tests/MC/AArch64/SVE2/sabalb.s.yaml
new file mode 100644
index 000000000..d29b76d21
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/sabalb.s.yaml
@@ -0,0 +1,100 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0xc0, 0x5f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sabalb z0.h, z1.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc0, 0x9f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sabalb z0.s, z1.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc0, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sabalb z0.d, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x95, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z21, z28"
+
+  -
+    input:
+      bytes: [ 0x35, 0xc0, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sabalb z21.d, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc0, 0x5f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sabalb z0.h, z1.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc0, 0x9f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sabalb z0.s, z1.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc0, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sabalb z0.d, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x95, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z21, z28"
+
+  -
+    input:
+      bytes: [ 0x35, 0xc0, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sabalb z21.d, z1.s, z31.s"
diff --git a/tests/MC/AArch64/SVE2/sabalt.s.yaml b/tests/MC/AArch64/SVE2/sabalt.s.yaml
new file mode 100644
index 000000000..33bb7dd11
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/sabalt.s.yaml
@@ -0,0 +1,100 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0xc4, 0x5f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sabalt z0.h, z1.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc4, 0x9f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sabalt z0.s, z1.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc4, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sabalt z0.d, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x95, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z21, z28"
+
+  -
+    input:
+      bytes: [ 0x35, 0xc4, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sabalt z21.d, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc4, 0x5f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sabalt z0.h, z1.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc4, 0x9f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sabalt z0.s, z1.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc4, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sabalt z0.d, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x95, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z21, z28"
+
+  -
+    input:
+      bytes: [ 0x35, 0xc4, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sabalt z21.d, z1.s, z31.s"
diff --git a/tests/MC/AArch64/SVE2/sabdlb.s.yaml b/tests/MC/AArch64/SVE2/sabdlb.s.yaml
new file mode 100644
index 000000000..94239dd96
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/sabdlb.s.yaml
@@ -0,0 +1,60 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x30, 0x42, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sabdlb z0.h, z1.b, z2.b"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x33, 0x9f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sabdlb z29.s, z30.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x33, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sabdlb z31.d, z31.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x30, 0x42, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sabdlb z0.h, z1.b, z2.b"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x33, 0x9f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sabdlb z29.s, z30.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x33, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sabdlb z31.d, z31.s, z31.s"
diff --git a/tests/MC/AArch64/SVE2/sabdlt.s.yaml b/tests/MC/AArch64/SVE2/sabdlt.s.yaml
new file mode 100644
index 000000000..f4bcaee25
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/sabdlt.s.yaml
@@ -0,0 +1,60 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x34, 0x42, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sabdlt z0.h, z1.b, z2.b"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x37, 0x9f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sabdlt z29.s, z30.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x37, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sabdlt z31.d, z31.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x34, 0x42, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sabdlt z0.h, z1.b, z2.b"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x37, 0x9f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sabdlt z29.s, z30.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x37, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sabdlt z31.d, z31.s, z31.s"
diff --git a/tests/MC/AArch64/SVE2/sadalp.s.yaml b/tests/MC/AArch64/SVE2/sadalp.s.yaml
new file mode 100644
index 000000000..3045f95bb
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/sadalp.s.yaml
@@ -0,0 +1,140 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0xa0, 0x44, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sadalp z0.h, p0/m, z1.b"
+
+  -
+    input:
+      bytes: [ 0xdd, 0xa3, 0x84, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sadalp z29.s, p0/m, z30.h"
+
+  -
+    input:
+      bytes: [ 0xfe, 0xbf, 0xc4, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sadalp z30.d, p7/m, z31.s"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31.d, p0/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xa3, 0xc4, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sadalp z31.d, p0/m, z30.s"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xa3, 0xc4, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sadalp z31.d, p0/m, z30.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa0, 0x44, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sadalp z0.h, p0/m, z1.b"
+
+  -
+    input:
+      bytes: [ 0xdd, 0xa3, 0x84, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sadalp z29.s, p0/m, z30.h"
+
+  -
+    input:
+      bytes: [ 0xfe, 0xbf, 0xc4, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sadalp z30.d, p7/m, z31.s"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31.d, p0/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xa3, 0xc4, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sadalp z31.d, p0/m, z30.s"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xa3, 0xc4, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sadalp z31.d, p0/m, z30.s"
diff --git a/tests/MC/AArch64/SVE2/saddlb.s.yaml b/tests/MC/AArch64/SVE2/saddlb.s.yaml
new file mode 100644
index 000000000..9dafe43c5
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/saddlb.s.yaml
@@ -0,0 +1,60 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x00, 0x42, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "saddlb z0.h, z1.b, z2.b"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x03, 0x9f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "saddlb z29.s, z30.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x03, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "saddlb z31.d, z31.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x00, 0x42, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "saddlb z0.h, z1.b, z2.b"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x03, 0x9f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "saddlb z29.s, z30.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x03, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "saddlb z31.d, z31.s, z31.s"
diff --git a/tests/MC/AArch64/SVE2/saddlbt.s.yaml b/tests/MC/AArch64/SVE2/saddlbt.s.yaml
new file mode 100644
index 000000000..6a14a445f
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/saddlbt.s.yaml
@@ -0,0 +1,60 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x5f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "saddlbt z0.h, z1.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x9f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "saddlbt z0.s, z1.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "saddlbt z0.d, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x5f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "saddlbt z0.h, z1.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x9f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "saddlbt z0.s, z1.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "saddlbt z0.d, z1.s, z31.s"
diff --git a/tests/MC/AArch64/SVE2/saddlt.s.yaml b/tests/MC/AArch64/SVE2/saddlt.s.yaml
new file mode 100644
index 000000000..f7a8a4a1a
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/saddlt.s.yaml
@@ -0,0 +1,60 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x04, 0x42, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "saddlt z0.h, z1.b, z2.b"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x07, 0x9f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "saddlt z29.s, z30.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x07, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "saddlt z31.d, z31.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x04, 0x42, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "saddlt z0.h, z1.b, z2.b"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x07, 0x9f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "saddlt z29.s, z30.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x07, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "saddlt z31.d, z31.s, z31.s"
diff --git a/tests/MC/AArch64/SVE2/saddwb.s.yaml b/tests/MC/AArch64/SVE2/saddwb.s.yaml
new file mode 100644
index 000000000..4606da802
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/saddwb.s.yaml
@@ -0,0 +1,60 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x40, 0x42, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "saddwb z0.h, z1.h, z2.b"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x43, 0x9f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "saddwb z29.s, z30.s, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x43, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "saddwb z31.d, z31.d, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x40, 0x42, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "saddwb z0.h, z1.h, z2.b"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x43, 0x9f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "saddwb z29.s, z30.s, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x43, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "saddwb z31.d, z31.d, z31.s"
diff --git a/tests/MC/AArch64/SVE2/saddwt.s.yaml b/tests/MC/AArch64/SVE2/saddwt.s.yaml
new file mode 100644
index 000000000..a10135234
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/saddwt.s.yaml
@@ -0,0 +1,60 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x44, 0x42, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "saddwt z0.h, z1.h, z2.b"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x47, 0x9f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "saddwt z29.s, z30.s, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x47, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "saddwt z31.d, z31.d, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x44, 0x42, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "saddwt z0.h, z1.h, z2.b"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x47, 0x9f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "saddwt z29.s, z30.s, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x47, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "saddwt z31.d, z31.d, z31.s"
diff --git a/tests/MC/AArch64/SVE2/sbclb.s.yaml b/tests/MC/AArch64/SVE2/sbclb.s.yaml
new file mode 100644
index 000000000..b08f8c7a6
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/sbclb.s.yaml
@@ -0,0 +1,80 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0xd0, 0x9f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sbclb z0.s, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd0, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sbclb z0.d, z1.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd0, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sbclb z0.d, z1.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd0, 0x9f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sbclb z0.s, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd0, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sbclb z0.d, z1.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd0, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sbclb z0.d, z1.d, z31.d"
diff --git a/tests/MC/AArch64/SVE2/sbclt.s.yaml b/tests/MC/AArch64/SVE2/sbclt.s.yaml
new file mode 100644
index 000000000..53037e57f
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/sbclt.s.yaml
@@ -0,0 +1,80 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0xd4, 0x9f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sbclt z0.s, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd4, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sbclt z0.d, z1.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd4, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sbclt z0.d, z1.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd4, 0x9f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sbclt z0.s, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd4, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sbclt z0.d, z1.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd4, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sbclt z0.d, z1.d, z31.d"
diff --git a/tests/MC/AArch64/SVE2/shadd.s.yaml b/tests/MC/AArch64/SVE2/shadd.s.yaml
new file mode 100644
index 000000000..022d4ab7b
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/shadd.s.yaml
@@ -0,0 +1,160 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x10, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "shadd z0.b, p0/m, z0.b, z1.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x50, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "shadd z0.h, p0/m, z0.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x9f, 0x90, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "shadd z29.s, p7/m, z29.s, z30.s"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xd0, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "shadd z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31.d, p0/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x83, 0xd0, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "shadd z31.d, p0/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xd0, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "shadd z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x10, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "shadd z0.b, p0/m, z0.b, z1.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x50, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "shadd z0.h, p0/m, z0.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x9f, 0x90, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "shadd z29.s, p7/m, z29.s, z30.s"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xd0, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "shadd z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31.d, p0/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x83, 0xd0, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "shadd z31.d, p0/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xd0, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "shadd z31.d, p7/m, z31.d, z30.d"
diff --git a/tests/MC/AArch64/SVE2/shrnb.s.yaml b/tests/MC/AArch64/SVE2/shrnb.s.yaml
new file mode 100644
index 000000000..395ac7941
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/shrnb.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x10, 0x2f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "shrnb z0.b, z0.h, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x13, 0x28, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "shrnb z31.b, z31.h, #8"
+
+  -
+    input:
+      bytes: [ 0x00, 0x10, 0x3f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "shrnb z0.h, z0.s, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x13, 0x30, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "shrnb z31.h, z31.s, #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0x10, 0x7f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "shrnb z0.s, z0.d, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x13, 0x60, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "shrnb z31.s, z31.d, #32"
+
+  -
+    input:
+      bytes: [ 0x00, 0x10, 0x2f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "shrnb z0.b, z0.h, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x13, 0x28, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "shrnb z31.b, z31.h, #8"
+
+  -
+    input:
+      bytes: [ 0x00, 0x10, 0x3f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "shrnb z0.h, z0.s, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x13, 0x30, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "shrnb z31.h, z31.s, #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0x10, 0x7f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "shrnb z0.s, z0.d, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x13, 0x60, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "shrnb z31.s, z31.d, #32"
diff --git a/tests/MC/AArch64/SVE2/shrnt.s.yaml b/tests/MC/AArch64/SVE2/shrnt.s.yaml
new file mode 100644
index 000000000..3d24388c9
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/shrnt.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x14, 0x2f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "shrnt z0.b, z0.h, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x17, 0x28, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "shrnt z31.b, z31.h, #8"
+
+  -
+    input:
+      bytes: [ 0x00, 0x14, 0x3f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "shrnt z0.h, z0.s, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x17, 0x30, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "shrnt z31.h, z31.s, #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0x14, 0x7f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "shrnt z0.s, z0.d, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x17, 0x60, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "shrnt z31.s, z31.d, #32"
+
+  -
+    input:
+      bytes: [ 0x00, 0x14, 0x2f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "shrnt z0.b, z0.h, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x17, 0x28, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "shrnt z31.b, z31.h, #8"
+
+  -
+    input:
+      bytes: [ 0x00, 0x14, 0x3f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "shrnt z0.h, z0.s, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x17, 0x30, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "shrnt z31.h, z31.s, #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0x14, 0x7f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "shrnt z0.s, z0.d, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x17, 0x60, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "shrnt z31.s, z31.d, #32"
diff --git a/tests/MC/AArch64/SVE2/shsub.s.yaml b/tests/MC/AArch64/SVE2/shsub.s.yaml
new file mode 100644
index 000000000..86ede4b9f
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/shsub.s.yaml
@@ -0,0 +1,160 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x12, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "shsub z0.b, p0/m, z0.b, z1.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x52, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "shsub z0.h, p0/m, z0.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x9f, 0x92, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "shsub z29.s, p7/m, z29.s, z30.s"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xd2, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "shsub z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31.d, p0/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x83, 0xd2, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "shsub z31.d, p0/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xd2, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "shsub z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x12, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "shsub z0.b, p0/m, z0.b, z1.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x52, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "shsub z0.h, p0/m, z0.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x9f, 0x92, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "shsub z29.s, p7/m, z29.s, z30.s"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xd2, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "shsub z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31.d, p0/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x83, 0xd2, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "shsub z31.d, p0/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xd2, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "shsub z31.d, p7/m, z31.d, z30.d"
diff --git a/tests/MC/AArch64/SVE2/shsubr.s.yaml b/tests/MC/AArch64/SVE2/shsubr.s.yaml
new file mode 100644
index 000000000..2b9170932
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/shsubr.s.yaml
@@ -0,0 +1,160 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x16, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "shsubr z0.b, p0/m, z0.b, z1.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x56, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "shsubr z0.h, p0/m, z0.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x9f, 0x96, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "shsubr z29.s, p7/m, z29.s, z30.s"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xd6, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "shsubr z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31.d, p0/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x83, 0xd6, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "shsubr z31.d, p0/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xd6, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "shsubr z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x16, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "shsubr z0.b, p0/m, z0.b, z1.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x56, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "shsubr z0.h, p0/m, z0.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x9f, 0x96, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "shsubr z29.s, p7/m, z29.s, z30.s"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xd6, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "shsubr z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31.d, p0/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x83, 0xd6, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "shsubr z31.d, p0/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xd6, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "shsubr z31.d, p7/m, z31.d, z30.d"
diff --git a/tests/MC/AArch64/SVE2/sli.s.yaml b/tests/MC/AArch64/SVE2/sli.s.yaml
new file mode 100644
index 000000000..06acb33ea
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/sli.s.yaml
@@ -0,0 +1,160 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xf4, 0x08, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sli z0.b, z0.b, #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0xf7, 0x0f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sli z31.b, z31.b, #7"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf4, 0x10, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sli z0.h, z0.h, #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0xf7, 0x1f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sli z31.h, z31.h, #15"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf4, 0x40, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sli z0.s, z0.s, #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0xf7, 0x5f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sli z31.s, z31.s, #31"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf4, 0x80, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sli z0.d, z0.d, #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0xf7, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sli z31.d, z31.d, #63"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf4, 0x08, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sli z0.b, z0.b, #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0xf7, 0x0f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sli z31.b, z31.b, #7"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf4, 0x10, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sli z0.h, z0.h, #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0xf7, 0x1f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sli z31.h, z31.h, #15"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf4, 0x40, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sli z0.s, z0.s, #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0xf7, 0x5f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sli z31.s, z31.s, #31"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf4, 0x80, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sli z0.d, z0.d, #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0xf7, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sli z31.d, z31.d, #63"
diff --git a/tests/MC/AArch64/SVE2/sm4e.s.yaml b/tests/MC/AArch64/SVE2/sm4e.s.yaml
new file mode 100644
index 000000000..64c87a643
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/sm4e.s.yaml
@@ -0,0 +1,10 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xe0, 0xe3, 0x23, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2-sm4" ]
+    expected:
+      insns:
+        -
+          asm_text: "sm4e z0.s, z0.s, z31.s"
diff --git a/tests/MC/AArch64/SVE2/sm4ekey.s.yaml b/tests/MC/AArch64/SVE2/sm4ekey.s.yaml
new file mode 100644
index 000000000..6ad07d7ad
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/sm4ekey.s.yaml
@@ -0,0 +1,10 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0xf0, 0x3f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2-sm4" ]
+    expected:
+      insns:
+        -
+          asm_text: "sm4ekey z0.s, z1.s, z31.s"
diff --git a/tests/MC/AArch64/SVE2/smaxp.s.yaml b/tests/MC/AArch64/SVE2/smaxp.s.yaml
new file mode 100644
index 000000000..dd126d3bf
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/smaxp.s.yaml
@@ -0,0 +1,160 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0xa0, 0x14, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smaxp z0.b, p0/m, z0.b, z1.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa0, 0x54, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smaxp z0.h, p0/m, z0.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0xdd, 0xbf, 0x94, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smaxp z29.s, p7/m, z29.s, z30.s"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbf, 0xd4, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smaxp z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31.d, p0/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xa3, 0xd4, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smaxp z31.d, p0/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbf, 0xd4, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smaxp z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa0, 0x14, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smaxp z0.b, p0/m, z0.b, z1.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa0, 0x54, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smaxp z0.h, p0/m, z0.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0xdd, 0xbf, 0x94, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smaxp z29.s, p7/m, z29.s, z30.s"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbf, 0xd4, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smaxp z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31.d, p0/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xa3, 0xd4, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smaxp z31.d, p0/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbf, 0xd4, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smaxp z31.d, p7/m, z31.d, z30.d"
diff --git a/tests/MC/AArch64/SVE2/sminp.s.yaml b/tests/MC/AArch64/SVE2/sminp.s.yaml
new file mode 100644
index 000000000..dc612f5ed
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/sminp.s.yaml
@@ -0,0 +1,160 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0xa0, 0x16, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sminp z0.b, p0/m, z0.b, z1.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa0, 0x56, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sminp z0.h, p0/m, z0.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0xdd, 0xbf, 0x96, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sminp z29.s, p7/m, z29.s, z30.s"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbf, 0xd6, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sminp z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31.d, p0/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xa3, 0xd6, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sminp z31.d, p0/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbf, 0xd6, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sminp z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa0, 0x16, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sminp z0.b, p0/m, z0.b, z1.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa0, 0x56, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sminp z0.h, p0/m, z0.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0xdd, 0xbf, 0x96, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sminp z29.s, p7/m, z29.s, z30.s"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbf, 0xd6, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sminp z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31.d, p0/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xa3, 0xd6, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sminp z31.d, p0/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbf, 0xd6, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sminp z31.d, p7/m, z31.d, z30.d"
diff --git a/tests/MC/AArch64/SVE2/smlalb.s.yaml b/tests/MC/AArch64/SVE2/smlalb.s.yaml
new file mode 100644
index 000000000..1ed103d46
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/smlalb.s.yaml
@@ -0,0 +1,180 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x40, 0x5f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlalb z0.h, z1.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x40, 0x9f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlalb z0.s, z1.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x40, 0xdf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlalb z0.d, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x88, 0xbf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlalb z0.s, z1.h, z7.h[7]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x88, 0xef, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlalb z0.d, z1.s, z15.s[1]"
+
+  -
+    input:
+      bytes: [ 0x95, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z21, z28"
+
+  -
+    input:
+      bytes: [ 0x35, 0x40, 0xdf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlalb z21.d, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x95, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z21, z28"
+
+  -
+    input:
+      bytes: [ 0x55, 0x89, 0xe5, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlalb z21.d, z10.s, z5.s[1]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x40, 0x5f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlalb z0.h, z1.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x40, 0x9f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlalb z0.s, z1.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x40, 0xdf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlalb z0.d, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x88, 0xbf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlalb z0.s, z1.h, z7.h[7]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x88, 0xef, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlalb z0.d, z1.s, z15.s[1]"
+
+  -
+    input:
+      bytes: [ 0x95, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z21, z28"
+
+  -
+    input:
+      bytes: [ 0x35, 0x40, 0xdf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlalb z21.d, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x95, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z21, z28"
+
+  -
+    input:
+      bytes: [ 0x55, 0x89, 0xe5, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlalb z21.d, z10.s, z5.s[1]"
diff --git a/tests/MC/AArch64/SVE2/smlalt.s.yaml b/tests/MC/AArch64/SVE2/smlalt.s.yaml
new file mode 100644
index 000000000..6aeb13a01
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/smlalt.s.yaml
@@ -0,0 +1,180 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x44, 0x5f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlalt z0.h, z1.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x44, 0x9f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlalt z0.s, z1.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x44, 0xdf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlalt z0.d, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x8c, 0xbf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlalt z0.s, z1.h, z7.h[7]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x8c, 0xef, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlalt z0.d, z1.s, z15.s[1]"
+
+  -
+    input:
+      bytes: [ 0x95, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z21, z28"
+
+  -
+    input:
+      bytes: [ 0x35, 0x44, 0xdf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlalt z21.d, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x95, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z21, z28"
+
+  -
+    input:
+      bytes: [ 0x55, 0x8d, 0xe5, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlalt z21.d, z10.s, z5.s[1]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x44, 0x5f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlalt z0.h, z1.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x44, 0x9f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlalt z0.s, z1.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x44, 0xdf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlalt z0.d, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x8c, 0xbf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlalt z0.s, z1.h, z7.h[7]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x8c, 0xef, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlalt z0.d, z1.s, z15.s[1]"
+
+  -
+    input:
+      bytes: [ 0x95, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z21, z28"
+
+  -
+    input:
+      bytes: [ 0x35, 0x44, 0xdf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlalt z21.d, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x95, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z21, z28"
+
+  -
+    input:
+      bytes: [ 0x55, 0x8d, 0xe5, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlalt z21.d, z10.s, z5.s[1]"
diff --git a/tests/MC/AArch64/SVE2/smlslb.s.yaml b/tests/MC/AArch64/SVE2/smlslb.s.yaml
new file mode 100644
index 000000000..ce3d050e8
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/smlslb.s.yaml
@@ -0,0 +1,180 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x50, 0x5f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlslb z0.h, z1.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x50, 0x9f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlslb z0.s, z1.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x50, 0xdf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlslb z0.d, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa8, 0xbf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlslb z0.s, z1.h, z7.h[7]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa8, 0xef, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlslb z0.d, z1.s, z15.s[1]"
+
+  -
+    input:
+      bytes: [ 0x95, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z21, z28"
+
+  -
+    input:
+      bytes: [ 0x35, 0x50, 0xdf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlslb z21.d, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x95, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z21, z28"
+
+  -
+    input:
+      bytes: [ 0x55, 0xa9, 0xe5, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlslb z21.d, z10.s, z5.s[1]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x50, 0x5f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlslb z0.h, z1.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x50, 0x9f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlslb z0.s, z1.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x50, 0xdf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlslb z0.d, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa8, 0xbf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlslb z0.s, z1.h, z7.h[7]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa8, 0xef, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlslb z0.d, z1.s, z15.s[1]"
+
+  -
+    input:
+      bytes: [ 0x95, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z21, z28"
+
+  -
+    input:
+      bytes: [ 0x35, 0x50, 0xdf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlslb z21.d, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x95, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z21, z28"
+
+  -
+    input:
+      bytes: [ 0x55, 0xa9, 0xe5, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlslb z21.d, z10.s, z5.s[1]"
diff --git a/tests/MC/AArch64/SVE2/smlslt.s.yaml b/tests/MC/AArch64/SVE2/smlslt.s.yaml
new file mode 100644
index 000000000..4ec129b38
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/smlslt.s.yaml
@@ -0,0 +1,180 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x54, 0x5f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlslt z0.h, z1.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x54, 0x9f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlslt z0.s, z1.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x54, 0xdf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlslt z0.d, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0xac, 0xbf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlslt z0.s, z1.h, z7.h[7]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xac, 0xef, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlslt z0.d, z1.s, z15.s[1]"
+
+  -
+    input:
+      bytes: [ 0x95, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z21, z28"
+
+  -
+    input:
+      bytes: [ 0x35, 0x54, 0xdf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlslt z21.d, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x95, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z21, z28"
+
+  -
+    input:
+      bytes: [ 0x55, 0xad, 0xe5, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlslt z21.d, z10.s, z5.s[1]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x54, 0x5f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlslt z0.h, z1.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x54, 0x9f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlslt z0.s, z1.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x54, 0xdf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlslt z0.d, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0xac, 0xbf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlslt z0.s, z1.h, z7.h[7]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xac, 0xef, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlslt z0.d, z1.s, z15.s[1]"
+
+  -
+    input:
+      bytes: [ 0x95, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z21, z28"
+
+  -
+    input:
+      bytes: [ 0x35, 0x54, 0xdf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlslt z21.d, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x95, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z21, z28"
+
+  -
+    input:
+      bytes: [ 0x55, 0xad, 0xe5, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlslt z21.d, z10.s, z5.s[1]"
diff --git a/tests/MC/AArch64/SVE2/smulh.s.yaml b/tests/MC/AArch64/SVE2/smulh.s.yaml
new file mode 100644
index 000000000..485a891dc
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/smulh.s.yaml
@@ -0,0 +1,80 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x68, 0x22, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smulh z0.b, z1.b, z2.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x68, 0x62, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smulh z0.h, z1.h, z2.h"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x6b, 0xbf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smulh z29.s, z30.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0x6b, 0xff, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smulh z31.d, z31.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x68, 0x22, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smulh z0.b, z1.b, z2.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x68, 0x62, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smulh z0.h, z1.h, z2.h"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x6b, 0xbf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smulh z29.s, z30.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0x6b, 0xff, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smulh z31.d, z31.d, z31.d"
diff --git a/tests/MC/AArch64/SVE2/smullb.s.yaml b/tests/MC/AArch64/SVE2/smullb.s.yaml
new file mode 100644
index 000000000..69f8dca14
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/smullb.s.yaml
@@ -0,0 +1,100 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x70, 0x42, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smullb z0.h, z1.b, z2.b"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x73, 0x9f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smullb z29.s, z30.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x73, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smullb z31.d, z31.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc8, 0xbf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smullb z0.s, z1.h, z7.h[7]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc8, 0xef, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smullb z0.d, z1.s, z15.s[1]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x70, 0x42, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smullb z0.h, z1.b, z2.b"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x73, 0x9f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smullb z29.s, z30.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x73, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smullb z31.d, z31.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc8, 0xbf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smullb z0.s, z1.h, z7.h[7]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc8, 0xef, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smullb z0.d, z1.s, z15.s[1]"
diff --git a/tests/MC/AArch64/SVE2/smullt.s.yaml b/tests/MC/AArch64/SVE2/smullt.s.yaml
new file mode 100644
index 000000000..1e9d7cfaa
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/smullt.s.yaml
@@ -0,0 +1,100 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x74, 0x42, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smullt z0.h, z1.b, z2.b"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x77, 0x9f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smullt z29.s, z30.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x77, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smullt z31.d, z31.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0xcc, 0xbf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smullt z0.s, z1.h, z7.h[7]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xcc, 0xef, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "smullt z0.d, z1.s, z15.s[1]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x74, 0x42, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smullt z0.h, z1.b, z2.b"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x77, 0x9f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smullt z29.s, z30.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x77, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smullt z31.d, z31.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0xcc, 0xbf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smullt z0.s, z1.h, z7.h[7]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xcc, 0xef, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "smullt z0.d, z1.s, z15.s[1]"
diff --git a/tests/MC/AArch64/SVE2/splice.s.yaml b/tests/MC/AArch64/SVE2/splice.s.yaml
new file mode 100644
index 000000000..c7e6d98af
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/splice.s.yaml
@@ -0,0 +1,80 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xdd, 0x9f, 0x2d, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "splice z29.b, p7, { z30.b, z31.b }"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x9f, 0x6d, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "splice z29.h, p7, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x9f, 0xad, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "splice z29.s, p7, { z30.s, z31.s }"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x9f, 0xed, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "splice z29.d, p7, { z30.d, z31.d }"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x9f, 0x2d, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "splice z29.b, p7, { z30.b, z31.b }"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x9f, 0x6d, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "splice z29.h, p7, { z30.h, z31.h }"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x9f, 0xad, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "splice z29.s, p7, { z30.s, z31.s }"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x9f, 0xed, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "splice z29.d, p7, { z30.d, z31.d }"
diff --git a/tests/MC/AArch64/SVE2/sqabs.s.yaml b/tests/MC/AArch64/SVE2/sqabs.s.yaml
new file mode 100644
index 000000000..25f14a9f0
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/sqabs.s.yaml
@@ -0,0 +1,160 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x08, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqabs z31.b, p7/m, z31.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x48, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqabs z31.h, p7/m, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x88, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqabs z31.s, p7/m, z31.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0xc8, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqabs z31.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0x3c, 0x90, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4.s, p7/z, z6.s"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xbf, 0x88, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqabs z4.s, p7/m, z31.s"
+
+  -
+    input:
+      bytes: [ 0xc4, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4, z6"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xbf, 0x88, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqabs z4.s, p7/m, z31.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x08, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqabs z31.b, p7/m, z31.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x48, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqabs z31.h, p7/m, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x88, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqabs z31.s, p7/m, z31.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0xc8, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqabs z31.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0x3c, 0x90, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4.s, p7/z, z6.s"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xbf, 0x88, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqabs z4.s, p7/m, z31.s"
+
+  -
+    input:
+      bytes: [ 0xc4, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4, z6"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xbf, 0x88, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqabs z4.s, p7/m, z31.s"
diff --git a/tests/MC/AArch64/SVE2/sqadd.s.yaml b/tests/MC/AArch64/SVE2/sqadd.s.yaml
new file mode 100644
index 000000000..93f4f9d90
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/sqadd.s.yaml
@@ -0,0 +1,160 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x18, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqadd z0.b, p0/m, z0.b, z1.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x58, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqadd z0.h, p0/m, z0.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x9f, 0x98, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqadd z29.s, p7/m, z29.s, z30.s"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xd8, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqadd z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31.d, p0/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x83, 0xd8, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqadd z31.d, p0/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xd8, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqadd z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x18, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqadd z0.b, p0/m, z0.b, z1.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x58, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqadd z0.h, p0/m, z0.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x9f, 0x98, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqadd z29.s, p7/m, z29.s, z30.s"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xd8, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqadd z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31.d, p0/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x83, 0xd8, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqadd z31.d, p0/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xd8, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqadd z31.d, p7/m, z31.d, z30.d"
diff --git a/tests/MC/AArch64/SVE2/sqcadd.s.yaml b/tests/MC/AArch64/SVE2/sqcadd.s.yaml
new file mode 100644
index 000000000..8ea8f3d7b
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/sqcadd.s.yaml
@@ -0,0 +1,200 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xd8, 0x01, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqcadd z0.b, z0.b, z0.b, #90"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd8, 0x41, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqcadd z0.h, z0.h, z0.h, #90"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd8, 0x81, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqcadd z0.s, z0.s, z0.s, #90"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd8, 0xc1, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqcadd z0.d, z0.d, z0.d, #90"
+
+  -
+    input:
+      bytes: [ 0xff, 0xdf, 0x01, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqcadd z31.b, z31.b, z31.b, #270"
+
+  -
+    input:
+      bytes: [ 0xff, 0xdf, 0x41, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqcadd z31.h, z31.h, z31.h, #270"
+
+  -
+    input:
+      bytes: [ 0xff, 0xdf, 0x81, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqcadd z31.s, z31.s, z31.s, #270"
+
+  -
+    input:
+      bytes: [ 0xff, 0xdf, 0xc1, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqcadd z31.d, z31.d, z31.d, #270"
+
+  -
+    input:
+      bytes: [ 0xc4, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4, z6"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xdf, 0xc1, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqcadd z4.d, z4.d, z31.d, #270"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd8, 0x01, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqcadd z0.b, z0.b, z0.b, #90"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd8, 0x41, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqcadd z0.h, z0.h, z0.h, #90"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd8, 0x81, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqcadd z0.s, z0.s, z0.s, #90"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd8, 0xc1, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqcadd z0.d, z0.d, z0.d, #90"
+
+  -
+    input:
+      bytes: [ 0xff, 0xdf, 0x01, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqcadd z31.b, z31.b, z31.b, #270"
+
+  -
+    input:
+      bytes: [ 0xff, 0xdf, 0x41, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqcadd z31.h, z31.h, z31.h, #270"
+
+  -
+    input:
+      bytes: [ 0xff, 0xdf, 0x81, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqcadd z31.s, z31.s, z31.s, #270"
+
+  -
+    input:
+      bytes: [ 0xff, 0xdf, 0xc1, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqcadd z31.d, z31.d, z31.d, #270"
+
+  -
+    input:
+      bytes: [ 0xc4, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4, z6"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xdf, 0xc1, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqcadd z4.d, z4.d, z31.d, #270"
diff --git a/tests/MC/AArch64/SVE2/sqdmlalb.s.yaml b/tests/MC/AArch64/SVE2/sqdmlalb.s.yaml
new file mode 100644
index 000000000..264f45186
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/sqdmlalb.s.yaml
@@ -0,0 +1,180 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x60, 0x5f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmlalb z0.h, z1.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x60, 0x9f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmlalb z0.s, z1.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x60, 0xdf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmlalb z0.d, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x28, 0xbf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmlalb z0.s, z1.h, z7.h[7]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x28, 0xff, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmlalb z0.d, z1.s, z15.s[3]"
+
+  -
+    input:
+      bytes: [ 0x95, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z21, z28"
+
+  -
+    input:
+      bytes: [ 0x35, 0x60, 0xdf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmlalb z21.d, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x95, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z21, z28"
+
+  -
+    input:
+      bytes: [ 0x55, 0x29, 0xe5, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmlalb z21.d, z10.s, z5.s[1]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x60, 0x5f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmlalb z0.h, z1.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x60, 0x9f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmlalb z0.s, z1.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x60, 0xdf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmlalb z0.d, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x28, 0xbf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmlalb z0.s, z1.h, z7.h[7]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x28, 0xff, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmlalb z0.d, z1.s, z15.s[3]"
+
+  -
+    input:
+      bytes: [ 0x95, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z21, z28"
+
+  -
+    input:
+      bytes: [ 0x35, 0x60, 0xdf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmlalb z21.d, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x95, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z21, z28"
+
+  -
+    input:
+      bytes: [ 0x55, 0x29, 0xe5, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmlalb z21.d, z10.s, z5.s[1]"
diff --git a/tests/MC/AArch64/SVE2/sqdmlalbt.s.yaml b/tests/MC/AArch64/SVE2/sqdmlalbt.s.yaml
new file mode 100644
index 000000000..90823c1b6
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/sqdmlalbt.s.yaml
@@ -0,0 +1,100 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x08, 0x5f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmlalbt z0.h, z1.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x08, 0x9f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmlalbt z0.s, z1.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x08, 0xdf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmlalbt z0.d, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x95, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z21, z28"
+
+  -
+    input:
+      bytes: [ 0x35, 0x08, 0xdf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmlalbt z21.d, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x08, 0x5f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmlalbt z0.h, z1.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x08, 0x9f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmlalbt z0.s, z1.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x08, 0xdf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmlalbt z0.d, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x95, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z21, z28"
+
+  -
+    input:
+      bytes: [ 0x35, 0x08, 0xdf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmlalbt z21.d, z1.s, z31.s"
diff --git a/tests/MC/AArch64/SVE2/sqdmlalt.s.yaml b/tests/MC/AArch64/SVE2/sqdmlalt.s.yaml
new file mode 100644
index 000000000..76d4b929e
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/sqdmlalt.s.yaml
@@ -0,0 +1,180 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x64, 0x5f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmlalt z0.h, z1.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x64, 0x9f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmlalt z0.s, z1.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x64, 0xdf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmlalt z0.d, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x2c, 0xbf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmlalt z0.s, z1.h, z7.h[7]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x2c, 0xff, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmlalt z0.d, z1.s, z15.s[3]"
+
+  -
+    input:
+      bytes: [ 0x95, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z21, z28"
+
+  -
+    input:
+      bytes: [ 0x35, 0x64, 0xdf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmlalt z21.d, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x95, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z21, z28"
+
+  -
+    input:
+      bytes: [ 0x55, 0x2d, 0xe5, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmlalt z21.d, z10.s, z5.s[1]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x64, 0x5f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmlalt z0.h, z1.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x64, 0x9f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmlalt z0.s, z1.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x64, 0xdf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmlalt z0.d, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x2c, 0xbf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmlalt z0.s, z1.h, z7.h[7]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x2c, 0xff, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmlalt z0.d, z1.s, z15.s[3]"
+
+  -
+    input:
+      bytes: [ 0x95, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z21, z28"
+
+  -
+    input:
+      bytes: [ 0x35, 0x64, 0xdf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmlalt z21.d, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x95, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z21, z28"
+
+  -
+    input:
+      bytes: [ 0x55, 0x2d, 0xe5, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmlalt z21.d, z10.s, z5.s[1]"
diff --git a/tests/MC/AArch64/SVE2/sqdmlslb.s.yaml b/tests/MC/AArch64/SVE2/sqdmlslb.s.yaml
new file mode 100644
index 000000000..c1f942edf
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/sqdmlslb.s.yaml
@@ -0,0 +1,180 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x68, 0x5f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmlslb z0.h, z1.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x68, 0x9f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmlslb z0.s, z1.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x68, 0xdf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmlslb z0.d, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x38, 0xbf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmlslb z0.s, z1.h, z7.h[7]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x38, 0xff, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmlslb z0.d, z1.s, z15.s[3]"
+
+  -
+    input:
+      bytes: [ 0x95, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z21, z28"
+
+  -
+    input:
+      bytes: [ 0x35, 0x68, 0xdf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmlslb z21.d, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x95, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z21, z28"
+
+  -
+    input:
+      bytes: [ 0x55, 0x39, 0xe5, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmlslb z21.d, z10.s, z5.s[1]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x68, 0x5f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmlslb z0.h, z1.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x68, 0x9f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmlslb z0.s, z1.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x68, 0xdf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmlslb z0.d, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x38, 0xbf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmlslb z0.s, z1.h, z7.h[7]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x38, 0xff, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmlslb z0.d, z1.s, z15.s[3]"
+
+  -
+    input:
+      bytes: [ 0x95, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z21, z28"
+
+  -
+    input:
+      bytes: [ 0x35, 0x68, 0xdf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmlslb z21.d, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x95, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z21, z28"
+
+  -
+    input:
+      bytes: [ 0x55, 0x39, 0xe5, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmlslb z21.d, z10.s, z5.s[1]"
diff --git a/tests/MC/AArch64/SVE2/sqdmlslbt.s.yaml b/tests/MC/AArch64/SVE2/sqdmlslbt.s.yaml
new file mode 100644
index 000000000..c7d29a3ab
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/sqdmlslbt.s.yaml
@@ -0,0 +1,100 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x0c, 0x5f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmlslbt z0.h, z1.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x0c, 0x9f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmlslbt z0.s, z1.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x0c, 0xdf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmlslbt z0.d, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x95, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z21, z28"
+
+  -
+    input:
+      bytes: [ 0x35, 0x0c, 0xdf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmlslbt z21.d, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x0c, 0x5f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmlslbt z0.h, z1.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x0c, 0x9f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmlslbt z0.s, z1.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x0c, 0xdf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmlslbt z0.d, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x95, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z21, z28"
+
+  -
+    input:
+      bytes: [ 0x35, 0x0c, 0xdf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmlslbt z21.d, z1.s, z31.s"
diff --git a/tests/MC/AArch64/SVE2/sqdmlslt.s.yaml b/tests/MC/AArch64/SVE2/sqdmlslt.s.yaml
new file mode 100644
index 000000000..8575b1fe7
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/sqdmlslt.s.yaml
@@ -0,0 +1,180 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x6c, 0x5f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmlslt z0.h, z1.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x6c, 0x9f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmlslt z0.s, z1.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x6c, 0xdf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmlslt z0.d, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x3c, 0xbf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmlslt z0.s, z1.h, z7.h[7]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x3c, 0xff, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmlslt z0.d, z1.s, z15.s[3]"
+
+  -
+    input:
+      bytes: [ 0x95, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z21, z28"
+
+  -
+    input:
+      bytes: [ 0x35, 0x6c, 0xdf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmlslt z21.d, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x95, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z21, z28"
+
+  -
+    input:
+      bytes: [ 0x55, 0x3d, 0xe5, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmlslt z21.d, z10.s, z5.s[1]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x6c, 0x5f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmlslt z0.h, z1.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x6c, 0x9f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmlslt z0.s, z1.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x6c, 0xdf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmlslt z0.d, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x3c, 0xbf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmlslt z0.s, z1.h, z7.h[7]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x3c, 0xff, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmlslt z0.d, z1.s, z15.s[3]"
+
+  -
+    input:
+      bytes: [ 0x95, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z21, z28"
+
+  -
+    input:
+      bytes: [ 0x35, 0x6c, 0xdf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmlslt z21.d, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x95, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z21, z28"
+
+  -
+    input:
+      bytes: [ 0x55, 0x3d, 0xe5, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmlslt z21.d, z10.s, z5.s[1]"
diff --git a/tests/MC/AArch64/SVE2/sqdmulh.s.yaml b/tests/MC/AArch64/SVE2/sqdmulh.s.yaml
new file mode 100644
index 000000000..eb390de1c
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/sqdmulh.s.yaml
@@ -0,0 +1,140 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x70, 0x22, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmulh z0.b, z1.b, z2.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x70, 0x62, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmulh z0.h, z1.h, z2.h"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x73, 0xbf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmulh z29.s, z30.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0x73, 0xff, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmulh z31.d, z31.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf0, 0x7f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmulh z0.h, z1.h, z7.h[7]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf0, 0xbf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmulh z0.s, z1.s, z7.s[3]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf0, 0xff, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmulh z0.d, z1.d, z15.d[1]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x70, 0x22, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmulh z0.b, z1.b, z2.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x70, 0x62, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmulh z0.h, z1.h, z2.h"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x73, 0xbf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmulh z29.s, z30.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0x73, 0xff, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmulh z31.d, z31.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf0, 0x7f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmulh z0.h, z1.h, z7.h[7]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf0, 0xbf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmulh z0.s, z1.s, z7.s[3]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf0, 0xff, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmulh z0.d, z1.d, z15.d[1]"
diff --git a/tests/MC/AArch64/SVE2/sqdmullb.s.yaml b/tests/MC/AArch64/SVE2/sqdmullb.s.yaml
new file mode 100644
index 000000000..625daa864
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/sqdmullb.s.yaml
@@ -0,0 +1,100 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x60, 0x42, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmullb z0.h, z1.b, z2.b"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x63, 0x9f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmullb z29.s, z30.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x63, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmullb z31.d, z31.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe8, 0xbf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmullb z0.s, z1.h, z7.h[7]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe8, 0xef, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmullb z0.d, z1.s, z15.s[1]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x60, 0x42, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmullb z0.h, z1.b, z2.b"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x63, 0x9f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmullb z29.s, z30.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x63, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmullb z31.d, z31.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe8, 0xbf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmullb z0.s, z1.h, z7.h[7]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe8, 0xef, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmullb z0.d, z1.s, z15.s[1]"
diff --git a/tests/MC/AArch64/SVE2/sqdmullt.s.yaml b/tests/MC/AArch64/SVE2/sqdmullt.s.yaml
new file mode 100644
index 000000000..bf4a1582a
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/sqdmullt.s.yaml
@@ -0,0 +1,100 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x64, 0x42, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmullt z0.h, z1.b, z2.b"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x67, 0x9f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmullt z29.s, z30.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x67, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmullt z31.d, z31.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0xec, 0xbf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmullt z0.s, z1.h, z7.h[7]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xec, 0xef, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmullt z0.d, z1.s, z15.s[1]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x64, 0x42, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmullt z0.h, z1.b, z2.b"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x67, 0x9f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmullt z29.s, z30.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x67, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmullt z31.d, z31.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0xec, 0xbf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmullt z0.s, z1.h, z7.h[7]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xec, 0xef, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmullt z0.d, z1.s, z15.s[1]"
diff --git a/tests/MC/AArch64/SVE2/sqneg.s.yaml b/tests/MC/AArch64/SVE2/sqneg.s.yaml
new file mode 100644
index 000000000..352bbf4e3
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/sqneg.s.yaml
@@ -0,0 +1,160 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x09, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqneg z31.b, p7/m, z31.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x49, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqneg z31.h, p7/m, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x89, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqneg z31.s, p7/m, z31.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0xc9, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqneg z31.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0x3c, 0x90, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4.s, p7/z, z6.s"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xbf, 0x89, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqneg z4.s, p7/m, z31.s"
+
+  -
+    input:
+      bytes: [ 0xc4, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4, z6"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xbf, 0x89, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqneg z4.s, p7/m, z31.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x09, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqneg z31.b, p7/m, z31.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x49, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqneg z31.h, p7/m, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x89, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqneg z31.s, p7/m, z31.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0xc9, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqneg z31.d, p7/m, z31.d"
+
+  -
+    input:
+      bytes: [ 0xc4, 0x3c, 0x90, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4.s, p7/z, z6.s"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xbf, 0x89, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqneg z4.s, p7/m, z31.s"
+
+  -
+    input:
+      bytes: [ 0xc4, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4, z6"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xbf, 0x89, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqneg z4.s, p7/m, z31.s"
diff --git a/tests/MC/AArch64/SVE2/sqrdcmlah.s.yaml b/tests/MC/AArch64/SVE2/sqrdcmlah.s.yaml
new file mode 100644
index 000000000..d585a3f3c
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/sqrdcmlah.s.yaml
@@ -0,0 +1,480 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x30, 0x02, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrdcmlah z0.b, z1.b, z2.b, #0"
+
+  -
+    input:
+      bytes: [ 0x20, 0x30, 0x42, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrdcmlah z0.h, z1.h, z2.h, #0"
+
+  -
+    input:
+      bytes: [ 0x20, 0x30, 0x82, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrdcmlah z0.s, z1.s, z2.s, #0"
+
+  -
+    input:
+      bytes: [ 0x20, 0x30, 0xc2, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrdcmlah z0.d, z1.d, z2.d, #0"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x37, 0x1f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrdcmlah z29.b, z30.b, z31.b, #90"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x37, 0x5f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrdcmlah z29.h, z30.h, z31.h, #90"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x37, 0x9f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrdcmlah z29.s, z30.s, z31.s, #90"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x37, 0xdf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrdcmlah z29.d, z30.d, z31.d, #90"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3b, 0x1f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrdcmlah z31.b, z31.b, z31.b, #180"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3b, 0x5f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrdcmlah z31.h, z31.h, z31.h, #180"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3b, 0x9f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrdcmlah z31.s, z31.s, z31.s, #180"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3b, 0xdf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrdcmlah z31.d, z31.d, z31.d, #180"
+
+  -
+    input:
+      bytes: [ 0x0f, 0x3e, 0x11, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrdcmlah z15.b, z16.b, z17.b, #270"
+
+  -
+    input:
+      bytes: [ 0x0f, 0x3e, 0x51, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrdcmlah z15.h, z16.h, z17.h, #270"
+
+  -
+    input:
+      bytes: [ 0x0f, 0x3e, 0x91, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrdcmlah z15.s, z16.s, z17.s, #270"
+
+  -
+    input:
+      bytes: [ 0x0f, 0x3e, 0xd1, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrdcmlah z15.d, z16.d, z17.d, #270"
+
+  -
+    input:
+      bytes: [ 0x20, 0x70, 0xa2, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrdcmlah z0.h, z1.h, z2.h[0], #0"
+
+  -
+    input:
+      bytes: [ 0x20, 0x70, 0xe2, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrdcmlah z0.s, z1.s, z2.s[0], #0"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x7b, 0xa7, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrdcmlah z31.h, z30.h, z7.h[0], #180"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x7b, 0xe7, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrdcmlah z31.s, z30.s, z7.s[0], #180"
+
+  -
+    input:
+      bytes: [ 0xc4, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4, z6"
+
+  -
+    input:
+      bytes: [ 0xe4, 0x3f, 0xdf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrdcmlah z4.d, z31.d, z31.d, #270"
+
+  -
+    input:
+      bytes: [ 0x95, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z21, z28"
+
+  -
+    input:
+      bytes: [ 0x55, 0x75, 0xf5, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrdcmlah z21.s, z10.s, z5.s[1], #90"
+
+  -
+    input:
+      bytes: [ 0x20, 0x30, 0x02, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrdcmlah z0.b, z1.b, z2.b, #0"
+
+  -
+    input:
+      bytes: [ 0x20, 0x30, 0x42, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrdcmlah z0.h, z1.h, z2.h, #0"
+
+  -
+    input:
+      bytes: [ 0x20, 0x30, 0x82, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrdcmlah z0.s, z1.s, z2.s, #0"
+
+  -
+    input:
+      bytes: [ 0x20, 0x30, 0xc2, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrdcmlah z0.d, z1.d, z2.d, #0"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x37, 0x1f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrdcmlah z29.b, z30.b, z31.b, #90"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x37, 0x5f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrdcmlah z29.h, z30.h, z31.h, #90"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x37, 0x9f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrdcmlah z29.s, z30.s, z31.s, #90"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x37, 0xdf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrdcmlah z29.d, z30.d, z31.d, #90"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3b, 0x1f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrdcmlah z31.b, z31.b, z31.b, #180"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3b, 0x5f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrdcmlah z31.h, z31.h, z31.h, #180"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3b, 0x9f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrdcmlah z31.s, z31.s, z31.s, #180"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3b, 0xdf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrdcmlah z31.d, z31.d, z31.d, #180"
+
+  -
+    input:
+      bytes: [ 0x0f, 0x3e, 0x11, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrdcmlah z15.b, z16.b, z17.b, #270"
+
+  -
+    input:
+      bytes: [ 0x0f, 0x3e, 0x51, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrdcmlah z15.h, z16.h, z17.h, #270"
+
+  -
+    input:
+      bytes: [ 0x0f, 0x3e, 0x91, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrdcmlah z15.s, z16.s, z17.s, #270"
+
+  -
+    input:
+      bytes: [ 0x0f, 0x3e, 0xd1, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrdcmlah z15.d, z16.d, z17.d, #270"
+
+  -
+    input:
+      bytes: [ 0x20, 0x70, 0xa2, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrdcmlah z0.h, z1.h, z2.h[0], #0"
+
+  -
+    input:
+      bytes: [ 0x20, 0x70, 0xe2, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrdcmlah z0.s, z1.s, z2.s[0], #0"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x7b, 0xa7, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrdcmlah z31.h, z30.h, z7.h[0], #180"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x7b, 0xe7, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrdcmlah z31.s, z30.s, z7.s[0], #180"
+
+  -
+    input:
+      bytes: [ 0xc4, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4, z6"
+
+  -
+    input:
+      bytes: [ 0xe4, 0x3f, 0xdf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrdcmlah z4.d, z31.d, z31.d, #270"
+
+  -
+    input:
+      bytes: [ 0x95, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z21, z28"
+
+  -
+    input:
+      bytes: [ 0x55, 0x75, 0xf5, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrdcmlah z21.s, z10.s, z5.s[1], #90"
diff --git a/tests/MC/AArch64/SVE2/sqrdmlah.s.yaml b/tests/MC/AArch64/SVE2/sqrdmlah.s.yaml
new file mode 100644
index 000000000..70a46f284
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/sqrdmlah.s.yaml
@@ -0,0 +1,220 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x70, 0x1f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrdmlah z0.b, z1.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x70, 0x5f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrdmlah z0.h, z1.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x70, 0x9f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrdmlah z0.s, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x70, 0xdf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrdmlah z0.d, z1.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x10, 0x7f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrdmlah z0.h, z1.h, z7.h[7]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x10, 0xbf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrdmlah z0.s, z1.s, z7.s[3]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x10, 0xff, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrdmlah z0.d, z1.d, z15.d[1]"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x20, 0x70, 0xdf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrdmlah z0.d, z1.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x20, 0x10, 0xff, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrdmlah z0.d, z1.d, z15.d[1]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x70, 0x1f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrdmlah z0.b, z1.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x70, 0x5f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrdmlah z0.h, z1.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x70, 0x9f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrdmlah z0.s, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x70, 0xdf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrdmlah z0.d, z1.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x10, 0x7f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrdmlah z0.h, z1.h, z7.h[7]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x10, 0xbf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrdmlah z0.s, z1.s, z7.s[3]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x10, 0xff, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrdmlah z0.d, z1.d, z15.d[1]"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x20, 0x70, 0xdf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrdmlah z0.d, z1.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x20, 0x10, 0xff, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrdmlah z0.d, z1.d, z15.d[1]"
diff --git a/tests/MC/AArch64/SVE2/sqrdmlsh.s.yaml b/tests/MC/AArch64/SVE2/sqrdmlsh.s.yaml
new file mode 100644
index 000000000..8a2b1a202
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/sqrdmlsh.s.yaml
@@ -0,0 +1,220 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x74, 0x1f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrdmlsh z0.b, z1.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x74, 0x5f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrdmlsh z0.h, z1.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x74, 0x9f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrdmlsh z0.s, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x74, 0xdf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrdmlsh z0.d, z1.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x14, 0x7f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrdmlsh z0.h, z1.h, z7.h[7]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x14, 0xbf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrdmlsh z0.s, z1.s, z7.s[3]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x14, 0xff, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrdmlsh z0.d, z1.d, z15.d[1]"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x20, 0x74, 0xdf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrdmlsh z0.d, z1.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x20, 0x14, 0xff, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrdmlsh z0.d, z1.d, z15.d[1]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x74, 0x1f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrdmlsh z0.b, z1.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x74, 0x5f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrdmlsh z0.h, z1.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x74, 0x9f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrdmlsh z0.s, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x74, 0xdf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrdmlsh z0.d, z1.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x14, 0x7f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrdmlsh z0.h, z1.h, z7.h[7]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x14, 0xbf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrdmlsh z0.s, z1.s, z7.s[3]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x14, 0xff, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrdmlsh z0.d, z1.d, z15.d[1]"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x20, 0x74, 0xdf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrdmlsh z0.d, z1.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x20, 0x14, 0xff, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrdmlsh z0.d, z1.d, z15.d[1]"
diff --git a/tests/MC/AArch64/SVE2/sqrdmulh.s.yaml b/tests/MC/AArch64/SVE2/sqrdmulh.s.yaml
new file mode 100644
index 000000000..acd4a3fe3
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/sqrdmulh.s.yaml
@@ -0,0 +1,140 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x74, 0x22, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrdmulh z0.b, z1.b, z2.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x74, 0x62, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrdmulh z0.h, z1.h, z2.h"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x77, 0xbf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrdmulh z29.s, z30.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0x77, 0xff, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrdmulh z31.d, z31.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf4, 0x7f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrdmulh z0.h, z1.h, z7.h[7]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf4, 0xbf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrdmulh z0.s, z1.s, z7.s[3]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf4, 0xff, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrdmulh z0.d, z1.d, z15.d[1]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x74, 0x22, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrdmulh z0.b, z1.b, z2.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x74, 0x62, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrdmulh z0.h, z1.h, z2.h"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x77, 0xbf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrdmulh z29.s, z30.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0x77, 0xff, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrdmulh z31.d, z31.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf4, 0x7f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrdmulh z0.h, z1.h, z7.h[7]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf4, 0xbf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrdmulh z0.s, z1.s, z7.s[3]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf4, 0xff, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrdmulh z0.d, z1.d, z15.d[1]"
diff --git a/tests/MC/AArch64/SVE2/sqrshl.s.yaml b/tests/MC/AArch64/SVE2/sqrshl.s.yaml
new file mode 100644
index 000000000..d3727bf38
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/sqrshl.s.yaml
@@ -0,0 +1,160 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x0a, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshl z0.b, p0/m, z0.b, z1.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x4a, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshl z0.h, p0/m, z0.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x9f, 0x8a, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshl z29.s, p7/m, z29.s, z30.s"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xca, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshl z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31.d, p0/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x83, 0xca, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshl z31.d, p0/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xca, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshl z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x0a, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshl z0.b, p0/m, z0.b, z1.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x4a, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshl z0.h, p0/m, z0.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x9f, 0x8a, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshl z29.s, p7/m, z29.s, z30.s"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xca, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshl z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31.d, p0/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x83, 0xca, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshl z31.d, p0/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xca, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshl z31.d, p7/m, z31.d, z30.d"
diff --git a/tests/MC/AArch64/SVE2/sqrshlr.s.yaml b/tests/MC/AArch64/SVE2/sqrshlr.s.yaml
new file mode 100644
index 000000000..d2f59e2d2
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/sqrshlr.s.yaml
@@ -0,0 +1,160 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x0e, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshlr z0.b, p0/m, z0.b, z1.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x4e, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshlr z0.h, p0/m, z0.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x9f, 0x8e, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshlr z29.s, p7/m, z29.s, z30.s"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xce, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshlr z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31.d, p0/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x83, 0xce, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshlr z31.d, p0/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xce, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshlr z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x0e, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshlr z0.b, p0/m, z0.b, z1.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x4e, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshlr z0.h, p0/m, z0.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x9f, 0x8e, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshlr z29.s, p7/m, z29.s, z30.s"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xce, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshlr z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31.d, p0/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x83, 0xce, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshlr z31.d, p0/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xce, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshlr z31.d, p7/m, z31.d, z30.d"
diff --git a/tests/MC/AArch64/SVE2/sqrshrnb.s.yaml b/tests/MC/AArch64/SVE2/sqrshrnb.s.yaml
new file mode 100644
index 000000000..5b3fb2465
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/sqrshrnb.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x28, 0x2f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshrnb z0.b, z0.h, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x2b, 0x28, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshrnb z31.b, z31.h, #8"
+
+  -
+    input:
+      bytes: [ 0x00, 0x28, 0x3f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshrnb z0.h, z0.s, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x2b, 0x30, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshrnb z31.h, z31.s, #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0x28, 0x7f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshrnb z0.s, z0.d, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x2b, 0x60, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshrnb z31.s, z31.d, #32"
+
+  -
+    input:
+      bytes: [ 0x00, 0x28, 0x2f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshrnb z0.b, z0.h, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x2b, 0x28, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshrnb z31.b, z31.h, #8"
+
+  -
+    input:
+      bytes: [ 0x00, 0x28, 0x3f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshrnb z0.h, z0.s, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x2b, 0x30, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshrnb z31.h, z31.s, #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0x28, 0x7f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshrnb z0.s, z0.d, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x2b, 0x60, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshrnb z31.s, z31.d, #32"
diff --git a/tests/MC/AArch64/SVE2/sqrshrnt.s.yaml b/tests/MC/AArch64/SVE2/sqrshrnt.s.yaml
new file mode 100644
index 000000000..36d532094
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/sqrshrnt.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x2c, 0x2f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshrnt z0.b, z0.h, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x2f, 0x28, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshrnt z31.b, z31.h, #8"
+
+  -
+    input:
+      bytes: [ 0x00, 0x2c, 0x3f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshrnt z0.h, z0.s, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x2f, 0x30, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshrnt z31.h, z31.s, #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0x2c, 0x7f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshrnt z0.s, z0.d, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x2f, 0x60, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshrnt z31.s, z31.d, #32"
+
+  -
+    input:
+      bytes: [ 0x00, 0x2c, 0x2f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshrnt z0.b, z0.h, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x2f, 0x28, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshrnt z31.b, z31.h, #8"
+
+  -
+    input:
+      bytes: [ 0x00, 0x2c, 0x3f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshrnt z0.h, z0.s, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x2f, 0x30, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshrnt z31.h, z31.s, #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0x2c, 0x7f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshrnt z0.s, z0.d, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x2f, 0x60, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshrnt z31.s, z31.d, #32"
diff --git a/tests/MC/AArch64/SVE2/sqrshrunb.s.yaml b/tests/MC/AArch64/SVE2/sqrshrunb.s.yaml
new file mode 100644
index 000000000..f90899a7c
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/sqrshrunb.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x08, 0x2f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshrunb z0.b, z0.h, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x0b, 0x28, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshrunb z31.b, z31.h, #8"
+
+  -
+    input:
+      bytes: [ 0x00, 0x08, 0x3f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshrunb z0.h, z0.s, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x0b, 0x30, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshrunb z31.h, z31.s, #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0x08, 0x7f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshrunb z0.s, z0.d, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x0b, 0x60, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshrunb z31.s, z31.d, #32"
+
+  -
+    input:
+      bytes: [ 0x00, 0x08, 0x2f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshrunb z0.b, z0.h, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x0b, 0x28, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshrunb z31.b, z31.h, #8"
+
+  -
+    input:
+      bytes: [ 0x00, 0x08, 0x3f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshrunb z0.h, z0.s, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x0b, 0x30, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshrunb z31.h, z31.s, #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0x08, 0x7f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshrunb z0.s, z0.d, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x0b, 0x60, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshrunb z31.s, z31.d, #32"
diff --git a/tests/MC/AArch64/SVE2/sqrshrunt.s.yaml b/tests/MC/AArch64/SVE2/sqrshrunt.s.yaml
new file mode 100644
index 000000000..e3f5fec29
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/sqrshrunt.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x0c, 0x2f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshrunt z0.b, z0.h, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x0f, 0x28, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshrunt z31.b, z31.h, #8"
+
+  -
+    input:
+      bytes: [ 0x00, 0x0c, 0x3f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshrunt z0.h, z0.s, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x0f, 0x30, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshrunt z31.h, z31.s, #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0x0c, 0x7f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshrunt z0.s, z0.d, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x0f, 0x60, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshrunt z31.s, z31.d, #32"
+
+  -
+    input:
+      bytes: [ 0x00, 0x0c, 0x2f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshrunt z0.b, z0.h, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x0f, 0x28, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshrunt z31.b, z31.h, #8"
+
+  -
+    input:
+      bytes: [ 0x00, 0x0c, 0x3f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshrunt z0.h, z0.s, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x0f, 0x30, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshrunt z31.h, z31.s, #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0x0c, 0x7f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshrunt z0.s, z0.d, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x0f, 0x60, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshrunt z31.s, z31.d, #32"
diff --git a/tests/MC/AArch64/SVE2/sqshl.s.yaml b/tests/MC/AArch64/SVE2/sqshl.s.yaml
new file mode 100644
index 000000000..e22b0a8e8
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/sqshl.s.yaml
@@ -0,0 +1,400 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x08, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshl z0.b, p0/m, z0.b, z1.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x48, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshl z0.h, p0/m, z0.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x9f, 0x88, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshl z29.s, p7/m, z29.s, z30.s"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xc8, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshl z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x81, 0x06, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshl z0.b, p0/m, z0.b, #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0x81, 0x06, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshl z31.b, p0/m, z31.b, #7"
+
+  -
+    input:
+      bytes: [ 0x00, 0x82, 0x06, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshl z0.h, p0/m, z0.h, #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0x83, 0x06, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshl z31.h, p0/m, z31.h, #15"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x46, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshl z0.s, p0/m, z0.s, #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0x83, 0x46, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshl z31.s, p0/m, z31.s, #31"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x86, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshl z0.d, p0/m, z0.d, #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0x83, 0xc6, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshl z31.d, p0/m, z31.d, #63"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31.d, p0/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x83, 0xc8, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshl z31.d, p0/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xc8, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshl z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31.d, p0/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0x83, 0xc6, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshl z31.d, p0/m, z31.d, #63"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xff, 0x83, 0xc6, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshl z31.d, p0/m, z31.d, #63"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x08, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshl z0.b, p0/m, z0.b, z1.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x48, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshl z0.h, p0/m, z0.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x9f, 0x88, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshl z29.s, p7/m, z29.s, z30.s"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xc8, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshl z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x81, 0x06, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshl z0.b, p0/m, z0.b, #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0x81, 0x06, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshl z31.b, p0/m, z31.b, #7"
+
+  -
+    input:
+      bytes: [ 0x00, 0x82, 0x06, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshl z0.h, p0/m, z0.h, #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0x83, 0x06, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshl z31.h, p0/m, z31.h, #15"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x46, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshl z0.s, p0/m, z0.s, #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0x83, 0x46, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshl z31.s, p0/m, z31.s, #31"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x86, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshl z0.d, p0/m, z0.d, #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0x83, 0xc6, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshl z31.d, p0/m, z31.d, #63"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31.d, p0/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x83, 0xc8, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshl z31.d, p0/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xc8, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshl z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31.d, p0/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0x83, 0xc6, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshl z31.d, p0/m, z31.d, #63"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xff, 0x83, 0xc6, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshl z31.d, p0/m, z31.d, #63"
diff --git a/tests/MC/AArch64/SVE2/sqshlr.s.yaml b/tests/MC/AArch64/SVE2/sqshlr.s.yaml
new file mode 100644
index 000000000..27e376745
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/sqshlr.s.yaml
@@ -0,0 +1,160 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x0c, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshlr z0.b, p0/m, z0.b, z1.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x4c, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshlr z0.h, p0/m, z0.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x9f, 0x8c, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshlr z29.s, p7/m, z29.s, z30.s"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xcc, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshlr z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31.d, p0/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x83, 0xcc, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshlr z31.d, p0/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xcc, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshlr z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x0c, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshlr z0.b, p0/m, z0.b, z1.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x4c, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshlr z0.h, p0/m, z0.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x9f, 0x8c, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshlr z29.s, p7/m, z29.s, z30.s"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xcc, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshlr z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31.d, p0/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x83, 0xcc, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshlr z31.d, p0/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xcc, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshlr z31.d, p7/m, z31.d, z30.d"
diff --git a/tests/MC/AArch64/SVE2/sqshlu.s.yaml b/tests/MC/AArch64/SVE2/sqshlu.s.yaml
new file mode 100644
index 000000000..bbf876d09
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/sqshlu.s.yaml
@@ -0,0 +1,240 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x81, 0x0f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshlu z0.b, p0/m, z0.b, #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0x81, 0x0f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshlu z31.b, p0/m, z31.b, #7"
+
+  -
+    input:
+      bytes: [ 0x00, 0x82, 0x0f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshlu z0.h, p0/m, z0.h, #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0x83, 0x0f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshlu z31.h, p0/m, z31.h, #15"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x4f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshlu z0.s, p0/m, z0.s, #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0x83, 0x4f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshlu z31.s, p0/m, z31.s, #31"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x8f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshlu z0.d, p0/m, z0.d, #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0x83, 0xcf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshlu z31.d, p0/m, z31.d, #63"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31.d, p0/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0x83, 0xcf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshlu z31.d, p0/m, z31.d, #63"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xff, 0x83, 0xcf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshlu z31.d, p0/m, z31.d, #63"
+
+  -
+    input:
+      bytes: [ 0x00, 0x81, 0x0f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshlu z0.b, p0/m, z0.b, #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0x81, 0x0f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshlu z31.b, p0/m, z31.b, #7"
+
+  -
+    input:
+      bytes: [ 0x00, 0x82, 0x0f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshlu z0.h, p0/m, z0.h, #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0x83, 0x0f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshlu z31.h, p0/m, z31.h, #15"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x4f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshlu z0.s, p0/m, z0.s, #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0x83, 0x4f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshlu z31.s, p0/m, z31.s, #31"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x8f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshlu z0.d, p0/m, z0.d, #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0x83, 0xcf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshlu z31.d, p0/m, z31.d, #63"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31.d, p0/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0x83, 0xcf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshlu z31.d, p0/m, z31.d, #63"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xff, 0x83, 0xcf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshlu z31.d, p0/m, z31.d, #63"
diff --git a/tests/MC/AArch64/SVE2/sqshrnb.s.yaml b/tests/MC/AArch64/SVE2/sqshrnb.s.yaml
new file mode 100644
index 000000000..8955126b4
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/sqshrnb.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x2f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshrnb z0.b, z0.h, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x23, 0x28, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshrnb z31.b, z31.h, #8"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x3f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshrnb z0.h, z0.s, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x23, 0x30, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshrnb z31.h, z31.s, #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x7f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshrnb z0.s, z0.d, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x23, 0x60, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshrnb z31.s, z31.d, #32"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x2f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshrnb z0.b, z0.h, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x23, 0x28, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshrnb z31.b, z31.h, #8"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x3f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshrnb z0.h, z0.s, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x23, 0x30, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshrnb z31.h, z31.s, #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x7f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshrnb z0.s, z0.d, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x23, 0x60, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshrnb z31.s, z31.d, #32"
diff --git a/tests/MC/AArch64/SVE2/sqshrnt.s.yaml b/tests/MC/AArch64/SVE2/sqshrnt.s.yaml
new file mode 100644
index 000000000..fc2d8daad
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/sqshrnt.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x24, 0x2f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshrnt z0.b, z0.h, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x27, 0x28, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshrnt z31.b, z31.h, #8"
+
+  -
+    input:
+      bytes: [ 0x00, 0x24, 0x3f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshrnt z0.h, z0.s, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x27, 0x30, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshrnt z31.h, z31.s, #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0x24, 0x7f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshrnt z0.s, z0.d, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x27, 0x60, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshrnt z31.s, z31.d, #32"
+
+  -
+    input:
+      bytes: [ 0x00, 0x24, 0x2f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshrnt z0.b, z0.h, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x27, 0x28, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshrnt z31.b, z31.h, #8"
+
+  -
+    input:
+      bytes: [ 0x00, 0x24, 0x3f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshrnt z0.h, z0.s, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x27, 0x30, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshrnt z31.h, z31.s, #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0x24, 0x7f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshrnt z0.s, z0.d, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x27, 0x60, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshrnt z31.s, z31.d, #32"
diff --git a/tests/MC/AArch64/SVE2/sqshrunb.s.yaml b/tests/MC/AArch64/SVE2/sqshrunb.s.yaml
new file mode 100644
index 000000000..b707d1ca9
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/sqshrunb.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x2f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshrunb z0.b, z0.h, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x03, 0x28, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshrunb z31.b, z31.h, #8"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x3f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshrunb z0.h, z0.s, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x03, 0x30, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshrunb z31.h, z31.s, #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x7f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshrunb z0.s, z0.d, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x03, 0x60, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshrunb z31.s, z31.d, #32"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x2f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshrunb z0.b, z0.h, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x03, 0x28, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshrunb z31.b, z31.h, #8"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x3f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshrunb z0.h, z0.s, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x03, 0x30, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshrunb z31.h, z31.s, #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x7f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshrunb z0.s, z0.d, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x03, 0x60, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshrunb z31.s, z31.d, #32"
diff --git a/tests/MC/AArch64/SVE2/sqshrunt.s.yaml b/tests/MC/AArch64/SVE2/sqshrunt.s.yaml
new file mode 100644
index 000000000..562785aa5
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/sqshrunt.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x04, 0x2f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshrunt z0.b, z0.h, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x07, 0x28, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshrunt z31.b, z31.h, #8"
+
+  -
+    input:
+      bytes: [ 0x00, 0x04, 0x3f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshrunt z0.h, z0.s, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x07, 0x30, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshrunt z31.h, z31.s, #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0x04, 0x7f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshrunt z0.s, z0.d, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x07, 0x60, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshrunt z31.s, z31.d, #32"
+
+  -
+    input:
+      bytes: [ 0x00, 0x04, 0x2f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshrunt z0.b, z0.h, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x07, 0x28, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshrunt z31.b, z31.h, #8"
+
+  -
+    input:
+      bytes: [ 0x00, 0x04, 0x3f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshrunt z0.h, z0.s, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x07, 0x30, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshrunt z31.h, z31.s, #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0x04, 0x7f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshrunt z0.s, z0.d, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x07, 0x60, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshrunt z31.s, z31.d, #32"
diff --git a/tests/MC/AArch64/SVE2/sqsub.s.yaml b/tests/MC/AArch64/SVE2/sqsub.s.yaml
new file mode 100644
index 000000000..81bbf64a5
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/sqsub.s.yaml
@@ -0,0 +1,160 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x1a, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqsub z0.b, p0/m, z0.b, z1.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x5a, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqsub z0.h, p0/m, z0.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x9f, 0x9a, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqsub z29.s, p7/m, z29.s, z30.s"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xda, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqsub z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31.d, p0/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x83, 0xda, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqsub z31.d, p0/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xda, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqsub z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x1a, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqsub z0.b, p0/m, z0.b, z1.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x5a, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqsub z0.h, p0/m, z0.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x9f, 0x9a, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqsub z29.s, p7/m, z29.s, z30.s"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xda, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqsub z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31.d, p0/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x83, 0xda, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqsub z31.d, p0/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xda, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqsub z31.d, p7/m, z31.d, z30.d"
diff --git a/tests/MC/AArch64/SVE2/sqsubr.s.yaml b/tests/MC/AArch64/SVE2/sqsubr.s.yaml
new file mode 100644
index 000000000..4f3a5fbc6
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/sqsubr.s.yaml
@@ -0,0 +1,160 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x1e, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqsubr z0.b, p0/m, z0.b, z1.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x5e, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqsubr z0.h, p0/m, z0.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x9f, 0x9e, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqsubr z29.s, p7/m, z29.s, z30.s"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xde, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqsubr z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31.d, p0/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x83, 0xde, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqsubr z31.d, p0/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xde, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqsubr z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x1e, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqsubr z0.b, p0/m, z0.b, z1.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x5e, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqsubr z0.h, p0/m, z0.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x9f, 0x9e, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqsubr z29.s, p7/m, z29.s, z30.s"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xde, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqsubr z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31.d, p0/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x83, 0xde, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqsubr z31.d, p0/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xde, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqsubr z31.d, p7/m, z31.d, z30.d"
diff --git a/tests/MC/AArch64/SVE2/sqxtnb.s.yaml b/tests/MC/AArch64/SVE2/sqxtnb.s.yaml
new file mode 100644
index 000000000..e8496db70
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/sqxtnb.s.yaml
@@ -0,0 +1,60 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xe0, 0x43, 0x28, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqxtnb z0.b, z31.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x43, 0x30, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqxtnb z0.h, z31.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x43, 0x60, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqxtnb z0.s, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x43, 0x28, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqxtnb z0.b, z31.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x43, 0x30, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqxtnb z0.h, z31.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x43, 0x60, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqxtnb z0.s, z31.d"
diff --git a/tests/MC/AArch64/SVE2/sqxtnt.s.yaml b/tests/MC/AArch64/SVE2/sqxtnt.s.yaml
new file mode 100644
index 000000000..a03bc5a64
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/sqxtnt.s.yaml
@@ -0,0 +1,60 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xe0, 0x47, 0x28, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqxtnt z0.b, z31.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x47, 0x30, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqxtnt z0.h, z31.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x47, 0x60, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqxtnt z0.s, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x47, 0x28, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqxtnt z0.b, z31.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x47, 0x30, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqxtnt z0.h, z31.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x47, 0x60, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqxtnt z0.s, z31.d"
diff --git a/tests/MC/AArch64/SVE2/sqxtunb.s.yaml b/tests/MC/AArch64/SVE2/sqxtunb.s.yaml
new file mode 100644
index 000000000..b7f4e0b04
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/sqxtunb.s.yaml
@@ -0,0 +1,60 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xe0, 0x53, 0x28, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqxtunb z0.b, z31.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x53, 0x30, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqxtunb z0.h, z31.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x53, 0x60, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqxtunb z0.s, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x53, 0x28, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqxtunb z0.b, z31.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x53, 0x30, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqxtunb z0.h, z31.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x53, 0x60, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqxtunb z0.s, z31.d"
diff --git a/tests/MC/AArch64/SVE2/sqxtunt.s.yaml b/tests/MC/AArch64/SVE2/sqxtunt.s.yaml
new file mode 100644
index 000000000..39d4f40cf
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/sqxtunt.s.yaml
@@ -0,0 +1,60 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xe0, 0x57, 0x28, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqxtunt z0.b, z31.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x57, 0x30, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqxtunt z0.h, z31.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x57, 0x60, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqxtunt z0.s, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x57, 0x28, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqxtunt z0.b, z31.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x57, 0x30, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqxtunt z0.h, z31.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x57, 0x60, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqxtunt z0.s, z31.d"
diff --git a/tests/MC/AArch64/SVE2/srhadd.s.yaml b/tests/MC/AArch64/SVE2/srhadd.s.yaml
new file mode 100644
index 000000000..d8c9b4391
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/srhadd.s.yaml
@@ -0,0 +1,160 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x14, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "srhadd z0.b, p0/m, z0.b, z1.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x54, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "srhadd z0.h, p0/m, z0.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x9f, 0x94, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "srhadd z29.s, p7/m, z29.s, z30.s"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xd4, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "srhadd z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31.d, p0/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x83, 0xd4, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "srhadd z31.d, p0/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xd4, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "srhadd z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x14, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "srhadd z0.b, p0/m, z0.b, z1.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x54, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "srhadd z0.h, p0/m, z0.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x9f, 0x94, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "srhadd z29.s, p7/m, z29.s, z30.s"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xd4, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "srhadd z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31.d, p0/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x83, 0xd4, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "srhadd z31.d, p0/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xd4, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "srhadd z31.d, p7/m, z31.d, z30.d"
diff --git a/tests/MC/AArch64/SVE2/sri.s.yaml b/tests/MC/AArch64/SVE2/sri.s.yaml
new file mode 100644
index 000000000..4d5fcd36c
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/sri.s.yaml
@@ -0,0 +1,160 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xf0, 0x0f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sri z0.b, z0.b, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0xf3, 0x08, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sri z31.b, z31.b, #8"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf0, 0x1f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sri z0.h, z0.h, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0xf3, 0x10, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sri z31.h, z31.h, #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf0, 0x5f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sri z0.s, z0.s, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0xf3, 0x40, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sri z31.s, z31.s, #32"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf0, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sri z0.d, z0.d, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0xf3, 0x80, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sri z31.d, z31.d, #64"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf0, 0x0f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sri z0.b, z0.b, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0xf3, 0x08, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sri z31.b, z31.b, #8"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf0, 0x1f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sri z0.h, z0.h, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0xf3, 0x10, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sri z31.h, z31.h, #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf0, 0x5f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sri z0.s, z0.s, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0xf3, 0x40, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sri z31.s, z31.s, #32"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf0, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sri z0.d, z0.d, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0xf3, 0x80, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sri z31.d, z31.d, #64"
diff --git a/tests/MC/AArch64/SVE2/srshl.s.yaml b/tests/MC/AArch64/SVE2/srshl.s.yaml
new file mode 100644
index 000000000..47b5066c9
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/srshl.s.yaml
@@ -0,0 +1,160 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x02, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshl z0.b, p0/m, z0.b, z1.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x42, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshl z0.h, p0/m, z0.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x9f, 0x82, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshl z29.s, p7/m, z29.s, z30.s"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xc2, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshl z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31.d, p0/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x83, 0xc2, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshl z31.d, p0/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xc2, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshl z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x02, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshl z0.b, p0/m, z0.b, z1.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x42, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshl z0.h, p0/m, z0.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x9f, 0x82, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshl z29.s, p7/m, z29.s, z30.s"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xc2, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshl z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31.d, p0/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x83, 0xc2, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshl z31.d, p0/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xc2, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshl z31.d, p7/m, z31.d, z30.d"
diff --git a/tests/MC/AArch64/SVE2/srshlr.s.yaml b/tests/MC/AArch64/SVE2/srshlr.s.yaml
new file mode 100644
index 000000000..f23e18ed0
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/srshlr.s.yaml
@@ -0,0 +1,160 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x06, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshlr z0.b, p0/m, z0.b, z1.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x46, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshlr z0.h, p0/m, z0.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x9f, 0x86, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshlr z29.s, p7/m, z29.s, z30.s"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xc6, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshlr z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31.d, p0/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x83, 0xc6, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshlr z31.d, p0/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xc6, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshlr z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x06, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshlr z0.b, p0/m, z0.b, z1.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x46, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshlr z0.h, p0/m, z0.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x9f, 0x86, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshlr z29.s, p7/m, z29.s, z30.s"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xc6, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshlr z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31.d, p0/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x83, 0xc6, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshlr z31.d, p0/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xc6, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshlr z31.d, p7/m, z31.d, z30.d"
diff --git a/tests/MC/AArch64/SVE2/srshr.s.yaml b/tests/MC/AArch64/SVE2/srshr.s.yaml
new file mode 100644
index 000000000..d0e9051cb
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/srshr.s.yaml
@@ -0,0 +1,240 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xe0, 0x81, 0x0c, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshr z0.b, p0/m, z0.b, #1"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x81, 0x0c, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshr z31.b, p0/m, z31.b, #8"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x83, 0x0c, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshr z0.h, p0/m, z0.h, #1"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x82, 0x0c, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshr z31.h, p0/m, z31.h, #16"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x83, 0x4c, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshr z0.s, p0/m, z0.s, #1"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x80, 0x4c, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshr z31.s, p0/m, z31.s, #32"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x83, 0xcc, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshr z0.d, p0/m, z0.d, #1"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x80, 0x8c, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshr z31.d, p0/m, z31.d, #64"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31.d, p0/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x80, 0x8c, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshr z31.d, p0/m, z31.d, #64"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x80, 0x8c, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshr z31.d, p0/m, z31.d, #64"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x81, 0x0c, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshr z0.b, p0/m, z0.b, #1"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x81, 0x0c, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshr z31.b, p0/m, z31.b, #8"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x83, 0x0c, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshr z0.h, p0/m, z0.h, #1"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x82, 0x0c, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshr z31.h, p0/m, z31.h, #16"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x83, 0x4c, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshr z0.s, p0/m, z0.s, #1"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x80, 0x4c, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshr z31.s, p0/m, z31.s, #32"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x83, 0xcc, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshr z0.d, p0/m, z0.d, #1"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x80, 0x8c, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshr z31.d, p0/m, z31.d, #64"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31.d, p0/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x80, 0x8c, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshr z31.d, p0/m, z31.d, #64"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x80, 0x8c, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshr z31.d, p0/m, z31.d, #64"
diff --git a/tests/MC/AArch64/SVE2/srsra.s.yaml b/tests/MC/AArch64/SVE2/srsra.s.yaml
new file mode 100644
index 000000000..65c7cb59c
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/srsra.s.yaml
@@ -0,0 +1,200 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xe8, 0x0f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "srsra z0.b, z0.b, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0xeb, 0x08, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "srsra z31.b, z31.b, #8"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe8, 0x1f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "srsra z0.h, z0.h, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0xeb, 0x10, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "srsra z31.h, z31.h, #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe8, 0x5f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "srsra z0.s, z0.s, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0xeb, 0x40, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "srsra z31.s, z31.s, #32"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe8, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "srsra z0.d, z0.d, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0xeb, 0x80, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "srsra z31.d, z31.d, #64"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe8, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "srsra z0.d, z1.d, #1"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe8, 0x0f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "srsra z0.b, z0.b, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0xeb, 0x08, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "srsra z31.b, z31.b, #8"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe8, 0x1f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "srsra z0.h, z0.h, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0xeb, 0x10, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "srsra z31.h, z31.h, #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe8, 0x5f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "srsra z0.s, z0.s, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0xeb, 0x40, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "srsra z31.s, z31.s, #32"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe8, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "srsra z0.d, z0.d, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0xeb, 0x80, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "srsra z31.d, z31.d, #64"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe8, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "srsra z0.d, z1.d, #1"
diff --git a/tests/MC/AArch64/SVE2/sshllb.s.yaml b/tests/MC/AArch64/SVE2/sshllb.s.yaml
new file mode 100644
index 000000000..a6dc67bb1
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/sshllb.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x08, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sshllb z0.h, z0.b, #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0xa3, 0x0f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sshllb z31.h, z31.b, #7"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x10, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sshllb z0.s, z0.h, #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0xa3, 0x1f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sshllb z31.s, z31.h, #15"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x40, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sshllb z0.d, z0.s, #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0xa3, 0x5f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sshllb z31.d, z31.s, #31"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x08, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sshllb z0.h, z0.b, #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0xa3, 0x0f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sshllb z31.h, z31.b, #7"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x10, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sshllb z0.s, z0.h, #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0xa3, 0x1f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sshllb z31.s, z31.h, #15"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x40, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sshllb z0.d, z0.s, #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0xa3, 0x5f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sshllb z31.d, z31.s, #31"
diff --git a/tests/MC/AArch64/SVE2/sshllt.s.yaml b/tests/MC/AArch64/SVE2/sshllt.s.yaml
new file mode 100644
index 000000000..b87b0ef91
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/sshllt.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xa4, 0x08, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sshllt z0.h, z0.b, #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0xa7, 0x0f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sshllt z31.h, z31.b, #7"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa4, 0x10, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sshllt z0.s, z0.h, #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0xa7, 0x1f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sshllt z31.s, z31.h, #15"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa4, 0x40, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sshllt z0.d, z0.s, #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0xa7, 0x5f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sshllt z31.d, z31.s, #31"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa4, 0x08, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sshllt z0.h, z0.b, #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0xa7, 0x0f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sshllt z31.h, z31.b, #7"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa4, 0x10, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sshllt z0.s, z0.h, #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0xa7, 0x1f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sshllt z31.s, z31.h, #15"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa4, 0x40, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sshllt z0.d, z0.s, #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0xa7, 0x5f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "sshllt z31.d, z31.s, #31"
diff --git a/tests/MC/AArch64/SVE2/ssra.s.yaml b/tests/MC/AArch64/SVE2/ssra.s.yaml
new file mode 100644
index 000000000..3d8c8a58a
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/ssra.s.yaml
@@ -0,0 +1,200 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x0f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ssra z0.b, z0.b, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0xe3, 0x08, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ssra z31.b, z31.b, #8"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x1f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ssra z0.h, z0.h, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0xe3, 0x10, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ssra z31.h, z31.h, #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x5f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ssra z0.s, z0.s, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0xe3, 0x40, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ssra z31.s, z31.s, #32"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ssra z0.d, z0.d, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0xe3, 0x80, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ssra z31.d, z31.d, #64"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe0, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ssra z0.d, z1.d, #1"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x0f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ssra z0.b, z0.b, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0xe3, 0x08, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ssra z31.b, z31.b, #8"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x1f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ssra z0.h, z0.h, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0xe3, 0x10, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ssra z31.h, z31.h, #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x5f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ssra z0.s, z0.s, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0xe3, 0x40, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ssra z31.s, z31.s, #32"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ssra z0.d, z0.d, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0xe3, 0x80, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ssra z31.d, z31.d, #64"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe0, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ssra z0.d, z1.d, #1"
diff --git a/tests/MC/AArch64/SVE2/ssublb.s.yaml b/tests/MC/AArch64/SVE2/ssublb.s.yaml
new file mode 100644
index 000000000..2ec0a5e63
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/ssublb.s.yaml
@@ -0,0 +1,60 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x10, 0x42, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ssublb z0.h, z1.b, z2.b"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x13, 0x9f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ssublb z29.s, z30.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x13, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ssublb z31.d, z31.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x10, 0x42, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ssublb z0.h, z1.b, z2.b"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x13, 0x9f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ssublb z29.s, z30.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x13, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ssublb z31.d, z31.s, z31.s"
diff --git a/tests/MC/AArch64/SVE2/ssublbt.s.yaml b/tests/MC/AArch64/SVE2/ssublbt.s.yaml
new file mode 100644
index 000000000..81272feae
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/ssublbt.s.yaml
@@ -0,0 +1,60 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x88, 0x5f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ssublbt z0.h, z1.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x88, 0x9f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ssublbt z0.s, z1.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x88, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ssublbt z0.d, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x88, 0x5f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ssublbt z0.h, z1.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x88, 0x9f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ssublbt z0.s, z1.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x88, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ssublbt z0.d, z1.s, z31.s"
diff --git a/tests/MC/AArch64/SVE2/ssublt.s.yaml b/tests/MC/AArch64/SVE2/ssublt.s.yaml
new file mode 100644
index 000000000..71578eb29
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/ssublt.s.yaml
@@ -0,0 +1,60 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x14, 0x42, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ssublt z0.h, z1.b, z2.b"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x17, 0x9f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ssublt z29.s, z30.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x17, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ssublt z31.d, z31.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x14, 0x42, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ssublt z0.h, z1.b, z2.b"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x17, 0x9f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ssublt z29.s, z30.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x17, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ssublt z31.d, z31.s, z31.s"
diff --git a/tests/MC/AArch64/SVE2/ssubltb.s.yaml b/tests/MC/AArch64/SVE2/ssubltb.s.yaml
new file mode 100644
index 000000000..1e6015530
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/ssubltb.s.yaml
@@ -0,0 +1,60 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x8c, 0x5f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ssubltb z0.h, z1.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x8c, 0x9f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ssubltb z0.s, z1.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x8c, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ssubltb z0.d, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x8c, 0x5f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ssubltb z0.h, z1.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x8c, 0x9f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ssubltb z0.s, z1.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x8c, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ssubltb z0.d, z1.s, z31.s"
diff --git a/tests/MC/AArch64/SVE2/ssubwb.s.yaml b/tests/MC/AArch64/SVE2/ssubwb.s.yaml
new file mode 100644
index 000000000..8ac090edc
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/ssubwb.s.yaml
@@ -0,0 +1,60 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x50, 0x42, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ssubwb z0.h, z1.h, z2.b"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x53, 0x9f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ssubwb z29.s, z30.s, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x53, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ssubwb z31.d, z31.d, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x50, 0x42, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ssubwb z0.h, z1.h, z2.b"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x53, 0x9f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ssubwb z29.s, z30.s, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x53, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ssubwb z31.d, z31.d, z31.s"
diff --git a/tests/MC/AArch64/SVE2/ssubwt.s.yaml b/tests/MC/AArch64/SVE2/ssubwt.s.yaml
new file mode 100644
index 000000000..35423b748
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/ssubwt.s.yaml
@@ -0,0 +1,60 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x54, 0x42, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ssubwt z0.h, z1.h, z2.b"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x57, 0x9f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ssubwt z29.s, z30.s, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x57, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ssubwt z31.d, z31.d, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x54, 0x42, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ssubwt z0.h, z1.h, z2.b"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x57, 0x9f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ssubwt z29.s, z30.s, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x57, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ssubwt z31.d, z31.d, z31.s"
diff --git a/tests/MC/AArch64/SVE2/stnt1b.s.yaml b/tests/MC/AArch64/SVE2/stnt1b.s.yaml
new file mode 100644
index 000000000..f3c3ec8a6
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/stnt1b.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x20, 0x5f, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1b { z0.s }, p0, [z1.s]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0x5f, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1b { z31.s }, p7, [z31.s]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0x40, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1b { z31.s }, p7, [z31.s, x0]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x20, 0x1f, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1b { z0.d }, p0, [z1.d]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0x1f, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1b { z31.d }, p7, [z31.d]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0x00, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1b { z31.d }, p7, [z31.d, x0]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x20, 0x5f, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1b { z0.s }, p0, [z1.s]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0x5f, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1b { z31.s }, p7, [z31.s]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0x40, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1b { z31.s }, p7, [z31.s, x0]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x20, 0x1f, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1b { z0.d }, p0, [z1.d]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0x1f, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1b { z31.d }, p7, [z31.d]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0x00, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1b { z31.d }, p7, [z31.d, x0]"
diff --git a/tests/MC/AArch64/SVE2/stnt1d.s.yaml b/tests/MC/AArch64/SVE2/stnt1d.s.yaml
new file mode 100644
index 000000000..39801b643
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/stnt1d.s.yaml
@@ -0,0 +1,60 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x20, 0x9f, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1d { z0.d }, p0, [z1.d]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0x9f, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1d { z31.d }, p7, [z31.d]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0x80, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1d { z31.d }, p7, [z31.d, x0]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x20, 0x9f, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1d { z0.d }, p0, [z1.d]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0x9f, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1d { z31.d }, p7, [z31.d]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0x80, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1d { z31.d }, p7, [z31.d, x0]"
diff --git a/tests/MC/AArch64/SVE2/stnt1h.s.yaml b/tests/MC/AArch64/SVE2/stnt1h.s.yaml
new file mode 100644
index 000000000..5693d8a53
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/stnt1h.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x20, 0xdf, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1h { z0.s }, p0, [z1.s]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0xdf, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1h { z31.s }, p7, [z31.s]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0xc0, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1h { z31.s }, p7, [z31.s, x0]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x20, 0x9f, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1h { z0.d }, p0, [z1.d]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0x9f, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1h { z31.d }, p7, [z31.d]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0x80, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1h { z31.d }, p7, [z31.d, x0]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x20, 0xdf, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1h { z0.s }, p0, [z1.s]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0xdf, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1h { z31.s }, p7, [z31.s]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0xc0, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1h { z31.s }, p7, [z31.s, x0]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x20, 0x9f, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1h { z0.d }, p0, [z1.d]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0x9f, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1h { z31.d }, p7, [z31.d]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0x80, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1h { z31.d }, p7, [z31.d, x0]"
diff --git a/tests/MC/AArch64/SVE2/stnt1w.s.yaml b/tests/MC/AArch64/SVE2/stnt1w.s.yaml
new file mode 100644
index 000000000..7554bb03c
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/stnt1w.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x20, 0x5f, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1w { z0.s }, p0, [z1.s]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0x5f, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1w { z31.s }, p7, [z31.s]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0x40, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1w { z31.s }, p7, [z31.s, x0]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x20, 0x1f, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1w { z0.d }, p0, [z1.d]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0x1f, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1w { z31.d }, p7, [z31.d]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0x00, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1w { z31.d }, p7, [z31.d, x0]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x20, 0x5f, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1w { z0.s }, p0, [z1.s]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0x5f, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1w { z31.s }, p7, [z31.s]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0x40, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1w { z31.s }, p7, [z31.s, x0]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x20, 0x1f, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1w { z0.d }, p0, [z1.d]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0x1f, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1w { z31.d }, p7, [z31.d]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0x00, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1w { z31.d }, p7, [z31.d, x0]"
diff --git a/tests/MC/AArch64/SVE2/subhnb.s.yaml b/tests/MC/AArch64/SVE2/subhnb.s.yaml
new file mode 100644
index 000000000..a2367e891
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/subhnb.s.yaml
@@ -0,0 +1,60 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x70, 0x7f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "subhnb z0.b, z1.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x70, 0xbf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "subhnb z0.h, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x70, 0xff, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "subhnb z0.s, z1.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x70, 0x7f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "subhnb z0.b, z1.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x70, 0xbf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "subhnb z0.h, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x70, 0xff, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "subhnb z0.s, z1.d, z31.d"
diff --git a/tests/MC/AArch64/SVE2/subhnt.s.yaml b/tests/MC/AArch64/SVE2/subhnt.s.yaml
new file mode 100644
index 000000000..1de1714a6
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/subhnt.s.yaml
@@ -0,0 +1,60 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x74, 0x7f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "subhnt z0.b, z1.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x74, 0xbf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "subhnt z0.h, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x74, 0xff, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "subhnt z0.s, z1.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x74, 0x7f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "subhnt z0.b, z1.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x74, 0xbf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "subhnt z0.h, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x74, 0xff, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "subhnt z0.s, z1.d, z31.d"
diff --git a/tests/MC/AArch64/SVE2/suqadd.s.yaml b/tests/MC/AArch64/SVE2/suqadd.s.yaml
new file mode 100644
index 000000000..2366fac75
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/suqadd.s.yaml
@@ -0,0 +1,160 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x1c, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "suqadd z0.b, p0/m, z0.b, z1.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x5c, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "suqadd z0.h, p0/m, z0.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x9f, 0x9c, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "suqadd z29.s, p7/m, z29.s, z30.s"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xdc, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "suqadd z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31.d, p0/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x83, 0xdc, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "suqadd z31.d, p0/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xdc, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "suqadd z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x1c, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "suqadd z0.b, p0/m, z0.b, z1.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x5c, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "suqadd z0.h, p0/m, z0.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x9f, 0x9c, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "suqadd z29.s, p7/m, z29.s, z30.s"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xdc, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "suqadd z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31.d, p0/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x83, 0xdc, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "suqadd z31.d, p0/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xdc, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "suqadd z31.d, p7/m, z31.d, z30.d"
diff --git a/tests/MC/AArch64/SVE2/tbl.s.yaml b/tests/MC/AArch64/SVE2/tbl.s.yaml
new file mode 100644
index 000000000..4b69f7e06
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/tbl.s.yaml
@@ -0,0 +1,80 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xbc, 0x2b, 0x3f, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "tbl z28.b, { z29.b, z30.b }, z31.b"
+
+  -
+    input:
+      bytes: [ 0xbc, 0x2b, 0x7f, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "tbl z28.h, { z29.h, z30.h }, z31.h"
+
+  -
+    input:
+      bytes: [ 0xbc, 0x2b, 0xbf, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "tbl z28.s, { z29.s, z30.s }, z31.s"
+
+  -
+    input:
+      bytes: [ 0xbc, 0x2b, 0xff, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "tbl z28.d, { z29.d, z30.d }, z31.d"
+
+  -
+    input:
+      bytes: [ 0xbc, 0x2b, 0x3f, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "tbl z28.b, { z29.b, z30.b }, z31.b"
+
+  -
+    input:
+      bytes: [ 0xbc, 0x2b, 0x7f, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "tbl z28.h, { z29.h, z30.h }, z31.h"
+
+  -
+    input:
+      bytes: [ 0xbc, 0x2b, 0xbf, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "tbl z28.s, { z29.s, z30.s }, z31.s"
+
+  -
+    input:
+      bytes: [ 0xbc, 0x2b, 0xff, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "tbl z28.d, { z29.d, z30.d }, z31.d"
diff --git a/tests/MC/AArch64/SVE2/tbx.s.yaml b/tests/MC/AArch64/SVE2/tbx.s.yaml
new file mode 100644
index 000000000..305c1c2a9
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/tbx.s.yaml
@@ -0,0 +1,80 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xff, 0x2f, 0x3f, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "tbx z31.b, z31.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x2f, 0x7f, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "tbx z31.h, z31.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x2f, 0xbf, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "tbx z31.s, z31.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0x2f, 0xff, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "tbx z31.d, z31.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0x2f, 0x3f, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "tbx z31.b, z31.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x2f, 0x7f, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "tbx z31.h, z31.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x2f, 0xbf, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "tbx z31.s, z31.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0x2f, 0xff, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "tbx z31.d, z31.d, z31.d"
diff --git a/tests/MC/AArch64/SVE2/uaba.s.yaml b/tests/MC/AArch64/SVE2/uaba.s.yaml
new file mode 100644
index 000000000..e030597e1
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/uaba.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0xfc, 0x1f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uaba z0.b, z1.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0xfc, 0x5f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uaba z0.h, z1.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0xfc, 0x9f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uaba z0.s, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0xfc, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uaba z0.d, z1.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x20, 0xfc, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uaba z0.d, z1.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0xfc, 0x1f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uaba z0.b, z1.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0xfc, 0x5f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uaba z0.h, z1.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0xfc, 0x9f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uaba z0.s, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0xfc, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uaba z0.d, z1.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x20, 0xfc, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uaba z0.d, z1.d, z31.d"
diff --git a/tests/MC/AArch64/SVE2/uabalb.s.yaml b/tests/MC/AArch64/SVE2/uabalb.s.yaml
new file mode 100644
index 000000000..b279a8195
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/uabalb.s.yaml
@@ -0,0 +1,100 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0xc8, 0x5f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uabalb z0.h, z1.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc8, 0x9f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uabalb z0.s, z1.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc8, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uabalb z0.d, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x95, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z21, z28"
+
+  -
+    input:
+      bytes: [ 0x35, 0xc8, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uabalb z21.d, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc8, 0x5f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uabalb z0.h, z1.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc8, 0x9f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uabalb z0.s, z1.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc8, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uabalb z0.d, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x95, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z21, z28"
+
+  -
+    input:
+      bytes: [ 0x35, 0xc8, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uabalb z21.d, z1.s, z31.s"
diff --git a/tests/MC/AArch64/SVE2/uabalt.s.yaml b/tests/MC/AArch64/SVE2/uabalt.s.yaml
new file mode 100644
index 000000000..a5882df5f
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/uabalt.s.yaml
@@ -0,0 +1,100 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0xcc, 0x5f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uabalt z0.h, z1.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0xcc, 0x9f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uabalt z0.s, z1.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0xcc, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uabalt z0.d, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x95, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z21, z28"
+
+  -
+    input:
+      bytes: [ 0x35, 0xcc, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uabalt z21.d, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0xcc, 0x5f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uabalt z0.h, z1.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0xcc, 0x9f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uabalt z0.s, z1.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0xcc, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uabalt z0.d, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x95, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z21, z28"
+
+  -
+    input:
+      bytes: [ 0x35, 0xcc, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uabalt z21.d, z1.s, z31.s"
diff --git a/tests/MC/AArch64/SVE2/uabdlb.s.yaml b/tests/MC/AArch64/SVE2/uabdlb.s.yaml
new file mode 100644
index 000000000..e0835213d
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/uabdlb.s.yaml
@@ -0,0 +1,60 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x38, 0x42, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uabdlb z0.h, z1.b, z2.b"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x3b, 0x9f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uabdlb z29.s, z30.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3b, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uabdlb z31.d, z31.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x38, 0x42, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uabdlb z0.h, z1.b, z2.b"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x3b, 0x9f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uabdlb z29.s, z30.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3b, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uabdlb z31.d, z31.s, z31.s"
diff --git a/tests/MC/AArch64/SVE2/uabdlt.s.yaml b/tests/MC/AArch64/SVE2/uabdlt.s.yaml
new file mode 100644
index 000000000..90496d267
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/uabdlt.s.yaml
@@ -0,0 +1,60 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x3c, 0x42, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uabdlt z0.h, z1.b, z2.b"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x3f, 0x9f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uabdlt z29.s, z30.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uabdlt z31.d, z31.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x3c, 0x42, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uabdlt z0.h, z1.b, z2.b"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x3f, 0x9f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uabdlt z29.s, z30.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uabdlt z31.d, z31.s, z31.s"
diff --git a/tests/MC/AArch64/SVE2/uadalp.s.yaml b/tests/MC/AArch64/SVE2/uadalp.s.yaml
new file mode 100644
index 000000000..6e0d7eab3
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/uadalp.s.yaml
@@ -0,0 +1,140 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0xa0, 0x45, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uadalp z0.h, p0/m, z1.b"
+
+  -
+    input:
+      bytes: [ 0xdd, 0xa3, 0x85, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uadalp z29.s, p0/m, z30.h"
+
+  -
+    input:
+      bytes: [ 0xfe, 0xbf, 0xc5, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uadalp z30.d, p7/m, z31.s"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31.d, p0/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xa3, 0xc5, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uadalp z31.d, p0/m, z30.s"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xa3, 0xc5, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uadalp z31.d, p0/m, z30.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa0, 0x45, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uadalp z0.h, p0/m, z1.b"
+
+  -
+    input:
+      bytes: [ 0xdd, 0xa3, 0x85, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uadalp z29.s, p0/m, z30.h"
+
+  -
+    input:
+      bytes: [ 0xfe, 0xbf, 0xc5, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uadalp z30.d, p7/m, z31.s"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31.d, p0/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xa3, 0xc5, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uadalp z31.d, p0/m, z30.s"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xa3, 0xc5, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uadalp z31.d, p0/m, z30.s"
diff --git a/tests/MC/AArch64/SVE2/uaddlb.s.yaml b/tests/MC/AArch64/SVE2/uaddlb.s.yaml
new file mode 100644
index 000000000..cabe957fd
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/uaddlb.s.yaml
@@ -0,0 +1,60 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x08, 0x42, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uaddlb z0.h, z1.b, z2.b"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x0b, 0x9f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uaddlb z29.s, z30.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x0b, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uaddlb z31.d, z31.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x08, 0x42, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uaddlb z0.h, z1.b, z2.b"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x0b, 0x9f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uaddlb z29.s, z30.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x0b, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uaddlb z31.d, z31.s, z31.s"
diff --git a/tests/MC/AArch64/SVE2/uaddlt.s.yaml b/tests/MC/AArch64/SVE2/uaddlt.s.yaml
new file mode 100644
index 000000000..f65753fa0
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/uaddlt.s.yaml
@@ -0,0 +1,60 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x0c, 0x42, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uaddlt z0.h, z1.b, z2.b"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x0f, 0x9f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uaddlt z29.s, z30.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x0f, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uaddlt z31.d, z31.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x0c, 0x42, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uaddlt z0.h, z1.b, z2.b"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x0f, 0x9f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uaddlt z29.s, z30.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x0f, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uaddlt z31.d, z31.s, z31.s"
diff --git a/tests/MC/AArch64/SVE2/uaddwb.s.yaml b/tests/MC/AArch64/SVE2/uaddwb.s.yaml
new file mode 100644
index 000000000..b1d392dff
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/uaddwb.s.yaml
@@ -0,0 +1,60 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x48, 0x42, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uaddwb z0.h, z1.h, z2.b"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x4b, 0x9f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uaddwb z29.s, z30.s, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x4b, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uaddwb z31.d, z31.d, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x48, 0x42, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uaddwb z0.h, z1.h, z2.b"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x4b, 0x9f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uaddwb z29.s, z30.s, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x4b, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uaddwb z31.d, z31.d, z31.s"
diff --git a/tests/MC/AArch64/SVE2/uaddwt.s.yaml b/tests/MC/AArch64/SVE2/uaddwt.s.yaml
new file mode 100644
index 000000000..f5a4d906a
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/uaddwt.s.yaml
@@ -0,0 +1,60 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x4c, 0x42, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uaddwt z0.h, z1.h, z2.b"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x4f, 0x9f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uaddwt z29.s, z30.s, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x4f, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uaddwt z31.d, z31.d, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x4c, 0x42, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uaddwt z0.h, z1.h, z2.b"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x4f, 0x9f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uaddwt z29.s, z30.s, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x4f, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uaddwt z31.d, z31.d, z31.s"
diff --git a/tests/MC/AArch64/SVE2/uhadd.s.yaml b/tests/MC/AArch64/SVE2/uhadd.s.yaml
new file mode 100644
index 000000000..1db9d9834
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/uhadd.s.yaml
@@ -0,0 +1,160 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x11, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uhadd z0.b, p0/m, z0.b, z1.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x51, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uhadd z0.h, p0/m, z0.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x9f, 0x91, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uhadd z29.s, p7/m, z29.s, z30.s"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xd1, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uhadd z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31.d, p0/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x83, 0xd1, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uhadd z31.d, p0/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xd1, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uhadd z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x11, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uhadd z0.b, p0/m, z0.b, z1.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x51, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uhadd z0.h, p0/m, z0.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x9f, 0x91, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uhadd z29.s, p7/m, z29.s, z30.s"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xd1, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uhadd z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31.d, p0/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x83, 0xd1, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uhadd z31.d, p0/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xd1, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uhadd z31.d, p7/m, z31.d, z30.d"
diff --git a/tests/MC/AArch64/SVE2/uhsub.s.yaml b/tests/MC/AArch64/SVE2/uhsub.s.yaml
new file mode 100644
index 000000000..f02ac22d6
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/uhsub.s.yaml
@@ -0,0 +1,160 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x13, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uhsub z0.b, p0/m, z0.b, z1.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x53, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uhsub z0.h, p0/m, z0.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x9f, 0x93, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uhsub z29.s, p7/m, z29.s, z30.s"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xd3, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uhsub z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31.d, p0/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x83, 0xd3, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uhsub z31.d, p0/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xd3, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uhsub z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x13, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uhsub z0.b, p0/m, z0.b, z1.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x53, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uhsub z0.h, p0/m, z0.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x9f, 0x93, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uhsub z29.s, p7/m, z29.s, z30.s"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xd3, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uhsub z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31.d, p0/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x83, 0xd3, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uhsub z31.d, p0/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xd3, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uhsub z31.d, p7/m, z31.d, z30.d"
diff --git a/tests/MC/AArch64/SVE2/uhsubr.s.yaml b/tests/MC/AArch64/SVE2/uhsubr.s.yaml
new file mode 100644
index 000000000..fcd864e2f
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/uhsubr.s.yaml
@@ -0,0 +1,160 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x17, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uhsubr z0.b, p0/m, z0.b, z1.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x57, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uhsubr z0.h, p0/m, z0.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x9f, 0x97, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uhsubr z29.s, p7/m, z29.s, z30.s"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xd7, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uhsubr z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31.d, p0/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x83, 0xd7, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uhsubr z31.d, p0/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xd7, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uhsubr z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x17, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uhsubr z0.b, p0/m, z0.b, z1.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x57, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uhsubr z0.h, p0/m, z0.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x9f, 0x97, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uhsubr z29.s, p7/m, z29.s, z30.s"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xd7, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uhsubr z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31.d, p0/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x83, 0xd7, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uhsubr z31.d, p0/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xd7, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uhsubr z31.d, p7/m, z31.d, z30.d"
diff --git a/tests/MC/AArch64/SVE2/umaxp.s.yaml b/tests/MC/AArch64/SVE2/umaxp.s.yaml
new file mode 100644
index 000000000..953c36459
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/umaxp.s.yaml
@@ -0,0 +1,160 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0xa0, 0x15, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umaxp z0.b, p0/m, z0.b, z1.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa0, 0x55, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umaxp z0.h, p0/m, z0.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0xdd, 0xbf, 0x95, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umaxp z29.s, p7/m, z29.s, z30.s"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbf, 0xd5, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umaxp z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31.d, p0/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xa3, 0xd5, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umaxp z31.d, p0/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbf, 0xd5, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umaxp z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa0, 0x15, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "umaxp z0.b, p0/m, z0.b, z1.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa0, 0x55, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "umaxp z0.h, p0/m, z0.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0xdd, 0xbf, 0x95, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "umaxp z29.s, p7/m, z29.s, z30.s"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbf, 0xd5, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "umaxp z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31.d, p0/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xa3, 0xd5, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "umaxp z31.d, p0/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbf, 0xd5, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "umaxp z31.d, p7/m, z31.d, z30.d"
diff --git a/tests/MC/AArch64/SVE2/uminp.s.yaml b/tests/MC/AArch64/SVE2/uminp.s.yaml
new file mode 100644
index 000000000..2c704e7bb
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/uminp.s.yaml
@@ -0,0 +1,160 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0xa0, 0x17, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uminp z0.b, p0/m, z0.b, z1.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa0, 0x57, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uminp z0.h, p0/m, z0.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0xdd, 0xbf, 0x97, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uminp z29.s, p7/m, z29.s, z30.s"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbf, 0xd7, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uminp z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31.d, p0/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xa3, 0xd7, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uminp z31.d, p0/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbf, 0xd7, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uminp z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa0, 0x17, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uminp z0.b, p0/m, z0.b, z1.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa0, 0x57, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uminp z0.h, p0/m, z0.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0xdd, 0xbf, 0x97, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uminp z29.s, p7/m, z29.s, z30.s"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbf, 0xd7, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uminp z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31.d, p0/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xa3, 0xd7, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uminp z31.d, p0/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbf, 0xd7, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uminp z31.d, p7/m, z31.d, z30.d"
diff --git a/tests/MC/AArch64/SVE2/umlalb.s.yaml b/tests/MC/AArch64/SVE2/umlalb.s.yaml
new file mode 100644
index 000000000..58e31e65d
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/umlalb.s.yaml
@@ -0,0 +1,180 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x48, 0x5f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlalb z0.h, z1.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x48, 0x9f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlalb z0.s, z1.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x48, 0xdf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlalb z0.d, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x98, 0xbf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlalb z0.s, z1.h, z7.h[7]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x98, 0xef, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlalb z0.d, z1.s, z15.s[1]"
+
+  -
+    input:
+      bytes: [ 0x95, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z21, z28"
+
+  -
+    input:
+      bytes: [ 0x35, 0x48, 0xdf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlalb z21.d, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x95, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z21, z28"
+
+  -
+    input:
+      bytes: [ 0x55, 0x99, 0xe5, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlalb z21.d, z10.s, z5.s[1]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x48, 0x5f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlalb z0.h, z1.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x48, 0x9f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlalb z0.s, z1.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x48, 0xdf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlalb z0.d, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x98, 0xbf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlalb z0.s, z1.h, z7.h[7]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x98, 0xef, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlalb z0.d, z1.s, z15.s[1]"
+
+  -
+    input:
+      bytes: [ 0x95, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z21, z28"
+
+  -
+    input:
+      bytes: [ 0x35, 0x48, 0xdf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlalb z21.d, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x95, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z21, z28"
+
+  -
+    input:
+      bytes: [ 0x55, 0x99, 0xe5, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlalb z21.d, z10.s, z5.s[1]"
diff --git a/tests/MC/AArch64/SVE2/umlalt.s.yaml b/tests/MC/AArch64/SVE2/umlalt.s.yaml
new file mode 100644
index 000000000..453cc1cbc
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/umlalt.s.yaml
@@ -0,0 +1,180 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x4c, 0x5f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlalt z0.h, z1.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x4c, 0x9f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlalt z0.s, z1.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x4c, 0xdf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlalt z0.d, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x9c, 0xbf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlalt z0.s, z1.h, z7.h[7]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x9c, 0xef, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlalt z0.d, z1.s, z15.s[1]"
+
+  -
+    input:
+      bytes: [ 0x95, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z21, z28"
+
+  -
+    input:
+      bytes: [ 0x35, 0x4c, 0xdf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlalt z21.d, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x95, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z21, z28"
+
+  -
+    input:
+      bytes: [ 0x55, 0x9d, 0xe5, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlalt z21.d, z10.s, z5.s[1]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x4c, 0x5f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlalt z0.h, z1.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x4c, 0x9f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlalt z0.s, z1.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x4c, 0xdf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlalt z0.d, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x9c, 0xbf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlalt z0.s, z1.h, z7.h[7]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x9c, 0xef, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlalt z0.d, z1.s, z15.s[1]"
+
+  -
+    input:
+      bytes: [ 0x95, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z21, z28"
+
+  -
+    input:
+      bytes: [ 0x35, 0x4c, 0xdf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlalt z21.d, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x95, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z21, z28"
+
+  -
+    input:
+      bytes: [ 0x55, 0x9d, 0xe5, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlalt z21.d, z10.s, z5.s[1]"
diff --git a/tests/MC/AArch64/SVE2/umlslb.s.yaml b/tests/MC/AArch64/SVE2/umlslb.s.yaml
new file mode 100644
index 000000000..86ccec243
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/umlslb.s.yaml
@@ -0,0 +1,180 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x58, 0x5f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlslb z0.h, z1.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x58, 0x9f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlslb z0.s, z1.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x58, 0xdf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlslb z0.d, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0xb8, 0xbf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlslb z0.s, z1.h, z7.h[7]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xb8, 0xef, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlslb z0.d, z1.s, z15.s[1]"
+
+  -
+    input:
+      bytes: [ 0x95, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z21, z28"
+
+  -
+    input:
+      bytes: [ 0x35, 0x58, 0xdf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlslb z21.d, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x95, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z21, z28"
+
+  -
+    input:
+      bytes: [ 0x55, 0xb9, 0xe5, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlslb z21.d, z10.s, z5.s[1]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x58, 0x5f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlslb z0.h, z1.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x58, 0x9f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlslb z0.s, z1.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x58, 0xdf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlslb z0.d, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0xb8, 0xbf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlslb z0.s, z1.h, z7.h[7]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xb8, 0xef, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlslb z0.d, z1.s, z15.s[1]"
+
+  -
+    input:
+      bytes: [ 0x95, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z21, z28"
+
+  -
+    input:
+      bytes: [ 0x35, 0x58, 0xdf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlslb z21.d, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x95, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z21, z28"
+
+  -
+    input:
+      bytes: [ 0x55, 0xb9, 0xe5, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlslb z21.d, z10.s, z5.s[1]"
diff --git a/tests/MC/AArch64/SVE2/umlslt.s.yaml b/tests/MC/AArch64/SVE2/umlslt.s.yaml
new file mode 100644
index 000000000..010e840b6
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/umlslt.s.yaml
@@ -0,0 +1,180 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x5c, 0x5f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlslt z0.h, z1.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x5c, 0x9f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlslt z0.s, z1.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x5c, 0xdf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlslt z0.d, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0xbc, 0xbf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlslt z0.s, z1.h, z7.h[7]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xbc, 0xef, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlslt z0.d, z1.s, z15.s[1]"
+
+  -
+    input:
+      bytes: [ 0x95, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z21, z28"
+
+  -
+    input:
+      bytes: [ 0x35, 0x5c, 0xdf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlslt z21.d, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x95, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z21, z28"
+
+  -
+    input:
+      bytes: [ 0x55, 0xbd, 0xe5, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlslt z21.d, z10.s, z5.s[1]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x5c, 0x5f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlslt z0.h, z1.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x5c, 0x9f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlslt z0.s, z1.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x5c, 0xdf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlslt z0.d, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0xbc, 0xbf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlslt z0.s, z1.h, z7.h[7]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xbc, 0xef, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlslt z0.d, z1.s, z15.s[1]"
+
+  -
+    input:
+      bytes: [ 0x95, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z21, z28"
+
+  -
+    input:
+      bytes: [ 0x35, 0x5c, 0xdf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlslt z21.d, z1.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x95, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z21, z28"
+
+  -
+    input:
+      bytes: [ 0x55, 0xbd, 0xe5, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlslt z21.d, z10.s, z5.s[1]"
diff --git a/tests/MC/AArch64/SVE2/umulh.s.yaml b/tests/MC/AArch64/SVE2/umulh.s.yaml
new file mode 100644
index 000000000..248e117c3
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/umulh.s.yaml
@@ -0,0 +1,80 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x6c, 0x22, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umulh z0.b, z1.b, z2.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x6c, 0x62, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umulh z0.h, z1.h, z2.h"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x6f, 0xbf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umulh z29.s, z30.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0x6f, 0xff, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umulh z31.d, z31.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x6c, 0x22, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "umulh z0.b, z1.b, z2.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x6c, 0x62, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "umulh z0.h, z1.h, z2.h"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x6f, 0xbf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "umulh z29.s, z30.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0x6f, 0xff, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "umulh z31.d, z31.d, z31.d"
diff --git a/tests/MC/AArch64/SVE2/umullb.s.yaml b/tests/MC/AArch64/SVE2/umullb.s.yaml
new file mode 100644
index 000000000..6470beee6
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/umullb.s.yaml
@@ -0,0 +1,100 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x78, 0x42, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umullb z0.h, z1.b, z2.b"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x7b, 0x9f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umullb z29.s, z30.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x7b, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umullb z31.d, z31.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd8, 0xbf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umullb z0.s, z1.h, z7.h[7]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd8, 0xef, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umullb z0.d, z1.s, z15.s[1]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x78, 0x42, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "umullb z0.h, z1.b, z2.b"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x7b, 0x9f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "umullb z29.s, z30.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x7b, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "umullb z31.d, z31.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd8, 0xbf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "umullb z0.s, z1.h, z7.h[7]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd8, 0xef, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "umullb z0.d, z1.s, z15.s[1]"
diff --git a/tests/MC/AArch64/SVE2/umullt.s.yaml b/tests/MC/AArch64/SVE2/umullt.s.yaml
new file mode 100644
index 000000000..749463dc9
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/umullt.s.yaml
@@ -0,0 +1,100 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x7c, 0x42, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umullt z0.h, z1.b, z2.b"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x7f, 0x9f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umullt z29.s, z30.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x7f, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umullt z31.d, z31.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0xdc, 0xbf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umullt z0.s, z1.h, z7.h[7]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xdc, 0xef, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "umullt z0.d, z1.s, z15.s[1]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x7c, 0x42, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "umullt z0.h, z1.b, z2.b"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x7f, 0x9f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "umullt z29.s, z30.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x7f, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "umullt z31.d, z31.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0xdc, 0xbf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "umullt z0.s, z1.h, z7.h[7]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xdc, 0xef, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "umullt z0.d, z1.s, z15.s[1]"
diff --git a/tests/MC/AArch64/SVE2/uqadd.s.yaml b/tests/MC/AArch64/SVE2/uqadd.s.yaml
new file mode 100644
index 000000000..95df9fd90
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/uqadd.s.yaml
@@ -0,0 +1,160 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x19, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqadd z0.b, p0/m, z0.b, z1.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x59, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqadd z0.h, p0/m, z0.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x9f, 0x99, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqadd z29.s, p7/m, z29.s, z30.s"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xd9, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqadd z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31.d, p0/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x83, 0xd9, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqadd z31.d, p0/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xd9, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqadd z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x19, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqadd z0.b, p0/m, z0.b, z1.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x59, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqadd z0.h, p0/m, z0.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x9f, 0x99, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqadd z29.s, p7/m, z29.s, z30.s"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xd9, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqadd z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31.d, p0/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x83, 0xd9, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqadd z31.d, p0/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xd9, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqadd z31.d, p7/m, z31.d, z30.d"
diff --git a/tests/MC/AArch64/SVE2/uqrshl.s.yaml b/tests/MC/AArch64/SVE2/uqrshl.s.yaml
new file mode 100644
index 000000000..59a37de4a
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/uqrshl.s.yaml
@@ -0,0 +1,160 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x0b, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqrshl z0.b, p0/m, z0.b, z1.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x4b, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqrshl z0.h, p0/m, z0.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x9f, 0x8b, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqrshl z29.s, p7/m, z29.s, z30.s"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xcb, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqrshl z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31.d, p0/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x83, 0xcb, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqrshl z31.d, p0/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xcb, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqrshl z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x0b, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqrshl z0.b, p0/m, z0.b, z1.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x4b, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqrshl z0.h, p0/m, z0.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x9f, 0x8b, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqrshl z29.s, p7/m, z29.s, z30.s"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xcb, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqrshl z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31.d, p0/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x83, 0xcb, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqrshl z31.d, p0/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xcb, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqrshl z31.d, p7/m, z31.d, z30.d"
diff --git a/tests/MC/AArch64/SVE2/uqrshlr.s.yaml b/tests/MC/AArch64/SVE2/uqrshlr.s.yaml
new file mode 100644
index 000000000..f8bfcd453
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/uqrshlr.s.yaml
@@ -0,0 +1,160 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x0f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqrshlr z0.b, p0/m, z0.b, z1.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x4f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqrshlr z0.h, p0/m, z0.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x9f, 0x8f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqrshlr z29.s, p7/m, z29.s, z30.s"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xcf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqrshlr z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31.d, p0/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x83, 0xcf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqrshlr z31.d, p0/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xcf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqrshlr z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x0f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqrshlr z0.b, p0/m, z0.b, z1.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x4f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqrshlr z0.h, p0/m, z0.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x9f, 0x8f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqrshlr z29.s, p7/m, z29.s, z30.s"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xcf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqrshlr z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31.d, p0/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x83, 0xcf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqrshlr z31.d, p0/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xcf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqrshlr z31.d, p7/m, z31.d, z30.d"
diff --git a/tests/MC/AArch64/SVE2/uqrshrnb.s.yaml b/tests/MC/AArch64/SVE2/uqrshrnb.s.yaml
new file mode 100644
index 000000000..4713ceff6
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/uqrshrnb.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x38, 0x2f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqrshrnb z0.b, z0.h, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3b, 0x28, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqrshrnb z31.b, z31.h, #8"
+
+  -
+    input:
+      bytes: [ 0x00, 0x38, 0x3f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqrshrnb z0.h, z0.s, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3b, 0x30, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqrshrnb z31.h, z31.s, #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0x38, 0x7f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqrshrnb z0.s, z0.d, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3b, 0x60, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqrshrnb z31.s, z31.d, #32"
+
+  -
+    input:
+      bytes: [ 0x00, 0x38, 0x2f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqrshrnb z0.b, z0.h, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3b, 0x28, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqrshrnb z31.b, z31.h, #8"
+
+  -
+    input:
+      bytes: [ 0x00, 0x38, 0x3f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqrshrnb z0.h, z0.s, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3b, 0x30, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqrshrnb z31.h, z31.s, #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0x38, 0x7f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqrshrnb z0.s, z0.d, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3b, 0x60, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqrshrnb z31.s, z31.d, #32"
diff --git a/tests/MC/AArch64/SVE2/uqrshrnt.s.yaml b/tests/MC/AArch64/SVE2/uqrshrnt.s.yaml
new file mode 100644
index 000000000..a853eefad
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/uqrshrnt.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x3c, 0x2f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqrshrnt z0.b, z0.h, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0x28, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqrshrnt z31.b, z31.h, #8"
+
+  -
+    input:
+      bytes: [ 0x00, 0x3c, 0x3f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqrshrnt z0.h, z0.s, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0x30, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqrshrnt z31.h, z31.s, #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0x3c, 0x7f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqrshrnt z0.s, z0.d, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0x60, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqrshrnt z31.s, z31.d, #32"
+
+  -
+    input:
+      bytes: [ 0x00, 0x3c, 0x2f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqrshrnt z0.b, z0.h, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0x28, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqrshrnt z31.b, z31.h, #8"
+
+  -
+    input:
+      bytes: [ 0x00, 0x3c, 0x3f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqrshrnt z0.h, z0.s, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0x30, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqrshrnt z31.h, z31.s, #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0x3c, 0x7f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqrshrnt z0.s, z0.d, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0x60, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqrshrnt z31.s, z31.d, #32"
diff --git a/tests/MC/AArch64/SVE2/uqshl.s.yaml b/tests/MC/AArch64/SVE2/uqshl.s.yaml
new file mode 100644
index 000000000..4c4233428
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/uqshl.s.yaml
@@ -0,0 +1,400 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x09, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqshl z0.b, p0/m, z0.b, z1.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x49, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqshl z0.h, p0/m, z0.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x9f, 0x89, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqshl z29.s, p7/m, z29.s, z30.s"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xc9, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqshl z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x81, 0x07, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqshl z0.b, p0/m, z0.b, #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0x81, 0x07, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqshl z31.b, p0/m, z31.b, #7"
+
+  -
+    input:
+      bytes: [ 0x00, 0x82, 0x07, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqshl z0.h, p0/m, z0.h, #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0x83, 0x07, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqshl z31.h, p0/m, z31.h, #15"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x47, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqshl z0.s, p0/m, z0.s, #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0x83, 0x47, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqshl z31.s, p0/m, z31.s, #31"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x87, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqshl z0.d, p0/m, z0.d, #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0x83, 0xc7, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqshl z31.d, p0/m, z31.d, #63"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31.d, p0/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x83, 0xc9, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqshl z31.d, p0/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xc9, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqshl z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31.d, p0/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0x83, 0xc7, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqshl z31.d, p0/m, z31.d, #63"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xff, 0x83, 0xc7, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqshl z31.d, p0/m, z31.d, #63"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x09, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqshl z0.b, p0/m, z0.b, z1.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x49, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqshl z0.h, p0/m, z0.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x9f, 0x89, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqshl z29.s, p7/m, z29.s, z30.s"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xc9, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqshl z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x81, 0x07, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqshl z0.b, p0/m, z0.b, #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0x81, 0x07, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqshl z31.b, p0/m, z31.b, #7"
+
+  -
+    input:
+      bytes: [ 0x00, 0x82, 0x07, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqshl z0.h, p0/m, z0.h, #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0x83, 0x07, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqshl z31.h, p0/m, z31.h, #15"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x47, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqshl z0.s, p0/m, z0.s, #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0x83, 0x47, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqshl z31.s, p0/m, z31.s, #31"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x87, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqshl z0.d, p0/m, z0.d, #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0x83, 0xc7, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqshl z31.d, p0/m, z31.d, #63"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31.d, p0/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x83, 0xc9, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqshl z31.d, p0/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xc9, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqshl z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31.d, p0/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0x83, 0xc7, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqshl z31.d, p0/m, z31.d, #63"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xff, 0x83, 0xc7, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqshl z31.d, p0/m, z31.d, #63"
diff --git a/tests/MC/AArch64/SVE2/uqshlr.s.yaml b/tests/MC/AArch64/SVE2/uqshlr.s.yaml
new file mode 100644
index 000000000..cf4dbcc1c
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/uqshlr.s.yaml
@@ -0,0 +1,160 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x0d, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqshlr z0.b, p0/m, z0.b, z1.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x4d, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqshlr z0.h, p0/m, z0.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x9f, 0x8d, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqshlr z29.s, p7/m, z29.s, z30.s"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xcd, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqshlr z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31.d, p0/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x83, 0xcd, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqshlr z31.d, p0/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xcd, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqshlr z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x0d, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqshlr z0.b, p0/m, z0.b, z1.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x4d, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqshlr z0.h, p0/m, z0.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x9f, 0x8d, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqshlr z29.s, p7/m, z29.s, z30.s"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xcd, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqshlr z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31.d, p0/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x83, 0xcd, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqshlr z31.d, p0/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xcd, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqshlr z31.d, p7/m, z31.d, z30.d"
diff --git a/tests/MC/AArch64/SVE2/uqshrnb.s.yaml b/tests/MC/AArch64/SVE2/uqshrnb.s.yaml
new file mode 100644
index 000000000..1ab560a0d
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/uqshrnb.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x30, 0x2f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqshrnb z0.b, z0.h, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x33, 0x28, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqshrnb z31.b, z31.h, #8"
+
+  -
+    input:
+      bytes: [ 0x00, 0x30, 0x3f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqshrnb z0.h, z0.s, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x33, 0x30, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqshrnb z31.h, z31.s, #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0x30, 0x7f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqshrnb z0.s, z0.d, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x33, 0x60, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqshrnb z31.s, z31.d, #32"
+
+  -
+    input:
+      bytes: [ 0x00, 0x30, 0x2f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqshrnb z0.b, z0.h, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x33, 0x28, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqshrnb z31.b, z31.h, #8"
+
+  -
+    input:
+      bytes: [ 0x00, 0x30, 0x3f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqshrnb z0.h, z0.s, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x33, 0x30, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqshrnb z31.h, z31.s, #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0x30, 0x7f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqshrnb z0.s, z0.d, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x33, 0x60, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqshrnb z31.s, z31.d, #32"
diff --git a/tests/MC/AArch64/SVE2/uqshrnt.s.yaml b/tests/MC/AArch64/SVE2/uqshrnt.s.yaml
new file mode 100644
index 000000000..99cc10407
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/uqshrnt.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x34, 0x2f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqshrnt z0.b, z0.h, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x37, 0x28, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqshrnt z31.b, z31.h, #8"
+
+  -
+    input:
+      bytes: [ 0x00, 0x34, 0x3f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqshrnt z0.h, z0.s, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x37, 0x30, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqshrnt z31.h, z31.s, #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0x34, 0x7f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqshrnt z0.s, z0.d, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x37, 0x60, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqshrnt z31.s, z31.d, #32"
+
+  -
+    input:
+      bytes: [ 0x00, 0x34, 0x2f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqshrnt z0.b, z0.h, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x37, 0x28, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqshrnt z31.b, z31.h, #8"
+
+  -
+    input:
+      bytes: [ 0x00, 0x34, 0x3f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqshrnt z0.h, z0.s, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x37, 0x30, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqshrnt z31.h, z31.s, #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0x34, 0x7f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqshrnt z0.s, z0.d, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x37, 0x60, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqshrnt z31.s, z31.d, #32"
diff --git a/tests/MC/AArch64/SVE2/uqsub.s.yaml b/tests/MC/AArch64/SVE2/uqsub.s.yaml
new file mode 100644
index 000000000..a67b2a914
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/uqsub.s.yaml
@@ -0,0 +1,160 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x1b, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqsub z0.b, p0/m, z0.b, z1.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x5b, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqsub z0.h, p0/m, z0.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x9f, 0x9b, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqsub z29.s, p7/m, z29.s, z30.s"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xdb, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqsub z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31.d, p0/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x83, 0xdb, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqsub z31.d, p0/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xdb, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqsub z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x1b, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqsub z0.b, p0/m, z0.b, z1.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x5b, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqsub z0.h, p0/m, z0.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x9f, 0x9b, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqsub z29.s, p7/m, z29.s, z30.s"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xdb, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqsub z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31.d, p0/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x83, 0xdb, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqsub z31.d, p0/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xdb, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqsub z31.d, p7/m, z31.d, z30.d"
diff --git a/tests/MC/AArch64/SVE2/uqsubr.s.yaml b/tests/MC/AArch64/SVE2/uqsubr.s.yaml
new file mode 100644
index 000000000..935cfe337
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/uqsubr.s.yaml
@@ -0,0 +1,160 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x1f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqsubr z0.b, p0/m, z0.b, z1.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x5f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqsubr z0.h, p0/m, z0.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x9f, 0x9f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqsubr z29.s, p7/m, z29.s, z30.s"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xdf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqsubr z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31.d, p0/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x83, 0xdf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqsubr z31.d, p0/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xdf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqsubr z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x1f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqsubr z0.b, p0/m, z0.b, z1.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x5f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqsubr z0.h, p0/m, z0.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x9f, 0x9f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqsubr z29.s, p7/m, z29.s, z30.s"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xdf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqsubr z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31.d, p0/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x83, 0xdf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqsubr z31.d, p0/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xdf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqsubr z31.d, p7/m, z31.d, z30.d"
diff --git a/tests/MC/AArch64/SVE2/uqxtnb.s.yaml b/tests/MC/AArch64/SVE2/uqxtnb.s.yaml
new file mode 100644
index 000000000..b61bf05cd
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/uqxtnb.s.yaml
@@ -0,0 +1,60 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xe0, 0x4b, 0x28, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqxtnb z0.b, z31.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x4b, 0x30, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqxtnb z0.h, z31.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x4b, 0x60, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqxtnb z0.s, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x4b, 0x28, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqxtnb z0.b, z31.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x4b, 0x30, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqxtnb z0.h, z31.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x4b, 0x60, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqxtnb z0.s, z31.d"
diff --git a/tests/MC/AArch64/SVE2/uqxtnt.s.yaml b/tests/MC/AArch64/SVE2/uqxtnt.s.yaml
new file mode 100644
index 000000000..ca90f6600
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/uqxtnt.s.yaml
@@ -0,0 +1,60 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xe0, 0x4f, 0x28, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqxtnt z0.b, z31.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x4f, 0x30, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqxtnt z0.h, z31.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x4f, 0x60, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqxtnt z0.s, z31.d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x4f, 0x28, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqxtnt z0.b, z31.h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x4f, 0x30, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqxtnt z0.h, z31.s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x4f, 0x60, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqxtnt z0.s, z31.d"
diff --git a/tests/MC/AArch64/SVE2/urecpe.s.yaml b/tests/MC/AArch64/SVE2/urecpe.s.yaml
new file mode 100644
index 000000000..e56c1a109
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/urecpe.s.yaml
@@ -0,0 +1,100 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x80, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "urecpe z31.s, p7/m, z31.s"
+
+  -
+    input:
+      bytes: [ 0xc4, 0x3c, 0x90, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4.s, p7/z, z6.s"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xbf, 0x80, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "urecpe z4.s, p7/m, z31.s"
+
+  -
+    input:
+      bytes: [ 0xc4, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4, z6"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xbf, 0x80, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "urecpe z4.s, p7/m, z31.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x80, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "urecpe z31.s, p7/m, z31.s"
+
+  -
+    input:
+      bytes: [ 0xc4, 0x3c, 0x90, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4.s, p7/z, z6.s"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xbf, 0x80, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "urecpe z4.s, p7/m, z31.s"
+
+  -
+    input:
+      bytes: [ 0xc4, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4, z6"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xbf, 0x80, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "urecpe z4.s, p7/m, z31.s"
diff --git a/tests/MC/AArch64/SVE2/urhadd.s.yaml b/tests/MC/AArch64/SVE2/urhadd.s.yaml
new file mode 100644
index 000000000..7b5a9a713
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/urhadd.s.yaml
@@ -0,0 +1,160 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x15, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "urhadd z0.b, p0/m, z0.b, z1.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x55, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "urhadd z0.h, p0/m, z0.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x9f, 0x95, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "urhadd z29.s, p7/m, z29.s, z30.s"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xd5, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "urhadd z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31.d, p0/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x83, 0xd5, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "urhadd z31.d, p0/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xd5, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "urhadd z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x15, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "urhadd z0.b, p0/m, z0.b, z1.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x55, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "urhadd z0.h, p0/m, z0.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x9f, 0x95, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "urhadd z29.s, p7/m, z29.s, z30.s"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xd5, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "urhadd z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31.d, p0/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x83, 0xd5, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "urhadd z31.d, p0/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xd5, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "urhadd z31.d, p7/m, z31.d, z30.d"
diff --git a/tests/MC/AArch64/SVE2/urshl.s.yaml b/tests/MC/AArch64/SVE2/urshl.s.yaml
new file mode 100644
index 000000000..7a3b66566
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/urshl.s.yaml
@@ -0,0 +1,160 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x03, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshl z0.b, p0/m, z0.b, z1.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x43, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshl z0.h, p0/m, z0.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x9f, 0x83, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshl z29.s, p7/m, z29.s, z30.s"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xc3, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshl z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31.d, p0/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x83, 0xc3, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshl z31.d, p0/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xc3, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshl z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x03, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshl z0.b, p0/m, z0.b, z1.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x43, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshl z0.h, p0/m, z0.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x9f, 0x83, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshl z29.s, p7/m, z29.s, z30.s"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xc3, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshl z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31.d, p0/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x83, 0xc3, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshl z31.d, p0/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xc3, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshl z31.d, p7/m, z31.d, z30.d"
diff --git a/tests/MC/AArch64/SVE2/urshlr.s.yaml b/tests/MC/AArch64/SVE2/urshlr.s.yaml
new file mode 100644
index 000000000..2c15e4e2f
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/urshlr.s.yaml
@@ -0,0 +1,160 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x07, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshlr z0.b, p0/m, z0.b, z1.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x47, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshlr z0.h, p0/m, z0.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x9f, 0x87, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshlr z29.s, p7/m, z29.s, z30.s"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xc7, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshlr z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31.d, p0/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x83, 0xc7, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshlr z31.d, p0/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xc7, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshlr z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x07, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshlr z0.b, p0/m, z0.b, z1.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x47, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshlr z0.h, p0/m, z0.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x9f, 0x87, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshlr z29.s, p7/m, z29.s, z30.s"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xc7, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshlr z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31.d, p0/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x83, 0xc7, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshlr z31.d, p0/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xc7, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshlr z31.d, p7/m, z31.d, z30.d"
diff --git a/tests/MC/AArch64/SVE2/urshr.s.yaml b/tests/MC/AArch64/SVE2/urshr.s.yaml
new file mode 100644
index 000000000..4a388c635
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/urshr.s.yaml
@@ -0,0 +1,240 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xe0, 0x81, 0x0d, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshr z0.b, p0/m, z0.b, #1"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x81, 0x0d, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshr z31.b, p0/m, z31.b, #8"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x83, 0x0d, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshr z0.h, p0/m, z0.h, #1"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x82, 0x0d, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshr z31.h, p0/m, z31.h, #16"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x83, 0x4d, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshr z0.s, p0/m, z0.s, #1"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x80, 0x4d, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshr z31.s, p0/m, z31.s, #32"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x83, 0xcd, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshr z0.d, p0/m, z0.d, #1"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x80, 0x8d, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshr z31.d, p0/m, z31.d, #64"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31.d, p0/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x80, 0x8d, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshr z31.d, p0/m, z31.d, #64"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x80, 0x8d, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshr z31.d, p0/m, z31.d, #64"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x81, 0x0d, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshr z0.b, p0/m, z0.b, #1"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x81, 0x0d, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshr z31.b, p0/m, z31.b, #8"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x83, 0x0d, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshr z0.h, p0/m, z0.h, #1"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x82, 0x0d, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshr z31.h, p0/m, z31.h, #16"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x83, 0x4d, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshr z0.s, p0/m, z0.s, #1"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x80, 0x4d, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshr z31.s, p0/m, z31.s, #32"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x83, 0xcd, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshr z0.d, p0/m, z0.d, #1"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x80, 0x8d, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshr z31.d, p0/m, z31.d, #64"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31.d, p0/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x80, 0x8d, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshr z31.d, p0/m, z31.d, #64"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x80, 0x8d, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshr z31.d, p0/m, z31.d, #64"
diff --git a/tests/MC/AArch64/SVE2/ursqrte.s.yaml b/tests/MC/AArch64/SVE2/ursqrte.s.yaml
new file mode 100644
index 000000000..b19b4a6ee
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/ursqrte.s.yaml
@@ -0,0 +1,100 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x81, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ursqrte z31.s, p7/m, z31.s"
+
+  -
+    input:
+      bytes: [ 0xc4, 0x3c, 0x90, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4.s, p7/z, z6.s"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xbf, 0x81, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ursqrte z4.s, p7/m, z31.s"
+
+  -
+    input:
+      bytes: [ 0xc4, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4, z6"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xbf, 0x81, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ursqrte z4.s, p7/m, z31.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x81, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ursqrte z31.s, p7/m, z31.s"
+
+  -
+    input:
+      bytes: [ 0xc4, 0x3c, 0x90, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4.s, p7/z, z6.s"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xbf, 0x81, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ursqrte z4.s, p7/m, z31.s"
+
+  -
+    input:
+      bytes: [ 0xc4, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z4, z6"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xbf, 0x81, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ursqrte z4.s, p7/m, z31.s"
diff --git a/tests/MC/AArch64/SVE2/ursra.s.yaml b/tests/MC/AArch64/SVE2/ursra.s.yaml
new file mode 100644
index 000000000..7d87597b5
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/ursra.s.yaml
@@ -0,0 +1,200 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xec, 0x0f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ursra z0.b, z0.b, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0xef, 0x08, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ursra z31.b, z31.b, #8"
+
+  -
+    input:
+      bytes: [ 0x00, 0xec, 0x1f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ursra z0.h, z0.h, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0xef, 0x10, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ursra z31.h, z31.h, #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xec, 0x5f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ursra z0.s, z0.s, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0xef, 0x40, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ursra z31.s, z31.s, #32"
+
+  -
+    input:
+      bytes: [ 0x00, 0xec, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ursra z0.d, z0.d, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0xef, 0x80, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ursra z31.d, z31.d, #64"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x20, 0xec, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ursra z0.d, z1.d, #1"
+
+  -
+    input:
+      bytes: [ 0x00, 0xec, 0x0f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ursra z0.b, z0.b, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0xef, 0x08, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ursra z31.b, z31.b, #8"
+
+  -
+    input:
+      bytes: [ 0x00, 0xec, 0x1f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ursra z0.h, z0.h, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0xef, 0x10, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ursra z31.h, z31.h, #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xec, 0x5f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ursra z0.s, z0.s, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0xef, 0x40, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ursra z31.s, z31.s, #32"
+
+  -
+    input:
+      bytes: [ 0x00, 0xec, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ursra z0.d, z0.d, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0xef, 0x80, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ursra z31.d, z31.d, #64"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x20, 0xec, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ursra z0.d, z1.d, #1"
diff --git a/tests/MC/AArch64/SVE2/ushllb.s.yaml b/tests/MC/AArch64/SVE2/ushllb.s.yaml
new file mode 100644
index 000000000..b9f0a45fe
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/ushllb.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xa8, 0x08, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ushllb z0.h, z0.b, #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0xab, 0x0f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ushllb z31.h, z31.b, #7"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa8, 0x10, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ushllb z0.s, z0.h, #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0xab, 0x1f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ushllb z31.s, z31.h, #15"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa8, 0x40, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ushllb z0.d, z0.s, #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0xab, 0x5f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ushllb z31.d, z31.s, #31"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa8, 0x08, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ushllb z0.h, z0.b, #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0xab, 0x0f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ushllb z31.h, z31.b, #7"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa8, 0x10, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ushllb z0.s, z0.h, #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0xab, 0x1f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ushllb z31.s, z31.h, #15"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa8, 0x40, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ushllb z0.d, z0.s, #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0xab, 0x5f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ushllb z31.d, z31.s, #31"
diff --git a/tests/MC/AArch64/SVE2/ushllt.s.yaml b/tests/MC/AArch64/SVE2/ushllt.s.yaml
new file mode 100644
index 000000000..f65e6891d
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/ushllt.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xac, 0x08, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ushllt z0.h, z0.b, #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0xaf, 0x0f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ushllt z31.h, z31.b, #7"
+
+  -
+    input:
+      bytes: [ 0x00, 0xac, 0x10, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ushllt z0.s, z0.h, #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0xaf, 0x1f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ushllt z31.s, z31.h, #15"
+
+  -
+    input:
+      bytes: [ 0x00, 0xac, 0x40, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ushllt z0.d, z0.s, #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0xaf, 0x5f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ushllt z31.d, z31.s, #31"
+
+  -
+    input:
+      bytes: [ 0x00, 0xac, 0x08, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ushllt z0.h, z0.b, #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0xaf, 0x0f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ushllt z31.h, z31.b, #7"
+
+  -
+    input:
+      bytes: [ 0x00, 0xac, 0x10, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ushllt z0.s, z0.h, #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0xaf, 0x1f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ushllt z31.s, z31.h, #15"
+
+  -
+    input:
+      bytes: [ 0x00, 0xac, 0x40, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ushllt z0.d, z0.s, #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0xaf, 0x5f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ushllt z31.d, z31.s, #31"
diff --git a/tests/MC/AArch64/SVE2/usqadd.s.yaml b/tests/MC/AArch64/SVE2/usqadd.s.yaml
new file mode 100644
index 000000000..8802d241b
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/usqadd.s.yaml
@@ -0,0 +1,160 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x1d, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usqadd z0.b, p0/m, z0.b, z1.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x5d, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usqadd z0.h, p0/m, z0.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x9f, 0x9d, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usqadd z29.s, p7/m, z29.s, z30.s"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xdd, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usqadd z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31.d, p0/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x83, 0xdd, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usqadd z31.d, p0/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xdd, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usqadd z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x1d, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "usqadd z0.b, p0/m, z0.b, z1.b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x5d, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "usqadd z0.h, p0/m, z0.h, z1.h"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x9f, 0x9d, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "usqadd z29.s, p7/m, z29.s, z30.s"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xdd, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "usqadd z31.d, p7/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x20, 0xd0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31.d, p0/z, z6.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x83, 0xdd, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "usqadd z31.d, p0/m, z31.d, z30.d"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z6"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x9f, 0xdd, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "usqadd z31.d, p7/m, z31.d, z30.d"
diff --git a/tests/MC/AArch64/SVE2/usra.s.yaml b/tests/MC/AArch64/SVE2/usra.s.yaml
new file mode 100644
index 000000000..8eb1a28a2
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/usra.s.yaml
@@ -0,0 +1,200 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xe4, 0x0f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usra z0.b, z0.b, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0xe7, 0x08, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usra z31.b, z31.b, #8"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe4, 0x1f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usra z0.h, z0.h, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0xe7, 0x10, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usra z31.h, z31.h, #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe4, 0x5f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usra z0.s, z0.s, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0xe7, 0x40, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usra z31.s, z31.s, #32"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe4, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usra z0.d, z0.d, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0xe7, 0x80, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usra z31.d, z31.d, #64"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe4, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usra z0.d, z1.d, #1"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe4, 0x0f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "usra z0.b, z0.b, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0xe7, 0x08, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "usra z31.b, z31.b, #8"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe4, 0x1f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "usra z0.h, z0.h, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0xe7, 0x10, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "usra z31.h, z31.h, #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe4, 0x5f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "usra z0.s, z0.s, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0xe7, 0x40, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "usra z31.s, z31.s, #32"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe4, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "usra z0.d, z0.d, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0xe7, 0x80, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "usra z31.d, z31.d, #64"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z0, z7"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe4, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "usra z0.d, z1.d, #1"
diff --git a/tests/MC/AArch64/SVE2/usublb.s.yaml b/tests/MC/AArch64/SVE2/usublb.s.yaml
new file mode 100644
index 000000000..5aea13583
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/usublb.s.yaml
@@ -0,0 +1,60 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x18, 0x42, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usublb z0.h, z1.b, z2.b"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x1b, 0x9f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usublb z29.s, z30.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1b, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usublb z31.d, z31.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x18, 0x42, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "usublb z0.h, z1.b, z2.b"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x1b, 0x9f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "usublb z29.s, z30.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1b, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "usublb z31.d, z31.s, z31.s"
diff --git a/tests/MC/AArch64/SVE2/usublt.s.yaml b/tests/MC/AArch64/SVE2/usublt.s.yaml
new file mode 100644
index 000000000..258a2e52f
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/usublt.s.yaml
@@ -0,0 +1,60 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x1c, 0x42, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usublt z0.h, z1.b, z2.b"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x1f, 0x9f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usublt z29.s, z30.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usublt z31.d, z31.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x1c, 0x42, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "usublt z0.h, z1.b, z2.b"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x1f, 0x9f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "usublt z29.s, z30.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "usublt z31.d, z31.s, z31.s"
diff --git a/tests/MC/AArch64/SVE2/usubwb.s.yaml b/tests/MC/AArch64/SVE2/usubwb.s.yaml
new file mode 100644
index 000000000..6011daa98
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/usubwb.s.yaml
@@ -0,0 +1,60 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x58, 0x42, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usubwb z0.h, z1.h, z2.b"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x5b, 0x9f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usubwb z29.s, z30.s, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x5b, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usubwb z31.d, z31.d, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x58, 0x42, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "usubwb z0.h, z1.h, z2.b"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x5b, 0x9f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "usubwb z29.s, z30.s, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x5b, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "usubwb z31.d, z31.d, z31.s"
diff --git a/tests/MC/AArch64/SVE2/usubwt.s.yaml b/tests/MC/AArch64/SVE2/usubwt.s.yaml
new file mode 100644
index 000000000..02acb83a4
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/usubwt.s.yaml
@@ -0,0 +1,60 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x5c, 0x42, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usubwt z0.h, z1.h, z2.b"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x5f, 0x9f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usubwt z29.s, z30.s, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x5f, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "usubwt z31.d, z31.d, z31.s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x5c, 0x42, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "usubwt z0.h, z1.h, z2.b"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x5f, 0x9f, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "usubwt z29.s, z30.s, z31.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x5f, 0xdf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "usubwt z31.d, z31.d, z31.s"
diff --git a/tests/MC/AArch64/SVE2/whilege.s.yaml b/tests/MC/AArch64/SVE2/whilege.s.yaml
new file mode 100644
index 000000000..6383a5eae
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/whilege.s.yaml
@@ -0,0 +1,200 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xef, 0x13, 0x20, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilege p15.b, xzr, x0"
+
+  -
+    input:
+      bytes: [ 0x0f, 0x10, 0x3f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilege p15.b, x0, xzr"
+
+  -
+    input:
+      bytes: [ 0xef, 0x03, 0x20, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilege p15.b, wzr, w0"
+
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0x3f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilege p15.b, w0, wzr"
+
+  -
+    input:
+      bytes: [ 0x0f, 0x10, 0x7f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilege p15.h, x0, xzr"
+
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0x7f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilege p15.h, w0, wzr"
+
+  -
+    input:
+      bytes: [ 0x0f, 0x10, 0xbf, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilege p15.s, x0, xzr"
+
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0xbf, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilege p15.s, w0, wzr"
+
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0xff, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilege p15.d, w0, wzr"
+
+  -
+    input:
+      bytes: [ 0x0f, 0x10, 0xff, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilege p15.d, x0, xzr"
+
+  -
+    input:
+      bytes: [ 0xef, 0x13, 0x20, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilege p15.b, xzr, x0"
+
+  -
+    input:
+      bytes: [ 0x0f, 0x10, 0x3f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilege p15.b, x0, xzr"
+
+  -
+    input:
+      bytes: [ 0xef, 0x03, 0x20, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilege p15.b, wzr, w0"
+
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0x3f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilege p15.b, w0, wzr"
+
+  -
+    input:
+      bytes: [ 0x0f, 0x10, 0x7f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilege p15.h, x0, xzr"
+
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0x7f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilege p15.h, w0, wzr"
+
+  -
+    input:
+      bytes: [ 0x0f, 0x10, 0xbf, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilege p15.s, x0, xzr"
+
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0xbf, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilege p15.s, w0, wzr"
+
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0xff, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilege p15.d, w0, wzr"
+
+  -
+    input:
+      bytes: [ 0x0f, 0x10, 0xff, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilege p15.d, x0, xzr"
diff --git a/tests/MC/AArch64/SVE2/whilegt.s.yaml b/tests/MC/AArch64/SVE2/whilegt.s.yaml
new file mode 100644
index 000000000..109691a1d
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/whilegt.s.yaml
@@ -0,0 +1,200 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xff, 0x13, 0x20, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilegt p15.b, xzr, x0"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x10, 0x3f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilegt p15.b, x0, xzr"
+
+  -
+    input:
+      bytes: [ 0xff, 0x03, 0x20, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilegt p15.b, wzr, w0"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x00, 0x3f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilegt p15.b, w0, wzr"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x10, 0x7f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilegt p15.h, x0, xzr"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x00, 0x7f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilegt p15.h, w0, wzr"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x10, 0xbf, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilegt p15.s, x0, xzr"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x00, 0xbf, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilegt p15.s, w0, wzr"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x00, 0xff, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilegt p15.d, w0, wzr"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x10, 0xff, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilegt p15.d, x0, xzr"
+
+  -
+    input:
+      bytes: [ 0xff, 0x13, 0x20, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilegt p15.b, xzr, x0"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x10, 0x3f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilegt p15.b, x0, xzr"
+
+  -
+    input:
+      bytes: [ 0xff, 0x03, 0x20, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilegt p15.b, wzr, w0"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x00, 0x3f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilegt p15.b, w0, wzr"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x10, 0x7f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilegt p15.h, x0, xzr"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x00, 0x7f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilegt p15.h, w0, wzr"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x10, 0xbf, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilegt p15.s, x0, xzr"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x00, 0xbf, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilegt p15.s, w0, wzr"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x00, 0xff, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilegt p15.d, w0, wzr"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x10, 0xff, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilegt p15.d, x0, xzr"
diff --git a/tests/MC/AArch64/SVE2/whilehi.s.yaml b/tests/MC/AArch64/SVE2/whilehi.s.yaml
new file mode 100644
index 000000000..ede403181
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/whilehi.s.yaml
@@ -0,0 +1,200 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xff, 0x1b, 0x20, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehi p15.b, xzr, x0"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x18, 0x3f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehi p15.b, x0, xzr"
+
+  -
+    input:
+      bytes: [ 0xff, 0x0b, 0x20, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehi p15.b, wzr, w0"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x08, 0x3f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehi p15.b, w0, wzr"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x18, 0x7f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehi p15.h, x0, xzr"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x08, 0x7f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehi p15.h, w0, wzr"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x18, 0xbf, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehi p15.s, x0, xzr"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x08, 0xbf, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehi p15.s, w0, wzr"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x08, 0xff, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehi p15.d, w0, wzr"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x18, 0xff, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehi p15.d, x0, xzr"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1b, 0x20, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehi p15.b, xzr, x0"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x18, 0x3f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehi p15.b, x0, xzr"
+
+  -
+    input:
+      bytes: [ 0xff, 0x0b, 0x20, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehi p15.b, wzr, w0"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x08, 0x3f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehi p15.b, w0, wzr"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x18, 0x7f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehi p15.h, x0, xzr"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x08, 0x7f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehi p15.h, w0, wzr"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x18, 0xbf, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehi p15.s, x0, xzr"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x08, 0xbf, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehi p15.s, w0, wzr"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x08, 0xff, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehi p15.d, w0, wzr"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x18, 0xff, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehi p15.d, x0, xzr"
diff --git a/tests/MC/AArch64/SVE2/whilehs.s.yaml b/tests/MC/AArch64/SVE2/whilehs.s.yaml
new file mode 100644
index 000000000..f7761a1ad
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/whilehs.s.yaml
@@ -0,0 +1,200 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xef, 0x1b, 0x20, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehs p15.b, xzr, x0"
+
+  -
+    input:
+      bytes: [ 0x0f, 0x18, 0x3f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehs p15.b, x0, xzr"
+
+  -
+    input:
+      bytes: [ 0xef, 0x0b, 0x20, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehs p15.b, wzr, w0"
+
+  -
+    input:
+      bytes: [ 0x0f, 0x08, 0x3f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehs p15.b, w0, wzr"
+
+  -
+    input:
+      bytes: [ 0x0f, 0x18, 0x7f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehs p15.h, x0, xzr"
+
+  -
+    input:
+      bytes: [ 0x0f, 0x08, 0x7f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehs p15.h, w0, wzr"
+
+  -
+    input:
+      bytes: [ 0x0f, 0x18, 0xbf, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehs p15.s, x0, xzr"
+
+  -
+    input:
+      bytes: [ 0x0f, 0x08, 0xbf, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehs p15.s, w0, wzr"
+
+  -
+    input:
+      bytes: [ 0x0f, 0x08, 0xff, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehs p15.d, w0, wzr"
+
+  -
+    input:
+      bytes: [ 0x0f, 0x18, 0xff, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehs p15.d, x0, xzr"
+
+  -
+    input:
+      bytes: [ 0xef, 0x1b, 0x20, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehs p15.b, xzr, x0"
+
+  -
+    input:
+      bytes: [ 0x0f, 0x18, 0x3f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehs p15.b, x0, xzr"
+
+  -
+    input:
+      bytes: [ 0xef, 0x0b, 0x20, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehs p15.b, wzr, w0"
+
+  -
+    input:
+      bytes: [ 0x0f, 0x08, 0x3f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehs p15.b, w0, wzr"
+
+  -
+    input:
+      bytes: [ 0x0f, 0x18, 0x7f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehs p15.h, x0, xzr"
+
+  -
+    input:
+      bytes: [ 0x0f, 0x08, 0x7f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehs p15.h, w0, wzr"
+
+  -
+    input:
+      bytes: [ 0x0f, 0x18, 0xbf, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehs p15.s, x0, xzr"
+
+  -
+    input:
+      bytes: [ 0x0f, 0x08, 0xbf, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehs p15.s, w0, wzr"
+
+  -
+    input:
+      bytes: [ 0x0f, 0x08, 0xff, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehs p15.d, w0, wzr"
+
+  -
+    input:
+      bytes: [ 0x0f, 0x18, 0xff, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehs p15.d, x0, xzr"
diff --git a/tests/MC/AArch64/SVE2/whilerw.s.yaml b/tests/MC/AArch64/SVE2/whilerw.s.yaml
new file mode 100644
index 000000000..cbd90e31d
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/whilerw.s.yaml
@@ -0,0 +1,80 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xdf, 0x33, 0x3e, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilerw p15.b, x30, x30"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x33, 0x7e, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilerw p15.h, x30, x30"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x33, 0xbe, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilerw p15.s, x30, x30"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x33, 0xfe, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilerw p15.d, x30, x30"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x33, 0x3e, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilerw p15.b, x30, x30"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x33, 0x7e, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilerw p15.h, x30, x30"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x33, 0xbe, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilerw p15.s, x30, x30"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x33, 0xfe, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilerw p15.d, x30, x30"
diff --git a/tests/MC/AArch64/SVE2/whilewr.s.yaml b/tests/MC/AArch64/SVE2/whilewr.s.yaml
new file mode 100644
index 000000000..79d6809ba
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/whilewr.s.yaml
@@ -0,0 +1,80 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xcf, 0x33, 0x3e, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilewr p15.b, x30, x30"
+
+  -
+    input:
+      bytes: [ 0xcf, 0x33, 0x7e, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilewr p15.h, x30, x30"
+
+  -
+    input:
+      bytes: [ 0xcf, 0x33, 0xbe, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilewr p15.s, x30, x30"
+
+  -
+    input:
+      bytes: [ 0xcf, 0x33, 0xfe, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilewr p15.d, x30, x30"
+
+  -
+    input:
+      bytes: [ 0xcf, 0x33, 0x3e, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilewr p15.b, x30, x30"
+
+  -
+    input:
+      bytes: [ 0xcf, 0x33, 0x7e, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilewr p15.h, x30, x30"
+
+  -
+    input:
+      bytes: [ 0xcf, 0x33, 0xbe, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilewr p15.s, x30, x30"
+
+  -
+    input:
+      bytes: [ 0xcf, 0x33, 0xfe, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilewr p15.d, x30, x30"
diff --git a/tests/MC/AArch64/SVE2/xar.s.yaml b/tests/MC/AArch64/SVE2/xar.s.yaml
new file mode 100644
index 000000000..d47563eb1
--- /dev/null
+++ b/tests/MC/AArch64/SVE2/xar.s.yaml
@@ -0,0 +1,200 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x34, 0x2f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "xar z0.b, z0.b, z1.b, #1"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x37, 0x28, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "xar z31.b, z31.b, z30.b, #8"
+
+  -
+    input:
+      bytes: [ 0x20, 0x34, 0x3f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "xar z0.h, z0.h, z1.h, #1"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x37, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "xar z31.h, z31.h, z30.h, #16"
+
+  -
+    input:
+      bytes: [ 0x20, 0x34, 0x7f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "xar z0.s, z0.s, z1.s, #1"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x37, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "xar z31.s, z31.s, z30.s, #32"
+
+  -
+    input:
+      bytes: [ 0x20, 0x34, 0xff, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "xar z0.d, z0.d, z1.d, #1"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x37, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "xar z31.d, z31.d, z30.d, #64"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z7"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x37, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2" ]
+    expected:
+      insns:
+        -
+          asm_text: "xar z31.d, z31.d, z30.d, #64"
+
+  -
+    input:
+      bytes: [ 0x20, 0x34, 0x2f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "xar z0.b, z0.b, z1.b, #1"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x37, 0x28, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "xar z31.b, z31.b, z30.b, #8"
+
+  -
+    input:
+      bytes: [ 0x20, 0x34, 0x3f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "xar z0.h, z0.h, z1.h, #1"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x37, 0x30, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "xar z31.h, z31.h, z30.h, #16"
+
+  -
+    input:
+      bytes: [ 0x20, 0x34, 0x7f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "xar z0.s, z0.s, z1.s, #1"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x37, 0x60, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "xar z31.s, z31.s, z30.s, #32"
+
+  -
+    input:
+      bytes: [ 0x20, 0x34, 0xff, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "xar z0.d, z0.d, z1.d, #1"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x37, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "xar z31.d, z31.d, z30.d, #64"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbc, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z31, z7"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x37, 0xa0, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme" ]
+    expected:
+      insns:
+        -
+          asm_text: "xar z31.d, z31.d, z30.d, #64"
diff --git a/tests/MC/AArch64/SVE2p1/addqv.s.yaml b/tests/MC/AArch64/SVE2p1/addqv.s.yaml
new file mode 100644
index 000000000..a9b6a6940
--- /dev/null
+++ b/tests/MC/AArch64/SVE2p1/addqv.s.yaml
@@ -0,0 +1,320 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x45, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "addqv v0.8h, p0, z0.h"
+
+  -
+    input:
+      bytes: [ 0x55, 0x35, 0x45, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "addqv v21.8h, p5, z10.h"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x2d, 0x45, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "addqv v23.8h, p3, z13.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0x45, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "addqv v31.8h, p7, z31.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x85, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "addqv v0.4s, p0, z0.s"
+
+  -
+    input:
+      bytes: [ 0x55, 0x35, 0x85, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "addqv v21.4s, p5, z10.s"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x2d, 0x85, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "addqv v23.4s, p3, z13.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0x85, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "addqv v31.4s, p7, z31.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0xc5, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "addqv v0.2d, p0, z0.d"
+
+  -
+    input:
+      bytes: [ 0x55, 0x35, 0xc5, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "addqv v21.2d, p5, z10.d"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x2d, 0xc5, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "addqv v23.2d, p3, z13.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0xc5, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "addqv v31.2d, p7, z31.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x05, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "addqv v0.16b, p0, z0.b"
+
+  -
+    input:
+      bytes: [ 0x55, 0x35, 0x05, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "addqv v21.16b, p5, z10.b"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x2d, 0x05, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "addqv v23.16b, p3, z13.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0x05, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "addqv v31.16b, p7, z31.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x45, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "addqv v0.8h, p0, z0.h"
+
+  -
+    input:
+      bytes: [ 0x55, 0x35, 0x45, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "addqv v21.8h, p5, z10.h"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x2d, 0x45, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "addqv v23.8h, p3, z13.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0x45, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "addqv v31.8h, p7, z31.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x85, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "addqv v0.4s, p0, z0.s"
+
+  -
+    input:
+      bytes: [ 0x55, 0x35, 0x85, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "addqv v21.4s, p5, z10.s"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x2d, 0x85, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "addqv v23.4s, p3, z13.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0x85, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "addqv v31.4s, p7, z31.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0xc5, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "addqv v0.2d, p0, z0.d"
+
+  -
+    input:
+      bytes: [ 0x55, 0x35, 0xc5, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "addqv v21.2d, p5, z10.d"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x2d, 0xc5, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "addqv v23.2d, p3, z13.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0xc5, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "addqv v31.2d, p7, z31.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x05, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "addqv v0.16b, p0, z0.b"
+
+  -
+    input:
+      bytes: [ 0x55, 0x35, 0x05, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "addqv v21.16b, p5, z10.b"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x2d, 0x05, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "addqv v23.16b, p3, z13.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0x05, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "addqv v31.16b, p7, z31.b"
diff --git a/tests/MC/AArch64/SVE2p1/andqv.s.yaml b/tests/MC/AArch64/SVE2p1/andqv.s.yaml
new file mode 100644
index 000000000..c8f623741
--- /dev/null
+++ b/tests/MC/AArch64/SVE2p1/andqv.s.yaml
@@ -0,0 +1,320 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x5e, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "andqv v0.8h, p0, z0.h"
+
+  -
+    input:
+      bytes: [ 0x55, 0x35, 0x5e, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "andqv v21.8h, p5, z10.h"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x2d, 0x5e, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "andqv v23.8h, p3, z13.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0x5e, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "andqv v31.8h, p7, z31.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x9e, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "andqv v0.4s, p0, z0.s"
+
+  -
+    input:
+      bytes: [ 0x55, 0x35, 0x9e, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "andqv v21.4s, p5, z10.s"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x2d, 0x9e, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "andqv v23.4s, p3, z13.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0x9e, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "andqv v31.4s, p7, z31.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0xde, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "andqv v0.2d, p0, z0.d"
+
+  -
+    input:
+      bytes: [ 0x55, 0x35, 0xde, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "andqv v21.2d, p5, z10.d"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x2d, 0xde, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "andqv v23.2d, p3, z13.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0xde, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "andqv v31.2d, p7, z31.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x1e, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "andqv v0.16b, p0, z0.b"
+
+  -
+    input:
+      bytes: [ 0x55, 0x35, 0x1e, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "andqv v21.16b, p5, z10.b"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x2d, 0x1e, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "andqv v23.16b, p3, z13.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0x1e, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "andqv v31.16b, p7, z31.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x5e, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "andqv v0.8h, p0, z0.h"
+
+  -
+    input:
+      bytes: [ 0x55, 0x35, 0x5e, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "andqv v21.8h, p5, z10.h"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x2d, 0x5e, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "andqv v23.8h, p3, z13.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0x5e, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "andqv v31.8h, p7, z31.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x9e, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "andqv v0.4s, p0, z0.s"
+
+  -
+    input:
+      bytes: [ 0x55, 0x35, 0x9e, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "andqv v21.4s, p5, z10.s"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x2d, 0x9e, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "andqv v23.4s, p3, z13.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0x9e, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "andqv v31.4s, p7, z31.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0xde, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "andqv v0.2d, p0, z0.d"
+
+  -
+    input:
+      bytes: [ 0x55, 0x35, 0xde, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "andqv v21.2d, p5, z10.d"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x2d, 0xde, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "andqv v23.2d, p3, z13.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0xde, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "andqv v31.2d, p7, z31.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x1e, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "andqv v0.16b, p0, z0.b"
+
+  -
+    input:
+      bytes: [ 0x55, 0x35, 0x1e, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "andqv v21.16b, p5, z10.b"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x2d, 0x1e, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "andqv v23.16b, p3, z13.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0x1e, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "andqv v31.16b, p7, z31.b"
diff --git a/tests/MC/AArch64/SVE2p1/bfadd.s.yaml b/tests/MC/AArch64/SVE2p1/bfadd.s.yaml
new file mode 100644
index 000000000..3c5875274
--- /dev/null
+++ b/tests/MC/AArch64/SVE2p1/bfadd.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xf7, 0x2f, 0x51, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z23.h, p3/m, z31.h"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x8d, 0x00, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfadd z23.h, p3/m, z23.h, z13.h"
+
+  -
+    input:
+      bytes: [ 0xf7, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z23, z31"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x8d, 0x00, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfadd z23.h, p3/m, z23.h, z13.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x00, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfadd z0.h, p0/m, z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x55, 0x95, 0x00, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfadd z21.h, p5/m, z21.h, z10.h"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x8d, 0x00, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfadd z23.h, p3/m, z23.h, z13.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x9f, 0x00, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfadd z31.h, p7/m, z31.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x00, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfadd z0.h, z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x55, 0x01, 0x15, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfadd z21.h, z10.h, z21.h"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x01, 0x08, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfadd z23.h, z13.h, z8.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x03, 0x1f, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfadd z31.h, z31.h, z31.h"
diff --git a/tests/MC/AArch64/SVE2p1/bfclamp.s.yaml b/tests/MC/AArch64/SVE2p1/bfclamp.s.yaml
new file mode 100644
index 000000000..8497365cd
--- /dev/null
+++ b/tests/MC/AArch64/SVE2p1/bfclamp.s.yaml
@@ -0,0 +1,60 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xf7, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z23, z31"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x25, 0x28, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfclamp z23.h, z13.h, z8.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x24, 0x20, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfclamp z0.h, z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x55, 0x25, 0x35, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfclamp z21.h, z10.h, z21.h"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x25, 0x28, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfclamp z23.h, z13.h, z8.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x27, 0x3f, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfclamp z31.h, z31.h, z31.h"
diff --git a/tests/MC/AArch64/SVE2p1/bfmax.s.yaml b/tests/MC/AArch64/SVE2p1/bfmax.s.yaml
new file mode 100644
index 000000000..5f82cbae1
--- /dev/null
+++ b/tests/MC/AArch64/SVE2p1/bfmax.s.yaml
@@ -0,0 +1,80 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xf7, 0x2f, 0x51, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z23.h, p3/m, z31.h"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x8d, 0x06, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmax z23.h, p3/m, z23.h, z13.h"
+
+  -
+    input:
+      bytes: [ 0xf7, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z23, z31"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x8d, 0x06, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmax z23.h, p3/m, z23.h, z13.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x06, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmax z0.h, p0/m, z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x55, 0x95, 0x06, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmax z21.h, p5/m, z21.h, z10.h"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x8d, 0x06, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmax z23.h, p3/m, z23.h, z13.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x9f, 0x06, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmax z31.h, p7/m, z31.h, z31.h"
diff --git a/tests/MC/AArch64/SVE2p1/bfmaxnm.s.yaml b/tests/MC/AArch64/SVE2p1/bfmaxnm.s.yaml
new file mode 100644
index 000000000..45aac3fce
--- /dev/null
+++ b/tests/MC/AArch64/SVE2p1/bfmaxnm.s.yaml
@@ -0,0 +1,80 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xf7, 0x2f, 0x51, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z23.h, p3/m, z31.h"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x8d, 0x04, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmaxnm z23.h, p3/m, z23.h, z13.h"
+
+  -
+    input:
+      bytes: [ 0xf7, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z23, z31"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x8d, 0x04, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmaxnm z23.h, p3/m, z23.h, z13.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x04, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmaxnm z0.h, p0/m, z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x55, 0x95, 0x04, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmaxnm z21.h, p5/m, z21.h, z10.h"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x8d, 0x04, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmaxnm z23.h, p3/m, z23.h, z13.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x9f, 0x04, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmaxnm z31.h, p7/m, z31.h, z31.h"
diff --git a/tests/MC/AArch64/SVE2p1/bfmin.s.yaml b/tests/MC/AArch64/SVE2p1/bfmin.s.yaml
new file mode 100644
index 000000000..86b6b7b88
--- /dev/null
+++ b/tests/MC/AArch64/SVE2p1/bfmin.s.yaml
@@ -0,0 +1,80 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xf7, 0x2f, 0x51, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z23.h, p3/m, z31.h"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x8d, 0x07, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmin z23.h, p3/m, z23.h, z13.h"
+
+  -
+    input:
+      bytes: [ 0xf7, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z23, z31"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x8d, 0x07, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmin z23.h, p3/m, z23.h, z13.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x07, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmin z0.h, p0/m, z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x55, 0x95, 0x07, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmin z21.h, p5/m, z21.h, z10.h"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x8d, 0x07, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmin z23.h, p3/m, z23.h, z13.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x9f, 0x07, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmin z31.h, p7/m, z31.h, z31.h"
diff --git a/tests/MC/AArch64/SVE2p1/bfminnm.s.yaml b/tests/MC/AArch64/SVE2p1/bfminnm.s.yaml
new file mode 100644
index 000000000..c4017d0b3
--- /dev/null
+++ b/tests/MC/AArch64/SVE2p1/bfminnm.s.yaml
@@ -0,0 +1,80 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xf7, 0x2f, 0x51, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z23.h, p3/m, z31.h"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x8d, 0x05, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfminnm z23.h, p3/m, z23.h, z13.h"
+
+  -
+    input:
+      bytes: [ 0xf7, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z23, z31"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x8d, 0x05, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfminnm z23.h, p3/m, z23.h, z13.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x05, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfminnm z0.h, p0/m, z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x55, 0x95, 0x05, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfminnm z21.h, p5/m, z21.h, z10.h"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x8d, 0x05, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfminnm z23.h, p3/m, z23.h, z13.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x9f, 0x05, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfminnm z31.h, p7/m, z31.h, z31.h"
diff --git a/tests/MC/AArch64/SVE2p1/bfmla.s.yaml b/tests/MC/AArch64/SVE2p1/bfmla.s.yaml
new file mode 100644
index 000000000..10847c77a
--- /dev/null
+++ b/tests/MC/AArch64/SVE2p1/bfmla.s.yaml
@@ -0,0 +1,140 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xf7, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z23, z31"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x09, 0x68, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla z23.h, z13.h, z0.h[5]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x08, 0x20, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla z0.h, z0.h, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x09, 0x75, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla z21.h, z10.h, z5.h[6]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x09, 0x68, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla z23.h, z13.h, z0.h[5]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x0b, 0x7f, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla z31.h, z31.h, z7.h[7]"
+
+  -
+    input:
+      bytes: [ 0xf7, 0x2f, 0x51, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z23.h, p3/m, z31.h"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x0d, 0x28, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla z23.h, p3/m, z13.h, z8.h"
+
+  -
+    input:
+      bytes: [ 0xf7, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z23, z31"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x0d, 0x28, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla z23.h, p3/m, z13.h, z8.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x20, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla z0.h, p0/m, z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x55, 0x15, 0x35, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla z21.h, p5/m, z10.h, z21.h"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x0d, 0x28, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla z23.h, p3/m, z13.h, z8.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0x3f, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmla z31.h, p7/m, z31.h, z31.h"
diff --git a/tests/MC/AArch64/SVE2p1/bfmls.s.yaml b/tests/MC/AArch64/SVE2p1/bfmls.s.yaml
new file mode 100644
index 000000000..0cef7f6eb
--- /dev/null
+++ b/tests/MC/AArch64/SVE2p1/bfmls.s.yaml
@@ -0,0 +1,140 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xf7, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z23, z31"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x0d, 0x68, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls z23.h, z13.h, z0.h[5]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x0c, 0x20, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls z0.h, z0.h, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x0d, 0x75, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls z21.h, z10.h, z5.h[6]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x0d, 0x68, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls z23.h, z13.h, z0.h[5]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x0f, 0x7f, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls z31.h, z31.h, z7.h[7]"
+
+  -
+    input:
+      bytes: [ 0xf7, 0x2f, 0x51, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z23.h, p3/m, z31.h"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x2d, 0x28, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls z23.h, p3/m, z13.h, z8.h"
+
+  -
+    input:
+      bytes: [ 0xf7, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z23, z31"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x2d, 0x28, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls z23.h, p3/m, z13.h, z8.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x20, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls z0.h, p0/m, z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x55, 0x35, 0x35, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls z21.h, p5/m, z10.h, z21.h"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x2d, 0x28, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls z23.h, p3/m, z13.h, z8.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0x3f, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmls z31.h, p7/m, z31.h, z31.h"
diff --git a/tests/MC/AArch64/SVE2p1/bfmlslb.s.yaml b/tests/MC/AArch64/SVE2p1/bfmlslb.s.yaml
new file mode 100644
index 000000000..0f94df496
--- /dev/null
+++ b/tests/MC/AArch64/SVE2p1/bfmlslb.s.yaml
@@ -0,0 +1,240 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xf7, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z23, z31"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xa1, 0xe8, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlslb z23.s, z13.h, z8.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xe0, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlslb z0.s, z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x55, 0xa1, 0xf5, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlslb z21.s, z10.h, z21.h"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xa1, 0xe8, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlslb z23.s, z13.h, z8.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0xa3, 0xff, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlslb z31.s, z31.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xf7, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z23, z31"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x69, 0xe8, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlslb z23.s, z13.h, z0.h[3]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0xe0, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlslb z0.s, z0.h, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x61, 0xf5, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlslb z21.s, z10.h, z5.h[4]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x69, 0xe8, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlslb z23.s, z13.h, z0.h[3]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x6b, 0xff, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlslb z31.s, z31.h, z7.h[7]"
+
+  -
+    input:
+      bytes: [ 0xf7, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z23, z31"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xa1, 0xe8, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlslb z23.s, z13.h, z8.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xe0, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlslb z0.s, z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x55, 0xa1, 0xf5, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlslb z21.s, z10.h, z21.h"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xa1, 0xe8, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlslb z23.s, z13.h, z8.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0xa3, 0xff, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlslb z31.s, z31.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xf7, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z23, z31"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x69, 0xe8, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlslb z23.s, z13.h, z0.h[3]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0xe0, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlslb z0.s, z0.h, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x61, 0xf5, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlslb z21.s, z10.h, z5.h[4]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x69, 0xe8, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlslb z23.s, z13.h, z0.h[3]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x6b, 0xff, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlslb z31.s, z31.h, z7.h[7]"
diff --git a/tests/MC/AArch64/SVE2p1/bfmlslt.s.yaml b/tests/MC/AArch64/SVE2p1/bfmlslt.s.yaml
new file mode 100644
index 000000000..86e4cb923
--- /dev/null
+++ b/tests/MC/AArch64/SVE2p1/bfmlslt.s.yaml
@@ -0,0 +1,240 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xf7, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z23, z31"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xa5, 0xe8, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlslt z23.s, z13.h, z8.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa4, 0xe0, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlslt z0.s, z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x55, 0xa5, 0xf5, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlslt z21.s, z10.h, z21.h"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xa5, 0xe8, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlslt z23.s, z13.h, z8.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0xa7, 0xff, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlslt z31.s, z31.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xf7, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z23, z31"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x6d, 0xe8, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlslt z23.s, z13.h, z0.h[3]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x64, 0xe0, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlslt z0.s, z0.h, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x65, 0xf5, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlslt z21.s, z10.h, z5.h[4]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x6d, 0xe8, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlslt z23.s, z13.h, z0.h[3]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x6f, 0xff, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlslt z31.s, z31.h, z7.h[7]"
+
+  -
+    input:
+      bytes: [ 0xf7, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z23, z31"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xa5, 0xe8, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlslt z23.s, z13.h, z8.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa4, 0xe0, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlslt z0.s, z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x55, 0xa5, 0xf5, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlslt z21.s, z10.h, z21.h"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xa5, 0xe8, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlslt z23.s, z13.h, z8.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0xa7, 0xff, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlslt z31.s, z31.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xf7, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z23, z31"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x6d, 0xe8, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlslt z23.s, z13.h, z0.h[3]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x64, 0xe0, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlslt z0.s, z0.h, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x65, 0xf5, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlslt z21.s, z10.h, z5.h[4]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x6d, 0xe8, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlslt z23.s, z13.h, z0.h[3]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x6f, 0xff, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlslt z31.s, z31.h, z7.h[7]"
diff --git a/tests/MC/AArch64/SVE2p1/bfmul.s.yaml b/tests/MC/AArch64/SVE2p1/bfmul.s.yaml
new file mode 100644
index 000000000..fe0eb564a
--- /dev/null
+++ b/tests/MC/AArch64/SVE2p1/bfmul.s.yaml
@@ -0,0 +1,160 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x28, 0x20, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmul z0.h, z0.h, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x29, 0x75, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmul z21.h, z10.h, z5.h[6]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x29, 0x68, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmul z23.h, z13.h, z0.h[5]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x2b, 0x7f, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmul z31.h, z31.h, z7.h[7]"
+
+  -
+    input:
+      bytes: [ 0xf7, 0x2f, 0x51, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z23.h, p3/m, z31.h"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x8d, 0x02, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmul z23.h, p3/m, z23.h, z13.h"
+
+  -
+    input:
+      bytes: [ 0xf7, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z23, z31"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x8d, 0x02, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmul z23.h, p3/m, z23.h, z13.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x02, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmul z0.h, p0/m, z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x55, 0x95, 0x02, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmul z21.h, p5/m, z21.h, z10.h"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x8d, 0x02, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmul z23.h, p3/m, z23.h, z13.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x9f, 0x02, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmul z31.h, p7/m, z31.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x08, 0x00, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmul z0.h, z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x55, 0x09, 0x15, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmul z21.h, z10.h, z21.h"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x09, 0x08, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmul z23.h, z13.h, z8.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x0b, 0x1f, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmul z31.h, z31.h, z31.h"
diff --git a/tests/MC/AArch64/SVE2p1/bfsub.s.yaml b/tests/MC/AArch64/SVE2p1/bfsub.s.yaml
new file mode 100644
index 000000000..b243bb772
--- /dev/null
+++ b/tests/MC/AArch64/SVE2p1/bfsub.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xf7, 0x2f, 0x51, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z23.h, p3/m, z31.h"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x8d, 0x01, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfsub z23.h, p3/m, z23.h, z13.h"
+
+  -
+    input:
+      bytes: [ 0xf7, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z23, z31"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x8d, 0x01, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfsub z23.h, p3/m, z23.h, z13.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x01, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfsub z0.h, p0/m, z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x55, 0x95, 0x01, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfsub z21.h, p5/m, z21.h, z10.h"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x8d, 0x01, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfsub z23.h, p3/m, z23.h, z13.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x9f, 0x01, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfsub z31.h, p7/m, z31.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x04, 0x00, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfsub z0.h, z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x55, 0x05, 0x15, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfsub z21.h, z10.h, z21.h"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x05, 0x08, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfsub z23.h, z13.h, z8.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x07, 0x1f, 0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2", "+b16b16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfsub z31.h, z31.h, z31.h"
diff --git a/tests/MC/AArch64/SVE2p1/cntp.s.yaml b/tests/MC/AArch64/SVE2p1/cntp.s.yaml
new file mode 100644
index 000000000..1975135db
--- /dev/null
+++ b/tests/MC/AArch64/SVE2p1/cntp.s.yaml
@@ -0,0 +1,320 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x82, 0x60, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "cntp x0, pn0.h, vlx2"
+
+  -
+    input:
+      bytes: [ 0x55, 0x87, 0x60, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "cntp x21, pn10.h, vlx4"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x87, 0x60, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "cntp x23, pn13.h, vlx4"
+
+  -
+    input:
+      bytes: [ 0xff, 0x87, 0x60, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "cntp xzr, pn15.h, vlx4"
+
+  -
+    input:
+      bytes: [ 0x00, 0x82, 0xa0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "cntp x0, pn0.s, vlx2"
+
+  -
+    input:
+      bytes: [ 0x55, 0x87, 0xa0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "cntp x21, pn10.s, vlx4"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x87, 0xa0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "cntp x23, pn13.s, vlx4"
+
+  -
+    input:
+      bytes: [ 0xff, 0x87, 0xa0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "cntp xzr, pn15.s, vlx4"
+
+  -
+    input:
+      bytes: [ 0x00, 0x82, 0xe0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "cntp x0, pn0.d, vlx2"
+
+  -
+    input:
+      bytes: [ 0x55, 0x87, 0xe0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "cntp x21, pn10.d, vlx4"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x87, 0xe0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "cntp x23, pn13.d, vlx4"
+
+  -
+    input:
+      bytes: [ 0xff, 0x87, 0xe0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "cntp xzr, pn15.d, vlx4"
+
+  -
+    input:
+      bytes: [ 0x00, 0x82, 0x20, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "cntp x0, pn0.b, vlx2"
+
+  -
+    input:
+      bytes: [ 0x55, 0x87, 0x20, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "cntp x21, pn10.b, vlx4"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x87, 0x20, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "cntp x23, pn13.b, vlx4"
+
+  -
+    input:
+      bytes: [ 0xff, 0x87, 0x20, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "cntp xzr, pn15.b, vlx4"
+
+  -
+    input:
+      bytes: [ 0x00, 0x82, 0x60, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "cntp x0, pn0.h, vlx2"
+
+  -
+    input:
+      bytes: [ 0x55, 0x87, 0x60, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "cntp x21, pn10.h, vlx4"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x87, 0x60, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "cntp x23, pn13.h, vlx4"
+
+  -
+    input:
+      bytes: [ 0xff, 0x87, 0x60, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "cntp xzr, pn15.h, vlx4"
+
+  -
+    input:
+      bytes: [ 0x00, 0x82, 0xa0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "cntp x0, pn0.s, vlx2"
+
+  -
+    input:
+      bytes: [ 0x55, 0x87, 0xa0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "cntp x21, pn10.s, vlx4"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x87, 0xa0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "cntp x23, pn13.s, vlx4"
+
+  -
+    input:
+      bytes: [ 0xff, 0x87, 0xa0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "cntp xzr, pn15.s, vlx4"
+
+  -
+    input:
+      bytes: [ 0x00, 0x82, 0xe0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "cntp x0, pn0.d, vlx2"
+
+  -
+    input:
+      bytes: [ 0x55, 0x87, 0xe0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "cntp x21, pn10.d, vlx4"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x87, 0xe0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "cntp x23, pn13.d, vlx4"
+
+  -
+    input:
+      bytes: [ 0xff, 0x87, 0xe0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "cntp xzr, pn15.d, vlx4"
+
+  -
+    input:
+      bytes: [ 0x00, 0x82, 0x20, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "cntp x0, pn0.b, vlx2"
+
+  -
+    input:
+      bytes: [ 0x55, 0x87, 0x20, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "cntp x21, pn10.b, vlx4"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x87, 0x20, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "cntp x23, pn13.b, vlx4"
+
+  -
+    input:
+      bytes: [ 0xff, 0x87, 0x20, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "cntp xzr, pn15.b, vlx4"
diff --git a/tests/MC/AArch64/SVE2p1/dupq.s.yaml b/tests/MC/AArch64/SVE2p1/dupq.s.yaml
new file mode 100644
index 000000000..0f8f7c102
--- /dev/null
+++ b/tests/MC/AArch64/SVE2p1/dupq.s.yaml
@@ -0,0 +1,320 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x24, 0x22, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "dupq z0.h, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x25, 0x36, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "dupq z21.h, z10.h[5]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x25, 0x2a, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "dupq z23.h, z13.h[2]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x27, 0x3e, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "dupq z31.h, z31.h[7]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x24, 0x24, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "dupq z0.s, z0.s[0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x25, 0x34, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "dupq z21.s, z10.s[2]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x25, 0x2c, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "dupq z23.s, z13.s[1]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x27, 0x3c, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "dupq z31.s, z31.s[3]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x24, 0x28, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "dupq z0.d, z0.d[0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x25, 0x38, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "dupq z21.d, z10.d[1]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x25, 0x28, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "dupq z23.d, z13.d[0]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x27, 0x38, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "dupq z31.d, z31.d[1]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x24, 0x21, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "dupq z0.b, z0.b[0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x25, 0x35, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "dupq z21.b, z10.b[10]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x25, 0x29, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "dupq z23.b, z13.b[4]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x27, 0x3f, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "dupq z31.b, z31.b[15]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x24, 0x22, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "dupq z0.h, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x25, 0x36, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "dupq z21.h, z10.h[5]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x25, 0x2a, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "dupq z23.h, z13.h[2]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x27, 0x3e, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "dupq z31.h, z31.h[7]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x24, 0x24, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "dupq z0.s, z0.s[0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x25, 0x34, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "dupq z21.s, z10.s[2]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x25, 0x2c, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "dupq z23.s, z13.s[1]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x27, 0x3c, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "dupq z31.s, z31.s[3]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x24, 0x28, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "dupq z0.d, z0.d[0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x25, 0x38, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "dupq z21.d, z10.d[1]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x25, 0x28, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "dupq z23.d, z13.d[0]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x27, 0x38, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "dupq z31.d, z31.d[1]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x24, 0x21, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "dupq z0.b, z0.b[0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x25, 0x35, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "dupq z21.b, z10.b[10]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x25, 0x29, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "dupq z23.b, z13.b[4]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x27, 0x3f, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "dupq z31.b, z31.b[15]"
diff --git a/tests/MC/AArch64/SVE2p1/eorqv.s.yaml b/tests/MC/AArch64/SVE2p1/eorqv.s.yaml
new file mode 100644
index 000000000..1d413c0c0
--- /dev/null
+++ b/tests/MC/AArch64/SVE2p1/eorqv.s.yaml
@@ -0,0 +1,320 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x5d, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "eorqv v0.8h, p0, z0.h"
+
+  -
+    input:
+      bytes: [ 0x55, 0x35, 0x5d, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "eorqv v21.8h, p5, z10.h"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x2d, 0x5d, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "eorqv v23.8h, p3, z13.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0x5d, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "eorqv v31.8h, p7, z31.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x9d, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "eorqv v0.4s, p0, z0.s"
+
+  -
+    input:
+      bytes: [ 0x55, 0x35, 0x9d, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "eorqv v21.4s, p5, z10.s"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x2d, 0x9d, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "eorqv v23.4s, p3, z13.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0x9d, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "eorqv v31.4s, p7, z31.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0xdd, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "eorqv v0.2d, p0, z0.d"
+
+  -
+    input:
+      bytes: [ 0x55, 0x35, 0xdd, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "eorqv v21.2d, p5, z10.d"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x2d, 0xdd, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "eorqv v23.2d, p3, z13.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0xdd, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "eorqv v31.2d, p7, z31.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x1d, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "eorqv v0.16b, p0, z0.b"
+
+  -
+    input:
+      bytes: [ 0x55, 0x35, 0x1d, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "eorqv v21.16b, p5, z10.b"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x2d, 0x1d, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "eorqv v23.16b, p3, z13.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0x1d, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "eorqv v31.16b, p7, z31.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x5d, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "eorqv v0.8h, p0, z0.h"
+
+  -
+    input:
+      bytes: [ 0x55, 0x35, 0x5d, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "eorqv v21.8h, p5, z10.h"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x2d, 0x5d, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "eorqv v23.8h, p3, z13.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0x5d, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "eorqv v31.8h, p7, z31.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x9d, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "eorqv v0.4s, p0, z0.s"
+
+  -
+    input:
+      bytes: [ 0x55, 0x35, 0x9d, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "eorqv v21.4s, p5, z10.s"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x2d, 0x9d, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "eorqv v23.4s, p3, z13.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0x9d, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "eorqv v31.4s, p7, z31.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0xdd, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "eorqv v0.2d, p0, z0.d"
+
+  -
+    input:
+      bytes: [ 0x55, 0x35, 0xdd, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "eorqv v21.2d, p5, z10.d"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x2d, 0xdd, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "eorqv v23.2d, p3, z13.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0xdd, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "eorqv v31.2d, p7, z31.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x1d, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "eorqv v0.16b, p0, z0.b"
+
+  -
+    input:
+      bytes: [ 0x55, 0x35, 0x1d, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "eorqv v21.16b, p5, z10.b"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x2d, 0x1d, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "eorqv v23.16b, p3, z13.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0x1d, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "eorqv v31.16b, p7, z31.b"
diff --git a/tests/MC/AArch64/SVE2p1/extq.s.yaml b/tests/MC/AArch64/SVE2p1/extq.s.yaml
new file mode 100644
index 000000000..0195b1462
--- /dev/null
+++ b/tests/MC/AArch64/SVE2p1/extq.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xf7, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z23, z31"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x25, 0x68, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "extq z23.b, z23.b, z13.b, #8"
+
+  -
+    input:
+      bytes: [ 0x00, 0x24, 0x60, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "extq z0.b, z0.b, z0.b, #0"
+
+  -
+    input:
+      bytes: [ 0x55, 0x25, 0x65, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "extq z21.b, z21.b, z10.b, #5"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x25, 0x68, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "extq z23.b, z23.b, z13.b, #8"
+
+  -
+    input:
+      bytes: [ 0xff, 0x27, 0x6f, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "extq z31.b, z31.b, z31.b, #15"
+
+  -
+    input:
+      bytes: [ 0xf7, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z23, z31"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x25, 0x68, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "extq z23.b, z23.b, z13.b, #8"
+
+  -
+    input:
+      bytes: [ 0x00, 0x24, 0x60, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "extq z0.b, z0.b, z0.b, #0"
+
+  -
+    input:
+      bytes: [ 0x55, 0x25, 0x65, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "extq z21.b, z21.b, z10.b, #5"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x25, 0x68, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "extq z23.b, z23.b, z13.b, #8"
+
+  -
+    input:
+      bytes: [ 0xff, 0x27, 0x6f, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "extq z31.b, z31.b, z31.b, #15"
diff --git a/tests/MC/AArch64/SVE2p1/faddqv.s.yaml b/tests/MC/AArch64/SVE2p1/faddqv.s.yaml
new file mode 100644
index 000000000..b0fa9e6c9
--- /dev/null
+++ b/tests/MC/AArch64/SVE2p1/faddqv.s.yaml
@@ -0,0 +1,240 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xd0, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "faddqv v0.2d, p0, z0.d"
+
+  -
+    input:
+      bytes: [ 0x55, 0xb5, 0xd0, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "faddqv v21.2d, p5, z10.d"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xad, 0xd0, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "faddqv v23.2d, p3, z13.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0xd0, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "faddqv v31.2d, p7, z31.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x50, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "faddqv v0.8h, p0, z0.h"
+
+  -
+    input:
+      bytes: [ 0x55, 0xb5, 0x50, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "faddqv v21.8h, p5, z10.h"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xad, 0x50, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "faddqv v23.8h, p3, z13.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x50, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "faddqv v31.8h, p7, z31.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x90, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "faddqv v0.4s, p0, z0.s"
+
+  -
+    input:
+      bytes: [ 0x55, 0xb5, 0x90, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "faddqv v21.4s, p5, z10.s"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xad, 0x90, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "faddqv v23.4s, p3, z13.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x90, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "faddqv v31.4s, p7, z31.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xd0, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "faddqv v0.2d, p0, z0.d"
+
+  -
+    input:
+      bytes: [ 0x55, 0xb5, 0xd0, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "faddqv v21.2d, p5, z10.d"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xad, 0xd0, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "faddqv v23.2d, p3, z13.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0xd0, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "faddqv v31.2d, p7, z31.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x50, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "faddqv v0.8h, p0, z0.h"
+
+  -
+    input:
+      bytes: [ 0x55, 0xb5, 0x50, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "faddqv v21.8h, p5, z10.h"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xad, 0x50, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "faddqv v23.8h, p3, z13.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x50, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "faddqv v31.8h, p7, z31.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x90, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "faddqv v0.4s, p0, z0.s"
+
+  -
+    input:
+      bytes: [ 0x55, 0xb5, 0x90, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "faddqv v21.4s, p5, z10.s"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xad, 0x90, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "faddqv v23.4s, p3, z13.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x90, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "faddqv v31.4s, p7, z31.s"
diff --git a/tests/MC/AArch64/SVE2p1/fclamp.s.yaml b/tests/MC/AArch64/SVE2p1/fclamp.s.yaml
new file mode 100644
index 000000000..a4dad9306
--- /dev/null
+++ b/tests/MC/AArch64/SVE2p1/fclamp.s.yaml
@@ -0,0 +1,360 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xf7, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z23, z31"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x25, 0xe8, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fclamp z23.d, z13.d, z8.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x24, 0xe0, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fclamp z0.d, z0.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0x55, 0x25, 0xf5, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fclamp z21.d, z10.d, z21.d"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x25, 0xe8, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fclamp z23.d, z13.d, z8.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0x27, 0xff, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fclamp z31.d, z31.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xf7, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z23, z31"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x25, 0x68, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fclamp z23.h, z13.h, z8.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x24, 0x60, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fclamp z0.h, z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x55, 0x25, 0x75, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fclamp z21.h, z10.h, z21.h"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x25, 0x68, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fclamp z23.h, z13.h, z8.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x27, 0x7f, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fclamp z31.h, z31.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xf7, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z23, z31"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x25, 0xa8, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fclamp z23.s, z13.s, z8.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0x24, 0xa0, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fclamp z0.s, z0.s, z0.s"
+
+  -
+    input:
+      bytes: [ 0x55, 0x25, 0xb5, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fclamp z21.s, z10.s, z21.s"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x25, 0xa8, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fclamp z23.s, z13.s, z8.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0x27, 0xbf, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fclamp z31.s, z31.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0xf7, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z23, z31"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x25, 0xe8, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fclamp z23.d, z13.d, z8.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x24, 0xe0, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fclamp z0.d, z0.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0x55, 0x25, 0xf5, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fclamp z21.d, z10.d, z21.d"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x25, 0xe8, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fclamp z23.d, z13.d, z8.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0x27, 0xff, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fclamp z31.d, z31.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0xf7, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z23, z31"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x25, 0x68, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fclamp z23.h, z13.h, z8.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x24, 0x60, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fclamp z0.h, z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x55, 0x25, 0x75, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fclamp z21.h, z10.h, z21.h"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x25, 0x68, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fclamp z23.h, z13.h, z8.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x27, 0x7f, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fclamp z31.h, z31.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xf7, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z23, z31"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x25, 0xa8, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fclamp z23.s, z13.s, z8.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0x24, 0xa0, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fclamp z0.s, z0.s, z0.s"
+
+  -
+    input:
+      bytes: [ 0x55, 0x25, 0xb5, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fclamp z21.s, z10.s, z21.s"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x25, 0xa8, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fclamp z23.s, z13.s, z8.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0x27, 0xbf, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fclamp z31.s, z31.s, z31.s"
diff --git a/tests/MC/AArch64/SVE2p1/fdot.s.yaml b/tests/MC/AArch64/SVE2p1/fdot.s.yaml
new file mode 100644
index 000000000..ef62304bd
--- /dev/null
+++ b/tests/MC/AArch64/SVE2p1/fdot.s.yaml
@@ -0,0 +1,240 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xf7, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z23, z31"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x81, 0x28, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot z23.s, z13.h, z8.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x20, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot z0.s, z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x55, 0x81, 0x35, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot z21.s, z10.h, z21.h"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x81, 0x28, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot z23.s, z13.h, z8.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x83, 0x3f, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot z31.s, z31.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xf7, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z23, z31"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x41, 0x28, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot z23.s, z13.h, z0.h[1]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0x20, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot z0.s, z0.h, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x41, 0x35, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot z21.s, z10.h, z5.h[2]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x41, 0x28, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot z23.s, z13.h, z0.h[1]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x43, 0x3f, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot z31.s, z31.h, z7.h[3]"
+
+  -
+    input:
+      bytes: [ 0xf7, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z23, z31"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x81, 0x28, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot z23.s, z13.h, z8.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x20, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot z0.s, z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x55, 0x81, 0x35, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot z21.s, z10.h, z21.h"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x81, 0x28, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot z23.s, z13.h, z8.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x83, 0x3f, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot z31.s, z31.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xf7, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z23, z31"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x41, 0x28, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot z23.s, z13.h, z0.h[1]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0x20, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot z0.s, z0.h, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x41, 0x35, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot z21.s, z10.h, z5.h[2]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x41, 0x28, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot z23.s, z13.h, z0.h[1]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x43, 0x3f, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdot z31.s, z31.h, z7.h[3]"
diff --git a/tests/MC/AArch64/SVE2p1/feature-sve2p1-implies-sve2.s.yaml b/tests/MC/AArch64/SVE2p1/feature-sve2p1-implies-sve2.s.yaml
new file mode 100644
index 000000000..f7f5644c5
--- /dev/null
+++ b/tests/MC/AArch64/SVE2p1/feature-sve2p1-implies-sve2.s.yaml
@@ -0,0 +1,10 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x20, 0x02, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmla z0.b, z1.b, z2.b, #0"
diff --git a/tests/MC/AArch64/SVE2p1/fmaxnmqv.s.yaml b/tests/MC/AArch64/SVE2p1/fmaxnmqv.s.yaml
new file mode 100644
index 000000000..8de0e1d13
--- /dev/null
+++ b/tests/MC/AArch64/SVE2p1/fmaxnmqv.s.yaml
@@ -0,0 +1,240 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xd4, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnmqv v0.2d, p0, z0.d"
+
+  -
+    input:
+      bytes: [ 0x55, 0xb5, 0xd4, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnmqv v21.2d, p5, z10.d"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xad, 0xd4, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnmqv v23.2d, p3, z13.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0xd4, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnmqv v31.2d, p7, z31.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x54, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnmqv v0.8h, p0, z0.h"
+
+  -
+    input:
+      bytes: [ 0x55, 0xb5, 0x54, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnmqv v21.8h, p5, z10.h"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xad, 0x54, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnmqv v23.8h, p3, z13.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x54, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnmqv v31.8h, p7, z31.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x94, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnmqv v0.4s, p0, z0.s"
+
+  -
+    input:
+      bytes: [ 0x55, 0xb5, 0x94, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnmqv v21.4s, p5, z10.s"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xad, 0x94, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnmqv v23.4s, p3, z13.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x94, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnmqv v31.4s, p7, z31.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xd4, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnmqv v0.2d, p0, z0.d"
+
+  -
+    input:
+      bytes: [ 0x55, 0xb5, 0xd4, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnmqv v21.2d, p5, z10.d"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xad, 0xd4, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnmqv v23.2d, p3, z13.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0xd4, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnmqv v31.2d, p7, z31.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x54, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnmqv v0.8h, p0, z0.h"
+
+  -
+    input:
+      bytes: [ 0x55, 0xb5, 0x54, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnmqv v21.8h, p5, z10.h"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xad, 0x54, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnmqv v23.8h, p3, z13.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x54, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnmqv v31.8h, p7, z31.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x94, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnmqv v0.4s, p0, z0.s"
+
+  -
+    input:
+      bytes: [ 0x55, 0xb5, 0x94, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnmqv v21.4s, p5, z10.s"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xad, 0x94, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnmqv v23.4s, p3, z13.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x94, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnmqv v31.4s, p7, z31.s"
diff --git a/tests/MC/AArch64/SVE2p1/fmaxqv.s.yaml b/tests/MC/AArch64/SVE2p1/fmaxqv.s.yaml
new file mode 100644
index 000000000..5039327e4
--- /dev/null
+++ b/tests/MC/AArch64/SVE2p1/fmaxqv.s.yaml
@@ -0,0 +1,240 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xd6, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxqv v0.2d, p0, z0.d"
+
+  -
+    input:
+      bytes: [ 0x55, 0xb5, 0xd6, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxqv v21.2d, p5, z10.d"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xad, 0xd6, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxqv v23.2d, p3, z13.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0xd6, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxqv v31.2d, p7, z31.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x56, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxqv v0.8h, p0, z0.h"
+
+  -
+    input:
+      bytes: [ 0x55, 0xb5, 0x56, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxqv v21.8h, p5, z10.h"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xad, 0x56, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxqv v23.8h, p3, z13.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x56, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxqv v31.8h, p7, z31.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x96, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxqv v0.4s, p0, z0.s"
+
+  -
+    input:
+      bytes: [ 0x55, 0xb5, 0x96, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxqv v21.4s, p5, z10.s"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xad, 0x96, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxqv v23.4s, p3, z13.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x96, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxqv v31.4s, p7, z31.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xd6, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxqv v0.2d, p0, z0.d"
+
+  -
+    input:
+      bytes: [ 0x55, 0xb5, 0xd6, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxqv v21.2d, p5, z10.d"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xad, 0xd6, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxqv v23.2d, p3, z13.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0xd6, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxqv v31.2d, p7, z31.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x56, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxqv v0.8h, p0, z0.h"
+
+  -
+    input:
+      bytes: [ 0x55, 0xb5, 0x56, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxqv v21.8h, p5, z10.h"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xad, 0x56, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxqv v23.8h, p3, z13.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x56, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxqv v31.8h, p7, z31.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x96, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxqv v0.4s, p0, z0.s"
+
+  -
+    input:
+      bytes: [ 0x55, 0xb5, 0x96, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxqv v21.4s, p5, z10.s"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xad, 0x96, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxqv v23.4s, p3, z13.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x96, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxqv v31.4s, p7, z31.s"
diff --git a/tests/MC/AArch64/SVE2p1/fminnmqv.s.yaml b/tests/MC/AArch64/SVE2p1/fminnmqv.s.yaml
new file mode 100644
index 000000000..33bbd9a3c
--- /dev/null
+++ b/tests/MC/AArch64/SVE2p1/fminnmqv.s.yaml
@@ -0,0 +1,240 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xd5, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnmqv v0.2d, p0, z0.d"
+
+  -
+    input:
+      bytes: [ 0x55, 0xb5, 0xd5, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnmqv v21.2d, p5, z10.d"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xad, 0xd5, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnmqv v23.2d, p3, z13.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0xd5, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnmqv v31.2d, p7, z31.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x55, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnmqv v0.8h, p0, z0.h"
+
+  -
+    input:
+      bytes: [ 0x55, 0xb5, 0x55, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnmqv v21.8h, p5, z10.h"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xad, 0x55, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnmqv v23.8h, p3, z13.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x55, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnmqv v31.8h, p7, z31.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x95, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnmqv v0.4s, p0, z0.s"
+
+  -
+    input:
+      bytes: [ 0x55, 0xb5, 0x95, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnmqv v21.4s, p5, z10.s"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xad, 0x95, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnmqv v23.4s, p3, z13.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x95, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnmqv v31.4s, p7, z31.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xd5, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnmqv v0.2d, p0, z0.d"
+
+  -
+    input:
+      bytes: [ 0x55, 0xb5, 0xd5, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnmqv v21.2d, p5, z10.d"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xad, 0xd5, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnmqv v23.2d, p3, z13.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0xd5, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnmqv v31.2d, p7, z31.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x55, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnmqv v0.8h, p0, z0.h"
+
+  -
+    input:
+      bytes: [ 0x55, 0xb5, 0x55, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnmqv v21.8h, p5, z10.h"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xad, 0x55, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnmqv v23.8h, p3, z13.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x55, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnmqv v31.8h, p7, z31.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x95, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnmqv v0.4s, p0, z0.s"
+
+  -
+    input:
+      bytes: [ 0x55, 0xb5, 0x95, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnmqv v21.4s, p5, z10.s"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xad, 0x95, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnmqv v23.4s, p3, z13.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x95, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnmqv v31.4s, p7, z31.s"
diff --git a/tests/MC/AArch64/SVE2p1/fminqv.s.yaml b/tests/MC/AArch64/SVE2p1/fminqv.s.yaml
new file mode 100644
index 000000000..3d3516529
--- /dev/null
+++ b/tests/MC/AArch64/SVE2p1/fminqv.s.yaml
@@ -0,0 +1,240 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xd7, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminqv v0.2d, p0, z0.d"
+
+  -
+    input:
+      bytes: [ 0x55, 0xb5, 0xd7, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminqv v21.2d, p5, z10.d"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xad, 0xd7, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminqv v23.2d, p3, z13.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0xd7, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminqv v31.2d, p7, z31.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x57, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminqv v0.8h, p0, z0.h"
+
+  -
+    input:
+      bytes: [ 0x55, 0xb5, 0x57, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminqv v21.8h, p5, z10.h"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xad, 0x57, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminqv v23.8h, p3, z13.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x57, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminqv v31.8h, p7, z31.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x97, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminqv v0.4s, p0, z0.s"
+
+  -
+    input:
+      bytes: [ 0x55, 0xb5, 0x97, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminqv v21.4s, p5, z10.s"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xad, 0x97, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminqv v23.4s, p3, z13.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x97, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminqv v31.4s, p7, z31.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xd7, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminqv v0.2d, p0, z0.d"
+
+  -
+    input:
+      bytes: [ 0x55, 0xb5, 0xd7, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminqv v21.2d, p5, z10.d"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xad, 0xd7, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminqv v23.2d, p3, z13.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0xd7, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminqv v31.2d, p7, z31.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x57, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminqv v0.8h, p0, z0.h"
+
+  -
+    input:
+      bytes: [ 0x55, 0xb5, 0x57, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminqv v21.8h, p5, z10.h"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xad, 0x57, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminqv v23.8h, p3, z13.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x57, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminqv v31.8h, p7, z31.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x97, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminqv v0.4s, p0, z0.s"
+
+  -
+    input:
+      bytes: [ 0x55, 0xb5, 0x97, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminqv v21.4s, p5, z10.s"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xad, 0x97, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminqv v23.4s, p3, z13.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x97, 0x64 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminqv v31.4s, p7, z31.s"
diff --git a/tests/MC/AArch64/SVE2p1/ld1b.s.yaml b/tests/MC/AArch64/SVE2p1/ld1b.s.yaml
new file mode 100644
index 000000000..ac07f4c6f
--- /dev/null
+++ b/tests/MC/AArch64/SVE2p1/ld1b.s.yaml
@@ -0,0 +1,320 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x00, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b { z0.b, z1.b }, pn8/z, [x0, x0]"
+
+  -
+    input:
+      bytes: [ 0x54, 0x15, 0x15, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b { z20.b, z21.b }, pn13/z, [x10, x21]"
+
+  -
+    input:
+      bytes: [ 0xb6, 0x0d, 0x08, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b { z22.b, z23.b }, pn11/z, [x13, x8]"
+
+  -
+    input:
+      bytes: [ 0xfe, 0x1f, 0x1f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b { z30.b, z31.b }, pn15/z, [sp, xzr]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x40, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b { z0.b, z1.b }, pn8/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x54, 0x15, 0x45, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b { z20.b, z21.b }, pn13/z, [x10, #10, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xb6, 0x0d, 0x48, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b { z22.b, z23.b }, pn11/z, [x13, #-16, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xfe, 0x1f, 0x4f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b { z30.b, z31.b }, pn15/z, [sp, #-2, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x00, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b { z0.b - z3.b }, pn8/z, [x0, x0]"
+
+  -
+    input:
+      bytes: [ 0x54, 0x95, 0x15, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b { z20.b - z23.b }, pn13/z, [x10, x21]"
+
+  -
+    input:
+      bytes: [ 0xb4, 0x8d, 0x08, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b { z20.b - z23.b }, pn11/z, [x13, x8]"
+
+  -
+    input:
+      bytes: [ 0xfc, 0x9f, 0x1f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b { z28.b - z31.b }, pn15/z, [sp, xzr]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x40, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b { z0.b - z3.b }, pn8/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x54, 0x95, 0x45, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b { z20.b - z23.b }, pn13/z, [x10, #20, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xb4, 0x8d, 0x48, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b { z20.b - z23.b }, pn11/z, [x13, #-32, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xfc, 0x9f, 0x4f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b { z28.b - z31.b }, pn15/z, [sp, #-4, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x00, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b { z0.b, z1.b }, pn8/z, [x0, x0]"
+
+  -
+    input:
+      bytes: [ 0x54, 0x15, 0x15, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b { z20.b, z21.b }, pn13/z, [x10, x21]"
+
+  -
+    input:
+      bytes: [ 0xb6, 0x0d, 0x08, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b { z22.b, z23.b }, pn11/z, [x13, x8]"
+
+  -
+    input:
+      bytes: [ 0xfe, 0x1f, 0x1f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b { z30.b, z31.b }, pn15/z, [sp, xzr]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x40, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b { z0.b, z1.b }, pn8/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x54, 0x15, 0x45, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b { z20.b, z21.b }, pn13/z, [x10, #10, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xb6, 0x0d, 0x48, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b { z22.b, z23.b }, pn11/z, [x13, #-16, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xfe, 0x1f, 0x4f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b { z30.b, z31.b }, pn15/z, [sp, #-2, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x00, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b { z0.b - z3.b }, pn8/z, [x0, x0]"
+
+  -
+    input:
+      bytes: [ 0x54, 0x95, 0x15, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b { z20.b - z23.b }, pn13/z, [x10, x21]"
+
+  -
+    input:
+      bytes: [ 0xb4, 0x8d, 0x08, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b { z20.b - z23.b }, pn11/z, [x13, x8]"
+
+  -
+    input:
+      bytes: [ 0xfc, 0x9f, 0x1f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b { z28.b - z31.b }, pn15/z, [sp, xzr]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x40, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b { z0.b - z3.b }, pn8/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x54, 0x95, 0x45, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b { z20.b - z23.b }, pn13/z, [x10, #20, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xb4, 0x8d, 0x48, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b { z20.b - z23.b }, pn11/z, [x13, #-32, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xfc, 0x9f, 0x4f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1b { z28.b - z31.b }, pn15/z, [sp, #-4, mul vl]"
diff --git a/tests/MC/AArch64/SVE2p1/ld1d.s.yaml b/tests/MC/AArch64/SVE2p1/ld1d.s.yaml
new file mode 100644
index 000000000..79240c648
--- /dev/null
+++ b/tests/MC/AArch64/SVE2p1/ld1d.s.yaml
@@ -0,0 +1,320 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0x00, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d { z0.d, z1.d }, pn8/z, [x0, x0, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x54, 0x75, 0x15, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d { z20.d, z21.d }, pn13/z, [x10, x21, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0xb6, 0x6d, 0x08, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d { z22.d, z23.d }, pn11/z, [x13, x8, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0xfe, 0x7f, 0x1f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d { z30.d, z31.d }, pn15/z, [sp, xzr, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0x40, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d { z0.d, z1.d }, pn8/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x54, 0x75, 0x45, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d { z20.d, z21.d }, pn13/z, [x10, #10, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xb6, 0x6d, 0x48, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d { z22.d, z23.d }, pn11/z, [x13, #-16, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xfe, 0x7f, 0x4f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d { z30.d, z31.d }, pn15/z, [sp, #-2, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x00, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d { z0.d - z3.d }, pn8/z, [x0, x0, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x54, 0xf5, 0x15, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d { z20.d - z23.d }, pn13/z, [x10, x21, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0xb4, 0xed, 0x08, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d { z20.d - z23.d }, pn11/z, [x13, x8, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0xfc, 0xff, 0x1f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d { z28.d - z31.d }, pn15/z, [sp, xzr, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x40, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d { z0.d - z3.d }, pn8/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x54, 0xf5, 0x45, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d { z20.d - z23.d }, pn13/z, [x10, #20, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xb4, 0xed, 0x48, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d { z20.d - z23.d }, pn11/z, [x13, #-32, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xfc, 0xff, 0x4f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d { z28.d - z31.d }, pn15/z, [sp, #-4, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0x00, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d { z0.d, z1.d }, pn8/z, [x0, x0, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x54, 0x75, 0x15, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d { z20.d, z21.d }, pn13/z, [x10, x21, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0xb6, 0x6d, 0x08, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d { z22.d, z23.d }, pn11/z, [x13, x8, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0xfe, 0x7f, 0x1f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d { z30.d, z31.d }, pn15/z, [sp, xzr, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0x40, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d { z0.d, z1.d }, pn8/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x54, 0x75, 0x45, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d { z20.d, z21.d }, pn13/z, [x10, #10, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xb6, 0x6d, 0x48, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d { z22.d, z23.d }, pn11/z, [x13, #-16, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xfe, 0x7f, 0x4f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d { z30.d, z31.d }, pn15/z, [sp, #-2, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x00, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d { z0.d - z3.d }, pn8/z, [x0, x0, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x54, 0xf5, 0x15, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d { z20.d - z23.d }, pn13/z, [x10, x21, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0xb4, 0xed, 0x08, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d { z20.d - z23.d }, pn11/z, [x13, x8, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0xfc, 0xff, 0x1f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d { z28.d - z31.d }, pn15/z, [sp, xzr, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x40, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d { z0.d - z3.d }, pn8/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x54, 0xf5, 0x45, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d { z20.d - z23.d }, pn13/z, [x10, #20, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xb4, 0xed, 0x48, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d { z20.d - z23.d }, pn11/z, [x13, #-32, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xfc, 0xff, 0x4f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d { z28.d - z31.d }, pn15/z, [sp, #-4, mul vl]"
diff --git a/tests/MC/AArch64/SVE2p1/ld1d_q.s.yaml b/tests/MC/AArch64/SVE2p1/ld1d_q.s.yaml
new file mode 100644
index 000000000..78820c6e9
--- /dev/null
+++ b/tests/MC/AArch64/SVE2p1/ld1d_q.s.yaml
@@ -0,0 +1,100 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x80, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d { z0.q }, p0/z, [x0, x0, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x95, 0x95, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d { z21.q }, p5/z, [x10, x21, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x8d, 0x88, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d { z23.q }, p3/z, [x13, x8, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x8d, 0x88, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d { z23.q }, p3/z, [x13, x8, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x90, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d { z0.q }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x90, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d { z0.q }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x35, 0x95, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d { z21.q }, p5/z, [x10, #5, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x2d, 0x98, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d { z23.q }, p3/z, [x13, #-8, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0x9f, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d { z31.q }, p7/z, [sp, #-1, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0x9f, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1d { z31.q }, p7/z, [sp, #-1, mul vl]"
diff --git a/tests/MC/AArch64/SVE2p1/ld1h.s.yaml b/tests/MC/AArch64/SVE2p1/ld1h.s.yaml
new file mode 100644
index 000000000..0c1971565
--- /dev/null
+++ b/tests/MC/AArch64/SVE2p1/ld1h.s.yaml
@@ -0,0 +1,320 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x00, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h { z0.h, z1.h }, pn8/z, [x0, x0, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x54, 0x35, 0x15, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h { z20.h, z21.h }, pn13/z, [x10, x21, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0xb6, 0x2d, 0x08, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h { z22.h, z23.h }, pn11/z, [x13, x8, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0xfe, 0x3f, 0x1f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h { z30.h, z31.h }, pn15/z, [sp, xzr, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x40, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h { z0.h, z1.h }, pn8/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x54, 0x35, 0x45, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h { z20.h, z21.h }, pn13/z, [x10, #10, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xb6, 0x2d, 0x48, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h { z22.h, z23.h }, pn11/z, [x13, #-16, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xfe, 0x3f, 0x4f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h { z30.h, z31.h }, pn15/z, [sp, #-2, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x00, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h { z0.h - z3.h }, pn8/z, [x0, x0, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x54, 0xb5, 0x15, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h { z20.h - z23.h }, pn13/z, [x10, x21, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0xb4, 0xad, 0x08, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h { z20.h - z23.h }, pn11/z, [x13, x8, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0xfc, 0xbf, 0x1f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h { z28.h - z31.h }, pn15/z, [sp, xzr, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x40, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h { z0.h - z3.h }, pn8/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x54, 0xb5, 0x45, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h { z20.h - z23.h }, pn13/z, [x10, #20, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xb4, 0xad, 0x48, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h { z20.h - z23.h }, pn11/z, [x13, #-32, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xfc, 0xbf, 0x4f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h { z28.h - z31.h }, pn15/z, [sp, #-4, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x00, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h { z0.h, z1.h }, pn8/z, [x0, x0, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x54, 0x35, 0x15, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h { z20.h, z21.h }, pn13/z, [x10, x21, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0xb6, 0x2d, 0x08, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h { z22.h, z23.h }, pn11/z, [x13, x8, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0xfe, 0x3f, 0x1f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h { z30.h, z31.h }, pn15/z, [sp, xzr, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x40, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h { z0.h, z1.h }, pn8/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x54, 0x35, 0x45, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h { z20.h, z21.h }, pn13/z, [x10, #10, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xb6, 0x2d, 0x48, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h { z22.h, z23.h }, pn11/z, [x13, #-16, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xfe, 0x3f, 0x4f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h { z30.h, z31.h }, pn15/z, [sp, #-2, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x00, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h { z0.h - z3.h }, pn8/z, [x0, x0, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x54, 0xb5, 0x15, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h { z20.h - z23.h }, pn13/z, [x10, x21, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0xb4, 0xad, 0x08, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h { z20.h - z23.h }, pn11/z, [x13, x8, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0xfc, 0xbf, 0x1f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h { z28.h - z31.h }, pn15/z, [sp, xzr, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x40, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h { z0.h - z3.h }, pn8/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x54, 0xb5, 0x45, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h { z20.h - z23.h }, pn13/z, [x10, #20, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xb4, 0xad, 0x48, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h { z20.h - z23.h }, pn11/z, [x13, #-32, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xfc, 0xbf, 0x4f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1h { z28.h - z31.h }, pn15/z, [sp, #-4, mul vl]"
diff --git a/tests/MC/AArch64/SVE2p1/ld1q.s.yaml b/tests/MC/AArch64/SVE2p1/ld1q.s.yaml
new file mode 100644
index 000000000..de0f6e1cb
--- /dev/null
+++ b/tests/MC/AArch64/SVE2p1/ld1q.s.yaml
@@ -0,0 +1,40 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x00, 0xc4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1q { z0.q }, p0/z, [z0.d, x0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xb5, 0x15, 0xc4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1q { z21.q }, p5/z, [z10.d, x21]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xad, 0x08, 0xc4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1q { z23.q }, p3/z, [z13.d, x8]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbf, 0x1f, 0xc4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1q { z31.q }, p7/z, [z31.d]"
diff --git a/tests/MC/AArch64/SVE2p1/ld1w.s.yaml b/tests/MC/AArch64/SVE2p1/ld1w.s.yaml
new file mode 100644
index 000000000..dd4ad3faa
--- /dev/null
+++ b/tests/MC/AArch64/SVE2p1/ld1w.s.yaml
@@ -0,0 +1,320 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0x00, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w { z0.s, z1.s }, pn8/z, [x0, x0, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x54, 0x55, 0x15, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w { z20.s, z21.s }, pn13/z, [x10, x21, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0xb6, 0x4d, 0x08, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w { z22.s, z23.s }, pn11/z, [x13, x8, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0xfe, 0x5f, 0x1f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w { z30.s, z31.s }, pn15/z, [sp, xzr, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0x40, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w { z0.s, z1.s }, pn8/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x54, 0x55, 0x45, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w { z20.s, z21.s }, pn13/z, [x10, #10, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xb6, 0x4d, 0x48, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w { z22.s, z23.s }, pn11/z, [x13, #-16, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xfe, 0x5f, 0x4f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w { z30.s, z31.s }, pn15/z, [sp, #-2, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x00, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w { z0.s - z3.s }, pn8/z, [x0, x0, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x54, 0xd5, 0x15, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w { z20.s - z23.s }, pn13/z, [x10, x21, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0xb4, 0xcd, 0x08, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w { z20.s - z23.s }, pn11/z, [x13, x8, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0xfc, 0xdf, 0x1f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w { z28.s - z31.s }, pn15/z, [sp, xzr, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x40, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w { z0.s - z3.s }, pn8/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x54, 0xd5, 0x45, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w { z20.s - z23.s }, pn13/z, [x10, #20, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xb4, 0xcd, 0x48, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w { z20.s - z23.s }, pn11/z, [x13, #-32, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xfc, 0xdf, 0x4f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w { z28.s - z31.s }, pn15/z, [sp, #-4, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0x00, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w { z0.s, z1.s }, pn8/z, [x0, x0, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x54, 0x55, 0x15, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w { z20.s, z21.s }, pn13/z, [x10, x21, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0xb6, 0x4d, 0x08, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w { z22.s, z23.s }, pn11/z, [x13, x8, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0xfe, 0x5f, 0x1f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w { z30.s, z31.s }, pn15/z, [sp, xzr, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0x40, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w { z0.s, z1.s }, pn8/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x54, 0x55, 0x45, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w { z20.s, z21.s }, pn13/z, [x10, #10, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xb6, 0x4d, 0x48, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w { z22.s, z23.s }, pn11/z, [x13, #-16, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xfe, 0x5f, 0x4f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w { z30.s, z31.s }, pn15/z, [sp, #-2, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x00, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w { z0.s - z3.s }, pn8/z, [x0, x0, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x54, 0xd5, 0x15, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w { z20.s - z23.s }, pn13/z, [x10, x21, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0xb4, 0xcd, 0x08, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w { z20.s - z23.s }, pn11/z, [x13, x8, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0xfc, 0xdf, 0x1f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w { z28.s - z31.s }, pn15/z, [sp, xzr, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x40, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w { z0.s - z3.s }, pn8/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x54, 0xd5, 0x45, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w { z20.s - z23.s }, pn13/z, [x10, #20, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xb4, 0xcd, 0x48, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w { z20.s - z23.s }, pn11/z, [x13, #-32, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xfc, 0xdf, 0x4f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w { z28.s - z31.s }, pn15/z, [sp, #-4, mul vl]"
diff --git a/tests/MC/AArch64/SVE2p1/ld1w_q.s.yaml b/tests/MC/AArch64/SVE2p1/ld1w_q.s.yaml
new file mode 100644
index 000000000..c93d49259
--- /dev/null
+++ b/tests/MC/AArch64/SVE2p1/ld1w_q.s.yaml
@@ -0,0 +1,80 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x00, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w { z0.q }, p0/z, [x0, x0, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x95, 0x15, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w { z21.q }, p5/z, [x10, x21, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x8d, 0x08, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w { z23.q }, p3/z, [x13, x8, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x8d, 0x08, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w { z23.q }, p3/z, [x13, x8, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x10, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w { z0.q }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x35, 0x15, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w { z21.q }, p5/z, [x10, #5, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x2d, 0x18, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w { z23.q }, p3/z, [x13, #-8, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0x1f, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1w { z31.q }, p7/z, [sp, #-1, mul vl]"
diff --git a/tests/MC/AArch64/SVE2p1/ld2q.s.yaml b/tests/MC/AArch64/SVE2p1/ld2q.s.yaml
new file mode 100644
index 000000000..0b387bbd5
--- /dev/null
+++ b/tests/MC/AArch64/SVE2p1/ld2q.s.yaml
@@ -0,0 +1,140 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xa0, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld2q { z0.q, z1.q }, p0/z, [x0, x0, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x95, 0xb5, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld2q { z21.q, z22.q }, p5/z, [x10, x21, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x8d, 0xa8, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld2q { z23.q, z24.q }, p3/z, [x13, x8, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x90, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld2q { z0.q, z1.q }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf5, 0x95, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld2q { z21.q, z22.q }, p5/z, [x10, #10, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0x98, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld2q { z23.q, z24.q }, p3/z, [x13, #-16, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0x9f, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld2q { z31.q, z0.q }, p7/z, [sp, #-2, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xa0, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld2q { z0.q, z1.q }, p0/z, [x0, x0, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x95, 0xb5, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld2q { z21.q, z22.q }, p5/z, [x10, x21, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x8d, 0xa8, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld2q { z23.q, z24.q }, p3/z, [x13, x8, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x90, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld2q { z0.q, z1.q }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf5, 0x95, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld2q { z21.q, z22.q }, p5/z, [x10, #10, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0x98, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld2q { z23.q, z24.q }, p3/z, [x13, #-16, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0x9f, 0xa4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld2q { z31.q, z0.q }, p7/z, [sp, #-2, mul vl]"
diff --git a/tests/MC/AArch64/SVE2p1/ld3q.s.yaml b/tests/MC/AArch64/SVE2p1/ld3q.s.yaml
new file mode 100644
index 000000000..0657f697d
--- /dev/null
+++ b/tests/MC/AArch64/SVE2p1/ld3q.s.yaml
@@ -0,0 +1,140 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x20, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld3q { z0.q - z2.q }, p0/z, [x0, x0, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x95, 0x35, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld3q { z21.q - z23.q }, p5/z, [x10, x21, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x8d, 0x28, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld3q { z23.q - z25.q }, p3/z, [x13, x8, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x10, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld3q { z0.q - z2.q }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf5, 0x15, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld3q { z21.q - z23.q }, p5/z, [x10, #15, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0x18, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld3q { z23.q - z25.q }, p3/z, [x13, #-24, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0x1f, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld3q { z31.q, z0.q, z1.q }, p7/z, [sp, #-3, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x20, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld3q { z0.q - z2.q }, p0/z, [x0, x0, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x95, 0x35, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld3q { z21.q - z23.q }, p5/z, [x10, x21, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x8d, 0x28, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld3q { z23.q - z25.q }, p3/z, [x13, x8, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x10, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld3q { z0.q - z2.q }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf5, 0x15, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld3q { z21.q - z23.q }, p5/z, [x10, #15, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0x18, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld3q { z23.q - z25.q }, p3/z, [x13, #-24, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0x1f, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld3q { z31.q, z0.q, z1.q }, p7/z, [sp, #-3, mul vl]"
diff --git a/tests/MC/AArch64/SVE2p1/ld4q.s.yaml b/tests/MC/AArch64/SVE2p1/ld4q.s.yaml
new file mode 100644
index 000000000..5b6eac037
--- /dev/null
+++ b/tests/MC/AArch64/SVE2p1/ld4q.s.yaml
@@ -0,0 +1,140 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xa0, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld4q { z0.q - z3.q }, p0/z, [x0, x0, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x95, 0xb5, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld4q { z21.q - z24.q }, p5/z, [x10, x21, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x8d, 0xa8, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld4q { z23.q - z26.q }, p3/z, [x13, x8, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x90, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld4q { z0.q - z3.q }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf5, 0x95, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld4q { z21.q - z24.q }, p5/z, [x10, #20, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0x98, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld4q { z23.q - z26.q }, p3/z, [x13, #-32, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0x9f, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld4q { z31.q, z0.q, z1.q, z2.q }, p7/z, [sp, #-4, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xa0, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld4q { z0.q - z3.q }, p0/z, [x0, x0, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x95, 0xb5, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld4q { z21.q - z24.q }, p5/z, [x10, x21, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x8d, 0xa8, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld4q { z23.q - z26.q }, p3/z, [x13, x8, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x90, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld4q { z0.q - z3.q }, p0/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf5, 0x95, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld4q { z21.q - z24.q }, p5/z, [x10, #20, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0x98, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld4q { z23.q - z26.q }, p3/z, [x13, #-32, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0x9f, 0xa5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld4q { z31.q, z0.q, z1.q, z2.q }, p7/z, [sp, #-4, mul vl]"
diff --git a/tests/MC/AArch64/SVE2p1/ldnt1b.s.yaml b/tests/MC/AArch64/SVE2p1/ldnt1b.s.yaml
new file mode 100644
index 000000000..e135d5f19
--- /dev/null
+++ b/tests/MC/AArch64/SVE2p1/ldnt1b.s.yaml
@@ -0,0 +1,320 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0x00, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1b { z0.b, z1.b }, pn8/z, [x0, x0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x15, 0x15, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1b { z20.b, z21.b }, pn13/z, [x10, x21]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x0d, 0x08, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1b { z22.b, z23.b }, pn11/z, [x13, x8]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0x1f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1b { z30.b, z31.b }, pn15/z, [sp, xzr]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0x40, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1b { z0.b, z1.b }, pn8/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x15, 0x45, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1b { z20.b, z21.b }, pn13/z, [x10, #10, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x0d, 0x48, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1b { z22.b, z23.b }, pn11/z, [x13, #-16, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0x4f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1b { z30.b, z31.b }, pn15/z, [sp, #-2, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x80, 0x00, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1b { z0.b - z3.b }, pn8/z, [x0, x0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x95, 0x15, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1b { z20.b - z23.b }, pn13/z, [x10, x21]"
+
+  -
+    input:
+      bytes: [ 0xb5, 0x8d, 0x08, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1b { z20.b - z23.b }, pn11/z, [x13, x8]"
+
+  -
+    input:
+      bytes: [ 0xfd, 0x9f, 0x1f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1b { z28.b - z31.b }, pn15/z, [sp, xzr]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x80, 0x40, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1b { z0.b - z3.b }, pn8/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x95, 0x45, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1b { z20.b - z23.b }, pn13/z, [x10, #20, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xb5, 0x8d, 0x48, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1b { z20.b - z23.b }, pn11/z, [x13, #-32, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xfd, 0x9f, 0x4f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1b { z28.b - z31.b }, pn15/z, [sp, #-4, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0x00, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1b { z0.b, z1.b }, pn8/z, [x0, x0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x15, 0x15, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1b { z20.b, z21.b }, pn13/z, [x10, x21]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x0d, 0x08, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1b { z22.b, z23.b }, pn11/z, [x13, x8]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0x1f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1b { z30.b, z31.b }, pn15/z, [sp, xzr]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0x40, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1b { z0.b, z1.b }, pn8/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x15, 0x45, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1b { z20.b, z21.b }, pn13/z, [x10, #10, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x0d, 0x48, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1b { z22.b, z23.b }, pn11/z, [x13, #-16, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0x4f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1b { z30.b, z31.b }, pn15/z, [sp, #-2, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x80, 0x00, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1b { z0.b - z3.b }, pn8/z, [x0, x0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x95, 0x15, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1b { z20.b - z23.b }, pn13/z, [x10, x21]"
+
+  -
+    input:
+      bytes: [ 0xb5, 0x8d, 0x08, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1b { z20.b - z23.b }, pn11/z, [x13, x8]"
+
+  -
+    input:
+      bytes: [ 0xfd, 0x9f, 0x1f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1b { z28.b - z31.b }, pn15/z, [sp, xzr]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x80, 0x40, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1b { z0.b - z3.b }, pn8/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x95, 0x45, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1b { z20.b - z23.b }, pn13/z, [x10, #20, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xb5, 0x8d, 0x48, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1b { z20.b - z23.b }, pn11/z, [x13, #-32, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xfd, 0x9f, 0x4f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1b { z28.b - z31.b }, pn15/z, [sp, #-4, mul vl]"
diff --git a/tests/MC/AArch64/SVE2p1/ldnt1d.s.yaml b/tests/MC/AArch64/SVE2p1/ldnt1d.s.yaml
new file mode 100644
index 000000000..774115116
--- /dev/null
+++ b/tests/MC/AArch64/SVE2p1/ldnt1d.s.yaml
@@ -0,0 +1,320 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x01, 0x60, 0x00, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1d { z0.d, z1.d }, pn8/z, [x0, x0, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x75, 0x15, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1d { z20.d, z21.d }, pn13/z, [x10, x21, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x6d, 0x08, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1d { z22.d, z23.d }, pn11/z, [x13, x8, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x7f, 0x1f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1d { z30.d, z31.d }, pn15/z, [sp, xzr, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x60, 0x40, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1d { z0.d, z1.d }, pn8/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x75, 0x45, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1d { z20.d, z21.d }, pn13/z, [x10, #10, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x6d, 0x48, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1d { z22.d, z23.d }, pn11/z, [x13, #-16, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x7f, 0x4f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1d { z30.d, z31.d }, pn15/z, [sp, #-2, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x01, 0xe0, 0x00, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1d { z0.d - z3.d }, pn8/z, [x0, x0, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf5, 0x15, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1d { z20.d - z23.d }, pn13/z, [x10, x21, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0xb5, 0xed, 0x08, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1d { z20.d - z23.d }, pn11/z, [x13, x8, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0xfd, 0xff, 0x1f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1d { z28.d - z31.d }, pn15/z, [sp, xzr, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x01, 0xe0, 0x40, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1d { z0.d - z3.d }, pn8/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf5, 0x45, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1d { z20.d - z23.d }, pn13/z, [x10, #20, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xb5, 0xed, 0x48, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1d { z20.d - z23.d }, pn11/z, [x13, #-32, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xfd, 0xff, 0x4f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1d { z28.d - z31.d }, pn15/z, [sp, #-4, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x60, 0x00, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1d { z0.d, z1.d }, pn8/z, [x0, x0, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x75, 0x15, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1d { z20.d, z21.d }, pn13/z, [x10, x21, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x6d, 0x08, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1d { z22.d, z23.d }, pn11/z, [x13, x8, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x7f, 0x1f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1d { z30.d, z31.d }, pn15/z, [sp, xzr, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x60, 0x40, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1d { z0.d, z1.d }, pn8/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x75, 0x45, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1d { z20.d, z21.d }, pn13/z, [x10, #10, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x6d, 0x48, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1d { z22.d, z23.d }, pn11/z, [x13, #-16, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x7f, 0x4f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1d { z30.d, z31.d }, pn15/z, [sp, #-2, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x01, 0xe0, 0x00, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1d { z0.d - z3.d }, pn8/z, [x0, x0, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf5, 0x15, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1d { z20.d - z23.d }, pn13/z, [x10, x21, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0xb5, 0xed, 0x08, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1d { z20.d - z23.d }, pn11/z, [x13, x8, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0xfd, 0xff, 0x1f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1d { z28.d - z31.d }, pn15/z, [sp, xzr, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x01, 0xe0, 0x40, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1d { z0.d - z3.d }, pn8/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf5, 0x45, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1d { z20.d - z23.d }, pn13/z, [x10, #20, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xb5, 0xed, 0x48, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1d { z20.d - z23.d }, pn11/z, [x13, #-32, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xfd, 0xff, 0x4f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1d { z28.d - z31.d }, pn15/z, [sp, #-4, mul vl]"
diff --git a/tests/MC/AArch64/SVE2p1/ldnt1h.s.yaml b/tests/MC/AArch64/SVE2p1/ldnt1h.s.yaml
new file mode 100644
index 000000000..0329153e9
--- /dev/null
+++ b/tests/MC/AArch64/SVE2p1/ldnt1h.s.yaml
@@ -0,0 +1,320 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x01, 0x20, 0x00, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1h { z0.h, z1.h }, pn8/z, [x0, x0, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x35, 0x15, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1h { z20.h, z21.h }, pn13/z, [x10, x21, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x2d, 0x08, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1h { z22.h, z23.h }, pn11/z, [x13, x8, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0x1f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1h { z30.h, z31.h }, pn15/z, [sp, xzr, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x20, 0x40, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1h { z0.h, z1.h }, pn8/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x35, 0x45, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1h { z20.h, z21.h }, pn13/z, [x10, #10, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x2d, 0x48, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1h { z22.h, z23.h }, pn11/z, [x13, #-16, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0x4f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1h { z30.h, z31.h }, pn15/z, [sp, #-2, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x01, 0xa0, 0x00, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1h { z0.h - z3.h }, pn8/z, [x0, x0, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xb5, 0x15, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1h { z20.h - z23.h }, pn13/z, [x10, x21, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0xb5, 0xad, 0x08, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1h { z20.h - z23.h }, pn11/z, [x13, x8, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0xfd, 0xbf, 0x1f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1h { z28.h - z31.h }, pn15/z, [sp, xzr, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x01, 0xa0, 0x40, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1h { z0.h - z3.h }, pn8/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xb5, 0x45, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1h { z20.h - z23.h }, pn13/z, [x10, #20, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xb5, 0xad, 0x48, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1h { z20.h - z23.h }, pn11/z, [x13, #-32, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xfd, 0xbf, 0x4f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1h { z28.h - z31.h }, pn15/z, [sp, #-4, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x20, 0x00, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1h { z0.h, z1.h }, pn8/z, [x0, x0, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x35, 0x15, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1h { z20.h, z21.h }, pn13/z, [x10, x21, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x2d, 0x08, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1h { z22.h, z23.h }, pn11/z, [x13, x8, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0x1f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1h { z30.h, z31.h }, pn15/z, [sp, xzr, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x20, 0x40, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1h { z0.h, z1.h }, pn8/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x35, 0x45, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1h { z20.h, z21.h }, pn13/z, [x10, #10, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x2d, 0x48, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1h { z22.h, z23.h }, pn11/z, [x13, #-16, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0x4f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1h { z30.h, z31.h }, pn15/z, [sp, #-2, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x01, 0xa0, 0x00, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1h { z0.h - z3.h }, pn8/z, [x0, x0, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xb5, 0x15, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1h { z20.h - z23.h }, pn13/z, [x10, x21, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0xb5, 0xad, 0x08, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1h { z20.h - z23.h }, pn11/z, [x13, x8, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0xfd, 0xbf, 0x1f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1h { z28.h - z31.h }, pn15/z, [sp, xzr, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x01, 0xa0, 0x40, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1h { z0.h - z3.h }, pn8/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xb5, 0x45, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1h { z20.h - z23.h }, pn13/z, [x10, #20, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xb5, 0xad, 0x48, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1h { z20.h - z23.h }, pn11/z, [x13, #-32, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xfd, 0xbf, 0x4f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1h { z28.h - z31.h }, pn15/z, [sp, #-4, mul vl]"
diff --git a/tests/MC/AArch64/SVE2p1/ldnt1w.s.yaml b/tests/MC/AArch64/SVE2p1/ldnt1w.s.yaml
new file mode 100644
index 000000000..d0b6e3bb2
--- /dev/null
+++ b/tests/MC/AArch64/SVE2p1/ldnt1w.s.yaml
@@ -0,0 +1,320 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x01, 0x40, 0x00, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1w { z0.s, z1.s }, pn8/z, [x0, x0, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x55, 0x15, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1w { z20.s, z21.s }, pn13/z, [x10, x21, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x4d, 0x08, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1w { z22.s, z23.s }, pn11/z, [x13, x8, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x5f, 0x1f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1w { z30.s, z31.s }, pn15/z, [sp, xzr, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x40, 0x40, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1w { z0.s, z1.s }, pn8/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x55, 0x45, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1w { z20.s, z21.s }, pn13/z, [x10, #10, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x4d, 0x48, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1w { z22.s, z23.s }, pn11/z, [x13, #-16, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x5f, 0x4f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1w { z30.s, z31.s }, pn15/z, [sp, #-2, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x01, 0xc0, 0x00, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1w { z0.s - z3.s }, pn8/z, [x0, x0, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xd5, 0x15, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1w { z20.s - z23.s }, pn13/z, [x10, x21, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0xb5, 0xcd, 0x08, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1w { z20.s - z23.s }, pn11/z, [x13, x8, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0xfd, 0xdf, 0x1f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1w { z28.s - z31.s }, pn15/z, [sp, xzr, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x01, 0xc0, 0x40, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1w { z0.s - z3.s }, pn8/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xd5, 0x45, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1w { z20.s - z23.s }, pn13/z, [x10, #20, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xb5, 0xcd, 0x48, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1w { z20.s - z23.s }, pn11/z, [x13, #-32, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xfd, 0xdf, 0x4f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1w { z28.s - z31.s }, pn15/z, [sp, #-4, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x40, 0x00, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1w { z0.s, z1.s }, pn8/z, [x0, x0, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x55, 0x15, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1w { z20.s, z21.s }, pn13/z, [x10, x21, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x4d, 0x08, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1w { z22.s, z23.s }, pn11/z, [x13, x8, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x5f, 0x1f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1w { z30.s, z31.s }, pn15/z, [sp, xzr, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x40, 0x40, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1w { z0.s, z1.s }, pn8/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x55, 0x45, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1w { z20.s, z21.s }, pn13/z, [x10, #10, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x4d, 0x48, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1w { z22.s, z23.s }, pn11/z, [x13, #-16, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x5f, 0x4f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1w { z30.s, z31.s }, pn15/z, [sp, #-2, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x01, 0xc0, 0x00, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1w { z0.s - z3.s }, pn8/z, [x0, x0, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xd5, 0x15, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1w { z20.s - z23.s }, pn13/z, [x10, x21, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0xb5, 0xcd, 0x08, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1w { z20.s - z23.s }, pn11/z, [x13, x8, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0xfd, 0xdf, 0x1f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1w { z28.s - z31.s }, pn15/z, [sp, xzr, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x01, 0xc0, 0x40, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1w { z0.s - z3.s }, pn8/z, [x0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xd5, 0x45, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1w { z20.s - z23.s }, pn13/z, [x10, #20, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xb5, 0xcd, 0x48, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1w { z20.s - z23.s }, pn11/z, [x13, #-32, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xfd, 0xdf, 0x4f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnt1w { z28.s - z31.s }, pn15/z, [sp, #-4, mul vl]"
diff --git a/tests/MC/AArch64/SVE2p1/orqv.s.yaml b/tests/MC/AArch64/SVE2p1/orqv.s.yaml
new file mode 100644
index 000000000..221cdaf52
--- /dev/null
+++ b/tests/MC/AArch64/SVE2p1/orqv.s.yaml
@@ -0,0 +1,320 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x5c, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "orqv v0.8h, p0, z0.h"
+
+  -
+    input:
+      bytes: [ 0x55, 0x35, 0x5c, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "orqv v21.8h, p5, z10.h"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x2d, 0x5c, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "orqv v23.8h, p3, z13.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0x5c, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "orqv v31.8h, p7, z31.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x9c, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "orqv v0.4s, p0, z0.s"
+
+  -
+    input:
+      bytes: [ 0x55, 0x35, 0x9c, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "orqv v21.4s, p5, z10.s"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x2d, 0x9c, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "orqv v23.4s, p3, z13.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0x9c, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "orqv v31.4s, p7, z31.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0xdc, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "orqv v0.2d, p0, z0.d"
+
+  -
+    input:
+      bytes: [ 0x55, 0x35, 0xdc, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "orqv v21.2d, p5, z10.d"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x2d, 0xdc, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "orqv v23.2d, p3, z13.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0xdc, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "orqv v31.2d, p7, z31.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x1c, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "orqv v0.16b, p0, z0.b"
+
+  -
+    input:
+      bytes: [ 0x55, 0x35, 0x1c, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "orqv v21.16b, p5, z10.b"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x2d, 0x1c, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "orqv v23.16b, p3, z13.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0x1c, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "orqv v31.16b, p7, z31.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x5c, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "orqv v0.8h, p0, z0.h"
+
+  -
+    input:
+      bytes: [ 0x55, 0x35, 0x5c, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "orqv v21.8h, p5, z10.h"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x2d, 0x5c, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "orqv v23.8h, p3, z13.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0x5c, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "orqv v31.8h, p7, z31.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x9c, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "orqv v0.4s, p0, z0.s"
+
+  -
+    input:
+      bytes: [ 0x55, 0x35, 0x9c, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "orqv v21.4s, p5, z10.s"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x2d, 0x9c, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "orqv v23.4s, p3, z13.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0x9c, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "orqv v31.4s, p7, z31.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0xdc, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "orqv v0.2d, p0, z0.d"
+
+  -
+    input:
+      bytes: [ 0x55, 0x35, 0xdc, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "orqv v21.2d, p5, z10.d"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x2d, 0xdc, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "orqv v23.2d, p3, z13.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0xdc, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "orqv v31.2d, p7, z31.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x1c, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "orqv v0.16b, p0, z0.b"
+
+  -
+    input:
+      bytes: [ 0x55, 0x35, 0x1c, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "orqv v21.16b, p5, z10.b"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x2d, 0x1c, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "orqv v23.16b, p3, z13.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0x1c, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "orqv v31.16b, p7, z31.b"
diff --git a/tests/MC/AArch64/SVE2p1/pext.s.yaml b/tests/MC/AArch64/SVE2p1/pext.s.yaml
new file mode 100644
index 000000000..96e61a928
--- /dev/null
+++ b/tests/MC/AArch64/SVE2p1/pext.s.yaml
@@ -0,0 +1,600 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x10, 0x70, 0x60, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "pext p0.h, pn8[0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x71, 0x60, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "pext p5.h, pn10[1]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x71, 0x60, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "pext p7.h, pn13[1]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x73, 0x60, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "pext p15.h, pn15[3]"
+
+  -
+    input:
+      bytes: [ 0x10, 0x70, 0xa0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "pext p0.s, pn8[0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x71, 0xa0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "pext p5.s, pn10[1]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x71, 0xa0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "pext p7.s, pn13[1]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x73, 0xa0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "pext p15.s, pn15[3]"
+
+  -
+    input:
+      bytes: [ 0x10, 0x70, 0xe0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "pext p0.d, pn8[0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x71, 0xe0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "pext p5.d, pn10[1]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x71, 0xe0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "pext p7.d, pn13[1]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x73, 0xe0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "pext p15.d, pn15[3]"
+
+  -
+    input:
+      bytes: [ 0x10, 0x70, 0x20, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "pext p0.b, pn8[0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x71, 0x20, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "pext p5.b, pn10[1]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x71, 0x20, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "pext p7.b, pn13[1]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x73, 0x20, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "pext p15.b, pn15[3]"
+
+  -
+    input:
+      bytes: [ 0x10, 0x74, 0x60, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "pext { p0.h, p1.h }, pn8[0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x75, 0x60, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "pext { p5.h, p6.h }, pn10[1]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x75, 0x60, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "pext { p7.h, p8.h }, pn13[1]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x75, 0x60, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "pext { p15.h, p0.h }, pn15[1]"
+
+  -
+    input:
+      bytes: [ 0x10, 0x74, 0xa0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "pext { p0.s, p1.s }, pn8[0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x75, 0xa0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "pext { p5.s, p6.s }, pn10[1]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x75, 0xa0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "pext { p7.s, p8.s }, pn13[1]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x75, 0xa0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "pext { p15.s, p0.s }, pn15[1]"
+
+  -
+    input:
+      bytes: [ 0x10, 0x74, 0xe0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "pext { p0.d, p1.d }, pn8[0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x75, 0xe0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "pext { p5.d, p6.d }, pn10[1]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x75, 0xe0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "pext { p7.d, p8.d }, pn13[1]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x75, 0xe0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "pext { p15.d, p0.d }, pn15[1]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x75, 0x20, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "pext { p7.b, p8.b }, pn13[1]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x75, 0x20, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "pext { p15.b, p0.b }, pn15[1]"
+
+  -
+    input:
+      bytes: [ 0x10, 0x70, 0x60, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "pext p0.h, pn8[0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x71, 0x60, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "pext p5.h, pn10[1]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x71, 0x60, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "pext p7.h, pn13[1]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x73, 0x60, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "pext p15.h, pn15[3]"
+
+  -
+    input:
+      bytes: [ 0x10, 0x70, 0xa0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "pext p0.s, pn8[0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x71, 0xa0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "pext p5.s, pn10[1]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x71, 0xa0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "pext p7.s, pn13[1]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x73, 0xa0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "pext p15.s, pn15[3]"
+
+  -
+    input:
+      bytes: [ 0x10, 0x70, 0xe0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "pext p0.d, pn8[0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x71, 0xe0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "pext p5.d, pn10[1]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x71, 0xe0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "pext p7.d, pn13[1]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x73, 0xe0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "pext p15.d, pn15[3]"
+
+  -
+    input:
+      bytes: [ 0x10, 0x70, 0x20, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "pext p0.b, pn8[0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x71, 0x20, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "pext p5.b, pn10[1]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x71, 0x20, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "pext p7.b, pn13[1]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x73, 0x20, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "pext p15.b, pn15[3]"
+
+  -
+    input:
+      bytes: [ 0x10, 0x74, 0x60, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "pext { p0.h, p1.h }, pn8[0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x75, 0x60, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "pext { p5.h, p6.h }, pn10[1]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x75, 0x60, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "pext { p7.h, p8.h }, pn13[1]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x75, 0x60, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "pext { p15.h, p0.h }, pn15[1]"
+
+  -
+    input:
+      bytes: [ 0x10, 0x74, 0xa0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "pext { p0.s, p1.s }, pn8[0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x75, 0xa0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "pext { p5.s, p6.s }, pn10[1]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x75, 0xa0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "pext { p7.s, p8.s }, pn13[1]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x75, 0xa0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "pext { p15.s, p0.s }, pn15[1]"
+
+  -
+    input:
+      bytes: [ 0x10, 0x74, 0xe0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "pext { p0.d, p1.d }, pn8[0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x75, 0xe0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "pext { p5.d, p6.d }, pn10[1]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x75, 0xe0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "pext { p7.d, p8.d }, pn13[1]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x75, 0xe0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "pext { p15.d, p0.d }, pn15[1]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x75, 0x20, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "pext { p7.b, p8.b }, pn13[1]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x75, 0x20, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "pext { p15.b, p0.b }, pn15[1]"
diff --git a/tests/MC/AArch64/SVE2p1/pmov.s.yaml b/tests/MC/AArch64/SVE2p1/pmov.s.yaml
new file mode 100644
index 000000000..69c9919d4
--- /dev/null
+++ b/tests/MC/AArch64/SVE2p1/pmov.s.yaml
@@ -0,0 +1,800 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x38, 0x2c, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "pmov p0.h, z0[0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x38, 0x2c, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "pmov p0.h, z0[0]"
+
+  -
+    input:
+      bytes: [ 0x45, 0x39, 0x2c, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "pmov p5.h, z10[0]"
+
+  -
+    input:
+      bytes: [ 0xa7, 0x39, 0x2c, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "pmov p7.h, z13[0]"
+
+  -
+    input:
+      bytes: [ 0xef, 0x3b, 0x2e, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "pmov p15.h, z31[1]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x38, 0x68, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "pmov p0.s, z0[0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x38, 0x68, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "pmov p0.s, z0[0]"
+
+  -
+    input:
+      bytes: [ 0x45, 0x39, 0x6c, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "pmov p5.s, z10[2]"
+
+  -
+    input:
+      bytes: [ 0xa7, 0x39, 0x68, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "pmov p7.s, z13[0]"
+
+  -
+    input:
+      bytes: [ 0xef, 0x3b, 0x6e, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "pmov p15.s, z31[3]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x38, 0xa8, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "pmov p0.d, z0[0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x38, 0xa8, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "pmov p0.d, z0[0]"
+
+  -
+    input:
+      bytes: [ 0x45, 0x39, 0xec, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "pmov p5.d, z10[6]"
+
+  -
+    input:
+      bytes: [ 0xa7, 0x39, 0xe8, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "pmov p7.d, z13[4]"
+
+  -
+    input:
+      bytes: [ 0xef, 0x3b, 0xee, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "pmov p15.d, z31[7]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x38, 0x2a, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "pmov p0.b, z0"
+
+  -
+    input:
+      bytes: [ 0x45, 0x39, 0x2a, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "pmov p5.b, z10"
+
+  -
+    input:
+      bytes: [ 0xa7, 0x39, 0x2a, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "pmov p7.b, z13"
+
+  -
+    input:
+      bytes: [ 0xef, 0x3b, 0x2a, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "pmov p15.b, z31"
+
+  -
+    input:
+      bytes: [ 0x00, 0x38, 0x2a, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "pmov p0.b, z0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x38, 0x2d, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "pmov z0[0], p0.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x38, 0x2d, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "pmov z0[0], p0.h"
+
+  -
+    input:
+      bytes: [ 0x55, 0x39, 0x2d, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "pmov z21[0], p10.h"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x39, 0x2d, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "pmov z23[0], p13.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x39, 0x2f, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "pmov z31[1], p15.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x38, 0x69, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "pmov z0[0], p0.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0x38, 0x69, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "pmov z0[0], p0.s"
+
+  -
+    input:
+      bytes: [ 0x55, 0x39, 0x6d, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "pmov z21[2], p10.s"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x39, 0x69, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "pmov z23[0], p13.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0x39, 0x6f, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "pmov z31[3], p15.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0x38, 0xa9, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "pmov z0[0], p0.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x38, 0xa9, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "pmov z0[0], p0.d"
+
+  -
+    input:
+      bytes: [ 0x55, 0x39, 0xed, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "pmov z21[6], p10.d"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x39, 0xe9, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "pmov z23[4], p13.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0x39, 0xef, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "pmov z31[7], p15.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x38, 0x2b, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "pmov z0, p0.b"
+
+  -
+    input:
+      bytes: [ 0x55, 0x39, 0x2b, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "pmov z21, p10.b"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x39, 0x2b, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "pmov z23, p13.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x39, 0x2b, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "pmov z31, p15.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x38, 0x2b, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "pmov z0, p0.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x38, 0x2c, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "pmov p0.h, z0[0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x38, 0x2c, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "pmov p0.h, z0[0]"
+
+  -
+    input:
+      bytes: [ 0x45, 0x39, 0x2c, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "pmov p5.h, z10[0]"
+
+  -
+    input:
+      bytes: [ 0xa7, 0x39, 0x2c, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "pmov p7.h, z13[0]"
+
+  -
+    input:
+      bytes: [ 0xef, 0x3b, 0x2e, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "pmov p15.h, z31[1]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x38, 0x68, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "pmov p0.s, z0[0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x38, 0x68, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "pmov p0.s, z0[0]"
+
+  -
+    input:
+      bytes: [ 0x45, 0x39, 0x6c, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "pmov p5.s, z10[2]"
+
+  -
+    input:
+      bytes: [ 0xa7, 0x39, 0x68, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "pmov p7.s, z13[0]"
+
+  -
+    input:
+      bytes: [ 0xef, 0x3b, 0x6e, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "pmov p15.s, z31[3]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x38, 0xa8, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "pmov p0.d, z0[0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x38, 0xa8, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "pmov p0.d, z0[0]"
+
+  -
+    input:
+      bytes: [ 0x45, 0x39, 0xec, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "pmov p5.d, z10[6]"
+
+  -
+    input:
+      bytes: [ 0xa7, 0x39, 0xe8, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "pmov p7.d, z13[4]"
+
+  -
+    input:
+      bytes: [ 0xef, 0x3b, 0xee, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "pmov p15.d, z31[7]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x38, 0x2a, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "pmov p0.b, z0"
+
+  -
+    input:
+      bytes: [ 0x45, 0x39, 0x2a, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "pmov p5.b, z10"
+
+  -
+    input:
+      bytes: [ 0xa7, 0x39, 0x2a, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "pmov p7.b, z13"
+
+  -
+    input:
+      bytes: [ 0xef, 0x3b, 0x2a, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "pmov p15.b, z31"
+
+  -
+    input:
+      bytes: [ 0x00, 0x38, 0x2a, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "pmov p0.b, z0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x38, 0x2d, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "pmov z0[0], p0.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x38, 0x2d, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "pmov z0[0], p0.h"
+
+  -
+    input:
+      bytes: [ 0x55, 0x39, 0x2d, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "pmov z21[0], p10.h"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x39, 0x2d, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "pmov z23[0], p13.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x39, 0x2f, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "pmov z31[1], p15.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x38, 0x69, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "pmov z0[0], p0.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0x38, 0x69, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "pmov z0[0], p0.s"
+
+  -
+    input:
+      bytes: [ 0x55, 0x39, 0x6d, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "pmov z21[2], p10.s"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x39, 0x69, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "pmov z23[0], p13.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0x39, 0x6f, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "pmov z31[3], p15.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0x38, 0xa9, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "pmov z0[0], p0.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x38, 0xa9, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "pmov z0[0], p0.d"
+
+  -
+    input:
+      bytes: [ 0x55, 0x39, 0xed, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "pmov z21[6], p10.d"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x39, 0xe9, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "pmov z23[4], p13.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0x39, 0xef, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "pmov z31[7], p15.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x38, 0x2b, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "pmov z0, p0.b"
+
+  -
+    input:
+      bytes: [ 0x55, 0x39, 0x2b, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "pmov z21, p10.b"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x39, 0x2b, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "pmov z23, p13.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x39, 0x2b, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "pmov z31, p15.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x38, 0x2b, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "pmov z0, p0.b"
diff --git a/tests/MC/AArch64/SVE2p1/ptrue.s.yaml b/tests/MC/AArch64/SVE2p1/ptrue.s.yaml
new file mode 100644
index 000000000..9b3ca34d6
--- /dev/null
+++ b/tests/MC/AArch64/SVE2p1/ptrue.s.yaml
@@ -0,0 +1,320 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x10, 0x78, 0x60, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrue pn8.h"
+
+  -
+    input:
+      bytes: [ 0x15, 0x78, 0x60, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrue pn13.h"
+
+  -
+    input:
+      bytes: [ 0x17, 0x78, 0x60, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrue pn15.h"
+
+  -
+    input:
+      bytes: [ 0x11, 0x78, 0x60, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrue pn9.h"
+
+  -
+    input:
+      bytes: [ 0x10, 0x78, 0xa0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrue pn8.s"
+
+  -
+    input:
+      bytes: [ 0x15, 0x78, 0xa0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrue pn13.s"
+
+  -
+    input:
+      bytes: [ 0x17, 0x78, 0xa0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrue pn15.s"
+
+  -
+    input:
+      bytes: [ 0x11, 0x78, 0xa0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrue pn9.s"
+
+  -
+    input:
+      bytes: [ 0x10, 0x78, 0xe0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrue pn8.d"
+
+  -
+    input:
+      bytes: [ 0x15, 0x78, 0xe0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrue pn13.d"
+
+  -
+    input:
+      bytes: [ 0x17, 0x78, 0xe0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrue pn15.d"
+
+  -
+    input:
+      bytes: [ 0x11, 0x78, 0xe0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrue pn9.d"
+
+  -
+    input:
+      bytes: [ 0x10, 0x78, 0x20, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrue pn8.b"
+
+  -
+    input:
+      bytes: [ 0x15, 0x78, 0x20, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrue pn13.b"
+
+  -
+    input:
+      bytes: [ 0x17, 0x78, 0x20, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrue pn15.b"
+
+  -
+    input:
+      bytes: [ 0x11, 0x78, 0x20, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrue pn9.b"
+
+  -
+    input:
+      bytes: [ 0x10, 0x78, 0x60, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrue pn8.h"
+
+  -
+    input:
+      bytes: [ 0x15, 0x78, 0x60, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrue pn13.h"
+
+  -
+    input:
+      bytes: [ 0x17, 0x78, 0x60, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrue pn15.h"
+
+  -
+    input:
+      bytes: [ 0x11, 0x78, 0x60, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrue pn9.h"
+
+  -
+    input:
+      bytes: [ 0x10, 0x78, 0xa0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrue pn8.s"
+
+  -
+    input:
+      bytes: [ 0x15, 0x78, 0xa0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrue pn13.s"
+
+  -
+    input:
+      bytes: [ 0x17, 0x78, 0xa0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrue pn15.s"
+
+  -
+    input:
+      bytes: [ 0x11, 0x78, 0xa0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrue pn9.s"
+
+  -
+    input:
+      bytes: [ 0x10, 0x78, 0xe0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrue pn8.d"
+
+  -
+    input:
+      bytes: [ 0x15, 0x78, 0xe0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrue pn13.d"
+
+  -
+    input:
+      bytes: [ 0x17, 0x78, 0xe0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrue pn15.d"
+
+  -
+    input:
+      bytes: [ 0x11, 0x78, 0xe0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrue pn9.d"
+
+  -
+    input:
+      bytes: [ 0x10, 0x78, 0x20, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrue pn8.b"
+
+  -
+    input:
+      bytes: [ 0x15, 0x78, 0x20, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrue pn13.b"
+
+  -
+    input:
+      bytes: [ 0x17, 0x78, 0x20, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrue pn15.b"
+
+  -
+    input:
+      bytes: [ 0x11, 0x78, 0x20, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptrue pn9.b"
diff --git a/tests/MC/AArch64/SVE2p1/sdot.s.yaml b/tests/MC/AArch64/SVE2p1/sdot.s.yaml
new file mode 100644
index 000000000..f7d9209c7
--- /dev/null
+++ b/tests/MC/AArch64/SVE2p1/sdot.s.yaml
@@ -0,0 +1,240 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xf7, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z23, z31"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xc9, 0x88, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot z23.s, z13.h, z0.h[1]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc8, 0x80, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot z0.s, z0.h, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xc9, 0x95, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot z21.s, z10.h, z5.h[2]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xc9, 0x88, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot z23.s, z13.h, z0.h[1]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xcb, 0x9f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot z31.s, z31.h, z7.h[3]"
+
+  -
+    input:
+      bytes: [ 0xf7, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z23, z31"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xc9, 0x08, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot z23.s, z13.h, z8.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc8, 0x00, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot z0.s, z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x55, 0xc9, 0x15, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot z21.s, z10.h, z21.h"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xc9, 0x08, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot z23.s, z13.h, z8.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0xcb, 0x1f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot z31.s, z31.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xf7, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z23, z31"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xc9, 0x88, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot z23.s, z13.h, z0.h[1]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc8, 0x80, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot z0.s, z0.h, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xc9, 0x95, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot z21.s, z10.h, z5.h[2]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xc9, 0x88, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot z23.s, z13.h, z0.h[1]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xcb, 0x9f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot z31.s, z31.h, z7.h[3]"
+
+  -
+    input:
+      bytes: [ 0xf7, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z23, z31"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xc9, 0x08, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot z23.s, z13.h, z8.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc8, 0x00, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot z0.s, z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x55, 0xc9, 0x15, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot z21.s, z10.h, z21.h"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xc9, 0x08, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot z23.s, z13.h, z8.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0xcb, 0x1f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot z31.s, z31.h, z31.h"
diff --git a/tests/MC/AArch64/SVE2p1/smaxqv.s.yaml b/tests/MC/AArch64/SVE2p1/smaxqv.s.yaml
new file mode 100644
index 000000000..1e4579d96
--- /dev/null
+++ b/tests/MC/AArch64/SVE2p1/smaxqv.s.yaml
@@ -0,0 +1,320 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x4c, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "smaxqv v0.8h, p0, z0.h"
+
+  -
+    input:
+      bytes: [ 0x55, 0x35, 0x4c, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "smaxqv v21.8h, p5, z10.h"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x2d, 0x4c, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "smaxqv v23.8h, p3, z13.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0x4c, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "smaxqv v31.8h, p7, z31.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x8c, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "smaxqv v0.4s, p0, z0.s"
+
+  -
+    input:
+      bytes: [ 0x55, 0x35, 0x8c, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "smaxqv v21.4s, p5, z10.s"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x2d, 0x8c, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "smaxqv v23.4s, p3, z13.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0x8c, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "smaxqv v31.4s, p7, z31.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0xcc, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "smaxqv v0.2d, p0, z0.d"
+
+  -
+    input:
+      bytes: [ 0x55, 0x35, 0xcc, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "smaxqv v21.2d, p5, z10.d"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x2d, 0xcc, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "smaxqv v23.2d, p3, z13.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0xcc, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "smaxqv v31.2d, p7, z31.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x0c, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "smaxqv v0.16b, p0, z0.b"
+
+  -
+    input:
+      bytes: [ 0x55, 0x35, 0x0c, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "smaxqv v21.16b, p5, z10.b"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x2d, 0x0c, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "smaxqv v23.16b, p3, z13.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0x0c, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "smaxqv v31.16b, p7, z31.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x4c, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "smaxqv v0.8h, p0, z0.h"
+
+  -
+    input:
+      bytes: [ 0x55, 0x35, 0x4c, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "smaxqv v21.8h, p5, z10.h"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x2d, 0x4c, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "smaxqv v23.8h, p3, z13.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0x4c, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "smaxqv v31.8h, p7, z31.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x8c, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "smaxqv v0.4s, p0, z0.s"
+
+  -
+    input:
+      bytes: [ 0x55, 0x35, 0x8c, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "smaxqv v21.4s, p5, z10.s"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x2d, 0x8c, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "smaxqv v23.4s, p3, z13.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0x8c, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "smaxqv v31.4s, p7, z31.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0xcc, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "smaxqv v0.2d, p0, z0.d"
+
+  -
+    input:
+      bytes: [ 0x55, 0x35, 0xcc, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "smaxqv v21.2d, p5, z10.d"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x2d, 0xcc, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "smaxqv v23.2d, p3, z13.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0xcc, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "smaxqv v31.2d, p7, z31.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x0c, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "smaxqv v0.16b, p0, z0.b"
+
+  -
+    input:
+      bytes: [ 0x55, 0x35, 0x0c, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "smaxqv v21.16b, p5, z10.b"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x2d, 0x0c, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "smaxqv v23.16b, p3, z13.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0x0c, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "smaxqv v31.16b, p7, z31.b"
diff --git a/tests/MC/AArch64/SVE2p1/sminqv.s.yaml b/tests/MC/AArch64/SVE2p1/sminqv.s.yaml
new file mode 100644
index 000000000..88f4db2a2
--- /dev/null
+++ b/tests/MC/AArch64/SVE2p1/sminqv.s.yaml
@@ -0,0 +1,320 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x4e, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "sminqv v0.8h, p0, z0.h"
+
+  -
+    input:
+      bytes: [ 0x55, 0x35, 0x4e, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "sminqv v21.8h, p5, z10.h"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x2d, 0x4e, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "sminqv v23.8h, p3, z13.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0x4e, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "sminqv v31.8h, p7, z31.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x8e, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "sminqv v0.4s, p0, z0.s"
+
+  -
+    input:
+      bytes: [ 0x55, 0x35, 0x8e, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "sminqv v21.4s, p5, z10.s"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x2d, 0x8e, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "sminqv v23.4s, p3, z13.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0x8e, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "sminqv v31.4s, p7, z31.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0xce, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "sminqv v0.2d, p0, z0.d"
+
+  -
+    input:
+      bytes: [ 0x55, 0x35, 0xce, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "sminqv v21.2d, p5, z10.d"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x2d, 0xce, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "sminqv v23.2d, p3, z13.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0xce, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "sminqv v31.2d, p7, z31.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x0e, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "sminqv v0.16b, p0, z0.b"
+
+  -
+    input:
+      bytes: [ 0x55, 0x35, 0x0e, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "sminqv v21.16b, p5, z10.b"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x2d, 0x0e, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "sminqv v23.16b, p3, z13.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0x0e, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "sminqv v31.16b, p7, z31.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x4e, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "sminqv v0.8h, p0, z0.h"
+
+  -
+    input:
+      bytes: [ 0x55, 0x35, 0x4e, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "sminqv v21.8h, p5, z10.h"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x2d, 0x4e, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "sminqv v23.8h, p3, z13.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0x4e, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "sminqv v31.8h, p7, z31.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x8e, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "sminqv v0.4s, p0, z0.s"
+
+  -
+    input:
+      bytes: [ 0x55, 0x35, 0x8e, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "sminqv v21.4s, p5, z10.s"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x2d, 0x8e, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "sminqv v23.4s, p3, z13.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0x8e, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "sminqv v31.4s, p7, z31.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0xce, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "sminqv v0.2d, p0, z0.d"
+
+  -
+    input:
+      bytes: [ 0x55, 0x35, 0xce, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "sminqv v21.2d, p5, z10.d"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x2d, 0xce, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "sminqv v23.2d, p3, z13.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0xce, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "sminqv v31.2d, p7, z31.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x0e, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "sminqv v0.16b, p0, z0.b"
+
+  -
+    input:
+      bytes: [ 0x55, 0x35, 0x0e, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "sminqv v21.16b, p5, z10.b"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x2d, 0x0e, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "sminqv v23.16b, p3, z13.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0x0e, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "sminqv v31.16b, p7, z31.b"
diff --git a/tests/MC/AArch64/SVE2p1/sqcvtn.s.yaml b/tests/MC/AArch64/SVE2p1/sqcvtn.s.yaml
new file mode 100644
index 000000000..41c3d38eb
--- /dev/null
+++ b/tests/MC/AArch64/SVE2p1/sqcvtn.s.yaml
@@ -0,0 +1,80 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0x31, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqcvtn z0.h, { z0.s, z1.s }"
+
+  -
+    input:
+      bytes: [ 0x55, 0x41, 0x31, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqcvtn z21.h, { z10.s, z11.s }"
+
+  -
+    input:
+      bytes: [ 0x97, 0x41, 0x31, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqcvtn z23.h, { z12.s, z13.s }"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x43, 0x31, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqcvtn z31.h, { z30.s, z31.s }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0x31, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqcvtn z0.h, { z0.s, z1.s }"
+
+  -
+    input:
+      bytes: [ 0x55, 0x41, 0x31, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqcvtn z21.h, { z10.s, z11.s }"
+
+  -
+    input:
+      bytes: [ 0x97, 0x41, 0x31, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqcvtn z23.h, { z12.s, z13.s }"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x43, 0x31, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqcvtn z31.h, { z30.s, z31.s }"
diff --git a/tests/MC/AArch64/SVE2p1/sqcvtun.s.yaml b/tests/MC/AArch64/SVE2p1/sqcvtun.s.yaml
new file mode 100644
index 000000000..1d4ab6d7b
--- /dev/null
+++ b/tests/MC/AArch64/SVE2p1/sqcvtun.s.yaml
@@ -0,0 +1,80 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x50, 0x31, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqcvtun z0.h, { z0.s, z1.s }"
+
+  -
+    input:
+      bytes: [ 0x55, 0x51, 0x31, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqcvtun z21.h, { z10.s, z11.s }"
+
+  -
+    input:
+      bytes: [ 0x97, 0x51, 0x31, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqcvtun z23.h, { z12.s, z13.s }"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x53, 0x31, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqcvtun z31.h, { z30.s, z31.s }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x50, 0x31, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqcvtun z0.h, { z0.s, z1.s }"
+
+  -
+    input:
+      bytes: [ 0x55, 0x51, 0x31, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqcvtun z21.h, { z10.s, z11.s }"
+
+  -
+    input:
+      bytes: [ 0x97, 0x51, 0x31, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqcvtun z23.h, { z12.s, z13.s }"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x53, 0x31, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqcvtun z31.h, { z30.s, z31.s }"
diff --git a/tests/MC/AArch64/SVE2p1/sqrshrn.s.yaml b/tests/MC/AArch64/SVE2p1/sqrshrn.s.yaml
new file mode 100644
index 000000000..fd8a679d3
--- /dev/null
+++ b/tests/MC/AArch64/SVE2p1/sqrshrn.s.yaml
@@ -0,0 +1,80 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x28, 0xb0, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshrn z0.h, { z0.s, z1.s }, #16"
+
+  -
+    input:
+      bytes: [ 0x55, 0x29, 0xb5, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshrn z21.h, { z10.s, z11.s }, #11"
+
+  -
+    input:
+      bytes: [ 0x97, 0x29, 0xb8, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshrn z23.h, { z12.s, z13.s }, #8"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x2b, 0xbf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshrn z31.h, { z30.s, z31.s }, #1"
+
+  -
+    input:
+      bytes: [ 0x00, 0x28, 0xb0, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshrn z0.h, { z0.s, z1.s }, #16"
+
+  -
+    input:
+      bytes: [ 0x55, 0x29, 0xb5, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshrn z21.h, { z10.s, z11.s }, #11"
+
+  -
+    input:
+      bytes: [ 0x97, 0x29, 0xb8, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshrn z23.h, { z12.s, z13.s }, #8"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x2b, 0xbf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshrn z31.h, { z30.s, z31.s }, #1"
diff --git a/tests/MC/AArch64/SVE2p1/sqrshrun.s.yaml b/tests/MC/AArch64/SVE2p1/sqrshrun.s.yaml
new file mode 100644
index 000000000..362ff82f3
--- /dev/null
+++ b/tests/MC/AArch64/SVE2p1/sqrshrun.s.yaml
@@ -0,0 +1,80 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x08, 0xb0, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshrun z0.h, { z0.s, z1.s }, #16"
+
+  -
+    input:
+      bytes: [ 0x55, 0x09, 0xb5, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshrun z21.h, { z10.s, z11.s }, #11"
+
+  -
+    input:
+      bytes: [ 0x97, 0x09, 0xb8, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshrun z23.h, { z12.s, z13.s }, #8"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x0b, 0xbf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshrun z31.h, { z30.s, z31.s }, #1"
+
+  -
+    input:
+      bytes: [ 0x00, 0x08, 0xb0, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshrun z0.h, { z0.s, z1.s }, #16"
+
+  -
+    input:
+      bytes: [ 0x55, 0x09, 0xb5, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshrun z21.h, { z10.s, z11.s }, #11"
+
+  -
+    input:
+      bytes: [ 0x97, 0x09, 0xb8, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshrun z23.h, { z12.s, z13.s }, #8"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x0b, 0xbf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshrun z31.h, { z30.s, z31.s }, #1"
diff --git a/tests/MC/AArch64/SVE2p1/st1b.s.yaml b/tests/MC/AArch64/SVE2p1/st1b.s.yaml
new file mode 100644
index 000000000..c44537249
--- /dev/null
+++ b/tests/MC/AArch64/SVE2p1/st1b.s.yaml
@@ -0,0 +1,320 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x20, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b { z0.b, z1.b }, pn8, [x0, x0]"
+
+  -
+    input:
+      bytes: [ 0x54, 0x15, 0x35, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b { z20.b, z21.b }, pn13, [x10, x21]"
+
+  -
+    input:
+      bytes: [ 0xb6, 0x0d, 0x28, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b { z22.b, z23.b }, pn11, [x13, x8]"
+
+  -
+    input:
+      bytes: [ 0xfe, 0x1f, 0x3f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b { z30.b, z31.b }, pn15, [sp, xzr]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x60, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b { z0.b, z1.b }, pn8, [x0]"
+
+  -
+    input:
+      bytes: [ 0x54, 0x15, 0x65, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b { z20.b, z21.b }, pn13, [x10, #10, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xb6, 0x0d, 0x68, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b { z22.b, z23.b }, pn11, [x13, #-16, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xfe, 0x1f, 0x6f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b { z30.b, z31.b }, pn15, [sp, #-2, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x20, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b { z0.b - z3.b }, pn8, [x0, x0]"
+
+  -
+    input:
+      bytes: [ 0x54, 0x95, 0x35, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b { z20.b - z23.b }, pn13, [x10, x21]"
+
+  -
+    input:
+      bytes: [ 0xb4, 0x8d, 0x28, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b { z20.b - z23.b }, pn11, [x13, x8]"
+
+  -
+    input:
+      bytes: [ 0xfc, 0x9f, 0x3f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b { z28.b - z31.b }, pn15, [sp, xzr]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x60, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b { z0.b - z3.b }, pn8, [x0]"
+
+  -
+    input:
+      bytes: [ 0x54, 0x95, 0x65, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b { z20.b - z23.b }, pn13, [x10, #20, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xb4, 0x8d, 0x68, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b { z20.b - z23.b }, pn11, [x13, #-32, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xfc, 0x9f, 0x6f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b { z28.b - z31.b }, pn15, [sp, #-4, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x20, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b { z0.b, z1.b }, pn8, [x0, x0]"
+
+  -
+    input:
+      bytes: [ 0x54, 0x15, 0x35, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b { z20.b, z21.b }, pn13, [x10, x21]"
+
+  -
+    input:
+      bytes: [ 0xb6, 0x0d, 0x28, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b { z22.b, z23.b }, pn11, [x13, x8]"
+
+  -
+    input:
+      bytes: [ 0xfe, 0x1f, 0x3f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b { z30.b, z31.b }, pn15, [sp, xzr]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x60, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b { z0.b, z1.b }, pn8, [x0]"
+
+  -
+    input:
+      bytes: [ 0x54, 0x15, 0x65, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b { z20.b, z21.b }, pn13, [x10, #10, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xb6, 0x0d, 0x68, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b { z22.b, z23.b }, pn11, [x13, #-16, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xfe, 0x1f, 0x6f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b { z30.b, z31.b }, pn15, [sp, #-2, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x20, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b { z0.b - z3.b }, pn8, [x0, x0]"
+
+  -
+    input:
+      bytes: [ 0x54, 0x95, 0x35, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b { z20.b - z23.b }, pn13, [x10, x21]"
+
+  -
+    input:
+      bytes: [ 0xb4, 0x8d, 0x28, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b { z20.b - z23.b }, pn11, [x13, x8]"
+
+  -
+    input:
+      bytes: [ 0xfc, 0x9f, 0x3f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b { z28.b - z31.b }, pn15, [sp, xzr]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x60, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b { z0.b - z3.b }, pn8, [x0]"
+
+  -
+    input:
+      bytes: [ 0x54, 0x95, 0x65, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b { z20.b - z23.b }, pn13, [x10, #20, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xb4, 0x8d, 0x68, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b { z20.b - z23.b }, pn11, [x13, #-32, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xfc, 0x9f, 0x6f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1b { z28.b - z31.b }, pn15, [sp, #-4, mul vl]"
diff --git a/tests/MC/AArch64/SVE2p1/st1d.s.yaml b/tests/MC/AArch64/SVE2p1/st1d.s.yaml
new file mode 100644
index 000000000..fbb0af06b
--- /dev/null
+++ b/tests/MC/AArch64/SVE2p1/st1d.s.yaml
@@ -0,0 +1,320 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0x20, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d { z0.d, z1.d }, pn8, [x0, x0, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x54, 0x75, 0x35, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d { z20.d, z21.d }, pn13, [x10, x21, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0xb6, 0x6d, 0x28, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d { z22.d, z23.d }, pn11, [x13, x8, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0xfe, 0x7f, 0x3f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d { z30.d, z31.d }, pn15, [sp, xzr, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0x60, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d { z0.d, z1.d }, pn8, [x0]"
+
+  -
+    input:
+      bytes: [ 0x54, 0x75, 0x65, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d { z20.d, z21.d }, pn13, [x10, #10, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xb6, 0x6d, 0x68, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d { z22.d, z23.d }, pn11, [x13, #-16, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xfe, 0x7f, 0x6f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d { z30.d, z31.d }, pn15, [sp, #-2, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x20, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d { z0.d - z3.d }, pn8, [x0, x0, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x54, 0xf5, 0x35, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d { z20.d - z23.d }, pn13, [x10, x21, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0xb4, 0xed, 0x28, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d { z20.d - z23.d }, pn11, [x13, x8, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0xfc, 0xff, 0x3f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d { z28.d - z31.d }, pn15, [sp, xzr, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x60, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d { z0.d - z3.d }, pn8, [x0]"
+
+  -
+    input:
+      bytes: [ 0x54, 0xf5, 0x65, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d { z20.d - z23.d }, pn13, [x10, #20, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xb4, 0xed, 0x68, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d { z20.d - z23.d }, pn11, [x13, #-32, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xfc, 0xff, 0x6f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d { z28.d - z31.d }, pn15, [sp, #-4, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0x20, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d { z0.d, z1.d }, pn8, [x0, x0, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x54, 0x75, 0x35, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d { z20.d, z21.d }, pn13, [x10, x21, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0xb6, 0x6d, 0x28, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d { z22.d, z23.d }, pn11, [x13, x8, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0xfe, 0x7f, 0x3f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d { z30.d, z31.d }, pn15, [sp, xzr, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0x60, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d { z0.d, z1.d }, pn8, [x0]"
+
+  -
+    input:
+      bytes: [ 0x54, 0x75, 0x65, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d { z20.d, z21.d }, pn13, [x10, #10, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xb6, 0x6d, 0x68, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d { z22.d, z23.d }, pn11, [x13, #-16, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xfe, 0x7f, 0x6f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d { z30.d, z31.d }, pn15, [sp, #-2, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x20, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d { z0.d - z3.d }, pn8, [x0, x0, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x54, 0xf5, 0x35, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d { z20.d - z23.d }, pn13, [x10, x21, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0xb4, 0xed, 0x28, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d { z20.d - z23.d }, pn11, [x13, x8, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0xfc, 0xff, 0x3f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d { z28.d - z31.d }, pn15, [sp, xzr, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x60, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d { z0.d - z3.d }, pn8, [x0]"
+
+  -
+    input:
+      bytes: [ 0x54, 0xf5, 0x65, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d { z20.d - z23.d }, pn13, [x10, #20, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xb4, 0xed, 0x68, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d { z20.d - z23.d }, pn11, [x13, #-32, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xfc, 0xff, 0x6f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d { z28.d - z31.d }, pn15, [sp, #-4, mul vl]"
diff --git a/tests/MC/AArch64/SVE2p1/st1d_q.s.yaml b/tests/MC/AArch64/SVE2p1/st1d_q.s.yaml
new file mode 100644
index 000000000..1ff939d43
--- /dev/null
+++ b/tests/MC/AArch64/SVE2p1/st1d_q.s.yaml
@@ -0,0 +1,100 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0xc0, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d { z0.q }, p0, [x0, x0, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x55, 0xd5, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d { z21.q }, p5, [x10, x21, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x4d, 0xc8, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d { z23.q }, p3, [x13, x8, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x4d, 0xc8, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d { z23.q }, p3, [x13, x8, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xc0, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d { z0.q }, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xc0, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d { z0.q }, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf5, 0xc5, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d { z21.q }, p5, [x10, #5, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0xc8, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d { z23.q }, p3, [x13, #-8, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xcf, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d { z31.q }, p7, [sp, #-1, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xcf, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1d { z31.q }, p7, [sp, #-1, mul vl]"
diff --git a/tests/MC/AArch64/SVE2p1/st1h.s.yaml b/tests/MC/AArch64/SVE2p1/st1h.s.yaml
new file mode 100644
index 000000000..444b780f6
--- /dev/null
+++ b/tests/MC/AArch64/SVE2p1/st1h.s.yaml
@@ -0,0 +1,320 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x20, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h { z0.h, z1.h }, pn8, [x0, x0, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x54, 0x35, 0x35, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h { z20.h, z21.h }, pn13, [x10, x21, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0xb6, 0x2d, 0x28, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h { z22.h, z23.h }, pn11, [x13, x8, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0xfe, 0x3f, 0x3f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h { z30.h, z31.h }, pn15, [sp, xzr, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x60, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h { z0.h, z1.h }, pn8, [x0]"
+
+  -
+    input:
+      bytes: [ 0x54, 0x35, 0x65, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h { z20.h, z21.h }, pn13, [x10, #10, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xb6, 0x2d, 0x68, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h { z22.h, z23.h }, pn11, [x13, #-16, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xfe, 0x3f, 0x6f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h { z30.h, z31.h }, pn15, [sp, #-2, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x20, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h { z0.h - z3.h }, pn8, [x0, x0, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x54, 0xb5, 0x35, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h { z20.h - z23.h }, pn13, [x10, x21, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0xb4, 0xad, 0x28, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h { z20.h - z23.h }, pn11, [x13, x8, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0xfc, 0xbf, 0x3f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h { z28.h - z31.h }, pn15, [sp, xzr, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x60, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h { z0.h - z3.h }, pn8, [x0]"
+
+  -
+    input:
+      bytes: [ 0x54, 0xb5, 0x65, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h { z20.h - z23.h }, pn13, [x10, #20, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xb4, 0xad, 0x68, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h { z20.h - z23.h }, pn11, [x13, #-32, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xfc, 0xbf, 0x6f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h { z28.h - z31.h }, pn15, [sp, #-4, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x20, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h { z0.h, z1.h }, pn8, [x0, x0, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x54, 0x35, 0x35, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h { z20.h, z21.h }, pn13, [x10, x21, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0xb6, 0x2d, 0x28, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h { z22.h, z23.h }, pn11, [x13, x8, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0xfe, 0x3f, 0x3f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h { z30.h, z31.h }, pn15, [sp, xzr, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x60, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h { z0.h, z1.h }, pn8, [x0]"
+
+  -
+    input:
+      bytes: [ 0x54, 0x35, 0x65, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h { z20.h, z21.h }, pn13, [x10, #10, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xb6, 0x2d, 0x68, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h { z22.h, z23.h }, pn11, [x13, #-16, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xfe, 0x3f, 0x6f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h { z30.h, z31.h }, pn15, [sp, #-2, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x20, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h { z0.h - z3.h }, pn8, [x0, x0, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x54, 0xb5, 0x35, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h { z20.h - z23.h }, pn13, [x10, x21, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0xb4, 0xad, 0x28, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h { z20.h - z23.h }, pn11, [x13, x8, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0xfc, 0xbf, 0x3f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h { z28.h - z31.h }, pn15, [sp, xzr, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x60, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h { z0.h - z3.h }, pn8, [x0]"
+
+  -
+    input:
+      bytes: [ 0x54, 0xb5, 0x65, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h { z20.h - z23.h }, pn13, [x10, #20, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xb4, 0xad, 0x68, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h { z20.h - z23.h }, pn11, [x13, #-32, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xfc, 0xbf, 0x6f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1h { z28.h - z31.h }, pn15, [sp, #-4, mul vl]"
diff --git a/tests/MC/AArch64/SVE2p1/st1q.s.yaml b/tests/MC/AArch64/SVE2p1/st1q.s.yaml
new file mode 100644
index 000000000..f8c9a9006
--- /dev/null
+++ b/tests/MC/AArch64/SVE2p1/st1q.s.yaml
@@ -0,0 +1,40 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x20, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1q { z0.q }, p0, [z0.d, x0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x35, 0x35, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1q { z21.q }, p5, [z10.d, x21]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x2d, 0x28, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1q { z23.q }, p3, [z13.d, x8]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0x3f, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1q { z31.q }, p7, [z31.d]"
diff --git a/tests/MC/AArch64/SVE2p1/st1w.s.yaml b/tests/MC/AArch64/SVE2p1/st1w.s.yaml
new file mode 100644
index 000000000..99f51f46d
--- /dev/null
+++ b/tests/MC/AArch64/SVE2p1/st1w.s.yaml
@@ -0,0 +1,320 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0x20, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w { z0.s, z1.s }, pn8, [x0, x0, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x54, 0x55, 0x35, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w { z20.s, z21.s }, pn13, [x10, x21, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0xb6, 0x4d, 0x28, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w { z22.s, z23.s }, pn11, [x13, x8, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0xfe, 0x5f, 0x3f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w { z30.s, z31.s }, pn15, [sp, xzr, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0x60, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w { z0.s, z1.s }, pn8, [x0]"
+
+  -
+    input:
+      bytes: [ 0x54, 0x55, 0x65, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w { z20.s, z21.s }, pn13, [x10, #10, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xb6, 0x4d, 0x68, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w { z22.s, z23.s }, pn11, [x13, #-16, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xfe, 0x5f, 0x6f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w { z30.s, z31.s }, pn15, [sp, #-2, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x20, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w { z0.s - z3.s }, pn8, [x0, x0, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x54, 0xd5, 0x35, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w { z20.s - z23.s }, pn13, [x10, x21, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0xb4, 0xcd, 0x28, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w { z20.s - z23.s }, pn11, [x13, x8, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0xfc, 0xdf, 0x3f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w { z28.s - z31.s }, pn15, [sp, xzr, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x60, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w { z0.s - z3.s }, pn8, [x0]"
+
+  -
+    input:
+      bytes: [ 0x54, 0xd5, 0x65, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w { z20.s - z23.s }, pn13, [x10, #20, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xb4, 0xcd, 0x68, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w { z20.s - z23.s }, pn11, [x13, #-32, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xfc, 0xdf, 0x6f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w { z28.s - z31.s }, pn15, [sp, #-4, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0x20, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w { z0.s, z1.s }, pn8, [x0, x0, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x54, 0x55, 0x35, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w { z20.s, z21.s }, pn13, [x10, x21, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0xb6, 0x4d, 0x28, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w { z22.s, z23.s }, pn11, [x13, x8, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0xfe, 0x5f, 0x3f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w { z30.s, z31.s }, pn15, [sp, xzr, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0x60, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w { z0.s, z1.s }, pn8, [x0]"
+
+  -
+    input:
+      bytes: [ 0x54, 0x55, 0x65, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w { z20.s, z21.s }, pn13, [x10, #10, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xb6, 0x4d, 0x68, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w { z22.s, z23.s }, pn11, [x13, #-16, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xfe, 0x5f, 0x6f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w { z30.s, z31.s }, pn15, [sp, #-2, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x20, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w { z0.s - z3.s }, pn8, [x0, x0, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x54, 0xd5, 0x35, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w { z20.s - z23.s }, pn13, [x10, x21, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0xb4, 0xcd, 0x28, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w { z20.s - z23.s }, pn11, [x13, x8, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0xfc, 0xdf, 0x3f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w { z28.s - z31.s }, pn15, [sp, xzr, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x60, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w { z0.s - z3.s }, pn8, [x0]"
+
+  -
+    input:
+      bytes: [ 0x54, 0xd5, 0x65, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w { z20.s - z23.s }, pn13, [x10, #20, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xb4, 0xcd, 0x68, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w { z20.s - z23.s }, pn11, [x13, #-32, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xfc, 0xdf, 0x6f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w { z28.s - z31.s }, pn15, [sp, #-4, mul vl]"
diff --git a/tests/MC/AArch64/SVE2p1/st1w_q.s.yaml b/tests/MC/AArch64/SVE2p1/st1w_q.s.yaml
new file mode 100644
index 000000000..050f61735
--- /dev/null
+++ b/tests/MC/AArch64/SVE2p1/st1w_q.s.yaml
@@ -0,0 +1,100 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0x00, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w { z0.q }, p0, [x0, x0, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x55, 0x15, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w { z21.q }, p5, [x10, x21, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x4d, 0x08, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w { z23.q }, p3, [x13, x8, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x4d, 0x08, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w { z23.q }, p3, [x13, x8, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x00, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w { z0.q }, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x00, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w { z0.q }, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf5, 0x05, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w { z21.q }, p5, [x10, #5, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0x08, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w { z23.q }, p3, [x13, #-8, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0x0f, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w { z31.q }, p7, [sp, #-1, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0x0f, 0xe5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1w { z31.q }, p7, [sp, #-1, mul vl]"
diff --git a/tests/MC/AArch64/SVE2p1/st2q.s.yaml b/tests/MC/AArch64/SVE2p1/st2q.s.yaml
new file mode 100644
index 000000000..b199050c5
--- /dev/null
+++ b/tests/MC/AArch64/SVE2p1/st2q.s.yaml
@@ -0,0 +1,140 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x60, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st2q { z0.q, z1.q }, p0, [x0, x0, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x15, 0x75, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st2q { z21.q, z22.q }, p5, [x10, x21, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x0d, 0x68, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st2q { z23.q, z24.q }, p3, [x13, x8, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x40, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st2q { z0.q, z1.q }, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x15, 0x45, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st2q { z21.q, z22.q }, p5, [x10, #10, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x0d, 0x48, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st2q { z23.q, z24.q }, p3, [x13, #-16, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0x4f, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st2q { z31.q, z0.q }, p7, [sp, #-2, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x60, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st2q { z0.q, z1.q }, p0, [x0, x0, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x15, 0x75, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st2q { z21.q, z22.q }, p5, [x10, x21, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x0d, 0x68, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st2q { z23.q, z24.q }, p3, [x13, x8, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x40, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st2q { z0.q, z1.q }, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x15, 0x45, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st2q { z21.q, z22.q }, p5, [x10, #10, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x0d, 0x48, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st2q { z23.q, z24.q }, p3, [x13, #-16, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0x4f, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st2q { z31.q, z0.q }, p7, [sp, #-2, mul vl]"
diff --git a/tests/MC/AArch64/SVE2p1/st3q.s.yaml b/tests/MC/AArch64/SVE2p1/st3q.s.yaml
new file mode 100644
index 000000000..533b56c5a
--- /dev/null
+++ b/tests/MC/AArch64/SVE2p1/st3q.s.yaml
@@ -0,0 +1,140 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0xa0, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st3q { z0.q - z2.q }, p0, [x0, x0, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x15, 0xb5, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st3q { z21.q - z23.q }, p5, [x10, x21, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x0d, 0xa8, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st3q { z23.q - z25.q }, p3, [x13, x8, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x80, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st3q { z0.q - z2.q }, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x15, 0x85, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st3q { z21.q - z23.q }, p5, [x10, #15, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x0d, 0x88, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st3q { z23.q - z25.q }, p3, [x13, #-24, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0x8f, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st3q { z31.q, z0.q, z1.q }, p7, [sp, #-3, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0xa0, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st3q { z0.q - z2.q }, p0, [x0, x0, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x15, 0xb5, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st3q { z21.q - z23.q }, p5, [x10, x21, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x0d, 0xa8, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st3q { z23.q - z25.q }, p3, [x13, x8, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x80, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st3q { z0.q - z2.q }, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x15, 0x85, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st3q { z21.q - z23.q }, p5, [x10, #15, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x0d, 0x88, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st3q { z23.q - z25.q }, p3, [x13, #-24, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0x8f, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st3q { z31.q, z0.q, z1.q }, p7, [sp, #-3, mul vl]"
diff --git a/tests/MC/AArch64/SVE2p1/st4q.s.yaml b/tests/MC/AArch64/SVE2p1/st4q.s.yaml
new file mode 100644
index 000000000..4cec2424a
--- /dev/null
+++ b/tests/MC/AArch64/SVE2p1/st4q.s.yaml
@@ -0,0 +1,140 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0xe0, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st4q { z0.q - z3.q }, p0, [x0, x0, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x15, 0xf5, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st4q { z21.q - z24.q }, p5, [x10, x21, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x0d, 0xe8, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st4q { z23.q - z26.q }, p3, [x13, x8, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0xc0, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st4q { z0.q - z3.q }, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x15, 0xc5, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st4q { z21.q - z24.q }, p5, [x10, #20, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x0d, 0xc8, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st4q { z23.q - z26.q }, p3, [x13, #-32, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0xcf, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st4q { z31.q, z0.q, z1.q, z2.q }, p7, [sp, #-4, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0xe0, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st4q { z0.q - z3.q }, p0, [x0, x0, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x15, 0xf5, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st4q { z21.q - z24.q }, p5, [x10, x21, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x0d, 0xe8, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st4q { z23.q - z26.q }, p3, [x13, x8, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0xc0, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st4q { z0.q - z3.q }, p0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x15, 0xc5, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st4q { z21.q - z24.q }, p5, [x10, #20, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x0d, 0xc8, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st4q { z23.q - z26.q }, p3, [x13, #-32, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0xcf, 0xe4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "st4q { z31.q, z0.q, z1.q, z2.q }, p7, [sp, #-4, mul vl]"
diff --git a/tests/MC/AArch64/SVE2p1/stnt1b.s.yaml b/tests/MC/AArch64/SVE2p1/stnt1b.s.yaml
new file mode 100644
index 000000000..2b69d5066
--- /dev/null
+++ b/tests/MC/AArch64/SVE2p1/stnt1b.s.yaml
@@ -0,0 +1,320 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0x20, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1b { z0.b, z1.b }, pn8, [x0, x0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x15, 0x35, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1b { z20.b, z21.b }, pn13, [x10, x21]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x0d, 0x28, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1b { z22.b, z23.b }, pn11, [x13, x8]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0x3f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1b { z30.b, z31.b }, pn15, [sp, xzr]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0x60, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1b { z0.b, z1.b }, pn8, [x0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x15, 0x65, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1b { z20.b, z21.b }, pn13, [x10, #10, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x0d, 0x68, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1b { z22.b, z23.b }, pn11, [x13, #-16, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0x6f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1b { z30.b, z31.b }, pn15, [sp, #-2, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x80, 0x20, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1b { z0.b - z3.b }, pn8, [x0, x0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x95, 0x35, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1b { z20.b - z23.b }, pn13, [x10, x21]"
+
+  -
+    input:
+      bytes: [ 0xb5, 0x8d, 0x28, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1b { z20.b - z23.b }, pn11, [x13, x8]"
+
+  -
+    input:
+      bytes: [ 0xfd, 0x9f, 0x3f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1b { z28.b - z31.b }, pn15, [sp, xzr]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x80, 0x60, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1b { z0.b - z3.b }, pn8, [x0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x95, 0x65, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1b { z20.b - z23.b }, pn13, [x10, #20, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xb5, 0x8d, 0x68, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1b { z20.b - z23.b }, pn11, [x13, #-32, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xfd, 0x9f, 0x6f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1b { z28.b - z31.b }, pn15, [sp, #-4, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0x20, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1b { z0.b, z1.b }, pn8, [x0, x0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x15, 0x35, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1b { z20.b, z21.b }, pn13, [x10, x21]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x0d, 0x28, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1b { z22.b, z23.b }, pn11, [x13, x8]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0x3f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1b { z30.b, z31.b }, pn15, [sp, xzr]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0x60, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1b { z0.b, z1.b }, pn8, [x0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x15, 0x65, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1b { z20.b, z21.b }, pn13, [x10, #10, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x0d, 0x68, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1b { z22.b, z23.b }, pn11, [x13, #-16, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0x6f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1b { z30.b, z31.b }, pn15, [sp, #-2, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x80, 0x20, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1b { z0.b - z3.b }, pn8, [x0, x0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x95, 0x35, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1b { z20.b - z23.b }, pn13, [x10, x21]"
+
+  -
+    input:
+      bytes: [ 0xb5, 0x8d, 0x28, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1b { z20.b - z23.b }, pn11, [x13, x8]"
+
+  -
+    input:
+      bytes: [ 0xfd, 0x9f, 0x3f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1b { z28.b - z31.b }, pn15, [sp, xzr]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x80, 0x60, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1b { z0.b - z3.b }, pn8, [x0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x95, 0x65, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1b { z20.b - z23.b }, pn13, [x10, #20, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xb5, 0x8d, 0x68, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1b { z20.b - z23.b }, pn11, [x13, #-32, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xfd, 0x9f, 0x6f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1b { z28.b - z31.b }, pn15, [sp, #-4, mul vl]"
diff --git a/tests/MC/AArch64/SVE2p1/stnt1d.s.yaml b/tests/MC/AArch64/SVE2p1/stnt1d.s.yaml
new file mode 100644
index 000000000..93b56b963
--- /dev/null
+++ b/tests/MC/AArch64/SVE2p1/stnt1d.s.yaml
@@ -0,0 +1,320 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x01, 0x60, 0x20, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1d { z0.d, z1.d }, pn8, [x0, x0, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x75, 0x35, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1d { z20.d, z21.d }, pn13, [x10, x21, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x6d, 0x28, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1d { z22.d, z23.d }, pn11, [x13, x8, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x7f, 0x3f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1d { z30.d, z31.d }, pn15, [sp, xzr, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x60, 0x60, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1d { z0.d, z1.d }, pn8, [x0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x75, 0x65, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1d { z20.d, z21.d }, pn13, [x10, #10, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x6d, 0x68, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1d { z22.d, z23.d }, pn11, [x13, #-16, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x7f, 0x6f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1d { z30.d, z31.d }, pn15, [sp, #-2, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x01, 0xe0, 0x20, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1d { z0.d - z3.d }, pn8, [x0, x0, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf5, 0x35, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1d { z20.d - z23.d }, pn13, [x10, x21, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0xb5, 0xed, 0x28, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1d { z20.d - z23.d }, pn11, [x13, x8, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0xfd, 0xff, 0x3f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1d { z28.d - z31.d }, pn15, [sp, xzr, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x01, 0xe0, 0x60, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1d { z0.d - z3.d }, pn8, [x0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf5, 0x65, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1d { z20.d - z23.d }, pn13, [x10, #20, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xb5, 0xed, 0x68, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1d { z20.d - z23.d }, pn11, [x13, #-32, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xfd, 0xff, 0x6f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1d { z28.d - z31.d }, pn15, [sp, #-4, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x60, 0x20, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1d { z0.d, z1.d }, pn8, [x0, x0, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x75, 0x35, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1d { z20.d, z21.d }, pn13, [x10, x21, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x6d, 0x28, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1d { z22.d, z23.d }, pn11, [x13, x8, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x7f, 0x3f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1d { z30.d, z31.d }, pn15, [sp, xzr, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x60, 0x60, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1d { z0.d, z1.d }, pn8, [x0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x75, 0x65, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1d { z20.d, z21.d }, pn13, [x10, #10, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x6d, 0x68, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1d { z22.d, z23.d }, pn11, [x13, #-16, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x7f, 0x6f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1d { z30.d, z31.d }, pn15, [sp, #-2, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x01, 0xe0, 0x20, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1d { z0.d - z3.d }, pn8, [x0, x0, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf5, 0x35, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1d { z20.d - z23.d }, pn13, [x10, x21, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0xb5, 0xed, 0x28, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1d { z20.d - z23.d }, pn11, [x13, x8, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0xfd, 0xff, 0x3f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1d { z28.d - z31.d }, pn15, [sp, xzr, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0x01, 0xe0, 0x60, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1d { z0.d - z3.d }, pn8, [x0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf5, 0x65, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1d { z20.d - z23.d }, pn13, [x10, #20, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xb5, 0xed, 0x68, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1d { z20.d - z23.d }, pn11, [x13, #-32, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xfd, 0xff, 0x6f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1d { z28.d - z31.d }, pn15, [sp, #-4, mul vl]"
diff --git a/tests/MC/AArch64/SVE2p1/stnt1h.s.yaml b/tests/MC/AArch64/SVE2p1/stnt1h.s.yaml
new file mode 100644
index 000000000..8ce949430
--- /dev/null
+++ b/tests/MC/AArch64/SVE2p1/stnt1h.s.yaml
@@ -0,0 +1,320 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x01, 0x20, 0x20, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1h { z0.h, z1.h }, pn8, [x0, x0, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x35, 0x35, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1h { z20.h, z21.h }, pn13, [x10, x21, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x2d, 0x28, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1h { z22.h, z23.h }, pn11, [x13, x8, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0x3f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1h { z30.h, z31.h }, pn15, [sp, xzr, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x20, 0x60, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1h { z0.h, z1.h }, pn8, [x0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x35, 0x65, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1h { z20.h, z21.h }, pn13, [x10, #10, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x2d, 0x68, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1h { z22.h, z23.h }, pn11, [x13, #-16, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0x6f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1h { z30.h, z31.h }, pn15, [sp, #-2, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x01, 0xa0, 0x20, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1h { z0.h - z3.h }, pn8, [x0, x0, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xb5, 0x35, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1h { z20.h - z23.h }, pn13, [x10, x21, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0xb5, 0xad, 0x28, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1h { z20.h - z23.h }, pn11, [x13, x8, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0xfd, 0xbf, 0x3f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1h { z28.h - z31.h }, pn15, [sp, xzr, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x01, 0xa0, 0x60, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1h { z0.h - z3.h }, pn8, [x0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xb5, 0x65, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1h { z20.h - z23.h }, pn13, [x10, #20, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xb5, 0xad, 0x68, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1h { z20.h - z23.h }, pn11, [x13, #-32, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xfd, 0xbf, 0x6f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1h { z28.h - z31.h }, pn15, [sp, #-4, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x20, 0x20, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1h { z0.h, z1.h }, pn8, [x0, x0, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x35, 0x35, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1h { z20.h, z21.h }, pn13, [x10, x21, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x2d, 0x28, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1h { z22.h, z23.h }, pn11, [x13, x8, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0x3f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1h { z30.h, z31.h }, pn15, [sp, xzr, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x20, 0x60, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1h { z0.h, z1.h }, pn8, [x0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x35, 0x65, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1h { z20.h, z21.h }, pn13, [x10, #10, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x2d, 0x68, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1h { z22.h, z23.h }, pn11, [x13, #-16, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0x6f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1h { z30.h, z31.h }, pn15, [sp, #-2, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x01, 0xa0, 0x20, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1h { z0.h - z3.h }, pn8, [x0, x0, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xb5, 0x35, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1h { z20.h - z23.h }, pn13, [x10, x21, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0xb5, 0xad, 0x28, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1h { z20.h - z23.h }, pn11, [x13, x8, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0xfd, 0xbf, 0x3f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1h { z28.h - z31.h }, pn15, [sp, xzr, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0x01, 0xa0, 0x60, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1h { z0.h - z3.h }, pn8, [x0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xb5, 0x65, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1h { z20.h - z23.h }, pn13, [x10, #20, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xb5, 0xad, 0x68, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1h { z20.h - z23.h }, pn11, [x13, #-32, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xfd, 0xbf, 0x6f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1h { z28.h - z31.h }, pn15, [sp, #-4, mul vl]"
diff --git a/tests/MC/AArch64/SVE2p1/stnt1w.s.yaml b/tests/MC/AArch64/SVE2p1/stnt1w.s.yaml
new file mode 100644
index 000000000..90ca4c798
--- /dev/null
+++ b/tests/MC/AArch64/SVE2p1/stnt1w.s.yaml
@@ -0,0 +1,320 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x01, 0x40, 0x20, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1w { z0.s, z1.s }, pn8, [x0, x0, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x55, 0x35, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1w { z20.s, z21.s }, pn13, [x10, x21, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x4d, 0x28, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1w { z22.s, z23.s }, pn11, [x13, x8, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x5f, 0x3f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1w { z30.s, z31.s }, pn15, [sp, xzr, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x40, 0x60, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1w { z0.s, z1.s }, pn8, [x0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x55, 0x65, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1w { z20.s, z21.s }, pn13, [x10, #10, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x4d, 0x68, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1w { z22.s, z23.s }, pn11, [x13, #-16, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x5f, 0x6f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1w { z30.s, z31.s }, pn15, [sp, #-2, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x01, 0xc0, 0x20, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1w { z0.s - z3.s }, pn8, [x0, x0, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xd5, 0x35, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1w { z20.s - z23.s }, pn13, [x10, x21, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0xb5, 0xcd, 0x28, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1w { z20.s - z23.s }, pn11, [x13, x8, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0xfd, 0xdf, 0x3f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1w { z28.s - z31.s }, pn15, [sp, xzr, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x01, 0xc0, 0x60, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1w { z0.s - z3.s }, pn8, [x0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xd5, 0x65, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1w { z20.s - z23.s }, pn13, [x10, #20, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xb5, 0xcd, 0x68, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1w { z20.s - z23.s }, pn11, [x13, #-32, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xfd, 0xdf, 0x6f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1w { z28.s - z31.s }, pn15, [sp, #-4, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x40, 0x20, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1w { z0.s, z1.s }, pn8, [x0, x0, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x55, 0x35, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1w { z20.s, z21.s }, pn13, [x10, x21, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x4d, 0x28, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1w { z22.s, z23.s }, pn11, [x13, x8, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x5f, 0x3f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1w { z30.s, z31.s }, pn15, [sp, xzr, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x40, 0x60, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1w { z0.s, z1.s }, pn8, [x0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0x55, 0x65, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1w { z20.s, z21.s }, pn13, [x10, #10, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x4d, 0x68, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1w { z22.s, z23.s }, pn11, [x13, #-16, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x5f, 0x6f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1w { z30.s, z31.s }, pn15, [sp, #-2, mul vl]"
+
+  -
+    input:
+      bytes: [ 0x01, 0xc0, 0x20, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1w { z0.s - z3.s }, pn8, [x0, x0, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xd5, 0x35, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1w { z20.s - z23.s }, pn13, [x10, x21, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0xb5, 0xcd, 0x28, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1w { z20.s - z23.s }, pn11, [x13, x8, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0xfd, 0xdf, 0x3f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1w { z28.s - z31.s }, pn15, [sp, xzr, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0x01, 0xc0, 0x60, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1w { z0.s - z3.s }, pn8, [x0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xd5, 0x65, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1w { z20.s - z23.s }, pn13, [x10, #20, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xb5, 0xcd, 0x68, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1w { z20.s - z23.s }, pn11, [x13, #-32, mul vl]"
+
+  -
+    input:
+      bytes: [ 0xfd, 0xdf, 0x6f, 0xa0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnt1w { z28.s - z31.s }, pn15, [sp, #-4, mul vl]"
diff --git a/tests/MC/AArch64/SVE2p1/tblq.s.yaml b/tests/MC/AArch64/SVE2p1/tblq.s.yaml
new file mode 100644
index 000000000..58911f6a0
--- /dev/null
+++ b/tests/MC/AArch64/SVE2p1/tblq.s.yaml
@@ -0,0 +1,320 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xf8, 0x40, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "tblq z0.h, { z0.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf9, 0x55, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "tblq z21.h, { z10.h }, z21.h"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xf9, 0x48, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "tblq z23.h, { z13.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0xfb, 0x5f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "tblq z31.h, { z31.h }, z31.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf8, 0x80, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "tblq z0.s, { z0.s }, z0.s"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf9, 0x95, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "tblq z21.s, { z10.s }, z21.s"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xf9, 0x88, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "tblq z23.s, { z13.s }, z8.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0xfb, 0x9f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "tblq z31.s, { z31.s }, z31.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf8, 0xc0, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "tblq z0.d, { z0.d }, z0.d"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf9, 0xd5, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "tblq z21.d, { z10.d }, z21.d"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xf9, 0xc8, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "tblq z23.d, { z13.d }, z8.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0xfb, 0xdf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "tblq z31.d, { z31.d }, z31.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf8, 0x00, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "tblq z0.b, { z0.b }, z0.b"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf9, 0x15, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "tblq z21.b, { z10.b }, z21.b"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xf9, 0x08, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "tblq z23.b, { z13.b }, z8.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0xfb, 0x1f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "tblq z31.b, { z31.b }, z31.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf8, 0x40, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "tblq z0.h, { z0.h }, z0.h"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf9, 0x55, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "tblq z21.h, { z10.h }, z21.h"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xf9, 0x48, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "tblq z23.h, { z13.h }, z8.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0xfb, 0x5f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "tblq z31.h, { z31.h }, z31.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf8, 0x80, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "tblq z0.s, { z0.s }, z0.s"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf9, 0x95, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "tblq z21.s, { z10.s }, z21.s"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xf9, 0x88, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "tblq z23.s, { z13.s }, z8.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0xfb, 0x9f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "tblq z31.s, { z31.s }, z31.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf8, 0xc0, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "tblq z0.d, { z0.d }, z0.d"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf9, 0xd5, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "tblq z21.d, { z10.d }, z21.d"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xf9, 0xc8, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "tblq z23.d, { z13.d }, z8.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0xfb, 0xdf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "tblq z31.d, { z31.d }, z31.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf8, 0x00, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "tblq z0.b, { z0.b }, z0.b"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf9, 0x15, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "tblq z21.b, { z10.b }, z21.b"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xf9, 0x08, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "tblq z23.b, { z13.b }, z8.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0xfb, 0x1f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "tblq z31.b, { z31.b }, z31.b"
diff --git a/tests/MC/AArch64/SVE2p1/tbxq.s.yaml b/tests/MC/AArch64/SVE2p1/tbxq.s.yaml
new file mode 100644
index 000000000..5136a59d6
--- /dev/null
+++ b/tests/MC/AArch64/SVE2p1/tbxq.s.yaml
@@ -0,0 +1,320 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x34, 0x60, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "tbxq z0.h, z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x55, 0x35, 0x75, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "tbxq z21.h, z10.h, z21.h"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x35, 0x68, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "tbxq z23.h, z13.h, z8.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x37, 0x7f, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "tbxq z31.h, z31.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x34, 0xa0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "tbxq z0.s, z0.s, z0.s"
+
+  -
+    input:
+      bytes: [ 0x55, 0x35, 0xb5, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "tbxq z21.s, z10.s, z21.s"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x35, 0xa8, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "tbxq z23.s, z13.s, z8.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0x37, 0xbf, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "tbxq z31.s, z31.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0x34, 0xe0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "tbxq z0.d, z0.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0x55, 0x35, 0xf5, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "tbxq z21.d, z10.d, z21.d"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x35, 0xe8, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "tbxq z23.d, z13.d, z8.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0x37, 0xff, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "tbxq z31.d, z31.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x34, 0x20, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "tbxq z0.b, z0.b, z0.b"
+
+  -
+    input:
+      bytes: [ 0x55, 0x35, 0x35, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "tbxq z21.b, z10.b, z21.b"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x35, 0x28, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "tbxq z23.b, z13.b, z8.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x37, 0x3f, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "tbxq z31.b, z31.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x34, 0x60, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "tbxq z0.h, z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x55, 0x35, 0x75, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "tbxq z21.h, z10.h, z21.h"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x35, 0x68, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "tbxq z23.h, z13.h, z8.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x37, 0x7f, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "tbxq z31.h, z31.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x34, 0xa0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "tbxq z0.s, z0.s, z0.s"
+
+  -
+    input:
+      bytes: [ 0x55, 0x35, 0xb5, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "tbxq z21.s, z10.s, z21.s"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x35, 0xa8, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "tbxq z23.s, z13.s, z8.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0x37, 0xbf, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "tbxq z31.s, z31.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0x34, 0xe0, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "tbxq z0.d, z0.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0x55, 0x35, 0xf5, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "tbxq z21.d, z10.d, z21.d"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x35, 0xe8, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "tbxq z23.d, z13.d, z8.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0x37, 0xff, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "tbxq z31.d, z31.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x34, 0x20, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "tbxq z0.b, z0.b, z0.b"
+
+  -
+    input:
+      bytes: [ 0x55, 0x35, 0x35, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "tbxq z21.b, z10.b, z21.b"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x35, 0x28, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "tbxq z23.b, z13.b, z8.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x37, 0x3f, 0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "tbxq z31.b, z31.b, z31.b"
diff --git a/tests/MC/AArch64/SVE2p1/udot.s.yaml b/tests/MC/AArch64/SVE2p1/udot.s.yaml
new file mode 100644
index 000000000..7b4fd5161
--- /dev/null
+++ b/tests/MC/AArch64/SVE2p1/udot.s.yaml
@@ -0,0 +1,240 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xf7, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z23, z31"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xcd, 0x88, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot z23.s, z13.h, z0.h[1]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xcc, 0x80, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot z0.s, z0.h, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xcd, 0x95, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot z21.s, z10.h, z5.h[2]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xcd, 0x88, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot z23.s, z13.h, z0.h[1]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xcf, 0x9f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot z31.s, z31.h, z7.h[3]"
+
+  -
+    input:
+      bytes: [ 0xf7, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z23, z31"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xcd, 0x08, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot z23.s, z13.h, z8.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0xcc, 0x00, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot z0.s, z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x55, 0xcd, 0x15, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot z21.s, z10.h, z21.h"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xcd, 0x08, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot z23.s, z13.h, z8.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0xcf, 0x1f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot z31.s, z31.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0xf7, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z23, z31"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xcd, 0x88, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot z23.s, z13.h, z0.h[1]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xcc, 0x80, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot z0.s, z0.h, z0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xcd, 0x95, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot z21.s, z10.h, z5.h[2]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xcd, 0x88, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot z23.s, z13.h, z0.h[1]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xcf, 0x9f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot z31.s, z31.h, z7.h[3]"
+
+  -
+    input:
+      bytes: [ 0xf7, 0xbf, 0x20, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "movprfx z23, z31"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xcd, 0x08, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot z23.s, z13.h, z8.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0xcc, 0x00, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot z0.s, z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x55, 0xcd, 0x15, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot z21.s, z10.h, z21.h"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xcd, 0x08, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot z23.s, z13.h, z8.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0xcf, 0x1f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot z31.s, z31.h, z31.h"
diff --git a/tests/MC/AArch64/SVE2p1/umaxqv.s.yaml b/tests/MC/AArch64/SVE2p1/umaxqv.s.yaml
new file mode 100644
index 000000000..8286c2d08
--- /dev/null
+++ b/tests/MC/AArch64/SVE2p1/umaxqv.s.yaml
@@ -0,0 +1,320 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x4d, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "umaxqv v0.8h, p0, z0.h"
+
+  -
+    input:
+      bytes: [ 0x55, 0x35, 0x4d, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "umaxqv v21.8h, p5, z10.h"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x2d, 0x4d, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "umaxqv v23.8h, p3, z13.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0x4d, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "umaxqv v31.8h, p7, z31.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x8d, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "umaxqv v0.4s, p0, z0.s"
+
+  -
+    input:
+      bytes: [ 0x55, 0x35, 0x8d, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "umaxqv v21.4s, p5, z10.s"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x2d, 0x8d, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "umaxqv v23.4s, p3, z13.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0x8d, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "umaxqv v31.4s, p7, z31.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0xcd, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "umaxqv v0.2d, p0, z0.d"
+
+  -
+    input:
+      bytes: [ 0x55, 0x35, 0xcd, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "umaxqv v21.2d, p5, z10.d"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x2d, 0xcd, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "umaxqv v23.2d, p3, z13.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0xcd, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "umaxqv v31.2d, p7, z31.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x0d, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "umaxqv v0.16b, p0, z0.b"
+
+  -
+    input:
+      bytes: [ 0x55, 0x35, 0x0d, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "umaxqv v21.16b, p5, z10.b"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x2d, 0x0d, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "umaxqv v23.16b, p3, z13.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0x0d, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "umaxqv v31.16b, p7, z31.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x4d, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "umaxqv v0.8h, p0, z0.h"
+
+  -
+    input:
+      bytes: [ 0x55, 0x35, 0x4d, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "umaxqv v21.8h, p5, z10.h"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x2d, 0x4d, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "umaxqv v23.8h, p3, z13.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0x4d, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "umaxqv v31.8h, p7, z31.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x8d, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "umaxqv v0.4s, p0, z0.s"
+
+  -
+    input:
+      bytes: [ 0x55, 0x35, 0x8d, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "umaxqv v21.4s, p5, z10.s"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x2d, 0x8d, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "umaxqv v23.4s, p3, z13.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0x8d, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "umaxqv v31.4s, p7, z31.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0xcd, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "umaxqv v0.2d, p0, z0.d"
+
+  -
+    input:
+      bytes: [ 0x55, 0x35, 0xcd, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "umaxqv v21.2d, p5, z10.d"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x2d, 0xcd, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "umaxqv v23.2d, p3, z13.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0xcd, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "umaxqv v31.2d, p7, z31.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x0d, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "umaxqv v0.16b, p0, z0.b"
+
+  -
+    input:
+      bytes: [ 0x55, 0x35, 0x0d, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "umaxqv v21.16b, p5, z10.b"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x2d, 0x0d, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "umaxqv v23.16b, p3, z13.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0x0d, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "umaxqv v31.16b, p7, z31.b"
diff --git a/tests/MC/AArch64/SVE2p1/uminqv.s.yaml b/tests/MC/AArch64/SVE2p1/uminqv.s.yaml
new file mode 100644
index 000000000..5f934f4e5
--- /dev/null
+++ b/tests/MC/AArch64/SVE2p1/uminqv.s.yaml
@@ -0,0 +1,320 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x4f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "uminqv v0.8h, p0, z0.h"
+
+  -
+    input:
+      bytes: [ 0x55, 0x35, 0x4f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "uminqv v21.8h, p5, z10.h"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x2d, 0x4f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "uminqv v23.8h, p3, z13.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0x4f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "uminqv v31.8h, p7, z31.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x8f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "uminqv v0.4s, p0, z0.s"
+
+  -
+    input:
+      bytes: [ 0x55, 0x35, 0x8f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "uminqv v21.4s, p5, z10.s"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x2d, 0x8f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "uminqv v23.4s, p3, z13.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0x8f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "uminqv v31.4s, p7, z31.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0xcf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "uminqv v0.2d, p0, z0.d"
+
+  -
+    input:
+      bytes: [ 0x55, 0x35, 0xcf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "uminqv v21.2d, p5, z10.d"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x2d, 0xcf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "uminqv v23.2d, p3, z13.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0xcf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "uminqv v31.2d, p7, z31.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x0f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "uminqv v0.16b, p0, z0.b"
+
+  -
+    input:
+      bytes: [ 0x55, 0x35, 0x0f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "uminqv v21.16b, p5, z10.b"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x2d, 0x0f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "uminqv v23.16b, p3, z13.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0x0f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "uminqv v31.16b, p7, z31.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x4f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "uminqv v0.8h, p0, z0.h"
+
+  -
+    input:
+      bytes: [ 0x55, 0x35, 0x4f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "uminqv v21.8h, p5, z10.h"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x2d, 0x4f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "uminqv v23.8h, p3, z13.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0x4f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "uminqv v31.8h, p7, z31.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x8f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "uminqv v0.4s, p0, z0.s"
+
+  -
+    input:
+      bytes: [ 0x55, 0x35, 0x8f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "uminqv v21.4s, p5, z10.s"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x2d, 0x8f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "uminqv v23.4s, p3, z13.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0x8f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "uminqv v31.4s, p7, z31.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0xcf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "uminqv v0.2d, p0, z0.d"
+
+  -
+    input:
+      bytes: [ 0x55, 0x35, 0xcf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "uminqv v21.2d, p5, z10.d"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x2d, 0xcf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "uminqv v23.2d, p3, z13.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0xcf, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "uminqv v31.2d, p7, z31.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x0f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "uminqv v0.16b, p0, z0.b"
+
+  -
+    input:
+      bytes: [ 0x55, 0x35, 0x0f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "uminqv v21.16b, p5, z10.b"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x2d, 0x0f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "uminqv v23.16b, p3, z13.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0x0f, 0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "uminqv v31.16b, p7, z31.b"
diff --git a/tests/MC/AArch64/SVE2p1/uqcvtn.s.yaml b/tests/MC/AArch64/SVE2p1/uqcvtn.s.yaml
new file mode 100644
index 000000000..3ee3adc63
--- /dev/null
+++ b/tests/MC/AArch64/SVE2p1/uqcvtn.s.yaml
@@ -0,0 +1,80 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x48, 0x31, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqcvtn z0.h, { z0.s, z1.s }"
+
+  -
+    input:
+      bytes: [ 0x55, 0x49, 0x31, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqcvtn z21.h, { z10.s, z11.s }"
+
+  -
+    input:
+      bytes: [ 0x97, 0x49, 0x31, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqcvtn z23.h, { z12.s, z13.s }"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x4b, 0x31, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqcvtn z31.h, { z30.s, z31.s }"
+
+  -
+    input:
+      bytes: [ 0x00, 0x48, 0x31, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqcvtn z0.h, { z0.s, z1.s }"
+
+  -
+    input:
+      bytes: [ 0x55, 0x49, 0x31, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqcvtn z21.h, { z10.s, z11.s }"
+
+  -
+    input:
+      bytes: [ 0x97, 0x49, 0x31, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqcvtn z23.h, { z12.s, z13.s }"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x4b, 0x31, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqcvtn z31.h, { z30.s, z31.s }"
diff --git a/tests/MC/AArch64/SVE2p1/uqrshrn.s.yaml b/tests/MC/AArch64/SVE2p1/uqrshrn.s.yaml
new file mode 100644
index 000000000..32393c0e5
--- /dev/null
+++ b/tests/MC/AArch64/SVE2p1/uqrshrn.s.yaml
@@ -0,0 +1,80 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x38, 0xb0, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqrshrn z0.h, { z0.s, z1.s }, #16"
+
+  -
+    input:
+      bytes: [ 0x55, 0x39, 0xb5, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqrshrn z21.h, { z10.s, z11.s }, #11"
+
+  -
+    input:
+      bytes: [ 0x97, 0x39, 0xb8, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqrshrn z23.h, { z12.s, z13.s }, #8"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x3b, 0xbf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqrshrn z31.h, { z30.s, z31.s }, #1"
+
+  -
+    input:
+      bytes: [ 0x00, 0x38, 0xb0, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqrshrn z0.h, { z0.s, z1.s }, #16"
+
+  -
+    input:
+      bytes: [ 0x55, 0x39, 0xb5, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqrshrn z21.h, { z10.s, z11.s }, #11"
+
+  -
+    input:
+      bytes: [ 0x97, 0x39, 0xb8, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqrshrn z23.h, { z12.s, z13.s }, #8"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x3b, 0xbf, 0x45 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqrshrn z31.h, { z30.s, z31.s }, #1"
diff --git a/tests/MC/AArch64/SVE2p1/uzpq1.s.yaml b/tests/MC/AArch64/SVE2p1/uzpq1.s.yaml
new file mode 100644
index 000000000..a2822b542
--- /dev/null
+++ b/tests/MC/AArch64/SVE2p1/uzpq1.s.yaml
@@ -0,0 +1,320 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xe8, 0x40, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzpq1 z0.h, z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x55, 0xe9, 0x55, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzpq1 z21.h, z10.h, z21.h"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xe9, 0x48, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzpq1 z23.h, z13.h, z8.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0xeb, 0x5f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzpq1 z31.h, z31.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe8, 0x80, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzpq1 z0.s, z0.s, z0.s"
+
+  -
+    input:
+      bytes: [ 0x55, 0xe9, 0x95, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzpq1 z21.s, z10.s, z21.s"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xe9, 0x88, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzpq1 z23.s, z13.s, z8.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0xeb, 0x9f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzpq1 z31.s, z31.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe8, 0xc0, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzpq1 z0.d, z0.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0x55, 0xe9, 0xd5, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzpq1 z21.d, z10.d, z21.d"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xe9, 0xc8, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzpq1 z23.d, z13.d, z8.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0xeb, 0xdf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzpq1 z31.d, z31.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe8, 0x00, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzpq1 z0.b, z0.b, z0.b"
+
+  -
+    input:
+      bytes: [ 0x55, 0xe9, 0x15, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzpq1 z21.b, z10.b, z21.b"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xe9, 0x08, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzpq1 z23.b, z13.b, z8.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0xeb, 0x1f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzpq1 z31.b, z31.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe8, 0x40, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzpq1 z0.h, z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x55, 0xe9, 0x55, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzpq1 z21.h, z10.h, z21.h"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xe9, 0x48, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzpq1 z23.h, z13.h, z8.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0xeb, 0x5f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzpq1 z31.h, z31.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe8, 0x80, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzpq1 z0.s, z0.s, z0.s"
+
+  -
+    input:
+      bytes: [ 0x55, 0xe9, 0x95, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzpq1 z21.s, z10.s, z21.s"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xe9, 0x88, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzpq1 z23.s, z13.s, z8.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0xeb, 0x9f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzpq1 z31.s, z31.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe8, 0xc0, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzpq1 z0.d, z0.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0x55, 0xe9, 0xd5, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzpq1 z21.d, z10.d, z21.d"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xe9, 0xc8, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzpq1 z23.d, z13.d, z8.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0xeb, 0xdf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzpq1 z31.d, z31.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe8, 0x00, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzpq1 z0.b, z0.b, z0.b"
+
+  -
+    input:
+      bytes: [ 0x55, 0xe9, 0x15, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzpq1 z21.b, z10.b, z21.b"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xe9, 0x08, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzpq1 z23.b, z13.b, z8.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0xeb, 0x1f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzpq1 z31.b, z31.b, z31.b"
diff --git a/tests/MC/AArch64/SVE2p1/uzpq2.s.yaml b/tests/MC/AArch64/SVE2p1/uzpq2.s.yaml
new file mode 100644
index 000000000..cd36b4a52
--- /dev/null
+++ b/tests/MC/AArch64/SVE2p1/uzpq2.s.yaml
@@ -0,0 +1,320 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xec, 0x40, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzpq2 z0.h, z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x55, 0xed, 0x55, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzpq2 z21.h, z10.h, z21.h"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0x48, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzpq2 z23.h, z13.h, z8.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0xef, 0x5f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzpq2 z31.h, z31.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0xec, 0x80, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzpq2 z0.s, z0.s, z0.s"
+
+  -
+    input:
+      bytes: [ 0x55, 0xed, 0x95, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzpq2 z21.s, z10.s, z21.s"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0x88, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzpq2 z23.s, z13.s, z8.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0xef, 0x9f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzpq2 z31.s, z31.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0xec, 0xc0, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzpq2 z0.d, z0.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0x55, 0xed, 0xd5, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzpq2 z21.d, z10.d, z21.d"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0xc8, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzpq2 z23.d, z13.d, z8.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0xef, 0xdf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzpq2 z31.d, z31.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0xec, 0x00, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzpq2 z0.b, z0.b, z0.b"
+
+  -
+    input:
+      bytes: [ 0x55, 0xed, 0x15, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzpq2 z21.b, z10.b, z21.b"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0x08, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzpq2 z23.b, z13.b, z8.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0xef, 0x1f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzpq2 z31.b, z31.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0xec, 0x40, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzpq2 z0.h, z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x55, 0xed, 0x55, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzpq2 z21.h, z10.h, z21.h"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0x48, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzpq2 z23.h, z13.h, z8.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0xef, 0x5f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzpq2 z31.h, z31.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0xec, 0x80, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzpq2 z0.s, z0.s, z0.s"
+
+  -
+    input:
+      bytes: [ 0x55, 0xed, 0x95, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzpq2 z21.s, z10.s, z21.s"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0x88, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzpq2 z23.s, z13.s, z8.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0xef, 0x9f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzpq2 z31.s, z31.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0xec, 0xc0, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzpq2 z0.d, z0.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0x55, 0xed, 0xd5, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzpq2 z21.d, z10.d, z21.d"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0xc8, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzpq2 z23.d, z13.d, z8.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0xef, 0xdf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzpq2 z31.d, z31.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0xec, 0x00, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzpq2 z0.b, z0.b, z0.b"
+
+  -
+    input:
+      bytes: [ 0x55, 0xed, 0x15, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzpq2 z21.b, z10.b, z21.b"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xed, 0x08, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzpq2 z23.b, z13.b, z8.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0xef, 0x1f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzpq2 z31.b, z31.b, z31.b"
diff --git a/tests/MC/AArch64/SVE2p1/whilege.s.yaml b/tests/MC/AArch64/SVE2p1/whilege.s.yaml
new file mode 100644
index 000000000..ada60db90
--- /dev/null
+++ b/tests/MC/AArch64/SVE2p1/whilege.s.yaml
@@ -0,0 +1,640 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x10, 0x40, 0x60, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilege pn8.h, x0, x0, vlx2"
+
+  -
+    input:
+      bytes: [ 0x55, 0x41, 0x75, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilege pn13.h, x10, x21, vlx2"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x61, 0x68, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilege pn15.h, x13, x8, vlx4"
+
+  -
+    input:
+      bytes: [ 0xf7, 0x63, 0x7f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilege pn15.h, xzr, xzr, vlx4"
+
+  -
+    input:
+      bytes: [ 0x10, 0x50, 0x60, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilege { p0.h, p1.h }, x0, x0"
+
+  -
+    input:
+      bytes: [ 0x54, 0x51, 0x75, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilege { p4.h, p5.h }, x10, x21"
+
+  -
+    input:
+      bytes: [ 0xb6, 0x51, 0x68, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilege { p6.h, p7.h }, x13, x8"
+
+  -
+    input:
+      bytes: [ 0xfe, 0x53, 0x7f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilege { p14.h, p15.h }, xzr, xzr"
+
+  -
+    input:
+      bytes: [ 0x10, 0x40, 0xa0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilege pn8.s, x0, x0, vlx2"
+
+  -
+    input:
+      bytes: [ 0x55, 0x41, 0xb5, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilege pn13.s, x10, x21, vlx2"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x61, 0xa8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilege pn15.s, x13, x8, vlx4"
+
+  -
+    input:
+      bytes: [ 0xf7, 0x63, 0xbf, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilege pn15.s, xzr, xzr, vlx4"
+
+  -
+    input:
+      bytes: [ 0x10, 0x50, 0xa0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilege { p0.s, p1.s }, x0, x0"
+
+  -
+    input:
+      bytes: [ 0x54, 0x51, 0xb5, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilege { p4.s, p5.s }, x10, x21"
+
+  -
+    input:
+      bytes: [ 0xb6, 0x51, 0xa8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilege { p6.s, p7.s }, x13, x8"
+
+  -
+    input:
+      bytes: [ 0xfe, 0x53, 0xbf, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilege { p14.s, p15.s }, xzr, xzr"
+
+  -
+    input:
+      bytes: [ 0x10, 0x40, 0xe0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilege pn8.d, x0, x0, vlx2"
+
+  -
+    input:
+      bytes: [ 0x55, 0x41, 0xf5, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilege pn13.d, x10, x21, vlx2"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x61, 0xe8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilege pn15.d, x13, x8, vlx4"
+
+  -
+    input:
+      bytes: [ 0xf7, 0x63, 0xff, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilege pn15.d, xzr, xzr, vlx4"
+
+  -
+    input:
+      bytes: [ 0x10, 0x50, 0xe0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilege { p0.d, p1.d }, x0, x0"
+
+  -
+    input:
+      bytes: [ 0x54, 0x51, 0xf5, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilege { p4.d, p5.d }, x10, x21"
+
+  -
+    input:
+      bytes: [ 0xb6, 0x51, 0xe8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilege { p6.d, p7.d }, x13, x8"
+
+  -
+    input:
+      bytes: [ 0xfe, 0x53, 0xff, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilege { p14.d, p15.d }, xzr, xzr"
+
+  -
+    input:
+      bytes: [ 0x10, 0x40, 0x20, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilege pn8.b, x0, x0, vlx2"
+
+  -
+    input:
+      bytes: [ 0x55, 0x41, 0x35, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilege pn13.b, x10, x21, vlx2"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x61, 0x28, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilege pn15.b, x13, x8, vlx4"
+
+  -
+    input:
+      bytes: [ 0xf7, 0x63, 0x3f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilege pn15.b, xzr, xzr, vlx4"
+
+  -
+    input:
+      bytes: [ 0x10, 0x50, 0x20, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilege { p0.b, p1.b }, x0, x0"
+
+  -
+    input:
+      bytes: [ 0x54, 0x51, 0x35, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilege { p4.b, p5.b }, x10, x21"
+
+  -
+    input:
+      bytes: [ 0xb6, 0x51, 0x28, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilege { p6.b, p7.b }, x13, x8"
+
+  -
+    input:
+      bytes: [ 0xfe, 0x53, 0x3f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilege { p14.b, p15.b }, xzr, xzr"
+
+  -
+    input:
+      bytes: [ 0x10, 0x40, 0x60, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilege pn8.h, x0, x0, vlx2"
+
+  -
+    input:
+      bytes: [ 0x55, 0x41, 0x75, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilege pn13.h, x10, x21, vlx2"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x61, 0x68, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilege pn15.h, x13, x8, vlx4"
+
+  -
+    input:
+      bytes: [ 0xf7, 0x63, 0x7f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilege pn15.h, xzr, xzr, vlx4"
+
+  -
+    input:
+      bytes: [ 0x10, 0x50, 0x60, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilege { p0.h, p1.h }, x0, x0"
+
+  -
+    input:
+      bytes: [ 0x54, 0x51, 0x75, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilege { p4.h, p5.h }, x10, x21"
+
+  -
+    input:
+      bytes: [ 0xb6, 0x51, 0x68, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilege { p6.h, p7.h }, x13, x8"
+
+  -
+    input:
+      bytes: [ 0xfe, 0x53, 0x7f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilege { p14.h, p15.h }, xzr, xzr"
+
+  -
+    input:
+      bytes: [ 0x10, 0x40, 0xa0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilege pn8.s, x0, x0, vlx2"
+
+  -
+    input:
+      bytes: [ 0x55, 0x41, 0xb5, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilege pn13.s, x10, x21, vlx2"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x61, 0xa8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilege pn15.s, x13, x8, vlx4"
+
+  -
+    input:
+      bytes: [ 0xf7, 0x63, 0xbf, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilege pn15.s, xzr, xzr, vlx4"
+
+  -
+    input:
+      bytes: [ 0x10, 0x50, 0xa0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilege { p0.s, p1.s }, x0, x0"
+
+  -
+    input:
+      bytes: [ 0x54, 0x51, 0xb5, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilege { p4.s, p5.s }, x10, x21"
+
+  -
+    input:
+      bytes: [ 0xb6, 0x51, 0xa8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilege { p6.s, p7.s }, x13, x8"
+
+  -
+    input:
+      bytes: [ 0xfe, 0x53, 0xbf, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilege { p14.s, p15.s }, xzr, xzr"
+
+  -
+    input:
+      bytes: [ 0x10, 0x40, 0xe0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilege pn8.d, x0, x0, vlx2"
+
+  -
+    input:
+      bytes: [ 0x55, 0x41, 0xf5, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilege pn13.d, x10, x21, vlx2"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x61, 0xe8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilege pn15.d, x13, x8, vlx4"
+
+  -
+    input:
+      bytes: [ 0xf7, 0x63, 0xff, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilege pn15.d, xzr, xzr, vlx4"
+
+  -
+    input:
+      bytes: [ 0x10, 0x50, 0xe0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilege { p0.d, p1.d }, x0, x0"
+
+  -
+    input:
+      bytes: [ 0x54, 0x51, 0xf5, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilege { p4.d, p5.d }, x10, x21"
+
+  -
+    input:
+      bytes: [ 0xb6, 0x51, 0xe8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilege { p6.d, p7.d }, x13, x8"
+
+  -
+    input:
+      bytes: [ 0xfe, 0x53, 0xff, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilege { p14.d, p15.d }, xzr, xzr"
+
+  -
+    input:
+      bytes: [ 0x10, 0x40, 0x20, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilege pn8.b, x0, x0, vlx2"
+
+  -
+    input:
+      bytes: [ 0x55, 0x41, 0x35, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilege pn13.b, x10, x21, vlx2"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x61, 0x28, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilege pn15.b, x13, x8, vlx4"
+
+  -
+    input:
+      bytes: [ 0xf7, 0x63, 0x3f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilege pn15.b, xzr, xzr, vlx4"
+
+  -
+    input:
+      bytes: [ 0x10, 0x50, 0x20, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilege { p0.b, p1.b }, x0, x0"
+
+  -
+    input:
+      bytes: [ 0x54, 0x51, 0x35, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilege { p4.b, p5.b }, x10, x21"
+
+  -
+    input:
+      bytes: [ 0xb6, 0x51, 0x28, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilege { p6.b, p7.b }, x13, x8"
+
+  -
+    input:
+      bytes: [ 0xfe, 0x53, 0x3f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilege { p14.b, p15.b }, xzr, xzr"
diff --git a/tests/MC/AArch64/SVE2p1/whilegt.s.yaml b/tests/MC/AArch64/SVE2p1/whilegt.s.yaml
new file mode 100644
index 000000000..ab15461ac
--- /dev/null
+++ b/tests/MC/AArch64/SVE2p1/whilegt.s.yaml
@@ -0,0 +1,640 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x18, 0x40, 0x60, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilegt pn8.h, x0, x0, vlx2"
+
+  -
+    input:
+      bytes: [ 0x5d, 0x41, 0x75, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilegt pn13.h, x10, x21, vlx2"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x61, 0x68, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilegt pn15.h, x13, x8, vlx4"
+
+  -
+    input:
+      bytes: [ 0xff, 0x63, 0x7f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilegt pn15.h, xzr, xzr, vlx4"
+
+  -
+    input:
+      bytes: [ 0x11, 0x50, 0x60, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilegt { p0.h, p1.h }, x0, x0"
+
+  -
+    input:
+      bytes: [ 0x55, 0x51, 0x75, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilegt { p4.h, p5.h }, x10, x21"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x51, 0x68, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilegt { p6.h, p7.h }, x13, x8"
+
+  -
+    input:
+      bytes: [ 0xff, 0x53, 0x7f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilegt { p14.h, p15.h }, xzr, xzr"
+
+  -
+    input:
+      bytes: [ 0x18, 0x40, 0xa0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilegt pn8.s, x0, x0, vlx2"
+
+  -
+    input:
+      bytes: [ 0x5d, 0x41, 0xb5, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilegt pn13.s, x10, x21, vlx2"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x61, 0xa8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilegt pn15.s, x13, x8, vlx4"
+
+  -
+    input:
+      bytes: [ 0xff, 0x63, 0xbf, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilegt pn15.s, xzr, xzr, vlx4"
+
+  -
+    input:
+      bytes: [ 0x11, 0x50, 0xa0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilegt { p0.s, p1.s }, x0, x0"
+
+  -
+    input:
+      bytes: [ 0x55, 0x51, 0xb5, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilegt { p4.s, p5.s }, x10, x21"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x51, 0xa8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilegt { p6.s, p7.s }, x13, x8"
+
+  -
+    input:
+      bytes: [ 0xff, 0x53, 0xbf, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilegt { p14.s, p15.s }, xzr, xzr"
+
+  -
+    input:
+      bytes: [ 0x18, 0x40, 0xe0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilegt pn8.d, x0, x0, vlx2"
+
+  -
+    input:
+      bytes: [ 0x5d, 0x41, 0xf5, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilegt pn13.d, x10, x21, vlx2"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x61, 0xe8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilegt pn15.d, x13, x8, vlx4"
+
+  -
+    input:
+      bytes: [ 0xff, 0x63, 0xff, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilegt pn15.d, xzr, xzr, vlx4"
+
+  -
+    input:
+      bytes: [ 0x11, 0x50, 0xe0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilegt { p0.d, p1.d }, x0, x0"
+
+  -
+    input:
+      bytes: [ 0x55, 0x51, 0xf5, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilegt { p4.d, p5.d }, x10, x21"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x51, 0xe8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilegt { p6.d, p7.d }, x13, x8"
+
+  -
+    input:
+      bytes: [ 0xff, 0x53, 0xff, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilegt { p14.d, p15.d }, xzr, xzr"
+
+  -
+    input:
+      bytes: [ 0x18, 0x40, 0x20, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilegt pn8.b, x0, x0, vlx2"
+
+  -
+    input:
+      bytes: [ 0x5d, 0x41, 0x35, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilegt pn13.b, x10, x21, vlx2"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x61, 0x28, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilegt pn15.b, x13, x8, vlx4"
+
+  -
+    input:
+      bytes: [ 0xff, 0x63, 0x3f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilegt pn15.b, xzr, xzr, vlx4"
+
+  -
+    input:
+      bytes: [ 0x11, 0x50, 0x20, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilegt { p0.b, p1.b }, x0, x0"
+
+  -
+    input:
+      bytes: [ 0x55, 0x51, 0x35, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilegt { p4.b, p5.b }, x10, x21"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x51, 0x28, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilegt { p6.b, p7.b }, x13, x8"
+
+  -
+    input:
+      bytes: [ 0xff, 0x53, 0x3f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilegt { p14.b, p15.b }, xzr, xzr"
+
+  -
+    input:
+      bytes: [ 0x18, 0x40, 0x60, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilegt pn8.h, x0, x0, vlx2"
+
+  -
+    input:
+      bytes: [ 0x5d, 0x41, 0x75, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilegt pn13.h, x10, x21, vlx2"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x61, 0x68, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilegt pn15.h, x13, x8, vlx4"
+
+  -
+    input:
+      bytes: [ 0xff, 0x63, 0x7f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilegt pn15.h, xzr, xzr, vlx4"
+
+  -
+    input:
+      bytes: [ 0x11, 0x50, 0x60, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilegt { p0.h, p1.h }, x0, x0"
+
+  -
+    input:
+      bytes: [ 0x55, 0x51, 0x75, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilegt { p4.h, p5.h }, x10, x21"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x51, 0x68, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilegt { p6.h, p7.h }, x13, x8"
+
+  -
+    input:
+      bytes: [ 0xff, 0x53, 0x7f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilegt { p14.h, p15.h }, xzr, xzr"
+
+  -
+    input:
+      bytes: [ 0x18, 0x40, 0xa0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilegt pn8.s, x0, x0, vlx2"
+
+  -
+    input:
+      bytes: [ 0x5d, 0x41, 0xb5, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilegt pn13.s, x10, x21, vlx2"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x61, 0xa8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilegt pn15.s, x13, x8, vlx4"
+
+  -
+    input:
+      bytes: [ 0xff, 0x63, 0xbf, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilegt pn15.s, xzr, xzr, vlx4"
+
+  -
+    input:
+      bytes: [ 0x11, 0x50, 0xa0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilegt { p0.s, p1.s }, x0, x0"
+
+  -
+    input:
+      bytes: [ 0x55, 0x51, 0xb5, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilegt { p4.s, p5.s }, x10, x21"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x51, 0xa8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilegt { p6.s, p7.s }, x13, x8"
+
+  -
+    input:
+      bytes: [ 0xff, 0x53, 0xbf, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilegt { p14.s, p15.s }, xzr, xzr"
+
+  -
+    input:
+      bytes: [ 0x18, 0x40, 0xe0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilegt pn8.d, x0, x0, vlx2"
+
+  -
+    input:
+      bytes: [ 0x5d, 0x41, 0xf5, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilegt pn13.d, x10, x21, vlx2"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x61, 0xe8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilegt pn15.d, x13, x8, vlx4"
+
+  -
+    input:
+      bytes: [ 0xff, 0x63, 0xff, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilegt pn15.d, xzr, xzr, vlx4"
+
+  -
+    input:
+      bytes: [ 0x11, 0x50, 0xe0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilegt { p0.d, p1.d }, x0, x0"
+
+  -
+    input:
+      bytes: [ 0x55, 0x51, 0xf5, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilegt { p4.d, p5.d }, x10, x21"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x51, 0xe8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilegt { p6.d, p7.d }, x13, x8"
+
+  -
+    input:
+      bytes: [ 0xff, 0x53, 0xff, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilegt { p14.d, p15.d }, xzr, xzr"
+
+  -
+    input:
+      bytes: [ 0x18, 0x40, 0x20, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilegt pn8.b, x0, x0, vlx2"
+
+  -
+    input:
+      bytes: [ 0x5d, 0x41, 0x35, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilegt pn13.b, x10, x21, vlx2"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x61, 0x28, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilegt pn15.b, x13, x8, vlx4"
+
+  -
+    input:
+      bytes: [ 0xff, 0x63, 0x3f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilegt pn15.b, xzr, xzr, vlx4"
+
+  -
+    input:
+      bytes: [ 0x11, 0x50, 0x20, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilegt { p0.b, p1.b }, x0, x0"
+
+  -
+    input:
+      bytes: [ 0x55, 0x51, 0x35, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilegt { p4.b, p5.b }, x10, x21"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x51, 0x28, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilegt { p6.b, p7.b }, x13, x8"
+
+  -
+    input:
+      bytes: [ 0xff, 0x53, 0x3f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilegt { p14.b, p15.b }, xzr, xzr"
diff --git a/tests/MC/AArch64/SVE2p1/whilehi.s.yaml b/tests/MC/AArch64/SVE2p1/whilehi.s.yaml
new file mode 100644
index 000000000..063d586b6
--- /dev/null
+++ b/tests/MC/AArch64/SVE2p1/whilehi.s.yaml
@@ -0,0 +1,640 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x18, 0x48, 0x60, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehi pn8.h, x0, x0, vlx2"
+
+  -
+    input:
+      bytes: [ 0x5d, 0x49, 0x75, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehi pn13.h, x10, x21, vlx2"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x69, 0x68, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehi pn15.h, x13, x8, vlx4"
+
+  -
+    input:
+      bytes: [ 0xff, 0x6b, 0x7f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehi pn15.h, xzr, xzr, vlx4"
+
+  -
+    input:
+      bytes: [ 0x11, 0x58, 0x60, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehi { p0.h, p1.h }, x0, x0"
+
+  -
+    input:
+      bytes: [ 0x55, 0x59, 0x75, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehi { p4.h, p5.h }, x10, x21"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x59, 0x68, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehi { p6.h, p7.h }, x13, x8"
+
+  -
+    input:
+      bytes: [ 0xff, 0x5b, 0x7f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehi { p14.h, p15.h }, xzr, xzr"
+
+  -
+    input:
+      bytes: [ 0x18, 0x48, 0xa0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehi pn8.s, x0, x0, vlx2"
+
+  -
+    input:
+      bytes: [ 0x5d, 0x49, 0xb5, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehi pn13.s, x10, x21, vlx2"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x69, 0xa8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehi pn15.s, x13, x8, vlx4"
+
+  -
+    input:
+      bytes: [ 0xff, 0x6b, 0xbf, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehi pn15.s, xzr, xzr, vlx4"
+
+  -
+    input:
+      bytes: [ 0x11, 0x58, 0xa0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehi { p0.s, p1.s }, x0, x0"
+
+  -
+    input:
+      bytes: [ 0x55, 0x59, 0xb5, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehi { p4.s, p5.s }, x10, x21"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x59, 0xa8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehi { p6.s, p7.s }, x13, x8"
+
+  -
+    input:
+      bytes: [ 0xff, 0x5b, 0xbf, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehi { p14.s, p15.s }, xzr, xzr"
+
+  -
+    input:
+      bytes: [ 0x18, 0x48, 0xe0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehi pn8.d, x0, x0, vlx2"
+
+  -
+    input:
+      bytes: [ 0x5d, 0x49, 0xf5, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehi pn13.d, x10, x21, vlx2"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x69, 0xe8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehi pn15.d, x13, x8, vlx4"
+
+  -
+    input:
+      bytes: [ 0xff, 0x6b, 0xff, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehi pn15.d, xzr, xzr, vlx4"
+
+  -
+    input:
+      bytes: [ 0x11, 0x58, 0xe0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehi { p0.d, p1.d }, x0, x0"
+
+  -
+    input:
+      bytes: [ 0x55, 0x59, 0xf5, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehi { p4.d, p5.d }, x10, x21"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x59, 0xe8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehi { p6.d, p7.d }, x13, x8"
+
+  -
+    input:
+      bytes: [ 0xff, 0x5b, 0xff, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehi { p14.d, p15.d }, xzr, xzr"
+
+  -
+    input:
+      bytes: [ 0x18, 0x48, 0x20, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehi pn8.b, x0, x0, vlx2"
+
+  -
+    input:
+      bytes: [ 0x5d, 0x49, 0x35, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehi pn13.b, x10, x21, vlx2"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x69, 0x28, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehi pn15.b, x13, x8, vlx4"
+
+  -
+    input:
+      bytes: [ 0xff, 0x6b, 0x3f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehi pn15.b, xzr, xzr, vlx4"
+
+  -
+    input:
+      bytes: [ 0x11, 0x58, 0x20, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehi { p0.b, p1.b }, x0, x0"
+
+  -
+    input:
+      bytes: [ 0x55, 0x59, 0x35, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehi { p4.b, p5.b }, x10, x21"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x59, 0x28, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehi { p6.b, p7.b }, x13, x8"
+
+  -
+    input:
+      bytes: [ 0xff, 0x5b, 0x3f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehi { p14.b, p15.b }, xzr, xzr"
+
+  -
+    input:
+      bytes: [ 0x18, 0x48, 0x60, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehi pn8.h, x0, x0, vlx2"
+
+  -
+    input:
+      bytes: [ 0x5d, 0x49, 0x75, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehi pn13.h, x10, x21, vlx2"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x69, 0x68, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehi pn15.h, x13, x8, vlx4"
+
+  -
+    input:
+      bytes: [ 0xff, 0x6b, 0x7f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehi pn15.h, xzr, xzr, vlx4"
+
+  -
+    input:
+      bytes: [ 0x11, 0x58, 0x60, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehi { p0.h, p1.h }, x0, x0"
+
+  -
+    input:
+      bytes: [ 0x55, 0x59, 0x75, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehi { p4.h, p5.h }, x10, x21"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x59, 0x68, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehi { p6.h, p7.h }, x13, x8"
+
+  -
+    input:
+      bytes: [ 0xff, 0x5b, 0x7f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehi { p14.h, p15.h }, xzr, xzr"
+
+  -
+    input:
+      bytes: [ 0x18, 0x48, 0xa0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehi pn8.s, x0, x0, vlx2"
+
+  -
+    input:
+      bytes: [ 0x5d, 0x49, 0xb5, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehi pn13.s, x10, x21, vlx2"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x69, 0xa8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehi pn15.s, x13, x8, vlx4"
+
+  -
+    input:
+      bytes: [ 0xff, 0x6b, 0xbf, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehi pn15.s, xzr, xzr, vlx4"
+
+  -
+    input:
+      bytes: [ 0x11, 0x58, 0xa0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehi { p0.s, p1.s }, x0, x0"
+
+  -
+    input:
+      bytes: [ 0x55, 0x59, 0xb5, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehi { p4.s, p5.s }, x10, x21"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x59, 0xa8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehi { p6.s, p7.s }, x13, x8"
+
+  -
+    input:
+      bytes: [ 0xff, 0x5b, 0xbf, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehi { p14.s, p15.s }, xzr, xzr"
+
+  -
+    input:
+      bytes: [ 0x18, 0x48, 0xe0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehi pn8.d, x0, x0, vlx2"
+
+  -
+    input:
+      bytes: [ 0x5d, 0x49, 0xf5, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehi pn13.d, x10, x21, vlx2"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x69, 0xe8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehi pn15.d, x13, x8, vlx4"
+
+  -
+    input:
+      bytes: [ 0xff, 0x6b, 0xff, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehi pn15.d, xzr, xzr, vlx4"
+
+  -
+    input:
+      bytes: [ 0x11, 0x58, 0xe0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehi { p0.d, p1.d }, x0, x0"
+
+  -
+    input:
+      bytes: [ 0x55, 0x59, 0xf5, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehi { p4.d, p5.d }, x10, x21"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x59, 0xe8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehi { p6.d, p7.d }, x13, x8"
+
+  -
+    input:
+      bytes: [ 0xff, 0x5b, 0xff, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehi { p14.d, p15.d }, xzr, xzr"
+
+  -
+    input:
+      bytes: [ 0x18, 0x48, 0x20, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehi pn8.b, x0, x0, vlx2"
+
+  -
+    input:
+      bytes: [ 0x5d, 0x49, 0x35, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehi pn13.b, x10, x21, vlx2"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x69, 0x28, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehi pn15.b, x13, x8, vlx4"
+
+  -
+    input:
+      bytes: [ 0xff, 0x6b, 0x3f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehi pn15.b, xzr, xzr, vlx4"
+
+  -
+    input:
+      bytes: [ 0x11, 0x58, 0x20, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehi { p0.b, p1.b }, x0, x0"
+
+  -
+    input:
+      bytes: [ 0x55, 0x59, 0x35, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehi { p4.b, p5.b }, x10, x21"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x59, 0x28, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehi { p6.b, p7.b }, x13, x8"
+
+  -
+    input:
+      bytes: [ 0xff, 0x5b, 0x3f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehi { p14.b, p15.b }, xzr, xzr"
diff --git a/tests/MC/AArch64/SVE2p1/whilehs.s.yaml b/tests/MC/AArch64/SVE2p1/whilehs.s.yaml
new file mode 100644
index 000000000..ddd506979
--- /dev/null
+++ b/tests/MC/AArch64/SVE2p1/whilehs.s.yaml
@@ -0,0 +1,640 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x10, 0x48, 0x60, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehs pn8.h, x0, x0, vlx2"
+
+  -
+    input:
+      bytes: [ 0x55, 0x49, 0x75, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehs pn13.h, x10, x21, vlx2"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x69, 0x68, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehs pn15.h, x13, x8, vlx4"
+
+  -
+    input:
+      bytes: [ 0xf7, 0x6b, 0x7f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehs pn15.h, xzr, xzr, vlx4"
+
+  -
+    input:
+      bytes: [ 0x10, 0x58, 0x60, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehs { p0.h, p1.h }, x0, x0"
+
+  -
+    input:
+      bytes: [ 0x54, 0x59, 0x75, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehs { p4.h, p5.h }, x10, x21"
+
+  -
+    input:
+      bytes: [ 0xb6, 0x59, 0x68, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehs { p6.h, p7.h }, x13, x8"
+
+  -
+    input:
+      bytes: [ 0xfe, 0x5b, 0x7f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehs { p14.h, p15.h }, xzr, xzr"
+
+  -
+    input:
+      bytes: [ 0x10, 0x48, 0xa0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehs pn8.s, x0, x0, vlx2"
+
+  -
+    input:
+      bytes: [ 0x55, 0x49, 0xb5, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehs pn13.s, x10, x21, vlx2"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x69, 0xa8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehs pn15.s, x13, x8, vlx4"
+
+  -
+    input:
+      bytes: [ 0xf7, 0x6b, 0xbf, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehs pn15.s, xzr, xzr, vlx4"
+
+  -
+    input:
+      bytes: [ 0x10, 0x58, 0xa0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehs { p0.s, p1.s }, x0, x0"
+
+  -
+    input:
+      bytes: [ 0x54, 0x59, 0xb5, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehs { p4.s, p5.s }, x10, x21"
+
+  -
+    input:
+      bytes: [ 0xb6, 0x59, 0xa8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehs { p6.s, p7.s }, x13, x8"
+
+  -
+    input:
+      bytes: [ 0xfe, 0x5b, 0xbf, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehs { p14.s, p15.s }, xzr, xzr"
+
+  -
+    input:
+      bytes: [ 0x10, 0x48, 0xe0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehs pn8.d, x0, x0, vlx2"
+
+  -
+    input:
+      bytes: [ 0x55, 0x49, 0xf5, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehs pn13.d, x10, x21, vlx2"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x69, 0xe8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehs pn15.d, x13, x8, vlx4"
+
+  -
+    input:
+      bytes: [ 0xf7, 0x6b, 0xff, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehs pn15.d, xzr, xzr, vlx4"
+
+  -
+    input:
+      bytes: [ 0x10, 0x58, 0xe0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehs { p0.d, p1.d }, x0, x0"
+
+  -
+    input:
+      bytes: [ 0x54, 0x59, 0xf5, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehs { p4.d, p5.d }, x10, x21"
+
+  -
+    input:
+      bytes: [ 0xb6, 0x59, 0xe8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehs { p6.d, p7.d }, x13, x8"
+
+  -
+    input:
+      bytes: [ 0xfe, 0x5b, 0xff, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehs { p14.d, p15.d }, xzr, xzr"
+
+  -
+    input:
+      bytes: [ 0x10, 0x48, 0x20, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehs pn8.b, x0, x0, vlx2"
+
+  -
+    input:
+      bytes: [ 0x55, 0x49, 0x35, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehs pn13.b, x10, x21, vlx2"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x69, 0x28, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehs pn15.b, x13, x8, vlx4"
+
+  -
+    input:
+      bytes: [ 0xf7, 0x6b, 0x3f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehs pn15.b, xzr, xzr, vlx4"
+
+  -
+    input:
+      bytes: [ 0x10, 0x58, 0x20, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehs { p0.b, p1.b }, x0, x0"
+
+  -
+    input:
+      bytes: [ 0x54, 0x59, 0x35, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehs { p4.b, p5.b }, x10, x21"
+
+  -
+    input:
+      bytes: [ 0xb6, 0x59, 0x28, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehs { p6.b, p7.b }, x13, x8"
+
+  -
+    input:
+      bytes: [ 0xfe, 0x5b, 0x3f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehs { p14.b, p15.b }, xzr, xzr"
+
+  -
+    input:
+      bytes: [ 0x10, 0x48, 0x60, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehs pn8.h, x0, x0, vlx2"
+
+  -
+    input:
+      bytes: [ 0x55, 0x49, 0x75, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehs pn13.h, x10, x21, vlx2"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x69, 0x68, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehs pn15.h, x13, x8, vlx4"
+
+  -
+    input:
+      bytes: [ 0xf7, 0x6b, 0x7f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehs pn15.h, xzr, xzr, vlx4"
+
+  -
+    input:
+      bytes: [ 0x10, 0x58, 0x60, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehs { p0.h, p1.h }, x0, x0"
+
+  -
+    input:
+      bytes: [ 0x54, 0x59, 0x75, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehs { p4.h, p5.h }, x10, x21"
+
+  -
+    input:
+      bytes: [ 0xb6, 0x59, 0x68, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehs { p6.h, p7.h }, x13, x8"
+
+  -
+    input:
+      bytes: [ 0xfe, 0x5b, 0x7f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehs { p14.h, p15.h }, xzr, xzr"
+
+  -
+    input:
+      bytes: [ 0x10, 0x48, 0xa0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehs pn8.s, x0, x0, vlx2"
+
+  -
+    input:
+      bytes: [ 0x55, 0x49, 0xb5, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehs pn13.s, x10, x21, vlx2"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x69, 0xa8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehs pn15.s, x13, x8, vlx4"
+
+  -
+    input:
+      bytes: [ 0xf7, 0x6b, 0xbf, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehs pn15.s, xzr, xzr, vlx4"
+
+  -
+    input:
+      bytes: [ 0x10, 0x58, 0xa0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehs { p0.s, p1.s }, x0, x0"
+
+  -
+    input:
+      bytes: [ 0x54, 0x59, 0xb5, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehs { p4.s, p5.s }, x10, x21"
+
+  -
+    input:
+      bytes: [ 0xb6, 0x59, 0xa8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehs { p6.s, p7.s }, x13, x8"
+
+  -
+    input:
+      bytes: [ 0xfe, 0x5b, 0xbf, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehs { p14.s, p15.s }, xzr, xzr"
+
+  -
+    input:
+      bytes: [ 0x10, 0x48, 0xe0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehs pn8.d, x0, x0, vlx2"
+
+  -
+    input:
+      bytes: [ 0x55, 0x49, 0xf5, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehs pn13.d, x10, x21, vlx2"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x69, 0xe8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehs pn15.d, x13, x8, vlx4"
+
+  -
+    input:
+      bytes: [ 0xf7, 0x6b, 0xff, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehs pn15.d, xzr, xzr, vlx4"
+
+  -
+    input:
+      bytes: [ 0x10, 0x58, 0xe0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehs { p0.d, p1.d }, x0, x0"
+
+  -
+    input:
+      bytes: [ 0x54, 0x59, 0xf5, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehs { p4.d, p5.d }, x10, x21"
+
+  -
+    input:
+      bytes: [ 0xb6, 0x59, 0xe8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehs { p6.d, p7.d }, x13, x8"
+
+  -
+    input:
+      bytes: [ 0xfe, 0x5b, 0xff, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehs { p14.d, p15.d }, xzr, xzr"
+
+  -
+    input:
+      bytes: [ 0x10, 0x48, 0x20, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehs pn8.b, x0, x0, vlx2"
+
+  -
+    input:
+      bytes: [ 0x55, 0x49, 0x35, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehs pn13.b, x10, x21, vlx2"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x69, 0x28, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehs pn15.b, x13, x8, vlx4"
+
+  -
+    input:
+      bytes: [ 0xf7, 0x6b, 0x3f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehs pn15.b, xzr, xzr, vlx4"
+
+  -
+    input:
+      bytes: [ 0x10, 0x58, 0x20, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehs { p0.b, p1.b }, x0, x0"
+
+  -
+    input:
+      bytes: [ 0x54, 0x59, 0x35, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehs { p4.b, p5.b }, x10, x21"
+
+  -
+    input:
+      bytes: [ 0xb6, 0x59, 0x28, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehs { p6.b, p7.b }, x13, x8"
+
+  -
+    input:
+      bytes: [ 0xfe, 0x5b, 0x3f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilehs { p14.b, p15.b }, xzr, xzr"
diff --git a/tests/MC/AArch64/SVE2p1/whilele.s.yaml b/tests/MC/AArch64/SVE2p1/whilele.s.yaml
new file mode 100644
index 000000000..25db92327
--- /dev/null
+++ b/tests/MC/AArch64/SVE2p1/whilele.s.yaml
@@ -0,0 +1,640 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x18, 0x44, 0x60, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilele pn8.h, x0, x0, vlx2"
+
+  -
+    input:
+      bytes: [ 0x5d, 0x45, 0x75, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilele pn13.h, x10, x21, vlx2"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x65, 0x68, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilele pn15.h, x13, x8, vlx4"
+
+  -
+    input:
+      bytes: [ 0xff, 0x67, 0x7f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilele pn15.h, xzr, xzr, vlx4"
+
+  -
+    input:
+      bytes: [ 0x11, 0x54, 0x60, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilele { p0.h, p1.h }, x0, x0"
+
+  -
+    input:
+      bytes: [ 0x55, 0x55, 0x75, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilele { p4.h, p5.h }, x10, x21"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x55, 0x68, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilele { p6.h, p7.h }, x13, x8"
+
+  -
+    input:
+      bytes: [ 0xff, 0x57, 0x7f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilele { p14.h, p15.h }, xzr, xzr"
+
+  -
+    input:
+      bytes: [ 0x18, 0x44, 0xa0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilele pn8.s, x0, x0, vlx2"
+
+  -
+    input:
+      bytes: [ 0x5d, 0x45, 0xb5, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilele pn13.s, x10, x21, vlx2"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x65, 0xa8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilele pn15.s, x13, x8, vlx4"
+
+  -
+    input:
+      bytes: [ 0xff, 0x67, 0xbf, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilele pn15.s, xzr, xzr, vlx4"
+
+  -
+    input:
+      bytes: [ 0x11, 0x54, 0xa0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilele { p0.s, p1.s }, x0, x0"
+
+  -
+    input:
+      bytes: [ 0x55, 0x55, 0xb5, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilele { p4.s, p5.s }, x10, x21"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x55, 0xa8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilele { p6.s, p7.s }, x13, x8"
+
+  -
+    input:
+      bytes: [ 0xff, 0x57, 0xbf, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilele { p14.s, p15.s }, xzr, xzr"
+
+  -
+    input:
+      bytes: [ 0x18, 0x44, 0xe0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilele pn8.d, x0, x0, vlx2"
+
+  -
+    input:
+      bytes: [ 0x5d, 0x45, 0xf5, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilele pn13.d, x10, x21, vlx2"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x65, 0xe8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilele pn15.d, x13, x8, vlx4"
+
+  -
+    input:
+      bytes: [ 0xff, 0x67, 0xff, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilele pn15.d, xzr, xzr, vlx4"
+
+  -
+    input:
+      bytes: [ 0x11, 0x54, 0xe0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilele { p0.d, p1.d }, x0, x0"
+
+  -
+    input:
+      bytes: [ 0x55, 0x55, 0xf5, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilele { p4.d, p5.d }, x10, x21"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x55, 0xe8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilele { p6.d, p7.d }, x13, x8"
+
+  -
+    input:
+      bytes: [ 0xff, 0x57, 0xff, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilele { p14.d, p15.d }, xzr, xzr"
+
+  -
+    input:
+      bytes: [ 0x18, 0x44, 0x20, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilele pn8.b, x0, x0, vlx2"
+
+  -
+    input:
+      bytes: [ 0x5d, 0x45, 0x35, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilele pn13.b, x10, x21, vlx2"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x65, 0x28, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilele pn15.b, x13, x8, vlx4"
+
+  -
+    input:
+      bytes: [ 0xff, 0x67, 0x3f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilele pn15.b, xzr, xzr, vlx4"
+
+  -
+    input:
+      bytes: [ 0x11, 0x54, 0x20, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilele { p0.b, p1.b }, x0, x0"
+
+  -
+    input:
+      bytes: [ 0x55, 0x55, 0x35, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilele { p4.b, p5.b }, x10, x21"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x55, 0x28, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilele { p6.b, p7.b }, x13, x8"
+
+  -
+    input:
+      bytes: [ 0xff, 0x57, 0x3f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilele { p14.b, p15.b }, xzr, xzr"
+
+  -
+    input:
+      bytes: [ 0x18, 0x44, 0x60, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilele pn8.h, x0, x0, vlx2"
+
+  -
+    input:
+      bytes: [ 0x5d, 0x45, 0x75, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilele pn13.h, x10, x21, vlx2"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x65, 0x68, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilele pn15.h, x13, x8, vlx4"
+
+  -
+    input:
+      bytes: [ 0xff, 0x67, 0x7f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilele pn15.h, xzr, xzr, vlx4"
+
+  -
+    input:
+      bytes: [ 0x11, 0x54, 0x60, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilele { p0.h, p1.h }, x0, x0"
+
+  -
+    input:
+      bytes: [ 0x55, 0x55, 0x75, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilele { p4.h, p5.h }, x10, x21"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x55, 0x68, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilele { p6.h, p7.h }, x13, x8"
+
+  -
+    input:
+      bytes: [ 0xff, 0x57, 0x7f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilele { p14.h, p15.h }, xzr, xzr"
+
+  -
+    input:
+      bytes: [ 0x18, 0x44, 0xa0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilele pn8.s, x0, x0, vlx2"
+
+  -
+    input:
+      bytes: [ 0x5d, 0x45, 0xb5, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilele pn13.s, x10, x21, vlx2"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x65, 0xa8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilele pn15.s, x13, x8, vlx4"
+
+  -
+    input:
+      bytes: [ 0xff, 0x67, 0xbf, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilele pn15.s, xzr, xzr, vlx4"
+
+  -
+    input:
+      bytes: [ 0x11, 0x54, 0xa0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilele { p0.s, p1.s }, x0, x0"
+
+  -
+    input:
+      bytes: [ 0x55, 0x55, 0xb5, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilele { p4.s, p5.s }, x10, x21"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x55, 0xa8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilele { p6.s, p7.s }, x13, x8"
+
+  -
+    input:
+      bytes: [ 0xff, 0x57, 0xbf, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilele { p14.s, p15.s }, xzr, xzr"
+
+  -
+    input:
+      bytes: [ 0x18, 0x44, 0xe0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilele pn8.d, x0, x0, vlx2"
+
+  -
+    input:
+      bytes: [ 0x5d, 0x45, 0xf5, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilele pn13.d, x10, x21, vlx2"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x65, 0xe8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilele pn15.d, x13, x8, vlx4"
+
+  -
+    input:
+      bytes: [ 0xff, 0x67, 0xff, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilele pn15.d, xzr, xzr, vlx4"
+
+  -
+    input:
+      bytes: [ 0x11, 0x54, 0xe0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilele { p0.d, p1.d }, x0, x0"
+
+  -
+    input:
+      bytes: [ 0x55, 0x55, 0xf5, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilele { p4.d, p5.d }, x10, x21"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x55, 0xe8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilele { p6.d, p7.d }, x13, x8"
+
+  -
+    input:
+      bytes: [ 0xff, 0x57, 0xff, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilele { p14.d, p15.d }, xzr, xzr"
+
+  -
+    input:
+      bytes: [ 0x18, 0x44, 0x20, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilele pn8.b, x0, x0, vlx2"
+
+  -
+    input:
+      bytes: [ 0x5d, 0x45, 0x35, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilele pn13.b, x10, x21, vlx2"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x65, 0x28, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilele pn15.b, x13, x8, vlx4"
+
+  -
+    input:
+      bytes: [ 0xff, 0x67, 0x3f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilele pn15.b, xzr, xzr, vlx4"
+
+  -
+    input:
+      bytes: [ 0x11, 0x54, 0x20, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilele { p0.b, p1.b }, x0, x0"
+
+  -
+    input:
+      bytes: [ 0x55, 0x55, 0x35, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilele { p4.b, p5.b }, x10, x21"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x55, 0x28, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilele { p6.b, p7.b }, x13, x8"
+
+  -
+    input:
+      bytes: [ 0xff, 0x57, 0x3f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilele { p14.b, p15.b }, xzr, xzr"
diff --git a/tests/MC/AArch64/SVE2p1/whilelo.s.yaml b/tests/MC/AArch64/SVE2p1/whilelo.s.yaml
new file mode 100644
index 000000000..578939c13
--- /dev/null
+++ b/tests/MC/AArch64/SVE2p1/whilelo.s.yaml
@@ -0,0 +1,640 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x10, 0x4c, 0x60, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelo pn8.h, x0, x0, vlx2"
+
+  -
+    input:
+      bytes: [ 0x55, 0x4d, 0x75, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelo pn13.h, x10, x21, vlx2"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x6d, 0x68, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelo pn15.h, x13, x8, vlx4"
+
+  -
+    input:
+      bytes: [ 0xf7, 0x6f, 0x7f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelo pn15.h, xzr, xzr, vlx4"
+
+  -
+    input:
+      bytes: [ 0x10, 0x5c, 0x60, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelo { p0.h, p1.h }, x0, x0"
+
+  -
+    input:
+      bytes: [ 0x54, 0x5d, 0x75, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelo { p4.h, p5.h }, x10, x21"
+
+  -
+    input:
+      bytes: [ 0xb6, 0x5d, 0x68, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelo { p6.h, p7.h }, x13, x8"
+
+  -
+    input:
+      bytes: [ 0xfe, 0x5f, 0x7f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelo { p14.h, p15.h }, xzr, xzr"
+
+  -
+    input:
+      bytes: [ 0x10, 0x4c, 0xa0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelo pn8.s, x0, x0, vlx2"
+
+  -
+    input:
+      bytes: [ 0x55, 0x4d, 0xb5, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelo pn13.s, x10, x21, vlx2"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x6d, 0xa8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelo pn15.s, x13, x8, vlx4"
+
+  -
+    input:
+      bytes: [ 0xf7, 0x6f, 0xbf, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelo pn15.s, xzr, xzr, vlx4"
+
+  -
+    input:
+      bytes: [ 0x10, 0x5c, 0xa0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelo { p0.s, p1.s }, x0, x0"
+
+  -
+    input:
+      bytes: [ 0x54, 0x5d, 0xb5, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelo { p4.s, p5.s }, x10, x21"
+
+  -
+    input:
+      bytes: [ 0xb6, 0x5d, 0xa8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelo { p6.s, p7.s }, x13, x8"
+
+  -
+    input:
+      bytes: [ 0xfe, 0x5f, 0xbf, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelo { p14.s, p15.s }, xzr, xzr"
+
+  -
+    input:
+      bytes: [ 0x10, 0x4c, 0xe0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelo pn8.d, x0, x0, vlx2"
+
+  -
+    input:
+      bytes: [ 0x55, 0x4d, 0xf5, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelo pn13.d, x10, x21, vlx2"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x6d, 0xe8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelo pn15.d, x13, x8, vlx4"
+
+  -
+    input:
+      bytes: [ 0xf7, 0x6f, 0xff, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelo pn15.d, xzr, xzr, vlx4"
+
+  -
+    input:
+      bytes: [ 0x10, 0x5c, 0xe0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelo { p0.d, p1.d }, x0, x0"
+
+  -
+    input:
+      bytes: [ 0x54, 0x5d, 0xf5, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelo { p4.d, p5.d }, x10, x21"
+
+  -
+    input:
+      bytes: [ 0xb6, 0x5d, 0xe8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelo { p6.d, p7.d }, x13, x8"
+
+  -
+    input:
+      bytes: [ 0xfe, 0x5f, 0xff, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelo { p14.d, p15.d }, xzr, xzr"
+
+  -
+    input:
+      bytes: [ 0x10, 0x4c, 0x20, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelo pn8.b, x0, x0, vlx2"
+
+  -
+    input:
+      bytes: [ 0x55, 0x4d, 0x35, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelo pn13.b, x10, x21, vlx2"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x6d, 0x28, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelo pn15.b, x13, x8, vlx4"
+
+  -
+    input:
+      bytes: [ 0xf7, 0x6f, 0x3f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelo pn15.b, xzr, xzr, vlx4"
+
+  -
+    input:
+      bytes: [ 0x10, 0x5c, 0x20, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelo { p0.b, p1.b }, x0, x0"
+
+  -
+    input:
+      bytes: [ 0x54, 0x5d, 0x35, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelo { p4.b, p5.b }, x10, x21"
+
+  -
+    input:
+      bytes: [ 0xb6, 0x5d, 0x28, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelo { p6.b, p7.b }, x13, x8"
+
+  -
+    input:
+      bytes: [ 0xfe, 0x5f, 0x3f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelo { p14.b, p15.b }, xzr, xzr"
+
+  -
+    input:
+      bytes: [ 0x10, 0x4c, 0x60, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelo pn8.h, x0, x0, vlx2"
+
+  -
+    input:
+      bytes: [ 0x55, 0x4d, 0x75, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelo pn13.h, x10, x21, vlx2"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x6d, 0x68, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelo pn15.h, x13, x8, vlx4"
+
+  -
+    input:
+      bytes: [ 0xf7, 0x6f, 0x7f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelo pn15.h, xzr, xzr, vlx4"
+
+  -
+    input:
+      bytes: [ 0x10, 0x5c, 0x60, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelo { p0.h, p1.h }, x0, x0"
+
+  -
+    input:
+      bytes: [ 0x54, 0x5d, 0x75, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelo { p4.h, p5.h }, x10, x21"
+
+  -
+    input:
+      bytes: [ 0xb6, 0x5d, 0x68, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelo { p6.h, p7.h }, x13, x8"
+
+  -
+    input:
+      bytes: [ 0xfe, 0x5f, 0x7f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelo { p14.h, p15.h }, xzr, xzr"
+
+  -
+    input:
+      bytes: [ 0x10, 0x4c, 0xa0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelo pn8.s, x0, x0, vlx2"
+
+  -
+    input:
+      bytes: [ 0x55, 0x4d, 0xb5, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelo pn13.s, x10, x21, vlx2"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x6d, 0xa8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelo pn15.s, x13, x8, vlx4"
+
+  -
+    input:
+      bytes: [ 0xf7, 0x6f, 0xbf, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelo pn15.s, xzr, xzr, vlx4"
+
+  -
+    input:
+      bytes: [ 0x10, 0x5c, 0xa0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelo { p0.s, p1.s }, x0, x0"
+
+  -
+    input:
+      bytes: [ 0x54, 0x5d, 0xb5, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelo { p4.s, p5.s }, x10, x21"
+
+  -
+    input:
+      bytes: [ 0xb6, 0x5d, 0xa8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelo { p6.s, p7.s }, x13, x8"
+
+  -
+    input:
+      bytes: [ 0xfe, 0x5f, 0xbf, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelo { p14.s, p15.s }, xzr, xzr"
+
+  -
+    input:
+      bytes: [ 0x10, 0x4c, 0xe0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelo pn8.d, x0, x0, vlx2"
+
+  -
+    input:
+      bytes: [ 0x55, 0x4d, 0xf5, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelo pn13.d, x10, x21, vlx2"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x6d, 0xe8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelo pn15.d, x13, x8, vlx4"
+
+  -
+    input:
+      bytes: [ 0xf7, 0x6f, 0xff, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelo pn15.d, xzr, xzr, vlx4"
+
+  -
+    input:
+      bytes: [ 0x10, 0x5c, 0xe0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelo { p0.d, p1.d }, x0, x0"
+
+  -
+    input:
+      bytes: [ 0x54, 0x5d, 0xf5, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelo { p4.d, p5.d }, x10, x21"
+
+  -
+    input:
+      bytes: [ 0xb6, 0x5d, 0xe8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelo { p6.d, p7.d }, x13, x8"
+
+  -
+    input:
+      bytes: [ 0xfe, 0x5f, 0xff, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelo { p14.d, p15.d }, xzr, xzr"
+
+  -
+    input:
+      bytes: [ 0x10, 0x4c, 0x20, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelo pn8.b, x0, x0, vlx2"
+
+  -
+    input:
+      bytes: [ 0x55, 0x4d, 0x35, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelo pn13.b, x10, x21, vlx2"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x6d, 0x28, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelo pn15.b, x13, x8, vlx4"
+
+  -
+    input:
+      bytes: [ 0xf7, 0x6f, 0x3f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelo pn15.b, xzr, xzr, vlx4"
+
+  -
+    input:
+      bytes: [ 0x10, 0x5c, 0x20, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelo { p0.b, p1.b }, x0, x0"
+
+  -
+    input:
+      bytes: [ 0x54, 0x5d, 0x35, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelo { p4.b, p5.b }, x10, x21"
+
+  -
+    input:
+      bytes: [ 0xb6, 0x5d, 0x28, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelo { p6.b, p7.b }, x13, x8"
+
+  -
+    input:
+      bytes: [ 0xfe, 0x5f, 0x3f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelo { p14.b, p15.b }, xzr, xzr"
diff --git a/tests/MC/AArch64/SVE2p1/whilels.s.yaml b/tests/MC/AArch64/SVE2p1/whilels.s.yaml
new file mode 100644
index 000000000..5ac4b4d3e
--- /dev/null
+++ b/tests/MC/AArch64/SVE2p1/whilels.s.yaml
@@ -0,0 +1,640 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x18, 0x4c, 0x60, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilels pn8.h, x0, x0, vlx2"
+
+  -
+    input:
+      bytes: [ 0x5d, 0x4d, 0x75, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilels pn13.h, x10, x21, vlx2"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x6d, 0x68, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilels pn15.h, x13, x8, vlx4"
+
+  -
+    input:
+      bytes: [ 0xff, 0x6f, 0x7f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilels pn15.h, xzr, xzr, vlx4"
+
+  -
+    input:
+      bytes: [ 0x11, 0x5c, 0x60, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilels { p0.h, p1.h }, x0, x0"
+
+  -
+    input:
+      bytes: [ 0x55, 0x5d, 0x75, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilels { p4.h, p5.h }, x10, x21"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x5d, 0x68, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilels { p6.h, p7.h }, x13, x8"
+
+  -
+    input:
+      bytes: [ 0xff, 0x5f, 0x7f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilels { p14.h, p15.h }, xzr, xzr"
+
+  -
+    input:
+      bytes: [ 0x18, 0x4c, 0xa0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilels pn8.s, x0, x0, vlx2"
+
+  -
+    input:
+      bytes: [ 0x5d, 0x4d, 0xb5, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilels pn13.s, x10, x21, vlx2"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x6d, 0xa8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilels pn15.s, x13, x8, vlx4"
+
+  -
+    input:
+      bytes: [ 0xff, 0x6f, 0xbf, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilels pn15.s, xzr, xzr, vlx4"
+
+  -
+    input:
+      bytes: [ 0x11, 0x5c, 0xa0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilels { p0.s, p1.s }, x0, x0"
+
+  -
+    input:
+      bytes: [ 0x55, 0x5d, 0xb5, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilels { p4.s, p5.s }, x10, x21"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x5d, 0xa8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilels { p6.s, p7.s }, x13, x8"
+
+  -
+    input:
+      bytes: [ 0xff, 0x5f, 0xbf, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilels { p14.s, p15.s }, xzr, xzr"
+
+  -
+    input:
+      bytes: [ 0x18, 0x4c, 0xe0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilels pn8.d, x0, x0, vlx2"
+
+  -
+    input:
+      bytes: [ 0x5d, 0x4d, 0xf5, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilels pn13.d, x10, x21, vlx2"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x6d, 0xe8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilels pn15.d, x13, x8, vlx4"
+
+  -
+    input:
+      bytes: [ 0xff, 0x6f, 0xff, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilels pn15.d, xzr, xzr, vlx4"
+
+  -
+    input:
+      bytes: [ 0x11, 0x5c, 0xe0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilels { p0.d, p1.d }, x0, x0"
+
+  -
+    input:
+      bytes: [ 0x55, 0x5d, 0xf5, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilels { p4.d, p5.d }, x10, x21"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x5d, 0xe8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilels { p6.d, p7.d }, x13, x8"
+
+  -
+    input:
+      bytes: [ 0xff, 0x5f, 0xff, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilels { p14.d, p15.d }, xzr, xzr"
+
+  -
+    input:
+      bytes: [ 0x18, 0x4c, 0x20, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilels pn8.b, x0, x0, vlx2"
+
+  -
+    input:
+      bytes: [ 0x5d, 0x4d, 0x35, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilels pn13.b, x10, x21, vlx2"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x6d, 0x28, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilels pn15.b, x13, x8, vlx4"
+
+  -
+    input:
+      bytes: [ 0xff, 0x6f, 0x3f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilels pn15.b, xzr, xzr, vlx4"
+
+  -
+    input:
+      bytes: [ 0x11, 0x5c, 0x20, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilels { p0.b, p1.b }, x0, x0"
+
+  -
+    input:
+      bytes: [ 0x55, 0x5d, 0x35, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilels { p4.b, p5.b }, x10, x21"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x5d, 0x28, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilels { p6.b, p7.b }, x13, x8"
+
+  -
+    input:
+      bytes: [ 0xff, 0x5f, 0x3f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilels { p14.b, p15.b }, xzr, xzr"
+
+  -
+    input:
+      bytes: [ 0x18, 0x4c, 0x60, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilels pn8.h, x0, x0, vlx2"
+
+  -
+    input:
+      bytes: [ 0x5d, 0x4d, 0x75, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilels pn13.h, x10, x21, vlx2"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x6d, 0x68, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilels pn15.h, x13, x8, vlx4"
+
+  -
+    input:
+      bytes: [ 0xff, 0x6f, 0x7f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilels pn15.h, xzr, xzr, vlx4"
+
+  -
+    input:
+      bytes: [ 0x11, 0x5c, 0x60, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilels { p0.h, p1.h }, x0, x0"
+
+  -
+    input:
+      bytes: [ 0x55, 0x5d, 0x75, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilels { p4.h, p5.h }, x10, x21"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x5d, 0x68, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilels { p6.h, p7.h }, x13, x8"
+
+  -
+    input:
+      bytes: [ 0xff, 0x5f, 0x7f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilels { p14.h, p15.h }, xzr, xzr"
+
+  -
+    input:
+      bytes: [ 0x18, 0x4c, 0xa0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilels pn8.s, x0, x0, vlx2"
+
+  -
+    input:
+      bytes: [ 0x5d, 0x4d, 0xb5, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilels pn13.s, x10, x21, vlx2"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x6d, 0xa8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilels pn15.s, x13, x8, vlx4"
+
+  -
+    input:
+      bytes: [ 0xff, 0x6f, 0xbf, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilels pn15.s, xzr, xzr, vlx4"
+
+  -
+    input:
+      bytes: [ 0x11, 0x5c, 0xa0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilels { p0.s, p1.s }, x0, x0"
+
+  -
+    input:
+      bytes: [ 0x55, 0x5d, 0xb5, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilels { p4.s, p5.s }, x10, x21"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x5d, 0xa8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilels { p6.s, p7.s }, x13, x8"
+
+  -
+    input:
+      bytes: [ 0xff, 0x5f, 0xbf, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilels { p14.s, p15.s }, xzr, xzr"
+
+  -
+    input:
+      bytes: [ 0x18, 0x4c, 0xe0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilels pn8.d, x0, x0, vlx2"
+
+  -
+    input:
+      bytes: [ 0x5d, 0x4d, 0xf5, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilels pn13.d, x10, x21, vlx2"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x6d, 0xe8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilels pn15.d, x13, x8, vlx4"
+
+  -
+    input:
+      bytes: [ 0xff, 0x6f, 0xff, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilels pn15.d, xzr, xzr, vlx4"
+
+  -
+    input:
+      bytes: [ 0x11, 0x5c, 0xe0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilels { p0.d, p1.d }, x0, x0"
+
+  -
+    input:
+      bytes: [ 0x55, 0x5d, 0xf5, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilels { p4.d, p5.d }, x10, x21"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x5d, 0xe8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilels { p6.d, p7.d }, x13, x8"
+
+  -
+    input:
+      bytes: [ 0xff, 0x5f, 0xff, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilels { p14.d, p15.d }, xzr, xzr"
+
+  -
+    input:
+      bytes: [ 0x18, 0x4c, 0x20, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilels pn8.b, x0, x0, vlx2"
+
+  -
+    input:
+      bytes: [ 0x5d, 0x4d, 0x35, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilels pn13.b, x10, x21, vlx2"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x6d, 0x28, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilels pn15.b, x13, x8, vlx4"
+
+  -
+    input:
+      bytes: [ 0xff, 0x6f, 0x3f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilels pn15.b, xzr, xzr, vlx4"
+
+  -
+    input:
+      bytes: [ 0x11, 0x5c, 0x20, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilels { p0.b, p1.b }, x0, x0"
+
+  -
+    input:
+      bytes: [ 0x55, 0x5d, 0x35, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilels { p4.b, p5.b }, x10, x21"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x5d, 0x28, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilels { p6.b, p7.b }, x13, x8"
+
+  -
+    input:
+      bytes: [ 0xff, 0x5f, 0x3f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilels { p14.b, p15.b }, xzr, xzr"
diff --git a/tests/MC/AArch64/SVE2p1/whilelt.s.yaml b/tests/MC/AArch64/SVE2p1/whilelt.s.yaml
new file mode 100644
index 000000000..e5f0d9140
--- /dev/null
+++ b/tests/MC/AArch64/SVE2p1/whilelt.s.yaml
@@ -0,0 +1,640 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x10, 0x44, 0x60, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelt pn8.h, x0, x0, vlx2"
+
+  -
+    input:
+      bytes: [ 0x55, 0x45, 0x75, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelt pn13.h, x10, x21, vlx2"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x65, 0x68, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelt pn15.h, x13, x8, vlx4"
+
+  -
+    input:
+      bytes: [ 0xf7, 0x67, 0x7f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelt pn15.h, xzr, xzr, vlx4"
+
+  -
+    input:
+      bytes: [ 0x10, 0x54, 0x60, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelt { p0.h, p1.h }, x0, x0"
+
+  -
+    input:
+      bytes: [ 0x54, 0x55, 0x75, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelt { p4.h, p5.h }, x10, x21"
+
+  -
+    input:
+      bytes: [ 0xb6, 0x55, 0x68, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelt { p6.h, p7.h }, x13, x8"
+
+  -
+    input:
+      bytes: [ 0xfe, 0x57, 0x7f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelt { p14.h, p15.h }, xzr, xzr"
+
+  -
+    input:
+      bytes: [ 0x10, 0x44, 0xa0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelt pn8.s, x0, x0, vlx2"
+
+  -
+    input:
+      bytes: [ 0x55, 0x45, 0xb5, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelt pn13.s, x10, x21, vlx2"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x65, 0xa8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelt pn15.s, x13, x8, vlx4"
+
+  -
+    input:
+      bytes: [ 0xf7, 0x67, 0xbf, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelt pn15.s, xzr, xzr, vlx4"
+
+  -
+    input:
+      bytes: [ 0x10, 0x54, 0xa0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelt { p0.s, p1.s }, x0, x0"
+
+  -
+    input:
+      bytes: [ 0x54, 0x55, 0xb5, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelt { p4.s, p5.s }, x10, x21"
+
+  -
+    input:
+      bytes: [ 0xb6, 0x55, 0xa8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelt { p6.s, p7.s }, x13, x8"
+
+  -
+    input:
+      bytes: [ 0xfe, 0x57, 0xbf, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelt { p14.s, p15.s }, xzr, xzr"
+
+  -
+    input:
+      bytes: [ 0x10, 0x44, 0xe0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelt pn8.d, x0, x0, vlx2"
+
+  -
+    input:
+      bytes: [ 0x55, 0x45, 0xf5, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelt pn13.d, x10, x21, vlx2"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x65, 0xe8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelt pn15.d, x13, x8, vlx4"
+
+  -
+    input:
+      bytes: [ 0xf7, 0x67, 0xff, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelt pn15.d, xzr, xzr, vlx4"
+
+  -
+    input:
+      bytes: [ 0x10, 0x54, 0xe0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelt { p0.d, p1.d }, x0, x0"
+
+  -
+    input:
+      bytes: [ 0x54, 0x55, 0xf5, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelt { p4.d, p5.d }, x10, x21"
+
+  -
+    input:
+      bytes: [ 0xb6, 0x55, 0xe8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelt { p6.d, p7.d }, x13, x8"
+
+  -
+    input:
+      bytes: [ 0xfe, 0x57, 0xff, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelt { p14.d, p15.d }, xzr, xzr"
+
+  -
+    input:
+      bytes: [ 0x10, 0x44, 0x20, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelt pn8.b, x0, x0, vlx2"
+
+  -
+    input:
+      bytes: [ 0x55, 0x45, 0x35, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelt pn13.b, x10, x21, vlx2"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x65, 0x28, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelt pn15.b, x13, x8, vlx4"
+
+  -
+    input:
+      bytes: [ 0xf7, 0x67, 0x3f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelt pn15.b, xzr, xzr, vlx4"
+
+  -
+    input:
+      bytes: [ 0x10, 0x54, 0x20, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelt { p0.b, p1.b }, x0, x0"
+
+  -
+    input:
+      bytes: [ 0x54, 0x55, 0x35, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelt { p4.b, p5.b }, x10, x21"
+
+  -
+    input:
+      bytes: [ 0xb6, 0x55, 0x28, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelt { p6.b, p7.b }, x13, x8"
+
+  -
+    input:
+      bytes: [ 0xfe, 0x57, 0x3f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelt { p14.b, p15.b }, xzr, xzr"
+
+  -
+    input:
+      bytes: [ 0x10, 0x44, 0x60, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelt pn8.h, x0, x0, vlx2"
+
+  -
+    input:
+      bytes: [ 0x55, 0x45, 0x75, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelt pn13.h, x10, x21, vlx2"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x65, 0x68, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelt pn15.h, x13, x8, vlx4"
+
+  -
+    input:
+      bytes: [ 0xf7, 0x67, 0x7f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelt pn15.h, xzr, xzr, vlx4"
+
+  -
+    input:
+      bytes: [ 0x10, 0x54, 0x60, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelt { p0.h, p1.h }, x0, x0"
+
+  -
+    input:
+      bytes: [ 0x54, 0x55, 0x75, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelt { p4.h, p5.h }, x10, x21"
+
+  -
+    input:
+      bytes: [ 0xb6, 0x55, 0x68, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelt { p6.h, p7.h }, x13, x8"
+
+  -
+    input:
+      bytes: [ 0xfe, 0x57, 0x7f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelt { p14.h, p15.h }, xzr, xzr"
+
+  -
+    input:
+      bytes: [ 0x10, 0x44, 0xa0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelt pn8.s, x0, x0, vlx2"
+
+  -
+    input:
+      bytes: [ 0x55, 0x45, 0xb5, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelt pn13.s, x10, x21, vlx2"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x65, 0xa8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelt pn15.s, x13, x8, vlx4"
+
+  -
+    input:
+      bytes: [ 0xf7, 0x67, 0xbf, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelt pn15.s, xzr, xzr, vlx4"
+
+  -
+    input:
+      bytes: [ 0x10, 0x54, 0xa0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelt { p0.s, p1.s }, x0, x0"
+
+  -
+    input:
+      bytes: [ 0x54, 0x55, 0xb5, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelt { p4.s, p5.s }, x10, x21"
+
+  -
+    input:
+      bytes: [ 0xb6, 0x55, 0xa8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelt { p6.s, p7.s }, x13, x8"
+
+  -
+    input:
+      bytes: [ 0xfe, 0x57, 0xbf, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelt { p14.s, p15.s }, xzr, xzr"
+
+  -
+    input:
+      bytes: [ 0x10, 0x44, 0xe0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelt pn8.d, x0, x0, vlx2"
+
+  -
+    input:
+      bytes: [ 0x55, 0x45, 0xf5, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelt pn13.d, x10, x21, vlx2"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x65, 0xe8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelt pn15.d, x13, x8, vlx4"
+
+  -
+    input:
+      bytes: [ 0xf7, 0x67, 0xff, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelt pn15.d, xzr, xzr, vlx4"
+
+  -
+    input:
+      bytes: [ 0x10, 0x54, 0xe0, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelt { p0.d, p1.d }, x0, x0"
+
+  -
+    input:
+      bytes: [ 0x54, 0x55, 0xf5, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelt { p4.d, p5.d }, x10, x21"
+
+  -
+    input:
+      bytes: [ 0xb6, 0x55, 0xe8, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelt { p6.d, p7.d }, x13, x8"
+
+  -
+    input:
+      bytes: [ 0xfe, 0x57, 0xff, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelt { p14.d, p15.d }, xzr, xzr"
+
+  -
+    input:
+      bytes: [ 0x10, 0x44, 0x20, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelt pn8.b, x0, x0, vlx2"
+
+  -
+    input:
+      bytes: [ 0x55, 0x45, 0x35, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelt pn13.b, x10, x21, vlx2"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x65, 0x28, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelt pn15.b, x13, x8, vlx4"
+
+  -
+    input:
+      bytes: [ 0xf7, 0x67, 0x3f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelt pn15.b, xzr, xzr, vlx4"
+
+  -
+    input:
+      bytes: [ 0x10, 0x54, 0x20, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelt { p0.b, p1.b }, x0, x0"
+
+  -
+    input:
+      bytes: [ 0x54, 0x55, 0x35, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelt { p4.b, p5.b }, x10, x21"
+
+  -
+    input:
+      bytes: [ 0xb6, 0x55, 0x28, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelt { p6.b, p7.b }, x13, x8"
+
+  -
+    input:
+      bytes: [ 0xfe, 0x57, 0x3f, 0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "whilelt { p14.b, p15.b }, xzr, xzr"
diff --git a/tests/MC/AArch64/SVE2p1/zipq1.s.yaml b/tests/MC/AArch64/SVE2p1/zipq1.s.yaml
new file mode 100644
index 000000000..e1122ca48
--- /dev/null
+++ b/tests/MC/AArch64/SVE2p1/zipq1.s.yaml
@@ -0,0 +1,320 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x40, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zipq1 z0.h, z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x55, 0xe1, 0x55, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zipq1 z21.h, z10.h, z21.h"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xe1, 0x48, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zipq1 z23.h, z13.h, z8.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0xe3, 0x5f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zipq1 z31.h, z31.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x80, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zipq1 z0.s, z0.s, z0.s"
+
+  -
+    input:
+      bytes: [ 0x55, 0xe1, 0x95, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zipq1 z21.s, z10.s, z21.s"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xe1, 0x88, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zipq1 z23.s, z13.s, z8.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0xe3, 0x9f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zipq1 z31.s, z31.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xc0, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zipq1 z0.d, z0.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0x55, 0xe1, 0xd5, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zipq1 z21.d, z10.d, z21.d"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xe1, 0xc8, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zipq1 z23.d, z13.d, z8.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0xe3, 0xdf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zipq1 z31.d, z31.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x00, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zipq1 z0.b, z0.b, z0.b"
+
+  -
+    input:
+      bytes: [ 0x55, 0xe1, 0x15, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zipq1 z21.b, z10.b, z21.b"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xe1, 0x08, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zipq1 z23.b, z13.b, z8.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0xe3, 0x1f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zipq1 z31.b, z31.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x40, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zipq1 z0.h, z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x55, 0xe1, 0x55, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zipq1 z21.h, z10.h, z21.h"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xe1, 0x48, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zipq1 z23.h, z13.h, z8.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0xe3, 0x5f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zipq1 z31.h, z31.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x80, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zipq1 z0.s, z0.s, z0.s"
+
+  -
+    input:
+      bytes: [ 0x55, 0xe1, 0x95, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zipq1 z21.s, z10.s, z21.s"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xe1, 0x88, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zipq1 z23.s, z13.s, z8.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0xe3, 0x9f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zipq1 z31.s, z31.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xc0, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zipq1 z0.d, z0.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0x55, 0xe1, 0xd5, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zipq1 z21.d, z10.d, z21.d"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xe1, 0xc8, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zipq1 z23.d, z13.d, z8.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0xe3, 0xdf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zipq1 z31.d, z31.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x00, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zipq1 z0.b, z0.b, z0.b"
+
+  -
+    input:
+      bytes: [ 0x55, 0xe1, 0x15, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zipq1 z21.b, z10.b, z21.b"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xe1, 0x08, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zipq1 z23.b, z13.b, z8.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0xe3, 0x1f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zipq1 z31.b, z31.b, z31.b"
diff --git a/tests/MC/AArch64/SVE2p1/zipq2.s.yaml b/tests/MC/AArch64/SVE2p1/zipq2.s.yaml
new file mode 100644
index 000000000..1850b3c76
--- /dev/null
+++ b/tests/MC/AArch64/SVE2p1/zipq2.s.yaml
@@ -0,0 +1,320 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xe4, 0x40, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zipq2 z0.h, z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x55, 0xe5, 0x55, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zipq2 z21.h, z10.h, z21.h"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xe5, 0x48, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zipq2 z23.h, z13.h, z8.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0xe7, 0x5f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zipq2 z31.h, z31.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe4, 0x80, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zipq2 z0.s, z0.s, z0.s"
+
+  -
+    input:
+      bytes: [ 0x55, 0xe5, 0x95, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zipq2 z21.s, z10.s, z21.s"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xe5, 0x88, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zipq2 z23.s, z13.s, z8.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0xe7, 0x9f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zipq2 z31.s, z31.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe4, 0xc0, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zipq2 z0.d, z0.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0x55, 0xe5, 0xd5, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zipq2 z21.d, z10.d, z21.d"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xe5, 0xc8, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zipq2 z23.d, z13.d, z8.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0xe7, 0xdf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zipq2 z31.d, z31.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe4, 0x00, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zipq2 z0.b, z0.b, z0.b"
+
+  -
+    input:
+      bytes: [ 0x55, 0xe5, 0x15, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zipq2 z21.b, z10.b, z21.b"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xe5, 0x08, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zipq2 z23.b, z13.b, z8.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0xe7, 0x1f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sme2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zipq2 z31.b, z31.b, z31.b"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe4, 0x40, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zipq2 z0.h, z0.h, z0.h"
+
+  -
+    input:
+      bytes: [ 0x55, 0xe5, 0x55, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zipq2 z21.h, z10.h, z21.h"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xe5, 0x48, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zipq2 z23.h, z13.h, z8.h"
+
+  -
+    input:
+      bytes: [ 0xff, 0xe7, 0x5f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zipq2 z31.h, z31.h, z31.h"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe4, 0x80, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zipq2 z0.s, z0.s, z0.s"
+
+  -
+    input:
+      bytes: [ 0x55, 0xe5, 0x95, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zipq2 z21.s, z10.s, z21.s"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xe5, 0x88, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zipq2 z23.s, z13.s, z8.s"
+
+  -
+    input:
+      bytes: [ 0xff, 0xe7, 0x9f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zipq2 z31.s, z31.s, z31.s"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe4, 0xc0, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zipq2 z0.d, z0.d, z0.d"
+
+  -
+    input:
+      bytes: [ 0x55, 0xe5, 0xd5, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zipq2 z21.d, z10.d, z21.d"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xe5, 0xc8, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zipq2 z23.d, z13.d, z8.d"
+
+  -
+    input:
+      bytes: [ 0xff, 0xe7, 0xdf, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zipq2 z31.d, z31.d, z31.d"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe4, 0x00, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zipq2 z0.b, z0.b, z0.b"
+
+  -
+    input:
+      bytes: [ 0x55, 0xe5, 0x15, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zipq2 z21.b, z10.b, z21.b"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xe5, 0x08, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zipq2 z23.b, z13.b, z8.b"
+
+  -
+    input:
+      bytes: [ 0xff, 0xe7, 0x1f, 0x44 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "sve2p1" ]
+    expected:
+      insns:
+        -
+          asm_text: "zipq2 z31.b, z31.b, z31.b"
diff --git a/tests/MC/AArch64/a64-ignored-fields.txt.yaml b/tests/MC/AArch64/a64-ignored-fields.txt.yaml
new file mode 100644
index 000000000..c9068907d
--- /dev/null
+++ b/tests/MC/AArch64/a64-ignored-fields.txt.yaml
@@ -0,0 +1,20 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xe8, 0x23, 0x20, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmp s31, #0.0"
+
+  -
+    input:
+      bytes: [ 0xe8, 0x23, 0x20, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmp s31, #0.0"
diff --git a/tests/MC/AArch64/arm64-basic-a64-instructions.s.yaml b/tests/MC/AArch64/arm64-basic-a64-instructions.s.yaml
new file mode 100644
index 000000000..b75f6d3cc
--- /dev/null
+++ b/tests/MC/AArch64/arm64-basic-a64-instructions.s.yaml
@@ -0,0 +1,80 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xe5, 0x40, 0xd4, 0x1a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "crc" ]
+    expected:
+      insns:
+        -
+          asm_text: "crc32b w5, w7, w20"
+
+  -
+    input:
+      bytes: [ 0xfc, 0x47, 0xde, 0x1a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "crc" ]
+    expected:
+      insns:
+        -
+          asm_text: "crc32h w28, wzr, w30"
+
+  -
+    input:
+      bytes: [ 0x20, 0x48, 0xc2, 0x1a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "crc" ]
+    expected:
+      insns:
+        -
+          asm_text: "crc32w w0, w1, w2"
+
+  -
+    input:
+      bytes: [ 0x27, 0x4d, 0xd4, 0x9a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "crc" ]
+    expected:
+      insns:
+        -
+          asm_text: "crc32x w7, w9, x20"
+
+  -
+    input:
+      bytes: [ 0xa9, 0x50, 0xc4, 0x1a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "crc" ]
+    expected:
+      insns:
+        -
+          asm_text: "crc32cb w9, w5, w4"
+
+  -
+    input:
+      bytes: [ 0x2d, 0x56, 0xd9, 0x1a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "crc" ]
+    expected:
+      insns:
+        -
+          asm_text: "crc32ch w13, w17, w25"
+
+  -
+    input:
+      bytes: [ 0x7f, 0x58, 0xc5, 0x1a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "crc" ]
+    expected:
+      insns:
+        -
+          asm_text: "crc32cw wzr, w3, w5"
+
+  -
+    input:
+      bytes: [ 0x12, 0x5e, 0xdf, 0x9a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "crc" ]
+    expected:
+      insns:
+        -
+          asm_text: "crc32cx w18, w16, xzr"
diff --git a/tests/MC/AArch64/arm64-nv-cond.s.yaml b/tests/MC/AArch64/arm64-nv-cond.s.yaml
new file mode 100644
index 000000000..eda662287
--- /dev/null
+++ b/tests/MC/AArch64/arm64-nv-cond.s.yaml
@@ -0,0 +1,40 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xfc, 0xff, 0x7f, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcsel d28, d31, d31, nv"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf0, 0x80, 0x9a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "csel x0, x0, x0, nv"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf0, 0x40, 0xfa ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ccmp x0, x0, #0, nv"
+
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0x00, 0x54 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "b.nv #0"
diff --git a/tests/MC/AArch64/arm64-target-specific-sysreg.s.yaml b/tests/MC/AArch64/arm64-target-specific-sysreg.s.yaml
new file mode 100644
index 000000000..343a5cf3a
--- /dev/null
+++ b/tests/MC/AArch64/arm64-target-specific-sysreg.s.yaml
@@ -0,0 +1,10 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xf2, 0x1f, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "cyclone" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr CPM_IOACC_CTL_EL3, x0"
diff --git a/tests/MC/AArch64/arm64-verbose-vector-case.s.yaml b/tests/MC/AArch64/arm64-verbose-vector-case.s.yaml
new file mode 100644
index 000000000..47587b889
--- /dev/null
+++ b/tests/MC/AArch64/arm64-verbose-vector-case.s.yaml
@@ -0,0 +1,80 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x08, 0xe1, 0x28, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "crypto" ]
+    expected:
+      insns:
+        -
+          asm_text: "pmull v8.8h, v8.8b, v8.8b"
+
+  -
+    input:
+      bytes: [ 0x08, 0xe1, 0x28, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "crypto" ]
+    expected:
+      insns:
+        -
+          asm_text: "pmull2 v8.8h, v8.16b, v8.16b"
+
+  -
+    input:
+      bytes: [ 0x08, 0xe1, 0xe8, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "crypto" ]
+    expected:
+      insns:
+        -
+          asm_text: "pmull v8.1q, v8.1d, v8.1d"
+
+  -
+    input:
+      bytes: [ 0x08, 0xe1, 0xe8, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "crypto" ]
+    expected:
+      insns:
+        -
+          asm_text: "pmull2 v8.1q, v8.2d, v8.2d"
+
+  -
+    input:
+      bytes: [ 0x08, 0xe1, 0x28, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "crypto" ]
+    expected:
+      insns:
+        -
+          asm_text: "pmull v8.8h, v8.8b, v8.8b"
+
+  -
+    input:
+      bytes: [ 0x08, 0xe1, 0x28, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "crypto" ]
+    expected:
+      insns:
+        -
+          asm_text: "pmull2 v8.8h, v8.16b, v8.16b"
+
+  -
+    input:
+      bytes: [ 0x08, 0xe1, 0xe8, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "crypto" ]
+    expected:
+      insns:
+        -
+          asm_text: "pmull v8.1q, v8.1d, v8.1d"
+
+  -
+    input:
+      bytes: [ 0x08, 0xe1, 0xe8, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "crypto" ]
+    expected:
+      insns:
+        -
+          asm_text: "pmull2 v8.1q, v8.2d, v8.2d"
diff --git a/tests/MC/AArch64/arm64e.s.yaml b/tests/MC/AArch64/arm64e.s.yaml
new file mode 100644
index 000000000..fd442dcce
--- /dev/null
+++ b/tests/MC/AArch64/arm64e.s.yaml
@@ -0,0 +1,10 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x00, 0xc1, 0xda ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64e--" ]
+    expected:
+      insns:
+        -
+          asm_text: "pacia x0, x1"
diff --git a/tests/MC/AArch64/armv8.1a-vhe.s.yaml b/tests/MC/AArch64/armv8.1a-vhe.s.yaml
new file mode 100644
index 000000000..54da93b4b
--- /dev/null
+++ b/tests/MC/AArch64/armv8.1a-vhe.s.yaml
@@ -0,0 +1,270 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x20, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.1a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TTBR1_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd0, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.1a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr CONTEXTIDR_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe3, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.1a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr CNTHV_TVAL_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x40, 0xe3, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.1a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr CNTHV_CVAL_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe3, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.1a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr CNTHV_CTL_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x10, 0x1d, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.1a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SCTLR_EL12, x0"
+
+  -
+    input:
+      bytes: [ 0x40, 0x10, 0x1d, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.1a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr CPACR_EL12, x0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x1d, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.1a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TTBR0_EL12, x0"
+
+  -
+    input:
+      bytes: [ 0x20, 0x20, 0x1d, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.1a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TTBR1_EL12, x0"
+
+  -
+    input:
+      bytes: [ 0x40, 0x20, 0x1d, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.1a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TCR_EL12, x0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x51, 0x1d, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.1a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AFSR0_EL12, x0"
+
+  -
+    input:
+      bytes: [ 0x20, 0x51, 0x1d, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.1a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AFSR1_EL12, x0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x52, 0x1d, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.1a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ESR_EL12, x0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0x1d, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.1a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr FAR_EL12, x0"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa2, 0x1d, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.1a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr MAIR_EL12, x0"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa3, 0x1d, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.1a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMAIR_EL12, x0"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x1d, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.1a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr VBAR_EL12, x0"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd0, 0x1d, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.1a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr CONTEXTIDR_EL12, x0"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe1, 0x1d, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.1a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr CNTKCTL_EL12, x0"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe2, 0x1d, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.1a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr CNTP_TVAL_EL02, x0"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe2, 0x1d, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.1a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr CNTP_CTL_EL02, x0"
+
+  -
+    input:
+      bytes: [ 0x40, 0xe2, 0x1d, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.1a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr CNTP_CVAL_EL02, x0"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe3, 0x1d, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.1a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr CNTV_TVAL_EL02, x0"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe3, 0x1d, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.1a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr CNTV_CTL_EL02, x0"
+
+  -
+    input:
+      bytes: [ 0x40, 0xe3, 0x1d, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.1a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr CNTV_CVAL_EL02, x0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0x1d, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.1a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPSR_EL12, x0"
+
+  -
+    input:
+      bytes: [ 0x20, 0x40, 0x1d, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.1a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ELR_EL12, x0"
diff --git a/tests/MC/AArch64/armv8.2a-at.s.yaml b/tests/MC/AArch64/armv8.2a-at.s.yaml
new file mode 100644
index 000000000..dc32028ea
--- /dev/null
+++ b/tests/MC/AArch64/armv8.2a-at.s.yaml
@@ -0,0 +1,60 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x01, 0x79, 0x08, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.2a" ]
+    expected:
+      insns:
+        -
+          asm_text: "at s1e1rp, x1"
+
+  -
+    input:
+      bytes: [ 0x22, 0x79, 0x08, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.2a" ]
+    expected:
+      insns:
+        -
+          asm_text: "at s1e1wp, x2"
+
+  -
+    input:
+      bytes: [ 0x01, 0x79, 0x08, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-v8.2a", "+pan-rwv" ]
+    expected:
+      insns:
+        -
+          asm_text: "at s1e1rp, x1"
+
+  -
+    input:
+      bytes: [ 0x22, 0x79, 0x08, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-v8.2a", "+pan-rwv" ]
+    expected:
+      insns:
+        -
+          asm_text: "at s1e1wp, x2"
+
+  -
+    input:
+      bytes: [ 0x01, 0x79, 0x08, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "at s1e1rp, x1"
+
+  -
+    input:
+      bytes: [ 0x22, 0x79, 0x08, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "at s1e1wp, x2"
diff --git a/tests/MC/AArch64/armv8.2a-dotprod.s.yaml b/tests/MC/AArch64/armv8.2a-dotprod.s.yaml
new file mode 100644
index 000000000..ca11e9de2
--- /dev/null
+++ b/tests/MC/AArch64/armv8.2a-dotprod.s.yaml
@@ -0,0 +1,1800 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x94, 0x82, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "dotprod" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot v0.2s, v1.8b, v2.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x94, 0x82, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "dotprod" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot v0.2s, v1.8b, v2.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x94, 0x82, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "dotprod" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot v0.4s, v1.16b, v2.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x94, 0x82, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "dotprod" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot v0.4s, v1.16b, v2.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe0, 0x82, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "dotprod" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot v0.2s, v1.8b, v2.4b[0]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe0, 0xa2, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "dotprod" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot v0.2s, v1.8b, v2.4b[1]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe8, 0x82, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "dotprod" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot v0.4s, v1.16b, v2.4b[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe8, 0xa2, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "dotprod" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot v0.4s, v1.16b, v2.4b[3]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe0, 0x82, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "dotprod" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot v0.2s, v1.8b, v2.4b[0]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe8, 0x82, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "dotprod" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot v0.4s, v1.16b, v2.4b[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x94, 0x82, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a55" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot v0.2s, v1.8b, v2.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x94, 0x82, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a55" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot v0.2s, v1.8b, v2.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x94, 0x82, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a55" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot v0.4s, v1.16b, v2.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x94, 0x82, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a55" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot v0.4s, v1.16b, v2.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe0, 0x82, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a55" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot v0.2s, v1.8b, v2.4b[0]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe0, 0xa2, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a55" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot v0.2s, v1.8b, v2.4b[1]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe8, 0x82, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a55" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot v0.4s, v1.16b, v2.4b[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe8, 0xa2, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a55" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot v0.4s, v1.16b, v2.4b[3]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe0, 0x82, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a55" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot v0.2s, v1.8b, v2.4b[0]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe8, 0x82, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a55" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot v0.4s, v1.16b, v2.4b[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x94, 0x82, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a65" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot v0.2s, v1.8b, v2.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x94, 0x82, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a65" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot v0.2s, v1.8b, v2.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x94, 0x82, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a65" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot v0.4s, v1.16b, v2.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x94, 0x82, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a65" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot v0.4s, v1.16b, v2.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe0, 0x82, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a65" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot v0.2s, v1.8b, v2.4b[0]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe0, 0xa2, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a65" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot v0.2s, v1.8b, v2.4b[1]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe8, 0x82, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a65" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot v0.4s, v1.16b, v2.4b[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe8, 0xa2, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a65" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot v0.4s, v1.16b, v2.4b[3]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe0, 0x82, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a65" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot v0.2s, v1.8b, v2.4b[0]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe8, 0x82, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a65" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot v0.4s, v1.16b, v2.4b[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x94, 0x82, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a65ae" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot v0.2s, v1.8b, v2.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x94, 0x82, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a65ae" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot v0.2s, v1.8b, v2.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x94, 0x82, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a65ae" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot v0.4s, v1.16b, v2.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x94, 0x82, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a65ae" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot v0.4s, v1.16b, v2.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe0, 0x82, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a65ae" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot v0.2s, v1.8b, v2.4b[0]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe0, 0xa2, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a65ae" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot v0.2s, v1.8b, v2.4b[1]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe8, 0x82, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a65ae" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot v0.4s, v1.16b, v2.4b[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe8, 0xa2, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a65ae" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot v0.4s, v1.16b, v2.4b[3]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe0, 0x82, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a65ae" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot v0.2s, v1.8b, v2.4b[0]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe8, 0x82, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a65ae" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot v0.4s, v1.16b, v2.4b[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x94, 0x82, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a75" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot v0.2s, v1.8b, v2.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x94, 0x82, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a75" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot v0.2s, v1.8b, v2.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x94, 0x82, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a75" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot v0.4s, v1.16b, v2.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x94, 0x82, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a75" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot v0.4s, v1.16b, v2.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe0, 0x82, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a75" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot v0.2s, v1.8b, v2.4b[0]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe0, 0xa2, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a75" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot v0.2s, v1.8b, v2.4b[1]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe8, 0x82, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a75" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot v0.4s, v1.16b, v2.4b[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe8, 0xa2, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a75" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot v0.4s, v1.16b, v2.4b[3]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe0, 0x82, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a75" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot v0.2s, v1.8b, v2.4b[0]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe8, 0x82, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a75" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot v0.4s, v1.16b, v2.4b[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x94, 0x82, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a76" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot v0.2s, v1.8b, v2.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x94, 0x82, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a76" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot v0.2s, v1.8b, v2.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x94, 0x82, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a76" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot v0.4s, v1.16b, v2.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x94, 0x82, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a76" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot v0.4s, v1.16b, v2.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe0, 0x82, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a76" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot v0.2s, v1.8b, v2.4b[0]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe0, 0xa2, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a76" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot v0.2s, v1.8b, v2.4b[1]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe8, 0x82, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a76" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot v0.4s, v1.16b, v2.4b[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe8, 0xa2, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a76" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot v0.4s, v1.16b, v2.4b[3]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe0, 0x82, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a76" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot v0.2s, v1.8b, v2.4b[0]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe8, 0x82, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a76" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot v0.4s, v1.16b, v2.4b[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x94, 0x82, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a77" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot v0.2s, v1.8b, v2.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x94, 0x82, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a77" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot v0.2s, v1.8b, v2.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x94, 0x82, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a77" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot v0.4s, v1.16b, v2.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x94, 0x82, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a77" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot v0.4s, v1.16b, v2.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe0, 0x82, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a77" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot v0.2s, v1.8b, v2.4b[0]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe0, 0xa2, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a77" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot v0.2s, v1.8b, v2.4b[1]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe8, 0x82, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a77" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot v0.4s, v1.16b, v2.4b[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe8, 0xa2, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a77" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot v0.4s, v1.16b, v2.4b[3]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe0, 0x82, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a77" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot v0.2s, v1.8b, v2.4b[0]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe8, 0x82, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a77" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot v0.4s, v1.16b, v2.4b[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x94, 0x82, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a78" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot v0.2s, v1.8b, v2.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x94, 0x82, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a78" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot v0.2s, v1.8b, v2.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x94, 0x82, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a78" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot v0.4s, v1.16b, v2.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x94, 0x82, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a78" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot v0.4s, v1.16b, v2.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe0, 0x82, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a78" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot v0.2s, v1.8b, v2.4b[0]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe0, 0xa2, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a78" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot v0.2s, v1.8b, v2.4b[1]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe8, 0x82, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a78" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot v0.4s, v1.16b, v2.4b[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe8, 0xa2, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a78" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot v0.4s, v1.16b, v2.4b[3]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe0, 0x82, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a78" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot v0.2s, v1.8b, v2.4b[0]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe8, 0x82, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a78" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot v0.4s, v1.16b, v2.4b[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x94, 0x82, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-x1" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot v0.2s, v1.8b, v2.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x94, 0x82, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-x1" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot v0.2s, v1.8b, v2.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x94, 0x82, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-x1" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot v0.4s, v1.16b, v2.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x94, 0x82, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-x1" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot v0.4s, v1.16b, v2.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe0, 0x82, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-x1" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot v0.2s, v1.8b, v2.4b[0]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe0, 0xa2, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-x1" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot v0.2s, v1.8b, v2.4b[1]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe8, 0x82, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-x1" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot v0.4s, v1.16b, v2.4b[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe8, 0xa2, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-x1" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot v0.4s, v1.16b, v2.4b[3]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe0, 0x82, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-x1" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot v0.2s, v1.8b, v2.4b[0]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe8, 0x82, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-x1" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot v0.4s, v1.16b, v2.4b[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x94, 0x82, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "neoverse-e1" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot v0.2s, v1.8b, v2.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x94, 0x82, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "neoverse-e1" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot v0.2s, v1.8b, v2.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x94, 0x82, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "neoverse-e1" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot v0.4s, v1.16b, v2.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x94, 0x82, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "neoverse-e1" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot v0.4s, v1.16b, v2.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe0, 0x82, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "neoverse-e1" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot v0.2s, v1.8b, v2.4b[0]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe0, 0xa2, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "neoverse-e1" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot v0.2s, v1.8b, v2.4b[1]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe8, 0x82, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "neoverse-e1" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot v0.4s, v1.16b, v2.4b[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe8, 0xa2, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "neoverse-e1" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot v0.4s, v1.16b, v2.4b[3]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe0, 0x82, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "neoverse-e1" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot v0.2s, v1.8b, v2.4b[0]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe8, 0x82, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "neoverse-e1" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot v0.4s, v1.16b, v2.4b[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x94, 0x82, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "neoverse-n1" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot v0.2s, v1.8b, v2.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x94, 0x82, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "neoverse-n1" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot v0.2s, v1.8b, v2.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x94, 0x82, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "neoverse-n1" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot v0.4s, v1.16b, v2.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x94, 0x82, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "neoverse-n1" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot v0.4s, v1.16b, v2.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe0, 0x82, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "neoverse-n1" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot v0.2s, v1.8b, v2.4b[0]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe0, 0xa2, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "neoverse-n1" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot v0.2s, v1.8b, v2.4b[1]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe8, 0x82, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "neoverse-n1" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot v0.4s, v1.16b, v2.4b[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe8, 0xa2, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "neoverse-n1" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot v0.4s, v1.16b, v2.4b[3]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe0, 0x82, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "neoverse-n1" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot v0.2s, v1.8b, v2.4b[0]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe8, 0x82, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "neoverse-n1" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot v0.4s, v1.16b, v2.4b[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x94, 0x82, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "neoverse-n2" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot v0.2s, v1.8b, v2.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x94, 0x82, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "neoverse-n2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot v0.2s, v1.8b, v2.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x94, 0x82, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "neoverse-n2" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot v0.4s, v1.16b, v2.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x94, 0x82, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "neoverse-n2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot v0.4s, v1.16b, v2.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe0, 0x82, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "neoverse-n2" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot v0.2s, v1.8b, v2.4b[0]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe0, 0xa2, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "neoverse-n2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot v0.2s, v1.8b, v2.4b[1]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe8, 0x82, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "neoverse-n2" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot v0.4s, v1.16b, v2.4b[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe8, 0xa2, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "neoverse-n2" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot v0.4s, v1.16b, v2.4b[3]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe0, 0x82, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "neoverse-n2" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot v0.2s, v1.8b, v2.4b[0]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe8, 0x82, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "neoverse-n2" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot v0.4s, v1.16b, v2.4b[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x94, 0x82, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "tsv110" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot v0.2s, v1.8b, v2.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x94, 0x82, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "tsv110" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot v0.2s, v1.8b, v2.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x94, 0x82, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "tsv110" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot v0.4s, v1.16b, v2.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x94, 0x82, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "tsv110" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot v0.4s, v1.16b, v2.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe0, 0x82, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "tsv110" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot v0.2s, v1.8b, v2.4b[0]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe0, 0xa2, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "tsv110" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot v0.2s, v1.8b, v2.4b[1]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe8, 0x82, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "tsv110" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot v0.4s, v1.16b, v2.4b[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe8, 0xa2, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "tsv110" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot v0.4s, v1.16b, v2.4b[3]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe0, 0x82, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "tsv110" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot v0.2s, v1.8b, v2.4b[0]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe8, 0x82, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "tsv110" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot v0.4s, v1.16b, v2.4b[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x94, 0x82, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-r82" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot v0.2s, v1.8b, v2.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x94, 0x82, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-r82" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot v0.2s, v1.8b, v2.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x94, 0x82, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-r82" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot v0.4s, v1.16b, v2.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x94, 0x82, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-r82" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot v0.4s, v1.16b, v2.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe0, 0x82, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-r82" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot v0.2s, v1.8b, v2.4b[0]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe0, 0xa2, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-r82" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot v0.2s, v1.8b, v2.4b[1]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe8, 0x82, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-r82" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot v0.4s, v1.16b, v2.4b[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe8, 0xa2, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-r82" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot v0.4s, v1.16b, v2.4b[3]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe0, 0x82, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-r82" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot v0.2s, v1.8b, v2.4b[0]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe8, 0x82, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-r82" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot v0.4s, v1.16b, v2.4b[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x94, 0x82, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot v0.2s, v1.8b, v2.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x94, 0x82, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot v0.2s, v1.8b, v2.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x94, 0x82, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot v0.4s, v1.16b, v2.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x94, 0x82, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot v0.4s, v1.16b, v2.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe0, 0x82, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot v0.2s, v1.8b, v2.4b[0]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe0, 0xa2, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot v0.2s, v1.8b, v2.4b[1]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe8, 0x82, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot v0.4s, v1.16b, v2.4b[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe8, 0xa2, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot v0.4s, v1.16b, v2.4b[3]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe0, 0x82, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot v0.2s, v1.8b, v2.4b[0]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe8, 0x82, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot v0.4s, v1.16b, v2.4b[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x94, 0x82, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ampere1" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot v0.2s, v1.8b, v2.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x94, 0x82, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ampere1" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot v0.2s, v1.8b, v2.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x94, 0x82, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ampere1" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot v0.4s, v1.16b, v2.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x94, 0x82, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ampere1" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot v0.4s, v1.16b, v2.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe0, 0x82, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ampere1" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot v0.2s, v1.8b, v2.4b[0]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe0, 0xa2, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ampere1" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot v0.2s, v1.8b, v2.4b[1]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe8, 0x82, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ampere1" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot v0.4s, v1.16b, v2.4b[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe8, 0xa2, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ampere1" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot v0.4s, v1.16b, v2.4b[3]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe0, 0x82, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ampere1" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot v0.2s, v1.8b, v2.4b[0]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe8, 0x82, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ampere1" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot v0.4s, v1.16b, v2.4b[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x94, 0x82, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ampere1a" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot v0.2s, v1.8b, v2.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x94, 0x82, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ampere1a" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot v0.2s, v1.8b, v2.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x94, 0x82, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ampere1a" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot v0.4s, v1.16b, v2.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x94, 0x82, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ampere1a" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot v0.4s, v1.16b, v2.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe0, 0x82, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ampere1a" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot v0.2s, v1.8b, v2.4b[0]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe0, 0xa2, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ampere1a" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot v0.2s, v1.8b, v2.4b[1]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe8, 0x82, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ampere1a" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot v0.4s, v1.16b, v2.4b[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe8, 0xa2, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ampere1a" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot v0.4s, v1.16b, v2.4b[3]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe0, 0x82, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ampere1a" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot v0.2s, v1.8b, v2.4b[0]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe8, 0x82, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ampere1a" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot v0.4s, v1.16b, v2.4b[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x94, 0x82, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ampere1b" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot v0.2s, v1.8b, v2.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x94, 0x82, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ampere1b" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot v0.2s, v1.8b, v2.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x94, 0x82, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ampere1b" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot v0.4s, v1.16b, v2.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x94, 0x82, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ampere1b" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot v0.4s, v1.16b, v2.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe0, 0x82, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ampere1b" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot v0.2s, v1.8b, v2.4b[0]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe0, 0xa2, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ampere1b" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot v0.2s, v1.8b, v2.4b[1]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe8, 0x82, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ampere1b" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot v0.4s, v1.16b, v2.4b[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe8, 0xa2, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ampere1b" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdot v0.4s, v1.16b, v2.4b[3]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe0, 0x82, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ampere1b" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot v0.2s, v1.8b, v2.4b[0]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe8, 0x82, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ampere1b" ]
+    expected:
+      insns:
+        -
+          asm_text: "udot v0.4s, v1.16b, v2.4b[2]"
diff --git a/tests/MC/AArch64/armv8.2a-persistent-memory.s.yaml b/tests/MC/AArch64/armv8.2a-persistent-memory.s.yaml
new file mode 100644
index 000000000..ab87f564a
--- /dev/null
+++ b/tests/MC/AArch64/armv8.2a-persistent-memory.s.yaml
@@ -0,0 +1,30 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x27, 0x7c, 0x0b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.2a" ]
+    expected:
+      insns:
+        -
+          asm_text: "dc cvap, x7"
+
+  -
+    input:
+      bytes: [ 0x27, 0x7c, 0x0b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ccpp" ]
+    expected:
+      insns:
+        -
+          asm_text: "dc cvap, x7"
+
+  -
+    input:
+      bytes: [ 0x27, 0x7c, 0x0b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "dc cvap, x7"
diff --git a/tests/MC/AArch64/armv8.3a-ID_ISAR6_EL1.s.yaml b/tests/MC/AArch64/armv8.3a-ID_ISAR6_EL1.s.yaml
new file mode 100644
index 000000000..8c735fc49
--- /dev/null
+++ b/tests/MC/AArch64/armv8.3a-ID_ISAR6_EL1.s.yaml
@@ -0,0 +1,10 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xe0, 0x02, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, ID_ISAR6_EL1"
diff --git a/tests/MC/AArch64/armv8.3a-complex.s.yaml b/tests/MC/AArch64/armv8.3a-complex.s.yaml
new file mode 100644
index 000000000..4c4913b71
--- /dev/null
+++ b/tests/MC/AArch64/armv8.3a-complex.s.yaml
@@ -0,0 +1,500 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0xc4, 0x42, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "complxnum", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmla v0.4h, v1.4h, v2.4h, #0"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc4, 0x42, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "complxnum", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmla v0.8h, v1.8h, v2.8h, #0"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc4, 0x82, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "complxnum", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmla v0.2s, v1.2s, v2.2s, #0"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc4, 0x82, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "complxnum", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmla v0.4s, v1.4s, v2.4s, #0"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc4, 0xc2, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "complxnum", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmla v0.2d, v1.2d, v2.2d, #0"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc4, 0x82, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "complxnum", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmla v0.2s, v1.2s, v2.2s, #0"
+
+  -
+    input:
+      bytes: [ 0x20, 0xcc, 0x82, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "complxnum", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmla v0.2s, v1.2s, v2.2s, #90"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd4, 0x82, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "complxnum", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmla v0.2s, v1.2s, v2.2s, #180"
+
+  -
+    input:
+      bytes: [ 0x20, 0xdc, 0x82, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "complxnum", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmla v0.2s, v1.2s, v2.2s, #270"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe4, 0x42, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "complxnum", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcadd v0.4h, v1.4h, v2.4h, #90"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe4, 0x42, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "complxnum", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcadd v0.8h, v1.8h, v2.8h, #90"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe4, 0x82, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "complxnum", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcadd v0.2s, v1.2s, v2.2s, #90"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe4, 0x82, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "complxnum", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcadd v0.4s, v1.4s, v2.4s, #90"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe4, 0xc2, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "complxnum", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcadd v0.2d, v1.2d, v2.2d, #90"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe4, 0x82, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "complxnum", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcadd v0.2s, v1.2s, v2.2s, #90"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf4, 0x82, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "complxnum", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcadd v0.2s, v1.2s, v2.2s, #270"
+
+  -
+    input:
+      bytes: [ 0x20, 0x10, 0x42, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "complxnum", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmla v0.4h, v1.4h, v2.h[0], #0"
+
+  -
+    input:
+      bytes: [ 0x20, 0x10, 0x42, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "complxnum", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmla v0.8h, v1.8h, v2.h[0], #0"
+
+  -
+    input:
+      bytes: [ 0x20, 0x10, 0x82, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "complxnum", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmla v0.4s, v1.4s, v2.s[0], #0"
+
+  -
+    input:
+      bytes: [ 0x20, 0x30, 0x82, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "complxnum", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmla v0.4s, v1.4s, v2.s[0], #90"
+
+  -
+    input:
+      bytes: [ 0x20, 0x50, 0x82, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "complxnum", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmla v0.4s, v1.4s, v2.s[0], #180"
+
+  -
+    input:
+      bytes: [ 0x20, 0x70, 0x82, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "complxnum", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmla v0.4s, v1.4s, v2.s[0], #270"
+
+  -
+    input:
+      bytes: [ 0x20, 0x10, 0x62, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "complxnum", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmla v0.4h, v1.4h, v2.h[1], #0"
+
+  -
+    input:
+      bytes: [ 0x20, 0x18, 0x62, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "complxnum", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmla v0.8h, v1.8h, v2.h[3], #0"
+
+  -
+    input:
+      bytes: [ 0x20, 0x18, 0x82, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "complxnum", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmla v0.4s, v1.4s, v2.s[1], #0"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc4, 0x42, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmla v0.4h, v1.4h, v2.4h, #0"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc4, 0x42, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmla v0.8h, v1.8h, v2.8h, #0"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc4, 0x82, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmla v0.2s, v1.2s, v2.2s, #0"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc4, 0x82, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmla v0.4s, v1.4s, v2.4s, #0"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc4, 0xc2, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmla v0.2d, v1.2d, v2.2d, #0"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc4, 0x82, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmla v0.2s, v1.2s, v2.2s, #0"
+
+  -
+    input:
+      bytes: [ 0x20, 0xcc, 0x82, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmla v0.2s, v1.2s, v2.2s, #90"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd4, 0x82, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmla v0.2s, v1.2s, v2.2s, #180"
+
+  -
+    input:
+      bytes: [ 0x20, 0xdc, 0x82, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmla v0.2s, v1.2s, v2.2s, #270"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe4, 0x42, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcadd v0.4h, v1.4h, v2.4h, #90"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe4, 0x42, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcadd v0.8h, v1.8h, v2.8h, #90"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe4, 0x82, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcadd v0.2s, v1.2s, v2.2s, #90"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe4, 0x82, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcadd v0.4s, v1.4s, v2.4s, #90"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe4, 0xc2, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcadd v0.2d, v1.2d, v2.2d, #90"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe4, 0x82, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcadd v0.2s, v1.2s, v2.2s, #90"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf4, 0x82, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcadd v0.2s, v1.2s, v2.2s, #270"
+
+  -
+    input:
+      bytes: [ 0x20, 0x10, 0x42, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmla v0.4h, v1.4h, v2.h[0], #0"
+
+  -
+    input:
+      bytes: [ 0x20, 0x10, 0x42, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmla v0.8h, v1.8h, v2.h[0], #0"
+
+  -
+    input:
+      bytes: [ 0x20, 0x10, 0x82, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmla v0.4s, v1.4s, v2.s[0], #0"
+
+  -
+    input:
+      bytes: [ 0x20, 0x30, 0x82, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmla v0.4s, v1.4s, v2.s[0], #90"
+
+  -
+    input:
+      bytes: [ 0x20, 0x50, 0x82, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmla v0.4s, v1.4s, v2.s[0], #180"
+
+  -
+    input:
+      bytes: [ 0x20, 0x70, 0x82, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmla v0.4s, v1.4s, v2.s[0], #270"
+
+  -
+    input:
+      bytes: [ 0x20, 0x10, 0x62, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmla v0.4h, v1.4h, v2.h[1], #0"
+
+  -
+    input:
+      bytes: [ 0x20, 0x18, 0x62, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmla v0.8h, v1.8h, v2.h[3], #0"
+
+  -
+    input:
+      bytes: [ 0x20, 0x18, 0x82, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmla v0.4s, v1.4s, v2.s[1], #0"
diff --git a/tests/MC/AArch64/armv8.3a-complex_nofp16.s.yaml b/tests/MC/AArch64/armv8.3a-complex_nofp16.s.yaml
new file mode 100644
index 000000000..6e46e2298
--- /dev/null
+++ b/tests/MC/AArch64/armv8.3a-complex_nofp16.s.yaml
@@ -0,0 +1,170 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0xc4, 0x82, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "complxnum" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmla v0.2s, v1.2s, v2.2s, #0"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc4, 0x82, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "complxnum" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmla v0.4s, v1.4s, v2.4s, #0"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc4, 0xc2, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "complxnum" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmla v0.2d, v1.2d, v2.2d, #0"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc4, 0x82, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "complxnum" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmla v0.2s, v1.2s, v2.2s, #0"
+
+  -
+    input:
+      bytes: [ 0x20, 0xcc, 0x82, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "complxnum" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmla v0.2s, v1.2s, v2.2s, #90"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd4, 0x82, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "complxnum" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmla v0.2s, v1.2s, v2.2s, #180"
+
+  -
+    input:
+      bytes: [ 0x20, 0xdc, 0x82, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "complxnum" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmla v0.2s, v1.2s, v2.2s, #270"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe4, 0x82, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "complxnum" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcadd v0.2s, v1.2s, v2.2s, #90"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe4, 0x82, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "complxnum" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcadd v0.4s, v1.4s, v2.4s, #90"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe4, 0xc2, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "complxnum" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcadd v0.2d, v1.2d, v2.2d, #90"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe4, 0x82, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "complxnum" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcadd v0.2s, v1.2s, v2.2s, #90"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf4, 0x82, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "complxnum" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcadd v0.2s, v1.2s, v2.2s, #270"
+
+  -
+    input:
+      bytes: [ 0x20, 0x10, 0x82, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "complxnum" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmla v0.4s, v1.4s, v2.s[0], #0"
+
+  -
+    input:
+      bytes: [ 0x20, 0x30, 0x82, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "complxnum" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmla v0.4s, v1.4s, v2.s[0], #90"
+
+  -
+    input:
+      bytes: [ 0x20, 0x50, 0x82, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "complxnum" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmla v0.4s, v1.4s, v2.s[0], #180"
+
+  -
+    input:
+      bytes: [ 0x20, 0x70, 0x82, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "complxnum" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmla v0.4s, v1.4s, v2.s[0], #270"
+
+  -
+    input:
+      bytes: [ 0x20, 0x18, 0x82, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "complxnum" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmla v0.4s, v1.4s, v2.s[1], #0"
diff --git a/tests/MC/AArch64/armv8.3a-js.s.yaml b/tests/MC/AArch64/armv8.3a-js.s.yaml
new file mode 100644
index 000000000..266a29d57
--- /dev/null
+++ b/tests/MC/AArch64/armv8.3a-js.s.yaml
@@ -0,0 +1,20 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x7e, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ]
+    expected:
+      insns:
+        -
+          asm_text: "fjcvtzs w0, d0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x7e, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "jsconv" ]
+    expected:
+      insns:
+        -
+          asm_text: "fjcvtzs w0, d0"
diff --git a/tests/MC/AArch64/armv8.3a-pauth.s.yaml b/tests/MC/AArch64/armv8.3a-pauth.s.yaml
new file mode 100644
index 000000000..e45bfb159
--- /dev/null
+++ b/tests/MC/AArch64/armv8.3a-pauth.s.yaml
@@ -0,0 +1,10 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x3f, 0x23, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "pauth" ]
+    expected:
+      insns:
+        -
+          asm_text: "paciasp"
diff --git a/tests/MC/AArch64/armv8.3a-rcpc.s.yaml b/tests/MC/AArch64/armv8.3a-rcpc.s.yaml
new file mode 100644
index 000000000..a290e71a0
--- /dev/null
+++ b/tests/MC/AArch64/armv8.3a-rcpc.s.yaml
@@ -0,0 +1,660 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0xbf, 0x38 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldaprb w0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc2, 0xbf, 0x78 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldaprh w0, [x17]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc0, 0xbf, 0xb8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapr w0, [x1]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0xbf, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapr x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x12, 0xc0, 0xbf, 0xb8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapr w18, [x0]"
+
+  -
+    input:
+      bytes: [ 0x0f, 0xc0, 0xbf, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapr x15, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0xbf, 0x38 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a65" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldaprb w0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc2, 0xbf, 0x78 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a65" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldaprh w0, [x17]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc0, 0xbf, 0xb8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a65" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapr w0, [x1]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0xbf, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a65" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapr x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x12, 0xc0, 0xbf, 0xb8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a65" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapr w18, [x0]"
+
+  -
+    input:
+      bytes: [ 0x0f, 0xc0, 0xbf, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a65" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapr x15, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0xbf, 0x38 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a65ae" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldaprb w0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc2, 0xbf, 0x78 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a65ae" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldaprh w0, [x17]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc0, 0xbf, 0xb8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a65ae" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapr w0, [x1]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0xbf, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a65ae" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapr x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x12, 0xc0, 0xbf, 0xb8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a65ae" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapr w18, [x0]"
+
+  -
+    input:
+      bytes: [ 0x0f, 0xc0, 0xbf, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a65ae" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapr x15, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0xbf, 0x38 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a75" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldaprb w0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc2, 0xbf, 0x78 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a75" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldaprh w0, [x17]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc0, 0xbf, 0xb8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a75" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapr w0, [x1]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0xbf, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a75" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapr x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x12, 0xc0, 0xbf, 0xb8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a75" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapr w18, [x0]"
+
+  -
+    input:
+      bytes: [ 0x0f, 0xc0, 0xbf, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a75" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapr x15, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0xbf, 0x38 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a55" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldaprb w0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc2, 0xbf, 0x78 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a55" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldaprh w0, [x17]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc0, 0xbf, 0xb8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a55" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapr w0, [x1]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0xbf, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a55" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapr x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x12, 0xc0, 0xbf, 0xb8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a55" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapr w18, [x0]"
+
+  -
+    input:
+      bytes: [ 0x0f, 0xc0, 0xbf, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a55" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapr x15, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0xbf, 0x38 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neoverse-e1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldaprb w0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc2, 0xbf, 0x78 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neoverse-e1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldaprh w0, [x17]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc0, 0xbf, 0xb8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neoverse-e1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapr w0, [x1]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0xbf, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neoverse-e1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapr x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x12, 0xc0, 0xbf, 0xb8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neoverse-e1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapr w18, [x0]"
+
+  -
+    input:
+      bytes: [ 0x0f, 0xc0, 0xbf, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neoverse-e1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapr x15, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0xbf, 0x38 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neoverse-n1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldaprb w0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc2, 0xbf, 0x78 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neoverse-n1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldaprh w0, [x17]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc0, 0xbf, 0xb8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neoverse-n1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapr w0, [x1]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0xbf, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neoverse-n1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapr x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x12, 0xc0, 0xbf, 0xb8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neoverse-n1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapr w18, [x0]"
+
+  -
+    input:
+      bytes: [ 0x0f, 0xc0, 0xbf, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neoverse-n1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapr x15, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0xbf, 0x38 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neoverse-n2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldaprb w0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc2, 0xbf, 0x78 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neoverse-n2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldaprh w0, [x17]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc0, 0xbf, 0xb8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neoverse-n2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapr w0, [x1]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0xbf, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neoverse-n2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapr x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x12, 0xc0, 0xbf, 0xb8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neoverse-n2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapr w18, [x0]"
+
+  -
+    input:
+      bytes: [ 0x0f, 0xc0, 0xbf, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neoverse-n2" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapr x15, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0xbf, 0x38 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ampere1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldaprb w0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc2, 0xbf, 0x78 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ampere1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldaprh w0, [x17]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc0, 0xbf, 0xb8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ampere1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapr w0, [x1]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0xbf, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ampere1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapr x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x12, 0xc0, 0xbf, 0xb8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ampere1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapr w18, [x0]"
+
+  -
+    input:
+      bytes: [ 0x0f, 0xc0, 0xbf, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ampere1" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapr x15, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0xbf, 0x38 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ampere1a" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldaprb w0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc2, 0xbf, 0x78 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ampere1a" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldaprh w0, [x17]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc0, 0xbf, 0xb8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ampere1a" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapr w0, [x1]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0xbf, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ampere1a" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapr x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x12, 0xc0, 0xbf, 0xb8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ampere1a" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapr w18, [x0]"
+
+  -
+    input:
+      bytes: [ 0x0f, 0xc0, 0xbf, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ampere1a" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapr x15, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0xbf, 0x38 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.2a", "rcpc" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldaprb w0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc2, 0xbf, 0x78 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.2a", "rcpc" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldaprh w0, [x17]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc0, 0xbf, 0xb8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.2a", "rcpc" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapr w0, [x1]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0xbf, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.2a", "rcpc" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapr x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x12, 0xc0, 0xbf, 0xb8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.2a", "rcpc" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapr w18, [x0]"
+
+  -
+    input:
+      bytes: [ 0x0f, 0xc0, 0xbf, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.2a", "rcpc" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapr x15, [x0]"
diff --git a/tests/MC/AArch64/armv8.3a-signed-pointer.s.yaml b/tests/MC/AArch64/armv8.3a-signed-pointer.s.yaml
new file mode 100644
index 000000000..a3e2c6e90
--- /dev/null
+++ b/tests/MC/AArch64/armv8.3a-signed-pointer.s.yaml
@@ -0,0 +1,910 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x21, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, APIAKeyLo_EL1"
+
+  -
+    input:
+      bytes: [ 0x20, 0x21, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, APIAKeyHi_EL1"
+
+  -
+    input:
+      bytes: [ 0x40, 0x21, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, APIBKeyLo_EL1"
+
+  -
+    input:
+      bytes: [ 0x60, 0x21, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, APIBKeyHi_EL1"
+
+  -
+    input:
+      bytes: [ 0x00, 0x22, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, APDAKeyLo_EL1"
+
+  -
+    input:
+      bytes: [ 0x20, 0x22, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, APDAKeyHi_EL1"
+
+  -
+    input:
+      bytes: [ 0x40, 0x22, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, APDBKeyLo_EL1"
+
+  -
+    input:
+      bytes: [ 0x60, 0x22, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, APDBKeyHi_EL1"
+
+  -
+    input:
+      bytes: [ 0x00, 0x23, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, APGAKeyLo_EL1"
+
+  -
+    input:
+      bytes: [ 0x20, 0x23, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, APGAKeyHi_EL1"
+
+  -
+    input:
+      bytes: [ 0x00, 0x21, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr APIAKeyLo_EL1, x0"
+
+  -
+    input:
+      bytes: [ 0x20, 0x21, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr APIAKeyHi_EL1, x0"
+
+  -
+    input:
+      bytes: [ 0x40, 0x21, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr APIBKeyLo_EL1, x0"
+
+  -
+    input:
+      bytes: [ 0x60, 0x21, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr APIBKeyHi_EL1, x0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x22, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr APDAKeyLo_EL1, x0"
+
+  -
+    input:
+      bytes: [ 0x20, 0x22, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr APDAKeyHi_EL1, x0"
+
+  -
+    input:
+      bytes: [ 0x40, 0x22, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr APDBKeyLo_EL1, x0"
+
+  -
+    input:
+      bytes: [ 0x60, 0x22, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr APDBKeyHi_EL1, x0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x23, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr APGAKeyLo_EL1, x0"
+
+  -
+    input:
+      bytes: [ 0x20, 0x23, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr APGAKeyHi_EL1, x0"
+
+  -
+    input:
+      bytes: [ 0xff, 0x20, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ]
+    expected:
+      insns:
+        -
+          asm_text: "xpaclri"
+
+  -
+    input:
+      bytes: [ 0xff, 0x20, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ]
+    expected:
+      insns:
+        -
+          asm_text: "xpaclri"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x21, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ]
+    expected:
+      insns:
+        -
+          asm_text: "pacia1716"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x21, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ]
+    expected:
+      insns:
+        -
+          asm_text: "pacia1716"
+
+  -
+    input:
+      bytes: [ 0x5f, 0x21, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ]
+    expected:
+      insns:
+        -
+          asm_text: "pacib1716"
+
+  -
+    input:
+      bytes: [ 0x5f, 0x21, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ]
+    expected:
+      insns:
+        -
+          asm_text: "pacib1716"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x21, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ]
+    expected:
+      insns:
+        -
+          asm_text: "autia1716"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x21, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ]
+    expected:
+      insns:
+        -
+          asm_text: "autia1716"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x21, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ]
+    expected:
+      insns:
+        -
+          asm_text: "autib1716"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x21, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ]
+    expected:
+      insns:
+        -
+          asm_text: "autib1716"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x23, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ]
+    expected:
+      insns:
+        -
+          asm_text: "paciaz"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x23, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ]
+    expected:
+      insns:
+        -
+          asm_text: "paciaz"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x23, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ]
+    expected:
+      insns:
+        -
+          asm_text: "paciasp"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x23, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ]
+    expected:
+      insns:
+        -
+          asm_text: "paciasp"
+
+  -
+    input:
+      bytes: [ 0x5f, 0x23, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ]
+    expected:
+      insns:
+        -
+          asm_text: "pacibz"
+
+  -
+    input:
+      bytes: [ 0x5f, 0x23, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ]
+    expected:
+      insns:
+        -
+          asm_text: "pacibz"
+
+  -
+    input:
+      bytes: [ 0x7f, 0x23, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ]
+    expected:
+      insns:
+        -
+          asm_text: "pacibsp"
+
+  -
+    input:
+      bytes: [ 0x7f, 0x23, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ]
+    expected:
+      insns:
+        -
+          asm_text: "pacibsp"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x23, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ]
+    expected:
+      insns:
+        -
+          asm_text: "autiaz"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x23, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ]
+    expected:
+      insns:
+        -
+          asm_text: "autiaz"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x23, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ]
+    expected:
+      insns:
+        -
+          asm_text: "autiasp"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x23, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ]
+    expected:
+      insns:
+        -
+          asm_text: "autiasp"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x23, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ]
+    expected:
+      insns:
+        -
+          asm_text: "autibz"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x23, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ]
+    expected:
+      insns:
+        -
+          asm_text: "autibz"
+
+  -
+    input:
+      bytes: [ 0xff, 0x23, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ]
+    expected:
+      insns:
+        -
+          asm_text: "autibsp"
+
+  -
+    input:
+      bytes: [ 0xff, 0x23, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ]
+    expected:
+      insns:
+        -
+          asm_text: "autibsp"
+
+  -
+    input:
+      bytes: [ 0x20, 0x00, 0xc1, 0xda ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ]
+    expected:
+      insns:
+        -
+          asm_text: "pacia x0, x1"
+
+  -
+    input:
+      bytes: [ 0x20, 0x10, 0xc1, 0xda ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ]
+    expected:
+      insns:
+        -
+          asm_text: "autia x0, x1"
+
+  -
+    input:
+      bytes: [ 0x20, 0x08, 0xc1, 0xda ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ]
+    expected:
+      insns:
+        -
+          asm_text: "pacda x0, x1"
+
+  -
+    input:
+      bytes: [ 0x20, 0x18, 0xc1, 0xda ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ]
+    expected:
+      insns:
+        -
+          asm_text: "autda x0, x1"
+
+  -
+    input:
+      bytes: [ 0x20, 0x04, 0xc1, 0xda ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ]
+    expected:
+      insns:
+        -
+          asm_text: "pacib x0, x1"
+
+  -
+    input:
+      bytes: [ 0x20, 0x14, 0xc1, 0xda ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ]
+    expected:
+      insns:
+        -
+          asm_text: "autib x0, x1"
+
+  -
+    input:
+      bytes: [ 0x20, 0x0c, 0xc1, 0xda ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ]
+    expected:
+      insns:
+        -
+          asm_text: "pacdb x0, x1"
+
+  -
+    input:
+      bytes: [ 0x20, 0x1c, 0xc1, 0xda ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ]
+    expected:
+      insns:
+        -
+          asm_text: "autdb x0, x1"
+
+  -
+    input:
+      bytes: [ 0x20, 0x30, 0xc2, 0x9a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ]
+    expected:
+      insns:
+        -
+          asm_text: "pacga x0, x1, x2"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x23, 0xc1, 0xda ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ]
+    expected:
+      insns:
+        -
+          asm_text: "paciza x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x33, 0xc1, 0xda ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ]
+    expected:
+      insns:
+        -
+          asm_text: "autiza x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x2b, 0xc1, 0xda ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ]
+    expected:
+      insns:
+        -
+          asm_text: "pacdza x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3b, 0xc1, 0xda ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ]
+    expected:
+      insns:
+        -
+          asm_text: "autdza x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x27, 0xc1, 0xda ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ]
+    expected:
+      insns:
+        -
+          asm_text: "pacizb x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x37, 0xc1, 0xda ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ]
+    expected:
+      insns:
+        -
+          asm_text: "autizb x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x2f, 0xc1, 0xda ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ]
+    expected:
+      insns:
+        -
+          asm_text: "pacdzb x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3f, 0xc1, 0xda ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ]
+    expected:
+      insns:
+        -
+          asm_text: "autdzb x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x43, 0xc1, 0xda ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ]
+    expected:
+      insns:
+        -
+          asm_text: "xpaci x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x47, 0xc1, 0xda ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ]
+    expected:
+      insns:
+        -
+          asm_text: "xpacd x0"
+
+  -
+    input:
+      bytes: [ 0x01, 0x08, 0x1f, 0xd7 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ]
+    expected:
+      insns:
+        -
+          asm_text: "braa x0, x1"
+
+  -
+    input:
+      bytes: [ 0x01, 0x0c, 0x1f, 0xd7 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ]
+    expected:
+      insns:
+        -
+          asm_text: "brab x0, x1"
+
+  -
+    input:
+      bytes: [ 0x01, 0x08, 0x3f, 0xd7 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ]
+    expected:
+      insns:
+        -
+          asm_text: "blraa x0, x1"
+
+  -
+    input:
+      bytes: [ 0x01, 0x0c, 0x3f, 0xd7 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ]
+    expected:
+      insns:
+        -
+          asm_text: "blrab x0, x1"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x08, 0x1f, 0xd6 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ]
+    expected:
+      insns:
+        -
+          asm_text: "braaz x0"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x0c, 0x1f, 0xd6 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ]
+    expected:
+      insns:
+        -
+          asm_text: "brabz x0"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x08, 0x3f, 0xd6 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ]
+    expected:
+      insns:
+        -
+          asm_text: "blraaz x0"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x0c, 0x3f, 0xd6 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ]
+    expected:
+      insns:
+        -
+          asm_text: "blrabz x0"
+
+  -
+    input:
+      bytes: [ 0xff, 0x0b, 0x5f, 0xd6 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ]
+    expected:
+      insns:
+        -
+          asm_text: "retaa"
+
+  -
+    input:
+      bytes: [ 0xff, 0x0f, 0x5f, 0xd6 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ]
+    expected:
+      insns:
+        -
+          asm_text: "retab"
+
+  -
+    input:
+      bytes: [ 0xff, 0x0b, 0x9f, 0xd6 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ]
+    expected:
+      insns:
+        -
+          asm_text: "eretaa"
+
+  -
+    input:
+      bytes: [ 0xff, 0x0f, 0x9f, 0xd6 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ]
+    expected:
+      insns:
+        -
+          asm_text: "eretab"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf4, 0x3f, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldraa x0, [x1, #4088]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x04, 0x60, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldraa x0, [x1, #-4096]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf4, 0xbf, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldrab x0, [x1, #4088]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x04, 0xe0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldrab x0, [x1, #-4096]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xfc, 0x3f, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldraa x0, [x1, #4088]!"
+
+  -
+    input:
+      bytes: [ 0x20, 0x0c, 0x60, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldraa x0, [x1, #-4096]!"
+
+  -
+    input:
+      bytes: [ 0x20, 0xfc, 0xbf, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldrab x0, [x1, #4088]!"
+
+  -
+    input:
+      bytes: [ 0x20, 0x0c, 0xe0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldrab x0, [x1, #-4096]!"
+
+  -
+    input:
+      bytes: [ 0x20, 0x04, 0x20, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldraa x0, [x1]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x04, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldrab x0, [x1]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x0c, 0x20, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldraa x0, [x1, #0]!"
+
+  -
+    input:
+      bytes: [ 0x20, 0x0c, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldrab x0, [x1, #0]!"
+
+  -
+    input:
+      bytes: [ 0xff, 0x0f, 0x60, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldraa xzr, [sp, #-4096]!"
+
+  -
+    input:
+      bytes: [ 0xff, 0x0f, 0xe0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.3a" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldrab xzr, [sp, #-4096]!"
diff --git a/tests/MC/AArch64/armv8.4a-flag.s.yaml b/tests/MC/AArch64/armv8.4a-flag.s.yaml
new file mode 100644
index 000000000..c4335cb3e
--- /dev/null
+++ b/tests/MC/AArch64/armv8.4a-flag.s.yaml
@@ -0,0 +1,140 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x1f, 0x40, 0x00, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "cfinv"
+
+  -
+    input:
+      bytes: [ 0x2d, 0x08, 0x00, 0x3a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "setf8 w1"
+
+  -
+    input:
+      bytes: [ 0xed, 0x0b, 0x00, 0x3a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "setf8 wzr"
+
+  -
+    input:
+      bytes: [ 0x2d, 0x48, 0x00, 0x3a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "setf16 w1"
+
+  -
+    input:
+      bytes: [ 0xed, 0x4b, 0x00, 0x3a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "setf16 wzr"
+
+  -
+    input:
+      bytes: [ 0x2f, 0x84, 0x1f, 0xba ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "rmif x1, #63, #15"
+
+  -
+    input:
+      bytes: [ 0xef, 0x87, 0x1f, 0xba ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "rmif xzr, #63, #15"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x40, 0x00, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "flagm" ]
+    expected:
+      insns:
+        -
+          asm_text: "cfinv"
+
+  -
+    input:
+      bytes: [ 0x2d, 0x08, 0x00, 0x3a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "flagm" ]
+    expected:
+      insns:
+        -
+          asm_text: "setf8 w1"
+
+  -
+    input:
+      bytes: [ 0xed, 0x0b, 0x00, 0x3a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "flagm" ]
+    expected:
+      insns:
+        -
+          asm_text: "setf8 wzr"
+
+  -
+    input:
+      bytes: [ 0x2d, 0x48, 0x00, 0x3a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "flagm" ]
+    expected:
+      insns:
+        -
+          asm_text: "setf16 w1"
+
+  -
+    input:
+      bytes: [ 0xed, 0x4b, 0x00, 0x3a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "flagm" ]
+    expected:
+      insns:
+        -
+          asm_text: "setf16 wzr"
+
+  -
+    input:
+      bytes: [ 0x2f, 0x84, 0x1f, 0xba ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "flagm" ]
+    expected:
+      insns:
+        -
+          asm_text: "rmif x1, #63, #15"
+
+  -
+    input:
+      bytes: [ 0xef, 0x87, 0x1f, 0xba ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "flagm" ]
+    expected:
+      insns:
+        -
+          asm_text: "rmif xzr, #63, #15"
diff --git a/tests/MC/AArch64/armv8.4a-flagm.s.yaml b/tests/MC/AArch64/armv8.4a-flagm.s.yaml
new file mode 100644
index 000000000..482415b63
--- /dev/null
+++ b/tests/MC/AArch64/armv8.4a-flagm.s.yaml
@@ -0,0 +1,20 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x1f, 0x40, 0x00, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "flagm" ]
+    expected:
+      insns:
+        -
+          asm_text: "cfinv"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x40, 0x00, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "flagm" ]
+    expected:
+      insns:
+        -
+          asm_text: "cfinv"
diff --git a/tests/MC/AArch64/armv8.4a-ldst.s.yaml b/tests/MC/AArch64/armv8.4a-ldst.s.yaml
new file mode 100644
index 000000000..bfd9f4637
--- /dev/null
+++ b/tests/MC/AArch64/armv8.4a-ldst.s.yaml
@@ -0,0 +1,1100 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x5f, 0x01, 0x00, 0x19 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "stlurb wzr, [x10]"
+
+  -
+    input:
+      bytes: [ 0x41, 0x01, 0x00, 0x19 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "stlurb w1, [x10]"
+
+  -
+    input:
+      bytes: [ 0x41, 0x01, 0x10, 0x19 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "stlurb w1, [x10, #-256]"
+
+  -
+    input:
+      bytes: [ 0x62, 0xf1, 0x0f, 0x19 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "stlurb w2, [x11, #255]"
+
+  -
+    input:
+      bytes: [ 0xe3, 0xd3, 0x1f, 0x19 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "stlurb w3, [sp, #-3]"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x01, 0x40, 0x19 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapurb wzr, [x12]"
+
+  -
+    input:
+      bytes: [ 0x84, 0x01, 0x40, 0x19 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapurb w4, [x12]"
+
+  -
+    input:
+      bytes: [ 0x84, 0x01, 0x50, 0x19 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapurb w4, [x12, #-256]"
+
+  -
+    input:
+      bytes: [ 0xa5, 0xf1, 0x4f, 0x19 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapurb w5, [x13, #255]"
+
+  -
+    input:
+      bytes: [ 0xe6, 0xe3, 0x5f, 0x19 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapurb w6, [sp, #-2]"
+
+  -
+    input:
+      bytes: [ 0xc7, 0x01, 0xc0, 0x19 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapursb w7, [x14]"
+
+  -
+    input:
+      bytes: [ 0xc7, 0x01, 0xd0, 0x19 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapursb w7, [x14, #-256]"
+
+  -
+    input:
+      bytes: [ 0xe8, 0xf1, 0xcf, 0x19 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapursb w8, [x15, #255]"
+
+  -
+    input:
+      bytes: [ 0xe9, 0xf3, 0xdf, 0x19 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapursb w9, [sp, #-1]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x02, 0x80, 0x19 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapursb x0, [x16]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x02, 0x90, 0x19 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapursb x0, [x16, #-256]"
+
+  -
+    input:
+      bytes: [ 0x21, 0xf2, 0x8f, 0x19 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapursb x1, [x17, #255]"
+
+  -
+    input:
+      bytes: [ 0xe2, 0x03, 0x80, 0x19 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapursb x2, [sp]"
+
+  -
+    input:
+      bytes: [ 0xe2, 0x03, 0x80, 0x19 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapursb x2, [sp]"
+
+  -
+    input:
+      bytes: [ 0x4a, 0x02, 0x00, 0x59 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "stlurh w10, [x18]"
+
+  -
+    input:
+      bytes: [ 0x4a, 0x02, 0x10, 0x59 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "stlurh w10, [x18, #-256]"
+
+  -
+    input:
+      bytes: [ 0x6b, 0xf2, 0x0f, 0x59 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "stlurh w11, [x19, #255]"
+
+  -
+    input:
+      bytes: [ 0xec, 0x13, 0x00, 0x59 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "stlurh w12, [sp, #1]"
+
+  -
+    input:
+      bytes: [ 0x8d, 0x02, 0x40, 0x59 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapurh w13, [x20]"
+
+  -
+    input:
+      bytes: [ 0x8d, 0x02, 0x50, 0x59 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapurh w13, [x20, #-256]"
+
+  -
+    input:
+      bytes: [ 0xae, 0xf2, 0x4f, 0x59 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapurh w14, [x21, #255]"
+
+  -
+    input:
+      bytes: [ 0xef, 0x23, 0x40, 0x59 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapurh w15, [sp, #2]"
+
+  -
+    input:
+      bytes: [ 0xd0, 0x02, 0xc0, 0x59 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapursh w16, [x22]"
+
+  -
+    input:
+      bytes: [ 0xd0, 0x02, 0xd0, 0x59 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapursh w16, [x22, #-256]"
+
+  -
+    input:
+      bytes: [ 0xf1, 0xf2, 0xcf, 0x59 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapursh w17, [x23, #255]"
+
+  -
+    input:
+      bytes: [ 0xf2, 0x33, 0xc0, 0x59 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapursh w18, [sp, #3]"
+
+  -
+    input:
+      bytes: [ 0x03, 0x03, 0x80, 0x59 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapursh x3, [x24]"
+
+  -
+    input:
+      bytes: [ 0x03, 0x03, 0x90, 0x59 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapursh x3, [x24, #-256]"
+
+  -
+    input:
+      bytes: [ 0x24, 0xf3, 0x8f, 0x59 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapursh x4, [x25, #255]"
+
+  -
+    input:
+      bytes: [ 0xe5, 0x43, 0x80, 0x59 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapursh x5, [sp, #4]"
+
+  -
+    input:
+      bytes: [ 0x53, 0x03, 0x00, 0x99 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "stlur w19, [x26]"
+
+  -
+    input:
+      bytes: [ 0x53, 0x03, 0x10, 0x99 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "stlur w19, [x26, #-256]"
+
+  -
+    input:
+      bytes: [ 0x74, 0xf3, 0x0f, 0x99 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "stlur w20, [x27, #255]"
+
+  -
+    input:
+      bytes: [ 0xf5, 0x53, 0x00, 0x99 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "stlur w21, [sp, #5]"
+
+  -
+    input:
+      bytes: [ 0x96, 0x03, 0x40, 0x99 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapur w22, [x28]"
+
+  -
+    input:
+      bytes: [ 0x96, 0x03, 0x50, 0x99 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapur w22, [x28, #-256]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xf3, 0x4f, 0x99 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapur w23, [x29, #255]"
+
+  -
+    input:
+      bytes: [ 0xf8, 0x63, 0x40, 0x99 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapur w24, [sp, #6]"
+
+  -
+    input:
+      bytes: [ 0xc6, 0x03, 0x80, 0x99 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapursw x6, [x30]"
+
+  -
+    input:
+      bytes: [ 0xc6, 0x03, 0x90, 0x99 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapursw x6, [x30, #-256]"
+
+  -
+    input:
+      bytes: [ 0x07, 0xf0, 0x8f, 0x99 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapursw x7, [x0, #255]"
+
+  -
+    input:
+      bytes: [ 0xe8, 0x73, 0x80, 0x99 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapursw x8, [sp, #7]"
+
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0x00, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "stlur x9, [x1]"
+
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0x10, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "stlur x9, [x1, #-256]"
+
+  -
+    input:
+      bytes: [ 0x4a, 0xf0, 0x0f, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "stlur x10, [x2, #255]"
+
+  -
+    input:
+      bytes: [ 0xeb, 0x83, 0x00, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "stlur x11, [sp, #8]"
+
+  -
+    input:
+      bytes: [ 0x6c, 0x00, 0x40, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapur x12, [x3]"
+
+  -
+    input:
+      bytes: [ 0x6c, 0x00, 0x50, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapur x12, [x3, #-256]"
+
+  -
+    input:
+      bytes: [ 0x8d, 0xf0, 0x4f, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapur x13, [x4, #255]"
+
+  -
+    input:
+      bytes: [ 0xee, 0x93, 0x40, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapur x14, [sp, #9]"
+
+  -
+    input:
+      bytes: [ 0x5f, 0x01, 0x00, 0x19 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-v8.4a", "+rcpc-immo" ]
+    expected:
+      insns:
+        -
+          asm_text: "stlurb wzr, [x10]"
+
+  -
+    input:
+      bytes: [ 0x41, 0x01, 0x00, 0x19 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-v8.4a", "+rcpc-immo" ]
+    expected:
+      insns:
+        -
+          asm_text: "stlurb w1, [x10]"
+
+  -
+    input:
+      bytes: [ 0x41, 0x01, 0x10, 0x19 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-v8.4a", "+rcpc-immo" ]
+    expected:
+      insns:
+        -
+          asm_text: "stlurb w1, [x10, #-256]"
+
+  -
+    input:
+      bytes: [ 0x62, 0xf1, 0x0f, 0x19 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-v8.4a", "+rcpc-immo" ]
+    expected:
+      insns:
+        -
+          asm_text: "stlurb w2, [x11, #255]"
+
+  -
+    input:
+      bytes: [ 0xe3, 0xd3, 0x1f, 0x19 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-v8.4a", "+rcpc-immo" ]
+    expected:
+      insns:
+        -
+          asm_text: "stlurb w3, [sp, #-3]"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x01, 0x40, 0x19 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-v8.4a", "+rcpc-immo" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapurb wzr, [x12]"
+
+  -
+    input:
+      bytes: [ 0x84, 0x01, 0x40, 0x19 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-v8.4a", "+rcpc-immo" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapurb w4, [x12]"
+
+  -
+    input:
+      bytes: [ 0x84, 0x01, 0x50, 0x19 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-v8.4a", "+rcpc-immo" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapurb w4, [x12, #-256]"
+
+  -
+    input:
+      bytes: [ 0xa5, 0xf1, 0x4f, 0x19 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-v8.4a", "+rcpc-immo" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapurb w5, [x13, #255]"
+
+  -
+    input:
+      bytes: [ 0xe6, 0xe3, 0x5f, 0x19 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-v8.4a", "+rcpc-immo" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapurb w6, [sp, #-2]"
+
+  -
+    input:
+      bytes: [ 0xc7, 0x01, 0xc0, 0x19 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-v8.4a", "+rcpc-immo" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapursb w7, [x14]"
+
+  -
+    input:
+      bytes: [ 0xc7, 0x01, 0xd0, 0x19 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-v8.4a", "+rcpc-immo" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapursb w7, [x14, #-256]"
+
+  -
+    input:
+      bytes: [ 0xe8, 0xf1, 0xcf, 0x19 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-v8.4a", "+rcpc-immo" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapursb w8, [x15, #255]"
+
+  -
+    input:
+      bytes: [ 0xe9, 0xf3, 0xdf, 0x19 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-v8.4a", "+rcpc-immo" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapursb w9, [sp, #-1]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x02, 0x80, 0x19 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-v8.4a", "+rcpc-immo" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapursb x0, [x16]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x02, 0x90, 0x19 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-v8.4a", "+rcpc-immo" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapursb x0, [x16, #-256]"
+
+  -
+    input:
+      bytes: [ 0x21, 0xf2, 0x8f, 0x19 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-v8.4a", "+rcpc-immo" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapursb x1, [x17, #255]"
+
+  -
+    input:
+      bytes: [ 0xe2, 0x03, 0x80, 0x19 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-v8.4a", "+rcpc-immo" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapursb x2, [sp]"
+
+  -
+    input:
+      bytes: [ 0xe2, 0x03, 0x80, 0x19 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-v8.4a", "+rcpc-immo" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapursb x2, [sp]"
+
+  -
+    input:
+      bytes: [ 0x4a, 0x02, 0x00, 0x59 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-v8.4a", "+rcpc-immo" ]
+    expected:
+      insns:
+        -
+          asm_text: "stlurh w10, [x18]"
+
+  -
+    input:
+      bytes: [ 0x4a, 0x02, 0x10, 0x59 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-v8.4a", "+rcpc-immo" ]
+    expected:
+      insns:
+        -
+          asm_text: "stlurh w10, [x18, #-256]"
+
+  -
+    input:
+      bytes: [ 0x6b, 0xf2, 0x0f, 0x59 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-v8.4a", "+rcpc-immo" ]
+    expected:
+      insns:
+        -
+          asm_text: "stlurh w11, [x19, #255]"
+
+  -
+    input:
+      bytes: [ 0xec, 0x13, 0x00, 0x59 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-v8.4a", "+rcpc-immo" ]
+    expected:
+      insns:
+        -
+          asm_text: "stlurh w12, [sp, #1]"
+
+  -
+    input:
+      bytes: [ 0x8d, 0x02, 0x40, 0x59 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-v8.4a", "+rcpc-immo" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapurh w13, [x20]"
+
+  -
+    input:
+      bytes: [ 0x8d, 0x02, 0x50, 0x59 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-v8.4a", "+rcpc-immo" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapurh w13, [x20, #-256]"
+
+  -
+    input:
+      bytes: [ 0xae, 0xf2, 0x4f, 0x59 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-v8.4a", "+rcpc-immo" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapurh w14, [x21, #255]"
+
+  -
+    input:
+      bytes: [ 0xef, 0x23, 0x40, 0x59 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-v8.4a", "+rcpc-immo" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapurh w15, [sp, #2]"
+
+  -
+    input:
+      bytes: [ 0xd0, 0x02, 0xc0, 0x59 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-v8.4a", "+rcpc-immo" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapursh w16, [x22]"
+
+  -
+    input:
+      bytes: [ 0xd0, 0x02, 0xd0, 0x59 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-v8.4a", "+rcpc-immo" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapursh w16, [x22, #-256]"
+
+  -
+    input:
+      bytes: [ 0xf1, 0xf2, 0xcf, 0x59 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-v8.4a", "+rcpc-immo" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapursh w17, [x23, #255]"
+
+  -
+    input:
+      bytes: [ 0xf2, 0x33, 0xc0, 0x59 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-v8.4a", "+rcpc-immo" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapursh w18, [sp, #3]"
+
+  -
+    input:
+      bytes: [ 0x03, 0x03, 0x80, 0x59 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-v8.4a", "+rcpc-immo" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapursh x3, [x24]"
+
+  -
+    input:
+      bytes: [ 0x03, 0x03, 0x90, 0x59 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-v8.4a", "+rcpc-immo" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapursh x3, [x24, #-256]"
+
+  -
+    input:
+      bytes: [ 0x24, 0xf3, 0x8f, 0x59 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-v8.4a", "+rcpc-immo" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapursh x4, [x25, #255]"
+
+  -
+    input:
+      bytes: [ 0xe5, 0x43, 0x80, 0x59 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-v8.4a", "+rcpc-immo" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapursh x5, [sp, #4]"
+
+  -
+    input:
+      bytes: [ 0x53, 0x03, 0x00, 0x99 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-v8.4a", "+rcpc-immo" ]
+    expected:
+      insns:
+        -
+          asm_text: "stlur w19, [x26]"
+
+  -
+    input:
+      bytes: [ 0x53, 0x03, 0x10, 0x99 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-v8.4a", "+rcpc-immo" ]
+    expected:
+      insns:
+        -
+          asm_text: "stlur w19, [x26, #-256]"
+
+  -
+    input:
+      bytes: [ 0x74, 0xf3, 0x0f, 0x99 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-v8.4a", "+rcpc-immo" ]
+    expected:
+      insns:
+        -
+          asm_text: "stlur w20, [x27, #255]"
+
+  -
+    input:
+      bytes: [ 0xf5, 0x53, 0x00, 0x99 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-v8.4a", "+rcpc-immo" ]
+    expected:
+      insns:
+        -
+          asm_text: "stlur w21, [sp, #5]"
+
+  -
+    input:
+      bytes: [ 0x96, 0x03, 0x40, 0x99 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-v8.4a", "+rcpc-immo" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapur w22, [x28]"
+
+  -
+    input:
+      bytes: [ 0x96, 0x03, 0x50, 0x99 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-v8.4a", "+rcpc-immo" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapur w22, [x28, #-256]"
+
+  -
+    input:
+      bytes: [ 0xb7, 0xf3, 0x4f, 0x99 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-v8.4a", "+rcpc-immo" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapur w23, [x29, #255]"
+
+  -
+    input:
+      bytes: [ 0xf8, 0x63, 0x40, 0x99 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-v8.4a", "+rcpc-immo" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapur w24, [sp, #6]"
+
+  -
+    input:
+      bytes: [ 0xc6, 0x03, 0x80, 0x99 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-v8.4a", "+rcpc-immo" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapursw x6, [x30]"
+
+  -
+    input:
+      bytes: [ 0xc6, 0x03, 0x90, 0x99 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-v8.4a", "+rcpc-immo" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapursw x6, [x30, #-256]"
+
+  -
+    input:
+      bytes: [ 0x07, 0xf0, 0x8f, 0x99 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-v8.4a", "+rcpc-immo" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapursw x7, [x0, #255]"
+
+  -
+    input:
+      bytes: [ 0xe8, 0x73, 0x80, 0x99 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-v8.4a", "+rcpc-immo" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapursw x8, [sp, #7]"
+
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0x00, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-v8.4a", "+rcpc-immo" ]
+    expected:
+      insns:
+        -
+          asm_text: "stlur x9, [x1]"
+
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0x10, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-v8.4a", "+rcpc-immo" ]
+    expected:
+      insns:
+        -
+          asm_text: "stlur x9, [x1, #-256]"
+
+  -
+    input:
+      bytes: [ 0x4a, 0xf0, 0x0f, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-v8.4a", "+rcpc-immo" ]
+    expected:
+      insns:
+        -
+          asm_text: "stlur x10, [x2, #255]"
+
+  -
+    input:
+      bytes: [ 0xeb, 0x83, 0x00, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-v8.4a", "+rcpc-immo" ]
+    expected:
+      insns:
+        -
+          asm_text: "stlur x11, [sp, #8]"
+
+  -
+    input:
+      bytes: [ 0x6c, 0x00, 0x40, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-v8.4a", "+rcpc-immo" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapur x12, [x3]"
+
+  -
+    input:
+      bytes: [ 0x6c, 0x00, 0x50, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-v8.4a", "+rcpc-immo" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapur x12, [x3, #-256]"
+
+  -
+    input:
+      bytes: [ 0x8d, 0xf0, 0x4f, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-v8.4a", "+rcpc-immo" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapur x13, [x4, #255]"
+
+  -
+    input:
+      bytes: [ 0xee, 0x93, 0x40, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-v8.4a", "+rcpc-immo" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapur x14, [sp, #9]"
diff --git a/tests/MC/AArch64/armv8.4a-trace.s.yaml b/tests/MC/AArch64/armv8.4a-trace.s.yaml
new file mode 100644
index 000000000..fbfdd5ca8
--- /dev/null
+++ b/tests/MC/AArch64/armv8.4a-trace.s.yaml
@@ -0,0 +1,140 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x12, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRFCR_EL1, x0"
+
+  -
+    input:
+      bytes: [ 0x20, 0x12, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRFCR_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x20, 0x12, 0x1d, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRFCR_EL12, x0"
+
+  -
+    input:
+      bytes: [ 0x20, 0x12, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, TRFCR_EL1"
+
+  -
+    input:
+      bytes: [ 0x20, 0x12, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, TRFCR_EL2"
+
+  -
+    input:
+      bytes: [ 0x20, 0x12, 0x3d, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, TRFCR_EL12"
+
+  -
+    input:
+      bytes: [ 0x5f, 0x22, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "tsb csync"
+
+  -
+    input:
+      bytes: [ 0x20, 0x12, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "tracev8.4" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRFCR_EL1, x0"
+
+  -
+    input:
+      bytes: [ 0x20, 0x12, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "tracev8.4" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRFCR_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x20, 0x12, 0x1d, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "tracev8.4" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRFCR_EL12, x0"
+
+  -
+    input:
+      bytes: [ 0x20, 0x12, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "tracev8.4" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, TRFCR_EL1"
+
+  -
+    input:
+      bytes: [ 0x20, 0x12, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "tracev8.4" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, TRFCR_EL2"
+
+  -
+    input:
+      bytes: [ 0x20, 0x12, 0x3d, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "tracev8.4" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, TRFCR_EL12"
+
+  -
+    input:
+      bytes: [ 0x5f, 0x22, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "tracev8.4" ]
+    expected:
+      insns:
+        -
+          asm_text: "tsb csync"
diff --git a/tests/MC/AArch64/armv8.4a-virt.s.yaml b/tests/MC/AArch64/armv8.4a-virt.s.yaml
new file mode 100644
index 000000000..97345dfff
--- /dev/null
+++ b/tests/MC/AArch64/armv8.4a-virt.s.yaml
@@ -0,0 +1,90 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x40, 0x26, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr VSTCR_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x26, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr VSTTBR_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x2c, 0x13, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SDER32_EL2, x12"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe4, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr CNTHVS_TVAL_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x40, 0xe4, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr CNTHVS_CVAL_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe4, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr CNTHVS_CTL_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe5, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr CNTHPS_TVAL_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x40, 0xe5, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr CNTHPS_CVAL_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe5, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr CNTHPS_CTL_EL2, x0"
diff --git a/tests/MC/AArch64/armv8.4a-vncr.s.yaml b/tests/MC/AArch64/armv8.4a-vncr.s.yaml
new file mode 100644
index 000000000..8566f7c41
--- /dev/null
+++ b/tests/MC/AArch64/armv8.4a-vncr.s.yaml
@@ -0,0 +1,20 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x22, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, VNCR_EL2"
+
+  -
+    input:
+      bytes: [ 0x00, 0x22, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr VNCR_EL2, x0"
diff --git a/tests/MC/AArch64/armv8.5a-altnzcv.s.yaml b/tests/MC/AArch64/armv8.5a-altnzcv.s.yaml
new file mode 100644
index 000000000..cefd7c601
--- /dev/null
+++ b/tests/MC/AArch64/armv8.5a-altnzcv.s.yaml
@@ -0,0 +1,40 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x3f, 0x40, 0x00, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.5a" ]
+    expected:
+      insns:
+        -
+          asm_text: "xaflag"
+
+  -
+    input:
+      bytes: [ 0x5f, 0x40, 0x00, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.5a" ]
+    expected:
+      insns:
+        -
+          asm_text: "axflag"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x40, 0x00, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a", "+altnzcv" ]
+    expected:
+      insns:
+        -
+          asm_text: "xaflag"
+
+  -
+    input:
+      bytes: [ 0x5f, 0x40, 0x00, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a", "+altnzcv" ]
+    expected:
+      insns:
+        -
+          asm_text: "axflag"
diff --git a/tests/MC/AArch64/armv8.5a-bti.s.yaml b/tests/MC/AArch64/armv8.5a-bti.s.yaml
new file mode 100644
index 000000000..940fbd730
--- /dev/null
+++ b/tests/MC/AArch64/armv8.5a-bti.s.yaml
@@ -0,0 +1,240 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x1f, 0x24, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "bti" ]
+    expected:
+      insns:
+        -
+          asm_text: "bti"
+
+  -
+    input:
+      bytes: [ 0x5f, 0x24, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "bti" ]
+    expected:
+      insns:
+        -
+          asm_text: "bti c"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x24, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "bti" ]
+    expected:
+      insns:
+        -
+          asm_text: "bti j"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x24, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "bti" ]
+    expected:
+      insns:
+        -
+          asm_text: "bti jc"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x24, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "bti" ]
+    expected:
+      insns:
+        -
+          asm_text: "bti"
+
+  -
+    input:
+      bytes: [ 0x5f, 0x24, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "bti" ]
+    expected:
+      insns:
+        -
+          asm_text: "bti c"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x24, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "bti" ]
+    expected:
+      insns:
+        -
+          asm_text: "bti j"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x24, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "bti" ]
+    expected:
+      insns:
+        -
+          asm_text: "bti jc"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x24, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.5a" ]
+    expected:
+      insns:
+        -
+          asm_text: "bti"
+
+  -
+    input:
+      bytes: [ 0x5f, 0x24, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.5a" ]
+    expected:
+      insns:
+        -
+          asm_text: "bti c"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x24, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.5a" ]
+    expected:
+      insns:
+        -
+          asm_text: "bti j"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x24, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.5a" ]
+    expected:
+      insns:
+        -
+          asm_text: "bti jc"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x24, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.5a" ]
+    expected:
+      insns:
+        -
+          asm_text: "bti"
+
+  -
+    input:
+      bytes: [ 0x5f, 0x24, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.5a" ]
+    expected:
+      insns:
+        -
+          asm_text: "bti c"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x24, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.5a" ]
+    expected:
+      insns:
+        -
+          asm_text: "bti j"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x24, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.5a" ]
+    expected:
+      insns:
+        -
+          asm_text: "bti jc"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x24, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-bti" ]
+    expected:
+      insns:
+        -
+          asm_text: "bti"
+
+  -
+    input:
+      bytes: [ 0x5f, 0x24, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-bti" ]
+    expected:
+      insns:
+        -
+          asm_text: "bti c"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x24, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-bti" ]
+    expected:
+      insns:
+        -
+          asm_text: "bti j"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x24, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-bti" ]
+    expected:
+      insns:
+        -
+          asm_text: "bti jc"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x24, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-bti" ]
+    expected:
+      insns:
+        -
+          asm_text: "bti"
+
+  -
+    input:
+      bytes: [ 0x5f, 0x24, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-bti" ]
+    expected:
+      insns:
+        -
+          asm_text: "bti c"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x24, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-bti" ]
+    expected:
+      insns:
+        -
+          asm_text: "bti j"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x24, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-bti" ]
+    expected:
+      insns:
+        -
+          asm_text: "bti jc"
diff --git a/tests/MC/AArch64/armv8.5a-frint.s.yaml b/tests/MC/AArch64/armv8.5a-frint.s.yaml
new file mode 100644
index 000000000..d4d7553dd
--- /dev/null
+++ b/tests/MC/AArch64/armv8.5a-frint.s.yaml
@@ -0,0 +1,400 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x40, 0x28, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.5a" ]
+    expected:
+      insns:
+        -
+          asm_text: "frint32z s0, s1"
+
+  -
+    input:
+      bytes: [ 0x20, 0x40, 0x68, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.5a" ]
+    expected:
+      insns:
+        -
+          asm_text: "frint32z d0, d1"
+
+  -
+    input:
+      bytes: [ 0x62, 0x40, 0x29, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.5a" ]
+    expected:
+      insns:
+        -
+          asm_text: "frint64z s2, s3"
+
+  -
+    input:
+      bytes: [ 0x62, 0x40, 0x69, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.5a" ]
+    expected:
+      insns:
+        -
+          asm_text: "frint64z d2, d3"
+
+  -
+    input:
+      bytes: [ 0xa4, 0xc0, 0x28, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.5a" ]
+    expected:
+      insns:
+        -
+          asm_text: "frint32x s4, s5"
+
+  -
+    input:
+      bytes: [ 0xa4, 0xc0, 0x68, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.5a" ]
+    expected:
+      insns:
+        -
+          asm_text: "frint32x d4, d5"
+
+  -
+    input:
+      bytes: [ 0xe6, 0xc0, 0x29, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.5a" ]
+    expected:
+      insns:
+        -
+          asm_text: "frint64x s6, s7"
+
+  -
+    input:
+      bytes: [ 0xe6, 0xc0, 0x69, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.5a" ]
+    expected:
+      insns:
+        -
+          asm_text: "frint64x d6, d7"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe8, 0x21, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.5a" ]
+    expected:
+      insns:
+        -
+          asm_text: "frint32z v0.2s, v1.2s"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe8, 0x61, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.5a" ]
+    expected:
+      insns:
+        -
+          asm_text: "frint32z v0.2d, v1.2d"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe8, 0x21, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.5a" ]
+    expected:
+      insns:
+        -
+          asm_text: "frint32z v0.4s, v1.4s"
+
+  -
+    input:
+      bytes: [ 0x62, 0xf8, 0x21, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.5a" ]
+    expected:
+      insns:
+        -
+          asm_text: "frint64z v2.2s, v3.2s"
+
+  -
+    input:
+      bytes: [ 0x62, 0xf8, 0x61, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.5a" ]
+    expected:
+      insns:
+        -
+          asm_text: "frint64z v2.2d, v3.2d"
+
+  -
+    input:
+      bytes: [ 0x62, 0xf8, 0x21, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.5a" ]
+    expected:
+      insns:
+        -
+          asm_text: "frint64z v2.4s, v3.4s"
+
+  -
+    input:
+      bytes: [ 0xa4, 0xe8, 0x21, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.5a" ]
+    expected:
+      insns:
+        -
+          asm_text: "frint32x v4.2s, v5.2s"
+
+  -
+    input:
+      bytes: [ 0xa4, 0xe8, 0x61, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.5a" ]
+    expected:
+      insns:
+        -
+          asm_text: "frint32x v4.2d, v5.2d"
+
+  -
+    input:
+      bytes: [ 0xa4, 0xe8, 0x21, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.5a" ]
+    expected:
+      insns:
+        -
+          asm_text: "frint32x v4.4s, v5.4s"
+
+  -
+    input:
+      bytes: [ 0xe6, 0xf8, 0x21, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.5a" ]
+    expected:
+      insns:
+        -
+          asm_text: "frint64x v6.2s, v7.2s"
+
+  -
+    input:
+      bytes: [ 0xe6, 0xf8, 0x61, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.5a" ]
+    expected:
+      insns:
+        -
+          asm_text: "frint64x v6.2d, v7.2d"
+
+  -
+    input:
+      bytes: [ 0xe6, 0xf8, 0x21, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.5a" ]
+    expected:
+      insns:
+        -
+          asm_text: "frint64x v6.4s, v7.4s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x40, 0x28, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a", "+fptoint" ]
+    expected:
+      insns:
+        -
+          asm_text: "frint32z s0, s1"
+
+  -
+    input:
+      bytes: [ 0x20, 0x40, 0x68, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a", "+fptoint" ]
+    expected:
+      insns:
+        -
+          asm_text: "frint32z d0, d1"
+
+  -
+    input:
+      bytes: [ 0x62, 0x40, 0x29, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a", "+fptoint" ]
+    expected:
+      insns:
+        -
+          asm_text: "frint64z s2, s3"
+
+  -
+    input:
+      bytes: [ 0x62, 0x40, 0x69, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a", "+fptoint" ]
+    expected:
+      insns:
+        -
+          asm_text: "frint64z d2, d3"
+
+  -
+    input:
+      bytes: [ 0xa4, 0xc0, 0x28, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a", "+fptoint" ]
+    expected:
+      insns:
+        -
+          asm_text: "frint32x s4, s5"
+
+  -
+    input:
+      bytes: [ 0xa4, 0xc0, 0x68, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a", "+fptoint" ]
+    expected:
+      insns:
+        -
+          asm_text: "frint32x d4, d5"
+
+  -
+    input:
+      bytes: [ 0xe6, 0xc0, 0x29, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a", "+fptoint" ]
+    expected:
+      insns:
+        -
+          asm_text: "frint64x s6, s7"
+
+  -
+    input:
+      bytes: [ 0xe6, 0xc0, 0x69, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a", "+fptoint" ]
+    expected:
+      insns:
+        -
+          asm_text: "frint64x d6, d7"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe8, 0x21, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a", "+fptoint" ]
+    expected:
+      insns:
+        -
+          asm_text: "frint32z v0.2s, v1.2s"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe8, 0x61, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a", "+fptoint" ]
+    expected:
+      insns:
+        -
+          asm_text: "frint32z v0.2d, v1.2d"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe8, 0x21, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a", "+fptoint" ]
+    expected:
+      insns:
+        -
+          asm_text: "frint32z v0.4s, v1.4s"
+
+  -
+    input:
+      bytes: [ 0x62, 0xf8, 0x21, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a", "+fptoint" ]
+    expected:
+      insns:
+        -
+          asm_text: "frint64z v2.2s, v3.2s"
+
+  -
+    input:
+      bytes: [ 0x62, 0xf8, 0x61, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a", "+fptoint" ]
+    expected:
+      insns:
+        -
+          asm_text: "frint64z v2.2d, v3.2d"
+
+  -
+    input:
+      bytes: [ 0x62, 0xf8, 0x21, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a", "+fptoint" ]
+    expected:
+      insns:
+        -
+          asm_text: "frint64z v2.4s, v3.4s"
+
+  -
+    input:
+      bytes: [ 0xa4, 0xe8, 0x21, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a", "+fptoint" ]
+    expected:
+      insns:
+        -
+          asm_text: "frint32x v4.2s, v5.2s"
+
+  -
+    input:
+      bytes: [ 0xa4, 0xe8, 0x61, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a", "+fptoint" ]
+    expected:
+      insns:
+        -
+          asm_text: "frint32x v4.2d, v5.2d"
+
+  -
+    input:
+      bytes: [ 0xa4, 0xe8, 0x21, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a", "+fptoint" ]
+    expected:
+      insns:
+        -
+          asm_text: "frint32x v4.4s, v5.4s"
+
+  -
+    input:
+      bytes: [ 0xe6, 0xf8, 0x21, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a", "+fptoint" ]
+    expected:
+      insns:
+        -
+          asm_text: "frint64x v6.2s, v7.2s"
+
+  -
+    input:
+      bytes: [ 0xe6, 0xf8, 0x61, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a", "+fptoint" ]
+    expected:
+      insns:
+        -
+          asm_text: "frint64x v6.2d, v7.2d"
+
+  -
+    input:
+      bytes: [ 0xe6, 0xf8, 0x21, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.4a", "+fptoint" ]
+    expected:
+      insns:
+        -
+          asm_text: "frint64x v6.4s, v7.4s"
diff --git a/tests/MC/AArch64/armv8.5a-mte.s.yaml b/tests/MC/AArch64/armv8.5a-mte.s.yaml
new file mode 100644
index 000000000..b4796e801
--- /dev/null
+++ b/tests/MC/AArch64/armv8.5a-mte.s.yaml
@@ -0,0 +1,1430 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x10, 0xdf, 0x9a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "irg x0, x1"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x10, 0xdf, 0x9a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "irg sp, x1"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x13, 0xdf, 0x9a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "irg x0, sp"
+
+  -
+    input:
+      bytes: [ 0x20, 0x10, 0xc2, 0x9a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "irg x0, x1, x2"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x10, 0xc2, 0x9a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "irg sp, x1, x2"
+
+  -
+    input:
+      bytes: [ 0x20, 0x04, 0x80, 0x91 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "addg x0, x1, #0, #1"
+
+  -
+    input:
+      bytes: [ 0x5f, 0x0c, 0x82, 0x91 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "addg sp, x2, #32, #3"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x17, 0x84, 0x91 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "addg x0, sp, #64, #5"
+
+  -
+    input:
+      bytes: [ 0x83, 0x18, 0xbf, 0x91 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "addg x3, x4, #1008, #6"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x3c, 0x87, 0x91 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "addg x5, x6, #112, #15"
+
+  -
+    input:
+      bytes: [ 0x20, 0x04, 0x80, 0xd1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "subg x0, x1, #0, #1"
+
+  -
+    input:
+      bytes: [ 0x5f, 0x0c, 0x82, 0xd1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "subg sp, x2, #32, #3"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x17, 0x84, 0xd1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "subg x0, sp, #64, #5"
+
+  -
+    input:
+      bytes: [ 0x83, 0x18, 0xbf, 0xd1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "subg x3, x4, #1008, #6"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x3c, 0x87, 0xd1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "subg x5, x6, #112, #15"
+
+  -
+    input:
+      bytes: [ 0x20, 0x14, 0xc2, 0x9a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "gmi x0, x1, x2"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x17, 0xc4, 0x9a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "gmi x3, sp, x4"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x14, 0xde, 0x9a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "gmi xzr, x0, x30"
+
+  -
+    input:
+      bytes: [ 0x1e, 0x14, 0xdf, 0x9a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "gmi x30, x0, xzr"
+
+  -
+    input:
+      bytes: [ 0x20, 0x08, 0x20, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "stg x0, [x1]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x08, 0x30, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "stg x1, [x1, #-4096]"
+
+  -
+    input:
+      bytes: [ 0x42, 0xf8, 0x2f, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "stg x2, [x2, #4080]"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x1b, 0x20, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "stg x3, [sp, #16]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1b, 0x20, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "stg sp, [sp, #16]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x08, 0x60, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "stzg x0, [x1]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x08, 0x70, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "stzg x1, [x1, #-4096]"
+
+  -
+    input:
+      bytes: [ 0x42, 0xf8, 0x6f, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "stzg x2, [x2, #4080]"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x1b, 0x60, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "stzg x3, [sp, #16]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1b, 0x60, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "stzg sp, [sp, #16]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x0c, 0x30, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "stg x0, [x1, #-4096]!"
+
+  -
+    input:
+      bytes: [ 0x41, 0xfc, 0x2f, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "stg x1, [x2, #4080]!"
+
+  -
+    input:
+      bytes: [ 0xe2, 0x1f, 0x20, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "stg x2, [sp, #16]!"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0x20, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "stg sp, [sp, #16]!"
+
+  -
+    input:
+      bytes: [ 0x20, 0x0c, 0x70, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "stzg x0, [x1, #-4096]!"
+
+  -
+    input:
+      bytes: [ 0x41, 0xfc, 0x6f, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "stzg x1, [x2, #4080]!"
+
+  -
+    input:
+      bytes: [ 0xe2, 0x1f, 0x60, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "stzg x2, [sp, #16]!"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0x60, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "stzg sp, [sp, #16]!"
+
+  -
+    input:
+      bytes: [ 0x20, 0x04, 0x30, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "stg x0, [x1], #-4096"
+
+  -
+    input:
+      bytes: [ 0x41, 0xf4, 0x2f, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "stg x1, [x2], #4080"
+
+  -
+    input:
+      bytes: [ 0xe2, 0x17, 0x20, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "stg x2, [sp], #16"
+
+  -
+    input:
+      bytes: [ 0xff, 0x17, 0x20, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "stg sp, [sp], #16"
+
+  -
+    input:
+      bytes: [ 0x20, 0x04, 0x70, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "stzg x0, [x1], #-4096"
+
+  -
+    input:
+      bytes: [ 0x41, 0xf4, 0x6f, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "stzg x1, [x2], #4080"
+
+  -
+    input:
+      bytes: [ 0xe2, 0x17, 0x60, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "stzg x2, [sp], #16"
+
+  -
+    input:
+      bytes: [ 0xff, 0x17, 0x60, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "stzg sp, [sp], #16"
+
+  -
+    input:
+      bytes: [ 0x20, 0x08, 0xa0, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "st2g x0, [x1]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x08, 0xb0, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "st2g x1, [x1, #-4096]"
+
+  -
+    input:
+      bytes: [ 0x42, 0xf8, 0xaf, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "st2g x2, [x2, #4080]"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x1b, 0xa0, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "st2g x3, [sp, #16]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1b, 0xa0, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "st2g sp, [sp, #16]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x08, 0xe0, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "stz2g x0, [x1]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x08, 0xf0, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "stz2g x1, [x1, #-4096]"
+
+  -
+    input:
+      bytes: [ 0x42, 0xf8, 0xef, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "stz2g x2, [x2, #4080]"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x1b, 0xe0, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "stz2g x3, [sp, #16]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1b, 0xe0, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "stz2g sp, [sp, #16]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x0c, 0xb0, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "st2g x0, [x1, #-4096]!"
+
+  -
+    input:
+      bytes: [ 0x41, 0xfc, 0xaf, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "st2g x1, [x2, #4080]!"
+
+  -
+    input:
+      bytes: [ 0xe2, 0x1f, 0xa0, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "st2g x2, [sp, #16]!"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0xa0, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "st2g sp, [sp, #16]!"
+
+  -
+    input:
+      bytes: [ 0x20, 0x0c, 0xf0, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "stz2g x0, [x1, #-4096]!"
+
+  -
+    input:
+      bytes: [ 0x41, 0xfc, 0xef, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "stz2g x1, [x2, #4080]!"
+
+  -
+    input:
+      bytes: [ 0xe2, 0x1f, 0xe0, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "stz2g x2, [sp, #16]!"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0xe0, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "stz2g sp, [sp, #16]!"
+
+  -
+    input:
+      bytes: [ 0x20, 0x04, 0xb0, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "st2g x0, [x1], #-4096"
+
+  -
+    input:
+      bytes: [ 0x41, 0xf4, 0xaf, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "st2g x1, [x2], #4080"
+
+  -
+    input:
+      bytes: [ 0xe2, 0x17, 0xa0, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "st2g x2, [sp], #16"
+
+  -
+    input:
+      bytes: [ 0xff, 0x17, 0xa0, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "st2g sp, [sp], #16"
+
+  -
+    input:
+      bytes: [ 0x20, 0x04, 0xf0, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "stz2g x0, [x1], #-4096"
+
+  -
+    input:
+      bytes: [ 0x41, 0xf4, 0xef, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "stz2g x1, [x2], #4080"
+
+  -
+    input:
+      bytes: [ 0xe2, 0x17, 0xe0, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "stz2g x2, [sp], #16"
+
+  -
+    input:
+      bytes: [ 0xff, 0x17, 0xe0, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "stz2g sp, [sp], #16"
+
+  -
+    input:
+      bytes: [ 0x40, 0x04, 0x00, 0x69 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "stgp x0, x1, [x2]"
+
+  -
+    input:
+      bytes: [ 0x40, 0x04, 0x20, 0x69 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "stgp x0, x1, [x2, #-1024]"
+
+  -
+    input:
+      bytes: [ 0x40, 0x84, 0x1f, 0x69 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "stgp x0, x1, [x2, #1008]"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x87, 0x00, 0x69 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "stgp x0, x1, [sp, #16]"
+
+  -
+    input:
+      bytes: [ 0x5f, 0x84, 0x00, 0x69 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "stgp xzr, x1, [x2, #16]"
+
+  -
+    input:
+      bytes: [ 0x40, 0xfc, 0x00, 0x69 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "stgp x0, xzr, [x2, #16]"
+
+  -
+    input:
+      bytes: [ 0x40, 0x04, 0xa0, 0x69 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "stgp x0, x1, [x2, #-1024]!"
+
+  -
+    input:
+      bytes: [ 0x40, 0x84, 0x9f, 0x69 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "stgp x0, x1, [x2, #1008]!"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x87, 0x80, 0x69 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "stgp x0, x1, [sp, #16]!"
+
+  -
+    input:
+      bytes: [ 0x5f, 0x84, 0x80, 0x69 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "stgp xzr, x1, [x2, #16]!"
+
+  -
+    input:
+      bytes: [ 0x40, 0xfc, 0x80, 0x69 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "stgp x0, xzr, [x2, #16]!"
+
+  -
+    input:
+      bytes: [ 0x40, 0x04, 0xa0, 0x68 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "stgp x0, x1, [x2], #-1024"
+
+  -
+    input:
+      bytes: [ 0x40, 0x84, 0x9f, 0x68 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "stgp x0, x1, [x2], #1008"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x87, 0x80, 0x68 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "stgp x0, x1, [sp], #16"
+
+  -
+    input:
+      bytes: [ 0x5f, 0x84, 0x80, 0x68 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "stgp xzr, x1, [x2], #16"
+
+  -
+    input:
+      bytes: [ 0x40, 0xfc, 0x80, 0x68 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "stgp x0, xzr, [x2], #16"
+
+  -
+    input:
+      bytes: [ 0x60, 0x76, 0x08, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "dc igvac, x0"
+
+  -
+    input:
+      bytes: [ 0x81, 0x76, 0x08, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "dc igsw, x1"
+
+  -
+    input:
+      bytes: [ 0x82, 0x7a, 0x08, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "dc cgsw, x2"
+
+  -
+    input:
+      bytes: [ 0x83, 0x7e, 0x08, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "dc cigsw, x3"
+
+  -
+    input:
+      bytes: [ 0x64, 0x7a, 0x0b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "dc cgvac, x4"
+
+  -
+    input:
+      bytes: [ 0x65, 0x7c, 0x0b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "dc cgvap, x5"
+
+  -
+    input:
+      bytes: [ 0x66, 0x7d, 0x0b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "dc cgvadp, x6"
+
+  -
+    input:
+      bytes: [ 0x67, 0x7e, 0x0b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "dc cigvac, x7"
+
+  -
+    input:
+      bytes: [ 0x68, 0x74, 0x0b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "dc gva, x8"
+
+  -
+    input:
+      bytes: [ 0xa9, 0x76, 0x08, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "dc igdvac, x9"
+
+  -
+    input:
+      bytes: [ 0xca, 0x76, 0x08, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "dc igdsw, x10"
+
+  -
+    input:
+      bytes: [ 0xcb, 0x7a, 0x08, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "dc cgdsw, x11"
+
+  -
+    input:
+      bytes: [ 0xcc, 0x7e, 0x08, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "dc cigdsw, x12"
+
+  -
+    input:
+      bytes: [ 0xad, 0x7a, 0x0b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "dc cgdvac, x13"
+
+  -
+    input:
+      bytes: [ 0xae, 0x7c, 0x0b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "dc cgdvap, x14"
+
+  -
+    input:
+      bytes: [ 0xaf, 0x7d, 0x0b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "dc cgdvadp, x15"
+
+  -
+    input:
+      bytes: [ 0xb0, 0x7e, 0x0b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "dc cigdvac, x16"
+
+  -
+    input:
+      bytes: [ 0x91, 0x74, 0x0b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "dc gzva, x17"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x42, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, TCO"
+
+  -
+    input:
+      bytes: [ 0xc1, 0x10, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x1, GCR_EL1"
+
+  -
+    input:
+      bytes: [ 0xa2, 0x10, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x2, RGSR_EL1"
+
+  -
+    input:
+      bytes: [ 0x03, 0x56, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, TFSR_EL1"
+
+  -
+    input:
+      bytes: [ 0x04, 0x56, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x4, TFSR_EL2"
+
+  -
+    input:
+      bytes: [ 0x05, 0x56, 0x3e, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x5, TFSR_EL3"
+
+  -
+    input:
+      bytes: [ 0x06, 0x56, 0x3d, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x6, TFSR_EL12"
+
+  -
+    input:
+      bytes: [ 0x27, 0x56, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x7, TFSRE0_EL1"
+
+  -
+    input:
+      bytes: [ 0x87, 0x00, 0x39, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x7, GMID_EL1"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x40, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TCO, #0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x42, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TCO, x0"
+
+  -
+    input:
+      bytes: [ 0xc1, 0x10, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr GCR_EL1, x1"
+
+  -
+    input:
+      bytes: [ 0xa2, 0x10, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr RGSR_EL1, x2"
+
+  -
+    input:
+      bytes: [ 0x03, 0x56, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TFSR_EL1, x3"
+
+  -
+    input:
+      bytes: [ 0x04, 0x56, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TFSR_EL2, x4"
+
+  -
+    input:
+      bytes: [ 0x05, 0x56, 0x1e, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TFSR_EL3, x5"
+
+  -
+    input:
+      bytes: [ 0x06, 0x56, 0x1d, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TFSR_EL12, x6"
+
+  -
+    input:
+      bytes: [ 0x27, 0x56, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TFSRE0_EL1, x7"
+
+  -
+    input:
+      bytes: [ 0x20, 0x00, 0xc2, 0x9a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "subp x0, x1, x2"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x03, 0xdf, 0x9a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "subp x0, sp, sp"
+
+  -
+    input:
+      bytes: [ 0x20, 0x00, 0xc2, 0xba ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "subps x0, x1, x2"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x03, 0xdf, 0xba ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "subps x0, sp, sp"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x00, 0xc1, 0xba ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "subps xzr, x0, x1"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x00, 0xc1, 0xba ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "subps xzr, x0, x1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x03, 0xdf, 0xba ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "subps xzr, sp, sp"
+
+  -
+    input:
+      bytes: [ 0xff, 0x03, 0xdf, 0xba ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "subps xzr, sp, sp"
+
+  -
+    input:
+      bytes: [ 0x20, 0x00, 0x60, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldg x0, [x1]"
+
+  -
+    input:
+      bytes: [ 0xe2, 0x03, 0x70, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldg x2, [sp, #-4096]"
+
+  -
+    input:
+      bytes: [ 0x83, 0xf0, 0x6f, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldg x3, [x4, #4080]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x00, 0xe0, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldgm x0, [x1]"
+
+  -
+    input:
+      bytes: [ 0xe1, 0x03, 0xe0, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldgm x1, [sp]"
+
+  -
+    input:
+      bytes: [ 0x5f, 0x00, 0xe0, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldgm xzr, [x2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x00, 0xa0, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "stgm x0, [x1]"
+
+  -
+    input:
+      bytes: [ 0xe1, 0x03, 0xa0, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "stgm x1, [sp]"
+
+  -
+    input:
+      bytes: [ 0x5f, 0x00, 0xa0, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "stgm xzr, [x2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x00, 0x20, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "stzgm x0, [x1]"
+
+  -
+    input:
+      bytes: [ 0xe1, 0x03, 0x20, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "stzgm x1, [sp]"
+
+  -
+    input:
+      bytes: [ 0x5f, 0x00, 0x20, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "mte" ]
+    expected:
+      insns:
+        -
+          asm_text: "stzgm xzr, [x2]"
diff --git a/tests/MC/AArch64/armv8.5a-persistent-memory.s.yaml b/tests/MC/AArch64/armv8.5a-persistent-memory.s.yaml
new file mode 100644
index 000000000..63be0f267
--- /dev/null
+++ b/tests/MC/AArch64/armv8.5a-persistent-memory.s.yaml
@@ -0,0 +1,20 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x27, 0x7d, 0x0b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ccdp" ]
+    expected:
+      insns:
+        -
+          asm_text: "dc cvadp, x7"
+
+  -
+    input:
+      bytes: [ 0x27, 0x7d, 0x0b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.5a" ]
+    expected:
+      insns:
+        -
+          asm_text: "dc cvadp, x7"
diff --git a/tests/MC/AArch64/armv8.5a-predres.s.yaml b/tests/MC/AArch64/armv8.5a-predres.s.yaml
new file mode 100644
index 000000000..b0d4585d9
--- /dev/null
+++ b/tests/MC/AArch64/armv8.5a-predres.s.yaml
@@ -0,0 +1,60 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x80, 0x73, 0x0b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "predres" ]
+    expected:
+      insns:
+        -
+          asm_text: "cfp rctx, x0"
+
+  -
+    input:
+      bytes: [ 0xa1, 0x73, 0x0b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "predres" ]
+    expected:
+      insns:
+        -
+          asm_text: "dvp rctx, x1"
+
+  -
+    input:
+      bytes: [ 0xe2, 0x73, 0x0b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "predres" ]
+    expected:
+      insns:
+        -
+          asm_text: "cpp rctx, x2"
+
+  -
+    input:
+      bytes: [ 0x80, 0x73, 0x0b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.5a" ]
+    expected:
+      insns:
+        -
+          asm_text: "cfp rctx, x0"
+
+  -
+    input:
+      bytes: [ 0xa1, 0x73, 0x0b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.5a" ]
+    expected:
+      insns:
+        -
+          asm_text: "dvp rctx, x1"
+
+  -
+    input:
+      bytes: [ 0xe2, 0x73, 0x0b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.5a" ]
+    expected:
+      insns:
+        -
+          asm_text: "cpp rctx, x2"
diff --git a/tests/MC/AArch64/armv8.5a-rand.s.yaml b/tests/MC/AArch64/armv8.5a-rand.s.yaml
new file mode 100644
index 000000000..64d81621f
--- /dev/null
+++ b/tests/MC/AArch64/armv8.5a-rand.s.yaml
@@ -0,0 +1,20 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x24, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "rand" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, RNDR"
+
+  -
+    input:
+      bytes: [ 0x21, 0x24, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "rand" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x1, RNDRRS"
diff --git a/tests/MC/AArch64/armv8.5a-sb.s.yaml b/tests/MC/AArch64/armv8.5a-sb.s.yaml
new file mode 100644
index 000000000..455376688
--- /dev/null
+++ b/tests/MC/AArch64/armv8.5a-sb.s.yaml
@@ -0,0 +1,20 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xff, 0x30, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "sb" ]
+    expected:
+      insns:
+        -
+          asm_text: "sb"
+
+  -
+    input:
+      bytes: [ 0xff, 0x30, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.5a" ]
+    expected:
+      insns:
+        -
+          asm_text: "sb"
diff --git a/tests/MC/AArch64/armv8.5a-specrestrict.s.yaml b/tests/MC/AArch64/armv8.5a-specrestrict.s.yaml
new file mode 100644
index 000000000..10460d274
--- /dev/null
+++ b/tests/MC/AArch64/armv8.5a-specrestrict.s.yaml
@@ -0,0 +1,220 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x89, 0x03, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "specrestrict" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, ID_PFR2_EL1"
+
+  -
+    input:
+      bytes: [ 0xe8, 0xd0, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "specrestrict" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x8, SCXTNUM_EL0"
+
+  -
+    input:
+      bytes: [ 0xe7, 0xd0, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "specrestrict" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x7, SCXTNUM_EL1"
+
+  -
+    input:
+      bytes: [ 0xe6, 0xd0, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "specrestrict" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x6, SCXTNUM_EL2"
+
+  -
+    input:
+      bytes: [ 0xe5, 0xd0, 0x3e, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "specrestrict" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x5, SCXTNUM_EL3"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xd0, 0x3d, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "specrestrict" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x4, SCXTNUM_EL12"
+
+  -
+    input:
+      bytes: [ 0xe8, 0xd0, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "specrestrict" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SCXTNUM_EL0, x8"
+
+  -
+    input:
+      bytes: [ 0xe7, 0xd0, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "specrestrict" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SCXTNUM_EL1, x7"
+
+  -
+    input:
+      bytes: [ 0xe6, 0xd0, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "specrestrict" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SCXTNUM_EL2, x6"
+
+  -
+    input:
+      bytes: [ 0xe5, 0xd0, 0x1e, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "specrestrict" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SCXTNUM_EL3, x5"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xd0, 0x1d, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "specrestrict" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SCXTNUM_EL12, x4"
+
+  -
+    input:
+      bytes: [ 0x89, 0x03, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.5a" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, ID_PFR2_EL1"
+
+  -
+    input:
+      bytes: [ 0xe8, 0xd0, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.5a" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x8, SCXTNUM_EL0"
+
+  -
+    input:
+      bytes: [ 0xe7, 0xd0, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.5a" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x7, SCXTNUM_EL1"
+
+  -
+    input:
+      bytes: [ 0xe6, 0xd0, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.5a" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x6, SCXTNUM_EL2"
+
+  -
+    input:
+      bytes: [ 0xe5, 0xd0, 0x3e, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.5a" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x5, SCXTNUM_EL3"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xd0, 0x3d, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.5a" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x4, SCXTNUM_EL12"
+
+  -
+    input:
+      bytes: [ 0xe8, 0xd0, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.5a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SCXTNUM_EL0, x8"
+
+  -
+    input:
+      bytes: [ 0xe7, 0xd0, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.5a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SCXTNUM_EL1, x7"
+
+  -
+    input:
+      bytes: [ 0xe6, 0xd0, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.5a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SCXTNUM_EL2, x6"
+
+  -
+    input:
+      bytes: [ 0xe5, 0xd0, 0x1e, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.5a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SCXTNUM_EL3, x5"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xd0, 0x1d, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.5a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SCXTNUM_EL12, x4"
diff --git a/tests/MC/AArch64/armv8.5a-ssbs.s.yaml b/tests/MC/AArch64/armv8.5a-ssbs.s.yaml
new file mode 100644
index 000000000..a9df26d14
--- /dev/null
+++ b/tests/MC/AArch64/armv8.5a-ssbs.s.yaml
@@ -0,0 +1,270 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xc2, 0x42, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssbs" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x2, SSBS"
+
+  -
+    input:
+      bytes: [ 0xc3, 0x42, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssbs" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SSBS, x3"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x41, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "ssbs" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SSBS, #1"
+
+  -
+    input:
+      bytes: [ 0xc2, 0x42, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.5a" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x2, SSBS"
+
+  -
+    input:
+      bytes: [ 0xc3, 0x42, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.5a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SSBS, x3"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x41, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.5a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SSBS, #1"
+
+  -
+    input:
+      bytes: [ 0xc2, 0x42, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a65" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x2, SSBS"
+
+  -
+    input:
+      bytes: [ 0xc3, 0x42, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a65" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SSBS, x3"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x41, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a65" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SSBS, #1"
+
+  -
+    input:
+      bytes: [ 0xc2, 0x42, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a65ae" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x2, SSBS"
+
+  -
+    input:
+      bytes: [ 0xc3, 0x42, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a65ae" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SSBS, x3"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x41, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a65ae" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SSBS, #1"
+
+  -
+    input:
+      bytes: [ 0xc2, 0x42, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a76" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x2, SSBS"
+
+  -
+    input:
+      bytes: [ 0xc3, 0x42, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a76" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SSBS, x3"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x41, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a76" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SSBS, #1"
+
+  -
+    input:
+      bytes: [ 0xc2, 0x42, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a76ae" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x2, SSBS"
+
+  -
+    input:
+      bytes: [ 0xc3, 0x42, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a76ae" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SSBS, x3"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x41, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cortex-a76ae" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SSBS, #1"
+
+  -
+    input:
+      bytes: [ 0xc2, 0x42, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "neoverse-e1" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x2, SSBS"
+
+  -
+    input:
+      bytes: [ 0xc3, 0x42, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "neoverse-e1" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SSBS, x3"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x41, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "neoverse-e1" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SSBS, #1"
+
+  -
+    input:
+      bytes: [ 0xc2, 0x42, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "neoverse-n1" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x2, SSBS"
+
+  -
+    input:
+      bytes: [ 0xc3, 0x42, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "neoverse-n1" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SSBS, x3"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x41, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "neoverse-n1" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SSBS, #1"
+
+  -
+    input:
+      bytes: [ 0xc2, 0x42, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "neoverse-n2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x2, SSBS"
+
+  -
+    input:
+      bytes: [ 0xc3, 0x42, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "neoverse-n2" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SSBS, x3"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x41, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "neoverse-n2" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SSBS, #1"
diff --git a/tests/MC/AArch64/armv8.6a-amvs.s.yaml b/tests/MC/AArch64/armv8.6a-amvs.s.yaml
new file mode 100644
index 000000000..f9732a163
--- /dev/null
+++ b/tests/MC/AArch64/armv8.6a-amvs.s.yaml
@@ -0,0 +1,3280 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xc0, 0xd2, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr S3_3_C13_C2_6, x0"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xd2, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMCG1IDR_EL0"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd8, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF00_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd8, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF01_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x40, 0xd8, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF02_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x60, 0xd8, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF03_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x80, 0xd8, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF04_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xd8, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF05_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xd8, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF06_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xd8, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF07_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd9, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF08_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd9, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF09_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x40, 0xd9, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF010_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x60, 0xd9, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF011_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x80, 0xd9, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF012_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xd9, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF013_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xd9, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF014_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xd9, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF015_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd8, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF00_EL2"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd8, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF01_EL2"
+
+  -
+    input:
+      bytes: [ 0x40, 0xd8, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF02_EL2"
+
+  -
+    input:
+      bytes: [ 0x60, 0xd8, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF03_EL2"
+
+  -
+    input:
+      bytes: [ 0x80, 0xd8, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF04_EL2"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xd8, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF05_EL2"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xd8, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF06_EL2"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xd8, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF07_EL2"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd9, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF08_EL2"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd9, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF09_EL2"
+
+  -
+    input:
+      bytes: [ 0x40, 0xd9, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF010_EL2"
+
+  -
+    input:
+      bytes: [ 0x60, 0xd9, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF011_EL2"
+
+  -
+    input:
+      bytes: [ 0x80, 0xd9, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF012_EL2"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xd9, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF013_EL2"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xd9, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF014_EL2"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xd9, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF015_EL2"
+
+  -
+    input:
+      bytes: [ 0x00, 0xda, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF10_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x20, 0xda, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF11_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x40, 0xda, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF12_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x60, 0xda, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF13_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x80, 0xda, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF14_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xda, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF15_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xda, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF16_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xda, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF17_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x00, 0xdb, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF18_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x20, 0xdb, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF19_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x40, 0xdb, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF110_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x60, 0xdb, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF111_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x80, 0xdb, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF112_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xdb, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF113_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xdb, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF114_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xdb, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF115_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x00, 0xda, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF10_EL2"
+
+  -
+    input:
+      bytes: [ 0x20, 0xda, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF11_EL2"
+
+  -
+    input:
+      bytes: [ 0x40, 0xda, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF12_EL2"
+
+  -
+    input:
+      bytes: [ 0x60, 0xda, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF13_EL2"
+
+  -
+    input:
+      bytes: [ 0x80, 0xda, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF14_EL2"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xda, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF15_EL2"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xda, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF16_EL2"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xda, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF17_EL2"
+
+  -
+    input:
+      bytes: [ 0x00, 0xdb, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF18_EL2"
+
+  -
+    input:
+      bytes: [ 0x20, 0xdb, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF19_EL2"
+
+  -
+    input:
+      bytes: [ 0x40, 0xdb, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF110_EL2"
+
+  -
+    input:
+      bytes: [ 0x60, 0xdb, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF111_EL2"
+
+  -
+    input:
+      bytes: [ 0x80, 0xdb, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF112_EL2"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xdb, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF113_EL2"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xdb, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF114_EL2"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xdb, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF115_EL2"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xd2, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr S3_3_C13_C2_6, x0"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xd2, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMCG1IDR_EL0"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd8, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF00_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd8, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF01_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x40, 0xd8, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF02_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x60, 0xd8, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF03_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x80, 0xd8, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF04_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xd8, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF05_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xd8, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF06_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xd8, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF07_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd9, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF08_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd9, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF09_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x40, 0xd9, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF010_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x60, 0xd9, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF011_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x80, 0xd9, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF012_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xd9, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF013_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xd9, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF014_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xd9, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF015_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd8, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF00_EL2"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd8, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF01_EL2"
+
+  -
+    input:
+      bytes: [ 0x40, 0xd8, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF02_EL2"
+
+  -
+    input:
+      bytes: [ 0x60, 0xd8, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF03_EL2"
+
+  -
+    input:
+      bytes: [ 0x80, 0xd8, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF04_EL2"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xd8, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF05_EL2"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xd8, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF06_EL2"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xd8, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF07_EL2"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd9, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF08_EL2"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd9, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF09_EL2"
+
+  -
+    input:
+      bytes: [ 0x40, 0xd9, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF010_EL2"
+
+  -
+    input:
+      bytes: [ 0x60, 0xd9, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF011_EL2"
+
+  -
+    input:
+      bytes: [ 0x80, 0xd9, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF012_EL2"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xd9, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF013_EL2"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xd9, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF014_EL2"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xd9, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF015_EL2"
+
+  -
+    input:
+      bytes: [ 0x00, 0xda, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF10_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x20, 0xda, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF11_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x40, 0xda, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF12_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x60, 0xda, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF13_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x80, 0xda, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF14_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xda, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF15_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xda, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF16_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xda, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF17_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x00, 0xdb, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF18_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x20, 0xdb, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF19_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x40, 0xdb, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF110_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x60, 0xdb, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF111_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x80, 0xdb, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF112_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xdb, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF113_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xdb, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF114_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xdb, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF115_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x00, 0xda, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF10_EL2"
+
+  -
+    input:
+      bytes: [ 0x20, 0xda, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF11_EL2"
+
+  -
+    input:
+      bytes: [ 0x40, 0xda, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF12_EL2"
+
+  -
+    input:
+      bytes: [ 0x60, 0xda, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF13_EL2"
+
+  -
+    input:
+      bytes: [ 0x80, 0xda, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF14_EL2"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xda, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF15_EL2"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xda, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF16_EL2"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xda, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF17_EL2"
+
+  -
+    input:
+      bytes: [ 0x00, 0xdb, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF18_EL2"
+
+  -
+    input:
+      bytes: [ 0x20, 0xdb, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF19_EL2"
+
+  -
+    input:
+      bytes: [ 0x40, 0xdb, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF110_EL2"
+
+  -
+    input:
+      bytes: [ 0x60, 0xdb, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF111_EL2"
+
+  -
+    input:
+      bytes: [ 0x80, 0xdb, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF112_EL2"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xdb, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF113_EL2"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xdb, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF114_EL2"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xdb, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF115_EL2"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xd2, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr S3_3_C13_C2_6, x0"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xd2, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMCG1IDR_EL0"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd8, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF00_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd8, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF01_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x40, 0xd8, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF02_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x60, 0xd8, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF03_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x80, 0xd8, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF04_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xd8, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF05_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xd8, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF06_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xd8, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF07_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd9, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF08_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd9, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF09_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x40, 0xd9, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF010_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x60, 0xd9, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF011_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x80, 0xd9, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF012_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xd9, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF013_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xd9, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF014_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xd9, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF015_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd8, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF00_EL2"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd8, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF01_EL2"
+
+  -
+    input:
+      bytes: [ 0x40, 0xd8, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF02_EL2"
+
+  -
+    input:
+      bytes: [ 0x60, 0xd8, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF03_EL2"
+
+  -
+    input:
+      bytes: [ 0x80, 0xd8, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF04_EL2"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xd8, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF05_EL2"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xd8, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF06_EL2"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xd8, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF07_EL2"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd9, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF08_EL2"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd9, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF09_EL2"
+
+  -
+    input:
+      bytes: [ 0x40, 0xd9, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF010_EL2"
+
+  -
+    input:
+      bytes: [ 0x60, 0xd9, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF011_EL2"
+
+  -
+    input:
+      bytes: [ 0x80, 0xd9, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF012_EL2"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xd9, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF013_EL2"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xd9, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF014_EL2"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xd9, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF015_EL2"
+
+  -
+    input:
+      bytes: [ 0x00, 0xda, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF10_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x20, 0xda, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF11_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x40, 0xda, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF12_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x60, 0xda, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF13_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x80, 0xda, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF14_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xda, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF15_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xda, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF16_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xda, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF17_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x00, 0xdb, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF18_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x20, 0xdb, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF19_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x40, 0xdb, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF110_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x60, 0xdb, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF111_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x80, 0xdb, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF112_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xdb, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF113_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xdb, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF114_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xdb, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF115_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x00, 0xda, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF10_EL2"
+
+  -
+    input:
+      bytes: [ 0x20, 0xda, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF11_EL2"
+
+  -
+    input:
+      bytes: [ 0x40, 0xda, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF12_EL2"
+
+  -
+    input:
+      bytes: [ 0x60, 0xda, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF13_EL2"
+
+  -
+    input:
+      bytes: [ 0x80, 0xda, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF14_EL2"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xda, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF15_EL2"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xda, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF16_EL2"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xda, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF17_EL2"
+
+  -
+    input:
+      bytes: [ 0x00, 0xdb, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF18_EL2"
+
+  -
+    input:
+      bytes: [ 0x20, 0xdb, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF19_EL2"
+
+  -
+    input:
+      bytes: [ 0x40, 0xdb, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF110_EL2"
+
+  -
+    input:
+      bytes: [ 0x60, 0xdb, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF111_EL2"
+
+  -
+    input:
+      bytes: [ 0x80, 0xdb, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF112_EL2"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xdb, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF113_EL2"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xdb, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF114_EL2"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xdb, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF115_EL2"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xd2, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMCG1IDR_EL0"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd8, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF00_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd8, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF01_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x40, 0xd8, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF02_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x60, 0xd8, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF03_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x80, 0xd8, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF04_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xd8, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF05_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xd8, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF06_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xd8, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF07_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd9, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF08_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd9, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF09_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x40, 0xd9, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF010_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x60, 0xd9, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF011_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x80, 0xd9, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF012_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xd9, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF013_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xd9, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF014_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xd9, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF015_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd8, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF00_EL2"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd8, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF01_EL2"
+
+  -
+    input:
+      bytes: [ 0x40, 0xd8, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF02_EL2"
+
+  -
+    input:
+      bytes: [ 0x60, 0xd8, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF03_EL2"
+
+  -
+    input:
+      bytes: [ 0x80, 0xd8, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF04_EL2"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xd8, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF05_EL2"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xd8, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF06_EL2"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xd8, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF07_EL2"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd9, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF08_EL2"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd9, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF09_EL2"
+
+  -
+    input:
+      bytes: [ 0x40, 0xd9, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF010_EL2"
+
+  -
+    input:
+      bytes: [ 0x60, 0xd9, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF011_EL2"
+
+  -
+    input:
+      bytes: [ 0x80, 0xd9, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF012_EL2"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xd9, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF013_EL2"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xd9, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF014_EL2"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xd9, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF015_EL2"
+
+  -
+    input:
+      bytes: [ 0x00, 0xda, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF10_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x20, 0xda, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF11_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x40, 0xda, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF12_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x60, 0xda, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF13_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x80, 0xda, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF14_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xda, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF15_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xda, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF16_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xda, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF17_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x00, 0xdb, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF18_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x20, 0xdb, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF19_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x40, 0xdb, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF110_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x60, 0xdb, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF111_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x80, 0xdb, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF112_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xdb, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF113_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xdb, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF114_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xdb, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF115_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x00, 0xda, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF10_EL2"
+
+  -
+    input:
+      bytes: [ 0x20, 0xda, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF11_EL2"
+
+  -
+    input:
+      bytes: [ 0x40, 0xda, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF12_EL2"
+
+  -
+    input:
+      bytes: [ 0x60, 0xda, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF13_EL2"
+
+  -
+    input:
+      bytes: [ 0x80, 0xda, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF14_EL2"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xda, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF15_EL2"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xda, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF16_EL2"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xda, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF17_EL2"
+
+  -
+    input:
+      bytes: [ 0x00, 0xdb, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF18_EL2"
+
+  -
+    input:
+      bytes: [ 0x20, 0xdb, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF19_EL2"
+
+  -
+    input:
+      bytes: [ 0x40, 0xdb, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF110_EL2"
+
+  -
+    input:
+      bytes: [ 0x60, 0xdb, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF111_EL2"
+
+  -
+    input:
+      bytes: [ 0x80, 0xdb, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF112_EL2"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xdb, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF113_EL2"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xdb, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF114_EL2"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xdb, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "amvs" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF115_EL2"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xd2, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMCG1IDR_EL0"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd8, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF00_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd8, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF01_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x40, 0xd8, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF02_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x60, 0xd8, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF03_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x80, 0xd8, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF04_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xd8, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF05_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xd8, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF06_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xd8, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF07_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd9, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF08_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd9, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF09_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x40, 0xd9, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF010_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x60, 0xd9, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF011_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x80, 0xd9, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF012_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xd9, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF013_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xd9, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF014_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xd9, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF015_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd8, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF00_EL2"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd8, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF01_EL2"
+
+  -
+    input:
+      bytes: [ 0x40, 0xd8, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF02_EL2"
+
+  -
+    input:
+      bytes: [ 0x60, 0xd8, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF03_EL2"
+
+  -
+    input:
+      bytes: [ 0x80, 0xd8, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF04_EL2"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xd8, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF05_EL2"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xd8, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF06_EL2"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xd8, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF07_EL2"
+
+  -
+    input:
+      bytes: [ 0x00, 0xd9, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF08_EL2"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd9, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF09_EL2"
+
+  -
+    input:
+      bytes: [ 0x40, 0xd9, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF010_EL2"
+
+  -
+    input:
+      bytes: [ 0x60, 0xd9, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF011_EL2"
+
+  -
+    input:
+      bytes: [ 0x80, 0xd9, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF012_EL2"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xd9, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF013_EL2"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xd9, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF014_EL2"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xd9, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF015_EL2"
+
+  -
+    input:
+      bytes: [ 0x00, 0xda, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF10_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x20, 0xda, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF11_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x40, 0xda, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF12_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x60, 0xda, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF13_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x80, 0xda, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF14_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xda, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF15_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xda, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF16_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xda, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF17_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x00, 0xdb, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF18_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x20, 0xdb, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF19_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x40, 0xdb, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF110_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x60, 0xdb, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF111_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x80, 0xdb, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF112_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xdb, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF113_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xdb, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF114_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xdb, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMEVCNTVOFF115_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x00, 0xda, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF10_EL2"
+
+  -
+    input:
+      bytes: [ 0x20, 0xda, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF11_EL2"
+
+  -
+    input:
+      bytes: [ 0x40, 0xda, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF12_EL2"
+
+  -
+    input:
+      bytes: [ 0x60, 0xda, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF13_EL2"
+
+  -
+    input:
+      bytes: [ 0x80, 0xda, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF14_EL2"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xda, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF15_EL2"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xda, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF16_EL2"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xda, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF17_EL2"
+
+  -
+    input:
+      bytes: [ 0x00, 0xdb, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF18_EL2"
+
+  -
+    input:
+      bytes: [ 0x20, 0xdb, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF19_EL2"
+
+  -
+    input:
+      bytes: [ 0x40, 0xdb, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF110_EL2"
+
+  -
+    input:
+      bytes: [ 0x60, 0xdb, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF111_EL2"
+
+  -
+    input:
+      bytes: [ 0x80, 0xdb, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF112_EL2"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xdb, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF113_EL2"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xdb, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF114_EL2"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xdb, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, AMEVCNTVOFF115_EL2"
diff --git a/tests/MC/AArch64/armv8.6a-bf16.s.yaml b/tests/MC/AArch64/armv8.6a-bf16.s.yaml
new file mode 100644
index 000000000..a94d431ad
--- /dev/null
+++ b/tests/MC/AArch64/armv8.6a-bf16.s.yaml
@@ -0,0 +1,690 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x62, 0xfc, 0x44, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot v2.2s, v3.4h, v4.4h"
+
+  -
+    input:
+      bytes: [ 0x62, 0xfc, 0x44, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot v2.4s, v3.8h, v4.8h"
+
+  -
+    input:
+      bytes: [ 0x62, 0xf0, 0x44, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot v2.2s, v3.4h, v4.2h[0]"
+
+  -
+    input:
+      bytes: [ 0x62, 0xf0, 0x64, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot v2.2s, v3.4h, v4.2h[1]"
+
+  -
+    input:
+      bytes: [ 0x62, 0xf8, 0x44, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot v2.2s, v3.4h, v4.2h[2]"
+
+  -
+    input:
+      bytes: [ 0x62, 0xf8, 0x64, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot v2.2s, v3.4h, v4.2h[3]"
+
+  -
+    input:
+      bytes: [ 0x62, 0xf0, 0x44, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot v2.4s, v3.8h, v4.2h[0]"
+
+  -
+    input:
+      bytes: [ 0x62, 0xf0, 0x64, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot v2.4s, v3.8h, v4.2h[1]"
+
+  -
+    input:
+      bytes: [ 0x62, 0xf8, 0x44, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot v2.4s, v3.8h, v4.2h[2]"
+
+  -
+    input:
+      bytes: [ 0x62, 0xf8, 0x64, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot v2.4s, v3.8h, v4.2h[3]"
+
+  -
+    input:
+      bytes: [ 0x62, 0xec, 0x44, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmmla v2.4s, v3.8h, v4.8h"
+
+  -
+    input:
+      bytes: [ 0x83, 0xec, 0x45, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmmla v3.4s, v4.8h, v5.8h"
+
+  -
+    input:
+      bytes: [ 0xa5, 0x68, 0xa1, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfcvtn v5.4h, v5.4s"
+
+  -
+    input:
+      bytes: [ 0xa5, 0x68, 0xa1, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfcvtn2 v5.8h, v5.4s"
+
+  -
+    input:
+      bytes: [ 0x65, 0x40, 0x63, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfcvt h5, s3"
+
+  -
+    input:
+      bytes: [ 0xaa, 0xfe, 0xce, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlalb v10.4s, v21.8h, v14.8h"
+
+  -
+    input:
+      bytes: [ 0xd5, 0xfd, 0xca, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlalt v21.4s, v14.8h, v10.8h"
+
+  -
+    input:
+      bytes: [ 0xae, 0xf2, 0xda, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlalb v14.4s, v21.8h, v10.h[1]"
+
+  -
+    input:
+      bytes: [ 0xae, 0xf2, 0xea, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlalb v14.4s, v21.8h, v10.h[2]"
+
+  -
+    input:
+      bytes: [ 0xae, 0xfa, 0xfa, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlalb v14.4s, v21.8h, v10.h[7]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf1, 0xde, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlalt v21.4s, v10.8h, v14.h[1]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf1, 0xee, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlalt v21.4s, v10.8h, v14.h[2]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf9, 0xfe, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "bf16" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlalt v21.4s, v10.8h, v14.h[7]"
+
+  -
+    input:
+      bytes: [ 0x62, 0xfc, 0x44, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot v2.2s, v3.4h, v4.4h"
+
+  -
+    input:
+      bytes: [ 0x62, 0xfc, 0x44, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot v2.4s, v3.8h, v4.8h"
+
+  -
+    input:
+      bytes: [ 0x62, 0xf0, 0x44, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot v2.2s, v3.4h, v4.2h[0]"
+
+  -
+    input:
+      bytes: [ 0x62, 0xf0, 0x64, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot v2.2s, v3.4h, v4.2h[1]"
+
+  -
+    input:
+      bytes: [ 0x62, 0xf8, 0x44, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot v2.2s, v3.4h, v4.2h[2]"
+
+  -
+    input:
+      bytes: [ 0x62, 0xf8, 0x64, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot v2.2s, v3.4h, v4.2h[3]"
+
+  -
+    input:
+      bytes: [ 0x62, 0xf0, 0x44, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot v2.4s, v3.8h, v4.2h[0]"
+
+  -
+    input:
+      bytes: [ 0x62, 0xf0, 0x64, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot v2.4s, v3.8h, v4.2h[1]"
+
+  -
+    input:
+      bytes: [ 0x62, 0xf8, 0x44, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot v2.4s, v3.8h, v4.2h[2]"
+
+  -
+    input:
+      bytes: [ 0x62, 0xf8, 0x64, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot v2.4s, v3.8h, v4.2h[3]"
+
+  -
+    input:
+      bytes: [ 0x62, 0xec, 0x44, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmmla v2.4s, v3.8h, v4.8h"
+
+  -
+    input:
+      bytes: [ 0x83, 0xec, 0x45, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmmla v3.4s, v4.8h, v5.8h"
+
+  -
+    input:
+      bytes: [ 0xa5, 0x68, 0xa1, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfcvtn v5.4h, v5.4s"
+
+  -
+    input:
+      bytes: [ 0xa5, 0x68, 0xa1, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfcvtn2 v5.8h, v5.4s"
+
+  -
+    input:
+      bytes: [ 0x65, 0x40, 0x63, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfcvt h5, s3"
+
+  -
+    input:
+      bytes: [ 0xaa, 0xfe, 0xce, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlalb v10.4s, v21.8h, v14.8h"
+
+  -
+    input:
+      bytes: [ 0xd5, 0xfd, 0xca, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlalt v21.4s, v14.8h, v10.8h"
+
+  -
+    input:
+      bytes: [ 0xae, 0xf2, 0xda, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlalb v14.4s, v21.8h, v10.h[1]"
+
+  -
+    input:
+      bytes: [ 0xae, 0xf2, 0xea, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlalb v14.4s, v21.8h, v10.h[2]"
+
+  -
+    input:
+      bytes: [ 0xae, 0xfa, 0xfa, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlalb v14.4s, v21.8h, v10.h[7]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf1, 0xde, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlalt v21.4s, v10.8h, v14.h[1]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf1, 0xee, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlalt v21.4s, v10.8h, v14.h[2]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf9, 0xfe, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlalt v21.4s, v10.8h, v14.h[7]"
+
+  -
+    input:
+      bytes: [ 0x62, 0xfc, 0x44, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "all" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot v2.2s, v3.4h, v4.4h"
+
+  -
+    input:
+      bytes: [ 0x62, 0xfc, 0x44, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "all" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot v2.4s, v3.8h, v4.8h"
+
+  -
+    input:
+      bytes: [ 0x62, 0xf0, 0x44, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "all" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot v2.2s, v3.4h, v4.2h[0]"
+
+  -
+    input:
+      bytes: [ 0x62, 0xf0, 0x64, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "all" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot v2.2s, v3.4h, v4.2h[1]"
+
+  -
+    input:
+      bytes: [ 0x62, 0xf8, 0x44, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "all" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot v2.2s, v3.4h, v4.2h[2]"
+
+  -
+    input:
+      bytes: [ 0x62, 0xf8, 0x64, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "all" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot v2.2s, v3.4h, v4.2h[3]"
+
+  -
+    input:
+      bytes: [ 0x62, 0xf0, 0x44, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "all" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot v2.4s, v3.8h, v4.2h[0]"
+
+  -
+    input:
+      bytes: [ 0x62, 0xf0, 0x64, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "all" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot v2.4s, v3.8h, v4.2h[1]"
+
+  -
+    input:
+      bytes: [ 0x62, 0xf8, 0x44, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "all" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot v2.4s, v3.8h, v4.2h[2]"
+
+  -
+    input:
+      bytes: [ 0x62, 0xf8, 0x64, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "all" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfdot v2.4s, v3.8h, v4.2h[3]"
+
+  -
+    input:
+      bytes: [ 0x62, 0xec, 0x44, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "all" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmmla v2.4s, v3.8h, v4.8h"
+
+  -
+    input:
+      bytes: [ 0x83, 0xec, 0x45, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "all" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmmla v3.4s, v4.8h, v5.8h"
+
+  -
+    input:
+      bytes: [ 0xa5, 0x68, 0xa1, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "all" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfcvtn v5.4h, v5.4s"
+
+  -
+    input:
+      bytes: [ 0xa5, 0x68, 0xa1, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "all" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfcvtn2 v5.8h, v5.4s"
+
+  -
+    input:
+      bytes: [ 0x65, 0x40, 0x63, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "all" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfcvt h5, s3"
+
+  -
+    input:
+      bytes: [ 0xaa, 0xfe, 0xce, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "all" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlalb v10.4s, v21.8h, v14.8h"
+
+  -
+    input:
+      bytes: [ 0xd5, 0xfd, 0xca, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "all" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlalt v21.4s, v14.8h, v10.8h"
+
+  -
+    input:
+      bytes: [ 0xae, 0xf2, 0xda, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "all" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlalb v14.4s, v21.8h, v10.h[1]"
+
+  -
+    input:
+      bytes: [ 0xae, 0xf2, 0xea, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "all" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlalb v14.4s, v21.8h, v10.h[2]"
+
+  -
+    input:
+      bytes: [ 0xae, 0xfa, 0xfa, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "all" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlalb v14.4s, v21.8h, v10.h[7]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf1, 0xde, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "all" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlalt v21.4s, v10.8h, v14.h[1]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf1, 0xee, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "all" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlalt v21.4s, v10.8h, v14.h[2]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf9, 0xfe, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "all" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfmlalt v21.4s, v10.8h, v14.h[7]"
diff --git a/tests/MC/AArch64/armv8.6a-fgt.s.yaml b/tests/MC/AArch64/armv8.6a-fgt.s.yaml
new file mode 100644
index 000000000..58c94d178
--- /dev/null
+++ b/tests/MC/AArch64/armv8.6a-fgt.s.yaml
@@ -0,0 +1,440 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x80, 0x11, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fgt" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr HFGRTR_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0xa5, 0x11, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fgt" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr HFGWTR_EL2, x5"
+
+  -
+    input:
+      bytes: [ 0xca, 0x11, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fgt" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr HFGITR_EL2, x10"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x31, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fgt" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr HDFGRTR_EL2, x15"
+
+  -
+    input:
+      bytes: [ 0xb4, 0x31, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fgt" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr HDFGWTR_EL2, x20"
+
+  -
+    input:
+      bytes: [ 0xd9, 0x31, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fgt" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr HAFGRTR_EL2, x25"
+
+  -
+    input:
+      bytes: [ 0x9e, 0x11, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fgt" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x30, HFGRTR_EL2"
+
+  -
+    input:
+      bytes: [ 0xb9, 0x11, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fgt" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x25, HFGWTR_EL2"
+
+  -
+    input:
+      bytes: [ 0xd4, 0x11, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fgt" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x20, HFGITR_EL2"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x31, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fgt" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x15, HDFGRTR_EL2"
+
+  -
+    input:
+      bytes: [ 0xaa, 0x31, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fgt" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x10, HDFGWTR_EL2"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x31, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fgt" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x5, HAFGRTR_EL2"
+
+  -
+    input:
+      bytes: [ 0x03, 0x31, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fgt" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, HDFGRTR2_EL2"
+
+  -
+    input:
+      bytes: [ 0x23, 0x31, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fgt" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, HDFGWTR2_EL2"
+
+  -
+    input:
+      bytes: [ 0x43, 0x31, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fgt" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, HFGRTR2_EL2"
+
+  -
+    input:
+      bytes: [ 0x63, 0x31, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fgt" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, HFGWTR2_EL2"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x31, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fgt" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, HFGITR2_EL2"
+
+  -
+    input:
+      bytes: [ 0x03, 0x31, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fgt" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr HDFGRTR2_EL2, x3"
+
+  -
+    input:
+      bytes: [ 0x23, 0x31, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fgt" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr HDFGWTR2_EL2, x3"
+
+  -
+    input:
+      bytes: [ 0x43, 0x31, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fgt" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr HFGRTR2_EL2, x3"
+
+  -
+    input:
+      bytes: [ 0x63, 0x31, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fgt" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr HFGWTR2_EL2, x3"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x31, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "fgt" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr HFGITR2_EL2, x3"
+
+  -
+    input:
+      bytes: [ 0x80, 0x11, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr HFGRTR_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0xa5, 0x11, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr HFGWTR_EL2, x5"
+
+  -
+    input:
+      bytes: [ 0xca, 0x11, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr HFGITR_EL2, x10"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x31, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr HDFGRTR_EL2, x15"
+
+  -
+    input:
+      bytes: [ 0xb4, 0x31, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr HDFGWTR_EL2, x20"
+
+  -
+    input:
+      bytes: [ 0xd9, 0x31, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr HAFGRTR_EL2, x25"
+
+  -
+    input:
+      bytes: [ 0x9e, 0x11, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x30, HFGRTR_EL2"
+
+  -
+    input:
+      bytes: [ 0xb9, 0x11, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x25, HFGWTR_EL2"
+
+  -
+    input:
+      bytes: [ 0xd4, 0x11, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x20, HFGITR_EL2"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x31, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x15, HDFGRTR_EL2"
+
+  -
+    input:
+      bytes: [ 0xaa, 0x31, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x10, HDFGWTR_EL2"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x31, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x5, HAFGRTR_EL2"
+
+  -
+    input:
+      bytes: [ 0x03, 0x31, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, HDFGRTR2_EL2"
+
+  -
+    input:
+      bytes: [ 0x23, 0x31, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, HDFGWTR2_EL2"
+
+  -
+    input:
+      bytes: [ 0x43, 0x31, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, HFGRTR2_EL2"
+
+  -
+    input:
+      bytes: [ 0x63, 0x31, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, HFGWTR2_EL2"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x31, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, HFGITR2_EL2"
+
+  -
+    input:
+      bytes: [ 0x03, 0x31, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr HDFGRTR2_EL2, x3"
+
+  -
+    input:
+      bytes: [ 0x23, 0x31, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr HDFGWTR2_EL2, x3"
+
+  -
+    input:
+      bytes: [ 0x43, 0x31, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr HFGRTR2_EL2, x3"
+
+  -
+    input:
+      bytes: [ 0x63, 0x31, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr HFGWTR2_EL2, x3"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x31, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr HFGITR2_EL2, x3"
diff --git a/tests/MC/AArch64/armv8.6a-simd-matmul.s.yaml b/tests/MC/AArch64/armv8.6a-simd-matmul.s.yaml
new file mode 100644
index 000000000..9906268d1
--- /dev/null
+++ b/tests/MC/AArch64/armv8.6a-simd-matmul.s.yaml
@@ -0,0 +1,180 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x01, 0xa6, 0x9f, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "i8mm" ]
+    expected:
+      insns:
+        -
+          asm_text: "smmla v1.4s, v16.16b, v31.16b"
+
+  -
+    input:
+      bytes: [ 0x01, 0xa6, 0x9f, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "i8mm" ]
+    expected:
+      insns:
+        -
+          asm_text: "ummla v1.4s, v16.16b, v31.16b"
+
+  -
+    input:
+      bytes: [ 0x01, 0xae, 0x9f, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "i8mm" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmmla v1.4s, v16.16b, v31.16b"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x9d, 0x9e, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "i8mm" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot v3.2s, v15.8b, v30.8b"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x9d, 0x9e, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "i8mm" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot v3.4s, v15.16b, v30.16b"
+
+  -
+    input:
+      bytes: [ 0x3f, 0xf8, 0xa2, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "i8mm" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot v31.2s, v1.8b, v2.4b[3]"
+
+  -
+    input:
+      bytes: [ 0x3f, 0xf8, 0xa2, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "i8mm" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot v31.4s, v1.16b, v2.4b[3]"
+
+  -
+    input:
+      bytes: [ 0x3f, 0xf8, 0x22, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "i8mm" ]
+    expected:
+      insns:
+        -
+          asm_text: "sudot v31.2s, v1.8b, v2.4b[3]"
+
+  -
+    input:
+      bytes: [ 0x3f, 0xf8, 0x22, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "i8mm" ]
+    expected:
+      insns:
+        -
+          asm_text: "sudot v31.4s, v1.16b, v2.4b[3]"
+
+  -
+    input:
+      bytes: [ 0x01, 0xa6, 0x9f, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "smmla v1.4s, v16.16b, v31.16b"
+
+  -
+    input:
+      bytes: [ 0x01, 0xa6, 0x9f, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "ummla v1.4s, v16.16b, v31.16b"
+
+  -
+    input:
+      bytes: [ 0x01, 0xae, 0x9f, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "usmmla v1.4s, v16.16b, v31.16b"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x9d, 0x9e, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot v3.2s, v15.8b, v30.8b"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x9d, 0x9e, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot v3.4s, v15.16b, v30.16b"
+
+  -
+    input:
+      bytes: [ 0x3f, 0xf8, 0xa2, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot v31.2s, v1.8b, v2.4b[3]"
+
+  -
+    input:
+      bytes: [ 0x3f, 0xf8, 0xa2, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "usdot v31.4s, v1.16b, v2.4b[3]"
+
+  -
+    input:
+      bytes: [ 0x3f, 0xf8, 0x22, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "sudot v31.2s, v1.8b, v2.4b[3]"
+
+  -
+    input:
+      bytes: [ 0x3f, 0xf8, 0x22, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.6a" ]
+    expected:
+      insns:
+        -
+          asm_text: "sudot v31.4s, v1.16b, v2.4b[3]"
diff --git a/tests/MC/AArch64/armv8.7a-hcx.s.yaml b/tests/MC/AArch64/armv8.7a-hcx.s.yaml
new file mode 100644
index 000000000..d6ba83674
--- /dev/null
+++ b/tests/MC/AArch64/armv8.7a-hcx.s.yaml
@@ -0,0 +1,40 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x42, 0x12, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "hcx" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x2, HCRX_EL2"
+
+  -
+    input:
+      bytes: [ 0x43, 0x12, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "hcx" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr HCRX_EL2, x3"
+
+  -
+    input:
+      bytes: [ 0x42, 0x12, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.7a" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x2, HCRX_EL2"
+
+  -
+    input:
+      bytes: [ 0x43, 0x12, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.7a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr HCRX_EL2, x3"
diff --git a/tests/MC/AArch64/armv8.7a-wfxt.s.yaml b/tests/MC/AArch64/armv8.7a-wfxt.s.yaml
new file mode 100644
index 000000000..93d8bcfd0
--- /dev/null
+++ b/tests/MC/AArch64/armv8.7a-wfxt.s.yaml
@@ -0,0 +1,40 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x11, 0x10, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "wfxt" ]
+    expected:
+      insns:
+        -
+          asm_text: "wfet x17"
+
+  -
+    input:
+      bytes: [ 0x23, 0x10, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "wfxt" ]
+    expected:
+      insns:
+        -
+          asm_text: "wfit x3"
+
+  -
+    input:
+      bytes: [ 0x11, 0x10, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.7a" ]
+    expected:
+      insns:
+        -
+          asm_text: "wfet x17"
+
+  -
+    input:
+      bytes: [ 0x23, 0x10, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.7a" ]
+    expected:
+      insns:
+        -
+          asm_text: "wfit x3"
diff --git a/tests/MC/AArch64/armv8.8a-nmi.s.yaml b/tests/MC/AArch64/armv8.8a-nmi.s.yaml
new file mode 100644
index 000000000..14af955c7
--- /dev/null
+++ b/tests/MC/AArch64/armv8.8a-nmi.s.yaml
@@ -0,0 +1,80 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x02, 0x43, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "nmi" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x2, ALLINT"
+
+  -
+    input:
+      bytes: [ 0x03, 0x43, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "nmi" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ALLINT, x3"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x41, 0x01, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "nmi" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ALLINT, #1"
+
+  -
+    input:
+      bytes: [ 0xa7, 0xc9, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "nmi" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x7, ICC_NMIAR1_EL1"
+
+  -
+    input:
+      bytes: [ 0x02, 0x43, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.8a" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x2, ALLINT"
+
+  -
+    input:
+      bytes: [ 0x03, 0x43, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.8a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ALLINT, x3"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x41, 0x01, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.8a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ALLINT, #1"
+
+  -
+    input:
+      bytes: [ 0xa7, 0xc9, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.8a" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x7, ICC_NMIAR1_EL1"
diff --git a/tests/MC/AArch64/armv8.9a-ats1a.s.yaml b/tests/MC/AArch64/armv8.9a-ats1a.s.yaml
new file mode 100644
index 000000000..a2950c53c
--- /dev/null
+++ b/tests/MC/AArch64/armv8.9a-ats1a.s.yaml
@@ -0,0 +1,30 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x41, 0x79, 0x08, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "at s1e1a, x1"
+
+  -
+    input:
+      bytes: [ 0x41, 0x79, 0x0c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "at s1e2a, x1"
+
+  -
+    input:
+      bytes: [ 0x41, 0x79, 0x0e, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "at s1e3a, x1"
diff --git a/tests/MC/AArch64/armv8.9a-clrbhb.s.yaml b/tests/MC/AArch64/armv8.9a-clrbhb.s.yaml
new file mode 100644
index 000000000..0ec8475fc
--- /dev/null
+++ b/tests/MC/AArch64/armv8.9a-clrbhb.s.yaml
@@ -0,0 +1,420 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xdf, 0x22, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-elf" ]
+    expected:
+      insns:
+        -
+          asm_text: "clrbhb"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x22, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-elf" ]
+    expected:
+      insns:
+        -
+          asm_text: "clrbhb"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x22, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-elf", "v8a" ]
+    expected:
+      insns:
+        -
+          asm_text: "clrbhb"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x22, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-elf", "v8a" ]
+    expected:
+      insns:
+        -
+          asm_text: "clrbhb"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x22, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-elf", "v8.8a" ]
+    expected:
+      insns:
+        -
+          asm_text: "clrbhb"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x22, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-elf", "v8.8a" ]
+    expected:
+      insns:
+        -
+          asm_text: "clrbhb"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x22, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-elf", "v9a" ]
+    expected:
+      insns:
+        -
+          asm_text: "clrbhb"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x22, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-elf", "v9a" ]
+    expected:
+      insns:
+        -
+          asm_text: "clrbhb"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x22, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-elf", "v9.3a" ]
+    expected:
+      insns:
+        -
+          asm_text: "clrbhb"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x22, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-elf", "v9.3a" ]
+    expected:
+      insns:
+        -
+          asm_text: "clrbhb"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x22, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-elf", "-clrbhb" ]
+    expected:
+      insns:
+        -
+          asm_text: "clrbhb"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x22, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-elf", "-clrbhb" ]
+    expected:
+      insns:
+        -
+          asm_text: "clrbhb"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x22, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-elf", "v8a", "-clrbhb" ]
+    expected:
+      insns:
+        -
+          asm_text: "clrbhb"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x22, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-elf", "v8a", "-clrbhb" ]
+    expected:
+      insns:
+        -
+          asm_text: "clrbhb"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x22, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-elf", "v8.8a", "-clrbhb" ]
+    expected:
+      insns:
+        -
+          asm_text: "clrbhb"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x22, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-elf", "v8.8a", "-clrbhb" ]
+    expected:
+      insns:
+        -
+          asm_text: "clrbhb"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x22, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-elf", "v9a", "-clrbhb" ]
+    expected:
+      insns:
+        -
+          asm_text: "clrbhb"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x22, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-elf", "v9a", "-clrbhb" ]
+    expected:
+      insns:
+        -
+          asm_text: "clrbhb"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x22, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-elf", "v9.3a", "-clrbhb" ]
+    expected:
+      insns:
+        -
+          asm_text: "clrbhb"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x22, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-elf", "v9.3a", "-clrbhb" ]
+    expected:
+      insns:
+        -
+          asm_text: "clrbhb"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x22, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-elf", "clrbhb" ]
+    expected:
+      insns:
+        -
+          asm_text: "clrbhb"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x22, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-elf", "clrbhb" ]
+    expected:
+      insns:
+        -
+          asm_text: "clrbhb"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x22, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-elf", "v8a", "+clrbhb" ]
+    expected:
+      insns:
+        -
+          asm_text: "clrbhb"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x22, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-elf", "v8a", "+clrbhb" ]
+    expected:
+      insns:
+        -
+          asm_text: "clrbhb"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x22, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-elf", "v8.8a", "+clrbhb" ]
+    expected:
+      insns:
+        -
+          asm_text: "clrbhb"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x22, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-elf", "v8.8a", "+clrbhb" ]
+    expected:
+      insns:
+        -
+          asm_text: "clrbhb"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x22, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-elf", "v9a", "+clrbhb" ]
+    expected:
+      insns:
+        -
+          asm_text: "clrbhb"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x22, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-elf", "v9a", "+clrbhb" ]
+    expected:
+      insns:
+        -
+          asm_text: "clrbhb"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x22, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-elf", "v9.3a", "+clrbhb" ]
+    expected:
+      insns:
+        -
+          asm_text: "clrbhb"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x22, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-elf", "v9.3a", "+clrbhb" ]
+    expected:
+      insns:
+        -
+          asm_text: "clrbhb"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x22, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-elf", "v8.9a" ]
+    expected:
+      insns:
+        -
+          asm_text: "clrbhb"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x22, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-elf", "v8.9a" ]
+    expected:
+      insns:
+        -
+          asm_text: "clrbhb"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x22, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-elf", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "clrbhb"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x22, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-elf", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "clrbhb"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x22, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-elf", "v8.9a", "+clrbhb" ]
+    expected:
+      insns:
+        -
+          asm_text: "clrbhb"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x22, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-elf", "v8.9a", "+clrbhb" ]
+    expected:
+      insns:
+        -
+          asm_text: "clrbhb"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x22, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-elf", "v9.4a", "+clrbhb" ]
+    expected:
+      insns:
+        -
+          asm_text: "clrbhb"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x22, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-elf", "v9.4a", "+clrbhb" ]
+    expected:
+      insns:
+        -
+          asm_text: "clrbhb"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x22, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-elf", "v8.9a", "-clrbhb" ]
+    expected:
+      insns:
+        -
+          asm_text: "clrbhb"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x22, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-elf", "v8.9a", "-clrbhb" ]
+    expected:
+      insns:
+        -
+          asm_text: "clrbhb"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x22, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-elf", "v9.4a", "-clrbhb" ]
+    expected:
+      insns:
+        -
+          asm_text: "clrbhb"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x22, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-elf", "v9.4a", "-clrbhb" ]
+    expected:
+      insns:
+        -
+          asm_text: "clrbhb"
diff --git a/tests/MC/AArch64/armv8.9a-cssc.s.yaml b/tests/MC/AArch64/armv8.9a-cssc.s.yaml
new file mode 100644
index 000000000..4d8889dab
--- /dev/null
+++ b/tests/MC/AArch64/armv8.9a-cssc.s.yaml
@@ -0,0 +1,600 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x20, 0xc0, 0xda ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "abs x0, x1"
+
+  -
+    input:
+      bytes: [ 0x20, 0x20, 0xc0, 0x5a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "abs w0, w1"
+
+  -
+    input:
+      bytes: [ 0x20, 0x1c, 0xc0, 0xda ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "cnt x0, x1"
+
+  -
+    input:
+      bytes: [ 0x20, 0x1c, 0xc0, 0x5a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "cnt w0, w1"
+
+  -
+    input:
+      bytes: [ 0x20, 0x18, 0xc0, 0xda ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "ctz x0, x1"
+
+  -
+    input:
+      bytes: [ 0x20, 0x18, 0xc0, 0x5a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "ctz w0, w1"
+
+  -
+    input:
+      bytes: [ 0x41, 0x60, 0xc3, 0x9a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax x1, x2, x3"
+
+  -
+    input:
+      bytes: [ 0x41, 0x0c, 0xc0, 0x91 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax x1, x2, #3"
+
+  -
+    input:
+      bytes: [ 0x41, 0x60, 0xc3, 0x1a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax w1, w2, w3"
+
+  -
+    input:
+      bytes: [ 0x41, 0x0c, 0xc0, 0x11 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax w1, w2, #3"
+
+  -
+    input:
+      bytes: [ 0x41, 0x68, 0xc3, 0x9a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin x1, x2, x3"
+
+  -
+    input:
+      bytes: [ 0x41, 0x0c, 0xc8, 0x91 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin x1, x2, #3"
+
+  -
+    input:
+      bytes: [ 0x41, 0x68, 0xc3, 0x1a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin w1, w2, w3"
+
+  -
+    input:
+      bytes: [ 0x41, 0x0c, 0xc8, 0x11 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin w1, w2, #3"
+
+  -
+    input:
+      bytes: [ 0x41, 0x64, 0xc3, 0x9a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax x1, x2, x3"
+
+  -
+    input:
+      bytes: [ 0x41, 0x0c, 0xc4, 0x91 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax x1, x2, #3"
+
+  -
+    input:
+      bytes: [ 0x41, 0x64, 0xc3, 0x1a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax w1, w2, w3"
+
+  -
+    input:
+      bytes: [ 0x41, 0x0c, 0xc4, 0x11 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax w1, w2, #3"
+
+  -
+    input:
+      bytes: [ 0x41, 0x6c, 0xc3, 0x9a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin x1, x2, x3"
+
+  -
+    input:
+      bytes: [ 0x41, 0x0c, 0xcc, 0x91 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin x1, x2, #3"
+
+  -
+    input:
+      bytes: [ 0x41, 0x6c, 0xc3, 0x1a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin w1, w2, w3"
+
+  -
+    input:
+      bytes: [ 0x41, 0x0c, 0xcc, 0x11 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin w1, w2, #3"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xc7, 0x11 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax wzr, wzr, #255"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xc7, 0x91 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax xzr, xzr, #255"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xcf, 0x91 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin xzr, xzr, #255"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xcf, 0x11 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin wzr, wzr, #255"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xc3, 0x91 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax xzr, xzr, #-1"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xc3, 0x11 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax wzr, wzr, #-1"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xcb, 0x91 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin xzr, xzr, #-1"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xcb, 0x11 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin wzr, wzr, #-1"
+
+  -
+    input:
+      bytes: [ 0x20, 0x20, 0xc0, 0xda ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a" ]
+    expected:
+      insns:
+        -
+          asm_text: "abs x0, x1"
+
+  -
+    input:
+      bytes: [ 0x20, 0x20, 0xc0, 0x5a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a" ]
+    expected:
+      insns:
+        -
+          asm_text: "abs w0, w1"
+
+  -
+    input:
+      bytes: [ 0x20, 0x1c, 0xc0, 0xda ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a" ]
+    expected:
+      insns:
+        -
+          asm_text: "cnt x0, x1"
+
+  -
+    input:
+      bytes: [ 0x20, 0x1c, 0xc0, 0x5a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a" ]
+    expected:
+      insns:
+        -
+          asm_text: "cnt w0, w1"
+
+  -
+    input:
+      bytes: [ 0x20, 0x18, 0xc0, 0xda ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a" ]
+    expected:
+      insns:
+        -
+          asm_text: "ctz x0, x1"
+
+  -
+    input:
+      bytes: [ 0x20, 0x18, 0xc0, 0x5a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a" ]
+    expected:
+      insns:
+        -
+          asm_text: "ctz w0, w1"
+
+  -
+    input:
+      bytes: [ 0x41, 0x60, 0xc3, 0x9a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax x1, x2, x3"
+
+  -
+    input:
+      bytes: [ 0x41, 0x0c, 0xc0, 0x91 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax x1, x2, #3"
+
+  -
+    input:
+      bytes: [ 0x41, 0x60, 0xc3, 0x1a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax w1, w2, w3"
+
+  -
+    input:
+      bytes: [ 0x41, 0x0c, 0xc0, 0x11 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax w1, w2, #3"
+
+  -
+    input:
+      bytes: [ 0x41, 0x68, 0xc3, 0x9a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin x1, x2, x3"
+
+  -
+    input:
+      bytes: [ 0x41, 0x0c, 0xc8, 0x91 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin x1, x2, #3"
+
+  -
+    input:
+      bytes: [ 0x41, 0x68, 0xc3, 0x1a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin w1, w2, w3"
+
+  -
+    input:
+      bytes: [ 0x41, 0x0c, 0xc8, 0x11 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin w1, w2, #3"
+
+  -
+    input:
+      bytes: [ 0x41, 0x64, 0xc3, 0x9a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax x1, x2, x3"
+
+  -
+    input:
+      bytes: [ 0x41, 0x0c, 0xc4, 0x91 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax x1, x2, #3"
+
+  -
+    input:
+      bytes: [ 0x41, 0x64, 0xc3, 0x1a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax w1, w2, w3"
+
+  -
+    input:
+      bytes: [ 0x41, 0x0c, 0xc4, 0x11 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax w1, w2, #3"
+
+  -
+    input:
+      bytes: [ 0x41, 0x6c, 0xc3, 0x9a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin x1, x2, x3"
+
+  -
+    input:
+      bytes: [ 0x41, 0x0c, 0xcc, 0x91 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin x1, x2, #3"
+
+  -
+    input:
+      bytes: [ 0x41, 0x6c, 0xc3, 0x1a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin w1, w2, w3"
+
+  -
+    input:
+      bytes: [ 0x41, 0x0c, 0xcc, 0x11 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin w1, w2, #3"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xc7, 0x11 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax wzr, wzr, #255"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xc7, 0x91 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax xzr, xzr, #255"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xcf, 0x91 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin xzr, xzr, #255"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xcf, 0x11 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin wzr, wzr, #255"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xc3, 0x91 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax xzr, xzr, #-1"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xc3, 0x11 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax wzr, wzr, #-1"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xcb, 0x91 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin xzr, xzr, #-1"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xcb, 0x11 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin wzr, wzr, #-1"
diff --git a/tests/MC/AArch64/armv8.9a-debug-pmu.s.yaml b/tests/MC/AArch64/armv8.9a-debug-pmu.s.yaml
new file mode 100644
index 000000000..4152b0c1d
--- /dev/null
+++ b/tests/MC/AArch64/armv8.9a-debug-pmu.s.yaml
@@ -0,0 +1,11050 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x43, 0x04, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, MDSELR_EL1"
+
+  -
+    input:
+      bytes: [ 0x41, 0x04, 0x10, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr MDSELR_EL1, x1"
+
+  -
+    input:
+      bytes: [ 0x83, 0x9e, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMUACR_EL1"
+
+  -
+    input:
+      bytes: [ 0x81, 0x9e, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PMUACR_EL1, x1"
+
+  -
+    input:
+      bytes: [ 0xe3, 0xeb, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMCCNTSVR_EL1"
+
+  -
+    input:
+      bytes: [ 0x03, 0xec, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMICNTSVR_EL1"
+
+  -
+    input:
+      bytes: [ 0x63, 0x9d, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMSSCR_EL1"
+
+  -
+    input:
+      bytes: [ 0x61, 0x9d, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PMSSCR_EL1, x1"
+
+  -
+    input:
+      bytes: [ 0x03, 0xe8, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR0_EL1"
+
+  -
+    input:
+      bytes: [ 0x23, 0xe8, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR1_EL1"
+
+  -
+    input:
+      bytes: [ 0x43, 0xe8, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR2_EL1"
+
+  -
+    input:
+      bytes: [ 0x63, 0xe8, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR3_EL1"
+
+  -
+    input:
+      bytes: [ 0x83, 0xe8, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR4_EL1"
+
+  -
+    input:
+      bytes: [ 0xa3, 0xe8, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR5_EL1"
+
+  -
+    input:
+      bytes: [ 0xc3, 0xe8, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR6_EL1"
+
+  -
+    input:
+      bytes: [ 0xe3, 0xe8, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR7_EL1"
+
+  -
+    input:
+      bytes: [ 0x03, 0xe9, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR8_EL1"
+
+  -
+    input:
+      bytes: [ 0x23, 0xe9, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR9_EL1"
+
+  -
+    input:
+      bytes: [ 0x43, 0xe9, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR10_EL1"
+
+  -
+    input:
+      bytes: [ 0x63, 0xe9, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR11_EL1"
+
+  -
+    input:
+      bytes: [ 0x83, 0xe9, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR12_EL1"
+
+  -
+    input:
+      bytes: [ 0xa3, 0xe9, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR13_EL1"
+
+  -
+    input:
+      bytes: [ 0xc3, 0xe9, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR14_EL1"
+
+  -
+    input:
+      bytes: [ 0xe3, 0xe9, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR15_EL1"
+
+  -
+    input:
+      bytes: [ 0x03, 0xea, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR16_EL1"
+
+  -
+    input:
+      bytes: [ 0x23, 0xea, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR17_EL1"
+
+  -
+    input:
+      bytes: [ 0x43, 0xea, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR18_EL1"
+
+  -
+    input:
+      bytes: [ 0x63, 0xea, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR19_EL1"
+
+  -
+    input:
+      bytes: [ 0x83, 0xea, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR20_EL1"
+
+  -
+    input:
+      bytes: [ 0xa3, 0xea, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR21_EL1"
+
+  -
+    input:
+      bytes: [ 0xc3, 0xea, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR22_EL1"
+
+  -
+    input:
+      bytes: [ 0xe3, 0xea, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR23_EL1"
+
+  -
+    input:
+      bytes: [ 0x03, 0xeb, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR24_EL1"
+
+  -
+    input:
+      bytes: [ 0x23, 0xeb, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR25_EL1"
+
+  -
+    input:
+      bytes: [ 0x43, 0xeb, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR26_EL1"
+
+  -
+    input:
+      bytes: [ 0x63, 0xeb, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR27_EL1"
+
+  -
+    input:
+      bytes: [ 0x83, 0xeb, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR28_EL1"
+
+  -
+    input:
+      bytes: [ 0xa3, 0xeb, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR29_EL1"
+
+  -
+    input:
+      bytes: [ 0xc3, 0xeb, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR30_EL1"
+
+  -
+    input:
+      bytes: [ 0x03, 0x94, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMICNTR_EL0"
+
+  -
+    input:
+      bytes: [ 0x03, 0x94, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PMICNTR_EL0, x3"
+
+  -
+    input:
+      bytes: [ 0x03, 0x96, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMICFILTR_EL0"
+
+  -
+    input:
+      bytes: [ 0x03, 0x96, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PMICFILTR_EL0, x3"
+
+  -
+    input:
+      bytes: [ 0x83, 0x9d, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PMZR_EL0, x3"
+
+  -
+    input:
+      bytes: [ 0xa3, 0x9e, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMECR_EL1"
+
+  -
+    input:
+      bytes: [ 0xa1, 0x9e, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PMECR_EL1, x1"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x9e, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMIAR_EL1"
+
+  -
+    input:
+      bytes: [ 0xe1, 0x9e, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PMIAR_EL1, x1"
+
+  -
+    input:
+      bytes: [ 0x63, 0x9d, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMACCESSR_EL1"
+
+  -
+    input:
+      bytes: [ 0x61, 0x9d, 0x10, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMACCESSR_EL1, x1"
+
+  -
+    input:
+      bytes: [ 0x63, 0x9d, 0x35, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMACCESSR_EL12"
+
+  -
+    input:
+      bytes: [ 0x61, 0x9d, 0x15, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMACCESSR_EL12, x1"
+
+  -
+    input:
+      bytes: [ 0x63, 0x9d, 0x34, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMACCESSR_EL2"
+
+  -
+    input:
+      bytes: [ 0x61, 0x9d, 0x14, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMACCESSR_EL2, x1"
+
+  -
+    input:
+      bytes: [ 0x63, 0x9d, 0x36, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMACCESSR_EL3"
+
+  -
+    input:
+      bytes: [ 0x61, 0x9d, 0x16, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMACCESSR_EL3, x1"
+
+  -
+    input:
+      bytes: [ 0x43, 0x9c, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMCNTENCLR_EL0"
+
+  -
+    input:
+      bytes: [ 0x41, 0x9c, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMCNTENCLR_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x23, 0x9c, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMCNTENSET_EL0"
+
+  -
+    input:
+      bytes: [ 0x21, 0x9c, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMCNTENSET_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x03, 0x9c, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMCR_EL0"
+
+  -
+    input:
+      bytes: [ 0x01, 0x9c, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMCR_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xc3, 0x9d, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMDEVAFF_EL1"
+
+  -
+    input:
+      bytes: [ 0xa3, 0x9d, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMDEVARCH_EL1"
+
+  -
+    input:
+      bytes: [ 0x03, 0xe0, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVCNTR0_EL0"
+
+  -
+    input:
+      bytes: [ 0x01, 0xe0, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVCNTR0_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x23, 0xe0, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVCNTR1_EL0"
+
+  -
+    input:
+      bytes: [ 0x21, 0xe0, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVCNTR1_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x43, 0xe0, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVCNTR2_EL0"
+
+  -
+    input:
+      bytes: [ 0x41, 0xe0, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVCNTR2_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x63, 0xe0, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVCNTR3_EL0"
+
+  -
+    input:
+      bytes: [ 0x61, 0xe0, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVCNTR3_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x83, 0xe0, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVCNTR4_EL0"
+
+  -
+    input:
+      bytes: [ 0x81, 0xe0, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVCNTR4_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xa3, 0xe0, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVCNTR5_EL0"
+
+  -
+    input:
+      bytes: [ 0xa1, 0xe0, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVCNTR5_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xc3, 0xe0, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVCNTR6_EL0"
+
+  -
+    input:
+      bytes: [ 0xc1, 0xe0, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVCNTR6_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xe3, 0xe0, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVCNTR7_EL0"
+
+  -
+    input:
+      bytes: [ 0xe1, 0xe0, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVCNTR7_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x03, 0xe1, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVCNTR8_EL0"
+
+  -
+    input:
+      bytes: [ 0x01, 0xe1, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVCNTR8_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x23, 0xe1, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVCNTR9_EL0"
+
+  -
+    input:
+      bytes: [ 0x21, 0xe1, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVCNTR9_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x43, 0xe1, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVCNTR10_EL0"
+
+  -
+    input:
+      bytes: [ 0x41, 0xe1, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVCNTR10_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x63, 0xe1, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVCNTR11_EL0"
+
+  -
+    input:
+      bytes: [ 0x61, 0xe1, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVCNTR11_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x83, 0xe1, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVCNTR12_EL0"
+
+  -
+    input:
+      bytes: [ 0x81, 0xe1, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVCNTR12_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xa3, 0xe1, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVCNTR13_EL0"
+
+  -
+    input:
+      bytes: [ 0xa1, 0xe1, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVCNTR13_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xc3, 0xe1, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVCNTR14_EL0"
+
+  -
+    input:
+      bytes: [ 0xc1, 0xe1, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVCNTR14_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xe3, 0xe1, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVCNTR15_EL0"
+
+  -
+    input:
+      bytes: [ 0xe1, 0xe1, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVCNTR15_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x03, 0xe6, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILT2R0_EL0"
+
+  -
+    input:
+      bytes: [ 0x01, 0xe6, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILT2R0_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x23, 0xe6, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILT2R1_EL0"
+
+  -
+    input:
+      bytes: [ 0x21, 0xe6, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILT2R1_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x43, 0xe6, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILT2R2_EL0"
+
+  -
+    input:
+      bytes: [ 0x41, 0xe6, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILT2R2_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x63, 0xe6, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILT2R3_EL0"
+
+  -
+    input:
+      bytes: [ 0x61, 0xe6, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILT2R3_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x83, 0xe6, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILT2R4_EL0"
+
+  -
+    input:
+      bytes: [ 0x81, 0xe6, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILT2R4_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xa3, 0xe6, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILT2R5_EL0"
+
+  -
+    input:
+      bytes: [ 0xa1, 0xe6, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILT2R5_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xc3, 0xe6, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILT2R6_EL0"
+
+  -
+    input:
+      bytes: [ 0xc1, 0xe6, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILT2R6_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xe3, 0xe6, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILT2R7_EL0"
+
+  -
+    input:
+      bytes: [ 0xe1, 0xe6, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILT2R7_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x03, 0xe7, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILT2R8_EL0"
+
+  -
+    input:
+      bytes: [ 0x01, 0xe7, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILT2R8_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x23, 0xe7, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILT2R9_EL0"
+
+  -
+    input:
+      bytes: [ 0x21, 0xe7, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILT2R9_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x43, 0xe7, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILT2R10_EL0"
+
+  -
+    input:
+      bytes: [ 0x41, 0xe7, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILT2R10_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x63, 0xe7, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILT2R11_EL0"
+
+  -
+    input:
+      bytes: [ 0x61, 0xe7, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILT2R11_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x83, 0xe7, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILT2R12_EL0"
+
+  -
+    input:
+      bytes: [ 0x81, 0xe7, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILT2R12_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xa3, 0xe7, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILT2R13_EL0"
+
+  -
+    input:
+      bytes: [ 0xa1, 0xe7, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILT2R13_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xc3, 0xe7, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILT2R14_EL0"
+
+  -
+    input:
+      bytes: [ 0xc1, 0xe7, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILT2R14_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xe3, 0xe7, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILT2R15_EL0"
+
+  -
+    input:
+      bytes: [ 0xe1, 0xe7, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILT2R15_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x03, 0xe4, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILTR0_EL0"
+
+  -
+    input:
+      bytes: [ 0x01, 0xe4, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILTR0_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x23, 0xe4, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILTR1_EL0"
+
+  -
+    input:
+      bytes: [ 0x21, 0xe4, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILTR1_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x43, 0xe4, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILTR2_EL0"
+
+  -
+    input:
+      bytes: [ 0x41, 0xe4, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILTR2_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x63, 0xe4, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILTR3_EL0"
+
+  -
+    input:
+      bytes: [ 0x61, 0xe4, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILTR3_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x83, 0xe4, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILTR4_EL0"
+
+  -
+    input:
+      bytes: [ 0x81, 0xe4, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILTR4_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xa3, 0xe4, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILTR5_EL0"
+
+  -
+    input:
+      bytes: [ 0xa1, 0xe4, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILTR5_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xc3, 0xe4, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILTR6_EL0"
+
+  -
+    input:
+      bytes: [ 0xc1, 0xe4, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILTR6_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xe3, 0xe4, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILTR7_EL0"
+
+  -
+    input:
+      bytes: [ 0xe1, 0xe4, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILTR7_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x03, 0xe5, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILTR8_EL0"
+
+  -
+    input:
+      bytes: [ 0x01, 0xe5, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILTR8_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x23, 0xe5, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILTR9_EL0"
+
+  -
+    input:
+      bytes: [ 0x21, 0xe5, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILTR9_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x43, 0xe5, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILTR10_EL0"
+
+  -
+    input:
+      bytes: [ 0x41, 0xe5, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILTR10_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x63, 0xe5, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILTR11_EL0"
+
+  -
+    input:
+      bytes: [ 0x61, 0xe5, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILTR11_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x83, 0xe5, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILTR12_EL0"
+
+  -
+    input:
+      bytes: [ 0x81, 0xe5, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILTR12_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xa3, 0xe5, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILTR13_EL0"
+
+  -
+    input:
+      bytes: [ 0xa1, 0xe5, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILTR13_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xc3, 0xe5, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILTR14_EL0"
+
+  -
+    input:
+      bytes: [ 0xc1, 0xe5, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILTR14_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xe3, 0xe5, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILTR15_EL0"
+
+  -
+    input:
+      bytes: [ 0xe1, 0xe5, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILTR15_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x03, 0xe2, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVTYPER0_EL0"
+
+  -
+    input:
+      bytes: [ 0x01, 0xe2, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVTYPER0_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x23, 0xe2, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVTYPER1_EL0"
+
+  -
+    input:
+      bytes: [ 0x21, 0xe2, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVTYPER1_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x43, 0xe2, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVTYPER2_EL0"
+
+  -
+    input:
+      bytes: [ 0x41, 0xe2, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVTYPER2_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x63, 0xe2, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVTYPER3_EL0"
+
+  -
+    input:
+      bytes: [ 0x61, 0xe2, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVTYPER3_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x83, 0xe2, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVTYPER4_EL0"
+
+  -
+    input:
+      bytes: [ 0x81, 0xe2, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVTYPER4_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xa3, 0xe2, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVTYPER5_EL0"
+
+  -
+    input:
+      bytes: [ 0xa1, 0xe2, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVTYPER5_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xc3, 0xe2, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVTYPER6_EL0"
+
+  -
+    input:
+      bytes: [ 0xc1, 0xe2, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVTYPER6_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xe3, 0xe2, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVTYPER7_EL0"
+
+  -
+    input:
+      bytes: [ 0xe1, 0xe2, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVTYPER7_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x03, 0xe3, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVTYPER8_EL0"
+
+  -
+    input:
+      bytes: [ 0x01, 0xe3, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVTYPER8_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x23, 0xe3, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVTYPER9_EL0"
+
+  -
+    input:
+      bytes: [ 0x21, 0xe3, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVTYPER9_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x43, 0xe3, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVTYPER10_EL0"
+
+  -
+    input:
+      bytes: [ 0x41, 0xe3, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVTYPER10_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x63, 0xe3, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVTYPER11_EL0"
+
+  -
+    input:
+      bytes: [ 0x61, 0xe3, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVTYPER11_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x83, 0xe3, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVTYPER12_EL0"
+
+  -
+    input:
+      bytes: [ 0x81, 0xe3, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVTYPER12_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xa3, 0xe3, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVTYPER13_EL0"
+
+  -
+    input:
+      bytes: [ 0xa1, 0xe3, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVTYPER13_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xc3, 0xe3, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVTYPER14_EL0"
+
+  -
+    input:
+      bytes: [ 0xc1, 0xe3, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVTYPER14_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xe3, 0xe3, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVTYPER15_EL0"
+
+  -
+    input:
+      bytes: [ 0xe1, 0xe3, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVTYPER15_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x83, 0x9d, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMIIDR_EL1"
+
+  -
+    input:
+      bytes: [ 0x43, 0x9e, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMINTENCLR_EL1"
+
+  -
+    input:
+      bytes: [ 0x41, 0x9e, 0x10, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMINTENCLR_EL1, x1"
+
+  -
+    input:
+      bytes: [ 0x23, 0x9e, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMINTENSET_EL1"
+
+  -
+    input:
+      bytes: [ 0x21, 0x9e, 0x10, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMINTENSET_EL1, x1"
+
+  -
+    input:
+      bytes: [ 0x63, 0x9c, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMOVSCLR_EL0"
+
+  -
+    input:
+      bytes: [ 0x61, 0x9c, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMOVSCLR_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x63, 0x9e, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMOVSSET_EL0"
+
+  -
+    input:
+      bytes: [ 0x61, 0x9e, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMOVSSET_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xa3, 0x9c, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMSELR_EL0"
+
+  -
+    input:
+      bytes: [ 0xa1, 0x9c, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMSELR_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x03, 0x9d, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMCGCR0_EL1"
+
+  -
+    input:
+      bytes: [ 0x23, 0x9d, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMCGCR1_EL1"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x9d, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMCFGR_EL1"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x9e, 0x36, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMROOTCR_EL3"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x9e, 0x16, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMROOTCR_EL3, x3"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x9e, 0x37, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMSCR_EL1"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x9e, 0x17, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMSCR_EL1, x3"
+
+  -
+    input:
+      bytes: [ 0x23, 0x02, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, TRCITEEDCR"
+
+  -
+    input:
+      bytes: [ 0x23, 0x02, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCITEEDCR, x3"
+
+  -
+    input:
+      bytes: [ 0x63, 0x12, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, TRCITECR_EL1"
+
+  -
+    input:
+      bytes: [ 0x61, 0x12, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCITECR_EL1, x1"
+
+  -
+    input:
+      bytes: [ 0x63, 0x12, 0x3d, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, TRCITECR_EL12"
+
+  -
+    input:
+      bytes: [ 0x61, 0x12, 0x1d, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCITECR_EL12, x1"
+
+  -
+    input:
+      bytes: [ 0x63, 0x12, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, TRCITECR_EL2"
+
+  -
+    input:
+      bytes: [ 0x61, 0x12, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCITECR_EL2, x1"
+
+  -
+    input:
+      bytes: [ 0xe1, 0x72, 0x0b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "trcit x1"
+
+  -
+    input:
+      bytes: [ 0x83, 0x9a, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMSDSFR_EL1"
+
+  -
+    input:
+      bytes: [ 0x83, 0x9a, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PMSDSFR_EL1, x3"
+
+  -
+    input:
+      bytes: [ 0x43, 0x04, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, MDSELR_EL1"
+
+  -
+    input:
+      bytes: [ 0x41, 0x04, 0x10, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr MDSELR_EL1, x1"
+
+  -
+    input:
+      bytes: [ 0x83, 0x9e, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMUACR_EL1"
+
+  -
+    input:
+      bytes: [ 0x81, 0x9e, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PMUACR_EL1, x1"
+
+  -
+    input:
+      bytes: [ 0xe3, 0xeb, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMCCNTSVR_EL1"
+
+  -
+    input:
+      bytes: [ 0x03, 0xec, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMICNTSVR_EL1"
+
+  -
+    input:
+      bytes: [ 0x63, 0x9d, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMSSCR_EL1"
+
+  -
+    input:
+      bytes: [ 0x61, 0x9d, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PMSSCR_EL1, x1"
+
+  -
+    input:
+      bytes: [ 0x03, 0xe8, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR0_EL1"
+
+  -
+    input:
+      bytes: [ 0x23, 0xe8, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR1_EL1"
+
+  -
+    input:
+      bytes: [ 0x43, 0xe8, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR2_EL1"
+
+  -
+    input:
+      bytes: [ 0x63, 0xe8, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR3_EL1"
+
+  -
+    input:
+      bytes: [ 0x83, 0xe8, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR4_EL1"
+
+  -
+    input:
+      bytes: [ 0xa3, 0xe8, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR5_EL1"
+
+  -
+    input:
+      bytes: [ 0xc3, 0xe8, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR6_EL1"
+
+  -
+    input:
+      bytes: [ 0xe3, 0xe8, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR7_EL1"
+
+  -
+    input:
+      bytes: [ 0x03, 0xe9, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR8_EL1"
+
+  -
+    input:
+      bytes: [ 0x23, 0xe9, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR9_EL1"
+
+  -
+    input:
+      bytes: [ 0x43, 0xe9, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR10_EL1"
+
+  -
+    input:
+      bytes: [ 0x63, 0xe9, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR11_EL1"
+
+  -
+    input:
+      bytes: [ 0x83, 0xe9, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR12_EL1"
+
+  -
+    input:
+      bytes: [ 0xa3, 0xe9, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR13_EL1"
+
+  -
+    input:
+      bytes: [ 0xc3, 0xe9, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR14_EL1"
+
+  -
+    input:
+      bytes: [ 0xe3, 0xe9, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR15_EL1"
+
+  -
+    input:
+      bytes: [ 0x03, 0xea, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR16_EL1"
+
+  -
+    input:
+      bytes: [ 0x23, 0xea, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR17_EL1"
+
+  -
+    input:
+      bytes: [ 0x43, 0xea, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR18_EL1"
+
+  -
+    input:
+      bytes: [ 0x63, 0xea, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR19_EL1"
+
+  -
+    input:
+      bytes: [ 0x83, 0xea, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR20_EL1"
+
+  -
+    input:
+      bytes: [ 0xa3, 0xea, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR21_EL1"
+
+  -
+    input:
+      bytes: [ 0xc3, 0xea, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR22_EL1"
+
+  -
+    input:
+      bytes: [ 0xe3, 0xea, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR23_EL1"
+
+  -
+    input:
+      bytes: [ 0x03, 0xeb, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR24_EL1"
+
+  -
+    input:
+      bytes: [ 0x23, 0xeb, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR25_EL1"
+
+  -
+    input:
+      bytes: [ 0x43, 0xeb, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR26_EL1"
+
+  -
+    input:
+      bytes: [ 0x63, 0xeb, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR27_EL1"
+
+  -
+    input:
+      bytes: [ 0x83, 0xeb, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR28_EL1"
+
+  -
+    input:
+      bytes: [ 0xa3, 0xeb, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR29_EL1"
+
+  -
+    input:
+      bytes: [ 0xc3, 0xeb, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR30_EL1"
+
+  -
+    input:
+      bytes: [ 0x03, 0x94, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMICNTR_EL0"
+
+  -
+    input:
+      bytes: [ 0x03, 0x94, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PMICNTR_EL0, x3"
+
+  -
+    input:
+      bytes: [ 0x03, 0x96, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMICFILTR_EL0"
+
+  -
+    input:
+      bytes: [ 0x03, 0x96, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PMICFILTR_EL0, x3"
+
+  -
+    input:
+      bytes: [ 0x83, 0x9d, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PMZR_EL0, x3"
+
+  -
+    input:
+      bytes: [ 0xa3, 0x9e, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMECR_EL1"
+
+  -
+    input:
+      bytes: [ 0xa1, 0x9e, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PMECR_EL1, x1"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x9e, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMIAR_EL1"
+
+  -
+    input:
+      bytes: [ 0xe1, 0x9e, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PMIAR_EL1, x1"
+
+  -
+    input:
+      bytes: [ 0x63, 0x9d, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMACCESSR_EL1"
+
+  -
+    input:
+      bytes: [ 0x61, 0x9d, 0x10, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMACCESSR_EL1, x1"
+
+  -
+    input:
+      bytes: [ 0x63, 0x9d, 0x35, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMACCESSR_EL12"
+
+  -
+    input:
+      bytes: [ 0x61, 0x9d, 0x15, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMACCESSR_EL12, x1"
+
+  -
+    input:
+      bytes: [ 0x63, 0x9d, 0x34, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMACCESSR_EL2"
+
+  -
+    input:
+      bytes: [ 0x61, 0x9d, 0x14, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMACCESSR_EL2, x1"
+
+  -
+    input:
+      bytes: [ 0x63, 0x9d, 0x36, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMACCESSR_EL3"
+
+  -
+    input:
+      bytes: [ 0x61, 0x9d, 0x16, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMACCESSR_EL3, x1"
+
+  -
+    input:
+      bytes: [ 0x43, 0x9c, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMCNTENCLR_EL0"
+
+  -
+    input:
+      bytes: [ 0x41, 0x9c, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMCNTENCLR_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x23, 0x9c, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMCNTENSET_EL0"
+
+  -
+    input:
+      bytes: [ 0x21, 0x9c, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMCNTENSET_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x03, 0x9c, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMCR_EL0"
+
+  -
+    input:
+      bytes: [ 0x01, 0x9c, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMCR_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xc3, 0x9d, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMDEVAFF_EL1"
+
+  -
+    input:
+      bytes: [ 0xa3, 0x9d, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMDEVARCH_EL1"
+
+  -
+    input:
+      bytes: [ 0x03, 0xe0, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVCNTR0_EL0"
+
+  -
+    input:
+      bytes: [ 0x01, 0xe0, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVCNTR0_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x23, 0xe0, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVCNTR1_EL0"
+
+  -
+    input:
+      bytes: [ 0x21, 0xe0, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVCNTR1_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x43, 0xe0, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVCNTR2_EL0"
+
+  -
+    input:
+      bytes: [ 0x41, 0xe0, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVCNTR2_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x63, 0xe0, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVCNTR3_EL0"
+
+  -
+    input:
+      bytes: [ 0x61, 0xe0, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVCNTR3_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x83, 0xe0, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVCNTR4_EL0"
+
+  -
+    input:
+      bytes: [ 0x81, 0xe0, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVCNTR4_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xa3, 0xe0, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVCNTR5_EL0"
+
+  -
+    input:
+      bytes: [ 0xa1, 0xe0, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVCNTR5_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xc3, 0xe0, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVCNTR6_EL0"
+
+  -
+    input:
+      bytes: [ 0xc1, 0xe0, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVCNTR6_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xe3, 0xe0, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVCNTR7_EL0"
+
+  -
+    input:
+      bytes: [ 0xe1, 0xe0, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVCNTR7_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x03, 0xe1, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVCNTR8_EL0"
+
+  -
+    input:
+      bytes: [ 0x01, 0xe1, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVCNTR8_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x23, 0xe1, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVCNTR9_EL0"
+
+  -
+    input:
+      bytes: [ 0x21, 0xe1, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVCNTR9_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x43, 0xe1, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVCNTR10_EL0"
+
+  -
+    input:
+      bytes: [ 0x41, 0xe1, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVCNTR10_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x63, 0xe1, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVCNTR11_EL0"
+
+  -
+    input:
+      bytes: [ 0x61, 0xe1, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVCNTR11_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x83, 0xe1, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVCNTR12_EL0"
+
+  -
+    input:
+      bytes: [ 0x81, 0xe1, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVCNTR12_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xa3, 0xe1, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVCNTR13_EL0"
+
+  -
+    input:
+      bytes: [ 0xa1, 0xe1, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVCNTR13_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xc3, 0xe1, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVCNTR14_EL0"
+
+  -
+    input:
+      bytes: [ 0xc1, 0xe1, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVCNTR14_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xe3, 0xe1, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVCNTR15_EL0"
+
+  -
+    input:
+      bytes: [ 0xe1, 0xe1, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVCNTR15_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x03, 0xe6, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILT2R0_EL0"
+
+  -
+    input:
+      bytes: [ 0x01, 0xe6, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILT2R0_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x23, 0xe6, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILT2R1_EL0"
+
+  -
+    input:
+      bytes: [ 0x21, 0xe6, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILT2R1_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x43, 0xe6, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILT2R2_EL0"
+
+  -
+    input:
+      bytes: [ 0x41, 0xe6, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILT2R2_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x63, 0xe6, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILT2R3_EL0"
+
+  -
+    input:
+      bytes: [ 0x61, 0xe6, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILT2R3_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x83, 0xe6, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILT2R4_EL0"
+
+  -
+    input:
+      bytes: [ 0x81, 0xe6, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILT2R4_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xa3, 0xe6, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILT2R5_EL0"
+
+  -
+    input:
+      bytes: [ 0xa1, 0xe6, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILT2R5_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xc3, 0xe6, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILT2R6_EL0"
+
+  -
+    input:
+      bytes: [ 0xc1, 0xe6, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILT2R6_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xe3, 0xe6, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILT2R7_EL0"
+
+  -
+    input:
+      bytes: [ 0xe1, 0xe6, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILT2R7_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x03, 0xe7, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILT2R8_EL0"
+
+  -
+    input:
+      bytes: [ 0x01, 0xe7, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILT2R8_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x23, 0xe7, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILT2R9_EL0"
+
+  -
+    input:
+      bytes: [ 0x21, 0xe7, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILT2R9_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x43, 0xe7, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILT2R10_EL0"
+
+  -
+    input:
+      bytes: [ 0x41, 0xe7, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILT2R10_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x63, 0xe7, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILT2R11_EL0"
+
+  -
+    input:
+      bytes: [ 0x61, 0xe7, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILT2R11_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x83, 0xe7, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILT2R12_EL0"
+
+  -
+    input:
+      bytes: [ 0x81, 0xe7, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILT2R12_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xa3, 0xe7, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILT2R13_EL0"
+
+  -
+    input:
+      bytes: [ 0xa1, 0xe7, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILT2R13_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xc3, 0xe7, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILT2R14_EL0"
+
+  -
+    input:
+      bytes: [ 0xc1, 0xe7, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILT2R14_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xe3, 0xe7, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILT2R15_EL0"
+
+  -
+    input:
+      bytes: [ 0xe1, 0xe7, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILT2R15_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x03, 0xe4, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILTR0_EL0"
+
+  -
+    input:
+      bytes: [ 0x01, 0xe4, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILTR0_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x23, 0xe4, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILTR1_EL0"
+
+  -
+    input:
+      bytes: [ 0x21, 0xe4, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILTR1_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x43, 0xe4, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILTR2_EL0"
+
+  -
+    input:
+      bytes: [ 0x41, 0xe4, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILTR2_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x63, 0xe4, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILTR3_EL0"
+
+  -
+    input:
+      bytes: [ 0x61, 0xe4, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILTR3_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x83, 0xe4, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILTR4_EL0"
+
+  -
+    input:
+      bytes: [ 0x81, 0xe4, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILTR4_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xa3, 0xe4, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILTR5_EL0"
+
+  -
+    input:
+      bytes: [ 0xa1, 0xe4, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILTR5_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xc3, 0xe4, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILTR6_EL0"
+
+  -
+    input:
+      bytes: [ 0xc1, 0xe4, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILTR6_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xe3, 0xe4, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILTR7_EL0"
+
+  -
+    input:
+      bytes: [ 0xe1, 0xe4, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILTR7_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x03, 0xe5, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILTR8_EL0"
+
+  -
+    input:
+      bytes: [ 0x01, 0xe5, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILTR8_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x23, 0xe5, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILTR9_EL0"
+
+  -
+    input:
+      bytes: [ 0x21, 0xe5, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILTR9_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x43, 0xe5, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILTR10_EL0"
+
+  -
+    input:
+      bytes: [ 0x41, 0xe5, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILTR10_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x63, 0xe5, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILTR11_EL0"
+
+  -
+    input:
+      bytes: [ 0x61, 0xe5, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILTR11_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x83, 0xe5, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILTR12_EL0"
+
+  -
+    input:
+      bytes: [ 0x81, 0xe5, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILTR12_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xa3, 0xe5, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILTR13_EL0"
+
+  -
+    input:
+      bytes: [ 0xa1, 0xe5, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILTR13_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xc3, 0xe5, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILTR14_EL0"
+
+  -
+    input:
+      bytes: [ 0xc1, 0xe5, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILTR14_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xe3, 0xe5, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILTR15_EL0"
+
+  -
+    input:
+      bytes: [ 0xe1, 0xe5, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILTR15_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x03, 0xe2, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVTYPER0_EL0"
+
+  -
+    input:
+      bytes: [ 0x01, 0xe2, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVTYPER0_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x23, 0xe2, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVTYPER1_EL0"
+
+  -
+    input:
+      bytes: [ 0x21, 0xe2, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVTYPER1_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x43, 0xe2, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVTYPER2_EL0"
+
+  -
+    input:
+      bytes: [ 0x41, 0xe2, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVTYPER2_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x63, 0xe2, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVTYPER3_EL0"
+
+  -
+    input:
+      bytes: [ 0x61, 0xe2, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVTYPER3_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x83, 0xe2, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVTYPER4_EL0"
+
+  -
+    input:
+      bytes: [ 0x81, 0xe2, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVTYPER4_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xa3, 0xe2, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVTYPER5_EL0"
+
+  -
+    input:
+      bytes: [ 0xa1, 0xe2, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVTYPER5_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xc3, 0xe2, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVTYPER6_EL0"
+
+  -
+    input:
+      bytes: [ 0xc1, 0xe2, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVTYPER6_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xe3, 0xe2, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVTYPER7_EL0"
+
+  -
+    input:
+      bytes: [ 0xe1, 0xe2, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVTYPER7_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x03, 0xe3, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVTYPER8_EL0"
+
+  -
+    input:
+      bytes: [ 0x01, 0xe3, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVTYPER8_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x23, 0xe3, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVTYPER9_EL0"
+
+  -
+    input:
+      bytes: [ 0x21, 0xe3, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVTYPER9_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x43, 0xe3, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVTYPER10_EL0"
+
+  -
+    input:
+      bytes: [ 0x41, 0xe3, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVTYPER10_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x63, 0xe3, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVTYPER11_EL0"
+
+  -
+    input:
+      bytes: [ 0x61, 0xe3, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVTYPER11_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x83, 0xe3, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVTYPER12_EL0"
+
+  -
+    input:
+      bytes: [ 0x81, 0xe3, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVTYPER12_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xa3, 0xe3, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVTYPER13_EL0"
+
+  -
+    input:
+      bytes: [ 0xa1, 0xe3, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVTYPER13_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xc3, 0xe3, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVTYPER14_EL0"
+
+  -
+    input:
+      bytes: [ 0xc1, 0xe3, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVTYPER14_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xe3, 0xe3, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVTYPER15_EL0"
+
+  -
+    input:
+      bytes: [ 0xe1, 0xe3, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVTYPER15_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x83, 0x9d, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMIIDR_EL1"
+
+  -
+    input:
+      bytes: [ 0x43, 0x9e, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMINTENCLR_EL1"
+
+  -
+    input:
+      bytes: [ 0x41, 0x9e, 0x10, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMINTENCLR_EL1, x1"
+
+  -
+    input:
+      bytes: [ 0x23, 0x9e, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMINTENSET_EL1"
+
+  -
+    input:
+      bytes: [ 0x21, 0x9e, 0x10, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMINTENSET_EL1, x1"
+
+  -
+    input:
+      bytes: [ 0x63, 0x9c, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMOVSCLR_EL0"
+
+  -
+    input:
+      bytes: [ 0x61, 0x9c, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMOVSCLR_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x63, 0x9e, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMOVSSET_EL0"
+
+  -
+    input:
+      bytes: [ 0x61, 0x9e, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMOVSSET_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xa3, 0x9c, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMSELR_EL0"
+
+  -
+    input:
+      bytes: [ 0xa1, 0x9c, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMSELR_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x03, 0x9d, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMCGCR0_EL1"
+
+  -
+    input:
+      bytes: [ 0x23, 0x9d, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMCGCR1_EL1"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x9d, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMCFGR_EL1"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x9e, 0x36, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMROOTCR_EL3"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x9e, 0x16, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMROOTCR_EL3, x3"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x9e, 0x37, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMSCR_EL1"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x9e, 0x17, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMSCR_EL1, x3"
+
+  -
+    input:
+      bytes: [ 0x23, 0x02, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, TRCITEEDCR"
+
+  -
+    input:
+      bytes: [ 0x23, 0x02, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCITEEDCR, x3"
+
+  -
+    input:
+      bytes: [ 0x63, 0x12, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, TRCITECR_EL1"
+
+  -
+    input:
+      bytes: [ 0x61, 0x12, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCITECR_EL1, x1"
+
+  -
+    input:
+      bytes: [ 0x63, 0x12, 0x3d, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, TRCITECR_EL12"
+
+  -
+    input:
+      bytes: [ 0x61, 0x12, 0x1d, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCITECR_EL12, x1"
+
+  -
+    input:
+      bytes: [ 0x63, 0x12, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, TRCITECR_EL2"
+
+  -
+    input:
+      bytes: [ 0x61, 0x12, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCITECR_EL2, x1"
+
+  -
+    input:
+      bytes: [ 0xe1, 0x72, 0x0b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "trcit x1"
+
+  -
+    input:
+      bytes: [ 0x83, 0x9a, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMSDSFR_EL1"
+
+  -
+    input:
+      bytes: [ 0x83, 0x9a, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.8a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PMSDSFR_EL1, x3"
+
+  -
+    input:
+      bytes: [ 0x43, 0x04, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, MDSELR_EL1"
+
+  -
+    input:
+      bytes: [ 0x41, 0x04, 0x10, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr MDSELR_EL1, x1"
+
+  -
+    input:
+      bytes: [ 0x83, 0x9e, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMUACR_EL1"
+
+  -
+    input:
+      bytes: [ 0x81, 0x9e, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PMUACR_EL1, x1"
+
+  -
+    input:
+      bytes: [ 0xe3, 0xeb, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMCCNTSVR_EL1"
+
+  -
+    input:
+      bytes: [ 0x03, 0xec, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMICNTSVR_EL1"
+
+  -
+    input:
+      bytes: [ 0x63, 0x9d, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMSSCR_EL1"
+
+  -
+    input:
+      bytes: [ 0x61, 0x9d, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PMSSCR_EL1, x1"
+
+  -
+    input:
+      bytes: [ 0x03, 0xe8, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR0_EL1"
+
+  -
+    input:
+      bytes: [ 0x23, 0xe8, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR1_EL1"
+
+  -
+    input:
+      bytes: [ 0x43, 0xe8, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR2_EL1"
+
+  -
+    input:
+      bytes: [ 0x63, 0xe8, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR3_EL1"
+
+  -
+    input:
+      bytes: [ 0x83, 0xe8, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR4_EL1"
+
+  -
+    input:
+      bytes: [ 0xa3, 0xe8, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR5_EL1"
+
+  -
+    input:
+      bytes: [ 0xc3, 0xe8, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR6_EL1"
+
+  -
+    input:
+      bytes: [ 0xe3, 0xe8, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR7_EL1"
+
+  -
+    input:
+      bytes: [ 0x03, 0xe9, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR8_EL1"
+
+  -
+    input:
+      bytes: [ 0x23, 0xe9, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR9_EL1"
+
+  -
+    input:
+      bytes: [ 0x43, 0xe9, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR10_EL1"
+
+  -
+    input:
+      bytes: [ 0x63, 0xe9, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR11_EL1"
+
+  -
+    input:
+      bytes: [ 0x83, 0xe9, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR12_EL1"
+
+  -
+    input:
+      bytes: [ 0xa3, 0xe9, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR13_EL1"
+
+  -
+    input:
+      bytes: [ 0xc3, 0xe9, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR14_EL1"
+
+  -
+    input:
+      bytes: [ 0xe3, 0xe9, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR15_EL1"
+
+  -
+    input:
+      bytes: [ 0x03, 0xea, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR16_EL1"
+
+  -
+    input:
+      bytes: [ 0x23, 0xea, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR17_EL1"
+
+  -
+    input:
+      bytes: [ 0x43, 0xea, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR18_EL1"
+
+  -
+    input:
+      bytes: [ 0x63, 0xea, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR19_EL1"
+
+  -
+    input:
+      bytes: [ 0x83, 0xea, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR20_EL1"
+
+  -
+    input:
+      bytes: [ 0xa3, 0xea, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR21_EL1"
+
+  -
+    input:
+      bytes: [ 0xc3, 0xea, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR22_EL1"
+
+  -
+    input:
+      bytes: [ 0xe3, 0xea, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR23_EL1"
+
+  -
+    input:
+      bytes: [ 0x03, 0xeb, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR24_EL1"
+
+  -
+    input:
+      bytes: [ 0x23, 0xeb, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR25_EL1"
+
+  -
+    input:
+      bytes: [ 0x43, 0xeb, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR26_EL1"
+
+  -
+    input:
+      bytes: [ 0x63, 0xeb, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR27_EL1"
+
+  -
+    input:
+      bytes: [ 0x83, 0xeb, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR28_EL1"
+
+  -
+    input:
+      bytes: [ 0xa3, 0xeb, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR29_EL1"
+
+  -
+    input:
+      bytes: [ 0xc3, 0xeb, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR30_EL1"
+
+  -
+    input:
+      bytes: [ 0x03, 0x94, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMICNTR_EL0"
+
+  -
+    input:
+      bytes: [ 0x03, 0x94, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PMICNTR_EL0, x3"
+
+  -
+    input:
+      bytes: [ 0x03, 0x96, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMICFILTR_EL0"
+
+  -
+    input:
+      bytes: [ 0x03, 0x96, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PMICFILTR_EL0, x3"
+
+  -
+    input:
+      bytes: [ 0x83, 0x9d, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PMZR_EL0, x3"
+
+  -
+    input:
+      bytes: [ 0xa3, 0x9e, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMECR_EL1"
+
+  -
+    input:
+      bytes: [ 0xa1, 0x9e, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PMECR_EL1, x1"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x9e, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMIAR_EL1"
+
+  -
+    input:
+      bytes: [ 0xe1, 0x9e, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PMIAR_EL1, x1"
+
+  -
+    input:
+      bytes: [ 0x63, 0x9d, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMACCESSR_EL1"
+
+  -
+    input:
+      bytes: [ 0x61, 0x9d, 0x10, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMACCESSR_EL1, x1"
+
+  -
+    input:
+      bytes: [ 0x63, 0x9d, 0x35, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMACCESSR_EL12"
+
+  -
+    input:
+      bytes: [ 0x61, 0x9d, 0x15, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMACCESSR_EL12, x1"
+
+  -
+    input:
+      bytes: [ 0x63, 0x9d, 0x34, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMACCESSR_EL2"
+
+  -
+    input:
+      bytes: [ 0x61, 0x9d, 0x14, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMACCESSR_EL2, x1"
+
+  -
+    input:
+      bytes: [ 0x63, 0x9d, 0x36, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMACCESSR_EL3"
+
+  -
+    input:
+      bytes: [ 0x61, 0x9d, 0x16, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMACCESSR_EL3, x1"
+
+  -
+    input:
+      bytes: [ 0x43, 0x9c, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMCNTENCLR_EL0"
+
+  -
+    input:
+      bytes: [ 0x41, 0x9c, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMCNTENCLR_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x23, 0x9c, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMCNTENSET_EL0"
+
+  -
+    input:
+      bytes: [ 0x21, 0x9c, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMCNTENSET_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x03, 0x9c, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMCR_EL0"
+
+  -
+    input:
+      bytes: [ 0x01, 0x9c, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMCR_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xc3, 0x9d, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMDEVAFF_EL1"
+
+  -
+    input:
+      bytes: [ 0xa3, 0x9d, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMDEVARCH_EL1"
+
+  -
+    input:
+      bytes: [ 0x03, 0xe0, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVCNTR0_EL0"
+
+  -
+    input:
+      bytes: [ 0x01, 0xe0, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVCNTR0_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x23, 0xe0, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVCNTR1_EL0"
+
+  -
+    input:
+      bytes: [ 0x21, 0xe0, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVCNTR1_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x43, 0xe0, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVCNTR2_EL0"
+
+  -
+    input:
+      bytes: [ 0x41, 0xe0, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVCNTR2_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x63, 0xe0, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVCNTR3_EL0"
+
+  -
+    input:
+      bytes: [ 0x61, 0xe0, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVCNTR3_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x83, 0xe0, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVCNTR4_EL0"
+
+  -
+    input:
+      bytes: [ 0x81, 0xe0, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVCNTR4_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xa3, 0xe0, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVCNTR5_EL0"
+
+  -
+    input:
+      bytes: [ 0xa1, 0xe0, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVCNTR5_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xc3, 0xe0, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVCNTR6_EL0"
+
+  -
+    input:
+      bytes: [ 0xc1, 0xe0, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVCNTR6_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xe3, 0xe0, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVCNTR7_EL0"
+
+  -
+    input:
+      bytes: [ 0xe1, 0xe0, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVCNTR7_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x03, 0xe1, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVCNTR8_EL0"
+
+  -
+    input:
+      bytes: [ 0x01, 0xe1, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVCNTR8_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x23, 0xe1, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVCNTR9_EL0"
+
+  -
+    input:
+      bytes: [ 0x21, 0xe1, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVCNTR9_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x43, 0xe1, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVCNTR10_EL0"
+
+  -
+    input:
+      bytes: [ 0x41, 0xe1, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVCNTR10_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x63, 0xe1, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVCNTR11_EL0"
+
+  -
+    input:
+      bytes: [ 0x61, 0xe1, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVCNTR11_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x83, 0xe1, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVCNTR12_EL0"
+
+  -
+    input:
+      bytes: [ 0x81, 0xe1, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVCNTR12_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xa3, 0xe1, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVCNTR13_EL0"
+
+  -
+    input:
+      bytes: [ 0xa1, 0xe1, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVCNTR13_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xc3, 0xe1, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVCNTR14_EL0"
+
+  -
+    input:
+      bytes: [ 0xc1, 0xe1, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVCNTR14_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xe3, 0xe1, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVCNTR15_EL0"
+
+  -
+    input:
+      bytes: [ 0xe1, 0xe1, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVCNTR15_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x03, 0xe6, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILT2R0_EL0"
+
+  -
+    input:
+      bytes: [ 0x01, 0xe6, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILT2R0_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x23, 0xe6, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILT2R1_EL0"
+
+  -
+    input:
+      bytes: [ 0x21, 0xe6, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILT2R1_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x43, 0xe6, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILT2R2_EL0"
+
+  -
+    input:
+      bytes: [ 0x41, 0xe6, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILT2R2_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x63, 0xe6, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILT2R3_EL0"
+
+  -
+    input:
+      bytes: [ 0x61, 0xe6, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILT2R3_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x83, 0xe6, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILT2R4_EL0"
+
+  -
+    input:
+      bytes: [ 0x81, 0xe6, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILT2R4_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xa3, 0xe6, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILT2R5_EL0"
+
+  -
+    input:
+      bytes: [ 0xa1, 0xe6, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILT2R5_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xc3, 0xe6, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILT2R6_EL0"
+
+  -
+    input:
+      bytes: [ 0xc1, 0xe6, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILT2R6_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xe3, 0xe6, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILT2R7_EL0"
+
+  -
+    input:
+      bytes: [ 0xe1, 0xe6, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILT2R7_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x03, 0xe7, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILT2R8_EL0"
+
+  -
+    input:
+      bytes: [ 0x01, 0xe7, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILT2R8_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x23, 0xe7, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILT2R9_EL0"
+
+  -
+    input:
+      bytes: [ 0x21, 0xe7, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILT2R9_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x43, 0xe7, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILT2R10_EL0"
+
+  -
+    input:
+      bytes: [ 0x41, 0xe7, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILT2R10_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x63, 0xe7, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILT2R11_EL0"
+
+  -
+    input:
+      bytes: [ 0x61, 0xe7, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILT2R11_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x83, 0xe7, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILT2R12_EL0"
+
+  -
+    input:
+      bytes: [ 0x81, 0xe7, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILT2R12_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xa3, 0xe7, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILT2R13_EL0"
+
+  -
+    input:
+      bytes: [ 0xa1, 0xe7, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILT2R13_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xc3, 0xe7, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILT2R14_EL0"
+
+  -
+    input:
+      bytes: [ 0xc1, 0xe7, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILT2R14_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xe3, 0xe7, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILT2R15_EL0"
+
+  -
+    input:
+      bytes: [ 0xe1, 0xe7, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILT2R15_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x03, 0xe4, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILTR0_EL0"
+
+  -
+    input:
+      bytes: [ 0x01, 0xe4, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILTR0_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x23, 0xe4, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILTR1_EL0"
+
+  -
+    input:
+      bytes: [ 0x21, 0xe4, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILTR1_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x43, 0xe4, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILTR2_EL0"
+
+  -
+    input:
+      bytes: [ 0x41, 0xe4, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILTR2_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x63, 0xe4, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILTR3_EL0"
+
+  -
+    input:
+      bytes: [ 0x61, 0xe4, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILTR3_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x83, 0xe4, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILTR4_EL0"
+
+  -
+    input:
+      bytes: [ 0x81, 0xe4, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILTR4_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xa3, 0xe4, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILTR5_EL0"
+
+  -
+    input:
+      bytes: [ 0xa1, 0xe4, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILTR5_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xc3, 0xe4, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILTR6_EL0"
+
+  -
+    input:
+      bytes: [ 0xc1, 0xe4, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILTR6_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xe3, 0xe4, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILTR7_EL0"
+
+  -
+    input:
+      bytes: [ 0xe1, 0xe4, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILTR7_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x03, 0xe5, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILTR8_EL0"
+
+  -
+    input:
+      bytes: [ 0x01, 0xe5, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILTR8_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x23, 0xe5, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILTR9_EL0"
+
+  -
+    input:
+      bytes: [ 0x21, 0xe5, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILTR9_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x43, 0xe5, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILTR10_EL0"
+
+  -
+    input:
+      bytes: [ 0x41, 0xe5, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILTR10_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x63, 0xe5, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILTR11_EL0"
+
+  -
+    input:
+      bytes: [ 0x61, 0xe5, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILTR11_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x83, 0xe5, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILTR12_EL0"
+
+  -
+    input:
+      bytes: [ 0x81, 0xe5, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILTR12_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xa3, 0xe5, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILTR13_EL0"
+
+  -
+    input:
+      bytes: [ 0xa1, 0xe5, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILTR13_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xc3, 0xe5, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILTR14_EL0"
+
+  -
+    input:
+      bytes: [ 0xc1, 0xe5, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILTR14_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xe3, 0xe5, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILTR15_EL0"
+
+  -
+    input:
+      bytes: [ 0xe1, 0xe5, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILTR15_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x03, 0xe2, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVTYPER0_EL0"
+
+  -
+    input:
+      bytes: [ 0x01, 0xe2, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVTYPER0_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x23, 0xe2, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVTYPER1_EL0"
+
+  -
+    input:
+      bytes: [ 0x21, 0xe2, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVTYPER1_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x43, 0xe2, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVTYPER2_EL0"
+
+  -
+    input:
+      bytes: [ 0x41, 0xe2, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVTYPER2_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x63, 0xe2, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVTYPER3_EL0"
+
+  -
+    input:
+      bytes: [ 0x61, 0xe2, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVTYPER3_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x83, 0xe2, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVTYPER4_EL0"
+
+  -
+    input:
+      bytes: [ 0x81, 0xe2, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVTYPER4_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xa3, 0xe2, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVTYPER5_EL0"
+
+  -
+    input:
+      bytes: [ 0xa1, 0xe2, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVTYPER5_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xc3, 0xe2, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVTYPER6_EL0"
+
+  -
+    input:
+      bytes: [ 0xc1, 0xe2, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVTYPER6_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xe3, 0xe2, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVTYPER7_EL0"
+
+  -
+    input:
+      bytes: [ 0xe1, 0xe2, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVTYPER7_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x03, 0xe3, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVTYPER8_EL0"
+
+  -
+    input:
+      bytes: [ 0x01, 0xe3, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVTYPER8_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x23, 0xe3, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVTYPER9_EL0"
+
+  -
+    input:
+      bytes: [ 0x21, 0xe3, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVTYPER9_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x43, 0xe3, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVTYPER10_EL0"
+
+  -
+    input:
+      bytes: [ 0x41, 0xe3, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVTYPER10_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x63, 0xe3, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVTYPER11_EL0"
+
+  -
+    input:
+      bytes: [ 0x61, 0xe3, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVTYPER11_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x83, 0xe3, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVTYPER12_EL0"
+
+  -
+    input:
+      bytes: [ 0x81, 0xe3, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVTYPER12_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xa3, 0xe3, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVTYPER13_EL0"
+
+  -
+    input:
+      bytes: [ 0xa1, 0xe3, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVTYPER13_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xc3, 0xe3, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVTYPER14_EL0"
+
+  -
+    input:
+      bytes: [ 0xc1, 0xe3, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVTYPER14_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xe3, 0xe3, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVTYPER15_EL0"
+
+  -
+    input:
+      bytes: [ 0xe1, 0xe3, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVTYPER15_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x83, 0x9d, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMIIDR_EL1"
+
+  -
+    input:
+      bytes: [ 0x43, 0x9e, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMINTENCLR_EL1"
+
+  -
+    input:
+      bytes: [ 0x41, 0x9e, 0x10, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMINTENCLR_EL1, x1"
+
+  -
+    input:
+      bytes: [ 0x23, 0x9e, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMINTENSET_EL1"
+
+  -
+    input:
+      bytes: [ 0x21, 0x9e, 0x10, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMINTENSET_EL1, x1"
+
+  -
+    input:
+      bytes: [ 0x63, 0x9c, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMOVSCLR_EL0"
+
+  -
+    input:
+      bytes: [ 0x61, 0x9c, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMOVSCLR_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x63, 0x9e, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMOVSSET_EL0"
+
+  -
+    input:
+      bytes: [ 0x61, 0x9e, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMOVSSET_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xa3, 0x9c, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMSELR_EL0"
+
+  -
+    input:
+      bytes: [ 0xa1, 0x9c, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMSELR_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x03, 0x9d, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMCGCR0_EL1"
+
+  -
+    input:
+      bytes: [ 0x23, 0x9d, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMCGCR1_EL1"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x9d, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMCFGR_EL1"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x9e, 0x36, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMROOTCR_EL3"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x9e, 0x16, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMROOTCR_EL3, x3"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x9e, 0x37, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMSCR_EL1"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x9e, 0x17, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMSCR_EL1, x3"
+
+  -
+    input:
+      bytes: [ 0x23, 0x02, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, TRCITEEDCR"
+
+  -
+    input:
+      bytes: [ 0x23, 0x02, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCITEEDCR, x3"
+
+  -
+    input:
+      bytes: [ 0x63, 0x12, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, TRCITECR_EL1"
+
+  -
+    input:
+      bytes: [ 0x61, 0x12, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCITECR_EL1, x1"
+
+  -
+    input:
+      bytes: [ 0x63, 0x12, 0x3d, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, TRCITECR_EL12"
+
+  -
+    input:
+      bytes: [ 0x61, 0x12, 0x1d, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCITECR_EL12, x1"
+
+  -
+    input:
+      bytes: [ 0x63, 0x12, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, TRCITECR_EL2"
+
+  -
+    input:
+      bytes: [ 0x61, 0x12, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCITECR_EL2, x1"
+
+  -
+    input:
+      bytes: [ 0xe1, 0x72, 0x0b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "trcit x1"
+
+  -
+    input:
+      bytes: [ 0x83, 0x9a, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMSDSFR_EL1"
+
+  -
+    input:
+      bytes: [ 0x83, 0x9a, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PMSDSFR_EL1, x3"
+
+  -
+    input:
+      bytes: [ 0x43, 0x04, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, MDSELR_EL1"
+
+  -
+    input:
+      bytes: [ 0x41, 0x04, 0x10, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr MDSELR_EL1, x1"
+
+  -
+    input:
+      bytes: [ 0x83, 0x9e, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMUACR_EL1"
+
+  -
+    input:
+      bytes: [ 0x81, 0x9e, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PMUACR_EL1, x1"
+
+  -
+    input:
+      bytes: [ 0xe3, 0xeb, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMCCNTSVR_EL1"
+
+  -
+    input:
+      bytes: [ 0x03, 0xec, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMICNTSVR_EL1"
+
+  -
+    input:
+      bytes: [ 0x63, 0x9d, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMSSCR_EL1"
+
+  -
+    input:
+      bytes: [ 0x61, 0x9d, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PMSSCR_EL1, x1"
+
+  -
+    input:
+      bytes: [ 0x03, 0xe8, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR0_EL1"
+
+  -
+    input:
+      bytes: [ 0x23, 0xe8, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR1_EL1"
+
+  -
+    input:
+      bytes: [ 0x43, 0xe8, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR2_EL1"
+
+  -
+    input:
+      bytes: [ 0x63, 0xe8, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR3_EL1"
+
+  -
+    input:
+      bytes: [ 0x83, 0xe8, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR4_EL1"
+
+  -
+    input:
+      bytes: [ 0xa3, 0xe8, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR5_EL1"
+
+  -
+    input:
+      bytes: [ 0xc3, 0xe8, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR6_EL1"
+
+  -
+    input:
+      bytes: [ 0xe3, 0xe8, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR7_EL1"
+
+  -
+    input:
+      bytes: [ 0x03, 0xe9, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR8_EL1"
+
+  -
+    input:
+      bytes: [ 0x23, 0xe9, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR9_EL1"
+
+  -
+    input:
+      bytes: [ 0x43, 0xe9, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR10_EL1"
+
+  -
+    input:
+      bytes: [ 0x63, 0xe9, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR11_EL1"
+
+  -
+    input:
+      bytes: [ 0x83, 0xe9, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR12_EL1"
+
+  -
+    input:
+      bytes: [ 0xa3, 0xe9, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR13_EL1"
+
+  -
+    input:
+      bytes: [ 0xc3, 0xe9, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR14_EL1"
+
+  -
+    input:
+      bytes: [ 0xe3, 0xe9, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR15_EL1"
+
+  -
+    input:
+      bytes: [ 0x03, 0xea, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR16_EL1"
+
+  -
+    input:
+      bytes: [ 0x23, 0xea, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR17_EL1"
+
+  -
+    input:
+      bytes: [ 0x43, 0xea, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR18_EL1"
+
+  -
+    input:
+      bytes: [ 0x63, 0xea, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR19_EL1"
+
+  -
+    input:
+      bytes: [ 0x83, 0xea, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR20_EL1"
+
+  -
+    input:
+      bytes: [ 0xa3, 0xea, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR21_EL1"
+
+  -
+    input:
+      bytes: [ 0xc3, 0xea, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR22_EL1"
+
+  -
+    input:
+      bytes: [ 0xe3, 0xea, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR23_EL1"
+
+  -
+    input:
+      bytes: [ 0x03, 0xeb, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR24_EL1"
+
+  -
+    input:
+      bytes: [ 0x23, 0xeb, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR25_EL1"
+
+  -
+    input:
+      bytes: [ 0x43, 0xeb, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR26_EL1"
+
+  -
+    input:
+      bytes: [ 0x63, 0xeb, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR27_EL1"
+
+  -
+    input:
+      bytes: [ 0x83, 0xeb, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR28_EL1"
+
+  -
+    input:
+      bytes: [ 0xa3, 0xeb, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR29_EL1"
+
+  -
+    input:
+      bytes: [ 0xc3, 0xeb, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR30_EL1"
+
+  -
+    input:
+      bytes: [ 0x03, 0x94, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMICNTR_EL0"
+
+  -
+    input:
+      bytes: [ 0x03, 0x94, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PMICNTR_EL0, x3"
+
+  -
+    input:
+      bytes: [ 0x03, 0x96, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMICFILTR_EL0"
+
+  -
+    input:
+      bytes: [ 0x03, 0x96, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PMICFILTR_EL0, x3"
+
+  -
+    input:
+      bytes: [ 0x83, 0x9d, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PMZR_EL0, x3"
+
+  -
+    input:
+      bytes: [ 0xa3, 0x9e, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMECR_EL1"
+
+  -
+    input:
+      bytes: [ 0xa1, 0x9e, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PMECR_EL1, x1"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x9e, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMIAR_EL1"
+
+  -
+    input:
+      bytes: [ 0xe1, 0x9e, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PMIAR_EL1, x1"
+
+  -
+    input:
+      bytes: [ 0x63, 0x9d, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMACCESSR_EL1"
+
+  -
+    input:
+      bytes: [ 0x61, 0x9d, 0x10, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMACCESSR_EL1, x1"
+
+  -
+    input:
+      bytes: [ 0x63, 0x9d, 0x35, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMACCESSR_EL12"
+
+  -
+    input:
+      bytes: [ 0x61, 0x9d, 0x15, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMACCESSR_EL12, x1"
+
+  -
+    input:
+      bytes: [ 0x63, 0x9d, 0x34, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMACCESSR_EL2"
+
+  -
+    input:
+      bytes: [ 0x61, 0x9d, 0x14, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMACCESSR_EL2, x1"
+
+  -
+    input:
+      bytes: [ 0x63, 0x9d, 0x36, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMACCESSR_EL3"
+
+  -
+    input:
+      bytes: [ 0x61, 0x9d, 0x16, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMACCESSR_EL3, x1"
+
+  -
+    input:
+      bytes: [ 0x43, 0x9c, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMCNTENCLR_EL0"
+
+  -
+    input:
+      bytes: [ 0x41, 0x9c, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMCNTENCLR_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x23, 0x9c, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMCNTENSET_EL0"
+
+  -
+    input:
+      bytes: [ 0x21, 0x9c, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMCNTENSET_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x03, 0x9c, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMCR_EL0"
+
+  -
+    input:
+      bytes: [ 0x01, 0x9c, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMCR_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xc3, 0x9d, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMDEVAFF_EL1"
+
+  -
+    input:
+      bytes: [ 0xa3, 0x9d, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMDEVARCH_EL1"
+
+  -
+    input:
+      bytes: [ 0x03, 0xe0, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVCNTR0_EL0"
+
+  -
+    input:
+      bytes: [ 0x01, 0xe0, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVCNTR0_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x23, 0xe0, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVCNTR1_EL0"
+
+  -
+    input:
+      bytes: [ 0x21, 0xe0, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVCNTR1_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x43, 0xe0, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVCNTR2_EL0"
+
+  -
+    input:
+      bytes: [ 0x41, 0xe0, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVCNTR2_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x63, 0xe0, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVCNTR3_EL0"
+
+  -
+    input:
+      bytes: [ 0x61, 0xe0, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVCNTR3_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x83, 0xe0, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVCNTR4_EL0"
+
+  -
+    input:
+      bytes: [ 0x81, 0xe0, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVCNTR4_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xa3, 0xe0, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVCNTR5_EL0"
+
+  -
+    input:
+      bytes: [ 0xa1, 0xe0, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVCNTR5_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xc3, 0xe0, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVCNTR6_EL0"
+
+  -
+    input:
+      bytes: [ 0xc1, 0xe0, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVCNTR6_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xe3, 0xe0, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVCNTR7_EL0"
+
+  -
+    input:
+      bytes: [ 0xe1, 0xe0, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVCNTR7_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x03, 0xe1, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVCNTR8_EL0"
+
+  -
+    input:
+      bytes: [ 0x01, 0xe1, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVCNTR8_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x23, 0xe1, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVCNTR9_EL0"
+
+  -
+    input:
+      bytes: [ 0x21, 0xe1, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVCNTR9_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x43, 0xe1, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVCNTR10_EL0"
+
+  -
+    input:
+      bytes: [ 0x41, 0xe1, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVCNTR10_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x63, 0xe1, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVCNTR11_EL0"
+
+  -
+    input:
+      bytes: [ 0x61, 0xe1, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVCNTR11_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x83, 0xe1, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVCNTR12_EL0"
+
+  -
+    input:
+      bytes: [ 0x81, 0xe1, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVCNTR12_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xa3, 0xe1, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVCNTR13_EL0"
+
+  -
+    input:
+      bytes: [ 0xa1, 0xe1, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVCNTR13_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xc3, 0xe1, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVCNTR14_EL0"
+
+  -
+    input:
+      bytes: [ 0xc1, 0xe1, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVCNTR14_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xe3, 0xe1, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVCNTR15_EL0"
+
+  -
+    input:
+      bytes: [ 0xe1, 0xe1, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVCNTR15_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x03, 0xe6, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILT2R0_EL0"
+
+  -
+    input:
+      bytes: [ 0x01, 0xe6, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILT2R0_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x23, 0xe6, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILT2R1_EL0"
+
+  -
+    input:
+      bytes: [ 0x21, 0xe6, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILT2R1_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x43, 0xe6, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILT2R2_EL0"
+
+  -
+    input:
+      bytes: [ 0x41, 0xe6, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILT2R2_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x63, 0xe6, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILT2R3_EL0"
+
+  -
+    input:
+      bytes: [ 0x61, 0xe6, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILT2R3_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x83, 0xe6, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILT2R4_EL0"
+
+  -
+    input:
+      bytes: [ 0x81, 0xe6, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILT2R4_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xa3, 0xe6, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILT2R5_EL0"
+
+  -
+    input:
+      bytes: [ 0xa1, 0xe6, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILT2R5_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xc3, 0xe6, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILT2R6_EL0"
+
+  -
+    input:
+      bytes: [ 0xc1, 0xe6, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILT2R6_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xe3, 0xe6, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILT2R7_EL0"
+
+  -
+    input:
+      bytes: [ 0xe1, 0xe6, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILT2R7_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x03, 0xe7, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILT2R8_EL0"
+
+  -
+    input:
+      bytes: [ 0x01, 0xe7, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILT2R8_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x23, 0xe7, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILT2R9_EL0"
+
+  -
+    input:
+      bytes: [ 0x21, 0xe7, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILT2R9_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x43, 0xe7, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILT2R10_EL0"
+
+  -
+    input:
+      bytes: [ 0x41, 0xe7, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILT2R10_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x63, 0xe7, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILT2R11_EL0"
+
+  -
+    input:
+      bytes: [ 0x61, 0xe7, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILT2R11_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x83, 0xe7, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILT2R12_EL0"
+
+  -
+    input:
+      bytes: [ 0x81, 0xe7, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILT2R12_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xa3, 0xe7, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILT2R13_EL0"
+
+  -
+    input:
+      bytes: [ 0xa1, 0xe7, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILT2R13_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xc3, 0xe7, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILT2R14_EL0"
+
+  -
+    input:
+      bytes: [ 0xc1, 0xe7, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILT2R14_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xe3, 0xe7, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILT2R15_EL0"
+
+  -
+    input:
+      bytes: [ 0xe1, 0xe7, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILT2R15_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x03, 0xe4, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILTR0_EL0"
+
+  -
+    input:
+      bytes: [ 0x01, 0xe4, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILTR0_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x23, 0xe4, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILTR1_EL0"
+
+  -
+    input:
+      bytes: [ 0x21, 0xe4, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILTR1_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x43, 0xe4, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILTR2_EL0"
+
+  -
+    input:
+      bytes: [ 0x41, 0xe4, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILTR2_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x63, 0xe4, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILTR3_EL0"
+
+  -
+    input:
+      bytes: [ 0x61, 0xe4, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILTR3_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x83, 0xe4, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILTR4_EL0"
+
+  -
+    input:
+      bytes: [ 0x81, 0xe4, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILTR4_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xa3, 0xe4, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILTR5_EL0"
+
+  -
+    input:
+      bytes: [ 0xa1, 0xe4, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILTR5_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xc3, 0xe4, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILTR6_EL0"
+
+  -
+    input:
+      bytes: [ 0xc1, 0xe4, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILTR6_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xe3, 0xe4, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILTR7_EL0"
+
+  -
+    input:
+      bytes: [ 0xe1, 0xe4, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILTR7_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x03, 0xe5, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILTR8_EL0"
+
+  -
+    input:
+      bytes: [ 0x01, 0xe5, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILTR8_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x23, 0xe5, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILTR9_EL0"
+
+  -
+    input:
+      bytes: [ 0x21, 0xe5, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILTR9_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x43, 0xe5, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILTR10_EL0"
+
+  -
+    input:
+      bytes: [ 0x41, 0xe5, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILTR10_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x63, 0xe5, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILTR11_EL0"
+
+  -
+    input:
+      bytes: [ 0x61, 0xe5, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILTR11_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x83, 0xe5, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILTR12_EL0"
+
+  -
+    input:
+      bytes: [ 0x81, 0xe5, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILTR12_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xa3, 0xe5, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILTR13_EL0"
+
+  -
+    input:
+      bytes: [ 0xa1, 0xe5, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILTR13_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xc3, 0xe5, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILTR14_EL0"
+
+  -
+    input:
+      bytes: [ 0xc1, 0xe5, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILTR14_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xe3, 0xe5, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILTR15_EL0"
+
+  -
+    input:
+      bytes: [ 0xe1, 0xe5, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILTR15_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x03, 0xe2, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVTYPER0_EL0"
+
+  -
+    input:
+      bytes: [ 0x01, 0xe2, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVTYPER0_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x23, 0xe2, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVTYPER1_EL0"
+
+  -
+    input:
+      bytes: [ 0x21, 0xe2, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVTYPER1_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x43, 0xe2, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVTYPER2_EL0"
+
+  -
+    input:
+      bytes: [ 0x41, 0xe2, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVTYPER2_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x63, 0xe2, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVTYPER3_EL0"
+
+  -
+    input:
+      bytes: [ 0x61, 0xe2, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVTYPER3_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x83, 0xe2, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVTYPER4_EL0"
+
+  -
+    input:
+      bytes: [ 0x81, 0xe2, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVTYPER4_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xa3, 0xe2, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVTYPER5_EL0"
+
+  -
+    input:
+      bytes: [ 0xa1, 0xe2, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVTYPER5_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xc3, 0xe2, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVTYPER6_EL0"
+
+  -
+    input:
+      bytes: [ 0xc1, 0xe2, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVTYPER6_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xe3, 0xe2, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVTYPER7_EL0"
+
+  -
+    input:
+      bytes: [ 0xe1, 0xe2, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVTYPER7_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x03, 0xe3, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVTYPER8_EL0"
+
+  -
+    input:
+      bytes: [ 0x01, 0xe3, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVTYPER8_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x23, 0xe3, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVTYPER9_EL0"
+
+  -
+    input:
+      bytes: [ 0x21, 0xe3, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVTYPER9_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x43, 0xe3, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVTYPER10_EL0"
+
+  -
+    input:
+      bytes: [ 0x41, 0xe3, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVTYPER10_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x63, 0xe3, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVTYPER11_EL0"
+
+  -
+    input:
+      bytes: [ 0x61, 0xe3, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVTYPER11_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x83, 0xe3, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVTYPER12_EL0"
+
+  -
+    input:
+      bytes: [ 0x81, 0xe3, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVTYPER12_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xa3, 0xe3, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVTYPER13_EL0"
+
+  -
+    input:
+      bytes: [ 0xa1, 0xe3, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVTYPER13_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xc3, 0xe3, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVTYPER14_EL0"
+
+  -
+    input:
+      bytes: [ 0xc1, 0xe3, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVTYPER14_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xe3, 0xe3, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVTYPER15_EL0"
+
+  -
+    input:
+      bytes: [ 0xe1, 0xe3, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVTYPER15_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x83, 0x9d, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMIIDR_EL1"
+
+  -
+    input:
+      bytes: [ 0x43, 0x9e, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMINTENCLR_EL1"
+
+  -
+    input:
+      bytes: [ 0x41, 0x9e, 0x10, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMINTENCLR_EL1, x1"
+
+  -
+    input:
+      bytes: [ 0x23, 0x9e, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMINTENSET_EL1"
+
+  -
+    input:
+      bytes: [ 0x21, 0x9e, 0x10, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMINTENSET_EL1, x1"
+
+  -
+    input:
+      bytes: [ 0x63, 0x9c, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMOVSCLR_EL0"
+
+  -
+    input:
+      bytes: [ 0x61, 0x9c, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMOVSCLR_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x63, 0x9e, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMOVSSET_EL0"
+
+  -
+    input:
+      bytes: [ 0x61, 0x9e, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMOVSSET_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xa3, 0x9c, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMSELR_EL0"
+
+  -
+    input:
+      bytes: [ 0xa1, 0x9c, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMSELR_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x03, 0x9d, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMCGCR0_EL1"
+
+  -
+    input:
+      bytes: [ 0x23, 0x9d, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMCGCR1_EL1"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x9d, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMCFGR_EL1"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x9e, 0x36, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMROOTCR_EL3"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x9e, 0x16, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMROOTCR_EL3, x3"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x9e, 0x37, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMSCR_EL1"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x9e, 0x17, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMSCR_EL1, x3"
+
+  -
+    input:
+      bytes: [ 0x23, 0x02, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, TRCITEEDCR"
+
+  -
+    input:
+      bytes: [ 0x23, 0x02, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCITEEDCR, x3"
+
+  -
+    input:
+      bytes: [ 0x63, 0x12, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, TRCITECR_EL1"
+
+  -
+    input:
+      bytes: [ 0x61, 0x12, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCITECR_EL1, x1"
+
+  -
+    input:
+      bytes: [ 0x63, 0x12, 0x3d, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, TRCITECR_EL12"
+
+  -
+    input:
+      bytes: [ 0x61, 0x12, 0x1d, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCITECR_EL12, x1"
+
+  -
+    input:
+      bytes: [ 0x63, 0x12, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, TRCITECR_EL2"
+
+  -
+    input:
+      bytes: [ 0x61, 0x12, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCITECR_EL2, x1"
+
+  -
+    input:
+      bytes: [ 0xe1, 0x72, 0x0b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "trcit x1"
+
+  -
+    input:
+      bytes: [ 0x83, 0x9a, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMSDSFR_EL1"
+
+  -
+    input:
+      bytes: [ 0x83, 0x9a, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.3a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PMSDSFR_EL1, x3"
+
+  -
+    input:
+      bytes: [ 0x43, 0x04, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, MDSELR_EL1"
+
+  -
+    input:
+      bytes: [ 0x41, 0x04, 0x10, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr MDSELR_EL1, x1"
+
+  -
+    input:
+      bytes: [ 0x83, 0x9e, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMUACR_EL1"
+
+  -
+    input:
+      bytes: [ 0x81, 0x9e, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PMUACR_EL1, x1"
+
+  -
+    input:
+      bytes: [ 0xe3, 0xeb, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMCCNTSVR_EL1"
+
+  -
+    input:
+      bytes: [ 0x03, 0xec, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMICNTSVR_EL1"
+
+  -
+    input:
+      bytes: [ 0x63, 0x9d, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMSSCR_EL1"
+
+  -
+    input:
+      bytes: [ 0x61, 0x9d, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PMSSCR_EL1, x1"
+
+  -
+    input:
+      bytes: [ 0x03, 0xe8, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR0_EL1"
+
+  -
+    input:
+      bytes: [ 0x23, 0xe8, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR1_EL1"
+
+  -
+    input:
+      bytes: [ 0x43, 0xe8, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR2_EL1"
+
+  -
+    input:
+      bytes: [ 0x63, 0xe8, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR3_EL1"
+
+  -
+    input:
+      bytes: [ 0x83, 0xe8, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR4_EL1"
+
+  -
+    input:
+      bytes: [ 0xa3, 0xe8, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR5_EL1"
+
+  -
+    input:
+      bytes: [ 0xc3, 0xe8, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR6_EL1"
+
+  -
+    input:
+      bytes: [ 0xe3, 0xe8, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR7_EL1"
+
+  -
+    input:
+      bytes: [ 0x03, 0xe9, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR8_EL1"
+
+  -
+    input:
+      bytes: [ 0x23, 0xe9, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR9_EL1"
+
+  -
+    input:
+      bytes: [ 0x43, 0xe9, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR10_EL1"
+
+  -
+    input:
+      bytes: [ 0x63, 0xe9, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR11_EL1"
+
+  -
+    input:
+      bytes: [ 0x83, 0xe9, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR12_EL1"
+
+  -
+    input:
+      bytes: [ 0xa3, 0xe9, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR13_EL1"
+
+  -
+    input:
+      bytes: [ 0xc3, 0xe9, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR14_EL1"
+
+  -
+    input:
+      bytes: [ 0xe3, 0xe9, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR15_EL1"
+
+  -
+    input:
+      bytes: [ 0x03, 0xea, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR16_EL1"
+
+  -
+    input:
+      bytes: [ 0x23, 0xea, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR17_EL1"
+
+  -
+    input:
+      bytes: [ 0x43, 0xea, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR18_EL1"
+
+  -
+    input:
+      bytes: [ 0x63, 0xea, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR19_EL1"
+
+  -
+    input:
+      bytes: [ 0x83, 0xea, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR20_EL1"
+
+  -
+    input:
+      bytes: [ 0xa3, 0xea, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR21_EL1"
+
+  -
+    input:
+      bytes: [ 0xc3, 0xea, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR22_EL1"
+
+  -
+    input:
+      bytes: [ 0xe3, 0xea, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR23_EL1"
+
+  -
+    input:
+      bytes: [ 0x03, 0xeb, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR24_EL1"
+
+  -
+    input:
+      bytes: [ 0x23, 0xeb, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR25_EL1"
+
+  -
+    input:
+      bytes: [ 0x43, 0xeb, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR26_EL1"
+
+  -
+    input:
+      bytes: [ 0x63, 0xeb, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR27_EL1"
+
+  -
+    input:
+      bytes: [ 0x83, 0xeb, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR28_EL1"
+
+  -
+    input:
+      bytes: [ 0xa3, 0xeb, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR29_EL1"
+
+  -
+    input:
+      bytes: [ 0xc3, 0xeb, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMEVCNTSVR30_EL1"
+
+  -
+    input:
+      bytes: [ 0x03, 0x94, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMICNTR_EL0"
+
+  -
+    input:
+      bytes: [ 0x03, 0x94, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PMICNTR_EL0, x3"
+
+  -
+    input:
+      bytes: [ 0x03, 0x96, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMICFILTR_EL0"
+
+  -
+    input:
+      bytes: [ 0x03, 0x96, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PMICFILTR_EL0, x3"
+
+  -
+    input:
+      bytes: [ 0x83, 0x9d, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PMZR_EL0, x3"
+
+  -
+    input:
+      bytes: [ 0xa3, 0x9e, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMECR_EL1"
+
+  -
+    input:
+      bytes: [ 0xa1, 0x9e, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PMECR_EL1, x1"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x9e, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMIAR_EL1"
+
+  -
+    input:
+      bytes: [ 0xe1, 0x9e, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PMIAR_EL1, x1"
+
+  -
+    input:
+      bytes: [ 0x63, 0x9d, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMACCESSR_EL1"
+
+  -
+    input:
+      bytes: [ 0x61, 0x9d, 0x10, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMACCESSR_EL1, x1"
+
+  -
+    input:
+      bytes: [ 0x63, 0x9d, 0x35, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMACCESSR_EL12"
+
+  -
+    input:
+      bytes: [ 0x61, 0x9d, 0x15, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMACCESSR_EL12, x1"
+
+  -
+    input:
+      bytes: [ 0x63, 0x9d, 0x34, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMACCESSR_EL2"
+
+  -
+    input:
+      bytes: [ 0x61, 0x9d, 0x14, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMACCESSR_EL2, x1"
+
+  -
+    input:
+      bytes: [ 0x63, 0x9d, 0x36, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMACCESSR_EL3"
+
+  -
+    input:
+      bytes: [ 0x61, 0x9d, 0x16, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMACCESSR_EL3, x1"
+
+  -
+    input:
+      bytes: [ 0x43, 0x9c, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMCNTENCLR_EL0"
+
+  -
+    input:
+      bytes: [ 0x41, 0x9c, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMCNTENCLR_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x23, 0x9c, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMCNTENSET_EL0"
+
+  -
+    input:
+      bytes: [ 0x21, 0x9c, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMCNTENSET_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x03, 0x9c, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMCR_EL0"
+
+  -
+    input:
+      bytes: [ 0x01, 0x9c, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMCR_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xc3, 0x9d, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMDEVAFF_EL1"
+
+  -
+    input:
+      bytes: [ 0xa3, 0x9d, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMDEVARCH_EL1"
+
+  -
+    input:
+      bytes: [ 0x03, 0xe0, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVCNTR0_EL0"
+
+  -
+    input:
+      bytes: [ 0x01, 0xe0, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVCNTR0_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x23, 0xe0, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVCNTR1_EL0"
+
+  -
+    input:
+      bytes: [ 0x21, 0xe0, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVCNTR1_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x43, 0xe0, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVCNTR2_EL0"
+
+  -
+    input:
+      bytes: [ 0x41, 0xe0, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVCNTR2_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x63, 0xe0, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVCNTR3_EL0"
+
+  -
+    input:
+      bytes: [ 0x61, 0xe0, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVCNTR3_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x83, 0xe0, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVCNTR4_EL0"
+
+  -
+    input:
+      bytes: [ 0x81, 0xe0, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVCNTR4_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xa3, 0xe0, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVCNTR5_EL0"
+
+  -
+    input:
+      bytes: [ 0xa1, 0xe0, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVCNTR5_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xc3, 0xe0, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVCNTR6_EL0"
+
+  -
+    input:
+      bytes: [ 0xc1, 0xe0, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVCNTR6_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xe3, 0xe0, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVCNTR7_EL0"
+
+  -
+    input:
+      bytes: [ 0xe1, 0xe0, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVCNTR7_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x03, 0xe1, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVCNTR8_EL0"
+
+  -
+    input:
+      bytes: [ 0x01, 0xe1, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVCNTR8_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x23, 0xe1, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVCNTR9_EL0"
+
+  -
+    input:
+      bytes: [ 0x21, 0xe1, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVCNTR9_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x43, 0xe1, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVCNTR10_EL0"
+
+  -
+    input:
+      bytes: [ 0x41, 0xe1, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVCNTR10_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x63, 0xe1, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVCNTR11_EL0"
+
+  -
+    input:
+      bytes: [ 0x61, 0xe1, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVCNTR11_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x83, 0xe1, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVCNTR12_EL0"
+
+  -
+    input:
+      bytes: [ 0x81, 0xe1, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVCNTR12_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xa3, 0xe1, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVCNTR13_EL0"
+
+  -
+    input:
+      bytes: [ 0xa1, 0xe1, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVCNTR13_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xc3, 0xe1, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVCNTR14_EL0"
+
+  -
+    input:
+      bytes: [ 0xc1, 0xe1, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVCNTR14_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xe3, 0xe1, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVCNTR15_EL0"
+
+  -
+    input:
+      bytes: [ 0xe1, 0xe1, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVCNTR15_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x03, 0xe6, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILT2R0_EL0"
+
+  -
+    input:
+      bytes: [ 0x01, 0xe6, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILT2R0_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x23, 0xe6, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILT2R1_EL0"
+
+  -
+    input:
+      bytes: [ 0x21, 0xe6, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILT2R1_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x43, 0xe6, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILT2R2_EL0"
+
+  -
+    input:
+      bytes: [ 0x41, 0xe6, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILT2R2_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x63, 0xe6, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILT2R3_EL0"
+
+  -
+    input:
+      bytes: [ 0x61, 0xe6, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILT2R3_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x83, 0xe6, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILT2R4_EL0"
+
+  -
+    input:
+      bytes: [ 0x81, 0xe6, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILT2R4_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xa3, 0xe6, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILT2R5_EL0"
+
+  -
+    input:
+      bytes: [ 0xa1, 0xe6, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILT2R5_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xc3, 0xe6, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILT2R6_EL0"
+
+  -
+    input:
+      bytes: [ 0xc1, 0xe6, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILT2R6_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xe3, 0xe6, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILT2R7_EL0"
+
+  -
+    input:
+      bytes: [ 0xe1, 0xe6, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILT2R7_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x03, 0xe7, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILT2R8_EL0"
+
+  -
+    input:
+      bytes: [ 0x01, 0xe7, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILT2R8_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x23, 0xe7, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILT2R9_EL0"
+
+  -
+    input:
+      bytes: [ 0x21, 0xe7, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILT2R9_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x43, 0xe7, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILT2R10_EL0"
+
+  -
+    input:
+      bytes: [ 0x41, 0xe7, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILT2R10_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x63, 0xe7, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILT2R11_EL0"
+
+  -
+    input:
+      bytes: [ 0x61, 0xe7, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILT2R11_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x83, 0xe7, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILT2R12_EL0"
+
+  -
+    input:
+      bytes: [ 0x81, 0xe7, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILT2R12_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xa3, 0xe7, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILT2R13_EL0"
+
+  -
+    input:
+      bytes: [ 0xa1, 0xe7, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILT2R13_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xc3, 0xe7, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILT2R14_EL0"
+
+  -
+    input:
+      bytes: [ 0xc1, 0xe7, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILT2R14_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xe3, 0xe7, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILT2R15_EL0"
+
+  -
+    input:
+      bytes: [ 0xe1, 0xe7, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILT2R15_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x03, 0xe4, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILTR0_EL0"
+
+  -
+    input:
+      bytes: [ 0x01, 0xe4, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILTR0_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x23, 0xe4, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILTR1_EL0"
+
+  -
+    input:
+      bytes: [ 0x21, 0xe4, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILTR1_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x43, 0xe4, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILTR2_EL0"
+
+  -
+    input:
+      bytes: [ 0x41, 0xe4, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILTR2_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x63, 0xe4, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILTR3_EL0"
+
+  -
+    input:
+      bytes: [ 0x61, 0xe4, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILTR3_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x83, 0xe4, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILTR4_EL0"
+
+  -
+    input:
+      bytes: [ 0x81, 0xe4, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILTR4_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xa3, 0xe4, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILTR5_EL0"
+
+  -
+    input:
+      bytes: [ 0xa1, 0xe4, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILTR5_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xc3, 0xe4, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILTR6_EL0"
+
+  -
+    input:
+      bytes: [ 0xc1, 0xe4, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILTR6_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xe3, 0xe4, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILTR7_EL0"
+
+  -
+    input:
+      bytes: [ 0xe1, 0xe4, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILTR7_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x03, 0xe5, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILTR8_EL0"
+
+  -
+    input:
+      bytes: [ 0x01, 0xe5, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILTR8_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x23, 0xe5, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILTR9_EL0"
+
+  -
+    input:
+      bytes: [ 0x21, 0xe5, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILTR9_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x43, 0xe5, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILTR10_EL0"
+
+  -
+    input:
+      bytes: [ 0x41, 0xe5, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILTR10_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x63, 0xe5, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILTR11_EL0"
+
+  -
+    input:
+      bytes: [ 0x61, 0xe5, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILTR11_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x83, 0xe5, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILTR12_EL0"
+
+  -
+    input:
+      bytes: [ 0x81, 0xe5, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILTR12_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xa3, 0xe5, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILTR13_EL0"
+
+  -
+    input:
+      bytes: [ 0xa1, 0xe5, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILTR13_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xc3, 0xe5, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILTR14_EL0"
+
+  -
+    input:
+      bytes: [ 0xc1, 0xe5, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILTR14_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xe3, 0xe5, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVFILTR15_EL0"
+
+  -
+    input:
+      bytes: [ 0xe1, 0xe5, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVFILTR15_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x03, 0xe2, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVTYPER0_EL0"
+
+  -
+    input:
+      bytes: [ 0x01, 0xe2, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVTYPER0_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x23, 0xe2, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVTYPER1_EL0"
+
+  -
+    input:
+      bytes: [ 0x21, 0xe2, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVTYPER1_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x43, 0xe2, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVTYPER2_EL0"
+
+  -
+    input:
+      bytes: [ 0x41, 0xe2, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVTYPER2_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x63, 0xe2, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVTYPER3_EL0"
+
+  -
+    input:
+      bytes: [ 0x61, 0xe2, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVTYPER3_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x83, 0xe2, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVTYPER4_EL0"
+
+  -
+    input:
+      bytes: [ 0x81, 0xe2, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVTYPER4_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xa3, 0xe2, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVTYPER5_EL0"
+
+  -
+    input:
+      bytes: [ 0xa1, 0xe2, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVTYPER5_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xc3, 0xe2, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVTYPER6_EL0"
+
+  -
+    input:
+      bytes: [ 0xc1, 0xe2, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVTYPER6_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xe3, 0xe2, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVTYPER7_EL0"
+
+  -
+    input:
+      bytes: [ 0xe1, 0xe2, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVTYPER7_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x03, 0xe3, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVTYPER8_EL0"
+
+  -
+    input:
+      bytes: [ 0x01, 0xe3, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVTYPER8_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x23, 0xe3, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVTYPER9_EL0"
+
+  -
+    input:
+      bytes: [ 0x21, 0xe3, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVTYPER9_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x43, 0xe3, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVTYPER10_EL0"
+
+  -
+    input:
+      bytes: [ 0x41, 0xe3, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVTYPER10_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x63, 0xe3, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVTYPER11_EL0"
+
+  -
+    input:
+      bytes: [ 0x61, 0xe3, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVTYPER11_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x83, 0xe3, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVTYPER12_EL0"
+
+  -
+    input:
+      bytes: [ 0x81, 0xe3, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVTYPER12_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xa3, 0xe3, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVTYPER13_EL0"
+
+  -
+    input:
+      bytes: [ 0xa1, 0xe3, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVTYPER13_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xc3, 0xe3, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVTYPER14_EL0"
+
+  -
+    input:
+      bytes: [ 0xc1, 0xe3, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVTYPER14_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xe3, 0xe3, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMEVTYPER15_EL0"
+
+  -
+    input:
+      bytes: [ 0xe1, 0xe3, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMEVTYPER15_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x83, 0x9d, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMIIDR_EL1"
+
+  -
+    input:
+      bytes: [ 0x43, 0x9e, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMINTENCLR_EL1"
+
+  -
+    input:
+      bytes: [ 0x41, 0x9e, 0x10, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMINTENCLR_EL1, x1"
+
+  -
+    input:
+      bytes: [ 0x23, 0x9e, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMINTENSET_EL1"
+
+  -
+    input:
+      bytes: [ 0x21, 0x9e, 0x10, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMINTENSET_EL1, x1"
+
+  -
+    input:
+      bytes: [ 0x63, 0x9c, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMOVSCLR_EL0"
+
+  -
+    input:
+      bytes: [ 0x61, 0x9c, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMOVSCLR_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x63, 0x9e, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMOVSSET_EL0"
+
+  -
+    input:
+      bytes: [ 0x61, 0x9e, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMOVSSET_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0xa3, 0x9c, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMSELR_EL0"
+
+  -
+    input:
+      bytes: [ 0xa1, 0x9c, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMSELR_EL0, x1"
+
+  -
+    input:
+      bytes: [ 0x03, 0x9d, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMCGCR0_EL1"
+
+  -
+    input:
+      bytes: [ 0x23, 0x9d, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMCGCR1_EL1"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x9d, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMCFGR_EL1"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x9e, 0x36, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMROOTCR_EL3"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x9e, 0x16, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMROOTCR_EL3, x3"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x9e, 0x37, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, SPMSCR_EL1"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x9e, 0x17, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMSCR_EL1, x3"
+
+  -
+    input:
+      bytes: [ 0x23, 0x02, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, TRCITEEDCR"
+
+  -
+    input:
+      bytes: [ 0x23, 0x02, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCITEEDCR, x3"
+
+  -
+    input:
+      bytes: [ 0x63, 0x12, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, TRCITECR_EL1"
+
+  -
+    input:
+      bytes: [ 0x61, 0x12, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCITECR_EL1, x1"
+
+  -
+    input:
+      bytes: [ 0x63, 0x12, 0x3d, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, TRCITECR_EL12"
+
+  -
+    input:
+      bytes: [ 0x61, 0x12, 0x1d, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCITECR_EL12, x1"
+
+  -
+    input:
+      bytes: [ 0x63, 0x12, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, TRCITECR_EL2"
+
+  -
+    input:
+      bytes: [ 0x61, 0x12, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCITECR_EL2, x1"
+
+  -
+    input:
+      bytes: [ 0xe1, 0x72, 0x0b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "trcit x1"
+
+  -
+    input:
+      bytes: [ 0x83, 0x9a, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, PMSDSFR_EL1"
+
+  -
+    input:
+      bytes: [ 0x83, 0x9a, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "ite" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PMSDSFR_EL1, x3"
diff --git a/tests/MC/AArch64/armv8.9a-lrcpc3.s.yaml b/tests/MC/AArch64/armv8.9a-lrcpc3.s.yaml
new file mode 100644
index 000000000..77843303e
--- /dev/null
+++ b/tests/MC/AArch64/armv8.9a-lrcpc3.s.yaml
@@ -0,0 +1,1320 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x18, 0x0a, 0x00, 0x99 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "stilp w24, w0, [x16, #-8]!"
+
+  -
+    input:
+      bytes: [ 0x18, 0x0a, 0x00, 0x99 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "stilp w24, w0, [x16, #-8]!"
+
+  -
+    input:
+      bytes: [ 0x39, 0x0a, 0x01, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "stilp x25, x1, [x17, #-16]!"
+
+  -
+    input:
+      bytes: [ 0x39, 0x0a, 0x01, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "stilp x25, x1, [x17, #-16]!"
+
+  -
+    input:
+      bytes: [ 0x5a, 0x1a, 0x02, 0x99 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "stilp w26, w2, [x18]"
+
+  -
+    input:
+      bytes: [ 0x5a, 0x1a, 0x02, 0x99 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "stilp w26, w2, [x18]"
+
+  -
+    input:
+      bytes: [ 0xfb, 0x1b, 0x03, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "stilp x27, x3, [sp]"
+
+  -
+    input:
+      bytes: [ 0xfb, 0x1b, 0x03, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "stilp x27, x3, [sp]"
+
+  -
+    input:
+      bytes: [ 0x9c, 0x0a, 0x44, 0x99 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldiapp w28, w4, [x20], #8"
+
+  -
+    input:
+      bytes: [ 0x9c, 0x0a, 0x44, 0x99 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldiapp w28, w4, [x20], #8"
+
+  -
+    input:
+      bytes: [ 0x9c, 0x0a, 0x44, 0x99 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldiapp w28, w4, [x20], #8"
+
+  -
+    input:
+      bytes: [ 0x9c, 0x0a, 0x44, 0x99 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldiapp w28, w4, [x20], #8"
+
+  -
+    input:
+      bytes: [ 0xbd, 0x0a, 0x45, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldiapp x29, x5, [x21], #16"
+
+  -
+    input:
+      bytes: [ 0xbd, 0x0a, 0x45, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldiapp x29, x5, [x21], #16"
+
+  -
+    input:
+      bytes: [ 0xfe, 0x1b, 0x46, 0x99 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldiapp w30, w6, [sp]"
+
+  -
+    input:
+      bytes: [ 0xfe, 0x1b, 0x46, 0x99 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldiapp w30, w6, [sp]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1a, 0x47, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldiapp xzr, x7, [x23]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1a, 0x47, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldiapp xzr, x7, [x23]"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x09, 0x80, 0x99 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "stlr w3, [x15, #-4]!"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x09, 0x80, 0x99 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "stlr w3, [x15, #-4]!"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x09, 0x80, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "stlr x3, [x15, #-8]!"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x0b, 0x80, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "stlr x3, [sp, #-8]!"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x0b, 0xc0, 0x99 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapr w3, [sp], #4"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x09, 0xc0, 0x99 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapr w3, [x15], #4"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x09, 0xc0, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapr x3, [x15], #8"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x09, 0xc0, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapr x3, [x15], #8"
+
+  -
+    input:
+      bytes: [ 0xe3, 0xf9, 0x1f, 0x1d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "stlur b3, [x15, #-1]"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x29, 0x00, 0x5d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "stlur h3, [x15, #2]"
+
+  -
+    input:
+      bytes: [ 0xe3, 0xd9, 0x1f, 0x9d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "stlur s3, [x15, #-3]"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x4b, 0x00, 0xdd ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "stlur d3, [sp, #4]"
+
+  -
+    input:
+      bytes: [ 0xe3, 0xb9, 0x9f, 0x1d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "stlur q3, [x15, #-5]"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x69, 0x40, 0x1d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapur b3, [x15, #6]"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x99, 0x5f, 0x5d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapur h3, [x15, #-7]"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x89, 0x40, 0x9d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapur s3, [x15, #8]"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x79, 0x5f, 0xdd ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapur d3, [x15, #-9]"
+
+  -
+    input:
+      bytes: [ 0xe3, 0xab, 0xc0, 0x1d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapur q3, [sp, #10]"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x85, 0x01, 0x0d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "stl1 { v3.d }[0], [x15]"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x85, 0x01, 0x0d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "stl1 { v3.d }[0], [x15]"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x87, 0x01, 0x4d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "stl1 { v3.d }[1], [sp]"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x87, 0x01, 0x4d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "stl1 { v3.d }[1], [sp]"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x87, 0x41, 0x0d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldap1 { v3.d }[0], [sp]"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x87, 0x41, 0x0d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldap1 { v3.d }[0], [sp]"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x85, 0x41, 0x4d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldap1 { v3.d }[1], [x15]"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x85, 0x41, 0x4d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldap1 { v3.d }[1], [x15]"
+
+  -
+    input:
+      bytes: [ 0x18, 0x0a, 0x00, 0x99 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "stilp w24, w0, [x16, #-8]!"
+
+  -
+    input:
+      bytes: [ 0x18, 0x0a, 0x00, 0x99 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "stilp w24, w0, [x16, #-8]!"
+
+  -
+    input:
+      bytes: [ 0x39, 0x0a, 0x01, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "stilp x25, x1, [x17, #-16]!"
+
+  -
+    input:
+      bytes: [ 0x39, 0x0a, 0x01, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "stilp x25, x1, [x17, #-16]!"
+
+  -
+    input:
+      bytes: [ 0x5a, 0x1a, 0x02, 0x99 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "stilp w26, w2, [x18]"
+
+  -
+    input:
+      bytes: [ 0x5a, 0x1a, 0x02, 0x99 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "stilp w26, w2, [x18]"
+
+  -
+    input:
+      bytes: [ 0xfb, 0x1b, 0x03, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "stilp x27, x3, [sp]"
+
+  -
+    input:
+      bytes: [ 0xfb, 0x1b, 0x03, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "stilp x27, x3, [sp]"
+
+  -
+    input:
+      bytes: [ 0x9c, 0x0a, 0x44, 0x99 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldiapp w28, w4, [x20], #8"
+
+  -
+    input:
+      bytes: [ 0x9c, 0x0a, 0x44, 0x99 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldiapp w28, w4, [x20], #8"
+
+  -
+    input:
+      bytes: [ 0x9c, 0x0a, 0x44, 0x99 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldiapp w28, w4, [x20], #8"
+
+  -
+    input:
+      bytes: [ 0x9c, 0x0a, 0x44, 0x99 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldiapp w28, w4, [x20], #8"
+
+  -
+    input:
+      bytes: [ 0xbd, 0x0a, 0x45, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldiapp x29, x5, [x21], #16"
+
+  -
+    input:
+      bytes: [ 0xbd, 0x0a, 0x45, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldiapp x29, x5, [x21], #16"
+
+  -
+    input:
+      bytes: [ 0xfe, 0x1b, 0x46, 0x99 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldiapp w30, w6, [sp]"
+
+  -
+    input:
+      bytes: [ 0xfe, 0x1b, 0x46, 0x99 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldiapp w30, w6, [sp]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1a, 0x47, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldiapp xzr, x7, [x23]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1a, 0x47, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldiapp xzr, x7, [x23]"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x09, 0x80, 0x99 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "stlr w3, [x15, #-4]!"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x09, 0x80, 0x99 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "stlr w3, [x15, #-4]!"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x09, 0x80, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "stlr x3, [x15, #-8]!"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x0b, 0x80, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "stlr x3, [sp, #-8]!"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x0b, 0xc0, 0x99 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapr w3, [sp], #4"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x09, 0xc0, 0x99 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapr w3, [x15], #4"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x09, 0xc0, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapr x3, [x15], #8"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x09, 0xc0, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapr x3, [x15], #8"
+
+  -
+    input:
+      bytes: [ 0xe3, 0xf9, 0x1f, 0x1d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "stlur b3, [x15, #-1]"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x29, 0x00, 0x5d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "stlur h3, [x15, #2]"
+
+  -
+    input:
+      bytes: [ 0xe3, 0xd9, 0x1f, 0x9d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "stlur s3, [x15, #-3]"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x4b, 0x00, 0xdd ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "stlur d3, [sp, #4]"
+
+  -
+    input:
+      bytes: [ 0xe3, 0xb9, 0x9f, 0x1d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "stlur q3, [x15, #-5]"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x69, 0x40, 0x1d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapur b3, [x15, #6]"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x99, 0x5f, 0x5d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapur h3, [x15, #-7]"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x89, 0x40, 0x9d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapur s3, [x15, #8]"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x79, 0x5f, 0xdd ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapur d3, [x15, #-9]"
+
+  -
+    input:
+      bytes: [ 0xe3, 0xab, 0xc0, 0x1d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapur q3, [sp, #10]"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x85, 0x01, 0x0d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "stl1 { v3.d }[0], [x15]"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x85, 0x01, 0x0d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "stl1 { v3.d }[0], [x15]"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x87, 0x01, 0x4d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "stl1 { v3.d }[1], [sp]"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x87, 0x01, 0x4d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "stl1 { v3.d }[1], [sp]"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x87, 0x41, 0x0d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldap1 { v3.d }[0], [sp]"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x87, 0x41, 0x0d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldap1 { v3.d }[0], [sp]"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x85, 0x41, 0x4d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldap1 { v3.d }[1], [x15]"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x85, 0x41, 0x4d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldap1 { v3.d }[1], [x15]"
+
+  -
+    input:
+      bytes: [ 0x18, 0x0a, 0x00, 0x99 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "stilp w24, w0, [x16, #-8]!"
+
+  -
+    input:
+      bytes: [ 0x18, 0x0a, 0x00, 0x99 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "stilp w24, w0, [x16, #-8]!"
+
+  -
+    input:
+      bytes: [ 0x39, 0x0a, 0x01, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "stilp x25, x1, [x17, #-16]!"
+
+  -
+    input:
+      bytes: [ 0x39, 0x0a, 0x01, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "stilp x25, x1, [x17, #-16]!"
+
+  -
+    input:
+      bytes: [ 0x5a, 0x1a, 0x02, 0x99 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "stilp w26, w2, [x18]"
+
+  -
+    input:
+      bytes: [ 0x5a, 0x1a, 0x02, 0x99 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "stilp w26, w2, [x18]"
+
+  -
+    input:
+      bytes: [ 0xfb, 0x1b, 0x03, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "stilp x27, x3, [sp]"
+
+  -
+    input:
+      bytes: [ 0xfb, 0x1b, 0x03, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "stilp x27, x3, [sp]"
+
+  -
+    input:
+      bytes: [ 0x9c, 0x0a, 0x44, 0x99 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldiapp w28, w4, [x20], #8"
+
+  -
+    input:
+      bytes: [ 0x9c, 0x0a, 0x44, 0x99 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldiapp w28, w4, [x20], #8"
+
+  -
+    input:
+      bytes: [ 0x9c, 0x0a, 0x44, 0x99 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldiapp w28, w4, [x20], #8"
+
+  -
+    input:
+      bytes: [ 0x9c, 0x0a, 0x44, 0x99 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldiapp w28, w4, [x20], #8"
+
+  -
+    input:
+      bytes: [ 0xbd, 0x0a, 0x45, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldiapp x29, x5, [x21], #16"
+
+  -
+    input:
+      bytes: [ 0xbd, 0x0a, 0x45, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldiapp x29, x5, [x21], #16"
+
+  -
+    input:
+      bytes: [ 0xfe, 0x1b, 0x46, 0x99 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldiapp w30, w6, [sp]"
+
+  -
+    input:
+      bytes: [ 0xfe, 0x1b, 0x46, 0x99 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldiapp w30, w6, [sp]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1a, 0x47, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldiapp xzr, x7, [x23]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1a, 0x47, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldiapp xzr, x7, [x23]"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x09, 0x80, 0x99 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "stlr w3, [x15, #-4]!"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x09, 0x80, 0x99 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "stlr w3, [x15, #-4]!"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x09, 0x80, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "stlr x3, [x15, #-8]!"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x0b, 0x80, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "stlr x3, [sp, #-8]!"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x0b, 0xc0, 0x99 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapr w3, [sp], #4"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x09, 0xc0, 0x99 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapr w3, [x15], #4"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x09, 0xc0, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapr x3, [x15], #8"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x09, 0xc0, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapr x3, [x15], #8"
+
+  -
+    input:
+      bytes: [ 0xe3, 0xf9, 0x1f, 0x1d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "stlur b3, [x15, #-1]"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x29, 0x00, 0x5d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "stlur h3, [x15, #2]"
+
+  -
+    input:
+      bytes: [ 0xe3, 0xd9, 0x1f, 0x9d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "stlur s3, [x15, #-3]"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x4b, 0x00, 0xdd ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "stlur d3, [sp, #4]"
+
+  -
+    input:
+      bytes: [ 0xe3, 0xb9, 0x9f, 0x1d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "stlur q3, [x15, #-5]"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x69, 0x40, 0x1d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapur b3, [x15, #6]"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x99, 0x5f, 0x5d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapur h3, [x15, #-7]"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x89, 0x40, 0x9d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapur s3, [x15, #8]"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x79, 0x5f, 0xdd ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapur d3, [x15, #-9]"
+
+  -
+    input:
+      bytes: [ 0xe3, 0xab, 0xc0, 0x1d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapur q3, [sp, #10]"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x85, 0x01, 0x0d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "stl1 { v3.d }[0], [x15]"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x85, 0x01, 0x0d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "stl1 { v3.d }[0], [x15]"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x87, 0x01, 0x4d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "stl1 { v3.d }[1], [sp]"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x87, 0x01, 0x4d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "stl1 { v3.d }[1], [sp]"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x87, 0x41, 0x0d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldap1 { v3.d }[0], [sp]"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x87, 0x41, 0x0d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldap1 { v3.d }[0], [sp]"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x85, 0x41, 0x4d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldap1 { v3.d }[1], [x15]"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x85, 0x41, 0x4d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldap1 { v3.d }[1], [x15]"
diff --git a/tests/MC/AArch64/armv8.9a-lrcpc3.txt.yaml b/tests/MC/AArch64/armv8.9a-lrcpc3.txt.yaml
new file mode 100644
index 000000000..75f2f246d
--- /dev/null
+++ b/tests/MC/AArch64/armv8.9a-lrcpc3.txt.yaml
@@ -0,0 +1,1020 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x18, 0x0a, 0x00, 0x99 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "stilp w24, w0, [x16, #-8]!"
+
+  -
+    input:
+      bytes: [ 0x18, 0x0a, 0x00, 0x99 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "stilp w24, w0, [x16, #-8]!"
+
+  -
+    input:
+      bytes: [ 0x39, 0x0a, 0x01, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "stilp x25, x1, [x17, #-16]!"
+
+  -
+    input:
+      bytes: [ 0x39, 0x0a, 0x01, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "stilp x25, x1, [x17, #-16]!"
+
+  -
+    input:
+      bytes: [ 0x5a, 0x1a, 0x02, 0x99 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "stilp w26, w2, [x18]"
+
+  -
+    input:
+      bytes: [ 0xfb, 0x1b, 0x03, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "stilp x27, x3, [sp]"
+
+  -
+    input:
+      bytes: [ 0x9c, 0x0a, 0x44, 0x99 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldiapp w28, w4, [x20], #8"
+
+  -
+    input:
+      bytes: [ 0x9c, 0x0a, 0x44, 0x99 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldiapp w28, w4, [x20], #8"
+
+  -
+    input:
+      bytes: [ 0xbd, 0x0a, 0x45, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldiapp x29, x5, [x21], #16"
+
+  -
+    input:
+      bytes: [ 0xbd, 0x0a, 0x45, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldiapp x29, x5, [x21], #16"
+
+  -
+    input:
+      bytes: [ 0xfe, 0x1b, 0x46, 0x99 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldiapp w30, w6, [sp]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1a, 0x47, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldiapp xzr, x7, [x23]"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x09, 0x80, 0x99 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "stlr w3, [x15, #-4]!"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x09, 0x80, 0x99 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "stlr w3, [x15, #-4]!"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x09, 0x80, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "stlr x3, [x15, #-8]!"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x0b, 0x80, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "stlr x3, [sp, #-8]!"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x0b, 0xc0, 0x99 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapr w3, [sp], #4"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x09, 0xc0, 0x99 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapr w3, [x15], #4"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x09, 0xc0, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapr x3, [x15], #8"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x09, 0xc0, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapr x3, [x15], #8"
+
+  -
+    input:
+      bytes: [ 0xe3, 0xf9, 0x1f, 0x1d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "stlur b3, [x15, #-1]"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x29, 0x00, 0x5d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "stlur h3, [x15, #2]"
+
+  -
+    input:
+      bytes: [ 0xe3, 0xd9, 0x1f, 0x9d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "stlur s3, [x15, #-3]"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x4b, 0x00, 0xdd ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "stlur d3, [sp, #4]"
+
+  -
+    input:
+      bytes: [ 0xe3, 0xb9, 0x9f, 0x1d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "stlur q3, [x15, #-5]"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x69, 0x40, 0x1d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapur b3, [x15, #6]"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x99, 0x5f, 0x5d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapur h3, [x15, #-7]"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x89, 0x40, 0x9d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapur s3, [x15, #8]"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x79, 0x5f, 0xdd ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapur d3, [x15, #-9]"
+
+  -
+    input:
+      bytes: [ 0xe3, 0xab, 0xc0, 0x1d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapur q3, [sp, #10]"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x85, 0x01, 0x0d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "stl1 { v3.d }[0], [x15]"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x87, 0x01, 0x4d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "stl1 { v3.d }[1], [sp]"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x87, 0x41, 0x0d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldap1 { v3.d }[0], [sp]"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x85, 0x41, 0x4d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldap1 { v3.d }[1], [x15]"
+
+  -
+    input:
+      bytes: [ 0x18, 0x0a, 0x00, 0x99 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "stilp w24, w0, [x16, #-8]!"
+
+  -
+    input:
+      bytes: [ 0x18, 0x0a, 0x00, 0x99 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "stilp w24, w0, [x16, #-8]!"
+
+  -
+    input:
+      bytes: [ 0x39, 0x0a, 0x01, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "stilp x25, x1, [x17, #-16]!"
+
+  -
+    input:
+      bytes: [ 0x39, 0x0a, 0x01, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "stilp x25, x1, [x17, #-16]!"
+
+  -
+    input:
+      bytes: [ 0x5a, 0x1a, 0x02, 0x99 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "stilp w26, w2, [x18]"
+
+  -
+    input:
+      bytes: [ 0xfb, 0x1b, 0x03, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "stilp x27, x3, [sp]"
+
+  -
+    input:
+      bytes: [ 0x9c, 0x0a, 0x44, 0x99 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldiapp w28, w4, [x20], #8"
+
+  -
+    input:
+      bytes: [ 0x9c, 0x0a, 0x44, 0x99 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldiapp w28, w4, [x20], #8"
+
+  -
+    input:
+      bytes: [ 0xbd, 0x0a, 0x45, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldiapp x29, x5, [x21], #16"
+
+  -
+    input:
+      bytes: [ 0xbd, 0x0a, 0x45, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldiapp x29, x5, [x21], #16"
+
+  -
+    input:
+      bytes: [ 0xfe, 0x1b, 0x46, 0x99 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldiapp w30, w6, [sp]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1a, 0x47, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldiapp xzr, x7, [x23]"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x09, 0x80, 0x99 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "stlr w3, [x15, #-4]!"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x09, 0x80, 0x99 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "stlr w3, [x15, #-4]!"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x09, 0x80, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "stlr x3, [x15, #-8]!"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x0b, 0x80, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "stlr x3, [sp, #-8]!"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x0b, 0xc0, 0x99 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapr w3, [sp], #4"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x09, 0xc0, 0x99 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapr w3, [x15], #4"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x09, 0xc0, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapr x3, [x15], #8"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x09, 0xc0, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapr x3, [x15], #8"
+
+  -
+    input:
+      bytes: [ 0xe3, 0xf9, 0x1f, 0x1d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "stlur b3, [x15, #-1]"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x29, 0x00, 0x5d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "stlur h3, [x15, #2]"
+
+  -
+    input:
+      bytes: [ 0xe3, 0xd9, 0x1f, 0x9d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "stlur s3, [x15, #-3]"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x4b, 0x00, 0xdd ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "stlur d3, [sp, #4]"
+
+  -
+    input:
+      bytes: [ 0xe3, 0xb9, 0x9f, 0x1d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "stlur q3, [x15, #-5]"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x69, 0x40, 0x1d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapur b3, [x15, #6]"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x99, 0x5f, 0x5d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapur h3, [x15, #-7]"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x89, 0x40, 0x9d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapur s3, [x15, #8]"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x79, 0x5f, 0xdd ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapur d3, [x15, #-9]"
+
+  -
+    input:
+      bytes: [ 0xe3, 0xab, 0xc0, 0x1d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapur q3, [sp, #10]"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x85, 0x01, 0x0d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "stl1 { v3.d }[0], [x15]"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x87, 0x01, 0x4d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "stl1 { v3.d }[1], [sp]"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x87, 0x41, 0x0d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldap1 { v3.d }[0], [sp]"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x85, 0x41, 0x4d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldap1 { v3.d }[1], [x15]"
+
+  -
+    input:
+      bytes: [ 0x18, 0x0a, 0x00, 0x99 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "stilp w24, w0, [x16, #-8]!"
+
+  -
+    input:
+      bytes: [ 0x18, 0x0a, 0x00, 0x99 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "stilp w24, w0, [x16, #-8]!"
+
+  -
+    input:
+      bytes: [ 0x39, 0x0a, 0x01, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "stilp x25, x1, [x17, #-16]!"
+
+  -
+    input:
+      bytes: [ 0x39, 0x0a, 0x01, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "stilp x25, x1, [x17, #-16]!"
+
+  -
+    input:
+      bytes: [ 0x5a, 0x1a, 0x02, 0x99 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "stilp w26, w2, [x18]"
+
+  -
+    input:
+      bytes: [ 0xfb, 0x1b, 0x03, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "stilp x27, x3, [sp]"
+
+  -
+    input:
+      bytes: [ 0x9c, 0x0a, 0x44, 0x99 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldiapp w28, w4, [x20], #8"
+
+  -
+    input:
+      bytes: [ 0x9c, 0x0a, 0x44, 0x99 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldiapp w28, w4, [x20], #8"
+
+  -
+    input:
+      bytes: [ 0xbd, 0x0a, 0x45, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldiapp x29, x5, [x21], #16"
+
+  -
+    input:
+      bytes: [ 0xbd, 0x0a, 0x45, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldiapp x29, x5, [x21], #16"
+
+  -
+    input:
+      bytes: [ 0xfe, 0x1b, 0x46, 0x99 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldiapp w30, w6, [sp]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x1a, 0x47, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldiapp xzr, x7, [x23]"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x09, 0x80, 0x99 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "stlr w3, [x15, #-4]!"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x09, 0x80, 0x99 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "stlr w3, [x15, #-4]!"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x09, 0x80, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "stlr x3, [x15, #-8]!"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x0b, 0x80, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "stlr x3, [sp, #-8]!"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x0b, 0xc0, 0x99 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapr w3, [sp], #4"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x09, 0xc0, 0x99 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapr w3, [x15], #4"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x09, 0xc0, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapr x3, [x15], #8"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x09, 0xc0, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapr x3, [x15], #8"
+
+  -
+    input:
+      bytes: [ 0xe3, 0xf9, 0x1f, 0x1d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "stlur b3, [x15, #-1]"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x29, 0x00, 0x5d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "stlur h3, [x15, #2]"
+
+  -
+    input:
+      bytes: [ 0xe3, 0xd9, 0x1f, 0x9d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "stlur s3, [x15, #-3]"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x4b, 0x00, 0xdd ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "stlur d3, [sp, #4]"
+
+  -
+    input:
+      bytes: [ 0xe3, 0xb9, 0x9f, 0x1d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "stlur q3, [x15, #-5]"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x69, 0x40, 0x1d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapur b3, [x15, #6]"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x99, 0x5f, 0x5d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapur h3, [x15, #-7]"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x89, 0x40, 0x9d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapur s3, [x15, #8]"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x79, 0x5f, 0xdd ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapur d3, [x15, #-9]"
+
+  -
+    input:
+      bytes: [ 0xe3, 0xab, 0xc0, 0x1d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldapur q3, [sp, #10]"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x85, 0x01, 0x0d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "stl1 { v3.d }[0], [x15]"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x87, 0x01, 0x4d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "stl1 { v3.d }[1], [sp]"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x87, 0x41, 0x0d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldap1 { v3.d }[0], [sp]"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x85, 0x41, 0x4d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a", "rcpc3" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldap1 { v3.d }[1], [x15]"
diff --git a/tests/MC/AArch64/armv8.9a-pfar.s.yaml b/tests/MC/AArch64/armv8.9a-pfar.s.yaml
new file mode 100644
index 000000000..cacd31866
--- /dev/null
+++ b/tests/MC/AArch64/armv8.9a-pfar.s.yaml
@@ -0,0 +1,80 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xa0, 0x60, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, PFAR_EL1"
+
+  -
+    input:
+      bytes: [ 0xa0, 0x60, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PFAR_EL1, x0"
+
+  -
+    input:
+      bytes: [ 0xa0, 0x60, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, PFAR_EL2"
+
+  -
+    input:
+      bytes: [ 0xa0, 0x60, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PFAR_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0xa0, 0x60, 0x3d, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, PFAR_EL12"
+
+  -
+    input:
+      bytes: [ 0xa0, 0x60, 0x1d, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PFAR_EL12, x0"
+
+  -
+    input:
+      bytes: [ 0xa0, 0x60, 0x3e, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, MFAR_EL3"
+
+  -
+    input:
+      bytes: [ 0xa0, 0x60, 0x1e, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr MFAR_EL3, x0"
diff --git a/tests/MC/AArch64/armv8.9a-prfm-slc.s.yaml b/tests/MC/AArch64/armv8.9a-prfm-slc.s.yaml
new file mode 100644
index 000000000..28b863fb1
--- /dev/null
+++ b/tests/MC/AArch64/armv8.9a-prfm-slc.s.yaml
@@ -0,0 +1,210 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x66, 0x00, 0x80, 0xf9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfm pldslckeep, [x3]"
+
+  -
+    input:
+      bytes: [ 0x67, 0x00, 0x80, 0xf9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfm pldslcstrm, [x3]"
+
+  -
+    input:
+      bytes: [ 0x6e, 0x00, 0x80, 0xf9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfm plislckeep, [x3]"
+
+  -
+    input:
+      bytes: [ 0x6f, 0x00, 0x80, 0xf9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfm plislcstrm, [x3]"
+
+  -
+    input:
+      bytes: [ 0x76, 0x00, 0x80, 0xf9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfm pstslckeep, [x3]"
+
+  -
+    input:
+      bytes: [ 0x77, 0x00, 0x80, 0xf9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfm pstslcstrm, [x3]"
+
+  -
+    input:
+      bytes: [ 0x66, 0x68, 0xa5, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfm pldslckeep, [x3, x5]"
+
+  -
+    input:
+      bytes: [ 0x66, 0x00, 0x80, 0xf9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.9a" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfm pldslckeep, [x3]"
+
+  -
+    input:
+      bytes: [ 0x67, 0x00, 0x80, 0xf9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.9a" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfm pldslcstrm, [x3]"
+
+  -
+    input:
+      bytes: [ 0x6e, 0x00, 0x80, 0xf9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.9a" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfm plislckeep, [x3]"
+
+  -
+    input:
+      bytes: [ 0x6f, 0x00, 0x80, 0xf9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.9a" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfm plislcstrm, [x3]"
+
+  -
+    input:
+      bytes: [ 0x76, 0x00, 0x80, 0xf9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.9a" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfm pstslckeep, [x3]"
+
+  -
+    input:
+      bytes: [ 0x77, 0x00, 0x80, 0xf9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.9a" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfm pstslcstrm, [x3]"
+
+  -
+    input:
+      bytes: [ 0x66, 0x68, 0xa5, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.9a" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfm pldslckeep, [x3, x5]"
+
+  -
+    input:
+      bytes: [ 0x66, 0x00, 0x80, 0xf9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfm pldslckeep, [x3]"
+
+  -
+    input:
+      bytes: [ 0x67, 0x00, 0x80, 0xf9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfm pldslcstrm, [x3]"
+
+  -
+    input:
+      bytes: [ 0x6e, 0x00, 0x80, 0xf9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfm plislckeep, [x3]"
+
+  -
+    input:
+      bytes: [ 0x6f, 0x00, 0x80, 0xf9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfm plislcstrm, [x3]"
+
+  -
+    input:
+      bytes: [ 0x76, 0x00, 0x80, 0xf9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfm pstslckeep, [x3]"
+
+  -
+    input:
+      bytes: [ 0x77, 0x00, 0x80, 0xf9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfm pstslcstrm, [x3]"
+
+  -
+    input:
+      bytes: [ 0x66, 0x68, 0xa5, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfm pldslckeep, [x3, x5]"
diff --git a/tests/MC/AArch64/armv8.9a-rasv2.s.yaml b/tests/MC/AArch64/armv8.9a-rasv2.s.yaml
new file mode 100644
index 000000000..b9f2e7540
--- /dev/null
+++ b/tests/MC/AArch64/armv8.9a-rasv2.s.yaml
@@ -0,0 +1,30 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x40, 0x53, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "rasv2" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, ERXGSR_EL1"
+
+  -
+    input:
+      bytes: [ 0x40, 0x53, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.9a" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, ERXGSR_EL1"
+
+  -
+    input:
+      bytes: [ 0x40, 0x53, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, ERXGSR_EL1"
diff --git a/tests/MC/AArch64/armv8.9a-specres2.s.yaml b/tests/MC/AArch64/armv8.9a-specres2.s.yaml
new file mode 100644
index 000000000..d15a8b55c
--- /dev/null
+++ b/tests/MC/AArch64/armv8.9a-specres2.s.yaml
@@ -0,0 +1,60 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xc0, 0x73, 0x0b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "specres2" ]
+    expected:
+      insns:
+        -
+          asm_text: "cosp rctx, x0"
+
+  -
+    input:
+      bytes: [ 0xc0, 0x73, 0x0b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "specres2" ]
+    expected:
+      insns:
+        -
+          asm_text: "cosp rctx, x0"
+
+  -
+    input:
+      bytes: [ 0xc0, 0x73, 0x0b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a" ]
+    expected:
+      insns:
+        -
+          asm_text: "cosp rctx, x0"
+
+  -
+    input:
+      bytes: [ 0xc0, 0x73, 0x0b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8.9a" ]
+    expected:
+      insns:
+        -
+          asm_text: "cosp rctx, x0"
+
+  -
+    input:
+      bytes: [ 0xc0, 0x73, 0x0b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "cosp rctx, x0"
+
+  -
+    input:
+      bytes: [ 0xc0, 0x73, 0x0b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "cosp rctx, x0"
diff --git a/tests/MC/AArch64/armv8a-fpmul.s.yaml b/tests/MC/AArch64/armv8a-fpmul.s.yaml
new file mode 100644
index 000000000..7708e20d7
--- /dev/null
+++ b/tests/MC/AArch64/armv8a-fpmul.s.yaml
@@ -0,0 +1,480 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0xec, 0x22, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "fp16fml" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal v0.2s, v1.2h, v2.2h"
+
+  -
+    input:
+      bytes: [ 0x20, 0xec, 0xa2, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "fp16fml" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl v0.2s, v1.2h, v2.2h"
+
+  -
+    input:
+      bytes: [ 0x20, 0xec, 0x22, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "fp16fml" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal v0.4s, v1.4h, v2.4h"
+
+  -
+    input:
+      bytes: [ 0x20, 0xec, 0xa2, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "fp16fml" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl v0.4s, v1.4h, v2.4h"
+
+  -
+    input:
+      bytes: [ 0x20, 0xcc, 0x22, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "fp16fml" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal2 v0.2s, v1.2h, v2.2h"
+
+  -
+    input:
+      bytes: [ 0x20, 0xcc, 0xa2, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "fp16fml" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl2 v0.2s, v1.2h, v2.2h"
+
+  -
+    input:
+      bytes: [ 0x20, 0xcc, 0x22, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "fp16fml" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal2 v0.4s, v1.4h, v2.4h"
+
+  -
+    input:
+      bytes: [ 0x20, 0xcc, 0xa2, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "fp16fml" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl2 v0.4s, v1.4h, v2.4h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x08, 0xb2, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "fp16fml" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal v0.2s, v1.2h, v2.h[7]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x48, 0xb2, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "fp16fml" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl v0.2s, v1.2h, v2.h[7]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x08, 0xb2, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "fp16fml" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal v0.4s, v1.4h, v2.h[7]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x48, 0xb2, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "fp16fml" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl v0.4s, v1.4h, v2.h[7]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x88, 0xb2, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "fp16fml" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal2 v0.2s, v1.2h, v2.h[7]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc8, 0xb2, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "fp16fml" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl2 v0.2s, v1.2h, v2.h[7]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x88, 0xb2, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "fp16fml" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal2 v0.4s, v1.4h, v2.h[7]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc8, 0xb2, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "fp16fml" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl2 v0.4s, v1.4h, v2.h[7]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x08, 0x92, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "fp16fml" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal v0.2s, v1.2h, v2.h[5]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x48, 0x92, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "fp16fml" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl v0.2s, v1.2h, v2.h[5]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x08, 0x92, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "fp16fml" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal v0.4s, v1.4h, v2.h[5]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x48, 0x92, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "fp16fml" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl v0.4s, v1.4h, v2.h[5]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x88, 0x92, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "fp16fml" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal2 v0.2s, v1.2h, v2.h[5]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc8, 0x92, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "fp16fml" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl2 v0.2s, v1.2h, v2.h[5]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x88, 0x92, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "fp16fml" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal2 v0.4s, v1.4h, v2.h[5]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc8, 0x92, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "fp16fml" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl2 v0.4s, v1.4h, v2.h[5]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xec, 0x22, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-fullfp16", "+fp16fml" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal v0.2s, v1.2h, v2.2h"
+
+  -
+    input:
+      bytes: [ 0x20, 0xec, 0xa2, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-fullfp16", "+fp16fml" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl v0.2s, v1.2h, v2.2h"
+
+  -
+    input:
+      bytes: [ 0x20, 0xec, 0x22, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-fullfp16", "+fp16fml" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal v0.4s, v1.4h, v2.4h"
+
+  -
+    input:
+      bytes: [ 0x20, 0xec, 0xa2, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-fullfp16", "+fp16fml" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl v0.4s, v1.4h, v2.4h"
+
+  -
+    input:
+      bytes: [ 0x20, 0xcc, 0x22, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-fullfp16", "+fp16fml" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal2 v0.2s, v1.2h, v2.2h"
+
+  -
+    input:
+      bytes: [ 0x20, 0xcc, 0xa2, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-fullfp16", "+fp16fml" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl2 v0.2s, v1.2h, v2.2h"
+
+  -
+    input:
+      bytes: [ 0x20, 0xcc, 0x22, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-fullfp16", "+fp16fml" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal2 v0.4s, v1.4h, v2.4h"
+
+  -
+    input:
+      bytes: [ 0x20, 0xcc, 0xa2, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-fullfp16", "+fp16fml" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl2 v0.4s, v1.4h, v2.4h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x08, 0xb2, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-fullfp16", "+fp16fml" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal v0.2s, v1.2h, v2.h[7]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x48, 0xb2, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-fullfp16", "+fp16fml" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl v0.2s, v1.2h, v2.h[7]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x08, 0xb2, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-fullfp16", "+fp16fml" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal v0.4s, v1.4h, v2.h[7]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x48, 0xb2, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-fullfp16", "+fp16fml" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl v0.4s, v1.4h, v2.h[7]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x88, 0xb2, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-fullfp16", "+fp16fml" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal2 v0.2s, v1.2h, v2.h[7]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc8, 0xb2, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-fullfp16", "+fp16fml" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl2 v0.2s, v1.2h, v2.h[7]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x88, 0xb2, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-fullfp16", "+fp16fml" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal2 v0.4s, v1.4h, v2.h[7]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc8, 0xb2, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-fullfp16", "+fp16fml" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl2 v0.4s, v1.4h, v2.h[7]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x08, 0x92, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-fullfp16", "+fp16fml" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal v0.2s, v1.2h, v2.h[5]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x48, 0x92, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-fullfp16", "+fp16fml" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl v0.2s, v1.2h, v2.h[5]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x08, 0x92, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-fullfp16", "+fp16fml" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal v0.4s, v1.4h, v2.h[5]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x48, 0x92, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-fullfp16", "+fp16fml" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl v0.4s, v1.4h, v2.h[5]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x88, 0x92, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-fullfp16", "+fp16fml" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal2 v0.2s, v1.2h, v2.h[5]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc8, 0x92, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-fullfp16", "+fp16fml" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl2 v0.2s, v1.2h, v2.h[5]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x88, 0x92, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-fullfp16", "+fp16fml" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlal2 v0.4s, v1.4h, v2.h[5]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc8, 0x92, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "-fullfp16", "+fp16fml" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmlsl2 v0.4s, v1.4h, v2.h[5]"
diff --git a/tests/MC/AArch64/armv8r-inst.s.yaml b/tests/MC/AArch64/armv8r-inst.s.yaml
new file mode 100644
index 000000000..604085821
--- /dev/null
+++ b/tests/MC/AArch64/armv8r-inst.s.yaml
@@ -0,0 +1,10 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x9f, 0x3c, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "dfb"
diff --git a/tests/MC/AArch64/armv8r-sysreg.s.yaml b/tests/MC/AArch64/armv8r-sysreg.s.yaml
new file mode 100644
index 000000000..d593ffb09
--- /dev/null
+++ b/tests/MC/AArch64/armv8r-sysreg.s.yaml
@@ -0,0 +1,2850 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, TTBR0_EL2"
+
+  -
+    input:
+      bytes: [ 0x80, 0x00, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, MPUIR_EL1"
+
+  -
+    input:
+      bytes: [ 0x80, 0x00, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, MPUIR_EL2"
+
+  -
+    input:
+      bytes: [ 0x20, 0x61, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, PRENR_EL1"
+
+  -
+    input:
+      bytes: [ 0x20, 0x61, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, PRENR_EL2"
+
+  -
+    input:
+      bytes: [ 0x20, 0x62, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, PRSELR_EL1"
+
+  -
+    input:
+      bytes: [ 0x20, 0x62, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, PRSELR_EL2"
+
+  -
+    input:
+      bytes: [ 0x00, 0x68, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, PRBAR_EL1"
+
+  -
+    input:
+      bytes: [ 0x00, 0x68, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, PRBAR_EL2"
+
+  -
+    input:
+      bytes: [ 0x20, 0x68, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, PRLAR_EL1"
+
+  -
+    input:
+      bytes: [ 0x20, 0x68, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, PRLAR_EL2"
+
+  -
+    input:
+      bytes: [ 0x80, 0x68, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, PRBAR1_EL1"
+
+  -
+    input:
+      bytes: [ 0x00, 0x69, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, PRBAR2_EL1"
+
+  -
+    input:
+      bytes: [ 0x80, 0x69, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, PRBAR3_EL1"
+
+  -
+    input:
+      bytes: [ 0x00, 0x6a, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, PRBAR4_EL1"
+
+  -
+    input:
+      bytes: [ 0x80, 0x6a, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, PRBAR5_EL1"
+
+  -
+    input:
+      bytes: [ 0x00, 0x6b, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, PRBAR6_EL1"
+
+  -
+    input:
+      bytes: [ 0x80, 0x6b, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, PRBAR7_EL1"
+
+  -
+    input:
+      bytes: [ 0x00, 0x6c, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, PRBAR8_EL1"
+
+  -
+    input:
+      bytes: [ 0x80, 0x6c, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, PRBAR9_EL1"
+
+  -
+    input:
+      bytes: [ 0x00, 0x6d, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, PRBAR10_EL1"
+
+  -
+    input:
+      bytes: [ 0x80, 0x6d, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, PRBAR11_EL1"
+
+  -
+    input:
+      bytes: [ 0x00, 0x6e, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, PRBAR12_EL1"
+
+  -
+    input:
+      bytes: [ 0x80, 0x6e, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, PRBAR13_EL1"
+
+  -
+    input:
+      bytes: [ 0x00, 0x6f, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, PRBAR14_EL1"
+
+  -
+    input:
+      bytes: [ 0x80, 0x6f, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, PRBAR15_EL1"
+
+  -
+    input:
+      bytes: [ 0xa0, 0x68, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, PRLAR1_EL1"
+
+  -
+    input:
+      bytes: [ 0x20, 0x69, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, PRLAR2_EL1"
+
+  -
+    input:
+      bytes: [ 0xa0, 0x69, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, PRLAR3_EL1"
+
+  -
+    input:
+      bytes: [ 0x20, 0x6a, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, PRLAR4_EL1"
+
+  -
+    input:
+      bytes: [ 0xa0, 0x6a, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, PRLAR5_EL1"
+
+  -
+    input:
+      bytes: [ 0x20, 0x6b, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, PRLAR6_EL1"
+
+  -
+    input:
+      bytes: [ 0xa0, 0x6b, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, PRLAR7_EL1"
+
+  -
+    input:
+      bytes: [ 0x20, 0x6c, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, PRLAR8_EL1"
+
+  -
+    input:
+      bytes: [ 0xa0, 0x6c, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, PRLAR9_EL1"
+
+  -
+    input:
+      bytes: [ 0x20, 0x6d, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, PRLAR10_EL1"
+
+  -
+    input:
+      bytes: [ 0xa0, 0x6d, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, PRLAR11_EL1"
+
+  -
+    input:
+      bytes: [ 0x20, 0x6e, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, PRLAR12_EL1"
+
+  -
+    input:
+      bytes: [ 0xa0, 0x6e, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, PRLAR13_EL1"
+
+  -
+    input:
+      bytes: [ 0x20, 0x6f, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, PRLAR14_EL1"
+
+  -
+    input:
+      bytes: [ 0xa0, 0x6f, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, PRLAR15_EL1"
+
+  -
+    input:
+      bytes: [ 0x80, 0x68, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, PRBAR1_EL2"
+
+  -
+    input:
+      bytes: [ 0x00, 0x69, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, PRBAR2_EL2"
+
+  -
+    input:
+      bytes: [ 0x80, 0x69, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, PRBAR3_EL2"
+
+  -
+    input:
+      bytes: [ 0x00, 0x6a, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, PRBAR4_EL2"
+
+  -
+    input:
+      bytes: [ 0x80, 0x6a, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, PRBAR5_EL2"
+
+  -
+    input:
+      bytes: [ 0x00, 0x6b, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, PRBAR6_EL2"
+
+  -
+    input:
+      bytes: [ 0x80, 0x6b, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, PRBAR7_EL2"
+
+  -
+    input:
+      bytes: [ 0x00, 0x6c, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, PRBAR8_EL2"
+
+  -
+    input:
+      bytes: [ 0x80, 0x6c, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, PRBAR9_EL2"
+
+  -
+    input:
+      bytes: [ 0x00, 0x6d, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, PRBAR10_EL2"
+
+  -
+    input:
+      bytes: [ 0x80, 0x6d, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, PRBAR11_EL2"
+
+  -
+    input:
+      bytes: [ 0x00, 0x6e, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, PRBAR12_EL2"
+
+  -
+    input:
+      bytes: [ 0x80, 0x6e, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, PRBAR13_EL2"
+
+  -
+    input:
+      bytes: [ 0x00, 0x6f, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, PRBAR14_EL2"
+
+  -
+    input:
+      bytes: [ 0x80, 0x6f, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, PRBAR15_EL2"
+
+  -
+    input:
+      bytes: [ 0xa0, 0x68, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, PRLAR1_EL2"
+
+  -
+    input:
+      bytes: [ 0x20, 0x69, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, PRLAR2_EL2"
+
+  -
+    input:
+      bytes: [ 0xa0, 0x69, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, PRLAR3_EL2"
+
+  -
+    input:
+      bytes: [ 0x20, 0x6a, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, PRLAR4_EL2"
+
+  -
+    input:
+      bytes: [ 0xa0, 0x6a, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, PRLAR5_EL2"
+
+  -
+    input:
+      bytes: [ 0x20, 0x6b, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, PRLAR6_EL2"
+
+  -
+    input:
+      bytes: [ 0xa0, 0x6b, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, PRLAR7_EL2"
+
+  -
+    input:
+      bytes: [ 0x20, 0x6c, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, PRLAR8_EL2"
+
+  -
+    input:
+      bytes: [ 0xa0, 0x6c, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, PRLAR9_EL2"
+
+  -
+    input:
+      bytes: [ 0x20, 0x6d, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, PRLAR10_EL2"
+
+  -
+    input:
+      bytes: [ 0xa0, 0x6d, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, PRLAR11_EL2"
+
+  -
+    input:
+      bytes: [ 0x20, 0x6e, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, PRLAR12_EL2"
+
+  -
+    input:
+      bytes: [ 0xa0, 0x6e, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, PRLAR13_EL2"
+
+  -
+    input:
+      bytes: [ 0x20, 0x6f, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, PRLAR14_EL2"
+
+  -
+    input:
+      bytes: [ 0xa0, 0x6f, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, PRLAR15_EL2"
+
+  -
+    input:
+      bytes: [ 0x1e, 0x20, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x30, TTBR0_EL2"
+
+  -
+    input:
+      bytes: [ 0x9e, 0x00, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x30, MPUIR_EL1"
+
+  -
+    input:
+      bytes: [ 0x9e, 0x00, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x30, MPUIR_EL2"
+
+  -
+    input:
+      bytes: [ 0x3e, 0x61, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x30, PRENR_EL1"
+
+  -
+    input:
+      bytes: [ 0x3e, 0x61, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x30, PRENR_EL2"
+
+  -
+    input:
+      bytes: [ 0x3e, 0x62, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x30, PRSELR_EL1"
+
+  -
+    input:
+      bytes: [ 0x3e, 0x62, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x30, PRSELR_EL2"
+
+  -
+    input:
+      bytes: [ 0x1e, 0x68, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x30, PRBAR_EL1"
+
+  -
+    input:
+      bytes: [ 0x1e, 0x68, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x30, PRBAR_EL2"
+
+  -
+    input:
+      bytes: [ 0x3e, 0x68, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x30, PRLAR_EL1"
+
+  -
+    input:
+      bytes: [ 0x3e, 0x68, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x30, PRLAR_EL2"
+
+  -
+    input:
+      bytes: [ 0x9e, 0x68, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x30, PRBAR1_EL1"
+
+  -
+    input:
+      bytes: [ 0x1e, 0x69, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x30, PRBAR2_EL1"
+
+  -
+    input:
+      bytes: [ 0x9e, 0x69, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x30, PRBAR3_EL1"
+
+  -
+    input:
+      bytes: [ 0x1e, 0x6a, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x30, PRBAR4_EL1"
+
+  -
+    input:
+      bytes: [ 0x9e, 0x6a, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x30, PRBAR5_EL1"
+
+  -
+    input:
+      bytes: [ 0x1e, 0x6b, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x30, PRBAR6_EL1"
+
+  -
+    input:
+      bytes: [ 0x9e, 0x6b, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x30, PRBAR7_EL1"
+
+  -
+    input:
+      bytes: [ 0x1e, 0x6c, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x30, PRBAR8_EL1"
+
+  -
+    input:
+      bytes: [ 0x9e, 0x6c, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x30, PRBAR9_EL1"
+
+  -
+    input:
+      bytes: [ 0x1e, 0x6d, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x30, PRBAR10_EL1"
+
+  -
+    input:
+      bytes: [ 0x9e, 0x6d, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x30, PRBAR11_EL1"
+
+  -
+    input:
+      bytes: [ 0x1e, 0x6e, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x30, PRBAR12_EL1"
+
+  -
+    input:
+      bytes: [ 0x9e, 0x6e, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x30, PRBAR13_EL1"
+
+  -
+    input:
+      bytes: [ 0x1e, 0x6f, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x30, PRBAR14_EL1"
+
+  -
+    input:
+      bytes: [ 0x9e, 0x6f, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x30, PRBAR15_EL1"
+
+  -
+    input:
+      bytes: [ 0xbe, 0x68, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x30, PRLAR1_EL1"
+
+  -
+    input:
+      bytes: [ 0x3e, 0x69, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x30, PRLAR2_EL1"
+
+  -
+    input:
+      bytes: [ 0xbe, 0x69, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x30, PRLAR3_EL1"
+
+  -
+    input:
+      bytes: [ 0x3e, 0x6a, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x30, PRLAR4_EL1"
+
+  -
+    input:
+      bytes: [ 0xbe, 0x6a, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x30, PRLAR5_EL1"
+
+  -
+    input:
+      bytes: [ 0x3e, 0x6b, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x30, PRLAR6_EL1"
+
+  -
+    input:
+      bytes: [ 0xbe, 0x6b, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x30, PRLAR7_EL1"
+
+  -
+    input:
+      bytes: [ 0x3e, 0x6c, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x30, PRLAR8_EL1"
+
+  -
+    input:
+      bytes: [ 0xbe, 0x6c, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x30, PRLAR9_EL1"
+
+  -
+    input:
+      bytes: [ 0x3e, 0x6d, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x30, PRLAR10_EL1"
+
+  -
+    input:
+      bytes: [ 0xbe, 0x6d, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x30, PRLAR11_EL1"
+
+  -
+    input:
+      bytes: [ 0x3e, 0x6e, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x30, PRLAR12_EL1"
+
+  -
+    input:
+      bytes: [ 0xbe, 0x6e, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x30, PRLAR13_EL1"
+
+  -
+    input:
+      bytes: [ 0x3e, 0x6f, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x30, PRLAR14_EL1"
+
+  -
+    input:
+      bytes: [ 0xbe, 0x6f, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x30, PRLAR15_EL1"
+
+  -
+    input:
+      bytes: [ 0x9e, 0x68, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x30, PRBAR1_EL2"
+
+  -
+    input:
+      bytes: [ 0x1e, 0x69, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x30, PRBAR2_EL2"
+
+  -
+    input:
+      bytes: [ 0x9e, 0x69, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x30, PRBAR3_EL2"
+
+  -
+    input:
+      bytes: [ 0x1e, 0x6a, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x30, PRBAR4_EL2"
+
+  -
+    input:
+      bytes: [ 0x9e, 0x6a, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x30, PRBAR5_EL2"
+
+  -
+    input:
+      bytes: [ 0x1e, 0x6b, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x30, PRBAR6_EL2"
+
+  -
+    input:
+      bytes: [ 0x9e, 0x6b, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x30, PRBAR7_EL2"
+
+  -
+    input:
+      bytes: [ 0x1e, 0x6c, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x30, PRBAR8_EL2"
+
+  -
+    input:
+      bytes: [ 0x9e, 0x6c, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x30, PRBAR9_EL2"
+
+  -
+    input:
+      bytes: [ 0x1e, 0x6d, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x30, PRBAR10_EL2"
+
+  -
+    input:
+      bytes: [ 0x9e, 0x6d, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x30, PRBAR11_EL2"
+
+  -
+    input:
+      bytes: [ 0x1e, 0x6e, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x30, PRBAR12_EL2"
+
+  -
+    input:
+      bytes: [ 0x9e, 0x6e, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x30, PRBAR13_EL2"
+
+  -
+    input:
+      bytes: [ 0x1e, 0x6f, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x30, PRBAR14_EL2"
+
+  -
+    input:
+      bytes: [ 0x9e, 0x6f, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x30, PRBAR15_EL2"
+
+  -
+    input:
+      bytes: [ 0xbe, 0x68, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x30, PRLAR1_EL2"
+
+  -
+    input:
+      bytes: [ 0x3e, 0x69, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x30, PRLAR2_EL2"
+
+  -
+    input:
+      bytes: [ 0xbe, 0x69, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x30, PRLAR3_EL2"
+
+  -
+    input:
+      bytes: [ 0x3e, 0x6a, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x30, PRLAR4_EL2"
+
+  -
+    input:
+      bytes: [ 0xbe, 0x6a, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x30, PRLAR5_EL2"
+
+  -
+    input:
+      bytes: [ 0x3e, 0x6b, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x30, PRLAR6_EL2"
+
+  -
+    input:
+      bytes: [ 0xbe, 0x6b, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x30, PRLAR7_EL2"
+
+  -
+    input:
+      bytes: [ 0x3e, 0x6c, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x30, PRLAR8_EL2"
+
+  -
+    input:
+      bytes: [ 0xbe, 0x6c, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x30, PRLAR9_EL2"
+
+  -
+    input:
+      bytes: [ 0x3e, 0x6d, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x30, PRLAR10_EL2"
+
+  -
+    input:
+      bytes: [ 0xbe, 0x6d, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x30, PRLAR11_EL2"
+
+  -
+    input:
+      bytes: [ 0x3e, 0x6e, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x30, PRLAR12_EL2"
+
+  -
+    input:
+      bytes: [ 0xbe, 0x6e, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x30, PRLAR13_EL2"
+
+  -
+    input:
+      bytes: [ 0x3e, 0x6f, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x30, PRLAR14_EL2"
+
+  -
+    input:
+      bytes: [ 0xbe, 0x6f, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x30, PRLAR15_EL2"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TTBR0_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x80, 0x00, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr MPUIR_EL1, x0"
+
+  -
+    input:
+      bytes: [ 0x80, 0x00, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr MPUIR_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x20, 0x61, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRENR_EL1, x0"
+
+  -
+    input:
+      bytes: [ 0x20, 0x61, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRENR_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x20, 0x62, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRSELR_EL1, x0"
+
+  -
+    input:
+      bytes: [ 0x20, 0x62, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRSELR_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x68, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRBAR_EL1, x0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x68, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRBAR_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x20, 0x68, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRLAR_EL1, x0"
+
+  -
+    input:
+      bytes: [ 0x20, 0x68, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRLAR_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x80, 0x68, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRBAR1_EL1, x0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x69, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRBAR2_EL1, x0"
+
+  -
+    input:
+      bytes: [ 0x80, 0x69, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRBAR3_EL1, x0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x6a, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRBAR4_EL1, x0"
+
+  -
+    input:
+      bytes: [ 0x80, 0x6a, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRBAR5_EL1, x0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x6b, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRBAR6_EL1, x0"
+
+  -
+    input:
+      bytes: [ 0x80, 0x6b, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRBAR7_EL1, x0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x6c, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRBAR8_EL1, x0"
+
+  -
+    input:
+      bytes: [ 0x80, 0x6c, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRBAR9_EL1, x0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x6d, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRBAR10_EL1, x0"
+
+  -
+    input:
+      bytes: [ 0x80, 0x6d, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRBAR11_EL1, x0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x6e, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRBAR12_EL1, x0"
+
+  -
+    input:
+      bytes: [ 0x80, 0x6e, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRBAR13_EL1, x0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x6f, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRBAR14_EL1, x0"
+
+  -
+    input:
+      bytes: [ 0x80, 0x6f, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRBAR15_EL1, x0"
+
+  -
+    input:
+      bytes: [ 0xa0, 0x68, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRLAR1_EL1, x0"
+
+  -
+    input:
+      bytes: [ 0x20, 0x69, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRLAR2_EL1, x0"
+
+  -
+    input:
+      bytes: [ 0xa0, 0x69, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRLAR3_EL1, x0"
+
+  -
+    input:
+      bytes: [ 0x20, 0x6a, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRLAR4_EL1, x0"
+
+  -
+    input:
+      bytes: [ 0xa0, 0x6a, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRLAR5_EL1, x0"
+
+  -
+    input:
+      bytes: [ 0x20, 0x6b, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRLAR6_EL1, x0"
+
+  -
+    input:
+      bytes: [ 0xa0, 0x6b, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRLAR7_EL1, x0"
+
+  -
+    input:
+      bytes: [ 0x20, 0x6c, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRLAR8_EL1, x0"
+
+  -
+    input:
+      bytes: [ 0xa0, 0x6c, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRLAR9_EL1, x0"
+
+  -
+    input:
+      bytes: [ 0x20, 0x6d, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRLAR10_EL1, x0"
+
+  -
+    input:
+      bytes: [ 0xa0, 0x6d, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRLAR11_EL1, x0"
+
+  -
+    input:
+      bytes: [ 0x20, 0x6e, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRLAR12_EL1, x0"
+
+  -
+    input:
+      bytes: [ 0xa0, 0x6e, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRLAR13_EL1, x0"
+
+  -
+    input:
+      bytes: [ 0x20, 0x6f, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRLAR14_EL1, x0"
+
+  -
+    input:
+      bytes: [ 0xa0, 0x6f, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRLAR15_EL1, x0"
+
+  -
+    input:
+      bytes: [ 0x80, 0x68, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRBAR1_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x69, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRBAR2_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x80, 0x69, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRBAR3_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x6a, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRBAR4_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x80, 0x6a, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRBAR5_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x6b, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRBAR6_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x80, 0x6b, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRBAR7_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x6c, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRBAR8_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x80, 0x6c, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRBAR9_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x6d, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRBAR10_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x80, 0x6d, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRBAR11_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x6e, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRBAR12_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x80, 0x6e, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRBAR13_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x6f, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRBAR14_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x80, 0x6f, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRBAR15_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0xa0, 0x68, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRLAR1_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x20, 0x69, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRLAR2_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0xa0, 0x69, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRLAR3_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x20, 0x6a, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRLAR4_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0xa0, 0x6a, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRLAR5_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x20, 0x6b, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRLAR6_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0xa0, 0x6b, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRLAR7_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x20, 0x6c, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRLAR8_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0xa0, 0x6c, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRLAR9_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x20, 0x6d, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRLAR10_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0xa0, 0x6d, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRLAR11_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x20, 0x6e, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRLAR12_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0xa0, 0x6e, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRLAR13_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x20, 0x6f, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRLAR14_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0xa0, 0x6f, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRLAR15_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x1e, 0x20, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TTBR0_EL2, x30"
+
+  -
+    input:
+      bytes: [ 0x9e, 0x00, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr MPUIR_EL1, x30"
+
+  -
+    input:
+      bytes: [ 0x9e, 0x00, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr MPUIR_EL2, x30"
+
+  -
+    input:
+      bytes: [ 0x3e, 0x61, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRENR_EL1, x30"
+
+  -
+    input:
+      bytes: [ 0x3e, 0x61, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRENR_EL2, x30"
+
+  -
+    input:
+      bytes: [ 0x3e, 0x62, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRSELR_EL1, x30"
+
+  -
+    input:
+      bytes: [ 0x3e, 0x62, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRSELR_EL2, x30"
+
+  -
+    input:
+      bytes: [ 0x1e, 0x68, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRBAR_EL1, x30"
+
+  -
+    input:
+      bytes: [ 0x1e, 0x68, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRBAR_EL2, x30"
+
+  -
+    input:
+      bytes: [ 0x3e, 0x68, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRLAR_EL1, x30"
+
+  -
+    input:
+      bytes: [ 0x3e, 0x68, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRLAR_EL2, x30"
+
+  -
+    input:
+      bytes: [ 0x9e, 0x68, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRBAR1_EL1, x30"
+
+  -
+    input:
+      bytes: [ 0x1e, 0x69, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRBAR2_EL1, x30"
+
+  -
+    input:
+      bytes: [ 0x9e, 0x69, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRBAR3_EL1, x30"
+
+  -
+    input:
+      bytes: [ 0x1e, 0x6a, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRBAR4_EL1, x30"
+
+  -
+    input:
+      bytes: [ 0x9e, 0x6a, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRBAR5_EL1, x30"
+
+  -
+    input:
+      bytes: [ 0x1e, 0x6b, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRBAR6_EL1, x30"
+
+  -
+    input:
+      bytes: [ 0x9e, 0x6b, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRBAR7_EL1, x30"
+
+  -
+    input:
+      bytes: [ 0x1e, 0x6c, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRBAR8_EL1, x30"
+
+  -
+    input:
+      bytes: [ 0x9e, 0x6c, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRBAR9_EL1, x30"
+
+  -
+    input:
+      bytes: [ 0x1e, 0x6d, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRBAR10_EL1, x30"
+
+  -
+    input:
+      bytes: [ 0x9e, 0x6d, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRBAR11_EL1, x30"
+
+  -
+    input:
+      bytes: [ 0x1e, 0x6e, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRBAR12_EL1, x30"
+
+  -
+    input:
+      bytes: [ 0x9e, 0x6e, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRBAR13_EL1, x30"
+
+  -
+    input:
+      bytes: [ 0x1e, 0x6f, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRBAR14_EL1, x30"
+
+  -
+    input:
+      bytes: [ 0x9e, 0x6f, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRBAR15_EL1, x30"
+
+  -
+    input:
+      bytes: [ 0xbe, 0x68, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRLAR1_EL1, x30"
+
+  -
+    input:
+      bytes: [ 0x3e, 0x69, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRLAR2_EL1, x30"
+
+  -
+    input:
+      bytes: [ 0xbe, 0x69, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRLAR3_EL1, x30"
+
+  -
+    input:
+      bytes: [ 0x3e, 0x6a, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRLAR4_EL1, x30"
+
+  -
+    input:
+      bytes: [ 0xbe, 0x6a, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRLAR5_EL1, x30"
+
+  -
+    input:
+      bytes: [ 0x3e, 0x6b, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRLAR6_EL1, x30"
+
+  -
+    input:
+      bytes: [ 0xbe, 0x6b, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRLAR7_EL1, x30"
+
+  -
+    input:
+      bytes: [ 0x3e, 0x6c, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRLAR8_EL1, x30"
+
+  -
+    input:
+      bytes: [ 0xbe, 0x6c, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRLAR9_EL1, x30"
+
+  -
+    input:
+      bytes: [ 0x3e, 0x6d, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRLAR10_EL1, x30"
+
+  -
+    input:
+      bytes: [ 0xbe, 0x6d, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRLAR11_EL1, x30"
+
+  -
+    input:
+      bytes: [ 0x3e, 0x6e, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRLAR12_EL1, x30"
+
+  -
+    input:
+      bytes: [ 0xbe, 0x6e, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRLAR13_EL1, x30"
+
+  -
+    input:
+      bytes: [ 0x3e, 0x6f, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRLAR14_EL1, x30"
+
+  -
+    input:
+      bytes: [ 0xbe, 0x6f, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRLAR15_EL1, x30"
+
+  -
+    input:
+      bytes: [ 0x9e, 0x68, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRBAR1_EL2, x30"
+
+  -
+    input:
+      bytes: [ 0x1e, 0x69, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRBAR2_EL2, x30"
+
+  -
+    input:
+      bytes: [ 0x9e, 0x69, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRBAR3_EL2, x30"
+
+  -
+    input:
+      bytes: [ 0x1e, 0x6a, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRBAR4_EL2, x30"
+
+  -
+    input:
+      bytes: [ 0x9e, 0x6a, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRBAR5_EL2, x30"
+
+  -
+    input:
+      bytes: [ 0x1e, 0x6b, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRBAR6_EL2, x30"
+
+  -
+    input:
+      bytes: [ 0x9e, 0x6b, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRBAR7_EL2, x30"
+
+  -
+    input:
+      bytes: [ 0x1e, 0x6c, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRBAR8_EL2, x30"
+
+  -
+    input:
+      bytes: [ 0x9e, 0x6c, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRBAR9_EL2, x30"
+
+  -
+    input:
+      bytes: [ 0x1e, 0x6d, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRBAR10_EL2, x30"
+
+  -
+    input:
+      bytes: [ 0x9e, 0x6d, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRBAR11_EL2, x30"
+
+  -
+    input:
+      bytes: [ 0x1e, 0x6e, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRBAR12_EL2, x30"
+
+  -
+    input:
+      bytes: [ 0x9e, 0x6e, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRBAR13_EL2, x30"
+
+  -
+    input:
+      bytes: [ 0x1e, 0x6f, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRBAR14_EL2, x30"
+
+  -
+    input:
+      bytes: [ 0x9e, 0x6f, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRBAR15_EL2, x30"
+
+  -
+    input:
+      bytes: [ 0xbe, 0x68, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRLAR1_EL2, x30"
+
+  -
+    input:
+      bytes: [ 0x3e, 0x69, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRLAR2_EL2, x30"
+
+  -
+    input:
+      bytes: [ 0xbe, 0x69, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRLAR3_EL2, x30"
+
+  -
+    input:
+      bytes: [ 0x3e, 0x6a, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRLAR4_EL2, x30"
+
+  -
+    input:
+      bytes: [ 0xbe, 0x6a, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRLAR5_EL2, x30"
+
+  -
+    input:
+      bytes: [ 0x3e, 0x6b, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRLAR6_EL2, x30"
+
+  -
+    input:
+      bytes: [ 0xbe, 0x6b, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRLAR7_EL2, x30"
+
+  -
+    input:
+      bytes: [ 0x3e, 0x6c, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRLAR8_EL2, x30"
+
+  -
+    input:
+      bytes: [ 0xbe, 0x6c, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRLAR9_EL2, x30"
+
+  -
+    input:
+      bytes: [ 0x3e, 0x6d, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRLAR10_EL2, x30"
+
+  -
+    input:
+      bytes: [ 0xbe, 0x6d, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRLAR11_EL2, x30"
+
+  -
+    input:
+      bytes: [ 0x3e, 0x6e, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRLAR12_EL2, x30"
+
+  -
+    input:
+      bytes: [ 0xbe, 0x6e, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRLAR13_EL2, x30"
+
+  -
+    input:
+      bytes: [ 0x3e, 0x6f, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRLAR14_EL2, x30"
+
+  -
+    input:
+      bytes: [ 0xbe, 0x6f, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PRLAR15_EL2, x30"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd0, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr CONTEXTIDR_EL2, x0"
diff --git a/tests/MC/AArch64/armv8r-unsupported-inst.s.yaml b/tests/MC/AArch64/armv8r-unsupported-inst.s.yaml
new file mode 100644
index 000000000..4e7b7357e
--- /dev/null
+++ b/tests/MC/AArch64/armv8r-unsupported-inst.s.yaml
@@ -0,0 +1,60 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x03, 0x00, 0xa0, 0xd4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "el3" ]
+    expected:
+      insns:
+        -
+          asm_text: "dcps3"
+
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0xa0, 0xd4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "el3" ]
+    expected:
+      insns:
+        -
+          asm_text: "dcps3 #0x4"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0xd4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "el3" ]
+    expected:
+      insns:
+        -
+          asm_text: "smc #0x7"
+
+  -
+    input:
+      bytes: [ 0x03, 0x00, 0xa0, 0xd4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8a" ]
+    expected:
+      insns:
+        -
+          asm_text: "dcps3"
+
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0xa0, 0xd4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8a" ]
+    expected:
+      insns:
+        -
+          asm_text: "dcps3 #0x4"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0xd4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8a" ]
+    expected:
+      insns:
+        -
+          asm_text: "smc #0x7"
diff --git a/tests/MC/AArch64/armv8r-unsupported-sysreg.s.yaml b/tests/MC/AArch64/armv8r-unsupported-sysreg.s.yaml
new file mode 100644
index 000000000..f4b126a8f
--- /dev/null
+++ b/tests/MC/AArch64/armv8r-unsupported-sysreg.s.yaml
@@ -0,0 +1,60 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x03, 0x20, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TTBR0_EL2, x3"
+
+  -
+    input:
+      bytes: [ 0x03, 0x20, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8a" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, TTBR0_EL2"
+
+  -
+    input:
+      bytes: [ 0x03, 0x21, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr VTTBR_EL2, x3"
+
+  -
+    input:
+      bytes: [ 0x03, 0x21, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8a" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, VTTBR_EL2"
+
+  -
+    input:
+      bytes: [ 0x03, 0x26, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr VSTTBR_EL2, x3"
+
+  -
+    input:
+      bytes: [ 0x03, 0x26, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8a" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, VSTTBR_EL2"
diff --git a/tests/MC/AArch64/armv9-sysreg128.txt.yaml b/tests/MC/AArch64/armv9-sysreg128.txt.yaml
new file mode 100644
index 000000000..675717a82
--- /dev/null
+++ b/tests/MC/AArch64/armv9-sysreg128.txt.yaml
@@ -0,0 +1,1320 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x78, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrrs x0, x1, TTBR0_EL1"
+
+  -
+    input:
+      bytes: [ 0x20, 0x20, 0x78, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrrs x0, x1, TTBR1_EL1"
+
+  -
+    input:
+      bytes: [ 0x00, 0x74, 0x78, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrrs x0, x1, PAR_EL1"
+
+  -
+    input:
+      bytes: [ 0x60, 0xd0, 0x78, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrrs x0, x1, RCWSMASK_EL1"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xd0, 0x78, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrrs x0, x1, RCWMASK_EL1"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x7c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrrs x0, x1, TTBR0_EL2"
+
+  -
+    input:
+      bytes: [ 0x20, 0x20, 0x7c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrrs x0, x1, TTBR1_EL2"
+
+  -
+    input:
+      bytes: [ 0x00, 0x21, 0x7c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrrs x0, x1, VTTBR_EL2"
+
+  -
+    input:
+      bytes: [ 0x00, 0x21, 0x7c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrrs x0, x1, VTTBR_EL2"
+
+  -
+    input:
+      bytes: [ 0x02, 0x21, 0x7c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrrs x2, x3, VTTBR_EL2"
+
+  -
+    input:
+      bytes: [ 0x04, 0x21, 0x7c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrrs x4, x5, VTTBR_EL2"
+
+  -
+    input:
+      bytes: [ 0x06, 0x21, 0x7c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrrs x6, x7, VTTBR_EL2"
+
+  -
+    input:
+      bytes: [ 0x08, 0x21, 0x7c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrrs x8, x9, VTTBR_EL2"
+
+  -
+    input:
+      bytes: [ 0x0a, 0x21, 0x7c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrrs x10, x11, VTTBR_EL2"
+
+  -
+    input:
+      bytes: [ 0x0c, 0x21, 0x7c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrrs x12, x13, VTTBR_EL2"
+
+  -
+    input:
+      bytes: [ 0x0e, 0x21, 0x7c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrrs x14, x15, VTTBR_EL2"
+
+  -
+    input:
+      bytes: [ 0x10, 0x21, 0x7c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrrs x16, x17, VTTBR_EL2"
+
+  -
+    input:
+      bytes: [ 0x12, 0x21, 0x7c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrrs x18, x19, VTTBR_EL2"
+
+  -
+    input:
+      bytes: [ 0x14, 0x21, 0x7c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrrs x20, x21, VTTBR_EL2"
+
+  -
+    input:
+      bytes: [ 0x16, 0x21, 0x7c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrrs x22, x23, VTTBR_EL2"
+
+  -
+    input:
+      bytes: [ 0x18, 0x21, 0x7c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrrs x24, x25, VTTBR_EL2"
+
+  -
+    input:
+      bytes: [ 0x1a, 0x21, 0x7c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrrs x26, x27, VTTBR_EL2"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x58, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ]
+    expected:
+      insns:
+        -
+          asm_text: "msrr TTBR0_EL1, x0, x1"
+
+  -
+    input:
+      bytes: [ 0x20, 0x20, 0x58, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ]
+    expected:
+      insns:
+        -
+          asm_text: "msrr TTBR1_EL1, x0, x1"
+
+  -
+    input:
+      bytes: [ 0x00, 0x74, 0x58, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ]
+    expected:
+      insns:
+        -
+          asm_text: "msrr PAR_EL1, x0, x1"
+
+  -
+    input:
+      bytes: [ 0x60, 0xd0, 0x58, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ]
+    expected:
+      insns:
+        -
+          asm_text: "msrr RCWSMASK_EL1, x0, x1"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xd0, 0x58, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ]
+    expected:
+      insns:
+        -
+          asm_text: "msrr RCWMASK_EL1, x0, x1"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x5c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ]
+    expected:
+      insns:
+        -
+          asm_text: "msrr TTBR0_EL2, x0, x1"
+
+  -
+    input:
+      bytes: [ 0x20, 0x20, 0x5c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ]
+    expected:
+      insns:
+        -
+          asm_text: "msrr TTBR1_EL2, x0, x1"
+
+  -
+    input:
+      bytes: [ 0x00, 0x21, 0x5c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ]
+    expected:
+      insns:
+        -
+          asm_text: "msrr VTTBR_EL2, x0, x1"
+
+  -
+    input:
+      bytes: [ 0x00, 0x21, 0x5c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ]
+    expected:
+      insns:
+        -
+          asm_text: "msrr VTTBR_EL2, x0, x1"
+
+  -
+    input:
+      bytes: [ 0x02, 0x21, 0x5c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ]
+    expected:
+      insns:
+        -
+          asm_text: "msrr VTTBR_EL2, x2, x3"
+
+  -
+    input:
+      bytes: [ 0x04, 0x21, 0x5c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ]
+    expected:
+      insns:
+        -
+          asm_text: "msrr VTTBR_EL2, x4, x5"
+
+  -
+    input:
+      bytes: [ 0x06, 0x21, 0x5c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ]
+    expected:
+      insns:
+        -
+          asm_text: "msrr VTTBR_EL2, x6, x7"
+
+  -
+    input:
+      bytes: [ 0x08, 0x21, 0x5c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ]
+    expected:
+      insns:
+        -
+          asm_text: "msrr VTTBR_EL2, x8, x9"
+
+  -
+    input:
+      bytes: [ 0x0a, 0x21, 0x5c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ]
+    expected:
+      insns:
+        -
+          asm_text: "msrr VTTBR_EL2, x10, x11"
+
+  -
+    input:
+      bytes: [ 0x0c, 0x21, 0x5c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ]
+    expected:
+      insns:
+        -
+          asm_text: "msrr VTTBR_EL2, x12, x13"
+
+  -
+    input:
+      bytes: [ 0x0e, 0x21, 0x5c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ]
+    expected:
+      insns:
+        -
+          asm_text: "msrr VTTBR_EL2, x14, x15"
+
+  -
+    input:
+      bytes: [ 0x10, 0x21, 0x5c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ]
+    expected:
+      insns:
+        -
+          asm_text: "msrr VTTBR_EL2, x16, x17"
+
+  -
+    input:
+      bytes: [ 0x12, 0x21, 0x5c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ]
+    expected:
+      insns:
+        -
+          asm_text: "msrr VTTBR_EL2, x18, x19"
+
+  -
+    input:
+      bytes: [ 0x14, 0x21, 0x5c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ]
+    expected:
+      insns:
+        -
+          asm_text: "msrr VTTBR_EL2, x20, x21"
+
+  -
+    input:
+      bytes: [ 0x16, 0x21, 0x5c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ]
+    expected:
+      insns:
+        -
+          asm_text: "msrr VTTBR_EL2, x22, x23"
+
+  -
+    input:
+      bytes: [ 0x18, 0x21, 0x5c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ]
+    expected:
+      insns:
+        -
+          asm_text: "msrr VTTBR_EL2, x24, x25"
+
+  -
+    input:
+      bytes: [ 0x1a, 0x21, 0x5c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128" ]
+    expected:
+      insns:
+        -
+          asm_text: "msrr VTTBR_EL2, x26, x27"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x78, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrrs x0, x1, TTBR0_EL1"
+
+  -
+    input:
+      bytes: [ 0x20, 0x20, 0x78, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrrs x0, x1, TTBR1_EL1"
+
+  -
+    input:
+      bytes: [ 0x00, 0x74, 0x78, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrrs x0, x1, PAR_EL1"
+
+  -
+    input:
+      bytes: [ 0x60, 0xd0, 0x78, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrrs x0, x1, RCWSMASK_EL1"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xd0, 0x78, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrrs x0, x1, RCWMASK_EL1"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x7c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrrs x0, x1, TTBR0_EL2"
+
+  -
+    input:
+      bytes: [ 0x20, 0x20, 0x7c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrrs x0, x1, TTBR1_EL2"
+
+  -
+    input:
+      bytes: [ 0x00, 0x21, 0x7c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrrs x0, x1, VTTBR_EL2"
+
+  -
+    input:
+      bytes: [ 0x00, 0x21, 0x7c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrrs x0, x1, VTTBR_EL2"
+
+  -
+    input:
+      bytes: [ 0x02, 0x21, 0x7c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrrs x2, x3, VTTBR_EL2"
+
+  -
+    input:
+      bytes: [ 0x04, 0x21, 0x7c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrrs x4, x5, VTTBR_EL2"
+
+  -
+    input:
+      bytes: [ 0x06, 0x21, 0x7c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrrs x6, x7, VTTBR_EL2"
+
+  -
+    input:
+      bytes: [ 0x08, 0x21, 0x7c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrrs x8, x9, VTTBR_EL2"
+
+  -
+    input:
+      bytes: [ 0x0a, 0x21, 0x7c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrrs x10, x11, VTTBR_EL2"
+
+  -
+    input:
+      bytes: [ 0x0c, 0x21, 0x7c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrrs x12, x13, VTTBR_EL2"
+
+  -
+    input:
+      bytes: [ 0x0e, 0x21, 0x7c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrrs x14, x15, VTTBR_EL2"
+
+  -
+    input:
+      bytes: [ 0x10, 0x21, 0x7c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrrs x16, x17, VTTBR_EL2"
+
+  -
+    input:
+      bytes: [ 0x12, 0x21, 0x7c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrrs x18, x19, VTTBR_EL2"
+
+  -
+    input:
+      bytes: [ 0x14, 0x21, 0x7c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrrs x20, x21, VTTBR_EL2"
+
+  -
+    input:
+      bytes: [ 0x16, 0x21, 0x7c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrrs x22, x23, VTTBR_EL2"
+
+  -
+    input:
+      bytes: [ 0x18, 0x21, 0x7c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrrs x24, x25, VTTBR_EL2"
+
+  -
+    input:
+      bytes: [ 0x1a, 0x21, 0x7c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrrs x26, x27, VTTBR_EL2"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x58, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ]
+    expected:
+      insns:
+        -
+          asm_text: "msrr TTBR0_EL1, x0, x1"
+
+  -
+    input:
+      bytes: [ 0x20, 0x20, 0x58, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ]
+    expected:
+      insns:
+        -
+          asm_text: "msrr TTBR1_EL1, x0, x1"
+
+  -
+    input:
+      bytes: [ 0x00, 0x74, 0x58, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ]
+    expected:
+      insns:
+        -
+          asm_text: "msrr PAR_EL1, x0, x1"
+
+  -
+    input:
+      bytes: [ 0x60, 0xd0, 0x58, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ]
+    expected:
+      insns:
+        -
+          asm_text: "msrr RCWSMASK_EL1, x0, x1"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xd0, 0x58, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ]
+    expected:
+      insns:
+        -
+          asm_text: "msrr RCWMASK_EL1, x0, x1"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x5c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ]
+    expected:
+      insns:
+        -
+          asm_text: "msrr TTBR0_EL2, x0, x1"
+
+  -
+    input:
+      bytes: [ 0x20, 0x20, 0x5c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ]
+    expected:
+      insns:
+        -
+          asm_text: "msrr TTBR1_EL2, x0, x1"
+
+  -
+    input:
+      bytes: [ 0x00, 0x21, 0x5c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ]
+    expected:
+      insns:
+        -
+          asm_text: "msrr VTTBR_EL2, x0, x1"
+
+  -
+    input:
+      bytes: [ 0x00, 0x21, 0x5c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ]
+    expected:
+      insns:
+        -
+          asm_text: "msrr VTTBR_EL2, x0, x1"
+
+  -
+    input:
+      bytes: [ 0x02, 0x21, 0x5c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ]
+    expected:
+      insns:
+        -
+          asm_text: "msrr VTTBR_EL2, x2, x3"
+
+  -
+    input:
+      bytes: [ 0x04, 0x21, 0x5c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ]
+    expected:
+      insns:
+        -
+          asm_text: "msrr VTTBR_EL2, x4, x5"
+
+  -
+    input:
+      bytes: [ 0x06, 0x21, 0x5c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ]
+    expected:
+      insns:
+        -
+          asm_text: "msrr VTTBR_EL2, x6, x7"
+
+  -
+    input:
+      bytes: [ 0x08, 0x21, 0x5c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ]
+    expected:
+      insns:
+        -
+          asm_text: "msrr VTTBR_EL2, x8, x9"
+
+  -
+    input:
+      bytes: [ 0x0a, 0x21, 0x5c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ]
+    expected:
+      insns:
+        -
+          asm_text: "msrr VTTBR_EL2, x10, x11"
+
+  -
+    input:
+      bytes: [ 0x0c, 0x21, 0x5c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ]
+    expected:
+      insns:
+        -
+          asm_text: "msrr VTTBR_EL2, x12, x13"
+
+  -
+    input:
+      bytes: [ 0x0e, 0x21, 0x5c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ]
+    expected:
+      insns:
+        -
+          asm_text: "msrr VTTBR_EL2, x14, x15"
+
+  -
+    input:
+      bytes: [ 0x10, 0x21, 0x5c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ]
+    expected:
+      insns:
+        -
+          asm_text: "msrr VTTBR_EL2, x16, x17"
+
+  -
+    input:
+      bytes: [ 0x12, 0x21, 0x5c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ]
+    expected:
+      insns:
+        -
+          asm_text: "msrr VTTBR_EL2, x18, x19"
+
+  -
+    input:
+      bytes: [ 0x14, 0x21, 0x5c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ]
+    expected:
+      insns:
+        -
+          asm_text: "msrr VTTBR_EL2, x20, x21"
+
+  -
+    input:
+      bytes: [ 0x16, 0x21, 0x5c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ]
+    expected:
+      insns:
+        -
+          asm_text: "msrr VTTBR_EL2, x22, x23"
+
+  -
+    input:
+      bytes: [ 0x18, 0x21, 0x5c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ]
+    expected:
+      insns:
+        -
+          asm_text: "msrr VTTBR_EL2, x24, x25"
+
+  -
+    input:
+      bytes: [ 0x1a, 0x21, 0x5c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "d128", "+the", "+el2vmsa", "+vh" ]
+    expected:
+      insns:
+        -
+          asm_text: "msrr VTTBR_EL2, x26, x27"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x78, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrrs x0, x1, TTBR0_EL1"
+
+  -
+    input:
+      bytes: [ 0x20, 0x20, 0x78, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrrs x0, x1, TTBR1_EL1"
+
+  -
+    input:
+      bytes: [ 0x00, 0x74, 0x78, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrrs x0, x1, PAR_EL1"
+
+  -
+    input:
+      bytes: [ 0x60, 0xd0, 0x78, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrrs x0, x1, RCWSMASK_EL1"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xd0, 0x78, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrrs x0, x1, RCWMASK_EL1"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x7c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrrs x0, x1, TTBR0_EL2"
+
+  -
+    input:
+      bytes: [ 0x20, 0x20, 0x7c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrrs x0, x1, TTBR1_EL2"
+
+  -
+    input:
+      bytes: [ 0x00, 0x21, 0x7c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrrs x0, x1, VTTBR_EL2"
+
+  -
+    input:
+      bytes: [ 0x00, 0x21, 0x7c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrrs x0, x1, VTTBR_EL2"
+
+  -
+    input:
+      bytes: [ 0x02, 0x21, 0x7c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrrs x2, x3, VTTBR_EL2"
+
+  -
+    input:
+      bytes: [ 0x04, 0x21, 0x7c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrrs x4, x5, VTTBR_EL2"
+
+  -
+    input:
+      bytes: [ 0x06, 0x21, 0x7c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrrs x6, x7, VTTBR_EL2"
+
+  -
+    input:
+      bytes: [ 0x08, 0x21, 0x7c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrrs x8, x9, VTTBR_EL2"
+
+  -
+    input:
+      bytes: [ 0x0a, 0x21, 0x7c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrrs x10, x11, VTTBR_EL2"
+
+  -
+    input:
+      bytes: [ 0x0c, 0x21, 0x7c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrrs x12, x13, VTTBR_EL2"
+
+  -
+    input:
+      bytes: [ 0x0e, 0x21, 0x7c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrrs x14, x15, VTTBR_EL2"
+
+  -
+    input:
+      bytes: [ 0x10, 0x21, 0x7c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrrs x16, x17, VTTBR_EL2"
+
+  -
+    input:
+      bytes: [ 0x12, 0x21, 0x7c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrrs x18, x19, VTTBR_EL2"
+
+  -
+    input:
+      bytes: [ 0x14, 0x21, 0x7c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrrs x20, x21, VTTBR_EL2"
+
+  -
+    input:
+      bytes: [ 0x16, 0x21, 0x7c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrrs x22, x23, VTTBR_EL2"
+
+  -
+    input:
+      bytes: [ 0x18, 0x21, 0x7c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrrs x24, x25, VTTBR_EL2"
+
+  -
+    input:
+      bytes: [ 0x1a, 0x21, 0x7c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrrs x26, x27, VTTBR_EL2"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x58, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "msrr TTBR0_EL1, x0, x1"
+
+  -
+    input:
+      bytes: [ 0x20, 0x20, 0x58, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "msrr TTBR1_EL1, x0, x1"
+
+  -
+    input:
+      bytes: [ 0x00, 0x74, 0x58, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "msrr PAR_EL1, x0, x1"
+
+  -
+    input:
+      bytes: [ 0x60, 0xd0, 0x58, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "msrr RCWSMASK_EL1, x0, x1"
+
+  -
+    input:
+      bytes: [ 0xc0, 0xd0, 0x58, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "msrr RCWMASK_EL1, x0, x1"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x5c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "msrr TTBR0_EL2, x0, x1"
+
+  -
+    input:
+      bytes: [ 0x20, 0x20, 0x5c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "msrr TTBR1_EL2, x0, x1"
+
+  -
+    input:
+      bytes: [ 0x00, 0x21, 0x5c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "msrr VTTBR_EL2, x0, x1"
+
+  -
+    input:
+      bytes: [ 0x00, 0x21, 0x5c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "msrr VTTBR_EL2, x0, x1"
+
+  -
+    input:
+      bytes: [ 0x02, 0x21, 0x5c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "msrr VTTBR_EL2, x2, x3"
+
+  -
+    input:
+      bytes: [ 0x04, 0x21, 0x5c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "msrr VTTBR_EL2, x4, x5"
+
+  -
+    input:
+      bytes: [ 0x06, 0x21, 0x5c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "msrr VTTBR_EL2, x6, x7"
+
+  -
+    input:
+      bytes: [ 0x08, 0x21, 0x5c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "msrr VTTBR_EL2, x8, x9"
+
+  -
+    input:
+      bytes: [ 0x0a, 0x21, 0x5c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "msrr VTTBR_EL2, x10, x11"
+
+  -
+    input:
+      bytes: [ 0x0c, 0x21, 0x5c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "msrr VTTBR_EL2, x12, x13"
+
+  -
+    input:
+      bytes: [ 0x0e, 0x21, 0x5c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "msrr VTTBR_EL2, x14, x15"
+
+  -
+    input:
+      bytes: [ 0x10, 0x21, 0x5c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "msrr VTTBR_EL2, x16, x17"
+
+  -
+    input:
+      bytes: [ 0x12, 0x21, 0x5c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "msrr VTTBR_EL2, x18, x19"
+
+  -
+    input:
+      bytes: [ 0x14, 0x21, 0x5c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "msrr VTTBR_EL2, x20, x21"
+
+  -
+    input:
+      bytes: [ 0x16, 0x21, 0x5c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "msrr VTTBR_EL2, x22, x23"
+
+  -
+    input:
+      bytes: [ 0x18, 0x21, 0x5c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "msrr VTTBR_EL2, x24, x25"
+
+  -
+    input:
+      bytes: [ 0x1a, 0x21, 0x5c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "msrr VTTBR_EL2, x26, x27"
diff --git a/tests/MC/AArch64/armv9.4a-chk.s.yaml b/tests/MC/AArch64/armv9.4a-chk.s.yaml
new file mode 100644
index 000000000..afd02c2cd
--- /dev/null
+++ b/tests/MC/AArch64/armv9.4a-chk.s.yaml
@@ -0,0 +1,80 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x1f, 0x25, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "chk" ]
+    expected:
+      insns:
+        -
+          asm_text: "chkfeat x16"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x25, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "chk" ]
+    expected:
+      insns:
+        -
+          asm_text: "chkfeat x16"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x25, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.9a" ]
+    expected:
+      insns:
+        -
+          asm_text: "chkfeat x16"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x25, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8.9a" ]
+    expected:
+      insns:
+        -
+          asm_text: "chkfeat x16"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x25, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "chkfeat x16"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x25, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v9.4a" ]
+    expected:
+      insns:
+        -
+          asm_text: "chkfeat x16"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x25, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8a" ]
+    expected:
+      insns:
+        -
+          asm_text: "chkfeat x16"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x25, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "v8a" ]
+    expected:
+      insns:
+        -
+          asm_text: "chkfeat x16"
diff --git a/tests/MC/AArch64/armv9.4a-ebep.s.yaml b/tests/MC/AArch64/armv9.4a-ebep.s.yaml
new file mode 100644
index 000000000..76cba36c6
--- /dev/null
+++ b/tests/MC/AArch64/armv9.4a-ebep.s.yaml
@@ -0,0 +1,30 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x22, 0x43, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x2, PM"
+
+  -
+    input:
+      bytes: [ 0x23, 0x43, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PM, x3"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x43, 0x01, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PM, #1"
diff --git a/tests/MC/AArch64/armv9.4a-gcs.s.yaml b/tests/MC/AArch64/armv9.4a-gcs.s.yaml
new file mode 100644
index 000000000..512306f56
--- /dev/null
+++ b/tests/MC/AArch64/armv9.4a-gcs.s.yaml
@@ -0,0 +1,350 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x25, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "gcs" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr GCSCR_EL1, x0"
+
+  -
+    input:
+      bytes: [ 0x01, 0x25, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "gcs" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x1, GCSCR_EL1"
+
+  -
+    input:
+      bytes: [ 0x22, 0x25, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "gcs" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr GCSPR_EL1, x2"
+
+  -
+    input:
+      bytes: [ 0x23, 0x25, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "gcs" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, GCSPR_EL1"
+
+  -
+    input:
+      bytes: [ 0x44, 0x25, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "gcs" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr GCSCRE0_EL1, x4"
+
+  -
+    input:
+      bytes: [ 0x45, 0x25, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "gcs" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x5, GCSCRE0_EL1"
+
+  -
+    input:
+      bytes: [ 0x26, 0x25, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "gcs" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr GCSPR_EL0, x6"
+
+  -
+    input:
+      bytes: [ 0x27, 0x25, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "gcs" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x7, GCSPR_EL0"
+
+  -
+    input:
+      bytes: [ 0x0a, 0x25, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "gcs" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr GCSCR_EL2, x10"
+
+  -
+    input:
+      bytes: [ 0x0b, 0x25, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "gcs" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x11, GCSCR_EL2"
+
+  -
+    input:
+      bytes: [ 0x2c, 0x25, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "gcs" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr GCSPR_EL2, x12"
+
+  -
+    input:
+      bytes: [ 0x2d, 0x25, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "gcs" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x13, GCSPR_EL2"
+
+  -
+    input:
+      bytes: [ 0x0e, 0x25, 0x1d, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "gcs" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr GCSCR_EL12, x14"
+
+  -
+    input:
+      bytes: [ 0x0f, 0x25, 0x3d, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "gcs" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x15, GCSCR_EL12"
+
+  -
+    input:
+      bytes: [ 0x30, 0x25, 0x1d, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "gcs" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr GCSPR_EL12, x16"
+
+  -
+    input:
+      bytes: [ 0x31, 0x25, 0x3d, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "gcs" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x17, GCSPR_EL12"
+
+  -
+    input:
+      bytes: [ 0x12, 0x25, 0x1e, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "gcs" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr GCSCR_EL3, x18"
+
+  -
+    input:
+      bytes: [ 0x13, 0x25, 0x3e, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "gcs" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x19, GCSCR_EL3"
+
+  -
+    input:
+      bytes: [ 0x34, 0x25, 0x1e, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "gcs" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr GCSPR_EL3, x20"
+
+  -
+    input:
+      bytes: [ 0x35, 0x25, 0x3e, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "gcs" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x21, GCSPR_EL3"
+
+  -
+    input:
+      bytes: [ 0x55, 0x77, 0x0b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "gcs" ]
+    expected:
+      insns:
+        -
+          asm_text: "gcsss1 x21"
+
+  -
+    input:
+      bytes: [ 0x76, 0x77, 0x2b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "gcs" ]
+    expected:
+      insns:
+        -
+          asm_text: "gcsss2 x22"
+
+  -
+    input:
+      bytes: [ 0x19, 0x77, 0x0b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "gcs" ]
+    expected:
+      insns:
+        -
+          asm_text: "gcspushm x25"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x77, 0x2b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "gcs" ]
+    expected:
+      insns:
+        -
+          asm_text: "gcspopm"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x77, 0x2b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "gcs" ]
+    expected:
+      insns:
+        -
+          asm_text: "gcspopm"
+
+  -
+    input:
+      bytes: [ 0x39, 0x77, 0x2b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "gcs" ]
+    expected:
+      insns:
+        -
+          asm_text: "gcspopm x25"
+
+  -
+    input:
+      bytes: [ 0x7f, 0x22, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "gcs" ]
+    expected:
+      insns:
+        -
+          asm_text: "gcsb dsync"
+
+  -
+    input:
+      bytes: [ 0x7f, 0x22, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "gcs" ]
+    expected:
+      insns:
+        -
+          asm_text: "gcsb dsync"
+
+  -
+    input:
+      bytes: [ 0x7a, 0x0f, 0x1f, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "gcs" ]
+    expected:
+      insns:
+        -
+          asm_text: "gcsstr x26, x27"
+
+  -
+    input:
+      bytes: [ 0xfa, 0x0f, 0x1f, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "gcs" ]
+    expected:
+      insns:
+        -
+          asm_text: "gcsstr x26, sp"
+
+  -
+    input:
+      bytes: [ 0x7a, 0x1f, 0x1f, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "gcs" ]
+    expected:
+      insns:
+        -
+          asm_text: "gcssttr x26, x27"
+
+  -
+    input:
+      bytes: [ 0xfa, 0x1f, 0x1f, 0xd9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "gcs" ]
+    expected:
+      insns:
+        -
+          asm_text: "gcssttr x26, sp"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x77, 0x08, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "gcs" ]
+    expected:
+      insns:
+        -
+          asm_text: "gcspushx"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x77, 0x08, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "gcs" ]
+    expected:
+      insns:
+        -
+          asm_text: "gcspopcx"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x77, 0x08, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "gcs" ]
+    expected:
+      insns:
+        -
+          asm_text: "gcspopx"
diff --git a/tests/MC/AArch64/armv9.5a-cpa.s.yaml b/tests/MC/AArch64/armv9.5a-cpa.s.yaml
new file mode 100644
index 000000000..4960b6a47
--- /dev/null
+++ b/tests/MC/AArch64/armv9.5a-cpa.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x20, 0x02, 0x9a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cpa" ]
+    expected:
+      insns:
+        -
+          asm_text: "addpt x0, x1, x2"
+
+  -
+    input:
+      bytes: [ 0xff, 0x23, 0x02, 0x9a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cpa" ]
+    expected:
+      insns:
+        -
+          asm_text: "addpt sp, sp, x2"
+
+  -
+    input:
+      bytes: [ 0x20, 0x20, 0x02, 0x9a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cpa" ]
+    expected:
+      insns:
+        -
+          asm_text: "addpt x0, x1, x2"
+
+  -
+    input:
+      bytes: [ 0x20, 0x3c, 0x02, 0x9a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cpa" ]
+    expected:
+      insns:
+        -
+          asm_text: "addpt x0, x1, x2, lsl #7"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0x02, 0x9a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cpa" ]
+    expected:
+      insns:
+        -
+          asm_text: "addpt sp, sp, x2, lsl #7"
+
+  -
+    input:
+      bytes: [ 0x20, 0x20, 0x02, 0xda ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cpa" ]
+    expected:
+      insns:
+        -
+          asm_text: "subpt x0, x1, x2"
+
+  -
+    input:
+      bytes: [ 0xff, 0x23, 0x02, 0xda ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cpa" ]
+    expected:
+      insns:
+        -
+          asm_text: "subpt sp, sp, x2"
+
+  -
+    input:
+      bytes: [ 0x20, 0x20, 0x02, 0xda ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cpa" ]
+    expected:
+      insns:
+        -
+          asm_text: "subpt x0, x1, x2"
+
+  -
+    input:
+      bytes: [ 0x20, 0x3c, 0x02, 0xda ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cpa" ]
+    expected:
+      insns:
+        -
+          asm_text: "subpt x0, x1, x2, lsl #7"
+
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0x02, 0xda ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cpa" ]
+    expected:
+      insns:
+        -
+          asm_text: "subpt sp, sp, x2, lsl #7"
+
+  -
+    input:
+      bytes: [ 0x20, 0x0c, 0x62, 0x9b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cpa" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddpt x0, x1, x2, x3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x8c, 0x62, 0x9b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "cpa" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubpt x0, x1, x2, x3"
diff --git a/tests/MC/AArch64/armv9.5a-e3dse.s.yaml b/tests/MC/AArch64/armv9.5a-e3dse.s.yaml
new file mode 100644
index 000000000..3f0da942a
--- /dev/null
+++ b/tests/MC/AArch64/armv9.5a-e3dse.s.yaml
@@ -0,0 +1,40 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0xc1, 0x3e, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, VDISR_EL3"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc1, 0x1e, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr VDISR_EL3, x0"
+
+  -
+    input:
+      bytes: [ 0x60, 0x52, 0x3e, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, VSESR_EL3"
+
+  -
+    input:
+      bytes: [ 0x60, 0x52, 0x1e, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr VSESR_EL3, x0"
diff --git a/tests/MC/AArch64/armv9.5a-fgwte3.s.yaml b/tests/MC/AArch64/armv9.5a-fgwte3.s.yaml
new file mode 100644
index 000000000..f590567d9
--- /dev/null
+++ b/tests/MC/AArch64/armv9.5a-fgwte3.s.yaml
@@ -0,0 +1,20 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xa0, 0x11, 0x3e, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, FGWTE3_EL3"
+
+  -
+    input:
+      bytes: [ 0xa0, 0x11, 0x1e, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr FGWTE3_EL3, x0"
diff --git a/tests/MC/AArch64/armv9.5a-hacdbs.s.yaml b/tests/MC/AArch64/armv9.5a-hacdbs.s.yaml
new file mode 100644
index 000000000..d14d41e54
--- /dev/null
+++ b/tests/MC/AArch64/armv9.5a-hacdbs.s.yaml
@@ -0,0 +1,40 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x80, 0x23, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, HACDBSBR_EL2"
+
+  -
+    input:
+      bytes: [ 0x80, 0x23, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr HACDBSBR_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0xa0, 0x23, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, HACDBSCONS_EL2"
+
+  -
+    input:
+      bytes: [ 0xa0, 0x23, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr HACDBSCONS_EL2, x0"
diff --git a/tests/MC/AArch64/armv9.5a-hdbss.s.yaml b/tests/MC/AArch64/armv9.5a-hdbss.s.yaml
new file mode 100644
index 000000000..f7cc6019f
--- /dev/null
+++ b/tests/MC/AArch64/armv9.5a-hdbss.s.yaml
@@ -0,0 +1,40 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x40, 0x23, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, HDBSSBR_EL2"
+
+  -
+    input:
+      bytes: [ 0x40, 0x23, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr HDBSSBR_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x60, 0x23, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, HDBSSPROD_EL2"
+
+  -
+    input:
+      bytes: [ 0x60, 0x23, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr HDBSSPROD_EL2, x0"
diff --git a/tests/MC/AArch64/armv9.5a-pauthlr.s.yaml b/tests/MC/AArch64/armv9.5a-pauthlr.s.yaml
new file mode 100644
index 000000000..0446d2003
--- /dev/null
+++ b/tests/MC/AArch64/armv9.5a-pauthlr.s.yaml
@@ -0,0 +1,204 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x1f, 0x20, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "pauth-lr" ]
+    expected:
+      insns:
+        -
+          asm_text: "nop"
+
+  -
+    input:
+      bytes: [ 0xfe, 0xa3, 0xc1, 0xda ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "pauth-lr" ]
+    expected:
+      insns:
+        -
+          asm_text: "paciasppc"
+
+  -
+    input:
+      bytes: [ 0xfe, 0xa7, 0xc1, 0xda ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "pauth-lr" ]
+    expected:
+      insns:
+        -
+          asm_text: "pacibsppc"
+
+  -
+    input:
+      bytes: [ 0xfe, 0x83, 0xc1, 0xda ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "pauth-lr" ]
+    expected:
+      insns:
+        -
+          asm_text: "pacnbiasppc"
+
+  -
+    input:
+      bytes: [ 0xfe, 0x87, 0xc1, 0xda ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "pauth-lr" ]
+    expected:
+      insns:
+        -
+          asm_text: "pacnbibsppc"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x00, 0xa0, 0xf3 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "pauth-lr" ]
+    expected:
+      insns:
+        -
+          asm_text: "autibsppc #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xbf, 0xf3 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "pauth-lr" ]
+    expected:
+      insns:
+        -
+          asm_text: "autibsppc #-262140"
+    skip: true
+    skip_reason: "Capstone does not handle expressions."
+
+  -
+    input:
+      bytes: [ 0x1e, 0x90, 0xc1, 0xda ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "pauth-lr" ]
+    expected:
+      insns:
+        -
+          asm_text: "autiasppc x0"
+
+  -
+    input:
+      bytes: [ 0x3e, 0x94, 0xc1, 0xda ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "pauth-lr" ]
+    expected:
+      insns:
+        -
+          asm_text: "autibsppc x1"
+
+  -
+    input:
+      bytes: [ 0xfe, 0x93, 0xc1, 0xda ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "pauth-lr" ]
+    expected:
+      insns:
+        -
+          asm_text: "autiasppc xzr"
+
+  -
+    input:
+      bytes: [ 0xfe, 0x97, 0xc1, 0xda ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "pauth-lr" ]
+    expected:
+      insns:
+        -
+          asm_text: "autibsppc xzr"
+
+  -
+    input:
+      bytes: [ 0xfe, 0x8b, 0xc1, 0xda ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "pauth-lr" ]
+    expected:
+      insns:
+        -
+          asm_text: "pacia171615"
+
+  -
+    input:
+      bytes: [ 0xfe, 0x8f, 0xc1, 0xda ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "pauth-lr" ]
+    expected:
+      insns:
+        -
+          asm_text: "pacib171615"
+
+  -
+    input:
+      bytes: [ 0xfe, 0xbb, 0xc1, 0xda ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "pauth-lr" ]
+    expected:
+      insns:
+        -
+          asm_text: "autia171615"
+
+  -
+    input:
+      bytes: [ 0xfe, 0xbf, 0xc1, 0xda ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "pauth-lr" ]
+    expected:
+      insns:
+        -
+          asm_text: "autib171615"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x00, 0x00, 0x55 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "pauth-lr" ]
+    expected:
+      insns:
+        -
+          asm_text: "retaasppc #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0x1f, 0x55 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "pauth-lr" ]
+    expected:
+      insns:
+        -
+          asm_text: "retaasppc #-262140"
+    skip: true
+    skip_reason: "Capstone does not handle expressions."
+
+  -
+    input:
+      bytes: [ 0xe2, 0x0b, 0x5f, 0xd6 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "pauth-lr" ]
+    expected:
+      insns:
+        -
+          asm_text: "retaasppc x2"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x0f, 0x5f, 0xd6 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "pauth-lr" ]
+    expected:
+      insns:
+        -
+          asm_text: "retabsppc x3"
+
+  -
+    input:
+      bytes: [ 0xff, 0x24, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "pauth-lr" ]
+    expected:
+      insns:
+        -
+          asm_text: "pacm"
diff --git a/tests/MC/AArch64/armv9.5a-spmu2.s.yaml b/tests/MC/AArch64/armv9.5a-spmu2.s.yaml
new file mode 100644
index 000000000..8c87a881c
--- /dev/null
+++ b/tests/MC/AArch64/armv9.5a-spmu2.s.yaml
@@ -0,0 +1,10 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x80, 0x9c, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPMZR_EL0, x0"
diff --git a/tests/MC/AArch64/armv9.5a-step2.s.yaml b/tests/MC/AArch64/armv9.5a-step2.s.yaml
new file mode 100644
index 000000000..00da2b54a
--- /dev/null
+++ b/tests/MC/AArch64/armv9.5a-step2.s.yaml
@@ -0,0 +1,20 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x40, 0x05, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, MDSTEPOP_EL1"
+
+  -
+    input:
+      bytes: [ 0x40, 0x05, 0x10, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr MDSTEPOP_EL1, x0"
diff --git a/tests/MC/AArch64/armv9.5a-tlbiw.s.yaml b/tests/MC/AArch64/armv9.5a-tlbiw.s.yaml
new file mode 100644
index 000000000..e3d452526
--- /dev/null
+++ b/tests/MC/AArch64/armv9.5a-tlbiw.s.yaml
@@ -0,0 +1,60 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x5f, 0x86, 0x0c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "tlbiw", "xs" ]
+    expected:
+      insns:
+        -
+          asm_text: "tlbi vmallws2e1"
+
+  -
+    input:
+      bytes: [ 0x5f, 0x82, 0x0c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "tlbiw", "xs" ]
+    expected:
+      insns:
+        -
+          asm_text: "tlbi vmallws2e1is"
+
+  -
+    input:
+      bytes: [ 0x5f, 0x85, 0x0c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "tlbiw", "xs" ]
+    expected:
+      insns:
+        -
+          asm_text: "tlbi vmallws2e1os"
+
+  -
+    input:
+      bytes: [ 0x5f, 0x96, 0x0c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "tlbiw", "xs" ]
+    expected:
+      insns:
+        -
+          asm_text: "tlbi vmallws2e1nxs"
+
+  -
+    input:
+      bytes: [ 0x5f, 0x92, 0x0c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "tlbiw", "xs" ]
+    expected:
+      insns:
+        -
+          asm_text: "tlbi vmallws2e1isnxs"
+
+  -
+    input:
+      bytes: [ 0x5f, 0x95, 0x0c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "tlbiw", "xs" ]
+    expected:
+      insns:
+        -
+          asm_text: "tlbi vmallws2e1osnxs"
diff --git a/tests/MC/AArch64/armv9a-mec.s.yaml b/tests/MC/AArch64/armv9a-mec.s.yaml
new file mode 100644
index 000000000..e7a59c10a
--- /dev/null
+++ b/tests/MC/AArch64/armv9a-mec.s.yaml
@@ -0,0 +1,340 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xe0, 0xa8, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "mec" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, MECIDR_EL2"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa8, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "mec" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, MECID_P0_EL2"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa8, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "mec" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, MECID_A0_EL2"
+
+  -
+    input:
+      bytes: [ 0x40, 0xa8, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "mec" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, MECID_P1_EL2"
+
+  -
+    input:
+      bytes: [ 0x60, 0xa8, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "mec" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, MECID_A1_EL2"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa9, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "mec" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, VMECID_P_EL2"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa9, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "mec" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, VMECID_A_EL2"
+
+  -
+    input:
+      bytes: [ 0x20, 0xaa, 0x3e, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "mec" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, MECID_RL_A_EL3"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa8, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "mec" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr MECID_P0_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa8, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "mec" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr MECID_A0_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x40, 0xa8, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "mec" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr MECID_P1_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x60, 0xa8, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "mec" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr MECID_A1_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa9, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "mec" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr VMECID_P_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa9, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "mec" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr VMECID_A_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x20, 0xaa, 0x1e, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "mec" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr MECID_RL_A_EL3, x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x7e, 0x0c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "mec" ]
+    expected:
+      insns:
+        -
+          asm_text: "dc cigdpae, x0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x7e, 0x0c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "mec" ]
+    expected:
+      insns:
+        -
+          asm_text: "dc cipae, x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xa8, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9a" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, MECIDR_EL2"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa8, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9a" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, MECID_P0_EL2"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa8, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9a" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, MECID_A0_EL2"
+
+  -
+    input:
+      bytes: [ 0x40, 0xa8, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9a" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, MECID_P1_EL2"
+
+  -
+    input:
+      bytes: [ 0x60, 0xa8, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9a" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, MECID_A1_EL2"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa9, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9a" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, VMECID_P_EL2"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa9, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9a" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, VMECID_A_EL2"
+
+  -
+    input:
+      bytes: [ 0x20, 0xaa, 0x3e, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9a" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, MECID_RL_A_EL3"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa8, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr MECID_P0_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa8, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr MECID_A0_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x40, 0xa8, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr MECID_P1_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x60, 0xa8, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr MECID_A1_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa9, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr VMECID_P_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa9, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr VMECID_A_EL2, x0"
+
+  -
+    input:
+      bytes: [ 0x20, 0xaa, 0x1e, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9a" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr MECID_RL_A_EL3, x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x7e, 0x0c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9a" ]
+    expected:
+      insns:
+        -
+          asm_text: "dc cigdpae, x0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x7e, 0x0c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v9a" ]
+    expected:
+      insns:
+        -
+          asm_text: "dc cipae, x0"
diff --git a/tests/MC/AArch64/basic-a64-instructions.s.yaml b/tests/MC/AArch64/basic-a64-instructions.s.yaml
new file mode 100644
index 000000000..a2893ae2f
--- /dev/null
+++ b/tests/MC/AArch64/basic-a64-instructions.s.yaml
@@ -0,0 +1,20904 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x82, 0x00, 0x25, 0x8b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "add x2, x4, w5, uxtb"
+
+  -
+    input:
+      bytes: [ 0xf4, 0x23, 0x33, 0x8b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "add x20, sp, w19, uxth"
+
+  -
+    input:
+      bytes: [ 0x2c, 0x40, 0x34, 0x8b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "add x12, x1, w20, uxtw"
+
+  -
+    input:
+      bytes: [ 0x74, 0x60, 0x2d, 0x8b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "add x20, x3, x13, uxtx"
+
+  -
+    input:
+      bytes: [ 0x31, 0x83, 0x34, 0x8b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "add x17, x25, w20, sxtb"
+
+  -
+    input:
+      bytes: [ 0xb2, 0xa1, 0x33, 0x8b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "add x18, x13, w19, sxth"
+
+  -
+    input:
+      bytes: [ 0x5f, 0xc0, 0x23, 0x8b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "add sp, x2, w3, sxtw"
+
+  -
+    input:
+      bytes: [ 0xa3, 0xe0, 0x29, 0x8b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "add x3, x5, x9, sxtx"
+
+  -
+    input:
+      bytes: [ 0xa2, 0x00, 0x27, 0x0b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "add w2, w5, w7, uxtb"
+
+  -
+    input:
+      bytes: [ 0xf5, 0x21, 0x31, 0x0b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "add w21, w15, w17, uxth"
+
+  -
+    input:
+      bytes: [ 0xbe, 0x43, 0x3f, 0x0b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "add w30, w29, wzr, uxtw"
+
+  -
+    input:
+      bytes: [ 0x33, 0x62, 0x21, 0x0b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "add w19, w17, w1, uxtx"
+
+  -
+    input:
+      bytes: [ 0xa2, 0x80, 0x21, 0x0b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "add w2, w5, w1, sxtb"
+
+  -
+    input:
+      bytes: [ 0x3a, 0xa2, 0x33, 0x0b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "add w26, w17, w19, sxth"
+
+  -
+    input:
+      bytes: [ 0x40, 0xc0, 0x23, 0x0b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "add w0, w2, w3, sxtw"
+
+  -
+    input:
+      bytes: [ 0x62, 0xe0, 0x25, 0x0b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "add w2, w3, w5, sxtx"
+
+  -
+    input:
+      bytes: [ 0x62, 0x80, 0x25, 0x8b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "add x2, x3, w5, sxtb"
+
+  -
+    input:
+      bytes: [ 0x67, 0x31, 0x2d, 0x8b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "add x7, x11, w13, uxth #4"
+
+  -
+    input:
+      bytes: [ 0x71, 0x4a, 0x37, 0x0b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "add w17, w19, w23, uxtw #2"
+
+  -
+    input:
+      bytes: [ 0xfd, 0x66, 0x31, 0x0b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "add w29, w23, w17, uxtx #1"
+
+  -
+    input:
+      bytes: [ 0x82, 0x08, 0x25, 0xcb ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub x2, x4, w5, uxtb #2"
+
+  -
+    input:
+      bytes: [ 0xf4, 0x33, 0x33, 0xcb ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub x20, sp, w19, uxth #4"
+
+  -
+    input:
+      bytes: [ 0x2c, 0x40, 0x34, 0xcb ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub x12, x1, w20, uxtw"
+
+  -
+    input:
+      bytes: [ 0x74, 0x60, 0x2d, 0xcb ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub x20, x3, x13, uxtx"
+
+  -
+    input:
+      bytes: [ 0x31, 0x83, 0x34, 0xcb ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub x17, x25, w20, sxtb"
+
+  -
+    input:
+      bytes: [ 0xb2, 0xa1, 0x33, 0xcb ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub x18, x13, w19, sxth"
+
+  -
+    input:
+      bytes: [ 0x5f, 0xc0, 0x23, 0xcb ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub sp, x2, w3, sxtw"
+
+  -
+    input:
+      bytes: [ 0xa3, 0xe0, 0x29, 0xcb ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub x3, x5, x9, sxtx"
+
+  -
+    input:
+      bytes: [ 0xa2, 0x00, 0x27, 0x4b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub w2, w5, w7, uxtb"
+
+  -
+    input:
+      bytes: [ 0xf5, 0x21, 0x31, 0x4b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub w21, w15, w17, uxth"
+
+  -
+    input:
+      bytes: [ 0xbe, 0x43, 0x3f, 0x4b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub w30, w29, wzr, uxtw"
+
+  -
+    input:
+      bytes: [ 0x33, 0x62, 0x21, 0x4b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub w19, w17, w1, uxtx"
+
+  -
+    input:
+      bytes: [ 0xa2, 0x80, 0x21, 0x4b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub w2, w5, w1, sxtb"
+
+  -
+    input:
+      bytes: [ 0xfa, 0xa3, 0x33, 0x4b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub w26, wsp, w19, sxth"
+
+  -
+    input:
+      bytes: [ 0x5f, 0xc0, 0x23, 0x4b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub wsp, w2, w3, sxtw"
+
+  -
+    input:
+      bytes: [ 0x62, 0xe0, 0x25, 0x4b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub w2, w3, w5, sxtx"
+
+  -
+    input:
+      bytes: [ 0x82, 0x08, 0x25, 0xab ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "adds x2, x4, w5, uxtb #2"
+
+  -
+    input:
+      bytes: [ 0xf4, 0x33, 0x33, 0xab ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "adds x20, sp, w19, uxth #4"
+
+  -
+    input:
+      bytes: [ 0x2c, 0x40, 0x34, 0xab ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "adds x12, x1, w20, uxtw"
+
+  -
+    input:
+      bytes: [ 0x74, 0x60, 0x2d, 0xab ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "adds x20, x3, x13, uxtx"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x8f, 0x34, 0xab ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmn x25, w20, sxtb #3"
+
+  -
+    input:
+      bytes: [ 0xf2, 0xa3, 0x33, 0xab ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "adds x18, sp, w19, sxth"
+
+  -
+    input:
+      bytes: [ 0x5f, 0xc0, 0x23, 0xab ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmn x2, w3, sxtw"
+
+  -
+    input:
+      bytes: [ 0xa3, 0xe8, 0x29, 0xab ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "adds x3, x5, x9, sxtx #2"
+
+  -
+    input:
+      bytes: [ 0xa2, 0x00, 0x27, 0x2b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "adds w2, w5, w7, uxtb"
+
+  -
+    input:
+      bytes: [ 0xf5, 0x21, 0x31, 0x2b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "adds w21, w15, w17, uxth"
+
+  -
+    input:
+      bytes: [ 0xbe, 0x43, 0x3f, 0x2b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "adds w30, w29, wzr, uxtw"
+
+  -
+    input:
+      bytes: [ 0x33, 0x62, 0x21, 0x2b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "adds w19, w17, w1, uxtx"
+
+  -
+    input:
+      bytes: [ 0xa2, 0x84, 0x21, 0x2b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "adds w2, w5, w1, sxtb #1"
+
+  -
+    input:
+      bytes: [ 0xfa, 0xa3, 0x33, 0x2b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "adds w26, wsp, w19, sxth"
+
+  -
+    input:
+      bytes: [ 0x5f, 0xc0, 0x23, 0x2b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmn w2, w3, sxtw"
+
+  -
+    input:
+      bytes: [ 0x62, 0xe0, 0x25, 0x2b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "adds w2, w3, w5, sxtx"
+
+  -
+    input:
+      bytes: [ 0x82, 0x08, 0x25, 0xeb ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "subs x2, x4, w5, uxtb #2"
+
+  -
+    input:
+      bytes: [ 0xf4, 0x33, 0x33, 0xeb ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "subs x20, sp, w19, uxth #4"
+
+  -
+    input:
+      bytes: [ 0x2c, 0x40, 0x34, 0xeb ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "subs x12, x1, w20, uxtw"
+
+  -
+    input:
+      bytes: [ 0x74, 0x60, 0x2d, 0xeb ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "subs x20, x3, x13, uxtx"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x8f, 0x34, 0xeb ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmp x25, w20, sxtb #3"
+
+  -
+    input:
+      bytes: [ 0xf2, 0xa3, 0x33, 0xeb ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "subs x18, sp, w19, sxth"
+
+  -
+    input:
+      bytes: [ 0x5f, 0xc0, 0x23, 0xeb ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmp x2, w3, sxtw"
+
+  -
+    input:
+      bytes: [ 0xa3, 0xe8, 0x29, 0xeb ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "subs x3, x5, x9, sxtx #2"
+
+  -
+    input:
+      bytes: [ 0xa2, 0x00, 0x27, 0x6b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "subs w2, w5, w7, uxtb"
+
+  -
+    input:
+      bytes: [ 0xf5, 0x21, 0x31, 0x6b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "subs w21, w15, w17, uxth"
+
+  -
+    input:
+      bytes: [ 0xbe, 0x43, 0x3f, 0x6b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "subs w30, w29, wzr, uxtw"
+
+  -
+    input:
+      bytes: [ 0x33, 0x62, 0x21, 0x6b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "subs w19, w17, w1, uxtx"
+
+  -
+    input:
+      bytes: [ 0xa2, 0x84, 0x21, 0x6b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "subs w2, w5, w1, sxtb #1"
+
+  -
+    input:
+      bytes: [ 0xfa, 0xa3, 0x33, 0x6b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "subs w26, wsp, w19, sxth"
+
+  -
+    input:
+      bytes: [ 0x5f, 0xc0, 0x23, 0x6b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmp w2, w3, sxtw"
+
+  -
+    input:
+      bytes: [ 0x62, 0xe0, 0x25, 0x6b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "subs w2, w3, w5, sxtx"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x08, 0x25, 0xeb ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmp x4, w5, uxtb #2"
+
+  -
+    input:
+      bytes: [ 0xff, 0x33, 0x33, 0xeb ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmp sp, w19, uxth #4"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x40, 0x34, 0xeb ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmp x1, w20, uxtw"
+
+  -
+    input:
+      bytes: [ 0x7f, 0x60, 0x2d, 0xeb ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmp x3, x13, uxtx"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x8f, 0x34, 0xeb ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmp x25, w20, sxtb #3"
+
+  -
+    input:
+      bytes: [ 0xff, 0xa3, 0x33, 0xeb ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmp sp, w19, sxth"
+
+  -
+    input:
+      bytes: [ 0x5f, 0xc0, 0x23, 0xeb ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmp x2, w3, sxtw"
+
+  -
+    input:
+      bytes: [ 0xbf, 0xe8, 0x29, 0xeb ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmp x5, x9, sxtx #2"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x00, 0x27, 0x6b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmp w5, w7, uxtb"
+
+  -
+    input:
+      bytes: [ 0xff, 0x21, 0x31, 0x6b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmp w15, w17, uxth"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x43, 0x3f, 0x6b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmp w29, wzr, uxtw"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x62, 0x21, 0x6b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmp w17, w1, uxtx"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x84, 0x21, 0x6b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmp w5, w1, sxtb #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0xa3, 0x33, 0x6b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmp wsp, w19, sxth"
+
+  -
+    input:
+      bytes: [ 0x5f, 0xc0, 0x23, 0x6b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmp w2, w3, sxtw"
+
+  -
+    input:
+      bytes: [ 0x7f, 0xe0, 0x25, 0x6b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmp w3, w5, sxtx"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x08, 0x25, 0xab ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmn x4, w5, uxtb #2"
+
+  -
+    input:
+      bytes: [ 0xff, 0x33, 0x33, 0xab ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmn sp, w19, uxth #4"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x40, 0x34, 0xab ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmn x1, w20, uxtw"
+
+  -
+    input:
+      bytes: [ 0x7f, 0x60, 0x2d, 0xab ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmn x3, x13, uxtx"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x8f, 0x34, 0xab ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmn x25, w20, sxtb #3"
+
+  -
+    input:
+      bytes: [ 0xff, 0xa3, 0x33, 0xab ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmn sp, w19, sxth"
+
+  -
+    input:
+      bytes: [ 0x5f, 0xc0, 0x23, 0xab ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmn x2, w3, sxtw"
+
+  -
+    input:
+      bytes: [ 0xbf, 0xe8, 0x29, 0xab ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmn x5, x9, sxtx #2"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x00, 0x27, 0x2b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmn w5, w7, uxtb"
+
+  -
+    input:
+      bytes: [ 0xff, 0x21, 0x31, 0x2b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmn w15, w17, uxth"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x43, 0x3f, 0x2b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmn w29, wzr, uxtw"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x62, 0x21, 0x2b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmn w17, w1, uxtx"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x84, 0x21, 0x2b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmn w5, w1, sxtb #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0xa3, 0x33, 0x2b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmn wsp, w19, sxth"
+
+  -
+    input:
+      bytes: [ 0x5f, 0xc0, 0x23, 0x2b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmn w2, w3, sxtw"
+
+  -
+    input:
+      bytes: [ 0x7f, 0xe0, 0x25, 0x2b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmn w3, w5, sxtx"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x0e, 0x3d, 0xeb ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmp x20, w29, uxtb #3"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x71, 0x2d, 0xeb ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmp x12, x13, uxtx #4"
+
+  -
+    input:
+      bytes: [ 0xff, 0x03, 0x21, 0x6b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmp wsp, w1, uxtb"
+
+  -
+    input:
+      bytes: [ 0xff, 0xc3, 0x3f, 0x2b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmn wsp, wzr, sxtw"
+
+  -
+    input:
+      bytes: [ 0x7f, 0x70, 0x27, 0xcb ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub sp, x3, x7, lsl #4"
+
+  -
+    input:
+      bytes: [ 0xe2, 0x47, 0x23, 0x0b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "add w2, wsp, w3, lsl #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0x43, 0x29, 0x6b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmp wsp, w9"
+
+  -
+    input:
+      bytes: [ 0xff, 0x53, 0x23, 0x2b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmn wsp, w3, lsl #4"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x6b, 0x29, 0xeb ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "subs x3, sp, x9, lsl #2"
+
+  -
+    input:
+      bytes: [ 0xa4, 0x00, 0x00, 0x11 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "add w4, w5, #0"
+
+  -
+    input:
+      bytes: [ 0x62, 0xfc, 0x3f, 0x11 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "add w2, w3, #4095"
+
+  -
+    input:
+      bytes: [ 0xbe, 0x07, 0x40, 0x11 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "add w30, w29, #1, lsl #12"
+
+  -
+    input:
+      bytes: [ 0xad, 0xfc, 0x7f, 0x11 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "add w13, w5, #4095, lsl #12"
+
+  -
+    input:
+      bytes: [ 0xe5, 0x98, 0x19, 0x91 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "add x5, x7, #1638"
+
+  -
+    input:
+      bytes: [ 0xf4, 0x87, 0x0c, 0x11 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "add w20, wsp, #801"
+
+  -
+    input:
+      bytes: [ 0xff, 0x43, 0x11, 0x11 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "add wsp, wsp, #1104"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xd3, 0x3f, 0x11 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "add wsp, w30, #4084"
+
+  -
+    input:
+      bytes: [ 0x00, 0x8f, 0x04, 0x91 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "add x0, x24, #291"
+
+  -
+    input:
+      bytes: [ 0x03, 0xff, 0x7f, 0x91 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "add x3, x24, #4095, lsl #12"
+
+  -
+    input:
+      bytes: [ 0xe8, 0xcb, 0x10, 0x91 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "add x8, sp, #1074"
+
+  -
+    input:
+      bytes: [ 0xbf, 0xa3, 0x3b, 0x91 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "add sp, x29, #3816"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xb7, 0x3f, 0x51 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub w0, wsp, #4077"
+
+  -
+    input:
+      bytes: [ 0x84, 0x8a, 0x48, 0x51 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub w4, w20, #546, lsl #12"
+
+  -
+    input:
+      bytes: [ 0xff, 0x83, 0x04, 0xd1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub sp, sp, #288"
+
+  -
+    input:
+      bytes: [ 0x7f, 0x42, 0x00, 0x51 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub wsp, w19, #16"
+
+  -
+    input:
+      bytes: [ 0xed, 0x8e, 0x44, 0x31 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "adds w13, w23, #291, lsl #12"
+
+  -
+    input:
+      bytes: [ 0x5f, 0xfc, 0x3f, 0x31 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmn w2, #4095"
+
+  -
+    input:
+      bytes: [ 0xf4, 0x03, 0x00, 0x31 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "adds w20, wsp, #0"
+
+  -
+    input:
+      bytes: [ 0x7f, 0x04, 0x40, 0xb1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmn x3, #1, lsl #12"
+
+  -
+    input:
+      bytes: [ 0xff, 0x53, 0x40, 0xf1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmp sp, #20, lsl #12"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xff, 0x3f, 0xf1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmp x30, #4095"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xbb, 0x3b, 0xf1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "subs x4, sp, #3822"
+
+  -
+    input:
+      bytes: [ 0x7f, 0x8c, 0x44, 0x31 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmn w3, #291, lsl #12"
+
+  -
+    input:
+      bytes: [ 0xff, 0x57, 0x15, 0x31 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmn wsp, #1365"
+
+  -
+    input:
+      bytes: [ 0xff, 0x13, 0x51, 0xb1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmn sp, #1092, lsl #12"
+
+  -
+    input:
+      bytes: [ 0x9f, 0xb0, 0x44, 0xf1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmp x4, #300, lsl #12"
+
+  -
+    input:
+      bytes: [ 0xff, 0xd3, 0x07, 0x71 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmp wsp, #500"
+
+  -
+    input:
+      bytes: [ 0xff, 0x23, 0x03, 0xf1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmp sp, #200"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x03, 0x00, 0x91 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov sp, x30"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x02, 0x00, 0x11 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov wsp, w20"
+
+  -
+    input:
+      bytes: [ 0xeb, 0x03, 0x00, 0x91 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov x11, sp"
+
+  -
+    input:
+      bytes: [ 0xf8, 0x03, 0x00, 0x11 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov w24, wsp"
+
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0x07, 0x0b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "add w3, w5, w7"
+
+  -
+    input:
+      bytes: [ 0x7f, 0x00, 0x05, 0x0b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "add wzr, w3, w5"
+
+  -
+    input:
+      bytes: [ 0xf4, 0x03, 0x04, 0x0b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "add w20, wzr, w4"
+
+  -
+    input:
+      bytes: [ 0xc4, 0x00, 0x1f, 0x0b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "add w4, w6, wzr"
+
+  -
+    input:
+      bytes: [ 0xab, 0x01, 0x0f, 0x0b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "add w11, w13, w15"
+
+  -
+    input:
+      bytes: [ 0x69, 0x28, 0x1f, 0x0b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "add w9, w3, wzr, lsl #10"
+
+  -
+    input:
+      bytes: [ 0xb1, 0x7f, 0x14, 0x0b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "add w17, w29, w20, lsl #31"
+
+  -
+    input:
+      bytes: [ 0xb1, 0x77, 0x14, 0x0b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "add w17, w29, w20, lsl #29"
+
+  -
+    input:
+      bytes: [ 0xd5, 0x02, 0x57, 0x0b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "add w21, w22, w23, lsr #0"
+
+  -
+    input:
+      bytes: [ 0x38, 0x4b, 0x5a, 0x0b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "add w24, w25, w26, lsr #18"
+
+  -
+    input:
+      bytes: [ 0x9b, 0x7f, 0x5d, 0x0b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "add w27, w28, w29, lsr #31"
+
+  -
+    input:
+      bytes: [ 0x9b, 0x77, 0x5d, 0x0b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "add w27, w28, w29, lsr #29"
+
+  -
+    input:
+      bytes: [ 0x62, 0x00, 0x84, 0x0b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "add w2, w3, w4, asr #0"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x54, 0x87, 0x0b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "add w5, w6, w7, asr #21"
+
+  -
+    input:
+      bytes: [ 0x28, 0x7d, 0x8a, 0x0b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "add w8, w9, w10, asr #31"
+
+  -
+    input:
+      bytes: [ 0x28, 0x75, 0x8a, 0x0b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "add w8, w9, w10, asr #29"
+
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0x07, 0x8b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "add x3, x5, x7"
+
+  -
+    input:
+      bytes: [ 0x7f, 0x00, 0x05, 0x8b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "add xzr, x3, x5"
+
+  -
+    input:
+      bytes: [ 0xf4, 0x03, 0x04, 0x8b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "add x20, xzr, x4"
+
+  -
+    input:
+      bytes: [ 0xc4, 0x00, 0x1f, 0x8b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "add x4, x6, xzr"
+
+  -
+    input:
+      bytes: [ 0xab, 0x01, 0x0f, 0x8b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "add x11, x13, x15"
+
+  -
+    input:
+      bytes: [ 0x69, 0x28, 0x1f, 0x8b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "add x9, x3, xzr, lsl #10"
+
+  -
+    input:
+      bytes: [ 0xb1, 0xff, 0x14, 0x8b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "add x17, x29, x20, lsl #63"
+
+  -
+    input:
+      bytes: [ 0xb1, 0xeb, 0x14, 0x8b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "add x17, x29, x20, lsl #58"
+
+  -
+    input:
+      bytes: [ 0xd5, 0x02, 0x57, 0x8b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "add x21, x22, x23, lsr #0"
+
+  -
+    input:
+      bytes: [ 0x38, 0x4b, 0x5a, 0x8b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "add x24, x25, x26, lsr #18"
+
+  -
+    input:
+      bytes: [ 0x9b, 0xff, 0x5d, 0x8b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "add x27, x28, x29, lsr #63"
+
+  -
+    input:
+      bytes: [ 0xb1, 0xeb, 0x54, 0x8b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "add x17, x29, x20, lsr #58"
+
+  -
+    input:
+      bytes: [ 0x62, 0x00, 0x84, 0x8b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "add x2, x3, x4, asr #0"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x54, 0x87, 0x8b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "add x5, x6, x7, asr #21"
+
+  -
+    input:
+      bytes: [ 0x28, 0xfd, 0x8a, 0x8b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "add x8, x9, x10, asr #63"
+
+  -
+    input:
+      bytes: [ 0xb1, 0xeb, 0x94, 0x8b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "add x17, x29, x20, asr #58"
+
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0x07, 0x2b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "adds w3, w5, w7"
+
+  -
+    input:
+      bytes: [ 0x7f, 0x00, 0x05, 0x2b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmn w3, w5"
+
+  -
+    input:
+      bytes: [ 0xf4, 0x03, 0x04, 0x2b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "adds w20, wzr, w4"
+
+  -
+    input:
+      bytes: [ 0xc4, 0x00, 0x1f, 0x2b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "adds w4, w6, wzr"
+
+  -
+    input:
+      bytes: [ 0xab, 0x01, 0x0f, 0x2b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "adds w11, w13, w15"
+
+  -
+    input:
+      bytes: [ 0x69, 0x28, 0x1f, 0x2b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "adds w9, w3, wzr, lsl #10"
+
+  -
+    input:
+      bytes: [ 0xb1, 0x7f, 0x14, 0x2b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "adds w17, w29, w20, lsl #31"
+
+  -
+    input:
+      bytes: [ 0xd5, 0x02, 0x57, 0x2b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "adds w21, w22, w23, lsr #0"
+
+  -
+    input:
+      bytes: [ 0x38, 0x4b, 0x5a, 0x2b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "adds w24, w25, w26, lsr #18"
+
+  -
+    input:
+      bytes: [ 0x9b, 0x7f, 0x5d, 0x2b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "adds w27, w28, w29, lsr #31"
+
+  -
+    input:
+      bytes: [ 0x62, 0x00, 0x84, 0x2b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "adds w2, w3, w4, asr #0"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x54, 0x87, 0x2b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "adds w5, w6, w7, asr #21"
+
+  -
+    input:
+      bytes: [ 0x28, 0x7d, 0x8a, 0x2b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "adds w8, w9, w10, asr #31"
+
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0x07, 0xab ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "adds x3, x5, x7"
+
+  -
+    input:
+      bytes: [ 0x7f, 0x00, 0x05, 0xab ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmn x3, x5"
+
+  -
+    input:
+      bytes: [ 0xf4, 0x03, 0x04, 0xab ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "adds x20, xzr, x4"
+
+  -
+    input:
+      bytes: [ 0xc4, 0x00, 0x1f, 0xab ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "adds x4, x6, xzr"
+
+  -
+    input:
+      bytes: [ 0xab, 0x01, 0x0f, 0xab ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "adds x11, x13, x15"
+
+  -
+    input:
+      bytes: [ 0x69, 0x28, 0x1f, 0xab ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "adds x9, x3, xzr, lsl #10"
+
+  -
+    input:
+      bytes: [ 0xb1, 0xff, 0x14, 0xab ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "adds x17, x29, x20, lsl #63"
+
+  -
+    input:
+      bytes: [ 0xd5, 0x02, 0x57, 0xab ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "adds x21, x22, x23, lsr #0"
+
+  -
+    input:
+      bytes: [ 0x38, 0x4b, 0x5a, 0xab ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "adds x24, x25, x26, lsr #18"
+
+  -
+    input:
+      bytes: [ 0x9b, 0xff, 0x5d, 0xab ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "adds x27, x28, x29, lsr #63"
+
+  -
+    input:
+      bytes: [ 0x62, 0x00, 0x84, 0xab ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "adds x2, x3, x4, asr #0"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x54, 0x87, 0xab ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "adds x5, x6, x7, asr #21"
+
+  -
+    input:
+      bytes: [ 0x28, 0xfd, 0x8a, 0xab ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "adds x8, x9, x10, asr #63"
+
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0x07, 0x4b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub w3, w5, w7"
+
+  -
+    input:
+      bytes: [ 0x7f, 0x00, 0x05, 0x4b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub wzr, w3, w5"
+
+  -
+    input:
+      bytes: [ 0xf4, 0x03, 0x04, 0x4b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "neg w20, w4"
+
+  -
+    input:
+      bytes: [ 0xc4, 0x00, 0x1f, 0x4b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub w4, w6, wzr"
+
+  -
+    input:
+      bytes: [ 0xab, 0x01, 0x0f, 0x4b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub w11, w13, w15"
+
+  -
+    input:
+      bytes: [ 0x69, 0x28, 0x1f, 0x4b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub w9, w3, wzr, lsl #10"
+
+  -
+    input:
+      bytes: [ 0xb1, 0x7f, 0x14, 0x4b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub w17, w29, w20, lsl #31"
+
+  -
+    input:
+      bytes: [ 0xd5, 0x02, 0x57, 0x4b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub w21, w22, w23, lsr #0"
+
+  -
+    input:
+      bytes: [ 0x38, 0x4b, 0x5a, 0x4b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub w24, w25, w26, lsr #18"
+
+  -
+    input:
+      bytes: [ 0x9b, 0x7f, 0x5d, 0x4b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub w27, w28, w29, lsr #31"
+
+  -
+    input:
+      bytes: [ 0x62, 0x00, 0x84, 0x4b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub w2, w3, w4, asr #0"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x54, 0x87, 0x4b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub w5, w6, w7, asr #21"
+
+  -
+    input:
+      bytes: [ 0x28, 0x7d, 0x8a, 0x4b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub w8, w9, w10, asr #31"
+
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0x07, 0xcb ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub x3, x5, x7"
+
+  -
+    input:
+      bytes: [ 0x7f, 0x00, 0x05, 0xcb ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub xzr, x3, x5"
+
+  -
+    input:
+      bytes: [ 0xf4, 0x03, 0x04, 0xcb ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "neg x20, x4"
+
+  -
+    input:
+      bytes: [ 0xc4, 0x00, 0x1f, 0xcb ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub x4, x6, xzr"
+
+  -
+    input:
+      bytes: [ 0xab, 0x01, 0x0f, 0xcb ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub x11, x13, x15"
+
+  -
+    input:
+      bytes: [ 0x69, 0x28, 0x1f, 0xcb ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub x9, x3, xzr, lsl #10"
+
+  -
+    input:
+      bytes: [ 0xb1, 0xff, 0x14, 0xcb ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub x17, x29, x20, lsl #63"
+
+  -
+    input:
+      bytes: [ 0xd5, 0x02, 0x57, 0xcb ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub x21, x22, x23, lsr #0"
+
+  -
+    input:
+      bytes: [ 0x38, 0x4b, 0x5a, 0xcb ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub x24, x25, x26, lsr #18"
+
+  -
+    input:
+      bytes: [ 0x9b, 0xff, 0x5d, 0xcb ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub x27, x28, x29, lsr #63"
+
+  -
+    input:
+      bytes: [ 0x62, 0x00, 0x84, 0xcb ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub x2, x3, x4, asr #0"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x54, 0x87, 0xcb ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub x5, x6, x7, asr #21"
+
+  -
+    input:
+      bytes: [ 0x28, 0xfd, 0x8a, 0xcb ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub x8, x9, x10, asr #63"
+
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0x07, 0x6b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "subs w3, w5, w7"
+
+  -
+    input:
+      bytes: [ 0x7f, 0x00, 0x05, 0x6b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmp w3, w5"
+
+  -
+    input:
+      bytes: [ 0xf4, 0x03, 0x04, 0x6b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "negs w20, w4"
+
+  -
+    input:
+      bytes: [ 0xc4, 0x00, 0x1f, 0x6b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "subs w4, w6, wzr"
+
+  -
+    input:
+      bytes: [ 0xab, 0x01, 0x0f, 0x6b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "subs w11, w13, w15"
+
+  -
+    input:
+      bytes: [ 0x69, 0x28, 0x1f, 0x6b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "subs w9, w3, wzr, lsl #10"
+
+  -
+    input:
+      bytes: [ 0xb1, 0x7f, 0x14, 0x6b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "subs w17, w29, w20, lsl #31"
+
+  -
+    input:
+      bytes: [ 0xd5, 0x02, 0x57, 0x6b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "subs w21, w22, w23, lsr #0"
+
+  -
+    input:
+      bytes: [ 0x38, 0x4b, 0x5a, 0x6b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "subs w24, w25, w26, lsr #18"
+
+  -
+    input:
+      bytes: [ 0x9b, 0x7f, 0x5d, 0x6b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "subs w27, w28, w29, lsr #31"
+
+  -
+    input:
+      bytes: [ 0x62, 0x00, 0x84, 0x6b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "subs w2, w3, w4, asr #0"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x54, 0x87, 0x6b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "subs w5, w6, w7, asr #21"
+
+  -
+    input:
+      bytes: [ 0x28, 0x7d, 0x8a, 0x6b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "subs w8, w9, w10, asr #31"
+
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0x07, 0xeb ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "subs x3, x5, x7"
+
+  -
+    input:
+      bytes: [ 0x7f, 0x00, 0x05, 0xeb ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmp x3, x5"
+
+  -
+    input:
+      bytes: [ 0xf4, 0x03, 0x04, 0xeb ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "negs x20, x4"
+
+  -
+    input:
+      bytes: [ 0xc4, 0x00, 0x1f, 0xeb ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "subs x4, x6, xzr"
+
+  -
+    input:
+      bytes: [ 0xab, 0x01, 0x0f, 0xeb ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "subs x11, x13, x15"
+
+  -
+    input:
+      bytes: [ 0x69, 0x28, 0x1f, 0xeb ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "subs x9, x3, xzr, lsl #10"
+
+  -
+    input:
+      bytes: [ 0xb1, 0xff, 0x14, 0xeb ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "subs x17, x29, x20, lsl #63"
+
+  -
+    input:
+      bytes: [ 0xd5, 0x02, 0x57, 0xeb ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "subs x21, x22, x23, lsr #0"
+
+  -
+    input:
+      bytes: [ 0x38, 0x4b, 0x5a, 0xeb ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "subs x24, x25, x26, lsr #18"
+
+  -
+    input:
+      bytes: [ 0x9b, 0xff, 0x5d, 0xeb ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "subs x27, x28, x29, lsr #63"
+
+  -
+    input:
+      bytes: [ 0x62, 0x00, 0x84, 0xeb ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "subs x2, x3, x4, asr #0"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x54, 0x87, 0xeb ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "subs x5, x6, x7, asr #21"
+
+  -
+    input:
+      bytes: [ 0x28, 0xfd, 0x8a, 0xeb ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "subs x8, x9, x10, asr #63"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x00, 0x03, 0x2b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmn w0, w3"
+
+  -
+    input:
+      bytes: [ 0xff, 0x03, 0x04, 0x2b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmn wzr, w4"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x00, 0x1f, 0x2b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmn w5, wzr"
+
+  -
+    input:
+      bytes: [ 0xff, 0x43, 0x26, 0x2b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmn wsp, w6"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x00, 0x07, 0x2b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmn w6, w7"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x3d, 0x09, 0x2b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmn w8, w9, lsl #15"
+
+  -
+    input:
+      bytes: [ 0x5f, 0x7d, 0x0b, 0x2b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmn w10, w11, lsl #31"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x01, 0x4d, 0x2b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmn w12, w13, lsr #0"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x55, 0x4f, 0x2b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmn w14, w15, lsr #21"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x7e, 0x51, 0x2b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmn w16, w17, lsr #31"
+
+  -
+    input:
+      bytes: [ 0x5f, 0x02, 0x93, 0x2b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmn w18, w19, asr #0"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x5a, 0x95, 0x2b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmn w20, w21, asr #22"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x7e, 0x97, 0x2b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmn w22, w23, asr #31"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x00, 0x03, 0xab ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmn x0, x3"
+
+  -
+    input:
+      bytes: [ 0xff, 0x03, 0x04, 0xab ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmn xzr, x4"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x00, 0x1f, 0xab ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmn x5, xzr"
+
+  -
+    input:
+      bytes: [ 0xff, 0x63, 0x26, 0xab ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmn sp, x6"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x00, 0x07, 0xab ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmn x6, x7"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x3d, 0x09, 0xab ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmn x8, x9, lsl #15"
+
+  -
+    input:
+      bytes: [ 0x5f, 0xfd, 0x0b, 0xab ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmn x10, x11, lsl #63"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x01, 0x4d, 0xab ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmn x12, x13, lsr #0"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xa5, 0x4f, 0xab ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmn x14, x15, lsr #41"
+
+  -
+    input:
+      bytes: [ 0x1f, 0xfe, 0x51, 0xab ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmn x16, x17, lsr #63"
+
+  -
+    input:
+      bytes: [ 0x5f, 0x02, 0x93, 0xab ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmn x18, x19, asr #0"
+
+  -
+    input:
+      bytes: [ 0x9f, 0xde, 0x95, 0xab ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmn x20, x21, asr #55"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xfe, 0x97, 0xab ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmn x22, x23, asr #63"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x00, 0x03, 0x6b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmp w0, w3"
+
+  -
+    input:
+      bytes: [ 0xff, 0x03, 0x04, 0x6b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmp wzr, w4"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x00, 0x1f, 0x6b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmp w5, wzr"
+
+  -
+    input:
+      bytes: [ 0xff, 0x43, 0x26, 0x6b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmp wsp, w6"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x00, 0x07, 0x6b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmp w6, w7"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x3d, 0x09, 0x6b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmp w8, w9, lsl #15"
+
+  -
+    input:
+      bytes: [ 0x5f, 0x7d, 0x0b, 0x6b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmp w10, w11, lsl #31"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x01, 0x4d, 0x6b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmp w12, w13, lsr #0"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x55, 0x4f, 0x6b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmp w14, w15, lsr #21"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x7e, 0x51, 0x6b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmp w16, w17, lsr #31"
+
+  -
+    input:
+      bytes: [ 0x5f, 0x02, 0x93, 0x6b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmp w18, w19, asr #0"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x5a, 0x95, 0x6b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmp w20, w21, asr #22"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x7e, 0x97, 0x6b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmp w22, w23, asr #31"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x00, 0x03, 0xeb ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmp x0, x3"
+
+  -
+    input:
+      bytes: [ 0xff, 0x03, 0x04, 0xeb ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmp xzr, x4"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x00, 0x1f, 0xeb ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmp x5, xzr"
+
+  -
+    input:
+      bytes: [ 0xff, 0x63, 0x26, 0xeb ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmp sp, x6"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x00, 0x07, 0xeb ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmp x6, x7"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x3d, 0x09, 0xeb ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmp x8, x9, lsl #15"
+
+  -
+    input:
+      bytes: [ 0x5f, 0xfd, 0x0b, 0xeb ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmp x10, x11, lsl #63"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x01, 0x4d, 0xeb ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmp x12, x13, lsr #0"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xa5, 0x4f, 0xeb ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmp x14, x15, lsr #41"
+
+  -
+    input:
+      bytes: [ 0x1f, 0xfe, 0x51, 0xeb ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmp x16, x17, lsr #63"
+
+  -
+    input:
+      bytes: [ 0x5f, 0x02, 0x93, 0xeb ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmp x18, x19, asr #0"
+
+  -
+    input:
+      bytes: [ 0x9f, 0xde, 0x95, 0xeb ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmp x20, x21, asr #55"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xfe, 0x97, 0xeb ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmp x22, x23, asr #63"
+
+  -
+    input:
+      bytes: [ 0xfd, 0x03, 0x1e, 0x4b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "neg w29, w30"
+
+  -
+    input:
+      bytes: [ 0xfe, 0x03, 0x1f, 0x4b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "neg w30, wzr"
+
+  -
+    input:
+      bytes: [ 0xff, 0x03, 0x00, 0x4b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "neg wzr, w0"
+
+  -
+    input:
+      bytes: [ 0xfc, 0x03, 0x1b, 0x4b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "neg w28, w27"
+
+  -
+    input:
+      bytes: [ 0xfa, 0x77, 0x19, 0x4b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "neg w26, w25, lsl #29"
+
+  -
+    input:
+      bytes: [ 0xf8, 0x7f, 0x17, 0x4b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "neg w24, w23, lsl #31"
+
+  -
+    input:
+      bytes: [ 0xf6, 0x03, 0x55, 0x4b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "neg w22, w21, lsr #0"
+
+  -
+    input:
+      bytes: [ 0xf4, 0x07, 0x53, 0x4b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "neg w20, w19, lsr #1"
+
+  -
+    input:
+      bytes: [ 0xf2, 0x7f, 0x51, 0x4b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "neg w18, w17, lsr #31"
+
+  -
+    input:
+      bytes: [ 0xf0, 0x03, 0x8f, 0x4b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "neg w16, w15, asr #0"
+
+  -
+    input:
+      bytes: [ 0xee, 0x33, 0x8d, 0x4b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "neg w14, w13, asr #12"
+
+  -
+    input:
+      bytes: [ 0xec, 0x7f, 0x8b, 0x4b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "neg w12, w11, asr #31"
+
+  -
+    input:
+      bytes: [ 0xfd, 0x03, 0x1e, 0xcb ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "neg x29, x30"
+
+  -
+    input:
+      bytes: [ 0xfe, 0x03, 0x1f, 0xcb ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "neg x30, xzr"
+
+  -
+    input:
+      bytes: [ 0xff, 0x03, 0x00, 0xcb ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "neg xzr, x0"
+
+  -
+    input:
+      bytes: [ 0xfc, 0x03, 0x1b, 0xcb ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "neg x28, x27"
+
+  -
+    input:
+      bytes: [ 0xfa, 0x77, 0x19, 0xcb ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "neg x26, x25, lsl #29"
+
+  -
+    input:
+      bytes: [ 0xf8, 0x7f, 0x17, 0xcb ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "neg x24, x23, lsl #31"
+
+  -
+    input:
+      bytes: [ 0xf6, 0x03, 0x55, 0xcb ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "neg x22, x21, lsr #0"
+
+  -
+    input:
+      bytes: [ 0xf4, 0x07, 0x53, 0xcb ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "neg x20, x19, lsr #1"
+
+  -
+    input:
+      bytes: [ 0xf2, 0x7f, 0x51, 0xcb ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "neg x18, x17, lsr #31"
+
+  -
+    input:
+      bytes: [ 0xf0, 0x03, 0x8f, 0xcb ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "neg x16, x15, asr #0"
+
+  -
+    input:
+      bytes: [ 0xee, 0x33, 0x8d, 0xcb ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "neg x14, x13, asr #12"
+
+  -
+    input:
+      bytes: [ 0xec, 0x7f, 0x8b, 0xcb ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "neg x12, x11, asr #31"
+
+  -
+    input:
+      bytes: [ 0xfd, 0x03, 0x1e, 0x6b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "negs w29, w30"
+
+  -
+    input:
+      bytes: [ 0xfe, 0x03, 0x1f, 0x6b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "negs w30, wzr"
+
+  -
+    input:
+      bytes: [ 0xff, 0x03, 0x00, 0x6b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmp wzr, w0"
+
+  -
+    input:
+      bytes: [ 0xfc, 0x03, 0x1b, 0x6b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "negs w28, w27"
+
+  -
+    input:
+      bytes: [ 0xfa, 0x77, 0x19, 0x6b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "negs w26, w25, lsl #29"
+
+  -
+    input:
+      bytes: [ 0xf8, 0x7f, 0x17, 0x6b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "negs w24, w23, lsl #31"
+
+  -
+    input:
+      bytes: [ 0xf6, 0x03, 0x55, 0x6b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "negs w22, w21, lsr #0"
+
+  -
+    input:
+      bytes: [ 0xf4, 0x07, 0x53, 0x6b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "negs w20, w19, lsr #1"
+
+  -
+    input:
+      bytes: [ 0xf2, 0x7f, 0x51, 0x6b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "negs w18, w17, lsr #31"
+
+  -
+    input:
+      bytes: [ 0xf0, 0x03, 0x8f, 0x6b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "negs w16, w15, asr #0"
+
+  -
+    input:
+      bytes: [ 0xee, 0x33, 0x8d, 0x6b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "negs w14, w13, asr #12"
+
+  -
+    input:
+      bytes: [ 0xec, 0x7f, 0x8b, 0x6b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "negs w12, w11, asr #31"
+
+  -
+    input:
+      bytes: [ 0xfd, 0x03, 0x1e, 0xeb ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "negs x29, x30"
+
+  -
+    input:
+      bytes: [ 0xfe, 0x03, 0x1f, 0xeb ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "negs x30, xzr"
+
+  -
+    input:
+      bytes: [ 0xff, 0x03, 0x00, 0xeb ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmp xzr, x0"
+
+  -
+    input:
+      bytes: [ 0xfc, 0x03, 0x1b, 0xeb ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "negs x28, x27"
+
+  -
+    input:
+      bytes: [ 0xfa, 0x77, 0x19, 0xeb ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "negs x26, x25, lsl #29"
+
+  -
+    input:
+      bytes: [ 0xf8, 0x7f, 0x17, 0xeb ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "negs x24, x23, lsl #31"
+
+  -
+    input:
+      bytes: [ 0xf6, 0x03, 0x55, 0xeb ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "negs x22, x21, lsr #0"
+
+  -
+    input:
+      bytes: [ 0xf4, 0x07, 0x53, 0xeb ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "negs x20, x19, lsr #1"
+
+  -
+    input:
+      bytes: [ 0xf2, 0x7f, 0x51, 0xeb ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "negs x18, x17, lsr #31"
+
+  -
+    input:
+      bytes: [ 0xf0, 0x03, 0x8f, 0xeb ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "negs x16, x15, asr #0"
+
+  -
+    input:
+      bytes: [ 0xee, 0x33, 0x8d, 0xeb ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "negs x14, x13, asr #12"
+
+  -
+    input:
+      bytes: [ 0xec, 0x7f, 0x8b, 0xeb ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "negs x12, x11, asr #31"
+
+  -
+    input:
+      bytes: [ 0x7d, 0x03, 0x19, 0x1a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "adc w29, w27, w25"
+
+  -
+    input:
+      bytes: [ 0x7f, 0x00, 0x04, 0x1a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "adc wzr, w3, w4"
+
+  -
+    input:
+      bytes: [ 0xe9, 0x03, 0x0a, 0x1a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "adc w9, wzr, w10"
+
+  -
+    input:
+      bytes: [ 0x14, 0x00, 0x1f, 0x1a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "adc w20, w0, wzr"
+
+  -
+    input:
+      bytes: [ 0x7d, 0x03, 0x19, 0x9a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "adc x29, x27, x25"
+
+  -
+    input:
+      bytes: [ 0x7f, 0x00, 0x04, 0x9a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "adc xzr, x3, x4"
+
+  -
+    input:
+      bytes: [ 0xe9, 0x03, 0x0a, 0x9a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "adc x9, xzr, x10"
+
+  -
+    input:
+      bytes: [ 0x14, 0x00, 0x1f, 0x9a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "adc x20, x0, xzr"
+
+  -
+    input:
+      bytes: [ 0x7d, 0x03, 0x19, 0x3a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "adcs w29, w27, w25"
+
+  -
+    input:
+      bytes: [ 0x7f, 0x00, 0x04, 0x3a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "adcs wzr, w3, w4"
+
+  -
+    input:
+      bytes: [ 0xe9, 0x03, 0x0a, 0x3a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "adcs w9, wzr, w10"
+
+  -
+    input:
+      bytes: [ 0x14, 0x00, 0x1f, 0x3a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "adcs w20, w0, wzr"
+
+  -
+    input:
+      bytes: [ 0x7d, 0x03, 0x19, 0xba ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "adcs x29, x27, x25"
+
+  -
+    input:
+      bytes: [ 0x7f, 0x00, 0x04, 0xba ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "adcs xzr, x3, x4"
+
+  -
+    input:
+      bytes: [ 0xe9, 0x03, 0x0a, 0xba ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "adcs x9, xzr, x10"
+
+  -
+    input:
+      bytes: [ 0x14, 0x00, 0x1f, 0xba ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "adcs x20, x0, xzr"
+
+  -
+    input:
+      bytes: [ 0x7d, 0x03, 0x19, 0x5a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "sbc w29, w27, w25"
+
+  -
+    input:
+      bytes: [ 0x7f, 0x00, 0x04, 0x5a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "sbc wzr, w3, w4"
+
+  -
+    input:
+      bytes: [ 0xe9, 0x03, 0x0a, 0x5a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ngc w9, w10"
+
+  -
+    input:
+      bytes: [ 0x14, 0x00, 0x1f, 0x5a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "sbc w20, w0, wzr"
+
+  -
+    input:
+      bytes: [ 0x7d, 0x03, 0x19, 0xda ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "sbc x29, x27, x25"
+
+  -
+    input:
+      bytes: [ 0x7f, 0x00, 0x04, 0xda ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "sbc xzr, x3, x4"
+
+  -
+    input:
+      bytes: [ 0xe9, 0x03, 0x0a, 0xda ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ngc x9, x10"
+
+  -
+    input:
+      bytes: [ 0x14, 0x00, 0x1f, 0xda ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "sbc x20, x0, xzr"
+
+  -
+    input:
+      bytes: [ 0x7d, 0x03, 0x19, 0x7a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "sbcs w29, w27, w25"
+
+  -
+    input:
+      bytes: [ 0x7f, 0x00, 0x04, 0x7a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "sbcs wzr, w3, w4"
+
+  -
+    input:
+      bytes: [ 0xe9, 0x03, 0x0a, 0x7a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ngcs w9, w10"
+
+  -
+    input:
+      bytes: [ 0x14, 0x00, 0x1f, 0x7a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "sbcs w20, w0, wzr"
+
+  -
+    input:
+      bytes: [ 0x7d, 0x03, 0x19, 0xfa ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "sbcs x29, x27, x25"
+
+  -
+    input:
+      bytes: [ 0x7f, 0x00, 0x04, 0xfa ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "sbcs xzr, x3, x4"
+
+  -
+    input:
+      bytes: [ 0xe9, 0x03, 0x0a, 0xfa ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ngcs x9, x10"
+
+  -
+    input:
+      bytes: [ 0x14, 0x00, 0x1f, 0xfa ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "sbcs x20, x0, xzr"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x03, 0x0c, 0x5a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ngc w3, w12"
+
+  -
+    input:
+      bytes: [ 0xff, 0x03, 0x09, 0x5a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ngc wzr, w9"
+
+  -
+    input:
+      bytes: [ 0xf7, 0x03, 0x1f, 0x5a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ngc w23, wzr"
+
+  -
+    input:
+      bytes: [ 0xfd, 0x03, 0x1e, 0xda ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ngc x29, x30"
+
+  -
+    input:
+      bytes: [ 0xff, 0x03, 0x00, 0xda ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ngc xzr, x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x03, 0x1f, 0xda ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ngc x0, xzr"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x03, 0x0c, 0x7a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ngcs w3, w12"
+
+  -
+    input:
+      bytes: [ 0xff, 0x03, 0x09, 0x7a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ngcs wzr, w9"
+
+  -
+    input:
+      bytes: [ 0xf7, 0x03, 0x1f, 0x7a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ngcs w23, wzr"
+
+  -
+    input:
+      bytes: [ 0xfd, 0x03, 0x1e, 0xfa ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ngcs x29, x30"
+
+  -
+    input:
+      bytes: [ 0xff, 0x03, 0x00, 0xfa ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ngcs xzr, x0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x03, 0x1f, 0xfa ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ngcs x0, xzr"
+
+  -
+    input:
+      bytes: [ 0x41, 0x10, 0x43, 0x93 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "sbfx x1, x2, #3, #2"
+
+  -
+    input:
+      bytes: [ 0x83, 0xfc, 0x7f, 0x93 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "asr x3, x4, #63"
+
+  -
+    input:
+      bytes: [ 0xff, 0x7f, 0x1f, 0x13 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "asr wzr, wzr, #31"
+
+  -
+    input:
+      bytes: [ 0x2c, 0x01, 0x00, 0x13 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "sbfx w12, w9, #0, #1"
+
+  -
+    input:
+      bytes: [ 0xa4, 0x28, 0x4c, 0xd3 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ubfiz x4, x5, #52, #11"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x00, 0x40, 0xd3 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ubfx xzr, x4, #0, #1"
+
+  -
+    input:
+      bytes: [ 0xe4, 0x17, 0x7f, 0xd3 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ubfiz x4, xzr, #1, #6"
+
+  -
+    input:
+      bytes: [ 0xc5, 0xfc, 0x4c, 0xd3 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsr x5, x6, #12"
+
+  -
+    input:
+      bytes: [ 0xa4, 0x28, 0x4c, 0xb3 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfi x4, x5, #52, #11"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x00, 0x40, 0xb3 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfxil xzr, x4, #0, #1"
+
+  -
+    input:
+      bytes: [ 0xe4, 0x17, 0x7f, 0xb3 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfi x4, xzr, #1, #6"
+    skip: true
+    skip_reason: "Requires to disable the HasV8_2aOps feature. Which is not possible without adding unnecessary bloat."
+
+  -
+    input:
+      bytes: [ 0xc5, 0xfc, 0x4c, 0xb3 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfxil x5, x6, #12, #52"
+
+  -
+    input:
+      bytes: [ 0x41, 0x1c, 0x00, 0x13 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "sxtb w1, w2"
+
+  -
+    input:
+      bytes: [ 0x7f, 0x1c, 0x40, 0x93 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "sxtb xzr, w3"
+
+  -
+    input:
+      bytes: [ 0x49, 0x3d, 0x00, 0x13 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "sxth w9, w10"
+
+  -
+    input:
+      bytes: [ 0x20, 0x3c, 0x40, 0x93 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "sxth x0, w1"
+
+  -
+    input:
+      bytes: [ 0xc3, 0x7f, 0x40, 0x93 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "sxtw x3, w30"
+
+  -
+    input:
+      bytes: [ 0x41, 0x1c, 0x00, 0x53 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "uxtb w1, w2"
+
+  -
+    input:
+      bytes: [ 0x7f, 0x1c, 0x00, 0x53 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "uxtb wzr, w3"
+
+  -
+    input:
+      bytes: [ 0x49, 0x3d, 0x00, 0x53 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "uxth w9, w10"
+
+  -
+    input:
+      bytes: [ 0x20, 0x3c, 0x00, 0x53 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "uxth w0, w1"
+
+  -
+    input:
+      bytes: [ 0x43, 0x7c, 0x00, 0x13 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "asr w3, w2, #0"
+
+  -
+    input:
+      bytes: [ 0x49, 0x7d, 0x1f, 0x13 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "asr w9, w10, #31"
+
+  -
+    input:
+      bytes: [ 0xb4, 0xfe, 0x7f, 0x93 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "asr x20, x21, #63"
+
+  -
+    input:
+      bytes: [ 0xe1, 0x7f, 0x03, 0x13 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "asr w1, wzr, #3"
+
+  -
+    input:
+      bytes: [ 0x43, 0x7c, 0x00, 0x53 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsr w3, w2, #0"
+
+  -
+    input:
+      bytes: [ 0x49, 0x7d, 0x1f, 0x53 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsr w9, w10, #31"
+
+  -
+    input:
+      bytes: [ 0xb4, 0xfe, 0x7f, 0xd3 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsr x20, x21, #63"
+
+  -
+    input:
+      bytes: [ 0xff, 0x7f, 0x03, 0x53 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsr wzr, wzr, #3"
+
+  -
+    input:
+      bytes: [ 0x43, 0x7c, 0x00, 0x53 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsr w3, w2, #0"
+
+  -
+    input:
+      bytes: [ 0x49, 0x01, 0x01, 0x53 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsl w9, w10, #31"
+
+  -
+    input:
+      bytes: [ 0xb4, 0x02, 0x41, 0xd3 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsl x20, x21, #63"
+
+  -
+    input:
+      bytes: [ 0xe1, 0x73, 0x1d, 0x53 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsl w1, wzr, #3"
+
+  -
+    input:
+      bytes: [ 0x49, 0x01, 0x00, 0x13 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "sbfx w9, w10, #0, #1"
+
+  -
+    input:
+      bytes: [ 0x62, 0x00, 0x41, 0x93 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "sbfiz x2, x3, #63, #1"
+
+  -
+    input:
+      bytes: [ 0x93, 0xfe, 0x40, 0x93 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "asr x19, x20, #0"
+
+  -
+    input:
+      bytes: [ 0x49, 0xe9, 0x7b, 0x93 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "sbfiz x9, x10, #5, #59"
+
+  -
+    input:
+      bytes: [ 0x49, 0x7d, 0x00, 0x13 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "asr w9, w10, #0"
+
+  -
+    input:
+      bytes: [ 0x8b, 0x01, 0x01, 0x13 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "sbfiz w11, w12, #31, #1"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x09, 0x03, 0x13 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "sbfiz w13, w14, #29, #3"
+
+  -
+    input:
+      bytes: [ 0xff, 0x2b, 0x76, 0x93 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "sbfiz xzr, xzr, #10, #11"
+
+  -
+    input:
+      bytes: [ 0x49, 0x01, 0x00, 0x13 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "sbfx w9, w10, #0, #1"
+
+  -
+    input:
+      bytes: [ 0x62, 0xfc, 0x7f, 0x93 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "asr x2, x3, #63"
+
+  -
+    input:
+      bytes: [ 0x93, 0xfe, 0x40, 0x93 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "asr x19, x20, #0"
+
+  -
+    input:
+      bytes: [ 0x49, 0xfd, 0x45, 0x93 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "asr x9, x10, #5"
+
+  -
+    input:
+      bytes: [ 0x49, 0x7d, 0x00, 0x13 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "asr w9, w10, #0"
+
+  -
+    input:
+      bytes: [ 0x8b, 0x7d, 0x1f, 0x13 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "asr w11, w12, #31"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x7d, 0x1d, 0x13 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "asr w13, w14, #29"
+
+  -
+    input:
+      bytes: [ 0xff, 0x53, 0x4a, 0x93 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "sbfx xzr, xzr, #10, #11"
+
+  -
+    input:
+      bytes: [ 0x49, 0x01, 0x00, 0x33 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfxil w9, w10, #0, #1"
+
+  -
+    input:
+      bytes: [ 0x62, 0x00, 0x41, 0xb3 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfi x2, x3, #63, #1"
+
+  -
+    input:
+      bytes: [ 0x93, 0xfe, 0x40, 0xb3 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfxil x19, x20, #0, #64"
+
+  -
+    input:
+      bytes: [ 0x49, 0xe9, 0x7b, 0xb3 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfi x9, x10, #5, #59"
+
+  -
+    input:
+      bytes: [ 0x49, 0x7d, 0x00, 0x33 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfxil w9, w10, #0, #32"
+
+  -
+    input:
+      bytes: [ 0x8b, 0x01, 0x01, 0x33 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfi w11, w12, #31, #1"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x09, 0x03, 0x33 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfi w13, w14, #29, #3"
+
+  -
+    input:
+      bytes: [ 0xff, 0x2b, 0x76, 0xb3 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfi xzr, xzr, #10, #11"
+    skip: true
+    skip_reason: "Requires to disable the HasV8_2aOps feature. Which is not possible without adding unnecessary bloat."
+
+  -
+    input:
+      bytes: [ 0x49, 0x01, 0x00, 0x33 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfxil w9, w10, #0, #1"
+
+  -
+    input:
+      bytes: [ 0x62, 0xfc, 0x7f, 0xb3 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfxil x2, x3, #63, #1"
+
+  -
+    input:
+      bytes: [ 0x93, 0xfe, 0x40, 0xb3 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfxil x19, x20, #0, #64"
+
+  -
+    input:
+      bytes: [ 0x49, 0xfd, 0x45, 0xb3 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfxil x9, x10, #5, #59"
+
+  -
+    input:
+      bytes: [ 0x49, 0x7d, 0x00, 0x33 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfxil w9, w10, #0, #32"
+
+  -
+    input:
+      bytes: [ 0x8b, 0x7d, 0x1f, 0x33 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfxil w11, w12, #31, #1"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x7d, 0x1d, 0x33 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfxil w13, w14, #29, #3"
+
+  -
+    input:
+      bytes: [ 0xff, 0x53, 0x4a, 0xb3 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfxil xzr, xzr, #10, #11"
+
+  -
+    input:
+      bytes: [ 0x49, 0x01, 0x00, 0x53 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ubfx w9, w10, #0, #1"
+
+  -
+    input:
+      bytes: [ 0x62, 0x00, 0x41, 0xd3 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsl x2, x3, #63"
+
+  -
+    input:
+      bytes: [ 0x93, 0xfe, 0x40, 0xd3 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsr x19, x20, #0"
+
+  -
+    input:
+      bytes: [ 0x49, 0xe9, 0x7b, 0xd3 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsl x9, x10, #5"
+
+  -
+    input:
+      bytes: [ 0x49, 0x7d, 0x00, 0x53 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsr w9, w10, #0"
+
+  -
+    input:
+      bytes: [ 0x8b, 0x01, 0x01, 0x53 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsl w11, w12, #31"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x09, 0x03, 0x53 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsl w13, w14, #29"
+
+  -
+    input:
+      bytes: [ 0xff, 0x2b, 0x76, 0xd3 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ubfiz xzr, xzr, #10, #11"
+
+  -
+    input:
+      bytes: [ 0x49, 0x01, 0x00, 0x53 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ubfx w9, w10, #0, #1"
+
+  -
+    input:
+      bytes: [ 0x62, 0xfc, 0x7f, 0xd3 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsr x2, x3, #63"
+
+  -
+    input:
+      bytes: [ 0x93, 0xfe, 0x40, 0xd3 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsr x19, x20, #0"
+
+  -
+    input:
+      bytes: [ 0x49, 0xfd, 0x45, 0xd3 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsr x9, x10, #5"
+
+  -
+    input:
+      bytes: [ 0x49, 0x7d, 0x00, 0x53 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsr w9, w10, #0"
+
+  -
+    input:
+      bytes: [ 0x8b, 0x7d, 0x1f, 0x53 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsr w11, w12, #31"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x7d, 0x1d, 0x53 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsr w13, w14, #29"
+
+  -
+    input:
+      bytes: [ 0xff, 0x53, 0x4a, 0xd3 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ubfx xzr, xzr, #10, #11"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x7f, 0x00, 0x33 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfxil w3, wzr, #0, #32"
+    skip: true
+    skip_reason: "Requires to disable the HasV8_2aOps feature. Which is not possible without adding unnecessary bloat."
+
+  -
+    input:
+      bytes: [ 0xff, 0x03, 0x01, 0x33 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfi wzr, wzr, #31, #1"
+    skip: true
+    skip_reason: "Requires to disable the HasV8_2aOps feature. Which is not possible without adding unnecessary bloat."
+
+  -
+    input:
+      bytes: [ 0xe0, 0x23, 0x7b, 0xb3 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfi x0, xzr, #5, #9"
+    skip: true
+    skip_reason: "Requires to disable the HasV8_2aOps feature. Which is not possible without adding unnecessary bloat."
+
+  -
+    input:
+      bytes: [ 0xff, 0x03, 0x41, 0xb3 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfi xzr, xzr, #63, #1"
+    skip: true
+    skip_reason: "Requires to disable the HasV8_2aOps feature. Which is not possible without adding unnecessary bloat."
+
+  -
+    input:
+      bytes: [ 0x05, 0x00, 0x00, 0x34 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cbz w5, #0"
+
+  -
+    input:
+      bytes: [ 0xe3, 0xff, 0xff, 0xb5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cbnz x3, #-4"
+
+  -
+    input:
+      bytes: [ 0xf4, 0xff, 0x7f, 0x34 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cbz w20, #1048572"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x00, 0x80, 0xb5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cbnz xzr, #-1048576"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x00, 0x54 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "b.eq #0"
+
+  -
+    input:
+      bytes: [ 0xeb, 0xff, 0xff, 0x54 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "b.lt #-4"
+
+  -
+    input:
+      bytes: [ 0xe3, 0xff, 0x7f, 0x54 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "b.lo #1048572"
+
+  -
+    input:
+      bytes: [ 0x20, 0x08, 0x5f, 0x7a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ccmp w1, #31, #0, eq"
+
+  -
+    input:
+      bytes: [ 0x6f, 0x28, 0x40, 0x7a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ccmp w3, #0, #15, hs"
+
+  -
+    input:
+      bytes: [ 0xed, 0x2b, 0x4f, 0x7a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ccmp wzr, #15, #13, hs"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd9, 0x5f, 0xfa ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ccmp x9, #31, #0, le"
+
+  -
+    input:
+      bytes: [ 0x6f, 0xc8, 0x40, 0xfa ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ccmp x3, #0, #15, gt"
+
+  -
+    input:
+      bytes: [ 0xe7, 0x1b, 0x45, 0xfa ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ccmp xzr, #5, #7, ne"
+
+  -
+    input:
+      bytes: [ 0x20, 0x08, 0x5f, 0x3a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ccmn w1, #31, #0, eq"
+
+  -
+    input:
+      bytes: [ 0x6f, 0x28, 0x40, 0x3a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ccmn w3, #0, #15, hs"
+
+  -
+    input:
+      bytes: [ 0xed, 0x2b, 0x4f, 0x3a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ccmn wzr, #15, #13, hs"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd9, 0x5f, 0xba ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ccmn x9, #31, #0, le"
+
+  -
+    input:
+      bytes: [ 0x6f, 0xc8, 0x40, 0xba ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ccmn x3, #0, #15, gt"
+
+  -
+    input:
+      bytes: [ 0xe7, 0x1b, 0x45, 0xba ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ccmn xzr, #5, #7, ne"
+
+  -
+    input:
+      bytes: [ 0x20, 0x00, 0x5f, 0x7a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ccmp w1, wzr, #0, eq"
+
+  -
+    input:
+      bytes: [ 0x6f, 0x20, 0x40, 0x7a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ccmp w3, w0, #15, hs"
+
+  -
+    input:
+      bytes: [ 0xed, 0x23, 0x4f, 0x7a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ccmp wzr, w15, #13, hs"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd1, 0x5f, 0xfa ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ccmp x9, xzr, #0, le"
+
+  -
+    input:
+      bytes: [ 0x6f, 0xc0, 0x40, 0xfa ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ccmp x3, x0, #15, gt"
+
+  -
+    input:
+      bytes: [ 0xe7, 0x13, 0x45, 0xfa ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ccmp xzr, x5, #7, ne"
+
+  -
+    input:
+      bytes: [ 0x20, 0x00, 0x5f, 0x3a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ccmn w1, wzr, #0, eq"
+
+  -
+    input:
+      bytes: [ 0x6f, 0x20, 0x40, 0x3a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ccmn w3, w0, #15, hs"
+
+  -
+    input:
+      bytes: [ 0xed, 0x23, 0x4f, 0x3a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ccmn wzr, w15, #13, hs"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd1, 0x5f, 0xba ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ccmn x9, xzr, #0, le"
+
+  -
+    input:
+      bytes: [ 0x6f, 0xc0, 0x40, 0xba ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ccmn x3, x0, #15, gt"
+
+  -
+    input:
+      bytes: [ 0xe7, 0x13, 0x45, 0xba ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ccmn xzr, x5, #7, ne"
+
+  -
+    input:
+      bytes: [ 0x01, 0x10, 0x93, 0x1a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "csel w1, w0, w19, ne"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x00, 0x89, 0x1a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "csel wzr, w5, w9, eq"
+
+  -
+    input:
+      bytes: [ 0xe9, 0xc3, 0x9e, 0x1a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "csel w9, wzr, w30, gt"
+
+  -
+    input:
+      bytes: [ 0x81, 0x43, 0x9f, 0x1a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "csel w1, w28, wzr, mi"
+
+  -
+    input:
+      bytes: [ 0xf3, 0xb2, 0x9d, 0x9a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "csel x19, x23, x29, lt"
+
+  -
+    input:
+      bytes: [ 0x7f, 0xa0, 0x84, 0x9a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "csel xzr, x3, x4, ge"
+
+  -
+    input:
+      bytes: [ 0xe5, 0x23, 0x86, 0x9a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "csel x5, xzr, x6, hs"
+
+  -
+    input:
+      bytes: [ 0x07, 0x31, 0x9f, 0x9a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "csel x7, x8, xzr, lo"
+
+  -
+    input:
+      bytes: [ 0x01, 0x14, 0x93, 0x1a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "csinc w1, w0, w19, ne"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x04, 0x89, 0x1a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "csinc wzr, w5, w9, eq"
+
+  -
+    input:
+      bytes: [ 0xe9, 0xc7, 0x9e, 0x1a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "csinc w9, wzr, w30, gt"
+
+  -
+    input:
+      bytes: [ 0x81, 0x47, 0x9f, 0x1a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "csinc w1, w28, wzr, mi"
+
+  -
+    input:
+      bytes: [ 0xf3, 0xb6, 0x9d, 0x9a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "csinc x19, x23, x29, lt"
+
+  -
+    input:
+      bytes: [ 0x7f, 0xa4, 0x84, 0x9a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "csinc xzr, x3, x4, ge"
+
+  -
+    input:
+      bytes: [ 0xe5, 0x27, 0x86, 0x9a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "csinc x5, xzr, x6, hs"
+
+  -
+    input:
+      bytes: [ 0x07, 0x35, 0x9f, 0x9a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "csinc x7, x8, xzr, lo"
+
+  -
+    input:
+      bytes: [ 0x01, 0x10, 0x93, 0x5a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "csinv w1, w0, w19, ne"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x00, 0x89, 0x5a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "csinv wzr, w5, w9, eq"
+
+  -
+    input:
+      bytes: [ 0xe9, 0xc3, 0x9e, 0x5a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "csinv w9, wzr, w30, gt"
+
+  -
+    input:
+      bytes: [ 0x81, 0x43, 0x9f, 0x5a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "csinv w1, w28, wzr, mi"
+
+  -
+    input:
+      bytes: [ 0xf3, 0xb2, 0x9d, 0xda ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "csinv x19, x23, x29, lt"
+
+  -
+    input:
+      bytes: [ 0x7f, 0xa0, 0x84, 0xda ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "csinv xzr, x3, x4, ge"
+
+  -
+    input:
+      bytes: [ 0xe5, 0x23, 0x86, 0xda ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "csinv x5, xzr, x6, hs"
+
+  -
+    input:
+      bytes: [ 0x07, 0x31, 0x9f, 0xda ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "csinv x7, x8, xzr, lo"
+
+  -
+    input:
+      bytes: [ 0x01, 0x14, 0x93, 0x5a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "csneg w1, w0, w19, ne"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x04, 0x89, 0x5a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "csneg wzr, w5, w9, eq"
+
+  -
+    input:
+      bytes: [ 0xe9, 0xc7, 0x9e, 0x5a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "csneg w9, wzr, w30, gt"
+
+  -
+    input:
+      bytes: [ 0x81, 0x47, 0x9f, 0x5a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "csneg w1, w28, wzr, mi"
+
+  -
+    input:
+      bytes: [ 0xf3, 0xb6, 0x9d, 0xda ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "csneg x19, x23, x29, lt"
+
+  -
+    input:
+      bytes: [ 0x7f, 0xa4, 0x84, 0xda ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "csneg xzr, x3, x4, ge"
+
+  -
+    input:
+      bytes: [ 0xe5, 0x27, 0x86, 0xda ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "csneg x5, xzr, x6, hs"
+
+  -
+    input:
+      bytes: [ 0x07, 0x35, 0x9f, 0xda ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "csneg x7, x8, xzr, lo"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x17, 0x9f, 0x1a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cset w3, eq"
+
+  -
+    input:
+      bytes: [ 0xe9, 0x47, 0x9f, 0x9a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cset x9, pl"
+
+  -
+    input:
+      bytes: [ 0xf4, 0x03, 0x9f, 0x5a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "csetm w20, ne"
+
+  -
+    input:
+      bytes: [ 0xfe, 0xb3, 0x9f, 0xda ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "csetm x30, ge"
+
+  -
+    input:
+      bytes: [ 0xa3, 0xd4, 0x85, 0x1a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cinc w3, w5, gt"
+
+  -
+    input:
+      bytes: [ 0x9f, 0xc4, 0x84, 0x1a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cinc wzr, w4, le"
+
+  -
+    input:
+      bytes: [ 0xe9, 0xa7, 0x9f, 0x1a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cset w9, lt"
+
+  -
+    input:
+      bytes: [ 0xa3, 0xd4, 0x85, 0x9a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cinc x3, x5, gt"
+
+  -
+    input:
+      bytes: [ 0x9f, 0xc4, 0x84, 0x9a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cinc xzr, x4, le"
+
+  -
+    input:
+      bytes: [ 0xe9, 0xa7, 0x9f, 0x9a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cset x9, lt"
+
+  -
+    input:
+      bytes: [ 0xa3, 0xd0, 0x85, 0x5a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cinv w3, w5, gt"
+
+  -
+    input:
+      bytes: [ 0x9f, 0xc0, 0x84, 0x5a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cinv wzr, w4, le"
+
+  -
+    input:
+      bytes: [ 0xe9, 0xa3, 0x9f, 0x5a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "csetm w9, lt"
+
+  -
+    input:
+      bytes: [ 0xa3, 0xd0, 0x85, 0xda ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cinv x3, x5, gt"
+
+  -
+    input:
+      bytes: [ 0x9f, 0xc0, 0x84, 0xda ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cinv xzr, x4, le"
+
+  -
+    input:
+      bytes: [ 0xe9, 0xa3, 0x9f, 0xda ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "csetm x9, lt"
+
+  -
+    input:
+      bytes: [ 0xa3, 0xd4, 0x85, 0x5a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cneg w3, w5, gt"
+
+  -
+    input:
+      bytes: [ 0x9f, 0xc4, 0x84, 0x5a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cneg wzr, w4, le"
+
+  -
+    input:
+      bytes: [ 0xe9, 0xa7, 0x9f, 0x5a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cneg w9, wzr, lt"
+
+  -
+    input:
+      bytes: [ 0xa3, 0xd4, 0x85, 0xda ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cneg x3, x5, gt"
+
+  -
+    input:
+      bytes: [ 0x9f, 0xc4, 0x84, 0xda ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cneg xzr, x4, le"
+
+  -
+    input:
+      bytes: [ 0xe9, 0xa7, 0x9f, 0xda ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cneg x9, xzr, lt"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x00, 0xc0, 0x5a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "rbit w0, w7"
+
+  -
+    input:
+      bytes: [ 0x72, 0x00, 0xc0, 0xda ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "rbit x18, x3"
+
+  -
+    input:
+      bytes: [ 0x31, 0x04, 0xc0, 0x5a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "rev16 w17, w1"
+
+  -
+    input:
+      bytes: [ 0x45, 0x04, 0xc0, 0xda ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "rev16 x5, x2"
+
+  -
+    input:
+      bytes: [ 0x12, 0x08, 0xc0, 0x5a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "rev w18, w0"
+
+  -
+    input:
+      bytes: [ 0x34, 0x08, 0xc0, 0xda ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "rev32 x20, x1"
+
+  -
+    input:
+      bytes: [ 0xf4, 0x0b, 0xc0, 0xda ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "rev32 x20, xzr"
+
+  -
+    input:
+      bytes: [ 0x56, 0x0c, 0xc0, 0xda ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "rev x22, x2"
+
+  -
+    input:
+      bytes: [ 0xf2, 0x0f, 0xc0, 0xda ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "rev x18, xzr"
+
+  -
+    input:
+      bytes: [ 0xe7, 0x0b, 0xc0, 0x5a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "rev w7, wzr"
+
+  -
+    input:
+      bytes: [ 0x78, 0x10, 0xc0, 0x5a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "clz w24, w3"
+
+  -
+    input:
+      bytes: [ 0x9a, 0x10, 0xc0, 0xda ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "clz x26, x4"
+
+  -
+    input:
+      bytes: [ 0xa3, 0x14, 0xc0, 0x5a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cls w3, w5"
+
+  -
+    input:
+      bytes: [ 0xb4, 0x14, 0xc0, 0xda ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "cls x20, x5"
+
+  -
+    input:
+      bytes: [ 0xf8, 0x13, 0xc0, 0x5a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "clz w24, wzr"
+
+  -
+    input:
+      bytes: [ 0xf6, 0x0f, 0xc0, 0xda ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "rev x22, xzr"
+
+  -
+    input:
+      bytes: [ 0x8d, 0x0d, 0xc0, 0xda ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "rev x13, x12"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x08, 0xca, 0x1a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "udiv w0, w7, w10"
+
+  -
+    input:
+      bytes: [ 0xc9, 0x0a, 0xc4, 0x9a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "udiv x9, x22, x4"
+
+  -
+    input:
+      bytes: [ 0xac, 0x0e, 0xc0, 0x1a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdiv w12, w21, w0"
+
+  -
+    input:
+      bytes: [ 0x4d, 0x0c, 0xc1, 0x9a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdiv x13, x2, x1"
+
+  -
+    input:
+      bytes: [ 0x8b, 0x21, 0xcd, 0x1a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsl w11, w12, w13"
+
+  -
+    input:
+      bytes: [ 0xee, 0x21, 0xd0, 0x9a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsl x14, x15, x16"
+
+  -
+    input:
+      bytes: [ 0x51, 0x26, 0xd3, 0x1a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsr w17, w18, w19"
+
+  -
+    input:
+      bytes: [ 0xb4, 0x26, 0xd6, 0x9a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsr x20, x21, x22"
+
+  -
+    input:
+      bytes: [ 0x17, 0x2b, 0xd9, 0x1a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "asr w23, w24, w25"
+
+  -
+    input:
+      bytes: [ 0x7a, 0x2b, 0xdc, 0x9a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "asr x26, x27, x28"
+
+  -
+    input:
+      bytes: [ 0x20, 0x2c, 0xc2, 0x1a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ror w0, w1, w2"
+
+  -
+    input:
+      bytes: [ 0x83, 0x2c, 0xc5, 0x9a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ror x3, x4, x5"
+
+  -
+    input:
+      bytes: [ 0xe6, 0x20, 0xc8, 0x1a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsl w6, w7, w8"
+
+  -
+    input:
+      bytes: [ 0x49, 0x21, 0xcb, 0x9a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsl x9, x10, x11"
+
+  -
+    input:
+      bytes: [ 0xac, 0x25, 0xce, 0x1a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsr w12, w13, w14"
+
+  -
+    input:
+      bytes: [ 0x0f, 0x26, 0xd1, 0x9a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsr x15, x16, x17"
+
+  -
+    input:
+      bytes: [ 0x72, 0x2a, 0xd4, 0x1a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "asr w18, w19, w20"
+
+  -
+    input:
+      bytes: [ 0xd5, 0x2a, 0xd7, 0x9a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "asr x21, x22, x23"
+
+  -
+    input:
+      bytes: [ 0x38, 0x2f, 0xda, 0x1a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ror w24, w25, w26"
+
+  -
+    input:
+      bytes: [ 0x9b, 0x2f, 0xdd, 0x9a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ror x27, x28, x29"
+
+  -
+    input:
+      bytes: [ 0x61, 0x10, 0x07, 0x1b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd w1, w3, w7, w4"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x2c, 0x09, 0x1b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd wzr, w0, w9, w11"
+
+  -
+    input:
+      bytes: [ 0xed, 0x13, 0x04, 0x1b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd w13, wzr, w4, w4"
+
+  -
+    input:
+      bytes: [ 0xd3, 0x77, 0x1f, 0x1b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd w19, w30, wzr, w29"
+
+  -
+    input:
+      bytes: [ 0xa4, 0x7c, 0x06, 0x1b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul w4, w5, w6"
+
+  -
+    input:
+      bytes: [ 0x61, 0x10, 0x07, 0x9b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd x1, x3, x7, x4"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x2c, 0x09, 0x9b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd xzr, x0, x9, x11"
+
+  -
+    input:
+      bytes: [ 0xed, 0x13, 0x04, 0x9b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd x13, xzr, x4, x4"
+
+  -
+    input:
+      bytes: [ 0xd3, 0x77, 0x1f, 0x9b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd x19, x30, xzr, x29"
+
+  -
+    input:
+      bytes: [ 0xa4, 0x7c, 0x06, 0x9b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul x4, x5, x6"
+
+  -
+    input:
+      bytes: [ 0x61, 0x90, 0x07, 0x1b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub w1, w3, w7, w4"
+
+  -
+    input:
+      bytes: [ 0x1f, 0xac, 0x09, 0x1b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub wzr, w0, w9, w11"
+
+  -
+    input:
+      bytes: [ 0xed, 0x93, 0x04, 0x1b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub w13, wzr, w4, w4"
+
+  -
+    input:
+      bytes: [ 0xd3, 0xf7, 0x1f, 0x1b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub w19, w30, wzr, w29"
+
+  -
+    input:
+      bytes: [ 0xa4, 0xfc, 0x06, 0x1b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mneg w4, w5, w6"
+
+  -
+    input:
+      bytes: [ 0x61, 0x90, 0x07, 0x9b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub x1, x3, x7, x4"
+
+  -
+    input:
+      bytes: [ 0x1f, 0xac, 0x09, 0x9b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub xzr, x0, x9, x11"
+
+  -
+    input:
+      bytes: [ 0xed, 0x93, 0x04, 0x9b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub x13, xzr, x4, x4"
+
+  -
+    input:
+      bytes: [ 0xd3, 0xf7, 0x1f, 0x9b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub x19, x30, xzr, x29"
+
+  -
+    input:
+      bytes: [ 0xa4, 0xfc, 0x06, 0x9b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mneg x4, x5, x6"
+
+  -
+    input:
+      bytes: [ 0xa3, 0x24, 0x22, 0x9b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "smaddl x3, w5, w2, x9"
+
+  -
+    input:
+      bytes: [ 0x5f, 0x31, 0x2b, 0x9b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "smaddl xzr, w10, w11, x12"
+
+  -
+    input:
+      bytes: [ 0xed, 0x3f, 0x2e, 0x9b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "smaddl x13, wzr, w14, x15"
+
+  -
+    input:
+      bytes: [ 0x30, 0x4a, 0x3f, 0x9b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "smaddl x16, w17, wzr, x18"
+
+  -
+    input:
+      bytes: [ 0x93, 0x7e, 0x35, 0x9b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "smull x19, w20, w21"
+
+  -
+    input:
+      bytes: [ 0xa3, 0xa4, 0x22, 0x9b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "smsubl x3, w5, w2, x9"
+
+  -
+    input:
+      bytes: [ 0x5f, 0xb1, 0x2b, 0x9b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "smsubl xzr, w10, w11, x12"
+
+  -
+    input:
+      bytes: [ 0xed, 0xbf, 0x2e, 0x9b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "smsubl x13, wzr, w14, x15"
+
+  -
+    input:
+      bytes: [ 0x30, 0xca, 0x3f, 0x9b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "smsubl x16, w17, wzr, x18"
+
+  -
+    input:
+      bytes: [ 0x93, 0xfe, 0x35, 0x9b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "smnegl x19, w20, w21"
+
+  -
+    input:
+      bytes: [ 0xa3, 0x24, 0xa2, 0x9b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "umaddl x3, w5, w2, x9"
+
+  -
+    input:
+      bytes: [ 0x5f, 0x31, 0xab, 0x9b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "umaddl xzr, w10, w11, x12"
+
+  -
+    input:
+      bytes: [ 0xed, 0x3f, 0xae, 0x9b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "umaddl x13, wzr, w14, x15"
+
+  -
+    input:
+      bytes: [ 0x30, 0x4a, 0xbf, 0x9b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "umaddl x16, w17, wzr, x18"
+
+  -
+    input:
+      bytes: [ 0x93, 0x7e, 0xb5, 0x9b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "umull x19, w20, w21"
+
+  -
+    input:
+      bytes: [ 0xa3, 0xa4, 0xa2, 0x9b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "umsubl x3, w5, w2, x9"
+
+  -
+    input:
+      bytes: [ 0x5f, 0xb1, 0xab, 0x9b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "umsubl xzr, w10, w11, x12"
+
+  -
+    input:
+      bytes: [ 0xed, 0xbf, 0xae, 0x9b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "umsubl x13, wzr, w14, x15"
+
+  -
+    input:
+      bytes: [ 0x30, 0xca, 0xbf, 0x9b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "umsubl x16, w17, wzr, x18"
+
+  -
+    input:
+      bytes: [ 0x93, 0xfe, 0xb5, 0x9b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "umnegl x19, w20, w21"
+
+  -
+    input:
+      bytes: [ 0xbe, 0x7f, 0x5c, 0x9b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "smulh x30, x29, x28"
+
+  -
+    input:
+      bytes: [ 0x7f, 0x7f, 0x5a, 0x9b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "smulh xzr, x27, x26"
+
+  -
+    input:
+      bytes: [ 0xf9, 0x7f, 0x58, 0x9b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "smulh x25, xzr, x24"
+
+  -
+    input:
+      bytes: [ 0xd7, 0x7e, 0x5f, 0x9b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "smulh x23, x22, xzr"
+
+  -
+    input:
+      bytes: [ 0xbe, 0x7f, 0xdc, 0x9b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "umulh x30, x29, x28"
+
+  -
+    input:
+      bytes: [ 0x7f, 0x7f, 0xda, 0x9b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "umulh xzr, x27, x26"
+
+  -
+    input:
+      bytes: [ 0xf9, 0x7f, 0xd8, 0x9b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "umulh x25, xzr, x24"
+
+  -
+    input:
+      bytes: [ 0xd7, 0x7e, 0xdf, 0x9b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "umulh x23, x22, xzr"
+
+  -
+    input:
+      bytes: [ 0x83, 0x7c, 0x05, 0x1b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul w3, w4, w5"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x7c, 0x07, 0x1b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul wzr, w6, w7"
+
+  -
+    input:
+      bytes: [ 0xe8, 0x7f, 0x09, 0x1b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul w8, wzr, w9"
+
+  -
+    input:
+      bytes: [ 0x6a, 0x7d, 0x1f, 0x1b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul w10, w11, wzr"
+
+  -
+    input:
+      bytes: [ 0xac, 0x7d, 0x0e, 0x9b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul x12, x13, x14"
+
+  -
+    input:
+      bytes: [ 0xff, 0x7d, 0x10, 0x9b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul xzr, x15, x16"
+
+  -
+    input:
+      bytes: [ 0xf1, 0x7f, 0x12, 0x9b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul x17, xzr, x18"
+
+  -
+    input:
+      bytes: [ 0x93, 0x7e, 0x1f, 0x9b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul x19, x20, xzr"
+
+  -
+    input:
+      bytes: [ 0xd5, 0xfe, 0x17, 0x1b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mneg w21, w22, w23"
+
+  -
+    input:
+      bytes: [ 0x1f, 0xff, 0x19, 0x1b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mneg wzr, w24, w25"
+
+  -
+    input:
+      bytes: [ 0xfa, 0xff, 0x1b, 0x1b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mneg w26, wzr, w27"
+
+  -
+    input:
+      bytes: [ 0xbc, 0xff, 0x1f, 0x1b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mneg w28, w29, wzr"
+
+  -
+    input:
+      bytes: [ 0xab, 0x7d, 0x31, 0x9b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "smull x11, w13, w17"
+
+  -
+    input:
+      bytes: [ 0xab, 0x7d, 0xb1, 0x9b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "umull x11, w13, w17"
+
+  -
+    input:
+      bytes: [ 0xab, 0xfd, 0x31, 0x9b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "smnegl x11, w13, w17"
+
+  -
+    input:
+      bytes: [ 0xab, 0xfd, 0xb1, 0x9b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "umnegl x11, w13, w17"
+
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0x00, 0xd4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "svc #0"
+
+  -
+    input:
+      bytes: [ 0xe1, 0xff, 0x1f, 0xd4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "svc #0xffff"
+
+  -
+    input:
+      bytes: [ 0x22, 0x00, 0x00, 0xd4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "hvc #0x1"
+
+  -
+    input:
+      bytes: [ 0x03, 0xdc, 0x05, 0xd4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "smc #0x2ee0"
+
+  -
+    input:
+      bytes: [ 0x80, 0x01, 0x20, 0xd4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "brk #0xc"
+
+  -
+    input:
+      bytes: [ 0x60, 0x0f, 0x40, 0xd4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "hlt #0x7b"
+
+  -
+    input:
+      bytes: [ 0x41, 0x05, 0xa0, 0xd4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "dcps1 #0x2a"
+
+  -
+    input:
+      bytes: [ 0x22, 0x01, 0xa0, 0xd4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "dcps2 #0x9"
+
+  -
+    input:
+      bytes: [ 0x03, 0x7d, 0xa0, 0xd4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "dcps3 #0x3e8"
+
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0xa0, 0xd4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "dcps1"
+
+  -
+    input:
+      bytes: [ 0x02, 0x00, 0xa0, 0xd4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "dcps2"
+
+  -
+    input:
+      bytes: [ 0x03, 0x00, 0xa0, 0xd4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "dcps3"
+
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0x87, 0x13 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr w3, w5, w7, #0"
+
+  -
+    input:
+      bytes: [ 0xab, 0x7d, 0x91, 0x13 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr w11, w13, w17, #31"
+
+  -
+    input:
+      bytes: [ 0xa3, 0x3c, 0xc7, 0x93 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr x3, x5, x7, #15"
+
+  -
+    input:
+      bytes: [ 0xab, 0xfd, 0xd1, 0x93 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr x11, x13, x17, #63"
+
+  -
+    input:
+      bytes: [ 0xf3, 0x62, 0xd7, 0x93 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ror x19, x23, #24"
+
+  -
+    input:
+      bytes: [ 0xfd, 0xff, 0xdf, 0x93 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ror x29, xzr, #63"
+
+  -
+    input:
+      bytes: [ 0xa9, 0x7d, 0x8d, 0x13 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ror w9, w13, #31"
+
+  -
+    input:
+      bytes: [ 0x60, 0x20, 0x25, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmp s3, s5"
+
+  -
+    input:
+      bytes: [ 0xe8, 0x23, 0x20, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmp s31, #0.0"
+
+  -
+    input:
+      bytes: [ 0xb0, 0x23, 0x3e, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmpe s29, s30"
+
+  -
+    input:
+      bytes: [ 0xf8, 0x21, 0x20, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmpe s15, #0.0"
+
+  -
+    input:
+      bytes: [ 0x80, 0x20, 0x6c, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmp d4, d12"
+
+  -
+    input:
+      bytes: [ 0xe8, 0x22, 0x60, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmp d23, #0.0"
+
+  -
+    input:
+      bytes: [ 0x50, 0x23, 0x76, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmpe d26, d22"
+
+  -
+    input:
+      bytes: [ 0xb8, 0x23, 0x60, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmpe d29, #0.0"
+
+  -
+    input:
+      bytes: [ 0x20, 0x04, 0x3f, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fccmp s1, s31, #0, eq"
+
+  -
+    input:
+      bytes: [ 0x6f, 0x24, 0x20, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fccmp s3, s0, #15, hs"
+
+  -
+    input:
+      bytes: [ 0xed, 0x27, 0x2f, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fccmp s31, s15, #13, hs"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd5, 0x7f, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fccmp d9, d31, #0, le"
+
+  -
+    input:
+      bytes: [ 0x6f, 0xc4, 0x60, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fccmp d3, d0, #15, gt"
+
+  -
+    input:
+      bytes: [ 0xe7, 0x17, 0x65, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fccmp d31, d5, #7, ne"
+
+  -
+    input:
+      bytes: [ 0x30, 0x04, 0x3f, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fccmpe s1, s31, #0, eq"
+
+  -
+    input:
+      bytes: [ 0x7f, 0x24, 0x20, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fccmpe s3, s0, #15, hs"
+
+  -
+    input:
+      bytes: [ 0xfd, 0x27, 0x2f, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fccmpe s31, s15, #13, hs"
+
+  -
+    input:
+      bytes: [ 0x30, 0xd5, 0x7f, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fccmpe d9, d31, #0, le"
+
+  -
+    input:
+      bytes: [ 0x7f, 0xc4, 0x60, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fccmpe d3, d0, #15, gt"
+
+  -
+    input:
+      bytes: [ 0xf7, 0x17, 0x65, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fccmpe d31, d5, #7, ne"
+
+  -
+    input:
+      bytes: [ 0x83, 0x5e, 0x29, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcsel s3, s20, s9, pl"
+
+  -
+    input:
+      bytes: [ 0x49, 0x4d, 0x6b, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcsel d9, d10, d11, mi"
+
+  -
+    input:
+      bytes: [ 0x20, 0x40, 0x20, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov s0, s1"
+
+  -
+    input:
+      bytes: [ 0x62, 0xc0, 0x20, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fabs s2, s3"
+
+  -
+    input:
+      bytes: [ 0xa4, 0x40, 0x21, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fneg s4, s5"
+
+  -
+    input:
+      bytes: [ 0xe6, 0xc0, 0x21, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsqrt s6, s7"
+
+  -
+    input:
+      bytes: [ 0x28, 0xc1, 0x22, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvt d8, s9"
+
+  -
+    input:
+      bytes: [ 0x6a, 0xc1, 0x23, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvt h10, s11"
+
+  -
+    input:
+      bytes: [ 0xac, 0x41, 0x24, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "frintn s12, s13"
+
+  -
+    input:
+      bytes: [ 0xee, 0xc1, 0x24, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "frintp s14, s15"
+
+  -
+    input:
+      bytes: [ 0x30, 0x42, 0x25, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "frintm s16, s17"
+
+  -
+    input:
+      bytes: [ 0x72, 0xc2, 0x25, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "frintz s18, s19"
+
+  -
+    input:
+      bytes: [ 0xb4, 0x42, 0x26, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "frinta s20, s21"
+
+  -
+    input:
+      bytes: [ 0xf6, 0x42, 0x27, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "frintx s22, s23"
+
+  -
+    input:
+      bytes: [ 0x38, 0xc3, 0x27, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "frinti s24, s25"
+
+  -
+    input:
+      bytes: [ 0x20, 0x40, 0x60, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov d0, d1"
+
+  -
+    input:
+      bytes: [ 0x62, 0xc0, 0x60, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fabs d2, d3"
+
+  -
+    input:
+      bytes: [ 0xa4, 0x40, 0x61, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fneg d4, d5"
+
+  -
+    input:
+      bytes: [ 0xe6, 0xc0, 0x61, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsqrt d6, d7"
+
+  -
+    input:
+      bytes: [ 0x28, 0x41, 0x62, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvt s8, d9"
+
+  -
+    input:
+      bytes: [ 0x6a, 0xc1, 0x63, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvt h10, d11"
+
+  -
+    input:
+      bytes: [ 0xac, 0x41, 0x64, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "frintn d12, d13"
+
+  -
+    input:
+      bytes: [ 0xee, 0xc1, 0x64, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "frintp d14, d15"
+
+  -
+    input:
+      bytes: [ 0x30, 0x42, 0x65, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "frintm d16, d17"
+
+  -
+    input:
+      bytes: [ 0x72, 0xc2, 0x65, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "frintz d18, d19"
+
+  -
+    input:
+      bytes: [ 0xb4, 0x42, 0x66, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "frinta d20, d21"
+
+  -
+    input:
+      bytes: [ 0xf6, 0x42, 0x67, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "frintx d22, d23"
+
+  -
+    input:
+      bytes: [ 0x38, 0xc3, 0x67, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "frinti d24, d25"
+
+  -
+    input:
+      bytes: [ 0x7a, 0x43, 0xe2, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvt s26, h27"
+
+  -
+    input:
+      bytes: [ 0xbc, 0xc3, 0xe2, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvt d28, h29"
+
+  -
+    input:
+      bytes: [ 0x74, 0x0a, 0x31, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmul s20, s19, s17"
+
+  -
+    input:
+      bytes: [ 0x41, 0x18, 0x23, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdiv s1, s2, s3"
+
+  -
+    input:
+      bytes: [ 0xa4, 0x28, 0x26, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd s4, s5, s6"
+
+  -
+    input:
+      bytes: [ 0x07, 0x39, 0x29, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub s7, s8, s9"
+
+  -
+    input:
+      bytes: [ 0x6a, 0x49, 0x2c, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmax s10, s11, s12"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x59, 0x2f, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmin s13, s14, s15"
+
+  -
+    input:
+      bytes: [ 0x30, 0x6a, 0x32, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnm s16, s17, s18"
+
+  -
+    input:
+      bytes: [ 0x93, 0x7a, 0x35, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnm s19, s20, s21"
+
+  -
+    input:
+      bytes: [ 0xf6, 0x8a, 0x38, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fnmul s22, s23, s24"
+
+  -
+    input:
+      bytes: [ 0x74, 0x0a, 0x71, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmul d20, d19, d17"
+
+  -
+    input:
+      bytes: [ 0x41, 0x18, 0x63, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdiv d1, d2, d3"
+
+  -
+    input:
+      bytes: [ 0xa4, 0x28, 0x66, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd d4, d5, d6"
+
+  -
+    input:
+      bytes: [ 0x07, 0x39, 0x69, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub d7, d8, d9"
+
+  -
+    input:
+      bytes: [ 0x6a, 0x49, 0x6c, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmax d10, d11, d12"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x59, 0x6f, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmin d13, d14, d15"
+
+  -
+    input:
+      bytes: [ 0x30, 0x6a, 0x72, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnm d16, d17, d18"
+
+  -
+    input:
+      bytes: [ 0x93, 0x7a, 0x75, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnm d19, d20, d21"
+
+  -
+    input:
+      bytes: [ 0xf6, 0x8a, 0x78, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fnmul d22, d23, d24"
+
+  -
+    input:
+      bytes: [ 0xa3, 0x7c, 0x06, 0x1f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmadd s3, s5, s6, s31"
+
+  -
+    input:
+      bytes: [ 0xa3, 0x5d, 0x40, 0x1f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmadd d3, d13, d0, d23"
+
+  -
+    input:
+      bytes: [ 0xa3, 0xfc, 0x06, 0x1f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmsub s3, s5, s6, s31"
+
+  -
+    input:
+      bytes: [ 0xa3, 0xdd, 0x40, 0x1f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmsub d3, d13, d0, d23"
+
+  -
+    input:
+      bytes: [ 0xa3, 0x7c, 0x26, 0x1f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fnmadd s3, s5, s6, s31"
+
+  -
+    input:
+      bytes: [ 0xa3, 0x5d, 0x60, 0x1f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fnmadd d3, d13, d0, d23"
+
+  -
+    input:
+      bytes: [ 0xa3, 0xfc, 0x26, 0x1f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fnmsub s3, s5, s6, s31"
+
+  -
+    input:
+      bytes: [ 0xa3, 0xdd, 0x60, 0x1f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fnmsub d3, d13, d0, d23"
+
+  -
+    input:
+      bytes: [ 0xa3, 0xfc, 0x18, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtzs w3, s5, #1"
+
+  -
+    input:
+      bytes: [ 0x9f, 0xce, 0x18, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtzs wzr, s20, #13"
+
+  -
+    input:
+      bytes: [ 0x13, 0x80, 0x18, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtzs w19, s0, #32"
+
+  -
+    input:
+      bytes: [ 0xa3, 0xfc, 0x18, 0x9e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtzs x3, s5, #1"
+
+  -
+    input:
+      bytes: [ 0xcc, 0x4f, 0x18, 0x9e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtzs x12, s30, #45"
+
+  -
+    input:
+      bytes: [ 0x13, 0x00, 0x18, 0x9e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtzs x19, s0, #64"
+
+  -
+    input:
+      bytes: [ 0xa3, 0xfc, 0x58, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtzs w3, d5, #1"
+
+  -
+    input:
+      bytes: [ 0x9f, 0xce, 0x58, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtzs wzr, d20, #13"
+
+  -
+    input:
+      bytes: [ 0x13, 0x80, 0x58, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtzs w19, d0, #32"
+
+  -
+    input:
+      bytes: [ 0xa3, 0xfc, 0x58, 0x9e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtzs x3, d5, #1"
+
+  -
+    input:
+      bytes: [ 0xcc, 0x4f, 0x58, 0x9e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtzs x12, d30, #45"
+
+  -
+    input:
+      bytes: [ 0x13, 0x00, 0x58, 0x9e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtzs x19, d0, #64"
+
+  -
+    input:
+      bytes: [ 0xa3, 0xfc, 0x19, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtzu w3, s5, #1"
+
+  -
+    input:
+      bytes: [ 0x9f, 0xce, 0x19, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtzu wzr, s20, #13"
+
+  -
+    input:
+      bytes: [ 0x13, 0x80, 0x19, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtzu w19, s0, #32"
+
+  -
+    input:
+      bytes: [ 0xa3, 0xfc, 0x19, 0x9e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtzu x3, s5, #1"
+
+  -
+    input:
+      bytes: [ 0xcc, 0x4f, 0x19, 0x9e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtzu x12, s30, #45"
+
+  -
+    input:
+      bytes: [ 0x13, 0x00, 0x19, 0x9e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtzu x19, s0, #64"
+
+  -
+    input:
+      bytes: [ 0xa3, 0xfc, 0x59, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtzu w3, d5, #1"
+
+  -
+    input:
+      bytes: [ 0x9f, 0xce, 0x59, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtzu wzr, d20, #13"
+
+  -
+    input:
+      bytes: [ 0x13, 0x80, 0x59, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtzu w19, d0, #32"
+
+  -
+    input:
+      bytes: [ 0xa3, 0xfc, 0x59, 0x9e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtzu x3, d5, #1"
+
+  -
+    input:
+      bytes: [ 0xcc, 0x4f, 0x59, 0x9e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtzu x12, d30, #45"
+
+  -
+    input:
+      bytes: [ 0x13, 0x00, 0x59, 0x9e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtzu x19, d0, #64"
+
+  -
+    input:
+      bytes: [ 0x77, 0xfe, 0x02, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "scvtf s23, w19, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0xb3, 0x02, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "scvtf s31, wzr, #20"
+
+  -
+    input:
+      bytes: [ 0x0e, 0x80, 0x02, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "scvtf s14, w0, #32"
+
+  -
+    input:
+      bytes: [ 0x77, 0xfe, 0x02, 0x9e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "scvtf s23, x19, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0xb3, 0x02, 0x9e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "scvtf s31, xzr, #20"
+
+  -
+    input:
+      bytes: [ 0x0e, 0x00, 0x02, 0x9e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "scvtf s14, x0, #64"
+
+  -
+    input:
+      bytes: [ 0x77, 0xfe, 0x42, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "scvtf d23, w19, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0xb3, 0x42, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "scvtf d31, wzr, #20"
+
+  -
+    input:
+      bytes: [ 0x0e, 0x80, 0x42, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "scvtf d14, w0, #32"
+
+  -
+    input:
+      bytes: [ 0x77, 0xfe, 0x42, 0x9e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "scvtf d23, x19, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0xb3, 0x42, 0x9e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "scvtf d31, xzr, #20"
+
+  -
+    input:
+      bytes: [ 0x0e, 0x00, 0x42, 0x9e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "scvtf d14, x0, #64"
+
+  -
+    input:
+      bytes: [ 0x77, 0xfe, 0x03, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ucvtf s23, w19, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0xb3, 0x03, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ucvtf s31, wzr, #20"
+
+  -
+    input:
+      bytes: [ 0x0e, 0x80, 0x03, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ucvtf s14, w0, #32"
+
+  -
+    input:
+      bytes: [ 0x77, 0xfe, 0x03, 0x9e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ucvtf s23, x19, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0xb3, 0x03, 0x9e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ucvtf s31, xzr, #20"
+
+  -
+    input:
+      bytes: [ 0x0e, 0x00, 0x03, 0x9e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ucvtf s14, x0, #64"
+
+  -
+    input:
+      bytes: [ 0x77, 0xfe, 0x43, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ucvtf d23, w19, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0xb3, 0x43, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ucvtf d31, wzr, #20"
+
+  -
+    input:
+      bytes: [ 0x0e, 0x80, 0x43, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ucvtf d14, w0, #32"
+
+  -
+    input:
+      bytes: [ 0x77, 0xfe, 0x43, 0x9e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ucvtf d23, x19, #1"
+
+  -
+    input:
+      bytes: [ 0xff, 0xb3, 0x43, 0x9e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ucvtf d31, xzr, #20"
+
+  -
+    input:
+      bytes: [ 0x0e, 0x00, 0x43, 0x9e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ucvtf d14, x0, #64"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x03, 0x20, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtns w3, s31"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x01, 0x20, 0x9e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtns xzr, s12"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x01, 0x21, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtnu wzr, s12"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x21, 0x9e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtnu x0, s0"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x01, 0x28, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtps wzr, s9"
+
+  -
+    input:
+      bytes: [ 0x8c, 0x02, 0x28, 0x9e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtps x12, s20"
+
+  -
+    input:
+      bytes: [ 0xfe, 0x02, 0x29, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtpu w30, s23"
+
+  -
+    input:
+      bytes: [ 0x7d, 0x00, 0x29, 0x9e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtpu x29, s3"
+
+  -
+    input:
+      bytes: [ 0x62, 0x00, 0x30, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtms w2, s3"
+
+  -
+    input:
+      bytes: [ 0xa4, 0x00, 0x30, 0x9e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtms x4, s5"
+
+  -
+    input:
+      bytes: [ 0xe6, 0x00, 0x31, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtmu w6, s7"
+
+  -
+    input:
+      bytes: [ 0x28, 0x01, 0x31, 0x9e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtmu x8, s9"
+
+  -
+    input:
+      bytes: [ 0x6a, 0x01, 0x38, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtzs w10, s11"
+
+  -
+    input:
+      bytes: [ 0xac, 0x01, 0x38, 0x9e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtzs x12, s13"
+
+  -
+    input:
+      bytes: [ 0xee, 0x01, 0x39, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtzu w14, s15"
+
+  -
+    input:
+      bytes: [ 0x0f, 0x02, 0x39, 0x9e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtzu x15, s16"
+
+  -
+    input:
+      bytes: [ 0x51, 0x02, 0x22, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "scvtf s17, w18"
+
+  -
+    input:
+      bytes: [ 0x93, 0x02, 0x22, 0x9e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "scvtf s19, x20"
+
+  -
+    input:
+      bytes: [ 0xd5, 0x02, 0x23, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ucvtf s21, w22"
+
+  -
+    input:
+      bytes: [ 0x17, 0x03, 0x22, 0x9e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "scvtf s23, x24"
+
+  -
+    input:
+      bytes: [ 0x59, 0x03, 0x24, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtas w25, s26"
+
+  -
+    input:
+      bytes: [ 0x9b, 0x03, 0x24, 0x9e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtas x27, s28"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x03, 0x25, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtau w29, s30"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x00, 0x25, 0x9e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtau xzr, s0"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x03, 0x60, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtns w3, d31"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x01, 0x60, 0x9e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtns xzr, d12"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x01, 0x61, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtnu wzr, d12"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x61, 0x9e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtnu x0, d0"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x01, 0x68, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtps wzr, d9"
+
+  -
+    input:
+      bytes: [ 0x8c, 0x02, 0x68, 0x9e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtps x12, d20"
+
+  -
+    input:
+      bytes: [ 0xfe, 0x02, 0x69, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtpu w30, d23"
+
+  -
+    input:
+      bytes: [ 0x7d, 0x00, 0x69, 0x9e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtpu x29, d3"
+
+  -
+    input:
+      bytes: [ 0x62, 0x00, 0x70, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtms w2, d3"
+
+  -
+    input:
+      bytes: [ 0xa4, 0x00, 0x70, 0x9e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtms x4, d5"
+
+  -
+    input:
+      bytes: [ 0xe6, 0x00, 0x71, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtmu w6, d7"
+
+  -
+    input:
+      bytes: [ 0x28, 0x01, 0x71, 0x9e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtmu x8, d9"
+
+  -
+    input:
+      bytes: [ 0x6a, 0x01, 0x78, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtzs w10, d11"
+
+  -
+    input:
+      bytes: [ 0xac, 0x01, 0x78, 0x9e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtzs x12, d13"
+
+  -
+    input:
+      bytes: [ 0xee, 0x01, 0x79, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtzu w14, d15"
+
+  -
+    input:
+      bytes: [ 0x0f, 0x02, 0x79, 0x9e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtzu x15, d16"
+
+  -
+    input:
+      bytes: [ 0x51, 0x02, 0x62, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "scvtf d17, w18"
+
+  -
+    input:
+      bytes: [ 0x93, 0x02, 0x62, 0x9e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "scvtf d19, x20"
+
+  -
+    input:
+      bytes: [ 0xd5, 0x02, 0x63, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ucvtf d21, w22"
+
+  -
+    input:
+      bytes: [ 0x17, 0x03, 0x63, 0x9e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ucvtf d23, x24"
+
+  -
+    input:
+      bytes: [ 0x59, 0x03, 0x64, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtas w25, d26"
+
+  -
+    input:
+      bytes: [ 0x9b, 0x03, 0x64, 0x9e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtas x27, d28"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x03, 0x65, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtau w29, d30"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x00, 0x65, 0x9e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtau xzr, d0"
+
+  -
+    input:
+      bytes: [ 0x23, 0x01, 0x26, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov w3, s9"
+
+  -
+    input:
+      bytes: [ 0x69, 0x00, 0x27, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov s9, w3"
+
+  -
+    input:
+      bytes: [ 0xf4, 0x03, 0x66, 0x9e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov x20, d31"
+
+  -
+    input:
+      bytes: [ 0xe1, 0x01, 0x67, 0x9e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov d1, x15"
+
+  -
+    input:
+      bytes: [ 0x83, 0x01, 0xae, 0x9e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov x3, v12.d[1]"
+
+  -
+    input:
+      bytes: [ 0x61, 0x02, 0xaf, 0x9e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov v1.d[1], x19"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x03, 0xaf, 0x9e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov v3.d[1], xzr"
+
+  -
+    input:
+      bytes: [ 0x02, 0x10, 0x28, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov s2, #0.12500000"
+
+  -
+    input:
+      bytes: [ 0x03, 0x10, 0x2e, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov s3, #1.00000000"
+
+  -
+    input:
+      bytes: [ 0x1e, 0x10, 0x66, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov d30, #16.00000000"
+
+  -
+    input:
+      bytes: [ 0x04, 0x30, 0x2e, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov s4, #1.06250000"
+
+  -
+    input:
+      bytes: [ 0x0a, 0xf0, 0x6f, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov d10, #1.93750000"
+
+  -
+    input:
+      bytes: [ 0x0c, 0x10, 0x3e, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov s12, #-1.00000000"
+
+  -
+    input:
+      bytes: [ 0x10, 0x30, 0x64, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov d16, #8.50000000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xff, 0x7f, 0x18 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr w0, #1048572"
+
+  -
+    input:
+      bytes: [ 0x0a, 0x00, 0x80, 0x58 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr x10, #-1048576"
+
+  -
+    input:
+      bytes: [ 0x62, 0x7c, 0x01, 0x08 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "stxrb w1, w2, [x3]"
+
+  -
+    input:
+      bytes: [ 0x83, 0x7c, 0x02, 0x48 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "stxrh w2, w3, [x4]"
+
+  -
+    input:
+      bytes: [ 0xe4, 0x7f, 0x1f, 0x88 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "stxr wzr, w4, [sp]"
+
+  -
+    input:
+      bytes: [ 0xe6, 0x7c, 0x05, 0xc8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "stxr w5, x6, [x7]"
+
+  -
+    input:
+      bytes: [ 0x27, 0x7d, 0x5f, 0x08 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldxrb w7, [x9]"
+
+  -
+    input:
+      bytes: [ 0x5f, 0x7d, 0x5f, 0x48 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldxrh wzr, [x10]"
+
+  -
+    input:
+      bytes: [ 0xe9, 0x7f, 0x5f, 0x88 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldxr w9, [sp]"
+
+  -
+    input:
+      bytes: [ 0x6a, 0x7d, 0x5f, 0xc8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldxr x10, [x11]"
+
+  -
+    input:
+      bytes: [ 0xcc, 0x35, 0x2b, 0x88 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "stxp w11, w12, w13, [x14]"
+
+  -
+    input:
+      bytes: [ 0xf7, 0x39, 0x3f, 0xc8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "stxp wzr, x23, x14, [x15]"
+
+  -
+    input:
+      bytes: [ 0xec, 0x7f, 0x7f, 0x88 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldxp w12, wzr, [sp]"
+
+  -
+    input:
+      bytes: [ 0xed, 0x39, 0x7f, 0xc8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldxp x13, x14, [x15]"
+
+  -
+    input:
+      bytes: [ 0x0f, 0xfe, 0x0e, 0x08 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "stlxrb w14, w15, [x16]"
+
+  -
+    input:
+      bytes: [ 0x30, 0xfe, 0x0f, 0x48 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "stlxrh w15, w16, [x17]"
+
+  -
+    input:
+      bytes: [ 0xf1, 0xff, 0x1f, 0x88 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "stlxr wzr, w17, [sp]"
+
+  -
+    input:
+      bytes: [ 0x93, 0xfe, 0x12, 0xc8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "stlxr w18, x19, [x20]"
+
+  -
+    input:
+      bytes: [ 0xb3, 0xfe, 0x5f, 0x08 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldaxrb w19, [x21]"
+
+  -
+    input:
+      bytes: [ 0xf4, 0xff, 0x5f, 0x48 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldaxrh w20, [sp]"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xfe, 0x5f, 0x88 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldaxr wzr, [x22]"
+
+  -
+    input:
+      bytes: [ 0xf5, 0xfe, 0x5f, 0xc8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldaxr x21, [x23]"
+
+  -
+    input:
+      bytes: [ 0x16, 0xdf, 0x3f, 0x88 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "stlxp wzr, w22, w23, [x24]"
+
+  -
+    input:
+      bytes: [ 0xfa, 0xef, 0x39, 0xc8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "stlxp w25, x26, x27, [sp]"
+
+  -
+    input:
+      bytes: [ 0xfa, 0xff, 0x7f, 0x88 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldaxp w26, wzr, [sp]"
+
+  -
+    input:
+      bytes: [ 0xdb, 0xf3, 0x7f, 0xc8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldaxp x27, x28, [x30]"
+
+  -
+    input:
+      bytes: [ 0xfb, 0xff, 0x9f, 0x08 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "stlrb w27, [sp]"
+
+  -
+    input:
+      bytes: [ 0x1c, 0xfc, 0x9f, 0x48 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "stlrh w28, [x0]"
+
+  -
+    input:
+      bytes: [ 0x3f, 0xfc, 0x9f, 0x88 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "stlr wzr, [x1]"
+
+  -
+    input:
+      bytes: [ 0x5e, 0xfc, 0x9f, 0xc8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "stlr x30, [x2]"
+
+  -
+    input:
+      bytes: [ 0xfd, 0xff, 0xdf, 0x08 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldarb w29, [sp]"
+
+  -
+    input:
+      bytes: [ 0x1e, 0xfc, 0xdf, 0x48 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldarh w30, [x0]"
+
+  -
+    input:
+      bytes: [ 0x3f, 0xfc, 0xdf, 0x88 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldar wzr, [x1]"
+
+  -
+    input:
+      bytes: [ 0x41, 0xfc, 0xdf, 0xc8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldar x1, [x2]"
+
+  -
+    input:
+      bytes: [ 0x16, 0xdf, 0x3f, 0x88 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "stlxp wzr, w22, w23, [x24]"
+
+  -
+    input:
+      bytes: [ 0xe9, 0x03, 0x00, 0x38 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "sturb w9, [sp]"
+
+  -
+    input:
+      bytes: [ 0x9f, 0xf1, 0x0f, 0x78 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "sturh wzr, [x12, #255]"
+
+  -
+    input:
+      bytes: [ 0x10, 0x00, 0x10, 0xb8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "stur w16, [x0, #-256]"
+
+  -
+    input:
+      bytes: [ 0xdc, 0x11, 0x00, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "stur x28, [x14, #1]"
+
+  -
+    input:
+      bytes: [ 0x81, 0xf2, 0x4f, 0x38 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldurb w1, [x20, #255]"
+
+  -
+    input:
+      bytes: [ 0x34, 0xf0, 0x4f, 0x78 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldurh w20, [x1, #255]"
+
+  -
+    input:
+      bytes: [ 0xec, 0xf3, 0x4f, 0xb8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldur w12, [sp, #255]"
+
+  -
+    input:
+      bytes: [ 0x9f, 0xf1, 0x4f, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldur xzr, [x12, #255]"
+
+  -
+    input:
+      bytes: [ 0xe9, 0x00, 0x90, 0x38 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldursb x9, [x7, #-256]"
+
+  -
+    input:
+      bytes: [ 0x71, 0x02, 0x90, 0x78 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldursh x17, [x19, #-256]"
+
+  -
+    input:
+      bytes: [ 0xf4, 0x01, 0x90, 0xb8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldursw x20, [x15, #-256]"
+
+  -
+    input:
+      bytes: [ 0x4d, 0x00, 0x80, 0xb8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldursw x13, [x2]"
+
+  -
+    input:
+      bytes: [ 0xe2, 0x03, 0x90, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfum pldl2keep, [sp, #-256]"
+
+  -
+    input:
+      bytes: [ 0x33, 0x00, 0xd0, 0x38 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldursb w19, [x1, #-256]"
+
+  -
+    input:
+      bytes: [ 0xaf, 0x02, 0xd0, 0x78 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldursh w15, [x21, #-256]"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x13, 0x00, 0x3c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "stur b0, [sp, #1]"
+
+  -
+    input:
+      bytes: [ 0x8c, 0xf1, 0x1f, 0x7c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "stur h12, [x12, #-1]"
+
+  -
+    input:
+      bytes: [ 0x0f, 0xf0, 0x0f, 0xbc ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "stur s15, [x0, #255]"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x90, 0x01, 0xfc ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "stur d31, [x5, #25]"
+
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x80, 0x3c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "stur q9, [x5]"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x03, 0x40, 0x3c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldur b3, [sp]"
+
+  -
+    input:
+      bytes: [ 0x85, 0x00, 0x50, 0x7c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldur h5, [x4, #-256]"
+
+  -
+    input:
+      bytes: [ 0x87, 0xf1, 0x5f, 0xbc ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldur s7, [x12, #-1]"
+
+  -
+    input:
+      bytes: [ 0x6b, 0x42, 0x40, 0xfc ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldur d11, [x19, #4]"
+
+  -
+    input:
+      bytes: [ 0x2d, 0x20, 0xc0, 0x3c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldur q13, [x1, #2]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x40, 0xf9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0xa4, 0x03, 0x40, 0xf9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr x4, [x29]"
+
+  -
+    input:
+      bytes: [ 0x9e, 0xfd, 0x7f, 0xf9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr x30, [x12, #32760]"
+
+  -
+    input:
+      bytes: [ 0xf4, 0x07, 0x40, 0xf9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr x20, [sp, #8]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x03, 0x40, 0xf9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr xzr, [sp]"
+
+  -
+    input:
+      bytes: [ 0xe2, 0x03, 0x40, 0xb9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr w2, [sp]"
+
+  -
+    input:
+      bytes: [ 0xf1, 0xff, 0x7f, 0xb9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr w17, [sp, #16380]"
+
+  -
+    input:
+      bytes: [ 0x4d, 0x04, 0x40, 0xb9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr w13, [x2, #4]"
+
+  -
+    input:
+      bytes: [ 0xa2, 0x04, 0x80, 0xb9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldrsw x2, [x5, #4]"
+
+  -
+    input:
+      bytes: [ 0xf7, 0xff, 0xbf, 0xb9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldrsw x23, [sp, #16380]"
+
+  -
+    input:
+      bytes: [ 0x82, 0x00, 0x40, 0x79 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldrh w2, [x4]"
+
+  -
+    input:
+      bytes: [ 0xd7, 0xfc, 0xff, 0x79 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldrsh w23, [x6, #8190]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x07, 0xc0, 0x79 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldrsh wzr, [sp, #2]"
+
+  -
+    input:
+      bytes: [ 0x5d, 0x04, 0x80, 0x79 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldrsh x29, [x2, #2]"
+
+  -
+    input:
+      bytes: [ 0x7a, 0xe4, 0x41, 0x39 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldrb w26, [x3, #121]"
+
+  -
+    input:
+      bytes: [ 0x4c, 0x00, 0x40, 0x39 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldrb w12, [x2]"
+
+  -
+    input:
+      bytes: [ 0xfb, 0xff, 0xff, 0x39 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldrsb w27, [sp, #4095]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x01, 0x80, 0x39 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldrsb xzr, [x15]"
+
+  -
+    input:
+      bytes: [ 0xfe, 0x03, 0x00, 0xf9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "str x30, [sp]"
+
+  -
+    input:
+      bytes: [ 0x94, 0xfc, 0x3f, 0xb9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "str w20, [x4, #16380]"
+
+  -
+    input:
+      bytes: [ 0x54, 0x1d, 0x00, 0x79 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "strh w20, [x10, #14]"
+
+  -
+    input:
+      bytes: [ 0xf1, 0xff, 0x3f, 0x79 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "strh w17, [sp, #8190]"
+
+  -
+    input:
+      bytes: [ 0x77, 0xfc, 0x3f, 0x39 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "strb w23, [x3, #4095]"
+
+  -
+    input:
+      bytes: [ 0x5f, 0x00, 0x00, 0x39 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "strb wzr, [x2]"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x07, 0x80, 0xf9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfm pldl1keep, [sp, #8]"
+
+  -
+    input:
+      bytes: [ 0x61, 0x00, 0x80, 0xf9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfm pldl1strm, [x3]"
+
+  -
+    input:
+      bytes: [ 0xa2, 0x08, 0x80, 0xf9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfm pldl2keep, [x5, #16]"
+
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x80, 0xf9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfm pldl2strm, [x2]"
+
+  -
+    input:
+      bytes: [ 0xa4, 0x00, 0x80, 0xf9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfm pldl3keep, [x5]"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x00, 0x80, 0xf9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfm pldl3strm, [x6]"
+
+  -
+    input:
+      bytes: [ 0xe8, 0x07, 0x80, 0xf9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfm plil1keep, [sp, #8]"
+
+  -
+    input:
+      bytes: [ 0x69, 0x00, 0x80, 0xf9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfm plil1strm, [x3]"
+
+  -
+    input:
+      bytes: [ 0xaa, 0x08, 0x80, 0xf9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfm plil2keep, [x5, #16]"
+
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0x80, 0xf9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfm plil2strm, [x2]"
+
+  -
+    input:
+      bytes: [ 0xac, 0x00, 0x80, 0xf9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfm plil3keep, [x5]"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x00, 0x80, 0xf9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfm plil3strm, [x6]"
+
+  -
+    input:
+      bytes: [ 0xf0, 0x07, 0x80, 0xf9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfm pstl1keep, [sp, #8]"
+
+  -
+    input:
+      bytes: [ 0x71, 0x00, 0x80, 0xf9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfm pstl1strm, [x3]"
+
+  -
+    input:
+      bytes: [ 0xb2, 0x08, 0x80, 0xf9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfm pstl2keep, [x5, #16]"
+
+  -
+    input:
+      bytes: [ 0x53, 0x00, 0x80, 0xf9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfm pstl2strm, [x2]"
+
+  -
+    input:
+      bytes: [ 0xb4, 0x00, 0x80, 0xf9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfm pstl3keep, [x5]"
+
+  -
+    input:
+      bytes: [ 0xd5, 0x00, 0x80, 0xf9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfm pstl3strm, [x6]"
+
+  -
+    input:
+      bytes: [ 0xef, 0x03, 0x80, 0xf9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfm plislcstrm, [sp]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0x7f, 0x3d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr b31, [sp, #4095]"
+
+  -
+    input:
+      bytes: [ 0x54, 0xfc, 0x7f, 0x7d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr h20, [x2, #8190]"
+
+  -
+    input:
+      bytes: [ 0x6a, 0xfe, 0x7f, 0xbd ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr s10, [x19, #16380]"
+
+  -
+    input:
+      bytes: [ 0x43, 0xfd, 0x7f, 0xfd ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr d3, [x10, #32760]"
+
+  -
+    input:
+      bytes: [ 0xec, 0xff, 0xbf, 0x3d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "str q12, [sp, #65520]"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x6b, 0x65, 0x38 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldrb w3, [sp, x5]"
+
+  -
+    input:
+      bytes: [ 0x69, 0x7b, 0x66, 0x38 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldrb w9, [x27, x6, lsl #0]"
+
+  -
+    input:
+      bytes: [ 0xca, 0x6b, 0xe7, 0x38 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldrsb w10, [x30, x7]"
+
+  -
+    input:
+      bytes: [ 0xab, 0xeb, 0x63, 0x38 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldrb w11, [x29, x3, sxtx]"
+
+  -
+    input:
+      bytes: [ 0x8c, 0xfb, 0x3f, 0x38 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "strb w12, [x28, xzr, sxtx #0]"
+
+  -
+    input:
+      bytes: [ 0x4e, 0x4b, 0x66, 0x38 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldrb w14, [x26, w6, uxtw]"
+
+  -
+    input:
+      bytes: [ 0x2f, 0x5b, 0xe7, 0x38 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldrsb w15, [x25, w7, uxtw #0]"
+
+  -
+    input:
+      bytes: [ 0xf1, 0xca, 0x69, 0x38 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldrb w17, [x23, w9, sxtw]"
+
+  -
+    input:
+      bytes: [ 0xd2, 0xda, 0xaa, 0x38 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldrsb x18, [x22, w10, sxtw #0]"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x6b, 0xe5, 0x78 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldrsh w3, [sp, x5]"
+
+  -
+    input:
+      bytes: [ 0x69, 0x6b, 0xe6, 0x78 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldrsh w9, [x27, x6]"
+
+  -
+    input:
+      bytes: [ 0xca, 0x7b, 0x67, 0x78 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldrh w10, [x30, x7, lsl #1]"
+
+  -
+    input:
+      bytes: [ 0xab, 0xeb, 0x23, 0x78 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "strh w11, [x29, x3, sxtx]"
+
+  -
+    input:
+      bytes: [ 0x8c, 0xeb, 0x7f, 0x78 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldrh w12, [x28, xzr, sxtx]"
+
+  -
+    input:
+      bytes: [ 0x6d, 0xfb, 0xa5, 0x78 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldrsh x13, [x27, x5, sxtx #1]"
+
+  -
+    input:
+      bytes: [ 0x4e, 0x4b, 0x66, 0x78 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldrh w14, [x26, w6, uxtw]"
+
+  -
+    input:
+      bytes: [ 0x2f, 0x4b, 0x67, 0x78 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldrh w15, [x25, w7, uxtw]"
+
+  -
+    input:
+      bytes: [ 0x10, 0x5b, 0xe8, 0x78 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldrsh w16, [x24, w8, uxtw #1]"
+
+  -
+    input:
+      bytes: [ 0xf1, 0xca, 0x69, 0x78 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldrh w17, [x23, w9, sxtw]"
+
+  -
+    input:
+      bytes: [ 0xd2, 0xca, 0x6a, 0x78 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldrh w18, [x22, w10, sxtw]"
+
+  -
+    input:
+      bytes: [ 0xb3, 0xda, 0x3f, 0x78 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "strh w19, [x21, wzr, sxtw #1]"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x6b, 0x65, 0xb8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr w3, [sp, x5]"
+
+  -
+    input:
+      bytes: [ 0x69, 0x6b, 0x66, 0xbc ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr s9, [x27, x6]"
+
+  -
+    input:
+      bytes: [ 0xca, 0x7b, 0x67, 0xb8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr w10, [x30, x7, lsl #2]"
+
+  -
+    input:
+      bytes: [ 0xab, 0xeb, 0x63, 0xb8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr w11, [x29, x3, sxtx]"
+
+  -
+    input:
+      bytes: [ 0x8c, 0xeb, 0x3f, 0xbc ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "str s12, [x28, xzr, sxtx]"
+
+  -
+    input:
+      bytes: [ 0x6d, 0xfb, 0x25, 0xb8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "str w13, [x27, x5, sxtx #2]"
+
+  -
+    input:
+      bytes: [ 0x4e, 0x4b, 0x26, 0xb8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "str w14, [x26, w6, uxtw]"
+
+  -
+    input:
+      bytes: [ 0x2f, 0x4b, 0x67, 0xb8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr w15, [x25, w7, uxtw]"
+
+  -
+    input:
+      bytes: [ 0x10, 0x5b, 0x68, 0xb8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr w16, [x24, w8, uxtw #2]"
+
+  -
+    input:
+      bytes: [ 0xf1, 0xca, 0xa9, 0xb8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldrsw x17, [x23, w9, sxtw]"
+
+  -
+    input:
+      bytes: [ 0xd2, 0xca, 0x6a, 0xb8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr w18, [x22, w10, sxtw]"
+
+  -
+    input:
+      bytes: [ 0xb3, 0xda, 0xbf, 0xb8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldrsw x19, [x21, wzr, sxtw #2]"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x6b, 0x65, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr x3, [sp, x5]"
+
+  -
+    input:
+      bytes: [ 0x69, 0x6b, 0x26, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "str x9, [x27, x6]"
+
+  -
+    input:
+      bytes: [ 0xca, 0x7b, 0x67, 0xfc ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr d10, [x30, x7, lsl #3]"
+
+  -
+    input:
+      bytes: [ 0xab, 0xeb, 0x23, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "str x11, [x29, x3, sxtx]"
+
+  -
+    input:
+      bytes: [ 0x8c, 0xeb, 0x7f, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr x12, [x28, xzr, sxtx]"
+
+  -
+    input:
+      bytes: [ 0x6d, 0xfb, 0x65, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr x13, [x27, x5, sxtx #3]"
+
+  -
+    input:
+      bytes: [ 0x40, 0x4b, 0xa6, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfm pldl1keep, [x26, w6, uxtw]"
+
+  -
+    input:
+      bytes: [ 0x2f, 0x4b, 0x67, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr x15, [x25, w7, uxtw]"
+
+  -
+    input:
+      bytes: [ 0x10, 0x5b, 0x68, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr x16, [x24, w8, uxtw #3]"
+
+  -
+    input:
+      bytes: [ 0xf1, 0xca, 0x69, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr x17, [x23, w9, sxtw]"
+
+  -
+    input:
+      bytes: [ 0xd2, 0xca, 0x6a, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr x18, [x22, w10, sxtw]"
+
+  -
+    input:
+      bytes: [ 0xb3, 0xda, 0x3f, 0xfc ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "str d19, [x21, wzr, sxtw #3]"
+
+  -
+    input:
+      bytes: [ 0x06, 0x68, 0xa5, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "prfm pldslckeep, [x0, x5]"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x6b, 0xe5, 0x3c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr q3, [sp, x5]"
+
+  -
+    input:
+      bytes: [ 0x69, 0x6b, 0xe6, 0x3c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr q9, [x27, x6]"
+
+  -
+    input:
+      bytes: [ 0xca, 0x7b, 0xe7, 0x3c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr q10, [x30, x7, lsl #4]"
+
+  -
+    input:
+      bytes: [ 0xab, 0xeb, 0xa3, 0x3c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "str q11, [x29, x3, sxtx]"
+
+  -
+    input:
+      bytes: [ 0x8c, 0xeb, 0xbf, 0x3c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "str q12, [x28, xzr, sxtx]"
+
+  -
+    input:
+      bytes: [ 0x6d, 0xfb, 0xa5, 0x3c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "str q13, [x27, x5, sxtx #4]"
+
+  -
+    input:
+      bytes: [ 0x4e, 0x4b, 0xe6, 0x3c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr q14, [x26, w6, uxtw]"
+
+  -
+    input:
+      bytes: [ 0x2f, 0x4b, 0xe7, 0x3c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr q15, [x25, w7, uxtw]"
+
+  -
+    input:
+      bytes: [ 0x10, 0x5b, 0xe8, 0x3c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr q16, [x24, w8, uxtw #4]"
+
+  -
+    input:
+      bytes: [ 0xf1, 0xca, 0xe9, 0x3c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr q17, [x23, w9, sxtw]"
+
+  -
+    input:
+      bytes: [ 0xd2, 0xca, 0xaa, 0x3c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "str q18, [x22, w10, sxtw]"
+
+  -
+    input:
+      bytes: [ 0xb3, 0xda, 0xff, 0x3c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr q19, [x21, wzr, sxtw #4]"
+
+  -
+    input:
+      bytes: [ 0x49, 0xf4, 0x0f, 0x38 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "strb w9, [x2], #255"
+
+  -
+    input:
+      bytes: [ 0x6a, 0x14, 0x00, 0x38 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "strb w10, [x3], #1"
+
+  -
+    input:
+      bytes: [ 0x6a, 0x04, 0x10, 0x38 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "strb w10, [x3], #-256"
+
+  -
+    input:
+      bytes: [ 0x49, 0xf4, 0x0f, 0x78 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "strh w9, [x2], #255"
+
+  -
+    input:
+      bytes: [ 0x49, 0x14, 0x00, 0x78 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "strh w9, [x2], #1"
+
+  -
+    input:
+      bytes: [ 0x6a, 0x04, 0x10, 0x78 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "strh w10, [x3], #-256"
+
+  -
+    input:
+      bytes: [ 0xf3, 0xf7, 0x0f, 0xb8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "str w19, [sp], #255"
+
+  -
+    input:
+      bytes: [ 0xd4, 0x17, 0x00, 0xb8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "str w20, [x30], #1"
+
+  -
+    input:
+      bytes: [ 0x95, 0x05, 0x10, 0xb8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "str w21, [x12], #-256"
+
+  -
+    input:
+      bytes: [ 0x3f, 0xf5, 0x0f, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "str xzr, [x9], #255"
+
+  -
+    input:
+      bytes: [ 0x62, 0x14, 0x00, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "str x2, [x3], #1"
+
+  -
+    input:
+      bytes: [ 0x93, 0x05, 0x10, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "str x19, [x12], #-256"
+
+  -
+    input:
+      bytes: [ 0x49, 0xf4, 0x4f, 0x38 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldrb w9, [x2], #255"
+
+  -
+    input:
+      bytes: [ 0x6a, 0x14, 0x40, 0x38 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldrb w10, [x3], #1"
+
+  -
+    input:
+      bytes: [ 0x6a, 0x04, 0x50, 0x38 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldrb w10, [x3], #-256"
+
+  -
+    input:
+      bytes: [ 0x49, 0xf4, 0x4f, 0x78 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldrh w9, [x2], #255"
+
+  -
+    input:
+      bytes: [ 0x49, 0x14, 0x40, 0x78 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldrh w9, [x2], #1"
+
+  -
+    input:
+      bytes: [ 0x6a, 0x04, 0x50, 0x78 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldrh w10, [x3], #-256"
+
+  -
+    input:
+      bytes: [ 0xf3, 0xf7, 0x4f, 0xb8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr w19, [sp], #255"
+
+  -
+    input:
+      bytes: [ 0xd4, 0x17, 0x40, 0xb8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr w20, [x30], #1"
+
+  -
+    input:
+      bytes: [ 0x95, 0x05, 0x50, 0xb8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr w21, [x12], #-256"
+
+  -
+    input:
+      bytes: [ 0x3f, 0xf5, 0x4f, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr xzr, [x9], #255"
+
+  -
+    input:
+      bytes: [ 0x62, 0x14, 0x40, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr x2, [x3], #1"
+
+  -
+    input:
+      bytes: [ 0x93, 0x05, 0x50, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr x19, [x12], #-256"
+
+  -
+    input:
+      bytes: [ 0x3f, 0xf5, 0x8f, 0x38 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldrsb xzr, [x9], #255"
+
+  -
+    input:
+      bytes: [ 0x62, 0x14, 0x80, 0x38 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldrsb x2, [x3], #1"
+
+  -
+    input:
+      bytes: [ 0x93, 0x05, 0x90, 0x38 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldrsb x19, [x12], #-256"
+
+  -
+    input:
+      bytes: [ 0x3f, 0xf5, 0x8f, 0x78 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldrsh xzr, [x9], #255"
+
+  -
+    input:
+      bytes: [ 0x62, 0x14, 0x80, 0x78 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldrsh x2, [x3], #1"
+
+  -
+    input:
+      bytes: [ 0x93, 0x05, 0x90, 0x78 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldrsh x19, [x12], #-256"
+
+  -
+    input:
+      bytes: [ 0x3f, 0xf5, 0x8f, 0xb8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldrsw xzr, [x9], #255"
+
+  -
+    input:
+      bytes: [ 0x62, 0x14, 0x80, 0xb8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldrsw x2, [x3], #1"
+
+  -
+    input:
+      bytes: [ 0x93, 0x05, 0x90, 0xb8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldrsw x19, [x12], #-256"
+
+  -
+    input:
+      bytes: [ 0x3f, 0xf5, 0xcf, 0x38 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldrsb wzr, [x9], #255"
+
+  -
+    input:
+      bytes: [ 0x62, 0x14, 0xc0, 0x38 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldrsb w2, [x3], #1"
+
+  -
+    input:
+      bytes: [ 0x93, 0x05, 0xd0, 0x38 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldrsb w19, [x12], #-256"
+
+  -
+    input:
+      bytes: [ 0x3f, 0xf5, 0xcf, 0x78 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldrsh wzr, [x9], #255"
+
+  -
+    input:
+      bytes: [ 0x62, 0x14, 0xc0, 0x78 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldrsh w2, [x3], #1"
+
+  -
+    input:
+      bytes: [ 0x93, 0x05, 0xd0, 0x78 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldrsh w19, [x12], #-256"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf4, 0x0f, 0x3c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "str b0, [x0], #255"
+
+  -
+    input:
+      bytes: [ 0x63, 0x14, 0x00, 0x3c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "str b3, [x3], #1"
+
+  -
+    input:
+      bytes: [ 0xe5, 0x07, 0x10, 0x3c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "str b5, [sp], #-256"
+
+  -
+    input:
+      bytes: [ 0x4a, 0xf5, 0x0f, 0x7c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "str h10, [x10], #255"
+
+  -
+    input:
+      bytes: [ 0xed, 0x16, 0x00, 0x7c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "str h13, [x23], #1"
+
+  -
+    input:
+      bytes: [ 0xef, 0x07, 0x10, 0x7c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "str h15, [sp], #-256"
+
+  -
+    input:
+      bytes: [ 0x94, 0xf6, 0x0f, 0xbc ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "str s20, [x20], #255"
+
+  -
+    input:
+      bytes: [ 0xf7, 0x16, 0x00, 0xbc ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "str s23, [x23], #1"
+
+  -
+    input:
+      bytes: [ 0x19, 0x04, 0x10, 0xbc ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "str s25, [x0], #-256"
+
+  -
+    input:
+      bytes: [ 0x94, 0xf6, 0x0f, 0xfc ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "str d20, [x20], #255"
+
+  -
+    input:
+      bytes: [ 0xf7, 0x16, 0x00, 0xfc ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "str d23, [x23], #1"
+
+  -
+    input:
+      bytes: [ 0x19, 0x04, 0x10, 0xfc ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "str d25, [x0], #-256"
+
+  -
+    input:
+      bytes: [ 0x00, 0xf4, 0x4f, 0x3c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr b0, [x0], #255"
+
+  -
+    input:
+      bytes: [ 0x63, 0x14, 0x40, 0x3c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr b3, [x3], #1"
+
+  -
+    input:
+      bytes: [ 0xe5, 0x07, 0x50, 0x3c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr b5, [sp], #-256"
+
+  -
+    input:
+      bytes: [ 0x4a, 0xf5, 0x4f, 0x7c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr h10, [x10], #255"
+
+  -
+    input:
+      bytes: [ 0xed, 0x16, 0x40, 0x7c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr h13, [x23], #1"
+
+  -
+    input:
+      bytes: [ 0xef, 0x07, 0x50, 0x7c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr h15, [sp], #-256"
+
+  -
+    input:
+      bytes: [ 0x94, 0xf6, 0x4f, 0xbc ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr s20, [x20], #255"
+
+  -
+    input:
+      bytes: [ 0xf7, 0x16, 0x40, 0xbc ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr s23, [x23], #1"
+
+  -
+    input:
+      bytes: [ 0x19, 0x04, 0x50, 0xbc ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr s25, [x0], #-256"
+
+  -
+    input:
+      bytes: [ 0x94, 0xf6, 0x4f, 0xfc ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr d20, [x20], #255"
+
+  -
+    input:
+      bytes: [ 0xf7, 0x16, 0x40, 0xfc ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr d23, [x23], #1"
+
+  -
+    input:
+      bytes: [ 0x19, 0x04, 0x50, 0xfc ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr d25, [x0], #-256"
+
+  -
+    input:
+      bytes: [ 0x34, 0xf4, 0xcf, 0x3c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr q20, [x1], #255"
+
+  -
+    input:
+      bytes: [ 0x37, 0x15, 0xc0, 0x3c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr q23, [x9], #1"
+
+  -
+    input:
+      bytes: [ 0x99, 0x06, 0xd0, 0x3c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr q25, [x20], #-256"
+
+  -
+    input:
+      bytes: [ 0x2a, 0xf4, 0x8f, 0x3c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "str q10, [x1], #255"
+
+  -
+    input:
+      bytes: [ 0xf6, 0x17, 0x80, 0x3c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "str q22, [sp], #1"
+
+  -
+    input:
+      bytes: [ 0x95, 0x06, 0x90, 0x3c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "str q21, [x20], #-256"
+
+  -
+    input:
+      bytes: [ 0x83, 0x0c, 0x40, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr x3, [x4, #0]!"
+
+  -
+    input:
+      bytes: [ 0xff, 0x0f, 0x40, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr xzr, [sp, #0]!"
+
+  -
+    input:
+      bytes: [ 0x49, 0xfc, 0x0f, 0x38 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "strb w9, [x2, #255]!"
+
+  -
+    input:
+      bytes: [ 0x6a, 0x1c, 0x00, 0x38 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "strb w10, [x3, #1]!"
+
+  -
+    input:
+      bytes: [ 0x6a, 0x0c, 0x10, 0x38 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "strb w10, [x3, #-256]!"
+
+  -
+    input:
+      bytes: [ 0x49, 0xfc, 0x0f, 0x78 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "strh w9, [x2, #255]!"
+
+  -
+    input:
+      bytes: [ 0x49, 0x1c, 0x00, 0x78 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "strh w9, [x2, #1]!"
+
+  -
+    input:
+      bytes: [ 0x6a, 0x0c, 0x10, 0x78 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "strh w10, [x3, #-256]!"
+
+  -
+    input:
+      bytes: [ 0xf3, 0xff, 0x0f, 0xb8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "str w19, [sp, #255]!"
+
+  -
+    input:
+      bytes: [ 0xd4, 0x1f, 0x00, 0xb8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "str w20, [x30, #1]!"
+
+  -
+    input:
+      bytes: [ 0x95, 0x0d, 0x10, 0xb8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "str w21, [x12, #-256]!"
+
+  -
+    input:
+      bytes: [ 0x3f, 0xfd, 0x0f, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "str xzr, [x9, #255]!"
+
+  -
+    input:
+      bytes: [ 0x62, 0x1c, 0x00, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "str x2, [x3, #1]!"
+
+  -
+    input:
+      bytes: [ 0x93, 0x0d, 0x10, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "str x19, [x12, #-256]!"
+
+  -
+    input:
+      bytes: [ 0x49, 0xfc, 0x4f, 0x38 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldrb w9, [x2, #255]!"
+
+  -
+    input:
+      bytes: [ 0x6a, 0x1c, 0x40, 0x38 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldrb w10, [x3, #1]!"
+
+  -
+    input:
+      bytes: [ 0x6a, 0x0c, 0x50, 0x38 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldrb w10, [x3, #-256]!"
+
+  -
+    input:
+      bytes: [ 0x49, 0xfc, 0x4f, 0x78 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldrh w9, [x2, #255]!"
+
+  -
+    input:
+      bytes: [ 0x49, 0x1c, 0x40, 0x78 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldrh w9, [x2, #1]!"
+
+  -
+    input:
+      bytes: [ 0x6a, 0x0c, 0x50, 0x78 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldrh w10, [x3, #-256]!"
+
+  -
+    input:
+      bytes: [ 0xf3, 0xff, 0x4f, 0xb8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr w19, [sp, #255]!"
+
+  -
+    input:
+      bytes: [ 0xd4, 0x1f, 0x40, 0xb8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr w20, [x30, #1]!"
+
+  -
+    input:
+      bytes: [ 0x95, 0x0d, 0x50, 0xb8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr w21, [x12, #-256]!"
+
+  -
+    input:
+      bytes: [ 0x3f, 0xfd, 0x4f, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr xzr, [x9, #255]!"
+
+  -
+    input:
+      bytes: [ 0x62, 0x1c, 0x40, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr x2, [x3, #1]!"
+
+  -
+    input:
+      bytes: [ 0x93, 0x0d, 0x50, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr x19, [x12, #-256]!"
+
+  -
+    input:
+      bytes: [ 0x3f, 0xfd, 0x8f, 0x38 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldrsb xzr, [x9, #255]!"
+
+  -
+    input:
+      bytes: [ 0x62, 0x1c, 0x80, 0x38 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldrsb x2, [x3, #1]!"
+
+  -
+    input:
+      bytes: [ 0x93, 0x0d, 0x90, 0x38 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldrsb x19, [x12, #-256]!"
+
+  -
+    input:
+      bytes: [ 0x3f, 0xfd, 0x8f, 0x78 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldrsh xzr, [x9, #255]!"
+
+  -
+    input:
+      bytes: [ 0x62, 0x1c, 0x80, 0x78 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldrsh x2, [x3, #1]!"
+
+  -
+    input:
+      bytes: [ 0x93, 0x0d, 0x90, 0x78 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldrsh x19, [x12, #-256]!"
+
+  -
+    input:
+      bytes: [ 0x3f, 0xfd, 0x8f, 0xb8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldrsw xzr, [x9, #255]!"
+
+  -
+    input:
+      bytes: [ 0x62, 0x1c, 0x80, 0xb8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldrsw x2, [x3, #1]!"
+
+  -
+    input:
+      bytes: [ 0x93, 0x0d, 0x90, 0xb8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldrsw x19, [x12, #-256]!"
+
+  -
+    input:
+      bytes: [ 0x3f, 0xfd, 0xcf, 0x38 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldrsb wzr, [x9, #255]!"
+
+  -
+    input:
+      bytes: [ 0x62, 0x1c, 0xc0, 0x38 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldrsb w2, [x3, #1]!"
+
+  -
+    input:
+      bytes: [ 0x93, 0x0d, 0xd0, 0x38 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldrsb w19, [x12, #-256]!"
+
+  -
+    input:
+      bytes: [ 0x3f, 0xfd, 0xcf, 0x78 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldrsh wzr, [x9, #255]!"
+
+  -
+    input:
+      bytes: [ 0x62, 0x1c, 0xc0, 0x78 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldrsh w2, [x3, #1]!"
+
+  -
+    input:
+      bytes: [ 0x93, 0x0d, 0xd0, 0x78 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldrsh w19, [x12, #-256]!"
+
+  -
+    input:
+      bytes: [ 0x00, 0xfc, 0x0f, 0x3c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "str b0, [x0, #255]!"
+
+  -
+    input:
+      bytes: [ 0x63, 0x1c, 0x00, 0x3c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "str b3, [x3, #1]!"
+
+  -
+    input:
+      bytes: [ 0xe5, 0x0f, 0x10, 0x3c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "str b5, [sp, #-256]!"
+
+  -
+    input:
+      bytes: [ 0x4a, 0xfd, 0x0f, 0x7c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "str h10, [x10, #255]!"
+
+  -
+    input:
+      bytes: [ 0xed, 0x1e, 0x00, 0x7c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "str h13, [x23, #1]!"
+
+  -
+    input:
+      bytes: [ 0xef, 0x0f, 0x10, 0x7c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "str h15, [sp, #-256]!"
+
+  -
+    input:
+      bytes: [ 0x94, 0xfe, 0x0f, 0xbc ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "str s20, [x20, #255]!"
+
+  -
+    input:
+      bytes: [ 0xf7, 0x1e, 0x00, 0xbc ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "str s23, [x23, #1]!"
+
+  -
+    input:
+      bytes: [ 0x19, 0x0c, 0x10, 0xbc ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "str s25, [x0, #-256]!"
+
+  -
+    input:
+      bytes: [ 0x94, 0xfe, 0x0f, 0xfc ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "str d20, [x20, #255]!"
+
+  -
+    input:
+      bytes: [ 0xf7, 0x1e, 0x00, 0xfc ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "str d23, [x23, #1]!"
+
+  -
+    input:
+      bytes: [ 0x19, 0x0c, 0x10, 0xfc ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "str d25, [x0, #-256]!"
+
+  -
+    input:
+      bytes: [ 0x00, 0xfc, 0x4f, 0x3c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr b0, [x0, #255]!"
+
+  -
+    input:
+      bytes: [ 0x63, 0x1c, 0x40, 0x3c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr b3, [x3, #1]!"
+
+  -
+    input:
+      bytes: [ 0xe5, 0x0f, 0x50, 0x3c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr b5, [sp, #-256]!"
+
+  -
+    input:
+      bytes: [ 0x4a, 0xfd, 0x4f, 0x7c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr h10, [x10, #255]!"
+
+  -
+    input:
+      bytes: [ 0xed, 0x1e, 0x40, 0x7c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr h13, [x23, #1]!"
+
+  -
+    input:
+      bytes: [ 0xef, 0x0f, 0x50, 0x7c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr h15, [sp, #-256]!"
+
+  -
+    input:
+      bytes: [ 0x94, 0xfe, 0x4f, 0xbc ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr s20, [x20, #255]!"
+
+  -
+    input:
+      bytes: [ 0xf7, 0x1e, 0x40, 0xbc ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr s23, [x23, #1]!"
+
+  -
+    input:
+      bytes: [ 0x19, 0x0c, 0x50, 0xbc ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr s25, [x0, #-256]!"
+
+  -
+    input:
+      bytes: [ 0x94, 0xfe, 0x4f, 0xfc ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr d20, [x20, #255]!"
+
+  -
+    input:
+      bytes: [ 0xf7, 0x1e, 0x40, 0xfc ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr d23, [x23, #1]!"
+
+  -
+    input:
+      bytes: [ 0x19, 0x0c, 0x50, 0xfc ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr d25, [x0, #-256]!"
+
+  -
+    input:
+      bytes: [ 0x34, 0xfc, 0xcf, 0x3c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr q20, [x1, #255]!"
+
+  -
+    input:
+      bytes: [ 0x37, 0x1d, 0xc0, 0x3c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr q23, [x9, #1]!"
+
+  -
+    input:
+      bytes: [ 0x99, 0x0e, 0xd0, 0x3c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr q25, [x20, #-256]!"
+
+  -
+    input:
+      bytes: [ 0x2a, 0xfc, 0x8f, 0x3c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "str q10, [x1, #255]!"
+
+  -
+    input:
+      bytes: [ 0xf6, 0x1f, 0x80, 0x3c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "str q22, [sp, #1]!"
+
+  -
+    input:
+      bytes: [ 0x95, 0x0e, 0x90, 0x3c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "str q21, [x20, #-256]!"
+
+  -
+    input:
+      bytes: [ 0xe9, 0x0b, 0x00, 0x38 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "sttrb w9, [sp]"
+
+  -
+    input:
+      bytes: [ 0x9f, 0xf9, 0x0f, 0x78 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "sttrh wzr, [x12, #255]"
+
+  -
+    input:
+      bytes: [ 0x10, 0x08, 0x10, 0xb8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "sttr w16, [x0, #-256]"
+
+  -
+    input:
+      bytes: [ 0xdc, 0x19, 0x00, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "sttr x28, [x14, #1]"
+
+  -
+    input:
+      bytes: [ 0x81, 0xfa, 0x4f, 0x38 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldtrb w1, [x20, #255]"
+
+  -
+    input:
+      bytes: [ 0x34, 0xf8, 0x4f, 0x78 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldtrh w20, [x1, #255]"
+
+  -
+    input:
+      bytes: [ 0xec, 0xfb, 0x4f, 0xb8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldtr w12, [sp, #255]"
+
+  -
+    input:
+      bytes: [ 0x9f, 0xf9, 0x4f, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldtr xzr, [x12, #255]"
+
+  -
+    input:
+      bytes: [ 0xe9, 0x08, 0x90, 0x38 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldtrsb x9, [x7, #-256]"
+
+  -
+    input:
+      bytes: [ 0x71, 0x0a, 0x90, 0x78 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldtrsh x17, [x19, #-256]"
+
+  -
+    input:
+      bytes: [ 0xf4, 0x09, 0x90, 0xb8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldtrsw x20, [x15, #-256]"
+
+  -
+    input:
+      bytes: [ 0x33, 0x08, 0xd0, 0x38 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldtrsb w19, [x1, #-256]"
+
+  -
+    input:
+      bytes: [ 0xaf, 0x0a, 0xd0, 0x78 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldtrsh w15, [x21, #-256]"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x17, 0x40, 0x29 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldp w3, w5, [sp]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xa7, 0x1f, 0x29 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "stp wzr, w9, [sp, #252]"
+
+  -
+    input:
+      bytes: [ 0xe2, 0x7f, 0x60, 0x29 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldp w2, wzr, [sp, #-256]"
+
+  -
+    input:
+      bytes: [ 0xe9, 0xab, 0x40, 0x29 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldp w9, w10, [sp, #4]"
+
+  -
+    input:
+      bytes: [ 0xe9, 0xab, 0x40, 0x69 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldpsw x9, x10, [sp, #4]"
+
+  -
+    input:
+      bytes: [ 0x49, 0x28, 0x60, 0x69 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldpsw x9, x10, [x2, #-256]"
+
+  -
+    input:
+      bytes: [ 0xf4, 0xfb, 0x5f, 0x69 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldpsw x20, x30, [sp, #252]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf4, 0x5f, 0xa9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldp x21, x29, [x2, #504]"
+
+  -
+    input:
+      bytes: [ 0x76, 0x5c, 0x60, 0xa9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldp x22, x23, [x3, #-512]"
+
+  -
+    input:
+      bytes: [ 0x98, 0xe4, 0x40, 0xa9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldp x24, x25, [x4, #8]"
+
+  -
+    input:
+      bytes: [ 0xfd, 0xf3, 0x5f, 0x2d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldp s29, s28, [sp, #252]"
+
+  -
+    input:
+      bytes: [ 0xfb, 0x6b, 0x20, 0x2d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "stp s27, s26, [sp, #-256]"
+
+  -
+    input:
+      bytes: [ 0x61, 0x88, 0x45, 0x2d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldp s1, s2, [x3, #44]"
+
+  -
+    input:
+      bytes: [ 0x23, 0x95, 0x1f, 0x6d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "stp d3, d5, [x9, #504]"
+
+  -
+    input:
+      bytes: [ 0x47, 0x2d, 0x20, 0x6d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "stp d7, d11, [x10, #-512]"
+
+  -
+    input:
+      bytes: [ 0xc2, 0x8f, 0x7f, 0x6d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldp d2, d3, [x30, #-8]"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x17, 0x00, 0xad ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "stp q3, q5, [sp]"
+
+  -
+    input:
+      bytes: [ 0xf1, 0xcf, 0x1f, 0xad ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "stp q17, q19, [sp, #1008]"
+
+  -
+    input:
+      bytes: [ 0x37, 0x74, 0x60, 0xad ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldp q23, q29, [x1, #-1024]"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x17, 0xc0, 0x28 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldp w3, w5, [sp], #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0xa7, 0x9f, 0x28 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "stp wzr, w9, [sp], #252"
+
+  -
+    input:
+      bytes: [ 0xe2, 0x7f, 0xe0, 0x28 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldp w2, wzr, [sp], #-256"
+
+  -
+    input:
+      bytes: [ 0xe9, 0xab, 0xc0, 0x28 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldp w9, w10, [sp], #4"
+
+  -
+    input:
+      bytes: [ 0xe9, 0xab, 0xc0, 0x68 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldpsw x9, x10, [sp], #4"
+
+  -
+    input:
+      bytes: [ 0x49, 0x28, 0xe0, 0x68 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldpsw x9, x10, [x2], #-256"
+
+  -
+    input:
+      bytes: [ 0xf4, 0xfb, 0xdf, 0x68 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldpsw x20, x30, [sp], #252"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf4, 0xdf, 0xa8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldp x21, x29, [x2], #504"
+
+  -
+    input:
+      bytes: [ 0x76, 0x5c, 0xe0, 0xa8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldp x22, x23, [x3], #-512"
+
+  -
+    input:
+      bytes: [ 0x98, 0xe4, 0xc0, 0xa8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldp x24, x25, [x4], #8"
+
+  -
+    input:
+      bytes: [ 0xfd, 0xf3, 0xdf, 0x2c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldp s29, s28, [sp], #252"
+
+  -
+    input:
+      bytes: [ 0xfb, 0x6b, 0xa0, 0x2c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "stp s27, s26, [sp], #-256"
+
+  -
+    input:
+      bytes: [ 0x61, 0x88, 0xc5, 0x2c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldp s1, s2, [x3], #44"
+
+  -
+    input:
+      bytes: [ 0x23, 0x95, 0x9f, 0x6c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "stp d3, d5, [x9], #504"
+
+  -
+    input:
+      bytes: [ 0x47, 0x2d, 0xa0, 0x6c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "stp d7, d11, [x10], #-512"
+
+  -
+    input:
+      bytes: [ 0xc2, 0x8f, 0xff, 0x6c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldp d2, d3, [x30], #-8"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x17, 0x80, 0xac ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "stp q3, q5, [sp], #0"
+
+  -
+    input:
+      bytes: [ 0xf1, 0xcf, 0x9f, 0xac ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "stp q17, q19, [sp], #1008"
+
+  -
+    input:
+      bytes: [ 0x37, 0x74, 0xe0, 0xac ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldp q23, q29, [x1], #-1024"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x17, 0xc0, 0x29 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldp w3, w5, [sp, #0]!"
+
+  -
+    input:
+      bytes: [ 0xff, 0xa7, 0x9f, 0x29 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "stp wzr, w9, [sp, #252]!"
+
+  -
+    input:
+      bytes: [ 0xe2, 0x7f, 0xe0, 0x29 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldp w2, wzr, [sp, #-256]!"
+
+  -
+    input:
+      bytes: [ 0xe9, 0xab, 0xc0, 0x29 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldp w9, w10, [sp, #4]!"
+
+  -
+    input:
+      bytes: [ 0xe9, 0xab, 0xc0, 0x69 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldpsw x9, x10, [sp, #4]!"
+
+  -
+    input:
+      bytes: [ 0x49, 0x28, 0xe0, 0x69 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldpsw x9, x10, [x2, #-256]!"
+
+  -
+    input:
+      bytes: [ 0xf4, 0xfb, 0xdf, 0x69 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldpsw x20, x30, [sp, #252]!"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf4, 0xdf, 0xa9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldp x21, x29, [x2, #504]!"
+
+  -
+    input:
+      bytes: [ 0x76, 0x5c, 0xe0, 0xa9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldp x22, x23, [x3, #-512]!"
+
+  -
+    input:
+      bytes: [ 0x98, 0xe4, 0xc0, 0xa9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldp x24, x25, [x4, #8]!"
+
+  -
+    input:
+      bytes: [ 0xfd, 0xf3, 0xdf, 0x2d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldp s29, s28, [sp, #252]!"
+
+  -
+    input:
+      bytes: [ 0xfb, 0x6b, 0xa0, 0x2d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "stp s27, s26, [sp, #-256]!"
+
+  -
+    input:
+      bytes: [ 0x61, 0x88, 0xc5, 0x2d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldp s1, s2, [x3, #44]!"
+
+  -
+    input:
+      bytes: [ 0x23, 0x95, 0x9f, 0x6d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "stp d3, d5, [x9, #504]!"
+
+  -
+    input:
+      bytes: [ 0x47, 0x2d, 0xa0, 0x6d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "stp d7, d11, [x10, #-512]!"
+
+  -
+    input:
+      bytes: [ 0xc2, 0x8f, 0xff, 0x6d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldp d2, d3, [x30, #-8]!"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x17, 0x80, 0xad ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "stp q3, q5, [sp, #0]!"
+
+  -
+    input:
+      bytes: [ 0xf1, 0xcf, 0x9f, 0xad ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "stp q17, q19, [sp, #1008]!"
+
+  -
+    input:
+      bytes: [ 0x37, 0x74, 0xe0, 0xad ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldp q23, q29, [x1, #-1024]!"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x17, 0x40, 0x28 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnp w3, w5, [sp]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xa7, 0x1f, 0x28 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnp wzr, w9, [sp, #252]"
+
+  -
+    input:
+      bytes: [ 0xe2, 0x7f, 0x60, 0x28 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnp w2, wzr, [sp, #-256]"
+
+  -
+    input:
+      bytes: [ 0xe9, 0xab, 0x40, 0x28 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnp w9, w10, [sp, #4]"
+
+  -
+    input:
+      bytes: [ 0x55, 0xf4, 0x5f, 0xa8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnp x21, x29, [x2, #504]"
+
+  -
+    input:
+      bytes: [ 0x76, 0x5c, 0x60, 0xa8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnp x22, x23, [x3, #-512]"
+
+  -
+    input:
+      bytes: [ 0x98, 0xe4, 0x40, 0xa8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnp x24, x25, [x4, #8]"
+
+  -
+    input:
+      bytes: [ 0xfd, 0xf3, 0x5f, 0x2c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnp s29, s28, [sp, #252]"
+
+  -
+    input:
+      bytes: [ 0xfb, 0x6b, 0x20, 0x2c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnp s27, s26, [sp, #-256]"
+
+  -
+    input:
+      bytes: [ 0x61, 0x88, 0x45, 0x2c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnp s1, s2, [x3, #44]"
+
+  -
+    input:
+      bytes: [ 0x23, 0x95, 0x1f, 0x6c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnp d3, d5, [x9, #504]"
+
+  -
+    input:
+      bytes: [ 0x47, 0x2d, 0x20, 0x6c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnp d7, d11, [x10, #-512]"
+
+  -
+    input:
+      bytes: [ 0xc2, 0x8f, 0x7f, 0x6c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnp d2, d3, [x30, #-8]"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x17, 0x00, 0xac ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnp q3, q5, [sp]"
+
+  -
+    input:
+      bytes: [ 0xf1, 0xcf, 0x1f, 0xac ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "stnp q17, q19, [sp, #1008]"
+
+  -
+    input:
+      bytes: [ 0x37, 0x74, 0x60, 0xac ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldnp q23, q29, [x1, #-1024]"
+
+  -
+    input:
+      bytes: [ 0x23, 0x3d, 0x10, 0x32 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "orr w3, w9, #0xffff0000"
+
+  -
+    input:
+      bytes: [ 0x5f, 0x29, 0x03, 0x32 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "orr wsp, w10, #0xe00000ff"
+
+  -
+    input:
+      bytes: [ 0x49, 0x25, 0x00, 0x32 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "orr w9, w10, #0x3ff"
+
+  -
+    input:
+      bytes: [ 0xee, 0x81, 0x01, 0x12 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "and w14, w15, #0x80008000"
+
+  -
+    input:
+      bytes: [ 0xac, 0xad, 0x0a, 0x12 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "and w12, w13, #0xffc3ffc3"
+
+  -
+    input:
+      bytes: [ 0xeb, 0x87, 0x00, 0x12 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "and w11, wzr, #0x30003"
+
+  -
+    input:
+      bytes: [ 0xc3, 0xc8, 0x03, 0x52 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "eor w3, w6, #0xe0e0e0e0"
+
+  -
+    input:
+      bytes: [ 0xff, 0xc7, 0x00, 0x52 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "eor wsp, wzr, #0x3030303"
+
+  -
+    input:
+      bytes: [ 0x30, 0xc6, 0x01, 0x52 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "eor w16, w17, #0x81818181"
+
+  -
+    input:
+      bytes: [ 0x5f, 0xe6, 0x02, 0x72 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "tst w18, #0xcccccccc"
+
+  -
+    input:
+      bytes: [ 0x93, 0xe6, 0x00, 0x72 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ands w19, w20, #0x33333333"
+
+  -
+    input:
+      bytes: [ 0xd5, 0xe6, 0x01, 0x72 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ands w21, w22, #0x99999999"
+
+  -
+    input:
+      bytes: [ 0x7f, 0xf0, 0x01, 0x72 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "tst w3, #0xaaaaaaaa"
+
+  -
+    input:
+      bytes: [ 0xff, 0xf3, 0x00, 0x72 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "tst wzr, #0x55555555"
+
+  -
+    input:
+      bytes: [ 0xa3, 0x84, 0x66, 0xd2 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "eor x3, x5, #0xffffffffc000000"
+
+  -
+    input:
+      bytes: [ 0x49, 0xb9, 0x40, 0x92 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "and x9, x10, #0x7fffffffffff"
+
+  -
+    input:
+      bytes: [ 0x8b, 0x31, 0x41, 0xb2 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "orr x11, x12, #0x8000000000000fff"
+
+  -
+    input:
+      bytes: [ 0x23, 0x3d, 0x10, 0xb2 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "orr x3, x9, #0xffff0000ffff0000"
+
+  -
+    input:
+      bytes: [ 0x5f, 0x29, 0x03, 0xb2 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "orr sp, x10, #0xe00000ffe00000ff"
+
+  -
+    input:
+      bytes: [ 0x49, 0x25, 0x00, 0xb2 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "orr x9, x10, #0x3ff000003ff"
+
+  -
+    input:
+      bytes: [ 0xee, 0x81, 0x01, 0x92 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "and x14, x15, #0x8000800080008000"
+
+  -
+    input:
+      bytes: [ 0xac, 0xad, 0x0a, 0x92 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "and x12, x13, #0xffc3ffc3ffc3ffc3"
+
+  -
+    input:
+      bytes: [ 0xeb, 0x87, 0x00, 0x92 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "and x11, xzr, #0x3000300030003"
+
+  -
+    input:
+      bytes: [ 0xc3, 0xc8, 0x03, 0xd2 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "eor x3, x6, #0xe0e0e0e0e0e0e0e0"
+
+  -
+    input:
+      bytes: [ 0xff, 0xc7, 0x00, 0xd2 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "eor sp, xzr, #0x303030303030303"
+
+  -
+    input:
+      bytes: [ 0x30, 0xc6, 0x01, 0xd2 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "eor x16, x17, #0x8181818181818181"
+
+  -
+    input:
+      bytes: [ 0x5f, 0xe6, 0x02, 0xf2 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "tst x18, #0xcccccccccccccccc"
+
+  -
+    input:
+      bytes: [ 0x93, 0xe6, 0x00, 0xf2 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ands x19, x20, #0x3333333333333333"
+
+  -
+    input:
+      bytes: [ 0xd5, 0xe6, 0x01, 0xf2 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ands x21, x22, #0x9999999999999999"
+
+  -
+    input:
+      bytes: [ 0x7f, 0xf0, 0x01, 0xf2 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "tst x3, #0xaaaaaaaaaaaaaaaa"
+
+  -
+    input:
+      bytes: [ 0xff, 0xf3, 0x00, 0xf2 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "tst xzr, #0x5555555555555555"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x8f, 0x00, 0x32 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov w3, #983055"
+
+  -
+    input:
+      bytes: [ 0xea, 0xf3, 0x01, 0xb2 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov x10, #-6148914691236517206"
+
+  -
+    input:
+      bytes: [ 0x62, 0x78, 0x1e, 0x12 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "and w2, w3, #0xfffffffd"
+
+  -
+    input:
+      bytes: [ 0x20, 0x78, 0x1e, 0x32 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "orr w0, w1, #0xfffffffd"
+
+  -
+    input:
+      bytes: [ 0x30, 0x76, 0x1d, 0x52 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "eor w16, w17, #0xfffffff9"
+
+  -
+    input:
+      bytes: [ 0x93, 0x6e, 0x1c, 0x72 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ands w19, w20, #0xfffffff0"
+
+  -
+    input:
+      bytes: [ 0xec, 0x02, 0x15, 0x0a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "and w12, w23, w21"
+
+  -
+    input:
+      bytes: [ 0xf0, 0x05, 0x01, 0x0a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "and w16, w15, w1, lsl #1"
+
+  -
+    input:
+      bytes: [ 0x89, 0x7c, 0x0a, 0x0a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "and w9, w4, w10, lsl #31"
+
+  -
+    input:
+      bytes: [ 0xc3, 0x03, 0x0b, 0x0a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "and w3, w30, w11"
+
+  -
+    input:
+      bytes: [ 0xa3, 0xfc, 0x07, 0x8a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "and x3, x5, x7, lsl #63"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x11, 0x93, 0x8a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "and x5, x14, x19, asr #4"
+
+  -
+    input:
+      bytes: [ 0x23, 0x7e, 0xd3, 0x0a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "and w3, w17, w19, ror #31"
+
+  -
+    input:
+      bytes: [ 0x40, 0x44, 0x5f, 0x0a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "and w0, w2, wzr, lsr #17"
+
+  -
+    input:
+      bytes: [ 0xc3, 0x03, 0x8b, 0x0a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "and w3, w30, w11, asr #0"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x00, 0x1a, 0x8a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "and xzr, x4, x26"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x03, 0xd4, 0x0a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "and w3, wzr, w20, ror #0"
+
+  -
+    input:
+      bytes: [ 0x87, 0xfe, 0x9f, 0x8a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "and x7, x20, xzr, asr #63"
+
+  -
+    input:
+      bytes: [ 0x8d, 0xbe, 0x2e, 0x8a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "bic x13, x20, x14, lsl #47"
+
+  -
+    input:
+      bytes: [ 0xe2, 0x00, 0x29, 0x0a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "bic w2, w7, w9"
+
+  -
+    input:
+      bytes: [ 0xe2, 0x7c, 0x80, 0x2a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "orr w2, w7, w0, asr #31"
+
+  -
+    input:
+      bytes: [ 0x28, 0x31, 0x0a, 0xaa ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "orr x8, x9, x10, lsl #12"
+
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0xa7, 0xaa ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "orn x3, x5, x7, asr #0"
+
+  -
+    input:
+      bytes: [ 0xa2, 0x00, 0x3d, 0x2a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "orn w2, w5, w29"
+
+  -
+    input:
+      bytes: [ 0xe7, 0x07, 0x09, 0x6a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ands w7, wzr, w9, lsl #1"
+
+  -
+    input:
+      bytes: [ 0xa3, 0xfc, 0xd4, 0xea ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ands x3, x5, x20, ror #63"
+
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0x27, 0x6a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "bics w3, w5, w7"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x07, 0x23, 0xea ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "bics x3, xzr, x3, lsl #1"
+
+  -
+    input:
+      bytes: [ 0x7f, 0x7c, 0x07, 0x6a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "tst w3, w7, lsl #31"
+
+  -
+    input:
+      bytes: [ 0x5f, 0x00, 0x94, 0xea ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "tst x2, x20, asr #0"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x03, 0x06, 0xaa ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov x3, x6"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x03, 0x1f, 0xaa ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov x3, xzr"
+
+  -
+    input:
+      bytes: [ 0xff, 0x03, 0x02, 0x2a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov wzr, w2"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x03, 0x05, 0x2a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov w3, w5"
+
+  -
+    input:
+      bytes: [ 0xe1, 0xff, 0x9f, 0x52 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov w1, #65535"
+
+  -
+    input:
+      bytes: [ 0x02, 0x00, 0xa0, 0x52 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "movz w2, #0, lsl #16"
+
+  -
+    input:
+      bytes: [ 0x42, 0x9a, 0x80, 0x12 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov w2, #-1235"
+
+  -
+    input:
+      bytes: [ 0x42, 0x9a, 0xc0, 0xd2 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov x2, #5299989643264"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x1c, 0xe2, 0xf2 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "movk xzr, #4321, lsl #48"
+
+  -
+    input:
+      bytes: [ 0x1e, 0x00, 0x00, 0xb0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "adrp x30, #4096"
+
+  -
+    input:
+      bytes: [ 0x14, 0x00, 0x00, 0x10 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "adr x20, #0"
+
+  -
+    input:
+      bytes: [ 0xe9, 0xff, 0xff, 0x70 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "adr x9, #-1"
+
+  -
+    input:
+      bytes: [ 0xe5, 0xff, 0x7f, 0x70 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "adr x5, #1048575"
+
+  -
+    input:
+      bytes: [ 0xe9, 0xff, 0x7f, 0x70 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "adr x9, #1048575"
+
+  -
+    input:
+      bytes: [ 0x02, 0x00, 0x80, 0x10 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "adr x2, #-1048576"
+
+  -
+    input:
+      bytes: [ 0xe9, 0xff, 0x7f, 0xf0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "adrp x9, #4294963200"
+
+  -
+    input:
+      bytes: [ 0x14, 0x00, 0x80, 0x90 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "adrp x20, #-4294967296"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x20, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "nop"
+
+  -
+    input:
+      bytes: [ 0xff, 0x2f, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "hint #127"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x20, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "nop"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x20, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "yield"
+
+  -
+    input:
+      bytes: [ 0x5f, 0x20, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "wfe"
+
+  -
+    input:
+      bytes: [ 0x7f, 0x20, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "wfi"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x20, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "sev"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x20, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "sevl"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x20, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "dgh"
+
+  -
+    input:
+      bytes: [ 0x5f, 0x3f, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "clrex"
+
+  -
+    input:
+      bytes: [ 0x5f, 0x30, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "clrex #0"
+
+  -
+    input:
+      bytes: [ 0x5f, 0x37, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "clrex #7"
+
+  -
+    input:
+      bytes: [ 0x5f, 0x3f, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "clrex"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x30, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ssbb"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x34, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "pssbb"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x3c, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "dfb"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x3f, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "dsb sy"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x31, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "dsb oshld"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x32, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "dsb oshst"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x33, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "dsb osh"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x35, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "dsb nshld"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x36, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "dsb nshst"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x37, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "dsb nsh"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x39, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "dsb ishld"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x3a, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "dsb ishst"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x3b, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "dsb ish"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x3d, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "dsb ld"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x3e, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "dsb st"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x3f, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "dsb sy"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x30, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "dmb #0"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x3c, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "dmb #12"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x3f, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "dmb sy"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x31, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "dmb oshld"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x32, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "dmb oshst"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x33, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "dmb osh"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x35, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "dmb nshld"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x36, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "dmb nshst"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x37, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "dmb nsh"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x39, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "dmb ishld"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x3a, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "dmb ishst"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x3b, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "dmb ish"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x3d, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "dmb ld"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x3e, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "dmb st"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x3f, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "dmb sy"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x3f, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "isb"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x3f, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "isb"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x3c, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "isb #12"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x40, 0x00, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPSel, #0"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x4f, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr DAIFSet, #15"
+
+  -
+    input:
+      bytes: [ 0xff, 0x4c, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr DAIFClr, #12"
+
+  -
+    input:
+      bytes: [ 0xe5, 0x59, 0x0f, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "sys #7, c5, c9, #7, x5"
+
+  -
+    input:
+      bytes: [ 0x5f, 0xff, 0x08, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "sys #0, c15, c15, #2"
+
+  -
+    input:
+      bytes: [ 0xe9, 0x59, 0x2f, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "sysl x9, #7, c5, c9, #7"
+
+  -
+    input:
+      bytes: [ 0x41, 0xff, 0x28, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "sysl x1, #0, c15, c15, #2"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x71, 0x08, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ic ialluis"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x75, 0x08, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ic iallu"
+
+  -
+    input:
+      bytes: [ 0x29, 0x75, 0x0b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ic ivau, x9"
+
+  -
+    input:
+      bytes: [ 0x2c, 0x74, 0x0b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "dc zva, x12"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x76, 0x08, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "dc ivac, xzr"
+
+  -
+    input:
+      bytes: [ 0x42, 0x76, 0x08, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "dc isw, x2"
+
+  -
+    input:
+      bytes: [ 0x29, 0x7a, 0x0b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "dc cvac, x9"
+
+  -
+    input:
+      bytes: [ 0x4a, 0x7a, 0x08, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "dc csw, x10"
+
+  -
+    input:
+      bytes: [ 0x20, 0x7b, 0x0b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "dc cvau, x0"
+
+  -
+    input:
+      bytes: [ 0x23, 0x7e, 0x0b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "dc civac, x3"
+
+  -
+    input:
+      bytes: [ 0x5e, 0x7e, 0x08, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "dc cisw, x30"
+
+  -
+    input:
+      bytes: [ 0x13, 0x78, 0x08, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "at s1e1r, x19"
+
+  -
+    input:
+      bytes: [ 0x13, 0x78, 0x0c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "at s1e2r, x19"
+
+  -
+    input:
+      bytes: [ 0x13, 0x78, 0x0e, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "at s1e3r, x19"
+
+  -
+    input:
+      bytes: [ 0x33, 0x78, 0x08, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "at s1e1w, x19"
+
+  -
+    input:
+      bytes: [ 0x33, 0x78, 0x0c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "at s1e2w, x19"
+
+  -
+    input:
+      bytes: [ 0x33, 0x78, 0x0e, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "at s1e3w, x19"
+
+  -
+    input:
+      bytes: [ 0x53, 0x78, 0x08, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "at s1e0r, x19"
+
+  -
+    input:
+      bytes: [ 0x73, 0x78, 0x08, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "at s1e0w, x19"
+
+  -
+    input:
+      bytes: [ 0x94, 0x78, 0x0c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "at s12e1r, x20"
+
+  -
+    input:
+      bytes: [ 0xb4, 0x78, 0x0c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "at s12e1w, x20"
+
+  -
+    input:
+      bytes: [ 0xd4, 0x78, 0x0c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "at s12e0r, x20"
+
+  -
+    input:
+      bytes: [ 0xf4, 0x78, 0x0c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "at s12e0w, x20"
+
+  -
+    input:
+      bytes: [ 0x24, 0x80, 0x0c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "tlbi ipas2e1is, x4"
+
+  -
+    input:
+      bytes: [ 0xa9, 0x80, 0x0c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "tlbi ipas2le1is, x9"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x83, 0x08, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "tlbi vmalle1is"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x83, 0x0c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "tlbi alle2is"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x83, 0x0e, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "tlbi alle3is"
+
+  -
+    input:
+      bytes: [ 0x21, 0x83, 0x08, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "tlbi vae1is, x1"
+
+  -
+    input:
+      bytes: [ 0x22, 0x83, 0x0c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "tlbi vae2is, x2"
+
+  -
+    input:
+      bytes: [ 0x23, 0x83, 0x0e, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "tlbi vae3is, x3"
+
+  -
+    input:
+      bytes: [ 0x45, 0x83, 0x08, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "tlbi aside1is, x5"
+
+  -
+    input:
+      bytes: [ 0x69, 0x83, 0x08, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "tlbi vaae1is, x9"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x83, 0x0c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "tlbi alle1is"
+
+  -
+    input:
+      bytes: [ 0xaa, 0x83, 0x08, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "tlbi vale1is, x10"
+
+  -
+    input:
+      bytes: [ 0xab, 0x83, 0x0c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "tlbi vale2is, x11"
+
+  -
+    input:
+      bytes: [ 0xad, 0x83, 0x0e, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "tlbi vale3is, x13"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x83, 0x0c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "tlbi vmalls12e1is"
+
+  -
+    input:
+      bytes: [ 0xee, 0x83, 0x08, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "tlbi vaale1is, x14"
+
+  -
+    input:
+      bytes: [ 0x2f, 0x84, 0x0c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "tlbi ipas2e1, x15"
+
+  -
+    input:
+      bytes: [ 0xb0, 0x84, 0x0c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "tlbi ipas2le1, x16"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x87, 0x08, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "tlbi vmalle1"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x87, 0x0c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "tlbi alle2"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x87, 0x0e, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "tlbi alle3"
+
+  -
+    input:
+      bytes: [ 0x31, 0x87, 0x08, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "tlbi vae1, x17"
+
+  -
+    input:
+      bytes: [ 0x32, 0x87, 0x0c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "tlbi vae2, x18"
+
+  -
+    input:
+      bytes: [ 0x33, 0x87, 0x0e, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "tlbi vae3, x19"
+
+  -
+    input:
+      bytes: [ 0x54, 0x87, 0x08, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "tlbi aside1, x20"
+
+  -
+    input:
+      bytes: [ 0x75, 0x87, 0x08, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "tlbi vaae1, x21"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x87, 0x0c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "tlbi alle1"
+
+  -
+    input:
+      bytes: [ 0xb6, 0x87, 0x08, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "tlbi vale1, x22"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x87, 0x0c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "tlbi vale2, x23"
+
+  -
+    input:
+      bytes: [ 0xb8, 0x87, 0x0e, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "tlbi vale3, x24"
+
+  -
+    input:
+      bytes: [ 0xdf, 0x87, 0x0c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "tlbi vmalls12e1"
+
+  -
+    input:
+      bytes: [ 0xf9, 0x87, 0x08, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "tlbi vaale1, x25"
+
+  -
+    input:
+      bytes: [ 0x0c, 0x00, 0x12, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TEECR32_EL1, x12"
+
+  -
+    input:
+      bytes: [ 0x4c, 0x00, 0x10, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr OSDTRRX_EL1, x12"
+
+  -
+    input:
+      bytes: [ 0x0c, 0x02, 0x10, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr MDCCINT_EL1, x12"
+
+  -
+    input:
+      bytes: [ 0x4c, 0x02, 0x10, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr MDSCR_EL1, x12"
+
+  -
+    input:
+      bytes: [ 0x4c, 0x03, 0x10, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr OSDTRTX_EL1, x12"
+
+  -
+    input:
+      bytes: [ 0x0c, 0x04, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr DBGDTR_EL0, x12"
+
+  -
+    input:
+      bytes: [ 0x0c, 0x05, 0x13, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr DBGDTRTX_EL0, x12"
+
+  -
+    input:
+      bytes: [ 0x4c, 0x06, 0x10, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr OSECCR_EL1, x12"
+
+  -
+    input:
+      bytes: [ 0x0c, 0x07, 0x14, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr DBGVCR32_EL2, x12"
+
+  -
+    input:
+      bytes: [ 0x8c, 0x00, 0x10, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr DBGBVR0_EL1, x12"
+
+  -
+    input:
+      bytes: [ 0x8c, 0x01, 0x10, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr DBGBVR1_EL1, x12"
+
+  -
+    input:
+      bytes: [ 0x8c, 0x02, 0x10, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr DBGBVR2_EL1, x12"
+
+  -
+    input:
+      bytes: [ 0x8c, 0x03, 0x10, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr DBGBVR3_EL1, x12"
+
+  -
+    input:
+      bytes: [ 0x8c, 0x04, 0x10, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr DBGBVR4_EL1, x12"
+
+  -
+    input:
+      bytes: [ 0x8c, 0x05, 0x10, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr DBGBVR5_EL1, x12"
+
+  -
+    input:
+      bytes: [ 0x8c, 0x06, 0x10, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr DBGBVR6_EL1, x12"
+
+  -
+    input:
+      bytes: [ 0x8c, 0x07, 0x10, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr DBGBVR7_EL1, x12"
+
+  -
+    input:
+      bytes: [ 0x8c, 0x08, 0x10, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr DBGBVR8_EL1, x12"
+
+  -
+    input:
+      bytes: [ 0x8c, 0x09, 0x10, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr DBGBVR9_EL1, x12"
+
+  -
+    input:
+      bytes: [ 0x8c, 0x0a, 0x10, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr DBGBVR10_EL1, x12"
+
+  -
+    input:
+      bytes: [ 0x8c, 0x0b, 0x10, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr DBGBVR11_EL1, x12"
+
+  -
+    input:
+      bytes: [ 0x8c, 0x0c, 0x10, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr DBGBVR12_EL1, x12"
+
+  -
+    input:
+      bytes: [ 0x8c, 0x0d, 0x10, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr DBGBVR13_EL1, x12"
+
+  -
+    input:
+      bytes: [ 0x8c, 0x0e, 0x10, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr DBGBVR14_EL1, x12"
+
+  -
+    input:
+      bytes: [ 0x8c, 0x0f, 0x10, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr DBGBVR15_EL1, x12"
+
+  -
+    input:
+      bytes: [ 0xac, 0x00, 0x10, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr DBGBCR0_EL1, x12"
+
+  -
+    input:
+      bytes: [ 0xac, 0x01, 0x10, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr DBGBCR1_EL1, x12"
+
+  -
+    input:
+      bytes: [ 0xac, 0x02, 0x10, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr DBGBCR2_EL1, x12"
+
+  -
+    input:
+      bytes: [ 0xac, 0x03, 0x10, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr DBGBCR3_EL1, x12"
+
+  -
+    input:
+      bytes: [ 0xac, 0x04, 0x10, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr DBGBCR4_EL1, x12"
+
+  -
+    input:
+      bytes: [ 0xac, 0x05, 0x10, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr DBGBCR5_EL1, x12"
+
+  -
+    input:
+      bytes: [ 0xac, 0x06, 0x10, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr DBGBCR6_EL1, x12"
+
+  -
+    input:
+      bytes: [ 0xac, 0x07, 0x10, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr DBGBCR7_EL1, x12"
+
+  -
+    input:
+      bytes: [ 0xac, 0x08, 0x10, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr DBGBCR8_EL1, x12"
+
+  -
+    input:
+      bytes: [ 0xac, 0x09, 0x10, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr DBGBCR9_EL1, x12"
+
+  -
+    input:
+      bytes: [ 0xac, 0x0a, 0x10, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr DBGBCR10_EL1, x12"
+
+  -
+    input:
+      bytes: [ 0xac, 0x0b, 0x10, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr DBGBCR11_EL1, x12"
+
+  -
+    input:
+      bytes: [ 0xac, 0x0c, 0x10, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr DBGBCR12_EL1, x12"
+
+  -
+    input:
+      bytes: [ 0xac, 0x0d, 0x10, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr DBGBCR13_EL1, x12"
+
+  -
+    input:
+      bytes: [ 0xac, 0x0e, 0x10, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr DBGBCR14_EL1, x12"
+
+  -
+    input:
+      bytes: [ 0xac, 0x0f, 0x10, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr DBGBCR15_EL1, x12"
+
+  -
+    input:
+      bytes: [ 0xcc, 0x00, 0x10, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr DBGWVR0_EL1, x12"
+
+  -
+    input:
+      bytes: [ 0xcc, 0x01, 0x10, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr DBGWVR1_EL1, x12"
+
+  -
+    input:
+      bytes: [ 0xcc, 0x02, 0x10, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr DBGWVR2_EL1, x12"
+
+  -
+    input:
+      bytes: [ 0xcc, 0x03, 0x10, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr DBGWVR3_EL1, x12"
+
+  -
+    input:
+      bytes: [ 0xcc, 0x04, 0x10, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr DBGWVR4_EL1, x12"
+
+  -
+    input:
+      bytes: [ 0xcc, 0x05, 0x10, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr DBGWVR5_EL1, x12"
+
+  -
+    input:
+      bytes: [ 0xcc, 0x06, 0x10, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr DBGWVR6_EL1, x12"
+
+  -
+    input:
+      bytes: [ 0xcc, 0x07, 0x10, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr DBGWVR7_EL1, x12"
+
+  -
+    input:
+      bytes: [ 0xcc, 0x08, 0x10, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr DBGWVR8_EL1, x12"
+
+  -
+    input:
+      bytes: [ 0xcc, 0x09, 0x10, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr DBGWVR9_EL1, x12"
+
+  -
+    input:
+      bytes: [ 0xcc, 0x0a, 0x10, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr DBGWVR10_EL1, x12"
+
+  -
+    input:
+      bytes: [ 0xcc, 0x0b, 0x10, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr DBGWVR11_EL1, x12"
+
+  -
+    input:
+      bytes: [ 0xcc, 0x0c, 0x10, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr DBGWVR12_EL1, x12"
+
+  -
+    input:
+      bytes: [ 0xcc, 0x0d, 0x10, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr DBGWVR13_EL1, x12"
+
+  -
+    input:
+      bytes: [ 0xcc, 0x0e, 0x10, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr DBGWVR14_EL1, x12"
+
+  -
+    input:
+      bytes: [ 0xcc, 0x0f, 0x10, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr DBGWVR15_EL1, x12"
+
+  -
+    input:
+      bytes: [ 0xec, 0x00, 0x10, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr DBGWCR0_EL1, x12"
+
+  -
+    input:
+      bytes: [ 0xec, 0x01, 0x10, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr DBGWCR1_EL1, x12"
+
+  -
+    input:
+      bytes: [ 0xec, 0x02, 0x10, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr DBGWCR2_EL1, x12"
+
+  -
+    input:
+      bytes: [ 0xec, 0x03, 0x10, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr DBGWCR3_EL1, x12"
+
+  -
+    input:
+      bytes: [ 0xec, 0x04, 0x10, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr DBGWCR4_EL1, x12"
+
+  -
+    input:
+      bytes: [ 0xec, 0x05, 0x10, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr DBGWCR5_EL1, x12"
+
+  -
+    input:
+      bytes: [ 0xec, 0x06, 0x10, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr DBGWCR6_EL1, x12"
+
+  -
+    input:
+      bytes: [ 0xec, 0x07, 0x10, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr DBGWCR7_EL1, x12"
+
+  -
+    input:
+      bytes: [ 0xec, 0x08, 0x10, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr DBGWCR8_EL1, x12"
+
+  -
+    input:
+      bytes: [ 0xec, 0x09, 0x10, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr DBGWCR9_EL1, x12"
+
+  -
+    input:
+      bytes: [ 0xec, 0x0a, 0x10, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr DBGWCR10_EL1, x12"
+
+  -
+    input:
+      bytes: [ 0xec, 0x0b, 0x10, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr DBGWCR11_EL1, x12"
+
+  -
+    input:
+      bytes: [ 0xec, 0x0c, 0x10, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr DBGWCR12_EL1, x12"
+
+  -
+    input:
+      bytes: [ 0xec, 0x0d, 0x10, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr DBGWCR13_EL1, x12"
+
+  -
+    input:
+      bytes: [ 0xec, 0x0e, 0x10, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr DBGWCR14_EL1, x12"
+
+  -
+    input:
+      bytes: [ 0xec, 0x0f, 0x10, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr DBGWCR15_EL1, x12"
+
+  -
+    input:
+      bytes: [ 0x0c, 0x10, 0x12, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TEEHBR32_EL1, x12"
+
+  -
+    input:
+      bytes: [ 0x8c, 0x10, 0x10, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr OSLAR_EL1, x12"
+
+  -
+    input:
+      bytes: [ 0x8c, 0x13, 0x10, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr OSDLR_EL1, x12"
+
+  -
+    input:
+      bytes: [ 0x8c, 0x14, 0x10, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr DBGPRCR_EL1, x12"
+
+  -
+    input:
+      bytes: [ 0xcc, 0x78, 0x10, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr DBGCLAIMSET_EL1, x12"
+
+  -
+    input:
+      bytes: [ 0xcc, 0x79, 0x10, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr DBGCLAIMCLR_EL1, x12"
+
+  -
+    input:
+      bytes: [ 0x0c, 0x00, 0x1a, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr CSSELR_EL1, x12"
+
+  -
+    input:
+      bytes: [ 0x0c, 0x00, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr VPIDR_EL2, x12"
+
+  -
+    input:
+      bytes: [ 0xac, 0x00, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr VMPIDR_EL2, x12"
+
+  -
+    input:
+      bytes: [ 0x0c, 0x10, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SCTLR_EL1, x12"
+
+  -
+    input:
+      bytes: [ 0x0c, 0x10, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SCTLR_EL2, x12"
+
+  -
+    input:
+      bytes: [ 0x0c, 0x10, 0x1e, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SCTLR_EL3, x12"
+
+  -
+    input:
+      bytes: [ 0x2c, 0x10, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ACTLR_EL1, x12"
+
+  -
+    input:
+      bytes: [ 0x2c, 0x10, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ACTLR_EL2, x12"
+
+  -
+    input:
+      bytes: [ 0x2c, 0x10, 0x1e, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ACTLR_EL3, x12"
+
+  -
+    input:
+      bytes: [ 0x4c, 0x10, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr CPACR_EL1, x12"
+
+  -
+    input:
+      bytes: [ 0x0c, 0x11, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr HCR_EL2, x12"
+
+  -
+    input:
+      bytes: [ 0x0c, 0x11, 0x1e, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SCR_EL3, x12"
+
+  -
+    input:
+      bytes: [ 0x2c, 0x11, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr MDCR_EL2, x12"
+
+  -
+    input:
+      bytes: [ 0x2c, 0x11, 0x1e, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SDER32_EL3, x12"
+
+  -
+    input:
+      bytes: [ 0x4c, 0x11, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr CPTR_EL2, x12"
+
+  -
+    input:
+      bytes: [ 0x4c, 0x11, 0x1e, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr CPTR_EL3, x12"
+
+  -
+    input:
+      bytes: [ 0x6c, 0x11, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr HSTR_EL2, x12"
+
+  -
+    input:
+      bytes: [ 0xec, 0x11, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr HACR_EL2, x12"
+
+  -
+    input:
+      bytes: [ 0x2c, 0x13, 0x1e, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr MDCR_EL3, x12"
+
+  -
+    input:
+      bytes: [ 0x0c, 0x20, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TTBR0_EL1, x12"
+
+  -
+    input:
+      bytes: [ 0x0c, 0x20, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TTBR0_EL2, x12"
+
+  -
+    input:
+      bytes: [ 0x0c, 0x20, 0x1e, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TTBR0_EL3, x12"
+
+  -
+    input:
+      bytes: [ 0x2c, 0x20, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TTBR1_EL1, x12"
+
+  -
+    input:
+      bytes: [ 0x4c, 0x20, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TCR_EL1, x12"
+
+  -
+    input:
+      bytes: [ 0x4c, 0x20, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TCR_EL2, x12"
+
+  -
+    input:
+      bytes: [ 0x4c, 0x20, 0x1e, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TCR_EL3, x12"
+
+  -
+    input:
+      bytes: [ 0x0c, 0x21, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr VTTBR_EL2, x12"
+
+  -
+    input:
+      bytes: [ 0x4c, 0x21, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr VTCR_EL2, x12"
+
+  -
+    input:
+      bytes: [ 0x0c, 0x30, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr DACR32_EL2, x12"
+
+  -
+    input:
+      bytes: [ 0x0c, 0x40, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPSR_EL1, x12"
+
+  -
+    input:
+      bytes: [ 0x0c, 0x40, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPSR_EL2, x12"
+
+  -
+    input:
+      bytes: [ 0x0c, 0x40, 0x1e, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPSR_EL3, x12"
+
+  -
+    input:
+      bytes: [ 0x2c, 0x40, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ELR_EL1, x12"
+
+  -
+    input:
+      bytes: [ 0x2c, 0x40, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ELR_EL2, x12"
+
+  -
+    input:
+      bytes: [ 0x2c, 0x40, 0x1e, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ELR_EL3, x12"
+
+  -
+    input:
+      bytes: [ 0x0c, 0x41, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SP_EL0, x12"
+
+  -
+    input:
+      bytes: [ 0x0c, 0x41, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SP_EL1, x12"
+
+  -
+    input:
+      bytes: [ 0x0c, 0x41, 0x1e, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SP_EL2, x12"
+
+  -
+    input:
+      bytes: [ 0x0c, 0x42, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPSel, x12"
+
+  -
+    input:
+      bytes: [ 0x0c, 0x42, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr NZCV, x12"
+
+  -
+    input:
+      bytes: [ 0x2c, 0x42, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr DAIF, x12"
+
+  -
+    input:
+      bytes: [ 0x0c, 0x43, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPSR_irq, x12"
+
+  -
+    input:
+      bytes: [ 0x2c, 0x43, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPSR_abt, x12"
+
+  -
+    input:
+      bytes: [ 0x4c, 0x43, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPSR_und, x12"
+
+  -
+    input:
+      bytes: [ 0x6c, 0x43, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SPSR_fiq, x12"
+
+  -
+    input:
+      bytes: [ 0x0c, 0x44, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr FPCR, x12"
+
+  -
+    input:
+      bytes: [ 0x2c, 0x44, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr FPSR, x12"
+
+  -
+    input:
+      bytes: [ 0x0c, 0x45, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr DSPSR_EL0, x12"
+
+  -
+    input:
+      bytes: [ 0x2c, 0x45, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr DLR_EL0, x12"
+
+  -
+    input:
+      bytes: [ 0x2c, 0x50, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr IFSR32_EL2, x12"
+
+  -
+    input:
+      bytes: [ 0x0c, 0x51, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AFSR0_EL1, x12"
+
+  -
+    input:
+      bytes: [ 0x0c, 0x51, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AFSR0_EL2, x12"
+
+  -
+    input:
+      bytes: [ 0x0c, 0x51, 0x1e, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AFSR0_EL3, x12"
+
+  -
+    input:
+      bytes: [ 0x2c, 0x51, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AFSR1_EL1, x12"
+
+  -
+    input:
+      bytes: [ 0x2c, 0x51, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AFSR1_EL2, x12"
+
+  -
+    input:
+      bytes: [ 0x2c, 0x51, 0x1e, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AFSR1_EL3, x12"
+
+  -
+    input:
+      bytes: [ 0x0c, 0x52, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ESR_EL1, x12"
+
+  -
+    input:
+      bytes: [ 0x0c, 0x52, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ESR_EL2, x12"
+
+  -
+    input:
+      bytes: [ 0x0c, 0x52, 0x1e, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ESR_EL3, x12"
+
+  -
+    input:
+      bytes: [ 0x0c, 0x53, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr FPEXC32_EL2, x12"
+
+  -
+    input:
+      bytes: [ 0x0c, 0x60, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr FAR_EL1, x12"
+
+  -
+    input:
+      bytes: [ 0x0c, 0x60, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr FAR_EL2, x12"
+
+  -
+    input:
+      bytes: [ 0x0c, 0x60, 0x1e, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr FAR_EL3, x12"
+
+  -
+    input:
+      bytes: [ 0x8c, 0x60, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr HPFAR_EL2, x12"
+
+  -
+    input:
+      bytes: [ 0x0c, 0x74, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PAR_EL1, x12"
+
+  -
+    input:
+      bytes: [ 0x0c, 0x9c, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PMCR_EL0, x12"
+
+  -
+    input:
+      bytes: [ 0x2c, 0x9c, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PMCNTENSET_EL0, x12"
+
+  -
+    input:
+      bytes: [ 0x4c, 0x9c, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PMCNTENCLR_EL0, x12"
+
+  -
+    input:
+      bytes: [ 0x6c, 0x9c, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PMOVSCLR_EL0, x12"
+
+  -
+    input:
+      bytes: [ 0xac, 0x9c, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PMSELR_EL0, x12"
+
+  -
+    input:
+      bytes: [ 0x0c, 0x9d, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PMCCNTR_EL0, x12"
+
+  -
+    input:
+      bytes: [ 0x2c, 0x9d, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PMXEVTYPER_EL0, x12"
+
+  -
+    input:
+      bytes: [ 0x4c, 0x9d, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PMXEVCNTR_EL0, x12"
+
+  -
+    input:
+      bytes: [ 0x0c, 0x9e, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PMUSERENR_EL0, x12"
+
+  -
+    input:
+      bytes: [ 0x2c, 0x9e, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PMINTENSET_EL1, x12"
+
+  -
+    input:
+      bytes: [ 0x4c, 0x9e, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PMINTENCLR_EL1, x12"
+
+  -
+    input:
+      bytes: [ 0x6c, 0x9e, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PMOVSSET_EL0, x12"
+
+  -
+    input:
+      bytes: [ 0x0c, 0xa2, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr MAIR_EL1, x12"
+
+  -
+    input:
+      bytes: [ 0x0c, 0xa2, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr MAIR_EL2, x12"
+
+  -
+    input:
+      bytes: [ 0x0c, 0xa2, 0x1e, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr MAIR_EL3, x12"
+
+  -
+    input:
+      bytes: [ 0x0c, 0xa3, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMAIR_EL1, x12"
+
+  -
+    input:
+      bytes: [ 0x0c, 0xa3, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMAIR_EL2, x12"
+
+  -
+    input:
+      bytes: [ 0x0c, 0xa3, 0x1e, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMAIR_EL3, x12"
+
+  -
+    input:
+      bytes: [ 0x0c, 0xc0, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr VBAR_EL1, x12"
+
+  -
+    input:
+      bytes: [ 0x0c, 0xc0, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr VBAR_EL2, x12"
+
+  -
+    input:
+      bytes: [ 0x0c, 0xc0, 0x1e, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr VBAR_EL3, x12"
+
+  -
+    input:
+      bytes: [ 0x4c, 0xc0, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr RMR_EL1, x12"
+
+  -
+    input:
+      bytes: [ 0x4c, 0xc0, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr RMR_EL2, x12"
+
+  -
+    input:
+      bytes: [ 0x4c, 0xc0, 0x1e, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr RMR_EL3, x12"
+
+  -
+    input:
+      bytes: [ 0x2c, 0xd0, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr CONTEXTIDR_EL1, x12"
+
+  -
+    input:
+      bytes: [ 0x4c, 0xd0, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TPIDR_EL0, x12"
+
+  -
+    input:
+      bytes: [ 0x4c, 0xd0, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TPIDR_EL2, x12"
+
+  -
+    input:
+      bytes: [ 0x4c, 0xd0, 0x1e, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TPIDR_EL3, x12"
+
+  -
+    input:
+      bytes: [ 0x6c, 0xd0, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TPIDRRO_EL0, x12"
+
+  -
+    input:
+      bytes: [ 0x8c, 0xd0, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TPIDR_EL1, x12"
+
+  -
+    input:
+      bytes: [ 0x0c, 0xe0, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr CNTFRQ_EL0, x12"
+
+  -
+    input:
+      bytes: [ 0x6c, 0xe0, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr CNTVOFF_EL2, x12"
+
+  -
+    input:
+      bytes: [ 0x0c, 0xe1, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr CNTKCTL_EL1, x12"
+
+  -
+    input:
+      bytes: [ 0x0c, 0xe1, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr CNTHCTL_EL2, x12"
+
+  -
+    input:
+      bytes: [ 0x0c, 0xe2, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr CNTP_TVAL_EL0, x12"
+
+  -
+    input:
+      bytes: [ 0x0c, 0xe2, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr CNTHP_TVAL_EL2, x12"
+
+  -
+    input:
+      bytes: [ 0x0c, 0xe2, 0x1f, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr CNTPS_TVAL_EL1, x12"
+
+  -
+    input:
+      bytes: [ 0x2c, 0xe2, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr CNTP_CTL_EL0, x12"
+
+  -
+    input:
+      bytes: [ 0x2c, 0xe2, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr CNTHP_CTL_EL2, x12"
+
+  -
+    input:
+      bytes: [ 0x2c, 0xe2, 0x1f, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr CNTPS_CTL_EL1, x12"
+
+  -
+    input:
+      bytes: [ 0x4c, 0xe2, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr CNTP_CVAL_EL0, x12"
+
+  -
+    input:
+      bytes: [ 0x4c, 0xe2, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr CNTHP_CVAL_EL2, x12"
+
+  -
+    input:
+      bytes: [ 0x4c, 0xe2, 0x1f, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr CNTPS_CVAL_EL1, x12"
+
+  -
+    input:
+      bytes: [ 0x0c, 0xe3, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr CNTV_TVAL_EL0, x12"
+
+  -
+    input:
+      bytes: [ 0x2c, 0xe3, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr CNTV_CTL_EL0, x12"
+
+  -
+    input:
+      bytes: [ 0x4c, 0xe3, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr CNTV_CVAL_EL0, x12"
+
+  -
+    input:
+      bytes: [ 0x0c, 0xe8, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PMEVCNTR0_EL0, x12"
+
+  -
+    input:
+      bytes: [ 0x2c, 0xe8, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PMEVCNTR1_EL0, x12"
+
+  -
+    input:
+      bytes: [ 0x4c, 0xe8, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PMEVCNTR2_EL0, x12"
+
+  -
+    input:
+      bytes: [ 0x6c, 0xe8, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PMEVCNTR3_EL0, x12"
+
+  -
+    input:
+      bytes: [ 0x8c, 0xe8, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PMEVCNTR4_EL0, x12"
+
+  -
+    input:
+      bytes: [ 0xac, 0xe8, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PMEVCNTR5_EL0, x12"
+
+  -
+    input:
+      bytes: [ 0xcc, 0xe8, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PMEVCNTR6_EL0, x12"
+
+  -
+    input:
+      bytes: [ 0xec, 0xe8, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PMEVCNTR7_EL0, x12"
+
+  -
+    input:
+      bytes: [ 0x0c, 0xe9, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PMEVCNTR8_EL0, x12"
+
+  -
+    input:
+      bytes: [ 0x2c, 0xe9, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PMEVCNTR9_EL0, x12"
+
+  -
+    input:
+      bytes: [ 0x4c, 0xe9, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PMEVCNTR10_EL0, x12"
+
+  -
+    input:
+      bytes: [ 0x6c, 0xe9, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PMEVCNTR11_EL0, x12"
+
+  -
+    input:
+      bytes: [ 0x8c, 0xe9, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PMEVCNTR12_EL0, x12"
+
+  -
+    input:
+      bytes: [ 0xac, 0xe9, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PMEVCNTR13_EL0, x12"
+
+  -
+    input:
+      bytes: [ 0xcc, 0xe9, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PMEVCNTR14_EL0, x12"
+
+  -
+    input:
+      bytes: [ 0xec, 0xe9, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PMEVCNTR15_EL0, x12"
+
+  -
+    input:
+      bytes: [ 0x0c, 0xea, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PMEVCNTR16_EL0, x12"
+
+  -
+    input:
+      bytes: [ 0x2c, 0xea, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PMEVCNTR17_EL0, x12"
+
+  -
+    input:
+      bytes: [ 0x4c, 0xea, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PMEVCNTR18_EL0, x12"
+
+  -
+    input:
+      bytes: [ 0x6c, 0xea, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PMEVCNTR19_EL0, x12"
+
+  -
+    input:
+      bytes: [ 0x8c, 0xea, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PMEVCNTR20_EL0, x12"
+
+  -
+    input:
+      bytes: [ 0xac, 0xea, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PMEVCNTR21_EL0, x12"
+
+  -
+    input:
+      bytes: [ 0xcc, 0xea, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PMEVCNTR22_EL0, x12"
+
+  -
+    input:
+      bytes: [ 0xec, 0xea, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PMEVCNTR23_EL0, x12"
+
+  -
+    input:
+      bytes: [ 0x0c, 0xeb, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PMEVCNTR24_EL0, x12"
+
+  -
+    input:
+      bytes: [ 0x2c, 0xeb, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PMEVCNTR25_EL0, x12"
+
+  -
+    input:
+      bytes: [ 0x4c, 0xeb, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PMEVCNTR26_EL0, x12"
+
+  -
+    input:
+      bytes: [ 0x6c, 0xeb, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PMEVCNTR27_EL0, x12"
+
+  -
+    input:
+      bytes: [ 0x8c, 0xeb, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PMEVCNTR28_EL0, x12"
+
+  -
+    input:
+      bytes: [ 0xac, 0xeb, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PMEVCNTR29_EL0, x12"
+
+  -
+    input:
+      bytes: [ 0xcc, 0xeb, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PMEVCNTR30_EL0, x12"
+
+  -
+    input:
+      bytes: [ 0xec, 0xef, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PMCCFILTR_EL0, x12"
+
+  -
+    input:
+      bytes: [ 0x0c, 0xec, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PMEVTYPER0_EL0, x12"
+
+  -
+    input:
+      bytes: [ 0x2c, 0xec, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PMEVTYPER1_EL0, x12"
+
+  -
+    input:
+      bytes: [ 0x4c, 0xec, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PMEVTYPER2_EL0, x12"
+
+  -
+    input:
+      bytes: [ 0x6c, 0xec, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PMEVTYPER3_EL0, x12"
+
+  -
+    input:
+      bytes: [ 0x8c, 0xec, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PMEVTYPER4_EL0, x12"
+
+  -
+    input:
+      bytes: [ 0xac, 0xec, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PMEVTYPER5_EL0, x12"
+
+  -
+    input:
+      bytes: [ 0xcc, 0xec, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PMEVTYPER6_EL0, x12"
+
+  -
+    input:
+      bytes: [ 0xec, 0xec, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PMEVTYPER7_EL0, x12"
+
+  -
+    input:
+      bytes: [ 0x0c, 0xed, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PMEVTYPER8_EL0, x12"
+
+  -
+    input:
+      bytes: [ 0x2c, 0xed, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PMEVTYPER9_EL0, x12"
+
+  -
+    input:
+      bytes: [ 0x4c, 0xed, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PMEVTYPER10_EL0, x12"
+
+  -
+    input:
+      bytes: [ 0x6c, 0xed, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PMEVTYPER11_EL0, x12"
+
+  -
+    input:
+      bytes: [ 0x8c, 0xed, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PMEVTYPER12_EL0, x12"
+
+  -
+    input:
+      bytes: [ 0xac, 0xed, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PMEVTYPER13_EL0, x12"
+
+  -
+    input:
+      bytes: [ 0xcc, 0xed, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PMEVTYPER14_EL0, x12"
+
+  -
+    input:
+      bytes: [ 0xec, 0xed, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PMEVTYPER15_EL0, x12"
+
+  -
+    input:
+      bytes: [ 0x0c, 0xee, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PMEVTYPER16_EL0, x12"
+
+  -
+    input:
+      bytes: [ 0x2c, 0xee, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PMEVTYPER17_EL0, x12"
+
+  -
+    input:
+      bytes: [ 0x4c, 0xee, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PMEVTYPER18_EL0, x12"
+
+  -
+    input:
+      bytes: [ 0x6c, 0xee, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PMEVTYPER19_EL0, x12"
+
+  -
+    input:
+      bytes: [ 0x8c, 0xee, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PMEVTYPER20_EL0, x12"
+
+  -
+    input:
+      bytes: [ 0xac, 0xee, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PMEVTYPER21_EL0, x12"
+
+  -
+    input:
+      bytes: [ 0xcc, 0xee, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PMEVTYPER22_EL0, x12"
+
+  -
+    input:
+      bytes: [ 0xec, 0xee, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PMEVTYPER23_EL0, x12"
+
+  -
+    input:
+      bytes: [ 0x0c, 0xef, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PMEVTYPER24_EL0, x12"
+
+  -
+    input:
+      bytes: [ 0x2c, 0xef, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PMEVTYPER25_EL0, x12"
+
+  -
+    input:
+      bytes: [ 0x4c, 0xef, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PMEVTYPER26_EL0, x12"
+
+  -
+    input:
+      bytes: [ 0x6c, 0xef, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PMEVTYPER27_EL0, x12"
+
+  -
+    input:
+      bytes: [ 0x8c, 0xef, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PMEVTYPER28_EL0, x12"
+
+  -
+    input:
+      bytes: [ 0xac, 0xef, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PMEVTYPER29_EL0, x12"
+
+  -
+    input:
+      bytes: [ 0xcc, 0xef, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PMEVTYPER30_EL0, x12"
+
+  -
+    input:
+      bytes: [ 0x2c, 0xa3, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMAIR2_EL1, x12"
+
+  -
+    input:
+      bytes: [ 0x2c, 0xa3, 0x1d, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMAIR2_EL12, x12"
+
+  -
+    input:
+      bytes: [ 0x2c, 0xa3, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMAIR2_EL2, x12"
+
+  -
+    input:
+      bytes: [ 0x2c, 0xa3, 0x1e, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr AMAIR2_EL3, x12"
+
+  -
+    input:
+      bytes: [ 0x2c, 0xa2, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr MAIR2_EL1, x12"
+
+  -
+    input:
+      bytes: [ 0x2c, 0xa2, 0x1d, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr MAIR2_EL12, x12"
+
+  -
+    input:
+      bytes: [ 0x2c, 0xa1, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr MAIR2_EL2, x12"
+
+  -
+    input:
+      bytes: [ 0x2c, 0xa1, 0x1e, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr MAIR2_EL3, x12"
+
+  -
+    input:
+      bytes: [ 0x4c, 0xa2, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PIRE0_EL1, x12"
+
+  -
+    input:
+      bytes: [ 0x4c, 0xa2, 0x1d, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PIRE0_EL12, x12"
+
+  -
+    input:
+      bytes: [ 0x4c, 0xa2, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PIRE0_EL2, x12"
+
+  -
+    input:
+      bytes: [ 0x6c, 0xa2, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PIR_EL1, x12"
+
+  -
+    input:
+      bytes: [ 0x6c, 0xa2, 0x1d, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PIR_EL12, x12"
+
+  -
+    input:
+      bytes: [ 0x6c, 0xa2, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PIR_EL2, x12"
+
+  -
+    input:
+      bytes: [ 0x6c, 0xa2, 0x1e, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PIR_EL3, x12"
+
+  -
+    input:
+      bytes: [ 0xac, 0xa2, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr S2PIR_EL2, x12"
+
+  -
+    input:
+      bytes: [ 0x8c, 0xa2, 0x1b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr POR_EL0, x12"
+
+  -
+    input:
+      bytes: [ 0x8c, 0xa2, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr POR_EL1, x12"
+
+  -
+    input:
+      bytes: [ 0x8c, 0xa2, 0x1d, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr POR_EL12, x12"
+
+  -
+    input:
+      bytes: [ 0x8c, 0xa2, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr POR_EL2, x12"
+
+  -
+    input:
+      bytes: [ 0x8c, 0xa2, 0x1e, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr POR_EL3, x12"
+
+  -
+    input:
+      bytes: [ 0xac, 0xa2, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr S2POR_EL1, x12"
+
+  -
+    input:
+      bytes: [ 0x6c, 0x10, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SCTLR2_EL1, x12"
+
+  -
+    input:
+      bytes: [ 0x6c, 0x10, 0x1d, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SCTLR2_EL12, x12"
+
+  -
+    input:
+      bytes: [ 0x6c, 0x10, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SCTLR2_EL2, x12"
+
+  -
+    input:
+      bytes: [ 0x6c, 0x10, 0x1e, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr SCTLR2_EL3, x12"
+
+  -
+    input:
+      bytes: [ 0x6c, 0x20, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TCR2_EL1, x12"
+
+  -
+    input:
+      bytes: [ 0x6c, 0x20, 0x1d, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TCR2_EL12, x12"
+
+  -
+    input:
+      bytes: [ 0x6c, 0x20, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TCR2_EL2, x12"
+
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x32, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, TEECR32_EL1"
+
+  -
+    input:
+      bytes: [ 0x49, 0x00, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, OSDTRRX_EL1"
+
+  -
+    input:
+      bytes: [ 0x09, 0x01, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, MDCCSR_EL0"
+
+  -
+    input:
+      bytes: [ 0x09, 0x02, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, MDCCINT_EL1"
+
+  -
+    input:
+      bytes: [ 0x49, 0x02, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, MDSCR_EL1"
+
+  -
+    input:
+      bytes: [ 0x49, 0x03, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, OSDTRTX_EL1"
+
+  -
+    input:
+      bytes: [ 0x09, 0x04, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, DBGDTR_EL0"
+
+  -
+    input:
+      bytes: [ 0x09, 0x05, 0x33, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, DBGDTRRX_EL0"
+
+  -
+    input:
+      bytes: [ 0x49, 0x06, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, OSECCR_EL1"
+
+  -
+    input:
+      bytes: [ 0x09, 0x07, 0x34, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, DBGVCR32_EL2"
+
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, DBGBVR0_EL1"
+
+  -
+    input:
+      bytes: [ 0x89, 0x01, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, DBGBVR1_EL1"
+
+  -
+    input:
+      bytes: [ 0x89, 0x02, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, DBGBVR2_EL1"
+
+  -
+    input:
+      bytes: [ 0x89, 0x03, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, DBGBVR3_EL1"
+
+  -
+    input:
+      bytes: [ 0x89, 0x04, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, DBGBVR4_EL1"
+
+  -
+    input:
+      bytes: [ 0x89, 0x05, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, DBGBVR5_EL1"
+
+  -
+    input:
+      bytes: [ 0x89, 0x06, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, DBGBVR6_EL1"
+
+  -
+    input:
+      bytes: [ 0x89, 0x07, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, DBGBVR7_EL1"
+
+  -
+    input:
+      bytes: [ 0x89, 0x08, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, DBGBVR8_EL1"
+
+  -
+    input:
+      bytes: [ 0x89, 0x09, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, DBGBVR9_EL1"
+
+  -
+    input:
+      bytes: [ 0x89, 0x0a, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, DBGBVR10_EL1"
+
+  -
+    input:
+      bytes: [ 0x89, 0x0b, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, DBGBVR11_EL1"
+
+  -
+    input:
+      bytes: [ 0x89, 0x0c, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, DBGBVR12_EL1"
+
+  -
+    input:
+      bytes: [ 0x89, 0x0d, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, DBGBVR13_EL1"
+
+  -
+    input:
+      bytes: [ 0x89, 0x0e, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, DBGBVR14_EL1"
+
+  -
+    input:
+      bytes: [ 0x89, 0x0f, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, DBGBVR15_EL1"
+
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, DBGBCR0_EL1"
+
+  -
+    input:
+      bytes: [ 0xa9, 0x01, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, DBGBCR1_EL1"
+
+  -
+    input:
+      bytes: [ 0xa9, 0x02, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, DBGBCR2_EL1"
+
+  -
+    input:
+      bytes: [ 0xa9, 0x03, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, DBGBCR3_EL1"
+
+  -
+    input:
+      bytes: [ 0xa9, 0x04, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, DBGBCR4_EL1"
+
+  -
+    input:
+      bytes: [ 0xa9, 0x05, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, DBGBCR5_EL1"
+
+  -
+    input:
+      bytes: [ 0xa9, 0x06, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, DBGBCR6_EL1"
+
+  -
+    input:
+      bytes: [ 0xa9, 0x07, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, DBGBCR7_EL1"
+
+  -
+    input:
+      bytes: [ 0xa9, 0x08, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, DBGBCR8_EL1"
+
+  -
+    input:
+      bytes: [ 0xa9, 0x09, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, DBGBCR9_EL1"
+
+  -
+    input:
+      bytes: [ 0xa9, 0x0a, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, DBGBCR10_EL1"
+
+  -
+    input:
+      bytes: [ 0xa9, 0x0b, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, DBGBCR11_EL1"
+
+  -
+    input:
+      bytes: [ 0xa9, 0x0c, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, DBGBCR12_EL1"
+
+  -
+    input:
+      bytes: [ 0xa9, 0x0d, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, DBGBCR13_EL1"
+
+  -
+    input:
+      bytes: [ 0xa9, 0x0e, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, DBGBCR14_EL1"
+
+  -
+    input:
+      bytes: [ 0xa9, 0x0f, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, DBGBCR15_EL1"
+
+  -
+    input:
+      bytes: [ 0xc9, 0x00, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, DBGWVR0_EL1"
+
+  -
+    input:
+      bytes: [ 0xc9, 0x01, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, DBGWVR1_EL1"
+
+  -
+    input:
+      bytes: [ 0xc9, 0x02, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, DBGWVR2_EL1"
+
+  -
+    input:
+      bytes: [ 0xc9, 0x03, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, DBGWVR3_EL1"
+
+  -
+    input:
+      bytes: [ 0xc9, 0x04, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, DBGWVR4_EL1"
+
+  -
+    input:
+      bytes: [ 0xc9, 0x05, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, DBGWVR5_EL1"
+
+  -
+    input:
+      bytes: [ 0xc9, 0x06, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, DBGWVR6_EL1"
+
+  -
+    input:
+      bytes: [ 0xc9, 0x07, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, DBGWVR7_EL1"
+
+  -
+    input:
+      bytes: [ 0xc9, 0x08, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, DBGWVR8_EL1"
+
+  -
+    input:
+      bytes: [ 0xc9, 0x09, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, DBGWVR9_EL1"
+
+  -
+    input:
+      bytes: [ 0xc9, 0x0a, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, DBGWVR10_EL1"
+
+  -
+    input:
+      bytes: [ 0xc9, 0x0b, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, DBGWVR11_EL1"
+
+  -
+    input:
+      bytes: [ 0xc9, 0x0c, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, DBGWVR12_EL1"
+
+  -
+    input:
+      bytes: [ 0xc9, 0x0d, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, DBGWVR13_EL1"
+
+  -
+    input:
+      bytes: [ 0xc9, 0x0e, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, DBGWVR14_EL1"
+
+  -
+    input:
+      bytes: [ 0xc9, 0x0f, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, DBGWVR15_EL1"
+
+  -
+    input:
+      bytes: [ 0xe9, 0x00, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, DBGWCR0_EL1"
+
+  -
+    input:
+      bytes: [ 0xe9, 0x01, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, DBGWCR1_EL1"
+
+  -
+    input:
+      bytes: [ 0xe9, 0x02, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, DBGWCR2_EL1"
+
+  -
+    input:
+      bytes: [ 0xe9, 0x03, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, DBGWCR3_EL1"
+
+  -
+    input:
+      bytes: [ 0xe9, 0x04, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, DBGWCR4_EL1"
+
+  -
+    input:
+      bytes: [ 0xe9, 0x05, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, DBGWCR5_EL1"
+
+  -
+    input:
+      bytes: [ 0xe9, 0x06, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, DBGWCR6_EL1"
+
+  -
+    input:
+      bytes: [ 0xe9, 0x07, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, DBGWCR7_EL1"
+
+  -
+    input:
+      bytes: [ 0xe9, 0x08, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, DBGWCR8_EL1"
+
+  -
+    input:
+      bytes: [ 0xe9, 0x09, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, DBGWCR9_EL1"
+
+  -
+    input:
+      bytes: [ 0xe9, 0x0a, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, DBGWCR10_EL1"
+
+  -
+    input:
+      bytes: [ 0xe9, 0x0b, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, DBGWCR11_EL1"
+
+  -
+    input:
+      bytes: [ 0xe9, 0x0c, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, DBGWCR12_EL1"
+
+  -
+    input:
+      bytes: [ 0xe9, 0x0d, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, DBGWCR13_EL1"
+
+  -
+    input:
+      bytes: [ 0xe9, 0x0e, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, DBGWCR14_EL1"
+
+  -
+    input:
+      bytes: [ 0xe9, 0x0f, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, DBGWCR15_EL1"
+
+  -
+    input:
+      bytes: [ 0x09, 0x10, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, MDRAR_EL1"
+
+  -
+    input:
+      bytes: [ 0x09, 0x10, 0x32, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, TEEHBR32_EL1"
+
+  -
+    input:
+      bytes: [ 0x89, 0x11, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, OSLSR_EL1"
+
+  -
+    input:
+      bytes: [ 0x89, 0x13, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, OSDLR_EL1"
+
+  -
+    input:
+      bytes: [ 0x89, 0x14, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, DBGPRCR_EL1"
+
+  -
+    input:
+      bytes: [ 0xc9, 0x78, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, DBGCLAIMSET_EL1"
+
+  -
+    input:
+      bytes: [ 0xc9, 0x79, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, DBGCLAIMCLR_EL1"
+
+  -
+    input:
+      bytes: [ 0xc9, 0x7e, 0x30, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, DBGAUTHSTATUS_EL1"
+
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, MIDR_EL1"
+
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x39, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, CCSIDR_EL1"
+
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x3a, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, CSSELR_EL1"
+
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, VPIDR_EL2"
+
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0x39, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, CLIDR_EL1"
+
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, CTR_EL0"
+
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, MPIDR_EL1"
+
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, VMPIDR_EL2"
+
+  -
+    input:
+      bytes: [ 0xc9, 0x00, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, REVIDR_EL1"
+
+  -
+    input:
+      bytes: [ 0xe9, 0x00, 0x39, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, AIDR_EL1"
+
+  -
+    input:
+      bytes: [ 0xe9, 0x00, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, DCZID_EL0"
+
+  -
+    input:
+      bytes: [ 0x09, 0x01, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, ID_PFR0_EL1"
+
+  -
+    input:
+      bytes: [ 0x29, 0x01, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, ID_PFR1_EL1"
+
+  -
+    input:
+      bytes: [ 0x49, 0x01, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, ID_DFR0_EL1"
+
+  -
+    input:
+      bytes: [ 0xa9, 0x03, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, ID_DFR1_EL1"
+
+  -
+    input:
+      bytes: [ 0x69, 0x01, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, ID_AFR0_EL1"
+
+  -
+    input:
+      bytes: [ 0x89, 0x01, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, ID_MMFR0_EL1"
+
+  -
+    input:
+      bytes: [ 0xa9, 0x01, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, ID_MMFR1_EL1"
+
+  -
+    input:
+      bytes: [ 0xc9, 0x01, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, ID_MMFR2_EL1"
+
+  -
+    input:
+      bytes: [ 0xe9, 0x01, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, ID_MMFR3_EL1"
+
+  -
+    input:
+      bytes: [ 0xc9, 0x02, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, ID_MMFR4_EL1"
+
+  -
+    input:
+      bytes: [ 0xc9, 0x03, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, ID_MMFR5_EL1"
+
+  -
+    input:
+      bytes: [ 0x09, 0x02, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, ID_ISAR0_EL1"
+
+  -
+    input:
+      bytes: [ 0x29, 0x02, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, ID_ISAR1_EL1"
+
+  -
+    input:
+      bytes: [ 0x49, 0x02, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, ID_ISAR2_EL1"
+
+  -
+    input:
+      bytes: [ 0x69, 0x02, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, ID_ISAR3_EL1"
+
+  -
+    input:
+      bytes: [ 0x89, 0x02, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, ID_ISAR4_EL1"
+
+  -
+    input:
+      bytes: [ 0xa9, 0x02, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, ID_ISAR5_EL1"
+
+  -
+    input:
+      bytes: [ 0x09, 0x03, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, MVFR0_EL1"
+
+  -
+    input:
+      bytes: [ 0x29, 0x03, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, MVFR1_EL1"
+
+  -
+    input:
+      bytes: [ 0x49, 0x03, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, MVFR2_EL1"
+
+  -
+    input:
+      bytes: [ 0x09, 0x04, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, ID_AA64PFR0_EL1"
+
+  -
+    input:
+      bytes: [ 0x29, 0x04, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, ID_AA64PFR1_EL1"
+
+  -
+    input:
+      bytes: [ 0x49, 0x04, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, ID_AA64PFR2_EL1"
+
+  -
+    input:
+      bytes: [ 0x09, 0x05, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, ID_AA64DFR0_EL1"
+
+  -
+    input:
+      bytes: [ 0x29, 0x05, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, ID_AA64DFR1_EL1"
+
+  -
+    input:
+      bytes: [ 0x49, 0x05, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, ID_AA64DFR2_EL1"
+
+  -
+    input:
+      bytes: [ 0x89, 0x05, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, ID_AA64AFR0_EL1"
+
+  -
+    input:
+      bytes: [ 0xa9, 0x05, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, ID_AA64AFR1_EL1"
+
+  -
+    input:
+      bytes: [ 0x09, 0x06, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, ID_AA64ISAR0_EL1"
+
+  -
+    input:
+      bytes: [ 0x29, 0x06, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, ID_AA64ISAR1_EL1"
+
+  -
+    input:
+      bytes: [ 0x49, 0x06, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, ID_AA64ISAR2_EL1"
+
+  -
+    input:
+      bytes: [ 0x69, 0x06, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, ID_AA64ISAR3_EL1"
+
+  -
+    input:
+      bytes: [ 0x09, 0x07, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, ID_AA64MMFR0_EL1"
+
+  -
+    input:
+      bytes: [ 0x29, 0x07, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, ID_AA64MMFR1_EL1"
+
+  -
+    input:
+      bytes: [ 0x49, 0x07, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, ID_AA64MMFR2_EL1"
+
+  -
+    input:
+      bytes: [ 0x69, 0x07, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, ID_AA64MMFR3_EL1"
+
+  -
+    input:
+      bytes: [ 0x89, 0x07, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, ID_AA64MMFR4_EL1"
+
+  -
+    input:
+      bytes: [ 0x09, 0x10, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, SCTLR_EL1"
+
+  -
+    input:
+      bytes: [ 0x09, 0x10, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, SCTLR_EL2"
+
+  -
+    input:
+      bytes: [ 0x09, 0x10, 0x3e, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, SCTLR_EL3"
+
+  -
+    input:
+      bytes: [ 0x29, 0x10, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, ACTLR_EL1"
+
+  -
+    input:
+      bytes: [ 0x29, 0x10, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, ACTLR_EL2"
+
+  -
+    input:
+      bytes: [ 0x29, 0x10, 0x3e, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, ACTLR_EL3"
+
+  -
+    input:
+      bytes: [ 0x49, 0x10, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, CPACR_EL1"
+
+  -
+    input:
+      bytes: [ 0x09, 0x11, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, HCR_EL2"
+
+  -
+    input:
+      bytes: [ 0x09, 0x11, 0x3e, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, SCR_EL3"
+
+  -
+    input:
+      bytes: [ 0x29, 0x11, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, MDCR_EL2"
+
+  -
+    input:
+      bytes: [ 0x29, 0x11, 0x3e, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, SDER32_EL3"
+
+  -
+    input:
+      bytes: [ 0x49, 0x11, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, CPTR_EL2"
+
+  -
+    input:
+      bytes: [ 0x49, 0x11, 0x3e, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, CPTR_EL3"
+
+  -
+    input:
+      bytes: [ 0x69, 0x11, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, HSTR_EL2"
+
+  -
+    input:
+      bytes: [ 0xe9, 0x11, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, HACR_EL2"
+
+  -
+    input:
+      bytes: [ 0x29, 0x13, 0x3e, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, MDCR_EL3"
+
+  -
+    input:
+      bytes: [ 0x09, 0x20, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, TTBR0_EL1"
+
+  -
+    input:
+      bytes: [ 0x09, 0x20, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, TTBR0_EL2"
+
+  -
+    input:
+      bytes: [ 0x09, 0x20, 0x3e, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, TTBR0_EL3"
+
+  -
+    input:
+      bytes: [ 0x29, 0x20, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, TTBR1_EL1"
+
+  -
+    input:
+      bytes: [ 0x49, 0x20, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, TCR_EL1"
+
+  -
+    input:
+      bytes: [ 0x49, 0x20, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, TCR_EL2"
+
+  -
+    input:
+      bytes: [ 0x49, 0x20, 0x3e, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, TCR_EL3"
+
+  -
+    input:
+      bytes: [ 0x09, 0x21, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, VTTBR_EL2"
+
+  -
+    input:
+      bytes: [ 0x49, 0x21, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, VTCR_EL2"
+
+  -
+    input:
+      bytes: [ 0x09, 0x30, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, DACR32_EL2"
+
+  -
+    input:
+      bytes: [ 0x09, 0x40, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, SPSR_EL1"
+
+  -
+    input:
+      bytes: [ 0x09, 0x40, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, SPSR_EL2"
+
+  -
+    input:
+      bytes: [ 0x09, 0x40, 0x3e, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, SPSR_EL3"
+
+  -
+    input:
+      bytes: [ 0x29, 0x40, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, ELR_EL1"
+
+  -
+    input:
+      bytes: [ 0x29, 0x40, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, ELR_EL2"
+
+  -
+    input:
+      bytes: [ 0x29, 0x40, 0x3e, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, ELR_EL3"
+
+  -
+    input:
+      bytes: [ 0x09, 0x41, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, SP_EL0"
+
+  -
+    input:
+      bytes: [ 0x09, 0x41, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, SP_EL1"
+
+  -
+    input:
+      bytes: [ 0x09, 0x41, 0x3e, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, SP_EL2"
+
+  -
+    input:
+      bytes: [ 0x09, 0x42, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, SPSel"
+
+  -
+    input:
+      bytes: [ 0x09, 0x42, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, NZCV"
+
+  -
+    input:
+      bytes: [ 0x29, 0x42, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, DAIF"
+
+  -
+    input:
+      bytes: [ 0x49, 0x42, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, CurrentEL"
+
+  -
+    input:
+      bytes: [ 0x09, 0x43, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, SPSR_irq"
+
+  -
+    input:
+      bytes: [ 0x29, 0x43, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, SPSR_abt"
+
+  -
+    input:
+      bytes: [ 0x49, 0x43, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, SPSR_und"
+
+  -
+    input:
+      bytes: [ 0x69, 0x43, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, SPSR_fiq"
+
+  -
+    input:
+      bytes: [ 0x09, 0x44, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, FPCR"
+
+  -
+    input:
+      bytes: [ 0x29, 0x44, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, FPSR"
+
+  -
+    input:
+      bytes: [ 0x09, 0x45, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, DSPSR_EL0"
+
+  -
+    input:
+      bytes: [ 0x29, 0x45, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, DLR_EL0"
+
+  -
+    input:
+      bytes: [ 0x29, 0x50, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, IFSR32_EL2"
+
+  -
+    input:
+      bytes: [ 0x09, 0x51, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, AFSR0_EL1"
+
+  -
+    input:
+      bytes: [ 0x09, 0x51, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, AFSR0_EL2"
+
+  -
+    input:
+      bytes: [ 0x09, 0x51, 0x3e, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, AFSR0_EL3"
+
+  -
+    input:
+      bytes: [ 0x29, 0x51, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, AFSR1_EL1"
+
+  -
+    input:
+      bytes: [ 0x29, 0x51, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, AFSR1_EL2"
+
+  -
+    input:
+      bytes: [ 0x29, 0x51, 0x3e, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, AFSR1_EL3"
+
+  -
+    input:
+      bytes: [ 0x09, 0x52, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, ESR_EL1"
+
+  -
+    input:
+      bytes: [ 0x09, 0x52, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, ESR_EL2"
+
+  -
+    input:
+      bytes: [ 0x09, 0x52, 0x3e, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, ESR_EL3"
+
+  -
+    input:
+      bytes: [ 0x09, 0x53, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, FPEXC32_EL2"
+
+  -
+    input:
+      bytes: [ 0x09, 0x60, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, FAR_EL1"
+
+  -
+    input:
+      bytes: [ 0x09, 0x60, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, FAR_EL2"
+
+  -
+    input:
+      bytes: [ 0x09, 0x60, 0x3e, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, FAR_EL3"
+
+  -
+    input:
+      bytes: [ 0x89, 0x60, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, HPFAR_EL2"
+
+  -
+    input:
+      bytes: [ 0x09, 0x74, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, PAR_EL1"
+
+  -
+    input:
+      bytes: [ 0x09, 0x9c, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, PMCR_EL0"
+
+  -
+    input:
+      bytes: [ 0x29, 0x9c, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, PMCNTENSET_EL0"
+
+  -
+    input:
+      bytes: [ 0x49, 0x9c, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, PMCNTENCLR_EL0"
+
+  -
+    input:
+      bytes: [ 0x69, 0x9c, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, PMOVSCLR_EL0"
+
+  -
+    input:
+      bytes: [ 0xa9, 0x9c, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, PMSELR_EL0"
+
+  -
+    input:
+      bytes: [ 0xc9, 0x9c, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, PMCEID0_EL0"
+
+  -
+    input:
+      bytes: [ 0xe9, 0x9c, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, PMCEID1_EL0"
+
+  -
+    input:
+      bytes: [ 0x09, 0x9d, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, PMCCNTR_EL0"
+
+  -
+    input:
+      bytes: [ 0x29, 0x9d, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, PMXEVTYPER_EL0"
+
+  -
+    input:
+      bytes: [ 0x49, 0x9d, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, PMXEVCNTR_EL0"
+
+  -
+    input:
+      bytes: [ 0x09, 0x9e, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, PMUSERENR_EL0"
+
+  -
+    input:
+      bytes: [ 0x29, 0x9e, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, PMINTENSET_EL1"
+
+  -
+    input:
+      bytes: [ 0x49, 0x9e, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, PMINTENCLR_EL1"
+
+  -
+    input:
+      bytes: [ 0x69, 0x9e, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, PMOVSSET_EL0"
+
+  -
+    input:
+      bytes: [ 0xc9, 0x9e, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, PMMIR_EL1"
+
+  -
+    input:
+      bytes: [ 0x09, 0xa2, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, MAIR_EL1"
+
+  -
+    input:
+      bytes: [ 0x09, 0xa2, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, MAIR_EL2"
+
+  -
+    input:
+      bytes: [ 0x09, 0xa2, 0x3e, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, MAIR_EL3"
+
+  -
+    input:
+      bytes: [ 0x09, 0xa3, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, AMAIR_EL1"
+
+  -
+    input:
+      bytes: [ 0x09, 0xa3, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, AMAIR_EL2"
+
+  -
+    input:
+      bytes: [ 0x09, 0xa3, 0x3e, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, AMAIR_EL3"
+
+  -
+    input:
+      bytes: [ 0x09, 0xc0, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, VBAR_EL1"
+
+  -
+    input:
+      bytes: [ 0x09, 0xc0, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, VBAR_EL2"
+
+  -
+    input:
+      bytes: [ 0x09, 0xc0, 0x3e, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, VBAR_EL3"
+
+  -
+    input:
+      bytes: [ 0x29, 0xc0, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, RVBAR_EL1"
+
+  -
+    input:
+      bytes: [ 0x29, 0xc0, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, RVBAR_EL2"
+
+  -
+    input:
+      bytes: [ 0x29, 0xc0, 0x3e, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, RVBAR_EL3"
+
+  -
+    input:
+      bytes: [ 0x49, 0xc0, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, RMR_EL1"
+
+  -
+    input:
+      bytes: [ 0x49, 0xc0, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, RMR_EL2"
+
+  -
+    input:
+      bytes: [ 0x49, 0xc0, 0x3e, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, RMR_EL3"
+
+  -
+    input:
+      bytes: [ 0x09, 0xc1, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, ISR_EL1"
+
+  -
+    input:
+      bytes: [ 0x29, 0xd0, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, CONTEXTIDR_EL1"
+
+  -
+    input:
+      bytes: [ 0x49, 0xd0, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, TPIDR_EL0"
+
+  -
+    input:
+      bytes: [ 0x49, 0xd0, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, TPIDR_EL2"
+
+  -
+    input:
+      bytes: [ 0x49, 0xd0, 0x3e, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, TPIDR_EL3"
+
+  -
+    input:
+      bytes: [ 0x69, 0xd0, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, TPIDRRO_EL0"
+
+  -
+    input:
+      bytes: [ 0x89, 0xd0, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, TPIDR_EL1"
+
+  -
+    input:
+      bytes: [ 0x09, 0xe0, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, CNTFRQ_EL0"
+
+  -
+    input:
+      bytes: [ 0x29, 0xe0, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, CNTPCT_EL0"
+
+  -
+    input:
+      bytes: [ 0x49, 0xe0, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, CNTVCT_EL0"
+
+  -
+    input:
+      bytes: [ 0x69, 0xe0, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, CNTVOFF_EL2"
+
+  -
+    input:
+      bytes: [ 0x09, 0xe1, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, CNTKCTL_EL1"
+
+  -
+    input:
+      bytes: [ 0x09, 0xe1, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, CNTHCTL_EL2"
+
+  -
+    input:
+      bytes: [ 0x09, 0xe2, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, CNTP_TVAL_EL0"
+
+  -
+    input:
+      bytes: [ 0x09, 0xe2, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, CNTHP_TVAL_EL2"
+
+  -
+    input:
+      bytes: [ 0x09, 0xe2, 0x3f, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, CNTPS_TVAL_EL1"
+
+  -
+    input:
+      bytes: [ 0x29, 0xe2, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, CNTP_CTL_EL0"
+
+  -
+    input:
+      bytes: [ 0x29, 0xe2, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, CNTHP_CTL_EL2"
+
+  -
+    input:
+      bytes: [ 0x29, 0xe2, 0x3f, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, CNTPS_CTL_EL1"
+
+  -
+    input:
+      bytes: [ 0x49, 0xe2, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, CNTP_CVAL_EL0"
+
+  -
+    input:
+      bytes: [ 0x49, 0xe2, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, CNTHP_CVAL_EL2"
+
+  -
+    input:
+      bytes: [ 0x49, 0xe2, 0x3f, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, CNTPS_CVAL_EL1"
+
+  -
+    input:
+      bytes: [ 0x09, 0xe3, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, CNTV_TVAL_EL0"
+
+  -
+    input:
+      bytes: [ 0x29, 0xe3, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, CNTV_CTL_EL0"
+
+  -
+    input:
+      bytes: [ 0x49, 0xe3, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, CNTV_CVAL_EL0"
+
+  -
+    input:
+      bytes: [ 0x09, 0xe8, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, PMEVCNTR0_EL0"
+
+  -
+    input:
+      bytes: [ 0x29, 0xe8, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, PMEVCNTR1_EL0"
+
+  -
+    input:
+      bytes: [ 0x49, 0xe8, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, PMEVCNTR2_EL0"
+
+  -
+    input:
+      bytes: [ 0x69, 0xe8, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, PMEVCNTR3_EL0"
+
+  -
+    input:
+      bytes: [ 0x89, 0xe8, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, PMEVCNTR4_EL0"
+
+  -
+    input:
+      bytes: [ 0xa9, 0xe8, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, PMEVCNTR5_EL0"
+
+  -
+    input:
+      bytes: [ 0xc9, 0xe8, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, PMEVCNTR6_EL0"
+
+  -
+    input:
+      bytes: [ 0xe9, 0xe8, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, PMEVCNTR7_EL0"
+
+  -
+    input:
+      bytes: [ 0x09, 0xe9, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, PMEVCNTR8_EL0"
+
+  -
+    input:
+      bytes: [ 0x29, 0xe9, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, PMEVCNTR9_EL0"
+
+  -
+    input:
+      bytes: [ 0x49, 0xe9, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, PMEVCNTR10_EL0"
+
+  -
+    input:
+      bytes: [ 0x69, 0xe9, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, PMEVCNTR11_EL0"
+
+  -
+    input:
+      bytes: [ 0x89, 0xe9, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, PMEVCNTR12_EL0"
+
+  -
+    input:
+      bytes: [ 0xa9, 0xe9, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, PMEVCNTR13_EL0"
+
+  -
+    input:
+      bytes: [ 0xc9, 0xe9, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, PMEVCNTR14_EL0"
+
+  -
+    input:
+      bytes: [ 0xe9, 0xe9, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, PMEVCNTR15_EL0"
+
+  -
+    input:
+      bytes: [ 0x09, 0xea, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, PMEVCNTR16_EL0"
+
+  -
+    input:
+      bytes: [ 0x29, 0xea, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, PMEVCNTR17_EL0"
+
+  -
+    input:
+      bytes: [ 0x49, 0xea, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, PMEVCNTR18_EL0"
+
+  -
+    input:
+      bytes: [ 0x69, 0xea, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, PMEVCNTR19_EL0"
+
+  -
+    input:
+      bytes: [ 0x89, 0xea, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, PMEVCNTR20_EL0"
+
+  -
+    input:
+      bytes: [ 0xa9, 0xea, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, PMEVCNTR21_EL0"
+
+  -
+    input:
+      bytes: [ 0xc9, 0xea, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, PMEVCNTR22_EL0"
+
+  -
+    input:
+      bytes: [ 0xe9, 0xea, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, PMEVCNTR23_EL0"
+
+  -
+    input:
+      bytes: [ 0x09, 0xeb, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, PMEVCNTR24_EL0"
+
+  -
+    input:
+      bytes: [ 0x29, 0xeb, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, PMEVCNTR25_EL0"
+
+  -
+    input:
+      bytes: [ 0x49, 0xeb, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, PMEVCNTR26_EL0"
+
+  -
+    input:
+      bytes: [ 0x69, 0xeb, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, PMEVCNTR27_EL0"
+
+  -
+    input:
+      bytes: [ 0x89, 0xeb, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, PMEVCNTR28_EL0"
+
+  -
+    input:
+      bytes: [ 0xa9, 0xeb, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, PMEVCNTR29_EL0"
+
+  -
+    input:
+      bytes: [ 0xc9, 0xeb, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, PMEVCNTR30_EL0"
+
+  -
+    input:
+      bytes: [ 0xe9, 0xef, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, PMCCFILTR_EL0"
+
+  -
+    input:
+      bytes: [ 0x09, 0xec, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, PMEVTYPER0_EL0"
+
+  -
+    input:
+      bytes: [ 0x29, 0xec, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, PMEVTYPER1_EL0"
+
+  -
+    input:
+      bytes: [ 0x49, 0xec, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, PMEVTYPER2_EL0"
+
+  -
+    input:
+      bytes: [ 0x69, 0xec, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, PMEVTYPER3_EL0"
+
+  -
+    input:
+      bytes: [ 0x89, 0xec, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, PMEVTYPER4_EL0"
+
+  -
+    input:
+      bytes: [ 0xa9, 0xec, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, PMEVTYPER5_EL0"
+
+  -
+    input:
+      bytes: [ 0xc9, 0xec, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, PMEVTYPER6_EL0"
+
+  -
+    input:
+      bytes: [ 0xe9, 0xec, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, PMEVTYPER7_EL0"
+
+  -
+    input:
+      bytes: [ 0x09, 0xed, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, PMEVTYPER8_EL0"
+
+  -
+    input:
+      bytes: [ 0x29, 0xed, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, PMEVTYPER9_EL0"
+
+  -
+    input:
+      bytes: [ 0x49, 0xed, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, PMEVTYPER10_EL0"
+
+  -
+    input:
+      bytes: [ 0x69, 0xed, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, PMEVTYPER11_EL0"
+
+  -
+    input:
+      bytes: [ 0x89, 0xed, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, PMEVTYPER12_EL0"
+
+  -
+    input:
+      bytes: [ 0xa9, 0xed, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, PMEVTYPER13_EL0"
+
+  -
+    input:
+      bytes: [ 0xc9, 0xed, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, PMEVTYPER14_EL0"
+
+  -
+    input:
+      bytes: [ 0xe9, 0xed, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, PMEVTYPER15_EL0"
+
+  -
+    input:
+      bytes: [ 0x09, 0xee, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, PMEVTYPER16_EL0"
+
+  -
+    input:
+      bytes: [ 0x29, 0xee, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, PMEVTYPER17_EL0"
+
+  -
+    input:
+      bytes: [ 0x49, 0xee, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, PMEVTYPER18_EL0"
+
+  -
+    input:
+      bytes: [ 0x69, 0xee, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, PMEVTYPER19_EL0"
+
+  -
+    input:
+      bytes: [ 0x89, 0xee, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, PMEVTYPER20_EL0"
+
+  -
+    input:
+      bytes: [ 0xa9, 0xee, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, PMEVTYPER21_EL0"
+
+  -
+    input:
+      bytes: [ 0xc9, 0xee, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, PMEVTYPER22_EL0"
+
+  -
+    input:
+      bytes: [ 0xe9, 0xee, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, PMEVTYPER23_EL0"
+
+  -
+    input:
+      bytes: [ 0x09, 0xef, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, PMEVTYPER24_EL0"
+
+  -
+    input:
+      bytes: [ 0x29, 0xef, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, PMEVTYPER25_EL0"
+
+  -
+    input:
+      bytes: [ 0x49, 0xef, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, PMEVTYPER26_EL0"
+
+  -
+    input:
+      bytes: [ 0x69, 0xef, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, PMEVTYPER27_EL0"
+
+  -
+    input:
+      bytes: [ 0x89, 0xef, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, PMEVTYPER28_EL0"
+
+  -
+    input:
+      bytes: [ 0xa9, 0xef, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, PMEVTYPER29_EL0"
+
+  -
+    input:
+      bytes: [ 0xc9, 0xef, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, PMEVTYPER30_EL0"
+
+  -
+    input:
+      bytes: [ 0x29, 0xa3, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, AMAIR2_EL1"
+
+  -
+    input:
+      bytes: [ 0x29, 0xa3, 0x3d, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, AMAIR2_EL12"
+
+  -
+    input:
+      bytes: [ 0x29, 0xa3, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, AMAIR2_EL2"
+
+  -
+    input:
+      bytes: [ 0x29, 0xa3, 0x3e, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, AMAIR2_EL3"
+
+  -
+    input:
+      bytes: [ 0x29, 0xa2, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, MAIR2_EL1"
+
+  -
+    input:
+      bytes: [ 0x29, 0xa2, 0x3d, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, MAIR2_EL12"
+
+  -
+    input:
+      bytes: [ 0x29, 0xa1, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, MAIR2_EL2"
+
+  -
+    input:
+      bytes: [ 0x29, 0xa1, 0x3e, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, MAIR2_EL3"
+
+  -
+    input:
+      bytes: [ 0x49, 0xa2, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, PIRE0_EL1"
+
+  -
+    input:
+      bytes: [ 0x49, 0xa2, 0x3d, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, PIRE0_EL12"
+
+  -
+    input:
+      bytes: [ 0x49, 0xa2, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, PIRE0_EL2"
+
+  -
+    input:
+      bytes: [ 0x69, 0xa2, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, PIR_EL1"
+
+  -
+    input:
+      bytes: [ 0x69, 0xa2, 0x3d, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, PIR_EL12"
+
+  -
+    input:
+      bytes: [ 0x69, 0xa2, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, PIR_EL2"
+
+  -
+    input:
+      bytes: [ 0x69, 0xa2, 0x3e, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, PIR_EL3"
+
+  -
+    input:
+      bytes: [ 0xa9, 0xa2, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, S2PIR_EL2"
+
+  -
+    input:
+      bytes: [ 0x89, 0xa2, 0x3b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, POR_EL0"
+
+  -
+    input:
+      bytes: [ 0x89, 0xa2, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, POR_EL1"
+
+  -
+    input:
+      bytes: [ 0x89, 0xa2, 0x3d, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, POR_EL12"
+
+  -
+    input:
+      bytes: [ 0x89, 0xa2, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, POR_EL2"
+
+  -
+    input:
+      bytes: [ 0x89, 0xa2, 0x3e, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, POR_EL3"
+
+  -
+    input:
+      bytes: [ 0xa9, 0xa2, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, S2POR_EL1"
+
+  -
+    input:
+      bytes: [ 0x69, 0x10, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, SCTLR2_EL1"
+
+  -
+    input:
+      bytes: [ 0x69, 0x10, 0x3d, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, SCTLR2_EL12"
+
+  -
+    input:
+      bytes: [ 0x69, 0x10, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, SCTLR2_EL2"
+
+  -
+    input:
+      bytes: [ 0x69, 0x10, 0x3e, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, SCTLR2_EL3"
+
+  -
+    input:
+      bytes: [ 0x69, 0x20, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, TCR2_EL1"
+
+  -
+    input:
+      bytes: [ 0x69, 0x20, 0x3d, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, TCR2_EL12"
+
+  -
+    input:
+      bytes: [ 0x69, 0x20, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, TCR2_EL2"
+
+  -
+    input:
+      bytes: [ 0xac, 0xf1, 0x3f, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x12, S3_7_C15_C1_5"
+
+  -
+    input:
+      bytes: [ 0xed, 0xbf, 0x3a, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x13, S3_2_C11_C15_7"
+
+  -
+    input:
+      bytes: [ 0x2e, 0x92, 0x2b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "sysl	x14, #3, c9, c2, #1"
+    skip_reason: "Just a note: This test is correct, llvm-mc emits the msr variant, when it assembles. Disassembly only matches."
+
+  -
+    input:
+      bytes: [ 0x0c, 0xf0, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr S3_0_C15_C0_0, x12"
+
+  -
+    input:
+      bytes: [ 0xe5, 0xbd, 0x1f, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr S3_7_C11_C13_7, x5"
+
+  -
+    input:
+      bytes: [ 0x24, 0x92, 0x0b, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "sys #3, c9, c2, #1, x4"
+    skip_reason: "Just a note: This test is correct, llvm-mc emits the msr variant, when it assembles. Disassembly only matches."
+
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0x00, 0x14 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "b #4"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x00, 0x94 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "bl #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0xff, 0x15 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "b #134217724"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x00, 0x96 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "bl #-134217728"
+
+  -
+    input:
+      bytes: [ 0x80, 0x02, 0x1f, 0xd6 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "br x20"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x03, 0x3f, 0xd6 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "blr xzr"
+
+  -
+    input:
+      bytes: [ 0x40, 0x01, 0x5f, 0xd6 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ret x10"
+
+  -
+    input:
+      bytes: [ 0xc0, 0x03, 0x5f, 0xd6 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "ret"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x03, 0x9f, 0xd6 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "eret"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x03, 0xbf, 0xd6 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8a", "+fp-armv8" ]
+    expected:
+      insns:
+        -
+          asm_text: "drps"
diff --git a/tests/MC/AArch64/case-insen-reg-names.s.yaml b/tests/MC/AArch64/case-insen-reg-names.s.yaml
new file mode 100644
index 000000000..36792f519
--- /dev/null
+++ b/tests/MC/AArch64/case-insen-reg-names.s.yaml
@@ -0,0 +1,30 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xa0, 0xd4, 0x66, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd v0.2d, v5.2d, v6.2d"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xd4, 0x66, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd v0.2d, v5.2d, v6.2d"
+
+  -
+    input:
+      bytes: [ 0xa0, 0xd4, 0x66, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd v0.2d, v5.2d, v6.2d"
diff --git a/tests/MC/AArch64/dot-req.s.yaml b/tests/MC/AArch64/dot-req.s.yaml
new file mode 100644
index 000000000..83b9694aa
--- /dev/null
+++ b/tests/MC/AArch64/dot-req.s.yaml
@@ -0,0 +1,110 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xe5, 0x03, 0x0b, 0xaa ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov x5, x11"
+
+  -
+    input:
+      bytes: [ 0xe1, 0x03, 0x06, 0x2a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov w1, w6"
+
+  -
+    input:
+      bytes: [ 0xe1, 0x03, 0x06, 0x2a ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov w1, w6"
+
+  -
+    input:
+      bytes: [ 0x06, 0xb8, 0x31, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "addv b6, v0.8b"
+
+  -
+    input:
+      bytes: [ 0x85, 0x04, 0x0e, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov h5, v4.h[3]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x28, 0x24, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd s0, s4, s4"
+
+  -
+    input:
+      bytes: [ 0x62, 0x40, 0x60, 0x1e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov d2, d3"
+
+  -
+    input:
+      bytes: [ 0xe2, 0x03, 0xc0, 0x3d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr q2, [sp]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x1c, 0xa1, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov v0.8b, v1.8b"
+
+  -
+    input:
+      bytes: [ 0x06, 0x00, 0x00, 0x8b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "add x6, x0, x0"
+
+  -
+    input:
+      bytes: [ 0x06, 0x00, 0x00, 0x8b ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "add x6, x0, x0"
diff --git a/tests/MC/AArch64/ete-sysregs.s.yaml b/tests/MC/AArch64/ete-sysregs.s.yaml
new file mode 100644
index 000000000..661d8e3f6
--- /dev/null
+++ b/tests/MC/AArch64/ete-sysregs.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x0a, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, TRCRSR"
+
+  -
+    input:
+      bytes: [ 0x80, 0x08, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, TRCEXTINSELR"
+
+  -
+    input:
+      bytes: [ 0x80, 0x08, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, TRCEXTINSELR"
+
+  -
+    input:
+      bytes: [ 0x80, 0x09, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, TRCEXTINSELR1"
+
+  -
+    input:
+      bytes: [ 0x80, 0x0a, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, TRCEXTINSELR2"
+
+  -
+    input:
+      bytes: [ 0x80, 0x0b, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, TRCEXTINSELR3"
+
+  -
+    input:
+      bytes: [ 0x00, 0x0a, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCRSR, x0"
+
+  -
+    input:
+      bytes: [ 0x80, 0x08, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCEXTINSELR, x0"
+
+  -
+    input:
+      bytes: [ 0x80, 0x08, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCEXTINSELR, x0"
+
+  -
+    input:
+      bytes: [ 0x80, 0x09, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCEXTINSELR1, x0"
+
+  -
+    input:
+      bytes: [ 0x80, 0x0a, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCEXTINSELR2, x0"
+
+  -
+    input:
+      bytes: [ 0x80, 0x0b, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCEXTINSELR3, x0"
diff --git a/tests/MC/AArch64/gicv3-regs.s.yaml b/tests/MC/AArch64/gicv3-regs.s.yaml
new file mode 100644
index 000000000..2df4d8594
--- /dev/null
+++ b/tests/MC/AArch64/gicv3-regs.s.yaml
@@ -0,0 +1,1050 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x08, 0xcc, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x8, ICC_IAR1_EL1"
+
+  -
+    input:
+      bytes: [ 0x1a, 0xc8, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x26, ICC_IAR0_EL1"
+
+  -
+    input:
+      bytes: [ 0x42, 0xcc, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x2, ICC_HPPIR1_EL1"
+
+  -
+    input:
+      bytes: [ 0x51, 0xc8, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x17, ICC_HPPIR0_EL1"
+
+  -
+    input:
+      bytes: [ 0x7d, 0xcb, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x29, ICC_RPR_EL1"
+
+  -
+    input:
+      bytes: [ 0x24, 0xcb, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x4, ICH_VTR_EL2"
+
+  -
+    input:
+      bytes: [ 0x78, 0xcb, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x24, ICH_EISR_EL2"
+
+  -
+    input:
+      bytes: [ 0xa9, 0xcb, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, ICH_ELRSR_EL2"
+
+  -
+    input:
+      bytes: [ 0x78, 0xcc, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x24, ICC_BPR1_EL1"
+
+  -
+    input:
+      bytes: [ 0x6e, 0xc8, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x14, ICC_BPR0_EL1"
+
+  -
+    input:
+      bytes: [ 0x13, 0x46, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x19, ICC_PMR_EL1"
+
+  -
+    input:
+      bytes: [ 0x97, 0xcc, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x23, ICC_CTLR_EL1"
+
+  -
+    input:
+      bytes: [ 0x94, 0xcc, 0x3e, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x20, ICC_CTLR_EL3"
+
+  -
+    input:
+      bytes: [ 0xbc, 0xcc, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x28, ICC_SRE_EL1"
+
+  -
+    input:
+      bytes: [ 0xb9, 0xc9, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x25, ICC_SRE_EL2"
+
+  -
+    input:
+      bytes: [ 0xa8, 0xcc, 0x3e, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x8, ICC_SRE_EL3"
+
+  -
+    input:
+      bytes: [ 0xd6, 0xcc, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x22, ICC_IGRPEN0_EL1"
+
+  -
+    input:
+      bytes: [ 0xe5, 0xcc, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x5, ICC_IGRPEN1_EL1"
+
+  -
+    input:
+      bytes: [ 0xe7, 0xcc, 0x3e, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x7, ICC_IGRPEN1_EL3"
+
+  -
+    input:
+      bytes: [ 0x84, 0xc8, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x4, ICC_AP0R0_EL1"
+
+  -
+    input:
+      bytes: [ 0xab, 0xc8, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x11, ICC_AP0R1_EL1"
+
+  -
+    input:
+      bytes: [ 0xdb, 0xc8, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x27, ICC_AP0R2_EL1"
+
+  -
+    input:
+      bytes: [ 0xf5, 0xc8, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x21, ICC_AP0R3_EL1"
+
+  -
+    input:
+      bytes: [ 0x02, 0xc9, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x2, ICC_AP1R0_EL1"
+
+  -
+    input:
+      bytes: [ 0x35, 0xc9, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x21, ICC_AP1R1_EL1"
+
+  -
+    input:
+      bytes: [ 0x4a, 0xc9, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x10, ICC_AP1R2_EL1"
+
+  -
+    input:
+      bytes: [ 0x7b, 0xc9, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x27, ICC_AP1R3_EL1"
+
+  -
+    input:
+      bytes: [ 0x14, 0xc8, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x20, ICH_AP0R0_EL2"
+
+  -
+    input:
+      bytes: [ 0x35, 0xc8, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x21, ICH_AP0R1_EL2"
+
+  -
+    input:
+      bytes: [ 0x45, 0xc8, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x5, ICH_AP0R2_EL2"
+
+  -
+    input:
+      bytes: [ 0x64, 0xc8, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x4, ICH_AP0R3_EL2"
+
+  -
+    input:
+      bytes: [ 0x0f, 0xc9, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x15, ICH_AP1R0_EL2"
+
+  -
+    input:
+      bytes: [ 0x2c, 0xc9, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x12, ICH_AP1R1_EL2"
+
+  -
+    input:
+      bytes: [ 0x5b, 0xc9, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x27, ICH_AP1R2_EL2"
+
+  -
+    input:
+      bytes: [ 0x74, 0xc9, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x20, ICH_AP1R3_EL2"
+
+  -
+    input:
+      bytes: [ 0x0a, 0xcb, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x10, ICH_HCR_EL2"
+
+  -
+    input:
+      bytes: [ 0x5b, 0xcb, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x27, ICH_MISR_EL2"
+
+  -
+    input:
+      bytes: [ 0xe6, 0xcb, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x6, ICH_VMCR_EL2"
+
+  -
+    input:
+      bytes: [ 0x03, 0xcc, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, ICH_LR0_EL2"
+
+  -
+    input:
+      bytes: [ 0x21, 0xcc, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x1, ICH_LR1_EL2"
+
+  -
+    input:
+      bytes: [ 0x56, 0xcc, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x22, ICH_LR2_EL2"
+
+  -
+    input:
+      bytes: [ 0x75, 0xcc, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x21, ICH_LR3_EL2"
+
+  -
+    input:
+      bytes: [ 0x86, 0xcc, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x6, ICH_LR4_EL2"
+
+  -
+    input:
+      bytes: [ 0xaa, 0xcc, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x10, ICH_LR5_EL2"
+
+  -
+    input:
+      bytes: [ 0xcb, 0xcc, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x11, ICH_LR6_EL2"
+
+  -
+    input:
+      bytes: [ 0xec, 0xcc, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x12, ICH_LR7_EL2"
+
+  -
+    input:
+      bytes: [ 0x00, 0xcd, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, ICH_LR8_EL2"
+
+  -
+    input:
+      bytes: [ 0x35, 0xcd, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x21, ICH_LR9_EL2"
+
+  -
+    input:
+      bytes: [ 0x4d, 0xcd, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x13, ICH_LR10_EL2"
+
+  -
+    input:
+      bytes: [ 0x7a, 0xcd, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x26, ICH_LR11_EL2"
+
+  -
+    input:
+      bytes: [ 0x81, 0xcd, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x1, ICH_LR12_EL2"
+
+  -
+    input:
+      bytes: [ 0xa8, 0xcd, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x8, ICH_LR13_EL2"
+
+  -
+    input:
+      bytes: [ 0xc2, 0xcd, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x2, ICH_LR14_EL2"
+
+  -
+    input:
+      bytes: [ 0xe8, 0xcd, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x8, ICH_LR15_EL2"
+
+  -
+    input:
+      bytes: [ 0x3b, 0xcc, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ICC_EOIR1_EL1, x27"
+
+  -
+    input:
+      bytes: [ 0x25, 0xc8, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ICC_EOIR0_EL1, x5"
+
+  -
+    input:
+      bytes: [ 0x2d, 0xcb, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ICC_DIR_EL1, x13"
+
+  -
+    input:
+      bytes: [ 0xb5, 0xcb, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ICC_SGI1R_EL1, x21"
+
+  -
+    input:
+      bytes: [ 0xd9, 0xcb, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ICC_ASGI1R_EL1, x25"
+
+  -
+    input:
+      bytes: [ 0xfc, 0xcb, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ICC_SGI0R_EL1, x28"
+
+  -
+    input:
+      bytes: [ 0x67, 0xcc, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ICC_BPR1_EL1, x7"
+
+  -
+    input:
+      bytes: [ 0x69, 0xc8, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ICC_BPR0_EL1, x9"
+
+  -
+    input:
+      bytes: [ 0x1d, 0x46, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ICC_PMR_EL1, x29"
+
+  -
+    input:
+      bytes: [ 0x98, 0xcc, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ICC_CTLR_EL1, x24"
+
+  -
+    input:
+      bytes: [ 0x80, 0xcc, 0x1e, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ICC_CTLR_EL3, x0"
+
+  -
+    input:
+      bytes: [ 0xa2, 0xcc, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ICC_SRE_EL1, x2"
+
+  -
+    input:
+      bytes: [ 0xa5, 0xc9, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ICC_SRE_EL2, x5"
+
+  -
+    input:
+      bytes: [ 0xaa, 0xcc, 0x1e, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ICC_SRE_EL3, x10"
+
+  -
+    input:
+      bytes: [ 0xd6, 0xcc, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ICC_IGRPEN0_EL1, x22"
+
+  -
+    input:
+      bytes: [ 0xeb, 0xcc, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ICC_IGRPEN1_EL1, x11"
+
+  -
+    input:
+      bytes: [ 0xe8, 0xcc, 0x1e, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ICC_IGRPEN1_EL3, x8"
+
+  -
+    input:
+      bytes: [ 0x9b, 0xc8, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ICC_AP0R0_EL1, x27"
+
+  -
+    input:
+      bytes: [ 0xa5, 0xc8, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ICC_AP0R1_EL1, x5"
+
+  -
+    input:
+      bytes: [ 0xd4, 0xc8, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ICC_AP0R2_EL1, x20"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xc8, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ICC_AP0R3_EL1, x0"
+
+  -
+    input:
+      bytes: [ 0x02, 0xc9, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ICC_AP1R0_EL1, x2"
+
+  -
+    input:
+      bytes: [ 0x3d, 0xc9, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ICC_AP1R1_EL1, x29"
+
+  -
+    input:
+      bytes: [ 0x57, 0xc9, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ICC_AP1R2_EL1, x23"
+
+  -
+    input:
+      bytes: [ 0x6b, 0xc9, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ICC_AP1R3_EL1, x11"
+
+  -
+    input:
+      bytes: [ 0x02, 0xc8, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ICH_AP0R0_EL2, x2"
+
+  -
+    input:
+      bytes: [ 0x3b, 0xc8, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ICH_AP0R1_EL2, x27"
+
+  -
+    input:
+      bytes: [ 0x47, 0xc8, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ICH_AP0R2_EL2, x7"
+
+  -
+    input:
+      bytes: [ 0x61, 0xc8, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ICH_AP0R3_EL2, x1"
+
+  -
+    input:
+      bytes: [ 0x07, 0xc9, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ICH_AP1R0_EL2, x7"
+
+  -
+    input:
+      bytes: [ 0x2c, 0xc9, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ICH_AP1R1_EL2, x12"
+
+  -
+    input:
+      bytes: [ 0x4e, 0xc9, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ICH_AP1R2_EL2, x14"
+
+  -
+    input:
+      bytes: [ 0x6d, 0xc9, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ICH_AP1R3_EL2, x13"
+
+  -
+    input:
+      bytes: [ 0x01, 0xcb, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ICH_HCR_EL2, x1"
+
+  -
+    input:
+      bytes: [ 0xf8, 0xcb, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ICH_VMCR_EL2, x24"
+
+  -
+    input:
+      bytes: [ 0x1a, 0xcc, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ICH_LR0_EL2, x26"
+
+  -
+    input:
+      bytes: [ 0x29, 0xcc, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ICH_LR1_EL2, x9"
+
+  -
+    input:
+      bytes: [ 0x52, 0xcc, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ICH_LR2_EL2, x18"
+
+  -
+    input:
+      bytes: [ 0x7a, 0xcc, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ICH_LR3_EL2, x26"
+
+  -
+    input:
+      bytes: [ 0x96, 0xcc, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ICH_LR4_EL2, x22"
+
+  -
+    input:
+      bytes: [ 0xba, 0xcc, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ICH_LR5_EL2, x26"
+
+  -
+    input:
+      bytes: [ 0xdb, 0xcc, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ICH_LR6_EL2, x27"
+
+  -
+    input:
+      bytes: [ 0xe8, 0xcc, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ICH_LR7_EL2, x8"
+
+  -
+    input:
+      bytes: [ 0x11, 0xcd, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ICH_LR8_EL2, x17"
+
+  -
+    input:
+      bytes: [ 0x33, 0xcd, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ICH_LR9_EL2, x19"
+
+  -
+    input:
+      bytes: [ 0x51, 0xcd, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ICH_LR10_EL2, x17"
+
+  -
+    input:
+      bytes: [ 0x65, 0xcd, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ICH_LR11_EL2, x5"
+
+  -
+    input:
+      bytes: [ 0x9d, 0xcd, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ICH_LR12_EL2, x29"
+
+  -
+    input:
+      bytes: [ 0xa2, 0xcd, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ICH_LR13_EL2, x2"
+
+  -
+    input:
+      bytes: [ 0xcd, 0xcd, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ICH_LR14_EL2, x13"
+
+  -
+    input:
+      bytes: [ 0xfb, 0xcd, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ICH_LR15_EL2, x27"
diff --git a/tests/MC/AArch64/neon-2velem.s.yaml b/tests/MC/AArch64/neon-2velem.s.yaml
new file mode 100644
index 000000000..042b62811
--- /dev/null
+++ b/tests/MC/AArch64/neon-2velem.s.yaml
@@ -0,0 +1,1200 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x08, 0x82, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "mla v0.2s, v1.2s, v2.s[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x08, 0x96, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "mla v0.2s, v1.2s, v22.s[2]"
+
+  -
+    input:
+      bytes: [ 0x03, 0x01, 0xa2, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "mla v3.4s, v8.4s, v2.s[1]"
+
+  -
+    input:
+      bytes: [ 0x03, 0x09, 0xb6, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "mla v3.4s, v8.4s, v22.s[3]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x00, 0x62, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "mla v0.4h, v1.4h, v2.h[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x00, 0x6f, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "mla v0.4h, v1.4h, v15.h[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x08, 0x72, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "mla v0.8h, v1.8h, v2.h[7]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x08, 0x6e, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "mla v0.8h, v1.8h, v14.h[6]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x48, 0x82, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "mls v0.2s, v1.2s, v2.s[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x48, 0x96, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "mls v0.2s, v1.2s, v22.s[2]"
+
+  -
+    input:
+      bytes: [ 0x03, 0x41, 0xa2, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "mls v3.4s, v8.4s, v2.s[1]"
+
+  -
+    input:
+      bytes: [ 0x03, 0x49, 0xb6, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "mls v3.4s, v8.4s, v22.s[3]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x40, 0x62, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "mls v0.4h, v1.4h, v2.h[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x40, 0x6f, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "mls v0.4h, v1.4h, v15.h[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x48, 0x72, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "mls v0.8h, v1.8h, v2.h[7]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x48, 0x6e, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "mls v0.8h, v1.8h, v14.h[6]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x10, 0x22, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla v0.4h, v1.4h, v2.h[2]"
+
+  -
+    input:
+      bytes: [ 0x03, 0x11, 0x12, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla v3.8h, v8.8h, v2.h[1]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x18, 0x82, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla v0.2s, v1.2s, v2.s[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x18, 0x96, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla v0.2s, v1.2s, v22.s[2]"
+
+  -
+    input:
+      bytes: [ 0x03, 0x11, 0xa2, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla v3.4s, v8.4s, v2.s[1]"
+
+  -
+    input:
+      bytes: [ 0x03, 0x19, 0xb6, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla v3.4s, v8.4s, v22.s[3]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x18, 0xc2, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla v0.2d, v1.2d, v2.d[1]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x18, 0xd6, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla v0.2d, v1.2d, v22.d[1]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x50, 0x22, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls v0.4h, v1.4h, v2.h[2]"
+
+  -
+    input:
+      bytes: [ 0x03, 0x51, 0x12, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls v3.8h, v8.8h, v2.h[1]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x58, 0x82, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls v0.2s, v1.2s, v2.s[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x58, 0x96, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls v0.2s, v1.2s, v22.s[2]"
+
+  -
+    input:
+      bytes: [ 0x03, 0x51, 0xa2, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls v3.4s, v8.4s, v2.s[1]"
+
+  -
+    input:
+      bytes: [ 0x03, 0x59, 0xb6, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls v3.4s, v8.4s, v22.s[3]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x58, 0xc2, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls v0.2d, v1.2d, v2.d[1]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x58, 0xd6, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls v0.2d, v1.2d, v22.d[1]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x20, 0x62, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal v0.4s, v1.4h, v2.h[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x28, 0x82, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal v0.2d, v1.2s, v2.s[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x28, 0x96, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal v0.2d, v1.2s, v22.s[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x20, 0x61, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal2 v0.4s, v1.8h, v1.h[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x28, 0x81, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal2 v0.2d, v1.4s, v1.s[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x28, 0x96, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal2 v0.2d, v1.4s, v22.s[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x60, 0x62, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl v0.4s, v1.4h, v2.h[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x68, 0x82, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl v0.2d, v1.2s, v2.s[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x68, 0x96, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl v0.2d, v1.2s, v22.s[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x60, 0x61, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl2 v0.4s, v1.8h, v1.h[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x68, 0x81, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl2 v0.2d, v1.4s, v1.s[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x68, 0x96, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl2 v0.2d, v1.4s, v22.s[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x30, 0x62, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmlal v0.4s, v1.4h, v2.h[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x38, 0x82, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmlal v0.2d, v1.2s, v2.s[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x38, 0x96, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmlal v0.2d, v1.2s, v22.s[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x30, 0x61, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmlal2 v0.4s, v1.8h, v1.h[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x38, 0x81, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmlal2 v0.2d, v1.4s, v1.s[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x38, 0x96, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmlal2 v0.2d, v1.4s, v22.s[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x20, 0x62, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal v0.4s, v1.4h, v2.h[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x28, 0x82, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal v0.2d, v1.2s, v2.s[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x28, 0x96, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal v0.2d, v1.2s, v22.s[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x20, 0x61, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal2 v0.4s, v1.8h, v1.h[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x28, 0x81, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal2 v0.2d, v1.4s, v1.s[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x28, 0x96, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal2 v0.2d, v1.4s, v22.s[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x60, 0x62, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl v0.4s, v1.4h, v2.h[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x68, 0x82, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl v0.2d, v1.2s, v2.s[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x68, 0x96, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl v0.2d, v1.2s, v22.s[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x60, 0x61, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl2 v0.4s, v1.8h, v1.h[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x68, 0x81, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl2 v0.2d, v1.4s, v1.s[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x68, 0x96, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl2 v0.2d, v1.4s, v22.s[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x70, 0x62, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmlsl v0.4s, v1.4h, v2.h[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x78, 0x82, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmlsl v0.2d, v1.2s, v2.s[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x78, 0x96, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmlsl v0.2d, v1.2s, v22.s[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x70, 0x61, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmlsl2 v0.4s, v1.8h, v1.h[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x78, 0x81, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmlsl2 v0.2d, v1.4s, v1.s[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x78, 0x96, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmlsl2 v0.2d, v1.4s, v22.s[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x62, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul v0.4h, v1.4h, v2.h[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x62, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul v0.8h, v1.8h, v2.h[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x88, 0x82, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul v0.2s, v1.2s, v2.s[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x88, 0x96, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul v0.2s, v1.2s, v22.s[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x88, 0x82, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul v0.4s, v1.4s, v2.s[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x88, 0x96, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul v0.4s, v1.4s, v22.s[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x90, 0x22, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmul v0.4h, v1.4h, v2.h[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x90, 0x22, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmul v0.8h, v1.8h, v2.h[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x98, 0x82, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmul v0.2s, v1.2s, v2.s[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x98, 0x96, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmul v0.2s, v1.2s, v22.s[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x98, 0x82, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmul v0.4s, v1.4s, v2.s[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x98, 0x96, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmul v0.4s, v1.4s, v22.s[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x98, 0xc2, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmul v0.2d, v1.2d, v2.d[1]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x98, 0xd6, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmul v0.2d, v1.2d, v22.d[1]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x90, 0x22, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmulx v0.4h, v1.4h, v2.h[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x90, 0x22, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmulx v0.8h, v1.8h, v2.h[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x98, 0x82, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmulx v0.2s, v1.2s, v2.s[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x98, 0x96, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmulx v0.2s, v1.2s, v22.s[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x98, 0x82, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmulx v0.4s, v1.4s, v2.s[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x98, 0x96, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmulx v0.4s, v1.4s, v22.s[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x98, 0xc2, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmulx v0.2d, v1.2d, v2.d[1]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x98, 0xd6, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmulx v0.2d, v1.2d, v22.d[1]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa0, 0x62, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "smull v0.4s, v1.4h, v2.h[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa8, 0x82, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "smull v0.2d, v1.2s, v2.s[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa8, 0x96, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "smull v0.2d, v1.2s, v22.s[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa0, 0x62, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "smull2 v0.4s, v1.8h, v2.h[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa8, 0x82, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "smull2 v0.2d, v1.4s, v2.s[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa8, 0x96, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "smull2 v0.2d, v1.4s, v22.s[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa0, 0x62, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "umull v0.4s, v1.4h, v2.h[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa8, 0x82, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "umull v0.2d, v1.2s, v2.s[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa8, 0x96, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "umull v0.2d, v1.2s, v22.s[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa0, 0x62, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "umull2 v0.4s, v1.8h, v2.h[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa8, 0x82, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "umull2 v0.2d, v1.4s, v2.s[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa8, 0x96, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "umull2 v0.2d, v1.4s, v22.s[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xb0, 0x62, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmull v0.4s, v1.4h, v2.h[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xb8, 0x82, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmull v0.2d, v1.2s, v2.s[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xb8, 0x96, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmull v0.2d, v1.2s, v22.s[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xb0, 0x62, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmull2 v0.4s, v1.8h, v2.h[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xb8, 0x82, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmull2 v0.2d, v1.4s, v2.s[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xb8, 0x96, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmull2 v0.2d, v1.4s, v22.s[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc0, 0x62, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmulh v0.4h, v1.4h, v2.h[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc0, 0x62, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmulh v0.8h, v1.8h, v2.h[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc8, 0x82, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmulh v0.2s, v1.2s, v2.s[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc8, 0x96, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmulh v0.2s, v1.2s, v22.s[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc8, 0x82, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmulh v0.4s, v1.4s, v2.s[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc8, 0x96, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmulh v0.4s, v1.4s, v22.s[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd0, 0x62, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrdmulh v0.4h, v1.4h, v2.h[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd0, 0x62, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrdmulh v0.8h, v1.8h, v2.h[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd8, 0x82, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrdmulh v0.2s, v1.2s, v2.s[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd8, 0x96, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrdmulh v0.2s, v1.2s, v22.s[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd8, 0x82, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrdmulh v0.4s, v1.4s, v2.s[2]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd8, 0x96, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrdmulh v0.4s, v1.4s, v22.s[2]"
diff --git a/tests/MC/AArch64/neon-3vdiff.s.yaml b/tests/MC/AArch64/neon-3vdiff.s.yaml
new file mode 100644
index 000000000..5c7d3c0d7
--- /dev/null
+++ b/tests/MC/AArch64/neon-3vdiff.s.yaml
@@ -0,0 +1,1420 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x00, 0x22, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "saddl v0.8h, v1.8b, v2.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x00, 0x62, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "saddl v0.4s, v1.4h, v2.4h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x00, 0xa2, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "saddl v0.2d, v1.2s, v2.2s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x00, 0x62, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "saddl2 v0.4s, v1.8h, v2.8h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x00, 0x22, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "saddl2 v0.8h, v1.16b, v2.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x00, 0xa2, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "saddl2 v0.2d, v1.4s, v2.4s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x00, 0x22, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "uaddl v0.8h, v1.8b, v2.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x00, 0x62, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "uaddl v0.4s, v1.4h, v2.4h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x00, 0xa2, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "uaddl v0.2d, v1.2s, v2.2s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x00, 0x22, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "uaddl2 v0.8h, v1.16b, v2.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x00, 0x62, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "uaddl2 v0.4s, v1.8h, v2.8h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x00, 0xa2, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "uaddl2 v0.2d, v1.4s, v2.4s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x20, 0x22, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ssubl v0.8h, v1.8b, v2.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x20, 0x62, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ssubl v0.4s, v1.4h, v2.4h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x20, 0xa2, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ssubl v0.2d, v1.2s, v2.2s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x20, 0x22, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ssubl2 v0.8h, v1.16b, v2.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x20, 0x62, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ssubl2 v0.4s, v1.8h, v2.8h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x20, 0xa2, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ssubl2 v0.2d, v1.4s, v2.4s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x20, 0x22, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "usubl v0.8h, v1.8b, v2.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x20, 0x62, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "usubl v0.4s, v1.4h, v2.4h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x20, 0xa2, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "usubl v0.2d, v1.2s, v2.2s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x20, 0x22, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "usubl2 v0.8h, v1.16b, v2.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x20, 0x62, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "usubl2 v0.4s, v1.8h, v2.8h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x20, 0xa2, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "usubl2 v0.2d, v1.4s, v2.4s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x50, 0x22, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sabal v0.8h, v1.8b, v2.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x50, 0x62, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sabal v0.4s, v1.4h, v2.4h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x50, 0xa2, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sabal v0.2d, v1.2s, v2.2s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x50, 0x22, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sabal2 v0.8h, v1.16b, v2.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x50, 0x62, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sabal2 v0.4s, v1.8h, v2.8h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x50, 0xa2, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sabal2 v0.2d, v1.4s, v2.4s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x50, 0x22, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "uabal v0.8h, v1.8b, v2.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x50, 0x62, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "uabal v0.4s, v1.4h, v2.4h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x50, 0xa2, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "uabal v0.2d, v1.2s, v2.2s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x50, 0x22, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "uabal2 v0.8h, v1.16b, v2.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x50, 0x62, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "uabal2 v0.4s, v1.8h, v2.8h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x50, 0xa2, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "uabal2 v0.2d, v1.4s, v2.4s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x70, 0x22, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sabdl v0.8h, v1.8b, v2.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x70, 0x62, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sabdl v0.4s, v1.4h, v2.4h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x70, 0xa2, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sabdl v0.2d, v1.2s, v2.2s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x70, 0x22, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sabdl2 v0.8h, v1.16b, v2.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x70, 0x62, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sabdl2 v0.4s, v1.8h, v2.8h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x70, 0xa2, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sabdl2 v0.2d, v1.4s, v2.4s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x70, 0x22, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "uabdl v0.8h, v1.8b, v2.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x70, 0x62, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "uabdl v0.4s, v1.4h, v2.4h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x70, 0xa2, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "uabdl v0.2d, v1.2s, v2.2s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x70, 0x22, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "uabdl2 v0.8h, v1.16b, v2.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x70, 0x62, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "uabdl2 v0.4s, v1.8h, v2.8h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x70, 0xa2, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "uabdl2 v0.2d, v1.4s, v2.4s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x22, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal v0.8h, v1.8b, v2.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x62, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal v0.4s, v1.4h, v2.4h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0xa2, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal v0.2d, v1.2s, v2.2s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x22, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal2 v0.8h, v1.16b, v2.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x62, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal2 v0.4s, v1.8h, v2.8h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0xa2, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlal2 v0.2d, v1.4s, v2.4s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x22, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal v0.8h, v1.8b, v2.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x62, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal v0.4s, v1.4h, v2.4h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0xa2, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal v0.2d, v1.2s, v2.2s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x22, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal2 v0.8h, v1.16b, v2.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0x62, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal2 v0.4s, v1.8h, v2.8h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x80, 0xa2, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlal2 v0.2d, v1.4s, v2.4s"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa0, 0x22, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl v0.8h, v1.8b, v2.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa0, 0x62, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl v0.4s, v1.4h, v2.4h"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa0, 0xa2, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl v0.2d, v1.2s, v2.2s"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa0, 0x22, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl2 v0.8h, v1.16b, v2.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa0, 0x62, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl2 v0.4s, v1.8h, v2.8h"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa0, 0xa2, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "smlsl2 v0.2d, v1.4s, v2.4s"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa0, 0x22, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl v0.8h, v1.8b, v2.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa0, 0x62, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl v0.4s, v1.4h, v2.4h"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa0, 0xa2, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl v0.2d, v1.2s, v2.2s"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa0, 0x22, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl2 v0.8h, v1.16b, v2.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa0, 0x62, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl2 v0.4s, v1.8h, v2.8h"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa0, 0xa2, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "umlsl2 v0.2d, v1.4s, v2.4s"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc0, 0x22, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "smull v0.8h, v1.8b, v2.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc0, 0x62, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "smull v0.4s, v1.4h, v2.4h"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc0, 0xa2, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "smull v0.2d, v1.2s, v2.2s"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc0, 0x22, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "smull2 v0.8h, v1.16b, v2.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc0, 0x62, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "smull2 v0.4s, v1.8h, v2.8h"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc0, 0xa2, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "smull2 v0.2d, v1.4s, v2.4s"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc0, 0x22, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "umull v0.8h, v1.8b, v2.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc0, 0x62, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "umull v0.4s, v1.4h, v2.4h"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc0, 0xa2, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "umull v0.2d, v1.2s, v2.2s"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc0, 0x22, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "umull2 v0.8h, v1.16b, v2.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc0, 0x62, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "umull2 v0.4s, v1.8h, v2.8h"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc0, 0xa2, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "umull2 v0.2d, v1.4s, v2.4s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x90, 0x62, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmlal v0.4s, v1.4h, v2.4h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x90, 0xa2, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmlal v0.2d, v1.2s, v2.2s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x90, 0x62, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmlal2 v0.4s, v1.8h, v2.8h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x90, 0xa2, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmlal2 v0.2d, v1.4s, v2.4s"
+
+  -
+    input:
+      bytes: [ 0x20, 0xb0, 0x62, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmlsl v0.4s, v1.4h, v2.4h"
+
+  -
+    input:
+      bytes: [ 0x20, 0xb0, 0xa2, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmlsl v0.2d, v1.2s, v2.2s"
+
+  -
+    input:
+      bytes: [ 0x20, 0xb0, 0x62, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmlsl2 v0.4s, v1.8h, v2.8h"
+
+  -
+    input:
+      bytes: [ 0x20, 0xb0, 0xa2, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmlsl2 v0.2d, v1.4s, v2.4s"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd0, 0x62, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmull v0.4s, v1.4h, v2.4h"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd0, 0xa2, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmull v0.2d, v1.2s, v2.2s"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd0, 0x62, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmull2 v0.4s, v1.8h, v2.8h"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd0, 0xa2, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmull2 v0.2d, v1.4s, v2.4s"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe0, 0x22, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "pmull v0.8h, v1.8b, v2.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe0, 0xe2, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "pmull v0.1q, v1.1d, v2.1d"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe0, 0x22, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "pmull2 v0.8h, v1.16b, v2.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe0, 0xe2, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "pmull2 v0.1q, v1.2d, v2.2d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x10, 0x22, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "saddw v0.8h, v1.8h, v2.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x10, 0x62, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "saddw v0.4s, v1.4s, v2.4h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x10, 0xa2, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "saddw v0.2d, v1.2d, v2.2s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x10, 0x22, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "saddw2 v0.8h, v1.8h, v2.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x10, 0x62, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "saddw2 v0.4s, v1.4s, v2.8h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x10, 0xa2, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "saddw2 v0.2d, v1.2d, v2.4s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x10, 0x22, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "uaddw v0.8h, v1.8h, v2.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x10, 0x62, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "uaddw v0.4s, v1.4s, v2.4h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x10, 0xa2, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "uaddw v0.2d, v1.2d, v2.2s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x10, 0x22, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "uaddw2 v0.8h, v1.8h, v2.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x10, 0x62, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "uaddw2 v0.4s, v1.4s, v2.8h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x10, 0xa2, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "uaddw2 v0.2d, v1.2d, v2.4s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x30, 0x22, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ssubw v0.8h, v1.8h, v2.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x30, 0x62, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ssubw v0.4s, v1.4s, v2.4h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x30, 0xa2, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ssubw v0.2d, v1.2d, v2.2s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x30, 0x22, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ssubw2 v0.8h, v1.8h, v2.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x30, 0x62, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ssubw2 v0.4s, v1.4s, v2.8h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x30, 0xa2, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ssubw2 v0.2d, v1.2d, v2.4s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x30, 0x22, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "usubw v0.8h, v1.8h, v2.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x30, 0x62, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "usubw v0.4s, v1.4s, v2.4h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x30, 0xa2, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "usubw v0.2d, v1.2d, v2.2s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x30, 0x22, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "usubw2 v0.8h, v1.8h, v2.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x30, 0x62, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "usubw2 v0.4s, v1.4s, v2.8h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x30, 0xa2, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "usubw2 v0.2d, v1.2d, v2.4s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x40, 0x22, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "addhn v0.8b, v1.8h, v2.8h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x40, 0x62, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "addhn v0.4h, v1.4s, v2.4s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x40, 0xa2, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "addhn v0.2s, v1.2d, v2.2d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x40, 0x22, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "addhn2 v0.16b, v1.8h, v2.8h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x40, 0x62, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "addhn2 v0.8h, v1.4s, v2.4s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x40, 0xa2, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "addhn2 v0.4s, v1.2d, v2.2d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x40, 0x22, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "raddhn v0.8b, v1.8h, v2.8h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x40, 0x62, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "raddhn v0.4h, v1.4s, v2.4s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x40, 0xa2, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "raddhn v0.2s, v1.2d, v2.2d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x40, 0x22, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "raddhn2 v0.16b, v1.8h, v2.8h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x40, 0x62, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "raddhn2 v0.8h, v1.4s, v2.4s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x40, 0xa2, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "raddhn2 v0.4s, v1.2d, v2.2d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x60, 0x22, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "rsubhn v0.8b, v1.8h, v2.8h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x60, 0x62, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "rsubhn v0.4h, v1.4s, v2.4s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x60, 0xa2, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "rsubhn v0.2s, v1.2d, v2.2d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x60, 0x22, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "rsubhn2 v0.16b, v1.8h, v2.8h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x60, 0x62, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "rsubhn2 v0.8h, v1.4s, v2.4s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x60, 0xa2, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "crypto", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "rsubhn2 v0.4s, v1.2d, v2.2d"
diff --git a/tests/MC/AArch64/neon-aba-abd.s.yaml b/tests/MC/AArch64/neon-aba-abd.s.yaml
new file mode 100644
index 000000000..4f9eedc7a
--- /dev/null
+++ b/tests/MC/AArch64/neon-aba-abd.s.yaml
@@ -0,0 +1,280 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x7c, 0x22, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "uaba v0.8b, v1.8b, v2.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x7c, 0x22, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "uaba v0.16b, v1.16b, v2.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x7c, 0x62, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "uaba v0.4h, v1.4h, v2.4h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x7c, 0x62, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "uaba v0.8h, v1.8h, v2.8h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x7c, 0xa2, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "uaba v0.2s, v1.2s, v2.2s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x7c, 0xa2, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "uaba v0.4s, v1.4s, v2.4s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x7c, 0x22, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "saba v0.8b, v1.8b, v2.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x7c, 0x22, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "saba v0.16b, v1.16b, v2.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x7c, 0x62, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "saba v0.4h, v1.4h, v2.4h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x7c, 0x62, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "saba v0.8h, v1.8h, v2.8h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x7c, 0xa2, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "saba v0.2s, v1.2s, v2.2s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x7c, 0xa2, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "saba v0.4s, v1.4s, v2.4s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x74, 0x22, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "uabd v0.8b, v1.8b, v2.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x74, 0x22, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "uabd v0.16b, v1.16b, v2.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x74, 0x62, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "uabd v0.4h, v1.4h, v2.4h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x74, 0x62, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "uabd v0.8h, v1.8h, v2.8h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x74, 0xa2, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "uabd v0.2s, v1.2s, v2.2s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x74, 0xa2, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "uabd v0.4s, v1.4s, v2.4s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x74, 0x22, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sabd v0.8b, v1.8b, v2.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x74, 0x22, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sabd v0.16b, v1.16b, v2.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x74, 0x62, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sabd v0.4h, v1.4h, v2.4h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x74, 0x62, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sabd v0.8h, v1.8h, v2.8h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x74, 0xa2, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sabd v0.2s, v1.2s, v2.2s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x74, 0xa2, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sabd v0.4s, v1.4s, v2.4s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x14, 0xc2, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fabd v0.4h, v1.4h, v2.4h"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd4, 0xa2, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fabd v0.2s, v1.2s, v2.2s"
+
+  -
+    input:
+      bytes: [ 0xff, 0xd5, 0xb0, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fabd v31.4s, v15.4s, v16.4s"
+
+  -
+    input:
+      bytes: [ 0x07, 0xd5, 0xf9, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fabd v7.2d, v8.2d, v25.2d"
diff --git a/tests/MC/AArch64/neon-across.s.yaml b/tests/MC/AArch64/neon-across.s.yaml
new file mode 100644
index 000000000..8631d6b09
--- /dev/null
+++ b/tests/MC/AArch64/neon-across.s.yaml
@@ -0,0 +1,470 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x38, 0x30, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "saddlv h0, v1.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x38, 0x30, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "saddlv h0, v1.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x38, 0x70, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "saddlv s0, v1.4h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x38, 0x70, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "saddlv s0, v1.8h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x38, 0xb0, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "saddlv d0, v1.4s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x38, 0x30, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "uaddlv h0, v1.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x38, 0x30, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "uaddlv h0, v1.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x38, 0x70, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "uaddlv s0, v1.4h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x38, 0x70, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "uaddlv s0, v1.8h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x38, 0xb0, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "uaddlv d0, v1.4s"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa8, 0x30, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "smaxv b0, v1.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa8, 0x30, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "smaxv b0, v1.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa8, 0x70, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "smaxv h0, v1.4h"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa8, 0x70, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "smaxv h0, v1.8h"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa8, 0xb0, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "smaxv s0, v1.4s"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa8, 0x31, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sminv b0, v1.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa8, 0x31, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sminv b0, v1.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa8, 0x71, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sminv h0, v1.4h"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa8, 0x71, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sminv h0, v1.8h"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa8, 0xb1, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sminv s0, v1.4s"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa8, 0x30, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "umaxv b0, v1.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa8, 0x30, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "umaxv b0, v1.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa8, 0x70, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "umaxv h0, v1.4h"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa8, 0x70, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "umaxv h0, v1.8h"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa8, 0xb0, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "umaxv s0, v1.4s"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa8, 0x31, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "uminv b0, v1.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa8, 0x31, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "uminv b0, v1.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa8, 0x71, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "uminv h0, v1.4h"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa8, 0x71, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "uminv h0, v1.8h"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa8, 0xb1, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "uminv s0, v1.4s"
+
+  -
+    input:
+      bytes: [ 0x20, 0xb8, 0x31, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "addv b0, v1.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0xb8, 0x31, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "addv b0, v1.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0xb8, 0x71, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "addv h0, v1.4h"
+
+  -
+    input:
+      bytes: [ 0x20, 0xb8, 0x71, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "addv h0, v1.8h"
+
+  -
+    input:
+      bytes: [ 0x20, 0xb8, 0xb1, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "addv s0, v1.4s"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc8, 0x30, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnmv h0, v1.4h"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc8, 0xb0, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnmv h0, v1.4h"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf8, 0x30, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxv h0, v1.4h"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf8, 0xb0, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminv h0, v1.4h"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc8, 0x30, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnmv h0, v1.8h"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc8, 0xb0, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnmv h0, v1.8h"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf8, 0x30, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxv h0, v1.8h"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf8, 0xb0, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminv h0, v1.8h"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc8, 0x30, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnmv s0, v1.4s"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc8, 0xb0, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnmv s0, v1.4s"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf8, 0x30, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxv s0, v1.4s"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf8, 0xb0, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminv s0, v1.4s"
diff --git a/tests/MC/AArch64/neon-add-pairwise.s.yaml b/tests/MC/AArch64/neon-add-pairwise.s.yaml
new file mode 100644
index 000000000..18988c6fb
--- /dev/null
+++ b/tests/MC/AArch64/neon-add-pairwise.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0xbc, 0x22, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "addp v0.8b, v1.8b, v2.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0xbc, 0x22, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "addp v0.16b, v1.16b, v2.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0xbc, 0x62, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "addp v0.4h, v1.4h, v2.4h"
+
+  -
+    input:
+      bytes: [ 0x20, 0xbc, 0x62, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "addp v0.8h, v1.8h, v2.8h"
+
+  -
+    input:
+      bytes: [ 0x20, 0xbc, 0xa2, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "addp v0.2s, v1.2s, v2.2s"
+
+  -
+    input:
+      bytes: [ 0x20, 0xbc, 0xa2, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "addp v0.4s, v1.4s, v2.4s"
+
+  -
+    input:
+      bytes: [ 0x20, 0xbc, 0xe2, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "addp v0.2d, v1.2d, v2.2d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x14, 0x42, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "faddp v0.4h, v1.4h, v2.4h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x14, 0x42, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "faddp v0.8h, v1.8h, v2.8h"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd4, 0x22, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "faddp v0.2s, v1.2s, v2.2s"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd4, 0x22, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "faddp v0.4s, v1.4s, v2.4s"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd4, 0x62, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "faddp v0.2d, v1.2d, v2.2d"
diff --git a/tests/MC/AArch64/neon-add-sub-instructions.s.yaml b/tests/MC/AArch64/neon-add-sub-instructions.s.yaml
new file mode 100644
index 000000000..b90a7f005
--- /dev/null
+++ b/tests/MC/AArch64/neon-add-sub-instructions.s.yaml
@@ -0,0 +1,240 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x84, 0x22, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "add v0.8b, v1.8b, v2.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x84, 0x22, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "add v0.16b, v1.16b, v2.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x84, 0x62, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "add v0.4h, v1.4h, v2.4h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x84, 0x62, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "add v0.8h, v1.8h, v2.8h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x84, 0xa2, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "add v0.2s, v1.2s, v2.2s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x84, 0xa2, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "add v0.4s, v1.4s, v2.4s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x84, 0xe2, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "add v0.2d, v1.2d, v2.2d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x84, 0x22, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub v0.8b, v1.8b, v2.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x84, 0x22, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub v0.16b, v1.16b, v2.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x84, 0x62, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub v0.4h, v1.4h, v2.4h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x84, 0x62, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub v0.8h, v1.8h, v2.8h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x84, 0xa2, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub v0.2s, v1.2s, v2.2s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x84, 0xa2, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub v0.4s, v1.4s, v2.4s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x84, 0xe2, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub v0.2d, v1.2d, v2.2d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x14, 0x42, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd v0.4h, v1.4h, v2.4h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x14, 0x42, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd v0.8h, v1.8h, v2.8h"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd4, 0x22, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd v0.2s, v1.2s, v2.2s"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd4, 0x22, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd v0.4s, v1.4s, v2.4s"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd4, 0x62, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd v0.2d, v1.2d, v2.2d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x14, 0xc2, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub v0.4h, v1.4h, v2.4h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x14, 0xc2, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub v0.8h, v1.8h, v2.8h"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd4, 0xa2, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub v0.2s, v1.2s, v2.2s"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd4, 0xa2, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub v0.4s, v1.4s, v2.4s"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd4, 0xe2, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub v0.2d, v1.2d, v2.2d"
diff --git a/tests/MC/AArch64/neon-bitwise-instructions.s.yaml b/tests/MC/AArch64/neon-bitwise-instructions.s.yaml
new file mode 100644
index 000000000..145c16313
--- /dev/null
+++ b/tests/MC/AArch64/neon-bitwise-instructions.s.yaml
@@ -0,0 +1,160 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x1c, 0x22, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "and v0.8b, v1.8b, v2.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x1c, 0x22, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "and v0.16b, v1.16b, v2.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x1c, 0xa2, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "orr v0.8b, v1.8b, v2.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x1c, 0xa2, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "orr v0.16b, v1.16b, v2.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x1c, 0x22, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "eor v0.8b, v1.8b, v2.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x1c, 0x22, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "eor v0.16b, v1.16b, v2.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x1c, 0xa2, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "bit v0.8b, v1.8b, v2.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x1c, 0xa2, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "bit v0.16b, v1.16b, v2.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x1c, 0xe2, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "bif v0.8b, v1.8b, v2.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x1c, 0xe2, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "bif v0.16b, v1.16b, v2.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x1c, 0x62, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "bsl v0.8b, v1.8b, v2.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x1c, 0x62, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "bsl v0.16b, v1.16b, v2.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x1c, 0xe2, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "orn v0.8b, v1.8b, v2.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x1c, 0xe2, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "orn v0.16b, v1.16b, v2.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x1c, 0x62, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "bic v0.8b, v1.8b, v2.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x1c, 0x62, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "bic v0.16b, v1.16b, v2.16b"
diff --git a/tests/MC/AArch64/neon-compare-instructions.s.yaml b/tests/MC/AArch64/neon-compare-instructions.s.yaml
new file mode 100644
index 000000000..5cc2ae032
--- /dev/null
+++ b/tests/MC/AArch64/neon-compare-instructions.s.yaml
@@ -0,0 +1,1800 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xe0, 0x8d, 0x31, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmeq v0.8b, v15.8b, v17.8b"
+
+  -
+    input:
+      bytes: [ 0xe1, 0x8f, 0x28, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmeq v1.16b, v31.16b, v8.16b"
+
+  -
+    input:
+      bytes: [ 0x0f, 0x8e, 0x71, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmeq v15.4h, v16.4h, v17.4h"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x8c, 0x67, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmeq v5.8h, v6.8h, v7.8h"
+
+  -
+    input:
+      bytes: [ 0x7d, 0x8f, 0xbc, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmeq v29.2s, v27.2s, v28.2s"
+
+  -
+    input:
+      bytes: [ 0xe9, 0x8c, 0xa8, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmeq v9.4s, v7.4s, v8.4s"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x8f, 0xf5, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmeq v3.2d, v31.2d, v21.2d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3d, 0x31, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmhs v0.8b, v15.8b, v17.8b"
+
+  -
+    input:
+      bytes: [ 0xe1, 0x3f, 0x28, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmhs v1.16b, v31.16b, v8.16b"
+
+  -
+    input:
+      bytes: [ 0x0f, 0x3e, 0x71, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmhs v15.4h, v16.4h, v17.4h"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x3c, 0x67, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmhs v5.8h, v6.8h, v7.8h"
+
+  -
+    input:
+      bytes: [ 0x7d, 0x3f, 0xbc, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmhs v29.2s, v27.2s, v28.2s"
+
+  -
+    input:
+      bytes: [ 0xe9, 0x3c, 0xa8, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmhs v9.4s, v7.4s, v8.4s"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x3f, 0xf5, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmhs v3.2d, v31.2d, v21.2d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3d, 0x31, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmhs v0.8b, v15.8b, v17.8b"
+
+  -
+    input:
+      bytes: [ 0xe1, 0x3f, 0x28, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmhs v1.16b, v31.16b, v8.16b"
+
+  -
+    input:
+      bytes: [ 0x0f, 0x3e, 0x71, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmhs v15.4h, v16.4h, v17.4h"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x3c, 0x67, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmhs v5.8h, v6.8h, v7.8h"
+
+  -
+    input:
+      bytes: [ 0x7d, 0x3f, 0xbc, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmhs v29.2s, v27.2s, v28.2s"
+
+  -
+    input:
+      bytes: [ 0xe9, 0x3c, 0xa8, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmhs v9.4s, v7.4s, v8.4s"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x3f, 0xf5, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmhs v3.2d, v31.2d, v21.2d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3d, 0x31, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmge v0.8b, v15.8b, v17.8b"
+
+  -
+    input:
+      bytes: [ 0xe1, 0x3f, 0x28, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmge v1.16b, v31.16b, v8.16b"
+
+  -
+    input:
+      bytes: [ 0x0f, 0x3e, 0x71, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmge v15.4h, v16.4h, v17.4h"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x3c, 0x67, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmge v5.8h, v6.8h, v7.8h"
+
+  -
+    input:
+      bytes: [ 0x7d, 0x3f, 0xbc, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmge v29.2s, v27.2s, v28.2s"
+
+  -
+    input:
+      bytes: [ 0xe9, 0x3c, 0xa8, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmge v9.4s, v7.4s, v8.4s"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x3f, 0xf5, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmge v3.2d, v31.2d, v21.2d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3d, 0x31, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmge v0.8b, v15.8b, v17.8b"
+
+  -
+    input:
+      bytes: [ 0xe1, 0x3f, 0x28, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmge v1.16b, v31.16b, v8.16b"
+
+  -
+    input:
+      bytes: [ 0x0f, 0x3e, 0x71, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmge v15.4h, v16.4h, v17.4h"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x3c, 0x67, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmge v5.8h, v6.8h, v7.8h"
+
+  -
+    input:
+      bytes: [ 0x7d, 0x3f, 0xbc, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmge v29.2s, v27.2s, v28.2s"
+
+  -
+    input:
+      bytes: [ 0xe9, 0x3c, 0xa8, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmge v9.4s, v7.4s, v8.4s"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x3f, 0xf5, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmge v3.2d, v31.2d, v21.2d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x35, 0x31, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmhi v0.8b, v15.8b, v17.8b"
+
+  -
+    input:
+      bytes: [ 0xe1, 0x37, 0x28, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmhi v1.16b, v31.16b, v8.16b"
+
+  -
+    input:
+      bytes: [ 0x0f, 0x36, 0x71, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmhi v15.4h, v16.4h, v17.4h"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x34, 0x67, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmhi v5.8h, v6.8h, v7.8h"
+
+  -
+    input:
+      bytes: [ 0x7d, 0x37, 0xbc, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmhi v29.2s, v27.2s, v28.2s"
+
+  -
+    input:
+      bytes: [ 0xe9, 0x34, 0xa8, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmhi v9.4s, v7.4s, v8.4s"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x37, 0xf5, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmhi v3.2d, v31.2d, v21.2d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x35, 0x31, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmhi v0.8b, v15.8b, v17.8b"
+
+  -
+    input:
+      bytes: [ 0xe1, 0x37, 0x28, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmhi v1.16b, v31.16b, v8.16b"
+
+  -
+    input:
+      bytes: [ 0x0f, 0x36, 0x71, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmhi v15.4h, v16.4h, v17.4h"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x34, 0x67, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmhi v5.8h, v6.8h, v7.8h"
+
+  -
+    input:
+      bytes: [ 0x7d, 0x37, 0xbc, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmhi v29.2s, v27.2s, v28.2s"
+
+  -
+    input:
+      bytes: [ 0xe9, 0x34, 0xa8, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmhi v9.4s, v7.4s, v8.4s"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x37, 0xf5, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmhi v3.2d, v31.2d, v21.2d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x35, 0x31, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmgt v0.8b, v15.8b, v17.8b"
+
+  -
+    input:
+      bytes: [ 0xe1, 0x37, 0x28, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmgt v1.16b, v31.16b, v8.16b"
+
+  -
+    input:
+      bytes: [ 0x0f, 0x36, 0x71, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmgt v15.4h, v16.4h, v17.4h"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x34, 0x67, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmgt v5.8h, v6.8h, v7.8h"
+
+  -
+    input:
+      bytes: [ 0x7d, 0x37, 0xbc, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmgt v29.2s, v27.2s, v28.2s"
+
+  -
+    input:
+      bytes: [ 0xe9, 0x34, 0xa8, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmgt v9.4s, v7.4s, v8.4s"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x37, 0xf5, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmgt v3.2d, v31.2d, v21.2d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x35, 0x31, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmgt v0.8b, v15.8b, v17.8b"
+
+  -
+    input:
+      bytes: [ 0xe1, 0x37, 0x28, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmgt v1.16b, v31.16b, v8.16b"
+
+  -
+    input:
+      bytes: [ 0x0f, 0x36, 0x71, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmgt v15.4h, v16.4h, v17.4h"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x34, 0x67, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmgt v5.8h, v6.8h, v7.8h"
+
+  -
+    input:
+      bytes: [ 0x7d, 0x37, 0xbc, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmgt v29.2s, v27.2s, v28.2s"
+
+  -
+    input:
+      bytes: [ 0xe9, 0x34, 0xa8, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmgt v9.4s, v7.4s, v8.4s"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x37, 0xf5, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmgt v3.2d, v31.2d, v21.2d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x8d, 0x31, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmtst v0.8b, v15.8b, v17.8b"
+
+  -
+    input:
+      bytes: [ 0xe1, 0x8f, 0x28, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmtst v1.16b, v31.16b, v8.16b"
+
+  -
+    input:
+      bytes: [ 0x0f, 0x8e, 0x71, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmtst v15.4h, v16.4h, v17.4h"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x8c, 0x67, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmtst v5.8h, v6.8h, v7.8h"
+
+  -
+    input:
+      bytes: [ 0x7d, 0x8f, 0xbc, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmtst v29.2s, v27.2s, v28.2s"
+
+  -
+    input:
+      bytes: [ 0xe9, 0x8c, 0xa8, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmtst v9.4s, v7.4s, v8.4s"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x8f, 0xf5, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmtst v3.2d, v31.2d, v21.2d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x27, 0x50, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmeq v0.4h, v31.4h, v16.4h"
+
+  -
+    input:
+      bytes: [ 0xe4, 0x24, 0x4f, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmeq v4.8h, v7.8h, v15.8h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xe7, 0x30, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmeq v0.2s, v31.2s, v16.2s"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xe4, 0x2f, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmeq v4.4s, v7.4s, v15.4s"
+
+  -
+    input:
+      bytes: [ 0x5d, 0xe4, 0x65, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmeq v29.2d, v2.2d, v5.2d"
+
+  -
+    input:
+      bytes: [ 0x03, 0x25, 0x4c, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmge v3.4h, v8.4h, v12.4h"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x27, 0x5c, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmge v31.8h, v29.8h, v28.8h"
+
+  -
+    input:
+      bytes: [ 0x03, 0x25, 0x4c, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmge v3.4h, v8.4h, v12.4h"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x27, 0x5c, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmge v31.8h, v29.8h, v28.8h"
+
+  -
+    input:
+      bytes: [ 0xbf, 0xe7, 0x3c, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmge v31.4s, v29.4s, v28.4s"
+
+  -
+    input:
+      bytes: [ 0x03, 0xe5, 0x2c, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmge v3.2s, v8.2s, v12.2s"
+
+  -
+    input:
+      bytes: [ 0xf1, 0xe5, 0x6d, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmge v17.2d, v15.2d, v13.2d"
+
+  -
+    input:
+      bytes: [ 0xbf, 0xe7, 0x3c, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmge v31.4s, v29.4s, v28.4s"
+
+  -
+    input:
+      bytes: [ 0x03, 0xe5, 0x2c, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmge v3.2s, v8.2s, v12.2s"
+
+  -
+    input:
+      bytes: [ 0xf1, 0xe5, 0x6d, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmge v17.2d, v15.2d, v13.2d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x27, 0xd0, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmgt v0.4h, v31.4h, v16.4h"
+
+  -
+    input:
+      bytes: [ 0xe4, 0x24, 0xcf, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmgt v4.8h, v7.8h, v15.8h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x27, 0xd0, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmgt v0.4h, v31.4h, v16.4h"
+
+  -
+    input:
+      bytes: [ 0xe4, 0x24, 0xcf, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmgt v4.8h, v7.8h, v15.8h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xe7, 0xb0, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmgt v0.2s, v31.2s, v16.2s"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xe4, 0xaf, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmgt v4.4s, v7.4s, v15.4s"
+
+  -
+    input:
+      bytes: [ 0x5d, 0xe4, 0xe5, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmgt v29.2d, v2.2d, v5.2d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xe7, 0xb0, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmgt v0.2s, v31.2s, v16.2s"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xe4, 0xaf, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmgt v4.4s, v7.4s, v15.4s"
+
+  -
+    input:
+      bytes: [ 0x5d, 0xe4, 0xe5, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmgt v29.2d, v2.2d, v5.2d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x99, 0x20, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmeq v0.8b, v15.8b, #0"
+
+  -
+    input:
+      bytes: [ 0xe1, 0x9b, 0x20, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmeq v1.16b, v31.16b, #0"
+
+  -
+    input:
+      bytes: [ 0x0f, 0x9a, 0x60, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmeq v15.4h, v16.4h, #0"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x98, 0x60, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmeq v5.8h, v6.8h, #0"
+
+  -
+    input:
+      bytes: [ 0x7d, 0x9b, 0xa0, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmeq v29.2s, v27.2s, #0"
+
+  -
+    input:
+      bytes: [ 0xe9, 0x98, 0xa0, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmeq v9.4s, v7.4s, #0"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x9b, 0xe0, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmeq v3.2d, v31.2d, #0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x89, 0x20, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmge v0.8b, v15.8b, #0"
+
+  -
+    input:
+      bytes: [ 0xe1, 0x8b, 0x20, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmge v1.16b, v31.16b, #0"
+
+  -
+    input:
+      bytes: [ 0x0f, 0x8a, 0x60, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmge v15.4h, v16.4h, #0"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x88, 0x60, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmge v5.8h, v6.8h, #0"
+
+  -
+    input:
+      bytes: [ 0x7d, 0x8b, 0xa0, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmge v29.2s, v27.2s, #0"
+
+  -
+    input:
+      bytes: [ 0x91, 0x8a, 0xa0, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmge v17.4s, v20.4s, #0"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x8b, 0xe0, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmge v3.2d, v31.2d, #0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x89, 0x20, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmgt v0.8b, v15.8b, #0"
+
+  -
+    input:
+      bytes: [ 0xe1, 0x8b, 0x20, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmgt v1.16b, v31.16b, #0"
+
+  -
+    input:
+      bytes: [ 0x0f, 0x8a, 0x60, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmgt v15.4h, v16.4h, #0"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x88, 0x60, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmgt v5.8h, v6.8h, #0"
+
+  -
+    input:
+      bytes: [ 0x7d, 0x8b, 0xa0, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmgt v29.2s, v27.2s, #0"
+
+  -
+    input:
+      bytes: [ 0xe9, 0x88, 0xa0, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmgt v9.4s, v7.4s, #0"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x8b, 0xe0, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmgt v3.2d, v31.2d, #0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x99, 0x20, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmle v0.8b, v15.8b, #0"
+
+  -
+    input:
+      bytes: [ 0xe1, 0x9b, 0x20, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmle v1.16b, v31.16b, #0"
+
+  -
+    input:
+      bytes: [ 0x0f, 0x9a, 0x60, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmle v15.4h, v16.4h, #0"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x98, 0x60, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmle v5.8h, v6.8h, #0"
+
+  -
+    input:
+      bytes: [ 0x7d, 0x9b, 0xa0, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmle v29.2s, v27.2s, #0"
+
+  -
+    input:
+      bytes: [ 0xe9, 0x98, 0xa0, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmle v9.4s, v7.4s, #0"
+
+  -
+    input:
+      bytes: [ 0xe3, 0x9b, 0xe0, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmle v3.2d, v31.2d, #0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xa9, 0x20, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmlt v0.8b, v15.8b, #0"
+
+  -
+    input:
+      bytes: [ 0xe1, 0xab, 0x20, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmlt v1.16b, v31.16b, #0"
+
+  -
+    input:
+      bytes: [ 0x0f, 0xaa, 0x60, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmlt v15.4h, v16.4h, #0"
+
+  -
+    input:
+      bytes: [ 0xc5, 0xa8, 0x60, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmlt v5.8h, v6.8h, #0"
+
+  -
+    input:
+      bytes: [ 0x7d, 0xab, 0xa0, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmlt v29.2s, v27.2s, #0"
+
+  -
+    input:
+      bytes: [ 0xe9, 0xa8, 0xa0, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmlt v9.4s, v7.4s, #0"
+
+  -
+    input:
+      bytes: [ 0xe3, 0xab, 0xe0, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmlt v3.2d, v31.2d, #0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xdb, 0xf8, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmeq v0.4h, v31.4h, #0.0"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xd8, 0xf8, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmeq v4.8h, v7.8h, #0.0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xdb, 0xa0, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmeq v0.2s, v31.2s, #0.0"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xd8, 0xa0, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmeq v4.4s, v7.4s, #0.0"
+
+  -
+    input:
+      bytes: [ 0x5d, 0xd8, 0xe0, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmeq v29.2d, v2.2d, #0.0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xdb, 0xf8, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmeq v0.4h, v31.4h, #0.0"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xd8, 0xf8, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmeq v4.8h, v7.8h, #0.0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xdb, 0xa0, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmeq v0.2s, v31.2s, #0.0"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xd8, 0xa0, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmeq v4.4s, v7.4s, #0.0"
+
+  -
+    input:
+      bytes: [ 0x5d, 0xd8, 0xe0, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmeq v29.2d, v2.2d, #0.0"
+
+  -
+    input:
+      bytes: [ 0x03, 0xc9, 0xf8, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmge v3.4h, v8.4h, #0.0"
+
+  -
+    input:
+      bytes: [ 0xbf, 0xcb, 0xf8, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmge v31.8h, v29.8h, #0.0"
+
+  -
+    input:
+      bytes: [ 0xbf, 0xcb, 0xa0, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmge v31.4s, v29.4s, #0.0"
+
+  -
+    input:
+      bytes: [ 0x03, 0xc9, 0xa0, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmge v3.2s, v8.2s, #0.0"
+
+  -
+    input:
+      bytes: [ 0xf1, 0xc9, 0xe0, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmge v17.2d, v15.2d, #0.0"
+
+  -
+    input:
+      bytes: [ 0x03, 0xc9, 0xf8, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmge v3.4h, v8.4h, #0.0"
+
+  -
+    input:
+      bytes: [ 0xbf, 0xcb, 0xf8, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmge v31.8h, v29.8h, #0.0"
+
+  -
+    input:
+      bytes: [ 0xbf, 0xcb, 0xa0, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmge v31.4s, v29.4s, #0.0"
+
+  -
+    input:
+      bytes: [ 0x03, 0xc9, 0xa0, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmge v3.2s, v8.2s, #0.0"
+
+  -
+    input:
+      bytes: [ 0xf1, 0xc9, 0xe0, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmge v17.2d, v15.2d, #0.0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xcb, 0xf8, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmgt v0.4h, v31.4h, #0.0"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xc8, 0xf8, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmgt v4.8h, v7.8h, #0.0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xcb, 0xa0, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmgt v0.2s, v31.2s, #0.0"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xc8, 0xa0, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmgt v4.4s, v7.4s, #0.0"
+
+  -
+    input:
+      bytes: [ 0x5d, 0xc8, 0xe0, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmgt v29.2d, v2.2d, #0.0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xcb, 0xf8, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmgt v0.4h, v31.4h, #0.0"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xc8, 0xf8, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmgt v4.8h, v7.8h, #0.0"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xcb, 0xa0, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmgt v0.2s, v31.2s, #0.0"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xc8, 0xa0, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmgt v4.4s, v7.4s, #0.0"
+
+  -
+    input:
+      bytes: [ 0x5d, 0xc8, 0xe0, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmgt v29.2d, v2.2d, #0.0"
+
+  -
+    input:
+      bytes: [ 0x83, 0xda, 0xf8, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmle v3.4h, v20.4h, #0.0"
+
+  -
+    input:
+      bytes: [ 0x01, 0xd9, 0xf8, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmle v1.8h, v8.8h, #0.0"
+
+  -
+    input:
+      bytes: [ 0x01, 0xd9, 0xa0, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmle v1.4s, v8.4s, #0.0"
+
+  -
+    input:
+      bytes: [ 0x83, 0xda, 0xa0, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmle v3.2s, v20.2s, #0.0"
+
+  -
+    input:
+      bytes: [ 0xa7, 0xd9, 0xe0, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmle v7.2d, v13.2d, #0.0"
+
+  -
+    input:
+      bytes: [ 0x83, 0xda, 0xf8, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmle v3.4h, v20.4h, #0.0"
+
+  -
+    input:
+      bytes: [ 0x01, 0xd9, 0xf8, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmle v1.8h, v8.8h, #0.0"
+
+  -
+    input:
+      bytes: [ 0x01, 0xd9, 0xa0, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmle v1.4s, v8.4s, #0.0"
+
+  -
+    input:
+      bytes: [ 0x83, 0xda, 0xa0, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmle v3.2s, v20.2s, #0.0"
+
+  -
+    input:
+      bytes: [ 0xa7, 0xd9, 0xe0, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmle v7.2d, v13.2d, #0.0"
+
+  -
+    input:
+      bytes: [ 0x50, 0xe8, 0xf8, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmlt v16.4h, v2.4h, #0.0"
+
+  -
+    input:
+      bytes: [ 0x8f, 0xe8, 0xf8, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmlt v15.8h, v4.8h, #0.0"
+
+  -
+    input:
+      bytes: [ 0x50, 0xe8, 0xa0, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmlt v16.2s, v2.2s, #0.0"
+
+  -
+    input:
+      bytes: [ 0x8f, 0xe8, 0xa0, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmlt v15.4s, v4.4s, #0.0"
+
+  -
+    input:
+      bytes: [ 0xa5, 0xeb, 0xe0, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmlt v5.2d, v29.2d, #0.0"
+
+  -
+    input:
+      bytes: [ 0x50, 0xe8, 0xf8, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmlt v16.4h, v2.4h, #0.0"
+
+  -
+    input:
+      bytes: [ 0x8f, 0xe8, 0xf8, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmlt v15.8h, v4.8h, #0.0"
+
+  -
+    input:
+      bytes: [ 0x50, 0xe8, 0xa0, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmlt v16.2s, v2.2s, #0.0"
+
+  -
+    input:
+      bytes: [ 0x8f, 0xe8, 0xa0, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmlt v15.4s, v4.4s, #0.0"
+
+  -
+    input:
+      bytes: [ 0xa5, 0xeb, 0xe0, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmlt v5.2d, v29.2d, #0.0"
diff --git a/tests/MC/AArch64/neon-crypto.s.yaml b/tests/MC/AArch64/neon-crypto.s.yaml
new file mode 100644
index 000000000..421882ae6
--- /dev/null
+++ b/tests/MC/AArch64/neon-crypto.s.yaml
@@ -0,0 +1,140 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x48, 0x28, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "crypto" ]
+    expected:
+      insns:
+        -
+          asm_text: "aese v0.16b, v1.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x58, 0x28, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "crypto" ]
+    expected:
+      insns:
+        -
+          asm_text: "aesd v0.16b, v1.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x68, 0x28, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "crypto" ]
+    expected:
+      insns:
+        -
+          asm_text: "aesmc v0.16b, v1.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x78, 0x28, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "crypto" ]
+    expected:
+      insns:
+        -
+          asm_text: "aesimc v0.16b, v1.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x08, 0x28, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "crypto" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha1h s0, s1"
+
+  -
+    input:
+      bytes: [ 0x20, 0x18, 0x28, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "crypto" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha1su1 v0.4s, v1.4s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x28, 0x28, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "crypto" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha256su0 v0.4s, v1.4s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x00, 0x02, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "crypto" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha1c q0, s1, v2.4s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x10, 0x02, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "crypto" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha1p q0, s1, v2.4s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x20, 0x02, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "crypto" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha1m q0, s1, v2.4s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x30, 0x02, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "crypto" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha1su0 v0.4s, v1.4s, v2.4s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x40, 0x02, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "crypto" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha256h q0, q1, v2.4s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x50, 0x02, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "crypto" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha256h2 q0, q1, v2.4s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x60, 0x02, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "crypto" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha256su1 v0.4s, v1.4s, v2.4s"
diff --git a/tests/MC/AArch64/neon-extract.s.yaml b/tests/MC/AArch64/neon-extract.s.yaml
new file mode 100644
index 000000000..bbf8c4b49
--- /dev/null
+++ b/tests/MC/AArch64/neon-extract.s.yaml
@@ -0,0 +1,20 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x18, 0x02, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ext v0.8b, v1.8b, v2.8b, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x18, 0x02, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ext v0.16b, v1.16b, v2.16b, #3"
diff --git a/tests/MC/AArch64/neon-facge-facgt.s.yaml b/tests/MC/AArch64/neon-facge-facgt.s.yaml
new file mode 100644
index 000000000..465335f8f
--- /dev/null
+++ b/tests/MC/AArch64/neon-facge-facgt.s.yaml
@@ -0,0 +1,200 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xe0, 0x2f, 0x50, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "facge v0.4h, v31.4h, v16.4h"
+
+  -
+    input:
+      bytes: [ 0xe4, 0x2c, 0x4f, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "facge v4.8h, v7.8h, v15.8h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xef, 0x30, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "facge v0.2s, v31.2s, v16.2s"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xec, 0x2f, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "facge v4.4s, v7.4s, v15.4s"
+
+  -
+    input:
+      bytes: [ 0x5d, 0xec, 0x65, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "facge v29.2d, v2.2d, v5.2d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x2f, 0x50, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "facge v0.4h, v31.4h, v16.4h"
+
+  -
+    input:
+      bytes: [ 0xe4, 0x2c, 0x4f, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "facge v4.8h, v7.8h, v15.8h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xef, 0x30, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "facge v0.2s, v31.2s, v16.2s"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xec, 0x2f, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "facge v4.4s, v7.4s, v15.4s"
+
+  -
+    input:
+      bytes: [ 0x5d, 0xec, 0x65, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "facge v29.2d, v2.2d, v5.2d"
+
+  -
+    input:
+      bytes: [ 0x03, 0x2d, 0xcc, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "facgt v3.4h, v8.4h, v12.4h"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x2f, 0xdc, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "facgt v31.8h, v29.8h, v28.8h"
+
+  -
+    input:
+      bytes: [ 0xbf, 0xef, 0xbc, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "facgt v31.4s, v29.4s, v28.4s"
+
+  -
+    input:
+      bytes: [ 0x03, 0xed, 0xac, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "facgt v3.2s, v8.2s, v12.2s"
+
+  -
+    input:
+      bytes: [ 0xf1, 0xed, 0xed, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "facgt v17.2d, v15.2d, v13.2d"
+
+  -
+    input:
+      bytes: [ 0x03, 0x2d, 0xcc, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "facgt v3.4h, v8.4h, v12.4h"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x2f, 0xdc, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "facgt v31.8h, v29.8h, v28.8h"
+
+  -
+    input:
+      bytes: [ 0xbf, 0xef, 0xbc, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "facgt v31.4s, v29.4s, v28.4s"
+
+  -
+    input:
+      bytes: [ 0x03, 0xed, 0xac, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "facgt v3.2s, v8.2s, v12.2s"
+
+  -
+    input:
+      bytes: [ 0xf1, 0xed, 0xed, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "facgt v17.2d, v15.2d, v13.2d"
diff --git a/tests/MC/AArch64/neon-frsqrt-frecp.s.yaml b/tests/MC/AArch64/neon-frsqrt-frecp.s.yaml
new file mode 100644
index 000000000..45e36b5f7
--- /dev/null
+++ b/tests/MC/AArch64/neon-frsqrt-frecp.s.yaml
@@ -0,0 +1,100 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xe0, 0x3f, 0xd0, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "frsqrts v0.4h, v31.4h, v16.4h"
+
+  -
+    input:
+      bytes: [ 0xe4, 0x3c, 0xcf, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "frsqrts v4.8h, v7.8h, v15.8h"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xff, 0xb0, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "frsqrts v0.2s, v31.2s, v16.2s"
+
+  -
+    input:
+      bytes: [ 0xe4, 0xfc, 0xaf, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "frsqrts v4.4s, v7.4s, v15.4s"
+
+  -
+    input:
+      bytes: [ 0x5d, 0xfc, 0xe5, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "frsqrts v29.2d, v2.2d, v5.2d"
+
+  -
+    input:
+      bytes: [ 0x03, 0x3d, 0x4c, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "frecps v3.4h, v8.4h, v12.4h"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x3f, 0x5c, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "frecps v31.8h, v29.8h, v28.8h"
+
+  -
+    input:
+      bytes: [ 0xbf, 0xff, 0x3c, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "frecps v31.4s, v29.4s, v28.4s"
+
+  -
+    input:
+      bytes: [ 0x03, 0xfd, 0x2c, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "frecps v3.2s, v8.2s, v12.2s"
+
+  -
+    input:
+      bytes: [ 0xf1, 0xfd, 0x6d, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "frecps v17.2d, v15.2d, v13.2d"
diff --git a/tests/MC/AArch64/neon-halving-add-sub.s.yaml b/tests/MC/AArch64/neon-halving-add-sub.s.yaml
new file mode 100644
index 000000000..1cfe9cf6b
--- /dev/null
+++ b/tests/MC/AArch64/neon-halving-add-sub.s.yaml
@@ -0,0 +1,240 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x04, 0x22, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "shadd v0.8b, v1.8b, v2.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x04, 0x22, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "shadd v0.16b, v1.16b, v2.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x04, 0x62, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "shadd v0.4h, v1.4h, v2.4h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x04, 0x62, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "shadd v0.8h, v1.8h, v2.8h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x04, 0xa2, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "shadd v0.2s, v1.2s, v2.2s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x04, 0xa2, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "shadd v0.4s, v1.4s, v2.4s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x04, 0x22, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "uhadd v0.8b, v1.8b, v2.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x04, 0x22, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "uhadd v0.16b, v1.16b, v2.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x04, 0x62, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "uhadd v0.4h, v1.4h, v2.4h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x04, 0x62, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "uhadd v0.8h, v1.8h, v2.8h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x04, 0xa2, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "uhadd v0.2s, v1.2s, v2.2s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x04, 0xa2, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "uhadd v0.4s, v1.4s, v2.4s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x24, 0x22, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "shsub v0.8b, v1.8b, v2.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x24, 0x22, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "shsub v0.16b, v1.16b, v2.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x24, 0x62, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "shsub v0.4h, v1.4h, v2.4h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x24, 0x62, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "shsub v0.8h, v1.8h, v2.8h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x24, 0xa2, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "shsub v0.2s, v1.2s, v2.2s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x24, 0xa2, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "shsub v0.4s, v1.4s, v2.4s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x24, 0x22, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "uhsub v0.8b, v1.8b, v2.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x24, 0x22, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "uhsub v0.16b, v1.16b, v2.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x24, 0x62, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "uhsub v0.4h, v1.4h, v2.4h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x24, 0x62, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "uhsub v0.8h, v1.8h, v2.8h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x24, 0xa2, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "uhsub v0.2s, v1.2s, v2.2s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x24, 0xa2, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "uhsub v0.4s, v1.4s, v2.4s"
diff --git a/tests/MC/AArch64/neon-max-min-pairwise.s.yaml b/tests/MC/AArch64/neon-max-min-pairwise.s.yaml
new file mode 100644
index 000000000..768467ddd
--- /dev/null
+++ b/tests/MC/AArch64/neon-max-min-pairwise.s.yaml
@@ -0,0 +1,440 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0xa4, 0x22, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "smaxp v0.8b, v1.8b, v2.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa4, 0x22, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "smaxp v0.16b, v1.16b, v2.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa4, 0x62, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "smaxp v0.4h, v1.4h, v2.4h"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa4, 0x62, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "smaxp v0.8h, v1.8h, v2.8h"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa4, 0xa2, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "smaxp v0.2s, v1.2s, v2.2s"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa4, 0xa2, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "smaxp v0.4s, v1.4s, v2.4s"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa4, 0x22, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "umaxp v0.8b, v1.8b, v2.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa4, 0x22, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "umaxp v0.16b, v1.16b, v2.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa4, 0x62, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "umaxp v0.4h, v1.4h, v2.4h"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa4, 0x62, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "umaxp v0.8h, v1.8h, v2.8h"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa4, 0xa2, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "umaxp v0.2s, v1.2s, v2.2s"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa4, 0xa2, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "umaxp v0.4s, v1.4s, v2.4s"
+
+  -
+    input:
+      bytes: [ 0x20, 0xac, 0x22, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sminp v0.8b, v1.8b, v2.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0xac, 0x22, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sminp v0.16b, v1.16b, v2.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0xac, 0x62, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sminp v0.4h, v1.4h, v2.4h"
+
+  -
+    input:
+      bytes: [ 0x20, 0xac, 0x62, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sminp v0.8h, v1.8h, v2.8h"
+
+  -
+    input:
+      bytes: [ 0x20, 0xac, 0xa2, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sminp v0.2s, v1.2s, v2.2s"
+
+  -
+    input:
+      bytes: [ 0x20, 0xac, 0xa2, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sminp v0.4s, v1.4s, v2.4s"
+
+  -
+    input:
+      bytes: [ 0x20, 0xac, 0x22, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "uminp v0.8b, v1.8b, v2.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0xac, 0x22, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "uminp v0.16b, v1.16b, v2.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0xac, 0x62, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "uminp v0.4h, v1.4h, v2.4h"
+
+  -
+    input:
+      bytes: [ 0x20, 0xac, 0x62, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "uminp v0.8h, v1.8h, v2.8h"
+
+  -
+    input:
+      bytes: [ 0x20, 0xac, 0xa2, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "uminp v0.2s, v1.2s, v2.2s"
+
+  -
+    input:
+      bytes: [ 0x20, 0xac, 0xa2, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "uminp v0.4s, v1.4s, v2.4s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x34, 0x42, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxp v0.4h, v1.4h, v2.4h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x35, 0x50, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxp v31.8h, v15.8h, v16.8h"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf4, 0x22, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxp v0.2s, v1.2s, v2.2s"
+
+  -
+    input:
+      bytes: [ 0xff, 0xf5, 0x30, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxp v31.4s, v15.4s, v16.4s"
+
+  -
+    input:
+      bytes: [ 0x07, 0xf5, 0x79, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxp v7.2d, v8.2d, v25.2d"
+
+  -
+    input:
+      bytes: [ 0xea, 0x35, 0xd6, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminp v10.4h, v15.4h, v22.4h"
+
+  -
+    input:
+      bytes: [ 0xa3, 0x34, 0xc6, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminp v3.8h, v5.8h, v6.8h"
+
+  -
+    input:
+      bytes: [ 0xea, 0xf5, 0xb6, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminp v10.2s, v15.2s, v22.2s"
+
+  -
+    input:
+      bytes: [ 0xa3, 0xf4, 0xa6, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminp v3.4s, v5.4s, v6.4s"
+
+  -
+    input:
+      bytes: [ 0xb1, 0xf5, 0xe2, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminp v17.2d, v13.2d, v2.2d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x04, 0x42, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnmp v0.4h, v1.4h, v2.4h"
+
+  -
+    input:
+      bytes: [ 0xff, 0x05, 0x50, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnmp v31.8h, v15.8h, v16.8h"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc4, 0x22, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnmp v0.2s, v1.2s, v2.2s"
+
+  -
+    input:
+      bytes: [ 0xff, 0xc5, 0x30, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnmp v31.4s, v15.4s, v16.4s"
+
+  -
+    input:
+      bytes: [ 0x07, 0xc5, 0x79, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnmp v7.2d, v8.2d, v25.2d"
+
+  -
+    input:
+      bytes: [ 0xea, 0x05, 0xd6, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnmp v10.4h, v15.4h, v22.4h"
+
+  -
+    input:
+      bytes: [ 0xa3, 0x04, 0xc6, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnmp v3.8h, v5.8h, v6.8h"
+
+  -
+    input:
+      bytes: [ 0xea, 0xc5, 0xb6, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnmp v10.2s, v15.2s, v22.2s"
+
+  -
+    input:
+      bytes: [ 0xa3, 0xc4, 0xa6, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnmp v3.4s, v5.4s, v6.4s"
+
+  -
+    input:
+      bytes: [ 0xb1, 0xc5, 0xe2, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnmp v17.2d, v13.2d, v2.2d"
diff --git a/tests/MC/AArch64/neon-max-min.s.yaml b/tests/MC/AArch64/neon-max-min.s.yaml
new file mode 100644
index 000000000..a7b373ca0
--- /dev/null
+++ b/tests/MC/AArch64/neon-max-min.s.yaml
@@ -0,0 +1,440 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x64, 0x22, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax v0.8b, v1.8b, v2.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x64, 0x22, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax v0.16b, v1.16b, v2.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x64, 0x62, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax v0.4h, v1.4h, v2.4h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x64, 0x62, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax v0.8h, v1.8h, v2.8h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x64, 0xa2, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax v0.2s, v1.2s, v2.2s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x64, 0xa2, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "smax v0.4s, v1.4s, v2.4s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x64, 0x22, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax v0.8b, v1.8b, v2.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x64, 0x22, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax v0.16b, v1.16b, v2.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x64, 0x62, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax v0.4h, v1.4h, v2.4h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x64, 0x62, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax v0.8h, v1.8h, v2.8h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x64, 0xa2, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax v0.2s, v1.2s, v2.2s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x64, 0xa2, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "umax v0.4s, v1.4s, v2.4s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x6c, 0x22, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin v0.8b, v1.8b, v2.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x6c, 0x22, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin v0.16b, v1.16b, v2.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x6c, 0x62, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin v0.4h, v1.4h, v2.4h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x6c, 0x62, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin v0.8h, v1.8h, v2.8h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x6c, 0xa2, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin v0.2s, v1.2s, v2.2s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x6c, 0xa2, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "smin v0.4s, v1.4s, v2.4s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x6c, 0x22, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin v0.8b, v1.8b, v2.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x6c, 0x22, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin v0.16b, v1.16b, v2.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x6c, 0x62, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin v0.4h, v1.4h, v2.4h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x6c, 0x62, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin v0.8h, v1.8h, v2.8h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x6c, 0xa2, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin v0.2s, v1.2s, v2.2s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x6c, 0xa2, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "umin v0.4s, v1.4s, v2.4s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x34, 0x42, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmax v0.4h, v1.4h, v2.4h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x34, 0x42, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmax v0.8h, v1.8h, v2.8h"
+
+  -
+    input:
+      bytes: [ 0x20, 0xf4, 0x22, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmax v0.2s, v1.2s, v2.2s"
+
+  -
+    input:
+      bytes: [ 0xff, 0xf5, 0x30, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmax v31.4s, v15.4s, v16.4s"
+
+  -
+    input:
+      bytes: [ 0x07, 0xf5, 0x79, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmax v7.2d, v8.2d, v25.2d"
+
+  -
+    input:
+      bytes: [ 0xea, 0x35, 0xd6, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmin v10.4h, v15.4h, v22.4h"
+
+  -
+    input:
+      bytes: [ 0xea, 0x35, 0xd6, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmin v10.8h, v15.8h, v22.8h"
+
+  -
+    input:
+      bytes: [ 0xea, 0xf5, 0xb6, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmin v10.2s, v15.2s, v22.2s"
+
+  -
+    input:
+      bytes: [ 0xa3, 0xf4, 0xa6, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmin v3.4s, v5.4s, v6.4s"
+
+  -
+    input:
+      bytes: [ 0xb1, 0xf5, 0xe2, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmin v17.2d, v13.2d, v2.2d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x04, 0x42, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnm v0.4h, v1.4h, v2.4h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x04, 0x42, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnm v0.8h, v1.8h, v2.8h"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc4, 0x22, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnm v0.2s, v1.2s, v2.2s"
+
+  -
+    input:
+      bytes: [ 0xff, 0xc5, 0x30, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnm v31.4s, v15.4s, v16.4s"
+
+  -
+    input:
+      bytes: [ 0x07, 0xc5, 0x79, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxnm v7.2d, v8.2d, v25.2d"
+
+  -
+    input:
+      bytes: [ 0xea, 0x05, 0xd6, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnm v10.4h, v15.4h, v22.4h"
+
+  -
+    input:
+      bytes: [ 0xea, 0x05, 0xd6, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnm v10.8h, v15.8h, v22.8h"
+
+  -
+    input:
+      bytes: [ 0xea, 0xc5, 0xb6, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnm v10.2s, v15.2s, v22.2s"
+
+  -
+    input:
+      bytes: [ 0xa3, 0xc4, 0xa6, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnm v3.4s, v5.4s, v6.4s"
+
+  -
+    input:
+      bytes: [ 0xb1, 0xc5, 0xe2, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fminnm v17.2d, v13.2d, v2.2d"
diff --git a/tests/MC/AArch64/neon-mla-mls-instructions.s.yaml b/tests/MC/AArch64/neon-mla-mls-instructions.s.yaml
new file mode 100644
index 000000000..647c1e4d0
--- /dev/null
+++ b/tests/MC/AArch64/neon-mla-mls-instructions.s.yaml
@@ -0,0 +1,220 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x94, 0x22, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "mla v0.8b, v1.8b, v2.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x94, 0x22, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "mla v0.16b, v1.16b, v2.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x94, 0x62, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "mla v0.4h, v1.4h, v2.4h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x94, 0x62, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "mla v0.8h, v1.8h, v2.8h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x94, 0xa2, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "mla v0.2s, v1.2s, v2.2s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x94, 0xa2, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "mla v0.4s, v1.4s, v2.4s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x94, 0x22, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "mls v0.8b, v1.8b, v2.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x94, 0x22, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "mls v0.16b, v1.16b, v2.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x94, 0x62, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "mls v0.4h, v1.4h, v2.4h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x94, 0x62, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "mls v0.8h, v1.8h, v2.8h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x94, 0xa2, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "mls v0.2s, v1.2s, v2.2s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x94, 0xa2, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "mls v0.4s, v1.4s, v2.4s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x0c, 0x42, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla v0.4h, v1.4h, v2.4h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x0c, 0x42, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla v0.8h, v1.8h, v2.8h"
+
+  -
+    input:
+      bytes: [ 0x20, 0xcc, 0x22, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla v0.2s, v1.2s, v2.2s"
+
+  -
+    input:
+      bytes: [ 0x20, 0xcc, 0x22, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla v0.4s, v1.4s, v2.4s"
+
+  -
+    input:
+      bytes: [ 0x20, 0xcc, 0x62, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla v0.2d, v1.2d, v2.2d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x0c, 0xc2, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls v0.4h, v1.4h, v2.4h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x0c, 0xc2, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls v0.8h, v1.8h, v2.8h"
+
+  -
+    input:
+      bytes: [ 0x20, 0xcc, 0xa2, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls v0.2s, v1.2s, v2.2s"
+
+  -
+    input:
+      bytes: [ 0x20, 0xcc, 0xa2, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls v0.4s, v1.4s, v2.4s"
+
+  -
+    input:
+      bytes: [ 0x20, 0xcc, 0xe2, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls v0.2d, v1.2d, v2.2d"
diff --git a/tests/MC/AArch64/neon-mov.s.yaml b/tests/MC/AArch64/neon-mov.s.yaml
new file mode 100644
index 000000000..5bb1c9b41
--- /dev/null
+++ b/tests/MC/AArch64/neon-mov.s.yaml
@@ -0,0 +1,730 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x04, 0x00, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "movi v0.2s, #1"
+
+  -
+    input:
+      bytes: [ 0x01, 0x04, 0x00, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "movi v1.2s, #0"
+
+  -
+    input:
+      bytes: [ 0x2f, 0x24, 0x00, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "movi v15.2s, #1, lsl #8"
+
+  -
+    input:
+      bytes: [ 0x30, 0x44, 0x00, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "movi v16.2s, #1, lsl #16"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x64, 0x00, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "movi v31.2s, #1, lsl #24"
+
+  -
+    input:
+      bytes: [ 0x20, 0x04, 0x00, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "movi v0.4s, #1"
+
+  -
+    input:
+      bytes: [ 0x20, 0x24, 0x00, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "movi v0.4s, #1, lsl #8"
+
+  -
+    input:
+      bytes: [ 0x20, 0x44, 0x00, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "movi v0.4s, #1, lsl #16"
+
+  -
+    input:
+      bytes: [ 0x20, 0x64, 0x00, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "movi v0.4s, #1, lsl #24"
+
+  -
+    input:
+      bytes: [ 0x20, 0x84, 0x00, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "movi v0.4h, #1"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa4, 0x00, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "movi v0.4h, #1, lsl #8"
+
+  -
+    input:
+      bytes: [ 0x20, 0x84, 0x00, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "movi v0.8h, #1"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa4, 0x00, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "movi v0.8h, #1, lsl #8"
+
+  -
+    input:
+      bytes: [ 0x20, 0x04, 0x00, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "mvni v0.2s, #1"
+
+  -
+    input:
+      bytes: [ 0x01, 0x04, 0x00, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "mvni v1.2s, #0"
+
+  -
+    input:
+      bytes: [ 0x20, 0x24, 0x00, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "mvni v0.2s, #1, lsl #8"
+
+  -
+    input:
+      bytes: [ 0x20, 0x44, 0x00, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "mvni v0.2s, #1, lsl #16"
+
+  -
+    input:
+      bytes: [ 0x20, 0x64, 0x00, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "mvni v0.2s, #1, lsl #24"
+
+  -
+    input:
+      bytes: [ 0x20, 0x04, 0x00, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "mvni v0.4s, #1"
+
+  -
+    input:
+      bytes: [ 0x2f, 0x24, 0x00, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "mvni v15.4s, #1, lsl #8"
+
+  -
+    input:
+      bytes: [ 0x30, 0x44, 0x00, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "mvni v16.4s, #1, lsl #16"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x64, 0x00, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "mvni v31.4s, #1, lsl #24"
+
+  -
+    input:
+      bytes: [ 0x20, 0x84, 0x00, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "mvni v0.4h, #1"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa4, 0x00, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "mvni v0.4h, #1, lsl #8"
+
+  -
+    input:
+      bytes: [ 0x20, 0x84, 0x00, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "mvni v0.8h, #1"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa4, 0x00, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "mvni v0.8h, #1, lsl #8"
+
+  -
+    input:
+      bytes: [ 0x20, 0x14, 0x00, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "bic v0.2s, #1"
+
+  -
+    input:
+      bytes: [ 0x01, 0x14, 0x00, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "bic v1.2s, #0"
+
+  -
+    input:
+      bytes: [ 0x20, 0x34, 0x00, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "bic v0.2s, #1, lsl #8"
+
+  -
+    input:
+      bytes: [ 0x20, 0x54, 0x00, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "bic v0.2s, #1, lsl #16"
+
+  -
+    input:
+      bytes: [ 0x20, 0x74, 0x00, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "bic v0.2s, #1, lsl #24"
+
+  -
+    input:
+      bytes: [ 0x20, 0x14, 0x00, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "bic v0.4s, #1"
+
+  -
+    input:
+      bytes: [ 0x20, 0x34, 0x00, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "bic v0.4s, #1, lsl #8"
+
+  -
+    input:
+      bytes: [ 0x20, 0x54, 0x00, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "bic v0.4s, #1, lsl #16"
+
+  -
+    input:
+      bytes: [ 0x20, 0x74, 0x00, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "bic v0.4s, #1, lsl #24"
+
+  -
+    input:
+      bytes: [ 0x2f, 0x94, 0x00, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "bic v15.4h, #1"
+
+  -
+    input:
+      bytes: [ 0x30, 0xb4, 0x00, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "bic v16.4h, #1, lsl #8"
+
+  -
+    input:
+      bytes: [ 0x20, 0x94, 0x00, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "bic v0.8h, #1"
+
+  -
+    input:
+      bytes: [ 0x3f, 0xb4, 0x00, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "bic v31.8h, #1, lsl #8"
+
+  -
+    input:
+      bytes: [ 0x20, 0x14, 0x00, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "orr v0.2s, #1"
+
+  -
+    input:
+      bytes: [ 0x01, 0x14, 0x00, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "orr v1.2s, #0"
+
+  -
+    input:
+      bytes: [ 0x20, 0x34, 0x00, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "orr v0.2s, #1, lsl #8"
+
+  -
+    input:
+      bytes: [ 0x20, 0x54, 0x00, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "orr v0.2s, #1, lsl #16"
+
+  -
+    input:
+      bytes: [ 0x20, 0x74, 0x00, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "orr v0.2s, #1, lsl #24"
+
+  -
+    input:
+      bytes: [ 0x20, 0x14, 0x00, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "orr v0.4s, #1"
+
+  -
+    input:
+      bytes: [ 0x20, 0x34, 0x00, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "orr v0.4s, #1, lsl #8"
+
+  -
+    input:
+      bytes: [ 0x20, 0x54, 0x00, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "orr v0.4s, #1, lsl #16"
+
+  -
+    input:
+      bytes: [ 0x20, 0x74, 0x00, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "orr v0.4s, #1, lsl #24"
+
+  -
+    input:
+      bytes: [ 0x3f, 0x94, 0x00, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "orr v31.4h, #1"
+
+  -
+    input:
+      bytes: [ 0x2f, 0xb4, 0x00, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "orr v15.4h, #1, lsl #8"
+
+  -
+    input:
+      bytes: [ 0x20, 0x94, 0x00, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "orr v0.8h, #1"
+
+  -
+    input:
+      bytes: [ 0x30, 0xb4, 0x00, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "orr v16.8h, #1, lsl #8"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc4, 0x00, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "movi v0.2s, #1, msl #8"
+
+  -
+    input:
+      bytes: [ 0x21, 0xd4, 0x00, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "movi v1.2s, #1, msl #16"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc4, 0x00, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "movi v0.4s, #1, msl #8"
+
+  -
+    input:
+      bytes: [ 0x3f, 0xd4, 0x00, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "movi v31.4s, #1, msl #16"
+
+  -
+    input:
+      bytes: [ 0x21, 0xc4, 0x00, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "mvni v1.2s, #1, msl #8"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd4, 0x00, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "mvni v0.2s, #1, msl #16"
+
+  -
+    input:
+      bytes: [ 0x3f, 0xc4, 0x00, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "mvni v31.4s, #1, msl #8"
+
+  -
+    input:
+      bytes: [ 0x20, 0xd4, 0x00, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "mvni v0.4s, #1, msl #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe4, 0x00, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "movi v0.8b, #0"
+
+  -
+    input:
+      bytes: [ 0xff, 0xe7, 0x07, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "movi v31.8b, #255"
+
+  -
+    input:
+      bytes: [ 0xef, 0xe5, 0x00, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "movi v15.16b, #15"
+
+  -
+    input:
+      bytes: [ 0xff, 0xe7, 0x00, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "movi v31.16b, #31"
+
+  -
+    input:
+      bytes: [ 0x40, 0xe5, 0x05, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "movi v0.2d, #0xff00ff00ff00ff00"
+
+  -
+    input:
+      bytes: [ 0x40, 0xe5, 0x05, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "movi d0, #0xff00ff00ff00ff00"
+
+  -
+    input:
+      bytes: [ 0x01, 0xf6, 0x03, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov v1.2s, #1.00000000"
+
+  -
+    input:
+      bytes: [ 0x0f, 0xf6, 0x03, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov v15.4s, #1.00000000"
+
+  -
+    input:
+      bytes: [ 0x1f, 0xf6, 0x03, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov v31.2d, #1.00000000"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x1f, 0xbf, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov v0.8b, v31.8b"
+
+  -
+    input:
+      bytes: [ 0x0f, 0x1e, 0xb0, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov v15.16b, v16.16b"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x1f, 0xbf, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov v0.8b, v31.8b"
+
+  -
+    input:
+      bytes: [ 0x0f, 0x1e, 0xb0, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov v15.16b, v16.16b"
diff --git a/tests/MC/AArch64/neon-mul-div-instructions.s.yaml b/tests/MC/AArch64/neon-mul-div-instructions.s.yaml
new file mode 100644
index 000000000..9e3e4c579
--- /dev/null
+++ b/tests/MC/AArch64/neon-mul-div-instructions.s.yaml
@@ -0,0 +1,230 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x9c, 0x22, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul v0.8b, v1.8b, v2.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x9c, 0x22, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul v0.16b, v1.16b, v2.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x9c, 0x62, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul v0.4h, v1.4h, v2.4h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x9c, 0x62, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul v0.8h, v1.8h, v2.8h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x9c, 0xa2, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul v0.2s, v1.2s, v2.2s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x9c, 0xa2, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul v0.4s, v1.4s, v2.4s"
+
+  -
+    input:
+      bytes: [ 0x20, 0xdc, 0x22, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmul v0.2s, v1.2s, v2.2s"
+
+  -
+    input:
+      bytes: [ 0x20, 0xdc, 0x22, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmul v0.4s, v1.4s, v2.4s"
+
+  -
+    input:
+      bytes: [ 0x20, 0xdc, 0x62, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmul v0.2d, v1.2d, v2.2d"
+
+  -
+    input:
+      bytes: [ 0x20, 0xfc, 0x22, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdiv v0.2s, v1.2s, v2.2s"
+
+  -
+    input:
+      bytes: [ 0x20, 0xfc, 0x22, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdiv v0.4s, v1.4s, v2.4s"
+
+  -
+    input:
+      bytes: [ 0x20, 0xfc, 0x62, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdiv v0.2d, v1.2d, v2.2d"
+
+  -
+    input:
+      bytes: [ 0xf1, 0x9f, 0x30, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "pmul v17.8b, v31.8b, v16.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x9c, 0x22, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "pmul v0.16b, v1.16b, v2.16b"
+
+  -
+    input:
+      bytes: [ 0x22, 0xb7, 0x63, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmulh v2.4h, v25.4h, v3.4h"
+
+  -
+    input:
+      bytes: [ 0xac, 0xb4, 0x6d, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmulh v12.8h, v5.8h, v13.8h"
+
+  -
+    input:
+      bytes: [ 0x23, 0xb4, 0xbe, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmulh v3.2s, v1.2s, v30.2s"
+
+  -
+    input:
+      bytes: [ 0x22, 0xb7, 0x63, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrdmulh v2.4h, v25.4h, v3.4h"
+
+  -
+    input:
+      bytes: [ 0xac, 0xb4, 0x6d, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrdmulh v12.8h, v5.8h, v13.8h"
+
+  -
+    input:
+      bytes: [ 0x23, 0xb4, 0xbe, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrdmulh v3.2s, v1.2s, v30.2s"
+
+  -
+    input:
+      bytes: [ 0xb5, 0xdc, 0x2d, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmulx v21.2s, v5.2s, v13.2s"
+
+  -
+    input:
+      bytes: [ 0x21, 0xdf, 0x23, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmulx v1.4s, v25.4s, v3.4s"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xde, 0x62, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmulx v31.2d, v22.2d, v2.2d"
diff --git a/tests/MC/AArch64/neon-perm.s.yaml b/tests/MC/AArch64/neon-perm.s.yaml
new file mode 100644
index 000000000..989341c35
--- /dev/null
+++ b/tests/MC/AArch64/neon-perm.s.yaml
@@ -0,0 +1,420 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x18, 0x02, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzp1 v0.8b, v1.8b, v2.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x18, 0x02, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzp1 v0.16b, v1.16b, v2.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x18, 0x42, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzp1 v0.4h, v1.4h, v2.4h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x18, 0x42, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzp1 v0.8h, v1.8h, v2.8h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x18, 0x82, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzp1 v0.2s, v1.2s, v2.2s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x18, 0x82, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzp1 v0.4s, v1.4s, v2.4s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x18, 0xc2, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzp1 v0.2d, v1.2d, v2.2d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x28, 0x02, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "trn1 v0.8b, v1.8b, v2.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x28, 0x02, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "trn1 v0.16b, v1.16b, v2.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x28, 0x42, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "trn1 v0.4h, v1.4h, v2.4h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x28, 0x42, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "trn1 v0.8h, v1.8h, v2.8h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x28, 0x82, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "trn1 v0.2s, v1.2s, v2.2s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x28, 0x82, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "trn1 v0.4s, v1.4s, v2.4s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x28, 0xc2, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "trn1 v0.2d, v1.2d, v2.2d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x38, 0x02, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip1 v0.8b, v1.8b, v2.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x38, 0x02, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip1 v0.16b, v1.16b, v2.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x38, 0x42, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip1 v0.4h, v1.4h, v2.4h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x38, 0x42, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip1 v0.8h, v1.8h, v2.8h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x38, 0x82, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip1 v0.2s, v1.2s, v2.2s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x38, 0x82, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip1 v0.4s, v1.4s, v2.4s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x38, 0xc2, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip1 v0.2d, v1.2d, v2.2d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x58, 0x02, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzp2 v0.8b, v1.8b, v2.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x58, 0x02, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzp2 v0.16b, v1.16b, v2.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x58, 0x42, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzp2 v0.4h, v1.4h, v2.4h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x58, 0x42, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzp2 v0.8h, v1.8h, v2.8h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x58, 0x82, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzp2 v0.2s, v1.2s, v2.2s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x58, 0x82, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzp2 v0.4s, v1.4s, v2.4s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x58, 0xc2, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "uzp2 v0.2d, v1.2d, v2.2d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x68, 0x02, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "trn2 v0.8b, v1.8b, v2.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x68, 0x02, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "trn2 v0.16b, v1.16b, v2.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x68, 0x42, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "trn2 v0.4h, v1.4h, v2.4h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x68, 0x42, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "trn2 v0.8h, v1.8h, v2.8h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x68, 0x82, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "trn2 v0.2s, v1.2s, v2.2s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x68, 0x82, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "trn2 v0.4s, v1.4s, v2.4s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x68, 0xc2, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "trn2 v0.2d, v1.2d, v2.2d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x78, 0x02, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip2 v0.8b, v1.8b, v2.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x78, 0x02, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip2 v0.16b, v1.16b, v2.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x78, 0x42, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip2 v0.4h, v1.4h, v2.4h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x78, 0x42, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip2 v0.8h, v1.8h, v2.8h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x78, 0x82, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip2 v0.2s, v1.2s, v2.2s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x78, 0x82, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip2 v0.4s, v1.4s, v2.4s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x78, 0xc2, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "zip2 v0.2d, v1.2d, v2.2d"
diff --git a/tests/MC/AArch64/neon-rounding-halving-add.s.yaml b/tests/MC/AArch64/neon-rounding-halving-add.s.yaml
new file mode 100644
index 000000000..45430adc8
--- /dev/null
+++ b/tests/MC/AArch64/neon-rounding-halving-add.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x14, 0x22, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "srhadd v0.8b, v1.8b, v2.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x14, 0x22, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "srhadd v0.16b, v1.16b, v2.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x14, 0x62, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "srhadd v0.4h, v1.4h, v2.4h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x14, 0x62, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "srhadd v0.8h, v1.8h, v2.8h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x14, 0xa2, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "srhadd v0.2s, v1.2s, v2.2s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x14, 0xa2, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "srhadd v0.4s, v1.4s, v2.4s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x14, 0x22, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "urhadd v0.8b, v1.8b, v2.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x14, 0x22, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "urhadd v0.16b, v1.16b, v2.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x14, 0x62, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "urhadd v0.4h, v1.4h, v2.4h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x14, 0x62, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "urhadd v0.8h, v1.8h, v2.8h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x14, 0xa2, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "urhadd v0.2s, v1.2s, v2.2s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x14, 0xa2, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "urhadd v0.4s, v1.4s, v2.4s"
diff --git a/tests/MC/AArch64/neon-rounding-shift.s.yaml b/tests/MC/AArch64/neon-rounding-shift.s.yaml
new file mode 100644
index 000000000..8b15af072
--- /dev/null
+++ b/tests/MC/AArch64/neon-rounding-shift.s.yaml
@@ -0,0 +1,140 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x54, 0x22, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshl v0.8b, v1.8b, v2.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x54, 0x22, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshl v0.16b, v1.16b, v2.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x54, 0x62, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshl v0.4h, v1.4h, v2.4h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x54, 0x62, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshl v0.8h, v1.8h, v2.8h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x54, 0xa2, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshl v0.2s, v1.2s, v2.2s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x54, 0xa2, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshl v0.4s, v1.4s, v2.4s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x54, 0xe2, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshl v0.2d, v1.2d, v2.2d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x54, 0x22, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshl v0.8b, v1.8b, v2.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x54, 0x22, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshl v0.16b, v1.16b, v2.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x54, 0x62, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshl v0.4h, v1.4h, v2.4h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x54, 0x62, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshl v0.8h, v1.8h, v2.8h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x54, 0xa2, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshl v0.2s, v1.2s, v2.2s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x54, 0xa2, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshl v0.4s, v1.4s, v2.4s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x54, 0xe2, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshl v0.2d, v1.2d, v2.2d"
diff --git a/tests/MC/AArch64/neon-saturating-add-sub.s.yaml b/tests/MC/AArch64/neon-saturating-add-sub.s.yaml
new file mode 100644
index 000000000..df44702a6
--- /dev/null
+++ b/tests/MC/AArch64/neon-saturating-add-sub.s.yaml
@@ -0,0 +1,280 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x0c, 0x22, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqadd v0.8b, v1.8b, v2.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x0c, 0x22, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqadd v0.16b, v1.16b, v2.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x0c, 0x62, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqadd v0.4h, v1.4h, v2.4h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x0c, 0x62, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqadd v0.8h, v1.8h, v2.8h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x0c, 0xa2, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqadd v0.2s, v1.2s, v2.2s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x0c, 0xa2, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqadd v0.4s, v1.4s, v2.4s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x0c, 0xe2, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqadd v0.2d, v1.2d, v2.2d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x0c, 0x22, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqadd v0.8b, v1.8b, v2.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x0c, 0x22, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqadd v0.16b, v1.16b, v2.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x0c, 0x62, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqadd v0.4h, v1.4h, v2.4h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x0c, 0x62, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqadd v0.8h, v1.8h, v2.8h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x0c, 0xa2, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqadd v0.2s, v1.2s, v2.2s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x0c, 0xa2, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqadd v0.4s, v1.4s, v2.4s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x0c, 0xe2, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqadd v0.2d, v1.2d, v2.2d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x2c, 0x22, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqsub v0.8b, v1.8b, v2.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x2c, 0x22, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqsub v0.16b, v1.16b, v2.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x2c, 0x62, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqsub v0.4h, v1.4h, v2.4h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x2c, 0x62, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqsub v0.8h, v1.8h, v2.8h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x2c, 0xa2, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqsub v0.2s, v1.2s, v2.2s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x2c, 0xa2, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqsub v0.4s, v1.4s, v2.4s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x2c, 0xe2, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqsub v0.2d, v1.2d, v2.2d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x2c, 0x22, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqsub v0.8b, v1.8b, v2.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x2c, 0x22, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqsub v0.16b, v1.16b, v2.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x2c, 0x62, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqsub v0.4h, v1.4h, v2.4h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x2c, 0x62, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqsub v0.8h, v1.8h, v2.8h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x2c, 0xa2, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqsub v0.2s, v1.2s, v2.2s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x2c, 0xa2, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqsub v0.4s, v1.4s, v2.4s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x2c, 0xe2, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqsub v0.2d, v1.2d, v2.2d"
diff --git a/tests/MC/AArch64/neon-saturating-rounding-shift.s.yaml b/tests/MC/AArch64/neon-saturating-rounding-shift.s.yaml
new file mode 100644
index 000000000..b8a9b7bb7
--- /dev/null
+++ b/tests/MC/AArch64/neon-saturating-rounding-shift.s.yaml
@@ -0,0 +1,140 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x5c, 0x22, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshl v0.8b, v1.8b, v2.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x5c, 0x22, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshl v0.16b, v1.16b, v2.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x5c, 0x62, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshl v0.4h, v1.4h, v2.4h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x5c, 0x62, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshl v0.8h, v1.8h, v2.8h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x5c, 0xa2, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshl v0.2s, v1.2s, v2.2s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x5c, 0xa2, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshl v0.4s, v1.4s, v2.4s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x5c, 0xe2, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshl v0.2d, v1.2d, v2.2d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x5c, 0x22, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqrshl v0.8b, v1.8b, v2.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x5c, 0x22, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqrshl v0.16b, v1.16b, v2.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x5c, 0x62, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqrshl v0.4h, v1.4h, v2.4h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x5c, 0x62, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqrshl v0.8h, v1.8h, v2.8h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x5c, 0xa2, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqrshl v0.2s, v1.2s, v2.2s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x5c, 0xa2, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqrshl v0.4s, v1.4s, v2.4s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x5c, 0xe2, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqrshl v0.2d, v1.2d, v2.2d"
diff --git a/tests/MC/AArch64/neon-saturating-shift.s.yaml b/tests/MC/AArch64/neon-saturating-shift.s.yaml
new file mode 100644
index 000000000..589d7b3d2
--- /dev/null
+++ b/tests/MC/AArch64/neon-saturating-shift.s.yaml
@@ -0,0 +1,140 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x4c, 0x22, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshl v0.8b, v1.8b, v2.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x4c, 0x22, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshl v0.16b, v1.16b, v2.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x4c, 0x62, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshl v0.4h, v1.4h, v2.4h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x4c, 0x62, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshl v0.8h, v1.8h, v2.8h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x4c, 0xa2, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshl v0.2s, v1.2s, v2.2s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x4c, 0xa2, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshl v0.4s, v1.4s, v2.4s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x4c, 0xe2, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshl v0.2d, v1.2d, v2.2d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x4c, 0x22, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqshl v0.8b, v1.8b, v2.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x4c, 0x22, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqshl v0.16b, v1.16b, v2.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x4c, 0x62, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqshl v0.4h, v1.4h, v2.4h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x4c, 0x62, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqshl v0.8h, v1.8h, v2.8h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x4c, 0xa2, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqshl v0.2s, v1.2s, v2.2s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x4c, 0xa2, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqshl v0.4s, v1.4s, v2.4s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x4c, 0xe2, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqshl v0.2d, v1.2d, v2.2d"
diff --git a/tests/MC/AArch64/neon-scalar-abs.s.yaml b/tests/MC/AArch64/neon-scalar-abs.s.yaml
new file mode 100644
index 000000000..ca92632a8
--- /dev/null
+++ b/tests/MC/AArch64/neon-scalar-abs.s.yaml
@@ -0,0 +1,80 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x1d, 0xbb, 0xe0, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "abs d29, d24"
+
+  -
+    input:
+      bytes: [ 0x1d, 0x17, 0xd4, 0x7e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fabd h29, h24, h20"
+
+  -
+    input:
+      bytes: [ 0x1d, 0xd7, 0xb4, 0x7e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fabd s29, s24, s20"
+
+  -
+    input:
+      bytes: [ 0x1d, 0xd7, 0xf4, 0x7e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fabd d29, d24, d20"
+
+  -
+    input:
+      bytes: [ 0xd3, 0x79, 0x20, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqabs b19, b14"
+
+  -
+    input:
+      bytes: [ 0xf5, 0x79, 0x60, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqabs h21, h15"
+
+  -
+    input:
+      bytes: [ 0x94, 0x79, 0xa0, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqabs s20, s12"
+
+  -
+    input:
+      bytes: [ 0x92, 0x79, 0xe0, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqabs d18, d12"
diff --git a/tests/MC/AArch64/neon-scalar-add-sub.s.yaml b/tests/MC/AArch64/neon-scalar-add-sub.s.yaml
new file mode 100644
index 000000000..eff424950
--- /dev/null
+++ b/tests/MC/AArch64/neon-scalar-add-sub.s.yaml
@@ -0,0 +1,20 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x1f, 0x84, 0xf0, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d31, d0, d16"
+
+  -
+    input:
+      bytes: [ 0xe1, 0x84, 0xe8, 0x7e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub d1, d7, d8"
diff --git a/tests/MC/AArch64/neon-scalar-by-elem-mla.s.yaml b/tests/MC/AArch64/neon-scalar-by-elem-mla.s.yaml
new file mode 100644
index 000000000..9c3103c99
--- /dev/null
+++ b/tests/MC/AArch64/neon-scalar-by-elem-mla.s.yaml
@@ -0,0 +1,140 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x18, 0x11, 0x5f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla h0, h1, v1.h[5]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x10, 0x81, 0x5f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla s0, s1, v1.s[0]"
+
+  -
+    input:
+      bytes: [ 0x7e, 0x11, 0xa1, 0x5f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla s30, s11, v1.s[1]"
+
+  -
+    input:
+      bytes: [ 0xa4, 0x18, 0x87, 0x5f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla s4, s5, v7.s[2]"
+
+  -
+    input:
+      bytes: [ 0xd0, 0x1a, 0xb0, 0x5f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla s16, s22, v16.s[3]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x10, 0xc1, 0x5f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla d0, d1, v1.d[0]"
+
+  -
+    input:
+      bytes: [ 0x7e, 0x19, 0xc1, 0x5f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmla d30, d11, v1.d[1]"
+
+  -
+    input:
+      bytes: [ 0x62, 0x58, 0x14, 0x5f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls h2, h3, v4.h[5]"
+
+  -
+    input:
+      bytes: [ 0x62, 0x50, 0x84, 0x5f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls s2, s3, v4.s[0]"
+
+  -
+    input:
+      bytes: [ 0x5d, 0x51, 0xbc, 0x5f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls s29, s10, v28.s[1]"
+
+  -
+    input:
+      bytes: [ 0x85, 0x59, 0x97, 0x5f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls s5, s12, v23.s[2]"
+
+  -
+    input:
+      bytes: [ 0x27, 0x5a, 0xba, 0x5f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls s7, s17, v26.s[3]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x50, 0xc1, 0x5f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls d0, d1, v1.d[0]"
+
+  -
+    input:
+      bytes: [ 0x7e, 0x59, 0xc1, 0x5f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmls d30, d11, v1.d[1]"
diff --git a/tests/MC/AArch64/neon-scalar-by-elem-mul.s.yaml b/tests/MC/AArch64/neon-scalar-by-elem-mul.s.yaml
new file mode 100644
index 000000000..248de73b9
--- /dev/null
+++ b/tests/MC/AArch64/neon-scalar-by-elem-mul.s.yaml
@@ -0,0 +1,140 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x98, 0x11, 0x5f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmul h0, h1, v1.h[5]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x90, 0x81, 0x5f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmul s0, s1, v1.s[0]"
+
+  -
+    input:
+      bytes: [ 0x7e, 0x91, 0xa1, 0x5f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmul s30, s11, v1.s[1]"
+
+  -
+    input:
+      bytes: [ 0xa4, 0x98, 0x87, 0x5f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmul s4, s5, v7.s[2]"
+
+  -
+    input:
+      bytes: [ 0xd0, 0x9a, 0xb0, 0x5f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmul s16, s22, v16.s[3]"
+
+  -
+    input:
+      bytes: [ 0x20, 0x90, 0xc1, 0x5f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmul d0, d1, v1.d[0]"
+
+  -
+    input:
+      bytes: [ 0x7e, 0x99, 0xc1, 0x5f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmul d30, d11, v1.d[1]"
+
+  -
+    input:
+      bytes: [ 0x46, 0x98, 0x18, 0x7f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmulx h6, h2, v8.h[5]"
+
+  -
+    input:
+      bytes: [ 0x46, 0x90, 0x88, 0x7f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmulx s6, s2, v8.s[0]"
+
+  -
+    input:
+      bytes: [ 0x67, 0x90, 0xad, 0x7f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmulx s7, s3, v13.s[1]"
+
+  -
+    input:
+      bytes: [ 0xe9, 0x98, 0x89, 0x7f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmulx s9, s7, v9.s[2]"
+
+  -
+    input:
+      bytes: [ 0xad, 0x9a, 0xaa, 0x7f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmulx s13, s21, v10.s[3]"
+
+  -
+    input:
+      bytes: [ 0x2f, 0x91, 0xc7, 0x7f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmulx d15, d9, v7.d[0]"
+
+  -
+    input:
+      bytes: [ 0x8d, 0x99, 0xcb, 0x7f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmulx d13, d12, v11.d[1]"
diff --git a/tests/MC/AArch64/neon-scalar-by-elem-saturating-mla.s.yaml b/tests/MC/AArch64/neon-scalar-by-elem-saturating-mla.s.yaml
new file mode 100644
index 000000000..11319c544
--- /dev/null
+++ b/tests/MC/AArch64/neon-scalar-by-elem-saturating-mla.s.yaml
@@ -0,0 +1,140 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x30, 0x40, 0x5f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmlal s0, h0, v0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x27, 0x30, 0x74, 0x5f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmlal s7, h1, v4.h[3]"
+
+  -
+    input:
+      bytes: [ 0x0b, 0x3a, 0x48, 0x5f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmlal s11, h16, v8.h[4]"
+
+  -
+    input:
+      bytes: [ 0xde, 0x3b, 0x7f, 0x5f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmlal s30, h30, v15.h[7]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x30, 0x83, 0x5f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmlal d0, s0, v3.s[0]"
+
+  -
+    input:
+      bytes: [ 0xde, 0x3b, 0xbe, 0x5f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmlal d30, s30, v30.s[3]"
+
+  -
+    input:
+      bytes: [ 0x28, 0x31, 0xae, 0x5f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmlal d8, s9, v14.s[1]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x70, 0x41, 0x5f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmlsl s1, h1, v1.h[0]"
+
+  -
+    input:
+      bytes: [ 0x48, 0x70, 0x55, 0x5f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmlsl s8, h2, v5.h[1]"
+
+  -
+    input:
+      bytes: [ 0xac, 0x71, 0x6e, 0x5f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmlsl s12, h13, v14.h[2]"
+
+  -
+    input:
+      bytes: [ 0x9d, 0x7b, 0x7b, 0x5f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmlsl s29, h28, v11.h[7]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x70, 0x8d, 0x5f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmlsl d1, s1, v13.s[0]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x7b, 0x9f, 0x5f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmlsl d31, s31, v31.s[2]"
+
+  -
+    input:
+      bytes: [ 0x50, 0x7a, 0xbc, 0x5f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmlsl d16, s18, v28.s[3]"
diff --git a/tests/MC/AArch64/neon-scalar-by-elem-saturating-mul.s.yaml b/tests/MC/AArch64/neon-scalar-by-elem-saturating-mul.s.yaml
new file mode 100644
index 000000000..4cafebde7
--- /dev/null
+++ b/tests/MC/AArch64/neon-scalar-by-elem-saturating-mul.s.yaml
@@ -0,0 +1,170 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x21, 0xb0, 0x51, 0x5f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmull s1, h1, v1.h[1]"
+
+  -
+    input:
+      bytes: [ 0x48, 0xb0, 0x65, 0x5f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmull s8, h2, v5.h[2]"
+
+  -
+    input:
+      bytes: [ 0x2c, 0xb2, 0x79, 0x5f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmull s12, h17, v9.h[3]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbb, 0x7f, 0x5f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmull s31, h31, v15.h[7]"
+
+  -
+    input:
+      bytes: [ 0x21, 0xb0, 0x84, 0x5f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmull d1, s1, v4.s[0]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xbb, 0xbf, 0x5f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmull d31, s31, v31.s[3]"
+
+  -
+    input:
+      bytes: [ 0x49, 0xb1, 0x8f, 0x5f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmull d9, s10, v15.s[0]"
+
+  -
+    input:
+      bytes: [ 0x20, 0xc0, 0x40, 0x5f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmulh h0, h1, v0.h[0]"
+
+  -
+    input:
+      bytes: [ 0x6a, 0xc9, 0x4a, 0x5f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmulh h10, h11, v10.h[4]"
+
+  -
+    input:
+      bytes: [ 0xb4, 0xca, 0x7f, 0x5f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmulh h20, h21, v15.h[7]"
+
+  -
+    input:
+      bytes: [ 0x59, 0xcb, 0xbb, 0x5f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmulh s25, s26, v27.s[3]"
+
+  -
+    input:
+      bytes: [ 0xc2, 0xc0, 0x87, 0x5f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmulh s2, s6, v7.s[0]"
+
+  -
+    input:
+      bytes: [ 0xdf, 0xd3, 0x6e, 0x5f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrdmulh h31, h30, v14.h[2]"
+
+  -
+    input:
+      bytes: [ 0x21, 0xd8, 0x41, 0x5f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrdmulh h1, h1, v1.h[4]"
+
+  -
+    input:
+      bytes: [ 0xd5, 0xda, 0x7f, 0x5f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrdmulh h21, h22, v15.h[7]"
+
+  -
+    input:
+      bytes: [ 0xc5, 0xd8, 0x87, 0x5f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrdmulh s5, s6, v7.s[2]"
+
+  -
+    input:
+      bytes: [ 0x54, 0xd3, 0xbb, 0x5f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrdmulh s20, s26, v27.s[1]"
diff --git a/tests/MC/AArch64/neon-scalar-compare.s.yaml b/tests/MC/AArch64/neon-scalar-compare.s.yaml
new file mode 100644
index 000000000..ad71b7d67
--- /dev/null
+++ b/tests/MC/AArch64/neon-scalar-compare.s.yaml
@@ -0,0 +1,110 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xb4, 0x8e, 0xf6, 0x7e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmeq d20, d21, d22"
+
+  -
+    input:
+      bytes: [ 0xb4, 0x9a, 0xe0, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmeq d20, d21, #0"
+
+  -
+    input:
+      bytes: [ 0xb4, 0x3e, 0xf6, 0x7e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmhs d20, d21, d22"
+
+  -
+    input:
+      bytes: [ 0xb4, 0x3e, 0xf6, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmge d20, d21, d22"
+
+  -
+    input:
+      bytes: [ 0xb4, 0x8a, 0xe0, 0x7e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmge d20, d21, #0"
+
+  -
+    input:
+      bytes: [ 0xb4, 0x36, 0xf6, 0x7e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmhi d20, d21, d22"
+
+  -
+    input:
+      bytes: [ 0xb4, 0x36, 0xf6, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmgt d20, d21, d22"
+
+  -
+    input:
+      bytes: [ 0xb4, 0x8a, 0xe0, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmgt d20, d21, #0"
+
+  -
+    input:
+      bytes: [ 0xb4, 0x9a, 0xe0, 0x7e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmle d20, d21, #0"
+
+  -
+    input:
+      bytes: [ 0xb4, 0xaa, 0xe0, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmlt d20, d21, #0"
+
+  -
+    input:
+      bytes: [ 0xb4, 0x8e, 0xf6, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmtst d20, d21, d22"
diff --git a/tests/MC/AArch64/neon-scalar-cvt.s.yaml b/tests/MC/AArch64/neon-scalar-cvt.s.yaml
new file mode 100644
index 000000000..8d8c06e5a
--- /dev/null
+++ b/tests/MC/AArch64/neon-scalar-cvt.s.yaml
@@ -0,0 +1,490 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xd7, 0xd9, 0x79, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "scvtf h23, h14"
+
+  -
+    input:
+      bytes: [ 0xb6, 0xd9, 0x21, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "scvtf s22, s13"
+
+  -
+    input:
+      bytes: [ 0x95, 0xd9, 0x61, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "scvtf d21, d12"
+
+  -
+    input:
+      bytes: [ 0x94, 0xd9, 0x79, 0x7e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "ucvtf h20, h12"
+
+  -
+    input:
+      bytes: [ 0xb6, 0xd9, 0x21, 0x7e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "ucvtf s22, s13"
+
+  -
+    input:
+      bytes: [ 0xd5, 0xd9, 0x61, 0x7e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "ucvtf d21, d14"
+
+  -
+    input:
+      bytes: [ 0xb6, 0xe5, 0x10, 0x5f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "scvtf h22, h13, #16"
+
+  -
+    input:
+      bytes: [ 0xb6, 0xe5, 0x20, 0x5f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "scvtf s22, s13, #32"
+
+  -
+    input:
+      bytes: [ 0x95, 0xe5, 0x40, 0x5f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "scvtf d21, d12, #64"
+
+  -
+    input:
+      bytes: [ 0xb6, 0xe5, 0x10, 0x7f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "ucvtf h22, h13, #16"
+
+  -
+    input:
+      bytes: [ 0xb6, 0xe5, 0x20, 0x7f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "ucvtf s22, s13, #32"
+
+  -
+    input:
+      bytes: [ 0xd5, 0xe5, 0x40, 0x7f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "ucvtf d21, d14, #64"
+
+  -
+    input:
+      bytes: [ 0x95, 0xfd, 0x1f, 0x5f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtzs h21, h12, #1"
+
+  -
+    input:
+      bytes: [ 0x95, 0xfd, 0x3f, 0x5f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtzs s21, s12, #1"
+
+  -
+    input:
+      bytes: [ 0x95, 0xfd, 0x7f, 0x5f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtzs d21, d12, #1"
+
+  -
+    input:
+      bytes: [ 0x95, 0xfd, 0x1f, 0x7f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtzu h21, h12, #1"
+
+  -
+    input:
+      bytes: [ 0x95, 0xfd, 0x3f, 0x7f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtzu s21, s12, #1"
+
+  -
+    input:
+      bytes: [ 0x95, 0xfd, 0x7f, 0x7f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtzu d21, d12, #1"
+
+  -
+    input:
+      bytes: [ 0xb6, 0x69, 0x61, 0x7e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtxn s22, d13"
+
+  -
+    input:
+      bytes: [ 0xac, 0xc9, 0x79, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtas h12, h13"
+
+  -
+    input:
+      bytes: [ 0xac, 0xc9, 0x21, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtas s12, s13"
+
+  -
+    input:
+      bytes: [ 0xd5, 0xc9, 0x61, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtas d21, d14"
+
+  -
+    input:
+      bytes: [ 0xac, 0xc9, 0x79, 0x7e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtau h12, h13"
+
+  -
+    input:
+      bytes: [ 0xac, 0xc9, 0x21, 0x7e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtau s12, s13"
+
+  -
+    input:
+      bytes: [ 0xd5, 0xc9, 0x61, 0x7e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtau d21, d14"
+
+  -
+    input:
+      bytes: [ 0xb6, 0xb9, 0x79, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtms h22, h13"
+
+  -
+    input:
+      bytes: [ 0xb6, 0xb9, 0x21, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtms s22, s13"
+
+  -
+    input:
+      bytes: [ 0xd5, 0xb9, 0x61, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtms d21, d14"
+
+  -
+    input:
+      bytes: [ 0xac, 0xb9, 0x79, 0x7e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtmu h12, h13"
+
+  -
+    input:
+      bytes: [ 0xac, 0xb9, 0x21, 0x7e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtmu s12, s13"
+
+  -
+    input:
+      bytes: [ 0xd5, 0xb9, 0x61, 0x7e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtmu d21, d14"
+
+  -
+    input:
+      bytes: [ 0xb6, 0xa9, 0x79, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtns h22, h13"
+
+  -
+    input:
+      bytes: [ 0xb6, 0xa9, 0x21, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtns s22, s13"
+
+  -
+    input:
+      bytes: [ 0xd5, 0xa9, 0x61, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtns d21, d14"
+
+  -
+    input:
+      bytes: [ 0xac, 0xa9, 0x79, 0x7e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtnu h12, h13"
+
+  -
+    input:
+      bytes: [ 0xac, 0xa9, 0x21, 0x7e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtnu s12, s13"
+
+  -
+    input:
+      bytes: [ 0xd5, 0xa9, 0x61, 0x7e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtnu d21, d14"
+
+  -
+    input:
+      bytes: [ 0xb6, 0xa9, 0xf9, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtps h22, h13"
+
+  -
+    input:
+      bytes: [ 0xb6, 0xa9, 0xa1, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtps s22, s13"
+
+  -
+    input:
+      bytes: [ 0xd5, 0xa9, 0xe1, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtps d21, d14"
+
+  -
+    input:
+      bytes: [ 0xac, 0xa9, 0xf9, 0x7e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtpu h12, h13"
+
+  -
+    input:
+      bytes: [ 0xac, 0xa9, 0xa1, 0x7e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtpu s12, s13"
+
+  -
+    input:
+      bytes: [ 0xd5, 0xa9, 0xe1, 0x7e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtpu d21, d14"
+
+  -
+    input:
+      bytes: [ 0xac, 0xb9, 0xf9, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtzs h12, h13"
+
+  -
+    input:
+      bytes: [ 0xac, 0xb9, 0xa1, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtzs s12, s13"
+
+  -
+    input:
+      bytes: [ 0xd5, 0xb9, 0xe1, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtzs d21, d14"
+
+  -
+    input:
+      bytes: [ 0xac, 0xb9, 0xf9, 0x7e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtzu h12, h13"
+
+  -
+    input:
+      bytes: [ 0xac, 0xb9, 0xa1, 0x7e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtzu s12, s13"
+
+  -
+    input:
+      bytes: [ 0xd5, 0xb9, 0xe1, 0x7e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtzu d21, d14"
diff --git a/tests/MC/AArch64/neon-scalar-dup.s.yaml b/tests/MC/AArch64/neon-scalar-dup.s.yaml
new file mode 100644
index 000000000..f9f463056
--- /dev/null
+++ b/tests/MC/AArch64/neon-scalar-dup.s.yaml
@@ -0,0 +1,220 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x04, 0x1f, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov b0, v0.b[15]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x04, 0x0f, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov b1, v0.b[7]"
+
+  -
+    input:
+      bytes: [ 0x11, 0x04, 0x01, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov b17, v0.b[0]"
+
+  -
+    input:
+      bytes: [ 0xe5, 0x07, 0x1e, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov h5, v31.h[7]"
+
+  -
+    input:
+      bytes: [ 0x29, 0x04, 0x12, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov h9, v1.h[4]"
+
+  -
+    input:
+      bytes: [ 0x2b, 0x06, 0x02, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov h11, v17.h[0]"
+
+  -
+    input:
+      bytes: [ 0x42, 0x04, 0x1c, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov s2, v2.s[3]"
+
+  -
+    input:
+      bytes: [ 0xa4, 0x06, 0x04, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov s4, v21.s[0]"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x06, 0x14, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov s31, v21.s[2]"
+
+  -
+    input:
+      bytes: [ 0xa3, 0x04, 0x08, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d3, v5.d[0]"
+
+  -
+    input:
+      bytes: [ 0xa6, 0x04, 0x18, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d6, v5.d[1]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x04, 0x1f, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov b0, v0.b[15]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x04, 0x0f, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov b1, v0.b[7]"
+
+  -
+    input:
+      bytes: [ 0x11, 0x04, 0x01, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov b17, v0.b[0]"
+
+  -
+    input:
+      bytes: [ 0xe5, 0x07, 0x1e, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov h5, v31.h[7]"
+
+  -
+    input:
+      bytes: [ 0x29, 0x04, 0x12, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov h9, v1.h[4]"
+
+  -
+    input:
+      bytes: [ 0x2b, 0x06, 0x02, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov h11, v17.h[0]"
+
+  -
+    input:
+      bytes: [ 0x42, 0x04, 0x1c, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov s2, v2.s[3]"
+
+  -
+    input:
+      bytes: [ 0xa4, 0x06, 0x04, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov s4, v21.s[0]"
+
+  -
+    input:
+      bytes: [ 0xbf, 0x06, 0x14, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov s31, v21.s[2]"
+
+  -
+    input:
+      bytes: [ 0xa3, 0x04, 0x08, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d3, v5.d[0]"
+
+  -
+    input:
+      bytes: [ 0xa6, 0x04, 0x18, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d6, v5.d[1]"
diff --git a/tests/MC/AArch64/neon-scalar-extract-narrow.s.yaml b/tests/MC/AArch64/neon-scalar-extract-narrow.s.yaml
new file mode 100644
index 000000000..4eefeac15
--- /dev/null
+++ b/tests/MC/AArch64/neon-scalar-extract-narrow.s.yaml
@@ -0,0 +1,90 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xd3, 0x29, 0x21, 0x7e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqxtun b19, h14"
+
+  -
+    input:
+      bytes: [ 0xf5, 0x29, 0x61, 0x7e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqxtun h21, s15"
+
+  -
+    input:
+      bytes: [ 0x94, 0x29, 0xa1, 0x7e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqxtun s20, d12"
+
+  -
+    input:
+      bytes: [ 0x52, 0x4a, 0x21, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqxtn b18, h18"
+
+  -
+    input:
+      bytes: [ 0x34, 0x4a, 0x61, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqxtn h20, s17"
+
+  -
+    input:
+      bytes: [ 0xd3, 0x49, 0xa1, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqxtn s19, d14"
+
+  -
+    input:
+      bytes: [ 0x52, 0x4a, 0x21, 0x7e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqxtn b18, h18"
+
+  -
+    input:
+      bytes: [ 0x34, 0x4a, 0x61, 0x7e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqxtn h20, s17"
+
+  -
+    input:
+      bytes: [ 0xd3, 0x49, 0xa1, 0x7e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqxtn s19, d14"
diff --git a/tests/MC/AArch64/neon-scalar-fp-compare.s.yaml b/tests/MC/AArch64/neon-scalar-fp-compare.s.yaml
new file mode 100644
index 000000000..e4373d85f
--- /dev/null
+++ b/tests/MC/AArch64/neon-scalar-fp-compare.s.yaml
@@ -0,0 +1,450 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x6a, 0x25, 0x4c, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmeq h10, h11, h12"
+
+  -
+    input:
+      bytes: [ 0x6a, 0xe5, 0x2c, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmeq s10, s11, s12"
+
+  -
+    input:
+      bytes: [ 0xb4, 0xe6, 0x76, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmeq d20, d21, d22"
+
+  -
+    input:
+      bytes: [ 0x6a, 0xd9, 0xf8, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmeq h10, h11, #0.0"
+
+  -
+    input:
+      bytes: [ 0x6a, 0xd9, 0xa0, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmeq s10, s11, #0.0"
+
+  -
+    input:
+      bytes: [ 0xb4, 0xda, 0xe0, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmeq d20, d21, #0.0"
+
+  -
+    input:
+      bytes: [ 0x6a, 0xd9, 0xf8, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmeq h10, h11, #0.0"
+
+  -
+    input:
+      bytes: [ 0x6a, 0xd9, 0xa0, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmeq s10, s11, #0.0"
+
+  -
+    input:
+      bytes: [ 0xb4, 0xda, 0xe0, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmeq d20, d21, #0.0"
+
+  -
+    input:
+      bytes: [ 0x6a, 0x25, 0x4c, 0x7e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmge h10, h11, h12"
+
+  -
+    input:
+      bytes: [ 0x6a, 0xe5, 0x2c, 0x7e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmge s10, s11, s12"
+
+  -
+    input:
+      bytes: [ 0xb4, 0xe6, 0x76, 0x7e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmge d20, d21, d22"
+
+  -
+    input:
+      bytes: [ 0x6a, 0xc9, 0xf8, 0x7e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmge h10, h11, #0.0"
+
+  -
+    input:
+      bytes: [ 0x6a, 0xc9, 0xa0, 0x7e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmge s10, s11, #0.0"
+
+  -
+    input:
+      bytes: [ 0xb4, 0xca, 0xe0, 0x7e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmge d20, d21, #0.0"
+
+  -
+    input:
+      bytes: [ 0x6a, 0xc9, 0xf8, 0x7e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmge h10, h11, #0.0"
+
+  -
+    input:
+      bytes: [ 0x6a, 0xc9, 0xa0, 0x7e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmge s10, s11, #0.0"
+
+  -
+    input:
+      bytes: [ 0xb4, 0xca, 0xe0, 0x7e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmge d20, d21, #0.0"
+
+  -
+    input:
+      bytes: [ 0x6a, 0x25, 0xcc, 0x7e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmgt h10, h11, h12"
+
+  -
+    input:
+      bytes: [ 0x6a, 0xe5, 0xac, 0x7e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmgt s10, s11, s12"
+
+  -
+    input:
+      bytes: [ 0xb4, 0xe6, 0xf6, 0x7e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmgt d20, d21, d22"
+
+  -
+    input:
+      bytes: [ 0x6a, 0xc9, 0xf8, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmgt h10, h11, #0.0"
+
+  -
+    input:
+      bytes: [ 0x6a, 0xc9, 0xa0, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmgt s10, s11, #0.0"
+
+  -
+    input:
+      bytes: [ 0xb4, 0xca, 0xe0, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmgt d20, d21, #0.0"
+
+  -
+    input:
+      bytes: [ 0x6a, 0xc9, 0xf8, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmgt h10, h11, #0.0"
+
+  -
+    input:
+      bytes: [ 0x6a, 0xc9, 0xa0, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmgt s10, s11, #0.0"
+
+  -
+    input:
+      bytes: [ 0xb4, 0xca, 0xe0, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmgt d20, d21, #0.0"
+
+  -
+    input:
+      bytes: [ 0x6a, 0xd9, 0xf8, 0x7e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmle h10, h11, #0.0"
+
+  -
+    input:
+      bytes: [ 0x6a, 0xd9, 0xa0, 0x7e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmle s10, s11, #0.0"
+
+  -
+    input:
+      bytes: [ 0xb4, 0xda, 0xe0, 0x7e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmle d20, d21, #0.0"
+
+  -
+    input:
+      bytes: [ 0x6a, 0xd9, 0xf8, 0x7e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmle h10, h11, #0.0"
+
+  -
+    input:
+      bytes: [ 0x6a, 0xd9, 0xa0, 0x7e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmle s10, s11, #0.0"
+
+  -
+    input:
+      bytes: [ 0xb4, 0xda, 0xe0, 0x7e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmle d20, d21, #0.0"
+
+  -
+    input:
+      bytes: [ 0x6a, 0xe9, 0xf8, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmlt h10, h11, #0.0"
+
+  -
+    input:
+      bytes: [ 0x6a, 0xe9, 0xa0, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmlt s10, s11, #0.0"
+
+  -
+    input:
+      bytes: [ 0xb4, 0xea, 0xe0, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmlt d20, d21, #0.0"
+
+  -
+    input:
+      bytes: [ 0x6a, 0xe9, 0xf8, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmlt h10, h11, #0.0"
+
+  -
+    input:
+      bytes: [ 0x6a, 0xe9, 0xa0, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmlt s10, s11, #0.0"
+
+  -
+    input:
+      bytes: [ 0xb4, 0xea, 0xe0, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmlt d20, d21, #0.0"
+
+  -
+    input:
+      bytes: [ 0x6a, 0x2d, 0x4c, 0x7e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "facge h10, h11, h12"
+
+  -
+    input:
+      bytes: [ 0x6a, 0xed, 0x2c, 0x7e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "facge s10, s11, s12"
+
+  -
+    input:
+      bytes: [ 0xb4, 0xee, 0x76, 0x7e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "facge d20, d21, d22"
+
+  -
+    input:
+      bytes: [ 0x6a, 0x2d, 0xcc, 0x7e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "facgt h10, h11, h12"
+
+  -
+    input:
+      bytes: [ 0x6a, 0xed, 0xac, 0x7e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "facgt s10, s11, s12"
+
+  -
+    input:
+      bytes: [ 0xb4, 0xee, 0xf6, 0x7e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "facgt d20, d21, d22"
diff --git a/tests/MC/AArch64/neon-scalar-mul.s.yaml b/tests/MC/AArch64/neon-scalar-mul.s.yaml
new file mode 100644
index 000000000..044446699
--- /dev/null
+++ b/tests/MC/AArch64/neon-scalar-mul.s.yaml
@@ -0,0 +1,130 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x6a, 0xb5, 0x6c, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmulh h10, h11, h12"
+
+  -
+    input:
+      bytes: [ 0xb4, 0xb6, 0xa2, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmulh s20, s21, s2"
+
+  -
+    input:
+      bytes: [ 0x6a, 0xb5, 0x6c, 0x7e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrdmulh h10, h11, h12"
+
+  -
+    input:
+      bytes: [ 0xb4, 0xb6, 0xa2, 0x7e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrdmulh s20, s21, s2"
+
+  -
+    input:
+      bytes: [ 0xd4, 0x1e, 0x4f, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmulx h20, h22, h15"
+
+  -
+    input:
+      bytes: [ 0xd4, 0xde, 0x2f, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmulx s20, s22, s15"
+
+  -
+    input:
+      bytes: [ 0x77, 0xdd, 0x61, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmulx d23, d11, d1"
+
+  -
+    input:
+      bytes: [ 0x71, 0x93, 0x6c, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmlal s17, h27, h12"
+
+  -
+    input:
+      bytes: [ 0x13, 0x93, 0xac, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmlal d19, s24, s12"
+
+  -
+    input:
+      bytes: [ 0x8e, 0xb1, 0x79, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmlsl s14, h12, h25"
+
+  -
+    input:
+      bytes: [ 0xec, 0xb2, 0xad, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmlsl d12, s23, s13"
+
+  -
+    input:
+      bytes: [ 0xcc, 0xd2, 0x6c, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmull s12, h22, h12"
+
+  -
+    input:
+      bytes: [ 0xcf, 0xd2, 0xac, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdmull d15, s22, s12"
diff --git a/tests/MC/AArch64/neon-scalar-neg.s.yaml b/tests/MC/AArch64/neon-scalar-neg.s.yaml
new file mode 100644
index 000000000..832b9b6e7
--- /dev/null
+++ b/tests/MC/AArch64/neon-scalar-neg.s.yaml
@@ -0,0 +1,50 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x1d, 0xbb, 0xe0, 0x7e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "neg d29, d24"
+
+  -
+    input:
+      bytes: [ 0xd3, 0x79, 0x20, 0x7e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqneg b19, b14"
+
+  -
+    input:
+      bytes: [ 0xf5, 0x79, 0x60, 0x7e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqneg h21, h15"
+
+  -
+    input:
+      bytes: [ 0x94, 0x79, 0xa0, 0x7e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqneg s20, s12"
+
+  -
+    input:
+      bytes: [ 0x92, 0x79, 0xe0, 0x7e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqneg d18, d12"
diff --git a/tests/MC/AArch64/neon-scalar-recip.s.yaml b/tests/MC/AArch64/neon-scalar-recip.s.yaml
new file mode 100644
index 000000000..ef6d651b5
--- /dev/null
+++ b/tests/MC/AArch64/neon-scalar-recip.s.yaml
@@ -0,0 +1,150 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x15, 0x3e, 0x4d, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "frecps h21, h16, h13"
+
+  -
+    input:
+      bytes: [ 0x15, 0xfe, 0x2d, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "frecps s21, s16, s13"
+
+  -
+    input:
+      bytes: [ 0xd6, 0xff, 0x75, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "frecps d22, d30, d21"
+
+  -
+    input:
+      bytes: [ 0xb5, 0x3c, 0xcc, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "frsqrts h21, h5, h12"
+
+  -
+    input:
+      bytes: [ 0xb5, 0xfc, 0xac, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "frsqrts s21, s5, s12"
+
+  -
+    input:
+      bytes: [ 0xc8, 0xfe, 0xf2, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "frsqrts d8, d22, d18"
+
+  -
+    input:
+      bytes: [ 0xd3, 0xd9, 0xf9, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "frecpe h19, h14"
+
+  -
+    input:
+      bytes: [ 0xd3, 0xd9, 0xa1, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "frecpe s19, s14"
+
+  -
+    input:
+      bytes: [ 0xad, 0xd9, 0xe1, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "frecpe d13, d13"
+
+  -
+    input:
+      bytes: [ 0x52, 0xf9, 0xf9, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "frecpx h18, h10"
+
+  -
+    input:
+      bytes: [ 0x52, 0xf9, 0xa1, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "frecpx s18, s10"
+
+  -
+    input:
+      bytes: [ 0x70, 0xfa, 0xe1, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "frecpx d16, d19"
+
+  -
+    input:
+      bytes: [ 0xb6, 0xd9, 0xf9, 0x7e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "frsqrte h22, h13"
+
+  -
+    input:
+      bytes: [ 0xb6, 0xd9, 0xa1, 0x7e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "frsqrte s22, s13"
+
+  -
+    input:
+      bytes: [ 0x95, 0xd9, 0xe1, 0x7e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "frsqrte d21, d12"
diff --git a/tests/MC/AArch64/neon-scalar-reduce-pairwise.s.yaml b/tests/MC/AArch64/neon-scalar-reduce-pairwise.s.yaml
new file mode 100644
index 000000000..0e5195424
--- /dev/null
+++ b/tests/MC/AArch64/neon-scalar-reduce-pairwise.s.yaml
@@ -0,0 +1,50 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0xb8, 0xf1, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "addp d0, v1.2d"
+
+  -
+    input:
+      bytes: [ 0x72, 0xd8, 0x30, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "faddp h18, v3.2h"
+
+  -
+    input:
+      bytes: [ 0x72, 0xd8, 0x30, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "faddp h18, v3.2h"
+
+  -
+    input:
+      bytes: [ 0x53, 0xd8, 0x30, 0x7e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "faddp s19, v2.2s"
+
+  -
+    input:
+      bytes: [ 0x34, 0xd8, 0x70, 0x7e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "faddp d20, v1.2d"
diff --git a/tests/MC/AArch64/neon-scalar-rounding-shift.s.yaml b/tests/MC/AArch64/neon-scalar-rounding-shift.s.yaml
new file mode 100644
index 000000000..7c038ba02
--- /dev/null
+++ b/tests/MC/AArch64/neon-scalar-rounding-shift.s.yaml
@@ -0,0 +1,20 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xf1, 0x57, 0xe8, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshl d17, d31, d8"
+
+  -
+    input:
+      bytes: [ 0xf1, 0x57, 0xe8, 0x7e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshl d17, d31, d8"
diff --git a/tests/MC/AArch64/neon-scalar-saturating-add-sub.s.yaml b/tests/MC/AArch64/neon-scalar-saturating-add-sub.s.yaml
new file mode 100644
index 000000000..223b47d9a
--- /dev/null
+++ b/tests/MC/AArch64/neon-scalar-saturating-add-sub.s.yaml
@@ -0,0 +1,240 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x0c, 0x22, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqadd b0, b1, b2"
+
+  -
+    input:
+      bytes: [ 0x6a, 0x0d, 0x6c, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqadd h10, h11, h12"
+
+  -
+    input:
+      bytes: [ 0xb4, 0x0e, 0xa2, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqadd s20, s21, s2"
+
+  -
+    input:
+      bytes: [ 0xf1, 0x0f, 0xe8, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqadd d17, d31, d8"
+
+  -
+    input:
+      bytes: [ 0x20, 0x0c, 0x22, 0x7e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqadd b0, b1, b2"
+
+  -
+    input:
+      bytes: [ 0x6a, 0x0d, 0x6c, 0x7e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqadd h10, h11, h12"
+
+  -
+    input:
+      bytes: [ 0xb4, 0x0e, 0xa2, 0x7e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqadd s20, s21, s2"
+
+  -
+    input:
+      bytes: [ 0xf1, 0x0f, 0xe8, 0x7e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqadd d17, d31, d8"
+
+  -
+    input:
+      bytes: [ 0x20, 0x2c, 0x22, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqsub b0, b1, b2"
+
+  -
+    input:
+      bytes: [ 0x6a, 0x2d, 0x6c, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqsub h10, h11, h12"
+
+  -
+    input:
+      bytes: [ 0xb4, 0x2e, 0xa2, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqsub s20, s21, s2"
+
+  -
+    input:
+      bytes: [ 0xf1, 0x2f, 0xe8, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqsub d17, d31, d8"
+
+  -
+    input:
+      bytes: [ 0x20, 0x2c, 0x22, 0x7e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqsub b0, b1, b2"
+
+  -
+    input:
+      bytes: [ 0x6a, 0x2d, 0x6c, 0x7e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqsub h10, h11, h12"
+
+  -
+    input:
+      bytes: [ 0xb4, 0x2e, 0xa2, 0x7e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqsub s20, s21, s2"
+
+  -
+    input:
+      bytes: [ 0xf1, 0x2f, 0xe8, 0x7e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqsub d17, d31, d8"
+
+  -
+    input:
+      bytes: [ 0xd3, 0x39, 0x20, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "suqadd b19, b14"
+
+  -
+    input:
+      bytes: [ 0xf4, 0x39, 0x60, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "suqadd h20, h15"
+
+  -
+    input:
+      bytes: [ 0x95, 0x39, 0xa0, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "suqadd s21, s12"
+
+  -
+    input:
+      bytes: [ 0xd2, 0x3a, 0xe0, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "suqadd d18, d22"
+
+  -
+    input:
+      bytes: [ 0xd3, 0x39, 0x20, 0x7e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "usqadd b19, b14"
+
+  -
+    input:
+      bytes: [ 0xf4, 0x39, 0x60, 0x7e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "usqadd h20, h15"
+
+  -
+    input:
+      bytes: [ 0x95, 0x39, 0xa0, 0x7e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "usqadd s21, s12"
+
+  -
+    input:
+      bytes: [ 0xd2, 0x3a, 0xe0, 0x7e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "usqadd d18, d22"
diff --git a/tests/MC/AArch64/neon-scalar-saturating-rounding-shift.s.yaml b/tests/MC/AArch64/neon-scalar-saturating-rounding-shift.s.yaml
new file mode 100644
index 000000000..aa6da494e
--- /dev/null
+++ b/tests/MC/AArch64/neon-scalar-saturating-rounding-shift.s.yaml
@@ -0,0 +1,80 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x5c, 0x22, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshl b0, b1, b2"
+
+  -
+    input:
+      bytes: [ 0x6a, 0x5d, 0x6c, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshl h10, h11, h12"
+
+  -
+    input:
+      bytes: [ 0xb4, 0x5e, 0xa2, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshl s20, s21, s2"
+
+  -
+    input:
+      bytes: [ 0xf1, 0x5f, 0xe8, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshl d17, d31, d8"
+
+  -
+    input:
+      bytes: [ 0x20, 0x5c, 0x22, 0x7e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqrshl b0, b1, b2"
+
+  -
+    input:
+      bytes: [ 0x6a, 0x5d, 0x6c, 0x7e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqrshl h10, h11, h12"
+
+  -
+    input:
+      bytes: [ 0xb4, 0x5e, 0xa2, 0x7e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqrshl s20, s21, s2"
+
+  -
+    input:
+      bytes: [ 0xf1, 0x5f, 0xe8, 0x7e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqrshl d17, d31, d8"
diff --git a/tests/MC/AArch64/neon-scalar-saturating-shift.s.yaml b/tests/MC/AArch64/neon-scalar-saturating-shift.s.yaml
new file mode 100644
index 000000000..103005607
--- /dev/null
+++ b/tests/MC/AArch64/neon-scalar-saturating-shift.s.yaml
@@ -0,0 +1,80 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x4c, 0x22, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshl b0, b1, b2"
+
+  -
+    input:
+      bytes: [ 0x6a, 0x4d, 0x6c, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshl h10, h11, h12"
+
+  -
+    input:
+      bytes: [ 0xb4, 0x4e, 0xa2, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshl s20, s21, s2"
+
+  -
+    input:
+      bytes: [ 0xf1, 0x4f, 0xe8, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshl d17, d31, d8"
+
+  -
+    input:
+      bytes: [ 0x20, 0x4c, 0x22, 0x7e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqshl b0, b1, b2"
+
+  -
+    input:
+      bytes: [ 0x6a, 0x4d, 0x6c, 0x7e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqshl h10, h11, h12"
+
+  -
+    input:
+      bytes: [ 0xb4, 0x4e, 0xa2, 0x7e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqshl s20, s21, s2"
+
+  -
+    input:
+      bytes: [ 0xf1, 0x4f, 0xe8, 0x7e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqshl d17, d31, d8"
diff --git a/tests/MC/AArch64/neon-scalar-shift-imm.s.yaml b/tests/MC/AArch64/neon-scalar-shift-imm.s.yaml
new file mode 100644
index 000000000..c5aac3a69
--- /dev/null
+++ b/tests/MC/AArch64/neon-scalar-shift-imm.s.yaml
@@ -0,0 +1,410 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x0f, 0x06, 0x74, 0x5f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sshr d15, d16, #12"
+
+  -
+    input:
+      bytes: [ 0x2a, 0x06, 0x6e, 0x7f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ushr d10, d17, #18"
+
+  -
+    input:
+      bytes: [ 0x53, 0x26, 0x79, 0x5f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshr d19, d18, #7"
+
+  -
+    input:
+      bytes: [ 0xf4, 0x26, 0x61, 0x7f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshr d20, d23, #31"
+
+  -
+    input:
+      bytes: [ 0x92, 0x15, 0x6b, 0x5f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ssra d18, d12, #21"
+
+  -
+    input:
+      bytes: [ 0xb4, 0x15, 0x43, 0x7f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "usra d20, d13, #61"
+
+  -
+    input:
+      bytes: [ 0x6f, 0x35, 0x6d, 0x5f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "srsra d15, d11, #19"
+
+  -
+    input:
+      bytes: [ 0x52, 0x35, 0x73, 0x7f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ursra d18, d10, #13"
+
+  -
+    input:
+      bytes: [ 0x47, 0x55, 0x4c, 0x5f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "shl d7, d10, #12"
+
+  -
+    input:
+      bytes: [ 0x6b, 0x76, 0x0f, 0x5f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshl b11, b19, #7"
+
+  -
+    input:
+      bytes: [ 0x4d, 0x76, 0x1b, 0x5f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshl h13, h18, #11"
+
+  -
+    input:
+      bytes: [ 0x2e, 0x76, 0x36, 0x5f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshl s14, s17, #22"
+
+  -
+    input:
+      bytes: [ 0x0f, 0x76, 0x73, 0x5f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshl d15, d16, #51"
+
+  -
+    input:
+      bytes: [ 0xf2, 0x75, 0x0e, 0x7f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqshl b18, b15, #6"
+
+  -
+    input:
+      bytes: [ 0x4b, 0x76, 0x17, 0x7f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqshl h11, h18, #7"
+
+  -
+    input:
+      bytes: [ 0x6e, 0x76, 0x32, 0x7f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqshl s14, s19, #18"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x75, 0x53, 0x7f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqshl d15, d12, #19"
+
+  -
+    input:
+      bytes: [ 0x4f, 0x66, 0x0e, 0x7f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshlu b15, b18, #6"
+
+  -
+    input:
+      bytes: [ 0x33, 0x66, 0x16, 0x7f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshlu h19, h17, #6"
+
+  -
+    input:
+      bytes: [ 0xd0, 0x65, 0x39, 0x7f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshlu s16, s14, #25"
+
+  -
+    input:
+      bytes: [ 0xab, 0x65, 0x60, 0x7f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshlu d11, d13, #32"
+
+  -
+    input:
+      bytes: [ 0x8a, 0x45, 0x72, 0x7f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sri d10, d12, #14"
+
+  -
+    input:
+      bytes: [ 0xca, 0x55, 0x4c, 0x7f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sli d10, d14, #12"
+
+  -
+    input:
+      bytes: [ 0xea, 0x95, 0x0b, 0x5f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshrn b10, h15, #5"
+
+  -
+    input:
+      bytes: [ 0x51, 0x95, 0x1c, 0x5f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshrn h17, s10, #4"
+
+  -
+    input:
+      bytes: [ 0x52, 0x95, 0x21, 0x5f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshrn s18, d10, #31"
+
+  -
+    input:
+      bytes: [ 0x4c, 0x95, 0x09, 0x7f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqshrn b12, h10, #7"
+
+  -
+    input:
+      bytes: [ 0xca, 0x95, 0x1b, 0x7f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqshrn h10, s14, #5"
+
+  -
+    input:
+      bytes: [ 0x8a, 0x95, 0x33, 0x7f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqshrn s10, d12, #13"
+
+  -
+    input:
+      bytes: [ 0xaa, 0x9d, 0x0e, 0x5f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshrn b10, h13, #2"
+
+  -
+    input:
+      bytes: [ 0x4f, 0x9d, 0x1a, 0x5f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshrn h15, s10, #6"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x9d, 0x37, 0x5f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshrn s15, d12, #9"
+
+  -
+    input:
+      bytes: [ 0x8a, 0x9d, 0x0b, 0x7f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqrshrn b10, h12, #5"
+
+  -
+    input:
+      bytes: [ 0x4c, 0x9d, 0x12, 0x7f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqrshrn h12, s10, #14"
+
+  -
+    input:
+      bytes: [ 0x4a, 0x9d, 0x27, 0x7f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqrshrn s10, d10, #25"
+
+  -
+    input:
+      bytes: [ 0x4f, 0x85, 0x09, 0x7f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshrun b15, h10, #7"
+
+  -
+    input:
+      bytes: [ 0xd4, 0x85, 0x1d, 0x7f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshrun h20, s14, #3"
+
+  -
+    input:
+      bytes: [ 0xea, 0x85, 0x31, 0x7f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshrun s10, d15, #15"
+
+  -
+    input:
+      bytes: [ 0x51, 0x8d, 0x0a, 0x7f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshrun b17, h10, #6"
+
+  -
+    input:
+      bytes: [ 0xaa, 0x8d, 0x11, 0x7f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshrun h10, s13, #15"
+
+  -
+    input:
+      bytes: [ 0x16, 0x8e, 0x21, 0x7f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshrun s22, d16, #31"
diff --git a/tests/MC/AArch64/neon-scalar-shift.s.yaml b/tests/MC/AArch64/neon-scalar-shift.s.yaml
new file mode 100644
index 000000000..1550b5876
--- /dev/null
+++ b/tests/MC/AArch64/neon-scalar-shift.s.yaml
@@ -0,0 +1,20 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xf1, 0x47, 0xe8, 0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sshl d17, d31, d8"
+
+  -
+    input:
+      bytes: [ 0xf1, 0x47, 0xe8, 0x7e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ushl d17, d31, d8"
diff --git a/tests/MC/AArch64/neon-shift-left-long.s.yaml b/tests/MC/AArch64/neon-shift-left-long.s.yaml
new file mode 100644
index 000000000..f73fee2ac
--- /dev/null
+++ b/tests/MC/AArch64/neon-shift-left-long.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0xa4, 0x0b, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sshll v0.8h, v1.8b, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa4, 0x13, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sshll v0.4s, v1.4h, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa4, 0x23, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sshll v0.2d, v1.2s, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa4, 0x0b, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sshll2 v0.8h, v1.16b, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa4, 0x13, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sshll2 v0.4s, v1.8h, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa4, 0x23, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sshll2 v0.2d, v1.4s, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa4, 0x0b, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ushll v0.8h, v1.8b, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa4, 0x13, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ushll v0.4s, v1.4h, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa4, 0x23, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ushll v0.2d, v1.2s, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa4, 0x0b, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ushll2 v0.8h, v1.16b, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa4, 0x13, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ushll2 v0.4s, v1.8h, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa4, 0x23, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ushll2 v0.2d, v1.4s, #3"
diff --git a/tests/MC/AArch64/neon-shift.s.yaml b/tests/MC/AArch64/neon-shift.s.yaml
new file mode 100644
index 000000000..a66e644d4
--- /dev/null
+++ b/tests/MC/AArch64/neon-shift.s.yaml
@@ -0,0 +1,210 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x44, 0x22, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sshl v0.8b, v1.8b, v2.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x44, 0x22, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sshl v0.16b, v1.16b, v2.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x44, 0x62, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sshl v0.4h, v1.4h, v2.4h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x44, 0x62, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sshl v0.8h, v1.8h, v2.8h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x44, 0xa2, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sshl v0.2s, v1.2s, v2.2s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x44, 0xa2, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sshl v0.4s, v1.4s, v2.4s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x44, 0xe2, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sshl v0.2d, v1.2d, v2.2d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x44, 0x22, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ushl v0.8b, v1.8b, v2.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x44, 0x22, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ushl v0.16b, v1.16b, v2.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x44, 0x62, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ushl v0.4h, v1.4h, v2.4h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x44, 0x62, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ushl v0.8h, v1.8h, v2.8h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x44, 0xa2, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ushl v0.2s, v1.2s, v2.2s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x44, 0xa2, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ushl v0.4s, v1.4s, v2.4s"
+
+  -
+    input:
+      bytes: [ 0x20, 0x44, 0xe2, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ushl v0.2d, v1.2d, v2.2d"
+
+  -
+    input:
+      bytes: [ 0x20, 0x54, 0x0b, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "shl v0.8b, v1.8b, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x54, 0x13, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "shl v0.4h, v1.4h, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x54, 0x23, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "shl v0.2s, v1.2s, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x54, 0x0b, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "shl v0.16b, v1.16b, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x54, 0x13, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "shl v0.8h, v1.8h, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x54, 0x23, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "shl v0.4s, v1.4s, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x54, 0x43, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "shl v0.2d, v1.2d, #3"
diff --git a/tests/MC/AArch64/neon-simd-copy.s.yaml b/tests/MC/AArch64/neon-simd-copy.s.yaml
new file mode 100644
index 000000000..ff731d1f5
--- /dev/null
+++ b/tests/MC/AArch64/neon-simd-copy.s.yaml
@@ -0,0 +1,410 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x22, 0x1c, 0x05, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov v2.b[2], w1"
+
+  -
+    input:
+      bytes: [ 0xc7, 0x1d, 0x1e, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov v7.h[7], w14"
+
+  -
+    input:
+      bytes: [ 0xd4, 0x1f, 0x04, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov v20.s[0], w30"
+
+  -
+    input:
+      bytes: [ 0xe1, 0x1c, 0x18, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov v1.d[1], x7"
+
+  -
+    input:
+      bytes: [ 0x22, 0x1c, 0x05, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov v2.b[2], w1"
+
+  -
+    input:
+      bytes: [ 0xc7, 0x1d, 0x1e, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov v7.h[7], w14"
+
+  -
+    input:
+      bytes: [ 0xd4, 0x1f, 0x04, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov v20.s[0], w30"
+
+  -
+    input:
+      bytes: [ 0xe1, 0x1c, 0x18, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov v1.d[1], x7"
+
+  -
+    input:
+      bytes: [ 0x01, 0x2c, 0x1f, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "smov w1, v0.b[15]"
+
+  -
+    input:
+      bytes: [ 0xce, 0x2c, 0x12, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "smov w14, v6.h[4]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x2c, 0x1f, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "smov x1, v0.b[15]"
+
+  -
+    input:
+      bytes: [ 0xce, 0x2c, 0x12, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "smov x14, v6.h[4]"
+
+  -
+    input:
+      bytes: [ 0x34, 0x2d, 0x14, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "smov x20, v9.s[2]"
+
+  -
+    input:
+      bytes: [ 0x01, 0x3c, 0x1f, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "umov w1, v0.b[15]"
+
+  -
+    input:
+      bytes: [ 0xce, 0x3c, 0x12, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "umov w14, v6.h[4]"
+
+  -
+    input:
+      bytes: [ 0x34, 0x3d, 0x14, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov w20, v9.s[2]"
+
+  -
+    input:
+      bytes: [ 0x47, 0x3e, 0x18, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov x7, v18.d[1]"
+
+  -
+    input:
+      bytes: [ 0x34, 0x3d, 0x14, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov w20, v9.s[2]"
+
+  -
+    input:
+      bytes: [ 0x47, 0x3e, 0x18, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov x7, v18.d[1]"
+
+  -
+    input:
+      bytes: [ 0x61, 0x34, 0x1d, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov v1.b[14], v3.b[6]"
+
+  -
+    input:
+      bytes: [ 0xe6, 0x54, 0x1e, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov v6.h[7], v7.h[5]"
+
+  -
+    input:
+      bytes: [ 0xcf, 0x46, 0x1c, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov v15.s[3], v22.s[2]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x44, 0x08, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov v0.d[0], v4.d[1]"
+
+  -
+    input:
+      bytes: [ 0x61, 0x34, 0x1d, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov v1.b[14], v3.b[6]"
+
+  -
+    input:
+      bytes: [ 0xe6, 0x54, 0x1e, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov v6.h[7], v7.h[5]"
+
+  -
+    input:
+      bytes: [ 0xcf, 0x46, 0x1c, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov v15.s[3], v22.s[2]"
+
+  -
+    input:
+      bytes: [ 0x80, 0x44, 0x08, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov v0.d[0], v4.d[1]"
+
+  -
+    input:
+      bytes: [ 0x41, 0x04, 0x05, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "dup v1.8b, v2.b[2]"
+
+  -
+    input:
+      bytes: [ 0xeb, 0x04, 0x1e, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "dup v11.4h, v7.h[7]"
+
+  -
+    input:
+      bytes: [ 0x91, 0x06, 0x04, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "dup v17.2s, v20.s[0]"
+
+  -
+    input:
+      bytes: [ 0x41, 0x04, 0x05, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "dup v1.16b, v2.b[2]"
+
+  -
+    input:
+      bytes: [ 0xeb, 0x04, 0x1e, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "dup v11.8h, v7.h[7]"
+
+  -
+    input:
+      bytes: [ 0x91, 0x06, 0x04, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "dup v17.4s, v20.s[0]"
+
+  -
+    input:
+      bytes: [ 0x25, 0x04, 0x18, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "dup v5.2d, v1.d[1]"
+
+  -
+    input:
+      bytes: [ 0x21, 0x0c, 0x01, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "dup v1.8b, w1"
+
+  -
+    input:
+      bytes: [ 0xcb, 0x0d, 0x02, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "dup v11.4h, w14"
+
+  -
+    input:
+      bytes: [ 0xd1, 0x0f, 0x04, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "dup v17.2s, w30"
+
+  -
+    input:
+      bytes: [ 0x41, 0x0c, 0x01, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "dup v1.16b, w2"
+
+  -
+    input:
+      bytes: [ 0x0b, 0x0e, 0x02, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "dup v11.8h, w16"
+
+  -
+    input:
+      bytes: [ 0x91, 0x0f, 0x04, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "dup v17.4s, w28"
+
+  -
+    input:
+      bytes: [ 0x05, 0x0c, 0x08, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "dup v5.2d, x0"
diff --git a/tests/MC/AArch64/neon-simd-ldst-multi-elem.s.yaml b/tests/MC/AArch64/neon-simd-ldst-multi-elem.s.yaml
new file mode 100644
index 000000000..9b2b75e81
--- /dev/null
+++ b/tests/MC/AArch64/neon-simd-ldst-multi-elem.s.yaml
@@ -0,0 +1,1960 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x70, 0x00, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1 { v0.16b }, [x0]"
+
+  -
+    input:
+      bytes: [ 0xef, 0x75, 0x00, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1 { v15.8h }, [x15]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x7b, 0x00, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1 { v31.4s }, [sp]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x7c, 0x00, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1 { v0.2d }, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x70, 0x00, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1 { v0.8b }, [x0]"
+
+  -
+    input:
+      bytes: [ 0xef, 0x75, 0x00, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1 { v15.4h }, [x15]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x7b, 0x00, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1 { v31.2s }, [sp]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x7c, 0x00, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1 { v0.1d }, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x00, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1 { v0.16b, v1.16b }, [x0]"
+
+  -
+    input:
+      bytes: [ 0xef, 0xa5, 0x00, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1 { v15.8h, v16.8h }, [x15]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xab, 0x00, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1 { v31.4s, v0.4s }, [sp]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xac, 0x00, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1 { v0.2d, v1.2d }, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x00, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1 { v0.8b, v1.8b }, [x0]"
+
+  -
+    input:
+      bytes: [ 0xef, 0xa5, 0x00, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1 { v15.4h, v16.4h }, [x15]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xab, 0x00, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1 { v31.2s, v0.2s }, [sp]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xac, 0x00, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1 { v0.1d, v1.1d }, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x00, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1 { v0.16b, v1.16b }, [x0]"
+
+  -
+    input:
+      bytes: [ 0xef, 0xa5, 0x00, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1 { v15.8h, v16.8h }, [x15]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xab, 0x00, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1 { v31.4s, v0.4s }, [sp]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xac, 0x00, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1 { v0.2d, v1.2d }, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x00, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1 { v0.8b, v1.8b }, [x0]"
+
+  -
+    input:
+      bytes: [ 0xef, 0xa5, 0x00, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1 { v15.4h, v16.4h }, [x15]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xab, 0x00, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1 { v31.2s, v0.2s }, [sp]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xac, 0x00, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1 { v0.1d, v1.1d }, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0x00, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1 { v0.16b, v1.16b, v2.16b }, [x0]"
+
+  -
+    input:
+      bytes: [ 0xef, 0x65, 0x00, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1 { v15.8h, v16.8h, v17.8h }, [x15]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x6b, 0x00, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1 { v31.4s, v0.4s, v1.4s }, [sp]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x6c, 0x00, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1 { v0.2d, v1.2d, v2.2d }, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0x00, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1 { v0.8b, v1.8b, v2.8b }, [x0]"
+
+  -
+    input:
+      bytes: [ 0xef, 0x65, 0x00, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1 { v15.4h, v16.4h, v17.4h }, [x15]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x6b, 0x00, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1 { v31.2s, v0.2s, v1.2s }, [sp]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x6c, 0x00, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1 { v0.1d, v1.1d, v2.1d }, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0x00, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1 { v0.16b, v1.16b, v2.16b }, [x0]"
+
+  -
+    input:
+      bytes: [ 0xef, 0x65, 0x00, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1 { v15.8h, v16.8h, v17.8h }, [x15]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x6b, 0x00, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1 { v31.4s, v0.4s, v1.4s }, [sp]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x6c, 0x00, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1 { v0.2d, v1.2d, v2.2d }, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0x00, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1 { v0.8b, v1.8b, v2.8b }, [x0]"
+
+  -
+    input:
+      bytes: [ 0xef, 0x65, 0x00, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1 { v15.4h, v16.4h, v17.4h }, [x15]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x6b, 0x00, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1 { v31.2s, v0.2s, v1.2s }, [sp]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x6c, 0x00, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1 { v0.1d, v1.1d, v2.1d }, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x00, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1 { v0.16b, v1.16b, v2.16b, v3.16b }, [x0]"
+
+  -
+    input:
+      bytes: [ 0xef, 0x25, 0x00, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1 { v15.8h, v16.8h, v17.8h, v18.8h }, [x15]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x2b, 0x00, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1 { v31.4s, v0.4s, v1.4s, v2.4s }, [sp]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x2c, 0x00, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x00, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0]"
+
+  -
+    input:
+      bytes: [ 0xef, 0x25, 0x00, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1 { v15.4h, v16.4h, v17.4h, v18.4h }, [x15]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x2b, 0x00, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1 { v31.2s, v0.2s, v1.2s, v2.2s }, [sp]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x2c, 0x00, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1 { v0.1d, v1.1d, v2.1d, v3.1d }, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x00, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1 { v0.16b, v1.16b, v2.16b, v3.16b }, [x0]"
+
+  -
+    input:
+      bytes: [ 0xef, 0x25, 0x00, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1 { v15.8h, v16.8h, v17.8h, v18.8h }, [x15]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x2b, 0x00, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1 { v31.4s, v0.4s, v1.4s, v2.4s }, [sp]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x2c, 0x00, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x00, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0]"
+
+  -
+    input:
+      bytes: [ 0xef, 0x25, 0x00, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1 { v15.4h, v16.4h, v17.4h, v18.4h }, [x15]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x2b, 0x00, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1 { v31.2s, v0.2s, v1.2s, v2.2s }, [sp]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x2c, 0x00, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1 { v0.1d, v1.1d, v2.1d, v3.1d }, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x00, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st2 { v0.16b, v1.16b }, [x0]"
+
+  -
+    input:
+      bytes: [ 0xef, 0x85, 0x00, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st2 { v15.8h, v16.8h }, [x15]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x8b, 0x00, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st2 { v31.4s, v0.4s }, [sp]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x8c, 0x00, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st2 { v0.2d, v1.2d }, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x00, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st2 { v0.8b, v1.8b }, [x0]"
+
+  -
+    input:
+      bytes: [ 0xef, 0x85, 0x00, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st2 { v15.4h, v16.4h }, [x15]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x8b, 0x00, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st2 { v31.2s, v0.2s }, [sp]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x00, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st2 { v0.16b, v1.16b }, [x0]"
+
+  -
+    input:
+      bytes: [ 0xef, 0x85, 0x00, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st2 { v15.8h, v16.8h }, [x15]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x8b, 0x00, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st2 { v31.4s, v0.4s }, [sp]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x8c, 0x00, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st2 { v0.2d, v1.2d }, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x00, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st2 { v0.8b, v1.8b }, [x0]"
+
+  -
+    input:
+      bytes: [ 0xef, 0x85, 0x00, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st2 { v15.4h, v16.4h }, [x15]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x8b, 0x00, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st2 { v31.2s, v0.2s }, [sp]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0x00, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st3 { v0.16b, v1.16b, v2.16b }, [x0]"
+
+  -
+    input:
+      bytes: [ 0xef, 0x45, 0x00, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st3 { v15.8h, v16.8h, v17.8h }, [x15]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x4b, 0x00, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st3 { v31.4s, v0.4s, v1.4s }, [sp]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x4c, 0x00, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st3 { v0.2d, v1.2d, v2.2d }, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0x00, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st3 { v0.8b, v1.8b, v2.8b }, [x0]"
+
+  -
+    input:
+      bytes: [ 0xef, 0x45, 0x00, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st3 { v15.4h, v16.4h, v17.4h }, [x15]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x4b, 0x00, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st3 { v31.2s, v0.2s, v1.2s }, [sp]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0x00, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st3 { v0.16b, v1.16b, v2.16b }, [x0]"
+
+  -
+    input:
+      bytes: [ 0xef, 0x45, 0x00, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st3 { v15.8h, v16.8h, v17.8h }, [x15]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x4b, 0x00, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st3 { v31.4s, v0.4s, v1.4s }, [sp]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x4c, 0x00, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st3 { v0.2d, v1.2d, v2.2d }, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0x00, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st3 { v0.8b, v1.8b, v2.8b }, [x0]"
+
+  -
+    input:
+      bytes: [ 0xef, 0x45, 0x00, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st3 { v15.4h, v16.4h, v17.4h }, [x15]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x4b, 0x00, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st3 { v31.2s, v0.2s, v1.2s }, [sp]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x00, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x0]"
+
+  -
+    input:
+      bytes: [ 0xef, 0x05, 0x00, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st4 { v15.8h, v16.8h, v17.8h, v18.8h }, [x15]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x0b, 0x00, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st4 { v31.4s, v0.4s, v1.4s, v2.4s }, [sp]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x0c, 0x00, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st4 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x00, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st4 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0]"
+
+  -
+    input:
+      bytes: [ 0xef, 0x05, 0x00, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st4 { v15.4h, v16.4h, v17.4h, v18.4h }, [x15]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x0b, 0x00, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st4 { v31.2s, v0.2s, v1.2s, v2.2s }, [sp]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x00, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x0]"
+
+  -
+    input:
+      bytes: [ 0xef, 0x05, 0x00, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st4 { v15.8h, v16.8h, v17.8h, v18.8h }, [x15]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x0b, 0x00, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st4 { v31.4s, v0.4s, v1.4s, v2.4s }, [sp]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x0c, 0x00, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st4 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x00, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st4 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0]"
+
+  -
+    input:
+      bytes: [ 0xef, 0x05, 0x00, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st4 { v15.4h, v16.4h, v17.4h, v18.4h }, [x15]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x0b, 0x00, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st4 { v31.2s, v0.2s, v1.2s, v2.2s }, [sp]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x70, 0x40, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1 { v0.16b }, [x0]"
+
+  -
+    input:
+      bytes: [ 0xef, 0x75, 0x40, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1 { v15.8h }, [x15]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x7b, 0x40, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1 { v31.4s }, [sp]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x7c, 0x40, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1 { v0.2d }, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x70, 0x40, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1 { v0.8b }, [x0]"
+
+  -
+    input:
+      bytes: [ 0xef, 0x75, 0x40, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1 { v15.4h }, [x15]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x7b, 0x40, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1 { v31.2s }, [sp]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x7c, 0x40, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1 { v0.1d }, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x40, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1 { v0.16b, v1.16b }, [x0]"
+
+  -
+    input:
+      bytes: [ 0xef, 0xa5, 0x40, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1 { v15.8h, v16.8h }, [x15]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xab, 0x40, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1 { v31.4s, v0.4s }, [sp]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xac, 0x40, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1 { v0.2d, v1.2d }, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x40, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1 { v0.8b, v1.8b }, [x0]"
+
+  -
+    input:
+      bytes: [ 0xef, 0xa5, 0x40, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1 { v15.4h, v16.4h }, [x15]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xab, 0x40, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1 { v31.2s, v0.2s }, [sp]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xac, 0x40, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1 { v0.1d, v1.1d }, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x40, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1 { v0.16b, v1.16b }, [x0]"
+
+  -
+    input:
+      bytes: [ 0xef, 0xa5, 0x40, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1 { v15.8h, v16.8h }, [x15]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xab, 0x40, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1 { v31.4s, v0.4s }, [sp]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xac, 0x40, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1 { v0.2d, v1.2d }, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x40, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1 { v0.8b, v1.8b }, [x0]"
+
+  -
+    input:
+      bytes: [ 0xef, 0xa5, 0x40, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1 { v15.4h, v16.4h }, [x15]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xab, 0x40, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1 { v31.2s, v0.2s }, [sp]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xac, 0x40, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1 { v0.1d, v1.1d }, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0x40, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1 { v0.16b, v1.16b, v2.16b }, [x0]"
+
+  -
+    input:
+      bytes: [ 0xef, 0x65, 0x40, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1 { v15.8h, v16.8h, v17.8h }, [x15]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x6b, 0x40, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1 { v31.4s, v0.4s, v1.4s }, [sp]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x6c, 0x40, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1 { v0.2d, v1.2d, v2.2d }, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0x40, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1 { v0.8b, v1.8b, v2.8b }, [x0]"
+
+  -
+    input:
+      bytes: [ 0xef, 0x65, 0x40, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1 { v15.4h, v16.4h, v17.4h }, [x15]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x6b, 0x40, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1 { v31.2s, v0.2s, v1.2s }, [sp]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x6c, 0x40, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1 { v0.1d, v1.1d, v2.1d }, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0x40, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1 { v0.16b, v1.16b, v2.16b }, [x0]"
+
+  -
+    input:
+      bytes: [ 0xef, 0x65, 0x40, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1 { v15.8h, v16.8h, v17.8h }, [x15]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x6b, 0x40, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1 { v31.4s, v0.4s, v1.4s }, [sp]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x6c, 0x40, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1 { v0.2d, v1.2d, v2.2d }, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0x40, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1 { v0.8b, v1.8b, v2.8b }, [x0]"
+
+  -
+    input:
+      bytes: [ 0xef, 0x65, 0x40, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1 { v15.4h, v16.4h, v17.4h }, [x15]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x6b, 0x40, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1 { v31.2s, v0.2s, v1.2s }, [sp]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x6c, 0x40, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1 { v0.1d, v1.1d, v2.1d }, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x40, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1 { v0.16b, v1.16b, v2.16b, v3.16b }, [x0]"
+
+  -
+    input:
+      bytes: [ 0xef, 0x25, 0x40, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1 { v15.8h, v16.8h, v17.8h, v18.8h }, [x15]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x2b, 0x40, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1 { v31.4s, v0.4s, v1.4s, v2.4s }, [sp]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x2c, 0x40, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x40, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0]"
+
+  -
+    input:
+      bytes: [ 0xef, 0x25, 0x40, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1 { v15.4h, v16.4h, v17.4h, v18.4h }, [x15]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x2b, 0x40, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1 { v31.2s, v0.2s, v1.2s, v2.2s }, [sp]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x2c, 0x40, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1 { v0.1d, v1.1d, v2.1d, v3.1d }, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x40, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1 { v0.16b, v1.16b, v2.16b, v3.16b }, [x0]"
+
+  -
+    input:
+      bytes: [ 0xef, 0x25, 0x40, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1 { v15.8h, v16.8h, v17.8h, v18.8h }, [x15]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x2b, 0x40, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1 { v31.4s, v0.4s, v1.4s, v2.4s }, [sp]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x2c, 0x40, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x40, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0]"
+
+  -
+    input:
+      bytes: [ 0xef, 0x25, 0x40, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1 { v15.4h, v16.4h, v17.4h, v18.4h }, [x15]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x2b, 0x40, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1 { v31.2s, v0.2s, v1.2s, v2.2s }, [sp]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x2c, 0x40, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1 { v0.1d, v1.1d, v2.1d, v3.1d }, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x40, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld2 { v0.16b, v1.16b }, [x0]"
+
+  -
+    input:
+      bytes: [ 0xef, 0x85, 0x40, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld2 { v15.8h, v16.8h }, [x15]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x8b, 0x40, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld2 { v31.4s, v0.4s }, [sp]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x8c, 0x40, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld2 { v0.2d, v1.2d }, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x40, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld2 { v0.8b, v1.8b }, [x0]"
+
+  -
+    input:
+      bytes: [ 0xef, 0x85, 0x40, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld2 { v15.4h, v16.4h }, [x15]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x8b, 0x40, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld2 { v31.2s, v0.2s }, [sp]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x40, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld2 { v0.16b, v1.16b }, [x0]"
+
+  -
+    input:
+      bytes: [ 0xef, 0x85, 0x40, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld2 { v15.8h, v16.8h }, [x15]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x8b, 0x40, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld2 { v31.4s, v0.4s }, [sp]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x8c, 0x40, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld2 { v0.2d, v1.2d }, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x40, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld2 { v0.8b, v1.8b }, [x0]"
+
+  -
+    input:
+      bytes: [ 0xef, 0x85, 0x40, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld2 { v15.4h, v16.4h }, [x15]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x8b, 0x40, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld2 { v31.2s, v0.2s }, [sp]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0x40, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld3 { v0.16b, v1.16b, v2.16b }, [x0]"
+
+  -
+    input:
+      bytes: [ 0xef, 0x45, 0x40, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld3 { v15.8h, v16.8h, v17.8h }, [x15]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x4b, 0x40, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld3 { v31.4s, v0.4s, v1.4s }, [sp]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x4c, 0x40, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld3 { v0.2d, v1.2d, v2.2d }, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0x40, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld3 { v0.8b, v1.8b, v2.8b }, [x0]"
+
+  -
+    input:
+      bytes: [ 0xef, 0x45, 0x40, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld3 { v15.4h, v16.4h, v17.4h }, [x15]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x4b, 0x40, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld3 { v31.2s, v0.2s, v1.2s }, [sp]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0x40, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld3 { v0.16b, v1.16b, v2.16b }, [x0]"
+
+  -
+    input:
+      bytes: [ 0xef, 0x45, 0x40, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld3 { v15.8h, v16.8h, v17.8h }, [x15]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x4b, 0x40, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld3 { v31.4s, v0.4s, v1.4s }, [sp]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x4c, 0x40, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld3 { v0.2d, v1.2d, v2.2d }, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0x40, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld3 { v0.8b, v1.8b, v2.8b }, [x0]"
+
+  -
+    input:
+      bytes: [ 0xef, 0x45, 0x40, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld3 { v15.4h, v16.4h, v17.4h }, [x15]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x4b, 0x40, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld3 { v31.2s, v0.2s, v1.2s }, [sp]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x40, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x0]"
+
+  -
+    input:
+      bytes: [ 0xef, 0x05, 0x40, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld4 { v15.8h, v16.8h, v17.8h, v18.8h }, [x15]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x0b, 0x40, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld4 { v31.4s, v0.4s, v1.4s, v2.4s }, [sp]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x0c, 0x40, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld4 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x40, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld4 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0]"
+
+  -
+    input:
+      bytes: [ 0xef, 0x05, 0x40, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld4 { v15.4h, v16.4h, v17.4h, v18.4h }, [x15]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x0b, 0x40, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld4 { v31.2s, v0.2s, v1.2s, v2.2s }, [sp]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x40, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x0]"
+
+  -
+    input:
+      bytes: [ 0xef, 0x05, 0x40, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld4 { v15.8h, v16.8h, v17.8h, v18.8h }, [x15]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x0b, 0x40, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld4 { v31.4s, v0.4s, v1.4s, v2.4s }, [sp]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x0c, 0x40, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld4 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x40, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld4 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0]"
+
+  -
+    input:
+      bytes: [ 0xef, 0x05, 0x40, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld4 { v15.4h, v16.4h, v17.4h, v18.4h }, [x15]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x0b, 0x40, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld4 { v31.2s, v0.2s, v1.2s, v2.2s }, [sp]"
diff --git a/tests/MC/AArch64/neon-simd-ldst-one-elem.s.yaml b/tests/MC/AArch64/neon-simd-ldst-one-elem.s.yaml
new file mode 100644
index 000000000..8f3d115e3
--- /dev/null
+++ b/tests/MC/AArch64/neon-simd-ldst-one-elem.s.yaml
@@ -0,0 +1,1280 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x40, 0x4d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1r { v0.16b }, [x0]"
+
+  -
+    input:
+      bytes: [ 0xef, 0xc5, 0x40, 0x4d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1r { v15.8h }, [x15]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xcb, 0x40, 0x4d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1r { v31.4s }, [sp]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xcc, 0x40, 0x4d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1r { v0.2d }, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x40, 0x0d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1r { v0.8b }, [x0]"
+
+  -
+    input:
+      bytes: [ 0xef, 0xc5, 0x40, 0x0d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1r { v15.4h }, [x15]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xcb, 0x40, 0x0d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1r { v31.2s }, [sp]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xcc, 0x40, 0x0d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1r { v0.1d }, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x60, 0x4d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld2r { v0.16b, v1.16b }, [x0]"
+
+  -
+    input:
+      bytes: [ 0xef, 0xc5, 0x60, 0x4d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld2r { v15.8h, v16.8h }, [x15]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xcb, 0x60, 0x4d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld2r { v31.4s, v0.4s }, [sp]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xcc, 0x60, 0x4d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld2r { v0.2d, v1.2d }, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x60, 0x0d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld2r { v0.8b, v1.8b }, [x0]"
+
+  -
+    input:
+      bytes: [ 0xef, 0xc5, 0x60, 0x0d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld2r { v15.4h, v16.4h }, [x15]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xcb, 0x60, 0x0d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld2r { v31.2s, v0.2s }, [sp]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xcf, 0x60, 0x0d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld2r { v31.1d, v0.1d }, [sp]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x40, 0x4d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld3r { v0.16b, v1.16b, v2.16b }, [x0]"
+
+  -
+    input:
+      bytes: [ 0xef, 0xe5, 0x40, 0x4d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld3r { v15.8h, v16.8h, v17.8h }, [x15]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xeb, 0x40, 0x4d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld3r { v31.4s, v0.4s, v1.4s }, [sp]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xec, 0x40, 0x4d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld3r { v0.2d, v1.2d, v2.2d }, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x40, 0x0d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld3r { v0.8b, v1.8b, v2.8b }, [x0]"
+
+  -
+    input:
+      bytes: [ 0xef, 0xe5, 0x40, 0x0d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld3r { v15.4h, v16.4h, v17.4h }, [x15]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xeb, 0x40, 0x0d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld3r { v31.2s, v0.2s, v1.2s }, [sp]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xef, 0x40, 0x0d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld3r { v31.1d, v0.1d, v1.1d }, [sp]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x60, 0x4d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld4r { v0.16b, v1.16b, v2.16b, v3.16b }, [x0]"
+
+  -
+    input:
+      bytes: [ 0xef, 0xe5, 0x60, 0x4d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld4r { v15.8h, v16.8h, v17.8h, v18.8h }, [x15]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xeb, 0x60, 0x4d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld4r { v31.4s, v0.4s, v1.4s, v2.4s }, [sp]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xec, 0x60, 0x4d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld4r { v0.2d, v1.2d, v2.2d, v3.2d }, [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x60, 0x0d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld4r { v0.8b, v1.8b, v2.8b, v3.8b }, [x0]"
+
+  -
+    input:
+      bytes: [ 0xef, 0xe5, 0x60, 0x0d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld4r { v15.4h, v16.4h, v17.4h, v18.4h }, [x15]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xeb, 0x60, 0x0d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld4r { v31.2s, v0.2s, v1.2s, v2.2s }, [sp]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xef, 0x60, 0x0d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld4r { v31.1d, v0.1d, v1.1d, v2.1d }, [sp]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x04, 0x40, 0x4d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1 { v0.b }[9], [x0]"
+
+  -
+    input:
+      bytes: [ 0xef, 0x59, 0x40, 0x4d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1 { v15.h }[7], [x15]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x93, 0x40, 0x4d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1 { v31.s }[3], [sp]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x84, 0x40, 0x4d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1 { v0.d }[1], [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x04, 0x60, 0x4d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld2 { v0.b, v1.b }[9], [x0]"
+
+  -
+    input:
+      bytes: [ 0xef, 0x59, 0x60, 0x4d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld2 { v15.h, v16.h }[7], [x15]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x93, 0x60, 0x4d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld2 { v31.s, v0.s }[3], [sp]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x84, 0x60, 0x4d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld2 { v0.d, v1.d }[1], [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x24, 0x40, 0x4d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld3 { v0.b, v1.b, v2.b }[9], [x0]"
+
+  -
+    input:
+      bytes: [ 0xef, 0x79, 0x40, 0x4d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld3 { v15.h, v16.h, v17.h }[7], [x15]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xb3, 0x40, 0x4d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld3 { v31.s, v0.s, v1.s }[3], [sp]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa4, 0x40, 0x4d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld3 { v0.d, v1.d, v2.d }[1], [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x24, 0x60, 0x4d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld4 { v0.b, v1.b, v2.b, v3.b }[9], [x0]"
+
+  -
+    input:
+      bytes: [ 0xef, 0x79, 0x60, 0x4d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld4 { v15.h, v16.h, v17.h, v18.h }[7], [x15]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xb3, 0x60, 0x4d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld4 { v31.s, v0.s, v1.s, v2.s }[3], [sp]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa4, 0x60, 0x4d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld4 { v0.d, v1.d, v2.d, v3.d }[1], [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x04, 0x00, 0x4d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1 { v0.b }[9], [x0]"
+
+  -
+    input:
+      bytes: [ 0xef, 0x59, 0x00, 0x4d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1 { v15.h }[7], [x15]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x93, 0x00, 0x4d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1 { v31.s }[3], [sp]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x84, 0x00, 0x4d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1 { v0.d }[1], [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x04, 0x20, 0x4d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st2 { v0.b, v1.b }[9], [x0]"
+
+  -
+    input:
+      bytes: [ 0xef, 0x59, 0x20, 0x4d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st2 { v15.h, v16.h }[7], [x15]"
+
+  -
+    input:
+      bytes: [ 0xff, 0x93, 0x20, 0x4d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st2 { v31.s, v0.s }[3], [sp]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x84, 0x20, 0x4d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st2 { v0.d, v1.d }[1], [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x24, 0x00, 0x4d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st3 { v0.b, v1.b, v2.b }[9], [x0]"
+
+  -
+    input:
+      bytes: [ 0xef, 0x79, 0x00, 0x4d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st3 { v15.h, v16.h, v17.h }[7], [x15]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xb3, 0x00, 0x4d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st3 { v31.s, v0.s, v1.s }[3], [sp]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa4, 0x00, 0x4d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st3 { v0.d, v1.d, v2.d }[1], [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0x24, 0x20, 0x4d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st4 { v0.b, v1.b, v2.b, v3.b }[9], [x0]"
+
+  -
+    input:
+      bytes: [ 0xef, 0x79, 0x20, 0x4d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st4 { v15.h, v16.h, v17.h, v18.h }[7], [x15]"
+
+  -
+    input:
+      bytes: [ 0xff, 0xb3, 0x20, 0x4d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st4 { v31.s, v0.s, v1.s, v2.s }[3], [sp]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa4, 0x20, 0x4d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st4 { v0.d, v1.d, v2.d, v3.d }[1], [x0]"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0xdf, 0x4d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1r { v0.16b }, [x0], #1"
+
+  -
+    input:
+      bytes: [ 0xef, 0xc5, 0xdf, 0x4d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1r { v15.8h }, [x15], #2"
+
+  -
+    input:
+      bytes: [ 0xff, 0xcb, 0xdf, 0x4d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1r { v31.4s }, [sp], #4"
+
+  -
+    input:
+      bytes: [ 0x00, 0xcc, 0xdf, 0x4d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1r { v0.2d }, [x0], #8"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0xc0, 0x0d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1r { v0.8b }, [x0], x0"
+
+  -
+    input:
+      bytes: [ 0xef, 0xc5, 0xc1, 0x0d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1r { v15.4h }, [x15], x1"
+
+  -
+    input:
+      bytes: [ 0xff, 0xcb, 0xc2, 0x0d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1r { v31.2s }, [sp], x2"
+
+  -
+    input:
+      bytes: [ 0x00, 0xcc, 0xc3, 0x0d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1r { v0.1d }, [x0], x3"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0xff, 0x4d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld2r { v0.16b, v1.16b }, [x0], #2"
+
+  -
+    input:
+      bytes: [ 0xef, 0xc5, 0xff, 0x4d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld2r { v15.8h, v16.8h }, [x15], #4"
+
+  -
+    input:
+      bytes: [ 0xff, 0xcb, 0xff, 0x4d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld2r { v31.4s, v0.4s }, [sp], #8"
+
+  -
+    input:
+      bytes: [ 0x00, 0xcc, 0xff, 0x4d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld2r { v0.2d, v1.2d }, [x0], #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0xe6, 0x0d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld2r { v0.8b, v1.8b }, [x0], x6"
+
+  -
+    input:
+      bytes: [ 0xef, 0xc5, 0xe7, 0x0d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld2r { v15.4h, v16.4h }, [x15], x7"
+
+  -
+    input:
+      bytes: [ 0xff, 0xcb, 0xe9, 0x0d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld2r { v31.2s, v0.2s }, [sp], x9"
+
+  -
+    input:
+      bytes: [ 0x1f, 0xcc, 0xe5, 0x0d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld2r { v31.1d, v0.1d }, [x0], x5"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xc9, 0x4d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld3r { v0.16b, v1.16b, v2.16b }, [x0], x9"
+
+  -
+    input:
+      bytes: [ 0xef, 0xe5, 0xc6, 0x4d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld3r { v15.8h, v16.8h, v17.8h }, [x15], x6"
+
+  -
+    input:
+      bytes: [ 0xff, 0xeb, 0xc7, 0x4d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld3r { v31.4s, v0.4s, v1.4s }, [sp], x7"
+
+  -
+    input:
+      bytes: [ 0x00, 0xec, 0xc5, 0x4d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld3r { v0.2d, v1.2d, v2.2d }, [x0], x5"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xdf, 0x0d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld3r { v0.8b, v1.8b, v2.8b }, [x0], #3"
+
+  -
+    input:
+      bytes: [ 0xef, 0xe5, 0xdf, 0x0d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld3r { v15.4h, v16.4h, v17.4h }, [x15], #6"
+
+  -
+    input:
+      bytes: [ 0xff, 0xeb, 0xdf, 0x0d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld3r { v31.2s, v0.2s, v1.2s }, [sp], #12"
+
+  -
+    input:
+      bytes: [ 0xff, 0xef, 0xdf, 0x0d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld3r { v31.1d, v0.1d, v1.1d }, [sp], #24"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xff, 0x4d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld4r { v0.16b, v1.16b, v2.16b, v3.16b }, [x0], #4"
+
+  -
+    input:
+      bytes: [ 0xef, 0xe5, 0xff, 0x4d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld4r { v15.8h, v16.8h, v17.8h, v18.8h }, [x15], #8"
+
+  -
+    input:
+      bytes: [ 0xff, 0xeb, 0xff, 0x4d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld4r { v31.4s, v0.4s, v1.4s, v2.4s }, [sp], #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xec, 0xff, 0x4d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld4r { v0.2d, v1.2d, v2.2d, v3.2d }, [x0], #32"
+
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0xe5, 0x0d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld4r { v0.8b, v1.8b, v2.8b, v3.8b }, [x0], x5"
+
+  -
+    input:
+      bytes: [ 0xef, 0xe5, 0xe9, 0x0d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld4r { v15.4h, v16.4h, v17.4h, v18.4h }, [x15], x9"
+
+  -
+    input:
+      bytes: [ 0xff, 0xeb, 0xfe, 0x0d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld4r { v31.2s, v0.2s, v1.2s, v2.2s }, [sp], x30"
+
+  -
+    input:
+      bytes: [ 0xff, 0xef, 0xe7, 0x0d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld4r { v31.1d, v0.1d, v1.1d, v2.1d }, [sp], x7"
+
+  -
+    input:
+      bytes: [ 0x00, 0x04, 0xdf, 0x4d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1 { v0.b }[9], [x0], #1"
+
+  -
+    input:
+      bytes: [ 0xef, 0x59, 0xc9, 0x4d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1 { v15.h }[7], [x15], x9"
+
+  -
+    input:
+      bytes: [ 0xff, 0x93, 0xc6, 0x4d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1 { v31.s }[3], [sp], x6"
+
+  -
+    input:
+      bytes: [ 0x00, 0x84, 0xdf, 0x4d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1 { v0.d }[1], [x0], #8"
+
+  -
+    input:
+      bytes: [ 0x00, 0x04, 0xe3, 0x4d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld2 { v0.b, v1.b }[9], [x0], x3"
+
+  -
+    input:
+      bytes: [ 0xef, 0x59, 0xff, 0x4d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld2 { v15.h, v16.h }[7], [x15], #4"
+
+  -
+    input:
+      bytes: [ 0xff, 0x93, 0xff, 0x4d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld2 { v31.s, v0.s }[3], [sp], #8"
+
+  -
+    input:
+      bytes: [ 0x00, 0x84, 0xe0, 0x4d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld2 { v0.d, v1.d }[1], [x0], x0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x24, 0xdf, 0x4d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld3 { v0.b, v1.b, v2.b }[9], [x0], #3"
+
+  -
+    input:
+      bytes: [ 0xef, 0x79, 0xdf, 0x4d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld3 { v15.h, v16.h, v17.h }[7], [x15], #6"
+
+  -
+    input:
+      bytes: [ 0xff, 0xb3, 0xc3, 0x4d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld3 { v31.s, v0.s, v1.s }[3], [sp], x3"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa4, 0xc6, 0x4d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld3 { v0.d, v1.d, v2.d }[1], [x0], x6"
+
+  -
+    input:
+      bytes: [ 0x00, 0x24, 0xe5, 0x4d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld4 { v0.b, v1.b, v2.b, v3.b }[9], [x0], x5"
+
+  -
+    input:
+      bytes: [ 0xef, 0x79, 0xe7, 0x4d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld4 { v15.h, v16.h, v17.h, v18.h }[7], [x15], x7"
+
+  -
+    input:
+      bytes: [ 0xff, 0xb3, 0xff, 0x4d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld4 { v31.s, v0.s, v1.s, v2.s }[3], [sp], #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa4, 0xff, 0x4d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld4 { v0.d, v1.d, v2.d, v3.d }[1], [x0], #32"
+
+  -
+    input:
+      bytes: [ 0x00, 0x04, 0x9f, 0x4d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1 { v0.b }[9], [x0], #1"
+
+  -
+    input:
+      bytes: [ 0xef, 0x59, 0x89, 0x4d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1 { v15.h }[7], [x15], x9"
+
+  -
+    input:
+      bytes: [ 0xff, 0x93, 0x86, 0x4d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1 { v31.s }[3], [sp], x6"
+
+  -
+    input:
+      bytes: [ 0x00, 0x84, 0x9f, 0x4d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1 { v0.d }[1], [x0], #8"
+
+  -
+    input:
+      bytes: [ 0x00, 0x04, 0xa3, 0x4d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st2 { v0.b, v1.b }[9], [x0], x3"
+
+  -
+    input:
+      bytes: [ 0xef, 0x59, 0xbf, 0x4d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st2 { v15.h, v16.h }[7], [x15], #4"
+
+  -
+    input:
+      bytes: [ 0xff, 0x93, 0xbf, 0x4d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st2 { v31.s, v0.s }[3], [sp], #8"
+
+  -
+    input:
+      bytes: [ 0x00, 0x84, 0xa0, 0x4d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st2 { v0.d, v1.d }[1], [x0], x0"
+
+  -
+    input:
+      bytes: [ 0x00, 0x24, 0x9f, 0x4d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st3 { v0.b, v1.b, v2.b }[9], [x0], #3"
+
+  -
+    input:
+      bytes: [ 0xef, 0x79, 0x9f, 0x4d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st3 { v15.h, v16.h, v17.h }[7], [x15], #6"
+
+  -
+    input:
+      bytes: [ 0xff, 0xb3, 0x83, 0x4d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st3 { v31.s, v0.s, v1.s }[3], [sp], x3"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa4, 0x86, 0x4d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st3 { v0.d, v1.d, v2.d }[1], [x0], x6"
+
+  -
+    input:
+      bytes: [ 0x00, 0x24, 0xa5, 0x4d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st4 { v0.b, v1.b, v2.b, v3.b }[9], [x0], x5"
+
+  -
+    input:
+      bytes: [ 0xef, 0x79, 0xa7, 0x4d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st4 { v15.h, v16.h, v17.h, v18.h }[7], [x15], x7"
+
+  -
+    input:
+      bytes: [ 0xff, 0xb3, 0xbf, 0x4d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st4 { v31.s, v0.s, v1.s, v2.s }[3], [sp], #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa4, 0xbf, 0x4d ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st4 { v0.d, v1.d, v2.d, v3.d }[1], [x0], #32"
diff --git a/tests/MC/AArch64/neon-simd-misc.s.yaml b/tests/MC/AArch64/neon-simd-misc.s.yaml
new file mode 100644
index 000000000..d099696ff
--- /dev/null
+++ b/tests/MC/AArch64/neon-simd-misc.s.yaml
@@ -0,0 +1,2600 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xe0, 0x0b, 0x20, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "rev64 v0.16b, v31.16b"
+
+  -
+    input:
+      bytes: [ 0x82, 0x08, 0x60, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "rev64 v2.8h, v4.8h"
+
+  -
+    input:
+      bytes: [ 0x06, 0x09, 0xa0, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "rev64 v6.4s, v8.4s"
+
+  -
+    input:
+      bytes: [ 0x21, 0x09, 0x20, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "rev64 v1.8b, v9.8b"
+
+  -
+    input:
+      bytes: [ 0xad, 0x0a, 0x60, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "rev64 v13.4h, v21.4h"
+
+  -
+    input:
+      bytes: [ 0x04, 0x08, 0xa0, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "rev64 v4.2s, v0.2s"
+
+  -
+    input:
+      bytes: [ 0xfe, 0x0b, 0x20, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "rev32 v30.16b, v31.16b"
+
+  -
+    input:
+      bytes: [ 0xe4, 0x08, 0x60, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "rev32 v4.8h, v7.8h"
+
+  -
+    input:
+      bytes: [ 0x35, 0x08, 0x20, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "rev32 v21.8b, v1.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x09, 0x60, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "rev32 v0.4h, v9.4h"
+
+  -
+    input:
+      bytes: [ 0xfe, 0x1b, 0x20, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "rev16 v30.16b, v31.16b"
+
+  -
+    input:
+      bytes: [ 0x35, 0x18, 0x20, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "rev16 v21.8b, v1.8b"
+
+  -
+    input:
+      bytes: [ 0xa3, 0x2a, 0x20, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "saddlp v3.8h, v21.16b"
+
+  -
+    input:
+      bytes: [ 0xa8, 0x28, 0x20, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "saddlp v8.4h, v5.8b"
+
+  -
+    input:
+      bytes: [ 0x29, 0x28, 0x60, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "saddlp v9.4s, v1.8h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x28, 0x60, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "saddlp v0.2s, v1.4h"
+
+  -
+    input:
+      bytes: [ 0x8c, 0x28, 0xa0, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "saddlp v12.2d, v4.4s"
+
+  -
+    input:
+      bytes: [ 0x91, 0x2b, 0xa0, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "saddlp v17.1d, v28.2s"
+
+  -
+    input:
+      bytes: [ 0xa3, 0x2a, 0x20, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "uaddlp v3.8h, v21.16b"
+
+  -
+    input:
+      bytes: [ 0xa8, 0x28, 0x20, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "uaddlp v8.4h, v5.8b"
+
+  -
+    input:
+      bytes: [ 0x29, 0x28, 0x60, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "uaddlp v9.4s, v1.8h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x28, 0x60, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "uaddlp v0.2s, v1.4h"
+
+  -
+    input:
+      bytes: [ 0x8c, 0x28, 0xa0, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "uaddlp v12.2d, v4.4s"
+
+  -
+    input:
+      bytes: [ 0x91, 0x2b, 0xa0, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "uaddlp v17.1d, v28.2s"
+
+  -
+    input:
+      bytes: [ 0xa3, 0x6a, 0x20, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sadalp v3.8h, v21.16b"
+
+  -
+    input:
+      bytes: [ 0xa8, 0x68, 0x20, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sadalp v8.4h, v5.8b"
+
+  -
+    input:
+      bytes: [ 0x29, 0x68, 0x60, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sadalp v9.4s, v1.8h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x68, 0x60, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sadalp v0.2s, v1.4h"
+
+  -
+    input:
+      bytes: [ 0x8c, 0x68, 0xa0, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sadalp v12.2d, v4.4s"
+
+  -
+    input:
+      bytes: [ 0x91, 0x6b, 0xa0, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sadalp v17.1d, v28.2s"
+
+  -
+    input:
+      bytes: [ 0xa3, 0x6a, 0x20, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "uadalp v3.8h, v21.16b"
+
+  -
+    input:
+      bytes: [ 0xa8, 0x68, 0x20, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "uadalp v8.4h, v5.8b"
+
+  -
+    input:
+      bytes: [ 0x29, 0x68, 0x60, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "uadalp v9.4s, v1.8h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x68, 0x60, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "uadalp v0.2s, v1.4h"
+
+  -
+    input:
+      bytes: [ 0x8c, 0x68, 0xa0, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "uadalp v12.2d, v4.4s"
+
+  -
+    input:
+      bytes: [ 0x91, 0x6b, 0xa0, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "uadalp v17.1d, v28.2s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3b, 0x20, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "suqadd v0.16b, v31.16b"
+
+  -
+    input:
+      bytes: [ 0x82, 0x38, 0x60, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "suqadd v2.8h, v4.8h"
+
+  -
+    input:
+      bytes: [ 0x06, 0x39, 0xa0, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "suqadd v6.4s, v8.4s"
+
+  -
+    input:
+      bytes: [ 0x06, 0x39, 0xe0, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "suqadd v6.2d, v8.2d"
+
+  -
+    input:
+      bytes: [ 0x21, 0x39, 0x20, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "suqadd v1.8b, v9.8b"
+
+  -
+    input:
+      bytes: [ 0xad, 0x3a, 0x60, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "suqadd v13.4h, v21.4h"
+
+  -
+    input:
+      bytes: [ 0x04, 0x38, 0xa0, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "suqadd v4.2s, v0.2s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3b, 0x20, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "usqadd v0.16b, v31.16b"
+
+  -
+    input:
+      bytes: [ 0x82, 0x38, 0x60, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "usqadd v2.8h, v4.8h"
+
+  -
+    input:
+      bytes: [ 0x06, 0x39, 0xa0, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "usqadd v6.4s, v8.4s"
+
+  -
+    input:
+      bytes: [ 0x06, 0x39, 0xe0, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "usqadd v6.2d, v8.2d"
+
+  -
+    input:
+      bytes: [ 0x21, 0x39, 0x20, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "usqadd v1.8b, v9.8b"
+
+  -
+    input:
+      bytes: [ 0xad, 0x3a, 0x60, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "usqadd v13.4h, v21.4h"
+
+  -
+    input:
+      bytes: [ 0x04, 0x38, 0xa0, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "usqadd v4.2s, v0.2s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x7b, 0x20, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqabs v0.16b, v31.16b"
+
+  -
+    input:
+      bytes: [ 0x82, 0x78, 0x60, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqabs v2.8h, v4.8h"
+
+  -
+    input:
+      bytes: [ 0x06, 0x79, 0xa0, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqabs v6.4s, v8.4s"
+
+  -
+    input:
+      bytes: [ 0x06, 0x79, 0xe0, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqabs v6.2d, v8.2d"
+
+  -
+    input:
+      bytes: [ 0x21, 0x79, 0x20, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqabs v1.8b, v9.8b"
+
+  -
+    input:
+      bytes: [ 0xad, 0x7a, 0x60, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqabs v13.4h, v21.4h"
+
+  -
+    input:
+      bytes: [ 0x04, 0x78, 0xa0, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqabs v4.2s, v0.2s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x7b, 0x20, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqneg v0.16b, v31.16b"
+
+  -
+    input:
+      bytes: [ 0x82, 0x78, 0x60, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqneg v2.8h, v4.8h"
+
+  -
+    input:
+      bytes: [ 0x06, 0x79, 0xa0, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqneg v6.4s, v8.4s"
+
+  -
+    input:
+      bytes: [ 0x06, 0x79, 0xe0, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqneg v6.2d, v8.2d"
+
+  -
+    input:
+      bytes: [ 0x21, 0x79, 0x20, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqneg v1.8b, v9.8b"
+
+  -
+    input:
+      bytes: [ 0xad, 0x7a, 0x60, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqneg v13.4h, v21.4h"
+
+  -
+    input:
+      bytes: [ 0x04, 0x78, 0xa0, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqneg v4.2s, v0.2s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbb, 0x20, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "abs v0.16b, v31.16b"
+
+  -
+    input:
+      bytes: [ 0x82, 0xb8, 0x60, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "abs v2.8h, v4.8h"
+
+  -
+    input:
+      bytes: [ 0x06, 0xb9, 0xa0, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "abs v6.4s, v8.4s"
+
+  -
+    input:
+      bytes: [ 0x06, 0xb9, 0xe0, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "abs v6.2d, v8.2d"
+
+  -
+    input:
+      bytes: [ 0x21, 0xb9, 0x20, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "abs v1.8b, v9.8b"
+
+  -
+    input:
+      bytes: [ 0xad, 0xba, 0x60, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "abs v13.4h, v21.4h"
+
+  -
+    input:
+      bytes: [ 0x04, 0xb8, 0xa0, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "abs v4.2s, v0.2s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0xbb, 0x20, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "neg v0.16b, v31.16b"
+
+  -
+    input:
+      bytes: [ 0x82, 0xb8, 0x60, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "neg v2.8h, v4.8h"
+
+  -
+    input:
+      bytes: [ 0x06, 0xb9, 0xa0, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "neg v6.4s, v8.4s"
+
+  -
+    input:
+      bytes: [ 0x06, 0xb9, 0xe0, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "neg v6.2d, v8.2d"
+
+  -
+    input:
+      bytes: [ 0x21, 0xb9, 0x20, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "neg v1.8b, v9.8b"
+
+  -
+    input:
+      bytes: [ 0xad, 0xba, 0x60, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "neg v13.4h, v21.4h"
+
+  -
+    input:
+      bytes: [ 0x04, 0xb8, 0xa0, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "neg v4.2s, v0.2s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x4b, 0x20, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "cls v0.16b, v31.16b"
+
+  -
+    input:
+      bytes: [ 0x82, 0x48, 0x60, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "cls v2.8h, v4.8h"
+
+  -
+    input:
+      bytes: [ 0x06, 0x49, 0xa0, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "cls v6.4s, v8.4s"
+
+  -
+    input:
+      bytes: [ 0x21, 0x49, 0x20, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "cls v1.8b, v9.8b"
+
+  -
+    input:
+      bytes: [ 0xad, 0x4a, 0x60, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "cls v13.4h, v21.4h"
+
+  -
+    input:
+      bytes: [ 0x04, 0x48, 0xa0, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "cls v4.2s, v0.2s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x4b, 0x20, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "clz v0.16b, v31.16b"
+
+  -
+    input:
+      bytes: [ 0x82, 0x48, 0x60, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "clz v2.8h, v4.8h"
+
+  -
+    input:
+      bytes: [ 0x06, 0x49, 0xa0, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "clz v6.4s, v8.4s"
+
+  -
+    input:
+      bytes: [ 0x21, 0x49, 0x20, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "clz v1.8b, v9.8b"
+
+  -
+    input:
+      bytes: [ 0xad, 0x4a, 0x60, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "clz v13.4h, v21.4h"
+
+  -
+    input:
+      bytes: [ 0x04, 0x48, 0xa0, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "clz v4.2s, v0.2s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x5b, 0x20, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "cnt v0.16b, v31.16b"
+
+  -
+    input:
+      bytes: [ 0x21, 0x59, 0x20, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "cnt v1.8b, v9.8b"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x5b, 0x20, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "mvn v0.16b, v31.16b"
+
+  -
+    input:
+      bytes: [ 0x21, 0x59, 0x20, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "mvn v1.8b, v9.8b"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x5b, 0x60, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "rbit v0.16b, v31.16b"
+
+  -
+    input:
+      bytes: [ 0x21, 0x59, 0x60, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "rbit v1.8b, v9.8b"
+
+  -
+    input:
+      bytes: [ 0x04, 0xf8, 0xf8, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fabs v4.4h, v0.4h"
+
+  -
+    input:
+      bytes: [ 0x06, 0xf9, 0xf8, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fabs v6.8h, v8.8h"
+
+  -
+    input:
+      bytes: [ 0x06, 0xf9, 0xa0, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fabs v6.4s, v8.4s"
+
+  -
+    input:
+      bytes: [ 0x06, 0xf9, 0xe0, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fabs v6.2d, v8.2d"
+
+  -
+    input:
+      bytes: [ 0x04, 0xf8, 0xa0, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fabs v4.2s, v0.2s"
+
+  -
+    input:
+      bytes: [ 0x04, 0xf8, 0xf8, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fneg v4.4h, v0.4h"
+
+  -
+    input:
+      bytes: [ 0x06, 0xf9, 0xf8, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fneg v6.8h, v8.8h"
+
+  -
+    input:
+      bytes: [ 0x06, 0xf9, 0xa0, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fneg v6.4s, v8.4s"
+
+  -
+    input:
+      bytes: [ 0x06, 0xf9, 0xe0, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fneg v6.2d, v8.2d"
+
+  -
+    input:
+      bytes: [ 0x04, 0xf8, 0xa0, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fneg v4.2s, v0.2s"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x2b, 0x21, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "xtn2 v0.16b, v31.8h"
+
+  -
+    input:
+      bytes: [ 0x82, 0x28, 0x61, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "xtn2 v2.8h, v4.4s"
+
+  -
+    input:
+      bytes: [ 0x06, 0x29, 0xa1, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "xtn2 v6.4s, v8.2d"
+
+  -
+    input:
+      bytes: [ 0x21, 0x29, 0x21, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "xtn v1.8b, v9.8h"
+
+  -
+    input:
+      bytes: [ 0xad, 0x2a, 0x61, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "xtn v13.4h, v21.4s"
+
+  -
+    input:
+      bytes: [ 0x04, 0x28, 0xa1, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "xtn v4.2s, v0.2d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x2b, 0x21, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqxtun2 v0.16b, v31.8h"
+
+  -
+    input:
+      bytes: [ 0x82, 0x28, 0x61, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqxtun2 v2.8h, v4.4s"
+
+  -
+    input:
+      bytes: [ 0x06, 0x29, 0xa1, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqxtun2 v6.4s, v8.2d"
+
+  -
+    input:
+      bytes: [ 0x21, 0x29, 0x21, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqxtun v1.8b, v9.8h"
+
+  -
+    input:
+      bytes: [ 0xad, 0x2a, 0x61, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqxtun v13.4h, v21.4s"
+
+  -
+    input:
+      bytes: [ 0x04, 0x28, 0xa1, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqxtun v4.2s, v0.2d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x4b, 0x21, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqxtn2 v0.16b, v31.8h"
+
+  -
+    input:
+      bytes: [ 0x82, 0x48, 0x61, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqxtn2 v2.8h, v4.4s"
+
+  -
+    input:
+      bytes: [ 0x06, 0x49, 0xa1, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqxtn2 v6.4s, v8.2d"
+
+  -
+    input:
+      bytes: [ 0x21, 0x49, 0x21, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqxtn v1.8b, v9.8h"
+
+  -
+    input:
+      bytes: [ 0xad, 0x4a, 0x61, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqxtn v13.4h, v21.4s"
+
+  -
+    input:
+      bytes: [ 0x04, 0x48, 0xa1, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqxtn v4.2s, v0.2d"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x4b, 0x21, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqxtn2 v0.16b, v31.8h"
+
+  -
+    input:
+      bytes: [ 0x82, 0x48, 0x61, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqxtn2 v2.8h, v4.4s"
+
+  -
+    input:
+      bytes: [ 0x06, 0x49, 0xa1, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqxtn2 v6.4s, v8.2d"
+
+  -
+    input:
+      bytes: [ 0x21, 0x49, 0x21, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqxtn v1.8b, v9.8h"
+
+  -
+    input:
+      bytes: [ 0xad, 0x4a, 0x61, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqxtn v13.4h, v21.4s"
+
+  -
+    input:
+      bytes: [ 0x04, 0x48, 0xa1, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqxtn v4.2s, v0.2d"
+
+  -
+    input:
+      bytes: [ 0x82, 0x38, 0x21, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "shll2 v2.8h, v4.16b, #8"
+
+  -
+    input:
+      bytes: [ 0x06, 0x39, 0x61, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "shll2 v6.4s, v8.8h, #16"
+
+  -
+    input:
+      bytes: [ 0x06, 0x39, 0xa1, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "shll2 v6.2d, v8.4s, #32"
+
+  -
+    input:
+      bytes: [ 0x82, 0x38, 0x21, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "shll v2.8h, v4.8b, #8"
+
+  -
+    input:
+      bytes: [ 0x06, 0x39, 0x61, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "shll v6.4s, v8.4h, #16"
+
+  -
+    input:
+      bytes: [ 0x06, 0x39, 0xa1, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "shll v6.2d, v8.2s, #32"
+
+  -
+    input:
+      bytes: [ 0x82, 0x68, 0x21, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtn2 v2.8h, v4.4s"
+
+  -
+    input:
+      bytes: [ 0x06, 0x69, 0x61, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtn2 v6.4s, v8.2d"
+
+  -
+    input:
+      bytes: [ 0xad, 0x6a, 0x21, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtn v13.4h, v21.4s"
+
+  -
+    input:
+      bytes: [ 0x04, 0x68, 0x61, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtn v4.2s, v0.2d"
+
+  -
+    input:
+      bytes: [ 0x06, 0x69, 0x61, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtxn2 v6.4s, v8.2d"
+
+  -
+    input:
+      bytes: [ 0x04, 0x68, 0x61, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtxn v4.2s, v0.2d"
+
+  -
+    input:
+      bytes: [ 0x29, 0x78, 0x21, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtl v9.4s, v1.4h"
+
+  -
+    input:
+      bytes: [ 0x20, 0x78, 0x61, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtl v0.2d, v1.2s"
+
+  -
+    input:
+      bytes: [ 0x8c, 0x78, 0x21, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtl2 v12.4s, v4.8h"
+
+  -
+    input:
+      bytes: [ 0x91, 0x7b, 0x61, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtl2 v17.2d, v28.4s"
+
+  -
+    input:
+      bytes: [ 0x04, 0x88, 0x79, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "frintn v4.4h, v0.4h"
+
+  -
+    input:
+      bytes: [ 0x06, 0x89, 0x79, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "frintn v6.8h, v8.8h"
+
+  -
+    input:
+      bytes: [ 0x06, 0x89, 0x21, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "frintn v6.4s, v8.4s"
+
+  -
+    input:
+      bytes: [ 0x06, 0x89, 0x61, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "frintn v6.2d, v8.2d"
+
+  -
+    input:
+      bytes: [ 0x04, 0x88, 0x21, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "frintn v4.2s, v0.2s"
+
+  -
+    input:
+      bytes: [ 0x04, 0x88, 0x79, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "frinta v4.4h, v0.4h"
+
+  -
+    input:
+      bytes: [ 0x06, 0x89, 0x79, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "frinta v6.8h, v8.8h"
+
+  -
+    input:
+      bytes: [ 0x06, 0x89, 0x21, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "frinta v6.4s, v8.4s"
+
+  -
+    input:
+      bytes: [ 0x06, 0x89, 0x61, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "frinta v6.2d, v8.2d"
+
+  -
+    input:
+      bytes: [ 0x04, 0x88, 0x21, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "frinta v4.2s, v0.2s"
+
+  -
+    input:
+      bytes: [ 0x04, 0x88, 0xf9, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "frintp v4.4h, v0.4h"
+
+  -
+    input:
+      bytes: [ 0x06, 0x89, 0xf9, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "frintp v6.8h, v8.8h"
+
+  -
+    input:
+      bytes: [ 0x06, 0x89, 0xa1, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "frintp v6.4s, v8.4s"
+
+  -
+    input:
+      bytes: [ 0x06, 0x89, 0xe1, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "frintp v6.2d, v8.2d"
+
+  -
+    input:
+      bytes: [ 0x04, 0x88, 0xa1, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "frintp v4.2s, v0.2s"
+
+  -
+    input:
+      bytes: [ 0x04, 0x98, 0x79, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "frintm v4.4h, v0.4h"
+
+  -
+    input:
+      bytes: [ 0x06, 0x99, 0x79, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "frintm v6.8h, v8.8h"
+
+  -
+    input:
+      bytes: [ 0x06, 0x99, 0x21, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "frintm v6.4s, v8.4s"
+
+  -
+    input:
+      bytes: [ 0x06, 0x99, 0x61, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "frintm v6.2d, v8.2d"
+
+  -
+    input:
+      bytes: [ 0x04, 0x98, 0x21, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "frintm v4.2s, v0.2s"
+
+  -
+    input:
+      bytes: [ 0x04, 0x98, 0x79, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "frintx v4.4h, v0.4h"
+
+  -
+    input:
+      bytes: [ 0x06, 0x99, 0x79, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "frintx v6.8h, v8.8h"
+
+  -
+    input:
+      bytes: [ 0x06, 0x99, 0x21, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "frintx v6.4s, v8.4s"
+
+  -
+    input:
+      bytes: [ 0x06, 0x99, 0x61, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "frintx v6.2d, v8.2d"
+
+  -
+    input:
+      bytes: [ 0x04, 0x98, 0x21, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "frintx v4.2s, v0.2s"
+
+  -
+    input:
+      bytes: [ 0x04, 0x98, 0xf9, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "frintz v4.4h, v0.4h"
+
+  -
+    input:
+      bytes: [ 0x06, 0x99, 0xf9, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "frintz v6.8h, v8.8h"
+
+  -
+    input:
+      bytes: [ 0x06, 0x99, 0xa1, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "frintz v6.4s, v8.4s"
+
+  -
+    input:
+      bytes: [ 0x06, 0x99, 0xe1, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "frintz v6.2d, v8.2d"
+
+  -
+    input:
+      bytes: [ 0x04, 0x98, 0xa1, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "frintz v4.2s, v0.2s"
+
+  -
+    input:
+      bytes: [ 0x04, 0x98, 0xf9, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "frinti v4.4h, v0.4h"
+
+  -
+    input:
+      bytes: [ 0x06, 0x99, 0xf9, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "frinti v6.8h, v8.8h"
+
+  -
+    input:
+      bytes: [ 0x06, 0x99, 0xa1, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "frinti v6.4s, v8.4s"
+
+  -
+    input:
+      bytes: [ 0x06, 0x99, 0xe1, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "frinti v6.2d, v8.2d"
+
+  -
+    input:
+      bytes: [ 0x04, 0x98, 0xa1, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "frinti v4.2s, v0.2s"
+
+  -
+    input:
+      bytes: [ 0x04, 0xa8, 0x79, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtns v4.4h, v0.4h"
+
+  -
+    input:
+      bytes: [ 0x06, 0xa9, 0x79, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtns v6.8h, v8.8h"
+
+  -
+    input:
+      bytes: [ 0x06, 0xa9, 0x21, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtns v6.4s, v8.4s"
+
+  -
+    input:
+      bytes: [ 0x06, 0xa9, 0x61, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtns v6.2d, v8.2d"
+
+  -
+    input:
+      bytes: [ 0x04, 0xa8, 0x21, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtns v4.2s, v0.2s"
+
+  -
+    input:
+      bytes: [ 0x04, 0xa8, 0x79, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtnu v4.4h, v0.4h"
+
+  -
+    input:
+      bytes: [ 0x06, 0xa9, 0x79, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtnu v6.8h, v8.8h"
+
+  -
+    input:
+      bytes: [ 0x06, 0xa9, 0x21, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtnu v6.4s, v8.4s"
+
+  -
+    input:
+      bytes: [ 0x06, 0xa9, 0x61, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtnu v6.2d, v8.2d"
+
+  -
+    input:
+      bytes: [ 0x04, 0xa8, 0x21, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtnu v4.2s, v0.2s"
+
+  -
+    input:
+      bytes: [ 0x04, 0xa8, 0xf9, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtps v4.4h, v0.4h"
+
+  -
+    input:
+      bytes: [ 0x06, 0xa9, 0xf9, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtps v6.8h, v8.8h"
+
+  -
+    input:
+      bytes: [ 0x06, 0xa9, 0xa1, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtps v6.4s, v8.4s"
+
+  -
+    input:
+      bytes: [ 0x06, 0xa9, 0xe1, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtps v6.2d, v8.2d"
+
+  -
+    input:
+      bytes: [ 0x04, 0xa8, 0xa1, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtps v4.2s, v0.2s"
+
+  -
+    input:
+      bytes: [ 0x04, 0xa8, 0xf9, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtpu v4.4h, v0.4h"
+
+  -
+    input:
+      bytes: [ 0x06, 0xa9, 0xf9, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtpu v6.8h, v8.8h"
+
+  -
+    input:
+      bytes: [ 0x06, 0xa9, 0xa1, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtpu v6.4s, v8.4s"
+
+  -
+    input:
+      bytes: [ 0x06, 0xa9, 0xe1, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtpu v6.2d, v8.2d"
+
+  -
+    input:
+      bytes: [ 0x04, 0xa8, 0xa1, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtpu v4.2s, v0.2s"
+
+  -
+    input:
+      bytes: [ 0x04, 0xb8, 0x79, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtms v4.4h, v0.4h"
+
+  -
+    input:
+      bytes: [ 0x06, 0xb9, 0x79, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtms v6.8h, v8.8h"
+
+  -
+    input:
+      bytes: [ 0x06, 0xb9, 0x21, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtms v6.4s, v8.4s"
+
+  -
+    input:
+      bytes: [ 0x06, 0xb9, 0x61, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtms v6.2d, v8.2d"
+
+  -
+    input:
+      bytes: [ 0x04, 0xb8, 0x21, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtms v4.2s, v0.2s"
+
+  -
+    input:
+      bytes: [ 0x04, 0xb8, 0x79, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtmu v4.4h, v0.4h"
+
+  -
+    input:
+      bytes: [ 0x06, 0xb9, 0x79, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtmu v6.8h, v8.8h"
+
+  -
+    input:
+      bytes: [ 0x06, 0xb9, 0x21, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtmu v6.4s, v8.4s"
+
+  -
+    input:
+      bytes: [ 0x06, 0xb9, 0x61, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtmu v6.2d, v8.2d"
+
+  -
+    input:
+      bytes: [ 0x04, 0xb8, 0x21, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtmu v4.2s, v0.2s"
+
+  -
+    input:
+      bytes: [ 0x04, 0xb8, 0xf9, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtzs v4.4h, v0.4h"
+
+  -
+    input:
+      bytes: [ 0x06, 0xb9, 0xf9, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtzs v6.8h, v8.8h"
+
+  -
+    input:
+      bytes: [ 0x06, 0xb9, 0xa1, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtzs v6.4s, v8.4s"
+
+  -
+    input:
+      bytes: [ 0x06, 0xb9, 0xe1, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtzs v6.2d, v8.2d"
+
+  -
+    input:
+      bytes: [ 0x04, 0xb8, 0xa1, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtzs v4.2s, v0.2s"
+
+  -
+    input:
+      bytes: [ 0x04, 0xb8, 0xf9, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtzu v4.4h, v0.4h"
+
+  -
+    input:
+      bytes: [ 0x06, 0xb9, 0xf9, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtzu v6.8h, v8.8h"
+
+  -
+    input:
+      bytes: [ 0x06, 0xb9, 0xa1, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtzu v6.4s, v8.4s"
+
+  -
+    input:
+      bytes: [ 0x06, 0xb9, 0xe1, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtzu v6.2d, v8.2d"
+
+  -
+    input:
+      bytes: [ 0x04, 0xb8, 0xa1, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtzu v4.2s, v0.2s"
+
+  -
+    input:
+      bytes: [ 0x04, 0xc8, 0x79, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtas v4.4h, v0.4h"
+
+  -
+    input:
+      bytes: [ 0x06, 0xc9, 0x79, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtas v6.8h, v8.8h"
+
+  -
+    input:
+      bytes: [ 0x06, 0xc9, 0x21, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtas v6.4s, v8.4s"
+
+  -
+    input:
+      bytes: [ 0x06, 0xc9, 0x61, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtas v6.2d, v8.2d"
+
+  -
+    input:
+      bytes: [ 0x04, 0xc8, 0x21, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtas v4.2s, v0.2s"
+
+  -
+    input:
+      bytes: [ 0x04, 0xc8, 0x79, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtau v4.4h, v0.4h"
+
+  -
+    input:
+      bytes: [ 0x06, 0xc9, 0x79, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtau v6.8h, v8.8h"
+
+  -
+    input:
+      bytes: [ 0x06, 0xc9, 0x21, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtau v6.4s, v8.4s"
+
+  -
+    input:
+      bytes: [ 0x06, 0xc9, 0x61, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtau v6.2d, v8.2d"
+
+  -
+    input:
+      bytes: [ 0x04, 0xc8, 0x21, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtau v4.2s, v0.2s"
+
+  -
+    input:
+      bytes: [ 0x06, 0xc9, 0xa1, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "urecpe v6.4s, v8.4s"
+
+  -
+    input:
+      bytes: [ 0x04, 0xc8, 0xa1, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "urecpe v4.2s, v0.2s"
+
+  -
+    input:
+      bytes: [ 0x06, 0xc9, 0xa1, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "ursqrte v6.4s, v8.4s"
+
+  -
+    input:
+      bytes: [ 0x04, 0xc8, 0xa1, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "ursqrte v4.2s, v0.2s"
+
+  -
+    input:
+      bytes: [ 0x04, 0xd8, 0x79, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "scvtf v4.4h, v0.4h"
+
+  -
+    input:
+      bytes: [ 0x06, 0xd9, 0x79, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "scvtf v6.8h, v8.8h"
+
+  -
+    input:
+      bytes: [ 0x06, 0xd9, 0x21, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "scvtf v6.4s, v8.4s"
+
+  -
+    input:
+      bytes: [ 0x06, 0xd9, 0x61, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "scvtf v6.2d, v8.2d"
+
+  -
+    input:
+      bytes: [ 0x04, 0xd8, 0x21, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "scvtf v4.2s, v0.2s"
+
+  -
+    input:
+      bytes: [ 0x04, 0xd8, 0x79, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "ucvtf v4.4h, v0.4h"
+
+  -
+    input:
+      bytes: [ 0x06, 0xd9, 0x79, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "ucvtf v6.8h, v8.8h"
+
+  -
+    input:
+      bytes: [ 0x06, 0xd9, 0x21, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "ucvtf v6.4s, v8.4s"
+
+  -
+    input:
+      bytes: [ 0x06, 0xd9, 0x61, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "ucvtf v6.2d, v8.2d"
+
+  -
+    input:
+      bytes: [ 0x04, 0xd8, 0x21, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "ucvtf v4.2s, v0.2s"
+
+  -
+    input:
+      bytes: [ 0x04, 0xd8, 0xf9, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "frecpe v4.4h, v0.4h"
+
+  -
+    input:
+      bytes: [ 0x06, 0xd9, 0xf9, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "frecpe v6.8h, v8.8h"
+
+  -
+    input:
+      bytes: [ 0x06, 0xd9, 0xa1, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "frecpe v6.4s, v8.4s"
+
+  -
+    input:
+      bytes: [ 0x06, 0xd9, 0xe1, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "frecpe v6.2d, v8.2d"
+
+  -
+    input:
+      bytes: [ 0x04, 0xd8, 0xa1, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "frecpe v4.2s, v0.2s"
+
+  -
+    input:
+      bytes: [ 0x04, 0xd8, 0xf9, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "frsqrte v4.4h, v0.4h"
+
+  -
+    input:
+      bytes: [ 0x06, 0xd9, 0xf9, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "frsqrte v6.8h, v8.8h"
+
+  -
+    input:
+      bytes: [ 0x06, 0xd9, 0xa1, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "frsqrte v6.4s, v8.4s"
+
+  -
+    input:
+      bytes: [ 0x06, 0xd9, 0xe1, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "frsqrte v6.2d, v8.2d"
+
+  -
+    input:
+      bytes: [ 0x04, 0xd8, 0xa1, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "frsqrte v4.2s, v0.2s"
+
+  -
+    input:
+      bytes: [ 0x04, 0xf8, 0xf9, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsqrt v4.4h, v0.4h"
+
+  -
+    input:
+      bytes: [ 0x06, 0xf9, 0xf9, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsqrt v6.8h, v8.8h"
+
+  -
+    input:
+      bytes: [ 0x06, 0xf9, 0xa1, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsqrt v6.4s, v8.4s"
+
+  -
+    input:
+      bytes: [ 0x06, 0xf9, 0xe1, 0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsqrt v6.2d, v8.2d"
+
+  -
+    input:
+      bytes: [ 0x04, 0xf8, 0xa1, 0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsqrt v4.2s, v0.2s"
diff --git a/tests/MC/AArch64/neon-simd-post-ldst-multi-elem.s.yaml b/tests/MC/AArch64/neon-simd-post-ldst-multi-elem.s.yaml
new file mode 100644
index 000000000..79857b2e9
--- /dev/null
+++ b/tests/MC/AArch64/neon-simd-post-ldst-multi-elem.s.yaml
@@ -0,0 +1,1060 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x70, 0xc1, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1 { v0.16b }, [x0], x1"
+
+  -
+    input:
+      bytes: [ 0xef, 0x75, 0xc2, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1 { v15.8h }, [x15], x2"
+
+  -
+    input:
+      bytes: [ 0xff, 0x7b, 0xdf, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1 { v31.4s }, [sp], #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0x7c, 0xdf, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1 { v0.2d }, [x0], #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0x70, 0xc2, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1 { v0.8b }, [x0], x2"
+
+  -
+    input:
+      bytes: [ 0xef, 0x75, 0xc3, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1 { v15.4h }, [x15], x3"
+
+  -
+    input:
+      bytes: [ 0xff, 0x7b, 0xdf, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1 { v31.2s }, [sp], #8"
+
+  -
+    input:
+      bytes: [ 0x00, 0x7c, 0xdf, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1 { v0.1d }, [x0], #8"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xc1, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1 { v0.16b, v1.16b }, [x0], x1"
+
+  -
+    input:
+      bytes: [ 0xef, 0xa5, 0xc2, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1 { v15.8h, v16.8h }, [x15], x2"
+
+  -
+    input:
+      bytes: [ 0xff, 0xab, 0xdf, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1 { v31.4s, v0.4s }, [sp], #32"
+
+  -
+    input:
+      bytes: [ 0x00, 0xac, 0xdf, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1 { v0.2d, v1.2d }, [x0], #32"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xc2, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1 { v0.8b, v1.8b }, [x0], x2"
+
+  -
+    input:
+      bytes: [ 0xef, 0xa5, 0xc3, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1 { v15.4h, v16.4h }, [x15], x3"
+
+  -
+    input:
+      bytes: [ 0xff, 0xab, 0xdf, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1 { v31.2s, v0.2s }, [sp], #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xac, 0xdf, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1 { v0.1d, v1.1d }, [x0], #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0xc1, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1 { v0.16b, v1.16b, v2.16b }, [x0], x1"
+
+  -
+    input:
+      bytes: [ 0xef, 0x65, 0xc2, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1 { v15.8h, v16.8h, v17.8h }, [x15], x2"
+
+  -
+    input:
+      bytes: [ 0xff, 0x6b, 0xdf, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1 { v31.4s, v0.4s, v1.4s }, [sp], #48"
+
+  -
+    input:
+      bytes: [ 0x00, 0x6c, 0xdf, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1 { v0.2d, v1.2d, v2.2d }, [x0], #48"
+
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0xc2, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1 { v0.8b, v1.8b, v2.8b }, [x0], x2"
+
+  -
+    input:
+      bytes: [ 0xef, 0x65, 0xc3, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1 { v15.4h, v16.4h, v17.4h }, [x15], x3"
+
+  -
+    input:
+      bytes: [ 0xff, 0x6b, 0xdf, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1 { v31.2s, v0.2s, v1.2s }, [sp], #24"
+
+  -
+    input:
+      bytes: [ 0x00, 0x6c, 0xdf, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1 { v0.1d, v1.1d, v2.1d }, [x0], #24"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0xc1, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1 { v0.16b, v1.16b, v2.16b, v3.16b }, [x0], x1"
+
+  -
+    input:
+      bytes: [ 0xef, 0x25, 0xc2, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1 { v15.8h, v16.8h, v17.8h, v18.8h }, [x15], x2"
+
+  -
+    input:
+      bytes: [ 0xff, 0x2b, 0xdf, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1 { v31.4s, v0.4s, v1.4s, v2.4s }, [sp], #64"
+
+  -
+    input:
+      bytes: [ 0x00, 0x2c, 0xdf, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0], #64"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0xc3, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0], x3"
+
+  -
+    input:
+      bytes: [ 0xef, 0x25, 0xc4, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1 { v15.4h, v16.4h, v17.4h, v18.4h }, [x15], x4"
+
+  -
+    input:
+      bytes: [ 0xff, 0x2b, 0xdf, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1 { v31.2s, v0.2s, v1.2s, v2.2s }, [sp], #32"
+
+  -
+    input:
+      bytes: [ 0x00, 0x2c, 0xdf, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld1 { v0.1d, v1.1d, v2.1d, v3.1d }, [x0], #32"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xc1, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld2 { v0.16b, v1.16b }, [x0], x1"
+
+  -
+    input:
+      bytes: [ 0xef, 0x85, 0xc2, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld2 { v15.8h, v16.8h }, [x15], x2"
+
+  -
+    input:
+      bytes: [ 0xff, 0x8b, 0xdf, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld2 { v31.4s, v0.4s }, [sp], #32"
+
+  -
+    input:
+      bytes: [ 0x00, 0x8c, 0xdf, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld2 { v0.2d, v1.2d }, [x0], #32"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xc2, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld2 { v0.8b, v1.8b }, [x0], x2"
+
+  -
+    input:
+      bytes: [ 0xef, 0x85, 0xc3, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld2 { v15.4h, v16.4h }, [x15], x3"
+
+  -
+    input:
+      bytes: [ 0xff, 0x8b, 0xdf, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld2 { v31.2s, v0.2s }, [sp], #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0xc1, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld3 { v0.16b, v1.16b, v2.16b }, [x0], x1"
+
+  -
+    input:
+      bytes: [ 0xef, 0x45, 0xc2, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld3 { v15.8h, v16.8h, v17.8h }, [x15], x2"
+
+  -
+    input:
+      bytes: [ 0xff, 0x4b, 0xdf, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld3 { v31.4s, v0.4s, v1.4s }, [sp], #48"
+
+  -
+    input:
+      bytes: [ 0x00, 0x4c, 0xdf, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld3 { v0.2d, v1.2d, v2.2d }, [x0], #48"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0xc2, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld3 { v0.8b, v1.8b, v2.8b }, [x0], x2"
+
+  -
+    input:
+      bytes: [ 0xef, 0x45, 0xc3, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld3 { v15.4h, v16.4h, v17.4h }, [x15], x3"
+
+  -
+    input:
+      bytes: [ 0xff, 0x4b, 0xdf, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld3 { v31.2s, v0.2s, v1.2s }, [sp], #24"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0xc1, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x0], x1"
+
+  -
+    input:
+      bytes: [ 0xef, 0x05, 0xc2, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld4 { v15.8h, v16.8h, v17.8h, v18.8h }, [x15], x2"
+
+  -
+    input:
+      bytes: [ 0xff, 0x0b, 0xdf, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld4 { v31.4s, v0.4s, v1.4s, v2.4s }, [sp], #64"
+
+  -
+    input:
+      bytes: [ 0x00, 0x0c, 0xdf, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld4 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0], #64"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0xc3, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld4 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0], x3"
+
+  -
+    input:
+      bytes: [ 0xef, 0x05, 0xc4, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld4 { v15.4h, v16.4h, v17.4h, v18.4h }, [x15], x4"
+
+  -
+    input:
+      bytes: [ 0xff, 0x0b, 0xdf, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld4 { v31.2s, v0.2s, v1.2s, v2.2s }, [sp], #32"
+
+  -
+    input:
+      bytes: [ 0x00, 0x70, 0x81, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1 { v0.16b }, [x0], x1"
+
+  -
+    input:
+      bytes: [ 0xef, 0x75, 0x82, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1 { v15.8h }, [x15], x2"
+
+  -
+    input:
+      bytes: [ 0xff, 0x7b, 0x9f, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1 { v31.4s }, [sp], #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0x7c, 0x9f, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1 { v0.2d }, [x0], #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0x70, 0x82, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1 { v0.8b }, [x0], x2"
+
+  -
+    input:
+      bytes: [ 0xef, 0x75, 0x83, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1 { v15.4h }, [x15], x3"
+
+  -
+    input:
+      bytes: [ 0xff, 0x7b, 0x9f, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1 { v31.2s }, [sp], #8"
+
+  -
+    input:
+      bytes: [ 0x00, 0x7c, 0x9f, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1 { v0.1d }, [x0], #8"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x81, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1 { v0.16b, v1.16b }, [x0], x1"
+
+  -
+    input:
+      bytes: [ 0xef, 0xa5, 0x82, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1 { v15.8h, v16.8h }, [x15], x2"
+
+  -
+    input:
+      bytes: [ 0xff, 0xab, 0x9f, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1 { v31.4s, v0.4s }, [sp], #32"
+
+  -
+    input:
+      bytes: [ 0x00, 0xac, 0x9f, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1 { v0.2d, v1.2d }, [x0], #32"
+
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0x82, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1 { v0.8b, v1.8b }, [x0], x2"
+
+  -
+    input:
+      bytes: [ 0xef, 0xa5, 0x83, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1 { v15.4h, v16.4h }, [x15], x3"
+
+  -
+    input:
+      bytes: [ 0xff, 0xab, 0x9f, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1 { v31.2s, v0.2s }, [sp], #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0xac, 0x9f, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1 { v0.1d, v1.1d }, [x0], #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0x81, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1 { v0.16b, v1.16b, v2.16b }, [x0], x1"
+
+  -
+    input:
+      bytes: [ 0xef, 0x65, 0x82, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1 { v15.8h, v16.8h, v17.8h }, [x15], x2"
+
+  -
+    input:
+      bytes: [ 0xff, 0x6b, 0x9f, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1 { v31.4s, v0.4s, v1.4s }, [sp], #48"
+
+  -
+    input:
+      bytes: [ 0x00, 0x6c, 0x9f, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1 { v0.2d, v1.2d, v2.2d }, [x0], #48"
+
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0x82, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1 { v0.8b, v1.8b, v2.8b }, [x0], x2"
+
+  -
+    input:
+      bytes: [ 0xef, 0x65, 0x83, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1 { v15.4h, v16.4h, v17.4h }, [x15], x3"
+
+  -
+    input:
+      bytes: [ 0xff, 0x6b, 0x9f, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1 { v31.2s, v0.2s, v1.2s }, [sp], #24"
+
+  -
+    input:
+      bytes: [ 0x00, 0x6c, 0x9f, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1 { v0.1d, v1.1d, v2.1d }, [x0], #24"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x81, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1 { v0.16b, v1.16b, v2.16b, v3.16b }, [x0], x1"
+
+  -
+    input:
+      bytes: [ 0xef, 0x25, 0x82, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1 { v15.8h, v16.8h, v17.8h, v18.8h }, [x15], x2"
+
+  -
+    input:
+      bytes: [ 0xff, 0x2b, 0x9f, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1 { v31.4s, v0.4s, v1.4s, v2.4s }, [sp], #64"
+
+  -
+    input:
+      bytes: [ 0x00, 0x2c, 0x9f, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0], #64"
+
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x83, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0], x3"
+
+  -
+    input:
+      bytes: [ 0xef, 0x25, 0x84, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1 { v15.4h, v16.4h, v17.4h, v18.4h }, [x15], x4"
+
+  -
+    input:
+      bytes: [ 0xff, 0x2b, 0x9f, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1 { v31.2s, v0.2s, v1.2s, v2.2s }, [sp], #32"
+
+  -
+    input:
+      bytes: [ 0x00, 0x2c, 0x9f, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st1 { v0.1d, v1.1d, v2.1d, v3.1d }, [x0], #32"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x81, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st2 { v0.16b, v1.16b }, [x0], x1"
+
+  -
+    input:
+      bytes: [ 0xef, 0x85, 0x82, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st2 { v15.8h, v16.8h }, [x15], x2"
+
+  -
+    input:
+      bytes: [ 0xff, 0x8b, 0x9f, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st2 { v31.4s, v0.4s }, [sp], #32"
+
+  -
+    input:
+      bytes: [ 0x00, 0x8c, 0x9f, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st2 { v0.2d, v1.2d }, [x0], #32"
+
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x82, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st2 { v0.8b, v1.8b }, [x0], x2"
+
+  -
+    input:
+      bytes: [ 0xef, 0x85, 0x83, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st2 { v15.4h, v16.4h }, [x15], x3"
+
+  -
+    input:
+      bytes: [ 0xff, 0x8b, 0x9f, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st2 { v31.2s, v0.2s }, [sp], #16"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0x81, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st3 { v0.16b, v1.16b, v2.16b }, [x0], x1"
+
+  -
+    input:
+      bytes: [ 0xef, 0x45, 0x82, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st3 { v15.8h, v16.8h, v17.8h }, [x15], x2"
+
+  -
+    input:
+      bytes: [ 0xff, 0x4b, 0x9f, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st3 { v31.4s, v0.4s, v1.4s }, [sp], #48"
+
+  -
+    input:
+      bytes: [ 0x00, 0x4c, 0x9f, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st3 { v0.2d, v1.2d, v2.2d }, [x0], #48"
+
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0x82, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st3 { v0.8b, v1.8b, v2.8b }, [x0], x2"
+
+  -
+    input:
+      bytes: [ 0xef, 0x45, 0x83, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st3 { v15.4h, v16.4h, v17.4h }, [x15], x3"
+
+  -
+    input:
+      bytes: [ 0xff, 0x4b, 0x9f, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st3 { v31.2s, v0.2s, v1.2s }, [sp], #24"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x81, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x0], x1"
+
+  -
+    input:
+      bytes: [ 0xef, 0x05, 0x82, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st4 { v15.8h, v16.8h, v17.8h, v18.8h }, [x15], x2"
+
+  -
+    input:
+      bytes: [ 0xff, 0x0b, 0x9f, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st4 { v31.4s, v0.4s, v1.4s, v2.4s }, [sp], #64"
+
+  -
+    input:
+      bytes: [ 0x00, 0x0c, 0x9f, 0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st4 { v0.2d, v1.2d, v2.2d, v3.2d }, [x0], #64"
+
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x83, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st4 { v0.8b, v1.8b, v2.8b, v3.8b }, [x0], x3"
+
+  -
+    input:
+      bytes: [ 0xef, 0x05, 0x84, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st4 { v15.4h, v16.4h, v17.4h, v18.4h }, [x15], x4"
+
+  -
+    input:
+      bytes: [ 0xff, 0x0b, 0x9f, 0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "st4 { v31.2s, v0.2s, v1.2s, v2.2s }, [sp], #32"
diff --git a/tests/MC/AArch64/neon-simd-shift.s.yaml b/tests/MC/AArch64/neon-simd-shift.s.yaml
new file mode 100644
index 000000000..709a67822
--- /dev/null
+++ b/tests/MC/AArch64/neon-simd-shift.s.yaml
@@ -0,0 +1,1590 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x04, 0x0d, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sshr v0.8b, v1.8b, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x04, 0x1d, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sshr v0.4h, v1.4h, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x04, 0x3d, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sshr v0.2s, v1.2s, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x04, 0x0d, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sshr v0.16b, v1.16b, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x04, 0x1d, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sshr v0.8h, v1.8h, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x04, 0x3d, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sshr v0.4s, v1.4s, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x04, 0x7d, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sshr v0.2d, v1.2d, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x04, 0x0d, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "ushr v0.8b, v1.8b, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x04, 0x1d, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "ushr v0.4h, v1.4h, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x04, 0x3d, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "ushr v0.2s, v1.2s, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x04, 0x0d, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "ushr v0.16b, v1.16b, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x04, 0x1d, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "ushr v0.8h, v1.8h, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x04, 0x3d, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "ushr v0.4s, v1.4s, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x04, 0x7d, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "ushr v0.2d, v1.2d, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x14, 0x0d, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "ssra v0.8b, v1.8b, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x14, 0x1d, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "ssra v0.4h, v1.4h, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x14, 0x3d, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "ssra v0.2s, v1.2s, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x14, 0x0d, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "ssra v0.16b, v1.16b, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x14, 0x1d, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "ssra v0.8h, v1.8h, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x14, 0x3d, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "ssra v0.4s, v1.4s, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x14, 0x7d, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "ssra v0.2d, v1.2d, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x14, 0x0d, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "usra v0.8b, v1.8b, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x14, 0x1d, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "usra v0.4h, v1.4h, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x14, 0x3d, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "usra v0.2s, v1.2s, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x14, 0x0d, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "usra v0.16b, v1.16b, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x14, 0x1d, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "usra v0.8h, v1.8h, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x14, 0x3d, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "usra v0.4s, v1.4s, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x14, 0x7d, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "usra v0.2d, v1.2d, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x24, 0x0d, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshr v0.8b, v1.8b, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x24, 0x1d, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshr v0.4h, v1.4h, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x24, 0x3d, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshr v0.2s, v1.2s, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x24, 0x0d, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshr v0.16b, v1.16b, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x24, 0x1d, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshr v0.8h, v1.8h, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x24, 0x3d, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshr v0.4s, v1.4s, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x24, 0x7d, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "srshr v0.2d, v1.2d, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x24, 0x0d, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshr v0.8b, v1.8b, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x24, 0x1d, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshr v0.4h, v1.4h, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x24, 0x3d, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshr v0.2s, v1.2s, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x24, 0x0d, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshr v0.16b, v1.16b, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x24, 0x1d, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshr v0.8h, v1.8h, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x24, 0x3d, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshr v0.4s, v1.4s, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x24, 0x7d, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "urshr v0.2d, v1.2d, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x34, 0x0d, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "srsra v0.8b, v1.8b, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x34, 0x1d, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "srsra v0.4h, v1.4h, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x34, 0x3d, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "srsra v0.2s, v1.2s, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x34, 0x0d, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "srsra v0.16b, v1.16b, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x34, 0x1d, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "srsra v0.8h, v1.8h, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x34, 0x3d, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "srsra v0.4s, v1.4s, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x34, 0x7d, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "srsra v0.2d, v1.2d, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x34, 0x0d, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "ursra v0.8b, v1.8b, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x34, 0x1d, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "ursra v0.4h, v1.4h, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x34, 0x3d, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "ursra v0.2s, v1.2s, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x34, 0x0d, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "ursra v0.16b, v1.16b, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x34, 0x1d, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "ursra v0.8h, v1.8h, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x34, 0x3d, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "ursra v0.4s, v1.4s, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x34, 0x7d, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "ursra v0.2d, v1.2d, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x44, 0x0d, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sri v0.8b, v1.8b, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x44, 0x1d, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sri v0.4h, v1.4h, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x44, 0x3d, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sri v0.2s, v1.2s, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x44, 0x0d, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sri v0.16b, v1.16b, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x44, 0x1d, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sri v0.8h, v1.8h, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x44, 0x3d, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sri v0.4s, v1.4s, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x44, 0x7d, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sri v0.2d, v1.2d, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x54, 0x0b, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sli v0.8b, v1.8b, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x54, 0x13, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sli v0.4h, v1.4h, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x54, 0x23, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sli v0.2s, v1.2s, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x54, 0x0b, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sli v0.16b, v1.16b, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x54, 0x13, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sli v0.8h, v1.8h, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x54, 0x23, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sli v0.4s, v1.4s, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x54, 0x43, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sli v0.2d, v1.2d, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x64, 0x0b, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshlu v0.8b, v1.8b, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x64, 0x13, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshlu v0.4h, v1.4h, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x64, 0x23, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshlu v0.2s, v1.2s, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x64, 0x0b, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshlu v0.16b, v1.16b, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x64, 0x13, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshlu v0.8h, v1.8h, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x64, 0x23, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshlu v0.4s, v1.4s, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x64, 0x43, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshlu v0.2d, v1.2d, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x74, 0x0b, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshl v0.8b, v1.8b, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x74, 0x13, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshl v0.4h, v1.4h, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x74, 0x23, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshl v0.2s, v1.2s, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x74, 0x0b, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshl v0.16b, v1.16b, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x74, 0x13, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshl v0.8h, v1.8h, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x74, 0x23, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshl v0.4s, v1.4s, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x74, 0x43, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshl v0.2d, v1.2d, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x74, 0x0b, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqshl v0.8b, v1.8b, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x74, 0x13, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqshl v0.4h, v1.4h, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x74, 0x23, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqshl v0.2s, v1.2s, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x74, 0x0b, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqshl v0.16b, v1.16b, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x74, 0x13, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqshl v0.8h, v1.8h, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x74, 0x23, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqshl v0.4s, v1.4s, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x74, 0x43, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqshl v0.2d, v1.2d, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x84, 0x0d, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "shrn v0.8b, v1.8h, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x84, 0x1d, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "shrn v0.4h, v1.4s, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x84, 0x3d, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "shrn v0.2s, v1.2d, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x84, 0x0d, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "shrn2 v0.16b, v1.8h, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x84, 0x1d, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "shrn2 v0.8h, v1.4s, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x84, 0x3d, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "shrn2 v0.4s, v1.2d, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x84, 0x0d, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshrun v0.8b, v1.8h, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x84, 0x1d, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshrun v0.4h, v1.4s, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x84, 0x3d, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshrun v0.2s, v1.2d, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x84, 0x0d, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshrun2 v0.16b, v1.8h, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x84, 0x1d, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshrun2 v0.8h, v1.4s, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x84, 0x3d, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshrun2 v0.4s, v1.2d, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x8c, 0x0d, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "rshrn v0.8b, v1.8h, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x8c, 0x1d, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "rshrn v0.4h, v1.4s, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x8c, 0x3d, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "rshrn v0.2s, v1.2d, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x8c, 0x0d, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "rshrn2 v0.16b, v1.8h, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x8c, 0x1d, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "rshrn2 v0.8h, v1.4s, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x8c, 0x3d, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "rshrn2 v0.4s, v1.2d, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x8c, 0x0d, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshrun v0.8b, v1.8h, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x8c, 0x1d, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshrun v0.4h, v1.4s, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x8c, 0x3d, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshrun v0.2s, v1.2d, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x8c, 0x0d, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshrun2 v0.16b, v1.8h, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x8c, 0x1d, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshrun2 v0.8h, v1.4s, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x8c, 0x3d, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshrun2 v0.4s, v1.2d, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x94, 0x0d, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshrn v0.8b, v1.8h, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x94, 0x1d, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshrn v0.4h, v1.4s, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x94, 0x3d, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshrn v0.2s, v1.2d, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x94, 0x0d, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshrn2 v0.16b, v1.8h, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x94, 0x1d, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshrn2 v0.8h, v1.4s, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x94, 0x3d, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqshrn2 v0.4s, v1.2d, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x94, 0x0d, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqshrn v0.8b, v1.8h, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x94, 0x1d, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqshrn v0.4h, v1.4s, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x94, 0x3d, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqshrn v0.2s, v1.2d, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x94, 0x0d, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqshrn2 v0.16b, v1.8h, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x94, 0x1d, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqshrn2 v0.8h, v1.4s, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x94, 0x3d, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqshrn2 v0.4s, v1.2d, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x9c, 0x0d, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshrn v0.8b, v1.8h, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x9c, 0x1d, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshrn v0.4h, v1.4s, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x9c, 0x3d, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshrn v0.2s, v1.2d, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x9c, 0x0d, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshrn2 v0.16b, v1.8h, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x9c, 0x1d, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshrn2 v0.8h, v1.4s, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x9c, 0x3d, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrshrn2 v0.4s, v1.2d, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x9c, 0x0d, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqrshrn v0.8b, v1.8h, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x9c, 0x1d, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqrshrn v0.4h, v1.4s, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x9c, 0x3d, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqrshrn v0.2s, v1.2d, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x9c, 0x0d, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqrshrn2 v0.16b, v1.8h, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x9c, 0x1d, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqrshrn2 v0.8h, v1.4s, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0x9c, 0x3d, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "uqrshrn2 v0.4s, v1.2d, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe4, 0x1d, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "scvtf v0.4h, v1.4h, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe4, 0x1d, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "scvtf v0.8h, v1.8h, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe4, 0x3d, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "scvtf v0.2s, v1.2s, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe4, 0x3d, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "scvtf v0.4s, v1.4s, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe4, 0x7d, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "scvtf v0.2d, v1.2d, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe4, 0x1d, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "ucvtf v0.4h, v1.4h, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe4, 0x1d, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "ucvtf v0.8h, v1.8h, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe4, 0x3d, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "ucvtf v0.2s, v1.2s, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe4, 0x3d, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "ucvtf v0.4s, v1.4s, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0xe4, 0x7d, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "ucvtf v0.2d, v1.2d, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0xfc, 0x1d, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtzs v0.4h, v1.4h, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0xfc, 0x1d, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtzs v0.8h, v1.8h, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0xfc, 0x3d, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtzs v0.2s, v1.2s, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0xfc, 0x3d, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtzs v0.4s, v1.4s, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0xfc, 0x7d, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtzs v0.2d, v1.2d, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0xfc, 0x1d, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtzu v0.4h, v1.4h, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0xfc, 0x1d, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtzu v0.8h, v1.8h, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0xfc, 0x3d, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtzu v0.2s, v1.2s, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0xfc, 0x3d, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtzu v0.4s, v1.4s, #3"
+
+  -
+    input:
+      bytes: [ 0x20, 0xfc, 0x7d, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon", "+fullfp16" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvtzu v0.2d, v1.2d, #3"
diff --git a/tests/MC/AArch64/neon-sxtl.s.yaml b/tests/MC/AArch64/neon-sxtl.s.yaml
new file mode 100644
index 000000000..0b931666e
--- /dev/null
+++ b/tests/MC/AArch64/neon-sxtl.s.yaml
@@ -0,0 +1,60 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0xa4, 0x08, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sshll v0.8h, v1.8b, #0"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa4, 0x10, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sshll v0.4s, v1.4h, #0"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa4, 0x20, 0x0f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sshll v0.2d, v1.2s, #0"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa4, 0x08, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sshll2 v0.8h, v1.16b, #0"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa4, 0x10, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sshll2 v0.4s, v1.8h, #0"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa4, 0x20, 0x4f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "sshll2 v0.2d, v1.4s, #0"
diff --git a/tests/MC/AArch64/neon-tbl.s.yaml b/tests/MC/AArch64/neon-tbl.s.yaml
new file mode 100644
index 000000000..f82bd0d24
--- /dev/null
+++ b/tests/MC/AArch64/neon-tbl.s.yaml
@@ -0,0 +1,200 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x00, 0x02, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "tbl v0.8b, { v1.16b }, v2.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x20, 0x02, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "tbl v0.8b, { v1.16b, v2.16b }, v2.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x40, 0x02, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "tbl v0.8b, { v1.16b, v2.16b, v3.16b }, v2.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x60, 0x02, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "tbl v0.8b, { v1.16b, v2.16b, v3.16b, v4.16b }, v2.8b"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x63, 0x02, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "tbl v0.8b, { v31.16b, v0.16b, v1.16b, v2.16b }, v2.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x00, 0x02, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "tbl v0.16b, { v1.16b }, v2.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x20, 0x02, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "tbl v0.16b, { v1.16b, v2.16b }, v2.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x40, 0x02, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "tbl v0.16b, { v1.16b, v2.16b, v3.16b }, v2.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x60, 0x02, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "tbl v0.16b, { v1.16b, v2.16b, v3.16b, v4.16b }, v2.16b"
+
+  -
+    input:
+      bytes: [ 0xc0, 0x63, 0x02, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "tbl v0.16b, { v30.16b, v31.16b, v0.16b, v1.16b }, v2.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x10, 0x02, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "tbx v0.8b, { v1.16b }, v2.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x30, 0x02, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "tbx v0.8b, { v1.16b, v2.16b }, v2.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x50, 0x02, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "tbx v0.8b, { v1.16b, v2.16b, v3.16b }, v2.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x70, 0x02, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "tbx v0.8b, { v1.16b, v2.16b, v3.16b, v4.16b }, v2.8b"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x73, 0x02, 0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "tbx v0.8b, { v31.16b, v0.16b, v1.16b, v2.16b }, v2.8b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x10, 0x02, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "tbx v0.16b, { v1.16b }, v2.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x30, 0x02, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "tbx v0.16b, { v1.16b, v2.16b }, v2.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x50, 0x02, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "tbx v0.16b, { v1.16b, v2.16b, v3.16b }, v2.16b"
+
+  -
+    input:
+      bytes: [ 0x20, 0x70, 0x02, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "tbx v0.16b, { v1.16b, v2.16b, v3.16b, v4.16b }, v2.16b"
+
+  -
+    input:
+      bytes: [ 0xc0, 0x73, 0x02, 0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "arm64", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "tbx v0.16b, { v30.16b, v31.16b, v0.16b, v1.16b }, v2.16b"
diff --git a/tests/MC/AArch64/neon-uxtl.s.yaml b/tests/MC/AArch64/neon-uxtl.s.yaml
new file mode 100644
index 000000000..bb490cf82
--- /dev/null
+++ b/tests/MC/AArch64/neon-uxtl.s.yaml
@@ -0,0 +1,60 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0xa4, 0x08, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ushll v0.8h, v1.8b, #0"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa4, 0x10, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ushll v0.4s, v1.4h, #0"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa4, 0x20, 0x2f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ushll v0.2d, v1.2s, #0"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa4, 0x08, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ushll2 v0.8h, v1.16b, #0"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa4, 0x10, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ushll2 v0.4s, v1.8h, #0"
+
+  -
+    input:
+      bytes: [ 0x20, 0xa4, 0x20, 0x6f ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "neon" ]
+    expected:
+      insns:
+        -
+          asm_text: "ushll2 v0.2d, v1.4s, #0"
diff --git a/tests/MC/AArch64/ras-extension.s.yaml b/tests/MC/AArch64/ras-extension.s.yaml
new file mode 100644
index 000000000..c682d8088
--- /dev/null
+++ b/tests/MC/AArch64/ras-extension.s.yaml
@@ -0,0 +1,1500 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x1f, 0x22, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ras" ]
+    expected:
+      insns:
+        -
+          asm_text: "esb"
+
+  -
+    input:
+      bytes: [ 0x20, 0x53, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ras" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ERRSELR_EL1, x0"
+
+  -
+    input:
+      bytes: [ 0x2f, 0x53, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ras" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ERRSELR_EL1, x15"
+
+  -
+    input:
+      bytes: [ 0x39, 0x53, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ras" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ERRSELR_EL1, x25"
+
+  -
+    input:
+      bytes: [ 0x21, 0x54, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ras" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ERXCTLR_EL1, x1"
+
+  -
+    input:
+      bytes: [ 0x42, 0x54, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ras" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ERXSTATUS_EL1, x2"
+
+  -
+    input:
+      bytes: [ 0x63, 0x54, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ras" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ERXADDR_EL1, x3"
+
+  -
+    input:
+      bytes: [ 0x04, 0x55, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ras" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ERXMISC0_EL1, x4"
+
+  -
+    input:
+      bytes: [ 0x25, 0x55, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ras" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ERXMISC1_EL1, x5"
+
+  -
+    input:
+      bytes: [ 0x26, 0xc1, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ras" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr DISR_EL1, x6"
+
+  -
+    input:
+      bytes: [ 0x27, 0xc1, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ras" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr VDISR_EL2, x7"
+
+  -
+    input:
+      bytes: [ 0x68, 0x52, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ras" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr VSESR_EL2, x8"
+
+  -
+    input:
+      bytes: [ 0x20, 0x53, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ras" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, ERRSELR_EL1"
+
+  -
+    input:
+      bytes: [ 0x2f, 0x53, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ras" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x15, ERRSELR_EL1"
+
+  -
+    input:
+      bytes: [ 0x39, 0x53, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ras" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x25, ERRSELR_EL1"
+
+  -
+    input:
+      bytes: [ 0x21, 0x54, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ras" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x1, ERXCTLR_EL1"
+
+  -
+    input:
+      bytes: [ 0x42, 0x54, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ras" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x2, ERXSTATUS_EL1"
+
+  -
+    input:
+      bytes: [ 0x63, 0x54, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ras" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, ERXADDR_EL1"
+
+  -
+    input:
+      bytes: [ 0x04, 0x55, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ras" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x4, ERXMISC0_EL1"
+
+  -
+    input:
+      bytes: [ 0x25, 0x55, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ras" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x5, ERXMISC1_EL1"
+
+  -
+    input:
+      bytes: [ 0x26, 0xc1, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ras" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x6, DISR_EL1"
+
+  -
+    input:
+      bytes: [ 0x27, 0xc1, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ras" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x7, VDISR_EL2"
+
+  -
+    input:
+      bytes: [ 0x68, 0x52, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ras" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x8, VSESR_EL2"
+
+  -
+    input:
+      bytes: [ 0x00, 0x53, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ras" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, ERRIDR_EL1"
+
+  -
+    input:
+      bytes: [ 0x01, 0x54, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "ras" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x1, ERXFR_EL1"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x22, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a55" ]
+    expected:
+      insns:
+        -
+          asm_text: "esb"
+
+  -
+    input:
+      bytes: [ 0x20, 0x53, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a55" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ERRSELR_EL1, x0"
+
+  -
+    input:
+      bytes: [ 0x2f, 0x53, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a55" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ERRSELR_EL1, x15"
+
+  -
+    input:
+      bytes: [ 0x39, 0x53, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a55" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ERRSELR_EL1, x25"
+
+  -
+    input:
+      bytes: [ 0x21, 0x54, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a55" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ERXCTLR_EL1, x1"
+
+  -
+    input:
+      bytes: [ 0x42, 0x54, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a55" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ERXSTATUS_EL1, x2"
+
+  -
+    input:
+      bytes: [ 0x63, 0x54, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a55" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ERXADDR_EL1, x3"
+
+  -
+    input:
+      bytes: [ 0x04, 0x55, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a55" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ERXMISC0_EL1, x4"
+
+  -
+    input:
+      bytes: [ 0x25, 0x55, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a55" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ERXMISC1_EL1, x5"
+
+  -
+    input:
+      bytes: [ 0x26, 0xc1, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a55" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr DISR_EL1, x6"
+
+  -
+    input:
+      bytes: [ 0x27, 0xc1, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a55" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr VDISR_EL2, x7"
+
+  -
+    input:
+      bytes: [ 0x68, 0x52, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a55" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr VSESR_EL2, x8"
+
+  -
+    input:
+      bytes: [ 0x20, 0x53, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a55" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, ERRSELR_EL1"
+
+  -
+    input:
+      bytes: [ 0x2f, 0x53, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a55" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x15, ERRSELR_EL1"
+
+  -
+    input:
+      bytes: [ 0x39, 0x53, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a55" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x25, ERRSELR_EL1"
+
+  -
+    input:
+      bytes: [ 0x21, 0x54, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a55" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x1, ERXCTLR_EL1"
+
+  -
+    input:
+      bytes: [ 0x42, 0x54, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a55" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x2, ERXSTATUS_EL1"
+
+  -
+    input:
+      bytes: [ 0x63, 0x54, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a55" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, ERXADDR_EL1"
+
+  -
+    input:
+      bytes: [ 0x04, 0x55, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a55" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x4, ERXMISC0_EL1"
+
+  -
+    input:
+      bytes: [ 0x25, 0x55, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a55" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x5, ERXMISC1_EL1"
+
+  -
+    input:
+      bytes: [ 0x26, 0xc1, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a55" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x6, DISR_EL1"
+
+  -
+    input:
+      bytes: [ 0x27, 0xc1, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a55" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x7, VDISR_EL2"
+
+  -
+    input:
+      bytes: [ 0x68, 0x52, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a55" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x8, VSESR_EL2"
+
+  -
+    input:
+      bytes: [ 0x00, 0x53, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a55" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, ERRIDR_EL1"
+
+  -
+    input:
+      bytes: [ 0x01, 0x54, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a55" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x1, ERXFR_EL1"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x22, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a75" ]
+    expected:
+      insns:
+        -
+          asm_text: "esb"
+
+  -
+    input:
+      bytes: [ 0x20, 0x53, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a75" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ERRSELR_EL1, x0"
+
+  -
+    input:
+      bytes: [ 0x2f, 0x53, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a75" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ERRSELR_EL1, x15"
+
+  -
+    input:
+      bytes: [ 0x39, 0x53, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a75" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ERRSELR_EL1, x25"
+
+  -
+    input:
+      bytes: [ 0x21, 0x54, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a75" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ERXCTLR_EL1, x1"
+
+  -
+    input:
+      bytes: [ 0x42, 0x54, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a75" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ERXSTATUS_EL1, x2"
+
+  -
+    input:
+      bytes: [ 0x63, 0x54, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a75" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ERXADDR_EL1, x3"
+
+  -
+    input:
+      bytes: [ 0x04, 0x55, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a75" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ERXMISC0_EL1, x4"
+
+  -
+    input:
+      bytes: [ 0x25, 0x55, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a75" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ERXMISC1_EL1, x5"
+
+  -
+    input:
+      bytes: [ 0x26, 0xc1, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a75" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr DISR_EL1, x6"
+
+  -
+    input:
+      bytes: [ 0x27, 0xc1, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a75" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr VDISR_EL2, x7"
+
+  -
+    input:
+      bytes: [ 0x68, 0x52, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a75" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr VSESR_EL2, x8"
+
+  -
+    input:
+      bytes: [ 0x20, 0x53, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a75" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, ERRSELR_EL1"
+
+  -
+    input:
+      bytes: [ 0x2f, 0x53, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a75" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x15, ERRSELR_EL1"
+
+  -
+    input:
+      bytes: [ 0x39, 0x53, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a75" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x25, ERRSELR_EL1"
+
+  -
+    input:
+      bytes: [ 0x21, 0x54, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a75" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x1, ERXCTLR_EL1"
+
+  -
+    input:
+      bytes: [ 0x42, 0x54, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a75" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x2, ERXSTATUS_EL1"
+
+  -
+    input:
+      bytes: [ 0x63, 0x54, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a75" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, ERXADDR_EL1"
+
+  -
+    input:
+      bytes: [ 0x04, 0x55, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a75" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x4, ERXMISC0_EL1"
+
+  -
+    input:
+      bytes: [ 0x25, 0x55, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a75" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x5, ERXMISC1_EL1"
+
+  -
+    input:
+      bytes: [ 0x26, 0xc1, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a75" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x6, DISR_EL1"
+
+  -
+    input:
+      bytes: [ 0x27, 0xc1, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a75" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x7, VDISR_EL2"
+
+  -
+    input:
+      bytes: [ 0x68, 0x52, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a75" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x8, VSESR_EL2"
+
+  -
+    input:
+      bytes: [ 0x00, 0x53, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a75" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, ERRIDR_EL1"
+
+  -
+    input:
+      bytes: [ 0x01, 0x54, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-a75" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x1, ERXFR_EL1"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x22, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "tsv110" ]
+    expected:
+      insns:
+        -
+          asm_text: "esb"
+
+  -
+    input:
+      bytes: [ 0x20, 0x53, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "tsv110" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ERRSELR_EL1, x0"
+
+  -
+    input:
+      bytes: [ 0x2f, 0x53, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "tsv110" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ERRSELR_EL1, x15"
+
+  -
+    input:
+      bytes: [ 0x39, 0x53, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "tsv110" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ERRSELR_EL1, x25"
+
+  -
+    input:
+      bytes: [ 0x21, 0x54, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "tsv110" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ERXCTLR_EL1, x1"
+
+  -
+    input:
+      bytes: [ 0x42, 0x54, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "tsv110" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ERXSTATUS_EL1, x2"
+
+  -
+    input:
+      bytes: [ 0x63, 0x54, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "tsv110" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ERXADDR_EL1, x3"
+
+  -
+    input:
+      bytes: [ 0x04, 0x55, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "tsv110" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ERXMISC0_EL1, x4"
+
+  -
+    input:
+      bytes: [ 0x25, 0x55, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "tsv110" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ERXMISC1_EL1, x5"
+
+  -
+    input:
+      bytes: [ 0x26, 0xc1, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "tsv110" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr DISR_EL1, x6"
+
+  -
+    input:
+      bytes: [ 0x27, 0xc1, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "tsv110" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr VDISR_EL2, x7"
+
+  -
+    input:
+      bytes: [ 0x68, 0x52, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "tsv110" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr VSESR_EL2, x8"
+
+  -
+    input:
+      bytes: [ 0x20, 0x53, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "tsv110" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, ERRSELR_EL1"
+
+  -
+    input:
+      bytes: [ 0x2f, 0x53, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "tsv110" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x15, ERRSELR_EL1"
+
+  -
+    input:
+      bytes: [ 0x39, 0x53, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "tsv110" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x25, ERRSELR_EL1"
+
+  -
+    input:
+      bytes: [ 0x21, 0x54, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "tsv110" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x1, ERXCTLR_EL1"
+
+  -
+    input:
+      bytes: [ 0x42, 0x54, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "tsv110" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x2, ERXSTATUS_EL1"
+
+  -
+    input:
+      bytes: [ 0x63, 0x54, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "tsv110" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, ERXADDR_EL1"
+
+  -
+    input:
+      bytes: [ 0x04, 0x55, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "tsv110" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x4, ERXMISC0_EL1"
+
+  -
+    input:
+      bytes: [ 0x25, 0x55, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "tsv110" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x5, ERXMISC1_EL1"
+
+  -
+    input:
+      bytes: [ 0x26, 0xc1, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "tsv110" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x6, DISR_EL1"
+
+  -
+    input:
+      bytes: [ 0x27, 0xc1, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "tsv110" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x7, VDISR_EL2"
+
+  -
+    input:
+      bytes: [ 0x68, 0x52, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "tsv110" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x8, VSESR_EL2"
+
+  -
+    input:
+      bytes: [ 0x00, 0x53, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "tsv110" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, ERRIDR_EL1"
+
+  -
+    input:
+      bytes: [ 0x01, 0x54, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "tsv110" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x1, ERXFR_EL1"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x22, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-r82" ]
+    expected:
+      insns:
+        -
+          asm_text: "esb"
+
+  -
+    input:
+      bytes: [ 0x20, 0x53, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-r82" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ERRSELR_EL1, x0"
+
+  -
+    input:
+      bytes: [ 0x2f, 0x53, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-r82" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ERRSELR_EL1, x15"
+
+  -
+    input:
+      bytes: [ 0x39, 0x53, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-r82" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ERRSELR_EL1, x25"
+
+  -
+    input:
+      bytes: [ 0x21, 0x54, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-r82" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ERXCTLR_EL1, x1"
+
+  -
+    input:
+      bytes: [ 0x42, 0x54, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-r82" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ERXSTATUS_EL1, x2"
+
+  -
+    input:
+      bytes: [ 0x63, 0x54, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-r82" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ERXADDR_EL1, x3"
+
+  -
+    input:
+      bytes: [ 0x04, 0x55, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-r82" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ERXMISC0_EL1, x4"
+
+  -
+    input:
+      bytes: [ 0x25, 0x55, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-r82" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ERXMISC1_EL1, x5"
+
+  -
+    input:
+      bytes: [ 0x26, 0xc1, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-r82" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr DISR_EL1, x6"
+
+  -
+    input:
+      bytes: [ 0x27, 0xc1, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-r82" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr VDISR_EL2, x7"
+
+  -
+    input:
+      bytes: [ 0x68, 0x52, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-r82" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr VSESR_EL2, x8"
+
+  -
+    input:
+      bytes: [ 0x20, 0x53, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-r82" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, ERRSELR_EL1"
+
+  -
+    input:
+      bytes: [ 0x2f, 0x53, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-r82" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x15, ERRSELR_EL1"
+
+  -
+    input:
+      bytes: [ 0x39, 0x53, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-r82" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x25, ERRSELR_EL1"
+
+  -
+    input:
+      bytes: [ 0x21, 0x54, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-r82" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x1, ERXCTLR_EL1"
+
+  -
+    input:
+      bytes: [ 0x42, 0x54, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-r82" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x2, ERXSTATUS_EL1"
+
+  -
+    input:
+      bytes: [ 0x63, 0x54, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-r82" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, ERXADDR_EL1"
+
+  -
+    input:
+      bytes: [ 0x04, 0x55, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-r82" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x4, ERXMISC0_EL1"
+
+  -
+    input:
+      bytes: [ 0x25, 0x55, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-r82" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x5, ERXMISC1_EL1"
+
+  -
+    input:
+      bytes: [ 0x26, 0xc1, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-r82" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x6, DISR_EL1"
+
+  -
+    input:
+      bytes: [ 0x27, 0xc1, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-r82" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x7, VDISR_EL2"
+
+  -
+    input:
+      bytes: [ 0x68, 0x52, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-r82" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x8, VSESR_EL2"
+
+  -
+    input:
+      bytes: [ 0x00, 0x53, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-r82" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, ERRIDR_EL1"
+
+  -
+    input:
+      bytes: [ 0x01, 0x54, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "cortex-r82" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x1, ERXFR_EL1"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x22, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "esb"
+
+  -
+    input:
+      bytes: [ 0x20, 0x53, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ERRSELR_EL1, x0"
+
+  -
+    input:
+      bytes: [ 0x2f, 0x53, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ERRSELR_EL1, x15"
+
+  -
+    input:
+      bytes: [ 0x39, 0x53, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ERRSELR_EL1, x25"
+
+  -
+    input:
+      bytes: [ 0x21, 0x54, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ERXCTLR_EL1, x1"
+
+  -
+    input:
+      bytes: [ 0x42, 0x54, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ERXSTATUS_EL1, x2"
+
+  -
+    input:
+      bytes: [ 0x63, 0x54, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ERXADDR_EL1, x3"
+
+  -
+    input:
+      bytes: [ 0x04, 0x55, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ERXMISC0_EL1, x4"
+
+  -
+    input:
+      bytes: [ 0x25, 0x55, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr ERXMISC1_EL1, x5"
+
+  -
+    input:
+      bytes: [ 0x26, 0xc1, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr DISR_EL1, x6"
+
+  -
+    input:
+      bytes: [ 0x27, 0xc1, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr VDISR_EL2, x7"
+
+  -
+    input:
+      bytes: [ 0x68, 0x52, 0x1c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr VSESR_EL2, x8"
+
+  -
+    input:
+      bytes: [ 0x20, 0x53, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, ERRSELR_EL1"
+
+  -
+    input:
+      bytes: [ 0x2f, 0x53, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x15, ERRSELR_EL1"
+
+  -
+    input:
+      bytes: [ 0x39, 0x53, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x25, ERRSELR_EL1"
+
+  -
+    input:
+      bytes: [ 0x21, 0x54, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x1, ERXCTLR_EL1"
+
+  -
+    input:
+      bytes: [ 0x42, 0x54, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x2, ERXSTATUS_EL1"
+
+  -
+    input:
+      bytes: [ 0x63, 0x54, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, ERXADDR_EL1"
+
+  -
+    input:
+      bytes: [ 0x04, 0x55, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x4, ERXMISC0_EL1"
+
+  -
+    input:
+      bytes: [ 0x25, 0x55, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x5, ERXMISC1_EL1"
+
+  -
+    input:
+      bytes: [ 0x26, 0xc1, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x6, DISR_EL1"
+
+  -
+    input:
+      bytes: [ 0x27, 0xc1, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x7, VDISR_EL2"
+
+  -
+    input:
+      bytes: [ 0x68, 0x52, 0x3c, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x8, VSESR_EL2"
+
+  -
+    input:
+      bytes: [ 0x00, 0x53, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, ERRIDR_EL1"
+
+  -
+    input:
+      bytes: [ 0x01, 0x54, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu", "v8r" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x1, ERXFR_EL1"
diff --git a/tests/MC/AArch64/rprfm.s.yaml b/tests/MC/AArch64/rprfm.s.yaml
new file mode 100644
index 000000000..63cdc6f2f
--- /dev/null
+++ b/tests/MC/AArch64/rprfm.s.yaml
@@ -0,0 +1,1280 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x18, 0x48, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm pldkeep, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x19, 0x48, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm pstkeep, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x1a, 0x48, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #2, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x1b, 0x48, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #3, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x1c, 0x48, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm pldstrm, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x1d, 0x48, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm pststrm, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x1e, 0x48, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #6, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x48, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #7, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x18, 0x58, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #8, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x19, 0x58, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #9, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x1a, 0x58, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #10, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x1b, 0x58, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #11, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x1c, 0x58, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #12, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x1d, 0x58, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #13, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x1e, 0x58, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #14, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x58, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #15, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x18, 0x68, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #16, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x19, 0x68, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #17, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x1a, 0x68, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #18, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x1b, 0x68, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #19, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x1c, 0x68, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #20, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x1d, 0x68, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #21, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x1e, 0x68, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #22, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x68, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #23, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x18, 0x78, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #24, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x19, 0x78, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #25, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x1a, 0x78, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #26, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x1b, 0x78, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #27, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x1c, 0x78, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #28, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x1d, 0x78, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #29, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x1e, 0x78, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #30, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x78, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #31, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x18, 0xc8, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #32, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x19, 0xc8, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #33, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x1a, 0xc8, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #34, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x1b, 0xc8, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #35, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x1c, 0xc8, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #36, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x1d, 0xc8, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #37, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x1e, 0xc8, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #38, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x1f, 0xc8, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #39, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x18, 0xd8, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #40, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x19, 0xd8, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #41, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x1a, 0xd8, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #42, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x1b, 0xd8, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #43, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x1c, 0xd8, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #44, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x1d, 0xd8, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #45, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x1e, 0xd8, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #46, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x1f, 0xd8, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #47, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x18, 0xe8, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #48, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x19, 0xe8, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #49, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x1a, 0xe8, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #50, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x1b, 0xe8, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #51, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x1c, 0xe8, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #52, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x1d, 0xe8, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #53, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x1e, 0xe8, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #54, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x1f, 0xe8, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #55, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x18, 0xf8, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #56, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x19, 0xf8, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #57, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x1a, 0xf8, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #58, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x1b, 0xf8, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #59, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x1c, 0xf8, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #60, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x1d, 0xf8, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #61, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x1e, 0xf8, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #62, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x1f, 0xf8, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #63, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x18, 0x48, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm pldkeep, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x19, 0x48, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm pstkeep, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x1a, 0x48, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #2, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x1b, 0x48, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #3, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x1c, 0x48, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm pldstrm, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x1d, 0x48, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm pststrm, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x1e, 0x48, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #6, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x48, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #7, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x18, 0x58, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #8, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x19, 0x58, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #9, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x1a, 0x58, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #10, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x1b, 0x58, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #11, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x1c, 0x58, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #12, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x1d, 0x58, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #13, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x1e, 0x58, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #14, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x58, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #15, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x18, 0x68, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #16, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x19, 0x68, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #17, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x1a, 0x68, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #18, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x1b, 0x68, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #19, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x1c, 0x68, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #20, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x1d, 0x68, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #21, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x1e, 0x68, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #22, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x68, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #23, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x18, 0x78, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #24, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x19, 0x78, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #25, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x1a, 0x78, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #26, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x1b, 0x78, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #27, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x1c, 0x78, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #28, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x1d, 0x78, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #29, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x1e, 0x78, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #30, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x1f, 0x78, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #31, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x18, 0xc8, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #32, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x19, 0xc8, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #33, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x1a, 0xc8, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #34, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x1b, 0xc8, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #35, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x1c, 0xc8, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #36, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x1d, 0xc8, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #37, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x1e, 0xc8, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #38, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x1f, 0xc8, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #39, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x18, 0xd8, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #40, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x19, 0xd8, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #41, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x1a, 0xd8, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #42, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x1b, 0xd8, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #43, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x1c, 0xd8, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #44, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x1d, 0xd8, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #45, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x1e, 0xd8, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #46, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x1f, 0xd8, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #47, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x18, 0xe8, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #48, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x19, 0xe8, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #49, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x1a, 0xe8, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #50, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x1b, 0xe8, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #51, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x1c, 0xe8, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #52, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x1d, 0xe8, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #53, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x1e, 0xe8, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #54, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x1f, 0xe8, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #55, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x18, 0xf8, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #56, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x19, 0xf8, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #57, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x1a, 0xf8, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #58, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x1b, 0xf8, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #59, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x1c, 0xf8, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #60, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x1d, 0xf8, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #61, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x1e, 0xf8, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #62, x0, [x0]"
+
+  -
+    input:
+      bytes: [ 0x1f, 0xf8, 0xa0, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rprfm #63, x0, [x0]"
diff --git a/tests/MC/AArch64/spe.s.yaml b/tests/MC/AArch64/spe.s.yaml
new file mode 100644
index 000000000..e1d854f76
--- /dev/null
+++ b/tests/MC/AArch64/spe.s.yaml
@@ -0,0 +1,20 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x99, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "spe-eef" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr PMSNEVFR_EL1, x0"
+
+  -
+    input:
+      bytes: [ 0x21, 0x99, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "spe-eef" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x1, PMSNEVFR_EL1"
diff --git a/tests/MC/AArch64/speculation-barriers.s.yaml b/tests/MC/AArch64/speculation-barriers.s.yaml
new file mode 100644
index 000000000..fbeff1466
--- /dev/null
+++ b/tests/MC/AArch64/speculation-barriers.s.yaml
@@ -0,0 +1,30 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x9f, 0x22, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "csdb"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x30, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "ssbb"
+
+  -
+    input:
+      bytes: [ 0x9f, 0x34, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "pssbb"
diff --git a/tests/MC/AArch64/tme.s.yaml b/tests/MC/AArch64/tme.s.yaml
new file mode 100644
index 000000000..8bb03bbda
--- /dev/null
+++ b/tests/MC/AArch64/tme.s.yaml
@@ -0,0 +1,40 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x63, 0x30, 0x23, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "tme" ]
+    expected:
+      insns:
+        -
+          asm_text: "tstart x3"
+
+  -
+    input:
+      bytes: [ 0x64, 0x31, 0x23, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "tme" ]
+    expected:
+      insns:
+        -
+          asm_text: "ttest x4"
+
+  -
+    input:
+      bytes: [ 0x7f, 0x30, 0x03, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "tme" ]
+    expected:
+      insns:
+        -
+          asm_text: "tcommit"
+
+  -
+    input:
+      bytes: [ 0x80, 0x46, 0x62, 0xd4 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64", "tme" ]
+    expected:
+      insns:
+        -
+          asm_text: "tcancel #0x1234"
diff --git a/tests/MC/AArch64/trace-regs.s.yaml b/tests/MC/AArch64/trace-regs.s.yaml
new file mode 100644
index 000000000..07b733542
--- /dev/null
+++ b/tests/MC/AArch64/trace-regs.s.yaml
@@ -0,0 +1,3820 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x08, 0x03, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x8, TRCSTATR"
+
+  -
+    input:
+      bytes: [ 0xc9, 0x00, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, TRCIDR8"
+
+  -
+    input:
+      bytes: [ 0xcb, 0x01, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x11, TRCIDR9"
+
+  -
+    input:
+      bytes: [ 0xd9, 0x02, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x25, TRCIDR10"
+
+  -
+    input:
+      bytes: [ 0xc7, 0x03, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x7, TRCIDR11"
+
+  -
+    input:
+      bytes: [ 0xc7, 0x04, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x7, TRCIDR12"
+
+  -
+    input:
+      bytes: [ 0xc6, 0x05, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x6, TRCIDR13"
+
+  -
+    input:
+      bytes: [ 0xfb, 0x08, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x27, TRCIDR0"
+
+  -
+    input:
+      bytes: [ 0xfd, 0x09, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x29, TRCIDR1"
+
+  -
+    input:
+      bytes: [ 0xe4, 0x0a, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x4, TRCIDR2"
+
+  -
+    input:
+      bytes: [ 0xe8, 0x0b, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x8, TRCIDR3"
+
+  -
+    input:
+      bytes: [ 0xef, 0x0c, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x15, TRCIDR4"
+
+  -
+    input:
+      bytes: [ 0xf4, 0x0d, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x20, TRCIDR5"
+
+  -
+    input:
+      bytes: [ 0xe6, 0x0e, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x6, TRCIDR6"
+
+  -
+    input:
+      bytes: [ 0xe6, 0x0f, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x6, TRCIDR7"
+
+  -
+    input:
+      bytes: [ 0x98, 0x11, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x24, TRCOSLSR"
+
+  -
+    input:
+      bytes: [ 0x92, 0x15, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x18, TRCPDSR"
+
+  -
+    input:
+      bytes: [ 0xdc, 0x7a, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x28, TRCDEVAFF0"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x7b, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x5, TRCDEVAFF1"
+
+  -
+    input:
+      bytes: [ 0xc5, 0x7d, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x5, TRCLSR"
+
+  -
+    input:
+      bytes: [ 0xcb, 0x7e, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x11, TRCAUTHSTATUS"
+
+  -
+    input:
+      bytes: [ 0xcd, 0x7f, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x13, TRCDEVARCH"
+
+  -
+    input:
+      bytes: [ 0xf2, 0x72, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x18, TRCDEVID"
+
+  -
+    input:
+      bytes: [ 0xf6, 0x73, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x22, TRCDEVTYPE"
+
+  -
+    input:
+      bytes: [ 0xee, 0x74, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x14, TRCPIDR4"
+
+  -
+    input:
+      bytes: [ 0xe5, 0x75, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x5, TRCPIDR5"
+
+  -
+    input:
+      bytes: [ 0xe5, 0x76, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x5, TRCPIDR6"
+
+  -
+    input:
+      bytes: [ 0xe9, 0x77, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, TRCPIDR7"
+
+  -
+    input:
+      bytes: [ 0xef, 0x78, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x15, TRCPIDR0"
+
+  -
+    input:
+      bytes: [ 0xe6, 0x79, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x6, TRCPIDR1"
+
+  -
+    input:
+      bytes: [ 0xeb, 0x7a, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x11, TRCPIDR2"
+
+  -
+    input:
+      bytes: [ 0xf4, 0x7b, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x20, TRCPIDR3"
+
+  -
+    input:
+      bytes: [ 0xf1, 0x7c, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x17, TRCCIDR0"
+
+  -
+    input:
+      bytes: [ 0xe2, 0x7d, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x2, TRCCIDR1"
+
+  -
+    input:
+      bytes: [ 0xf4, 0x7e, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x20, TRCCIDR2"
+
+  -
+    input:
+      bytes: [ 0xe4, 0x7f, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x4, TRCCIDR3"
+
+  -
+    input:
+      bytes: [ 0x0b, 0x01, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x11, TRCPRGCTLR"
+
+  -
+    input:
+      bytes: [ 0x17, 0x02, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x23, TRCPROCSELR"
+
+  -
+    input:
+      bytes: [ 0x0d, 0x04, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x13, TRCCONFIGR"
+
+  -
+    input:
+      bytes: [ 0x17, 0x06, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x23, TRCAUXCTLR"
+
+  -
+    input:
+      bytes: [ 0x09, 0x08, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, TRCEVENTCTL0R"
+
+  -
+    input:
+      bytes: [ 0x10, 0x09, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x16, TRCEVENTCTL1R"
+
+  -
+    input:
+      bytes: [ 0x04, 0x0b, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x4, TRCSTALLCTLR"
+
+  -
+    input:
+      bytes: [ 0x0e, 0x0c, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x14, TRCTSCTLR"
+
+  -
+    input:
+      bytes: [ 0x18, 0x0d, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x24, TRCSYNCPR"
+
+  -
+    input:
+      bytes: [ 0x1c, 0x0e, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x28, TRCCCCTLR"
+
+  -
+    input:
+      bytes: [ 0x0f, 0x0f, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x15, TRCBBCTLR"
+
+  -
+    input:
+      bytes: [ 0x21, 0x00, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x1, TRCTRACEIDR"
+
+  -
+    input:
+      bytes: [ 0x34, 0x01, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x20, TRCQCTLR"
+
+  -
+    input:
+      bytes: [ 0x42, 0x00, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x2, TRCVICTLR"
+
+  -
+    input:
+      bytes: [ 0x4c, 0x01, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x12, TRCVIIECTLR"
+
+  -
+    input:
+      bytes: [ 0x50, 0x02, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x16, TRCVISSCTLR"
+
+  -
+    input:
+      bytes: [ 0x48, 0x03, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x8, TRCVIPCSSCTLR"
+
+  -
+    input:
+      bytes: [ 0x5b, 0x08, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x27, TRCVDCTLR"
+
+  -
+    input:
+      bytes: [ 0x49, 0x09, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, TRCVDSACCTLR"
+
+  -
+    input:
+      bytes: [ 0x40, 0x0a, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, TRCVDARCCTLR"
+
+  -
+    input:
+      bytes: [ 0x8d, 0x00, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x13, TRCSEQEVR0"
+
+  -
+    input:
+      bytes: [ 0x8b, 0x01, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x11, TRCSEQEVR1"
+
+  -
+    input:
+      bytes: [ 0x9a, 0x02, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x26, TRCSEQEVR2"
+
+  -
+    input:
+      bytes: [ 0x8e, 0x06, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x14, TRCSEQRSTEVR"
+
+  -
+    input:
+      bytes: [ 0x84, 0x07, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x4, TRCSEQSTR"
+
+  -
+    input:
+      bytes: [ 0x91, 0x08, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x17, TRCEXTINSELR"
+
+  -
+    input:
+      bytes: [ 0xb5, 0x00, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x21, TRCCNTRLDVR0"
+
+  -
+    input:
+      bytes: [ 0xaa, 0x01, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x10, TRCCNTRLDVR1"
+
+  -
+    input:
+      bytes: [ 0xb4, 0x02, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x20, TRCCNTRLDVR2"
+
+  -
+    input:
+      bytes: [ 0xa5, 0x03, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x5, TRCCNTRLDVR3"
+
+  -
+    input:
+      bytes: [ 0xb1, 0x04, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x17, TRCCNTCTLR0"
+
+  -
+    input:
+      bytes: [ 0xa1, 0x05, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x1, TRCCNTCTLR1"
+
+  -
+    input:
+      bytes: [ 0xb1, 0x06, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x17, TRCCNTCTLR2"
+
+  -
+    input:
+      bytes: [ 0xa6, 0x07, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x6, TRCCNTCTLR3"
+
+  -
+    input:
+      bytes: [ 0xbc, 0x08, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x28, TRCCNTVR0"
+
+  -
+    input:
+      bytes: [ 0xb7, 0x09, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x23, TRCCNTVR1"
+
+  -
+    input:
+      bytes: [ 0xa9, 0x0a, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, TRCCNTVR2"
+
+  -
+    input:
+      bytes: [ 0xa6, 0x0b, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x6, TRCCNTVR3"
+
+  -
+    input:
+      bytes: [ 0xf8, 0x00, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x24, TRCIMSPEC0"
+
+  -
+    input:
+      bytes: [ 0xf8, 0x01, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x24, TRCIMSPEC1"
+
+  -
+    input:
+      bytes: [ 0xef, 0x02, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x15, TRCIMSPEC2"
+
+  -
+    input:
+      bytes: [ 0xea, 0x03, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x10, TRCIMSPEC3"
+
+  -
+    input:
+      bytes: [ 0xfd, 0x04, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x29, TRCIMSPEC4"
+
+  -
+    input:
+      bytes: [ 0xf2, 0x05, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x18, TRCIMSPEC5"
+
+  -
+    input:
+      bytes: [ 0xfd, 0x06, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x29, TRCIMSPEC6"
+
+  -
+    input:
+      bytes: [ 0xe2, 0x07, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x2, TRCIMSPEC7"
+
+  -
+    input:
+      bytes: [ 0x08, 0x12, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x8, TRCRSCTLR2"
+
+  -
+    input:
+      bytes: [ 0x00, 0x13, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, TRCRSCTLR3"
+
+  -
+    input:
+      bytes: [ 0x0c, 0x14, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x12, TRCRSCTLR4"
+
+  -
+    input:
+      bytes: [ 0x1a, 0x15, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x26, TRCRSCTLR5"
+
+  -
+    input:
+      bytes: [ 0x1d, 0x16, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x29, TRCRSCTLR6"
+
+  -
+    input:
+      bytes: [ 0x11, 0x17, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x17, TRCRSCTLR7"
+
+  -
+    input:
+      bytes: [ 0x00, 0x18, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, TRCRSCTLR8"
+
+  -
+    input:
+      bytes: [ 0x01, 0x19, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x1, TRCRSCTLR9"
+
+  -
+    input:
+      bytes: [ 0x11, 0x1a, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x17, TRCRSCTLR10"
+
+  -
+    input:
+      bytes: [ 0x15, 0x1b, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x21, TRCRSCTLR11"
+
+  -
+    input:
+      bytes: [ 0x01, 0x1c, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x1, TRCRSCTLR12"
+
+  -
+    input:
+      bytes: [ 0x08, 0x1d, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x8, TRCRSCTLR13"
+
+  -
+    input:
+      bytes: [ 0x18, 0x1e, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x24, TRCRSCTLR14"
+
+  -
+    input:
+      bytes: [ 0x00, 0x1f, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, TRCRSCTLR15"
+
+  -
+    input:
+      bytes: [ 0x22, 0x10, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x2, TRCRSCTLR16"
+
+  -
+    input:
+      bytes: [ 0x3d, 0x11, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x29, TRCRSCTLR17"
+
+  -
+    input:
+      bytes: [ 0x36, 0x12, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x22, TRCRSCTLR18"
+
+  -
+    input:
+      bytes: [ 0x26, 0x13, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x6, TRCRSCTLR19"
+
+  -
+    input:
+      bytes: [ 0x3a, 0x14, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x26, TRCRSCTLR20"
+
+  -
+    input:
+      bytes: [ 0x3a, 0x15, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x26, TRCRSCTLR21"
+
+  -
+    input:
+      bytes: [ 0x24, 0x16, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x4, TRCRSCTLR22"
+
+  -
+    input:
+      bytes: [ 0x2c, 0x17, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x12, TRCRSCTLR23"
+
+  -
+    input:
+      bytes: [ 0x21, 0x18, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x1, TRCRSCTLR24"
+
+  -
+    input:
+      bytes: [ 0x20, 0x19, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, TRCRSCTLR25"
+
+  -
+    input:
+      bytes: [ 0x31, 0x1a, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x17, TRCRSCTLR26"
+
+  -
+    input:
+      bytes: [ 0x28, 0x1b, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x8, TRCRSCTLR27"
+
+  -
+    input:
+      bytes: [ 0x2a, 0x1c, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x10, TRCRSCTLR28"
+
+  -
+    input:
+      bytes: [ 0x39, 0x1d, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x25, TRCRSCTLR29"
+
+  -
+    input:
+      bytes: [ 0x2c, 0x1e, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x12, TRCRSCTLR30"
+
+  -
+    input:
+      bytes: [ 0x2b, 0x1f, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x11, TRCRSCTLR31"
+
+  -
+    input:
+      bytes: [ 0x52, 0x10, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x18, TRCSSCCR0"
+
+  -
+    input:
+      bytes: [ 0x4c, 0x11, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x12, TRCSSCCR1"
+
+  -
+    input:
+      bytes: [ 0x43, 0x12, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, TRCSSCCR2"
+
+  -
+    input:
+      bytes: [ 0x42, 0x13, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x2, TRCSSCCR3"
+
+  -
+    input:
+      bytes: [ 0x55, 0x14, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x21, TRCSSCCR4"
+
+  -
+    input:
+      bytes: [ 0x4a, 0x15, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x10, TRCSSCCR5"
+
+  -
+    input:
+      bytes: [ 0x56, 0x16, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x22, TRCSSCCR6"
+
+  -
+    input:
+      bytes: [ 0x57, 0x17, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x23, TRCSSCCR7"
+
+  -
+    input:
+      bytes: [ 0x57, 0x18, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x23, TRCSSCSR0"
+
+  -
+    input:
+      bytes: [ 0x53, 0x19, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x19, TRCSSCSR1"
+
+  -
+    input:
+      bytes: [ 0x59, 0x1a, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x25, TRCSSCSR2"
+
+  -
+    input:
+      bytes: [ 0x51, 0x1b, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x17, TRCSSCSR3"
+
+  -
+    input:
+      bytes: [ 0x53, 0x1c, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x19, TRCSSCSR4"
+
+  -
+    input:
+      bytes: [ 0x4b, 0x1d, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x11, TRCSSCSR5"
+
+  -
+    input:
+      bytes: [ 0x45, 0x1e, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x5, TRCSSCSR6"
+
+  -
+    input:
+      bytes: [ 0x49, 0x1f, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, TRCSSCSR7"
+
+  -
+    input:
+      bytes: [ 0x61, 0x10, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x1, TRCSSPCICR0"
+
+  -
+    input:
+      bytes: [ 0x6c, 0x11, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x12, TRCSSPCICR1"
+
+  -
+    input:
+      bytes: [ 0x75, 0x12, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x21, TRCSSPCICR2"
+
+  -
+    input:
+      bytes: [ 0x6b, 0x13, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x11, TRCSSPCICR3"
+
+  -
+    input:
+      bytes: [ 0x63, 0x14, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, TRCSSPCICR4"
+
+  -
+    input:
+      bytes: [ 0x69, 0x15, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, TRCSSPCICR5"
+
+  -
+    input:
+      bytes: [ 0x65, 0x16, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x5, TRCSSPCICR6"
+
+  -
+    input:
+      bytes: [ 0x62, 0x17, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x2, TRCSSPCICR7"
+
+  -
+    input:
+      bytes: [ 0x9a, 0x14, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x26, TRCPDCR"
+
+  -
+    input:
+      bytes: [ 0x08, 0x20, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x8, TRCACVR0"
+
+  -
+    input:
+      bytes: [ 0x0f, 0x22, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x15, TRCACVR1"
+
+  -
+    input:
+      bytes: [ 0x13, 0x24, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x19, TRCACVR2"
+
+  -
+    input:
+      bytes: [ 0x08, 0x26, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x8, TRCACVR3"
+
+  -
+    input:
+      bytes: [ 0x1c, 0x28, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x28, TRCACVR4"
+
+  -
+    input:
+      bytes: [ 0x03, 0x2a, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, TRCACVR5"
+
+  -
+    input:
+      bytes: [ 0x19, 0x2c, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x25, TRCACVR6"
+
+  -
+    input:
+      bytes: [ 0x18, 0x2e, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x24, TRCACVR7"
+
+  -
+    input:
+      bytes: [ 0x26, 0x20, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x6, TRCACVR8"
+
+  -
+    input:
+      bytes: [ 0x23, 0x22, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, TRCACVR9"
+
+  -
+    input:
+      bytes: [ 0x38, 0x24, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x24, TRCACVR10"
+
+  -
+    input:
+      bytes: [ 0x23, 0x26, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, TRCACVR11"
+
+  -
+    input:
+      bytes: [ 0x2c, 0x28, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x12, TRCACVR12"
+
+  -
+    input:
+      bytes: [ 0x29, 0x2a, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, TRCACVR13"
+
+  -
+    input:
+      bytes: [ 0x2e, 0x2c, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x14, TRCACVR14"
+
+  -
+    input:
+      bytes: [ 0x23, 0x2e, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x3, TRCACVR15"
+
+  -
+    input:
+      bytes: [ 0x55, 0x20, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x21, TRCACATR0"
+
+  -
+    input:
+      bytes: [ 0x5a, 0x22, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x26, TRCACATR1"
+
+  -
+    input:
+      bytes: [ 0x48, 0x24, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x8, TRCACATR2"
+
+  -
+    input:
+      bytes: [ 0x56, 0x26, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x22, TRCACATR3"
+
+  -
+    input:
+      bytes: [ 0x46, 0x28, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x6, TRCACATR4"
+
+  -
+    input:
+      bytes: [ 0x5d, 0x2a, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x29, TRCACATR5"
+
+  -
+    input:
+      bytes: [ 0x45, 0x2c, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x5, TRCACATR6"
+
+  -
+    input:
+      bytes: [ 0x52, 0x2e, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x18, TRCACATR7"
+
+  -
+    input:
+      bytes: [ 0x62, 0x20, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x2, TRCACATR8"
+
+  -
+    input:
+      bytes: [ 0x73, 0x22, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x19, TRCACATR9"
+
+  -
+    input:
+      bytes: [ 0x6d, 0x24, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x13, TRCACATR10"
+
+  -
+    input:
+      bytes: [ 0x79, 0x26, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x25, TRCACATR11"
+
+  -
+    input:
+      bytes: [ 0x72, 0x28, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x18, TRCACATR12"
+
+  -
+    input:
+      bytes: [ 0x7d, 0x2a, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x29, TRCACATR13"
+
+  -
+    input:
+      bytes: [ 0x69, 0x2c, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, TRCACATR14"
+
+  -
+    input:
+      bytes: [ 0x72, 0x2e, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x18, TRCACATR15"
+
+  -
+    input:
+      bytes: [ 0x9d, 0x20, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x29, TRCDVCVR0"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x24, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x15, TRCDVCVR1"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x28, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x15, TRCDVCVR2"
+
+  -
+    input:
+      bytes: [ 0x8f, 0x2c, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x15, TRCDVCVR3"
+
+  -
+    input:
+      bytes: [ 0xb3, 0x20, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x19, TRCDVCVR4"
+
+  -
+    input:
+      bytes: [ 0xb6, 0x24, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x22, TRCDVCVR5"
+
+  -
+    input:
+      bytes: [ 0xbb, 0x28, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x27, TRCDVCVR6"
+
+  -
+    input:
+      bytes: [ 0xa1, 0x2c, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x1, TRCDVCVR7"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x20, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x29, TRCDVCMR0"
+
+  -
+    input:
+      bytes: [ 0xc9, 0x24, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, TRCDVCMR1"
+
+  -
+    input:
+      bytes: [ 0xc1, 0x28, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x1, TRCDVCMR2"
+
+  -
+    input:
+      bytes: [ 0xc2, 0x2c, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x2, TRCDVCMR3"
+
+  -
+    input:
+      bytes: [ 0xe5, 0x20, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x5, TRCDVCMR4"
+
+  -
+    input:
+      bytes: [ 0xf5, 0x24, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x21, TRCDVCMR5"
+
+  -
+    input:
+      bytes: [ 0xe5, 0x28, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x5, TRCDVCMR6"
+
+  -
+    input:
+      bytes: [ 0xe1, 0x2c, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x1, TRCDVCMR7"
+
+  -
+    input:
+      bytes: [ 0x15, 0x30, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x21, TRCCIDCVR0"
+
+  -
+    input:
+      bytes: [ 0x18, 0x32, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x24, TRCCIDCVR1"
+
+  -
+    input:
+      bytes: [ 0x18, 0x34, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x24, TRCCIDCVR2"
+
+  -
+    input:
+      bytes: [ 0x0c, 0x36, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x12, TRCCIDCVR3"
+
+  -
+    input:
+      bytes: [ 0x0a, 0x38, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x10, TRCCIDCVR4"
+
+  -
+    input:
+      bytes: [ 0x09, 0x3a, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, TRCCIDCVR5"
+
+  -
+    input:
+      bytes: [ 0x06, 0x3c, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x6, TRCCIDCVR6"
+
+  -
+    input:
+      bytes: [ 0x14, 0x3e, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x20, TRCCIDCVR7"
+
+  -
+    input:
+      bytes: [ 0x34, 0x30, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x20, TRCVMIDCVR0"
+
+  -
+    input:
+      bytes: [ 0x34, 0x32, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x20, TRCVMIDCVR1"
+
+  -
+    input:
+      bytes: [ 0x3a, 0x34, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x26, TRCVMIDCVR2"
+
+  -
+    input:
+      bytes: [ 0x21, 0x36, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x1, TRCVMIDCVR3"
+
+  -
+    input:
+      bytes: [ 0x2e, 0x38, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x14, TRCVMIDCVR4"
+
+  -
+    input:
+      bytes: [ 0x3b, 0x3a, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x27, TRCVMIDCVR5"
+
+  -
+    input:
+      bytes: [ 0x3d, 0x3c, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x29, TRCVMIDCVR6"
+
+  -
+    input:
+      bytes: [ 0x31, 0x3e, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x17, TRCVMIDCVR7"
+
+  -
+    input:
+      bytes: [ 0x4a, 0x30, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x10, TRCCIDCCTLR0"
+
+  -
+    input:
+      bytes: [ 0x44, 0x31, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x4, TRCCIDCCTLR1"
+
+  -
+    input:
+      bytes: [ 0x49, 0x32, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, TRCVMIDCCTLR0"
+
+  -
+    input:
+      bytes: [ 0x4b, 0x33, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x11, TRCVMIDCCTLR1"
+
+  -
+    input:
+      bytes: [ 0x96, 0x70, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x22, TRCITCTRL"
+
+  -
+    input:
+      bytes: [ 0xd7, 0x78, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x23, TRCCLAIMSET"
+
+  -
+    input:
+      bytes: [ 0xce, 0x79, 0x31, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x14, TRCCLAIMCLR"
+
+  -
+    input:
+      bytes: [ 0x9c, 0x10, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCOSLAR, x28"
+
+  -
+    input:
+      bytes: [ 0xce, 0x7c, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCLAR, x14"
+
+  -
+    input:
+      bytes: [ 0x0a, 0x01, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCPRGCTLR, x10"
+
+  -
+    input:
+      bytes: [ 0x1b, 0x02, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCPROCSELR, x27"
+
+  -
+    input:
+      bytes: [ 0x18, 0x04, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCCONFIGR, x24"
+
+  -
+    input:
+      bytes: [ 0x08, 0x06, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCAUXCTLR, x8"
+
+  -
+    input:
+      bytes: [ 0x10, 0x08, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCEVENTCTL0R, x16"
+
+  -
+    input:
+      bytes: [ 0x1b, 0x09, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCEVENTCTL1R, x27"
+
+  -
+    input:
+      bytes: [ 0x1a, 0x0b, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCSTALLCTLR, x26"
+
+  -
+    input:
+      bytes: [ 0x00, 0x0c, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCTSCTLR, x0"
+
+  -
+    input:
+      bytes: [ 0x0e, 0x0d, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCSYNCPR, x14"
+
+  -
+    input:
+      bytes: [ 0x08, 0x0e, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCCCCTLR, x8"
+
+  -
+    input:
+      bytes: [ 0x06, 0x0f, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCBBCTLR, x6"
+
+  -
+    input:
+      bytes: [ 0x37, 0x00, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCTRACEIDR, x23"
+
+  -
+    input:
+      bytes: [ 0x25, 0x01, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCQCTLR, x5"
+
+  -
+    input:
+      bytes: [ 0x40, 0x00, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCVICTLR, x0"
+
+  -
+    input:
+      bytes: [ 0x40, 0x01, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCVIIECTLR, x0"
+
+  -
+    input:
+      bytes: [ 0x41, 0x02, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCVISSCTLR, x1"
+
+  -
+    input:
+      bytes: [ 0x40, 0x03, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCVIPCSSCTLR, x0"
+
+  -
+    input:
+      bytes: [ 0x47, 0x08, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCVDCTLR, x7"
+
+  -
+    input:
+      bytes: [ 0x52, 0x09, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCVDSACCTLR, x18"
+
+  -
+    input:
+      bytes: [ 0x58, 0x0a, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCVDARCCTLR, x24"
+
+  -
+    input:
+      bytes: [ 0x9c, 0x00, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCSEQEVR0, x28"
+
+  -
+    input:
+      bytes: [ 0x95, 0x01, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCSEQEVR1, x21"
+
+  -
+    input:
+      bytes: [ 0x90, 0x02, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCSEQEVR2, x16"
+
+  -
+    input:
+      bytes: [ 0x90, 0x06, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCSEQRSTEVR, x16"
+
+  -
+    input:
+      bytes: [ 0x99, 0x07, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCSEQSTR, x25"
+
+  -
+    input:
+      bytes: [ 0x9d, 0x08, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCEXTINSELR, x29"
+
+  -
+    input:
+      bytes: [ 0xb4, 0x00, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCCNTRLDVR0, x20"
+
+  -
+    input:
+      bytes: [ 0xb4, 0x01, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCCNTRLDVR1, x20"
+
+  -
+    input:
+      bytes: [ 0xb6, 0x02, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCCNTRLDVR2, x22"
+
+  -
+    input:
+      bytes: [ 0xac, 0x03, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCCNTRLDVR3, x12"
+
+  -
+    input:
+      bytes: [ 0xb4, 0x04, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCCNTCTLR0, x20"
+
+  -
+    input:
+      bytes: [ 0xa4, 0x05, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCCNTCTLR1, x4"
+
+  -
+    input:
+      bytes: [ 0xa8, 0x06, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCCNTCTLR2, x8"
+
+  -
+    input:
+      bytes: [ 0xb0, 0x07, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCCNTCTLR3, x16"
+
+  -
+    input:
+      bytes: [ 0xa5, 0x08, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCCNTVR0, x5"
+
+  -
+    input:
+      bytes: [ 0xbb, 0x09, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCCNTVR1, x27"
+
+  -
+    input:
+      bytes: [ 0xb5, 0x0a, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCCNTVR2, x21"
+
+  -
+    input:
+      bytes: [ 0xa8, 0x0b, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCCNTVR3, x8"
+
+  -
+    input:
+      bytes: [ 0xe6, 0x00, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCIMSPEC0, x6"
+
+  -
+    input:
+      bytes: [ 0xfb, 0x01, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCIMSPEC1, x27"
+
+  -
+    input:
+      bytes: [ 0xf7, 0x02, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCIMSPEC2, x23"
+
+  -
+    input:
+      bytes: [ 0xef, 0x03, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCIMSPEC3, x15"
+
+  -
+    input:
+      bytes: [ 0xed, 0x04, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCIMSPEC4, x13"
+
+  -
+    input:
+      bytes: [ 0xf9, 0x05, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCIMSPEC5, x25"
+
+  -
+    input:
+      bytes: [ 0xf3, 0x06, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCIMSPEC6, x19"
+
+  -
+    input:
+      bytes: [ 0xfb, 0x07, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCIMSPEC7, x27"
+
+  -
+    input:
+      bytes: [ 0x04, 0x12, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCRSCTLR2, x4"
+
+  -
+    input:
+      bytes: [ 0x00, 0x13, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCRSCTLR3, x0"
+
+  -
+    input:
+      bytes: [ 0x15, 0x14, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCRSCTLR4, x21"
+
+  -
+    input:
+      bytes: [ 0x08, 0x15, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCRSCTLR5, x8"
+
+  -
+    input:
+      bytes: [ 0x14, 0x16, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCRSCTLR6, x20"
+
+  -
+    input:
+      bytes: [ 0x0b, 0x17, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCRSCTLR7, x11"
+
+  -
+    input:
+      bytes: [ 0x12, 0x18, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCRSCTLR8, x18"
+
+  -
+    input:
+      bytes: [ 0x18, 0x19, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCRSCTLR9, x24"
+
+  -
+    input:
+      bytes: [ 0x0f, 0x1a, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCRSCTLR10, x15"
+
+  -
+    input:
+      bytes: [ 0x15, 0x1b, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCRSCTLR11, x21"
+
+  -
+    input:
+      bytes: [ 0x04, 0x1c, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCRSCTLR12, x4"
+
+  -
+    input:
+      bytes: [ 0x1c, 0x1d, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCRSCTLR13, x28"
+
+  -
+    input:
+      bytes: [ 0x03, 0x1e, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCRSCTLR14, x3"
+
+  -
+    input:
+      bytes: [ 0x14, 0x1f, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCRSCTLR15, x20"
+
+  -
+    input:
+      bytes: [ 0x2c, 0x10, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCRSCTLR16, x12"
+
+  -
+    input:
+      bytes: [ 0x31, 0x11, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCRSCTLR17, x17"
+
+  -
+    input:
+      bytes: [ 0x2a, 0x12, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCRSCTLR18, x10"
+
+  -
+    input:
+      bytes: [ 0x2b, 0x13, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCRSCTLR19, x11"
+
+  -
+    input:
+      bytes: [ 0x23, 0x14, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCRSCTLR20, x3"
+
+  -
+    input:
+      bytes: [ 0x32, 0x15, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCRSCTLR21, x18"
+
+  -
+    input:
+      bytes: [ 0x3a, 0x16, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCRSCTLR22, x26"
+
+  -
+    input:
+      bytes: [ 0x25, 0x17, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCRSCTLR23, x5"
+
+  -
+    input:
+      bytes: [ 0x39, 0x18, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCRSCTLR24, x25"
+
+  -
+    input:
+      bytes: [ 0x25, 0x19, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCRSCTLR25, x5"
+
+  -
+    input:
+      bytes: [ 0x24, 0x1a, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCRSCTLR26, x4"
+
+  -
+    input:
+      bytes: [ 0x34, 0x1b, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCRSCTLR27, x20"
+
+  -
+    input:
+      bytes: [ 0x25, 0x1c, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCRSCTLR28, x5"
+
+  -
+    input:
+      bytes: [ 0x2a, 0x1d, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCRSCTLR29, x10"
+
+  -
+    input:
+      bytes: [ 0x38, 0x1e, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCRSCTLR30, x24"
+
+  -
+    input:
+      bytes: [ 0x34, 0x1f, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCRSCTLR31, x20"
+
+  -
+    input:
+      bytes: [ 0x57, 0x10, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCSSCCR0, x23"
+
+  -
+    input:
+      bytes: [ 0x5b, 0x11, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCSSCCR1, x27"
+
+  -
+    input:
+      bytes: [ 0x5b, 0x12, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCSSCCR2, x27"
+
+  -
+    input:
+      bytes: [ 0x46, 0x13, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCSSCCR3, x6"
+
+  -
+    input:
+      bytes: [ 0x43, 0x14, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCSSCCR4, x3"
+
+  -
+    input:
+      bytes: [ 0x4c, 0x15, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCSSCCR5, x12"
+
+  -
+    input:
+      bytes: [ 0x47, 0x16, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCSSCCR6, x7"
+
+  -
+    input:
+      bytes: [ 0x46, 0x17, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCSSCCR7, x6"
+
+  -
+    input:
+      bytes: [ 0x54, 0x18, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCSSCSR0, x20"
+
+  -
+    input:
+      bytes: [ 0x51, 0x19, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCSSCSR1, x17"
+
+  -
+    input:
+      bytes: [ 0x4b, 0x1a, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCSSCSR2, x11"
+
+  -
+    input:
+      bytes: [ 0x44, 0x1b, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCSSCSR3, x4"
+
+  -
+    input:
+      bytes: [ 0x4e, 0x1c, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCSSCSR4, x14"
+
+  -
+    input:
+      bytes: [ 0x56, 0x1d, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCSSCSR5, x22"
+
+  -
+    input:
+      bytes: [ 0x43, 0x1e, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCSSCSR6, x3"
+
+  -
+    input:
+      bytes: [ 0x4b, 0x1f, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCSSCSR7, x11"
+
+  -
+    input:
+      bytes: [ 0x62, 0x10, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCSSPCICR0, x2"
+
+  -
+    input:
+      bytes: [ 0x63, 0x11, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCSSPCICR1, x3"
+
+  -
+    input:
+      bytes: [ 0x65, 0x12, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCSSPCICR2, x5"
+
+  -
+    input:
+      bytes: [ 0x67, 0x13, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCSSPCICR3, x7"
+
+  -
+    input:
+      bytes: [ 0x6b, 0x14, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCSSPCICR4, x11"
+
+  -
+    input:
+      bytes: [ 0x6d, 0x15, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCSSPCICR5, x13"
+
+  -
+    input:
+      bytes: [ 0x71, 0x16, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCSSPCICR6, x17"
+
+  -
+    input:
+      bytes: [ 0x77, 0x17, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCSSPCICR7, x23"
+
+  -
+    input:
+      bytes: [ 0x83, 0x14, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCPDCR, x3"
+
+  -
+    input:
+      bytes: [ 0x06, 0x20, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCACVR0, x6"
+
+  -
+    input:
+      bytes: [ 0x14, 0x22, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCACVR1, x20"
+
+  -
+    input:
+      bytes: [ 0x19, 0x24, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCACVR2, x25"
+
+  -
+    input:
+      bytes: [ 0x01, 0x26, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCACVR3, x1"
+
+  -
+    input:
+      bytes: [ 0x1c, 0x28, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCACVR4, x28"
+
+  -
+    input:
+      bytes: [ 0x0f, 0x2a, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCACVR5, x15"
+
+  -
+    input:
+      bytes: [ 0x19, 0x2c, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCACVR6, x25"
+
+  -
+    input:
+      bytes: [ 0x0c, 0x2e, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCACVR7, x12"
+
+  -
+    input:
+      bytes: [ 0x25, 0x20, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCACVR8, x5"
+
+  -
+    input:
+      bytes: [ 0x39, 0x22, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCACVR9, x25"
+
+  -
+    input:
+      bytes: [ 0x2d, 0x24, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCACVR10, x13"
+
+  -
+    input:
+      bytes: [ 0x2a, 0x26, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCACVR11, x10"
+
+  -
+    input:
+      bytes: [ 0x33, 0x28, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCACVR12, x19"
+
+  -
+    input:
+      bytes: [ 0x2a, 0x2a, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCACVR13, x10"
+
+  -
+    input:
+      bytes: [ 0x33, 0x2c, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCACVR14, x19"
+
+  -
+    input:
+      bytes: [ 0x22, 0x2e, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCACVR15, x2"
+
+  -
+    input:
+      bytes: [ 0x4f, 0x20, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCACATR0, x15"
+
+  -
+    input:
+      bytes: [ 0x4d, 0x22, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCACATR1, x13"
+
+  -
+    input:
+      bytes: [ 0x48, 0x24, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCACATR2, x8"
+
+  -
+    input:
+      bytes: [ 0x41, 0x26, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCACATR3, x1"
+
+  -
+    input:
+      bytes: [ 0x4b, 0x28, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCACATR4, x11"
+
+  -
+    input:
+      bytes: [ 0x48, 0x2a, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCACATR5, x8"
+
+  -
+    input:
+      bytes: [ 0x58, 0x2c, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCACATR6, x24"
+
+  -
+    input:
+      bytes: [ 0x46, 0x2e, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCACATR7, x6"
+
+  -
+    input:
+      bytes: [ 0x77, 0x20, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCACATR8, x23"
+
+  -
+    input:
+      bytes: [ 0x65, 0x22, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCACATR9, x5"
+
+  -
+    input:
+      bytes: [ 0x6b, 0x24, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCACATR10, x11"
+
+  -
+    input:
+      bytes: [ 0x6b, 0x26, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCACATR11, x11"
+
+  -
+    input:
+      bytes: [ 0x63, 0x28, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCACATR12, x3"
+
+  -
+    input:
+      bytes: [ 0x7c, 0x2a, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCACATR13, x28"
+
+  -
+    input:
+      bytes: [ 0x79, 0x2c, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCACATR14, x25"
+
+  -
+    input:
+      bytes: [ 0x64, 0x2e, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCACATR15, x4"
+
+  -
+    input:
+      bytes: [ 0x86, 0x20, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCDVCVR0, x6"
+
+  -
+    input:
+      bytes: [ 0x83, 0x24, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCDVCVR1, x3"
+
+  -
+    input:
+      bytes: [ 0x85, 0x28, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCDVCVR2, x5"
+
+  -
+    input:
+      bytes: [ 0x8b, 0x2c, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCDVCVR3, x11"
+
+  -
+    input:
+      bytes: [ 0xa9, 0x20, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCDVCVR4, x9"
+
+  -
+    input:
+      bytes: [ 0xae, 0x24, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCDVCVR5, x14"
+
+  -
+    input:
+      bytes: [ 0xaa, 0x28, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCDVCVR6, x10"
+
+  -
+    input:
+      bytes: [ 0xac, 0x2c, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCDVCVR7, x12"
+
+  -
+    input:
+      bytes: [ 0xc8, 0x20, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCDVCMR0, x8"
+
+  -
+    input:
+      bytes: [ 0xc8, 0x24, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCDVCMR1, x8"
+
+  -
+    input:
+      bytes: [ 0xd6, 0x28, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCDVCMR2, x22"
+
+  -
+    input:
+      bytes: [ 0xd6, 0x2c, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCDVCMR3, x22"
+
+  -
+    input:
+      bytes: [ 0xe5, 0x20, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCDVCMR4, x5"
+
+  -
+    input:
+      bytes: [ 0xf0, 0x24, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCDVCMR5, x16"
+
+  -
+    input:
+      bytes: [ 0xfb, 0x28, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCDVCMR6, x27"
+
+  -
+    input:
+      bytes: [ 0xf5, 0x2c, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCDVCMR7, x21"
+
+  -
+    input:
+      bytes: [ 0x08, 0x30, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCCIDCVR0, x8"
+
+  -
+    input:
+      bytes: [ 0x06, 0x32, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCCIDCVR1, x6"
+
+  -
+    input:
+      bytes: [ 0x09, 0x34, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCCIDCVR2, x9"
+
+  -
+    input:
+      bytes: [ 0x08, 0x36, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCCIDCVR3, x8"
+
+  -
+    input:
+      bytes: [ 0x03, 0x38, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCCIDCVR4, x3"
+
+  -
+    input:
+      bytes: [ 0x15, 0x3a, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCCIDCVR5, x21"
+
+  -
+    input:
+      bytes: [ 0x0c, 0x3c, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCCIDCVR6, x12"
+
+  -
+    input:
+      bytes: [ 0x07, 0x3e, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCCIDCVR7, x7"
+
+  -
+    input:
+      bytes: [ 0x24, 0x30, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCVMIDCVR0, x4"
+
+  -
+    input:
+      bytes: [ 0x23, 0x32, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCVMIDCVR1, x3"
+
+  -
+    input:
+      bytes: [ 0x29, 0x34, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCVMIDCVR2, x9"
+
+  -
+    input:
+      bytes: [ 0x31, 0x36, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCVMIDCVR3, x17"
+
+  -
+    input:
+      bytes: [ 0x2e, 0x38, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCVMIDCVR4, x14"
+
+  -
+    input:
+      bytes: [ 0x2c, 0x3a, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCVMIDCVR5, x12"
+
+  -
+    input:
+      bytes: [ 0x2a, 0x3c, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCVMIDCVR6, x10"
+
+  -
+    input:
+      bytes: [ 0x23, 0x3e, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCVMIDCVR7, x3"
+
+  -
+    input:
+      bytes: [ 0x4e, 0x30, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCCIDCCTLR0, x14"
+
+  -
+    input:
+      bytes: [ 0x56, 0x31, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCCIDCCTLR1, x22"
+
+  -
+    input:
+      bytes: [ 0x48, 0x32, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCVMIDCCTLR0, x8"
+
+  -
+    input:
+      bytes: [ 0x4f, 0x33, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCVMIDCCTLR1, x15"
+
+  -
+    input:
+      bytes: [ 0x81, 0x70, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCITCTRL, x1"
+
+  -
+    input:
+      bytes: [ 0xc7, 0x78, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCCLAIMSET, x7"
+
+  -
+    input:
+      bytes: [ 0xdd, 0x79, 0x11, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-none-linux-gnu" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRCCLAIMCLR, x29"
diff --git a/tests/MC/AArch64/trbe-sysreg.s.yaml b/tests/MC/AArch64/trbe-sysreg.s.yaml
new file mode 100644
index 000000000..4da848761
--- /dev/null
+++ b/tests/MC/AArch64/trbe-sysreg.s.yaml
@@ -0,0 +1,130 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x9b, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, TRBLIMITR_EL1"
+
+  -
+    input:
+      bytes: [ 0x20, 0x9b, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, TRBPTR_EL1"
+
+  -
+    input:
+      bytes: [ 0x40, 0x9b, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, TRBBASER_EL1"
+
+  -
+    input:
+      bytes: [ 0x60, 0x9b, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, TRBSR_EL1"
+
+  -
+    input:
+      bytes: [ 0x80, 0x9b, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, TRBMAR_EL1"
+
+  -
+    input:
+      bytes: [ 0xc0, 0x9b, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, TRBTRG_EL1"
+
+  -
+    input:
+      bytes: [ 0xe0, 0x9b, 0x38, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs x0, TRBIDR_EL1"
+
+  -
+    input:
+      bytes: [ 0x00, 0x9b, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRBLIMITR_EL1, x0"
+
+  -
+    input:
+      bytes: [ 0x20, 0x9b, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRBPTR_EL1, x0"
+
+  -
+    input:
+      bytes: [ 0x40, 0x9b, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRBBASER_EL1, x0"
+
+  -
+    input:
+      bytes: [ 0x60, 0x9b, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRBSR_EL1, x0"
+
+  -
+    input:
+      bytes: [ 0x80, 0x9b, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRBMAR_EL1, x0"
+
+  -
+    input:
+      bytes: [ 0xc0, 0x9b, 0x18, 0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr TRBTRG_EL1, x0"
diff --git a/tests/MC/AArch64/udf.s.yaml b/tests/MC/AArch64/udf.s.yaml
new file mode 100644
index 000000000..018649e41
--- /dev/null
+++ b/tests/MC/AArch64/udf.s.yaml
@@ -0,0 +1,30 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-" ]
+    expected:
+      insns:
+        -
+          asm_text: "udf #0"
+
+  -
+    input:
+      bytes: [ 0x01, 0x02, 0x00, 0x00 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-" ]
+    expected:
+      insns:
+        -
+          asm_text: "udf #513"
+
+  -
+    input:
+      bytes: [ 0xff, 0xff, 0x00, 0x00 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "aarch64-" ]
+    expected:
+      insns:
+        -
+          asm_text: "udf #65535"
diff --git a/tests/MC/ARM/arm-aliases.s.yaml b/tests/MC/ARM/arm-aliases.s.yaml
new file mode 100644
index 000000000..5338902d5
--- /dev/null
+++ b/tests/MC/ARM/arm-aliases.s.yaml
@@ -0,0 +1,20 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x03, 0x10, 0x82, 0xe0, 0x03, 0x10, 0x42, 0xe0, 0x03, 0x10, 0x22, 0xe0, 0x03, 0x10, 0x82, 0xe1, 0x03, 0x10, 0x02, 0xe0, 0x03, 0x10, 0xc2, 0xe1 ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ]
+    expected:
+      insns:
+        -
+          asm_text: "add r1, r2, r3"
+        -
+          asm_text: "sub r1, r2, r3"
+        -
+          asm_text: "eor r1, r2, r3"
+        -
+          asm_text: "orr r1, r2, r3"
+        -
+          asm_text: "and r1, r2, r3"
+        -
+          asm_text: "bic r1, r2, r3"
diff --git a/tests/MC/ARM/arm-arithmetic-aliases.s.yaml b/tests/MC/ARM/arm-arithmetic-aliases.s.yaml
new file mode 100644
index 000000000..a1788540c
--- /dev/null
+++ b/tests/MC/ARM/arm-arithmetic-aliases.s.yaml
@@ -0,0 +1,106 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x06, 0x20, 0x42, 0xe2, 0x06, 0x20, 0x42, 0xe2, 0x03, 0x20, 0x42, 0xe0, 0x03, 0x20, 0x42, 0xe0, 0x06, 0x20, 0x82, 0xe2, 0x06, 0x20, 0x82, 0xe2, 0x03, 0x20, 0x82, 0xe0, 0x03, 0x20, 0x82, 0xe0, 0x06, 0x20, 0x02, 0xe2, 0x06, 0x20, 0x02, 0xe2, 0x03, 0x20, 0x02, 0xe0, 0x03, 0x20, 0x02, 0xe0, 0x06, 0x20, 0x82, 0xe3, 0x06, 0x20, 0x82, 0xe3, 0x03, 0x20, 0x82, 0xe1, 0x03, 0x20, 0x82, 0xe1, 0x06, 0x20, 0x22, 0xe2, 0x06, 0x20, 0x22, 0xe2, 0x03, 0x20, 0x22, 0xe0, 0x03, 0x20, 0x22, 0xe0, 0x06, 0x20, 0xc2, 0xe3, 0x06, 0x20, 0xc2, 0xe3, 0x03, 0x20, 0xc2, 0xe1, 0x03, 0x20, 0xc2, 0xe1, 0x06, 0x20, 0x52, 0x02, 0x06, 0x20, 0x52, 0x02, 0x03, 0x20, 0x52, 0x00, 0x03, 0x20, 0x52, 0x00, 0x06, 0x20, 0x92, 0x02, 0x06, 0x20, 0x92, 0x02, 0x03, 0x20, 0x92, 0x00, 0x03, 0x20, 0x92, 0x00, 0x06, 0x20, 0x12, 0x02, 0x06, 0x20, 0x12, 0x02, 0x03, 0x20, 0x12, 0x00, 0x03, 0x20, 0x12, 0x00, 0x06, 0x20, 0x92, 0x03, 0x06, 0x20, 0x92, 0x03, 0x03, 0x20, 0x92, 0x01, 0x03, 0x20, 0x92, 0x01, 0x06, 0x20, 0x32, 0x02, 0x06, 0x20, 0x32, 0x02, 0x03, 0x20, 0x32, 0x00, 0x03, 0x20, 0x32, 0x00, 0x06, 0x20, 0xd2, 0x03, 0x06, 0x20, 0xd2, 0x03, 0x03, 0x20, 0xd2, 0x01, 0x03, 0x20, 0xd2, 0x01, 0x7b, 0x00, 0x8f, 0xe2 ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub r2, r2, #6"
+        -
+          asm_text: "sub r2, r2, #6"
+        -
+          asm_text: "sub r2, r2, r3"
+        -
+          asm_text: "sub r2, r2, r3"
+        -
+          asm_text: "add r2, r2, #6"
+        -
+          asm_text: "add r2, r2, #6"
+        -
+          asm_text: "add r2, r2, r3"
+        -
+          asm_text: "add r2, r2, r3"
+        -
+          asm_text: "and r2, r2, #6"
+        -
+          asm_text: "and r2, r2, #6"
+        -
+          asm_text: "and r2, r2, r3"
+        -
+          asm_text: "and r2, r2, r3"
+        -
+          asm_text: "orr r2, r2, #6"
+        -
+          asm_text: "orr r2, r2, #6"
+        -
+          asm_text: "orr r2, r2, r3"
+        -
+          asm_text: "orr r2, r2, r3"
+        -
+          asm_text: "eor r2, r2, #6"
+        -
+          asm_text: "eor r2, r2, #6"
+        -
+          asm_text: "eor r2, r2, r3"
+        -
+          asm_text: "eor r2, r2, r3"
+        -
+          asm_text: "bic r2, r2, #6"
+        -
+          asm_text: "bic r2, r2, #6"
+        -
+          asm_text: "bic r2, r2, r3"
+        -
+          asm_text: "bic r2, r2, r3"
+        -
+          asm_text: "subseq r2, r2, #6"
+        -
+          asm_text: "subseq r2, r2, #6"
+        -
+          asm_text: "subseq r2, r2, r3"
+        -
+          asm_text: "subseq r2, r2, r3"
+        -
+          asm_text: "addseq r2, r2, #6"
+        -
+          asm_text: "addseq r2, r2, #6"
+        -
+          asm_text: "addseq r2, r2, r3"
+        -
+          asm_text: "addseq r2, r2, r3"
+        -
+          asm_text: "andseq r2, r2, #6"
+        -
+          asm_text: "andseq r2, r2, #6"
+        -
+          asm_text: "andseq r2, r2, r3"
+        -
+          asm_text: "andseq r2, r2, r3"
+        -
+          asm_text: "orrseq r2, r2, #6"
+        -
+          asm_text: "orrseq r2, r2, #6"
+        -
+          asm_text: "orrseq r2, r2, r3"
+        -
+          asm_text: "orrseq r2, r2, r3"
+        -
+          asm_text: "eorseq r2, r2, #6"
+        -
+          asm_text: "eorseq r2, r2, #6"
+        -
+          asm_text: "eorseq r2, r2, r3"
+        -
+          asm_text: "eorseq r2, r2, r3"
+        -
+          asm_text: "bicseq r2, r2, #6"
+        -
+          asm_text: "bicseq r2, r2, #6"
+        -
+          asm_text: "bicseq r2, r2, r3"
+        -
+          asm_text: "bicseq r2, r2, r3"
+        -
+          asm_text: "add r0, pc, #0x7b"
diff --git a/tests/MC/ARM/arm-branches.s.yaml b/tests/MC/ARM/arm-branches.s.yaml
new file mode 100644
index 000000000..b443756c8
--- /dev/null
+++ b/tests/MC/ARM/arm-branches.s.yaml
@@ -0,0 +1,18 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0x00, 0xea, 0x01, 0x00, 0x00, 0xeb, 0x01, 0x00, 0x00, 0x0a, 0x00, 0x00, 0x00, 0xfb, 0x01, 0x00, 0x00, 0xea ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ]
+    expected:
+      insns:
+        -
+          asm_text: "b #4"
+        -
+          asm_text: "bl #4"
+        -
+          asm_text: "beq #4"
+        -
+          asm_text: "blx #2"
+        -
+          asm_text: "b #4"
diff --git a/tests/MC/ARM/arm-it-block.s.yaml b/tests/MC/ARM/arm-it-block.s.yaml
new file mode 100644
index 000000000..252fb1874
--- /dev/null
+++ b/tests/MC/ARM/arm-it-block.s.yaml
@@ -0,0 +1,10 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x03, 0x20, 0xa0, 0x01 ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ]
+    expected:
+      insns:
+        -
+          asm_text: "moveq r2, r3"
diff --git a/tests/MC/ARM/arm-memory-instructions.s.yaml b/tests/MC/ARM/arm-memory-instructions.s.yaml
new file mode 100644
index 000000000..8a3d1a40d
--- /dev/null
+++ b/tests/MC/ARM/arm-memory-instructions.s.yaml
@@ -0,0 +1,292 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x50, 0x97, 0xe5, 0x3f, 0x60, 0x93, 0xe5, 0xff, 0x2f, 0xb4, 0xe5, 0x1e, 0x10, 0x92, 0xe4, 0x1e, 0x30, 0x11, 0xe4, 0x00, 0x90, 0x12, 0xe4, 0x01, 0x30, 0x98, 0xe7, 0x03, 0x20, 0x15, 0xe7, 0x09, 0x10, 0xb5, 0xe7, 0x08, 0x60, 0x37, 0xe7, 0xa2, 0x11, 0xb0, 0xe7, 0x02, 0x50, 0x99, 0xe6, 0x06, 0x40, 0x13, 0xe6, 0x82, 0x37, 0x18, 0xe7, 0xc3, 0x17, 0x95, 0xe6, 0x00, 0x30, 0xd8, 0xe5, 0x3f, 0x10, 0xdd, 0xe5, 0xff, 0x9f, 0xf3, 0xe5, 0x16, 0x80, 0xd1, 0xe4, 0x13, 0x20, 0x57, 0xe4, 0x05, 0x90, 0xd8, 0xe7, 0x01, 0x10, 0x55, 0xe7, 0x02, 0x30, 0xf5, 0xe7, 0x03, 0x60, 0x79, 0xe7, 0x04, 0x20, 0xd1, 0xe6, 0x05, 0x80, 0x54, 0xe6, 0x81, 0x77, 0x5c, 0xe7, 0xc9, 0x57, 0xd2, 0xe6, 0x04, 0x30, 0xf1, 0xe4, 0x08, 0x20, 0x78, 0xe4, 0x06, 0x80, 0xf7, 0xe6, 0x06, 0x16, 0x72, 0xe6, 0xd0, 0x20, 0xc5, 0xe1, 0xdf, 0x60, 0xc2, 0xe1, 0xd0, 0x02, 0xe9, 0xe1, 0xd8, 0x60, 0xc1, 0xe0, 0xd0, 0x00, 0xc8, 0xe0, 0xd0, 0x00, 0xc8, 0xe0, 0xd0, 0x00, 0x48, 0xe0, 0xd3, 0x40, 0x81, 0xe1, 0xd2, 0x40, 0xa7, 0xe1, 0xdc, 0x00, 0x88, 0xe0, 0xdc, 0x00, 0x08, 0xe0, 0xb0, 0x30, 0xd4, 0xe1, 0xb4, 0x20, 0xd7, 0xe1, 0xb0, 0x14, 0xf8, 0xe1, 0xb4, 0xc0, 0xdd, 0xe0, 0xb4, 0x60, 0x95, 0xe1, 0xbb, 0x30, 0xb8, 0xe1, 0xb1, 0x10, 0x32, 0xe1, 0xb2, 0x90, 0x97, 0xe0, 0xb2, 0x40, 0x13, 0xe0, 0xb0, 0x98, 0xf7, 0xe0, 0xbb, 0x44, 0x73, 0xe0, 0xb0, 0x40, 0xf3, 0xe0, 0xb2, 0x90, 0xb7, 0xe0, 0xb2, 0x40, 0x33, 0xe0, 0xd0, 0x30, 0xd4, 0xe1, 0xd1, 0x21, 0xd7, 0xe1, 0xdf, 0x1f, 0xf8, 0xe1, 0xd9, 0xc0, 0xdd, 0xe0, 0xd4, 0x60, 0x95, 0xe1, 0xdb, 0x30, 0xb8, 0xe1, 0xd1, 0x10, 0x32, 0xe1, 0xd2, 0x90, 0x97, 0xe0, 0xd2, 0x40, 0x13, 0xe0, 0xd1, 0x50, 0xf6, 0xe0, 0xdc, 0x30, 0x78, 0xe0, 0xd0, 0x50, 0xf6, 0xe0, 0xd5, 0x80, 0xb9, 0xe0, 0xd4, 0x20, 0x31, 0xe0, 0xf0, 0x50, 0xd9, 0xe1, 0xf7, 0x40, 0xd5, 0xe1, 0xf7, 0x33, 0xf6, 0xe1, 0xf9, 0x20, 0x57, 0xe0, 0xf5, 0x30, 0x91, 0xe1, 0xf1, 0x40, 0xb6, 0xe1, 0xf6, 0x50, 0x33, 0xe1, 0xf8, 0x60, 0x99, 0xe0, 0xf3, 0x70, 0x18, 0xe0, 0xf1, 0x50, 0xf6, 0xe0, 0xfc, 0x30, 0x78, 0xe0, 0xf0, 0x50, 0xf6, 0xe0, 0xf5, 0x80, 0xb9, 0xe0, 0xf4, 0x20, 0x31, 0xe0, 0x00, 0x80, 0x8c, 0xe5, 0x0c, 0x70, 0x81, 0xe5, 0x28, 0x30, 0xa5, 0xe5, 0xff, 0x9f, 0x8d, 0xe4, 0x80, 0x10, 0x07, 0xe4, 0x00, 0x10, 0x00, 0xe4, 0x03, 0x90, 0x86, 0xe7, 0x02, 0x80, 0x00, 0xe7, 0x06, 0x70, 0xa1, 0xe7, 0x01, 0x60, 0x2d, 0xe7, 0x09, 0x50, 0x83, 0xe6, 0x05, 0x40, 0x02, 0xe6, 0x02, 0x31, 0x04, 0xe7, 0x43, 0x2c, 0x87, 0xe6, 0x00, 0x90, 0xc2, 0xe5, 0x03, 0x70, 0xc1, 0xe5, 0x95, 0x61, 0xe4, 0xe5, 0x48, 0x50, 0xc7, 0xe4, 0x01, 0x10, 0x4d, 0xe4, 0x09, 0x10, 0xc2, 0xe7, 0x08, 0x20, 0x43, 0xe7, 0x07, 0x30, 0xe4, 0xe7, 0x06, 0x40, 0x65, 0xe7, 0x05, 0x50, 0xc6, 0xe6, 0x04, 0x60, 0x42, 0xe6, 0x83, 0x72, 0x4c, 0xe7, 0x42, 0xd6, 0xc7, 0xe6, 0x0c, 0x60, 0xe2, 0xe4, 0x0d, 0x50, 0x66, 0xe4, 0x05, 0x40, 0xe9, 0xe6, 0x82, 0x31, 0x68, 0xe6, 0xf0, 0x20, 0xc4, 0xe1, 0xf1, 0x20, 0xc6, 0xe1, 0xf6, 0x01, 0xe7, 0xe1, 0xf7, 0x40, 0xc8, 0xe0, 0xf0, 0x40, 0xcd, 0xe0, 0xf0, 0x60, 0xce, 0xe0, 0xf0, 0xa0, 0x49, 0xe0, 0xf1, 0x80, 0x84, 0xe1, 0xf9, 0x60, 0xa3, 0xe1, 0xf8, 0x60, 0x85, 0xe0, 0xfa, 0x40, 0x0c, 0xe0, 0xb0, 0x30, 0xc4, 0xe1, 0xb4, 0x20, 0xc7, 0xe1, 0xb0, 0x14, 0xe8, 0xe1, 0xb4, 0xc0, 0xcd, 0xe0, 0xb4, 0x60, 0x85, 0xe1, 0xbb, 0x30, 0xa8, 0xe1, 0xb1, 0x10, 0x22, 0xe1, 0xb2, 0x90, 0x87, 0xe0, 0xb2, 0x40, 0x03, 0xe0, 0xbc, 0x24, 0xe5, 0xe0, 0xb9, 0x81, 0x61, 0xe0, 0xb4, 0x50, 0xa3, 0xe0, 0xb0, 0x60, 0x28, 0xe0, 0xd0, 0x00, 0xcd, 0xe1, 0xf0, 0x00, 0xcd, 0xe1 ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr r5, [r7]"
+        -
+          asm_text: "ldr r6, [r3, #0x3f]"
+        -
+          asm_text: "ldr r2, [r4, #0xfff]!"
+        -
+          asm_text: "ldr r1, [r2], #0x1e"
+        -
+          asm_text: "ldr r3, [r1], #-0x1e"
+        -
+          asm_text: "ldr r9, [r2], #-0"
+        -
+          asm_text: "ldr r3, [r8, r1]"
+        -
+          asm_text: "ldr r2, [r5, -r3]"
+        -
+          asm_text: "ldr r1, [r5, r9]!"
+        -
+          asm_text: "ldr r6, [r7, -r8]!"
+        -
+          asm_text: "ldr r1, [r0, r2, lsr #3]!"
+        -
+          asm_text: "ldr r5, [r9], r2"
+        -
+          asm_text: "ldr r4, [r3], -r6"
+        -
+          asm_text: "ldr r3, [r8, -r2, lsl #0xf]"
+        -
+          asm_text: "ldr r1, [r5], r3, asr #0xf"
+        -
+          asm_text: "ldrb r3, [r8]"
+        -
+          asm_text: "ldrb r1, [sp, #0x3f]"
+        -
+          asm_text: "ldrb r9, [r3, #0xfff]!"
+        -
+          asm_text: "ldrb r8, [r1], #0x16"
+        -
+          asm_text: "ldrb r2, [r7], #-0x13"
+        -
+          asm_text: "ldrb r9, [r8, r5]"
+        -
+          asm_text: "ldrb r1, [r5, -r1]"
+        -
+          asm_text: "ldrb r3, [r5, r2]!"
+        -
+          asm_text: "ldrb r6, [r9, -r3]!"
+        -
+          asm_text: "ldrb r2, [r1], r4"
+        -
+          asm_text: "ldrb r8, [r4], -r5"
+        -
+          asm_text: "ldrb r7, [r12, -r1, lsl #0xf]"
+        -
+          asm_text: "ldrb r5, [r2], r9, asr #0xf"
+        -
+          asm_text: "ldrbt r3, [r1], #4"
+        -
+          asm_text: "ldrbt r2, [r8], #-8"
+        -
+          asm_text: "ldrbt r8, [r7], r6"
+        -
+          asm_text: "ldrbt r1, [r2], -r6, lsl #0xc"
+        -
+          asm_text: "ldrd r2, r3, [r5]"
+        -
+          asm_text: "ldrd r6, r7, [r2, #0xf]"
+        -
+          asm_text: "ldrd r0, r1, [r9, #0x20]!"
+        -
+          asm_text: "ldrd r6, r7, [r1], #8"
+        -
+          asm_text: "ldrd r0, r1, [r8], #0"
+        -
+          asm_text: "ldrd r0, r1, [r8], #0"
+        -
+          asm_text: "ldrd r0, r1, [r8], #-0"
+        -
+          asm_text: "ldrd r4, r5, [r1, r3]"
+        -
+          asm_text: "ldrd r4, r5, [r7, r2]!"
+        -
+          asm_text: "ldrd r0, r1, [r8], r12"
+        -
+          asm_text: "ldrd r0, r1, [r8], -r12"
+        -
+          asm_text: "ldrh r3, [r4]"
+        -
+          asm_text: "ldrh r2, [r7, #4]"
+        -
+          asm_text: "ldrh r1, [r8, #0x40]!"
+        -
+          asm_text: "ldrh r12, [sp], #4"
+        -
+          asm_text: "ldrh r6, [r5, r4]"
+        -
+          asm_text: "ldrh r3, [r8, r11]!"
+        -
+          asm_text: "ldrh r1, [r2, -r1]!"
+        -
+          asm_text: "ldrh r9, [r7], r2"
+        -
+          asm_text: "ldrh r4, [r3], -r2"
+        -
+          asm_text: "ldrht r9, [r7], #0x80"
+        -
+          asm_text: "ldrht r4, [r3], #-0x4b"
+        -
+          asm_text: "ldrht r4, [r3], #0"
+        -
+          asm_text: "ldrht r9, [r7], r2"
+        -
+          asm_text: "ldrht r4, [r3], -r2"
+        -
+          asm_text: "ldrsb r3, [r4]"
+        -
+          asm_text: "ldrsb r2, [r7, #0x11]"
+        -
+          asm_text: "ldrsb r1, [r8, #0xff]!"
+        -
+          asm_text: "ldrsb r12, [sp], #0x9"
+        -
+          asm_text: "ldrsb r6, [r5, r4]"
+        -
+          asm_text: "ldrsb r3, [r8, r11]!"
+        -
+          asm_text: "ldrsb r1, [r2, -r1]!"
+        -
+          asm_text: "ldrsb r9, [r7], r2"
+        -
+          asm_text: "ldrsb r4, [r3], -r2"
+        -
+          asm_text: "ldrsbt r5, [r6], #1"
+        -
+          asm_text: "ldrsbt r3, [r8], #-0xc"
+        -
+          asm_text: "ldrsbt r5, [r6], #0"
+        -
+          asm_text: "ldrsbt r8, [r9], r5"
+        -
+          asm_text: "ldrsbt r2, [r1], -r4"
+        -
+          asm_text: "ldrsh r5, [r9]"
+        -
+          asm_text: "ldrsh r4, [r5, #7]"
+        -
+          asm_text: "ldrsh r3, [r6, #0x37]!"
+        -
+          asm_text: "ldrsh r2, [r7], #-0x9"
+        -
+          asm_text: "ldrsh r3, [r1, r5]"
+        -
+          asm_text: "ldrsh r4, [r6, r1]!"
+        -
+          asm_text: "ldrsh r5, [r3, -r6]!"
+        -
+          asm_text: "ldrsh r6, [r9], r8"
+        -
+          asm_text: "ldrsh r7, [r8], -r3"
+        -
+          asm_text: "ldrsht r5, [r6], #1"
+        -
+          asm_text: "ldrsht r3, [r8], #-0xc"
+        -
+          asm_text: "ldrsht r5, [r6], #0"
+        -
+          asm_text: "ldrsht r8, [r9], r5"
+        -
+          asm_text: "ldrsht r2, [r1], -r4"
+        -
+          asm_text: "str r8, [r12]"
+        -
+          asm_text: "str r7, [r1, #0xc]"
+        -
+          asm_text: "str r3, [r5, #0x28]!"
+        -
+          asm_text: "str r9, [sp], #0xfff"
+        -
+          asm_text: "str r1, [r7], #-0x80"
+        -
+          asm_text: "str r1, [r0], #-0"
+        -
+          asm_text: "str r9, [r6, r3]"
+        -
+          asm_text: "str r8, [r0, -r2]"
+        -
+          asm_text: "str r7, [r1, r6]!"
+        -
+          asm_text: "str r6, [sp, -r1]!"
+        -
+          asm_text: "str r5, [r3], r9"
+        -
+          asm_text: "str r4, [r2], -r5"
+        -
+          asm_text: "str r3, [r4, -r2, lsl #2]"
+        -
+          asm_text: "str r2, [r7], r3, asr #0x18"
+        -
+          asm_text: "strb r9, [r2]"
+        -
+          asm_text: "strb r7, [r1, #3]"
+        -
+          asm_text: "strb r6, [r4, #0x195]!"
+        -
+          asm_text: "strb r5, [r7], #0x48"
+        -
+          asm_text: "strb r1, [sp], #-1"
+        -
+          asm_text: "strb r1, [r2, r9]"
+        -
+          asm_text: "strb r2, [r3, -r8]"
+        -
+          asm_text: "strb r3, [r4, r7]!"
+        -
+          asm_text: "strb r4, [r5, -r6]!"
+        -
+          asm_text: "strb r5, [r6], r5"
+        -
+          asm_text: "strb r6, [r2], -r4"
+        -
+          asm_text: "strb r7, [r12, -r3, lsl #5]"
+        -
+          asm_text: "strb sp, [r7], r2, asr #0xc"
+        -
+          asm_text: "strbt r6, [r2], #0xc"
+        -
+          asm_text: "strbt r5, [r6], #-0xd"
+        -
+          asm_text: "strbt r4, [r9], r5"
+        -
+          asm_text: "strbt r3, [r8], -r2, lsl #3"
+        -
+          asm_text: "strd r2, r3, [r4]"
+        -
+          asm_text: "strd r2, r3, [r6, #1]"
+        -
+          asm_text: "strd r0, r1, [r7, #0x16]!"
+        -
+          asm_text: "strd r4, r5, [r8], #7"
+        -
+          asm_text: "strd r4, r5, [sp], #0"
+        -
+          asm_text: "strd r6, r7, [lr], #0"
+        -
+          asm_text: "strd r10, r11, [r9], #-0"
+        -
+          asm_text: "strd r8, r9, [r4, r1]"
+        -
+          asm_text: "strd r6, r7, [r3, r9]!"
+        -
+          asm_text: "strd r6, r7, [r5], r8"
+        -
+          asm_text: "strd r4, r5, [r12], -r10"
+        -
+          asm_text: "strh r3, [r4]"
+        -
+          asm_text: "strh r2, [r7, #4]"
+        -
+          asm_text: "strh r1, [r8, #0x40]!"
+        -
+          asm_text: "strh r12, [sp], #4"
+        -
+          asm_text: "strh r6, [r5, r4]"
+        -
+          asm_text: "strh r3, [r8, r11]!"
+        -
+          asm_text: "strh r1, [r2, -r1]!"
+        -
+          asm_text: "strh r9, [r7], r2"
+        -
+          asm_text: "strh r4, [r3], -r2"
+        -
+          asm_text: "strht r2, [r5], #0x4c"
+        -
+          asm_text: "strht r8, [r1], #-0x19"
+        -
+          asm_text: "strht r5, [r3], r4"
+        -
+          asm_text: "strht r6, [r8], -r0"
+        -
+          asm_text: "ldrd r0, r1, [sp]"
+        -
+          asm_text: "strd r0, r1, [sp]"
diff --git a/tests/MC/ARM/arm-shift-encoding.s.yaml b/tests/MC/ARM/arm-shift-encoding.s.yaml
new file mode 100644
index 000000000..4258d2f12
--- /dev/null
+++ b/tests/MC/ARM/arm-shift-encoding.s.yaml
@@ -0,0 +1,106 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x90, 0xe7, 0x20, 0x00, 0x90, 0xe7, 0x20, 0x08, 0x90, 0xe7, 0x00, 0x00, 0x90, 0xe7, 0x00, 0x08, 0x90, 0xe7, 0x40, 0x00, 0x90, 0xe7, 0x40, 0x08, 0x90, 0xe7, 0x60, 0x00, 0x90, 0xe7, 0x60, 0x08, 0x90, 0xe7, 0x00, 0xf0, 0xd0, 0xf7, 0x20, 0xf0, 0xd0, 0xf7, 0x20, 0xf8, 0xd0, 0xf7, 0x00, 0xf0, 0xd0, 0xf7, 0x00, 0xf8, 0xd0, 0xf7, 0x40, 0xf0, 0xd0, 0xf7, 0x40, 0xf8, 0xd0, 0xf7, 0x60, 0xf0, 0xd0, 0xf7, 0x60, 0xf8, 0xd0, 0xf7, 0x00, 0x00, 0x80, 0xe7, 0x20, 0x00, 0x80, 0xe7, 0x20, 0x08, 0x80, 0xe7, 0x00, 0x00, 0x80, 0xe7, 0x00, 0x08, 0x80, 0xe7, 0x40, 0x00, 0x80, 0xe7, 0x40, 0x08, 0x80, 0xe7, 0x60, 0x00, 0x80, 0xe7, 0x60, 0x08, 0x80, 0xe7, 0x62, 0x00, 0x91, 0xe6, 0x05, 0x30, 0x94, 0xe6, 0x08, 0x60, 0x87, 0xe6, 0x0b, 0x90, 0x8a, 0xe6, 0x0f, 0xd0, 0xae, 0xe0, 0x29, 0x10, 0xa8, 0xe0, 0x2f, 0x28, 0xa7, 0xe0, 0x0a, 0x30, 0xa6, 0xe0, 0x0e, 0x48, 0xa5, 0xe0, 0x4b, 0x50, 0xa4, 0xe0, 0x4d, 0x68, 0xa3, 0xe0, 0x6c, 0x70, 0xa2, 0xe0, 0x60, 0x88, 0xa1, 0xe0, 0x0e, 0x00, 0x5d, 0xe1, 0x28, 0x00, 0x51, 0xe1, 0x27, 0x08, 0x52, 0xe1, 0x06, 0x00, 0x53, 0xe1, 0x05, 0x08, 0x54, 0xe1, 0x44, 0x00, 0x55, 0xe1, 0x43, 0x08, 0x56, 0xe1, 0x62, 0x00, 0x57, 0xe1, 0x61, 0x08, 0x58, 0xe1 ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr r0, [r0, r0]"
+        -
+          asm_text: "ldr r0, [r0, r0, lsr #0x20]"
+        -
+          asm_text: "ldr r0, [r0, r0, lsr #0x10]"
+        -
+          asm_text: "ldr r0, [r0, r0]"
+        -
+          asm_text: "ldr r0, [r0, r0, lsl #0x10]"
+        -
+          asm_text: "ldr r0, [r0, r0, asr #0x20]"
+        -
+          asm_text: "ldr r0, [r0, r0, asr #0x10]"
+        -
+          asm_text: "ldr r0, [r0, r0, rrx]"
+        -
+          asm_text: "ldr r0, [r0, r0, ror #0x10]"
+        -
+          asm_text: "pld [r0, r0]"
+        -
+          asm_text: "pld [r0, r0, lsr #0x20]"
+        -
+          asm_text: "pld [r0, r0, lsr #0x10]"
+        -
+          asm_text: "pld [r0, r0]"
+        -
+          asm_text: "pld [r0, r0, lsl #0x10]"
+        -
+          asm_text: "pld [r0, r0, asr #0x20]"
+        -
+          asm_text: "pld [r0, r0, asr #0x10]"
+        -
+          asm_text: "pld [r0, r0, rrx]"
+        -
+          asm_text: "pld [r0, r0, ror #0x10]"
+        -
+          asm_text: "str r0, [r0, r0]"
+        -
+          asm_text: "str r0, [r0, r0, lsr #0x20]"
+        -
+          asm_text: "str r0, [r0, r0, lsr #0x10]"
+        -
+          asm_text: "str r0, [r0, r0]"
+        -
+          asm_text: "str r0, [r0, r0, lsl #0x10]"
+        -
+          asm_text: "str r0, [r0, r0, asr #0x20]"
+        -
+          asm_text: "str r0, [r0, r0, asr #0x10]"
+        -
+          asm_text: "str r0, [r0, r0, rrx]"
+        -
+          asm_text: "str r0, [r0, r0, ror #0x10]"
+        -
+          asm_text: "ldr r0, [r1], r2, rrx"
+        -
+          asm_text: "ldr r3, [r4], r5"
+        -
+          asm_text: "str r6, [r7], r8"
+        -
+          asm_text: "str r9, [r10], r11"
+        -
+          asm_text: "adc sp, lr, pc"
+        -
+          asm_text: "adc r1, r8, r9, lsr #0x20"
+        -
+          asm_text: "adc r2, r7, pc, lsr #0x10"
+        -
+          asm_text: "adc r3, r6, r10"
+        -
+          asm_text: "adc r4, r5, lr, lsl #0x10"
+        -
+          asm_text: "adc r5, r4, r11, asr #0x20"
+        -
+          asm_text: "adc r6, r3, sp, asr #0x10"
+        -
+          asm_text: "adc r7, r2, r12, rrx"
+        -
+          asm_text: "adc r8, r1, r0, ror #0x10"
+        -
+          asm_text: "cmp sp, lr"
+        -
+          asm_text: "cmp r1, r8, lsr #0x20"
+        -
+          asm_text: "cmp r2, r7, lsr #0x10"
+        -
+          asm_text: "cmp r3, r6"
+        -
+          asm_text: "cmp r4, r5, lsl #0x10"
+        -
+          asm_text: "cmp r5, r4, asr #0x20"
+        -
+          asm_text: "cmp r6, r3, asr #0x10"
+        -
+          asm_text: "cmp r7, r2, rrx"
+        -
+          asm_text: "cmp r8, r1, ror #0x10"
diff --git a/tests/MC/ARM/arm-thumb-trustzone.s.yaml b/tests/MC/ARM/arm-thumb-trustzone.s.yaml
new file mode 100644
index 000000000..5ce7956b2
--- /dev/null
+++ b/tests/MC/ARM/arm-thumb-trustzone.s.yaml
@@ -0,0 +1,12 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xff, 0xf7, 0x00, 0x80, 0x0c, 0xbf ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ]
+    expected:
+      insns:
+        -
+          asm_text: "smc #15"
+        -
+          asm_text: "ite eq"
diff --git a/tests/MC/ARM/arm-trustzone.s.yaml b/tests/MC/ARM/arm-trustzone.s.yaml
new file mode 100644
index 000000000..09f114132
--- /dev/null
+++ b/tests/MC/ARM/arm-trustzone.s.yaml
@@ -0,0 +1,12 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x7f, 0x00, 0x60, 0xe1, 0x70, 0x00, 0x60, 0x01 ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ]
+    expected:
+      insns:
+        -
+          asm_text: "smc #15"
+        -
+          asm_text: "smceq #0"
diff --git a/tests/MC/ARM/arm_addrmode2.s.yaml b/tests/MC/ARM/arm_addrmode2.s.yaml
new file mode 100644
index 000000000..0d55f5526
--- /dev/null
+++ b/tests/MC/ARM/arm_addrmode2.s.yaml
@@ -0,0 +1,44 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x02, 0x10, 0xb0, 0xe6, 0xa2, 0x11, 0xb0, 0xe6, 0x04, 0x10, 0xb0, 0xe4, 0x00, 0x10, 0xb0, 0xe4, 0x02, 0x10, 0xf0, 0xe6, 0xa2, 0x11, 0xf0, 0xe6, 0x04, 0x10, 0xf0, 0xe4, 0x00, 0x10, 0xf0, 0xe4, 0x02, 0x10, 0xa0, 0xe6, 0xa2, 0x11, 0xa0, 0xe6, 0x04, 0x10, 0xa0, 0xe4, 0x00, 0x10, 0xa0, 0xe4, 0x02, 0x10, 0xe0, 0xe6, 0xa2, 0x11, 0xe0, 0xe6, 0x04, 0x10, 0xe0, 0xe4, 0x00, 0x10, 0xe0, 0xe4, 0xa2, 0x11, 0xb0, 0xe7, 0xa2, 0x11, 0xf0, 0xe7 ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldrt r1, [r0], r2"
+        -
+          asm_text: "ldrt r1, [r0], r2, lsr #3"
+        -
+          asm_text: "ldrt r1, [r0], #4"
+        -
+          asm_text: "ldrt r1, [r0], #0"
+        -
+          asm_text: "ldrbt r1, [r0], r2"
+        -
+          asm_text: "ldrbt r1, [r0], r2, lsr #3"
+        -
+          asm_text: "ldrbt r1, [r0], #4"
+        -
+          asm_text: "ldrbt r1, [r0], #0"
+        -
+          asm_text: "strt r1, [r0], r2"
+        -
+          asm_text: "strt r1, [r0], r2, lsr #3"
+        -
+          asm_text: "strt r1, [r0], #4"
+        -
+          asm_text: "strt r1, [r0], #0"
+        -
+          asm_text: "strbt r1, [r0], r2"
+        -
+          asm_text: "strbt r1, [r0], r2, lsr #3"
+        -
+          asm_text: "strbt r1, [r0], #4"
+        -
+          asm_text: "strbt r1, [r0], #0"
+        -
+          asm_text: "ldr r1, [r0, r2, lsr #3]!"
+        -
+          asm_text: "ldrb r1, [r0, r2, lsr #3]!"
diff --git a/tests/MC/ARM/arm_addrmode3.s.yaml b/tests/MC/ARM/arm_addrmode3.s.yaml
new file mode 100644
index 000000000..2a6a95de0
--- /dev/null
+++ b/tests/MC/ARM/arm_addrmode3.s.yaml
@@ -0,0 +1,24 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xd2, 0x10, 0xb0, 0xe0, 0xd4, 0x10, 0xf0, 0xe0, 0xf2, 0x10, 0xb0, 0xe0, 0xf4, 0x10, 0xf0, 0xe0, 0xb2, 0x10, 0xb0, 0xe0, 0xb4, 0x10, 0xf0, 0xe0, 0xb2, 0x10, 0xa0, 0xe0, 0xb4, 0x10, 0xe0, 0xe0 ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldrsbt r1, [r0], r2"
+        -
+          asm_text: "ldrsbt r1, [r0], #4"
+        -
+          asm_text: "ldrsht r1, [r0], r2"
+        -
+          asm_text: "ldrsht r1, [r0], #4"
+        -
+          asm_text: "ldrht r1, [r0], r2"
+        -
+          asm_text: "ldrht r1, [r0], #4"
+        -
+          asm_text: "strht r1, [r0], r2"
+        -
+          asm_text: "strht r1, [r0], #4"
diff --git a/tests/MC/ARM/arm_instructions.s.yaml b/tests/MC/ARM/arm_instructions.s.yaml
new file mode 100644
index 000000000..72559b88e
--- /dev/null
+++ b/tests/MC/ARM/arm_instructions.s.yaml
@@ -0,0 +1,52 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x03, 0x10, 0x02, 0xe0, 0x03, 0x10, 0x12, 0xe0, 0x03, 0x10, 0x22, 0xe0, 0x03, 0x10, 0x32, 0xe0, 0x03, 0x10, 0x42, 0xe0, 0x03, 0x10, 0x52, 0xe0, 0x03, 0x10, 0x82, 0xe0, 0x03, 0x10, 0x92, 0xe0, 0x03, 0x10, 0xa2, 0xe0, 0x03, 0x10, 0xc2, 0xe1, 0x03, 0x10, 0xd2, 0xe1, 0x02, 0x10, 0xa0, 0xe1, 0x02, 0x10, 0xe0, 0xe1, 0x02, 0x10, 0xf0, 0xe1, 0x90, 0x02, 0xcb, 0xe7, 0x7a, 0x00, 0x20, 0xe1, 0x81, 0x17, 0x11, 0xee, 0x81, 0x17, 0x11, 0xfe, 0x13, 0x14, 0x82, 0xe0, 0x30, 0x0f, 0xa6, 0xe6, 0x00, 0x00, 0x0a, 0xf1, 0xb0, 0x30, 0x42, 0xe1 ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ]
+    expected:
+      insns:
+        -
+          asm_text: "and r1, r2, r3"
+        -
+          asm_text: "ands r1, r2, r3"
+        -
+          asm_text: "eor r1, r2, r3"
+        -
+          asm_text: "eors r1, r2, r3"
+        -
+          asm_text: "sub r1, r2, r3"
+        -
+          asm_text: "subs r1, r2, r3"
+        -
+          asm_text: "add r1, r2, r3"
+        -
+          asm_text: "adds r1, r2, r3"
+        -
+          asm_text: "adc r1, r2, r3"
+        -
+          asm_text: "bic r1, r2, r3"
+        -
+          asm_text: "bics r1, r2, r3"
+        -
+          asm_text: "mov r1, r2"
+        -
+          asm_text: "mvn r1, r2"
+        -
+          asm_text: "mvns r1, r2"
+        -
+          asm_text: "bfi r0, r0, #5, #7"
+        -
+          asm_text: "bkpt #0xa"
+        -
+          asm_text: "cdp p7, #1, c1, c1, c1, #4"
+        -
+          asm_text: "cdp2 p7, #1, c1, c1, c1, #4"
+        -
+          asm_text: "add r1, r2, r3, lsl r4"
+        -
+          asm_text: "ssat16 r0, #7, r0"
+        -
+          asm_text: "cpsie none, #0"
+        -
+          asm_text: "strh r3, [r2, #-0]"
diff --git a/tests/MC/ARM/armv8.1m-pacbti.s.yaml b/tests/MC/ARM/armv8.1m-pacbti.s.yaml
new file mode 100644
index 000000000..c0b528208
--- /dev/null
+++ b/tests/MC/ARM/armv8.1m-pacbti.s.yaml
@@ -0,0 +1,18 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xaf, 0xf3, 0x2d, 0x80, 0xaf, 0xf3, 0x0f, 0x80, 0xaf, 0xf3, 0x0f, 0x80, 0xaf, 0xf3, 0x1d, 0x80, 0xaf, 0xf3, 0x0d, 0x80 ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ]
+    expected:
+      insns:
+        -
+          asm_text: "aut r12, lr, sp"
+        -
+          asm_text: "bti"
+        -
+          asm_text: "bti"
+        -
+          asm_text: "pac r12, lr, sp"
+        -
+          asm_text: "pacbti r12, lr, sp"
diff --git a/tests/MC/ARM/armv8.2a-dotprod-a32.s.yaml b/tests/MC/ARM/armv8.2a-dotprod-a32.s.yaml
new file mode 100644
index 000000000..5ae5ce21d
--- /dev/null
+++ b/tests/MC/ARM/armv8.2a-dotprod-a32.s.yaml
@@ -0,0 +1,24 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x12, 0x0d, 0x21, 0xfc, 0x02, 0x0d, 0x21, 0xfc, 0x58, 0x0d, 0x22, 0xfc, 0x48, 0x0d, 0x22, 0xfc, 0x12, 0x0d, 0x21, 0xfe, 0x22, 0x0d, 0x21, 0xfe, 0x54, 0x0d, 0x22, 0xfe, 0x64, 0x0d, 0x22, 0xfe ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ]
+    expected:
+      insns:
+        -
+          asm_text: "vudot.u8 d0, d1, d2"
+        -
+          asm_text: "vsdot.s8 d0, d1, d2"
+        -
+          asm_text: "vudot.u8 q0, q1, q4"
+        -
+          asm_text: "vsdot.s8 q0, q1, q4"
+        -
+          asm_text: "vudot.u8 d0, d1, d2[0]"
+        -
+          asm_text: "vsdot.s8 d0, d1, d2[1]"
+        -
+          asm_text: "vudot.u8 q0, q1, d4[0]"
+        -
+          asm_text: "vsdot.s8 q0, q1, d4[1]"
diff --git a/tests/MC/ARM/armv8.2a-dotprod-t32.s.yaml b/tests/MC/ARM/armv8.2a-dotprod-t32.s.yaml
new file mode 100644
index 000000000..218c43f67
--- /dev/null
+++ b/tests/MC/ARM/armv8.2a-dotprod-t32.s.yaml
@@ -0,0 +1,24 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x21, 0xfc, 0x12, 0x0d, 0x21, 0xfc, 0x02, 0x0d, 0x22, 0xfc, 0x58, 0x0d, 0x22, 0xfc, 0x48, 0x0d, 0x21, 0xfe, 0x12, 0x0d, 0x21, 0xfe, 0x22, 0x0d, 0x22, 0xfe, 0x54, 0x0d, 0x22, 0xfe, 0x64, 0x0d ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ]
+    expected:
+      insns:
+        -
+          asm_text: "vudot.u8 d0, d1, d2"
+        -
+          asm_text: "vsdot.s8 d0, d1, d2"
+        -
+          asm_text: "vudot.u8 q0, q1, q4"
+        -
+          asm_text: "vsdot.s8 q0, q1, q4"
+        -
+          asm_text: "vudot.u8 d0, d1, d2[0]"
+        -
+          asm_text: "vsdot.s8 d0, d1, d2[1]"
+        -
+          asm_text: "vudot.u8 q0, q1, d4[0]"
+        -
+          asm_text: "vsdot.s8 q0, q1, d4[1]"
diff --git a/tests/MC/ARM/armv8.5a-sb.s.yaml b/tests/MC/ARM/armv8.5a-sb.s.yaml
new file mode 100644
index 000000000..63e3e7151
--- /dev/null
+++ b/tests/MC/ARM/armv8.5a-sb.s.yaml
@@ -0,0 +1,10 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x70, 0xf0, 0x7f, 0xf5 ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ]
+    expected:
+      insns:
+        -
+          asm_text: "sb"
diff --git a/tests/MC/ARM/armv8a-fpmul.s.yaml b/tests/MC/ARM/armv8a-fpmul.s.yaml
new file mode 100644
index 000000000..901d69fa1
--- /dev/null
+++ b/tests/MC/ARM/armv8a-fpmul.s.yaml
@@ -0,0 +1,24 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x91, 0x08, 0x20, 0xfc, 0x91, 0x08, 0xa0, 0xfc, 0x52, 0x08, 0x21, 0xfc, 0x52, 0x08, 0xa1, 0xfc, 0x99, 0x08, 0x00, 0xfe, 0x99, 0x08, 0x10, 0xfe, 0x7a, 0x08, 0x01, 0xfe, 0x7a, 0x08, 0x11, 0xfe ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmal.f16 d0, s1, s2"
+        -
+          asm_text: "vfmsl.f16 d0, s1, s2"
+        -
+          asm_text: "vfmal.f16 q0, d1, d2"
+        -
+          asm_text: "vfmsl.f16 q0, d1, d2"
+        -
+          asm_text: "vfmal.f16 d0, s1, s2[1]"
+        -
+          asm_text: "vfmsl.f16 d0, s1, s2[1]"
+        -
+          asm_text: "vfmal.f16 q0, d1, d2[3]"
+        -
+          asm_text: "vfmsl.f16 q0, d1, d2[3]"
diff --git a/tests/MC/ARM/basic-arm-instructions-v8.s.yaml b/tests/MC/ARM/basic-arm-instructions-v8.s.yaml
new file mode 100644
index 000000000..8a92264d6
--- /dev/null
+++ b/tests/MC/ARM/basic-arm-instructions-v8.s.yaml
@@ -0,0 +1,26 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x59, 0xf0, 0x7f, 0xf5, 0x51, 0xf0, 0x7f, 0xf5, 0x55, 0xf0, 0x7f, 0xf5, 0x5d, 0xf0, 0x7f, 0xf5, 0x49, 0xf0, 0x7f, 0xf5, 0x41, 0xf0, 0x7f, 0xf5, 0x45, 0xf0, 0x7f, 0xf5, 0x4d, 0xf0, 0x7f, 0xf5, 0x05, 0xf0, 0x20, 0xe3 ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_V8", "CS_MODE_ARM" ]
+    expected:
+      insns:
+        -
+          asm_text: "dmb ishld"
+        -
+          asm_text: "dmb oshld"
+        -
+          asm_text: "dmb nshld"
+        -
+          asm_text: "dmb ld"
+        -
+          asm_text: "dsb ishld"
+        -
+          asm_text: "dsb oshld"
+        -
+          asm_text: "dsb nshld"
+        -
+          asm_text: "dsb ld"
+        -
+          asm_text: "sevl"
diff --git a/tests/MC/ARM/basic-arm-instructions.s.yaml b/tests/MC/ARM/basic-arm-instructions.s.yaml
new file mode 100644
index 000000000..ed1fbc05e
--- /dev/null
+++ b/tests/MC/ARM/basic-arm-instructions.s.yaml
@@ -0,0 +1,2616 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x0f, 0x10, 0xa2, 0xe2, 0x0f, 0x10, 0xa2, 0xe2, 0x0f, 0x10, 0xa2, 0xe2, 0xff, 0x78, 0xa8, 0xe2, 0x2a, 0x71, 0xa8, 0xe2, 0x2a, 0x71, 0xa8, 0xe2, 0x28, 0x71, 0xa8, 0xe2, 0x28, 0x71, 0xa8, 0xe2, 0x28, 0x71, 0xa8, 0xe2, 0x28, 0x71, 0xa8, 0xe2, 0xf0, 0x10, 0xa2, 0xe2, 0x0f, 0x1c, 0xa2, 0xe2, 0x0f, 0x1a, 0xa2, 0xe2, 0x0f, 0x18, 0xa2, 0xe2, 0x0f, 0x16, 0xa2, 0xe2, 0x0f, 0x14, 0xa2, 0xe2, 0x0f, 0x12, 0xa2, 0xe2, 0xff, 0x12, 0xa2, 0xe2, 0x0f, 0x1c, 0xb2, 0xe2, 0x28, 0x71, 0xb8, 0xe2, 0x0f, 0x1c, 0xb2, 0x02, 0x0f, 0x1c, 0xa2, 0x02, 0x06, 0x40, 0xa5, 0xe0, 0x86, 0x40, 0xa5, 0xe0, 0x86, 0x4f, 0xa5, 0xe0, 0xa6, 0x40, 0xa5, 0xe0, 0xa6, 0x4f, 0xa5, 0xe0, 0x26, 0x40, 0xa5, 0xe0, 0xc6, 0x40, 0xa5, 0xe0, 0xc6, 0x4f, 0xa5, 0xe0, 0x46, 0x40, 0xa5, 0xe0, 0xe6, 0x40, 0xa5, 0xe0, 0xe6, 0x4f, 0xa5, 0xe0, 0x18, 0x69, 0xa7, 0xe0, 0x38, 0x69, 0xa7, 0xe0, 0x58, 0x69, 0xa7, 0xe0, 0x78, 0x69, 0xa7, 0xe0, 0x66, 0x40, 0xa5, 0xe0, 0x06, 0x50, 0xa5, 0xe0, 0x85, 0x40, 0xa4, 0xe0, 0x85, 0x4f, 0xa4, 0xe0, 0xa5, 0x40, 0xa4, 0xe0, 0xa5, 0x4f, 0xa4, 0xe0, 0x25, 0x40, 0xa4, 0xe0, 0xc5, 0x40, 0xa4, 0xe0, 0xc5, 0x4f, 0xa4, 0xe0, 0x45, 0x40, 0xa4, 0xe0, 0xe5, 0x40, 0xa4, 0xe0, 0xe5, 0x4f, 0xa4, 0xe0, 0x65, 0x40, 0xa4, 0xe0, 0x17, 0x69, 0xa6, 0xe0, 0x37, 0x69, 0xa6, 0xe0, 0x57, 0x69, 0xa6, 0xe0, 0x77, 0x69, 0xa6, 0xe0, 0x65, 0x40, 0xa4, 0xe0, 0x03, 0x20, 0x8f, 0xe2, 0x03, 0x20, 0x4f, 0xe2, 0x00, 0x10, 0x4f, 0xe2, 0x12, 0x14, 0x4f, 0xe2, 0x06, 0x11, 0x4f, 0xe2, 0x12, 0x14, 0x8f, 0xe2, 0x06, 0x11, 0x8f, 0xe2, 0x0f, 0x4a, 0x85, 0xe2, 0x0f, 0x4a, 0x85, 0xe2, 0x0f, 0x4a, 0x85, 0xe2, 0x0f, 0x4a, 0x45, 0xe2, 0xff, 0x78, 0x88, 0xe2, 0x2a, 0x71, 0x88, 0xe2, 0x2a, 0x71, 0x88, 0xe2, 0x28, 0x71, 0x88, 0xe2, 0x28, 0x71, 0x88, 0xe2, 0x28, 0x71, 0x88, 0xe2, 0x28, 0x71, 0x88, 0xe2, 0x06, 0x40, 0x85, 0xe0, 0x86, 0x42, 0x85, 0xe0, 0xa6, 0x42, 0x85, 0xe0, 0xa6, 0x42, 0x85, 0xe0, 0xc6, 0x42, 0x85, 0xe0, 0xe6, 0x42, 0x85, 0xe0, 0x18, 0x69, 0x87, 0xe0, 0x13, 0x49, 0x84, 0xe0, 0x38, 0x69, 0x87, 0xe0, 0x58, 0x69, 0x87, 0xe0, 0x78, 0x69, 0x87, 0xe0, 0x66, 0x40, 0x85, 0xe0, 0x0f, 0x5a, 0x85, 0xe2, 0x0f, 0x5a, 0x85, 0xe2, 0x0f, 0x5a, 0x85, 0xe2, 0x0f, 0x5a, 0x45, 0xe2, 0xff, 0x78, 0x87, 0xe2, 0x2a, 0x71, 0x87, 0xe2, 0x2a, 0x71, 0x87, 0xe2, 0x28, 0x71, 0x87, 0xe2, 0x28, 0x71, 0x87, 0xe2, 0x28, 0x71, 0x87, 0xe2, 0x28, 0x71, 0x87, 0xe2, 0x05, 0x40, 0x84, 0xe0, 0x85, 0x42, 0x84, 0xe0, 0xa5, 0x42, 0x84, 0xe0, 0xa5, 0x42, 0x84, 0xe0, 0xc5, 0x42, 0x84, 0xe0, 0xe5, 0x42, 0x84, 0xe0, 0x17, 0x69, 0x86, 0xe0, 0x37, 0x69, 0x86, 0xe0, 0x57, 0x69, 0x86, 0xe0, 0x77, 0x69, 0x86, 0xe0, 0x65, 0x40, 0x84, 0xe0, 0x04, 0x00, 0x40, 0xe2, 0x15, 0x40, 0x45, 0xe2, 0x03, 0x01, 0x8f, 0xe2, 0x03, 0x01, 0x9f, 0x02, 0x22, 0x30, 0x81, 0xe0, 0x42, 0x30, 0x81, 0xe0, 0xff, 0x78, 0x98, 0xe2, 0xff, 0x78, 0x98, 0xe2, 0xff, 0x78, 0x98, 0xe2, 0xff, 0x78, 0x98, 0xe2, 0x2a, 0x71, 0x98, 0xe2, 0x2a, 0x71, 0x98, 0xe2, 0x28, 0x71, 0x98, 0xe2, 0x28, 0x71, 0x98, 0xe2, 0x28, 0x71, 0x98, 0xe2, 0x28, 0x71, 0x98, 0xe2, 0x0f, 0xa0, 0x01, 0xe2, 0x0f, 0xa0, 0x01, 0xe2, 0x0f, 0xa0, 0x01, 0xe2, 0x0e, 0xa0, 0xc1, 0xe3, 0xff, 0x78, 0x08, 0xe2, 0x2a, 0x71, 0x08, 0xe2, 0x2a, 0x71, 0x08, 0xe2, 0x28, 0x71, 0x08, 0xe2, 0x28, 0x71, 0x08, 0xe2, 0x28, 0x71, 0x08, 0xe2, 0x28, 0x71, 0x08, 0xe2, 0x06, 0xa0, 0x01, 0xe0, 0x06, 0xa5, 0x01, 0xe0, 0x26, 0xa5, 0x01, 0xe0, 0x26, 0xa5, 0x01, 0xe0, 0x46, 0xa5, 0x01, 0xe0, 0x66, 0xa5, 0x01, 0xe0, 0x18, 0x62, 0x07, 0xe0, 0x38, 0x62, 0x07, 0xe0, 0x58, 0x62, 0x07, 0xe0, 0x78, 0x62, 0x07, 0xe0, 0x66, 0xa0, 0x01, 0xe0, 0x02, 0x21, 0xc3, 0xe3, 0x02, 0xd1, 0xcd, 0xe3, 0x02, 0xf1, 0xcf, 0xe3, 0x0f, 0x10, 0x01, 0xe2, 0x0f, 0x10, 0x01, 0xe2, 0x0f, 0x10, 0x01, 0xe2, 0x0e, 0x10, 0xc1, 0xe3, 0xff, 0x78, 0x07, 0xe2, 0x2a, 0x71, 0x07, 0xe2, 0x2a, 0x71, 0x07, 0xe2, 0x28, 0x71, 0x07, 0xe2, 0x28, 0x71, 0x07, 0xe2, 0x28, 0x71, 0x07, 0xe2, 0x28, 0x71, 0x07, 0xe2, 0x01, 0xa0, 0x0a, 0xe0, 0x01, 0xa5, 0x0a, 0xe0, 0x21, 0xa5, 0x0a, 0xe0, 0x21, 0xa5, 0x0a, 0xe0, 0x41, 0xa5, 0x0a, 0xe0, 0x61, 0xa5, 0x0a, 0xe0, 0x17, 0x62, 0x06, 0xe0, 0x37, 0x62, 0x06, 0xe0, 0x57, 0x62, 0x06, 0xe0, 0x77, 0x62, 0x06, 0xe0, 0x61, 0xa0, 0x0a, 0xe0, 0x22, 0x30, 0x01, 0xe0, 0x42, 0x30, 0x01, 0xe0, 0x44, 0x20, 0xa0, 0xe1, 0x44, 0x21, 0xa0, 0xe1, 0x04, 0x20, 0xa0, 0xe1, 0x44, 0x41, 0xa0, 0xe1, 0x9f, 0x51, 0xd3, 0xe7, 0x9f, 0x51, 0xd3, 0x37, 0x92, 0x51, 0xd3, 0xe7, 0x92, 0x51, 0xd3, 0x17, 0x0f, 0xa0, 0xc1, 0xe3, 0x0f, 0xa0, 0xc1, 0xe3, 0x0f, 0xa0, 0xc1, 0xe3, 0x0e, 0xa0, 0x01, 0xe2, 0xff, 0x78, 0xc8, 0xe3, 0x2a, 0x71, 0xc8, 0xe3, 0x2a, 0x71, 0xc8, 0xe3, 0x28, 0x71, 0xc8, 0xe3, 0x28, 0x71, 0xc8, 0xe3, 0x28, 0x71, 0xc8, 0xe3, 0x06, 0xa0, 0xc1, 0xe1, 0x06, 0xa5, 0xc1, 0xe1, 0x26, 0xa5, 0xc1, 0xe1, 0x26, 0xa5, 0xc1, 0xe1, 0x46, 0xa5, 0xc1, 0xe1, 0x66, 0xa5, 0xc1, 0xe1, 0x18, 0x62, 0xc7, 0xe1, 0x38, 0x62, 0xc7, 0xe1, 0x58, 0x62, 0xc7, 0xe1, 0x78, 0x62, 0xc7, 0xe1, 0x66, 0xa0, 0xc1, 0xe1, 0x02, 0x21, 0x03, 0xe2, 0x02, 0xd1, 0x0d, 0xe2, 0x02, 0xf1, 0x0f, 0xe2, 0x0f, 0x10, 0xc1, 0xe3, 0x0f, 0x10, 0xc1, 0xe3, 0x0f, 0x10, 0xc1, 0xe3, 0x0e, 0x10, 0x01, 0xe2, 0xff, 0x78, 0xc7, 0xe3, 0x2a, 0x71, 0xc7, 0xe3, 0x2a, 0x71, 0xc7, 0xe3, 0x28, 0x71, 0xc7, 0xe3, 0x28, 0x71, 0xc7, 0xe3, 0x28, 0x71, 0xc7, 0xe3, 0x28, 0x71, 0xc7, 0xe3, 0x01, 0xa0, 0xca, 0xe1, 0x01, 0xa5, 0xca, 0xe1, 0x21, 0xa5, 0xca, 0xe1, 0x21, 0xa5, 0xca, 0xe1, 0x41, 0xa5, 0xca, 0xe1, 0x61, 0xa5, 0xca, 0xe1, 0x17, 0x62, 0xc6, 0xe1, 0x37, 0x62, 0xc6, 0xe1, 0x57, 0x62, 0xc6, 0xe1, 0x77, 0x62, 0xc6, 0xe1, 0x61, 0xa0, 0xca, 0xe1, 0x22, 0x30, 0xc1, 0xe1, 0x42, 0x30, 0xc1, 0xe1, 0x7a, 0x00, 0x20, 0xe1, 0x7f, 0xff, 0x2f, 0xe1, 0x27, 0x3b, 0x6d, 0x9b, 0xa0, 0xb0, 0x7b, 0xfa, 0x50, 0xd8, 0x3d, 0xfa, 0x32, 0xff, 0x2f, 0xe1, 0x32, 0xff, 0x2f, 0x11, 0x12, 0xff, 0x2f, 0xe1, 0x12, 0xff, 0x2f, 0x11, 0x22, 0xff, 0x2f, 0xe1, 0x22, 0xff, 0x2f, 0x11, 0x81, 0x17, 0x11, 0xee, 0x81, 0x17, 0x11, 0xfe, 0xe0, 0x6c, 0x0c, 0xfe, 0x81, 0x17, 0x11, 0x1e, 0x1f, 0xf0, 0x7f, 0xf5, 0x12, 0x1f, 0x6f, 0xe1, 0x12, 0x1f, 0x6f, 0x01, 0x0f, 0x00, 0x71, 0xe3, 0x0f, 0x00, 0x71, 0xe3, 0x0f, 0x00, 0x71, 0xe3, 0x0f, 0x00, 0x51, 0xe3, 0xff, 0x08, 0x77, 0xe3, 0x2a, 0x01, 0x77, 0xe3, 0x2a, 0x01, 0x77, 0xe3, 0x28, 0x01, 0x77, 0xe3, 0x28, 0x01, 0x77, 0xe3, 0x28, 0x01, 0x77, 0xe3, 0x28, 0x01, 0x77, 0xe3, 0x06, 0x00, 0x71, 0xe1, 0x06, 0x05, 0x71, 0xe1, 0x26, 0x05, 0x71, 0xe1, 0x26, 0x05, 0x7d, 0xe1, 0x46, 0x05, 0x71, 0xe1, 0x66, 0x05, 0x71, 0xe1, 0x18, 0x02, 0x77, 0xe1, 0x38, 0x02, 0x7d, 0xe1, 0x58, 0x02, 0x77, 0xe1, 0x78, 0x02, 0x77, 0xe1, 0x66, 0x00, 0x71, 0xe1, 0x0f, 0x00, 0x51, 0xe3, 0x0f, 0x00, 0x51, 0xe3, 0x0f, 0x00, 0x51, 0xe3, 0x0f, 0x00, 0x71, 0xe3, 0xff, 0x08, 0x57, 0xe3, 0x2a, 0x01, 0x57, 0xe3, 0x2a, 0x01, 0x57, 0xe3, 0x28, 0x01, 0x57, 0xe3, 0x28, 0x01, 0x57, 0xe3, 0x28, 0x01, 0x57, 0xe3, 0x28, 0x01, 0x57, 0xe3, 0x06, 0x00, 0x51, 0xe1, 0x06, 0x05, 0x51, 0xe1, 0x26, 0x05, 0x51, 0xe1, 0x26, 0x05, 0x5d, 0xe1, 0x46, 0x05, 0x51, 0xe1, 0x66, 0x05, 0x51, 0xe1, 0x18, 0x02, 0x57, 0xe1, 0x38, 0x02, 0x5d, 0xe1, 0x58, 0x02, 0x57, 0xe1, 0x78, 0x02, 0x57, 0xe1, 0x66, 0x00, 0x51, 0xe1, 0x02, 0x00, 0x70, 0xe3, 0x00, 0x00, 0x5e, 0xe3, 0xc0, 0x01, 0x08, 0xf1, 0xc0, 0x01, 0x08, 0xf1, 0x0f, 0x00, 0x02, 0xf1, 0xca, 0x00, 0x0e, 0xf1, 0xf0, 0xf0, 0x20, 0xe3, 0xf5, 0xf0, 0x20, 0xe3, 0xff, 0xf0, 0x20, 0xe3, 0x5f, 0xf0, 0x7f, 0xf5, 0x5e, 0xf0, 0x7f, 0xf5, 0x5d, 0xf0, 0x7f, 0xf5, 0x5c, 0xf0, 0x7f, 0xf5, 0x5b, 0xf0, 0x7f, 0xf5, 0x5a, 0xf0, 0x7f, 0xf5, 0x59, 0xf0, 0x7f, 0xf5, 0x58, 0xf0, 0x7f, 0xf5, 0x57, 0xf0, 0x7f, 0xf5, 0x56, 0xf0, 0x7f, 0xf5, 0x55, 0xf0, 0x7f, 0xf5, 0x54, 0xf0, 0x7f, 0xf5, 0x53, 0xf0, 0x7f, 0xf5, 0x52, 0xf0, 0x7f, 0xf5, 0x51, 0xf0, 0x7f, 0xf5, 0x50, 0xf0, 0x7f, 0xf5, 0x5f, 0xf0, 0x7f, 0xf5, 0x5e, 0xf0, 0x7f, 0xf5, 0x5b, 0xf0, 0x7f, 0xf5, 0x5b, 0xf0, 0x7f, 0xf5, 0x5a, 0xf0, 0x7f, 0xf5, 0x5a, 0xf0, 0x7f, 0xf5, 0x57, 0xf0, 0x7f, 0xf5, 0x57, 0xf0, 0x7f, 0xf5, 0x56, 0xf0, 0x7f, 0xf5, 0x56, 0xf0, 0x7f, 0xf5, 0x53, 0xf0, 0x7f, 0xf5, 0x52, 0xf0, 0x7f, 0xf5, 0x5f, 0xf0, 0x7f, 0xf5, 0x4f, 0xf0, 0x7f, 0xf5, 0x4e, 0xf0, 0x7f, 0xf5, 0x4d, 0xf0, 0x7f, 0xf5, 0x4c, 0xf0, 0x7f, 0xf5, 0x4b, 0xf0, 0x7f, 0xf5, 0x4a, 0xf0, 0x7f, 0xf5, 0x49, 0xf0, 0x7f, 0xf5, 0x48, 0xf0, 0x7f, 0xf5, 0x47, 0xf0, 0x7f, 0xf5, 0x46, 0xf0, 0x7f, 0xf5, 0x45, 0xf0, 0x7f, 0xf5, 0x44, 0xf0, 0x7f, 0xf5, 0x43, 0xf0, 0x7f, 0xf5, 0x42, 0xf0, 0x7f, 0xf5, 0x41, 0xf0, 0x7f, 0xf5, 0x40, 0xf0, 0x7f, 0xf5, 0x48, 0xf0, 0x7f, 0xf5, 0x47, 0xf0, 0x7f, 0xf5, 0x4f, 0xf0, 0x7f, 0xf5, 0x4e, 0xf0, 0x7f, 0xf5, 0x4b, 0xf0, 0x7f, 0xf5, 0x4b, 0xf0, 0x7f, 0xf5, 0x4a, 0xf0, 0x7f, 0xf5, 0x4a, 0xf0, 0x7f, 0xf5, 0x47, 0xf0, 0x7f, 0xf5, 0x47, 0xf0, 0x7f, 0xf5, 0x46, 0xf0, 0x7f, 0xf5, 0x46, 0xf0, 0x7f, 0xf5, 0x43, 0xf0, 0x7f, 0xf5, 0x42, 0xf0, 0x7f, 0xf5, 0x4f, 0xf0, 0x7f, 0xf5, 0x4f, 0xf0, 0x7f, 0xf5, 0x42, 0xf0, 0x7f, 0xf5, 0x0f, 0x4a, 0x25, 0xe2, 0x0f, 0x4a, 0x25, 0xe2, 0x0f, 0x4a, 0x25, 0xe2, 0xff, 0x78, 0x28, 0xe2, 0x2a, 0x71, 0x28, 0xe2, 0x2a, 0x71, 0x28, 0xe2, 0x28, 0x71, 0x28, 0xe2, 0x28, 0x71, 0x28, 0xe2, 0x28, 0x71, 0x28, 0xe2, 0x28, 0x71, 0x28, 0xe2, 0x06, 0x40, 0x25, 0xe0, 0x86, 0x42, 0x25, 0xe0, 0xa6, 0x42, 0x25, 0xe0, 0xa6, 0x42, 0x25, 0xe0, 0xc6, 0x42, 0x25, 0xe0, 0xe6, 0x42, 0x25, 0xe0, 0x18, 0x69, 0x27, 0xe0, 0x38, 0x69, 0x27, 0xe0, 0x58, 0x69, 0x27, 0xe0, 0x78, 0x69, 0x27, 0xe0, 0x66, 0x40, 0x25, 0xe0, 0x0f, 0x5a, 0x25, 0xe2, 0x0f, 0x5a, 0x25, 0xe2, 0x0f, 0x5a, 0x25, 0xe2, 0xff, 0x78, 0x27, 0xe2, 0x2a, 0x71, 0x27, 0xe2, 0x2a, 0x71, 0x27, 0xe2, 0x28, 0x71, 0x27, 0xe2, 0x28, 0x71, 0x27, 0xe2, 0x28, 0x71, 0x27, 0xe2, 0x28, 0x71, 0x27, 0xe2, 0x05, 0x40, 0x24, 0xe0, 0x85, 0x42, 0x24, 0xe0, 0xa5, 0x42, 0x24, 0xe0, 0xa5, 0x42, 0x24, 0xe0, 0xc5, 0x42, 0x24, 0xe0, 0xe5, 0x42, 0x24, 0xe0, 0x17, 0x69, 0x26, 0xe0, 0x37, 0x69, 0x26, 0xe0, 0x57, 0x69, 0x26, 0xe0, 0x77, 0x69, 0x26, 0xe0, 0x65, 0x40, 0x24, 0xe0, 0x22, 0x30, 0x21, 0xe0, 0x42, 0x30, 0x21, 0xe0, 0x6f, 0xf0, 0x7f, 0xf5, 0x6f, 0xf0, 0x7f, 0xf5, 0x6f, 0xf0, 0x7f, 0xf5, 0x61, 0xf0, 0x7f, 0xf5, 0x01, 0x80, 0x91, 0xfd, 0x00, 0x71, 0x92, 0xfd, 0x38, 0x62, 0x13, 0xfd, 0x1e, 0x53, 0x34, 0xfd, 0x04, 0x44, 0xb5, 0xfc, 0x12, 0x35, 0x36, 0xfc, 0x01, 0x26, 0xd7, 0xfd, 0x00, 0x17, 0xd8, 0xfd, 0x38, 0x08, 0x59, 0xfd, 0x1e, 0x19, 0x7a, 0xfd, 0x04, 0x20, 0xfb, 0xfc, 0x12, 0x31, 0x7c, 0xfc, 0x01, 0x4c, 0x90, 0xed, 0x00, 0x5d, 0x91, 0xed, 0x38, 0x6e, 0x12, 0xed, 0x1e, 0x7f, 0x33, 0xed, 0x04, 0x85, 0xb4, 0xec, 0x12, 0x94, 0x35, 0xec, 0x01, 0xa3, 0xd6, 0xed, 0x00, 0xb2, 0xd7, 0xed, 0x38, 0xc1, 0x58, 0xed, 0x1e, 0xd0, 0x79, 0xed, 0x04, 0xe6, 0xfa, 0xec, 0x12, 0xf7, 0x7b, 0xec, 0x01, 0x4c, 0x90, 0x3d, 0x00, 0x5d, 0x91, 0x8d, 0x38, 0x6e, 0x12, 0x2d, 0x1e, 0x7f, 0x33, 0x3d, 0x04, 0x85, 0xb4, 0x0c, 0x12, 0x94, 0x35, 0xcc, 0x01, 0xa3, 0xd6, 0xbd, 0x00, 0xb2, 0xd7, 0xad, 0x38, 0xc1, 0x58, 0xdd, 0x1e, 0xd0, 0x79, 0x1d, 0x04, 0xe6, 0xfa, 0x0c, 0x12, 0xf7, 0x7b, 0x8c, 0x19, 0x82, 0x91, 0xfc, 0x7a, 0x20, 0x92, 0xe8, 0x7a, 0x20, 0x92, 0xe8, 0x7a, 0x20, 0x92, 0xe9, 0x7a, 0x20, 0x12, 0xe8, 0x7a, 0x20, 0x12, 0xe9, 0x7a, 0x20, 0x92, 0xe8, 0x7a, 0x20, 0xb2, 0xe8, 0x7a, 0x20, 0xb2, 0xe9, 0x7a, 0x20, 0x32, 0xe8, 0x7a, 0x20, 0x32, 0xe9, 0x05, 0x40, 0xd0, 0xe8, 0x0f, 0x80, 0xfd, 0xe8, 0x9f, 0x3f, 0xd4, 0xe1, 0x9f, 0x2f, 0xf5, 0xe1, 0x9f, 0x1f, 0x97, 0xe1, 0x9f, 0x6f, 0xb8, 0xe1, 0xb0, 0x80, 0x7b, 0x80, 0xb0, 0x80, 0xfb, 0x80, 0x84, 0x2f, 0xa0, 0xe1, 0x84, 0x20, 0xa0, 0xe1, 0x04, 0x20, 0xa0, 0xe1, 0x84, 0x40, 0xa0, 0xe1, 0x24, 0x20, 0xa0, 0xe1, 0x24, 0x21, 0xa0, 0xe1, 0x04, 0x20, 0xa0, 0xe1, 0x24, 0x41, 0xa0, 0xe1, 0x91, 0x57, 0x21, 0xee, 0x91, 0x57, 0x21, 0xfe, 0x91, 0x57, 0x21, 0xee, 0x91, 0x57, 0x21, 0xfe, 0x91, 0x57, 0x21, 0x9e, 0x91, 0x57, 0x21, 0x9e, 0xf1, 0x57, 0x44, 0xec, 0xf1, 0x57, 0x44, 0xfc, 0xf1, 0x57, 0x44, 0xec, 0xf1, 0x57, 0x44, 0xfc, 0xf1, 0x57, 0x44, 0xcc, 0xf1, 0x57, 0x44, 0xcc, 0x92, 0x43, 0x21, 0xe0, 0x92, 0x43, 0x31, 0xe0, 0x92, 0x43, 0x21, 0x10, 0x92, 0x43, 0x31, 0x10, 0x95, 0x36, 0x62, 0xe0, 0x95, 0x36, 0x62, 0x10, 0x07, 0x30, 0xa0, 0xe3, 0x07, 0x30, 0xa0, 0xe3, 0x07, 0x30, 0xa0, 0xe3, 0x06, 0x30, 0xe0, 0xe3, 0xff, 0x4e, 0xa0, 0xe3, 0xff, 0x58, 0xa0, 0xe3, 0x2a, 0x70, 0xa0, 0xe3, 0x2a, 0x75, 0xa0, 0xe3, 0xff, 0x78, 0xa0, 0xe3, 0x2a, 0x71, 0xa0, 0xe3, 0x2a, 0x71, 0xa0, 0xe3, 0x2a, 0xf1, 0xa0, 0xe3, 0x00, 0x71, 0xa0, 0xe3, 0x28, 0x71, 0xa0, 0xe3, 0x28, 0x71, 0xa0, 0xe3, 0x28, 0x71, 0xa0, 0xe3, 0x28, 0x71, 0xa0, 0xe3, 0x2a, 0x7f, 0xa0, 0xe3, 0xff, 0x6f, 0x0f, 0xe3, 0xff, 0x9f, 0x0f, 0xe3, 0x07, 0x30, 0xb0, 0xe3, 0xff, 0x4e, 0xa0, 0x03, 0xff, 0x58, 0xb0, 0x03, 0x03, 0x20, 0xa0, 0xe1, 0x03, 0x20, 0xb0, 0xe1, 0x03, 0x20, 0xa0, 0x01, 0x03, 0x20, 0xb0, 0x01, 0x08, 0xc0, 0xa0, 0xe1, 0x03, 0x20, 0xa0, 0xe1, 0x08, 0xc0, 0xa0, 0xe1, 0x03, 0x20, 0xa0, 0xe1, 0x08, 0xc0, 0xa0, 0xe1, 0x03, 0x20, 0xa0, 0xe1, 0x08, 0xc0, 0xa0, 0xe1, 0x03, 0x20, 0xa0, 0xe1, 0x07, 0x30, 0x40, 0xe3, 0xff, 0x6f, 0x4f, 0xe3, 0xf0, 0x4f, 0x40, 0x03, 0x92, 0x1e, 0x11, 0xee, 0xd6, 0xff, 0xff, 0xee, 0x92, 0x1e, 0x11, 0xfe, 0x30, 0xf9, 0xff, 0xfe, 0x92, 0x1e, 0x11, 0xee, 0xd6, 0xff, 0xff, 0xee, 0x92, 0x1e, 0x11, 0xfe, 0x30, 0xf9, 0xff, 0xfe, 0xd6, 0xff, 0xff, 0x0e, 0xd6, 0xff, 0xff, 0x0e, 0x11, 0x57, 0x54, 0xec, 0x11, 0x57, 0x54, 0xfc, 0x11, 0x57, 0x54, 0xec, 0x11, 0x57, 0x54, 0xfc, 0x11, 0x57, 0x54, 0x3c, 0x11, 0x57, 0x54, 0x3c, 0x00, 0x80, 0x0f, 0xe1, 0x00, 0x80, 0x0f, 0xe1, 0x00, 0x80, 0x4f, 0xe1, 0x05, 0xf0, 0x28, 0xe3, 0x05, 0xf0, 0x28, 0xe3, 0x05, 0xf0, 0x28, 0xe3, 0x05, 0xf0, 0x24, 0xe3, 0x05, 0xf0, 0x28, 0xe3, 0x05, 0xf0, 0x28, 0xe3, 0x05, 0xf0, 0x2c, 0xe3, 0x05, 0xf0, 0x29, 0xe3, 0x05, 0xf0, 0x21, 0xe3, 0x05, 0xf0, 0x22, 0xe3, 0x05, 0xf0, 0x29, 0xe3, 0x05, 0xf0, 0x29, 0xe3, 0x05, 0xf0, 0x2e, 0xe3, 0x05, 0xf0, 0x69, 0xe3, 0x05, 0xf0, 0x6f, 0xe3, 0x05, 0xf0, 0x2f, 0xe3, 0xff, 0xf8, 0x2c, 0xe3, 0x2a, 0xf1, 0x28, 0xe3, 0x2a, 0xf1, 0x2c, 0xe3, 0x28, 0xf1, 0x6f, 0xe3, 0x28, 0xf1, 0x6f, 0xe3, 0x28, 0xf1, 0x6f, 0xe3, 0x28, 0xf1, 0x6f, 0xe3, 0x00, 0xf0, 0x28, 0xe1, 0x00, 0xf0, 0x24, 0xe1, 0x00, 0xf0, 0x28, 0xe1, 0x00, 0xf0, 0x28, 0xe1, 0x00, 0xf0, 0x2c, 0xe1, 0x00, 0xf0, 0x29, 0xe1, 0x00, 0xf0, 0x21, 0xe1, 0x00, 0xf0, 0x22, 0xe1, 0x00, 0xf0, 0x29, 0xe1, 0x00, 0xf0, 0x29, 0xe1, 0x00, 0xf0, 0x2e, 0xe1, 0x00, 0xf0, 0x69, 0xe1, 0x00, 0xf0, 0x6f, 0xe1, 0x00, 0xf0, 0x2f, 0xe1, 0x96, 0x07, 0x05, 0xe0, 0x96, 0x07, 0x15, 0xe0, 0x96, 0x07, 0x05, 0xc0, 0x96, 0x07, 0x15, 0xd0, 0x07, 0x30, 0xe0, 0xe3, 0x07, 0x30, 0xe0, 0xe3, 0x07, 0x30, 0xe0, 0xe3, 0x06, 0x30, 0xa0, 0xe3, 0xff, 0x70, 0xe0, 0xe3, 0xff, 0x4e, 0xe0, 0xe3, 0xff, 0x58, 0xe0, 0xe3, 0xff, 0x78, 0xe0, 0xe3, 0x2a, 0x71, 0xe0, 0xe3, 0x2a, 0x71, 0xe0, 0xe3, 0x28, 0x71, 0xe0, 0xe3, 0x28, 0x71, 0xe0, 0xe3, 0x28, 0x71, 0xe0, 0xe3, 0x28, 0x71, 0xe0, 0xe3, 0x07, 0x30, 0xf0, 0xe3, 0xff, 0x4e, 0xe0, 0x03, 0xff, 0x58, 0xf0, 0x03, 0x03, 0x20, 0xe0, 0xe1, 0x03, 0x20, 0xf0, 0xe1, 0x86, 0x59, 0xe0, 0xe1, 0xa6, 0x54, 0xe0, 0xe1, 0x46, 0x52, 0xe0, 0xe1, 0x66, 0x53, 0xe0, 0xe1, 0x66, 0x50, 0xe0, 0xe1, 0x03, 0x20, 0xe0, 0x01, 0x03, 0x25, 0xf0, 0x01, 0x16, 0x57, 0xe0, 0xe1, 0x36, 0x57, 0xf0, 0xe1, 0x56, 0x57, 0xe0, 0xc1, 0x76, 0x57, 0xf0, 0xb1, 0x00, 0x50, 0x68, 0xe2, 0x00, 0xf0, 0x20, 0xe3, 0x00, 0xf0, 0x20, 0xe3, 0x00, 0xf0, 0x20, 0xc3, 0x0f, 0x4a, 0x85, 0xe3, 0x0f, 0x4a, 0x85, 0xe3, 0x0f, 0x4a, 0x85, 0xe3, 0xff, 0x78, 0x88, 0xe3, 0x2a, 0x71, 0x88, 0xe3, 0x2a, 0x71, 0x88, 0xe3, 0x28, 0x71, 0x88, 0xe3, 0x28, 0x71, 0x88, 0xe3, 0x28, 0x71, 0x88, 0xe3, 0x28, 0x71, 0x88, 0xe3, 0x06, 0x40, 0x85, 0xe1, 0x86, 0x42, 0x85, 0xe1, 0xa6, 0x42, 0x85, 0xe1, 0xa6, 0x42, 0x85, 0xe1, 0xc6, 0x42, 0x85, 0xe1, 0xe6, 0x42, 0x85, 0xe1, 0x18, 0x69, 0x87, 0xe1, 0x38, 0x69, 0x87, 0xe1, 0x58, 0x69, 0x87, 0xe1, 0x78, 0x69, 0x87, 0xe1, 0x66, 0x40, 0x85, 0xe1, 0x0f, 0x5a, 0x85, 0xe3, 0x0f, 0x5a, 0x85, 0xe3, 0x0f, 0x5a, 0x85, 0xe3, 0xff, 0x78, 0x87, 0xe3, 0x2a, 0x71, 0x87, 0xe3, 0x2a, 0x71, 0x87, 0xe3, 0x28, 0x71, 0x87, 0xe3, 0x28, 0x71, 0x87, 0xe3, 0x28, 0x71, 0x87, 0xe3, 0x28, 0x71, 0x87, 0xe3, 0x05, 0x40, 0x84, 0xe1, 0x85, 0x42, 0x84, 0xe1, 0xa5, 0x42, 0x84, 0xe1, 0xa5, 0x42, 0x84, 0xe1, 0xc5, 0x42, 0x84, 0xe1, 0xe5, 0x42, 0x84, 0xe1, 0x17, 0x69, 0x86, 0xe1, 0x37, 0x69, 0x86, 0xe1, 0x57, 0x69, 0x86, 0xe1, 0x77, 0x69, 0x86, 0xe1, 0x65, 0x40, 0x84, 0xe1, 0x0f, 0x4a, 0x95, 0x03, 0x06, 0x40, 0x85, 0x11, 0x86, 0x42, 0x95, 0x01, 0x78, 0x69, 0x87, 0x31, 0x66, 0x40, 0x95, 0x81, 0x0f, 0x5a, 0x85, 0x23, 0x05, 0x40, 0x94, 0x01, 0x57, 0x69, 0x86, 0x11, 0x77, 0x69, 0x96, 0xb1, 0x65, 0x40, 0x94, 0xc1, 0x22, 0x30, 0x81, 0xe1, 0x42, 0x30, 0x81, 0xe1, 0x13, 0x20, 0x82, 0xe6, 0x93, 0x2f, 0x82, 0xe6, 0x13, 0x20, 0x82, 0xe6, 0x93, 0x27, 0x82, 0xe6, 0x12, 0x20, 0x83, 0xe6, 0xd3, 0x2f, 0x82, 0xe6, 0xd3, 0x27, 0x82, 0xe6, 0x04, 0x70, 0x9d, 0xe4, 0x80, 0x07, 0xbd, 0xe8, 0x04, 0x70, 0x2d, 0xe5, 0x80, 0x07, 0x2d, 0xe9, 0x52, 0x10, 0x03, 0xe1, 0x52, 0x10, 0x03, 0x11, 0x13, 0x1f, 0x22, 0xe6, 0x13, 0x1f, 0x22, 0xc6, 0x93, 0x1f, 0x22, 0xe6, 0x93, 0x1f, 0x22, 0xd6, 0x57, 0x60, 0x48, 0xe1, 0x57, 0x60, 0x48, 0x81, 0x57, 0x60, 0x68, 0xe1, 0x57, 0x60, 0x68, 0x81, 0x50, 0x9f, 0x2c, 0xe6, 0x50, 0x9f, 0x2c, 0x06, 0x52, 0x10, 0x23, 0xe1, 0x52, 0x10, 0x23, 0x11, 0x73, 0x1f, 0x22, 0xe6, 0x73, 0x1f, 0x22, 0xc6, 0xf3, 0x1f, 0x22, 0xe6, 0xf3, 0x1f, 0x22, 0xd6, 0x32, 0x1f, 0xff, 0xe6, 0x32, 0x1f, 0xff, 0x16, 0x39, 0x1f, 0xbf, 0xe6, 0x35, 0x1f, 0xbf, 0x16, 0xb3, 0x8f, 0xbf, 0xe6, 0xb4, 0xcf, 0xbf, 0x16, 0xb9, 0x4f, 0xff, 0xe6, 0xb1, 0x9f, 0xff, 0x16, 0x00, 0x0a, 0x12, 0xf8, 0x00, 0x0a, 0x13, 0xf9, 0x00, 0x0a, 0x95, 0xf8, 0x00, 0x0a, 0x96, 0xf9, 0x00, 0x0a, 0x34, 0xf8, 0x00, 0x0a, 0x37, 0xf9, 0x00, 0x0a, 0xb9, 0xf8, 0x00, 0x0a, 0xb8, 0xf9, 0x00, 0x0a, 0x12, 0xf8, 0x00, 0x0a, 0x13, 0xf9, 0x00, 0x0a, 0x95, 0xf8, 0x00, 0x0a, 0x96, 0xf9, 0x00, 0x0a, 0x34, 0xf8, 0x00, 0x0a, 0x37, 0xf9, 0x00, 0x0a, 0xb9, 0xf8, 0x00, 0x0a, 0xb8, 0xf9, 0x00, 0x0a, 0x91, 0xf8, 0x00, 0x0a, 0xb1, 0xf8, 0xe4, 0x2f, 0xa0, 0xe1, 0xe4, 0x20, 0xa0, 0xe1, 0x04, 0x20, 0xa0, 0xe1, 0xe4, 0x40, 0xa0, 0xe1, 0x0f, 0x4a, 0x65, 0xe2, 0x0f, 0x4a, 0x65, 0xe2, 0x0f, 0x4a, 0x65, 0xe2, 0xff, 0x78, 0x68, 0xe2, 0x2a, 0x71, 0x68, 0xe2, 0x2a, 0x71, 0x68, 0xe2, 0x28, 0x71, 0x68, 0xe2, 0x28, 0x71, 0x68, 0xe2, 0x28, 0x71, 0x68, 0xe2, 0x28, 0x71, 0x68, 0xe2, 0x06, 0x40, 0x65, 0xe0, 0x86, 0x42, 0x65, 0xe0, 0xa6, 0x42, 0x65, 0x30, 0xa6, 0x42, 0x65, 0xe0, 0xc6, 0x42, 0x65, 0xe0, 0xe6, 0x42, 0x65, 0xe0, 0x18, 0x69, 0x67, 0xe0, 0x38, 0x69, 0x67, 0xe0, 0x58, 0x69, 0x67, 0xe0, 0x78, 0x69, 0x67, 0xd0, 0x66, 0x40, 0x65, 0xe0, 0x0f, 0x5a, 0x65, 0xe2, 0x0f, 0x5a, 0x65, 0xe2, 0x0f, 0x5a, 0x65, 0xe2, 0xff, 0x78, 0x67, 0xe2, 0x2a, 0x71, 0x67, 0xe2, 0x2a, 0x71, 0x67, 0xe2, 0x28, 0x71, 0x67, 0xe2, 0x28, 0x71, 0x67, 0xe2, 0x28, 0x71, 0x67, 0xe2, 0x28, 0x71, 0x67, 0xe2, 0x05, 0x40, 0x64, 0xe0, 0x85, 0x42, 0x64, 0xe0, 0xa5, 0x42, 0x64, 0xe0, 0xa5, 0x42, 0x64, 0x10, 0xc5, 0x42, 0x64, 0xe0, 0xe5, 0x42, 0x64, 0xe0, 0x17, 0x69, 0x66, 0xc0, 0x37, 0x69, 0x66, 0xe0, 0x57, 0x69, 0x66, 0xe0, 0x77, 0x69, 0x66, 0xe0, 0x65, 0x40, 0x64, 0xe0, 0xff, 0x78, 0x77, 0xe2, 0xff, 0x78, 0x77, 0xe2, 0xff, 0x78, 0x77, 0xe2, 0xff, 0x78, 0x77, 0xe2, 0x2a, 0x71, 0x78, 0xe2, 0x2a, 0x71, 0x78, 0xe2, 0x28, 0x71, 0x78, 0xe2, 0x28, 0x71, 0x78, 0xe2, 0x28, 0x71, 0x78, 0xe2, 0x28, 0x71, 0x78, 0xe2, 0x0f, 0x4a, 0xe5, 0xe2, 0x0f, 0x4a, 0xe5, 0xe2, 0x0f, 0x4a, 0xe5, 0xe2, 0xff, 0x78, 0xe8, 0xe2, 0x2a, 0x71, 0xe8, 0xe2, 0x2a, 0x71, 0xe8, 0xe2, 0x28, 0x71, 0xe8, 0xe2, 0x28, 0x71, 0xe8, 0xe2, 0x28, 0x71, 0xe8, 0xe2, 0x28, 0x71, 0xe8, 0xe2, 0x06, 0x40, 0xe5, 0xe0, 0x86, 0x42, 0xe5, 0xe0, 0xa6, 0x42, 0xe5, 0x30, 0xa6, 0x42, 0xe5, 0xe0, 0xc6, 0x42, 0xe5, 0xe0, 0xe6, 0x42, 0xe5, 0xe0, 0x18, 0x69, 0xe7, 0xe0, 0x38, 0x69, 0xe7, 0xe0, 0x58, 0x69, 0xe7, 0xe0, 0x78, 0x69, 0xe7, 0xd0, 0xfe, 0x1e, 0xf8, 0xe2, 0x0f, 0x5a, 0xe5, 0xe2, 0x0f, 0x5a, 0xe5, 0xe2, 0x0f, 0x5a, 0xe5, 0xe2, 0xff, 0x78, 0xe7, 0xe2, 0x2a, 0x71, 0xe7, 0xe2, 0x2a, 0x71, 0xe7, 0xe2, 0x28, 0x71, 0xe7, 0xe2, 0x28, 0x71, 0xe7, 0xe2, 0x28, 0x71, 0xe7, 0xe2, 0x28, 0x71, 0xe7, 0xe2, 0x05, 0x40, 0xe4, 0xe0, 0x85, 0x42, 0xe4, 0xe0, 0xa5, 0x42, 0xe4, 0xe0, 0xa5, 0x42, 0xe4, 0x10, 0xc5, 0x42, 0xe4, 0xe0, 0xe5, 0x42, 0xe4, 0xe0, 0x17, 0x69, 0xe6, 0xc0, 0x37, 0x69, 0xe6, 0xe0, 0x57, 0x69, 0xe6, 0xe0, 0x77, 0x69, 0xe6, 0xe0, 0x61, 0x00, 0xa0, 0xe1, 0x6f, 0xd0, 0xa0, 0xe1, 0x6e, 0xf0, 0xa0, 0xe1, 0x6d, 0xe0, 0xa0, 0xe1, 0x61, 0x00, 0xb0, 0xe1, 0x6f, 0xd0, 0xb0, 0xe1, 0x6e, 0xf0, 0xb0, 0xe1, 0x6d, 0xe0, 0xb0, 0xe1, 0x13, 0x1f, 0x12, 0xe6, 0x13, 0x1f, 0x12, 0xc6, 0x93, 0x1f, 0x12, 0xe6, 0x93, 0x1f, 0x12, 0xd6, 0x30, 0x9f, 0x1c, 0xe6, 0x30, 0x9f, 0x1c, 0x06, 0x0f, 0x4a, 0xc5, 0xe2, 0x0f, 0x4a, 0xc5, 0xe2, 0x0f, 0x4a, 0xc5, 0xe2, 0xff, 0x78, 0xc8, 0xe2, 0x2a, 0x71, 0xc8, 0xe2, 0x2a, 0x71, 0xc8, 0xe2, 0x28, 0x71, 0xc8, 0xe2, 0x28, 0x71, 0xc8, 0xe2, 0x28, 0x71, 0xc8, 0xe2, 0x28, 0x71, 0xc8, 0xe2, 0x06, 0x40, 0xc5, 0xe0, 0x86, 0x42, 0xc5, 0xe0, 0xa6, 0x42, 0xc5, 0xe0, 0xa6, 0x42, 0xc5, 0xe0, 0xc6, 0x42, 0xc5, 0xe0, 0xe6, 0x42, 0xc5, 0xe0, 0x18, 0x69, 0xc7, 0xe0, 0x38, 0x69, 0xc7, 0xe0, 0x58, 0x69, 0xc7, 0xe0, 0x78, 0x69, 0xc7, 0xe0, 0x0f, 0x5a, 0xc5, 0xe2, 0x0f, 0x5a, 0xc5, 0xe2, 0x0f, 0x5a, 0xc5, 0xe2, 0xff, 0x78, 0xc7, 0xe2, 0x2a, 0x71, 0xc7, 0xe2, 0x2a, 0x71, 0xc7, 0xe2, 0x28, 0x71, 0xc7, 0xe2, 0x28, 0x71, 0xc7, 0xe2, 0x28, 0x71, 0xc7, 0xe2, 0x28, 0x71, 0xc7, 0xe2, 0x05, 0x40, 0xc4, 0xe0, 0x85, 0x42, 0xc4, 0xe0, 0xa5, 0x42, 0xc4, 0xe0, 0xa5, 0x42, 0xc4, 0xe0, 0xc5, 0x42, 0xc4, 0xe0, 0xe5, 0x42, 0xc4, 0xe0, 0x17, 0x69, 0xc6, 0xe0, 0x37, 0x69, 0xc6, 0xe0, 0x57, 0x69, 0xc6, 0xe0, 0x77, 0x69, 0xc6, 0xe0, 0x55, 0x48, 0xa0, 0xe7, 0x55, 0x48, 0xaf, 0xc7, 0xb1, 0x9f, 0x82, 0xe6, 0xb1, 0x9f, 0x82, 0x16, 0x00, 0x02, 0x01, 0xf1, 0x00, 0x02, 0x01, 0xf1, 0x00, 0x00, 0x01, 0xf1, 0x00, 0x00, 0x01, 0xf1, 0x04, 0xf0, 0x20, 0xe3, 0x04, 0xf0, 0x20, 0x03, 0x12, 0x4f, 0x38, 0xe6, 0x12, 0x4f, 0x38, 0xc6, 0x92, 0x4f, 0x38, 0xe6, 0x92, 0x4f, 0x38, 0xc6, 0x32, 0x4f, 0x38, 0xe6, 0x32, 0x4f, 0x38, 0xc6, 0x72, 0x4f, 0x38, 0xe6, 0x72, 0x4f, 0x38, 0xc6, 0xf2, 0x4f, 0x38, 0xe6, 0xf2, 0x4f, 0x38, 0xc6, 0x81, 0x09, 0x03, 0xe1, 0xc6, 0x14, 0x05, 0xe1, 0xa2, 0x23, 0x04, 0xe1, 0xe3, 0x48, 0x08, 0xe1, 0x81, 0x09, 0x03, 0xa1, 0xc6, 0x14, 0x05, 0xd1, 0xa2, 0x23, 0x04, 0x11, 0xe3, 0x48, 0x08, 0x01, 0x13, 0x85, 0x02, 0xe7, 0x33, 0x85, 0x02, 0xe7, 0x13, 0x85, 0x02, 0x07, 0x33, 0x85, 0x02, 0x87, 0x95, 0x28, 0xe3, 0xe0, 0x95, 0x28, 0xf3, 0xe0, 0x95, 0x28, 0xe3, 0x00, 0x95, 0x28, 0xf3, 0x80, 0x89, 0x30, 0x41, 0xe1, 0xc4, 0x51, 0x46, 0xe1, 0xa3, 0x42, 0x42, 0xe1, 0xe8, 0x84, 0x43, 0xe1, 0x89, 0x30, 0x41, 0xa1, 0xc4, 0x51, 0x46, 0xd1, 0xa3, 0x42, 0x42, 0x11, 0xe8, 0x84, 0x43, 0x01, 0x15, 0x28, 0x43, 0xe7, 0x35, 0x28, 0x43, 0xe7, 0x15, 0x28, 0x43, 0x07, 0x35, 0x28, 0x43, 0x87, 0x83, 0x8a, 0x22, 0xe1, 0xc3, 0x95, 0x28, 0xe1, 0x87, 0x85, 0x22, 0x01, 0xc3, 0x80, 0x21, 0x81, 0x53, 0x85, 0x02, 0xe7, 0x73, 0x85, 0x02, 0xe7, 0x53, 0x85, 0x02, 0x07, 0x73, 0x85, 0x02, 0x87, 0x55, 0x21, 0x49, 0xe7, 0x72, 0x48, 0x4b, 0xe7, 0x55, 0x86, 0x42, 0x07, 0x73, 0x18, 0x40, 0x87, 0x12, 0x43, 0x51, 0xe7, 0x33, 0x12, 0x54, 0xe7, 0x12, 0x43, 0x51, 0x37, 0x33, 0x12, 0x54, 0x27, 0xd2, 0x43, 0x51, 0xe7, 0xf3, 0x12, 0x54, 0xe7, 0xd2, 0x43, 0x51, 0x37, 0xf3, 0x12, 0x54, 0x27, 0x13, 0xf4, 0x52, 0xe7, 0x32, 0xf1, 0x53, 0xe7, 0x13, 0xf4, 0x52, 0x37, 0x32, 0xf1, 0x53, 0x27, 0x13, 0xf4, 0x02, 0xe7, 0x32, 0xf1, 0x03, 0xe7, 0x13, 0xf4, 0x02, 0xb7, 0x32, 0xf1, 0x03, 0xa7, 0x89, 0x00, 0x63, 0xe1, 0xc4, 0x01, 0x65, 0xe1, 0xa2, 0x02, 0x64, 0xe1, 0xe3, 0x04, 0x68, 0xe1, 0x89, 0x00, 0x61, 0xa1, 0xc6, 0x04, 0x65, 0xd1, 0xa3, 0x02, 0x62, 0x11, 0xe3, 0x04, 0x68, 0x01, 0x90, 0x31, 0xc9, 0xe0, 0x90, 0x32, 0xd9, 0xe0, 0x94, 0x85, 0xc3, 0x00, 0x94, 0x83, 0xd3, 0x00, 0xa9, 0x00, 0x23, 0xe1, 0xe9, 0x02, 0x23, 0xe1, 0x50, 0xf1, 0x03, 0xe7, 0x79, 0xf2, 0x03, 0xe7, 0x53, 0xf2, 0x08, 0x07, 0x74, 0xf3, 0x07, 0x17, 0x05, 0x05, 0x4d, 0xf8, 0x01, 0x05, 0x4d, 0xf9, 0x00, 0x05, 0xcd, 0xf8, 0x0f, 0x05, 0xcd, 0xf9, 0x1f, 0x05, 0x6d, 0xf8, 0x13, 0x05, 0x6d, 0xf9, 0x02, 0x05, 0xed, 0xf8, 0x0e, 0x05, 0xed, 0xf9, 0x0b, 0x05, 0xcd, 0xf9, 0x0a, 0x05, 0xcd, 0xf8, 0x09, 0x05, 0x4d, 0xf9, 0x05, 0x05, 0x4d, 0xf8, 0x05, 0x05, 0xed, 0xf9, 0x05, 0x05, 0xed, 0xf8, 0x05, 0x05, 0x6d, 0xf9, 0x05, 0x05, 0x6d, 0xf8, 0x05, 0x05, 0xcd, 0xf8, 0x05, 0x05, 0xed, 0xf8, 0x05, 0x05, 0x4d, 0xf8, 0x01, 0x05, 0x4d, 0xf9, 0x00, 0x05, 0xcd, 0xf8, 0x0f, 0x05, 0xcd, 0xf9, 0x1f, 0x05, 0x6d, 0xf8, 0x13, 0x05, 0x6d, 0xf9, 0x02, 0x05, 0xed, 0xf8, 0x0e, 0x05, 0xed, 0xf9, 0x0b, 0x05, 0xcd, 0xf9, 0x0a, 0x05, 0xcd, 0xf8, 0x09, 0x05, 0x4d, 0xf9, 0x05, 0x05, 0x4d, 0xf8, 0x05, 0x05, 0xed, 0xf9, 0x05, 0x05, 0xed, 0xf8, 0x05, 0x05, 0x6d, 0xf9, 0x05, 0x05, 0x6d, 0xf8, 0x05, 0x05, 0xcd, 0xf8, 0x05, 0x05, 0xed, 0xf8, 0x1a, 0x80, 0xa0, 0xe6, 0x1a, 0x80, 0xa0, 0xe6, 0x9a, 0x8f, 0xa0, 0xe6, 0x5a, 0x80, 0xa0, 0xe6, 0xda, 0x80, 0xa0, 0xe6, 0x37, 0x2f, 0xa0, 0xe6, 0x35, 0x3f, 0xaf, 0xe6, 0x54, 0x2f, 0x13, 0xe6, 0x54, 0x2f, 0x13, 0xb6, 0x76, 0x1f, 0x10, 0xe6, 0x72, 0x5f, 0x13, 0x16, 0xf4, 0x9f, 0x12, 0xe6, 0xf2, 0x5f, 0x11, 0x06, 0x01, 0x80, 0x81, 0xfd, 0x00, 0x71, 0x82, 0xfd, 0x38, 0x62, 0x03, 0xfd, 0x1e, 0x53, 0x24, 0xfd, 0x04, 0x44, 0xa5, 0xfc, 0x12, 0x35, 0x26, 0xfc, 0x01, 0x26, 0xc7, 0xfd, 0x00, 0x17, 0xc8, 0xfd, 0x38, 0x08, 0x49, 0xfd, 0x1e, 0x19, 0x6a, 0xfd, 0x04, 0x20, 0xeb, 0xfc, 0x12, 0x31, 0x6c, 0xfc, 0x01, 0x4c, 0x80, 0xed, 0x00, 0x5d, 0x81, 0xed, 0x38, 0x6e, 0x02, 0xed, 0x1e, 0x7f, 0x23, 0xed, 0x04, 0x85, 0xa4, 0xec, 0x12, 0x94, 0x25, 0xec, 0x01, 0xa3, 0xc6, 0xed, 0x00, 0xb2, 0xc7, 0xed, 0x38, 0xc1, 0x48, 0xed, 0x1e, 0xd0, 0x69, 0xed, 0x04, 0xe6, 0xea, 0xec, 0x12, 0xf7, 0x6b, 0xec, 0x01, 0x4c, 0x80, 0x3d, 0x00, 0x5d, 0x81, 0x8d, 0x38, 0x6e, 0x02, 0x2d, 0x1e, 0x7f, 0x23, 0x3d, 0x04, 0x85, 0xa4, 0x0c, 0x12, 0x94, 0x25, 0xcc, 0x01, 0xa3, 0xc6, 0xbd, 0x00, 0xb2, 0xc7, 0xad, 0x38, 0xc1, 0x48, 0xdd, 0x1e, 0xd0, 0x69, 0x1d, 0x04, 0xe6, 0xea, 0x0c, 0x12, 0xf7, 0x6b, 0x8c, 0x19, 0x82, 0x81, 0xfc, 0x7a, 0x20, 0x82, 0xe8, 0x7a, 0x40, 0x83, 0xe8, 0x7a, 0x20, 0x84, 0xe9, 0x7a, 0x20, 0x05, 0xe8, 0x7a, 0x01, 0x06, 0xe9, 0x7a, 0x20, 0x0d, 0xe9, 0x7a, 0x20, 0xa8, 0xe8, 0x7a, 0x20, 0xa9, 0xe9, 0x7a, 0x00, 0x2d, 0xe8, 0xa2, 0x20, 0x20, 0xe9, 0x93, 0x1f, 0xc4, 0xe1, 0x92, 0x4f, 0xe5, 0xe1, 0x91, 0x2f, 0x87, 0xe1, 0x92, 0x6f, 0xa8, 0xe1, 0x00, 0x30, 0x2a, 0x55, 0x00, 0x30, 0xaa, 0x55, 0x0f, 0x4a, 0x45, 0xe2, 0x0f, 0x4a, 0x45, 0xe2, 0x0f, 0x4a, 0x45, 0xe2, 0xff, 0x78, 0x48, 0xe2, 0x2a, 0x71, 0x48, 0xe2, 0x2a, 0x71, 0x48, 0xe2, 0x28, 0x71, 0x48, 0xe2, 0x28, 0x71, 0x48, 0xe2, 0x28, 0x71, 0x48, 0xe2, 0x28, 0x71, 0x48, 0xe2, 0x06, 0x40, 0x45, 0xe0, 0x86, 0x42, 0x45, 0xe0, 0xa6, 0x42, 0x45, 0xe0, 0xa6, 0x42, 0x45, 0xe0, 0xc6, 0x42, 0x45, 0xe0, 0xe6, 0x42, 0x45, 0xe0, 0x18, 0x69, 0x47, 0xe0, 0x38, 0x69, 0x47, 0xe0, 0x58, 0x69, 0x47, 0xe0, 0x78, 0x69, 0x47, 0xe0, 0x0f, 0x5a, 0x45, 0xe2, 0x0f, 0x5a, 0x45, 0xe2, 0x0f, 0x5a, 0x45, 0xe2, 0xff, 0x78, 0x47, 0xe2, 0x2a, 0x71, 0x47, 0xe2, 0x2a, 0x71, 0x47, 0xe2, 0x28, 0x71, 0x47, 0xe2, 0x28, 0x71, 0x47, 0xe2, 0x28, 0x71, 0x47, 0xe2, 0x05, 0x40, 0x44, 0xe0, 0x85, 0x42, 0x44, 0xe0, 0xa5, 0x42, 0x44, 0xe0, 0xa5, 0x42, 0x44, 0xe0, 0xc5, 0x42, 0x44, 0xe0, 0xe5, 0x42, 0x44, 0xe0, 0x17, 0x69, 0x46, 0xe0, 0x37, 0x69, 0x46, 0xe0, 0x57, 0x69, 0x46, 0xe0, 0x77, 0x69, 0x46, 0xe0, 0x22, 0x30, 0x41, 0xe0, 0x42, 0x30, 0x41, 0xe0, 0xff, 0x78, 0x58, 0xe2, 0xff, 0x78, 0x58, 0xe2, 0xff, 0x78, 0x58, 0xe2, 0xff, 0x78, 0x58, 0xe2, 0x2a, 0x71, 0x58, 0xe2, 0x2a, 0x71, 0x58, 0xe2, 0x28, 0x71, 0x58, 0xe2, 0x28, 0x71, 0x58, 0xe2, 0x28, 0x71, 0x58, 0xe2, 0x28, 0x71, 0x58, 0xe2, 0x10, 0x00, 0x00, 0xef, 0x00, 0x00, 0x00, 0xef, 0xff, 0xff, 0xff, 0xef, 0x92, 0x10, 0x03, 0xe1, 0x94, 0x40, 0x06, 0xe1, 0x91, 0x50, 0x49, 0xe1, 0x74, 0x20, 0xa3, 0xe6, 0x76, 0x40, 0xa5, 0xe6, 0x79, 0x64, 0xa2, 0xb6, 0x74, 0x58, 0xa1, 0xe6, 0x73, 0x7c, 0xa8, 0xe6, 0x74, 0x00, 0x81, 0xa6, 0x77, 0x60, 0x82, 0xe6, 0x78, 0x34, 0x85, 0xe6, 0x71, 0x38, 0x82, 0xe6, 0x73, 0x1c, 0x82, 0x06, 0x79, 0x10, 0xb3, 0xe6, 0x76, 0x60, 0xb1, 0x86, 0x73, 0x34, 0xb8, 0xe6, 0x74, 0x28, 0xb2, 0x36, 0x73, 0x9c, 0xb3, 0xe6, 0x74, 0x20, 0xaf, 0xa6, 0x76, 0x50, 0xaf, 0xe6, 0x79, 0x64, 0xaf, 0xe6, 0x71, 0x58, 0xaf, 0x36, 0x73, 0x8c, 0xaf, 0xe6, 0x74, 0x10, 0x8f, 0xe6, 0x77, 0x60, 0x8f, 0xe6, 0x75, 0x34, 0x8f, 0x26, 0x71, 0x38, 0x8f, 0xe6, 0x73, 0x2c, 0x8f, 0xa6, 0x79, 0x30, 0xbf, 0x16, 0x76, 0x10, 0xbf, 0xe6, 0x78, 0x34, 0xbf, 0xe6, 0x72, 0x28, 0xbf, 0xd6, 0x73, 0x9c, 0xbf, 0xe6, 0x0f, 0x0a, 0x35, 0xe3, 0x0f, 0x0a, 0x35, 0xe3, 0x0f, 0x0a, 0x35, 0xe3, 0xff, 0x08, 0x37, 0xe3, 0x2a, 0x01, 0x37, 0xe3, 0x2a, 0x01, 0x37, 0xe3, 0x28, 0x01, 0x37, 0xe3, 0x28, 0x01, 0x37, 0xe3, 0x28, 0x01, 0x37, 0xe3, 0x28, 0x01, 0x37, 0xe3, 0x05, 0x00, 0x34, 0xe1, 0x85, 0x02, 0x34, 0xe1, 0xa5, 0x02, 0x34, 0xe1, 0xa5, 0x02, 0x34, 0xe1, 0xc5, 0x02, 0x34, 0xe1, 0xe5, 0x02, 0x34, 0xe1, 0x17, 0x09, 0x36, 0xe1, 0x37, 0x09, 0x36, 0xe1, 0x57, 0x09, 0x36, 0xe1, 0x77, 0x09, 0x36, 0xe1, 0x0f, 0x0a, 0x15, 0xe3, 0x0f, 0x0a, 0x15, 0xe3, 0x0f, 0x0a, 0x15, 0xe3, 0xff, 0x08, 0x17, 0xe3, 0x2a, 0x01, 0x17, 0xe3, 0x2a, 0x01, 0x17, 0xe3, 0x28, 0x01, 0x17, 0xe3, 0x28, 0x01, 0x17, 0xe3, 0x28, 0x01, 0x17, 0xe3, 0x28, 0x01, 0x17, 0xe3, 0x05, 0x00, 0x14, 0xe1, 0x85, 0x02, 0x14, 0xe1, 0xa5, 0x02, 0x14, 0xe1, 0xa5, 0x02, 0x14, 0xe1, 0xc5, 0x02, 0x14, 0xe1, 0xe5, 0x02, 0x14, 0xe1, 0x17, 0x09, 0x16, 0xe1, 0x37, 0x09, 0x16, 0xe1, 0x57, 0x09, 0x16, 0xe1, 0x77, 0x09, 0x16, 0xe1, 0x13, 0x1f, 0x52, 0xe6, 0x13, 0x1f, 0x52, 0xc6, 0x93, 0x1f, 0x52, 0xe6, 0x93, 0x1f, 0x52, 0xd6, 0x30, 0x9f, 0x5c, 0xe6, 0x30, 0x9f, 0x5c, 0x06, 0x55, 0x48, 0xe0, 0xe7, 0x55, 0x48, 0xef, 0xc7, 0x12, 0x4f, 0x78, 0xe6, 0x12, 0x4f, 0x78, 0xc6, 0x92, 0x4f, 0x78, 0xe6, 0x92, 0x4f, 0x78, 0xc6, 0x32, 0x4f, 0x78, 0xe6, 0x32, 0x4f, 0x78, 0xc6, 0x72, 0x4f, 0x78, 0xe6, 0x72, 0x4f, 0x78, 0xc6, 0xf2, 0x4f, 0x78, 0xe6, 0xf2, 0x4f, 0x78, 0xc6, 0x95, 0x36, 0x44, 0xe0, 0x95, 0x36, 0x44, 0xb0, 0x96, 0x28, 0xa4, 0xe0, 0x92, 0x66, 0xa1, 0xc0, 0x92, 0x23, 0xb9, 0xe0, 0x91, 0x32, 0xb5, 0x00, 0x96, 0x28, 0x84, 0xe0, 0x92, 0x66, 0x81, 0xc0, 0x92, 0x23, 0x99, 0xe0, 0x91, 0x32, 0x95, 0x00, 0x13, 0x1f, 0x62, 0xe6, 0x19, 0x4f, 0x67, 0xc6, 0x98, 0x3f, 0x64, 0xe6, 0x92, 0x8f, 0x61, 0xd6, 0x31, 0x2f, 0x64, 0xe6, 0x39, 0x5f, 0x62, 0x86, 0x57, 0x1f, 0x63, 0xe6, 0x52, 0x3f, 0x66, 0xe6, 0x73, 0x1f, 0x65, 0xe6, 0x75, 0x3f, 0x62, 0xc6, 0xf4, 0x2f, 0x61, 0xe6, 0xf9, 0x4f, 0x66, 0xd6, 0x11, 0xf4, 0x82, 0xe7, 0x16, 0xf9, 0x84, 0xd7, 0x15, 0x73, 0x81, 0xe7, 0x12, 0x15, 0x83, 0xc7, 0x1a, 0x80, 0xe1, 0xe6, 0x1a, 0x80, 0xe4, 0xe6, 0x9a, 0x8f, 0xe5, 0xe6, 0x5a, 0x80, 0xff, 0xe6, 0xda, 0x80, 0xf0, 0xe6, 0x37, 0x2f, 0xe2, 0xe6, 0x35, 0x3f, 0xef, 0xe6, 0x54, 0x2f, 0x53, 0xe6, 0x54, 0x2f, 0x53, 0x16, 0x77, 0x4f, 0x52, 0xe6, 0x73, 0x1f, 0x51, 0x86, 0xf5, 0x1f, 0x58, 0xe6, 0xf3, 0x9f, 0x52, 0xd6, 0x74, 0x20, 0xe3, 0xe6, 0x76, 0x40, 0xe5, 0xe6, 0x79, 0x64, 0xe2, 0xb6, 0x74, 0x58, 0xe1, 0xe6, 0x73, 0x7c, 0xe8, 0xe6, 0x74, 0x00, 0xc1, 0xa6, 0x77, 0x60, 0xc2, 0xe6, 0x78, 0x34, 0xc5, 0xe6, 0x71, 0x38, 0xc2, 0xe6, 0x73, 0x1c, 0xc2, 0x06, 0x79, 0x10, 0xf3, 0xe6, 0x76, 0x60, 0xf1, 0x86, 0x73, 0x34, 0xf8, 0xe6, 0x74, 0x28, 0xf2, 0x36, 0x73, 0x9c, 0xf3, 0xe6, 0x74, 0x20, 0xef, 0xa6, 0x76, 0x50, 0xef, 0xe6, 0x79, 0x64, 0xef, 0xe6, 0x71, 0x58, 0xef, 0x36, 0x73, 0x8c, 0xef, 0xe6, 0x74, 0x10, 0xcf, 0xe6, 0x77, 0x60, 0xcf, 0xe6, 0x75, 0x34, 0xcf, 0x26, 0x71, 0x38, 0xcf, 0xe6, 0x73, 0x2c, 0xcf, 0xa6, 0x79, 0x30, 0xff, 0x16, 0x76, 0x10, 0xff, 0xe6, 0x78, 0x34, 0xff, 0xe6, 0x72, 0x28, 0xff, 0xd6, 0x73, 0x9c, 0xff, 0xe6, 0x02, 0xf0, 0x20, 0xe3, 0x02, 0xf0, 0x20, 0x83, 0x03, 0xf0, 0x20, 0xe3, 0x03, 0xf0, 0x20, 0xb3, 0x01, 0xf0, 0x20, 0xe3, 0x01, 0xf0, 0x20, 0x13, 0x04, 0xf0, 0x20, 0xe3, 0x03, 0xf0, 0x20, 0xe3, 0x02, 0xf0, 0x20, 0xe3, 0x01, 0xf0, 0x20, 0xe3, 0x00, 0xf0, 0x20, 0xe3, 0xef, 0xf0, 0x20, 0xc3 ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ]
+    expected:
+      insns:
+        -
+          asm_text: "adc r1, r2, #0xf"
+        -
+          asm_text: "adc r1, r2, #0xf"
+        -
+          asm_text: "adc r1, r2, #0xf"
+        -
+          asm_text: "adc r7, r8, #0xff0000"
+        -
+          asm_text: "adc r7, r8, #-0x7ffffff6"
+        -
+          asm_text: "adc r7, r8, #-0x7ffffff6"
+        -
+          asm_text: "adc r7, r8, #0x28, #2"
+        -
+          asm_text: "adc r7, r8, #0x28, #2"
+        -
+          asm_text: "adc r7, r8, #0x28, #2"
+        -
+          asm_text: "adc r7, r8, #0x28, #2"
+        -
+          asm_text: "adc r1, r2, #0xf0"
+        -
+          asm_text: "adc r1, r2, #0xf00"
+        -
+          asm_text: "adc r1, r2, #0xf000"
+        -
+          asm_text: "adc r1, r2, #0xf0000"
+        -
+          asm_text: "adc r1, r2, #0xf00000"
+        -
+          asm_text: "adc r1, r2, #0xf000000"
+        -
+          asm_text: "adc r1, r2, #-0x10000000"
+        -
+          asm_text: "adc r1, r2, #-0xffffff1"
+        -
+          asm_text: "adcs r1, r2, #0xf00"
+        -
+          asm_text: "adcs r7, r8, #0x28, #2"
+        -
+          asm_text: "adcseq r1, r2, #0xf00"
+        -
+          asm_text: "adceq r1, r2, #0xf00"
+        -
+          asm_text: "adc r4, r5, r6"
+        -
+          asm_text: "adc r4, r5, r6, lsl #1"
+        -
+          asm_text: "adc r4, r5, r6, lsl #0x1f"
+        -
+          asm_text: "adc r4, r5, r6, lsr #1"
+        -
+          asm_text: "adc r4, r5, r6, lsr #0x1f"
+        -
+          asm_text: "adc r4, r5, r6, lsr #0x20"
+        -
+          asm_text: "adc r4, r5, r6, asr #1"
+        -
+          asm_text: "adc r4, r5, r6, asr #0x1f"
+        -
+          asm_text: "adc r4, r5, r6, asr #0x20"
+        -
+          asm_text: "adc r4, r5, r6, ror #1"
+        -
+          asm_text: "adc r4, r5, r6, ror #0x1f"
+        -
+          asm_text: "adc r6, r7, r8, lsl r9"
+        -
+          asm_text: "adc r6, r7, r8, lsr r9"
+        -
+          asm_text: "adc r6, r7, r8, asr r9"
+        -
+          asm_text: "adc r6, r7, r8, ror r9"
+        -
+          asm_text: "adc r4, r5, r6, rrx"
+        -
+          asm_text: "adc r5, r5, r6"
+        -
+          asm_text: "adc r4, r4, r5, lsl #1"
+        -
+          asm_text: "adc r4, r4, r5, lsl #0x1f"
+        -
+          asm_text: "adc r4, r4, r5, lsr #1"
+        -
+          asm_text: "adc r4, r4, r5, lsr #0x1f"
+        -
+          asm_text: "adc r4, r4, r5, lsr #0x20"
+        -
+          asm_text: "adc r4, r4, r5, asr #1"
+        -
+          asm_text: "adc r4, r4, r5, asr #0x1f"
+        -
+          asm_text: "adc r4, r4, r5, asr #0x20"
+        -
+          asm_text: "adc r4, r4, r5, ror #1"
+        -
+          asm_text: "adc r4, r4, r5, ror #0x1f"
+        -
+          asm_text: "adc r4, r4, r5, rrx"
+        -
+          asm_text: "adc r6, r6, r7, lsl r9"
+        -
+          asm_text: "adc r6, r6, r7, lsr r9"
+        -
+          asm_text: "adc r6, r6, r7, asr r9"
+        -
+          asm_text: "adc r6, r6, r7, ror r9"
+        -
+          asm_text: "adc r4, r4, r5, rrx"
+        -
+          asm_text: "add r2, pc, #3"
+        -
+          asm_text: "sub r2, pc, #3"
+        -
+          asm_text: "sub r1, pc, #0"
+        -
+          asm_text: "sub r1, pc, #301989888"
+        -
+          asm_text: "sub r1, pc, #-2147483647"
+        -
+          asm_text: "add r1, pc, #301989888"
+        -
+          asm_text: "add r1, pc, #-2147483647"
+        -
+          asm_text: "add r4, r5, #0xf000"
+        -
+          asm_text: "add r4, r5, #0xf000"
+        -
+          asm_text: "add r4, r5, #0xf000"
+        -
+          asm_text: "sub r4, r5, #0xf000"
+        -
+          asm_text: "add r7, r8, #0xff0000"
+        -
+          asm_text: "add r7, r8, #-0x7ffffff6"
+        -
+          asm_text: "add r7, r8, #-0x7ffffff6"
+        -
+          asm_text: "add r7, r8, #0x28, #2"
+        -
+          asm_text: "add r7, r8, #0x28, #2"
+        -
+          asm_text: "add r7, r8, #0x28, #2"
+        -
+          asm_text: "add r7, r8, #0x28, #2"
+        -
+          asm_text: "add r4, r5, r6"
+        -
+          asm_text: "add r4, r5, r6, lsl #5"
+        -
+          asm_text: "add r4, r5, r6, lsr #5"
+        -
+          asm_text: "add r4, r5, r6, lsr #5"
+        -
+          asm_text: "add r4, r5, r6, asr #5"
+        -
+          asm_text: "add r4, r5, r6, ror #5"
+        -
+          asm_text: "add r6, r7, r8, lsl r9"
+        -
+          asm_text: "add r4, r4, r3, lsl r9"
+        -
+          asm_text: "add r6, r7, r8, lsr r9"
+        -
+          asm_text: "add r6, r7, r8, asr r9"
+        -
+          asm_text: "add r6, r7, r8, ror r9"
+        -
+          asm_text: "add r4, r5, r6, rrx"
+        -
+          asm_text: "add r5, r5, #0xf000"
+        -
+          asm_text: "add r5, r5, #0xf000"
+        -
+          asm_text: "add r5, r5, #0xf000"
+        -
+          asm_text: "sub r5, r5, #0xf000"
+        -
+          asm_text: "add r7, r7, #0xff0000"
+        -
+          asm_text: "add r7, r7, #-0x7ffffff6"
+        -
+          asm_text: "add r7, r7, #-0x7ffffff6"
+        -
+          asm_text: "add r7, r7, #0x28, #2"
+        -
+          asm_text: "add r7, r7, #0x28, #2"
+        -
+          asm_text: "add r7, r7, #0x28, #2"
+        -
+          asm_text: "add r7, r7, #0x28, #2"
+        -
+          asm_text: "add r4, r4, r5"
+        -
+          asm_text: "add r4, r4, r5, lsl #5"
+        -
+          asm_text: "add r4, r4, r5, lsr #5"
+        -
+          asm_text: "add r4, r4, r5, lsr #5"
+        -
+          asm_text: "add r4, r4, r5, asr #5"
+        -
+          asm_text: "add r4, r4, r5, ror #5"
+        -
+          asm_text: "add r6, r6, r7, lsl r9"
+        -
+          asm_text: "add r6, r6, r7, lsr r9"
+        -
+          asm_text: "add r6, r6, r7, asr r9"
+        -
+          asm_text: "add r6, r6, r7, ror r9"
+        -
+          asm_text: "add r4, r4, r5, rrx"
+        -
+          asm_text: "sub r0, r0, #4"
+        -
+          asm_text: "sub r4, r5, #0x15"
+        -
+          asm_text: "add r0, pc, #-1073741824"
+        -
+          asm_text: "addseq r0, pc, #-0x40000000"
+        -
+          asm_text: "add r3, r1, r2, lsr #0x20"
+        -
+          asm_text: "add r3, r1, r2, asr #0x20"
+        -
+          asm_text: "adds r7, r8, #0xff0000"
+        -
+          asm_text: "adds r7, r8, #0xff0000"
+        -
+          asm_text: "adds r7, r8, #0xff0000"
+        -
+          asm_text: "adds r7, r8, #0xff0000"
+        -
+          asm_text: "adds r7, r8, #-0x7ffffff6"
+        -
+          asm_text: "adds r7, r8, #-0x7ffffff6"
+        -
+          asm_text: "adds r7, r8, #0x28, #2"
+        -
+          asm_text: "adds r7, r8, #0x28, #2"
+        -
+          asm_text: "adds r7, r8, #0x28, #2"
+        -
+          asm_text: "adds r7, r8, #0x28, #2"
+        -
+          asm_text: "and r10, r1, #0xf"
+        -
+          asm_text: "and r10, r1, #0xf"
+        -
+          asm_text: "and r10, r1, #0xf"
+        -
+          asm_text: "bic r10, r1, #0xe"
+        -
+          asm_text: "and r7, r8, #0xff0000"
+        -
+          asm_text: "and r7, r8, #-0x7ffffff6"
+        -
+          asm_text: "and r7, r8, #-0x7ffffff6"
+        -
+          asm_text: "and r7, r8, #0x28, #2"
+        -
+          asm_text: "and r7, r8, #0x28, #2"
+        -
+          asm_text: "and r7, r8, #0x28, #2"
+        -
+          asm_text: "and r7, r8, #0x28, #2"
+        -
+          asm_text: "and r10, r1, r6"
+        -
+          asm_text: "and r10, r1, r6, lsl #0xa"
+        -
+          asm_text: "and r10, r1, r6, lsr #0xa"
+        -
+          asm_text: "and r10, r1, r6, lsr #0xa"
+        -
+          asm_text: "and r10, r1, r6, asr #0xa"
+        -
+          asm_text: "and r10, r1, r6, ror #0xa"
+        -
+          asm_text: "and r6, r7, r8, lsl r2"
+        -
+          asm_text: "and r6, r7, r8, lsr r2"
+        -
+          asm_text: "and r6, r7, r8, asr r2"
+        -
+          asm_text: "and r6, r7, r8, ror r2"
+        -
+          asm_text: "and r10, r1, r6, rrx"
+        -
+          asm_text: "bic r2, r3, #-0x80000000"
+        -
+          asm_text: "bic sp, sp, #-0x80000000"
+        -
+          asm_text: "bic pc, pc, #-0x80000000"
+        -
+          asm_text: "and r1, r1, #0xf"
+        -
+          asm_text: "and r1, r1, #0xf"
+        -
+          asm_text: "and r1, r1, #0xf"
+        -
+          asm_text: "bic r1, r1, #0xe"
+        -
+          asm_text: "and r7, r7, #0xff0000"
+        -
+          asm_text: "and r7, r7, #-0x7ffffff6"
+        -
+          asm_text: "and r7, r7, #-0x7ffffff6"
+        -
+          asm_text: "and r7, r7, #0x28, #2"
+        -
+          asm_text: "and r7, r7, #0x28, #2"
+        -
+          asm_text: "and r7, r7, #0x28, #2"
+        -
+          asm_text: "and r7, r7, #0x28, #2"
+        -
+          asm_text: "and r10, r10, r1"
+        -
+          asm_text: "and r10, r10, r1, lsl #0xa"
+        -
+          asm_text: "and r10, r10, r1, lsr #0xa"
+        -
+          asm_text: "and r10, r10, r1, lsr #0xa"
+        -
+          asm_text: "and r10, r10, r1, asr #0xa"
+        -
+          asm_text: "and r10, r10, r1, ror #0xa"
+        -
+          asm_text: "and r6, r6, r7, lsl r2"
+        -
+          asm_text: "and r6, r6, r7, lsr r2"
+        -
+          asm_text: "and r6, r6, r7, asr r2"
+        -
+          asm_text: "and r6, r6, r7, ror r2"
+        -
+          asm_text: "and r10, r10, r1, rrx"
+        -
+          asm_text: "and r3, r1, r2, lsr #0x20"
+        -
+          asm_text: "and r3, r1, r2, asr #0x20"
+        -
+          asm_text: "asr r2, r4, #0x20"
+        -
+          asm_text: "asr r2, r4, #2"
+        -
+          asm_text: "mov r2, r4"
+        -
+          asm_text: "asr r4, r4, #2"
+        -
+          asm_text: "bfc r5, #3, #0x11"
+        -
+          asm_text: "bfclo r5, #3, #0x11"
+        -
+          asm_text: "bfi r5, r2, #3, #0x11"
+        -
+          asm_text: "bfine r5, r2, #3, #0x11"
+        -
+          asm_text: "bic r10, r1, #0xf"
+        -
+          asm_text: "bic r10, r1, #0xf"
+        -
+          asm_text: "bic r10, r1, #0xf"
+        -
+          asm_text: "and r10, r1, #0xe"
+        -
+          asm_text: "bic r7, r8, #0xff0000"
+        -
+          asm_text: "bic r7, r8, #-0x7ffffff6"
+        -
+          asm_text: "bic r7, r8, #-0x7ffffff6"
+        -
+          asm_text: "bic r7, r8, #0x28, #2"
+        -
+          asm_text: "bic r7, r8, #0x28, #2"
+        -
+          asm_text: "bic r7, r8, #0x28, #2"
+        -
+          asm_text: "bic r10, r1, r6"
+        -
+          asm_text: "bic r10, r1, r6, lsl #0xa"
+        -
+          asm_text: "bic r10, r1, r6, lsr #0xa"
+        -
+          asm_text: "bic r10, r1, r6, lsr #0xa"
+        -
+          asm_text: "bic r10, r1, r6, asr #0xa"
+        -
+          asm_text: "bic r10, r1, r6, ror #0xa"
+        -
+          asm_text: "bic r6, r7, r8, lsl r2"
+        -
+          asm_text: "bic r6, r7, r8, lsr r2"
+        -
+          asm_text: "bic r6, r7, r8, asr r2"
+        -
+          asm_text: "bic r6, r7, r8, ror r2"
+        -
+          asm_text: "bic r10, r1, r6, rrx"
+        -
+          asm_text: "and r2, r3, #-0x80000000"
+        -
+          asm_text: "and sp, sp, #-0x80000000"
+        -
+          asm_text: "and pc, pc, #-0x80000000"
+        -
+          asm_text: "bic r1, r1, #0xf"
+        -
+          asm_text: "bic r1, r1, #0xf"
+        -
+          asm_text: "bic r1, r1, #0xf"
+        -
+          asm_text: "and r1, r1, #0xe"
+        -
+          asm_text: "bic r7, r7, #0xff0000"
+        -
+          asm_text: "bic r7, r7, #-0x7ffffff6"
+        -
+          asm_text: "bic r7, r7, #-0x7ffffff6"
+        -
+          asm_text: "bic r7, r7, #0x28, #2"
+        -
+          asm_text: "bic r7, r7, #0x28, #2"
+        -
+          asm_text: "bic r7, r7, #0x28, #2"
+        -
+          asm_text: "bic r7, r7, #0x28, #2"
+        -
+          asm_text: "bic r10, r10, r1"
+        -
+          asm_text: "bic r10, r10, r1, lsl #0xa"
+        -
+          asm_text: "bic r10, r10, r1, lsr #0xa"
+        -
+          asm_text: "bic r10, r10, r1, lsr #0xa"
+        -
+          asm_text: "bic r10, r10, r1, asr #0xa"
+        -
+          asm_text: "bic r10, r10, r1, ror #0xa"
+        -
+          asm_text: "bic r6, r6, r7, lsl r2"
+        -
+          asm_text: "bic r6, r6, r7, lsr r2"
+        -
+          asm_text: "bic r6, r6, r7, asr r2"
+        -
+          asm_text: "bic r6, r6, r7, ror r2"
+        -
+          asm_text: "bic r10, r10, r1, rrx"
+        -
+          asm_text: "bic r3, r1, r2, lsr #0x20"
+        -
+          asm_text: "bic r3, r1, r2, asr #0x20"
+        -
+          asm_text: "bkpt #0xa"
+        -
+          asm_text: "bkpt #0xffff"
+        -
+          asm_text: "blls #0x1b4ec9c"
+        -
+          asm_text: "blx #0x1eec280"
+        -
+          asm_text: "blx #0xf76140"
+        -
+          asm_text: "blx r2"
+        -
+          asm_text: "blxne r2"
+        -
+          asm_text: "bx r2"
+        -
+          asm_text: "bxne r2"
+        -
+          asm_text: "bxj r2"
+        -
+          asm_text: "bxjne r2"
+        -
+          asm_text: "cdp p7, #1, c1, c1, c1, #4"
+        -
+          asm_text: "cdp2 p7, #1, c1, c1, c1, #4"
+        -
+          asm_text: "cdp2 p12, #0, c6, c12, c0, #7"
+        -
+          asm_text: "cdpne p7, #1, c1, c1, c1, #4"
+        -
+          asm_text: "clrex"
+        -
+          asm_text: "clz r1, r2"
+        -
+          asm_text: "clzeq r1, r2"
+        -
+          asm_text: "cmn r1, #0xf"
+        -
+          asm_text: "cmn r1, #0xf"
+        -
+          asm_text: "cmn r1, #0xf"
+        -
+          asm_text: "cmp r1, #0xf"
+        -
+          asm_text: "cmn r7, #0xff0000"
+        -
+          asm_text: "cmn r7, #-0x7ffffff6"
+        -
+          asm_text: "cmn r7, #-0x7ffffff6"
+        -
+          asm_text: "cmn r7, #0x28, #2"
+        -
+          asm_text: "cmn r7, #0x28, #2"
+        -
+          asm_text: "cmn r7, #0x28, #2"
+        -
+          asm_text: "cmn r7, #0x28, #2"
+        -
+          asm_text: "cmn r1, r6"
+        -
+          asm_text: "cmn r1, r6, lsl #0xa"
+        -
+          asm_text: "cmn r1, r6, lsr #0xa"
+        -
+          asm_text: "cmn sp, r6, lsr #0xa"
+        -
+          asm_text: "cmn r1, r6, asr #0xa"
+        -
+          asm_text: "cmn r1, r6, ror #0xa"
+        -
+          asm_text: "cmn r7, r8, lsl r2"
+        -
+          asm_text: "cmn sp, r8, lsr r2"
+        -
+          asm_text: "cmn r7, r8, asr r2"
+        -
+          asm_text: "cmn r7, r8, ror r2"
+        -
+          asm_text: "cmn r1, r6, rrx"
+        -
+          asm_text: "cmp r1, #0xf"
+        -
+          asm_text: "cmp r1, #0xf"
+        -
+          asm_text: "cmp r1, #0xf"
+        -
+          asm_text: "cmn r1, #0xf"
+        -
+          asm_text: "cmp r7, #0xff0000"
+        -
+          asm_text: "cmp r7, #-0x7ffffff6"
+        -
+          asm_text: "cmp r7, #-0x7ffffff6"
+        -
+          asm_text: "cmp r7, #0x28, #2"
+        -
+          asm_text: "cmp r7, #0x28, #2"
+        -
+          asm_text: "cmp r7, #0x28, #2"
+        -
+          asm_text: "cmp r7, #0x28, #2"
+        -
+          asm_text: "cmp r1, r6"
+        -
+          asm_text: "cmp r1, r6, lsl #0xa"
+        -
+          asm_text: "cmp r1, r6, lsr #0xa"
+        -
+          asm_text: "cmp sp, r6, lsr #0xa"
+        -
+          asm_text: "cmp r1, r6, asr #0xa"
+        -
+          asm_text: "cmp r1, r6, ror #0xa"
+        -
+          asm_text: "cmp r7, r8, lsl r2"
+        -
+          asm_text: "cmp sp, r8, lsr r2"
+        -
+          asm_text: "cmp r7, r8, asr r2"
+        -
+          asm_text: "cmp r7, r8, ror r2"
+        -
+          asm_text: "cmp r1, r6, rrx"
+        -
+          asm_text: "cmn r0, #2"
+        -
+          asm_text: "cmp lr, #0"
+        -
+          asm_text: "cpsie aif"
+        -
+          asm_text: "cpsie aif"
+        -
+          asm_text: "cps #0xf"
+        -
+          asm_text: "cpsid if, #0xa"
+        -
+          asm_text: "dbg #0"
+        -
+          asm_text: "dbg #5"
+        -
+          asm_text: "dbg #0xf"
+        -
+          asm_text: "dmb sy"
+        -
+          asm_text: "dmb st"
+        -
+          asm_text: "dmb #0xd"
+        -
+          asm_text: "dmb #0xc"
+        -
+          asm_text: "dmb ish"
+        -
+          asm_text: "dmb ishst"
+        -
+          asm_text: "dmb #0x9"
+        -
+          asm_text: "dmb #0x8"
+        -
+          asm_text: "dmb nsh"
+        -
+          asm_text: "dmb nshst"
+        -
+          asm_text: "dmb #0x5"
+        -
+          asm_text: "dmb #0x4"
+        -
+          asm_text: "dmb osh"
+        -
+          asm_text: "dmb oshst"
+        -
+          asm_text: "dmb #0x1"
+        -
+          asm_text: "dmb #0x0"
+        -
+          asm_text: "dmb sy"
+        -
+          asm_text: "dmb st"
+        -
+          asm_text: "dmb ish"
+        -
+          asm_text: "dmb ish"
+        -
+          asm_text: "dmb ishst"
+        -
+          asm_text: "dmb ishst"
+        -
+          asm_text: "dmb nsh"
+        -
+          asm_text: "dmb nsh"
+        -
+          asm_text: "dmb nshst"
+        -
+          asm_text: "dmb nshst"
+        -
+          asm_text: "dmb osh"
+        -
+          asm_text: "dmb oshst"
+        -
+          asm_text: "dmb sy"
+        -
+          asm_text: "dsb sy"
+        -
+          asm_text: "dsb st"
+        -
+          asm_text: "dsb #0xd"
+        -
+          asm_text: "dsb #0xc"
+        -
+          asm_text: "dsb ish"
+        -
+          asm_text: "dsb ishst"
+        -
+          asm_text: "dsb #0x9"
+        -
+          asm_text: "dsb #0x8"
+        -
+          asm_text: "dsb nsh"
+        -
+          asm_text: "dsb nshst"
+        -
+          asm_text: "dsb #0x5"
+        -
+          asm_text: "pssbb"
+        -
+          asm_text: "dsb osh"
+        -
+          asm_text: "dsb oshst"
+        -
+          asm_text: "dsb #0x1"
+        -
+          asm_text: "ssbb"
+        -
+          asm_text: "dsb #0x8"
+        -
+          asm_text: "dsb nsh"
+        -
+          asm_text: "dsb sy"
+        -
+          asm_text: "dsb st"
+        -
+          asm_text: "dsb ish"
+        -
+          asm_text: "dsb ish"
+        -
+          asm_text: "dsb ishst"
+        -
+          asm_text: "dsb ishst"
+        -
+          asm_text: "dsb nsh"
+        -
+          asm_text: "dsb nsh"
+        -
+          asm_text: "dsb nshst"
+        -
+          asm_text: "dsb nshst"
+        -
+          asm_text: "dsb osh"
+        -
+          asm_text: "dsb oshst"
+        -
+          asm_text: "dsb sy"
+        -
+          asm_text: "dsb sy"
+        -
+          asm_text: "dsb oshst"
+        -
+          asm_text: "eor r4, r5, #0xf000"
+        -
+          asm_text: "eor r4, r5, #0xf000"
+        -
+          asm_text: "eor r4, r5, #0xf000"
+        -
+          asm_text: "eor r7, r8, #0xff0000"
+        -
+          asm_text: "eor r7, r8, #-0x7ffffff6"
+        -
+          asm_text: "eor r7, r8, #-0x7ffffff6"
+        -
+          asm_text: "eor r7, r8, #0x28, #2"
+        -
+          asm_text: "eor r7, r8, #0x28, #2"
+        -
+          asm_text: "eor r7, r8, #0x28, #2"
+        -
+          asm_text: "eor r7, r8, #0x28, #2"
+        -
+          asm_text: "eor r4, r5, r6"
+        -
+          asm_text: "eor r4, r5, r6, lsl #5"
+        -
+          asm_text: "eor r4, r5, r6, lsr #5"
+        -
+          asm_text: "eor r4, r5, r6, lsr #5"
+        -
+          asm_text: "eor r4, r5, r6, asr #5"
+        -
+          asm_text: "eor r4, r5, r6, ror #5"
+        -
+          asm_text: "eor r6, r7, r8, lsl r9"
+        -
+          asm_text: "eor r6, r7, r8, lsr r9"
+        -
+          asm_text: "eor r6, r7, r8, asr r9"
+        -
+          asm_text: "eor r6, r7, r8, ror r9"
+        -
+          asm_text: "eor r4, r5, r6, rrx"
+        -
+          asm_text: "eor r5, r5, #0xf000"
+        -
+          asm_text: "eor r5, r5, #0xf000"
+        -
+          asm_text: "eor r5, r5, #0xf000"
+        -
+          asm_text: "eor r7, r7, #0xff0000"
+        -
+          asm_text: "eor r7, r7, #-0x7ffffff6"
+        -
+          asm_text: "eor r7, r7, #-0x7ffffff6"
+        -
+          asm_text: "eor r7, r7, #0x28, #2"
+        -
+          asm_text: "eor r7, r7, #0x28, #2"
+        -
+          asm_text: "eor r7, r7, #0x28, #2"
+        -
+          asm_text: "eor r7, r7, #0x28, #2"
+        -
+          asm_text: "eor r4, r4, r5"
+        -
+          asm_text: "eor r4, r4, r5, lsl #5"
+        -
+          asm_text: "eor r4, r4, r5, lsr #5"
+        -
+          asm_text: "eor r4, r4, r5, lsr #5"
+        -
+          asm_text: "eor r4, r4, r5, asr #5"
+        -
+          asm_text: "eor r4, r4, r5, ror #5"
+        -
+          asm_text: "eor r6, r6, r7, lsl r9"
+        -
+          asm_text: "eor r6, r6, r7, lsr r9"
+        -
+          asm_text: "eor r6, r6, r7, asr r9"
+        -
+          asm_text: "eor r6, r6, r7, ror r9"
+        -
+          asm_text: "eor r4, r4, r5, rrx"
+        -
+          asm_text: "eor r3, r1, r2, lsr #0x20"
+        -
+          asm_text: "eor r3, r1, r2, asr #0x20"
+        -
+          asm_text: "isb sy"
+        -
+          asm_text: "isb sy"
+        -
+          asm_text: "isb sy"
+        -
+          asm_text: "isb #0x1"
+        -
+          asm_text: "ldc2 p0, c8, [r1, #4]"
+        -
+          asm_text: "ldc2 p1, c7, [r2]"
+        -
+          asm_text: "ldc2 p2, c6, [r3, #-0xe0]"
+        -
+          asm_text: "ldc2 p3, c5, [r4, #-0x78]!"
+        -
+          asm_text: "ldc2 p4, c4, [r5], #0x10"
+        -
+          asm_text: "ldc2 p5, c3, [r6], #-0x48"
+        -
+          asm_text: "ldc2l p6, c2, [r7, #4]"
+        -
+          asm_text: "ldc2l p7, c1, [r8]"
+        -
+          asm_text: "ldc2l p8, c0, [r9, #-0xe0]"
+        -
+          asm_text: "ldc2l p9, c1, [r10, #-0x78]!"
+        -
+          asm_text: "ldc2l p0, c2, [r11], #0x10"
+        -
+          asm_text: "ldc2l p1, c3, [r12], #-0x48"
+        -
+          asm_text: "ldc p12, c4, [r0, #4]"
+        -
+          asm_text: "ldc p13, c5, [r1]"
+        -
+          asm_text: "ldc p14, c6, [r2, #-0xe0]"
+        -
+          asm_text: "ldc p15, c7, [r3, #-0x78]!"
+        -
+          asm_text: "ldc p5, c8, [r4], #0x10"
+        -
+          asm_text: "ldc p4, c9, [r5], #-0x48"
+        -
+          asm_text: "ldcl p3, c10, [r6, #4]"
+        -
+          asm_text: "ldcl p2, c11, [r7]"
+        -
+          asm_text: "ldcl p1, c12, [r8, #-0xe0]"
+        -
+          asm_text: "ldcl p0, c13, [r9, #-0x78]!"
+        -
+          asm_text: "ldcl p6, c14, [r10], #0x10"
+        -
+          asm_text: "ldcl p7, c15, [r11], #-0x48"
+        -
+          asm_text: "ldclo p12, c4, [r0, #4]"
+        -
+          asm_text: "ldchi p13, c5, [r1]"
+        -
+          asm_text: "ldchs p14, c6, [r2, #-0xe0]"
+        -
+          asm_text: "ldclo p15, c7, [r3, #-0x78]!"
+        -
+          asm_text: "ldceq p5, c8, [r4], #0x10"
+        -
+          asm_text: "ldcgt p4, c9, [r5], #-0x48"
+        -
+          asm_text: "ldcllt p3, c10, [r6, #4]"
+        -
+          asm_text: "ldclge p2, c11, [r7]"
+        -
+          asm_text: "ldclle p1, c12, [r8, #-0xe0]"
+        -
+          asm_text: "ldclne p0, c13, [r9, #-0x78]!"
+        -
+          asm_text: "ldcleq p6, c14, [r10], #0x10"
+        -
+          asm_text: "ldclhi p7, c15, [r11], #-0x48"
+        -
+          asm_text: "ldc2 p2, c8, [r1], {25}"
+        -
+          asm_text: "ldm r2, {r1, r3, r4, r5, r6, sp}"
+        -
+          asm_text: "ldm r2, {r1, r3, r4, r5, r6, sp}"
+        -
+          asm_text: "ldmib r2, {r1, r3, r4, r5, r6, sp}"
+        -
+          asm_text: "ldmda r2, {r1, r3, r4, r5, r6, sp}"
+        -
+          asm_text: "ldmdb r2, {r1, r3, r4, r5, r6, sp}"
+        -
+          asm_text: "ldm r2, {r1, r3, r4, r5, r6, sp}"
+        -
+          asm_text: "ldm r2!, {r1, r3, r4, r5, r6, sp}"
+        -
+          asm_text: "ldmib r2!, {r1, r3, r4, r5, r6, sp}"
+        -
+          asm_text: "ldmda r2!, {r1, r3, r4, r5, r6, sp}"
+        -
+          asm_text: "ldmdb r2!, {r1, r3, r4, r5, r6, sp}"
+        -
+          asm_text: "ldm r0, {r0, r2, lr} ^"
+        -
+          asm_text: "ldm sp!, {r0, r1, r2, r3, pc} ^"
+        -
+          asm_text: "ldrexb r3, [r4]"
+        -
+          asm_text: "ldrexh r2, [r5]"
+        -
+          asm_text: "ldrex r1, [r7]"
+        -
+          asm_text: "ldrexd r6, r7, [r8]"
+        -
+          asm_text: "ldrhthi r8, [r11], #-0"
+        -
+          asm_text: "ldrhthi r8, [r11], #0"
+        -
+          asm_text: "lsl r2, r4, #0x1f"
+        -
+          asm_text: "lsl r2, r4, #1"
+        -
+          asm_text: "mov r2, r4"
+        -
+          asm_text: "lsl r4, r4, #1"
+        -
+          asm_text: "lsr r2, r4, #0x20"
+        -
+          asm_text: "lsr r2, r4, #2"
+        -
+          asm_text: "mov r2, r4"
+        -
+          asm_text: "lsr r4, r4, #2"
+        -
+          asm_text: "mcr p7, #1, r5, c1, c1, #4"
+        -
+          asm_text: "mcr2 p7, #1, r5, c1, c1, #4"
+        -
+          asm_text: "mcr p7, #1, r5, c1, c1, #4"
+        -
+          asm_text: "mcr2 p7, #1, r5, c1, c1, #4"
+        -
+          asm_text: "mcrls p7, #1, r5, c1, c1, #4"
+        -
+          asm_text: "mcrls p7, #1, r5, c1, c1, #4"
+        -
+          asm_text: "mcrr p7, #0xf, r5, r4, c1"
+        -
+          asm_text: "mcrr2 p7, #0xf, r5, r4, c1"
+        -
+          asm_text: "mcrr p7, #0xf, r5, r4, c1"
+        -
+          asm_text: "mcrr2 p7, #0xf, r5, r4, c1"
+        -
+          asm_text: "mcrrgt p7, #0xf, r5, r4, c1"
+        -
+          asm_text: "mcrrgt p7, #0xf, r5, r4, c1"
+        -
+          asm_text: "mla r1, r2, r3, r4"
+        -
+          asm_text: "mlas r1, r2, r3, r4"
+        -
+          asm_text: "mlane r1, r2, r3, r4"
+        -
+          asm_text: "mlasne r1, r2, r3, r4"
+        -
+          asm_text: "mls r2, r5, r6, r3"
+        -
+          asm_text: "mlsne r2, r5, r6, r3"
+        -
+          asm_text: "mov r3, #7"
+        -
+          asm_text: "mov r3, #7"
+        -
+          asm_text: "mov r3, #7"
+        -
+          asm_text: "mvn r3, #6"
+        -
+          asm_text: "mov r4, #0xff0"
+        -
+          asm_text: "mov r5, #0xff0000"
+        -
+          asm_text: "mov r7, #0x2a"
+        -
+          asm_text: "mov r7, #0xa800000"
+        -
+          asm_text: "mov r7, #0xff0000"
+        -
+          asm_text: "mov r7, #-0x7ffffff6"
+        -
+          asm_text: "mov r7, #-0x7ffffff6"
+        -
+          asm_text: "mov pc, #0x8000000a"
+        -
+          asm_text: "mov r7, #0, #2"
+        -
+          asm_text: "mov r7, #0x28, #2"
+        -
+          asm_text: "mov r7, #0x28, #2"
+        -
+          asm_text: "mov r7, #0x28, #2"
+        -
+          asm_text: "mov r7, #0x28, #2"
+        -
+          asm_text: "mov r7, #0x2a, #0x1e"
+        -
+          asm_text: "movw r6, #0xffff"
+        -
+          asm_text: "movw r9, #0xffff"
+        -
+          asm_text: "movs r3, #7"
+        -
+          asm_text: "moveq r4, #0xff0"
+        -
+          asm_text: "movseq r5, #0xff0000"
+        -
+          asm_text: "mov r2, r3"
+        -
+          asm_text: "movs r2, r3"
+        -
+          asm_text: "moveq r2, r3"
+        -
+          asm_text: "movseq r2, r3"
+        -
+          asm_text: "mov r12, r8"
+        -
+          asm_text: "mov r2, r3"
+        -
+          asm_text: "mov r12, r8"
+        -
+          asm_text: "mov r2, r3"
+        -
+          asm_text: "mov r12, r8"
+        -
+          asm_text: "mov r2, r3"
+        -
+          asm_text: "mov r12, r8"
+        -
+          asm_text: "mov r2, r3"
+        -
+          asm_text: "movt r3, #7"
+        -
+          asm_text: "movt r6, #0xffff"
+        -
+          asm_text: "movteq r4, #0xff0"
+        -
+          asm_text: "mrc p14, #0, r1, c1, c2, #4"
+        -
+          asm_text: "mrc p15, #7, apsr_nzcv, c15, c6, #6"
+        -
+          asm_text: "mrc2 p14, #0, r1, c1, c2, #4"
+        -
+          asm_text: "mrc2 p9, #7, apsr_nzcv, c15, c0, #1"
+        -
+          asm_text: "mrc p14, #0, r1, c1, c2, #4"
+        -
+          asm_text: "mrc p15, #7, apsr_nzcv, c15, c6, #6"
+        -
+          asm_text: "mrc2 p14, #0, r1, c1, c2, #4"
+        -
+          asm_text: "mrc2 p9, #7, apsr_nzcv, c15, c0, #1"
+        -
+          asm_text: "mrceq p15, #7, apsr_nzcv, c15, c6, #6"
+        -
+          asm_text: "mrceq p15, #7, apsr_nzcv, c15, c6, #6"
+        -
+          asm_text: "mrrc p7, #1, r5, r4, c1"
+        -
+          asm_text: "mrrc2 p7, #1, r5, r4, c1"
+        -
+          asm_text: "mrrc p7, #1, r5, r4, c1"
+        -
+          asm_text: "mrrc2 p7, #1, r5, r4, c1"
+        -
+          asm_text: "mrrclo p7, #1, r5, r4, c1"
+        -
+          asm_text: "mrrclo p7, #1, r5, r4, c1"
+        -
+          asm_text: "mrs r8, apsr"
+        -
+          asm_text: "mrs r8, apsr"
+        -
+          asm_text: "mrs r8, spsr"
+        -
+          asm_text: "msr apsr_nzcvq, #5"
+        -
+          asm_text: "msr apsr_nzcvq, #5"
+        -
+          asm_text: "msr apsr_nzcvq, #5"
+        -
+          asm_text: "msr apsr_g, #5"
+        -
+          asm_text: "msr apsr_nzcvq, #5"
+        -
+          asm_text: "msr apsr_nzcvq, #5"
+        -
+          asm_text: "msr apsr_nzcvqg, #5"
+        -
+          asm_text: "msr cpsr_fc, #5"
+        -
+          asm_text: "msr cpsr_c, #5"
+        -
+          asm_text: "msr cpsr_x, #5"
+        -
+          asm_text: "msr cpsr_fc, #5"
+        -
+          asm_text: "msr cpsr_fc, #5"
+        -
+          asm_text: "msr cpsr_fsx, #5"
+        -
+          asm_text: "msr spsr_fc, #5"
+        -
+          asm_text: "msr spsr_fsxc, #5"
+        -
+          asm_text: "msr cpsr_fsxc, #5"
+        -
+          asm_text: "msr apsr_nzcvqg, #0xff0000"
+        -
+          asm_text: "msr apsr_nzcvq, #0x8000000a"
+        -
+          asm_text: "msr apsr_nzcvqg, #0x8000000a"
+        -
+          asm_text: "msr spsr_fsxc, #0x28, #2"
+        -
+          asm_text: "msr spsr_fsxc, #0x28, #2"
+        -
+          asm_text: "msr spsr_fsxc, #0x28, #2"
+        -
+          asm_text: "msr spsr_fsxc, #0x28, #2"
+        -
+          asm_text: "msr apsr_nzcvq, r0"
+        -
+          asm_text: "msr apsr_g, r0"
+        -
+          asm_text: "msr apsr_nzcvq, r0"
+        -
+          asm_text: "msr apsr_nzcvq, r0"
+        -
+          asm_text: "msr apsr_nzcvqg, r0"
+        -
+          asm_text: "msr cpsr_fc, r0"
+        -
+          asm_text: "msr cpsr_c, r0"
+        -
+          asm_text: "msr cpsr_x, r0"
+        -
+          asm_text: "msr cpsr_fc, r0"
+        -
+          asm_text: "msr cpsr_fc, r0"
+        -
+          asm_text: "msr cpsr_fsx, r0"
+        -
+          asm_text: "msr spsr_fc, r0"
+        -
+          asm_text: "msr spsr_fsxc, r0"
+        -
+          asm_text: "msr cpsr_fsxc, r0"
+        -
+          asm_text: "mul r5, r6, r7"
+        -
+          asm_text: "muls r5, r6, r7"
+        -
+          asm_text: "mulgt r5, r6, r7"
+        -
+          asm_text: "mulsle r5, r6, r7"
+        -
+          asm_text: "mvn r3, #7"
+        -
+          asm_text: "mvn r3, #7"
+        -
+          asm_text: "mvn r3, #7"
+        -
+          asm_text: "mov r3, #6"
+        -
+          asm_text: "mvn r7, #0xff"
+        -
+          asm_text: "mvn r4, #0xff0"
+        -
+          asm_text: "mvn r5, #0xff0000"
+        -
+          asm_text: "mvn r7, #0xff0000"
+        -
+          asm_text: "mvn r7, #-0x7ffffff6"
+        -
+          asm_text: "mvn r7, #-0x7ffffff6"
+        -
+          asm_text: "mvn r7, #0x28, #2"
+        -
+          asm_text: "mvn r7, #0x28, #2"
+        -
+          asm_text: "mvn r7, #0x28, #2"
+        -
+          asm_text: "mvn r7, #0x28, #2"
+        -
+          asm_text: "mvns r3, #7"
+        -
+          asm_text: "mvneq r4, #0xff0"
+        -
+          asm_text: "mvnseq r5, #0xff0000"
+        -
+          asm_text: "mvn r2, r3"
+        -
+          asm_text: "mvns r2, r3"
+        -
+          asm_text: "mvn r5, r6, lsl #0x13"
+        -
+          asm_text: "mvn r5, r6, lsr #0x9"
+        -
+          asm_text: "mvn r5, r6, asr #4"
+        -
+          asm_text: "mvn r5, r6, ror #6"
+        -
+          asm_text: "mvn r5, r6, rrx"
+        -
+          asm_text: "mvneq r2, r3"
+        -
+          asm_text: "mvnseq r2, r3, lsl #0xa"
+        -
+          asm_text: "mvn r5, r6, lsl r7"
+        -
+          asm_text: "mvns r5, r6, lsr r7"
+        -
+          asm_text: "mvngt r5, r6, asr r7"
+        -
+          asm_text: "mvnslt r5, r6, ror r7"
+        -
+          asm_text: "rsb r5, r8, #0"
+        -
+          asm_text: "nop"
+        -
+          asm_text: "nop"
+        -
+          asm_text: "nopgt"
+        -
+          asm_text: "orr r4, r5, #0xf000"
+        -
+          asm_text: "orr r4, r5, #0xf000"
+        -
+          asm_text: "orr r4, r5, #0xf000"
+        -
+          asm_text: "orr r7, r8, #0xff0000"
+        -
+          asm_text: "orr r7, r8, #-0x7ffffff6"
+        -
+          asm_text: "orr r7, r8, #-0x7ffffff6"
+        -
+          asm_text: "orr r7, r8, #0x28, #2"
+        -
+          asm_text: "orr r7, r8, #0x28, #2"
+        -
+          asm_text: "orr r7, r8, #0x28, #2"
+        -
+          asm_text: "orr r7, r8, #0x28, #2"
+        -
+          asm_text: "orr r4, r5, r6"
+        -
+          asm_text: "orr r4, r5, r6, lsl #5"
+        -
+          asm_text: "orr r4, r5, r6, lsr #5"
+        -
+          asm_text: "orr r4, r5, r6, lsr #5"
+        -
+          asm_text: "orr r4, r5, r6, asr #5"
+        -
+          asm_text: "orr r4, r5, r6, ror #5"
+        -
+          asm_text: "orr r6, r7, r8, lsl r9"
+        -
+          asm_text: "orr r6, r7, r8, lsr r9"
+        -
+          asm_text: "orr r6, r7, r8, asr r9"
+        -
+          asm_text: "orr r6, r7, r8, ror r9"
+        -
+          asm_text: "orr r4, r5, r6, rrx"
+        -
+          asm_text: "orr r5, r5, #0xf000"
+        -
+          asm_text: "orr r5, r5, #0xf000"
+        -
+          asm_text: "orr r5, r5, #0xf000"
+        -
+          asm_text: "orr r7, r7, #0xff0000"
+        -
+          asm_text: "orr r7, r7, #-0x7ffffff6"
+        -
+          asm_text: "orr r7, r7, #-0x7ffffff6"
+        -
+          asm_text: "orr r7, r7, #0x28, #2"
+        -
+          asm_text: "orr r7, r7, #0x28, #2"
+        -
+          asm_text: "orr r7, r7, #0x28, #2"
+        -
+          asm_text: "orr r7, r7, #0x28, #2"
+        -
+          asm_text: "orr r4, r4, r5"
+        -
+          asm_text: "orr r4, r4, r5, lsl #5"
+        -
+          asm_text: "orr r4, r4, r5, lsr #5"
+        -
+          asm_text: "orr r4, r4, r5, lsr #5"
+        -
+          asm_text: "orr r4, r4, r5, asr #5"
+        -
+          asm_text: "orr r4, r4, r5, ror #5"
+        -
+          asm_text: "orr r6, r6, r7, lsl r9"
+        -
+          asm_text: "orr r6, r6, r7, lsr r9"
+        -
+          asm_text: "orr r6, r6, r7, asr r9"
+        -
+          asm_text: "orr r6, r6, r7, ror r9"
+        -
+          asm_text: "orr r4, r4, r5, rrx"
+        -
+          asm_text: "orrseq r4, r5, #0xf000"
+        -
+          asm_text: "orrne r4, r5, r6"
+        -
+          asm_text: "orrseq r4, r5, r6, lsl #5"
+        -
+          asm_text: "orrlo r6, r7, r8, ror r9"
+        -
+          asm_text: "orrshi r4, r5, r6, rrx"
+        -
+          asm_text: "orrhs r5, r5, #0xf000"
+        -
+          asm_text: "orrseq r4, r4, r5"
+        -
+          asm_text: "orrne r6, r6, r7, asr r9"
+        -
+          asm_text: "orrslt r6, r6, r7, ror r9"
+        -
+          asm_text: "orrsgt r4, r4, r5, rrx"
+        -
+          asm_text: "orr r3, r1, r2, lsr #0x20"
+        -
+          asm_text: "orr r3, r1, r2, asr #0x20"
+        -
+          asm_text: "pkhbt r2, r2, r3"
+        -
+          asm_text: "pkhbt r2, r2, r3, lsl #0x1f"
+        -
+          asm_text: "pkhbt r2, r2, r3"
+        -
+          asm_text: "pkhbt r2, r2, r3, lsl #0xf"
+        -
+          asm_text: "pkhbt r2, r3, r2"
+        -
+          asm_text: "pkhtb r2, r2, r3, asr #0x1f"
+        -
+          asm_text: "pkhtb r2, r2, r3, asr #0xf"
+        -
+          asm_text: "pop {r7}"
+        -
+          asm_text: "pop {r7, r8, r9, r10}"
+        -
+          asm_text: "str r7, [sp, #-0x4]!"
+        -
+          asm_text: "push {r7, r8, r9, r10}"
+        -
+          asm_text: "qadd r1, r2, r3"
+        -
+          asm_text: "qaddne r1, r2, r3"
+        -
+          asm_text: "qadd16 r1, r2, r3"
+        -
+          asm_text: "qadd16gt r1, r2, r3"
+        -
+          asm_text: "qadd8 r1, r2, r3"
+        -
+          asm_text: "qadd8le r1, r2, r3"
+        -
+          asm_text: "qdadd r6, r7, r8"
+        -
+          asm_text: "qdaddhi r6, r7, r8"
+        -
+          asm_text: "qdsub r6, r7, r8"
+        -
+          asm_text: "qdsubhi r6, r7, r8"
+        -
+          asm_text: "qsax r9, r12, r0"
+        -
+          asm_text: "qsaxeq r9, r12, r0"
+        -
+          asm_text: "qsub r1, r2, r3"
+        -
+          asm_text: "qsubne r1, r2, r3"
+        -
+          asm_text: "qsub16 r1, r2, r3"
+        -
+          asm_text: "qsub16gt r1, r2, r3"
+        -
+          asm_text: "qsub8 r1, r2, r3"
+        -
+          asm_text: "qsub8le r1, r2, r3"
+        -
+          asm_text: "rbit r1, r2"
+        -
+          asm_text: "rbitne r1, r2"
+        -
+          asm_text: "rev r1, r9"
+        -
+          asm_text: "revne r1, r5"
+        -
+          asm_text: "rev16 r8, r3"
+        -
+          asm_text: "rev16ne r12, r4"
+        -
+          asm_text: "revsh r4, r9"
+        -
+          asm_text: "revshne r9, r1"
+        -
+          asm_text: "rfeda r2"
+        -
+          asm_text: "rfedb r3"
+        -
+          asm_text: "rfeia r5"
+        -
+          asm_text: "rfeib r6"
+        -
+          asm_text: "rfeda r4!"
+        -
+          asm_text: "rfedb r7!"
+        -
+          asm_text: "rfeia r9!"
+        -
+          asm_text: "rfeib r8!"
+        -
+          asm_text: "rfeda r2"
+        -
+          asm_text: "rfedb r3"
+        -
+          asm_text: "rfeia r5"
+        -
+          asm_text: "rfeib r6"
+        -
+          asm_text: "rfeda r4!"
+        -
+          asm_text: "rfedb r7!"
+        -
+          asm_text: "rfeia r9!"
+        -
+          asm_text: "rfeib r8!"
+        -
+          asm_text: "rfeia r1"
+        -
+          asm_text: "rfeia r1!"
+        -
+          asm_text: "ror r2, r4, #0x1f"
+        -
+          asm_text: "ror r2, r4, #1"
+        -
+          asm_text: "mov r2, r4"
+        -
+          asm_text: "ror r4, r4, #1"
+        -
+          asm_text: "rsb r4, r5, #0xf000"
+        -
+          asm_text: "rsb r4, r5, #0xf000"
+        -
+          asm_text: "rsb r4, r5, #0xf000"
+        -
+          asm_text: "rsb r7, r8, #0xff0000"
+        -
+          asm_text: "rsb r7, r8, #-0x7ffffff6"
+        -
+          asm_text: "rsb r7, r8, #-0x7ffffff6"
+        -
+          asm_text: "rsb r7, r8, #0x28, #2"
+        -
+          asm_text: "rsb r7, r8, #0x28, #2"
+        -
+          asm_text: "rsb r7, r8, #0x28, #2"
+        -
+          asm_text: "rsb r7, r8, #0x28, #2"
+        -
+          asm_text: "rsb r4, r5, r6"
+        -
+          asm_text: "rsb r4, r5, r6, lsl #5"
+        -
+          asm_text: "rsblo r4, r5, r6, lsr #5"
+        -
+          asm_text: "rsb r4, r5, r6, lsr #5"
+        -
+          asm_text: "rsb r4, r5, r6, asr #5"
+        -
+          asm_text: "rsb r4, r5, r6, ror #5"
+        -
+          asm_text: "rsb r6, r7, r8, lsl r9"
+        -
+          asm_text: "rsb r6, r7, r8, lsr r9"
+        -
+          asm_text: "rsb r6, r7, r8, asr r9"
+        -
+          asm_text: "rsble r6, r7, r8, ror r9"
+        -
+          asm_text: "rsb r4, r5, r6, rrx"
+        -
+          asm_text: "rsb r5, r5, #0xf000"
+        -
+          asm_text: "rsb r5, r5, #0xf000"
+        -
+          asm_text: "rsb r5, r5, #0xf000"
+        -
+          asm_text: "rsb r7, r7, #0xff0000"
+        -
+          asm_text: "rsb r7, r7, #-0x7ffffff6"
+        -
+          asm_text: "rsb r7, r7, #-0x7ffffff6"
+        -
+          asm_text: "rsb r7, r7, #0x28, #2"
+        -
+          asm_text: "rsb r7, r7, #0x28, #2"
+        -
+          asm_text: "rsb r7, r7, #0x28, #2"
+        -
+          asm_text: "rsb r7, r7, #0x28, #2"
+        -
+          asm_text: "rsb r4, r4, r5"
+        -
+          asm_text: "rsb r4, r4, r5, lsl #5"
+        -
+          asm_text: "rsb r4, r4, r5, lsr #5"
+        -
+          asm_text: "rsbne r4, r4, r5, lsr #5"
+        -
+          asm_text: "rsb r4, r4, r5, asr #5"
+        -
+          asm_text: "rsb r4, r4, r5, ror #5"
+        -
+          asm_text: "rsbgt r6, r6, r7, lsl r9"
+        -
+          asm_text: "rsb r6, r6, r7, lsr r9"
+        -
+          asm_text: "rsb r6, r6, r7, asr r9"
+        -
+          asm_text: "rsb r6, r6, r7, ror r9"
+        -
+          asm_text: "rsb r4, r4, r5, rrx"
+        -
+          asm_text: "rsbs r7, r7, #0xff0000"
+        -
+          asm_text: "rsbs r7, r7, #0xff0000"
+        -
+          asm_text: "rsbs r7, r7, #0xff0000"
+        -
+          asm_text: "rsbs r7, r7, #0xff0000"
+        -
+          asm_text: "rsbs r7, r8, #-0x7ffffff6"
+        -
+          asm_text: "rsbs r7, r8, #-0x7ffffff6"
+        -
+          asm_text: "rsbs r7, r8, #0x28, #2"
+        -
+          asm_text: "rsbs r7, r8, #0x28, #2"
+        -
+          asm_text: "rsbs r7, r8, #0x28, #2"
+        -
+          asm_text: "rsbs r7, r8, #0x28, #2"
+        -
+          asm_text: "rsc r4, r5, #0xf000"
+        -
+          asm_text: "rsc r4, r5, #0xf000"
+        -
+          asm_text: "rsc r4, r5, #0xf000"
+        -
+          asm_text: "rsc r7, r8, #0xff0000"
+        -
+          asm_text: "rsc r7, r8, #-0x7ffffff6"
+        -
+          asm_text: "rsc r7, r8, #-0x7ffffff6"
+        -
+          asm_text: "rsc r7, r8, #0x28, #2"
+        -
+          asm_text: "rsc r7, r8, #0x28, #2"
+        -
+          asm_text: "rsc r7, r8, #0x28, #2"
+        -
+          asm_text: "rsc r7, r8, #0x28, #2"
+        -
+          asm_text: "rsc r4, r5, r6"
+        -
+          asm_text: "rsc r4, r5, r6, lsl #5"
+        -
+          asm_text: "rsclo r4, r5, r6, lsr #5"
+        -
+          asm_text: "rsc r4, r5, r6, lsr #5"
+        -
+          asm_text: "rsc r4, r5, r6, asr #5"
+        -
+          asm_text: "rsc r4, r5, r6, ror #5"
+        -
+          asm_text: "rsc r6, r7, r8, lsl r9"
+        -
+          asm_text: "rsc r6, r7, r8, lsr r9"
+        -
+          asm_text: "rsc r6, r7, r8, asr r9"
+        -
+          asm_text: "rscle r6, r7, r8, ror r9"
+        -
+          asm_text: "rscs r1, r8, #0xfe0"
+        -
+          asm_text: "rsc r5, r5, #0xf000"
+        -
+          asm_text: "rsc r5, r5, #0xf000"
+        -
+          asm_text: "rsc r5, r5, #0xf000"
+        -
+          asm_text: "rsc r7, r7, #0xff0000"
+        -
+          asm_text: "rsc r7, r7, #-0x7ffffff6"
+        -
+          asm_text: "rsc r7, r7, #-0x7ffffff6"
+        -
+          asm_text: "rsc r7, r7, #0x28, #2"
+        -
+          asm_text: "rsc r7, r7, #0x28, #2"
+        -
+          asm_text: "rsc r7, r7, #0x28, #2"
+        -
+          asm_text: "rsc r7, r7, #0x28, #2"
+        -
+          asm_text: "rsc r4, r4, r5"
+        -
+          asm_text: "rsc r4, r4, r5, lsl #5"
+        -
+          asm_text: "rsc r4, r4, r5, lsr #5"
+        -
+          asm_text: "rscne r4, r4, r5, lsr #5"
+        -
+          asm_text: "rsc r4, r4, r5, asr #5"
+        -
+          asm_text: "rsc r4, r4, r5, ror #5"
+        -
+          asm_text: "rscgt r6, r6, r7, lsl r9"
+        -
+          asm_text: "rsc r6, r6, r7, lsr r9"
+        -
+          asm_text: "rsc r6, r6, r7, asr r9"
+        -
+          asm_text: "rsc r6, r6, r7, ror r9"
+        -
+          asm_text: "rrx r0, r1"
+        -
+          asm_text: "rrx sp, pc"
+        -
+          asm_text: "rrx pc, lr"
+        -
+          asm_text: "rrx lr, sp"
+        -
+          asm_text: "rrxs r0, r1"
+        -
+          asm_text: "rrxs sp, pc"
+        -
+          asm_text: "rrxs pc, lr"
+        -
+          asm_text: "rrxs lr, sp"
+        -
+          asm_text: "sadd16 r1, r2, r3"
+        -
+          asm_text: "sadd16gt r1, r2, r3"
+        -
+          asm_text: "sadd8 r1, r2, r3"
+        -
+          asm_text: "sadd8le r1, r2, r3"
+        -
+          asm_text: "sasx r9, r12, r0"
+        -
+          asm_text: "sasxeq r9, r12, r0"
+        -
+          asm_text: "sbc r4, r5, #0xf000"
+        -
+          asm_text: "sbc r4, r5, #0xf000"
+        -
+          asm_text: "sbc r4, r5, #0xf000"
+        -
+          asm_text: "sbc r7, r8, #0xff0000"
+        -
+          asm_text: "sbc r7, r8, #-0x7ffffff6"
+        -
+          asm_text: "sbc r7, r8, #-0x7ffffff6"
+        -
+          asm_text: "sbc r7, r8, #0x28, #2"
+        -
+          asm_text: "sbc r7, r8, #0x28, #2"
+        -
+          asm_text: "sbc r7, r8, #0x28, #2"
+        -
+          asm_text: "sbc r7, r8, #0x28, #2"
+        -
+          asm_text: "sbc r4, r5, r6"
+        -
+          asm_text: "sbc r4, r5, r6, lsl #5"
+        -
+          asm_text: "sbc r4, r5, r6, lsr #5"
+        -
+          asm_text: "sbc r4, r5, r6, lsr #5"
+        -
+          asm_text: "sbc r4, r5, r6, asr #5"
+        -
+          asm_text: "sbc r4, r5, r6, ror #5"
+        -
+          asm_text: "sbc r6, r7, r8, lsl r9"
+        -
+          asm_text: "sbc r6, r7, r8, lsr r9"
+        -
+          asm_text: "sbc r6, r7, r8, asr r9"
+        -
+          asm_text: "sbc r6, r7, r8, ror r9"
+        -
+          asm_text: "sbc r5, r5, #0xf000"
+        -
+          asm_text: "sbc r5, r5, #0xf000"
+        -
+          asm_text: "sbc r5, r5, #0xf000"
+        -
+          asm_text: "sbc r7, r7, #0xff0000"
+        -
+          asm_text: "sbc r7, r7, #-0x7ffffff6"
+        -
+          asm_text: "sbc r7, r7, #-0x7ffffff6"
+        -
+          asm_text: "sbc r7, r7, #0x28, #2"
+        -
+          asm_text: "sbc r7, r7, #0x28, #2"
+        -
+          asm_text: "sbc r7, r7, #0x28, #2"
+        -
+          asm_text: "sbc r7, r7, #0x28, #2"
+        -
+          asm_text: "sbc r4, r4, r5"
+        -
+          asm_text: "sbc r4, r4, r5, lsl #5"
+        -
+          asm_text: "sbc r4, r4, r5, lsr #5"
+        -
+          asm_text: "sbc r4, r4, r5, lsr #5"
+        -
+          asm_text: "sbc r4, r4, r5, asr #5"
+        -
+          asm_text: "sbc r4, r4, r5, ror #5"
+        -
+          asm_text: "sbc r6, r6, r7, lsl r9"
+        -
+          asm_text: "sbc r6, r6, r7, lsr r9"
+        -
+          asm_text: "sbc r6, r6, r7, asr r9"
+        -
+          asm_text: "sbc r6, r6, r7, ror r9"
+        -
+          asm_text: "sbfx r4, r5, #0x10, #1"
+        -
+          asm_text: "sbfxgt r4, r5, #0x10, #0x10"
+        -
+          asm_text: "sel r9, r2, r1"
+        -
+          asm_text: "selne r9, r2, r1"
+        -
+          asm_text: "setend be"
+        -
+          asm_text: "setend be"
+        -
+          asm_text: "setend le"
+        -
+          asm_text: "setend le"
+        -
+          asm_text: "sev"
+        -
+          asm_text: "seveq"
+        -
+          asm_text: "shadd16 r4, r8, r2"
+        -
+          asm_text: "shadd16gt r4, r8, r2"
+        -
+          asm_text: "shadd8 r4, r8, r2"
+        -
+          asm_text: "shadd8gt r4, r8, r2"
+        -
+          asm_text: "shasx r4, r8, r2"
+        -
+          asm_text: "shasxgt r4, r8, r2"
+        -
+          asm_text: "shsub16 r4, r8, r2"
+        -
+          asm_text: "shsub16gt r4, r8, r2"
+        -
+          asm_text: "shsub8 r4, r8, r2"
+        -
+          asm_text: "shsub8gt r4, r8, r2"
+        -
+          asm_text: "smlabb r3, r1, r9, r0"
+        -
+          asm_text: "smlabt r5, r6, r4, r1"
+        -
+          asm_text: "smlatb r4, r2, r3, r2"
+        -
+          asm_text: "smlatt r8, r3, r8, r4"
+        -
+          asm_text: "smlabbge r3, r1, r9, r0"
+        -
+          asm_text: "smlabtle r5, r6, r4, r1"
+        -
+          asm_text: "smlatbne r4, r2, r3, r2"
+        -
+          asm_text: "smlatteq r8, r3, r8, r4"
+        -
+          asm_text: "smlad r2, r3, r5, r8"
+        -
+          asm_text: "smladx r2, r3, r5, r8"
+        -
+          asm_text: "smladeq r2, r3, r5, r8"
+        -
+          asm_text: "smladxhi r2, r3, r5, r8"
+        -
+          asm_text: "smlal r2, r3, r5, r8"
+        -
+          asm_text: "smlals r2, r3, r5, r8"
+        -
+          asm_text: "smlaleq r2, r3, r5, r8"
+        -
+          asm_text: "smlalshi r2, r3, r5, r8"
+        -
+          asm_text: "smlalbb r3, r1, r9, r0"
+        -
+          asm_text: "smlalbt r5, r6, r4, r1"
+        -
+          asm_text: "smlaltb r4, r2, r3, r2"
+        -
+          asm_text: "smlaltt r8, r3, r8, r4"
+        -
+          asm_text: "smlalbbge r3, r1, r9, r0"
+        -
+          asm_text: "smlalbtle r5, r6, r4, r1"
+        -
+          asm_text: "smlaltbne r4, r2, r3, r2"
+        -
+          asm_text: "smlaltteq r8, r3, r8, r4"
+        -
+          asm_text: "smlald r2, r3, r5, r8"
+        -
+          asm_text: "smlaldx r2, r3, r5, r8"
+        -
+          asm_text: "smlaldeq r2, r3, r5, r8"
+        -
+          asm_text: "smlaldxhi r2, r3, r5, r8"
+        -
+          asm_text: "smlawb r2, r3, r10, r8"
+        -
+          asm_text: "smlawt r8, r3, r5, r9"
+        -
+          asm_text: "smlawbeq r2, r7, r5, r8"
+        -
+          asm_text: "smlawthi r1, r3, r0, r8"
+        -
+          asm_text: "smlsd r2, r3, r5, r8"
+        -
+          asm_text: "smlsdx r2, r3, r5, r8"
+        -
+          asm_text: "smlsdeq r2, r3, r5, r8"
+        -
+          asm_text: "smlsdxhi r2, r3, r5, r8"
+        -
+          asm_text: "smlsld r2, r9, r5, r1"
+        -
+          asm_text: "smlsldx r4, r11, r2, r8"
+        -
+          asm_text: "smlsldeq r8, r2, r5, r6"
+        -
+          asm_text: "smlsldxhi r1, r0, r3, r8"
+        -
+          asm_text: "smmla r1, r2, r3, r4"
+        -
+          asm_text: "smmlar r4, r3, r2, r1"
+        -
+          asm_text: "smmlalo r1, r2, r3, r4"
+        -
+          asm_text: "smmlarhs r4, r3, r2, r1"
+        -
+          asm_text: "smmls r1, r2, r3, r4"
+        -
+          asm_text: "smmlsr r4, r3, r2, r1"
+        -
+          asm_text: "smmlslo r1, r2, r3, r4"
+        -
+          asm_text: "smmlsrhs r4, r3, r2, r1"
+        -
+          asm_text: "smmul r2, r3, r4"
+        -
+          asm_text: "smmulr r3, r2, r1"
+        -
+          asm_text: "smmullo r2, r3, r4"
+        -
+          asm_text: "smmulrhs r3, r2, r1"
+        -
+          asm_text: "smuad r2, r3, r4"
+        -
+          asm_text: "smuadx r3, r2, r1"
+        -
+          asm_text: "smuadlt r2, r3, r4"
+        -
+          asm_text: "smuadxge r3, r2, r1"
+        -
+          asm_text: "smulbb r3, r9, r0"
+        -
+          asm_text: "smulbt r5, r4, r1"
+        -
+          asm_text: "smultb r4, r2, r2"
+        -
+          asm_text: "smultt r8, r3, r4"
+        -
+          asm_text: "smulbbge r1, r9, r0"
+        -
+          asm_text: "smulbtle r5, r6, r4"
+        -
+          asm_text: "smultbne r2, r3, r2"
+        -
+          asm_text: "smultteq r8, r3, r4"
+        -
+          asm_text: "smull r3, r9, r0, r1"
+        -
+          asm_text: "smulls r3, r9, r0, r2"
+        -
+          asm_text: "smulleq r8, r3, r4, r5"
+        -
+          asm_text: "smullseq r8, r3, r4, r3"
+        -
+          asm_text: "smulwb r3, r9, r0"
+        -
+          asm_text: "smulwt r3, r9, r2"
+        -
+          asm_text: "smusd r3, r0, r1"
+        -
+          asm_text: "smusdx r3, r9, r2"
+        -
+          asm_text: "smusdeq r8, r3, r2"
+        -
+          asm_text: "smusdxne r7, r4, r3"
+        -
+          asm_text: "srsda sp, #5"
+        -
+          asm_text: "srsdb sp, #1"
+        -
+          asm_text: "srsia sp, #0"
+        -
+          asm_text: "srsib sp, #0xf"
+        -
+          asm_text: "srsda sp!, #0x1f"
+        -
+          asm_text: "srsdb sp!, #0x13"
+        -
+          asm_text: "srsia sp!, #2"
+        -
+          asm_text: "srsib sp!, #0xe"
+        -
+          asm_text: "srsib sp, #0xb"
+        -
+          asm_text: "srsia sp, #0xa"
+        -
+          asm_text: "srsdb sp, #0x9"
+        -
+          asm_text: "srsda sp, #5"
+        -
+          asm_text: "srsib sp!, #5"
+        -
+          asm_text: "srsia sp!, #5"
+        -
+          asm_text: "srsdb sp!, #5"
+        -
+          asm_text: "srsda sp!, #5"
+        -
+          asm_text: "srsia sp, #5"
+        -
+          asm_text: "srsia sp!, #5"
+        -
+          asm_text: "srsda sp, #5"
+        -
+          asm_text: "srsdb sp, #1"
+        -
+          asm_text: "srsia sp, #0"
+        -
+          asm_text: "srsib sp, #0xf"
+        -
+          asm_text: "srsda sp!, #0x1f"
+        -
+          asm_text: "srsdb sp!, #0x13"
+        -
+          asm_text: "srsia sp!, #2"
+        -
+          asm_text: "srsib sp!, #0xe"
+        -
+          asm_text: "srsib sp, #0xb"
+        -
+          asm_text: "srsia sp, #0xa"
+        -
+          asm_text: "srsdb sp, #0x9"
+        -
+          asm_text: "srsda sp, #5"
+        -
+          asm_text: "srsib sp!, #5"
+        -
+          asm_text: "srsia sp!, #5"
+        -
+          asm_text: "srsdb sp!, #5"
+        -
+          asm_text: "srsda sp!, #5"
+        -
+          asm_text: "srsia sp, #5"
+        -
+          asm_text: "srsia sp!, #5"
+        -
+          asm_text: "ssat r8, #1, r10"
+        -
+          asm_text: "ssat r8, #1, r10"
+        -
+          asm_text: "ssat r8, #1, r10, lsl #0x1f"
+        -
+          asm_text: "ssat r8, #1, r10, asr #0x20"
+        -
+          asm_text: "ssat r8, #1, r10, asr #1"
+        -
+          asm_text: "ssat16 r2, #1, r7"
+        -
+          asm_text: "ssat16 r3, #0x10, r5"
+        -
+          asm_text: "ssax r2, r3, r4"
+        -
+          asm_text: "ssaxlt r2, r3, r4"
+        -
+          asm_text: "ssub16 r1, r0, r6"
+        -
+          asm_text: "ssub16ne r5, r3, r2"
+        -
+          asm_text: "ssub8 r9, r2, r4"
+        -
+          asm_text: "ssub8eq r5, r1, r2"
+        -
+          asm_text: "stc2 p0, c8, [r1, #4]"
+        -
+          asm_text: "stc2 p1, c7, [r2]"
+        -
+          asm_text: "stc2 p2, c6, [r3, #-0xe0]"
+        -
+          asm_text: "stc2 p3, c5, [r4, #-0x78]!"
+        -
+          asm_text: "stc2 p4, c4, [r5], #0x10"
+        -
+          asm_text: "stc2 p5, c3, [r6], #-0x48"
+        -
+          asm_text: "stc2l p6, c2, [r7, #4]"
+        -
+          asm_text: "stc2l p7, c1, [r8]"
+        -
+          asm_text: "stc2l p8, c0, [r9, #-0xe0]"
+        -
+          asm_text: "stc2l p9, c1, [r10, #-0x78]!"
+        -
+          asm_text: "stc2l p0, c2, [r11], #0x10"
+        -
+          asm_text: "stc2l p1, c3, [r12], #-0x48"
+        -
+          asm_text: "stc p12, c4, [r0, #4]"
+        -
+          asm_text: "stc p13, c5, [r1]"
+        -
+          asm_text: "stc p14, c6, [r2, #-0xe0]"
+        -
+          asm_text: "stc p15, c7, [r3, #-0x78]!"
+        -
+          asm_text: "stc p5, c8, [r4], #0x10"
+        -
+          asm_text: "stc p4, c9, [r5], #-0x48"
+        -
+          asm_text: "stcl p3, c10, [r6, #4]"
+        -
+          asm_text: "stcl p2, c11, [r7]"
+        -
+          asm_text: "stcl p1, c12, [r8, #-0xe0]"
+        -
+          asm_text: "stcl p0, c13, [r9, #-0x78]!"
+        -
+          asm_text: "stcl p6, c14, [r10], #0x10"
+        -
+          asm_text: "stcl p7, c15, [r11], #-0x48"
+        -
+          asm_text: "stclo p12, c4, [r0, #4]"
+        -
+          asm_text: "stchi p13, c5, [r1]"
+        -
+          asm_text: "stchs p14, c6, [r2, #-0xe0]"
+        -
+          asm_text: "stclo p15, c7, [r3, #-0x78]!"
+        -
+          asm_text: "stceq p5, c8, [r4], #0x10"
+        -
+          asm_text: "stcgt p4, c9, [r5], #-0x48"
+        -
+          asm_text: "stcllt p3, c10, [r6, #4]"
+        -
+          asm_text: "stclge p2, c11, [r7]"
+        -
+          asm_text: "stclle p1, c12, [r8, #-0xe0]"
+        -
+          asm_text: "stclne p0, c13, [r9, #-0x78]!"
+        -
+          asm_text: "stcleq p6, c14, [r10], #0x10"
+        -
+          asm_text: "stclhi p7, c15, [r11], #-0x48"
+        -
+          asm_text: "stc2 p2, c8, [r1], {25}"
+        -
+          asm_text: "stm r2, {r1, r3, r4, r5, r6, sp}"
+        -
+          asm_text: "stm r3, {r1, r3, r4, r5, r6, lr}"
+        -
+          asm_text: "stmib r4, {r1, r3, r4, r5, r6, sp}"
+        -
+          asm_text: "stmda r5, {r1, r3, r4, r5, r6, sp}"
+        -
+          asm_text: "stmdb r6, {r1, r3, r4, r5, r6, r8}"
+        -
+          asm_text: "stmdb sp, {r1, r3, r4, r5, r6, sp}"
+        -
+          asm_text: "stm r8!, {r1, r3, r4, r5, r6, sp}"
+        -
+          asm_text: "stmib r9!, {r1, r3, r4, r5, r6, sp}"
+        -
+          asm_text: "stmda sp!, {r1, r3, r4, r5, r6}"
+        -
+          asm_text: "stmdb r0!, {r1, r5, r7, sp}"
+        -
+          asm_text: "strexb r1, r3, [r4]"
+        -
+          asm_text: "strexh r4, r2, [r5]"
+        -
+          asm_text: "strex r2, r1, [r7]"
+        -
+          asm_text: "strexd r6, r2, r3, [r8]"
+        -
+          asm_text: "strpl r3, [r10, #-0]!"
+        -
+          asm_text: "strpl r3, [r10, #0]!"
+        -
+          asm_text: "sub r4, r5, #0xf000"
+        -
+          asm_text: "sub r4, r5, #0xf000"
+        -
+          asm_text: "sub r4, r5, #0xf000"
+        -
+          asm_text: "sub r7, r8, #0xff0000"
+        -
+          asm_text: "sub r7, r8, #-0x7ffffff6"
+        -
+          asm_text: "sub r7, r8, #-0x7ffffff6"
+        -
+          asm_text: "sub r7, r8, #0x28, #2"
+        -
+          asm_text: "sub r7, r8, #0x28, #2"
+        -
+          asm_text: "sub r7, r8, #0x28, #2"
+        -
+          asm_text: "sub r7, r8, #0x28, #2"
+        -
+          asm_text: "sub r4, r5, r6"
+        -
+          asm_text: "sub r4, r5, r6, lsl #5"
+        -
+          asm_text: "sub r4, r5, r6, lsr #5"
+        -
+          asm_text: "sub r4, r5, r6, lsr #5"
+        -
+          asm_text: "sub r4, r5, r6, asr #5"
+        -
+          asm_text: "sub r4, r5, r6, ror #5"
+        -
+          asm_text: "sub r6, r7, r8, lsl r9"
+        -
+          asm_text: "sub r6, r7, r8, lsr r9"
+        -
+          asm_text: "sub r6, r7, r8, asr r9"
+        -
+          asm_text: "sub r6, r7, r8, ror r9"
+        -
+          asm_text: "sub r5, r5, #0xf000"
+        -
+          asm_text: "sub r5, r5, #0xf000"
+        -
+          asm_text: "sub r5, r5, #0xf000"
+        -
+          asm_text: "sub r7, r7, #0xff0000"
+        -
+          asm_text: "sub r7, r7, #-0x7ffffff6"
+        -
+          asm_text: "sub r7, r7, #-0x7ffffff6"
+        -
+          asm_text: "sub r7, r7, #0x28, #2"
+        -
+          asm_text: "sub r7, r7, #0x28, #2"
+        -
+          asm_text: "sub r7, r7, #0x28, #2"
+        -
+          asm_text: "sub r4, r4, r5"
+        -
+          asm_text: "sub r4, r4, r5, lsl #5"
+        -
+          asm_text: "sub r4, r4, r5, lsr #5"
+        -
+          asm_text: "sub r4, r4, r5, lsr #5"
+        -
+          asm_text: "sub r4, r4, r5, asr #5"
+        -
+          asm_text: "sub r4, r4, r5, ror #5"
+        -
+          asm_text: "sub r6, r6, r7, lsl r9"
+        -
+          asm_text: "sub r6, r6, r7, lsr r9"
+        -
+          asm_text: "sub r6, r6, r7, asr r9"
+        -
+          asm_text: "sub r6, r6, r7, ror r9"
+        -
+          asm_text: "sub r3, r1, r2, lsr #0x20"
+        -
+          asm_text: "sub r3, r1, r2, asr #0x20"
+        -
+          asm_text: "subs r7, r8, #0xff0000"
+        -
+          asm_text: "subs r7, r8, #0xff0000"
+        -
+          asm_text: "subs r7, r8, #0xff0000"
+        -
+          asm_text: "subs r7, r8, #0xff0000"
+        -
+          asm_text: "subs r7, r8, #-0x7ffffff6"
+        -
+          asm_text: "subs r7, r8, #-0x7ffffff6"
+        -
+          asm_text: "subs r7, r8, #0x28, #2"
+        -
+          asm_text: "subs r7, r8, #0x28, #2"
+        -
+          asm_text: "subs r7, r8, #0x28, #2"
+        -
+          asm_text: "subs r7, r8, #0x28, #2"
+        -
+          asm_text: "svc #0x10"
+        -
+          asm_text: "svc #0"
+        -
+          asm_text: "svc #0xffffff"
+        -
+          asm_text: "swp r1, r2, [r3]"
+        -
+          asm_text: "swp r4, r4, [r6]"
+        -
+          asm_text: "swpb r5, r1, [r9]"
+        -
+          asm_text: "sxtab r2, r3, r4"
+        -
+          asm_text: "sxtab r4, r5, r6"
+        -
+          asm_text: "sxtablt r6, r2, r9, ror #8"
+        -
+          asm_text: "sxtab r5, r1, r4, ror #0x10"
+        -
+          asm_text: "sxtab r7, r8, r3, ror #0x18"
+        -
+          asm_text: "sxtab16ge r0, r1, r4"
+        -
+          asm_text: "sxtab16 r6, r2, r7"
+        -
+          asm_text: "sxtab16 r3, r5, r8, ror #8"
+        -
+          asm_text: "sxtab16 r3, r2, r1, ror #0x10"
+        -
+          asm_text: "sxtab16eq r1, r2, r3, ror #0x18"
+        -
+          asm_text: "sxtah r1, r3, r9"
+        -
+          asm_text: "sxtahhi r6, r1, r6"
+        -
+          asm_text: "sxtah r3, r8, r3, ror #8"
+        -
+          asm_text: "sxtahlo r2, r2, r4, ror #0x10"
+        -
+          asm_text: "sxtah r9, r3, r3, ror #0x18"
+        -
+          asm_text: "sxtbge r2, r4"
+        -
+          asm_text: "sxtb r5, r6"
+        -
+          asm_text: "sxtb r6, r9, ror #8"
+        -
+          asm_text: "sxtblo r5, r1, ror #0x10"
+        -
+          asm_text: "sxtb r8, r3, ror #0x18"
+        -
+          asm_text: "sxtb16 r1, r4"
+        -
+          asm_text: "sxtb16 r6, r7"
+        -
+          asm_text: "sxtb16hs r3, r5, ror #8"
+        -
+          asm_text: "sxtb16 r3, r1, ror #0x10"
+        -
+          asm_text: "sxtb16ge r2, r3, ror #0x18"
+        -
+          asm_text: "sxthne r3, r9"
+        -
+          asm_text: "sxth r1, r6"
+        -
+          asm_text: "sxth r3, r8, ror #8"
+        -
+          asm_text: "sxthle r2, r2, ror #0x10"
+        -
+          asm_text: "sxth r9, r3, ror #0x18"
+        -
+          asm_text: "teq r5, #0xf000"
+        -
+          asm_text: "teq r5, #0xf000"
+        -
+          asm_text: "teq r5, #0xf000"
+        -
+          asm_text: "teq r7, #0xff0000"
+        -
+          asm_text: "teq r7, #-0x7ffffff6"
+        -
+          asm_text: "teq r7, #-0x7ffffff6"
+        -
+          asm_text: "teq r7, #0x28, #2"
+        -
+          asm_text: "teq r7, #0x28, #2"
+        -
+          asm_text: "teq r7, #0x28, #2"
+        -
+          asm_text: "teq r7, #0x28, #2"
+        -
+          asm_text: "teq r4, r5"
+        -
+          asm_text: "teq r4, r5, lsl #5"
+        -
+          asm_text: "teq r4, r5, lsr #5"
+        -
+          asm_text: "teq r4, r5, lsr #5"
+        -
+          asm_text: "teq r4, r5, asr #5"
+        -
+          asm_text: "teq r4, r5, ror #5"
+        -
+          asm_text: "teq r6, r7, lsl r9"
+        -
+          asm_text: "teq r6, r7, lsr r9"
+        -
+          asm_text: "teq r6, r7, asr r9"
+        -
+          asm_text: "teq r6, r7, ror r9"
+        -
+          asm_text: "tst r5, #0xf000"
+        -
+          asm_text: "tst r5, #0xf000"
+        -
+          asm_text: "tst r5, #0xf000"
+        -
+          asm_text: "tst r7, #0xff0000"
+        -
+          asm_text: "tst r7, #-0x7ffffff6"
+        -
+          asm_text: "tst r7, #-0x7ffffff6"
+        -
+          asm_text: "tst r7, #0x28, #2"
+        -
+          asm_text: "tst r7, #0x28, #2"
+        -
+          asm_text: "tst r7, #0x28, #2"
+        -
+          asm_text: "tst r7, #0x28, #2"
+        -
+          asm_text: "tst r4, r5"
+        -
+          asm_text: "tst r4, r5, lsl #5"
+        -
+          asm_text: "tst r4, r5, lsr #5"
+        -
+          asm_text: "tst r4, r5, lsr #5"
+        -
+          asm_text: "tst r4, r5, asr #5"
+        -
+          asm_text: "tst r4, r5, ror #5"
+        -
+          asm_text: "tst r6, r7, lsl r9"
+        -
+          asm_text: "tst r6, r7, lsr r9"
+        -
+          asm_text: "tst r6, r7, asr r9"
+        -
+          asm_text: "tst r6, r7, ror r9"
+        -
+          asm_text: "uadd16 r1, r2, r3"
+        -
+          asm_text: "uadd16gt r1, r2, r3"
+        -
+          asm_text: "uadd8 r1, r2, r3"
+        -
+          asm_text: "uadd8le r1, r2, r3"
+        -
+          asm_text: "uasx r9, r12, r0"
+        -
+          asm_text: "uasxeq r9, r12, r0"
+        -
+          asm_text: "ubfx r4, r5, #0x10, #1"
+        -
+          asm_text: "ubfxgt r4, r5, #0x10, #0x10"
+        -
+          asm_text: "uhadd16 r4, r8, r2"
+        -
+          asm_text: "uhadd16gt r4, r8, r2"
+        -
+          asm_text: "uhadd8 r4, r8, r2"
+        -
+          asm_text: "uhadd8gt r4, r8, r2"
+        -
+          asm_text: "uhasx r4, r8, r2"
+        -
+          asm_text: "uhasxgt r4, r8, r2"
+        -
+          asm_text: "uhsub16 r4, r8, r2"
+        -
+          asm_text: "uhsub16gt r4, r8, r2"
+        -
+          asm_text: "uhsub8 r4, r8, r2"
+        -
+          asm_text: "uhsub8gt r4, r8, r2"
+        -
+          asm_text: "umaal r3, r4, r5, r6"
+        -
+          asm_text: "umaallt r3, r4, r5, r6"
+        -
+          asm_text: "umlal r2, r4, r6, r8"
+        -
+          asm_text: "umlalgt r6, r1, r2, r6"
+        -
+          asm_text: "umlals r2, r9, r2, r3"
+        -
+          asm_text: "umlalseq r3, r5, r1, r2"
+        -
+          asm_text: "umull r2, r4, r6, r8"
+        -
+          asm_text: "umullgt r6, r1, r2, r6"
+        -
+          asm_text: "umulls r2, r9, r2, r3"
+        -
+          asm_text: "umullseq r3, r5, r1, r2"
+        -
+          asm_text: "uqadd16 r1, r2, r3"
+        -
+          asm_text: "uqadd16gt r4, r7, r9"
+        -
+          asm_text: "uqadd8 r3, r4, r8"
+        -
+          asm_text: "uqadd8le r8, r1, r2"
+        -
+          asm_text: "uqasx r2, r4, r1"
+        -
+          asm_text: "uqasxhi r5, r2, r9"
+        -
+          asm_text: "uqsax r1, r3, r7"
+        -
+          asm_text: "uqsax r3, r6, r2"
+        -
+          asm_text: "uqsub16 r1, r5, r3"
+        -
+          asm_text: "uqsub16gt r3, r2, r5"
+        -
+          asm_text: "uqsub8 r2, r1, r4"
+        -
+          asm_text: "uqsub8le r4, r6, r9"
+        -
+          asm_text: "usad8 r2, r1, r4"
+        -
+          asm_text: "usad8le r4, r6, r9"
+        -
+          asm_text: "usada8 r1, r5, r3, r7"
+        -
+          asm_text: "usada8gt r3, r2, r5, r1"
+        -
+          asm_text: "usat r8, #1, r10"
+        -
+          asm_text: "usat r8, #4, r10"
+        -
+          asm_text: "usat r8, #5, r10, lsl #0x1f"
+        -
+          asm_text: "usat r8, #0x1f, r10, asr #0x20"
+        -
+          asm_text: "usat r8, #0x10, r10, asr #1"
+        -
+          asm_text: "usat16 r2, #2, r7"
+        -
+          asm_text: "usat16 r3, #0xf, r5"
+        -
+          asm_text: "usax r2, r3, r4"
+        -
+          asm_text: "usaxne r2, r3, r4"
+        -
+          asm_text: "usub16 r4, r2, r7"
+        -
+          asm_text: "usub16hi r1, r1, r3"
+        -
+          asm_text: "usub8 r1, r8, r5"
+        -
+          asm_text: "usub8le r9, r2, r3"
+        -
+          asm_text: "uxtab r2, r3, r4"
+        -
+          asm_text: "uxtab r4, r5, r6"
+        -
+          asm_text: "uxtablt r6, r2, r9, ror #8"
+        -
+          asm_text: "uxtab r5, r1, r4, ror #0x10"
+        -
+          asm_text: "uxtab r7, r8, r3, ror #0x18"
+        -
+          asm_text: "uxtab16ge r0, r1, r4"
+        -
+          asm_text: "uxtab16 r6, r2, r7"
+        -
+          asm_text: "uxtab16 r3, r5, r8, ror #8"
+        -
+          asm_text: "uxtab16 r3, r2, r1, ror #0x10"
+        -
+          asm_text: "uxtab16eq r1, r2, r3, ror #0x18"
+        -
+          asm_text: "uxtah r1, r3, r9"
+        -
+          asm_text: "uxtahhi r6, r1, r6"
+        -
+          asm_text: "uxtah r3, r8, r3, ror #8"
+        -
+          asm_text: "uxtahlo r2, r2, r4, ror #0x10"
+        -
+          asm_text: "uxtah r9, r3, r3, ror #0x18"
+        -
+          asm_text: "uxtbge r2, r4"
+        -
+          asm_text: "uxtb r5, r6"
+        -
+          asm_text: "uxtb r6, r9, ror #8"
+        -
+          asm_text: "uxtblo r5, r1, ror #0x10"
+        -
+          asm_text: "uxtb r8, r3, ror #0x18"
+        -
+          asm_text: "uxtb16 r1, r4"
+        -
+          asm_text: "uxtb16 r6, r7"
+        -
+          asm_text: "uxtb16hs r3, r5, ror #8"
+        -
+          asm_text: "uxtb16 r3, r1, ror #0x10"
+        -
+          asm_text: "uxtb16ge r2, r3, ror #0x18"
+        -
+          asm_text: "uxthne r3, r9"
+        -
+          asm_text: "uxth r1, r6"
+        -
+          asm_text: "uxth r3, r8, ror #8"
+        -
+          asm_text: "uxthle r2, r2, ror #0x10"
+        -
+          asm_text: "uxth r9, r3, ror #0x18"
+        -
+          asm_text: "wfe"
+        -
+          asm_text: "wfehi"
+        -
+          asm_text: "wfi"
+        -
+          asm_text: "wfilt"
+        -
+          asm_text: "yield"
+        -
+          asm_text: "yieldne"
+        -
+          asm_text: "sev"
+        -
+          asm_text: "wfi"
+        -
+          asm_text: "wfe"
+        -
+          asm_text: "yield"
+        -
+          asm_text: "nop"
+        -
+          asm_text: "hintgt #0xef"
diff --git a/tests/MC/ARM/basic-thumb-instructions.s.yaml b/tests/MC/ARM/basic-thumb-instructions.s.yaml
new file mode 100644
index 000000000..83e7b0f5c
--- /dev/null
+++ b/tests/MC/ARM/basic-thumb-instructions.s.yaml
@@ -0,0 +1,266 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x74, 0x41, 0xd1, 0x1c, 0x03, 0x32, 0x08, 0x32, 0xd1, 0x18, 0x42, 0x44, 0x01, 0xb0, 0x7f, 0xb0, 0x01, 0xb0, 0x02, 0xaa, 0xff, 0xaa, 0x82, 0xb0, 0x82, 0xb0, 0x9d, 0x44, 0x6a, 0x44, 0x00, 0xa5, 0x01, 0xa2, 0xff, 0xa3, 0x1a, 0x10, 0x5a, 0x11, 0x5a, 0x10, 0x6d, 0x15, 0x6d, 0x15, 0x6b, 0x15, 0x15, 0x41, 0x97, 0xe3, 0x2e, 0xe7, 0x80, 0xd0, 0x50, 0xd0, 0xd8, 0xf0, 0x20, 0xe8, 0xb0, 0xf1, 0x40, 0xe8, 0xb1, 0x43, 0x00, 0xbe, 0xff, 0xbe, 0xa0, 0x47, 0x10, 0x47, 0xcd, 0x42, 0x20, 0x2e, 0xa3, 0x42, 0x88, 0x45, 0x61, 0xb6, 0x74, 0xb6, 0x6c, 0x40, 0xff, 0xcb, 0xba, 0xca, 0x02, 0xc9, 0x29, 0x68, 0x32, 0x6a, 0xfb, 0x6f, 0x00, 0x99, 0x06, 0x9a, 0xff, 0x9b, 0x97, 0x4b, 0x5c, 0x4b, 0xd1, 0x58, 0x1c, 0x78, 0x35, 0x78, 0xfe, 0x7f, 0x66, 0x5d, 0x1b, 0x88, 0x74, 0x88, 0xfd, 0x8f, 0x96, 0x5b, 0x96, 0x57, 0x7b, 0x5e, 0x2c, 0x00, 0x2c, 0x01, 0x1b, 0x03, 0x1b, 0x03, 0x19, 0x03, 0xb2, 0x40, 0x59, 0x08, 0x19, 0x08, 0x24, 0x0d, 0x24, 0x0d, 0x22, 0x0d, 0xf2, 0x40, 0x00, 0x22, 0xff, 0x22, 0x17, 0x22, 0x23, 0x46, 0x19, 0x00, 0x51, 0x43, 0x5a, 0x43, 0x63, 0x43, 0xde, 0x43, 0x63, 0x42, 0x4c, 0xbc, 0x86, 0xb4, 0x1e, 0xba, 0x57, 0xba, 0xcd, 0xba, 0xfa, 0x41, 0x59, 0x42, 0x9c, 0x41, 0x58, 0xb6, 0x50, 0xb6, 0x44, 0xc1, 0x8e, 0xc1, 0x3a, 0x60, 0x3a, 0x60, 0x4d, 0x60, 0xfb, 0x67, 0x00, 0x92, 0x00, 0x93, 0x05, 0x94, 0xff, 0x95, 0xfa, 0x50, 0x1c, 0x70, 0x35, 0x70, 0xfe, 0x77, 0x66, 0x55, 0x1b, 0x80, 0x74, 0x80, 0xfd, 0x87, 0x96, 0x53, 0xd1, 0x1e, 0x03, 0x3a, 0x08, 0x3a, 0x83, 0xb0, 0xff, 0xb0, 0xd1, 0x1a, 0x00, 0xdf, 0xff, 0xdf, 0x6b, 0xb2, 0x2b, 0xb2, 0x0e, 0x42, 0xd7, 0xb2, 0xa1, 0xb2 ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ]
+    expected:
+      insns:
+        -
+          asm_text: "adcs r4, r6"
+        -
+          asm_text: "adds r1, r2, #3"
+        -
+          asm_text: "adds r2, #3"
+        -
+          asm_text: "adds r2, #8"
+        -
+          asm_text: "adds r1, r2, r3"
+        -
+          asm_text: "add r2, r8"
+        -
+          asm_text: "add sp, #4"
+        -
+          asm_text: "add sp, #0x1fc"
+        -
+          asm_text: "add sp, #4"
+        -
+          asm_text: "add r2, sp, #8"
+        -
+          asm_text: "add r2, sp, #0x3fc"
+        -
+          asm_text: "sub sp, #8"
+        -
+          asm_text: "sub sp, #8"
+        -
+          asm_text: "add sp, r3"
+        -
+          asm_text: "add r2, sp, r2"
+        -
+          asm_text: "adr r5, #0"
+        -
+          asm_text: "adr r2, #4"
+        -
+          asm_text: "adr r3, #0x3fc"
+        -
+          asm_text: "asrs r2, r3, #0x20"
+        -
+          asm_text: "asrs r2, r3, #5"
+        -
+          asm_text: "asrs r2, r3, #1"
+        -
+          asm_text: "asrs r5, r5, #0x15"
+        -
+          asm_text: "asrs r5, r5, #0x15"
+        -
+          asm_text: "asrs r3, r5, #0x15"
+        -
+          asm_text: "asrs r5, r2"
+        -
+          asm_text: "b #0x72e"
+        -
+          asm_text: "b #-0x1a4"
+        -
+          asm_text: "beq #-0x100"
+        -
+          asm_text: "beq #0xa0"
+        -
+          asm_text: "blx #0xd8040"
+        -
+          asm_text: "blx #0x1b0080"
+        -
+          asm_text: "bics r1, r6"
+        -
+          asm_text: "bkpt #0"
+        -
+          asm_text: "bkpt #0xff"
+        -
+          asm_text: "blx r4"
+        -
+          asm_text: "bx r2"
+        -
+          asm_text: "cmn r5, r1"
+        -
+          asm_text: "cmp r6, #0x20"
+        -
+          asm_text: "cmp r3, r4"
+        -
+          asm_text: "cmp r8, r1"
+        -
+          asm_text: "cpsie f"
+        -
+          asm_text: "cpsid a"
+        -
+          asm_text: "eors r4, r5"
+        -
+          asm_text: "ldm r3, {r0, r1, r2, r3, r4, r5, r6, r7}"
+        -
+          asm_text: "ldm r2!, {r1, r3, r4, r5, r7}"
+        -
+          asm_text: "ldm r1, {r1}"
+        -
+          asm_text: "ldr r1, [r5]"
+        -
+          asm_text: "ldr r2, [r6, #0x20]"
+        -
+          asm_text: "ldr r3, [r7, #0x7c]"
+        -
+          asm_text: "ldr r1, [sp]"
+        -
+          asm_text: "ldr r2, [sp, #0x18]"
+        -
+          asm_text: "ldr r3, [sp, #0x3fc]"
+        -
+          asm_text: "ldr r3, [pc, #0x25c]"
+        -
+          asm_text: "ldr r3, [pc, #0x170]"
+        -
+          asm_text: "ldr r1, [r2, r3]"
+        -
+          asm_text: "ldrb r4, [r3]"
+        -
+          asm_text: "ldrb r5, [r6]"
+        -
+          asm_text: "ldrb r6, [r7, #0x1f]"
+        -
+          asm_text: "ldrb r6, [r4, r5]"
+        -
+          asm_text: "ldrh r3, [r3]"
+        -
+          asm_text: "ldrh r4, [r6, #2]"
+        -
+          asm_text: "ldrh r5, [r7, #0x3e]"
+        -
+          asm_text: "ldrh r6, [r2, r6]"
+        -
+          asm_text: "ldrsb r6, [r2, r6]"
+        -
+          asm_text: "ldrsh r3, [r7, r1]"
+        -
+          asm_text: "movs r4, r5"
+        -
+          asm_text: "lsls r4, r5, #4"
+        -
+          asm_text: "lsls r3, r3, #0xc"
+        -
+          asm_text: "lsls r3, r3, #0xc"
+        -
+          asm_text: "lsls r1, r3, #0xc"
+        -
+          asm_text: "lsls r2, r6"
+        -
+          asm_text: "lsrs r1, r3, #1"
+        -
+          asm_text: "lsrs r1, r3, #0x20"
+        -
+          asm_text: "lsrs r4, r4, #0x14"
+        -
+          asm_text: "lsrs r4, r4, #0x14"
+        -
+          asm_text: "lsrs r2, r4, #0x14"
+        -
+          asm_text: "lsrs r2, r6"
+        -
+          asm_text: "movs r2, #0"
+        -
+          asm_text: "movs r2, #0xff"
+        -
+          asm_text: "movs r2, #0x17"
+        -
+          asm_text: "mov r3, r4"
+        -
+          asm_text: "movs r1, r3"
+        -
+          asm_text: "muls r1, r2, r1"
+        -
+          asm_text: "muls r2, r3, r2"
+        -
+          asm_text: "muls r3, r4, r3"
+        -
+          asm_text: "mvns r6, r3"
+        -
+          asm_text: "rsbs r3, r4, #0"
+        -
+          asm_text: "pop {r2, r3, r6}"
+        -
+          asm_text: "push {r1, r2, r7}"
+        -
+          asm_text: "rev r6, r3"
+        -
+          asm_text: "rev16 r7, r2"
+        -
+          asm_text: "revsh r5, r1"
+        -
+          asm_text: "rors r2, r7"
+        -
+          asm_text: "rsbs r1, r3, #0"
+        -
+          asm_text: "sbcs r4, r3"
+        -
+          asm_text: "setend be"
+        -
+          asm_text: "setend le"
+        -
+          asm_text: "stm r1!, {r2, r6}"
+        -
+          asm_text: "stm r1!, {r1, r2, r3, r7}"
+        -
+          asm_text: "str r2, [r7]"
+        -
+          asm_text: "str r2, [r7]"
+        -
+          asm_text: "str r5, [r1, #4]"
+        -
+          asm_text: "str r3, [r7, #0x7c]"
+        -
+          asm_text: "str r2, [sp]"
+        -
+          asm_text: "str r3, [sp]"
+        -
+          asm_text: "str r4, [sp, #0x14]"
+        -
+          asm_text: "str r5, [sp, #0x3fc]"
+        -
+          asm_text: "str r2, [r7, r3]"
+        -
+          asm_text: "strb r4, [r3]"
+        -
+          asm_text: "strb r5, [r6]"
+        -
+          asm_text: "strb r6, [r7, #0x1f]"
+        -
+          asm_text: "strb r6, [r4, r5]"
+        -
+          asm_text: "strh r3, [r3]"
+        -
+          asm_text: "strh r4, [r6, #2]"
+        -
+          asm_text: "strh r5, [r7, #0x3e]"
+        -
+          asm_text: "strh r6, [r2, r6]"
+        -
+          asm_text: "subs r1, r2, #3"
+        -
+          asm_text: "subs r2, #3"
+        -
+          asm_text: "subs r2, #8"
+        -
+          asm_text: "sub sp, #0xc"
+        -
+          asm_text: "sub sp, #0x1fc"
+        -
+          asm_text: "subs r1, r2, r3"
+        -
+          asm_text: "svc #0"
+        -
+          asm_text: "svc #0xff"
+        -
+          asm_text: "sxtb r3, r5"
+        -
+          asm_text: "sxth r3, r5"
+        -
+          asm_text: "tst r6, r1"
+        -
+          asm_text: "uxtb r7, r2"
+        -
+          asm_text: "uxth r1, r4"
diff --git a/tests/MC/ARM/basic-thumb2-instructions.s.yaml b/tests/MC/ARM/basic-thumb2-instructions.s.yaml
new file mode 100644
index 000000000..634286b5b
--- /dev/null
+++ b/tests/MC/ARM/basic-thumb2-instructions.s.yaml
@@ -0,0 +1,2688 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x41, 0xf1, 0x04, 0x00, 0x51, 0xf1, 0x00, 0x00, 0x42, 0xf1, 0xff, 0x01, 0x47, 0xf1, 0x55, 0x13, 0x4c, 0xf1, 0xaa, 0x28, 0x47, 0xf1, 0xa5, 0x39, 0x43, 0xf1, 0x07, 0x45, 0x42, 0xf1, 0xff, 0x44, 0x42, 0xf5, 0xd0, 0x64, 0x45, 0xeb, 0x06, 0x04, 0x55, 0xeb, 0x06, 0x04, 0x41, 0xeb, 0x03, 0x09, 0x51, 0xeb, 0x03, 0x09, 0x41, 0xeb, 0x33, 0x10, 0x51, 0xeb, 0xc3, 0x10, 0x41, 0xeb, 0xd3, 0x70, 0x51, 0xeb, 0x23, 0x00, 0x0a, 0xbf, 0x11, 0x1d, 0x03, 0xf2, 0xff, 0x35, 0x05, 0xf2, 0x25, 0x14, 0x0d, 0xf5, 0x80, 0x62, 0x08, 0xf5, 0x7f, 0x42, 0x03, 0xf2, 0x01, 0x12, 0x03, 0xf2, 0x01, 0x12, 0x06, 0xf5, 0x80, 0x7c, 0x06, 0xf2, 0x00, 0x1c, 0x12, 0xf5, 0xf8, 0x71, 0x02, 0xf1, 0x01, 0x02, 0x00, 0xf1, 0x20, 0x00, 0x38, 0x32, 0x38, 0x32, 0x07, 0xf1, 0xcb, 0x31, 0xb2, 0xf1, 0x10, 0x02, 0xb2, 0xf1, 0x10, 0x02, 0xa2, 0xf2, 0x10, 0x02, 0xa2, 0xf2, 0x10, 0x02, 0xa2, 0xf2, 0x10, 0x02, 0x02, 0xeb, 0x08, 0x01, 0x09, 0xeb, 0x22, 0x05, 0x13, 0xeb, 0xc1, 0x77, 0x13, 0xeb, 0x56, 0x60, 0x08, 0xeb, 0x31, 0x34, 0xc9, 0x19, 0x08, 0xbf, 0x59, 0x19, 0x08, 0xbf, 0x49, 0x19, 0x08, 0xbf, 0x13, 0xeb, 0x05, 0x01, 0x08, 0xbf, 0x11, 0xeb, 0x05, 0x01, 0xc2, 0x44, 0xc2, 0x44, 0x08, 0xbf, 0x51, 0x44, 0x08, 0xbf, 0x11, 0xeb, 0x0a, 0x01, 0x08, 0xbf, 0xff, 0xaf, 0x08, 0xbf, 0x7f, 0xb0, 0x0d, 0xf1, 0x0f, 0x07, 0x1d, 0xf1, 0x10, 0x07, 0x0d, 0xf1, 0x10, 0x08, 0x0d, 0xf2, 0xfc, 0x36, 0x0d, 0xf2, 0xfb, 0x36, 0x08, 0xbf, 0xe8, 0x44, 0x08, 0xbf, 0xcd, 0x44, 0x0d, 0xeb, 0x0c, 0x02, 0x08, 0xbf, 0x0d, 0xeb, 0x0c, 0x02, 0xaf, 0xf6, 0xc6, 0x4b, 0x0f, 0xf2, 0x03, 0x02, 0xaf, 0xf2, 0x3a, 0x3b, 0xaf, 0xf2, 0x00, 0x01, 0x05, 0xf4, 0x7f, 0x22, 0x1c, 0xf0, 0x0f, 0x03, 0x01, 0xf0, 0xff, 0x01, 0x01, 0xf0, 0xff, 0x01, 0x04, 0xf0, 0xff, 0x35, 0x19, 0xf0, 0xff, 0x31, 0x09, 0xea, 0x08, 0x04, 0x04, 0xea, 0xe8, 0x01, 0x11, 0xea, 0x47, 0x02, 0x15, 0xea, 0x12, 0x54, 0x0c, 0xea, 0x71, 0x49, 0x4f, 0xea, 0x23, 0x32, 0x5f, 0xea, 0x23, 0x08, 0x5f, 0xea, 0x63, 0x02, 0x4f, 0xea, 0x23, 0x12, 0x5f, 0xea, 0xec, 0x32, 0x4f, 0xea, 0xe3, 0x43, 0x5f, 0xea, 0xa8, 0x08, 0x5f, 0xea, 0x67, 0x17, 0x4f, 0xea, 0x6c, 0x5c, 0x51, 0x10, 0x04, 0xbf, 0x5f, 0xea, 0x62, 0x01, 0x51, 0x10, 0x44, 0xfa, 0x02, 0xf3, 0x41, 0xfa, 0x02, 0xf1, 0x54, 0xfa, 0x08, 0xf3, 0x08, 0xbf, 0x13, 0xf5, 0xce, 0xa9, 0x6f, 0xf3, 0xd3, 0x05, 0x38, 0xbf, 0x6f, 0xf3, 0xd3, 0x05, 0x62, 0xf3, 0xd3, 0x05, 0x18, 0xbf, 0x62, 0xf3, 0xd3, 0x05, 0x21, 0xf0, 0x0f, 0x0a, 0x22, 0xf0, 0xff, 0x35, 0x3a, 0xf0, 0xff, 0x3b, 0x23, 0xea, 0x06, 0x0c, 0x22, 0xea, 0x06, 0x3b, 0x24, 0xea, 0xd1, 0x28, 0x25, 0xea, 0xd7, 0x37, 0x27, 0xea, 0x29, 0x06, 0x26, 0xea, 0x78, 0x05, 0x21, 0xf0, 0x0f, 0x01, 0x21, 0xea, 0x01, 0x01, 0x24, 0xea, 0xc2, 0x74, 0x26, 0xea, 0x13, 0x36, 0x27, 0xea, 0xd4, 0x17, 0x28, 0xea, 0xe5, 0x38, 0x2c, 0xea, 0x76, 0x7c, 0x58, 0xbf, 0xea, 0xbe, 0xc5, 0xf3, 0x00, 0x8f, 0x18, 0xbf, 0xc7, 0xf3, 0x00, 0x8f, 0x1f, 0xb9, 0x37, 0xb9, 0x11, 0xee, 0x81, 0x17, 0x11, 0xfe, 0x81, 0x17, 0xbf, 0xf3, 0x2f, 0x8f, 0x18, 0xbf, 0xbf, 0xf3, 0x2f, 0x8f, 0xb2, 0xfa, 0x82, 0xf1, 0x08, 0xbf, 0xb2, 0xfa, 0x82, 0xf1, 0x11, 0xf1, 0x0f, 0x0f, 0x18, 0xeb, 0x06, 0x0f, 0x11, 0xeb, 0x86, 0x2f, 0x11, 0xeb, 0x96, 0x2f, 0x1d, 0xeb, 0x96, 0x2f, 0x11, 0xeb, 0xa6, 0x2f, 0x11, 0xeb, 0xb6, 0x2f, 0xb5, 0xf5, 0x7f, 0x4f, 0xb4, 0xeb, 0x0c, 0x0f, 0xb9, 0xeb, 0x06, 0x3f, 0xb3, 0xeb, 0xd7, 0x7f, 0xbd, 0xeb, 0x56, 0x0f, 0xb2, 0xeb, 0x25, 0x6f, 0xb1, 0xeb, 0xf4, 0x3f, 0x12, 0xf1, 0x02, 0x0f, 0xb9, 0xf1, 0x01, 0x0f, 0x61, 0xb6, 0x74, 0xb6, 0xaf, 0xf3, 0x20, 0x84, 0xaf, 0xf3, 0x80, 0x86, 0xaf, 0xf3, 0x43, 0x85, 0xaf, 0xf3, 0x43, 0x85, 0xaf, 0xf3, 0x29, 0x87, 0xaf, 0xf3, 0x29, 0x87, 0xaf, 0xf3, 0x00, 0x81, 0xaf, 0xf3, 0x00, 0x81, 0xaf, 0xf3, 0xf5, 0x80, 0xaf, 0xf3, 0xf0, 0x80, 0xaf, 0xf3, 0xff, 0x80, 0xaf, 0xf3, 0xf0, 0x80, 0x18, 0xbf, 0xaf, 0xf3, 0xf0, 0x80, 0xbf, 0xf3, 0x5f, 0x8f, 0xbf, 0xf3, 0x5e, 0x8f, 0xbf, 0xf3, 0x5d, 0x8f, 0xbf, 0xf3, 0x5c, 0x8f, 0xbf, 0xf3, 0x5b, 0x8f, 0xbf, 0xf3, 0x5a, 0x8f, 0xbf, 0xf3, 0x59, 0x8f, 0xbf, 0xf3, 0x58, 0x8f, 0xbf, 0xf3, 0x57, 0x8f, 0xbf, 0xf3, 0x56, 0x8f, 0xbf, 0xf3, 0x55, 0x8f, 0xbf, 0xf3, 0x54, 0x8f, 0xbf, 0xf3, 0x53, 0x8f, 0xbf, 0xf3, 0x52, 0x8f, 0xbf, 0xf3, 0x51, 0x8f, 0xbf, 0xf3, 0x50, 0x8f, 0xbf, 0xf3, 0x5f, 0x8f, 0xbf, 0xf3, 0x5f, 0x8f, 0xbf, 0xf3, 0x5e, 0x8f, 0xbf, 0xf3, 0x5b, 0x8f, 0xbf, 0xf3, 0x5b, 0x8f, 0xbf, 0xf3, 0x5a, 0x8f, 0xbf, 0xf3, 0x5a, 0x8f, 0xbf, 0xf3, 0x57, 0x8f, 0xbf, 0xf3, 0x57, 0x8f, 0xbf, 0xf3, 0x56, 0x8f, 0xbf, 0xf3, 0x56, 0x8f, 0xbf, 0xf3, 0x53, 0x8f, 0xbf, 0xf3, 0x52, 0x8f, 0xbf, 0xf3, 0x5f, 0x8f, 0xbf, 0xf3, 0x5f, 0x8f, 0xbf, 0xf3, 0x4f, 0x8f, 0xbf, 0xf3, 0x4e, 0x8f, 0xbf, 0xf3, 0x4d, 0x8f, 0xbf, 0xf3, 0x4c, 0x8f, 0xbf, 0xf3, 0x4b, 0x8f, 0xbf, 0xf3, 0x4a, 0x8f, 0xbf, 0xf3, 0x49, 0x8f, 0xbf, 0xf3, 0x48, 0x8f, 0xbf, 0xf3, 0x47, 0x8f, 0xbf, 0xf3, 0x46, 0x8f, 0xbf, 0xf3, 0x45, 0x8f, 0xbf, 0xf3, 0x44, 0x8f, 0xbf, 0xf3, 0x43, 0x8f, 0xbf, 0xf3, 0x42, 0x8f, 0xbf, 0xf3, 0x41, 0x8f, 0xbf, 0xf3, 0x40, 0x8f, 0xbf, 0xf3, 0x4f, 0x8f, 0xbf, 0xf3, 0x4f, 0x8f, 0xbf, 0xf3, 0x4e, 0x8f, 0xbf, 0xf3, 0x4b, 0x8f, 0xbf, 0xf3, 0x4b, 0x8f, 0xbf, 0xf3, 0x4a, 0x8f, 0xbf, 0xf3, 0x4a, 0x8f, 0xbf, 0xf3, 0x47, 0x8f, 0xbf, 0xf3, 0x47, 0x8f, 0xbf, 0xf3, 0x46, 0x8f, 0xbf, 0xf3, 0x46, 0x8f, 0xbf, 0xf3, 0x43, 0x8f, 0xbf, 0xf3, 0x42, 0x8f, 0xbf, 0xf3, 0x4f, 0x8f, 0xbf, 0xf3, 0x4f, 0x8f, 0x85, 0xf4, 0x70, 0x44, 0x85, 0xea, 0x06, 0x04, 0x85, 0xea, 0x46, 0x14, 0x85, 0xea, 0x56, 0x14, 0x85, 0xea, 0x56, 0x14, 0x85, 0xea, 0x66, 0x14, 0x85, 0xea, 0x76, 0x14, 0xbf, 0xf3, 0x6f, 0x8f, 0xbf, 0xf3, 0x6f, 0x8f, 0xbf, 0xf3, 0x6f, 0x8f, 0xbf, 0xf3, 0x6f, 0x8f, 0xbf, 0xf3, 0x6f, 0x8f, 0xbf, 0xf3, 0x61, 0x8f, 0x0d, 0xbf, 0x88, 0x18, 0x00, 0xbf, 0xf5, 0x1b, 0x11, 0x1d, 0x0d, 0xbf, 0x88, 0x18, 0x00, 0xbf, 0xf5, 0x1b, 0x11, 0x1d, 0x91, 0xfd, 0x01, 0x80, 0x92, 0xfd, 0x00, 0x71, 0x13, 0xfd, 0x38, 0x62, 0x34, 0xfd, 0x1e, 0x53, 0xb5, 0xfc, 0x04, 0x44, 0x36, 0xfc, 0x12, 0x35, 0xd7, 0xfd, 0x01, 0x26, 0xd8, 0xfd, 0x00, 0x17, 0x59, 0xfd, 0x38, 0x08, 0x7a, 0xfd, 0x1e, 0x19, 0xfb, 0xfc, 0x04, 0x20, 0x7c, 0xfc, 0x12, 0x31, 0x90, 0xed, 0x01, 0x4c, 0x91, 0xed, 0x00, 0x5d, 0x12, 0xed, 0x38, 0x6e, 0x33, 0xed, 0x1e, 0x7f, 0xb4, 0xec, 0x04, 0x85, 0x35, 0xec, 0x12, 0x94, 0xd6, 0xed, 0x01, 0xa3, 0xd7, 0xed, 0x00, 0xb2, 0x58, 0xed, 0x38, 0xc1, 0x79, 0xed, 0x1e, 0xd0, 0xfa, 0xec, 0x04, 0xe6, 0x7b, 0xec, 0x12, 0xf7, 0x91, 0xfc, 0x19, 0x82, 0x94, 0xe8, 0x30, 0x03, 0x94, 0xe8, 0x60, 0x00, 0xb5, 0xe8, 0x08, 0x01, 0x94, 0xe8, 0x30, 0x03, 0x94, 0xe8, 0x60, 0x00, 0xb5, 0xe8, 0x08, 0x01, 0xb5, 0xe8, 0x06, 0x00, 0x92, 0xe8, 0x06, 0x00, 0x94, 0xe8, 0x30, 0x03, 0x94, 0xe8, 0x60, 0x00, 0xb5, 0xe8, 0x08, 0x01, 0x94, 0xe8, 0x30, 0x03, 0x94, 0xe8, 0x60, 0x00, 0xb5, 0xe8, 0x08, 0x01, 0xb5, 0xe8, 0x08, 0x01, 0xbd, 0xe8, 0xf0, 0x8f, 0x14, 0xe9, 0x30, 0x03, 0x14, 0xe9, 0x60, 0x00, 0x35, 0xe9, 0x08, 0x01, 0x35, 0xe9, 0x08, 0x01, 0x14, 0xe9, 0x60, 0x00, 0x35, 0xe9, 0x08, 0x01, 0x55, 0xf8, 0x04, 0x5c, 0x35, 0x6a, 0xd6, 0xf8, 0x21, 0x50, 0xd6, 0xf8, 0x01, 0x51, 0xd7, 0xf8, 0x01, 0xf1, 0x54, 0xf8, 0xff, 0x2f, 0x5d, 0xf8, 0x04, 0x8f, 0x5d, 0xf8, 0x04, 0xed, 0x54, 0xf8, 0xff, 0x2b, 0x5d, 0xf8, 0x04, 0x8b, 0x5d, 0xf8, 0x04, 0xe9, 0x02, 0x4f, 0x02, 0x4f, 0xdf, 0xf8, 0x08, 0x70, 0xff, 0x4c, 0x5f, 0xf8, 0xfc, 0x33, 0xdf, 0xf8, 0x00, 0x64, 0x5f, 0xf8, 0x00, 0x04, 0xdf, 0xf8, 0xff, 0x2f, 0x5f, 0xf8, 0xff, 0x1f, 0xdf, 0xf8, 0x84, 0x80, 0xdf, 0xf8, 0x00, 0xf1, 0x5f, 0xf8, 0x90, 0xf1, 0xdf, 0xf8, 0x04, 0xd0, 0x1f, 0xf8, 0x00, 0x90, 0x1f, 0xf9, 0x00, 0xb0, 0x3f, 0xf8, 0x00, 0xa0, 0x3f, 0xf9, 0x00, 0x10, 0x5f, 0xf8, 0x00, 0x50, 0x58, 0xf8, 0x01, 0x10, 0x55, 0xf8, 0x02, 0x40, 0x50, 0xf8, 0x32, 0x60, 0x58, 0xf8, 0x22, 0x80, 0x5d, 0xf8, 0x12, 0x70, 0x5d, 0xf8, 0x02, 0x70, 0x15, 0xf8, 0x04, 0x5c, 0x96, 0xf8, 0x20, 0x50, 0x96, 0xf8, 0x21, 0x50, 0x96, 0xf8, 0x01, 0x51, 0x97, 0xf8, 0x01, 0xe1, 0x18, 0xf8, 0xff, 0x5f, 0x15, 0xf8, 0x04, 0x2f, 0x14, 0xf8, 0x04, 0x1d, 0x13, 0xf8, 0xff, 0xeb, 0x12, 0xf8, 0x04, 0x9b, 0x1d, 0xf8, 0x04, 0x39, 0x18, 0xf8, 0x01, 0x10, 0x15, 0xf8, 0x02, 0x40, 0x10, 0xf8, 0x32, 0x60, 0x18, 0xf8, 0x22, 0x80, 0x1d, 0xf8, 0x12, 0x70, 0x1d, 0xf8, 0x02, 0x70, 0x12, 0xf8, 0x00, 0x1e, 0x18, 0xf8, 0x00, 0x1e, 0x18, 0xf8, 0x03, 0x1e, 0x18, 0xf8, 0xff, 0x1e, 0xd6, 0xe9, 0x06, 0x35, 0xf6, 0xe9, 0x06, 0x35, 0xf6, 0xe8, 0x01, 0x35, 0x76, 0xe8, 0x02, 0x35, 0xd6, 0xe9, 0x00, 0x35, 0xd3, 0xe9, 0x00, 0x81, 0x52, 0xe9, 0x00, 0x01, 0x72, 0xe9, 0x00, 0x01, 0x72, 0xe8, 0x00, 0x01, 0x54, 0xe8, 0x00, 0x1f, 0x54, 0xe8, 0x00, 0x8f, 0x5d, 0xe8, 0x20, 0x2f, 0xd7, 0xe8, 0x4f, 0x5f, 0xdc, 0xe8, 0x5f, 0x9f, 0xd4, 0xe8, 0x7f, 0x93, 0x35, 0xf8, 0x04, 0x5c, 0x35, 0x8c, 0xb6, 0xf8, 0x21, 0x50, 0xb6, 0xf8, 0x01, 0x51, 0xb7, 0xf8, 0x01, 0xe1, 0x38, 0xf8, 0xff, 0x5f, 0x35, 0xf8, 0x04, 0x2f, 0x34, 0xf8, 0x04, 0x1d, 0x33, 0xf8, 0xff, 0xeb, 0x32, 0xf8, 0x04, 0x9b, 0x3d, 0xf8, 0x04, 0x39, 0x38, 0xf8, 0x01, 0x10, 0x35, 0xf8, 0x02, 0x40, 0x30, 0xf8, 0x32, 0x60, 0x38, 0xf8, 0x22, 0x80, 0x3d, 0xf8, 0x12, 0x70, 0x3d, 0xf8, 0x02, 0x70, 0x32, 0xf8, 0x00, 0x1e, 0x38, 0xf8, 0x00, 0x1e, 0x38, 0xf8, 0x03, 0x1e, 0x38, 0xf8, 0xff, 0x1e, 0x15, 0xf9, 0x04, 0x5c, 0x96, 0xf9, 0x20, 0x50, 0x96, 0xf9, 0x21, 0x50, 0x96, 0xf9, 0x01, 0x51, 0x97, 0xf9, 0x01, 0xe1, 0x18, 0xf9, 0x01, 0x10, 0x15, 0xf9, 0x02, 0x40, 0x10, 0xf9, 0x32, 0x60, 0x18, 0xf9, 0x22, 0x80, 0x1d, 0xf9, 0x12, 0x70, 0x1d, 0xf9, 0x02, 0x70, 0x18, 0xf9, 0xff, 0x5f, 0x15, 0xf9, 0x04, 0x2f, 0x14, 0xf9, 0x04, 0x1d, 0x13, 0xf9, 0xff, 0xeb, 0x12, 0xf9, 0x04, 0x9b, 0x1d, 0xf9, 0x04, 0x39, 0x12, 0xf9, 0x00, 0x1e, 0x18, 0xf9, 0x00, 0x1e, 0x18, 0xf9, 0x03, 0x1e, 0x18, 0xf9, 0xff, 0x1e, 0x35, 0xf9, 0x04, 0x5c, 0xb6, 0xf9, 0x20, 0x50, 0xb6, 0xf9, 0x21, 0x50, 0xb6, 0xf9, 0x01, 0x51, 0xb7, 0xf9, 0x01, 0xe1, 0x38, 0xf9, 0x01, 0x10, 0x35, 0xf9, 0x02, 0x40, 0x30, 0xf9, 0x32, 0x60, 0x38, 0xf9, 0x22, 0x80, 0x3d, 0xf9, 0x12, 0x70, 0x3d, 0xf9, 0x02, 0x70, 0x38, 0xf9, 0xff, 0x5f, 0x35, 0xf9, 0x04, 0x2f, 0x34, 0xf9, 0x04, 0x1d, 0x33, 0xf9, 0xff, 0xeb, 0x32, 0xf9, 0x04, 0x9b, 0x3d, 0xf9, 0x04, 0x39, 0x32, 0xf9, 0x00, 0x1e, 0x38, 0xf9, 0x00, 0x1e, 0x38, 0xf9, 0x03, 0x1e, 0x38, 0xf9, 0xff, 0x1e, 0x52, 0xf8, 0x00, 0x1e, 0x56, 0xf8, 0x00, 0x2e, 0x57, 0xf8, 0x03, 0x3e, 0x59, 0xf8, 0xff, 0x4e, 0x4f, 0xea, 0x03, 0x32, 0x5f, 0xea, 0xc3, 0x78, 0x5f, 0xea, 0x43, 0x02, 0x4f, 0xea, 0x03, 0x12, 0x5f, 0xea, 0xcc, 0x32, 0x4f, 0xea, 0xc3, 0x43, 0x5f, 0xea, 0x88, 0x08, 0x5f, 0xea, 0x47, 0x17, 0x4f, 0xea, 0x4c, 0x5c, 0x51, 0x00, 0x04, 0xbf, 0x5f, 0xea, 0x42, 0x01, 0x51, 0x00, 0x04, 0xfa, 0x02, 0xf3, 0x01, 0xfa, 0x02, 0xf1, 0x14, 0xfa, 0x08, 0xf3, 0x4f, 0xea, 0x13, 0x32, 0x5f, 0xea, 0x13, 0x08, 0x5f, 0xea, 0x53, 0x02, 0x4f, 0xea, 0x13, 0x12, 0x5f, 0xea, 0xdc, 0x32, 0x4f, 0xea, 0xd3, 0x43, 0x5f, 0xea, 0x98, 0x08, 0x5f, 0xea, 0x57, 0x17, 0x4f, 0xea, 0x5c, 0x5c, 0x51, 0x08, 0x04, 0xbf, 0x5f, 0xea, 0x52, 0x01, 0x51, 0x08, 0x24, 0xfa, 0x02, 0xf3, 0x21, 0xfa, 0x02, 0xf1, 0x34, 0xfa, 0x08, 0xf3, 0x21, 0xee, 0x91, 0x57, 0x21, 0xfe, 0x91, 0x57, 0x00, 0xee, 0x15, 0x4e, 0x41, 0xfe, 0x13, 0x24, 0x21, 0xee, 0x91, 0x57, 0x21, 0xfe, 0x91, 0x57, 0x00, 0xee, 0x15, 0x4e, 0x41, 0xfe, 0x13, 0x24, 0x44, 0xec, 0xf1, 0x57, 0x44, 0xfc, 0xf1, 0x57, 0x44, 0xec, 0xf1, 0x57, 0x44, 0xfc, 0xf1, 0x57, 0x02, 0xfb, 0x03, 0x41, 0x02, 0xfb, 0x13, 0x41, 0x15, 0x21, 0x5f, 0xf0, 0x15, 0x01, 0x5f, 0xf0, 0x15, 0x08, 0x4f, 0xf6, 0xff, 0x70, 0x4a, 0xf6, 0x01, 0x31, 0x4a, 0xf6, 0x10, 0x31, 0x4f, 0xf0, 0x7f, 0x70, 0x4f, 0xf0, 0x7f, 0x70, 0x5f, 0xf0, 0x7f, 0x70, 0x06, 0xbf, 0x5f, 0xf0, 0x0c, 0x01, 0x0c, 0x21, 0x4f, 0xf0, 0x0c, 0x01, 0x4f, 0xf4, 0xe1, 0x76, 0x38, 0xbf, 0x4f, 0xf0, 0xff, 0x31, 0x6f, 0xf0, 0x02, 0x03, 0x4a, 0xf6, 0xcd, 0x3b, 0x01, 0x20, 0x18, 0xbf, 0x0f, 0x23, 0x04, 0xbf, 0xff, 0x20, 0x40, 0xf2, 0x00, 0x11, 0x4f, 0xea, 0x02, 0x46, 0x4f, 0xea, 0x02, 0x46, 0x4f, 0xea, 0x12, 0x46, 0x4f, 0xea, 0x12, 0x46, 0x16, 0x10, 0x5f, 0xea, 0x22, 0x06, 0x5f, 0xea, 0x72, 0x16, 0x5f, 0xea, 0x72, 0x16, 0xac, 0x40, 0x14, 0xfa, 0x05, 0xf4, 0xec, 0x40, 0x34, 0xfa, 0x05, 0xf4, 0x2c, 0x41, 0x54, 0xfa, 0x05, 0xf4, 0xec, 0x41, 0x74, 0xfa, 0x05, 0xf4, 0x04, 0xfa, 0x05, 0xf4, 0x74, 0xfa, 0x08, 0xf4, 0x35, 0xfa, 0x06, 0xf4, 0x01, 0xbf, 0xac, 0x40, 0xec, 0x40, 0x2c, 0x41, 0xec, 0x41, 0x4f, 0xea, 0x34, 0x04, 0xc0, 0xf2, 0x07, 0x03, 0xcf, 0xf6, 0xff, 0x76, 0x08, 0xbf, 0xc0, 0xf6, 0xf0, 0x74, 0x11, 0xee, 0x92, 0x1e, 0xff, 0xee, 0xd6, 0xff, 0x32, 0xee, 0x12, 0x19, 0x73, 0xfe, 0x14, 0x3c, 0x11, 0xfe, 0x92, 0x1e, 0xff, 0xfe, 0x30, 0xf8, 0x11, 0xee, 0x92, 0x1e, 0xff, 0xee, 0xd6, 0xff, 0x32, 0xee, 0x12, 0x19, 0x73, 0xfe, 0x14, 0x3c, 0x11, 0xfe, 0x92, 0x1e, 0xff, 0xfe, 0x30, 0xf8, 0x54, 0xec, 0x11, 0x57, 0x54, 0xfc, 0x11, 0x57, 0x54, 0xec, 0x11, 0x57, 0x54, 0xfc, 0x11, 0x57, 0xef, 0xf3, 0x00, 0x88, 0xef, 0xf3, 0x00, 0x88, 0xff, 0xf3, 0x00, 0x88, 0x81, 0xf3, 0x00, 0x88, 0x82, 0xf3, 0x00, 0x84, 0x83, 0xf3, 0x00, 0x88, 0x84, 0xf3, 0x00, 0x88, 0x85, 0xf3, 0x00, 0x8c, 0x86, 0xf3, 0x00, 0x89, 0x87, 0xf3, 0x00, 0x81, 0x88, 0xf3, 0x00, 0x82, 0x89, 0xf3, 0x00, 0x89, 0x8b, 0xf3, 0x00, 0x89, 0x8c, 0xf3, 0x00, 0x8e, 0x90, 0xf3, 0x00, 0x89, 0x95, 0xf3, 0x00, 0x8f, 0x88, 0xf3, 0x00, 0x8f, 0x83, 0xf3, 0x00, 0x89, 0x63, 0x43, 0x04, 0xfb, 0x03, 0xf3, 0x04, 0xfb, 0x06, 0xf3, 0x08, 0xbf, 0x04, 0xfb, 0x05, 0xf3, 0xd8, 0xbf, 0x04, 0xfb, 0x08, 0xf4, 0x06, 0xfb, 0x05, 0xf5, 0x7f, 0xf0, 0x15, 0x08, 0x6f, 0xf0, 0x7f, 0x70, 0x7f, 0xf0, 0x7f, 0x70, 0x06, 0xbf, 0x7f, 0xf0, 0x0c, 0x01, 0x6f, 0xf0, 0x0c, 0x01, 0x6f, 0xf0, 0x0c, 0x01, 0x6f, 0xea, 0x03, 0x02, 0xda, 0x43, 0x6f, 0xea, 0xc6, 0x45, 0x6f, 0xea, 0x56, 0x25, 0x6f, 0xea, 0x26, 0x15, 0x6f, 0xea, 0xb6, 0x15, 0x6f, 0xea, 0x36, 0x05, 0x08, 0xbf, 0xda, 0x43, 0xc2, 0xf1, 0x00, 0x05, 0xc8, 0xf1, 0x00, 0x05, 0xaf, 0xf3, 0x00, 0x80, 0x65, 0xf4, 0x70, 0x44, 0x65, 0xf4, 0x70, 0x44, 0x65, 0xea, 0x06, 0x04, 0x65, 0xea, 0x06, 0x04, 0x75, 0xea, 0x06, 0x04, 0x75, 0xea, 0x06, 0x04, 0x65, 0xea, 0x46, 0x14, 0x65, 0xea, 0x46, 0x14, 0x75, 0xea, 0x56, 0x14, 0x65, 0xea, 0x56, 0x14, 0x75, 0xea, 0x66, 0x14, 0x65, 0xea, 0x76, 0x14, 0x45, 0xf4, 0x70, 0x44, 0x45, 0xea, 0x06, 0x04, 0x45, 0xea, 0x46, 0x14, 0x55, 0xea, 0x56, 0x14, 0x45, 0xea, 0x56, 0x14, 0x55, 0xea, 0x66, 0x14, 0x45, 0xea, 0x76, 0x14, 0xc2, 0xea, 0x03, 0x02, 0xc2, 0xea, 0xc3, 0x72, 0xc2, 0xea, 0x03, 0x02, 0xc2, 0xea, 0xc3, 0x32, 0xc3, 0xea, 0x02, 0x02, 0xc2, 0xea, 0xe3, 0x72, 0xc2, 0xea, 0xe3, 0x32, 0x15, 0xf8, 0x04, 0xfc, 0x96, 0xf8, 0x20, 0xf0, 0x96, 0xf8, 0x21, 0xf0, 0x96, 0xf8, 0x01, 0xf1, 0x97, 0xf8, 0x01, 0xf1, 0x91, 0xf8, 0x00, 0xf0, 0x11, 0xf8, 0x00, 0xfc, 0x11, 0xf8, 0x00, 0xfc, 0x1f, 0xf8, 0xff, 0xff, 0x1f, 0xf8, 0xff, 0xff, 0x18, 0xf8, 0x01, 0xf0, 0x15, 0xf8, 0x02, 0xf0, 0x15, 0xf8, 0x02, 0xf0, 0x10, 0xf8, 0x32, 0xf0, 0x18, 0xf8, 0x22, 0xf0, 0x1d, 0xf8, 0x12, 0xf0, 0x1d, 0xf8, 0x02, 0xf0, 0x1d, 0xf8, 0x12, 0xf0, 0x15, 0xf9, 0x04, 0xfc, 0x96, 0xf9, 0x20, 0xf0, 0x96, 0xf9, 0x21, 0xf0, 0x96, 0xf9, 0x01, 0xf1, 0x97, 0xf9, 0x01, 0xf1, 0x9f, 0xf9, 0xff, 0xff, 0x1f, 0xf9, 0xff, 0xff, 0x1f, 0xf9, 0xff, 0xff, 0x18, 0xf9, 0x01, 0xf0, 0x15, 0xf9, 0x02, 0xf0, 0x15, 0xf9, 0x02, 0xf0, 0x10, 0xf9, 0x32, 0xf0, 0x18, 0xf9, 0x22, 0xf0, 0x1d, 0xf9, 0x12, 0xf0, 0x1d, 0xf9, 0x02, 0xf0, 0x1d, 0xf9, 0x12, 0xf0, 0xbd, 0xe8, 0x04, 0x02, 0x2d, 0xe9, 0x04, 0x02, 0x83, 0xfa, 0x82, 0xf1, 0x92, 0xfa, 0x13, 0xf1, 0x82, 0xfa, 0x13, 0xf1, 0xc6, 0xbf, 0x83, 0xfa, 0x82, 0xf1, 0x92, 0xfa, 0x13, 0xf1, 0x82, 0xfa, 0x13, 0xf1, 0x88, 0xfa, 0x97, 0xf6, 0x88, 0xfa, 0xb7, 0xf6, 0x84, 0xbf, 0x88, 0xfa, 0x97, 0xf6, 0x88, 0xfa, 0xb7, 0xf6, 0xec, 0xfa, 0x10, 0xf9, 0x08, 0xbf, 0xec, 0xfa, 0x10, 0xf9, 0x83, 0xfa, 0xa2, 0xf1, 0xd2, 0xfa, 0x13, 0xf1, 0xc2, 0xfa, 0x13, 0xf1, 0xd6, 0xbf, 0x83, 0xfa, 0xa2, 0xf1, 0xd2, 0xfa, 0x13, 0xf1, 0xc2, 0xfa, 0x13, 0xf1, 0x92, 0xfa, 0xa2, 0xf1, 0x18, 0xbf, 0x92, 0xfa, 0xa2, 0xf1, 0x92, 0xfa, 0x82, 0xf1, 0x98, 0xfa, 0x88, 0xf2, 0x1c, 0xbf, 0x11, 0xba, 0x98, 0xfa, 0x88, 0xf1, 0x92, 0xfa, 0x92, 0xf1, 0x98, 0xfa, 0x98, 0xf2, 0x1c, 0xbf, 0x51, 0xba, 0x98, 0xfa, 0x98, 0xf1, 0x92, 0xfa, 0xb2, 0xf1, 0x98, 0xfa, 0xb8, 0xf2, 0x1c, 0xbf, 0xd1, 0xba, 0x98, 0xfa, 0xb8, 0xf1, 0x4f, 0xea, 0x33, 0x32, 0x5f, 0xea, 0xf3, 0x78, 0x5f, 0xea, 0x73, 0x02, 0x4f, 0xea, 0x33, 0x12, 0x5f, 0xea, 0xfc, 0x32, 0x4f, 0xea, 0xf3, 0x43, 0x5f, 0xea, 0xb8, 0x08, 0x5f, 0xea, 0x77, 0x17, 0x4f, 0xea, 0x7c, 0x5c, 0x64, 0xfa, 0x02, 0xf3, 0x61, 0xfa, 0x02, 0xf1, 0x74, 0xfa, 0x08, 0xf3, 0x4f, 0xea, 0x32, 0x01, 0x5f, 0xea, 0x32, 0x01, 0xb4, 0xbf, 0x4f, 0xea, 0x3c, 0x09, 0x5f, 0xea, 0x33, 0x08, 0xc5, 0xf5, 0x7f, 0x22, 0xdc, 0xf1, 0x0f, 0x03, 0xc1, 0xf1, 0xff, 0x01, 0xc1, 0xf1, 0xff, 0x01, 0xcb, 0xf1, 0x00, 0x0b, 0xc9, 0xf1, 0x00, 0x09, 0x4b, 0x42, 0xc1, 0xf1, 0x00, 0x03, 0xc4, 0xeb, 0x08, 0x04, 0xc4, 0xeb, 0x08, 0x04, 0xc9, 0xeb, 0x08, 0x04, 0xc9, 0xeb, 0x08, 0x04, 0xc4, 0xeb, 0xe8, 0x01, 0xc4, 0xeb, 0xe8, 0x01, 0xd1, 0xeb, 0x47, 0x02, 0xd1, 0xeb, 0x47, 0x02, 0xd1, 0xeb, 0x02, 0x00, 0xd1, 0xeb, 0x02, 0x00, 0x94, 0xfa, 0x08, 0xf3, 0x18, 0xbf, 0x94, 0xfa, 0x08, 0xf3, 0x84, 0xfa, 0x08, 0xf3, 0x18, 0xbf, 0x84, 0xfa, 0x08, 0xf3, 0xa2, 0xfa, 0x07, 0xf9, 0x18, 0xbf, 0xa5, 0xfa, 0x06, 0xf2, 0xa2, 0xfa, 0x07, 0xf9, 0x18, 0xbf, 0xa5, 0xfa, 0x06, 0xf2, 0x61, 0xf1, 0x04, 0x00, 0x71, 0xf1, 0x00, 0x00, 0x62, 0xf1, 0xff, 0x01, 0x67, 0xf1, 0x55, 0x13, 0x6c, 0xf1, 0xaa, 0x28, 0x67, 0xf1, 0xa5, 0x39, 0x63, 0xf1, 0x07, 0x45, 0x62, 0xf1, 0xff, 0x44, 0x62, 0xf5, 0xd0, 0x64, 0x65, 0xeb, 0x06, 0x04, 0x75, 0xeb, 0x06, 0x04, 0x61, 0xeb, 0x03, 0x09, 0x71, 0xeb, 0x03, 0x09, 0x61, 0xeb, 0x33, 0x10, 0x71, 0xeb, 0xc3, 0x10, 0x61, 0xeb, 0xd3, 0x70, 0x71, 0xeb, 0x23, 0x00, 0x45, 0xf3, 0x00, 0x44, 0xc8, 0xbf, 0x45, 0xf3, 0x0f, 0x44, 0xa9, 0xfa, 0x82, 0xf5, 0xd8, 0xbf, 0xa9, 0xfa, 0x82, 0xf5, 0xaf, 0xf3, 0x04, 0x80, 0x08, 0xbf, 0xaf, 0xf3, 0x04, 0x80, 0x92, 0xfa, 0x03, 0xf1, 0x82, 0xfa, 0x03, 0xf1, 0xcc, 0xbf, 0x92, 0xfa, 0x03, 0xf1, 0x82, 0xfa, 0x03, 0xf1, 0xa8, 0xfa, 0x22, 0xf4, 0xc8, 0xbf, 0xa8, 0xfa, 0x22, 0xf4, 0xa8, 0xfa, 0x22, 0xf4, 0xc8, 0xbf, 0xa8, 0xfa, 0x22, 0xf4, 0xe8, 0xfa, 0x22, 0xf4, 0xc8, 0xbf, 0xe8, 0xfa, 0x22, 0xf4, 0xe8, 0xfa, 0x22, 0xf4, 0xc8, 0xbf, 0xe8, 0xfa, 0x22, 0xf4, 0xd8, 0xfa, 0x22, 0xf4, 0xc8, 0xfa, 0x22, 0xf4, 0xc4, 0xbf, 0xd8, 0xfa, 0x22, 0xf4, 0xc8, 0xfa, 0x22, 0xf4, 0x11, 0xfb, 0x09, 0x03, 0x16, 0xfb, 0x14, 0x15, 0x12, 0xfb, 0x23, 0x24, 0x13, 0xfb, 0x38, 0x48, 0xcb, 0xbf, 0x11, 0xfb, 0x09, 0x03, 0x16, 0xfb, 0x14, 0x15, 0x12, 0xfb, 0x23, 0x24, 0x13, 0xfb, 0x38, 0x48, 0x23, 0xfb, 0x05, 0x82, 0x23, 0xfb, 0x15, 0x82, 0x84, 0xbf, 0x23, 0xfb, 0x05, 0x82, 0x23, 0xfb, 0x15, 0x82, 0xc5, 0xfb, 0x08, 0x23, 0x08, 0xbf, 0xc5, 0xfb, 0x08, 0x23, 0xc9, 0xfb, 0x80, 0x31, 0xc4, 0xfb, 0x91, 0x56, 0xc3, 0xfb, 0xa2, 0x42, 0xc8, 0xfb, 0xb4, 0x83, 0xad, 0xbf, 0xc9, 0xfb, 0x80, 0x31, 0xc4, 0xfb, 0x91, 0x56, 0xc3, 0xfb, 0xa2, 0x42, 0xc8, 0xfb, 0xb4, 0x83, 0xc5, 0xfb, 0xc8, 0x23, 0xc5, 0xfb, 0xd8, 0x23, 0x0c, 0xbf, 0xc5, 0xfb, 0xc8, 0x23, 0xc5, 0xfb, 0xd8, 0x23, 0x33, 0xfb, 0x0a, 0x82, 0x33, 0xfb, 0x15, 0x98, 0x0c, 0xbf, 0x37, 0xfb, 0x05, 0x82, 0x33, 0xfb, 0x10, 0x81, 0x43, 0xfb, 0x05, 0x82, 0x43, 0xfb, 0x15, 0x82, 0xd4, 0xbf, 0x43, 0xfb, 0x05, 0x82, 0x43, 0xfb, 0x15, 0x82, 0xd5, 0xfb, 0xc1, 0x29, 0xd2, 0xfb, 0xd8, 0x4b, 0xac, 0xbf, 0xd5, 0xfb, 0xc6, 0x82, 0xd3, 0xfb, 0xd8, 0x10, 0x52, 0xfb, 0x03, 0x41, 0x53, 0xfb, 0x12, 0x14, 0x34, 0xbf, 0x52, 0xfb, 0x03, 0x41, 0x53, 0xfb, 0x12, 0x14, 0x62, 0xfb, 0x03, 0x41, 0x63, 0xfb, 0x12, 0x14, 0x34, 0xbf, 0x62, 0xfb, 0x03, 0x41, 0x63, 0xfb, 0x12, 0x14, 0x53, 0xfb, 0x04, 0xf2, 0x52, 0xfb, 0x11, 0xf3, 0x34, 0xbf, 0x53, 0xfb, 0x04, 0xf2, 0x52, 0xfb, 0x11, 0xf3, 0x23, 0xfb, 0x04, 0xf2, 0x22, 0xfb, 0x11, 0xf3, 0xb4, 0xbf, 0x23, 0xfb, 0x04, 0xf2, 0x22, 0xfb, 0x11, 0xf3, 0x19, 0xfb, 0x00, 0xf3, 0x14, 0xfb, 0x11, 0xf5, 0x12, 0xfb, 0x22, 0xf4, 0x13, 0xfb, 0x34, 0xf8, 0xab, 0xbf, 0x19, 0xfb, 0x00, 0xf1, 0x16, 0xfb, 0x14, 0xf5, 0x13, 0xfb, 0x22, 0xf2, 0x13, 0xfb, 0x34, 0xf8, 0x80, 0xfb, 0x01, 0x39, 0x08, 0xbf, 0x84, 0xfb, 0x05, 0x83, 0x39, 0xfb, 0x00, 0xf3, 0x39, 0xfb, 0x12, 0xf3, 0xcc, 0xbf, 0x39, 0xfb, 0x00, 0xf3, 0x39, 0xfb, 0x12, 0xf3, 0x40, 0xfb, 0x01, 0xf3, 0x49, 0xfb, 0x12, 0xf3, 0x0c, 0xbf, 0x43, 0xfb, 0x02, 0xf8, 0x44, 0xfb, 0x13, 0xf7, 0x0d, 0xe8, 0x01, 0xc0, 0x8d, 0xe9, 0x00, 0xc0, 0x2d, 0xe8, 0x13, 0xc0, 0xad, 0xe9, 0x02, 0xc0, 0x8d, 0xe9, 0x0a, 0xc0, 0x0d, 0xe8, 0x09, 0xc0, 0xad, 0xe9, 0x05, 0xc0, 0x2d, 0xe8, 0x05, 0xc0, 0x8d, 0xe9, 0x05, 0xc0, 0xad, 0xe9, 0x05, 0xc0, 0x0d, 0xe8, 0x01, 0xc0, 0x8d, 0xe9, 0x00, 0xc0, 0x2d, 0xe8, 0x13, 0xc0, 0xad, 0xe9, 0x02, 0xc0, 0x8d, 0xe9, 0x0a, 0xc0, 0x0d, 0xe8, 0x09, 0xc0, 0xad, 0xe9, 0x05, 0xc0, 0x2d, 0xe8, 0x05, 0xc0, 0x8d, 0xe9, 0x05, 0xc0, 0xad, 0xe9, 0x05, 0xc0, 0x0a, 0xf3, 0x00, 0x08, 0x0a, 0xf3, 0x00, 0x08, 0x0a, 0xf3, 0xc0, 0x78, 0x2a, 0xf3, 0x40, 0x08, 0x27, 0xf3, 0x00, 0x02, 0x25, 0xf3, 0x0f, 0x03, 0xe3, 0xfa, 0x04, 0xf2, 0xb8, 0xbf, 0xe3, 0xfa, 0x04, 0xf2, 0xe3, 0xfa, 0x04, 0xf2, 0xb8, 0xbf, 0xe3, 0xfa, 0x04, 0xf2, 0xd0, 0xfa, 0x06, 0xf1, 0xc2, 0xfa, 0x04, 0xf9, 0x14, 0xbf, 0xd3, 0xfa, 0x02, 0xf5, 0xc1, 0xfa, 0x02, 0xf5, 0x81, 0xfd, 0x01, 0x80, 0x82, 0xfd, 0x00, 0x71, 0x03, 0xfd, 0x38, 0x62, 0x24, 0xfd, 0x1e, 0x53, 0xa5, 0xfc, 0x04, 0x44, 0x26, 0xfc, 0x12, 0x35, 0xc7, 0xfd, 0x01, 0x26, 0xc8, 0xfd, 0x00, 0x17, 0x49, 0xfd, 0x38, 0x08, 0x6a, 0xfd, 0x1e, 0x19, 0xeb, 0xfc, 0x04, 0x20, 0x6c, 0xfc, 0x12, 0x31, 0x80, 0xed, 0x01, 0x4c, 0x81, 0xed, 0x00, 0x5d, 0x02, 0xed, 0x38, 0x6e, 0x23, 0xed, 0x1e, 0x7f, 0xa4, 0xec, 0x04, 0x85, 0x25, 0xec, 0x12, 0x94, 0xc6, 0xed, 0x01, 0xa3, 0xc7, 0xed, 0x00, 0xb2, 0x48, 0xed, 0x38, 0xc1, 0x69, 0xed, 0x1e, 0xd0, 0xea, 0xec, 0x04, 0xe6, 0x6b, 0xec, 0x12, 0xf7, 0x81, 0xfc, 0x19, 0x82, 0x84, 0xe8, 0x30, 0x03, 0x84, 0xe8, 0x60, 0x00, 0xa5, 0xe8, 0x08, 0x01, 0x84, 0xe8, 0x30, 0x03, 0x84, 0xe8, 0x60, 0x00, 0xa5, 0xe8, 0x08, 0x01, 0xa5, 0xe8, 0x06, 0x00, 0x82, 0xe8, 0x06, 0x00, 0x84, 0xe8, 0x30, 0x03, 0x84, 0xe8, 0x60, 0x00, 0xa5, 0xe8, 0x08, 0x01, 0x84, 0xe8, 0x30, 0x03, 0x84, 0xe8, 0x60, 0x00, 0xa5, 0xe8, 0x08, 0x01, 0xa5, 0xe8, 0x08, 0x01, 0x04, 0xe9, 0x30, 0x03, 0x04, 0xe9, 0x60, 0x00, 0x25, 0xe9, 0x08, 0x01, 0xa5, 0xe8, 0x08, 0x01, 0x05, 0xe9, 0x03, 0x00, 0x45, 0xf8, 0x04, 0x5c, 0x35, 0x62, 0xc6, 0xf8, 0x21, 0x50, 0xc6, 0xf8, 0x01, 0x51, 0xc7, 0xf8, 0x01, 0xf1, 0x44, 0xf8, 0xff, 0x2f, 0x4d, 0xf8, 0x04, 0x8f, 0x4d, 0xf8, 0x04, 0xed, 0x44, 0xf8, 0xff, 0x2b, 0x4d, 0xf8, 0x04, 0x8b, 0x4d, 0xf8, 0x04, 0xe9, 0x48, 0xf8, 0x01, 0x10, 0x45, 0xf8, 0x02, 0x40, 0x40, 0xf8, 0x32, 0x60, 0x48, 0xf8, 0x22, 0x80, 0x4d, 0xf8, 0x12, 0x70, 0x4d, 0xf8, 0x02, 0x70, 0x05, 0xf8, 0x04, 0x5c, 0x86, 0xf8, 0x20, 0x50, 0x86, 0xf8, 0x21, 0x50, 0x86, 0xf8, 0x01, 0x51, 0x87, 0xf8, 0x01, 0xe1, 0x08, 0xf8, 0xff, 0x5f, 0x05, 0xf8, 0x04, 0x2f, 0x04, 0xf8, 0x04, 0x1d, 0x03, 0xf8, 0xff, 0xeb, 0x02, 0xf8, 0x04, 0x9b, 0x0d, 0xf8, 0x04, 0x39, 0x08, 0xf8, 0x00, 0x4d, 0x00, 0xf8, 0x00, 0x19, 0x08, 0xf8, 0x01, 0x10, 0x05, 0xf8, 0x02, 0x40, 0x00, 0xf8, 0x32, 0x60, 0x08, 0xf8, 0x22, 0x80, 0x0d, 0xf8, 0x12, 0x70, 0x0d, 0xf8, 0x02, 0x70, 0x02, 0xf8, 0x00, 0x1e, 0x08, 0xf8, 0x00, 0x1e, 0x08, 0xf8, 0x03, 0x1e, 0x08, 0xf8, 0xff, 0x1e, 0xc6, 0xe9, 0x06, 0x35, 0xe6, 0xe9, 0x06, 0x35, 0xe6, 0xe8, 0x01, 0x35, 0x66, 0xe8, 0x02, 0x35, 0xc6, 0xe9, 0x00, 0x35, 0xc3, 0xe9, 0x00, 0x81, 0x42, 0xe9, 0x00, 0x01, 0x62, 0xe9, 0x00, 0x01, 0x62, 0xe8, 0x00, 0x01, 0xc2, 0xe9, 0x40, 0x01, 0xe2, 0xe9, 0x40, 0x01, 0xe2, 0xe8, 0x40, 0x01, 0x44, 0xe8, 0x00, 0x81, 0x44, 0xe8, 0x00, 0x28, 0x4d, 0xe8, 0x20, 0xc2, 0xc7, 0xe8, 0x45, 0x1f, 0xcc, 0xe8, 0x59, 0x7f, 0xc4, 0xe8, 0x79, 0x36, 0x25, 0xf8, 0x04, 0x5c, 0x35, 0x84, 0xa6, 0xf8, 0x21, 0x50, 0xa6, 0xf8, 0x01, 0x51, 0xa7, 0xf8, 0x01, 0xe1, 0x28, 0xf8, 0xff, 0x5f, 0x25, 0xf8, 0x04, 0x2f, 0x24, 0xf8, 0x04, 0x1d, 0x23, 0xf8, 0xff, 0xeb, 0x22, 0xf8, 0x04, 0x9b, 0x2d, 0xf8, 0x04, 0x39, 0x28, 0xf8, 0x01, 0x10, 0x25, 0xf8, 0x02, 0x40, 0x20, 0xf8, 0x32, 0x60, 0x28, 0xf8, 0x22, 0x80, 0x2d, 0xf8, 0x12, 0x70, 0x2d, 0xf8, 0x02, 0x70, 0x22, 0xf8, 0x00, 0x1e, 0x28, 0xf8, 0x00, 0x1e, 0x28, 0xf8, 0x03, 0x1e, 0x28, 0xf8, 0xff, 0x1e, 0x42, 0xf8, 0x00, 0x1e, 0x48, 0xf8, 0x00, 0x1e, 0x48, 0xf8, 0x03, 0x1e, 0x48, 0xf8, 0xff, 0x1e, 0x0a, 0xbf, 0x11, 0x1f, 0xa3, 0xf2, 0xff, 0x35, 0xa5, 0xf2, 0x25, 0x14, 0xad, 0xf5, 0x80, 0x62, 0xa8, 0xf5, 0x7f, 0x42, 0xa3, 0xf2, 0x01, 0x12, 0xa3, 0xf2, 0x01, 0x12, 0xa6, 0xf5, 0x80, 0x7c, 0xa6, 0xf2, 0x00, 0x1c, 0xb2, 0xf5, 0xf8, 0x71, 0xa2, 0xf1, 0x01, 0x02, 0xa0, 0xf1, 0x20, 0x00, 0x38, 0x3a, 0x38, 0x3a, 0xa5, 0xeb, 0x06, 0x04, 0xa5, 0xeb, 0x46, 0x14, 0xa5, 0xeb, 0x56, 0x14, 0xa5, 0xeb, 0x56, 0x14, 0xa5, 0xeb, 0x66, 0x14, 0xa5, 0xeb, 0x76, 0x14, 0xa2, 0xeb, 0x3c, 0x05, 0xad, 0xeb, 0x0c, 0x02, 0xad, 0xeb, 0x0c, 0x0d, 0xad, 0xeb, 0x0c, 0x0d, 0xad, 0xeb, 0x0c, 0x02, 0xad, 0xeb, 0x0c, 0x0d, 0xad, 0xeb, 0x0c, 0x0d, 0x00, 0xdf, 0x08, 0xbf, 0xff, 0xdf, 0x18, 0xbf, 0x21, 0xdf, 0x04, 0xbf, 0x00, 0xdf, 0x01, 0xdf, 0x43, 0xfa, 0x84, 0xf2, 0x45, 0xfa, 0x86, 0xf4, 0xb8, 0xbf, 0x42, 0xfa, 0x99, 0xf6, 0x41, 0xfa, 0xa4, 0xf5, 0x48, 0xfa, 0xb3, 0xf7, 0x22, 0xfa, 0x87, 0xf6, 0x25, 0xfa, 0x98, 0xf3, 0x22, 0xfa, 0xa1, 0xf3, 0x14, 0xbf, 0x21, 0xfa, 0x84, 0xf0, 0x22, 0xfa, 0xb3, 0xf1, 0x03, 0xfa, 0x89, 0xf1, 0x08, 0xfa, 0x93, 0xf3, 0x03, 0xfa, 0xb3, 0xf9, 0x8c, 0xbf, 0x01, 0xfa, 0x86, 0xf6, 0x02, 0xfa, 0xa4, 0xf2, 0x75, 0xb2, 0x4f, 0xfa, 0x99, 0xf6, 0x4f, 0xfa, 0xb3, 0xf8, 0xac, 0xbf, 0x62, 0xb2, 0x4f, 0xfa, 0xa1, 0xf5, 0x4f, 0xfa, 0x88, 0xf7, 0x2f, 0xfa, 0x84, 0xf1, 0x2f, 0xfa, 0x87, 0xf6, 0x2f, 0xfa, 0xa1, 0xf3, 0x2c, 0xbf, 0x2f, 0xfa, 0x95, 0xf3, 0x2f, 0xfa, 0xb3, 0xf2, 0x31, 0xb2, 0x0f, 0xfa, 0x98, 0xf3, 0x0f, 0xfa, 0xb3, 0xf9, 0x1c, 0xbf, 0x0f, 0xfa, 0x89, 0xf3, 0x0f, 0xfa, 0xa2, 0xf2, 0x0f, 0xfa, 0x88, 0xf7, 0x75, 0xb2, 0x4f, 0xfa, 0x99, 0xf6, 0x4f, 0xfa, 0xb3, 0xf8, 0xac, 0xbf, 0x62, 0xb2, 0x4f, 0xfa, 0xa1, 0xf5, 0x2f, 0xfa, 0x84, 0xf1, 0x2f, 0xfa, 0x87, 0xf6, 0x2f, 0xfa, 0xa1, 0xf3, 0x2c, 0xbf, 0x2f, 0xfa, 0x95, 0xf3, 0x2f, 0xfa, 0xb3, 0xf2, 0x31, 0xb2, 0x0f, 0xfa, 0x98, 0xf3, 0x0f, 0xfa, 0xb3, 0xf9, 0x1c, 0xbf, 0x0f, 0xfa, 0x89, 0xf3, 0x0f, 0xfa, 0xa2, 0xf2, 0xd3, 0xe8, 0x08, 0xf0, 0xd3, 0xe8, 0x18, 0xf0, 0x08, 0xbf, 0xd3, 0xe8, 0x08, 0xf0, 0x28, 0xbf, 0xd3, 0xe8, 0x18, 0xf0, 0x95, 0xf4, 0x70, 0x4f, 0x94, 0xea, 0x05, 0x0f, 0x94, 0xea, 0x45, 0x1f, 0x94, 0xea, 0x55, 0x1f, 0x94, 0xea, 0x55, 0x1f, 0x94, 0xea, 0x65, 0x1f, 0x94, 0xea, 0x75, 0x1f, 0x15, 0xf4, 0x70, 0x4f, 0x2a, 0x42, 0x13, 0xea, 0x4c, 0x1f, 0x14, 0xea, 0x1b, 0x1f, 0x15, 0xea, 0x1a, 0x3f, 0x16, 0xea, 0xa9, 0x7f, 0x17, 0xea, 0xb8, 0x0f, 0x92, 0xfa, 0x43, 0xf1, 0x82, 0xfa, 0x43, 0xf1, 0xcc, 0xbf, 0x92, 0xfa, 0x43, 0xf1, 0x82, 0xfa, 0x43, 0xf1, 0xac, 0xfa, 0x40, 0xf9, 0x08, 0xbf, 0xac, 0xfa, 0x40, 0xf9, 0xac, 0xfa, 0x40, 0xf9, 0x08, 0xbf, 0xac, 0xfa, 0x40, 0xf9, 0xc5, 0xf3, 0x00, 0x44, 0xc8, 0xbf, 0xc5, 0xf3, 0x0f, 0x44, 0x98, 0xfa, 0x62, 0xf4, 0x88, 0xfa, 0x62, 0xf4, 0xc4, 0xbf, 0x98, 0xfa, 0x62, 0xf4, 0x88, 0xfa, 0x62, 0xf4, 0xa1, 0xfa, 0x65, 0xf4, 0xe6, 0xfa, 0x66, 0xf5, 0xc4, 0xbf, 0xa9, 0xfa, 0x68, 0xf6, 0xe8, 0xfa, 0x6c, 0xf7, 0xa1, 0xfa, 0x65, 0xf4, 0xe6, 0xfa, 0x66, 0xf5, 0xc4, 0xbf, 0xa9, 0xfa, 0x68, 0xf6, 0xe8, 0xfa, 0x6c, 0xf7, 0xd8, 0xfa, 0x63, 0xf5, 0xc7, 0xfa, 0x66, 0xf1, 0xbc, 0xbf, 0xd9, 0xfa, 0x6c, 0xf4, 0xc1, 0xfa, 0x65, 0xf3, 0xe5, 0xfb, 0x66, 0x34, 0xb8, 0xbf, 0xe5, 0xfb, 0x66, 0x34, 0xe6, 0xfb, 0x08, 0x24, 0xc8, 0xbf, 0xe2, 0xfb, 0x06, 0x61, 0xa6, 0xfb, 0x08, 0x24, 0xc8, 0xbf, 0xa2, 0xfb, 0x06, 0x61, 0x92, 0xfa, 0x53, 0xf1, 0x84, 0xfa, 0x58, 0xf3, 0xcc, 0xbf, 0x97, 0xfa, 0x59, 0xf4, 0x81, 0xfa, 0x52, 0xf8, 0xa2, 0xfa, 0x53, 0xf1, 0xe4, 0xfa, 0x58, 0xf3, 0xcc, 0xbf, 0xa7, 0xfa, 0x59, 0xf4, 0xe1, 0xfa, 0x52, 0xf8, 0xa2, 0xfa, 0x53, 0xf1, 0xe4, 0xfa, 0x58, 0xf3, 0xcc, 0xbf, 0xa7, 0xfa, 0x59, 0xf4, 0xe1, 0xfa, 0x52, 0xf8, 0xc2, 0xfa, 0x59, 0xf8, 0xd9, 0xfa, 0x57, 0xf1, 0xcc, 0xbf, 0xc1, 0xfa, 0x56, 0xf3, 0xd6, 0xfa, 0x54, 0xf4, 0x79, 0xfb, 0x07, 0xf1, 0x72, 0xfb, 0x09, 0xc8, 0xcc, 0xbf, 0x71, 0xfb, 0x06, 0x93, 0x76, 0xfb, 0x04, 0xf4, 0x8a, 0xf3, 0x01, 0x08, 0x8a, 0xf3, 0x04, 0x08, 0x8a, 0xf3, 0xc5, 0x78, 0xaa, 0xf3, 0x50, 0x08, 0xa7, 0xf3, 0x02, 0x02, 0xa5, 0xf3, 0x0f, 0x03, 0xe3, 0xfa, 0x44, 0xf2, 0x18, 0xbf, 0xe1, 0xfa, 0x49, 0xf6, 0xe3, 0xfa, 0x44, 0xf2, 0x18, 0xbf, 0xe1, 0xfa, 0x49, 0xf6, 0xd2, 0xfa, 0x47, 0xf4, 0xc8, 0xfa, 0x45, 0xf1, 0x8c, 0xbf, 0xd1, 0xfa, 0x43, 0xf1, 0xc2, 0xfa, 0x43, 0xf9, 0x53, 0xfa, 0x84, 0xf2, 0x55, 0xfa, 0x86, 0xf4, 0xb8, 0xbf, 0x52, 0xfa, 0x99, 0xf6, 0x51, 0xfa, 0xa4, 0xf5, 0x58, 0xfa, 0xb3, 0xf7, 0xa8, 0xbf, 0x31, 0xfa, 0x84, 0xf0, 0x32, 0xfa, 0x87, 0xf6, 0x35, 0xfa, 0x98, 0xf3, 0x32, 0xfa, 0xa1, 0xf3, 0x08, 0xbf, 0x32, 0xfa, 0xb3, 0xf1, 0x13, 0xfa, 0x89, 0xf1, 0x88, 0xbf, 0x11, 0xfa, 0x86, 0xf6, 0x18, 0xfa, 0x93, 0xf3, 0x38, 0xbf, 0x12, 0xfa, 0xa4, 0xf2, 0x13, 0xfa, 0xb3, 0xf9, 0xa8, 0xbf, 0xe2, 0xb2, 0xf5, 0xb2, 0x5f, 0xfa, 0x99, 0xf6, 0x38, 0xbf, 0x5f, 0xfa, 0xa1, 0xf5, 0x5f, 0xfa, 0xb3, 0xf8, 0x5f, 0xfa, 0x88, 0xf7, 0x3f, 0xfa, 0x84, 0xf1, 0x3f, 0xfa, 0x87, 0xf6, 0x28, 0xbf, 0x3f, 0xfa, 0x95, 0xf3, 0x3f, 0xfa, 0xa1, 0xf3, 0xa8, 0xbf, 0x3f, 0xfa, 0xb3, 0xf2, 0x18, 0xbf, 0x1f, 0xfa, 0x89, 0xf3, 0xb1, 0xb2, 0x1f, 0xfa, 0x98, 0xf3, 0xd8, 0xbf, 0x1f, 0xfa, 0xa2, 0xf2, 0x1f, 0xfa, 0xb3, 0xf9, 0x1f, 0xfa, 0x88, 0xf7, 0x20, 0xbf, 0x30, 0xbf, 0x10, 0xbf, 0xb6, 0xbf, 0x20, 0xbf, 0x30, 0xbf, 0x10, 0xbf, 0xaf, 0xf3, 0x04, 0x80, 0xaf, 0xf3, 0x03, 0x80, 0xaf, 0xf3, 0x02, 0x80, 0xaf, 0xf3, 0x01, 0x80, 0xaf, 0xf3, 0x00, 0x80, 0x40, 0xbf, 0x30, 0xbf, 0x20, 0xbf, 0x10, 0xbf, 0x00, 0xbf, 0xb6, 0xbf, 0xf0, 0xbf, 0xaf, 0xf3, 0x10, 0x80, 0xaf, 0xf3, 0xef, 0x80, 0x70, 0xbf, 0xaf, 0xf3, 0x07, 0x80, 0x9f, 0xf8, 0x16, 0xb0, 0xbf, 0xf8, 0x16, 0xb0, 0x9f, 0xf9, 0x16, 0xb0, 0xbf, 0xf9, 0x16, 0xb0, 0xdf, 0xf8, 0x16, 0xb0, 0x9f, 0xf8, 0x16, 0xb0, 0xbf, 0xf8, 0x16, 0xb0, 0x9f, 0xf9, 0x16, 0xb0, 0xbf, 0xf9, 0x16, 0xb0, 0x5f, 0xf8, 0x16, 0xb0, 0x1f, 0xf8, 0x16, 0xb0, 0x3f, 0xf8, 0x16, 0xb0, 0x1f, 0xf9, 0x16, 0xb0, 0x3f, 0xf9, 0x16, 0xb0, 0x5f, 0xf8, 0x16, 0xb0, 0x1f, 0xf8, 0x16, 0xb0, 0x3f, 0xf8, 0x16, 0xb0, 0x1f, 0xf9, 0x16, 0xb0, 0x3f, 0xf9, 0x16, 0xb0, 0x03, 0x49, 0xde, 0xf3, 0x04, 0x8f ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ]
+    expected:
+      insns:
+        -
+          asm_text: "adc r0, r1, #4"
+        -
+          asm_text: "adcs r0, r1, #0"
+        -
+          asm_text: "adc r1, r2, #0xff"
+        -
+          asm_text: "adc r3, r7, #0x550055"
+        -
+          asm_text: "adc r8, r12, #0xaa00aa00"
+        -
+          asm_text: "adc r9, r7, #0xa5a5a5a5"
+        -
+          asm_text: "adc r5, r3, #0x87000000"
+        -
+          asm_text: "adc r4, r2, #0x7f800000"
+        -
+          asm_text: "adc r4, r2, #0x680"
+        -
+          asm_text: "adc.w r4, r5, r6"
+        -
+          asm_text: "adcs.w r4, r5, r6"
+        -
+          asm_text: "adc.w r9, r1, r3"
+        -
+          asm_text: "adcs.w r9, r1, r3"
+        -
+          asm_text: "adc.w r0, r1, r3, ror #4"
+        -
+          asm_text: "adcs.w r0, r1, r3, lsl #7"
+        -
+          asm_text: "adc.w r0, r1, r3, lsr #0x1f"
+        -
+          asm_text: "adcs.w r0, r1, r3, asr #0x20"
+        -
+          asm_text: "itet eq"
+        -
+          asm_text: "addeq r1, r2, #4"
+        -
+          asm_text: "addwne r5, r3, #0x3ff"
+        -
+          asm_text: "addweq r4, r5, #0x125"
+        -
+          asm_text: "add.w r2, sp, #0x400"
+        -
+          asm_text: "add.w r2, r8, #0xff00"
+        -
+          asm_text: "addw r2, r3, #0x101"
+        -
+          asm_text: "addw r2, r3, #0x101"
+        -
+          asm_text: "add.w r12, r6, #0x100"
+        -
+          asm_text: "addw r12, r6, #0x100"
+        -
+          asm_text: "adds.w r1, r2, #0x1f0"
+        -
+          asm_text: "add.w r2, r2, #1"
+        -
+          asm_text: "add.w r0, r0, #0x20"
+        -
+          asm_text: "adds r2, #0x38"
+        -
+          asm_text: "adds r2, #0x38"
+        -
+          asm_text: "add.w r1, r7, #0xcbcbcbcb"
+        -
+          asm_text: "subs.w r2, r2, #0x10"
+        -
+          asm_text: "subs.w r2, r2, #0x10"
+        -
+          asm_text: "subw r2, r2, #0x10"
+        -
+          asm_text: "subw r2, r2, #0x10"
+        -
+          asm_text: "subw r2, r2, #0x10"
+        -
+          asm_text: "add.w r1, r2, r8"
+        -
+          asm_text: "add.w r5, r9, r2, asr #0x20"
+        -
+          asm_text: "adds.w r7, r3, r1, lsl #0x1f"
+        -
+          asm_text: "adds.w r0, r3, r6, lsr #0x19"
+        -
+          asm_text: "add.w r4, r8, r1, ror #0xc"
+        -
+          asm_text: "adds r1, r1, r7"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "addeq r1, r3, r5"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "addeq r1, r1, r5"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "addseq.w r1, r3, r5"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "addseq.w r1, r1, r5"
+        -
+          asm_text: "add r10, r8"
+        -
+          asm_text: "add r10, r8"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "addeq r1, r10"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "addseq.w r1, r1, r10"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "addeq r7, sp, #0x3fc"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "addeq sp, #0x1fc"
+        -
+          asm_text: "add.w r7, sp, #0xf"
+        -
+          asm_text: "adds.w r7, sp, #0x10"
+        -
+          asm_text: "add.w r8, sp, #0x10"
+        -
+          asm_text: "addw r6, sp, #0x3fc"
+        -
+          asm_text: "addw r6, sp, #0x3fb"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "addeq r8, sp, r8"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "addeq sp, r9"
+        -
+          asm_text: "add.w r2, sp, r12"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "addeq.w r2, sp, r12"
+        -
+          asm_text: "adr.w r11, #4294964026"
+        -
+          asm_text: "adr.w r2, #3"
+        -
+          asm_text: "adr.w r11, #-0x33a"
+        -
+          asm_text: "subw r1, pc, #0"
+        -
+          asm_text: "and r2, r5, #0xff000"
+        -
+          asm_text: "ands r3, r12, #0xf"
+        -
+          asm_text: "and r1, r1, #0xff"
+        -
+          asm_text: "and r1, r1, #0xff"
+        -
+          asm_text: "and r5, r4, #0xffffffff"
+        -
+          asm_text: "ands r1, r9, #0xffffffff"
+        -
+          asm_text: "and.w r4, r9, r8"
+        -
+          asm_text: "and.w r1, r4, r8, asr #3"
+        -
+          asm_text: "ands.w r2, r1, r7, lsl #1"
+        -
+          asm_text: "ands.w r4, r5, r2, lsr #0x14"
+        -
+          asm_text: "and.w r9, r12, r1, ror #0x11"
+        -
+          asm_text: "asr.w r2, r3, #0xc"
+        -
+          asm_text: "asrs.w r8, r3, #0x20"
+        -
+          asm_text: "asrs.w r2, r3, #1"
+        -
+          asm_text: "asr.w r2, r3, #4"
+        -
+          asm_text: "asrs.w r2, r12, #0xf"
+        -
+          asm_text: "asr.w r3, r3, #0x13"
+        -
+          asm_text: "asrs.w r8, r8, #2"
+        -
+          asm_text: "asrs.w r7, r7, #5"
+        -
+          asm_text: "asr.w r12, r12, #0x15"
+        -
+          asm_text: "asrs r1, r2, #1"
+        -
+          asm_text: "itt eq"
+        -
+          asm_text: "asrseq.w r1, r2, #1"
+        -
+          asm_text: "asreq r1, r2, #1"
+        -
+          asm_text: "asr.w r3, r4, r2"
+        -
+          asm_text: "asr.w r1, r1, r2"
+        -
+          asm_text: "asrs.w r3, r4, r8"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "beq.w #-0x2cc64"
+        -
+          asm_text: "bfc r5, #3, #0x11"
+        -
+          asm_text: "it lo"
+        -
+          asm_text: "bfclo r5, #3, #0x11"
+        -
+          asm_text: "bfi r5, r2, #3, #0x11"
+        -
+          asm_text: "it ne"
+        -
+          asm_text: "bfine r5, r2, #3, #0x11"
+        -
+          asm_text: "bic r10, r1, #0xf"
+        -
+          asm_text: "bic r5, r2, #0xffffffff"
+        -
+          asm_text: "bics r11, r10, #0xffffffff"
+        -
+          asm_text: "bic.w r12, r3, r6"
+        -
+          asm_text: "bic.w r11, r2, r6, lsl #0xc"
+        -
+          asm_text: "bic.w r8, r4, r1, lsr #0xb"
+        -
+          asm_text: "bic.w r7, r5, r7, lsr #0xf"
+        -
+          asm_text: "bic.w r6, r7, r9, asr #0x20"
+        -
+          asm_text: "bic.w r5, r6, r8, ror #1"
+        -
+          asm_text: "bic r1, r1, #0xf"
+        -
+          asm_text: "bic.w r1, r1, r1"
+        -
+          asm_text: "bic.w r4, r4, r2, lsl #0x1f"
+        -
+          asm_text: "bic.w r6, r6, r3, lsr #0xc"
+        -
+          asm_text: "bic.w r7, r7, r4, lsr #7"
+        -
+          asm_text: "bic.w r8, r8, r5, asr #0xf"
+        -
+          asm_text: "bic.w r12, r12, r6, ror #0x1d"
+        -
+          asm_text: "it pl"
+        -
+          asm_text: "bkpt #0xea"
+        -
+          asm_text: "bxj r5"
+        -
+          asm_text: "it ne"
+        -
+          asm_text: "bxjne r7"
+        -
+          asm_text: "cbnz r7, #6"
+        -
+          asm_text: "cbnz r7, #0xc"
+        -
+          asm_text: "cdp p7, #1, c1, c1, c1, #4"
+        -
+          asm_text: "cdp2 p7, #1, c1, c1, c1, #4"
+        -
+          asm_text: "clrex"
+        -
+          asm_text: "it ne"
+        -
+          asm_text: "clrexne"
+        -
+          asm_text: "clz r1, r2"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "clzeq r1, r2"
+        -
+          asm_text: "cmn.w r1, #0xf"
+        -
+          asm_text: "cmn.w r8, r6"
+        -
+          asm_text: "cmn.w r1, r6, lsl #0xa"
+        -
+          asm_text: "cmn.w r1, r6, lsr #0xa"
+        -
+          asm_text: "cmn.w sp, r6, lsr #0xa"
+        -
+          asm_text: "cmn.w r1, r6, asr #0xa"
+        -
+          asm_text: "cmn.w r1, r6, ror #0xa"
+        -
+          asm_text: "cmp.w r5, #0xff00"
+        -
+          asm_text: "cmp.w r4, r12"
+        -
+          asm_text: "cmp.w r9, r6, lsl #0xc"
+        -
+          asm_text: "cmp.w r3, r7, lsr #0x1f"
+        -
+          asm_text: "cmp.w sp, r6, lsr #1"
+        -
+          asm_text: "cmp.w r2, r5, asr #0x18"
+        -
+          asm_text: "cmp.w r1, r4, ror #0xf"
+        -
+          asm_text: "cmn.w r2, #2"
+        -
+          asm_text: "cmp.w r9, #1"
+        -
+          asm_text: "cpsie f"
+        -
+          asm_text: "cpsid a"
+        -
+          asm_text: "cpsie.w f"
+        -
+          asm_text: "cpsid.w a"
+        -
+          asm_text: "cpsie i, #3"
+        -
+          asm_text: "cpsie i, #3"
+        -
+          asm_text: "cpsid f, #0x9"
+        -
+          asm_text: "cpsid f, #0x9"
+        -
+          asm_text: "cps #0"
+        -
+          asm_text: "cps #0"
+        -
+          asm_text: "dbg #5"
+        -
+          asm_text: "dbg #0"
+        -
+          asm_text: "dbg #0xf"
+        -
+          asm_text: "dbg #0"
+        -
+          asm_text: "it ne"
+        -
+          asm_text: "dbgne #0"
+        -
+          asm_text: "dmb sy"
+        -
+          asm_text: "dmb st"
+        -
+          asm_text: "dmb #0xd"
+        -
+          asm_text: "dmb #0xc"
+        -
+          asm_text: "dmb ish"
+        -
+          asm_text: "dmb ishst"
+        -
+          asm_text: "dmb #0x9"
+        -
+          asm_text: "dmb #0x8"
+        -
+          asm_text: "dmb nsh"
+        -
+          asm_text: "dmb nshst"
+        -
+          asm_text: "dmb #0x5"
+        -
+          asm_text: "dmb #0x4"
+        -
+          asm_text: "dmb osh"
+        -
+          asm_text: "dmb oshst"
+        -
+          asm_text: "dmb #0x1"
+        -
+          asm_text: "dmb #0x0"
+        -
+          asm_text: "dmb sy"
+        -
+          asm_text: "dmb sy"
+        -
+          asm_text: "dmb st"
+        -
+          asm_text: "dmb ish"
+        -
+          asm_text: "dmb ish"
+        -
+          asm_text: "dmb ishst"
+        -
+          asm_text: "dmb ishst"
+        -
+          asm_text: "dmb nsh"
+        -
+          asm_text: "dmb nsh"
+        -
+          asm_text: "dmb nshst"
+        -
+          asm_text: "dmb nshst"
+        -
+          asm_text: "dmb osh"
+        -
+          asm_text: "dmb oshst"
+        -
+          asm_text: "dmb sy"
+        -
+          asm_text: "dmb sy"
+        -
+          asm_text: "dsb sy"
+        -
+          asm_text: "dsb st"
+        -
+          asm_text: "dsb #0xd"
+        -
+          asm_text: "dsb #0xc"
+        -
+          asm_text: "dsb ish"
+        -
+          asm_text: "dsb ishst"
+        -
+          asm_text: "dsb #0x9"
+        -
+          asm_text: "dsb #0x8"
+        -
+          asm_text: "dsb nsh"
+        -
+          asm_text: "dsb nshst"
+        -
+          asm_text: "dsb #0x5"
+        -
+          asm_text: "pssbb"
+        -
+          asm_text: "dsb osh"
+        -
+          asm_text: "dsb oshst"
+        -
+          asm_text: "dsb #0x1"
+        -
+          asm_text: "ssbb"
+        -
+          asm_text: "dsb sy"
+        -
+          asm_text: "dsb sy"
+        -
+          asm_text: "dsb st"
+        -
+          asm_text: "dsb ish"
+        -
+          asm_text: "dsb ish"
+        -
+          asm_text: "dsb ishst"
+        -
+          asm_text: "dsb ishst"
+        -
+          asm_text: "dsb nsh"
+        -
+          asm_text: "dsb nsh"
+        -
+          asm_text: "dsb nshst"
+        -
+          asm_text: "dsb nshst"
+        -
+          asm_text: "dsb osh"
+        -
+          asm_text: "dsb oshst"
+        -
+          asm_text: "dsb sy"
+        -
+          asm_text: "dsb sy"
+        -
+          asm_text: "eor r4, r5, #0xf000"
+        -
+          asm_text: "eor.w r4, r5, r6"
+        -
+          asm_text: "eor.w r4, r5, r6, lsl #5"
+        -
+          asm_text: "eor.w r4, r5, r6, lsr #5"
+        -
+          asm_text: "eor.w r4, r5, r6, lsr #5"
+        -
+          asm_text: "eor.w r4, r5, r6, asr #5"
+        -
+          asm_text: "eor.w r4, r5, r6, ror #5"
+        -
+          asm_text: "isb sy"
+        -
+          asm_text: "isb sy"
+        -
+          asm_text: "isb sy"
+        -
+          asm_text: "isb sy"
+        -
+          asm_text: "isb sy"
+        -
+          asm_text: "isb #0x1"
+        -
+          asm_text: "iteet eq"
+        -
+          asm_text: "addeq r0, r1, r2"
+        -
+          asm_text: "nopne"
+        -
+          asm_text: "subne r5, r6, r7"
+        -
+          asm_text: "addeq r1, r2, #4"
+        -
+          asm_text: "iteet eq"
+        -
+          asm_text: "addeq r0, r1, r2"
+        -
+          asm_text: "nopne"
+        -
+          asm_text: "subne r5, r6, r7"
+        -
+          asm_text: "addeq r1, r2, #4"
+        -
+          asm_text: "ldc2 p0, c8, [r1, #4]"
+        -
+          asm_text: "ldc2 p1, c7, [r2]"
+        -
+          asm_text: "ldc2 p2, c6, [r3, #-0xe0]"
+        -
+          asm_text: "ldc2 p3, c5, [r4, #-0x78]!"
+        -
+          asm_text: "ldc2 p4, c4, [r5], #0x10"
+        -
+          asm_text: "ldc2 p5, c3, [r6], #-0x48"
+        -
+          asm_text: "ldc2l p6, c2, [r7, #4]"
+        -
+          asm_text: "ldc2l p7, c1, [r8]"
+        -
+          asm_text: "ldc2l p8, c0, [r9, #-0xe0]"
+        -
+          asm_text: "ldc2l p9, c1, [r10, #-0x78]!"
+        -
+          asm_text: "ldc2l p0, c2, [r11], #0x10"
+        -
+          asm_text: "ldc2l p1, c3, [r12], #-0x48"
+        -
+          asm_text: "ldc p12, c4, [r0, #4]"
+        -
+          asm_text: "ldc p13, c5, [r1]"
+        -
+          asm_text: "ldc p14, c6, [r2, #-0xe0]"
+        -
+          asm_text: "ldc p15, c7, [r3, #-0x78]!"
+        -
+          asm_text: "ldc p5, c8, [r4], #0x10"
+        -
+          asm_text: "ldc p4, c9, [r5], #-0x48"
+        -
+          asm_text: "ldcl p3, c10, [r6, #4]"
+        -
+          asm_text: "ldcl p2, c11, [r7]"
+        -
+          asm_text: "ldcl p1, c12, [r8, #-0xe0]"
+        -
+          asm_text: "ldcl p0, c13, [r9, #-0x78]!"
+        -
+          asm_text: "ldcl p6, c14, [r10], #0x10"
+        -
+          asm_text: "ldcl p7, c15, [r11], #-0x48"
+        -
+          asm_text: "ldc2 p2, c8, [r1], {25}"
+        -
+          asm_text: "ldm.w r4, {r4, r5, r8, r9}"
+        -
+          asm_text: "ldm.w r4, {r5, r6}"
+        -
+          asm_text: "ldm.w r5!, {r3, r8}"
+        -
+          asm_text: "ldm.w r4, {r4, r5, r8, r9}"
+        -
+          asm_text: "ldm.w r4, {r5, r6}"
+        -
+          asm_text: "ldm.w r5!, {r3, r8}"
+        -
+          asm_text: "ldm.w r5!, {r1, r2}"
+        -
+          asm_text: "ldm.w r2, {r1, r2}"
+        -
+          asm_text: "ldm.w r4, {r4, r5, r8, r9}"
+        -
+          asm_text: "ldm.w r4, {r5, r6}"
+        -
+          asm_text: "ldm.w r5!, {r3, r8}"
+        -
+          asm_text: "ldm.w r4, {r4, r5, r8, r9}"
+        -
+          asm_text: "ldm.w r4, {r5, r6}"
+        -
+          asm_text: "ldm.w r5!, {r3, r8}"
+        -
+          asm_text: "ldm.w r5!, {r3, r8}"
+        -
+          asm_text: "pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc}"
+        -
+          asm_text: "ldmdb r4, {r4, r5, r8, r9}"
+        -
+          asm_text: "ldmdb r4, {r5, r6}"
+        -
+          asm_text: "ldmdb r5!, {r3, r8}"
+        -
+          asm_text: "ldmdb r5!, {r3, r8}"
+        -
+          asm_text: "ldmdb r4, {r5, r6}"
+        -
+          asm_text: "ldmdb r5!, {r3, r8}"
+        -
+          asm_text: "ldr r5, [r5, #-4]"
+        -
+          asm_text: "ldr r5, [r6, #0x20]"
+        -
+          asm_text: "ldr.w r5, [r6, #0x21]"
+        -
+          asm_text: "ldr.w r5, [r6, #0x101]"
+        -
+          asm_text: "ldr.w pc, [r7, #0x101]"
+        -
+          asm_text: "ldr r2, [r4, #0xff]!"
+        -
+          asm_text: "ldr r8, [sp, #4]!"
+        -
+          asm_text: "ldr lr, [sp, #-4]!"
+        -
+          asm_text: "ldr r2, [r4], #0xff"
+        -
+          asm_text: "pop {r8}"
+        -
+          asm_text: "ldr lr, [sp], #-4"
+        -
+          asm_text: "ldr r7, [pc, #8]"
+        -
+          asm_text: "ldr r7, [pc, #8]"
+        -
+          asm_text: "ldr.w r7, [pc, #8]"
+        -
+          asm_text: "ldr r4, [pc, #0x3fc]"
+        -
+          asm_text: "ldr.w r3, [pc, #-0x3fc]"
+        -
+          asm_text: "ldr.w r6, [pc, #0x400]"
+        -
+          asm_text: "ldr.w r0, [pc, #-0x400]"
+        -
+          asm_text: "ldr.w r2, [pc, #0xfff]"
+        -
+          asm_text: "ldr.w r1, [pc, #-0xfff]"
+        -
+          asm_text: "ldr.w r8, [pc, #0x84]"
+        -
+          asm_text: "ldr.w pc, [pc, #0x100]"
+        -
+          asm_text: "ldr.w pc, [pc, #-0x190]"
+        -
+          asm_text: "ldr.w sp, [pc, #4]"
+        -
+          asm_text: "ldrb.w r9, [pc, #-0]"
+        -
+          asm_text: "ldrsb.w r11, [pc, #-0]"
+        -
+          asm_text: "ldrh.w r10, [pc, #-0]"
+        -
+          asm_text: "ldrsh.w r1, [pc, #-0]"
+        -
+          asm_text: "ldr.w r5, [pc, #-0]"
+        -
+          asm_text: "ldr.w r1, [r8, r1]"
+        -
+          asm_text: "ldr.w r4, [r5, r2]"
+        -
+          asm_text: "ldr.w r6, [r0, r2, lsl #3]"
+        -
+          asm_text: "ldr.w r8, [r8, r2, lsl #2]"
+        -
+          asm_text: "ldr.w r7, [sp, r2, lsl #1]"
+        -
+          asm_text: "ldr.w r7, [sp, r2]"
+        -
+          asm_text: "ldrb r5, [r5, #-4]"
+        -
+          asm_text: "ldrb.w r5, [r6, #0x20]"
+        -
+          asm_text: "ldrb.w r5, [r6, #0x21]"
+        -
+          asm_text: "ldrb.w r5, [r6, #0x101]"
+        -
+          asm_text: "ldrb.w lr, [r7, #0x101]"
+        -
+          asm_text: "ldrb r5, [r8, #0xff]!"
+        -
+          asm_text: "ldrb r2, [r5, #4]!"
+        -
+          asm_text: "ldrb r1, [r4, #-4]!"
+        -
+          asm_text: "ldrb lr, [r3], #0xff"
+        -
+          asm_text: "ldrb r9, [r2], #4"
+        -
+          asm_text: "ldrb r3, [sp], #-4"
+        -
+          asm_text: "ldrb.w r1, [r8, r1]"
+        -
+          asm_text: "ldrb.w r4, [r5, r2]"
+        -
+          asm_text: "ldrb.w r6, [r0, r2, lsl #3]"
+        -
+          asm_text: "ldrb.w r8, [r8, r2, lsl #2]"
+        -
+          asm_text: "ldrb.w r7, [sp, r2, lsl #1]"
+        -
+          asm_text: "ldrb.w r7, [sp, r2]"
+        -
+          asm_text: "ldrbt r1, [r2]"
+        -
+          asm_text: "ldrbt r1, [r8]"
+        -
+          asm_text: "ldrbt r1, [r8, #3]"
+        -
+          asm_text: "ldrbt r1, [r8, #0xff]"
+        -
+          asm_text: "ldrd r3, r5, [r6, #0x18]"
+        -
+          asm_text: "ldrd r3, r5, [r6, #0x18]!"
+        -
+          asm_text: "ldrd r3, r5, [r6], #4"
+        -
+          asm_text: "ldrd r3, r5, [r6], #-8"
+        -
+          asm_text: "ldrd r3, r5, [r6]"
+        -
+          asm_text: "ldrd r8, r1, [r3]"
+        -
+          asm_text: "ldrd r0, r1, [r2, #-0]"
+        -
+          asm_text: "ldrd r0, r1, [r2, #-0]!"
+        -
+          asm_text: "ldrd r0, r1, [r2], #-0"
+        -
+          asm_text: "ldrex r1, [r4]"
+        -
+          asm_text: "ldrex r8, [r4]"
+        -
+          asm_text: "ldrex r2, [sp, #0x80]"
+        -
+          asm_text: "ldrexb r5, [r7]"
+        -
+          asm_text: "ldrexh r9, [r12]"
+        -
+          asm_text: "ldrexd r9, r3, [r4]"
+        -
+          asm_text: "ldrh r5, [r5, #-4]"
+        -
+          asm_text: "ldrh r5, [r6, #0x20]"
+        -
+          asm_text: "ldrh.w r5, [r6, #0x21]"
+        -
+          asm_text: "ldrh.w r5, [r6, #0x101]"
+        -
+          asm_text: "ldrh.w lr, [r7, #0x101]"
+        -
+          asm_text: "ldrh r5, [r8, #0xff]!"
+        -
+          asm_text: "ldrh r2, [r5, #4]!"
+        -
+          asm_text: "ldrh r1, [r4, #-4]!"
+        -
+          asm_text: "ldrh lr, [r3], #0xff"
+        -
+          asm_text: "ldrh r9, [r2], #4"
+        -
+          asm_text: "ldrh r3, [sp], #-4"
+        -
+          asm_text: "ldrh.w r1, [r8, r1]"
+        -
+          asm_text: "ldrh.w r4, [r5, r2]"
+        -
+          asm_text: "ldrh.w r6, [r0, r2, lsl #3]"
+        -
+          asm_text: "ldrh.w r8, [r8, r2, lsl #2]"
+        -
+          asm_text: "ldrh.w r7, [sp, r2, lsl #1]"
+        -
+          asm_text: "ldrh.w r7, [sp, r2]"
+        -
+          asm_text: "ldrht r1, [r2]"
+        -
+          asm_text: "ldrht r1, [r8]"
+        -
+          asm_text: "ldrht r1, [r8, #3]"
+        -
+          asm_text: "ldrht r1, [r8, #0xff]"
+        -
+          asm_text: "ldrsb r5, [r5, #-4]"
+        -
+          asm_text: "ldrsb.w r5, [r6, #0x20]"
+        -
+          asm_text: "ldrsb.w r5, [r6, #0x21]"
+        -
+          asm_text: "ldrsb.w r5, [r6, #0x101]"
+        -
+          asm_text: "ldrsb.w lr, [r7, #0x101]"
+        -
+          asm_text: "ldrsb.w r1, [r8, r1]"
+        -
+          asm_text: "ldrsb.w r4, [r5, r2]"
+        -
+          asm_text: "ldrsb.w r6, [r0, r2, lsl #3]"
+        -
+          asm_text: "ldrsb.w r8, [r8, r2, lsl #2]"
+        -
+          asm_text: "ldrsb.w r7, [sp, r2, lsl #1]"
+        -
+          asm_text: "ldrsb.w r7, [sp, r2]"
+        -
+          asm_text: "ldrsb r5, [r8, #0xff]!"
+        -
+          asm_text: "ldrsb r2, [r5, #4]!"
+        -
+          asm_text: "ldrsb r1, [r4, #-4]!"
+        -
+          asm_text: "ldrsb lr, [r3], #0xff"
+        -
+          asm_text: "ldrsb r9, [r2], #4"
+        -
+          asm_text: "ldrsb r3, [sp], #-4"
+        -
+          asm_text: "ldrsbt r1, [r2]"
+        -
+          asm_text: "ldrsbt r1, [r8]"
+        -
+          asm_text: "ldrsbt r1, [r8, #3]"
+        -
+          asm_text: "ldrsbt r1, [r8, #0xff]"
+        -
+          asm_text: "ldrsh r5, [r5, #-4]"
+        -
+          asm_text: "ldrsh.w r5, [r6, #0x20]"
+        -
+          asm_text: "ldrsh.w r5, [r6, #0x21]"
+        -
+          asm_text: "ldrsh.w r5, [r6, #0x101]"
+        -
+          asm_text: "ldrsh.w lr, [r7, #0x101]"
+        -
+          asm_text: "ldrsh.w r1, [r8, r1]"
+        -
+          asm_text: "ldrsh.w r4, [r5, r2]"
+        -
+          asm_text: "ldrsh.w r6, [r0, r2, lsl #3]"
+        -
+          asm_text: "ldrsh.w r8, [r8, r2, lsl #2]"
+        -
+          asm_text: "ldrsh.w r7, [sp, r2, lsl #1]"
+        -
+          asm_text: "ldrsh.w r7, [sp, r2]"
+        -
+          asm_text: "ldrsh r5, [r8, #0xff]!"
+        -
+          asm_text: "ldrsh r2, [r5, #4]!"
+        -
+          asm_text: "ldrsh r1, [r4, #-4]!"
+        -
+          asm_text: "ldrsh lr, [r3], #0xff"
+        -
+          asm_text: "ldrsh r9, [r2], #4"
+        -
+          asm_text: "ldrsh r3, [sp], #-4"
+        -
+          asm_text: "ldrsht r1, [r2]"
+        -
+          asm_text: "ldrsht r1, [r8]"
+        -
+          asm_text: "ldrsht r1, [r8, #3]"
+        -
+          asm_text: "ldrsht r1, [r8, #0xff]"
+        -
+          asm_text: "ldrt r1, [r2]"
+        -
+          asm_text: "ldrt r2, [r6]"
+        -
+          asm_text: "ldrt r3, [r7, #3]"
+        -
+          asm_text: "ldrt r4, [r9, #0xff]"
+        -
+          asm_text: "lsl.w r2, r3, #0xc"
+        -
+          asm_text: "lsls.w r8, r3, #0x1f"
+        -
+          asm_text: "lsls.w r2, r3, #1"
+        -
+          asm_text: "lsl.w r2, r3, #4"
+        -
+          asm_text: "lsls.w r2, r12, #0xf"
+        -
+          asm_text: "lsl.w r3, r3, #0x13"
+        -
+          asm_text: "lsls.w r8, r8, #2"
+        -
+          asm_text: "lsls.w r7, r7, #5"
+        -
+          asm_text: "lsl.w r12, r12, #0x15"
+        -
+          asm_text: "lsls r1, r2, #1"
+        -
+          asm_text: "itt eq"
+        -
+          asm_text: "lslseq.w r1, r2, #1"
+        -
+          asm_text: "lsleq r1, r2, #1"
+        -
+          asm_text: "lsl.w r3, r4, r2"
+        -
+          asm_text: "lsl.w r1, r1, r2"
+        -
+          asm_text: "lsls.w r3, r4, r8"
+        -
+          asm_text: "lsr.w r2, r3, #0xc"
+        -
+          asm_text: "lsrs.w r8, r3, #0x20"
+        -
+          asm_text: "lsrs.w r2, r3, #1"
+        -
+          asm_text: "lsr.w r2, r3, #4"
+        -
+          asm_text: "lsrs.w r2, r12, #0xf"
+        -
+          asm_text: "lsr.w r3, r3, #0x13"
+        -
+          asm_text: "lsrs.w r8, r8, #2"
+        -
+          asm_text: "lsrs.w r7, r7, #5"
+        -
+          asm_text: "lsr.w r12, r12, #0x15"
+        -
+          asm_text: "lsrs r1, r2, #1"
+        -
+          asm_text: "itt eq"
+        -
+          asm_text: "lsrseq.w r1, r2, #1"
+        -
+          asm_text: "lsreq r1, r2, #1"
+        -
+          asm_text: "lsr.w r3, r4, r2"
+        -
+          asm_text: "lsr.w r1, r1, r2"
+        -
+          asm_text: "lsrs.w r3, r4, r8"
+        -
+          asm_text: "mcr p7, #1, r5, c1, c1, #4"
+        -
+          asm_text: "mcr2 p7, #1, r5, c1, c1, #4"
+        -
+          asm_text: "mcr p14, #0, r4, c0, c5, #0"
+        -
+          asm_text: "mcr2 p4, #2, r2, c1, c3, #0"
+        -
+          asm_text: "mcr p7, #1, r5, c1, c1, #4"
+        -
+          asm_text: "mcr2 p7, #1, r5, c1, c1, #4"
+        -
+          asm_text: "mcr p14, #0, r4, c0, c5, #0"
+        -
+          asm_text: "mcr2 p4, #2, r2, c1, c3, #0"
+        -
+          asm_text: "mcrr p7, #0xf, r5, r4, c1"
+        -
+          asm_text: "mcrr2 p7, #0xf, r5, r4, c1"
+        -
+          asm_text: "mcrr p7, #0xf, r5, r4, c1"
+        -
+          asm_text: "mcrr2 p7, #0xf, r5, r4, c1"
+        -
+          asm_text: "mla r1, r2, r3, r4"
+        -
+          asm_text: "mls r1, r2, r3, r4"
+        -
+          asm_text: "movs r1, #0x15"
+        -
+          asm_text: "movs.w r1, #0x15"
+        -
+          asm_text: "movs.w r8, #0x15"
+        -
+          asm_text: "movw r0, #0xffff"
+        -
+          asm_text: "movw r1, #0xab01"
+        -
+          asm_text: "movw r1, #0xab10"
+        -
+          asm_text: "mov.w r0, #0x3fc0000"
+        -
+          asm_text: "mov.w r0, #0x3fc0000"
+        -
+          asm_text: "movs.w r0, #0x3fc0000"
+        -
+          asm_text: "itte eq"
+        -
+          asm_text: "movseq.w r1, #0xc"
+        -
+          asm_text: "moveq r1, #0xc"
+        -
+          asm_text: "movne.w r1, #0xc"
+        -
+          asm_text: "mov.w r6, #0x1c2"
+        -
+          asm_text: "it lo"
+        -
+          asm_text: "movlo.w r1, #-1"
+        -
+          asm_text: "mvn r3, #2"
+        -
+          asm_text: "movw r11, #0xabcd"
+        -
+          asm_text: "movs r0, #1"
+        -
+          asm_text: "it ne"
+        -
+          asm_text: "movne r3, #0xf"
+        -
+          asm_text: "itt eq"
+        -
+          asm_text: "moveq r0, #0xff"
+        -
+          asm_text: "movweq r1, #0x100"
+        -
+          asm_text: "lsl.w r6, r2, #0x10"
+        -
+          asm_text: "lsl.w r6, r2, #0x10"
+        -
+          asm_text: "lsr.w r6, r2, #0x10"
+        -
+          asm_text: "lsr.w r6, r2, #0x10"
+        -
+          asm_text: "asrs r6, r2, #0x20"
+        -
+          asm_text: "asrs.w r6, r2, #0x20"
+        -
+          asm_text: "rors.w r6, r2, #5"
+        -
+          asm_text: "rors.w r6, r2, #5"
+        -
+          asm_text: "lsls r4, r5"
+        -
+          asm_text: "lsls.w r4, r4, r5"
+        -
+          asm_text: "lsrs r4, r5"
+        -
+          asm_text: "lsrs.w r4, r4, r5"
+        -
+          asm_text: "asrs r4, r5"
+        -
+          asm_text: "asrs.w r4, r4, r5"
+        -
+          asm_text: "rors r4, r5"
+        -
+          asm_text: "rors.w r4, r4, r5"
+        -
+          asm_text: "lsl.w r4, r4, r5"
+        -
+          asm_text: "rors.w r4, r4, r8"
+        -
+          asm_text: "lsrs.w r4, r5, r6"
+        -
+          asm_text: "itttt eq"
+        -
+          asm_text: "lsleq r4, r5"
+        -
+          asm_text: "lsreq r4, r5"
+        -
+          asm_text: "asreq r4, r5"
+        -
+          asm_text: "roreq r4, r5"
+        -
+          asm_text: "rrx r4, r4"
+        -
+          asm_text: "movt r3, #7"
+        -
+          asm_text: "movt r6, #0xffff"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "movteq r4, #0xff0"
+        -
+          asm_text: "mrc p14, #0, r1, c1, c2, #4"
+        -
+          asm_text: "mrc p15, #7, apsr_nzcv, c15, c6, #6"
+        -
+          asm_text: "mrc p9, #1, r1, c2, c2, #0"
+        -
+          asm_text: "mrc2 p12, #3, r3, c3, c4, #0"
+        -
+          asm_text: "mrc2 p14, #0, r1, c1, c2, #4"
+        -
+          asm_text: "mrc2 p8, #7, apsr_nzcv, c15, c0, #1"
+        -
+          asm_text: "mrc p14, #0, r1, c1, c2, #4"
+        -
+          asm_text: "mrc p15, #7, apsr_nzcv, c15, c6, #6"
+        -
+          asm_text: "mrc p9, #1, r1, c2, c2, #0"
+        -
+          asm_text: "mrc2 p12, #3, r3, c3, c4, #0"
+        -
+          asm_text: "mrc2 p14, #0, r1, c1, c2, #4"
+        -
+          asm_text: "mrc2 p8, #7, apsr_nzcv, c15, c0, #1"
+        -
+          asm_text: "mrrc p7, #1, r5, r4, c1"
+        -
+          asm_text: "mrrc2 p7, #1, r5, r4, c1"
+        -
+          asm_text: "mrrc p7, #1, r5, r4, c1"
+        -
+          asm_text: "mrrc2 p7, #1, r5, r4, c1"
+        -
+          asm_text: "mrs r8, apsr"
+        -
+          asm_text: "mrs r8, apsr"
+        -
+          asm_text: "mrs r8, spsr"
+        -
+          asm_text: "msr apsr_nzcvq, r1"
+        -
+          asm_text: "msr apsr_g, r2"
+        -
+          asm_text: "msr apsr_nzcvq, r3"
+        -
+          asm_text: "msr apsr_nzcvq, r4"
+        -
+          asm_text: "msr apsr_nzcvqg, r5"
+        -
+          asm_text: "msr cpsr_fc, r6"
+        -
+          asm_text: "msr cpsr_c, r7"
+        -
+          asm_text: "msr cpsr_x, r8"
+        -
+          asm_text: "msr cpsr_fc, r9"
+        -
+          asm_text: "msr cpsr_fc, r11"
+        -
+          asm_text: "msr cpsr_fsx, r12"
+        -
+          asm_text: "msr spsr_fc, r0"
+        -
+          asm_text: "msr spsr_fsxc, r5"
+        -
+          asm_text: "msr cpsr_fsxc, r8"
+        -
+          asm_text: "msr cpsr_fc, r3"
+        -
+          asm_text: "muls r3, r4, r3"
+        -
+          asm_text: "mul r3, r4, r3"
+        -
+          asm_text: "mul r3, r4, r6"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "muleq r3, r4, r5"
+        -
+          asm_text: "it le"
+        -
+          asm_text: "mulle r4, r4, r8"
+        -
+          asm_text: "mul r5, r6, r5"
+        -
+          asm_text: "mvns r8, #0x15"
+        -
+          asm_text: "mvn r0, #0x3fc0000"
+        -
+          asm_text: "mvns r0, #0x3fc0000"
+        -
+          asm_text: "itte eq"
+        -
+          asm_text: "mvnseq r1, #0xc"
+        -
+          asm_text: "mvneq r1, #0xc"
+        -
+          asm_text: "mvnne r1, #0xc"
+        -
+          asm_text: "mvn.w r2, r3"
+        -
+          asm_text: "mvns r2, r3"
+        -
+          asm_text: "mvn.w r5, r6, lsl #0x13"
+        -
+          asm_text: "mvn.w r5, r6, lsr #0x9"
+        -
+          asm_text: "mvn.w r5, r6, asr #4"
+        -
+          asm_text: "mvn.w r5, r6, ror #6"
+        -
+          asm_text: "mvn.w r5, r6, rrx"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "mvneq r2, r3"
+        -
+          asm_text: "rsb.w r5, r2, #0"
+        -
+          asm_text: "rsb.w r5, r8, #0"
+        -
+          asm_text: "nop.w"
+        -
+          asm_text: "orn r4, r5, #0xf000"
+        -
+          asm_text: "orn r4, r5, #0xf000"
+        -
+          asm_text: "orn r4, r5, r6"
+        -
+          asm_text: "orn r4, r5, r6"
+        -
+          asm_text: "orns r4, r5, r6"
+        -
+          asm_text: "orns r4, r5, r6"
+        -
+          asm_text: "orn r4, r5, r6, lsl #5"
+        -
+          asm_text: "orn r4, r5, r6, lsl #5"
+        -
+          asm_text: "orns r4, r5, r6, lsr #5"
+        -
+          asm_text: "orn r4, r5, r6, lsr #5"
+        -
+          asm_text: "orns r4, r5, r6, asr #5"
+        -
+          asm_text: "orn r4, r5, r6, ror #5"
+        -
+          asm_text: "orr r4, r5, #0xf000"
+        -
+          asm_text: "orr.w r4, r5, r6"
+        -
+          asm_text: "orr.w r4, r5, r6, lsl #5"
+        -
+          asm_text: "orrs.w r4, r5, r6, lsr #5"
+        -
+          asm_text: "orr.w r4, r5, r6, lsr #5"
+        -
+          asm_text: "orrs.w r4, r5, r6, asr #5"
+        -
+          asm_text: "orr.w r4, r5, r6, ror #5"
+        -
+          asm_text: "pkhbt r2, r2, r3"
+        -
+          asm_text: "pkhbt r2, r2, r3, lsl #0x1f"
+        -
+          asm_text: "pkhbt r2, r2, r3"
+        -
+          asm_text: "pkhbt r2, r2, r3, lsl #0xf"
+        -
+          asm_text: "pkhbt r2, r3, r2"
+        -
+          asm_text: "pkhtb r2, r2, r3, asr #0x1f"
+        -
+          asm_text: "pkhtb r2, r2, r3, asr #0xf"
+        -
+          asm_text: "pld [r5, #-4]"
+        -
+          asm_text: "pld [r6, #0x20]"
+        -
+          asm_text: "pld [r6, #0x21]"
+        -
+          asm_text: "pld [r6, #0x101]"
+        -
+          asm_text: "pld [r7, #0x101]"
+        -
+          asm_text: "pld [r1]"
+        -
+          asm_text: "pld [r1, #-0]"
+        -
+          asm_text: "pld [r1, #-0]"
+        -
+          asm_text: "pld [pc, #-0xfff]"
+        -
+          asm_text: "pld [pc, #-0xfff]"
+        -
+          asm_text: "pld [r8, r1]"
+        -
+          asm_text: "pld [r5, r2]"
+        -
+          asm_text: "pld [r5, r2]"
+        -
+          asm_text: "pld [r0, r2, lsl #3]"
+        -
+          asm_text: "pld [r8, r2, lsl #2]"
+        -
+          asm_text: "pld [sp, r2, lsl #1]"
+        -
+          asm_text: "pld [sp, r2]"
+        -
+          asm_text: "pld [sp, r2, lsl #1]"
+        -
+          asm_text: "pli [r5, #-4]"
+        -
+          asm_text: "pli [r6, #0x20]"
+        -
+          asm_text: "pli [r6, #0x21]"
+        -
+          asm_text: "pli [r6, #0x101]"
+        -
+          asm_text: "pli [r7, #0x101]"
+        -
+          asm_text: "pli [pc, #0xfff]"
+        -
+          asm_text: "pli [pc, #-0xfff]"
+        -
+          asm_text: "pli [pc, #-0xfff]"
+        -
+          asm_text: "pli [r8, r1]"
+        -
+          asm_text: "pli [r5, r2]"
+        -
+          asm_text: "pli [r5, r2]"
+        -
+          asm_text: "pli [r0, r2, lsl #3]"
+        -
+          asm_text: "pli [r8, r2, lsl #2]"
+        -
+          asm_text: "pli [sp, r2, lsl #1]"
+        -
+          asm_text: "pli [sp, r2]"
+        -
+          asm_text: "pli [sp, r2, lsl #1]"
+        -
+          asm_text: "pop.w {r2, r9}"
+        -
+          asm_text: "push.w {r2, r9}"
+        -
+          asm_text: "qadd r1, r2, r3"
+        -
+          asm_text: "qadd16 r1, r2, r3"
+        -
+          asm_text: "qadd8 r1, r2, r3"
+        -
+          asm_text: "itte gt"
+        -
+          asm_text: "qaddgt r1, r2, r3"
+        -
+          asm_text: "qadd16gt r1, r2, r3"
+        -
+          asm_text: "qadd8le r1, r2, r3"
+        -
+          asm_text: "qdadd r6, r7, r8"
+        -
+          asm_text: "qdsub r6, r7, r8"
+        -
+          asm_text: "itt hi"
+        -
+          asm_text: "qdaddhi r6, r7, r8"
+        -
+          asm_text: "qdsubhi r6, r7, r8"
+        -
+          asm_text: "qsax r9, r12, r0"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "qsaxeq r9, r12, r0"
+        -
+          asm_text: "qsub r1, r2, r3"
+        -
+          asm_text: "qsub16 r1, r2, r3"
+        -
+          asm_text: "qsub8 r1, r2, r3"
+        -
+          asm_text: "itet le"
+        -
+          asm_text: "qsuble r1, r2, r3"
+        -
+          asm_text: "qsub16gt r1, r2, r3"
+        -
+          asm_text: "qsub8le r1, r2, r3"
+        -
+          asm_text: "rbit r1, r2"
+        -
+          asm_text: "it ne"
+        -
+          asm_text: "rbitne r1, r2"
+        -
+          asm_text: "rev.w r1, r2"
+        -
+          asm_text: "rev.w r2, r8"
+        -
+          asm_text: "itt ne"
+        -
+          asm_text: "revne r1, r2"
+        -
+          asm_text: "revne.w r1, r8"
+        -
+          asm_text: "rev16.w r1, r2"
+        -
+          asm_text: "rev16.w r2, r8"
+        -
+          asm_text: "itt ne"
+        -
+          asm_text: "rev16ne r1, r2"
+        -
+          asm_text: "rev16ne.w r1, r8"
+        -
+          asm_text: "revsh.w r1, r2"
+        -
+          asm_text: "revsh.w r2, r8"
+        -
+          asm_text: "itt ne"
+        -
+          asm_text: "revshne r1, r2"
+        -
+          asm_text: "revshne.w r1, r8"
+        -
+          asm_text: "ror.w r2, r3, #0xc"
+        -
+          asm_text: "rors.w r8, r3, #0x1f"
+        -
+          asm_text: "rors.w r2, r3, #1"
+        -
+          asm_text: "ror.w r2, r3, #4"
+        -
+          asm_text: "rors.w r2, r12, #0xf"
+        -
+          asm_text: "ror.w r3, r3, #0x13"
+        -
+          asm_text: "rors.w r8, r8, #2"
+        -
+          asm_text: "rors.w r7, r7, #5"
+        -
+          asm_text: "ror.w r12, r12, #0x15"
+        -
+          asm_text: "ror.w r3, r4, r2"
+        -
+          asm_text: "ror.w r1, r1, r2"
+        -
+          asm_text: "rors.w r3, r4, r8"
+        -
+          asm_text: "rrx r1, r2"
+        -
+          asm_text: "rrxs r1, r2"
+        -
+          asm_text: "ite lt"
+        -
+          asm_text: "rrxlt r9, r12"
+        -
+          asm_text: "rrxsge r8, r3"
+        -
+          asm_text: "rsb.w r2, r5, #0xff000"
+        -
+          asm_text: "rsbs.w r3, r12, #0xf"
+        -
+          asm_text: "rsb.w r1, r1, #0xff"
+        -
+          asm_text: "rsb.w r1, r1, #0xff"
+        -
+          asm_text: "rsb.w r11, r11, #0"
+        -
+          asm_text: "rsb.w r9, r9, #0"
+        -
+          asm_text: "rsbs r3, r1, #0"
+        -
+          asm_text: "rsb.w r3, r1, #0"
+        -
+          asm_text: "rsb r4, r4, r8"
+        -
+          asm_text: "rsb r4, r4, r8"
+        -
+          asm_text: "rsb r4, r9, r8"
+        -
+          asm_text: "rsb r4, r9, r8"
+        -
+          asm_text: "rsb r1, r4, r8, asr #3"
+        -
+          asm_text: "rsb r1, r4, r8, asr #3"
+        -
+          asm_text: "rsbs r2, r1, r7, lsl #1"
+        -
+          asm_text: "rsbs r2, r1, r7, lsl #1"
+        -
+          asm_text: "rsbs r0, r1, r2"
+        -
+          asm_text: "rsbs r0, r1, r2"
+        -
+          asm_text: "sadd16 r3, r4, r8"
+        -
+          asm_text: "it ne"
+        -
+          asm_text: "sadd16ne r3, r4, r8"
+        -
+          asm_text: "sadd8 r3, r4, r8"
+        -
+          asm_text: "it ne"
+        -
+          asm_text: "sadd8ne r3, r4, r8"
+        -
+          asm_text: "sasx r9, r2, r7"
+        -
+          asm_text: "it ne"
+        -
+          asm_text: "sasxne r2, r5, r6"
+        -
+          asm_text: "sasx r9, r2, r7"
+        -
+          asm_text: "it ne"
+        -
+          asm_text: "sasxne r2, r5, r6"
+        -
+          asm_text: "sbc r0, r1, #4"
+        -
+          asm_text: "sbcs r0, r1, #0"
+        -
+          asm_text: "sbc r1, r2, #0xff"
+        -
+          asm_text: "sbc r3, r7, #0x550055"
+        -
+          asm_text: "sbc r8, r12, #0xaa00aa00"
+        -
+          asm_text: "sbc r9, r7, #0xa5a5a5a5"
+        -
+          asm_text: "sbc r5, r3, #0x87000000"
+        -
+          asm_text: "sbc r4, r2, #0x7f800000"
+        -
+          asm_text: "sbc r4, r2, #0x680"
+        -
+          asm_text: "sbc.w r4, r5, r6"
+        -
+          asm_text: "sbcs.w r4, r5, r6"
+        -
+          asm_text: "sbc.w r9, r1, r3"
+        -
+          asm_text: "sbcs.w r9, r1, r3"
+        -
+          asm_text: "sbc.w r0, r1, r3, ror #4"
+        -
+          asm_text: "sbcs.w r0, r1, r3, lsl #7"
+        -
+          asm_text: "sbc.w r0, r1, r3, lsr #0x1f"
+        -
+          asm_text: "sbcs.w r0, r1, r3, asr #0x20"
+        -
+          asm_text: "sbfx r4, r5, #0x10, #1"
+        -
+          asm_text: "it gt"
+        -
+          asm_text: "sbfxgt r4, r5, #0x10, #0x10"
+        -
+          asm_text: "sel r5, r9, r2"
+        -
+          asm_text: "it le"
+        -
+          asm_text: "selle r5, r9, r2"
+        -
+          asm_text: "sev.w"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "seveq.w"
+        -
+          asm_text: "sadd16 r1, r2, r3"
+        -
+          asm_text: "sadd8 r1, r2, r3"
+        -
+          asm_text: "ite gt"
+        -
+          asm_text: "sadd16gt r1, r2, r3"
+        -
+          asm_text: "sadd8le r1, r2, r3"
+        -
+          asm_text: "shasx r4, r8, r2"
+        -
+          asm_text: "it gt"
+        -
+          asm_text: "shasxgt r4, r8, r2"
+        -
+          asm_text: "shasx r4, r8, r2"
+        -
+          asm_text: "it gt"
+        -
+          asm_text: "shasxgt r4, r8, r2"
+        -
+          asm_text: "shsax r4, r8, r2"
+        -
+          asm_text: "it gt"
+        -
+          asm_text: "shsaxgt r4, r8, r2"
+        -
+          asm_text: "shsax r4, r8, r2"
+        -
+          asm_text: "it gt"
+        -
+          asm_text: "shsaxgt r4, r8, r2"
+        -
+          asm_text: "shsub16 r4, r8, r2"
+        -
+          asm_text: "shsub8 r4, r8, r2"
+        -
+          asm_text: "itt gt"
+        -
+          asm_text: "shsub16gt r4, r8, r2"
+        -
+          asm_text: "shsub8gt r4, r8, r2"
+        -
+          asm_text: "smlabb r3, r1, r9, r0"
+        -
+          asm_text: "smlabt r5, r6, r4, r1"
+        -
+          asm_text: "smlatb r4, r2, r3, r2"
+        -
+          asm_text: "smlatt r8, r3, r8, r4"
+        -
+          asm_text: "itete gt"
+        -
+          asm_text: "smlabbgt r3, r1, r9, r0"
+        -
+          asm_text: "smlabtle r5, r6, r4, r1"
+        -
+          asm_text: "smlatbgt r4, r2, r3, r2"
+        -
+          asm_text: "smlattle r8, r3, r8, r4"
+        -
+          asm_text: "smlad r2, r3, r5, r8"
+        -
+          asm_text: "smladx r2, r3, r5, r8"
+        -
+          asm_text: "itt hi"
+        -
+          asm_text: "smladhi r2, r3, r5, r8"
+        -
+          asm_text: "smladxhi r2, r3, r5, r8"
+        -
+          asm_text: "smlal r2, r3, r5, r8"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "smlaleq r2, r3, r5, r8"
+        -
+          asm_text: "smlalbb r3, r1, r9, r0"
+        -
+          asm_text: "smlalbt r5, r6, r4, r1"
+        -
+          asm_text: "smlaltb r4, r2, r3, r2"
+        -
+          asm_text: "smlaltt r8, r3, r8, r4"
+        -
+          asm_text: "iteet ge"
+        -
+          asm_text: "smlalbbge r3, r1, r9, r0"
+        -
+          asm_text: "smlalbtlt r5, r6, r4, r1"
+        -
+          asm_text: "smlaltblt r4, r2, r3, r2"
+        -
+          asm_text: "smlalttge r8, r3, r8, r4"
+        -
+          asm_text: "smlald r2, r3, r5, r8"
+        -
+          asm_text: "smlaldx r2, r3, r5, r8"
+        -
+          asm_text: "ite eq"
+        -
+          asm_text: "smlaldeq r2, r3, r5, r8"
+        -
+          asm_text: "smlaldxne r2, r3, r5, r8"
+        -
+          asm_text: "smlawb r2, r3, r10, r8"
+        -
+          asm_text: "smlawt r8, r3, r5, r9"
+        -
+          asm_text: "ite eq"
+        -
+          asm_text: "smlawbeq r2, r7, r5, r8"
+        -
+          asm_text: "smlawtne r1, r3, r0, r8"
+        -
+          asm_text: "smlsd r2, r3, r5, r8"
+        -
+          asm_text: "smlsdx r2, r3, r5, r8"
+        -
+          asm_text: "ite le"
+        -
+          asm_text: "smlsdle r2, r3, r5, r8"
+        -
+          asm_text: "smlsdxgt r2, r3, r5, r8"
+        -
+          asm_text: "smlsld r2, r9, r5, r1"
+        -
+          asm_text: "smlsldx r4, r11, r2, r8"
+        -
+          asm_text: "ite ge"
+        -
+          asm_text: "smlsldge r8, r2, r5, r6"
+        -
+          asm_text: "smlsldxlt r1, r0, r3, r8"
+        -
+          asm_text: "smmla r1, r2, r3, r4"
+        -
+          asm_text: "smmlar r4, r3, r2, r1"
+        -
+          asm_text: "ite lo"
+        -
+          asm_text: "smmlalo r1, r2, r3, r4"
+        -
+          asm_text: "smmlarhs r4, r3, r2, r1"
+        -
+          asm_text: "smmls r1, r2, r3, r4"
+        -
+          asm_text: "smmlsr r4, r3, r2, r1"
+        -
+          asm_text: "ite lo"
+        -
+          asm_text: "smmlslo r1, r2, r3, r4"
+        -
+          asm_text: "smmlsrhs r4, r3, r2, r1"
+        -
+          asm_text: "smmul r2, r3, r4"
+        -
+          asm_text: "smmulr r3, r2, r1"
+        -
+          asm_text: "ite lo"
+        -
+          asm_text: "smmullo r2, r3, r4"
+        -
+          asm_text: "smmulrhs r3, r2, r1"
+        -
+          asm_text: "smuad r2, r3, r4"
+        -
+          asm_text: "smuadx r3, r2, r1"
+        -
+          asm_text: "ite lt"
+        -
+          asm_text: "smuadlt r2, r3, r4"
+        -
+          asm_text: "smuadxge r3, r2, r1"
+        -
+          asm_text: "smulbb r3, r9, r0"
+        -
+          asm_text: "smulbt r5, r4, r1"
+        -
+          asm_text: "smultb r4, r2, r2"
+        -
+          asm_text: "smultt r8, r3, r4"
+        -
+          asm_text: "itete ge"
+        -
+          asm_text: "smulbbge r1, r9, r0"
+        -
+          asm_text: "smulbtlt r5, r6, r4"
+        -
+          asm_text: "smultbge r2, r3, r2"
+        -
+          asm_text: "smulttlt r8, r3, r4"
+        -
+          asm_text: "smull r3, r9, r0, r1"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "smulleq r8, r3, r4, r5"
+        -
+          asm_text: "smulwb r3, r9, r0"
+        -
+          asm_text: "smulwt r3, r9, r2"
+        -
+          asm_text: "ite gt"
+        -
+          asm_text: "smulwbgt r3, r9, r0"
+        -
+          asm_text: "smulwtle r3, r9, r2"
+        -
+          asm_text: "smusd r3, r0, r1"
+        -
+          asm_text: "smusdx r3, r9, r2"
+        -
+          asm_text: "ite eq"
+        -
+          asm_text: "smusdeq r8, r3, r2"
+        -
+          asm_text: "smusdxne r7, r4, r3"
+        -
+          asm_text: "srsdb sp, #1"
+        -
+          asm_text: "srsia sp, #0"
+        -
+          asm_text: "srsdb sp!, #0x13"
+        -
+          asm_text: "srsia sp!, #2"
+        -
+          asm_text: "srsia sp, #0xa"
+        -
+          asm_text: "srsdb sp, #0x9"
+        -
+          asm_text: "srsia sp!, #5"
+        -
+          asm_text: "srsdb sp!, #5"
+        -
+          asm_text: "srsia sp, #5"
+        -
+          asm_text: "srsia sp!, #5"
+        -
+          asm_text: "srsdb sp, #1"
+        -
+          asm_text: "srsia sp, #0"
+        -
+          asm_text: "srsdb sp!, #0x13"
+        -
+          asm_text: "srsia sp!, #2"
+        -
+          asm_text: "srsia sp, #0xa"
+        -
+          asm_text: "srsdb sp, #0x9"
+        -
+          asm_text: "srsia sp!, #5"
+        -
+          asm_text: "srsdb sp!, #5"
+        -
+          asm_text: "srsia sp, #5"
+        -
+          asm_text: "srsia sp!, #5"
+        -
+          asm_text: "ssat r8, #1, r10"
+        -
+          asm_text: "ssat r8, #1, r10"
+        -
+          asm_text: "ssat r8, #1, r10, lsl #0x1f"
+        -
+          asm_text: "ssat r8, #1, r10, asr #1"
+        -
+          asm_text: "ssat16 r2, #1, r7"
+        -
+          asm_text: "ssat16 r3, #0x10, r5"
+        -
+          asm_text: "ssax r2, r3, r4"
+        -
+          asm_text: "it lt"
+        -
+          asm_text: "ssaxlt r2, r3, r4"
+        -
+          asm_text: "ssax r2, r3, r4"
+        -
+          asm_text: "it lt"
+        -
+          asm_text: "ssaxlt r2, r3, r4"
+        -
+          asm_text: "ssub16 r1, r0, r6"
+        -
+          asm_text: "ssub8 r9, r2, r4"
+        -
+          asm_text: "ite ne"
+        -
+          asm_text: "ssub16ne r5, r3, r2"
+        -
+          asm_text: "ssub8eq r5, r1, r2"
+        -
+          asm_text: "stc2 p0, c8, [r1, #4]"
+        -
+          asm_text: "stc2 p1, c7, [r2]"
+        -
+          asm_text: "stc2 p2, c6, [r3, #-0xe0]"
+        -
+          asm_text: "stc2 p3, c5, [r4, #-0x78]!"
+        -
+          asm_text: "stc2 p4, c4, [r5], #0x10"
+        -
+          asm_text: "stc2 p5, c3, [r6], #-0x48"
+        -
+          asm_text: "stc2l p6, c2, [r7, #4]"
+        -
+          asm_text: "stc2l p7, c1, [r8]"
+        -
+          asm_text: "stc2l p8, c0, [r9, #-0xe0]"
+        -
+          asm_text: "stc2l p9, c1, [r10, #-0x78]!"
+        -
+          asm_text: "stc2l p0, c2, [r11], #0x10"
+        -
+          asm_text: "stc2l p1, c3, [r12], #-0x48"
+        -
+          asm_text: "stc p12, c4, [r0, #4]"
+        -
+          asm_text: "stc p13, c5, [r1]"
+        -
+          asm_text: "stc p14, c6, [r2, #-0xe0]"
+        -
+          asm_text: "stc p15, c7, [r3, #-0x78]!"
+        -
+          asm_text: "stc p5, c8, [r4], #0x10"
+        -
+          asm_text: "stc p4, c9, [r5], #-0x48"
+        -
+          asm_text: "stcl p3, c10, [r6, #4]"
+        -
+          asm_text: "stcl p2, c11, [r7]"
+        -
+          asm_text: "stcl p1, c12, [r8, #-0xe0]"
+        -
+          asm_text: "stcl p0, c13, [r9, #-0x78]!"
+        -
+          asm_text: "stcl p6, c14, [r10], #0x10"
+        -
+          asm_text: "stcl p7, c15, [r11], #-0x48"
+        -
+          asm_text: "stc2 p2, c8, [r1], {25}"
+        -
+          asm_text: "stm.w r4, {r4, r5, r8, r9}"
+        -
+          asm_text: "stm.w r4, {r5, r6}"
+        -
+          asm_text: "stm.w r5!, {r3, r8}"
+        -
+          asm_text: "stm.w r4, {r4, r5, r8, r9}"
+        -
+          asm_text: "stm.w r4, {r5, r6}"
+        -
+          asm_text: "stm.w r5!, {r3, r8}"
+        -
+          asm_text: "stm.w r5!, {r1, r2}"
+        -
+          asm_text: "stm.w r2, {r1, r2}"
+        -
+          asm_text: "stm.w r4, {r4, r5, r8, r9}"
+        -
+          asm_text: "stm.w r4, {r5, r6}"
+        -
+          asm_text: "stm.w r5!, {r3, r8}"
+        -
+          asm_text: "stm.w r4, {r4, r5, r8, r9}"
+        -
+          asm_text: "stm.w r4, {r5, r6}"
+        -
+          asm_text: "stm.w r5!, {r3, r8}"
+        -
+          asm_text: "stm.w r5!, {r3, r8}"
+        -
+          asm_text: "stmdb r4, {r4, r5, r8, r9}"
+        -
+          asm_text: "stmdb r4, {r5, r6}"
+        -
+          asm_text: "stmdb r5!, {r3, r8}"
+        -
+          asm_text: "stm.w r5!, {r3, r8}"
+        -
+          asm_text: "stmdb r5, {r0, r1}"
+        -
+          asm_text: "str r5, [r5, #-4]"
+        -
+          asm_text: "str r5, [r6, #0x20]"
+        -
+          asm_text: "str.w r5, [r6, #0x21]"
+        -
+          asm_text: "str.w r5, [r6, #0x101]"
+        -
+          asm_text: "str.w pc, [r7, #0x101]"
+        -
+          asm_text: "str r2, [r4, #0xff]!"
+        -
+          asm_text: "str r8, [sp, #4]!"
+        -
+          asm_text: "str lr, [sp, #-4]!"
+        -
+          asm_text: "str r2, [r4], #0xff"
+        -
+          asm_text: "str r8, [sp], #4"
+        -
+          asm_text: "str lr, [sp], #-4"
+        -
+          asm_text: "str.w r1, [r8, r1]"
+        -
+          asm_text: "str.w r4, [r5, r2]"
+        -
+          asm_text: "str.w r6, [r0, r2, lsl #3]"
+        -
+          asm_text: "str.w r8, [r8, r2, lsl #2]"
+        -
+          asm_text: "str.w r7, [sp, r2, lsl #1]"
+        -
+          asm_text: "str.w r7, [sp, r2]"
+        -
+          asm_text: "strb r5, [r5, #-4]"
+        -
+          asm_text: "strb.w r5, [r6, #0x20]"
+        -
+          asm_text: "strb.w r5, [r6, #0x21]"
+        -
+          asm_text: "strb.w r5, [r6, #0x101]"
+        -
+          asm_text: "strb.w lr, [r7, #0x101]"
+        -
+          asm_text: "strb r5, [r8, #0xff]!"
+        -
+          asm_text: "strb r2, [r5, #4]!"
+        -
+          asm_text: "strb r1, [r4, #-4]!"
+        -
+          asm_text: "strb lr, [r3], #0xff"
+        -
+          asm_text: "strb r9, [r2], #4"
+        -
+          asm_text: "strb r3, [sp], #-4"
+        -
+          asm_text: "strb r4, [r8, #-0]!"
+        -
+          asm_text: "strb r1, [r0], #-0"
+        -
+          asm_text: "strb.w r1, [r8, r1]"
+        -
+          asm_text: "strb.w r4, [r5, r2]"
+        -
+          asm_text: "strb.w r6, [r0, r2, lsl #3]"
+        -
+          asm_text: "strb.w r8, [r8, r2, lsl #2]"
+        -
+          asm_text: "strb.w r7, [sp, r2, lsl #1]"
+        -
+          asm_text: "strb.w r7, [sp, r2]"
+        -
+          asm_text: "strbt r1, [r2]"
+        -
+          asm_text: "strbt r1, [r8]"
+        -
+          asm_text: "strbt r1, [r8, #3]"
+        -
+          asm_text: "strbt r1, [r8, #0xff]"
+        -
+          asm_text: "strd r3, r5, [r6, #0x18]"
+        -
+          asm_text: "strd r3, r5, [r6, #0x18]!"
+        -
+          asm_text: "strd r3, r5, [r6], #4"
+        -
+          asm_text: "strd r3, r5, [r6], #-8"
+        -
+          asm_text: "strd r3, r5, [r6]"
+        -
+          asm_text: "strd r8, r1, [r3]"
+        -
+          asm_text: "strd r0, r1, [r2, #-0]"
+        -
+          asm_text: "strd r0, r1, [r2, #-0]!"
+        -
+          asm_text: "strd r0, r1, [r2], #-0"
+        -
+          asm_text: "strd r0, r1, [r2, #0x100]"
+        -
+          asm_text: "strd r0, r1, [r2, #0x100]!"
+        -
+          asm_text: "strd r0, r1, [r2], #0x100"
+        -
+          asm_text: "strex r1, r8, [r4]"
+        -
+          asm_text: "strex r8, r2, [r4]"
+        -
+          asm_text: "strex r2, r12, [sp, #0x80]"
+        -
+          asm_text: "strexb r5, r1, [r7]"
+        -
+          asm_text: "strexh r9, r7, [r12]"
+        -
+          asm_text: "strexd r9, r3, r6, [r4]"
+        -
+          asm_text: "strh r5, [r5, #-4]"
+        -
+          asm_text: "strh r5, [r6, #0x20]"
+        -
+          asm_text: "strh.w r5, [r6, #0x21]"
+        -
+          asm_text: "strh.w r5, [r6, #0x101]"
+        -
+          asm_text: "strh.w lr, [r7, #0x101]"
+        -
+          asm_text: "strh r5, [r8, #0xff]!"
+        -
+          asm_text: "strh r2, [r5, #4]!"
+        -
+          asm_text: "strh r1, [r4, #-4]!"
+        -
+          asm_text: "strh lr, [r3], #0xff"
+        -
+          asm_text: "strh r9, [r2], #4"
+        -
+          asm_text: "strh r3, [sp], #-4"
+        -
+          asm_text: "strh.w r1, [r8, r1]"
+        -
+          asm_text: "strh.w r4, [r5, r2]"
+        -
+          asm_text: "strh.w r6, [r0, r2, lsl #3]"
+        -
+          asm_text: "strh.w r8, [r8, r2, lsl #2]"
+        -
+          asm_text: "strh.w r7, [sp, r2, lsl #1]"
+        -
+          asm_text: "strh.w r7, [sp, r2]"
+        -
+          asm_text: "strht r1, [r2]"
+        -
+          asm_text: "strht r1, [r8]"
+        -
+          asm_text: "strht r1, [r8, #3]"
+        -
+          asm_text: "strht r1, [r8, #0xff]"
+        -
+          asm_text: "strt r1, [r2]"
+        -
+          asm_text: "strt r1, [r8]"
+        -
+          asm_text: "strt r1, [r8, #3]"
+        -
+          asm_text: "strt r1, [r8, #0xff]"
+        -
+          asm_text: "itet eq"
+        -
+          asm_text: "subeq r1, r2, #4"
+        -
+          asm_text: "subwne r5, r3, #0x3ff"
+        -
+          asm_text: "subweq r4, r5, #0x125"
+        -
+          asm_text: "sub.w r2, sp, #0x400"
+        -
+          asm_text: "sub.w r2, r8, #0xff00"
+        -
+          asm_text: "subw r2, r3, #0x101"
+        -
+          asm_text: "subw r2, r3, #0x101"
+        -
+          asm_text: "sub.w r12, r6, #0x100"
+        -
+          asm_text: "subw r12, r6, #0x100"
+        -
+          asm_text: "subs.w r1, r2, #0x1f0"
+        -
+          asm_text: "sub.w r2, r2, #1"
+        -
+          asm_text: "sub.w r0, r0, #0x20"
+        -
+          asm_text: "subs r2, #0x38"
+        -
+          asm_text: "subs r2, #0x38"
+        -
+          asm_text: "sub.w r4, r5, r6"
+        -
+          asm_text: "sub.w r4, r5, r6, lsl #5"
+        -
+          asm_text: "sub.w r4, r5, r6, lsr #5"
+        -
+          asm_text: "sub.w r4, r5, r6, lsr #5"
+        -
+          asm_text: "sub.w r4, r5, r6, asr #5"
+        -
+          asm_text: "sub.w r4, r5, r6, ror #5"
+        -
+          asm_text: "sub.w r5, r2, r12, rrx"
+        -
+          asm_text: "sub.w r2, sp, r12"
+        -
+          asm_text: "sub.w sp, sp, r12"
+        -
+          asm_text: "sub.w sp, sp, r12"
+        -
+          asm_text: "sub.w r2, sp, r12"
+        -
+          asm_text: "sub.w sp, sp, r12"
+        -
+          asm_text: "sub.w sp, sp, r12"
+        -
+          asm_text: "svc #0"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "svceq #0xff"
+        -
+          asm_text: "it ne"
+        -
+          asm_text: "svcne #0x21"
+        -
+          asm_text: "itt eq"
+        -
+          asm_text: "svceq #0"
+        -
+          asm_text: "svceq #1"
+        -
+          asm_text: "sxtab r2, r3, r4"
+        -
+          asm_text: "sxtab r4, r5, r6"
+        -
+          asm_text: "it lt"
+        -
+          asm_text: "sxtablt r6, r2, r9, ror #8"
+        -
+          asm_text: "sxtab r5, r1, r4, ror #0x10"
+        -
+          asm_text: "sxtab r7, r8, r3, ror #0x18"
+        -
+          asm_text: "sxtab16 r6, r2, r7"
+        -
+          asm_text: "sxtab16 r3, r5, r8, ror #8"
+        -
+          asm_text: "sxtab16 r3, r2, r1, ror #0x10"
+        -
+          asm_text: "ite ne"
+        -
+          asm_text: "sxtab16ne r0, r1, r4"
+        -
+          asm_text: "sxtab16eq r1, r2, r3, ror #0x18"
+        -
+          asm_text: "sxtah r1, r3, r9"
+        -
+          asm_text: "sxtah r3, r8, r3, ror #8"
+        -
+          asm_text: "sxtah r9, r3, r3, ror #0x18"
+        -
+          asm_text: "ite hi"
+        -
+          asm_text: "sxtahhi r6, r1, r6"
+        -
+          asm_text: "sxtahls r2, r2, r4, ror #0x10"
+        -
+          asm_text: "sxtb r5, r6"
+        -
+          asm_text: "sxtb.w r6, r9, ror #8"
+        -
+          asm_text: "sxtb.w r8, r3, ror #0x18"
+        -
+          asm_text: "ite ge"
+        -
+          asm_text: "sxtbge r2, r4"
+        -
+          asm_text: "sxtblt.w r5, r1, ror #0x10"
+        -
+          asm_text: "sxtb.w r7, r8"
+        -
+          asm_text: "sxtb16 r1, r4"
+        -
+          asm_text: "sxtb16 r6, r7"
+        -
+          asm_text: "sxtb16 r3, r1, ror #0x10"
+        -
+          asm_text: "ite hs"
+        -
+          asm_text: "sxtb16hs r3, r5, ror #8"
+        -
+          asm_text: "sxtb16lo r2, r3, ror #0x18"
+        -
+          asm_text: "sxth r1, r6"
+        -
+          asm_text: "sxth.w r3, r8, ror #8"
+        -
+          asm_text: "sxth.w r9, r3, ror #0x18"
+        -
+          asm_text: "itt ne"
+        -
+          asm_text: "sxthne.w r3, r9"
+        -
+          asm_text: "sxthne.w r2, r2, ror #0x10"
+        -
+          asm_text: "sxth.w r7, r8"
+        -
+          asm_text: "sxtb r5, r6"
+        -
+          asm_text: "sxtb.w r6, r9, ror #8"
+        -
+          asm_text: "sxtb.w r8, r3, ror #0x18"
+        -
+          asm_text: "ite ge"
+        -
+          asm_text: "sxtbge r2, r4"
+        -
+          asm_text: "sxtblt.w r5, r1, ror #0x10"
+        -
+          asm_text: "sxtb16 r1, r4"
+        -
+          asm_text: "sxtb16 r6, r7"
+        -
+          asm_text: "sxtb16 r3, r1, ror #0x10"
+        -
+          asm_text: "ite hs"
+        -
+          asm_text: "sxtb16hs r3, r5, ror #8"
+        -
+          asm_text: "sxtb16lo r2, r3, ror #0x18"
+        -
+          asm_text: "sxth r1, r6"
+        -
+          asm_text: "sxth.w r3, r8, ror #8"
+        -
+          asm_text: "sxth.w r9, r3, ror #0x18"
+        -
+          asm_text: "itt ne"
+        -
+          asm_text: "sxthne.w r3, r9"
+        -
+          asm_text: "sxthne.w r2, r2, ror #0x10"
+        -
+          asm_text: "tbb [r3, r8]"
+        -
+          asm_text: "tbh [r3, r8, lsl #1]"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "tbbeq [r3, r8]"
+        -
+          asm_text: "it hs"
+        -
+          asm_text: "tbhhs [r3, r8, lsl #1]"
+        -
+          asm_text: "teq.w r5, #0xf000"
+        -
+          asm_text: "teq.w r4, r5"
+        -
+          asm_text: "teq.w r4, r5, lsl #5"
+        -
+          asm_text: "teq.w r4, r5, lsr #5"
+        -
+          asm_text: "teq.w r4, r5, lsr #5"
+        -
+          asm_text: "teq.w r4, r5, asr #5"
+        -
+          asm_text: "teq.w r4, r5, ror #5"
+        -
+          asm_text: "tst.w r5, #0xf000"
+        -
+          asm_text: "tst r2, r5"
+        -
+          asm_text: "tst.w r3, r12, lsl #5"
+        -
+          asm_text: "tst.w r4, r11, lsr #4"
+        -
+          asm_text: "tst.w r5, r10, lsr #0xc"
+        -
+          asm_text: "tst.w r6, r9, asr #0x1e"
+        -
+          asm_text: "tst.w r7, r8, ror #2"
+        -
+          asm_text: "uadd16 r1, r2, r3"
+        -
+          asm_text: "uadd8 r1, r2, r3"
+        -
+          asm_text: "ite gt"
+        -
+          asm_text: "uadd16gt r1, r2, r3"
+        -
+          asm_text: "uadd8le r1, r2, r3"
+        -
+          asm_text: "uasx r9, r12, r0"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "uasxeq r9, r12, r0"
+        -
+          asm_text: "uasx r9, r12, r0"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "uasxeq r9, r12, r0"
+        -
+          asm_text: "ubfx r4, r5, #0x10, #1"
+        -
+          asm_text: "it gt"
+        -
+          asm_text: "ubfxgt r4, r5, #0x10, #0x10"
+        -
+          asm_text: "uhadd16 r4, r8, r2"
+        -
+          asm_text: "uhadd8 r4, r8, r2"
+        -
+          asm_text: "itt gt"
+        -
+          asm_text: "uhadd16gt r4, r8, r2"
+        -
+          asm_text: "uhadd8gt r4, r8, r2"
+        -
+          asm_text: "uhasx r4, r1, r5"
+        -
+          asm_text: "uhsax r5, r6, r6"
+        -
+          asm_text: "itt gt"
+        -
+          asm_text: "uhasxgt r6, r9, r8"
+        -
+          asm_text: "uhsaxgt r7, r8, r12"
+        -
+          asm_text: "uhasx r4, r1, r5"
+        -
+          asm_text: "uhsax r5, r6, r6"
+        -
+          asm_text: "itt gt"
+        -
+          asm_text: "uhasxgt r6, r9, r8"
+        -
+          asm_text: "uhsaxgt r7, r8, r12"
+        -
+          asm_text: "uhsub16 r5, r8, r3"
+        -
+          asm_text: "uhsub8 r1, r7, r6"
+        -
+          asm_text: "itt lt"
+        -
+          asm_text: "uhsub16lt r4, r9, r12"
+        -
+          asm_text: "uhsub8lt r3, r1, r5"
+        -
+          asm_text: "umaal r3, r4, r5, r6"
+        -
+          asm_text: "it lt"
+        -
+          asm_text: "umaallt r3, r4, r5, r6"
+        -
+          asm_text: "umlal r2, r4, r6, r8"
+        -
+          asm_text: "it gt"
+        -
+          asm_text: "umlalgt r6, r1, r2, r6"
+        -
+          asm_text: "umull r2, r4, r6, r8"
+        -
+          asm_text: "it gt"
+        -
+          asm_text: "umullgt r6, r1, r2, r6"
+        -
+          asm_text: "uqadd16 r1, r2, r3"
+        -
+          asm_text: "uqadd8 r3, r4, r8"
+        -
+          asm_text: "ite gt"
+        -
+          asm_text: "uqadd16gt r4, r7, r9"
+        -
+          asm_text: "uqadd8le r8, r1, r2"
+        -
+          asm_text: "uqasx r1, r2, r3"
+        -
+          asm_text: "uqsax r3, r4, r8"
+        -
+          asm_text: "ite gt"
+        -
+          asm_text: "uqasxgt r4, r7, r9"
+        -
+          asm_text: "uqsaxle r8, r1, r2"
+        -
+          asm_text: "uqasx r1, r2, r3"
+        -
+          asm_text: "uqsax r3, r4, r8"
+        -
+          asm_text: "ite gt"
+        -
+          asm_text: "uqasxgt r4, r7, r9"
+        -
+          asm_text: "uqsaxle r8, r1, r2"
+        -
+          asm_text: "uqsub8 r8, r2, r9"
+        -
+          asm_text: "uqsub16 r1, r9, r7"
+        -
+          asm_text: "ite gt"
+        -
+          asm_text: "uqsub8gt r3, r1, r6"
+        -
+          asm_text: "uqsub16le r4, r6, r4"
+        -
+          asm_text: "usad8 r1, r9, r7"
+        -
+          asm_text: "usada8 r8, r2, r9, r12"
+        -
+          asm_text: "ite gt"
+        -
+          asm_text: "usada8gt r3, r1, r6, r9"
+        -
+          asm_text: "usad8le r4, r6, r4"
+        -
+          asm_text: "usat r8, #1, r10"
+        -
+          asm_text: "usat r8, #4, r10"
+        -
+          asm_text: "usat r8, #5, r10, lsl #0x1f"
+        -
+          asm_text: "usat r8, #0x10, r10, asr #1"
+        -
+          asm_text: "usat16 r2, #2, r7"
+        -
+          asm_text: "usat16 r3, #0xf, r5"
+        -
+          asm_text: "usax r2, r3, r4"
+        -
+          asm_text: "it ne"
+        -
+          asm_text: "usaxne r6, r1, r9"
+        -
+          asm_text: "usax r2, r3, r4"
+        -
+          asm_text: "it ne"
+        -
+          asm_text: "usaxne r6, r1, r9"
+        -
+          asm_text: "usub16 r4, r2, r7"
+        -
+          asm_text: "usub8 r1, r8, r5"
+        -
+          asm_text: "ite hi"
+        -
+          asm_text: "usub16hi r1, r1, r3"
+        -
+          asm_text: "usub8ls r9, r2, r3"
+        -
+          asm_text: "uxtab r2, r3, r4"
+        -
+          asm_text: "uxtab r4, r5, r6"
+        -
+          asm_text: "it lt"
+        -
+          asm_text: "uxtablt r6, r2, r9, ror #8"
+        -
+          asm_text: "uxtab r5, r1, r4, ror #0x10"
+        -
+          asm_text: "uxtab r7, r8, r3, ror #0x18"
+        -
+          asm_text: "it ge"
+        -
+          asm_text: "uxtab16ge r0, r1, r4"
+        -
+          asm_text: "uxtab16 r6, r2, r7"
+        -
+          asm_text: "uxtab16 r3, r5, r8, ror #8"
+        -
+          asm_text: "uxtab16 r3, r2, r1, ror #0x10"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "uxtab16eq r1, r2, r3, ror #0x18"
+        -
+          asm_text: "uxtah r1, r3, r9"
+        -
+          asm_text: "it hi"
+        -
+          asm_text: "uxtahhi r6, r1, r6"
+        -
+          asm_text: "uxtah r3, r8, r3, ror #8"
+        -
+          asm_text: "it lo"
+        -
+          asm_text: "uxtahlo r2, r2, r4, ror #0x10"
+        -
+          asm_text: "uxtah r9, r3, r3, ror #0x18"
+        -
+          asm_text: "it ge"
+        -
+          asm_text: "uxtbge r2, r4"
+        -
+          asm_text: "uxtb r5, r6"
+        -
+          asm_text: "uxtb.w r6, r9, ror #8"
+        -
+          asm_text: "it lo"
+        -
+          asm_text: "uxtblo.w r5, r1, ror #0x10"
+        -
+          asm_text: "uxtb.w r8, r3, ror #0x18"
+        -
+          asm_text: "uxtb.w r7, r8"
+        -
+          asm_text: "uxtb16 r1, r4"
+        -
+          asm_text: "uxtb16 r6, r7"
+        -
+          asm_text: "it hs"
+        -
+          asm_text: "uxtb16hs r3, r5, ror #8"
+        -
+          asm_text: "uxtb16 r3, r1, ror #0x10"
+        -
+          asm_text: "it ge"
+        -
+          asm_text: "uxtb16ge r2, r3, ror #0x18"
+        -
+          asm_text: "it ne"
+        -
+          asm_text: "uxthne.w r3, r9"
+        -
+          asm_text: "uxth r1, r6"
+        -
+          asm_text: "uxth.w r3, r8, ror #8"
+        -
+          asm_text: "it le"
+        -
+          asm_text: "uxthle.w r2, r2, ror #0x10"
+        -
+          asm_text: "uxth.w r9, r3, ror #0x18"
+        -
+          asm_text: "uxth.w r7, r8"
+        -
+          asm_text: "wfe"
+        -
+          asm_text: "wfi"
+        -
+          asm_text: "yield"
+        -
+          asm_text: "itet lt"
+        -
+          asm_text: "wfelt"
+        -
+          asm_text: "wfige"
+        -
+          asm_text: "yieldlt"
+        -
+          asm_text: "sev.w"
+        -
+          asm_text: "wfi.w"
+        -
+          asm_text: "wfe.w"
+        -
+          asm_text: "yield.w"
+        -
+          asm_text: "nop.w"
+        -
+          asm_text: "sev"
+        -
+          asm_text: "wfi"
+        -
+          asm_text: "wfe"
+        -
+          asm_text: "yield"
+        -
+          asm_text: "nop"
+        -
+          asm_text: "itet lt"
+        -
+          asm_text: "hintlt #0xf"
+        -
+          asm_text: "hintge.w #0x10"
+        -
+          asm_text: "hintlt.w #0xef"
+        -
+          asm_text: "hint #7"
+        -
+          asm_text: "hint.w #7"
+        -
+          asm_text: "ldrb.w r11, [pc, #0x16]"
+        -
+          asm_text: "ldrh.w r11, [pc, #0x16]"
+        -
+          asm_text: "ldrsb.w r11, [pc, #0x16]"
+        -
+          asm_text: "ldrsh.w r11, [pc, #0x16]"
+        -
+          asm_text: "ldr.w r11, [pc, #0x16]"
+        -
+          asm_text: "ldrb.w r11, [pc, #0x16]"
+        -
+          asm_text: "ldrh.w r11, [pc, #0x16]"
+        -
+          asm_text: "ldrsb.w r11, [pc, #0x16]"
+        -
+          asm_text: "ldrsh.w r11, [pc, #0x16]"
+        -
+          asm_text: "ldr.w r11, [pc, #-0x16]"
+        -
+          asm_text: "ldrb.w r11, [pc, #-0x16]"
+        -
+          asm_text: "ldrh.w r11, [pc, #-0x16]"
+        -
+          asm_text: "ldrsb.w r11, [pc, #-0x16]"
+        -
+          asm_text: "ldrsh.w r11, [pc, #-0x16]"
+        -
+          asm_text: "ldr.w r11, [pc, #-0x16]"
+        -
+          asm_text: "ldrb.w r11, [pc, #-0x16]"
+        -
+          asm_text: "ldrh.w r11, [pc, #-0x16]"
+        -
+          asm_text: "ldrsb.w r11, [pc, #-0x16]"
+        -
+          asm_text: "ldrsh.w r11, [pc, #-0x16]"
+        -
+          asm_text: "ldr r1, [pc, #0xc]"
+        -
+          asm_text: "subs pc, lr, #4"
diff --git a/tests/MC/ARM/bfloat16-a32.s.yaml b/tests/MC/ARM/bfloat16-a32.s.yaml
new file mode 100644
index 000000000..4acde4f85
--- /dev/null
+++ b/tests/MC/ARM/bfloat16-a32.s.yaml
@@ -0,0 +1,10 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x05, 0x3d, 0x04, 0xfc ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ]
+    expected:
+      insns:
+        -
+          asm_text: "vdot.bf16 d3, d4, d5"
diff --git a/tests/MC/ARM/bfloat16-t32.s.yaml b/tests/MC/ARM/bfloat16-t32.s.yaml
new file mode 100644
index 000000000..08354ff3d
--- /dev/null
+++ b/tests/MC/ARM/bfloat16-t32.s.yaml
@@ -0,0 +1,14 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xb6, 0xff, 0x46, 0x16, 0x18, 0xbf, 0xf3, 0xee, 0xe1, 0x09 ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvt.bf16.f32 d1, q3"
+        -
+          asm_text: "it ne"
+        -
+          asm_text: "vcvtt.bf16.f32 s1, s3"
diff --git a/tests/MC/ARM/cde-integer.s.yaml b/tests/MC/ARM/cde-integer.s.yaml
new file mode 100644
index 000000000..2a9016b4b
--- /dev/null
+++ b/tests/MC/ARM/cde-integer.s.yaml
@@ -0,0 +1,10 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x06, 0xbf ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ]
+    expected:
+      insns:
+        -
+          asm_text: "itte eq"
diff --git a/tests/MC/ARM/cde-vec-pred.s.yaml b/tests/MC/ARM/cde-vec-pred.s.yaml
new file mode 100644
index 000000000..79161f7fd
--- /dev/null
+++ b/tests/MC/ARM/cde-vec-pred.s.yaml
@@ -0,0 +1,10 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x41, 0xfe, 0x00, 0xef ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_MCLASS", "CS_MODE_V8", "CS_MODE_THUMB" ]
+    expected:
+      insns:
+        -
+          asm_text: "vptete.i8 eq, q0, q0"
diff --git a/tests/MC/ARM/clrm-asm.s.yaml b/tests/MC/ARM/clrm-asm.s.yaml
new file mode 100644
index 000000000..3f07e55a7
--- /dev/null
+++ b/tests/MC/ARM/clrm-asm.s.yaml
@@ -0,0 +1,20 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x9f, 0xe8, 0x0f, 0x00, 0x9f, 0xe8, 0x1e, 0x00, 0x9f, 0xe8, 0xff, 0xdf, 0x9f, 0xe8, 0x00, 0xc0, 0x9f, 0xe8, 0x03, 0x80, 0x9f, 0xe8, 0x1f, 0xc0 ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_V8", "CS_MODE_THUMB" ]
+    expected:
+      insns:
+        -
+          asm_text: "clrm {r0, r1, r2, r3}"
+        -
+          asm_text: "clrm {r1, r2, r3, r4}"
+        -
+          asm_text: "clrm {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, lr, apsr}"
+        -
+          asm_text: "clrm {lr, apsr}"
+        -
+          asm_text: "clrm {r0, r1, apsr}"
+        -
+          asm_text: "clrm {r0, r1, r2, r3, r4, lr, apsr}"
diff --git a/tests/MC/ARM/cps.s.yaml b/tests/MC/ARM/cps.s.yaml
new file mode 100644
index 000000000..0ea21d963
--- /dev/null
+++ b/tests/MC/ARM/cps.s.yaml
@@ -0,0 +1,14 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x61, 0xb6, 0xaf, 0xf3, 0x43, 0x85, 0xaf, 0xf3, 0x00, 0x81 ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ]
+    expected:
+      insns:
+        -
+          asm_text: "cpsie f"
+        -
+          asm_text: "cpsie i, #3"
+        -
+          asm_text: "cps #0"
diff --git a/tests/MC/ARM/crc32-thumb.s.yaml b/tests/MC/ARM/crc32-thumb.s.yaml
new file mode 100644
index 000000000..782489e32
--- /dev/null
+++ b/tests/MC/ARM/crc32-thumb.s.yaml
@@ -0,0 +1,20 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xc1, 0xfa, 0x82, 0xf0, 0xc1, 0xfa, 0x92, 0xf0, 0xc1, 0xfa, 0xa2, 0xf0, 0xd1, 0xfa, 0x82, 0xf0, 0xd1, 0xfa, 0x92, 0xf0, 0xd1, 0xfa, 0xa2, 0xf0 ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_V8", "CS_MODE_THUMB" ]
+    expected:
+      insns:
+        -
+          asm_text: "crc32b r0, r1, r2"
+        -
+          asm_text: "crc32h r0, r1, r2"
+        -
+          asm_text: "crc32w r0, r1, r2"
+        -
+          asm_text: "crc32cb r0, r1, r2"
+        -
+          asm_text: "crc32ch r0, r1, r2"
+        -
+          asm_text: "crc32cw r0, r1, r2"
diff --git a/tests/MC/ARM/crc32.s.yaml b/tests/MC/ARM/crc32.s.yaml
new file mode 100644
index 000000000..4b630d1c9
--- /dev/null
+++ b/tests/MC/ARM/crc32.s.yaml
@@ -0,0 +1,20 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x42, 0x00, 0x01, 0xe1, 0x42, 0x00, 0x21, 0xe1, 0x42, 0x00, 0x41, 0xe1, 0x42, 0x02, 0x01, 0xe1, 0x42, 0x02, 0x21, 0xe1, 0x42, 0x02, 0x41, 0xe1 ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_V8", "CS_MODE_ARM" ]
+    expected:
+      insns:
+        -
+          asm_text: "crc32b r0, r1, r2"
+        -
+          asm_text: "crc32h r0, r1, r2"
+        -
+          asm_text: "crc32w r0, r1, r2"
+        -
+          asm_text: "crc32cb r0, r1, r2"
+        -
+          asm_text: "crc32ch r0, r1, r2"
+        -
+          asm_text: "crc32cw r0, r1, r2"
diff --git a/tests/MC/ARM/dot-req.s.yaml b/tests/MC/ARM/dot-req.s.yaml
new file mode 100644
index 000000000..f9be9d9e7
--- /dev/null
+++ b/tests/MC/ARM/dot-req.s.yaml
@@ -0,0 +1,12 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x05, 0xb0, 0xa0, 0xe1, 0x06, 0x10, 0xa0, 0xe1 ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov r11, r5"
+        -
+          asm_text: "mov r1, r6"
diff --git a/tests/MC/ARM/fconst.s.yaml b/tests/MC/ARM/fconst.s.yaml
new file mode 100644
index 000000000..430f726e4
--- /dev/null
+++ b/tests/MC/ARM/fconst.s.yaml
@@ -0,0 +1,24 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x2a, 0xb0, 0xee, 0x00, 0x2a, 0xb7, 0xee, 0x00, 0x3b, 0xb0, 0xee, 0x00, 0x3b, 0xb7, 0xee, 0x01, 0x2a, 0xf0, 0x1e, 0x00, 0x2a, 0xf2, 0xce, 0x03, 0x2b, 0xb0, 0xbe, 0x00, 0x2b, 0xb4, 0xae ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmov.f32 s4, #2.000000e+00"
+        -
+          asm_text: "vmov.f32 s4, #1.000000e+00"
+        -
+          asm_text: "vmov.f64 d3, #2.000000e+00"
+        -
+          asm_text: "vmov.f64 d3, #1.000000e+00"
+        -
+          asm_text: "vmovne.f32 s5, #2.125000e+00"
+        -
+          asm_text: "vmovgt.f32 s5, #8.000000e+00"
+        -
+          asm_text: "vmovlt.f64 d2, #2.375000e+00"
+        -
+          asm_text: "vmovge.f64 d2, #1.250000e-01"
diff --git a/tests/MC/ARM/fp-armv8.s.yaml b/tests/MC/ARM/fp-armv8.s.yaml
new file mode 100644
index 000000000..0da54dbb7
--- /dev/null
+++ b/tests/MC/ARM/fp-armv8.s.yaml
@@ -0,0 +1,110 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xe0, 0x3b, 0xb2, 0xee, 0xcc, 0x2b, 0xf3, 0xee, 0x60, 0x3b, 0xb2, 0xee, 0x41, 0x2b, 0xb3, 0xee, 0xe0, 0x3b, 0xb2, 0xae, 0xcc, 0x2b, 0xf3, 0xce, 0x60, 0x3b, 0xb2, 0x0e, 0x41, 0x2b, 0xb3, 0xbe, 0xe1, 0x1a, 0xbc, 0xfe, 0xc3, 0x1b, 0xbc, 0xfe, 0xeb, 0x3a, 0xbd, 0xfe, 0xe7, 0x3b, 0xbd, 0xfe, 0xc2, 0x0a, 0xbe, 0xfe, 0xc4, 0x0b, 0xbe, 0xfe, 0xc4, 0x8a, 0xff, 0xfe, 0xc8, 0x8b, 0xff, 0xfe, 0x61, 0x1a, 0xbc, 0xfe, 0x43, 0x1b, 0xbc, 0xfe, 0x6b, 0x3a, 0xbd, 0xfe, 0x67, 0x3b, 0xbd, 0xfe, 0x42, 0x0a, 0xbe, 0xfe, 0x44, 0x0b, 0xbe, 0xfe, 0x44, 0x8a, 0xff, 0xfe, 0x48, 0x8b, 0xff, 0xfe, 0xab, 0x2a, 0x20, 0xfe, 0xa7, 0xeb, 0x6f, 0xfe, 0x80, 0x0a, 0x30, 0xfe, 0x24, 0x5b, 0x3a, 0xfe, 0x2b, 0xfa, 0x0e, 0xfe, 0x08, 0x2b, 0x04, 0xfe, 0x07, 0xaa, 0x58, 0xfe, 0x2f, 0x0b, 0x11, 0xfe, 0x00, 0x2a, 0xc6, 0xfe, 0xae, 0x5b, 0x86, 0xfe, 0x46, 0x0a, 0x80, 0xfe, 0x49, 0x4b, 0x86, 0xfe, 0xcc, 0x3b, 0xb6, 0xae, 0xcc, 0x1a, 0xf6, 0xee, 0x40, 0x5b, 0xb6, 0xbe, 0x64, 0x0a, 0xb6, 0xee, 0x6e, 0xcb, 0xf7, 0x0e, 0x47, 0x5a, 0xb7, 0x6e, 0x44, 0x3b, 0xb8, 0xfe, 0x60, 0x6a, 0xb8, 0xfe, 0x44, 0x3b, 0xb9, 0xfe, 0x60, 0x6a, 0xb9, 0xfe, 0x44, 0x3b, 0xba, 0xfe, 0x60, 0x6a, 0xba, 0xfe, 0x44, 0x3b, 0xbb, 0xfe, 0x60, 0x6a, 0xbb, 0xfe, 0x10, 0xda, 0xf5, 0xee ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_V8", "CS_MODE_ARM" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvtt.f64.f16 d3, s1"
+        -
+          asm_text: "vcvtt.f16.f64 s5, d12"
+        -
+          asm_text: "vcvtb.f64.f16 d3, s1"
+        -
+          asm_text: "vcvtb.f16.f64 s4, d1"
+        -
+          asm_text: "vcvttge.f64.f16 d3, s1"
+        -
+          asm_text: "vcvttgt.f16.f64 s5, d12"
+        -
+          asm_text: "vcvtbeq.f64.f16 d3, s1"
+        -
+          asm_text: "vcvtblt.f16.f64 s4, d1"
+        -
+          asm_text: "vcvta.s32.f32 s2, s3"
+        -
+          asm_text: "vcvta.s32.f64 s2, d3"
+        -
+          asm_text: "vcvtn.s32.f32 s6, s23"
+        -
+          asm_text: "vcvtn.s32.f64 s6, d23"
+        -
+          asm_text: "vcvtp.s32.f32 s0, s4"
+        -
+          asm_text: "vcvtp.s32.f64 s0, d4"
+        -
+          asm_text: "vcvtm.s32.f32 s17, s8"
+        -
+          asm_text: "vcvtm.s32.f64 s17, d8"
+        -
+          asm_text: "vcvta.u32.f32 s2, s3"
+        -
+          asm_text: "vcvta.u32.f64 s2, d3"
+        -
+          asm_text: "vcvtn.u32.f32 s6, s23"
+        -
+          asm_text: "vcvtn.u32.f64 s6, d23"
+        -
+          asm_text: "vcvtp.u32.f32 s0, s4"
+        -
+          asm_text: "vcvtp.u32.f64 s0, d4"
+        -
+          asm_text: "vcvtm.u32.f32 s17, s8"
+        -
+          asm_text: "vcvtm.u32.f64 s17, d8"
+        -
+          asm_text: "vselge.f32 s4, s1, s23"
+        -
+          asm_text: "vselge.f64 d30, d31, d23"
+        -
+          asm_text: "vselgt.f32 s0, s1, s0"
+        -
+          asm_text: "vselgt.f64 d5, d10, d20"
+        -
+          asm_text: "vseleq.f32 s30, s28, s23"
+        -
+          asm_text: "vseleq.f64 d2, d4, d8"
+        -
+          asm_text: "vselvs.f32 s21, s16, s14"
+        -
+          asm_text: "vselvs.f64 d0, d1, d31"
+        -
+          asm_text: "vmaxnm.f32 s5, s12, s0"
+        -
+          asm_text: "vmaxnm.f64 d5, d22, d30"
+        -
+          asm_text: "vminnm.f32 s0, s0, s12"
+        -
+          asm_text: "vminnm.f64 d4, d6, d9"
+        -
+          asm_text: "vrintzge.f64 d3, d12"
+        -
+          asm_text: "vrintz.f32 s3, s24"
+        -
+          asm_text: "vrintrlt.f64 d5, d0"
+        -
+          asm_text: "vrintr.f32 s0, s9"
+        -
+          asm_text: "vrintxeq.f64 d28, d30"
+        -
+          asm_text: "vrintxvs.f32 s10, s14"
+        -
+          asm_text: "vrinta.f64 d3, d4"
+        -
+          asm_text: "vrinta.f32 s12, s1"
+        -
+          asm_text: "vrintn.f64 d3, d4"
+        -
+          asm_text: "vrintn.f32 s12, s1"
+        -
+          asm_text: "vrintp.f64 d3, d4"
+        -
+          asm_text: "vrintp.f32 s12, s1"
+        -
+          asm_text: "vrintm.f64 d3, d4"
+        -
+          asm_text: "vrintm.f32 s12, s1"
+        -
+          asm_text: "vmrs sp, mvfr2"
diff --git a/tests/MC/ARM/fpv8.s.yaml b/tests/MC/ARM/fpv8.s.yaml
new file mode 100644
index 000000000..ad0e68505
--- /dev/null
+++ b/tests/MC/ARM/fpv8.s.yaml
@@ -0,0 +1,78 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xa0, 0x0b, 0x71, 0xee, 0xe0, 0x0b, 0x71, 0xee, 0xa0, 0x0b, 0xc1, 0xee, 0x07, 0x5b, 0x85, 0xee, 0xa0, 0x0b, 0x61, 0xee, 0xa1, 0x4b, 0x64, 0xee, 0xe0, 0x0b, 0x61, 0xee, 0xe0, 0x1b, 0xf4, 0xee, 0xc0, 0x0b, 0xf5, 0xee, 0xe0, 0x0b, 0xf0, 0xee, 0xe0, 0x0b, 0xb7, 0xee, 0xc0, 0x0a, 0xf7, 0xee, 0x60, 0x0b, 0xf1, 0xee, 0xe0, 0x0b, 0xf1, 0xee, 0xc0, 0x0b, 0xf8, 0xee, 0x40, 0x0b, 0xf8, 0xee, 0xe0, 0x0b, 0xbd, 0xee, 0xe0, 0x0b, 0xbc, 0xee, 0xa1, 0x0b, 0x42, 0xee, 0xe1, 0x0b, 0x42, 0xee, 0xe1, 0x0b, 0x52, 0xee, 0xa1, 0x0b, 0x52, 0xee, 0x60, 0x0b, 0xf1, 0x1e, 0x08, 0x0b, 0xf0, 0xee, 0x08, 0x0b, 0xf8, 0xee, 0x40, 0x0b, 0xbd, 0xee, 0x40, 0x0b, 0xbc, 0xee, 0xc0, 0x0b, 0xba, 0xee, 0x40, 0x0b, 0xba, 0xee, 0xc0, 0x4b, 0xfb, 0xee, 0x40, 0x7b, 0xfb, 0xee, 0xc0, 0x2b, 0xbe, 0xee, 0x40, 0xfb, 0xbe, 0xee, 0xc0, 0x4b, 0xff, 0xee, 0x40, 0x7b, 0xff, 0xee ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_V8", "CS_MODE_ARM" ]
+    expected:
+      insns:
+        -
+          asm_text: "vadd.f64 d16, d17, d16"
+        -
+          asm_text: "vsub.f64 d16, d17, d16"
+        -
+          asm_text: "vdiv.f64 d16, d17, d16"
+        -
+          asm_text: "vdiv.f64 d5, d5, d7"
+        -
+          asm_text: "vmul.f64 d16, d17, d16"
+        -
+          asm_text: "vmul.f64 d20, d20, d17"
+        -
+          asm_text: "vnmul.f64 d16, d17, d16"
+        -
+          asm_text: "vcmpe.f64 d17, d16"
+        -
+          asm_text: "vcmpe.f64 d16, #0"
+        -
+          asm_text: "vabs.f64 d16, d16"
+        -
+          asm_text: "vcvt.f32.f64 s0, d16"
+        -
+          asm_text: "vcvt.f64.f32 d16, s0"
+        -
+          asm_text: "vneg.f64 d16, d16"
+        -
+          asm_text: "vsqrt.f64 d16, d16"
+        -
+          asm_text: "vcvt.f64.s32 d16, s0"
+        -
+          asm_text: "vcvt.f64.u32 d16, s0"
+        -
+          asm_text: "vcvt.s32.f64 s0, d16"
+        -
+          asm_text: "vcvt.u32.f64 s0, d16"
+        -
+          asm_text: "vmla.f64 d16, d18, d17"
+        -
+          asm_text: "vmls.f64 d16, d18, d17"
+        -
+          asm_text: "vnmla.f64 d16, d18, d17"
+        -
+          asm_text: "vnmls.f64 d16, d18, d17"
+        -
+          asm_text: "vnegne.f64 d16, d16"
+        -
+          asm_text: "vmov.f64 d16, #3.000000e+00"
+        -
+          asm_text: "vmov.f64 d16, #-3.000000e+00"
+        -
+          asm_text: "vcvtr.s32.f64 s0, d0"
+        -
+          asm_text: "vcvtr.u32.f64 s0, d0"
+        -
+          asm_text: "vcvt.f64.s32 d0, d0, #32"
+        -
+          asm_text: "vcvt.f64.s16 d0, d0, #16"
+        -
+          asm_text: "vcvt.f64.u32 d20, d20, #32"
+        -
+          asm_text: "vcvt.f64.u16 d23, d23, #16"
+        -
+          asm_text: "vcvt.s32.f64 d2, d2, #32"
+        -
+          asm_text: "vcvt.s16.f64 d15, d15, #16"
+        -
+          asm_text: "vcvt.u32.f64 d20, d20, #32"
+        -
+          asm_text: "vcvt.u16.f64 d23, d23, #16"
diff --git a/tests/MC/ARM/gas-compl-copr-reg.s.yaml b/tests/MC/ARM/gas-compl-copr-reg.s.yaml
new file mode 100644
index 000000000..7b77861f6
--- /dev/null
+++ b/tests/MC/ARM/gas-compl-copr-reg.s.yaml
@@ -0,0 +1,16 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x01, 0x4c, 0x90, 0xed, 0x38, 0x6e, 0x02, 0xed, 0x01, 0x4c, 0x90, 0xed, 0x38, 0x6e, 0x02, 0xed ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldc p12, c4, [r0, #4]"
+        -
+          asm_text: "stc p14, c6, [r2, #-0xe0]"
+        -
+          asm_text: "ldc p12, c4, [r0, #4]"
+        -
+          asm_text: "stc p14, c6, [r2, #-0xe0]"
diff --git a/tests/MC/ARM/idiv-thumb.s.yaml b/tests/MC/ARM/idiv-thumb.s.yaml
new file mode 100644
index 000000000..6e2933b8e
--- /dev/null
+++ b/tests/MC/ARM/idiv-thumb.s.yaml
@@ -0,0 +1,12 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x92, 0xfb, 0xf3, 0xf1, 0xb4, 0xfb, 0xf5, 0xf3 ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdiv r1, r2, r3"
+        -
+          asm_text: "udiv r3, r4, r5"
diff --git a/tests/MC/ARM/idiv.s.yaml b/tests/MC/ARM/idiv.s.yaml
new file mode 100644
index 000000000..6cc10c7b6
--- /dev/null
+++ b/tests/MC/ARM/idiv.s.yaml
@@ -0,0 +1,12 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x12, 0xf3, 0x11, 0xe7, 0x14, 0xf5, 0x33, 0xe7 ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdiv r1, r2, r3"
+        -
+          asm_text: "udiv r3, r4, r5"
diff --git a/tests/MC/ARM/implicit-it-generation.s.yaml b/tests/MC/ARM/implicit-it-generation.s.yaml
new file mode 100644
index 000000000..6ddc9738f
--- /dev/null
+++ b/tests/MC/ARM/implicit-it-generation.s.yaml
@@ -0,0 +1,30 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x01, 0x30, 0x10, 0xf1, 0x01, 0x00, 0x80, 0xe0, 0x00, 0xf0, 0x00, 0xbc, 0x02, 0xd0, 0x00, 0xf0, 0x80, 0x80, 0x02, 0xe0, 0x80, 0xe0, 0x00, 0xf0, 0x00, 0xbc, 0x02, 0xdc, 0x00, 0xf3, 0x80, 0x80 ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ]
+    expected:
+      insns:
+        -
+          asm_text: "adds r0, #1"
+        -
+          asm_text: "adds.w r0, r0, #1"
+        -
+          asm_text: "b #0x100"
+        -
+          asm_text: "b.w #0x800"
+        -
+          asm_text: "beq #4"
+        -
+          asm_text: "beq.w #0x100"
+        -
+          asm_text: "b #4"
+        -
+          asm_text: "b #0x100"
+        -
+          asm_text: "b.w #0x800"
+        -
+          asm_text: "bgt #4"
+        -
+          asm_text: "bgt.w #0x100"
diff --git a/tests/MC/ARM/ldrd-strd-gnu-arm.s.yaml b/tests/MC/ARM/ldrd-strd-gnu-arm.s.yaml
new file mode 100644
index 000000000..230eabd5e
--- /dev/null
+++ b/tests/MC/ARM/ldrd-strd-gnu-arm.s.yaml
@@ -0,0 +1,20 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xd0, 0x02, 0xea, 0xe1, 0xd0, 0x02, 0xca, 0xe0, 0xd0, 0x02, 0xca, 0xe1, 0xf0, 0x02, 0xea, 0xe1, 0xf0, 0x02, 0xca, 0xe0, 0xf0, 0x02, 0xca, 0xe1 ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldrd r0, r1, [r10, #0x20]!"
+        -
+          asm_text: "ldrd r0, r1, [r10], #0x20"
+        -
+          asm_text: "ldrd r0, r1, [r10, #0x20]"
+        -
+          asm_text: "strd r0, r1, [r10, #0x20]!"
+        -
+          asm_text: "strd r0, r1, [r10], #0x20"
+        -
+          asm_text: "strd r0, r1, [r10, #0x20]"
diff --git a/tests/MC/ARM/ldrd-strd-gnu-thumb.s.yaml b/tests/MC/ARM/ldrd-strd-gnu-thumb.s.yaml
new file mode 100644
index 000000000..076ae9154
--- /dev/null
+++ b/tests/MC/ARM/ldrd-strd-gnu-thumb.s.yaml
@@ -0,0 +1,32 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xfa, 0xe9, 0x80, 0x01, 0xfa, 0xe8, 0x80, 0x01, 0xda, 0xe9, 0x80, 0x01, 0xea, 0xe9, 0x80, 0x01, 0xea, 0xe8, 0x80, 0x01, 0xca, 0xe9, 0x80, 0x01, 0xfa, 0xe9, 0x80, 0x12, 0xfa, 0xe8, 0x80, 0x12, 0xda, 0xe9, 0x80, 0x12, 0xea, 0xe9, 0x80, 0x12, 0xea, 0xe8, 0x80, 0x12, 0xca, 0xe9, 0x80, 0x12 ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldrd r0, r1, [r10, #0x200]!"
+        -
+          asm_text: "ldrd r0, r1, [r10], #0x200"
+        -
+          asm_text: "ldrd r0, r1, [r10, #0x200]"
+        -
+          asm_text: "strd r0, r1, [r10, #0x200]!"
+        -
+          asm_text: "strd r0, r1, [r10], #0x200"
+        -
+          asm_text: "strd r0, r1, [r10, #0x200]"
+        -
+          asm_text: "ldrd r1, r2, [r10, #0x200]!"
+        -
+          asm_text: "ldrd r1, r2, [r10], #0x200"
+        -
+          asm_text: "ldrd r1, r2, [r10, #0x200]"
+        -
+          asm_text: "strd r1, r2, [r10, #0x200]!"
+        -
+          asm_text: "strd r1, r2, [r10], #0x200"
+        -
+          asm_text: "strd r1, r2, [r10, #0x200]"
diff --git a/tests/MC/ARM/load-store-acquire-release-v8-thumb.s.yaml b/tests/MC/ARM/load-store-acquire-release-v8-thumb.s.yaml
new file mode 100644
index 000000000..6f376cc26
--- /dev/null
+++ b/tests/MC/ARM/load-store-acquire-release-v8-thumb.s.yaml
@@ -0,0 +1,36 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xd4, 0xe8, 0xcf, 0x3f, 0xd5, 0xe8, 0xdf, 0x2f, 0xd7, 0xe8, 0xef, 0x1f, 0xd8, 0xe8, 0xff, 0x67, 0xc4, 0xe8, 0xc1, 0x3f, 0xc5, 0xe8, 0xd4, 0x2f, 0xc7, 0xe8, 0xe2, 0x1f, 0xc8, 0xe8, 0xf6, 0x23, 0xd6, 0xe8, 0xaf, 0x5f, 0xd6, 0xe8, 0x8f, 0x5f, 0xd9, 0xe8, 0x9f, 0xcf, 0xc0, 0xe8, 0xaf, 0x3f, 0xc1, 0xe8, 0x8f, 0x2f, 0xc3, 0xe8, 0x9f, 0x2f ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_V8", "CS_MODE_THUMB" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldaexb r3, [r4]"
+        -
+          asm_text: "ldaexh r2, [r5]"
+        -
+          asm_text: "ldaex r1, [r7]"
+        -
+          asm_text: "ldaexd r6, r7, [r8]"
+        -
+          asm_text: "stlexb r1, r3, [r4]"
+        -
+          asm_text: "stlexh r4, r2, [r5]"
+        -
+          asm_text: "stlex r2, r1, [r7]"
+        -
+          asm_text: "stlexd r6, r2, r3, [r8]"
+        -
+          asm_text: "lda r5, [r6]"
+        -
+          asm_text: "ldab r5, [r6]"
+        -
+          asm_text: "ldah r12, [r9]"
+        -
+          asm_text: "stl r3, [r0]"
+        -
+          asm_text: "stlb r2, [r1]"
+        -
+          asm_text: "stlh r2, [r3]"
diff --git a/tests/MC/ARM/load-store-acquire-release-v8.s.yaml b/tests/MC/ARM/load-store-acquire-release-v8.s.yaml
new file mode 100644
index 000000000..de9f4b00d
--- /dev/null
+++ b/tests/MC/ARM/load-store-acquire-release-v8.s.yaml
@@ -0,0 +1,36 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x9f, 0x3e, 0xd4, 0xe1, 0x9f, 0x2e, 0xf5, 0xe1, 0x9f, 0x1e, 0x97, 0xe1, 0x9f, 0x6e, 0xb8, 0xe1, 0x93, 0x1e, 0xc4, 0xe1, 0x92, 0x4e, 0xe5, 0xe1, 0x91, 0x2e, 0x87, 0xe1, 0x92, 0x6e, 0xa8, 0xe1, 0x9f, 0x5c, 0x96, 0xe1, 0x9f, 0x5c, 0xd6, 0xe1, 0x9f, 0xcc, 0xf9, 0xe1, 0x93, 0xfc, 0x80, 0xe1, 0x92, 0xfc, 0xc1, 0xe1, 0x92, 0xfc, 0xe3, 0xe1 ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_V8", "CS_MODE_ARM" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldaexb r3, [r4]"
+        -
+          asm_text: "ldaexh r2, [r5]"
+        -
+          asm_text: "ldaex r1, [r7]"
+        -
+          asm_text: "ldaexd r6, r7, [r8]"
+        -
+          asm_text: "stlexb r1, r3, [r4]"
+        -
+          asm_text: "stlexh r4, r2, [r5]"
+        -
+          asm_text: "stlex r2, r1, [r7]"
+        -
+          asm_text: "stlexd r6, r2, r3, [r8]"
+        -
+          asm_text: "lda r5, [r6]"
+        -
+          asm_text: "ldab r5, [r6]"
+        -
+          asm_text: "ldah r12, [r9]"
+        -
+          asm_text: "stl r3, [r0]"
+        -
+          asm_text: "stlb r2, [r1]"
+        -
+          asm_text: "stlh r2, [r3]"
diff --git a/tests/MC/ARM/mve-bitops.s.yaml b/tests/MC/ARM/mve-bitops.s.yaml
new file mode 100644
index 000000000..e61a502d1
--- /dev/null
+++ b/tests/MC/ARM/mve-bitops.s.yaml
@@ -0,0 +1,198 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x81, 0xef, 0x52, 0x09, 0x81, 0xef, 0x52, 0x03, 0x86, 0xff, 0x5d, 0x09, 0x86, 0xff, 0x5d, 0x03, 0x86, 0xff, 0x5d, 0x05, 0x86, 0xff, 0x5d, 0x07, 0x82, 0xef, 0x72, 0x09, 0x81, 0xef, 0x71, 0x03, 0x85, 0xff, 0x7d, 0x09, 0x85, 0xff, 0x7d, 0x0b, 0x86, 0xff, 0x7e, 0x01, 0x86, 0xff, 0x7e, 0x03, 0x86, 0xff, 0x7e, 0x05, 0x86, 0xff, 0x7e, 0x07, 0x12, 0xef, 0x5e, 0x01, 0x12, 0xef, 0x5e, 0x01, 0x12, 0xef, 0x5e, 0x01, 0x12, 0xef, 0x5e, 0x01, 0x12, 0xef, 0x5e, 0x01, 0x12, 0xef, 0x5e, 0x01, 0x12, 0xef, 0x5e, 0x01, 0x12, 0xef, 0x5e, 0x01, 0x12, 0xef, 0x5e, 0x01, 0x12, 0xef, 0x5e, 0x01, 0x12, 0xef, 0x5e, 0x01, 0x12, 0xef, 0x5e, 0x01, 0xb0, 0xff, 0x48, 0x00, 0xb4, 0xff, 0x46, 0x20, 0xb8, 0xff, 0x44, 0x00, 0xb0, 0xff, 0xc2, 0x00, 0xb4, 0xff, 0xca, 0x00, 0xb0, 0xff, 0x44, 0x01, 0xb0, 0xff, 0xc4, 0x05, 0x02, 0xff, 0x5e, 0x41, 0x02, 0xff, 0x5e, 0x41, 0x02, 0xff, 0x5e, 0x41, 0x02, 0xff, 0x5e, 0x41, 0x02, 0xff, 0x5e, 0x41, 0x02, 0xff, 0x5e, 0x41, 0x02, 0xff, 0x5e, 0x41, 0x02, 0xff, 0x5e, 0x41, 0x02, 0xff, 0x5e, 0x41, 0x02, 0xff, 0x5e, 0x41, 0x02, 0xff, 0x5e, 0x41, 0x02, 0xff, 0x5e, 0x41, 0x36, 0xef, 0x54, 0x01, 0x36, 0xef, 0x54, 0x01, 0x36, 0xef, 0x54, 0x01, 0x36, 0xef, 0x54, 0x01, 0x36, 0xef, 0x54, 0x01, 0x36, 0xef, 0x54, 0x01, 0x36, 0xef, 0x54, 0x01, 0x36, 0xef, 0x54, 0x01, 0x36, 0xef, 0x54, 0x01, 0x36, 0xef, 0x54, 0x01, 0x36, 0xef, 0x54, 0x01, 0x36, 0xef, 0x54, 0x01, 0x24, 0xef, 0x52, 0x21, 0x24, 0xef, 0x52, 0x21, 0x24, 0xef, 0x52, 0x21, 0x24, 0xef, 0x52, 0x21, 0x24, 0xef, 0x52, 0x21, 0x24, 0xef, 0x52, 0x21, 0x24, 0xef, 0x52, 0x21, 0x24, 0xef, 0x52, 0x21, 0x24, 0xef, 0x52, 0x21, 0x24, 0xef, 0x52, 0x21, 0x24, 0xef, 0x52, 0x21, 0x24, 0xef, 0x52, 0x21, 0x04, 0xef, 0x50, 0x01, 0x04, 0xef, 0x50, 0x01, 0x04, 0xef, 0x50, 0x01, 0x04, 0xef, 0x50, 0x01, 0x04, 0xef, 0x50, 0x01, 0x04, 0xef, 0x50, 0x01, 0x04, 0xef, 0x50, 0x01, 0x04, 0xef, 0x50, 0x01, 0x04, 0xef, 0x50, 0x01, 0x04, 0xef, 0x50, 0x01, 0x04, 0xef, 0x50, 0x01, 0x04, 0xef, 0x50, 0x01, 0x40, 0xee, 0x30, 0x8b, 0x20, 0xee, 0x30, 0x5b, 0x2d, 0xee, 0x10, 0xbb, 0x12, 0xee, 0x10, 0x0b, 0x35, 0xee, 0x70, 0x1b, 0x79, 0xee, 0x30, 0x0b, 0x93, 0xee, 0x30, 0x0b, 0xfa, 0xee, 0x70, 0x0b, 0x71, 0xfe, 0x4d, 0x8f, 0xb0, 0xff, 0xc2, 0x05, 0xb0, 0xff, 0xc2, 0x05, 0x71, 0xfe, 0x4d, 0x8f, 0x32, 0xef, 0x54, 0x01, 0x32, 0xef, 0x54, 0x01 ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_MCLASS", "CS_MODE_V8", "CS_MODE_THUMB" ]
+    expected:
+      insns:
+        -
+          asm_text: "vorr.i16 q0, #0x12"
+        -
+          asm_text: "vorr.i32 q0, #0x1200"
+        -
+          asm_text: "vorr.i16 q0, #0xed"
+        -
+          asm_text: "vorr.i32 q0, #0xed00"
+        -
+          asm_text: "vorr.i32 q0, #0xed0000"
+        -
+          asm_text: "vorr.i32 q0, #0xed000000"
+        -
+          asm_text: "vbic.i16 q0, #0x22"
+        -
+          asm_text: "vbic.i32 q0, #0x1100"
+        -
+          asm_text: "vbic.i16 q0, #0xdd"
+        -
+          asm_text: "vbic.i16 q0, #0xdd00"
+        -
+          asm_text: "vbic.i32 q0, #0xee"
+        -
+          asm_text: "vbic.i32 q0, #0xee00"
+        -
+          asm_text: "vbic.i32 q0, #0xee0000"
+        -
+          asm_text: "vbic.i32 q0, #0xee000000"
+        -
+          asm_text: "vbic q0, q1, q7"
+        -
+          asm_text: "vbic q0, q1, q7"
+        -
+          asm_text: "vbic q0, q1, q7"
+        -
+          asm_text: "vbic q0, q1, q7"
+        -
+          asm_text: "vbic q0, q1, q7"
+        -
+          asm_text: "vbic q0, q1, q7"
+        -
+          asm_text: "vbic q0, q1, q7"
+        -
+          asm_text: "vbic q0, q1, q7"
+        -
+          asm_text: "vbic q0, q1, q7"
+        -
+          asm_text: "vbic q0, q1, q7"
+        -
+          asm_text: "vbic q0, q1, q7"
+        -
+          asm_text: "vbic q0, q1, q7"
+        -
+          asm_text: "vrev64.8 q0, q4"
+        -
+          asm_text: "vrev64.16 q1, q3"
+        -
+          asm_text: "vrev64.32 q0, q2"
+        -
+          asm_text: "vrev32.8 q0, q1"
+        -
+          asm_text: "vrev32.16 q0, q5"
+        -
+          asm_text: "vrev16.8 q0, q2"
+        -
+          asm_text: "vmvn q0, q2"
+        -
+          asm_text: "veor q2, q1, q7"
+        -
+          asm_text: "veor q2, q1, q7"
+        -
+          asm_text: "veor q2, q1, q7"
+        -
+          asm_text: "veor q2, q1, q7"
+        -
+          asm_text: "veor q2, q1, q7"
+        -
+          asm_text: "veor q2, q1, q7"
+        -
+          asm_text: "veor q2, q1, q7"
+        -
+          asm_text: "veor q2, q1, q7"
+        -
+          asm_text: "veor q2, q1, q7"
+        -
+          asm_text: "veor q2, q1, q7"
+        -
+          asm_text: "veor q2, q1, q7"
+        -
+          asm_text: "veor q2, q1, q7"
+        -
+          asm_text: "vorn q0, q3, q2"
+        -
+          asm_text: "vorn q0, q3, q2"
+        -
+          asm_text: "vorn q0, q3, q2"
+        -
+          asm_text: "vorn q0, q3, q2"
+        -
+          asm_text: "vorn q0, q3, q2"
+        -
+          asm_text: "vorn q0, q3, q2"
+        -
+          asm_text: "vorn q0, q3, q2"
+        -
+          asm_text: "vorn q0, q3, q2"
+        -
+          asm_text: "vorn q0, q3, q2"
+        -
+          asm_text: "vorn q0, q3, q2"
+        -
+          asm_text: "vorn q0, q3, q2"
+        -
+          asm_text: "vorn q0, q3, q2"
+        -
+          asm_text: "vorr q1, q2, q1"
+        -
+          asm_text: "vorr q1, q2, q1"
+        -
+          asm_text: "vorr q1, q2, q1"
+        -
+          asm_text: "vorr q1, q2, q1"
+        -
+          asm_text: "vorr q1, q2, q1"
+        -
+          asm_text: "vorr q1, q2, q1"
+        -
+          asm_text: "vorr q1, q2, q1"
+        -
+          asm_text: "vorr q1, q2, q1"
+        -
+          asm_text: "vorr q1, q2, q1"
+        -
+          asm_text: "vorr q1, q2, q1"
+        -
+          asm_text: "vorr q1, q2, q1"
+        -
+          asm_text: "vorr q1, q2, q1"
+        -
+          asm_text: "vand q0, q2, q0"
+        -
+          asm_text: "vand q0, q2, q0"
+        -
+          asm_text: "vand q0, q2, q0"
+        -
+          asm_text: "vand q0, q2, q0"
+        -
+          asm_text: "vand q0, q2, q0"
+        -
+          asm_text: "vand q0, q2, q0"
+        -
+          asm_text: "vand q0, q2, q0"
+        -
+          asm_text: "vand q0, q2, q0"
+        -
+          asm_text: "vand q0, q2, q0"
+        -
+          asm_text: "vand q0, q2, q0"
+        -
+          asm_text: "vand q0, q2, q0"
+        -
+          asm_text: "vand q0, q2, q0"
+        -
+          asm_text: "vmov.8 q0[1], r8"
+        -
+          asm_text: "vmov.16 q0[2], r5"
+        -
+          asm_text: "vmov.32 q6[3], r11"
+        -
+          asm_text: "vmov.32 r0, q1[0]"
+        -
+          asm_text: "vmov.s16 r1, q2[7]"
+        -
+          asm_text: "vmov.s8 r0, q4[13]"
+        -
+          asm_text: "vmov.u16 r0, q1[4]"
+        -
+          asm_text: "vmov.u8 r0, q5[7]"
+        -
+          asm_text: "vpste"
+        -
+          asm_text: "vmvnt q0, q1"
+        -
+          asm_text: "vmvne q0, q1"
+        -
+          asm_text: "vpste"
+        -
+          asm_text: "vornt q0, q1, q2"
+        -
+          asm_text: "vorne q0, q1, q2"
diff --git a/tests/MC/ARM/mve-float.s.yaml b/tests/MC/ARM/mve-float.s.yaml
new file mode 100644
index 000000000..c2b9188c5
--- /dev/null
+++ b/tests/MC/ARM/mve-float.s.yaml
@@ -0,0 +1,212 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xb6, 0xff, 0x40, 0x24, 0xba, 0xff, 0x48, 0x04, 0xb6, 0xff, 0x42, 0x05, 0xba, 0xff, 0x46, 0x25, 0xb6, 0xff, 0xca, 0x06, 0xba, 0xff, 0xc8, 0x06, 0xb6, 0xff, 0xc0, 0x27, 0xba, 0xff, 0xc2, 0x07, 0xb6, 0xff, 0xc4, 0x24, 0xba, 0xff, 0xc2, 0x24, 0xb6, 0xff, 0xcc, 0x25, 0xba, 0xff, 0xc0, 0x25, 0xb6, 0xee, 0x60, 0x0a, 0xb6, 0xee, 0x41, 0x0b, 0x12, 0xff, 0x56, 0x4d, 0x00, 0xff, 0x5a, 0x0d, 0x24, 0xfc, 0x42, 0x68, 0xa0, 0xfc, 0x4a, 0x08, 0x2e, 0xfd, 0x44, 0x68, 0xae, 0xfd, 0x4c, 0x48, 0x3c, 0xfc, 0x4c, 0x48, 0xb2, 0xfc, 0x46, 0xe8, 0x3a, 0xfd, 0x46, 0x88, 0xb4, 0xfd, 0x4e, 0x68, 0x14, 0xef, 0x56, 0x0c, 0x06, 0xef, 0x5e, 0x0c, 0x34, 0xef, 0x5a, 0x0c, 0x22, 0xef, 0x54, 0x2c, 0x10, 0xef, 0x4a, 0x0d, 0x06, 0xef, 0x40, 0x2d, 0x02, 0xef, 0x44, 0x0d, 0x82, 0xfc, 0x4e, 0x48, 0x8a, 0xfd, 0x4e, 0x48, 0x98, 0xfc, 0x4e, 0x08, 0x94, 0xfd, 0x46, 0x48, 0x30, 0xff, 0x4c, 0x0d, 0x22, 0xff, 0x48, 0x0d, 0xbf, 0xef, 0x5e, 0x2c, 0xb0, 0xef, 0x5e, 0x2c, 0xb5, 0xef, 0x5e, 0x2c, 0xbd, 0xef, 0x52, 0x2d, 0xb6, 0xff, 0x52, 0x4c, 0xbd, 0xff, 0x50, 0x0d, 0xbf, 0xef, 0x5e, 0x2e, 0xa0, 0xef, 0x5e, 0x2e, 0xba, 0xef, 0x5e, 0x2e, 0xab, 0xef, 0x50, 0x2f, 0xbc, 0xff, 0x58, 0x2e, 0xb8, 0xff, 0x5a, 0x2f, 0xb7, 0xff, 0x42, 0x06, 0xb7, 0xff, 0xc8, 0x06, 0xb7, 0xff, 0x40, 0x07, 0xb7, 0xff, 0xc0, 0x07, 0xbb, 0xff, 0x40, 0x06, 0xbb, 0xff, 0xc0, 0x06, 0xbb, 0xff, 0x40, 0x07, 0xbb, 0xff, 0xc4, 0x07, 0xb7, 0xff, 0x4e, 0x00, 0xbc, 0xfe, 0xe1, 0x1a, 0xb7, 0xff, 0x4e, 0x00, 0xbb, 0xff, 0xcc, 0xe1, 0xbb, 0xff, 0x4e, 0x02, 0xbb, 0xff, 0xc8, 0x23, 0xb5, 0xff, 0xce, 0x07, 0xb9, 0xff, 0xc4, 0x07, 0xb5, 0xff, 0x44, 0x07, 0xb9, 0xff, 0x40, 0x07, 0x3f, 0xfe, 0x83, 0x2e, 0x3f, 0xee, 0x8d, 0x4e, 0x3f, 0xfe, 0x85, 0x1e, 0x3f, 0xee, 0x83, 0x1e, 0x08, 0xbf, 0x30, 0xee, 0x20, 0x0a, 0x71, 0xfe, 0x4d, 0x0f, 0x12, 0xef, 0x44, 0x0d, 0x71, 0xfe, 0x4d, 0x8f, 0xbb, 0xff, 0xc2, 0x03, 0xbb, 0xff, 0x42, 0x01, 0x18, 0xbf, 0xbd, 0xee, 0xe0, 0x0a, 0xa8, 0xbf, 0xb2, 0xee, 0xe0, 0x3b, 0x77, 0xee, 0xc1, 0x9f, 0xbb, 0xff, 0xc0, 0x47, 0xbb, 0xff, 0xc0, 0x27, 0x0c, 0xbf, 0xbc, 0xee, 0xe0, 0x0a, 0xb8, 0xee, 0x60, 0x0a, 0x71, 0xfe, 0x4d, 0x8f, 0x12, 0xff, 0x54, 0x0d, 0x12, 0xff, 0x54, 0x0d, 0x0c, 0xbf, 0x20, 0xee, 0x01, 0x0b, 0x20, 0xee, 0x02, 0x1b, 0x08, 0xbf, 0xb1, 0xee, 0x60, 0x0a, 0x04, 0xbf, 0x20, 0xee, 0xc1, 0x0a, 0x20, 0xee, 0x81, 0x0a, 0x71, 0xfe, 0x4d, 0x8f, 0xb6, 0xff, 0x42, 0x04, 0xba, 0xff, 0x42, 0x04 ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_MCLASS", "CS_MODE_THUMB" ]
+    expected:
+      insns:
+        -
+          asm_text: "vrintn.f16 q1, q0"
+        -
+          asm_text: "vrintn.f32 q0, q4"
+        -
+          asm_text: "vrinta.f16 q0, q1"
+        -
+          asm_text: "vrinta.f32 q1, q3"
+        -
+          asm_text: "vrintm.f16 q0, q5"
+        -
+          asm_text: "vrintm.f32 q0, q4"
+        -
+          asm_text: "vrintp.f16 q1, q0"
+        -
+          asm_text: "vrintp.f32 q0, q1"
+        -
+          asm_text: "vrintx.f16 q1, q2"
+        -
+          asm_text: "vrintx.f32 q1, q1"
+        -
+          asm_text: "vrintz.f16 q1, q6"
+        -
+          asm_text: "vrintz.f32 q1, q0"
+        -
+          asm_text: "vrintr.f32 s0, s1"
+        -
+          asm_text: "vrintr.f64 d0, d1"
+        -
+          asm_text: "vmul.f16 q2, q1, q3"
+        -
+          asm_text: "vmul.f32 q0, q0, q5"
+        -
+          asm_text: "vcmla.f16 q3, q2, q1, #0"
+        -
+          asm_text: "vcmla.f16 q0, q0, q5, #0x5a"
+        -
+          asm_text: "vcmla.f16 q3, q7, q2, #0xb4"
+        -
+          asm_text: "vcmla.f16 q2, q7, q6, #0x10e"
+        -
+          asm_text: "vcmla.f32 q2, q6, q6, #0"
+        -
+          asm_text: "vcmla.f32 q7, q1, q3, #0x5a"
+        -
+          asm_text: "vcmla.f32 q4, q5, q3, #0xb4"
+        -
+          asm_text: "vcmla.f32 q3, q2, q7, #0x10e"
+        -
+          asm_text: "vfma.f16 q0, q2, q3"
+        -
+          asm_text: "vfma.f32 q0, q3, q7"
+        -
+          asm_text: "vfms.f16 q0, q2, q5"
+        -
+          asm_text: "vfms.f32 q1, q1, q2"
+        -
+          asm_text: "vadd.f16 q0, q0, q5"
+        -
+          asm_text: "vadd.f32 q1, q3, q0"
+        -
+          asm_text: "vadd.f32 q0, q1, q2"
+        -
+          asm_text: "vcadd.f16 q2, q1, q7, #0x5a"
+        -
+          asm_text: "vcadd.f16 q2, q5, q7, #0x10e"
+        -
+          asm_text: "vcadd.f32 q0, q4, q7, #0x5a"
+        -
+          asm_text: "vcadd.f32 q2, q2, q3, #0x10e"
+        -
+          asm_text: "vabd.f16 q0, q0, q6"
+        -
+          asm_text: "vabd.f32 q0, q1, q4"
+        -
+          asm_text: "vcvt.f16.s16 q1, q7, #1"
+        -
+          asm_text: "vcvt.f16.s16 q1, q7, #0x10"
+        -
+          asm_text: "vcvt.f16.s16 q1, q7, #0xb"
+        -
+          asm_text: "vcvt.s16.f16 q1, q1, #3"
+        -
+          asm_text: "vcvt.f16.u16 q2, q1, #0xa"
+        -
+          asm_text: "vcvt.u16.f16 q0, q0, #3"
+        -
+          asm_text: "vcvt.f32.s32 q1, q7, #1"
+        -
+          asm_text: "vcvt.f32.s32 q1, q7, #0x20"
+        -
+          asm_text: "vcvt.f32.s32 q1, q7, #6"
+        -
+          asm_text: "vcvt.s32.f32 q1, q0, #0x15"
+        -
+          asm_text: "vcvt.f32.u32 q1, q4, #4"
+        -
+          asm_text: "vcvt.u32.f32 q1, q5, #8"
+        -
+          asm_text: "vcvt.f16.s16 q0, q1"
+        -
+          asm_text: "vcvt.f16.u16 q0, q4"
+        -
+          asm_text: "vcvt.s16.f16 q0, q0"
+        -
+          asm_text: "vcvt.u16.f16 q0, q0"
+        -
+          asm_text: "vcvt.f32.s32 q0, q0"
+        -
+          asm_text: "vcvt.f32.u32 q0, q0"
+        -
+          asm_text: "vcvt.s32.f32 q0, q0"
+        -
+          asm_text: "vcvt.u32.f32 q0, q2"
+        -
+          asm_text: "vcvta.s16.f16 q0, q7"
+        -
+          asm_text: "vcvta.s32.f32 s2, s3"
+        -
+          asm_text: "vcvta.s16.f16 q0, q7"
+        -
+          asm_text: "vcvtn.u32.f32 q7, q6"
+        -
+          asm_text: "vcvtp.s32.f32 q0, q7"
+        -
+          asm_text: "vcvtm.u32.f32 q1, q4"
+        -
+          asm_text: "vneg.f16 q0, q7"
+        -
+          asm_text: "vneg.f32 q0, q2"
+        -
+          asm_text: "vabs.f16 q0, q2"
+        -
+          asm_text: "vabs.f32 q0, q0"
+        -
+          asm_text: "vmaxnma.f16 q1, q1"
+        -
+          asm_text: "vmaxnma.f32 q2, q6"
+        -
+          asm_text: "vminnma.f16 q0, q2"
+        -
+          asm_text: "vminnma.f32 q0, q1"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "vaddeq.f32 s0, s0, s1"
+        -
+          asm_text: "vpst"
+        -
+          asm_text: "vaddt.f16 q0, q1, q2"
+        -
+          asm_text: "vpste"
+        -
+          asm_text: "vcvtmt.u32.f32 q0, q1"
+        -
+          asm_text: "vcvtne.s32.f32 q0, q1"
+        -
+          asm_text: "it ne"
+        -
+          asm_text: "vcvtne.s32.f32 s0, s1"
+        -
+          asm_text: "it ge"
+        -
+          asm_text: "vcvttge.f64.f16 d3, s1"
+        -
+          asm_text: "vpte.f32 lt, q3, r1"
+        -
+          asm_text: "vcvtt.u32.f32 q2, q0"
+        -
+          asm_text: "vcvte.u32.f32 q1, q0"
+        -
+          asm_text: "ite eq"
+        -
+          asm_text: "vcvteq.u32.f32 s0, s1"
+        -
+          asm_text: "vcvtne.f32.u32 s0, s1"
+        -
+          asm_text: "vpste"
+        -
+          asm_text: "vmult.f16 q0, q1, q2"
+        -
+          asm_text: "vmule.f16 q0, q1, q2"
+        -
+          asm_text: "ite eq"
+        -
+          asm_text: "vmuleq.f64 d0, d0, d1"
+        -
+          asm_text: "vmulne.f64 d1, d0, d2"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "vnegeq.f32 s0, s1"
+        -
+          asm_text: "itt eq"
+        -
+          asm_text: "vnmuleq.f32 s0, s1, s2"
+        -
+          asm_text: "vmuleq.f32 s0, s1, s2"
+        -
+          asm_text: "vpste"
+        -
+          asm_text: "vrintnt.f16 q0, q1"
+        -
+          asm_text: "vrintne.f32 q0, q1"
diff --git a/tests/MC/ARM/mve-integer.s.yaml b/tests/MC/ARM/mve-integer.s.yaml
new file mode 100644
index 000000000..fcc984d1a
--- /dev/null
+++ b/tests/MC/ARM/mve-integer.s.yaml
@@ -0,0 +1,206 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x81, 0xef, 0x5b, 0x0c, 0x85, 0xef, 0x5c, 0x08, 0x84, 0xef, 0x5c, 0x0e, 0x80, 0xff, 0x5d, 0x0f, 0x84, 0xef, 0x50, 0x0f, 0x84, 0xef, 0x51, 0x0f, 0x83, 0xef, 0x5f, 0x0f, 0xb0, 0xee, 0x60, 0x8a, 0xb0, 0xee, 0x41, 0x0b, 0x81, 0xff, 0x7f, 0x0e, 0x00, 0xef, 0x56, 0x09, 0x10, 0xef, 0x56, 0xc9, 0x26, 0xef, 0x5c, 0xe9, 0x0a, 0xff, 0x4a, 0x0b, 0x18, 0xff, 0x44, 0x2b, 0x2a, 0xff, 0x40, 0x0b, 0x08, 0xef, 0x4a, 0x0b, 0x18, 0xef, 0x40, 0xcb, 0x20, 0xef, 0x4c, 0xab, 0x04, 0xff, 0x4a, 0x68, 0x16, 0xff, 0x4c, 0x08, 0x20, 0xff, 0x4c, 0x08, 0x04, 0xef, 0x44, 0x08, 0x14, 0xef, 0x42, 0x48, 0x20, 0xef, 0x4c, 0x08, 0x0c, 0xef, 0x50, 0x22, 0x1c, 0xef, 0x52, 0x02, 0x20, 0xef, 0x5a, 0x02, 0x04, 0xff, 0x5c, 0x02, 0x1e, 0xff, 0x52, 0x02, 0x28, 0xff, 0x5e, 0x22, 0x02, 0xef, 0x54, 0x00, 0x08, 0xef, 0x5c, 0x00, 0x1a, 0xef, 0x5a, 0x00, 0x20, 0xef, 0x58, 0x00, 0x08, 0xff, 0x54, 0x00, 0x1c, 0xff, 0x5c, 0x80, 0x22, 0xff, 0x54, 0x00, 0x00, 0xef, 0x44, 0x07, 0x1a, 0xef, 0x48, 0x27, 0x26, 0xef, 0x44, 0x47, 0x0c, 0xff, 0x48, 0x27, 0x1c, 0xff, 0x44, 0x07, 0x2e, 0xff, 0x48, 0x07, 0x02, 0xef, 0x42, 0x01, 0x12, 0xef, 0x40, 0x01, 0x28, 0xef, 0x42, 0x01, 0x00, 0xff, 0x4c, 0x21, 0x14, 0xff, 0x4a, 0x41, 0x26, 0xff, 0x40, 0x41, 0x00, 0xef, 0x44, 0x02, 0x16, 0xef, 0x42, 0x22, 0x24, 0xef, 0x4a, 0x02, 0x08, 0xff, 0x44, 0x02, 0x1e, 0xff, 0x4a, 0x02, 0x2c, 0xff, 0x48, 0x42, 0x0e, 0xef, 0x40, 0x00, 0x10, 0xef, 0x44, 0x80, 0x26, 0xef, 0x42, 0x00, 0x00, 0xff, 0x46, 0x60, 0x12, 0xff, 0x46, 0x00, 0x22, 0xff, 0x46, 0x00, 0xec, 0xee, 0x10, 0x8b, 0xae, 0xee, 0x30, 0xeb, 0xa2, 0xee, 0x10, 0x9b, 0xa0, 0xee, 0x30, 0x1b, 0xa0, 0xee, 0x30, 0x1b, 0xb0, 0xff, 0x42, 0x44, 0xb4, 0xff, 0x48, 0x04, 0xb8, 0xff, 0x40, 0x04, 0xb0, 0xff, 0xce, 0x04, 0xb4, 0xff, 0xce, 0x84, 0xb8, 0xff, 0xca, 0xe4, 0xb1, 0xff, 0xc0, 0x23, 0xb5, 0xff, 0xc2, 0x03, 0xb9, 0xff, 0xc4, 0xe3, 0xb1, 0xff, 0x42, 0x23, 0xb5, 0xff, 0x44, 0x03, 0xb9, 0xff, 0x4e, 0x03, 0xb0, 0xff, 0xc0, 0x07, 0xb4, 0xff, 0xc4, 0xc7, 0xb8, 0xff, 0xc4, 0xe7, 0xb0, 0xff, 0x48, 0x47, 0xb4, 0xff, 0x44, 0x07, 0xb8, 0xff, 0x4a, 0x07, 0x71, 0xfe, 0x4d, 0x8f, 0xb1, 0xff, 0xc2, 0x03, 0xb1, 0xff, 0xc2, 0x03, 0x71, 0xfe, 0x4d, 0x0f, 0x12, 0xef, 0x54, 0x00, 0x71, 0xfe, 0x4d, 0x8f, 0xb0, 0xff, 0xc2, 0x07, 0xb4, 0xff, 0xc2, 0x07, 0x33, 0xee, 0x8f, 0x3e, 0x37, 0xee, 0x89, 0x3e, 0x3b, 0xee, 0x8f, 0x1e, 0x33, 0xee, 0x8f, 0x0e, 0x37, 0xee, 0x81, 0x2e, 0x3b, 0xee, 0x81, 0x2e ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_MCLASS", "CS_MODE_V8", "CS_MODE_THUMB" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmov.i32 q0, #0x1bff"
+        -
+          asm_text: "vmov.i16 q0, #0x5c"
+        -
+          asm_text: "vmov.i8 q0, #0x4c"
+        -
+          asm_text: "vmov.f32 q0, #-3.625000e+00"
+        -
+          asm_text: "vmov.f32 q0, #1.250000e-01"
+        -
+          asm_text: "vmov.f32 q0, #1.328125e-01"
+        -
+          asm_text: "vmov.f32 q0, #3.100000e+01"
+        -
+          asm_text: "vmov.f32 s16, s1"
+        -
+          asm_text: "vmov.f64 d0, d1"
+        -
+          asm_text: "vmov.i64 q0, #0xff0000ffffffffff"
+        -
+          asm_text: "vmul.i8 q0, q0, q3"
+        -
+          asm_text: "vmul.i16 q6, q0, q3"
+        -
+          asm_text: "vmul.i32 q7, q3, q6"
+        -
+          asm_text: "vqrdmulh.s8 q0, q5, q5"
+        -
+          asm_text: "vqrdmulh.s16 q1, q4, q2"
+        -
+          asm_text: "vqrdmulh.s32 q0, q5, q0"
+        -
+          asm_text: "vqdmulh.s8 q0, q4, q5"
+        -
+          asm_text: "vqdmulh.s16 q6, q4, q0"
+        -
+          asm_text: "vqdmulh.s32 q5, q0, q6"
+        -
+          asm_text: "vsub.i8 q3, q2, q5"
+        -
+          asm_text: "vsub.i16 q0, q3, q6"
+        -
+          asm_text: "vsub.i32 q0, q0, q6"
+        -
+          asm_text: "vadd.i8 q0, q2, q2"
+        -
+          asm_text: "vadd.i16 q2, q2, q1"
+        -
+          asm_text: "vadd.i32 q0, q0, q6"
+        -
+          asm_text: "vqsub.s8 q1, q6, q0"
+        -
+          asm_text: "vqsub.s16 q0, q6, q1"
+        -
+          asm_text: "vqsub.s32 q0, q0, q5"
+        -
+          asm_text: "vqsub.u8 q0, q2, q6"
+        -
+          asm_text: "vqsub.u16 q0, q7, q1"
+        -
+          asm_text: "vqsub.u32 q1, q4, q7"
+        -
+          asm_text: "vqadd.s8 q0, q1, q2"
+        -
+          asm_text: "vqadd.s8 q0, q4, q6"
+        -
+          asm_text: "vqadd.s16 q0, q5, q5"
+        -
+          asm_text: "vqadd.s32 q0, q0, q4"
+        -
+          asm_text: "vqadd.u8 q0, q4, q2"
+        -
+          asm_text: "vqadd.u16 q4, q6, q6"
+        -
+          asm_text: "vqadd.u32 q0, q1, q2"
+        -
+          asm_text: "vabd.s8 q0, q0, q2"
+        -
+          asm_text: "vabd.s16 q1, q5, q4"
+        -
+          asm_text: "vabd.s32 q2, q3, q2"
+        -
+          asm_text: "vabd.u8 q1, q6, q4"
+        -
+          asm_text: "vabd.u16 q0, q6, q2"
+        -
+          asm_text: "vabd.u32 q0, q7, q4"
+        -
+          asm_text: "vrhadd.s8 q0, q1, q1"
+        -
+          asm_text: "vrhadd.s16 q0, q1, q0"
+        -
+          asm_text: "vrhadd.s32 q0, q4, q1"
+        -
+          asm_text: "vrhadd.u8 q1, q0, q6"
+        -
+          asm_text: "vrhadd.u16 q2, q2, q5"
+        -
+          asm_text: "vrhadd.u32 q2, q3, q0"
+        -
+          asm_text: "vhsub.s8 q0, q0, q2"
+        -
+          asm_text: "vhsub.s16 q1, q3, q1"
+        -
+          asm_text: "vhsub.s32 q0, q2, q5"
+        -
+          asm_text: "vhsub.u8 q0, q4, q2"
+        -
+          asm_text: "vhsub.u16 q0, q7, q5"
+        -
+          asm_text: "vhsub.u32 q2, q6, q4"
+        -
+          asm_text: "vhadd.s8 q0, q7, q0"
+        -
+          asm_text: "vhadd.s16 q4, q0, q2"
+        -
+          asm_text: "vhadd.s32 q0, q3, q1"
+        -
+          asm_text: "vhadd.u8 q3, q0, q3"
+        -
+          asm_text: "vhadd.u16 q0, q1, q3"
+        -
+          asm_text: "vhadd.u32 q0, q1, q3"
+        -
+          asm_text: "vdup.8 q6, r8"
+        -
+          asm_text: "vdup.16 q7, lr"
+        -
+          asm_text: "vdup.32 q1, r9"
+        -
+          asm_text: "vdup.16 q0, r1"
+        -
+          asm_text: "vdup.16 q0, r1"
+        -
+          asm_text: "vcls.s8 q2, q1"
+        -
+          asm_text: "vcls.s16 q0, q4"
+        -
+          asm_text: "vcls.s32 q0, q0"
+        -
+          asm_text: "vclz.i8 q0, q7"
+        -
+          asm_text: "vclz.i16 q4, q7"
+        -
+          asm_text: "vclz.i32 q7, q5"
+        -
+          asm_text: "vneg.s8 q1, q0"
+        -
+          asm_text: "vneg.s16 q0, q1"
+        -
+          asm_text: "vneg.s32 q7, q2"
+        -
+          asm_text: "vabs.s8 q1, q1"
+        -
+          asm_text: "vabs.s16 q0, q2"
+        -
+          asm_text: "vabs.s32 q0, q7"
+        -
+          asm_text: "vqneg.s8 q0, q0"
+        -
+          asm_text: "vqneg.s16 q6, q2"
+        -
+          asm_text: "vqneg.s32 q7, q2"
+        -
+          asm_text: "vqabs.s8 q2, q4"
+        -
+          asm_text: "vqabs.s16 q0, q2"
+        -
+          asm_text: "vqabs.s32 q0, q5"
+        -
+          asm_text: "vpste"
+        -
+          asm_text: "vnegt.s8 q0, q1"
+        -
+          asm_text: "vnege.s8 q0, q1"
+        -
+          asm_text: "vpst"
+        -
+          asm_text: "vqaddt.s16 q0, q1, q2"
+        -
+          asm_text: "vpste"
+        -
+          asm_text: "vqnegt.s8 q0, q1"
+        -
+          asm_text: "vqnege.s16 q0, q1"
+        -
+          asm_text: "vmina.s8 q1, q7"
+        -
+          asm_text: "vmina.s16 q1, q4"
+        -
+          asm_text: "vmina.s32 q0, q7"
+        -
+          asm_text: "vmaxa.s8 q0, q7"
+        -
+          asm_text: "vmaxa.s16 q1, q0"
+        -
+          asm_text: "vmaxa.s32 q1, q0"
diff --git a/tests/MC/ARM/mve-interleave.s.yaml b/tests/MC/ARM/mve-interleave.s.yaml
new file mode 100644
index 000000000..d73d934d9
--- /dev/null
+++ b/tests/MC/ARM/mve-interleave.s.yaml
@@ -0,0 +1,142 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x9d, 0xfc, 0x00, 0x1e, 0x90, 0xfc, 0x00, 0x1e, 0xb0, 0xfc, 0x00, 0x1e, 0x9b, 0xfc, 0x00, 0x1e, 0xb0, 0xfc, 0x00, 0xbe, 0x90, 0xfc, 0x20, 0x1e, 0xb0, 0xfc, 0x20, 0x7e, 0x90, 0xfc, 0x80, 0x1e, 0xb0, 0xfc, 0x80, 0x1e, 0x9b, 0xfc, 0x80, 0x1e, 0xb0, 0xfc, 0x80, 0xbe, 0x90, 0xfc, 0xa0, 0x1e, 0xb0, 0xfc, 0xa0, 0x7e, 0x90, 0xfc, 0x00, 0x1f, 0xb0, 0xfc, 0x00, 0x1f, 0x9b, 0xfc, 0x00, 0x1f, 0xb0, 0xfc, 0x00, 0xbf, 0x90, 0xfc, 0x20, 0x1f, 0xb0, 0xfc, 0x20, 0x7f, 0x80, 0xfc, 0x00, 0x1e, 0xa0, 0xfc, 0x00, 0x1e, 0x8b, 0xfc, 0x00, 0x1e, 0xa0, 0xfc, 0x00, 0xbe, 0x80, 0xfc, 0x20, 0x1e, 0xa0, 0xfc, 0x20, 0x7e, 0x80, 0xfc, 0x80, 0x1e, 0xa0, 0xfc, 0x80, 0x1e, 0x8b, 0xfc, 0x80, 0x1e, 0xa0, 0xfc, 0x80, 0xbe, 0x80, 0xfc, 0xa0, 0x1e, 0xa0, 0xfc, 0xa0, 0x7e, 0x80, 0xfc, 0x00, 0x1f, 0xa0, 0xfc, 0x00, 0x1f, 0x8b, 0xfc, 0x00, 0x1f, 0xa0, 0xfc, 0x00, 0xbf, 0x80, 0xfc, 0x20, 0x1f, 0xa0, 0xfc, 0x20, 0x7f, 0x90, 0xfc, 0x01, 0x1e, 0xb0, 0xfc, 0x01, 0x1e, 0x9b, 0xfc, 0x01, 0x1e, 0xb0, 0xfc, 0x01, 0x7e, 0x90, 0xfc, 0x21, 0x1e, 0xb0, 0xfc, 0x21, 0x9e, 0x90, 0xfc, 0x41, 0x1e, 0xb0, 0xfc, 0x41, 0x1e, 0x90, 0xfc, 0x61, 0x1e, 0xb0, 0xfc, 0x61, 0x9e, 0x90, 0xfc, 0x81, 0x1e, 0xb0, 0xfc, 0x81, 0x1e, 0x9b, 0xfc, 0x81, 0x1e, 0xb0, 0xfc, 0x81, 0x7e, 0x90, 0xfc, 0xa1, 0x1e, 0xb0, 0xfc, 0xa1, 0x9e, 0x90, 0xfc, 0xc1, 0x1e, 0xb0, 0xfc, 0xc1, 0x1e, 0x90, 0xfc, 0xe1, 0x1e, 0xb0, 0xfc, 0xe1, 0x9e, 0x90, 0xfc, 0x01, 0x1f, 0xb0, 0xfc, 0x01, 0x1f, 0x9b, 0xfc, 0x01, 0x1f, 0xb0, 0xfc, 0x01, 0x7f, 0x90, 0xfc, 0x21, 0x1f, 0xb0, 0xfc, 0x21, 0x9f, 0x90, 0xfc, 0x41, 0x1f, 0xb0, 0xfc, 0x41, 0x1f, 0x90, 0xfc, 0x61, 0x1f, 0xb0, 0xfc, 0x61, 0x9f ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_MCLASS", "CS_MODE_V8", "CS_MODE_THUMB" ]
+    expected:
+      insns:
+        -
+          asm_text: "vld20.8 {q0, q1}, [sp]"
+        -
+          asm_text: "vld20.8 {q0, q1}, [r0]"
+        -
+          asm_text: "vld20.8 {q0, q1}, [r0]!"
+        -
+          asm_text: "vld20.8 {q0, q1}, [r11]"
+        -
+          asm_text: "vld20.8 {q5, q6}, [r0]!"
+        -
+          asm_text: "vld21.8 {q0, q1}, [r0]"
+        -
+          asm_text: "vld21.8 {q3, q4}, [r0]!"
+        -
+          asm_text: "vld20.16 {q0, q1}, [r0]"
+        -
+          asm_text: "vld20.16 {q0, q1}, [r0]!"
+        -
+          asm_text: "vld20.16 {q0, q1}, [r11]"
+        -
+          asm_text: "vld20.16 {q5, q6}, [r0]!"
+        -
+          asm_text: "vld21.16 {q0, q1}, [r0]"
+        -
+          asm_text: "vld21.16 {q3, q4}, [r0]!"
+        -
+          asm_text: "vld20.32 {q0, q1}, [r0]"
+        -
+          asm_text: "vld20.32 {q0, q1}, [r0]!"
+        -
+          asm_text: "vld20.32 {q0, q1}, [r11]"
+        -
+          asm_text: "vld20.32 {q5, q6}, [r0]!"
+        -
+          asm_text: "vld21.32 {q0, q1}, [r0]"
+        -
+          asm_text: "vld21.32 {q3, q4}, [r0]!"
+        -
+          asm_text: "vst20.8 {q0, q1}, [r0]"
+        -
+          asm_text: "vst20.8 {q0, q1}, [r0]!"
+        -
+          asm_text: "vst20.8 {q0, q1}, [r11]"
+        -
+          asm_text: "vst20.8 {q5, q6}, [r0]!"
+        -
+          asm_text: "vst21.8 {q0, q1}, [r0]"
+        -
+          asm_text: "vst21.8 {q3, q4}, [r0]!"
+        -
+          asm_text: "vst20.16 {q0, q1}, [r0]"
+        -
+          asm_text: "vst20.16 {q0, q1}, [r0]!"
+        -
+          asm_text: "vst20.16 {q0, q1}, [r11]"
+        -
+          asm_text: "vst20.16 {q5, q6}, [r0]!"
+        -
+          asm_text: "vst21.16 {q0, q1}, [r0]"
+        -
+          asm_text: "vst21.16 {q3, q4}, [r0]!"
+        -
+          asm_text: "vst20.32 {q0, q1}, [r0]"
+        -
+          asm_text: "vst20.32 {q0, q1}, [r0]!"
+        -
+          asm_text: "vst20.32 {q0, q1}, [r11]"
+        -
+          asm_text: "vst20.32 {q5, q6}, [r0]!"
+        -
+          asm_text: "vst21.32 {q0, q1}, [r0]"
+        -
+          asm_text: "vst21.32 {q3, q4}, [r0]!"
+        -
+          asm_text: "vld40.8 {q0, q1, q2, q3}, [r0]"
+        -
+          asm_text: "vld40.8 {q0, q1, q2, q3}, [r0]!"
+        -
+          asm_text: "vld40.8 {q0, q1, q2, q3}, [r11]"
+        -
+          asm_text: "vld40.8 {q3, q4, q5, q6}, [r0]!"
+        -
+          asm_text: "vld41.8 {q0, q1, q2, q3}, [r0]"
+        -
+          asm_text: "vld41.8 {q4, q5, q6, q7}, [r0]!"
+        -
+          asm_text: "vld42.8 {q0, q1, q2, q3}, [r0]"
+        -
+          asm_text: "vld42.8 {q0, q1, q2, q3}, [r0]!"
+        -
+          asm_text: "vld43.8 {q0, q1, q2, q3}, [r0]"
+        -
+          asm_text: "vld43.8 {q4, q5, q6, q7}, [r0]!"
+        -
+          asm_text: "vld40.16 {q0, q1, q2, q3}, [r0]"
+        -
+          asm_text: "vld40.16 {q0, q1, q2, q3}, [r0]!"
+        -
+          asm_text: "vld40.16 {q0, q1, q2, q3}, [r11]"
+        -
+          asm_text: "vld40.16 {q3, q4, q5, q6}, [r0]!"
+        -
+          asm_text: "vld41.16 {q0, q1, q2, q3}, [r0]"
+        -
+          asm_text: "vld41.16 {q4, q5, q6, q7}, [r0]!"
+        -
+          asm_text: "vld42.16 {q0, q1, q2, q3}, [r0]"
+        -
+          asm_text: "vld42.16 {q0, q1, q2, q3}, [r0]!"
+        -
+          asm_text: "vld43.16 {q0, q1, q2, q3}, [r0]"
+        -
+          asm_text: "vld43.16 {q4, q5, q6, q7}, [r0]!"
+        -
+          asm_text: "vld40.32 {q0, q1, q2, q3}, [r0]"
+        -
+          asm_text: "vld40.32 {q0, q1, q2, q3}, [r0]!"
+        -
+          asm_text: "vld40.32 {q0, q1, q2, q3}, [r11]"
+        -
+          asm_text: "vld40.32 {q3, q4, q5, q6}, [r0]!"
+        -
+          asm_text: "vld41.32 {q0, q1, q2, q3}, [r0]"
+        -
+          asm_text: "vld41.32 {q4, q5, q6, q7}, [r0]!"
+        -
+          asm_text: "vld42.32 {q0, q1, q2, q3}, [r0]"
+        -
+          asm_text: "vld42.32 {q0, q1, q2, q3}, [r0]!"
+        -
+          asm_text: "vld43.32 {q0, q1, q2, q3}, [r0]"
+        -
+          asm_text: "vld43.32 {q4, q5, q6, q7}, [r0]!"
diff --git a/tests/MC/ARM/mve-load-store.s.yaml b/tests/MC/ARM/mve-load-store.s.yaml
new file mode 100644
index 000000000..363333fcb
--- /dev/null
+++ b/tests/MC/ARM/mve-load-store.s.yaml
@@ -0,0 +1,892 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x90, 0xed, 0x00, 0x1e, 0x90, 0xed, 0x00, 0x3e, 0x9b, 0xed, 0x00, 0x1e, 0x9b, 0xed, 0x00, 0x7e, 0x94, 0xed, 0x38, 0x1e, 0x94, 0xed, 0x38, 0x9e, 0x98, 0xed, 0x38, 0x1e, 0xb4, 0xed, 0x38, 0xbe, 0xb4, 0xed, 0x38, 0xbe, 0x34, 0xec, 0x19, 0xbe, 0x3a, 0xec, 0x19, 0xbe, 0x1d, 0xed, 0x19, 0xbe, 0x1d, 0xed, 0x7f, 0xbe, 0x80, 0xed, 0x00, 0x1e, 0x80, 0xed, 0x00, 0x3e, 0x8b, 0xed, 0x00, 0x1e, 0x8b, 0xed, 0x00, 0x7e, 0x84, 0xed, 0x38, 0x1e, 0x84, 0xed, 0x38, 0x9e, 0x88, 0xed, 0x38, 0x1e, 0xa4, 0xed, 0x38, 0xbe, 0xa4, 0xed, 0x38, 0xbe, 0x24, 0xec, 0x19, 0xbe, 0x2a, 0xec, 0x19, 0xbe, 0x0d, 0xed, 0x19, 0xbe, 0x8d, 0xed, 0x7f, 0xbe, 0x90, 0xfd, 0x80, 0x0e, 0x90, 0xfd, 0x80, 0x2e, 0x97, 0xfd, 0x80, 0x0e, 0x97, 0xfd, 0x80, 0x6e, 0x94, 0xfd, 0xb8, 0x0e, 0x94, 0xfd, 0xb8, 0x8e, 0x92, 0xfd, 0xb8, 0x0e, 0xb4, 0xfd, 0xb8, 0xae, 0xb4, 0xfd, 0xb8, 0xae, 0x34, 0xfc, 0x81, 0xae, 0x33, 0xfc, 0x99, 0xae, 0x16, 0xfd, 0x99, 0xae, 0x16, 0xfd, 0xc0, 0xae, 0x90, 0xed, 0x80, 0x0e, 0x90, 0xed, 0x80, 0x2e, 0x97, 0xed, 0x80, 0x0e, 0x97, 0xed, 0x80, 0x6e, 0x94, 0xed, 0xb8, 0x0e, 0x94, 0xed, 0xb8, 0x8e, 0x92, 0xed, 0xb8, 0x0e, 0xb4, 0xed, 0xb8, 0xae, 0xb4, 0xed, 0xb8, 0xae, 0x34, 0xec, 0x99, 0xae, 0x33, 0xec, 0x99, 0xae, 0x16, 0xed, 0x99, 0xae, 0x16, 0xed, 0xc0, 0xae, 0x80, 0xed, 0x80, 0x0e, 0x80, 0xed, 0x80, 0x2e, 0x87, 0xed, 0x80, 0x0e, 0x87, 0xed, 0x80, 0x6e, 0x84, 0xed, 0xb8, 0x0e, 0x84, 0xed, 0xb8, 0x8e, 0x85, 0xed, 0xb8, 0x0e, 0xa4, 0xed, 0xb8, 0xae, 0xa4, 0xed, 0xb8, 0xae, 0x24, 0xec, 0x99, 0xae, 0x23, 0xec, 0x99, 0xae, 0x02, 0xed, 0x99, 0xae, 0x02, 0xed, 0xc0, 0xae, 0x90, 0xfd, 0x00, 0x0f, 0x90, 0xfd, 0x00, 0x2f, 0x97, 0xfd, 0x00, 0x0f, 0x97, 0xfd, 0x00, 0x6f, 0x94, 0xfd, 0x38, 0x0f, 0x94, 0xfd, 0x38, 0x8f, 0x92, 0xfd, 0x38, 0x0f, 0xb4, 0xfd, 0x38, 0xaf, 0xb4, 0xfd, 0x38, 0xaf, 0x34, 0xfc, 0x19, 0xaf, 0x33, 0xfc, 0x19, 0xaf, 0x16, 0xfd, 0x19, 0xaf, 0x16, 0xfd, 0x40, 0xaf, 0x90, 0xed, 0x00, 0x0f, 0x90, 0xed, 0x00, 0x2f, 0x97, 0xed, 0x00, 0x0f, 0x97, 0xed, 0x00, 0x6f, 0x94, 0xed, 0x38, 0x0f, 0x94, 0xed, 0x38, 0x8f, 0x92, 0xed, 0x38, 0x0f, 0xb4, 0xed, 0x38, 0xaf, 0xb4, 0xed, 0x38, 0xaf, 0x34, 0xec, 0x19, 0xaf, 0x33, 0xec, 0x19, 0xaf, 0x16, 0xed, 0x19, 0xaf, 0x16, 0xed, 0x40, 0xaf, 0x80, 0xed, 0x00, 0x0f, 0x80, 0xed, 0x00, 0x2f, 0x87, 0xed, 0x00, 0x0f, 0x87, 0xed, 0x00, 0x6f, 0x84, 0xed, 0x38, 0x0f, 0x84, 0xed, 0x38, 0x8f, 0x85, 0xed, 0x38, 0x0f, 0xa4, 0xed, 0x38, 0xaf, 0xa4, 0xed, 0x38, 0xaf, 0x24, 0xec, 0x19, 0xaf, 0x23, 0xec, 0x19, 0xaf, 0x02, 0xed, 0x19, 0xaf, 0x02, 0xed, 0x40, 0xaf, 0x90, 0xed, 0x80, 0x1e, 0x90, 0xed, 0x80, 0x3e, 0x9b, 0xed, 0x80, 0x1e, 0x9b, 0xed, 0x80, 0x7e, 0x94, 0xed, 0x9c, 0x1e, 0x94, 0xed, 0x9c, 0x9e, 0x98, 0xed, 0x9c, 0x1e, 0xb4, 0xed, 0x9c, 0xbe, 0xb4, 0xed, 0x9c, 0xbe, 0x34, 0xec, 0x8d, 0xbe, 0x3a, 0xec, 0x8d, 0xbe, 0x1d, 0xed, 0x8d, 0xbe, 0x1d, 0xed, 0xa0, 0xbe, 0x1d, 0xed, 0xff, 0xbe, 0xba, 0xec, 0xff, 0xbe, 0x80, 0xed, 0x80, 0x1e, 0x80, 0xed, 0x80, 0x3e, 0x8b, 0xed, 0x80, 0x1e, 0x8b, 0xed, 0x80, 0x7e, 0x84, 0xed, 0x9c, 0x1e, 0x84, 0xed, 0x9c, 0x9e, 0x88, 0xed, 0x9c, 0x1e, 0xa4, 0xed, 0x9c, 0xbe, 0xa4, 0xed, 0x9c, 0xbe, 0x24, 0xec, 0x8d, 0xbe, 0x2a, 0xec, 0x8d, 0xbe, 0x0d, 0xed, 0x8d, 0xbe, 0x0d, 0xed, 0xa0, 0xbe, 0x0d, 0xed, 0xff, 0xbe, 0xaa, 0xec, 0xff, 0xbe, 0x98, 0xfd, 0x00, 0x0f, 0x98, 0xfd, 0x00, 0x2f, 0x9f, 0xfd, 0x00, 0x0f, 0x9f, 0xfd, 0x00, 0x6f, 0x9c, 0xfd, 0x1c, 0x0f, 0x9c, 0xfd, 0x1c, 0x8f, 0x9a, 0xfd, 0x1c, 0x0f, 0xbc, 0xfd, 0x1c, 0xaf, 0xbc, 0xfd, 0x1c, 0xaf, 0x3c, 0xfc, 0x0d, 0xaf, 0x3b, 0xfc, 0x0d, 0xaf, 0x1e, 0xfd, 0x0d, 0xaf, 0x1e, 0xfd, 0x20, 0xaf, 0x1e, 0xfd, 0x7f, 0xaf, 0xbc, 0xfd, 0x7f, 0xaf, 0x98, 0xed, 0x00, 0x0f, 0x98, 0xed, 0x00, 0x2f, 0x9f, 0xed, 0x00, 0x0f, 0x9f, 0xed, 0x00, 0x6f, 0x9c, 0xed, 0x1c, 0x0f, 0x9c, 0xed, 0x1c, 0x8f, 0x9a, 0xed, 0x1c, 0x0f, 0xbc, 0xed, 0x1c, 0xaf, 0xbc, 0xed, 0x1c, 0xaf, 0x3c, 0xec, 0x0d, 0xaf, 0x3b, 0xec, 0x0d, 0xaf, 0x1e, 0xed, 0x0d, 0xaf, 0x1e, 0xed, 0x20, 0xaf, 0x1e, 0xed, 0x7f, 0xaf, 0xbc, 0xed, 0x7f, 0xaf, 0x88, 0xed, 0x00, 0x0f, 0x88, 0xed, 0x00, 0x2f, 0x8f, 0xed, 0x00, 0x0f, 0x8f, 0xed, 0x00, 0x6f, 0x8c, 0xed, 0x1c, 0x0f, 0x8c, 0xed, 0x1c, 0x8f, 0x8d, 0xed, 0x1c, 0x0f, 0xac, 0xed, 0x1c, 0xaf, 0xac, 0xed, 0x1c, 0xaf, 0x2c, 0xec, 0x0d, 0xaf, 0x2b, 0xec, 0x0d, 0xaf, 0x0a, 0xed, 0x0d, 0xaf, 0x0a, 0xed, 0x20, 0xaf, 0x0a, 0xed, 0x7f, 0xaf, 0xac, 0xed, 0x7f, 0xaf, 0x90, 0xed, 0x00, 0x1f, 0x90, 0xed, 0x00, 0x3f, 0x9b, 0xed, 0x00, 0x1f, 0x9b, 0xed, 0x00, 0x7f, 0x94, 0xed, 0x0e, 0x1f, 0x94, 0xed, 0x0e, 0x9f, 0x98, 0xed, 0x0e, 0x1f, 0xb4, 0xed, 0x0e, 0xbf, 0xb4, 0xed, 0x0e, 0xbf, 0x34, 0xec, 0x07, 0xbf, 0x3a, 0xec, 0x07, 0xbf, 0x1d, 0xed, 0x07, 0xbf, 0x1d, 0xed, 0x10, 0xbf, 0x1d, 0xed, 0x7f, 0xbf, 0xb4, 0xed, 0x7f, 0xbf, 0x80, 0xed, 0x00, 0x1f, 0x80, 0xed, 0x00, 0x3f, 0x8b, 0xed, 0x00, 0x1f, 0x8b, 0xed, 0x00, 0x7f, 0x84, 0xed, 0x0e, 0x1f, 0x84, 0xed, 0x0e, 0x9f, 0x88, 0xed, 0x0e, 0x1f, 0xa4, 0xed, 0x0e, 0xbf, 0xa4, 0xed, 0x0e, 0xbf, 0x24, 0xec, 0x07, 0xbf, 0x2a, 0xec, 0x07, 0xbf, 0x0d, 0xed, 0x07, 0xbf, 0x0d, 0xed, 0x10, 0xbf, 0x0d, 0xed, 0x7f, 0xbf, 0xa4, 0xed, 0x7f, 0xbf, 0x90, 0xfc, 0x02, 0x0e, 0x9a, 0xfc, 0x02, 0x6e, 0x90, 0xfc, 0x82, 0x0e, 0x99, 0xfc, 0x82, 0x6e, 0x90, 0xec, 0x82, 0x0e, 0x9d, 0xec, 0x82, 0x6e, 0x90, 0xfc, 0x02, 0x0f, 0x90, 0xfc, 0x02, 0x6f, 0x90, 0xec, 0x02, 0x0f, 0x90, 0xec, 0x02, 0x6f, 0x90, 0xfc, 0x92, 0x0e, 0x90, 0xfc, 0x92, 0x6e, 0x90, 0xfc, 0x12, 0x0f, 0x90, 0xfc, 0x12, 0x6f, 0x90, 0xec, 0x12, 0x0f, 0x90, 0xec, 0x12, 0x6f, 0x90, 0xfc, 0x93, 0x0e, 0x90, 0xfc, 0x42, 0x0f, 0x90, 0xfc, 0x42, 0x6f, 0x90, 0xfc, 0x43, 0x0f, 0x9d, 0xfc, 0x43, 0x0f, 0x90, 0xfc, 0xd2, 0x0f, 0x90, 0xfc, 0xd2, 0x6f, 0x90, 0xfc, 0xd3, 0x0f, 0x9d, 0xfc, 0xd3, 0x0f, 0x80, 0xec, 0x02, 0x0e, 0x8a, 0xec, 0x02, 0x6e, 0x80, 0xec, 0x06, 0x6e, 0x80, 0xec, 0x82, 0x0e, 0x8d, 0xec, 0x82, 0x6e, 0x80, 0xec, 0x86, 0x6e, 0x80, 0xec, 0x02, 0x0f, 0x80, 0xec, 0x02, 0x6f, 0x80, 0xec, 0x06, 0x6f, 0x80, 0xec, 0x92, 0x0e, 0x80, 0xec, 0x92, 0x6e, 0x80, 0xec, 0x96, 0x6e, 0x80, 0xec, 0x12, 0x0f, 0x80, 0xec, 0x12, 0x6f, 0x80, 0xec, 0x16, 0x6f, 0x80, 0xec, 0x93, 0x0e, 0x88, 0xec, 0x17, 0x6f, 0x80, 0xec, 0x42, 0x0f, 0x80, 0xec, 0x42, 0x6f, 0x80, 0xec, 0x46, 0x6f, 0x80, 0xec, 0x43, 0x0f, 0x8d, 0xec, 0x43, 0x0f, 0x80, 0xec, 0xd2, 0x0f, 0x80, 0xec, 0xd2, 0x6f, 0x80, 0xec, 0xd6, 0x6f, 0x80, 0xec, 0xd3, 0x0f, 0x8d, 0xec, 0xd3, 0x0f, 0x92, 0xfd, 0x00, 0x1e, 0x92, 0xfd, 0x00, 0xfe, 0xb2, 0xfd, 0x00, 0xfe, 0x92, 0xfd, 0x01, 0xfe, 0x12, 0xfd, 0x01, 0xfe, 0x92, 0xfd, 0x7f, 0xfe, 0x12, 0xfd, 0x7f, 0xfe, 0x92, 0xfd, 0x42, 0xfe, 0xb2, 0xfd, 0x01, 0xfe, 0x82, 0xfd, 0x00, 0x1e, 0x82, 0xfd, 0x00, 0x3e, 0x82, 0xfd, 0x00, 0xfe, 0xa2, 0xfd, 0x00, 0xfe, 0x8e, 0xfd, 0x00, 0xfe, 0x82, 0xfd, 0x01, 0xfe, 0x02, 0xfd, 0x01, 0xfe, 0x82, 0xfd, 0x7f, 0xfe, 0x02, 0xfd, 0x7f, 0xfe, 0xa2, 0xfd, 0x42, 0xfe, 0x92, 0xfd, 0x00, 0x1f, 0x92, 0xfd, 0x00, 0xff, 0xb2, 0xfd, 0x00, 0xff, 0x92, 0xfd, 0x01, 0xff, 0x12, 0xfd, 0x01, 0xff, 0x92, 0xfd, 0x7f, 0xff, 0x12, 0xfd, 0x7f, 0xff, 0x92, 0xfd, 0x21, 0xff, 0x92, 0xfd, 0x4e, 0xff, 0x92, 0xfd, 0x21, 0xff, 0x32, 0xfd, 0x7f, 0xff, 0x82, 0xfd, 0x00, 0x1f, 0x82, 0xfd, 0x00, 0x3f, 0x82, 0xfd, 0x00, 0xff, 0xa2, 0xfd, 0x00, 0xff, 0x8e, 0xfd, 0x00, 0xff, 0x82, 0xfd, 0x01, 0xff, 0x22, 0xfd, 0x01, 0xff, 0x82, 0xfd, 0x7f, 0xff, 0x02, 0xfd, 0x7f, 0xff, 0x82, 0xfd, 0x21, 0xff, 0x82, 0xfd, 0x4e, 0xff, 0x82, 0xfd, 0x21, 0xff, 0x90, 0xed, 0x00, 0x1e, 0x90, 0xed, 0x00, 0x1e, 0x98, 0xed, 0x38, 0x1e, 0x98, 0xed, 0x38, 0x1e, 0xb4, 0xed, 0x38, 0xbe, 0xb4, 0xed, 0x38, 0xbe, 0x80, 0xed, 0x00, 0x1e, 0x80, 0xed, 0x00, 0x1e, 0x84, 0xed, 0x38, 0x9e, 0x84, 0xed, 0x38, 0x9e, 0xa4, 0xed, 0x38, 0xbe, 0xa4, 0xed, 0x38, 0xbe, 0x90, 0xed, 0x80, 0x1e, 0x90, 0xed, 0x80, 0x1e, 0x90, 0xed, 0x80, 0x1e, 0x94, 0xed, 0x9c, 0x1e, 0x94, 0xed, 0x9c, 0x1e, 0x94, 0xed, 0x9c, 0x1e, 0xb4, 0xed, 0x9c, 0xbe, 0xb4, 0xed, 0x9c, 0xbe, 0xb4, 0xed, 0x9c, 0xbe, 0x80, 0xed, 0x80, 0x1e, 0x80, 0xed, 0x80, 0x1e, 0x80, 0xed, 0x80, 0x1e, 0x84, 0xed, 0x9c, 0x1e, 0x84, 0xed, 0x9c, 0x1e, 0x84, 0xed, 0x9c, 0x1e, 0xa4, 0xed, 0x9c, 0xbe, 0xa4, 0xed, 0x9c, 0xbe, 0xa4, 0xed, 0x9c, 0xbe, 0x90, 0xed, 0x00, 0x1f, 0x90, 0xed, 0x00, 0x1f, 0x90, 0xed, 0x00, 0x1f, 0x94, 0xed, 0x0e, 0x1f, 0x94, 0xed, 0x0e, 0x1f, 0x94, 0xed, 0x0e, 0x1f, 0xb4, 0xed, 0x0e, 0xbf, 0xb4, 0xed, 0x0e, 0xbf, 0xb4, 0xed, 0x0e, 0xbf, 0x80, 0xed, 0x00, 0x1f, 0x80, 0xed, 0x00, 0x1f, 0x80, 0xed, 0x00, 0x1f, 0x84, 0xed, 0x0e, 0x1f, 0x84, 0xed, 0x0e, 0x1f, 0x84, 0xed, 0x0e, 0x1f, 0xa4, 0xed, 0x0e, 0xbf, 0xa4, 0xed, 0x0e, 0xbf, 0xa4, 0xed, 0x0e, 0xbf, 0x90, 0xfc, 0x02, 0x0e, 0x90, 0xfc, 0x02, 0x0e, 0x90, 0xfc, 0x92, 0x6e, 0x90, 0xfc, 0x92, 0x6e, 0x90, 0xfc, 0x92, 0x6e, 0x90, 0xfc, 0x93, 0x0e, 0x90, 0xfc, 0x93, 0x0e, 0x90, 0xfc, 0x93, 0x0e, 0x90, 0xfc, 0x42, 0x0f, 0x90, 0xfc, 0x42, 0x0f, 0x90, 0xfc, 0x42, 0x0f, 0x90, 0xfc, 0x43, 0x0f, 0x90, 0xfc, 0x43, 0x0f, 0x90, 0xfc, 0x43, 0x0f, 0x90, 0xfc, 0xd2, 0x0f, 0x90, 0xfc, 0xd2, 0x0f, 0x90, 0xfc, 0xd2, 0x0f, 0x90, 0xfc, 0xd3, 0x0f, 0x90, 0xfc, 0xd3, 0x0f, 0x90, 0xfc, 0xd3, 0x0f, 0x80, 0xec, 0x02, 0x0e, 0x80, 0xec, 0x02, 0x0e, 0x80, 0xec, 0x92, 0x6e, 0x80, 0xec, 0x92, 0x6e, 0x80, 0xec, 0x92, 0x6e, 0x80, 0xec, 0x93, 0x0e, 0x80, 0xec, 0x93, 0x0e, 0x80, 0xec, 0x93, 0x0e, 0x80, 0xec, 0x42, 0x0f, 0x80, 0xec, 0x42, 0x0f, 0x80, 0xec, 0x42, 0x0f, 0x80, 0xec, 0x43, 0x0f, 0x80, 0xec, 0x43, 0x0f, 0x80, 0xec, 0x43, 0x0f, 0x80, 0xec, 0xd2, 0x6f, 0x80, 0xec, 0xd2, 0x6f, 0x80, 0xec, 0xd2, 0x6f, 0x80, 0xec, 0xd3, 0x0f, 0x80, 0xec, 0xd3, 0x0f, 0x80, 0xec, 0xd3, 0x0f, 0x92, 0xfd, 0x00, 0x1e, 0x92, 0xfd, 0x00, 0x1e, 0x92, 0xfd, 0x00, 0x1e, 0xb2, 0xfd, 0x00, 0xfe, 0xb2, 0xfd, 0x00, 0xfe, 0xb2, 0xfd, 0x00, 0xfe, 0x92, 0xfd, 0x01, 0xfe, 0x92, 0xfd, 0x01, 0xfe, 0x92, 0xfd, 0x01, 0xfe, 0xb2, 0xfd, 0x01, 0xfe, 0xb2, 0xfd, 0x01, 0xfe, 0xb2, 0xfd, 0x01, 0xfe, 0x82, 0xfd, 0x00, 0x1e, 0x82, 0xfd, 0x00, 0x1e, 0x82, 0xfd, 0x00, 0x1e, 0xa2, 0xfd, 0x00, 0xfe, 0xa2, 0xfd, 0x00, 0xfe, 0xa2, 0xfd, 0x00, 0xfe, 0x82, 0xfd, 0x7f, 0xfe, 0x82, 0xfd, 0x7f, 0xfe, 0x82, 0xfd, 0x7f, 0xfe, 0xa2, 0xfd, 0x42, 0xfe, 0xa2, 0xfd, 0x42, 0xfe, 0xa2, 0xfd, 0x42, 0xfe, 0x92, 0xfd, 0x00, 0x1f, 0x92, 0xfd, 0x00, 0x1f, 0x92, 0xfd, 0x00, 0x1f, 0xb2, 0xfd, 0x00, 0xff, 0xb2, 0xfd, 0x00, 0xff, 0xb2, 0xfd, 0x00, 0xff, 0x92, 0xfd, 0x01, 0xff, 0x92, 0xfd, 0x01, 0xff, 0x92, 0xfd, 0x01, 0xff, 0x32, 0xfd, 0x7f, 0xff, 0x32, 0xfd, 0x7f, 0xff, 0x32, 0xfd, 0x7f, 0xff, 0x82, 0xfd, 0x00, 0x1f, 0x82, 0xfd, 0x00, 0x1f, 0x82, 0xfd, 0x00, 0x1f, 0xa2, 0xfd, 0x00, 0xff, 0xa2, 0xfd, 0x00, 0xff, 0xa2, 0xfd, 0x00, 0xff, 0x82, 0xfd, 0x7f, 0xff, 0x82, 0xfd, 0x7f, 0xff, 0x82, 0xfd, 0x7f, 0xff, 0x22, 0xfd, 0x01, 0xff, 0x22, 0xfd, 0x01, 0xff, 0x22, 0xfd, 0x01, 0xff, 0x71, 0xfe, 0x4d, 0x8f, 0xa2, 0xfd, 0x42, 0xfe, 0x92, 0xfd, 0x01, 0xff ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_MCLASS", "CS_MODE_V8", "CS_MODE_THUMB" ]
+    expected:
+      insns:
+        -
+          asm_text: "vldrb.u8 q0, [r0]"
+        -
+          asm_text: "vldrb.u8 q1, [r0]"
+        -
+          asm_text: "vldrb.u8 q0, [r11]"
+        -
+          asm_text: "vldrb.u8 q3, [r11]"
+        -
+          asm_text: "vldrb.u8 q0, [r4, #0x38]"
+        -
+          asm_text: "vldrb.u8 q4, [r4, #0x38]"
+        -
+          asm_text: "vldrb.u8 q0, [r8, #0x38]"
+        -
+          asm_text: "vldrb.u8 q5, [r4, #0x38]!"
+        -
+          asm_text: "vldrb.u8 q5, [r4, #0x38]!"
+        -
+          asm_text: "vldrb.u8 q5, [r4], #-0x19"
+        -
+          asm_text: "vldrb.u8 q5, [r10], #-0x19"
+        -
+          asm_text: "vldrb.u8 q5, [sp, #-0x19]"
+        -
+          asm_text: "vldrb.u8 q5, [sp, #-0x7f]"
+        -
+          asm_text: "vstrb.8 q0, [r0]"
+        -
+          asm_text: "vstrb.8 q1, [r0]"
+        -
+          asm_text: "vstrb.8 q0, [r11]"
+        -
+          asm_text: "vstrb.8 q3, [r11]"
+        -
+          asm_text: "vstrb.8 q0, [r4, #0x38]"
+        -
+          asm_text: "vstrb.8 q4, [r4, #0x38]"
+        -
+          asm_text: "vstrb.8 q0, [r8, #0x38]"
+        -
+          asm_text: "vstrb.8 q5, [r4, #0x38]!"
+        -
+          asm_text: "vstrb.8 q5, [r4, #0x38]!"
+        -
+          asm_text: "vstrb.8 q5, [r4], #-0x19"
+        -
+          asm_text: "vstrb.8 q5, [r10], #-0x19"
+        -
+          asm_text: "vstrb.8 q5, [sp, #-0x19]"
+        -
+          asm_text: "vstrb.8 q5, [sp, #0x7f]"
+        -
+          asm_text: "vldrb.u16 q0, [r0]"
+        -
+          asm_text: "vldrb.u16 q1, [r0]"
+        -
+          asm_text: "vldrb.u16 q0, [r7]"
+        -
+          asm_text: "vldrb.u16 q3, [r7]"
+        -
+          asm_text: "vldrb.u16 q0, [r4, #0x38]"
+        -
+          asm_text: "vldrb.u16 q4, [r4, #0x38]"
+        -
+          asm_text: "vldrb.u16 q0, [r2, #0x38]"
+        -
+          asm_text: "vldrb.u16 q5, [r4, #0x38]!"
+        -
+          asm_text: "vldrb.u16 q5, [r4, #0x38]!"
+        -
+          asm_text: "vldrb.u16 q5, [r4], #-1"
+        -
+          asm_text: "vldrb.u16 q5, [r3], #-0x19"
+        -
+          asm_text: "vldrb.u16 q5, [r6, #-0x19]"
+        -
+          asm_text: "vldrb.u16 q5, [r6, #-0x40]"
+        -
+          asm_text: "vldrb.s16 q0, [r0]"
+        -
+          asm_text: "vldrb.s16 q1, [r0]"
+        -
+          asm_text: "vldrb.s16 q0, [r7]"
+        -
+          asm_text: "vldrb.s16 q3, [r7]"
+        -
+          asm_text: "vldrb.s16 q0, [r4, #0x38]"
+        -
+          asm_text: "vldrb.s16 q4, [r4, #0x38]"
+        -
+          asm_text: "vldrb.s16 q0, [r2, #0x38]"
+        -
+          asm_text: "vldrb.s16 q5, [r4, #0x38]!"
+        -
+          asm_text: "vldrb.s16 q5, [r4, #0x38]!"
+        -
+          asm_text: "vldrb.s16 q5, [r4], #-0x19"
+        -
+          asm_text: "vldrb.s16 q5, [r3], #-0x19"
+        -
+          asm_text: "vldrb.s16 q5, [r6, #-0x19]"
+        -
+          asm_text: "vldrb.s16 q5, [r6, #-0x40]"
+        -
+          asm_text: "vstrb.16 q0, [r0]"
+        -
+          asm_text: "vstrb.16 q1, [r0]"
+        -
+          asm_text: "vstrb.16 q0, [r7]"
+        -
+          asm_text: "vstrb.16 q3, [r7]"
+        -
+          asm_text: "vstrb.16 q0, [r4, #0x38]"
+        -
+          asm_text: "vstrb.16 q4, [r4, #0x38]"
+        -
+          asm_text: "vstrb.16 q0, [r5, #0x38]"
+        -
+          asm_text: "vstrb.16 q5, [r4, #0x38]!"
+        -
+          asm_text: "vstrb.16 q5, [r4, #0x38]!"
+        -
+          asm_text: "vstrb.16 q5, [r4], #-0x19"
+        -
+          asm_text: "vstrb.16 q5, [r3], #-0x19"
+        -
+          asm_text: "vstrb.16 q5, [r2, #-0x19]"
+        -
+          asm_text: "vstrb.16 q5, [r2, #-0x40]"
+        -
+          asm_text: "vldrb.u32 q0, [r0]"
+        -
+          asm_text: "vldrb.u32 q1, [r0]"
+        -
+          asm_text: "vldrb.u32 q0, [r7]"
+        -
+          asm_text: "vldrb.u32 q3, [r7]"
+        -
+          asm_text: "vldrb.u32 q0, [r4, #0x38]"
+        -
+          asm_text: "vldrb.u32 q4, [r4, #0x38]"
+        -
+          asm_text: "vldrb.u32 q0, [r2, #0x38]"
+        -
+          asm_text: "vldrb.u32 q5, [r4, #0x38]!"
+        -
+          asm_text: "vldrb.u32 q5, [r4, #0x38]!"
+        -
+          asm_text: "vldrb.u32 q5, [r4], #-0x19"
+        -
+          asm_text: "vldrb.u32 q5, [r3], #-0x19"
+        -
+          asm_text: "vldrb.u32 q5, [r6, #-0x19]"
+        -
+          asm_text: "vldrb.u32 q5, [r6, #-0x40]"
+        -
+          asm_text: "vldrb.s32 q0, [r0]"
+        -
+          asm_text: "vldrb.s32 q1, [r0]"
+        -
+          asm_text: "vldrb.s32 q0, [r7]"
+        -
+          asm_text: "vldrb.s32 q3, [r7]"
+        -
+          asm_text: "vldrb.s32 q0, [r4, #0x38]"
+        -
+          asm_text: "vldrb.s32 q4, [r4, #0x38]"
+        -
+          asm_text: "vldrb.s32 q0, [r2, #0x38]"
+        -
+          asm_text: "vldrb.s32 q5, [r4, #0x38]!"
+        -
+          asm_text: "vldrb.s32 q5, [r4, #0x38]!"
+        -
+          asm_text: "vldrb.s32 q5, [r4], #-0x19"
+        -
+          asm_text: "vldrb.s32 q5, [r3], #-0x19"
+        -
+          asm_text: "vldrb.s32 q5, [r6, #-0x19]"
+        -
+          asm_text: "vldrb.s32 q5, [r6, #-0x40]"
+        -
+          asm_text: "vstrb.32 q0, [r0]"
+        -
+          asm_text: "vstrb.32 q1, [r0]"
+        -
+          asm_text: "vstrb.32 q0, [r7]"
+        -
+          asm_text: "vstrb.32 q3, [r7]"
+        -
+          asm_text: "vstrb.32 q0, [r4, #0x38]"
+        -
+          asm_text: "vstrb.32 q4, [r4, #0x38]"
+        -
+          asm_text: "vstrb.32 q0, [r5, #0x38]"
+        -
+          asm_text: "vstrb.32 q5, [r4, #0x38]!"
+        -
+          asm_text: "vstrb.32 q5, [r4, #0x38]!"
+        -
+          asm_text: "vstrb.32 q5, [r4], #-0x19"
+        -
+          asm_text: "vstrb.32 q5, [r3], #-0x19"
+        -
+          asm_text: "vstrb.32 q5, [r2, #-0x19]"
+        -
+          asm_text: "vstrb.32 q5, [r2, #-0x40]"
+        -
+          asm_text: "vldrh.u16 q0, [r0]"
+        -
+          asm_text: "vldrh.u16 q1, [r0]"
+        -
+          asm_text: "vldrh.u16 q0, [r11]"
+        -
+          asm_text: "vldrh.u16 q3, [r11]"
+        -
+          asm_text: "vldrh.u16 q0, [r4, #0x38]"
+        -
+          asm_text: "vldrh.u16 q4, [r4, #0x38]"
+        -
+          asm_text: "vldrh.u16 q0, [r8, #0x38]"
+        -
+          asm_text: "vldrh.u16 q5, [r4, #0x38]!"
+        -
+          asm_text: "vldrh.u16 q5, [r4, #0x38]!"
+        -
+          asm_text: "vldrh.u16 q5, [r4], #-0x1a"
+        -
+          asm_text: "vldrh.u16 q5, [r10], #-0x1a"
+        -
+          asm_text: "vldrh.u16 q5, [sp, #-0x1a]"
+        -
+          asm_text: "vldrh.u16 q5, [sp, #-0x40]"
+        -
+          asm_text: "vldrh.u16 q5, [sp, #-0xfe]"
+        -
+          asm_text: "vldrh.u16 q5, [r10], #0xfe"
+        -
+          asm_text: "vstrh.16 q0, [r0]"
+        -
+          asm_text: "vstrh.16 q1, [r0]"
+        -
+          asm_text: "vstrh.16 q0, [r11]"
+        -
+          asm_text: "vstrh.16 q3, [r11]"
+        -
+          asm_text: "vstrh.16 q0, [r4, #0x38]"
+        -
+          asm_text: "vstrh.16 q4, [r4, #0x38]"
+        -
+          asm_text: "vstrh.16 q0, [r8, #0x38]"
+        -
+          asm_text: "vstrh.16 q5, [r4, #0x38]!"
+        -
+          asm_text: "vstrh.16 q5, [r4, #0x38]!"
+        -
+          asm_text: "vstrh.16 q5, [r4], #-0x1a"
+        -
+          asm_text: "vstrh.16 q5, [r10], #-0x1a"
+        -
+          asm_text: "vstrh.16 q5, [sp, #-0x1a]"
+        -
+          asm_text: "vstrh.16 q5, [sp, #-0x40]"
+        -
+          asm_text: "vstrh.16 q5, [sp, #-0xfe]"
+        -
+          asm_text: "vstrh.16 q5, [r10], #0xfe"
+        -
+          asm_text: "vldrh.u32 q0, [r0]"
+        -
+          asm_text: "vldrh.u32 q1, [r0]"
+        -
+          asm_text: "vldrh.u32 q0, [r7]"
+        -
+          asm_text: "vldrh.u32 q3, [r7]"
+        -
+          asm_text: "vldrh.u32 q0, [r4, #0x38]"
+        -
+          asm_text: "vldrh.u32 q4, [r4, #0x38]"
+        -
+          asm_text: "vldrh.u32 q0, [r2, #0x38]"
+        -
+          asm_text: "vldrh.u32 q5, [r4, #0x38]!"
+        -
+          asm_text: "vldrh.u32 q5, [r4, #0x38]!"
+        -
+          asm_text: "vldrh.u32 q5, [r4], #-0x1a"
+        -
+          asm_text: "vldrh.u32 q5, [r3], #-0x1a"
+        -
+          asm_text: "vldrh.u32 q5, [r6, #-0x1a]"
+        -
+          asm_text: "vldrh.u32 q5, [r6, #-0x40]"
+        -
+          asm_text: "vldrh.u32 q5, [r6, #-0xfe]"
+        -
+          asm_text: "vldrh.u32 q5, [r4, #0xfe]!"
+        -
+          asm_text: "vldrh.s32 q0, [r0]"
+        -
+          asm_text: "vldrh.s32 q1, [r0]"
+        -
+          asm_text: "vldrh.s32 q0, [r7]"
+        -
+          asm_text: "vldrh.s32 q3, [r7]"
+        -
+          asm_text: "vldrh.s32 q0, [r4, #0x38]"
+        -
+          asm_text: "vldrh.s32 q4, [r4, #0x38]"
+        -
+          asm_text: "vldrh.s32 q0, [r2, #0x38]"
+        -
+          asm_text: "vldrh.s32 q5, [r4, #0x38]!"
+        -
+          asm_text: "vldrh.s32 q5, [r4, #0x38]!"
+        -
+          asm_text: "vldrh.s32 q5, [r4], #-0x1a"
+        -
+          asm_text: "vldrh.s32 q5, [r3], #-0x1a"
+        -
+          asm_text: "vldrh.s32 q5, [r6, #-0x1a]"
+        -
+          asm_text: "vldrh.s32 q5, [r6, #-0x40]"
+        -
+          asm_text: "vldrh.s32 q5, [r6, #-0xfe]"
+        -
+          asm_text: "vldrh.s32 q5, [r4, #0xfe]!"
+        -
+          asm_text: "vstrh.32 q0, [r0]"
+        -
+          asm_text: "vstrh.32 q1, [r0]"
+        -
+          asm_text: "vstrh.32 q0, [r7]"
+        -
+          asm_text: "vstrh.32 q3, [r7]"
+        -
+          asm_text: "vstrh.32 q0, [r4, #0x38]"
+        -
+          asm_text: "vstrh.32 q4, [r4, #0x38]"
+        -
+          asm_text: "vstrh.32 q0, [r5, #0x38]"
+        -
+          asm_text: "vstrh.32 q5, [r4, #0x38]!"
+        -
+          asm_text: "vstrh.32 q5, [r4, #0x38]!"
+        -
+          asm_text: "vstrh.32 q5, [r4], #-0x1a"
+        -
+          asm_text: "vstrh.32 q5, [r3], #-0x1a"
+        -
+          asm_text: "vstrh.32 q5, [r2, #-0x1a]"
+        -
+          asm_text: "vstrh.32 q5, [r2, #-0x40]"
+        -
+          asm_text: "vstrh.32 q5, [r2, #-0xfe]"
+        -
+          asm_text: "vstrh.32 q5, [r4, #0xfe]!"
+        -
+          asm_text: "vldrw.u32 q0, [r0]"
+        -
+          asm_text: "vldrw.u32 q1, [r0]"
+        -
+          asm_text: "vldrw.u32 q0, [r11]"
+        -
+          asm_text: "vldrw.u32 q3, [r11]"
+        -
+          asm_text: "vldrw.u32 q0, [r4, #0x38]"
+        -
+          asm_text: "vldrw.u32 q4, [r4, #0x38]"
+        -
+          asm_text: "vldrw.u32 q0, [r8, #0x38]"
+        -
+          asm_text: "vldrw.u32 q5, [r4, #0x38]!"
+        -
+          asm_text: "vldrw.u32 q5, [r4, #0x38]!"
+        -
+          asm_text: "vldrw.u32 q5, [r4], #-0x1c"
+        -
+          asm_text: "vldrw.u32 q5, [r10], #-0x1c"
+        -
+          asm_text: "vldrw.u32 q5, [sp, #-0x1c]"
+        -
+          asm_text: "vldrw.u32 q5, [sp, #-0x40]"
+        -
+          asm_text: "vldrw.u32 q5, [sp, #-0x1fc]"
+        -
+          asm_text: "vldrw.u32 q5, [r4, #0x1fc]!"
+        -
+          asm_text: "vstrw.32 q0, [r0]"
+        -
+          asm_text: "vstrw.32 q1, [r0]"
+        -
+          asm_text: "vstrw.32 q0, [r11]"
+        -
+          asm_text: "vstrw.32 q3, [r11]"
+        -
+          asm_text: "vstrw.32 q0, [r4, #0x38]"
+        -
+          asm_text: "vstrw.32 q4, [r4, #0x38]"
+        -
+          asm_text: "vstrw.32 q0, [r8, #0x38]"
+        -
+          asm_text: "vstrw.32 q5, [r4, #0x38]!"
+        -
+          asm_text: "vstrw.32 q5, [r4, #0x38]!"
+        -
+          asm_text: "vstrw.32 q5, [r4], #-0x1c"
+        -
+          asm_text: "vstrw.32 q5, [r10], #-0x1c"
+        -
+          asm_text: "vstrw.32 q5, [sp, #-0x1c]"
+        -
+          asm_text: "vstrw.32 q5, [sp, #-0x40]"
+        -
+          asm_text: "vstrw.32 q5, [sp, #-0x1fc]"
+        -
+          asm_text: "vstrw.32 q5, [r4, #0x1fc]!"
+        -
+          asm_text: "vldrb.u8 q0, [r0, q1]"
+        -
+          asm_text: "vldrb.u8 q3, [r10, q1]"
+        -
+          asm_text: "vldrb.u16 q0, [r0, q1]"
+        -
+          asm_text: "vldrb.u16 q3, [r9, q1]"
+        -
+          asm_text: "vldrb.s16 q0, [r0, q1]"
+        -
+          asm_text: "vldrb.s16 q3, [sp, q1]"
+        -
+          asm_text: "vldrb.u32 q0, [r0, q1]"
+        -
+          asm_text: "vldrb.u32 q3, [r0, q1]"
+        -
+          asm_text: "vldrb.s32 q0, [r0, q1]"
+        -
+          asm_text: "vldrb.s32 q3, [r0, q1]"
+        -
+          asm_text: "vldrh.u16 q0, [r0, q1]"
+        -
+          asm_text: "vldrh.u16 q3, [r0, q1]"
+        -
+          asm_text: "vldrh.u32 q0, [r0, q1]"
+        -
+          asm_text: "vldrh.u32 q3, [r0, q1]"
+        -
+          asm_text: "vldrh.s32 q0, [r0, q1]"
+        -
+          asm_text: "vldrh.s32 q3, [r0, q1]"
+        -
+          asm_text: "vldrh.u16 q0, [r0, q1, uxtw #1]"
+        -
+          asm_text: "vldrw.u32 q0, [r0, q1]"
+        -
+          asm_text: "vldrw.u32 q3, [r0, q1]"
+        -
+          asm_text: "vldrw.u32 q0, [r0, q1, uxtw #2]"
+        -
+          asm_text: "vldrw.u32 q0, [sp, q1, uxtw #2]"
+        -
+          asm_text: "vldrd.u64 q0, [r0, q1]"
+        -
+          asm_text: "vldrd.u64 q3, [r0, q1]"
+        -
+          asm_text: "vldrd.u64 q0, [r0, q1, uxtw #3]"
+        -
+          asm_text: "vldrd.u64 q0, [sp, q1, uxtw #3]"
+        -
+          asm_text: "vstrb.8 q0, [r0, q1]"
+        -
+          asm_text: "vstrb.8 q3, [r10, q1]"
+        -
+          asm_text: "vstrb.8 q3, [r0, q3]"
+        -
+          asm_text: "vstrb.16 q0, [r0, q1]"
+        -
+          asm_text: "vstrb.16 q3, [sp, q1]"
+        -
+          asm_text: "vstrb.16 q3, [r0, q3]"
+        -
+          asm_text: "vstrb.32 q0, [r0, q1]"
+        -
+          asm_text: "vstrb.32 q3, [r0, q1]"
+        -
+          asm_text: "vstrb.32 q3, [r0, q3]"
+        -
+          asm_text: "vstrh.16 q0, [r0, q1]"
+        -
+          asm_text: "vstrh.16 q3, [r0, q1]"
+        -
+          asm_text: "vstrh.16 q3, [r0, q3]"
+        -
+          asm_text: "vstrh.32 q0, [r0, q1]"
+        -
+          asm_text: "vstrh.32 q3, [r0, q1]"
+        -
+          asm_text: "vstrh.32 q3, [r0, q3]"
+        -
+          asm_text: "vstrh.16 q0, [r0, q1, uxtw #1]"
+        -
+          asm_text: "vstrh.32 q3, [r8, q3, uxtw #1]"
+        -
+          asm_text: "vstrw.32 q0, [r0, q1]"
+        -
+          asm_text: "vstrw.32 q3, [r0, q1]"
+        -
+          asm_text: "vstrw.32 q3, [r0, q3]"
+        -
+          asm_text: "vstrw.32 q0, [r0, q1, uxtw #2]"
+        -
+          asm_text: "vstrw.32 q0, [sp, q1, uxtw #2]"
+        -
+          asm_text: "vstrd.64 q0, [r0, q1]"
+        -
+          asm_text: "vstrd.64 q3, [r0, q1]"
+        -
+          asm_text: "vstrd.64 q3, [r0, q3]"
+        -
+          asm_text: "vstrd.64 q0, [r0, q1, uxtw #3]"
+        -
+          asm_text: "vstrd.64 q0, [sp, q1, uxtw #3]"
+        -
+          asm_text: "vldrw.u32 q0, [q1]"
+        -
+          asm_text: "vldrw.u32 q7, [q1]"
+        -
+          asm_text: "vldrw.u32 q7, [q1]!"
+        -
+          asm_text: "vldrw.u32 q7, [q1, #4]"
+        -
+          asm_text: "vldrw.u32 q7, [q1, #-4]"
+        -
+          asm_text: "vldrw.u32 q7, [q1, #0x1fc]"
+        -
+          asm_text: "vldrw.u32 q7, [q1, #-0x1fc]"
+        -
+          asm_text: "vldrw.u32 q7, [q1, #0x108]"
+        -
+          asm_text: "vldrw.u32 q7, [q1, #4]!"
+        -
+          asm_text: "vstrw.32 q0, [q1]"
+        -
+          asm_text: "vstrw.32 q1, [q1]"
+        -
+          asm_text: "vstrw.32 q7, [q1]"
+        -
+          asm_text: "vstrw.32 q7, [q1]!"
+        -
+          asm_text: "vstrw.32 q7, [q7]"
+        -
+          asm_text: "vstrw.32 q7, [q1, #4]"
+        -
+          asm_text: "vstrw.32 q7, [q1, #-4]"
+        -
+          asm_text: "vstrw.32 q7, [q1, #0x1fc]"
+        -
+          asm_text: "vstrw.32 q7, [q1, #-0x1fc]"
+        -
+          asm_text: "vstrw.32 q7, [q1, #0x108]!"
+        -
+          asm_text: "vldrd.u64 q0, [q1]"
+        -
+          asm_text: "vldrd.u64 q7, [q1]"
+        -
+          asm_text: "vldrd.u64 q7, [q1]!"
+        -
+          asm_text: "vldrd.u64 q7, [q1, #8]"
+        -
+          asm_text: "vldrd.u64 q7, [q1, #-8]"
+        -
+          asm_text: "vldrd.u64 q7, [q1, #0x3f8]"
+        -
+          asm_text: "vldrd.u64 q7, [q1, #-0x3f8]"
+        -
+          asm_text: "vldrd.u64 q7, [q1, #0x108]"
+        -
+          asm_text: "vldrd.u64 q7, [q1, #0x270]"
+        -
+          asm_text: "vldrd.u64 q7, [q1, #0x108]"
+        -
+          asm_text: "vldrd.u64 q7, [q1, #-0x3f8]!"
+        -
+          asm_text: "vstrd.64 q0, [q1]"
+        -
+          asm_text: "vstrd.64 q1, [q1]"
+        -
+          asm_text: "vstrd.64 q7, [q1]"
+        -
+          asm_text: "vstrd.64 q7, [q1]!"
+        -
+          asm_text: "vstrd.64 q7, [q7]"
+        -
+          asm_text: "vstrd.64 q7, [q1, #8]"
+        -
+          asm_text: "vstrd.64 q7, [q1, #-8]!"
+        -
+          asm_text: "vstrd.64 q7, [q1, #0x3f8]"
+        -
+          asm_text: "vstrd.64 q7, [q1, #-0x3f8]"
+        -
+          asm_text: "vstrd.64 q7, [q1, #0x108]"
+        -
+          asm_text: "vstrd.64 q7, [q1, #0x270]"
+        -
+          asm_text: "vstrd.64 q7, [q1, #0x108]"
+        -
+          asm_text: "vldrb.u8 q0, [r0]"
+        -
+          asm_text: "vldrb.u8 q0, [r0]"
+        -
+          asm_text: "vldrb.u8 q0, [r8, #0x38]"
+        -
+          asm_text: "vldrb.u8 q0, [r8, #0x38]"
+        -
+          asm_text: "vldrb.u8 q5, [r4, #0x38]!"
+        -
+          asm_text: "vldrb.u8 q5, [r4, #0x38]!"
+        -
+          asm_text: "vstrb.8 q0, [r0]"
+        -
+          asm_text: "vstrb.8 q0, [r0]"
+        -
+          asm_text: "vstrb.8 q4, [r4, #0x38]"
+        -
+          asm_text: "vstrb.8 q4, [r4, #0x38]"
+        -
+          asm_text: "vstrb.8 q5, [r4, #0x38]!"
+        -
+          asm_text: "vstrb.8 q5, [r4, #0x38]!"
+        -
+          asm_text: "vldrh.u16 q0, [r0]"
+        -
+          asm_text: "vldrh.u16 q0, [r0]"
+        -
+          asm_text: "vldrh.u16 q0, [r0]"
+        -
+          asm_text: "vldrh.u16 q0, [r4, #0x38]"
+        -
+          asm_text: "vldrh.u16 q0, [r4, #0x38]"
+        -
+          asm_text: "vldrh.u16 q0, [r4, #0x38]"
+        -
+          asm_text: "vldrh.u16 q5, [r4, #0x38]!"
+        -
+          asm_text: "vldrh.u16 q5, [r4, #0x38]!"
+        -
+          asm_text: "vldrh.u16 q5, [r4, #0x38]!"
+        -
+          asm_text: "vstrh.16 q0, [r0]"
+        -
+          asm_text: "vstrh.16 q0, [r0]"
+        -
+          asm_text: "vstrh.16 q0, [r0]"
+        -
+          asm_text: "vstrh.16 q0, [r4, #0x38]"
+        -
+          asm_text: "vstrh.16 q0, [r4, #0x38]"
+        -
+          asm_text: "vstrh.16 q0, [r4, #0x38]"
+        -
+          asm_text: "vstrh.16 q5, [r4, #0x38]!"
+        -
+          asm_text: "vstrh.16 q5, [r4, #0x38]!"
+        -
+          asm_text: "vstrh.16 q5, [r4, #0x38]!"
+        -
+          asm_text: "vldrw.u32 q0, [r0]"
+        -
+          asm_text: "vldrw.u32 q0, [r0]"
+        -
+          asm_text: "vldrw.u32 q0, [r0]"
+        -
+          asm_text: "vldrw.u32 q0, [r4, #0x38]"
+        -
+          asm_text: "vldrw.u32 q0, [r4, #0x38]"
+        -
+          asm_text: "vldrw.u32 q0, [r4, #0x38]"
+        -
+          asm_text: "vldrw.u32 q5, [r4, #0x38]!"
+        -
+          asm_text: "vldrw.u32 q5, [r4, #0x38]!"
+        -
+          asm_text: "vldrw.u32 q5, [r4, #0x38]!"
+        -
+          asm_text: "vstrw.32 q0, [r0]"
+        -
+          asm_text: "vstrw.32 q0, [r0]"
+        -
+          asm_text: "vstrw.32 q0, [r0]"
+        -
+          asm_text: "vstrw.32 q0, [r4, #0x38]"
+        -
+          asm_text: "vstrw.32 q0, [r4, #0x38]"
+        -
+          asm_text: "vstrw.32 q0, [r4, #0x38]"
+        -
+          asm_text: "vstrw.32 q5, [r4, #0x38]!"
+        -
+          asm_text: "vstrw.32 q5, [r4, #0x38]!"
+        -
+          asm_text: "vstrw.32 q5, [r4, #0x38]!"
+        -
+          asm_text: "vldrb.u8 q0, [r0, q1]"
+        -
+          asm_text: "vldrb.u8 q0, [r0, q1]"
+        -
+          asm_text: "vldrh.u16 q3, [r0, q1]"
+        -
+          asm_text: "vldrh.u16 q3, [r0, q1]"
+        -
+          asm_text: "vldrh.u16 q3, [r0, q1]"
+        -
+          asm_text: "vldrh.u16 q0, [r0, q1, uxtw #1]"
+        -
+          asm_text: "vldrh.u16 q0, [r0, q1, uxtw #1]"
+        -
+          asm_text: "vldrh.u16 q0, [r0, q1, uxtw #1]"
+        -
+          asm_text: "vldrw.u32 q0, [r0, q1]"
+        -
+          asm_text: "vldrw.u32 q0, [r0, q1]"
+        -
+          asm_text: "vldrw.u32 q0, [r0, q1]"
+        -
+          asm_text: "vldrw.u32 q0, [r0, q1, uxtw #2]"
+        -
+          asm_text: "vldrw.u32 q0, [r0, q1, uxtw #2]"
+        -
+          asm_text: "vldrw.u32 q0, [r0, q1, uxtw #2]"
+        -
+          asm_text: "vldrd.u64 q0, [r0, q1]"
+        -
+          asm_text: "vldrd.u64 q0, [r0, q1]"
+        -
+          asm_text: "vldrd.u64 q0, [r0, q1]"
+        -
+          asm_text: "vldrd.u64 q0, [r0, q1, uxtw #3]"
+        -
+          asm_text: "vldrd.u64 q0, [r0, q1, uxtw #3]"
+        -
+          asm_text: "vldrd.u64 q0, [r0, q1, uxtw #3]"
+        -
+          asm_text: "vstrb.8 q0, [r0, q1]"
+        -
+          asm_text: "vstrb.8 q0, [r0, q1]"
+        -
+          asm_text: "vstrh.16 q3, [r0, q1]"
+        -
+          asm_text: "vstrh.16 q3, [r0, q1]"
+        -
+          asm_text: "vstrh.16 q3, [r0, q1]"
+        -
+          asm_text: "vstrh.16 q0, [r0, q1, uxtw #1]"
+        -
+          asm_text: "vstrh.16 q0, [r0, q1, uxtw #1]"
+        -
+          asm_text: "vstrh.16 q0, [r0, q1, uxtw #1]"
+        -
+          asm_text: "vstrw.32 q0, [r0, q1]"
+        -
+          asm_text: "vstrw.32 q0, [r0, q1]"
+        -
+          asm_text: "vstrw.32 q0, [r0, q1]"
+        -
+          asm_text: "vstrw.32 q0, [r0, q1, uxtw #2]"
+        -
+          asm_text: "vstrw.32 q0, [r0, q1, uxtw #2]"
+        -
+          asm_text: "vstrw.32 q0, [r0, q1, uxtw #2]"
+        -
+          asm_text: "vstrd.64 q3, [r0, q1]"
+        -
+          asm_text: "vstrd.64 q3, [r0, q1]"
+        -
+          asm_text: "vstrd.64 q3, [r0, q1]"
+        -
+          asm_text: "vstrd.64 q0, [r0, q1, uxtw #3]"
+        -
+          asm_text: "vstrd.64 q0, [r0, q1, uxtw #3]"
+        -
+          asm_text: "vstrd.64 q0, [r0, q1, uxtw #3]"
+        -
+          asm_text: "vldrw.u32 q0, [q1]"
+        -
+          asm_text: "vldrw.u32 q0, [q1]"
+        -
+          asm_text: "vldrw.u32 q0, [q1]"
+        -
+          asm_text: "vldrw.u32 q7, [q1]!"
+        -
+          asm_text: "vldrw.u32 q7, [q1]!"
+        -
+          asm_text: "vldrw.u32 q7, [q1]!"
+        -
+          asm_text: "vldrw.u32 q7, [q1, #4]"
+        -
+          asm_text: "vldrw.u32 q7, [q1, #4]"
+        -
+          asm_text: "vldrw.u32 q7, [q1, #4]"
+        -
+          asm_text: "vldrw.u32 q7, [q1, #4]!"
+        -
+          asm_text: "vldrw.u32 q7, [q1, #4]!"
+        -
+          asm_text: "vldrw.u32 q7, [q1, #4]!"
+        -
+          asm_text: "vstrw.32 q0, [q1]"
+        -
+          asm_text: "vstrw.32 q0, [q1]"
+        -
+          asm_text: "vstrw.32 q0, [q1]"
+        -
+          asm_text: "vstrw.32 q7, [q1]!"
+        -
+          asm_text: "vstrw.32 q7, [q1]!"
+        -
+          asm_text: "vstrw.32 q7, [q1]!"
+        -
+          asm_text: "vstrw.32 q7, [q1, #0x1fc]"
+        -
+          asm_text: "vstrw.32 q7, [q1, #0x1fc]"
+        -
+          asm_text: "vstrw.32 q7, [q1, #0x1fc]"
+        -
+          asm_text: "vstrw.32 q7, [q1, #0x108]!"
+        -
+          asm_text: "vstrw.32 q7, [q1, #0x108]!"
+        -
+          asm_text: "vstrw.32 q7, [q1, #0x108]!"
+        -
+          asm_text: "vldrd.u64 q0, [q1]"
+        -
+          asm_text: "vldrd.u64 q0, [q1]"
+        -
+          asm_text: "vldrd.u64 q0, [q1]"
+        -
+          asm_text: "vldrd.u64 q7, [q1]!"
+        -
+          asm_text: "vldrd.u64 q7, [q1]!"
+        -
+          asm_text: "vldrd.u64 q7, [q1]!"
+        -
+          asm_text: "vldrd.u64 q7, [q1, #8]"
+        -
+          asm_text: "vldrd.u64 q7, [q1, #8]"
+        -
+          asm_text: "vldrd.u64 q7, [q1, #8]"
+        -
+          asm_text: "vldrd.u64 q7, [q1, #-0x3f8]!"
+        -
+          asm_text: "vldrd.u64 q7, [q1, #-0x3f8]!"
+        -
+          asm_text: "vldrd.u64 q7, [q1, #-0x3f8]!"
+        -
+          asm_text: "vstrd.64 q0, [q1]"
+        -
+          asm_text: "vstrd.64 q0, [q1]"
+        -
+          asm_text: "vstrd.64 q0, [q1]"
+        -
+          asm_text: "vstrd.64 q7, [q1]!"
+        -
+          asm_text: "vstrd.64 q7, [q1]!"
+        -
+          asm_text: "vstrd.64 q7, [q1]!"
+        -
+          asm_text: "vstrd.64 q7, [q1, #0x3f8]"
+        -
+          asm_text: "vstrd.64 q7, [q1, #0x3f8]"
+        -
+          asm_text: "vstrd.64 q7, [q1, #0x3f8]"
+        -
+          asm_text: "vstrd.64 q7, [q1, #-8]!"
+        -
+          asm_text: "vstrd.64 q7, [q1, #-8]!"
+        -
+          asm_text: "vstrd.64 q7, [q1, #-8]!"
+        -
+          asm_text: "vpste"
+        -
+          asm_text: "vstrwt.32 q7, [q1, #0x108]!"
+        -
+          asm_text: "vldrde.u64 q7, [q1, #8]"
diff --git a/tests/MC/ARM/mve-minmax.s.yaml b/tests/MC/ARM/mve-minmax.s.yaml
new file mode 100644
index 000000000..53d8e241b
--- /dev/null
+++ b/tests/MC/ARM/mve-minmax.s.yaml
@@ -0,0 +1,42 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x02, 0xff, 0x58, 0x0f, 0x30, 0xff, 0x52, 0x6f, 0x00, 0xef, 0x5e, 0x66, 0x12, 0xef, 0x54, 0x06, 0x22, 0xef, 0x54, 0x06, 0x02, 0xff, 0x54, 0x06, 0x12, 0xff, 0x54, 0x06, 0x22, 0xff, 0x54, 0x06, 0x00, 0xef, 0x4e, 0x66, 0x12, 0xef, 0x44, 0x06, 0x22, 0xef, 0x44, 0x06, 0x02, 0xff, 0x44, 0x06, 0x12, 0xff, 0x44, 0x06, 0x22, 0xff, 0x44, 0x06, 0x71, 0xfe, 0x4d, 0x8f, 0x02, 0xef, 0x54, 0x06, 0x12, 0xef, 0x54, 0x06 ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_MCLASS", "CS_MODE_V8", "CS_MODE_THUMB" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmaxnm.f32 q0, q1, q4"
+        -
+          asm_text: "vminnm.f16 q3, q0, q1"
+        -
+          asm_text: "vmin.s8 q3, q0, q7"
+        -
+          asm_text: "vmin.s16 q0, q1, q2"
+        -
+          asm_text: "vmin.s32 q0, q1, q2"
+        -
+          asm_text: "vmin.u8 q0, q1, q2"
+        -
+          asm_text: "vmin.u16 q0, q1, q2"
+        -
+          asm_text: "vmin.u32 q0, q1, q2"
+        -
+          asm_text: "vmax.s8 q3, q0, q7"
+        -
+          asm_text: "vmax.s16 q0, q1, q2"
+        -
+          asm_text: "vmax.s32 q0, q1, q2"
+        -
+          asm_text: "vmax.u8 q0, q1, q2"
+        -
+          asm_text: "vmax.u16 q0, q1, q2"
+        -
+          asm_text: "vmax.u32 q0, q1, q2"
+        -
+          asm_text: "vpste"
+        -
+          asm_text: "vmint.s8 q0, q1, q2"
+        -
+          asm_text: "vmine.s16 q0, q1, q2"
diff --git a/tests/MC/ARM/mve-misc.s.yaml b/tests/MC/ARM/mve-misc.s.yaml
new file mode 100644
index 000000000..ed291285a
--- /dev/null
+++ b/tests/MC/ARM/mve-misc.s.yaml
@@ -0,0 +1,66 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x3b, 0xfe, 0x05, 0x0f, 0x31, 0xfe, 0x4d, 0x0f, 0x00, 0xf0, 0x43, 0xc3, 0x10, 0xf0, 0x43, 0xc3, 0x24, 0xf0, 0x49, 0xcd, 0x3e, 0xf0, 0xe9, 0xcd, 0x05, 0xf0, 0xb7, 0xc6, 0x11, 0xf0, 0x13, 0xc2, 0x27, 0xf0, 0xe3, 0xc7, 0x01, 0xf0, 0x0d, 0xc9, 0x0a, 0xf0, 0xbf, 0xc2, 0x0a, 0xf0, 0xc1, 0xc2, 0x0a, 0xf0, 0x9b, 0xcc, 0x0a, 0xf0, 0xfb, 0xcf, 0x0b, 0xf0, 0xd1, 0xca, 0x35, 0xf0, 0x01, 0xc0, 0x05, 0xf0, 0x01, 0xe0, 0x15, 0xf0, 0x01, 0xe0, 0x27, 0xf0, 0x01, 0xe0, 0x32, 0xf0, 0x01, 0xe0, 0x1f, 0xf0, 0x01, 0xc8, 0x1f, 0xf0, 0x05, 0xc0, 0x1f, 0xf0, 0xff, 0xcf, 0x0f, 0xf0, 0x01, 0xe0, 0x08, 0xbf, 0x0f, 0xf0, 0x01, 0xe0, 0x71, 0xfe, 0x4d, 0x8f, 0x33, 0xfe, 0x05, 0x0f, 0x33, 0xfe, 0x05, 0x0f ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_MCLASS", "CS_MODE_V8", "CS_MODE_THUMB" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpsel q0, q5, q2"
+        -
+          asm_text: "vpnot"
+        -
+          asm_text: "wlstp.8 lr, r0, #0x684"
+        -
+          asm_text: "wlstp.16 lr, r0, #0x684"
+        -
+          asm_text: "wlstp.32 lr, r4, #0xa92"
+        -
+          asm_text: "wlstp.64 lr, lr, #0xbd2"
+        -
+          asm_text: "wlstp.8 lr, r5, #0xd6c"
+        -
+          asm_text: "wlstp.16 lr, r1, #0x424"
+        -
+          asm_text: "wlstp.32 lr, r7, #0xfc4"
+        -
+          asm_text: "wlstp.8 lr, r1, #0x21a"
+        -
+          asm_text: "wlstp.8 lr, r10, #0x57c"
+        -
+          asm_text: "wlstp.8 lr, r10, #0x580"
+        -
+          asm_text: "wlstp.8 lr, r10, #0x936"
+        -
+          asm_text: "wlstp.8 lr, r10, #0xff6"
+        -
+          asm_text: "wlstp.8 lr, r11, #0x5a2"
+        -
+          asm_text: "wlstp.64 lr, r5, #0"
+        -
+          asm_text: "dlstp.8 lr, r5"
+        -
+          asm_text: "dlstp.16 lr, r5"
+        -
+          asm_text: "dlstp.32 lr, r7"
+        -
+          asm_text: "dlstp.64 lr, r2"
+        -
+          asm_text: "letp lr, #-2"
+        -
+          asm_text: "letp lr, #-8"
+        -
+          asm_text: "letp lr, #-0xffe"
+        -
+          asm_text: "lctp"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "lctpeq"
+        -
+          asm_text: "vpste"
+        -
+          asm_text: "vpselt q0, q1, q2"
+        -
+          asm_text: "vpsele q0, q1, q2"
diff --git a/tests/MC/ARM/mve-qdest-qsrc.s.yaml b/tests/MC/ARM/mve-qdest-qsrc.s.yaml
new file mode 100644
index 000000000..98ecfc2ef
--- /dev/null
+++ b/tests/MC/ARM/mve-qdest-qsrc.s.yaml
@@ -0,0 +1,276 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x3f, 0xee, 0x09, 0x2e, 0x3f, 0xfe, 0x03, 0x1e, 0xb2, 0xee, 0xc0, 0x0b, 0xf3, 0xee, 0xc2, 0x0b, 0x3f, 0xee, 0x09, 0x3e, 0x0c, 0xee, 0x0c, 0x3e, 0x12, 0xee, 0x08, 0x1e, 0x26, 0xee, 0x0e, 0x1e, 0x02, 0xee, 0x02, 0x0e, 0x14, 0xee, 0x04, 0x0e, 0x2a, 0xee, 0x0e, 0x2e, 0x0e, 0xee, 0x01, 0x1e, 0x10, 0xee, 0x03, 0x1e, 0x20, 0xee, 0x09, 0x3e, 0x22, 0xee, 0x01, 0x3e, 0x20, 0xee, 0x03, 0x3e, 0x0c, 0xee, 0x05, 0x0e, 0x1a, 0xee, 0x09, 0x2e, 0x24, 0xee, 0x05, 0x0e, 0x08, 0xfe, 0x0e, 0x3e, 0x14, 0xfe, 0x0a, 0x1e, 0x28, 0xfe, 0x0c, 0x7e, 0x06, 0xfe, 0x0c, 0x0e, 0x18, 0xfe, 0x02, 0x0e, 0x2a, 0xfe, 0x00, 0x4e, 0x06, 0xfe, 0x03, 0x1e, 0x12, 0xfe, 0x09, 0x1e, 0x2c, 0xfe, 0x07, 0x3e, 0x06, 0xfe, 0x01, 0x6e, 0x1e, 0xfe, 0x09, 0x0e, 0x2c, 0xfe, 0x0f, 0x0e, 0x20, 0xfe, 0x0f, 0x0e, 0x2c, 0xfe, 0x01, 0x0e, 0x32, 0xee, 0x05, 0x0e, 0x34, 0xee, 0x0a, 0xce, 0x30, 0xee, 0x0b, 0x2e, 0x30, 0xee, 0x0a, 0x3e, 0x30, 0xee, 0x0b, 0x3e, 0x30, 0xee, 0x03, 0x3e, 0x3e, 0xfe, 0x0a, 0x2e, 0x38, 0xfe, 0x05, 0x6e, 0x32, 0xfe, 0x06, 0xbe, 0x3e, 0xfe, 0x09, 0x1e, 0x0d, 0xee, 0x00, 0x4e, 0x19, 0xee, 0x06, 0x6e, 0x2b, 0xee, 0x0c, 0x6e, 0x0d, 0xee, 0x04, 0x1e, 0x11, 0xee, 0x04, 0x1e, 0x29, 0xee, 0x08, 0x5e, 0x37, 0xee, 0x0e, 0x4e, 0x33, 0xfe, 0x06, 0x0e, 0x33, 0xee, 0x0e, 0x3e, 0x3f, 0xfe, 0x0e, 0x1e, 0x09, 0xee, 0x0b, 0x0e, 0x1f, 0xee, 0x09, 0x0e, 0x2f, 0xee, 0x09, 0x0e, 0x0b, 0xfe, 0x05, 0x6e, 0x1f, 0xfe, 0x09, 0x4e, 0x27, 0xfe, 0x05, 0x2e, 0x03, 0xee, 0x05, 0x3e, 0x13, 0xee, 0x05, 0x3e, 0x23, 0xee, 0x01, 0x7e, 0x0d, 0xfe, 0x01, 0x3e, 0x17, 0xfe, 0x0d, 0x9e, 0x25, 0xfe, 0x05, 0x3e, 0x33, 0xee, 0x03, 0x0e, 0x33, 0xee, 0x01, 0x5e, 0x37, 0xee, 0x0b, 0x0e, 0x37, 0xee, 0x03, 0x1e, 0x33, 0xfe, 0x09, 0x0e, 0x33, 0xfe, 0x0f, 0x1e, 0x37, 0xfe, 0x09, 0x0e, 0x37, 0xfe, 0x05, 0x1e, 0x3f, 0xee, 0x09, 0x2e, 0x3f, 0xee, 0x09, 0x3e, 0x3f, 0xfe, 0x07, 0x0e, 0x3f, 0xfe, 0x03, 0x1e, 0x31, 0xee, 0x87, 0x0e, 0x31, 0xee, 0x83, 0x9e, 0x35, 0xee, 0x8f, 0x2e, 0x35, 0xee, 0x85, 0x1e, 0x31, 0xfe, 0x8b, 0x2e, 0x31, 0xfe, 0x81, 0x1e, 0x35, 0xfe, 0x81, 0x2e, 0x35, 0xfe, 0x87, 0x7e, 0x0e, 0xee, 0x0a, 0x6f, 0x10, 0xee, 0x0c, 0x0f, 0x10, 0xee, 0x0c, 0x0f, 0x12, 0xee, 0x00, 0x7f, 0x28, 0xee, 0x0a, 0x6f, 0x2e, 0xee, 0x04, 0xdf, 0x30, 0xee, 0x04, 0x2f, 0x32, 0xee, 0x02, 0x1f, 0x00, 0xfe, 0x04, 0x2f, 0x14, 0xfe, 0x06, 0x0f, 0x1a, 0xfe, 0x0a, 0x1f, 0x24, 0xfe, 0x0a, 0x8f, 0x2a, 0xfe, 0x00, 0xbf, 0x32, 0xfe, 0x02, 0x6f, 0x3c, 0xfe, 0x04, 0x5f, 0x38, 0xee, 0x0b, 0x0f, 0x3c, 0xee, 0x0b, 0x1f, 0x36, 0xfe, 0x0f, 0x0f, 0x3e, 0xfe, 0x0b, 0x1f, 0x32, 0xee, 0x01, 0x0f, 0x30, 0xee, 0x0b, 0x1f, 0x32, 0xee, 0x05, 0x1f, 0x30, 0xee, 0x60, 0x0f, 0x20, 0xfe, 0x02, 0x1f, 0x90, 0xfd, 0x42, 0x08, 0x20, 0xee, 0x02, 0x1f, 0x10, 0xee, 0x02, 0x1f, 0xb0, 0xff, 0xc0, 0x00, 0x71, 0xfe, 0x4d, 0x8f, 0x32, 0xfe, 0x05, 0x1f, 0x32, 0xee, 0x05, 0x0f, 0x71, 0xfe, 0x4d, 0x8f, 0x33, 0xee, 0x04, 0x1e, 0x33, 0xfe, 0x04, 0x0e, 0x71, 0xfe, 0x4d, 0x8f, 0x32, 0xee, 0x04, 0x1e, 0x32, 0xee, 0x04, 0x1e, 0x71, 0xfe, 0x4d, 0xcf, 0x3f, 0xee, 0x03, 0x0e, 0xb7, 0xff, 0x42, 0x01, 0x77, 0xee, 0xc1, 0x9f, 0x3f, 0xee, 0x01, 0x5e, 0x3f, 0xfe, 0x01, 0x3e, 0x77, 0xee, 0xc1, 0x9f, 0x3f, 0xee, 0x01, 0x4e, 0x3f, 0xfe, 0x01, 0x2e, 0x0c, 0xbf, 0xb3, 0xee, 0xe0, 0x0a, 0xb3, 0xee, 0xe0, 0x0a ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_MCLASS", "CS_MODE_V8", "CS_MODE_THUMB" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvtb.f16.f32 q1, q4"
+        -
+          asm_text: "vcvtt.f32.f16 q0, q1"
+        -
+          asm_text: "vcvtt.f64.f16 d0, s0"
+        -
+          asm_text: "vcvtt.f16.f64 s1, d2"
+        -
+          asm_text: "vcvtt.f16.f32 q1, q4"
+        -
+          asm_text: "vqdmladhx.s8 q1, q6, q6"
+        -
+          asm_text: "vqdmladhx.s16 q0, q1, q4"
+        -
+          asm_text: "vqdmladhx.s32 q0, q3, q7"
+        -
+          asm_text: "vqdmladh.s8 q0, q1, q1"
+        -
+          asm_text: "vqdmladh.s16 q0, q2, q2"
+        -
+          asm_text: "vqdmladh.s32 q1, q5, q7"
+        -
+          asm_text: "vqrdmladhx.s8 q0, q7, q0"
+        -
+          asm_text: "vqrdmladhx.s16 q0, q0, q1"
+        -
+          asm_text: "vqrdmladhx.s32 q1, q0, q4"
+        -
+          asm_text: "vqrdmladhx.s32 q1, q1, q0"
+        -
+          asm_text: "vqrdmladhx.s32 q1, q0, q1"
+        -
+          asm_text: "vqrdmladh.s8 q0, q6, q2"
+        -
+          asm_text: "vqrdmladh.s16 q1, q5, q4"
+        -
+          asm_text: "vqrdmladh.s32 q0, q2, q2"
+        -
+          asm_text: "vqdmlsdhx.s8 q1, q4, q7"
+        -
+          asm_text: "vqdmlsdhx.s16 q0, q2, q5"
+        -
+          asm_text: "vqdmlsdhx.s32 q3, q4, q6"
+        -
+          asm_text: "vqdmlsdh.s8 q0, q3, q6"
+        -
+          asm_text: "vqdmlsdh.s16 q0, q4, q1"
+        -
+          asm_text: "vqdmlsdh.s32 q2, q5, q0"
+        -
+          asm_text: "vqrdmlsdhx.s8 q0, q3, q1"
+        -
+          asm_text: "vqrdmlsdhx.s16 q0, q1, q4"
+        -
+          asm_text: "vqrdmlsdhx.s32 q1, q6, q3"
+        -
+          asm_text: "vqrdmlsdh.s8 q3, q3, q0"
+        -
+          asm_text: "vqrdmlsdh.s16 q0, q7, q4"
+        -
+          asm_text: "vqrdmlsdh.s32 q0, q6, q7"
+        -
+          asm_text: "vqrdmlsdh.s32 q0, q0, q7"
+        -
+          asm_text: "vqrdmlsdh.s32 q0, q6, q0"
+        -
+          asm_text: "vcmul.f16 q0, q1, q2, #0x5a"
+        -
+          asm_text: "vcmul.f16 q6, q2, q5, #0"
+        -
+          asm_text: "vcmul.f16 q1, q0, q5, #0x5a"
+        -
+          asm_text: "vcmul.f16 q1, q0, q5, #0xb4"
+        -
+          asm_text: "vcmul.f16 q1, q0, q5, #0x10e"
+        -
+          asm_text: "vcmul.f16 q1, q0, q1, #0x10e"
+        -
+          asm_text: "vcmul.f32 q1, q7, q5, #0"
+        -
+          asm_text: "vcmul.f32 q3, q4, q2, #0x5a"
+        -
+          asm_text: "vcmul.f32 q5, q1, q3, #0xb4"
+        -
+          asm_text: "vcmul.f32 q0, q7, q4, #0x10e"
+        -
+          asm_text: "vmullb.s8 q2, q6, q0"
+        -
+          asm_text: "vmullb.s16 q3, q4, q3"
+        -
+          asm_text: "vmullb.s32 q3, q5, q6"
+        -
+          asm_text: "vmullt.s8 q0, q6, q2"
+        -
+          asm_text: "vmullt.s16 q0, q0, q2"
+        -
+          asm_text: "vmullt.s32 q2, q4, q4"
+        -
+          asm_text: "vmullb.p8 q2, q3, q7"
+        -
+          asm_text: "vmullb.p16 q0, q1, q3"
+        -
+          asm_text: "vmullt.p8 q1, q1, q7"
+        -
+          asm_text: "vmullt.p16 q0, q7, q7"
+        -
+          asm_text: "vmulh.s8 q0, q4, q5"
+        -
+          asm_text: "vmulh.s16 q0, q7, q4"
+        -
+          asm_text: "vmulh.s32 q0, q7, q4"
+        -
+          asm_text: "vmulh.u8 q3, q5, q2"
+        -
+          asm_text: "vmulh.u16 q2, q7, q4"
+        -
+          asm_text: "vmulh.u32 q1, q3, q2"
+        -
+          asm_text: "vrmulh.s8 q1, q1, q2"
+        -
+          asm_text: "vrmulh.s16 q1, q1, q2"
+        -
+          asm_text: "vrmulh.s32 q3, q1, q0"
+        -
+          asm_text: "vrmulh.u8 q1, q6, q0"
+        -
+          asm_text: "vrmulh.u16 q4, q3, q6"
+        -
+          asm_text: "vrmulh.u32 q1, q2, q2"
+        -
+          asm_text: "vqmovnb.s16 q0, q1"
+        -
+          asm_text: "vqmovnt.s16 q2, q0"
+        -
+          asm_text: "vqmovnb.s32 q0, q5"
+        -
+          asm_text: "vqmovnt.s32 q0, q1"
+        -
+          asm_text: "vqmovnb.u16 q0, q4"
+        -
+          asm_text: "vqmovnt.u16 q0, q7"
+        -
+          asm_text: "vqmovnb.u32 q0, q4"
+        -
+          asm_text: "vqmovnt.u32 q0, q2"
+        -
+          asm_text: "vcvtb.f16.f32 q1, q4"
+        -
+          asm_text: "vcvtt.f16.f32 q1, q4"
+        -
+          asm_text: "vcvtb.f32.f16 q0, q3"
+        -
+          asm_text: "vcvtt.f32.f16 q0, q1"
+        -
+          asm_text: "vqmovunb.s16 q0, q3"
+        -
+          asm_text: "vqmovunt.s16 q4, q1"
+        -
+          asm_text: "vqmovunb.s32 q1, q7"
+        -
+          asm_text: "vqmovunt.s32 q0, q2"
+        -
+          asm_text: "vmovnb.i16 q1, q5"
+        -
+          asm_text: "vmovnt.i16 q0, q0"
+        -
+          asm_text: "vmovnb.i32 q1, q0"
+        -
+          asm_text: "vmovnt.i32 q3, q3"
+        -
+          asm_text: "vhcadd.s8 q3, q7, q5, #0x5a"
+        -
+          asm_text: "vhcadd.s16 q0, q0, q6, #0x5a"
+        -
+          asm_text: "vhcadd.s16 q0, q0, q6, #0x5a"
+        -
+          asm_text: "vhcadd.s16 q3, q1, q0, #0x10e"
+        -
+          asm_text: "vhcadd.s32 q3, q4, q5, #0x5a"
+        -
+          asm_text: "vhcadd.s32 q6, q7, q2, #0x10e"
+        -
+          asm_text: "vadc.i32 q1, q0, q2"
+        -
+          asm_text: "vadci.i32 q0, q1, q1"
+        -
+          asm_text: "vcadd.i8 q1, q0, q2, #0x5a"
+        -
+          asm_text: "vcadd.i16 q0, q2, q3, #0x5a"
+        -
+          asm_text: "vcadd.i16 q0, q5, q5, #0x10e"
+        -
+          asm_text: "vcadd.i32 q4, q2, q5, #0x5a"
+        -
+          asm_text: "vcadd.i32 q5, q5, q0, #0x10e"
+        -
+          asm_text: "vsbc.i32 q3, q1, q1"
+        -
+          asm_text: "vsbci.i32 q2, q6, q2"
+        -
+          asm_text: "vqdmullb.s16 q0, q4, q5"
+        -
+          asm_text: "vqdmullt.s16 q0, q6, q5"
+        -
+          asm_text: "vqdmullb.s32 q0, q3, q7"
+        -
+          asm_text: "vqdmullt.s32 q0, q7, q5"
+        -
+          asm_text: "vqdmullb.s16 q0, q1, q0"
+        -
+          asm_text: "vqdmullt.s16 q0, q0, q5"
+        -
+          asm_text: "vqdmullt.s16 q0, q1, q2"
+        -
+          asm_text: "vqdmullb.s16 q0, q0, r0"
+        -
+          asm_text: "vcadd.i32 q0, q0, q1, #0x10e"
+        -
+          asm_text: "vcadd.f32 q0, q0, q1, #0x10e"
+        -
+          asm_text: "vhcadd.s32 q0, q0, q1, #0x10e"
+        -
+          asm_text: "vhcadd.s16 q0, q0, q1, #0x10e"
+        -
+          asm_text: "vrev32.8 q0, q0"
+        -
+          asm_text: "vpste"
+        -
+          asm_text: "vqdmulltt.s32 q0, q1, q2"
+        -
+          asm_text: "vqdmullbe.s16 q0, q1, q2"
+        -
+          asm_text: "vpste"
+        -
+          asm_text: "vmulltt.p8 q0, q1, q2"
+        -
+          asm_text: "vmullbe.p16 q0, q1, q2"
+        -
+          asm_text: "vpste"
+        -
+          asm_text: "vcmult.f16 q0, q1, q2, #0xb4"
+        -
+          asm_text: "vcmule.f16 q0, q1, q2, #0xb4"
+        -
+          asm_text: "vpstet"
+        -
+          asm_text: "vcvtbt.f16.f32 q0, q1"
+        -
+          asm_text: "vcvtne.s16.f16 q0, q1"
+        -
+          asm_text: "vpte.f32 lt, q3, r1"
+        -
+          asm_text: "vcvttt.f16.f32 q2, q0"
+        -
+          asm_text: "vcvtte.f32.f16 q1, q0"
+        -
+          asm_text: "vpte.f32 lt, q3, r1"
+        -
+          asm_text: "vcvtbt.f16.f32 q2, q0"
+        -
+          asm_text: "vcvtbe.f32.f16 q1, q0"
+        -
+          asm_text: "ite eq"
+        -
+          asm_text: "vcvtteq.f16.f32 s0, s1"
+        -
+          asm_text: "vcvttne.f16.f32 s0, s1"
diff --git a/tests/MC/ARM/mve-qdest-rsrc.s.yaml b/tests/MC/ARM/mve-qdest-rsrc.s.yaml
new file mode 100644
index 000000000..8e23f31db
--- /dev/null
+++ b/tests/MC/ARM/mve-qdest-rsrc.s.yaml
@@ -0,0 +1,292 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x07, 0xee, 0x43, 0x1f, 0x1f, 0xee, 0x4e, 0x1f, 0x2b, 0xee, 0x4a, 0x3f, 0x09, 0xee, 0x47, 0x2f, 0x1d, 0xee, 0x4b, 0x0f, 0x23, 0xee, 0x46, 0x0f, 0x04, 0xee, 0x68, 0x5f, 0x18, 0xee, 0x60, 0x3f, 0x24, 0xee, 0x60, 0x1f, 0x02, 0xfe, 0x62, 0x1f, 0x14, 0xfe, 0x66, 0x1f, 0x24, 0xfe, 0x62, 0x1f, 0x0c, 0xee, 0x61, 0x0f, 0x18, 0xee, 0x62, 0x6f, 0x2a, 0xee, 0x6b, 0x0f, 0x02, 0xfe, 0x68, 0x0f, 0x1a, 0xfe, 0x69, 0x0f, 0x20, 0xfe, 0x67, 0x0f, 0x32, 0xee, 0x66, 0x0f, 0x36, 0xfe, 0x0f, 0x0f, 0x32, 0xee, 0x60, 0x1f, 0x38, 0xfe, 0x65, 0x1f, 0x36, 0xfe, 0x47, 0x1f, 0x32, 0xee, 0x4a, 0x3f, 0x32, 0xfe, 0x4e, 0x0f, 0x38, 0xee, 0x44, 0x2f, 0x06, 0xee, 0x4e, 0x1f, 0x10, 0xee, 0x46, 0x1f, 0x24, 0xee, 0x47, 0x3f, 0x0c, 0xfe, 0x45, 0x3f, 0x18, 0xfe, 0x4a, 0x1f, 0x28, 0xfe, 0x4c, 0x1f, 0x04, 0xee, 0x41, 0x0f, 0x14, 0xee, 0x41, 0x0f, 0x20, 0xee, 0x4a, 0x0f, 0x0a, 0xfe, 0x4e, 0x0f, 0x14, 0xfe, 0x42, 0x2f, 0x24, 0xfe, 0x4b, 0x0f, 0x33, 0xee, 0xe0, 0x1e, 0x37, 0xee, 0xe3, 0x1e, 0x3b, 0xee, 0xee, 0x1e, 0x33, 0xfe, 0xe0, 0x1e, 0x37, 0xfe, 0xe2, 0x1e, 0x3b, 0xfe, 0xe3, 0x1e, 0x31, 0xee, 0xe0, 0x1e, 0x35, 0xee, 0xe1, 0x3e, 0x39, 0xee, 0xe3, 0x1e, 0x31, 0xfe, 0xe1, 0x1e, 0x35, 0xfe, 0xeb, 0x1e, 0x39, 0xfe, 0xee, 0x1e, 0x33, 0xee, 0x66, 0x1e, 0x37, 0xee, 0x6e, 0x1e, 0x3b, 0xee, 0x64, 0x1e, 0x33, 0xfe, 0x60, 0x1e, 0x37, 0xfe, 0x6a, 0x1e, 0x3b, 0xfe, 0x61, 0x1e, 0x31, 0xee, 0x6e, 0x1e, 0x35, 0xee, 0x6e, 0x1e, 0x39, 0xee, 0x61, 0x1e, 0x31, 0xfe, 0x6a, 0x1e, 0x35, 0xfe, 0x6a, 0x3e, 0x39, 0xfe, 0x6c, 0x1e, 0x09, 0xfe, 0x68, 0x1e, 0x13, 0xfe, 0x61, 0x1e, 0x2d, 0xfe, 0x60, 0x1e, 0x01, 0xee, 0x6c, 0x1e, 0x19, 0xee, 0x67, 0x1e, 0x23, 0xee, 0x6b, 0x1e, 0x31, 0xfe, 0x6a, 0x0e, 0x33, 0xee, 0x67, 0x0e, 0x03, 0xee, 0x66, 0x0e, 0x15, 0xee, 0x62, 0x0e, 0x27, 0xee, 0x68, 0x2e, 0x05, 0xfe, 0x66, 0x0e, 0x11, 0xfe, 0x62, 0x0e, 0x21, 0xfe, 0x62, 0x0e, 0x31, 0xfe, 0x4c, 0x1e, 0x37, 0xee, 0x4e, 0x1e, 0x01, 0xee, 0x46, 0x1e, 0x15, 0xee, 0x49, 0x1e, 0x2f, 0xee, 0x46, 0x1e, 0x01, 0xee, 0x46, 0x1e, 0x15, 0xee, 0x49, 0x1e, 0x2f, 0xee, 0x46, 0x1e, 0x0b, 0xee, 0x4e, 0x1e, 0x17, 0xee, 0x4c, 0x1e, 0x23, 0xee, 0x4b, 0x3e, 0x33, 0xfe, 0x46, 0x2e, 0x39, 0xee, 0x46, 0xfe, 0x07, 0xee, 0x48, 0x0e, 0x17, 0xee, 0x4a, 0x2e, 0x27, 0xee, 0x41, 0x2e, 0x07, 0xee, 0x48, 0x0e, 0x17, 0xee, 0x4a, 0x2e, 0x27, 0xee, 0x41, 0x2e, 0x0f, 0xee, 0x4a, 0x0e, 0x11, 0xee, 0x47, 0x0e, 0x2d, 0xee, 0x4a, 0x2e, 0x00, 0xee, 0x65, 0x1e, 0x1a, 0xee, 0x6e, 0x1e, 0x24, 0xee, 0x63, 0x1e, 0x06, 0xee, 0x63, 0x0e, 0x16, 0xee, 0x69, 0xae, 0x22, 0xee, 0x6b, 0x0e, 0x0a, 0xee, 0x4a, 0x1e, 0x16, 0xee, 0x42, 0x1e, 0x20, 0xee, 0x44, 0x1e, 0x0a, 0xee, 0x4b, 0x0e, 0x14, 0xee, 0x4a, 0x0e, 0x28, 0xee, 0x4b, 0x0e, 0x0f, 0xee, 0x60, 0x0f, 0x1b, 0xee, 0xe1, 0x2f, 0x2b, 0xee, 0xe4, 0xcf, 0x0d, 0xee, 0xeb, 0x1f, 0x1d, 0xee, 0x61, 0x1f, 0x21, 0xee, 0xe7, 0x1f, 0x0f, 0xee, 0x6f, 0x0f, 0x1f, 0xee, 0xee, 0x0f, 0x2d, 0xee, 0x6e, 0x0f, 0x05, 0xee, 0xee, 0x1f, 0x1b, 0xee, 0xee, 0x1f, 0x21, 0xee, 0xef, 0x5f, 0x0e, 0xf0, 0x01, 0xe8, 0x10, 0xf0, 0x01, 0xe8, 0x2a, 0xf0, 0x01, 0xe8, 0x31, 0xf0, 0x01, 0xe8, 0x71, 0xfe, 0x4d, 0x8f, 0x02, 0xef, 0x54, 0x09, 0x12, 0xef, 0x54, 0x09, 0x71, 0xfe, 0x4d, 0x8f, 0x12, 0xef, 0x54, 0x09, 0x14, 0xef, 0x56, 0x29, 0x3b, 0xfe, 0xe0, 0x1e, 0x71, 0xfe, 0x4d, 0x8f, 0x37, 0xfe, 0xe0, 0x1e, 0x14, 0xef, 0x52, 0x05, 0x71, 0xfe, 0x4d, 0x8f, 0x14, 0xff, 0x42, 0x05, 0x3b, 0xee, 0x60, 0x1e, 0x71, 0xfe, 0x4d, 0x8f, 0x31, 0xee, 0x60, 0x1e, 0x39, 0xfe, 0x60, 0x1e ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_MCLASS", "CS_MODE_V8", "CS_MODE_THUMB" ]
+    expected:
+      insns:
+        -
+          asm_text: "vsub.i8 q0, q3, r3"
+        -
+          asm_text: "vsub.i16 q0, q7, lr"
+        -
+          asm_text: "vsub.i32 q1, q5, r10"
+        -
+          asm_text: "vadd.i8 q1, q4, r7"
+        -
+          asm_text: "vadd.i16 q0, q6, r11"
+        -
+          asm_text: "vadd.i32 q0, q1, r6"
+        -
+          asm_text: "vqsub.s8 q2, q2, r8"
+        -
+          asm_text: "vqsub.s16 q1, q4, r0"
+        -
+          asm_text: "vqsub.s32 q0, q2, r0"
+        -
+          asm_text: "vqsub.u8 q0, q1, r2"
+        -
+          asm_text: "vqsub.u16 q0, q2, r6"
+        -
+          asm_text: "vqsub.u32 q0, q2, r2"
+        -
+          asm_text: "vqadd.s8 q0, q6, r1"
+        -
+          asm_text: "vqadd.s16 q3, q4, r2"
+        -
+          asm_text: "vqadd.s32 q0, q5, r11"
+        -
+          asm_text: "vqadd.u8 q0, q1, r8"
+        -
+          asm_text: "vqadd.u16 q0, q5, r9"
+        -
+          asm_text: "vqadd.u32 q0, q0, r7"
+        -
+          asm_text: "vqdmullb.s16 q0, q1, r6"
+        -
+          asm_text: "vqdmullb.s32 q0, q3, q7"
+        -
+          asm_text: "vqdmullt.s16 q0, q1, r0"
+        -
+          asm_text: "vqdmullt.s32 q0, q4, r5"
+        -
+          asm_text: "vsub.f16 q0, q3, r7"
+        -
+          asm_text: "vsub.f32 q1, q1, r10"
+        -
+          asm_text: "vadd.f16 q0, q1, lr"
+        -
+          asm_text: "vadd.f32 q1, q4, r4"
+        -
+          asm_text: "vhsub.s8 q0, q3, lr"
+        -
+          asm_text: "vhsub.s16 q0, q0, r6"
+        -
+          asm_text: "vhsub.s32 q1, q2, r7"
+        -
+          asm_text: "vhsub.u8 q1, q6, r5"
+        -
+          asm_text: "vhsub.u16 q0, q4, r10"
+        -
+          asm_text: "vhsub.u32 q0, q4, r12"
+        -
+          asm_text: "vhadd.s8 q0, q2, r1"
+        -
+          asm_text: "vhadd.s16 q0, q2, r1"
+        -
+          asm_text: "vhadd.s32 q0, q0, r10"
+        -
+          asm_text: "vhadd.u8 q0, q5, lr"
+        -
+          asm_text: "vhadd.u16 q1, q2, r2"
+        -
+          asm_text: "vhadd.u32 q0, q2, r11"
+        -
+          asm_text: "vqrshl.s8 q0, r0"
+        -
+          asm_text: "vqrshl.s16 q0, r3"
+        -
+          asm_text: "vqrshl.s32 q0, lr"
+        -
+          asm_text: "vqrshl.u8 q0, r0"
+        -
+          asm_text: "vqrshl.u16 q0, r2"
+        -
+          asm_text: "vqrshl.u32 q0, r3"
+        -
+          asm_text: "vqshl.s8 q0, r0"
+        -
+          asm_text: "vqshl.s16 q1, r1"
+        -
+          asm_text: "vqshl.s32 q0, r3"
+        -
+          asm_text: "vqshl.u8 q0, r1"
+        -
+          asm_text: "vqshl.u16 q0, r11"
+        -
+          asm_text: "vqshl.u32 q0, lr"
+        -
+          asm_text: "vrshl.s8 q0, r6"
+        -
+          asm_text: "vrshl.s16 q0, lr"
+        -
+          asm_text: "vrshl.s32 q0, r4"
+        -
+          asm_text: "vrshl.u8 q0, r0"
+        -
+          asm_text: "vrshl.u16 q0, r10"
+        -
+          asm_text: "vrshl.u32 q0, r1"
+        -
+          asm_text: "vshl.s8 q0, lr"
+        -
+          asm_text: "vshl.s16 q0, lr"
+        -
+          asm_text: "vshl.s32 q0, r1"
+        -
+          asm_text: "vshl.u8 q0, r10"
+        -
+          asm_text: "vshl.u16 q1, r10"
+        -
+          asm_text: "vshl.u32 q0, r12"
+        -
+          asm_text: "vbrsr.8 q0, q4, r8"
+        -
+          asm_text: "vbrsr.16 q0, q1, r1"
+        -
+          asm_text: "vbrsr.32 q0, q6, r0"
+        -
+          asm_text: "vmul.i8 q0, q0, r12"
+        -
+          asm_text: "vmul.i16 q0, q4, r7"
+        -
+          asm_text: "vmul.i32 q0, q1, r11"
+        -
+          asm_text: "vmul.f16 q0, q0, r10"
+        -
+          asm_text: "vmul.f32 q0, q1, r7"
+        -
+          asm_text: "vqdmulh.s8 q0, q1, r6"
+        -
+          asm_text: "vqdmulh.s16 q0, q2, r2"
+        -
+          asm_text: "vqdmulh.s32 q1, q3, r8"
+        -
+          asm_text: "vqrdmulh.s8 q0, q2, r6"
+        -
+          asm_text: "vqrdmulh.s16 q0, q0, r2"
+        -
+          asm_text: "vqrdmulh.s32 q0, q0, r2"
+        -
+          asm_text: "vfmas.f16 q0, q0, r12"
+        -
+          asm_text: "vfmas.f32 q0, q3, lr"
+        -
+          asm_text: "vmlas.i8 q0, q0, r6"
+        -
+          asm_text: "vmlas.i16 q0, q2, r9"
+        -
+          asm_text: "vmlas.i32 q0, q7, r6"
+        -
+          asm_text: "vmlas.i8 q0, q0, r6"
+        -
+          asm_text: "vmlas.i16 q0, q2, r9"
+        -
+          asm_text: "vmlas.i32 q0, q7, r6"
+        -
+          asm_text: "vmlas.i8 q0, q5, lr"
+        -
+          asm_text: "vmlas.i16 q0, q3, r12"
+        -
+          asm_text: "vmlas.i32 q1, q1, r11"
+        -
+          asm_text: "vfma.f16 q1, q1, r6"
+        -
+          asm_text: "vfmas.f32 q7, q4, r6"
+        -
+          asm_text: "vmla.i8 q0, q3, r8"
+        -
+          asm_text: "vmla.i16 q1, q3, r10"
+        -
+          asm_text: "vmla.i32 q1, q3, r1"
+        -
+          asm_text: "vmla.i8 q0, q3, r8"
+        -
+          asm_text: "vmla.i16 q1, q3, r10"
+        -
+          asm_text: "vmla.i32 q1, q3, r1"
+        -
+          asm_text: "vmla.i8 q0, q7, r10"
+        -
+          asm_text: "vmla.i16 q0, q0, r7"
+        -
+          asm_text: "vmla.i32 q1, q6, r10"
+        -
+          asm_text: "vqdmlash.s8 q0, q0, r5"
+        -
+          asm_text: "vqdmlash.s16 q0, q5, lr"
+        -
+          asm_text: "vqdmlash.s32 q0, q2, r3"
+        -
+          asm_text: "vqdmlah.s8 q0, q3, r3"
+        -
+          asm_text: "vqdmlah.s16 q5, q3, r9"
+        -
+          asm_text: "vqdmlah.s32 q0, q1, r11"
+        -
+          asm_text: "vqrdmlash.s8 q0, q5, r10"
+        -
+          asm_text: "vqrdmlash.s16 q0, q3, r2"
+        -
+          asm_text: "vqrdmlash.s32 q0, q0, r4"
+        -
+          asm_text: "vqrdmlah.s8 q0, q5, r11"
+        -
+          asm_text: "vqrdmlah.s16 q0, q2, r10"
+        -
+          asm_text: "vqrdmlah.s32 q0, q4, r11"
+        -
+          asm_text: "viwdup.u8 q0, lr, r1, #1"
+        -
+          asm_text: "viwdup.u16 q1, r10, r1, #8"
+        -
+          asm_text: "viwdup.u32 q6, r10, r5, #4"
+        -
+          asm_text: "vdwdup.u8 q0, r12, r11, #8"
+        -
+          asm_text: "vdwdup.u16 q0, r12, r1, #2"
+        -
+          asm_text: "vdwdup.u32 q0, r0, r7, #8"
+        -
+          asm_text: "vidup.u8 q0, lr, #2"
+        -
+          asm_text: "vidup.u16 q0, lr, #4"
+        -
+          asm_text: "vidup.u32 q0, r12, #1"
+        -
+          asm_text: "vddup.u8 q0, r4, #4"
+        -
+          asm_text: "vddup.u16 q0, r10, #4"
+        -
+          asm_text: "vddup.u32 q2, r0, #8"
+        -
+          asm_text: "vctp.8 lr"
+        -
+          asm_text: "vctp.16 r0"
+        -
+          asm_text: "vctp.32 r10"
+        -
+          asm_text: "vctp.64 r1"
+        -
+          asm_text: "vpste"
+        -
+          asm_text: "vmult.i8 q0, q1, q2"
+        -
+          asm_text: "vmule.i16 q0, q1, q2"
+        -
+          asm_text: "vpste"
+        -
+          asm_text: "vmult.i16 q0, q1, q2"
+        -
+          asm_text: "vmule.i16 q1, q2, q3"
+        -
+          asm_text: "vqrshl.u32 q0, r0"
+        -
+          asm_text: "vpste"
+        -
+          asm_text: "vqrshlt.u16 q0, r0"
+        -
+          asm_text: "vqrshle.s16 q0, q1, q2"
+        -
+          asm_text: "vpste"
+        -
+          asm_text: "vrshlt.u16 q0, q1, q2"
+        -
+          asm_text: "vrshle.s32 q0, r0"
+        -
+          asm_text: "vpste"
+        -
+          asm_text: "vshlt.s8 q0, r0"
+        -
+          asm_text: "vshle.u32 q0, r0"
diff --git a/tests/MC/ARM/mve-reductions-fp.s.yaml b/tests/MC/ARM/mve-reductions-fp.s.yaml
new file mode 100644
index 000000000..192574b7c
--- /dev/null
+++ b/tests/MC/ARM/mve-reductions-fp.s.yaml
@@ -0,0 +1,24 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xee, 0xfe, 0x86, 0xef, 0xee, 0xee, 0x82, 0xef, 0xec, 0xfe, 0x80, 0xef, 0xec, 0xee, 0x86, 0xef, 0xee, 0xfe, 0x02, 0xef, 0xee, 0xee, 0x02, 0xaf, 0xec, 0xfe, 0x0c, 0x0f, 0xec, 0xee, 0x0e, 0xef ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_MCLASS", "CS_MODE_V8", "CS_MODE_THUMB" ]
+    expected:
+      insns:
+        -
+          asm_text: "vminnmv.f16 lr, q3"
+        -
+          asm_text: "vminnmv.f32 lr, q1"
+        -
+          asm_text: "vminnmav.f16 lr, q0"
+        -
+          asm_text: "vminnmav.f32 lr, q3"
+        -
+          asm_text: "vmaxnmv.f16 lr, q1"
+        -
+          asm_text: "vmaxnmv.f32 r10, q1"
+        -
+          asm_text: "vmaxnmav.f16 r0, q6"
+        -
+          asm_text: "vmaxnmav.f32 lr, q7"
diff --git a/tests/MC/ARM/mve-reductions.s.yaml b/tests/MC/ARM/mve-reductions.s.yaml
new file mode 100644
index 000000000..989b9fd4b
--- /dev/null
+++ b/tests/MC/ARM/mve-reductions.s.yaml
@@ -0,0 +1,118 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x82, 0xee, 0x07, 0x0f, 0x92, 0xee, 0x07, 0x0f, 0xa2, 0xee, 0x07, 0x0f, 0x82, 0xfe, 0x07, 0x0f, 0x92, 0xfe, 0x07, 0x0f, 0xa2, 0xfe, 0x07, 0x0f, 0xf5, 0xee, 0x00, 0xef, 0xf5, 0xee, 0x0c, 0x0f, 0xf5, 0xee, 0x20, 0xef, 0xc9, 0xee, 0x04, 0x0f, 0x89, 0xfe, 0x02, 0x0f, 0xe2, 0xee, 0x80, 0xef, 0xe6, 0xee, 0x80, 0xef, 0xea, 0xee, 0x84, 0xef, 0xe2, 0xfe, 0x80, 0x0f, 0xea, 0xfe, 0x86, 0xaf, 0xe4, 0xee, 0x80, 0x0f, 0xe0, 0xee, 0x82, 0x0f, 0xe8, 0xee, 0x82, 0xef, 0xe2, 0xee, 0x08, 0xef, 0xe6, 0xee, 0x00, 0xef, 0xea, 0xee, 0x02, 0x1f, 0xe2, 0xfe, 0x08, 0x0f, 0xe6, 0xfe, 0x02, 0x0f, 0xea, 0xfe, 0x00, 0x1f, 0xe0, 0xee, 0x0c, 0xef, 0xe4, 0xee, 0x0c, 0x0f, 0xe8, 0xee, 0x0e, 0xaf, 0xf0, 0xee, 0x0e, 0xee, 0xf1, 0xee, 0x08, 0xee, 0xf0, 0xfe, 0x0e, 0xee, 0xf1, 0xfe, 0x00, 0xee, 0xf0, 0xee, 0x28, 0xee, 0xf0, 0xee, 0x0e, 0x1e, 0xf0, 0xee, 0x2e, 0xfe, 0xf6, 0xee, 0x00, 0xef, 0xf2, 0xfe, 0x0e, 0xef, 0x8c, 0xee, 0x04, 0xef, 0x8a, 0xfe, 0x04, 0xef, 0x8a, 0xfe, 0x04, 0xef, 0x86, 0xee, 0x20, 0xff, 0xdc, 0xfe, 0x0b, 0xee, 0xf0, 0xee, 0x07, 0xee, 0x8c, 0xee, 0x04, 0xef, 0x8a, 0xfe, 0x04, 0xef, 0x86, 0xee, 0x2c, 0xef, 0x8e, 0xfe, 0x22, 0xef, 0xf0, 0xee, 0x07, 0xee, 0xf5, 0xee, 0x0d, 0xee, 0xf2, 0xee, 0x29, 0xfe, 0xf0, 0xee, 0x0e, 0xee, 0x88, 0xee, 0x02, 0xee, 0xd9, 0xee, 0x02, 0xee, 0x8f, 0xee, 0x0c, 0x0e, 0xda, 0xfe, 0x08, 0xee ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_MCLASS", "CS_MODE_V8", "CS_MODE_THUMB" ]
+    expected:
+      insns:
+        -
+          asm_text: "vabav.s8 r0, q1, q3"
+        -
+          asm_text: "vabav.s16 r0, q1, q3"
+        -
+          asm_text: "vabav.s32 r0, q1, q3"
+        -
+          asm_text: "vabav.u8 r0, q1, q3"
+        -
+          asm_text: "vabav.u16 r0, q1, q3"
+        -
+          asm_text: "vabav.u32 r0, q1, q3"
+        -
+          asm_text: "vaddv.s16 lr, q0"
+        -
+          asm_text: "vaddv.s16 r0, q6"
+        -
+          asm_text: "vaddva.s16 lr, q0"
+        -
+          asm_text: "vaddlv.s32 r0, r9, q2"
+        -
+          asm_text: "vaddlv.u32 r0, r1, q1"
+        -
+          asm_text: "vminv.s8 lr, q0"
+        -
+          asm_text: "vminv.s16 lr, q0"
+        -
+          asm_text: "vminv.s32 lr, q2"
+        -
+          asm_text: "vminv.u8 r0, q0"
+        -
+          asm_text: "vminv.u32 r10, q3"
+        -
+          asm_text: "vminav.s16 r0, q0"
+        -
+          asm_text: "vminav.s8 r0, q1"
+        -
+          asm_text: "vminav.s32 lr, q1"
+        -
+          asm_text: "vmaxv.s8 lr, q4"
+        -
+          asm_text: "vmaxv.s16 lr, q0"
+        -
+          asm_text: "vmaxv.s32 r1, q1"
+        -
+          asm_text: "vmaxv.u8 r0, q4"
+        -
+          asm_text: "vmaxv.u16 r0, q1"
+        -
+          asm_text: "vmaxv.u32 r1, q0"
+        -
+          asm_text: "vmaxav.s8 lr, q6"
+        -
+          asm_text: "vmaxav.s16 r0, q6"
+        -
+          asm_text: "vmaxav.s32 r10, q7"
+        -
+          asm_text: "vmlav.s16 lr, q0, q7"
+        -
+          asm_text: "vmlav.s32 lr, q0, q4"
+        -
+          asm_text: "vmlav.u16 lr, q0, q7"
+        -
+          asm_text: "vmlav.u32 lr, q0, q0"
+        -
+          asm_text: "vmlava.s16 lr, q0, q4"
+        -
+          asm_text: "vmladavx.s16 r0, q0, q7"
+        -
+          asm_text: "vmladavax.s16 lr, q0, q7"
+        -
+          asm_text: "vmlav.s8 lr, q3, q0"
+        -
+          asm_text: "vmlav.u8 lr, q1, q7"
+        -
+          asm_text: "vrmlalvh.s32 lr, r1, q6, q2"
+        -
+          asm_text: "vrmlalvh.u32 lr, r1, q5, q2"
+        -
+          asm_text: "vrmlalvh.u32 lr, r1, q5, q2"
+        -
+          asm_text: "vrmlaldavhax.s32 lr, r1, q3, q0"
+        -
+          asm_text: "vrmlsldavh.s32 lr, r11, q6, q5"
+        -
+          asm_text: "vmlsdav.s16 lr, q0, q3"
+        -
+          asm_text: "vrmlalvh.s32 lr, r1, q6, q2"
+        -
+          asm_text: "vrmlalvh.u32 lr, r1, q5, q2"
+        -
+          asm_text: "vrmlalvha.s32 lr, r1, q3, q6"
+        -
+          asm_text: "vrmlalvha.u32 lr, r1, q7, q1"
+        -
+          asm_text: "vmlsdav.s16 lr, q0, q3"
+        -
+          asm_text: "vmlsdav.s32 lr, q2, q6"
+        -
+          asm_text: "vmlsdavax.s16 lr, q1, q4"
+        -
+          asm_text: "vmlav.s16 lr, q0, q7"
+        -
+          asm_text: "vmlalv.s16 lr, r1, q4, q1"
+        -
+          asm_text: "vmlalv.s32 lr, r11, q4, q1"
+        -
+          asm_text: "vmlalv.s32 r0, r1, q7, q6"
+        -
+          asm_text: "vmlalv.u16 lr, r11, q5, q4"
diff --git a/tests/MC/ARM/mve-scalar-shift.s.yaml b/tests/MC/ARM/mve-scalar-shift.s.yaml
new file mode 100644
index 000000000..44ad6d761
--- /dev/null
+++ b/tests/MC/ARM/mve-scalar-shift.s.yaml
@@ -0,0 +1,68 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x50, 0xea, 0xef, 0x51, 0x5e, 0xea, 0xef, 0x61, 0x50, 0xea, 0x2d, 0x41, 0x52, 0xea, 0x22, 0x9e, 0x57, 0xea, 0x47, 0x9e, 0x5c, 0xea, 0x3c, 0xae, 0x5a, 0xea, 0x3a, 0xbe, 0x59, 0xea, 0x7b, 0x89, 0x5f, 0xea, 0x1f, 0x9e, 0x5f, 0xea, 0x3f, 0xae, 0x5a, 0xea, 0xd7, 0x9e, 0x55, 0xea, 0x2f, 0xae, 0x52, 0xea, 0x42, 0xae, 0x51, 0xea, 0x7b, 0xbe, 0x5e, 0xea, 0xcf, 0x21, 0x5e, 0xea, 0x0d, 0x41, 0x5e, 0xea, 0x1f, 0x31, 0x5e, 0xea, 0x2d, 0xcf, 0x5b, 0xea, 0x2d, 0xcf, 0x5f, 0xea, 0x2d, 0x83, 0x5e, 0xea, 0x7f, 0x4f, 0x5f, 0xea, 0x3f, 0x7b, 0x5e, 0xea, 0xef, 0x2f, 0x5f, 0xea, 0xef, 0x5b, 0x5e, 0xea, 0x0d, 0x1f, 0x5f, 0xea, 0x8d, 0x41, 0x50, 0xea, 0x4f, 0x0f, 0x5f, 0xea, 0xcf, 0x17, 0x50, 0xea, 0x9f, 0x2f, 0x51, 0xea, 0x5f, 0x79 ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_MCLASS", "CS_MODE_V8", "CS_MODE_THUMB" ]
+    expected:
+      insns:
+        -
+          asm_text: "asrl r0, r1, #0x17"
+        -
+          asm_text: "asrl lr, r1, #0x1b"
+        -
+          asm_text: "asrl r0, r1, r4"
+        -
+          asm_text: "cinc lr, r2, lo"
+        -
+          asm_text: "cinc lr, r7, pl"
+        -
+          asm_text: "cinv lr, r12, hs"
+        -
+          asm_text: "cneg lr, r10, hs"
+        -
+          asm_text: "csel r9, r9, r11, vc"
+        -
+          asm_text: "cset lr, eq"
+        -
+          asm_text: "csetm lr, hs"
+        -
+          asm_text: "csinc lr, r10, r7, le"
+        -
+          asm_text: "csinv lr, r5, zr, hs"
+        -
+          asm_text: "cinv lr, r2, pl"
+        -
+          asm_text: "csneg lr, r1, r11, vc"
+        -
+          asm_text: "lsll lr, r1, #0xb"
+        -
+          asm_text: "lsll lr, r1, r4"
+        -
+          asm_text: "lsrl lr, r1, #0xc"
+        -
+          asm_text: "sqrshr lr, r12"
+        -
+          asm_text: "sqrshr r11, r12"
+        -
+          asm_text: "sqrshrl lr, r3, #0x40, r8"
+        -
+          asm_text: "sqshl lr, #0x11"
+        -
+          asm_text: "sqshll lr, r11, #0x1c"
+        -
+          asm_text: "srshr lr, #0xb"
+        -
+          asm_text: "srshrl lr, r11, #0x17"
+        -
+          asm_text: "uqrshl lr, r1"
+        -
+          asm_text: "uqrshll lr, r1, #0x30, r4"
+        -
+          asm_text: "uqshl r0, #1"
+        -
+          asm_text: "uqshll lr, r7, #7"
+        -
+          asm_text: "urshr r0, #0xa"
+        -
+          asm_text: "urshrl r0, r9, #0x1d"
diff --git a/tests/MC/ARM/mve-shifts.s.yaml b/tests/MC/ARM/mve-shifts.s.yaml
new file mode 100644
index 000000000..edb26b670
--- /dev/null
+++ b/tests/MC/ARM/mve-shifts.s.yaml
@@ -0,0 +1,218 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xa8, 0xee, 0xce, 0x0f, 0xa8, 0xee, 0x4c, 0x0f, 0xa8, 0xee, 0x48, 0x1f, 0x41, 0xfe, 0x00, 0x0f, 0xa8, 0xee, 0x48, 0x1f, 0xa8, 0xfe, 0x40, 0x0f, 0xa8, 0xfe, 0x44, 0x1f, 0xb0, 0xfe, 0x40, 0x2f, 0xb0, 0xfe, 0x44, 0x1f, 0x31, 0xee, 0x05, 0x0e, 0x31, 0xee, 0x0b, 0x3e, 0xaf, 0xee, 0x40, 0x0f, 0x31, 0xfe, 0x03, 0x2e, 0x31, 0xfe, 0x01, 0x1e, 0xab, 0xfe, 0x40, 0x0f, 0x35, 0xfe, 0x0b, 0x0e, 0x35, 0xfe, 0x07, 0x1e, 0x35, 0xee, 0x01, 0x1e, 0xbe, 0xee, 0x40, 0x1f, 0xbb, 0xee, 0x40, 0x1f, 0xb4, 0xfe, 0x44, 0x0f, 0x8f, 0xfe, 0xc7, 0x0f, 0x8b, 0xfe, 0xc5, 0x1f, 0x98, 0xfe, 0xc9, 0x0f, 0x99, 0xfe, 0xc5, 0x1f, 0x8f, 0xee, 0xc5, 0x2f, 0x8f, 0xee, 0xc3, 0x1f, 0x94, 0xee, 0xc1, 0x0f, 0x9c, 0xee, 0xc5, 0x1f, 0x88, 0xfe, 0xc4, 0x0f, 0x8a, 0xfe, 0xc0, 0x1f, 0x98, 0xfe, 0xc2, 0x1f, 0x93, 0xfe, 0xce, 0x0f, 0x8b, 0xee, 0xce, 0x0f, 0x89, 0xee, 0xc2, 0x1f, 0x9c, 0xee, 0xcc, 0x0f, 0x96, 0xee, 0xc4, 0x1f, 0x88, 0xee, 0x4f, 0x0f, 0x8c, 0xfe, 0x47, 0x3f, 0x99, 0xfe, 0x43, 0x0f, 0x95, 0xee, 0x43, 0x1f, 0x8b, 0xee, 0x4c, 0x0f, 0x8c, 0xee, 0x42, 0x1f, 0x89, 0xfe, 0x46, 0x0f, 0x88, 0xfe, 0x44, 0x1f, 0x9d, 0xee, 0x48, 0x3f, 0x92, 0xfe, 0x44, 0x0f, 0x0c, 0xef, 0x4c, 0xc4, 0x14, 0xef, 0x48, 0x04, 0x2a, 0xef, 0x42, 0x24, 0x04, 0xff, 0x4e, 0x24, 0x10, 0xff, 0x48, 0x04, 0x28, 0xff, 0x44, 0x44, 0x0c, 0xef, 0x52, 0x04, 0x1e, 0xef, 0x56, 0x84, 0x2a, 0xef, 0x5a, 0x04, 0x0c, 0xff, 0x50, 0x04, 0x18, 0xff, 0x5a, 0x04, 0x28, 0xff, 0x50, 0x24, 0x02, 0xef, 0x5c, 0x25, 0x1c, 0xef, 0x58, 0x45, 0x2a, 0xef, 0x50, 0x05, 0x02, 0xff, 0x54, 0x05, 0x10, 0xff, 0x5c, 0x25, 0x20, 0xff, 0x50, 0x05, 0x08, 0xef, 0x4c, 0x05, 0x1e, 0xef, 0x48, 0x25, 0x28, 0xef, 0x48, 0x25, 0x0a, 0xff, 0x46, 0x05, 0x1a, 0xff, 0x4c, 0xa5, 0x26, 0xff, 0x4e, 0x25, 0x8d, 0xff, 0x54, 0x04, 0x9b, 0xff, 0x54, 0x04, 0xb1, 0xff, 0x52, 0x04, 0x8b, 0xff, 0x56, 0x05, 0x9c, 0xff, 0x52, 0x05, 0xa8, 0xff, 0x52, 0x05, 0x8e, 0xef, 0x58, 0x07, 0x8e, 0xff, 0x5c, 0x07, 0x95, 0xef, 0x54, 0x27, 0x93, 0xff, 0x5a, 0x07, 0xbd, 0xef, 0x56, 0x27, 0xb3, 0xff, 0x54, 0x07, 0x88, 0xff, 0x52, 0x06, 0x9c, 0xff, 0x52, 0x46, 0xba, 0xff, 0x58, 0x06, 0x89, 0xef, 0x56, 0x22, 0x8e, 0xff, 0x56, 0x22, 0x96, 0xef, 0x52, 0x02, 0x94, 0xff, 0x5a, 0x02, 0xa9, 0xef, 0x5a, 0x02, 0xa2, 0xff, 0x52, 0x02, 0x8c, 0xef, 0x5e, 0x00, 0x8b, 0xff, 0x54, 0x00, 0x90, 0xef, 0x56, 0x00, 0x98, 0xff, 0x5c, 0xe0, 0xa8, 0xef, 0x5c, 0x00, 0xa2, 0xff, 0x5a, 0x40, 0x8e, 0xef, 0x5c, 0x05, 0x9c, 0xef, 0x50, 0x25, 0xba, 0xef, 0x54, 0x45, 0xa9, 0xee, 0x42, 0x1f, 0x71, 0xfe, 0x4d, 0x8f, 0xb4, 0xee, 0x42, 0x1f, 0xb8, 0xfe, 0x42, 0x0f ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_MCLASS", "CS_MODE_THUMB" ]
+    expected:
+      insns:
+        -
+          asm_text: "vshlc q0, lr, #8"
+        -
+          asm_text: "vmovlb.s8 q0, q6"
+        -
+          asm_text: "vmovlt.s8 q0, q4"
+        -
+          asm_text: "vpt.i8 eq, q0, q0"
+        -
+          asm_text: "vmovltt.s8 q0, q4"
+        -
+          asm_text: "vmovlb.u8 q0, q0"
+        -
+          asm_text: "vmovlt.u8 q0, q2"
+        -
+          asm_text: "vmovlb.u16 q1, q0"
+        -
+          asm_text: "vmovlt.u16 q0, q2"
+        -
+          asm_text: "vshllb.s8 q0, q2, #8"
+        -
+          asm_text: "vshllt.s8 q1, q5, #8"
+        -
+          asm_text: "vshllb.s8 q0, q0, #7"
+        -
+          asm_text: "vshllb.u8 q1, q1, #8"
+        -
+          asm_text: "vshllt.u8 q0, q0, #8"
+        -
+          asm_text: "vshllb.u8 q0, q0, #3"
+        -
+          asm_text: "vshllb.u16 q0, q5, #0x10"
+        -
+          asm_text: "vshllt.u16 q0, q3, #0x10"
+        -
+          asm_text: "vshllt.s16 q0, q0, #0x10"
+        -
+          asm_text: "vshllt.s16 q0, q0, #0xe"
+        -
+          asm_text: "vshllt.s16 q0, q0, #0xb"
+        -
+          asm_text: "vshllb.u16 q0, q2, #4"
+        -
+          asm_text: "vrshrnb.i16 q0, q3, #1"
+        -
+          asm_text: "vrshrnt.i16 q0, q2, #5"
+        -
+          asm_text: "vrshrnb.i32 q0, q4, #8"
+        -
+          asm_text: "vrshrnt.i32 q0, q2, #7"
+        -
+          asm_text: "vshrnb.i16 q1, q2, #1"
+        -
+          asm_text: "vshrnt.i16 q0, q1, #1"
+        -
+          asm_text: "vshrnb.i32 q0, q0, #0xc"
+        -
+          asm_text: "vshrnt.i32 q0, q2, #4"
+        -
+          asm_text: "vqrshrunb.s16 q0, q2, #8"
+        -
+          asm_text: "vqrshrunt.s16 q0, q0, #6"
+        -
+          asm_text: "vqrshrunt.s32 q0, q1, #8"
+        -
+          asm_text: "vqrshrunb.s32 q0, q7, #0xd"
+        -
+          asm_text: "vqshrunb.s16 q0, q7, #5"
+        -
+          asm_text: "vqshrunt.s16 q0, q1, #7"
+        -
+          asm_text: "vqshrunb.s32 q0, q6, #4"
+        -
+          asm_text: "vqshrunt.s32 q0, q2, #0xa"
+        -
+          asm_text: "vqrshrnb.s16 q0, q7, #8"
+        -
+          asm_text: "vqrshrnt.u16 q1, q3, #4"
+        -
+          asm_text: "vqrshrnb.u32 q0, q1, #7"
+        -
+          asm_text: "vqrshrnt.s32 q0, q1, #0xb"
+        -
+          asm_text: "vqshrnb.s16 q0, q6, #5"
+        -
+          asm_text: "vqshrnt.s16 q0, q1, #4"
+        -
+          asm_text: "vqshrnb.u16 q0, q3, #7"
+        -
+          asm_text: "vqshrnt.u16 q0, q2, #8"
+        -
+          asm_text: "vqshrnt.s32 q1, q4, #3"
+        -
+          asm_text: "vqshrnb.u32 q0, q2, #0xe"
+        -
+          asm_text: "vshl.s8 q6, q6, q6"
+        -
+          asm_text: "vshl.s16 q0, q4, q2"
+        -
+          asm_text: "vshl.s32 q1, q1, q5"
+        -
+          asm_text: "vshl.u8 q1, q7, q2"
+        -
+          asm_text: "vshl.u16 q0, q4, q0"
+        -
+          asm_text: "vshl.u32 q2, q2, q4"
+        -
+          asm_text: "vqshl.s8 q0, q1, q6"
+        -
+          asm_text: "vqshl.s16 q4, q3, q7"
+        -
+          asm_text: "vqshl.s32 q0, q5, q5"
+        -
+          asm_text: "vqshl.u8 q0, q0, q6"
+        -
+          asm_text: "vqshl.u16 q0, q5, q4"
+        -
+          asm_text: "vqshl.u32 q1, q0, q4"
+        -
+          asm_text: "vqrshl.s8 q1, q6, q1"
+        -
+          asm_text: "vqrshl.s16 q2, q4, q6"
+        -
+          asm_text: "vqrshl.s32 q0, q0, q5"
+        -
+          asm_text: "vqrshl.u8 q0, q2, q1"
+        -
+          asm_text: "vqrshl.u16 q1, q6, q0"
+        -
+          asm_text: "vqrshl.u32 q0, q0, q0"
+        -
+          asm_text: "vrshl.s8 q0, q6, q4"
+        -
+          asm_text: "vrshl.s16 q1, q4, q7"
+        -
+          asm_text: "vrshl.s32 q1, q4, q4"
+        -
+          asm_text: "vrshl.u8 q0, q3, q5"
+        -
+          asm_text: "vrshl.u16 q5, q6, q5"
+        -
+          asm_text: "vrshl.u32 q1, q7, q3"
+        -
+          asm_text: "vsri.8 q0, q2, #3"
+        -
+          asm_text: "vsri.16 q0, q2, #5"
+        -
+          asm_text: "vsri.32 q0, q1, #0xf"
+        -
+          asm_text: "vsli.8 q0, q3, #3"
+        -
+          asm_text: "vsli.16 q0, q1, #0xc"
+        -
+          asm_text: "vsli.32 q0, q1, #8"
+        -
+          asm_text: "vqshl.s8 q0, q4, #6"
+        -
+          asm_text: "vqshl.u8 q0, q6, #6"
+        -
+          asm_text: "vqshl.s16 q1, q2, #5"
+        -
+          asm_text: "vqshl.u16 q0, q5, #3"
+        -
+          asm_text: "vqshl.s32 q1, q3, #0x1d"
+        -
+          asm_text: "vqshl.u32 q0, q2, #0x13"
+        -
+          asm_text: "vqshlu.s8 q0, q1, #0"
+        -
+          asm_text: "vqshlu.s16 q2, q1, #0xc"
+        -
+          asm_text: "vqshlu.s32 q0, q4, #0x1a"
+        -
+          asm_text: "vrshr.s8 q1, q3, #7"
+        -
+          asm_text: "vrshr.u8 q1, q3, #2"
+        -
+          asm_text: "vrshr.s16 q0, q1, #0xa"
+        -
+          asm_text: "vrshr.u16 q0, q5, #0xc"
+        -
+          asm_text: "vrshr.s32 q0, q5, #0x17"
+        -
+          asm_text: "vrshr.u32 q0, q1, #0x1e"
+        -
+          asm_text: "vshr.s8 q0, q7, #4"
+        -
+          asm_text: "vshr.u8 q0, q2, #5"
+        -
+          asm_text: "vshr.s16 q0, q3, #0x10"
+        -
+          asm_text: "vshr.u16 q7, q6, #8"
+        -
+          asm_text: "vshr.s32 q0, q6, #0x18"
+        -
+          asm_text: "vshr.u32 q2, q5, #0x1e"
+        -
+          asm_text: "vshl.i8 q0, q6, #6"
+        -
+          asm_text: "vshl.i16 q1, q0, #0xc"
+        -
+          asm_text: "vshl.i32 q2, q2, #0x1a"
+        -
+          asm_text: "vshllt.s8 q0, q1, #1"
+        -
+          asm_text: "vpste"
+        -
+          asm_text: "vshlltt.s16 q0, q1, #4"
+        -
+          asm_text: "vshllbe.u16 q0, q1, #8"
diff --git a/tests/MC/ARM/mve-vcmp.s.yaml b/tests/MC/ARM/mve-vcmp.s.yaml
new file mode 100644
index 000000000..5b3fdd8eb
--- /dev/null
+++ b/tests/MC/ARM/mve-vcmp.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x31, 0xfe, 0x08, 0x0f, 0x35, 0xfe, 0x8e, 0x0f, 0x31, 0xfe, 0x00, 0x1f, 0x31, 0xfe, 0x82, 0x1f, 0x33, 0xfe, 0x09, 0x1f, 0x35, 0xfe, 0x8d, 0x1f, 0x35, 0xee, 0x0a, 0x0f, 0x37, 0xee, 0x88, 0x0f, 0x31, 0xee, 0x0e, 0x1f, 0x3b, 0xee, 0x84, 0x1f, 0x35, 0xee, 0x0f, 0x1f, 0x35, 0xee, 0x89, 0x1f, 0x09, 0xfe, 0x0c, 0x0f, 0x05, 0xfe, 0x84, 0x0f, 0x09, 0xfe, 0x0c, 0x0f, 0x05, 0xfe, 0x84, 0x0f, 0x09, 0xfe, 0x0c, 0x0f, 0x05, 0xfe, 0x84, 0x0f, 0x01, 0xfe, 0x00, 0x1f, 0x05, 0xfe, 0x8e, 0x1f, 0x09, 0xfe, 0x07, 0x1f, 0x0f, 0xfe, 0x87, 0x1f, 0x03, 0xfe, 0x89, 0x0f, 0x03, 0xfe, 0x09, 0x0f, 0x19, 0xfe, 0x0e, 0x0f, 0x15, 0xfe, 0x82, 0x0f, 0x13, 0xfe, 0x0e, 0x1f, 0x11, 0xfe, 0x82, 0x1f, 0x13, 0xfe, 0x0f, 0x1f, 0x15, 0xfe, 0x83, 0x1f, 0x13, 0xfe, 0x89, 0x0f, 0x13, 0xfe, 0x09, 0x0f, 0x25, 0xfe, 0x0e, 0x0f, 0x25, 0xfe, 0x88, 0x0f, 0x2b, 0xfe, 0x0a, 0x1f, 0x25, 0xfe, 0x84, 0x1f, 0x21, 0xfe, 0x03, 0x1f, 0x2b, 0xfe, 0x89, 0x1f, 0x23, 0xfe, 0x89, 0x0f, 0x23, 0xfe, 0x09, 0x0f, 0x39, 0xfe, 0x6f, 0x1f, 0x39, 0xfe, 0x4c, 0x0f, 0x37, 0xee, 0xc0, 0x0f, 0x03, 0xfe, 0x40, 0x0f, 0x03, 0xfe, 0xe0, 0x1f, 0x03, 0xfe, 0x60, 0x0f, 0x1b, 0xfe, 0x4a, 0x0f, 0x23, 0xfe, 0x44, 0x0f, 0x71, 0xfe, 0x4d, 0x8f, 0x01, 0xfe, 0x40, 0x0f, 0x11, 0xfe, 0xc0, 0x0f, 0xb4, 0xee, 0x60, 0x09, 0xb4, 0xee, 0xe0, 0x09, 0x04, 0xbf, 0xb4, 0xee, 0x60, 0x0a, 0xb4, 0xee, 0xe0, 0x0a ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_MCLASS", "CS_MODE_V8", "CS_MODE_THUMB" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmp.f16 eq, q0, q4"
+        -
+          asm_text: "vcmp.f16 ne, q2, q7"
+        -
+          asm_text: "vcmp.f16 ge, q0, q0"
+        -
+          asm_text: "vcmp.f16 lt, q0, q1"
+        -
+          asm_text: "vcmp.f16 gt, q1, q4"
+        -
+          asm_text: "vcmp.f16 le, q2, q6"
+        -
+          asm_text: "vcmp.f32 eq, q2, q5"
+        -
+          asm_text: "vcmp.f32 ne, q3, q4"
+        -
+          asm_text: "vcmp.f32 ge, q0, q7"
+        -
+          asm_text: "vcmp.f32 lt, q5, q2"
+        -
+          asm_text: "vcmp.f32 gt, q2, q7"
+        -
+          asm_text: "vcmp.f32 le, q2, q4"
+        -
+          asm_text: "vcmp.i8 eq, q4, q6"
+        -
+          asm_text: "vcmp.i8 ne, q2, q2"
+        -
+          asm_text: "vcmp.i8 eq, q4, q6"
+        -
+          asm_text: "vcmp.i8 ne, q2, q2"
+        -
+          asm_text: "vcmp.i8 eq, q4, q6"
+        -
+          asm_text: "vcmp.i8 ne, q2, q2"
+        -
+          asm_text: "vcmp.s8 ge, q0, q0"
+        -
+          asm_text: "vcmp.s8 lt, q2, q7"
+        -
+          asm_text: "vcmp.s8 gt, q4, q3"
+        -
+          asm_text: "vcmp.s8 le, q7, q3"
+        -
+          asm_text: "vcmp.u8 hi, q1, q4"
+        -
+          asm_text: "vcmp.u8 cs, q1, q4"
+        -
+          asm_text: "vcmp.i16 eq, q4, q7"
+        -
+          asm_text: "vcmp.i16 ne, q2, q1"
+        -
+          asm_text: "vcmp.s16 ge, q1, q7"
+        -
+          asm_text: "vcmp.s16 lt, q0, q1"
+        -
+          asm_text: "vcmp.s16 gt, q1, q7"
+        -
+          asm_text: "vcmp.s16 le, q2, q1"
+        -
+          asm_text: "vcmp.u16 hi, q1, q4"
+        -
+          asm_text: "vcmp.u16 cs, q1, q4"
+        -
+          asm_text: "vcmp.i32 eq, q2, q7"
+        -
+          asm_text: "vcmp.i32 ne, q2, q4"
+        -
+          asm_text: "vcmp.s32 ge, q5, q5"
+        -
+          asm_text: "vcmp.s32 lt, q2, q2"
+        -
+          asm_text: "vcmp.s32 gt, q0, q1"
+        -
+          asm_text: "vcmp.s32 le, q5, q4"
+        -
+          asm_text: "vcmp.u32 hi, q1, q4"
+        -
+          asm_text: "vcmp.u32 cs, q1, q4"
+        -
+          asm_text: "vcmp.f16 gt, q4, zr"
+        -
+          asm_text: "vcmp.f16 eq, q4, r12"
+        -
+          asm_text: "vcmp.f32 ne, q3, r0"
+        -
+          asm_text: "vcmp.i8 eq, q1, r0"
+        -
+          asm_text: "vcmp.s8 le, q1, r0"
+        -
+          asm_text: "vcmp.u8 cs, q1, r0"
+        -
+          asm_text: "vcmp.i16 eq, q5, r10"
+        -
+          asm_text: "vcmp.i32 eq, q1, r4"
+        -
+          asm_text: "vpste"
+        -
+          asm_text: "vcmpt.i8 eq, q0, r0"
+        -
+          asm_text: "vcmpe.i16 ne, q0, r0"
+        -
+          asm_text: "vcmp.f16 s0, s1"
+        -
+          asm_text: "vcmpe.f16 s0, s1"
+        -
+          asm_text: "itt eq"
+        -
+          asm_text: "vcmpeq.f32 s0, s1"
+        -
+          asm_text: "vcmpeeq.f32 s0, s1"
diff --git a/tests/MC/ARM/mve-vmov-pair.s.yaml b/tests/MC/ARM/mve-vmov-pair.s.yaml
new file mode 100644
index 000000000..957e55d57
--- /dev/null
+++ b/tests/MC/ARM/mve-vmov-pair.s.yaml
@@ -0,0 +1,12 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x07, 0xec, 0x0e, 0x8f, 0x11, 0xec, 0x14, 0x6f ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_MCLASS", "CS_MODE_V8", "CS_MODE_THUMB" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmov lr, r7, q4[2], q4[0]"
+        -
+          asm_text: "vmov q3[3], q3[1], r4, r1"
diff --git a/tests/MC/ARM/mve-vpt.s.yaml b/tests/MC/ARM/mve-vpt.s.yaml
new file mode 100644
index 000000000..c49bc1987
--- /dev/null
+++ b/tests/MC/ARM/mve-vpt.s.yaml
@@ -0,0 +1,16 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x41, 0xfe, 0x02, 0x2f, 0x21, 0xfe, 0x03, 0x3f, 0x71, 0xfe, 0x82, 0xef, 0x1c, 0xff, 0x54, 0x2f ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_MCLASS", "CS_MODE_V8", "CS_MODE_THUMB" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpteee.i8 eq, q0, q1"
+        -
+          asm_text: "vptttt.s32 gt, q0, q1"
+        -
+          asm_text: "vptete.f16 ne, q0, q1"
+        -
+          asm_text: "vmaxnmt.f16 q1, q6, q2"
diff --git a/tests/MC/ARM/negative-immediates.s.yaml b/tests/MC/ARM/negative-immediates.s.yaml
new file mode 100644
index 000000000..c530b98cb
--- /dev/null
+++ b/tests/MC/ARM/negative-immediates.s.yaml
@@ -0,0 +1,26 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x61, 0xf1, 0x01, 0x10, 0x61, 0xf1, 0x01, 0x20, 0xa0, 0xf1, 0xfe, 0x10, 0xa1, 0xf2, 0xff, 0x00, 0xa1, 0xf1, 0xff, 0x00, 0x21, 0xf0, 0x01, 0x20, 0x01, 0xf0, 0x01, 0x20, 0x61, 0xf0, 0x01, 0x20, 0x41, 0xf0, 0x01, 0x20 ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ]
+    expected:
+      insns:
+        -
+          asm_text: "sbc r0, r1, #0x10001"
+        -
+          asm_text: "sbc r0, r1, #0x1000100"
+        -
+          asm_text: "sub.w r0, r0, #0xfe00fe"
+        -
+          asm_text: "subw r0, r1, #0xff"
+        -
+          asm_text: "sub.w r0, r1, #0xff"
+        -
+          asm_text: "bic r0, r1, #0x1000100"
+        -
+          asm_text: "and r0, r1, #0x1000100"
+        -
+          asm_text: "orn r0, r1, #0x1000100"
+        -
+          asm_text: "orr r0, r1, #0x1000100"
diff --git a/tests/MC/ARM/neon-abs-encoding.s.yaml b/tests/MC/ARM/neon-abs-encoding.s.yaml
new file mode 100644
index 000000000..0dabf261b
--- /dev/null
+++ b/tests/MC/ARM/neon-abs-encoding.s.yaml
@@ -0,0 +1,36 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x03, 0xf1, 0xf3, 0x20, 0x03, 0xf5, 0xf3, 0x20, 0x03, 0xf9, 0xf3, 0x20, 0x07, 0xf9, 0xf3, 0x60, 0x03, 0xf1, 0xf3, 0x60, 0x03, 0xf5, 0xf3, 0x60, 0x03, 0xf9, 0xf3, 0x60, 0x07, 0xf9, 0xf3, 0x20, 0x07, 0xf0, 0xf3, 0x20, 0x07, 0xf4, 0xf3, 0x20, 0x07, 0xf8, 0xf3, 0x60, 0x07, 0xf0, 0xf3, 0x60, 0x07, 0xf4, 0xf3, 0x60, 0x07, 0xf8, 0xf3 ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ]
+    expected:
+      insns:
+        -
+          asm_text: "vabs.s8 d16, d16"
+        -
+          asm_text: "vabs.s16 d16, d16"
+        -
+          asm_text: "vabs.s32 d16, d16"
+        -
+          asm_text: "vabs.f32 d16, d16"
+        -
+          asm_text: "vabs.s8 q8, q8"
+        -
+          asm_text: "vabs.s16 q8, q8"
+        -
+          asm_text: "vabs.s32 q8, q8"
+        -
+          asm_text: "vabs.f32 q8, q8"
+        -
+          asm_text: "vqabs.s8 d16, d16"
+        -
+          asm_text: "vqabs.s16 d16, d16"
+        -
+          asm_text: "vqabs.s32 d16, d16"
+        -
+          asm_text: "vqabs.s8 q8, q8"
+        -
+          asm_text: "vqabs.s16 q8, q8"
+        -
+          asm_text: "vqabs.s32 q8, q8"
diff --git a/tests/MC/ARM/neon-absdiff-encoding.s.yaml b/tests/MC/ARM/neon-absdiff-encoding.s.yaml
new file mode 100644
index 000000000..11b03d419
--- /dev/null
+++ b/tests/MC/ARM/neon-absdiff-encoding.s.yaml
@@ -0,0 +1,84 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xa1, 0x07, 0x40, 0xf2, 0xa1, 0x07, 0x50, 0xf2, 0xa1, 0x07, 0x60, 0xf2, 0xa1, 0x07, 0x40, 0xf3, 0xa1, 0x07, 0x50, 0xf3, 0xa1, 0x07, 0x60, 0xf3, 0xa1, 0x0d, 0x60, 0xf3, 0xe2, 0x07, 0x40, 0xf2, 0xe2, 0x07, 0x50, 0xf2, 0xe2, 0x07, 0x60, 0xf2, 0xe2, 0x07, 0x40, 0xf3, 0xe2, 0x07, 0x50, 0xf3, 0xe2, 0x07, 0x60, 0xf3, 0xe2, 0x0d, 0x60, 0xf3, 0xa1, 0x07, 0xc0, 0xf2, 0xa1, 0x07, 0xd0, 0xf2, 0xa1, 0x07, 0xe0, 0xf2, 0xa1, 0x07, 0xc0, 0xf3, 0xa1, 0x07, 0xd0, 0xf3, 0xa1, 0x07, 0xe0, 0xf3, 0xb1, 0x07, 0x42, 0xf2, 0xb1, 0x07, 0x52, 0xf2, 0xb1, 0x07, 0x62, 0xf2, 0xb1, 0x07, 0x42, 0xf3, 0xb1, 0x07, 0x52, 0xf3, 0xb1, 0x07, 0x62, 0xf3, 0xf4, 0x27, 0x40, 0xf2, 0xf4, 0x27, 0x50, 0xf2, 0xf4, 0x27, 0x60, 0xf2, 0xf4, 0x27, 0x40, 0xf3, 0xf4, 0x27, 0x50, 0xf3, 0xf4, 0x27, 0x60, 0xf3, 0xa2, 0x05, 0xc3, 0xf2, 0xa2, 0x05, 0xd3, 0xf2, 0xa2, 0x05, 0xe3, 0xf2, 0xa2, 0x05, 0xc3, 0xf3, 0xa2, 0x05, 0xd3, 0xf3, 0xa2, 0x05, 0xe3, 0xf3 ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ]
+    expected:
+      insns:
+        -
+          asm_text: "vabd.s8 d16, d16, d17"
+        -
+          asm_text: "vabd.s16 d16, d16, d17"
+        -
+          asm_text: "vabd.s32 d16, d16, d17"
+        -
+          asm_text: "vabd.u8 d16, d16, d17"
+        -
+          asm_text: "vabd.u16 d16, d16, d17"
+        -
+          asm_text: "vabd.u32 d16, d16, d17"
+        -
+          asm_text: "vabd.f32 d16, d16, d17"
+        -
+          asm_text: "vabd.s8 q8, q8, q9"
+        -
+          asm_text: "vabd.s16 q8, q8, q9"
+        -
+          asm_text: "vabd.s32 q8, q8, q9"
+        -
+          asm_text: "vabd.u8 q8, q8, q9"
+        -
+          asm_text: "vabd.u16 q8, q8, q9"
+        -
+          asm_text: "vabd.u32 q8, q8, q9"
+        -
+          asm_text: "vabd.f32 q8, q8, q9"
+        -
+          asm_text: "vabdl.s8 q8, d16, d17"
+        -
+          asm_text: "vabdl.s16 q8, d16, d17"
+        -
+          asm_text: "vabdl.s32 q8, d16, d17"
+        -
+          asm_text: "vabdl.u8 q8, d16, d17"
+        -
+          asm_text: "vabdl.u16 q8, d16, d17"
+        -
+          asm_text: "vabdl.u32 q8, d16, d17"
+        -
+          asm_text: "vaba.s8 d16, d18, d17"
+        -
+          asm_text: "vaba.s16 d16, d18, d17"
+        -
+          asm_text: "vaba.s32 d16, d18, d17"
+        -
+          asm_text: "vaba.u8 d16, d18, d17"
+        -
+          asm_text: "vaba.u16 d16, d18, d17"
+        -
+          asm_text: "vaba.u32 d16, d18, d17"
+        -
+          asm_text: "vaba.s8 q9, q8, q10"
+        -
+          asm_text: "vaba.s16 q9, q8, q10"
+        -
+          asm_text: "vaba.s32 q9, q8, q10"
+        -
+          asm_text: "vaba.u8 q9, q8, q10"
+        -
+          asm_text: "vaba.u16 q9, q8, q10"
+        -
+          asm_text: "vaba.u32 q9, q8, q10"
+        -
+          asm_text: "vabal.s8 q8, d19, d18"
+        -
+          asm_text: "vabal.s16 q8, d19, d18"
+        -
+          asm_text: "vabal.s32 q8, d19, d18"
+        -
+          asm_text: "vabal.u8 q8, d19, d18"
+        -
+          asm_text: "vabal.u16 q8, d19, d18"
+        -
+          asm_text: "vabal.u32 q8, d19, d18"
diff --git a/tests/MC/ARM/neon-add-encoding.s.yaml b/tests/MC/ARM/neon-add-encoding.s.yaml
new file mode 100644
index 000000000..682dd4792
--- /dev/null
+++ b/tests/MC/ARM/neon-add-encoding.s.yaml
@@ -0,0 +1,244 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xa0, 0x08, 0x41, 0xf2, 0xa0, 0x08, 0x51, 0xf2, 0xa0, 0x08, 0x71, 0xf2, 0xa0, 0x08, 0x61, 0xf2, 0xa1, 0x0d, 0x40, 0xf2, 0xe2, 0x0d, 0x40, 0xf2, 0xa0, 0x00, 0xc1, 0xf2, 0xa0, 0x00, 0xd1, 0xf2, 0xa0, 0x00, 0xe1, 0xf2, 0xa0, 0x00, 0xc1, 0xf3, 0xa0, 0x00, 0xd1, 0xf3, 0xa0, 0x00, 0xe1, 0xf3, 0xa2, 0x01, 0xc0, 0xf2, 0xa2, 0x01, 0xd0, 0xf2, 0xa2, 0x01, 0xe0, 0xf2, 0xa2, 0x01, 0xc0, 0xf3, 0xa2, 0x01, 0xd0, 0xf3, 0xa2, 0x01, 0xe0, 0xf3, 0xa1, 0x00, 0x40, 0xf2, 0xa1, 0x00, 0x50, 0xf2, 0xa1, 0x00, 0x60, 0xf2, 0xa1, 0x00, 0x40, 0xf3, 0xa1, 0x00, 0x50, 0xf3, 0xa1, 0x00, 0x60, 0xf3, 0xe2, 0x00, 0x40, 0xf2, 0xe2, 0x00, 0x50, 0xf2, 0xe2, 0x00, 0x60, 0xf2, 0xe2, 0x00, 0x40, 0xf3, 0xe2, 0x00, 0x50, 0xf3, 0xe2, 0x00, 0x60, 0xf3, 0x28, 0xb0, 0x0b, 0xf2, 0x27, 0xc0, 0x1c, 0xf2, 0x26, 0xd0, 0x2d, 0xf2, 0x25, 0xe0, 0x0e, 0xf3, 0x24, 0xf0, 0x1f, 0xf3, 0xa3, 0x00, 0x60, 0xf3, 0x68, 0x20, 0x02, 0xf2, 0x66, 0x40, 0x14, 0xf2, 0x64, 0x60, 0x26, 0xf2, 0x62, 0x80, 0x08, 0xf3, 0x60, 0xa0, 0x1a, 0xf3, 0x4e, 0xc0, 0x2c, 0xf3, 0xa1, 0x01, 0x40, 0xf2, 0xa1, 0x01, 0x50, 0xf2, 0xa1, 0x01, 0x60, 0xf2, 0xa1, 0x01, 0x40, 0xf3, 0xa1, 0x01, 0x50, 0xf3, 0xa1, 0x01, 0x60, 0xf3, 0xe2, 0x01, 0x40, 0xf2, 0xe2, 0x01, 0x50, 0xf2, 0xe2, 0x01, 0x60, 0xf2, 0xe2, 0x01, 0x40, 0xf3, 0xe2, 0x01, 0x50, 0xf3, 0xe2, 0x01, 0x60, 0xf3, 0xa1, 0x01, 0x40, 0xf2, 0xa1, 0x01, 0x50, 0xf2, 0xa1, 0x01, 0x60, 0xf2, 0xa1, 0x01, 0x40, 0xf3, 0xa1, 0x01, 0x50, 0xf3, 0xa1, 0x01, 0x60, 0xf3, 0xe2, 0x01, 0x40, 0xf2, 0xe2, 0x01, 0x50, 0xf2, 0xe2, 0x01, 0x60, 0xf2, 0xe2, 0x01, 0x40, 0xf3, 0xe2, 0x01, 0x50, 0xf3, 0xe2, 0x01, 0x60, 0xf3, 0xb1, 0x00, 0x40, 0xf2, 0xb1, 0x00, 0x50, 0xf2, 0xb1, 0x00, 0x60, 0xf2, 0xb1, 0x00, 0x70, 0xf2, 0xb1, 0x00, 0x40, 0xf3, 0xb1, 0x00, 0x50, 0xf3, 0xb1, 0x00, 0x60, 0xf3, 0xb1, 0x00, 0x70, 0xf3, 0xf2, 0x00, 0x40, 0xf2, 0xf2, 0x00, 0x50, 0xf2, 0xf2, 0x00, 0x60, 0xf2, 0xf2, 0x00, 0x70, 0xf2, 0xf2, 0x00, 0x40, 0xf3, 0xf2, 0x00, 0x50, 0xf3, 0xf2, 0x00, 0x60, 0xf3, 0xf2, 0x00, 0x70, 0xf3, 0xb1, 0x00, 0x40, 0xf2, 0xb1, 0x00, 0x50, 0xf2, 0xb1, 0x00, 0x60, 0xf2, 0xb1, 0x00, 0x70, 0xf2, 0xb1, 0x00, 0x40, 0xf3, 0xb1, 0x00, 0x50, 0xf3, 0xb1, 0x00, 0x60, 0xf3, 0xb1, 0x00, 0x70, 0xf3, 0xf2, 0x00, 0x40, 0xf2, 0xf2, 0x00, 0x50, 0xf2, 0xf2, 0x00, 0x60, 0xf2, 0xf2, 0x00, 0x70, 0xf2, 0xf2, 0x00, 0x40, 0xf3, 0xf2, 0x00, 0x50, 0xf3, 0xf2, 0x00, 0x60, 0xf3, 0xf2, 0x00, 0x70, 0xf3, 0xa2, 0x04, 0xc0, 0xf2, 0xa2, 0x04, 0xd0, 0xf2, 0xa2, 0x04, 0xe0, 0xf2, 0xa2, 0x04, 0xc0, 0xf3, 0xa2, 0x04, 0xd0, 0xf3, 0xa2, 0x04, 0xe0, 0xf3, 0x05, 0x68, 0x06, 0xf2, 0x01, 0x78, 0x17, 0xf2, 0x02, 0x88, 0x28, 0xf2, 0x03, 0x98, 0x39, 0xf2, 0x4a, 0xc8, 0x0c, 0xf2, 0x42, 0xe8, 0x1e, 0xf2, 0xc4, 0x08, 0x60, 0xf2, 0xc6, 0x28, 0x72, 0xf2, 0x05, 0xc1, 0x8c, 0xf2, 0x01, 0xe1, 0x9e, 0xf2, 0x82, 0x01, 0xe0, 0xf2, 0x05, 0xc1, 0x8c, 0xf3, 0x01, 0xe1, 0x9e, 0xf3, 0x82, 0x01, 0xe0, 0xf3 ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ]
+    expected:
+      insns:
+        -
+          asm_text: "vadd.i8 d16, d17, d16"
+        -
+          asm_text: "vadd.i16 d16, d17, d16"
+        -
+          asm_text: "vadd.i64 d16, d17, d16"
+        -
+          asm_text: "vadd.i32 d16, d17, d16"
+        -
+          asm_text: "vadd.f32 d16, d16, d17"
+        -
+          asm_text: "vadd.f32 q8, q8, q9"
+        -
+          asm_text: "vaddl.s8 q8, d17, d16"
+        -
+          asm_text: "vaddl.s16 q8, d17, d16"
+        -
+          asm_text: "vaddl.s32 q8, d17, d16"
+        -
+          asm_text: "vaddl.u8 q8, d17, d16"
+        -
+          asm_text: "vaddl.u16 q8, d17, d16"
+        -
+          asm_text: "vaddl.u32 q8, d17, d16"
+        -
+          asm_text: "vaddw.s8 q8, q8, d18"
+        -
+          asm_text: "vaddw.s16 q8, q8, d18"
+        -
+          asm_text: "vaddw.s32 q8, q8, d18"
+        -
+          asm_text: "vaddw.u8 q8, q8, d18"
+        -
+          asm_text: "vaddw.u16 q8, q8, d18"
+        -
+          asm_text: "vaddw.u32 q8, q8, d18"
+        -
+          asm_text: "vhadd.s8 d16, d16, d17"
+        -
+          asm_text: "vhadd.s16 d16, d16, d17"
+        -
+          asm_text: "vhadd.s32 d16, d16, d17"
+        -
+          asm_text: "vhadd.u8 d16, d16, d17"
+        -
+          asm_text: "vhadd.u16 d16, d16, d17"
+        -
+          asm_text: "vhadd.u32 d16, d16, d17"
+        -
+          asm_text: "vhadd.s8 q8, q8, q9"
+        -
+          asm_text: "vhadd.s16 q8, q8, q9"
+        -
+          asm_text: "vhadd.s32 q8, q8, q9"
+        -
+          asm_text: "vhadd.u8 q8, q8, q9"
+        -
+          asm_text: "vhadd.u16 q8, q8, q9"
+        -
+          asm_text: "vhadd.u32 q8, q8, q9"
+        -
+          asm_text: "vhadd.s8 d11, d11, d24"
+        -
+          asm_text: "vhadd.s16 d12, d12, d23"
+        -
+          asm_text: "vhadd.s32 d13, d13, d22"
+        -
+          asm_text: "vhadd.u8 d14, d14, d21"
+        -
+          asm_text: "vhadd.u16 d15, d15, d20"
+        -
+          asm_text: "vhadd.u32 d16, d16, d19"
+        -
+          asm_text: "vhadd.s8 q1, q1, q12"
+        -
+          asm_text: "vhadd.s16 q2, q2, q11"
+        -
+          asm_text: "vhadd.s32 q3, q3, q10"
+        -
+          asm_text: "vhadd.u8 q4, q4, q9"
+        -
+          asm_text: "vhadd.u16 q5, q5, q8"
+        -
+          asm_text: "vhadd.u32 q6, q6, q7"
+        -
+          asm_text: "vrhadd.s8 d16, d16, d17"
+        -
+          asm_text: "vrhadd.s16 d16, d16, d17"
+        -
+          asm_text: "vrhadd.s32 d16, d16, d17"
+        -
+          asm_text: "vrhadd.u8 d16, d16, d17"
+        -
+          asm_text: "vrhadd.u16 d16, d16, d17"
+        -
+          asm_text: "vrhadd.u32 d16, d16, d17"
+        -
+          asm_text: "vrhadd.s8 q8, q8, q9"
+        -
+          asm_text: "vrhadd.s16 q8, q8, q9"
+        -
+          asm_text: "vrhadd.s32 q8, q8, q9"
+        -
+          asm_text: "vrhadd.u8 q8, q8, q9"
+        -
+          asm_text: "vrhadd.u16 q8, q8, q9"
+        -
+          asm_text: "vrhadd.u32 q8, q8, q9"
+        -
+          asm_text: "vrhadd.s8 d16, d16, d17"
+        -
+          asm_text: "vrhadd.s16 d16, d16, d17"
+        -
+          asm_text: "vrhadd.s32 d16, d16, d17"
+        -
+          asm_text: "vrhadd.u8 d16, d16, d17"
+        -
+          asm_text: "vrhadd.u16 d16, d16, d17"
+        -
+          asm_text: "vrhadd.u32 d16, d16, d17"
+        -
+          asm_text: "vrhadd.s8 q8, q8, q9"
+        -
+          asm_text: "vrhadd.s16 q8, q8, q9"
+        -
+          asm_text: "vrhadd.s32 q8, q8, q9"
+        -
+          asm_text: "vrhadd.u8 q8, q8, q9"
+        -
+          asm_text: "vrhadd.u16 q8, q8, q9"
+        -
+          asm_text: "vrhadd.u32 q8, q8, q9"
+        -
+          asm_text: "vqadd.s8 d16, d16, d17"
+        -
+          asm_text: "vqadd.s16 d16, d16, d17"
+        -
+          asm_text: "vqadd.s32 d16, d16, d17"
+        -
+          asm_text: "vqadd.s64 d16, d16, d17"
+        -
+          asm_text: "vqadd.u8 d16, d16, d17"
+        -
+          asm_text: "vqadd.u16 d16, d16, d17"
+        -
+          asm_text: "vqadd.u32 d16, d16, d17"
+        -
+          asm_text: "vqadd.u64 d16, d16, d17"
+        -
+          asm_text: "vqadd.s8 q8, q8, q9"
+        -
+          asm_text: "vqadd.s16 q8, q8, q9"
+        -
+          asm_text: "vqadd.s32 q8, q8, q9"
+        -
+          asm_text: "vqadd.s64 q8, q8, q9"
+        -
+          asm_text: "vqadd.u8 q8, q8, q9"
+        -
+          asm_text: "vqadd.u16 q8, q8, q9"
+        -
+          asm_text: "vqadd.u32 q8, q8, q9"
+        -
+          asm_text: "vqadd.u64 q8, q8, q9"
+        -
+          asm_text: "vqadd.s8 d16, d16, d17"
+        -
+          asm_text: "vqadd.s16 d16, d16, d17"
+        -
+          asm_text: "vqadd.s32 d16, d16, d17"
+        -
+          asm_text: "vqadd.s64 d16, d16, d17"
+        -
+          asm_text: "vqadd.u8 d16, d16, d17"
+        -
+          asm_text: "vqadd.u16 d16, d16, d17"
+        -
+          asm_text: "vqadd.u32 d16, d16, d17"
+        -
+          asm_text: "vqadd.u64 d16, d16, d17"
+        -
+          asm_text: "vqadd.s8 q8, q8, q9"
+        -
+          asm_text: "vqadd.s16 q8, q8, q9"
+        -
+          asm_text: "vqadd.s32 q8, q8, q9"
+        -
+          asm_text: "vqadd.s64 q8, q8, q9"
+        -
+          asm_text: "vqadd.u8 q8, q8, q9"
+        -
+          asm_text: "vqadd.u16 q8, q8, q9"
+        -
+          asm_text: "vqadd.u32 q8, q8, q9"
+        -
+          asm_text: "vqadd.u64 q8, q8, q9"
+        -
+          asm_text: "vaddhn.i16 d16, q8, q9"
+        -
+          asm_text: "vaddhn.i32 d16, q8, q9"
+        -
+          asm_text: "vaddhn.i64 d16, q8, q9"
+        -
+          asm_text: "vraddhn.i16 d16, q8, q9"
+        -
+          asm_text: "vraddhn.i32 d16, q8, q9"
+        -
+          asm_text: "vraddhn.i64 d16, q8, q9"
+        -
+          asm_text: "vadd.i8 d6, d6, d5"
+        -
+          asm_text: "vadd.i16 d7, d7, d1"
+        -
+          asm_text: "vadd.i32 d8, d8, d2"
+        -
+          asm_text: "vadd.i64 d9, d9, d3"
+        -
+          asm_text: "vadd.i8 q6, q6, q5"
+        -
+          asm_text: "vadd.i16 q7, q7, q1"
+        -
+          asm_text: "vadd.i32 q8, q8, q2"
+        -
+          asm_text: "vadd.i64 q9, q9, q3"
+        -
+          asm_text: "vaddw.s8 q6, q6, d5"
+        -
+          asm_text: "vaddw.s16 q7, q7, d1"
+        -
+          asm_text: "vaddw.s32 q8, q8, d2"
+        -
+          asm_text: "vaddw.u8 q6, q6, d5"
+        -
+          asm_text: "vaddw.u16 q7, q7, d1"
+        -
+          asm_text: "vaddw.u32 q8, q8, d2"
diff --git a/tests/MC/ARM/neon-bitcount-encoding.s.yaml b/tests/MC/ARM/neon-bitcount-encoding.s.yaml
new file mode 100644
index 000000000..44fcb1bcc
--- /dev/null
+++ b/tests/MC/ARM/neon-bitcount-encoding.s.yaml
@@ -0,0 +1,36 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x05, 0xf0, 0xf3, 0x60, 0x05, 0xf0, 0xf3, 0xa0, 0x04, 0xf0, 0xf3, 0xa0, 0x04, 0xf4, 0xf3, 0xa0, 0x04, 0xf8, 0xf3, 0xe0, 0x04, 0xf0, 0xf3, 0xe0, 0x04, 0xf4, 0xf3, 0xe0, 0x04, 0xf8, 0xf3, 0x20, 0x04, 0xf0, 0xf3, 0x20, 0x04, 0xf4, 0xf3, 0x20, 0x04, 0xf8, 0xf3, 0x60, 0x04, 0xf0, 0xf3, 0x60, 0x04, 0xf4, 0xf3, 0x60, 0x04, 0xf8, 0xf3 ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcnt.8 d16, d16"
+        -
+          asm_text: "vcnt.8 q8, q8"
+        -
+          asm_text: "vclz.i8 d16, d16"
+        -
+          asm_text: "vclz.i16 d16, d16"
+        -
+          asm_text: "vclz.i32 d16, d16"
+        -
+          asm_text: "vclz.i8 q8, q8"
+        -
+          asm_text: "vclz.i16 q8, q8"
+        -
+          asm_text: "vclz.i32 q8, q8"
+        -
+          asm_text: "vcls.s8 d16, d16"
+        -
+          asm_text: "vcls.s16 d16, d16"
+        -
+          asm_text: "vcls.s32 d16, d16"
+        -
+          asm_text: "vcls.s8 q8, q8"
+        -
+          asm_text: "vcls.s16 q8, q8"
+        -
+          asm_text: "vcls.s32 q8, q8"
diff --git a/tests/MC/ARM/neon-bitwise-encoding.s.yaml b/tests/MC/ARM/neon-bitwise-encoding.s.yaml
new file mode 100644
index 000000000..df1ee145f
--- /dev/null
+++ b/tests/MC/ARM/neon-bitwise-encoding.s.yaml
@@ -0,0 +1,310 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xb0, 0x01, 0x41, 0xf2, 0xf2, 0x01, 0x40, 0xf2, 0xb0, 0x01, 0x41, 0xf3, 0xf2, 0x01, 0x40, 0xf3, 0xb0, 0x01, 0x61, 0xf2, 0xf2, 0x01, 0x60, 0xf2, 0x11, 0x07, 0xc0, 0xf2, 0x51, 0x07, 0xc0, 0xf2, 0x50, 0x01, 0xc0, 0xf2, 0xb0, 0x01, 0x51, 0xf2, 0xf2, 0x01, 0x50, 0xf2, 0xf6, 0x41, 0x54, 0xf2, 0x11, 0x91, 0x19, 0xf2, 0x3f, 0x0b, 0xc7, 0xf3, 0x7f, 0x0b, 0xc7, 0xf3, 0x3f, 0x09, 0xc7, 0xf3, 0x7f, 0x09, 0xc7, 0xf3, 0x3f, 0x07, 0xc7, 0xf3, 0x7f, 0x07, 0xc7, 0xf3, 0x3f, 0x05, 0xc7, 0xf3, 0x7f, 0x05, 0xc7, 0xf3, 0x3f, 0x03, 0xc7, 0xf3, 0x7f, 0x03, 0xc7, 0xf3, 0x3f, 0x01, 0xc7, 0xf3, 0x7f, 0x01, 0xc7, 0xf3, 0x3c, 0xa9, 0x87, 0xf3, 0x7c, 0x49, 0xc7, 0xf3, 0x3c, 0xab, 0x87, 0xf3, 0x7c, 0x4b, 0xc7, 0xf3, 0x3c, 0xa7, 0x87, 0xf3, 0x7c, 0x47, 0xc7, 0xf3, 0x3c, 0xa5, 0x87, 0xf3, 0x7c, 0x45, 0xc7, 0xf3, 0x3c, 0xa3, 0x87, 0xf3, 0x7c, 0x43, 0xc7, 0xf3, 0x3c, 0xa1, 0x87, 0xf3, 0x7c, 0x41, 0xc7, 0xf3, 0xb0, 0x01, 0x71, 0xf2, 0xf2, 0x01, 0x70, 0xf2, 0xa0, 0x05, 0xf0, 0xf3, 0xe0, 0x05, 0xf0, 0xf3, 0xb0, 0x21, 0x51, 0xf3, 0xf2, 0x01, 0x54, 0xf3, 0xb0, 0x21, 0x61, 0xf3, 0xf2, 0x01, 0x64, 0xf3, 0xb0, 0x21, 0x71, 0xf3, 0xf2, 0x01, 0x74, 0xf3, 0x56, 0x81, 0x0e, 0xf3, 0x56, 0x81, 0x0e, 0xf3, 0x56, 0x81, 0x0e, 0xf3, 0x56, 0x81, 0x0e, 0xf3, 0x56, 0x81, 0x0e, 0xf3, 0x56, 0x81, 0x0e, 0xf3, 0x56, 0x81, 0x0e, 0xf3, 0x56, 0x81, 0x0e, 0xf3, 0x56, 0x81, 0x0e, 0xf3, 0x56, 0x81, 0x0e, 0xf3, 0x56, 0x81, 0x0e, 0xf3, 0x56, 0x81, 0x0e, 0xf3, 0x56, 0x81, 0x0e, 0xf3, 0x56, 0x81, 0x0e, 0xf3, 0x56, 0x81, 0x0e, 0xf3, 0x56, 0x81, 0x0e, 0xf3, 0x56, 0x81, 0x0e, 0xf3, 0x56, 0x81, 0x0e, 0xf3, 0x56, 0x81, 0x0e, 0xf3, 0x56, 0x81, 0x0e, 0xf3, 0x56, 0x81, 0x0e, 0xf3, 0x56, 0x81, 0x0e, 0xf3, 0x56, 0x81, 0x0e, 0xf3, 0x13, 0x41, 0x07, 0xf2, 0x13, 0x41, 0x07, 0xf2, 0x13, 0x41, 0x07, 0xf2, 0x13, 0x41, 0x07, 0xf2, 0x13, 0x41, 0x07, 0xf2, 0x13, 0x41, 0x07, 0xf2, 0x13, 0x41, 0x07, 0xf2, 0x13, 0x41, 0x07, 0xf2, 0x13, 0x41, 0x07, 0xf2, 0x13, 0x41, 0x07, 0xf2, 0x13, 0x41, 0x07, 0xf2, 0x13, 0x41, 0x07, 0xf2, 0x13, 0x41, 0x07, 0xf2, 0x13, 0x41, 0x07, 0xf2, 0x13, 0x41, 0x07, 0xf2, 0x13, 0x41, 0x07, 0xf2, 0x13, 0x41, 0x07, 0xf2, 0x13, 0x41, 0x07, 0xf2, 0x13, 0x41, 0x07, 0xf2, 0x13, 0x41, 0x07, 0xf2, 0x13, 0x41, 0x07, 0xf2, 0x13, 0x41, 0x07, 0xf2, 0x13, 0x41, 0x07, 0xf2, 0x13, 0x41, 0x27, 0xf2, 0x13, 0x41, 0x27, 0xf2, 0x13, 0x41, 0x27, 0xf2, 0x13, 0x41, 0x27, 0xf2, 0x13, 0x41, 0x27, 0xf2, 0x13, 0x41, 0x27, 0xf2, 0x13, 0x41, 0x27, 0xf2, 0x13, 0x41, 0x27, 0xf2, 0x13, 0x41, 0x27, 0xf2, 0x13, 0x41, 0x27, 0xf2, 0x13, 0x41, 0x27, 0xf2, 0x56, 0x81, 0x2e, 0xf2, 0x56, 0x81, 0x2e, 0xf2, 0x56, 0x81, 0x2e, 0xf2, 0x56, 0x81, 0x2e, 0xf2, 0x56, 0x81, 0x2e, 0xf2, 0x56, 0x81, 0x2e, 0xf2, 0x56, 0x81, 0x2e, 0xf2, 0x56, 0x81, 0x2e, 0xf2, 0x56, 0x81, 0x2e, 0xf2, 0x56, 0x81, 0x2e, 0xf2, 0x56, 0x81, 0x2e, 0xf2, 0x56, 0x81, 0x2e, 0xf2, 0x5a, 0xc1, 0x0c, 0xf2, 0x5a, 0xc1, 0x0c, 0xf2, 0x52, 0xe1, 0x0e, 0xf2, 0xd4, 0x01, 0x40, 0xf2, 0xd4, 0x01, 0x40, 0xf2, 0x5a, 0xc1, 0x0c, 0xf3, 0x5a, 0xc1, 0x0c, 0xf3, 0x52, 0xe1, 0x0e, 0xf3, 0xd4, 0x01, 0x40, 0xf3, 0xd4, 0x01, 0x40, 0xf3, 0x5a, 0xc1, 0x0c, 0xf3, 0x5a, 0xc1, 0x0c, 0xf3, 0x52, 0xe1, 0x0e, 0xf3, 0xd4, 0x01, 0x40, 0xf3, 0xd4, 0x01, 0x40, 0xf3, 0x4a, 0xa2, 0xb5, 0xf3, 0x05, 0x52, 0xb5, 0xf3, 0x56, 0xa8, 0x1a, 0xf3, 0x13, 0x58, 0x15, 0xf3, 0x46, 0xa3, 0x1a, 0xf2, 0x03, 0x53, 0x15, 0xf2, 0x56, 0xa3, 0x1a, 0xf2, 0x13, 0x53, 0x15, 0xf2, 0x4a, 0xa0, 0xb5, 0xf3, 0x05, 0x50, 0xb5, 0xf3, 0xca, 0xa0, 0xb5, 0xf3, 0x85, 0x50, 0xb5, 0xf3, 0x4a, 0xa1, 0xb5, 0xf3, 0x05, 0x51, 0xb5, 0xf3, 0xca, 0xa1, 0xb5, 0xf3, 0x85, 0x51, 0xb5, 0xf3, 0x3e, 0x5e, 0x05, 0xf3, 0x56, 0xae, 0x0a, 0xf3, 0x3e, 0x5e, 0x25, 0xf3, 0x56, 0xae, 0x2a, 0xf3 ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ]
+    expected:
+      insns:
+        -
+          asm_text: "vand d16, d17, d16"
+        -
+          asm_text: "vand q8, q8, q9"
+        -
+          asm_text: "veor d16, d17, d16"
+        -
+          asm_text: "veor q8, q8, q9"
+        -
+          asm_text: "vorr d16, d17, d16"
+        -
+          asm_text: "vorr q8, q8, q9"
+        -
+          asm_text: "vorr.i32 d16, #0x1000000"
+        -
+          asm_text: "vorr.i32 q8, #0x1000000"
+        -
+          asm_text: "vorr.i32 q8, #0x0"
+        -
+          asm_text: "vbic d16, d17, d16"
+        -
+          asm_text: "vbic q8, q8, q9"
+        -
+          asm_text: "vbic q10, q10, q11"
+        -
+          asm_text: "vbic d9, d9, d1"
+        -
+          asm_text: "vbic.i16 d16, #0xff00"
+        -
+          asm_text: "vbic.i16 q8, #0xff00"
+        -
+          asm_text: "vbic.i16 d16, #0xff"
+        -
+          asm_text: "vbic.i16 q8, #0xff"
+        -
+          asm_text: "vbic.i32 d16, #0xff000000"
+        -
+          asm_text: "vbic.i32 q8, #0xff000000"
+        -
+          asm_text: "vbic.i32 d16, #0xff0000"
+        -
+          asm_text: "vbic.i32 q8, #0xff0000"
+        -
+          asm_text: "vbic.i32 d16, #0xff00"
+        -
+          asm_text: "vbic.i32 q8, #0xff00"
+        -
+          asm_text: "vbic.i32 d16, #0xff"
+        -
+          asm_text: "vbic.i32 q8, #0xff"
+        -
+          asm_text: "vbic.i16 d10, #0xfc"
+        -
+          asm_text: "vbic.i16 q10, #0xfc"
+        -
+          asm_text: "vbic.i16 d10, #0xfc00"
+        -
+          asm_text: "vbic.i16 q10, #0xfc00"
+        -
+          asm_text: "vbic.i32 d10, #0xfc000000"
+        -
+          asm_text: "vbic.i32 q10, #0xfc000000"
+        -
+          asm_text: "vbic.i32 d10, #0xfc0000"
+        -
+          asm_text: "vbic.i32 q10, #0xfc0000"
+        -
+          asm_text: "vbic.i32 d10, #0xfc00"
+        -
+          asm_text: "vbic.i32 q10, #0xfc00"
+        -
+          asm_text: "vbic.i32 d10, #0xfc"
+        -
+          asm_text: "vbic.i32 q10, #0xfc"
+        -
+          asm_text: "vorn d16, d17, d16"
+        -
+          asm_text: "vorn q8, q8, q9"
+        -
+          asm_text: "vmvn d16, d16"
+        -
+          asm_text: "vmvn q8, q8"
+        -
+          asm_text: "vbsl d18, d17, d16"
+        -
+          asm_text: "vbsl q8, q10, q9"
+        -
+          asm_text: "vbit d18, d17, d16"
+        -
+          asm_text: "vbit q8, q10, q9"
+        -
+          asm_text: "vbif d18, d17, d16"
+        -
+          asm_text: "vbif q8, q10, q9"
+        -
+          asm_text: "veor q4, q7, q3"
+        -
+          asm_text: "veor q4, q7, q3"
+        -
+          asm_text: "veor q4, q7, q3"
+        -
+          asm_text: "veor q4, q7, q3"
+        -
+          asm_text: "veor q4, q7, q3"
+        -
+          asm_text: "veor q4, q7, q3"
+        -
+          asm_text: "veor q4, q7, q3"
+        -
+          asm_text: "veor q4, q7, q3"
+        -
+          asm_text: "veor q4, q7, q3"
+        -
+          asm_text: "veor q4, q7, q3"
+        -
+          asm_text: "veor q4, q7, q3"
+        -
+          asm_text: "veor q4, q7, q3"
+        -
+          asm_text: "veor q4, q7, q3"
+        -
+          asm_text: "veor q4, q7, q3"
+        -
+          asm_text: "veor q4, q7, q3"
+        -
+          asm_text: "veor q4, q7, q3"
+        -
+          asm_text: "veor q4, q7, q3"
+        -
+          asm_text: "veor q4, q7, q3"
+        -
+          asm_text: "veor q4, q7, q3"
+        -
+          asm_text: "veor q4, q7, q3"
+        -
+          asm_text: "veor q4, q7, q3"
+        -
+          asm_text: "veor q4, q7, q3"
+        -
+          asm_text: "veor q4, q7, q3"
+        -
+          asm_text: "vand d4, d7, d3"
+        -
+          asm_text: "vand d4, d7, d3"
+        -
+          asm_text: "vand d4, d7, d3"
+        -
+          asm_text: "vand d4, d7, d3"
+        -
+          asm_text: "vand d4, d7, d3"
+        -
+          asm_text: "vand d4, d7, d3"
+        -
+          asm_text: "vand d4, d7, d3"
+        -
+          asm_text: "vand d4, d7, d3"
+        -
+          asm_text: "vand d4, d7, d3"
+        -
+          asm_text: "vand d4, d7, d3"
+        -
+          asm_text: "vand d4, d7, d3"
+        -
+          asm_text: "vand d4, d7, d3"
+        -
+          asm_text: "vand d4, d7, d3"
+        -
+          asm_text: "vand d4, d7, d3"
+        -
+          asm_text: "vand d4, d7, d3"
+        -
+          asm_text: "vand d4, d7, d3"
+        -
+          asm_text: "vand d4, d7, d3"
+        -
+          asm_text: "vand d4, d7, d3"
+        -
+          asm_text: "vand d4, d7, d3"
+        -
+          asm_text: "vand d4, d7, d3"
+        -
+          asm_text: "vand d4, d7, d3"
+        -
+          asm_text: "vand d4, d7, d3"
+        -
+          asm_text: "vand d4, d7, d3"
+        -
+          asm_text: "vorr d4, d7, d3"
+        -
+          asm_text: "vorr d4, d7, d3"
+        -
+          asm_text: "vorr d4, d7, d3"
+        -
+          asm_text: "vorr d4, d7, d3"
+        -
+          asm_text: "vorr d4, d7, d3"
+        -
+          asm_text: "vorr d4, d7, d3"
+        -
+          asm_text: "vorr d4, d7, d3"
+        -
+          asm_text: "vorr d4, d7, d3"
+        -
+          asm_text: "vorr d4, d7, d3"
+        -
+          asm_text: "vorr d4, d7, d3"
+        -
+          asm_text: "vorr d4, d7, d3"
+        -
+          asm_text: "vorr q4, q7, q3"
+        -
+          asm_text: "vorr q4, q7, q3"
+        -
+          asm_text: "vorr q4, q7, q3"
+        -
+          asm_text: "vorr q4, q7, q3"
+        -
+          asm_text: "vorr q4, q7, q3"
+        -
+          asm_text: "vorr q4, q7, q3"
+        -
+          asm_text: "vorr q4, q7, q3"
+        -
+          asm_text: "vorr q4, q7, q3"
+        -
+          asm_text: "vorr q4, q7, q3"
+        -
+          asm_text: "vorr q4, q7, q3"
+        -
+          asm_text: "vorr q4, q7, q3"
+        -
+          asm_text: "vorr q4, q7, q3"
+        -
+          asm_text: "vand q6, q6, q5"
+        -
+          asm_text: "vand q6, q6, q5"
+        -
+          asm_text: "vand q7, q7, q1"
+        -
+          asm_text: "vand q8, q8, q2"
+        -
+          asm_text: "vand q8, q8, q2"
+        -
+          asm_text: "veor q6, q6, q5"
+        -
+          asm_text: "veor q6, q6, q5"
+        -
+          asm_text: "veor q7, q7, q1"
+        -
+          asm_text: "veor q8, q8, q2"
+        -
+          asm_text: "veor q8, q8, q2"
+        -
+          asm_text: "veor q6, q6, q5"
+        -
+          asm_text: "veor q6, q6, q5"
+        -
+          asm_text: "veor q7, q7, q1"
+        -
+          asm_text: "veor q8, q8, q2"
+        -
+          asm_text: "veor q8, q8, q2"
+        -
+          asm_text: "vclt.s16 q5, q5, #0"
+        -
+          asm_text: "vclt.s16 d5, d5, #0"
+        -
+          asm_text: "vceq.i16 q5, q5, q3"
+        -
+          asm_text: "vceq.i16 d5, d5, d3"
+        -
+          asm_text: "vcgt.s16 q5, q5, q3"
+        -
+          asm_text: "vcgt.s16 d5, d5, d3"
+        -
+          asm_text: "vcge.s16 q5, q5, q3"
+        -
+          asm_text: "vcge.s16 d5, d5, d3"
+        -
+          asm_text: "vcgt.s16 q5, q5, #0"
+        -
+          asm_text: "vcgt.s16 d5, d5, #0"
+        -
+          asm_text: "vcge.s16 q5, q5, #0"
+        -
+          asm_text: "vcge.s16 d5, d5, #0"
+        -
+          asm_text: "vceq.i16 q5, q5, #0"
+        -
+          asm_text: "vceq.i16 d5, d5, #0"
+        -
+          asm_text: "vcle.s16 q5, q5, #0"
+        -
+          asm_text: "vcle.s16 d5, d5, #0"
+        -
+          asm_text: "vacge.f32 d5, d5, d30"
+        -
+          asm_text: "vacge.f32 q5, q5, q3"
+        -
+          asm_text: "vacgt.f32 d5, d5, d30"
+        -
+          asm_text: "vacgt.f32 q5, q5, q3"
diff --git a/tests/MC/ARM/neon-cmp-encoding.s.yaml b/tests/MC/ARM/neon-cmp-encoding.s.yaml
new file mode 100644
index 000000000..8a72f2fce
--- /dev/null
+++ b/tests/MC/ARM/neon-cmp-encoding.s.yaml
@@ -0,0 +1,182 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xb1, 0x08, 0x40, 0xf3, 0xb1, 0x08, 0x50, 0xf3, 0xb1, 0x08, 0x60, 0xf3, 0xa1, 0x0e, 0x40, 0xf2, 0xf2, 0x08, 0x40, 0xf3, 0xf2, 0x08, 0x50, 0xf3, 0xf2, 0x08, 0x60, 0xf3, 0xe2, 0x0e, 0x40, 0xf2, 0xb1, 0x03, 0x40, 0xf2, 0xb1, 0x03, 0x50, 0xf2, 0xb1, 0x03, 0x60, 0xf2, 0xb1, 0x03, 0x40, 0xf3, 0xb1, 0x03, 0x50, 0xf3, 0xb1, 0x03, 0x60, 0xf3, 0xa1, 0x0e, 0x40, 0xf3, 0xf2, 0x03, 0x40, 0xf2, 0xf2, 0x03, 0x50, 0xf2, 0xf2, 0x03, 0x60, 0xf2, 0xf2, 0x03, 0x40, 0xf3, 0xf2, 0x03, 0x50, 0xf3, 0xf2, 0x03, 0x60, 0xf3, 0xe2, 0x0e, 0x40, 0xf3, 0xb1, 0x0e, 0x40, 0xf3, 0xf2, 0x0e, 0x40, 0xf3, 0xa1, 0x03, 0x40, 0xf2, 0xa1, 0x03, 0x50, 0xf2, 0xa1, 0x03, 0x60, 0xf2, 0xa1, 0x03, 0x40, 0xf3, 0xa1, 0x03, 0x50, 0xf3, 0xa1, 0x03, 0x60, 0xf3, 0xa1, 0x0e, 0x60, 0xf3, 0xe2, 0x03, 0x40, 0xf2, 0xe2, 0x03, 0x50, 0xf2, 0xe2, 0x03, 0x60, 0xf2, 0xe2, 0x03, 0x40, 0xf3, 0xe2, 0x03, 0x50, 0xf3, 0xe2, 0x03, 0x60, 0xf3, 0xe2, 0x0e, 0x60, 0xf3, 0xb1, 0x0e, 0x60, 0xf3, 0xf2, 0x0e, 0x60, 0xf3, 0xb1, 0x08, 0x40, 0xf2, 0xb1, 0x08, 0x50, 0xf2, 0xb1, 0x08, 0x60, 0xf2, 0xf2, 0x08, 0x40, 0xf2, 0xf2, 0x08, 0x50, 0xf2, 0xf2, 0x08, 0x60, 0xf2, 0x20, 0x01, 0xf1, 0xf3, 0xa0, 0x00, 0xf1, 0xf3, 0xa0, 0x01, 0xf1, 0xf3, 0x20, 0x00, 0xf1, 0xf3, 0x20, 0x02, 0xf1, 0xf3, 0x6a, 0x83, 0x46, 0xf2, 0x6a, 0x83, 0x56, 0xf2, 0x6a, 0x83, 0x66, 0xf2, 0x6a, 0x83, 0x46, 0xf3, 0x6a, 0x83, 0x56, 0xf3, 0x6a, 0x83, 0x66, 0xf3, 0x6a, 0x8e, 0x66, 0xf3, 0x0d, 0xc3, 0x03, 0xf2, 0x0d, 0xc3, 0x13, 0xf2, 0x0d, 0xc3, 0x23, 0xf2, 0x0d, 0xc3, 0x03, 0xf3, 0x0d, 0xc3, 0x13, 0xf3, 0x0d, 0xc3, 0x23, 0xf3, 0x0d, 0xce, 0x23, 0xf3, 0xb0, 0x03, 0x41, 0xf2, 0xb0, 0x03, 0x51, 0xf2, 0xb0, 0x03, 0x61, 0xf2, 0xb0, 0x03, 0x41, 0xf3, 0xb0, 0x03, 0x51, 0xf3, 0xb0, 0x03, 0x61, 0xf3, 0xa0, 0x0e, 0x41, 0xf3, 0xf0, 0x03, 0x42, 0xf2, 0xf0, 0x03, 0x52, 0xf2, 0xf0, 0x03, 0x62, 0xf2, 0xf0, 0x03, 0x42, 0xf3, 0xf0, 0x03, 0x52, 0xf3, 0xf0, 0x03, 0x62, 0xf3, 0xe0, 0x0e, 0x42, 0xf3, 0xf6, 0x2e, 0x68, 0xf3, 0x1b, 0x9e, 0x2c, 0xf3, 0xf6, 0x6e, 0x68, 0xf3, 0x1b, 0xbe, 0x2c, 0xf3, 0xf6, 0x2e, 0x48, 0xf3, 0x1b, 0x9e, 0x0c, 0xf3, 0xf6, 0x6e, 0x48, 0xf3, 0x1b, 0xbe, 0x0c, 0xf3 ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ]
+    expected:
+      insns:
+        -
+          asm_text: "vceq.i8 d16, d16, d17"
+        -
+          asm_text: "vceq.i16 d16, d16, d17"
+        -
+          asm_text: "vceq.i32 d16, d16, d17"
+        -
+          asm_text: "vceq.f32 d16, d16, d17"
+        -
+          asm_text: "vceq.i8 q8, q8, q9"
+        -
+          asm_text: "vceq.i16 q8, q8, q9"
+        -
+          asm_text: "vceq.i32 q8, q8, q9"
+        -
+          asm_text: "vceq.f32 q8, q8, q9"
+        -
+          asm_text: "vcge.s8 d16, d16, d17"
+        -
+          asm_text: "vcge.s16 d16, d16, d17"
+        -
+          asm_text: "vcge.s32 d16, d16, d17"
+        -
+          asm_text: "vcge.u8 d16, d16, d17"
+        -
+          asm_text: "vcge.u16 d16, d16, d17"
+        -
+          asm_text: "vcge.u32 d16, d16, d17"
+        -
+          asm_text: "vcge.f32 d16, d16, d17"
+        -
+          asm_text: "vcge.s8 q8, q8, q9"
+        -
+          asm_text: "vcge.s16 q8, q8, q9"
+        -
+          asm_text: "vcge.s32 q8, q8, q9"
+        -
+          asm_text: "vcge.u8 q8, q8, q9"
+        -
+          asm_text: "vcge.u16 q8, q8, q9"
+        -
+          asm_text: "vcge.u32 q8, q8, q9"
+        -
+          asm_text: "vcge.f32 q8, q8, q9"
+        -
+          asm_text: "vacge.f32 d16, d16, d17"
+        -
+          asm_text: "vacge.f32 q8, q8, q9"
+        -
+          asm_text: "vcgt.s8 d16, d16, d17"
+        -
+          asm_text: "vcgt.s16 d16, d16, d17"
+        -
+          asm_text: "vcgt.s32 d16, d16, d17"
+        -
+          asm_text: "vcgt.u8 d16, d16, d17"
+        -
+          asm_text: "vcgt.u16 d16, d16, d17"
+        -
+          asm_text: "vcgt.u32 d16, d16, d17"
+        -
+          asm_text: "vcgt.f32 d16, d16, d17"
+        -
+          asm_text: "vcgt.s8 q8, q8, q9"
+        -
+          asm_text: "vcgt.s16 q8, q8, q9"
+        -
+          asm_text: "vcgt.s32 q8, q8, q9"
+        -
+          asm_text: "vcgt.u8 q8, q8, q9"
+        -
+          asm_text: "vcgt.u16 q8, q8, q9"
+        -
+          asm_text: "vcgt.u32 q8, q8, q9"
+        -
+          asm_text: "vcgt.f32 q8, q8, q9"
+        -
+          asm_text: "vacgt.f32 d16, d16, d17"
+        -
+          asm_text: "vacgt.f32 q8, q8, q9"
+        -
+          asm_text: "vtst.8 d16, d16, d17"
+        -
+          asm_text: "vtst.16 d16, d16, d17"
+        -
+          asm_text: "vtst.32 d16, d16, d17"
+        -
+          asm_text: "vtst.8 q8, q8, q9"
+        -
+          asm_text: "vtst.16 q8, q8, q9"
+        -
+          asm_text: "vtst.32 q8, q8, q9"
+        -
+          asm_text: "vceq.i8 d16, d16, #0"
+        -
+          asm_text: "vcge.s8 d16, d16, #0"
+        -
+          asm_text: "vcle.s8 d16, d16, #0"
+        -
+          asm_text: "vcgt.s8 d16, d16, #0"
+        -
+          asm_text: "vclt.s8 d16, d16, #0"
+        -
+          asm_text: "vcgt.s8 q12, q3, q13"
+        -
+          asm_text: "vcgt.s16 q12, q3, q13"
+        -
+          asm_text: "vcgt.s32 q12, q3, q13"
+        -
+          asm_text: "vcgt.u8 q12, q3, q13"
+        -
+          asm_text: "vcgt.u16 q12, q3, q13"
+        -
+          asm_text: "vcgt.u32 q12, q3, q13"
+        -
+          asm_text: "vcgt.f32 q12, q3, q13"
+        -
+          asm_text: "vcgt.s8 d12, d3, d13"
+        -
+          asm_text: "vcgt.s16 d12, d3, d13"
+        -
+          asm_text: "vcgt.s32 d12, d3, d13"
+        -
+          asm_text: "vcgt.u8 d12, d3, d13"
+        -
+          asm_text: "vcgt.u16 d12, d3, d13"
+        -
+          asm_text: "vcgt.u32 d12, d3, d13"
+        -
+          asm_text: "vcgt.f32 d12, d3, d13"
+        -
+          asm_text: "vcge.s8 d16, d17, d16"
+        -
+          asm_text: "vcge.s16 d16, d17, d16"
+        -
+          asm_text: "vcge.s32 d16, d17, d16"
+        -
+          asm_text: "vcge.u8 d16, d17, d16"
+        -
+          asm_text: "vcge.u16 d16, d17, d16"
+        -
+          asm_text: "vcge.u32 d16, d17, d16"
+        -
+          asm_text: "vcge.f32 d16, d17, d16"
+        -
+          asm_text: "vcge.s8 q8, q9, q8"
+        -
+          asm_text: "vcge.s16 q8, q9, q8"
+        -
+          asm_text: "vcge.s32 q8, q9, q8"
+        -
+          asm_text: "vcge.u8 q8, q9, q8"
+        -
+          asm_text: "vcge.u16 q8, q9, q8"
+        -
+          asm_text: "vcge.u32 q8, q9, q8"
+        -
+          asm_text: "vcge.f32 q8, q9, q8"
+        -
+          asm_text: "vacgt.f32 q9, q12, q11"
+        -
+          asm_text: "vacgt.f32 d9, d12, d11"
+        -
+          asm_text: "vacgt.f32 q11, q12, q11"
+        -
+          asm_text: "vacgt.f32 d11, d12, d11"
+        -
+          asm_text: "vacge.f32 q9, q12, q11"
+        -
+          asm_text: "vacge.f32 d9, d12, d11"
+        -
+          asm_text: "vacge.f32 q11, q12, q11"
+        -
+          asm_text: "vacge.f32 d11, d12, d11"
diff --git a/tests/MC/ARM/neon-convert-encoding.s.yaml b/tests/MC/ARM/neon-convert-encoding.s.yaml
new file mode 100644
index 000000000..dd1a7b4f3
--- /dev/null
+++ b/tests/MC/ARM/neon-convert-encoding.s.yaml
@@ -0,0 +1,60 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x07, 0xfb, 0xf3, 0xa0, 0x07, 0xfb, 0xf3, 0x20, 0x06, 0xfb, 0xf3, 0xa0, 0x06, 0xfb, 0xf3, 0x60, 0x07, 0xfb, 0xf3, 0xe0, 0x07, 0xfb, 0xf3, 0x60, 0x06, 0xfb, 0xf3, 0xe0, 0x06, 0xfb, 0xf3, 0x30, 0x0f, 0xff, 0xf2, 0x20, 0x07, 0xfb, 0xf3, 0x30, 0x0f, 0xff, 0xf3, 0xa0, 0x07, 0xfb, 0xf3, 0x30, 0x0e, 0xff, 0xf2, 0x20, 0x06, 0xfb, 0xf3, 0x30, 0x0e, 0xff, 0xf3, 0xa0, 0x06, 0xfb, 0xf3, 0x70, 0x0f, 0xff, 0xf2, 0x60, 0x07, 0xfb, 0xf3, 0x70, 0x0f, 0xff, 0xf3, 0xe0, 0x07, 0xfb, 0xf3, 0x70, 0x0e, 0xff, 0xf2, 0x60, 0x06, 0xfb, 0xf3, 0x70, 0x0e, 0xff, 0xf3, 0xe0, 0x06, 0xfb, 0xf3, 0x20, 0x07, 0xf6, 0xf3, 0x20, 0x06, 0xf6, 0xf3 ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvt.s32.f32 d16, d16"
+        -
+          asm_text: "vcvt.u32.f32 d16, d16"
+        -
+          asm_text: "vcvt.f32.s32 d16, d16"
+        -
+          asm_text: "vcvt.f32.u32 d16, d16"
+        -
+          asm_text: "vcvt.s32.f32 q8, q8"
+        -
+          asm_text: "vcvt.u32.f32 q8, q8"
+        -
+          asm_text: "vcvt.f32.s32 q8, q8"
+        -
+          asm_text: "vcvt.f32.u32 q8, q8"
+        -
+          asm_text: "vcvt.s32.f32 d16, d16, #1"
+        -
+          asm_text: "vcvt.s32.f32 d16, d16"
+        -
+          asm_text: "vcvt.u32.f32 d16, d16, #1"
+        -
+          asm_text: "vcvt.u32.f32 d16, d16"
+        -
+          asm_text: "vcvt.f32.s32 d16, d16, #1"
+        -
+          asm_text: "vcvt.f32.s32 d16, d16"
+        -
+          asm_text: "vcvt.f32.u32 d16, d16, #1"
+        -
+          asm_text: "vcvt.f32.u32 d16, d16"
+        -
+          asm_text: "vcvt.s32.f32 q8, q8, #1"
+        -
+          asm_text: "vcvt.s32.f32 q8, q8"
+        -
+          asm_text: "vcvt.u32.f32 q8, q8, #1"
+        -
+          asm_text: "vcvt.u32.f32 q8, q8"
+        -
+          asm_text: "vcvt.f32.s32 q8, q8, #1"
+        -
+          asm_text: "vcvt.f32.s32 q8, q8"
+        -
+          asm_text: "vcvt.f32.u32 q8, q8, #1"
+        -
+          asm_text: "vcvt.f32.u32 q8, q8"
+        -
+          asm_text: "vcvt.f32.f16 q8, d16"
+        -
+          asm_text: "vcvt.f16.f32 d16, q8"
diff --git a/tests/MC/ARM/neon-crypto.s.yaml b/tests/MC/ARM/neon-crypto.s.yaml
new file mode 100644
index 000000000..bcabb88d5
--- /dev/null
+++ b/tests/MC/ARM/neon-crypto.s.yaml
@@ -0,0 +1,38 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x42, 0x03, 0xb0, 0xf3, 0x02, 0x03, 0xb0, 0xf3, 0xc2, 0x03, 0xb0, 0xf3, 0x82, 0x03, 0xb0, 0xf3, 0xc2, 0x02, 0xb9, 0xf3, 0x82, 0x03, 0xba, 0xf3, 0xc2, 0x03, 0xba, 0xf3, 0x44, 0x0c, 0x02, 0xf2, 0x44, 0x0c, 0x22, 0xf2, 0x44, 0x0c, 0x12, 0xf2, 0x44, 0x0c, 0x32, 0xf2, 0x44, 0x0c, 0x02, 0xf3, 0x44, 0x0c, 0x12, 0xf3, 0x44, 0x0c, 0x22, 0xf3, 0xa1, 0x0e, 0xe0, 0xf2 ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_V8", "CS_MODE_ARM" ]
+    expected:
+      insns:
+        -
+          asm_text: "aesd.8 q0, q1"
+        -
+          asm_text: "aese.8 q0, q1"
+        -
+          asm_text: "aesimc.8 q0, q1"
+        -
+          asm_text: "aesmc.8 q0, q1"
+        -
+          asm_text: "sha1h.32 q0, q1"
+        -
+          asm_text: "sha1su1.32 q0, q1"
+        -
+          asm_text: "sha256su0.32 q0, q1"
+        -
+          asm_text: "sha1c.32 q0, q1, q2"
+        -
+          asm_text: "sha1m.32 q0, q1, q2"
+        -
+          asm_text: "sha1p.32 q0, q1, q2"
+        -
+          asm_text: "sha1su0.32 q0, q1, q2"
+        -
+          asm_text: "sha256h.32 q0, q1, q2"
+        -
+          asm_text: "sha256h2.32 q0, q1, q2"
+        -
+          asm_text: "sha256su1.32 q0, q1, q2"
+        -
+          asm_text: "vmull.p64 q8, d16, d17"
diff --git a/tests/MC/ARM/neon-dup-encoding.s.yaml b/tests/MC/ARM/neon-dup-encoding.s.yaml
new file mode 100644
index 000000000..00c93e4bb
--- /dev/null
+++ b/tests/MC/ARM/neon-dup-encoding.s.yaml
@@ -0,0 +1,32 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x90, 0x0b, 0xc0, 0xee, 0xb0, 0x0b, 0x80, 0xee, 0x90, 0x0b, 0x80, 0xee, 0x90, 0x0b, 0xe0, 0xee, 0xb0, 0x0b, 0xa0, 0xee, 0x90, 0x0b, 0xa0, 0xee, 0x20, 0x0c, 0xf3, 0xf3, 0x20, 0x0c, 0xf6, 0xf3, 0x20, 0x0c, 0xfc, 0xf3, 0x60, 0x0c, 0xf3, 0xf3, 0x60, 0x0c, 0xf6, 0xf3, 0x60, 0x0c, 0xfc, 0xf3 ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ]
+    expected:
+      insns:
+        -
+          asm_text: "vdup.8 d16, r0"
+        -
+          asm_text: "vdup.16 d16, r0"
+        -
+          asm_text: "vdup.32 d16, r0"
+        -
+          asm_text: "vdup.8 q8, r0"
+        -
+          asm_text: "vdup.16 q8, r0"
+        -
+          asm_text: "vdup.32 q8, r0"
+        -
+          asm_text: "vdup.8 d16, d16[1]"
+        -
+          asm_text: "vdup.16 d16, d16[1]"
+        -
+          asm_text: "vdup.32 d16, d16[1]"
+        -
+          asm_text: "vdup.8 q8, d16[1]"
+        -
+          asm_text: "vdup.16 q8, d16[1]"
+        -
+          asm_text: "vdup.32 q8, d16[1]"
diff --git a/tests/MC/ARM/neon-minmax-encoding.s.yaml b/tests/MC/ARM/neon-minmax-encoding.s.yaml
new file mode 100644
index 000000000..83bb5e228
--- /dev/null
+++ b/tests/MC/ARM/neon-minmax-encoding.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x03, 0x16, 0x02, 0xf2, 0x06, 0x46, 0x15, 0xf2, 0x09, 0x76, 0x28, 0xf2, 0x0c, 0xa6, 0x0b, 0xf3, 0x0f, 0xd6, 0x1e, 0xf3, 0xa2, 0x06, 0x61, 0xf3, 0xa5, 0x3f, 0x44, 0xf2, 0x03, 0x26, 0x02, 0xf2, 0x06, 0x56, 0x15, 0xf2, 0x09, 0x86, 0x28, 0xf2, 0x0c, 0xb6, 0x0b, 0xf3, 0x0f, 0xe6, 0x1e, 0xf3, 0xa2, 0x16, 0x61, 0xf3, 0xa5, 0x4f, 0x44, 0xf2, 0x46, 0x26, 0x04, 0xf2, 0x4c, 0x86, 0x1a, 0xf2, 0xe2, 0xe6, 0x20, 0xf2, 0xe8, 0x46, 0x46, 0xf3, 0xee, 0xa6, 0x5c, 0xf3, 0x60, 0xc6, 0x2e, 0xf3, 0x42, 0x2f, 0x4a, 0xf2, 0x46, 0x46, 0x04, 0xf2, 0x4c, 0xa6, 0x1a, 0xf2, 0xe2, 0x06, 0x60, 0xf2, 0xc4, 0x66, 0x46, 0xf3, 0x4a, 0x86, 0x18, 0xf3, 0x60, 0xe6, 0x2e, 0xf3, 0x42, 0x4f, 0x04, 0xf2, 0x13, 0x16, 0x02, 0xf2, 0x16, 0x46, 0x15, 0xf2, 0x19, 0x76, 0x28, 0xf2, 0x1c, 0xa6, 0x0b, 0xf3, 0x1f, 0xd6, 0x1e, 0xf3, 0xb2, 0x06, 0x61, 0xf3, 0xa5, 0x3f, 0x64, 0xf2, 0x13, 0x26, 0x02, 0xf2, 0x16, 0x56, 0x15, 0xf2, 0x19, 0x86, 0x28, 0xf2, 0x1c, 0xb6, 0x0b, 0xf3, 0x1f, 0xe6, 0x1e, 0xf3, 0xb2, 0x16, 0x61, 0xf3, 0xa5, 0x4f, 0x64, 0xf2, 0x56, 0x26, 0x04, 0xf2, 0x5c, 0x86, 0x1a, 0xf2, 0xf2, 0xe6, 0x20, 0xf2, 0xf8, 0x46, 0x46, 0xf3, 0xfe, 0xa6, 0x5c, 0xf3, 0x70, 0xc6, 0x2e, 0xf3, 0x42, 0x2f, 0x6a, 0xf2, 0x56, 0x46, 0x04, 0xf2, 0x5c, 0xa6, 0x1a, 0xf2, 0xf2, 0x06, 0x60, 0xf2, 0xd4, 0x66, 0x46, 0xf3, 0x5a, 0x86, 0x18, 0xf3, 0x70, 0xe6, 0x2e, 0xf3, 0x42, 0x4f, 0x24, 0xf2 ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmax.s8 d1, d2, d3"
+        -
+          asm_text: "vmax.s16 d4, d5, d6"
+        -
+          asm_text: "vmax.s32 d7, d8, d9"
+        -
+          asm_text: "vmax.u8 d10, d11, d12"
+        -
+          asm_text: "vmax.u16 d13, d14, d15"
+        -
+          asm_text: "vmax.u32 d16, d17, d18"
+        -
+          asm_text: "vmax.f32 d19, d20, d21"
+        -
+          asm_text: "vmax.s8 d2, d2, d3"
+        -
+          asm_text: "vmax.s16 d5, d5, d6"
+        -
+          asm_text: "vmax.s32 d8, d8, d9"
+        -
+          asm_text: "vmax.u8 d11, d11, d12"
+        -
+          asm_text: "vmax.u16 d14, d14, d15"
+        -
+          asm_text: "vmax.u32 d17, d17, d18"
+        -
+          asm_text: "vmax.f32 d20, d20, d21"
+        -
+          asm_text: "vmax.s8 q1, q2, q3"
+        -
+          asm_text: "vmax.s16 q4, q5, q6"
+        -
+          asm_text: "vmax.s32 q7, q8, q9"
+        -
+          asm_text: "vmax.u8 q10, q11, q12"
+        -
+          asm_text: "vmax.u16 q13, q14, q15"
+        -
+          asm_text: "vmax.u32 q6, q7, q8"
+        -
+          asm_text: "vmax.f32 q9, q5, q1"
+        -
+          asm_text: "vmax.s8 q2, q2, q3"
+        -
+          asm_text: "vmax.s16 q5, q5, q6"
+        -
+          asm_text: "vmax.s32 q8, q8, q9"
+        -
+          asm_text: "vmax.u8 q11, q11, q2"
+        -
+          asm_text: "vmax.u16 q4, q4, q5"
+        -
+          asm_text: "vmax.u32 q7, q7, q8"
+        -
+          asm_text: "vmax.f32 q2, q2, q1"
+        -
+          asm_text: "vmin.s8 d1, d2, d3"
+        -
+          asm_text: "vmin.s16 d4, d5, d6"
+        -
+          asm_text: "vmin.s32 d7, d8, d9"
+        -
+          asm_text: "vmin.u8 d10, d11, d12"
+        -
+          asm_text: "vmin.u16 d13, d14, d15"
+        -
+          asm_text: "vmin.u32 d16, d17, d18"
+        -
+          asm_text: "vmin.f32 d19, d20, d21"
+        -
+          asm_text: "vmin.s8 d2, d2, d3"
+        -
+          asm_text: "vmin.s16 d5, d5, d6"
+        -
+          asm_text: "vmin.s32 d8, d8, d9"
+        -
+          asm_text: "vmin.u8 d11, d11, d12"
+        -
+          asm_text: "vmin.u16 d14, d14, d15"
+        -
+          asm_text: "vmin.u32 d17, d17, d18"
+        -
+          asm_text: "vmin.f32 d20, d20, d21"
+        -
+          asm_text: "vmin.s8 q1, q2, q3"
+        -
+          asm_text: "vmin.s16 q4, q5, q6"
+        -
+          asm_text: "vmin.s32 q7, q8, q9"
+        -
+          asm_text: "vmin.u8 q10, q11, q12"
+        -
+          asm_text: "vmin.u16 q13, q14, q15"
+        -
+          asm_text: "vmin.u32 q6, q7, q8"
+        -
+          asm_text: "vmin.f32 q9, q5, q1"
+        -
+          asm_text: "vmin.s8 q2, q2, q3"
+        -
+          asm_text: "vmin.s16 q5, q5, q6"
+        -
+          asm_text: "vmin.s32 q8, q8, q9"
+        -
+          asm_text: "vmin.u8 q11, q11, q2"
+        -
+          asm_text: "vmin.u16 q4, q4, q5"
+        -
+          asm_text: "vmin.u32 q7, q7, q8"
+        -
+          asm_text: "vmin.f32 q2, q2, q1"
diff --git a/tests/MC/ARM/neon-mov-encoding.s.yaml b/tests/MC/ARM/neon-mov-encoding.s.yaml
new file mode 100644
index 000000000..52866b208
--- /dev/null
+++ b/tests/MC/ARM/neon-mov-encoding.s.yaml
@@ -0,0 +1,158 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x18, 0x0e, 0xc0, 0xf2, 0x10, 0x08, 0xc1, 0xf2, 0x10, 0x0a, 0xc1, 0xf2, 0x10, 0x00, 0xc2, 0xf2, 0x10, 0x02, 0xc2, 0xf2, 0x10, 0x04, 0xc2, 0xf2, 0x10, 0x06, 0xc2, 0xf2, 0x10, 0x0c, 0xc2, 0xf2, 0x10, 0x0d, 0xc2, 0xf2, 0x33, 0x0e, 0xc1, 0xf3, 0x58, 0x0e, 0xc0, 0xf2, 0x50, 0x08, 0xc1, 0xf2, 0x50, 0x0a, 0xc1, 0xf2, 0x50, 0x00, 0xc2, 0xf2, 0x50, 0x02, 0xc2, 0xf2, 0x50, 0x04, 0xc2, 0xf2, 0x50, 0x06, 0xc2, 0xf2, 0x50, 0x0c, 0xc2, 0xf2, 0x50, 0x0d, 0xc2, 0xf2, 0x73, 0x0e, 0xc1, 0xf3, 0x30, 0x08, 0xc1, 0xf2, 0x30, 0x0a, 0xc1, 0xf2, 0x30, 0x00, 0xc2, 0xf2, 0x30, 0x02, 0xc2, 0xf2, 0x30, 0x04, 0xc2, 0xf2, 0x30, 0x06, 0xc2, 0xf2, 0x30, 0x0c, 0xc2, 0xf2, 0x30, 0x0d, 0xc2, 0xf2, 0x30, 0x0a, 0xc8, 0xf2, 0x30, 0x0a, 0xd0, 0xf2, 0x30, 0x0a, 0xe0, 0xf2, 0x30, 0x0a, 0xc8, 0xf3, 0x30, 0x0a, 0xd0, 0xf3, 0x30, 0x0a, 0xe0, 0xf3, 0x20, 0x02, 0xf2, 0xf3, 0x20, 0x02, 0xf6, 0xf3, 0x20, 0x02, 0xfa, 0xf3, 0xa0, 0x02, 0xf2, 0xf3, 0xa0, 0x02, 0xf6, 0xf3, 0xa0, 0x02, 0xfa, 0xf3, 0xe0, 0x02, 0xf2, 0xf3, 0xe0, 0x02, 0xf6, 0xf3, 0xe0, 0x02, 0xfa, 0xf3, 0x60, 0x02, 0xf2, 0xf3, 0x60, 0x02, 0xf6, 0xf3, 0x60, 0x02, 0xfa, 0xf3, 0xb0, 0x0b, 0x50, 0xee, 0xf0, 0x0b, 0x10, 0xee, 0xb0, 0x0b, 0xd0, 0xee, 0xf0, 0x0b, 0x90, 0xee, 0x90, 0x0b, 0x30, 0xee, 0xb0, 0x1b, 0x40, 0xee, 0xf0, 0x1b, 0x00, 0xee, 0x90, 0x1b, 0x20, 0xee, 0xb0, 0x1b, 0x42, 0xee, 0xf0, 0x1b, 0x02, 0xee, 0x90, 0x1b, 0x22, 0xee, 0x82, 0x15, 0xb0, 0xf3, 0x82, 0x15, 0xb0, 0xf3, 0x82, 0x15, 0xb0, 0xf3, 0x82, 0x15, 0xb0, 0xf3, 0x82, 0x15, 0xb0, 0xf3, 0x82, 0x15, 0xb0, 0xf3, 0x82, 0x15, 0xb0, 0xf3, 0x82, 0x15, 0xb0, 0xf3, 0x82, 0x15, 0xb0, 0xf3, 0x82, 0x15, 0xb0, 0xf3, 0x82, 0x15, 0xb0, 0xf3, 0x82, 0x15, 0xb0, 0xf3, 0x82, 0x15, 0xb0, 0xf3, 0x82, 0x15, 0xb0, 0xf3, 0x82, 0x15, 0xb0, 0xf3, 0x82, 0x15, 0xb0, 0xf3, 0x82, 0x15, 0xb0, 0xf3, 0x82, 0x15, 0xb0, 0xf3 ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmov.i8 d16, #0x8"
+        -
+          asm_text: "vmov.i16 d16, #0x10"
+        -
+          asm_text: "vmov.i16 d16, #0x1000"
+        -
+          asm_text: "vmov.i32 d16, #0x20"
+        -
+          asm_text: "vmov.i32 d16, #0x2000"
+        -
+          asm_text: "vmov.i32 d16, #0x200000"
+        -
+          asm_text: "vmov.i32 d16, #0x20000000"
+        -
+          asm_text: "vmov.i32 d16, #0x20ff"
+        -
+          asm_text: "vmov.i32 d16, #0x20ffff"
+        -
+          asm_text: "vmov.i64 d16, #0xff0000ff0000ffff"
+        -
+          asm_text: "vmov.i8 q8, #0x8"
+        -
+          asm_text: "vmov.i16 q8, #0x10"
+        -
+          asm_text: "vmov.i16 q8, #0x1000"
+        -
+          asm_text: "vmov.i32 q8, #0x20"
+        -
+          asm_text: "vmov.i32 q8, #0x2000"
+        -
+          asm_text: "vmov.i32 q8, #0x200000"
+        -
+          asm_text: "vmov.i32 q8, #0x20000000"
+        -
+          asm_text: "vmov.i32 q8, #0x20ff"
+        -
+          asm_text: "vmov.i32 q8, #0x20ffff"
+        -
+          asm_text: "vmov.i64 q8, #0xff0000ff0000ffff"
+        -
+          asm_text: "vmvn.i16 d16, #0x10"
+        -
+          asm_text: "vmvn.i16 d16, #0x1000"
+        -
+          asm_text: "vmvn.i32 d16, #0x20"
+        -
+          asm_text: "vmvn.i32 d16, #0x2000"
+        -
+          asm_text: "vmvn.i32 d16, #0x200000"
+        -
+          asm_text: "vmvn.i32 d16, #0x20000000"
+        -
+          asm_text: "vmvn.i32 d16, #0x20ff"
+        -
+          asm_text: "vmvn.i32 d16, #0x20ffff"
+        -
+          asm_text: "vmovl.s8 q8, d16"
+        -
+          asm_text: "vmovl.s16 q8, d16"
+        -
+          asm_text: "vmovl.s32 q8, d16"
+        -
+          asm_text: "vmovl.u8 q8, d16"
+        -
+          asm_text: "vmovl.u16 q8, d16"
+        -
+          asm_text: "vmovl.u32 q8, d16"
+        -
+          asm_text: "vmovn.i16 d16, q8"
+        -
+          asm_text: "vmovn.i32 d16, q8"
+        -
+          asm_text: "vmovn.i64 d16, q8"
+        -
+          asm_text: "vqmovn.s16 d16, q8"
+        -
+          asm_text: "vqmovn.s32 d16, q8"
+        -
+          asm_text: "vqmovn.s64 d16, q8"
+        -
+          asm_text: "vqmovn.u16 d16, q8"
+        -
+          asm_text: "vqmovn.u32 d16, q8"
+        -
+          asm_text: "vqmovn.u64 d16, q8"
+        -
+          asm_text: "vqmovun.s16 d16, q8"
+        -
+          asm_text: "vqmovun.s32 d16, q8"
+        -
+          asm_text: "vqmovun.s64 d16, q8"
+        -
+          asm_text: "vmov.s8 r0, d16[1]"
+        -
+          asm_text: "vmov.s16 r0, d16[1]"
+        -
+          asm_text: "vmov.u8 r0, d16[1]"
+        -
+          asm_text: "vmov.u16 r0, d16[1]"
+        -
+          asm_text: "vmov.32 r0, d16[1]"
+        -
+          asm_text: "vmov.8 d16[1], r1"
+        -
+          asm_text: "vmov.16 d16[1], r1"
+        -
+          asm_text: "vmov.32 d16[1], r1"
+        -
+          asm_text: "vmov.8 d18[1], r1"
+        -
+          asm_text: "vmov.16 d18[1], r1"
+        -
+          asm_text: "vmov.32 d18[1], r1"
+        -
+          asm_text: "vmvn d1, d2"
+        -
+          asm_text: "vmvn d1, d2"
+        -
+          asm_text: "vmvn d1, d2"
+        -
+          asm_text: "vmvn d1, d2"
+        -
+          asm_text: "vmvn d1, d2"
+        -
+          asm_text: "vmvn d1, d2"
+        -
+          asm_text: "vmvn d1, d2"
+        -
+          asm_text: "vmvn d1, d2"
+        -
+          asm_text: "vmvn d1, d2"
+        -
+          asm_text: "vmvn d1, d2"
+        -
+          asm_text: "vmvn d1, d2"
+        -
+          asm_text: "vmvn d1, d2"
+        -
+          asm_text: "vmvn d1, d2"
+        -
+          asm_text: "vmvn d1, d2"
+        -
+          asm_text: "vmvn d1, d2"
+        -
+          asm_text: "vmvn d1, d2"
+        -
+          asm_text: "vmvn d1, d2"
+        -
+          asm_text: "vmvn d1, d2"
diff --git a/tests/MC/ARM/neon-mul-accum-encoding.s.yaml b/tests/MC/ARM/neon-mul-accum-encoding.s.yaml
new file mode 100644
index 000000000..023b3df0c
--- /dev/null
+++ b/tests/MC/ARM/neon-mul-accum-encoding.s.yaml
@@ -0,0 +1,84 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xa1, 0x09, 0x42, 0xf2, 0xa1, 0x09, 0x52, 0xf2, 0xa1, 0x09, 0x62, 0xf2, 0xb1, 0x0d, 0x42, 0xf2, 0xe4, 0x29, 0x40, 0xf2, 0xe4, 0x29, 0x50, 0xf2, 0xe4, 0x29, 0x60, 0xf2, 0xf4, 0x2d, 0x40, 0xf2, 0xc3, 0x80, 0xe0, 0xf3, 0xa2, 0x08, 0xc3, 0xf2, 0xa2, 0x08, 0xd3, 0xf2, 0xa2, 0x08, 0xe3, 0xf2, 0xa2, 0x08, 0xc3, 0xf3, 0xa2, 0x08, 0xd3, 0xf3, 0xa2, 0x08, 0xe3, 0xf3, 0xa2, 0x09, 0xd3, 0xf2, 0xa2, 0x09, 0xe3, 0xf2, 0x47, 0x63, 0xdb, 0xf2, 0x4f, 0x63, 0xdb, 0xf2, 0x67, 0x63, 0xdb, 0xf2, 0x6f, 0x63, 0xdb, 0xf2, 0xa1, 0x09, 0x42, 0xf3, 0xa1, 0x09, 0x52, 0xf3, 0xa1, 0x09, 0x62, 0xf3, 0xb1, 0x0d, 0x62, 0xf2, 0xe4, 0x29, 0x40, 0xf3, 0xe4, 0x29, 0x50, 0xf3, 0xe4, 0x29, 0x60, 0xf3, 0xf4, 0x2d, 0x60, 0xf2, 0xe6, 0x84, 0x98, 0xf3, 0xa2, 0x0a, 0xc3, 0xf2, 0xa2, 0x0a, 0xd3, 0xf2, 0xa2, 0x0a, 0xe3, 0xf2, 0xa2, 0x0a, 0xc3, 0xf3, 0xa2, 0x0a, 0xd3, 0xf3, 0xa2, 0x0a, 0xe3, 0xf3, 0xa2, 0x0b, 0xd3, 0xf2, 0xa2, 0x0b, 0xe3, 0xf2 ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmla.i8 d16, d18, d17"
+        -
+          asm_text: "vmla.i16 d16, d18, d17"
+        -
+          asm_text: "vmla.i32 d16, d18, d17"
+        -
+          asm_text: "vmla.f32 d16, d18, d17"
+        -
+          asm_text: "vmla.i8 q9, q8, q10"
+        -
+          asm_text: "vmla.i16 q9, q8, q10"
+        -
+          asm_text: "vmla.i32 q9, q8, q10"
+        -
+          asm_text: "vmla.f32 q9, q8, q10"
+        -
+          asm_text: "vmla.i32 q12, q8, d3[0]"
+        -
+          asm_text: "vmlal.s8 q8, d19, d18"
+        -
+          asm_text: "vmlal.s16 q8, d19, d18"
+        -
+          asm_text: "vmlal.s32 q8, d19, d18"
+        -
+          asm_text: "vmlal.u8 q8, d19, d18"
+        -
+          asm_text: "vmlal.u16 q8, d19, d18"
+        -
+          asm_text: "vmlal.u32 q8, d19, d18"
+        -
+          asm_text: "vqdmlal.s16 q8, d19, d18"
+        -
+          asm_text: "vqdmlal.s32 q8, d19, d18"
+        -
+          asm_text: "vqdmlal.s16 q11, d11, d7[0]"
+        -
+          asm_text: "vqdmlal.s16 q11, d11, d7[1]"
+        -
+          asm_text: "vqdmlal.s16 q11, d11, d7[2]"
+        -
+          asm_text: "vqdmlal.s16 q11, d11, d7[3]"
+        -
+          asm_text: "vmls.i8 d16, d18, d17"
+        -
+          asm_text: "vmls.i16 d16, d18, d17"
+        -
+          asm_text: "vmls.i32 d16, d18, d17"
+        -
+          asm_text: "vmls.f32 d16, d18, d17"
+        -
+          asm_text: "vmls.i8 q9, q8, q10"
+        -
+          asm_text: "vmls.i16 q9, q8, q10"
+        -
+          asm_text: "vmls.i32 q9, q8, q10"
+        -
+          asm_text: "vmls.f32 q9, q8, q10"
+        -
+          asm_text: "vmls.i16 q4, q12, d6[2]"
+        -
+          asm_text: "vmlsl.s8 q8, d19, d18"
+        -
+          asm_text: "vmlsl.s16 q8, d19, d18"
+        -
+          asm_text: "vmlsl.s32 q8, d19, d18"
+        -
+          asm_text: "vmlsl.u8 q8, d19, d18"
+        -
+          asm_text: "vmlsl.u16 q8, d19, d18"
+        -
+          asm_text: "vmlsl.u32 q8, d19, d18"
+        -
+          asm_text: "vqdmlsl.s16 q8, d19, d18"
+        -
+          asm_text: "vqdmlsl.s32 q8, d19, d18"
diff --git a/tests/MC/ARM/neon-mul-encoding.s.yaml b/tests/MC/ARM/neon-mul-encoding.s.yaml
new file mode 100644
index 000000000..9d31fcd86
--- /dev/null
+++ b/tests/MC/ARM/neon-mul-encoding.s.yaml
@@ -0,0 +1,150 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xb1, 0x09, 0x40, 0xf2, 0xb1, 0x09, 0x50, 0xf2, 0xb1, 0x09, 0x60, 0xf2, 0xb1, 0x0d, 0x40, 0xf3, 0xf2, 0x09, 0x40, 0xf2, 0xf2, 0x09, 0x50, 0xf2, 0xf2, 0x09, 0x60, 0xf2, 0xf2, 0x0d, 0x40, 0xf3, 0xb1, 0x09, 0x40, 0xf3, 0xf2, 0x09, 0x40, 0xf3, 0x68, 0x28, 0xd8, 0xf2, 0xb1, 0x09, 0x40, 0xf2, 0xb1, 0x09, 0x50, 0xf2, 0xb1, 0x09, 0x60, 0xf2, 0xb1, 0x0d, 0x40, 0xf3, 0xf2, 0x09, 0x40, 0xf2, 0xf2, 0x09, 0x50, 0xf2, 0xf2, 0x09, 0x60, 0xf2, 0xf2, 0x0d, 0x40, 0xf3, 0xb1, 0x09, 0x40, 0xf3, 0xf2, 0x09, 0x40, 0xf3, 0xa1, 0x0b, 0x50, 0xf2, 0xa1, 0x0b, 0x60, 0xf2, 0xe2, 0x0b, 0x50, 0xf2, 0xe2, 0x0b, 0x60, 0xf2, 0xa1, 0x0b, 0x50, 0xf2, 0xa1, 0x0b, 0x60, 0xf2, 0xe2, 0x0b, 0x50, 0xf2, 0xe2, 0x0b, 0x60, 0xf2, 0x43, 0xbc, 0x92, 0xf2, 0xa1, 0x0b, 0x50, 0xf3, 0xa1, 0x0b, 0x60, 0xf3, 0xe2, 0x0b, 0x50, 0xf3, 0xe2, 0x0b, 0x60, 0xf3, 0xa1, 0x0c, 0xc0, 0xf2, 0xa1, 0x0c, 0xd0, 0xf2, 0xa1, 0x0c, 0xe0, 0xf2, 0xa1, 0x0c, 0xc0, 0xf3, 0xa1, 0x0c, 0xd0, 0xf3, 0xa1, 0x0c, 0xe0, 0xf3, 0xa1, 0x0e, 0xc0, 0xf2, 0xa1, 0x0d, 0xd0, 0xf2, 0xa1, 0x0d, 0xe0, 0xf2, 0x64, 0x08, 0x90, 0xf2, 0x6f, 0x18, 0x91, 0xf2, 0x49, 0x28, 0x92, 0xf2, 0x42, 0x38, 0xa3, 0xf2, 0x63, 0x48, 0xa4, 0xf2, 0x44, 0x58, 0xa5, 0xf2, 0x65, 0x69, 0xa6, 0xf2, 0x64, 0x08, 0x90, 0xf3, 0x6f, 0x28, 0x92, 0xf3, 0x49, 0x48, 0x94, 0xf3, 0x42, 0x68, 0xa6, 0xf3, 0x63, 0x88, 0xa8, 0xf3, 0x44, 0xa8, 0xaa, 0xf3, 0x65, 0xc9, 0xac, 0xf3, 0x64, 0x98, 0x90, 0xf2, 0x6f, 0x88, 0x91, 0xf2, 0x49, 0x78, 0x92, 0xf2, 0x42, 0x68, 0xa3, 0xf2, 0x63, 0x58, 0xa4, 0xf2, 0x44, 0x48, 0xa5, 0xf2, 0x65, 0x39, 0xa6, 0xf2, 0x64, 0x28, 0xd0, 0xf3, 0x6f, 0x08, 0xd2, 0xf3, 0x49, 0xe8, 0x94, 0xf3, 0x42, 0xc8, 0xa6, 0xf3, 0x63, 0xa8, 0xa8, 0xf3, 0x44, 0x88, 0xaa, 0xf3, 0x65, 0x69, 0xac, 0xf3 ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmul.i8 d16, d16, d17"
+        -
+          asm_text: "vmul.i16 d16, d16, d17"
+        -
+          asm_text: "vmul.i32 d16, d16, d17"
+        -
+          asm_text: "vmul.f32 d16, d16, d17"
+        -
+          asm_text: "vmul.i8 q8, q8, q9"
+        -
+          asm_text: "vmul.i16 q8, q8, q9"
+        -
+          asm_text: "vmul.i32 q8, q8, q9"
+        -
+          asm_text: "vmul.f32 q8, q8, q9"
+        -
+          asm_text: "vmul.p8 d16, d16, d17"
+        -
+          asm_text: "vmul.p8 q8, q8, q9"
+        -
+          asm_text: "vmul.i16 d18, d8, d0[3]"
+        -
+          asm_text: "vmul.i8 d16, d16, d17"
+        -
+          asm_text: "vmul.i16 d16, d16, d17"
+        -
+          asm_text: "vmul.i32 d16, d16, d17"
+        -
+          asm_text: "vmul.f32 d16, d16, d17"
+        -
+          asm_text: "vmul.i8 q8, q8, q9"
+        -
+          asm_text: "vmul.i16 q8, q8, q9"
+        -
+          asm_text: "vmul.i32 q8, q8, q9"
+        -
+          asm_text: "vmul.f32 q8, q8, q9"
+        -
+          asm_text: "vmul.p8 d16, d16, d17"
+        -
+          asm_text: "vmul.p8 q8, q8, q9"
+        -
+          asm_text: "vqdmulh.s16 d16, d16, d17"
+        -
+          asm_text: "vqdmulh.s32 d16, d16, d17"
+        -
+          asm_text: "vqdmulh.s16 q8, q8, q9"
+        -
+          asm_text: "vqdmulh.s32 q8, q8, q9"
+        -
+          asm_text: "vqdmulh.s16 d16, d16, d17"
+        -
+          asm_text: "vqdmulh.s32 d16, d16, d17"
+        -
+          asm_text: "vqdmulh.s16 q8, q8, q9"
+        -
+          asm_text: "vqdmulh.s32 q8, q8, q9"
+        -
+          asm_text: "vqdmulh.s16 d11, d2, d3[0]"
+        -
+          asm_text: "vqrdmulh.s16 d16, d16, d17"
+        -
+          asm_text: "vqrdmulh.s32 d16, d16, d17"
+        -
+          asm_text: "vqrdmulh.s16 q8, q8, q9"
+        -
+          asm_text: "vqrdmulh.s32 q8, q8, q9"
+        -
+          asm_text: "vmull.s8 q8, d16, d17"
+        -
+          asm_text: "vmull.s16 q8, d16, d17"
+        -
+          asm_text: "vmull.s32 q8, d16, d17"
+        -
+          asm_text: "vmull.u8 q8, d16, d17"
+        -
+          asm_text: "vmull.u16 q8, d16, d17"
+        -
+          asm_text: "vmull.u32 q8, d16, d17"
+        -
+          asm_text: "vmull.p8 q8, d16, d17"
+        -
+          asm_text: "vqdmull.s16 q8, d16, d17"
+        -
+          asm_text: "vqdmull.s32 q8, d16, d17"
+        -
+          asm_text: "vmul.i16 d0, d0, d4[2]"
+        -
+          asm_text: "vmul.i16 d1, d1, d7[3]"
+        -
+          asm_text: "vmul.i16 d2, d2, d1[1]"
+        -
+          asm_text: "vmul.i32 d3, d3, d2[0]"
+        -
+          asm_text: "vmul.i32 d4, d4, d3[1]"
+        -
+          asm_text: "vmul.i32 d5, d5, d4[0]"
+        -
+          asm_text: "vmul.f32 d6, d6, d5[1]"
+        -
+          asm_text: "vmul.i16 q0, q0, d4[2]"
+        -
+          asm_text: "vmul.i16 q1, q1, d7[3]"
+        -
+          asm_text: "vmul.i16 q2, q2, d1[1]"
+        -
+          asm_text: "vmul.i32 q3, q3, d2[0]"
+        -
+          asm_text: "vmul.i32 q4, q4, d3[1]"
+        -
+          asm_text: "vmul.i32 q5, q5, d4[0]"
+        -
+          asm_text: "vmul.f32 q6, q6, d5[1]"
+        -
+          asm_text: "vmul.i16 d9, d0, d4[2]"
+        -
+          asm_text: "vmul.i16 d8, d1, d7[3]"
+        -
+          asm_text: "vmul.i16 d7, d2, d1[1]"
+        -
+          asm_text: "vmul.i32 d6, d3, d2[0]"
+        -
+          asm_text: "vmul.i32 d5, d4, d3[1]"
+        -
+          asm_text: "vmul.i32 d4, d5, d4[0]"
+        -
+          asm_text: "vmul.f32 d3, d6, d5[1]"
+        -
+          asm_text: "vmul.i16 q9, q0, d4[2]"
+        -
+          asm_text: "vmul.i16 q8, q1, d7[3]"
+        -
+          asm_text: "vmul.i16 q7, q2, d1[1]"
+        -
+          asm_text: "vmul.i32 q6, q3, d2[0]"
+        -
+          asm_text: "vmul.i32 q5, q4, d3[1]"
+        -
+          asm_text: "vmul.i32 q4, q5, d4[0]"
+        -
+          asm_text: "vmul.f32 q3, q6, d5[1]"
diff --git a/tests/MC/ARM/neon-neg-encoding.s.yaml b/tests/MC/ARM/neon-neg-encoding.s.yaml
new file mode 100644
index 000000000..c80c07023
--- /dev/null
+++ b/tests/MC/ARM/neon-neg-encoding.s.yaml
@@ -0,0 +1,36 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xa0, 0x03, 0xf1, 0xf3, 0xa0, 0x03, 0xf5, 0xf3, 0xa0, 0x03, 0xf9, 0xf3, 0xa0, 0x07, 0xf9, 0xf3, 0xe0, 0x03, 0xf1, 0xf3, 0xe0, 0x03, 0xf5, 0xf3, 0xe0, 0x03, 0xf9, 0xf3, 0xe0, 0x07, 0xf9, 0xf3, 0xa0, 0x07, 0xf0, 0xf3, 0xa0, 0x07, 0xf4, 0xf3, 0xa0, 0x07, 0xf8, 0xf3, 0xe0, 0x07, 0xf0, 0xf3, 0xe0, 0x07, 0xf4, 0xf3, 0xe0, 0x07, 0xf8, 0xf3 ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ]
+    expected:
+      insns:
+        -
+          asm_text: "vneg.s8 d16, d16"
+        -
+          asm_text: "vneg.s16 d16, d16"
+        -
+          asm_text: "vneg.s32 d16, d16"
+        -
+          asm_text: "vneg.f32 d16, d16"
+        -
+          asm_text: "vneg.s8 q8, q8"
+        -
+          asm_text: "vneg.s16 q8, q8"
+        -
+          asm_text: "vneg.s32 q8, q8"
+        -
+          asm_text: "vneg.f32 q8, q8"
+        -
+          asm_text: "vqneg.s8 d16, d16"
+        -
+          asm_text: "vqneg.s16 d16, d16"
+        -
+          asm_text: "vqneg.s32 d16, d16"
+        -
+          asm_text: "vqneg.s8 q8, q8"
+        -
+          asm_text: "vqneg.s16 q8, q8"
+        -
+          asm_text: "vqneg.s32 q8, q8"
diff --git a/tests/MC/ARM/neon-pairwise-encoding.s.yaml b/tests/MC/ARM/neon-pairwise-encoding.s.yaml
new file mode 100644
index 000000000..771b39503
--- /dev/null
+++ b/tests/MC/ARM/neon-pairwise-encoding.s.yaml
@@ -0,0 +1,100 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xb0, 0x0b, 0x41, 0xf2, 0xb0, 0x0b, 0x51, 0xf2, 0xb0, 0x0b, 0x61, 0xf2, 0xa1, 0x0d, 0x40, 0xf3, 0xb0, 0x1b, 0x41, 0xf2, 0xb0, 0x1b, 0x51, 0xf2, 0xb0, 0x1b, 0x61, 0xf2, 0xa1, 0x0d, 0x40, 0xf3, 0x20, 0x02, 0xf0, 0xf3, 0x20, 0x02, 0xf4, 0xf3, 0x20, 0x02, 0xf8, 0xf3, 0xa0, 0x02, 0xf0, 0xf3, 0xa0, 0x02, 0xf4, 0xf3, 0xa0, 0x02, 0xf8, 0xf3, 0x60, 0x02, 0xf0, 0xf3, 0x60, 0x02, 0xf4, 0xf3, 0x60, 0x02, 0xf8, 0xf3, 0xe0, 0x02, 0xf0, 0xf3, 0xe0, 0x02, 0xf4, 0xf3, 0xe0, 0x02, 0xf8, 0xf3, 0x21, 0x06, 0xf0, 0xf3, 0x21, 0x06, 0xf4, 0xf3, 0x21, 0x06, 0xf8, 0xf3, 0xa1, 0x06, 0xf0, 0xf3, 0xa1, 0x06, 0xf4, 0xf3, 0xa1, 0x06, 0xf8, 0xf3, 0x60, 0x26, 0xf0, 0xf3, 0x60, 0x26, 0xf4, 0xf3, 0x60, 0x26, 0xf8, 0xf3, 0xe0, 0x26, 0xf0, 0xf3, 0xe0, 0x26, 0xf4, 0xf3, 0xe0, 0x26, 0xf8, 0xf3, 0xb1, 0x0a, 0x40, 0xf2, 0xb1, 0x0a, 0x50, 0xf2, 0xb1, 0x0a, 0x60, 0xf2, 0xb1, 0x0a, 0x40, 0xf3, 0xb1, 0x0a, 0x50, 0xf3, 0xb1, 0x0a, 0x60, 0xf3, 0xa1, 0x0f, 0x60, 0xf3, 0xa1, 0x0a, 0x40, 0xf2, 0xa1, 0x0a, 0x50, 0xf2, 0xa1, 0x0a, 0x60, 0xf2, 0xa1, 0x0a, 0x40, 0xf3, 0xa1, 0x0a, 0x50, 0xf3, 0xa1, 0x0a, 0x60, 0xf3, 0xa1, 0x0f, 0x40, 0xf3 ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpadd.i8 d16, d17, d16"
+        -
+          asm_text: "vpadd.i16 d16, d17, d16"
+        -
+          asm_text: "vpadd.i32 d16, d17, d16"
+        -
+          asm_text: "vpadd.f32 d16, d16, d17"
+        -
+          asm_text: "vpadd.i8 d17, d17, d16"
+        -
+          asm_text: "vpadd.i16 d17, d17, d16"
+        -
+          asm_text: "vpadd.i32 d17, d17, d16"
+        -
+          asm_text: "vpadd.f32 d16, d16, d17"
+        -
+          asm_text: "vpaddl.s8 d16, d16"
+        -
+          asm_text: "vpaddl.s16 d16, d16"
+        -
+          asm_text: "vpaddl.s32 d16, d16"
+        -
+          asm_text: "vpaddl.u8 d16, d16"
+        -
+          asm_text: "vpaddl.u16 d16, d16"
+        -
+          asm_text: "vpaddl.u32 d16, d16"
+        -
+          asm_text: "vpaddl.s8 q8, q8"
+        -
+          asm_text: "vpaddl.s16 q8, q8"
+        -
+          asm_text: "vpaddl.s32 q8, q8"
+        -
+          asm_text: "vpaddl.u8 q8, q8"
+        -
+          asm_text: "vpaddl.u16 q8, q8"
+        -
+          asm_text: "vpaddl.u32 q8, q8"
+        -
+          asm_text: "vpadal.s8 d16, d17"
+        -
+          asm_text: "vpadal.s16 d16, d17"
+        -
+          asm_text: "vpadal.s32 d16, d17"
+        -
+          asm_text: "vpadal.u8 d16, d17"
+        -
+          asm_text: "vpadal.u16 d16, d17"
+        -
+          asm_text: "vpadal.u32 d16, d17"
+        -
+          asm_text: "vpadal.s8 q9, q8"
+        -
+          asm_text: "vpadal.s16 q9, q8"
+        -
+          asm_text: "vpadal.s32 q9, q8"
+        -
+          asm_text: "vpadal.u8 q9, q8"
+        -
+          asm_text: "vpadal.u16 q9, q8"
+        -
+          asm_text: "vpadal.u32 q9, q8"
+        -
+          asm_text: "vpmin.s8 d16, d16, d17"
+        -
+          asm_text: "vpmin.s16 d16, d16, d17"
+        -
+          asm_text: "vpmin.s32 d16, d16, d17"
+        -
+          asm_text: "vpmin.u8 d16, d16, d17"
+        -
+          asm_text: "vpmin.u16 d16, d16, d17"
+        -
+          asm_text: "vpmin.u32 d16, d16, d17"
+        -
+          asm_text: "vpmin.f32 d16, d16, d17"
+        -
+          asm_text: "vpmax.s8 d16, d16, d17"
+        -
+          asm_text: "vpmax.s16 d16, d16, d17"
+        -
+          asm_text: "vpmax.s32 d16, d16, d17"
+        -
+          asm_text: "vpmax.u8 d16, d16, d17"
+        -
+          asm_text: "vpmax.u16 d16, d16, d17"
+        -
+          asm_text: "vpmax.u32 d16, d16, d17"
+        -
+          asm_text: "vpmax.f32 d16, d16, d17"
diff --git a/tests/MC/ARM/neon-reciprocal-encoding.s.yaml b/tests/MC/ARM/neon-reciprocal-encoding.s.yaml
new file mode 100644
index 000000000..d83492b66
--- /dev/null
+++ b/tests/MC/ARM/neon-reciprocal-encoding.s.yaml
@@ -0,0 +1,32 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x04, 0xfb, 0xf3, 0x60, 0x04, 0xfb, 0xf3, 0x20, 0x05, 0xfb, 0xf3, 0x60, 0x05, 0xfb, 0xf3, 0xb1, 0x0f, 0x40, 0xf2, 0xf2, 0x0f, 0x40, 0xf2, 0xa0, 0x04, 0xfb, 0xf3, 0xe0, 0x04, 0xfb, 0xf3, 0xa0, 0x05, 0xfb, 0xf3, 0xe0, 0x05, 0xfb, 0xf3, 0xb1, 0x0f, 0x60, 0xf2, 0xf2, 0x0f, 0x60, 0xf2 ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ]
+    expected:
+      insns:
+        -
+          asm_text: "vrecpe.u32 d16, d16"
+        -
+          asm_text: "vrecpe.u32 q8, q8"
+        -
+          asm_text: "vrecpe.f32 d16, d16"
+        -
+          asm_text: "vrecpe.f32 q8, q8"
+        -
+          asm_text: "vrecps.f32 d16, d16, d17"
+        -
+          asm_text: "vrecps.f32 q8, q8, q9"
+        -
+          asm_text: "vrsqrte.u32 d16, d16"
+        -
+          asm_text: "vrsqrte.u32 q8, q8"
+        -
+          asm_text: "vrsqrte.f32 d16, d16"
+        -
+          asm_text: "vrsqrte.f32 q8, q8"
+        -
+          asm_text: "vrsqrts.f32 d16, d16, d17"
+        -
+          asm_text: "vrsqrts.f32 q8, q8, q9"
diff --git a/tests/MC/ARM/neon-reverse-encoding.s.yaml b/tests/MC/ARM/neon-reverse-encoding.s.yaml
new file mode 100644
index 000000000..4493caae3
--- /dev/null
+++ b/tests/MC/ARM/neon-reverse-encoding.s.yaml
@@ -0,0 +1,32 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x00, 0xf0, 0xf3, 0x20, 0x00, 0xf4, 0xf3, 0x20, 0x00, 0xf8, 0xf3, 0x60, 0x00, 0xf0, 0xf3, 0x60, 0x00, 0xf4, 0xf3, 0x60, 0x00, 0xf8, 0xf3, 0xa0, 0x00, 0xf0, 0xf3, 0xa0, 0x00, 0xf4, 0xf3, 0xe0, 0x00, 0xf0, 0xf3, 0xe0, 0x00, 0xf4, 0xf3, 0x20, 0x01, 0xf0, 0xf3, 0x60, 0x01, 0xf0, 0xf3 ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ]
+    expected:
+      insns:
+        -
+          asm_text: "vrev64.8 d16, d16"
+        -
+          asm_text: "vrev64.16 d16, d16"
+        -
+          asm_text: "vrev64.32 d16, d16"
+        -
+          asm_text: "vrev64.8 q8, q8"
+        -
+          asm_text: "vrev64.16 q8, q8"
+        -
+          asm_text: "vrev64.32 q8, q8"
+        -
+          asm_text: "vrev32.8 d16, d16"
+        -
+          asm_text: "vrev32.16 d16, d16"
+        -
+          asm_text: "vrev32.8 q8, q8"
+        -
+          asm_text: "vrev32.16 q8, q8"
+        -
+          asm_text: "vrev16.8 d16, d16"
+        -
+          asm_text: "vrev16.8 q8, q8"
diff --git a/tests/MC/ARM/neon-satshift-encoding.s.yaml b/tests/MC/ARM/neon-satshift-encoding.s.yaml
new file mode 100644
index 000000000..36148b71e
--- /dev/null
+++ b/tests/MC/ARM/neon-satshift-encoding.s.yaml
@@ -0,0 +1,156 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xb0, 0x04, 0x41, 0xf2, 0xb0, 0x04, 0x51, 0xf2, 0xb0, 0x04, 0x61, 0xf2, 0xb0, 0x04, 0x71, 0xf2, 0xb0, 0x04, 0x41, 0xf3, 0xb0, 0x04, 0x51, 0xf3, 0xb0, 0x04, 0x61, 0xf3, 0xb0, 0x04, 0x71, 0xf3, 0xf0, 0x04, 0x42, 0xf2, 0xf0, 0x04, 0x52, 0xf2, 0xf0, 0x04, 0x62, 0xf2, 0xf0, 0x04, 0x72, 0xf2, 0xf0, 0x04, 0x42, 0xf3, 0xf0, 0x04, 0x52, 0xf3, 0xf0, 0x04, 0x62, 0xf3, 0xf0, 0x04, 0x72, 0xf3, 0x30, 0x07, 0xcf, 0xf2, 0x30, 0x07, 0xdf, 0xf2, 0x30, 0x07, 0xff, 0xf2, 0xb0, 0x07, 0xff, 0xf2, 0x30, 0x07, 0xcf, 0xf3, 0x30, 0x07, 0xdf, 0xf3, 0x30, 0x07, 0xff, 0xf3, 0xb0, 0x07, 0xff, 0xf3, 0x30, 0x06, 0xcf, 0xf3, 0x30, 0x06, 0xdf, 0xf3, 0x30, 0x06, 0xff, 0xf3, 0xb0, 0x06, 0xff, 0xf3, 0x70, 0x07, 0xcf, 0xf2, 0x70, 0x07, 0xdf, 0xf2, 0x70, 0x07, 0xff, 0xf2, 0xf0, 0x07, 0xff, 0xf2, 0x70, 0x07, 0xcf, 0xf3, 0x70, 0x07, 0xdf, 0xf3, 0x70, 0x07, 0xff, 0xf3, 0xf0, 0x07, 0xff, 0xf3, 0x70, 0x06, 0xcf, 0xf3, 0x70, 0x06, 0xdf, 0xf3, 0x70, 0x06, 0xff, 0xf3, 0xf0, 0x06, 0xff, 0xf3, 0xb0, 0x05, 0x41, 0xf2, 0xb0, 0x05, 0x51, 0xf2, 0xb0, 0x05, 0x61, 0xf2, 0xb0, 0x05, 0x71, 0xf2, 0xb0, 0x05, 0x41, 0xf3, 0xb0, 0x05, 0x51, 0xf3, 0xb0, 0x05, 0x61, 0xf3, 0xb0, 0x05, 0x71, 0xf3, 0xf0, 0x05, 0x42, 0xf2, 0xf0, 0x05, 0x52, 0xf2, 0xf0, 0x05, 0x62, 0xf2, 0xf0, 0x05, 0x72, 0xf2, 0xf0, 0x05, 0x42, 0xf3, 0xf0, 0x05, 0x52, 0xf3, 0xf0, 0x05, 0x62, 0xf3, 0xf0, 0x05, 0x72, 0xf3, 0x30, 0x09, 0xc8, 0xf2, 0x30, 0x09, 0xd0, 0xf2, 0x30, 0x09, 0xe0, 0xf2, 0x30, 0x09, 0xc8, 0xf3, 0x30, 0x09, 0xd0, 0xf3, 0x30, 0x09, 0xe0, 0xf3, 0x30, 0x08, 0xc8, 0xf3, 0x30, 0x08, 0xd0, 0xf3, 0x30, 0x08, 0xe0, 0xf3, 0x70, 0x09, 0xc8, 0xf2, 0x70, 0x09, 0xd0, 0xf2, 0x70, 0x09, 0xe0, 0xf2, 0x70, 0x09, 0xc8, 0xf3, 0x70, 0x09, 0xd0, 0xf3, 0x70, 0x09, 0xe0, 0xf3, 0x70, 0x08, 0xc8, 0xf3, 0x70, 0x08, 0xd0, 0xf3, 0x70, 0x08, 0xe0, 0xf3 ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ]
+    expected:
+      insns:
+        -
+          asm_text: "vqshl.s8 d16, d16, d17"
+        -
+          asm_text: "vqshl.s16 d16, d16, d17"
+        -
+          asm_text: "vqshl.s32 d16, d16, d17"
+        -
+          asm_text: "vqshl.s64 d16, d16, d17"
+        -
+          asm_text: "vqshl.u8 d16, d16, d17"
+        -
+          asm_text: "vqshl.u16 d16, d16, d17"
+        -
+          asm_text: "vqshl.u32 d16, d16, d17"
+        -
+          asm_text: "vqshl.u64 d16, d16, d17"
+        -
+          asm_text: "vqshl.s8 q8, q8, q9"
+        -
+          asm_text: "vqshl.s16 q8, q8, q9"
+        -
+          asm_text: "vqshl.s32 q8, q8, q9"
+        -
+          asm_text: "vqshl.s64 q8, q8, q9"
+        -
+          asm_text: "vqshl.u8 q8, q8, q9"
+        -
+          asm_text: "vqshl.u16 q8, q8, q9"
+        -
+          asm_text: "vqshl.u32 q8, q8, q9"
+        -
+          asm_text: "vqshl.u64 q8, q8, q9"
+        -
+          asm_text: "vqshl.s8 d16, d16, #7"
+        -
+          asm_text: "vqshl.s16 d16, d16, #0xf"
+        -
+          asm_text: "vqshl.s32 d16, d16, #0x1f"
+        -
+          asm_text: "vqshl.s64 d16, d16, #0x3f"
+        -
+          asm_text: "vqshl.u8 d16, d16, #7"
+        -
+          asm_text: "vqshl.u16 d16, d16, #0xf"
+        -
+          asm_text: "vqshl.u32 d16, d16, #0x1f"
+        -
+          asm_text: "vqshl.u64 d16, d16, #0x3f"
+        -
+          asm_text: "vqshlu.s8 d16, d16, #7"
+        -
+          asm_text: "vqshlu.s16 d16, d16, #0xf"
+        -
+          asm_text: "vqshlu.s32 d16, d16, #0x1f"
+        -
+          asm_text: "vqshlu.s64 d16, d16, #0x3f"
+        -
+          asm_text: "vqshl.s8 q8, q8, #7"
+        -
+          asm_text: "vqshl.s16 q8, q8, #0xf"
+        -
+          asm_text: "vqshl.s32 q8, q8, #0x1f"
+        -
+          asm_text: "vqshl.s64 q8, q8, #0x3f"
+        -
+          asm_text: "vqshl.u8 q8, q8, #7"
+        -
+          asm_text: "vqshl.u16 q8, q8, #0xf"
+        -
+          asm_text: "vqshl.u32 q8, q8, #0x1f"
+        -
+          asm_text: "vqshl.u64 q8, q8, #0x3f"
+        -
+          asm_text: "vqshlu.s8 q8, q8, #7"
+        -
+          asm_text: "vqshlu.s16 q8, q8, #0xf"
+        -
+          asm_text: "vqshlu.s32 q8, q8, #0x1f"
+        -
+          asm_text: "vqshlu.s64 q8, q8, #0x3f"
+        -
+          asm_text: "vqrshl.s8 d16, d16, d17"
+        -
+          asm_text: "vqrshl.s16 d16, d16, d17"
+        -
+          asm_text: "vqrshl.s32 d16, d16, d17"
+        -
+          asm_text: "vqrshl.s64 d16, d16, d17"
+        -
+          asm_text: "vqrshl.u8 d16, d16, d17"
+        -
+          asm_text: "vqrshl.u16 d16, d16, d17"
+        -
+          asm_text: "vqrshl.u32 d16, d16, d17"
+        -
+          asm_text: "vqrshl.u64 d16, d16, d17"
+        -
+          asm_text: "vqrshl.s8 q8, q8, q9"
+        -
+          asm_text: "vqrshl.s16 q8, q8, q9"
+        -
+          asm_text: "vqrshl.s32 q8, q8, q9"
+        -
+          asm_text: "vqrshl.s64 q8, q8, q9"
+        -
+          asm_text: "vqrshl.u8 q8, q8, q9"
+        -
+          asm_text: "vqrshl.u16 q8, q8, q9"
+        -
+          asm_text: "vqrshl.u32 q8, q8, q9"
+        -
+          asm_text: "vqrshl.u64 q8, q8, q9"
+        -
+          asm_text: "vqshrn.s16 d16, q8, #8"
+        -
+          asm_text: "vqshrn.s32 d16, q8, #0x10"
+        -
+          asm_text: "vqshrn.s64 d16, q8, #0x20"
+        -
+          asm_text: "vqshrn.u16 d16, q8, #8"
+        -
+          asm_text: "vqshrn.u32 d16, q8, #0x10"
+        -
+          asm_text: "vqshrn.u64 d16, q8, #0x20"
+        -
+          asm_text: "vqshrun.s16 d16, q8, #8"
+        -
+          asm_text: "vqshrun.s32 d16, q8, #0x10"
+        -
+          asm_text: "vqshrun.s64 d16, q8, #0x20"
+        -
+          asm_text: "vqrshrn.s16 d16, q8, #8"
+        -
+          asm_text: "vqrshrn.s32 d16, q8, #0x10"
+        -
+          asm_text: "vqrshrn.s64 d16, q8, #0x20"
+        -
+          asm_text: "vqrshrn.u16 d16, q8, #8"
+        -
+          asm_text: "vqrshrn.u32 d16, q8, #0x10"
+        -
+          asm_text: "vqrshrn.u64 d16, q8, #0x20"
+        -
+          asm_text: "vqrshrun.s16 d16, q8, #8"
+        -
+          asm_text: "vqrshrun.s32 d16, q8, #0x10"
+        -
+          asm_text: "vqrshrun.s64 d16, q8, #0x20"
diff --git a/tests/MC/ARM/neon-shift-encoding.s.yaml b/tests/MC/ARM/neon-shift-encoding.s.yaml
new file mode 100644
index 000000000..4296dbd95
--- /dev/null
+++ b/tests/MC/ARM/neon-shift-encoding.s.yaml
@@ -0,0 +1,482 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xa1, 0x04, 0x40, 0xf3, 0xa1, 0x04, 0x50, 0xf3, 0xa1, 0x04, 0x60, 0xf3, 0xa1, 0x04, 0x70, 0xf3, 0x30, 0x05, 0xcf, 0xf2, 0x30, 0x05, 0xdf, 0xf2, 0x30, 0x05, 0xff, 0xf2, 0xb0, 0x05, 0xff, 0xf2, 0xe2, 0x04, 0x40, 0xf3, 0xe2, 0x04, 0x50, 0xf3, 0xe2, 0x04, 0x60, 0xf3, 0xe2, 0x04, 0x70, 0xf3, 0x70, 0x05, 0xcf, 0xf2, 0x70, 0x05, 0xdf, 0xf2, 0x70, 0x05, 0xff, 0xf2, 0xf0, 0x05, 0xff, 0xf2, 0x30, 0x00, 0xc9, 0xf3, 0x30, 0x00, 0xd1, 0xf3, 0x30, 0x00, 0xe1, 0xf3, 0xb0, 0x00, 0xc1, 0xf3, 0x70, 0x00, 0xc9, 0xf3, 0x70, 0x00, 0xd1, 0xf3, 0x70, 0x00, 0xe1, 0xf3, 0xf0, 0x00, 0xc1, 0xf3, 0x30, 0x00, 0xc9, 0xf2, 0x30, 0x00, 0xd1, 0xf2, 0x30, 0x00, 0xe1, 0xf2, 0xb0, 0x00, 0xc1, 0xf2, 0x70, 0x00, 0xc9, 0xf2, 0x70, 0x00, 0xd1, 0xf2, 0x70, 0x00, 0xe1, 0xf2, 0xf0, 0x00, 0xc1, 0xf2, 0x30, 0x00, 0xc9, 0xf3, 0x30, 0x00, 0xd1, 0xf3, 0x30, 0x00, 0xe1, 0xf3, 0xb0, 0x00, 0xc1, 0xf3, 0x70, 0x00, 0xc9, 0xf3, 0x70, 0x00, 0xd1, 0xf3, 0x70, 0x00, 0xe1, 0xf3, 0xf0, 0x00, 0xc1, 0xf3, 0x30, 0x00, 0xc9, 0xf2, 0x30, 0x00, 0xd1, 0xf2, 0x30, 0x00, 0xe1, 0xf2, 0xb0, 0x00, 0xc1, 0xf2, 0x70, 0x00, 0xc9, 0xf2, 0x70, 0x00, 0xd1, 0xf2, 0x70, 0x00, 0xe1, 0xf2, 0xf0, 0x00, 0xc1, 0xf2, 0x16, 0x01, 0xc9, 0xf2, 0x32, 0xa1, 0xd1, 0xf2, 0x1a, 0xb1, 0xa1, 0xf2, 0xb3, 0xc1, 0x81, 0xf2, 0x70, 0x21, 0x89, 0xf2, 0x5e, 0x41, 0x91, 0xf2, 0x5c, 0x61, 0xa1, 0xf2, 0xda, 0x81, 0x81, 0xf2, 0x30, 0x01, 0xc9, 0xf2, 0x1f, 0xf1, 0x91, 0xf2, 0x1e, 0xe1, 0xa1, 0xf2, 0x9d, 0xd1, 0x81, 0xf2, 0x58, 0x81, 0x89, 0xf2, 0x5a, 0xa1, 0x91, 0xf2, 0x5c, 0xc1, 0xa1, 0xf2, 0xde, 0xe1, 0x81, 0xf2, 0x16, 0x01, 0xc9, 0xf3, 0x32, 0xa1, 0xd1, 0xf3, 0x1a, 0xb1, 0xa1, 0xf3, 0xb3, 0xc1, 0x81, 0xf3, 0x70, 0x21, 0x89, 0xf3, 0x5e, 0x41, 0x91, 0xf3, 0x5c, 0x61, 0xa1, 0xf3, 0xda, 0x81, 0x81, 0xf3, 0x30, 0x01, 0xc9, 0xf3, 0x1f, 0xf1, 0x91, 0xf3, 0x1e, 0xe1, 0xa1, 0xf3, 0x9d, 0xd1, 0x81, 0xf3, 0x58, 0x81, 0x89, 0xf3, 0x5a, 0xa1, 0x91, 0xf3, 0x5c, 0xc1, 0xa1, 0xf3, 0xde, 0xe1, 0x81, 0xf3, 0x16, 0x04, 0xc9, 0xf3, 0x32, 0xa4, 0xd1, 0xf3, 0x1a, 0xb4, 0xa1, 0xf3, 0xb3, 0xc4, 0x81, 0xf3, 0x70, 0x24, 0x89, 0xf3, 0x5e, 0x44, 0x91, 0xf3, 0x5c, 0x64, 0xa1, 0xf3, 0xda, 0x84, 0x81, 0xf3, 0x30, 0x04, 0xc9, 0xf3, 0x1f, 0xf4, 0x91, 0xf3, 0x1e, 0xe4, 0xa1, 0xf3, 0x9d, 0xd4, 0x81, 0xf3, 0x58, 0x84, 0x89, 0xf3, 0x5a, 0xa4, 0x91, 0xf3, 0x5c, 0xc4, 0xa1, 0xf3, 0xde, 0xe4, 0x81, 0xf3, 0x16, 0x05, 0xcf, 0xf3, 0x32, 0xa5, 0xdf, 0xf3, 0x1a, 0xb5, 0xbf, 0xf3, 0xb3, 0xc5, 0xbf, 0xf3, 0x70, 0x25, 0x8f, 0xf3, 0x5e, 0x45, 0x9f, 0xf3, 0x5c, 0x65, 0xbf, 0xf3, 0xda, 0x85, 0xbf, 0xf3, 0x30, 0x05, 0xcf, 0xf3, 0x1f, 0xf5, 0x9f, 0xf3, 0x1e, 0xe5, 0xbf, 0xf3, 0x9d, 0xd5, 0xbf, 0xf3, 0x58, 0x85, 0x8f, 0xf3, 0x5a, 0xa5, 0x9f, 0xf3, 0x5c, 0xc5, 0xbf, 0xf3, 0xde, 0xe5, 0xbf, 0xf3, 0x30, 0x0a, 0xcf, 0xf2, 0x30, 0x0a, 0xdf, 0xf2, 0x30, 0x0a, 0xff, 0xf2, 0x30, 0x0a, 0xcf, 0xf3, 0x30, 0x0a, 0xdf, 0xf3, 0x30, 0x0a, 0xff, 0xf3, 0x20, 0x03, 0xf2, 0xf3, 0x20, 0x03, 0xf6, 0xf3, 0x20, 0x03, 0xfa, 0xf3, 0x30, 0x08, 0xc8, 0xf2, 0x30, 0x08, 0xd0, 0xf2, 0x30, 0x08, 0xe0, 0xf2, 0xa1, 0x05, 0x40, 0xf2, 0xa1, 0x05, 0x50, 0xf2, 0xa1, 0x05, 0x60, 0xf2, 0xa1, 0x05, 0x70, 0xf2, 0xa1, 0x05, 0x40, 0xf3, 0xa1, 0x05, 0x50, 0xf3, 0xa1, 0x05, 0x60, 0xf3, 0xa1, 0x05, 0x70, 0xf3, 0xe2, 0x05, 0x40, 0xf2, 0xe2, 0x05, 0x50, 0xf2, 0xe2, 0x05, 0x60, 0xf2, 0xe2, 0x05, 0x70, 0xf2, 0xe2, 0x05, 0x40, 0xf3, 0xe2, 0x05, 0x50, 0xf3, 0xe2, 0x05, 0x60, 0xf3, 0xe2, 0x05, 0x70, 0xf3, 0x30, 0x02, 0xc8, 0xf2, 0x30, 0x02, 0xd0, 0xf2, 0x30, 0x02, 0xe0, 0xf2, 0xb0, 0x02, 0xc0, 0xf2, 0x30, 0x02, 0xc8, 0xf3, 0x30, 0x02, 0xd0, 0xf3, 0x30, 0x02, 0xe0, 0xf3, 0xb0, 0x02, 0xc0, 0xf3, 0x70, 0x02, 0xc8, 0xf2, 0x70, 0x02, 0xd0, 0xf2, 0x70, 0x02, 0xe0, 0xf2, 0xf0, 0x02, 0xc0, 0xf2, 0x70, 0x02, 0xc8, 0xf3, 0x70, 0x02, 0xd0, 0xf3, 0x70, 0x02, 0xe0, 0xf3, 0xf0, 0x02, 0xc0, 0xf3, 0x70, 0x08, 0xc8, 0xf2, 0x70, 0x08, 0xd0, 0xf2, 0x70, 0x08, 0xe0, 0xf2, 0x70, 0x09, 0xcc, 0xf2, 0x70, 0x09, 0xd3, 0xf2, 0x70, 0x09, 0xf3, 0xf2, 0x70, 0x09, 0xcc, 0xf3, 0x70, 0x09, 0xd3, 0xf3, 0x70, 0x09, 0xf3, 0xf3, 0x48, 0x84, 0x0a, 0xf2, 0x48, 0x84, 0x1a, 0xf2, 0x48, 0x84, 0x2a, 0xf2, 0x48, 0x84, 0x3a, 0xf2, 0x48, 0x84, 0x0a, 0xf3, 0x48, 0x84, 0x1a, 0xf3, 0x48, 0x84, 0x2a, 0xf3, 0x48, 0x84, 0x3a, 0xf3, 0x04, 0x44, 0x05, 0xf2, 0x04, 0x44, 0x15, 0xf2, 0x04, 0x44, 0x25, 0xf2, 0x04, 0x44, 0x35, 0xf2, 0x04, 0x44, 0x05, 0xf3, 0x04, 0x44, 0x15, 0xf3, 0x04, 0x44, 0x25, 0xf3, 0x04, 0x44, 0x35, 0xf3, 0x58, 0x85, 0x8a, 0xf2, 0x58, 0x85, 0x9e, 0xf2, 0x58, 0x85, 0xbb, 0xf2, 0xd8, 0x85, 0xa3, 0xf2, 0x14, 0x45, 0x8e, 0xf2, 0x14, 0x45, 0x9a, 0xf2, 0x14, 0x45, 0xb1, 0xf2, 0x94, 0x45, 0xab, 0xf2, 0x0b, 0xb5, 0x04, 0xf2, 0x0c, 0xc5, 0x15, 0xf2, 0x0d, 0xd5, 0x26, 0xf2, 0x0e, 0xe5, 0x37, 0xf2, 0x0f, 0xf5, 0x08, 0xf3, 0x20, 0x05, 0x59, 0xf3, 0x21, 0x15, 0x6a, 0xf3, 0x22, 0x25, 0x7b, 0xf3, 0xc2, 0x25, 0x00, 0xf2, 0xc4, 0x45, 0x1e, 0xf2, 0xc6, 0x65, 0x2c, 0xf2, 0xc8, 0x85, 0x3a, 0xf2, 0xca, 0xa5, 0x08, 0xf3, 0xcc, 0xc5, 0x16, 0xf3, 0xce, 0xe5, 0x24, 0xf3, 0xe0, 0x05, 0x72, 0xf3, 0x1f, 0xf0, 0x88, 0xf2, 0x1c, 0xc0, 0x90, 0xf2, 0x1d, 0xd0, 0xa0, 0xf2, 0x9e, 0xe0, 0x80, 0xf2, 0x30, 0x00, 0xc8, 0xf3, 0x31, 0x10, 0xd0, 0xf3, 0x16, 0x60, 0xa0, 0xf3, 0x9a, 0xa0, 0x80, 0xf3, 0x52, 0x20, 0x88, 0xf2, 0x54, 0x40, 0x90, 0xf2, 0x56, 0x60, 0xa0, 0xf2, 0xd8, 0x80, 0x80, 0xf2, 0x5a, 0xa0, 0x88, 0xf3, 0x5c, 0xc0, 0x90, 0xf3, 0x5e, 0xe0, 0xa0, 0xf3, 0xf0, 0x00, 0xc0, 0xf3, 0x1f, 0xf2, 0x88, 0xf2, 0x1c, 0xc2, 0x90, 0xf2, 0x1d, 0xd2, 0xa0, 0xf2, 0x9e, 0xe2, 0x80, 0xf2, 0x30, 0x02, 0xc8, 0xf3, 0x31, 0x12, 0xd0, 0xf3, 0x16, 0x62, 0xa0, 0xf3, 0x9a, 0xa2, 0x80, 0xf3, 0x52, 0x22, 0x88, 0xf2, 0x54, 0x42, 0x90, 0xf2, 0x56, 0x62, 0xa0, 0xf2, 0xd8, 0x82, 0x80, 0xf2, 0x5a, 0xa2, 0x88, 0xf3, 0x5c, 0xc2, 0x90, 0xf3, 0x5e, 0xe2, 0xa0, 0xf3, 0xf0, 0x02, 0xc0, 0xf3 ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ]
+    expected:
+      insns:
+        -
+          asm_text: "vshl.u8 d16, d17, d16"
+        -
+          asm_text: "vshl.u16 d16, d17, d16"
+        -
+          asm_text: "vshl.u32 d16, d17, d16"
+        -
+          asm_text: "vshl.u64 d16, d17, d16"
+        -
+          asm_text: "vshl.i8 d16, d16, #7"
+        -
+          asm_text: "vshl.i16 d16, d16, #0xf"
+        -
+          asm_text: "vshl.i32 d16, d16, #0x1f"
+        -
+          asm_text: "vshl.i64 d16, d16, #0x3f"
+        -
+          asm_text: "vshl.u8 q8, q9, q8"
+        -
+          asm_text: "vshl.u16 q8, q9, q8"
+        -
+          asm_text: "vshl.u32 q8, q9, q8"
+        -
+          asm_text: "vshl.u64 q8, q9, q8"
+        -
+          asm_text: "vshl.i8 q8, q8, #7"
+        -
+          asm_text: "vshl.i16 q8, q8, #0xf"
+        -
+          asm_text: "vshl.i32 q8, q8, #0x1f"
+        -
+          asm_text: "vshl.i64 q8, q8, #0x3f"
+        -
+          asm_text: "vshr.u8 d16, d16, #7"
+        -
+          asm_text: "vshr.u16 d16, d16, #0xf"
+        -
+          asm_text: "vshr.u32 d16, d16, #0x1f"
+        -
+          asm_text: "vshr.u64 d16, d16, #0x3f"
+        -
+          asm_text: "vshr.u8 q8, q8, #7"
+        -
+          asm_text: "vshr.u16 q8, q8, #0xf"
+        -
+          asm_text: "vshr.u32 q8, q8, #0x1f"
+        -
+          asm_text: "vshr.u64 q8, q8, #0x3f"
+        -
+          asm_text: "vshr.s8 d16, d16, #7"
+        -
+          asm_text: "vshr.s16 d16, d16, #0xf"
+        -
+          asm_text: "vshr.s32 d16, d16, #0x1f"
+        -
+          asm_text: "vshr.s64 d16, d16, #0x3f"
+        -
+          asm_text: "vshr.s8 q8, q8, #7"
+        -
+          asm_text: "vshr.s16 q8, q8, #0xf"
+        -
+          asm_text: "vshr.s32 q8, q8, #0x1f"
+        -
+          asm_text: "vshr.s64 q8, q8, #0x3f"
+        -
+          asm_text: "vshr.u8 d16, d16, #7"
+        -
+          asm_text: "vshr.u16 d16, d16, #0xf"
+        -
+          asm_text: "vshr.u32 d16, d16, #0x1f"
+        -
+          asm_text: "vshr.u64 d16, d16, #0x3f"
+        -
+          asm_text: "vshr.u8 q8, q8, #7"
+        -
+          asm_text: "vshr.u16 q8, q8, #0xf"
+        -
+          asm_text: "vshr.u32 q8, q8, #0x1f"
+        -
+          asm_text: "vshr.u64 q8, q8, #0x3f"
+        -
+          asm_text: "vshr.s8 d16, d16, #7"
+        -
+          asm_text: "vshr.s16 d16, d16, #0xf"
+        -
+          asm_text: "vshr.s32 d16, d16, #0x1f"
+        -
+          asm_text: "vshr.s64 d16, d16, #0x3f"
+        -
+          asm_text: "vshr.s8 q8, q8, #7"
+        -
+          asm_text: "vshr.s16 q8, q8, #0xf"
+        -
+          asm_text: "vshr.s32 q8, q8, #0x1f"
+        -
+          asm_text: "vshr.s64 q8, q8, #0x3f"
+        -
+          asm_text: "vsra.s8 d16, d6, #7"
+        -
+          asm_text: "vsra.s16 d26, d18, #0xf"
+        -
+          asm_text: "vsra.s32 d11, d10, #0x1f"
+        -
+          asm_text: "vsra.s64 d12, d19, #0x3f"
+        -
+          asm_text: "vsra.s8 q1, q8, #7"
+        -
+          asm_text: "vsra.s16 q2, q7, #0xf"
+        -
+          asm_text: "vsra.s32 q3, q6, #0x1f"
+        -
+          asm_text: "vsra.s64 q4, q5, #0x3f"
+        -
+          asm_text: "vsra.s8 d16, d16, #7"
+        -
+          asm_text: "vsra.s16 d15, d15, #0xf"
+        -
+          asm_text: "vsra.s32 d14, d14, #0x1f"
+        -
+          asm_text: "vsra.s64 d13, d13, #0x3f"
+        -
+          asm_text: "vsra.s8 q4, q4, #7"
+        -
+          asm_text: "vsra.s16 q5, q5, #0xf"
+        -
+          asm_text: "vsra.s32 q6, q6, #0x1f"
+        -
+          asm_text: "vsra.s64 q7, q7, #0x3f"
+        -
+          asm_text: "vsra.u8 d16, d6, #7"
+        -
+          asm_text: "vsra.u16 d26, d18, #0xf"
+        -
+          asm_text: "vsra.u32 d11, d10, #0x1f"
+        -
+          asm_text: "vsra.u64 d12, d19, #0x3f"
+        -
+          asm_text: "vsra.u8 q1, q8, #7"
+        -
+          asm_text: "vsra.u16 q2, q7, #0xf"
+        -
+          asm_text: "vsra.u32 q3, q6, #0x1f"
+        -
+          asm_text: "vsra.u64 q4, q5, #0x3f"
+        -
+          asm_text: "vsra.u8 d16, d16, #7"
+        -
+          asm_text: "vsra.u16 d15, d15, #0xf"
+        -
+          asm_text: "vsra.u32 d14, d14, #0x1f"
+        -
+          asm_text: "vsra.u64 d13, d13, #0x3f"
+        -
+          asm_text: "vsra.u8 q4, q4, #7"
+        -
+          asm_text: "vsra.u16 q5, q5, #0xf"
+        -
+          asm_text: "vsra.u32 q6, q6, #0x1f"
+        -
+          asm_text: "vsra.u64 q7, q7, #0x3f"
+        -
+          asm_text: "vsri.8 d16, d6, #7"
+        -
+          asm_text: "vsri.16 d26, d18, #0xf"
+        -
+          asm_text: "vsri.32 d11, d10, #0x1f"
+        -
+          asm_text: "vsri.64 d12, d19, #0x3f"
+        -
+          asm_text: "vsri.8 q1, q8, #7"
+        -
+          asm_text: "vsri.16 q2, q7, #0xf"
+        -
+          asm_text: "vsri.32 q3, q6, #0x1f"
+        -
+          asm_text: "vsri.64 q4, q5, #0x3f"
+        -
+          asm_text: "vsri.8 d16, d16, #7"
+        -
+          asm_text: "vsri.16 d15, d15, #0xf"
+        -
+          asm_text: "vsri.32 d14, d14, #0x1f"
+        -
+          asm_text: "vsri.64 d13, d13, #0x3f"
+        -
+          asm_text: "vsri.8 q4, q4, #7"
+        -
+          asm_text: "vsri.16 q5, q5, #0xf"
+        -
+          asm_text: "vsri.32 q6, q6, #0x1f"
+        -
+          asm_text: "vsri.64 q7, q7, #0x3f"
+        -
+          asm_text: "vsli.8 d16, d6, #7"
+        -
+          asm_text: "vsli.16 d26, d18, #0xf"
+        -
+          asm_text: "vsli.32 d11, d10, #0x1f"
+        -
+          asm_text: "vsli.64 d12, d19, #0x3f"
+        -
+          asm_text: "vsli.8 q1, q8, #7"
+        -
+          asm_text: "vsli.16 q2, q7, #0xf"
+        -
+          asm_text: "vsli.32 q3, q6, #0x1f"
+        -
+          asm_text: "vsli.64 q4, q5, #0x3f"
+        -
+          asm_text: "vsli.8 d16, d16, #7"
+        -
+          asm_text: "vsli.16 d15, d15, #0xf"
+        -
+          asm_text: "vsli.32 d14, d14, #0x1f"
+        -
+          asm_text: "vsli.64 d13, d13, #0x3f"
+        -
+          asm_text: "vsli.8 q4, q4, #7"
+        -
+          asm_text: "vsli.16 q5, q5, #0xf"
+        -
+          asm_text: "vsli.32 q6, q6, #0x1f"
+        -
+          asm_text: "vsli.64 q7, q7, #0x3f"
+        -
+          asm_text: "vshll.s8 q8, d16, #7"
+        -
+          asm_text: "vshll.s16 q8, d16, #0xf"
+        -
+          asm_text: "vshll.s32 q8, d16, #0x1f"
+        -
+          asm_text: "vshll.u8 q8, d16, #7"
+        -
+          asm_text: "vshll.u16 q8, d16, #0xf"
+        -
+          asm_text: "vshll.u32 q8, d16, #0x1f"
+        -
+          asm_text: "vshll.i8 q8, d16, #8"
+        -
+          asm_text: "vshll.i16 q8, d16, #0x10"
+        -
+          asm_text: "vshll.i32 q8, d16, #0x20"
+        -
+          asm_text: "vshrn.i16 d16, q8, #8"
+        -
+          asm_text: "vshrn.i32 d16, q8, #0x10"
+        -
+          asm_text: "vshrn.i64 d16, q8, #0x20"
+        -
+          asm_text: "vrshl.s8 d16, d17, d16"
+        -
+          asm_text: "vrshl.s16 d16, d17, d16"
+        -
+          asm_text: "vrshl.s32 d16, d17, d16"
+        -
+          asm_text: "vrshl.s64 d16, d17, d16"
+        -
+          asm_text: "vrshl.u8 d16, d17, d16"
+        -
+          asm_text: "vrshl.u16 d16, d17, d16"
+        -
+          asm_text: "vrshl.u32 d16, d17, d16"
+        -
+          asm_text: "vrshl.u64 d16, d17, d16"
+        -
+          asm_text: "vrshl.s8 q8, q9, q8"
+        -
+          asm_text: "vrshl.s16 q8, q9, q8"
+        -
+          asm_text: "vrshl.s32 q8, q9, q8"
+        -
+          asm_text: "vrshl.s64 q8, q9, q8"
+        -
+          asm_text: "vrshl.u8 q8, q9, q8"
+        -
+          asm_text: "vrshl.u16 q8, q9, q8"
+        -
+          asm_text: "vrshl.u32 q8, q9, q8"
+        -
+          asm_text: "vrshl.u64 q8, q9, q8"
+        -
+          asm_text: "vrshr.s8 d16, d16, #8"
+        -
+          asm_text: "vrshr.s16 d16, d16, #0x10"
+        -
+          asm_text: "vrshr.s32 d16, d16, #0x20"
+        -
+          asm_text: "vrshr.s64 d16, d16, #0x40"
+        -
+          asm_text: "vrshr.u8 d16, d16, #8"
+        -
+          asm_text: "vrshr.u16 d16, d16, #0x10"
+        -
+          asm_text: "vrshr.u32 d16, d16, #0x20"
+        -
+          asm_text: "vrshr.u64 d16, d16, #0x40"
+        -
+          asm_text: "vrshr.s8 q8, q8, #8"
+        -
+          asm_text: "vrshr.s16 q8, q8, #0x10"
+        -
+          asm_text: "vrshr.s32 q8, q8, #0x20"
+        -
+          asm_text: "vrshr.s64 q8, q8, #0x40"
+        -
+          asm_text: "vrshr.u8 q8, q8, #8"
+        -
+          asm_text: "vrshr.u16 q8, q8, #0x10"
+        -
+          asm_text: "vrshr.u32 q8, q8, #0x20"
+        -
+          asm_text: "vrshr.u64 q8, q8, #0x40"
+        -
+          asm_text: "vrshrn.i16 d16, q8, #8"
+        -
+          asm_text: "vrshrn.i32 d16, q8, #0x10"
+        -
+          asm_text: "vrshrn.i64 d16, q8, #0x20"
+        -
+          asm_text: "vqrshrn.s16 d16, q8, #4"
+        -
+          asm_text: "vqrshrn.s32 d16, q8, #0xd"
+        -
+          asm_text: "vqrshrn.s64 d16, q8, #0xd"
+        -
+          asm_text: "vqrshrn.u16 d16, q8, #4"
+        -
+          asm_text: "vqrshrn.u32 d16, q8, #0xd"
+        -
+          asm_text: "vqrshrn.u64 d16, q8, #0xd"
+        -
+          asm_text: "vshl.s8 q4, q4, q5"
+        -
+          asm_text: "vshl.s16 q4, q4, q5"
+        -
+          asm_text: "vshl.s32 q4, q4, q5"
+        -
+          asm_text: "vshl.s64 q4, q4, q5"
+        -
+          asm_text: "vshl.u8 q4, q4, q5"
+        -
+          asm_text: "vshl.u16 q4, q4, q5"
+        -
+          asm_text: "vshl.u32 q4, q4, q5"
+        -
+          asm_text: "vshl.u64 q4, q4, q5"
+        -
+          asm_text: "vshl.s8 d4, d4, d5"
+        -
+          asm_text: "vshl.s16 d4, d4, d5"
+        -
+          asm_text: "vshl.s32 d4, d4, d5"
+        -
+          asm_text: "vshl.s64 d4, d4, d5"
+        -
+          asm_text: "vshl.u8 d4, d4, d5"
+        -
+          asm_text: "vshl.u16 d4, d4, d5"
+        -
+          asm_text: "vshl.u32 d4, d4, d5"
+        -
+          asm_text: "vshl.u64 d4, d4, d5"
+        -
+          asm_text: "vshl.i8 q4, q4, #2"
+        -
+          asm_text: "vshl.i16 q4, q4, #0xe"
+        -
+          asm_text: "vshl.i32 q4, q4, #0x1b"
+        -
+          asm_text: "vshl.i64 q4, q4, #0x23"
+        -
+          asm_text: "vshl.i8 d4, d4, #6"
+        -
+          asm_text: "vshl.i16 d4, d4, #0xa"
+        -
+          asm_text: "vshl.i32 d4, d4, #0x11"
+        -
+          asm_text: "vshl.i64 d4, d4, #0x2b"
+        -
+          asm_text: "vrshl.s8 d11, d11, d4"
+        -
+          asm_text: "vrshl.s16 d12, d12, d5"
+        -
+          asm_text: "vrshl.s32 d13, d13, d6"
+        -
+          asm_text: "vrshl.s64 d14, d14, d7"
+        -
+          asm_text: "vrshl.u8 d15, d15, d8"
+        -
+          asm_text: "vrshl.u16 d16, d16, d9"
+        -
+          asm_text: "vrshl.u32 d17, d17, d10"
+        -
+          asm_text: "vrshl.u64 d18, d18, d11"
+        -
+          asm_text: "vrshl.s8 q1, q1, q8"
+        -
+          asm_text: "vrshl.s16 q2, q2, q15"
+        -
+          asm_text: "vrshl.s32 q3, q3, q14"
+        -
+          asm_text: "vrshl.s64 q4, q4, q13"
+        -
+          asm_text: "vrshl.u8 q5, q5, q12"
+        -
+          asm_text: "vrshl.u16 q6, q6, q11"
+        -
+          asm_text: "vrshl.u32 q7, q7, q10"
+        -
+          asm_text: "vrshl.u64 q8, q8, q9"
+        -
+          asm_text: "vshr.s8 d15, d15, #8"
+        -
+          asm_text: "vshr.s16 d12, d12, #0x10"
+        -
+          asm_text: "vshr.s32 d13, d13, #0x20"
+        -
+          asm_text: "vshr.s64 d14, d14, #0x40"
+        -
+          asm_text: "vshr.u8 d16, d16, #8"
+        -
+          asm_text: "vshr.u16 d17, d17, #0x10"
+        -
+          asm_text: "vshr.u32 d6, d6, #0x20"
+        -
+          asm_text: "vshr.u64 d10, d10, #0x40"
+        -
+          asm_text: "vshr.s8 q1, q1, #8"
+        -
+          asm_text: "vshr.s16 q2, q2, #0x10"
+        -
+          asm_text: "vshr.s32 q3, q3, #0x20"
+        -
+          asm_text: "vshr.s64 q4, q4, #0x40"
+        -
+          asm_text: "vshr.u8 q5, q5, #8"
+        -
+          asm_text: "vshr.u16 q6, q6, #0x10"
+        -
+          asm_text: "vshr.u32 q7, q7, #0x20"
+        -
+          asm_text: "vshr.u64 q8, q8, #0x40"
+        -
+          asm_text: "vrshr.s8 d15, d15, #8"
+        -
+          asm_text: "vrshr.s16 d12, d12, #0x10"
+        -
+          asm_text: "vrshr.s32 d13, d13, #0x20"
+        -
+          asm_text: "vrshr.s64 d14, d14, #0x40"
+        -
+          asm_text: "vrshr.u8 d16, d16, #8"
+        -
+          asm_text: "vrshr.u16 d17, d17, #0x10"
+        -
+          asm_text: "vrshr.u32 d6, d6, #0x20"
+        -
+          asm_text: "vrshr.u64 d10, d10, #0x40"
+        -
+          asm_text: "vrshr.s8 q1, q1, #8"
+        -
+          asm_text: "vrshr.s16 q2, q2, #0x10"
+        -
+          asm_text: "vrshr.s32 q3, q3, #0x20"
+        -
+          asm_text: "vrshr.s64 q4, q4, #0x40"
+        -
+          asm_text: "vrshr.u8 q5, q5, #8"
+        -
+          asm_text: "vrshr.u16 q6, q6, #0x10"
+        -
+          asm_text: "vrshr.u32 q7, q7, #0x20"
+        -
+          asm_text: "vrshr.u64 q8, q8, #0x40"
diff --git a/tests/MC/ARM/neon-shiftaccum-encoding.s.yaml b/tests/MC/ARM/neon-shiftaccum-encoding.s.yaml
new file mode 100644
index 000000000..9f81e38cb
--- /dev/null
+++ b/tests/MC/ARM/neon-shiftaccum-encoding.s.yaml
@@ -0,0 +1,200 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x30, 0x11, 0xc8, 0xf2, 0x1e, 0xf1, 0x90, 0xf2, 0x1c, 0xd1, 0xa0, 0xf2, 0x9a, 0xb1, 0x80, 0xf2, 0x54, 0xe1, 0x88, 0xf2, 0x5c, 0x61, 0x90, 0xf2, 0x5a, 0x21, 0xe0, 0xf2, 0xd8, 0x01, 0xc0, 0xf2, 0x30, 0x11, 0xc8, 0xf3, 0x1e, 0xb1, 0x95, 0xf3, 0x1f, 0xc1, 0xaa, 0xf3, 0xb0, 0xd1, 0x8a, 0xf3, 0x5e, 0x21, 0x88, 0xf3, 0x5e, 0x41, 0x9a, 0xf3, 0x5c, 0x61, 0xab, 0xf3, 0xda, 0x81, 0xa7, 0xf3, 0x30, 0x01, 0xc8, 0xf2, 0x1e, 0xe1, 0x90, 0xf2, 0x1c, 0xc1, 0xa0, 0xf2, 0x9a, 0xa1, 0x80, 0xf2, 0x54, 0x41, 0x88, 0xf2, 0x5c, 0xc1, 0x90, 0xf2, 0x5a, 0xa1, 0xa0, 0xf2, 0xd8, 0x81, 0x80, 0xf2, 0x30, 0x01, 0xc8, 0xf3, 0x1e, 0xe1, 0x95, 0xf3, 0x1f, 0xf1, 0xaa, 0xf3, 0xb0, 0x01, 0xca, 0xf3, 0x5e, 0xe1, 0x88, 0xf3, 0x5e, 0xe1, 0x9a, 0xf3, 0x5c, 0xc1, 0xab, 0xf3, 0xda, 0xa1, 0xa7, 0xf3, 0x3a, 0x53, 0x88, 0xf2, 0x39, 0x63, 0x90, 0xf2, 0x38, 0x73, 0xa0, 0xf2, 0xb7, 0xe3, 0x80, 0xf2, 0x36, 0xf3, 0x88, 0xf3, 0x35, 0x03, 0xd0, 0xf3, 0x34, 0x13, 0xe0, 0xf3, 0xb3, 0x23, 0xc0, 0xf3, 0x54, 0x23, 0x88, 0xf2, 0x56, 0x43, 0x90, 0xf2, 0x58, 0x63, 0xa0, 0xf2, 0xda, 0x83, 0x80, 0xf2, 0x5c, 0xa3, 0x88, 0xf3, 0x5e, 0xc3, 0x90, 0xf3, 0x70, 0xe3, 0xa0, 0xf3, 0xf2, 0x03, 0xc0, 0xf3, 0x3a, 0xa3, 0xc8, 0xf2, 0x39, 0x93, 0xd0, 0xf2, 0x38, 0x83, 0xe0, 0xf2, 0xb7, 0x73, 0xc0, 0xf2, 0x36, 0x63, 0xc8, 0xf3, 0x35, 0x53, 0xd0, 0xf3, 0x34, 0x43, 0xe0, 0xf3, 0xb3, 0x33, 0xc0, 0xf3, 0x54, 0x43, 0x88, 0xf2, 0x56, 0x63, 0x90, 0xf2, 0x58, 0x83, 0xa0, 0xf2, 0xda, 0xa3, 0x80, 0xf2, 0x5c, 0xc3, 0x88, 0xf3, 0x5e, 0xe3, 0x90, 0xf3, 0x70, 0x03, 0xe0, 0xf3, 0xf2, 0x23, 0xc0, 0xf3, 0x1c, 0xb5, 0x8f, 0xf3, 0x1d, 0xc5, 0x9f, 0xf3, 0x1e, 0xd5, 0xbf, 0xf3, 0x9f, 0xe5, 0xbf, 0xf3, 0x70, 0x25, 0x8f, 0xf3, 0x5e, 0x45, 0x9f, 0xf3, 0x58, 0x65, 0xbf, 0xf3, 0xda, 0x85, 0xbf, 0xf3, 0x1b, 0xc4, 0xc8, 0xf3, 0x1c, 0xa4, 0xd0, 0xf3, 0x1d, 0x84, 0xe0, 0xf3, 0x9e, 0x54, 0xc0, 0xf3, 0x70, 0x24, 0x88, 0xf3, 0x54, 0xa4, 0x90, 0xf3, 0x58, 0xe4, 0xa0, 0xf3, 0xdc, 0x24, 0xc0, 0xf3, 0x1c, 0xc5, 0x8f, 0xf3, 0x1d, 0xd5, 0x9f, 0xf3, 0x1e, 0xe5, 0xbf, 0xf3, 0x9f, 0xf5, 0xbf, 0xf3, 0x70, 0x05, 0xcf, 0xf3, 0x5e, 0xe5, 0x9f, 0xf3, 0x58, 0x85, 0xbf, 0xf3, 0xda, 0xa5, 0xbf, 0xf3, 0x1b, 0xb4, 0x88, 0xf3, 0x1c, 0xc4, 0x90, 0xf3, 0x1d, 0xd4, 0xa0, 0xf3, 0x9e, 0xe4, 0x80, 0xf3, 0x70, 0x04, 0xc8, 0xf3, 0x54, 0x44, 0x90, 0xf3, 0x58, 0x84, 0xa0, 0xf3, 0xdc, 0xc4, 0x80, 0xf3 ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ]
+    expected:
+      insns:
+        -
+          asm_text: "vsra.s8 d17, d16, #8"
+        -
+          asm_text: "vsra.s16 d15, d14, #0x10"
+        -
+          asm_text: "vsra.s32 d13, d12, #0x20"
+        -
+          asm_text: "vsra.s64 d11, d10, #0x40"
+        -
+          asm_text: "vsra.s8 q7, q2, #8"
+        -
+          asm_text: "vsra.s16 q3, q6, #0x10"
+        -
+          asm_text: "vsra.s32 q9, q5, #0x20"
+        -
+          asm_text: "vsra.s64 q8, q4, #0x40"
+        -
+          asm_text: "vsra.u8 d17, d16, #8"
+        -
+          asm_text: "vsra.u16 d11, d14, #0xb"
+        -
+          asm_text: "vsra.u32 d12, d15, #0x16"
+        -
+          asm_text: "vsra.u64 d13, d16, #0x36"
+        -
+          asm_text: "vsra.u8 q1, q7, #8"
+        -
+          asm_text: "vsra.u16 q2, q7, #6"
+        -
+          asm_text: "vsra.u32 q3, q6, #0x15"
+        -
+          asm_text: "vsra.u64 q4, q5, #0x19"
+        -
+          asm_text: "vsra.s8 d16, d16, #8"
+        -
+          asm_text: "vsra.s16 d14, d14, #0x10"
+        -
+          asm_text: "vsra.s32 d12, d12, #0x20"
+        -
+          asm_text: "vsra.s64 d10, d10, #0x40"
+        -
+          asm_text: "vsra.s8 q2, q2, #8"
+        -
+          asm_text: "vsra.s16 q6, q6, #0x10"
+        -
+          asm_text: "vsra.s32 q5, q5, #0x20"
+        -
+          asm_text: "vsra.s64 q4, q4, #0x40"
+        -
+          asm_text: "vsra.u8 d16, d16, #8"
+        -
+          asm_text: "vsra.u16 d14, d14, #0xb"
+        -
+          asm_text: "vsra.u32 d15, d15, #0x16"
+        -
+          asm_text: "vsra.u64 d16, d16, #0x36"
+        -
+          asm_text: "vsra.u8 q7, q7, #8"
+        -
+          asm_text: "vsra.u16 q7, q7, #6"
+        -
+          asm_text: "vsra.u32 q6, q6, #0x15"
+        -
+          asm_text: "vsra.u64 q5, q5, #0x19"
+        -
+          asm_text: "vrsra.s8 d5, d26, #8"
+        -
+          asm_text: "vrsra.s16 d6, d25, #0x10"
+        -
+          asm_text: "vrsra.s32 d7, d24, #0x20"
+        -
+          asm_text: "vrsra.s64 d14, d23, #0x40"
+        -
+          asm_text: "vrsra.u8 d15, d22, #8"
+        -
+          asm_text: "vrsra.u16 d16, d21, #0x10"
+        -
+          asm_text: "vrsra.u32 d17, d20, #0x20"
+        -
+          asm_text: "vrsra.u64 d18, d19, #0x40"
+        -
+          asm_text: "vrsra.s8 q1, q2, #8"
+        -
+          asm_text: "vrsra.s16 q2, q3, #0x10"
+        -
+          asm_text: "vrsra.s32 q3, q4, #0x20"
+        -
+          asm_text: "vrsra.s64 q4, q5, #0x40"
+        -
+          asm_text: "vrsra.u8 q5, q6, #8"
+        -
+          asm_text: "vrsra.u16 q6, q7, #0x10"
+        -
+          asm_text: "vrsra.u32 q7, q8, #0x20"
+        -
+          asm_text: "vrsra.u64 q8, q9, #0x40"
+        -
+          asm_text: "vrsra.s8 d26, d26, #8"
+        -
+          asm_text: "vrsra.s16 d25, d25, #0x10"
+        -
+          asm_text: "vrsra.s32 d24, d24, #0x20"
+        -
+          asm_text: "vrsra.s64 d23, d23, #0x40"
+        -
+          asm_text: "vrsra.u8 d22, d22, #8"
+        -
+          asm_text: "vrsra.u16 d21, d21, #0x10"
+        -
+          asm_text: "vrsra.u32 d20, d20, #0x20"
+        -
+          asm_text: "vrsra.u64 d19, d19, #0x40"
+        -
+          asm_text: "vrsra.s8 q2, q2, #8"
+        -
+          asm_text: "vrsra.s16 q3, q3, #0x10"
+        -
+          asm_text: "vrsra.s32 q4, q4, #0x20"
+        -
+          asm_text: "vrsra.s64 q5, q5, #0x40"
+        -
+          asm_text: "vrsra.u8 q6, q6, #8"
+        -
+          asm_text: "vrsra.u16 q7, q7, #0x10"
+        -
+          asm_text: "vrsra.u32 q8, q8, #0x20"
+        -
+          asm_text: "vrsra.u64 q9, q9, #0x40"
+        -
+          asm_text: "vsli.8 d11, d12, #7"
+        -
+          asm_text: "vsli.16 d12, d13, #0xf"
+        -
+          asm_text: "vsli.32 d13, d14, #0x1f"
+        -
+          asm_text: "vsli.64 d14, d15, #0x3f"
+        -
+          asm_text: "vsli.8 q1, q8, #7"
+        -
+          asm_text: "vsli.16 q2, q7, #0xf"
+        -
+          asm_text: "vsli.32 q3, q4, #0x1f"
+        -
+          asm_text: "vsli.64 q4, q5, #0x3f"
+        -
+          asm_text: "vsri.8 d28, d11, #8"
+        -
+          asm_text: "vsri.16 d26, d12, #0x10"
+        -
+          asm_text: "vsri.32 d24, d13, #0x20"
+        -
+          asm_text: "vsri.64 d21, d14, #0x40"
+        -
+          asm_text: "vsri.8 q1, q8, #8"
+        -
+          asm_text: "vsri.16 q5, q2, #0x10"
+        -
+          asm_text: "vsri.32 q7, q4, #0x20"
+        -
+          asm_text: "vsri.64 q9, q6, #0x40"
+        -
+          asm_text: "vsli.8 d12, d12, #7"
+        -
+          asm_text: "vsli.16 d13, d13, #0xf"
+        -
+          asm_text: "vsli.32 d14, d14, #0x1f"
+        -
+          asm_text: "vsli.64 d15, d15, #0x3f"
+        -
+          asm_text: "vsli.8 q8, q8, #7"
+        -
+          asm_text: "vsli.16 q7, q7, #0xf"
+        -
+          asm_text: "vsli.32 q4, q4, #0x1f"
+        -
+          asm_text: "vsli.64 q5, q5, #0x3f"
+        -
+          asm_text: "vsri.8 d11, d11, #8"
+        -
+          asm_text: "vsri.16 d12, d12, #0x10"
+        -
+          asm_text: "vsri.32 d13, d13, #0x20"
+        -
+          asm_text: "vsri.64 d14, d14, #0x40"
+        -
+          asm_text: "vsri.8 q8, q8, #8"
+        -
+          asm_text: "vsri.16 q2, q2, #0x10"
+        -
+          asm_text: "vsri.32 q4, q4, #0x20"
+        -
+          asm_text: "vsri.64 q6, q6, #0x40"
diff --git a/tests/MC/ARM/neon-shuffle-encoding.s.yaml b/tests/MC/ARM/neon-shuffle-encoding.s.yaml
new file mode 100644
index 000000000..d88d80cbe
--- /dev/null
+++ b/tests/MC/ARM/neon-shuffle-encoding.s.yaml
@@ -0,0 +1,124 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xa0, 0x03, 0xf1, 0xf2, 0xa0, 0x05, 0xf1, 0xf2, 0xe0, 0x03, 0xf2, 0xf2, 0xe0, 0x07, 0xf2, 0xf2, 0xa0, 0x06, 0xf1, 0xf2, 0xe0, 0x0c, 0xf2, 0xf2, 0xe0, 0x08, 0xf2, 0xf2, 0xa0, 0x13, 0xf1, 0xf2, 0x0b, 0x75, 0xb7, 0xf2, 0x60, 0x63, 0xb6, 0xf2, 0xc8, 0x27, 0xf2, 0xf2, 0x2a, 0x16, 0xb1, 0xf2, 0x60, 0xac, 0xba, 0xf2, 0x60, 0xa8, 0xba, 0xf2, 0xa0, 0x10, 0xf2, 0xf3, 0xa0, 0x10, 0xf6, 0xf3, 0xa0, 0x10, 0xfa, 0xf3, 0xe0, 0x20, 0xf2, 0xf3, 0xe0, 0x20, 0xf6, 0xf3, 0xe0, 0x20, 0xfa, 0xf3, 0x20, 0x11, 0xf2, 0xf3, 0x20, 0x11, 0xf6, 0xf3, 0x60, 0x21, 0xf2, 0xf3, 0x60, 0x21, 0xf6, 0xf3, 0x60, 0x21, 0xfa, 0xf3, 0xa0, 0x11, 0xf2, 0xf3, 0xa0, 0x11, 0xf6, 0xf3, 0xe0, 0x21, 0xf2, 0xf3, 0xe0, 0x21, 0xf6, 0xf3, 0xe0, 0x21, 0xfa, 0xf3, 0x83, 0x20, 0xba, 0xf3, 0x83, 0x20, 0xba, 0xf3, 0x89, 0x30, 0xb2, 0xf3, 0x89, 0x30, 0xb2, 0xf3, 0x89, 0x30, 0xb2, 0xf3, 0x89, 0x30, 0xb2, 0xf3, 0x89, 0x30, 0xb6, 0xf3, 0x89, 0x30, 0xb6, 0xf3, 0x89, 0x30, 0xb6, 0xf3, 0x89, 0x30, 0xb6, 0xf3, 0x89, 0x30, 0xba, 0xf3, 0x89, 0x30, 0xba, 0xf3, 0x89, 0x30, 0xba, 0xf3, 0x89, 0x30, 0xba, 0xf3, 0x89, 0x30, 0xba, 0xf3, 0xcc, 0xc0, 0xf2, 0xf3, 0xcc, 0xc0, 0xf2, 0xf3, 0xcc, 0xc0, 0xf2, 0xf3, 0xcc, 0xc0, 0xf2, 0xf3, 0xcc, 0xc0, 0xf6, 0xf3, 0xcc, 0xc0, 0xf6, 0xf3, 0xcc, 0xc0, 0xf6, 0xf3, 0xcc, 0xc0, 0xf6, 0xf3, 0xcc, 0xc0, 0xfa, 0xf3, 0xcc, 0xc0, 0xfa, 0xf3, 0xcc, 0xc0, 0xfa, 0xf3, 0xcc, 0xc0, 0xfa, 0xf3, 0xcc, 0xc0, 0xfa, 0xf3 ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ]
+    expected:
+      insns:
+        -
+          asm_text: "vext.8 d16, d17, d16, #3"
+        -
+          asm_text: "vext.8 d16, d17, d16, #5"
+        -
+          asm_text: "vext.8 q8, q9, q8, #3"
+        -
+          asm_text: "vext.8 q8, q9, q8, #7"
+        -
+          asm_text: "vext.16 d16, d17, d16, #3"
+        -
+          asm_text: "vext.32 q8, q9, q8, #3"
+        -
+          asm_text: "vext.64 q8, q9, q8, #1"
+        -
+          asm_text: "vext.8 d17, d17, d16, #3"
+        -
+          asm_text: "vext.8 d7, d7, d11, #5"
+        -
+          asm_text: "vext.8 q3, q3, q8, #3"
+        -
+          asm_text: "vext.8 q9, q9, q4, #7"
+        -
+          asm_text: "vext.16 d1, d1, d26, #3"
+        -
+          asm_text: "vext.32 q5, q5, q8, #3"
+        -
+          asm_text: "vext.64 q5, q5, q8, #1"
+        -
+          asm_text: "vtrn.8 d17, d16"
+        -
+          asm_text: "vtrn.16 d17, d16"
+        -
+          asm_text: "vtrn.32 d17, d16"
+        -
+          asm_text: "vtrn.8 q9, q8"
+        -
+          asm_text: "vtrn.16 q9, q8"
+        -
+          asm_text: "vtrn.32 q9, q8"
+        -
+          asm_text: "vuzp.8 d17, d16"
+        -
+          asm_text: "vuzp.16 d17, d16"
+        -
+          asm_text: "vuzp.8 q9, q8"
+        -
+          asm_text: "vuzp.16 q9, q8"
+        -
+          asm_text: "vuzp.32 q9, q8"
+        -
+          asm_text: "vzip.8 d17, d16"
+        -
+          asm_text: "vzip.16 d17, d16"
+        -
+          asm_text: "vzip.8 q9, q8"
+        -
+          asm_text: "vzip.16 q9, q8"
+        -
+          asm_text: "vzip.32 q9, q8"
+        -
+          asm_text: "vtrn.32 d2, d3"
+        -
+          asm_text: "vtrn.32 d2, d3"
+        -
+          asm_text: "vtrn.8 d3, d9"
+        -
+          asm_text: "vtrn.8 d3, d9"
+        -
+          asm_text: "vtrn.8 d3, d9"
+        -
+          asm_text: "vtrn.8 d3, d9"
+        -
+          asm_text: "vtrn.16 d3, d9"
+        -
+          asm_text: "vtrn.16 d3, d9"
+        -
+          asm_text: "vtrn.16 d3, d9"
+        -
+          asm_text: "vtrn.16 d3, d9"
+        -
+          asm_text: "vtrn.32 d3, d9"
+        -
+          asm_text: "vtrn.32 d3, d9"
+        -
+          asm_text: "vtrn.32 d3, d9"
+        -
+          asm_text: "vtrn.32 d3, d9"
+        -
+          asm_text: "vtrn.32 d3, d9"
+        -
+          asm_text: "vtrn.8 q14, q6"
+        -
+          asm_text: "vtrn.8 q14, q6"
+        -
+          asm_text: "vtrn.8 q14, q6"
+        -
+          asm_text: "vtrn.8 q14, q6"
+        -
+          asm_text: "vtrn.16 q14, q6"
+        -
+          asm_text: "vtrn.16 q14, q6"
+        -
+          asm_text: "vtrn.16 q14, q6"
+        -
+          asm_text: "vtrn.16 q14, q6"
+        -
+          asm_text: "vtrn.32 q14, q6"
+        -
+          asm_text: "vtrn.32 q14, q6"
+        -
+          asm_text: "vtrn.32 q14, q6"
+        -
+          asm_text: "vtrn.32 q14, q6"
+        -
+          asm_text: "vtrn.32 q14, q6"
diff --git a/tests/MC/ARM/neon-sub-encoding.s.yaml b/tests/MC/ARM/neon-sub-encoding.s.yaml
new file mode 100644
index 000000000..91e179fe1
--- /dev/null
+++ b/tests/MC/ARM/neon-sub-encoding.s.yaml
@@ -0,0 +1,170 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xa0, 0x08, 0x41, 0xf3, 0xa0, 0x08, 0x51, 0xf3, 0xa0, 0x08, 0x61, 0xf3, 0xa0, 0x08, 0x71, 0xf3, 0xa1, 0x0d, 0x60, 0xf2, 0xe2, 0x08, 0x40, 0xf3, 0xe2, 0x08, 0x50, 0xf3, 0xe2, 0x08, 0x60, 0xf3, 0xe2, 0x08, 0x70, 0xf3, 0xe2, 0x0d, 0x60, 0xf2, 0x25, 0xd8, 0x0d, 0xf3, 0x26, 0xe8, 0x1e, 0xf3, 0x27, 0xf8, 0x2f, 0xf3, 0xa8, 0x08, 0x70, 0xf3, 0xa9, 0x1d, 0x61, 0xf2, 0x64, 0x28, 0x02, 0xf3, 0x62, 0x48, 0x14, 0xf3, 0x60, 0x68, 0x26, 0xf3, 0x4e, 0x88, 0x38, 0xf3, 0x4c, 0xad, 0x2a, 0xf2, 0xa0, 0x02, 0xc1, 0xf2, 0xa0, 0x02, 0xd1, 0xf2, 0xa0, 0x02, 0xe1, 0xf2, 0xa0, 0x02, 0xc1, 0xf3, 0xa0, 0x02, 0xd1, 0xf3, 0xa0, 0x02, 0xe1, 0xf3, 0xa2, 0x03, 0xc0, 0xf2, 0xa2, 0x03, 0xd0, 0xf2, 0xa2, 0x03, 0xe0, 0xf2, 0xa2, 0x03, 0xc0, 0xf3, 0xa2, 0x03, 0xd0, 0xf3, 0xa2, 0x03, 0xe0, 0xf3, 0xa1, 0x02, 0x40, 0xf2, 0xa1, 0x02, 0x50, 0xf2, 0xa1, 0x02, 0x60, 0xf2, 0xa1, 0x02, 0x40, 0xf3, 0xa1, 0x02, 0x50, 0xf3, 0xa1, 0x02, 0x60, 0xf3, 0xe2, 0x02, 0x40, 0xf2, 0xe2, 0x02, 0x50, 0xf2, 0xe2, 0x02, 0x60, 0xf2, 0xb1, 0x02, 0x40, 0xf2, 0xb1, 0x02, 0x50, 0xf2, 0xb1, 0x02, 0x60, 0xf2, 0xb1, 0x02, 0x70, 0xf2, 0xb1, 0x02, 0x40, 0xf3, 0xb1, 0x02, 0x50, 0xf3, 0xb1, 0x02, 0x60, 0xf3, 0xb1, 0x02, 0x70, 0xf3, 0xf2, 0x02, 0x40, 0xf2, 0xf2, 0x02, 0x50, 0xf2, 0xf2, 0x02, 0x60, 0xf2, 0xf2, 0x02, 0x70, 0xf2, 0xf2, 0x02, 0x40, 0xf3, 0xf2, 0x02, 0x50, 0xf3, 0xf2, 0x02, 0x60, 0xf3, 0xf2, 0x02, 0x70, 0xf3, 0xa2, 0x06, 0xc0, 0xf2, 0xa2, 0x06, 0xd0, 0xf2, 0xa2, 0x06, 0xe0, 0xf2, 0xa2, 0x06, 0xc0, 0xf3, 0xa2, 0x06, 0xd0, 0xf3, 0xa2, 0x06, 0xe0, 0xf3, 0x28, 0xb2, 0x0b, 0xf2, 0x27, 0xc2, 0x1c, 0xf2, 0x26, 0xd2, 0x2d, 0xf2, 0x25, 0xe2, 0x0e, 0xf3, 0x24, 0xf2, 0x1f, 0xf3, 0xa3, 0x02, 0x60, 0xf3, 0x68, 0x22, 0x02, 0xf2, 0x66, 0x42, 0x14, 0xf2, 0x64, 0x62, 0x26, 0xf2, 0x62, 0x82, 0x08, 0xf3, 0x60, 0xa2, 0x1a, 0xf3, 0x4e, 0xc2, 0x2c, 0xf3, 0x05, 0xc3, 0x8c, 0xf2, 0x01, 0xe3, 0x9e, 0xf2, 0x82, 0x03, 0xe0, 0xf2, 0x05, 0xc3, 0x8c, 0xf3, 0x01, 0xe3, 0x9e, 0xf3, 0x82, 0x03, 0xe0, 0xf3 ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ]
+    expected:
+      insns:
+        -
+          asm_text: "vsub.i8 d16, d17, d16"
+        -
+          asm_text: "vsub.i16 d16, d17, d16"
+        -
+          asm_text: "vsub.i32 d16, d17, d16"
+        -
+          asm_text: "vsub.i64 d16, d17, d16"
+        -
+          asm_text: "vsub.f32 d16, d16, d17"
+        -
+          asm_text: "vsub.i8 q8, q8, q9"
+        -
+          asm_text: "vsub.i16 q8, q8, q9"
+        -
+          asm_text: "vsub.i32 q8, q8, q9"
+        -
+          asm_text: "vsub.i64 q8, q8, q9"
+        -
+          asm_text: "vsub.f32 q8, q8, q9"
+        -
+          asm_text: "vsub.i8 d13, d13, d21"
+        -
+          asm_text: "vsub.i16 d14, d14, d22"
+        -
+          asm_text: "vsub.i32 d15, d15, d23"
+        -
+          asm_text: "vsub.i64 d16, d16, d24"
+        -
+          asm_text: "vsub.f32 d17, d17, d25"
+        -
+          asm_text: "vsub.i8 q1, q1, q10"
+        -
+          asm_text: "vsub.i16 q2, q2, q9"
+        -
+          asm_text: "vsub.i32 q3, q3, q8"
+        -
+          asm_text: "vsub.i64 q4, q4, q7"
+        -
+          asm_text: "vsub.f32 q5, q5, q6"
+        -
+          asm_text: "vsubl.s8 q8, d17, d16"
+        -
+          asm_text: "vsubl.s16 q8, d17, d16"
+        -
+          asm_text: "vsubl.s32 q8, d17, d16"
+        -
+          asm_text: "vsubl.u8 q8, d17, d16"
+        -
+          asm_text: "vsubl.u16 q8, d17, d16"
+        -
+          asm_text: "vsubl.u32 q8, d17, d16"
+        -
+          asm_text: "vsubw.s8 q8, q8, d18"
+        -
+          asm_text: "vsubw.s16 q8, q8, d18"
+        -
+          asm_text: "vsubw.s32 q8, q8, d18"
+        -
+          asm_text: "vsubw.u8 q8, q8, d18"
+        -
+          asm_text: "vsubw.u16 q8, q8, d18"
+        -
+          asm_text: "vsubw.u32 q8, q8, d18"
+        -
+          asm_text: "vhsub.s8 d16, d16, d17"
+        -
+          asm_text: "vhsub.s16 d16, d16, d17"
+        -
+          asm_text: "vhsub.s32 d16, d16, d17"
+        -
+          asm_text: "vhsub.u8 d16, d16, d17"
+        -
+          asm_text: "vhsub.u16 d16, d16, d17"
+        -
+          asm_text: "vhsub.u32 d16, d16, d17"
+        -
+          asm_text: "vhsub.s8 q8, q8, q9"
+        -
+          asm_text: "vhsub.s16 q8, q8, q9"
+        -
+          asm_text: "vhsub.s32 q8, q8, q9"
+        -
+          asm_text: "vqsub.s8 d16, d16, d17"
+        -
+          asm_text: "vqsub.s16 d16, d16, d17"
+        -
+          asm_text: "vqsub.s32 d16, d16, d17"
+        -
+          asm_text: "vqsub.s64 d16, d16, d17"
+        -
+          asm_text: "vqsub.u8 d16, d16, d17"
+        -
+          asm_text: "vqsub.u16 d16, d16, d17"
+        -
+          asm_text: "vqsub.u32 d16, d16, d17"
+        -
+          asm_text: "vqsub.u64 d16, d16, d17"
+        -
+          asm_text: "vqsub.s8 q8, q8, q9"
+        -
+          asm_text: "vqsub.s16 q8, q8, q9"
+        -
+          asm_text: "vqsub.s32 q8, q8, q9"
+        -
+          asm_text: "vqsub.s64 q8, q8, q9"
+        -
+          asm_text: "vqsub.u8 q8, q8, q9"
+        -
+          asm_text: "vqsub.u16 q8, q8, q9"
+        -
+          asm_text: "vqsub.u32 q8, q8, q9"
+        -
+          asm_text: "vqsub.u64 q8, q8, q9"
+        -
+          asm_text: "vsubhn.i16 d16, q8, q9"
+        -
+          asm_text: "vsubhn.i32 d16, q8, q9"
+        -
+          asm_text: "vsubhn.i64 d16, q8, q9"
+        -
+          asm_text: "vrsubhn.i16 d16, q8, q9"
+        -
+          asm_text: "vrsubhn.i32 d16, q8, q9"
+        -
+          asm_text: "vrsubhn.i64 d16, q8, q9"
+        -
+          asm_text: "vhsub.s8 d11, d11, d24"
+        -
+          asm_text: "vhsub.s16 d12, d12, d23"
+        -
+          asm_text: "vhsub.s32 d13, d13, d22"
+        -
+          asm_text: "vhsub.u8 d14, d14, d21"
+        -
+          asm_text: "vhsub.u16 d15, d15, d20"
+        -
+          asm_text: "vhsub.u32 d16, d16, d19"
+        -
+          asm_text: "vhsub.s8 q1, q1, q12"
+        -
+          asm_text: "vhsub.s16 q2, q2, q11"
+        -
+          asm_text: "vhsub.s32 q3, q3, q10"
+        -
+          asm_text: "vhsub.u8 q4, q4, q9"
+        -
+          asm_text: "vhsub.u16 q5, q5, q8"
+        -
+          asm_text: "vhsub.u32 q6, q6, q7"
+        -
+          asm_text: "vsubw.s8 q6, q6, d5"
+        -
+          asm_text: "vsubw.s16 q7, q7, d1"
+        -
+          asm_text: "vsubw.s32 q8, q8, d2"
+        -
+          asm_text: "vsubw.u8 q6, q6, d5"
+        -
+          asm_text: "vsubw.u16 q7, q7, d1"
+        -
+          asm_text: "vsubw.u32 q8, q8, d2"
diff --git a/tests/MC/ARM/neon-table-encoding.s.yaml b/tests/MC/ARM/neon-table-encoding.s.yaml
new file mode 100644
index 000000000..7f2e0732d
--- /dev/null
+++ b/tests/MC/ARM/neon-table-encoding.s.yaml
@@ -0,0 +1,24 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xa0, 0x08, 0xf1, 0xf3, 0xa2, 0x09, 0xf0, 0xf3, 0xa4, 0x0a, 0xf0, 0xf3, 0xa4, 0x0b, 0xf0, 0xf3, 0xe1, 0x28, 0xf0, 0xf3, 0xe2, 0x39, 0xf0, 0xf3, 0xe5, 0x4a, 0xf0, 0xf3, 0xe5, 0x4b, 0xf0, 0xf3 ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ]
+    expected:
+      insns:
+        -
+          asm_text: "vtbl.8 d16, {d17}, d16"
+        -
+          asm_text: "vtbl.8 d16, {d16, d17}, d18"
+        -
+          asm_text: "vtbl.8 d16, {d16, d17, d18}, d20"
+        -
+          asm_text: "vtbl.8 d16, {d16, d17, d18, d19}, d20"
+        -
+          asm_text: "vtbx.8 d18, {d16}, d17"
+        -
+          asm_text: "vtbx.8 d19, {d16, d17}, d18"
+        -
+          asm_text: "vtbx.8 d20, {d16, d17, d18}, d21"
+        -
+          asm_text: "vtbx.8 d20, {d16, d17, d18, d19}, d21"
diff --git a/tests/MC/ARM/neon-v8.s.yaml b/tests/MC/ARM/neon-v8.s.yaml
new file mode 100644
index 000000000..217c03f05
--- /dev/null
+++ b/tests/MC/ARM/neon-v8.s.yaml
@@ -0,0 +1,82 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x11, 0x4f, 0x05, 0xf3, 0x5c, 0x4f, 0x08, 0xf3, 0x3e, 0x5f, 0x24, 0xf3, 0xd4, 0x0f, 0x2a, 0xf3, 0x06, 0x40, 0xbb, 0xf3, 0x8a, 0xc0, 0xbb, 0xf3, 0x4c, 0x80, 0xbb, 0xf3, 0xe4, 0x80, 0xbb, 0xf3, 0x2e, 0x13, 0xbb, 0xf3, 0x8a, 0xc3, 0xbb, 0xf3, 0x64, 0x23, 0xbb, 0xf3, 0xc2, 0xa3, 0xfb, 0xf3, 0x21, 0xf1, 0xbb, 0xf3, 0x83, 0x51, 0xbb, 0xf3, 0x60, 0x61, 0xbb, 0xf3, 0xc6, 0xa1, 0xbb, 0xf3, 0x25, 0xb2, 0xbb, 0xf3, 0xa7, 0xe2, 0xbb, 0xf3, 0x6e, 0x82, 0xbb, 0xf3, 0xe0, 0x22, 0xfb, 0xf3, 0x00, 0x34, 0xba, 0xf3, 0x48, 0x24, 0xba, 0xf3, 0x8c, 0x54, 0xba, 0xf3, 0xc6, 0x04, 0xba, 0xf3, 0x00, 0x35, 0xba, 0xf3, 0x44, 0x05, 0xfa, 0xf3, 0xa2, 0xc5, 0xba, 0xf3, 0xc8, 0x25, 0xfa, 0xf3, 0x80, 0x36, 0xba, 0xf3, 0xc8, 0x26, 0xba, 0xf3, 0x80, 0x37, 0xba, 0xf3, 0xc8, 0x27, 0xba, 0xf3, 0x00, 0x34, 0xba, 0xf3, 0xc6, 0x04, 0xba, 0xf3, 0x00, 0x35, 0xba, 0xf3, 0xc8, 0x25, 0xfa, 0xf3, 0xc8, 0x27, 0xba, 0xf3 ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_V8", "CS_MODE_ARM" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmaxnm.f32 d4, d5, d1"
+        -
+          asm_text: "vmaxnm.f32 q2, q4, q6"
+        -
+          asm_text: "vminnm.f32 d5, d4, d30"
+        -
+          asm_text: "vminnm.f32 q0, q13, q2"
+        -
+          asm_text: "vcvta.s32.f32 d4, d6"
+        -
+          asm_text: "vcvta.u32.f32 d12, d10"
+        -
+          asm_text: "vcvta.s32.f32 q4, q6"
+        -
+          asm_text: "vcvta.u32.f32 q4, q10"
+        -
+          asm_text: "vcvtm.s32.f32 d1, d30"
+        -
+          asm_text: "vcvtm.u32.f32 d12, d10"
+        -
+          asm_text: "vcvtm.s32.f32 q1, q10"
+        -
+          asm_text: "vcvtm.u32.f32 q13, q1"
+        -
+          asm_text: "vcvtn.s32.f32 d15, d17"
+        -
+          asm_text: "vcvtn.u32.f32 d5, d3"
+        -
+          asm_text: "vcvtn.s32.f32 q3, q8"
+        -
+          asm_text: "vcvtn.u32.f32 q5, q3"
+        -
+          asm_text: "vcvtp.s32.f32 d11, d21"
+        -
+          asm_text: "vcvtp.u32.f32 d14, d23"
+        -
+          asm_text: "vcvtp.s32.f32 q4, q15"
+        -
+          asm_text: "vcvtp.u32.f32 q9, q8"
+        -
+          asm_text: "vrintn.f32 d3, d0"
+        -
+          asm_text: "vrintn.f32 q1, q4"
+        -
+          asm_text: "vrintx.f32 d5, d12"
+        -
+          asm_text: "vrintx.f32 q0, q3"
+        -
+          asm_text: "vrinta.f32 d3, d0"
+        -
+          asm_text: "vrinta.f32 q8, q2"
+        -
+          asm_text: "vrintz.f32 d12, d18"
+        -
+          asm_text: "vrintz.f32 q9, q4"
+        -
+          asm_text: "vrintm.f32 d3, d0"
+        -
+          asm_text: "vrintm.f32 q1, q4"
+        -
+          asm_text: "vrintp.f32 d3, d0"
+        -
+          asm_text: "vrintp.f32 q1, q4"
+        -
+          asm_text: "vrintn.f32 d3, d0"
+        -
+          asm_text: "vrintx.f32 q0, q3"
+        -
+          asm_text: "vrinta.f32 d3, d0"
+        -
+          asm_text: "vrintz.f32 q9, q4"
+        -
+          asm_text: "vrintp.f32 q1, q4"
diff --git a/tests/MC/ARM/neon-vld-encoding.s.yaml b/tests/MC/ARM/neon-vld-encoding.s.yaml
new file mode 100644
index 000000000..a6af6c628
--- /dev/null
+++ b/tests/MC/ARM/neon-vld-encoding.s.yaml
@@ -0,0 +1,432 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x1f, 0x07, 0x60, 0xf4, 0x4f, 0x07, 0x60, 0xf4, 0x8f, 0x07, 0x60, 0xf4, 0xcf, 0x07, 0x60, 0xf4, 0x1f, 0x0a, 0x60, 0xf4, 0x6f, 0x0a, 0x60, 0xf4, 0x8f, 0x0a, 0x60, 0xf4, 0xcf, 0x0a, 0x60, 0xf4, 0x0f, 0x16, 0x23, 0xf4, 0x5f, 0x46, 0x23, 0xf4, 0x8f, 0x56, 0x23, 0xf4, 0xdf, 0x66, 0x23, 0xf4, 0x0f, 0x12, 0x23, 0xf4, 0x5f, 0x42, 0x23, 0xf4, 0x8f, 0x52, 0x23, 0xf4, 0xdf, 0x62, 0x23, 0xf4, 0x1d, 0x07, 0x60, 0xf4, 0x4d, 0x07, 0x60, 0xf4, 0x8d, 0x07, 0x60, 0xf4, 0xcd, 0x07, 0x60, 0xf4, 0x1d, 0x0a, 0x60, 0xf4, 0x6d, 0x0a, 0x60, 0xf4, 0x8d, 0x0a, 0x60, 0xf4, 0xcd, 0x0a, 0x60, 0xf4, 0x15, 0x07, 0x60, 0xf4, 0x45, 0x07, 0x60, 0xf4, 0x85, 0x07, 0x60, 0xf4, 0xc5, 0x07, 0x60, 0xf4, 0x15, 0x0a, 0x60, 0xf4, 0x65, 0x0a, 0x60, 0xf4, 0x85, 0x0a, 0x60, 0xf4, 0xc5, 0x0a, 0x60, 0xf4, 0x0d, 0x16, 0x23, 0xf4, 0x5d, 0x46, 0x23, 0xf4, 0x8d, 0x56, 0x23, 0xf4, 0xdd, 0x66, 0x23, 0xf4, 0x06, 0x16, 0x23, 0xf4, 0x56, 0x46, 0x23, 0xf4, 0x86, 0x56, 0x23, 0xf4, 0xd6, 0x66, 0x23, 0xf4, 0x0d, 0x12, 0x23, 0xf4, 0x5d, 0x42, 0x23, 0xf4, 0x8d, 0x52, 0x23, 0xf4, 0xdd, 0x62, 0x23, 0xf4, 0x08, 0x12, 0x23, 0xf4, 0x58, 0x42, 0x23, 0xf4, 0x88, 0x52, 0x23, 0xf4, 0xd8, 0x62, 0x23, 0xf4, 0x1f, 0x08, 0x60, 0xf4, 0x6f, 0x08, 0x60, 0xf4, 0x8f, 0x08, 0x60, 0xf4, 0x1f, 0x03, 0x60, 0xf4, 0x6f, 0x03, 0x60, 0xf4, 0xbf, 0x03, 0x60, 0xf4, 0x1d, 0x38, 0x60, 0xf4, 0x6d, 0x08, 0x60, 0xf4, 0x8d, 0x48, 0x60, 0xf4, 0x1d, 0x43, 0x20, 0xf4, 0x6d, 0x13, 0x20, 0xf4, 0xbd, 0xe3, 0x20, 0xf4, 0x16, 0x38, 0x60, 0xf4, 0x66, 0x08, 0x60, 0xf4, 0x86, 0x48, 0x60, 0xf4, 0x16, 0x43, 0x20, 0xf4, 0x66, 0x13, 0x20, 0xf4, 0xb6, 0xe3, 0x20, 0xf4, 0x0f, 0x04, 0x61, 0xf4, 0x4f, 0x64, 0x22, 0xf4, 0x8f, 0x14, 0x23, 0xf4, 0x1f, 0x05, 0x60, 0xf4, 0x4f, 0xb5, 0x64, 0xf4, 0x8f, 0x65, 0x25, 0xf4, 0x01, 0xc4, 0x26, 0xf4, 0x42, 0xb4, 0x27, 0xf4, 0x83, 0x24, 0x28, 0xf4, 0x04, 0x45, 0x29, 0xf4, 0x44, 0xe5, 0x29, 0xf4, 0x85, 0x05, 0x6a, 0xf4, 0x0d, 0x64, 0x28, 0xf4, 0x4d, 0x94, 0x27, 0xf4, 0x8d, 0x14, 0x26, 0xf4, 0x1d, 0x05, 0x60, 0xf4, 0x4d, 0x45, 0x65, 0xf4, 0x8d, 0x55, 0x24, 0xf4, 0x1f, 0x00, 0x61, 0xf4, 0x6f, 0x00, 0x62, 0xf4, 0xbf, 0x00, 0x63, 0xf4, 0x3f, 0x11, 0x65, 0xf4, 0x4f, 0x11, 0x67, 0xf4, 0x8f, 0x01, 0x68, 0xf4, 0x1d, 0x00, 0x61, 0xf4, 0x6d, 0x00, 0x62, 0xf4, 0xbd, 0x00, 0x63, 0xf4, 0x3d, 0x11, 0x65, 0xf4, 0x4d, 0x11, 0x67, 0xf4, 0x8d, 0x01, 0x68, 0xf4, 0x18, 0x00, 0x61, 0xf4, 0x47, 0x00, 0x62, 0xf4, 0x95, 0x00, 0x63, 0xf4, 0x32, 0x01, 0x64, 0xf4, 0x43, 0x01, 0x66, 0xf4, 0x84, 0x11, 0x69, 0xf4, 0x0f, 0x4c, 0xa1, 0xf4, 0x0d, 0x4c, 0xa1, 0xf4, 0x03, 0x4c, 0xa1, 0xf4, 0x2f, 0x4c, 0xa1, 0xf4, 0x2d, 0x4c, 0xa1, 0xf4, 0x23, 0x4c, 0xa1, 0xf4, 0x6f, 0x00, 0xe0, 0xf4, 0x9f, 0x04, 0xe0, 0xf4, 0xbf, 0x08, 0xe0, 0xf4, 0xcd, 0xc0, 0xa2, 0xf4, 0xc2, 0xc0, 0xa2, 0xf4, 0xcd, 0xc4, 0xa2, 0xf4, 0x82, 0xc4, 0xa2, 0xf4, 0x3f, 0x01, 0xe0, 0xf4, 0x5f, 0x05, 0xe0, 0xf4, 0x8f, 0x09, 0xe0, 0xf4, 0x6f, 0x15, 0xe0, 0xf4, 0x5f, 0x19, 0xe0, 0xf4, 0x5d, 0x19, 0xe0, 0xf4, 0x83, 0x21, 0xa2, 0xf4, 0x8d, 0x21, 0xa2, 0xf4, 0x8f, 0x21, 0xa2, 0xf4, 0x8f, 0x6d, 0xe1, 0xf4, 0xaf, 0x6d, 0xe1, 0xf4, 0x8d, 0xad, 0xa3, 0xf4, 0xad, 0xed, 0xa4, 0xf4, 0x84, 0x6d, 0xe5, 0xf4, 0xa4, 0x6d, 0xe6, 0xf4, 0x2f, 0x02, 0xe1, 0xf4, 0x4f, 0x66, 0xa2, 0xf4, 0x8f, 0x1a, 0xa3, 0xf4, 0xaf, 0xb6, 0xe4, 0xf4, 0x4f, 0x6a, 0xa5, 0xf4, 0x61, 0xc2, 0xa6, 0xf4, 0x82, 0xb6, 0xa7, 0xf4, 0x83, 0x2a, 0xa8, 0xf4, 0xa4, 0xe6, 0xa9, 0xf4, 0x45, 0x0a, 0xea, 0xf4, 0xcd, 0x62, 0xa8, 0xf4, 0x8d, 0x96, 0xa7, 0xf4, 0x8d, 0x1a, 0xa6, 0xf4, 0xad, 0x46, 0xe5, 0xf4, 0x4d, 0x5a, 0xa4, 0xf4, 0x0f, 0x0e, 0xe1, 0xf4, 0x4f, 0x0e, 0xe2, 0xf4, 0x8f, 0x0e, 0xe3, 0xf4, 0x2f, 0x1e, 0xe7, 0xf4, 0x6f, 0x1e, 0xe7, 0xf4, 0xaf, 0x0e, 0xe8, 0xf4, 0x0d, 0x0e, 0xe1, 0xf4, 0x4d, 0x0e, 0xe2, 0xf4, 0x8d, 0x0e, 0xe3, 0xf4, 0x2d, 0x1e, 0xe7, 0xf4, 0x6d, 0x1e, 0xe7, 0xf4, 0xad, 0x0e, 0xe8, 0xf4, 0x08, 0x0e, 0xe1, 0xf4, 0x47, 0x0e, 0xe2, 0xf4, 0x85, 0x0e, 0xe3, 0xf4, 0x23, 0x0e, 0xe6, 0xf4, 0x63, 0x0e, 0xe6, 0xf4, 0xa4, 0x1e, 0xe9, 0xf4, 0x2f, 0x03, 0xe1, 0xf4, 0x4f, 0x07, 0xe2, 0xf4, 0x8f, 0x0b, 0xe3, 0xf4, 0x6f, 0x17, 0xe7, 0xf4, 0xcf, 0x0b, 0xe8, 0xf4, 0x3d, 0x03, 0xe1, 0xf4, 0x5d, 0x07, 0xe2, 0xf4, 0xad, 0x0b, 0xe3, 0xf4, 0x6d, 0x17, 0xe7, 0xf4, 0xcd, 0x0b, 0xe8, 0xf4, 0x38, 0x03, 0xe1, 0xf4, 0x47, 0x07, 0xe2, 0xf4, 0x95, 0x0b, 0xe3, 0xf4, 0x63, 0x07, 0xe6, 0xf4, 0xc4, 0x1b, 0xe9, 0xf4, 0x0f, 0x0f, 0xe1, 0xf4, 0x4f, 0x0f, 0xe2, 0xf4, 0x8f, 0x0f, 0xe3, 0xf4, 0x2f, 0x1f, 0xe7, 0xf4, 0x6f, 0x1f, 0xe7, 0xf4, 0xaf, 0x0f, 0xe8, 0xf4, 0x0d, 0x0f, 0xe1, 0xf4, 0x4d, 0x0f, 0xe2, 0xf4, 0x8d, 0x0f, 0xe3, 0xf4, 0x2d, 0x1f, 0xe7, 0xf4, 0x6d, 0x1f, 0xe7, 0xf4, 0xad, 0x0f, 0xe8, 0xf4, 0x08, 0x0f, 0xe1, 0xf4, 0x47, 0x0f, 0xe2, 0xf4, 0x85, 0x0f, 0xe3, 0xf4, 0x23, 0x0f, 0xe6, 0xf4, 0x63, 0x0f, 0xe6, 0xf4, 0xa4, 0x1f, 0xe9, 0xf4, 0x0f, 0x6a, 0x29, 0xf4, 0x0f, 0x62, 0x29, 0xf4, 0x0f, 0x27, 0x22, 0xf4, 0x0f, 0x27, 0x22, 0xf4, 0x0f, 0x27, 0x22, 0xf4, 0x0f, 0x4a, 0x22, 0xf4, 0x0f, 0x4a, 0x22, 0xf4, 0x0f, 0x4a, 0x22, 0xf4, 0x8f, 0x4a, 0x22, 0xf4, 0x0f, 0x26, 0x22, 0xf4, 0x8f, 0x26, 0x22, 0xf4, 0xcf, 0x26, 0x22, 0xf4, 0xed, 0x22, 0x22, 0xf4, 0xed, 0x22, 0x22, 0xf4, 0x1f, 0x08, 0x60, 0xf4, 0x6f, 0x08, 0x60, 0xf4 ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ]
+    expected:
+      insns:
+        -
+          asm_text: "vld1.8 {d16}, [r0:64]"
+        -
+          asm_text: "vld1.16 {d16}, [r0]"
+        -
+          asm_text: "vld1.32 {d16}, [r0]"
+        -
+          asm_text: "vld1.64 {d16}, [r0]"
+        -
+          asm_text: "vld1.8 {d16, d17}, [r0:64]"
+        -
+          asm_text: "vld1.16 {d16, d17}, [r0:128]"
+        -
+          asm_text: "vld1.32 {d16, d17}, [r0]"
+        -
+          asm_text: "vld1.64 {d16, d17}, [r0]"
+        -
+          asm_text: "vld1.8 {d1, d2, d3}, [r3]"
+        -
+          asm_text: "vld1.16 {d4, d5, d6}, [r3:64]"
+        -
+          asm_text: "vld1.32 {d5, d6, d7}, [r3]"
+        -
+          asm_text: "vld1.64 {d6, d7, d8}, [r3:64]"
+        -
+          asm_text: "vld1.8 {d1, d2, d3, d4}, [r3]"
+        -
+          asm_text: "vld1.16 {d4, d5, d6, d7}, [r3:64]"
+        -
+          asm_text: "vld1.32 {d5, d6, d7, d8}, [r3]"
+        -
+          asm_text: "vld1.64 {d6, d7, d8, d9}, [r3:64]"
+        -
+          asm_text: "vld1.8 {d16}, [r0:64]!"
+        -
+          asm_text: "vld1.16 {d16}, [r0]!"
+        -
+          asm_text: "vld1.32 {d16}, [r0]!"
+        -
+          asm_text: "vld1.64 {d16}, [r0]!"
+        -
+          asm_text: "vld1.8 {d16, d17}, [r0:64]!"
+        -
+          asm_text: "vld1.16 {d16, d17}, [r0:128]!"
+        -
+          asm_text: "vld1.32 {d16, d17}, [r0]!"
+        -
+          asm_text: "vld1.64 {d16, d17}, [r0]!"
+        -
+          asm_text: "vld1.8 {d16}, [r0:64], r5"
+        -
+          asm_text: "vld1.16 {d16}, [r0], r5"
+        -
+          asm_text: "vld1.32 {d16}, [r0], r5"
+        -
+          asm_text: "vld1.64 {d16}, [r0], r5"
+        -
+          asm_text: "vld1.8 {d16, d17}, [r0:64], r5"
+        -
+          asm_text: "vld1.16 {d16, d17}, [r0:128], r5"
+        -
+          asm_text: "vld1.32 {d16, d17}, [r0], r5"
+        -
+          asm_text: "vld1.64 {d16, d17}, [r0], r5"
+        -
+          asm_text: "vld1.8 {d1, d2, d3}, [r3]!"
+        -
+          asm_text: "vld1.16 {d4, d5, d6}, [r3:64]!"
+        -
+          asm_text: "vld1.32 {d5, d6, d7}, [r3]!"
+        -
+          asm_text: "vld1.64 {d6, d7, d8}, [r3:64]!"
+        -
+          asm_text: "vld1.8 {d1, d2, d3}, [r3], r6"
+        -
+          asm_text: "vld1.16 {d4, d5, d6}, [r3:64], r6"
+        -
+          asm_text: "vld1.32 {d5, d6, d7}, [r3], r6"
+        -
+          asm_text: "vld1.64 {d6, d7, d8}, [r3:64], r6"
+        -
+          asm_text: "vld1.8 {d1, d2, d3, d4}, [r3]!"
+        -
+          asm_text: "vld1.16 {d4, d5, d6, d7}, [r3:64]!"
+        -
+          asm_text: "vld1.32 {d5, d6, d7, d8}, [r3]!"
+        -
+          asm_text: "vld1.64 {d6, d7, d8, d9}, [r3:64]!"
+        -
+          asm_text: "vld1.8 {d1, d2, d3, d4}, [r3], r8"
+        -
+          asm_text: "vld1.16 {d4, d5, d6, d7}, [r3:64], r8"
+        -
+          asm_text: "vld1.32 {d5, d6, d7, d8}, [r3], r8"
+        -
+          asm_text: "vld1.64 {d6, d7, d8, d9}, [r3:64], r8"
+        -
+          asm_text: "vld2.8 {d16, d17}, [r0:64]"
+        -
+          asm_text: "vld2.16 {d16, d17}, [r0:128]"
+        -
+          asm_text: "vld2.32 {d16, d17}, [r0]"
+        -
+          asm_text: "vld2.8 {d16, d17, d18, d19}, [r0:64]"
+        -
+          asm_text: "vld2.16 {d16, d17, d18, d19}, [r0:128]"
+        -
+          asm_text: "vld2.32 {d16, d17, d18, d19}, [r0:256]"
+        -
+          asm_text: "vld2.8 {d19, d20}, [r0:64]!"
+        -
+          asm_text: "vld2.16 {d16, d17}, [r0:128]!"
+        -
+          asm_text: "vld2.32 {d20, d21}, [r0]!"
+        -
+          asm_text: "vld2.8 {d4, d5, d6, d7}, [r0:64]!"
+        -
+          asm_text: "vld2.16 {d1, d2, d3, d4}, [r0:128]!"
+        -
+          asm_text: "vld2.32 {d14, d15, d16, d17}, [r0:256]!"
+        -
+          asm_text: "vld2.8 {d19, d20}, [r0:64], r6"
+        -
+          asm_text: "vld2.16 {d16, d17}, [r0:128], r6"
+        -
+          asm_text: "vld2.32 {d20, d21}, [r0], r6"
+        -
+          asm_text: "vld2.8 {d4, d5, d6, d7}, [r0:64], r6"
+        -
+          asm_text: "vld2.16 {d1, d2, d3, d4}, [r0:128], r6"
+        -
+          asm_text: "vld2.32 {d14, d15, d16, d17}, [r0:256], r6"
+        -
+          asm_text: "vld3.8 {d16, d17, d18}, [r1]"
+        -
+          asm_text: "vld3.16 {d6, d7, d8}, [r2]"
+        -
+          asm_text: "vld3.32 {d1, d2, d3}, [r3]"
+        -
+          asm_text: "vld3.8 {d16, d18, d20}, [r0:64]"
+        -
+          asm_text: "vld3.16 {d27, d29, d31}, [r4]"
+        -
+          asm_text: "vld3.32 {d6, d8, d10}, [r5]"
+        -
+          asm_text: "vld3.8 {d12, d13, d14}, [r6], r1"
+        -
+          asm_text: "vld3.16 {d11, d12, d13}, [r7], r2"
+        -
+          asm_text: "vld3.32 {d2, d3, d4}, [r8], r3"
+        -
+          asm_text: "vld3.8 {d4, d6, d8}, [r9], r4"
+        -
+          asm_text: "vld3.16 {d14, d16, d18}, [r9], r4"
+        -
+          asm_text: "vld3.32 {d16, d18, d20}, [r10], r5"
+        -
+          asm_text: "vld3.8 {d6, d7, d8}, [r8]!"
+        -
+          asm_text: "vld3.16 {d9, d10, d11}, [r7]!"
+        -
+          asm_text: "vld3.32 {d1, d2, d3}, [r6]!"
+        -
+          asm_text: "vld3.8 {d16, d18, d20}, [r0:64]!"
+        -
+          asm_text: "vld3.16 {d20, d22, d24}, [r5]!"
+        -
+          asm_text: "vld3.32 {d5, d7, d9}, [r4]!"
+        -
+          asm_text: "vld4.8 {d16, d17, d18, d19}, [r1:64]"
+        -
+          asm_text: "vld4.16 {d16, d17, d18, d19}, [r2:128]"
+        -
+          asm_text: "vld4.32 {d16, d17, d18, d19}, [r3:256]"
+        -
+          asm_text: "vld4.8 {d17, d19, d21, d23}, [r5:256]"
+        -
+          asm_text: "vld4.16 {d17, d19, d21, d23}, [r7]"
+        -
+          asm_text: "vld4.32 {d16, d18, d20, d22}, [r8]"
+        -
+          asm_text: "vld4.8 {d16, d17, d18, d19}, [r1:64]!"
+        -
+          asm_text: "vld4.16 {d16, d17, d18, d19}, [r2:128]!"
+        -
+          asm_text: "vld4.32 {d16, d17, d18, d19}, [r3:256]!"
+        -
+          asm_text: "vld4.8 {d17, d19, d21, d23}, [r5:256]!"
+        -
+          asm_text: "vld4.16 {d17, d19, d21, d23}, [r7]!"
+        -
+          asm_text: "vld4.32 {d16, d18, d20, d22}, [r8]!"
+        -
+          asm_text: "vld4.8 {d16, d17, d18, d19}, [r1:64], r8"
+        -
+          asm_text: "vld4.16 {d16, d17, d18, d19}, [r2], r7"
+        -
+          asm_text: "vld4.32 {d16, d17, d18, d19}, [r3:64], r5"
+        -
+          asm_text: "vld4.8 {d16, d18, d20, d22}, [r4:256], r2"
+        -
+          asm_text: "vld4.16 {d16, d18, d20, d22}, [r6], r3"
+        -
+          asm_text: "vld4.32 {d17, d19, d21, d23}, [r9], r4"
+        -
+          asm_text: "vld1.8 {d4[]}, [r1]"
+        -
+          asm_text: "vld1.8 {d4[]}, [r1]!"
+        -
+          asm_text: "vld1.8 {d4[]}, [r1], r3"
+        -
+          asm_text: "vld1.8 {d4[], d5[]}, [r1]"
+        -
+          asm_text: "vld1.8 {d4[], d5[]}, [r1]!"
+        -
+          asm_text: "vld1.8 {d4[], d5[]}, [r1], r3"
+        -
+          asm_text: "vld1.8 {d16[3]}, [r0]"
+        -
+          asm_text: "vld1.16 {d16[2]}, [r0:16]"
+        -
+          asm_text: "vld1.32 {d16[1]}, [r0:32]"
+        -
+          asm_text: "vld1.8 {d12[6]}, [r2]!"
+        -
+          asm_text: "vld1.8 {d12[6]}, [r2], r2"
+        -
+          asm_text: "vld1.16 {d12[3]}, [r2]!"
+        -
+          asm_text: "vld1.16 {d12[2]}, [r2], r2"
+        -
+          asm_text: "vld2.8 {d16[1], d17[1]}, [r0:16]"
+        -
+          asm_text: "vld2.16 {d16[1], d17[1]}, [r0:32]"
+        -
+          asm_text: "vld2.32 {d16[1], d17[1]}, [r0]"
+        -
+          asm_text: "vld2.16 {d17[1], d19[1]}, [r0]"
+        -
+          asm_text: "vld2.32 {d17[0], d19[0]}, [r0:64]"
+        -
+          asm_text: "vld2.32 {d17[0], d19[0]}, [r0:64]!"
+        -
+          asm_text: "vld2.8 {d2[4], d3[4]}, [r2], r3"
+        -
+          asm_text: "vld2.8 {d2[4], d3[4]}, [r2]!"
+        -
+          asm_text: "vld2.8 {d2[4], d3[4]}, [r2]"
+        -
+          asm_text: "vld2.32 {d22[], d23[]}, [r1]"
+        -
+          asm_text: "vld2.32 {d22[], d24[]}, [r1]"
+        -
+          asm_text: "vld2.32 {d10[], d11[]}, [r3]!"
+        -
+          asm_text: "vld2.32 {d14[], d16[]}, [r4]!"
+        -
+          asm_text: "vld2.32 {d22[], d23[]}, [r5], r4"
+        -
+          asm_text: "vld2.32 {d22[], d24[]}, [r6], r4"
+        -
+          asm_text: "vld3.8 {d16[1], d17[1], d18[1]}, [r1]"
+        -
+          asm_text: "vld3.16 {d6[1], d7[1], d8[1]}, [r2]"
+        -
+          asm_text: "vld3.32 {d1[1], d2[1], d3[1]}, [r3]"
+        -
+          asm_text: "vld3.16 {d27[2], d29[2], d31[2]}, [r4]"
+        -
+          asm_text: "vld3.32 {d6[0], d8[0], d10[0]}, [r5]"
+        -
+          asm_text: "vld3.8 {d12[3], d13[3], d14[3]}, [r6], r1"
+        -
+          asm_text: "vld3.16 {d11[2], d12[2], d13[2]}, [r7], r2"
+        -
+          asm_text: "vld3.32 {d2[1], d3[1], d4[1]}, [r8], r3"
+        -
+          asm_text: "vld3.16 {d14[2], d16[2], d18[2]}, [r9], r4"
+        -
+          asm_text: "vld3.32 {d16[0], d18[0], d20[0]}, [r10], r5"
+        -
+          asm_text: "vld3.8 {d6[6], d7[6], d8[6]}, [r8]!"
+        -
+          asm_text: "vld3.16 {d9[2], d10[2], d11[2]}, [r7]!"
+        -
+          asm_text: "vld3.32 {d1[1], d2[1], d3[1]}, [r6]!"
+        -
+          asm_text: "vld3.16 {d20[2], d22[2], d24[2]}, [r5]!"
+        -
+          asm_text: "vld3.32 {d5[0], d7[0], d9[0]}, [r4]!"
+        -
+          asm_text: "vld3.8 {d16[], d17[], d18[]}, [r1]"
+        -
+          asm_text: "vld3.16 {d16[], d17[], d18[]}, [r2]"
+        -
+          asm_text: "vld3.32 {d16[], d17[], d18[]}, [r3]"
+        -
+          asm_text: "vld3.8 {d17[], d19[], d21[]}, [r7]"
+        -
+          asm_text: "vld3.16 {d17[], d19[], d21[]}, [r7]"
+        -
+          asm_text: "vld3.32 {d16[], d18[], d20[]}, [r8]"
+        -
+          asm_text: "vld3.8 {d16[], d17[], d18[]}, [r1]!"
+        -
+          asm_text: "vld3.16 {d16[], d17[], d18[]}, [r2]!"
+        -
+          asm_text: "vld3.32 {d16[], d17[], d18[]}, [r3]!"
+        -
+          asm_text: "vld3.8 {d17[], d19[], d21[]}, [r7]!"
+        -
+          asm_text: "vld3.16 {d17[], d19[], d21[]}, [r7]!"
+        -
+          asm_text: "vld3.32 {d16[], d18[], d20[]}, [r8]!"
+        -
+          asm_text: "vld3.8 {d16[], d17[], d18[]}, [r1], r8"
+        -
+          asm_text: "vld3.16 {d16[], d17[], d18[]}, [r2], r7"
+        -
+          asm_text: "vld3.32 {d16[], d17[], d18[]}, [r3], r5"
+        -
+          asm_text: "vld3.8 {d16[], d18[], d20[]}, [r6], r3"
+        -
+          asm_text: "vld3.16 {d16[], d18[], d20[]}, [r6], r3"
+        -
+          asm_text: "vld3.32 {d17[], d19[], d21[]}, [r9], r4"
+        -
+          asm_text: "vld4.8 {d16[1], d17[1], d18[1], d19[1]}, [r1]"
+        -
+          asm_text: "vld4.16 {d16[1], d17[1], d18[1], d19[1]}, [r2]"
+        -
+          asm_text: "vld4.32 {d16[1], d17[1], d18[1], d19[1]}, [r3]"
+        -
+          asm_text: "vld4.16 {d17[1], d19[1], d21[1], d23[1]}, [r7]"
+        -
+          asm_text: "vld4.32 {d16[1], d18[1], d20[1], d22[1]}, [r8]"
+        -
+          asm_text: "vld4.8 {d16[1], d17[1], d18[1], d19[1]}, [r1:32]!"
+        -
+          asm_text: "vld4.16 {d16[1], d17[1], d18[1], d19[1]}, [r2:64]!"
+        -
+          asm_text: "vld4.32 {d16[1], d17[1], d18[1], d19[1]}, [r3:128]!"
+        -
+          asm_text: "vld4.16 {d17[1], d19[1], d21[1], d23[1]}, [r7]!"
+        -
+          asm_text: "vld4.32 {d16[1], d18[1], d20[1], d22[1]}, [r8]!"
+        -
+          asm_text: "vld4.8 {d16[1], d17[1], d18[1], d19[1]}, [r1:32], r8"
+        -
+          asm_text: "vld4.16 {d16[1], d17[1], d18[1], d19[1]}, [r2], r7"
+        -
+          asm_text: "vld4.32 {d16[1], d17[1], d18[1], d19[1]}, [r3:64], r5"
+        -
+          asm_text: "vld4.16 {d16[1], d18[1], d20[1], d22[1]}, [r6], r3"
+        -
+          asm_text: "vld4.32 {d17[1], d19[1], d21[1], d23[1]}, [r9], r4"
+        -
+          asm_text: "vld4.8 {d16[], d17[], d18[], d19[]}, [r1]"
+        -
+          asm_text: "vld4.16 {d16[], d17[], d18[], d19[]}, [r2]"
+        -
+          asm_text: "vld4.32 {d16[], d17[], d18[], d19[]}, [r3]"
+        -
+          asm_text: "vld4.8 {d17[], d19[], d21[], d23[]}, [r7]"
+        -
+          asm_text: "vld4.16 {d17[], d19[], d21[], d23[]}, [r7]"
+        -
+          asm_text: "vld4.32 {d16[], d18[], d20[], d22[]}, [r8]"
+        -
+          asm_text: "vld4.8 {d16[], d17[], d18[], d19[]}, [r1]!"
+        -
+          asm_text: "vld4.16 {d16[], d17[], d18[], d19[]}, [r2]!"
+        -
+          asm_text: "vld4.32 {d16[], d17[], d18[], d19[]}, [r3]!"
+        -
+          asm_text: "vld4.8 {d17[], d19[], d21[], d23[]}, [r7]!"
+        -
+          asm_text: "vld4.16 {d17[], d19[], d21[], d23[]}, [r7]!"
+        -
+          asm_text: "vld4.32 {d16[], d18[], d20[], d22[]}, [r8]!"
+        -
+          asm_text: "vld4.8 {d16[], d17[], d18[], d19[]}, [r1], r8"
+        -
+          asm_text: "vld4.16 {d16[], d17[], d18[], d19[]}, [r2], r7"
+        -
+          asm_text: "vld4.32 {d16[], d17[], d18[], d19[]}, [r3], r5"
+        -
+          asm_text: "vld4.8 {d16[], d18[], d20[], d22[]}, [r6], r3"
+        -
+          asm_text: "vld4.16 {d16[], d18[], d20[], d22[]}, [r6], r3"
+        -
+          asm_text: "vld4.32 {d17[], d19[], d21[], d23[]}, [r9], r4"
+        -
+          asm_text: "vld1.8 {d6, d7}, [r9]"
+        -
+          asm_text: "vld1.8 {d6, d7, d8, d9}, [r9]"
+        -
+          asm_text: "vld1.8 {d2}, [r2]"
+        -
+          asm_text: "vld1.8 {d2}, [r2]"
+        -
+          asm_text: "vld1.8 {d2}, [r2]"
+        -
+          asm_text: "vld1.8 {d4, d5}, [r2]"
+        -
+          asm_text: "vld1.8 {d4, d5}, [r2]"
+        -
+          asm_text: "vld1.8 {d4, d5}, [r2]"
+        -
+          asm_text: "vld1.32 {d4, d5}, [r2]"
+        -
+          asm_text: "vld1.8 {d2, d3, d4}, [r2]"
+        -
+          asm_text: "vld1.32 {d2, d3, d4}, [r2]"
+        -
+          asm_text: "vld1.64 {d2, d3, d4}, [r2]"
+        -
+          asm_text: "vld1.64 {d2, d3, d4, d5}, [r2:128]!"
+        -
+          asm_text: "vld1.64 {d2, d3, d4, d5}, [r2:128]!"
+        -
+          asm_text: "vld2.8 {d16, d17}, [r0:64]"
+        -
+          asm_text: "vld2.16 {d16, d17}, [r0:128]"
diff --git a/tests/MC/ARM/neon-vld-vst-align.s.yaml b/tests/MC/ARM/neon-vld-vst-align.s.yaml
new file mode 100644
index 000000000..d5a1486f1
--- /dev/null
+++ b/tests/MC/ARM/neon-vld-vst-align.s.yaml
@@ -0,0 +1,1922 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x24, 0xf9, 0x0f, 0x07, 0x24, 0xf9, 0x1f, 0x07, 0x24, 0xf9, 0x0d, 0x07, 0x24, 0xf9, 0x1d, 0x07, 0x24, 0xf9, 0x06, 0x07, 0x24, 0xf9, 0x16, 0x07, 0x24, 0xf9, 0x0f, 0x0a, 0x24, 0xf9, 0x1f, 0x0a, 0x24, 0xf9, 0x2f, 0x0a, 0x24, 0xf9, 0x0d, 0x0a, 0x24, 0xf9, 0x1d, 0x0a, 0x24, 0xf9, 0x2d, 0x0a, 0x24, 0xf9, 0x06, 0x0a, 0x24, 0xf9, 0x16, 0x0a, 0x24, 0xf9, 0x26, 0x0a, 0x24, 0xf9, 0x0f, 0x06, 0x24, 0xf9, 0x1f, 0x06, 0x24, 0xf9, 0x0d, 0x06, 0x24, 0xf9, 0x1d, 0x06, 0x24, 0xf9, 0x06, 0x06, 0x24, 0xf9, 0x16, 0x06, 0x24, 0xf9, 0x0f, 0x02, 0x24, 0xf9, 0x1f, 0x02, 0x24, 0xf9, 0x2f, 0x02, 0x24, 0xf9, 0x3f, 0x02, 0x24, 0xf9, 0x0d, 0x02, 0x24, 0xf9, 0x1d, 0x02, 0x24, 0xf9, 0x2d, 0x02, 0x24, 0xf9, 0x3d, 0x02, 0x24, 0xf9, 0x06, 0x02, 0x24, 0xf9, 0x16, 0x02, 0x24, 0xf9, 0x26, 0x02, 0x24, 0xf9, 0x36, 0x02, 0xa4, 0xf9, 0x4f, 0x00, 0xa4, 0xf9, 0x4d, 0x00, 0xa4, 0xf9, 0x46, 0x00, 0xa4, 0xf9, 0x0f, 0x0c, 0xa4, 0xf9, 0x0d, 0x0c, 0xa4, 0xf9, 0x06, 0x0c, 0xa4, 0xf9, 0x2f, 0x0c, 0xa4, 0xf9, 0x2d, 0x0c, 0xa4, 0xf9, 0x26, 0x0c, 0x24, 0xf9, 0x4f, 0x07, 0x24, 0xf9, 0x5f, 0x07, 0x24, 0xf9, 0x4d, 0x07, 0x24, 0xf9, 0x5d, 0x07, 0x24, 0xf9, 0x46, 0x07, 0x24, 0xf9, 0x56, 0x07, 0x24, 0xf9, 0x4f, 0x0a, 0x24, 0xf9, 0x5f, 0x0a, 0x24, 0xf9, 0x6f, 0x0a, 0x24, 0xf9, 0x4d, 0x0a, 0x24, 0xf9, 0x5d, 0x0a, 0x24, 0xf9, 0x6d, 0x0a, 0x24, 0xf9, 0x46, 0x0a, 0x24, 0xf9, 0x56, 0x0a, 0x24, 0xf9, 0x66, 0x0a, 0x24, 0xf9, 0x4f, 0x06, 0x24, 0xf9, 0x5f, 0x06, 0x24, 0xf9, 0x4d, 0x06, 0x24, 0xf9, 0x5d, 0x06, 0x24, 0xf9, 0x46, 0x06, 0x24, 0xf9, 0x56, 0x06, 0x24, 0xf9, 0x4f, 0x02, 0x24, 0xf9, 0x5f, 0x02, 0x24, 0xf9, 0x6f, 0x02, 0x24, 0xf9, 0x7f, 0x02, 0x24, 0xf9, 0x4d, 0x02, 0x24, 0xf9, 0x5d, 0x02, 0x24, 0xf9, 0x6d, 0x02, 0x24, 0xf9, 0x7d, 0x02, 0x24, 0xf9, 0x46, 0x02, 0x24, 0xf9, 0x56, 0x02, 0x24, 0xf9, 0x66, 0x02, 0x24, 0xf9, 0x76, 0x02, 0xa4, 0xf9, 0x8f, 0x04, 0xa4, 0xf9, 0x9f, 0x04, 0xa4, 0xf9, 0x8d, 0x04, 0xa4, 0xf9, 0x9d, 0x04, 0xa4, 0xf9, 0x86, 0x04, 0xa4, 0xf9, 0x96, 0x04, 0xa4, 0xf9, 0x4f, 0x0c, 0xa4, 0xf9, 0x5f, 0x0c, 0xa4, 0xf9, 0x4d, 0x0c, 0xa4, 0xf9, 0x5d, 0x0c, 0xa4, 0xf9, 0x46, 0x0c, 0xa4, 0xf9, 0x56, 0x0c, 0xa4, 0xf9, 0x6f, 0x0c, 0xa4, 0xf9, 0x7f, 0x0c, 0xa4, 0xf9, 0x6d, 0x0c, 0xa4, 0xf9, 0x7d, 0x0c, 0xa4, 0xf9, 0x66, 0x0c, 0xa4, 0xf9, 0x76, 0x0c, 0x24, 0xf9, 0x8f, 0x07, 0x24, 0xf9, 0x9f, 0x07, 0x24, 0xf9, 0x8d, 0x07, 0x24, 0xf9, 0x9d, 0x07, 0x24, 0xf9, 0x86, 0x07, 0x24, 0xf9, 0x96, 0x07, 0x24, 0xf9, 0x8f, 0x0a, 0x24, 0xf9, 0x9f, 0x0a, 0x24, 0xf9, 0xaf, 0x0a, 0x24, 0xf9, 0x8d, 0x0a, 0x24, 0xf9, 0x9d, 0x0a, 0x24, 0xf9, 0xad, 0x0a, 0x24, 0xf9, 0x86, 0x0a, 0x24, 0xf9, 0x96, 0x0a, 0x24, 0xf9, 0xa6, 0x0a, 0x24, 0xf9, 0x8f, 0x06, 0x24, 0xf9, 0x9f, 0x06, 0x24, 0xf9, 0x8d, 0x06, 0x24, 0xf9, 0x9d, 0x06, 0x24, 0xf9, 0x86, 0x06, 0x24, 0xf9, 0x96, 0x06, 0x24, 0xf9, 0x8f, 0x02, 0x24, 0xf9, 0x9f, 0x02, 0x24, 0xf9, 0xaf, 0x02, 0x24, 0xf9, 0xbf, 0x02, 0x24, 0xf9, 0x8d, 0x02, 0x24, 0xf9, 0x9d, 0x02, 0x24, 0xf9, 0xad, 0x02, 0x24, 0xf9, 0xbd, 0x02, 0x24, 0xf9, 0x86, 0x02, 0x24, 0xf9, 0x96, 0x02, 0x24, 0xf9, 0xa6, 0x02, 0x24, 0xf9, 0xb6, 0x02, 0xa4, 0xf9, 0x8f, 0x08, 0xa4, 0xf9, 0xbf, 0x08, 0xa4, 0xf9, 0x8d, 0x08, 0xa4, 0xf9, 0xbd, 0x08, 0xa4, 0xf9, 0x86, 0x08, 0xa4, 0xf9, 0xb6, 0x08, 0xa4, 0xf9, 0x8f, 0x0c, 0xa4, 0xf9, 0x9f, 0x0c, 0xa4, 0xf9, 0x8d, 0x0c, 0xa4, 0xf9, 0x9d, 0x0c, 0xa4, 0xf9, 0x86, 0x0c, 0xa4, 0xf9, 0x96, 0x0c, 0xa4, 0xf9, 0xaf, 0x0c, 0xa4, 0xf9, 0xbf, 0x0c, 0xa4, 0xf9, 0xad, 0x0c, 0xa4, 0xf9, 0xbd, 0x0c, 0xa4, 0xf9, 0xa6, 0x0c, 0xa4, 0xf9, 0xb6, 0x0c, 0xa4, 0xf9, 0x8f, 0x08, 0xa4, 0xf9, 0xbf, 0x08, 0xa4, 0xf9, 0x8d, 0x08, 0xa4, 0xf9, 0xbd, 0x08, 0xa4, 0xf9, 0x86, 0x08, 0xa4, 0xf9, 0xb6, 0x08, 0x24, 0xf9, 0xcf, 0x07, 0x24, 0xf9, 0xdf, 0x07, 0x24, 0xf9, 0xcd, 0x07, 0x24, 0xf9, 0xdd, 0x07, 0x24, 0xf9, 0xc6, 0x07, 0x24, 0xf9, 0xd6, 0x07, 0x24, 0xf9, 0xcf, 0x0a, 0x24, 0xf9, 0xdf, 0x0a, 0x24, 0xf9, 0xef, 0x0a, 0x24, 0xf9, 0xcd, 0x0a, 0x24, 0xf9, 0xdd, 0x0a, 0x24, 0xf9, 0xed, 0x0a, 0x24, 0xf9, 0xc6, 0x0a, 0x24, 0xf9, 0xd6, 0x0a, 0x24, 0xf9, 0xe6, 0x0a, 0x24, 0xf9, 0xcf, 0x06, 0x24, 0xf9, 0xdf, 0x06, 0x24, 0xf9, 0xcd, 0x06, 0x24, 0xf9, 0xdd, 0x06, 0x24, 0xf9, 0xc6, 0x06, 0x24, 0xf9, 0xd6, 0x06, 0x24, 0xf9, 0xcf, 0x02, 0x24, 0xf9, 0xdf, 0x02, 0x24, 0xf9, 0xef, 0x02, 0x24, 0xf9, 0xff, 0x02, 0x24, 0xf9, 0xcd, 0x02, 0x24, 0xf9, 0xdd, 0x02, 0x24, 0xf9, 0xed, 0x02, 0x24, 0xf9, 0xfd, 0x02, 0x24, 0xf9, 0xc6, 0x02, 0x24, 0xf9, 0xd6, 0x02, 0x24, 0xf9, 0xe6, 0x02, 0x24, 0xf9, 0xf6, 0x02, 0x24, 0xf9, 0x0f, 0x08, 0x24, 0xf9, 0x1f, 0x08, 0x24, 0xf9, 0x2f, 0x08, 0x24, 0xf9, 0x0d, 0x08, 0x24, 0xf9, 0x1d, 0x08, 0x24, 0xf9, 0x2d, 0x08, 0x24, 0xf9, 0x06, 0x08, 0x24, 0xf9, 0x16, 0x08, 0x24, 0xf9, 0x26, 0x08, 0x24, 0xf9, 0x0f, 0x09, 0x24, 0xf9, 0x1f, 0x09, 0x24, 0xf9, 0x2f, 0x09, 0x24, 0xf9, 0x0d, 0x09, 0x24, 0xf9, 0x1d, 0x09, 0x24, 0xf9, 0x2d, 0x09, 0x24, 0xf9, 0x06, 0x09, 0x24, 0xf9, 0x16, 0x09, 0x24, 0xf9, 0x26, 0x09, 0x24, 0xf9, 0x0f, 0x03, 0x24, 0xf9, 0x1f, 0x03, 0x24, 0xf9, 0x2f, 0x03, 0x24, 0xf9, 0x3f, 0x03, 0x24, 0xf9, 0x0d, 0x03, 0x24, 0xf9, 0x1d, 0x03, 0x24, 0xf9, 0x2d, 0x03, 0x24, 0xf9, 0x3d, 0x03, 0x24, 0xf9, 0x06, 0x03, 0x24, 0xf9, 0x16, 0x03, 0x24, 0xf9, 0x26, 0x03, 0x24, 0xf9, 0x36, 0x03, 0xa4, 0xf9, 0x4f, 0x01, 0xa4, 0xf9, 0x5f, 0x01, 0xa4, 0xf9, 0x4d, 0x01, 0xa4, 0xf9, 0x5d, 0x01, 0xa4, 0xf9, 0x46, 0x01, 0xa4, 0xf9, 0x56, 0x01, 0xa4, 0xf9, 0x0f, 0x0d, 0xa4, 0xf9, 0x1f, 0x0d, 0xa4, 0xf9, 0x0d, 0x0d, 0xa4, 0xf9, 0x1d, 0x0d, 0xa4, 0xf9, 0x06, 0x0d, 0xa4, 0xf9, 0x16, 0x0d, 0xa4, 0xf9, 0x2f, 0x0d, 0xa4, 0xf9, 0x3f, 0x0d, 0xa4, 0xf9, 0x2d, 0x0d, 0xa4, 0xf9, 0x3d, 0x0d, 0xa4, 0xf9, 0x26, 0x0d, 0xa4, 0xf9, 0x36, 0x0d, 0x24, 0xf9, 0x4f, 0x08, 0x24, 0xf9, 0x5f, 0x08, 0x24, 0xf9, 0x6f, 0x08, 0x24, 0xf9, 0x4d, 0x08, 0x24, 0xf9, 0x5d, 0x08, 0x24, 0xf9, 0x6d, 0x08, 0x24, 0xf9, 0x46, 0x08, 0x24, 0xf9, 0x56, 0x08, 0x24, 0xf9, 0x66, 0x08, 0x24, 0xf9, 0x4f, 0x09, 0x24, 0xf9, 0x5f, 0x09, 0x24, 0xf9, 0x6f, 0x09, 0x24, 0xf9, 0x4d, 0x09, 0x24, 0xf9, 0x5d, 0x09, 0x24, 0xf9, 0x6d, 0x09, 0x24, 0xf9, 0x46, 0x09, 0x24, 0xf9, 0x56, 0x09, 0x24, 0xf9, 0x66, 0x09, 0x24, 0xf9, 0x4f, 0x03, 0x24, 0xf9, 0x5f, 0x03, 0x24, 0xf9, 0x6f, 0x03, 0x24, 0xf9, 0x7f, 0x03, 0x24, 0xf9, 0x4d, 0x03, 0x24, 0xf9, 0x5d, 0x03, 0x24, 0xf9, 0x6d, 0x03, 0x24, 0xf9, 0x7d, 0x03, 0x24, 0xf9, 0x46, 0x03, 0x24, 0xf9, 0x56, 0x03, 0x24, 0xf9, 0x66, 0x03, 0x24, 0xf9, 0x76, 0x03, 0xa4, 0xf9, 0x8f, 0x05, 0xa4, 0xf9, 0x9f, 0x05, 0xa4, 0xf9, 0x8d, 0x05, 0xa4, 0xf9, 0x9d, 0x05, 0xa4, 0xf9, 0x86, 0x05, 0xa4, 0xf9, 0x96, 0x05, 0xa4, 0xf9, 0xaf, 0x05, 0xa4, 0xf9, 0xbf, 0x05, 0xa4, 0xf9, 0xad, 0x05, 0xa4, 0xf9, 0xbd, 0x05, 0xa4, 0xf9, 0xa6, 0x05, 0xa4, 0xf9, 0xb6, 0x05, 0xa4, 0xf9, 0x4f, 0x0d, 0xa4, 0xf9, 0x5f, 0x0d, 0xa4, 0xf9, 0x4d, 0x0d, 0xa4, 0xf9, 0x5d, 0x0d, 0xa4, 0xf9, 0x46, 0x0d, 0xa4, 0xf9, 0x56, 0x0d, 0xa4, 0xf9, 0x6f, 0x0d, 0xa4, 0xf9, 0x7f, 0x0d, 0xa4, 0xf9, 0x6d, 0x0d, 0xa4, 0xf9, 0x7d, 0x0d, 0xa4, 0xf9, 0x66, 0x0d, 0xa4, 0xf9, 0x76, 0x0d, 0x24, 0xf9, 0x8f, 0x08, 0x24, 0xf9, 0x9f, 0x08, 0x24, 0xf9, 0xaf, 0x08, 0x24, 0xf9, 0x8d, 0x08, 0x24, 0xf9, 0x9d, 0x08, 0x24, 0xf9, 0xad, 0x08, 0x24, 0xf9, 0x86, 0x08, 0x24, 0xf9, 0x96, 0x08, 0x24, 0xf9, 0xa6, 0x08, 0x24, 0xf9, 0x8f, 0x09, 0x24, 0xf9, 0x9f, 0x09, 0x24, 0xf9, 0xaf, 0x09, 0x24, 0xf9, 0x8d, 0x09, 0x24, 0xf9, 0x9d, 0x09, 0x24, 0xf9, 0xad, 0x09, 0x24, 0xf9, 0x86, 0x09, 0x24, 0xf9, 0x96, 0x09, 0x24, 0xf9, 0xa6, 0x09, 0x24, 0xf9, 0x8f, 0x03, 0x24, 0xf9, 0x9f, 0x03, 0x24, 0xf9, 0xaf, 0x03, 0x24, 0xf9, 0xbf, 0x03, 0x24, 0xf9, 0x8d, 0x03, 0x24, 0xf9, 0x9d, 0x03, 0x24, 0xf9, 0xad, 0x03, 0x24, 0xf9, 0xbd, 0x03, 0x24, 0xf9, 0x86, 0x03, 0x24, 0xf9, 0x96, 0x03, 0x24, 0xf9, 0xa6, 0x03, 0x24, 0xf9, 0xb6, 0x03, 0xa4, 0xf9, 0x8f, 0x09, 0xa4, 0xf9, 0x9f, 0x09, 0xa4, 0xf9, 0x8d, 0x09, 0xa4, 0xf9, 0x9d, 0x09, 0xa4, 0xf9, 0x86, 0x09, 0xa4, 0xf9, 0x96, 0x09, 0xa4, 0xf9, 0xcf, 0x09, 0xa4, 0xf9, 0xdf, 0x09, 0xa4, 0xf9, 0xcd, 0x09, 0xa4, 0xf9, 0xdd, 0x09, 0xa4, 0xf9, 0xc6, 0x09, 0xa4, 0xf9, 0xd6, 0x09, 0xa4, 0xf9, 0x8f, 0x0d, 0xa4, 0xf9, 0x9f, 0x0d, 0xa4, 0xf9, 0x8d, 0x0d, 0xa4, 0xf9, 0x9d, 0x0d, 0xa4, 0xf9, 0x86, 0x0d, 0xa4, 0xf9, 0x96, 0x0d, 0xa4, 0xf9, 0xaf, 0x0d, 0xa4, 0xf9, 0xbf, 0x0d, 0xa4, 0xf9, 0xad, 0x0d, 0xa4, 0xf9, 0xbd, 0x0d, 0xa4, 0xf9, 0xa6, 0x0d, 0xa4, 0xf9, 0xb6, 0x0d, 0x24, 0xf9, 0x0f, 0x04, 0x24, 0xf9, 0x1f, 0x04, 0x24, 0xf9, 0x0d, 0x04, 0x24, 0xf9, 0x1d, 0x04, 0x24, 0xf9, 0x06, 0x04, 0x24, 0xf9, 0x16, 0x04, 0x24, 0xf9, 0x0f, 0x05, 0x24, 0xf9, 0x1f, 0x05, 0x24, 0xf9, 0x0d, 0x05, 0x24, 0xf9, 0x1d, 0x05, 0x24, 0xf9, 0x06, 0x05, 0x24, 0xf9, 0x16, 0x05, 0xa4, 0xf9, 0x2f, 0x02, 0xa4, 0xf9, 0x2d, 0x02, 0xa4, 0xf9, 0x26, 0x02, 0xa4, 0xf9, 0x0f, 0x0e, 0xa4, 0xf9, 0x0d, 0x0e, 0xa4, 0xf9, 0x06, 0x0e, 0xa4, 0xf9, 0x2f, 0x0e, 0xa4, 0xf9, 0x2d, 0x0e, 0xa4, 0xf9, 0x26, 0x0e, 0x24, 0xf9, 0x4f, 0x04, 0x24, 0xf9, 0x5f, 0x04, 0x24, 0xf9, 0x4d, 0x04, 0x24, 0xf9, 0x5d, 0x04, 0x24, 0xf9, 0x46, 0x04, 0x24, 0xf9, 0x56, 0x04, 0x24, 0xf9, 0x4f, 0x05, 0x24, 0xf9, 0x5f, 0x05, 0x24, 0xf9, 0x4d, 0x05, 0x24, 0xf9, 0x5d, 0x05, 0x24, 0xf9, 0x46, 0x05, 0x24, 0xf9, 0x56, 0x05, 0xa4, 0xf9, 0x4f, 0x06, 0xa4, 0xf9, 0x4d, 0x06, 0xa4, 0xf9, 0x46, 0x06, 0xa4, 0xf9, 0x6f, 0x06, 0xa4, 0xf9, 0x6d, 0x06, 0xa4, 0xf9, 0x66, 0x06, 0xa4, 0xf9, 0x4f, 0x0e, 0xa4, 0xf9, 0x4d, 0x0e, 0xa4, 0xf9, 0x46, 0x0e, 0xa4, 0xf9, 0x6f, 0x0e, 0xa4, 0xf9, 0x6d, 0x0e, 0xa4, 0xf9, 0x66, 0x0e, 0x24, 0xf9, 0x8f, 0x04, 0x24, 0xf9, 0x9f, 0x04, 0x24, 0xf9, 0x8d, 0x04, 0x24, 0xf9, 0x9d, 0x04, 0x24, 0xf9, 0x86, 0x04, 0x24, 0xf9, 0x96, 0x04, 0x24, 0xf9, 0x8f, 0x05, 0x24, 0xf9, 0x9f, 0x05, 0x24, 0xf9, 0x8d, 0x05, 0x24, 0xf9, 0x9d, 0x05, 0x24, 0xf9, 0x86, 0x05, 0x24, 0xf9, 0x96, 0x05, 0xa4, 0xf9, 0x8f, 0x0a, 0xa4, 0xf9, 0x8d, 0x0a, 0xa4, 0xf9, 0x86, 0x0a, 0xa4, 0xf9, 0xcf, 0x0a, 0xa4, 0xf9, 0xcd, 0x0a, 0xa4, 0xf9, 0xc6, 0x0a, 0xa4, 0xf9, 0x8f, 0x0e, 0xa4, 0xf9, 0x8d, 0x0e, 0xa4, 0xf9, 0x86, 0x0e, 0xa4, 0xf9, 0xaf, 0x0e, 0xa4, 0xf9, 0xad, 0x0e, 0xa4, 0xf9, 0xa6, 0x0e, 0x24, 0xf9, 0x0f, 0x00, 0x24, 0xf9, 0x1f, 0x00, 0x24, 0xf9, 0x2f, 0x00, 0x24, 0xf9, 0x3f, 0x00, 0x24, 0xf9, 0x0d, 0x00, 0x24, 0xf9, 0x1d, 0x00, 0x24, 0xf9, 0x2d, 0x00, 0x24, 0xf9, 0x3d, 0x00, 0x24, 0xf9, 0x06, 0x00, 0x24, 0xf9, 0x16, 0x00, 0x24, 0xf9, 0x26, 0x00, 0x24, 0xf9, 0x36, 0x00, 0x24, 0xf9, 0x0f, 0x01, 0x24, 0xf9, 0x1f, 0x01, 0x24, 0xf9, 0x2f, 0x01, 0x24, 0xf9, 0x3f, 0x01, 0x24, 0xf9, 0x0d, 0x01, 0x24, 0xf9, 0x1d, 0x01, 0x24, 0xf9, 0x2d, 0x01, 0x24, 0xf9, 0x3d, 0x01, 0x24, 0xf9, 0x06, 0x01, 0x24, 0xf9, 0x16, 0x01, 0x24, 0xf9, 0x26, 0x01, 0x24, 0xf9, 0x36, 0x01, 0xa4, 0xf9, 0x2f, 0x03, 0xa4, 0xf9, 0x3f, 0x03, 0xa4, 0xf9, 0x2d, 0x03, 0xa4, 0xf9, 0x3d, 0x03, 0xa4, 0xf9, 0x26, 0x03, 0xa4, 0xf9, 0x36, 0x03, 0xa4, 0xf9, 0x0f, 0x0f, 0xa4, 0xf9, 0x1f, 0x0f, 0xa4, 0xf9, 0x0d, 0x0f, 0xa4, 0xf9, 0x1d, 0x0f, 0xa4, 0xf9, 0x06, 0x0f, 0xa4, 0xf9, 0x16, 0x0f, 0xa4, 0xf9, 0x2f, 0x0f, 0xa4, 0xf9, 0x3f, 0x0f, 0xa4, 0xf9, 0x2d, 0x0f, 0xa4, 0xf9, 0x3d, 0x0f, 0xa4, 0xf9, 0x26, 0x0f, 0xa4, 0xf9, 0x36, 0x0f, 0x24, 0xf9, 0x4f, 0x00, 0x24, 0xf9, 0x5f, 0x00, 0x24, 0xf9, 0x6f, 0x00, 0x24, 0xf9, 0x7f, 0x00, 0x24, 0xf9, 0x4d, 0x00, 0x24, 0xf9, 0x5d, 0x00, 0x24, 0xf9, 0x6d, 0x00, 0x24, 0xf9, 0x7d, 0x00, 0x24, 0xf9, 0x46, 0x00, 0x24, 0xf9, 0x56, 0x00, 0x24, 0xf9, 0x66, 0x00, 0x24, 0xf9, 0x76, 0x00, 0x24, 0xf9, 0x4f, 0x01, 0x24, 0xf9, 0x5f, 0x01, 0x24, 0xf9, 0x6f, 0x01, 0x24, 0xf9, 0x7f, 0x01, 0x24, 0xf9, 0x4d, 0x01, 0x24, 0xf9, 0x5d, 0x01, 0x24, 0xf9, 0x6d, 0x01, 0x24, 0xf9, 0x7d, 0x01, 0x24, 0xf9, 0x46, 0x01, 0x24, 0xf9, 0x56, 0x01, 0x24, 0xf9, 0x66, 0x01, 0x24, 0xf9, 0x76, 0x01, 0xa4, 0xf9, 0x4f, 0x07, 0xa4, 0xf9, 0x5f, 0x07, 0xa4, 0xf9, 0x4d, 0x07, 0xa4, 0xf9, 0x5d, 0x07, 0xa4, 0xf9, 0x46, 0x07, 0xa4, 0xf9, 0x56, 0x07, 0xa4, 0xf9, 0x6f, 0x07, 0xa4, 0xf9, 0x7f, 0x07, 0xa4, 0xf9, 0x6d, 0x07, 0xa4, 0xf9, 0x7d, 0x07, 0xa4, 0xf9, 0x66, 0x07, 0xa4, 0xf9, 0x76, 0x07, 0xa4, 0xf9, 0x4f, 0x0f, 0xa4, 0xf9, 0x5f, 0x0f, 0xa4, 0xf9, 0x4d, 0x0f, 0xa4, 0xf9, 0x5d, 0x0f, 0xa4, 0xf9, 0x46, 0x0f, 0xa4, 0xf9, 0x56, 0x0f, 0xa4, 0xf9, 0x6f, 0x0f, 0xa4, 0xf9, 0x7f, 0x0f, 0xa4, 0xf9, 0x6d, 0x0f, 0xa4, 0xf9, 0x7d, 0x0f, 0xa4, 0xf9, 0x66, 0x0f, 0xa4, 0xf9, 0x76, 0x0f, 0x24, 0xf9, 0x8f, 0x00, 0x24, 0xf9, 0x9f, 0x00, 0x24, 0xf9, 0xaf, 0x00, 0x24, 0xf9, 0xbf, 0x00, 0x24, 0xf9, 0x8d, 0x00, 0x24, 0xf9, 0x9d, 0x00, 0x24, 0xf9, 0xad, 0x00, 0x24, 0xf9, 0xbd, 0x00, 0x24, 0xf9, 0x86, 0x00, 0x24, 0xf9, 0x96, 0x00, 0x24, 0xf9, 0xa6, 0x00, 0x24, 0xf9, 0xb6, 0x00, 0x24, 0xf9, 0x8f, 0x01, 0x24, 0xf9, 0x9f, 0x01, 0x24, 0xf9, 0xaf, 0x01, 0x24, 0xf9, 0xbf, 0x01, 0x24, 0xf9, 0x8d, 0x01, 0x24, 0xf9, 0x9d, 0x01, 0x24, 0xf9, 0xad, 0x01, 0x24, 0xf9, 0xbd, 0x01, 0x24, 0xf9, 0x86, 0x01, 0x24, 0xf9, 0x96, 0x01, 0x24, 0xf9, 0xa6, 0x01, 0x24, 0xf9, 0xb6, 0x01, 0xa4, 0xf9, 0x8f, 0x0b, 0xa4, 0xf9, 0x9f, 0x0b, 0xa4, 0xf9, 0xaf, 0x0b, 0xa4, 0xf9, 0x8d, 0x0b, 0xa4, 0xf9, 0x9d, 0x0b, 0xa4, 0xf9, 0xad, 0x0b, 0xa4, 0xf9, 0x86, 0x0b, 0xa4, 0xf9, 0x96, 0x0b, 0xa4, 0xf9, 0xa6, 0x0b, 0xa4, 0xf9, 0xcf, 0x0b, 0xa4, 0xf9, 0xdf, 0x0b, 0xa4, 0xf9, 0xef, 0x0b, 0xa4, 0xf9, 0xcd, 0x0b, 0xa4, 0xf9, 0xdd, 0x0b, 0xa4, 0xf9, 0xed, 0x0b, 0xa4, 0xf9, 0xc6, 0x0b, 0xa4, 0xf9, 0xd6, 0x0b, 0xa4, 0xf9, 0xe6, 0x0b, 0xa4, 0xf9, 0x8f, 0x0f, 0xa4, 0xf9, 0x9f, 0x0f, 0xa4, 0xf9, 0xdf, 0x0f, 0xa4, 0xf9, 0x8d, 0x0f, 0xa4, 0xf9, 0x9d, 0x0f, 0xa4, 0xf9, 0xdd, 0x0f, 0xa4, 0xf9, 0x86, 0x0f, 0xa4, 0xf9, 0x96, 0x0f, 0xa4, 0xf9, 0xd6, 0x0f, 0xa4, 0xf9, 0xaf, 0x0f, 0xa4, 0xf9, 0xbf, 0x0f, 0xa4, 0xf9, 0xff, 0x0f, 0xa4, 0xf9, 0xad, 0x0f, 0xa4, 0xf9, 0xbd, 0x0f, 0xa4, 0xf9, 0xfd, 0x0f, 0xa4, 0xf9, 0xa6, 0x0f, 0xa4, 0xf9, 0xb6, 0x0f, 0xa4, 0xf9, 0xf6, 0x0f, 0x04, 0xf9, 0x0f, 0x07, 0x04, 0xf9, 0x1f, 0x07, 0x04, 0xf9, 0x0d, 0x07, 0x04, 0xf9, 0x1d, 0x07, 0x04, 0xf9, 0x06, 0x07, 0x04, 0xf9, 0x16, 0x07, 0x04, 0xf9, 0x0f, 0x0a, 0x04, 0xf9, 0x1f, 0x0a, 0x04, 0xf9, 0x2f, 0x0a, 0x04, 0xf9, 0x0d, 0x0a, 0x04, 0xf9, 0x1d, 0x0a, 0x04, 0xf9, 0x2d, 0x0a, 0x04, 0xf9, 0x06, 0x0a, 0x04, 0xf9, 0x16, 0x0a, 0x04, 0xf9, 0x26, 0x0a, 0x04, 0xf9, 0x0f, 0x06, 0x04, 0xf9, 0x1f, 0x06, 0x04, 0xf9, 0x0d, 0x06, 0x04, 0xf9, 0x1d, 0x06, 0x04, 0xf9, 0x06, 0x06, 0x04, 0xf9, 0x16, 0x06, 0x04, 0xf9, 0x0f, 0x02, 0x04, 0xf9, 0x1f, 0x02, 0x04, 0xf9, 0x2f, 0x02, 0x04, 0xf9, 0x3f, 0x02, 0x04, 0xf9, 0x0d, 0x02, 0x04, 0xf9, 0x1d, 0x02, 0x04, 0xf9, 0x2d, 0x02, 0x04, 0xf9, 0x3d, 0x02, 0x04, 0xf9, 0x06, 0x02, 0x04, 0xf9, 0x16, 0x02, 0x04, 0xf9, 0x26, 0x02, 0x04, 0xf9, 0x36, 0x02, 0x84, 0xf9, 0x4f, 0x00, 0x84, 0xf9, 0x4d, 0x00, 0x84, 0xf9, 0x46, 0x00, 0x04, 0xf9, 0x4f, 0x07, 0x04, 0xf9, 0x5f, 0x07, 0x04, 0xf9, 0x4d, 0x07, 0x04, 0xf9, 0x5d, 0x07, 0x04, 0xf9, 0x46, 0x07, 0x04, 0xf9, 0x56, 0x07, 0x04, 0xf9, 0x4f, 0x0a, 0x04, 0xf9, 0x5f, 0x0a, 0x04, 0xf9, 0x6f, 0x0a, 0x04, 0xf9, 0x4d, 0x0a, 0x04, 0xf9, 0x5d, 0x0a, 0x04, 0xf9, 0x6d, 0x0a, 0x04, 0xf9, 0x46, 0x0a, 0x04, 0xf9, 0x56, 0x0a, 0x04, 0xf9, 0x66, 0x0a, 0x04, 0xf9, 0x4f, 0x06, 0x04, 0xf9, 0x5f, 0x06, 0x04, 0xf9, 0x4d, 0x06, 0x04, 0xf9, 0x5d, 0x06, 0x04, 0xf9, 0x46, 0x06, 0x04, 0xf9, 0x56, 0x06, 0x04, 0xf9, 0x4f, 0x02, 0x04, 0xf9, 0x5f, 0x02, 0x04, 0xf9, 0x6f, 0x02, 0x04, 0xf9, 0x7f, 0x02, 0x04, 0xf9, 0x4d, 0x02, 0x04, 0xf9, 0x5d, 0x02, 0x04, 0xf9, 0x6d, 0x02, 0x04, 0xf9, 0x7d, 0x02, 0x04, 0xf9, 0x46, 0x02, 0x04, 0xf9, 0x56, 0x02, 0x04, 0xf9, 0x66, 0x02, 0x04, 0xf9, 0x76, 0x02, 0x84, 0xf9, 0x8f, 0x04, 0x84, 0xf9, 0x9f, 0x04, 0x84, 0xf9, 0x8d, 0x04, 0x84, 0xf9, 0x9d, 0x04, 0x84, 0xf9, 0x86, 0x04, 0x84, 0xf9, 0x96, 0x04, 0x04, 0xf9, 0x8f, 0x07, 0x04, 0xf9, 0x9f, 0x07, 0x04, 0xf9, 0x8d, 0x07, 0x04, 0xf9, 0x9d, 0x07, 0x04, 0xf9, 0x86, 0x07, 0x04, 0xf9, 0x96, 0x07, 0x04, 0xf9, 0x8f, 0x0a, 0x04, 0xf9, 0x9f, 0x0a, 0x04, 0xf9, 0xaf, 0x0a, 0x04, 0xf9, 0x8d, 0x0a, 0x04, 0xf9, 0x9d, 0x0a, 0x04, 0xf9, 0xad, 0x0a, 0x04, 0xf9, 0x86, 0x0a, 0x04, 0xf9, 0x96, 0x0a, 0x04, 0xf9, 0xa6, 0x0a, 0x04, 0xf9, 0x8f, 0x06, 0x04, 0xf9, 0x9f, 0x06, 0x04, 0xf9, 0x8d, 0x06, 0x04, 0xf9, 0x9d, 0x06, 0x04, 0xf9, 0x86, 0x06, 0x04, 0xf9, 0x96, 0x06, 0x04, 0xf9, 0x8f, 0x02, 0x04, 0xf9, 0x9f, 0x02, 0x04, 0xf9, 0xaf, 0x02, 0x04, 0xf9, 0xbf, 0x02, 0x04, 0xf9, 0x8d, 0x02, 0x04, 0xf9, 0x9d, 0x02, 0x04, 0xf9, 0xad, 0x02, 0x04, 0xf9, 0xbd, 0x02, 0x04, 0xf9, 0x86, 0x02, 0x04, 0xf9, 0x96, 0x02, 0x04, 0xf9, 0xa6, 0x02, 0x04, 0xf9, 0xb6, 0x02, 0x84, 0xf9, 0x8f, 0x08, 0x84, 0xf9, 0xbf, 0x08, 0x84, 0xf9, 0x8d, 0x08, 0x84, 0xf9, 0xbd, 0x08, 0x84, 0xf9, 0x86, 0x08, 0x84, 0xf9, 0xb6, 0x08, 0x04, 0xf9, 0xcf, 0x07, 0x04, 0xf9, 0xdf, 0x07, 0x04, 0xf9, 0xcd, 0x07, 0x04, 0xf9, 0xdd, 0x07, 0x04, 0xf9, 0xc6, 0x07, 0x04, 0xf9, 0xd6, 0x07, 0x04, 0xf9, 0xcf, 0x0a, 0x04, 0xf9, 0xdf, 0x0a, 0x04, 0xf9, 0xef, 0x0a, 0x04, 0xf9, 0xcd, 0x0a, 0x04, 0xf9, 0xdd, 0x0a, 0x04, 0xf9, 0xed, 0x0a, 0x04, 0xf9, 0xc6, 0x0a, 0x04, 0xf9, 0xd6, 0x0a, 0x04, 0xf9, 0xe6, 0x0a, 0x04, 0xf9, 0xcf, 0x06, 0x04, 0xf9, 0xdf, 0x06, 0x04, 0xf9, 0xcd, 0x06, 0x04, 0xf9, 0xdd, 0x06, 0x04, 0xf9, 0xc6, 0x06, 0x04, 0xf9, 0xd6, 0x06, 0x04, 0xf9, 0xcf, 0x02, 0x04, 0xf9, 0xdf, 0x02, 0x04, 0xf9, 0xef, 0x02, 0x04, 0xf9, 0xff, 0x02, 0x04, 0xf9, 0xcd, 0x02, 0x04, 0xf9, 0xdd, 0x02, 0x04, 0xf9, 0xed, 0x02, 0x04, 0xf9, 0xfd, 0x02, 0x04, 0xf9, 0xc6, 0x02, 0x04, 0xf9, 0xd6, 0x02, 0x04, 0xf9, 0xe6, 0x02, 0x04, 0xf9, 0xf6, 0x02, 0x04, 0xf9, 0x0f, 0x08, 0x04, 0xf9, 0x1f, 0x08, 0x04, 0xf9, 0x2f, 0x08, 0x04, 0xf9, 0x0d, 0x08, 0x04, 0xf9, 0x1d, 0x08, 0x04, 0xf9, 0x2d, 0x08, 0x04, 0xf9, 0x06, 0x08, 0x04, 0xf9, 0x16, 0x08, 0x04, 0xf9, 0x26, 0x08, 0x04, 0xf9, 0x0f, 0x09, 0x04, 0xf9, 0x1f, 0x09, 0x04, 0xf9, 0x2f, 0x09, 0x04, 0xf9, 0x0d, 0x09, 0x04, 0xf9, 0x1d, 0x09, 0x04, 0xf9, 0x2d, 0x09, 0x04, 0xf9, 0x06, 0x09, 0x04, 0xf9, 0x16, 0x09, 0x04, 0xf9, 0x26, 0x09, 0x04, 0xf9, 0x0f, 0x03, 0x04, 0xf9, 0x1f, 0x03, 0x04, 0xf9, 0x2f, 0x03, 0x04, 0xf9, 0x3f, 0x03, 0x04, 0xf9, 0x0d, 0x03, 0x04, 0xf9, 0x1d, 0x03, 0x04, 0xf9, 0x2d, 0x03, 0x04, 0xf9, 0x3d, 0x03, 0x04, 0xf9, 0x06, 0x03, 0x04, 0xf9, 0x16, 0x03, 0x04, 0xf9, 0x26, 0x03, 0x04, 0xf9, 0x36, 0x03, 0x84, 0xf9, 0x4f, 0x01, 0x84, 0xf9, 0x5f, 0x01, 0x84, 0xf9, 0x4d, 0x01, 0x84, 0xf9, 0x5d, 0x01, 0x84, 0xf9, 0x46, 0x01, 0x84, 0xf9, 0x56, 0x01, 0x04, 0xf9, 0x8f, 0x08, 0x04, 0xf9, 0x9f, 0x08, 0x04, 0xf9, 0xaf, 0x08, 0x04, 0xf9, 0x8d, 0x08, 0x04, 0xf9, 0x9d, 0x08, 0x04, 0xf9, 0xad, 0x08, 0x04, 0xf9, 0x86, 0x08, 0x04, 0xf9, 0x96, 0x08, 0x04, 0xf9, 0xa6, 0x08, 0x04, 0xf9, 0x8f, 0x09, 0x04, 0xf9, 0x9f, 0x09, 0x04, 0xf9, 0xaf, 0x09, 0x04, 0xf9, 0x8d, 0x09, 0x04, 0xf9, 0x9d, 0x09, 0x04, 0xf9, 0xad, 0x09, 0x04, 0xf9, 0x86, 0x09, 0x04, 0xf9, 0x96, 0x09, 0x04, 0xf9, 0xa6, 0x09, 0x04, 0xf9, 0x8f, 0x03, 0x04, 0xf9, 0x9f, 0x03, 0x04, 0xf9, 0xaf, 0x03, 0x04, 0xf9, 0xbf, 0x03, 0x04, 0xf9, 0x8d, 0x03, 0x04, 0xf9, 0x9d, 0x03, 0x04, 0xf9, 0xad, 0x03, 0x04, 0xf9, 0xbd, 0x03, 0x04, 0xf9, 0x86, 0x03, 0x04, 0xf9, 0x96, 0x03, 0x04, 0xf9, 0xa6, 0x03, 0x04, 0xf9, 0xb6, 0x03, 0x84, 0xf9, 0x8f, 0x09, 0x84, 0xf9, 0x9f, 0x09, 0x84, 0xf9, 0x8d, 0x09, 0x84, 0xf9, 0x9d, 0x09, 0x84, 0xf9, 0x86, 0x09, 0x84, 0xf9, 0x96, 0x09, 0x84, 0xf9, 0xcf, 0x09, 0x84, 0xf9, 0xdf, 0x09, 0x84, 0xf9, 0xcd, 0x09, 0x84, 0xf9, 0xdd, 0x09, 0x84, 0xf9, 0xc6, 0x09, 0x84, 0xf9, 0xd6, 0x09, 0x04, 0xf9, 0x0f, 0x04, 0x04, 0xf9, 0x1f, 0x04, 0x04, 0xf9, 0x0d, 0x04, 0x04, 0xf9, 0x1d, 0x04, 0x04, 0xf9, 0x06, 0x04, 0x04, 0xf9, 0x16, 0x04, 0x04, 0xf9, 0x0f, 0x05, 0x04, 0xf9, 0x1f, 0x05, 0x04, 0xf9, 0x0d, 0x05, 0x04, 0xf9, 0x1d, 0x05, 0x04, 0xf9, 0x06, 0x05, 0x04, 0xf9, 0x16, 0x05, 0x84, 0xf9, 0x2f, 0x02, 0x84, 0xf9, 0x2d, 0x02, 0x84, 0xf9, 0x26, 0x02, 0x04, 0xf9, 0x4f, 0x04, 0x04, 0xf9, 0x5f, 0x04, 0x04, 0xf9, 0x4d, 0x04, 0x04, 0xf9, 0x5d, 0x04, 0x04, 0xf9, 0x46, 0x04, 0x04, 0xf9, 0x56, 0x04, 0x04, 0xf9, 0x4f, 0x05, 0x04, 0xf9, 0x5f, 0x05, 0x04, 0xf9, 0x4d, 0x05, 0x04, 0xf9, 0x5d, 0x05, 0x04, 0xf9, 0x46, 0x05, 0x04, 0xf9, 0x56, 0x05, 0x84, 0xf9, 0x4f, 0x06, 0x84, 0xf9, 0x4d, 0x06, 0x84, 0xf9, 0x46, 0x06, 0x84, 0xf9, 0x6f, 0x06, 0x84, 0xf9, 0x6d, 0x06, 0x84, 0xf9, 0x66, 0x06, 0x04, 0xf9, 0x8f, 0x04, 0x04, 0xf9, 0x9f, 0x04, 0x04, 0xf9, 0x8d, 0x04, 0x04, 0xf9, 0x9d, 0x04, 0x04, 0xf9, 0x86, 0x04, 0x04, 0xf9, 0x96, 0x04, 0x04, 0xf9, 0x8f, 0x05, 0x04, 0xf9, 0x9f, 0x05, 0x04, 0xf9, 0x8d, 0x05, 0x04, 0xf9, 0x9d, 0x05, 0x04, 0xf9, 0x86, 0x05, 0x04, 0xf9, 0x96, 0x05, 0x84, 0xf9, 0x8f, 0x0a, 0x84, 0xf9, 0x8d, 0x0a, 0x84, 0xf9, 0x86, 0x0a, 0x84, 0xf9, 0xcf, 0x0a, 0x84, 0xf9, 0xcd, 0x0a, 0x84, 0xf9, 0xc6, 0x0a, 0x04, 0xf9, 0x0f, 0x00, 0x04, 0xf9, 0x1f, 0x00, 0x04, 0xf9, 0x2f, 0x00, 0x04, 0xf9, 0x3f, 0x00, 0x04, 0xf9, 0x0d, 0x00, 0x04, 0xf9, 0x1d, 0x00, 0x04, 0xf9, 0x2d, 0x00, 0x04, 0xf9, 0x3d, 0x00, 0x04, 0xf9, 0x06, 0x00, 0x04, 0xf9, 0x16, 0x00, 0x04, 0xf9, 0x26, 0x00, 0x04, 0xf9, 0x36, 0x00, 0x04, 0xf9, 0x0f, 0x01, 0x04, 0xf9, 0x1f, 0x01, 0x04, 0xf9, 0x2f, 0x01, 0x04, 0xf9, 0x3f, 0x01, 0x04, 0xf9, 0x0d, 0x01, 0x04, 0xf9, 0x1d, 0x01, 0x04, 0xf9, 0x2d, 0x01, 0x04, 0xf9, 0x3d, 0x01, 0x04, 0xf9, 0x06, 0x01, 0x04, 0xf9, 0x16, 0x01, 0x04, 0xf9, 0x26, 0x01, 0x04, 0xf9, 0x36, 0x01, 0x84, 0xf9, 0x2f, 0x03, 0x84, 0xf9, 0x3f, 0x03, 0x84, 0xf9, 0x2d, 0x03, 0x84, 0xf9, 0x3d, 0x03, 0x84, 0xf9, 0x26, 0x03, 0x84, 0xf9, 0x36, 0x03, 0x04, 0xf9, 0x4f, 0x00, 0x04, 0xf9, 0x5f, 0x00, 0x04, 0xf9, 0x6f, 0x00, 0x04, 0xf9, 0x7f, 0x00, 0x04, 0xf9, 0x4d, 0x00, 0x04, 0xf9, 0x5d, 0x00, 0x04, 0xf9, 0x6d, 0x00, 0x04, 0xf9, 0x7d, 0x00, 0x04, 0xf9, 0x46, 0x00, 0x04, 0xf9, 0x56, 0x00, 0x04, 0xf9, 0x66, 0x00, 0x04, 0xf9, 0x76, 0x00, 0x04, 0xf9, 0x4f, 0x01, 0x04, 0xf9, 0x5f, 0x01, 0x04, 0xf9, 0x6f, 0x01, 0x04, 0xf9, 0x7f, 0x01, 0x04, 0xf9, 0x4d, 0x01, 0x04, 0xf9, 0x5d, 0x01, 0x04, 0xf9, 0x6d, 0x01, 0x04, 0xf9, 0x7d, 0x01, 0x04, 0xf9, 0x46, 0x01, 0x04, 0xf9, 0x56, 0x01, 0x04, 0xf9, 0x66, 0x01, 0x04, 0xf9, 0x76, 0x01, 0x84, 0xf9, 0x4f, 0x07, 0x84, 0xf9, 0x5f, 0x07, 0x84, 0xf9, 0x4d, 0x07, 0x84, 0xf9, 0x5d, 0x07, 0x84, 0xf9, 0x46, 0x07, 0x84, 0xf9, 0x56, 0x07, 0x84, 0xf9, 0x6f, 0x07, 0x84, 0xf9, 0x7f, 0x07, 0x84, 0xf9, 0x6d, 0x07, 0x84, 0xf9, 0x7d, 0x07, 0x84, 0xf9, 0x66, 0x07, 0x84, 0xf9, 0x76, 0x07, 0x04, 0xf9, 0x8f, 0x00, 0x04, 0xf9, 0x9f, 0x00, 0x04, 0xf9, 0xaf, 0x00, 0x04, 0xf9, 0xbf, 0x00, 0x04, 0xf9, 0x8d, 0x00, 0x04, 0xf9, 0x9d, 0x00, 0x04, 0xf9, 0xad, 0x00, 0x04, 0xf9, 0xbd, 0x00, 0x04, 0xf9, 0x86, 0x00, 0x04, 0xf9, 0x96, 0x00, 0x04, 0xf9, 0xa6, 0x00, 0x04, 0xf9, 0xb6, 0x00, 0x04, 0xf9, 0x8f, 0x01, 0x04, 0xf9, 0x9f, 0x01, 0x04, 0xf9, 0xaf, 0x01, 0x04, 0xf9, 0xbf, 0x01, 0x04, 0xf9, 0x8d, 0x01, 0x04, 0xf9, 0x9d, 0x01, 0x04, 0xf9, 0xad, 0x01, 0x04, 0xf9, 0xbd, 0x01, 0x04, 0xf9, 0x86, 0x01, 0x04, 0xf9, 0x96, 0x01, 0x04, 0xf9, 0xa6, 0x01, 0x04, 0xf9, 0xb6, 0x01, 0x84, 0xf9, 0x8f, 0x0b, 0x84, 0xf9, 0x9f, 0x0b, 0x84, 0xf9, 0xaf, 0x0b, 0x84, 0xf9, 0x8d, 0x0b, 0x84, 0xf9, 0x9d, 0x0b, 0x84, 0xf9, 0xad, 0x0b, 0x84, 0xf9, 0x86, 0x0b, 0x84, 0xf9, 0x96, 0x0b, 0x84, 0xf9, 0xa6, 0x0b, 0x84, 0xf9, 0xcf, 0x0b, 0x84, 0xf9, 0xdf, 0x0b, 0x84, 0xf9, 0xef, 0x0b, 0x84, 0xf9, 0xcd, 0x0b, 0x84, 0xf9, 0xdd, 0x0b, 0x84, 0xf9, 0xed, 0x0b, 0x84, 0xf9, 0xc6, 0x0b, 0x84, 0xf9, 0xd6, 0x0b, 0x84, 0xf9, 0xe6, 0x0b, 0x84, 0xf9, 0x8d, 0x0b, 0x84, 0xf9, 0x9d, 0x0b, 0x84, 0xf9, 0xad, 0x0b, 0x84, 0xf9, 0x86, 0x0b, 0x84, 0xf9, 0x96, 0x0b, 0x84, 0xf9, 0xa6, 0x0b, 0x84, 0xf9, 0xcf, 0x0b, 0x84, 0xf9, 0xdf, 0x0b, 0x84, 0xf9, 0xef, 0x0b, 0x84, 0xf9, 0xcd, 0x0b, 0x84, 0xf9, 0xdd, 0x0b, 0x84, 0xf9, 0xed, 0x0b, 0x84, 0xf9, 0xc6, 0x0b, 0x84, 0xf9, 0xd6, 0x0b, 0x84, 0xf9, 0xe6, 0x0b ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ]
+    expected:
+      insns:
+        -
+          asm_text: "vld1.8 {d0}, [r4]"
+        -
+          asm_text: "vld1.8 {d0}, [r4:64]"
+        -
+          asm_text: "vld1.8 {d0}, [r4]!"
+        -
+          asm_text: "vld1.8 {d0}, [r4:64]!"
+        -
+          asm_text: "vld1.8 {d0}, [r4], r6"
+        -
+          asm_text: "vld1.8 {d0}, [r4:64], r6"
+        -
+          asm_text: "vld1.8 {d0, d1}, [r4]"
+        -
+          asm_text: "vld1.8 {d0, d1}, [r4:64]"
+        -
+          asm_text: "vld1.8 {d0, d1}, [r4:128]"
+        -
+          asm_text: "vld1.8 {d0, d1}, [r4]!"
+        -
+          asm_text: "vld1.8 {d0, d1}, [r4:64]!"
+        -
+          asm_text: "vld1.8 {d0, d1}, [r4:128]!"
+        -
+          asm_text: "vld1.8 {d0, d1}, [r4], r6"
+        -
+          asm_text: "vld1.8 {d0, d1}, [r4:64], r6"
+        -
+          asm_text: "vld1.8 {d0, d1}, [r4:128], r6"
+        -
+          asm_text: "vld1.8 {d0, d1, d2}, [r4]"
+        -
+          asm_text: "vld1.8 {d0, d1, d2}, [r4:64]"
+        -
+          asm_text: "vld1.8 {d0, d1, d2}, [r4]!"
+        -
+          asm_text: "vld1.8 {d0, d1, d2}, [r4:64]!"
+        -
+          asm_text: "vld1.8 {d0, d1, d2}, [r4], r6"
+        -
+          asm_text: "vld1.8 {d0, d1, d2}, [r4:64], r6"
+        -
+          asm_text: "vld1.8 {d0, d1, d2, d3}, [r4]"
+        -
+          asm_text: "vld1.8 {d0, d1, d2, d3}, [r4:64]"
+        -
+          asm_text: "vld1.8 {d0, d1, d2, d3}, [r4:128]"
+        -
+          asm_text: "vld1.8 {d0, d1, d2, d3}, [r4:256]"
+        -
+          asm_text: "vld1.8 {d0, d1, d2, d3}, [r4]!"
+        -
+          asm_text: "vld1.8 {d0, d1, d2, d3}, [r4:64]!"
+        -
+          asm_text: "vld1.8 {d0, d1, d2, d3}, [r4:128]!"
+        -
+          asm_text: "vld1.8 {d0, d1, d2, d3}, [r4:256]!"
+        -
+          asm_text: "vld1.8 {d0, d1, d2, d3}, [r4], r6"
+        -
+          asm_text: "vld1.8 {d0, d1, d2, d3}, [r4:64], r6"
+        -
+          asm_text: "vld1.8 {d0, d1, d2, d3}, [r4:128], r6"
+        -
+          asm_text: "vld1.8 {d0, d1, d2, d3}, [r4:256], r6"
+        -
+          asm_text: "vld1.8 {d0[2]}, [r4]"
+        -
+          asm_text: "vld1.8 {d0[2]}, [r4]!"
+        -
+          asm_text: "vld1.8 {d0[2]}, [r4], r6"
+        -
+          asm_text: "vld1.8 {d0[]}, [r4]"
+        -
+          asm_text: "vld1.8 {d0[]}, [r4]!"
+        -
+          asm_text: "vld1.8 {d0[]}, [r4], r6"
+        -
+          asm_text: "vld1.8 {d0[], d1[]}, [r4]"
+        -
+          asm_text: "vld1.8 {d0[], d1[]}, [r4]!"
+        -
+          asm_text: "vld1.8 {d0[], d1[]}, [r4], r6"
+        -
+          asm_text: "vld1.16 {d0}, [r4]"
+        -
+          asm_text: "vld1.16 {d0}, [r4:64]"
+        -
+          asm_text: "vld1.16 {d0}, [r4]!"
+        -
+          asm_text: "vld1.16 {d0}, [r4:64]!"
+        -
+          asm_text: "vld1.16 {d0}, [r4], r6"
+        -
+          asm_text: "vld1.16 {d0}, [r4:64], r6"
+        -
+          asm_text: "vld1.16 {d0, d1}, [r4]"
+        -
+          asm_text: "vld1.16 {d0, d1}, [r4:64]"
+        -
+          asm_text: "vld1.16 {d0, d1}, [r4:128]"
+        -
+          asm_text: "vld1.16 {d0, d1}, [r4]!"
+        -
+          asm_text: "vld1.16 {d0, d1}, [r4:64]!"
+        -
+          asm_text: "vld1.16 {d0, d1}, [r4:128]!"
+        -
+          asm_text: "vld1.16 {d0, d1}, [r4], r6"
+        -
+          asm_text: "vld1.16 {d0, d1}, [r4:64], r6"
+        -
+          asm_text: "vld1.16 {d0, d1}, [r4:128], r6"
+        -
+          asm_text: "vld1.16 {d0, d1, d2}, [r4]"
+        -
+          asm_text: "vld1.16 {d0, d1, d2}, [r4:64]"
+        -
+          asm_text: "vld1.16 {d0, d1, d2}, [r4]!"
+        -
+          asm_text: "vld1.16 {d0, d1, d2}, [r4:64]!"
+        -
+          asm_text: "vld1.16 {d0, d1, d2}, [r4], r6"
+        -
+          asm_text: "vld1.16 {d0, d1, d2}, [r4:64], r6"
+        -
+          asm_text: "vld1.16 {d0, d1, d2, d3}, [r4]"
+        -
+          asm_text: "vld1.16 {d0, d1, d2, d3}, [r4:64]"
+        -
+          asm_text: "vld1.16 {d0, d1, d2, d3}, [r4:128]"
+        -
+          asm_text: "vld1.16 {d0, d1, d2, d3}, [r4:256]"
+        -
+          asm_text: "vld1.16 {d0, d1, d2, d3}, [r4]!"
+        -
+          asm_text: "vld1.16 {d0, d1, d2, d3}, [r4:64]!"
+        -
+          asm_text: "vld1.16 {d0, d1, d2, d3}, [r4:128]!"
+        -
+          asm_text: "vld1.16 {d0, d1, d2, d3}, [r4:256]!"
+        -
+          asm_text: "vld1.16 {d0, d1, d2, d3}, [r4], r6"
+        -
+          asm_text: "vld1.16 {d0, d1, d2, d3}, [r4:64], r6"
+        -
+          asm_text: "vld1.16 {d0, d1, d2, d3}, [r4:128], r6"
+        -
+          asm_text: "vld1.16 {d0, d1, d2, d3}, [r4:256], r6"
+        -
+          asm_text: "vld1.16 {d0[2]}, [r4]"
+        -
+          asm_text: "vld1.16 {d0[2]}, [r4:16]"
+        -
+          asm_text: "vld1.16 {d0[2]}, [r4]!"
+        -
+          asm_text: "vld1.16 {d0[2]}, [r4:16]!"
+        -
+          asm_text: "vld1.16 {d0[2]}, [r4], r6"
+        -
+          asm_text: "vld1.16 {d0[2]}, [r4:16], r6"
+        -
+          asm_text: "vld1.16 {d0[]}, [r4]"
+        -
+          asm_text: "vld1.16 {d0[]}, [r4:16]"
+        -
+          asm_text: "vld1.16 {d0[]}, [r4]!"
+        -
+          asm_text: "vld1.16 {d0[]}, [r4:16]!"
+        -
+          asm_text: "vld1.16 {d0[]}, [r4], r6"
+        -
+          asm_text: "vld1.16 {d0[]}, [r4:16], r6"
+        -
+          asm_text: "vld1.16 {d0[], d1[]}, [r4]"
+        -
+          asm_text: "vld1.16 {d0[], d1[]}, [r4:16]"
+        -
+          asm_text: "vld1.16 {d0[], d1[]}, [r4]!"
+        -
+          asm_text: "vld1.16 {d0[], d1[]}, [r4:16]!"
+        -
+          asm_text: "vld1.16 {d0[], d1[]}, [r4], r6"
+        -
+          asm_text: "vld1.16 {d0[], d1[]}, [r4:16], r6"
+        -
+          asm_text: "vld1.32 {d0}, [r4]"
+        -
+          asm_text: "vld1.32 {d0}, [r4:64]"
+        -
+          asm_text: "vld1.32 {d0}, [r4]!"
+        -
+          asm_text: "vld1.32 {d0}, [r4:64]!"
+        -
+          asm_text: "vld1.32 {d0}, [r4], r6"
+        -
+          asm_text: "vld1.32 {d0}, [r4:64], r6"
+        -
+          asm_text: "vld1.32 {d0, d1}, [r4]"
+        -
+          asm_text: "vld1.32 {d0, d1}, [r4:64]"
+        -
+          asm_text: "vld1.32 {d0, d1}, [r4:128]"
+        -
+          asm_text: "vld1.32 {d0, d1}, [r4]!"
+        -
+          asm_text: "vld1.32 {d0, d1}, [r4:64]!"
+        -
+          asm_text: "vld1.32 {d0, d1}, [r4:128]!"
+        -
+          asm_text: "vld1.32 {d0, d1}, [r4], r6"
+        -
+          asm_text: "vld1.32 {d0, d1}, [r4:64], r6"
+        -
+          asm_text: "vld1.32 {d0, d1}, [r4:128], r6"
+        -
+          asm_text: "vld1.32 {d0, d1, d2}, [r4]"
+        -
+          asm_text: "vld1.32 {d0, d1, d2}, [r4:64]"
+        -
+          asm_text: "vld1.32 {d0, d1, d2}, [r4]!"
+        -
+          asm_text: "vld1.32 {d0, d1, d2}, [r4:64]!"
+        -
+          asm_text: "vld1.32 {d0, d1, d2}, [r4], r6"
+        -
+          asm_text: "vld1.32 {d0, d1, d2}, [r4:64], r6"
+        -
+          asm_text: "vld1.32 {d0, d1, d2, d3}, [r4]"
+        -
+          asm_text: "vld1.32 {d0, d1, d2, d3}, [r4:64]"
+        -
+          asm_text: "vld1.32 {d0, d1, d2, d3}, [r4:128]"
+        -
+          asm_text: "vld1.32 {d0, d1, d2, d3}, [r4:256]"
+        -
+          asm_text: "vld1.32 {d0, d1, d2, d3}, [r4]!"
+        -
+          asm_text: "vld1.32 {d0, d1, d2, d3}, [r4:64]!"
+        -
+          asm_text: "vld1.32 {d0, d1, d2, d3}, [r4:128]!"
+        -
+          asm_text: "vld1.32 {d0, d1, d2, d3}, [r4:256]!"
+        -
+          asm_text: "vld1.32 {d0, d1, d2, d3}, [r4], r6"
+        -
+          asm_text: "vld1.32 {d0, d1, d2, d3}, [r4:64], r6"
+        -
+          asm_text: "vld1.32 {d0, d1, d2, d3}, [r4:128], r6"
+        -
+          asm_text: "vld1.32 {d0, d1, d2, d3}, [r4:256], r6"
+        -
+          asm_text: "vld1.32 {d0[1]}, [r4]"
+        -
+          asm_text: "vld1.32 {d0[1]}, [r4:32]"
+        -
+          asm_text: "vld1.32 {d0[1]}, [r4]!"
+        -
+          asm_text: "vld1.32 {d0[1]}, [r4:32]!"
+        -
+          asm_text: "vld1.32 {d0[1]}, [r4], r6"
+        -
+          asm_text: "vld1.32 {d0[1]}, [r4:32], r6"
+        -
+          asm_text: "vld1.32 {d0[]}, [r4]"
+        -
+          asm_text: "vld1.32 {d0[]}, [r4:32]"
+        -
+          asm_text: "vld1.32 {d0[]}, [r4]!"
+        -
+          asm_text: "vld1.32 {d0[]}, [r4:32]!"
+        -
+          asm_text: "vld1.32 {d0[]}, [r4], r6"
+        -
+          asm_text: "vld1.32 {d0[]}, [r4:32], r6"
+        -
+          asm_text: "vld1.32 {d0[], d1[]}, [r4]"
+        -
+          asm_text: "vld1.32 {d0[], d1[]}, [r4:32]"
+        -
+          asm_text: "vld1.32 {d0[], d1[]}, [r4]!"
+        -
+          asm_text: "vld1.32 {d0[], d1[]}, [r4:32]!"
+        -
+          asm_text: "vld1.32 {d0[], d1[]}, [r4], r6"
+        -
+          asm_text: "vld1.32 {d0[], d1[]}, [r4:32], r6"
+        -
+          asm_text: "vld1.32 {d0[1]}, [r4]"
+        -
+          asm_text: "vld1.32 {d0[1]}, [r4:32]"
+        -
+          asm_text: "vld1.32 {d0[1]}, [r4]!"
+        -
+          asm_text: "vld1.32 {d0[1]}, [r4:32]!"
+        -
+          asm_text: "vld1.32 {d0[1]}, [r4], r6"
+        -
+          asm_text: "vld1.32 {d0[1]}, [r4:32], r6"
+        -
+          asm_text: "vld1.64 {d0}, [r4]"
+        -
+          asm_text: "vld1.64 {d0}, [r4:64]"
+        -
+          asm_text: "vld1.64 {d0}, [r4]!"
+        -
+          asm_text: "vld1.64 {d0}, [r4:64]!"
+        -
+          asm_text: "vld1.64 {d0}, [r4], r6"
+        -
+          asm_text: "vld1.64 {d0}, [r4:64], r6"
+        -
+          asm_text: "vld1.64 {d0, d1}, [r4]"
+        -
+          asm_text: "vld1.64 {d0, d1}, [r4:64]"
+        -
+          asm_text: "vld1.64 {d0, d1}, [r4:128]"
+        -
+          asm_text: "vld1.64 {d0, d1}, [r4]!"
+        -
+          asm_text: "vld1.64 {d0, d1}, [r4:64]!"
+        -
+          asm_text: "vld1.64 {d0, d1}, [r4:128]!"
+        -
+          asm_text: "vld1.64 {d0, d1}, [r4], r6"
+        -
+          asm_text: "vld1.64 {d0, d1}, [r4:64], r6"
+        -
+          asm_text: "vld1.64 {d0, d1}, [r4:128], r6"
+        -
+          asm_text: "vld1.64 {d0, d1, d2}, [r4]"
+        -
+          asm_text: "vld1.64 {d0, d1, d2}, [r4:64]"
+        -
+          asm_text: "vld1.64 {d0, d1, d2}, [r4]!"
+        -
+          asm_text: "vld1.64 {d0, d1, d2}, [r4:64]!"
+        -
+          asm_text: "vld1.64 {d0, d1, d2}, [r4], r6"
+        -
+          asm_text: "vld1.64 {d0, d1, d2}, [r4:64], r6"
+        -
+          asm_text: "vld1.64 {d0, d1, d2, d3}, [r4]"
+        -
+          asm_text: "vld1.64 {d0, d1, d2, d3}, [r4:64]"
+        -
+          asm_text: "vld1.64 {d0, d1, d2, d3}, [r4:128]"
+        -
+          asm_text: "vld1.64 {d0, d1, d2, d3}, [r4:256]"
+        -
+          asm_text: "vld1.64 {d0, d1, d2, d3}, [r4]!"
+        -
+          asm_text: "vld1.64 {d0, d1, d2, d3}, [r4:64]!"
+        -
+          asm_text: "vld1.64 {d0, d1, d2, d3}, [r4:128]!"
+        -
+          asm_text: "vld1.64 {d0, d1, d2, d3}, [r4:256]!"
+        -
+          asm_text: "vld1.64 {d0, d1, d2, d3}, [r4], r6"
+        -
+          asm_text: "vld1.64 {d0, d1, d2, d3}, [r4:64], r6"
+        -
+          asm_text: "vld1.64 {d0, d1, d2, d3}, [r4:128], r6"
+        -
+          asm_text: "vld1.64 {d0, d1, d2, d3}, [r4:256], r6"
+        -
+          asm_text: "vld2.8 {d0, d1}, [r4]"
+        -
+          asm_text: "vld2.8 {d0, d1}, [r4:64]"
+        -
+          asm_text: "vld2.8 {d0, d1}, [r4:128]"
+        -
+          asm_text: "vld2.8 {d0, d1}, [r4]!"
+        -
+          asm_text: "vld2.8 {d0, d1}, [r4:64]!"
+        -
+          asm_text: "vld2.8 {d0, d1}, [r4:128]!"
+        -
+          asm_text: "vld2.8 {d0, d1}, [r4], r6"
+        -
+          asm_text: "vld2.8 {d0, d1}, [r4:64], r6"
+        -
+          asm_text: "vld2.8 {d0, d1}, [r4:128], r6"
+        -
+          asm_text: "vld2.8 {d0, d2}, [r4]"
+        -
+          asm_text: "vld2.8 {d0, d2}, [r4:64]"
+        -
+          asm_text: "vld2.8 {d0, d2}, [r4:128]"
+        -
+          asm_text: "vld2.8 {d0, d2}, [r4]!"
+        -
+          asm_text: "vld2.8 {d0, d2}, [r4:64]!"
+        -
+          asm_text: "vld2.8 {d0, d2}, [r4:128]!"
+        -
+          asm_text: "vld2.8 {d0, d2}, [r4], r6"
+        -
+          asm_text: "vld2.8 {d0, d2}, [r4:64], r6"
+        -
+          asm_text: "vld2.8 {d0, d2}, [r4:128], r6"
+        -
+          asm_text: "vld2.8 {d0, d1, d2, d3}, [r4]"
+        -
+          asm_text: "vld2.8 {d0, d1, d2, d3}, [r4:64]"
+        -
+          asm_text: "vld2.8 {d0, d1, d2, d3}, [r4:128]"
+        -
+          asm_text: "vld2.8 {d0, d1, d2, d3}, [r4:256]"
+        -
+          asm_text: "vld2.8 {d0, d1, d2, d3}, [r4]!"
+        -
+          asm_text: "vld2.8 {d0, d1, d2, d3}, [r4:64]!"
+        -
+          asm_text: "vld2.8 {d0, d1, d2, d3}, [r4:128]!"
+        -
+          asm_text: "vld2.8 {d0, d1, d2, d3}, [r4:256]!"
+        -
+          asm_text: "vld2.8 {d0, d1, d2, d3}, [r4], r6"
+        -
+          asm_text: "vld2.8 {d0, d1, d2, d3}, [r4:64], r6"
+        -
+          asm_text: "vld2.8 {d0, d1, d2, d3}, [r4:128], r6"
+        -
+          asm_text: "vld2.8 {d0, d1, d2, d3}, [r4:256], r6"
+        -
+          asm_text: "vld2.8 {d0[2], d1[2]}, [r4]"
+        -
+          asm_text: "vld2.8 {d0[2], d1[2]}, [r4:16]"
+        -
+          asm_text: "vld2.8 {d0[2], d1[2]}, [r4]!"
+        -
+          asm_text: "vld2.8 {d0[2], d1[2]}, [r4:16]!"
+        -
+          asm_text: "vld2.8 {d0[2], d1[2]}, [r4], r6"
+        -
+          asm_text: "vld2.8 {d0[2], d1[2]}, [r4:16], r6"
+        -
+          asm_text: "vld2.8 {d0[], d1[]}, [r4]"
+        -
+          asm_text: "vld2.8 {d0[], d1[]}, [r4:16]"
+        -
+          asm_text: "vld2.8 {d0[], d1[]}, [r4]!"
+        -
+          asm_text: "vld2.8 {d0[], d1[]}, [r4:16]!"
+        -
+          asm_text: "vld2.8 {d0[], d1[]}, [r4], r6"
+        -
+          asm_text: "vld2.8 {d0[], d1[]}, [r4:16], r6"
+        -
+          asm_text: "vld2.8 {d0[], d2[]}, [r4]"
+        -
+          asm_text: "vld2.8 {d0[], d2[]}, [r4:16]"
+        -
+          asm_text: "vld2.8 {d0[], d2[]}, [r4]!"
+        -
+          asm_text: "vld2.8 {d0[], d2[]}, [r4:16]!"
+        -
+          asm_text: "vld2.8 {d0[], d2[]}, [r4], r6"
+        -
+          asm_text: "vld2.8 {d0[], d2[]}, [r4:16], r6"
+        -
+          asm_text: "vld2.16 {d0, d1}, [r4]"
+        -
+          asm_text: "vld2.16 {d0, d1}, [r4:64]"
+        -
+          asm_text: "vld2.16 {d0, d1}, [r4:128]"
+        -
+          asm_text: "vld2.16 {d0, d1}, [r4]!"
+        -
+          asm_text: "vld2.16 {d0, d1}, [r4:64]!"
+        -
+          asm_text: "vld2.16 {d0, d1}, [r4:128]!"
+        -
+          asm_text: "vld2.16 {d0, d1}, [r4], r6"
+        -
+          asm_text: "vld2.16 {d0, d1}, [r4:64], r6"
+        -
+          asm_text: "vld2.16 {d0, d1}, [r4:128], r6"
+        -
+          asm_text: "vld2.16 {d0, d2}, [r4]"
+        -
+          asm_text: "vld2.16 {d0, d2}, [r4:64]"
+        -
+          asm_text: "vld2.16 {d0, d2}, [r4:128]"
+        -
+          asm_text: "vld2.16 {d0, d2}, [r4]!"
+        -
+          asm_text: "vld2.16 {d0, d2}, [r4:64]!"
+        -
+          asm_text: "vld2.16 {d0, d2}, [r4:128]!"
+        -
+          asm_text: "vld2.16 {d0, d2}, [r4], r6"
+        -
+          asm_text: "vld2.16 {d0, d2}, [r4:64], r6"
+        -
+          asm_text: "vld2.16 {d0, d2}, [r4:128], r6"
+        -
+          asm_text: "vld2.16 {d0, d1, d2, d3}, [r4]"
+        -
+          asm_text: "vld2.16 {d0, d1, d2, d3}, [r4:64]"
+        -
+          asm_text: "vld2.16 {d0, d1, d2, d3}, [r4:128]"
+        -
+          asm_text: "vld2.16 {d0, d1, d2, d3}, [r4:256]"
+        -
+          asm_text: "vld2.16 {d0, d1, d2, d3}, [r4]!"
+        -
+          asm_text: "vld2.16 {d0, d1, d2, d3}, [r4:64]!"
+        -
+          asm_text: "vld2.16 {d0, d1, d2, d3}, [r4:128]!"
+        -
+          asm_text: "vld2.16 {d0, d1, d2, d3}, [r4:256]!"
+        -
+          asm_text: "vld2.16 {d0, d1, d2, d3}, [r4], r6"
+        -
+          asm_text: "vld2.16 {d0, d1, d2, d3}, [r4:64], r6"
+        -
+          asm_text: "vld2.16 {d0, d1, d2, d3}, [r4:128], r6"
+        -
+          asm_text: "vld2.16 {d0, d1, d2, d3}, [r4:256], r6"
+        -
+          asm_text: "vld2.16 {d0[2], d1[2]}, [r4]"
+        -
+          asm_text: "vld2.16 {d0[2], d1[2]}, [r4:32]"
+        -
+          asm_text: "vld2.16 {d0[2], d1[2]}, [r4]!"
+        -
+          asm_text: "vld2.16 {d0[2], d1[2]}, [r4:32]!"
+        -
+          asm_text: "vld2.16 {d0[2], d1[2]}, [r4], r6"
+        -
+          asm_text: "vld2.16 {d0[2], d1[2]}, [r4:32], r6"
+        -
+          asm_text: "vld2.16 {d0[2], d2[2]}, [r4]"
+        -
+          asm_text: "vld2.16 {d0[2], d2[2]}, [r4:32]"
+        -
+          asm_text: "vld2.16 {d0[2], d2[2]}, [r4]!"
+        -
+          asm_text: "vld2.16 {d0[2], d2[2]}, [r4:32]!"
+        -
+          asm_text: "vld2.16 {d0[2], d2[2]}, [r4], r6"
+        -
+          asm_text: "vld2.16 {d0[2], d2[2]}, [r4:32], r6"
+        -
+          asm_text: "vld2.16 {d0[], d1[]}, [r4]"
+        -
+          asm_text: "vld2.16 {d0[], d1[]}, [r4:32]"
+        -
+          asm_text: "vld2.16 {d0[], d1[]}, [r4]!"
+        -
+          asm_text: "vld2.16 {d0[], d1[]}, [r4:32]!"
+        -
+          asm_text: "vld2.16 {d0[], d1[]}, [r4], r6"
+        -
+          asm_text: "vld2.16 {d0[], d1[]}, [r4:32], r6"
+        -
+          asm_text: "vld2.16 {d0[], d2[]}, [r4]"
+        -
+          asm_text: "vld2.16 {d0[], d2[]}, [r4:32]"
+        -
+          asm_text: "vld2.16 {d0[], d2[]}, [r4]!"
+        -
+          asm_text: "vld2.16 {d0[], d2[]}, [r4:32]!"
+        -
+          asm_text: "vld2.16 {d0[], d2[]}, [r4], r6"
+        -
+          asm_text: "vld2.16 {d0[], d2[]}, [r4:32], r6"
+        -
+          asm_text: "vld2.32 {d0, d1}, [r4]"
+        -
+          asm_text: "vld2.32 {d0, d1}, [r4:64]"
+        -
+          asm_text: "vld2.32 {d0, d1}, [r4:128]"
+        -
+          asm_text: "vld2.32 {d0, d1}, [r4]!"
+        -
+          asm_text: "vld2.32 {d0, d1}, [r4:64]!"
+        -
+          asm_text: "vld2.32 {d0, d1}, [r4:128]!"
+        -
+          asm_text: "vld2.32 {d0, d1}, [r4], r6"
+        -
+          asm_text: "vld2.32 {d0, d1}, [r4:64], r6"
+        -
+          asm_text: "vld2.32 {d0, d1}, [r4:128], r6"
+        -
+          asm_text: "vld2.32 {d0, d2}, [r4]"
+        -
+          asm_text: "vld2.32 {d0, d2}, [r4:64]"
+        -
+          asm_text: "vld2.32 {d0, d2}, [r4:128]"
+        -
+          asm_text: "vld2.32 {d0, d2}, [r4]!"
+        -
+          asm_text: "vld2.32 {d0, d2}, [r4:64]!"
+        -
+          asm_text: "vld2.32 {d0, d2}, [r4:128]!"
+        -
+          asm_text: "vld2.32 {d0, d2}, [r4], r6"
+        -
+          asm_text: "vld2.32 {d0, d2}, [r4:64], r6"
+        -
+          asm_text: "vld2.32 {d0, d2}, [r4:128], r6"
+        -
+          asm_text: "vld2.32 {d0, d1, d2, d3}, [r4]"
+        -
+          asm_text: "vld2.32 {d0, d1, d2, d3}, [r4:64]"
+        -
+          asm_text: "vld2.32 {d0, d1, d2, d3}, [r4:128]"
+        -
+          asm_text: "vld2.32 {d0, d1, d2, d3}, [r4:256]"
+        -
+          asm_text: "vld2.32 {d0, d1, d2, d3}, [r4]!"
+        -
+          asm_text: "vld2.32 {d0, d1, d2, d3}, [r4:64]!"
+        -
+          asm_text: "vld2.32 {d0, d1, d2, d3}, [r4:128]!"
+        -
+          asm_text: "vld2.32 {d0, d1, d2, d3}, [r4:256]!"
+        -
+          asm_text: "vld2.32 {d0, d1, d2, d3}, [r4], r6"
+        -
+          asm_text: "vld2.32 {d0, d1, d2, d3}, [r4:64], r6"
+        -
+          asm_text: "vld2.32 {d0, d1, d2, d3}, [r4:128], r6"
+        -
+          asm_text: "vld2.32 {d0, d1, d2, d3}, [r4:256], r6"
+        -
+          asm_text: "vld2.32 {d0[1], d1[1]}, [r4]"
+        -
+          asm_text: "vld2.32 {d0[1], d1[1]}, [r4:64]"
+        -
+          asm_text: "vld2.32 {d0[1], d1[1]}, [r4]!"
+        -
+          asm_text: "vld2.32 {d0[1], d1[1]}, [r4:64]!"
+        -
+          asm_text: "vld2.32 {d0[1], d1[1]}, [r4], r6"
+        -
+          asm_text: "vld2.32 {d0[1], d1[1]}, [r4:64], r6"
+        -
+          asm_text: "vld2.32 {d0[1], d2[1]}, [r4]"
+        -
+          asm_text: "vld2.32 {d0[1], d2[1]}, [r4:64]"
+        -
+          asm_text: "vld2.32 {d0[1], d2[1]}, [r4]!"
+        -
+          asm_text: "vld2.32 {d0[1], d2[1]}, [r4:64]!"
+        -
+          asm_text: "vld2.32 {d0[1], d2[1]}, [r4], r6"
+        -
+          asm_text: "vld2.32 {d0[1], d2[1]}, [r4:64], r6"
+        -
+          asm_text: "vld2.32 {d0[], d1[]}, [r4]"
+        -
+          asm_text: "vld2.32 {d0[], d1[]}, [r4:64]"
+        -
+          asm_text: "vld2.32 {d0[], d1[]}, [r4]!"
+        -
+          asm_text: "vld2.32 {d0[], d1[]}, [r4:64]!"
+        -
+          asm_text: "vld2.32 {d0[], d1[]}, [r4], r6"
+        -
+          asm_text: "vld2.32 {d0[], d1[]}, [r4:64], r6"
+        -
+          asm_text: "vld2.32 {d0[], d2[]}, [r4]"
+        -
+          asm_text: "vld2.32 {d0[], d2[]}, [r4:64]"
+        -
+          asm_text: "vld2.32 {d0[], d2[]}, [r4]!"
+        -
+          asm_text: "vld2.32 {d0[], d2[]}, [r4:64]!"
+        -
+          asm_text: "vld2.32 {d0[], d2[]}, [r4], r6"
+        -
+          asm_text: "vld2.32 {d0[], d2[]}, [r4:64], r6"
+        -
+          asm_text: "vld3.8 {d0, d1, d2}, [r4]"
+        -
+          asm_text: "vld3.8 {d0, d1, d2}, [r4:64]"
+        -
+          asm_text: "vld3.8 {d0, d1, d2}, [r4]!"
+        -
+          asm_text: "vld3.8 {d0, d1, d2}, [r4:64]!"
+        -
+          asm_text: "vld3.8 {d0, d1, d2}, [r4], r6"
+        -
+          asm_text: "vld3.8 {d0, d1, d2}, [r4:64], r6"
+        -
+          asm_text: "vld3.8 {d0, d2, d4}, [r4]"
+        -
+          asm_text: "vld3.8 {d0, d2, d4}, [r4:64]"
+        -
+          asm_text: "vld3.8 {d0, d2, d4}, [r4]!"
+        -
+          asm_text: "vld3.8 {d0, d2, d4}, [r4:64]!"
+        -
+          asm_text: "vld3.8 {d0, d2, d4}, [r4], r6"
+        -
+          asm_text: "vld3.8 {d0, d2, d4}, [r4:64], r6"
+        -
+          asm_text: "vld3.8 {d0[1], d1[1], d2[1]}, [r4]"
+        -
+          asm_text: "vld3.8 {d0[1], d1[1], d2[1]}, [r4]!"
+        -
+          asm_text: "vld3.8 {d0[1], d1[1], d2[1]}, [r4], r6"
+        -
+          asm_text: "vld3.8 {d0[], d1[], d2[]}, [r4]"
+        -
+          asm_text: "vld3.8 {d0[], d1[], d2[]}, [r4]!"
+        -
+          asm_text: "vld3.8 {d0[], d1[], d2[]}, [r4], r6"
+        -
+          asm_text: "vld3.8 {d0[], d2[], d4[]}, [r4]"
+        -
+          asm_text: "vld3.8 {d0[], d2[], d4[]}, [r4]!"
+        -
+          asm_text: "vld3.8 {d0[], d2[], d4[]}, [r4], r6"
+        -
+          asm_text: "vld3.16 {d0, d1, d2}, [r4]"
+        -
+          asm_text: "vld3.16 {d0, d1, d2}, [r4:64]"
+        -
+          asm_text: "vld3.16 {d0, d1, d2}, [r4]!"
+        -
+          asm_text: "vld3.16 {d0, d1, d2}, [r4:64]!"
+        -
+          asm_text: "vld3.16 {d0, d1, d2}, [r4], r6"
+        -
+          asm_text: "vld3.16 {d0, d1, d2}, [r4:64], r6"
+        -
+          asm_text: "vld3.16 {d0, d2, d4}, [r4]"
+        -
+          asm_text: "vld3.16 {d0, d2, d4}, [r4:64]"
+        -
+          asm_text: "vld3.16 {d0, d2, d4}, [r4]!"
+        -
+          asm_text: "vld3.16 {d0, d2, d4}, [r4:64]!"
+        -
+          asm_text: "vld3.16 {d0, d2, d4}, [r4], r6"
+        -
+          asm_text: "vld3.16 {d0, d2, d4}, [r4:64], r6"
+        -
+          asm_text: "vld3.16 {d0[1], d1[1], d2[1]}, [r4]"
+        -
+          asm_text: "vld3.16 {d0[1], d1[1], d2[1]}, [r4]!"
+        -
+          asm_text: "vld3.16 {d0[1], d1[1], d2[1]}, [r4], r6"
+        -
+          asm_text: "vld3.16 {d0[1], d2[1], d4[1]}, [r4]"
+        -
+          asm_text: "vld3.16 {d0[1], d2[1], d4[1]}, [r4]!"
+        -
+          asm_text: "vld3.16 {d0[1], d2[1], d4[1]}, [r4], r6"
+        -
+          asm_text: "vld3.16 {d0[], d1[], d2[]}, [r4]"
+        -
+          asm_text: "vld3.16 {d0[], d1[], d2[]}, [r4]!"
+        -
+          asm_text: "vld3.16 {d0[], d1[], d2[]}, [r4], r6"
+        -
+          asm_text: "vld3.16 {d0[], d2[], d4[]}, [r4]"
+        -
+          asm_text: "vld3.16 {d0[], d2[], d4[]}, [r4]!"
+        -
+          asm_text: "vld3.16 {d0[], d2[], d4[]}, [r4], r6"
+        -
+          asm_text: "vld3.32 {d0, d1, d2}, [r4]"
+        -
+          asm_text: "vld3.32 {d0, d1, d2}, [r4:64]"
+        -
+          asm_text: "vld3.32 {d0, d1, d2}, [r4]!"
+        -
+          asm_text: "vld3.32 {d0, d1, d2}, [r4:64]!"
+        -
+          asm_text: "vld3.32 {d0, d1, d2}, [r4], r6"
+        -
+          asm_text: "vld3.32 {d0, d1, d2}, [r4:64], r6"
+        -
+          asm_text: "vld3.32 {d0, d2, d4}, [r4]"
+        -
+          asm_text: "vld3.32 {d0, d2, d4}, [r4:64]"
+        -
+          asm_text: "vld3.32 {d0, d2, d4}, [r4]!"
+        -
+          asm_text: "vld3.32 {d0, d2, d4}, [r4:64]!"
+        -
+          asm_text: "vld3.32 {d0, d2, d4}, [r4], r6"
+        -
+          asm_text: "vld3.32 {d0, d2, d4}, [r4:64], r6"
+        -
+          asm_text: "vld3.32 {d0[1], d1[1], d2[1]}, [r4]"
+        -
+          asm_text: "vld3.32 {d0[1], d1[1], d2[1]}, [r4]!"
+        -
+          asm_text: "vld3.32 {d0[1], d1[1], d2[1]}, [r4], r6"
+        -
+          asm_text: "vld3.32 {d0[1], d2[1], d4[1]}, [r4]"
+        -
+          asm_text: "vld3.32 {d0[1], d2[1], d4[1]}, [r4]!"
+        -
+          asm_text: "vld3.32 {d0[1], d2[1], d4[1]}, [r4], r6"
+        -
+          asm_text: "vld3.32 {d0[], d1[], d2[]}, [r4]"
+        -
+          asm_text: "vld3.32 {d0[], d1[], d2[]}, [r4]!"
+        -
+          asm_text: "vld3.32 {d0[], d1[], d2[]}, [r4], r6"
+        -
+          asm_text: "vld3.32 {d0[], d2[], d4[]}, [r4]"
+        -
+          asm_text: "vld3.32 {d0[], d2[], d4[]}, [r4]!"
+        -
+          asm_text: "vld3.32 {d0[], d2[], d4[]}, [r4], r6"
+        -
+          asm_text: "vld4.8 {d0, d1, d2, d3}, [r4]"
+        -
+          asm_text: "vld4.8 {d0, d1, d2, d3}, [r4:64]"
+        -
+          asm_text: "vld4.8 {d0, d1, d2, d3}, [r4:128]"
+        -
+          asm_text: "vld4.8 {d0, d1, d2, d3}, [r4:256]"
+        -
+          asm_text: "vld4.8 {d0, d1, d2, d3}, [r4]!"
+        -
+          asm_text: "vld4.8 {d0, d1, d2, d3}, [r4:64]!"
+        -
+          asm_text: "vld4.8 {d0, d1, d2, d3}, [r4:128]!"
+        -
+          asm_text: "vld4.8 {d0, d1, d2, d3}, [r4:256]!"
+        -
+          asm_text: "vld4.8 {d0, d1, d2, d3}, [r4], r6"
+        -
+          asm_text: "vld4.8 {d0, d1, d2, d3}, [r4:64], r6"
+        -
+          asm_text: "vld4.8 {d0, d1, d2, d3}, [r4:128], r6"
+        -
+          asm_text: "vld4.8 {d0, d1, d2, d3}, [r4:256], r6"
+        -
+          asm_text: "vld4.8 {d0, d2, d4, d6}, [r4]"
+        -
+          asm_text: "vld4.8 {d0, d2, d4, d6}, [r4:64]"
+        -
+          asm_text: "vld4.8 {d0, d2, d4, d6}, [r4:128]"
+        -
+          asm_text: "vld4.8 {d0, d2, d4, d6}, [r4:256]"
+        -
+          asm_text: "vld4.8 {d0, d2, d4, d6}, [r4]!"
+        -
+          asm_text: "vld4.8 {d0, d2, d4, d6}, [r4:64]!"
+        -
+          asm_text: "vld4.8 {d0, d2, d4, d6}, [r4:128]!"
+        -
+          asm_text: "vld4.8 {d0, d2, d4, d6}, [r4:256]!"
+        -
+          asm_text: "vld4.8 {d0, d2, d4, d6}, [r4], r6"
+        -
+          asm_text: "vld4.8 {d0, d2, d4, d6}, [r4:64], r6"
+        -
+          asm_text: "vld4.8 {d0, d2, d4, d6}, [r4:128], r6"
+        -
+          asm_text: "vld4.8 {d0, d2, d4, d6}, [r4:256], r6"
+        -
+          asm_text: "vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4]"
+        -
+          asm_text: "vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:32]"
+        -
+          asm_text: "vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4]!"
+        -
+          asm_text: "vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:32]!"
+        -
+          asm_text: "vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4], r6"
+        -
+          asm_text: "vld4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:32], r6"
+        -
+          asm_text: "vld4.8 {d0[], d1[], d2[], d3[]}, [r4]"
+        -
+          asm_text: "vld4.8 {d0[], d1[], d2[], d3[]}, [r4:32]"
+        -
+          asm_text: "vld4.8 {d0[], d1[], d2[], d3[]}, [r4]!"
+        -
+          asm_text: "vld4.8 {d0[], d1[], d2[], d3[]}, [r4:32]!"
+        -
+          asm_text: "vld4.8 {d0[], d1[], d2[], d3[]}, [r4], r6"
+        -
+          asm_text: "vld4.8 {d0[], d1[], d2[], d3[]}, [r4:32], r6"
+        -
+          asm_text: "vld4.8 {d0[], d2[], d4[], d6[]}, [r4]"
+        -
+          asm_text: "vld4.8 {d0[], d2[], d4[], d6[]}, [r4:32]"
+        -
+          asm_text: "vld4.8 {d0[], d2[], d4[], d6[]}, [r4]!"
+        -
+          asm_text: "vld4.8 {d0[], d2[], d4[], d6[]}, [r4:32]!"
+        -
+          asm_text: "vld4.8 {d0[], d2[], d4[], d6[]}, [r4], r6"
+        -
+          asm_text: "vld4.8 {d0[], d2[], d4[], d6[]}, [r4:32], r6"
+        -
+          asm_text: "vld4.16 {d0, d1, d2, d3}, [r4]"
+        -
+          asm_text: "vld4.16 {d0, d1, d2, d3}, [r4:64]"
+        -
+          asm_text: "vld4.16 {d0, d1, d2, d3}, [r4:128]"
+        -
+          asm_text: "vld4.16 {d0, d1, d2, d3}, [r4:256]"
+        -
+          asm_text: "vld4.16 {d0, d1, d2, d3}, [r4]!"
+        -
+          asm_text: "vld4.16 {d0, d1, d2, d3}, [r4:64]!"
+        -
+          asm_text: "vld4.16 {d0, d1, d2, d3}, [r4:128]!"
+        -
+          asm_text: "vld4.16 {d0, d1, d2, d3}, [r4:256]!"
+        -
+          asm_text: "vld4.16 {d0, d1, d2, d3}, [r4], r6"
+        -
+          asm_text: "vld4.16 {d0, d1, d2, d3}, [r4:64], r6"
+        -
+          asm_text: "vld4.16 {d0, d1, d2, d3}, [r4:128], r6"
+        -
+          asm_text: "vld4.16 {d0, d1, d2, d3}, [r4:256], r6"
+        -
+          asm_text: "vld4.16 {d0, d2, d4, d6}, [r4]"
+        -
+          asm_text: "vld4.16 {d0, d2, d4, d6}, [r4:64]"
+        -
+          asm_text: "vld4.16 {d0, d2, d4, d6}, [r4:128]"
+        -
+          asm_text: "vld4.16 {d0, d2, d4, d6}, [r4:256]"
+        -
+          asm_text: "vld4.16 {d0, d2, d4, d6}, [r4]!"
+        -
+          asm_text: "vld4.16 {d0, d2, d4, d6}, [r4:64]!"
+        -
+          asm_text: "vld4.16 {d0, d2, d4, d6}, [r4:128]!"
+        -
+          asm_text: "vld4.16 {d0, d2, d4, d6}, [r4:256]!"
+        -
+          asm_text: "vld4.16 {d0, d2, d4, d6}, [r4], r6"
+        -
+          asm_text: "vld4.16 {d0, d2, d4, d6}, [r4:64], r6"
+        -
+          asm_text: "vld4.16 {d0, d2, d4, d6}, [r4:128], r6"
+        -
+          asm_text: "vld4.16 {d0, d2, d4, d6}, [r4:256], r6"
+        -
+          asm_text: "vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4]"
+        -
+          asm_text: "vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:64]"
+        -
+          asm_text: "vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4]!"
+        -
+          asm_text: "vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:64]!"
+        -
+          asm_text: "vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4], r6"
+        -
+          asm_text: "vld4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:64], r6"
+        -
+          asm_text: "vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4]"
+        -
+          asm_text: "vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:64]"
+        -
+          asm_text: "vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4]!"
+        -
+          asm_text: "vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:64]!"
+        -
+          asm_text: "vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4], r6"
+        -
+          asm_text: "vld4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:64], r6"
+        -
+          asm_text: "vld4.16 {d0[], d1[], d2[], d3[]}, [r4]"
+        -
+          asm_text: "vld4.16 {d0[], d1[], d2[], d3[]}, [r4:64]"
+        -
+          asm_text: "vld4.16 {d0[], d1[], d2[], d3[]}, [r4]!"
+        -
+          asm_text: "vld4.16 {d0[], d1[], d2[], d3[]}, [r4:64]!"
+        -
+          asm_text: "vld4.16 {d0[], d1[], d2[], d3[]}, [r4], r6"
+        -
+          asm_text: "vld4.16 {d0[], d1[], d2[], d3[]}, [r4:64], r6"
+        -
+          asm_text: "vld4.16 {d0[], d2[], d4[], d6[]}, [r4]"
+        -
+          asm_text: "vld4.16 {d0[], d2[], d4[], d6[]}, [r4:64]"
+        -
+          asm_text: "vld4.16 {d0[], d2[], d4[], d6[]}, [r4]!"
+        -
+          asm_text: "vld4.16 {d0[], d2[], d4[], d6[]}, [r4:64]!"
+        -
+          asm_text: "vld4.16 {d0[], d2[], d4[], d6[]}, [r4], r6"
+        -
+          asm_text: "vld4.16 {d0[], d2[], d4[], d6[]}, [r4:64], r6"
+        -
+          asm_text: "vld4.32 {d0, d1, d2, d3}, [r4]"
+        -
+          asm_text: "vld4.32 {d0, d1, d2, d3}, [r4:64]"
+        -
+          asm_text: "vld4.32 {d0, d1, d2, d3}, [r4:128]"
+        -
+          asm_text: "vld4.32 {d0, d1, d2, d3}, [r4:256]"
+        -
+          asm_text: "vld4.32 {d0, d1, d2, d3}, [r4]!"
+        -
+          asm_text: "vld4.32 {d0, d1, d2, d3}, [r4:64]!"
+        -
+          asm_text: "vld4.32 {d0, d1, d2, d3}, [r4:128]!"
+        -
+          asm_text: "vld4.32 {d0, d1, d2, d3}, [r4:256]!"
+        -
+          asm_text: "vld4.32 {d0, d1, d2, d3}, [r4], r6"
+        -
+          asm_text: "vld4.32 {d0, d1, d2, d3}, [r4:64], r6"
+        -
+          asm_text: "vld4.32 {d0, d1, d2, d3}, [r4:128], r6"
+        -
+          asm_text: "vld4.32 {d0, d1, d2, d3}, [r4:256], r6"
+        -
+          asm_text: "vld4.32 {d0, d2, d4, d6}, [r4]"
+        -
+          asm_text: "vld4.32 {d0, d2, d4, d6}, [r4:64]"
+        -
+          asm_text: "vld4.32 {d0, d2, d4, d6}, [r4:128]"
+        -
+          asm_text: "vld4.32 {d0, d2, d4, d6}, [r4:256]"
+        -
+          asm_text: "vld4.32 {d0, d2, d4, d6}, [r4]!"
+        -
+          asm_text: "vld4.32 {d0, d2, d4, d6}, [r4:64]!"
+        -
+          asm_text: "vld4.32 {d0, d2, d4, d6}, [r4:128]!"
+        -
+          asm_text: "vld4.32 {d0, d2, d4, d6}, [r4:256]!"
+        -
+          asm_text: "vld4.32 {d0, d2, d4, d6}, [r4], r6"
+        -
+          asm_text: "vld4.32 {d0, d2, d4, d6}, [r4:64], r6"
+        -
+          asm_text: "vld4.32 {d0, d2, d4, d6}, [r4:128], r6"
+        -
+          asm_text: "vld4.32 {d0, d2, d4, d6}, [r4:256], r6"
+        -
+          asm_text: "vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4]"
+        -
+          asm_text: "vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:64]"
+        -
+          asm_text: "vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:128]"
+        -
+          asm_text: "vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4]!"
+        -
+          asm_text: "vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:64]!"
+        -
+          asm_text: "vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:128]!"
+        -
+          asm_text: "vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4], r6"
+        -
+          asm_text: "vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:64], r6"
+        -
+          asm_text: "vld4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:128], r6"
+        -
+          asm_text: "vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4]"
+        -
+          asm_text: "vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:64]"
+        -
+          asm_text: "vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:128]"
+        -
+          asm_text: "vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4]!"
+        -
+          asm_text: "vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:64]!"
+        -
+          asm_text: "vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:128]!"
+        -
+          asm_text: "vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4], r6"
+        -
+          asm_text: "vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:64], r6"
+        -
+          asm_text: "vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:128], r6"
+        -
+          asm_text: "vld4.32 {d0[], d1[], d2[], d3[]}, [r4]"
+        -
+          asm_text: "vld4.32 {d0[], d1[], d2[], d3[]}, [r4:64]"
+        -
+          asm_text: "vld4.32 {d0[], d1[], d2[], d3[]}, [r4:128]"
+        -
+          asm_text: "vld4.32 {d0[], d1[], d2[], d3[]}, [r4]!"
+        -
+          asm_text: "vld4.32 {d0[], d1[], d2[], d3[]}, [r4:64]!"
+        -
+          asm_text: "vld4.32 {d0[], d1[], d2[], d3[]}, [r4:128]!"
+        -
+          asm_text: "vld4.32 {d0[], d1[], d2[], d3[]}, [r4], r6"
+        -
+          asm_text: "vld4.32 {d0[], d1[], d2[], d3[]}, [r4:64], r6"
+        -
+          asm_text: "vld4.32 {d0[], d1[], d2[], d3[]}, [r4:128], r6"
+        -
+          asm_text: "vld4.32 {d0[], d2[], d4[], d6[]}, [r4]"
+        -
+          asm_text: "vld4.32 {d0[], d2[], d4[], d6[]}, [r4:64]"
+        -
+          asm_text: "vld4.32 {d0[], d2[], d4[], d6[]}, [r4:128]"
+        -
+          asm_text: "vld4.32 {d0[], d2[], d4[], d6[]}, [r4]!"
+        -
+          asm_text: "vld4.32 {d0[], d2[], d4[], d6[]}, [r4:64]!"
+        -
+          asm_text: "vld4.32 {d0[], d2[], d4[], d6[]}, [r4:128]!"
+        -
+          asm_text: "vld4.32 {d0[], d2[], d4[], d6[]}, [r4], r6"
+        -
+          asm_text: "vld4.32 {d0[], d2[], d4[], d6[]}, [r4:64], r6"
+        -
+          asm_text: "vld4.32 {d0[], d2[], d4[], d6[]}, [r4:128], r6"
+        -
+          asm_text: "vst1.8 {d0}, [r4]"
+        -
+          asm_text: "vst1.8 {d0}, [r4:64]"
+        -
+          asm_text: "vst1.8 {d0}, [r4]!"
+        -
+          asm_text: "vst1.8 {d0}, [r4:64]!"
+        -
+          asm_text: "vst1.8 {d0}, [r4], r6"
+        -
+          asm_text: "vst1.8 {d0}, [r4:64], r6"
+        -
+          asm_text: "vst1.8 {d0, d1}, [r4]"
+        -
+          asm_text: "vst1.8 {d0, d1}, [r4:64]"
+        -
+          asm_text: "vst1.8 {d0, d1}, [r4:128]"
+        -
+          asm_text: "vst1.8 {d0, d1}, [r4]!"
+        -
+          asm_text: "vst1.8 {d0, d1}, [r4:64]!"
+        -
+          asm_text: "vst1.8 {d0, d1}, [r4:128]!"
+        -
+          asm_text: "vst1.8 {d0, d1}, [r4], r6"
+        -
+          asm_text: "vst1.8 {d0, d1}, [r4:64], r6"
+        -
+          asm_text: "vst1.8 {d0, d1}, [r4:128], r6"
+        -
+          asm_text: "vst1.8 {d0, d1, d2}, [r4]"
+        -
+          asm_text: "vst1.8 {d0, d1, d2}, [r4:64]"
+        -
+          asm_text: "vst1.8 {d0, d1, d2}, [r4]!"
+        -
+          asm_text: "vst1.8 {d0, d1, d2}, [r4:64]!"
+        -
+          asm_text: "vst1.8 {d0, d1, d2}, [r4], r6"
+        -
+          asm_text: "vst1.8 {d0, d1, d2}, [r4:64], r6"
+        -
+          asm_text: "vst1.8 {d0, d1, d2, d3}, [r4]"
+        -
+          asm_text: "vst1.8 {d0, d1, d2, d3}, [r4:64]"
+        -
+          asm_text: "vst1.8 {d0, d1, d2, d3}, [r4:128]"
+        -
+          asm_text: "vst1.8 {d0, d1, d2, d3}, [r4:256]"
+        -
+          asm_text: "vst1.8 {d0, d1, d2, d3}, [r4]!"
+        -
+          asm_text: "vst1.8 {d0, d1, d2, d3}, [r4:64]!"
+        -
+          asm_text: "vst1.8 {d0, d1, d2, d3}, [r4:128]!"
+        -
+          asm_text: "vst1.8 {d0, d1, d2, d3}, [r4:256]!"
+        -
+          asm_text: "vst1.8 {d0, d1, d2, d3}, [r4], r6"
+        -
+          asm_text: "vst1.8 {d0, d1, d2, d3}, [r4:64], r6"
+        -
+          asm_text: "vst1.8 {d0, d1, d2, d3}, [r4:128], r6"
+        -
+          asm_text: "vst1.8 {d0, d1, d2, d3}, [r4:256], r6"
+        -
+          asm_text: "vst1.8 {d0[2]}, [r4]"
+        -
+          asm_text: "vst1.8 {d0[2]}, [r4]!"
+        -
+          asm_text: "vst1.8 {d0[2]}, [r4], r6"
+        -
+          asm_text: "vst1.16 {d0}, [r4]"
+        -
+          asm_text: "vst1.16 {d0}, [r4:64]"
+        -
+          asm_text: "vst1.16 {d0}, [r4]!"
+        -
+          asm_text: "vst1.16 {d0}, [r4:64]!"
+        -
+          asm_text: "vst1.16 {d0}, [r4], r6"
+        -
+          asm_text: "vst1.16 {d0}, [r4:64], r6"
+        -
+          asm_text: "vst1.16 {d0, d1}, [r4]"
+        -
+          asm_text: "vst1.16 {d0, d1}, [r4:64]"
+        -
+          asm_text: "vst1.16 {d0, d1}, [r4:128]"
+        -
+          asm_text: "vst1.16 {d0, d1}, [r4]!"
+        -
+          asm_text: "vst1.16 {d0, d1}, [r4:64]!"
+        -
+          asm_text: "vst1.16 {d0, d1}, [r4:128]!"
+        -
+          asm_text: "vst1.16 {d0, d1}, [r4], r6"
+        -
+          asm_text: "vst1.16 {d0, d1}, [r4:64], r6"
+        -
+          asm_text: "vst1.16 {d0, d1}, [r4:128], r6"
+        -
+          asm_text: "vst1.16 {d0, d1, d2}, [r4]"
+        -
+          asm_text: "vst1.16 {d0, d1, d2}, [r4:64]"
+        -
+          asm_text: "vst1.16 {d0, d1, d2}, [r4]!"
+        -
+          asm_text: "vst1.16 {d0, d1, d2}, [r4:64]!"
+        -
+          asm_text: "vst1.16 {d0, d1, d2}, [r4], r6"
+        -
+          asm_text: "vst1.16 {d0, d1, d2}, [r4:64], r6"
+        -
+          asm_text: "vst1.16 {d0, d1, d2, d3}, [r4]"
+        -
+          asm_text: "vst1.16 {d0, d1, d2, d3}, [r4:64]"
+        -
+          asm_text: "vst1.16 {d0, d1, d2, d3}, [r4:128]"
+        -
+          asm_text: "vst1.16 {d0, d1, d2, d3}, [r4:256]"
+        -
+          asm_text: "vst1.16 {d0, d1, d2, d3}, [r4]!"
+        -
+          asm_text: "vst1.16 {d0, d1, d2, d3}, [r4:64]!"
+        -
+          asm_text: "vst1.16 {d0, d1, d2, d3}, [r4:128]!"
+        -
+          asm_text: "vst1.16 {d0, d1, d2, d3}, [r4:256]!"
+        -
+          asm_text: "vst1.16 {d0, d1, d2, d3}, [r4], r6"
+        -
+          asm_text: "vst1.16 {d0, d1, d2, d3}, [r4:64], r6"
+        -
+          asm_text: "vst1.16 {d0, d1, d2, d3}, [r4:128], r6"
+        -
+          asm_text: "vst1.16 {d0, d1, d2, d3}, [r4:256], r6"
+        -
+          asm_text: "vst1.16 {d0[2]}, [r4]"
+        -
+          asm_text: "vst1.16 {d0[2]}, [r4:16]"
+        -
+          asm_text: "vst1.16 {d0[2]}, [r4]!"
+        -
+          asm_text: "vst1.16 {d0[2]}, [r4:16]!"
+        -
+          asm_text: "vst1.16 {d0[2]}, [r4], r6"
+        -
+          asm_text: "vst1.16 {d0[2]}, [r4:16], r6"
+        -
+          asm_text: "vst1.32 {d0}, [r4]"
+        -
+          asm_text: "vst1.32 {d0}, [r4:64]"
+        -
+          asm_text: "vst1.32 {d0}, [r4]!"
+        -
+          asm_text: "vst1.32 {d0}, [r4:64]!"
+        -
+          asm_text: "vst1.32 {d0}, [r4], r6"
+        -
+          asm_text: "vst1.32 {d0}, [r4:64], r6"
+        -
+          asm_text: "vst1.32 {d0, d1}, [r4]"
+        -
+          asm_text: "vst1.32 {d0, d1}, [r4:64]"
+        -
+          asm_text: "vst1.32 {d0, d1}, [r4:128]"
+        -
+          asm_text: "vst1.32 {d0, d1}, [r4]!"
+        -
+          asm_text: "vst1.32 {d0, d1}, [r4:64]!"
+        -
+          asm_text: "vst1.32 {d0, d1}, [r4:128]!"
+        -
+          asm_text: "vst1.32 {d0, d1}, [r4], r6"
+        -
+          asm_text: "vst1.32 {d0, d1}, [r4:64], r6"
+        -
+          asm_text: "vst1.32 {d0, d1}, [r4:128], r6"
+        -
+          asm_text: "vst1.32 {d0, d1, d2}, [r4]"
+        -
+          asm_text: "vst1.32 {d0, d1, d2}, [r4:64]"
+        -
+          asm_text: "vst1.32 {d0, d1, d2}, [r4]!"
+        -
+          asm_text: "vst1.32 {d0, d1, d2}, [r4:64]!"
+        -
+          asm_text: "vst1.32 {d0, d1, d2}, [r4], r6"
+        -
+          asm_text: "vst1.32 {d0, d1, d2}, [r4:64], r6"
+        -
+          asm_text: "vst1.32 {d0, d1, d2, d3}, [r4]"
+        -
+          asm_text: "vst1.32 {d0, d1, d2, d3}, [r4:64]"
+        -
+          asm_text: "vst1.32 {d0, d1, d2, d3}, [r4:128]"
+        -
+          asm_text: "vst1.32 {d0, d1, d2, d3}, [r4:256]"
+        -
+          asm_text: "vst1.32 {d0, d1, d2, d3}, [r4]!"
+        -
+          asm_text: "vst1.32 {d0, d1, d2, d3}, [r4:64]!"
+        -
+          asm_text: "vst1.32 {d0, d1, d2, d3}, [r4:128]!"
+        -
+          asm_text: "vst1.32 {d0, d1, d2, d3}, [r4:256]!"
+        -
+          asm_text: "vst1.32 {d0, d1, d2, d3}, [r4], r6"
+        -
+          asm_text: "vst1.32 {d0, d1, d2, d3}, [r4:64], r6"
+        -
+          asm_text: "vst1.32 {d0, d1, d2, d3}, [r4:128], r6"
+        -
+          asm_text: "vst1.32 {d0, d1, d2, d3}, [r4:256], r6"
+        -
+          asm_text: "vst1.32 {d0[1]}, [r4]"
+        -
+          asm_text: "vst1.32 {d0[1]}, [r4:32]"
+        -
+          asm_text: "vst1.32 {d0[1]}, [r4]!"
+        -
+          asm_text: "vst1.32 {d0[1]}, [r4:32]!"
+        -
+          asm_text: "vst1.32 {d0[1]}, [r4], r6"
+        -
+          asm_text: "vst1.32 {d0[1]}, [r4:32], r6"
+        -
+          asm_text: "vst1.64 {d0}, [r4]"
+        -
+          asm_text: "vst1.64 {d0}, [r4:64]"
+        -
+          asm_text: "vst1.64 {d0}, [r4]!"
+        -
+          asm_text: "vst1.64 {d0}, [r4:64]!"
+        -
+          asm_text: "vst1.64 {d0}, [r4], r6"
+        -
+          asm_text: "vst1.64 {d0}, [r4:64], r6"
+        -
+          asm_text: "vst1.64 {d0, d1}, [r4]"
+        -
+          asm_text: "vst1.64 {d0, d1}, [r4:64]"
+        -
+          asm_text: "vst1.64 {d0, d1}, [r4:128]"
+        -
+          asm_text: "vst1.64 {d0, d1}, [r4]!"
+        -
+          asm_text: "vst1.64 {d0, d1}, [r4:64]!"
+        -
+          asm_text: "vst1.64 {d0, d1}, [r4:128]!"
+        -
+          asm_text: "vst1.64 {d0, d1}, [r4], r6"
+        -
+          asm_text: "vst1.64 {d0, d1}, [r4:64], r6"
+        -
+          asm_text: "vst1.64 {d0, d1}, [r4:128], r6"
+        -
+          asm_text: "vst1.64 {d0, d1, d2}, [r4]"
+        -
+          asm_text: "vst1.64 {d0, d1, d2}, [r4:64]"
+        -
+          asm_text: "vst1.64 {d0, d1, d2}, [r4]!"
+        -
+          asm_text: "vst1.64 {d0, d1, d2}, [r4:64]!"
+        -
+          asm_text: "vst1.64 {d0, d1, d2}, [r4], r6"
+        -
+          asm_text: "vst1.64 {d0, d1, d2}, [r4:64], r6"
+        -
+          asm_text: "vst1.64 {d0, d1, d2, d3}, [r4]"
+        -
+          asm_text: "vst1.64 {d0, d1, d2, d3}, [r4:64]"
+        -
+          asm_text: "vst1.64 {d0, d1, d2, d3}, [r4:128]"
+        -
+          asm_text: "vst1.64 {d0, d1, d2, d3}, [r4:256]"
+        -
+          asm_text: "vst1.64 {d0, d1, d2, d3}, [r4]!"
+        -
+          asm_text: "vst1.64 {d0, d1, d2, d3}, [r4:64]!"
+        -
+          asm_text: "vst1.64 {d0, d1, d2, d3}, [r4:128]!"
+        -
+          asm_text: "vst1.64 {d0, d1, d2, d3}, [r4:256]!"
+        -
+          asm_text: "vst1.64 {d0, d1, d2, d3}, [r4], r6"
+        -
+          asm_text: "vst1.64 {d0, d1, d2, d3}, [r4:64], r6"
+        -
+          asm_text: "vst1.64 {d0, d1, d2, d3}, [r4:128], r6"
+        -
+          asm_text: "vst1.64 {d0, d1, d2, d3}, [r4:256], r6"
+        -
+          asm_text: "vst2.8 {d0, d1}, [r4]"
+        -
+          asm_text: "vst2.8 {d0, d1}, [r4:64]"
+        -
+          asm_text: "vst2.8 {d0, d1}, [r4:128]"
+        -
+          asm_text: "vst2.8 {d0, d1}, [r4]!"
+        -
+          asm_text: "vst2.8 {d0, d1}, [r4:64]!"
+        -
+          asm_text: "vst2.8 {d0, d1}, [r4:128]!"
+        -
+          asm_text: "vst2.8 {d0, d1}, [r4], r6"
+        -
+          asm_text: "vst2.8 {d0, d1}, [r4:64], r6"
+        -
+          asm_text: "vst2.8 {d0, d1}, [r4:128], r6"
+        -
+          asm_text: "vst2.8 {d0, d2}, [r4]"
+        -
+          asm_text: "vst2.8 {d0, d2}, [r4:64]"
+        -
+          asm_text: "vst2.8 {d0, d2}, [r4:128]"
+        -
+          asm_text: "vst2.8 {d0, d2}, [r4]!"
+        -
+          asm_text: "vst2.8 {d0, d2}, [r4:64]!"
+        -
+          asm_text: "vst2.8 {d0, d2}, [r4:128]!"
+        -
+          asm_text: "vst2.8 {d0, d2}, [r4], r6"
+        -
+          asm_text: "vst2.8 {d0, d2}, [r4:64], r6"
+        -
+          asm_text: "vst2.8 {d0, d2}, [r4:128], r6"
+        -
+          asm_text: "vst2.8 {d0, d1, d2, d3}, [r4]"
+        -
+          asm_text: "vst2.8 {d0, d1, d2, d3}, [r4:64]"
+        -
+          asm_text: "vst2.8 {d0, d1, d2, d3}, [r4:128]"
+        -
+          asm_text: "vst2.8 {d0, d1, d2, d3}, [r4:256]"
+        -
+          asm_text: "vst2.8 {d0, d1, d2, d3}, [r4]!"
+        -
+          asm_text: "vst2.8 {d0, d1, d2, d3}, [r4:64]!"
+        -
+          asm_text: "vst2.8 {d0, d1, d2, d3}, [r4:128]!"
+        -
+          asm_text: "vst2.8 {d0, d1, d2, d3}, [r4:256]!"
+        -
+          asm_text: "vst2.8 {d0, d1, d2, d3}, [r4], r6"
+        -
+          asm_text: "vst2.8 {d0, d1, d2, d3}, [r4:64], r6"
+        -
+          asm_text: "vst2.8 {d0, d1, d2, d3}, [r4:128], r6"
+        -
+          asm_text: "vst2.8 {d0, d1, d2, d3}, [r4:256], r6"
+        -
+          asm_text: "vst2.8 {d0[2], d1[2]}, [r4]"
+        -
+          asm_text: "vst2.8 {d0[2], d1[2]}, [r4:16]"
+        -
+          asm_text: "vst2.8 {d0[2], d1[2]}, [r4]!"
+        -
+          asm_text: "vst2.8 {d0[2], d1[2]}, [r4:16]!"
+        -
+          asm_text: "vst2.8 {d0[2], d1[2]}, [r4], r6"
+        -
+          asm_text: "vst2.8 {d0[2], d1[2]}, [r4:16], r6"
+        -
+          asm_text: "vst2.32 {d0, d1}, [r4]"
+        -
+          asm_text: "vst2.32 {d0, d1}, [r4:64]"
+        -
+          asm_text: "vst2.32 {d0, d1}, [r4:128]"
+        -
+          asm_text: "vst2.32 {d0, d1}, [r4]!"
+        -
+          asm_text: "vst2.32 {d0, d1}, [r4:64]!"
+        -
+          asm_text: "vst2.32 {d0, d1}, [r4:128]!"
+        -
+          asm_text: "vst2.32 {d0, d1}, [r4], r6"
+        -
+          asm_text: "vst2.32 {d0, d1}, [r4:64], r6"
+        -
+          asm_text: "vst2.32 {d0, d1}, [r4:128], r6"
+        -
+          asm_text: "vst2.32 {d0, d2}, [r4]"
+        -
+          asm_text: "vst2.32 {d0, d2}, [r4:64]"
+        -
+          asm_text: "vst2.32 {d0, d2}, [r4:128]"
+        -
+          asm_text: "vst2.32 {d0, d2}, [r4]!"
+        -
+          asm_text: "vst2.32 {d0, d2}, [r4:64]!"
+        -
+          asm_text: "vst2.32 {d0, d2}, [r4:128]!"
+        -
+          asm_text: "vst2.32 {d0, d2}, [r4], r6"
+        -
+          asm_text: "vst2.32 {d0, d2}, [r4:64], r6"
+        -
+          asm_text: "vst2.32 {d0, d2}, [r4:128], r6"
+        -
+          asm_text: "vst2.32 {d0, d1, d2, d3}, [r4]"
+        -
+          asm_text: "vst2.32 {d0, d1, d2, d3}, [r4:64]"
+        -
+          asm_text: "vst2.32 {d0, d1, d2, d3}, [r4:128]"
+        -
+          asm_text: "vst2.32 {d0, d1, d2, d3}, [r4:256]"
+        -
+          asm_text: "vst2.32 {d0, d1, d2, d3}, [r4]!"
+        -
+          asm_text: "vst2.32 {d0, d1, d2, d3}, [r4:64]!"
+        -
+          asm_text: "vst2.32 {d0, d1, d2, d3}, [r4:128]!"
+        -
+          asm_text: "vst2.32 {d0, d1, d2, d3}, [r4:256]!"
+        -
+          asm_text: "vst2.32 {d0, d1, d2, d3}, [r4], r6"
+        -
+          asm_text: "vst2.32 {d0, d1, d2, d3}, [r4:64], r6"
+        -
+          asm_text: "vst2.32 {d0, d1, d2, d3}, [r4:128], r6"
+        -
+          asm_text: "vst2.32 {d0, d1, d2, d3}, [r4:256], r6"
+        -
+          asm_text: "vst2.32 {d0[1], d1[1]}, [r4]"
+        -
+          asm_text: "vst2.32 {d0[1], d1[1]}, [r4:64]"
+        -
+          asm_text: "vst2.32 {d0[1], d1[1]}, [r4]!"
+        -
+          asm_text: "vst2.32 {d0[1], d1[1]}, [r4:64]!"
+        -
+          asm_text: "vst2.32 {d0[1], d1[1]}, [r4], r6"
+        -
+          asm_text: "vst2.32 {d0[1], d1[1]}, [r4:64], r6"
+        -
+          asm_text: "vst2.32 {d0[1], d2[1]}, [r4]"
+        -
+          asm_text: "vst2.32 {d0[1], d2[1]}, [r4:64]"
+        -
+          asm_text: "vst2.32 {d0[1], d2[1]}, [r4]!"
+        -
+          asm_text: "vst2.32 {d0[1], d2[1]}, [r4:64]!"
+        -
+          asm_text: "vst2.32 {d0[1], d2[1]}, [r4], r6"
+        -
+          asm_text: "vst2.32 {d0[1], d2[1]}, [r4:64], r6"
+        -
+          asm_text: "vst3.8 {d0, d1, d2}, [r4]"
+        -
+          asm_text: "vst3.8 {d0, d1, d2}, [r4:64]"
+        -
+          asm_text: "vst3.8 {d0, d1, d2}, [r4]!"
+        -
+          asm_text: "vst3.8 {d0, d1, d2}, [r4:64]!"
+        -
+          asm_text: "vst3.8 {d0, d1, d2}, [r4], r6"
+        -
+          asm_text: "vst3.8 {d0, d1, d2}, [r4:64], r6"
+        -
+          asm_text: "vst3.8 {d0, d2, d4}, [r4]"
+        -
+          asm_text: "vst3.8 {d0, d2, d4}, [r4:64]"
+        -
+          asm_text: "vst3.8 {d0, d2, d4}, [r4]!"
+        -
+          asm_text: "vst3.8 {d0, d2, d4}, [r4:64]!"
+        -
+          asm_text: "vst3.8 {d0, d2, d4}, [r4], r6"
+        -
+          asm_text: "vst3.8 {d0, d2, d4}, [r4:64], r6"
+        -
+          asm_text: "vst3.8 {d0[1], d1[1], d2[1]}, [r4]"
+        -
+          asm_text: "vst3.8 {d0[1], d1[1], d2[1]}, [r4]!"
+        -
+          asm_text: "vst3.8 {d0[1], d1[1], d2[1]}, [r4], r6"
+        -
+          asm_text: "vst3.16 {d0, d1, d2}, [r4]"
+        -
+          asm_text: "vst3.16 {d0, d1, d2}, [r4:64]"
+        -
+          asm_text: "vst3.16 {d0, d1, d2}, [r4]!"
+        -
+          asm_text: "vst3.16 {d0, d1, d2}, [r4:64]!"
+        -
+          asm_text: "vst3.16 {d0, d1, d2}, [r4], r6"
+        -
+          asm_text: "vst3.16 {d0, d1, d2}, [r4:64], r6"
+        -
+          asm_text: "vst3.16 {d0, d2, d4}, [r4]"
+        -
+          asm_text: "vst3.16 {d0, d2, d4}, [r4:64]"
+        -
+          asm_text: "vst3.16 {d0, d2, d4}, [r4]!"
+        -
+          asm_text: "vst3.16 {d0, d2, d4}, [r4:64]!"
+        -
+          asm_text: "vst3.16 {d0, d2, d4}, [r4], r6"
+        -
+          asm_text: "vst3.16 {d0, d2, d4}, [r4:64], r6"
+        -
+          asm_text: "vst3.16 {d0[1], d1[1], d2[1]}, [r4]"
+        -
+          asm_text: "vst3.16 {d0[1], d1[1], d2[1]}, [r4]!"
+        -
+          asm_text: "vst3.16 {d0[1], d1[1], d2[1]}, [r4], r6"
+        -
+          asm_text: "vst3.16 {d0[1], d2[1], d4[1]}, [r4]"
+        -
+          asm_text: "vst3.16 {d0[1], d2[1], d4[1]}, [r4]!"
+        -
+          asm_text: "vst3.16 {d0[1], d2[1], d4[1]}, [r4], r6"
+        -
+          asm_text: "vst3.32 {d0, d1, d2}, [r4]"
+        -
+          asm_text: "vst3.32 {d0, d1, d2}, [r4:64]"
+        -
+          asm_text: "vst3.32 {d0, d1, d2}, [r4]!"
+        -
+          asm_text: "vst3.32 {d0, d1, d2}, [r4:64]!"
+        -
+          asm_text: "vst3.32 {d0, d1, d2}, [r4], r6"
+        -
+          asm_text: "vst3.32 {d0, d1, d2}, [r4:64], r6"
+        -
+          asm_text: "vst3.32 {d0, d2, d4}, [r4]"
+        -
+          asm_text: "vst3.32 {d0, d2, d4}, [r4:64]"
+        -
+          asm_text: "vst3.32 {d0, d2, d4}, [r4]!"
+        -
+          asm_text: "vst3.32 {d0, d2, d4}, [r4:64]!"
+        -
+          asm_text: "vst3.32 {d0, d2, d4}, [r4], r6"
+        -
+          asm_text: "vst3.32 {d0, d2, d4}, [r4:64], r6"
+        -
+          asm_text: "vst3.32 {d0[1], d1[1], d2[1]}, [r4]"
+        -
+          asm_text: "vst3.32 {d0[1], d1[1], d2[1]}, [r4]!"
+        -
+          asm_text: "vst3.32 {d0[1], d1[1], d2[1]}, [r4], r6"
+        -
+          asm_text: "vst3.32 {d0[1], d2[1], d4[1]}, [r4]"
+        -
+          asm_text: "vst3.32 {d0[1], d2[1], d4[1]}, [r4]!"
+        -
+          asm_text: "vst3.32 {d0[1], d2[1], d4[1]}, [r4], r6"
+        -
+          asm_text: "vst4.8 {d0, d1, d2, d3}, [r4]"
+        -
+          asm_text: "vst4.8 {d0, d1, d2, d3}, [r4:64]"
+        -
+          asm_text: "vst4.8 {d0, d1, d2, d3}, [r4:128]"
+        -
+          asm_text: "vst4.8 {d0, d1, d2, d3}, [r4:256]"
+        -
+          asm_text: "vst4.8 {d0, d1, d2, d3}, [r4]!"
+        -
+          asm_text: "vst4.8 {d0, d1, d2, d3}, [r4:64]!"
+        -
+          asm_text: "vst4.8 {d0, d1, d2, d3}, [r4:128]!"
+        -
+          asm_text: "vst4.8 {d0, d1, d2, d3}, [r4:256]!"
+        -
+          asm_text: "vst4.8 {d0, d1, d2, d3}, [r4], r6"
+        -
+          asm_text: "vst4.8 {d0, d1, d2, d3}, [r4:64], r6"
+        -
+          asm_text: "vst4.8 {d0, d1, d2, d3}, [r4:128], r6"
+        -
+          asm_text: "vst4.8 {d0, d1, d2, d3}, [r4:256], r6"
+        -
+          asm_text: "vst4.8 {d0, d2, d4, d6}, [r4]"
+        -
+          asm_text: "vst4.8 {d0, d2, d4, d6}, [r4:64]"
+        -
+          asm_text: "vst4.8 {d0, d2, d4, d6}, [r4:128]"
+        -
+          asm_text: "vst4.8 {d0, d2, d4, d6}, [r4:256]"
+        -
+          asm_text: "vst4.8 {d0, d2, d4, d6}, [r4]!"
+        -
+          asm_text: "vst4.8 {d0, d2, d4, d6}, [r4:64]!"
+        -
+          asm_text: "vst4.8 {d0, d2, d4, d6}, [r4:128]!"
+        -
+          asm_text: "vst4.8 {d0, d2, d4, d6}, [r4:256]!"
+        -
+          asm_text: "vst4.8 {d0, d2, d4, d6}, [r4], r6"
+        -
+          asm_text: "vst4.8 {d0, d2, d4, d6}, [r4:64], r6"
+        -
+          asm_text: "vst4.8 {d0, d2, d4, d6}, [r4:128], r6"
+        -
+          asm_text: "vst4.8 {d0, d2, d4, d6}, [r4:256], r6"
+        -
+          asm_text: "vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4]"
+        -
+          asm_text: "vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:32]"
+        -
+          asm_text: "vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4]!"
+        -
+          asm_text: "vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:32]!"
+        -
+          asm_text: "vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4], r6"
+        -
+          asm_text: "vst4.8 {d0[1], d1[1], d2[1], d3[1]}, [r4:32], r6"
+        -
+          asm_text: "vst4.16 {d0, d1, d2, d3}, [r4]"
+        -
+          asm_text: "vst4.16 {d0, d1, d2, d3}, [r4:64]"
+        -
+          asm_text: "vst4.16 {d0, d1, d2, d3}, [r4:128]"
+        -
+          asm_text: "vst4.16 {d0, d1, d2, d3}, [r4:256]"
+        -
+          asm_text: "vst4.16 {d0, d1, d2, d3}, [r4]!"
+        -
+          asm_text: "vst4.16 {d0, d1, d2, d3}, [r4:64]!"
+        -
+          asm_text: "vst4.16 {d0, d1, d2, d3}, [r4:128]!"
+        -
+          asm_text: "vst4.16 {d0, d1, d2, d3}, [r4:256]!"
+        -
+          asm_text: "vst4.16 {d0, d1, d2, d3}, [r4], r6"
+        -
+          asm_text: "vst4.16 {d0, d1, d2, d3}, [r4:64], r6"
+        -
+          asm_text: "vst4.16 {d0, d1, d2, d3}, [r4:128], r6"
+        -
+          asm_text: "vst4.16 {d0, d1, d2, d3}, [r4:256], r6"
+        -
+          asm_text: "vst4.16 {d0, d2, d4, d6}, [r4]"
+        -
+          asm_text: "vst4.16 {d0, d2, d4, d6}, [r4:64]"
+        -
+          asm_text: "vst4.16 {d0, d2, d4, d6}, [r4:128]"
+        -
+          asm_text: "vst4.16 {d0, d2, d4, d6}, [r4:256]"
+        -
+          asm_text: "vst4.16 {d0, d2, d4, d6}, [r4]!"
+        -
+          asm_text: "vst4.16 {d0, d2, d4, d6}, [r4:64]!"
+        -
+          asm_text: "vst4.16 {d0, d2, d4, d6}, [r4:128]!"
+        -
+          asm_text: "vst4.16 {d0, d2, d4, d6}, [r4:256]!"
+        -
+          asm_text: "vst4.16 {d0, d2, d4, d6}, [r4], r6"
+        -
+          asm_text: "vst4.16 {d0, d2, d4, d6}, [r4:64], r6"
+        -
+          asm_text: "vst4.16 {d0, d2, d4, d6}, [r4:128], r6"
+        -
+          asm_text: "vst4.16 {d0, d2, d4, d6}, [r4:256], r6"
+        -
+          asm_text: "vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4]"
+        -
+          asm_text: "vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:64]"
+        -
+          asm_text: "vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4]!"
+        -
+          asm_text: "vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:64]!"
+        -
+          asm_text: "vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4], r6"
+        -
+          asm_text: "vst4.16 {d0[1], d1[1], d2[1], d3[1]}, [r4:64], r6"
+        -
+          asm_text: "vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4]"
+        -
+          asm_text: "vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:64]"
+        -
+          asm_text: "vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4]!"
+        -
+          asm_text: "vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:64]!"
+        -
+          asm_text: "vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4], r6"
+        -
+          asm_text: "vst4.16 {d0[1], d2[1], d4[1], d6[1]}, [r4:64], r6"
+        -
+          asm_text: "vst4.32 {d0, d1, d2, d3}, [r4]"
+        -
+          asm_text: "vst4.32 {d0, d1, d2, d3}, [r4:64]"
+        -
+          asm_text: "vst4.32 {d0, d1, d2, d3}, [r4:128]"
+        -
+          asm_text: "vst4.32 {d0, d1, d2, d3}, [r4:256]"
+        -
+          asm_text: "vst4.32 {d0, d1, d2, d3}, [r4]!"
+        -
+          asm_text: "vst4.32 {d0, d1, d2, d3}, [r4:64]!"
+        -
+          asm_text: "vst4.32 {d0, d1, d2, d3}, [r4:128]!"
+        -
+          asm_text: "vst4.32 {d0, d1, d2, d3}, [r4:256]!"
+        -
+          asm_text: "vst4.32 {d0, d1, d2, d3}, [r4], r6"
+        -
+          asm_text: "vst4.32 {d0, d1, d2, d3}, [r4:64], r6"
+        -
+          asm_text: "vst4.32 {d0, d1, d2, d3}, [r4:128], r6"
+        -
+          asm_text: "vst4.32 {d0, d1, d2, d3}, [r4:256], r6"
+        -
+          asm_text: "vst4.32 {d0, d2, d4, d6}, [r4]"
+        -
+          asm_text: "vst4.32 {d0, d2, d4, d6}, [r4:64]"
+        -
+          asm_text: "vst4.32 {d0, d2, d4, d6}, [r4:128]"
+        -
+          asm_text: "vst4.32 {d0, d2, d4, d6}, [r4:256]"
+        -
+          asm_text: "vst4.32 {d0, d2, d4, d6}, [r4]!"
+        -
+          asm_text: "vst4.32 {d0, d2, d4, d6}, [r4:64]!"
+        -
+          asm_text: "vst4.32 {d0, d2, d4, d6}, [r4:128]!"
+        -
+          asm_text: "vst4.32 {d0, d2, d4, d6}, [r4:256]!"
+        -
+          asm_text: "vst4.32 {d0, d2, d4, d6}, [r4], r6"
+        -
+          asm_text: "vst4.32 {d0, d2, d4, d6}, [r4:64], r6"
+        -
+          asm_text: "vst4.32 {d0, d2, d4, d6}, [r4:128], r6"
+        -
+          asm_text: "vst4.32 {d0, d2, d4, d6}, [r4:256], r6"
+        -
+          asm_text: "vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4]"
+        -
+          asm_text: "vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:64]"
+        -
+          asm_text: "vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:128]"
+        -
+          asm_text: "vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4]!"
+        -
+          asm_text: "vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:64]!"
+        -
+          asm_text: "vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:128]!"
+        -
+          asm_text: "vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4], r6"
+        -
+          asm_text: "vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:64], r6"
+        -
+          asm_text: "vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:128], r6"
+        -
+          asm_text: "vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4]"
+        -
+          asm_text: "vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:64]"
+        -
+          asm_text: "vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:128]"
+        -
+          asm_text: "vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4]!"
+        -
+          asm_text: "vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:64]!"
+        -
+          asm_text: "vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:128]!"
+        -
+          asm_text: "vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4], r6"
+        -
+          asm_text: "vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:64], r6"
+        -
+          asm_text: "vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:128], r6"
+        -
+          asm_text: "vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4]!"
+        -
+          asm_text: "vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:64]!"
+        -
+          asm_text: "vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:128]!"
+        -
+          asm_text: "vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4], r6"
+        -
+          asm_text: "vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:64], r6"
+        -
+          asm_text: "vst4.32 {d0[1], d1[1], d2[1], d3[1]}, [r4:128], r6"
+        -
+          asm_text: "vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4]"
+        -
+          asm_text: "vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:64]"
+        -
+          asm_text: "vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:128]"
+        -
+          asm_text: "vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4]!"
+        -
+          asm_text: "vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:64]!"
+        -
+          asm_text: "vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:128]!"
+        -
+          asm_text: "vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4], r6"
+        -
+          asm_text: "vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:64], r6"
+        -
+          asm_text: "vst4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:128], r6"
diff --git a/tests/MC/ARM/neon-vst-encoding.s.yaml b/tests/MC/ARM/neon-vst-encoding.s.yaml
new file mode 100644
index 000000000..7988717f7
--- /dev/null
+++ b/tests/MC/ARM/neon-vst-encoding.s.yaml
@@ -0,0 +1,246 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x1f, 0x07, 0x40, 0xf4, 0x4f, 0x07, 0x40, 0xf4, 0x8f, 0x07, 0x40, 0xf4, 0xcf, 0x07, 0x40, 0xf4, 0x1f, 0x0a, 0x40, 0xf4, 0x6f, 0x0a, 0x40, 0xf4, 0x8f, 0x0a, 0x40, 0xf4, 0xcf, 0x0a, 0x40, 0xf4, 0x1f, 0x06, 0x40, 0xf4, 0x1d, 0x06, 0x40, 0xf4, 0x03, 0x06, 0x40, 0xf4, 0x1f, 0x02, 0x40, 0xf4, 0x5d, 0x02, 0x41, 0xf4, 0xc2, 0x02, 0x43, 0xf4, 0x1f, 0x08, 0x40, 0xf4, 0x6f, 0x08, 0x40, 0xf4, 0x8f, 0x08, 0x40, 0xf4, 0x1f, 0x03, 0x40, 0xf4, 0x6f, 0x03, 0x40, 0xf4, 0xbf, 0x03, 0x40, 0xf4, 0x1d, 0x08, 0x40, 0xf4, 0x6d, 0xe8, 0x40, 0xf4, 0x8d, 0xe8, 0x00, 0xf4, 0x1d, 0x03, 0x40, 0xf4, 0x6d, 0x23, 0x40, 0xf4, 0xbd, 0x83, 0x00, 0xf4, 0x0f, 0x04, 0x41, 0xf4, 0x4f, 0x64, 0x02, 0xf4, 0x8f, 0x14, 0x03, 0xf4, 0x1f, 0x05, 0x40, 0xf4, 0x4f, 0xb5, 0x44, 0xf4, 0x8f, 0x65, 0x05, 0xf4, 0x01, 0xc4, 0x06, 0xf4, 0x42, 0xb4, 0x07, 0xf4, 0x83, 0x24, 0x08, 0xf4, 0x04, 0x45, 0x09, 0xf4, 0x44, 0xe5, 0x09, 0xf4, 0x85, 0x05, 0x4a, 0xf4, 0x0d, 0x64, 0x08, 0xf4, 0x4d, 0x94, 0x07, 0xf4, 0x8d, 0x14, 0x06, 0xf4, 0x1d, 0x05, 0x40, 0xf4, 0x4d, 0x45, 0x45, 0xf4, 0x8d, 0x55, 0x04, 0xf4, 0x1f, 0x00, 0x41, 0xf4, 0x6f, 0x00, 0x42, 0xf4, 0xbf, 0x00, 0x43, 0xf4, 0x3f, 0x11, 0x45, 0xf4, 0x4f, 0x11, 0x47, 0xf4, 0x8f, 0x01, 0x48, 0xf4, 0x1d, 0x00, 0x41, 0xf4, 0x6d, 0x00, 0x42, 0xf4, 0xbd, 0x00, 0x43, 0xf4, 0x3d, 0x11, 0x45, 0xf4, 0x4d, 0x11, 0x47, 0xf4, 0x8d, 0x01, 0x48, 0xf4, 0x18, 0x00, 0x41, 0xf4, 0x47, 0x00, 0x42, 0xf4, 0x95, 0x00, 0x43, 0xf4, 0x32, 0x01, 0x44, 0xf4, 0x43, 0x01, 0x46, 0xf4, 0x84, 0x11, 0x49, 0xf4, 0x3f, 0x01, 0xc0, 0xf4, 0x5f, 0x05, 0xc0, 0xf4, 0x8f, 0x09, 0xc0, 0xf4, 0x6f, 0x15, 0xc0, 0xf4, 0x5f, 0x19, 0xc0, 0xf4, 0x83, 0x21, 0x82, 0xf4, 0x8d, 0x21, 0x82, 0xf4, 0x8f, 0x21, 0x82, 0xf4, 0x6f, 0x15, 0xc0, 0xf4, 0x5f, 0x19, 0xc0, 0xf4, 0x6d, 0x75, 0x81, 0xf4, 0x5d, 0x69, 0x82, 0xf4, 0x65, 0x25, 0x83, 0xf4, 0x57, 0x59, 0x84, 0xf4, 0x2f, 0x02, 0xc1, 0xf4, 0x4f, 0x66, 0x82, 0xf4, 0x8f, 0x1a, 0x83, 0xf4, 0x6f, 0xb6, 0xc4, 0xf4, 0xcf, 0x6a, 0x85, 0xf4, 0x21, 0xc2, 0x86, 0xf4, 0x42, 0xb6, 0x87, 0xf4, 0x83, 0x2a, 0x88, 0xf4, 0x64, 0xe6, 0x89, 0xf4, 0xc5, 0x0a, 0xca, 0xf4, 0x2d, 0x62, 0x88, 0xf4, 0x4d, 0x96, 0x87, 0xf4, 0x8d, 0x1a, 0x86, 0xf4, 0x6d, 0x46, 0xc5, 0xf4, 0xcd, 0x5a, 0x84, 0xf4, 0x2f, 0x03, 0xc1, 0xf4, 0x4f, 0x07, 0xc2, 0xf4, 0x8f, 0x0b, 0xc3, 0xf4, 0x6f, 0x17, 0xc7, 0xf4, 0xcf, 0x0b, 0xc8, 0xf4, 0x3d, 0x03, 0xc1, 0xf4, 0x5d, 0x07, 0xc2, 0xf4, 0xad, 0x0b, 0xc3, 0xf4, 0x6d, 0x17, 0xc7, 0xf4, 0xcd, 0x0b, 0xc8, 0xf4, 0x38, 0x03, 0xc1, 0xf4, 0x47, 0x07, 0xc2, 0xf4, 0x95, 0x0b, 0xc3, 0xf4, 0x63, 0x07, 0xc6, 0xf4, 0xc4, 0x1b, 0xc9, 0xf4, 0x0f, 0x27, 0x02, 0xf4, 0x0f, 0x27, 0x02, 0xf4, 0x0f, 0x27, 0x02, 0xf4, 0x0f, 0x4a, 0x02, 0xf4, 0x0f, 0x4a, 0x02, 0xf4, 0x0f, 0x4a, 0x02, 0xf4, 0x8f, 0x4a, 0x02, 0xf4, 0x0f, 0x89, 0x04, 0xf4, 0xbf, 0x98, 0x83, 0xf4, 0xbd, 0xb8, 0xc9, 0xf4, 0xb5, 0xb8, 0xc3, 0xf4, 0x1f, 0x08, 0x40, 0xf4, 0x6f, 0x08, 0x40, 0xf4 ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_V8", "CS_MODE_ARM" ]
+    expected:
+      insns:
+        -
+          asm_text: "vst1.8 {d16}, [r0:64]"
+        -
+          asm_text: "vst1.16 {d16}, [r0]"
+        -
+          asm_text: "vst1.32 {d16}, [r0]"
+        -
+          asm_text: "vst1.64 {d16}, [r0]"
+        -
+          asm_text: "vst1.8 {d16, d17}, [r0:64]"
+        -
+          asm_text: "vst1.16 {d16, d17}, [r0:128]"
+        -
+          asm_text: "vst1.32 {d16, d17}, [r0]"
+        -
+          asm_text: "vst1.64 {d16, d17}, [r0]"
+        -
+          asm_text: "vst1.8 {d16, d17, d18}, [r0:64]"
+        -
+          asm_text: "vst1.8 {d16, d17, d18}, [r0:64]!"
+        -
+          asm_text: "vst1.8 {d16, d17, d18}, [r0], r3"
+        -
+          asm_text: "vst1.8 {d16, d17, d18, d19}, [r0:64]"
+        -
+          asm_text: "vst1.16 {d16, d17, d18, d19}, [r1:64]!"
+        -
+          asm_text: "vst1.64 {d16, d17, d18, d19}, [r3], r2"
+        -
+          asm_text: "vst2.8 {d16, d17}, [r0:64]"
+        -
+          asm_text: "vst2.16 {d16, d17}, [r0:128]"
+        -
+          asm_text: "vst2.32 {d16, d17}, [r0]"
+        -
+          asm_text: "vst2.8 {d16, d17, d18, d19}, [r0:64]"
+        -
+          asm_text: "vst2.16 {d16, d17, d18, d19}, [r0:128]"
+        -
+          asm_text: "vst2.32 {d16, d17, d18, d19}, [r0:256]"
+        -
+          asm_text: "vst2.8 {d16, d17}, [r0:64]!"
+        -
+          asm_text: "vst2.16 {d30, d31}, [r0:128]!"
+        -
+          asm_text: "vst2.32 {d14, d15}, [r0]!"
+        -
+          asm_text: "vst2.8 {d16, d17, d18, d19}, [r0:64]!"
+        -
+          asm_text: "vst2.16 {d18, d19, d20, d21}, [r0:128]!"
+        -
+          asm_text: "vst2.32 {d8, d9, d10, d11}, [r0:256]!"
+        -
+          asm_text: "vst3.8 {d16, d17, d18}, [r1]"
+        -
+          asm_text: "vst3.16 {d6, d7, d8}, [r2]"
+        -
+          asm_text: "vst3.32 {d1, d2, d3}, [r3]"
+        -
+          asm_text: "vst3.8 {d16, d18, d20}, [r0:64]"
+        -
+          asm_text: "vst3.16 {d27, d29, d31}, [r4]"
+        -
+          asm_text: "vst3.32 {d6, d8, d10}, [r5]"
+        -
+          asm_text: "vst3.8 {d12, d13, d14}, [r6], r1"
+        -
+          asm_text: "vst3.16 {d11, d12, d13}, [r7], r2"
+        -
+          asm_text: "vst3.32 {d2, d3, d4}, [r8], r3"
+        -
+          asm_text: "vst3.8 {d4, d6, d8}, [r9], r4"
+        -
+          asm_text: "vst3.16 {d14, d16, d18}, [r9], r4"
+        -
+          asm_text: "vst3.32 {d16, d18, d20}, [r10], r5"
+        -
+          asm_text: "vst3.8 {d6, d7, d8}, [r8]!"
+        -
+          asm_text: "vst3.16 {d9, d10, d11}, [r7]!"
+        -
+          asm_text: "vst3.32 {d1, d2, d3}, [r6]!"
+        -
+          asm_text: "vst3.8 {d16, d18, d20}, [r0:64]!"
+        -
+          asm_text: "vst3.16 {d20, d22, d24}, [r5]!"
+        -
+          asm_text: "vst3.32 {d5, d7, d9}, [r4]!"
+        -
+          asm_text: "vst4.8 {d16, d17, d18, d19}, [r1:64]"
+        -
+          asm_text: "vst4.16 {d16, d17, d18, d19}, [r2:128]"
+        -
+          asm_text: "vst4.32 {d16, d17, d18, d19}, [r3:256]"
+        -
+          asm_text: "vst4.8 {d17, d19, d21, d23}, [r5:256]"
+        -
+          asm_text: "vst4.16 {d17, d19, d21, d23}, [r7]"
+        -
+          asm_text: "vst4.32 {d16, d18, d20, d22}, [r8]"
+        -
+          asm_text: "vst4.8 {d16, d17, d18, d19}, [r1:64]!"
+        -
+          asm_text: "vst4.16 {d16, d17, d18, d19}, [r2:128]!"
+        -
+          asm_text: "vst4.32 {d16, d17, d18, d19}, [r3:256]!"
+        -
+          asm_text: "vst4.8 {d17, d19, d21, d23}, [r5:256]!"
+        -
+          asm_text: "vst4.16 {d17, d19, d21, d23}, [r7]!"
+        -
+          asm_text: "vst4.32 {d16, d18, d20, d22}, [r8]!"
+        -
+          asm_text: "vst4.8 {d16, d17, d18, d19}, [r1:64], r8"
+        -
+          asm_text: "vst4.16 {d16, d17, d18, d19}, [r2], r7"
+        -
+          asm_text: "vst4.32 {d16, d17, d18, d19}, [r3:64], r5"
+        -
+          asm_text: "vst4.8 {d16, d18, d20, d22}, [r4:256], r2"
+        -
+          asm_text: "vst4.16 {d16, d18, d20, d22}, [r6], r3"
+        -
+          asm_text: "vst4.32 {d17, d19, d21, d23}, [r9], r4"
+        -
+          asm_text: "vst2.8 {d16[1], d17[1]}, [r0:16]"
+        -
+          asm_text: "vst2.16 {d16[1], d17[1]}, [r0:32]"
+        -
+          asm_text: "vst2.32 {d16[1], d17[1]}, [r0]"
+        -
+          asm_text: "vst2.16 {d17[1], d19[1]}, [r0]"
+        -
+          asm_text: "vst2.32 {d17[0], d19[0]}, [r0:64]"
+        -
+          asm_text: "vst2.8 {d2[4], d3[4]}, [r2], r3"
+        -
+          asm_text: "vst2.8 {d2[4], d3[4]}, [r2]!"
+        -
+          asm_text: "vst2.8 {d2[4], d3[4]}, [r2]"
+        -
+          asm_text: "vst2.16 {d17[1], d19[1]}, [r0]"
+        -
+          asm_text: "vst2.32 {d17[0], d19[0]}, [r0:64]"
+        -
+          asm_text: "vst2.16 {d7[1], d9[1]}, [r1]!"
+        -
+          asm_text: "vst2.32 {d6[0], d8[0]}, [r2:64]!"
+        -
+          asm_text: "vst2.16 {d2[1], d4[1]}, [r3], r5"
+        -
+          asm_text: "vst2.32 {d5[0], d7[0]}, [r4:64], r7"
+        -
+          asm_text: "vst3.8 {d16[1], d17[1], d18[1]}, [r1]"
+        -
+          asm_text: "vst3.16 {d6[1], d7[1], d8[1]}, [r2]"
+        -
+          asm_text: "vst3.32 {d1[1], d2[1], d3[1]}, [r3]"
+        -
+          asm_text: "vst3.16 {d27[1], d29[1], d31[1]}, [r4]"
+        -
+          asm_text: "vst3.32 {d6[1], d8[1], d10[1]}, [r5]"
+        -
+          asm_text: "vst3.8 {d12[1], d13[1], d14[1]}, [r6], r1"
+        -
+          asm_text: "vst3.16 {d11[1], d12[1], d13[1]}, [r7], r2"
+        -
+          asm_text: "vst3.32 {d2[1], d3[1], d4[1]}, [r8], r3"
+        -
+          asm_text: "vst3.16 {d14[1], d16[1], d18[1]}, [r9], r4"
+        -
+          asm_text: "vst3.32 {d16[1], d18[1], d20[1]}, [r10], r5"
+        -
+          asm_text: "vst3.8 {d6[1], d7[1], d8[1]}, [r8]!"
+        -
+          asm_text: "vst3.16 {d9[1], d10[1], d11[1]}, [r7]!"
+        -
+          asm_text: "vst3.32 {d1[1], d2[1], d3[1]}, [r6]!"
+        -
+          asm_text: "vst3.16 {d20[1], d22[1], d24[1]}, [r5]!"
+        -
+          asm_text: "vst3.32 {d5[1], d7[1], d9[1]}, [r4]!"
+        -
+          asm_text: "vst4.8 {d16[1], d17[1], d18[1], d19[1]}, [r1]"
+        -
+          asm_text: "vst4.16 {d16[1], d17[1], d18[1], d19[1]}, [r2]"
+        -
+          asm_text: "vst4.32 {d16[1], d17[1], d18[1], d19[1]}, [r3]"
+        -
+          asm_text: "vst4.16 {d17[1], d19[1], d21[1], d23[1]}, [r7]"
+        -
+          asm_text: "vst4.32 {d16[1], d18[1], d20[1], d22[1]}, [r8]"
+        -
+          asm_text: "vst4.8 {d16[1], d17[1], d18[1], d19[1]}, [r1:32]!"
+        -
+          asm_text: "vst4.16 {d16[1], d17[1], d18[1], d19[1]}, [r2:64]!"
+        -
+          asm_text: "vst4.32 {d16[1], d17[1], d18[1], d19[1]}, [r3:128]!"
+        -
+          asm_text: "vst4.16 {d17[1], d19[1], d21[1], d23[1]}, [r7]!"
+        -
+          asm_text: "vst4.32 {d16[1], d18[1], d20[1], d22[1]}, [r8]!"
+        -
+          asm_text: "vst4.8 {d16[1], d17[1], d18[1], d19[1]}, [r1:32], r8"
+        -
+          asm_text: "vst4.16 {d16[1], d17[1], d18[1], d19[1]}, [r2], r7"
+        -
+          asm_text: "vst4.32 {d16[1], d17[1], d18[1], d19[1]}, [r3:64], r5"
+        -
+          asm_text: "vst4.16 {d16[1], d18[1], d20[1], d22[1]}, [r6], r3"
+        -
+          asm_text: "vst4.32 {d17[1], d19[1], d21[1], d23[1]}, [r9], r4"
+        -
+          asm_text: "vst1.8 {d2}, [r2]"
+        -
+          asm_text: "vst1.8 {d2}, [r2]"
+        -
+          asm_text: "vst1.8 {d2}, [r2]"
+        -
+          asm_text: "vst1.8 {d4, d5}, [r2]"
+        -
+          asm_text: "vst1.8 {d4, d5}, [r2]"
+        -
+          asm_text: "vst1.8 {d4, d5}, [r2]"
+        -
+          asm_text: "vst1.32 {d4, d5}, [r2]"
+        -
+          asm_text: "vst2.8 {d8, d10}, [r4]"
+        -
+          asm_text: "vst1.32 {d9[1]}, [r3:32]"
+        -
+          asm_text: "vst1.32 {d27[1]}, [r9:32]!"
+        -
+          asm_text: "vst1.32 {d27[1]}, [r3:32], r5"
+        -
+          asm_text: "vst2.8 {d16, d17}, [r0:64]"
+        -
+          asm_text: "vst2.16 {d16, d17}, [r0:128]"
diff --git a/tests/MC/ARM/neon-vswp.s.yaml b/tests/MC/ARM/neon-vswp.s.yaml
new file mode 100644
index 000000000..56acf945b
--- /dev/null
+++ b/tests/MC/ARM/neon-vswp.s.yaml
@@ -0,0 +1,12 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x02, 0x10, 0xb2, 0xf3, 0x44, 0x20, 0xb2, 0xf3 ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ]
+    expected:
+      insns:
+        -
+          asm_text: "vswp d1, d2"
+        -
+          asm_text: "vswp q1, q2"
diff --git a/tests/MC/ARM/neont2-abs-encoding.s.yaml b/tests/MC/ARM/neont2-abs-encoding.s.yaml
new file mode 100644
index 000000000..7fa31d775
--- /dev/null
+++ b/tests/MC/ARM/neont2-abs-encoding.s.yaml
@@ -0,0 +1,36 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xf1, 0xff, 0x20, 0x03, 0xf5, 0xff, 0x20, 0x03, 0xf9, 0xff, 0x20, 0x03, 0xf9, 0xff, 0x20, 0x07, 0xf1, 0xff, 0x60, 0x03, 0xf5, 0xff, 0x60, 0x03, 0xf9, 0xff, 0x60, 0x03, 0xf9, 0xff, 0x60, 0x07, 0xf0, 0xff, 0x20, 0x07, 0xf4, 0xff, 0x20, 0x07, 0xf8, 0xff, 0x20, 0x07, 0xf0, 0xff, 0x60, 0x07, 0xf4, 0xff, 0x60, 0x07, 0xf8, 0xff, 0x60, 0x07 ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ]
+    expected:
+      insns:
+        -
+          asm_text: "vabs.s8 d16, d16"
+        -
+          asm_text: "vabs.s16 d16, d16"
+        -
+          asm_text: "vabs.s32 d16, d16"
+        -
+          asm_text: "vabs.f32 d16, d16"
+        -
+          asm_text: "vabs.s8 q8, q8"
+        -
+          asm_text: "vabs.s16 q8, q8"
+        -
+          asm_text: "vabs.s32 q8, q8"
+        -
+          asm_text: "vabs.f32 q8, q8"
+        -
+          asm_text: "vqabs.s8 d16, d16"
+        -
+          asm_text: "vqabs.s16 d16, d16"
+        -
+          asm_text: "vqabs.s32 d16, d16"
+        -
+          asm_text: "vqabs.s8 q8, q8"
+        -
+          asm_text: "vqabs.s16 q8, q8"
+        -
+          asm_text: "vqabs.s32 q8, q8"
diff --git a/tests/MC/ARM/neont2-absdiff-encoding.s.yaml b/tests/MC/ARM/neont2-absdiff-encoding.s.yaml
new file mode 100644
index 000000000..7f70dda48
--- /dev/null
+++ b/tests/MC/ARM/neont2-absdiff-encoding.s.yaml
@@ -0,0 +1,84 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x40, 0xef, 0xa1, 0x07, 0x50, 0xef, 0xa1, 0x07, 0x60, 0xef, 0xa1, 0x07, 0x40, 0xff, 0xa1, 0x07, 0x50, 0xff, 0xa1, 0x07, 0x60, 0xff, 0xa1, 0x07, 0x60, 0xff, 0xa1, 0x0d, 0x40, 0xef, 0xe2, 0x07, 0x50, 0xef, 0xe2, 0x07, 0x60, 0xef, 0xe2, 0x07, 0x40, 0xff, 0xe2, 0x07, 0x50, 0xff, 0xe2, 0x07, 0x60, 0xff, 0xe2, 0x07, 0x60, 0xff, 0xe2, 0x0d, 0xc0, 0xef, 0xa1, 0x07, 0xd0, 0xef, 0xa1, 0x07, 0xe0, 0xef, 0xa1, 0x07, 0xc0, 0xff, 0xa1, 0x07, 0xd0, 0xff, 0xa1, 0x07, 0xe0, 0xff, 0xa1, 0x07, 0x42, 0xef, 0xb1, 0x07, 0x52, 0xef, 0xb1, 0x07, 0x62, 0xef, 0xb1, 0x07, 0x42, 0xff, 0xb1, 0x07, 0x52, 0xff, 0xb1, 0x07, 0x62, 0xff, 0xb1, 0x07, 0x40, 0xef, 0xf4, 0x27, 0x50, 0xef, 0xf4, 0x27, 0x60, 0xef, 0xf4, 0x27, 0x40, 0xff, 0xf4, 0x27, 0x50, 0xff, 0xf4, 0x27, 0x60, 0xff, 0xf4, 0x27, 0xc3, 0xef, 0xa2, 0x05, 0xd3, 0xef, 0xa2, 0x05, 0xe3, 0xef, 0xa2, 0x05, 0xc3, 0xff, 0xa2, 0x05, 0xd3, 0xff, 0xa2, 0x05, 0xe3, 0xff, 0xa2, 0x05 ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ]
+    expected:
+      insns:
+        -
+          asm_text: "vabd.s8 d16, d16, d17"
+        -
+          asm_text: "vabd.s16 d16, d16, d17"
+        -
+          asm_text: "vabd.s32 d16, d16, d17"
+        -
+          asm_text: "vabd.u8 d16, d16, d17"
+        -
+          asm_text: "vabd.u16 d16, d16, d17"
+        -
+          asm_text: "vabd.u32 d16, d16, d17"
+        -
+          asm_text: "vabd.f32 d16, d16, d17"
+        -
+          asm_text: "vabd.s8 q8, q8, q9"
+        -
+          asm_text: "vabd.s16 q8, q8, q9"
+        -
+          asm_text: "vabd.s32 q8, q8, q9"
+        -
+          asm_text: "vabd.u8 q8, q8, q9"
+        -
+          asm_text: "vabd.u16 q8, q8, q9"
+        -
+          asm_text: "vabd.u32 q8, q8, q9"
+        -
+          asm_text: "vabd.f32 q8, q8, q9"
+        -
+          asm_text: "vabdl.s8 q8, d16, d17"
+        -
+          asm_text: "vabdl.s16 q8, d16, d17"
+        -
+          asm_text: "vabdl.s32 q8, d16, d17"
+        -
+          asm_text: "vabdl.u8 q8, d16, d17"
+        -
+          asm_text: "vabdl.u16 q8, d16, d17"
+        -
+          asm_text: "vabdl.u32 q8, d16, d17"
+        -
+          asm_text: "vaba.s8 d16, d18, d17"
+        -
+          asm_text: "vaba.s16 d16, d18, d17"
+        -
+          asm_text: "vaba.s32 d16, d18, d17"
+        -
+          asm_text: "vaba.u8 d16, d18, d17"
+        -
+          asm_text: "vaba.u16 d16, d18, d17"
+        -
+          asm_text: "vaba.u32 d16, d18, d17"
+        -
+          asm_text: "vaba.s8 q9, q8, q10"
+        -
+          asm_text: "vaba.s16 q9, q8, q10"
+        -
+          asm_text: "vaba.s32 q9, q8, q10"
+        -
+          asm_text: "vaba.u8 q9, q8, q10"
+        -
+          asm_text: "vaba.u16 q9, q8, q10"
+        -
+          asm_text: "vaba.u32 q9, q8, q10"
+        -
+          asm_text: "vabal.s8 q8, d19, d18"
+        -
+          asm_text: "vabal.s16 q8, d19, d18"
+        -
+          asm_text: "vabal.s32 q8, d19, d18"
+        -
+          asm_text: "vabal.u8 q8, d19, d18"
+        -
+          asm_text: "vabal.u16 q8, d19, d18"
+        -
+          asm_text: "vabal.u32 q8, d19, d18"
diff --git a/tests/MC/ARM/neont2-add-encoding.s.yaml b/tests/MC/ARM/neont2-add-encoding.s.yaml
new file mode 100644
index 000000000..b61dc0cfe
--- /dev/null
+++ b/tests/MC/ARM/neont2-add-encoding.s.yaml
@@ -0,0 +1,136 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x41, 0xef, 0xa0, 0x08, 0x51, 0xef, 0xa0, 0x08, 0x71, 0xef, 0xa0, 0x08, 0x61, 0xef, 0xa0, 0x08, 0x40, 0xef, 0xa1, 0x0d, 0x40, 0xef, 0xe2, 0x0d, 0xc1, 0xef, 0xa0, 0x00, 0xd1, 0xef, 0xa0, 0x00, 0xe1, 0xef, 0xa0, 0x00, 0xc1, 0xff, 0xa0, 0x00, 0xd1, 0xff, 0xa0, 0x00, 0xe1, 0xff, 0xa0, 0x00, 0xc0, 0xef, 0xa2, 0x01, 0xd0, 0xef, 0xa2, 0x01, 0xe0, 0xef, 0xa2, 0x01, 0xc0, 0xff, 0xa2, 0x01, 0xd0, 0xff, 0xa2, 0x01, 0xe0, 0xff, 0xa2, 0x01, 0x40, 0xef, 0xa1, 0x00, 0x50, 0xef, 0xa1, 0x00, 0x60, 0xef, 0xa1, 0x00, 0x40, 0xff, 0xa1, 0x00, 0x50, 0xff, 0xa1, 0x00, 0x60, 0xff, 0xa1, 0x00, 0x40, 0xef, 0xe2, 0x00, 0x50, 0xef, 0xe2, 0x00, 0x60, 0xef, 0xe2, 0x00, 0x40, 0xff, 0xe2, 0x00, 0x50, 0xff, 0xe2, 0x00, 0x60, 0xff, 0xe2, 0x00, 0x40, 0xef, 0xa1, 0x01, 0x50, 0xef, 0xa1, 0x01, 0x60, 0xef, 0xa1, 0x01, 0x40, 0xff, 0xa1, 0x01, 0x50, 0xff, 0xa1, 0x01, 0x60, 0xff, 0xa1, 0x01, 0x40, 0xef, 0xe2, 0x01, 0x50, 0xef, 0xe2, 0x01, 0x60, 0xef, 0xe2, 0x01, 0x40, 0xff, 0xe2, 0x01, 0x50, 0xff, 0xe2, 0x01, 0x60, 0xff, 0xe2, 0x01, 0x40, 0xef, 0xb1, 0x00, 0x50, 0xef, 0xb1, 0x00, 0x60, 0xef, 0xb1, 0x00, 0x70, 0xef, 0xb1, 0x00, 0x40, 0xff, 0xb1, 0x00, 0x50, 0xff, 0xb1, 0x00, 0x60, 0xff, 0xb1, 0x00, 0x70, 0xff, 0xb1, 0x00, 0x40, 0xef, 0xf2, 0x00, 0x50, 0xef, 0xf2, 0x00, 0x60, 0xef, 0xf2, 0x00, 0x70, 0xef, 0xf2, 0x00, 0x40, 0xff, 0xf2, 0x00, 0x50, 0xff, 0xf2, 0x00, 0x60, 0xff, 0xf2, 0x00, 0x70, 0xff, 0xf2, 0x00, 0xc0, 0xef, 0xa2, 0x04, 0xd0, 0xef, 0xa2, 0x04, 0xe0, 0xef, 0xa2, 0x04, 0xc0, 0xff, 0xa2, 0x04, 0xd0, 0xff, 0xa2, 0x04, 0xe0, 0xff, 0xa2, 0x04 ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ]
+    expected:
+      insns:
+        -
+          asm_text: "vadd.i8 d16, d17, d16"
+        -
+          asm_text: "vadd.i16 d16, d17, d16"
+        -
+          asm_text: "vadd.i64 d16, d17, d16"
+        -
+          asm_text: "vadd.i32 d16, d17, d16"
+        -
+          asm_text: "vadd.f32 d16, d16, d17"
+        -
+          asm_text: "vadd.f32 q8, q8, q9"
+        -
+          asm_text: "vaddl.s8 q8, d17, d16"
+        -
+          asm_text: "vaddl.s16 q8, d17, d16"
+        -
+          asm_text: "vaddl.s32 q8, d17, d16"
+        -
+          asm_text: "vaddl.u8 q8, d17, d16"
+        -
+          asm_text: "vaddl.u16 q8, d17, d16"
+        -
+          asm_text: "vaddl.u32 q8, d17, d16"
+        -
+          asm_text: "vaddw.s8 q8, q8, d18"
+        -
+          asm_text: "vaddw.s16 q8, q8, d18"
+        -
+          asm_text: "vaddw.s32 q8, q8, d18"
+        -
+          asm_text: "vaddw.u8 q8, q8, d18"
+        -
+          asm_text: "vaddw.u16 q8, q8, d18"
+        -
+          asm_text: "vaddw.u32 q8, q8, d18"
+        -
+          asm_text: "vhadd.s8 d16, d16, d17"
+        -
+          asm_text: "vhadd.s16 d16, d16, d17"
+        -
+          asm_text: "vhadd.s32 d16, d16, d17"
+        -
+          asm_text: "vhadd.u8 d16, d16, d17"
+        -
+          asm_text: "vhadd.u16 d16, d16, d17"
+        -
+          asm_text: "vhadd.u32 d16, d16, d17"
+        -
+          asm_text: "vhadd.s8 q8, q8, q9"
+        -
+          asm_text: "vhadd.s16 q8, q8, q9"
+        -
+          asm_text: "vhadd.s32 q8, q8, q9"
+        -
+          asm_text: "vhadd.u8 q8, q8, q9"
+        -
+          asm_text: "vhadd.u16 q8, q8, q9"
+        -
+          asm_text: "vhadd.u32 q8, q8, q9"
+        -
+          asm_text: "vrhadd.s8 d16, d16, d17"
+        -
+          asm_text: "vrhadd.s16 d16, d16, d17"
+        -
+          asm_text: "vrhadd.s32 d16, d16, d17"
+        -
+          asm_text: "vrhadd.u8 d16, d16, d17"
+        -
+          asm_text: "vrhadd.u16 d16, d16, d17"
+        -
+          asm_text: "vrhadd.u32 d16, d16, d17"
+        -
+          asm_text: "vrhadd.s8 q8, q8, q9"
+        -
+          asm_text: "vrhadd.s16 q8, q8, q9"
+        -
+          asm_text: "vrhadd.s32 q8, q8, q9"
+        -
+          asm_text: "vrhadd.u8 q8, q8, q9"
+        -
+          asm_text: "vrhadd.u16 q8, q8, q9"
+        -
+          asm_text: "vrhadd.u32 q8, q8, q9"
+        -
+          asm_text: "vqadd.s8 d16, d16, d17"
+        -
+          asm_text: "vqadd.s16 d16, d16, d17"
+        -
+          asm_text: "vqadd.s32 d16, d16, d17"
+        -
+          asm_text: "vqadd.s64 d16, d16, d17"
+        -
+          asm_text: "vqadd.u8 d16, d16, d17"
+        -
+          asm_text: "vqadd.u16 d16, d16, d17"
+        -
+          asm_text: "vqadd.u32 d16, d16, d17"
+        -
+          asm_text: "vqadd.u64 d16, d16, d17"
+        -
+          asm_text: "vqadd.s8 q8, q8, q9"
+        -
+          asm_text: "vqadd.s16 q8, q8, q9"
+        -
+          asm_text: "vqadd.s32 q8, q8, q9"
+        -
+          asm_text: "vqadd.s64 q8, q8, q9"
+        -
+          asm_text: "vqadd.u8 q8, q8, q9"
+        -
+          asm_text: "vqadd.u16 q8, q8, q9"
+        -
+          asm_text: "vqadd.u32 q8, q8, q9"
+        -
+          asm_text: "vqadd.u64 q8, q8, q9"
+        -
+          asm_text: "vaddhn.i16 d16, q8, q9"
+        -
+          asm_text: "vaddhn.i32 d16, q8, q9"
+        -
+          asm_text: "vaddhn.i64 d16, q8, q9"
+        -
+          asm_text: "vraddhn.i16 d16, q8, q9"
+        -
+          asm_text: "vraddhn.i32 d16, q8, q9"
+        -
+          asm_text: "vraddhn.i64 d16, q8, q9"
diff --git a/tests/MC/ARM/neont2-bitcount-encoding.s.yaml b/tests/MC/ARM/neont2-bitcount-encoding.s.yaml
new file mode 100644
index 000000000..446c5fe34
--- /dev/null
+++ b/tests/MC/ARM/neont2-bitcount-encoding.s.yaml
@@ -0,0 +1,36 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xf0, 0xff, 0x20, 0x05, 0xf0, 0xff, 0x60, 0x05, 0xf0, 0xff, 0xa0, 0x04, 0xf4, 0xff, 0xa0, 0x04, 0xf8, 0xff, 0xa0, 0x04, 0xf0, 0xff, 0xe0, 0x04, 0xf4, 0xff, 0xe0, 0x04, 0xf8, 0xff, 0xe0, 0x04, 0xf0, 0xff, 0x20, 0x04, 0xf4, 0xff, 0x20, 0x04, 0xf8, 0xff, 0x20, 0x04, 0xf0, 0xff, 0x60, 0x04, 0xf4, 0xff, 0x60, 0x04, 0xf8, 0xff, 0x60, 0x04 ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcnt.8 d16, d16"
+        -
+          asm_text: "vcnt.8 q8, q8"
+        -
+          asm_text: "vclz.i8 d16, d16"
+        -
+          asm_text: "vclz.i16 d16, d16"
+        -
+          asm_text: "vclz.i32 d16, d16"
+        -
+          asm_text: "vclz.i8 q8, q8"
+        -
+          asm_text: "vclz.i16 q8, q8"
+        -
+          asm_text: "vclz.i32 q8, q8"
+        -
+          asm_text: "vcls.s8 d16, d16"
+        -
+          asm_text: "vcls.s16 d16, d16"
+        -
+          asm_text: "vcls.s32 d16, d16"
+        -
+          asm_text: "vcls.s8 q8, q8"
+        -
+          asm_text: "vcls.s16 q8, q8"
+        -
+          asm_text: "vcls.s32 q8, q8"
diff --git a/tests/MC/ARM/neont2-bitwise-encoding.s.yaml b/tests/MC/ARM/neont2-bitwise-encoding.s.yaml
new file mode 100644
index 000000000..ade8ef8c9
--- /dev/null
+++ b/tests/MC/ARM/neont2-bitwise-encoding.s.yaml
@@ -0,0 +1,44 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x41, 0xef, 0xb0, 0x01, 0x40, 0xef, 0xf2, 0x01, 0x41, 0xff, 0xb0, 0x01, 0x40, 0xff, 0xf2, 0x01, 0x61, 0xef, 0xb0, 0x01, 0x60, 0xef, 0xf2, 0x01, 0x51, 0xef, 0xb0, 0x01, 0x50, 0xef, 0xf2, 0x01, 0x71, 0xef, 0xb0, 0x01, 0x70, 0xef, 0xf2, 0x01, 0xf0, 0xff, 0xa0, 0x05, 0xf0, 0xff, 0xe0, 0x05, 0x51, 0xff, 0xb0, 0x21, 0x54, 0xff, 0xf2, 0x01, 0x61, 0xff, 0xb0, 0x21, 0x64, 0xff, 0xf2, 0x01, 0x71, 0xff, 0xb0, 0x21, 0x74, 0xff, 0xf2, 0x01 ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ]
+    expected:
+      insns:
+        -
+          asm_text: "vand d16, d17, d16"
+        -
+          asm_text: "vand q8, q8, q9"
+        -
+          asm_text: "veor d16, d17, d16"
+        -
+          asm_text: "veor q8, q8, q9"
+        -
+          asm_text: "vorr d16, d17, d16"
+        -
+          asm_text: "vorr q8, q8, q9"
+        -
+          asm_text: "vbic d16, d17, d16"
+        -
+          asm_text: "vbic q8, q8, q9"
+        -
+          asm_text: "vorn d16, d17, d16"
+        -
+          asm_text: "vorn q8, q8, q9"
+        -
+          asm_text: "vmvn d16, d16"
+        -
+          asm_text: "vmvn q8, q8"
+        -
+          asm_text: "vbsl d18, d17, d16"
+        -
+          asm_text: "vbsl q8, q10, q9"
+        -
+          asm_text: "vbit d18, d17, d16"
+        -
+          asm_text: "vbit q8, q10, q9"
+        -
+          asm_text: "vbif d18, d17, d16"
+        -
+          asm_text: "vbif q8, q10, q9"
diff --git a/tests/MC/ARM/neont2-cmp-encoding.s.yaml b/tests/MC/ARM/neont2-cmp-encoding.s.yaml
new file mode 100644
index 000000000..b83a7f633
--- /dev/null
+++ b/tests/MC/ARM/neont2-cmp-encoding.s.yaml
@@ -0,0 +1,40 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xfb, 0xff, 0x20, 0x07, 0xfb, 0xff, 0xa0, 0x07, 0xfb, 0xff, 0x20, 0x06, 0xfb, 0xff, 0xa0, 0x06, 0xfb, 0xff, 0x60, 0x07, 0xfb, 0xff, 0xe0, 0x07, 0xfb, 0xff, 0x60, 0x06, 0xfb, 0xff, 0xe0, 0x06, 0xff, 0xef, 0x30, 0x0f, 0xff, 0xff, 0x30, 0x0f, 0xff, 0xef, 0x30, 0x0e, 0xff, 0xff, 0x30, 0x0e, 0xff, 0xef, 0x70, 0x0f, 0xff, 0xff, 0x70, 0x0f, 0xff, 0xef, 0x70, 0x0e, 0xff, 0xff, 0x70, 0x0e ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvt.s32.f32 d16, d16"
+        -
+          asm_text: "vcvt.u32.f32 d16, d16"
+        -
+          asm_text: "vcvt.f32.s32 d16, d16"
+        -
+          asm_text: "vcvt.f32.u32 d16, d16"
+        -
+          asm_text: "vcvt.s32.f32 q8, q8"
+        -
+          asm_text: "vcvt.u32.f32 q8, q8"
+        -
+          asm_text: "vcvt.f32.s32 q8, q8"
+        -
+          asm_text: "vcvt.f32.u32 q8, q8"
+        -
+          asm_text: "vcvt.s32.f32 d16, d16, #1"
+        -
+          asm_text: "vcvt.u32.f32 d16, d16, #1"
+        -
+          asm_text: "vcvt.f32.s32 d16, d16, #1"
+        -
+          asm_text: "vcvt.f32.u32 d16, d16, #1"
+        -
+          asm_text: "vcvt.s32.f32 q8, q8, #1"
+        -
+          asm_text: "vcvt.u32.f32 q8, q8, #1"
+        -
+          asm_text: "vcvt.f32.s32 q8, q8, #1"
+        -
+          asm_text: "vcvt.f32.u32 q8, q8, #1"
diff --git a/tests/MC/ARM/neont2-convert-encoding.s.yaml b/tests/MC/ARM/neont2-convert-encoding.s.yaml
new file mode 100644
index 000000000..e2450a03d
--- /dev/null
+++ b/tests/MC/ARM/neont2-convert-encoding.s.yaml
@@ -0,0 +1,44 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xfb, 0xff, 0x20, 0x07, 0xfb, 0xff, 0xa0, 0x07, 0xfb, 0xff, 0x20, 0x06, 0xfb, 0xff, 0xa0, 0x06, 0xfb, 0xff, 0x60, 0x07, 0xfb, 0xff, 0xe0, 0x07, 0xfb, 0xff, 0x60, 0x06, 0xfb, 0xff, 0xe0, 0x06, 0xff, 0xef, 0x30, 0x0f, 0xff, 0xff, 0x30, 0x0f, 0xff, 0xef, 0x30, 0x0e, 0xff, 0xff, 0x30, 0x0e, 0xff, 0xef, 0x70, 0x0f, 0xff, 0xff, 0x70, 0x0f, 0xff, 0xef, 0x70, 0x0e, 0xff, 0xff, 0x70, 0x0e, 0xf6, 0xff, 0x20, 0x07, 0xf6, 0xff, 0x20, 0x06 ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvt.s32.f32 d16, d16"
+        -
+          asm_text: "vcvt.u32.f32 d16, d16"
+        -
+          asm_text: "vcvt.f32.s32 d16, d16"
+        -
+          asm_text: "vcvt.f32.u32 d16, d16"
+        -
+          asm_text: "vcvt.s32.f32 q8, q8"
+        -
+          asm_text: "vcvt.u32.f32 q8, q8"
+        -
+          asm_text: "vcvt.f32.s32 q8, q8"
+        -
+          asm_text: "vcvt.f32.u32 q8, q8"
+        -
+          asm_text: "vcvt.s32.f32 d16, d16, #1"
+        -
+          asm_text: "vcvt.u32.f32 d16, d16, #1"
+        -
+          asm_text: "vcvt.f32.s32 d16, d16, #1"
+        -
+          asm_text: "vcvt.f32.u32 d16, d16, #1"
+        -
+          asm_text: "vcvt.s32.f32 q8, q8, #1"
+        -
+          asm_text: "vcvt.u32.f32 q8, q8, #1"
+        -
+          asm_text: "vcvt.f32.s32 q8, q8, #1"
+        -
+          asm_text: "vcvt.f32.u32 q8, q8, #1"
+        -
+          asm_text: "vcvt.f32.f16 q8, d16"
+        -
+          asm_text: "vcvt.f16.f32 d16, q8"
diff --git a/tests/MC/ARM/neont2-dup-encoding.s.yaml b/tests/MC/ARM/neont2-dup-encoding.s.yaml
new file mode 100644
index 000000000..10ecb4997
--- /dev/null
+++ b/tests/MC/ARM/neont2-dup-encoding.s.yaml
@@ -0,0 +1,44 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xc0, 0xee, 0x90, 0x1b, 0x8f, 0xee, 0x30, 0x2b, 0x8e, 0xee, 0x10, 0x3b, 0xe2, 0xee, 0x90, 0x4b, 0xa0, 0xee, 0xb0, 0x5b, 0xae, 0xee, 0x10, 0x6b, 0xf1, 0xff, 0x0b, 0x0c, 0xf2, 0xff, 0x0c, 0x1c, 0xf4, 0xff, 0x0d, 0x2c, 0xb1, 0xff, 0x4a, 0x6c, 0xf2, 0xff, 0x49, 0x2c, 0xf4, 0xff, 0x48, 0x0c, 0xf3, 0xff, 0x0b, 0x0c, 0xf6, 0xff, 0x0c, 0x1c, 0xfc, 0xff, 0x0d, 0x2c, 0xb3, 0xff, 0x4a, 0x6c, 0xf6, 0xff, 0x49, 0x2c, 0xfc, 0xff, 0x48, 0x0c ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ]
+    expected:
+      insns:
+        -
+          asm_text: "vdup.8 d16, r1"
+        -
+          asm_text: "vdup.16 d15, r2"
+        -
+          asm_text: "vdup.32 d14, r3"
+        -
+          asm_text: "vdup.8 q9, r4"
+        -
+          asm_text: "vdup.16 q8, r5"
+        -
+          asm_text: "vdup.32 q7, r6"
+        -
+          asm_text: "vdup.8 d16, d11[0]"
+        -
+          asm_text: "vdup.16 d17, d12[0]"
+        -
+          asm_text: "vdup.32 d18, d13[0]"
+        -
+          asm_text: "vdup.8 q3, d10[0]"
+        -
+          asm_text: "vdup.16 q9, d9[0]"
+        -
+          asm_text: "vdup.32 q8, d8[0]"
+        -
+          asm_text: "vdup.8 d16, d11[1]"
+        -
+          asm_text: "vdup.16 d17, d12[1]"
+        -
+          asm_text: "vdup.32 d18, d13[1]"
+        -
+          asm_text: "vdup.8 q3, d10[1]"
+        -
+          asm_text: "vdup.16 q9, d9[1]"
+        -
+          asm_text: "vdup.32 q8, d8[1]"
diff --git a/tests/MC/ARM/neont2-minmax-encoding.s.yaml b/tests/MC/ARM/neont2-minmax-encoding.s.yaml
new file mode 100644
index 000000000..b78bb4164
--- /dev/null
+++ b/tests/MC/ARM/neont2-minmax-encoding.s.yaml
@@ -0,0 +1,120 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x02, 0xef, 0x03, 0x16, 0x15, 0xef, 0x06, 0x46, 0x28, 0xef, 0x09, 0x76, 0x0b, 0xff, 0x0c, 0xa6, 0x1e, 0xff, 0x0f, 0xd6, 0x61, 0xff, 0xa2, 0x06, 0x44, 0xef, 0xa5, 0x3f, 0x02, 0xef, 0x03, 0x26, 0x15, 0xef, 0x06, 0x56, 0x28, 0xef, 0x09, 0x86, 0x0b, 0xff, 0x0c, 0xb6, 0x1e, 0xff, 0x0f, 0xe6, 0x61, 0xff, 0xa2, 0x16, 0x44, 0xef, 0xa5, 0x4f, 0x04, 0xef, 0x46, 0x26, 0x1a, 0xef, 0x4c, 0x86, 0x20, 0xef, 0xe2, 0xe6, 0x46, 0xff, 0xe8, 0x46, 0x5c, 0xff, 0xee, 0xa6, 0x2e, 0xff, 0x60, 0xc6, 0x4a, 0xef, 0x42, 0x2f, 0x04, 0xef, 0x46, 0x46, 0x1a, 0xef, 0x4c, 0xa6, 0x60, 0xef, 0xe2, 0x06, 0x46, 0xff, 0xc4, 0x66, 0x18, 0xff, 0x4a, 0x86, 0x2e, 0xff, 0x60, 0xe6, 0x04, 0xef, 0x42, 0x4f, 0x02, 0xef, 0x13, 0x16, 0x15, 0xef, 0x16, 0x46, 0x28, 0xef, 0x19, 0x76, 0x0b, 0xff, 0x1c, 0xa6, 0x1e, 0xff, 0x1f, 0xd6, 0x61, 0xff, 0xb2, 0x06, 0x64, 0xef, 0xa5, 0x3f, 0x02, 0xef, 0x13, 0x26, 0x15, 0xef, 0x16, 0x56, 0x28, 0xef, 0x19, 0x86, 0x0b, 0xff, 0x1c, 0xb6, 0x1e, 0xff, 0x1f, 0xe6, 0x61, 0xff, 0xb2, 0x16, 0x64, 0xef, 0xa5, 0x4f, 0x04, 0xef, 0x56, 0x26, 0x1a, 0xef, 0x5c, 0x86, 0x20, 0xef, 0xf2, 0xe6, 0x46, 0xff, 0xf8, 0x46, 0x5c, 0xff, 0xfe, 0xa6, 0x2e, 0xff, 0x70, 0xc6, 0x6a, 0xef, 0x42, 0x2f, 0x04, 0xef, 0x56, 0x46, 0x1a, 0xef, 0x5c, 0xa6, 0x60, 0xef, 0xf2, 0x06, 0x46, 0xff, 0xd4, 0x66, 0x18, 0xff, 0x5a, 0x86, 0x2e, 0xff, 0x70, 0xe6, 0x24, 0xef, 0x42, 0x4f ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmax.s8 d1, d2, d3"
+        -
+          asm_text: "vmax.s16 d4, d5, d6"
+        -
+          asm_text: "vmax.s32 d7, d8, d9"
+        -
+          asm_text: "vmax.u8 d10, d11, d12"
+        -
+          asm_text: "vmax.u16 d13, d14, d15"
+        -
+          asm_text: "vmax.u32 d16, d17, d18"
+        -
+          asm_text: "vmax.f32 d19, d20, d21"
+        -
+          asm_text: "vmax.s8 d2, d2, d3"
+        -
+          asm_text: "vmax.s16 d5, d5, d6"
+        -
+          asm_text: "vmax.s32 d8, d8, d9"
+        -
+          asm_text: "vmax.u8 d11, d11, d12"
+        -
+          asm_text: "vmax.u16 d14, d14, d15"
+        -
+          asm_text: "vmax.u32 d17, d17, d18"
+        -
+          asm_text: "vmax.f32 d20, d20, d21"
+        -
+          asm_text: "vmax.s8 q1, q2, q3"
+        -
+          asm_text: "vmax.s16 q4, q5, q6"
+        -
+          asm_text: "vmax.s32 q7, q8, q9"
+        -
+          asm_text: "vmax.u8 q10, q11, q12"
+        -
+          asm_text: "vmax.u16 q13, q14, q15"
+        -
+          asm_text: "vmax.u32 q6, q7, q8"
+        -
+          asm_text: "vmax.f32 q9, q5, q1"
+        -
+          asm_text: "vmax.s8 q2, q2, q3"
+        -
+          asm_text: "vmax.s16 q5, q5, q6"
+        -
+          asm_text: "vmax.s32 q8, q8, q9"
+        -
+          asm_text: "vmax.u8 q11, q11, q2"
+        -
+          asm_text: "vmax.u16 q4, q4, q5"
+        -
+          asm_text: "vmax.u32 q7, q7, q8"
+        -
+          asm_text: "vmax.f32 q2, q2, q1"
+        -
+          asm_text: "vmin.s8 d1, d2, d3"
+        -
+          asm_text: "vmin.s16 d4, d5, d6"
+        -
+          asm_text: "vmin.s32 d7, d8, d9"
+        -
+          asm_text: "vmin.u8 d10, d11, d12"
+        -
+          asm_text: "vmin.u16 d13, d14, d15"
+        -
+          asm_text: "vmin.u32 d16, d17, d18"
+        -
+          asm_text: "vmin.f32 d19, d20, d21"
+        -
+          asm_text: "vmin.s8 d2, d2, d3"
+        -
+          asm_text: "vmin.s16 d5, d5, d6"
+        -
+          asm_text: "vmin.s32 d8, d8, d9"
+        -
+          asm_text: "vmin.u8 d11, d11, d12"
+        -
+          asm_text: "vmin.u16 d14, d14, d15"
+        -
+          asm_text: "vmin.u32 d17, d17, d18"
+        -
+          asm_text: "vmin.f32 d20, d20, d21"
+        -
+          asm_text: "vmin.s8 q1, q2, q3"
+        -
+          asm_text: "vmin.s16 q4, q5, q6"
+        -
+          asm_text: "vmin.s32 q7, q8, q9"
+        -
+          asm_text: "vmin.u8 q10, q11, q12"
+        -
+          asm_text: "vmin.u16 q13, q14, q15"
+        -
+          asm_text: "vmin.u32 q6, q7, q8"
+        -
+          asm_text: "vmin.f32 q9, q5, q1"
+        -
+          asm_text: "vmin.s8 q2, q2, q3"
+        -
+          asm_text: "vmin.s16 q5, q5, q6"
+        -
+          asm_text: "vmin.s32 q8, q8, q9"
+        -
+          asm_text: "vmin.u8 q11, q11, q2"
+        -
+          asm_text: "vmin.u16 q4, q4, q5"
+        -
+          asm_text: "vmin.u32 q7, q7, q8"
+        -
+          asm_text: "vmin.f32 q2, q2, q1"
diff --git a/tests/MC/ARM/neont2-mov-encoding.s.yaml b/tests/MC/ARM/neont2-mov-encoding.s.yaml
new file mode 100644
index 000000000..c0b06abc1
--- /dev/null
+++ b/tests/MC/ARM/neont2-mov-encoding.s.yaml
@@ -0,0 +1,122 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xc0, 0xef, 0x18, 0x0e, 0xc1, 0xef, 0x10, 0x08, 0xc1, 0xef, 0x10, 0x0a, 0xc2, 0xef, 0x10, 0x00, 0xc2, 0xef, 0x10, 0x02, 0xc2, 0xef, 0x10, 0x04, 0xc2, 0xef, 0x10, 0x06, 0xc2, 0xef, 0x10, 0x0c, 0xc2, 0xef, 0x10, 0x0d, 0xc1, 0xff, 0x33, 0x0e, 0xc0, 0xef, 0x58, 0x0e, 0xc1, 0xef, 0x50, 0x08, 0xc1, 0xef, 0x50, 0x0a, 0xc2, 0xef, 0x50, 0x00, 0xc2, 0xef, 0x50, 0x02, 0xc2, 0xef, 0x50, 0x04, 0xc2, 0xef, 0x50, 0x06, 0xc2, 0xef, 0x50, 0x0c, 0xc2, 0xef, 0x50, 0x0d, 0xc1, 0xff, 0x73, 0x0e, 0xc1, 0xef, 0x30, 0x08, 0xc1, 0xef, 0x30, 0x0a, 0xc2, 0xef, 0x30, 0x00, 0xc2, 0xef, 0x30, 0x02, 0xc2, 0xef, 0x30, 0x04, 0xc2, 0xef, 0x30, 0x06, 0xc2, 0xef, 0x30, 0x0c, 0xc2, 0xef, 0x30, 0x0d, 0xc8, 0xef, 0x30, 0x0a, 0xd0, 0xef, 0x30, 0x0a, 0xe0, 0xef, 0x30, 0x0a, 0xc8, 0xff, 0x30, 0x0a, 0xd0, 0xff, 0x30, 0x0a, 0xe0, 0xff, 0x30, 0x0a, 0xf2, 0xff, 0x20, 0x02, 0xf6, 0xff, 0x20, 0x02, 0xfa, 0xff, 0x20, 0x02, 0xf2, 0xff, 0xa0, 0x02, 0xf6, 0xff, 0xa0, 0x02, 0xfa, 0xff, 0xa0, 0x02, 0xf2, 0xff, 0xe0, 0x02, 0xf6, 0xff, 0xe0, 0x02, 0xfa, 0xff, 0xe0, 0x02, 0xf2, 0xff, 0x60, 0x02, 0xf6, 0xff, 0x60, 0x02, 0xfa, 0xff, 0x60, 0x02, 0x50, 0xee, 0xb0, 0x0b, 0x10, 0xee, 0xf0, 0x0b, 0xd0, 0xee, 0xb0, 0x0b, 0x90, 0xee, 0xf0, 0x0b, 0x30, 0xee, 0x90, 0x0b, 0x40, 0xee, 0xb0, 0x1b, 0x00, 0xee, 0xf0, 0x1b, 0x20, 0xee, 0x90, 0x1b, 0x42, 0xee, 0xb0, 0x1b, 0x02, 0xee, 0xf0, 0x1b, 0x22, 0xee, 0x90, 0x1b ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmov.i8 d16, #0x8"
+        -
+          asm_text: "vmov.i16 d16, #0x10"
+        -
+          asm_text: "vmov.i16 d16, #0x1000"
+        -
+          asm_text: "vmov.i32 d16, #0x20"
+        -
+          asm_text: "vmov.i32 d16, #0x2000"
+        -
+          asm_text: "vmov.i32 d16, #0x200000"
+        -
+          asm_text: "vmov.i32 d16, #0x20000000"
+        -
+          asm_text: "vmov.i32 d16, #0x20ff"
+        -
+          asm_text: "vmov.i32 d16, #0x20ffff"
+        -
+          asm_text: "vmov.i64 d16, #0xff0000ff0000ffff"
+        -
+          asm_text: "vmov.i8 q8, #0x8"
+        -
+          asm_text: "vmov.i16 q8, #0x10"
+        -
+          asm_text: "vmov.i16 q8, #0x1000"
+        -
+          asm_text: "vmov.i32 q8, #0x20"
+        -
+          asm_text: "vmov.i32 q8, #0x2000"
+        -
+          asm_text: "vmov.i32 q8, #0x200000"
+        -
+          asm_text: "vmov.i32 q8, #0x20000000"
+        -
+          asm_text: "vmov.i32 q8, #0x20ff"
+        -
+          asm_text: "vmov.i32 q8, #0x20ffff"
+        -
+          asm_text: "vmov.i64 q8, #0xff0000ff0000ffff"
+        -
+          asm_text: "vmvn.i16 d16, #0x10"
+        -
+          asm_text: "vmvn.i16 d16, #0x1000"
+        -
+          asm_text: "vmvn.i32 d16, #0x20"
+        -
+          asm_text: "vmvn.i32 d16, #0x2000"
+        -
+          asm_text: "vmvn.i32 d16, #0x200000"
+        -
+          asm_text: "vmvn.i32 d16, #0x20000000"
+        -
+          asm_text: "vmvn.i32 d16, #0x20ff"
+        -
+          asm_text: "vmvn.i32 d16, #0x20ffff"
+        -
+          asm_text: "vmovl.s8 q8, d16"
+        -
+          asm_text: "vmovl.s16 q8, d16"
+        -
+          asm_text: "vmovl.s32 q8, d16"
+        -
+          asm_text: "vmovl.u8 q8, d16"
+        -
+          asm_text: "vmovl.u16 q8, d16"
+        -
+          asm_text: "vmovl.u32 q8, d16"
+        -
+          asm_text: "vmovn.i16 d16, q8"
+        -
+          asm_text: "vmovn.i32 d16, q8"
+        -
+          asm_text: "vmovn.i64 d16, q8"
+        -
+          asm_text: "vqmovn.s16 d16, q8"
+        -
+          asm_text: "vqmovn.s32 d16, q8"
+        -
+          asm_text: "vqmovn.s64 d16, q8"
+        -
+          asm_text: "vqmovn.u16 d16, q8"
+        -
+          asm_text: "vqmovn.u32 d16, q8"
+        -
+          asm_text: "vqmovn.u64 d16, q8"
+        -
+          asm_text: "vqmovun.s16 d16, q8"
+        -
+          asm_text: "vqmovun.s32 d16, q8"
+        -
+          asm_text: "vqmovun.s64 d16, q8"
+        -
+          asm_text: "vmov.s8 r0, d16[1]"
+        -
+          asm_text: "vmov.s16 r0, d16[1]"
+        -
+          asm_text: "vmov.u8 r0, d16[1]"
+        -
+          asm_text: "vmov.u16 r0, d16[1]"
+        -
+          asm_text: "vmov.32 r0, d16[1]"
+        -
+          asm_text: "vmov.8 d16[1], r1"
+        -
+          asm_text: "vmov.16 d16[1], r1"
+        -
+          asm_text: "vmov.32 d16[1], r1"
+        -
+          asm_text: "vmov.8 d18[1], r1"
+        -
+          asm_text: "vmov.16 d18[1], r1"
+        -
+          asm_text: "vmov.32 d18[1], r1"
diff --git a/tests/MC/ARM/neont2-mul-accum-encoding.s.yaml b/tests/MC/ARM/neont2-mul-accum-encoding.s.yaml
new file mode 100644
index 000000000..d861d51a9
--- /dev/null
+++ b/tests/MC/ARM/neont2-mul-accum-encoding.s.yaml
@@ -0,0 +1,88 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x42, 0xef, 0xa1, 0x09, 0x52, 0xef, 0xa1, 0x09, 0x62, 0xef, 0xa1, 0x09, 0x42, 0xef, 0xb1, 0x0d, 0x40, 0xef, 0xe4, 0x29, 0x50, 0xef, 0xe4, 0x29, 0x60, 0xef, 0xe4, 0x29, 0x40, 0xef, 0xf4, 0x2d, 0xe0, 0xff, 0xc3, 0x80, 0xc3, 0xef, 0xa2, 0x08, 0xd3, 0xef, 0xa2, 0x08, 0xe3, 0xef, 0xa2, 0x08, 0xc3, 0xff, 0xa2, 0x08, 0xd3, 0xff, 0xa2, 0x08, 0xe3, 0xff, 0xa2, 0x08, 0xa5, 0xef, 0x4a, 0x02, 0xd3, 0xef, 0xa2, 0x09, 0xe3, 0xef, 0xa2, 0x09, 0xdb, 0xef, 0x47, 0x63, 0xdb, 0xef, 0x4f, 0x63, 0xdb, 0xef, 0x67, 0x63, 0xdb, 0xef, 0x6f, 0x63, 0x42, 0xff, 0xa1, 0x09, 0x52, 0xff, 0xa1, 0x09, 0x62, 0xff, 0xa1, 0x09, 0x62, 0xef, 0xb1, 0x0d, 0x40, 0xff, 0xe4, 0x29, 0x50, 0xff, 0xe4, 0x29, 0x60, 0xff, 0xe4, 0x29, 0x60, 0xef, 0xf4, 0x2d, 0x98, 0xff, 0xe6, 0x84, 0xc3, 0xef, 0xa2, 0x0a, 0xd3, 0xef, 0xa2, 0x0a, 0xe3, 0xef, 0xa2, 0x0a, 0xc3, 0xff, 0xa2, 0x0a, 0xd3, 0xff, 0xa2, 0x0a, 0xe3, 0xff, 0xa2, 0x0a, 0xd9, 0xff, 0xe9, 0x66, 0xd3, 0xef, 0xa2, 0x0b, 0xe3, 0xef, 0xa2, 0x0b ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmla.i8 d16, d18, d17"
+        -
+          asm_text: "vmla.i16 d16, d18, d17"
+        -
+          asm_text: "vmla.i32 d16, d18, d17"
+        -
+          asm_text: "vmla.f32 d16, d18, d17"
+        -
+          asm_text: "vmla.i8 q9, q8, q10"
+        -
+          asm_text: "vmla.i16 q9, q8, q10"
+        -
+          asm_text: "vmla.i32 q9, q8, q10"
+        -
+          asm_text: "vmla.f32 q9, q8, q10"
+        -
+          asm_text: "vmla.i32 q12, q8, d3[0]"
+        -
+          asm_text: "vmlal.s8 q8, d19, d18"
+        -
+          asm_text: "vmlal.s16 q8, d19, d18"
+        -
+          asm_text: "vmlal.s32 q8, d19, d18"
+        -
+          asm_text: "vmlal.u8 q8, d19, d18"
+        -
+          asm_text: "vmlal.u16 q8, d19, d18"
+        -
+          asm_text: "vmlal.u32 q8, d19, d18"
+        -
+          asm_text: "vmlal.s32 q0, d5, d10[0]"
+        -
+          asm_text: "vqdmlal.s16 q8, d19, d18"
+        -
+          asm_text: "vqdmlal.s32 q8, d19, d18"
+        -
+          asm_text: "vqdmlal.s16 q11, d11, d7[0]"
+        -
+          asm_text: "vqdmlal.s16 q11, d11, d7[1]"
+        -
+          asm_text: "vqdmlal.s16 q11, d11, d7[2]"
+        -
+          asm_text: "vqdmlal.s16 q11, d11, d7[3]"
+        -
+          asm_text: "vmls.i8 d16, d18, d17"
+        -
+          asm_text: "vmls.i16 d16, d18, d17"
+        -
+          asm_text: "vmls.i32 d16, d18, d17"
+        -
+          asm_text: "vmls.f32 d16, d18, d17"
+        -
+          asm_text: "vmls.i8 q9, q8, q10"
+        -
+          asm_text: "vmls.i16 q9, q8, q10"
+        -
+          asm_text: "vmls.i32 q9, q8, q10"
+        -
+          asm_text: "vmls.f32 q9, q8, q10"
+        -
+          asm_text: "vmls.i16 q4, q12, d6[2]"
+        -
+          asm_text: "vmlsl.s8 q8, d19, d18"
+        -
+          asm_text: "vmlsl.s16 q8, d19, d18"
+        -
+          asm_text: "vmlsl.s32 q8, d19, d18"
+        -
+          asm_text: "vmlsl.u8 q8, d19, d18"
+        -
+          asm_text: "vmlsl.u16 q8, d19, d18"
+        -
+          asm_text: "vmlsl.u32 q8, d19, d18"
+        -
+          asm_text: "vmlsl.u16 q11, d25, d1[3]"
+        -
+          asm_text: "vqdmlsl.s16 q8, d19, d18"
+        -
+          asm_text: "vqdmlsl.s32 q8, d19, d18"
diff --git a/tests/MC/ARM/neont2-mul-encoding.s.yaml b/tests/MC/ARM/neont2-mul-encoding.s.yaml
new file mode 100644
index 000000000..eb2b66b61
--- /dev/null
+++ b/tests/MC/ARM/neont2-mul-encoding.s.yaml
@@ -0,0 +1,68 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x40, 0xef, 0xb1, 0x09, 0x50, 0xef, 0xb1, 0x09, 0x60, 0xef, 0xb1, 0x09, 0x40, 0xff, 0xb1, 0x0d, 0x40, 0xef, 0xf2, 0x09, 0x50, 0xef, 0xf2, 0x09, 0x60, 0xef, 0xf2, 0x09, 0x40, 0xff, 0xf2, 0x0d, 0x40, 0xff, 0xb1, 0x09, 0x40, 0xff, 0xf2, 0x09, 0xd8, 0xef, 0x68, 0x28, 0x50, 0xef, 0xa1, 0x0b, 0x60, 0xef, 0xa1, 0x0b, 0x50, 0xef, 0xe2, 0x0b, 0x60, 0xef, 0xe2, 0x0b, 0x92, 0xef, 0x43, 0xbc, 0x50, 0xff, 0xa1, 0x0b, 0x60, 0xff, 0xa1, 0x0b, 0x50, 0xff, 0xe2, 0x0b, 0x60, 0xff, 0xe2, 0x0b, 0xc0, 0xef, 0xa1, 0x0c, 0xd0, 0xef, 0xa1, 0x0c, 0xe0, 0xef, 0xa1, 0x0c, 0xc0, 0xff, 0xa1, 0x0c, 0xd0, 0xff, 0xa1, 0x0c, 0xe0, 0xff, 0xa1, 0x0c, 0xc0, 0xef, 0xa1, 0x0e, 0xd0, 0xef, 0xa1, 0x0d, 0xe0, 0xef, 0xa1, 0x0d, 0x97, 0xef, 0x49, 0x2b ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmul.i8 d16, d16, d17"
+        -
+          asm_text: "vmul.i16 d16, d16, d17"
+        -
+          asm_text: "vmul.i32 d16, d16, d17"
+        -
+          asm_text: "vmul.f32 d16, d16, d17"
+        -
+          asm_text: "vmul.i8 q8, q8, q9"
+        -
+          asm_text: "vmul.i16 q8, q8, q9"
+        -
+          asm_text: "vmul.i32 q8, q8, q9"
+        -
+          asm_text: "vmul.f32 q8, q8, q9"
+        -
+          asm_text: "vmul.p8 d16, d16, d17"
+        -
+          asm_text: "vmul.p8 q8, q8, q9"
+        -
+          asm_text: "vmul.i16 d18, d8, d0[3]"
+        -
+          asm_text: "vqdmulh.s16 d16, d16, d17"
+        -
+          asm_text: "vqdmulh.s32 d16, d16, d17"
+        -
+          asm_text: "vqdmulh.s16 q8, q8, q9"
+        -
+          asm_text: "vqdmulh.s32 q8, q8, q9"
+        -
+          asm_text: "vqdmulh.s16 d11, d2, d3[0]"
+        -
+          asm_text: "vqrdmulh.s16 d16, d16, d17"
+        -
+          asm_text: "vqrdmulh.s32 d16, d16, d17"
+        -
+          asm_text: "vqrdmulh.s16 q8, q8, q9"
+        -
+          asm_text: "vqrdmulh.s32 q8, q8, q9"
+        -
+          asm_text: "vmull.s8 q8, d16, d17"
+        -
+          asm_text: "vmull.s16 q8, d16, d17"
+        -
+          asm_text: "vmull.s32 q8, d16, d17"
+        -
+          asm_text: "vmull.u8 q8, d16, d17"
+        -
+          asm_text: "vmull.u16 q8, d16, d17"
+        -
+          asm_text: "vmull.u32 q8, d16, d17"
+        -
+          asm_text: "vmull.p8 q8, d16, d17"
+        -
+          asm_text: "vqdmull.s16 q8, d16, d17"
+        -
+          asm_text: "vqdmull.s32 q8, d16, d17"
+        -
+          asm_text: "vqdmull.s16 q1, d7, d1[1]"
diff --git a/tests/MC/ARM/neont2-neg-encoding.s.yaml b/tests/MC/ARM/neont2-neg-encoding.s.yaml
new file mode 100644
index 000000000..0e303dd5e
--- /dev/null
+++ b/tests/MC/ARM/neont2-neg-encoding.s.yaml
@@ -0,0 +1,36 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xf1, 0xff, 0xa0, 0x03, 0xf5, 0xff, 0xa0, 0x03, 0xf9, 0xff, 0xa0, 0x03, 0xf9, 0xff, 0xa0, 0x07, 0xf1, 0xff, 0xe0, 0x03, 0xf5, 0xff, 0xe0, 0x03, 0xf9, 0xff, 0xe0, 0x03, 0xf9, 0xff, 0xe0, 0x07, 0xf0, 0xff, 0xa0, 0x07, 0xf4, 0xff, 0xa0, 0x07, 0xf8, 0xff, 0xa0, 0x07, 0xf0, 0xff, 0xe0, 0x07, 0xf4, 0xff, 0xe0, 0x07, 0xf8, 0xff, 0xe0, 0x07 ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ]
+    expected:
+      insns:
+        -
+          asm_text: "vneg.s8 d16, d16"
+        -
+          asm_text: "vneg.s16 d16, d16"
+        -
+          asm_text: "vneg.s32 d16, d16"
+        -
+          asm_text: "vneg.f32 d16, d16"
+        -
+          asm_text: "vneg.s8 q8, q8"
+        -
+          asm_text: "vneg.s16 q8, q8"
+        -
+          asm_text: "vneg.s32 q8, q8"
+        -
+          asm_text: "vneg.f32 q8, q8"
+        -
+          asm_text: "vqneg.s8 d16, d16"
+        -
+          asm_text: "vqneg.s16 d16, d16"
+        -
+          asm_text: "vqneg.s32 d16, d16"
+        -
+          asm_text: "vqneg.s8 q8, q8"
+        -
+          asm_text: "vqneg.s16 q8, q8"
+        -
+          asm_text: "vqneg.s32 q8, q8"
diff --git a/tests/MC/ARM/neont2-pairwise-encoding.s.yaml b/tests/MC/ARM/neont2-pairwise-encoding.s.yaml
new file mode 100644
index 000000000..b7fb1c8e5
--- /dev/null
+++ b/tests/MC/ARM/neont2-pairwise-encoding.s.yaml
@@ -0,0 +1,92 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x05, 0xef, 0x1b, 0x1b, 0x12, 0xef, 0x1c, 0xdb, 0x21, 0xef, 0x1d, 0xeb, 0x40, 0xff, 0x8e, 0x3d, 0xb0, 0xff, 0x0a, 0x72, 0xb4, 0xff, 0x0b, 0x82, 0xb8, 0xff, 0x0c, 0x92, 0xb0, 0xff, 0x8d, 0x02, 0xb4, 0xff, 0x8e, 0x52, 0xb8, 0xff, 0x8f, 0x62, 0xb0, 0xff, 0x4e, 0x82, 0xb4, 0xff, 0x4c, 0xa2, 0xb8, 0xff, 0x4a, 0xc2, 0xb0, 0xff, 0xc8, 0xe2, 0xf4, 0xff, 0xc6, 0x02, 0xf8, 0xff, 0xc4, 0x22, 0xf0, 0xff, 0x04, 0x06, 0xf4, 0xff, 0x09, 0x46, 0xf8, 0xff, 0x01, 0x26, 0xb0, 0xff, 0xa9, 0xe6, 0xb4, 0xff, 0x86, 0xc6, 0xb8, 0xff, 0x87, 0xb6, 0xb0, 0xff, 0x64, 0x86, 0xb4, 0xff, 0x66, 0xa6, 0xb8, 0xff, 0x68, 0xc6, 0xb0, 0xff, 0xea, 0xe6, 0xf4, 0xff, 0xec, 0x06, 0xf8, 0xff, 0xee, 0x26, 0x4d, 0xef, 0x9a, 0x0a, 0x5c, 0xef, 0x9b, 0x1a, 0x6b, 0xef, 0x9c, 0x2a, 0x4a, 0xff, 0x9d, 0x3a, 0x59, 0xff, 0x9e, 0x4a, 0x68, 0xff, 0x9f, 0x5a, 0x67, 0xff, 0xa0, 0x6f, 0x04, 0xef, 0xa1, 0x3a, 0x15, 0xef, 0xa0, 0x4a, 0x26, 0xef, 0x8f, 0x5a, 0x07, 0xff, 0x8e, 0x6a, 0x18, 0xff, 0x8d, 0x7a, 0x29, 0xff, 0x8c, 0x8a, 0x0a, 0xff, 0x8b, 0x9f ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpadd.i8 d1, d5, d11"
+        -
+          asm_text: "vpadd.i16 d13, d2, d12"
+        -
+          asm_text: "vpadd.i32 d14, d1, d13"
+        -
+          asm_text: "vpadd.f32 d19, d16, d14"
+        -
+          asm_text: "vpaddl.s8 d7, d10"
+        -
+          asm_text: "vpaddl.s16 d8, d11"
+        -
+          asm_text: "vpaddl.s32 d9, d12"
+        -
+          asm_text: "vpaddl.u8 d0, d13"
+        -
+          asm_text: "vpaddl.u16 d5, d14"
+        -
+          asm_text: "vpaddl.u32 d6, d15"
+        -
+          asm_text: "vpaddl.s8 q4, q7"
+        -
+          asm_text: "vpaddl.s16 q5, q6"
+        -
+          asm_text: "vpaddl.s32 q6, q5"
+        -
+          asm_text: "vpaddl.u8 q7, q4"
+        -
+          asm_text: "vpaddl.u16 q8, q3"
+        -
+          asm_text: "vpaddl.u32 q9, q2"
+        -
+          asm_text: "vpadal.s8 d16, d4"
+        -
+          asm_text: "vpadal.s16 d20, d9"
+        -
+          asm_text: "vpadal.s32 d18, d1"
+        -
+          asm_text: "vpadal.u8 d14, d25"
+        -
+          asm_text: "vpadal.u16 d12, d6"
+        -
+          asm_text: "vpadal.u32 d11, d7"
+        -
+          asm_text: "vpadal.s8 q4, q10"
+        -
+          asm_text: "vpadal.s16 q5, q11"
+        -
+          asm_text: "vpadal.s32 q6, q12"
+        -
+          asm_text: "vpadal.u8 q7, q13"
+        -
+          asm_text: "vpadal.u16 q8, q14"
+        -
+          asm_text: "vpadal.u32 q9, q15"
+        -
+          asm_text: "vpmin.s8 d16, d29, d10"
+        -
+          asm_text: "vpmin.s16 d17, d28, d11"
+        -
+          asm_text: "vpmin.s32 d18, d27, d12"
+        -
+          asm_text: "vpmin.u8 d19, d26, d13"
+        -
+          asm_text: "vpmin.u16 d20, d25, d14"
+        -
+          asm_text: "vpmin.u32 d21, d24, d15"
+        -
+          asm_text: "vpmin.f32 d22, d23, d16"
+        -
+          asm_text: "vpmax.s8 d3, d20, d17"
+        -
+          asm_text: "vpmax.s16 d4, d21, d16"
+        -
+          asm_text: "vpmax.s32 d5, d22, d15"
+        -
+          asm_text: "vpmax.u8 d6, d23, d14"
+        -
+          asm_text: "vpmax.u16 d7, d24, d13"
+        -
+          asm_text: "vpmax.u32 d8, d25, d12"
+        -
+          asm_text: "vpmax.f32 d9, d26, d11"
diff --git a/tests/MC/ARM/neont2-reciprocal-encoding.s.yaml b/tests/MC/ARM/neont2-reciprocal-encoding.s.yaml
new file mode 100644
index 000000000..b44836b58
--- /dev/null
+++ b/tests/MC/ARM/neont2-reciprocal-encoding.s.yaml
@@ -0,0 +1,32 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xfb, 0xff, 0x20, 0x04, 0xfb, 0xff, 0x60, 0x04, 0xfb, 0xff, 0x20, 0x05, 0xfb, 0xff, 0x60, 0x05, 0x40, 0xef, 0xb1, 0x0f, 0x40, 0xef, 0xf2, 0x0f, 0xfb, 0xff, 0xa0, 0x04, 0xfb, 0xff, 0xe0, 0x04, 0xfb, 0xff, 0xa0, 0x05, 0xfb, 0xff, 0xe0, 0x05, 0x60, 0xef, 0xb1, 0x0f, 0x60, 0xef, 0xf2, 0x0f ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ]
+    expected:
+      insns:
+        -
+          asm_text: "vrecpe.u32 d16, d16"
+        -
+          asm_text: "vrecpe.u32 q8, q8"
+        -
+          asm_text: "vrecpe.f32 d16, d16"
+        -
+          asm_text: "vrecpe.f32 q8, q8"
+        -
+          asm_text: "vrecps.f32 d16, d16, d17"
+        -
+          asm_text: "vrecps.f32 q8, q8, q9"
+        -
+          asm_text: "vrsqrte.u32 d16, d16"
+        -
+          asm_text: "vrsqrte.u32 q8, q8"
+        -
+          asm_text: "vrsqrte.f32 d16, d16"
+        -
+          asm_text: "vrsqrte.f32 q8, q8"
+        -
+          asm_text: "vrsqrts.f32 d16, d16, d17"
+        -
+          asm_text: "vrsqrts.f32 q8, q8, q9"
diff --git a/tests/MC/ARM/neont2-reverse-encoding.s.yaml b/tests/MC/ARM/neont2-reverse-encoding.s.yaml
new file mode 100644
index 000000000..d02f9b107
--- /dev/null
+++ b/tests/MC/ARM/neont2-reverse-encoding.s.yaml
@@ -0,0 +1,32 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xf0, 0xff, 0x20, 0x00, 0xf4, 0xff, 0x20, 0x00, 0xf8, 0xff, 0x20, 0x00, 0xf0, 0xff, 0x60, 0x00, 0xf4, 0xff, 0x60, 0x00, 0xf8, 0xff, 0x60, 0x00, 0xf0, 0xff, 0xa0, 0x00, 0xf4, 0xff, 0xa0, 0x00, 0xf0, 0xff, 0xe0, 0x00, 0xf4, 0xff, 0xe0, 0x00, 0xf0, 0xff, 0x20, 0x01, 0xf0, 0xff, 0x60, 0x01 ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ]
+    expected:
+      insns:
+        -
+          asm_text: "vrev64.8 d16, d16"
+        -
+          asm_text: "vrev64.16 d16, d16"
+        -
+          asm_text: "vrev64.32 d16, d16"
+        -
+          asm_text: "vrev64.8 q8, q8"
+        -
+          asm_text: "vrev64.16 q8, q8"
+        -
+          asm_text: "vrev64.32 q8, q8"
+        -
+          asm_text: "vrev32.8 d16, d16"
+        -
+          asm_text: "vrev32.16 d16, d16"
+        -
+          asm_text: "vrev32.8 q8, q8"
+        -
+          asm_text: "vrev32.16 q8, q8"
+        -
+          asm_text: "vrev16.8 d16, d16"
+        -
+          asm_text: "vrev16.8 q8, q8"
diff --git a/tests/MC/ARM/neont2-satshift-encoding.s.yaml b/tests/MC/ARM/neont2-satshift-encoding.s.yaml
new file mode 100644
index 000000000..8fb2e124f
--- /dev/null
+++ b/tests/MC/ARM/neont2-satshift-encoding.s.yaml
@@ -0,0 +1,156 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x41, 0xef, 0xb0, 0x04, 0x51, 0xef, 0xb0, 0x04, 0x61, 0xef, 0xb0, 0x04, 0x71, 0xef, 0xb0, 0x04, 0x41, 0xff, 0xb0, 0x04, 0x51, 0xff, 0xb0, 0x04, 0x61, 0xff, 0xb0, 0x04, 0x71, 0xff, 0xb0, 0x04, 0x42, 0xef, 0xf0, 0x04, 0x52, 0xef, 0xf0, 0x04, 0x62, 0xef, 0xf0, 0x04, 0x72, 0xef, 0xf0, 0x04, 0x42, 0xff, 0xf0, 0x04, 0x52, 0xff, 0xf0, 0x04, 0x62, 0xff, 0xf0, 0x04, 0x72, 0xff, 0xf0, 0x04, 0xcf, 0xef, 0x30, 0x07, 0xdf, 0xef, 0x30, 0x07, 0xff, 0xef, 0x30, 0x07, 0xff, 0xef, 0xb0, 0x07, 0xcf, 0xff, 0x30, 0x07, 0xdf, 0xff, 0x30, 0x07, 0xff, 0xff, 0x30, 0x07, 0xff, 0xff, 0xb0, 0x07, 0xcf, 0xff, 0x30, 0x06, 0xdf, 0xff, 0x30, 0x06, 0xff, 0xff, 0x30, 0x06, 0xff, 0xff, 0xb0, 0x06, 0xcf, 0xef, 0x70, 0x07, 0xdf, 0xef, 0x70, 0x07, 0xff, 0xef, 0x70, 0x07, 0xff, 0xef, 0xf0, 0x07, 0xcf, 0xff, 0x70, 0x07, 0xdf, 0xff, 0x70, 0x07, 0xff, 0xff, 0x70, 0x07, 0xff, 0xff, 0xf0, 0x07, 0xcf, 0xff, 0x70, 0x06, 0xdf, 0xff, 0x70, 0x06, 0xff, 0xff, 0x70, 0x06, 0xff, 0xff, 0xf0, 0x06, 0x41, 0xef, 0xb0, 0x05, 0x51, 0xef, 0xb0, 0x05, 0x61, 0xef, 0xb0, 0x05, 0x71, 0xef, 0xb0, 0x05, 0x41, 0xff, 0xb0, 0x05, 0x51, 0xff, 0xb0, 0x05, 0x61, 0xff, 0xb0, 0x05, 0x71, 0xff, 0xb0, 0x05, 0x42, 0xef, 0xf0, 0x05, 0x52, 0xef, 0xf0, 0x05, 0x62, 0xef, 0xf0, 0x05, 0x72, 0xef, 0xf0, 0x05, 0x42, 0xff, 0xf0, 0x05, 0x52, 0xff, 0xf0, 0x05, 0x62, 0xff, 0xf0, 0x05, 0x72, 0xff, 0xf0, 0x05, 0xc8, 0xef, 0x30, 0x09, 0xd0, 0xef, 0x30, 0x09, 0xe0, 0xef, 0x30, 0x09, 0xc8, 0xff, 0x30, 0x09, 0xd0, 0xff, 0x30, 0x09, 0xe0, 0xff, 0x30, 0x09, 0xc8, 0xff, 0x30, 0x08, 0xd0, 0xff, 0x30, 0x08, 0xe0, 0xff, 0x30, 0x08, 0xc8, 0xef, 0x70, 0x09, 0xd0, 0xef, 0x70, 0x09, 0xe0, 0xef, 0x70, 0x09, 0xc8, 0xff, 0x70, 0x09, 0xd0, 0xff, 0x70, 0x09, 0xe0, 0xff, 0x70, 0x09, 0xc8, 0xff, 0x70, 0x08, 0xd0, 0xff, 0x70, 0x08, 0xe0, 0xff, 0x70, 0x08 ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ]
+    expected:
+      insns:
+        -
+          asm_text: "vqshl.s8 d16, d16, d17"
+        -
+          asm_text: "vqshl.s16 d16, d16, d17"
+        -
+          asm_text: "vqshl.s32 d16, d16, d17"
+        -
+          asm_text: "vqshl.s64 d16, d16, d17"
+        -
+          asm_text: "vqshl.u8 d16, d16, d17"
+        -
+          asm_text: "vqshl.u16 d16, d16, d17"
+        -
+          asm_text: "vqshl.u32 d16, d16, d17"
+        -
+          asm_text: "vqshl.u64 d16, d16, d17"
+        -
+          asm_text: "vqshl.s8 q8, q8, q9"
+        -
+          asm_text: "vqshl.s16 q8, q8, q9"
+        -
+          asm_text: "vqshl.s32 q8, q8, q9"
+        -
+          asm_text: "vqshl.s64 q8, q8, q9"
+        -
+          asm_text: "vqshl.u8 q8, q8, q9"
+        -
+          asm_text: "vqshl.u16 q8, q8, q9"
+        -
+          asm_text: "vqshl.u32 q8, q8, q9"
+        -
+          asm_text: "vqshl.u64 q8, q8, q9"
+        -
+          asm_text: "vqshl.s8 d16, d16, #7"
+        -
+          asm_text: "vqshl.s16 d16, d16, #0xf"
+        -
+          asm_text: "vqshl.s32 d16, d16, #0x1f"
+        -
+          asm_text: "vqshl.s64 d16, d16, #0x3f"
+        -
+          asm_text: "vqshl.u8 d16, d16, #7"
+        -
+          asm_text: "vqshl.u16 d16, d16, #0xf"
+        -
+          asm_text: "vqshl.u32 d16, d16, #0x1f"
+        -
+          asm_text: "vqshl.u64 d16, d16, #0x3f"
+        -
+          asm_text: "vqshlu.s8 d16, d16, #7"
+        -
+          asm_text: "vqshlu.s16 d16, d16, #0xf"
+        -
+          asm_text: "vqshlu.s32 d16, d16, #0x1f"
+        -
+          asm_text: "vqshlu.s64 d16, d16, #0x3f"
+        -
+          asm_text: "vqshl.s8 q8, q8, #7"
+        -
+          asm_text: "vqshl.s16 q8, q8, #0xf"
+        -
+          asm_text: "vqshl.s32 q8, q8, #0x1f"
+        -
+          asm_text: "vqshl.s64 q8, q8, #0x3f"
+        -
+          asm_text: "vqshl.u8 q8, q8, #7"
+        -
+          asm_text: "vqshl.u16 q8, q8, #0xf"
+        -
+          asm_text: "vqshl.u32 q8, q8, #0x1f"
+        -
+          asm_text: "vqshl.u64 q8, q8, #0x3f"
+        -
+          asm_text: "vqshlu.s8 q8, q8, #7"
+        -
+          asm_text: "vqshlu.s16 q8, q8, #0xf"
+        -
+          asm_text: "vqshlu.s32 q8, q8, #0x1f"
+        -
+          asm_text: "vqshlu.s64 q8, q8, #0x3f"
+        -
+          asm_text: "vqrshl.s8 d16, d16, d17"
+        -
+          asm_text: "vqrshl.s16 d16, d16, d17"
+        -
+          asm_text: "vqrshl.s32 d16, d16, d17"
+        -
+          asm_text: "vqrshl.s64 d16, d16, d17"
+        -
+          asm_text: "vqrshl.u8 d16, d16, d17"
+        -
+          asm_text: "vqrshl.u16 d16, d16, d17"
+        -
+          asm_text: "vqrshl.u32 d16, d16, d17"
+        -
+          asm_text: "vqrshl.u64 d16, d16, d17"
+        -
+          asm_text: "vqrshl.s8 q8, q8, q9"
+        -
+          asm_text: "vqrshl.s16 q8, q8, q9"
+        -
+          asm_text: "vqrshl.s32 q8, q8, q9"
+        -
+          asm_text: "vqrshl.s64 q8, q8, q9"
+        -
+          asm_text: "vqrshl.u8 q8, q8, q9"
+        -
+          asm_text: "vqrshl.u16 q8, q8, q9"
+        -
+          asm_text: "vqrshl.u32 q8, q8, q9"
+        -
+          asm_text: "vqrshl.u64 q8, q8, q9"
+        -
+          asm_text: "vqshrn.s16 d16, q8, #8"
+        -
+          asm_text: "vqshrn.s32 d16, q8, #0x10"
+        -
+          asm_text: "vqshrn.s64 d16, q8, #0x20"
+        -
+          asm_text: "vqshrn.u16 d16, q8, #8"
+        -
+          asm_text: "vqshrn.u32 d16, q8, #0x10"
+        -
+          asm_text: "vqshrn.u64 d16, q8, #0x20"
+        -
+          asm_text: "vqshrun.s16 d16, q8, #8"
+        -
+          asm_text: "vqshrun.s32 d16, q8, #0x10"
+        -
+          asm_text: "vqshrun.s64 d16, q8, #0x20"
+        -
+          asm_text: "vqrshrn.s16 d16, q8, #8"
+        -
+          asm_text: "vqrshrn.s32 d16, q8, #0x10"
+        -
+          asm_text: "vqrshrn.s64 d16, q8, #0x20"
+        -
+          asm_text: "vqrshrn.u16 d16, q8, #8"
+        -
+          asm_text: "vqrshrn.u32 d16, q8, #0x10"
+        -
+          asm_text: "vqrshrn.u64 d16, q8, #0x20"
+        -
+          asm_text: "vqrshrun.s16 d16, q8, #8"
+        -
+          asm_text: "vqrshrun.s32 d16, q8, #0x10"
+        -
+          asm_text: "vqrshrun.s64 d16, q8, #0x20"
diff --git a/tests/MC/ARM/neont2-shift-encoding.s.yaml b/tests/MC/ARM/neont2-shift-encoding.s.yaml
new file mode 100644
index 000000000..e3643a401
--- /dev/null
+++ b/tests/MC/ARM/neont2-shift-encoding.s.yaml
@@ -0,0 +1,166 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x40, 0xff, 0xa1, 0x04, 0x50, 0xff, 0xa1, 0x04, 0x60, 0xff, 0xa1, 0x04, 0x70, 0xff, 0xa1, 0x04, 0xcf, 0xef, 0x30, 0x05, 0xdf, 0xef, 0x30, 0x05, 0xff, 0xef, 0x30, 0x05, 0xff, 0xef, 0xb0, 0x05, 0x40, 0xff, 0xe2, 0x04, 0x50, 0xff, 0xe2, 0x04, 0x60, 0xff, 0xe2, 0x04, 0x70, 0xff, 0xe2, 0x04, 0xcf, 0xef, 0x70, 0x05, 0xdf, 0xef, 0x70, 0x05, 0xff, 0xef, 0x70, 0x05, 0xff, 0xef, 0xf0, 0x05, 0xc8, 0xff, 0x30, 0x00, 0xd0, 0xff, 0x30, 0x00, 0xe0, 0xff, 0x30, 0x00, 0xc0, 0xff, 0xb0, 0x00, 0xc8, 0xff, 0x70, 0x00, 0xd0, 0xff, 0x70, 0x00, 0xe0, 0xff, 0x70, 0x00, 0xc0, 0xff, 0xf0, 0x00, 0xc8, 0xef, 0x30, 0x00, 0xd0, 0xef, 0x30, 0x00, 0xe0, 0xef, 0x30, 0x00, 0xc0, 0xef, 0xb0, 0x00, 0xc8, 0xef, 0x70, 0x00, 0xd0, 0xef, 0x70, 0x00, 0xe0, 0xef, 0x70, 0x00, 0xc0, 0xef, 0xf0, 0x00, 0xcf, 0xef, 0x30, 0x0a, 0xdf, 0xef, 0x30, 0x0a, 0xff, 0xef, 0x30, 0x0a, 0xcf, 0xff, 0x30, 0x0a, 0xdf, 0xff, 0x30, 0x0a, 0xff, 0xff, 0x30, 0x0a, 0xf2, 0xff, 0x20, 0x03, 0xf6, 0xff, 0x20, 0x03, 0xfa, 0xff, 0x20, 0x03, 0xc8, 0xef, 0x30, 0x08, 0xd0, 0xef, 0x30, 0x08, 0xe0, 0xef, 0x30, 0x08, 0x40, 0xef, 0xa1, 0x05, 0x50, 0xef, 0xa1, 0x05, 0x60, 0xef, 0xa1, 0x05, 0x70, 0xef, 0xa1, 0x05, 0x40, 0xff, 0xa1, 0x05, 0x50, 0xff, 0xa1, 0x05, 0x60, 0xff, 0xa1, 0x05, 0x70, 0xff, 0xa1, 0x05, 0x40, 0xef, 0xe2, 0x05, 0x50, 0xef, 0xe2, 0x05, 0x60, 0xef, 0xe2, 0x05, 0x70, 0xef, 0xe2, 0x05, 0x40, 0xff, 0xe2, 0x05, 0x50, 0xff, 0xe2, 0x05, 0x60, 0xff, 0xe2, 0x05, 0x70, 0xff, 0xe2, 0x05, 0xc8, 0xef, 0x30, 0x02, 0xd0, 0xef, 0x30, 0x02, 0xe0, 0xef, 0x30, 0x02, 0xc0, 0xef, 0xb0, 0x02, 0xc8, 0xff, 0x30, 0x02, 0xd0, 0xff, 0x30, 0x02, 0xe0, 0xff, 0x30, 0x02, 0xc0, 0xff, 0xb0, 0x02, 0xc8, 0xef, 0x70, 0x02, 0xd0, 0xef, 0x70, 0x02, 0xe0, 0xef, 0x70, 0x02, 0xc0, 0xef, 0xf0, 0x02, 0xc8, 0xff, 0x70, 0x02, 0xd0, 0xff, 0x70, 0x02, 0xe0, 0xff, 0x70, 0x02, 0xc0, 0xff, 0xf0, 0x02, 0xc8, 0xef, 0x70, 0x08, 0xd0, 0xef, 0x70, 0x08, 0xe0, 0xef, 0x70, 0x08 ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ]
+    expected:
+      insns:
+        -
+          asm_text: "vshl.u8 d16, d17, d16"
+        -
+          asm_text: "vshl.u16 d16, d17, d16"
+        -
+          asm_text: "vshl.u32 d16, d17, d16"
+        -
+          asm_text: "vshl.u64 d16, d17, d16"
+        -
+          asm_text: "vshl.i8 d16, d16, #7"
+        -
+          asm_text: "vshl.i16 d16, d16, #0xf"
+        -
+          asm_text: "vshl.i32 d16, d16, #0x1f"
+        -
+          asm_text: "vshl.i64 d16, d16, #0x3f"
+        -
+          asm_text: "vshl.u8 q8, q9, q8"
+        -
+          asm_text: "vshl.u16 q8, q9, q8"
+        -
+          asm_text: "vshl.u32 q8, q9, q8"
+        -
+          asm_text: "vshl.u64 q8, q9, q8"
+        -
+          asm_text: "vshl.i8 q8, q8, #7"
+        -
+          asm_text: "vshl.i16 q8, q8, #0xf"
+        -
+          asm_text: "vshl.i32 q8, q8, #0x1f"
+        -
+          asm_text: "vshl.i64 q8, q8, #0x3f"
+        -
+          asm_text: "vshr.u8 d16, d16, #8"
+        -
+          asm_text: "vshr.u16 d16, d16, #0x10"
+        -
+          asm_text: "vshr.u32 d16, d16, #0x20"
+        -
+          asm_text: "vshr.u64 d16, d16, #0x40"
+        -
+          asm_text: "vshr.u8 q8, q8, #8"
+        -
+          asm_text: "vshr.u16 q8, q8, #0x10"
+        -
+          asm_text: "vshr.u32 q8, q8, #0x20"
+        -
+          asm_text: "vshr.u64 q8, q8, #0x40"
+        -
+          asm_text: "vshr.s8 d16, d16, #8"
+        -
+          asm_text: "vshr.s16 d16, d16, #0x10"
+        -
+          asm_text: "vshr.s32 d16, d16, #0x20"
+        -
+          asm_text: "vshr.s64 d16, d16, #0x40"
+        -
+          asm_text: "vshr.s8 q8, q8, #8"
+        -
+          asm_text: "vshr.s16 q8, q8, #0x10"
+        -
+          asm_text: "vshr.s32 q8, q8, #0x20"
+        -
+          asm_text: "vshr.s64 q8, q8, #0x40"
+        -
+          asm_text: "vshll.s8 q8, d16, #7"
+        -
+          asm_text: "vshll.s16 q8, d16, #0xf"
+        -
+          asm_text: "vshll.s32 q8, d16, #0x1f"
+        -
+          asm_text: "vshll.u8 q8, d16, #7"
+        -
+          asm_text: "vshll.u16 q8, d16, #0xf"
+        -
+          asm_text: "vshll.u32 q8, d16, #0x1f"
+        -
+          asm_text: "vshll.i8 q8, d16, #8"
+        -
+          asm_text: "vshll.i16 q8, d16, #0x10"
+        -
+          asm_text: "vshll.i32 q8, d16, #0x20"
+        -
+          asm_text: "vshrn.i16 d16, q8, #8"
+        -
+          asm_text: "vshrn.i32 d16, q8, #0x10"
+        -
+          asm_text: "vshrn.i64 d16, q8, #0x20"
+        -
+          asm_text: "vrshl.s8 d16, d17, d16"
+        -
+          asm_text: "vrshl.s16 d16, d17, d16"
+        -
+          asm_text: "vrshl.s32 d16, d17, d16"
+        -
+          asm_text: "vrshl.s64 d16, d17, d16"
+        -
+          asm_text: "vrshl.u8 d16, d17, d16"
+        -
+          asm_text: "vrshl.u16 d16, d17, d16"
+        -
+          asm_text: "vrshl.u32 d16, d17, d16"
+        -
+          asm_text: "vrshl.u64 d16, d17, d16"
+        -
+          asm_text: "vrshl.s8 q8, q9, q8"
+        -
+          asm_text: "vrshl.s16 q8, q9, q8"
+        -
+          asm_text: "vrshl.s32 q8, q9, q8"
+        -
+          asm_text: "vrshl.s64 q8, q9, q8"
+        -
+          asm_text: "vrshl.u8 q8, q9, q8"
+        -
+          asm_text: "vrshl.u16 q8, q9, q8"
+        -
+          asm_text: "vrshl.u32 q8, q9, q8"
+        -
+          asm_text: "vrshl.u64 q8, q9, q8"
+        -
+          asm_text: "vrshr.s8 d16, d16, #8"
+        -
+          asm_text: "vrshr.s16 d16, d16, #0x10"
+        -
+          asm_text: "vrshr.s32 d16, d16, #0x20"
+        -
+          asm_text: "vrshr.s64 d16, d16, #0x40"
+        -
+          asm_text: "vrshr.u8 d16, d16, #8"
+        -
+          asm_text: "vrshr.u16 d16, d16, #0x10"
+        -
+          asm_text: "vrshr.u32 d16, d16, #0x20"
+        -
+          asm_text: "vrshr.u64 d16, d16, #0x40"
+        -
+          asm_text: "vrshr.s8 q8, q8, #8"
+        -
+          asm_text: "vrshr.s16 q8, q8, #0x10"
+        -
+          asm_text: "vrshr.s32 q8, q8, #0x20"
+        -
+          asm_text: "vrshr.s64 q8, q8, #0x40"
+        -
+          asm_text: "vrshr.u8 q8, q8, #8"
+        -
+          asm_text: "vrshr.u16 q8, q8, #0x10"
+        -
+          asm_text: "vrshr.u32 q8, q8, #0x20"
+        -
+          asm_text: "vrshr.u64 q8, q8, #0x40"
+        -
+          asm_text: "vrshrn.i16 d16, q8, #8"
+        -
+          asm_text: "vrshrn.i32 d16, q8, #0x10"
+        -
+          asm_text: "vrshrn.i64 d16, q8, #0x20"
diff --git a/tests/MC/ARM/neont2-shiftaccum-encoding.s.yaml b/tests/MC/ARM/neont2-shiftaccum-encoding.s.yaml
new file mode 100644
index 000000000..79c71a7c3
--- /dev/null
+++ b/tests/MC/ARM/neont2-shiftaccum-encoding.s.yaml
@@ -0,0 +1,200 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xc8, 0xef, 0x30, 0x11, 0x90, 0xef, 0x1e, 0xf1, 0xa0, 0xef, 0x1c, 0xd1, 0x80, 0xef, 0x9a, 0xb1, 0x88, 0xef, 0x54, 0xe1, 0x90, 0xef, 0x5c, 0x61, 0xe0, 0xef, 0x5a, 0x21, 0xc0, 0xef, 0xd8, 0x01, 0xc8, 0xff, 0x30, 0x11, 0x95, 0xff, 0x1e, 0xb1, 0xaa, 0xff, 0x1f, 0xc1, 0x8a, 0xff, 0xb0, 0xd1, 0x88, 0xff, 0x5e, 0x21, 0x9a, 0xff, 0x5e, 0x41, 0xab, 0xff, 0x5c, 0x61, 0xa7, 0xff, 0xda, 0x81, 0xc8, 0xef, 0x30, 0x01, 0x90, 0xef, 0x1e, 0xe1, 0xa0, 0xef, 0x1c, 0xc1, 0x80, 0xef, 0x9a, 0xa1, 0x88, 0xef, 0x54, 0x41, 0x90, 0xef, 0x5c, 0xc1, 0xa0, 0xef, 0x5a, 0xa1, 0x80, 0xef, 0xd8, 0x81, 0xc8, 0xff, 0x30, 0x01, 0x95, 0xff, 0x1e, 0xe1, 0xaa, 0xff, 0x1f, 0xf1, 0xca, 0xff, 0xb0, 0x01, 0x88, 0xff, 0x5e, 0xe1, 0x9a, 0xff, 0x5e, 0xe1, 0xab, 0xff, 0x5c, 0xc1, 0xa7, 0xff, 0xda, 0xa1, 0x88, 0xef, 0x3a, 0x53, 0x90, 0xef, 0x39, 0x63, 0xa0, 0xef, 0x38, 0x73, 0x80, 0xef, 0xb7, 0xe3, 0x88, 0xff, 0x36, 0xf3, 0xd0, 0xff, 0x35, 0x03, 0xe0, 0xff, 0x34, 0x13, 0xc0, 0xff, 0xb3, 0x23, 0x88, 0xef, 0x54, 0x23, 0x90, 0xef, 0x56, 0x43, 0xa0, 0xef, 0x58, 0x63, 0x80, 0xef, 0xda, 0x83, 0x88, 0xff, 0x5c, 0xa3, 0x90, 0xff, 0x5e, 0xc3, 0xa0, 0xff, 0x70, 0xe3, 0xc0, 0xff, 0xf2, 0x03, 0xc8, 0xef, 0x3a, 0xa3, 0xd0, 0xef, 0x39, 0x93, 0xe0, 0xef, 0x38, 0x83, 0xc0, 0xef, 0xb7, 0x73, 0xc8, 0xff, 0x36, 0x63, 0xd0, 0xff, 0x35, 0x53, 0xe0, 0xff, 0x34, 0x43, 0xc0, 0xff, 0xb3, 0x33, 0x88, 0xef, 0x54, 0x43, 0x90, 0xef, 0x56, 0x63, 0xa0, 0xef, 0x58, 0x83, 0x80, 0xef, 0xda, 0xa3, 0x88, 0xff, 0x5c, 0xc3, 0x90, 0xff, 0x5e, 0xe3, 0xe0, 0xff, 0x70, 0x03, 0xc0, 0xff, 0xf2, 0x23, 0x8f, 0xff, 0x1c, 0xb5, 0x9f, 0xff, 0x1d, 0xc5, 0xbf, 0xff, 0x1e, 0xd5, 0xbf, 0xff, 0x9f, 0xe5, 0x8f, 0xff, 0x70, 0x25, 0x9f, 0xff, 0x5e, 0x45, 0xbf, 0xff, 0x58, 0x65, 0xbf, 0xff, 0xda, 0x85, 0xc8, 0xff, 0x1b, 0xc4, 0xd0, 0xff, 0x1c, 0xa4, 0xe0, 0xff, 0x1d, 0x84, 0xc0, 0xff, 0x9e, 0x54, 0x88, 0xff, 0x70, 0x24, 0x90, 0xff, 0x54, 0xa4, 0xa0, 0xff, 0x58, 0xe4, 0xc0, 0xff, 0xdc, 0x24, 0x8f, 0xff, 0x1c, 0xc5, 0x9f, 0xff, 0x1d, 0xd5, 0xbf, 0xff, 0x1e, 0xe5, 0xbf, 0xff, 0x9f, 0xf5, 0xcf, 0xff, 0x70, 0x05, 0x9f, 0xff, 0x5e, 0xe5, 0xbf, 0xff, 0x58, 0x85, 0xbf, 0xff, 0xda, 0xa5, 0x88, 0xff, 0x1b, 0xb4, 0x90, 0xff, 0x1c, 0xc4, 0xa0, 0xff, 0x1d, 0xd4, 0x80, 0xff, 0x9e, 0xe4, 0xc8, 0xff, 0x70, 0x04, 0x90, 0xff, 0x54, 0x44, 0xa0, 0xff, 0x58, 0x84, 0x80, 0xff, 0xdc, 0xc4 ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ]
+    expected:
+      insns:
+        -
+          asm_text: "vsra.s8 d17, d16, #8"
+        -
+          asm_text: "vsra.s16 d15, d14, #0x10"
+        -
+          asm_text: "vsra.s32 d13, d12, #0x20"
+        -
+          asm_text: "vsra.s64 d11, d10, #0x40"
+        -
+          asm_text: "vsra.s8 q7, q2, #8"
+        -
+          asm_text: "vsra.s16 q3, q6, #0x10"
+        -
+          asm_text: "vsra.s32 q9, q5, #0x20"
+        -
+          asm_text: "vsra.s64 q8, q4, #0x40"
+        -
+          asm_text: "vsra.u8 d17, d16, #8"
+        -
+          asm_text: "vsra.u16 d11, d14, #0xb"
+        -
+          asm_text: "vsra.u32 d12, d15, #0x16"
+        -
+          asm_text: "vsra.u64 d13, d16, #0x36"
+        -
+          asm_text: "vsra.u8 q1, q7, #8"
+        -
+          asm_text: "vsra.u16 q2, q7, #6"
+        -
+          asm_text: "vsra.u32 q3, q6, #0x15"
+        -
+          asm_text: "vsra.u64 q4, q5, #0x19"
+        -
+          asm_text: "vsra.s8 d16, d16, #8"
+        -
+          asm_text: "vsra.s16 d14, d14, #0x10"
+        -
+          asm_text: "vsra.s32 d12, d12, #0x20"
+        -
+          asm_text: "vsra.s64 d10, d10, #0x40"
+        -
+          asm_text: "vsra.s8 q2, q2, #8"
+        -
+          asm_text: "vsra.s16 q6, q6, #0x10"
+        -
+          asm_text: "vsra.s32 q5, q5, #0x20"
+        -
+          asm_text: "vsra.s64 q4, q4, #0x40"
+        -
+          asm_text: "vsra.u8 d16, d16, #8"
+        -
+          asm_text: "vsra.u16 d14, d14, #0xb"
+        -
+          asm_text: "vsra.u32 d15, d15, #0x16"
+        -
+          asm_text: "vsra.u64 d16, d16, #0x36"
+        -
+          asm_text: "vsra.u8 q7, q7, #8"
+        -
+          asm_text: "vsra.u16 q7, q7, #6"
+        -
+          asm_text: "vsra.u32 q6, q6, #0x15"
+        -
+          asm_text: "vsra.u64 q5, q5, #0x19"
+        -
+          asm_text: "vrsra.s8 d5, d26, #8"
+        -
+          asm_text: "vrsra.s16 d6, d25, #0x10"
+        -
+          asm_text: "vrsra.s32 d7, d24, #0x20"
+        -
+          asm_text: "vrsra.s64 d14, d23, #0x40"
+        -
+          asm_text: "vrsra.u8 d15, d22, #8"
+        -
+          asm_text: "vrsra.u16 d16, d21, #0x10"
+        -
+          asm_text: "vrsra.u32 d17, d20, #0x20"
+        -
+          asm_text: "vrsra.u64 d18, d19, #0x40"
+        -
+          asm_text: "vrsra.s8 q1, q2, #8"
+        -
+          asm_text: "vrsra.s16 q2, q3, #0x10"
+        -
+          asm_text: "vrsra.s32 q3, q4, #0x20"
+        -
+          asm_text: "vrsra.s64 q4, q5, #0x40"
+        -
+          asm_text: "vrsra.u8 q5, q6, #8"
+        -
+          asm_text: "vrsra.u16 q6, q7, #0x10"
+        -
+          asm_text: "vrsra.u32 q7, q8, #0x20"
+        -
+          asm_text: "vrsra.u64 q8, q9, #0x40"
+        -
+          asm_text: "vrsra.s8 d26, d26, #8"
+        -
+          asm_text: "vrsra.s16 d25, d25, #0x10"
+        -
+          asm_text: "vrsra.s32 d24, d24, #0x20"
+        -
+          asm_text: "vrsra.s64 d23, d23, #0x40"
+        -
+          asm_text: "vrsra.u8 d22, d22, #8"
+        -
+          asm_text: "vrsra.u16 d21, d21, #0x10"
+        -
+          asm_text: "vrsra.u32 d20, d20, #0x20"
+        -
+          asm_text: "vrsra.u64 d19, d19, #0x40"
+        -
+          asm_text: "vrsra.s8 q2, q2, #8"
+        -
+          asm_text: "vrsra.s16 q3, q3, #0x10"
+        -
+          asm_text: "vrsra.s32 q4, q4, #0x20"
+        -
+          asm_text: "vrsra.s64 q5, q5, #0x40"
+        -
+          asm_text: "vrsra.u8 q6, q6, #8"
+        -
+          asm_text: "vrsra.u16 q7, q7, #0x10"
+        -
+          asm_text: "vrsra.u32 q8, q8, #0x20"
+        -
+          asm_text: "vrsra.u64 q9, q9, #0x40"
+        -
+          asm_text: "vsli.8 d11, d12, #7"
+        -
+          asm_text: "vsli.16 d12, d13, #0xf"
+        -
+          asm_text: "vsli.32 d13, d14, #0x1f"
+        -
+          asm_text: "vsli.64 d14, d15, #0x3f"
+        -
+          asm_text: "vsli.8 q1, q8, #7"
+        -
+          asm_text: "vsli.16 q2, q7, #0xf"
+        -
+          asm_text: "vsli.32 q3, q4, #0x1f"
+        -
+          asm_text: "vsli.64 q4, q5, #0x3f"
+        -
+          asm_text: "vsri.8 d28, d11, #8"
+        -
+          asm_text: "vsri.16 d26, d12, #0x10"
+        -
+          asm_text: "vsri.32 d24, d13, #0x20"
+        -
+          asm_text: "vsri.64 d21, d14, #0x40"
+        -
+          asm_text: "vsri.8 q1, q8, #8"
+        -
+          asm_text: "vsri.16 q5, q2, #0x10"
+        -
+          asm_text: "vsri.32 q7, q4, #0x20"
+        -
+          asm_text: "vsri.64 q9, q6, #0x40"
+        -
+          asm_text: "vsli.8 d12, d12, #7"
+        -
+          asm_text: "vsli.16 d13, d13, #0xf"
+        -
+          asm_text: "vsli.32 d14, d14, #0x1f"
+        -
+          asm_text: "vsli.64 d15, d15, #0x3f"
+        -
+          asm_text: "vsli.8 q8, q8, #7"
+        -
+          asm_text: "vsli.16 q7, q7, #0xf"
+        -
+          asm_text: "vsli.32 q4, q4, #0x1f"
+        -
+          asm_text: "vsli.64 q5, q5, #0x3f"
+        -
+          asm_text: "vsri.8 d11, d11, #8"
+        -
+          asm_text: "vsri.16 d12, d12, #0x10"
+        -
+          asm_text: "vsri.32 d13, d13, #0x20"
+        -
+          asm_text: "vsri.64 d14, d14, #0x40"
+        -
+          asm_text: "vsri.8 q8, q8, #8"
+        -
+          asm_text: "vsri.16 q2, q2, #0x10"
+        -
+          asm_text: "vsri.32 q4, q4, #0x20"
+        -
+          asm_text: "vsri.64 q6, q6, #0x40"
diff --git a/tests/MC/ARM/neont2-shuffle-encoding.s.yaml b/tests/MC/ARM/neont2-shuffle-encoding.s.yaml
new file mode 100644
index 000000000..f4c00ebd3
--- /dev/null
+++ b/tests/MC/ARM/neont2-shuffle-encoding.s.yaml
@@ -0,0 +1,52 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xf1, 0xef, 0xa0, 0x03, 0xf1, 0xef, 0xa0, 0x05, 0xf2, 0xef, 0xe0, 0x03, 0xf2, 0xef, 0xe0, 0x07, 0xf1, 0xef, 0xa0, 0x06, 0xf2, 0xef, 0xe0, 0x0c, 0xf2, 0xff, 0xa0, 0x10, 0xf6, 0xff, 0xa0, 0x10, 0xfa, 0xff, 0xa0, 0x10, 0xf2, 0xff, 0xe0, 0x20, 0xf6, 0xff, 0xe0, 0x20, 0xfa, 0xff, 0xe0, 0x20, 0xf2, 0xff, 0x20, 0x11, 0xf6, 0xff, 0x20, 0x11, 0xf2, 0xff, 0x60, 0x21, 0xf6, 0xff, 0x60, 0x21, 0xfa, 0xff, 0x60, 0x21, 0xf2, 0xff, 0xa0, 0x11, 0xf6, 0xff, 0xa0, 0x11, 0xf2, 0xff, 0xe0, 0x21, 0xf6, 0xff, 0xe0, 0x21, 0xfa, 0xff, 0xe0, 0x21 ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ]
+    expected:
+      insns:
+        -
+          asm_text: "vext.8 d16, d17, d16, #3"
+        -
+          asm_text: "vext.8 d16, d17, d16, #5"
+        -
+          asm_text: "vext.8 q8, q9, q8, #3"
+        -
+          asm_text: "vext.8 q8, q9, q8, #7"
+        -
+          asm_text: "vext.16 d16, d17, d16, #3"
+        -
+          asm_text: "vext.32 q8, q9, q8, #3"
+        -
+          asm_text: "vtrn.8 d17, d16"
+        -
+          asm_text: "vtrn.16 d17, d16"
+        -
+          asm_text: "vtrn.32 d17, d16"
+        -
+          asm_text: "vtrn.8 q9, q8"
+        -
+          asm_text: "vtrn.16 q9, q8"
+        -
+          asm_text: "vtrn.32 q9, q8"
+        -
+          asm_text: "vuzp.8 d17, d16"
+        -
+          asm_text: "vuzp.16 d17, d16"
+        -
+          asm_text: "vuzp.8 q9, q8"
+        -
+          asm_text: "vuzp.16 q9, q8"
+        -
+          asm_text: "vuzp.32 q9, q8"
+        -
+          asm_text: "vzip.8 d17, d16"
+        -
+          asm_text: "vzip.16 d17, d16"
+        -
+          asm_text: "vzip.8 q9, q8"
+        -
+          asm_text: "vzip.16 q9, q8"
+        -
+          asm_text: "vzip.32 q9, q8"
diff --git a/tests/MC/ARM/neont2-sub-encoding.s.yaml b/tests/MC/ARM/neont2-sub-encoding.s.yaml
new file mode 100644
index 000000000..f4c00ebd3
--- /dev/null
+++ b/tests/MC/ARM/neont2-sub-encoding.s.yaml
@@ -0,0 +1,52 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xf1, 0xef, 0xa0, 0x03, 0xf1, 0xef, 0xa0, 0x05, 0xf2, 0xef, 0xe0, 0x03, 0xf2, 0xef, 0xe0, 0x07, 0xf1, 0xef, 0xa0, 0x06, 0xf2, 0xef, 0xe0, 0x0c, 0xf2, 0xff, 0xa0, 0x10, 0xf6, 0xff, 0xa0, 0x10, 0xfa, 0xff, 0xa0, 0x10, 0xf2, 0xff, 0xe0, 0x20, 0xf6, 0xff, 0xe0, 0x20, 0xfa, 0xff, 0xe0, 0x20, 0xf2, 0xff, 0x20, 0x11, 0xf6, 0xff, 0x20, 0x11, 0xf2, 0xff, 0x60, 0x21, 0xf6, 0xff, 0x60, 0x21, 0xfa, 0xff, 0x60, 0x21, 0xf2, 0xff, 0xa0, 0x11, 0xf6, 0xff, 0xa0, 0x11, 0xf2, 0xff, 0xe0, 0x21, 0xf6, 0xff, 0xe0, 0x21, 0xfa, 0xff, 0xe0, 0x21 ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ]
+    expected:
+      insns:
+        -
+          asm_text: "vext.8 d16, d17, d16, #3"
+        -
+          asm_text: "vext.8 d16, d17, d16, #5"
+        -
+          asm_text: "vext.8 q8, q9, q8, #3"
+        -
+          asm_text: "vext.8 q8, q9, q8, #7"
+        -
+          asm_text: "vext.16 d16, d17, d16, #3"
+        -
+          asm_text: "vext.32 q8, q9, q8, #3"
+        -
+          asm_text: "vtrn.8 d17, d16"
+        -
+          asm_text: "vtrn.16 d17, d16"
+        -
+          asm_text: "vtrn.32 d17, d16"
+        -
+          asm_text: "vtrn.8 q9, q8"
+        -
+          asm_text: "vtrn.16 q9, q8"
+        -
+          asm_text: "vtrn.32 q9, q8"
+        -
+          asm_text: "vuzp.8 d17, d16"
+        -
+          asm_text: "vuzp.16 d17, d16"
+        -
+          asm_text: "vuzp.8 q9, q8"
+        -
+          asm_text: "vuzp.16 q9, q8"
+        -
+          asm_text: "vuzp.32 q9, q8"
+        -
+          asm_text: "vzip.8 d17, d16"
+        -
+          asm_text: "vzip.16 d17, d16"
+        -
+          asm_text: "vzip.8 q9, q8"
+        -
+          asm_text: "vzip.16 q9, q8"
+        -
+          asm_text: "vzip.32 q9, q8"
diff --git a/tests/MC/ARM/neont2-table-encoding.s.yaml b/tests/MC/ARM/neont2-table-encoding.s.yaml
new file mode 100644
index 000000000..11fbd4897
--- /dev/null
+++ b/tests/MC/ARM/neont2-table-encoding.s.yaml
@@ -0,0 +1,24 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xf1, 0xff, 0xa0, 0x08, 0xf0, 0xff, 0xa2, 0x09, 0xf0, 0xff, 0xa4, 0x0a, 0xf0, 0xff, 0xa4, 0x0b, 0xf0, 0xff, 0xe1, 0x28, 0xf0, 0xff, 0xe2, 0x39, 0xf0, 0xff, 0xe5, 0x4a, 0xf0, 0xff, 0xe5, 0x4b ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ]
+    expected:
+      insns:
+        -
+          asm_text: "vtbl.8 d16, {d17}, d16"
+        -
+          asm_text: "vtbl.8 d16, {d16, d17}, d18"
+        -
+          asm_text: "vtbl.8 d16, {d16, d17, d18}, d20"
+        -
+          asm_text: "vtbl.8 d16, {d16, d17, d18, d19}, d20"
+        -
+          asm_text: "vtbx.8 d18, {d16}, d17"
+        -
+          asm_text: "vtbx.8 d19, {d16, d17}, d18"
+        -
+          asm_text: "vtbx.8 d20, {d16, d17, d18}, d21"
+        -
+          asm_text: "vtbx.8 d20, {d16, d17, d18, d19}, d21"
diff --git a/tests/MC/ARM/neont2-vld-encoding.s.yaml b/tests/MC/ARM/neont2-vld-encoding.s.yaml
new file mode 100644
index 000000000..78ded52c0
--- /dev/null
+++ b/tests/MC/ARM/neont2-vld-encoding.s.yaml
@@ -0,0 +1,108 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x60, 0xf9, 0x1f, 0x07, 0x60, 0xf9, 0x4f, 0x07, 0x60, 0xf9, 0x8f, 0x07, 0x60, 0xf9, 0xcf, 0x07, 0x60, 0xf9, 0x1f, 0x0a, 0x60, 0xf9, 0x6f, 0x0a, 0x60, 0xf9, 0x8f, 0x0a, 0x60, 0xf9, 0xcf, 0x0a, 0x60, 0xf9, 0x1f, 0x08, 0x60, 0xf9, 0x6f, 0x08, 0x60, 0xf9, 0x8f, 0x08, 0x60, 0xf9, 0x1f, 0x03, 0x60, 0xf9, 0x6f, 0x03, 0x60, 0xf9, 0xbf, 0x03, 0x60, 0xf9, 0x1f, 0x04, 0x60, 0xf9, 0x4f, 0x04, 0x60, 0xf9, 0x8f, 0x04, 0x60, 0xf9, 0x1d, 0x05, 0x60, 0xf9, 0x1d, 0x15, 0x60, 0xf9, 0x4d, 0x05, 0x60, 0xf9, 0x4d, 0x15, 0x60, 0xf9, 0x8d, 0x05, 0x60, 0xf9, 0x8d, 0x15, 0x60, 0xf9, 0x1f, 0x00, 0x60, 0xf9, 0x6f, 0x00, 0x60, 0xf9, 0xbf, 0x00, 0x60, 0xf9, 0x3d, 0x01, 0x60, 0xf9, 0x3d, 0x11, 0x60, 0xf9, 0x4d, 0x01, 0x60, 0xf9, 0x4d, 0x11, 0x60, 0xf9, 0x8d, 0x01, 0x60, 0xf9, 0x8d, 0x11, 0xe0, 0xf9, 0x6f, 0x00, 0xe0, 0xf9, 0x9f, 0x04, 0xe0, 0xf9, 0xbf, 0x08, 0xe0, 0xf9, 0x3f, 0x01, 0xe0, 0xf9, 0x5f, 0x05, 0xe0, 0xf9, 0x8f, 0x09, 0xe0, 0xf9, 0x6f, 0x15, 0xe0, 0xf9, 0x5f, 0x19, 0xe0, 0xf9, 0x2f, 0x02, 0xe0, 0xf9, 0x4f, 0x06, 0xe0, 0xf9, 0x8f, 0x0a, 0xe0, 0xf9, 0x6f, 0x06, 0xe0, 0xf9, 0xcf, 0x1a, 0xe0, 0xf9, 0x3f, 0x03, 0xe0, 0xf9, 0x4f, 0x07, 0xe0, 0xf9, 0xaf, 0x0b, 0xe0, 0xf9, 0x7f, 0x07, 0xe0, 0xf9, 0x4f, 0x1b ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ]
+    expected:
+      insns:
+        -
+          asm_text: "vld1.8 {d16}, [r0:64]"
+        -
+          asm_text: "vld1.16 {d16}, [r0]"
+        -
+          asm_text: "vld1.32 {d16}, [r0]"
+        -
+          asm_text: "vld1.64 {d16}, [r0]"
+        -
+          asm_text: "vld1.8 {d16, d17}, [r0:64]"
+        -
+          asm_text: "vld1.16 {d16, d17}, [r0:128]"
+        -
+          asm_text: "vld1.32 {d16, d17}, [r0]"
+        -
+          asm_text: "vld1.64 {d16, d17}, [r0]"
+        -
+          asm_text: "vld2.8 {d16, d17}, [r0:64]"
+        -
+          asm_text: "vld2.16 {d16, d17}, [r0:128]"
+        -
+          asm_text: "vld2.32 {d16, d17}, [r0]"
+        -
+          asm_text: "vld2.8 {d16, d17, d18, d19}, [r0:64]"
+        -
+          asm_text: "vld2.16 {d16, d17, d18, d19}, [r0:128]"
+        -
+          asm_text: "vld2.32 {d16, d17, d18, d19}, [r0:256]"
+        -
+          asm_text: "vld3.8 {d16, d17, d18}, [r0:64]"
+        -
+          asm_text: "vld3.16 {d16, d17, d18}, [r0]"
+        -
+          asm_text: "vld3.32 {d16, d17, d18}, [r0]"
+        -
+          asm_text: "vld3.8 {d16, d18, d20}, [r0:64]!"
+        -
+          asm_text: "vld3.8 {d17, d19, d21}, [r0:64]!"
+        -
+          asm_text: "vld3.16 {d16, d18, d20}, [r0]!"
+        -
+          asm_text: "vld3.16 {d17, d19, d21}, [r0]!"
+        -
+          asm_text: "vld3.32 {d16, d18, d20}, [r0]!"
+        -
+          asm_text: "vld3.32 {d17, d19, d21}, [r0]!"
+        -
+          asm_text: "vld4.8 {d16, d17, d18, d19}, [r0:64]"
+        -
+          asm_text: "vld4.16 {d16, d17, d18, d19}, [r0:128]"
+        -
+          asm_text: "vld4.32 {d16, d17, d18, d19}, [r0:256]"
+        -
+          asm_text: "vld4.8 {d16, d18, d20, d22}, [r0:256]!"
+        -
+          asm_text: "vld4.8 {d17, d19, d21, d23}, [r0:256]!"
+        -
+          asm_text: "vld4.16 {d16, d18, d20, d22}, [r0]!"
+        -
+          asm_text: "vld4.16 {d17, d19, d21, d23}, [r0]!"
+        -
+          asm_text: "vld4.32 {d16, d18, d20, d22}, [r0]!"
+        -
+          asm_text: "vld4.32 {d17, d19, d21, d23}, [r0]!"
+        -
+          asm_text: "vld1.8 {d16[3]}, [r0]"
+        -
+          asm_text: "vld1.16 {d16[2]}, [r0:16]"
+        -
+          asm_text: "vld1.32 {d16[1]}, [r0:32]"
+        -
+          asm_text: "vld2.8 {d16[1], d17[1]}, [r0:16]"
+        -
+          asm_text: "vld2.16 {d16[1], d17[1]}, [r0:32]"
+        -
+          asm_text: "vld2.32 {d16[1], d17[1]}, [r0]"
+        -
+          asm_text: "vld2.16 {d17[1], d19[1]}, [r0]"
+        -
+          asm_text: "vld2.32 {d17[0], d19[0]}, [r0:64]"
+        -
+          asm_text: "vld3.8 {d16[1], d17[1], d18[1]}, [r0]"
+        -
+          asm_text: "vld3.16 {d16[1], d17[1], d18[1]}, [r0]"
+        -
+          asm_text: "vld3.32 {d16[1], d17[1], d18[1]}, [r0]"
+        -
+          asm_text: "vld3.16 {d16[1], d18[1], d20[1]}, [r0]"
+        -
+          asm_text: "vld3.32 {d17[1], d19[1], d21[1]}, [r0]"
+        -
+          asm_text: "vld4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0:32]"
+        -
+          asm_text: "vld4.16 {d16[1], d17[1], d18[1], d19[1]}, [r0]"
+        -
+          asm_text: "vld4.32 {d16[1], d17[1], d18[1], d19[1]}, [r0:128]"
+        -
+          asm_text: "vld4.16 {d16[1], d18[1], d20[1], d22[1]}, [r0:64]"
+        -
+          asm_text: "vld4.32 {d17[0], d19[0], d21[0], d23[0]}, [r0]"
diff --git a/tests/MC/ARM/neont2-vst-encoding.s.yaml b/tests/MC/ARM/neont2-vst-encoding.s.yaml
new file mode 100644
index 000000000..91ffb02e2
--- /dev/null
+++ b/tests/MC/ARM/neont2-vst-encoding.s.yaml
@@ -0,0 +1,102 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x40, 0xf9, 0x1f, 0x07, 0x40, 0xf9, 0x4f, 0x07, 0x40, 0xf9, 0x8f, 0x07, 0x40, 0xf9, 0xcf, 0x07, 0x40, 0xf9, 0x1f, 0x0a, 0x40, 0xf9, 0x6f, 0x0a, 0x40, 0xf9, 0x8f, 0x0a, 0x40, 0xf9, 0xcf, 0x0a, 0x40, 0xf9, 0x1f, 0x08, 0x40, 0xf9, 0x6f, 0x08, 0x40, 0xf9, 0x8f, 0x08, 0x40, 0xf9, 0x1f, 0x03, 0x40, 0xf9, 0x6f, 0x03, 0x40, 0xf9, 0xbf, 0x03, 0x40, 0xf9, 0x1f, 0x04, 0x40, 0xf9, 0x4f, 0x04, 0x40, 0xf9, 0x8f, 0x04, 0x40, 0xf9, 0x1d, 0x05, 0x40, 0xf9, 0x1d, 0x15, 0x40, 0xf9, 0x4d, 0x05, 0x40, 0xf9, 0x4d, 0x15, 0x40, 0xf9, 0x8d, 0x05, 0x40, 0xf9, 0x8d, 0x15, 0x40, 0xf9, 0x1f, 0x00, 0x40, 0xf9, 0x6f, 0x00, 0x40, 0xf9, 0x3d, 0x01, 0x40, 0xf9, 0x3d, 0x11, 0x40, 0xf9, 0x4d, 0x01, 0x40, 0xf9, 0x4d, 0x11, 0x40, 0xf9, 0x8d, 0x01, 0x40, 0xf9, 0x8d, 0x11, 0xc0, 0xf9, 0x3f, 0x01, 0xc0, 0xf9, 0x5f, 0x05, 0xc0, 0xf9, 0x8f, 0x09, 0xc0, 0xf9, 0x6f, 0x15, 0xc0, 0xf9, 0x5f, 0x19, 0xc0, 0xf9, 0x2f, 0x02, 0xc0, 0xf9, 0x4f, 0x06, 0xc0, 0xf9, 0x8f, 0x0a, 0xc0, 0xf9, 0xaf, 0x16, 0xc0, 0xf9, 0x4f, 0x0a, 0xc0, 0xf9, 0x3f, 0x03, 0xc0, 0xf9, 0x4f, 0x07, 0xc0, 0xf9, 0xaf, 0x0b, 0xc0, 0xf9, 0xff, 0x17, 0xc0, 0xf9, 0x4f, 0x1b, 0x04, 0xf9, 0x0f, 0x89 ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ]
+    expected:
+      insns:
+        -
+          asm_text: "vst1.8 {d16}, [r0:64]"
+        -
+          asm_text: "vst1.16 {d16}, [r0]"
+        -
+          asm_text: "vst1.32 {d16}, [r0]"
+        -
+          asm_text: "vst1.64 {d16}, [r0]"
+        -
+          asm_text: "vst1.8 {d16, d17}, [r0:64]"
+        -
+          asm_text: "vst1.16 {d16, d17}, [r0:128]"
+        -
+          asm_text: "vst1.32 {d16, d17}, [r0]"
+        -
+          asm_text: "vst1.64 {d16, d17}, [r0]"
+        -
+          asm_text: "vst2.8 {d16, d17}, [r0:64]"
+        -
+          asm_text: "vst2.16 {d16, d17}, [r0:128]"
+        -
+          asm_text: "vst2.32 {d16, d17}, [r0]"
+        -
+          asm_text: "vst2.8 {d16, d17, d18, d19}, [r0:64]"
+        -
+          asm_text: "vst2.16 {d16, d17, d18, d19}, [r0:128]"
+        -
+          asm_text: "vst2.32 {d16, d17, d18, d19}, [r0:256]"
+        -
+          asm_text: "vst3.8 {d16, d17, d18}, [r0:64]"
+        -
+          asm_text: "vst3.16 {d16, d17, d18}, [r0]"
+        -
+          asm_text: "vst3.32 {d16, d17, d18}, [r0]"
+        -
+          asm_text: "vst3.8 {d16, d18, d20}, [r0:64]!"
+        -
+          asm_text: "vst3.8 {d17, d19, d21}, [r0:64]!"
+        -
+          asm_text: "vst3.16 {d16, d18, d20}, [r0]!"
+        -
+          asm_text: "vst3.16 {d17, d19, d21}, [r0]!"
+        -
+          asm_text: "vst3.32 {d16, d18, d20}, [r0]!"
+        -
+          asm_text: "vst3.32 {d17, d19, d21}, [r0]!"
+        -
+          asm_text: "vst4.8 {d16, d17, d18, d19}, [r0:64]"
+        -
+          asm_text: "vst4.16 {d16, d17, d18, d19}, [r0:128]"
+        -
+          asm_text: "vst4.8 {d16, d18, d20, d22}, [r0:256]!"
+        -
+          asm_text: "vst4.8 {d17, d19, d21, d23}, [r0:256]!"
+        -
+          asm_text: "vst4.16 {d16, d18, d20, d22}, [r0]!"
+        -
+          asm_text: "vst4.16 {d17, d19, d21, d23}, [r0]!"
+        -
+          asm_text: "vst4.32 {d16, d18, d20, d22}, [r0]!"
+        -
+          asm_text: "vst4.32 {d17, d19, d21, d23}, [r0]!"
+        -
+          asm_text: "vst2.8 {d16[1], d17[1]}, [r0:16]"
+        -
+          asm_text: "vst2.16 {d16[1], d17[1]}, [r0:32]"
+        -
+          asm_text: "vst2.32 {d16[1], d17[1]}, [r0]"
+        -
+          asm_text: "vst2.16 {d17[1], d19[1]}, [r0]"
+        -
+          asm_text: "vst2.32 {d17[0], d19[0]}, [r0:64]"
+        -
+          asm_text: "vst3.8 {d16[1], d17[1], d18[1]}, [r0]"
+        -
+          asm_text: "vst3.16 {d16[1], d17[1], d18[1]}, [r0]"
+        -
+          asm_text: "vst3.32 {d16[1], d17[1], d18[1]}, [r0]"
+        -
+          asm_text: "vst3.16 {d17[2], d19[2], d21[2]}, [r0]"
+        -
+          asm_text: "vst3.32 {d16[0], d18[0], d20[0]}, [r0]"
+        -
+          asm_text: "vst4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0:32]"
+        -
+          asm_text: "vst4.16 {d16[1], d17[1], d18[1], d19[1]}, [r0]"
+        -
+          asm_text: "vst4.32 {d16[1], d17[1], d18[1], d19[1]}, [r0:128]"
+        -
+          asm_text: "vst4.16 {d17[3], d19[3], d21[3], d23[3]}, [r0:64]"
+        -
+          asm_text: "vst4.32 {d17[0], d19[0], d21[0], d23[0]}, [r0]"
+        -
+          asm_text: "vst2.8 {d8, d10}, [r4]"
diff --git a/tests/MC/ARM/simple-fp-encoding.s.yaml b/tests/MC/ARM/simple-fp-encoding.s.yaml
new file mode 100644
index 000000000..0775016d4
--- /dev/null
+++ b/tests/MC/ARM/simple-fp-encoding.s.yaml
@@ -0,0 +1,360 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xa0, 0x0b, 0x71, 0xee, 0x80, 0x0a, 0x30, 0xee, 0xe0, 0x0b, 0x71, 0xee, 0xc0, 0x0a, 0x30, 0xee, 0xa0, 0x0b, 0xc1, 0xee, 0x80, 0x0a, 0x80, 0xee, 0xa3, 0x2a, 0xc2, 0xee, 0x07, 0x5b, 0x85, 0xee, 0xa0, 0x0b, 0x61, 0xee, 0xa1, 0x4b, 0x64, 0xee, 0x80, 0x0a, 0x20, 0xee, 0xaa, 0x5a, 0x65, 0xee, 0xe0, 0x0b, 0x61, 0xee, 0xc0, 0x0a, 0x20, 0xee, 0x60, 0x1b, 0xf4, 0xee, 0x40, 0x0a, 0xf4, 0xee, 0x40, 0x1b, 0xf5, 0xee, 0x40, 0x0a, 0xf5, 0xee, 0xe0, 0x1b, 0xf4, 0xee, 0xc0, 0x0a, 0xf4, 0xee, 0xc0, 0x0b, 0xf5, 0xee, 0xc0, 0x0a, 0xb5, 0xee, 0xe0, 0x0b, 0xf0, 0xee, 0xc0, 0x0a, 0xb0, 0xee, 0xe0, 0x0b, 0xb7, 0xee, 0xc0, 0x0a, 0xf7, 0xee, 0x60, 0x0b, 0xf1, 0xee, 0x40, 0x0a, 0xb1, 0xee, 0xe0, 0x0b, 0xf1, 0xee, 0xc0, 0x0a, 0xb1, 0xee, 0xc0, 0x0b, 0xf8, 0xee, 0xc0, 0x0a, 0xb8, 0xee, 0x40, 0x0b, 0xf8, 0xee, 0x40, 0x0a, 0xb8, 0xee, 0xe0, 0x0b, 0xbd, 0xee, 0xc0, 0x0a, 0xbd, 0xee, 0xe0, 0x0b, 0xbc, 0xee, 0xc0, 0x0a, 0xbc, 0xee, 0xa1, 0x0b, 0x42, 0xee, 0x00, 0x0a, 0x41, 0xee, 0xe1, 0x0b, 0x42, 0xee, 0x40, 0x0a, 0x41, 0xee, 0xe1, 0x0b, 0x52, 0xee, 0x40, 0x0a, 0x51, 0xee, 0xa1, 0x0b, 0x52, 0xee, 0x00, 0x0a, 0x51, 0xee, 0x10, 0xfa, 0xf1, 0xee, 0x10, 0xfa, 0xf1, 0xee, 0x10, 0xfa, 0xf1, 0xee, 0x10, 0x2a, 0xf0, 0xee, 0x10, 0x3a, 0xf0, 0xee, 0x10, 0x4a, 0xf7, 0xee, 0x10, 0x5a, 0xf6, 0xee, 0x60, 0x0b, 0xf1, 0x1e, 0x10, 0x0a, 0x00, 0x1e, 0x10, 0x1a, 0x00, 0x0e, 0x10, 0x1a, 0x11, 0xee, 0x10, 0x3a, 0x02, 0xee, 0x12, 0x1b, 0x55, 0xec, 0x14, 0x3b, 0x49, 0xec, 0x10, 0x0a, 0xf1, 0xee, 0x10, 0x0a, 0xf8, 0xee, 0x10, 0x0a, 0xf0, 0xee, 0x10, 0x1a, 0xf9, 0xee, 0x10, 0x8a, 0xfa, 0xee, 0x10, 0x0a, 0xe1, 0xee, 0x10, 0x0a, 0xe8, 0xee, 0x10, 0x0a, 0xe0, 0xee, 0x10, 0x3a, 0xe9, 0xee, 0x10, 0x4a, 0xea, 0xee, 0x08, 0x0b, 0xf0, 0xee, 0x08, 0x0a, 0xb0, 0xee, 0x08, 0x0b, 0xf8, 0xee, 0x08, 0x0a, 0xb8, 0xee, 0x10, 0x0a, 0x00, 0xee, 0x90, 0x1a, 0x00, 0xee, 0x10, 0x2a, 0x01, 0xee, 0x90, 0x3a, 0x01, 0xee, 0x10, 0x0a, 0x10, 0xee, 0x90, 0x1a, 0x10, 0xee, 0x10, 0x2a, 0x11, 0xee, 0x90, 0x3a, 0x11, 0xee, 0x30, 0x0b, 0x51, 0xec, 0x31, 0x1a, 0x42, 0xec, 0x11, 0x1a, 0x42, 0xec, 0x31, 0x1a, 0x52, 0xec, 0x11, 0x1a, 0x52, 0xec, 0x1f, 0x1b, 0x42, 0xec, 0x30, 0x1b, 0x42, 0xec, 0x1f, 0x1b, 0x52, 0xec, 0x30, 0x1b, 0x52, 0xec, 0x00, 0x1b, 0xd0, 0xed, 0x00, 0x0a, 0x9e, 0xed, 0x00, 0x0b, 0x9e, 0xed, 0x08, 0x1b, 0x92, 0xed, 0x08, 0x1b, 0x12, 0xed, 0x00, 0x2b, 0x93, 0xed, 0x00, 0x3b, 0x9f, 0xed, 0x00, 0x3b, 0x9f, 0xed, 0x00, 0x3b, 0x1f, 0xed, 0x00, 0x6a, 0xd0, 0xed, 0x08, 0x0a, 0xd2, 0xed, 0x08, 0x0a, 0x52, 0xed, 0x00, 0x1a, 0x93, 0xed, 0x00, 0x2a, 0xdf, 0xed, 0x00, 0x2a, 0xdf, 0xed, 0x00, 0x2a, 0x5f, 0xed, 0x00, 0x4b, 0x81, 0xed, 0x06, 0x4b, 0x81, 0xed, 0x06, 0x4b, 0x01, 0xed, 0x00, 0x0a, 0x8e, 0xed, 0x00, 0x0b, 0x8e, 0xed, 0x00, 0x2a, 0x81, 0xed, 0x06, 0x2a, 0x81, 0xed, 0x06, 0x2a, 0x01, 0xed, 0x0c, 0x2b, 0x91, 0xec, 0x06, 0x1a, 0x91, 0xec, 0x0c, 0x2b, 0x81, 0xec, 0x06, 0x1a, 0x81, 0xec, 0x10, 0x8b, 0x2d, 0xed, 0x07, 0x0b, 0xb5, 0xec, 0x05, 0x4b, 0x90, 0x0c, 0x07, 0x4b, 0x35, 0x1d, 0x11, 0x0b, 0xa5, 0xec, 0x05, 0x8b, 0x84, 0x0c, 0x07, 0x2b, 0x27, 0x1d, 0x40, 0x0b, 0xbd, 0xee, 0x60, 0x0a, 0xbd, 0xee, 0x40, 0x0b, 0xbc, 0xee, 0x60, 0x0a, 0xbc, 0xee, 0x90, 0x8a, 0x00, 0xee, 0x10, 0x4a, 0x01, 0xee, 0x90, 0x6a, 0x01, 0xee, 0x10, 0x1a, 0x02, 0xee, 0x90, 0x2a, 0x02, 0xee, 0x10, 0x3a, 0x03, 0xee, 0x10, 0x1a, 0x14, 0xee, 0x10, 0x2a, 0x12, 0xee, 0x10, 0x3a, 0x13, 0xee, 0x90, 0x4a, 0x10, 0xee, 0x10, 0x5a, 0x11, 0xee, 0x90, 0x6a, 0x11, 0xee, 0xc6, 0x0a, 0xbb, 0xee, 0xc0, 0x0b, 0xba, 0xee, 0x67, 0x0a, 0xbb, 0xee, 0x40, 0x0b, 0xba, 0xee, 0xc6, 0x0a, 0xfa, 0xee, 0xc0, 0x4b, 0xfb, 0xee, 0x67, 0x8a, 0xfa, 0xee, 0x40, 0x7b, 0xfb, 0xee, 0xc6, 0x6a, 0xbf, 0xee, 0xc0, 0x2b, 0xbe, 0xee, 0x67, 0xea, 0xbf, 0xee, 0x40, 0xfb, 0xbe, 0xee, 0xc6, 0x0a, 0xfe, 0xee, 0xc0, 0x4b, 0xff, 0xee, 0x67, 0x8a, 0xfe, 0xee, 0x40, 0x7b, 0xff, 0xee, 0x10, 0x40, 0x80, 0xf2, 0x12, 0x46, 0x84, 0xf2, 0x00, 0x2a, 0xf7, 0xee, 0x00, 0x2a, 0xf4, 0xee, 0x0e, 0x2a, 0xff, 0xee, 0x03, 0x2a, 0xfe, 0xee, 0x00, 0x6b, 0xb7, 0xee, 0x00, 0x6b, 0xb4, 0xee, 0x0e, 0x6b, 0xbf, 0xee, 0x03, 0x6b, 0xbe, 0xee, 0x10, 0x7f, 0x87, 0xf2, 0x10, 0x7f, 0x84, 0xf2, 0x1e, 0x7f, 0x87, 0xf3, 0x13, 0x7f, 0x86, 0xf3, 0x50, 0x0f, 0xc7, 0xf2, 0x50, 0x0f, 0xc4, 0xf2, 0x5e, 0x0f, 0xc7, 0xf3, 0x53, 0x0f, 0xc6, 0xf3 ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ]
+    expected:
+      insns:
+        -
+          asm_text: "vadd.f64 d16, d17, d16"
+        -
+          asm_text: "vadd.f32 s0, s1, s0"
+        -
+          asm_text: "vsub.f64 d16, d17, d16"
+        -
+          asm_text: "vsub.f32 s0, s1, s0"
+        -
+          asm_text: "vdiv.f64 d16, d17, d16"
+        -
+          asm_text: "vdiv.f32 s0, s1, s0"
+        -
+          asm_text: "vdiv.f32 s5, s5, s7"
+        -
+          asm_text: "vdiv.f64 d5, d5, d7"
+        -
+          asm_text: "vmul.f64 d16, d17, d16"
+        -
+          asm_text: "vmul.f64 d20, d20, d17"
+        -
+          asm_text: "vmul.f32 s0, s1, s0"
+        -
+          asm_text: "vmul.f32 s11, s11, s21"
+        -
+          asm_text: "vnmul.f64 d16, d17, d16"
+        -
+          asm_text: "vnmul.f32 s0, s1, s0"
+        -
+          asm_text: "vcmp.f64 d17, d16"
+        -
+          asm_text: "vcmp.f32 s1, s0"
+        -
+          asm_text: "vcmp.f64 d17, #0"
+        -
+          asm_text: "vcmp.f32 s1, #0"
+        -
+          asm_text: "vcmpe.f64 d17, d16"
+        -
+          asm_text: "vcmpe.f32 s1, s0"
+        -
+          asm_text: "vcmpe.f64 d16, #0"
+        -
+          asm_text: "vcmpe.f32 s0, #0"
+        -
+          asm_text: "vabs.f64 d16, d16"
+        -
+          asm_text: "vabs.f32 s0, s0"
+        -
+          asm_text: "vcvt.f32.f64 s0, d16"
+        -
+          asm_text: "vcvt.f64.f32 d16, s0"
+        -
+          asm_text: "vneg.f64 d16, d16"
+        -
+          asm_text: "vneg.f32 s0, s0"
+        -
+          asm_text: "vsqrt.f64 d16, d16"
+        -
+          asm_text: "vsqrt.f32 s0, s0"
+        -
+          asm_text: "vcvt.f64.s32 d16, s0"
+        -
+          asm_text: "vcvt.f32.s32 s0, s0"
+        -
+          asm_text: "vcvt.f64.u32 d16, s0"
+        -
+          asm_text: "vcvt.f32.u32 s0, s0"
+        -
+          asm_text: "vcvt.s32.f64 s0, d16"
+        -
+          asm_text: "vcvt.s32.f32 s0, s0"
+        -
+          asm_text: "vcvt.u32.f64 s0, d16"
+        -
+          asm_text: "vcvt.u32.f32 s0, s0"
+        -
+          asm_text: "vmla.f64 d16, d18, d17"
+        -
+          asm_text: "vmla.f32 s1, s2, s0"
+        -
+          asm_text: "vmls.f64 d16, d18, d17"
+        -
+          asm_text: "vmls.f32 s1, s2, s0"
+        -
+          asm_text: "vnmla.f64 d16, d18, d17"
+        -
+          asm_text: "vnmla.f32 s1, s2, s0"
+        -
+          asm_text: "vnmls.f64 d16, d18, d17"
+        -
+          asm_text: "vnmls.f32 s1, s2, s0"
+        -
+          asm_text: "vmrs APSR_nzcv, fpscr"
+        -
+          asm_text: "vmrs APSR_nzcv, fpscr"
+        -
+          asm_text: "vmrs APSR_nzcv, fpscr"
+        -
+          asm_text: "vmrs r2, fpsid"
+        -
+          asm_text: "vmrs r3, fpsid"
+        -
+          asm_text: "vmrs r4, mvfr0"
+        -
+          asm_text: "vmrs r5, mvfr1"
+        -
+          asm_text: "vnegne.f64 d16, d16"
+        -
+          asm_text: "vmovne s0, r0"
+        -
+          asm_text: "vmoveq s0, r1"
+        -
+          asm_text: "vmov r1, s2"
+        -
+          asm_text: "vmov s4, r3"
+        -
+          asm_text: "vmov r1, r5, d2"
+        -
+          asm_text: "vmov d4, r3, r9"
+        -
+          asm_text: "vmrs r0, fpscr"
+        -
+          asm_text: "vmrs r0, fpexc"
+        -
+          asm_text: "vmrs r0, fpsid"
+        -
+          asm_text: "vmrs r1, fpinst"
+        -
+          asm_text: "vmrs r8, fpinst2"
+        -
+          asm_text: "vmsr fpscr, r0"
+        -
+          asm_text: "vmsr fpexc, r0"
+        -
+          asm_text: "vmsr fpsid, r0"
+        -
+          asm_text: "vmsr fpinst, r3"
+        -
+          asm_text: "vmsr fpinst2, r4"
+        -
+          asm_text: "vmov.f64 d16, #3.000000e+00"
+        -
+          asm_text: "vmov.f32 s0, #3.000000e+00"
+        -
+          asm_text: "vmov.f64 d16, #-3.000000e+00"
+        -
+          asm_text: "vmov.f32 s0, #-3.000000e+00"
+        -
+          asm_text: "vmov s0, r0"
+        -
+          asm_text: "vmov s1, r1"
+        -
+          asm_text: "vmov s2, r2"
+        -
+          asm_text: "vmov s3, r3"
+        -
+          asm_text: "vmov r0, s0"
+        -
+          asm_text: "vmov r1, s1"
+        -
+          asm_text: "vmov r2, s2"
+        -
+          asm_text: "vmov r3, s3"
+        -
+          asm_text: "vmov r0, r1, d16"
+        -
+          asm_text: "vmov s3, s4, r1, r2"
+        -
+          asm_text: "vmov s2, s3, r1, r2"
+        -
+          asm_text: "vmov r1, r2, s3, s4"
+        -
+          asm_text: "vmov r1, r2, s2, s3"
+        -
+          asm_text: "vmov d15, r1, r2"
+        -
+          asm_text: "vmov d16, r1, r2"
+        -
+          asm_text: "vmov r1, r2, d15"
+        -
+          asm_text: "vmov r1, r2, d16"
+        -
+          asm_text: "vldr d17, [r0]"
+        -
+          asm_text: "vldr s0, [lr]"
+        -
+          asm_text: "vldr d0, [lr]"
+        -
+          asm_text: "vldr d1, [r2, #0x20]"
+        -
+          asm_text: "vldr d1, [r2, #-0x20]"
+        -
+          asm_text: "vldr d2, [r3]"
+        -
+          asm_text: "vldr d3, [pc]"
+        -
+          asm_text: "vldr d3, [pc]"
+        -
+          asm_text: "vldr d3, [pc, #-0]"
+        -
+          asm_text: "vldr s13, [r0]"
+        -
+          asm_text: "vldr s1, [r2, #0x20]"
+        -
+          asm_text: "vldr s1, [r2, #-0x20]"
+        -
+          asm_text: "vldr s2, [r3]"
+        -
+          asm_text: "vldr s5, [pc]"
+        -
+          asm_text: "vldr s5, [pc]"
+        -
+          asm_text: "vldr s5, [pc, #-0]"
+        -
+          asm_text: "vstr d4, [r1]"
+        -
+          asm_text: "vstr d4, [r1, #0x18]"
+        -
+          asm_text: "vstr d4, [r1, #-0x18]"
+        -
+          asm_text: "vstr s0, [lr]"
+        -
+          asm_text: "vstr d0, [lr]"
+        -
+          asm_text: "vstr s4, [r1]"
+        -
+          asm_text: "vstr s4, [r1, #0x18]"
+        -
+          asm_text: "vstr s4, [r1, #-0x18]"
+        -
+          asm_text: "vldmia r1, {d2, d3, d4, d5, d6, d7}"
+        -
+          asm_text: "vldmia r1, {s2, s3, s4, s5, s6, s7}"
+        -
+          asm_text: "vstmia r1, {d2, d3, d4, d5, d6, d7}"
+        -
+          asm_text: "vstmia r1, {s2, s3, s4, s5, s6, s7}"
+        -
+          asm_text: "vpush {d8, d9, d10, d11, d12, d13, d14, d15}"
+        -
+          asm_text: "fldmiax r5!, {d0, d1, d2}"
+        -
+          asm_text: "fldmiaxeq r0, {d4, d5}"
+        -
+          asm_text: "fldmdbxne r5!, {d4, d5, d6}"
+        -
+          asm_text: "fstmiax r5!, {d0, d1, d2, d3, d4, d5, d6, d7}"
+        -
+          asm_text: "fstmiaxeq r4, {d8, d9}"
+        -
+          asm_text: "fstmdbxne r7!, {d2, d3, d4}"
+        -
+          asm_text: "vcvtr.s32.f64 s0, d0"
+        -
+          asm_text: "vcvtr.s32.f32 s0, s1"
+        -
+          asm_text: "vcvtr.u32.f64 s0, d0"
+        -
+          asm_text: "vcvtr.u32.f32 s0, s1"
+        -
+          asm_text: "vmov s1, r8"
+        -
+          asm_text: "vmov s2, r4"
+        -
+          asm_text: "vmov s3, r6"
+        -
+          asm_text: "vmov s4, r1"
+        -
+          asm_text: "vmov s5, r2"
+        -
+          asm_text: "vmov s6, r3"
+        -
+          asm_text: "vmov r1, s8"
+        -
+          asm_text: "vmov r2, s4"
+        -
+          asm_text: "vmov r3, s6"
+        -
+          asm_text: "vmov r4, s1"
+        -
+          asm_text: "vmov r5, s2"
+        -
+          asm_text: "vmov r6, s3"
+        -
+          asm_text: "vcvt.f32.u32 s0, s0, #0x14"
+        -
+          asm_text: "vcvt.f64.s32 d0, d0, #0x20"
+        -
+          asm_text: "vcvt.f32.u16 s0, s0, #1"
+        -
+          asm_text: "vcvt.f64.s16 d0, d0, #0x10"
+        -
+          asm_text: "vcvt.f32.s32 s1, s1, #0x14"
+        -
+          asm_text: "vcvt.f64.u32 d20, d20, #0x20"
+        -
+          asm_text: "vcvt.f32.s16 s17, s17, #1"
+        -
+          asm_text: "vcvt.f64.u16 d23, d23, #0x10"
+        -
+          asm_text: "vcvt.u32.f32 s12, s12, #0x14"
+        -
+          asm_text: "vcvt.s32.f64 d2, d2, #0x20"
+        -
+          asm_text: "vcvt.u16.f32 s28, s28, #1"
+        -
+          asm_text: "vcvt.s16.f64 d15, d15, #0x10"
+        -
+          asm_text: "vcvt.s32.f32 s1, s1, #0x14"
+        -
+          asm_text: "vcvt.u32.f64 d20, d20, #0x20"
+        -
+          asm_text: "vcvt.s16.f32 s17, s17, #1"
+        -
+          asm_text: "vcvt.u16.f64 d23, d23, #0x10"
+        -
+          asm_text: "vmov.i32 d4, #0x0"
+        -
+          asm_text: "vmov.i32 d4, #0x42000000"
+        -
+          asm_text: "vmov.f32 s5, #1.000000e+00"
+        -
+          asm_text: "vmov.f32 s5, #1.250000e-01"
+        -
+          asm_text: "vmov.f32 s5, #-1.875000e+00"
+        -
+          asm_text: "vmov.f32 s5, #-5.937500e-01"
+        -
+          asm_text: "vmov.f64 d6, #1.000000e+00"
+        -
+          asm_text: "vmov.f64 d6, #1.250000e-01"
+        -
+          asm_text: "vmov.f64 d6, #-1.875000e+00"
+        -
+          asm_text: "vmov.f64 d6, #-5.937500e-01"
+        -
+          asm_text: "vmov.f32 d7, #1.000000e+00"
+        -
+          asm_text: "vmov.f32 d7, #1.250000e-01"
+        -
+          asm_text: "vmov.f32 d7, #-1.875000e+00"
+        -
+          asm_text: "vmov.f32 d7, #-5.937500e-01"
+        -
+          asm_text: "vmov.f32 q8, #1.000000e+00"
+        -
+          asm_text: "vmov.f32 q8, #1.250000e-01"
+        -
+          asm_text: "vmov.f32 q8, #-1.875000e+00"
+        -
+          asm_text: "vmov.f32 q8, #-5.937500e-01"
diff --git a/tests/MC/ARM/thumb-add-sub-width.s.yaml b/tests/MC/ARM/thumb-add-sub-width.s.yaml
new file mode 100644
index 000000000..5c235b7da
--- /dev/null
+++ b/tests/MC/ARM/thumb-add-sub-width.s.yaml
@@ -0,0 +1,56 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x08, 0x44, 0x08, 0x44, 0x40, 0x18, 0x40, 0x18, 0x08, 0x44, 0x08, 0x44, 0x40, 0x18, 0x40, 0x18, 0x01, 0xbf, 0x40, 0x18, 0x08, 0x44, 0x10, 0xeb, 0x01, 0x00, 0x10, 0xeb, 0x01, 0x00, 0x40, 0x1a, 0x40, 0x1a, 0xa0, 0xeb, 0x01, 0x00, 0xa0, 0xeb, 0x01, 0x00, 0x40, 0x1a, 0x40, 0x1a, 0x01, 0xbf, 0x40, 0x1a, 0x40, 0x1a, 0xb0, 0xeb, 0x01, 0x00, 0xb0, 0xeb, 0x01, 0x00 ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ]
+    expected:
+      insns:
+        -
+          asm_text: "add r0, r1"
+        -
+          asm_text: "add r0, r1"
+        -
+          asm_text: "adds r0, r0, r1"
+        -
+          asm_text: "adds r0, r0, r1"
+        -
+          asm_text: "add r0, r1"
+        -
+          asm_text: "add r0, r1"
+        -
+          asm_text: "adds r0, r0, r1"
+        -
+          asm_text: "adds r0, r0, r1"
+        -
+          asm_text: "itttt eq"
+        -
+          asm_text: "addeq r0, r0, r1"
+        -
+          asm_text: "addeq r0, r1"
+        -
+          asm_text: "addseq.w r0, r0, r1"
+        -
+          asm_text: "addseq.w r0, r0, r1"
+        -
+          asm_text: "subs r0, r0, r1"
+        -
+          asm_text: "subs r0, r0, r1"
+        -
+          asm_text: "sub.w r0, r0, r1"
+        -
+          asm_text: "sub.w r0, r0, r1"
+        -
+          asm_text: "subs r0, r0, r1"
+        -
+          asm_text: "subs r0, r0, r1"
+        -
+          asm_text: "itttt eq"
+        -
+          asm_text: "subeq r0, r0, r1"
+        -
+          asm_text: "subeq r0, r0, r1"
+        -
+          asm_text: "subseq.w r0, r0, r1"
+        -
+          asm_text: "subseq.w r0, r0, r1"
diff --git a/tests/MC/ARM/thumb-fp-armv8.s.yaml b/tests/MC/ARM/thumb-fp-armv8.s.yaml
new file mode 100644
index 000000000..304c64c36
--- /dev/null
+++ b/tests/MC/ARM/thumb-fp-armv8.s.yaml
@@ -0,0 +1,92 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xb2, 0xee, 0xe0, 0x3b, 0xf3, 0xee, 0xcc, 0x2b, 0xb2, 0xee, 0x60, 0x3b, 0xb3, 0xee, 0x41, 0x2b, 0xbc, 0xfe, 0xe1, 0x1a, 0xbc, 0xfe, 0xc3, 0x1b, 0xbd, 0xfe, 0xeb, 0x3a, 0xbd, 0xfe, 0xe7, 0x3b, 0xbe, 0xfe, 0xc2, 0x0a, 0xbe, 0xfe, 0xc4, 0x0b, 0xff, 0xfe, 0xc4, 0x8a, 0xff, 0xfe, 0xc8, 0x8b, 0xbc, 0xfe, 0x61, 0x1a, 0xbc, 0xfe, 0x43, 0x1b, 0xbd, 0xfe, 0x6b, 0x3a, 0xbd, 0xfe, 0x67, 0x3b, 0xbe, 0xfe, 0x42, 0x0a, 0xbe, 0xfe, 0x44, 0x0b, 0xff, 0xfe, 0x44, 0x8a, 0xff, 0xfe, 0x48, 0x8b, 0x20, 0xfe, 0xab, 0x2a, 0x6f, 0xfe, 0xa7, 0xeb, 0x30, 0xfe, 0x80, 0x0a, 0x3a, 0xfe, 0x24, 0x5b, 0x0e, 0xfe, 0x2b, 0xfa, 0x04, 0xfe, 0x08, 0x2b, 0x58, 0xfe, 0x07, 0xaa, 0x11, 0xfe, 0x2f, 0x0b, 0xc6, 0xfe, 0x00, 0x2a, 0x86, 0xfe, 0xae, 0x5b, 0x80, 0xfe, 0x46, 0x0a, 0x86, 0xfe, 0x49, 0x4b, 0xf6, 0xee, 0xcc, 0x1a, 0xb6, 0xee, 0x64, 0x0a, 0xb8, 0xfe, 0x44, 0x3b, 0xb8, 0xfe, 0x60, 0x6a, 0xb9, 0xfe, 0x44, 0x3b, 0xb9, 0xfe, 0x60, 0x6a, 0xba, 0xfe, 0x44, 0x3b, 0xba, 0xfe, 0x60, 0x6a, 0xbb, 0xfe, 0x44, 0x3b, 0xbb, 0xfe, 0x60, 0x6a ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_V8", "CS_MODE_THUMB" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvtt.f64.f16 d3, s1"
+        -
+          asm_text: "vcvtt.f16.f64 s5, d12"
+        -
+          asm_text: "vcvtb.f64.f16 d3, s1"
+        -
+          asm_text: "vcvtb.f16.f64 s4, d1"
+        -
+          asm_text: "vcvta.s32.f32 s2, s3"
+        -
+          asm_text: "vcvta.s32.f64 s2, d3"
+        -
+          asm_text: "vcvtn.s32.f32 s6, s23"
+        -
+          asm_text: "vcvtn.s32.f64 s6, d23"
+        -
+          asm_text: "vcvtp.s32.f32 s0, s4"
+        -
+          asm_text: "vcvtp.s32.f64 s0, d4"
+        -
+          asm_text: "vcvtm.s32.f32 s17, s8"
+        -
+          asm_text: "vcvtm.s32.f64 s17, d8"
+        -
+          asm_text: "vcvta.u32.f32 s2, s3"
+        -
+          asm_text: "vcvta.u32.f64 s2, d3"
+        -
+          asm_text: "vcvtn.u32.f32 s6, s23"
+        -
+          asm_text: "vcvtn.u32.f64 s6, d23"
+        -
+          asm_text: "vcvtp.u32.f32 s0, s4"
+        -
+          asm_text: "vcvtp.u32.f64 s0, d4"
+        -
+          asm_text: "vcvtm.u32.f32 s17, s8"
+        -
+          asm_text: "vcvtm.u32.f64 s17, d8"
+        -
+          asm_text: "vselge.f32 s4, s1, s23"
+        -
+          asm_text: "vselge.f64 d30, d31, d23"
+        -
+          asm_text: "vselgt.f32 s0, s1, s0"
+        -
+          asm_text: "vselgt.f64 d5, d10, d20"
+        -
+          asm_text: "vseleq.f32 s30, s28, s23"
+        -
+          asm_text: "vseleq.f64 d2, d4, d8"
+        -
+          asm_text: "vselvs.f32 s21, s16, s14"
+        -
+          asm_text: "vselvs.f64 d0, d1, d31"
+        -
+          asm_text: "vmaxnm.f32 s5, s12, s0"
+        -
+          asm_text: "vmaxnm.f64 d5, d22, d30"
+        -
+          asm_text: "vminnm.f32 s0, s0, s12"
+        -
+          asm_text: "vminnm.f64 d4, d6, d9"
+        -
+          asm_text: "vrintz.f32 s3, s24"
+        -
+          asm_text: "vrintr.f32 s0, s9"
+        -
+          asm_text: "vrinta.f64 d3, d4"
+        -
+          asm_text: "vrinta.f32 s12, s1"
+        -
+          asm_text: "vrintn.f64 d3, d4"
+        -
+          asm_text: "vrintn.f32 s12, s1"
+        -
+          asm_text: "vrintp.f64 d3, d4"
+        -
+          asm_text: "vrintp.f32 s12, s1"
+        -
+          asm_text: "vrintm.f64 d3, d4"
+        -
+          asm_text: "vrintm.f32 s12, s1"
diff --git a/tests/MC/ARM/thumb-hints.s.yaml b/tests/MC/ARM/thumb-hints.s.yaml
new file mode 100644
index 000000000..a9df28249
--- /dev/null
+++ b/tests/MC/ARM/thumb-hints.s.yaml
@@ -0,0 +1,30 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xbf, 0x10, 0xbf, 0x20, 0xbf, 0x30, 0xbf, 0x40, 0xbf, 0xbf, 0xf3, 0x5f, 0x8f, 0xbf, 0xf3, 0x5f, 0x8f, 0xbf, 0xf3, 0x4f, 0x8f, 0xbf, 0xf3, 0x4f, 0x8f, 0xbf, 0xf3, 0x6f, 0x8f, 0xbf, 0xf3, 0x6f, 0x8f ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ]
+    expected:
+      insns:
+        -
+          asm_text: "nop"
+        -
+          asm_text: "yield"
+        -
+          asm_text: "wfe"
+        -
+          asm_text: "wfi"
+        -
+          asm_text: "sev"
+        -
+          asm_text: "dmb sy"
+        -
+          asm_text: "dmb sy"
+        -
+          asm_text: "dsb sy"
+        -
+          asm_text: "dsb sy"
+        -
+          asm_text: "isb sy"
+        -
+          asm_text: "isb sy"
diff --git a/tests/MC/ARM/thumb-mov.s.yaml b/tests/MC/ARM/thumb-mov.s.yaml
new file mode 100644
index 000000000..5ea3a9ab4
--- /dev/null
+++ b/tests/MC/ARM/thumb-mov.s.yaml
@@ -0,0 +1,24 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x85, 0x46, 0x68, 0x46, 0xed, 0x46, 0x87, 0x46, 0x78, 0x46, 0xff, 0x46, 0x4f, 0xea, 0x00, 0x0d, 0x4f, 0xea, 0x0d, 0x00 ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov sp, r0"
+        -
+          asm_text: "mov r0, sp"
+        -
+          asm_text: "mov sp, sp"
+        -
+          asm_text: "mov pc, r0"
+        -
+          asm_text: "mov r0, pc"
+        -
+          asm_text: "mov pc, pc"
+        -
+          asm_text: "mov.w sp, r0"
+        -
+          asm_text: "mov.w r0, sp"
diff --git a/tests/MC/ARM/thumb-neon-crypto.s.yaml b/tests/MC/ARM/thumb-neon-crypto.s.yaml
new file mode 100644
index 000000000..d0091047b
--- /dev/null
+++ b/tests/MC/ARM/thumb-neon-crypto.s.yaml
@@ -0,0 +1,38 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xb0, 0xff, 0x42, 0x03, 0xb0, 0xff, 0x02, 0x03, 0xb0, 0xff, 0xc2, 0x03, 0xb0, 0xff, 0x82, 0x03, 0xb9, 0xff, 0xc2, 0x02, 0xba, 0xff, 0x82, 0x03, 0xba, 0xff, 0xc2, 0x03, 0x02, 0xef, 0x44, 0x0c, 0x22, 0xef, 0x44, 0x0c, 0x12, 0xef, 0x44, 0x0c, 0x32, 0xef, 0x44, 0x0c, 0x02, 0xff, 0x44, 0x0c, 0x12, 0xff, 0x44, 0x0c, 0x22, 0xff, 0x44, 0x0c, 0xe0, 0xef, 0xa1, 0x0e ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_V8", "CS_MODE_THUMB" ]
+    expected:
+      insns:
+        -
+          asm_text: "aesd.8 q0, q1"
+        -
+          asm_text: "aese.8 q0, q1"
+        -
+          asm_text: "aesimc.8 q0, q1"
+        -
+          asm_text: "aesmc.8 q0, q1"
+        -
+          asm_text: "sha1h.32 q0, q1"
+        -
+          asm_text: "sha1su1.32 q0, q1"
+        -
+          asm_text: "sha256su0.32 q0, q1"
+        -
+          asm_text: "sha1c.32 q0, q1, q2"
+        -
+          asm_text: "sha1m.32 q0, q1, q2"
+        -
+          asm_text: "sha1p.32 q0, q1, q2"
+        -
+          asm_text: "sha1su0.32 q0, q1, q2"
+        -
+          asm_text: "sha256h.32 q0, q1, q2"
+        -
+          asm_text: "sha256h2.32 q0, q1, q2"
+        -
+          asm_text: "sha256su1.32 q0, q1, q2"
+        -
+          asm_text: "vmull.p64 q8, d16, d17"
diff --git a/tests/MC/ARM/thumb-neon-v8.s.yaml b/tests/MC/ARM/thumb-neon-v8.s.yaml
new file mode 100644
index 000000000..6d8fe53db
--- /dev/null
+++ b/tests/MC/ARM/thumb-neon-v8.s.yaml
@@ -0,0 +1,82 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x05, 0xff, 0x11, 0x4f, 0x08, 0xff, 0x5c, 0x4f, 0x24, 0xff, 0x3e, 0x5f, 0x2a, 0xff, 0xd4, 0x0f, 0xbb, 0xff, 0x06, 0x40, 0xbb, 0xff, 0x8a, 0xc0, 0xbb, 0xff, 0x4c, 0x80, 0xbb, 0xff, 0xe4, 0x80, 0xbb, 0xff, 0x2e, 0x13, 0xbb, 0xff, 0x8a, 0xc3, 0xbb, 0xff, 0x64, 0x23, 0xfb, 0xff, 0xc2, 0xa3, 0xbb, 0xff, 0x21, 0xf1, 0xbb, 0xff, 0x83, 0x51, 0xbb, 0xff, 0x60, 0x61, 0xbb, 0xff, 0xc6, 0xa1, 0xbb, 0xff, 0x25, 0xb2, 0xbb, 0xff, 0xa7, 0xe2, 0xbb, 0xff, 0x6e, 0x82, 0xfb, 0xff, 0xe0, 0x22, 0xba, 0xff, 0x00, 0x34, 0xba, 0xff, 0x48, 0x24, 0xba, 0xff, 0x8c, 0x54, 0xba, 0xff, 0xc6, 0x04, 0xba, 0xff, 0x00, 0x35, 0xfa, 0xff, 0x44, 0x05, 0xba, 0xff, 0xa2, 0xc5, 0xfa, 0xff, 0xc8, 0x25, 0xba, 0xff, 0x80, 0x36, 0xba, 0xff, 0xc8, 0x26, 0xba, 0xff, 0x80, 0x37, 0xba, 0xff, 0xc8, 0x27, 0xba, 0xff, 0x00, 0x34, 0xba, 0xff, 0xc6, 0x04, 0xba, 0xff, 0x00, 0x35, 0xfa, 0xff, 0xc8, 0x25, 0xba, 0xff, 0xc8, 0x27 ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_V8", "CS_MODE_THUMB" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmaxnm.f32 d4, d5, d1"
+        -
+          asm_text: "vmaxnm.f32 q2, q4, q6"
+        -
+          asm_text: "vminnm.f32 d5, d4, d30"
+        -
+          asm_text: "vminnm.f32 q0, q13, q2"
+        -
+          asm_text: "vcvta.s32.f32 d4, d6"
+        -
+          asm_text: "vcvta.u32.f32 d12, d10"
+        -
+          asm_text: "vcvta.s32.f32 q4, q6"
+        -
+          asm_text: "vcvta.u32.f32 q4, q10"
+        -
+          asm_text: "vcvtm.s32.f32 d1, d30"
+        -
+          asm_text: "vcvtm.u32.f32 d12, d10"
+        -
+          asm_text: "vcvtm.s32.f32 q1, q10"
+        -
+          asm_text: "vcvtm.u32.f32 q13, q1"
+        -
+          asm_text: "vcvtn.s32.f32 d15, d17"
+        -
+          asm_text: "vcvtn.u32.f32 d5, d3"
+        -
+          asm_text: "vcvtn.s32.f32 q3, q8"
+        -
+          asm_text: "vcvtn.u32.f32 q5, q3"
+        -
+          asm_text: "vcvtp.s32.f32 d11, d21"
+        -
+          asm_text: "vcvtp.u32.f32 d14, d23"
+        -
+          asm_text: "vcvtp.s32.f32 q4, q15"
+        -
+          asm_text: "vcvtp.u32.f32 q9, q8"
+        -
+          asm_text: "vrintn.f32 d3, d0"
+        -
+          asm_text: "vrintn.f32 q1, q4"
+        -
+          asm_text: "vrintx.f32 d5, d12"
+        -
+          asm_text: "vrintx.f32 q0, q3"
+        -
+          asm_text: "vrinta.f32 d3, d0"
+        -
+          asm_text: "vrinta.f32 q8, q2"
+        -
+          asm_text: "vrintz.f32 d12, d18"
+        -
+          asm_text: "vrintz.f32 q9, q4"
+        -
+          asm_text: "vrintm.f32 d3, d0"
+        -
+          asm_text: "vrintm.f32 q1, q4"
+        -
+          asm_text: "vrintp.f32 d3, d0"
+        -
+          asm_text: "vrintp.f32 q1, q4"
+        -
+          asm_text: "vrintn.f32 d3, d0"
+        -
+          asm_text: "vrintx.f32 q0, q3"
+        -
+          asm_text: "vrinta.f32 d3, d0"
+        -
+          asm_text: "vrintz.f32 q9, q4"
+        -
+          asm_text: "vrintp.f32 q1, q4"
diff --git a/tests/MC/ARM/thumb-shift-encoding.s.yaml b/tests/MC/ARM/thumb-shift-encoding.s.yaml
new file mode 100644
index 000000000..4909702ff
--- /dev/null
+++ b/tests/MC/ARM/thumb-shift-encoding.s.yaml
@@ -0,0 +1,44 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x6e, 0xeb, 0x00, 0x0c, 0x68, 0xeb, 0x19, 0x01, 0x67, 0xeb, 0x1a, 0x42, 0x66, 0xeb, 0x0a, 0x03, 0x65, 0xeb, 0x0e, 0x44, 0x64, 0xeb, 0x2b, 0x05, 0x63, 0xeb, 0x2c, 0x46, 0x62, 0xeb, 0x3c, 0x07, 0x61, 0xeb, 0x30, 0x48, 0x0e, 0xea, 0x00, 0x0c, 0x08, 0xea, 0x19, 0x01, 0x07, 0xea, 0x1a, 0x42, 0x06, 0xea, 0x0a, 0x03, 0x05, 0xea, 0x0e, 0x44, 0x04, 0xea, 0x2b, 0x05, 0x03, 0xea, 0x2c, 0x46, 0x02, 0xea, 0x3c, 0x07, 0x01, 0xea, 0x30, 0x48 ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ]
+    expected:
+      insns:
+        -
+          asm_text: "sbc.w r12, lr, r0"
+        -
+          asm_text: "sbc.w r1, r8, r9, lsr #0x20"
+        -
+          asm_text: "sbc.w r2, r7, r10, lsr #0x10"
+        -
+          asm_text: "sbc.w r3, r6, r10"
+        -
+          asm_text: "sbc.w r4, r5, lr, lsl #0x10"
+        -
+          asm_text: "sbc.w r5, r4, r11, asr #0x20"
+        -
+          asm_text: "sbc.w r6, r3, r12, asr #0x10"
+        -
+          asm_text: "sbc.w r7, r2, r12, rrx"
+        -
+          asm_text: "sbc.w r8, r1, r0, ror #0x10"
+        -
+          asm_text: "and.w r12, lr, r0"
+        -
+          asm_text: "and.w r1, r8, r9, lsr #0x20"
+        -
+          asm_text: "and.w r2, r7, r10, lsr #0x10"
+        -
+          asm_text: "and.w r3, r6, r10"
+        -
+          asm_text: "and.w r4, r5, lr, lsl #0x10"
+        -
+          asm_text: "and.w r5, r4, r11, asr #0x20"
+        -
+          asm_text: "and.w r6, r3, r12, asr #0x10"
+        -
+          asm_text: "and.w r7, r2, r12, rrx"
+        -
+          asm_text: "and.w r8, r1, r0, ror #0x10"
diff --git a/tests/MC/ARM/thumb.s.yaml b/tests/MC/ARM/thumb.s.yaml
new file mode 100644
index 000000000..8bff9f523
--- /dev/null
+++ b/tests/MC/ARM/thumb.s.yaml
@@ -0,0 +1,44 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x91, 0x42, 0x16, 0xbc, 0xfe, 0xde, 0xc8, 0x47, 0xd0, 0x47, 0x1a, 0xba, 0x63, 0xba, 0xf5, 0xba, 0x5a, 0xb2, 0x1a, 0xb2, 0x2c, 0x42, 0xf3, 0xb2, 0xb3, 0xb2, 0x8b, 0x58, 0x02, 0xbe, 0xc0, 0x46, 0x67, 0xb6, 0x78, 0x46 ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmp r1, r2"
+        -
+          asm_text: "pop {r1, r2, r4}"
+        -
+          asm_text: "trap"
+        -
+          asm_text: "blx r9"
+        -
+          asm_text: "blx r10"
+        -
+          asm_text: "rev r2, r3"
+        -
+          asm_text: "rev16 r3, r4"
+        -
+          asm_text: "revsh r5, r6"
+        -
+          asm_text: "sxtb r2, r3"
+        -
+          asm_text: "sxth r2, r3"
+        -
+          asm_text: "tst r4, r5"
+        -
+          asm_text: "uxtb r3, r6"
+        -
+          asm_text: "uxth r3, r6"
+        -
+          asm_text: "ldr r3, [r1, r2]"
+        -
+          asm_text: "bkpt #2"
+        -
+          asm_text: "mov r8, r8"
+        -
+          asm_text: "cpsie aif"
+        -
+          asm_text: "mov r0, pc"
diff --git a/tests/MC/ARM/thumb2-b.w-encodingT4.s.yaml b/tests/MC/ARM/thumb2-b.w-encodingT4.s.yaml
new file mode 100644
index 000000000..6f5e22088
--- /dev/null
+++ b/tests/MC/ARM/thumb2-b.w-encodingT4.s.yaml
@@ -0,0 +1,10 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x36, 0xf0, 0x06, 0xbc ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ]
+    expected:
+      insns:
+        -
+          asm_text: "b.w #0x3680c"
diff --git a/tests/MC/ARM/thumb2-branches.s.yaml b/tests/MC/ARM/thumb2-branches.s.yaml
new file mode 100644
index 000000000..b700f2ae1
--- /dev/null
+++ b/tests/MC/ARM/thumb2-branches.s.yaml
@@ -0,0 +1,192 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xe4, 0xff, 0xe3, 0xff, 0xf7, 0x00, 0xbc, 0x00, 0xf0, 0xff, 0xbb, 0x66, 0xf6, 0x30, 0xbc, 0x99, 0xf1, 0xcf, 0xbb, 0x00, 0xe4, 0xff, 0xe3, 0xff, 0xf7, 0xff, 0xbb, 0x00, 0xf0, 0x00, 0xbc, 0x66, 0xf6, 0x30, 0xbc, 0x99, 0xf1, 0xcf, 0xbb, 0x08, 0xbf, 0x00, 0xe4, 0x18, 0xbf, 0x01, 0xe4, 0xc8, 0xbf, 0xff, 0xf7, 0x00, 0xbc, 0xd8, 0xbf, 0x00, 0xf0, 0xff, 0xbb, 0xa8, 0xbf, 0x66, 0xf6, 0x30, 0xbc, 0xb8, 0xbf, 0x99, 0xf1, 0xcf, 0xbb, 0x80, 0xd0, 0x7f, 0xd1, 0x00, 0xf0, 0x80, 0xf8, 0x18, 0xbf, 0x00, 0xf0, 0x80, 0xf8, 0x3f, 0xf5, 0x80, 0xaf, 0x40, 0xf0, 0x7f, 0x80, 0xc0, 0xf6, 0x00, 0x80, 0xbf, 0xf2, 0xff, 0xaf, 0x80, 0xd1, 0x7f, 0xdc, 0x7f, 0xf4, 0x7f, 0xaf, 0x00, 0xf3, 0x80, 0x80, 0x40, 0xf4, 0x00, 0x80, 0x3f, 0xf3, 0xff, 0xaf, 0x08, 0xbf, 0x08, 0x44, 0x40, 0xd1, 0x0c, 0xbf, 0x08, 0x44, 0x40, 0xe0, 0x00, 0xe4, 0xff, 0xe3, 0xff, 0xf7, 0x00, 0xbc, 0x00, 0xf0, 0xff, 0xbb, 0x66, 0xf6, 0x30, 0xbc, 0x99, 0xf1, 0xcf, 0xbb, 0x00, 0xe4, 0xff, 0xe3, 0xff, 0xf7, 0xff, 0xbb, 0x00, 0xf0, 0x00, 0xbc, 0x66, 0xf6, 0x30, 0xbc, 0x99, 0xf1, 0xcf, 0xbb, 0x08, 0xbf, 0x00, 0xe4, 0x18, 0xbf, 0x01, 0xe4, 0xc8, 0xbf, 0xff, 0xf7, 0x00, 0xbc, 0xd8, 0xbf, 0x00, 0xf0, 0xff, 0xbb, 0xa8, 0xbf, 0x66, 0xf6, 0x30, 0xbc, 0xb8, 0xbf, 0x99, 0xf1, 0xcf, 0xbb, 0x80, 0xd0, 0x7f, 0xd1, 0x3f, 0xf5, 0x80, 0xaf, 0x40, 0xf0, 0x7f, 0x80, 0xc0, 0xf6, 0x00, 0x80, 0xbf, 0xf2, 0xff, 0xaf, 0x80, 0xd1, 0x7f, 0xdc, 0x7f, 0xf4, 0x7f, 0xaf, 0x00, 0xf3, 0x80, 0x80, 0x40, 0xf4, 0x00, 0x80, 0x3f, 0xf3, 0xff, 0xaf, 0x08, 0xbf, 0x08, 0x44, 0x40, 0xd1, 0x0c, 0xbf, 0x08, 0x44, 0x40, 0xe0, 0x01, 0xe0, 0x00, 0xf0, 0x01, 0xf8, 0x01, 0xd0, 0x08, 0xb1, 0x00, 0xf0, 0x02, 0xe8 ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ]
+    expected:
+      insns:
+        -
+          asm_text: "b #-0x800"
+        -
+          asm_text: "b #0x7fe"
+        -
+          asm_text: "b.w #-0x800"
+        -
+          asm_text: "b.w #0x7fe"
+        -
+          asm_text: "b.w #-0x1997a0"
+        -
+          asm_text: "b.w #0x19979e"
+        -
+          asm_text: "b #-0x800"
+        -
+          asm_text: "b #0x7fe"
+        -
+          asm_text: "b.w #-0x802"
+        -
+          asm_text: "b.w #0x800"
+        -
+          asm_text: "b.w #-0x1997a0"
+        -
+          asm_text: "b.w #0x19979e"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "beq #-0x800"
+        -
+          asm_text: "it ne"
+        -
+          asm_text: "bne #-0x7fe"
+        -
+          asm_text: "it gt"
+        -
+          asm_text: "bgt.w #-0x800"
+        -
+          asm_text: "it le"
+        -
+          asm_text: "ble.w #0x7fe"
+        -
+          asm_text: "it ge"
+        -
+          asm_text: "bge.w #-0x1997a0"
+        -
+          asm_text: "it lt"
+        -
+          asm_text: "blt.w #0x19979e"
+        -
+          asm_text: "beq #-0x100"
+        -
+          asm_text: "bne #0xfe"
+        -
+          asm_text: "bl #0x100"
+        -
+          asm_text: "it ne"
+        -
+          asm_text: "blne #0x100"
+        -
+          asm_text: "bmi.w #-0x100"
+        -
+          asm_text: "bne.w #0xfe"
+        -
+          asm_text: "blt.w #-0x100000"
+        -
+          asm_text: "bge.w #0xffffe"
+        -
+          asm_text: "bne #-0x100"
+        -
+          asm_text: "bgt #0xfe"
+        -
+          asm_text: "bne.w #-0x102"
+        -
+          asm_text: "bgt.w #0x100"
+        -
+          asm_text: "bne.w #-0x100000"
+        -
+          asm_text: "bgt.w #0xffffe"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "addeq r0, r1"
+        -
+          asm_text: "bne #0x80"
+        -
+          asm_text: "ite eq"
+        -
+          asm_text: "addeq r0, r1"
+        -
+          asm_text: "bne #0x80"
+        -
+          asm_text: "b #-0x800"
+        -
+          asm_text: "b #0x7fe"
+        -
+          asm_text: "b.w #-0x800"
+        -
+          asm_text: "b.w #0x7fe"
+        -
+          asm_text: "b.w #-0x1997a0"
+        -
+          asm_text: "b.w #0x19979e"
+        -
+          asm_text: "b #-0x800"
+        -
+          asm_text: "b #0x7fe"
+        -
+          asm_text: "b.w #-0x802"
+        -
+          asm_text: "b.w #0x800"
+        -
+          asm_text: "b.w #-0x1997a0"
+        -
+          asm_text: "b.w #0x19979e"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "beq #-0x800"
+        -
+          asm_text: "it ne"
+        -
+          asm_text: "bne #-0x7fe"
+        -
+          asm_text: "it gt"
+        -
+          asm_text: "bgt.w #-0x800"
+        -
+          asm_text: "it le"
+        -
+          asm_text: "ble.w #0x7fe"
+        -
+          asm_text: "it ge"
+        -
+          asm_text: "bge.w #-0x1997a0"
+        -
+          asm_text: "it lt"
+        -
+          asm_text: "blt.w #0x19979e"
+        -
+          asm_text: "beq #-0x100"
+        -
+          asm_text: "bne #0xfe"
+        -
+          asm_text: "bmi.w #-0x100"
+        -
+          asm_text: "bne.w #0xfe"
+        -
+          asm_text: "blt.w #-0x100000"
+        -
+          asm_text: "bge.w #0xffffe"
+        -
+          asm_text: "bne #-0x100"
+        -
+          asm_text: "bgt #0xfe"
+        -
+          asm_text: "bne.w #-0x102"
+        -
+          asm_text: "bgt.w #0x100"
+        -
+          asm_text: "bne.w #-0x100000"
+        -
+          asm_text: "bgt.w #0xffffe"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "addeq r0, r1"
+        -
+          asm_text: "bne #0x80"
+        -
+          asm_text: "ite eq"
+        -
+          asm_text: "addeq r0, r1"
+        -
+          asm_text: "bne #0x80"
+        -
+          asm_text: "b #2"
+        -
+          asm_text: "bl #2"
+        -
+          asm_text: "beq #2"
+        -
+          asm_text: "cbz r0, #2"
+        -
+          asm_text: "blx #4"
diff --git a/tests/MC/ARM/thumb2-bxj-v8.s.yaml b/tests/MC/ARM/thumb2-bxj-v8.s.yaml
new file mode 100644
index 000000000..280932a4d
--- /dev/null
+++ b/tests/MC/ARM/thumb2-bxj-v8.s.yaml
@@ -0,0 +1,10 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xcd, 0xf3, 0x00, 0x8f ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_V8", "CS_MODE_THUMB" ]
+    expected:
+      insns:
+        -
+          asm_text: "bxj sp"
diff --git a/tests/MC/ARM/thumb2-bxj.s.yaml b/tests/MC/ARM/thumb2-bxj.s.yaml
new file mode 100644
index 000000000..51e783862
--- /dev/null
+++ b/tests/MC/ARM/thumb2-bxj.s.yaml
@@ -0,0 +1,10 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xc2, 0xf3, 0x00, 0x8f ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ]
+    expected:
+      insns:
+        -
+          asm_text: "bxj r2"
diff --git a/tests/MC/ARM/thumb2-ldr.w-str.w.s.yaml b/tests/MC/ARM/thumb2-ldr.w-str.w.s.yaml
new file mode 100644
index 000000000..baf6f7437
--- /dev/null
+++ b/tests/MC/ARM/thumb2-ldr.w-str.w.s.yaml
@@ -0,0 +1,118 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x51, 0xf8, 0x04, 0x3b, 0x51, 0xf8, 0x04, 0x3b, 0x40, 0xf8, 0x04, 0x3b, 0x40, 0xf8, 0x04, 0x3b, 0x51, 0xf8, 0x04, 0x3d, 0x51, 0xf8, 0x04, 0x3d, 0x40, 0xf8, 0x04, 0x3d, 0x40, 0xf8, 0x04, 0x3d, 0x51, 0xf8, 0x04, 0x0d, 0x51, 0xf8, 0x04, 0xdd, 0x51, 0xf8, 0x04, 0xfd, 0x50, 0xf8, 0x04, 0x1d, 0x5d, 0xf8, 0x04, 0x1d, 0x50, 0xf8, 0xff, 0x1f, 0x50, 0xf8, 0xff, 0x1d, 0x50, 0xf8, 0x00, 0x1f, 0x08, 0xbf, 0x50, 0xf8, 0xff, 0x1f, 0xd8, 0xbf, 0x50, 0xf8, 0xff, 0x1f, 0x51, 0xf8, 0x04, 0x0b, 0x51, 0xf8, 0x04, 0xdb, 0x51, 0xf8, 0x04, 0xfb, 0x51, 0xf8, 0x04, 0x0b, 0x5d, 0xf8, 0x04, 0x0b, 0x5f, 0xf8, 0x04, 0x0b, 0x51, 0xf8, 0xff, 0x0b, 0x51, 0xf8, 0x00, 0x0b, 0x51, 0xf8, 0xff, 0x09, 0x08, 0xbf, 0x51, 0xf8, 0xff, 0x0b, 0xd8, 0xbf, 0x51, 0xf8, 0xff, 0x0b, 0x40, 0xf8, 0x04, 0x1d, 0x40, 0xf8, 0x04, 0xdd, 0x42, 0xf8, 0x04, 0x1d, 0x4d, 0xf8, 0x04, 0x1d, 0x42, 0xf8, 0xff, 0x1f, 0x42, 0xf8, 0x00, 0x1f, 0x42, 0xf8, 0xff, 0x1d, 0x08, 0xbf, 0x42, 0xf8, 0xff, 0x1f, 0xd8, 0xbf, 0x42, 0xf8, 0xff, 0x1f, 0x40, 0xf8, 0x04, 0x1b, 0x40, 0xf8, 0x04, 0xdb, 0x41, 0xf8, 0x04, 0x0b, 0x4d, 0xf8, 0x04, 0x0b, 0x40, 0xf8, 0xff, 0x1b, 0x40, 0xf8, 0x00, 0x1b, 0x40, 0xf8, 0xff, 0x19, 0x08, 0xbf, 0x40, 0xf8, 0xff, 0x1b, 0xd8, 0xbf, 0x40, 0xf8, 0xff, 0x1b ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr r3, [r1], #4"
+        -
+          asm_text: "ldr r3, [r1], #4"
+        -
+          asm_text: "str r3, [r0], #4"
+        -
+          asm_text: "str r3, [r0], #4"
+        -
+          asm_text: "ldr r3, [r1, #-4]!"
+        -
+          asm_text: "ldr r3, [r1, #-4]!"
+        -
+          asm_text: "str r3, [r0, #-4]!"
+        -
+          asm_text: "str r3, [r0, #-4]!"
+        -
+          asm_text: "ldr r0, [r1, #-4]!"
+        -
+          asm_text: "ldr sp, [r1, #-4]!"
+        -
+          asm_text: "ldr pc, [r1, #-4]!"
+        -
+          asm_text: "ldr r1, [r0, #-4]!"
+        -
+          asm_text: "ldr r1, [sp, #-4]!"
+        -
+          asm_text: "ldr r1, [r0, #0xff]!"
+        -
+          asm_text: "ldr r1, [r0, #-0xff]!"
+        -
+          asm_text: "ldr r1, [r0, #0]!"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "ldreq r1, [r0, #0xff]!"
+        -
+          asm_text: "it le"
+        -
+          asm_text: "ldrle r1, [r0, #0xff]!"
+        -
+          asm_text: "ldr r0, [r1], #4"
+        -
+          asm_text: "ldr sp, [r1], #4"
+        -
+          asm_text: "ldr pc, [r1], #4"
+        -
+          asm_text: "ldr r0, [r1], #4"
+        -
+          asm_text: "pop {r0}"
+        -
+          asm_text: "ldr.w r0, [pc, #-0xb04]"
+        -
+          asm_text: "ldr r0, [r1], #0xff"
+        -
+          asm_text: "ldr r0, [r1], #0"
+        -
+          asm_text: "ldr r0, [r1], #-0xff"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "ldreq r0, [r1], #0xff"
+        -
+          asm_text: "it le"
+        -
+          asm_text: "ldrle r0, [r1], #0xff"
+        -
+          asm_text: "str r1, [r0, #-4]!"
+        -
+          asm_text: "str sp, [r0, #-4]!"
+        -
+          asm_text: "str r1, [r2, #-4]!"
+        -
+          asm_text: "str r1, [sp, #-4]!"
+        -
+          asm_text: "str r1, [r2, #0xff]!"
+        -
+          asm_text: "str r1, [r2, #0]!"
+        -
+          asm_text: "str r1, [r2, #-0xff]!"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "streq r1, [r2, #0xff]!"
+        -
+          asm_text: "it le"
+        -
+          asm_text: "strle r1, [r2, #0xff]!"
+        -
+          asm_text: "str r1, [r0], #4"
+        -
+          asm_text: "str sp, [r0], #4"
+        -
+          asm_text: "str r0, [r1], #4"
+        -
+          asm_text: "str r0, [sp], #4"
+        -
+          asm_text: "str r1, [r0], #0xff"
+        -
+          asm_text: "str r1, [r0], #0"
+        -
+          asm_text: "str r1, [r0], #-0xff"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "streq r1, [r0], #0xff"
+        -
+          asm_text: "it le"
+        -
+          asm_text: "strle r1, [r0], #0xff"
diff --git a/tests/MC/ARM/thumb2-ldrexd-strexd.s.yaml b/tests/MC/ARM/thumb2-ldrexd-strexd.s.yaml
new file mode 100644
index 000000000..044932efb
--- /dev/null
+++ b/tests/MC/ARM/thumb2-ldrexd-strexd.s.yaml
@@ -0,0 +1,12 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xd2, 0xe8, 0x7f, 0x01, 0xc6, 0xe8, 0x73, 0x45 ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldrexd r0, r1, [r2]"
+        -
+          asm_text: "strexd r3, r4, r5, [r6]"
diff --git a/tests/MC/ARM/thumb2-mclass.s.yaml b/tests/MC/ARM/thumb2-mclass.s.yaml
new file mode 100644
index 000000000..fa7c524bc
--- /dev/null
+++ b/tests/MC/ARM/thumb2-mclass.s.yaml
@@ -0,0 +1,44 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xef, 0xf3, 0x00, 0x80, 0xef, 0xf3, 0x01, 0x80, 0xef, 0xf3, 0x02, 0x80, 0xef, 0xf3, 0x03, 0x80, 0xef, 0xf3, 0x05, 0x80, 0xef, 0xf3, 0x06, 0x80, 0xef, 0xf3, 0x07, 0x80, 0xef, 0xf3, 0x08, 0x80, 0xef, 0xf3, 0x09, 0x80, 0xef, 0xf3, 0x10, 0x80, 0xef, 0xf3, 0x14, 0x80, 0x80, 0xf3, 0x05, 0x88, 0x80, 0xf3, 0x06, 0x88, 0x80, 0xf3, 0x07, 0x88, 0x80, 0xf3, 0x08, 0x88, 0x80, 0xf3, 0x09, 0x88, 0x80, 0xf3, 0x10, 0x88, 0x80, 0xf3, 0x14, 0x88 ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_MCLASS", "CS_MODE_THUMB" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs r0, apsr"
+        -
+          asm_text: "mrs r0, iapsr"
+        -
+          asm_text: "mrs r0, eapsr"
+        -
+          asm_text: "mrs r0, xpsr"
+        -
+          asm_text: "mrs r0, ipsr"
+        -
+          asm_text: "mrs r0, epsr"
+        -
+          asm_text: "mrs r0, iepsr"
+        -
+          asm_text: "mrs r0, msp"
+        -
+          asm_text: "mrs r0, psp"
+        -
+          asm_text: "mrs r0, primask"
+        -
+          asm_text: "mrs r0, control"
+        -
+          asm_text: "msr ipsr, r0"
+        -
+          asm_text: "msr epsr, r0"
+        -
+          asm_text: "msr iepsr, r0"
+        -
+          asm_text: "msr msp, r0"
+        -
+          asm_text: "msr psp, r0"
+        -
+          asm_text: "msr primask, r0"
+        -
+          asm_text: "msr control, r0"
diff --git a/tests/MC/ARM/thumb2-narrow-dp.ll.yaml b/tests/MC/ARM/thumb2-narrow-dp.ll.yaml
new file mode 100644
index 000000000..5cdb15dd0
--- /dev/null
+++ b/tests/MC/ARM/thumb2-narrow-dp.ll.yaml
@@ -0,0 +1,836 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x40, 0x1d, 0x08, 0x31, 0x11, 0xf1, 0x08, 0x01, 0x18, 0xf1, 0x08, 0x08, 0x08, 0xbf, 0x40, 0x1d, 0x08, 0xbf, 0x08, 0x31, 0x08, 0xbf, 0x10, 0xf1, 0x05, 0x00, 0x08, 0xbf, 0x11, 0xf1, 0x08, 0x01, 0x50, 0x18, 0x52, 0x18, 0x0b, 0x44, 0x08, 0xbf, 0x50, 0x18, 0x08, 0xbf, 0x52, 0x18, 0x08, 0xbf, 0x12, 0xeb, 0x01, 0x00, 0x08, 0xbf, 0x12, 0xeb, 0x01, 0x02, 0x0b, 0x44, 0x7c, 0x44, 0x7c, 0x44, 0x97, 0x44, 0x97, 0x44, 0xef, 0x44, 0x05, 0xb0, 0x7f, 0xb0, 0x0d, 0xf5, 0x00, 0x7d, 0xe9, 0x44, 0xd5, 0x44, 0xd5, 0x44, 0xfd, 0x44, 0x12, 0xea, 0x01, 0x00, 0x0a, 0x40, 0x0a, 0x40, 0x10, 0xea, 0x01, 0x00, 0x11, 0xea, 0x03, 0x03, 0x01, 0xea, 0x00, 0x00, 0x0f, 0x40, 0x0f, 0x40, 0x11, 0xea, 0x08, 0x08, 0x18, 0xea, 0x01, 0x08, 0x18, 0xea, 0x00, 0x00, 0x11, 0xea, 0x08, 0x01, 0x12, 0xea, 0x41, 0x02, 0x11, 0xea, 0x50, 0x00, 0x08, 0xbf, 0x02, 0xea, 0x01, 0x00, 0x08, 0xbf, 0x0b, 0x40, 0x08, 0xbf, 0x0b, 0x40, 0x08, 0xbf, 0x00, 0xea, 0x01, 0x00, 0x08, 0xbf, 0x01, 0xea, 0x02, 0x02, 0x08, 0xbf, 0x11, 0xea, 0x00, 0x00, 0x08, 0xbf, 0x0f, 0x40, 0x08, 0xbf, 0x0f, 0x40, 0x08, 0xbf, 0x01, 0xea, 0x08, 0x08, 0x08, 0xbf, 0x08, 0xea, 0x01, 0x08, 0x08, 0xbf, 0x08, 0xea, 0x04, 0x04, 0x08, 0xbf, 0x04, 0xea, 0x08, 0x04, 0x08, 0xbf, 0x00, 0xea, 0x41, 0x00, 0x08, 0xbf, 0x01, 0xea, 0x55, 0x05, 0x92, 0xea, 0x01, 0x00, 0x4d, 0x40, 0x4d, 0x40, 0x90, 0xea, 0x01, 0x00, 0x91, 0xea, 0x02, 0x02, 0x81, 0xea, 0x01, 0x01, 0x4f, 0x40, 0x4f, 0x40, 0x91, 0xea, 0x08, 0x08, 0x98, 0xea, 0x01, 0x08, 0x98, 0xea, 0x06, 0x06, 0x90, 0xea, 0x08, 0x00, 0x92, 0xea, 0x41, 0x02, 0x91, 0xea, 0x50, 0x00, 0x08, 0xbf, 0x82, 0xea, 0x01, 0x03, 0x08, 0xbf, 0x48, 0x40, 0x08, 0xbf, 0x4a, 0x40, 0x08, 0xbf, 0x83, 0xea, 0x01, 0x03, 0x08, 0xbf, 0x81, 0xea, 0x00, 0x00, 0x08, 0xbf, 0x91, 0xea, 0x01, 0x01, 0x08, 0xbf, 0x4f, 0x40, 0x08, 0xbf, 0x4f, 0x40, 0x08, 0xbf, 0x81, 0xea, 0x08, 0x08, 0x08, 0xbf, 0x88, 0xea, 0x01, 0x08, 0x08, 0xbf, 0x88, 0xea, 0x00, 0x00, 0x08, 0xbf, 0x83, 0xea, 0x08, 0x03, 0x08, 0xbf, 0x84, 0xea, 0x41, 0x04, 0x08, 0xbf, 0x81, 0xea, 0x50, 0x00, 0x12, 0xfa, 0x01, 0xf0, 0x8a, 0x40, 0x11, 0xfa, 0x02, 0xf2, 0x10, 0xfa, 0x01, 0xf0, 0x11, 0xfa, 0x04, 0xf4, 0x01, 0xfa, 0x04, 0xf4, 0x8f, 0x40, 0x11, 0xfa, 0x08, 0xf8, 0x18, 0xfa, 0x01, 0xf8, 0x18, 0xfa, 0x03, 0xf3, 0x15, 0xfa, 0x08, 0xf5, 0x08, 0xbf, 0x02, 0xfa, 0x01, 0xf0, 0x08, 0xbf, 0x8a, 0x40, 0x08, 0xbf, 0x01, 0xfa, 0x02, 0xf2, 0x08, 0xbf, 0x00, 0xfa, 0x01, 0xf0, 0x08, 0xbf, 0x01, 0xfa, 0x03, 0xf3, 0x08, 0xbf, 0x11, 0xfa, 0x04, 0xf4, 0x08, 0xbf, 0x8f, 0x40, 0x08, 0xbf, 0x01, 0xfa, 0x08, 0xf8, 0x08, 0xbf, 0x08, 0xfa, 0x01, 0xf8, 0x08, 0xbf, 0x08, 0xfa, 0x00, 0xf0, 0x08, 0xbf, 0x03, 0xfa, 0x08, 0xf3, 0x32, 0xfa, 0x01, 0xf6, 0xca, 0x40, 0x31, 0xfa, 0x02, 0xf2, 0x32, 0xfa, 0x01, 0xf2, 0x31, 0xfa, 0x03, 0xf3, 0x21, 0xfa, 0x04, 0xf4, 0xcf, 0x40, 0x31, 0xfa, 0x08, 0xf8, 0x38, 0xfa, 0x01, 0xf8, 0x38, 0xfa, 0x02, 0xf2, 0x35, 0xfa, 0x08, 0xf5, 0x08, 0xbf, 0x22, 0xfa, 0x01, 0xf6, 0x08, 0xbf, 0xcf, 0x40, 0x08, 0xbf, 0x21, 0xfa, 0x07, 0xf7, 0x08, 0xbf, 0x27, 0xfa, 0x01, 0xf7, 0x08, 0xbf, 0x21, 0xfa, 0x02, 0xf2, 0x08, 0xbf, 0x31, 0xfa, 0x00, 0xf0, 0x08, 0xbf, 0xcf, 0x40, 0x08, 0xbf, 0x21, 0xfa, 0x08, 0xf8, 0x08, 0xbf, 0x28, 0xfa, 0x01, 0xf8, 0x08, 0xbf, 0x28, 0xfa, 0x01, 0xf1, 0x08, 0xbf, 0x24, 0xfa, 0x08, 0xf4, 0x56, 0xfa, 0x05, 0xf7, 0x08, 0x41, 0x51, 0xfa, 0x00, 0xf0, 0x53, 0xfa, 0x01, 0xf3, 0x51, 0xfa, 0x01, 0xf1, 0x41, 0xfa, 0x00, 0xf0, 0x0f, 0x41, 0x51, 0xfa, 0x08, 0xf8, 0x58, 0xfa, 0x01, 0xf8, 0x58, 0xfa, 0x05, 0xf5, 0x55, 0xfa, 0x08, 0xf5, 0x08, 0xbf, 0x42, 0xfa, 0x01, 0xf0, 0x08, 0xbf, 0x0a, 0x41, 0x08, 0xbf, 0x42, 0xfa, 0x01, 0xf1, 0x08, 0xbf, 0x44, 0xfa, 0x01, 0xf4, 0x08, 0xbf, 0x41, 0xfa, 0x06, 0xf6, 0x08, 0xbf, 0x51, 0xfa, 0x03, 0xf3, 0x08, 0xbf, 0x0f, 0x41, 0x08, 0xbf, 0x41, 0xfa, 0x08, 0xf8, 0x08, 0xbf, 0x48, 0xfa, 0x01, 0xf8, 0x08, 0xbf, 0x48, 0xfa, 0x01, 0xf1, 0x08, 0xbf, 0x43, 0xfa, 0x08, 0xf3, 0x52, 0xeb, 0x01, 0x05, 0x4d, 0x41, 0x4b, 0x41, 0x52, 0xeb, 0x01, 0x02, 0x51, 0xeb, 0x03, 0x03, 0x41, 0xeb, 0x00, 0x00, 0x4f, 0x41, 0x4f, 0x41, 0x51, 0xeb, 0x08, 0x08, 0x58, 0xeb, 0x01, 0x08, 0x58, 0xeb, 0x05, 0x05, 0x52, 0xeb, 0x08, 0x02, 0x53, 0xeb, 0x41, 0x03, 0x51, 0xeb, 0x54, 0x04, 0x08, 0xbf, 0x42, 0xeb, 0x03, 0x01, 0x08, 0xbf, 0x49, 0x41, 0x08, 0xbf, 0x4b, 0x41, 0x08, 0xbf, 0x43, 0xeb, 0x01, 0x03, 0x08, 0xbf, 0x41, 0xeb, 0x00, 0x00, 0x08, 0xbf, 0x51, 0xeb, 0x03, 0x03, 0x08, 0xbf, 0x4f, 0x41, 0x08, 0xbf, 0x4f, 0x41, 0x08, 0xbf, 0x41, 0xeb, 0x08, 0x08, 0x08, 0xbf, 0x48, 0xeb, 0x01, 0x08, 0x08, 0xbf, 0x48, 0xeb, 0x03, 0x03, 0x08, 0xbf, 0x41, 0xeb, 0x08, 0x01, 0x08, 0xbf, 0x42, 0xeb, 0x41, 0x02, 0x08, 0xbf, 0x41, 0xeb, 0x51, 0x01, 0x72, 0xeb, 0x01, 0x03, 0x8c, 0x41, 0x74, 0xeb, 0x01, 0x01, 0x74, 0xeb, 0x01, 0x04, 0x71, 0xeb, 0x02, 0x02, 0x61, 0xeb, 0x00, 0x00, 0x8f, 0x41, 0x71, 0xeb, 0x08, 0x08, 0x78, 0xeb, 0x01, 0x08, 0x78, 0xeb, 0x04, 0x04, 0x73, 0xeb, 0x08, 0x03, 0x72, 0xeb, 0x41, 0x02, 0x71, 0xeb, 0x55, 0x05, 0x08, 0xbf, 0x62, 0xeb, 0x01, 0x05, 0x08, 0xbf, 0x8d, 0x41, 0x08, 0xbf, 0x65, 0xeb, 0x01, 0x01, 0x08, 0xbf, 0x65, 0xeb, 0x01, 0x05, 0x08, 0xbf, 0x61, 0xeb, 0x00, 0x00, 0x08, 0xbf, 0x71, 0xeb, 0x02, 0x02, 0x08, 0xbf, 0x8f, 0x41, 0x08, 0xbf, 0x61, 0xeb, 0x08, 0x08, 0x08, 0xbf, 0x68, 0xeb, 0x01, 0x08, 0x08, 0xbf, 0x68, 0xeb, 0x07, 0x07, 0x08, 0xbf, 0x67, 0xeb, 0x08, 0x07, 0x08, 0xbf, 0x62, 0xeb, 0x41, 0x02, 0x08, 0xbf, 0x61, 0xeb, 0x55, 0x05, 0x72, 0xfa, 0x01, 0xf3, 0xc8, 0x41, 0x70, 0xfa, 0x01, 0xf1, 0x72, 0xfa, 0x01, 0xf2, 0x71, 0xfa, 0x02, 0xf2, 0x61, 0xfa, 0x05, 0xf5, 0xcf, 0x41, 0x71, 0xfa, 0x08, 0xf8, 0x78, 0xfa, 0x01, 0xf8, 0x78, 0xfa, 0x06, 0xf6, 0x76, 0xfa, 0x08, 0xf6, 0x08, 0xbf, 0x62, 0xfa, 0x01, 0xf4, 0x08, 0xbf, 0xcc, 0x41, 0x08, 0xbf, 0x64, 0xfa, 0x01, 0xf1, 0x08, 0xbf, 0x64, 0xfa, 0x01, 0xf4, 0x08, 0xbf, 0x61, 0xfa, 0x00, 0xf0, 0x08, 0xbf, 0x71, 0xfa, 0x00, 0xf0, 0x08, 0xbf, 0xcf, 0x41, 0x08, 0xbf, 0x61, 0xfa, 0x08, 0xf8, 0x08, 0xbf, 0x68, 0xfa, 0x01, 0xf8, 0x08, 0xbf, 0x68, 0xfa, 0x03, 0xf3, 0x08, 0xbf, 0x61, 0xfa, 0x08, 0xf1, 0x52, 0xea, 0x01, 0x07, 0x0a, 0x43, 0x0b, 0x43, 0x54, 0xea, 0x01, 0x04, 0x51, 0xea, 0x05, 0x05, 0x41, 0xea, 0x02, 0x02, 0x0f, 0x43, 0x0f, 0x43, 0x51, 0xea, 0x08, 0x08, 0x58, 0xea, 0x01, 0x08, 0x58, 0xea, 0x01, 0x01, 0x50, 0xea, 0x08, 0x00, 0x51, 0xea, 0x41, 0x01, 0x51, 0xea, 0x50, 0x00, 0x08, 0xbf, 0x42, 0xea, 0x01, 0x00, 0x08, 0xbf, 0x0d, 0x43, 0x08, 0xbf, 0x0d, 0x43, 0x08, 0xbf, 0x42, 0xea, 0x01, 0x02, 0x08, 0xbf, 0x41, 0xea, 0x03, 0x03, 0x08, 0xbf, 0x51, 0xea, 0x04, 0x04, 0x08, 0xbf, 0x0f, 0x43, 0x08, 0xbf, 0x0f, 0x43, 0x08, 0xbf, 0x41, 0xea, 0x08, 0x08, 0x08, 0xbf, 0x48, 0xea, 0x01, 0x08, 0x08, 0xbf, 0x48, 0xea, 0x00, 0x00, 0x08, 0xbf, 0x40, 0xea, 0x08, 0x00, 0x08, 0xbf, 0x42, 0xea, 0x41, 0x02, 0x08, 0xbf, 0x41, 0xea, 0x52, 0x02, 0x32, 0xea, 0x01, 0x03, 0x8a, 0x43, 0x32, 0xea, 0x01, 0x01, 0x32, 0xea, 0x01, 0x02, 0x31, 0xea, 0x00, 0x00, 0x21, 0xea, 0x00, 0x00, 0x8f, 0x43, 0x31, 0xea, 0x08, 0x08, 0x38, 0xea, 0x01, 0x08, 0x38, 0xea, 0x07, 0x07, 0x35, 0xea, 0x08, 0x05, 0x33, 0xea, 0x41, 0x03, 0x31, 0xea, 0x54, 0x04, 0x08, 0xbf, 0x22, 0xea, 0x01, 0x00, 0x08, 0xbf, 0x8d, 0x43, 0x08, 0xbf, 0x25, 0xea, 0x01, 0x01, 0x08, 0xbf, 0x24, 0xea, 0x01, 0x04, 0x08, 0xbf, 0x21, 0xea, 0x02, 0x02, 0x08, 0xbf, 0x31, 0xea, 0x05, 0x05, 0x08, 0xbf, 0x8f, 0x43, 0x08, 0xbf, 0x21, 0xea, 0x08, 0x08, 0x08, 0xbf, 0x28, 0xea, 0x01, 0x08, 0x08, 0xbf, 0x28, 0xea, 0x00, 0x00, 0x08, 0xbf, 0x22, 0xea, 0x08, 0x02, 0x08, 0xbf, 0x24, 0xea, 0x41, 0x04, 0x08, 0xbf, 0x21, 0xea, 0x55, 0x05 ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ]
+    expected:
+      insns:
+        -
+          asm_text: "adds r0, r0, #5"
+        -
+          asm_text: "adds r1, #8"
+        -
+          asm_text: "adds.w r1, r1, #8"
+        -
+          asm_text: "adds.w r8, r8, #8"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "addeq r0, r0, #5"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "addeq r1, #8"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "addseq.w r0, r0, #5"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "addseq.w r1, r1, #8"
+        -
+          asm_text: "adds r0, r2, r1"
+        -
+          asm_text: "adds r2, r2, r1"
+        -
+          asm_text: "add r3, r1"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "addeq r0, r2, r1"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "addeq r2, r2, r1"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "addseq.w r0, r2, r1"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "addseq.w r2, r2, r1"
+        -
+          asm_text: "add r3, r1"
+        -
+          asm_text: "add r4, pc"
+        -
+          asm_text: "add r4, pc"
+        -
+          asm_text: "add pc, r2"
+        -
+          asm_text: "add pc, r2"
+        -
+          asm_text: "add pc, sp, pc"
+        -
+          asm_text: "add sp, #0x14"
+        -
+          asm_text: "add sp, #0x1fc"
+        -
+          asm_text: "add.w sp, sp, #0x200"
+        -
+          asm_text: "add r9, sp, r9"
+        -
+          asm_text: "add sp, r10"
+        -
+          asm_text: "add sp, r10"
+        -
+          asm_text: "add sp, pc"
+        -
+          asm_text: "ands.w r0, r2, r1"
+        -
+          asm_text: "ands r2, r1"
+        -
+          asm_text: "ands r2, r1"
+        -
+          asm_text: "ands.w r0, r0, r1"
+        -
+          asm_text: "ands.w r3, r1, r3"
+        -
+          asm_text: "and.w r0, r1, r0"
+        -
+          asm_text: "ands r7, r1"
+        -
+          asm_text: "ands r7, r1"
+        -
+          asm_text: "ands.w r8, r1, r8"
+        -
+          asm_text: "ands.w r8, r8, r1"
+        -
+          asm_text: "ands.w r0, r8, r0"
+        -
+          asm_text: "ands.w r1, r1, r8"
+        -
+          asm_text: "ands.w r2, r2, r1, lsl #1"
+        -
+          asm_text: "ands.w r0, r1, r0, lsr #1"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "andeq.w r0, r2, r1"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "andeq r3, r1"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "andeq r3, r1"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "andeq.w r0, r0, r1"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "andeq.w r2, r1, r2"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "andseq.w r0, r1, r0"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "andeq r7, r1"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "andeq r7, r1"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "andeq.w r8, r1, r8"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "andeq.w r8, r8, r1"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "andeq.w r4, r8, r4"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "andeq.w r4, r4, r8"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "andeq.w r0, r0, r1, lsl #1"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "andeq.w r5, r1, r5, lsr #1"
+        -
+          asm_text: "eors.w r0, r2, r1"
+        -
+          asm_text: "eors r5, r1"
+        -
+          asm_text: "eors r5, r1"
+        -
+          asm_text: "eors.w r0, r0, r1"
+        -
+          asm_text: "eors.w r2, r1, r2"
+        -
+          asm_text: "eor.w r1, r1, r1"
+        -
+          asm_text: "eors r7, r1"
+        -
+          asm_text: "eors r7, r1"
+        -
+          asm_text: "eors.w r8, r1, r8"
+        -
+          asm_text: "eors.w r8, r8, r1"
+        -
+          asm_text: "eors.w r6, r8, r6"
+        -
+          asm_text: "eors.w r0, r0, r8"
+        -
+          asm_text: "eors.w r2, r2, r1, lsl #1"
+        -
+          asm_text: "eors.w r0, r1, r0, lsr #1"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "eoreq.w r3, r2, r1"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "eoreq r0, r1"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "eoreq r2, r1"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "eoreq.w r3, r3, r1"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "eoreq.w r0, r1, r0"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "eorseq.w r1, r1, r1"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "eoreq r7, r1"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "eoreq r7, r1"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "eoreq.w r8, r1, r8"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "eoreq.w r8, r8, r1"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "eoreq.w r0, r8, r0"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "eoreq.w r3, r3, r8"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "eoreq.w r4, r4, r1, lsl #1"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "eoreq.w r0, r1, r0, lsr #1"
+        -
+          asm_text: "lsls.w r0, r2, r1"
+        -
+          asm_text: "lsls r2, r1"
+        -
+          asm_text: "lsls.w r2, r1, r2"
+        -
+          asm_text: "lsls.w r0, r0, r1"
+        -
+          asm_text: "lsls.w r4, r1, r4"
+        -
+          asm_text: "lsl.w r4, r1, r4"
+        -
+          asm_text: "lsls r7, r1"
+        -
+          asm_text: "lsls.w r8, r1, r8"
+        -
+          asm_text: "lsls.w r8, r8, r1"
+        -
+          asm_text: "lsls.w r3, r8, r3"
+        -
+          asm_text: "lsls.w r5, r5, r8"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "lsleq.w r0, r2, r1"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "lsleq r2, r1"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "lsleq.w r2, r1, r2"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "lsleq.w r0, r0, r1"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "lsleq.w r3, r1, r3"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "lslseq.w r4, r1, r4"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "lsleq r7, r1"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "lsleq.w r8, r1, r8"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "lsleq.w r8, r8, r1"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "lsleq.w r0, r8, r0"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "lsleq.w r3, r3, r8"
+        -
+          asm_text: "lsrs.w r6, r2, r1"
+        -
+          asm_text: "lsrs r2, r1"
+        -
+          asm_text: "lsrs.w r2, r1, r2"
+        -
+          asm_text: "lsrs.w r2, r2, r1"
+        -
+          asm_text: "lsrs.w r3, r1, r3"
+        -
+          asm_text: "lsr.w r4, r1, r4"
+        -
+          asm_text: "lsrs r7, r1"
+        -
+          asm_text: "lsrs.w r8, r1, r8"
+        -
+          asm_text: "lsrs.w r8, r8, r1"
+        -
+          asm_text: "lsrs.w r2, r8, r2"
+        -
+          asm_text: "lsrs.w r5, r5, r8"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "lsreq.w r6, r2, r1"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "lsreq r7, r1"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "lsreq.w r7, r1, r7"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "lsreq.w r7, r7, r1"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "lsreq.w r2, r1, r2"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "lsrseq.w r0, r1, r0"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "lsreq r7, r1"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "lsreq.w r8, r1, r8"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "lsreq.w r8, r8, r1"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "lsreq.w r1, r8, r1"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "lsreq.w r4, r4, r8"
+        -
+          asm_text: "asrs.w r7, r6, r5"
+        -
+          asm_text: "asrs r0, r1"
+        -
+          asm_text: "asrs.w r0, r1, r0"
+        -
+          asm_text: "asrs.w r3, r3, r1"
+        -
+          asm_text: "asrs.w r1, r1, r1"
+        -
+          asm_text: "asr.w r0, r1, r0"
+        -
+          asm_text: "asrs r7, r1"
+        -
+          asm_text: "asrs.w r8, r1, r8"
+        -
+          asm_text: "asrs.w r8, r8, r1"
+        -
+          asm_text: "asrs.w r5, r8, r5"
+        -
+          asm_text: "asrs.w r5, r5, r8"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "asreq.w r0, r2, r1"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "asreq r2, r1"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "asreq.w r1, r2, r1"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "asreq.w r4, r4, r1"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "asreq.w r6, r1, r6"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "asrseq.w r3, r1, r3"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "asreq r7, r1"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "asreq.w r8, r1, r8"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "asreq.w r8, r8, r1"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "asreq.w r1, r8, r1"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "asreq.w r3, r3, r8"
+        -
+          asm_text: "adcs.w r5, r2, r1"
+        -
+          asm_text: "adcs r5, r1"
+        -
+          asm_text: "adcs r3, r1"
+        -
+          asm_text: "adcs.w r2, r2, r1"
+        -
+          asm_text: "adcs.w r3, r1, r3"
+        -
+          asm_text: "adc.w r0, r1, r0"
+        -
+          asm_text: "adcs r7, r1"
+        -
+          asm_text: "adcs r7, r1"
+        -
+          asm_text: "adcs.w r8, r1, r8"
+        -
+          asm_text: "adcs.w r8, r8, r1"
+        -
+          asm_text: "adcs.w r5, r8, r5"
+        -
+          asm_text: "adcs.w r2, r2, r8"
+        -
+          asm_text: "adcs.w r3, r3, r1, lsl #1"
+        -
+          asm_text: "adcs.w r4, r1, r4, lsr #1"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "adceq.w r1, r2, r3"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "adceq r1, r1"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "adceq r3, r1"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "adceq.w r3, r3, r1"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "adceq.w r0, r1, r0"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "adcseq.w r3, r1, r3"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "adceq r7, r1"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "adceq r7, r1"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "adceq.w r8, r1, r8"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "adceq.w r8, r8, r1"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "adceq.w r3, r8, r3"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "adceq.w r1, r1, r8"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "adceq.w r2, r2, r1, lsl #1"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "adceq.w r1, r1, r1, lsr #1"
+        -
+          asm_text: "sbcs.w r3, r2, r1"
+        -
+          asm_text: "sbcs r4, r1"
+        -
+          asm_text: "sbcs.w r1, r4, r1"
+        -
+          asm_text: "sbcs.w r4, r4, r1"
+        -
+          asm_text: "sbcs.w r2, r1, r2"
+        -
+          asm_text: "sbc.w r0, r1, r0"
+        -
+          asm_text: "sbcs r7, r1"
+        -
+          asm_text: "sbcs.w r8, r1, r8"
+        -
+          asm_text: "sbcs.w r8, r8, r1"
+        -
+          asm_text: "sbcs.w r4, r8, r4"
+        -
+          asm_text: "sbcs.w r3, r3, r8"
+        -
+          asm_text: "sbcs.w r2, r2, r1, lsl #1"
+        -
+          asm_text: "sbcs.w r5, r1, r5, lsr #1"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "sbceq.w r5, r2, r1"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "sbceq r5, r1"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "sbceq.w r1, r5, r1"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "sbceq.w r5, r5, r1"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "sbceq.w r0, r1, r0"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "sbcseq.w r2, r1, r2"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "sbceq r7, r1"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "sbceq.w r8, r1, r8"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "sbceq.w r8, r8, r1"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "sbceq.w r7, r8, r7"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "sbceq.w r7, r7, r8"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "sbceq.w r2, r2, r1, lsl #1"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "sbceq.w r5, r1, r5, lsr #1"
+        -
+          asm_text: "rors.w r3, r2, r1"
+        -
+          asm_text: "rors r0, r1"
+        -
+          asm_text: "rors.w r1, r0, r1"
+        -
+          asm_text: "rors.w r2, r2, r1"
+        -
+          asm_text: "rors.w r2, r1, r2"
+        -
+          asm_text: "ror.w r5, r1, r5"
+        -
+          asm_text: "rors r7, r1"
+        -
+          asm_text: "rors.w r8, r1, r8"
+        -
+          asm_text: "rors.w r8, r8, r1"
+        -
+          asm_text: "rors.w r6, r8, r6"
+        -
+          asm_text: "rors.w r6, r6, r8"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "roreq.w r4, r2, r1"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "roreq r4, r1"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "roreq.w r1, r4, r1"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "roreq.w r4, r4, r1"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "roreq.w r0, r1, r0"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "rorseq.w r0, r1, r0"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "roreq r7, r1"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "roreq.w r8, r1, r8"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "roreq.w r8, r8, r1"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "roreq.w r3, r8, r3"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "roreq.w r1, r1, r8"
+        -
+          asm_text: "orrs.w r7, r2, r1"
+        -
+          asm_text: "orrs r2, r1"
+        -
+          asm_text: "orrs r3, r1"
+        -
+          asm_text: "orrs.w r4, r4, r1"
+        -
+          asm_text: "orrs.w r5, r1, r5"
+        -
+          asm_text: "orr.w r2, r1, r2"
+        -
+          asm_text: "orrs r7, r1"
+        -
+          asm_text: "orrs r7, r1"
+        -
+          asm_text: "orrs.w r8, r1, r8"
+        -
+          asm_text: "orrs.w r8, r8, r1"
+        -
+          asm_text: "orrs.w r1, r8, r1"
+        -
+          asm_text: "orrs.w r0, r0, r8"
+        -
+          asm_text: "orrs.w r1, r1, r1, lsl #1"
+        -
+          asm_text: "orrs.w r0, r1, r0, lsr #1"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "orreq.w r0, r2, r1"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "orreq r5, r1"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "orreq r5, r1"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "orreq.w r2, r2, r1"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "orreq.w r3, r1, r3"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "orrseq.w r4, r1, r4"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "orreq r7, r1"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "orreq r7, r1"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "orreq.w r8, r1, r8"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "orreq.w r8, r8, r1"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "orreq.w r0, r8, r0"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "orreq.w r0, r0, r8"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "orreq.w r2, r2, r1, lsl #1"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "orreq.w r2, r1, r2, lsr #1"
+        -
+          asm_text: "bics.w r3, r2, r1"
+        -
+          asm_text: "bics r2, r1"
+        -
+          asm_text: "bics.w r1, r2, r1"
+        -
+          asm_text: "bics.w r2, r2, r1"
+        -
+          asm_text: "bics.w r0, r1, r0"
+        -
+          asm_text: "bic.w r0, r1, r0"
+        -
+          asm_text: "bics r7, r1"
+        -
+          asm_text: "bics.w r8, r1, r8"
+        -
+          asm_text: "bics.w r8, r8, r1"
+        -
+          asm_text: "bics.w r7, r8, r7"
+        -
+          asm_text: "bics.w r5, r5, r8"
+        -
+          asm_text: "bics.w r3, r3, r1, lsl #1"
+        -
+          asm_text: "bics.w r4, r1, r4, lsr #1"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "biceq.w r0, r2, r1"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "biceq r5, r1"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "biceq.w r1, r5, r1"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "biceq.w r4, r4, r1"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "biceq.w r2, r1, r2"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "bicseq.w r5, r1, r5"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "biceq r7, r1"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "biceq.w r8, r1, r8"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "biceq.w r8, r8, r1"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "biceq.w r0, r8, r0"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "biceq.w r2, r2, r8"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "biceq.w r4, r4, r1, lsl #1"
+        -
+          asm_text: "it eq"
+        -
+          asm_text: "biceq.w r5, r1, r5, lsr #1"
diff --git a/tests/MC/ARM/thumb2-pldw.s.yaml b/tests/MC/ARM/thumb2-pldw.s.yaml
new file mode 100644
index 000000000..5604eb4d6
--- /dev/null
+++ b/tests/MC/ARM/thumb2-pldw.s.yaml
@@ -0,0 +1,10 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xb0, 0xf8, 0x01, 0xf1 ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ]
+    expected:
+      insns:
+        -
+          asm_text: "pldw [r0, #0x101]"
diff --git a/tests/MC/ARM/thumb_rewrites.s.yaml b/tests/MC/ARM/thumb_rewrites.s.yaml
new file mode 100644
index 000000000..7b2702006
--- /dev/null
+++ b/tests/MC/ARM/thumb_rewrites.s.yaml
@@ -0,0 +1,70 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xc9, 0x1c, 0x03, 0x31, 0x08, 0x30, 0x00, 0x18, 0x40, 0x44, 0x41, 0x44, 0x85, 0x44, 0x6c, 0x44, 0x08, 0xb0, 0xfe, 0xad, 0x08, 0x44, 0x1a, 0x44, 0x00, 0x1a, 0x5b, 0x1f, 0x05, 0x3b, 0x08, 0x3a, 0x84, 0xb0, 0x08, 0x40, 0x08, 0x40, 0x48, 0x40, 0x48, 0x40, 0x88, 0x40, 0xc8, 0x40, 0x08, 0x41, 0x48, 0x41, 0x48, 0x41, 0x88, 0x41, 0xc8, 0x41, 0x08, 0x43, 0x08, 0x43, 0x88, 0x43 ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ]
+    expected:
+      insns:
+        -
+          asm_text: "adds r1, r1, #3"
+        -
+          asm_text: "adds r1, #3"
+        -
+          asm_text: "adds r0, #8"
+        -
+          asm_text: "adds r0, r0, r0"
+        -
+          asm_text: "add r0, r8"
+        -
+          asm_text: "add r1, r8"
+        -
+          asm_text: "add sp, r0"
+        -
+          asm_text: "add r4, sp, r4"
+        -
+          asm_text: "add sp, #0x20"
+        -
+          asm_text: "add r5, sp, #0x3f8"
+        -
+          asm_text: "add r0, r1"
+        -
+          asm_text: "add r2, r3"
+        -
+          asm_text: "subs r0, r0, r0"
+        -
+          asm_text: "subs r3, r3, #5"
+        -
+          asm_text: "subs r3, #5"
+        -
+          asm_text: "subs r2, #8"
+        -
+          asm_text: "sub sp, #0x10"
+        -
+          asm_text: "ands r0, r1"
+        -
+          asm_text: "ands r0, r1"
+        -
+          asm_text: "eors r0, r1"
+        -
+          asm_text: "eors r0, r1"
+        -
+          asm_text: "lsls r0, r1"
+        -
+          asm_text: "lsrs r0, r1"
+        -
+          asm_text: "asrs r0, r1"
+        -
+          asm_text: "adcs r0, r1"
+        -
+          asm_text: "adcs r0, r1"
+        -
+          asm_text: "sbcs r0, r1"
+        -
+          asm_text: "rors r0, r1"
+        -
+          asm_text: "orrs r0, r1"
+        -
+          asm_text: "orrs r0, r1"
+        -
+          asm_text: "bics r0, r1"
diff --git a/tests/MC/ARM/thumbv7em.s.yaml b/tests/MC/ARM/thumbv7em.s.yaml
new file mode 100644
index 000000000..e35517f4e
--- /dev/null
+++ b/tests/MC/ARM/thumbv7em.s.yaml
@@ -0,0 +1,24 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x80, 0xf3, 0x00, 0x84, 0x80, 0xf3, 0x00, 0x8c, 0x80, 0xf3, 0x01, 0x84, 0x80, 0xf3, 0x01, 0x8c, 0x80, 0xf3, 0x02, 0x84, 0x80, 0xf3, 0x02, 0x8c, 0x80, 0xf3, 0x03, 0x84, 0x80, 0xf3, 0x03, 0x8c ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_MCLASS", "CS_MODE_THUMB" ]
+    expected:
+      insns:
+        -
+          asm_text: "msr apsr_g, r0"
+        -
+          asm_text: "msr apsr_nzcvqg, r0"
+        -
+          asm_text: "msr iapsr_g, r0"
+        -
+          asm_text: "msr iapsr_nzcvqg, r0"
+        -
+          asm_text: "msr eapsr_g, r0"
+        -
+          asm_text: "msr eapsr_nzcvqg, r0"
+        -
+          asm_text: "msr xpsr_g, r0"
+        -
+          asm_text: "msr xpsr_nzcvqg, r0"
diff --git a/tests/MC/ARM/thumbv7m.s.yaml b/tests/MC/ARM/thumbv7m.s.yaml
new file mode 100644
index 000000000..c31e3d239
--- /dev/null
+++ b/tests/MC/ARM/thumbv7m.s.yaml
@@ -0,0 +1,20 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xef, 0xf3, 0x11, 0x80, 0xef, 0xf3, 0x12, 0x80, 0xef, 0xf3, 0x13, 0x80, 0x80, 0xf3, 0x11, 0x88, 0x80, 0xf3, 0x12, 0x88, 0x80, 0xf3, 0x13, 0x88 ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_MCLASS", "CS_MODE_THUMB" ]
+    expected:
+      insns:
+        -
+          asm_text: "mrs r0, basepri"
+        -
+          asm_text: "mrs r0, basepri_max"
+        -
+          asm_text: "mrs r0, faultmask"
+        -
+          asm_text: "msr basepri, r0"
+        -
+          asm_text: "msr basepri_max, r0"
+        -
+          asm_text: "msr faultmask, r0"
diff --git a/tests/MC/ARM/thumbv8.1m-vmrs-vmsr.s.yaml b/tests/MC/ARM/thumbv8.1m-vmrs-vmsr.s.yaml
new file mode 100644
index 000000000..bc3bb690a
--- /dev/null
+++ b/tests/MC/ARM/thumbv8.1m-vmrs-vmsr.s.yaml
@@ -0,0 +1,30 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xe2, 0xee, 0x10, 0x0a, 0xf2, 0xee, 0x10, 0xaa, 0xfe, 0xee, 0x10, 0x0a, 0xee, 0xee, 0x10, 0xaa, 0xef, 0xee, 0x10, 0x5a, 0xfe, 0xee, 0x10, 0x3a, 0xff, 0xee, 0x10, 0x0a, 0xfc, 0xee, 0x10, 0x0a, 0xfd, 0xee, 0x10, 0x4a, 0xec, 0xee, 0x10, 0x0a, 0xed, 0xee, 0x10, 0x4a ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_MCLASS", "CS_MODE_V8", "CS_MODE_THUMB" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmsr fpscr_nzcvqc, r0"
+        -
+          asm_text: "vmrs r10, fpscr_nzcvqc"
+        -
+          asm_text: "vmrs r0, fpcxtns"
+        -
+          asm_text: "vmsr fpcxtns, r10"
+        -
+          asm_text: "vmsr fpcxts, r5"
+        -
+          asm_text: "vmrs r3, fpcxtns"
+        -
+          asm_text: "vmrs r0, fpcxts"
+        -
+          asm_text: "vmrs r0, vpr"
+        -
+          asm_text: "vmrs r4, p0"
+        -
+          asm_text: "vmsr vpr, r0"
+        -
+          asm_text: "vmsr p0, r4"
diff --git a/tests/MC/ARM/thumbv8.1m.s.yaml b/tests/MC/ARM/thumbv8.1m.s.yaml
new file mode 100644
index 000000000..d3f18fe07
--- /dev/null
+++ b/tests/MC/ARM/thumbv8.1m.s.yaml
@@ -0,0 +1,338 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x42, 0xf0, 0x01, 0xe0, 0x4e, 0xf0, 0x01, 0xe0, 0x40, 0xf0, 0x01, 0xe0, 0x41, 0xf0, 0x01, 0xe0, 0x4a, 0xf0, 0x01, 0xe0, 0x4b, 0xf0, 0x01, 0xe0, 0x4c, 0xf0, 0x01, 0xe0, 0x42, 0xf0, 0x01, 0xe0, 0x43, 0xf0, 0x01, 0xe0, 0x45, 0xf0, 0x01, 0xe0, 0x46, 0xf0, 0x01, 0xe0, 0x47, 0xf0, 0x01, 0xe0, 0x48, 0xf0, 0x01, 0xe0, 0x49, 0xf0, 0x01, 0xe0, 0x2f, 0xf0, 0x35, 0xc8, 0x2f, 0xf0, 0x4b, 0xc2, 0x2f, 0xf0, 0x5d, 0xca, 0x2f, 0xf0, 0x77, 0xc2, 0x2f, 0xf0, 0x77, 0xca, 0x2f, 0xf0, 0x83, 0xc2, 0x2f, 0xf0, 0x83, 0xca, 0x2f, 0xf0, 0x0b, 0xc3, 0x2f, 0xf0, 0x59, 0xc8, 0x2f, 0xf0, 0xad, 0xcb, 0x2f, 0xf0, 0xb7, 0xc3, 0x2f, 0xf0, 0xbb, 0xcb, 0x2f, 0xf0, 0x0f, 0xc4, 0x2f, 0xf0, 0x6d, 0xcc, 0x2f, 0xf0, 0x8b, 0xc4, 0x2f, 0xf0, 0x8d, 0xc4, 0x2f, 0xf0, 0xcd, 0xc4, 0x2f, 0xf0, 0x7b, 0xc8, 0x2f, 0xf0, 0xd7, 0xc4, 0x2f, 0xf0, 0x09, 0xcd, 0x2f, 0xf0, 0x83, 0xc8, 0x2f, 0xf0, 0x33, 0xc5, 0x2f, 0xf0, 0x51, 0xcd, 0x2f, 0xf0, 0x9b, 0xc5, 0x2f, 0xf0, 0xa1, 0xcd, 0x2f, 0xf0, 0x29, 0xce, 0x2f, 0xf0, 0x65, 0xce, 0x2f, 0xf0, 0x8d, 0xc6, 0x2f, 0xf0, 0xa9, 0xc8, 0x2f, 0xf0, 0xc1, 0xce, 0x2f, 0xf0, 0xcd, 0xc6, 0x2f, 0xf0, 0xeb, 0xce, 0x2f, 0xf0, 0x1f, 0xc7, 0x2f, 0xf0, 0x2f, 0xc7, 0x2f, 0xf0, 0x37, 0xc7, 0x2f, 0xf0, 0x8b, 0xc7, 0x2f, 0xf0, 0xc9, 0xcf, 0x2f, 0xf0, 0xd3, 0xcf, 0x2f, 0xf0, 0xe1, 0xcf, 0x2f, 0xf0, 0xef, 0xc7, 0x2f, 0xf0, 0xf3, 0xc7, 0x2f, 0xf0, 0xef, 0xc8, 0x2f, 0xf0, 0x11, 0xc1, 0x2f, 0xf0, 0x25, 0xc9, 0x2f, 0xf0, 0x2f, 0xc9, 0x2f, 0xf0, 0x49, 0xc1, 0x2f, 0xf0, 0x73, 0xc1, 0x2f, 0xf0, 0x7d, 0xc9, 0x2f, 0xf0, 0xaf, 0xc9, 0x2f, 0xf0, 0xb3, 0xc9, 0x0f, 0xf0, 0x1d, 0xc2, 0x0f, 0xf0, 0x29, 0xc2, 0x0f, 0xf0, 0x41, 0xc2, 0x0f, 0xf0, 0xdb, 0xca, 0x0f, 0xf0, 0xdf, 0xca, 0x0f, 0xf0, 0x27, 0xc3, 0x0f, 0xf0, 0x31, 0xc3, 0x0f, 0xf0, 0x4f, 0xcb, 0x0f, 0xf0, 0x59, 0xcb, 0x0f, 0xf0, 0x9d, 0xcb, 0x0f, 0xf0, 0xab, 0xcb, 0x0f, 0xf0, 0xb5, 0xc3, 0x0f, 0xf0, 0xc1, 0xcb, 0x0f, 0xf0, 0xc3, 0xcb, 0x0f, 0xf0, 0x01, 0xc8, 0x0f, 0xf0, 0x1d, 0xc4, 0x0f, 0xf0, 0x23, 0xc4, 0x0f, 0xf0, 0x31, 0xc4, 0x0f, 0xf0, 0x47, 0xc4, 0x0f, 0xf0, 0x95, 0xc4, 0x0f, 0xf0, 0xcd, 0xc4, 0x0f, 0xf0, 0x19, 0xc5, 0x0f, 0xf0, 0x1d, 0xc5, 0x0f, 0xf0, 0x1f, 0xcd, 0x0f, 0xf0, 0x3d, 0xc5, 0x0f, 0xf0, 0x43, 0xcd, 0x0f, 0xf0, 0x91, 0xcd, 0x0f, 0xf0, 0x97, 0xc5, 0x0f, 0xf0, 0xdf, 0xc5, 0x0f, 0xf0, 0xe5, 0xcd, 0x0f, 0xf0, 0x99, 0xc0, 0x0f, 0xf0, 0x0d, 0xce, 0x0f, 0xf0, 0x4f, 0xc6, 0x0f, 0xf0, 0x7b, 0xc6, 0x0f, 0xf0, 0x83, 0xc6, 0x0f, 0xf0, 0x8d, 0xce, 0x0f, 0xf0, 0xbd, 0xcf, 0x0f, 0xf0, 0xe5, 0xcf, 0x0f, 0xf0, 0xeb, 0xc7, 0x0f, 0xf0, 0xe5, 0xc8, 0x0f, 0xf0, 0x1d, 0xc0, 0x0f, 0xf0, 0x23, 0xc9, 0x0f, 0xf0, 0x53, 0xc1, 0x0f, 0xf0, 0x79, 0xc1, 0x0f, 0xf0, 0x27, 0xc0, 0x0f, 0xf0, 0x91, 0xc9, 0x0f, 0xf0, 0xaf, 0xc9, 0x0f, 0xf0, 0xc3, 0xc9, 0x0f, 0xf0, 0xe5, 0xc1, 0x4e, 0xf0, 0x55, 0xc2, 0x4e, 0xf0, 0x2b, 0xcc, 0x4e, 0xf0, 0xe1, 0xc9, 0x40, 0xf0, 0x43, 0xc3, 0x40, 0xf0, 0x49, 0xcd, 0x40, 0xf0, 0xe9, 0xcd, 0x40, 0xf0, 0xb7, 0xc6, 0x41, 0xf0, 0x13, 0xc2, 0x41, 0xf0, 0xe3, 0xc7, 0x41, 0xf0, 0x0d, 0xc9, 0x4a, 0xf0, 0xbf, 0xc2, 0x4a, 0xf0, 0xc1, 0xc2, 0x4a, 0xf0, 0x9b, 0xcc, 0x4a, 0xf0, 0xfb, 0xcf, 0x4b, 0xf0, 0xd1, 0xca, 0x4b, 0xf0, 0x3b, 0xcd, 0x4b, 0xf0, 0x0d, 0xcf, 0x4c, 0xf0, 0x67, 0xc8, 0x4c, 0xf0, 0xa9, 0xc5, 0x4c, 0xf0, 0x5d, 0xce, 0x42, 0xf0, 0x55, 0xce, 0x42, 0xf0, 0x7d, 0xc7, 0x42, 0xf0, 0xb5, 0xc1, 0x43, 0xf0, 0xdd, 0xce, 0x43, 0xf0, 0x1b, 0xc7, 0x43, 0xf0, 0xb3, 0xcf, 0x43, 0xf0, 0x65, 0xc1, 0x44, 0xf0, 0x31, 0xcc, 0x44, 0xf0, 0xdb, 0xcc, 0x45, 0xf0, 0xb9, 0xcb, 0x45, 0xf0, 0xa3, 0xc6, 0x46, 0xf0, 0x7f, 0xce, 0x46, 0xf0, 0xd1, 0xc0, 0x46, 0xf0, 0xd3, 0xc8, 0x47, 0xf0, 0xc9, 0xce, 0x47, 0xf0, 0x1d, 0xc7, 0x48, 0xf0, 0x47, 0xc5, 0x49, 0xf0, 0x2d, 0xca, 0x49, 0xf0, 0xe1, 0xc3, 0x49, 0xf0, 0x57, 0xcf, 0x49, 0xf0, 0x6b, 0xc7, 0x52, 0xea, 0x22, 0x9e, 0x57, 0xea, 0x47, 0x9e, 0x5c, 0xea, 0x3c, 0xae, 0x5a, 0xea, 0x3a, 0xbe, 0x59, 0xea, 0x7b, 0x89, 0x5f, 0xea, 0x1f, 0x9e, 0x5f, 0xea, 0x3f, 0xae, 0x5a, 0xea, 0xd7, 0x9e, 0x55, 0xea, 0x2f, 0xae, 0x52, 0xea, 0x42, 0xae, 0x50, 0xea, 0x01, 0x80 ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_V8", "CS_MODE_THUMB" ]
+    expected:
+      insns:
+        -
+          asm_text: "dls lr, r2"
+        -
+          asm_text: "dls lr, lr"
+        -
+          asm_text: "dls lr, r0"
+        -
+          asm_text: "dls lr, r1"
+        -
+          asm_text: "dls lr, r10"
+        -
+          asm_text: "dls lr, r11"
+        -
+          asm_text: "dls lr, r12"
+        -
+          asm_text: "dls lr, r2"
+        -
+          asm_text: "dls lr, r3"
+        -
+          asm_text: "dls lr, r5"
+        -
+          asm_text: "dls lr, r6"
+        -
+          asm_text: "dls lr, r7"
+        -
+          asm_text: "dls lr, r8"
+        -
+          asm_text: "dls lr, r9"
+        -
+          asm_text: "le #-0x6a"
+        -
+          asm_text: "le #-0x494"
+        -
+          asm_text: "le #-0x4ba"
+        -
+          asm_text: "le #-0x4ec"
+        -
+          asm_text: "le #-0x4ee"
+        -
+          asm_text: "le #-0x504"
+        -
+          asm_text: "le #-0x506"
+        -
+          asm_text: "le #-0x614"
+        -
+          asm_text: "le #-0xb2"
+        -
+          asm_text: "le #-0x75a"
+        -
+          asm_text: "le #-0x76c"
+        -
+          asm_text: "le #-0x776"
+        -
+          asm_text: "le #-0x81c"
+        -
+          asm_text: "le #-0x8da"
+        -
+          asm_text: "le #-0x914"
+        -
+          asm_text: "le #-0x918"
+        -
+          asm_text: "le #-0x998"
+        -
+          asm_text: "le #-0xf6"
+        -
+          asm_text: "le #-0x9ac"
+        -
+          asm_text: "le #-0xa12"
+        -
+          asm_text: "le #-0x106"
+        -
+          asm_text: "le #-0xa64"
+        -
+          asm_text: "le #-0xaa2"
+        -
+          asm_text: "le #-0xb34"
+        -
+          asm_text: "le #-0xb42"
+        -
+          asm_text: "le #-0xc52"
+        -
+          asm_text: "le #-0xcca"
+        -
+          asm_text: "le #-0xd18"
+        -
+          asm_text: "le #-0x152"
+        -
+          asm_text: "le #-0xd82"
+        -
+          asm_text: "le #-0xd98"
+        -
+          asm_text: "le #-0xdd6"
+        -
+          asm_text: "le #-0xe3c"
+        -
+          asm_text: "le #-0xe5c"
+        -
+          asm_text: "le #-0xe6c"
+        -
+          asm_text: "le #-0xf14"
+        -
+          asm_text: "le #-0xf92"
+        -
+          asm_text: "le #-0xfa6"
+        -
+          asm_text: "le #-0xfc2"
+        -
+          asm_text: "le #-0xfdc"
+        -
+          asm_text: "le #-0xfe4"
+        -
+          asm_text: "le #-0x1de"
+        -
+          asm_text: "le #-0x220"
+        -
+          asm_text: "le #-0x24a"
+        -
+          asm_text: "le #-0x25e"
+        -
+          asm_text: "le #-0x290"
+        -
+          asm_text: "le #-0x2e4"
+        -
+          asm_text: "le #-0x2fa"
+        -
+          asm_text: "le #-0x35e"
+        -
+          asm_text: "le #-0x366"
+        -
+          asm_text: "le lr, #-0x438"
+        -
+          asm_text: "le lr, #-0x450"
+        -
+          asm_text: "le lr, #-0x480"
+        -
+          asm_text: "le lr, #-0x5b6"
+        -
+          asm_text: "le lr, #-0x5be"
+        -
+          asm_text: "le lr, #-0x64c"
+        -
+          asm_text: "le lr, #-0x660"
+        -
+          asm_text: "le lr, #-0x69e"
+        -
+          asm_text: "le lr, #-0x6b2"
+        -
+          asm_text: "le lr, #-0x73a"
+        -
+          asm_text: "le lr, #-0x756"
+        -
+          asm_text: "le lr, #-0x768"
+        -
+          asm_text: "le lr, #-0x782"
+        -
+          asm_text: "le lr, #-0x786"
+        -
+          asm_text: "le lr, #-2"
+        -
+          asm_text: "le lr, #-0x838"
+        -
+          asm_text: "le lr, #-0x844"
+        -
+          asm_text: "le lr, #-0x860"
+        -
+          asm_text: "le lr, #-0x88c"
+        -
+          asm_text: "le lr, #-0x928"
+        -
+          asm_text: "le lr, #-0x998"
+        -
+          asm_text: "le lr, #-0xa30"
+        -
+          asm_text: "le lr, #-0xa38"
+        -
+          asm_text: "le lr, #-0xa3e"
+        -
+          asm_text: "le lr, #-0xa78"
+        -
+          asm_text: "le lr, #-0xa86"
+        -
+          asm_text: "le lr, #-0xb22"
+        -
+          asm_text: "le lr, #-0xb2c"
+        -
+          asm_text: "le lr, #-0xbbc"
+        -
+          asm_text: "le lr, #-0xbca"
+        -
+          asm_text: "le lr, #-0x130"
+        -
+          asm_text: "le lr, #-0xc1a"
+        -
+          asm_text: "le lr, #-0xc9c"
+        -
+          asm_text: "le lr, #-0xcf4"
+        -
+          asm_text: "le lr, #-0xd04"
+        -
+          asm_text: "le lr, #-0xd1a"
+        -
+          asm_text: "le lr, #-0xf7a"
+        -
+          asm_text: "le lr, #-0xfca"
+        -
+          asm_text: "le lr, #-0xfd4"
+        -
+          asm_text: "le lr, #-0x1ca"
+        -
+          asm_text: "le lr, #-0x38"
+        -
+          asm_text: "le lr, #-0x246"
+        -
+          asm_text: "le lr, #-0x2a4"
+        -
+          asm_text: "le lr, #-0x2f0"
+        -
+          asm_text: "le lr, #-0x4c"
+        -
+          asm_text: "le lr, #-0x322"
+        -
+          asm_text: "le lr, #-0x35e"
+        -
+          asm_text: "le lr, #-0x386"
+        -
+          asm_text: "le lr, #-0x3c8"
+        -
+          asm_text: "wls lr, lr, #0x4a8"
+        -
+          asm_text: "wls lr, lr, #0x856"
+        -
+          asm_text: "wls lr, lr, #0x3c2"
+        -
+          asm_text: "wls lr, r0, #0x684"
+        -
+          asm_text: "wls lr, r0, #0xa92"
+        -
+          asm_text: "wls lr, r0, #0xbd2"
+        -
+          asm_text: "wls lr, r0, #0xd6c"
+        -
+          asm_text: "wls lr, r1, #0x424"
+        -
+          asm_text: "wls lr, r1, #0xfc4"
+        -
+          asm_text: "wls lr, r1, #0x21a"
+        -
+          asm_text: "wls lr, r10, #0x57c"
+        -
+          asm_text: "wls lr, r10, #0x580"
+        -
+          asm_text: "wls lr, r10, #0x936"
+        -
+          asm_text: "wls lr, r10, #0xff6"
+        -
+          asm_text: "wls lr, r11, #0x5a2"
+        -
+          asm_text: "wls lr, r11, #0xa76"
+        -
+          asm_text: "wls lr, r11, #0xe1a"
+        -
+          asm_text: "wls lr, r12, #0xce"
+        -
+          asm_text: "wls lr, r12, #0xb50"
+        -
+          asm_text: "wls lr, r12, #0xcba"
+        -
+          asm_text: "wls lr, r2, #0xcaa"
+        -
+          asm_text: "wls lr, r2, #0xef8"
+        -
+          asm_text: "wls lr, r2, #0x368"
+        -
+          asm_text: "wls lr, r3, #0xdba"
+        -
+          asm_text: "wls lr, r3, #0xe34"
+        -
+          asm_text: "wls lr, r3, #0xf66"
+        -
+          asm_text: "wls lr, r3, #0x2c8"
+        -
+          asm_text: "wls lr, r4, #0x862"
+        -
+          asm_text: "wls lr, r4, #0x9b6"
+        -
+          asm_text: "wls lr, r5, #0x772"
+        -
+          asm_text: "wls lr, r5, #0xd44"
+        -
+          asm_text: "wls lr, r6, #0xcfe"
+        -
+          asm_text: "wls lr, r6, #0x1a0"
+        -
+          asm_text: "wls lr, r6, #0x1a6"
+        -
+          asm_text: "wls lr, r7, #0xd92"
+        -
+          asm_text: "wls lr, r7, #0xe38"
+        -
+          asm_text: "wls lr, r8, #0xa8c"
+        -
+          asm_text: "wls lr, r9, #0x45a"
+        -
+          asm_text: "wls lr, r9, #0x7c0"
+        -
+          asm_text: "wls lr, r9, #0xeae"
+        -
+          asm_text: "wls lr, r9, #0xed4"
+        -
+          asm_text: "cinc lr, r2, lo"
+        -
+          asm_text: "cinc lr, r7, pl"
+        -
+          asm_text: "cinv lr, r12, hs"
+        -
+          asm_text: "cneg lr, r10, hs"
+        -
+          asm_text: "csel r9, r9, r11, vc"
+        -
+          asm_text: "cset lr, eq"
+        -
+          asm_text: "csetm lr, hs"
+        -
+          asm_text: "csinc lr, r10, r7, le"
+        -
+          asm_text: "csinv lr, r5, zr, hs"
+        -
+          asm_text: "cinv lr, r2, pl"
+        -
+          asm_text: "csel r0, r0, r1, eq"
diff --git a/tests/MC/ARM/thumbv8m.s.yaml b/tests/MC/ARM/thumbv8m.s.yaml
new file mode 100644
index 000000000..bbec48ec2
--- /dev/null
+++ b/tests/MC/ARM/thumbv8m.s.yaml
@@ -0,0 +1,100 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xbf, 0xf3, 0x6f, 0x8f, 0x92, 0xfb, 0xf3, 0xf1, 0xb2, 0xfb, 0xf3, 0xf1, 0xbf, 0xf3, 0x2f, 0x8f, 0x52, 0xe8, 0x01, 0x1f, 0xd2, 0xe8, 0x4f, 0x1f, 0xd2, 0xe8, 0x5f, 0x1f, 0x43, 0xe8, 0x01, 0x21, 0xc3, 0xe8, 0x41, 0x2f, 0xc3, 0xe8, 0x51, 0x2f, 0x4f, 0xf6, 0xff, 0x71, 0xcf, 0xf6, 0xff, 0x71, 0xd2, 0xe8, 0xaf, 0x1f, 0xd2, 0xe8, 0x8f, 0x1f, 0xd2, 0xe8, 0x9f, 0x1f, 0xc3, 0xe8, 0xaf, 0x1f, 0xc3, 0xe8, 0x8f, 0x1f, 0xc3, 0xe8, 0x9f, 0x1f, 0xd2, 0xe8, 0xef, 0x1f, 0xd2, 0xe8, 0xcf, 0x1f, 0xd2, 0xe8, 0xdf, 0x1f, 0xc3, 0xe8, 0xe1, 0x2f, 0xc3, 0xe8, 0xc1, 0x2f, 0xc3, 0xe8, 0xd1, 0x2f, 0x7f, 0xe9, 0x7f, 0xe9, 0x04, 0x47, 0x74, 0x47, 0x84, 0x47, 0x41, 0xe8, 0x00, 0xf0, 0x4d, 0xe8, 0x00, 0xf0, 0x41, 0xe8, 0x80, 0xf0, 0x41, 0xe8, 0x40, 0xf0, 0x41, 0xe8, 0xc0, 0xf0, 0xef, 0xf3, 0x88, 0x81, 0x82, 0xf3, 0x89, 0x88, 0xef, 0xf3, 0x90, 0x83, 0x84, 0xf3, 0x94, 0x88, 0xef, 0xf3, 0x98, 0x85, 0xef, 0xf3, 0x0a, 0x86, 0xef, 0xf3, 0x0b, 0x87, 0x88, 0xf3, 0x0a, 0x88, 0x89, 0xf3, 0x0b, 0x88, 0xef, 0xf3, 0x8a, 0x8a, 0x8b, 0xf3, 0x8b, 0x88, 0xef, 0xf3, 0x92, 0x88, 0x88, 0xf3, 0x92, 0x80 ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_MCLASS", "CS_MODE_V8", "CS_MODE_THUMB" ]
+    expected:
+      insns:
+        -
+          asm_text: "isb sy"
+        -
+          asm_text: "sdiv r1, r2, r3"
+        -
+          asm_text: "udiv r1, r2, r3"
+        -
+          asm_text: "clrex"
+        -
+          asm_text: "ldrex r1, [r2, #4]"
+        -
+          asm_text: "ldrexb r1, [r2]"
+        -
+          asm_text: "ldrexh r1, [r2]"
+        -
+          asm_text: "strex r1, r2, [r3, #4]"
+        -
+          asm_text: "strexb r1, r2, [r3]"
+        -
+          asm_text: "strexh r1, r2, [r3]"
+        -
+          asm_text: "movw r1, #0xffff"
+        -
+          asm_text: "movt r1, #0xffff"
+        -
+          asm_text: "lda r1, [r2]"
+        -
+          asm_text: "ldab r1, [r2]"
+        -
+          asm_text: "ldah r1, [r2]"
+        -
+          asm_text: "stl r1, [r3]"
+        -
+          asm_text: "stlb r1, [r3]"
+        -
+          asm_text: "stlh r1, [r3]"
+        -
+          asm_text: "ldaex r1, [r2]"
+        -
+          asm_text: "ldaexb r1, [r2]"
+        -
+          asm_text: "ldaexh r1, [r2]"
+        -
+          asm_text: "stlex r1, r2, [r3]"
+        -
+          asm_text: "stlexb r1, r2, [r3]"
+        -
+          asm_text: "stlexh r1, r2, [r3]"
+        -
+          asm_text: "sg"
+        -
+          asm_text: "bxns r0"
+        -
+          asm_text: "bxns lr"
+        -
+          asm_text: "blxns r0"
+        -
+          asm_text: "tt r0, r1"
+        -
+          asm_text: "tt r0, sp"
+        -
+          asm_text: "tta r0, r1"
+        -
+          asm_text: "ttt r0, r1"
+        -
+          asm_text: "ttat r0, r1"
+        -
+          asm_text: "mrs r1, msp_ns"
+        -
+          asm_text: "msr psp_ns, r2"
+        -
+          asm_text: "mrs r3, primask_ns"
+        -
+          asm_text: "msr control_ns, r4"
+        -
+          asm_text: "mrs r5, sp_ns"
+        -
+          asm_text: "mrs r6, msplim"
+        -
+          asm_text: "mrs r7, psplim"
+        -
+          asm_text: "msr msplim, r8"
+        -
+          asm_text: "msr psplim, r9"
+        -
+          asm_text: "mrs r10, msplim_ns"
+        -
+          asm_text: "msr psplim_ns, r11"
+        -
+          asm_text: "mrs r8, 0x92"
+        -
+          asm_text: "msr 0x92, r8"
diff --git a/tests/MC/ARM/udf-arm.s.yaml b/tests/MC/ARM/udf-arm.s.yaml
new file mode 100644
index 000000000..2a4769d35
--- /dev/null
+++ b/tests/MC/ARM/udf-arm.s.yaml
@@ -0,0 +1,10 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xf0, 0x00, 0xf0, 0xe7 ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ]
+    expected:
+      insns:
+        -
+          asm_text: "udf #0"
diff --git a/tests/MC/ARM/udf-thumb-2.s.yaml b/tests/MC/ARM/udf-thumb-2.s.yaml
new file mode 100644
index 000000000..1ca8f42dd
--- /dev/null
+++ b/tests/MC/ARM/udf-thumb-2.s.yaml
@@ -0,0 +1,12 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xde, 0xf0, 0xf7, 0x00, 0xa0 ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ]
+    expected:
+      insns:
+        -
+          asm_text: "udf #0"
+        -
+          asm_text: "udf.w #0"
diff --git a/tests/MC/ARM/udf-thumb.s.yaml b/tests/MC/ARM/udf-thumb.s.yaml
new file mode 100644
index 000000000..49b994366
--- /dev/null
+++ b/tests/MC/ARM/udf-thumb.s.yaml
@@ -0,0 +1,10 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xde ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ]
+    expected:
+      insns:
+        -
+          asm_text: "udf #0"
diff --git a/tests/MC/ARM/vfp4-thumb.s.yaml b/tests/MC/ARM/vfp4-thumb.s.yaml
new file mode 100644
index 000000000..498c32b4c
--- /dev/null
+++ b/tests/MC/ARM/vfp4-thumb.s.yaml
@@ -0,0 +1,24 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xa2, 0xee, 0x00, 0x1a, 0x42, 0xef, 0xb1, 0x0c, 0x08, 0xef, 0x50, 0x4c, 0x92, 0xee, 0x40, 0x1a, 0xa2, 0xee, 0x40, 0x1a, 0x62, 0xef, 0xb1, 0x0c, 0x28, 0xef, 0x50, 0x4c, 0x92, 0xee, 0x00, 0x1a ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfma.f32 s2, s4, s0"
+        -
+          asm_text: "vfma.f32 d16, d18, d17"
+        -
+          asm_text: "vfma.f32 q2, q4, q0"
+        -
+          asm_text: "vfnma.f32 s2, s4, s0"
+        -
+          asm_text: "vfms.f32 s2, s4, s0"
+        -
+          asm_text: "vfms.f32 d16, d18, d17"
+        -
+          asm_text: "vfms.f32 q2, q4, q0"
+        -
+          asm_text: "vfnms.f32 s2, s4, s0"
diff --git a/tests/MC/ARM/vfp4.s.yaml b/tests/MC/ARM/vfp4.s.yaml
new file mode 100644
index 000000000..82700c7d6
--- /dev/null
+++ b/tests/MC/ARM/vfp4.s.yaml
@@ -0,0 +1,24 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x1a, 0xa2, 0xee, 0xb1, 0x0c, 0x42, 0xf2, 0x50, 0x4c, 0x08, 0xf2, 0x40, 0x1a, 0x92, 0xee, 0x40, 0x1a, 0xa2, 0xee, 0xb1, 0x0c, 0x62, 0xf2, 0x50, 0x4c, 0x28, 0xf2, 0x00, 0x1a, 0x92, 0xee ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfma.f32 s2, s4, s0"
+        -
+          asm_text: "vfma.f32 d16, d18, d17"
+        -
+          asm_text: "vfma.f32 q2, q4, q0"
+        -
+          asm_text: "vfnma.f32 s2, s4, s0"
+        -
+          asm_text: "vfms.f32 s2, s4, s0"
+        -
+          asm_text: "vfms.f32 d16, d18, d17"
+        -
+          asm_text: "vfms.f32 q2, q4, q0"
+        -
+          asm_text: "vfnms.f32 s2, s4, s0"
diff --git a/tests/MC/ARM/vmov-vmvn-replicate.s.yaml b/tests/MC/ARM/vmov-vmvn-replicate.s.yaml
new file mode 100644
index 000000000..3a5b627a2
--- /dev/null
+++ b/tests/MC/ARM/vmov-vmvn-replicate.s.yaml
@@ -0,0 +1,100 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x3f, 0x2e, 0x87, 0xf3, 0x7f, 0x4e, 0x87, 0xf3, 0x1f, 0x2e, 0x87, 0xf3, 0x5f, 0x4e, 0x87, 0xf3, 0x1b, 0x2e, 0x82, 0xf3, 0x5b, 0x4e, 0x82, 0xf3, 0x1b, 0x2e, 0x82, 0xf3, 0x5b, 0x4e, 0x82, 0xf3, 0x5b, 0x4e, 0x82, 0xf3, 0x5b, 0x4e, 0x82, 0xf3, 0x3a, 0x2e, 0x82, 0xf3, 0x7a, 0x4e, 0x82, 0xf3, 0x15, 0x28, 0x82, 0xf3, 0x55, 0x48, 0x82, 0xf3, 0x15, 0x28, 0x82, 0xf3, 0x55, 0x48, 0x82, 0xf3, 0x15, 0x2a, 0x82, 0xf3, 0x55, 0x4a, 0x82, 0xf3, 0x15, 0x2a, 0x82, 0xf3, 0x55, 0x4a, 0x82, 0xf3, 0x15, 0x20, 0x82, 0xf3, 0x55, 0x40, 0x82, 0xf3, 0x15, 0x2d, 0x82, 0xf3, 0x55, 0x4d, 0x82, 0xf3, 0x10, 0x2e, 0x80, 0xf2, 0x50, 0x4e, 0x80, 0xf2, 0x10, 0x2e, 0x80, 0xf2, 0x50, 0x4e, 0x80, 0xf2, 0x14, 0x2e, 0x85, 0xf2, 0x54, 0x4e, 0x85, 0xf2, 0x14, 0x2e, 0x85, 0xf2, 0x54, 0x4e, 0x85, 0xf2, 0x14, 0x2e, 0x85, 0xf2, 0x54, 0x4e, 0x85, 0xf2, 0x35, 0x28, 0x82, 0xf3, 0x75, 0x48, 0x82, 0xf3, 0x35, 0x28, 0x82, 0xf3, 0x75, 0x48, 0x82, 0xf3, 0x35, 0x2a, 0x82, 0xf3, 0x75, 0x4a, 0x82, 0xf3, 0x35, 0x2a, 0x82, 0xf3, 0x75, 0x4a, 0x82, 0xf3, 0x35, 0x20, 0x82, 0xf3, 0x75, 0x40, 0x82, 0xf3, 0x35, 0x2d, 0x82, 0xf3, 0x75, 0x4d, 0x82, 0xf3 ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmov.i64 d2, #0xffffffffffffffff"
+        -
+          asm_text: "vmov.i64 q2, #0xffffffffffffffff"
+        -
+          asm_text: "vmov.i8 d2, #0xff"
+        -
+          asm_text: "vmov.i8 q2, #0xff"
+        -
+          asm_text: "vmov.i8 d2, #0xab"
+        -
+          asm_text: "vmov.i8 q2, #0xab"
+        -
+          asm_text: "vmov.i8 d2, #0xab"
+        -
+          asm_text: "vmov.i8 q2, #0xab"
+        -
+          asm_text: "vmov.i8 q2, #0xab"
+        -
+          asm_text: "vmov.i8 q2, #0xab"
+        -
+          asm_text: "vmov.i64 d2, #0xff00ff00ff00ff00"
+        -
+          asm_text: "vmov.i64 q2, #0xff00ff00ff00ff00"
+        -
+          asm_text: "vmov.i16 d2, #0xa5"
+        -
+          asm_text: "vmov.i16 q2, #0xa5"
+        -
+          asm_text: "vmov.i16 d2, #0xa5"
+        -
+          asm_text: "vmov.i16 q2, #0xa5"
+        -
+          asm_text: "vmov.i16 d2, #0xa500"
+        -
+          asm_text: "vmov.i16 q2, #0xa500"
+        -
+          asm_text: "vmov.i16 d2, #0xa500"
+        -
+          asm_text: "vmov.i16 q2, #0xa500"
+        -
+          asm_text: "vmov.i32 d2, #0xa5"
+        -
+          asm_text: "vmov.i32 q2, #0xa5"
+        -
+          asm_text: "vmov.i32 d2, #0xa5ffff"
+        -
+          asm_text: "vmov.i32 q2, #0xa5ffff"
+        -
+          asm_text: "vmov.i8 d2, #0x0"
+        -
+          asm_text: "vmov.i8 q2, #0x0"
+        -
+          asm_text: "vmov.i8 d2, #0x0"
+        -
+          asm_text: "vmov.i8 q2, #0x0"
+        -
+          asm_text: "vmov.i8 d2, #0x54"
+        -
+          asm_text: "vmov.i8 q2, #0x54"
+        -
+          asm_text: "vmov.i8 d2, #0x54"
+        -
+          asm_text: "vmov.i8 q2, #0x54"
+        -
+          asm_text: "vmov.i8 d2, #0x54"
+        -
+          asm_text: "vmov.i8 q2, #0x54"
+        -
+          asm_text: "vmvn.i16 d2, #0xa5"
+        -
+          asm_text: "vmvn.i16 q2, #0xa5"
+        -
+          asm_text: "vmvn.i16 d2, #0xa5"
+        -
+          asm_text: "vmvn.i16 q2, #0xa5"
+        -
+          asm_text: "vmvn.i16 d2, #0xa500"
+        -
+          asm_text: "vmvn.i16 q2, #0xa500"
+        -
+          asm_text: "vmvn.i16 d2, #0xa500"
+        -
+          asm_text: "vmvn.i16 q2, #0xa500"
+        -
+          asm_text: "vmvn.i32 d2, #0xa5"
+        -
+          asm_text: "vmvn.i32 q2, #0xa5"
+        -
+          asm_text: "vmvn.i32 d2, #0xa5ffff"
+        -
+          asm_text: "vmvn.i32 q2, #0xa5ffff"
diff --git a/tests/MC/ARM/vmovhr.s.yaml b/tests/MC/ARM/vmovhr.s.yaml
new file mode 100644
index 000000000..d9997f650
--- /dev/null
+++ b/tests/MC/ARM/vmovhr.s.yaml
@@ -0,0 +1,16 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x16, 0xee, 0x90, 0x09, 0x0a, 0xee, 0x90, 0x19, 0x01, 0xee, 0x10, 0xd9, 0x12, 0xee, 0x90, 0xd9 ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_V8", "CS_MODE_THUMB" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmov.f16 r0, s13"
+        -
+          asm_text: "vmov.f16 s21, r1"
+        -
+          asm_text: "vmov.f16 s2, sp"
+        -
+          asm_text: "vmov.f16 sp, s5"
diff --git a/tests/MC/ARM/vpush-vpop-thumb.s.yaml b/tests/MC/ARM/vpush-vpop-thumb.s.yaml
new file mode 100644
index 000000000..3aede9640
--- /dev/null
+++ b/tests/MC/ARM/vpush-vpop-thumb.s.yaml
@@ -0,0 +1,24 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x2d, 0xed, 0x0a, 0x8b, 0x2d, 0xed, 0x05, 0x4a, 0xbd, 0xec, 0x0a, 0x8b, 0xbd, 0xec, 0x05, 0x4a, 0x2d, 0xed, 0x0a, 0x8b, 0x2d, 0xed, 0x05, 0x4a, 0xbd, 0xec, 0x0a, 0x8b, 0xbd, 0xec, 0x05, 0x4a ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_THUMB" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpush {d8, d9, d10, d11, d12}"
+        -
+          asm_text: "vpush {s8, s9, s10, s11, s12}"
+        -
+          asm_text: "vpop {d8, d9, d10, d11, d12}"
+        -
+          asm_text: "vpop {s8, s9, s10, s11, s12}"
+        -
+          asm_text: "vpush {d8, d9, d10, d11, d12}"
+        -
+          asm_text: "vpush {s8, s9, s10, s11, s12}"
+        -
+          asm_text: "vpop {d8, d9, d10, d11, d12}"
+        -
+          asm_text: "vpop {s8, s9, s10, s11, s12}"
diff --git a/tests/MC/ARM/vpush-vpop.s.yaml b/tests/MC/ARM/vpush-vpop.s.yaml
new file mode 100644
index 000000000..4a6edad02
--- /dev/null
+++ b/tests/MC/ARM/vpush-vpop.s.yaml
@@ -0,0 +1,24 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x0a, 0x8b, 0x2d, 0xed, 0x05, 0x4a, 0x2d, 0xed, 0x0a, 0x8b, 0xbd, 0xec, 0x05, 0x4a, 0xbd, 0xec, 0x0a, 0x8b, 0x2d, 0xed, 0x05, 0x4a, 0x2d, 0xed, 0x0a, 0x8b, 0xbd, 0xec, 0x05, 0x4a, 0xbd, 0xec ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_ARM" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpush {d8, d9, d10, d11, d12}"
+        -
+          asm_text: "vpush {s8, s9, s10, s11, s12}"
+        -
+          asm_text: "vpop {d8, d9, d10, d11, d12}"
+        -
+          asm_text: "vpop {s8, s9, s10, s11, s12}"
+        -
+          asm_text: "vpush {d8, d9, d10, d11, d12}"
+        -
+          asm_text: "vpush {s8, s9, s10, s11, s12}"
+        -
+          asm_text: "vpop {d8, d9, d10, d11, d12}"
+        -
+          asm_text: "vpop {s8, s9, s10, s11, s12}"
diff --git a/tests/MC/ARM/vscclrm-asm.s.yaml b/tests/MC/ARM/vscclrm-asm.s.yaml
new file mode 100644
index 000000000..b4163355a
--- /dev/null
+++ b/tests/MC/ARM/vscclrm-asm.s.yaml
@@ -0,0 +1,26 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x9f, 0xec, 0x04, 0x0a, 0xdf, 0xec, 0x06, 0x1a, 0x9f, 0xec, 0x0c, 0x9a, 0xdf, 0xec, 0x01, 0xfa, 0x9f, 0xec, 0x04, 0x0b, 0x9f, 0xec, 0x08, 0x0b, 0x9f, 0xec, 0x06, 0x5b, 0x88, 0xbf, 0xdf, 0xec, 0x1d, 0x1a ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_V8", "CS_MODE_THUMB" ]
+    expected:
+      insns:
+        -
+          asm_text: "vscclrm {s0, s1, s2, s3, vpr}"
+        -
+          asm_text: "vscclrm {s3, s4, s5, s6, s7, s8, vpr}"
+        -
+          asm_text: "vscclrm {s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, vpr}"
+        -
+          asm_text: "vscclrm {s31, vpr}"
+        -
+          asm_text: "vscclrm {d0, d1, vpr}"
+        -
+          asm_text: "vscclrm {d0, d1, d2, d3, vpr}"
+        -
+          asm_text: "vscclrm {d5, d6, d7, vpr}"
+        -
+          asm_text: "it hi"
+        -
+          asm_text: "vscclrmhi {s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31, vpr}"
diff --git a/tests/MC/ARM/vstrldr_sys.s.yaml b/tests/MC/ARM/vstrldr_sys.s.yaml
new file mode 100644
index 000000000..9d0aff5d2
--- /dev/null
+++ b/tests/MC/ARM/vstrldr_sys.s.yaml
@@ -0,0 +1,102 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x80, 0xed, 0x80, 0x2f, 0x09, 0xed, 0x86, 0x4f, 0x29, 0xed, 0x86, 0x4f, 0x29, 0xec, 0x86, 0x4f, 0x88, 0xbf, 0x80, 0xed, 0x80, 0x2f, 0x90, 0xed, 0x80, 0x2f, 0x19, 0xed, 0x86, 0x4f, 0x39, 0xed, 0x86, 0x4f, 0x39, 0xec, 0x86, 0x4f, 0x3d, 0xec, 0x8d, 0x4f, 0x88, 0xbf, 0x90, 0xed, 0x80, 0x2f, 0xcc, 0xed, 0xff, 0xef, 0xec, 0xed, 0xff, 0xef, 0xec, 0xec, 0xff, 0xef, 0x6d, 0xec, 0x86, 0xef, 0xdc, 0xed, 0xff, 0xef, 0xfc, 0xed, 0xff, 0xef, 0xfc, 0xec, 0xff, 0xef, 0x7d, 0xec, 0x86, 0xef, 0xc0, 0xed, 0x80, 0xcf, 0x49, 0xed, 0x86, 0xcf, 0xc6, 0xed, 0xfd, 0xcf, 0x4e, 0xed, 0xff, 0xcf, 0xcc, 0xed, 0xff, 0xcf, 0x6d, 0xec, 0x86, 0xcf, 0xd0, 0xed, 0x80, 0xcf, 0x59, 0xed, 0x86, 0xcf, 0xd6, 0xed, 0xfd, 0xcf, 0x5e, 0xed, 0xff, 0xcf, 0xdc, 0xed, 0xff, 0xcf, 0x7d, 0xec, 0x86, 0xcf, 0xc6, 0xed, 0xfd, 0x8f, 0x4e, 0xed, 0xff, 0xaf, 0xe6, 0xed, 0xfd, 0x8f, 0x6e, 0xed, 0xff, 0xaf, 0xe6, 0xec, 0xfd, 0x8f, 0x6e, 0xec, 0xff, 0xaf, 0x6d, 0xec, 0x86, 0xaf, 0xd6, 0xed, 0xfd, 0x8f, 0x5e, 0xed, 0xff, 0xaf, 0xf6, 0xed, 0xfd, 0x8f, 0x7e, 0xed, 0xff, 0xaf, 0xf6, 0xec, 0xfd, 0x8f, 0x7e, 0xec, 0xff, 0xaf, 0x7d, 0xec, 0x86, 0xaf ]
+      arch: "CS_ARCH_ARM"
+      options: [ "CS_OPT_NO_BRANCH_OFFSET", "CS_MODE_MCLASS", "CS_MODE_V8", "CS_MODE_THUMB" ]
+    expected:
+      insns:
+        -
+          asm_text: "vstr fpscr, [r0]"
+        -
+          asm_text: "vstr fpscr_nzcvqc, [r9, #-0x18]"
+        -
+          asm_text: "vstr fpscr_nzcvqc, [r9, #-0x18]!"
+        -
+          asm_text: "vstr fpscr_nzcvqc, [r9], #-0x18"
+        -
+          asm_text: "it hi"
+        -
+          asm_text: "vstrhi fpscr, [r0]"
+        -
+          asm_text: "vldr fpscr, [r0]"
+        -
+          asm_text: "vldr fpscr_nzcvqc, [r9, #-0x18]"
+        -
+          asm_text: "vldr fpscr_nzcvqc, [r9, #-0x18]!"
+        -
+          asm_text: "vldr fpscr_nzcvqc, [r9], #-0x18"
+        -
+          asm_text: "vldr fpscr_nzcvqc, [sp], #-0x34"
+        -
+          asm_text: "it hi"
+        -
+          asm_text: "vldrhi fpscr, [r0]"
+        -
+          asm_text: "vstr fpcxts, [r12, #0x1fc]"
+        -
+          asm_text: "vstr fpcxts, [r12, #0x1fc]!"
+        -
+          asm_text: "vstr fpcxts, [r12], #0x1fc"
+        -
+          asm_text: "vstr fpcxts, [sp], #-0x18"
+        -
+          asm_text: "vldr fpcxts, [r12, #0x1fc]"
+        -
+          asm_text: "vldr fpcxts, [r12, #0x1fc]!"
+        -
+          asm_text: "vldr fpcxts, [r12], #0x1fc"
+        -
+          asm_text: "vldr fpcxts, [sp], #-0x18"
+        -
+          asm_text: "vstr fpcxtns, [r0]"
+        -
+          asm_text: "vstr fpcxtns, [r9, #-0x18]"
+        -
+          asm_text: "vstr fpcxtns, [r6, #0x1f4]"
+        -
+          asm_text: "vstr fpcxtns, [lr, #-0x1fc]"
+        -
+          asm_text: "vstr fpcxtns, [r12, #0x1fc]"
+        -
+          asm_text: "vstr fpcxtns, [sp], #-0x18"
+        -
+          asm_text: "vldr fpcxtns, [r0]"
+        -
+          asm_text: "vldr fpcxtns, [r9, #-0x18]"
+        -
+          asm_text: "vldr fpcxtns, [r6, #0x1f4]"
+        -
+          asm_text: "vldr fpcxtns, [lr, #-0x1fc]"
+        -
+          asm_text: "vldr fpcxtns, [r12, #0x1fc]"
+        -
+          asm_text: "vldr fpcxtns, [sp], #-0x18"
+        -
+          asm_text: "vstr vpr, [r6, #0x1f4]"
+        -
+          asm_text: "vstr p0, [lr, #-0x1fc]"
+        -
+          asm_text: "vstr vpr, [r6, #0x1f4]!"
+        -
+          asm_text: "vstr p0, [lr, #-0x1fc]!"
+        -
+          asm_text: "vstr vpr, [r6], #0x1f4"
+        -
+          asm_text: "vstr p0, [lr], #-0x1fc"
+        -
+          asm_text: "vstr p0, [sp], #-0x18"
+        -
+          asm_text: "vldr vpr, [r6, #0x1f4]"
+        -
+          asm_text: "vldr p0, [lr, #-0x1fc]"
+        -
+          asm_text: "vldr vpr, [r6, #0x1f4]!"
+        -
+          asm_text: "vldr p0, [lr, #-0x1fc]!"
+        -
+          asm_text: "vldr vpr, [r6], #0x1f4"
+        -
+          asm_text: "vldr p0, [lr], #-0x1fc"
+        -
+          asm_text: "vldr p0, [sp], #-0x18"
diff --git a/tests/MC/Alpha/insn-alpha-be.s.yaml b/tests/MC/Alpha/insn-alpha-be.s.yaml
new file mode 100644
index 000000000..96fb54010
--- /dev/null
+++ b/tests/MC/Alpha/insn-alpha-be.s.yaml
@@ -0,0 +1,1783 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x40, 0x22, 0x00, 0x03 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "addl $1,$2,$3"
+  -
+    input:
+      bytes: [ 0x40, 0x3b, 0xd0, 0x03 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "addl $1,0xde,$3"
+  -
+    input:
+      bytes: [ 0x40, 0x22, 0x04, 0x03 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "addq $1,$2,$3"
+  -
+    input:
+      bytes: [ 0x40, 0x3b, 0xd4, 0x03 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "addq $1,0xde,$3"
+  -
+    input:
+      bytes: [ 0x58, 0x22, 0xb0, 0x03 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "adds/su $f1,$f10,$f11"
+  -
+    input:
+      bytes: [ 0x58, 0x22, 0xb4, 0x03 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "addt/su $f1,$f10,$f11"
+  -
+    input:
+      bytes: [ 0x44, 0x22, 0x00, 0x03 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "and $1,$2,$3"
+  -
+    input:
+      bytes: [ 0x44, 0x3b, 0xd0, 0x03 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "and $1,0xde,$3"
+  -
+    input:
+      bytes: [ 0xe4, 0x20, 0x3f, 0xfc ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "beq $1,0xfffffffffffffff4"
+  -
+    input:
+      bytes: [ 0xf8, 0x20, 0x3f, 0xfc ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bge $1,0xfffffffffffffff4"
+  -
+    input:
+      bytes: [ 0xfc, 0x20, 0x3f, 0xfc ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bgt $1,0xfffffffffffffff4"
+  -
+    input:
+      bytes: [ 0x44, 0x22, 0x01, 0x03 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bic $1,$2,$3"
+  -
+    input:
+      bytes: [ 0x44, 0x3b, 0xd1, 0x03 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bic $1,0xde,$3"
+  -
+    input:
+      bytes: [ 0x44, 0x22, 0x04, 0x03 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bis $1,$2,$3"
+  -
+    input:
+      bytes: [ 0x44, 0x3b, 0xd4, 0x03 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bis $1,0xde,$3"
+  -
+    input:
+      bytes: [ 0xe0, 0x20, 0x3f, 0xfc ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "blbc $1,0xfffffffffffffff4"
+  -
+    input:
+      bytes: [ 0xf0, 0x20, 0x3f, 0xfc ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "blbs $1,0xfffffffffffffff4"
+  -
+    input:
+      bytes: [ 0xec, 0x20, 0x3f, 0xfc ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ble $1,0xfffffffffffffff4"
+  -
+    input:
+      bytes: [ 0xe8, 0x20, 0x3f, 0xfc ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "blt $1,0xfffffffffffffff4"
+  -
+    input:
+      bytes: [ 0xf4, 0x20, 0x3f, 0xfc ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bne $1,0xfffffffffffffff4"
+  -
+    input:
+      bytes: [ 0xc3, 0xe0, 0x3f, 0xfc ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "br $31,0xfffffffffffffff4"
+  -
+    input:
+      bytes: [ 0xd3, 0x40, 0x3f, 0xfc ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bsr $26,$0xfffffffffffffff4 ..ng"
+  -
+    input:
+      bytes: [ 0x44, 0x22, 0x04, 0x83 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmoveq $1,$2,$3"
+  -
+    input:
+      bytes: [ 0x44, 0x22, 0x08, 0xc3 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmovge $1,$2,$3"
+  -
+    input:
+      bytes: [ 0x44, 0x22, 0x0c, 0xc3 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmovgt $1,$2,$3"
+  -
+    input:
+      bytes: [ 0x44, 0x22, 0x02, 0xc3 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmovlbc $1,$2,$3"
+  -
+    input:
+      bytes: [ 0x44, 0x22, 0x02, 0x83 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmovlbs $1,$2,$3"
+  -
+    input:
+      bytes: [ 0x44, 0x22, 0x0c, 0x83 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmovle $1,$2,$3"
+  -
+    input:
+      bytes: [ 0x44, 0x22, 0x08, 0x83 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmovlt $1,$2,$3"
+  -
+    input:
+      bytes: [ 0x44, 0x22, 0x04, 0xc3 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmovne $1,$2,$3"
+  -
+    input:
+      bytes: [ 0x40, 0x22, 0x01, 0xe3 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpbge $1,$2,$3"
+  -
+    input:
+      bytes: [ 0x40, 0x3b, 0xd1, 0xe3 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpbge $1,0xde,$3"
+  -
+    input:
+      bytes: [ 0x40, 0x22, 0x05, 0xa3 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpeq $1,$2,$3"
+  -
+    input:
+      bytes: [ 0x40, 0x3b, 0xd5, 0xa3 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpeq $1,0xde,$3"
+  -
+    input:
+      bytes: [ 0x40, 0x22, 0x0d, 0xa3 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmple $1,$2,$3"
+  -
+    input:
+      bytes: [ 0x40, 0x3b, 0xdd, 0xa3 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmple $1,0xde,$3"
+  -
+    input:
+      bytes: [ 0x40, 0x22, 0x09, 0xa3 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmplt $1,$2,$3"
+  -
+    input:
+      bytes: [ 0x40, 0x3b, 0xd9, 0xa3 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmplt $1,0xde,$3"
+  -
+    input:
+      bytes: [ 0x58, 0x22, 0xb4, 0xa3 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpteq/su $f1,$f10,$f11"
+  -
+    input:
+      bytes: [ 0x58, 0x22, 0xb4, 0xe3 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmptle/su $f1,$f10,$f11"
+  -
+    input:
+      bytes: [ 0x58, 0x22, 0xb4, 0xc3 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmptlt/su $f1,$f10,$f11"
+  -
+    input:
+      bytes: [ 0x58, 0x22, 0xb4, 0x83 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmptun/su $f1,$f10,$f11"
+  -
+    input:
+      bytes: [ 0x40, 0x22, 0x07, 0xa3 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpule $1,$2,$3"
+  -
+    input:
+      bytes: [ 0x40, 0x3b, 0xd7, 0xa3 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpule $1,0xde,$3"
+  -
+    input:
+      bytes: [ 0x40, 0x22, 0x03, 0xa3 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpult $1,$2,$3"
+  -
+    input:
+      bytes: [ 0x40, 0x3b, 0xd3, 0xa3 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpult $1,0xde,$3"
+  -
+    input:
+      bytes: [ 0x5c, 0x22, 0x04, 0x43 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cpyse $f1,$f10,$f11"
+  -
+    input:
+      bytes: [ 0x5c, 0x22, 0x04, 0x23 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cpysn $f1,$f10,$f11"
+  -
+    input:
+      bytes: [ 0x5c, 0x22, 0x04, 0x03 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cpys $f1,$f10,$f11"
+  -
+    input:
+      bytes: [ 0x73, 0xe1, 0x06, 0x42 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ctlz $1,$2"
+  -
+    input:
+      bytes: [ 0x73, 0xe1, 0x06, 0x02 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ctpop $1,$2"
+  -
+    input:
+      bytes: [ 0x73, 0xe1, 0x06, 0x62 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cttz $1,$2"
+  -
+    input:
+      bytes: [ 0x5b, 0xe1, 0xf7, 0x82 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cvtqs/sui $f1,$f10"
+  -
+    input:
+      bytes: [ 0x5b, 0xe1, 0xf7, 0xc2 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cvtqt/sui $f1,$f10"
+  -
+    input:
+      bytes: [ 0x5b, 0xe1, 0xd5, 0x82 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cvtst/s $f1,$f10"
+  -
+    input:
+      bytes: [ 0x5b, 0xe1, 0xa5, 0xe2 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cvttq/svc $f1,$f10"
+  -
+    input:
+      bytes: [ 0x5b, 0xe1, 0xf5, 0x82 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cvtts/sui $f1,$f10"
+  -
+    input:
+      bytes: [ 0x58, 0x22, 0xb0, 0x63 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "divs/su $f1,$f10,$f11"
+  -
+    input:
+      bytes: [ 0x58, 0x22, 0xb4, 0x63 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "divt/su $f1,$f10,$f11"
+  -
+    input:
+      bytes: [ 0x63, 0xe1, 0xe8, 0x00 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ecb ($1)"
+  -
+    input:
+      bytes: [ 0x44, 0x22, 0x09, 0x03 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "eqv $1,$2,$3"
+  -
+    input:
+      bytes: [ 0x44, 0x3b, 0xd9, 0x03 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "eqv $1,0xde,$3"
+  -
+    input:
+      bytes: [ 0x60, 0x00, 0x04, 0x00 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "excb"
+  -
+    input:
+      bytes: [ 0x48, 0x22, 0x00, 0xc3 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "extbl $1,$2,$3"
+  -
+    input:
+      bytes: [ 0x48, 0x3b, 0xd0, 0xc3 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "extbl $1,0xde,$3"
+  -
+    input:
+      bytes: [ 0x48, 0x22, 0x0d, 0x43 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "extlh $1,$2,$3"
+  -
+    input:
+      bytes: [ 0x48, 0x3b, 0xdd, 0x43 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "extlh $1,0xde,$3"
+  -
+    input:
+      bytes: [ 0x48, 0x22, 0x04, 0xc3 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "extll $1,$2,$3"
+  -
+    input:
+      bytes: [ 0x48, 0x3b, 0xd4, 0xc3 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "extll $1,0xde,$3"
+  -
+    input:
+      bytes: [ 0x48, 0x22, 0x0f, 0x43 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "extqh $1,$2,$3"
+  -
+    input:
+      bytes: [ 0x48, 0x3b, 0xdf, 0x43 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "extqh $1,0xde,$3"
+  -
+    input:
+      bytes: [ 0x48, 0x22, 0x06, 0xc3 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "extql $1,$2,$3"
+  -
+    input:
+      bytes: [ 0x48, 0x3b, 0xd6, 0xc3 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "extql $1,0xde,$3"
+  -
+    input:
+      bytes: [ 0x48, 0x22, 0x0b, 0x43 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "extwh $1,$2,$3"
+  -
+    input:
+      bytes: [ 0x48, 0x3b, 0xdb, 0x43 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "extwh $1,0xde,$3"
+  -
+    input:
+      bytes: [ 0x48, 0x22, 0x02, 0xc3 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "extwl $1,$2,$3"
+  -
+    input:
+      bytes: [ 0x48, 0x3b, 0xd2, 0xc3 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "extwl $1,0xde,$3"
+  -
+    input:
+      bytes: [ 0xc4, 0x20, 0x3f, 0xfc ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fbeq $f1,0xfffffffffffffff4"
+  -
+    input:
+      bytes: [ 0xd8, 0x20, 0x3f, 0xfc ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fbge $f1,0xfffffffffffffff4"
+  -
+    input:
+      bytes: [ 0xdc, 0x20, 0x3f, 0xfc ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fbgt $f1,0xfffffffffffffff4"
+  -
+    input:
+      bytes: [ 0xcc, 0x20, 0x3f, 0xfc ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fble $f1,0xfffffffffffffff4"
+  -
+    input:
+      bytes: [ 0xc8, 0x20, 0x3f, 0xfc ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fblt $f1,0xfffffffffffffff4"
+  -
+    input:
+      bytes: [ 0xd4, 0x20, 0x3f, 0xfc ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fbne $f1,0xfffffffffffffff4"
+  -
+    input:
+      bytes: [ 0x5c, 0x22, 0x05, 0x43 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmoveq ,$f10,$f11"
+  -
+    input:
+      bytes: [ 0x5c, 0x22, 0x05, 0xa3 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmovge ,$f10,$f11"
+  -
+    input:
+      bytes: [ 0x5c, 0x22, 0x05, 0xe3 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmovgt ,$f10,$f11"
+  -
+    input:
+      bytes: [ 0x5c, 0x22, 0x05, 0xc3 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmovle ,$f10,$f11"
+  -
+    input:
+      bytes: [ 0x5c, 0x22, 0x05, 0x83 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmovlt ,$f10,$f11"
+  -
+    input:
+      bytes: [ 0x5c, 0x22, 0x05, 0x63 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmovne ,$f10,$f11"
+  -
+    input:
+      bytes: [ 0x63, 0xe1, 0x80, 0x00 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fetch ($1)"
+  -
+    input:
+      bytes: [ 0x63, 0xe1, 0xa0, 0x00 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fetch_m ($1)"
+  -
+    input:
+      bytes: [ 0x70, 0x3f, 0x0f, 0x01 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ftois $f1,$1"
+  -
+    input:
+      bytes: [ 0x70, 0x3f, 0x0e, 0x01 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ftoit $f1,$1"
+  -
+    input:
+      bytes: [ 0x48, 0x22, 0x01, 0x63 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "insbl $1,$2,$3"
+  -
+    input:
+      bytes: [ 0x48, 0x3b, 0xd1, 0x63 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "insbl $1,0xde,$3"
+  -
+    input:
+      bytes: [ 0x48, 0x22, 0x0c, 0xe3 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "inslh $1,$2,$3"
+  -
+    input:
+      bytes: [ 0x48, 0x3b, 0xdc, 0xe3 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "inslh $1,0xde,$3"
+  -
+    input:
+      bytes: [ 0x48, 0x22, 0x05, 0x63 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "insll $1,$2,$3"
+  -
+    input:
+      bytes: [ 0x48, 0x3b, 0xd5, 0x63 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "insll $1,0xde,$3"
+  -
+    input:
+      bytes: [ 0x48, 0x22, 0x0e, 0xe3 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "insqh $1,$2,$3"
+  -
+    input:
+      bytes: [ 0x48, 0x3b, 0xde, 0xe3 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "insqh $1,0xde,$3"
+  -
+    input:
+      bytes: [ 0x48, 0x22, 0x07, 0x63 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "insql $1,$2,$3"
+  -
+    input:
+      bytes: [ 0x48, 0x3b, 0xd7, 0x63 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "insql $1,0xde,$3"
+  -
+    input:
+      bytes: [ 0x48, 0x22, 0x0a, 0xe3 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "inswh $1,$2,$3"
+  -
+    input:
+      bytes: [ 0x48, 0x3b, 0xda, 0xe3 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "inswh $1,0xde,$3"
+  -
+    input:
+      bytes: [ 0x48, 0x22, 0x03, 0x63 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "inswl $1,$2,$3"
+  -
+    input:
+      bytes: [ 0x48, 0x3b, 0xd3, 0x63 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "inswl $1,0xde,$3"
+  -
+    input:
+      bytes: [ 0x50, 0x3f, 0x00, 0x81 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "itofs $1,$f1"
+  -
+    input:
+      bytes: [ 0x50, 0x3f, 0x04, 0x81 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "itoft $1,$f1"
+  -
+    input:
+      bytes: [ 0x6b, 0xfa, 0x00, 0x00 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "jmp $31,$12,0"
+  -
+    input:
+      bytes: [ 0x6b, 0x5b, 0x40, 0x00 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "jsr $26,($27),0"
+  -
+    input:
+      bytes: [ 0x68, 0x22, 0xcf, 0xff ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "jsr_coroutine $1,($2),0xfff"
+  -
+    input:
+      bytes: [ 0x20, 0x22, 0x00, 0x10 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "lda $1,0x10($2)"
+  -
+    input:
+      bytes: [ 0x24, 0x22, 0x00, 0x10 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldah $1,0x10($2)"
+  -
+    input:
+      bytes: [ 0x28, 0x22, 0x00, 0x10 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldbu $1,0x10($2)"
+  -
+    input:
+      bytes: [ 0xa0, 0x22, 0x00, 0x10 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldl $1,0x10($2)"
+  -
+    input:
+      bytes: [ 0xa8, 0x22, 0x00, 0x10 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldl_l $1,0x10($2)"
+  -
+    input:
+      bytes: [ 0xa4, 0x22, 0x00, 0x10 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldq $1,0x10($2)"
+  -
+    input:
+      bytes: [ 0xac, 0x22, 0x00, 0x10 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldq_l $1,0x10($2)"
+  -
+    input:
+      bytes: [ 0x2c, 0x22, 0x00, 0x10 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldq_u $1,0x10($2)"
+  -
+    input:
+      bytes: [ 0x88, 0x22, 0x00, 0x10 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "lds $f1,0x10($2)"
+  -
+    input:
+      bytes: [ 0x8c, 0x22, 0x00, 0x10 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldt $f1,0x10($2)"
+  -
+    input:
+      bytes: [ 0x30, 0x22, 0x00, 0x10 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldwu $1,0x10($2)"
+  -
+    input:
+      bytes: [ 0x60, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mb"
+  -
+    input:
+      bytes: [ 0x48, 0x22, 0x00, 0x43 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mskbl $1,$2,$3"
+  -
+    input:
+      bytes: [ 0x48, 0x3b, 0xd0, 0x43 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mskbl $1,0xde,$3"
+  -
+    input:
+      bytes: [ 0x48, 0x22, 0x0c, 0x43 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "msklh $1,$2,$3"
+  -
+    input:
+      bytes: [ 0x48, 0x3b, 0xdc, 0x43 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "msklh $1,0xde,$3"
+  -
+    input:
+      bytes: [ 0x48, 0x22, 0x04, 0x43 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mskll $1,$2,$3"
+  -
+    input:
+      bytes: [ 0x48, 0x3b, 0xd4, 0x43 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mskll $1,0xde,$3"
+  -
+    input:
+      bytes: [ 0x48, 0x22, 0x0e, 0x43 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mskqh $1,$2,$3"
+  -
+    input:
+      bytes: [ 0x48, 0x3b, 0xde, 0x43 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mskqh $1,0xde,$3"
+  -
+    input:
+      bytes: [ 0x48, 0x22, 0x06, 0x43 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mskql $1,$2,$3"
+  -
+    input:
+      bytes: [ 0x48, 0x3b, 0xd6, 0x43 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mskql $1,0xde,$3"
+  -
+    input:
+      bytes: [ 0x48, 0x22, 0x0a, 0x43 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mskwh $1,$2,$3"
+  -
+    input:
+      bytes: [ 0x48, 0x3b, 0xda, 0x43 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mskwh $1,0xde,$3"
+  -
+    input:
+      bytes: [ 0x48, 0x22, 0x02, 0x43 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mskwl $1,$2,$3"
+  -
+    input:
+      bytes: [ 0x48, 0x3b, 0xd2, 0x43 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mskwl $1,0xde,$3"
+  -
+    input:
+      bytes: [ 0x4c, 0x22, 0x00, 0x03 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mull $1,$2,$3"
+  -
+    input:
+      bytes: [ 0x4c, 0x3b, 0xd0, 0x03 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mull $1,0xde,$3"
+  -
+    input:
+      bytes: [ 0x4c, 0x22, 0x04, 0x03 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulq $1,$2,$3"
+  -
+    input:
+      bytes: [ 0x4c, 0x3b, 0xd4, 0x03 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulq $1,0xde,$3"
+  -
+    input:
+      bytes: [ 0x58, 0x22, 0xb0, 0x43 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "muls/su $f1,$f10,$f11"
+  -
+    input:
+      bytes: [ 0x58, 0x22, 0xb4, 0x43 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mult/su $f1,$f10,$f11"
+  -
+    input:
+      bytes: [ 0x44, 0x22, 0x05, 0x03 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ornot $1,$2,$3"
+  -
+    input:
+      bytes: [ 0x44, 0x3b, 0xd5, 0x03 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ornot $1,0xde,$3"
+  -
+    input:
+      bytes: [ 0x60, 0x20, 0xe0, 0x00 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "rc $1"
+  -
+    input:
+      bytes: [ 0x6b, 0xfa, 0x80, 0x01 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ret $31,($26),1"
+  -
+    input:
+      bytes: [ 0x60, 0x1f, 0xc0, 0x00 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "rpcc $0"
+  -
+    input:
+      bytes: [ 0x60, 0x20, 0xf0, 0x00 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "rs $1"
+  -
+    input:
+      bytes: [ 0x40, 0x22, 0x00, 0x43 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "s4addl $1,$2,$3"
+  -
+    input:
+      bytes: [ 0x40, 0x3b, 0xd0, 0x43 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "s4addl $1,0xde,$3"
+  -
+    input:
+      bytes: [ 0x40, 0x22, 0x01, 0x63 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "s4subl $1,$2,$3"
+  -
+    input:
+      bytes: [ 0x40, 0x3b, 0xd1, 0x63 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "s4subl $1,0xde,$3"
+  -
+    input:
+      bytes: [ 0x40, 0x22, 0x05, 0x63 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "s4subq $1,$2,$3"
+  -
+    input:
+      bytes: [ 0x40, 0x3b, 0xd5, 0x63 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "s4subq $1,0xde,$3"
+  -
+    input:
+      bytes: [ 0x40, 0x22, 0x02, 0x43 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "s8addl $1,$2,$3"
+  -
+    input:
+      bytes: [ 0x40, 0x3b, 0xd2, 0x43 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "s8addl $1,0xde,$3"
+  -
+    input:
+      bytes: [ 0x40, 0x22, 0x06, 0x43 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "s8addq $1,$2,$3"
+  -
+    input:
+      bytes: [ 0x40, 0x3b, 0xd6, 0x43 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "s8addq $1,0xde,$3"
+  -
+    input:
+      bytes: [ 0x40, 0x22, 0x03, 0x63 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "s8subl $1,$2,$3"
+  -
+    input:
+      bytes: [ 0x40, 0x3b, 0xd3, 0x63 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "s8subl $1,0xde,$3"
+  -
+    input:
+      bytes: [ 0x40, 0x22, 0x07, 0x63 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "s8subq $1,$2,$3"
+  -
+    input:
+      bytes: [ 0x40, 0x3b, 0xd7, 0x63 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "s8subq $1,0xde,$3"
+  -
+    input:
+      bytes: [ 0x73, 0xe1, 0x00, 0x02 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sextb $1,$2"
+  -
+    input:
+      bytes: [ 0x73, 0xe1, 0x00, 0x22 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sextw $1,$2"
+  -
+    input:
+      bytes: [ 0x48, 0x22, 0x07, 0x23 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sll $1,$2,$3"
+  -
+    input:
+      bytes: [ 0x48, 0x3b, 0xd7, 0x23 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sll $1,0xde,$3"
+  -
+    input:
+      bytes: [ 0x53, 0xe1, 0xb1, 0x62 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrts/su $f1,$f10"
+  -
+    input:
+      bytes: [ 0x53, 0xe1, 0xb5, 0x62 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrtt/su $f1,$f10"
+  -
+    input:
+      bytes: [ 0x48, 0x22, 0x07, 0x83 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sra $1,$2,$3"
+  -
+    input:
+      bytes: [ 0x48, 0x3b, 0xd7, 0x83 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sra $1,0xde,$3"
+  -
+    input:
+      bytes: [ 0x48, 0x22, 0x06, 0x83 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "srl $1,$2,$3"
+  -
+    input:
+      bytes: [ 0x48, 0x3b, 0xd6, 0x83 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "srl $1,0xde,$3"
+  -
+    input:
+      bytes: [ 0x38, 0x22, 0x00, 0x10 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "stb $1, 0x10($2)"
+  -
+    input:
+      bytes: [ 0xb0, 0x22, 0x00, 0x10 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "stl $1,0x10($2)"
+  -
+    input:
+      bytes: [ 0xb8, 0x22, 0x00, 0x10 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "stl_c $1,0x10($2)"
+  -
+    input:
+      bytes: [ 0xb4, 0x22, 0x00, 0x10 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "stq $1,0x10($2)"
+  -
+    input:
+      bytes: [ 0xbc, 0x22, 0x00, 0x10 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "stq_c $1,0x10($2)"
+  -
+    input:
+      bytes: [ 0x3c, 0x22, 0x00, 0x10 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "stq_u $1, 0x10($2)"
+  -
+    input:
+      bytes: [ 0x98, 0x22, 0x00, 0x10 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sts $f1,0x10($2)"
+  -
+    input:
+      bytes: [ 0x9c, 0x22, 0x00, 0x10 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "stt $f1,0x10($2)"
+  -
+    input:
+      bytes: [ 0x34, 0x22, 0x00, 0x10 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "stw $1,0x10($2)"
+  -
+    input:
+      bytes: [ 0x40, 0x22, 0x01, 0x23 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "subl $1,$2,$3"
+  -
+    input:
+      bytes: [ 0x40, 0x3b, 0xd1, 0x23 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "subl $1,0xde,$3"
+  -
+    input:
+      bytes: [ 0x40, 0x22, 0x05, 0x23 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "subq $1,$2,$3"
+  -
+    input:
+      bytes: [ 0x40, 0x3b, 0xd5, 0x23 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "subq $1,0xde,$3"
+  -
+    input:
+      bytes: [ 0x58, 0x22, 0xb0, 0x23 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "subs/su $f1,$f10,$f11"
+  -
+    input:
+      bytes: [ 0x58, 0x22, 0xb4, 0x23 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "subt/su $f1,$f10,$f11"
+  -
+    input:
+      bytes: [ 0x60, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "trapb"
+  -
+    input:
+      bytes: [ 0x4c, 0x22, 0x06, 0x03 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "umulh $1,$2,$3"
+  -
+    input:
+      bytes: [ 0x4c, 0x3b, 0xd6, 0x03 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "umulh $1,0xde,$3"
+  -
+    input:
+      bytes: [ 0x63, 0xe1, 0xf8, 0x00 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "wh64 ($1)"
+  -
+    input:
+      bytes: [ 0x63, 0xe1, 0xfc, 0x00 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "wh64en ($1)"
+  -
+    input:
+      bytes: [ 0x60, 0x00, 0x44, 0x00 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "wmb"
+  -
+    input:
+      bytes: [ 0x44, 0x22, 0x08, 0x03 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor $1,$2,$3"
+  -
+    input:
+      bytes: [ 0x44, 0x3b, 0xd8, 0x03 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor $1,0xde,$3"
+  -
+    input:
+      bytes: [ 0x48, 0x3b, 0xd6, 0x23 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "zapnot $1,0xde,$3"
diff --git a/tests/MC/Alpha/insn-alpha.s.yaml b/tests/MC/Alpha/insn-alpha.s.yaml
new file mode 100644
index 000000000..54fcbb4c3
--- /dev/null
+++ b/tests/MC/Alpha/insn-alpha.s.yaml
@@ -0,0 +1,1783 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x03, 0x00, 0x22, 0x40 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "addl $1,$2,$3"
+  -
+    input:
+      bytes: [ 0x03, 0xd0, 0x3b, 0x40 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "addl $1,0xde,$3"
+  -
+    input:
+      bytes: [ 0x03, 0x04, 0x22, 0x40 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "addq $1,$2,$3"
+  -
+    input:
+      bytes: [ 0x03, 0xd4, 0x3b, 0x40 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "addq $1,0xde,$3"
+  -
+    input:
+      bytes: [ 0x03, 0xb0, 0x22, 0x58 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "adds/su $f1,$f10,$f11"
+  -
+    input:
+      bytes: [ 0x03, 0xb4, 0x22, 0x58 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "addt/su $f1,$f10,$f11"
+  -
+    input:
+      bytes: [ 0x03, 0x00, 0x22, 0x44 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "and $1,$2,$3"
+  -
+    input:
+      bytes: [ 0x03, 0xd0, 0x3b, 0x44 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "and $1,0xde,$3"
+  -
+    input:
+      bytes: [ 0xfc, 0x3f, 0x20, 0xe4 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "beq $1,0xfffffffffffffff4"
+  -
+    input:
+      bytes: [ 0xfc, 0x3f, 0x20, 0xf8 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bge $1,0xfffffffffffffff4"
+  -
+    input:
+      bytes: [ 0xfc, 0x3f, 0x20, 0xfc ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bgt $1,0xfffffffffffffff4"
+  -
+    input:
+      bytes: [ 0x03, 0x01, 0x22, 0x44 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bic $1,$2,$3"
+  -
+    input:
+      bytes: [ 0x03, 0xd1, 0x3b, 0x44 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bic $1,0xde,$3"
+  -
+    input:
+      bytes: [ 0x03, 0x04, 0x22, 0x44 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bis $1,$2,$3"
+  -
+    input:
+      bytes: [ 0x03, 0xd4, 0x3b, 0x44 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bis $1,0xde,$3"
+  -
+    input:
+      bytes: [ 0xfc, 0x3f, 0x20, 0xe0 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "blbc $1,0xfffffffffffffff4"
+  -
+    input:
+      bytes: [ 0xfc, 0x3f, 0x20, 0xf0 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "blbs $1,0xfffffffffffffff4"
+  -
+    input:
+      bytes: [ 0xfc, 0x3f, 0x20, 0xec ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ble $1,0xfffffffffffffff4"
+  -
+    input:
+      bytes: [ 0xfc, 0x3f, 0x20, 0xe8 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "blt $1,0xfffffffffffffff4"
+  -
+    input:
+      bytes: [ 0xfc, 0x3f, 0x20, 0xf4 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bne $1,0xfffffffffffffff4"
+  -
+    input:
+      bytes: [ 0xfc, 0x3f, 0xe0, 0xc3 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "br $31,0xfffffffffffffff4"
+  -
+    input:
+      bytes: [ 0xfc, 0x3f, 0x40, 0xd3 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bsr $26,$0xfffffffffffffff4 ..ng"
+  -
+    input:
+      bytes: [ 0x83, 0x04, 0x22, 0x44 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmoveq $1,$2,$3"
+  -
+    input:
+      bytes: [ 0xc3, 0x08, 0x22, 0x44 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmovge $1,$2,$3"
+  -
+    input:
+      bytes: [ 0xc3, 0x0c, 0x22, 0x44 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmovgt $1,$2,$3"
+  -
+    input:
+      bytes: [ 0xc3, 0x02, 0x22, 0x44 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmovlbc $1,$2,$3"
+  -
+    input:
+      bytes: [ 0x83, 0x02, 0x22, 0x44 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmovlbs $1,$2,$3"
+  -
+    input:
+      bytes: [ 0x83, 0x0c, 0x22, 0x44 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmovle $1,$2,$3"
+  -
+    input:
+      bytes: [ 0x83, 0x08, 0x22, 0x44 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmovlt $1,$2,$3"
+  -
+    input:
+      bytes: [ 0xc3, 0x04, 0x22, 0x44 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmovne $1,$2,$3"
+  -
+    input:
+      bytes: [ 0xe3, 0x01, 0x22, 0x40 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpbge $1,$2,$3"
+  -
+    input:
+      bytes: [ 0xe3, 0xd1, 0x3b, 0x40 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpbge $1,0xde,$3"
+  -
+    input:
+      bytes: [ 0xa3, 0x05, 0x22, 0x40 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpeq $1,$2,$3"
+  -
+    input:
+      bytes: [ 0xa3, 0xd5, 0x3b, 0x40 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpeq $1,0xde,$3"
+  -
+    input:
+      bytes: [ 0xa3, 0x0d, 0x22, 0x40 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmple $1,$2,$3"
+  -
+    input:
+      bytes: [ 0xa3, 0xdd, 0x3b, 0x40 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmple $1,0xde,$3"
+  -
+    input:
+      bytes: [ 0xa3, 0x09, 0x22, 0x40 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmplt $1,$2,$3"
+  -
+    input:
+      bytes: [ 0xa3, 0xd9, 0x3b, 0x40 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmplt $1,0xde,$3"
+  -
+    input:
+      bytes: [ 0xa3, 0xb4, 0x22, 0x58 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpteq/su $f1,$f10,$f11"
+  -
+    input:
+      bytes: [ 0xe3, 0xb4, 0x22, 0x58 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmptle/su $f1,$f10,$f11"
+  -
+    input:
+      bytes: [ 0xc3, 0xb4, 0x22, 0x58 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmptlt/su $f1,$f10,$f11"
+  -
+    input:
+      bytes: [ 0x83, 0xb4, 0x22, 0x58 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmptun/su $f1,$f10,$f11"
+  -
+    input:
+      bytes: [ 0xa3, 0x07, 0x22, 0x40 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpule $1,$2,$3"
+  -
+    input:
+      bytes: [ 0xa3, 0xd7, 0x3b, 0x40 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpule $1,0xde,$3"
+  -
+    input:
+      bytes: [ 0xa3, 0x03, 0x22, 0x40 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpult $1,$2,$3"
+  -
+    input:
+      bytes: [ 0xa3, 0xd3, 0x3b, 0x40 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpult $1,0xde,$3"
+  -
+    input:
+      bytes: [ 0x43, 0x04, 0x22, 0x5c ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cpyse $f1,$f10,$f11"
+  -
+    input:
+      bytes: [ 0x23, 0x04, 0x22, 0x5c ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cpysn $f1,$f10,$f11"
+  -
+    input:
+      bytes: [ 0x03, 0x04, 0x22, 0x5c ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cpys $f1,$f10,$f11"
+  -
+    input:
+      bytes: [ 0x42, 0x06, 0xe1, 0x73 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ctlz $1,$2"
+  -
+    input:
+      bytes: [ 0x02, 0x06, 0xe1, 0x73 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ctpop $1,$2"
+  -
+    input:
+      bytes: [ 0x62, 0x06, 0xe1, 0x73 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cttz $1,$2"
+  -
+    input:
+      bytes: [ 0x82, 0xf7, 0xe1, 0x5b ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cvtqs/sui $f1,$f10"
+  -
+    input:
+      bytes: [ 0xc2, 0xf7, 0xe1, 0x5b ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cvtqt/sui $f1,$f10"
+  -
+    input:
+      bytes: [ 0x82, 0xd5, 0xe1, 0x5b ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cvtst/s $f1,$f10"
+  -
+    input:
+      bytes: [ 0xe2, 0xa5, 0xe1, 0x5b ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cvttq/svc $f1,$f10"
+  -
+    input:
+      bytes: [ 0x82, 0xf5, 0xe1, 0x5b ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cvtts/sui $f1,$f10"
+  -
+    input:
+      bytes: [ 0x63, 0xb0, 0x22, 0x58 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "divs/su $f1,$f10,$f11"
+  -
+    input:
+      bytes: [ 0x63, 0xb4, 0x22, 0x58 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "divt/su $f1,$f10,$f11"
+  -
+    input:
+      bytes: [ 0x00, 0xe8, 0xe1, 0x63 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ecb ($1)"
+  -
+    input:
+      bytes: [ 0x03, 0x09, 0x22, 0x44 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "eqv $1,$2,$3"
+  -
+    input:
+      bytes: [ 0x03, 0xd9, 0x3b, 0x44 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "eqv $1,0xde,$3"
+  -
+    input:
+      bytes: [ 0x00, 0x04, 0x00, 0x60 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "excb"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0x22, 0x48 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "extbl $1,$2,$3"
+  -
+    input:
+      bytes: [ 0xc3, 0xd0, 0x3b, 0x48 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "extbl $1,0xde,$3"
+  -
+    input:
+      bytes: [ 0x43, 0x0d, 0x22, 0x48 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "extlh $1,$2,$3"
+  -
+    input:
+      bytes: [ 0x43, 0xdd, 0x3b, 0x48 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "extlh $1,0xde,$3"
+  -
+    input:
+      bytes: [ 0xc3, 0x04, 0x22, 0x48 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "extll $1,$2,$3"
+  -
+    input:
+      bytes: [ 0xc3, 0xd4, 0x3b, 0x48 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "extll $1,0xde,$3"
+  -
+    input:
+      bytes: [ 0x43, 0x0f, 0x22, 0x48 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "extqh $1,$2,$3"
+  -
+    input:
+      bytes: [ 0x43, 0xdf, 0x3b, 0x48 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "extqh $1,0xde,$3"
+  -
+    input:
+      bytes: [ 0xc3, 0x06, 0x22, 0x48 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "extql $1,$2,$3"
+  -
+    input:
+      bytes: [ 0xc3, 0xd6, 0x3b, 0x48 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "extql $1,0xde,$3"
+  -
+    input:
+      bytes: [ 0x43, 0x0b, 0x22, 0x48 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "extwh $1,$2,$3"
+  -
+    input:
+      bytes: [ 0x43, 0xdb, 0x3b, 0x48 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "extwh $1,0xde,$3"
+  -
+    input:
+      bytes: [ 0xc3, 0x02, 0x22, 0x48 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "extwl $1,$2,$3"
+  -
+    input:
+      bytes: [ 0xc3, 0xd2, 0x3b, 0x48 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "extwl $1,0xde,$3"
+  -
+    input:
+      bytes: [ 0xfc, 0x3f, 0x20, 0xc4 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fbeq $f1,0xfffffffffffffff4"
+  -
+    input:
+      bytes: [ 0xfc, 0x3f, 0x20, 0xd8 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fbge $f1,0xfffffffffffffff4"
+  -
+    input:
+      bytes: [ 0xfc, 0x3f, 0x20, 0xdc ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fbgt $f1,0xfffffffffffffff4"
+  -
+    input:
+      bytes: [ 0xfc, 0x3f, 0x20, 0xcc ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fble $f1,0xfffffffffffffff4"
+  -
+    input:
+      bytes: [ 0xfc, 0x3f, 0x20, 0xc8 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fblt $f1,0xfffffffffffffff4"
+  -
+    input:
+      bytes: [ 0xfc, 0x3f, 0x20, 0xd4 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fbne $f1,0xfffffffffffffff4"
+  -
+    input:
+      bytes: [ 0x43, 0x05, 0x22, 0x5c ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmoveq ,$f10,$f11"
+  -
+    input:
+      bytes: [ 0xa3, 0x05, 0x22, 0x5c ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmovge ,$f10,$f11"
+  -
+    input:
+      bytes: [ 0xe3, 0x05, 0x22, 0x5c ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmovgt ,$f10,$f11"
+  -
+    input:
+      bytes: [ 0xc3, 0x05, 0x22, 0x5c ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmovle ,$f10,$f11"
+  -
+    input:
+      bytes: [ 0x83, 0x05, 0x22, 0x5c ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmovlt ,$f10,$f11"
+  -
+    input:
+      bytes: [ 0x63, 0x05, 0x22, 0x5c ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmovne ,$f10,$f11"
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0xe1, 0x63 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fetch ($1)"
+  -
+    input:
+      bytes: [ 0x00, 0xa0, 0xe1, 0x63 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fetch_m ($1)"
+  -
+    input:
+      bytes: [ 0x01, 0x0f, 0x3f, 0x70 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ftois $f1,$1"
+  -
+    input:
+      bytes: [ 0x01, 0x0e, 0x3f, 0x70 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ftoit $f1,$1"
+  -
+    input:
+      bytes: [ 0x63, 0x01, 0x22, 0x48 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "insbl $1,$2,$3"
+  -
+    input:
+      bytes: [ 0x63, 0xd1, 0x3b, 0x48 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "insbl $1,0xde,$3"
+  -
+    input:
+      bytes: [ 0xe3, 0x0c, 0x22, 0x48 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "inslh $1,$2,$3"
+  -
+    input:
+      bytes: [ 0xe3, 0xdc, 0x3b, 0x48 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "inslh $1,0xde,$3"
+  -
+    input:
+      bytes: [ 0x63, 0x05, 0x22, 0x48 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "insll $1,$2,$3"
+  -
+    input:
+      bytes: [ 0x63, 0xd5, 0x3b, 0x48 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "insll $1,0xde,$3"
+  -
+    input:
+      bytes: [ 0xe3, 0x0e, 0x22, 0x48 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "insqh $1,$2,$3"
+  -
+    input:
+      bytes: [ 0xe3, 0xde, 0x3b, 0x48 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "insqh $1,0xde,$3"
+  -
+    input:
+      bytes: [ 0x63, 0x07, 0x22, 0x48 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "insql $1,$2,$3"
+  -
+    input:
+      bytes: [ 0x63, 0xd7, 0x3b, 0x48 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "insql $1,0xde,$3"
+  -
+    input:
+      bytes: [ 0xe3, 0x0a, 0x22, 0x48 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "inswh $1,$2,$3"
+  -
+    input:
+      bytes: [ 0xe3, 0xda, 0x3b, 0x48 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "inswh $1,0xde,$3"
+  -
+    input:
+      bytes: [ 0x63, 0x03, 0x22, 0x48 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "inswl $1,$2,$3"
+  -
+    input:
+      bytes: [ 0x63, 0xd3, 0x3b, 0x48 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "inswl $1,0xde,$3"
+  -
+    input:
+      bytes: [ 0x81, 0x00, 0x3f, 0x50 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "itofs $1,$f1"
+  -
+    input:
+      bytes: [ 0x81, 0x04, 0x3f, 0x50 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "itoft $1,$f1"
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0xfa, 0x6b ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "jmp $31,$12,0"
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0x5b, 0x6b ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "jsr $26,($27),0"
+  -
+    input:
+      bytes: [ 0xff, 0xcf, 0x22, 0x68 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "jsr_coroutine $1,($2),0xfff"
+  -
+    input:
+      bytes: [ 0x10, 0x00, 0x22, 0x20 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "lda $1,0x10($2)"
+  -
+    input:
+      bytes: [ 0x10, 0x00, 0x22, 0x24 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldah $1,0x10($2)"
+  -
+    input:
+      bytes: [ 0x10, 0x00, 0x22, 0x28 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldbu $1,0x10($2)"
+  -
+    input:
+      bytes: [ 0x10, 0x00, 0x22, 0xa0 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldl $1,0x10($2)"
+  -
+    input:
+      bytes: [ 0x10, 0x00, 0x22, 0xa8 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldl_l $1,0x10($2)"
+  -
+    input:
+      bytes: [ 0x10, 0x00, 0x22, 0xa4 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldq $1,0x10($2)"
+  -
+    input:
+      bytes: [ 0x10, 0x00, 0x22, 0xac ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldq_l $1,0x10($2)"
+  -
+    input:
+      bytes: [ 0x10, 0x00, 0x22, 0x2c ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldq_u $1,0x10($2)"
+  -
+    input:
+      bytes: [ 0x10, 0x00, 0x22, 0x88 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "lds $f1,0x10($2)"
+  -
+    input:
+      bytes: [ 0x10, 0x00, 0x22, 0x8c ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldt $f1,0x10($2)"
+  -
+    input:
+      bytes: [ 0x10, 0x00, 0x22, 0x30 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldwu $1,0x10($2)"
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0x00, 0x60 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mb"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x22, 0x48 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mskbl $1,$2,$3"
+  -
+    input:
+      bytes: [ 0x43, 0xd0, 0x3b, 0x48 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mskbl $1,0xde,$3"
+  -
+    input:
+      bytes: [ 0x43, 0x0c, 0x22, 0x48 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "msklh $1,$2,$3"
+  -
+    input:
+      bytes: [ 0x43, 0xdc, 0x3b, 0x48 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "msklh $1,0xde,$3"
+  -
+    input:
+      bytes: [ 0x43, 0x04, 0x22, 0x48 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mskll $1,$2,$3"
+  -
+    input:
+      bytes: [ 0x43, 0xd4, 0x3b, 0x48 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mskll $1,0xde,$3"
+  -
+    input:
+      bytes: [ 0x43, 0x0e, 0x22, 0x48 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mskqh $1,$2,$3"
+  -
+    input:
+      bytes: [ 0x43, 0xde, 0x3b, 0x48 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mskqh $1,0xde,$3"
+  -
+    input:
+      bytes: [ 0x43, 0x06, 0x22, 0x48 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mskql $1,$2,$3"
+  -
+    input:
+      bytes: [ 0x43, 0xd6, 0x3b, 0x48 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mskql $1,0xde,$3"
+  -
+    input:
+      bytes: [ 0x43, 0x0a, 0x22, 0x48 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mskwh $1,$2,$3"
+  -
+    input:
+      bytes: [ 0x43, 0xda, 0x3b, 0x48 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mskwh $1,0xde,$3"
+  -
+    input:
+      bytes: [ 0x43, 0x02, 0x22, 0x48 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mskwl $1,$2,$3"
+  -
+    input:
+      bytes: [ 0x43, 0xd2, 0x3b, 0x48 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mskwl $1,0xde,$3"
+  -
+    input:
+      bytes: [ 0x03, 0x00, 0x22, 0x4c ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mull $1,$2,$3"
+  -
+    input:
+      bytes: [ 0x03, 0xd0, 0x3b, 0x4c ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mull $1,0xde,$3"
+  -
+    input:
+      bytes: [ 0x03, 0x04, 0x22, 0x4c ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulq $1,$2,$3"
+  -
+    input:
+      bytes: [ 0x03, 0xd4, 0x3b, 0x4c ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulq $1,0xde,$3"
+  -
+    input:
+      bytes: [ 0x43, 0xb0, 0x22, 0x58 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "muls/su $f1,$f10,$f11"
+  -
+    input:
+      bytes: [ 0x43, 0xb4, 0x22, 0x58 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mult/su $f1,$f10,$f11"
+  -
+    input:
+      bytes: [ 0x03, 0x05, 0x22, 0x44 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ornot $1,$2,$3"
+  -
+    input:
+      bytes: [ 0x03, 0xd5, 0x3b, 0x44 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ornot $1,0xde,$3"
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x20, 0x60 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "rc $1"
+  -
+    input:
+      bytes: [ 0x01, 0x80, 0xfa, 0x6b ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ret $31,($26),1"
+  -
+    input:
+      bytes: [ 0x00, 0xc0, 0x1f, 0x60 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "rpcc $0"
+  -
+    input:
+      bytes: [ 0x00, 0xf0, 0x20, 0x60 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "rs $1"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x22, 0x40 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "s4addl $1,$2,$3"
+  -
+    input:
+      bytes: [ 0x43, 0xd0, 0x3b, 0x40 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "s4addl $1,0xde,$3"
+  -
+    input:
+      bytes: [ 0x63, 0x01, 0x22, 0x40 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "s4subl $1,$2,$3"
+  -
+    input:
+      bytes: [ 0x63, 0xd1, 0x3b, 0x40 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "s4subl $1,0xde,$3"
+  -
+    input:
+      bytes: [ 0x63, 0x05, 0x22, 0x40 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "s4subq $1,$2,$3"
+  -
+    input:
+      bytes: [ 0x63, 0xd5, 0x3b, 0x40 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "s4subq $1,0xde,$3"
+  -
+    input:
+      bytes: [ 0x43, 0x02, 0x22, 0x40 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "s8addl $1,$2,$3"
+  -
+    input:
+      bytes: [ 0x43, 0xd2, 0x3b, 0x40 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "s8addl $1,0xde,$3"
+  -
+    input:
+      bytes: [ 0x43, 0x06, 0x22, 0x40 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "s8addq $1,$2,$3"
+  -
+    input:
+      bytes: [ 0x43, 0xd6, 0x3b, 0x40 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "s8addq $1,0xde,$3"
+  -
+    input:
+      bytes: [ 0x63, 0x03, 0x22, 0x40 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "s8subl $1,$2,$3"
+  -
+    input:
+      bytes: [ 0x63, 0xd3, 0x3b, 0x40 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "s8subl $1,0xde,$3"
+  -
+    input:
+      bytes: [ 0x63, 0x07, 0x22, 0x40 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "s8subq $1,$2,$3"
+  -
+    input:
+      bytes: [ 0x63, 0xd7, 0x3b, 0x40 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "s8subq $1,0xde,$3"
+  -
+    input:
+      bytes: [ 0x02, 0x00, 0xe1, 0x73 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sextb $1,$2"
+  -
+    input:
+      bytes: [ 0x22, 0x00, 0xe1, 0x73 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sextw $1,$2"
+  -
+    input:
+      bytes: [ 0x23, 0x07, 0x22, 0x48 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sll $1,$2,$3"
+  -
+    input:
+      bytes: [ 0x23, 0xd7, 0x3b, 0x48 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sll $1,0xde,$3"
+  -
+    input:
+      bytes: [ 0x62, 0xb1, 0xe1, 0x53 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrts/su $f1,$f10"
+  -
+    input:
+      bytes: [ 0x62, 0xb5, 0xe1, 0x53 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrtt/su $f1,$f10"
+  -
+    input:
+      bytes: [ 0x83, 0x07, 0x22, 0x48 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sra $1,$2,$3"
+  -
+    input:
+      bytes: [ 0x83, 0xd7, 0x3b, 0x48 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sra $1,0xde,$3"
+  -
+    input:
+      bytes: [ 0x83, 0x06, 0x22, 0x48 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "srl $1,$2,$3"
+  -
+    input:
+      bytes: [ 0x83, 0xd6, 0x3b, 0x48 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "srl $1,0xde,$3"
+  -
+    input:
+      bytes: [ 0x10, 0x00, 0x22, 0x38 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "stb $1, 0x10($2)"
+  -
+    input:
+      bytes: [ 0x10, 0x00, 0x22, 0xb0 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "stl $1,0x10($2)"
+  -
+    input:
+      bytes: [ 0x10, 0x00, 0x22, 0xb8 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "stl_c $1,0x10($2)"
+  -
+    input:
+      bytes: [ 0x10, 0x00, 0x22, 0xb4 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "stq $1,0x10($2)"
+  -
+    input:
+      bytes: [ 0x10, 0x00, 0x22, 0xbc ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "stq_c $1,0x10($2)"
+  -
+    input:
+      bytes: [ 0x10, 0x00, 0x22, 0x3c ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "stq_u $1, 0x10($2)"
+  -
+    input:
+      bytes: [ 0x10, 0x00, 0x22, 0x98 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sts $f1,0x10($2)"
+  -
+    input:
+      bytes: [ 0x10, 0x00, 0x22, 0x9c ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "stt $f1,0x10($2)"
+  -
+    input:
+      bytes: [ 0x10, 0x00, 0x22, 0x34 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "stw $1,0x10($2)"
+  -
+    input:
+      bytes: [ 0x23, 0x01, 0x22, 0x40 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "subl $1,$2,$3"
+  -
+    input:
+      bytes: [ 0x23, 0xd1, 0x3b, 0x40 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "subl $1,0xde,$3"
+  -
+    input:
+      bytes: [ 0x23, 0x05, 0x22, 0x40 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "subq $1,$2,$3"
+  -
+    input:
+      bytes: [ 0x23, 0xd5, 0x3b, 0x40 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "subq $1,0xde,$3"
+  -
+    input:
+      bytes: [ 0x23, 0xb0, 0x22, 0x58 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "subs/su $f1,$f10,$f11"
+  -
+    input:
+      bytes: [ 0x23, 0xb4, 0x22, 0x58 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "subt/su $f1,$f10,$f11"
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x00, 0x60 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "trapb"
+  -
+    input:
+      bytes: [ 0x03, 0x06, 0x22, 0x4c ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "umulh $1,$2,$3"
+  -
+    input:
+      bytes: [ 0x03, 0xd6, 0x3b, 0x4c ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "umulh $1,0xde,$3"
+  -
+    input:
+      bytes: [ 0x00, 0xf8, 0xe1, 0x63 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "wh64 ($1)"
+  -
+    input:
+      bytes: [ 0x00, 0xfc, 0xe1, 0x63 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "wh64en ($1)"
+  -
+    input:
+      bytes: [ 0x00, 0x44, 0x00, 0x60 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "wmb"
+  -
+    input:
+      bytes: [ 0x03, 0x08, 0x22, 0x44 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor $1,$2,$3"
+  -
+    input:
+      bytes: [ 0x03, 0xd8, 0x3b, 0x44 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor $1,0xde,$3"
+  -
+    input:
+      bytes: [ 0x23, 0xd6, 0x3b, 0x48 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "zapnot $1,0xde,$3"
diff --git a/tests/MC/BPF/classic-all.yaml b/tests/MC/BPF/classic-all.yaml
new file mode 100644
index 000000000..6502492e5
--- /dev/null
+++ b/tests/MC/BPF/classic-all.yaml
@@ -0,0 +1,451 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x98, 0xab, 0x08, 0x02, 0x0e, 0x45 ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_BPF_CLASSIC" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld 0x450e0208"
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0x44, 0x49, 0x1f, 0xfe, 0xd3, 0x93 ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_BPF_CLASSIC" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldx 0x93d3fe1f"
+  -
+    input:
+      bytes: [ 0x04, 0x00, 0xda, 0x23, 0x71, 0xc5, 0x51, 0x42 ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_BPF_CLASSIC" ]
+    expected:
+      insns:
+        -
+          asm_text: "add 0x4251c571"
+  -
+    input:
+      bytes: [ 0x05, 0x00, 0xd4, 0xbd, 0x37, 0xc8, 0x2c, 0xd5 ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_BPF_CLASSIC" ]
+    expected:
+      insns:
+        -
+          asm_text: "jmp +0xd52cc837"
+  -
+    input:
+      bytes: [ 0x06, 0x00, 0xa7, 0x84, 0x25, 0x40, 0x28, 0x1c ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_BPF_CLASSIC" ]
+    expected:
+      insns:
+        -
+          asm_text: "ret 0x1c284025"
+  -
+    input:
+      bytes: [ 0x07, 0x00, 0xe8, 0xe8, 0x48, 0xe2, 0x84, 0x2a ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_BPF_CLASSIC" ]
+    expected:
+      insns:
+        -
+          asm_text: "tax"
+  -
+    input:
+      bytes: [ 0x0c, 0x00, 0x55, 0x8c, 0x32, 0xd8, 0x21, 0xe8 ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_BPF_CLASSIC" ]
+    expected:
+      insns:
+        -
+          asm_text: "add x"
+  -
+    input:
+      bytes: [ 0x0e, 0x00, 0xd4, 0x24, 0x96, 0xf7, 0xa1, 0x49 ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_BPF_CLASSIC" ]
+    expected:
+      insns:
+        -
+          asm_text: "ret x"
+  -
+    input:
+      bytes: [ 0x14, 0x00, 0x6a, 0xc8, 0x14, 0x50, 0x2d, 0x69 ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_BPF_CLASSIC" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub 0x692d5014"
+  -
+    input:
+      bytes: [ 0x15, 0x00, 0xc3, 0x39, 0x6e, 0x4f, 0x37, 0x18 ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_BPF_CLASSIC" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq 0x18374f6e, +0xc3, +0x39"
+  -
+    input:
+      bytes: [ 0x16, 0x00, 0x57, 0xd2, 0xc4, 0xd4, 0x8a, 0x51 ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_BPF_CLASSIC" ]
+    expected:
+      insns:
+        -
+          asm_text: "ret a"
+  -
+    input:
+      bytes: [ 0x1c, 0x00, 0xd1, 0x51, 0x90, 0x8a, 0x8d, 0xea ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_BPF_CLASSIC" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub x"
+  -
+    input:
+      bytes: [ 0x1d, 0x00, 0x2e, 0xa8, 0xbc, 0xa7, 0xd5, 0x3a ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_BPF_CLASSIC" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq x, +0x2e, +0xa8"
+  -
+    input:
+      bytes: [ 0x20, 0x00, 0x9a, 0x43, 0x93, 0x27, 0xec, 0xf7 ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_BPF_CLASSIC" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld [0xf7ec2793]"
+  -
+    input:
+      bytes: [ 0x24, 0x00, 0x0f, 0x46, 0xbe, 0xe5, 0xd2, 0x4a ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_BPF_CLASSIC" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul 0x4ad2e5be"
+  -
+    input:
+      bytes: [ 0x25, 0x00, 0x8c, 0x80, 0xc1, 0x03, 0x38, 0x61 ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_BPF_CLASSIC" ]
+    expected:
+      insns:
+        -
+          asm_text: "jgt 0x613803c1, +0x8c, +0x80"
+  -
+    input:
+      bytes: [ 0x28, 0x00, 0xc3, 0x05, 0x73, 0x01, 0x39, 0xbd ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_BPF_CLASSIC" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldh [0xbd390173]"
+  -
+    input:
+      bytes: [ 0x2c, 0x00, 0x7a, 0x3d, 0xad, 0x19, 0xe7, 0xcc ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_BPF_CLASSIC" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul x"
+  -
+    input:
+      bytes: [ 0x2d, 0x00, 0xd9, 0xc6, 0xf7, 0x72, 0x9a, 0x9d ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_BPF_CLASSIC" ]
+    expected:
+      insns:
+        -
+          asm_text: "jgt x, +0xd9, +0xc6"
+  -
+    input:
+      bytes: [ 0x30, 0x00, 0x22, 0x29, 0x29, 0x5b, 0xb5, 0x87 ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_BPF_CLASSIC" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldb [0x87b55b29]"
+  -
+    input:
+      bytes: [ 0x34, 0x00, 0xa8, 0xfa, 0x6a, 0x92, 0xa2, 0xa8 ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_BPF_CLASSIC" ]
+    expected:
+      insns:
+        -
+          asm_text: "div 0xa8a2926a"
+  -
+    input:
+      bytes: [ 0x35, 0x00, 0x24, 0xdb, 0x58, 0x41, 0xa8, 0x58 ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_BPF_CLASSIC" ]
+    expected:
+      insns:
+        -
+          asm_text: "jge 0x58a84158, +0x24, +0xdb"
+  -
+    input:
+      bytes: [ 0x3c, 0x00, 0x41, 0xa6, 0xd5, 0x66, 0x8a, 0xdd ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_BPF_CLASSIC" ]
+    expected:
+      insns:
+        -
+          asm_text: "div x"
+  -
+    input:
+      bytes: [ 0x3d, 0x00, 0xe4, 0xbc, 0x40, 0xb3, 0x4d, 0x84 ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_BPF_CLASSIC" ]
+    expected:
+      insns:
+        -
+          asm_text: "jge x, +0xe4, +0xbc"
+  -
+    input:
+      bytes: [ 0x40, 0x00, 0xf1, 0xa0, 0xd9, 0x89, 0x72, 0x25 ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_BPF_CLASSIC" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld [x+0x257289d9]"
+  -
+    input:
+      bytes: [ 0x44, 0x00, 0x8d, 0xf8, 0x49, 0xdb, 0x10, 0x82 ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_BPF_CLASSIC" ]
+    expected:
+      insns:
+        -
+          asm_text: "or 0x8210db49"
+  -
+    input:
+      bytes: [ 0x45, 0x00, 0x43, 0xfc, 0x7d, 0xa1, 0x34, 0xed ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_BPF_CLASSIC" ]
+    expected:
+      insns:
+        -
+          asm_text: "jset 0xed34a17d, +0x43, +0xfc"
+  -
+    input:
+      bytes: [ 0x48, 0x00, 0x6b, 0x89, 0x0b, 0xca, 0xfb, 0x1b ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_BPF_CLASSIC" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldh [x+0x1bfbca0b]"
+  -
+    input:
+      bytes: [ 0x4c, 0x00, 0xc9, 0xff, 0x36, 0xe9, 0x2a, 0xe7 ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_BPF_CLASSIC" ]
+    expected:
+      insns:
+        -
+          asm_text: "or x"
+  -
+    input:
+      bytes: [ 0x4d, 0x00, 0x0d, 0xaa, 0xc3, 0x50, 0xea, 0x40 ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_BPF_CLASSIC" ]
+    expected:
+      insns:
+        -
+          asm_text: "jset x, +0xd, +0xaa"
+  -
+    input:
+      bytes: [ 0x50, 0x00, 0xd9, 0xf3, 0xda, 0xa7, 0xd9, 0xb1 ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_BPF_CLASSIC" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldb [x+0xb1d9a7da]"
+  -
+    input:
+      bytes: [ 0x54, 0x00, 0x14, 0x82, 0x29, 0x82, 0x6c, 0x06 ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_BPF_CLASSIC" ]
+    expected:
+      insns:
+        -
+          asm_text: "and 0x66c8229"
+  -
+    input:
+      bytes: [ 0x5c, 0x00, 0x80, 0x37, 0x5f, 0x52, 0xc0, 0x84 ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_BPF_CLASSIC" ]
+    expected:
+      insns:
+        -
+          asm_text: "and x"
+  -
+    input:
+      bytes: [ 0x60, 0x00, 0xba, 0x4e, 0xb5, 0x3f, 0xdc, 0xd8 ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_BPF_CLASSIC" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld m[0xd8dc3fb5]"
+  -
+    input:
+      bytes: [ 0x61, 0x00, 0x06, 0xd9, 0xcd, 0x84, 0x58, 0x94 ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_BPF_CLASSIC" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldx m[0x945884cd]"
+  -
+    input:
+      bytes: [ 0x62, 0x00, 0x2c, 0x44, 0xdf, 0x71, 0x48, 0x1b ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_BPF_CLASSIC" ]
+    expected:
+      insns:
+        -
+          asm_text: "st m[0x1b4871df]"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0xc9, 0x53, 0x7f, 0x80, 0x89, 0x2d ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_BPF_CLASSIC" ]
+    expected:
+      insns:
+        -
+          asm_text: "stx m[0x2d89807f]"
+  -
+    input:
+      bytes: [ 0x64, 0x00, 0x8a, 0xe5, 0xf0, 0x0c, 0xca, 0xfd ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_BPF_CLASSIC" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsh 0xfdca0cf0"
+  -
+    input:
+      bytes: [ 0x6c, 0x00, 0xd3, 0x85, 0xc1, 0x96, 0xb1, 0x48 ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_BPF_CLASSIC" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsh x"
+  -
+    input:
+      bytes: [ 0x74, 0x00, 0xfa, 0x6f, 0xe9, 0xbe, 0xde, 0x7e ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_BPF_CLASSIC" ]
+    expected:
+      insns:
+        -
+          asm_text: "rsh 0x7edebee9"
+  -
+    input:
+      bytes: [ 0x7c, 0x00, 0x0d, 0x89, 0xed, 0x17, 0x7d, 0xcd ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_BPF_CLASSIC" ]
+    expected:
+      insns:
+        -
+          asm_text: "rsh x"
+  -
+    input:
+      bytes: [ 0x80, 0x00, 0x70, 0x62, 0x0e, 0x61, 0x1b, 0x94 ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_BPF_CLASSIC" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld #len"
+  -
+    input:
+      bytes: [ 0x81, 0x00, 0xa0, 0x03, 0xa2, 0x5c, 0x1f, 0x2a ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_BPF_CLASSIC" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldx #len"
+  -
+    input:
+      bytes: [ 0x84, 0x00, 0x4f, 0x0f, 0xc9, 0x4a, 0x72, 0xff ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_BPF_CLASSIC" ]
+    expected:
+      insns:
+        -
+          asm_text: "neg"
+  -
+    input:
+      bytes: [ 0x87, 0x00, 0x17, 0x2a, 0x9a, 0xd6, 0xb6, 0x8f ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_BPF_CLASSIC" ]
+    expected:
+      insns:
+        -
+          asm_text: "txa"
+  -
+    input:
+      bytes: [ 0x94, 0x00, 0x85, 0x0c, 0x29, 0xb2, 0xbe, 0x83 ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_BPF_CLASSIC" ]
+    expected:
+      insns:
+        -
+          asm_text: "mod 0x83beb229"
+  -
+    input:
+      bytes: [ 0x9c, 0x00, 0x30, 0x3f, 0x9d, 0x33, 0x89, 0x50 ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_BPF_CLASSIC" ]
+    expected:
+      insns:
+        -
+          asm_text: "mod x"
+  -
+    input:
+      bytes: [ 0xa1, 0x00, 0x53, 0x03, 0xdd, 0xdf, 0xd4, 0xe3 ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_BPF_CLASSIC" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldx 4*([0xe3d4dfdd]&0xf)"
+  -
+    input:
+      bytes: [ 0xa4, 0x00, 0x66, 0x8f, 0x3c, 0xde, 0xe2, 0x4d ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_BPF_CLASSIC" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor 0x4de2de3c"
+  -
+    input:
+      bytes: [ 0xac, 0x00, 0x02, 0x2f, 0x1e, 0xe3, 0x2e, 0x84 ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_LITTLE_ENDIAN", "CS_MODE_BPF_CLASSIC" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor x"
diff --git a/tests/MC/BPF/classic-be.yaml b/tests/MC/BPF/classic-be.yaml
new file mode 100644
index 000000000..f62627b2c
--- /dev/null
+++ b/tests/MC/BPF/classic-be.yaml
@@ -0,0 +1,64 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x01, 0x00, 0x00, 0x33, 0x00, 0x0c, 0x11 ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_BPF_CLASSIC" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldx 0x33000c11"
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_BPF_CLASSIC" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld #len"
+  -
+    input:
+      bytes: [ 0x00, 0xa1, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_BPF_CLASSIC" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldx 4*([0x10000000]&0xf)"
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_BPF_CLASSIC" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld m[0x9000000]"
+  -
+    input:
+      bytes: [ 0x00, 0x30, 0x00, 0x00, 0x37, 0x13, 0x03, 0x00 ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_BPF_CLASSIC" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldb [0x37130300]"
+  -
+    input:
+      bytes: [ 0x00, 0x63, 0x00, 0x00, 0x0f, 0x00, 0x30, 0x00 ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_BPF_CLASSIC" ]
+    expected:
+      insns:
+        -
+          asm_text: "stx m[0xf003000]"
+  -
+    input:
+      bytes: [ 0x00, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_BPF_CLASSIC" ]
+    expected:
+      insns:
+        -
+          asm_text: "neg"
diff --git a/tests/MC/BPF/extended-all.yaml b/tests/MC/BPF/extended-all.yaml
new file mode 100644
index 000000000..8140cac33
--- /dev/null
+++ b/tests/MC/BPF/extended-all.yaml
@@ -0,0 +1,874 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x04, 0xb4, 0x97, 0xa8, 0xe8, 0x60, 0x56, 0xe1 ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "add r4, 0xe15660e8"
+  -
+    input:
+      bytes: [ 0x05, 0xc7, 0x71, 0xb0, 0x43, 0x1f, 0xb9, 0xf5 ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "jmp +0xb071"
+  -
+    input:
+      bytes: [ 0x07, 0x76, 0x01, 0x28, 0xc4, 0x09, 0xfe, 0x8b ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "add64 r6, 0x8bfe09c4"
+  -
+    input:
+      bytes: [ 0x0c, 0x42, 0x0a, 0x48, 0x58, 0xc4, 0xef, 0x37 ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "add r2, r4"
+  -
+    input:
+      bytes: [ 0x0f, 0x09, 0x40, 0x54, 0x67, 0x24, 0x2f, 0x88 ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "add64 r9, r0"
+  -
+    input:
+      bytes: [ 0x14, 0xd9, 0xba, 0xb8, 0x6f, 0x07, 0x93, 0x2a ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub r9, 0x2a93076f"
+  -
+    input:
+      bytes: [ 0x15, 0x6a, 0x9f, 0x38, 0x1a, 0x9d, 0xb7, 0x4d ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq r10, 0x4db79d1a, +0x389f"
+  -
+    input:
+      bytes: [ 0x17, 0xc5, 0x60, 0xed, 0x0b, 0xdc, 0xe6, 0x22 ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub64 r5, 0x22e6dc0b"
+  -
+    input:
+      bytes: [ 0x18, 0xa3, 0x5c, 0x14, 0xde, 0xf0, 0xa5, 0xff, 0x9a, 0x7e, 0x10, 0xee, 0xd8, 0xa4, 0x2b, 0x2f ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "lddw r3, 0x2f2ba4d8ffa5f0de"
+  -
+    input:
+      bytes: [ 0x1c, 0x73, 0x68, 0xa4, 0x8b, 0x5b, 0x93, 0x1f ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub r3, r7"
+  -
+    input:
+      bytes: [ 0x1d, 0x21, 0x20, 0x4d, 0xe3, 0x47, 0xaf, 0x1b ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq r1, r2, +0x4d20"
+  -
+    input:
+      bytes: [ 0x1f, 0x06, 0x51, 0x5a, 0x39, 0xb2, 0x10, 0x10 ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub64 r6, r0"
+  -
+    input:
+      bytes: [ 0x20, 0xc7, 0x0c, 0x70, 0xda, 0x41, 0x1a, 0xca ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldw [0xca1a41da]"
+  -
+    input:
+      bytes: [ 0x24, 0xb6, 0x69, 0x66, 0xe3, 0xef, 0xec, 0x25 ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul r6, 0x25ecefe3"
+  -
+    input:
+      bytes: [ 0x25, 0x89, 0xda, 0x53, 0x19, 0x73, 0x8a, 0xc0 ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "jgt r9, 0xc08a7319, +0x53da"
+  -
+    input:
+      bytes: [ 0x27, 0xb1, 0x96, 0x1d, 0xd4, 0xab, 0x2c, 0x8c ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul64 r1, 0x8c2cabd4"
+  -
+    input:
+      bytes: [ 0x28, 0x4e, 0xb0, 0x62, 0xe8, 0x48, 0x0b, 0x0d ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldh [0xd0b48e8]"
+  -
+    input:
+      bytes: [ 0x2c, 0x78, 0x03, 0xf6, 0x29, 0x29, 0x15, 0xfc ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul r8, r7"
+  -
+    input:
+      bytes: [ 0x2d, 0x18, 0x5b, 0xfd, 0x8f, 0x53, 0x3b, 0xf0 ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "jgt r8, r1, +0xfd5b"
+  -
+    input:
+      bytes: [ 0x2f, 0x77, 0xc7, 0xa4, 0x4c, 0x32, 0x73, 0x2a ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul64 r7, r7"
+  -
+    input:
+      bytes: [ 0x30, 0x5f, 0xfe, 0xfc, 0x85, 0x66, 0x7c, 0x4b ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldb [0x4b7c6685]"
+  -
+    input:
+      bytes: [ 0x34, 0x46, 0x49, 0x33, 0xe1, 0x72, 0xd4, 0xcb ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "div r6, 0xcbd472e1"
+  -
+    input:
+      bytes: [ 0x35, 0xa5, 0x42, 0xb9, 0x5b, 0x37, 0xa1, 0x3d ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "jge r5, 0x3da1375b, +0xb942"
+  -
+    input:
+      bytes: [ 0x37, 0x84, 0xd8, 0xba, 0x3b, 0x84, 0x55, 0x1f ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "div64 r4, 0x1f55843b"
+  -
+    input:
+      bytes: [ 0x38, 0x8e, 0x3f, 0xd7, 0x1c, 0x3e, 0x3a, 0x7b ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "lddw [0x7b3a3e1c]"
+  -
+    input:
+      bytes: [ 0x3d, 0x1a, 0xc3, 0x9b, 0x88, 0xa2, 0x3f, 0x65 ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "jge r10, r1, +0x9bc3"
+  -
+    input:
+      bytes: [ 0x3f, 0x36, 0x99, 0x32, 0x7e, 0x07, 0x59, 0x7a ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "div64 r6, r3"
+  -
+    input:
+      bytes: [ 0x40, 0x95, 0xc2, 0x39, 0x6b, 0xe7, 0xd7, 0xc4 ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldw [r9+0xc4d7e76b]"
+  -
+    input:
+      bytes: [ 0x44, 0x16, 0xf7, 0x98, 0xf7, 0x02, 0x92, 0x94 ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "or r6, 0x949202f7"
+  -
+    input:
+      bytes: [ 0x45, 0x12, 0xa2, 0xf2, 0x14, 0xe7, 0x2d, 0x1e ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "jset r2, 0x1e2de714, +0xf2a2"
+  -
+    input:
+      bytes: [ 0x47, 0x36, 0xf4, 0xd5, 0xbe, 0x04, 0x58, 0x4d ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "or64 r6, 0x4d5804be"
+  -
+    input:
+      bytes: [ 0x48, 0x7e, 0xfb, 0x77, 0xeb, 0x0e, 0x5a, 0x0d ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldh [r7+0xd5a0eeb]"
+  -
+    input:
+      bytes: [ 0x4c, 0x81, 0x0a, 0x66, 0xfc, 0x32, 0x61, 0xc4 ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "or r1, r8"
+  -
+    input:
+      bytes: [ 0x4d, 0x10, 0x67, 0x44, 0x4d, 0x3f, 0x4d, 0x8b ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "jset r0, r1, +0x4467"
+  -
+    input:
+      bytes: [ 0x4f, 0x81, 0xeb, 0x6b, 0xde, 0x98, 0x87, 0x64 ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "or64 r1, r8"
+  -
+    input:
+      bytes: [ 0x50, 0x38, 0x80, 0xf8, 0x04, 0x70, 0xd1, 0x6c ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldb [r3+0x6cd17004]"
+  -
+    input:
+      bytes: [ 0x54, 0x40, 0x0a, 0x6a, 0x4a, 0xe8, 0xab, 0xfb ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "and r0, 0xfbabe84a"
+  -
+    input:
+      bytes: [ 0x55, 0xb9, 0xa3, 0x80, 0x90, 0xbc, 0xc8, 0x96 ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne r9, 0x96c8bc90, +0x80a3"
+  -
+    input:
+      bytes: [ 0x57, 0x30, 0x12, 0xe9, 0x7c, 0x06, 0x82, 0x27 ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "and64 r0, 0x2782067c"
+  -
+    input:
+      bytes: [ 0x58, 0x6d, 0xf1, 0x05, 0xd3, 0x50, 0x4b, 0xc0 ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "lddw [r6+0xc04b50d3]"
+  -
+    input:
+      bytes: [ 0x5c, 0x02, 0x95, 0xb2, 0xbd, 0x3f, 0x38, 0x37 ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "and r2, r0"
+  -
+    input:
+      bytes: [ 0x5d, 0x56, 0xa3, 0x4c, 0x2a, 0xc8, 0x4a, 0xc5 ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne r6, r5, +0x4ca3"
+  -
+    input:
+      bytes: [ 0x5f, 0x59, 0xf6, 0xaa, 0x5d, 0xeb, 0x27, 0xdd ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "and64 r9, r5"
+  -
+    input:
+      bytes: [ 0x61, 0x28, 0xb2, 0xed, 0xb8, 0xcf, 0xb5, 0xe4 ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldxw r8, [r2+0xedb2]"
+  -
+    input:
+      bytes: [ 0x62, 0xa5, 0xdf, 0xe0, 0x14, 0x7d, 0x95, 0x78 ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "stw [r5+0xe0df], 0x78957d14"
+  -
+    input:
+      bytes: [ 0x63, 0x77, 0x2f, 0xcf, 0x76, 0xb7, 0xd3, 0xfa ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "stxw [r7+0xcf2f], r7"
+  -
+    input:
+      bytes: [ 0x64, 0x68, 0xc1, 0xf4, 0x88, 0x92, 0xd2, 0xeb ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsh r8, 0xebd29288"
+  -
+    input:
+      bytes: [ 0x65, 0xe8, 0x97, 0xe1, 0x87, 0xbe, 0x8f, 0xf8 ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "jsgt r8, 0xf88fbe87, +0xe197"
+  -
+    input:
+      bytes: [ 0x67, 0x00, 0xd7, 0xc0, 0x05, 0xb0, 0xf6, 0x74 ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsh64 r0, 0x74f6b005"
+  -
+    input:
+      bytes: [ 0x69, 0x14, 0xc7, 0x8e, 0x0b, 0xc1, 0xad, 0x69 ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldxh r4, [r1+0x8ec7]"
+  -
+    input:
+      bytes: [ 0x6a, 0xb5, 0xbc, 0x8c, 0x4f, 0x5c, 0x94, 0x01 ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sth [r5+0x8cbc], 0x1945c4f"
+  -
+    input:
+      bytes: [ 0x6b, 0x34, 0x58, 0xf5, 0xc8, 0x27, 0x9e, 0x14 ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "stxh [r4+0xf558], r3"
+  -
+    input:
+      bytes: [ 0x6c, 0x21, 0x10, 0x48, 0x01, 0x3e, 0x6e, 0xf8 ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsh r1, r2"
+  -
+    input:
+      bytes: [ 0x6d, 0x38, 0x69, 0xe3, 0xc9, 0xac, 0x3c, 0xdb ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "jsgt r8, r3, +0xe369"
+  -
+    input:
+      bytes: [ 0x6f, 0x64, 0x49, 0xd6, 0x07, 0xa9, 0x93, 0x13 ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsh64 r4, r6"
+  -
+    input:
+      bytes: [ 0x71, 0xa0, 0xeb, 0xfb, 0x3d, 0x6b, 0x58, 0x45 ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldxb r0, [r10+0xfbeb]"
+  -
+    input:
+      bytes: [ 0x72, 0xe2, 0xc1, 0x1b, 0x25, 0x2f, 0x4a, 0xdc ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "stb [r2+0x1bc1], 0xdc4a2f25"
+  -
+    input:
+      bytes: [ 0x73, 0x44, 0x09, 0x0f, 0xc1, 0x07, 0xa8, 0xf4 ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "stxb [r4+0xf09], r4"
+  -
+    input:
+      bytes: [ 0x74, 0xe0, 0x23, 0x23, 0x2f, 0x04, 0x15, 0x35 ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "rsh r0, 0x3515042f"
+  -
+    input:
+      bytes: [ 0x75, 0x04, 0x8e, 0x18, 0x6a, 0xcc, 0x3c, 0x09 ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "jsge r4, 0x93ccc6a, +0x188e"
+  -
+    input:
+      bytes: [ 0x77, 0x09, 0x3a, 0xa7, 0x3c, 0x6e, 0xfa, 0x23 ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "rsh64 r9, 0x23fa6e3c"
+  -
+    input:
+      bytes: [ 0x79, 0xa9, 0x5c, 0x7b, 0x16, 0x1f, 0xfb, 0x01 ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldxdw r9, [r10+0x7b5c]"
+  -
+    input:
+      bytes: [ 0x7a, 0xd8, 0x6b, 0x04, 0x76, 0xf0, 0x51, 0x75 ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "stdw [r8+0x46b], 0x7551f076"
+  -
+    input:
+      bytes: [ 0x7b, 0x72, 0x0f, 0x30, 0x51, 0x78, 0xd2, 0x9a ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "stxdw [r2+0x300f], r7"
+  -
+    input:
+      bytes: [ 0x7c, 0x13, 0x12, 0x73, 0x5a, 0x20, 0x65, 0xdb ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "rsh r3, r1"
+  -
+    input:
+      bytes: [ 0x7d, 0x58, 0x52, 0x01, 0x90, 0xf9, 0x30, 0x9a ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "jsge r8, r5, +0x152"
+  -
+    input:
+      bytes: [ 0x7f, 0x98, 0xea, 0xff, 0xcf, 0x5d, 0x5f, 0xa3 ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "rsh64 r8, r9"
+  -
+    input:
+      bytes: [ 0x84, 0x14, 0xd4, 0xaf, 0x60, 0xe1, 0x41, 0x18 ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "neg r4"
+  -
+    input:
+      bytes: [ 0x85, 0xd3, 0xa5, 0xe2, 0x83, 0x3d, 0xbd, 0x5d ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "call 0x5dbd3d83"
+  -
+    input:
+      bytes: [ 0x87, 0xf5, 0x2b, 0xbe, 0xa9, 0xc7, 0x31, 0xa3 ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "neg64 r5"
+  -
+    input:
+      bytes: [ 0x94, 0x39, 0x0d, 0xdc, 0x0b, 0xd2, 0xd1, 0xc9 ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mod r9, 0xc9d1d20b"
+  -
+    input:
+      bytes: [ 0x95, 0xf2, 0xd1, 0x83, 0x53, 0xa9, 0x09, 0x9f ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "exit"
+  -
+    input:
+      bytes: [ 0x97, 0xc8, 0xa6, 0x75, 0xd2, 0x09, 0x98, 0x09 ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mod64 r8, 0x99809d2"
+  -
+    input:
+      bytes: [ 0x9c, 0x96, 0xe7, 0x16, 0x0f, 0x69, 0x13, 0x90 ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mod r6, r9"
+  -
+    input:
+      bytes: [ 0x9f, 0x35, 0x5a, 0x59, 0xd6, 0x70, 0xd9, 0x5e ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mod64 r5, r3"
+  -
+    input:
+      bytes: [ 0xa4, 0x89, 0x6b, 0x5f, 0x0d, 0xbf, 0x90, 0xf7 ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor r9, 0xf790bf0d"
+  -
+    input:
+      bytes: [ 0xa5, 0xd4, 0xef, 0x79, 0xd3, 0xbb, 0xde, 0xfd ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt r4, 0xfddebbd3, +0x79ef"
+  -
+    input:
+      bytes: [ 0xa7, 0x80, 0x8b, 0x18, 0xa9, 0x34, 0x74, 0x45 ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor64 r0, 0x457434a9"
+  -
+    input:
+      bytes: [ 0xac, 0x36, 0x16, 0xe0, 0x0f, 0x52, 0x30, 0x65 ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor r6, r3"
+  -
+    input:
+      bytes: [ 0xaf, 0x41, 0x04, 0xc2, 0x2e, 0xc9, 0xf7, 0x84 ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor64 r1, r4"
+  -
+    input:
+      bytes: [ 0xb4, 0xa1, 0x9c, 0x78, 0xf9, 0x3f, 0x77, 0x1f ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov r1, 0x1f773ff9"
+  -
+    input:
+      bytes: [ 0xb5, 0x92, 0x5d, 0x5a, 0x49, 0x33, 0xfc, 0x33 ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "jle r2, 0x33fc3349, +0x5a5d"
+  -
+    input:
+      bytes: [ 0xb7, 0x70, 0x59, 0x4d, 0x5b, 0x52, 0x2a, 0x99 ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov64 r0, 0x992a525b"
+  -
+    input:
+      bytes: [ 0xbc, 0x72, 0x3e, 0x6c, 0xc9, 0x8a, 0x56, 0xd6 ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov r2, r7"
+  -
+    input:
+      bytes: [ 0xbd, 0x19, 0x80, 0xe8, 0x29, 0x85, 0xcf, 0x51 ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "jle r9, r1, +0xe880"
+  -
+    input:
+      bytes: [ 0xbf, 0x86, 0x55, 0x58, 0xb2, 0x6d, 0x14, 0x03 ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov64 r6, r8"
+  -
+    input:
+      bytes: [ 0xc4, 0xb6, 0xe2, 0xe0, 0x7c, 0x68, 0xc5, 0x2b ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "arsh r6, 0x2bc5687c"
+  -
+    input:
+      bytes: [ 0xc5, 0xf2, 0xeb, 0xe4, 0xba, 0xc0, 0xce, 0x4f ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "jslt r2, 0x4fcec0ba, +0xe4eb"
+  -
+    input:
+      bytes: [ 0xc7, 0xe8, 0xba, 0xff, 0x1f, 0xef, 0xc0, 0x88 ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "arsh64 r8, 0x88c0ef1f"
+  -
+    input:
+      bytes: [ 0xcc, 0x38, 0xc5, 0x37, 0x13, 0xc0, 0xe7, 0x27 ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "arsh r8, r3"
+  -
+    input:
+      bytes: [ 0xcd, 0x90, 0x67, 0x88, 0x6b, 0xd0, 0x27, 0xf4 ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "jslt r0, r9, +0x8867"
+  -
+    input:
+      bytes: [ 0xcf, 0x82, 0xe1, 0xcd, 0xbe, 0xc3, 0x2d, 0x7c ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "arsh64 r2, r8"
+  -
+    input:
+      bytes: [ 0xd4, 0x53, 0x3f, 0x0c, 0x40, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "le64 r3"
+  -
+    input:
+      bytes: [ 0xd5, 0xe9, 0xf6, 0xb2, 0x50, 0xfd, 0xb0, 0xe5 ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "jsle r9, 0xe5b0fd50, +0xb2f6"
+  -
+    input:
+      bytes: [ 0xdc, 0xb2, 0xa3, 0x50, 0x20, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "be32 r2"
+  -
+    input:
+      bytes: [ 0xdd, 0x95, 0xbf, 0xb1, 0xf2, 0x5f, 0x7b, 0xc4 ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "jsle r5, r9, +0xb1bf"
+  -
+    input:
+      bytes: [ 0x8d, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_LITTLE_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "callx r2"
diff --git a/tests/MC/BPF/extended-be.yaml b/tests/MC/BPF/extended-be.yaml
new file mode 100644
index 000000000..423ff70ad
--- /dev/null
+++ b/tests/MC/BPF/extended-be.yaml
@@ -0,0 +1,136 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldb [0x0]"
+  -
+    input:
+      bytes: [ 0x28, 0x00, 0x00, 0x00, 0xfa, 0x00, 0x00, 0xff ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldh [0xfa0000ff]"
+  -
+    input:
+      bytes: [ 0x40, 0x10, 0x00, 0x00, 0xcc, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldw [r1+0xcc000000]"
+  -
+    input:
+      bytes: [ 0x18, 0x00, 0x00, 0x00, 0x0c, 0xb0, 0xce, 0xfa, 0x00, 0x00, 0x00, 0x00, 0xef, 0xbe, 0xad, 0xde ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "lddw r0, 0xefbeadde0cb0cefa"
+  -
+    input:
+      bytes: [ 0x71, 0x13, 0x11, 0x00, 0x00, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldxb r3, [r1+0x1100]"
+  -
+    input:
+      bytes: [ 0x94, 0x09, 0x00, 0x00, 0x37, 0x13, 0x03, 0x00 ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mod r9, 0x37130300"
+  -
+    input:
+      bytes: [ 0x84, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "neg r3"
+  -
+    input:
+      bytes: [ 0x87, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "neg64 r0"
+  -
+    input:
+      bytes: [ 0xdc, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20 ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "be32 r2"
+  -
+    input:
+      bytes: [ 0x05, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "jmp +0x800"
+  -
+    input:
+      bytes: [ 0xdd, 0x35, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "jsle r5, r3, +0x3000"
+  -
+    input:
+      bytes: [ 0xa5, 0x35, 0x30, 0x00, 0x10, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt r5, 0x10000000, +0x3000"
+  -
+    input:
+      bytes: [ 0xc3, 0x12, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "xaddw [r2+0x10], r1"
+  -
+    input:
+      bytes: [ 0xdb, 0xa9, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "xadddw [r9+0x1], r10"
+  -
+    input:
+      bytes: [ 0x8d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02 ]
+      arch: "CS_ARCH_BPF"
+      options: [ "CS_MODE_BPF_EXTENDED", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "callx r2"
diff --git a/tests/MC/HPPA/alu11.s.yaml b/tests/MC/HPPA/alu11.s.yaml
new file mode 100644
index 000000000..f34e0c380
--- /dev/null
+++ b/tests/MC/HPPA/alu11.s.yaml
@@ -0,0 +1,3889 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x06, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "add r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x26, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "add,= r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x46, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "add,< r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x66, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "add,<= r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x86, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "add,nuv r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xa6, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "add,znv r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xc6, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "add,sv r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xe6, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "add,od r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x16, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "add,tr r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x36, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "add,<> r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x56, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "add,>= r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x76, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "add,> r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x96, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "add,uv r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xb6, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "add,vnz r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xd6, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "add,nsv r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xf6, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "add,ev r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x0e, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addo r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x2e, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addo,= r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x4e, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addo,< r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x6e, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addo,<= r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x8e, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addo,nuv r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xae, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addo,znv r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xce, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addo,sv r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xee, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addo,od r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x1e, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addo,tr r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x3e, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addo,<> r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x5e, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addo,>= r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x7e, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addo,> r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x9e, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addo,uv r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xbe, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addo,vnz r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xde, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addo,nsv r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xfe, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addo,ev r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x07, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addc r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x27, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addc,= r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x47, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addc,< r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x67, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addc,<= r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x87, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addc,nuv r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xa7, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addc,znv r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xc7, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addc,sv r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xe7, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addc,od r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x17, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addc,tr r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x37, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addc,<> r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x57, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addc,>= r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x77, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addc,> r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x97, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addc,uv r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xb7, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addc,vnz r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xd7, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addc,nsv r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xf7, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addc,ev r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x0f, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addco r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x2f, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addco,= r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x4f, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addco,< r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x6f, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addco,<= r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x8f, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addco,nuv r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xaf, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addco,znv r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xcf, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addco,sv r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xef, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addco,od r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x1f, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addco,tr r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x3f, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addco,<> r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x5f, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addco,>= r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x7f, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addco,> r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x9f, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addco,uv r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xbf, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addco,vnz r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xdf, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addco,nsv r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xff, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addco,ev r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x06, 0x43 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh1add r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x26, 0x43 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh1add,= r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x46, 0x43 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh1add,< r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x66, 0x43 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh1add,<= r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x86, 0x43 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh1add,nuv r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xa6, 0x43 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh1add,znv r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xc6, 0x43 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh1add,sv r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xe6, 0x43 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh1add,od r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x16, 0x43 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh1add,tr r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x36, 0x43 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh1add,<> r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x56, 0x43 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh1add,>= r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x76, 0x43 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh1add,> r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x96, 0x43 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh1add,uv r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xb6, 0x43 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh1add,vnz r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xd6, 0x43 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh1add,nsv r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xf6, 0x43 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh1add,ev r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x0e, 0x43 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh1addo r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x2e, 0x43 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh1addo,= r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x4e, 0x43 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh1addo,< r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x6e, 0x43 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh1addo,<= r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x8e, 0x43 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh1addo,nuv r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xae, 0x43 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh1addo,znv r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xce, 0x43 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh1addo,sv r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xee, 0x43 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh1addo,od r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x1e, 0x43 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh1addo,tr r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x3e, 0x43 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh1addo,<> r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x5e, 0x43 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh1addo,>= r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x7e, 0x43 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh1addo,> r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x9e, 0x43 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh1addo,uv r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xbe, 0x43 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh1addo,vnz r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xde, 0x43 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh1addo,nsv r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xfe, 0x43 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh1addo,ev r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x06, 0x83 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh2add r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x26, 0x83 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh2add,= r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x46, 0x83 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh2add,< r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x66, 0x83 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh2add,<= r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x86, 0x83 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh2add,nuv r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xa6, 0x83 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh2add,znv r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xc6, 0x83 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh2add,sv r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xe6, 0x83 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh2add,od r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x16, 0x83 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh2add,tr r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x36, 0x83 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh2add,<> r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x56, 0x83 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh2add,>= r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x76, 0x83 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh2add,> r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x96, 0x83 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh2add,uv r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xb6, 0x83 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh2add,vnz r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xd6, 0x83 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh2add,nsv r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xf6, 0x83 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh2add,ev r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x0e, 0x83 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh2addo r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x2e, 0x83 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh2addo,= r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x4e, 0x83 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh2addo,< r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x6e, 0x83 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh2addo,<= r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x8e, 0x83 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh2addo,nuv r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xae, 0x83 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh2addo,znv r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xce, 0x83 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh2addo,sv r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xee, 0x83 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh2addo,od r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x1e, 0x83 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh2addo,tr r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x3e, 0x83 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh2addo,<> r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x5e, 0x83 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh2addo,>= r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x7e, 0x83 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh2addo,> r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x9e, 0x83 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh2addo,uv r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xbe, 0x83 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh2addo,vnz r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xde, 0x83 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh2addo,nsv r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xfe, 0x83 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh2addo,ev r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x06, 0xc3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh3add r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x26, 0xc3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh3add r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x46, 0xc3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh3add r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x66, 0xc3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh3add r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x86, 0xc3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh3add r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xa6, 0xc3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh3add r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xc6, 0xc3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh3add r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xe6, 0xc3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh3add r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x16, 0xc3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh3add r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x36, 0xc3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh3add r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x56, 0xc3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh3add r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x76, 0xc3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh3add r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x96, 0xc3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh3add r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xb6, 0xc3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh3add r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xd6, 0xc3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh3add r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xf6, 0xc3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh3add r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x0e, 0xc3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh3addo r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x2e, 0xc3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh3addo,= r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x4e, 0xc3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh3addo,< r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x6e, 0xc3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh3addo,<= r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x8e, 0xc3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh3addo,nuv r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xae, 0xc3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh3addo,znv r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xce, 0xc3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh3addo,sv r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xee, 0xc3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh3addo,od r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x1e, 0xc3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh3addo,tr r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x3e, 0xc3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh3addo,<> r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x5e, 0xc3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh3addo,>= r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x7e, 0xc3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh3addo,> r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x9e, 0xc3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh3addo,uv r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xbe, 0xc3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh3addo,vnz r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xde, 0xc3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh3addo,nsv r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xfe, 0xc3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh3addo,ev r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x04, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x24, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub,= r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x44, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub,< r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x64, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub,<= r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x84, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub,<< r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xa4, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub,<<= r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xc4, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub,sv r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xe4, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub,od r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x14, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub,tr r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x34, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub,<> r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x54, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub,>= r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x74, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub,> r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x94, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub,>>= r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xb4, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub,>> r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xd4, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub,nsv r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xf4, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub,ev r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x0c, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "subo r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x2c, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "subo,= r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x4c, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "subo,< r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x6c, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "subo,<= r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x8c, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "subo,<< r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xac, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "subo,<<= r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xcc, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "subo,sv r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xec, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "subo,od r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x1c, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "subo,tr r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x3c, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "subo,<> r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x5c, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "subo,>= r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x7c, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "subo,> r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x9c, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "subo,>>= r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xbc, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "subo,>> r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xdc, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "subo,nsv r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xfc, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "subo,ev r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x04, 0xc3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "subt r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x24, 0xc3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "subt,= r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x44, 0xc3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "subt,< r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x64, 0xc3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "subt,<= r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x84, 0xc3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "subt,<< r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xa4, 0xc3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "subt,<<= r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xc4, 0xc3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "subt,sv r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xe4, 0xc3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "subt,od r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x14, 0xc3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "subt,tr r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x34, 0xc3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "subt,<> r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x54, 0xc3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "subt,>= r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x74, 0xc3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "subt,> r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x94, 0xc3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "subt,>>= r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xb4, 0xc3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "subt,>> r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xd4, 0xc3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "subt,nsv r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xf4, 0xc3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "subt,ev r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x0c, 0xc3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "subto r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x2c, 0xc3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "subto,= r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x4c, 0xc3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "subto,< r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x6c, 0xc3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "subto,<= r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x8c, 0xc3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "subto,<< r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xac, 0xc3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "subto,<<= r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xcc, 0xc3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "subto,sv r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xec, 0xc3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "subto,od r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x1c, 0xc3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "subto,tr r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x3c, 0xc3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "subto,<> r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x5c, 0xc3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "subto,>= r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x7c, 0xc3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "subto,> r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x9c, 0xc3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "subto,>>= r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xbc, 0xc3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "subto,>> r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xdc, 0xc3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "subto,nsv r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xfc, 0xc3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "subto,ev r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x05, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "subb r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x25, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "subb,= r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x45, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "subb,< r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x65, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "subb,<= r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x85, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "subb,<< r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xa5, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "subb,<<= r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xc5, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "subb,sv r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xe5, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "subb,od r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x15, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "subb,tr r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x35, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "subb,<> r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x55, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "subb,>= r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x75, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "subb,> r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x95, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "subb,>>= r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xb5, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "subb,>> r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xd5, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "subb,nsv r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xf5, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "subb,ev r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x0d, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "subbo r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x2d, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "subbo,= r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x4d, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "subbo,< r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x6d, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "subbo,<= r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x8d, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "subbo,<< r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xad, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "subbo,<<= r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xcd, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "subbo,sv r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xed, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "subbo,od r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x1d, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "subbo,tr r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x3d, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "subbo,<> r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x5d, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "subbo,>= r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x7d, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "subbo,> r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x9d, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "subbo,>>= r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xbd, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "subbo,>> r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xdd, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "subbo,nsv r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xfd, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "subbo,ev r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x04, 0x43 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "ds r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x24, 0x43 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "ds,= r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x44, 0x43 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "ds,< r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x64, 0x43 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "ds,<= r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x84, 0x43 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "ds,<< r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xa4, 0x43 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "ds,<<= r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xc4, 0x43 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "ds,sv r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xe4, 0x43 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "ds,od r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x14, 0x43 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "ds,tr r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x34, 0x43 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "ds,<> r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x54, 0x43 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "ds,>= r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x74, 0x43 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "ds,> r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x94, 0x43 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "ds,>>= r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xb4, 0x43 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "ds,>> r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xd4, 0x43 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "ds,nsv r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xf4, 0x43 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "ds,ev r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x00, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "andcm r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x20, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "andcm,= r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x40, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "andcm,< r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x60, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "andcm,<= r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xe0, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "andcm,od r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x10, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "andcm,tr r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x30, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "andcm,<> r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x50, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "andcm,>= r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x70, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "andcm,> r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xf0, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "andcm,ev r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x02, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "and r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x22, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "and,= r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x42, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "and,< r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x62, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "and,<= r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xe2, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "and,od r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x12, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "and,tr r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x32, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "and,<> r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x52, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "and,>= r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x72, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "and,> r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xf2, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "and,ev r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x02, 0x43 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "or r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x22, 0x43 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "or,= r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x42, 0x43 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "or,< r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x62, 0x43 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "or,<= r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xe2, 0x43 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "or,od r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x12, 0x43 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "or,tr r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x32, 0x43 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "or,<> r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x52, 0x43 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "or,>= r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x72, 0x43 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "or,> r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xf2, 0x43 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "or,ev r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x02, 0x83 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x22, 0x83 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor,= r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x42, 0x83 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor,< r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x62, 0x83 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor,<= r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xe2, 0x83 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor,od r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x12, 0x83 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor,tr r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x32, 0x83 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor,<> r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x52, 0x83 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor,>= r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x72, 0x83 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor,> r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xf2, 0x83 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor,ev r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x03, 0x83 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "uxor r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x23, 0x83 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "uxor,swz r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x43, 0x83 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "uxor,sbz r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x63, 0x83 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "uxor,shz r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x13, 0x83 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "uxor,tr r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x33, 0x83 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "uxor,nwz r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x53, 0x83 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "uxor,nbz r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x73, 0x83 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "uxor,nhz r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x08, 0x83 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "comclr r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x28, 0x83 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "comclr,= r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x48, 0x83 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "comclr,< r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x68, 0x83 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "comclr,<= r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x88, 0x83 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "comclr,<< r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xa8, 0x83 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "comclr,<<= r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xc8, 0x83 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "comclr,sv r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xe8, 0x83 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "comclr,od r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x18, 0x83 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "comclr,tr r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x38, 0x83 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "comclr,<> r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x58, 0x83 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "comclr,>= r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x78, 0x83 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "comclr,> r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x98, 0x83 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "comclr,>>= r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xb8, 0x83 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "comclr,>> r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xd8, 0x83 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "comclr,nsv r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xf8, 0x83 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "comclr,ev r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x09, 0x83 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "uaddcm r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x29, 0x83 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "uaddcm,swz r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x49, 0x83 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "uaddcm,sbz r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x69, 0x83 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "uaddcm,shz r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x19, 0x83 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "uaddcm,tr r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x39, 0x83 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "uaddcm,nwz r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x59, 0x83 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "uaddcm,nbz r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x79, 0x83 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "uaddcm,nhz r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x09, 0xc3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "uaddcmt r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x29, 0xc3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "uaddcmt,swz r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x49, 0xc3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "uaddcmt,sbz r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x69, 0xc3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "uaddcmt,shz r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x19, 0xc3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "uaddcmt,tr r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x39, 0xc3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "uaddcmt,nwz r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x59, 0xc3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "uaddcmt,nbz r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x79, 0xc3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "uaddcmt,nhz r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x0a, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addl r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x2a, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addl,= r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x4a, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addl,< r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x6a, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addl,<= r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x8a, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addl,nuv r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xaa, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addl,znv r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xca, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addl,sv r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xea, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addl,od r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x1a, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addl,tr r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x3a, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addl,<> r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x5a, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addl,>= r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x7a, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addl,> r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x9a, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addl,uv r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xba, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addl,vnz r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xda, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addl,nsv r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xfa, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addl,ev r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x0a, 0x43 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh1addl r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x2a, 0x43 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh1addl,= r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x4a, 0x43 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh1addl,< r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x6a, 0x43 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh1addl,<= r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x8a, 0x43 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh1addl,nuv r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xaa, 0x43 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh1addl,znv r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xca, 0x43 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh1addl,sv r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xea, 0x43 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh1addl,od r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x1a, 0x43 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh1addl,tr r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x3a, 0x43 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh1addl,<> r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x5a, 0x43 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh1addl,>= r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x7a, 0x43 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh1addl,> r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x9a, 0x43 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh1addl,uv r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xba, 0x43 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh1addl,vnz r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xda, 0x43 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh1addl,nsv r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xfa, 0x43 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh1addl,ev r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x0a, 0x83 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh2addl r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x2a, 0x83 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh2addl,= r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x4a, 0x83 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh2addl,< r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x6a, 0x83 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh2addl,<= r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x8a, 0x83 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh2addl,nuv r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xaa, 0x83 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh2addl,znv r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xca, 0x83 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh2addl,sv r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xea, 0x83 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh2addl,od r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x1a, 0x83 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh2addl,tr r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x3a, 0x83 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh2addl,<> r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x5a, 0x83 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh2addl,>= r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x7a, 0x83 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh2addl,> r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x9a, 0x83 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh2addl,uv r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xba, 0x83 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh2addl,vnz r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xda, 0x83 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh2addl,nsv r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xfa, 0x83 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh2addl,ev r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x0a, 0xc3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh3addl r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x2a, 0xc3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh3addl,= r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x4a, 0xc3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh3addl,< r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x6a, 0xc3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh3addl,<= r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x8a, 0xc3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh3addl,nuv r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xaa, 0xc3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh3addl,znv r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xca, 0xc3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh3addl,sv r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xea, 0xc3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh3addl,od r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x1a, 0xc3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh3addl,tr r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x3a, 0xc3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh3addl,<> r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x5a, 0xc3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh3addl,>= r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x7a, 0xc3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh3addl,> r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x9a, 0xc3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh3addl,uv r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xba, 0xc3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh3addl,vnz r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xda, 0xc3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh3addl,nsv r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xfa, 0xc3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh3addl,ev r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x20, 0x0b, 0x82 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "dcor r1,rp"
+  -
+    input:
+      bytes: [ 0x08, 0x20, 0x2b, 0x82 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "dcor,swz r1,rp"
+  -
+    input:
+      bytes: [ 0x08, 0x20, 0x4b, 0x82 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "dcor,sbz r1,rp"
+  -
+    input:
+      bytes: [ 0x08, 0x20, 0x6b, 0x82 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "dcor,shz r1,rp"
+  -
+    input:
+      bytes: [ 0x08, 0x20, 0x1b, 0x82 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "dcor,tr r1,rp"
+  -
+    input:
+      bytes: [ 0x08, 0x20, 0x3b, 0x82 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "dcor,nwz r1,rp"
+  -
+    input:
+      bytes: [ 0x08, 0x20, 0x5b, 0x82 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "dcor,nbz r1,rp"
+  -
+    input:
+      bytes: [ 0x08, 0x20, 0x7b, 0x82 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "dcor,nhz r1,rp"
+  -
+    input:
+      bytes: [ 0x08, 0x20, 0x0b, 0xc2 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "idcor r1,rp"
+  -
+    input:
+      bytes: [ 0x08, 0x20, 0x2b, 0xc2 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "idcor,swz r1,rp"
+  -
+    input:
+      bytes: [ 0x08, 0x20, 0x4b, 0xc2 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "idcor,sbz r1,rp"
+  -
+    input:
+      bytes: [ 0x08, 0x20, 0x6b, 0xc2 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "idcor,shz r1,rp"
+  -
+    input:
+      bytes: [ 0x08, 0x20, 0x1b, 0xc2 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "idcor,tr r1,rp"
+  -
+    input:
+      bytes: [ 0x08, 0x20, 0x3b, 0xc2 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "idcor,nwz r1,rp"
+  -
+    input:
+      bytes: [ 0x08, 0x20, 0x5b, 0xc2 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "idcor,nbz r1,rp"
+  -
+    input:
+      bytes: [ 0x08, 0x20, 0x7b, 0xc2 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "idcor,nhz r1,rp"
diff --git a/tests/MC/HPPA/arith_imm11.s.yaml b/tests/MC/HPPA/arith_imm11.s.yaml
new file mode 100644
index 000000000..708aca183
--- /dev/null
+++ b/tests/MC/HPPA/arith_imm11.s.yaml
@@ -0,0 +1,865 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xb4, 0x22, 0x00, 0x1e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addi 0xf,r1,rp"
+  -
+    input:
+      bytes: [ 0xb4, 0x22, 0x20, 0x1e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addi,= 0xf,r1,rp"
+  -
+    input:
+      bytes: [ 0xb4, 0x22, 0x40, 0x1e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addi,< 0xf,r1,rp"
+  -
+    input:
+      bytes: [ 0xb4, 0x22, 0x60, 0x1e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addi,<= 0xf,r1,rp"
+  -
+    input:
+      bytes: [ 0xb4, 0x22, 0x80, 0x1e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addi,nuv 0xf,r1,rp"
+  -
+    input:
+      bytes: [ 0xb4, 0x22, 0xa0, 0x1e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addi,znv 0xf,r1,rp"
+  -
+    input:
+      bytes: [ 0xb4, 0x22, 0xc0, 0x1e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addi,sv 0xf,r1,rp"
+  -
+    input:
+      bytes: [ 0xb4, 0x22, 0xe0, 0x1e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addi,od 0xf,r1,rp"
+  -
+    input:
+      bytes: [ 0xb4, 0x22, 0x10, 0x1e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addi,tr 0xf,r1,rp"
+  -
+    input:
+      bytes: [ 0xb4, 0x22, 0x30, 0x1e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addi,<> 0xf,r1,rp"
+  -
+    input:
+      bytes: [ 0xb4, 0x22, 0x50, 0x1e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addi,>= 0xf,r1,rp"
+  -
+    input:
+      bytes: [ 0xb4, 0x22, 0x70, 0x1e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addi,> 0xf,r1,rp"
+  -
+    input:
+      bytes: [ 0xb4, 0x22, 0x90, 0x1e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addi,uv 0xf,r1,rp"
+  -
+    input:
+      bytes: [ 0xb4, 0x22, 0xb0, 0x1e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addi,vnz 0xf,r1,rp"
+  -
+    input:
+      bytes: [ 0xb4, 0x22, 0xd0, 0x1e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addi,nsv 0xf,r1,rp"
+  -
+    input:
+      bytes: [ 0xb4, 0x22, 0xf0, 0x1e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addi,ev 0xf,r1,rp"
+  -
+    input:
+      bytes: [ 0xb0, 0x22, 0x00, 0x1e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addit 0xf,r1,rp"
+  -
+    input:
+      bytes: [ 0xb0, 0x22, 0x20, 0x1e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addit,= 0xf,r1,rp"
+  -
+    input:
+      bytes: [ 0xb0, 0x22, 0x40, 0x1e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addit,< 0xf,r1,rp"
+  -
+    input:
+      bytes: [ 0xb0, 0x22, 0x60, 0x1e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addit,<= 0xf,r1,rp"
+  -
+    input:
+      bytes: [ 0xb0, 0x22, 0x80, 0x1e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addit,nuv 0xf,r1,rp"
+  -
+    input:
+      bytes: [ 0xb0, 0x22, 0xa0, 0x1e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addit,znv 0xf,r1,rp"
+  -
+    input:
+      bytes: [ 0xb0, 0x22, 0xc0, 0x1e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addit,sv 0xf,r1,rp"
+  -
+    input:
+      bytes: [ 0xb0, 0x22, 0xe0, 0x1e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addit,od 0xf,r1,rp"
+  -
+    input:
+      bytes: [ 0xb0, 0x22, 0x10, 0x1e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addit,tr 0xf,r1,rp"
+  -
+    input:
+      bytes: [ 0xb0, 0x22, 0x30, 0x1e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addit,<> 0xf,r1,rp"
+  -
+    input:
+      bytes: [ 0xb0, 0x22, 0x50, 0x1e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addit,>= 0xf,r1,rp"
+  -
+    input:
+      bytes: [ 0xb0, 0x22, 0x70, 0x1e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addit,> 0xf,r1,rp"
+  -
+    input:
+      bytes: [ 0xb0, 0x22, 0x90, 0x1e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addit,uv 0xf,r1,rp"
+  -
+    input:
+      bytes: [ 0xb0, 0x22, 0xb0, 0x1e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addit,vnz 0xf,r1,rp"
+  -
+    input:
+      bytes: [ 0xb0, 0x22, 0xd0, 0x1e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addit,nsv 0xf,r1,rp"
+  -
+    input:
+      bytes: [ 0xb0, 0x22, 0xf0, 0x1e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addit,ev 0xf,r1,rp"
+  -
+    input:
+      bytes: [ 0x94, 0x22, 0x00, 0x1e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "subi 0xf,r1,rp"
+  -
+    input:
+      bytes: [ 0x94, 0x22, 0x20, 0x1e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "subi,= 0xf,r1,rp"
+  -
+    input:
+      bytes: [ 0x94, 0x22, 0x40, 0x1e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "subi,< 0xf,r1,rp"
+  -
+    input:
+      bytes: [ 0x94, 0x22, 0x60, 0x1e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "subi,<= 0xf,r1,rp"
+  -
+    input:
+      bytes: [ 0x94, 0x22, 0x80, 0x1e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "subi,<< 0xf,r1,rp"
+  -
+    input:
+      bytes: [ 0x94, 0x22, 0xa0, 0x1e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "subi,<<= 0xf,r1,rp"
+  -
+    input:
+      bytes: [ 0x94, 0x22, 0xc0, 0x1e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "subi,sv 0xf,r1,rp"
+  -
+    input:
+      bytes: [ 0x94, 0x22, 0xe0, 0x1e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "subi,od 0xf,r1,rp"
+  -
+    input:
+      bytes: [ 0x94, 0x22, 0x10, 0x1e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "subi,tr 0xf,r1,rp"
+  -
+    input:
+      bytes: [ 0x94, 0x22, 0x30, 0x1e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "subi,<> 0xf,r1,rp"
+  -
+    input:
+      bytes: [ 0x94, 0x22, 0x50, 0x1e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "subi,>= 0xf,r1,rp"
+  -
+    input:
+      bytes: [ 0x94, 0x22, 0x70, 0x1e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "subi,> 0xf,r1,rp"
+  -
+    input:
+      bytes: [ 0x94, 0x22, 0x90, 0x1e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "subi,>>= 0xf,r1,rp"
+  -
+    input:
+      bytes: [ 0x94, 0x22, 0xb0, 0x1e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "subi,>> 0xf,r1,rp"
+  -
+    input:
+      bytes: [ 0x94, 0x22, 0xd0, 0x1e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "subi,nsv 0xf,r1,rp"
+  -
+    input:
+      bytes: [ 0x94, 0x22, 0xf0, 0x1e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "subi,ev 0xf,r1,rp"
+  -
+    input:
+      bytes: [ 0xb4, 0x22, 0x08, 0x1e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addio 0xf,r1,rp"
+  -
+    input:
+      bytes: [ 0xb4, 0x22, 0x28, 0x1e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addio,= 0xf,r1,rp"
+  -
+    input:
+      bytes: [ 0xb4, 0x22, 0x48, 0x1e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addio,< 0xf,r1,rp"
+  -
+    input:
+      bytes: [ 0xb4, 0x22, 0x68, 0x1e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addio,<= 0xf,r1,rp"
+  -
+    input:
+      bytes: [ 0xb4, 0x22, 0x88, 0x1e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addio,nuv 0xf,r1,rp"
+  -
+    input:
+      bytes: [ 0xb4, 0x22, 0xa8, 0x1e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addio,znv 0xf,r1,rp"
+  -
+    input:
+      bytes: [ 0xb4, 0x22, 0xc8, 0x1e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addio,sv 0xf,r1,rp"
+  -
+    input:
+      bytes: [ 0xb4, 0x22, 0xe8, 0x1e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addio,od 0xf,r1,rp"
+  -
+    input:
+      bytes: [ 0xb4, 0x22, 0x18, 0x1e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addio,tr 0xf,r1,rp"
+  -
+    input:
+      bytes: [ 0xb4, 0x22, 0x38, 0x1e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addio,<> 0xf,r1,rp"
+  -
+    input:
+      bytes: [ 0xb4, 0x22, 0x58, 0x1e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addio,>= 0xf,r1,rp"
+  -
+    input:
+      bytes: [ 0xb4, 0x22, 0x78, 0x1e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addio,> 0xf,r1,rp"
+  -
+    input:
+      bytes: [ 0xb4, 0x22, 0x98, 0x1e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addio,uv 0xf,r1,rp"
+  -
+    input:
+      bytes: [ 0xb4, 0x22, 0xb8, 0x1e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addio,vnz 0xf,r1,rp"
+  -
+    input:
+      bytes: [ 0xb4, 0x22, 0xd8, 0x1e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addio,nsv 0xf,r1,rp"
+  -
+    input:
+      bytes: [ 0xb4, 0x22, 0xf8, 0x1e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addio,ev 0xf,r1,rp"
+  -
+    input:
+      bytes: [ 0xb0, 0x22, 0x08, 0x1e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addito 0xf,r1,rp"
+  -
+    input:
+      bytes: [ 0xb0, 0x22, 0x28, 0x1e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addito,= 0xf,r1,rp"
+  -
+    input:
+      bytes: [ 0xb0, 0x22, 0x48, 0x1e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addito,< 0xf,r1,rp"
+  -
+    input:
+      bytes: [ 0xb0, 0x22, 0x68, 0x1e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addito,<= 0xf,r1,rp"
+  -
+    input:
+      bytes: [ 0xb0, 0x22, 0x88, 0x1e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addito,nuv 0xf,r1,rp"
+  -
+    input:
+      bytes: [ 0xb0, 0x22, 0xa8, 0x1e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addito,znv 0xf,r1,rp"
+  -
+    input:
+      bytes: [ 0xb0, 0x22, 0xc8, 0x1e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addito,sv 0xf,r1,rp"
+  -
+    input:
+      bytes: [ 0xb0, 0x22, 0xe8, 0x1e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addito,od 0xf,r1,rp"
+  -
+    input:
+      bytes: [ 0xb0, 0x22, 0x18, 0x1e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addito,tr 0xf,r1,rp"
+  -
+    input:
+      bytes: [ 0xb0, 0x22, 0x38, 0x1e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addito,<> 0xf,r1,rp"
+  -
+    input:
+      bytes: [ 0xb0, 0x22, 0x58, 0x1e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addito,>= 0xf,r1,rp"
+  -
+    input:
+      bytes: [ 0xb0, 0x22, 0x78, 0x1e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addito,> 0xf,r1,rp"
+  -
+    input:
+      bytes: [ 0xb0, 0x22, 0x98, 0x1e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addito,uv 0xf,r1,rp"
+  -
+    input:
+      bytes: [ 0xb0, 0x22, 0xb8, 0x1e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addito,vnz 0xf,r1,rp"
+  -
+    input:
+      bytes: [ 0xb0, 0x22, 0xd8, 0x1e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addito,nsv 0xf,r1,rp"
+  -
+    input:
+      bytes: [ 0xb0, 0x22, 0xf8, 0x1e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addito,ev 0xf,r1,rp"
+  -
+    input:
+      bytes: [ 0x94, 0x22, 0x08, 0x1e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "subio 0xf,r1,rp"
+  -
+    input:
+      bytes: [ 0x94, 0x22, 0x28, 0x1e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "subio,= 0xf,r1,rp"
+  -
+    input:
+      bytes: [ 0x94, 0x22, 0x48, 0x1e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "subio,< 0xf,r1,rp"
+  -
+    input:
+      bytes: [ 0x94, 0x22, 0x68, 0x1e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "subio,<= 0xf,r1,rp"
+  -
+    input:
+      bytes: [ 0x94, 0x22, 0x88, 0x1e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "subio,<< 0xf,r1,rp"
+  -
+    input:
+      bytes: [ 0x94, 0x22, 0xa8, 0x1e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "subio,<<= 0xf,r1,rp"
+  -
+    input:
+      bytes: [ 0x94, 0x22, 0xc8, 0x1e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "subio,sv 0xf,r1,rp"
+  -
+    input:
+      bytes: [ 0x94, 0x22, 0xe8, 0x1e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "subio,od 0xf,r1,rp"
+  -
+    input:
+      bytes: [ 0x94, 0x22, 0x18, 0x1e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "subio,tr 0xf,r1,rp"
+  -
+    input:
+      bytes: [ 0x94, 0x22, 0x38, 0x1e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "subio,<> 0xf,r1,rp"
+  -
+    input:
+      bytes: [ 0x94, 0x22, 0x58, 0x1e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "subio,>= 0xf,r1,rp"
+  -
+    input:
+      bytes: [ 0x94, 0x22, 0x78, 0x1e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "subio,> 0xf,r1,rp"
+  -
+    input:
+      bytes: [ 0x94, 0x22, 0x98, 0x1e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "subio,>>= 0xf,r1,rp"
+  -
+    input:
+      bytes: [ 0x94, 0x22, 0xb8, 0x1e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "subio,>> 0xf,r1,rp"
+  -
+    input:
+      bytes: [ 0x94, 0x22, 0xd8, 0x1e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "subio,nsv 0xf,r1,rp"
+  -
+    input:
+      bytes: [ 0x94, 0x22, 0xf8, 0x1e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "subio,ev 0xf,r1,rp"
diff --git a/tests/MC/HPPA/assist20.s.yaml b/tests/MC/HPPA/assist20.s.yaml
new file mode 100644
index 000000000..95d83df06
--- /dev/null
+++ b/tests/MC/HPPA/assist20.s.yaml
@@ -0,0 +1,280 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x10, 0x00, 0x00, 0x61 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "spop0,1,1,n"
+  -
+    input:
+      bytes: [ 0x10, 0x00, 0x0a, 0x61 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "spop1,1,1,n r1"
+  -
+    input:
+      bytes: [ 0x10, 0x20, 0x04, 0x61 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "spop2,1,1,n r1"
+  -
+    input:
+      bytes: [ 0x10, 0x41, 0x06, 0x61 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "spop3,1,1,n r1,rp"
+  -
+    input:
+      bytes: [ 0x30, 0x00, 0x01, 0x61 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "copr,5,1,n"
+  -
+    input:
+      bytes: [ 0x2c, 0x5e, 0x59, 0x41 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "cldd,5,sl 0xf(sr1,rp),r1"
+  -
+    input:
+      bytes: [ 0x2c, 0x5e, 0x79, 0x61 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "cldd,5,mb,sl 0xf(sr1,rp),r1"
+  -
+    input:
+      bytes: [ 0x2c, 0x5e, 0x59, 0x61 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "cldd,5,ma,sl 0xf(sr1,rp),r1"
+  -
+    input:
+      bytes: [ 0x2c, 0x41, 0x49, 0x43 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "cldd,5,sl 2(sr1,rp),r3"
+  -
+    input:
+      bytes: [ 0x2c, 0x41, 0x69, 0x43 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "cldd,5,s,sl 2(sr1,rp),r3"
+  -
+    input:
+      bytes: [ 0x2c, 0x41, 0x69, 0x63 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "cldd,5,sm,sl 2(sr1,rp),r3"
+  -
+    input:
+      bytes: [ 0x2c, 0x41, 0x49, 0x63 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "cldd,5,m,sl 2(sr1,rp),r3"
+  -
+    input:
+      bytes: [ 0x24, 0x5e, 0x59, 0x41 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "cldw,5,sl 0xf(sr1,rp),r1"
+  -
+    input:
+      bytes: [ 0x24, 0x5e, 0x79, 0x61 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "cldw,5,mb,sl 0xf(sr1,rp),r1"
+  -
+    input:
+      bytes: [ 0x24, 0x5e, 0x59, 0x61 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "cldw,5,ma,sl 0xf(sr1,rp),r1"
+  -
+    input:
+      bytes: [ 0x24, 0x41, 0x49, 0x43 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "cldw,5,sl r1(sr1,rp),r3"
+  -
+    input:
+      bytes: [ 0x24, 0x41, 0x69, 0x43 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "cldw,5,s,sl r1(sr1,rp),r3"
+  -
+    input:
+      bytes: [ 0x24, 0x41, 0x69, 0x63 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "cldw,5,sm,sl r1(sr1,rp),r3"
+  -
+    input:
+      bytes: [ 0x24, 0x41, 0x49, 0x63 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "cldw,5,m,sl r1(sr1,rp),r3"
+  -
+    input:
+      bytes: [ 0x2c, 0x5e, 0x17, 0x41 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "cstd,5,bc r1,0xf(rp)"
+  -
+    input:
+      bytes: [ 0x2c, 0x5e, 0x37, 0x61 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "cstd,5,mb,bc r1,0xf(rp)"
+  -
+    input:
+      bytes: [ 0x2c, 0x5e, 0x17, 0x61 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "cstd,5,ma,bc r1,0xf(rp)"
+  -
+    input:
+      bytes: [ 0x2c, 0x43, 0x07, 0x41 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "cstd,5,bc r1,r3(rp)"
+  -
+    input:
+      bytes: [ 0x2c, 0x43, 0x27, 0x41 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "cstd,5,s,bc r1,r3(rp)"
+  -
+    input:
+      bytes: [ 0x2c, 0x43, 0x27, 0x61 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "cstd,5,sm,bc r1,r3(rp)"
+  -
+    input:
+      bytes: [ 0x24, 0x5e, 0x17, 0x41 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "cstw,5,bc r1,0xf(rp)"
+  -
+    input:
+      bytes: [ 0x24, 0x5e, 0x37, 0x61 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "cstw,5,mb,bc r1,0xf(rp)"
+  -
+    input:
+      bytes: [ 0x24, 0x5e, 0x17, 0x61 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "cstw,5,ma,bc r1,0xf(rp)"
+  -
+    input:
+      bytes: [ 0x24, 0x43, 0x07, 0x41 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "cstw,5,bc r1,r3(rp)"
+  -
+    input:
+      bytes: [ 0x24, 0x43, 0x27, 0x41 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "cstw,5,s,bc r1,r3(rp)"
+  -
+    input:
+      bytes: [ 0x24, 0x43, 0x27, 0x61 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "cstw,5,sm,bc r1,r3(rp)"
diff --git a/tests/MC/HPPA/branch11.s.yaml b/tests/MC/HPPA/branch11.s.yaml
new file mode 100644
index 000000000..b520dcb78
--- /dev/null
+++ b/tests/MC/HPPA/branch11.s.yaml
@@ -0,0 +1,73 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xe8, 0x3f, 0x1f, 0x75 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "bl 0xffffffffffffffc0,r1"
+  -
+    input:
+      bytes: [ 0xe8, 0x3f, 0x1f, 0x6f ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "bl,n 0xffffffffffffffbc,r1"
+  -
+    input:
+      bytes: [ 0xe8, 0x41, 0x40, 0x00 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "blr r1,rp"
+  -
+    input:
+      bytes: [ 0xe8, 0x41, 0x40, 0x02 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "blr,n r1,rp"
+  -
+    input:
+      bytes: [ 0xe8, 0x41, 0xc0, 0x00 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "bv r1(rp)"
+  -
+    input:
+      bytes: [ 0xe8, 0x41, 0xc0, 0x02 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "bv,n r1(rp)"
+  -
+    input:
+      bytes: [ 0xe8, 0x5f, 0x3f, 0x45 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "gate 0xffffffffffffffa8,rp"
+  -
+    input:
+      bytes: [ 0xe8, 0x5f, 0x3f, 0x3f ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "gate,n 0xffffffffffffffa4,rp"
diff --git a/tests/MC/HPPA/branch20.s.yaml b/tests/MC/HPPA/branch20.s.yaml
new file mode 100644
index 000000000..603b6b5ca
--- /dev/null
+++ b/tests/MC/HPPA/branch20.s.yaml
@@ -0,0 +1,379 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xeb, 0xff, 0xb8, 0x9d ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "b,l 0xfffffffffffffc54,r31"
+  -
+    input:
+      bytes: [ 0xeb, 0xff, 0xb8, 0x97 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "b,l,n 0xfffffffffffffc50,r31"
+  -
+    input:
+      bytes: [ 0xeb, 0x9f, 0x38, 0x8d ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "b,gate 0xfffffffffffffc4c,ret0"
+  -
+    input:
+      bytes: [ 0xeb, 0x9f, 0x38, 0x87 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "b,gate,n 0xfffffffffffffc48,ret0"
+  -
+    input:
+      bytes: [ 0xeb, 0xff, 0x98, 0x7d ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "b,l,push 0xfffffffffffffc44,r31"
+  -
+    input:
+      bytes: [ 0xeb, 0xff, 0x98, 0x77 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "b,l,push,n 0xfffffffffffffc40,r31"
+  -
+    input:
+      bytes: [ 0xe8, 0x41, 0x40, 0x00 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "blr r1,rp"
+  -
+    input:
+      bytes: [ 0xe8, 0x41, 0x40, 0x02 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "blr,n r1,rp"
+  -
+    input:
+      bytes: [ 0xe8, 0x41, 0xc0, 0x00 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "bv r1(rp)"
+  -
+    input:
+      bytes: [ 0xe8, 0x41, 0xc0, 0x02 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "bv,n r1(rp)"
+  -
+    input:
+      bytes: [ 0xe0, 0x20, 0x40, 0x00 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "be 0(sr1,r1)"
+  -
+    input:
+      bytes: [ 0xe0, 0x20, 0x40, 0x02 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "be,n 0(sr1,r1)"
+  -
+    input:
+      bytes: [ 0xe4, 0x20, 0x40, 0x00 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "be,l 0(sr1,r1),sr0,r31"
+  -
+    input:
+      bytes: [ 0xe4, 0x20, 0x40, 0x02 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "be,l,n 0(sr1,r1),sr0,r31"
+  -
+    input:
+      bytes: [ 0xe8, 0x40, 0xd0, 0x00 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "bve (rp)"
+  -
+    input:
+      bytes: [ 0xe8, 0x40, 0xd0, 0x02 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "bve,n (rp)"
+  -
+    input:
+      bytes: [ 0xe8, 0x40, 0xd0, 0x01 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "bve,pop (rp)"
+  -
+    input:
+      bytes: [ 0xe8, 0x40, 0xd0, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "bve,pop,n (rp)"
+  -
+    input:
+      bytes: [ 0xe8, 0x20, 0xf0, 0x00 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "bve,l (r1),rp"
+  -
+    input:
+      bytes: [ 0xe8, 0x20, 0xf0, 0x02 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "bve,l,n (r1),rp"
+  -
+    input:
+      bytes: [ 0xe8, 0x20, 0xf0, 0x01 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "bve,l,push (r1),rp"
+  -
+    input:
+      bytes: [ 0xe8, 0x20, 0xf0, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "bve,l,push,n (r1),rp"
+  -
+    input:
+      bytes: [ 0xa0, 0x41, 0x17, 0xed ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "addb r1,rp,0xfffffffffffffbfc"
+  -
+    input:
+      bytes: [ 0xa0, 0x41, 0x37, 0xe5 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "addb,= r1,rp,0xfffffffffffffbf8"
+  -
+    input:
+      bytes: [ 0xa0, 0x41, 0x37, 0xdf ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "addb,=,n r1,rp,0xfffffffffffffbf4"
+  -
+    input:
+      bytes: [ 0xa4, 0x5e, 0x17, 0xd5 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "addib 0xf,rp,0xfffffffffffffbf0"
+  -
+    input:
+      bytes: [ 0xa4, 0x5e, 0x37, 0xcd ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "addib,= 0xf,rp,0xfffffffffffffbec"
+  -
+    input:
+      bytes: [ 0xa4, 0x5e, 0x37, 0xc7 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "addib,=,n 0xf,rp,0xfffffffffffffbe8"
+  -
+    input:
+      bytes: [ 0xc5, 0xe1, 0xd7, 0xbd ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "bb,>= r1,0xf,0xfffffffffffffbe4"
+  -
+    input:
+      bytes: [ 0xc5, 0xe1, 0xd7, 0xb7 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "bb,>=,n r1,0xf,0xfffffffffffffbe0"
+  -
+    input:
+      bytes: [ 0x80, 0x41, 0x17, 0xad ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpb r1,rp,0xfffffffffffffbdc"
+  -
+    input:
+      bytes: [ 0x80, 0x41, 0x37, 0xa5 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpb,= r1,rp,0xfffffffffffffbd8"
+  -
+    input:
+      bytes: [ 0x80, 0x41, 0x37, 0x9f ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpb,=,n r1,rp,0xfffffffffffffbd4"
+  -
+    input:
+      bytes: [ 0x84, 0x5e, 0x17, 0x95 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpib 0xf,rp,0xfffffffffffffbd0"
+  -
+    input:
+      bytes: [ 0x84, 0x5e, 0x37, 0x8d ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpib,= 0xf,rp,0xfffffffffffffbcc"
+  -
+    input:
+      bytes: [ 0x84, 0x5e, 0x37, 0x87 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpib,=,n 0xf,rp,0xfffffffffffffbc8"
+  -
+    input:
+      bytes: [ 0xc8, 0x41, 0x17, 0x7d ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "movb r1,rp,0xfffffffffffffbc4"
+  -
+    input:
+      bytes: [ 0xc8, 0x41, 0x37, 0x75 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "movb,= r1,rp,0xfffffffffffffbc0"
+  -
+    input:
+      bytes: [ 0xc8, 0x41, 0x37, 0x6f ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "movb,=,n r1,rp,0xfffffffffffffbbc"
+  -
+    input:
+      bytes: [ 0xcc, 0x5e, 0x17, 0x65 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "movib 0xf,rp,0xfffffffffffffbb8"
+  -
+    input:
+      bytes: [ 0xcc, 0x5e, 0x37, 0x5d ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "movib,= 0xf,rp,0xfffffffffffffbb4"
+  -
+    input:
+      bytes: [ 0xcc, 0x5e, 0x37, 0x57 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "movib,=,n 0xf,rp,0xfffffffffffffbb0"
diff --git a/tests/MC/HPPA/computation20.s.yaml b/tests/MC/HPPA/computation20.s.yaml
new file mode 100644
index 000000000..65bec6f04
--- /dev/null
+++ b/tests/MC/HPPA/computation20.s.yaml
@@ -0,0 +1,559 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x66, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "add,<= r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x07, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "add,c r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x57, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "add,c,>= r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x07, 0x23 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "add,dc,* r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x27, 0x23 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "add,dc,*= r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x0a, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "add,l r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x4a, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "add,l,< r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x0e, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "add,tsv r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x7e, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "add,tsv,> r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x0f, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "add,c,tsv r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x3f, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "add,c,tsv,<> r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x0f, 0x23 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "add,dc,tsv,* r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x5f, 0x23 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "add,dc,tsv,*>= r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x06, 0xc3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "shladd r1,3,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x0a, 0xc3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "shladd,l r1,3,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x0e, 0xc3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "shladd,tsv r1,3,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xce, 0xc3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "shladd,tsv,sv r1,3,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x04, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x04, 0xc3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub,tc r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x05, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub,b r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x0c, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub,tsv r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x0c, 0xc3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub,tsv,tc r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x0d, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub,b,tsv r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x6d, 0x23 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub,db,tsv,*<= r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x02, 0x43 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "or r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x22, 0x43 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "or,= r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x02, 0x83 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x62, 0x83 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor,<= r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x02, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "and r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x62, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "and,<= r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x00, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "andcm r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x60, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "andcm,<= r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x09, 0x83 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "uaddcm r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x49, 0x83 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "uaddcm,sbz r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x09, 0xc3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "uaddcm,tc r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x03, 0x83 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "uxor r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x43, 0x83 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "uxor,sbz r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x04, 0x43 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "ds r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0xa4, 0x43 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "ds,<<= r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x08, 0x83 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpclr r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x98, 0x83 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpclr,>>= r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x20, 0x0b, 0x82 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "dcor r1,rp"
+  -
+    input:
+      bytes: [ 0x08, 0x20, 0x0b, 0xc2 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "dcor,i r1,rp"
+  -
+    input:
+      bytes: [ 0x08, 0x20, 0x4b, 0xc2 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "dcor,i,sbz r1,rp"
+  -
+    input:
+      bytes: [ 0xb4, 0x22, 0x01, 0xbc ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "addi 0xde,r1,rp"
+  -
+    input:
+      bytes: [ 0xb4, 0x22, 0x09, 0xbc ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "addi,tsv 0xde,r1,rp"
+  -
+    input:
+      bytes: [ 0xb0, 0x22, 0x01, 0xbc ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "addi,tc 0xde,r1,rp"
+  -
+    input:
+      bytes: [ 0xb0, 0x22, 0x09, 0xbc ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "addi,tsv,tc 0xde,r1,rp"
+  -
+    input:
+      bytes: [ 0xb0, 0x22, 0x69, 0xbc ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "addi,tsv,tc,<= 0xde,r1,rp"
+  -
+    input:
+      bytes: [ 0x94, 0x22, 0x01, 0xbc ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "subi 0xde,r1,rp"
+  -
+    input:
+      bytes: [ 0x94, 0x22, 0x09, 0xbc ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "subi,tsv 0xde,r1,rp"
+  -
+    input:
+      bytes: [ 0x94, 0x22, 0x29, 0xbc ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "subi,tsv,= 0xde,r1,rp"
+  -
+    input:
+      bytes: [ 0x90, 0x43, 0x01, 0xbc ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpiclr 0xde,rp,r3"
+  -
+    input:
+      bytes: [ 0x90, 0x43, 0x91, 0xbc ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpiclr,>>= 0xde,rp,r3"
+  -
+    input:
+      bytes: [ 0xd0, 0x41, 0x0f, 0x83 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "shrpd,* r1,rp,3,r3"
+  -
+    input:
+      bytes: [ 0xd0, 0x41, 0x4f, 0x83 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "shrpd,*< r1,rp,3,r3"
+  -
+    input:
+      bytes: [ 0xd0, 0x41, 0x0b, 0x83 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "shrpw r1,rp,3,r3"
+  -
+    input:
+      bytes: [ 0xd0, 0x41, 0x4b, 0x83 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "shrpw,< r1,rp,3,r3"
+  -
+    input:
+      bytes: [ 0xd0, 0x22, 0x16, 0x1c ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "extrd,s,* r1,sar,4,rp"
+  -
+    input:
+      bytes: [ 0xd8, 0x22, 0x07, 0xdc ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "extrd,s,* r1,0x1e,4,rp"
+  -
+    input:
+      bytes: [ 0xd8, 0x22, 0x03, 0xdc ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "extrd,u,* r1,0x1e,4,rp"
+  -
+    input:
+      bytes: [ 0xd8, 0x22, 0xc3, 0xdc ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "extrd,u,*>= r1,0x1e,4,rp"
diff --git a/tests/MC/HPPA/copr_dw11.s.yaml b/tests/MC/HPPA/copr_dw11.s.yaml
new file mode 100644
index 000000000..80ae93735
--- /dev/null
+++ b/tests/MC/HPPA/copr_dw11.s.yaml
@@ -0,0 +1,361 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x24, 0x41, 0x40, 0xc3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "cldwx,3 r1(sr1,rp),r3"
+  -
+    input:
+      bytes: [ 0x24, 0x41, 0x60, 0xc3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "cldwx,3,s r1(sr1,rp),r3"
+  -
+    input:
+      bytes: [ 0x24, 0x41, 0x40, 0xe3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "cldwx,3,m r1(sr1,rp),r3"
+  -
+    input:
+      bytes: [ 0x24, 0x41, 0x60, 0xe3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "cldwx,3,sm r1(sr1,rp),r3"
+  -
+    input:
+      bytes: [ 0x24, 0x41, 0x68, 0xe3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "cldwx,3,sm,sl r1(sr1,rp),r3"
+  -
+    input:
+      bytes: [ 0x2c, 0x41, 0x40, 0xc3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "clddx,3 r1(sr1,rp),r3"
+  -
+    input:
+      bytes: [ 0x2c, 0x41, 0x60, 0xc3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "clddx,3,s r1(sr1,rp),r3"
+  -
+    input:
+      bytes: [ 0x2c, 0x41, 0x40, 0xe3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "clddx,3,m r1(sr1,rp),r3"
+  -
+    input:
+      bytes: [ 0x2c, 0x41, 0x60, 0xe3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "clddx,3,sm r1(sr1,rp),r3"
+  -
+    input:
+      bytes: [ 0x2c, 0x41, 0x68, 0xe3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "clddx,3,sm,sl r1(sr1,rp),r3"
+  -
+    input:
+      bytes: [ 0x24, 0x62, 0x42, 0xc1 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "cstwx,3 r1,rp(sr1,r3)"
+  -
+    input:
+      bytes: [ 0x24, 0x62, 0x62, 0xc1 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "cstwx,3,s r1,rp(sr1,r3)"
+  -
+    input:
+      bytes: [ 0x24, 0x62, 0x42, 0xe1 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "cstwx,3,m r1,rp(sr1,r3)"
+  -
+    input:
+      bytes: [ 0x24, 0x62, 0x46, 0xe1 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "cstwx,3,m,bc r1,rp(sr1,r3)"
+  -
+    input:
+      bytes: [ 0x24, 0x62, 0x62, 0xe1 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "cstwx,3,sm r1,rp(sr1,r3)"
+  -
+    input:
+      bytes: [ 0x24, 0x62, 0x6a, 0xe1 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "cstwx,3,sm,sl r1,rp(sr1,r3)"
+  -
+    input:
+      bytes: [ 0x2c, 0x62, 0x42, 0xc1 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "cstdx,3 r1,rp(sr1,r3)"
+  -
+    input:
+      bytes: [ 0x2c, 0x62, 0x62, 0xc1 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "cstdx,3,s r1,rp(sr1,r3)"
+  -
+    input:
+      bytes: [ 0x2c, 0x62, 0x42, 0xe1 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "cstdx,3,m r1,rp(sr1,r3)"
+  -
+    input:
+      bytes: [ 0x2c, 0x62, 0x46, 0xe1 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "cstdx,3,m,bc r1,rp(sr1,r3)"
+  -
+    input:
+      bytes: [ 0x2c, 0x62, 0x62, 0xe1 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "cstdx,3,sm r1,rp(sr1,r3)"
+  -
+    input:
+      bytes: [ 0x2c, 0x62, 0x6a, 0xe1 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "cstdx,3,sm,sl r1,rp(sr1,r3)"
+  -
+    input:
+      bytes: [ 0x24, 0x3e, 0x50, 0xc2 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "cldws,3 0xf(sr1,r1),rp"
+  -
+    input:
+      bytes: [ 0x24, 0x3e, 0x50, 0xe2 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "cldws,3,ma 0xf(sr1,r1),rp"
+  -
+    input:
+      bytes: [ 0x24, 0x3e, 0x70, 0xe2 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "cldws,3,mb 0xf(sr1,r1),rp"
+  -
+    input:
+      bytes: [ 0x24, 0x3e, 0x78, 0xe2 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "cldws,3,mb,sl 0xf(sr1,r1),rp"
+  -
+    input:
+      bytes: [ 0x2c, 0x3e, 0x50, 0xc2 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "cldds,3 0xf(sr1,r1),rp"
+  -
+    input:
+      bytes: [ 0x2c, 0x3e, 0x50, 0xe2 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "cldds,3,ma 0xf(sr1,r1),rp"
+  -
+    input:
+      bytes: [ 0x2c, 0x3e, 0x70, 0xe2 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "cldds,3,mb 0xf(sr1,r1),rp"
+  -
+    input:
+      bytes: [ 0x2c, 0x3e, 0x78, 0xe2 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "cldds,3,mb,sl 0xf(sr1,r1),rp"
+  -
+    input:
+      bytes: [ 0x24, 0x5e, 0x52, 0xc1 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "cstws,3 r1,0xf(sr1,rp)"
+  -
+    input:
+      bytes: [ 0x24, 0x5e, 0x52, 0xe1 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "cstws,3,ma r1,0xf(sr1,rp)"
+  -
+    input:
+      bytes: [ 0x24, 0x5e, 0x56, 0xe1 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "cstws,3,ma,bc r1,0xf(sr1,rp)"
+  -
+    input:
+      bytes: [ 0x24, 0x5e, 0x72, 0xe1 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "cstws,3,mb r1,0xf(sr1,rp)"
+  -
+    input:
+      bytes: [ 0x24, 0x5e, 0x7a, 0xe1 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "cstws,3,mb,sl r1,0xf(sr1,rp)"
+  -
+    input:
+      bytes: [ 0x2c, 0x5e, 0x52, 0xc1 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "cstds,3 r1,0xf(sr1,rp)"
+  -
+    input:
+      bytes: [ 0x2c, 0x5e, 0x52, 0xe1 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "cstds,3,ma r1,0xf(sr1,rp)"
+  -
+    input:
+      bytes: [ 0x2c, 0x5e, 0x56, 0xe1 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "cstds,3,ma,bc r1,0xf(sr1,rp)"
+  -
+    input:
+      bytes: [ 0x2c, 0x5e, 0x72, 0xe1 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "cstds,3,mb r1,0xf(sr1,rp)"
+  -
+    input:
+      bytes: [ 0x2c, 0x5e, 0x7a, 0xe1 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "cstds,3,mb,sl r1,0xf(sr1,rp)"
diff --git a/tests/MC/HPPA/float11.s.yaml b/tests/MC/HPPA/float11.s.yaml
new file mode 100644
index 000000000..d475cd21f
--- /dev/null
+++ b/tests/MC/HPPA/float11.s.yaml
@@ -0,0 +1,793 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x30, 0x00, 0x00, 0x20 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "copr,0,0,n"
+  -
+    input:
+      bytes: [ 0x30, 0x00, 0x00, 0x62 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "copr,1,2,n"
+  -
+    input:
+      bytes: [ 0x30, 0x20, 0x40, 0x02 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcpy,sgl fpe2,fpe4"
+  -
+    input:
+      bytes: [ 0x30, 0x20, 0x48, 0x02 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcpy,dbl fpe2,fpe4"
+  -
+    input:
+      bytes: [ 0x30, 0x20, 0x58, 0x02 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcpy,quad fpe2,fpe4"
+  -
+    input:
+      bytes: [ 0x30, 0x20, 0x60, 0x02 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "fabs,sgl fpe2,fpe4"
+  -
+    input:
+      bytes: [ 0x30, 0x20, 0x68, 0x02 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "fabs,dbl fpe2,fpe4"
+  -
+    input:
+      bytes: [ 0x30, 0x20, 0x78, 0x02 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "fabs,quad fpe2,fpe4"
+  -
+    input:
+      bytes: [ 0x30, 0x20, 0x80, 0x02 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsqrt,sgl fpe2,fpe4"
+  -
+    input:
+      bytes: [ 0x30, 0x20, 0x88, 0x02 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsqrt,dbl fpe2,fpe4"
+  -
+    input:
+      bytes: [ 0x30, 0x20, 0x98, 0x02 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsqrt,quad fpe2,fpe4"
+  -
+    input:
+      bytes: [ 0x30, 0x20, 0xa0, 0x02 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "frnd,sgl fpe2,fpe4"
+  -
+    input:
+      bytes: [ 0x30, 0x20, 0xa8, 0x02 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "frnd,dbl fpe2,fpe4"
+  -
+    input:
+      bytes: [ 0x30, 0x20, 0xb8, 0x02 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "frnd,quad fpe2,fpe4"
+  -
+    input:
+      bytes: [ 0x30, 0x20, 0x22, 0x02 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcnvff,sgl,dbl fpe2,fpe4"
+  -
+    input:
+      bytes: [ 0x30, 0x20, 0x62, 0x02 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcnvff,sgl,quad fpe2,fpe4"
+  -
+    input:
+      bytes: [ 0x30, 0x20, 0x0a, 0x02 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcnvff,dbl,sgl fpe2,fpe4"
+  -
+    input:
+      bytes: [ 0x30, 0x20, 0x6a, 0x02 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcnvff,dbl,quad fpe2,fpe4"
+  -
+    input:
+      bytes: [ 0x30, 0x20, 0x02, 0x02 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcnvff,sgl,sgl fpe2,fpe4"
+  -
+    input:
+      bytes: [ 0x30, 0x20, 0x2a, 0x02 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcnvff,dbl,dbl fpe2,fpe4"
+  -
+    input:
+      bytes: [ 0x30, 0x20, 0x7a, 0x02 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcnvff,quad,quad fpe2,fpe4"
+  -
+    input:
+      bytes: [ 0x30, 0x20, 0xa2, 0x02 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcnvxf,sgl,dbl fpe2,fpe4"
+  -
+    input:
+      bytes: [ 0x30, 0x20, 0xe2, 0x02 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcnvxf,sgl,quad fpe2,fpe4"
+  -
+    input:
+      bytes: [ 0x30, 0x20, 0x8a, 0x02 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcnvxf,dbl,sgl fpe2,fpe4"
+  -
+    input:
+      bytes: [ 0x30, 0x20, 0xea, 0x02 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcnvxf,dbl,quad fpe2,fpe4"
+  -
+    input:
+      bytes: [ 0x30, 0x20, 0x82, 0x02 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcnvxf,sgl,sgl fpe2,fpe4"
+  -
+    input:
+      bytes: [ 0x30, 0x20, 0xaa, 0x02 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcnvxf,dbl,dbl fpe2,fpe4"
+  -
+    input:
+      bytes: [ 0x30, 0x20, 0xfa, 0x02 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcnvxf,quad,quad fpe2,fpe4"
+  -
+    input:
+      bytes: [ 0x30, 0x21, 0x22, 0x02 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcnvfx,sgl,dbl fpe2,fpe4"
+  -
+    input:
+      bytes: [ 0x30, 0x21, 0x62, 0x02 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcnvfx,sgl,quad fpe2,fpe4"
+  -
+    input:
+      bytes: [ 0x30, 0x21, 0x0a, 0x02 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcnvfx,dbl,sgl fpe2,fpe4"
+  -
+    input:
+      bytes: [ 0x30, 0x21, 0x6a, 0x02 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcnvfx,dbl,quad fpe2,fpe4"
+  -
+    input:
+      bytes: [ 0x30, 0x21, 0x02, 0x02 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcnvfx,sgl,sgl fpe2,fpe4"
+  -
+    input:
+      bytes: [ 0x30, 0x21, 0x2a, 0x02 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcnvfx,dbl,dbl fpe2,fpe4"
+  -
+    input:
+      bytes: [ 0x30, 0x21, 0x7a, 0x02 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcnvfx,quad,quad fpe2,fpe4"
+  -
+    input:
+      bytes: [ 0x30, 0x21, 0xa2, 0x02 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcnvfxt,sgl,dbl fpe2,fpe4"
+  -
+    input:
+      bytes: [ 0x30, 0x21, 0xe2, 0x02 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcnvfxt,sgl,quad fpe2,fpe4"
+  -
+    input:
+      bytes: [ 0x30, 0x21, 0x8a, 0x02 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcnvfxt,dbl,sgl fpe2,fpe4"
+  -
+    input:
+      bytes: [ 0x30, 0x21, 0xea, 0x02 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcnvfxt,dbl,quad fpe2,fpe4"
+  -
+    input:
+      bytes: [ 0x30, 0x21, 0x82, 0x02 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcnvfxt,sgl,sgl fpe2,fpe4"
+  -
+    input:
+      bytes: [ 0x30, 0x21, 0xaa, 0x02 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcnvfxt,dbl,dbl fpe2,fpe4"
+  -
+    input:
+      bytes: [ 0x30, 0x21, 0xfa, 0x02 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcnvfxt,quad,quad fpe2,fpe4"
+  -
+    input:
+      bytes: [ 0x30, 0x22, 0x04, 0x00 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmp,sgl,false? fpe2,fpe4"
+  -
+    input:
+      bytes: [ 0x30, 0x22, 0x04, 0x01 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmp,sgl,false fpe2,fpe4"
+  -
+    input:
+      bytes: [ 0x30, 0x22, 0x04, 0x02 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmp,sgl,? fpe2,fpe4"
+  -
+    input:
+      bytes: [ 0x30, 0x22, 0x04, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmp,sgl,!<=> fpe2,fpe4"
+  -
+    input:
+      bytes: [ 0x30, 0x22, 0x04, 0x04 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmp,sgl,= fpe2,fpe4"
+  -
+    input:
+      bytes: [ 0x30, 0x22, 0x04, 0x05 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmp,sgl,=t fpe2,fpe4"
+  -
+    input:
+      bytes: [ 0x30, 0x22, 0x04, 0x06 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmp,sgl,?= fpe2,fpe4"
+  -
+    input:
+      bytes: [ 0x30, 0x22, 0x04, 0x07 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmp,sgl,!<> fpe2,fpe4"
+  -
+    input:
+      bytes: [ 0x30, 0x22, 0x04, 0x08 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmp,sgl,!?>= fpe2,fpe4"
+  -
+    input:
+      bytes: [ 0x30, 0x22, 0x04, 0x09 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmp,sgl,< fpe2,fpe4"
+  -
+    input:
+      bytes: [ 0x30, 0x22, 0x04, 0x0a ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmp,sgl,?< fpe2,fpe4"
+  -
+    input:
+      bytes: [ 0x30, 0x22, 0x04, 0x0b ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmp,sgl,!>= fpe2,fpe4"
+  -
+    input:
+      bytes: [ 0x30, 0x22, 0x04, 0x0c ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmp,sgl,!?> fpe2,fpe4"
+  -
+    input:
+      bytes: [ 0x30, 0x22, 0x04, 0x0d ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmp,sgl,<= fpe2,fpe4"
+  -
+    input:
+      bytes: [ 0x30, 0x22, 0x04, 0x0e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmp,sgl,?<= fpe2,fpe4"
+  -
+    input:
+      bytes: [ 0x30, 0x22, 0x04, 0x0f ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmp,sgl,!> fpe2,fpe4"
+  -
+    input:
+      bytes: [ 0x30, 0x22, 0x04, 0x10 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmp,sgl,!?<= fpe2,fpe4"
+  -
+    input:
+      bytes: [ 0x30, 0x22, 0x04, 0x11 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmp,sgl,> fpe2,fpe4"
+  -
+    input:
+      bytes: [ 0x30, 0x22, 0x04, 0x12 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmp,sgl,?> fpe2,fpe4"
+  -
+    input:
+      bytes: [ 0x30, 0x22, 0x04, 0x13 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmp,sgl,!<= fpe2,fpe4"
+  -
+    input:
+      bytes: [ 0x30, 0x22, 0x04, 0x14 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmp,sgl,!?< fpe2,fpe4"
+  -
+    input:
+      bytes: [ 0x30, 0x22, 0x04, 0x15 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmp,sgl,>= fpe2,fpe4"
+  -
+    input:
+      bytes: [ 0x30, 0x22, 0x04, 0x16 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmp,sgl,?>= fpe2,fpe4"
+  -
+    input:
+      bytes: [ 0x30, 0x22, 0x04, 0x17 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmp,sgl,!< fpe2,fpe4"
+  -
+    input:
+      bytes: [ 0x30, 0x22, 0x04, 0x18 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmp,sgl,!?= fpe2,fpe4"
+  -
+    input:
+      bytes: [ 0x30, 0x22, 0x04, 0x19 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmp,sgl,<> fpe2,fpe4"
+  -
+    input:
+      bytes: [ 0x30, 0x22, 0x04, 0x1a ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmp,sgl,!= fpe2,fpe4"
+  -
+    input:
+      bytes: [ 0x30, 0x22, 0x04, 0x1b ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmp,sgl,!=t fpe2,fpe4"
+  -
+    input:
+      bytes: [ 0x30, 0x22, 0x04, 0x1c ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmp,sgl,!? fpe2,fpe4"
+  -
+    input:
+      bytes: [ 0x30, 0x22, 0x04, 0x1d ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmp,sgl,<=> fpe2,fpe4"
+  -
+    input:
+      bytes: [ 0x30, 0x22, 0x04, 0x1e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmp,sgl,true? fpe2,fpe4"
+  -
+    input:
+      bytes: [ 0x30, 0x22, 0x04, 0x1f ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmp,sgl,true fpe2,fpe4"
+  -
+    input:
+      bytes: [ 0x30, 0x00, 0x24, 0x20 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "ftest"
+  -
+    input:
+      bytes: [ 0x30, 0x22, 0x06, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd,sgl fpe2,fpe4,fpe6"
+  -
+    input:
+      bytes: [ 0x30, 0x22, 0x0e, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd,dbl fpe2,fpe4,fpe6"
+  -
+    input:
+      bytes: [ 0x30, 0x22, 0x1e, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd,quad fpe2,fpe4,fpe6"
+  -
+    input:
+      bytes: [ 0x30, 0x22, 0x26, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub,sgl fpe2,fpe4,fpe6"
+  -
+    input:
+      bytes: [ 0x30, 0x22, 0x2e, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub,dbl fpe2,fpe4,fpe6"
+  -
+    input:
+      bytes: [ 0x30, 0x22, 0x3e, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub,quad fpe2,fpe4,fpe6"
+  -
+    input:
+      bytes: [ 0x30, 0x22, 0x46, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmpy,sgl fpe2,fpe4,fpe6"
+  -
+    input:
+      bytes: [ 0x30, 0x22, 0x4e, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmpy,dbl fpe2,fpe4,fpe6"
+  -
+    input:
+      bytes: [ 0x30, 0x22, 0x5e, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmpy,quad fpe2,fpe4,fpe6"
+  -
+    input:
+      bytes: [ 0x30, 0x22, 0x66, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdiv,sgl fpe2,fpe4,fpe6"
+  -
+    input:
+      bytes: [ 0x30, 0x22, 0x6e, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdiv,dbl fpe2,fpe4,fpe6"
+  -
+    input:
+      bytes: [ 0x30, 0x22, 0x7e, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdiv,quad fpe2,fpe4,fpe6"
+  -
+    input:
+      bytes: [ 0x38, 0x22, 0x47, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "xmpyu fpe2,fpe4,fpe6"
diff --git a/tests/MC/HPPA/float20.s.yaml b/tests/MC/HPPA/float20.s.yaml
new file mode 100644
index 000000000..744b03acd
--- /dev/null
+++ b/tests/MC/HPPA/float20.s.yaml
@@ -0,0 +1,505 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x24, 0x2a, 0x10, 0x14 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "fldw 5(r1),fr20"
+  -
+    input:
+      bytes: [ 0x24, 0x2a, 0x30, 0x34 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "fldw,mb 5(r1),fr20"
+  -
+    input:
+      bytes: [ 0x24, 0x2a, 0x10, 0x34 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "fldw,ma 5(r1),fr20"
+  -
+    input:
+      bytes: [ 0x24, 0x22, 0x00, 0x14 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "fldw rp(r1),fr20"
+  -
+    input:
+      bytes: [ 0x24, 0x22, 0x20, 0x14 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "fldw,s rp(r1),fr20"
+  -
+    input:
+      bytes: [ 0x24, 0x22, 0x20, 0x34 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "fldw,sm rp(r1),fr20"
+  -
+    input:
+      bytes: [ 0x24, 0x22, 0x00, 0x34 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "fldw,m rp(r1),fr20"
+  -
+    input:
+      bytes: [ 0x2c, 0x2a, 0x10, 0x14 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "fldd 5(r1),fr20"
+  -
+    input:
+      bytes: [ 0x2c, 0x2a, 0x30, 0x34 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "fldd,mb 5(r1),fr20"
+  -
+    input:
+      bytes: [ 0x2c, 0x2a, 0x10, 0x34 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "fldd,ma 5(r1),fr20"
+  -
+    input:
+      bytes: [ 0x2c, 0x22, 0x00, 0x14 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "fldd rp(r1),fr20"
+  -
+    input:
+      bytes: [ 0x2c, 0x22, 0x20, 0x14 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "fldd,s rp(r1),fr20"
+  -
+    input:
+      bytes: [ 0x2c, 0x22, 0x20, 0x34 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "fldd,sm rp(r1),fr20"
+  -
+    input:
+      bytes: [ 0x2c, 0x22, 0x00, 0x34 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "fldd,m rp(r1),fr20"
+  -
+    input:
+      bytes: [ 0x24, 0x5e, 0x12, 0x14 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "fstw fr20,0xf(rp)"
+  -
+    input:
+      bytes: [ 0x24, 0x5e, 0x32, 0x34 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "fstw,mb fr20,0xf(rp)"
+  -
+    input:
+      bytes: [ 0x24, 0x5e, 0x12, 0x34 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "fstw,ma fr20,0xf(rp)"
+  -
+    input:
+      bytes: [ 0x24, 0x41, 0x06, 0x14 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "fstw,bc fr20,r1(rp)"
+  -
+    input:
+      bytes: [ 0x24, 0x41, 0x26, 0x14 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "fstw,s,bc fr20,r1(rp)"
+  -
+    input:
+      bytes: [ 0x24, 0x41, 0x26, 0x34 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "fstw,sm,bc fr20,r1(rp)"
+  -
+    input:
+      bytes: [ 0x24, 0x41, 0x06, 0x34 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "fstw,m,bc fr20,r1(rp)"
+  -
+    input:
+      bytes: [ 0x2c, 0x5e, 0x12, 0x14 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "fstd fr20,0xf(rp)"
+  -
+    input:
+      bytes: [ 0x2c, 0x5e, 0x32, 0x34 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "fstd,mb fr20,0xf(rp)"
+  -
+    input:
+      bytes: [ 0x2c, 0x5e, 0x12, 0x34 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "fstd,ma fr20,0xf(rp)"
+  -
+    input:
+      bytes: [ 0x2c, 0x41, 0x06, 0x14 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "fstd,bc fr20,r1(rp)"
+  -
+    input:
+      bytes: [ 0x2c, 0x41, 0x26, 0x14 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "fstd,s,bc fr20,r1(rp)"
+  -
+    input:
+      bytes: [ 0x2c, 0x41, 0x26, 0x34 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "fstd,sm,bc fr20,r1(rp)"
+  -
+    input:
+      bytes: [ 0x2c, 0x41, 0x06, 0x34 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "fstd,m,bc fr20,r1(rp)"
+  -
+    input:
+      bytes: [ 0x30, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "fid"
+  -
+    input:
+      bytes: [ 0x32, 0x80, 0x40, 0x15 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcpy,sgl fr20,fr21"
+  -
+    input:
+      bytes: [ 0x32, 0x80, 0x60, 0x15 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "fabs,sgl fr20,fr21"
+  -
+    input:
+      bytes: [ 0x32, 0x80, 0x80, 0x15 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsqrt,sgl fr20,fr21"
+  -
+    input:
+      bytes: [ 0x32, 0x80, 0xa0, 0x15 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "frnd,sgl fr20,fr21"
+  -
+    input:
+      bytes: [ 0x32, 0x80, 0xc0, 0x15 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "fneg,sgl fr20,fr21"
+  -
+    input:
+      bytes: [ 0x32, 0x80, 0xe0, 0x15 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "fnegabs,sgl fr20,fr21"
+  -
+    input:
+      bytes: [ 0x32, 0x80, 0x22, 0x15 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcnv,sgl,dbl fr20,fr21"
+  -
+    input:
+      bytes: [ 0x32, 0x80, 0xa2, 0x15 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcnv,w,dbl fr20,fr21"
+  -
+    input:
+      bytes: [ 0x32, 0x95, 0x04, 0x04 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmp,sgl,= fr20,fr21"
+  -
+    input:
+      bytes: [ 0x32, 0x95, 0x44, 0x04 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmp,sgl,= fr20,fr21,1"
+  -
+    input:
+      bytes: [ 0x30, 0x00, 0x64, 0x20 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "ftest 1"
+  -
+    input:
+      bytes: [ 0x30, 0x00, 0x24, 0x21 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "ftest,acc"
+  -
+    input:
+      bytes: [ 0x30, 0x00, 0x24, 0x25 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "ftest,acc8"
+  -
+    input:
+      bytes: [ 0x30, 0x00, 0x24, 0x29 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "ftest,acc6"
+  -
+    input:
+      bytes: [ 0x30, 0x00, 0x24, 0x2d ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "ftest,acc4"
+  -
+    input:
+      bytes: [ 0x30, 0x00, 0x24, 0x31 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "ftest,acc2"
+  -
+    input:
+      bytes: [ 0x30, 0x00, 0x24, 0x22 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "ftest,rej"
+  -
+    input:
+      bytes: [ 0x30, 0x00, 0x24, 0x26 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "ftest,rej8"
+  -
+    input:
+      bytes: [ 0x32, 0x95, 0x06, 0x16 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd,sgl fr20,fr21,fr22"
+  -
+    input:
+      bytes: [ 0x32, 0x95, 0x26, 0x16 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub,sgl fr20,fr21,fr22"
+  -
+    input:
+      bytes: [ 0x32, 0x95, 0x46, 0x16 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmpy,sgl fr20,fr21,fr22"
+  -
+    input:
+      bytes: [ 0x32, 0x95, 0x66, 0x16 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdiv,sgl fr20,fr21,fr22"
+  -
+    input:
+      bytes: [ 0x3a, 0x95, 0x47, 0x16 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "xmpyu fr20,fr21,fr22"
+  -
+    input:
+      bytes: [ 0x18, 0x85, 0x41, 0xe6 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmpyadd,sgl fr20L,fr21L,fr22L,fr23L,fr24L"
+  -
+    input:
+      bytes: [ 0x98, 0x85, 0x41, 0xe6 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmpysub,sgl fr20L,fr21L,fr22L,fr23L,fr24L"
+  -
+    input:
+      bytes: [ 0xba, 0x95, 0xa4, 0x17 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmpyfadd,sgl fr20,fr21,fr22,fr23"
+  -
+    input:
+      bytes: [ 0xba, 0x95, 0xa4, 0x37 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmpynfadd,sgl fr20,fr21,fr22,fr23"
diff --git a/tests/MC/HPPA/index_mem11.s.yaml b/tests/MC/HPPA/index_mem11.s.yaml
new file mode 100644
index 000000000..72c71b1b0
--- /dev/null
+++ b/tests/MC/HPPA/index_mem11.s.yaml
@@ -0,0 +1,784 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x0c, 0x20, 0x40, 0x02 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldbx flags(sr1,r1),rp"
+  -
+    input:
+      bytes: [ 0x0c, 0x20, 0x60, 0x02 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldbx,s flags(sr1,r1),rp"
+  -
+    input:
+      bytes: [ 0x0c, 0x20, 0x40, 0x22 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldbx,m flags(sr1,r1),rp"
+  -
+    input:
+      bytes: [ 0x0c, 0x20, 0x60, 0x22 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldbx,sm flags(sr1,r1),rp"
+  -
+    input:
+      bytes: [ 0x0c, 0x20, 0x68, 0x02 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldbx,s,sl flags(sr1,r1),rp"
+  -
+    input:
+      bytes: [ 0x0c, 0x20, 0x48, 0x22 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldbx,m,sl flags(sr1,r1),rp"
+  -
+    input:
+      bytes: [ 0x0c, 0x20, 0x68, 0x22 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldbx,sm,sl flags(sr1,r1),rp"
+  -
+    input:
+      bytes: [ 0x0c, 0x20, 0x40, 0x42 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldhx flags(sr1,r1),rp"
+  -
+    input:
+      bytes: [ 0x0c, 0x20, 0x60, 0x42 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldhx,s flags(sr1,r1),rp"
+  -
+    input:
+      bytes: [ 0x0c, 0x20, 0x40, 0x62 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldhx,m flags(sr1,r1),rp"
+  -
+    input:
+      bytes: [ 0x0c, 0x20, 0x60, 0x62 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldhx,sm flags(sr1,r1),rp"
+  -
+    input:
+      bytes: [ 0x0c, 0x20, 0x68, 0x42 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldhx,s,sl flags(sr1,r1),rp"
+  -
+    input:
+      bytes: [ 0x0c, 0x20, 0x48, 0x62 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldhx,m,sl flags(sr1,r1),rp"
+  -
+    input:
+      bytes: [ 0x0c, 0x20, 0x68, 0x62 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldhx,sm,sl flags(sr1,r1),rp"
+  -
+    input:
+      bytes: [ 0x0c, 0x20, 0x40, 0x82 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldwx flags(sr1,r1),rp"
+  -
+    input:
+      bytes: [ 0x0c, 0x20, 0x60, 0x82 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldwx,s flags(sr1,r1),rp"
+  -
+    input:
+      bytes: [ 0x0c, 0x20, 0x40, 0xa2 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldwx,m flags(sr1,r1),rp"
+  -
+    input:
+      bytes: [ 0x0c, 0x20, 0x60, 0xa2 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldwx,sm flags(sr1,r1),rp"
+  -
+    input:
+      bytes: [ 0x0c, 0x20, 0x68, 0x82 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldwx,s,sl flags(sr1,r1),rp"
+  -
+    input:
+      bytes: [ 0x0c, 0x20, 0x48, 0xa2 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldwx,m,sl flags(sr1,r1),rp"
+  -
+    input:
+      bytes: [ 0x0c, 0x20, 0x68, 0xa2 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldwx,sm,sl flags(sr1,r1),rp"
+  -
+    input:
+      bytes: [ 0x0c, 0x20, 0x01, 0x82 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldwax flags(r1),rp"
+  -
+    input:
+      bytes: [ 0x0c, 0x20, 0x21, 0x82 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldwax,s flags(r1),rp"
+  -
+    input:
+      bytes: [ 0x0c, 0x20, 0x01, 0xa2 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldwax,m flags(r1),rp"
+  -
+    input:
+      bytes: [ 0x0c, 0x20, 0x21, 0xa2 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldwax,sm flags(r1),rp"
+  -
+    input:
+      bytes: [ 0x0c, 0x20, 0x29, 0x82 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldwax,s,sl flags(r1),rp"
+  -
+    input:
+      bytes: [ 0x0c, 0x20, 0x09, 0xa2 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldwax,m,sl flags(r1),rp"
+  -
+    input:
+      bytes: [ 0x0c, 0x20, 0x29, 0xa2 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldwax,sm,sl flags(r1),rp"
+  -
+    input:
+      bytes: [ 0x0c, 0x20, 0x41, 0xc2 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldcwx flags(sr1,r1),rp"
+  -
+    input:
+      bytes: [ 0x0c, 0x20, 0x61, 0xc2 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldcwx,s flags(sr1,r1),rp"
+  -
+    input:
+      bytes: [ 0x0c, 0x20, 0x41, 0xe2 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldcwx,m flags(sr1,r1),rp"
+  -
+    input:
+      bytes: [ 0x0c, 0x20, 0x61, 0xe2 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldcwx,sm flags(sr1,r1),rp"
+  -
+    input:
+      bytes: [ 0x0c, 0x20, 0x65, 0xc2 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldcwx,s,co flags(sr1,r1),rp"
+  -
+    input:
+      bytes: [ 0x0c, 0x20, 0x45, 0xe2 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldcwx,m,co flags(sr1,r1),rp"
+  -
+    input:
+      bytes: [ 0x0c, 0x20, 0x65, 0xe2 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldcwx,sm,co flags(sr1,r1),rp"
+  -
+    input:
+      bytes: [ 0x0c, 0x3e, 0x50, 0x02 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldbs 0xf(sr1,r1),rp"
+  -
+    input:
+      bytes: [ 0x0c, 0x3e, 0x50, 0x22 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldbs,ma 0xf(sr1,r1),rp"
+  -
+    input:
+      bytes: [ 0x0c, 0x3e, 0x70, 0x22 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldbs,mb 0xf(sr1,r1),rp"
+  -
+    input:
+      bytes: [ 0x0c, 0x3e, 0x58, 0x22 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldbs,ma,sl 0xf(sr1,r1),rp"
+  -
+    input:
+      bytes: [ 0x0c, 0x3e, 0x78, 0x22 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldbs,mb,sl 0xf(sr1,r1),rp"
+  -
+    input:
+      bytes: [ 0x0c, 0x3e, 0x50, 0x42 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldhs 0xf(sr1,r1),rp"
+  -
+    input:
+      bytes: [ 0x0c, 0x3e, 0x50, 0x62 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldhs,ma 0xf(sr1,r1),rp"
+  -
+    input:
+      bytes: [ 0x0c, 0x3e, 0x70, 0x62 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldhs,mb 0xf(sr1,r1),rp"
+  -
+    input:
+      bytes: [ 0x0c, 0x3e, 0x58, 0x62 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldhs,ma,sl 0xf(sr1,r1),rp"
+  -
+    input:
+      bytes: [ 0x0c, 0x3e, 0x78, 0x62 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldhs,mb,sl 0xf(sr1,r1),rp"
+  -
+    input:
+      bytes: [ 0x0c, 0x3e, 0x50, 0x82 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldws 0xf(sr1,r1),rp"
+  -
+    input:
+      bytes: [ 0x0c, 0x3e, 0x50, 0xa2 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldws,ma 0xf(sr1,r1),rp"
+  -
+    input:
+      bytes: [ 0x0c, 0x3e, 0x70, 0xa2 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldws,mb 0xf(sr1,r1),rp"
+  -
+    input:
+      bytes: [ 0x0c, 0x3e, 0x58, 0xa2 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldws,ma,sl 0xf(sr1,r1),rp"
+  -
+    input:
+      bytes: [ 0x0c, 0x3e, 0x78, 0xa2 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldws,mb,sl 0xf(sr1,r1),rp"
+  -
+    input:
+      bytes: [ 0x0c, 0x3e, 0x11, 0x82 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldwas 0xf(r1),rp"
+  -
+    input:
+      bytes: [ 0x0c, 0x3e, 0x11, 0xa2 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldwas,ma 0xf(r1),rp"
+  -
+    input:
+      bytes: [ 0x0c, 0x3e, 0x31, 0xa2 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldwas,mb 0xf(r1),rp"
+  -
+    input:
+      bytes: [ 0x0c, 0x3e, 0x19, 0xa2 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldwas,ma,sl 0xf(r1),rp"
+  -
+    input:
+      bytes: [ 0x0c, 0x3e, 0x39, 0xa2 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldwas,mb,sl 0xf(r1),rp"
+  -
+    input:
+      bytes: [ 0x0c, 0x3e, 0x51, 0xc2 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldcws 0xf(sr1,r1),rp"
+  -
+    input:
+      bytes: [ 0x0c, 0x3e, 0x51, 0xe2 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldcws,ma 0xf(sr1,r1),rp"
+  -
+    input:
+      bytes: [ 0x0c, 0x3e, 0x71, 0xe2 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldcws,mb 0xf(sr1,r1),rp"
+  -
+    input:
+      bytes: [ 0x0c, 0x3e, 0x55, 0xe2 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldcws,ma,co 0xf(sr1,r1),rp"
+  -
+    input:
+      bytes: [ 0x0c, 0x3e, 0x75, 0xe2 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldcws,mb,co 0xf(sr1,r1),rp"
+  -
+    input:
+      bytes: [ 0x0c, 0x41, 0x52, 0x1e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "stbs r1,0xf(sr1,rp)"
+  -
+    input:
+      bytes: [ 0x0c, 0x41, 0x52, 0x3e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "stbs,ma r1,0xf(sr1,rp)"
+  -
+    input:
+      bytes: [ 0x0c, 0x41, 0x72, 0x3e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "stbs,mb r1,0xf(sr1,rp)"
+  -
+    input:
+      bytes: [ 0x0c, 0x41, 0x56, 0x3e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "stbs,ma,bc r1,0xf(sr1,rp)"
+  -
+    input:
+      bytes: [ 0x0c, 0x41, 0x7a, 0x3e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "stbs,mb,sl r1,0xf(sr1,rp)"
+  -
+    input:
+      bytes: [ 0x0c, 0x41, 0x52, 0x5e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sths r1,0xf(sr1,rp)"
+  -
+    input:
+      bytes: [ 0x0c, 0x41, 0x52, 0x7e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sths,ma r1,0xf(sr1,rp)"
+  -
+    input:
+      bytes: [ 0x0c, 0x41, 0x72, 0x7e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sths,mb r1,0xf(sr1,rp)"
+  -
+    input:
+      bytes: [ 0x0c, 0x41, 0x56, 0x7e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sths,ma,bc r1,0xf(sr1,rp)"
+  -
+    input:
+      bytes: [ 0x0c, 0x41, 0x7a, 0x7e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sths,mb,sl r1,0xf(sr1,rp)"
+  -
+    input:
+      bytes: [ 0x0c, 0x41, 0x52, 0x9e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "stws r1,0xf(sr1,rp)"
+  -
+    input:
+      bytes: [ 0x0c, 0x41, 0x52, 0xbe ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "stws,ma r1,0xf(sr1,rp)"
+  -
+    input:
+      bytes: [ 0x0c, 0x41, 0x72, 0xbe ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "stws,mb r1,0xf(sr1,rp)"
+  -
+    input:
+      bytes: [ 0x0c, 0x41, 0x56, 0xbe ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "stws,ma,bc r1,0xf(sr1,rp)"
+  -
+    input:
+      bytes: [ 0x0c, 0x41, 0x7a, 0xbe ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "stws,mb,sl r1,0xf(sr1,rp)"
+  -
+    input:
+      bytes: [ 0x0c, 0x41, 0x53, 0x1e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "stbys r1,0xf(sr1,rp)"
+  -
+    input:
+      bytes: [ 0x0c, 0x41, 0x53, 0x1e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "stbys r1,0xf(sr1,rp)"
+  -
+    input:
+      bytes: [ 0x0c, 0x41, 0x73, 0x1e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "stbys,e r1,0xf(sr1,rp)"
+  -
+    input:
+      bytes: [ 0x0c, 0x41, 0x53, 0x3e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "stbys,b,m r1,0xf(sr1,rp)"
+  -
+    input:
+      bytes: [ 0x0c, 0x41, 0x73, 0x3e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "stbys,e,m r1,0xf(sr1,rp)"
+  -
+    input:
+      bytes: [ 0x0c, 0x41, 0x57, 0x3e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "stbys,b,m,bc r1,0xf(sr1,rp)"
+  -
+    input:
+      bytes: [ 0x0c, 0x41, 0x7b, 0x3e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "stbys,e,m,sl r1,0xf(sr1,rp)"
+  -
+    input:
+      bytes: [ 0x0c, 0x41, 0x13, 0x9e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "stwas r1,0xf(rp)"
+  -
+    input:
+      bytes: [ 0x0c, 0x41, 0x33, 0xbe ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "stwas,mb r1,0xf(rp)"
+  -
+    input:
+      bytes: [ 0x0c, 0x41, 0x13, 0xbe ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "stwas,ma r1,0xf(rp)"
+  -
+    input:
+      bytes: [ 0x0c, 0x41, 0x37, 0xbe ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "stwas,mb,bc r1,0xf(rp)"
+  -
+    input:
+      bytes: [ 0x0c, 0x41, 0x1b, 0xbe ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "stwas,ma,sl r1,0xf(rp)"
diff --git a/tests/MC/HPPA/longimm20.s.yaml b/tests/MC/HPPA/longimm20.s.yaml
new file mode 100644
index 000000000..b5aea6734
--- /dev/null
+++ b/tests/MC/HPPA/longimm20.s.yaml
@@ -0,0 +1,28 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x34, 0x22, 0x3f, 0xf1 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldo -8(r1),rp"
+  -
+    input:
+      bytes: [ 0x23, 0x98, 0xc5, 0x4f ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldil -0x55810000,ret0"
+  -
+    input:
+      bytes: [ 0x2b, 0x98, 0xc5, 0x4f ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "addil -0x55810000,ret0"
diff --git a/tests/MC/HPPA/mem_mgmt11.s.yaml b/tests/MC/HPPA/mem_mgmt11.s.yaml
new file mode 100644
index 000000000..c635b11bd
--- /dev/null
+++ b/tests/MC/HPPA/mem_mgmt11.s.yaml
@@ -0,0 +1,217 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x04, 0x41, 0x40, 0x40 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "iitlba r1,(sr1,rp)"
+  -
+    input:
+      bytes: [ 0x04, 0x41, 0x40, 0x00 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "iitlbp r1,(sr1,rp)"
+  -
+    input:
+      bytes: [ 0x04, 0x41, 0x42, 0x00 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "pitlb r1(sr1,rp)"
+  -
+    input:
+      bytes: [ 0x04, 0x41, 0x42, 0x40 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "pitlbe r1(sr1,rp)"
+  -
+    input:
+      bytes: [ 0x04, 0x41, 0x42, 0x80 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "fic r1(sr1,rp)"
+  -
+    input:
+      bytes: [ 0x04, 0x41, 0x42, 0xa0 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "fic,m r1(sr1,rp)"
+  -
+    input:
+      bytes: [ 0x04, 0x41, 0x42, 0xc0 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "fice r1(sr1,rp)"
+  -
+    input:
+      bytes: [ 0x04, 0x41, 0x42, 0xe0 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "fice,m r1(sr1,rp)"
+  -
+    input:
+      bytes: [ 0x04, 0x41, 0x50, 0x40 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "idtlba r1,(sr1,rp)"
+  -
+    input:
+      bytes: [ 0x04, 0x41, 0x50, 0x00 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "idtlbp r1,(sr1,rp)"
+  -
+    input:
+      bytes: [ 0x04, 0x41, 0x52, 0x00 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "pdtlb r1(sr1,rp)"
+  -
+    input:
+      bytes: [ 0x04, 0x41, 0x52, 0x40 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "pdtlbe r1(sr1,rp)"
+  -
+    input:
+      bytes: [ 0x04, 0x41, 0x52, 0x80 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdc r1(sr1,rp)"
+  -
+    input:
+      bytes: [ 0x04, 0x41, 0x52, 0xa0 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdc,m r1(sr1,rp)"
+  -
+    input:
+      bytes: [ 0x04, 0x41, 0x52, 0xc0 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdce r1(sr1,rp)"
+  -
+    input:
+      bytes: [ 0x04, 0x41, 0x52, 0xe0 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdce,m r1(sr1,rp)"
+  -
+    input:
+      bytes: [ 0x04, 0x41, 0x53, 0x80 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "pdc r1(sr1,rp)"
+  -
+    input:
+      bytes: [ 0x04, 0x41, 0x53, 0xa0 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "pdc,m r1(sr1,rp)"
+  -
+    input:
+      bytes: [ 0x04, 0x22, 0x51, 0x83 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "prober (sr1,r1),rp,r3"
+  -
+    input:
+      bytes: [ 0x04, 0x30, 0x71, 0x83 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "proberi (sr1,r1),0x10,r3"
+  -
+    input:
+      bytes: [ 0x04, 0x22, 0x51, 0xc3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "probew (sr1,r1),rp,r3"
+  -
+    input:
+      bytes: [ 0x04, 0x30, 0x71, 0xc3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "probewi (sr1,r1),0x10,r3"
+  -
+    input:
+      bytes: [ 0x04, 0x41, 0x53, 0x43 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "lpa r1(sr1,rp),r3"
+  -
+    input:
+      bytes: [ 0x04, 0x41, 0x53, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "lci r1(sr1,rp),r3"
diff --git a/tests/MC/HPPA/memory_reference20.s.yaml b/tests/MC/HPPA/memory_reference20.s.yaml
new file mode 100644
index 000000000..6ace3bdc3
--- /dev/null
+++ b/tests/MC/HPPA/memory_reference20.s.yaml
@@ -0,0 +1,883 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x0c, 0x41, 0x40, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldb r1(sr1,rp),r3"
+  -
+    input:
+      bytes: [ 0x0c, 0x41, 0x60, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldb,s r1(sr1,rp),r3"
+  -
+    input:
+      bytes: [ 0x0c, 0x41, 0x60, 0x23 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldb,sm r1(sr1,rp),r3"
+  -
+    input:
+      bytes: [ 0x0c, 0x41, 0x40, 0x23 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldb,m r1(sr1,rp),r3"
+  -
+    input:
+      bytes: [ 0x0c, 0x51, 0x50, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldb -8(sr1,rp),r3"
+  -
+    input:
+      bytes: [ 0x0c, 0x51, 0x50, 0x23 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldb,ma -8(sr1,rp),r3"
+  -
+    input:
+      bytes: [ 0x0c, 0x51, 0x70, 0x23 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldb,mb -8(sr1,rp),r3"
+  -
+    input:
+      bytes: [ 0x0c, 0x50, 0x58, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldb,sl 8(sr1,rp),r3"
+  -
+    input:
+      bytes: [ 0x0c, 0x41, 0x40, 0x43 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldh r1(sr1,rp),r3"
+  -
+    input:
+      bytes: [ 0x0c, 0x41, 0x60, 0x43 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldh,s r1(sr1,rp),r3"
+  -
+    input:
+      bytes: [ 0x0c, 0x41, 0x60, 0x63 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldh,sm r1(sr1,rp),r3"
+  -
+    input:
+      bytes: [ 0x0c, 0x41, 0x40, 0x63 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldh,m r1(sr1,rp),r3"
+  -
+    input:
+      bytes: [ 0x44, 0x43, 0x41, 0xbc ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldh 0xde(sr1,rp),r3"
+  -
+    input:
+      bytes: [ 0x0c, 0x51, 0x50, 0x63 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldh,ma -8(sr1,rp),r3"
+  -
+    input:
+      bytes: [ 0x0c, 0x51, 0x70, 0x63 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldh,mb -8(sr1,rp),r3"
+  -
+    input:
+      bytes: [ 0x0c, 0x50, 0x58, 0x43 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldh,sl 8(sr1,rp),r3"
+  -
+    input:
+      bytes: [ 0x0c, 0x41, 0x40, 0x83 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldw r1(sr1,rp),r3"
+  -
+    input:
+      bytes: [ 0x0c, 0x41, 0x60, 0x83 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldw,s r1(sr1,rp),r3"
+  -
+    input:
+      bytes: [ 0x0c, 0x41, 0x60, 0xa3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldw,sm r1(sr1,rp),r3"
+  -
+    input:
+      bytes: [ 0x0c, 0x41, 0x40, 0xa3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldw,m r1(sr1,rp),r3"
+  -
+    input:
+      bytes: [ 0x48, 0x43, 0x41, 0xbc ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldw 0xde(sr1,rp),r3"
+  -
+    input:
+      bytes: [ 0x0c, 0x51, 0x50, 0xa3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldw,ma -8(sr1,rp),r3"
+  -
+    input:
+      bytes: [ 0x0c, 0x51, 0x70, 0xa3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldw,mb -8(sr1,rp),r3"
+  -
+    input:
+      bytes: [ 0x0c, 0x50, 0x58, 0x83 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldw,sl 8(sr1,rp),r3"
+  -
+    input:
+      bytes: [ 0x0c, 0x41, 0x40, 0xc3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldd r1(sr1,rp),r3"
+  -
+    input:
+      bytes: [ 0x0c, 0x41, 0x60, 0xc3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldd,s r1(sr1,rp),r3"
+  -
+    input:
+      bytes: [ 0x0c, 0x41, 0x60, 0xe3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldd,sm r1(sr1,rp),r3"
+  -
+    input:
+      bytes: [ 0x0c, 0x41, 0x40, 0xe3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldd,m r1(sr1,rp),r3"
+  -
+    input:
+      bytes: [ 0x0c, 0x51, 0x50, 0xc3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldd -8(sr1,rp),r3"
+  -
+    input:
+      bytes: [ 0x0c, 0x51, 0x50, 0xe3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldd,ma -8(sr1,rp),r3"
+  -
+    input:
+      bytes: [ 0x0c, 0x51, 0x70, 0xe3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldd,mb -8(sr1,rp),r3"
+  -
+    input:
+      bytes: [ 0x0c, 0x50, 0x58, 0xc3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldd,sl 8(sr1,rp),r3"
+  -
+    input:
+      bytes: [ 0x60, 0x21, 0xbf, 0xb1 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "stb r1,-0x28(sr2,r1)"
+  -
+    input:
+      bytes: [ 0x0c, 0x21, 0x92, 0x31 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "stb,ma r1,-8(sr2,r1)"
+  -
+    input:
+      bytes: [ 0x0c, 0x21, 0xb2, 0x31 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "stb,mb r1,-8(sr2,r1)"
+  -
+    input:
+      bytes: [ 0x0c, 0x21, 0x92, 0x20 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "stb,o r1,0(sr2,r1)"
+  -
+    input:
+      bytes: [ 0x64, 0x21, 0xbf, 0xb1 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "sth r1,-0x28(sr2,r1)"
+  -
+    input:
+      bytes: [ 0x0c, 0x21, 0x92, 0x71 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "sth,ma r1,-8(sr2,r1)"
+  -
+    input:
+      bytes: [ 0x0c, 0x21, 0xb2, 0x71 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "sth,mb r1,-8(sr2,r1)"
+  -
+    input:
+      bytes: [ 0x0c, 0x21, 0x92, 0x60 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "sth,o r1,0(sr2,r1)"
+  -
+    input:
+      bytes: [ 0x68, 0x21, 0xbf, 0xb1 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "stw r1,-0x28(sr2,r1)"
+  -
+    input:
+      bytes: [ 0x0c, 0x21, 0x92, 0xb1 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "stw,ma r1,-8(sr2,r1)"
+  -
+    input:
+      bytes: [ 0x0c, 0x21, 0xb2, 0xb1 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "stw,mb r1,-8(sr2,r1)"
+  -
+    input:
+      bytes: [ 0x0c, 0x21, 0x92, 0xa0 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "stw,o r1,0(sr2,r1)"
+  -
+    input:
+      bytes: [ 0x70, 0x21, 0xbf, 0xb1 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "std r1,-0x28(sr2,r1)"
+  -
+    input:
+      bytes: [ 0x0c, 0x21, 0x92, 0xf1 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "std,ma r1,-8(sr2,r1)"
+  -
+    input:
+      bytes: [ 0x0c, 0x21, 0xb2, 0xf1 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "std,mb r1,-8(sr2,r1)"
+  -
+    input:
+      bytes: [ 0x0c, 0x21, 0x92, 0xe0 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "std,o r1,0(sr2,r1)"
+  -
+    input:
+      bytes: [ 0x0c, 0x41, 0x01, 0x83 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldwa r1(rp),r3"
+  -
+    input:
+      bytes: [ 0x0c, 0x41, 0x21, 0x83 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldwa,s r1(rp),r3"
+  -
+    input:
+      bytes: [ 0x0c, 0x41, 0x21, 0xa3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldwa,sm r1(rp),r3"
+  -
+    input:
+      bytes: [ 0x0c, 0x41, 0x01, 0xa3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldwa,m r1(rp),r3"
+  -
+    input:
+      bytes: [ 0x0c, 0x51, 0x11, 0x83 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldwa -8(rp),r3"
+  -
+    input:
+      bytes: [ 0x0c, 0x51, 0x11, 0xa3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldwa,ma -8(rp),r3"
+  -
+    input:
+      bytes: [ 0x0c, 0x51, 0x31, 0xa3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldwa,mb -8(rp),r3"
+  -
+    input:
+      bytes: [ 0x0c, 0x50, 0x19, 0x83 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldwa,sl 8(rp),r3"
+  -
+    input:
+      bytes: [ 0x0c, 0x40, 0x11, 0xa3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldwa,o 0(rp),r3"
+  -
+    input:
+      bytes: [ 0x0c, 0x41, 0x01, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldda r1(rp),r3"
+  -
+    input:
+      bytes: [ 0x0c, 0x41, 0x21, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldda,s r1(rp),r3"
+  -
+    input:
+      bytes: [ 0x0c, 0x41, 0x21, 0x23 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldda,sm r1(rp),r3"
+  -
+    input:
+      bytes: [ 0x0c, 0x41, 0x01, 0x23 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldda,m r1(rp),r3"
+  -
+    input:
+      bytes: [ 0x0c, 0x51, 0x11, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldda -8(rp),r3"
+  -
+    input:
+      bytes: [ 0x0c, 0x51, 0x11, 0x23 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldda,ma -8(rp),r3"
+  -
+    input:
+      bytes: [ 0x0c, 0x51, 0x31, 0x23 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldda,mb -8(rp),r3"
+  -
+    input:
+      bytes: [ 0x0c, 0x50, 0x19, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldda,sl 8(rp),r3"
+  -
+    input:
+      bytes: [ 0x0c, 0x40, 0x11, 0x23 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldda,o 0(rp),r3"
+  -
+    input:
+      bytes: [ 0x0c, 0x21, 0x13, 0x91 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "stwa r1,-8(r1)"
+  -
+    input:
+      bytes: [ 0x0c, 0x21, 0x13, 0xb1 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "stwa,ma r1,-8(r1)"
+  -
+    input:
+      bytes: [ 0x0c, 0x21, 0x33, 0xb1 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "stwa,mb r1,-8(r1)"
+  -
+    input:
+      bytes: [ 0x0c, 0x21, 0x13, 0xa0 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "stwa,o r1,0(r1)"
+  -
+    input:
+      bytes: [ 0x0c, 0x21, 0x13, 0xd1 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "stda r1,-8(r1)"
+  -
+    input:
+      bytes: [ 0x0c, 0x21, 0x13, 0xf1 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "stda,ma r1,-8(r1)"
+  -
+    input:
+      bytes: [ 0x0c, 0x21, 0x33, 0xf1 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "stda,mb r1,-8(r1)"
+  -
+    input:
+      bytes: [ 0x0c, 0x21, 0x13, 0xe0 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "stda,o r1,0(r1)"
+  -
+    input:
+      bytes: [ 0x0c, 0x41, 0x41, 0xc3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldcw r1(sr1,rp),r3"
+  -
+    input:
+      bytes: [ 0x0c, 0x41, 0x61, 0xc3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldcw,s r1(sr1,rp),r3"
+  -
+    input:
+      bytes: [ 0x0c, 0x41, 0x61, 0xe3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldcw,sm r1(sr1,rp),r3"
+  -
+    input:
+      bytes: [ 0x0c, 0x41, 0x41, 0xe3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldcw,m r1(sr1,rp),r3"
+  -
+    input:
+      bytes: [ 0x0c, 0x51, 0x51, 0xc3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldcw -8(sr1,rp),r3"
+  -
+    input:
+      bytes: [ 0x0c, 0x51, 0x51, 0xe3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldcw,ma -8(sr1,rp),r3"
+  -
+    input:
+      bytes: [ 0x0c, 0x51, 0x71, 0xe3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldcw,mb -8(sr1,rp),r3"
+  -
+    input:
+      bytes: [ 0x0c, 0x40, 0x55, 0xc3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldcw,co 0(sr1,rp),r3"
+  -
+    input:
+      bytes: [ 0x0c, 0x41, 0x41, 0x43 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldcd r1(sr1,rp),r3"
+  -
+    input:
+      bytes: [ 0x0c, 0x41, 0x61, 0x43 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldcd,s r1(sr1,rp),r3"
+  -
+    input:
+      bytes: [ 0x0c, 0x41, 0x61, 0x63 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldcd,sm r1(sr1,rp),r3"
+  -
+    input:
+      bytes: [ 0x0c, 0x41, 0x41, 0x63 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldcd,m r1(sr1,rp),r3"
+  -
+    input:
+      bytes: [ 0x0c, 0x51, 0x51, 0x43 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldcd -8(sr1,rp),r3"
+  -
+    input:
+      bytes: [ 0x0c, 0x51, 0x51, 0x63 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldcd,ma -8(sr1,rp),r3"
+  -
+    input:
+      bytes: [ 0x0c, 0x51, 0x71, 0x63 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldcd,mb -8(sr1,rp),r3"
+  -
+    input:
+      bytes: [ 0x0c, 0x40, 0x55, 0x43 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldcd,co 0(sr1,rp),r3"
+  -
+    input:
+      bytes: [ 0x0c, 0x41, 0x53, 0x11 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "stby r1,-8(sr1,rp)"
+  -
+    input:
+      bytes: [ 0x0c, 0x41, 0x53, 0x31 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "stby,b,m r1,-8(sr1,rp)"
+  -
+    input:
+      bytes: [ 0x0c, 0x41, 0x73, 0x11 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "stby,e r1,-8(sr1,rp)"
+  -
+    input:
+      bytes: [ 0x0c, 0x41, 0x73, 0x31 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "stby,e,m r1,-8(sr1,rp)"
+  -
+    input:
+      bytes: [ 0x0c, 0x41, 0x53, 0x51 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "stdby r1,-8(sr1,rp)"
+  -
+    input:
+      bytes: [ 0x0c, 0x41, 0x53, 0x71 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "stdby,b,m r1,-8(sr1,rp)"
+  -
+    input:
+      bytes: [ 0x0c, 0x41, 0x73, 0x51 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "stdby,e r1,-8(sr1,rp)"
+  -
+    input:
+      bytes: [ 0x0c, 0x41, 0x73, 0x71 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "stdby,e,m r1,-8(sr1,rp)"
diff --git a/tests/MC/HPPA/multimedia20.s.yaml b/tests/MC/HPPA/multimedia20.s.yaml
new file mode 100644
index 000000000..41b14e8a0
--- /dev/null
+++ b/tests/MC/HPPA/multimedia20.s.yaml
@@ -0,0 +1,118 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x03, 0xc3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "hadd r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x03, 0x43 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "hadd,ss r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x03, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "hadd,us r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x01, 0xc3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "hsub r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x01, 0x43 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "hsub,ss r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x01, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "hsub,us r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x02, 0xc3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "havg r1,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x07, 0xc3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "hshladd r1,3,rp,r3"
+  -
+    input:
+      bytes: [ 0x08, 0x41, 0x05, 0xc3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "hshradd r1,3,rp,r3"
+  -
+    input:
+      bytes: [ 0xf8, 0x01, 0x88, 0xc2 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "hshl r1,3,rp"
+  -
+    input:
+      bytes: [ 0xf8, 0x20, 0xcc, 0xc2 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "hshr,s r1,3,rp"
+  -
+    input:
+      bytes: [ 0xf8, 0x21, 0x00, 0x02 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "permh,0000 r1,rp"
+  -
+    input:
+      bytes: [ 0xf8, 0x21, 0x06, 0xc2 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "permh,0123 r1,rp"
diff --git a/tests/MC/HPPA/no_grp11.s.yaml b/tests/MC/HPPA/no_grp11.s.yaml
new file mode 100644
index 000000000..8fc7bfe06
--- /dev/null
+++ b/tests/MC/HPPA/no_grp11.s.yaml
@@ -0,0 +1,973 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x14, 0x00, 0x00, 0x01 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "diag 1"
+  -
+    input:
+      bytes: [ 0x18, 0x22, 0x29, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmpyadd,dbl fpe2,fpe4,fpe6,fr4,fr5"
+  -
+    input:
+      bytes: [ 0x20, 0x39, 0x00, 0x00 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldil 0x32000,r1"
+  -
+    input:
+      bytes: [ 0x28, 0x39, 0x00, 0x00 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addil 0x32000,r1"
+  -
+    input:
+      bytes: [ 0x34, 0x22, 0x00, 0x1e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldo 0xf(r1),rp"
+  -
+    input:
+      bytes: [ 0x0c, 0x3e, 0x50, 0x02 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldbs 0xf(sr1,r1),rp"
+  -
+    input:
+      bytes: [ 0x0c, 0x3e, 0x50, 0x42 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldhs 0xf(sr1,r1),rp"
+  -
+    input:
+      bytes: [ 0x0c, 0x3e, 0x50, 0x82 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldws 0xf(sr1,r1),rp"
+  -
+    input:
+      bytes: [ 0x4c, 0x22, 0x40, 0x1e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldwm 0xf(sr1,r1),rp"
+  -
+    input:
+      bytes: [ 0x0c, 0x41, 0x12, 0x1e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "stbs r1,0xf(rp)"
+  -
+    input:
+      bytes: [ 0x0c, 0x41, 0x12, 0x5e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sths r1,0xf(rp)"
+  -
+    input:
+      bytes: [ 0x0c, 0x41, 0x12, 0x9e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "stws r1,0xf(rp)"
+  -
+    input:
+      bytes: [ 0x6c, 0x41, 0x00, 0x1e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "stwm r1,0xf(rp)"
+  -
+    input:
+      bytes: [ 0x80, 0x41, 0x1f, 0x0d ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "combt r1,rp,0xffffffffffffff8c"
+  -
+    input:
+      bytes: [ 0x80, 0x41, 0x3f, 0x05 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "combt,= r1,rp,0xffffffffffffff88"
+  -
+    input:
+      bytes: [ 0x80, 0x41, 0x5e, 0xfd ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "combt,< r1,rp,0xffffffffffffff84"
+  -
+    input:
+      bytes: [ 0x80, 0x41, 0x7e, 0xf5 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "combt,<= r1,rp,0xffffffffffffff80"
+  -
+    input:
+      bytes: [ 0x80, 0x41, 0x9e, 0xed ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "combt,<< r1,rp,0xffffffffffffff7c"
+  -
+    input:
+      bytes: [ 0x80, 0x41, 0xbe, 0xe5 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "combt,<<= r1,rp,0xffffffffffffff78"
+  -
+    input:
+      bytes: [ 0x80, 0x41, 0xde, 0xdd ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "combt,sv r1,rp,0xffffffffffffff74"
+  -
+    input:
+      bytes: [ 0x80, 0x41, 0xfe, 0xd5 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "combt,od r1,rp,0xffffffffffffff70"
+  -
+    input:
+      bytes: [ 0x84, 0x5e, 0x1e, 0xcd ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "comibt 0xf,rp,0xffffffffffffff6c"
+  -
+    input:
+      bytes: [ 0x84, 0x5e, 0x3e, 0xc5 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "comibt,= 0xf,rp,0xffffffffffffff68"
+  -
+    input:
+      bytes: [ 0x84, 0x5e, 0x5e, 0xbd ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "comibt,< 0xf,rp,0xffffffffffffff64"
+  -
+    input:
+      bytes: [ 0x84, 0x5e, 0x7e, 0xb5 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "comibt,<= 0xf,rp,0xffffffffffffff60"
+  -
+    input:
+      bytes: [ 0x84, 0x5e, 0x9e, 0xad ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "comibt,<< 0xf,rp,0xffffffffffffff5c"
+  -
+    input:
+      bytes: [ 0x84, 0x5e, 0xbe, 0xa5 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "comibt,<<= 0xf,rp,0xffffffffffffff58"
+  -
+    input:
+      bytes: [ 0x84, 0x5e, 0xde, 0x9d ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "comibt,sv 0xf,rp,0xffffffffffffff54"
+  -
+    input:
+      bytes: [ 0x84, 0x5e, 0xfe, 0x95 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "comibt,od 0xf,rp,0xffffffffffffff50"
+  -
+    input:
+      bytes: [ 0x88, 0x41, 0x1e, 0x8d ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "combf r1,rp,0xffffffffffffff4c"
+  -
+    input:
+      bytes: [ 0x88, 0x41, 0x3e, 0x85 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "combf,= r1,rp,0xffffffffffffff48"
+  -
+    input:
+      bytes: [ 0x88, 0x41, 0x5e, 0x7d ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "combf,< r1,rp,0xffffffffffffff44"
+  -
+    input:
+      bytes: [ 0x88, 0x41, 0x7e, 0x75 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "combf,<= r1,rp,0xffffffffffffff40"
+  -
+    input:
+      bytes: [ 0x88, 0x41, 0x9e, 0x6d ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "combf,<< r1,rp,0xffffffffffffff3c"
+  -
+    input:
+      bytes: [ 0x88, 0x41, 0xbe, 0x65 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "combf,<<= r1,rp,0xffffffffffffff38"
+  -
+    input:
+      bytes: [ 0x88, 0x41, 0xde, 0x5d ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "combf,sv r1,rp,0xffffffffffffff34"
+  -
+    input:
+      bytes: [ 0x88, 0x41, 0xfe, 0x55 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "combf,od r1,rp,0xffffffffffffff30"
+  -
+    input:
+      bytes: [ 0x8c, 0x5e, 0x1e, 0x4d ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "comibf 0xf,rp,0xffffffffffffff2c"
+  -
+    input:
+      bytes: [ 0x8c, 0x5e, 0x3e, 0x45 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "comibf,= 0xf,rp,0xffffffffffffff28"
+  -
+    input:
+      bytes: [ 0x8c, 0x5e, 0x5e, 0x3d ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "comibf,< 0xf,rp,0xffffffffffffff24"
+  -
+    input:
+      bytes: [ 0x8c, 0x5e, 0x7e, 0x35 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "comibf,<= 0xf,rp,0xffffffffffffff20"
+  -
+    input:
+      bytes: [ 0x8c, 0x5e, 0x9e, 0x2d ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "comibf,<< 0xf,rp,0xffffffffffffff1c"
+  -
+    input:
+      bytes: [ 0x8c, 0x5e, 0xbe, 0x25 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "comibf,<<= 0xf,rp,0xffffffffffffff18"
+  -
+    input:
+      bytes: [ 0x8c, 0x5e, 0xde, 0x1d ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "comibf,sv 0xf,rp,0xffffffffffffff14"
+  -
+    input:
+      bytes: [ 0x8c, 0x5e, 0xfe, 0x15 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "comibf,od 0xf,rp,0xffffffffffffff10"
+  -
+    input:
+      bytes: [ 0x90, 0x41, 0x00, 0x1e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "comiclr 0xf,rp,r1"
+  -
+    input:
+      bytes: [ 0x90, 0x41, 0x20, 0x1e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "comiclr,= 0xf,rp,r1"
+  -
+    input:
+      bytes: [ 0x90, 0x41, 0x40, 0x1e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "comiclr,< 0xf,rp,r1"
+  -
+    input:
+      bytes: [ 0x90, 0x41, 0x60, 0x1e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "comiclr,<= 0xf,rp,r1"
+  -
+    input:
+      bytes: [ 0x90, 0x41, 0x80, 0x1e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "comiclr,<< 0xf,rp,r1"
+  -
+    input:
+      bytes: [ 0x90, 0x41, 0xa0, 0x1e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "comiclr,<<= 0xf,rp,r1"
+  -
+    input:
+      bytes: [ 0x90, 0x41, 0xc0, 0x1e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "comiclr,sv 0xf,rp,r1"
+  -
+    input:
+      bytes: [ 0x90, 0x41, 0xe0, 0x1e ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "comiclr,od 0xf,rp,r1"
+  -
+    input:
+      bytes: [ 0x98, 0x22, 0x29, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmpysub,dbl fpe2,fpe4,fpe6,fr4,fr5"
+  -
+    input:
+      bytes: [ 0xa0, 0x41, 0x1d, 0xc5 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addbt r1,rp,0xfffffffffffffee8"
+  -
+    input:
+      bytes: [ 0xa0, 0x41, 0x3d, 0xbd ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addbt,= r1,rp,0xfffffffffffffee4"
+  -
+    input:
+      bytes: [ 0xa0, 0x41, 0x5d, 0xb5 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addbt,< r1,rp,0xfffffffffffffee0"
+  -
+    input:
+      bytes: [ 0xa0, 0x41, 0x7d, 0xad ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addbt,<= r1,rp,0xfffffffffffffedc"
+  -
+    input:
+      bytes: [ 0xa0, 0x41, 0x9d, 0xa7 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addbt,nuv,n r1,rp,0xfffffffffffffed8"
+  -
+    input:
+      bytes: [ 0xa0, 0x41, 0xbd, 0x9f ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addbt,znv,n r1,rp,0xfffffffffffffed4"
+  -
+    input:
+      bytes: [ 0xa0, 0x41, 0xdd, 0x95 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addbt,sv r1,rp,0xfffffffffffffed0"
+  -
+    input:
+      bytes: [ 0xa0, 0x41, 0xfd, 0x8d ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addbt,od r1,rp,0xfffffffffffffecc"
+  -
+    input:
+      bytes: [ 0xa4, 0x5e, 0x1d, 0x85 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addibt 0xf,rp,0xfffffffffffffec8"
+  -
+    input:
+      bytes: [ 0xa4, 0x5e, 0x3d, 0x7d ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addibt,= 0xf,rp,0xfffffffffffffec4"
+  -
+    input:
+      bytes: [ 0xa4, 0x5e, 0x5d, 0x75 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addibt,< 0xf,rp,0xfffffffffffffec0"
+  -
+    input:
+      bytes: [ 0xa4, 0x5e, 0x7d, 0x6d ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addibt,<= 0xf,rp,0xfffffffffffffebc"
+  -
+    input:
+      bytes: [ 0xa4, 0x5e, 0x9d, 0x67 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addibt,nuv,n 0xf,rp,0xfffffffffffffeb8"
+  -
+    input:
+      bytes: [ 0xa4, 0x5e, 0xbd, 0x5f ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addibt,znv,n 0xf,rp,0xfffffffffffffeb4"
+  -
+    input:
+      bytes: [ 0xa4, 0x5e, 0xdd, 0x55 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addibt,sv 0xf,rp,0xfffffffffffffeb0"
+  -
+    input:
+      bytes: [ 0xa4, 0x5e, 0xfd, 0x4d ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addibt,od 0xf,rp,0xfffffffffffffeac"
+  -
+    input:
+      bytes: [ 0xa8, 0x41, 0x1d, 0x45 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addbf r1,rp,0xfffffffffffffea8"
+  -
+    input:
+      bytes: [ 0xa8, 0x41, 0x3d, 0x3d ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addbf,= r1,rp,0xfffffffffffffea4"
+  -
+    input:
+      bytes: [ 0xa8, 0x41, 0x5d, 0x35 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addbf,< r1,rp,0xfffffffffffffea0"
+  -
+    input:
+      bytes: [ 0xa8, 0x41, 0x7d, 0x2d ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addbf,<= r1,rp,0xfffffffffffffe9c"
+  -
+    input:
+      bytes: [ 0xa8, 0x41, 0x9d, 0x27 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addbf,nuv,n r1,rp,0xfffffffffffffe98"
+  -
+    input:
+      bytes: [ 0xa8, 0x41, 0xbd, 0x1f ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addbf,znv,n r1,rp,0xfffffffffffffe94"
+  -
+    input:
+      bytes: [ 0xa8, 0x41, 0xdd, 0x15 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addbf,sv r1,rp,0xfffffffffffffe90"
+  -
+    input:
+      bytes: [ 0xa8, 0x41, 0xfd, 0x0d ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addbf,od r1,rp,0xfffffffffffffe8c"
+  -
+    input:
+      bytes: [ 0xac, 0x5e, 0x1d, 0x05 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addibf 0xf,rp,0xfffffffffffffe88"
+  -
+    input:
+      bytes: [ 0xac, 0x5e, 0x3c, 0xfd ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addibf,= 0xf,rp,0xfffffffffffffe84"
+  -
+    input:
+      bytes: [ 0xac, 0x5e, 0x5c, 0xf5 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addibf,< 0xf,rp,0xfffffffffffffe80"
+  -
+    input:
+      bytes: [ 0xac, 0x5e, 0x7c, 0xed ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addibf,<= 0xf,rp,0xfffffffffffffe7c"
+  -
+    input:
+      bytes: [ 0xac, 0x5e, 0x9c, 0xe7 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addibf,nuv,n 0xf,rp,0xfffffffffffffe78"
+  -
+    input:
+      bytes: [ 0xac, 0x5e, 0xbc, 0xdf ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addibf,znv,n 0xf,rp,0xfffffffffffffe74"
+  -
+    input:
+      bytes: [ 0xac, 0x5e, 0xdc, 0xd5 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addibf,sv 0xf,rp,0xfffffffffffffe70"
+  -
+    input:
+      bytes: [ 0xac, 0x5e, 0xfc, 0xcd ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "addibf,od 0xf,rp,0xfffffffffffffe6c"
+  -
+    input:
+      bytes: [ 0xc0, 0x01, 0x5c, 0xc7 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "bvb,<,n r1,0xfffffffffffffe68"
+  -
+    input:
+      bytes: [ 0xc0, 0x01, 0xdc, 0xbf ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "bvb,>=,n r1,0xfffffffffffffe64"
+  -
+    input:
+      bytes: [ 0xc4, 0x61, 0x5c, 0xb7 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "bb,<,n r1,3,0xfffffffffffffe60"
+  -
+    input:
+      bytes: [ 0xc4, 0x61, 0xdc, 0xaf ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "bb,>=,n r1,3,0xfffffffffffffe5c"
+  -
+    input:
+      bytes: [ 0xc8, 0x41, 0x1c, 0xa7 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "movb,n r1,rp,0xfffffffffffffe58"
+  -
+    input:
+      bytes: [ 0xc8, 0x41, 0x3c, 0x9d ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "movb,= r1,rp,0xfffffffffffffe54"
+  -
+    input:
+      bytes: [ 0xc8, 0x41, 0x5c, 0x95 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "movb,< r1,rp,0xfffffffffffffe50"
+  -
+    input:
+      bytes: [ 0xc8, 0x41, 0x7c, 0x8d ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "movb,od r1,rp,0xfffffffffffffe4c"
+  -
+    input:
+      bytes: [ 0xc8, 0x41, 0x9c, 0x85 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "movb,tr r1,rp,0xfffffffffffffe48"
+  -
+    input:
+      bytes: [ 0xc8, 0x41, 0xbc, 0x7d ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "movb,<> r1,rp,0xfffffffffffffe44"
+  -
+    input:
+      bytes: [ 0xc8, 0x41, 0xdc, 0x75 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "movb,>= r1,rp,0xfffffffffffffe40"
+  -
+    input:
+      bytes: [ 0xc8, 0x41, 0xfc, 0x6d ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "movb,ev r1,rp,0xfffffffffffffe3c"
+  -
+    input:
+      bytes: [ 0xcc, 0x5e, 0x1c, 0x67 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "movib,n 0xf,rp,0xfffffffffffffe38"
+  -
+    input:
+      bytes: [ 0xcc, 0x5e, 0x3c, 0x5d ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "movib,= 0xf,rp,0xfffffffffffffe34"
+  -
+    input:
+      bytes: [ 0xcc, 0x5e, 0x5c, 0x55 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "movib,< 0xf,rp,0xfffffffffffffe30"
+  -
+    input:
+      bytes: [ 0xcc, 0x5e, 0x7c, 0x4d ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "movib,od 0xf,rp,0xfffffffffffffe2c"
+  -
+    input:
+      bytes: [ 0xcc, 0x5e, 0x9c, 0x45 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "movib,tr 0xf,rp,0xfffffffffffffe28"
+  -
+    input:
+      bytes: [ 0xcc, 0x5e, 0xbc, 0x3d ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "movib,<> 0xf,rp,0xfffffffffffffe24"
+  -
+    input:
+      bytes: [ 0xcc, 0x5e, 0xdc, 0x35 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "movib,>= 0xf,rp,0xfffffffffffffe20"
+  -
+    input:
+      bytes: [ 0xcc, 0x5e, 0xfc, 0x2d ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "movib,ev 0xf,rp,0xfffffffffffffe1c"
+  -
+    input:
+      bytes: [ 0xe0, 0x20, 0x42, 0x02 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "be,n 0x100(sr1,r1)"
+  -
+    input:
+      bytes: [ 0xe4, 0x20, 0x42, 0x02 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "ble,n 0x100(sr1,r1)"
diff --git a/tests/MC/HPPA/sfu11.s.yaml b/tests/MC/HPPA/sfu11.s.yaml
new file mode 100644
index 000000000..568d56e4f
--- /dev/null
+++ b/tests/MC/HPPA/sfu11.s.yaml
@@ -0,0 +1,37 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x10, 0x00, 0x00, 0xa3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "spop0,2,3,n"
+  -
+    input:
+      bytes: [ 0x10, 0x00, 0x1a, 0xa1 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "spop1,2,3,n r1"
+  -
+    input:
+      bytes: [ 0x10, 0x20, 0x04, 0xa3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "spop2,2,3,n r1"
+  -
+    input:
+      bytes: [ 0x10, 0x41, 0x06, 0xa3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "spop3,2,3,n r1,rp"
diff --git a/tests/MC/HPPA/shexdep11.s.yaml b/tests/MC/HPPA/shexdep11.s.yaml
new file mode 100644
index 000000000..66ecf88bc
--- /dev/null
+++ b/tests/MC/HPPA/shexdep11.s.yaml
@@ -0,0 +1,1009 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xd0, 0x41, 0x00, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "vshd r1,rp,r3"
+  -
+    input:
+      bytes: [ 0xd0, 0x41, 0x20, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "vshd,= r1,rp,r3"
+  -
+    input:
+      bytes: [ 0xd0, 0x41, 0x40, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "vshd,< r1,rp,r3"
+  -
+    input:
+      bytes: [ 0xd0, 0x41, 0x60, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "vshd,od r1,rp,r3"
+  -
+    input:
+      bytes: [ 0xd0, 0x41, 0x80, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "vshd,tr r1,rp,r3"
+  -
+    input:
+      bytes: [ 0xd0, 0x41, 0xa0, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "vshd,<> r1,rp,r3"
+  -
+    input:
+      bytes: [ 0xd0, 0x41, 0xc0, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "vshd,>= r1,rp,r3"
+  -
+    input:
+      bytes: [ 0xd0, 0x41, 0xe0, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "vshd,ev r1,rp,r3"
+  -
+    input:
+      bytes: [ 0xd0, 0x41, 0x0a, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "shd r1,rp,0xf,r3"
+  -
+    input:
+      bytes: [ 0xd0, 0x41, 0x2a, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "shd,= r1,rp,0xf,r3"
+  -
+    input:
+      bytes: [ 0xd0, 0x41, 0x4a, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "shd,< r1,rp,0xf,r3"
+  -
+    input:
+      bytes: [ 0xd0, 0x41, 0x6a, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "shd,od r1,rp,0xf,r3"
+  -
+    input:
+      bytes: [ 0xd0, 0x41, 0x8a, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "shd,tr r1,rp,0xf,r3"
+  -
+    input:
+      bytes: [ 0xd0, 0x41, 0xaa, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "shd,<> r1,rp,0xf,r3"
+  -
+    input:
+      bytes: [ 0xd0, 0x41, 0xca, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "shd,>= r1,rp,0xf,r3"
+  -
+    input:
+      bytes: [ 0xd0, 0x41, 0xea, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "shd,ev r1,rp,0xf,r3"
+  -
+    input:
+      bytes: [ 0xd0, 0x23, 0x10, 0x11 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "vextru r1,0xf,r3"
+  -
+    input:
+      bytes: [ 0xd0, 0x23, 0x30, 0x11 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "vextru,= r1,0xf,r3"
+  -
+    input:
+      bytes: [ 0xd0, 0x23, 0x50, 0x11 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "vextru,< r1,0xf,r3"
+  -
+    input:
+      bytes: [ 0xd0, 0x23, 0x70, 0x11 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "vextru,od r1,0xf,r3"
+  -
+    input:
+      bytes: [ 0xd0, 0x23, 0x90, 0x11 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "vextru,tr r1,0xf,r3"
+  -
+    input:
+      bytes: [ 0xd0, 0x23, 0xb0, 0x11 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "vextru,<> r1,0xf,r3"
+  -
+    input:
+      bytes: [ 0xd0, 0x23, 0xd0, 0x11 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "vextru,>= r1,0xf,r3"
+  -
+    input:
+      bytes: [ 0xd0, 0x23, 0xf0, 0x11 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "vextru,ev r1,0xf,r3"
+  -
+    input:
+      bytes: [ 0xd0, 0x23, 0x14, 0x11 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "vextrs r1,0xf,r3"
+  -
+    input:
+      bytes: [ 0xd0, 0x23, 0x34, 0x11 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "vextrs,= r1,0xf,r3"
+  -
+    input:
+      bytes: [ 0xd0, 0x23, 0x54, 0x11 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "vextrs,< r1,0xf,r3"
+  -
+    input:
+      bytes: [ 0xd0, 0x23, 0x74, 0x11 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "vextrs,od r1,0xf,r3"
+  -
+    input:
+      bytes: [ 0xd0, 0x23, 0x94, 0x11 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "vextrs,tr r1,0xf,r3"
+  -
+    input:
+      bytes: [ 0xd0, 0x23, 0xb4, 0x11 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "vextrs,<> r1,0xf,r3"
+  -
+    input:
+      bytes: [ 0xd0, 0x23, 0xd4, 0x11 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "vextrs,>= r1,0xf,r3"
+  -
+    input:
+      bytes: [ 0xd0, 0x23, 0xf4, 0x11 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "vextrs,ev r1,0xf,r3"
+  -
+    input:
+      bytes: [ 0xd0, 0x23, 0x19, 0xd1 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "extru r1,0xe,0xf,r3"
+  -
+    input:
+      bytes: [ 0xd0, 0x23, 0x39, 0xd1 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "extru,= r1,0xe,0xf,r3"
+  -
+    input:
+      bytes: [ 0xd0, 0x23, 0x59, 0xd1 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "extru,< r1,0xe,0xf,r3"
+  -
+    input:
+      bytes: [ 0xd0, 0x23, 0x79, 0xd1 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "extru,od r1,0xe,0xf,r3"
+  -
+    input:
+      bytes: [ 0xd0, 0x23, 0x99, 0xd1 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "extru,tr r1,0xe,0xf,r3"
+  -
+    input:
+      bytes: [ 0xd0, 0x23, 0xb9, 0xd1 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "extru,<> r1,0xe,0xf,r3"
+  -
+    input:
+      bytes: [ 0xd0, 0x23, 0xd9, 0xd1 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "extru,>= r1,0xe,0xf,r3"
+  -
+    input:
+      bytes: [ 0xd0, 0x23, 0xf9, 0xd1 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "extru,ev r1,0xe,0xf,r3"
+  -
+    input:
+      bytes: [ 0xd0, 0x23, 0x1d, 0xd1 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "extrs r1,0xe,0xf,r3"
+  -
+    input:
+      bytes: [ 0xd0, 0x23, 0x3d, 0xd1 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "extrs,= r1,0xe,0xf,r3"
+  -
+    input:
+      bytes: [ 0xd0, 0x23, 0x5d, 0xd1 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "extrs,< r1,0xe,0xf,r3"
+  -
+    input:
+      bytes: [ 0xd0, 0x23, 0x7d, 0xd1 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "extrs,od r1,0xe,0xf,r3"
+  -
+    input:
+      bytes: [ 0xd0, 0x23, 0x9d, 0xd1 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "extrs,tr r1,0xe,0xf,r3"
+  -
+    input:
+      bytes: [ 0xd0, 0x23, 0xbd, 0xd1 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "extrs,<> r1,0xe,0xf,r3"
+  -
+    input:
+      bytes: [ 0xd0, 0x23, 0xdd, 0xd1 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "extrs,>= r1,0xe,0xf,r3"
+  -
+    input:
+      bytes: [ 0xd0, 0x23, 0xfd, 0xd1 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "extrs,ev r1,0xe,0xf,r3"
+  -
+    input:
+      bytes: [ 0xd4, 0x61, 0x00, 0x11 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "zvdep r1,0xf,r3"
+  -
+    input:
+      bytes: [ 0xd4, 0x61, 0x20, 0x11 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "zvdep,= r1,0xf,r3"
+  -
+    input:
+      bytes: [ 0xd4, 0x61, 0x40, 0x11 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "zvdep,< r1,0xf,r3"
+  -
+    input:
+      bytes: [ 0xd4, 0x61, 0x60, 0x11 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "zvdep,od r1,0xf,r3"
+  -
+    input:
+      bytes: [ 0xd4, 0x61, 0x80, 0x11 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "zvdep,tr r1,0xf,r3"
+  -
+    input:
+      bytes: [ 0xd4, 0x61, 0xa0, 0x11 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "zvdep,<> r1,0xf,r3"
+  -
+    input:
+      bytes: [ 0xd4, 0x61, 0xc0, 0x11 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "zvdep,>= r1,0xf,r3"
+  -
+    input:
+      bytes: [ 0xd4, 0x61, 0xe0, 0x11 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "zvdep,ev r1,0xf,r3"
+  -
+    input:
+      bytes: [ 0xd4, 0x61, 0x04, 0x11 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "vdep r1,0xf,r3"
+  -
+    input:
+      bytes: [ 0xd4, 0x61, 0x24, 0x11 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "vdep,= r1,0xf,r3"
+  -
+    input:
+      bytes: [ 0xd4, 0x61, 0x44, 0x11 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "vdep,< r1,0xf,r3"
+  -
+    input:
+      bytes: [ 0xd4, 0x61, 0x64, 0x11 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "vdep,od r1,0xf,r3"
+  -
+    input:
+      bytes: [ 0xd4, 0x61, 0x84, 0x11 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "vdep,tr r1,0xf,r3"
+  -
+    input:
+      bytes: [ 0xd4, 0x61, 0xa4, 0x11 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "vdep,<> r1,0xf,r3"
+  -
+    input:
+      bytes: [ 0xd4, 0x61, 0xc4, 0x11 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "vdep,>= r1,0xf,r3"
+  -
+    input:
+      bytes: [ 0xd4, 0x61, 0xe4, 0x11 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "vdep,ev r1,0xf,r3"
+  -
+    input:
+      bytes: [ 0xd4, 0x61, 0x0a, 0x31 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "zdep r1,0xe,0xf,r3"
+  -
+    input:
+      bytes: [ 0xd4, 0x61, 0x2a, 0x31 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "zdep,= r1,0xe,0xf,r3"
+  -
+    input:
+      bytes: [ 0xd4, 0x61, 0x4a, 0x31 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "zdep,< r1,0xe,0xf,r3"
+  -
+    input:
+      bytes: [ 0xd4, 0x61, 0x6a, 0x31 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "zdep,od r1,0xe,0xf,r3"
+  -
+    input:
+      bytes: [ 0xd4, 0x61, 0x8a, 0x31 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "zdep,tr r1,0xe,0xf,r3"
+  -
+    input:
+      bytes: [ 0xd4, 0x61, 0xaa, 0x31 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "zdep,<> r1,0xe,0xf,r3"
+  -
+    input:
+      bytes: [ 0xd4, 0x61, 0xca, 0x31 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "zdep,>= r1,0xe,0xf,r3"
+  -
+    input:
+      bytes: [ 0xd4, 0x61, 0xea, 0x31 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "zdep,ev r1,0xe,0xf,r3"
+  -
+    input:
+      bytes: [ 0xd4, 0x61, 0x0e, 0x31 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "dep r1,0xe,0xf,r3"
+  -
+    input:
+      bytes: [ 0xd4, 0x61, 0x2e, 0x31 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "dep,= r1,0xe,0xf,r3"
+  -
+    input:
+      bytes: [ 0xd4, 0x61, 0x4e, 0x31 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "dep,< r1,0xe,0xf,r3"
+  -
+    input:
+      bytes: [ 0xd4, 0x61, 0x6e, 0x31 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "dep,od r1,0xe,0xf,r3"
+  -
+    input:
+      bytes: [ 0xd4, 0x61, 0x8e, 0x31 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "dep,tr r1,0xe,0xf,r3"
+  -
+    input:
+      bytes: [ 0xd4, 0x61, 0xae, 0x31 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "dep,<> r1,0xe,0xf,r3"
+  -
+    input:
+      bytes: [ 0xd4, 0x61, 0xce, 0x31 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "dep,>= r1,0xe,0xf,r3"
+  -
+    input:
+      bytes: [ 0xd4, 0x61, 0xee, 0x31 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "dep,ev r1,0xe,0xf,r3"
+  -
+    input:
+      bytes: [ 0xd4, 0x7c, 0x10, 0x11 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "zvdepi 0xe,0xf,r3"
+  -
+    input:
+      bytes: [ 0xd4, 0x7c, 0x30, 0x11 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "zvdepi,= 0xe,0xf,r3"
+  -
+    input:
+      bytes: [ 0xd4, 0x7c, 0x50, 0x11 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "zvdepi,< 0xe,0xf,r3"
+  -
+    input:
+      bytes: [ 0xd4, 0x7c, 0x70, 0x11 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "zvdepi,od 0xe,0xf,r3"
+  -
+    input:
+      bytes: [ 0xd4, 0x7c, 0x90, 0x11 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "zvdepi,tr 0xe,0xf,r3"
+  -
+    input:
+      bytes: [ 0xd4, 0x7c, 0xb0, 0x11 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "zvdepi,<> 0xe,0xf,r3"
+  -
+    input:
+      bytes: [ 0xd4, 0x7c, 0xd0, 0x11 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "zvdepi,>= 0xe,0xf,r3"
+  -
+    input:
+      bytes: [ 0xd4, 0x7c, 0xf0, 0x11 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "zvdepi,ev 0xe,0xf,r3"
+  -
+    input:
+      bytes: [ 0xd4, 0x7c, 0x14, 0x11 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "vdepi 0xe,0xf,r3"
+  -
+    input:
+      bytes: [ 0xd4, 0x7c, 0x34, 0x11 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "vdepi,= 0xe,0xf,r3"
+  -
+    input:
+      bytes: [ 0xd4, 0x7c, 0x54, 0x11 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "vdepi,< 0xe,0xf,r3"
+  -
+    input:
+      bytes: [ 0xd4, 0x7c, 0x74, 0x11 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "vdepi,od 0xe,0xf,r3"
+  -
+    input:
+      bytes: [ 0xd4, 0x7c, 0x94, 0x11 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "vdepi,tr 0xe,0xf,r3"
+  -
+    input:
+      bytes: [ 0xd4, 0x7c, 0xb4, 0x11 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "vdepi,<> 0xe,0xf,r3"
+  -
+    input:
+      bytes: [ 0xd4, 0x7c, 0xd4, 0x11 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "vdepi,>= 0xe,0xf,r3"
+  -
+    input:
+      bytes: [ 0xd4, 0x7c, 0xf4, 0x11 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "vdepi,ev 0xe,0xf,r3"
+  -
+    input:
+      bytes: [ 0xd4, 0x66, 0x1b, 0xbf ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "zdepi 3,2,1,r3"
+  -
+    input:
+      bytes: [ 0xd4, 0x66, 0x3b, 0xbf ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "zdepi,= 3,2,1,r3"
+  -
+    input:
+      bytes: [ 0xd4, 0x66, 0x5b, 0xbf ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "zdepi,< 3,2,1,r3"
+  -
+    input:
+      bytes: [ 0xd4, 0x66, 0x7b, 0xbf ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "zdepi,od 3,2,1,r3"
+  -
+    input:
+      bytes: [ 0xd4, 0x66, 0x9b, 0xbf ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "zdepi,tr 3,2,1,r3"
+  -
+    input:
+      bytes: [ 0xd4, 0x66, 0xbb, 0xbf ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "zdepi,<> 3,2,1,r3"
+  -
+    input:
+      bytes: [ 0xd4, 0x66, 0xdb, 0xbf ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "zdepi,>= 3,2,1,r3"
+  -
+    input:
+      bytes: [ 0xd4, 0x66, 0xfb, 0xbf ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "zdepi,ev 3,2,1,r3"
+  -
+    input:
+      bytes: [ 0xd4, 0x66, 0x1f, 0xbf ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "depi 3,2,1,r3"
+  -
+    input:
+      bytes: [ 0xd4, 0x66, 0x3f, 0xbf ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "depi,= 3,2,1,r3"
+  -
+    input:
+      bytes: [ 0xd4, 0x66, 0x5f, 0xbf ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "depi,< 3,2,1,r3"
+  -
+    input:
+      bytes: [ 0xd4, 0x66, 0x7f, 0xbf ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "depi,od 3,2,1,r3"
+  -
+    input:
+      bytes: [ 0xd4, 0x66, 0x9f, 0xbf ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "depi,tr 3,2,1,r3"
+  -
+    input:
+      bytes: [ 0xd4, 0x66, 0xbf, 0xbf ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "depi,<> 3,2,1,r3"
+  -
+    input:
+      bytes: [ 0xd4, 0x66, 0xdf, 0xbf ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "depi,>= 3,2,1,r3"
+  -
+    input:
+      bytes: [ 0xd4, 0x66, 0xff, 0xbf ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "depi,ev 3,2,1,r3"
diff --git a/tests/MC/HPPA/sysctrl20.s.yaml b/tests/MC/HPPA/sysctrl20.s.yaml
new file mode 100644
index 000000000..e8405d407
--- /dev/null
+++ b/tests/MC/HPPA/sysctrl20.s.yaml
@@ -0,0 +1,433 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x50, 0xa2 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldsid (sr1,r1),rp"
+  -
+    input:
+      bytes: [ 0x00, 0x01, 0x58, 0x20 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "mtsp r1,sr1"
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x44, 0xa1 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "mfsp sr1,r1"
+  -
+    input:
+      bytes: [ 0x00, 0x41, 0x18, 0x40 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "mtctl r1,cr2"
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x08, 0xa2 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "mfctl cr1,rp"
+  -
+    input:
+      bytes: [ 0x01, 0x60, 0x48, 0xa1 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "mfctl,w sar,r1"
+  -
+    input:
+      bytes: [ 0x01, 0x61, 0x18, 0xc0 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "mtsarcm r1"
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x14, 0xa1 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "mfia r1"
+  -
+    input:
+      bytes: [ 0x00, 0x0f, 0x0d, 0x61 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "ssm 0xf,r1"
+  -
+    input:
+      bytes: [ 0x00, 0x0f, 0x0e, 0x61 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "rsm 0xf,r1"
+  -
+    input:
+      bytes: [ 0x00, 0x01, 0x18, 0x60 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "mtsm r1"
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x0c, 0x00 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "rfi"
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x0c, 0xa0 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "rfi,r"
+  -
+    input:
+      bytes: [ 0x03, 0xff, 0xc0, 0x1f ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "break 0x1f,0x1ffe"
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x04, 0x00 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "sync"
+  -
+    input:
+      bytes: [ 0x00, 0x10, 0x04, 0x00 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "syncdma"
+  -
+    input:
+      bytes: [ 0x04, 0x22, 0x51, 0x83 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "probe,r (sr1,r1),rp,r3"
+  -
+    input:
+      bytes: [ 0x04, 0x22, 0x51, 0xc3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "probe,w (sr1,r1),rp,r3"
+  -
+    input:
+      bytes: [ 0x04, 0x22, 0x51, 0x83 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "probe,r (sr1,r1),rp,r3"
+  -
+    input:
+      bytes: [ 0x04, 0x2f, 0x71, 0x83 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "probei,r (sr1,r1),0xf,r3"
+  -
+    input:
+      bytes: [ 0x04, 0x2f, 0x71, 0xc3 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "probei,w (sr1,r1),0xf,r3"
+  -
+    input:
+      bytes: [ 0x04, 0x2f, 0x71, 0x83 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "probei,r (sr1,r1),0xf,r3"
+  -
+    input:
+      bytes: [ 0x04, 0x41, 0x53, 0x43 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "lpa r1(sr1,rp),r3"
+  -
+    input:
+      bytes: [ 0x04, 0x41, 0x53, 0x63 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "lpa,m r1(sr1,rp),r3"
+  -
+    input:
+      bytes: [ 0x04, 0x41, 0x53, 0x03 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "lci r1(sr1,rp),r3"
+  -
+    input:
+      bytes: [ 0x04, 0x41, 0x12, 0x00 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "pdtlb r1(rp)"
+  -
+    input:
+      bytes: [ 0x04, 0x41, 0x16, 0x00 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "pdtlb,l r1(rp)"
+  -
+    input:
+      bytes: [ 0x04, 0x41, 0x16, 0x20 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "pdtlb,l,m r1(rp)"
+  -
+    input:
+      bytes: [ 0x04, 0x41, 0x42, 0x00 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "pitlb r1(sr1,rp)"
+  -
+    input:
+      bytes: [ 0x04, 0x41, 0x46, 0x00 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "pitlb,l r1(sr1,rp)"
+  -
+    input:
+      bytes: [ 0x04, 0x41, 0x46, 0x20 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "pitlb,l,m r1(sr1,rp)"
+  -
+    input:
+      bytes: [ 0x04, 0x41, 0x12, 0x40 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "pdtlbe r1(rp)"
+  -
+    input:
+      bytes: [ 0x04, 0x41, 0x12, 0x60 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "pdtlbe,m r1(rp)"
+  -
+    input:
+      bytes: [ 0x04, 0x41, 0x42, 0x40 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "pitlbe r1(sr1,rp)"
+  -
+    input:
+      bytes: [ 0x04, 0x41, 0x42, 0x60 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "pitlbe,m r1(sr1,rp)"
+  -
+    input:
+      bytes: [ 0x04, 0x41, 0x18, 0x00 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "idtlbt r1,rp"
+  -
+    input:
+      bytes: [ 0x04, 0x41, 0x08, 0x00 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "iitlbt r1,rp"
+  -
+    input:
+      bytes: [ 0x04, 0x41, 0x13, 0x80 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "pdc r1(rp)"
+  -
+    input:
+      bytes: [ 0x04, 0x41, 0x13, 0xa0 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "pdc,m r1(rp)"
+  -
+    input:
+      bytes: [ 0x04, 0x41, 0x52, 0x80 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdc r1(sr1,rp)"
+  -
+    input:
+      bytes: [ 0x04, 0x41, 0x52, 0xa0 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdc,m r1(sr1,rp)"
+  -
+    input:
+      bytes: [ 0x04, 0x5e, 0x72, 0x80 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdc 0xf(sr1,rp)"
+  -
+    input:
+      bytes: [ 0x04, 0x41, 0x42, 0x80 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "fic r1(sr1,rp)"
+  -
+    input:
+      bytes: [ 0x04, 0x41, 0x52, 0xc0 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdce r1(sr1,rp)"
+  -
+    input:
+      bytes: [ 0x04, 0x41, 0x52, 0xe0 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdce,m r1(sr1,rp)"
+  -
+    input:
+      bytes: [ 0x04, 0x41, 0x42, 0xc0 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "fice r1(sr1,rp)"
+  -
+    input:
+      bytes: [ 0x04, 0x41, 0x42, 0xe0 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "fice,m r1(sr1,rp)"
+  -
+    input:
+      bytes: [ 0x14, 0x00, 0xde, 0xad ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_20" ]
+    expected:
+      insns:
+        -
+          asm_text: "diag 0xdead"
diff --git a/tests/MC/HPPA/system_op11.s.yaml b/tests/MC/HPPA/system_op11.s.yaml
new file mode 100644
index 000000000..745a5e664
--- /dev/null
+++ b/tests/MC/HPPA/system_op11.s.yaml
@@ -0,0 +1,118 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x20, 0x01 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "break 1,1"
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x04, 0x00 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "sync"
+  -
+    input:
+      bytes: [ 0x00, 0x10, 0x04, 0x00 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "syncdma"
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x0c, 0x00 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "rfi"
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x0c, 0xa0 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "rfir"
+  -
+    input:
+      bytes: [ 0x00, 0x1e, 0x0d, 0x61 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "ssm 0x1e,r1"
+  -
+    input:
+      bytes: [ 0x00, 0x1e, 0x0e, 0x61 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "rsm 0x1e,r1"
+  -
+    input:
+      bytes: [ 0x00, 0x01, 0x18, 0x60 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "mtsm r1"
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x50, 0xa2 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldsid (sr1,r1),rp"
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x58, 0x20 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "mtsp flags,sr1"
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x44, 0xa0 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "mfsp sr1,flags"
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x18, 0x40 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "mtctl flags,rctr"
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x18, 0x40 ]
+      arch: "CS_ARCH_HPPA"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_HPPA_11" ]
+    expected:
+      insns:
+        -
+          asm_text: "mtctl flags,rctr"
diff --git a/tests/MC/LoongArch/absd.s.yaml b/tests/MC/LoongArch/absd.s.yaml
new file mode 100644
index 000000000..9de4e1d11
--- /dev/null
+++ b/tests/MC/LoongArch/absd.s.yaml
@@ -0,0 +1,73 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x36, 0x44, 0x60, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvabsd.b $xr22, $xr1, $xr17"
+  -
+    input:
+      bytes: [ 0x11, 0xa7, 0x60, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvabsd.h $xr17, $xr24, $xr9"
+  -
+    input:
+      bytes: [ 0x3c, 0x75, 0x61, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvabsd.w $xr28, $xr9, $xr29"
+  -
+    input:
+      bytes: [ 0xfe, 0xce, 0x61, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvabsd.d $xr30, $xr23, $xr19"
+  -
+    input:
+      bytes: [ 0x90, 0x3c, 0x62, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvabsd.bu $xr16, $xr4, $xr15"
+  -
+    input:
+      bytes: [ 0xed, 0xee, 0x62, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvabsd.hu $xr13, $xr23, $xr27"
+  -
+    input:
+      bytes: [ 0x5f, 0x3e, 0x63, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvabsd.wu $xr31, $xr18, $xr15"
+  -
+    input:
+      bytes: [ 0x5a, 0x91, 0x63, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvabsd.du $xr26, $xr10, $xr4"
diff --git a/tests/MC/LoongArch/add.s.yaml b/tests/MC/LoongArch/add.s.yaml
new file mode 100644
index 000000000..a41531746
--- /dev/null
+++ b/tests/MC/LoongArch/add.s.yaml
@@ -0,0 +1,46 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x74, 0x16, 0x0a, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvadd.b $xr20, $xr19, $xr5"
+  -
+    input:
+      bytes: [ 0xf8, 0xb8, 0x0a, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvadd.h $xr24, $xr7, $xr14"
+  -
+    input:
+      bytes: [ 0x33, 0x54, 0x0b, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvadd.w $xr19, $xr1, $xr21"
+  -
+    input:
+      bytes: [ 0xd3, 0xb4, 0x0b, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvadd.d $xr19, $xr6, $xr13"
+  -
+    input:
+      bytes: [ 0x84, 0x1b, 0x2d, 0x75 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvadd.q $xr4, $xr28, $xr6"
diff --git a/tests/MC/LoongArch/adda.s.yaml b/tests/MC/LoongArch/adda.s.yaml
new file mode 100644
index 000000000..1aba39cab
--- /dev/null
+++ b/tests/MC/LoongArch/adda.s.yaml
@@ -0,0 +1,37 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x0a, 0x6f, 0x5c, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvadda.b $xr10, $xr24, $xr27"
+  -
+    input:
+      bytes: [ 0x80, 0xf7, 0x5c, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvadda.h $xr0, $xr28, $xr29"
+  -
+    input:
+      bytes: [ 0x3f, 0x25, 0x5d, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvadda.w $xr31, $xr9, $xr9"
+  -
+    input:
+      bytes: [ 0x2a, 0xe4, 0x5d, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvadda.d $xr10, $xr1, $xr25"
diff --git a/tests/MC/LoongArch/addi.s.yaml b/tests/MC/LoongArch/addi.s.yaml
new file mode 100644
index 000000000..2492161c4
--- /dev/null
+++ b/tests/MC/LoongArch/addi.s.yaml
@@ -0,0 +1,37 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xc1, 0x0a, 0x8a, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvaddi.bu $xr1, $xr22, 2"
+  -
+    input:
+      bytes: [ 0x43, 0xf5, 0x8a, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvaddi.hu $xr3, $xr10, 0x1d"
+  -
+    input:
+      bytes: [ 0x65, 0x0d, 0x8b, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvaddi.wu $xr5, $xr11, 3"
+  -
+    input:
+      bytes: [ 0x06, 0x9c, 0x8b, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvaddi.du $xr6, $xr0, 7"
diff --git a/tests/MC/LoongArch/addw.s.yaml b/tests/MC/LoongArch/addw.s.yaml
new file mode 100644
index 000000000..bb7e0286a
--- /dev/null
+++ b/tests/MC/LoongArch/addw.s.yaml
@@ -0,0 +1,217 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xd7, 0x13, 0x1e, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvaddwev.h.b $xr23, $xr30, $xr4"
+  -
+    input:
+      bytes: [ 0x74, 0xfe, 0x1e, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvaddwev.w.h $xr20, $xr19, $xr31"
+  -
+    input:
+      bytes: [ 0x28, 0x65, 0x1f, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvaddwev.d.w $xr8, $xr9, $xr25"
+  -
+    input:
+      bytes: [ 0xdd, 0xf6, 0x1f, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvaddwev.q.d $xr29, $xr22, $xr29"
+  -
+    input:
+      bytes: [ 0xbe, 0x69, 0x2e, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvaddwev.h.bu $xr30, $xr13, $xr26"
+  -
+    input:
+      bytes: [ 0xef, 0xc3, 0x2e, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvaddwev.w.hu $xr15, $xr31, $xr16"
+  -
+    input:
+      bytes: [ 0x10, 0x52, 0x2f, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvaddwev.d.wu $xr16, $xr16, $xr20"
+  -
+    input:
+      bytes: [ 0x4a, 0xca, 0x2f, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvaddwev.q.du $xr10, $xr18, $xr18"
+  -
+    input:
+      bytes: [ 0xe3, 0x24, 0x3e, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvaddwev.h.bu.b $xr3, $xr7, $xr9"
+  -
+    input:
+      bytes: [ 0x1a, 0xee, 0x3e, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvaddwev.w.hu.h $xr26, $xr16, $xr27"
+  -
+    input:
+      bytes: [ 0xa0, 0x21, 0x3f, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvaddwev.d.wu.w $xr0, $xr13, $xr8"
+  -
+    input:
+      bytes: [ 0x53, 0x8d, 0x3f, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvaddwev.q.du.d $xr19, $xr10, $xr3"
+  -
+    input:
+      bytes: [ 0xae, 0x62, 0x22, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvaddwod.h.b $xr14, $xr21, $xr24"
+  -
+    input:
+      bytes: [ 0x53, 0xdf, 0x22, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvaddwod.w.h $xr19, $xr26, $xr23"
+  -
+    input:
+      bytes: [ 0x2c, 0x51, 0x23, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvaddwod.d.w $xr12, $xr9, $xr20"
+  -
+    input:
+      bytes: [ 0x4b, 0xa0, 0x23, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvaddwod.q.d $xr11, $xr2, $xr8"
+  -
+    input:
+      bytes: [ 0xc6, 0x24, 0x32, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvaddwod.h.bu $xr6, $xr6, $xr9"
+  -
+    input:
+      bytes: [ 0x61, 0xe7, 0x32, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvaddwod.w.hu $xr1, $xr27, $xr25"
+  -
+    input:
+      bytes: [ 0x7a, 0x2e, 0x33, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvaddwod.d.wu $xr26, $xr19, $xr11"
+  -
+    input:
+      bytes: [ 0xd5, 0xa2, 0x33, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvaddwod.q.du $xr21, $xr22, $xr8"
+  -
+    input:
+      bytes: [ 0x55, 0x63, 0x40, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvaddwod.h.bu.b $xr21, $xr26, $xr24"
+  -
+    input:
+      bytes: [ 0xdf, 0xc0, 0x40, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvaddwod.w.hu.h $xr31, $xr6, $xr16"
+  -
+    input:
+      bytes: [ 0x8c, 0x7f, 0x41, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvaddwod.d.wu.w $xr12, $xr28, $xr31"
+  -
+    input:
+      bytes: [ 0x9d, 0xb0, 0x41, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvaddwod.q.du.d $xr29, $xr4, $xr12"
diff --git a/tests/MC/LoongArch/and.s.yaml b/tests/MC/LoongArch/and.s.yaml
new file mode 100644
index 000000000..4cc12c527
--- /dev/null
+++ b/tests/MC/LoongArch/and.s.yaml
@@ -0,0 +1,10 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xee, 0x4e, 0x26, 0x75 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvand.v $xr14, $xr23, $xr19"
diff --git a/tests/MC/LoongArch/andi.s.yaml b/tests/MC/LoongArch/andi.s.yaml
new file mode 100644
index 000000000..923b57778
--- /dev/null
+++ b/tests/MC/LoongArch/andi.s.yaml
@@ -0,0 +1,10 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xeb, 0x08, 0xd1, 0x77 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvandi.b $xr11, $xr7, 0x42"
diff --git a/tests/MC/LoongArch/andn.s.yaml b/tests/MC/LoongArch/andn.s.yaml
new file mode 100644
index 000000000..79ca97e3f
--- /dev/null
+++ b/tests/MC/LoongArch/andn.s.yaml
@@ -0,0 +1,10 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xe3, 0x0d, 0x28, 0x75 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvandn.v $xr3, $xr15, $xr3"
diff --git a/tests/MC/LoongArch/arith.s.yaml b/tests/MC/LoongArch/arith.s.yaml
new file mode 100644
index 000000000..f970b44e5
--- /dev/null
+++ b/tests/MC/LoongArch/arith.s.yaml
@@ -0,0 +1,262 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x29, 0x7c, 0x10, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add.w $a5, $ra, $s8"
+  -
+    input:
+      bytes: [ 0x35, 0x4f, 0x11, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub.w $r21, $s2, $t7"
+  -
+    input:
+      bytes: [ 0xe5, 0xd8, 0x83, 0x02 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "addi.w $a1, $a3, 0xf6"
+  -
+    input:
+      bytes: [ 0x22, 0x8a, 0x05, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "alsl.w $tp, $t5, $tp, 4"
+  -
+    input:
+      bytes: [ 0x30, 0x06, 0x00, 0x14 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "lu12i.w $t4, 0x31"
+  -
+    input:
+      bytes: [ 0xe4, 0xff, 0xff, 0x15 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "lu12i.w $a0, -1"
+  -
+    input:
+      bytes: [ 0x5d, 0x0b, 0x12, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "slt $s6, $s3, $tp"
+  -
+    input:
+      bytes: [ 0xab, 0xf6, 0x12, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sltu $a7, $r21, $s6"
+  -
+    input:
+      bytes: [ 0x3b, 0xac, 0x03, 0x02 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "slti $s4, $ra, 0xeb"
+  -
+    input:
+      bytes: [ 0x00, 0x89, 0x42, 0x02 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sltui $zero, $a4, 0xa2"
+  -
+    input:
+      bytes: [ 0x69, 0x17, 0x00, 0x18 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "pcaddi $a5, 0xbb"
+  -
+    input:
+      bytes: [ 0xa0, 0x04, 0x00, 0x1c ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "pcaddu12i $zero, 0x25"
+  -
+    input:
+      bytes: [ 0x2a, 0x0b, 0x00, 0x1a ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "pcalau12i $a6, 0x59"
+  -
+    input:
+      bytes: [ 0xf3, 0x87, 0x14, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "and $t7, $s8, $ra"
+  -
+    input:
+      bytes: [ 0x11, 0x7a, 0x15, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "or $t5, $t4, $s7"
+  -
+    input:
+      bytes: [ 0x45, 0x16, 0x14, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "nor $a1, $t6, $a1"
+  -
+    input:
+      bytes: [ 0x6f, 0xa2, 0x15, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor $t3, $t7, $a4"
+  -
+    input:
+      bytes: [ 0x3c, 0x97, 0x16, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "andn $s5, $s2, $a1"
+  -
+    input:
+      bytes: [ 0x62, 0x64, 0x16, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "orn $tp, $sp, $s2"
+  -
+    input:
+      bytes: [ 0x19, 0xa8, 0x41, 0x03 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "andi $s2, $zero, 0x6a"
+  -
+    input:
+      bytes: [ 0xb1, 0xbc, 0x80, 0x03 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "ori $t5, $a1, 0x2f"
+  -
+    input:
+      bytes: [ 0xf2, 0x8e, 0xc1, 0x03 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xori $t6, $s0, 0x63"
+  -
+    input:
+      bytes: [ 0x44, 0x0e, 0x1c, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.w $a0, $t6, $sp"
+  -
+    input:
+      bytes: [ 0xfb, 0x82, 0x1c, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulh.w $s4, $s0, $zero"
+  -
+    input:
+      bytes: [ 0x2a, 0x62, 0x1d, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulh.wu $a6, $t5, $s1"
+  -
+    input:
+      bytes: [ 0xbe, 0x65, 0x20, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "div.w $s7, $t1, $s2"
+  -
+    input:
+      bytes: [ 0x41, 0xab, 0x20, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "mod.w $ra, $s3, $a6"
+  -
+    input:
+      bytes: [ 0xf3, 0x02, 0x21, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "div.wu $t7, $s0, $zero"
+  -
+    input:
+      bytes: [ 0x3b, 0xc5, 0x21, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "mod.wu $s4, $a5, $t5"
diff --git a/tests/MC/LoongArch/arm-alu.s.yaml b/tests/MC/LoongArch/arm-alu.s.yaml
new file mode 100644
index 000000000..94a8e2d28
--- /dev/null
+++ b/tests/MC/LoongArch/arm-alu.s.yaml
@@ -0,0 +1,73 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x91, 0x14, 0x37, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "armadd.w $a0, $a1, 1"
+  -
+    input:
+      bytes: [ 0x91, 0x94, 0x37, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "armsub.w $a0, $a1, 1"
+  -
+    input:
+      bytes: [ 0x91, 0x14, 0x38, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "armadc.w $a0, $a1, 1"
+  -
+    input:
+      bytes: [ 0x91, 0x94, 0x38, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "armsbc.w $a0, $a1, 1"
+  -
+    input:
+      bytes: [ 0x91, 0x14, 0x39, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "armand.w $a0, $a1, 1"
+  -
+    input:
+      bytes: [ 0x91, 0x94, 0x39, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "armor.w $a0, $a1, 1"
+  -
+    input:
+      bytes: [ 0x91, 0x14, 0x3a, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "armxor.w $a0, $a1, 1"
+  -
+    input:
+      bytes: [ 0x9c, 0xc4, 0x3f, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "armnot.w $a0, 1"
diff --git a/tests/MC/LoongArch/arm-jump.s.yaml b/tests/MC/LoongArch/arm-jump.s.yaml
new file mode 100644
index 000000000..d10ca4daf
--- /dev/null
+++ b/tests/MC/LoongArch/arm-jump.s.yaml
@@ -0,0 +1,10 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x04, 0xc4, 0x36, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "setarmj $a0, 1"
diff --git a/tests/MC/LoongArch/arm-mov.s.yaml b/tests/MC/LoongArch/arm-mov.s.yaml
new file mode 100644
index 000000000..5ba08cb23
--- /dev/null
+++ b/tests/MC/LoongArch/arm-mov.s.yaml
@@ -0,0 +1,46 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xa4, 0x44, 0x36, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "armmove $a0, $a1, 1"
+  -
+    input:
+      bytes: [ 0x9d, 0xc4, 0x3f, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "armmov.w $a0, 1"
+  -
+    input:
+      bytes: [ 0x9e, 0xc4, 0x3f, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "armmov.d $a0, 1"
+  -
+    input:
+      bytes: [ 0x44, 0x04, 0x5c, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "armmfflag $a0, 1"
+  -
+    input:
+      bytes: [ 0x64, 0x04, 0x5c, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "armmtflag $a0, 1"
diff --git a/tests/MC/LoongArch/arm-shift.s.yaml b/tests/MC/LoongArch/arm-shift.s.yaml
new file mode 100644
index 000000000..35f4e232c
--- /dev/null
+++ b/tests/MC/LoongArch/arm-shift.s.yaml
@@ -0,0 +1,82 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x91, 0x94, 0x3a, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "armsll.w $a0, $a1, 1"
+  -
+    input:
+      bytes: [ 0x91, 0x14, 0x3b, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "armsrl.w $a0, $a1, 1"
+  -
+    input:
+      bytes: [ 0x91, 0x94, 0x3b, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "armsra.w $a0, $a1, 1"
+  -
+    input:
+      bytes: [ 0x91, 0x14, 0x3c, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "armrotr.w $a0, $a1, 1"
+  -
+    input:
+      bytes: [ 0x91, 0x84, 0x3c, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "armslli.w $a0, 1, 1"
+  -
+    input:
+      bytes: [ 0x91, 0x04, 0x3d, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "armsrli.w $a0, 1, 1"
+  -
+    input:
+      bytes: [ 0x91, 0x84, 0x3d, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "armsrai.w $a0, 1, 1"
+  -
+    input:
+      bytes: [ 0x91, 0x04, 0x3e, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "armrotri.w $a0, 1, 1"
+  -
+    input:
+      bytes: [ 0x9f, 0xc4, 0x3f, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "armrrx.w $a0, 1"
diff --git a/tests/MC/LoongArch/atomic.s.yaml b/tests/MC/LoongArch/atomic.s.yaml
new file mode 100644
index 000000000..31dfcdc5b
--- /dev/null
+++ b/tests/MC/LoongArch/atomic.s.yaml
@@ -0,0 +1,37 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x62, 0xdf, 0x00, 0x20 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "ll.w $tp, $s4, 0xdc"
+  -
+    input:
+      bytes: [ 0xd3, 0x39, 0x00, 0x21 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sc.w $t7, $t2, 0x38"
+  -
+    input:
+      bytes: [ 0xcd, 0x81, 0x57, 0x38 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "llacq.w $t1, $t2"
+  -
+    input:
+      bytes: [ 0xcd, 0x85, 0x57, 0x38 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "screl.w $t1, $t2"
diff --git a/tests/MC/LoongArch/avg.s.yaml b/tests/MC/LoongArch/avg.s.yaml
new file mode 100644
index 000000000..5c1ec770f
--- /dev/null
+++ b/tests/MC/LoongArch/avg.s.yaml
@@ -0,0 +1,73 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xc5, 0x57, 0x64, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvavg.b $xr5, $xr30, $xr21"
+  -
+    input:
+      bytes: [ 0x32, 0xd6, 0x64, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvavg.h $xr18, $xr17, $xr21"
+  -
+    input:
+      bytes: [ 0xe3, 0x52, 0x65, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvavg.w $xr3, $xr23, $xr20"
+  -
+    input:
+      bytes: [ 0x1b, 0xec, 0x65, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvavg.d $xr27, $xr0, $xr27"
+  -
+    input:
+      bytes: [ 0x8b, 0x40, 0x66, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvavg.bu $xr11, $xr4, $xr16"
+  -
+    input:
+      bytes: [ 0x22, 0xcc, 0x66, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvavg.hu $xr2, $xr1, $xr19"
+  -
+    input:
+      bytes: [ 0x9b, 0x6e, 0x67, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvavg.wu $xr27, $xr20, $xr27"
+  -
+    input:
+      bytes: [ 0x97, 0xf6, 0x67, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvavg.du $xr23, $xr20, $xr29"
diff --git a/tests/MC/LoongArch/avgr.s.yaml b/tests/MC/LoongArch/avgr.s.yaml
new file mode 100644
index 000000000..49b30f14a
--- /dev/null
+++ b/tests/MC/LoongArch/avgr.s.yaml
@@ -0,0 +1,73 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xfd, 0x1d, 0x68, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvavgr.b $xr29, $xr15, $xr7"
+  -
+    input:
+      bytes: [ 0x40, 0xbf, 0x68, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvavgr.h $xr0, $xr26, $xr15"
+  -
+    input:
+      bytes: [ 0x17, 0x00, 0x69, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvavgr.w $xr23, $xr0, $xr0"
+  -
+    input:
+      bytes: [ 0xfd, 0x82, 0x69, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvavgr.d $xr29, $xr23, $xr0"
+  -
+    input:
+      bytes: [ 0x56, 0x64, 0x6a, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvavgr.bu $xr22, $xr2, $xr25"
+  -
+    input:
+      bytes: [ 0x59, 0xd5, 0x6a, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvavgr.hu $xr25, $xr10, $xr21"
+  -
+    input:
+      bytes: [ 0xd1, 0x0d, 0x6b, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvavgr.wu $xr17, $xr14, $xr3"
+  -
+    input:
+      bytes: [ 0x62, 0xb5, 0x6b, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvavgr.du $xr2, $xr11, $xr13"
diff --git a/tests/MC/LoongArch/barrier.s.yaml b/tests/MC/LoongArch/barrier.s.yaml
new file mode 100644
index 000000000..3c57629f2
--- /dev/null
+++ b/tests/MC/LoongArch/barrier.s.yaml
@@ -0,0 +1,19 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x72, 0x38 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "dbar 0"
+  -
+    input:
+      bytes: [ 0x00, 0x80, 0x72, 0x38 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "ibar 0"
diff --git a/tests/MC/LoongArch/base.s.yaml b/tests/MC/LoongArch/base.s.yaml
new file mode 100644
index 000000000..7e59d559b
--- /dev/null
+++ b/tests/MC/LoongArch/base.s.yaml
@@ -0,0 +1,298 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xa4, 0x04, 0x29, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "addu12i.w $a0, $a1, 1"
+  -
+    input:
+      bytes: [ 0xa4, 0x84, 0x29, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "addu12i.d $a0, $a1, 1"
+  -
+    input:
+      bytes: [ 0xa4, 0x18, 0x30, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "adc.b $a0, $a1, $a2"
+  -
+    input:
+      bytes: [ 0xa4, 0x98, 0x30, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "adc.h $a0, $a1, $a2"
+  -
+    input:
+      bytes: [ 0xa4, 0x18, 0x31, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "adc.w $a0, $a1, $a2"
+  -
+    input:
+      bytes: [ 0xa4, 0x98, 0x31, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "adc.d $a0, $a1, $a2"
+  -
+    input:
+      bytes: [ 0xa4, 0x18, 0x32, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sbc.b $a0, $a1, $a2"
+  -
+    input:
+      bytes: [ 0xa4, 0x98, 0x32, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sbc.h $a0, $a1, $a2"
+  -
+    input:
+      bytes: [ 0xa4, 0x18, 0x33, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sbc.w $a0, $a1, $a2"
+  -
+    input:
+      bytes: [ 0xa4, 0x98, 0x33, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sbc.d $a0, $a1, $a2"
+  -
+    input:
+      bytes: [ 0xa4, 0x18, 0x1a, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rotr.b $a0, $a1, $a2"
+  -
+    input:
+      bytes: [ 0xa4, 0x98, 0x1a, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rotr.h $a0, $a1, $a2"
+  -
+    input:
+      bytes: [ 0xa4, 0x24, 0x4c, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rotri.b $a0, $a1, 1"
+  -
+    input:
+      bytes: [ 0xa4, 0x44, 0x4c, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rotri.h $a0, $a1, 1"
+  -
+    input:
+      bytes: [ 0xa4, 0x18, 0x34, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rcr.b $a0, $a1, $a2"
+  -
+    input:
+      bytes: [ 0xa4, 0x98, 0x34, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rcr.h $a0, $a1, $a2"
+  -
+    input:
+      bytes: [ 0xa4, 0x18, 0x35, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rcr.w $a0, $a1, $a2"
+  -
+    input:
+      bytes: [ 0xa4, 0x98, 0x35, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rcr.d $a0, $a1, $a2"
+  -
+    input:
+      bytes: [ 0xa4, 0x24, 0x50, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rcri.b $a0, $a1, 1"
+  -
+    input:
+      bytes: [ 0xa4, 0x44, 0x50, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rcri.h $a0, $a1, 1"
+  -
+    input:
+      bytes: [ 0xa4, 0x84, 0x50, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rcri.w $a0, $a1, 1"
+  -
+    input:
+      bytes: [ 0xa4, 0x04, 0x51, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rcri.d $a0, $a1, 1"
+  -
+    input:
+      bytes: [ 0x20, 0xe4, 0x14, 0x01 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvt.ud.d $fa0, $fa1"
+  -
+    input:
+      bytes: [ 0x20, 0xe0, 0x14, 0x01 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvt.ld.d $fa0, $fa1"
+  -
+    input:
+      bytes: [ 0x20, 0x08, 0x15, 0x01 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvt.d.ld $fa0, $fa1, $fa2"
+  -
+    input:
+      bytes: [ 0xa4, 0x04, 0x80, 0x2e ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldl.d $a0, $a1, 1"
+  -
+    input:
+      bytes: [ 0xa4, 0x04, 0x00, 0x2e ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldl.w $a0, $a1, 1"
+  -
+    input:
+      bytes: [ 0xa4, 0x04, 0x40, 0x2e ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr.w $a0, $a1, 1"
+  -
+    input:
+      bytes: [ 0xa4, 0x04, 0xc0, 0x2e ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr.d $a0, $a1, 1"
+  -
+    input:
+      bytes: [ 0xa4, 0x04, 0x00, 0x2f ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "stl.w $a0, $a1, 1"
+  -
+    input:
+      bytes: [ 0xa4, 0x04, 0x80, 0x2f ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "stl.d $a0, $a1, 1"
+  -
+    input:
+      bytes: [ 0xa4, 0x04, 0x40, 0x2f ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "str.w $a0, $a1, 1"
+  -
+    input:
+      bytes: [ 0xa4, 0x04, 0xc0, 0x2f ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "str.d $a0, $a1, 1"
diff --git a/tests/MC/LoongArch/bit-manipu.s.yaml b/tests/MC/LoongArch/bit-manipu.s.yaml
new file mode 100644
index 000000000..f71335e0a
--- /dev/null
+++ b/tests/MC/LoongArch/bit-manipu.s.yaml
@@ -0,0 +1,109 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x61, 0x10, 0x00, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "clo.w $ra, $sp"
+  -
+    input:
+      bytes: [ 0x47, 0x15, 0x00, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "clz.w $a3, $a6"
+  -
+    input:
+      bytes: [ 0xc2, 0x18, 0x00, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "cto.w $tp, $a2"
+  -
+    input:
+      bytes: [ 0xc5, 0x1e, 0x00, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "ctz.w $a1, $fp"
+  -
+    input:
+      bytes: [ 0x1d, 0x40, 0x08, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "bytepick.w $s6, $zero, $t4, 0"
+  -
+    input:
+      bytes: [ 0x74, 0x31, 0x00, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "revb.2h $t8, $a7"
+  -
+    input:
+      bytes: [ 0x75, 0x4b, 0x00, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "bitrev.4b $r21, $s4"
+  -
+    input:
+      bytes: [ 0xb9, 0x50, 0x00, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "bitrev.w $s2, $a1"
+  -
+    input:
+      bytes: [ 0x68, 0x09, 0x67, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "bstrins.w $a4, $a7, 7, 2"
+  -
+    input:
+      bytes: [ 0x21, 0x91, 0x6a, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "bstrpick.w $ra, $a5, 0xa, 4"
+  -
+    input:
+      bytes: [ 0x74, 0x49, 0x13, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "maskeqz $t8, $a7, $t6"
+  -
+    input:
+      bytes: [ 0xb4, 0xe9, 0x13, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "masknez $t8, $t1, $s3"
diff --git a/tests/MC/LoongArch/bit-shift.s.yaml b/tests/MC/LoongArch/bit-shift.s.yaml
new file mode 100644
index 000000000..bef713646
--- /dev/null
+++ b/tests/MC/LoongArch/bit-shift.s.yaml
@@ -0,0 +1,73 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x78, 0x5f, 0x17, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sll.w $s1, $s4, $s0"
+  -
+    input:
+      bytes: [ 0x3f, 0x9e, 0x17, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "srl.w $s8, $t5, $a3"
+  -
+    input:
+      bytes: [ 0x8c, 0x2b, 0x18, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sra.w $t0, $s5, $a6"
+  -
+    input:
+      bytes: [ 0x41, 0x4b, 0x1b, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rotr.w $ra, $s3, $t6"
+  -
+    input:
+      bytes: [ 0x5a, 0x82, 0x40, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "slli.w $s3, $t6, 0"
+  -
+    input:
+      bytes: [ 0xca, 0xf9, 0x44, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "srli.w $a6, $t2, 0x1e"
+  -
+    input:
+      bytes: [ 0x28, 0xe2, 0x48, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "srai.w $a4, $t5, 0x18"
+  -
+    input:
+      bytes: [ 0x97, 0xde, 0x4c, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rotri.w $s0, $t8, 0x17"
diff --git a/tests/MC/LoongArch/bitclr.s.yaml b/tests/MC/LoongArch/bitclr.s.yaml
new file mode 100644
index 000000000..bcec28850
--- /dev/null
+++ b/tests/MC/LoongArch/bitclr.s.yaml
@@ -0,0 +1,73 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xb8, 0x38, 0x0c, 0x75 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvbitclr.b $xr24, $xr5, $xr14"
+  -
+    input:
+      bytes: [ 0x3e, 0xb5, 0x0c, 0x75 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvbitclr.h $xr30, $xr9, $xr13"
+  -
+    input:
+      bytes: [ 0x62, 0x1c, 0x0d, 0x75 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvbitclr.w $xr2, $xr3, $xr7"
+  -
+    input:
+      bytes: [ 0xae, 0xe4, 0x0d, 0x75 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvbitclr.d $xr14, $xr5, $xr25"
+  -
+    input:
+      bytes: [ 0x56, 0x3f, 0x10, 0x77 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvbitclri.b $xr22, $xr26, 7"
+  -
+    input:
+      bytes: [ 0xc2, 0x75, 0x10, 0x77 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvbitclri.h $xr2, $xr14, 0xd"
+  -
+    input:
+      bytes: [ 0x43, 0x80, 0x10, 0x77 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvbitclri.w $xr3, $xr2, 0"
+  -
+    input:
+      bytes: [ 0x8a, 0x1d, 0x11, 0x77 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvbitclri.d $xr10, $xr12, 7"
diff --git a/tests/MC/LoongArch/bitrev.s.yaml b/tests/MC/LoongArch/bitrev.s.yaml
new file mode 100644
index 000000000..649419716
--- /dev/null
+++ b/tests/MC/LoongArch/bitrev.s.yaml
@@ -0,0 +1,73 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x90, 0x0e, 0x10, 0x75 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvbitrev.b $xr16, $xr20, $xr3"
+  -
+    input:
+      bytes: [ 0x70, 0xd0, 0x10, 0x75 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvbitrev.h $xr16, $xr3, $xr20"
+  -
+    input:
+      bytes: [ 0x58, 0x5f, 0x11, 0x75 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvbitrev.w $xr24, $xr26, $xr23"
+  -
+    input:
+      bytes: [ 0x2d, 0xec, 0x11, 0x75 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvbitrev.d $xr13, $xr1, $xr27"
+  -
+    input:
+      bytes: [ 0x67, 0x35, 0x18, 0x77 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvbitrevi.b $xr7, $xr11, 5"
+  -
+    input:
+      bytes: [ 0xa1, 0x7c, 0x18, 0x77 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvbitrevi.h $xr1, $xr5, 0xf"
+  -
+    input:
+      bytes: [ 0xad, 0xca, 0x18, 0x77 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvbitrevi.w $xr13, $xr21, 0x12"
+  -
+    input:
+      bytes: [ 0x61, 0x24, 0x19, 0x77 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvbitrevi.d $xr1, $xr3, 0x9"
diff --git a/tests/MC/LoongArch/bitsel.s.yaml b/tests/MC/LoongArch/bitsel.s.yaml
new file mode 100644
index 000000000..dfb2e4c7b
--- /dev/null
+++ b/tests/MC/LoongArch/bitsel.s.yaml
@@ -0,0 +1,10 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xb2, 0xbf, 0x2a, 0x0d ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvbitsel.v $xr18, $xr29, $xr15, $xr21"
diff --git a/tests/MC/LoongArch/bitseli.s.yaml b/tests/MC/LoongArch/bitseli.s.yaml
new file mode 100644
index 000000000..08e790f41
--- /dev/null
+++ b/tests/MC/LoongArch/bitseli.s.yaml
@@ -0,0 +1,10 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xad, 0xe6, 0xc5, 0x77 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvbitseli.b $xr13, $xr21, 0x79"
diff --git a/tests/MC/LoongArch/bitset.s.yaml b/tests/MC/LoongArch/bitset.s.yaml
new file mode 100644
index 000000000..335f99bfe
--- /dev/null
+++ b/tests/MC/LoongArch/bitset.s.yaml
@@ -0,0 +1,73 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x06, 0x72, 0x0e, 0x75 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvbitset.b $xr6, $xr16, $xr28"
+  -
+    input:
+      bytes: [ 0xa5, 0xfd, 0x0e, 0x75 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvbitset.h $xr5, $xr13, $xr31"
+  -
+    input:
+      bytes: [ 0x87, 0x23, 0x0f, 0x75 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvbitset.w $xr7, $xr28, $xr8"
+  -
+    input:
+      bytes: [ 0x04, 0xb2, 0x0f, 0x75 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvbitset.d $xr4, $xr16, $xr12"
+  -
+    input:
+      bytes: [ 0x7a, 0x20, 0x14, 0x77 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvbitseti.b $xr26, $xr3, 0"
+  -
+    input:
+      bytes: [ 0x69, 0x66, 0x14, 0x77 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvbitseti.h $xr9, $xr19, 0x9"
+  -
+    input:
+      bytes: [ 0x6c, 0x8a, 0x14, 0x77 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvbitseti.w $xr12, $xr19, 2"
+  -
+    input:
+      bytes: [ 0xf4, 0x08, 0x15, 0x77 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvbitseti.d $xr20, $xr7, 2"
diff --git a/tests/MC/LoongArch/bound-check.s.yaml b/tests/MC/LoongArch/bound-check.s.yaml
new file mode 100644
index 000000000..b39054319
--- /dev/null
+++ b/tests/MC/LoongArch/bound-check.s.yaml
@@ -0,0 +1,145 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xc6, 0x74, 0x78, 0x38 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldgt.b $a2, $a2, $s6"
+  -
+    input:
+      bytes: [ 0xe5, 0x87, 0x78, 0x38 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldgt.h $a1, $s8, $ra"
+  -
+    input:
+      bytes: [ 0x4f, 0x23, 0x79, 0x38 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldgt.w $t3, $s3, $a4"
+  -
+    input:
+      bytes: [ 0x37, 0xff, 0x79, 0x38 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldgt.d $s0, $s2, $s8"
+  -
+    input:
+      bytes: [ 0x89, 0x3d, 0x7a, 0x38 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldle.b $a5, $t0, $t3"
+  -
+    input:
+      bytes: [ 0x6b, 0xdd, 0x7a, 0x38 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldle.h $a7, $a7, $s0"
+  -
+    input:
+      bytes: [ 0x58, 0x08, 0x7b, 0x38 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldle.w $s1, $tp, $tp"
+  -
+    input:
+      bytes: [ 0xf4, 0xc1, 0x7b, 0x38 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldle.d $t8, $t3, $t4"
+  -
+    input:
+      bytes: [ 0x7b, 0x52, 0x7c, 0x38 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "stgt.b $s4, $t7, $t8"
+  -
+    input:
+      bytes: [ 0x90, 0x98, 0x7c, 0x38 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "stgt.h $t4, $a0, $a2"
+  -
+    input:
+      bytes: [ 0x9f, 0x3b, 0x7d, 0x38 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "stgt.w $s8, $s5, $t2"
+  -
+    input:
+      bytes: [ 0xbe, 0xe2, 0x7d, 0x38 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "stgt.d $s7, $r21, $s1"
+  -
+    input:
+      bytes: [ 0x8a, 0x40, 0x7e, 0x38 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "stle.b $a6, $a0, $t4"
+  -
+    input:
+      bytes: [ 0x31, 0xd6, 0x7e, 0x38 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "stle.h $t5, $t5, $r21"
+  -
+    input:
+      bytes: [ 0x97, 0x77, 0x7f, 0x38 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "stle.w $s0, $s5, $s6"
+  -
+    input:
+      bytes: [ 0x19, 0xf7, 0x7f, 0x38 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "stle.d $s2, $s1, $s6"
diff --git a/tests/MC/LoongArch/branch.s.yaml b/tests/MC/LoongArch/branch.s.yaml
new file mode 100644
index 000000000..a02577418
--- /dev/null
+++ b/tests/MC/LoongArch/branch.s.yaml
@@ -0,0 +1,100 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x47, 0xb1, 0x00, 0x58 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "beq $a6, $a3, 0xb0"
+  -
+    input:
+      bytes: [ 0x21, 0x8b, 0x00, 0x5c ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "bne $s2, $ra, 0x88"
+  -
+    input:
+      bytes: [ 0xfe, 0xa9, 0x00, 0x60 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "blt $t3, $s7, 0xa8"
+  -
+    input:
+      bytes: [ 0x8f, 0x95, 0x00, 0x64 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "bge $t0, $t3, 0x94"
+  -
+    input:
+      bytes: [ 0x25, 0x06, 0x00, 0x68 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "bltu $t5, $a1, 4"
+  -
+    input:
+      bytes: [ 0xd7, 0x8c, 0x00, 0x6c ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "bgeu $a2, $s0, 0x8c"
+  -
+    input:
+      bytes: [ 0x20, 0x61, 0x00, 0x40 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "beqz $a5, 0x60"
+  -
+    input:
+      bytes: [ 0x60, 0xd4, 0x00, 0x44 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "bnez $sp, 0xd4"
+  -
+    input:
+      bytes: [ 0x00, 0xf8, 0x00, 0x50 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "b 0xf8"
+  -
+    input:
+      bytes: [ 0x00, 0xec, 0x00, 0x54 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "bl 0xec"
+  -
+    input:
+      bytes: [ 0x81, 0x04, 0x00, 0x4c ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "jirl $ra, $a0, 4"
diff --git a/tests/MC/LoongArch/bsll.s.yaml b/tests/MC/LoongArch/bsll.s.yaml
new file mode 100644
index 000000000..6396b2a3b
--- /dev/null
+++ b/tests/MC/LoongArch/bsll.s.yaml
@@ -0,0 +1,10 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xae, 0x52, 0x8e, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvbsll.v $xr14, $xr21, 0x14"
diff --git a/tests/MC/LoongArch/bsrl.s.yaml b/tests/MC/LoongArch/bsrl.s.yaml
new file mode 100644
index 000000000..2d909d5a3
--- /dev/null
+++ b/tests/MC/LoongArch/bsrl.s.yaml
@@ -0,0 +1,10 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xa4, 0xf4, 0x8e, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvbsrl.v $xr4, $xr5, 0x1d"
diff --git a/tests/MC/LoongArch/clo.s.yaml b/tests/MC/LoongArch/clo.s.yaml
new file mode 100644
index 000000000..647ad20fb
--- /dev/null
+++ b/tests/MC/LoongArch/clo.s.yaml
@@ -0,0 +1,37 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x89, 0x01, 0x9c, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvclo.b $xr9, $xr12"
+  -
+    input:
+      bytes: [ 0xd0, 0x05, 0x9c, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvclo.h $xr16, $xr14"
+  -
+    input:
+      bytes: [ 0x5e, 0x0a, 0x9c, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvclo.w $xr30, $xr18"
+  -
+    input:
+      bytes: [ 0xbf, 0x0c, 0x9c, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvclo.d $xr31, $xr5"
diff --git a/tests/MC/LoongArch/clz.s.yaml b/tests/MC/LoongArch/clz.s.yaml
new file mode 100644
index 000000000..20d216da8
--- /dev/null
+++ b/tests/MC/LoongArch/clz.s.yaml
@@ -0,0 +1,37 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xc5, 0x10, 0x9c, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvclz.b $xr5, $xr6"
+  -
+    input:
+      bytes: [ 0xe4, 0x14, 0x9c, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvclz.h $xr4, $xr7"
+  -
+    input:
+      bytes: [ 0x0c, 0x18, 0x9c, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvclz.w $xr12, $xr0"
+  -
+    input:
+      bytes: [ 0x01, 0x1c, 0x9c, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvclz.d $xr1, $xr0"
diff --git a/tests/MC/LoongArch/crc.s.yaml b/tests/MC/LoongArch/crc.s.yaml
new file mode 100644
index 000000000..328928f37
--- /dev/null
+++ b/tests/MC/LoongArch/crc.s.yaml
@@ -0,0 +1,73 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xf8, 0x08, 0x24, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "crc.w.b.w $s1, $a3, $tp"
+  -
+    input:
+      bytes: [ 0x5f, 0xc9, 0x24, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "crc.w.h.w $s8, $a6, $t6"
+  -
+    input:
+      bytes: [ 0xdc, 0x28, 0x25, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "crc.w.w.w $s5, $a2, $a6"
+  -
+    input:
+      bytes: [ 0x7c, 0xfd, 0x25, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "crc.w.d.w $s5, $a7, $s8"
+  -
+    input:
+      bytes: [ 0x4f, 0x0e, 0x26, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "crcc.w.b.w $t3, $t6, $sp"
+  -
+    input:
+      bytes: [ 0xb5, 0xcb, 0x26, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "crcc.w.h.w $r21, $s6, $t6"
+  -
+    input:
+      bytes: [ 0xd1, 0x35, 0x27, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "crcc.w.w.w $t5, $t2, $t1"
+  -
+    input:
+      bytes: [ 0xbe, 0xee, 0x27, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "crcc.w.d.w $s7, $r21, $s4"
diff --git a/tests/MC/LoongArch/d-arith.s.yaml b/tests/MC/LoongArch/d-arith.s.yaml
new file mode 100644
index 000000000..16471ded9
--- /dev/null
+++ b/tests/MC/LoongArch/d-arith.s.yaml
@@ -0,0 +1,217 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xfd, 0xe5, 0x00, 0x01 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd.s $fs5, $ft7, $fs1"
+  -
+    input:
+      bytes: [ 0xf9, 0x34, 0x01, 0x01 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd.d $fs1, $fa7, $ft5"
+  -
+    input:
+      bytes: [ 0x3d, 0x48, 0x03, 0x01 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub.d $fs5, $fa1, $ft10"
+  -
+    input:
+      bytes: [ 0xc4, 0x1f, 0x05, 0x01 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmul.d $fa4, $fs6, $fa7"
+  -
+    input:
+      bytes: [ 0x23, 0x73, 0x07, 0x01 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdiv.d $fa3, $fs1, $fs4"
+  -
+    input:
+      bytes: [ 0x15, 0x73, 0x2c, 0x08 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmadd.d $ft13, $fs0, $fs4, $fs0"
+  -
+    input:
+      bytes: [ 0x46, 0xd2, 0x6d, 0x08 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmsub.d $fa6, $ft10, $ft12, $fs3"
+  -
+    input:
+      bytes: [ 0xb9, 0x4d, 0xaf, 0x08 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fnmadd.d $fs1, $ft5, $ft11, $fs6"
+  -
+    input:
+      bytes: [ 0x5e, 0x1f, 0xec, 0x08 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fnmsub.d $fs6, $fs2, $fa7, $fs0"
+  -
+    input:
+      bytes: [ 0x4b, 0x37, 0x09, 0x01 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmax.d $ft3, $fs2, $ft5"
+  -
+    input:
+      bytes: [ 0xa1, 0x6d, 0x0b, 0x01 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmin.d $fa1, $ft5, $fs3"
+  -
+    input:
+      bytes: [ 0xb8, 0x11, 0x0d, 0x01 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxa.d $fs0, $ft5, $fa4"
+  -
+    input:
+      bytes: [ 0x52, 0x01, 0x0f, 0x01 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmina.d $ft10, $ft2, $fa0"
+  -
+    input:
+      bytes: [ 0x77, 0x08, 0x14, 0x01 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fabs.d $ft15, $fa3"
+  -
+    input:
+      bytes: [ 0x4b, 0x1b, 0x14, 0x01 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fneg.d $ft3, $fs2"
+  -
+    input:
+      bytes: [ 0x62, 0x49, 0x14, 0x01 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsqrt.d $fa2, $ft3"
+  -
+    input:
+      bytes: [ 0x7b, 0x5b, 0x14, 0x01 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "frecip.d $fs3, $fs3"
+  -
+    input:
+      bytes: [ 0x00, 0x78, 0x14, 0x01 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "frecipe.d $fa0, $fa0"
+  -
+    input:
+      bytes: [ 0x76, 0x68, 0x14, 0x01 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "frsqrt.d $ft14, $fa3"
+  -
+    input:
+      bytes: [ 0x21, 0x88, 0x14, 0x01 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "frsqrte.d $fa1, $fa1"
+  -
+    input:
+      bytes: [ 0xcc, 0x69, 0x11, 0x01 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fscaleb.d $ft4, $ft6, $fs2"
+  -
+    input:
+      bytes: [ 0xb5, 0x2b, 0x14, 0x01 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "flogb.d $ft13, $fs5"
+  -
+    input:
+      bytes: [ 0x50, 0x1b, 0x13, 0x01 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcopysign.d $ft8, $fs2, $fa6"
+  -
+    input:
+      bytes: [ 0x53, 0x38, 0x14, 0x01 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fclass.d $ft11, $fa2"
diff --git a/tests/MC/LoongArch/d-bound-check.s.yaml b/tests/MC/LoongArch/d-bound-check.s.yaml
new file mode 100644
index 000000000..216e0c56d
--- /dev/null
+++ b/tests/MC/LoongArch/d-bound-check.s.yaml
@@ -0,0 +1,46 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x63, 0x37, 0x74, 0x38 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fldgt.s $fa3, $s4, $t1"
+  -
+    input:
+      bytes: [ 0xba, 0xfc, 0x74, 0x38 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fldgt.d $fs2, $a1, $s8"
+  -
+    input:
+      bytes: [ 0xe3, 0xd9, 0x75, 0x38 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fldle.d $fa3, $t3, $fp"
+  -
+    input:
+      bytes: [ 0x6d, 0xe9, 0x76, 0x38 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fstgt.d $ft5, $a7, $s3"
+  -
+    input:
+      bytes: [ 0x32, 0xb5, 0x77, 0x38 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fstle.d $ft10, $a5, $t1"
diff --git a/tests/MC/LoongArch/d-branch.s.yaml b/tests/MC/LoongArch/d-branch.s.yaml
new file mode 100644
index 000000000..de6f91ffc
--- /dev/null
+++ b/tests/MC/LoongArch/d-branch.s.yaml
@@ -0,0 +1,10 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xc0, 0x0c, 0x00, 0x48 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "bceqz $fcc6, 0xc"
diff --git a/tests/MC/LoongArch/d-comp.s.yaml b/tests/MC/LoongArch/d-comp.s.yaml
new file mode 100644
index 000000000..2ac4d2a83
--- /dev/null
+++ b/tests/MC/LoongArch/d-comp.s.yaml
@@ -0,0 +1,208 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x04, 0x10, 0x0c ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmp.caf.s $fcc0, $fa0, $fa1"
+  -
+    input:
+      bytes: [ 0x00, 0x04, 0x20, 0x0c ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmp.caf.d $fcc0, $fa0, $fa1"
+  -
+    input:
+      bytes: [ 0x00, 0x04, 0x24, 0x0c ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmp.cun.d $fcc0, $fa0, $fa1"
+  -
+    input:
+      bytes: [ 0x00, 0x04, 0x22, 0x0c ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmp.ceq.d $fcc0, $fa0, $fa1"
+  -
+    input:
+      bytes: [ 0x00, 0x04, 0x26, 0x0c ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmp.cueq.d $fcc0, $fa0, $fa1"
+  -
+    input:
+      bytes: [ 0x00, 0x04, 0x21, 0x0c ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmp.clt.d $fcc0, $fa0, $fa1"
+  -
+    input:
+      bytes: [ 0x00, 0x04, 0x25, 0x0c ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmp.cult.d $fcc0, $fa0, $fa1"
+  -
+    input:
+      bytes: [ 0x00, 0x04, 0x23, 0x0c ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmp.cle.d $fcc0, $fa0, $fa1"
+  -
+    input:
+      bytes: [ 0x00, 0x04, 0x27, 0x0c ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmp.cule.d $fcc0, $fa0, $fa1"
+  -
+    input:
+      bytes: [ 0x00, 0x04, 0x28, 0x0c ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmp.cne.d $fcc0, $fa0, $fa1"
+  -
+    input:
+      bytes: [ 0x00, 0x04, 0x2a, 0x0c ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmp.cor.d $fcc0, $fa0, $fa1"
+  -
+    input:
+      bytes: [ 0x00, 0x04, 0x2c, 0x0c ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmp.cune.d $fcc0, $fa0, $fa1"
+  -
+    input:
+      bytes: [ 0x00, 0x84, 0x20, 0x0c ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmp.saf.d $fcc0, $fa0, $fa1"
+  -
+    input:
+      bytes: [ 0x00, 0x84, 0x24, 0x0c ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmp.sun.d $fcc0, $fa0, $fa1"
+  -
+    input:
+      bytes: [ 0x00, 0x84, 0x22, 0x0c ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmp.seq.d $fcc0, $fa0, $fa1"
+  -
+    input:
+      bytes: [ 0x00, 0x84, 0x26, 0x0c ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmp.sueq.d $fcc0, $fa0, $fa1"
+  -
+    input:
+      bytes: [ 0x00, 0x84, 0x21, 0x0c ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmp.slt.d $fcc0, $fa0, $fa1"
+  -
+    input:
+      bytes: [ 0x00, 0x84, 0x25, 0x0c ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmp.sult.d $fcc0, $fa0, $fa1"
+  -
+    input:
+      bytes: [ 0x00, 0x84, 0x23, 0x0c ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmp.sle.d $fcc0, $fa0, $fa1"
+  -
+    input:
+      bytes: [ 0x00, 0x84, 0x27, 0x0c ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmp.sule.d $fcc0, $fa0, $fa1"
+  -
+    input:
+      bytes: [ 0x00, 0x84, 0x28, 0x0c ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmp.sne.d $fcc0, $fa0, $fa1"
+  -
+    input:
+      bytes: [ 0x00, 0x84, 0x2a, 0x0c ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmp.sor.d $fcc0, $fa0, $fa1"
+  -
+    input:
+      bytes: [ 0x00, 0x84, 0x2c, 0x0c ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmp.sune.d $fcc0, $fa0, $fa1"
diff --git a/tests/MC/LoongArch/d-conv.s.yaml b/tests/MC/LoongArch/d-conv.s.yaml
new file mode 100644
index 000000000..1d6f35190
--- /dev/null
+++ b/tests/MC/LoongArch/d-conv.s.yaml
@@ -0,0 +1,199 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x25, 0x46, 0x1e, 0x01 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "frint.s $fa5, $ft9"
+  -
+    input:
+      bytes: [ 0x6c, 0x1a, 0x19, 0x01 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvt.s.d $ft4, $ft11"
+  -
+    input:
+      bytes: [ 0xca, 0x24, 0x19, 0x01 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvt.d.s $ft2, $fa6"
+  -
+    input:
+      bytes: [ 0xa6, 0x18, 0x1d, 0x01 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "ffint.s.l $fa6, $fa5"
+  -
+    input:
+      bytes: [ 0x58, 0x22, 0x1d, 0x01 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "ffint.d.w $fs0, $ft10"
+  -
+    input:
+      bytes: [ 0x57, 0x2b, 0x1d, 0x01 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "ffint.d.l $ft15, $fs2"
+  -
+    input:
+      bytes: [ 0xc3, 0x09, 0x1b, 0x01 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "ftint.w.d $fa3, $ft6"
+  -
+    input:
+      bytes: [ 0x1f, 0x27, 0x1b, 0x01 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "ftint.l.s $fs7, $fs0"
+  -
+    input:
+      bytes: [ 0x10, 0x2b, 0x1b, 0x01 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "ftint.l.d $ft8, $fs0"
+  -
+    input:
+      bytes: [ 0x07, 0x09, 0x1a, 0x01 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "ftintrm.w.d $fa7, $ft0"
+  -
+    input:
+      bytes: [ 0x58, 0x25, 0x1a, 0x01 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "ftintrm.l.s $fs0, $ft2"
+  -
+    input:
+      bytes: [ 0x29, 0x29, 0x1a, 0x01 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "ftintrm.l.d $ft1, $ft1"
+  -
+    input:
+      bytes: [ 0x6c, 0x48, 0x1a, 0x01 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "ftintrp.w.d $ft4, $fa3"
+  -
+    input:
+      bytes: [ 0x00, 0x66, 0x1a, 0x01 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "ftintrp.l.s $fa0, $ft8"
+  -
+    input:
+      bytes: [ 0xa4, 0x6b, 0x1a, 0x01 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "ftintrp.l.d $fa4, $fs5"
+  -
+    input:
+      bytes: [ 0x19, 0x8b, 0x1a, 0x01 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "ftintrz.w.d $fs1, $fs0"
+  -
+    input:
+      bytes: [ 0xb7, 0xa4, 0x1a, 0x01 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "ftintrz.l.s $ft15, $fa5"
+  -
+    input:
+      bytes: [ 0x43, 0xa9, 0x1a, 0x01 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "ftintrz.l.d $fa3, $ft2"
+  -
+    input:
+      bytes: [ 0x9f, 0xc9, 0x1a, 0x01 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "ftintrne.w.d $fs7, $ft4"
+  -
+    input:
+      bytes: [ 0x76, 0xe7, 0x1a, 0x01 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "ftintrne.l.s $ft14, $fs3"
+  -
+    input:
+      bytes: [ 0xdc, 0xe8, 0x1a, 0x01 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "ftintrne.l.d $fs4, $fa6"
+  -
+    input:
+      bytes: [ 0x5d, 0x48, 0x1e, 0x01 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "frint.d $fs5, $fa2"
diff --git a/tests/MC/LoongArch/d-memory.s.yaml b/tests/MC/LoongArch/d-memory.s.yaml
new file mode 100644
index 000000000..a1eeb5027
--- /dev/null
+++ b/tests/MC/LoongArch/d-memory.s.yaml
@@ -0,0 +1,46 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xf7, 0xe9, 0x03, 0x2b ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fld.s $ft15, $t3, 0xfa"
+  -
+    input:
+      bytes: [ 0x36, 0xca, 0x81, 0x2b ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fld.d $ft14, $t5, 0x72"
+  -
+    input:
+      bytes: [ 0xfc, 0x18, 0xc3, 0x2b ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fst.d $fs4, $a3, 0xc6"
+  -
+    input:
+      bytes: [ 0xbb, 0x7d, 0x34, 0x38 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fldx.d $fs3, $t1, $s8"
+  -
+    input:
+      bytes: [ 0xe6, 0x45, 0x3c, 0x38 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fstx.d $fa6, $t3, $t5"
diff --git a/tests/MC/LoongArch/d-move.s.yaml b/tests/MC/LoongArch/d-move.s.yaml
new file mode 100644
index 000000000..e13728684
--- /dev/null
+++ b/tests/MC/LoongArch/d-move.s.yaml
@@ -0,0 +1,28 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xed, 0x96, 0x14, 0x01 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov.s $ft5, $ft15"
+  -
+    input:
+      bytes: [ 0x3e, 0x99, 0x14, 0x01 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov.d $fs6, $ft1"
+  -
+    input:
+      bytes: [ 0x92, 0x56, 0x02, 0x0d ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsel $ft10, $ft12, $ft13, $fcc4"
diff --git a/tests/MC/LoongArch/div.s.yaml b/tests/MC/LoongArch/div.s.yaml
new file mode 100644
index 000000000..fce252bce
--- /dev/null
+++ b/tests/MC/LoongArch/div.s.yaml
@@ -0,0 +1,73 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x29, 0x23, 0xe0, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvdiv.b $xr9, $xr25, $xr8"
+  -
+    input:
+      bytes: [ 0x32, 0xec, 0xe0, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvdiv.h $xr18, $xr1, $xr27"
+  -
+    input:
+      bytes: [ 0x45, 0x6f, 0xe1, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvdiv.w $xr5, $xr26, $xr27"
+  -
+    input:
+      bytes: [ 0x5b, 0xb3, 0xe1, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvdiv.d $xr27, $xr26, $xr12"
+  -
+    input:
+      bytes: [ 0xc0, 0x7a, 0xe4, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvdiv.bu $xr0, $xr22, $xr30"
+  -
+    input:
+      bytes: [ 0xff, 0xe6, 0xe4, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvdiv.hu $xr31, $xr23, $xr25"
+  -
+    input:
+      bytes: [ 0x21, 0x1f, 0xe5, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvdiv.wu $xr1, $xr25, $xr7"
+  -
+    input:
+      bytes: [ 0x27, 0x9f, 0xe5, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvdiv.du $xr7, $xr25, $xr7"
diff --git a/tests/MC/LoongArch/ext2xv.s.yaml b/tests/MC/LoongArch/ext2xv.s.yaml
new file mode 100644
index 000000000..2a2adc813
--- /dev/null
+++ b/tests/MC/LoongArch/ext2xv.s.yaml
@@ -0,0 +1,109 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x7e, 0x12, 0x9f, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vext2xv.h.b $xr30, $xr19"
+  -
+    input:
+      bytes: [ 0xbb, 0x14, 0x9f, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vext2xv.w.b $xr27, $xr5"
+  -
+    input:
+      bytes: [ 0x39, 0x1b, 0x9f, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vext2xv.d.b $xr25, $xr25"
+  -
+    input:
+      bytes: [ 0x94, 0x1e, 0x9f, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vext2xv.w.h $xr20, $xr20"
+  -
+    input:
+      bytes: [ 0x68, 0x22, 0x9f, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vext2xv.d.h $xr8, $xr19"
+  -
+    input:
+      bytes: [ 0x24, 0x27, 0x9f, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vext2xv.d.w $xr4, $xr25"
+  -
+    input:
+      bytes: [ 0x99, 0x29, 0x9f, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vext2xv.hu.bu $xr25, $xr12"
+  -
+    input:
+      bytes: [ 0xbf, 0x2d, 0x9f, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vext2xv.wu.bu $xr31, $xr13"
+  -
+    input:
+      bytes: [ 0x2c, 0x33, 0x9f, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vext2xv.du.bu $xr12, $xr25"
+  -
+    input:
+      bytes: [ 0x97, 0x35, 0x9f, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vext2xv.wu.hu $xr23, $xr12"
+  -
+    input:
+      bytes: [ 0xd2, 0x38, 0x9f, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vext2xv.du.hu $xr18, $xr6"
+  -
+    input:
+      bytes: [ 0xaa, 0x3e, 0x9f, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vext2xv.du.wu $xr10, $xr21"
diff --git a/tests/MC/LoongArch/exth.s.yaml b/tests/MC/LoongArch/exth.s.yaml
new file mode 100644
index 000000000..24dadb7e1
--- /dev/null
+++ b/tests/MC/LoongArch/exth.s.yaml
@@ -0,0 +1,73 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x4f, 0xe1, 0x9e, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvexth.h.b $xr15, $xr10"
+  -
+    input:
+      bytes: [ 0x7a, 0xe5, 0x9e, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvexth.w.h $xr26, $xr11"
+  -
+    input:
+      bytes: [ 0x62, 0xeb, 0x9e, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvexth.d.w $xr2, $xr27"
+  -
+    input:
+      bytes: [ 0x36, 0xef, 0x9e, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvexth.q.d $xr22, $xr25"
+  -
+    input:
+      bytes: [ 0xd5, 0xf3, 0x9e, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvexth.hu.bu $xr21, $xr30"
+  -
+    input:
+      bytes: [ 0x7c, 0xf5, 0x9e, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvexth.wu.hu $xr28, $xr11"
+  -
+    input:
+      bytes: [ 0x3b, 0xfb, 0x9e, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvexth.du.wu $xr27, $xr25"
+  -
+    input:
+      bytes: [ 0x90, 0xff, 0x9e, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvexth.qu.du $xr16, $xr28"
diff --git a/tests/MC/LoongArch/extl.s.yaml b/tests/MC/LoongArch/extl.s.yaml
new file mode 100644
index 000000000..0aa2aa8f6
--- /dev/null
+++ b/tests/MC/LoongArch/extl.s.yaml
@@ -0,0 +1,19 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x9d, 0x01, 0x09, 0x77 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvextl.q.d $xr29, $xr12"
+  -
+    input:
+      bytes: [ 0x9b, 0x02, 0x0d, 0x77 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvextl.qu.du $xr27, $xr20"
diff --git a/tests/MC/LoongArch/extrins.s.yaml b/tests/MC/LoongArch/extrins.s.yaml
new file mode 100644
index 000000000..181d5e94f
--- /dev/null
+++ b/tests/MC/LoongArch/extrins.s.yaml
@@ -0,0 +1,37 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xfe, 0xf2, 0x8f, 0x77 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvextrins.b $xr30, $xr23, 0xfc"
+  -
+    input:
+      bytes: [ 0xa0, 0x21, 0x8b, 0x77 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvextrins.h $xr0, $xr13, 0xc8"
+  -
+    input:
+      bytes: [ 0xae, 0x62, 0x86, 0x77 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvextrins.w $xr14, $xr21, 0x98"
+  -
+    input:
+      bytes: [ 0xdf, 0x1f, 0x82, 0x77 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvextrins.d $xr31, $xr30, 0x87"
diff --git a/tests/MC/LoongArch/f-arith.s.yaml b/tests/MC/LoongArch/f-arith.s.yaml
new file mode 100644
index 000000000..08247b72b
--- /dev/null
+++ b/tests/MC/LoongArch/f-arith.s.yaml
@@ -0,0 +1,208 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xfd, 0xe5, 0x00, 0x01 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd.s $fs5, $ft7, $fs1"
+  -
+    input:
+      bytes: [ 0xce, 0xfc, 0x02, 0x01 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub.s $ft6, $fa6, $fs7"
+  -
+    input:
+      bytes: [ 0xe0, 0xc4, 0x04, 0x01 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmul.s $fa0, $fa7, $ft9"
+  -
+    input:
+      bytes: [ 0x14, 0xcf, 0x06, 0x01 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdiv.s $ft12, $fs0, $ft11"
+  -
+    input:
+      bytes: [ 0x03, 0x8e, 0x17, 0x08 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmadd.s $fa3, $ft8, $fa3, $ft7"
+  -
+    input:
+      bytes: [ 0x77, 0x55, 0x52, 0x08 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmsub.s $ft15, $ft3, $ft13, $fa4"
+  -
+    input:
+      bytes: [ 0x3d, 0x60, 0x9a, 0x08 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fnmadd.s $fs5, $fa1, $fs0, $ft12"
+  -
+    input:
+      bytes: [ 0x88, 0xe0, 0xdc, 0x08 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fnmsub.s $ft0, $fa4, $fs0, $fs1"
+  -
+    input:
+      bytes: [ 0xd6, 0xec, 0x08, 0x01 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmax.s $ft14, $fa6, $fs3"
+  -
+    input:
+      bytes: [ 0x4e, 0xcd, 0x0a, 0x01 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmin.s $ft6, $ft2, $ft11"
+  -
+    input:
+      bytes: [ 0x69, 0xff, 0x0c, 0x01 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmaxa.s $ft1, $fs3, $fs7"
+  -
+    input:
+      bytes: [ 0x4f, 0x86, 0x0e, 0x01 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmina.s $ft7, $ft10, $fa1"
+  -
+    input:
+      bytes: [ 0x9c, 0x05, 0x14, 0x01 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fabs.s $fs4, $ft4"
+  -
+    input:
+      bytes: [ 0x15, 0x17, 0x14, 0x01 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fneg.s $ft13, $fs0"
+  -
+    input:
+      bytes: [ 0x5b, 0x46, 0x14, 0x01 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsqrt.s $fs3, $ft10"
+  -
+    input:
+      bytes: [ 0x71, 0x57, 0x14, 0x01 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "frecip.s $ft9, $fs3"
+  -
+    input:
+      bytes: [ 0x00, 0x74, 0x14, 0x01 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "frecipe.s $fa0, $fa0"
+  -
+    input:
+      bytes: [ 0x99, 0x65, 0x14, 0x01 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "frsqrt.s $fs1, $ft4"
+  -
+    input:
+      bytes: [ 0x21, 0x84, 0x14, 0x01 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "frsqrte.s $fa1, $fa1"
+  -
+    input:
+      bytes: [ 0xf5, 0x9a, 0x10, 0x01 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fscaleb.s $ft13, $ft15, $fa6"
+  -
+    input:
+      bytes: [ 0xff, 0x26, 0x14, 0x01 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "flogb.s $fs7, $ft15"
+  -
+    input:
+      bytes: [ 0x0d, 0xdf, 0x12, 0x01 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcopysign.s $ft5, $fs0, $ft15"
+  -
+    input:
+      bytes: [ 0x34, 0x35, 0x14, 0x01 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fclass.s $ft12, $ft1"
diff --git a/tests/MC/LoongArch/f-bound-check.s.yaml b/tests/MC/LoongArch/f-bound-check.s.yaml
new file mode 100644
index 000000000..e973c3b9a
--- /dev/null
+++ b/tests/MC/LoongArch/f-bound-check.s.yaml
@@ -0,0 +1,37 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x63, 0x37, 0x74, 0x38 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fldgt.s $fa3, $s4, $t1"
+  -
+    input:
+      bytes: [ 0xb8, 0x47, 0x75, 0x38 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fldle.s $fs0, $s6, $t5"
+  -
+    input:
+      bytes: [ 0xbf, 0x79, 0x76, 0x38 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fstgt.s $fs7, $t1, $s7"
+  -
+    input:
+      bytes: [ 0xad, 0x1d, 0x77, 0x38 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fstle.s $ft5, $t1, $a3"
diff --git a/tests/MC/LoongArch/f-branch.s.yaml b/tests/MC/LoongArch/f-branch.s.yaml
new file mode 100644
index 000000000..da87d45ed
--- /dev/null
+++ b/tests/MC/LoongArch/f-branch.s.yaml
@@ -0,0 +1,19 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xc0, 0x0c, 0x00, 0x48 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "bceqz $fcc6, 0xc"
+  -
+    input:
+      bytes: [ 0xc0, 0x49, 0x00, 0x48 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "bcnez $fcc6, 0x48"
diff --git a/tests/MC/LoongArch/f-comp.s.yaml b/tests/MC/LoongArch/f-comp.s.yaml
new file mode 100644
index 000000000..8a01684fe
--- /dev/null
+++ b/tests/MC/LoongArch/f-comp.s.yaml
@@ -0,0 +1,199 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x04, 0x10, 0x0c ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmp.caf.s $fcc0, $fa0, $fa1"
+  -
+    input:
+      bytes: [ 0x00, 0x04, 0x14, 0x0c ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmp.cun.s $fcc0, $fa0, $fa1"
+  -
+    input:
+      bytes: [ 0x00, 0x04, 0x12, 0x0c ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmp.ceq.s $fcc0, $fa0, $fa1"
+  -
+    input:
+      bytes: [ 0x00, 0x04, 0x16, 0x0c ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmp.cueq.s $fcc0, $fa0, $fa1"
+  -
+    input:
+      bytes: [ 0x00, 0x04, 0x11, 0x0c ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmp.clt.s $fcc0, $fa0, $fa1"
+  -
+    input:
+      bytes: [ 0x00, 0x04, 0x15, 0x0c ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmp.cult.s $fcc0, $fa0, $fa1"
+  -
+    input:
+      bytes: [ 0x00, 0x04, 0x13, 0x0c ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmp.cle.s $fcc0, $fa0, $fa1"
+  -
+    input:
+      bytes: [ 0x00, 0x04, 0x17, 0x0c ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmp.cule.s $fcc0, $fa0, $fa1"
+  -
+    input:
+      bytes: [ 0x00, 0x04, 0x18, 0x0c ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmp.cne.s $fcc0, $fa0, $fa1"
+  -
+    input:
+      bytes: [ 0x00, 0x04, 0x1a, 0x0c ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmp.cor.s $fcc0, $fa0, $fa1"
+  -
+    input:
+      bytes: [ 0x00, 0x04, 0x1c, 0x0c ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmp.cune.s $fcc0, $fa0, $fa1"
+  -
+    input:
+      bytes: [ 0x00, 0x84, 0x10, 0x0c ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmp.saf.s $fcc0, $fa0, $fa1"
+  -
+    input:
+      bytes: [ 0x00, 0x84, 0x14, 0x0c ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmp.sun.s $fcc0, $fa0, $fa1"
+  -
+    input:
+      bytes: [ 0x00, 0x84, 0x12, 0x0c ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmp.seq.s $fcc0, $fa0, $fa1"
+  -
+    input:
+      bytes: [ 0x00, 0x84, 0x16, 0x0c ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmp.sueq.s $fcc0, $fa0, $fa1"
+  -
+    input:
+      bytes: [ 0x00, 0x84, 0x11, 0x0c ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmp.slt.s $fcc0, $fa0, $fa1"
+  -
+    input:
+      bytes: [ 0x00, 0x84, 0x15, 0x0c ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmp.sult.s $fcc0, $fa0, $fa1"
+  -
+    input:
+      bytes: [ 0x00, 0x84, 0x13, 0x0c ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmp.sle.s $fcc0, $fa0, $fa1"
+  -
+    input:
+      bytes: [ 0x00, 0x84, 0x17, 0x0c ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmp.sule.s $fcc0, $fa0, $fa1"
+  -
+    input:
+      bytes: [ 0x00, 0x84, 0x18, 0x0c ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmp.sne.s $fcc0, $fa0, $fa1"
+  -
+    input:
+      bytes: [ 0x00, 0x84, 0x1a, 0x0c ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmp.sor.s $fcc0, $fa0, $fa1"
+  -
+    input:
+      bytes: [ 0x00, 0x84, 0x1c, 0x0c ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmp.sune.s $fcc0, $fa0, $fa1"
diff --git a/tests/MC/LoongArch/f-conv.s.yaml b/tests/MC/LoongArch/f-conv.s.yaml
new file mode 100644
index 000000000..3b3e5aa09
--- /dev/null
+++ b/tests/MC/LoongArch/f-conv.s.yaml
@@ -0,0 +1,64 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xbe, 0x10, 0x1d, 0x01 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "ffint.s.w $fs6, $fa5"
+  -
+    input:
+      bytes: [ 0xb5, 0x05, 0x1b, 0x01 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "ftint.w.s $ft13, $ft5"
+  -
+    input:
+      bytes: [ 0x10, 0x06, 0x1a, 0x01 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "ftintrm.w.s $ft8, $ft8"
+  -
+    input:
+      bytes: [ 0xee, 0x47, 0x1a, 0x01 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "ftintrp.w.s $ft6, $fs7"
+  -
+    input:
+      bytes: [ 0xa4, 0x87, 0x1a, 0x01 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "ftintrz.w.s $fa4, $fs5"
+  -
+    input:
+      bytes: [ 0x24, 0xc6, 0x1a, 0x01 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "ftintrne.w.s $fa4, $ft9"
+  -
+    input:
+      bytes: [ 0x25, 0x46, 0x1e, 0x01 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "frint.s $fa5, $ft9"
diff --git a/tests/MC/LoongArch/f-memory.s.yaml b/tests/MC/LoongArch/f-memory.s.yaml
new file mode 100644
index 000000000..82d799bd0
--- /dev/null
+++ b/tests/MC/LoongArch/f-memory.s.yaml
@@ -0,0 +1,37 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xf7, 0xe9, 0x03, 0x2b ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fld.s $ft15, $t3, 0xfa"
+  -
+    input:
+      bytes: [ 0x7e, 0x9a, 0x43, 0x2b ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fst.s $fs6, $t7, 0xe6"
+  -
+    input:
+      bytes: [ 0xe1, 0x4d, 0x30, 0x38 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fldx.s $fa1, $t3, $t7"
+  -
+    input:
+      bytes: [ 0x7a, 0x58, 0x38, 0x38 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fstx.s $fs2, $sp, $fp"
diff --git a/tests/MC/LoongArch/f-move.s.yaml b/tests/MC/LoongArch/f-move.s.yaml
new file mode 100644
index 000000000..c6d0904d0
--- /dev/null
+++ b/tests/MC/LoongArch/f-move.s.yaml
@@ -0,0 +1,145 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xed, 0x96, 0x14, 0x01 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmov.s $ft5, $ft15"
+  -
+    input:
+      bytes: [ 0x92, 0x56, 0x02, 0x0d ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsel $ft10, $ft12, $ft13, $fcc4"
+  -
+    input:
+      bytes: [ 0x46, 0xa4, 0x14, 0x01 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "movgr2fr.w $fa6, $tp"
+  -
+    input:
+      bytes: [ 0xca, 0xb6, 0x14, 0x01 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "movfr2gr.s $a6, $ft14"
+  -
+    input:
+      bytes: [ 0x80, 0xc0, 0x14, 0x01 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "movgr2fcsr $fcsr0, $a0"
+  -
+    input:
+      bytes: [ 0x04, 0xc8, 0x14, 0x01 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "movfcsr2gr $a0, $fcsr0"
+  -
+    input:
+      bytes: [ 0x81, 0xc0, 0x14, 0x01 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "movgr2fcsr $fcsr1, $a0"
+  -
+    input:
+      bytes: [ 0x24, 0xc8, 0x14, 0x01 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "movfcsr2gr $a0, $fcsr1"
+  -
+    input:
+      bytes: [ 0x82, 0xc0, 0x14, 0x01 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "movgr2fcsr $fcsr2, $a0"
+  -
+    input:
+      bytes: [ 0x44, 0xc8, 0x14, 0x01 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "movfcsr2gr $a0, $fcsr2"
+  -
+    input:
+      bytes: [ 0x83, 0xc0, 0x14, 0x01 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "movgr2fcsr $fcsr3, $a0"
+  -
+    input:
+      bytes: [ 0x64, 0xc8, 0x14, 0x01 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "movfcsr2gr $a0, $fcsr3"
+  -
+    input:
+      bytes: [ 0x64, 0xd1, 0x14, 0x01 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "movfr2cf $fcc4, $ft3"
+  -
+    input:
+      bytes: [ 0x10, 0xd4, 0x14, 0x01 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "movcf2fr $ft8, $fcc0"
+  -
+    input:
+      bytes: [ 0x25, 0xd8, 0x14, 0x01 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "movgr2cf $fcc5, $ra"
+  -
+    input:
+      bytes: [ 0xf5, 0xdc, 0x14, 0x01 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "movcf2gr $r21, $fcc7"
diff --git a/tests/MC/LoongArch/fadd.s.yaml b/tests/MC/LoongArch/fadd.s.yaml
new file mode 100644
index 000000000..f0ec82215
--- /dev/null
+++ b/tests/MC/LoongArch/fadd.s.yaml
@@ -0,0 +1,19 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xa6, 0xbe, 0x30, 0x75 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvfadd.s $xr6, $xr21, $xr15"
+  -
+    input:
+      bytes: [ 0x1b, 0x05, 0x31, 0x75 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvfadd.d $xr27, $xr8, $xr1"
diff --git a/tests/MC/LoongArch/fclass.s.yaml b/tests/MC/LoongArch/fclass.s.yaml
new file mode 100644
index 000000000..9c6ca3848
--- /dev/null
+++ b/tests/MC/LoongArch/fclass.s.yaml
@@ -0,0 +1,19 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xe3, 0xd4, 0x9c, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvfclass.s $xr3, $xr7"
+  -
+    input:
+      bytes: [ 0x56, 0xd9, 0x9c, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvfclass.d $xr22, $xr10"
diff --git a/tests/MC/LoongArch/fcmp.s.yaml b/tests/MC/LoongArch/fcmp.s.yaml
new file mode 100644
index 000000000..72c744f40
--- /dev/null
+++ b/tests/MC/LoongArch/fcmp.s.yaml
@@ -0,0 +1,397 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x01, 0x7d, 0x90, 0x0c ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvfcmp.caf.s $xr1, $xr8, $xr31"
+  -
+    input:
+      bytes: [ 0xf3, 0x53, 0xa0, 0x0c ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvfcmp.caf.d $xr19, $xr31, $xr20"
+  -
+    input:
+      bytes: [ 0x28, 0x75, 0x94, 0x0c ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvfcmp.cun.s $xr8, $xr9, $xr29"
+  -
+    input:
+      bytes: [ 0xd3, 0x72, 0xa4, 0x0c ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvfcmp.cun.d $xr19, $xr22, $xr28"
+  -
+    input:
+      bytes: [ 0x20, 0x00, 0x92, 0x0c ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvfcmp.ceq.s $xr0, $xr1, $xr0"
+  -
+    input:
+      bytes: [ 0xfd, 0x52, 0xa2, 0x0c ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvfcmp.ceq.d $xr29, $xr23, $xr20"
+  -
+    input:
+      bytes: [ 0xa5, 0x7d, 0x96, 0x0c ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvfcmp.cueq.s $xr5, $xr13, $xr31"
+  -
+    input:
+      bytes: [ 0xc4, 0x1e, 0xa6, 0x0c ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvfcmp.cueq.d $xr4, $xr22, $xr7"
+  -
+    input:
+      bytes: [ 0x24, 0x05, 0x91, 0x0c ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvfcmp.clt.s $xr4, $xr9, $xr1"
+  -
+    input:
+      bytes: [ 0x93, 0x54, 0xa1, 0x0c ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvfcmp.clt.d $xr19, $xr4, $xr21"
+  -
+    input:
+      bytes: [ 0x2f, 0x0e, 0x95, 0x0c ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvfcmp.cult.s $xr15, $xr17, $xr3"
+  -
+    input:
+      bytes: [ 0x34, 0x1a, 0xa5, 0x0c ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvfcmp.cult.d $xr20, $xr17, $xr6"
+  -
+    input:
+      bytes: [ 0xd6, 0x3e, 0x93, 0x0c ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvfcmp.cle.s $xr22, $xr22, $xr15"
+  -
+    input:
+      bytes: [ 0x35, 0x33, 0xa3, 0x0c ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvfcmp.cle.d $xr21, $xr25, $xr12"
+  -
+    input:
+      bytes: [ 0x41, 0x74, 0x97, 0x0c ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvfcmp.cule.s $xr1, $xr2, $xr29"
+  -
+    input:
+      bytes: [ 0xa0, 0x2c, 0xa7, 0x0c ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvfcmp.cule.d $xr0, $xr5, $xr11"
+  -
+    input:
+      bytes: [ 0x27, 0x6a, 0x98, 0x0c ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvfcmp.cne.s $xr7, $xr17, $xr26"
+  -
+    input:
+      bytes: [ 0x32, 0x03, 0xa8, 0x0c ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvfcmp.cne.d $xr18, $xr25, $xr0"
+  -
+    input:
+      bytes: [ 0x41, 0x38, 0x9a, 0x0c ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvfcmp.cor.s $xr1, $xr2, $xr14"
+  -
+    input:
+      bytes: [ 0x6c, 0x5e, 0xaa, 0x0c ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvfcmp.cor.d $xr12, $xr19, $xr23"
+  -
+    input:
+      bytes: [ 0x35, 0x12, 0x9c, 0x0c ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvfcmp.cune.s $xr21, $xr17, $xr4"
+  -
+    input:
+      bytes: [ 0xd4, 0x33, 0xac, 0x0c ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvfcmp.cune.d $xr20, $xr30, $xr12"
+  -
+    input:
+      bytes: [ 0x77, 0x89, 0x90, 0x0c ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvfcmp.saf.s $xr23, $xr11, $xr2"
+  -
+    input:
+      bytes: [ 0x87, 0x9d, 0xa0, 0x0c ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvfcmp.saf.d $xr7, $xr12, $xr7"
+  -
+    input:
+      bytes: [ 0xe0, 0xf8, 0x94, 0x0c ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvfcmp.sun.s $xr0, $xr7, $xr30"
+  -
+    input:
+      bytes: [ 0x64, 0xf9, 0xa4, 0x0c ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvfcmp.sun.d $xr4, $xr11, $xr30"
+  -
+    input:
+      bytes: [ 0xef, 0xee, 0x92, 0x0c ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvfcmp.seq.s $xr15, $xr23, $xr27"
+  -
+    input:
+      bytes: [ 0xcf, 0x8e, 0xa2, 0x0c ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvfcmp.seq.d $xr15, $xr22, $xr3"
+  -
+    input:
+      bytes: [ 0x4c, 0xa7, 0x96, 0x0c ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvfcmp.sueq.s $xr12, $xr26, $xr9"
+  -
+    input:
+      bytes: [ 0x45, 0xc6, 0xa6, 0x0c ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvfcmp.sueq.d $xr5, $xr18, $xr17"
+  -
+    input:
+      bytes: [ 0x59, 0xfe, 0x91, 0x0c ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvfcmp.slt.s $xr25, $xr18, $xr31"
+  -
+    input:
+      bytes: [ 0x51, 0xe3, 0xa1, 0x0c ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvfcmp.slt.d $xr17, $xr26, $xr24"
+  -
+    input:
+      bytes: [ 0xe8, 0xc9, 0x95, 0x0c ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvfcmp.sult.s $xr8, $xr15, $xr18"
+  -
+    input:
+      bytes: [ 0x84, 0x94, 0xa5, 0x0c ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvfcmp.sult.d $xr4, $xr4, $xr5"
+  -
+    input:
+      bytes: [ 0xa1, 0xc0, 0x93, 0x0c ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvfcmp.sle.s $xr1, $xr5, $xr16"
+  -
+    input:
+      bytes: [ 0x23, 0xdc, 0xa3, 0x0c ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvfcmp.sle.d $xr3, $xr1, $xr23"
+  -
+    input:
+      bytes: [ 0x77, 0x85, 0x97, 0x0c ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvfcmp.sule.s $xr23, $xr11, $xr1"
+  -
+    input:
+      bytes: [ 0x4b, 0xc5, 0xa7, 0x0c ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvfcmp.sule.d $xr11, $xr10, $xr17"
+  -
+    input:
+      bytes: [ 0x9b, 0xf9, 0x98, 0x0c ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvfcmp.sne.s $xr27, $xr12, $xr30"
+  -
+    input:
+      bytes: [ 0x94, 0xc6, 0xa8, 0x0c ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvfcmp.sne.d $xr20, $xr20, $xr17"
+  -
+    input:
+      bytes: [ 0xab, 0x89, 0x9a, 0x0c ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvfcmp.sor.s $xr11, $xr13, $xr2"
+  -
+    input:
+      bytes: [ 0x86, 0x9b, 0xaa, 0x0c ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvfcmp.sor.d $xr6, $xr28, $xr6"
+  -
+    input:
+      bytes: [ 0x0b, 0xa2, 0x9c, 0x0c ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvfcmp.sune.s $xr11, $xr16, $xr8"
+  -
+    input:
+      bytes: [ 0xbe, 0xec, 0xac, 0x0c ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvfcmp.sune.d $xr30, $xr5, $xr27"
diff --git a/tests/MC/LoongArch/fcvt.s.yaml b/tests/MC/LoongArch/fcvt.s.yaml
new file mode 100644
index 000000000..2316aa094
--- /dev/null
+++ b/tests/MC/LoongArch/fcvt.s.yaml
@@ -0,0 +1,19 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x29, 0x5e, 0x46, 0x75 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvfcvt.h.s $xr9, $xr17, $xr23"
+  -
+    input:
+      bytes: [ 0x5b, 0xf5, 0x46, 0x75 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvfcvt.s.d $xr27, $xr10, $xr29"
diff --git a/tests/MC/LoongArch/fcvth.s.yaml b/tests/MC/LoongArch/fcvth.s.yaml
new file mode 100644
index 000000000..16c6d239f
--- /dev/null
+++ b/tests/MC/LoongArch/fcvth.s.yaml
@@ -0,0 +1,19 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x29, 0xef, 0x9d, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvfcvth.s.h $xr9, $xr25"
+  -
+    input:
+      bytes: [ 0x3d, 0xf6, 0x9d, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvfcvth.d.s $xr29, $xr17"
diff --git a/tests/MC/LoongArch/fcvtl.s.yaml b/tests/MC/LoongArch/fcvtl.s.yaml
new file mode 100644
index 000000000..98a21d70b
--- /dev/null
+++ b/tests/MC/LoongArch/fcvtl.s.yaml
@@ -0,0 +1,19 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xd0, 0xe9, 0x9d, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvfcvtl.s.h $xr16, $xr14"
+  -
+    input:
+      bytes: [ 0xb8, 0xf0, 0x9d, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvfcvtl.d.s $xr24, $xr5"
diff --git a/tests/MC/LoongArch/fdiv.s.yaml b/tests/MC/LoongArch/fdiv.s.yaml
new file mode 100644
index 000000000..1b90e55e4
--- /dev/null
+++ b/tests/MC/LoongArch/fdiv.s.yaml
@@ -0,0 +1,19 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xbd, 0xb0, 0x3a, 0x75 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvfdiv.s $xr29, $xr5, $xr12"
+  -
+    input:
+      bytes: [ 0x5f, 0x79, 0x3b, 0x75 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvfdiv.d $xr31, $xr10, $xr30"
diff --git a/tests/MC/LoongArch/ffint.s.yaml b/tests/MC/LoongArch/ffint.s.yaml
new file mode 100644
index 000000000..28a421a81
--- /dev/null
+++ b/tests/MC/LoongArch/ffint.s.yaml
@@ -0,0 +1,64 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0x9e, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvffint.s.w $xr3, $xr5"
+  -
+    input:
+      bytes: [ 0x65, 0x0a, 0x9e, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvffint.d.l $xr5, $xr19"
+  -
+    input:
+      bytes: [ 0x83, 0x07, 0x9e, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvffint.s.wu $xr3, $xr28"
+  -
+    input:
+      bytes: [ 0xbf, 0x0f, 0x9e, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvffint.d.lu $xr31, $xr29"
+  -
+    input:
+      bytes: [ 0xe2, 0x10, 0x9e, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvffintl.d.w $xr2, $xr7"
+  -
+    input:
+      bytes: [ 0x87, 0x17, 0x9e, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvffinth.d.w $xr7, $xr28"
+  -
+    input:
+      bytes: [ 0x6a, 0x0f, 0x48, 0x75 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvffint.s.l $xr10, $xr27, $xr3"
diff --git a/tests/MC/LoongArch/flogb.s.yaml b/tests/MC/LoongArch/flogb.s.yaml
new file mode 100644
index 000000000..77dd2a16a
--- /dev/null
+++ b/tests/MC/LoongArch/flogb.s.yaml
@@ -0,0 +1,19 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x91, 0xc5, 0x9c, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvflogb.s $xr17, $xr12"
+  -
+    input:
+      bytes: [ 0x3a, 0xc8, 0x9c, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvflogb.d $xr26, $xr1"
diff --git a/tests/MC/LoongArch/fmadd.s.yaml b/tests/MC/LoongArch/fmadd.s.yaml
new file mode 100644
index 000000000..a1d79bc11
--- /dev/null
+++ b/tests/MC/LoongArch/fmadd.s.yaml
@@ -0,0 +1,19 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xe5, 0xff, 0x1d, 0x0a ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvfmadd.s $xr5, $xr31, $xr31, $xr27"
+  -
+    input:
+      bytes: [ 0x09, 0xfe, 0x2c, 0x0a ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvfmadd.d $xr9, $xr16, $xr31, $xr25"
diff --git a/tests/MC/LoongArch/fmax.s.yaml b/tests/MC/LoongArch/fmax.s.yaml
new file mode 100644
index 000000000..cb526db71
--- /dev/null
+++ b/tests/MC/LoongArch/fmax.s.yaml
@@ -0,0 +1,19 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x1d, 0xa3, 0x3c, 0x75 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvfmax.s $xr29, $xr24, $xr8"
+  -
+    input:
+      bytes: [ 0x3f, 0x5f, 0x3d, 0x75 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvfmax.d $xr31, $xr25, $xr23"
diff --git a/tests/MC/LoongArch/fmaxa.s.yaml b/tests/MC/LoongArch/fmaxa.s.yaml
new file mode 100644
index 000000000..a97029a1b
--- /dev/null
+++ b/tests/MC/LoongArch/fmaxa.s.yaml
@@ -0,0 +1,19 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x4f, 0x96, 0x40, 0x75 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvfmaxa.s $xr15, $xr18, $xr5"
+  -
+    input:
+      bytes: [ 0x82, 0x76, 0x41, 0x75 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvfmaxa.d $xr2, $xr20, $xr29"
diff --git a/tests/MC/LoongArch/fmin.s.yaml b/tests/MC/LoongArch/fmin.s.yaml
new file mode 100644
index 000000000..d268dbca1
--- /dev/null
+++ b/tests/MC/LoongArch/fmin.s.yaml
@@ -0,0 +1,19 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xbf, 0xc0, 0x3e, 0x75 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvfmin.s $xr31, $xr5, $xr16"
+  -
+    input:
+      bytes: [ 0xcd, 0x67, 0x3f, 0x75 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvfmin.d $xr13, $xr30, $xr25"
diff --git a/tests/MC/LoongArch/fmina.s.yaml b/tests/MC/LoongArch/fmina.s.yaml
new file mode 100644
index 000000000..fb4c78211
--- /dev/null
+++ b/tests/MC/LoongArch/fmina.s.yaml
@@ -0,0 +1,19 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x7d, 0xc7, 0x42, 0x75 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvfmina.s $xr29, $xr27, $xr17"
+  -
+    input:
+      bytes: [ 0x8c, 0x4a, 0x43, 0x75 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvfmina.d $xr12, $xr20, $xr18"
diff --git a/tests/MC/LoongArch/fmsub.s.yaml b/tests/MC/LoongArch/fmsub.s.yaml
new file mode 100644
index 000000000..ad5d3ad31
--- /dev/null
+++ b/tests/MC/LoongArch/fmsub.s.yaml
@@ -0,0 +1,19 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x71, 0x8c, 0x5b, 0x0a ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvfmsub.s $xr17, $xr3, $xr3, $xr23"
+  -
+    input:
+      bytes: [ 0xfe, 0x41, 0x67, 0x0a ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvfmsub.d $xr30, $xr15, $xr16, $xr14"
diff --git a/tests/MC/LoongArch/fmul.s.yaml b/tests/MC/LoongArch/fmul.s.yaml
new file mode 100644
index 000000000..1f9a2ac3b
--- /dev/null
+++ b/tests/MC/LoongArch/fmul.s.yaml
@@ -0,0 +1,19 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xc9, 0xf9, 0x38, 0x75 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvfmul.s $xr9, $xr14, $xr30"
+  -
+    input:
+      bytes: [ 0x5c, 0x4f, 0x39, 0x75 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvfmul.d $xr28, $xr26, $xr19"
diff --git a/tests/MC/LoongArch/fnmadd.s.yaml b/tests/MC/LoongArch/fnmadd.s.yaml
new file mode 100644
index 000000000..b5cc18bd4
--- /dev/null
+++ b/tests/MC/LoongArch/fnmadd.s.yaml
@@ -0,0 +1,19 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xce, 0x5e, 0x9c, 0x0a ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvfnmadd.s $xr14, $xr22, $xr23, $xr24"
+  -
+    input:
+      bytes: [ 0xc1, 0x5f, 0xa6, 0x0a ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvfnmadd.d $xr1, $xr30, $xr23, $xr12"
diff --git a/tests/MC/LoongArch/fnmsub.s.yaml b/tests/MC/LoongArch/fnmsub.s.yaml
new file mode 100644
index 000000000..88f6cfd99
--- /dev/null
+++ b/tests/MC/LoongArch/fnmsub.s.yaml
@@ -0,0 +1,19 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xb6, 0x90, 0xd5, 0x0a ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvfnmsub.s $xr22, $xr5, $xr4, $xr11"
+  -
+    input:
+      bytes: [ 0x08, 0x74, 0xee, 0x0a ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvfnmsub.d $xr8, $xr0, $xr29, $xr28"
diff --git a/tests/MC/LoongArch/frecip.s.yaml b/tests/MC/LoongArch/frecip.s.yaml
new file mode 100644
index 000000000..b3993750a
--- /dev/null
+++ b/tests/MC/LoongArch/frecip.s.yaml
@@ -0,0 +1,37 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x03, 0xf6, 0x9c, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvfrecip.s $xr3, $xr16"
+  -
+    input:
+      bytes: [ 0x11, 0xfb, 0x9c, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvfrecip.d $xr17, $xr24"
+  -
+    input:
+      bytes: [ 0x03, 0x16, 0x9d, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvfrecipe.s $xr3, $xr16"
+  -
+    input:
+      bytes: [ 0x11, 0x1b, 0x9d, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvfrecipe.d $xr17, $xr24"
diff --git a/tests/MC/LoongArch/frint.s.yaml b/tests/MC/LoongArch/frint.s.yaml
new file mode 100644
index 000000000..6fa276013
--- /dev/null
+++ b/tests/MC/LoongArch/frint.s.yaml
@@ -0,0 +1,91 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x33, 0x76, 0x9d, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvfrintrne.s $xr19, $xr17"
+  -
+    input:
+      bytes: [ 0xac, 0x7b, 0x9d, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvfrintrne.d $xr12, $xr29"
+  -
+    input:
+      bytes: [ 0x2a, 0x65, 0x9d, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvfrintrz.s $xr10, $xr9"
+  -
+    input:
+      bytes: [ 0xbd, 0x68, 0x9d, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvfrintrz.d $xr29, $xr5"
+  -
+    input:
+      bytes: [ 0x1a, 0x56, 0x9d, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvfrintrp.s $xr26, $xr16"
+  -
+    input:
+      bytes: [ 0x81, 0x5b, 0x9d, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvfrintrp.d $xr1, $xr28"
+  -
+    input:
+      bytes: [ 0xbb, 0x45, 0x9d, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvfrintrm.s $xr27, $xr13"
+  -
+    input:
+      bytes: [ 0x6e, 0x4b, 0x9d, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvfrintrm.d $xr14, $xr27"
+  -
+    input:
+      bytes: [ 0x15, 0x37, 0x9d, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvfrint.s $xr21, $xr24"
+  -
+    input:
+      bytes: [ 0x5f, 0x3a, 0x9d, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvfrint.d $xr31, $xr18"
diff --git a/tests/MC/LoongArch/frsqrt.s.yaml b/tests/MC/LoongArch/frsqrt.s.yaml
new file mode 100644
index 000000000..246b1dd5e
--- /dev/null
+++ b/tests/MC/LoongArch/frsqrt.s.yaml
@@ -0,0 +1,37 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x3f, 0x07, 0x9d, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvfrsqrt.s $xr31, $xr25"
+  -
+    input:
+      bytes: [ 0xce, 0x0a, 0x9d, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvfrsqrt.d $xr14, $xr22"
+  -
+    input:
+      bytes: [ 0x3f, 0x27, 0x9d, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvfrsqrte.s $xr31, $xr25"
+  -
+    input:
+      bytes: [ 0xce, 0x2a, 0x9d, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvfrsqrte.d $xr14, $xr22"
diff --git a/tests/MC/LoongArch/frstp.s.yaml b/tests/MC/LoongArch/frstp.s.yaml
new file mode 100644
index 000000000..5f9f31ca6
--- /dev/null
+++ b/tests/MC/LoongArch/frstp.s.yaml
@@ -0,0 +1,37 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x57, 0x4a, 0x2b, 0x75 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvfrstp.b $xr23, $xr18, $xr18"
+  -
+    input:
+      bytes: [ 0xcd, 0x9b, 0x2b, 0x75 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvfrstp.h $xr13, $xr30, $xr6"
+  -
+    input:
+      bytes: [ 0x98, 0x7f, 0x9a, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvfrstpi.b $xr24, $xr28, 0x1f"
+  -
+    input:
+      bytes: [ 0x16, 0xcb, 0x9a, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvfrstpi.h $xr22, $xr24, 0x12"
diff --git a/tests/MC/LoongArch/fsqrt.s.yaml b/tests/MC/LoongArch/fsqrt.s.yaml
new file mode 100644
index 000000000..5c21a00a5
--- /dev/null
+++ b/tests/MC/LoongArch/fsqrt.s.yaml
@@ -0,0 +1,19 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x64, 0xe7, 0x9c, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvfsqrt.s $xr4, $xr27"
+  -
+    input:
+      bytes: [ 0x5a, 0xe8, 0x9c, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvfsqrt.d $xr26, $xr2"
diff --git a/tests/MC/LoongArch/fsub.s.yaml b/tests/MC/LoongArch/fsub.s.yaml
new file mode 100644
index 000000000..7f8e3aef8
--- /dev/null
+++ b/tests/MC/LoongArch/fsub.s.yaml
@@ -0,0 +1,19 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x16, 0x8c, 0x32, 0x75 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvfsub.s $xr22, $xr0, $xr3"
+  -
+    input:
+      bytes: [ 0x24, 0x3f, 0x33, 0x75 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvfsub.d $xr4, $xr25, $xr15"
diff --git a/tests/MC/LoongArch/ftint.s.yaml b/tests/MC/LoongArch/ftint.s.yaml
new file mode 100644
index 000000000..7f8714ed8
--- /dev/null
+++ b/tests/MC/LoongArch/ftint.s.yaml
@@ -0,0 +1,262 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xb4, 0x51, 0x9e, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvftintrne.w.s $xr20, $xr13"
+  -
+    input:
+      bytes: [ 0xde, 0x55, 0x9e, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvftintrne.l.d $xr30, $xr14"
+  -
+    input:
+      bytes: [ 0xae, 0x48, 0x9e, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvftintrz.w.s $xr14, $xr5"
+  -
+    input:
+      bytes: [ 0x41, 0x4f, 0x9e, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvftintrz.l.d $xr1, $xr26"
+  -
+    input:
+      bytes: [ 0x32, 0x40, 0x9e, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvftintrp.w.s $xr18, $xr1"
+  -
+    input:
+      bytes: [ 0x0a, 0x47, 0x9e, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvftintrp.l.d $xr10, $xr24"
+  -
+    input:
+      bytes: [ 0xe8, 0x3a, 0x9e, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvftintrm.w.s $xr8, $xr23"
+  -
+    input:
+      bytes: [ 0x2c, 0x3e, 0x9e, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvftintrm.l.d $xr12, $xr17"
+  -
+    input:
+      bytes: [ 0x2b, 0x33, 0x9e, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvftint.w.s $xr11, $xr25"
+  -
+    input:
+      bytes: [ 0xc7, 0x36, 0x9e, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvftint.l.d $xr7, $xr22"
+  -
+    input:
+      bytes: [ 0x6d, 0x72, 0x9e, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvftintrz.wu.s $xr13, $xr19"
+  -
+    input:
+      bytes: [ 0x78, 0x74, 0x9e, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvftintrz.lu.d $xr24, $xr3"
+  -
+    input:
+      bytes: [ 0xce, 0x58, 0x9e, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvftint.wu.s $xr14, $xr6"
+  -
+    input:
+      bytes: [ 0x42, 0x5c, 0x9e, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvftint.lu.d $xr2, $xr2"
+  -
+    input:
+      bytes: [ 0x8d, 0x96, 0x4b, 0x75 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvftintrne.w.d $xr13, $xr20, $xr5"
+  -
+    input:
+      bytes: [ 0x0d, 0x6d, 0x4b, 0x75 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvftintrz.w.d $xr13, $xr8, $xr27"
+  -
+    input:
+      bytes: [ 0x4e, 0xff, 0x4a, 0x75 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvftintrp.w.d $xr14, $xr26, $xr31"
+  -
+    input:
+      bytes: [ 0xfd, 0x1e, 0x4a, 0x75 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvftintrm.w.d $xr29, $xr23, $xr7"
+  -
+    input:
+      bytes: [ 0xc7, 0xf6, 0x49, 0x75 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvftint.w.d $xr7, $xr22, $xr29"
+  -
+    input:
+      bytes: [ 0x9f, 0xa3, 0x9e, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvftintrnel.l.s $xr31, $xr28"
+  -
+    input:
+      bytes: [ 0xb0, 0xa7, 0x9e, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvftintrneh.l.s $xr16, $xr29"
+  -
+    input:
+      bytes: [ 0xbb, 0x9b, 0x9e, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvftintrzl.l.s $xr27, $xr29"
+  -
+    input:
+      bytes: [ 0x4e, 0x9d, 0x9e, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvftintrzh.l.s $xr14, $xr10"
+  -
+    input:
+      bytes: [ 0x0e, 0x90, 0x9e, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvftintrpl.l.s $xr14, $xr0"
+  -
+    input:
+      bytes: [ 0x17, 0x94, 0x9e, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvftintrph.l.s $xr23, $xr0"
+  -
+    input:
+      bytes: [ 0xf6, 0x89, 0x9e, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvftintrml.l.s $xr22, $xr15"
+  -
+    input:
+      bytes: [ 0x6a, 0x8e, 0x9e, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvftintrmh.l.s $xr10, $xr19"
+  -
+    input:
+      bytes: [ 0x7f, 0x81, 0x9e, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvftintl.l.s $xr31, $xr11"
+  -
+    input:
+      bytes: [ 0xaf, 0x84, 0x9e, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvftinth.l.s $xr15, $xr5"
diff --git a/tests/MC/LoongArch/haddw.s.yaml b/tests/MC/LoongArch/haddw.s.yaml
new file mode 100644
index 000000000..a039cf3ea
--- /dev/null
+++ b/tests/MC/LoongArch/haddw.s.yaml
@@ -0,0 +1,73 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x7f, 0x76, 0x54, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvhaddw.h.b $xr31, $xr19, $xr29"
+  -
+    input:
+      bytes: [ 0x1f, 0xde, 0x54, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvhaddw.w.h $xr31, $xr16, $xr23"
+  -
+    input:
+      bytes: [ 0x3e, 0x60, 0x55, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvhaddw.d.w $xr30, $xr1, $xr24"
+  -
+    input:
+      bytes: [ 0xf0, 0xc5, 0x55, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvhaddw.q.d $xr16, $xr15, $xr17"
+  -
+    input:
+      bytes: [ 0x2e, 0x0a, 0x58, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvhaddw.hu.bu $xr14, $xr17, $xr2"
+  -
+    input:
+      bytes: [ 0x55, 0xa0, 0x58, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvhaddw.wu.hu $xr21, $xr2, $xr8"
+  -
+    input:
+      bytes: [ 0x06, 0x4f, 0x59, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvhaddw.du.wu $xr6, $xr24, $xr19"
+  -
+    input:
+      bytes: [ 0x8a, 0xb5, 0x59, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvhaddw.qu.du $xr10, $xr12, $xr13"
diff --git a/tests/MC/LoongArch/hsubw.s.yaml b/tests/MC/LoongArch/hsubw.s.yaml
new file mode 100644
index 000000000..9cc827f3f
--- /dev/null
+++ b/tests/MC/LoongArch/hsubw.s.yaml
@@ -0,0 +1,73 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xf6, 0x40, 0x56, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvhsubw.h.b $xr22, $xr7, $xr16"
+  -
+    input:
+      bytes: [ 0x13, 0xbd, 0x56, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvhsubw.w.h $xr19, $xr8, $xr15"
+  -
+    input:
+      bytes: [ 0xfe, 0x4e, 0x57, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvhsubw.d.w $xr30, $xr23, $xr19"
+  -
+    input:
+      bytes: [ 0xb4, 0xf1, 0x57, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvhsubw.q.d $xr20, $xr13, $xr28"
+  -
+    input:
+      bytes: [ 0x4a, 0x40, 0x5a, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvhsubw.hu.bu $xr10, $xr2, $xr16"
+  -
+    input:
+      bytes: [ 0x41, 0xcb, 0x5a, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvhsubw.wu.hu $xr1, $xr26, $xr18"
+  -
+    input:
+      bytes: [ 0xe5, 0x52, 0x5b, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvhsubw.du.wu $xr5, $xr23, $xr20"
+  -
+    input:
+      bytes: [ 0x9f, 0xa0, 0x5b, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvhsubw.qu.du $xr31, $xr4, $xr8"
diff --git a/tests/MC/LoongArch/ilv.s.yaml b/tests/MC/LoongArch/ilv.s.yaml
new file mode 100644
index 000000000..efcdff01d
--- /dev/null
+++ b/tests/MC/LoongArch/ilv.s.yaml
@@ -0,0 +1,73 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xdd, 0x01, 0x1a, 0x75 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvilvl.b $xr29, $xr14, $xr0"
+  -
+    input:
+      bytes: [ 0x3e, 0xd5, 0x1a, 0x75 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvilvl.h $xr30, $xr9, $xr21"
+  -
+    input:
+      bytes: [ 0xd8, 0x26, 0x1b, 0x75 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvilvl.w $xr24, $xr22, $xr9"
+  -
+    input:
+      bytes: [ 0x99, 0xaa, 0x1b, 0x75 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvilvl.d $xr25, $xr20, $xr10"
+  -
+    input:
+      bytes: [ 0xd3, 0x6a, 0x1c, 0x75 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvilvh.b $xr19, $xr22, $xr26"
+  -
+    input:
+      bytes: [ 0xea, 0x9e, 0x1c, 0x75 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvilvh.h $xr10, $xr23, $xr7"
+  -
+    input:
+      bytes: [ 0x05, 0x78, 0x1d, 0x75 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvilvh.w $xr5, $xr0, $xr30"
+  -
+    input:
+      bytes: [ 0x58, 0x88, 0x1d, 0x75 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvilvh.d $xr24, $xr2, $xr2"
diff --git a/tests/MC/LoongArch/insgr2vr.s.yaml b/tests/MC/LoongArch/insgr2vr.s.yaml
new file mode 100644
index 000000000..ddbade5a0
--- /dev/null
+++ b/tests/MC/LoongArch/insgr2vr.s.yaml
@@ -0,0 +1,19 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xd9, 0xdf, 0xeb, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvinsgr2vr.w $xr25, $s7, 7"
+  -
+    input:
+      bytes: [ 0xbb, 0xe6, 0xeb, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvinsgr2vr.d $xr27, $r21, 1"
diff --git a/tests/MC/LoongArch/insve0.s.yaml b/tests/MC/LoongArch/insve0.s.yaml
new file mode 100644
index 000000000..3ae0564be
--- /dev/null
+++ b/tests/MC/LoongArch/insve0.s.yaml
@@ -0,0 +1,19 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x26, 0xdc, 0xff, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvinsve0.w $xr6, $xr1, 7"
+  -
+    input:
+      bytes: [ 0x3c, 0xe0, 0xff, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvinsve0.d $xr28, $xr1, 0"
diff --git a/tests/MC/LoongArch/ld.s.yaml b/tests/MC/LoongArch/ld.s.yaml
new file mode 100644
index 000000000..0d95912ab
--- /dev/null
+++ b/tests/MC/LoongArch/ld.s.yaml
@@ -0,0 +1,19 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x63, 0xb8, 0xb5, 0x2c ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvld $xr3, $sp, -0x292"
+  -
+    input:
+      bytes: [ 0x37, 0x39, 0x48, 0x38 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvldx $xr23, $a5, $t2"
diff --git a/tests/MC/LoongArch/ldrepl.s.yaml b/tests/MC/LoongArch/ldrepl.s.yaml
new file mode 100644
index 000000000..1fda52360
--- /dev/null
+++ b/tests/MC/LoongArch/ldrepl.s.yaml
@@ -0,0 +1,37 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xb3, 0x92, 0x9d, 0x32 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvldrepl.b $xr19, $r21, 0x764"
+  -
+    input:
+      bytes: [ 0x20, 0xc6, 0x4d, 0x32 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvldrepl.h $xr0, $t5, 0x6e2"
+  -
+    input:
+      bytes: [ 0x4b, 0x0f, 0x2a, 0x32 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvldrepl.w $xr11, $s3, -0x5f4"
+  -
+    input:
+      bytes: [ 0x9c, 0xdd, 0x13, 0x32 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvldrepl.d $xr28, $t0, 0x7b8"
diff --git a/tests/MC/LoongArch/lvz.s.yaml b/tests/MC/LoongArch/lvz.s.yaml
new file mode 100644
index 000000000..17aea1894
--- /dev/null
+++ b/tests/MC/LoongArch/lvz.s.yaml
@@ -0,0 +1,46 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x04, 0x04, 0x00, 0x05 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "gcsrrd $a0, 1"
+  -
+    input:
+      bytes: [ 0x24, 0x04, 0x00, 0x05 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "gcsrwr $a0, 1"
+  -
+    input:
+      bytes: [ 0xa4, 0x04, 0x00, 0x05 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "gcsrxchg $a0, $a1, 1"
+  -
+    input:
+      bytes: [ 0x01, 0x24, 0x48, 0x06 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "gtlbflush"
+  -
+    input:
+      bytes: [ 0x01, 0x80, 0x2b, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "hvcl 1"
diff --git a/tests/MC/LoongArch/madd.s.yaml b/tests/MC/LoongArch/madd.s.yaml
new file mode 100644
index 000000000..7e59ae43b
--- /dev/null
+++ b/tests/MC/LoongArch/madd.s.yaml
@@ -0,0 +1,37 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xe5, 0x23, 0xa8, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvmadd.b $xr5, $xr31, $xr8"
+  -
+    input:
+      bytes: [ 0x04, 0xf0, 0xa8, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvmadd.h $xr4, $xr0, $xr28"
+  -
+    input:
+      bytes: [ 0xa2, 0x61, 0xa9, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvmadd.w $xr2, $xr13, $xr24"
+  -
+    input:
+      bytes: [ 0x13, 0xc9, 0xa9, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvmadd.d $xr19, $xr8, $xr18"
diff --git a/tests/MC/LoongArch/maddw.s.yaml b/tests/MC/LoongArch/maddw.s.yaml
new file mode 100644
index 000000000..e3b1cbe9a
--- /dev/null
+++ b/tests/MC/LoongArch/maddw.s.yaml
@@ -0,0 +1,217 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xf9, 0x25, 0xac, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvmaddwev.h.b $xr25, $xr15, $xr9"
+  -
+    input:
+      bytes: [ 0x3a, 0x80, 0xac, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvmaddwev.w.h $xr26, $xr1, $xr0"
+  -
+    input:
+      bytes: [ 0x17, 0x63, 0xad, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvmaddwev.d.w $xr23, $xr24, $xr24"
+  -
+    input:
+      bytes: [ 0x27, 0xd9, 0xad, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvmaddwev.q.d $xr7, $xr9, $xr22"
+  -
+    input:
+      bytes: [ 0xb7, 0x69, 0xb4, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvmaddwev.h.bu $xr23, $xr13, $xr26"
+  -
+    input:
+      bytes: [ 0x6d, 0x8c, 0xb4, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvmaddwev.w.hu $xr13, $xr3, $xr3"
+  -
+    input:
+      bytes: [ 0x7d, 0x73, 0xb5, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvmaddwev.d.wu $xr29, $xr27, $xr28"
+  -
+    input:
+      bytes: [ 0x5d, 0xa9, 0xb5, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvmaddwev.q.du $xr29, $xr10, $xr10"
+  -
+    input:
+      bytes: [ 0x5e, 0x7f, 0xbc, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvmaddwev.h.bu.b $xr30, $xr26, $xr31"
+  -
+    input:
+      bytes: [ 0x26, 0xfe, 0xbc, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvmaddwev.w.hu.h $xr6, $xr17, $xr31"
+  -
+    input:
+      bytes: [ 0x8a, 0x0b, 0xbd, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvmaddwev.d.wu.w $xr10, $xr28, $xr2"
+  -
+    input:
+      bytes: [ 0x90, 0xe2, 0xbd, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvmaddwev.q.du.d $xr16, $xr20, $xr24"
+  -
+    input:
+      bytes: [ 0x10, 0x49, 0xae, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvmaddwod.h.b $xr16, $xr8, $xr18"
+  -
+    input:
+      bytes: [ 0x0b, 0xbb, 0xae, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvmaddwod.w.h $xr11, $xr24, $xr14"
+  -
+    input:
+      bytes: [ 0x80, 0x36, 0xaf, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvmaddwod.d.w $xr0, $xr20, $xr13"
+  -
+    input:
+      bytes: [ 0xef, 0xca, 0xaf, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvmaddwod.q.d $xr15, $xr23, $xr18"
+  -
+    input:
+      bytes: [ 0xff, 0x1e, 0xb6, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvmaddwod.h.bu $xr31, $xr23, $xr7"
+  -
+    input:
+      bytes: [ 0x1d, 0xa2, 0xb6, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvmaddwod.w.hu $xr29, $xr16, $xr8"
+  -
+    input:
+      bytes: [ 0x17, 0x2e, 0xb7, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvmaddwod.d.wu $xr23, $xr16, $xr11"
+  -
+    input:
+      bytes: [ 0x49, 0xcd, 0xb7, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvmaddwod.q.du $xr9, $xr10, $xr19"
+  -
+    input:
+      bytes: [ 0x5b, 0x2c, 0xbe, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvmaddwod.h.bu.b $xr27, $xr2, $xr11"
+  -
+    input:
+      bytes: [ 0x0c, 0xcf, 0xbe, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvmaddwod.w.hu.h $xr12, $xr24, $xr19"
+  -
+    input:
+      bytes: [ 0x0b, 0x38, 0xbf, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvmaddwod.d.wu.w $xr11, $xr0, $xr14"
+  -
+    input:
+      bytes: [ 0x7d, 0xfe, 0xbf, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvmaddwod.q.du.d $xr29, $xr19, $xr31"
diff --git a/tests/MC/LoongArch/max.s.yaml b/tests/MC/LoongArch/max.s.yaml
new file mode 100644
index 000000000..cfeef1a8d
--- /dev/null
+++ b/tests/MC/LoongArch/max.s.yaml
@@ -0,0 +1,145 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x17, 0x35, 0x70, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvmax.b $xr23, $xr8, $xr13"
+  -
+    input:
+      bytes: [ 0x4d, 0xf2, 0x70, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvmax.h $xr13, $xr18, $xr28"
+  -
+    input:
+      bytes: [ 0x3a, 0x08, 0x71, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvmax.w $xr26, $xr1, $xr2"
+  -
+    input:
+      bytes: [ 0x22, 0xb6, 0x71, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvmax.d $xr2, $xr17, $xr13"
+  -
+    input:
+      bytes: [ 0xe6, 0x04, 0x90, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvmaxi.b $xr6, $xr7, 1"
+  -
+    input:
+      bytes: [ 0x58, 0xe5, 0x90, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvmaxi.h $xr24, $xr10, -7"
+  -
+    input:
+      bytes: [ 0x58, 0x62, 0x91, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvmaxi.w $xr24, $xr18, -8"
+  -
+    input:
+      bytes: [ 0xb5, 0xd4, 0x91, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvmaxi.d $xr21, $xr5, -0xb"
+  -
+    input:
+      bytes: [ 0xdd, 0x2f, 0x74, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvmax.bu $xr29, $xr30, $xr11"
+  -
+    input:
+      bytes: [ 0xe4, 0xee, 0x74, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvmax.hu $xr4, $xr23, $xr27"
+  -
+    input:
+      bytes: [ 0x1f, 0x00, 0x75, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvmax.wu $xr31, $xr0, $xr0"
+  -
+    input:
+      bytes: [ 0xc5, 0xa6, 0x75, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvmax.du $xr5, $xr22, $xr9"
+  -
+    input:
+      bytes: [ 0x6c, 0x73, 0x94, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvmaxi.bu $xr12, $xr27, 0x1c"
+  -
+    input:
+      bytes: [ 0x99, 0xc0, 0x94, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvmaxi.hu $xr25, $xr4, 0x10"
+  -
+    input:
+      bytes: [ 0xfb, 0x54, 0x95, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvmaxi.wu $xr27, $xr7, 0x15"
+  -
+    input:
+      bytes: [ 0xbf, 0xa5, 0x95, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvmaxi.du $xr31, $xr13, 0x9"
diff --git a/tests/MC/LoongArch/memory.s.yaml b/tests/MC/LoongArch/memory.s.yaml
new file mode 100644
index 000000000..0b99c88e3
--- /dev/null
+++ b/tests/MC/LoongArch/memory.s.yaml
@@ -0,0 +1,82 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x18, 0x55, 0x00, 0x28 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.b $s1, $a4, 0x15"
+  -
+    input:
+      bytes: [ 0x47, 0x42, 0x41, 0x28 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.h $a3, $t6, 0x50"
+  -
+    input:
+      bytes: [ 0x52, 0x73, 0x81, 0x28 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w $t6, $s3, 0x5c"
+  -
+    input:
+      bytes: [ 0xad, 0x59, 0x02, 0x2a ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu $t1, $t1, 0x96"
+  -
+    input:
+      bytes: [ 0xb2, 0x1b, 0x43, 0x2a ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.hu $t6, $s6, 0xc6"
+  -
+    input:
+      bytes: [ 0xe3, 0x7c, 0x01, 0x29 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b $sp, $a3, 0x5f"
+  -
+    input:
+      bytes: [ 0x19, 0xea, 0x41, 0x29 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h $s2, $t4, 0x7a"
+  -
+    input:
+      bytes: [ 0xad, 0xbd, 0x82, 0x29 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w $t1, $t1, 0xaf"
+  -
+    input:
+      bytes: [ 0x0a, 0x5c, 0xc0, 0x2a ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "preld 0xa, $zero, 0x17"
diff --git a/tests/MC/LoongArch/min.s.yaml b/tests/MC/LoongArch/min.s.yaml
new file mode 100644
index 000000000..9a94cacb5
--- /dev/null
+++ b/tests/MC/LoongArch/min.s.yaml
@@ -0,0 +1,145 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x55, 0x1f, 0x72, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvmin.b $xr21, $xr26, $xr7"
+  -
+    input:
+      bytes: [ 0xbd, 0xa4, 0x72, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvmin.h $xr29, $xr5, $xr9"
+  -
+    input:
+      bytes: [ 0x1f, 0x53, 0x73, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvmin.w $xr31, $xr24, $xr20"
+  -
+    input:
+      bytes: [ 0x7b, 0x8b, 0x73, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvmin.d $xr27, $xr27, $xr2"
+  -
+    input:
+      bytes: [ 0x36, 0x26, 0x92, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvmini.b $xr22, $xr17, 0x9"
+  -
+    input:
+      bytes: [ 0xec, 0xc6, 0x92, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvmini.h $xr12, $xr23, -0xf"
+  -
+    input:
+      bytes: [ 0x21, 0x4e, 0x93, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvmini.w $xr1, $xr17, -0xd"
+  -
+    input:
+      bytes: [ 0xea, 0xaf, 0x93, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvmini.d $xr10, $xr31, 0xb"
+  -
+    input:
+      bytes: [ 0x0f, 0x0e, 0x76, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvmin.bu $xr15, $xr16, $xr3"
+  -
+    input:
+      bytes: [ 0xe4, 0xef, 0x76, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvmin.hu $xr4, $xr31, $xr27"
+  -
+    input:
+      bytes: [ 0xaf, 0x71, 0x77, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvmin.wu $xr15, $xr13, $xr28"
+  -
+    input:
+      bytes: [ 0x7b, 0x94, 0x77, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvmin.du $xr27, $xr3, $xr5"
+  -
+    input:
+      bytes: [ 0x06, 0x1f, 0x96, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvmini.bu $xr6, $xr24, 7"
+  -
+    input:
+      bytes: [ 0xa8, 0xf4, 0x96, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvmini.hu $xr8, $xr5, 0x1d"
+  -
+    input:
+      bytes: [ 0xb1, 0x4d, 0x97, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvmini.wu $xr17, $xr13, 0x13"
+  -
+    input:
+      bytes: [ 0xf0, 0xfa, 0x97, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvmini.du $xr16, $xr23, 0x1e"
diff --git a/tests/MC/LoongArch/misc.s.yaml b/tests/MC/LoongArch/misc.s.yaml
new file mode 100644
index 000000000..5e798ba9f
--- /dev/null
+++ b/tests/MC/LoongArch/misc.s.yaml
@@ -0,0 +1,46 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x64, 0x00, 0x2b, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "syscall 0x64"
+  -
+    input:
+      bytes: [ 0xc7, 0x00, 0x2a, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "break 0xc7"
+  -
+    input:
+      bytes: [ 0x98, 0x60, 0x00, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rdtimel.w $s1, $a0"
+  -
+    input:
+      bytes: [ 0xab, 0x64, 0x00, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rdtimeh.w $a7, $a1"
+  -
+    input:
+      bytes: [ 0x03, 0x6d, 0x00, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "cpucfg $sp, $a4"
diff --git a/tests/MC/LoongArch/mod.s.yaml b/tests/MC/LoongArch/mod.s.yaml
new file mode 100644
index 000000000..bd2910edc
--- /dev/null
+++ b/tests/MC/LoongArch/mod.s.yaml
@@ -0,0 +1,73 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x68, 0x00, 0xe2, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvmod.b $xr8, $xr3, $xr0"
+  -
+    input:
+      bytes: [ 0x22, 0xf2, 0xe2, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvmod.h $xr2, $xr17, $xr28"
+  -
+    input:
+      bytes: [ 0x0e, 0x35, 0xe3, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvmod.w $xr14, $xr8, $xr13"
+  -
+    input:
+      bytes: [ 0x4b, 0xc9, 0xe3, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvmod.d $xr11, $xr10, $xr18"
+  -
+    input:
+      bytes: [ 0x30, 0x68, 0xe6, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvmod.bu $xr16, $xr1, $xr26"
+  -
+    input:
+      bytes: [ 0xaf, 0x81, 0xe6, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvmod.hu $xr15, $xr13, $xr0"
+  -
+    input:
+      bytes: [ 0x6b, 0x52, 0xe7, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvmod.wu $xr11, $xr19, $xr20"
+  -
+    input:
+      bytes: [ 0x6e, 0x98, 0xe7, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvmod.du $xr14, $xr3, $xr6"
diff --git a/tests/MC/LoongArch/mskgez.s.yaml b/tests/MC/LoongArch/mskgez.s.yaml
new file mode 100644
index 000000000..4087103ef
--- /dev/null
+++ b/tests/MC/LoongArch/mskgez.s.yaml
@@ -0,0 +1,10 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xbe, 0x50, 0x9c, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvmskgez.b $xr30, $xr5"
diff --git a/tests/MC/LoongArch/mskltz.s.yaml b/tests/MC/LoongArch/mskltz.s.yaml
new file mode 100644
index 000000000..a171348ff
--- /dev/null
+++ b/tests/MC/LoongArch/mskltz.s.yaml
@@ -0,0 +1,37 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xae, 0x40, 0x9c, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvmskltz.b $xr14, $xr5"
+  -
+    input:
+      bytes: [ 0x2b, 0x47, 0x9c, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvmskltz.h $xr11, $xr25"
+  -
+    input:
+      bytes: [ 0x6e, 0x4b, 0x9c, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvmskltz.w $xr14, $xr27"
+  -
+    input:
+      bytes: [ 0xe7, 0x4e, 0x9c, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvmskltz.d $xr7, $xr23"
diff --git a/tests/MC/LoongArch/msknz.s.yaml b/tests/MC/LoongArch/msknz.s.yaml
new file mode 100644
index 000000000..c78cf3249
--- /dev/null
+++ b/tests/MC/LoongArch/msknz.s.yaml
@@ -0,0 +1,10 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xd6, 0x62, 0x9c, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvmsknz.b $xr22, $xr22"
diff --git a/tests/MC/LoongArch/msub.s.yaml b/tests/MC/LoongArch/msub.s.yaml
new file mode 100644
index 000000000..033691c37
--- /dev/null
+++ b/tests/MC/LoongArch/msub.s.yaml
@@ -0,0 +1,37 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x96, 0x1e, 0xaa, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvmsub.b $xr22, $xr20, $xr7"
+  -
+    input:
+      bytes: [ 0x40, 0xb2, 0xaa, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvmsub.h $xr0, $xr18, $xr12"
+  -
+    input:
+      bytes: [ 0xc3, 0x76, 0xab, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvmsub.w $xr3, $xr22, $xr29"
+  -
+    input:
+      bytes: [ 0x4b, 0x8b, 0xab, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvmsub.d $xr11, $xr26, $xr2"
diff --git a/tests/MC/LoongArch/muh.s.yaml b/tests/MC/LoongArch/muh.s.yaml
new file mode 100644
index 000000000..1393272de
--- /dev/null
+++ b/tests/MC/LoongArch/muh.s.yaml
@@ -0,0 +1,73 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x04, 0x11, 0x86, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvmuh.b $xr4, $xr8, $xr4"
+  -
+    input:
+      bytes: [ 0xe5, 0xea, 0x86, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvmuh.h $xr5, $xr23, $xr26"
+  -
+    input:
+      bytes: [ 0x7c, 0x64, 0x87, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvmuh.w $xr28, $xr3, $xr25"
+  -
+    input:
+      bytes: [ 0x06, 0xa4, 0x87, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvmuh.d $xr6, $xr0, $xr9"
+  -
+    input:
+      bytes: [ 0x8f, 0x62, 0x88, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvmuh.bu $xr15, $xr20, $xr24"
+  -
+    input:
+      bytes: [ 0x9c, 0xed, 0x88, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvmuh.hu $xr28, $xr12, $xr27"
+  -
+    input:
+      bytes: [ 0xd9, 0x28, 0x89, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvmuh.wu $xr25, $xr6, $xr10"
+  -
+    input:
+      bytes: [ 0x13, 0xfd, 0x89, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvmuh.du $xr19, $xr8, $xr31"
diff --git a/tests/MC/LoongArch/mul.s.yaml b/tests/MC/LoongArch/mul.s.yaml
new file mode 100644
index 000000000..03b0be434
--- /dev/null
+++ b/tests/MC/LoongArch/mul.s.yaml
@@ -0,0 +1,37 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xf2, 0x6c, 0x84, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvmul.b $xr18, $xr7, $xr27"
+  -
+    input:
+      bytes: [ 0xe9, 0xca, 0x84, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvmul.h $xr9, $xr23, $xr18"
+  -
+    input:
+      bytes: [ 0x15, 0x6d, 0x85, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvmul.w $xr21, $xr8, $xr27"
+  -
+    input:
+      bytes: [ 0xe0, 0xa1, 0x85, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvmul.d $xr0, $xr15, $xr8"
diff --git a/tests/MC/LoongArch/mulw.s.yaml b/tests/MC/LoongArch/mulw.s.yaml
new file mode 100644
index 000000000..95a32ade7
--- /dev/null
+++ b/tests/MC/LoongArch/mulw.s.yaml
@@ -0,0 +1,217 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xe2, 0x40, 0x90, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvmulwev.h.b $xr2, $xr7, $xr16"
+  -
+    input:
+      bytes: [ 0x6c, 0x99, 0x90, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvmulwev.w.h $xr12, $xr11, $xr6"
+  -
+    input:
+      bytes: [ 0x10, 0x3f, 0x91, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvmulwev.d.w $xr16, $xr24, $xr15"
+  -
+    input:
+      bytes: [ 0x11, 0x92, 0x91, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvmulwev.q.d $xr17, $xr16, $xr4"
+  -
+    input:
+      bytes: [ 0xf4, 0x74, 0x98, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvmulwev.h.bu $xr20, $xr7, $xr29"
+  -
+    input:
+      bytes: [ 0x0d, 0xc7, 0x98, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvmulwev.w.hu $xr13, $xr24, $xr17"
+  -
+    input:
+      bytes: [ 0x01, 0x7b, 0x99, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvmulwev.d.wu $xr1, $xr24, $xr30"
+  -
+    input:
+      bytes: [ 0xc1, 0xee, 0x99, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvmulwev.q.du $xr1, $xr22, $xr27"
+  -
+    input:
+      bytes: [ 0x8d, 0x33, 0xa0, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvmulwev.h.bu.b $xr13, $xr28, $xr12"
+  -
+    input:
+      bytes: [ 0x1b, 0x9e, 0xa0, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvmulwev.w.hu.h $xr27, $xr16, $xr7"
+  -
+    input:
+      bytes: [ 0xed, 0x44, 0xa1, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvmulwev.d.wu.w $xr13, $xr7, $xr17"
+  -
+    input:
+      bytes: [ 0x89, 0xbe, 0xa1, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvmulwev.q.du.d $xr9, $xr20, $xr15"
+  -
+    input:
+      bytes: [ 0x50, 0x0a, 0x92, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvmulwod.h.b $xr16, $xr18, $xr2"
+  -
+    input:
+      bytes: [ 0x5e, 0xdc, 0x92, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvmulwod.w.h $xr30, $xr2, $xr23"
+  -
+    input:
+      bytes: [ 0x7e, 0x23, 0x93, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvmulwod.d.w $xr30, $xr27, $xr8"
+  -
+    input:
+      bytes: [ 0xb4, 0xbe, 0x93, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvmulwod.q.d $xr20, $xr21, $xr15"
+  -
+    input:
+      bytes: [ 0x53, 0x1f, 0x9a, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvmulwod.h.bu $xr19, $xr26, $xr7"
+  -
+    input:
+      bytes: [ 0x2e, 0x9a, 0x9a, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvmulwod.w.hu $xr14, $xr17, $xr6"
+  -
+    input:
+      bytes: [ 0xd8, 0x52, 0x9b, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvmulwod.d.wu $xr24, $xr22, $xr20"
+  -
+    input:
+      bytes: [ 0xfc, 0x9f, 0x9b, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvmulwod.q.du $xr28, $xr31, $xr7"
+  -
+    input:
+      bytes: [ 0xf8, 0x71, 0xa2, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvmulwod.h.bu.b $xr24, $xr15, $xr28"
+  -
+    input:
+      bytes: [ 0x18, 0x85, 0xa2, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvmulwod.w.hu.h $xr24, $xr8, $xr1"
+  -
+    input:
+      bytes: [ 0x6a, 0x04, 0xa3, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvmulwod.d.wu.w $xr10, $xr3, $xr1"
+  -
+    input:
+      bytes: [ 0xef, 0x89, 0xa3, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvmulwod.q.du.d $xr15, $xr15, $xr2"
diff --git a/tests/MC/LoongArch/neg.s.yaml b/tests/MC/LoongArch/neg.s.yaml
new file mode 100644
index 000000000..caa0fc59e
--- /dev/null
+++ b/tests/MC/LoongArch/neg.s.yaml
@@ -0,0 +1,37 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x97, 0x30, 0x9c, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvneg.b $xr23, $xr4"
+  -
+    input:
+      bytes: [ 0xc8, 0x35, 0x9c, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvneg.h $xr8, $xr14"
+  -
+    input:
+      bytes: [ 0xd7, 0x39, 0x9c, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvneg.w $xr23, $xr14"
+  -
+    input:
+      bytes: [ 0x34, 0x3e, 0x9c, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvneg.d $xr20, $xr17"
diff --git a/tests/MC/LoongArch/nor.s.yaml b/tests/MC/LoongArch/nor.s.yaml
new file mode 100644
index 000000000..243c22b1c
--- /dev/null
+++ b/tests/MC/LoongArch/nor.s.yaml
@@ -0,0 +1,10 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xe4, 0x8e, 0x27, 0x75 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvnor.v $xr4, $xr23, $xr3"
diff --git a/tests/MC/LoongArch/nori.s.yaml b/tests/MC/LoongArch/nori.s.yaml
new file mode 100644
index 000000000..0db9dbd66
--- /dev/null
+++ b/tests/MC/LoongArch/nori.s.yaml
@@ -0,0 +1,10 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x27, 0x44, 0xdf, 0x77 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvnori.b $xr7, $xr1, 0xd1"
diff --git a/tests/MC/LoongArch/or.s.yaml b/tests/MC/LoongArch/or.s.yaml
new file mode 100644
index 000000000..8b3648c28
--- /dev/null
+++ b/tests/MC/LoongArch/or.s.yaml
@@ -0,0 +1,10 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xa6, 0xd7, 0x26, 0x75 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvor.v $xr6, $xr29, $xr21"
diff --git a/tests/MC/LoongArch/ori.s.yaml b/tests/MC/LoongArch/ori.s.yaml
new file mode 100644
index 000000000..e4cb31449
--- /dev/null
+++ b/tests/MC/LoongArch/ori.s.yaml
@@ -0,0 +1,10 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x46, 0xbc, 0xd7, 0x77 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvori.b $xr6, $xr2, 0xef"
diff --git a/tests/MC/LoongArch/orn.s.yaml b/tests/MC/LoongArch/orn.s.yaml
new file mode 100644
index 000000000..b8a527a03
--- /dev/null
+++ b/tests/MC/LoongArch/orn.s.yaml
@@ -0,0 +1,10 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xb1, 0x97, 0x28, 0x75 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvorn.v $xr17, $xr29, $xr5"
diff --git a/tests/MC/LoongArch/pack.s.yaml b/tests/MC/LoongArch/pack.s.yaml
new file mode 100644
index 000000000..1eb169704
--- /dev/null
+++ b/tests/MC/LoongArch/pack.s.yaml
@@ -0,0 +1,73 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x55, 0x20, 0x16, 0x75 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvpackev.b $xr21, $xr2, $xr8"
+  -
+    input:
+      bytes: [ 0x48, 0x9a, 0x16, 0x75 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvpackev.h $xr8, $xr18, $xr6"
+  -
+    input:
+      bytes: [ 0xc0, 0x78, 0x17, 0x75 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvpackev.w $xr0, $xr6, $xr30"
+  -
+    input:
+      bytes: [ 0x20, 0x91, 0x17, 0x75 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvpackev.d $xr0, $xr9, $xr4"
+  -
+    input:
+      bytes: [ 0xbc, 0x7f, 0x18, 0x75 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvpackod.b $xr28, $xr29, $xr31"
+  -
+    input:
+      bytes: [ 0x4e, 0x99, 0x18, 0x75 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvpackod.h $xr14, $xr10, $xr6"
+  -
+    input:
+      bytes: [ 0xb6, 0x0a, 0x19, 0x75 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvpackod.w $xr22, $xr21, $xr2"
+  -
+    input:
+      bytes: [ 0x32, 0x89, 0x19, 0x75 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvpackod.d $xr18, $xr9, $xr2"
diff --git a/tests/MC/LoongArch/pcnt.s.yaml b/tests/MC/LoongArch/pcnt.s.yaml
new file mode 100644
index 000000000..b2cb8e77e
--- /dev/null
+++ b/tests/MC/LoongArch/pcnt.s.yaml
@@ -0,0 +1,37 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x68, 0x23, 0x9c, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvpcnt.b $xr8, $xr27"
+  -
+    input:
+      bytes: [ 0x8c, 0x24, 0x9c, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvpcnt.h $xr12, $xr4"
+  -
+    input:
+      bytes: [ 0xff, 0x2a, 0x9c, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvpcnt.w $xr31, $xr23"
+  -
+    input:
+      bytes: [ 0x9a, 0x2d, 0x9c, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvpcnt.d $xr26, $xr12"
diff --git a/tests/MC/LoongArch/perm.s.yaml b/tests/MC/LoongArch/perm.s.yaml
new file mode 100644
index 000000000..d5c8f3a59
--- /dev/null
+++ b/tests/MC/LoongArch/perm.s.yaml
@@ -0,0 +1,10 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xf8, 0x42, 0x7d, 0x75 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvperm.w $xr24, $xr23, $xr16"
diff --git a/tests/MC/LoongArch/permi.s.yaml b/tests/MC/LoongArch/permi.s.yaml
new file mode 100644
index 000000000..ee04cf480
--- /dev/null
+++ b/tests/MC/LoongArch/permi.s.yaml
@@ -0,0 +1,28 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x87, 0x95, 0xe5, 0x77 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvpermi.w $xr7, $xr12, 0x65"
+  -
+    input:
+      bytes: [ 0xd1, 0x0c, 0xea, 0x77 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvpermi.d $xr17, $xr6, 0x83"
+  -
+    input:
+      bytes: [ 0xea, 0xe1, 0xee, 0x77 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvpermi.q $xr10, $xr15, 0xb8"
diff --git a/tests/MC/LoongArch/pick.s.yaml b/tests/MC/LoongArch/pick.s.yaml
new file mode 100644
index 000000000..3edb7d2ca
--- /dev/null
+++ b/tests/MC/LoongArch/pick.s.yaml
@@ -0,0 +1,73 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x76, 0x1b, 0x1e, 0x75 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvpickev.b $xr22, $xr27, $xr6"
+  -
+    input:
+      bytes: [ 0x6e, 0x8d, 0x1e, 0x75 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvpickev.h $xr14, $xr11, $xr3"
+  -
+    input:
+      bytes: [ 0x9e, 0x37, 0x1f, 0x75 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvpickev.w $xr30, $xr28, $xr13"
+  -
+    input:
+      bytes: [ 0x01, 0xa7, 0x1f, 0x75 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvpickev.d $xr1, $xr24, $xr9"
+  -
+    input:
+      bytes: [ 0xce, 0x3e, 0x20, 0x75 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvpickod.b $xr14, $xr22, $xr15"
+  -
+    input:
+      bytes: [ 0xbf, 0xb2, 0x20, 0x75 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvpickod.h $xr31, $xr21, $xr12"
+  -
+    input:
+      bytes: [ 0x1f, 0x78, 0x21, 0x75 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvpickod.w $xr31, $xr0, $xr30"
+  -
+    input:
+      bytes: [ 0xaa, 0xc0, 0x21, 0x75 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvpickod.d $xr10, $xr5, $xr16"
diff --git a/tests/MC/LoongArch/pickve.s.yaml b/tests/MC/LoongArch/pickve.s.yaml
new file mode 100644
index 000000000..2d538fcb1
--- /dev/null
+++ b/tests/MC/LoongArch/pickve.s.yaml
@@ -0,0 +1,19 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x99, 0xc7, 0x03, 0x77 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvpickve.w $xr25, $xr28, 1"
+  -
+    input:
+      bytes: [ 0x2d, 0xe0, 0x03, 0x77 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvpickve.d $xr13, $xr1, 0"
diff --git a/tests/MC/LoongArch/pickve2gr.s.yaml b/tests/MC/LoongArch/pickve2gr.s.yaml
new file mode 100644
index 000000000..f12c084ea
--- /dev/null
+++ b/tests/MC/LoongArch/pickve2gr.s.yaml
@@ -0,0 +1,37 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x6e, 0xd9, 0xef, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvpickve2gr.w $t2, $xr11, 6"
+  -
+    input:
+      bytes: [ 0xc8, 0xe0, 0xef, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvpickve2gr.d $a4, $xr6, 0"
+  -
+    input:
+      bytes: [ 0x2c, 0xd0, 0xf3, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvpickve2gr.wu $t0, $xr1, 4"
+  -
+    input:
+      bytes: [ 0x0a, 0xe1, 0xf3, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvpickve2gr.du $a6, $xr8, 0"
diff --git a/tests/MC/LoongArch/pseudos.s.yaml b/tests/MC/LoongArch/pseudos.s.yaml
new file mode 100644
index 000000000..ddfba2728
--- /dev/null
+++ b/tests/MC/LoongArch/pseudos.s.yaml
@@ -0,0 +1,19 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x40, 0x03 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "nop"
+  -
+    input:
+      bytes: [ 0x28, 0x01, 0x15, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "move $a4, $a5"
diff --git a/tests/MC/LoongArch/repl128vei.s.yaml b/tests/MC/LoongArch/repl128vei.s.yaml
new file mode 100644
index 000000000..ded5f1c29
--- /dev/null
+++ b/tests/MC/LoongArch/repl128vei.s.yaml
@@ -0,0 +1,37 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x6a, 0x8a, 0xf7, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvrepl128vei.b $xr10, $xr19, 2"
+  -
+    input:
+      bytes: [ 0x66, 0xca, 0xf7, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvrepl128vei.h $xr6, $xr19, 2"
+  -
+    input:
+      bytes: [ 0xab, 0xe5, 0xf7, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvrepl128vei.w $xr11, $xr13, 1"
+  -
+    input:
+      bytes: [ 0xff, 0xf2, 0xf7, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvrepl128vei.d $xr31, $xr23, 0"
diff --git a/tests/MC/LoongArch/replgr2vr.s.yaml b/tests/MC/LoongArch/replgr2vr.s.yaml
new file mode 100644
index 000000000..9b5ca41c7
--- /dev/null
+++ b/tests/MC/LoongArch/replgr2vr.s.yaml
@@ -0,0 +1,37 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x10, 0x02, 0x9f, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvreplgr2vr.b $xr16, $t4"
+  -
+    input:
+      bytes: [ 0xc7, 0x06, 0x9f, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvreplgr2vr.h $xr7, $fp"
+  -
+    input:
+      bytes: [ 0xe4, 0x09, 0x9f, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvreplgr2vr.w $xr4, $t3"
+  -
+    input:
+      bytes: [ 0x10, 0x0f, 0x9f, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvreplgr2vr.d $xr16, $s1"
diff --git a/tests/MC/LoongArch/replve.s.yaml b/tests/MC/LoongArch/replve.s.yaml
new file mode 100644
index 000000000..501c2a2b7
--- /dev/null
+++ b/tests/MC/LoongArch/replve.s.yaml
@@ -0,0 +1,37 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x14, 0x2e, 0x22, 0x75 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvreplve.b $xr20, $xr16, $a7"
+  -
+    input:
+      bytes: [ 0xa0, 0xe2, 0x22, 0x75 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvreplve.h $xr0, $xr21, $s1"
+  -
+    input:
+      bytes: [ 0x54, 0x4a, 0x23, 0x75 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvreplve.w $xr20, $xr18, $t6"
+  -
+    input:
+      bytes: [ 0x64, 0xdc, 0x23, 0x75 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvreplve.d $xr4, $xr3, $s0"
diff --git a/tests/MC/LoongArch/replve0.s.yaml b/tests/MC/LoongArch/replve0.s.yaml
new file mode 100644
index 000000000..fa826a235
--- /dev/null
+++ b/tests/MC/LoongArch/replve0.s.yaml
@@ -0,0 +1,46 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x8b, 0x02, 0x07, 0x77 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvreplve0.b $xr11, $xr20"
+  -
+    input:
+      bytes: [ 0x4d, 0x83, 0x07, 0x77 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvreplve0.h $xr13, $xr26"
+  -
+    input:
+      bytes: [ 0x88, 0xc1, 0x07, 0x77 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvreplve0.w $xr8, $xr12"
+  -
+    input:
+      bytes: [ 0x94, 0xe0, 0x07, 0x77 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvreplve0.d $xr20, $xr4"
+  -
+    input:
+      bytes: [ 0x91, 0xf2, 0x07, 0x77 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvreplve0.q $xr17, $xr20"
diff --git a/tests/MC/LoongArch/replvei.s.yaml b/tests/MC/LoongArch/replvei.s.yaml
new file mode 100644
index 000000000..f39904fab
--- /dev/null
+++ b/tests/MC/LoongArch/replvei.s.yaml
@@ -0,0 +1,37 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x77, 0x8c, 0xf7, 0x72 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vreplvei.b $vr23, $vr3, 3"
+  -
+    input:
+      bytes: [ 0x1b, 0xc2, 0xf7, 0x72 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vreplvei.h $vr27, $vr16, 0"
+  -
+    input:
+      bytes: [ 0xf2, 0xee, 0xf7, 0x72 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vreplvei.w $vr18, $vr23, 3"
+  -
+    input:
+      bytes: [ 0x8f, 0xf5, 0xf7, 0x72 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vreplvei.d $vr15, $vr12, 1"
diff --git a/tests/MC/LoongArch/rotr.s.yaml b/tests/MC/LoongArch/rotr.s.yaml
new file mode 100644
index 000000000..00dd20aa7
--- /dev/null
+++ b/tests/MC/LoongArch/rotr.s.yaml
@@ -0,0 +1,73 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xc0, 0x78, 0xee, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvrotr.b $xr0, $xr6, $xr30"
+  -
+    input:
+      bytes: [ 0x33, 0xaa, 0xee, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvrotr.h $xr19, $xr17, $xr10"
+  -
+    input:
+      bytes: [ 0x52, 0x1c, 0xef, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvrotr.w $xr18, $xr2, $xr7"
+  -
+    input:
+      bytes: [ 0xeb, 0xae, 0xef, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvrotr.d $xr11, $xr23, $xr11"
+  -
+    input:
+      bytes: [ 0xa1, 0x2c, 0xa0, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvrotri.b $xr1, $xr5, 3"
+  -
+    input:
+      bytes: [ 0x21, 0x4e, 0xa0, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvrotri.h $xr1, $xr17, 3"
+  -
+    input:
+      bytes: [ 0xf9, 0xce, 0xa0, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvrotri.w $xr25, $xr23, 0x13"
+  -
+    input:
+      bytes: [ 0x07, 0x97, 0xa1, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvrotri.d $xr7, $xr24, 0x25"
diff --git a/tests/MC/LoongArch/sadd.s.yaml b/tests/MC/LoongArch/sadd.s.yaml
new file mode 100644
index 000000000..bf6d0457a
--- /dev/null
+++ b/tests/MC/LoongArch/sadd.s.yaml
@@ -0,0 +1,73 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xdb, 0x5b, 0x46, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsadd.b $xr27, $xr30, $xr22"
+  -
+    input:
+      bytes: [ 0x1d, 0x84, 0x46, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsadd.h $xr29, $xr0, $xr1"
+  -
+    input:
+      bytes: [ 0x96, 0x7f, 0x47, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsadd.w $xr22, $xr28, $xr31"
+  -
+    input:
+      bytes: [ 0x45, 0xea, 0x47, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsadd.d $xr5, $xr18, $xr26"
+  -
+    input:
+      bytes: [ 0x9d, 0x72, 0x4a, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsadd.bu $xr29, $xr20, $xr28"
+  -
+    input:
+      bytes: [ 0x07, 0x9a, 0x4a, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsadd.hu $xr7, $xr16, $xr6"
+  -
+    input:
+      bytes: [ 0x42, 0x3d, 0x4b, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsadd.wu $xr2, $xr10, $xr15"
+  -
+    input:
+      bytes: [ 0x12, 0xbb, 0x4b, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsadd.du $xr18, $xr24, $xr14"
diff --git a/tests/MC/LoongArch/sat.s.yaml b/tests/MC/LoongArch/sat.s.yaml
new file mode 100644
index 000000000..ec1826df8
--- /dev/null
+++ b/tests/MC/LoongArch/sat.s.yaml
@@ -0,0 +1,73 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xf6, 0x28, 0x24, 0x77 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsat.b $xr22, $xr7, 2"
+  -
+    input:
+      bytes: [ 0x03, 0x54, 0x24, 0x77 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsat.h $xr3, $xr0, 5"
+  -
+    input:
+      bytes: [ 0x09, 0x82, 0x24, 0x77 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsat.w $xr9, $xr16, 0"
+  -
+    input:
+      bytes: [ 0x03, 0x05, 0x25, 0x77 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsat.d $xr3, $xr8, 1"
+  -
+    input:
+      bytes: [ 0xc6, 0x30, 0x28, 0x77 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsat.bu $xr6, $xr6, 4"
+  -
+    input:
+      bytes: [ 0x2c, 0x73, 0x28, 0x77 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsat.hu $xr12, $xr25, 0xc"
+  -
+    input:
+      bytes: [ 0x34, 0x8c, 0x28, 0x77 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsat.wu $xr20, $xr1, 3"
+  -
+    input:
+      bytes: [ 0x85, 0x1e, 0x29, 0x77 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsat.du $xr5, $xr20, 7"
diff --git a/tests/MC/LoongArch/scr.s.yaml b/tests/MC/LoongArch/scr.s.yaml
new file mode 100644
index 000000000..6ed0db59f
--- /dev/null
+++ b/tests/MC/LoongArch/scr.s.yaml
@@ -0,0 +1,37 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xa0, 0x08, 0x00, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "movgr2scr $scr0, $a1"
+  -
+    input:
+      bytes: [ 0x24, 0x0c, 0x00, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "movscr2gr $a0, $scr1"
+  -
+    input:
+      bytes: [ 0x00, 0x66, 0x00, 0x48 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "jiscr0 0x64"
+  -
+    input:
+      bytes: [ 0x00, 0x67, 0x00, 0x48 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "jiscr1 0x64"
diff --git a/tests/MC/LoongArch/seq.s.yaml b/tests/MC/LoongArch/seq.s.yaml
new file mode 100644
index 000000000..a947109ac
--- /dev/null
+++ b/tests/MC/LoongArch/seq.s.yaml
@@ -0,0 +1,73 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x83, 0x4c, 0x00, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvseq.b $xr3, $xr4, $xr19"
+  -
+    input:
+      bytes: [ 0xa0, 0x96, 0x00, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvseq.h $xr0, $xr21, $xr5"
+  -
+    input:
+      bytes: [ 0x06, 0x4e, 0x01, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvseq.w $xr6, $xr16, $xr19"
+  -
+    input:
+      bytes: [ 0xa8, 0xb5, 0x01, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvseq.d $xr8, $xr13, $xr13"
+  -
+    input:
+      bytes: [ 0x2c, 0x03, 0x80, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvseqi.b $xr12, $xr25, 0"
+  -
+    input:
+      bytes: [ 0x89, 0xa8, 0x80, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvseqi.h $xr9, $xr4, 0xa"
+  -
+    input:
+      bytes: [ 0x99, 0x50, 0x81, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvseqi.w $xr25, $xr4, -0xc"
+  -
+    input:
+      bytes: [ 0xeb, 0x9c, 0x81, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvseqi.d $xr11, $xr7, 7"
diff --git a/tests/MC/LoongArch/set.s.yaml b/tests/MC/LoongArch/set.s.yaml
new file mode 100644
index 000000000..9346ffbc6
--- /dev/null
+++ b/tests/MC/LoongArch/set.s.yaml
@@ -0,0 +1,19 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x27, 0x98, 0x9c, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvseteqz.v $fcc7, $xr1"
+  -
+    input:
+      bytes: [ 0xa7, 0x9d, 0x9c, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsetnez.v $fcc7, $xr13"
diff --git a/tests/MC/LoongArch/setallnez.s.yaml b/tests/MC/LoongArch/setallnez.s.yaml
new file mode 100644
index 000000000..c90655bd4
--- /dev/null
+++ b/tests/MC/LoongArch/setallnez.s.yaml
@@ -0,0 +1,37 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xa5, 0xb3, 0x9c, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsetallnez.b $fcc5, $xr29"
+  -
+    input:
+      bytes: [ 0x85, 0xb4, 0x9c, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsetallnez.h $fcc5, $xr4"
+  -
+    input:
+      bytes: [ 0xa4, 0xb8, 0x9c, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsetallnez.w $fcc4, $xr5"
+  -
+    input:
+      bytes: [ 0x87, 0xbe, 0x9c, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsetallnez.d $fcc7, $xr20"
diff --git a/tests/MC/LoongArch/setanyeqz.s.yaml b/tests/MC/LoongArch/setanyeqz.s.yaml
new file mode 100644
index 000000000..fbd7656ff
--- /dev/null
+++ b/tests/MC/LoongArch/setanyeqz.s.yaml
@@ -0,0 +1,37 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x05, 0xa1, 0x9c, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsetanyeqz.b $fcc5, $xr8"
+  -
+    input:
+      bytes: [ 0x85, 0xa6, 0x9c, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsetanyeqz.h $fcc5, $xr20"
+  -
+    input:
+      bytes: [ 0xc7, 0xa8, 0x9c, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsetanyeqz.w $fcc7, $xr6"
+  -
+    input:
+      bytes: [ 0x26, 0xae, 0x9c, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsetanyeqz.d $fcc6, $xr17"
diff --git a/tests/MC/LoongArch/shuf.s.yaml b/tests/MC/LoongArch/shuf.s.yaml
new file mode 100644
index 000000000..2d77d9bd4
--- /dev/null
+++ b/tests/MC/LoongArch/shuf.s.yaml
@@ -0,0 +1,37 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xd4, 0xac, 0x67, 0x0d ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvshuf.b $xr20, $xr6, $xr11, $xr15"
+  -
+    input:
+      bytes: [ 0x1d, 0x87, 0x7a, 0x75 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvshuf.h $xr29, $xr24, $xr1"
+  -
+    input:
+      bytes: [ 0x0f, 0x77, 0x7b, 0x75 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvshuf.w $xr15, $xr24, $xr29"
+  -
+    input:
+      bytes: [ 0x5b, 0xbe, 0x7b, 0x75 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvshuf.d $xr27, $xr18, $xr15"
diff --git a/tests/MC/LoongArch/shuf4i.s.yaml b/tests/MC/LoongArch/shuf4i.s.yaml
new file mode 100644
index 000000000..f8ede46e4
--- /dev/null
+++ b/tests/MC/LoongArch/shuf4i.s.yaml
@@ -0,0 +1,37 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x95, 0xa3, 0x92, 0x77 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvshuf4i.b $xr21, $xr28, 0xa8"
+  -
+    input:
+      bytes: [ 0x72, 0x58, 0x94, 0x77 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvshuf4i.h $xr18, $xr3, 0x16"
+  -
+    input:
+      bytes: [ 0x20, 0x4b, 0x99, 0x77 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvshuf4i.w $xr0, $xr25, 0x52"
+  -
+    input:
+      bytes: [ 0x98, 0x8c, 0x9d, 0x77 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvshuf4i.d $xr24, $xr4, 0x63"
diff --git a/tests/MC/LoongArch/signcov.s.yaml b/tests/MC/LoongArch/signcov.s.yaml
new file mode 100644
index 000000000..61568091e
--- /dev/null
+++ b/tests/MC/LoongArch/signcov.s.yaml
@@ -0,0 +1,37 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x01, 0x37, 0x2e, 0x75 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsigncov.b $xr1, $xr24, $xr13"
+  -
+    input:
+      bytes: [ 0xe8, 0xba, 0x2e, 0x75 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsigncov.h $xr8, $xr23, $xr14"
+  -
+    input:
+      bytes: [ 0x23, 0x2b, 0x2f, 0x75 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsigncov.w $xr3, $xr25, $xr10"
+  -
+    input:
+      bytes: [ 0x3a, 0xfe, 0x2f, 0x75 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsigncov.d $xr26, $xr17, $xr31"
diff --git a/tests/MC/LoongArch/sle.s.yaml b/tests/MC/LoongArch/sle.s.yaml
new file mode 100644
index 000000000..3de94835b
--- /dev/null
+++ b/tests/MC/LoongArch/sle.s.yaml
@@ -0,0 +1,145 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xd8, 0x77, 0x02, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsle.b $xr24, $xr30, $xr29"
+  -
+    input:
+      bytes: [ 0xb7, 0xd1, 0x02, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsle.h $xr23, $xr13, $xr20"
+  -
+    input:
+      bytes: [ 0xea, 0x63, 0x03, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsle.w $xr10, $xr31, $xr24"
+  -
+    input:
+      bytes: [ 0x4d, 0xa3, 0x03, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsle.d $xr13, $xr26, $xr8"
+  -
+    input:
+      bytes: [ 0x6e, 0x59, 0x82, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvslei.b $xr14, $xr11, -0xa"
+  -
+    input:
+      bytes: [ 0xc2, 0xbe, 0x82, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvslei.h $xr2, $xr22, 0xf"
+  -
+    input:
+      bytes: [ 0xc3, 0x31, 0x83, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvslei.w $xr3, $xr14, 0xc"
+  -
+    input:
+      bytes: [ 0xd3, 0xab, 0x83, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvslei.d $xr19, $xr30, 0xa"
+  -
+    input:
+      bytes: [ 0x69, 0x0b, 0x04, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsle.bu $xr9, $xr27, $xr2"
+  -
+    input:
+      bytes: [ 0x3d, 0xdb, 0x04, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsle.hu $xr29, $xr25, $xr22"
+  -
+    input:
+      bytes: [ 0x30, 0x3b, 0x05, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsle.wu $xr16, $xr25, $xr14"
+  -
+    input:
+      bytes: [ 0xc5, 0xc8, 0x05, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsle.du $xr5, $xr6, $xr18"
+  -
+    input:
+      bytes: [ 0x51, 0x2b, 0x84, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvslei.bu $xr17, $xr26, 0xa"
+  -
+    input:
+      bytes: [ 0x74, 0xc9, 0x84, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvslei.hu $xr20, $xr11, 0x12"
+  -
+    input:
+      bytes: [ 0xa1, 0x2b, 0x85, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvslei.wu $xr1, $xr29, 0xa"
+  -
+    input:
+      bytes: [ 0xf9, 0xe3, 0x85, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvslei.du $xr25, $xr31, 0x18"
diff --git a/tests/MC/LoongArch/sll.s.yaml b/tests/MC/LoongArch/sll.s.yaml
new file mode 100644
index 000000000..da6231665
--- /dev/null
+++ b/tests/MC/LoongArch/sll.s.yaml
@@ -0,0 +1,73 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xa8, 0x27, 0xe8, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsll.b $xr8, $xr29, $xr9"
+  -
+    input:
+      bytes: [ 0x95, 0xf7, 0xe8, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsll.h $xr21, $xr28, $xr29"
+  -
+    input:
+      bytes: [ 0xd1, 0x2b, 0xe9, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsll.w $xr17, $xr30, $xr10"
+  -
+    input:
+      bytes: [ 0xd3, 0xe8, 0xe9, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsll.d $xr19, $xr6, $xr26"
+  -
+    input:
+      bytes: [ 0x59, 0x27, 0x2c, 0x77 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvslli.b $xr25, $xr26, 1"
+  -
+    input:
+      bytes: [ 0x91, 0x7b, 0x2c, 0x77 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvslli.h $xr17, $xr28, 0xe"
+  -
+    input:
+      bytes: [ 0xfa, 0xf7, 0x2c, 0x77 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvslli.w $xr26, $xr31, 0x1d"
+  -
+    input:
+      bytes: [ 0x8a, 0xbb, 0x2d, 0x77 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvslli.d $xr10, $xr28, 0x2e"
diff --git a/tests/MC/LoongArch/sllwil.s.yaml b/tests/MC/LoongArch/sllwil.s.yaml
new file mode 100644
index 000000000..168587bac
--- /dev/null
+++ b/tests/MC/LoongArch/sllwil.s.yaml
@@ -0,0 +1,55 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xad, 0x3a, 0x08, 0x77 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsllwil.h.b $xr13, $xr21, 6"
+  -
+    input:
+      bytes: [ 0xb4, 0x43, 0x08, 0x77 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsllwil.w.h $xr20, $xr29, 0"
+  -
+    input:
+      bytes: [ 0x83, 0xe2, 0x08, 0x77 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsllwil.d.w $xr3, $xr20, 0x18"
+  -
+    input:
+      bytes: [ 0xef, 0x39, 0x0c, 0x77 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsllwil.hu.bu $xr15, $xr15, 6"
+  -
+    input:
+      bytes: [ 0xb6, 0x43, 0x0c, 0x77 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsllwil.wu.hu $xr22, $xr29, 0"
+  -
+    input:
+      bytes: [ 0xa3, 0xfc, 0x0c, 0x77 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsllwil.du.wu $xr3, $xr5, 0x1f"
diff --git a/tests/MC/LoongArch/slt.s.yaml b/tests/MC/LoongArch/slt.s.yaml
new file mode 100644
index 000000000..4f173ee3c
--- /dev/null
+++ b/tests/MC/LoongArch/slt.s.yaml
@@ -0,0 +1,145 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xfe, 0x37, 0x06, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvslt.b $xr30, $xr31, $xr13"
+  -
+    input:
+      bytes: [ 0xf3, 0x82, 0x06, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvslt.h $xr19, $xr23, $xr0"
+  -
+    input:
+      bytes: [ 0x57, 0x0f, 0x07, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvslt.w $xr23, $xr26, $xr3"
+  -
+    input:
+      bytes: [ 0x43, 0xfd, 0x07, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvslt.d $xr3, $xr10, $xr31"
+  -
+    input:
+      bytes: [ 0x7f, 0x1b, 0x86, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvslti.b $xr31, $xr27, 6"
+  -
+    input:
+      bytes: [ 0x65, 0x9a, 0x86, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvslti.h $xr5, $xr19, 6"
+  -
+    input:
+      bytes: [ 0x14, 0x2d, 0x87, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvslti.w $xr20, $xr8, 0xb"
+  -
+    input:
+      bytes: [ 0x4d, 0x8a, 0x87, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvslti.d $xr13, $xr18, 2"
+  -
+    input:
+      bytes: [ 0xb4, 0x75, 0x08, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvslt.bu $xr20, $xr13, $xr29"
+  -
+    input:
+      bytes: [ 0xac, 0xeb, 0x08, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvslt.hu $xr12, $xr29, $xr26"
+  -
+    input:
+      bytes: [ 0x3a, 0x7f, 0x09, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvslt.wu $xr26, $xr25, $xr31"
+  -
+    input:
+      bytes: [ 0x9e, 0x8e, 0x09, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvslt.du $xr30, $xr20, $xr3"
+  -
+    input:
+      bytes: [ 0x81, 0x08, 0x88, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvslti.bu $xr1, $xr4, 2"
+  -
+    input:
+      bytes: [ 0xa0, 0xd0, 0x88, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvslti.hu $xr0, $xr5, 0x14"
+  -
+    input:
+      bytes: [ 0x20, 0x63, 0x89, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvslti.wu $xr0, $xr25, 0x18"
+  -
+    input:
+      bytes: [ 0xaa, 0xf4, 0x89, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvslti.du $xr10, $xr5, 0x1d"
diff --git a/tests/MC/LoongArch/sra.s.yaml b/tests/MC/LoongArch/sra.s.yaml
new file mode 100644
index 000000000..3ba38d4be
--- /dev/null
+++ b/tests/MC/LoongArch/sra.s.yaml
@@ -0,0 +1,73 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0xec, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsra.b $xr11, $xr2, $xr0"
+  -
+    input:
+      bytes: [ 0x71, 0x9b, 0xec, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsra.h $xr17, $xr27, $xr6"
+  -
+    input:
+      bytes: [ 0x8d, 0x31, 0xed, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsra.w $xr13, $xr12, $xr12"
+  -
+    input:
+      bytes: [ 0xe6, 0x85, 0xed, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsra.d $xr6, $xr15, $xr1"
+  -
+    input:
+      bytes: [ 0x50, 0x2c, 0x34, 0x77 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsrai.b $xr16, $xr2, 3"
+  -
+    input:
+      bytes: [ 0x6e, 0x70, 0x34, 0x77 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsrai.h $xr14, $xr3, 0xc"
+  -
+    input:
+      bytes: [ 0x51, 0xd6, 0x34, 0x77 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsrai.w $xr17, $xr18, 0x15"
+  -
+    input:
+      bytes: [ 0x8a, 0x12, 0x35, 0x77 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsrai.d $xr10, $xr20, 4"
diff --git a/tests/MC/LoongArch/sran.s.yaml b/tests/MC/LoongArch/sran.s.yaml
new file mode 100644
index 000000000..068d76533
--- /dev/null
+++ b/tests/MC/LoongArch/sran.s.yaml
@@ -0,0 +1,28 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xbe, 0x8d, 0xf6, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsran.b.h $xr30, $xr13, $xr3"
+  -
+    input:
+      bytes: [ 0x52, 0x13, 0xf7, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsran.h.w $xr18, $xr26, $xr4"
+  -
+    input:
+      bytes: [ 0x7b, 0xd6, 0xf7, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsran.w.d $xr27, $xr19, $xr21"
diff --git a/tests/MC/LoongArch/srani.s.yaml b/tests/MC/LoongArch/srani.s.yaml
new file mode 100644
index 000000000..ff13fafa8
--- /dev/null
+++ b/tests/MC/LoongArch/srani.s.yaml
@@ -0,0 +1,37 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xee, 0x7e, 0x58, 0x77 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsrani.b.h $xr14, $xr23, 0xf"
+  -
+    input:
+      bytes: [ 0x02, 0x95, 0x58, 0x77 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsrani.h.w $xr2, $xr8, 5"
+  -
+    input:
+      bytes: [ 0x65, 0x39, 0x59, 0x77 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsrani.w.d $xr5, $xr11, 0xe"
+  -
+    input:
+      bytes: [ 0xf1, 0xc4, 0x5b, 0x77 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsrani.d.q $xr17, $xr7, 0x71"
diff --git a/tests/MC/LoongArch/srar.s.yaml b/tests/MC/LoongArch/srar.s.yaml
new file mode 100644
index 000000000..a3d0b2d5d
--- /dev/null
+++ b/tests/MC/LoongArch/srar.s.yaml
@@ -0,0 +1,73 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x49, 0x2e, 0xf2, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsrar.b $xr9, $xr18, $xr11"
+  -
+    input:
+      bytes: [ 0x4f, 0x87, 0xf2, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsrar.h $xr15, $xr26, $xr1"
+  -
+    input:
+      bytes: [ 0x71, 0x3a, 0xf3, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsrar.w $xr17, $xr19, $xr14"
+  -
+    input:
+      bytes: [ 0xf3, 0x99, 0xf3, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsrar.d $xr19, $xr15, $xr6"
+  -
+    input:
+      bytes: [ 0x8a, 0x2f, 0xa8, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsrari.b $xr10, $xr28, 3"
+  -
+    input:
+      bytes: [ 0x3c, 0x78, 0xa8, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsrari.h $xr28, $xr1, 0xe"
+  -
+    input:
+      bytes: [ 0xed, 0xb0, 0xa8, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsrari.w $xr13, $xr7, 0xc"
+  -
+    input:
+      bytes: [ 0x3d, 0x21, 0xa9, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsrari.d $xr29, $xr9, 8"
diff --git a/tests/MC/LoongArch/srarn.s.yaml b/tests/MC/LoongArch/srarn.s.yaml
new file mode 100644
index 000000000..222843dc1
--- /dev/null
+++ b/tests/MC/LoongArch/srarn.s.yaml
@@ -0,0 +1,28 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x92, 0xbe, 0xfa, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsrarn.b.h $xr18, $xr20, $xr15"
+  -
+    input:
+      bytes: [ 0x2c, 0x10, 0xfb, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsrarn.h.w $xr12, $xr1, $xr4"
+  -
+    input:
+      bytes: [ 0x49, 0xea, 0xfb, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsrarn.w.d $xr9, $xr18, $xr26"
diff --git a/tests/MC/LoongArch/srarni.s.yaml b/tests/MC/LoongArch/srarni.s.yaml
new file mode 100644
index 000000000..0ce5da5ab
--- /dev/null
+++ b/tests/MC/LoongArch/srarni.s.yaml
@@ -0,0 +1,37 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xf5, 0x7f, 0x5c, 0x77 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsrarni.b.h $xr21, $xr31, 0xf"
+  -
+    input:
+      bytes: [ 0xc4, 0xe6, 0x5c, 0x77 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsrarni.h.w $xr4, $xr22, 0x19"
+  -
+    input:
+      bytes: [ 0x18, 0xa5, 0x5d, 0x77 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsrarni.w.d $xr24, $xr8, 0x29"
+  -
+    input:
+      bytes: [ 0xa7, 0x1c, 0x5e, 0x77 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsrarni.d.q $xr7, $xr5, 7"
diff --git a/tests/MC/LoongArch/srl.s.yaml b/tests/MC/LoongArch/srl.s.yaml
new file mode 100644
index 000000000..443573e04
--- /dev/null
+++ b/tests/MC/LoongArch/srl.s.yaml
@@ -0,0 +1,73 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x14, 0x77, 0xea, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsrl.b $xr20, $xr24, $xr29"
+  -
+    input:
+      bytes: [ 0x2b, 0xfe, 0xea, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsrl.h $xr11, $xr17, $xr31"
+  -
+    input:
+      bytes: [ 0x42, 0x21, 0xeb, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsrl.w $xr2, $xr10, $xr8"
+  -
+    input:
+      bytes: [ 0xcd, 0xeb, 0xeb, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsrl.d $xr13, $xr30, $xr26"
+  -
+    input:
+      bytes: [ 0x9d, 0x2c, 0x30, 0x77 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsrli.b $xr29, $xr4, 3"
+  -
+    input:
+      bytes: [ 0xdc, 0x71, 0x30, 0x77 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsrli.h $xr28, $xr14, 0xc"
+  -
+    input:
+      bytes: [ 0x4c, 0x9e, 0x30, 0x77 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsrli.w $xr12, $xr18, 7"
+  -
+    input:
+      bytes: [ 0x80, 0xb8, 0x31, 0x77 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsrli.d $xr0, $xr4, 0x2e"
diff --git a/tests/MC/LoongArch/srln.s.yaml b/tests/MC/LoongArch/srln.s.yaml
new file mode 100644
index 000000000..56f2ba3f8
--- /dev/null
+++ b/tests/MC/LoongArch/srln.s.yaml
@@ -0,0 +1,28 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xa7, 0x95, 0xf4, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsrln.b.h $xr7, $xr13, $xr5"
+  -
+    input:
+      bytes: [ 0x46, 0x16, 0xf5, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsrln.h.w $xr6, $xr18, $xr5"
+  -
+    input:
+      bytes: [ 0x8c, 0xf1, 0xf5, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsrln.w.d $xr12, $xr12, $xr28"
diff --git a/tests/MC/LoongArch/srlni.s.yaml b/tests/MC/LoongArch/srlni.s.yaml
new file mode 100644
index 000000000..964f4585b
--- /dev/null
+++ b/tests/MC/LoongArch/srlni.s.yaml
@@ -0,0 +1,37 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x05, 0x49, 0x40, 0x77 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsrlni.b.h $xr5, $xr8, 2"
+  -
+    input:
+      bytes: [ 0x87, 0xd0, 0x40, 0x77 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsrlni.h.w $xr7, $xr4, 0x14"
+  -
+    input:
+      bytes: [ 0xfe, 0x45, 0x41, 0x77 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsrlni.w.d $xr30, $xr15, 0x11"
+  -
+    input:
+      bytes: [ 0x8f, 0x7f, 0x43, 0x77 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsrlni.d.q $xr15, $xr28, 0x5f"
diff --git a/tests/MC/LoongArch/srlr.s.yaml b/tests/MC/LoongArch/srlr.s.yaml
new file mode 100644
index 000000000..7d36eb0df
--- /dev/null
+++ b/tests/MC/LoongArch/srlr.s.yaml
@@ -0,0 +1,73 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x72, 0x15, 0xf0, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsrlr.b $xr18, $xr11, $xr5"
+  -
+    input:
+      bytes: [ 0xbf, 0xd4, 0xf0, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsrlr.h $xr31, $xr5, $xr21"
+  -
+    input:
+      bytes: [ 0xa7, 0x04, 0xf1, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsrlr.w $xr7, $xr5, $xr1"
+  -
+    input:
+      bytes: [ 0x64, 0x9f, 0xf1, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsrlr.d $xr4, $xr27, $xr7"
+  -
+    input:
+      bytes: [ 0xdd, 0x33, 0xa4, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsrlri.b $xr29, $xr30, 4"
+  -
+    input:
+      bytes: [ 0xd0, 0x78, 0xa4, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsrlri.h $xr16, $xr6, 0xe"
+  -
+    input:
+      bytes: [ 0x58, 0xf1, 0xa4, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsrlri.w $xr24, $xr10, 0x1c"
+  -
+    input:
+      bytes: [ 0x94, 0xd2, 0xa5, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsrlri.d $xr20, $xr20, 0x34"
diff --git a/tests/MC/LoongArch/srlrn.s.yaml b/tests/MC/LoongArch/srlrn.s.yaml
new file mode 100644
index 000000000..9e0b9871d
--- /dev/null
+++ b/tests/MC/LoongArch/srlrn.s.yaml
@@ -0,0 +1,28 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x24, 0xeb, 0xf8, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsrlrn.b.h $xr4, $xr25, $xr26"
+  -
+    input:
+      bytes: [ 0xb1, 0x04, 0xf9, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsrlrn.h.w $xr17, $xr5, $xr1"
+  -
+    input:
+      bytes: [ 0x3d, 0xc4, 0xf9, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsrlrn.w.d $xr29, $xr1, $xr17"
diff --git a/tests/MC/LoongArch/srlrni.s.yaml b/tests/MC/LoongArch/srlrni.s.yaml
new file mode 100644
index 000000000..180a0ab66
--- /dev/null
+++ b/tests/MC/LoongArch/srlrni.s.yaml
@@ -0,0 +1,37 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x2a, 0x72, 0x44, 0x77 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsrlrni.b.h $xr10, $xr17, 0xc"
+  -
+    input:
+      bytes: [ 0xf6, 0xb6, 0x44, 0x77 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsrlrni.h.w $xr22, $xr23, 0xd"
+  -
+    input:
+      bytes: [ 0xd2, 0xea, 0x45, 0x77 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsrlrni.w.d $xr18, $xr22, 0x3a"
+  -
+    input:
+      bytes: [ 0x19, 0xa9, 0x46, 0x77 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsrlrni.d.q $xr25, $xr8, 0x2a"
diff --git a/tests/MC/LoongArch/ssran.s.yaml b/tests/MC/LoongArch/ssran.s.yaml
new file mode 100644
index 000000000..202bac488
--- /dev/null
+++ b/tests/MC/LoongArch/ssran.s.yaml
@@ -0,0 +1,55 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x91, 0x84, 0xfe, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvssran.b.h $xr17, $xr4, $xr1"
+  -
+    input:
+      bytes: [ 0x9c, 0x37, 0xff, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvssran.h.w $xr28, $xr28, $xr13"
+  -
+    input:
+      bytes: [ 0x35, 0xfc, 0xff, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvssran.w.d $xr21, $xr1, $xr31"
+  -
+    input:
+      bytes: [ 0x83, 0xe1, 0x06, 0x75 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvssran.bu.h $xr3, $xr12, $xr24"
+  -
+    input:
+      bytes: [ 0x19, 0x07, 0x07, 0x75 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvssran.hu.w $xr25, $xr24, $xr1"
+  -
+    input:
+      bytes: [ 0xde, 0xa9, 0x07, 0x75 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvssran.wu.d $xr30, $xr14, $xr10"
diff --git a/tests/MC/LoongArch/ssrani.s.yaml b/tests/MC/LoongArch/ssrani.s.yaml
new file mode 100644
index 000000000..324ec4f86
--- /dev/null
+++ b/tests/MC/LoongArch/ssrani.s.yaml
@@ -0,0 +1,73 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xda, 0x7a, 0x60, 0x77 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvssrani.b.h $xr26, $xr22, 0xe"
+  -
+    input:
+      bytes: [ 0xd3, 0xe9, 0x60, 0x77 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvssrani.h.w $xr19, $xr14, 0x1a"
+  -
+    input:
+      bytes: [ 0x61, 0x6f, 0x61, 0x77 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvssrani.w.d $xr1, $xr27, 0x1b"
+  -
+    input:
+      bytes: [ 0x49, 0xed, 0x62, 0x77 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvssrani.d.q $xr9, $xr10, 0x3b"
+  -
+    input:
+      bytes: [ 0x66, 0x68, 0x64, 0x77 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvssrani.bu.h $xr6, $xr3, 0xa"
+  -
+    input:
+      bytes: [ 0x34, 0x99, 0x64, 0x77 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvssrani.hu.w $xr20, $xr9, 6"
+  -
+    input:
+      bytes: [ 0x78, 0x21, 0x65, 0x77 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvssrani.wu.d $xr24, $xr11, 8"
+  -
+    input:
+      bytes: [ 0x50, 0x3c, 0x66, 0x77 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvssrani.du.q $xr16, $xr2, 0xf"
diff --git a/tests/MC/LoongArch/ssrarn.s.yaml b/tests/MC/LoongArch/ssrarn.s.yaml
new file mode 100644
index 000000000..d65317774
--- /dev/null
+++ b/tests/MC/LoongArch/ssrarn.s.yaml
@@ -0,0 +1,55 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xa7, 0x81, 0x02, 0x75 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvssrarn.b.h $xr7, $xr13, $xr0"
+  -
+    input:
+      bytes: [ 0x56, 0x38, 0x03, 0x75 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvssrarn.h.w $xr22, $xr2, $xr14"
+  -
+    input:
+      bytes: [ 0xed, 0xc0, 0x03, 0x75 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvssrarn.w.d $xr13, $xr7, $xr16"
+  -
+    input:
+      bytes: [ 0x84, 0x89, 0x0a, 0x75 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvssrarn.bu.h $xr4, $xr12, $xr2"
+  -
+    input:
+      bytes: [ 0x0f, 0x0f, 0x0b, 0x75 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvssrarn.hu.w $xr15, $xr24, $xr3"
+  -
+    input:
+      bytes: [ 0x3e, 0xa1, 0x0b, 0x75 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvssrarn.wu.d $xr30, $xr9, $xr8"
diff --git a/tests/MC/LoongArch/ssrarni.s.yaml b/tests/MC/LoongArch/ssrarni.s.yaml
new file mode 100644
index 000000000..93e5ce4f1
--- /dev/null
+++ b/tests/MC/LoongArch/ssrarni.s.yaml
@@ -0,0 +1,73 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x80, 0x74, 0x68, 0x77 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvssrarni.b.h $xr0, $xr4, 0xd"
+  -
+    input:
+      bytes: [ 0x08, 0xa4, 0x68, 0x77 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvssrarni.h.w $xr8, $xr0, 0x9"
+  -
+    input:
+      bytes: [ 0xa5, 0xa8, 0x69, 0x77 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvssrarni.w.d $xr5, $xr5, 0x2a"
+  -
+    input:
+      bytes: [ 0xe8, 0x4f, 0x6b, 0x77 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvssrarni.d.q $xr8, $xr31, 0x53"
+  -
+    input:
+      bytes: [ 0x75, 0x42, 0x6c, 0x77 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvssrarni.bu.h $xr21, $xr19, 0"
+  -
+    input:
+      bytes: [ 0xb6, 0x85, 0x6c, 0x77 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvssrarni.hu.w $xr22, $xr13, 1"
+  -
+    input:
+      bytes: [ 0xb5, 0x68, 0x6d, 0x77 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvssrarni.wu.d $xr21, $xr5, 0x1a"
+  -
+    input:
+      bytes: [ 0xcf, 0x79, 0x6f, 0x77 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvssrarni.du.q $xr15, $xr14, 0x5e"
diff --git a/tests/MC/LoongArch/ssrln.s.yaml b/tests/MC/LoongArch/ssrln.s.yaml
new file mode 100644
index 000000000..9f89f155d
--- /dev/null
+++ b/tests/MC/LoongArch/ssrln.s.yaml
@@ -0,0 +1,55 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x98, 0x90, 0xfc, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvssrln.b.h $xr24, $xr4, $xr4"
+  -
+    input:
+      bytes: [ 0xe5, 0x01, 0xfd, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvssrln.h.w $xr5, $xr15, $xr0"
+  -
+    input:
+      bytes: [ 0x20, 0xfb, 0xfd, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvssrln.w.d $xr0, $xr25, $xr30"
+  -
+    input:
+      bytes: [ 0x3a, 0xe9, 0x04, 0x75 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvssrln.bu.h $xr26, $xr9, $xr26"
+  -
+    input:
+      bytes: [ 0x87, 0x06, 0x05, 0x75 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvssrln.hu.w $xr7, $xr20, $xr1"
+  -
+    input:
+      bytes: [ 0xaf, 0xd1, 0x05, 0x75 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvssrln.wu.d $xr15, $xr13, $xr20"
diff --git a/tests/MC/LoongArch/ssrlni.s.yaml b/tests/MC/LoongArch/ssrlni.s.yaml
new file mode 100644
index 000000000..9cd00bfae
--- /dev/null
+++ b/tests/MC/LoongArch/ssrlni.s.yaml
@@ -0,0 +1,73 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x53, 0x66, 0x48, 0x77 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvssrlni.b.h $xr19, $xr18, 0x9"
+  -
+    input:
+      bytes: [ 0xbd, 0x8f, 0x48, 0x77 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvssrlni.h.w $xr29, $xr29, 3"
+  -
+    input:
+      bytes: [ 0xe9, 0xad, 0x49, 0x77 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvssrlni.w.d $xr9, $xr15, 0x2b"
+  -
+    input:
+      bytes: [ 0x68, 0xe5, 0x4b, 0x77 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvssrlni.d.q $xr8, $xr11, 0x79"
+  -
+    input:
+      bytes: [ 0x59, 0x55, 0x4c, 0x77 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvssrlni.bu.h $xr25, $xr10, 5"
+  -
+    input:
+      bytes: [ 0x49, 0xea, 0x4c, 0x77 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvssrlni.hu.w $xr9, $xr18, 0x1a"
+  -
+    input:
+      bytes: [ 0xd4, 0x36, 0x4d, 0x77 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvssrlni.wu.d $xr20, $xr22, 0xd"
+  -
+    input:
+      bytes: [ 0x88, 0xac, 0x4e, 0x77 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvssrlni.du.q $xr8, $xr4, 0x2b"
diff --git a/tests/MC/LoongArch/ssrlrn.s.yaml b/tests/MC/LoongArch/ssrlrn.s.yaml
new file mode 100644
index 000000000..d39995898
--- /dev/null
+++ b/tests/MC/LoongArch/ssrlrn.s.yaml
@@ -0,0 +1,55 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x88, 0xca, 0x00, 0x75 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvssrlrn.b.h $xr8, $xr20, $xr18"
+  -
+    input:
+      bytes: [ 0xa2, 0x4d, 0x01, 0x75 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvssrlrn.h.w $xr2, $xr13, $xr19"
+  -
+    input:
+      bytes: [ 0xf8, 0x94, 0x01, 0x75 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvssrlrn.w.d $xr24, $xr7, $xr5"
+  -
+    input:
+      bytes: [ 0xef, 0xca, 0x08, 0x75 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvssrlrn.bu.h $xr15, $xr23, $xr18"
+  -
+    input:
+      bytes: [ 0xd6, 0x41, 0x09, 0x75 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvssrlrn.hu.w $xr22, $xr14, $xr16"
+  -
+    input:
+      bytes: [ 0x94, 0x97, 0x09, 0x75 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvssrlrn.wu.d $xr20, $xr28, $xr5"
diff --git a/tests/MC/LoongArch/ssrlrni.s.yaml b/tests/MC/LoongArch/ssrlrni.s.yaml
new file mode 100644
index 000000000..c8be55572
--- /dev/null
+++ b/tests/MC/LoongArch/ssrlrni.s.yaml
@@ -0,0 +1,73 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x5a, 0x63, 0x50, 0x77 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvssrlrni.b.h $xr26, $xr26, 8"
+  -
+    input:
+      bytes: [ 0x06, 0xcc, 0x50, 0x77 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvssrlrni.h.w $xr6, $xr0, 0x13"
+  -
+    input:
+      bytes: [ 0xfc, 0xdd, 0x51, 0x77 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvssrlrni.w.d $xr28, $xr15, 0x37"
+  -
+    input:
+      bytes: [ 0x08, 0x02, 0x53, 0x77 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvssrlrni.d.q $xr8, $xr16, 0x40"
+  -
+    input:
+      bytes: [ 0x97, 0x4f, 0x54, 0x77 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvssrlrni.bu.h $xr23, $xr28, 3"
+  -
+    input:
+      bytes: [ 0x59, 0xc9, 0x54, 0x77 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvssrlrni.hu.w $xr25, $xr10, 0x12"
+  -
+    input:
+      bytes: [ 0x90, 0x3f, 0x55, 0x77 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvssrlrni.wu.d $xr16, $xr28, 0xf"
+  -
+    input:
+      bytes: [ 0x32, 0xb1, 0x56, 0x77 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvssrlrni.du.q $xr18, $xr9, 0x2c"
diff --git a/tests/MC/LoongArch/ssub.s.yaml b/tests/MC/LoongArch/ssub.s.yaml
new file mode 100644
index 000000000..d091d236f
--- /dev/null
+++ b/tests/MC/LoongArch/ssub.s.yaml
@@ -0,0 +1,73 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x6e, 0x62, 0x48, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvssub.b $xr14, $xr19, $xr24"
+  -
+    input:
+      bytes: [ 0x0d, 0xcd, 0x48, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvssub.h $xr13, $xr8, $xr19"
+  -
+    input:
+      bytes: [ 0x7c, 0x73, 0x49, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvssub.w $xr28, $xr27, $xr28"
+  -
+    input:
+      bytes: [ 0x1c, 0x8a, 0x49, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvssub.d $xr28, $xr16, $xr2"
+  -
+    input:
+      bytes: [ 0xab, 0x45, 0x4c, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvssub.bu $xr11, $xr13, $xr17"
+  -
+    input:
+      bytes: [ 0x50, 0xf1, 0x4c, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvssub.hu $xr16, $xr10, $xr28"
+  -
+    input:
+      bytes: [ 0x15, 0x34, 0x4d, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvssub.wu $xr21, $xr0, $xr13"
+  -
+    input:
+      bytes: [ 0x52, 0xef, 0x4d, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvssub.du $xr18, $xr26, $xr27"
diff --git a/tests/MC/LoongArch/st.s.yaml b/tests/MC/LoongArch/st.s.yaml
new file mode 100644
index 000000000..138d14e1d
--- /dev/null
+++ b/tests/MC/LoongArch/st.s.yaml
@@ -0,0 +1,19 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x8e, 0xbd, 0xce, 0x2c ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvst $xr14, $t0, 0x3af"
+  -
+    input:
+      bytes: [ 0x27, 0x55, 0x4c, 0x38 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvstx $xr7, $a5, $r21"
diff --git a/tests/MC/LoongArch/stelm.s.yaml b/tests/MC/LoongArch/stelm.s.yaml
new file mode 100644
index 000000000..06984b000
--- /dev/null
+++ b/tests/MC/LoongArch/stelm.s.yaml
@@ -0,0 +1,37 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x54, 0x5c, 0xaa, 0x33 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvstelm.b $xr20, $tp, -0x69, 0xa"
+  -
+    input:
+      bytes: [ 0x28, 0x40, 0x51, 0x33 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvstelm.h $xr8, $ra, 0xa0, 4"
+  -
+    input:
+      bytes: [ 0x53, 0x9e, 0x21, 0x33 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvstelm.w $xr19, $t6, 0x19c, 0"
+  -
+    input:
+      bytes: [ 0xd6, 0xe3, 0x1d, 0x33 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvstelm.d $xr22, $s7, 0x3c0, 3"
diff --git a/tests/MC/LoongArch/sub.s.yaml b/tests/MC/LoongArch/sub.s.yaml
new file mode 100644
index 000000000..62989d73c
--- /dev/null
+++ b/tests/MC/LoongArch/sub.s.yaml
@@ -0,0 +1,46 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x8b, 0x43, 0x0c, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsub.b $xr11, $xr28, $xr16"
+  -
+    input:
+      bytes: [ 0x6b, 0xe0, 0x0c, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsub.h $xr11, $xr3, $xr24"
+  -
+    input:
+      bytes: [ 0xee, 0x1a, 0x0d, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsub.w $xr14, $xr23, $xr6"
+  -
+    input:
+      bytes: [ 0xa5, 0x9d, 0x0d, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsub.d $xr5, $xr13, $xr7"
+  -
+    input:
+      bytes: [ 0x4d, 0xff, 0x2d, 0x75 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsub.q $xr13, $xr26, $xr31"
diff --git a/tests/MC/LoongArch/subi.s.yaml b/tests/MC/LoongArch/subi.s.yaml
new file mode 100644
index 000000000..2bc3080b2
--- /dev/null
+++ b/tests/MC/LoongArch/subi.s.yaml
@@ -0,0 +1,37 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x72, 0x07, 0x8c, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsubi.bu $xr18, $xr27, 1"
+  -
+    input:
+      bytes: [ 0xe6, 0xce, 0x8c, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsubi.hu $xr6, $xr23, 0x13"
+  -
+    input:
+      bytes: [ 0x6d, 0x14, 0x8d, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsubi.wu $xr13, $xr3, 5"
+  -
+    input:
+      bytes: [ 0x9a, 0xbb, 0x8d, 0x76 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsubi.du $xr26, $xr28, 0xe"
diff --git a/tests/MC/LoongArch/subw.s.yaml b/tests/MC/LoongArch/subw.s.yaml
new file mode 100644
index 000000000..b71b741c2
--- /dev/null
+++ b/tests/MC/LoongArch/subw.s.yaml
@@ -0,0 +1,145 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x3d, 0x70, 0x20, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsubwev.h.b $xr29, $xr1, $xr28"
+  -
+    input:
+      bytes: [ 0x98, 0xfe, 0x20, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsubwev.w.h $xr24, $xr20, $xr31"
+  -
+    input:
+      bytes: [ 0x86, 0x2c, 0x21, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsubwev.d.w $xr6, $xr4, $xr11"
+  -
+    input:
+      bytes: [ 0xfb, 0xb7, 0x21, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsubwev.q.d $xr27, $xr31, $xr13"
+  -
+    input:
+      bytes: [ 0x81, 0x0a, 0x30, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsubwev.h.bu $xr1, $xr20, $xr2"
+  -
+    input:
+      bytes: [ 0xd3, 0xb0, 0x30, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsubwev.w.hu $xr19, $xr6, $xr12"
+  -
+    input:
+      bytes: [ 0x3f, 0x5c, 0x31, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsubwev.d.wu $xr31, $xr1, $xr23"
+  -
+    input:
+      bytes: [ 0x9f, 0xc7, 0x31, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsubwev.q.du $xr31, $xr28, $xr17"
+  -
+    input:
+      bytes: [ 0x23, 0x45, 0x24, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsubwod.h.b $xr3, $xr9, $xr17"
+  -
+    input:
+      bytes: [ 0xae, 0xd4, 0x24, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsubwod.w.h $xr14, $xr5, $xr21"
+  -
+    input:
+      bytes: [ 0xc8, 0x0d, 0x25, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsubwod.d.w $xr8, $xr14, $xr3"
+  -
+    input:
+      bytes: [ 0xf8, 0xc9, 0x25, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsubwod.q.d $xr24, $xr15, $xr18"
+  -
+    input:
+      bytes: [ 0x5b, 0x04, 0x34, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsubwod.h.bu $xr27, $xr2, $xr1"
+  -
+    input:
+      bytes: [ 0xf3, 0xd8, 0x34, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsubwod.w.hu $xr19, $xr7, $xr22"
+  -
+    input:
+      bytes: [ 0x01, 0x6b, 0x35, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsubwod.d.wu $xr1, $xr24, $xr26"
+  -
+    input:
+      bytes: [ 0x5d, 0x9f, 0x35, 0x74 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvsubwod.q.du $xr29, $xr26, $xr7"
diff --git a/tests/MC/LoongArch/valid.s.yaml b/tests/MC/LoongArch/valid.s.yaml
new file mode 100644
index 000000000..ad7d0f8b8
--- /dev/null
+++ b/tests/MC/LoongArch/valid.s.yaml
@@ -0,0 +1,199 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x1a, 0x78, 0x00, 0x04 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "csrrd $s3, 0x1e"
+  -
+    input:
+      bytes: [ 0x38, 0x08, 0x03, 0x04 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "csrwr $s1, 0xc2"
+  -
+    input:
+      bytes: [ 0x66, 0x5b, 0x03, 0x04 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "csrxchg $a2, $s4, 0xd6"
+  -
+    input:
+      bytes: [ 0x1a, 0x03, 0x48, 0x06 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "iocsrrd.b $s3, $s1"
+  -
+    input:
+      bytes: [ 0x65, 0x07, 0x48, 0x06 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "iocsrrd.h $a1, $s4"
+  -
+    input:
+      bytes: [ 0x8a, 0x0a, 0x48, 0x06 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "iocsrrd.w $a6, $t8"
+  -
+    input:
+      bytes: [ 0xe4, 0x12, 0x48, 0x06 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "iocsrwr.b $a0, $s0"
+  -
+    input:
+      bytes: [ 0x0b, 0x14, 0x48, 0x06 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "iocsrwr.h $a7, $zero"
+  -
+    input:
+      bytes: [ 0x54, 0x1b, 0x48, 0x06 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "iocsrwr.w $t8, $s3"
+  -
+    input:
+      bytes: [ 0x40, 0x6d, 0x00, 0x06 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "cacop 0, $a6, 0x1b"
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x48, 0x06 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "tlbclr"
+  -
+    input:
+      bytes: [ 0x00, 0x24, 0x48, 0x06 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "tlbflush"
+  -
+    input:
+      bytes: [ 0x00, 0x28, 0x48, 0x06 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "tlbsrch"
+  -
+    input:
+      bytes: [ 0x00, 0x2c, 0x48, 0x06 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "tlbrd"
+  -
+    input:
+      bytes: [ 0x00, 0x30, 0x48, 0x06 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "tlbwr"
+  -
+    input:
+      bytes: [ 0x00, 0x34, 0x48, 0x06 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "tlbfill"
+  -
+    input:
+      bytes: [ 0xb0, 0xe7, 0x49, 0x06 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "invtlb 0x10, $s6, $s2"
+  -
+    input:
+      bytes: [ 0xcc, 0x73, 0x41, 0x06 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "lddir $t0, $s7, 0x5c"
+  -
+    input:
+      bytes: [ 0x40, 0x22, 0x47, 0x06 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldpte $t6, 0xc8"
+  -
+    input:
+      bytes: [ 0x00, 0x38, 0x48, 0x06 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "ertn"
+  -
+    input:
+      bytes: [ 0xc9, 0x80, 0x2a, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "dbcl 0xc9"
+  -
+    input:
+      bytes: [ 0xcc, 0x80, 0x48, 0x06 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "idle 0xcc"
diff --git a/tests/MC/LoongArch/x86-alu.s.yaml b/tests/MC/LoongArch/x86-alu.s.yaml
new file mode 100644
index 000000000..d7ee2a838
--- /dev/null
+++ b/tests/MC/LoongArch/x86-alu.s.yaml
@@ -0,0 +1,433 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x8c, 0x14, 0x3f, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "x86adc.b $a0, $a1"
+  -
+    input:
+      bytes: [ 0x8d, 0x14, 0x3f, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "x86adc.h $a0, $a1"
+  -
+    input:
+      bytes: [ 0x8e, 0x14, 0x3f, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "x86adc.w $a0, $a1"
+  -
+    input:
+      bytes: [ 0x8f, 0x14, 0x3f, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "x86adc.d $a0, $a1"
+  -
+    input:
+      bytes: [ 0x84, 0x14, 0x3f, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "x86add.b $a0, $a1"
+  -
+    input:
+      bytes: [ 0x85, 0x14, 0x3f, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "x86add.h $a0, $a1"
+  -
+    input:
+      bytes: [ 0x86, 0x14, 0x3f, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "x86add.w $a0, $a1"
+  -
+    input:
+      bytes: [ 0x87, 0x14, 0x3f, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "x86add.d $a0, $a1"
+  -
+    input:
+      bytes: [ 0x80, 0x14, 0x3f, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "x86add.wu $a0, $a1"
+  -
+    input:
+      bytes: [ 0x81, 0x14, 0x3f, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "x86add.du $a0, $a1"
+  -
+    input:
+      bytes: [ 0x80, 0x80, 0x00, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "x86inc.b $a0"
+  -
+    input:
+      bytes: [ 0x81, 0x80, 0x00, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "x86inc.h $a0"
+  -
+    input:
+      bytes: [ 0x82, 0x80, 0x00, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "x86inc.w $a0"
+  -
+    input:
+      bytes: [ 0x83, 0x80, 0x00, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "x86inc.d $a0"
+  -
+    input:
+      bytes: [ 0x90, 0x14, 0x3f, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "x86sbc.b $a0, $a1"
+  -
+    input:
+      bytes: [ 0x91, 0x14, 0x3f, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "x86sbc.h $a0, $a1"
+  -
+    input:
+      bytes: [ 0x92, 0x14, 0x3f, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "x86sbc.w $a0, $a1"
+  -
+    input:
+      bytes: [ 0x93, 0x14, 0x3f, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "x86sbc.d $a0, $a1"
+  -
+    input:
+      bytes: [ 0x88, 0x14, 0x3f, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "x86sub.b $a0, $a1"
+  -
+    input:
+      bytes: [ 0x89, 0x14, 0x3f, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "x86sub.h $a0, $a1"
+  -
+    input:
+      bytes: [ 0x8a, 0x14, 0x3f, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "x86sub.w $a0, $a1"
+  -
+    input:
+      bytes: [ 0x8b, 0x14, 0x3f, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "x86sub.d $a0, $a1"
+  -
+    input:
+      bytes: [ 0x82, 0x14, 0x3f, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "x86sub.wu $a0, $a1"
+  -
+    input:
+      bytes: [ 0x83, 0x14, 0x3f, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "x86sub.du $a0, $a1"
+  -
+    input:
+      bytes: [ 0x84, 0x80, 0x00, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "x86dec.b $a0"
+  -
+    input:
+      bytes: [ 0x85, 0x80, 0x00, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "x86dec.h $a0"
+  -
+    input:
+      bytes: [ 0x86, 0x80, 0x00, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "x86dec.w $a0"
+  -
+    input:
+      bytes: [ 0x87, 0x80, 0x00, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "x86dec.d $a0"
+  -
+    input:
+      bytes: [ 0x90, 0x94, 0x3f, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "x86and.b $a0, $a1"
+  -
+    input:
+      bytes: [ 0x91, 0x94, 0x3f, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "x86and.h $a0, $a1"
+  -
+    input:
+      bytes: [ 0x92, 0x94, 0x3f, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "x86and.w $a0, $a1"
+  -
+    input:
+      bytes: [ 0x93, 0x94, 0x3f, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "x86and.d $a0, $a1"
+  -
+    input:
+      bytes: [ 0x94, 0x94, 0x3f, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "x86or.b $a0, $a1"
+  -
+    input:
+      bytes: [ 0x95, 0x94, 0x3f, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "x86or.h $a0, $a1"
+  -
+    input:
+      bytes: [ 0x96, 0x94, 0x3f, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "x86or.w $a0, $a1"
+  -
+    input:
+      bytes: [ 0x97, 0x94, 0x3f, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "x86or.d $a0, $a1"
+  -
+    input:
+      bytes: [ 0x98, 0x94, 0x3f, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "x86xor.b $a0, $a1"
+  -
+    input:
+      bytes: [ 0x99, 0x94, 0x3f, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "x86xor.h $a0, $a1"
+  -
+    input:
+      bytes: [ 0x9a, 0x94, 0x3f, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "x86xor.w $a0, $a1"
+  -
+    input:
+      bytes: [ 0x9b, 0x94, 0x3f, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "x86xor.d $a0, $a1"
+  -
+    input:
+      bytes: [ 0x80, 0x94, 0x3e, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "x86mul.b $a0, $a1"
+  -
+    input:
+      bytes: [ 0x81, 0x94, 0x3e, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "x86mul.h $a0, $a1"
+  -
+    input:
+      bytes: [ 0x82, 0x94, 0x3e, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "x86mul.w $a0, $a1"
+  -
+    input:
+      bytes: [ 0x83, 0x94, 0x3e, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "x86mul.d $a0, $a1"
+  -
+    input:
+      bytes: [ 0x84, 0x94, 0x3e, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "x86mul.bu $a0, $a1"
+  -
+    input:
+      bytes: [ 0x85, 0x94, 0x3e, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "x86mul.hu $a0, $a1"
+  -
+    input:
+      bytes: [ 0x86, 0x94, 0x3e, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "x86mul.wu $a0, $a1"
+  -
+    input:
+      bytes: [ 0x87, 0x94, 0x3e, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "x86mul.du $a0, $a1"
diff --git a/tests/MC/LoongArch/x86-jump.s.yaml b/tests/MC/LoongArch/x86-jump.s.yaml
new file mode 100644
index 000000000..8f8192738
--- /dev/null
+++ b/tests/MC/LoongArch/x86-jump.s.yaml
@@ -0,0 +1,28 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x04, 0x84, 0x36, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "setx86j $a0, 1"
+  -
+    input:
+      bytes: [ 0xa4, 0x78, 0x00, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "setx86loope $a0, $a1"
+  -
+    input:
+      bytes: [ 0xa4, 0x7c, 0x00, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "setx86loopne $a0, $a1"
diff --git a/tests/MC/LoongArch/x86-misc.s.yaml b/tests/MC/LoongArch/x86-misc.s.yaml
new file mode 100644
index 000000000..29d878710
--- /dev/null
+++ b/tests/MC/LoongArch/x86-misc.s.yaml
@@ -0,0 +1,82 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x04, 0x04, 0x5c, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "x86mfflag $a0, 1"
+  -
+    input:
+      bytes: [ 0x24, 0x04, 0x5c, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "x86mtflag $a0, 1"
+  -
+    input:
+      bytes: [ 0x04, 0x74, 0x00, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "x86mftop $a0"
+  -
+    input:
+      bytes: [ 0x20, 0x70, 0x00, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "x86mttop 1"
+  -
+    input:
+      bytes: [ 0x09, 0x80, 0x00, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "x86inctop"
+  -
+    input:
+      bytes: [ 0x29, 0x80, 0x00, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "x86dectop"
+  -
+    input:
+      bytes: [ 0x08, 0x80, 0x00, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "x86settm"
+  -
+    input:
+      bytes: [ 0x28, 0x80, 0x00, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "x86clrtm"
+  -
+    input:
+      bytes: [ 0x24, 0x04, 0x58, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "x86settag $a0, 1, 1"
diff --git a/tests/MC/LoongArch/x86-shift.s.yaml b/tests/MC/LoongArch/x86-shift.s.yaml
new file mode 100644
index 000000000..e972d6b22
--- /dev/null
+++ b/tests/MC/LoongArch/x86-shift.s.yaml
@@ -0,0 +1,505 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x8c, 0x94, 0x3f, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "x86rcl.b $a0, $a1"
+  -
+    input:
+      bytes: [ 0x8d, 0x94, 0x3f, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "x86rcl.h $a0, $a1"
+  -
+    input:
+      bytes: [ 0x8e, 0x94, 0x3f, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "x86rcl.w $a0, $a1"
+  -
+    input:
+      bytes: [ 0x8f, 0x94, 0x3f, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "x86rcl.d $a0, $a1"
+  -
+    input:
+      bytes: [ 0x98, 0x24, 0x54, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "x86rcli.b $a0, 1"
+  -
+    input:
+      bytes: [ 0x99, 0x44, 0x54, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "x86rcli.h $a0, 1"
+  -
+    input:
+      bytes: [ 0x9a, 0x84, 0x54, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "x86rcli.w $a0, 1"
+  -
+    input:
+      bytes: [ 0x9b, 0x04, 0x55, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "x86rcli.d $a0, 1"
+  -
+    input:
+      bytes: [ 0x88, 0x94, 0x3f, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "x86rcr.b $a0, $a1"
+  -
+    input:
+      bytes: [ 0x89, 0x94, 0x3f, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "x86rcr.h $a0, $a1"
+  -
+    input:
+      bytes: [ 0x8a, 0x94, 0x3f, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "x86rcr.w $a0, $a1"
+  -
+    input:
+      bytes: [ 0x8b, 0x94, 0x3f, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "x86rcr.d $a0, $a1"
+  -
+    input:
+      bytes: [ 0x90, 0x24, 0x54, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "x86rcri.b $a0, 1"
+  -
+    input:
+      bytes: [ 0x91, 0x44, 0x54, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "x86rcri.h $a0, 1"
+  -
+    input:
+      bytes: [ 0x92, 0x84, 0x54, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "x86rcri.w $a0, 1"
+  -
+    input:
+      bytes: [ 0x93, 0x04, 0x55, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "x86rcri.d $a0, 1"
+  -
+    input:
+      bytes: [ 0x84, 0x94, 0x3f, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "x86rotl.b $a0, $a1"
+  -
+    input:
+      bytes: [ 0x85, 0x94, 0x3f, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "x86rotl.h $a0, $a1"
+  -
+    input:
+      bytes: [ 0x86, 0x94, 0x3f, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "x86rotl.w $a0, $a1"
+  -
+    input:
+      bytes: [ 0x87, 0x94, 0x3f, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "x86rotl.d $a0, $a1"
+  -
+    input:
+      bytes: [ 0x94, 0x24, 0x54, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "x86rotli.b $a0, 1"
+  -
+    input:
+      bytes: [ 0x95, 0x44, 0x54, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "x86rotli.h $a0, 1"
+  -
+    input:
+      bytes: [ 0x96, 0x84, 0x54, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "x86rotli.w $a0, 1"
+  -
+    input:
+      bytes: [ 0x97, 0x04, 0x55, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "x86rotli.d $a0, 1"
+  -
+    input:
+      bytes: [ 0x80, 0x94, 0x3f, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "x86rotr.b $a0, $a1"
+  -
+    input:
+      bytes: [ 0x81, 0x94, 0x3f, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "x86rotr.h $a0, $a1"
+  -
+    input:
+      bytes: [ 0x82, 0x94, 0x3f, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "x86rotr.d $a0, $a1"
+  -
+    input:
+      bytes: [ 0x83, 0x94, 0x3f, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "x86rotr.w $a0, $a1"
+  -
+    input:
+      bytes: [ 0x8c, 0x24, 0x54, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "x86rotri.b $a0, 1"
+  -
+    input:
+      bytes: [ 0x8d, 0x44, 0x54, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "x86rotri.h $a0, 1"
+  -
+    input:
+      bytes: [ 0x8e, 0x84, 0x54, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "x86rotri.w $a0, 1"
+  -
+    input:
+      bytes: [ 0x8f, 0x04, 0x55, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "x86rotri.d $a0, 1"
+  -
+    input:
+      bytes: [ 0x94, 0x14, 0x3f, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "x86sll.b $a0, $a1"
+  -
+    input:
+      bytes: [ 0x95, 0x14, 0x3f, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "x86sll.h $a0, $a1"
+  -
+    input:
+      bytes: [ 0x96, 0x14, 0x3f, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "x86sll.w $a0, $a1"
+  -
+    input:
+      bytes: [ 0x97, 0x14, 0x3f, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "x86sll.d $a0, $a1"
+  -
+    input:
+      bytes: [ 0x80, 0x24, 0x54, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "x86slli.b $a0, 1"
+  -
+    input:
+      bytes: [ 0x81, 0x44, 0x54, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "x86slli.h $a0, 1"
+  -
+    input:
+      bytes: [ 0x82, 0x84, 0x54, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "x86slli.w $a0, 1"
+  -
+    input:
+      bytes: [ 0x83, 0x04, 0x55, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "x86slli.d $a0, 1"
+  -
+    input:
+      bytes: [ 0x98, 0x14, 0x3f, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "x86srl.b $a0, $a1"
+  -
+    input:
+      bytes: [ 0x99, 0x14, 0x3f, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "x86srl.h $a0, $a1"
+  -
+    input:
+      bytes: [ 0x9a, 0x14, 0x3f, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "x86srl.w $a0, $a1"
+  -
+    input:
+      bytes: [ 0x9b, 0x14, 0x3f, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "x86srl.d $a0, $a1"
+  -
+    input:
+      bytes: [ 0x84, 0x24, 0x54, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "x86srli.b $a0, 1"
+  -
+    input:
+      bytes: [ 0x85, 0x44, 0x54, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "x86srli.h $a0, 1"
+  -
+    input:
+      bytes: [ 0x86, 0x84, 0x54, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "x86srli.w $a0, 1"
+  -
+    input:
+      bytes: [ 0x87, 0x04, 0x55, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "x86srli.d $a0, 1"
+  -
+    input:
+      bytes: [ 0x9c, 0x14, 0x3f, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "x86sra.b $a0, $a1"
+  -
+    input:
+      bytes: [ 0x9d, 0x14, 0x3f, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "x86sra.h $a0, $a1"
+  -
+    input:
+      bytes: [ 0x9e, 0x14, 0x3f, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "x86sra.w $a0, $a1"
+  -
+    input:
+      bytes: [ 0x9f, 0x14, 0x3f, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "x86sra.d $a0, $a1"
+  -
+    input:
+      bytes: [ 0x88, 0x24, 0x54, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "x86srai.b $a0, 1"
+  -
+    input:
+      bytes: [ 0x89, 0x44, 0x54, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "x86srai.h $a0, 1"
+  -
+    input:
+      bytes: [ 0x8a, 0x84, 0x54, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "x86srai.w $a0, 1"
+  -
+    input:
+      bytes: [ 0x8b, 0x04, 0x55, 0x00 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "x86srai.d $a0, 1"
diff --git a/tests/MC/LoongArch/xor.s.yaml b/tests/MC/LoongArch/xor.s.yaml
new file mode 100644
index 000000000..e56ca3bc7
--- /dev/null
+++ b/tests/MC/LoongArch/xor.s.yaml
@@ -0,0 +1,10 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x4e, 0x2b, 0x27, 0x75 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvxor.v $xr14, $xr26, $xr10"
diff --git a/tests/MC/LoongArch/xori.s.yaml b/tests/MC/LoongArch/xori.s.yaml
new file mode 100644
index 000000000..e5668eec0
--- /dev/null
+++ b/tests/MC/LoongArch/xori.s.yaml
@@ -0,0 +1,10 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x1a, 0x55, 0xda, 0x77 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ "CS_MODE_LOONGARCH64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xvxori.b $xr26, $xr8, 0x95"
diff --git a/tests/MC/Mips/hilo-addressing.s.yaml b/tests/MC/Mips/hilo-addressing.s.yaml
new file mode 100644
index 000000000..db654d99e
--- /dev/null
+++ b/tests/MC/Mips/hilo-addressing.s.yaml
@@ -0,0 +1,10 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x03, 0xe0, 0x00, 0x08 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "jr $ra"
diff --git a/tests/MC/Mips/micromips-alu-instructions-EB.s.yaml b/tests/MC/Mips/micromips-alu-instructions-EB.s.yaml
new file mode 100644
index 000000000..352ff3e9a
--- /dev/null
+++ b/tests/MC/Mips/micromips-alu-instructions-EB.s.yaml
@@ -0,0 +1,289 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xe6, 0x49, 0x10 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "add $t1, $a2, $a3"
+  -
+    input:
+      bytes: [ 0x11, 0x26, 0x45, 0x67 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "addi $t1, $a2, 17767"
+  -
+    input:
+      bytes: [ 0x31, 0x26, 0xc5, 0x67 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "addiu $t1, $a2, -15001"
+  -
+    input:
+      bytes: [ 0x11, 0x26, 0x45, 0x67 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "addi $t1, $a2, 17767"
+  -
+    input:
+      bytes: [ 0x31, 0x26, 0xc5, 0x67 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "addiu $t1, $a2, -15001"
+  -
+    input:
+      bytes: [ 0x00, 0xe6, 0x49, 0x50 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "addu $t1, $a2, $a3"
+  -
+    input:
+      bytes: [ 0x00, 0xe6, 0x49, 0x90 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub $t1, $a2, $a3"
+  -
+    input:
+      bytes: [ 0x00, 0xa3, 0x21, 0xd0 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "subu $a0, $v1, $a1"
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x31, 0x90 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub $a2, $zero, $a3"
+  -
+    input:
+      bytes: [ 0x00, 0xe0, 0x31, 0xd0 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "subu $a2, $zero, $a3"
+  -
+    input:
+      bytes: [ 0x00, 0x08, 0x39, 0x50 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "addu $a3, $t0, $zero"
+  -
+    input:
+      bytes: [ 0x00, 0xa3, 0x1b, 0x50 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "slt $v1, $v1, $a1"
+  -
+    input:
+      bytes: [ 0x90, 0x63, 0x00, 0x67 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "slti $v1, $v1, 103"
+  -
+    input:
+      bytes: [ 0x90, 0x63, 0x00, 0x67 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "slti $v1, $v1, 103"
+  -
+    input:
+      bytes: [ 0xb0, 0x63, 0x00, 0x67 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "sltiu $v1, $v1, 103"
+  -
+    input:
+      bytes: [ 0x00, 0xa3, 0x1b, 0x90 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "sltu $v1, $v1, $a1"
+  -
+    input:
+      bytes: [ 0x41, 0xa9, 0x45, 0x67 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "lui $t1, 17767"
+  -
+    input:
+      bytes: [ 0x00, 0xe6, 0x4a, 0x50 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "and $t1, $a2, $a3"
+  -
+    input:
+      bytes: [ 0xd1, 0x26, 0x45, 0x67 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "andi $t1, $a2, 17767"
+  -
+    input:
+      bytes: [ 0xd1, 0x26, 0x45, 0x67 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "andi $t1, $a2, 17767"
+  -
+    input:
+      bytes: [ 0x00, 0xa4, 0x1a, 0x90 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "or $v1, $a0, $a1"
+  -
+    input:
+      bytes: [ 0x51, 0x26, 0x45, 0x67 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "ori $t1, $a2, 17767"
+  -
+    input:
+      bytes: [ 0x00, 0xa3, 0x1b, 0x10 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor $v1, $v1, $a1"
+  -
+    input:
+      bytes: [ 0x71, 0x26, 0x45, 0x67 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "xori $t1, $a2, 17767"
+  -
+    input:
+      bytes: [ 0x71, 0x26, 0x45, 0x67 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "xori $t1, $a2, 17767"
+  -
+    input:
+      bytes: [ 0x00, 0xe6, 0x4a, 0xd0 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "nor $t1, $a2, $a3"
+  -
+    input:
+      bytes: [ 0x00, 0x08, 0x3a, 0xd0 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "not $a3, $t0"
+  -
+    input:
+      bytes: [ 0x00, 0xe6, 0x4a, 0x10 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul $t1, $a2, $a3"
+  -
+    input:
+      bytes: [ 0x00, 0xe9, 0x8b, 0x3c ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "mult $t1, $a3"
+  -
+    input:
+      bytes: [ 0x00, 0xe9, 0x9b, 0x3c ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "multu $t1, $a3"
+  -
+    input:
+      bytes: [ 0x00, 0xe9, 0xab, 0x3c ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "div $zero, $t1, $a3"
+  -
+    input:
+      bytes: [ 0x00, 0xe9, 0xbb, 0x3c ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "divu $zero, $t1, $a3"
diff --git a/tests/MC/Mips/micromips-alu-instructions.s.yaml b/tests/MC/Mips/micromips-alu-instructions.s.yaml
new file mode 100644
index 000000000..116479a58
--- /dev/null
+++ b/tests/MC/Mips/micromips-alu-instructions.s.yaml
@@ -0,0 +1,289 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xe6, 0x00, 0x10, 0x49 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "add $t1, $a2, $a3"
+  -
+    input:
+      bytes: [ 0x26, 0x11, 0x67, 0x45 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "addi $t1, $a2, 17767"
+  -
+    input:
+      bytes: [ 0x26, 0x31, 0x67, 0xc5 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "addiu $t1, $a2, -15001"
+  -
+    input:
+      bytes: [ 0x26, 0x11, 0x67, 0x45 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "addi $t1, $a2, 17767"
+  -
+    input:
+      bytes: [ 0x26, 0x31, 0x67, 0xc5 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "addiu $t1, $a2, -15001"
+  -
+    input:
+      bytes: [ 0xe6, 0x00, 0x50, 0x49 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "addu $t1, $a2, $a3"
+  -
+    input:
+      bytes: [ 0xe6, 0x00, 0x90, 0x49 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub $t1, $a2, $a3"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0xd0, 0x21 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "subu $a0, $v1, $a1"
+  -
+    input:
+      bytes: [ 0xe0, 0x00, 0x90, 0x31 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub $a2, $zero, $a3"
+  -
+    input:
+      bytes: [ 0xe0, 0x00, 0xd0, 0x31 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "subu $a2, $zero, $a3"
+  -
+    input:
+      bytes: [ 0x08, 0x00, 0x50, 0x39 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "addu $a3, $t0, $zero"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0x50, 0x1b ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "slt $v1, $v1, $a1"
+  -
+    input:
+      bytes: [ 0x63, 0x90, 0x67, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "slti $v1, $v1, 103"
+  -
+    input:
+      bytes: [ 0x63, 0x90, 0x67, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "slti $v1, $v1, 103"
+  -
+    input:
+      bytes: [ 0x63, 0xb0, 0x67, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "sltiu $v1, $v1, 103"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0x90, 0x1b ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "sltu $v1, $v1, $a1"
+  -
+    input:
+      bytes: [ 0xa9, 0x41, 0x67, 0x45 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "lui $t1, 17767"
+  -
+    input:
+      bytes: [ 0xe6, 0x00, 0x50, 0x4a ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "and $t1, $a2, $a3"
+  -
+    input:
+      bytes: [ 0x26, 0xd1, 0x67, 0x45 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "andi $t1, $a2, 17767"
+  -
+    input:
+      bytes: [ 0x26, 0xd1, 0x67, 0x45 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "andi $t1, $a2, 17767"
+  -
+    input:
+      bytes: [ 0xa4, 0x00, 0x90, 0x1a ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "or $v1, $a0, $a1"
+  -
+    input:
+      bytes: [ 0x26, 0x51, 0x67, 0x45 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "ori $t1, $a2, 17767"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0x10, 0x1b ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor $v1, $v1, $a1"
+  -
+    input:
+      bytes: [ 0x26, 0x71, 0x67, 0x45 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "xori $t1, $a2, 17767"
+  -
+    input:
+      bytes: [ 0x26, 0x71, 0x67, 0x45 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "xori $t1, $a2, 17767"
+  -
+    input:
+      bytes: [ 0xe6, 0x00, 0xd0, 0x4a ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "nor $t1, $a2, $a3"
+  -
+    input:
+      bytes: [ 0x08, 0x00, 0xd0, 0x3a ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "not $a3, $t0"
+  -
+    input:
+      bytes: [ 0xe6, 0x00, 0x10, 0x4a ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul $t1, $a2, $a3"
+  -
+    input:
+      bytes: [ 0xe9, 0x00, 0x3c, 0x8b ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "mult $t1, $a3"
+  -
+    input:
+      bytes: [ 0xe9, 0x00, 0x3c, 0x9b ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "multu $t1, $a3"
+  -
+    input:
+      bytes: [ 0xe9, 0x00, 0x3c, 0xab ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "div $zero, $t1, $a3"
+  -
+    input:
+      bytes: [ 0xe9, 0x00, 0x3c, 0xbb ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "divu $zero, $t1, $a3"
diff --git a/tests/MC/Mips/micromips-branch-instructions-EB.s.yaml b/tests/MC/Mips/micromips-branch-instructions-EB.s.yaml
new file mode 100644
index 000000000..019ad6229
--- /dev/null
+++ b/tests/MC/Mips/micromips-branch-instructions-EB.s.yaml
@@ -0,0 +1,82 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x94, 0x00, 0x02, 0x9a ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "b 1332"
+  -
+    input:
+      bytes: [ 0x94, 0xc9, 0x02, 0x9a ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "beq $t1, $a2, 1332"
+  -
+    input:
+      bytes: [ 0x40, 0x46, 0x02, 0x9a ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "bgez $a2, 1332"
+  -
+    input:
+      bytes: [ 0x40, 0x66, 0x02, 0x9a ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "bgezal $a2, 1332"
+  -
+    input:
+      bytes: [ 0x40, 0x26, 0x02, 0x9a ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "bltzal $a2, 1332"
+  -
+    input:
+      bytes: [ 0x40, 0xc6, 0x02, 0x9a ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "bgtz $a2, 1332"
+  -
+    input:
+      bytes: [ 0x40, 0x86, 0x02, 0x9a ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "blez $a2, 1332"
+  -
+    input:
+      bytes: [ 0xb4, 0xc9, 0x02, 0x9a ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "bne $t1, $a2, 1332"
+  -
+    input:
+      bytes: [ 0x40, 0x06, 0x02, 0x9a ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "bltz $a2, 1332"
diff --git a/tests/MC/Mips/micromips-branch-instructions.s.yaml b/tests/MC/Mips/micromips-branch-instructions.s.yaml
new file mode 100644
index 000000000..7da105943
--- /dev/null
+++ b/tests/MC/Mips/micromips-branch-instructions.s.yaml
@@ -0,0 +1,82 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x94, 0x9a, 0x02 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "b 1332"
+  -
+    input:
+      bytes: [ 0xc9, 0x94, 0x9a, 0x02 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "beq $t1, $a2, 1332"
+  -
+    input:
+      bytes: [ 0x46, 0x40, 0x9a, 0x02 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "bgez $a2, 1332"
+  -
+    input:
+      bytes: [ 0x66, 0x40, 0x9a, 0x02 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "bgezal $a2, 1332"
+  -
+    input:
+      bytes: [ 0x26, 0x40, 0x9a, 0x02 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "bltzal $a2, 1332"
+  -
+    input:
+      bytes: [ 0xc6, 0x40, 0x9a, 0x02 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "bgtz $a2, 1332"
+  -
+    input:
+      bytes: [ 0x86, 0x40, 0x9a, 0x02 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "blez $a2, 1332"
+  -
+    input:
+      bytes: [ 0xc9, 0xb4, 0x9a, 0x02 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "bne $t1, $a2, 1332"
+  -
+    input:
+      bytes: [ 0x06, 0x40, 0x9a, 0x02 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "bltz $a2, 1332"
diff --git a/tests/MC/Mips/micromips-expansions.s.yaml b/tests/MC/Mips/micromips-expansions.s.yaml
new file mode 100644
index 000000000..e28a7024d
--- /dev/null
+++ b/tests/MC/Mips/micromips-expansions.s.yaml
@@ -0,0 +1,163 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xa0, 0x50, 0x7b, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "ori $a1, $zero, 123"
+  -
+    input:
+      bytes: [ 0xc0, 0x30, 0xd7, 0xf6 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "addiu $a2, $zero, -2345"
+  -
+    input:
+      bytes: [ 0xa7, 0x41, 0x01, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "lui $a3, 1"
+  -
+    input:
+      bytes: [ 0xe7, 0x50, 0x02, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "ori $a3, $a3, 2"
+  -
+    input:
+      bytes: [ 0x80, 0x30, 0x14, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "addiu $a0, $zero, 20"
+  -
+    input:
+      bytes: [ 0xa7, 0x41, 0x01, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "lui $a3, 1"
+  -
+    input:
+      bytes: [ 0xe7, 0x50, 0x02, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "ori $a3, $a3, 2"
+  -
+    input:
+      bytes: [ 0x85, 0x30, 0x14, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "addiu $a0, $a1, 20"
+  -
+    input:
+      bytes: [ 0xa7, 0x41, 0x01, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "lui $a3, 1"
+  -
+    input:
+      bytes: [ 0xe7, 0x50, 0x02, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "ori $a3, $a3, 2"
+  -
+    input:
+      bytes: [ 0x07, 0x01, 0x50, 0x39 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "addu $a3, $a3, $t0"
+  -
+    input:
+      bytes: [ 0x8a, 0x00, 0x50, 0x51 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "addu $t2, $t2, $a0"
+  -
+    input:
+      bytes: [ 0x21, 0x01, 0x50, 0x09 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "addu $at, $at, $t1"
+  -
+    input:
+      bytes: [ 0xaa, 0x41, 0x0a, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "lui $t2, 10"
+  -
+    input:
+      bytes: [ 0x8a, 0x00, 0x50, 0x51 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "addu $t2, $t2, $a0"
+  -
+    input:
+      bytes: [ 0x4a, 0xfd, 0x7b, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "lw $t2, 123($t2)"
+  -
+    input:
+      bytes: [ 0xa1, 0x41, 0x02, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "lui $at, 2"
+  -
+    input:
+      bytes: [ 0x21, 0x01, 0x50, 0x09 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "addu $at, $at, $t1"
diff --git a/tests/MC/Mips/micromips-jump-instructions-EB.s.yaml b/tests/MC/Mips/micromips-jump-instructions-EB.s.yaml
new file mode 100644
index 000000000..b709a41cc
--- /dev/null
+++ b/tests/MC/Mips/micromips-jump-instructions-EB.s.yaml
@@ -0,0 +1,28 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xd4, 0x00, 0x02, 0x98 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "j 1328"
+  -
+    input:
+      bytes: [ 0xf4, 0x00, 0x02, 0x98 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "jal 1328"
+  -
+    input:
+      bytes: [ 0x00, 0x07, 0x0f, 0x3c ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "jr $a3"
diff --git a/tests/MC/Mips/micromips-jump-instructions.s.yaml b/tests/MC/Mips/micromips-jump-instructions.s.yaml
new file mode 100644
index 000000000..ed3eb4cf6
--- /dev/null
+++ b/tests/MC/Mips/micromips-jump-instructions.s.yaml
@@ -0,0 +1,37 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xd4, 0x98, 0x02 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "j 1328"
+  -
+    input:
+      bytes: [ 0x00, 0xf4, 0x98, 0x02 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "jal 1328"
+  -
+    input:
+      bytes: [ 0x07, 0x00, 0x3c, 0x0f ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "jr $a3"
+  -
+    input:
+      bytes: [ 0x07, 0x00, 0x3c, 0x0f ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "jr $a3"
diff --git a/tests/MC/Mips/micromips-loadstore-instructions-EB.s.yaml b/tests/MC/Mips/micromips-loadstore-instructions-EB.s.yaml
new file mode 100644
index 000000000..2040ea000
--- /dev/null
+++ b/tests/MC/Mips/micromips-loadstore-instructions-EB.s.yaml
@@ -0,0 +1,73 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x1c, 0xa4, 0x00, 0x08 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "lb $a1, 8($a0)"
+  -
+    input:
+      bytes: [ 0x14, 0xc4, 0x00, 0x08 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "lbu $a2, 8($a0)"
+  -
+    input:
+      bytes: [ 0x3c, 0x44, 0x00, 0x08 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "lh $v0, 8($a0)"
+  -
+    input:
+      bytes: [ 0x34, 0x82, 0x00, 0x08 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "lhu $a0, 8($v0)"
+  -
+    input:
+      bytes: [ 0xfc, 0xc5, 0x00, 0x04 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "lw $a2, 4($a1)"
+  -
+    input:
+      bytes: [ 0x18, 0xa4, 0x00, 0x08 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "sb $a1, 8($a0)"
+  -
+    input:
+      bytes: [ 0x38, 0x44, 0x00, 0x08 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh $v0, 8($a0)"
+  -
+    input:
+      bytes: [ 0xf8, 0xa6, 0x00, 0x04 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "sw $a1, 4($a2)"
diff --git a/tests/MC/Mips/micromips-loadstore-instructions.s.yaml b/tests/MC/Mips/micromips-loadstore-instructions.s.yaml
new file mode 100644
index 000000000..f87d7c990
--- /dev/null
+++ b/tests/MC/Mips/micromips-loadstore-instructions.s.yaml
@@ -0,0 +1,73 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xa4, 0x1c, 0x08, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "lb $a1, 8($a0)"
+  -
+    input:
+      bytes: [ 0xc4, 0x14, 0x08, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "lbu $a2, 8($a0)"
+  -
+    input:
+      bytes: [ 0x44, 0x3c, 0x08, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "lh $v0, 8($a0)"
+  -
+    input:
+      bytes: [ 0x82, 0x34, 0x08, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "lhu $a0, 8($v0)"
+  -
+    input:
+      bytes: [ 0xc5, 0xfc, 0x04, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "lw $a2, 4($a1)"
+  -
+    input:
+      bytes: [ 0xa4, 0x18, 0x08, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "sb $a1, 8($a0)"
+  -
+    input:
+      bytes: [ 0x44, 0x38, 0x08, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh $v0, 8($a0)"
+  -
+    input:
+      bytes: [ 0xa6, 0xf8, 0x04, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "sw $a1, 4($a2)"
diff --git a/tests/MC/Mips/micromips-loadstore-unaligned-EB.s.yaml b/tests/MC/Mips/micromips-loadstore-unaligned-EB.s.yaml
new file mode 100644
index 000000000..897c1d18d
--- /dev/null
+++ b/tests/MC/Mips/micromips-loadstore-unaligned-EB.s.yaml
@@ -0,0 +1,37 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x60, 0x85, 0x00, 0x10 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "lwl $a0, 16($a1)"
+  -
+    input:
+      bytes: [ 0x60, 0x85, 0x10, 0x10 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "lwr $a0, 16($a1)"
+  -
+    input:
+      bytes: [ 0x60, 0x85, 0x80, 0x10 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "swl $a0, 16($a1)"
+  -
+    input:
+      bytes: [ 0x60, 0x85, 0x90, 0x10 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "swr $a0, 16($a1)"
diff --git a/tests/MC/Mips/micromips-loadstore-unaligned.s.yaml b/tests/MC/Mips/micromips-loadstore-unaligned.s.yaml
new file mode 100644
index 000000000..b16e00f75
--- /dev/null
+++ b/tests/MC/Mips/micromips-loadstore-unaligned.s.yaml
@@ -0,0 +1,37 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x85, 0x60, 0x10, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "lwl $a0, 16($a1)"
+  -
+    input:
+      bytes: [ 0x85, 0x60, 0x10, 0x10 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "lwr $a0, 16($a1)"
+  -
+    input:
+      bytes: [ 0x85, 0x60, 0x10, 0x80 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "swl $a0, 16($a1)"
+  -
+    input:
+      bytes: [ 0x85, 0x60, 0x10, 0x90 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "swr $a0, 16($a1)"
diff --git a/tests/MC/Mips/micromips-movcond-instructions-EB.s.yaml b/tests/MC/Mips/micromips-movcond-instructions-EB.s.yaml
new file mode 100644
index 000000000..7559e3559
--- /dev/null
+++ b/tests/MC/Mips/micromips-movcond-instructions-EB.s.yaml
@@ -0,0 +1,37 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xe6, 0x48, 0x58 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "movz $t1, $a2, $a3"
+  -
+    input:
+      bytes: [ 0x00, 0xe6, 0x48, 0x18 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "movn $t1, $a2, $a3"
+  -
+    input:
+      bytes: [ 0x55, 0x26, 0x09, 0x7b ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "movt $t1, $a2, $fcc0"
+  -
+    input:
+      bytes: [ 0x55, 0x26, 0x01, 0x7b ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "movf $t1, $a2, $fcc0"
diff --git a/tests/MC/Mips/micromips-movcond-instructions.s.yaml b/tests/MC/Mips/micromips-movcond-instructions.s.yaml
new file mode 100644
index 000000000..4f091f156
--- /dev/null
+++ b/tests/MC/Mips/micromips-movcond-instructions.s.yaml
@@ -0,0 +1,37 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xe6, 0x00, 0x58, 0x48 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "movz $t1, $a2, $a3"
+  -
+    input:
+      bytes: [ 0xe6, 0x00, 0x18, 0x48 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "movn $t1, $a2, $a3"
+  -
+    input:
+      bytes: [ 0x26, 0x55, 0x7b, 0x09 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "movt $t1, $a2, $fcc0"
+  -
+    input:
+      bytes: [ 0x26, 0x55, 0x7b, 0x01 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "movf $t1, $a2, $fcc0"
diff --git a/tests/MC/Mips/micromips-multiply-instructions-EB.s.yaml b/tests/MC/Mips/micromips-multiply-instructions-EB.s.yaml
new file mode 100644
index 000000000..f5d5e1ebd
--- /dev/null
+++ b/tests/MC/Mips/micromips-multiply-instructions-EB.s.yaml
@@ -0,0 +1,37 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0xa4, 0xcb, 0x3c ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd $a0, $a1"
+  -
+    input:
+      bytes: [ 0x00, 0xa4, 0xdb, 0x3c ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddu $a0, $a1"
+  -
+    input:
+      bytes: [ 0x00, 0xa4, 0xeb, 0x3c ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub $a0, $a1"
+  -
+    input:
+      bytes: [ 0x00, 0xa4, 0xfb, 0x3c ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubu $a0, $a1"
diff --git a/tests/MC/Mips/micromips-multiply-instructions.s.yaml b/tests/MC/Mips/micromips-multiply-instructions.s.yaml
new file mode 100644
index 000000000..743106a28
--- /dev/null
+++ b/tests/MC/Mips/micromips-multiply-instructions.s.yaml
@@ -0,0 +1,37 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xa4, 0x00, 0x3c, 0xcb ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd $a0, $a1"
+  -
+    input:
+      bytes: [ 0xa4, 0x00, 0x3c, 0xdb ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddu $a0, $a1"
+  -
+    input:
+      bytes: [ 0xa4, 0x00, 0x3c, 0xeb ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub $a0, $a1"
+  -
+    input:
+      bytes: [ 0xa4, 0x00, 0x3c, 0xfb ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubu $a0, $a1"
diff --git a/tests/MC/Mips/micromips-shift-instructions-EB.s.yaml b/tests/MC/Mips/micromips-shift-instructions-EB.s.yaml
new file mode 100644
index 000000000..c833369cf
--- /dev/null
+++ b/tests/MC/Mips/micromips-shift-instructions-EB.s.yaml
@@ -0,0 +1,73 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x83, 0x38, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "sll $a0, $v1, 7"
+  -
+    input:
+      bytes: [ 0x00, 0x65, 0x10, 0x10 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "sllv $v0, $v1, $a1"
+  -
+    input:
+      bytes: [ 0x00, 0x83, 0x38, 0x80 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "sra $a0, $v1, 7"
+  -
+    input:
+      bytes: [ 0x00, 0x65, 0x10, 0x90 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "srav $v0, $v1, $a1"
+  -
+    input:
+      bytes: [ 0x00, 0x83, 0x38, 0x40 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "srl $a0, $v1, 7"
+  -
+    input:
+      bytes: [ 0x00, 0x65, 0x10, 0x50 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "srlv $v0, $v1, $a1"
+  -
+    input:
+      bytes: [ 0x01, 0x26, 0x38, 0xc0 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "rotr $t1, $a2, 7"
+  -
+    input:
+      bytes: [ 0x00, 0xc7, 0x48, 0xd0 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "rotrv $t1, $a2, $a3"
diff --git a/tests/MC/Mips/micromips-shift-instructions.s.yaml b/tests/MC/Mips/micromips-shift-instructions.s.yaml
new file mode 100644
index 000000000..cc8e0d4b1
--- /dev/null
+++ b/tests/MC/Mips/micromips-shift-instructions.s.yaml
@@ -0,0 +1,73 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0x00, 0x38 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "sll $a0, $v1, 7"
+  -
+    input:
+      bytes: [ 0x65, 0x00, 0x10, 0x10 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "sllv $v0, $v1, $a1"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0x80, 0x38 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "sra $a0, $v1, 7"
+  -
+    input:
+      bytes: [ 0x65, 0x00, 0x90, 0x10 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "srav $v0, $v1, $a1"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0x40, 0x38 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "srl $a0, $v1, 7"
+  -
+    input:
+      bytes: [ 0x65, 0x00, 0x50, 0x10 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "srlv $v0, $v1, $a1"
+  -
+    input:
+      bytes: [ 0x26, 0x01, 0xc0, 0x38 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "rotr $t1, $a2, 7"
+  -
+    input:
+      bytes: [ 0xc7, 0x00, 0xd0, 0x48 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "rotrv $t1, $a2, $a3"
diff --git a/tests/MC/Mips/micromips-trap-instructions-EB.s.yaml b/tests/MC/Mips/micromips-trap-instructions-EB.s.yaml
new file mode 100644
index 000000000..9f83c760d
--- /dev/null
+++ b/tests/MC/Mips/micromips-trap-instructions-EB.s.yaml
@@ -0,0 +1,55 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x41, 0xc9, 0x45, 0x67 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "teqi $t1, 17767"
+  -
+    input:
+      bytes: [ 0x41, 0x29, 0x45, 0x67 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "tgei $t1, 17767"
+  -
+    input:
+      bytes: [ 0x41, 0x69, 0x45, 0x67 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "tgeiu $t1, 17767"
+  -
+    input:
+      bytes: [ 0x41, 0x09, 0x45, 0x67 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "tlti $t1, 17767"
+  -
+    input:
+      bytes: [ 0x41, 0x49, 0x45, 0x67 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "tltiu $t1, 17767"
+  -
+    input:
+      bytes: [ 0x41, 0x89, 0x45, 0x67 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "tnei $t1, 17767"
diff --git a/tests/MC/Mips/micromips-trap-instructions.s.yaml b/tests/MC/Mips/micromips-trap-instructions.s.yaml
new file mode 100644
index 000000000..7b6cb8c7c
--- /dev/null
+++ b/tests/MC/Mips/micromips-trap-instructions.s.yaml
@@ -0,0 +1,55 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xc9, 0x41, 0x67, 0x45 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "teqi $t1, 17767"
+  -
+    input:
+      bytes: [ 0x29, 0x41, 0x67, 0x45 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "tgei $t1, 17767"
+  -
+    input:
+      bytes: [ 0x69, 0x41, 0x67, 0x45 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "tgeiu $t1, 17767"
+  -
+    input:
+      bytes: [ 0x09, 0x41, 0x67, 0x45 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "tlti $t1, 17767"
+  -
+    input:
+      bytes: [ 0x49, 0x41, 0x67, 0x45 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "tltiu $t1, 17767"
+  -
+    input:
+      bytes: [ 0x89, 0x41, 0x67, 0x45 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_MICRO" ]
+    expected:
+      insns:
+        -
+          asm_text: "tnei $t1, 17767"
diff --git a/tests/MC/Mips/mips-alu-instructions.s.yaml b/tests/MC/Mips/mips-alu-instructions.s.yaml
new file mode 100644
index 000000000..bf9dbc82c
--- /dev/null
+++ b/tests/MC/Mips/mips-alu-instructions.s.yaml
@@ -0,0 +1,469 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x24, 0x48, 0xc7, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "and $t1, $a2, $a3"
+  -
+    input:
+      bytes: [ 0x67, 0x45, 0xc9, 0x30 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "andi $t1, $a2, 17767"
+  -
+    input:
+      bytes: [ 0x67, 0x45, 0xc9, 0x30 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "andi $t1, $a2, 17767"
+  -
+    input:
+      bytes: [ 0x67, 0x45, 0x29, 0x31 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "andi $t1, $t1, 17767"
+  -
+    input:
+      bytes: [ 0x21, 0x30, 0xe6, 0x70 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "clo $a2, $a3"
+  -
+    input:
+      bytes: [ 0x20, 0x30, 0xe6, 0x70 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "clz $a2, $a3"
+  -
+    input:
+      bytes: [ 0x84, 0x61, 0x33, 0x7d ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "ins $s3, $t1, 6, 7"
+  -
+    input:
+      bytes: [ 0x27, 0x48, 0xc7, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "nor $t1, $a2, $a3"
+  -
+    input:
+      bytes: [ 0x25, 0x18, 0x65, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "or $v1, $v1, $a1"
+  -
+    input:
+      bytes: [ 0x67, 0x45, 0xa4, 0x34 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "ori $a0, $a1, 17767"
+  -
+    input:
+      bytes: [ 0x67, 0x45, 0xc9, 0x34 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "ori $t1, $a2, 17767"
+  -
+    input:
+      bytes: [ 0x80, 0x00, 0x6b, 0x35 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "ori $t3, $t3, 128"
+  -
+    input:
+      bytes: [ 0xc2, 0x49, 0x26, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "rotr $t1, $a2, 7"
+  -
+    input:
+      bytes: [ 0x46, 0x48, 0xe6, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "rotrv $t1, $a2, $a3"
+  -
+    input:
+      bytes: [ 0xc0, 0x21, 0x03, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "sll $a0, $v1, 7"
+  -
+    input:
+      bytes: [ 0x04, 0x10, 0xa3, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "sllv $v0, $v1, $a1"
+  -
+    input:
+      bytes: [ 0x2a, 0x18, 0x65, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "slt $v1, $v1, $a1"
+  -
+    input:
+      bytes: [ 0x67, 0x00, 0x63, 0x28 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "slti $v1, $v1, 103"
+  -
+    input:
+      bytes: [ 0x67, 0x00, 0x63, 0x28 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "slti $v1, $v1, 103"
+  -
+    input:
+      bytes: [ 0x67, 0x00, 0x63, 0x2c ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "sltiu $v1, $v1, 103"
+  -
+    input:
+      bytes: [ 0x2b, 0x18, 0x65, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "sltu $v1, $v1, $a1"
+  -
+    input:
+      bytes: [ 0xc3, 0x21, 0x03, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "sra $a0, $v1, 7"
+  -
+    input:
+      bytes: [ 0x07, 0x10, 0xa3, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "srav $v0, $v1, $a1"
+  -
+    input:
+      bytes: [ 0xc2, 0x21, 0x03, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "srl $a0, $v1, 7"
+  -
+    input:
+      bytes: [ 0x06, 0x10, 0xa3, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "srlv $v0, $v1, $a1"
+  -
+    input:
+      bytes: [ 0x26, 0x18, 0x65, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor $v1, $v1, $a1"
+  -
+    input:
+      bytes: [ 0x67, 0x45, 0xc9, 0x38 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "xori $t1, $a2, 17767"
+  -
+    input:
+      bytes: [ 0x67, 0x45, 0xc9, 0x38 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "xori $t1, $a2, 17767"
+  -
+    input:
+      bytes: [ 0x0c, 0x00, 0x6b, 0x39 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "xori $t3, $t3, 12"
+  -
+    input:
+      bytes: [ 0xa0, 0x30, 0x07, 0x7c ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "wsbh $a2, $a3"
+  -
+    input:
+      bytes: [ 0x27, 0x38, 0x00, 0x01 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "not $a3, $t0"
+  -
+    input:
+      bytes: [ 0x20, 0x48, 0xc7, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "add $t1, $a2, $a3"
+  -
+    input:
+      bytes: [ 0x67, 0x45, 0xc9, 0x20 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "addi $t1, $a2, 17767"
+  -
+    input:
+      bytes: [ 0x67, 0xc5, 0xc9, 0x24 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "addiu $t1, $a2, -15001"
+  -
+    input:
+      bytes: [ 0x67, 0x45, 0xc9, 0x20 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "addi $t1, $a2, 17767"
+  -
+    input:
+      bytes: [ 0x67, 0x45, 0x29, 0x21 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "addi $t1, $t1, 17767"
+  -
+    input:
+      bytes: [ 0x67, 0xc5, 0xc9, 0x24 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "addiu $t1, $a2, -15001"
+  -
+    input:
+      bytes: [ 0x28, 0x00, 0x6b, 0x25 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "addiu $t3, $t3, 40"
+  -
+    input:
+      bytes: [ 0x21, 0x48, 0xc7, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "addu $t1, $a2, $a3"
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0xc7, 0x70 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd $a2, $a3"
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0xc7, 0x70 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddu $a2, $a3"
+  -
+    input:
+      bytes: [ 0x04, 0x00, 0xc7, 0x70 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub $a2, $a3"
+  -
+    input:
+      bytes: [ 0x05, 0x00, 0xc7, 0x70 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubu $a2, $a3"
+  -
+    input:
+      bytes: [ 0x18, 0x00, 0x65, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "mult $v1, $a1"
+  -
+    input:
+      bytes: [ 0x19, 0x00, 0x65, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "multu $v1, $a1"
+  -
+    input:
+      bytes: [ 0x22, 0x48, 0xc7, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub $t1, $a2, $a3"
+  -
+    input:
+      bytes: [ 0xc8, 0xff, 0xbd, 0x23 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "addi $sp, $sp, -56"
+  -
+    input:
+      bytes: [ 0x23, 0x20, 0x65, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "subu $a0, $v1, $a1"
+  -
+    input:
+      bytes: [ 0xd8, 0xff, 0xbd, 0x27 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "addiu $sp, $sp, -40"
+  -
+    input:
+      bytes: [ 0x22, 0x30, 0x07, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "neg $a2, $a3"
+  -
+    input:
+      bytes: [ 0x23, 0x30, 0x07, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "negu $a2, $a3"
+  -
+    input:
+      bytes: [ 0x21, 0x38, 0x00, 0x01 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "move $a3, $t0"
diff --git a/tests/MC/Mips/mips-control-instructions-64.s.yaml b/tests/MC/Mips/mips-control-instructions-64.s.yaml
new file mode 100644
index 000000000..4986ca48b
--- /dev/null
+++ b/tests/MC/Mips/mips-control-instructions-64.s.yaml
@@ -0,0 +1,280 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x00, 0x0d ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "break"
+  -
+    input:
+      bytes: [ 0x00, 0x07, 0x01, 0x4d ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "break 7, 5"
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x00, 0x0c ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "syscall"
+  -
+    input:
+      bytes: [ 0x00, 0x0d, 0x15, 0x0c ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "syscall 13396"
+  -
+    input:
+      bytes: [ 0x42, 0x00, 0x00, 0x18 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "eret"
+  -
+    input:
+      bytes: [ 0x42, 0x00, 0x00, 0x1f ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "deret"
+  -
+    input:
+      bytes: [ 0x41, 0x60, 0x60, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "di"
+  -
+    input:
+      bytes: [ 0x41, 0x60, 0x60, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "di"
+  -
+    input:
+      bytes: [ 0x41, 0x6a, 0x60, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "di $t2"
+  -
+    input:
+      bytes: [ 0x41, 0x60, 0x60, 0x20 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "ei"
+  -
+    input:
+      bytes: [ 0x41, 0x60, 0x60, 0x20 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "ei"
+  -
+    input:
+      bytes: [ 0x41, 0x6a, 0x60, 0x20 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "ei $t2"
+  -
+    input:
+      bytes: [ 0x42, 0x00, 0x00, 0x20 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "wait"
+  -
+    input:
+      bytes: [ 0x00, 0x03, 0x00, 0x34 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "teq $zero, $v1"
+  -
+    input:
+      bytes: [ 0x00, 0x03, 0x00, 0x74 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "teq $zero, $v1, 1"
+  -
+    input:
+      bytes: [ 0x04, 0x6c, 0x00, 0x01 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "teqi $v1, 1"
+  -
+    input:
+      bytes: [ 0x00, 0x03, 0x00, 0x30 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "tge $zero, $v1"
+  -
+    input:
+      bytes: [ 0x00, 0x03, 0x00, 0xf0 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "tge $zero, $v1, 3"
+  -
+    input:
+      bytes: [ 0x04, 0x68, 0x00, 0x03 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "tgei $v1, 3"
+  -
+    input:
+      bytes: [ 0x00, 0x03, 0x00, 0x31 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "tgeu $zero, $v1"
+  -
+    input:
+      bytes: [ 0x00, 0x03, 0x01, 0xf1 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "tgeu $zero, $v1, 7"
+  -
+    input:
+      bytes: [ 0x04, 0x69, 0x00, 0x07 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "tgeiu $v1, 7"
+  -
+    input:
+      bytes: [ 0x00, 0x03, 0x00, 0x32 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "tlt $zero, $v1"
+  -
+    input:
+      bytes: [ 0x00, 0x03, 0x07, 0xf2 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "tlt $zero, $v1, 31"
+  -
+    input:
+      bytes: [ 0x04, 0x6a, 0x00, 0x1f ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "tlti $v1, 31"
+  -
+    input:
+      bytes: [ 0x00, 0x03, 0x00, 0x33 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "tltu $zero, $v1"
+  -
+    input:
+      bytes: [ 0x00, 0x03, 0x3f, 0xf3 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "tltu $zero, $v1, 255"
+  -
+    input:
+      bytes: [ 0x04, 0x6b, 0x00, 0xff ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "tltiu $v1, 255"
+  -
+    input:
+      bytes: [ 0x00, 0x03, 0x00, 0x36 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "tne $zero, $v1"
+  -
+    input:
+      bytes: [ 0x00, 0x03, 0xff, 0xf6 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "tne $zero, $v1, 1023"
+  -
+    input:
+      bytes: [ 0x04, 0x6e, 0x03, 0xff ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "tnei $v1, 1023"
diff --git a/tests/MC/Mips/mips-control-instructions.s.yaml b/tests/MC/Mips/mips-control-instructions.s.yaml
new file mode 100644
index 000000000..b526a9833
--- /dev/null
+++ b/tests/MC/Mips/mips-control-instructions.s.yaml
@@ -0,0 +1,280 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x00, 0x0d ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "break"
+  -
+    input:
+      bytes: [ 0x00, 0x07, 0x01, 0x4d ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "break 7, 5"
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x00, 0x0c ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "syscall"
+  -
+    input:
+      bytes: [ 0x00, 0x0d, 0x15, 0x0c ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "syscall 13396"
+  -
+    input:
+      bytes: [ 0x42, 0x00, 0x00, 0x18 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "eret"
+  -
+    input:
+      bytes: [ 0x42, 0x00, 0x00, 0x1f ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "deret"
+  -
+    input:
+      bytes: [ 0x41, 0x60, 0x60, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "di"
+  -
+    input:
+      bytes: [ 0x41, 0x60, 0x60, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "di"
+  -
+    input:
+      bytes: [ 0x41, 0x6a, 0x60, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "di $t2"
+  -
+    input:
+      bytes: [ 0x41, 0x60, 0x60, 0x20 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ei"
+  -
+    input:
+      bytes: [ 0x41, 0x60, 0x60, 0x20 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ei"
+  -
+    input:
+      bytes: [ 0x41, 0x6a, 0x60, 0x20 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ei $t2"
+  -
+    input:
+      bytes: [ 0x42, 0x00, 0x00, 0x20 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "wait"
+  -
+    input:
+      bytes: [ 0x00, 0x03, 0x00, 0x34 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "teq $zero, $v1"
+  -
+    input:
+      bytes: [ 0x00, 0x03, 0x00, 0x74 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "teq $zero, $v1, 1"
+  -
+    input:
+      bytes: [ 0x04, 0x6c, 0x00, 0x01 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "teqi $v1, 1"
+  -
+    input:
+      bytes: [ 0x00, 0x03, 0x00, 0x30 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "tge $zero, $v1"
+  -
+    input:
+      bytes: [ 0x00, 0x03, 0x00, 0xf0 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "tge $zero, $v1, 3"
+  -
+    input:
+      bytes: [ 0x04, 0x68, 0x00, 0x03 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "tgei $v1, 3"
+  -
+    input:
+      bytes: [ 0x00, 0x03, 0x00, 0x31 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "tgeu $zero, $v1"
+  -
+    input:
+      bytes: [ 0x00, 0x03, 0x01, 0xf1 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "tgeu $zero, $v1, 7"
+  -
+    input:
+      bytes: [ 0x04, 0x69, 0x00, 0x07 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "tgeiu $v1, 7"
+  -
+    input:
+      bytes: [ 0x00, 0x03, 0x00, 0x32 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "tlt $zero, $v1"
+  -
+    input:
+      bytes: [ 0x00, 0x03, 0x07, 0xf2 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "tlt $zero, $v1, 31"
+  -
+    input:
+      bytes: [ 0x04, 0x6a, 0x00, 0x1f ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "tlti $v1, 31"
+  -
+    input:
+      bytes: [ 0x00, 0x03, 0x00, 0x33 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "tltu $zero, $v1"
+  -
+    input:
+      bytes: [ 0x00, 0x03, 0x3f, 0xf3 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "tltu $zero, $v1, 255"
+  -
+    input:
+      bytes: [ 0x04, 0x6b, 0x00, 0xff ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "tltiu $v1, 255"
+  -
+    input:
+      bytes: [ 0x00, 0x03, 0x00, 0x36 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "tne $zero, $v1"
+  -
+    input:
+      bytes: [ 0x00, 0x03, 0xff, 0xf6 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "tne $zero, $v1, 1023"
+  -
+    input:
+      bytes: [ 0x04, 0x6e, 0x03, 0xff ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "tnei $v1, 1023"
diff --git a/tests/MC/Mips/mips-coprocessor-encodings.s.yaml b/tests/MC/Mips/mips-coprocessor-encodings.s.yaml
new file mode 100644
index 000000000..805d490ac
--- /dev/null
+++ b/tests/MC/Mips/mips-coprocessor-encodings.s.yaml
@@ -0,0 +1,145 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x40, 0xac, 0x80, 0x02 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "dmtc0 $t4, $s0, 2"
+  -
+    input:
+      bytes: [ 0x40, 0xac, 0x80, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "dmtc0 $t4, $s0, 0"
+  -
+    input:
+      bytes: [ 0x40, 0x8c, 0x80, 0x02 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "mtc0 $t4, $s0, 2"
+  -
+    input:
+      bytes: [ 0x40, 0x8c, 0x80, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "mtc0 $t4, $s0, 0"
+  -
+    input:
+      bytes: [ 0x40, 0x2c, 0x80, 0x02 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "dmfc0 $t4, $s0, 2"
+  -
+    input:
+      bytes: [ 0x40, 0x2c, 0x80, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "dmfc0 $t4, $s0, 0"
+  -
+    input:
+      bytes: [ 0x40, 0x0c, 0x80, 0x02 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "mfc0 $t4, $s0, 2"
+  -
+    input:
+      bytes: [ 0x40, 0x0c, 0x80, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "mfc0 $t4, $s0, 0"
+  -
+    input:
+      bytes: [ 0x48, 0xac, 0x80, 0x02 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "dmtc2 $t4, $s0, 2"
+  -
+    input:
+      bytes: [ 0x48, 0xac, 0x80, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "dmtc2 $t4, $s0, 0"
+  -
+    input:
+      bytes: [ 0x48, 0x8c, 0x80, 0x02 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "mtc2 $t4, $s0, 2"
+  -
+    input:
+      bytes: [ 0x48, 0x8c, 0x80, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "mtc2 $t4, $s0, 0"
+  -
+    input:
+      bytes: [ 0x48, 0x2c, 0x80, 0x02 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "dmfc2 $t4, $s0, 2"
+  -
+    input:
+      bytes: [ 0x48, 0x2c, 0x80, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "dmfc2 $t4, $s0, 0"
+  -
+    input:
+      bytes: [ 0x48, 0x0c, 0x80, 0x02 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "mfc2 $t4, $s0, 2"
+  -
+    input:
+      bytes: [ 0x48, 0x0c, 0x80, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "mfc2 $t4, $s0, 0"
diff --git a/tests/MC/Mips/mips-dsp-instructions.s.yaml b/tests/MC/Mips/mips-dsp-instructions.s.yaml
new file mode 100644
index 000000000..e986d707b
--- /dev/null
+++ b/tests/MC/Mips/mips-dsp-instructions.s.yaml
@@ -0,0 +1,343 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x7e, 0x32, 0x83, 0x11 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "precrq.qb.ph $s0, $s1, $s2"
+  -
+    input:
+      bytes: [ 0x7e, 0x53, 0x8d, 0x11 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "precrq.ph.w $s1, $s2, $s3"
+  -
+    input:
+      bytes: [ 0x7e, 0x74, 0x95, 0x51 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "precrq_rs.ph.w $s2, $s3, $s4"
+  -
+    input:
+      bytes: [ 0x7e, 0x95, 0x9b, 0xd1 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "precrqu_s.qb.ph $s3, $s4, $s5"
+  -
+    input:
+      bytes: [ 0x7c, 0x15, 0xa3, 0x12 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "preceq.w.phl $s4, $s5"
+  -
+    input:
+      bytes: [ 0x7c, 0x16, 0xab, 0x52 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "preceq.w.phr $s5, $s6"
+  -
+    input:
+      bytes: [ 0x7c, 0x17, 0xb1, 0x12 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "precequ.ph.qbl $s6, $s7"
+  -
+    input:
+      bytes: [ 0x7c, 0x18, 0xb9, 0x52 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "precequ.ph.qbr $s7, $t8"
+  -
+    input:
+      bytes: [ 0x7c, 0x19, 0xc1, 0x92 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "precequ.ph.qbla $t8, $t9"
+  -
+    input:
+      bytes: [ 0x7c, 0x1a, 0xc9, 0xd2 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "precequ.ph.qbra $t9, $k0"
+  -
+    input:
+      bytes: [ 0x7c, 0x1b, 0xd7, 0x12 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "preceu.ph.qbl $k0, $k1"
+  -
+    input:
+      bytes: [ 0x7c, 0x1c, 0xdf, 0x52 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "preceu.ph.qbr $k1, $gp"
+  -
+    input:
+      bytes: [ 0x7c, 0x1d, 0xe7, 0x92 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "preceu.ph.qbla $gp, $sp"
+  -
+    input:
+      bytes: [ 0x7c, 0x1e, 0xef, 0xd2 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "preceu.ph.qbra $sp, $fp"
+  -
+    input:
+      bytes: [ 0x7f, 0x19, 0xbb, 0x51 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "precr.qb.ph $s7, $t8, $t9"
+  -
+    input:
+      bytes: [ 0x7f, 0x38, 0x07, 0x91 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "precr_sra.ph.w $t8, $t9, 0"
+  -
+    input:
+      bytes: [ 0x7f, 0x38, 0xff, 0x91 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "precr_sra.ph.w $t8, $t9, 31"
+  -
+    input:
+      bytes: [ 0x7f, 0x59, 0x07, 0xd1 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "precr_sra_r.ph.w $t9, $k0, 0"
+  -
+    input:
+      bytes: [ 0x7f, 0x59, 0xff, 0xd1 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "precr_sra_r.ph.w $t9, $k0, 31"
+  -
+    input:
+      bytes: [ 0x7f, 0x54, 0x51, 0x8a ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "lbux $t2, $s4($k0)"
+  -
+    input:
+      bytes: [ 0x7f, 0x75, 0x59, 0x0a ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "lhx $t3, $s5($k1)"
+  -
+    input:
+      bytes: [ 0x7f, 0x96, 0x60, 0x0a ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "lwx $t4, $s6($gp)"
+  -
+    input:
+      bytes: [ 0x00, 0x43, 0x18, 0x18 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mult $ac3, $v0, $v1"
+  -
+    input:
+      bytes: [ 0x00, 0x85, 0x10, 0x19 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "multu $ac2, $a0, $a1"
+  -
+    input:
+      bytes: [ 0x70, 0xc7, 0x08, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd $ac1, $a2, $a3"
+  -
+    input:
+      bytes: [ 0x71, 0x4b, 0x18, 0x04 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub $ac3, $t2, $t3"
+  -
+    input:
+      bytes: [ 0x71, 0x8d, 0x10, 0x05 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubu $ac2, $t4, $t5"
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x70, 0x10 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mfhi $t6, $ac1"
+  -
+    input:
+      bytes: [ 0x02, 0x00, 0x18, 0x11 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mthi $s0, $ac3"
+  -
+    input:
+      bytes: [ 0x02, 0x20, 0x10, 0x13 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mtlo $s1, $ac2"
+  -
+    input:
+      bytes: [ 0x00, 0x43, 0x00, 0x18 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mult $v0, $v1"
+  -
+    input:
+      bytes: [ 0x00, 0x85, 0x00, 0x19 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "multu $a0, $a1"
+  -
+    input:
+      bytes: [ 0x70, 0xc7, 0x00, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd $a2, $a3"
+  -
+    input:
+      bytes: [ 0x71, 0x4b, 0x00, 0x04 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub $t2, $t3"
+  -
+    input:
+      bytes: [ 0x71, 0x8d, 0x00, 0x05 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubu $t4, $t5"
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x70, 0x10 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mfhi $t6"
+  -
+    input:
+      bytes: [ 0x02, 0x00, 0x00, 0x11 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mthi $s0"
+  -
+    input:
+      bytes: [ 0x02, 0x20, 0x00, 0x13 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mtlo $s1"
diff --git a/tests/MC/Mips/mips-expansions.s.yaml b/tests/MC/Mips/mips-expansions.s.yaml
new file mode 100644
index 000000000..b52e9eba5
--- /dev/null
+++ b/tests/MC/Mips/mips-expansions.s.yaml
@@ -0,0 +1,154 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x7b, 0x00, 0x05, 0x34 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "ori $a1, $zero, 123"
+  -
+    input:
+      bytes: [ 0xd7, 0xf6, 0x06, 0x24 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "addiu $a2, $zero, -2345"
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0x07, 0x3c ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "lui $a3, 1"
+  -
+    input:
+      bytes: [ 0x02, 0x00, 0xe7, 0x34 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "ori $a3, $a3, 2"
+  -
+    input:
+      bytes: [ 0x14, 0x00, 0x04, 0x24 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "addiu $a0, $zero, 20"
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0x07, 0x3c ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "lui $a3, 1"
+  -
+    input:
+      bytes: [ 0x02, 0x00, 0xe7, 0x34 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "ori $a3, $a3, 2"
+  -
+    input:
+      bytes: [ 0x14, 0x00, 0xa4, 0x24 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "addiu $a0, $a1, 20"
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0x07, 0x3c ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "lui $a3, 1"
+  -
+    input:
+      bytes: [ 0x02, 0x00, 0xe7, 0x34 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "ori $a3, $a3, 2"
+  -
+    input:
+      bytes: [ 0x21, 0x38, 0xe8, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "addu $a3, $a3, $t0"
+  -
+    input:
+      bytes: [ 0x21, 0x50, 0x44, 0x01 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "addu $t2, $t2, $a0"
+  -
+    input:
+      bytes: [ 0x21, 0x08, 0x29, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "addu $at, $at, $t1"
+  -
+    input:
+      bytes: [ 0x0a, 0x00, 0x0a, 0x3c ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "lui $t2, 10"
+  -
+    input:
+      bytes: [ 0x7b, 0x00, 0x4a, 0x8d ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "lw $t2, 123($t2)"
+  -
+    input:
+      bytes: [ 0x02, 0x00, 0x01, 0x3c ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "lui $at, 2"
+  -
+    input:
+      bytes: [ 0x21, 0x08, 0x29, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "addu $at, $at, $t1"
diff --git a/tests/MC/Mips/mips-fpu-instructions.s.yaml b/tests/MC/Mips/mips-fpu-instructions.s.yaml
new file mode 100644
index 000000000..0ff331ea6
--- /dev/null
+++ b/tests/MC/Mips/mips-fpu-instructions.s.yaml
@@ -0,0 +1,829 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x05, 0x73, 0x20, 0x46 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "abs.d $f12, $f14"
+  -
+    input:
+      bytes: [ 0x85, 0x39, 0x00, 0x46 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "abs.s $f6, $f7"
+  -
+    input:
+      bytes: [ 0x00, 0x62, 0x2e, 0x46 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "add.d $f8, $f12, $f14"
+  -
+    input:
+      bytes: [ 0x40, 0x32, 0x07, 0x46 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "add.s $f9, $f6, $f7"
+  -
+    input:
+      bytes: [ 0x0f, 0x73, 0x20, 0x46 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "floor.w.d $f12, $f14"
+  -
+    input:
+      bytes: [ 0x8f, 0x39, 0x00, 0x46 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "floor.w.s $f6, $f7"
+  -
+    input:
+      bytes: [ 0x0e, 0x73, 0x20, 0x46 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "ceil.w.d $f12, $f14"
+  -
+    input:
+      bytes: [ 0x8e, 0x39, 0x00, 0x46 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "ceil.w.s $f6, $f7"
+  -
+    input:
+      bytes: [ 0x02, 0x62, 0x2e, 0x46 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.d $f8, $f12, $f14"
+  -
+    input:
+      bytes: [ 0x42, 0x32, 0x07, 0x46 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.s $f9, $f6, $f7"
+  -
+    input:
+      bytes: [ 0x07, 0x73, 0x20, 0x46 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "neg.d $f12, $f14"
+  -
+    input:
+      bytes: [ 0x87, 0x39, 0x00, 0x46 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "neg.s $f6, $f7"
+  -
+    input:
+      bytes: [ 0x0c, 0x73, 0x20, 0x46 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "round.w.d $f12, $f14"
+  -
+    input:
+      bytes: [ 0x8c, 0x39, 0x00, 0x46 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "round.w.s $f6, $f7"
+  -
+    input:
+      bytes: [ 0x04, 0x73, 0x20, 0x46 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrt.d $f12, $f14"
+  -
+    input:
+      bytes: [ 0x84, 0x39, 0x00, 0x46 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "sqrt.s $f6, $f7"
+  -
+    input:
+      bytes: [ 0x01, 0x62, 0x2e, 0x46 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub.d $f8, $f12, $f14"
+  -
+    input:
+      bytes: [ 0x41, 0x32, 0x07, 0x46 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub.s $f9, $f6, $f7"
+  -
+    input:
+      bytes: [ 0x0d, 0x73, 0x20, 0x46 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "trunc.w.d $f12, $f14"
+  -
+    input:
+      bytes: [ 0x8d, 0x39, 0x00, 0x46 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "trunc.w.s $f6, $f7"
+  -
+    input:
+      bytes: [ 0x32, 0x60, 0x2e, 0x46 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "c.eq.d $f12, $f14"
+  -
+    input:
+      bytes: [ 0x32, 0x30, 0x07, 0x46 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "c.eq.s $f6, $f7"
+  -
+    input:
+      bytes: [ 0x30, 0x60, 0x2e, 0x46 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "c.f.d $f12, $f14"
+  -
+    input:
+      bytes: [ 0x30, 0x30, 0x07, 0x46 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "c.f.s $f6, $f7"
+  -
+    input:
+      bytes: [ 0x3e, 0x60, 0x2e, 0x46 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "c.le.d $f12, $f14"
+  -
+    input:
+      bytes: [ 0x3e, 0x30, 0x07, 0x46 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "c.le.s $f6, $f7"
+  -
+    input:
+      bytes: [ 0x3c, 0x60, 0x2e, 0x46 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "c.lt.d $f12, $f14"
+  -
+    input:
+      bytes: [ 0x3c, 0x30, 0x07, 0x46 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "c.lt.s $f6, $f7"
+  -
+    input:
+      bytes: [ 0x3d, 0x60, 0x2e, 0x46 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "c.nge.d $f12, $f14"
+  -
+    input:
+      bytes: [ 0x3d, 0x30, 0x07, 0x46 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "c.nge.s $f6, $f7"
+  -
+    input:
+      bytes: [ 0x3b, 0x60, 0x2e, 0x46 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "c.ngl.d $f12, $f14"
+  -
+    input:
+      bytes: [ 0x3b, 0x30, 0x07, 0x46 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "c.ngl.s $f6, $f7"
+  -
+    input:
+      bytes: [ 0x39, 0x60, 0x2e, 0x46 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "c.ngle.d $f12, $f14"
+  -
+    input:
+      bytes: [ 0x39, 0x30, 0x07, 0x46 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "c.ngle.s $f6, $f7"
+  -
+    input:
+      bytes: [ 0x3f, 0x60, 0x2e, 0x46 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "c.ngt.d $f12, $f14"
+  -
+    input:
+      bytes: [ 0x3f, 0x30, 0x07, 0x46 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "c.ngt.s $f6, $f7"
+  -
+    input:
+      bytes: [ 0x36, 0x60, 0x2e, 0x46 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "c.ole.d $f12, $f14"
+  -
+    input:
+      bytes: [ 0x36, 0x30, 0x07, 0x46 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "c.ole.s $f6, $f7"
+  -
+    input:
+      bytes: [ 0x34, 0x60, 0x2e, 0x46 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "c.olt.d $f12, $f14"
+  -
+    input:
+      bytes: [ 0x34, 0x30, 0x07, 0x46 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "c.olt.s $f6, $f7"
+  -
+    input:
+      bytes: [ 0x3a, 0x60, 0x2e, 0x46 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "c.seq.d $f12, $f14"
+  -
+    input:
+      bytes: [ 0x3a, 0x30, 0x07, 0x46 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "c.seq.s $f6, $f7"
+  -
+    input:
+      bytes: [ 0x38, 0x60, 0x2e, 0x46 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "c.sf.d $f12, $f14"
+  -
+    input:
+      bytes: [ 0x38, 0x30, 0x07, 0x46 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "c.sf.s $f6, $f7"
+  -
+    input:
+      bytes: [ 0x33, 0x60, 0x2e, 0x46 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "c.ueq.d $f12, $f14"
+  -
+    input:
+      bytes: [ 0x33, 0xe0, 0x12, 0x46 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "c.ueq.s $f28, $f18"
+  -
+    input:
+      bytes: [ 0x37, 0x60, 0x2e, 0x46 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "c.ule.d $f12, $f14"
+  -
+    input:
+      bytes: [ 0x37, 0x30, 0x07, 0x46 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "c.ule.s $f6, $f7"
+  -
+    input:
+      bytes: [ 0x35, 0x60, 0x2e, 0x46 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "c.ult.d $f12, $f14"
+  -
+    input:
+      bytes: [ 0x35, 0x30, 0x07, 0x46 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "c.ult.s $f6, $f7"
+  -
+    input:
+      bytes: [ 0x31, 0x60, 0x2e, 0x46 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "c.un.d $f12, $f14"
+  -
+    input:
+      bytes: [ 0x31, 0x30, 0x07, 0x46 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "c.un.s $f6, $f7"
+  -
+    input:
+      bytes: [ 0xa1, 0x39, 0x00, 0x46 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "cvt.d.s $f6, $f7"
+  -
+    input:
+      bytes: [ 0x21, 0x73, 0x80, 0x46 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "cvt.d.w $f12, $f14"
+  -
+    input:
+      bytes: [ 0x20, 0x73, 0x20, 0x46 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "cvt.s.d $f12, $f14"
+  -
+    input:
+      bytes: [ 0xa0, 0x39, 0x80, 0x46 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "cvt.s.w $f6, $f7"
+  -
+    input:
+      bytes: [ 0x24, 0x73, 0x20, 0x46 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "cvt.w.d $f12, $f14"
+  -
+    input:
+      bytes: [ 0xa4, 0x39, 0x00, 0x46 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "cvt.w.s $f6, $f7"
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x46, 0x44 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "cfc1 $a2, $0"
+  -
+    input:
+      bytes: [ 0x00, 0xf8, 0xca, 0x44 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "ctc1 $t2, $31"
+  -
+    input:
+      bytes: [ 0x00, 0x38, 0x06, 0x44 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "mfc1 $a2, $f7"
+  -
+    input:
+      bytes: [ 0x10, 0x28, 0x00, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "mfhi $a1"
+  -
+    input:
+      bytes: [ 0x12, 0x28, 0x00, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "mflo $a1"
+  -
+    input:
+      bytes: [ 0x86, 0x41, 0x20, 0x46 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.d $f6, $f8"
+  -
+    input:
+      bytes: [ 0x86, 0x39, 0x00, 0x46 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.s $f6, $f7"
+  -
+    input:
+      bytes: [ 0x00, 0x38, 0x86, 0x44 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "mtc1 $a2, $f7"
+  -
+    input:
+      bytes: [ 0x11, 0x00, 0xe0, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "mthi $a3"
+  -
+    input:
+      bytes: [ 0x13, 0x00, 0xe0, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "mtlo $a3"
+  -
+    input:
+      bytes: [ 0xc6, 0x23, 0xe9, 0xe4 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "swc1 $f9, 9158($a3)"
+  -
+    input:
+      bytes: [ 0x00, 0x38, 0x06, 0x40 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "mfc0 $a2, $a3, 0"
+  -
+    input:
+      bytes: [ 0x00, 0x40, 0x89, 0x40 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "mtc0 $t1, $t0, 0"
+  -
+    input:
+      bytes: [ 0x00, 0x38, 0x05, 0x48 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "mfc2 $a1, $a3, 0"
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x89, 0x48 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "mtc2 $t1, $a0, 0"
+  -
+    input:
+      bytes: [ 0x02, 0x38, 0x06, 0x40 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "mfc0 $a2, $a3, 2"
+  -
+    input:
+      bytes: [ 0x03, 0x40, 0x89, 0x40 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "mtc0 $t1, $t0, 3"
+  -
+    input:
+      bytes: [ 0x04, 0x38, 0x05, 0x48 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "mfc2 $a1, $a3, 4"
+  -
+    input:
+      bytes: [ 0x05, 0x20, 0x89, 0x48 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "mtc2 $t1, $a0, 5"
+  -
+    input:
+      bytes: [ 0x01, 0x10, 0x20, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "movf $v0, $at, $fcc0"
+  -
+    input:
+      bytes: [ 0x01, 0x10, 0x21, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "movt $v0, $at, $fcc0"
+  -
+    input:
+      bytes: [ 0x01, 0x20, 0xb1, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "movt $a0, $a1, $fcc4"
+  -
+    input:
+      bytes: [ 0x11, 0x31, 0x28, 0x46 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "movf.d $f4, $f6, $fcc2"
+  -
+    input:
+      bytes: [ 0x11, 0x31, 0x14, 0x46 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "movf.s $f4, $f6, $fcc5"
+  -
+    input:
+      bytes: [ 0x05, 0x00, 0xa6, 0x4c ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "luxc1 $f0, $a2($a1)"
+  -
+    input:
+      bytes: [ 0x0d, 0x20, 0xb8, 0x4c ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "suxc1 $f4, $t8($a1)"
+  -
+    input:
+      bytes: [ 0x00, 0x05, 0xcc, 0x4d ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "lwxc1 $f20, $t4($t6)"
+  -
+    input:
+      bytes: [ 0x08, 0xd0, 0xd2, 0x4e ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "swxc1 $f26, $s2($s6)"
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x71, 0x44 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "mfhc1 $s1, $f4"
+  -
+    input:
+      bytes: [ 0x00, 0x30, 0xf1, 0x44 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "mthc1 $s1, $f6"
+  -
+    input:
+      bytes: [ 0x10, 0x00, 0xa4, 0xeb ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "swc2 $4, 16($sp)"
+  -
+    input:
+      bytes: [ 0x10, 0x00, 0xa4, 0xfb ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdc2 $4, 16($sp)"
+  -
+    input:
+      bytes: [ 0x0c, 0x00, 0xeb, 0xcb ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "lwc2 $11, 12($ra)"
+  -
+    input:
+      bytes: [ 0x0c, 0x00, 0xeb, 0xdb ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldc2 $11, 12($ra)"
diff --git a/tests/MC/Mips/mips-memory-instructions.s.yaml b/tests/MC/Mips/mips-memory-instructions.s.yaml
new file mode 100644
index 000000000..ab3997e12
--- /dev/null
+++ b/tests/MC/Mips/mips-memory-instructions.s.yaml
@@ -0,0 +1,145 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x10, 0x00, 0xa4, 0xa0 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "sb $a0, 16($a1)"
+  -
+    input:
+      bytes: [ 0x10, 0x00, 0xa4, 0xe0 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "sc $a0, 16($a1)"
+  -
+    input:
+      bytes: [ 0x10, 0x00, 0xa4, 0xa4 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh $a0, 16($a1)"
+  -
+    input:
+      bytes: [ 0x10, 0x00, 0xa4, 0xac ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "sw $a0, 16($a1)"
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0xa7, 0xac ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "sw $a3, ($a1)"
+  -
+    input:
+      bytes: [ 0x10, 0x00, 0xa2, 0xe4 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "swc1 $f2, 16($a1)"
+  -
+    input:
+      bytes: [ 0x10, 0x00, 0xa4, 0xa8 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "swl $a0, 16($a1)"
+  -
+    input:
+      bytes: [ 0x04, 0x00, 0xa4, 0x80 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "lb $a0, 4($a1)"
+  -
+    input:
+      bytes: [ 0x04, 0x00, 0xa4, 0x8c ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "lw $a0, 4($a1)"
+  -
+    input:
+      bytes: [ 0x04, 0x00, 0xa4, 0x90 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "lbu $a0, 4($a1)"
+  -
+    input:
+      bytes: [ 0x04, 0x00, 0xa4, 0x84 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "lh $a0, 4($a1)"
+  -
+    input:
+      bytes: [ 0x04, 0x00, 0xa4, 0x94 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "lhu $a0, 4($a1)"
+  -
+    input:
+      bytes: [ 0x04, 0x00, 0xa4, 0xc0 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "ll $a0, 4($a1)"
+  -
+    input:
+      bytes: [ 0x04, 0x00, 0xa4, 0x8c ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "lw $a0, 4($a1)"
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0xe7, 0x8c ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "lw $a3, ($a3)"
+  -
+    input:
+      bytes: [ 0x10, 0x00, 0xa2, 0x8f ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "lw $v0, 16($sp)"
diff --git a/tests/MC/Mips/mips-register-names.s.yaml b/tests/MC/Mips/mips-register-names.s.yaml
new file mode 100644
index 000000000..03b6feb30
--- /dev/null
+++ b/tests/MC/Mips/mips-register-names.s.yaml
@@ -0,0 +1,280 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x24, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "addiu $zero, $zero, 0"
+  -
+    input:
+      bytes: [ 0x24, 0x01, 0x00, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "addiu $at, $zero, 0"
+  -
+    input:
+      bytes: [ 0x24, 0x02, 0x00, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "addiu $v0, $zero, 0"
+  -
+    input:
+      bytes: [ 0x24, 0x03, 0x00, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "addiu $v1, $zero, 0"
+  -
+    input:
+      bytes: [ 0x24, 0x04, 0x00, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "addiu $a0, $zero, 0"
+  -
+    input:
+      bytes: [ 0x24, 0x05, 0x00, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "addiu $a1, $zero, 0"
+  -
+    input:
+      bytes: [ 0x24, 0x06, 0x00, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "addiu $a2, $zero, 0"
+  -
+    input:
+      bytes: [ 0x24, 0x07, 0x00, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "addiu $a3, $zero, 0"
+  -
+    input:
+      bytes: [ 0x24, 0x08, 0x00, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "addiu $t0, $zero, 0"
+  -
+    input:
+      bytes: [ 0x24, 0x09, 0x00, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "addiu $t1, $zero, 0"
+  -
+    input:
+      bytes: [ 0x24, 0x0a, 0x00, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "addiu $t2, $zero, 0"
+  -
+    input:
+      bytes: [ 0x24, 0x0b, 0x00, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "addiu $t3, $zero, 0"
+  -
+    input:
+      bytes: [ 0x24, 0x0c, 0x00, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "addiu $t4, $zero, 0"
+  -
+    input:
+      bytes: [ 0x24, 0x0d, 0x00, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "addiu $t5, $zero, 0"
+  -
+    input:
+      bytes: [ 0x24, 0x0e, 0x00, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "addiu $t6, $zero, 0"
+  -
+    input:
+      bytes: [ 0x24, 0x0f, 0x00, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "addiu $t7, $zero, 0"
+  -
+    input:
+      bytes: [ 0x24, 0x10, 0x00, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "addiu $s0, $zero, 0"
+  -
+    input:
+      bytes: [ 0x24, 0x11, 0x00, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "addiu $s1, $zero, 0"
+  -
+    input:
+      bytes: [ 0x24, 0x12, 0x00, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "addiu $s2, $zero, 0"
+  -
+    input:
+      bytes: [ 0x24, 0x13, 0x00, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "addiu $s3, $zero, 0"
+  -
+    input:
+      bytes: [ 0x24, 0x14, 0x00, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "addiu $s4, $zero, 0"
+  -
+    input:
+      bytes: [ 0x24, 0x15, 0x00, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "addiu $s5, $zero, 0"
+  -
+    input:
+      bytes: [ 0x24, 0x16, 0x00, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "addiu $s6, $zero, 0"
+  -
+    input:
+      bytes: [ 0x24, 0x17, 0x00, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "addiu $s7, $zero, 0"
+  -
+    input:
+      bytes: [ 0x24, 0x18, 0x00, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "addiu $t8, $zero, 0"
+  -
+    input:
+      bytes: [ 0x24, 0x19, 0x00, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "addiu $t9, $zero, 0"
+  -
+    input:
+      bytes: [ 0x24, 0x1a, 0x00, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "addiu $k0, $zero, 0"
+  -
+    input:
+      bytes: [ 0x24, 0x1b, 0x00, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "addiu $k1, $zero, 0"
+  -
+    input:
+      bytes: [ 0x24, 0x1c, 0x00, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "addiu $gp, $zero, 0"
+  -
+    input:
+      bytes: [ 0x24, 0x1d, 0x00, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "addiu $sp, $zero, 0"
+  -
+    input:
+      bytes: [ 0x24, 0x1e, 0x00, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "addiu $fp, $zero, 0"
diff --git a/tests/MC/Mips/mips64-alu-instructions.s.yaml b/tests/MC/Mips/mips64-alu-instructions.s.yaml
new file mode 100644
index 000000000..258f56830
--- /dev/null
+++ b/tests/MC/Mips/mips64-alu-instructions.s.yaml
@@ -0,0 +1,406 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x24, 0x48, 0xc7, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "and $t1, $a2, $a3"
+  -
+    input:
+      bytes: [ 0x67, 0x45, 0xc9, 0x30 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "andi $t1, $a2, 17767"
+  -
+    input:
+      bytes: [ 0x67, 0x45, 0xc9, 0x30 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "andi $t1, $a2, 17767"
+  -
+    input:
+      bytes: [ 0x21, 0x30, 0xe6, 0x70 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "clo $a2, $a3"
+  -
+    input:
+      bytes: [ 0x20, 0x30, 0xe6, 0x70 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "clz $a2, $a3"
+  -
+    input:
+      bytes: [ 0x84, 0x61, 0x33, 0x7d ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "ins $s3, $t1, 6, 7"
+  -
+    input:
+      bytes: [ 0x27, 0x48, 0xc7, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "nor $t1, $a2, $a3"
+  -
+    input:
+      bytes: [ 0x25, 0x18, 0x65, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "or $v1, $v1, $a1"
+  -
+    input:
+      bytes: [ 0x67, 0x45, 0xa4, 0x34 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "ori $a0, $a1, 17767"
+  -
+    input:
+      bytes: [ 0x67, 0x45, 0xc9, 0x34 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "ori $t1, $a2, 17767"
+  -
+    input:
+      bytes: [ 0xc2, 0x49, 0x26, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rotr $t1, $a2, 7"
+  -
+    input:
+      bytes: [ 0x46, 0x48, 0xe6, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rotrv $t1, $a2, $a3"
+  -
+    input:
+      bytes: [ 0xc0, 0x21, 0x03, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sll $a0, $v1, 7"
+  -
+    input:
+      bytes: [ 0x04, 0x10, 0xa3, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sllv $v0, $v1, $a1"
+  -
+    input:
+      bytes: [ 0x2a, 0x18, 0x65, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "slt $v1, $v1, $a1"
+  -
+    input:
+      bytes: [ 0x67, 0x00, 0x63, 0x28 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "slti $v1, $v1, 103"
+  -
+    input:
+      bytes: [ 0x67, 0x00, 0x63, 0x28 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "slti $v1, $v1, 103"
+  -
+    input:
+      bytes: [ 0x67, 0x00, 0x63, 0x2c ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sltiu $v1, $v1, 103"
+  -
+    input:
+      bytes: [ 0x2b, 0x18, 0x65, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sltu $v1, $v1, $a1"
+  -
+    input:
+      bytes: [ 0xc3, 0x21, 0x03, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sra $a0, $v1, 7"
+  -
+    input:
+      bytes: [ 0x07, 0x10, 0xa3, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "srav $v0, $v1, $a1"
+  -
+    input:
+      bytes: [ 0xc2, 0x21, 0x03, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "srl $a0, $v1, 7"
+  -
+    input:
+      bytes: [ 0x06, 0x10, 0xa3, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "srlv $v0, $v1, $a1"
+  -
+    input:
+      bytes: [ 0x26, 0x18, 0x65, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor $v1, $v1, $a1"
+  -
+    input:
+      bytes: [ 0x67, 0x45, 0xc9, 0x38 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xori $t1, $a2, 17767"
+  -
+    input:
+      bytes: [ 0x67, 0x45, 0xc9, 0x38 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xori $t1, $a2, 17767"
+  -
+    input:
+      bytes: [ 0xa0, 0x30, 0x07, 0x7c ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "wsbh $a2, $a3"
+  -
+    input:
+      bytes: [ 0x27, 0x38, 0x00, 0x01 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "not $a3, $t0"
+  -
+    input:
+      bytes: [ 0x2c, 0x48, 0xc7, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "dadd $t1, $a2, $a3"
+  -
+    input:
+      bytes: [ 0x67, 0x45, 0xc9, 0x60 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "daddi $t1, $a2, 17767"
+  -
+    input:
+      bytes: [ 0x67, 0xc5, 0xc9, 0x64 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "daddiu $t1, $a2, -15001"
+  -
+    input:
+      bytes: [ 0x67, 0x45, 0xc9, 0x60 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "daddi $t1, $a2, 17767"
+  -
+    input:
+      bytes: [ 0x67, 0x45, 0x29, 0x61 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "daddi $t1, $t1, 17767"
+  -
+    input:
+      bytes: [ 0x67, 0xc5, 0xc9, 0x64 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "daddiu $t1, $a2, -15001"
+  -
+    input:
+      bytes: [ 0x67, 0xc5, 0x29, 0x65 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "daddiu $t1, $t1, -15001"
+  -
+    input:
+      bytes: [ 0x2d, 0x48, 0xc7, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "daddu $t1, $a2, $a3"
+  -
+    input:
+      bytes: [ 0x3a, 0x4d, 0x26, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "drotr $t1, $a2, 20"
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0xc7, 0x70 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd $a2, $a3"
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0xc7, 0x70 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddu $a2, $a3"
+  -
+    input:
+      bytes: [ 0x04, 0x00, 0xc7, 0x70 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub $a2, $a3"
+  -
+    input:
+      bytes: [ 0x05, 0x00, 0xc7, 0x70 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubu $a2, $a3"
+  -
+    input:
+      bytes: [ 0x18, 0x00, 0x65, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "mult $v1, $a1"
+  -
+    input:
+      bytes: [ 0x19, 0x00, 0x65, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "multu $v1, $a1"
+  -
+    input:
+      bytes: [ 0x2f, 0x20, 0x65, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "dsubu $a0, $v1, $a1"
+  -
+    input:
+      bytes: [ 0x2d, 0x38, 0x00, 0x01 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "move $a3, $t0"
diff --git a/tests/MC/Mips/mips64-instructions.s.yaml b/tests/MC/Mips/mips64-instructions.s.yaml
new file mode 100644
index 000000000..082a3d404
--- /dev/null
+++ b/tests/MC/Mips/mips64-instructions.s.yaml
@@ -0,0 +1,19 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x81, 0x00, 0x42, 0x4d ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldxc1 $f2, $v0($t2)"
+  -
+    input:
+      bytes: [ 0x09, 0x40, 0x24, 0x4f ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdxc1 $f8, $a0($t9)"
diff --git a/tests/MC/Mips/mips64-register-names.s.yaml b/tests/MC/Mips/mips64-register-names.s.yaml
new file mode 100644
index 000000000..659bfb3c7
--- /dev/null
+++ b/tests/MC/Mips/mips64-register-names.s.yaml
@@ -0,0 +1,217 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x64, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "daddiu $zero, $zero, 0"
+  -
+    input:
+      bytes: [ 0x64, 0x01, 0x00, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "daddiu $at, $zero, 0"
+  -
+    input:
+      bytes: [ 0x64, 0x02, 0x00, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "daddiu $v0, $zero, 0"
+  -
+    input:
+      bytes: [ 0x64, 0x03, 0x00, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "daddiu $v1, $zero, 0"
+  -
+    input:
+      bytes: [ 0x64, 0x04, 0x00, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "daddiu $a0, $zero, 0"
+  -
+    input:
+      bytes: [ 0x64, 0x05, 0x00, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "daddiu $a1, $zero, 0"
+  -
+    input:
+      bytes: [ 0x64, 0x06, 0x00, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "daddiu $a2, $zero, 0"
+  -
+    input:
+      bytes: [ 0x64, 0x0c, 0x00, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "daddiu $t4, $zero, 0"
+  -
+    input:
+      bytes: [ 0x64, 0x0d, 0x00, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "daddiu $t5, $zero, 0"
+  -
+    input:
+      bytes: [ 0x64, 0x0e, 0x00, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "daddiu $t6, $zero, 0"
+  -
+    input:
+      bytes: [ 0x64, 0x0f, 0x00, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "daddiu $t7, $zero, 0"
+  -
+    input:
+      bytes: [ 0x64, 0x10, 0x00, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "daddiu $s0, $zero, 0"
+  -
+    input:
+      bytes: [ 0x64, 0x11, 0x00, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "daddiu $s1, $zero, 0"
+  -
+    input:
+      bytes: [ 0x64, 0x12, 0x00, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "daddiu $s2, $zero, 0"
+  -
+    input:
+      bytes: [ 0x64, 0x13, 0x00, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "daddiu $s3, $zero, 0"
+  -
+    input:
+      bytes: [ 0x64, 0x14, 0x00, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "daddiu $s4, $zero, 0"
+  -
+    input:
+      bytes: [ 0x64, 0x15, 0x00, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "daddiu $s5, $zero, 0"
+  -
+    input:
+      bytes: [ 0x64, 0x16, 0x00, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "daddiu $s6, $zero, 0"
+  -
+    input:
+      bytes: [ 0x64, 0x17, 0x00, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "daddiu $s7, $zero, 0"
+  -
+    input:
+      bytes: [ 0x64, 0x18, 0x00, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "daddiu $t8, $zero, 0"
+  -
+    input:
+      bytes: [ 0x64, 0x19, 0x00, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "daddiu $t9, $zero, 0"
+  -
+    input:
+      bytes: [ 0x64, 0x1c, 0x00, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "daddiu $gp, $zero, 0"
+  -
+    input:
+      bytes: [ 0x64, 0x1d, 0x00, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "daddiu $sp, $zero, 0"
+  -
+    input:
+      bytes: [ 0x64, 0x1f, 0x00, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "daddiu $ra, $zero, 0"
diff --git a/tests/MC/Mips/mips_directives.s.yaml b/tests/MC/Mips/mips_directives.s.yaml
new file mode 100644
index 000000000..32f6c4d36
--- /dev/null
+++ b/tests/MC/Mips/mips_directives.s.yaml
@@ -0,0 +1,100 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x10, 0x00, 0x01, 0x4d ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "b 1336"
+  -
+    input:
+      bytes: [ 0x08, 0x00, 0x01, 0x4c ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "j 1328"
+  -
+    input:
+      bytes: [ 0x0c, 0x00, 0x01, 0x4c ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "jal 1328"
+  -
+    input:
+      bytes: [ 0x10, 0x00, 0x01, 0x4d ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "b 1336"
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "nop"
+  -
+    input:
+      bytes: [ 0x08, 0x00, 0x01, 0x4c ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "j 1328"
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "nop"
+  -
+    input:
+      bytes: [ 0x0c, 0x00, 0x01, 0x4c ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "jal 1328"
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "nop"
+  -
+    input:
+      bytes: [ 0x46, 0x00, 0x39, 0x85 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "abs.s $f6, $f7"
+  -
+    input:
+      bytes: [ 0x01, 0xef, 0x18, 0x24 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "and $v1, $t7, $t7"
diff --git a/tests/MC/Mips/nabi-regs.s.yaml b/tests/MC/Mips/nabi-regs.s.yaml
new file mode 100644
index 000000000..1a6c62346
--- /dev/null
+++ b/tests/MC/Mips/nabi-regs.s.yaml
@@ -0,0 +1,100 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x02, 0x04, 0x80, 0x20 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add $s0, $s0, $a0"
+  -
+    input:
+      bytes: [ 0x02, 0x06, 0x80, 0x20 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add $s0, $s0, $a2"
+  -
+    input:
+      bytes: [ 0x02, 0x07, 0x80, 0x20 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add $s0, $s0, $a3"
+  -
+    input:
+      bytes: [ 0x02, 0x08, 0x80, 0x20 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add $s0, $s0, $t0"
+  -
+    input:
+      bytes: [ 0x02, 0x09, 0x80, 0x20 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add $s0, $s0, $t1"
+  -
+    input:
+      bytes: [ 0x02, 0x0a, 0x80, 0x20 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add $s0, $s0, $t2"
+  -
+    input:
+      bytes: [ 0x02, 0x0b, 0x80, 0x20 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add $s0, $s0, $t3"
+  -
+    input:
+      bytes: [ 0x02, 0x0c, 0x80, 0x20 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add $s0, $s0, $t4"
+  -
+    input:
+      bytes: [ 0x02, 0x0d, 0x80, 0x20 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add $s0, $s0, $t5"
+  -
+    input:
+      bytes: [ 0x02, 0x0e, 0x80, 0x20 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add $s0, $s0, $t6"
+  -
+    input:
+      bytes: [ 0x02, 0x0f, 0x80, 0x20 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_BIG_ENDIAN", "CS_MODE_MIPS64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add $s0, $s0, $t7"
diff --git a/tests/MC/Mips/set-at-directive.s.yaml b/tests/MC/Mips/set-at-directive.s.yaml
new file mode 100644
index 000000000..422a55854
--- /dev/null
+++ b/tests/MC/Mips/set-at-directive.s.yaml
@@ -0,0 +1,46 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x08, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "jr $v1"
+  -
+    input:
+      bytes: [ 0x08, 0x00, 0x80, 0x03 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "jr $gp"
+  -
+    input:
+      bytes: [ 0x08, 0x00, 0xc0, 0x03 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "jr $fp"
+  -
+    input:
+      bytes: [ 0x08, 0x00, 0xa0, 0x03 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "jr $sp"
+  -
+    input:
+      bytes: [ 0x08, 0x00, 0xe0, 0x03 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32" ]
+    expected:
+      insns:
+        -
+          asm_text: "jr $ra"
diff --git a/tests/MC/Mips/test_2r.s.yaml b/tests/MC/Mips/test_2r.s.yaml
new file mode 100644
index 000000000..ee3216f95
--- /dev/null
+++ b/tests/MC/Mips/test_2r.s.yaml
@@ -0,0 +1,136 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x7b, 0x00, 0x4f, 0x9e ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fill.b $w30, $t1"
+  -
+    input:
+      bytes: [ 0x7b, 0x01, 0xbf, 0xde ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fill.h $w31, $s7"
+  -
+    input:
+      bytes: [ 0x7b, 0x02, 0xc4, 0x1e ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fill.w $w16, $t8"
+  -
+    input:
+      bytes: [ 0x7b, 0x08, 0x05, 0x5e ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "nloc.b $w21, $w0"
+  -
+    input:
+      bytes: [ 0x7b, 0x09, 0xfc, 0x9e ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "nloc.h $w18, $w31"
+  -
+    input:
+      bytes: [ 0x7b, 0x0a, 0xb8, 0x9e ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "nloc.w $w2, $w23"
+  -
+    input:
+      bytes: [ 0x7b, 0x0b, 0x51, 0x1e ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "nloc.d $w4, $w10"
+  -
+    input:
+      bytes: [ 0x7b, 0x0c, 0x17, 0xde ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "nlzc.b $w31, $w2"
+  -
+    input:
+      bytes: [ 0x7b, 0x0d, 0xb6, 0xde ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "nlzc.h $w27, $w22"
+  -
+    input:
+      bytes: [ 0x7b, 0x0e, 0xea, 0x9e ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "nlzc.w $w10, $w29"
+  -
+    input:
+      bytes: [ 0x7b, 0x0f, 0x4e, 0x5e ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "nlzc.d $w25, $w9"
+  -
+    input:
+      bytes: [ 0x7b, 0x04, 0x95, 0x1e ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "pcnt.b $w20, $w18"
+  -
+    input:
+      bytes: [ 0x7b, 0x05, 0x40, 0x1e ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "pcnt.h $w0, $w8"
+  -
+    input:
+      bytes: [ 0x7b, 0x06, 0x4d, 0xde ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "pcnt.w $w23, $w9"
+  -
+    input:
+      bytes: [ 0x7b, 0x07, 0xc5, 0x5e ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "pcnt.d $w21, $w24"
diff --git a/tests/MC/Mips/test_2rf.s.yaml b/tests/MC/Mips/test_2rf.s.yaml
new file mode 100644
index 000000000..14e13eb11
--- /dev/null
+++ b/tests/MC/Mips/test_2rf.s.yaml
@@ -0,0 +1,289 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x7b, 0x20, 0x66, 0x9e ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fclass.w $w26, $w12"
+  -
+    input:
+      bytes: [ 0x7b, 0x21, 0x8e, 0x1e ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fclass.d $w24, $w17"
+  -
+    input:
+      bytes: [ 0x7b, 0x30, 0x02, 0x1e ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fexupl.w $w8, $w0"
+  -
+    input:
+      bytes: [ 0x7b, 0x31, 0xec, 0x5e ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fexupl.d $w17, $w29"
+  -
+    input:
+      bytes: [ 0x7b, 0x32, 0x23, 0x5e ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fexupr.w $w13, $w4"
+  -
+    input:
+      bytes: [ 0x7b, 0x33, 0x11, 0x5e ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fexupr.d $w5, $w2"
+  -
+    input:
+      bytes: [ 0x7b, 0x3c, 0xed, 0x1e ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ffint_s.w $w20, $w29"
+  -
+    input:
+      bytes: [ 0x7b, 0x3d, 0x7b, 0x1e ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ffint_s.d $w12, $w15"
+  -
+    input:
+      bytes: [ 0x7b, 0x3e, 0xd9, 0xde ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ffint_u.w $w7, $w27"
+  -
+    input:
+      bytes: [ 0x7b, 0x3f, 0x84, 0xde ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ffint_u.d $w19, $w16"
+  -
+    input:
+      bytes: [ 0x7b, 0x34, 0x6f, 0xde ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ffql.w $w31, $w13"
+  -
+    input:
+      bytes: [ 0x7b, 0x35, 0x6b, 0x1e ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ffql.d $w12, $w13"
+  -
+    input:
+      bytes: [ 0x7b, 0x36, 0xf6, 0xde ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ffqr.w $w27, $w30"
+  -
+    input:
+      bytes: [ 0x7b, 0x37, 0x7f, 0x9e ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ffqr.d $w30, $w15"
+  -
+    input:
+      bytes: [ 0x7b, 0x2e, 0xfe, 0x5e ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "flog2.w $w25, $w31"
+  -
+    input:
+      bytes: [ 0x7b, 0x2f, 0x54, 0x9e ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "flog2.d $w18, $w10"
+  -
+    input:
+      bytes: [ 0x7b, 0x2c, 0x79, 0xde ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "frint.w $w7, $w15"
+  -
+    input:
+      bytes: [ 0x7b, 0x2d, 0xb5, 0x5e ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "frint.d $w21, $w22"
+  -
+    input:
+      bytes: [ 0x7b, 0x2a, 0x04, 0xde ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "frcp.w $w19, $w0"
+  -
+    input:
+      bytes: [ 0x7b, 0x2b, 0x71, 0x1e ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "frcp.d $w4, $w14"
+  -
+    input:
+      bytes: [ 0x7b, 0x28, 0x8b, 0x1e ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "frsqrt.w $w12, $w17"
+  -
+    input:
+      bytes: [ 0x7b, 0x29, 0x5d, 0xde ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "frsqrt.d $w23, $w11"
+  -
+    input:
+      bytes: [ 0x7b, 0x26, 0x58, 0x1e ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsqrt.w $w0, $w11"
+  -
+    input:
+      bytes: [ 0x7b, 0x27, 0x63, 0xde ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsqrt.d $w15, $w12"
+  -
+    input:
+      bytes: [ 0x7b, 0x38, 0x2f, 0x9e ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ftint_s.w $w30, $w5"
+  -
+    input:
+      bytes: [ 0x7b, 0x39, 0xb9, 0x5e ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ftint_s.d $w5, $w23"
+  -
+    input:
+      bytes: [ 0x7b, 0x3a, 0x75, 0x1e ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ftint_u.w $w20, $w14"
+  -
+    input:
+      bytes: [ 0x7b, 0x3b, 0xad, 0xde ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ftint_u.d $w23, $w21"
+  -
+    input:
+      bytes: [ 0x7b, 0x22, 0x8f, 0x5e ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ftrunc_s.w $w29, $w17"
+  -
+    input:
+      bytes: [ 0x7b, 0x23, 0xdb, 0x1e ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ftrunc_s.d $w12, $w27"
+  -
+    input:
+      bytes: [ 0x7b, 0x24, 0x7c, 0x5e ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ftrunc_u.w $w17, $w15"
+  -
+    input:
+      bytes: [ 0x7b, 0x25, 0xd9, 0x5e ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ftrunc_u.d $w5, $w27"
diff --git a/tests/MC/Mips/test_3r.s.yaml b/tests/MC/Mips/test_3r.s.yaml
new file mode 100644
index 000000000..bbee76575
--- /dev/null
+++ b/tests/MC/Mips/test_3r.s.yaml
@@ -0,0 +1,2179 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x78, 0x04, 0x4e, 0x90 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "add_a.b $w26, $w9, $w4"
+  -
+    input:
+      bytes: [ 0x78, 0x3f, 0xdd, 0xd0 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "add_a.h $w23, $w27, $w31"
+  -
+    input:
+      bytes: [ 0x78, 0x56, 0x32, 0xd0 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "add_a.w $w11, $w6, $w22"
+  -
+    input:
+      bytes: [ 0x78, 0x60, 0x51, 0x90 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "add_a.d $w6, $w10, $w0"
+  -
+    input:
+      bytes: [ 0x78, 0x93, 0xc4, 0xd0 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "adds_a.b $w19, $w24, $w19"
+  -
+    input:
+      bytes: [ 0x78, 0xa4, 0x36, 0x50 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "adds_a.h $w25, $w6, $w4"
+  -
+    input:
+      bytes: [ 0x78, 0xdb, 0x8e, 0x50 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "adds_a.w $w25, $w17, $w27"
+  -
+    input:
+      bytes: [ 0x78, 0xfa, 0x93, 0xd0 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "adds_a.d $w15, $w18, $w26"
+  -
+    input:
+      bytes: [ 0x79, 0x13, 0x5f, 0x50 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "adds_s.b $w29, $w11, $w19"
+  -
+    input:
+      bytes: [ 0x79, 0x3a, 0xb9, 0x50 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "adds_s.h $w5, $w23, $w26"
+  -
+    input:
+      bytes: [ 0x79, 0x4d, 0x74, 0x10 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "adds_s.w $w16, $w14, $w13"
+  -
+    input:
+      bytes: [ 0x79, 0x7c, 0x70, 0x90 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "adds_s.d $w2, $w14, $w28"
+  -
+    input:
+      bytes: [ 0x79, 0x8e, 0x88, 0xd0 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "adds_u.b $w3, $w17, $w14"
+  -
+    input:
+      bytes: [ 0x79, 0xa4, 0xf2, 0x90 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "adds_u.h $w10, $w30, $w4"
+  -
+    input:
+      bytes: [ 0x79, 0xd4, 0x93, 0xd0 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "adds_u.w $w15, $w18, $w20"
+  -
+    input:
+      bytes: [ 0x79, 0xe9, 0x57, 0x90 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "adds_u.d $w30, $w10, $w9"
+  -
+    input:
+      bytes: [ 0x78, 0x15, 0xa6, 0x0e ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "addv.b $w24, $w20, $w21"
+  -
+    input:
+      bytes: [ 0x78, 0x3b, 0x69, 0x0e ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "addv.h $w4, $w13, $w27"
+  -
+    input:
+      bytes: [ 0x78, 0x4e, 0x5c, 0xce ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "addv.w $w19, $w11, $w14"
+  -
+    input:
+      bytes: [ 0x78, 0x7f, 0xa8, 0x8e ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "addv.d $w2, $w21, $w31"
+  -
+    input:
+      bytes: [ 0x7a, 0x03, 0x85, 0xd1 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "asub_s.b $w23, $w16, $w3"
+  -
+    input:
+      bytes: [ 0x7a, 0x39, 0x8d, 0x91 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "asub_s.h $w22, $w17, $w25"
+  -
+    input:
+      bytes: [ 0x7a, 0x49, 0x0e, 0x11 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "asub_s.w $w24, $w1, $w9"
+  -
+    input:
+      bytes: [ 0x7a, 0x6c, 0x63, 0x51 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "asub_s.d $w13, $w12, $w12"
+  -
+    input:
+      bytes: [ 0x7a, 0x8b, 0xea, 0x91 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "asub_u.b $w10, $w29, $w11"
+  -
+    input:
+      bytes: [ 0x7a, 0xaf, 0x4c, 0x91 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "asub_u.h $w18, $w9, $w15"
+  -
+    input:
+      bytes: [ 0x7a, 0xdf, 0x9a, 0x91 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "asub_u.w $w10, $w19, $w31"
+  -
+    input:
+      bytes: [ 0x7a, 0xe0, 0x54, 0x51 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "asub_u.d $w17, $w10, $w0"
+  -
+    input:
+      bytes: [ 0x7a, 0x01, 0x28, 0x90 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ave_s.b $w2, $w5, $w1"
+  -
+    input:
+      bytes: [ 0x7a, 0x29, 0x9c, 0x10 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ave_s.h $w16, $w19, $w9"
+  -
+    input:
+      bytes: [ 0x7a, 0x45, 0xfc, 0x50 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ave_s.w $w17, $w31, $w5"
+  -
+    input:
+      bytes: [ 0x7a, 0x6a, 0xce, 0xd0 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ave_s.d $w27, $w25, $w10"
+  -
+    input:
+      bytes: [ 0x7a, 0x89, 0x9c, 0x10 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ave_u.b $w16, $w19, $w9"
+  -
+    input:
+      bytes: [ 0x7a, 0xab, 0xe7, 0x10 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ave_u.h $w28, $w28, $w11"
+  -
+    input:
+      bytes: [ 0x7a, 0xcb, 0x62, 0xd0 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ave_u.w $w11, $w12, $w11"
+  -
+    input:
+      bytes: [ 0x7a, 0xfc, 0x9f, 0x90 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ave_u.d $w30, $w19, $w28"
+  -
+    input:
+      bytes: [ 0x7b, 0x02, 0x86, 0x90 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "aver_s.b $w26, $w16, $w2"
+  -
+    input:
+      bytes: [ 0x7b, 0x3b, 0xdf, 0xd0 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "aver_s.h $w31, $w27, $w27"
+  -
+    input:
+      bytes: [ 0x7b, 0x59, 0x97, 0x10 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "aver_s.w $w28, $w18, $w25"
+  -
+    input:
+      bytes: [ 0x7b, 0x7b, 0xaf, 0x50 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "aver_s.d $w29, $w21, $w27"
+  -
+    input:
+      bytes: [ 0x7b, 0x83, 0xd7, 0x50 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "aver_u.b $w29, $w26, $w3"
+  -
+    input:
+      bytes: [ 0x7b, 0xa9, 0x94, 0x90 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "aver_u.h $w18, $w18, $w9"
+  -
+    input:
+      bytes: [ 0x7b, 0xdd, 0xcc, 0x50 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "aver_u.w $w17, $w25, $w29"
+  -
+    input:
+      bytes: [ 0x7b, 0xf3, 0xb5, 0x90 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "aver_u.d $w22, $w22, $w19"
+  -
+    input:
+      bytes: [ 0x79, 0x9d, 0x78, 0x8d ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bclr.b $w2, $w15, $w29"
+  -
+    input:
+      bytes: [ 0x79, 0xbc, 0xac, 0x0d ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bclr.h $w16, $w21, $w28"
+  -
+    input:
+      bytes: [ 0x79, 0xc9, 0x14, 0xcd ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bclr.w $w19, $w2, $w9"
+  -
+    input:
+      bytes: [ 0x79, 0xe4, 0xfe, 0xcd ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bclr.d $w27, $w31, $w4"
+  -
+    input:
+      bytes: [ 0x7b, 0x18, 0x81, 0x4d ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "binsl.b $w5, $w16, $w24"
+  -
+    input:
+      bytes: [ 0x7b, 0x2a, 0x2f, 0x8d ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "binsl.h $w30, $w5, $w10"
+  -
+    input:
+      bytes: [ 0x7b, 0x4d, 0x7b, 0x8d ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "binsl.w $w14, $w15, $w13"
+  -
+    input:
+      bytes: [ 0x7b, 0x6c, 0xa5, 0xcd ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "binsl.d $w23, $w20, $w12"
+  -
+    input:
+      bytes: [ 0x7b, 0x82, 0x5d, 0x8d ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "binsr.b $w22, $w11, $w2"
+  -
+    input:
+      bytes: [ 0x7b, 0xa6, 0xd0, 0x0d ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "binsr.h $w0, $w26, $w6"
+  -
+    input:
+      bytes: [ 0x7b, 0xdc, 0x1e, 0x8d ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "binsr.w $w26, $w3, $w28"
+  -
+    input:
+      bytes: [ 0x7b, 0xf5, 0x00, 0x0d ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "binsr.d $w0, $w0, $w21"
+  -
+    input:
+      bytes: [ 0x7a, 0x98, 0x58, 0x0d ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bneg.b $w0, $w11, $w24"
+  -
+    input:
+      bytes: [ 0x7a, 0xa4, 0x87, 0x0d ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bneg.h $w28, $w16, $w4"
+  -
+    input:
+      bytes: [ 0x7a, 0xd3, 0xd0, 0xcd ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bneg.w $w3, $w26, $w19"
+  -
+    input:
+      bytes: [ 0x7a, 0xef, 0xeb, 0x4d ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bneg.d $w13, $w29, $w15"
+  -
+    input:
+      bytes: [ 0x7a, 0x1f, 0x2f, 0xcd ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bset.b $w31, $w5, $w31"
+  -
+    input:
+      bytes: [ 0x7a, 0x26, 0x63, 0x8d ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bset.h $w14, $w12, $w6"
+  -
+    input:
+      bytes: [ 0x7a, 0x4c, 0x4f, 0xcd ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bset.w $w31, $w9, $w12"
+  -
+    input:
+      bytes: [ 0x7a, 0x65, 0xb1, 0x4d ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bset.d $w5, $w22, $w5"
+  -
+    input:
+      bytes: [ 0x78, 0x12, 0xff, 0xcf ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ceq.b $w31, $w31, $w18"
+  -
+    input:
+      bytes: [ 0x78, 0x29, 0xda, 0x8f ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ceq.h $w10, $w27, $w9"
+  -
+    input:
+      bytes: [ 0x78, 0x4e, 0x2a, 0x4f ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ceq.w $w9, $w5, $w14"
+  -
+    input:
+      bytes: [ 0x78, 0x60, 0x89, 0x4f ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ceq.d $w5, $w17, $w0"
+  -
+    input:
+      bytes: [ 0x7a, 0x09, 0x25, 0xcf ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cle_s.b $w23, $w4, $w9"
+  -
+    input:
+      bytes: [ 0x7a, 0x33, 0xdd, 0x8f ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cle_s.h $w22, $w27, $w19"
+  -
+    input:
+      bytes: [ 0x7a, 0x4a, 0xd7, 0x8f ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cle_s.w $w30, $w26, $w10"
+  -
+    input:
+      bytes: [ 0x7a, 0x6a, 0x2c, 0x8f ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cle_s.d $w18, $w5, $w10"
+  -
+    input:
+      bytes: [ 0x7a, 0x80, 0xc8, 0x4f ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cle_u.b $w1, $w25, $w0"
+  -
+    input:
+      bytes: [ 0x7a, 0xbd, 0x01, 0xcf ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cle_u.h $w7, $w0, $w29"
+  -
+    input:
+      bytes: [ 0x7a, 0xc1, 0x96, 0x4f ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cle_u.w $w25, $w18, $w1"
+  -
+    input:
+      bytes: [ 0x7a, 0xfe, 0x01, 0x8f ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cle_u.d $w6, $w0, $w30"
+  -
+    input:
+      bytes: [ 0x79, 0x15, 0x16, 0x4f ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "clt_s.b $w25, $w2, $w21"
+  -
+    input:
+      bytes: [ 0x79, 0x29, 0x98, 0x8f ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "clt_s.h $w2, $w19, $w9"
+  -
+    input:
+      bytes: [ 0x79, 0x50, 0x45, 0xcf ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "clt_s.w $w23, $w8, $w16"
+  -
+    input:
+      bytes: [ 0x79, 0x6c, 0xf1, 0xcf ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "clt_s.d $w7, $w30, $w12"
+  -
+    input:
+      bytes: [ 0x79, 0x8d, 0xf8, 0x8f ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "clt_u.b $w2, $w31, $w13"
+  -
+    input:
+      bytes: [ 0x79, 0xb7, 0xfc, 0x0f ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "clt_u.h $w16, $w31, $w23"
+  -
+    input:
+      bytes: [ 0x79, 0xc9, 0xc0, 0xcf ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "clt_u.w $w3, $w24, $w9"
+  -
+    input:
+      bytes: [ 0x79, 0xe1, 0x01, 0xcf ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "clt_u.d $w7, $w0, $w1"
+  -
+    input:
+      bytes: [ 0x7a, 0x12, 0x1f, 0x52 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "div_s.b $w29, $w3, $w18"
+  -
+    input:
+      bytes: [ 0x7a, 0x2d, 0x84, 0x52 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "div_s.h $w17, $w16, $w13"
+  -
+    input:
+      bytes: [ 0x7a, 0x5e, 0xc9, 0x12 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "div_s.w $w4, $w25, $w30"
+  -
+    input:
+      bytes: [ 0x7a, 0x74, 0x4f, 0xd2 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "div_s.d $w31, $w9, $w20"
+  -
+    input:
+      bytes: [ 0x7a, 0x8a, 0xe9, 0x92 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "div_u.b $w6, $w29, $w10"
+  -
+    input:
+      bytes: [ 0x7a, 0xae, 0xae, 0x12 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "div_u.h $w24, $w21, $w14"
+  -
+    input:
+      bytes: [ 0x7a, 0xd9, 0x77, 0x52 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "div_u.w $w29, $w14, $w25"
+  -
+    input:
+      bytes: [ 0x7a, 0xf5, 0x0f, 0xd2 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "div_u.d $w31, $w1, $w21"
+  -
+    input:
+      bytes: [ 0x78, 0x39, 0xb5, 0xd3 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "dotp_s.h $w23, $w22, $w25"
+  -
+    input:
+      bytes: [ 0x78, 0x45, 0x75, 0x13 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "dotp_s.w $w20, $w14, $w5"
+  -
+    input:
+      bytes: [ 0x78, 0x76, 0x14, 0x53 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "dotp_s.d $w17, $w2, $w22"
+  -
+    input:
+      bytes: [ 0x78, 0xa6, 0x13, 0x53 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "dotp_u.h $w13, $w2, $w6"
+  -
+    input:
+      bytes: [ 0x78, 0xd5, 0xb3, 0xd3 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "dotp_u.w $w15, $w22, $w21"
+  -
+    input:
+      bytes: [ 0x78, 0xfa, 0x81, 0x13 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "dotp_u.d $w4, $w16, $w26"
+  -
+    input:
+      bytes: [ 0x79, 0x36, 0xe0, 0x53 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "dpadd_s.h $w1, $w28, $w22"
+  -
+    input:
+      bytes: [ 0x79, 0x4c, 0x0a, 0x93 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "dpadd_s.w $w10, $w1, $w12"
+  -
+    input:
+      bytes: [ 0x79, 0x7b, 0xa8, 0xd3 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "dpadd_s.d $w3, $w21, $w27"
+  -
+    input:
+      bytes: [ 0x79, 0xb4, 0x2c, 0x53 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "dpadd_u.h $w17, $w5, $w20"
+  -
+    input:
+      bytes: [ 0x79, 0xd0, 0x46, 0x13 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "dpadd_u.w $w24, $w8, $w16"
+  -
+    input:
+      bytes: [ 0x79, 0xf0, 0xeb, 0xd3 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "dpadd_u.d $w15, $w29, $w16"
+  -
+    input:
+      bytes: [ 0x7a, 0x2c, 0x59, 0x13 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "dpsub_s.h $w4, $w11, $w12"
+  -
+    input:
+      bytes: [ 0x7a, 0x46, 0x39, 0x13 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "dpsub_s.w $w4, $w7, $w6"
+  -
+    input:
+      bytes: [ 0x7a, 0x7c, 0x67, 0xd3 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "dpsub_s.d $w31, $w12, $w28"
+  -
+    input:
+      bytes: [ 0x7a, 0xb1, 0xc9, 0x13 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "dpsub_u.h $w4, $w25, $w17"
+  -
+    input:
+      bytes: [ 0x7a, 0xd0, 0xcc, 0xd3 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "dpsub_u.w $w19, $w25, $w16"
+  -
+    input:
+      bytes: [ 0x7a, 0xfa, 0x51, 0xd3 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "dpsub_u.d $w7, $w10, $w26"
+  -
+    input:
+      bytes: [ 0x7a, 0x22, 0xc7, 0x15 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "hadd_s.h $w28, $w24, $w2"
+  -
+    input:
+      bytes: [ 0x7a, 0x4b, 0x8e, 0x15 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "hadd_s.w $w24, $w17, $w11"
+  -
+    input:
+      bytes: [ 0x7a, 0x74, 0x7c, 0x55 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "hadd_s.d $w17, $w15, $w20"
+  -
+    input:
+      bytes: [ 0x7a, 0xb1, 0xeb, 0x15 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "hadd_u.h $w12, $w29, $w17"
+  -
+    input:
+      bytes: [ 0x7a, 0xc6, 0x2a, 0x55 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "hadd_u.w $w9, $w5, $w6"
+  -
+    input:
+      bytes: [ 0x7a, 0xe6, 0xa0, 0x55 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "hadd_u.d $w1, $w20, $w6"
+  -
+    input:
+      bytes: [ 0x7b, 0x3d, 0x74, 0x15 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "hsub_s.h $w16, $w14, $w29"
+  -
+    input:
+      bytes: [ 0x7b, 0x4b, 0x6a, 0x55 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "hsub_s.w $w9, $w13, $w11"
+  -
+    input:
+      bytes: [ 0x7b, 0x6e, 0x97, 0x95 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "hsub_s.d $w30, $w18, $w14"
+  -
+    input:
+      bytes: [ 0x7b, 0xae, 0x61, 0xd5 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "hsub_u.h $w7, $w12, $w14"
+  -
+    input:
+      bytes: [ 0x7b, 0xc5, 0x2d, 0x55 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "hsub_u.w $w21, $w5, $w5"
+  -
+    input:
+      bytes: [ 0x7b, 0xff, 0x62, 0xd5 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "hsub_u.d $w11, $w12, $w31"
+  -
+    input:
+      bytes: [ 0x7b, 0x1e, 0x84, 0x94 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ilvev.b $w18, $w16, $w30"
+  -
+    input:
+      bytes: [ 0x7b, 0x2d, 0x03, 0x94 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ilvev.h $w14, $w0, $w13"
+  -
+    input:
+      bytes: [ 0x7b, 0x56, 0xcb, 0x14 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ilvev.w $w12, $w25, $w22"
+  -
+    input:
+      bytes: [ 0x7b, 0x63, 0xdf, 0x94 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ilvev.d $w30, $w27, $w3"
+  -
+    input:
+      bytes: [ 0x7a, 0x15, 0x1f, 0x54 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ilvl.b $w29, $w3, $w21"
+  -
+    input:
+      bytes: [ 0x7a, 0x31, 0x56, 0xd4 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ilvl.h $w27, $w10, $w17"
+  -
+    input:
+      bytes: [ 0x7a, 0x40, 0x09, 0x94 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ilvl.w $w6, $w1, $w0"
+  -
+    input:
+      bytes: [ 0x7a, 0x78, 0x80, 0xd4 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ilvl.d $w3, $w16, $w24"
+  -
+    input:
+      bytes: [ 0x7b, 0x94, 0x2a, 0xd4 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ilvod.b $w11, $w5, $w20"
+  -
+    input:
+      bytes: [ 0x7b, 0xbf, 0x6c, 0x94 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ilvod.h $w18, $w13, $w31"
+  -
+    input:
+      bytes: [ 0x7b, 0xd8, 0x87, 0x54 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ilvod.w $w29, $w16, $w24"
+  -
+    input:
+      bytes: [ 0x7b, 0xfd, 0x65, 0x94 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ilvod.d $w22, $w12, $w29"
+  -
+    input:
+      bytes: [ 0x7a, 0x86, 0xf1, 0x14 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ilvr.b $w4, $w30, $w6"
+  -
+    input:
+      bytes: [ 0x7a, 0xbd, 0x9f, 0x14 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ilvr.h $w28, $w19, $w29"
+  -
+    input:
+      bytes: [ 0x7a, 0xd5, 0xa4, 0x94 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ilvr.w $w18, $w20, $w21"
+  -
+    input:
+      bytes: [ 0x7a, 0xec, 0xf5, 0xd4 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ilvr.d $w23, $w30, $w12"
+  -
+    input:
+      bytes: [ 0x78, 0x9d, 0xfc, 0x52 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddv.b $w17, $w31, $w29"
+  -
+    input:
+      bytes: [ 0x78, 0xa9, 0xc1, 0xd2 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddv.h $w7, $w24, $w9"
+  -
+    input:
+      bytes: [ 0x78, 0xd4, 0xb5, 0x92 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddv.w $w22, $w22, $w20"
+  -
+    input:
+      bytes: [ 0x78, 0xf4, 0xd7, 0x92 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddv.d $w30, $w26, $w20"
+  -
+    input:
+      bytes: [ 0x7b, 0x17, 0x5d, 0xce ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "max_a.b $w23, $w11, $w23"
+  -
+    input:
+      bytes: [ 0x7b, 0x3e, 0x2d, 0x0e ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "max_a.h $w20, $w5, $w30"
+  -
+    input:
+      bytes: [ 0x7b, 0x5e, 0x91, 0xce ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "max_a.w $w7, $w18, $w30"
+  -
+    input:
+      bytes: [ 0x7b, 0x7f, 0x42, 0x0e ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "max_a.d $w8, $w8, $w31"
+  -
+    input:
+      bytes: [ 0x79, 0x13, 0x0a, 0x8e ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "max_s.b $w10, $w1, $w19"
+  -
+    input:
+      bytes: [ 0x79, 0x31, 0xeb, 0xce ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "max_s.h $w15, $w29, $w17"
+  -
+    input:
+      bytes: [ 0x79, 0x4e, 0xeb, 0xce ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "max_s.w $w15, $w29, $w14"
+  -
+    input:
+      bytes: [ 0x79, 0x63, 0xc6, 0x4e ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "max_s.d $w25, $w24, $w3"
+  -
+    input:
+      bytes: [ 0x79, 0x85, 0xc3, 0x0e ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "max_u.b $w12, $w24, $w5"
+  -
+    input:
+      bytes: [ 0x79, 0xa7, 0x31, 0x4e ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "max_u.h $w5, $w6, $w7"
+  -
+    input:
+      bytes: [ 0x79, 0xc7, 0x24, 0x0e ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "max_u.w $w16, $w4, $w7"
+  -
+    input:
+      bytes: [ 0x79, 0xf8, 0x66, 0x8e ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "max_u.d $w26, $w12, $w24"
+  -
+    input:
+      bytes: [ 0x7b, 0x81, 0xd1, 0x0e ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "min_a.b $w4, $w26, $w1"
+  -
+    input:
+      bytes: [ 0x7b, 0xbf, 0x6b, 0x0e ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "min_a.h $w12, $w13, $w31"
+  -
+    input:
+      bytes: [ 0x7b, 0xc0, 0xa7, 0x0e ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "min_a.w $w28, $w20, $w0"
+  -
+    input:
+      bytes: [ 0x7b, 0xf3, 0xa3, 0x0e ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "min_a.d $w12, $w20, $w19"
+  -
+    input:
+      bytes: [ 0x7a, 0x0e, 0x1c, 0xce ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "min_s.b $w19, $w3, $w14"
+  -
+    input:
+      bytes: [ 0x7a, 0x28, 0xae, 0xce ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "min_s.h $w27, $w21, $w8"
+  -
+    input:
+      bytes: [ 0x7a, 0x5e, 0x70, 0x0e ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "min_s.w $w0, $w14, $w30"
+  -
+    input:
+      bytes: [ 0x7a, 0x75, 0x41, 0x8e ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "min_s.d $w6, $w8, $w21"
+  -
+    input:
+      bytes: [ 0x7a, 0x88, 0xd5, 0x8e ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "min_u.b $w22, $w26, $w8"
+  -
+    input:
+      bytes: [ 0x7a, 0xac, 0xd9, 0xce ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "min_u.h $w7, $w27, $w12"
+  -
+    input:
+      bytes: [ 0x7a, 0xce, 0xa2, 0x0e ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "min_u.w $w8, $w20, $w14"
+  -
+    input:
+      bytes: [ 0x7a, 0xef, 0x76, 0x8e ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "min_u.d $w26, $w14, $w15"
+  -
+    input:
+      bytes: [ 0x7b, 0x1a, 0x0c, 0x92 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mod_s.b $w18, $w1, $w26"
+  -
+    input:
+      bytes: [ 0x7b, 0x3c, 0xf7, 0xd2 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mod_s.h $w31, $w30, $w28"
+  -
+    input:
+      bytes: [ 0x7b, 0x4d, 0x30, 0x92 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mod_s.w $w2, $w6, $w13"
+  -
+    input:
+      bytes: [ 0x7b, 0x76, 0xdd, 0x52 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mod_s.d $w21, $w27, $w22"
+  -
+    input:
+      bytes: [ 0x7b, 0x8d, 0x3c, 0x12 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mod_u.b $w16, $w7, $w13"
+  -
+    input:
+      bytes: [ 0x7b, 0xa7, 0x46, 0x12 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mod_u.h $w24, $w8, $w7"
+  -
+    input:
+      bytes: [ 0x7b, 0xd1, 0x17, 0x92 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mod_u.w $w30, $w2, $w17"
+  -
+    input:
+      bytes: [ 0x7b, 0xf9, 0x17, 0xd2 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mod_u.d $w31, $w2, $w25"
+  -
+    input:
+      bytes: [ 0x79, 0x0c, 0x2b, 0x92 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubv.b $w14, $w5, $w12"
+  -
+    input:
+      bytes: [ 0x79, 0x3e, 0x39, 0x92 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubv.h $w6, $w7, $w30"
+  -
+    input:
+      bytes: [ 0x79, 0x55, 0x13, 0x52 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubv.w $w13, $w2, $w21"
+  -
+    input:
+      bytes: [ 0x79, 0x7b, 0x74, 0x12 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubv.d $w16, $w14, $w27"
+  -
+    input:
+      bytes: [ 0x78, 0x0d, 0x1d, 0x12 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulv.b $w20, $w3, $w13"
+  -
+    input:
+      bytes: [ 0x78, 0x2e, 0xd6, 0xd2 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulv.h $w27, $w26, $w14"
+  -
+    input:
+      bytes: [ 0x78, 0x43, 0xea, 0x92 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulv.w $w10, $w29, $w3"
+  -
+    input:
+      bytes: [ 0x78, 0x7d, 0x99, 0xd2 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulv.d $w7, $w19, $w29"
+  -
+    input:
+      bytes: [ 0x79, 0x07, 0xd9, 0x54 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "pckev.b $w5, $w27, $w7"
+  -
+    input:
+      bytes: [ 0x79, 0x3b, 0x20, 0x54 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "pckev.h $w1, $w4, $w27"
+  -
+    input:
+      bytes: [ 0x79, 0x40, 0xa7, 0x94 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "pckev.w $w30, $w20, $w0"
+  -
+    input:
+      bytes: [ 0x79, 0x6f, 0x09, 0x94 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "pckev.d $w6, $w1, $w15"
+  -
+    input:
+      bytes: [ 0x79, 0x9e, 0xe4, 0x94 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "pckod.b $w18, $w28, $w30"
+  -
+    input:
+      bytes: [ 0x79, 0xa8, 0x2e, 0x94 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "pckod.h $w26, $w5, $w8"
+  -
+    input:
+      bytes: [ 0x79, 0xc2, 0x22, 0x54 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "pckod.w $w9, $w4, $w2"
+  -
+    input:
+      bytes: [ 0x79, 0xf4, 0xb7, 0x94 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "pckod.d $w30, $w22, $w20"
+  -
+    input:
+      bytes: [ 0x78, 0x0c, 0xb9, 0x54 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sld.b $w5, $w23[$t4]"
+  -
+    input:
+      bytes: [ 0x78, 0x23, 0xb8, 0x54 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sld.h $w1, $w23[$v1]"
+  -
+    input:
+      bytes: [ 0x78, 0x49, 0x45, 0x14 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sld.w $w20, $w8[$t1]"
+  -
+    input:
+      bytes: [ 0x78, 0x7e, 0xb9, 0xd4 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sld.d $w7, $w23[$fp]"
+  -
+    input:
+      bytes: [ 0x78, 0x11, 0x00, 0xcd ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sll.b $w3, $w0, $w17"
+  -
+    input:
+      bytes: [ 0x78, 0x23, 0xdc, 0x4d ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sll.h $w17, $w27, $w3"
+  -
+    input:
+      bytes: [ 0x78, 0x46, 0x3c, 0x0d ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sll.w $w16, $w7, $w6"
+  -
+    input:
+      bytes: [ 0x78, 0x7a, 0x02, 0x4d ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sll.d $w9, $w0, $w26"
+  -
+    input:
+      bytes: [ 0x78, 0x81, 0x0f, 0x14 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "splat.b $w28, $w1[$at]"
+  -
+    input:
+      bytes: [ 0x78, 0xab, 0x58, 0x94 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "splat.h $w2, $w11[$t3]"
+  -
+    input:
+      bytes: [ 0x78, 0xcb, 0x05, 0x94 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "splat.w $w22, $w0[$t3]"
+  -
+    input:
+      bytes: [ 0x78, 0xe2, 0x00, 0x14 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "splat.d $w0, $w0[$v0]"
+  -
+    input:
+      bytes: [ 0x78, 0x91, 0x27, 0x0d ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sra.b $w28, $w4, $w17"
+  -
+    input:
+      bytes: [ 0x78, 0xa3, 0x4b, 0x4d ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sra.h $w13, $w9, $w3"
+  -
+    input:
+      bytes: [ 0x78, 0xd3, 0xae, 0xcd ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sra.w $w27, $w21, $w19"
+  -
+    input:
+      bytes: [ 0x78, 0xf7, 0x47, 0x8d ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sra.d $w30, $w8, $w23"
+  -
+    input:
+      bytes: [ 0x78, 0x92, 0x94, 0xd5 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "srar.b $w19, $w18, $w18"
+  -
+    input:
+      bytes: [ 0x78, 0xa8, 0xb9, 0xd5 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "srar.h $w7, $w23, $w8"
+  -
+    input:
+      bytes: [ 0x78, 0xc2, 0x60, 0x55 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "srar.w $w1, $w12, $w2"
+  -
+    input:
+      bytes: [ 0x78, 0xee, 0x3d, 0x55 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "srar.d $w21, $w7, $w14"
+  -
+    input:
+      bytes: [ 0x79, 0x13, 0x1b, 0x0d ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "srl.b $w12, $w3, $w19"
+  -
+    input:
+      bytes: [ 0x79, 0x34, 0xfd, 0xcd ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "srl.h $w23, $w31, $w20"
+  -
+    input:
+      bytes: [ 0x79, 0x4b, 0xdc, 0x8d ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "srl.w $w18, $w27, $w11"
+  -
+    input:
+      bytes: [ 0x79, 0x7a, 0x60, 0xcd ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "srl.d $w3, $w12, $w26"
+  -
+    input:
+      bytes: [ 0x79, 0x0b, 0xab, 0xd5 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "srlr.b $w15, $w21, $w11"
+  -
+    input:
+      bytes: [ 0x79, 0x33, 0x6d, 0x55 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "srlr.h $w21, $w13, $w19"
+  -
+    input:
+      bytes: [ 0x79, 0x43, 0xf1, 0x95 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "srlr.w $w6, $w30, $w3"
+  -
+    input:
+      bytes: [ 0x79, 0x6e, 0x10, 0x55 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "srlr.d $w1, $w2, $w14"
+  -
+    input:
+      bytes: [ 0x78, 0x01, 0x7e, 0x51 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "subs_s.b $w25, $w15, $w1"
+  -
+    input:
+      bytes: [ 0x78, 0x36, 0xcf, 0x11 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "subs_s.h $w28, $w25, $w22"
+  -
+    input:
+      bytes: [ 0x78, 0x55, 0x62, 0x91 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "subs_s.w $w10, $w12, $w21"
+  -
+    input:
+      bytes: [ 0x78, 0x72, 0xa1, 0x11 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "subs_s.d $w4, $w20, $w18"
+  -
+    input:
+      bytes: [ 0x78, 0x99, 0x35, 0x51 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "subs_u.b $w21, $w6, $w25"
+  -
+    input:
+      bytes: [ 0x78, 0xa7, 0x50, 0xd1 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "subs_u.h $w3, $w10, $w7"
+  -
+    input:
+      bytes: [ 0x78, 0xca, 0x7a, 0x51 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "subs_u.w $w9, $w15, $w10"
+  -
+    input:
+      bytes: [ 0x78, 0xea, 0x99, 0xd1 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "subs_u.d $w7, $w19, $w10"
+  -
+    input:
+      bytes: [ 0x79, 0x0c, 0x39, 0x91 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "subsus_u.b $w6, $w7, $w12"
+  -
+    input:
+      bytes: [ 0x79, 0x33, 0xe9, 0x91 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "subsus_u.h $w6, $w29, $w19"
+  -
+    input:
+      bytes: [ 0x79, 0x47, 0x79, 0xd1 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "subsus_u.w $w7, $w15, $w7"
+  -
+    input:
+      bytes: [ 0x79, 0x6f, 0x1a, 0x51 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "subsus_u.d $w9, $w3, $w15"
+  -
+    input:
+      bytes: [ 0x79, 0x9f, 0x1d, 0x91 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "subsuu_s.b $w22, $w3, $w31"
+  -
+    input:
+      bytes: [ 0x79, 0xb6, 0xbc, 0xd1 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "subsuu_s.h $w19, $w23, $w22"
+  -
+    input:
+      bytes: [ 0x79, 0xcd, 0x52, 0x51 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "subsuu_s.w $w9, $w10, $w13"
+  -
+    input:
+      bytes: [ 0x79, 0xe0, 0x31, 0x51 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "subsuu_s.d $w5, $w6, $w0"
+  -
+    input:
+      bytes: [ 0x78, 0x93, 0x69, 0x8e ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "subv.b $w6, $w13, $w19"
+  -
+    input:
+      bytes: [ 0x78, 0xac, 0xc9, 0x0e ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "subv.h $w4, $w25, $w12"
+  -
+    input:
+      bytes: [ 0x78, 0xcb, 0xde, 0xce ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "subv.w $w27, $w27, $w11"
+  -
+    input:
+      bytes: [ 0x78, 0xea, 0xc2, 0x4e ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "subv.d $w9, $w24, $w10"
+  -
+    input:
+      bytes: [ 0x78, 0x05, 0x80, 0xd5 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vshf.b $w3, $w16, $w5"
+  -
+    input:
+      bytes: [ 0x78, 0x28, 0x9d, 0x15 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vshf.h $w20, $w19, $w8"
+  -
+    input:
+      bytes: [ 0x78, 0x59, 0xf4, 0x15 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vshf.w $w16, $w30, $w25"
+  -
+    input:
+      bytes: [ 0x78, 0x6f, 0x5c, 0xd5 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vshf.d $w19, $w11, $w15"
diff --git a/tests/MC/Mips/test_3rf.s.yaml b/tests/MC/Mips/test_3rf.s.yaml
new file mode 100644
index 000000000..31464d86a
--- /dev/null
+++ b/tests/MC/Mips/test_3rf.s.yaml
@@ -0,0 +1,739 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x78, 0x1c, 0x9f, 0x1b ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd.w $w28, $w19, $w28"
+  -
+    input:
+      bytes: [ 0x78, 0x3d, 0x13, 0x5b ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd.d $w13, $w2, $w29"
+  -
+    input:
+      bytes: [ 0x78, 0x19, 0x5b, 0x9a ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcaf.w $w14, $w11, $w25"
+  -
+    input:
+      bytes: [ 0x78, 0x33, 0x08, 0x5a ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcaf.d $w1, $w1, $w19"
+  -
+    input:
+      bytes: [ 0x78, 0x90, 0xb8, 0x5a ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fceq.w $w1, $w23, $w16"
+  -
+    input:
+      bytes: [ 0x78, 0xb0, 0x40, 0x1a ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fceq.d $w0, $w8, $w16"
+  -
+    input:
+      bytes: [ 0x79, 0x98, 0x4c, 0x1a ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcle.w $w16, $w9, $w24"
+  -
+    input:
+      bytes: [ 0x79, 0xa1, 0x76, 0xda ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcle.d $w27, $w14, $w1"
+  -
+    input:
+      bytes: [ 0x79, 0x08, 0x47, 0x1a ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fclt.w $w28, $w8, $w8"
+  -
+    input:
+      bytes: [ 0x79, 0x2b, 0xcf, 0x9a ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fclt.d $w30, $w25, $w11"
+  -
+    input:
+      bytes: [ 0x78, 0xd7, 0x90, 0x9c ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcne.w $w2, $w18, $w23"
+  -
+    input:
+      bytes: [ 0x78, 0xef, 0xa3, 0x9c ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcne.d $w14, $w20, $w15"
+  -
+    input:
+      bytes: [ 0x78, 0x59, 0x92, 0x9c ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcor.w $w10, $w18, $w25"
+  -
+    input:
+      bytes: [ 0x78, 0x6b, 0xcc, 0x5c ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcor.d $w17, $w25, $w11"
+  -
+    input:
+      bytes: [ 0x78, 0xd5, 0x13, 0x9a ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcueq.w $w14, $w2, $w21"
+  -
+    input:
+      bytes: [ 0x78, 0xe7, 0x1f, 0x5a ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcueq.d $w29, $w3, $w7"
+  -
+    input:
+      bytes: [ 0x79, 0xc3, 0x2c, 0x5a ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcule.w $w17, $w5, $w3"
+  -
+    input:
+      bytes: [ 0x79, 0xfe, 0x0f, 0xda ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcule.d $w31, $w1, $w30"
+  -
+    input:
+      bytes: [ 0x79, 0x49, 0xc9, 0x9a ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcult.w $w6, $w25, $w9"
+  -
+    input:
+      bytes: [ 0x79, 0x71, 0x46, 0xda ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcult.d $w27, $w8, $w17"
+  -
+    input:
+      bytes: [ 0x78, 0x48, 0xa1, 0x1a ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcun.w $w4, $w20, $w8"
+  -
+    input:
+      bytes: [ 0x78, 0x63, 0x5f, 0x5a ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcun.d $w29, $w11, $w3"
+  -
+    input:
+      bytes: [ 0x78, 0x93, 0x93, 0x5c ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcune.w $w13, $w18, $w19"
+  -
+    input:
+      bytes: [ 0x78, 0xb5, 0xd4, 0x1c ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcune.d $w16, $w26, $w21"
+  -
+    input:
+      bytes: [ 0x78, 0xc2, 0xc3, 0x5b ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdiv.w $w13, $w24, $w2"
+  -
+    input:
+      bytes: [ 0x78, 0xf9, 0x24, 0xdb ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdiv.d $w19, $w4, $w25"
+  -
+    input:
+      bytes: [ 0x7a, 0x10, 0x02, 0x1b ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fexdo.h $w8, $w0, $w16"
+  -
+    input:
+      bytes: [ 0x7a, 0x3b, 0x68, 0x1b ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fexdo.w $w0, $w13, $w27"
+  -
+    input:
+      bytes: [ 0x79, 0xc3, 0x04, 0x5b ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fexp2.w $w17, $w0, $w3"
+  -
+    input:
+      bytes: [ 0x79, 0xea, 0x05, 0x9b ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fexp2.d $w22, $w0, $w10"
+  -
+    input:
+      bytes: [ 0x79, 0x17, 0x37, 0x5b ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmadd.w $w29, $w6, $w23"
+  -
+    input:
+      bytes: [ 0x79, 0x35, 0xe2, 0xdb ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmadd.d $w11, $w28, $w21"
+  -
+    input:
+      bytes: [ 0x7b, 0x8d, 0xb8, 0x1b ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmax.w $w0, $w23, $w13"
+  -
+    input:
+      bytes: [ 0x7b, 0xa8, 0x96, 0x9b ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmax.d $w26, $w18, $w8"
+  -
+    input:
+      bytes: [ 0x7b, 0xca, 0x82, 0x9b ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmax_a.w $w10, $w16, $w10"
+  -
+    input:
+      bytes: [ 0x7b, 0xf6, 0x4f, 0x9b ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmax_a.d $w30, $w9, $w22"
+  -
+    input:
+      bytes: [ 0x7b, 0x1e, 0x0e, 0x1b ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmin.w $w24, $w1, $w30"
+  -
+    input:
+      bytes: [ 0x7b, 0x2a, 0xde, 0xdb ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmin.d $w27, $w27, $w10"
+  -
+    input:
+      bytes: [ 0x7b, 0x54, 0xea, 0x9b ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmin_a.w $w10, $w29, $w20"
+  -
+    input:
+      bytes: [ 0x7b, 0x78, 0xf3, 0x5b ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmin_a.d $w13, $w30, $w24"
+  -
+    input:
+      bytes: [ 0x79, 0x40, 0xcc, 0x5b ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmsub.w $w17, $w25, $w0"
+  -
+    input:
+      bytes: [ 0x79, 0x70, 0x92, 0x1b ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmsub.d $w8, $w18, $w16"
+  -
+    input:
+      bytes: [ 0x78, 0x8f, 0x78, 0xdb ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmul.w $w3, $w15, $w15"
+  -
+    input:
+      bytes: [ 0x78, 0xaa, 0xf2, 0x5b ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmul.d $w9, $w30, $w10"
+  -
+    input:
+      bytes: [ 0x7a, 0x0a, 0x2e, 0x5a ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsaf.w $w25, $w5, $w10"
+  -
+    input:
+      bytes: [ 0x7a, 0x3d, 0x1e, 0x5a ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsaf.d $w25, $w3, $w29"
+  -
+    input:
+      bytes: [ 0x7a, 0x8d, 0x8a, 0xda ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fseq.w $w11, $w17, $w13"
+  -
+    input:
+      bytes: [ 0x7a, 0xbf, 0x07, 0x5a ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fseq.d $w29, $w0, $w31"
+  -
+    input:
+      bytes: [ 0x7b, 0x9f, 0xff, 0x9a ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsle.w $w30, $w31, $w31"
+  -
+    input:
+      bytes: [ 0x7b, 0xb8, 0xbc, 0x9a ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsle.d $w18, $w23, $w24"
+  -
+    input:
+      bytes: [ 0x7b, 0x06, 0x2b, 0x1a ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fslt.w $w12, $w5, $w6"
+  -
+    input:
+      bytes: [ 0x7b, 0x35, 0xd4, 0x1a ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fslt.d $w16, $w26, $w21"
+  -
+    input:
+      bytes: [ 0x7a, 0xcc, 0x0f, 0x9c ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsne.w $w30, $w1, $w12"
+  -
+    input:
+      bytes: [ 0x7a, 0xf7, 0x6b, 0x9c ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsne.d $w14, $w13, $w23"
+  -
+    input:
+      bytes: [ 0x7a, 0x5b, 0x6e, 0xdc ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsor.w $w27, $w13, $w27"
+  -
+    input:
+      bytes: [ 0x7a, 0x6b, 0xc3, 0x1c ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsor.d $w12, $w24, $w11"
+  -
+    input:
+      bytes: [ 0x78, 0x41, 0xd7, 0xdb ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub.w $w31, $w26, $w1"
+  -
+    input:
+      bytes: [ 0x78, 0x7b, 0x8c, 0xdb ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub.d $w19, $w17, $w27"
+  -
+    input:
+      bytes: [ 0x7a, 0xd9, 0xc4, 0x1a ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsueq.w $w16, $w24, $w25"
+  -
+    input:
+      bytes: [ 0x7a, 0xee, 0x74, 0x9a ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsueq.d $w18, $w14, $w14"
+  -
+    input:
+      bytes: [ 0x7b, 0xcd, 0xf5, 0xda ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsule.w $w23, $w30, $w13"
+  -
+    input:
+      bytes: [ 0x7b, 0xfa, 0x58, 0x9a ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsule.d $w2, $w11, $w26"
+  -
+    input:
+      bytes: [ 0x7b, 0x56, 0xd2, 0xda ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsult.w $w11, $w26, $w22"
+  -
+    input:
+      bytes: [ 0x7b, 0x7e, 0xb9, 0x9a ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsult.d $w6, $w23, $w30"
+  -
+    input:
+      bytes: [ 0x7a, 0x5c, 0x90, 0xda ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsun.w $w3, $w18, $w28"
+  -
+    input:
+      bytes: [ 0x7a, 0x73, 0x5c, 0x9a ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsun.d $w18, $w11, $w19"
+  -
+    input:
+      bytes: [ 0x7a, 0x82, 0xfc, 0x1c ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsune.w $w16, $w31, $w2"
+  -
+    input:
+      bytes: [ 0x7a, 0xb1, 0xd0, 0xdc ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsune.d $w3, $w26, $w17"
+  -
+    input:
+      bytes: [ 0x7a, 0x98, 0x24, 0x1b ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ftq.h $w16, $w4, $w24"
+  -
+    input:
+      bytes: [ 0x7a, 0xb9, 0x29, 0x5b ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ftq.w $w5, $w5, $w25"
+  -
+    input:
+      bytes: [ 0x79, 0x4a, 0xa4, 0x1c ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd_q.h $w16, $w20, $w10"
+  -
+    input:
+      bytes: [ 0x79, 0x69, 0x17, 0x1c ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd_q.w $w28, $w2, $w9"
+  -
+    input:
+      bytes: [ 0x7b, 0x49, 0x92, 0x1c ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddr_q.h $w8, $w18, $w9"
+  -
+    input:
+      bytes: [ 0x7b, 0x70, 0x67, 0x5c ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddr_q.w $w29, $w12, $w16"
+  -
+    input:
+      bytes: [ 0x79, 0x8a, 0xd6, 0x1c ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub_q.h $w24, $w26, $w10"
+  -
+    input:
+      bytes: [ 0x79, 0xbc, 0xf3, 0x5c ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub_q.w $w13, $w30, $w28"
+  -
+    input:
+      bytes: [ 0x7b, 0x8b, 0xab, 0x1c ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubr_q.h $w12, $w21, $w11"
+  -
+    input:
+      bytes: [ 0x7b, 0xb4, 0x70, 0x5c ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubr_q.w $w1, $w14, $w20"
+  -
+    input:
+      bytes: [ 0x79, 0x1e, 0x81, 0x9c ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul_q.h $w6, $w16, $w30"
+  -
+    input:
+      bytes: [ 0x79, 0x24, 0x0c, 0x1c ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul_q.w $w16, $w1, $w4"
+  -
+    input:
+      bytes: [ 0x7b, 0x13, 0xa1, 0x9c ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulr_q.h $w6, $w20, $w19"
+  -
+    input:
+      bytes: [ 0x7b, 0x34, 0x0e, 0xdc ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulr_q.w $w27, $w1, $w20"
diff --git a/tests/MC/Mips/test_bit.s.yaml b/tests/MC/Mips/test_bit.s.yaml
new file mode 100644
index 000000000..e650c7bdb
--- /dev/null
+++ b/tests/MC/Mips/test_bit.s.yaml
@@ -0,0 +1,433 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x79, 0xf2, 0xf5, 0x49 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bclri.b $w21, $w30, 2"
+  -
+    input:
+      bytes: [ 0x79, 0xe0, 0xae, 0x09 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bclri.h $w24, $w21, 0"
+  -
+    input:
+      bytes: [ 0x79, 0xc3, 0xf5, 0xc9 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bclri.w $w23, $w30, 3"
+  -
+    input:
+      bytes: [ 0x79, 0x80, 0x5a, 0x49 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bclri.d $w9, $w11, 0"
+  -
+    input:
+      bytes: [ 0x7b, 0x71, 0x66, 0x49 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "binsli.b $w25, $w12, 1"
+  -
+    input:
+      bytes: [ 0x7b, 0x60, 0xb5, 0x49 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "binsli.h $w21, $w22, 0"
+  -
+    input:
+      bytes: [ 0x7b, 0x40, 0x25, 0x89 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "binsli.w $w22, $w4, 0"
+  -
+    input:
+      bytes: [ 0x7b, 0x06, 0x11, 0x89 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "binsli.d $w6, $w2, 6"
+  -
+    input:
+      bytes: [ 0x7b, 0xf0, 0x9b, 0xc9 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "binsri.b $w15, $w19, 0"
+  -
+    input:
+      bytes: [ 0x7b, 0xe1, 0xf2, 0x09 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "binsri.h $w8, $w30, 1"
+  -
+    input:
+      bytes: [ 0x7b, 0xc5, 0x98, 0x89 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "binsri.w $w2, $w19, 5"
+  -
+    input:
+      bytes: [ 0x7b, 0x81, 0xa4, 0x89 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "binsri.d $w18, $w20, 1"
+  -
+    input:
+      bytes: [ 0x7a, 0xf0, 0x9e, 0x09 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bnegi.b $w24, $w19, 0"
+  -
+    input:
+      bytes: [ 0x7a, 0xe3, 0x5f, 0x09 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bnegi.h $w28, $w11, 3"
+  -
+    input:
+      bytes: [ 0x7a, 0xc5, 0xd8, 0x49 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bnegi.w $w1, $w27, 5"
+  -
+    input:
+      bytes: [ 0x7a, 0x81, 0xa9, 0x09 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bnegi.d $w4, $w21, 1"
+  -
+    input:
+      bytes: [ 0x7a, 0x70, 0x44, 0x89 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bseti.b $w18, $w8, 0"
+  -
+    input:
+      bytes: [ 0x7a, 0x62, 0x76, 0x09 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bseti.h $w24, $w14, 2"
+  -
+    input:
+      bytes: [ 0x7a, 0x44, 0x92, 0x49 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bseti.w $w9, $w18, 4"
+  -
+    input:
+      bytes: [ 0x7a, 0x01, 0x79, 0xc9 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bseti.d $w7, $w15, 1"
+  -
+    input:
+      bytes: [ 0x78, 0x72, 0xff, 0xca ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sat_s.b $w31, $w31, 2"
+  -
+    input:
+      bytes: [ 0x78, 0x60, 0x9c, 0xca ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sat_s.h $w19, $w19, 0"
+  -
+    input:
+      bytes: [ 0x78, 0x40, 0xec, 0xca ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sat_s.w $w19, $w29, 0"
+  -
+    input:
+      bytes: [ 0x78, 0x00, 0xb2, 0xca ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sat_s.d $w11, $w22, 0"
+  -
+    input:
+      bytes: [ 0x78, 0xf3, 0x68, 0x4a ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sat_u.b $w1, $w13, 3"
+  -
+    input:
+      bytes: [ 0x78, 0xe4, 0xc7, 0x8a ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sat_u.h $w30, $w24, 4"
+  -
+    input:
+      bytes: [ 0x78, 0xc0, 0x6f, 0xca ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sat_u.w $w31, $w13, 0"
+  -
+    input:
+      bytes: [ 0x78, 0x85, 0x87, 0x4a ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sat_u.d $w29, $w16, 5"
+  -
+    input:
+      bytes: [ 0x78, 0x71, 0x55, 0xc9 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "slli.b $w23, $w10, 1"
+  -
+    input:
+      bytes: [ 0x78, 0x61, 0x92, 0x49 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "slli.h $w9, $w18, 1"
+  -
+    input:
+      bytes: [ 0x78, 0x44, 0xea, 0xc9 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "slli.w $w11, $w29, 4"
+  -
+    input:
+      bytes: [ 0x78, 0x01, 0xa6, 0x49 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "slli.d $w25, $w20, 1"
+  -
+    input:
+      bytes: [ 0x78, 0xf1, 0xee, 0x09 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "srai.b $w24, $w29, 1"
+  -
+    input:
+      bytes: [ 0x78, 0xe0, 0x30, 0x49 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "srai.h $w1, $w6, 0"
+  -
+    input:
+      bytes: [ 0x78, 0xc1, 0xd1, 0xc9 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "srai.w $w7, $w26, 1"
+  -
+    input:
+      bytes: [ 0x78, 0x83, 0xcd, 0x09 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "srai.d $w20, $w25, 3"
+  -
+    input:
+      bytes: [ 0x79, 0x70, 0xc9, 0x4a ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "srari.b $w5, $w25, 0"
+  -
+    input:
+      bytes: [ 0x79, 0x64, 0x31, 0xca ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "srari.h $w7, $w6, 4"
+  -
+    input:
+      bytes: [ 0x79, 0x45, 0x5c, 0x4a ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "srari.w $w17, $w11, 5"
+  -
+    input:
+      bytes: [ 0x79, 0x05, 0xcd, 0x4a ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "srari.d $w21, $w25, 5"
+  -
+    input:
+      bytes: [ 0x79, 0x72, 0x00, 0x89 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "srli.b $w2, $w0, 2"
+  -
+    input:
+      bytes: [ 0x79, 0x62, 0xff, 0xc9 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "srli.h $w31, $w31, 2"
+  -
+    input:
+      bytes: [ 0x79, 0x44, 0x49, 0x49 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "srli.w $w5, $w9, 4"
+  -
+    input:
+      bytes: [ 0x79, 0x05, 0xd6, 0xc9 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "srli.d $w27, $w26, 5"
+  -
+    input:
+      bytes: [ 0x79, 0xf0, 0x1c, 0x8a ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "srlri.b $w18, $w3, 0"
+  -
+    input:
+      bytes: [ 0x79, 0xe3, 0x10, 0x4a ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "srlri.h $w1, $w2, 3"
+  -
+    input:
+      bytes: [ 0x79, 0xc2, 0xb2, 0xca ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "srlri.w $w11, $w22, 2"
+  -
+    input:
+      bytes: [ 0x79, 0x86, 0x56, 0x0a ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "srlri.d $w24, $w10, 6"
diff --git a/tests/MC/Mips/test_ctrlregs.s.yaml b/tests/MC/Mips/test_ctrlregs.s.yaml
new file mode 100644
index 000000000..4f051220b
--- /dev/null
+++ b/tests/MC/Mips/test_ctrlregs.s.yaml
@@ -0,0 +1,289 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x78, 0x7e, 0x00, 0x59 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cfcmsa $at, $0"
+  -
+    input:
+      bytes: [ 0x78, 0x7e, 0x00, 0x59 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cfcmsa $at, $0"
+  -
+    input:
+      bytes: [ 0x78, 0x7e, 0x08, 0x99 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cfcmsa $v0, $1"
+  -
+    input:
+      bytes: [ 0x78, 0x7e, 0x08, 0x99 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cfcmsa $v0, $1"
+  -
+    input:
+      bytes: [ 0x78, 0x7e, 0x10, 0xd9 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cfcmsa $v1, $2"
+  -
+    input:
+      bytes: [ 0x78, 0x7e, 0x10, 0xd9 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cfcmsa $v1, $2"
+  -
+    input:
+      bytes: [ 0x78, 0x7e, 0x19, 0x19 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cfcmsa $a0, $3"
+  -
+    input:
+      bytes: [ 0x78, 0x7e, 0x19, 0x19 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cfcmsa $a0, $3"
+  -
+    input:
+      bytes: [ 0x78, 0x7e, 0x21, 0x59 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cfcmsa $a1, $4"
+  -
+    input:
+      bytes: [ 0x78, 0x7e, 0x21, 0x59 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cfcmsa $a1, $4"
+  -
+    input:
+      bytes: [ 0x78, 0x7e, 0x29, 0x99 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cfcmsa $a2, $5"
+  -
+    input:
+      bytes: [ 0x78, 0x7e, 0x29, 0x99 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cfcmsa $a2, $5"
+  -
+    input:
+      bytes: [ 0x78, 0x7e, 0x31, 0xd9 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cfcmsa $a3, $6"
+  -
+    input:
+      bytes: [ 0x78, 0x7e, 0x31, 0xd9 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cfcmsa $a3, $6"
+  -
+    input:
+      bytes: [ 0x78, 0x7e, 0x3a, 0x19 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cfcmsa $t0, $7"
+  -
+    input:
+      bytes: [ 0x78, 0x7e, 0x3a, 0x19 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cfcmsa $t0, $7"
+  -
+    input:
+      bytes: [ 0x78, 0x3e, 0x08, 0x19 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ctcmsa $0, $at"
+  -
+    input:
+      bytes: [ 0x78, 0x3e, 0x08, 0x19 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ctcmsa $0, $at"
+  -
+    input:
+      bytes: [ 0x78, 0x3e, 0x10, 0x59 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ctcmsa $1, $v0"
+  -
+    input:
+      bytes: [ 0x78, 0x3e, 0x10, 0x59 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ctcmsa $1, $v0"
+  -
+    input:
+      bytes: [ 0x78, 0x3e, 0x18, 0x99 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ctcmsa $2, $v1"
+  -
+    input:
+      bytes: [ 0x78, 0x3e, 0x18, 0x99 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ctcmsa $2, $v1"
+  -
+    input:
+      bytes: [ 0x78, 0x3e, 0x20, 0xd9 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ctcmsa $3, $a0"
+  -
+    input:
+      bytes: [ 0x78, 0x3e, 0x20, 0xd9 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ctcmsa $3, $a0"
+  -
+    input:
+      bytes: [ 0x78, 0x3e, 0x29, 0x19 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ctcmsa $4, $a1"
+  -
+    input:
+      bytes: [ 0x78, 0x3e, 0x29, 0x19 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ctcmsa $4, $a1"
+  -
+    input:
+      bytes: [ 0x78, 0x3e, 0x31, 0x59 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ctcmsa $5, $a2"
+  -
+    input:
+      bytes: [ 0x78, 0x3e, 0x31, 0x59 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ctcmsa $5, $a2"
+  -
+    input:
+      bytes: [ 0x78, 0x3e, 0x39, 0x99 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ctcmsa $6, $a3"
+  -
+    input:
+      bytes: [ 0x78, 0x3e, 0x39, 0x99 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ctcmsa $6, $a3"
+  -
+    input:
+      bytes: [ 0x78, 0x3e, 0x41, 0xd9 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ctcmsa $7, $t0"
+  -
+    input:
+      bytes: [ 0x78, 0x3e, 0x41, 0xd9 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ctcmsa $7, $t0"
diff --git a/tests/MC/Mips/test_elm.s.yaml b/tests/MC/Mips/test_elm.s.yaml
new file mode 100644
index 000000000..9ad7c3d49
--- /dev/null
+++ b/tests/MC/Mips/test_elm.s.yaml
@@ -0,0 +1,136 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x78, 0x82, 0x43, 0x59 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "copy_s.b $t5, $w8[2]"
+  -
+    input:
+      bytes: [ 0x78, 0xa0, 0xc8, 0x59 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "copy_s.h $at, $w25[0]"
+  -
+    input:
+      bytes: [ 0x78, 0xb1, 0x2d, 0x99 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "copy_s.w $s6, $w5[1]"
+  -
+    input:
+      bytes: [ 0x78, 0xc4, 0xa5, 0x99 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "copy_u.b $s6, $w20[4]"
+  -
+    input:
+      bytes: [ 0x78, 0xe0, 0x25, 0x19 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "copy_u.h $s4, $w4[0]"
+  -
+    input:
+      bytes: [ 0x78, 0xf2, 0x6f, 0x99 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "copy_u.w $fp, $w13[2]"
+  -
+    input:
+      bytes: [ 0x78, 0x04, 0xe8, 0x19 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sldi.b $w0, $w29[4]"
+  -
+    input:
+      bytes: [ 0x78, 0x20, 0x8a, 0x19 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sldi.h $w8, $w17[0]"
+  -
+    input:
+      bytes: [ 0x78, 0x32, 0xdd, 0x19 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sldi.w $w20, $w27[2]"
+  -
+    input:
+      bytes: [ 0x78, 0x38, 0x61, 0x19 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sldi.d $w4, $w12[0]"
+  -
+    input:
+      bytes: [ 0x78, 0x42, 0x1e, 0x59 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "splati.b $w25, $w3[2]"
+  -
+    input:
+      bytes: [ 0x78, 0x61, 0xe6, 0x19 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "splati.h $w24, $w28[1]"
+  -
+    input:
+      bytes: [ 0x78, 0x70, 0x93, 0x59 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "splati.w $w13, $w18[0]"
+  -
+    input:
+      bytes: [ 0x78, 0x78, 0x0f, 0x19 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "splati.d $w28, $w1[0]"
+  -
+    input:
+      bytes: [ 0x78, 0xbe, 0xc5, 0xd9 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "move.v $w23, $w24"
diff --git a/tests/MC/Mips/test_elm_insert.s.yaml b/tests/MC/Mips/test_elm_insert.s.yaml
new file mode 100644
index 000000000..71820d17a
--- /dev/null
+++ b/tests/MC/Mips/test_elm_insert.s.yaml
@@ -0,0 +1,28 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x79, 0x03, 0xed, 0xd9 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert.b $w23[3], $sp"
+  -
+    input:
+      bytes: [ 0x79, 0x22, 0x2d, 0x19 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert.h $w20[2], $a1"
+  -
+    input:
+      bytes: [ 0x79, 0x32, 0x7a, 0x19 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert.w $w8[2], $t7"
diff --git a/tests/MC/Mips/test_elm_insve.s.yaml b/tests/MC/Mips/test_elm_insve.s.yaml
new file mode 100644
index 000000000..6943ea869
--- /dev/null
+++ b/tests/MC/Mips/test_elm_insve.s.yaml
@@ -0,0 +1,37 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x79, 0x43, 0x4e, 0x59 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "insve.b $w25[3], $w9[0]"
+  -
+    input:
+      bytes: [ 0x79, 0x62, 0x16, 0x19 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "insve.h $w24[2], $w2[0]"
+  -
+    input:
+      bytes: [ 0x79, 0x72, 0x68, 0x19 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "insve.w $w0[2], $w13[0]"
+  -
+    input:
+      bytes: [ 0x79, 0x78, 0x90, 0xd9 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "insve.d $w3[0], $w18[0]"
diff --git a/tests/MC/Mips/test_i10.s.yaml b/tests/MC/Mips/test_i10.s.yaml
new file mode 100644
index 000000000..a49decba2
--- /dev/null
+++ b/tests/MC/Mips/test_i10.s.yaml
@@ -0,0 +1,28 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x7b, 0x06, 0x32, 0x07 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldi.b $w8, 198"
+  -
+    input:
+      bytes: [ 0x7b, 0x29, 0xcd, 0x07 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldi.h $w20, 313"
+  -
+    input:
+      bytes: [ 0x7b, 0x4f, 0x66, 0x07 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldi.w $w24, 492"
diff --git a/tests/MC/Mips/test_i5.s.yaml b/tests/MC/Mips/test_i5.s.yaml
new file mode 100644
index 000000000..bcc32a637
--- /dev/null
+++ b/tests/MC/Mips/test_i5.s.yaml
@@ -0,0 +1,289 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x78, 0x1e, 0xf8, 0xc6 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "addvi.b $w3, $w31, 30"
+  -
+    input:
+      bytes: [ 0x78, 0x3a, 0x6e, 0x06 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "addvi.h $w24, $w13, 26"
+  -
+    input:
+      bytes: [ 0x78, 0x5a, 0xa6, 0x86 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "addvi.w $w26, $w20, 26"
+  -
+    input:
+      bytes: [ 0x78, 0x75, 0x0c, 0x06 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "addvi.d $w16, $w1, 21"
+  -
+    input:
+      bytes: [ 0x78, 0x22, 0x7f, 0xc7 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ceqi.h $w31, $w15, 2"
+  -
+    input:
+      bytes: [ 0x78, 0x67, 0xb6, 0x07 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ceqi.d $w24, $w22, 7"
+  -
+    input:
+      bytes: [ 0x7a, 0x01, 0x83, 0x07 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "clei_s.b $w12, $w16, 1"
+  -
+    input:
+      bytes: [ 0x7a, 0x83, 0x8d, 0x47 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "clei_u.b $w21, $w17, 3"
+  -
+    input:
+      bytes: [ 0x7a, 0xb1, 0x3f, 0x47 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "clei_u.h $w29, $w7, 17"
+  -
+    input:
+      bytes: [ 0x7a, 0xc2, 0x08, 0x47 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "clei_u.w $w1, $w1, 2"
+  -
+    input:
+      bytes: [ 0x7a, 0xfd, 0xde, 0xc7 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "clei_u.d $w27, $w27, 29"
+  -
+    input:
+      bytes: [ 0x79, 0x4b, 0x63, 0x07 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "clti_s.w $w12, $w12, 11"
+  -
+    input:
+      bytes: [ 0x79, 0x9d, 0x4b, 0x87 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "clti_u.b $w14, $w9, 29"
+  -
+    input:
+      bytes: [ 0x79, 0xb9, 0xce, 0x07 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "clti_u.h $w24, $w25, 25"
+  -
+    input:
+      bytes: [ 0x79, 0xd6, 0x08, 0x47 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "clti_u.w $w1, $w1, 22"
+  -
+    input:
+      bytes: [ 0x79, 0xe1, 0xcd, 0x47 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "clti_u.d $w21, $w25, 1"
+  -
+    input:
+      bytes: [ 0x79, 0x01, 0xad, 0x86 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "maxi_s.b $w22, $w21, 1"
+  -
+    input:
+      bytes: [ 0x79, 0x8c, 0x05, 0x06 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "maxi_u.b $w20, $w0, 12"
+  -
+    input:
+      bytes: [ 0x79, 0xa3, 0x70, 0x46 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "maxi_u.h $w1, $w14, 3"
+  -
+    input:
+      bytes: [ 0x79, 0xcb, 0xb6, 0xc6 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "maxi_u.w $w27, $w22, 11"
+  -
+    input:
+      bytes: [ 0x79, 0xe4, 0x36, 0x86 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "maxi_u.d $w26, $w6, 4"
+  -
+    input:
+      bytes: [ 0x7a, 0x01, 0x09, 0x06 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mini_s.b $w4, $w1, 1"
+  -
+    input:
+      bytes: [ 0x7a, 0x49, 0x5f, 0x06 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mini_s.w $w28, $w11, 9"
+  -
+    input:
+      bytes: [ 0x7a, 0x6a, 0x52, 0xc6 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mini_s.d $w11, $w10, 10"
+  -
+    input:
+      bytes: [ 0x7a, 0x9b, 0xbc, 0x86 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mini_u.b $w18, $w23, 27"
+  -
+    input:
+      bytes: [ 0x7a, 0xb2, 0xd1, 0xc6 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mini_u.h $w7, $w26, 18"
+  -
+    input:
+      bytes: [ 0x7a, 0xda, 0x62, 0xc6 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mini_u.w $w11, $w12, 26"
+  -
+    input:
+      bytes: [ 0x7a, 0xe2, 0x7a, 0xc6 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mini_u.d $w11, $w15, 2"
+  -
+    input:
+      bytes: [ 0x78, 0x93, 0xa6, 0x06 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "subvi.b $w24, $w20, 19"
+  -
+    input:
+      bytes: [ 0x78, 0xa4, 0x9a, 0xc6 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "subvi.h $w11, $w19, 4"
+  -
+    input:
+      bytes: [ 0x78, 0xcb, 0x53, 0x06 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "subvi.w $w12, $w10, 11"
+  -
+    input:
+      bytes: [ 0x78, 0xe7, 0x84, 0xc6 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "subvi.d $w19, $w16, 7"
diff --git a/tests/MC/Mips/test_i8.s.yaml b/tests/MC/Mips/test_i8.s.yaml
new file mode 100644
index 000000000..7b5435217
--- /dev/null
+++ b/tests/MC/Mips/test_i8.s.yaml
@@ -0,0 +1,91 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x78, 0x30, 0xe8, 0x80 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "andi.b $w2, $w29, 48"
+  -
+    input:
+      bytes: [ 0x78, 0x7e, 0xb1, 0x81 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bmnzi.b $w6, $w22, 126"
+  -
+    input:
+      bytes: [ 0x79, 0x58, 0x0e, 0xc1 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bmzi.b $w27, $w1, 88"
+  -
+    input:
+      bytes: [ 0x7a, 0xbd, 0x1f, 0x41 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bseli.b $w29, $w3, 189"
+  -
+    input:
+      bytes: [ 0x7a, 0x38, 0x88, 0x40 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "nori.b $w1, $w17, 56"
+  -
+    input:
+      bytes: [ 0x79, 0x87, 0xa6, 0x80 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ori.b $w26, $w20, 135"
+  -
+    input:
+      bytes: [ 0x78, 0x69, 0xf4, 0xc2 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "shf.b $w19, $w30, 105"
+  -
+    input:
+      bytes: [ 0x79, 0x4c, 0x44, 0x42 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "shf.h $w17, $w8, 76"
+  -
+    input:
+      bytes: [ 0x7a, 0x5d, 0x1b, 0x82 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "shf.w $w14, $w3, 93"
+  -
+    input:
+      bytes: [ 0x7b, 0x14, 0x54, 0x00 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "xori.b $w16, $w10, 20"
diff --git a/tests/MC/Mips/test_lsa.s.yaml b/tests/MC/Mips/test_lsa.s.yaml
new file mode 100644
index 000000000..002c4dc2d
--- /dev/null
+++ b/tests/MC/Mips/test_lsa.s.yaml
@@ -0,0 +1,37 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x01, 0x2a, 0x40, 0x05 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsa $t0, $t1, $t2, 1"
+  -
+    input:
+      bytes: [ 0x01, 0x2a, 0x40, 0x45 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsa $t0, $t1, $t2, 2"
+  -
+    input:
+      bytes: [ 0x01, 0x2a, 0x40, 0x85 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsa $t0, $t1, $t2, 3"
+  -
+    input:
+      bytes: [ 0x01, 0x2a, 0x40, 0xc5 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "lsa $t0, $t1, $t2, 4"
diff --git a/tests/MC/Mips/test_mi10.s.yaml b/tests/MC/Mips/test_mi10.s.yaml
new file mode 100644
index 000000000..83aeb82f7
--- /dev/null
+++ b/tests/MC/Mips/test_mi10.s.yaml
@@ -0,0 +1,208 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x7a, 0x00, 0x08, 0x20 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.b $w0, -512($at)"
+  -
+    input:
+      bytes: [ 0x78, 0x00, 0x10, 0x60 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.b $w1, ($v0)"
+  -
+    input:
+      bytes: [ 0x79, 0xff, 0x18, 0xa0 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.b $w2, 511($v1)"
+  -
+    input:
+      bytes: [ 0x7a, 0x00, 0x20, 0xe1 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.h $w3, -1024($a0)"
+  -
+    input:
+      bytes: [ 0x7b, 0x00, 0x29, 0x21 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.h $w4, -512($a1)"
+  -
+    input:
+      bytes: [ 0x78, 0x00, 0x31, 0x61 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.h $w5, ($a2)"
+  -
+    input:
+      bytes: [ 0x79, 0x00, 0x39, 0xa1 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.h $w6, 512($a3)"
+  -
+    input:
+      bytes: [ 0x79, 0xff, 0x41, 0xe1 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.h $w7, 1022($t0)"
+  -
+    input:
+      bytes: [ 0x7a, 0x00, 0x4a, 0x22 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w $w8, -2048($t1)"
+  -
+    input:
+      bytes: [ 0x7b, 0x00, 0x52, 0x62 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w $w9, -1024($t2)"
+  -
+    input:
+      bytes: [ 0x7b, 0x80, 0x5a, 0xa2 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w $w10, -512($t3)"
+  -
+    input:
+      bytes: [ 0x78, 0x80, 0x62, 0xe2 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w $w11, 512($t4)"
+  -
+    input:
+      bytes: [ 0x79, 0x00, 0x6b, 0x22 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w $w12, 1024($t5)"
+  -
+    input:
+      bytes: [ 0x79, 0xff, 0x73, 0x62 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w $w13, 2044($t6)"
+  -
+    input:
+      bytes: [ 0x7a, 0x00, 0x7b, 0xa3 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.d $w14, -4096($t7)"
+  -
+    input:
+      bytes: [ 0x7b, 0x00, 0x83, 0xe3 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.d $w15, -2048($s0)"
+  -
+    input:
+      bytes: [ 0x7b, 0x80, 0x8c, 0x23 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.d $w16, -1024($s1)"
+  -
+    input:
+      bytes: [ 0x7b, 0xc0, 0x94, 0x63 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.d $w17, -512($s2)"
+  -
+    input:
+      bytes: [ 0x78, 0x00, 0x9c, 0xa3 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.d $w18, ($s3)"
+  -
+    input:
+      bytes: [ 0x78, 0x40, 0xa4, 0xe3 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.d $w19, 512($s4)"
+  -
+    input:
+      bytes: [ 0x78, 0x80, 0xad, 0x23 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.d $w20, 1024($s5)"
+  -
+    input:
+      bytes: [ 0x79, 0x00, 0xb5, 0x63 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.d $w21, 2048($s6)"
+  -
+    input:
+      bytes: [ 0x79, 0xff, 0xbd, 0xa3 ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.d $w22, 4088($s7)"
diff --git a/tests/MC/Mips/test_vec.s.yaml b/tests/MC/Mips/test_vec.s.yaml
new file mode 100644
index 000000000..34c4d2c68
--- /dev/null
+++ b/tests/MC/Mips/test_vec.s.yaml
@@ -0,0 +1,64 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x78, 0x1b, 0xa6, 0x5e ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.v $w25, $w20, $w27"
+  -
+    input:
+      bytes: [ 0x78, 0x87, 0x34, 0x5e ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bmnz.v $w17, $w6, $w7"
+  -
+    input:
+      bytes: [ 0x78, 0xa9, 0x88, 0xde ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bmz.v $w3, $w17, $w9"
+  -
+    input:
+      bytes: [ 0x78, 0xce, 0x02, 0x1e ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bsel.v $w8, $w0, $w14"
+  -
+    input:
+      bytes: [ 0x78, 0x40, 0xf9, 0xde ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "nor.v $w7, $w31, $w0"
+  -
+    input:
+      bytes: [ 0x78, 0x3e, 0xd6, 0x1e ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.v $w24, $w26, $w30"
+  -
+    input:
+      bytes: [ 0x78, 0x6f, 0xd9, 0xde ]
+      arch: "CS_ARCH_MIPS"
+      options: [ "CS_MODE_MIPS32", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor.v $w7, $w27, $w15"
diff --git a/tests/MC/PowerPC/ppc64-encoding-bookII.s.yaml b/tests/MC/PowerPC/ppc64-encoding-bookII.s.yaml
new file mode 100644
index 000000000..0aac7c46c
--- /dev/null
+++ b/tests/MC/PowerPC/ppc64-encoding-bookII.s.yaml
@@ -0,0 +1,163 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x7c, 0x02, 0x1f, 0xac ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "icbi 2, 3"
+  -
+    input:
+      bytes: [ 0x7c, 0x02, 0x1a, 0x2c ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "dcbt 2, 3"
+  -
+    input:
+      bytes: [ 0x7c, 0x02, 0x19, 0xec ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "dcbtst 2, 3"
+  -
+    input:
+      bytes: [ 0x7c, 0x02, 0x1f, 0xec ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "dcbz 2, 3"
+  -
+    input:
+      bytes: [ 0x7c, 0x02, 0x18, 0x6c ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "dcbst 2, 3"
+  -
+    input:
+      bytes: [ 0x4c, 0x00, 0x01, 0x2c ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "isync"
+  -
+    input:
+      bytes: [ 0x7c, 0x43, 0x21, 0x2d ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "stwcx. 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x43, 0x21, 0xad ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "stdcx. 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x00, 0x06, 0xac ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "eieio"
+  -
+    input:
+      bytes: [ 0x7c, 0x02, 0x18, 0xac ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "dcbf 2, 3"
+  -
+    input:
+      bytes: [ 0x7c, 0x43, 0x20, 0x28 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "lwarx 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x43, 0x20, 0xa8 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldarx 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x00, 0x04, 0xac ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sync"
+  -
+    input:
+      bytes: [ 0x7c, 0x20, 0x04, 0xac ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "lwsync"
+  -
+    input:
+      bytes: [ 0x7c, 0x40, 0x04, 0xac ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ptesync"
+  -
+    input:
+      bytes: [ 0x7c, 0x5b, 0x1a, 0xe6 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mftb 2, 123"
+  -
+    input:
+      bytes: [ 0x7c, 0x4c, 0x42, 0xe6 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mftb 2, 268"
+  -
+    input:
+      bytes: [ 0x7c, 0x4d, 0x42, 0xe6 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mftbu 2"
diff --git a/tests/MC/PowerPC/ppc64-encoding-bookIII.s.yaml b/tests/MC/PowerPC/ppc64-encoding-bookIII.s.yaml
new file mode 100644
index 000000000..4552729fa
--- /dev/null
+++ b/tests/MC/PowerPC/ppc64-encoding-bookIII.s.yaml
@@ -0,0 +1,505 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x4c, 0x00, 0x02, 0x24 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "", "CS_MODE_BOOKE", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "hrfid"
+  -
+    input:
+      bytes: [ 0x4c, 0x00, 0x03, 0x64 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "", "CS_MODE_BOOKE", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "nap"
+  -
+    input:
+      bytes: [ 0x7c, 0x80, 0x01, 0x24 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "", "CS_MODE_BOOKE", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mtmsr 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x81, 0x01, 0x24 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "", "CS_MODE_BOOKE", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mtmsr 4, 1"
+  -
+    input:
+      bytes: [ 0x7c, 0x80, 0x00, 0xa6 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "", "CS_MODE_BOOKE", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mfmsr 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x80, 0x01, 0x64 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "", "CS_MODE_BOOKE", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mtmsrd 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x81, 0x01, 0x64 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "", "CS_MODE_BOOKE", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mtmsrd 4, 1"
+  -
+    input:
+      bytes: [ 0x7c, 0x84, 0x42, 0xa6 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "", "CS_MODE_BOOKE", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mfspr 4, 260"
+  -
+    input:
+      bytes: [ 0x7c, 0x85, 0x42, 0xa6 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "", "CS_MODE_BOOKE", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mfspr 4, 261"
+  -
+    input:
+      bytes: [ 0x7c, 0x86, 0x42, 0xa6 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "", "CS_MODE_BOOKE", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mfspr 4, 262"
+  -
+    input:
+      bytes: [ 0x7c, 0x87, 0x42, 0xa6 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "", "CS_MODE_BOOKE", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mfspr 4, 263"
+  -
+    input:
+      bytes: [ 0x7c, 0x44, 0x42, 0xa6 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "", "CS_MODE_BOOKE", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mfspr 2, 260"
+  -
+    input:
+      bytes: [ 0x7c, 0x45, 0x42, 0xa6 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "", "CS_MODE_BOOKE", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mfspr 2, 261"
+  -
+    input:
+      bytes: [ 0x7c, 0x46, 0x42, 0xa6 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "", "CS_MODE_BOOKE", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mfspr 2, 262"
+  -
+    input:
+      bytes: [ 0x7c, 0x47, 0x42, 0xa6 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "", "CS_MODE_BOOKE", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mfspr 2, 263"
+  -
+    input:
+      bytes: [ 0x7c, 0x90, 0x43, 0xa6 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "", "CS_MODE_BOOKE", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mtspr 272, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x91, 0x43, 0xa6 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "", "CS_MODE_BOOKE", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mtspr 273, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x92, 0x43, 0xa6 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "", "CS_MODE_BOOKE", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mtspr 274, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x93, 0x43, 0xa6 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "", "CS_MODE_BOOKE", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mtspr 275, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x84, 0x43, 0xa6 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "", "CS_MODE_BOOKE", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mtspr 260, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x85, 0x43, 0xa6 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "", "CS_MODE_BOOKE", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mtspr 261, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x86, 0x43, 0xa6 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "", "CS_MODE_BOOKE", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mtspr 262, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x87, 0x43, 0xa6 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "", "CS_MODE_BOOKE", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mtspr 263, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x98, 0x43, 0xa6 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "", "CS_MODE_BOOKE", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mtasr 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x96, 0x02, 0xa6 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "", "CS_MODE_BOOKE", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mfdec 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x96, 0x03, 0xa6 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "", "CS_MODE_BOOKE", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mtdec 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x9f, 0x42, 0xa6 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "", "CS_MODE_BOOKE", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mfpvr 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x99, 0x02, 0xa6 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "", "CS_MODE_BOOKE", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mfsdr1 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x99, 0x03, 0xa6 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "", "CS_MODE_BOOKE", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mtsdr1 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x9a, 0x02, 0xa6 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "", "CS_MODE_BOOKE", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mfsrr0 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x9a, 0x03, 0xa6 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "", "CS_MODE_BOOKE", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mtsrr0 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x9b, 0x02, 0xa6 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "", "CS_MODE_BOOKE", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mfsrr1 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x9b, 0x03, 0xa6 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "", "CS_MODE_BOOKE", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mtsrr1 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x00, 0x23, 0x64 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "", "CS_MODE_BOOKE", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "slbie 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x80, 0x2b, 0x24 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "", "CS_MODE_BOOKE", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "slbmte 4, 5"
+  -
+    input:
+      bytes: [ 0x7c, 0x80, 0x2f, 0x26 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "", "CS_MODE_BOOKE", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "slbmfee 4, 5"
+  -
+    input:
+      bytes: [ 0x7c, 0x40, 0x1e, 0xa6 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "", "CS_MODE_BOOKE", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "slbmfev 2, 3"
+  -
+    input:
+      bytes: [ 0x7c, 0x00, 0x03, 0xe4 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "", "CS_MODE_BOOKE", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "slbia"
+  -
+    input:
+      bytes: [ 0x7c, 0x80, 0x2f, 0xa7 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "", "CS_MODE_BOOKE", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "slbfee. 4, 5"
+  -
+    input:
+      bytes: [ 0x7c, 0x00, 0x04, 0x6c ]
+      arch: "CS_ARCH_PPC"
+      options: [ "", "CS_MODE_BOOKE", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "tlbsync"
+  -
+    input:
+      bytes: [ 0x7c, 0x00, 0x22, 0x24 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "", "CS_MODE_BOOKE", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "tlbiel 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x00, 0x22, 0x64 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "", "CS_MODE_BOOKE", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "tlbie 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x00, 0x22, 0x64 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "", "CS_MODE_BOOKE", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "tlbie 4"
+  -
+    input:
+      bytes: [ 0x4c, 0x00, 0x00, 0x64 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "", "CS_MODE_BOOKE", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "rfi"
+  -
+    input:
+      bytes: [ 0x4c, 0x00, 0x00, 0x66 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "", "CS_MODE_BOOKE", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "rfci"
+  -
+    input:
+      bytes: [ 0x7d, 0x80, 0x01, 0x06 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "", "CS_MODE_BOOKE", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "wrtee 12"
+  -
+    input:
+      bytes: [ 0x7c, 0x00, 0x01, 0x46 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "", "CS_MODE_BOOKE", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "wrteei 0"
+  -
+    input:
+      bytes: [ 0x7c, 0x00, 0x81, 0x46 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "", "CS_MODE_BOOKE", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "wrteei 1"
+  -
+    input:
+      bytes: [ 0x7c, 0x00, 0x07, 0x64 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "", "CS_MODE_BOOKE", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "tlbre"
+  -
+    input:
+      bytes: [ 0x7c, 0x00, 0x07, 0xa4 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "", "CS_MODE_BOOKE", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "tlbwe"
+  -
+    input:
+      bytes: [ 0x7c, 0x0b, 0x66, 0x24 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "", "CS_MODE_BOOKE", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "tlbivax 11, 12"
+  -
+    input:
+      bytes: [ 0x7c, 0x0b, 0x67, 0x24 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "", "CS_MODE_BOOKE", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "tlbsx 11, 12"
+  -
+    input:
+      bytes: [ 0x7c, 0xb0, 0x62, 0x9c ]
+      arch: "CS_ARCH_PPC"
+      options: [ "", "CS_MODE_BOOKE", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mfpmr 5, 400"
+  -
+    input:
+      bytes: [ 0x7c, 0xd0, 0x63, 0x9c ]
+      arch: "CS_ARCH_PPC"
+      options: [ "", "CS_MODE_BOOKE", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mtpmr 400, 6"
+  -
+    input:
+      bytes: [ 0x7c, 0x00, 0x41, 0xcc ]
+      arch: "CS_ARCH_PPC"
+      options: [ "", "CS_MODE_BOOKE", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "icblc 0, 0, 8"
+  -
+    input:
+      bytes: [ 0x7c, 0x00, 0x4b, 0xcc ]
+      arch: "CS_ARCH_PPC"
+      options: [ "", "CS_MODE_BOOKE", "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "icbtls 0, 0, 9"
diff --git a/tests/MC/PowerPC/ppc64-encoding-ext.s.yaml b/tests/MC/PowerPC/ppc64-encoding-ext.s.yaml
new file mode 100644
index 000000000..23152c22f
--- /dev/null
+++ b/tests/MC/PowerPC/ppc64-encoding-ext.s.yaml
@@ -0,0 +1,5356 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x4d, 0x82, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btlr 2"
+  -
+    input:
+      bytes: [ 0x4d, 0x86, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btlr 6"
+  -
+    input:
+      bytes: [ 0x4d, 0x8a, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btlr 10"
+  -
+    input:
+      bytes: [ 0x4d, 0x8e, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btlr 14"
+  -
+    input:
+      bytes: [ 0x4d, 0x92, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btlr 18"
+  -
+    input:
+      bytes: [ 0x4d, 0x96, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btlr 22"
+  -
+    input:
+      bytes: [ 0x4d, 0x9a, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btlr 26"
+  -
+    input:
+      bytes: [ 0x4d, 0x9e, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btlr 30"
+  -
+    input:
+      bytes: [ 0x4d, 0x80, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btlr 0"
+  -
+    input:
+      bytes: [ 0x4d, 0x81, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btlr 1"
+  -
+    input:
+      bytes: [ 0x4d, 0x82, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btlr 2"
+  -
+    input:
+      bytes: [ 0x4d, 0x83, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btlr 3"
+  -
+    input:
+      bytes: [ 0x4d, 0x83, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btlr 3"
+  -
+    input:
+      bytes: [ 0x4d, 0x84, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btlr 4"
+  -
+    input:
+      bytes: [ 0x4d, 0x85, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btlr 5"
+  -
+    input:
+      bytes: [ 0x4d, 0x86, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btlr 6"
+  -
+    input:
+      bytes: [ 0x4d, 0x87, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btlr 7"
+  -
+    input:
+      bytes: [ 0x4d, 0x87, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btlr 7"
+  -
+    input:
+      bytes: [ 0x4d, 0x88, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btlr 8"
+  -
+    input:
+      bytes: [ 0x4d, 0x89, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btlr 9"
+  -
+    input:
+      bytes: [ 0x4d, 0x8a, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btlr 10"
+  -
+    input:
+      bytes: [ 0x4d, 0x8b, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btlr 11"
+  -
+    input:
+      bytes: [ 0x4d, 0x8b, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btlr 11"
+  -
+    input:
+      bytes: [ 0x4d, 0x8c, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btlr 12"
+  -
+    input:
+      bytes: [ 0x4d, 0x8d, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btlr 13"
+  -
+    input:
+      bytes: [ 0x4d, 0x8e, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btlr 14"
+  -
+    input:
+      bytes: [ 0x4d, 0x8f, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btlr 15"
+  -
+    input:
+      bytes: [ 0x4d, 0x8f, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btlr 15"
+  -
+    input:
+      bytes: [ 0x4d, 0x90, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btlr 16"
+  -
+    input:
+      bytes: [ 0x4d, 0x91, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btlr 17"
+  -
+    input:
+      bytes: [ 0x4d, 0x92, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btlr 18"
+  -
+    input:
+      bytes: [ 0x4d, 0x93, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btlr 19"
+  -
+    input:
+      bytes: [ 0x4d, 0x93, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btlr 19"
+  -
+    input:
+      bytes: [ 0x4d, 0x94, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btlr 20"
+  -
+    input:
+      bytes: [ 0x4d, 0x95, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btlr 21"
+  -
+    input:
+      bytes: [ 0x4d, 0x96, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btlr 22"
+  -
+    input:
+      bytes: [ 0x4d, 0x97, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btlr 23"
+  -
+    input:
+      bytes: [ 0x4d, 0x97, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btlr 23"
+  -
+    input:
+      bytes: [ 0x4d, 0x98, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btlr 24"
+  -
+    input:
+      bytes: [ 0x4d, 0x99, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btlr 25"
+  -
+    input:
+      bytes: [ 0x4d, 0x9a, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btlr 26"
+  -
+    input:
+      bytes: [ 0x4d, 0x9b, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btlr 27"
+  -
+    input:
+      bytes: [ 0x4d, 0x9b, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btlr 27"
+  -
+    input:
+      bytes: [ 0x4d, 0x9c, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btlr 28"
+  -
+    input:
+      bytes: [ 0x4d, 0x9d, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btlr 29"
+  -
+    input:
+      bytes: [ 0x4d, 0x9e, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btlr 30"
+  -
+    input:
+      bytes: [ 0x4d, 0x9f, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btlr 31"
+  -
+    input:
+      bytes: [ 0x4d, 0x9f, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btlr 31"
+  -
+    input:
+      bytes: [ 0x4e, 0x80, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "blr"
+  -
+    input:
+      bytes: [ 0x4e, 0x80, 0x04, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bctrl"
+  -
+    input:
+      bytes: [ 0x4d, 0x82, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btlr 2"
+  -
+    input:
+      bytes: [ 0x4d, 0x82, 0x04, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btctr 2"
+  -
+    input:
+      bytes: [ 0x4d, 0x82, 0x00, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btlrl 2"
+  -
+    input:
+      bytes: [ 0x4d, 0x82, 0x04, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btctrl 2"
+  -
+    input:
+      bytes: [ 0x4d, 0xe2, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btlr+ 2"
+  -
+    input:
+      bytes: [ 0x4d, 0xe2, 0x04, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btctr+ 2"
+  -
+    input:
+      bytes: [ 0x4d, 0xe2, 0x00, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btlrl+ 2"
+  -
+    input:
+      bytes: [ 0x4d, 0xe2, 0x04, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btctrl+ 2"
+  -
+    input:
+      bytes: [ 0x4d, 0xc2, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btlr- 2"
+  -
+    input:
+      bytes: [ 0x4d, 0xc2, 0x04, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btctr- 2"
+  -
+    input:
+      bytes: [ 0x4d, 0xc2, 0x00, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btlrl- 2"
+  -
+    input:
+      bytes: [ 0x4d, 0xc2, 0x04, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btctrl- 2"
+  -
+    input:
+      bytes: [ 0x4c, 0x82, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bflr 2"
+  -
+    input:
+      bytes: [ 0x4c, 0x82, 0x04, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfctr 2"
+  -
+    input:
+      bytes: [ 0x4c, 0x82, 0x00, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bflrl 2"
+  -
+    input:
+      bytes: [ 0x4c, 0x82, 0x04, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfctrl 2"
+  -
+    input:
+      bytes: [ 0x4c, 0xe2, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bflr+ 2"
+  -
+    input:
+      bytes: [ 0x4c, 0xe2, 0x04, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfctr+ 2"
+  -
+    input:
+      bytes: [ 0x4c, 0xe2, 0x00, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bflrl+ 2"
+  -
+    input:
+      bytes: [ 0x4c, 0xe2, 0x04, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfctrl+ 2"
+  -
+    input:
+      bytes: [ 0x4c, 0xc2, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bflr- 2"
+  -
+    input:
+      bytes: [ 0x4c, 0xc2, 0x04, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfctr- 2"
+  -
+    input:
+      bytes: [ 0x4c, 0xc2, 0x00, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bflrl- 2"
+  -
+    input:
+      bytes: [ 0x4c, 0xc2, 0x04, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfctrl- 2"
+  -
+    input:
+      bytes: [ 0x4d, 0x02, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bdnztlr 2"
+  -
+    input:
+      bytes: [ 0x4d, 0x02, 0x00, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bdnztlrl 2"
+  -
+    input:
+      bytes: [ 0x4c, 0x02, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bdnzflr 2"
+  -
+    input:
+      bytes: [ 0x4c, 0x02, 0x00, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bdnzflrl 2"
+  -
+    input:
+      bytes: [ 0x4d, 0x42, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bdztlr 2"
+  -
+    input:
+      bytes: [ 0x4d, 0x42, 0x00, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bdztlrl 2"
+  -
+    input:
+      bytes: [ 0x4c, 0x42, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bdzflr 2"
+  -
+    input:
+      bytes: [ 0x4c, 0x42, 0x00, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bdzflrl 2"
+  -
+    input:
+      bytes: [ 0x4d, 0x88, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btlr 8"
+  -
+    input:
+      bytes: [ 0x4d, 0x80, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btlr 0"
+  -
+    input:
+      bytes: [ 0x4d, 0x88, 0x04, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btctr 8"
+  -
+    input:
+      bytes: [ 0x4d, 0x80, 0x04, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btctr 0"
+  -
+    input:
+      bytes: [ 0x4d, 0x88, 0x00, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btlrl 8"
+  -
+    input:
+      bytes: [ 0x4d, 0x80, 0x00, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btlrl 0"
+  -
+    input:
+      bytes: [ 0x4d, 0x88, 0x04, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btctrl 8"
+  -
+    input:
+      bytes: [ 0x4d, 0x80, 0x04, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btctrl 0"
+  -
+    input:
+      bytes: [ 0x4d, 0xe8, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btlr+ 8"
+  -
+    input:
+      bytes: [ 0x4d, 0xe0, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btlr+ 0"
+  -
+    input:
+      bytes: [ 0x4d, 0xe8, 0x04, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btctr+ 8"
+  -
+    input:
+      bytes: [ 0x4d, 0xe0, 0x04, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btctr+ 0"
+  -
+    input:
+      bytes: [ 0x4d, 0xe8, 0x00, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btlrl+ 8"
+  -
+    input:
+      bytes: [ 0x4d, 0xe0, 0x00, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btlrl+ 0"
+  -
+    input:
+      bytes: [ 0x4d, 0xe8, 0x04, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btctrl+ 8"
+  -
+    input:
+      bytes: [ 0x4d, 0xe0, 0x04, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btctrl+ 0"
+  -
+    input:
+      bytes: [ 0x4d, 0xc8, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btlr- 8"
+  -
+    input:
+      bytes: [ 0x4d, 0xc0, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btlr- 0"
+  -
+    input:
+      bytes: [ 0x4d, 0xc8, 0x04, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btctr- 8"
+  -
+    input:
+      bytes: [ 0x4d, 0xc0, 0x04, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btctr- 0"
+  -
+    input:
+      bytes: [ 0x4d, 0xc8, 0x00, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btlrl- 8"
+  -
+    input:
+      bytes: [ 0x4d, 0xc0, 0x00, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btlrl- 0"
+  -
+    input:
+      bytes: [ 0x4d, 0xc8, 0x04, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btctrl- 8"
+  -
+    input:
+      bytes: [ 0x4d, 0xc0, 0x04, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btctrl- 0"
+  -
+    input:
+      bytes: [ 0x4c, 0x89, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bflr 9"
+  -
+    input:
+      bytes: [ 0x4c, 0x81, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bflr 1"
+  -
+    input:
+      bytes: [ 0x4c, 0x89, 0x04, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfctr 9"
+  -
+    input:
+      bytes: [ 0x4c, 0x81, 0x04, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfctr 1"
+  -
+    input:
+      bytes: [ 0x4c, 0x89, 0x00, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bflrl 9"
+  -
+    input:
+      bytes: [ 0x4c, 0x81, 0x00, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bflrl 1"
+  -
+    input:
+      bytes: [ 0x4c, 0x89, 0x04, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfctrl 9"
+  -
+    input:
+      bytes: [ 0x4c, 0x81, 0x04, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfctrl 1"
+  -
+    input:
+      bytes: [ 0x4c, 0xe9, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bflr+ 9"
+  -
+    input:
+      bytes: [ 0x4c, 0xe1, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bflr+ 1"
+  -
+    input:
+      bytes: [ 0x4c, 0xe9, 0x04, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfctr+ 9"
+  -
+    input:
+      bytes: [ 0x4c, 0xe1, 0x04, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfctr+ 1"
+  -
+    input:
+      bytes: [ 0x4c, 0xe9, 0x00, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bflrl+ 9"
+  -
+    input:
+      bytes: [ 0x4c, 0xe1, 0x00, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bflrl+ 1"
+  -
+    input:
+      bytes: [ 0x4c, 0xe9, 0x04, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfctrl+ 9"
+  -
+    input:
+      bytes: [ 0x4c, 0xe1, 0x04, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfctrl+ 1"
+  -
+    input:
+      bytes: [ 0x4c, 0xc9, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bflr- 9"
+  -
+    input:
+      bytes: [ 0x4c, 0xc1, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bflr- 1"
+  -
+    input:
+      bytes: [ 0x4c, 0xc9, 0x04, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfctr- 9"
+  -
+    input:
+      bytes: [ 0x4c, 0xc1, 0x04, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfctr- 1"
+  -
+    input:
+      bytes: [ 0x4c, 0xc9, 0x00, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bflrl- 9"
+  -
+    input:
+      bytes: [ 0x4c, 0xc1, 0x00, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bflrl- 1"
+  -
+    input:
+      bytes: [ 0x4c, 0xc9, 0x04, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfctrl- 9"
+  -
+    input:
+      bytes: [ 0x4c, 0xc1, 0x04, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfctrl- 1"
+  -
+    input:
+      bytes: [ 0x4d, 0x8a, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btlr 10"
+  -
+    input:
+      bytes: [ 0x4d, 0x82, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btlr 2"
+  -
+    input:
+      bytes: [ 0x4d, 0x8a, 0x04, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btctr 10"
+  -
+    input:
+      bytes: [ 0x4d, 0x82, 0x04, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btctr 2"
+  -
+    input:
+      bytes: [ 0x4d, 0x8a, 0x00, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btlrl 10"
+  -
+    input:
+      bytes: [ 0x4d, 0x82, 0x00, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btlrl 2"
+  -
+    input:
+      bytes: [ 0x4d, 0x8a, 0x04, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btctrl 10"
+  -
+    input:
+      bytes: [ 0x4d, 0x82, 0x04, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btctrl 2"
+  -
+    input:
+      bytes: [ 0x4d, 0xea, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btlr+ 10"
+  -
+    input:
+      bytes: [ 0x4d, 0xe2, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btlr+ 2"
+  -
+    input:
+      bytes: [ 0x4d, 0xea, 0x04, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btctr+ 10"
+  -
+    input:
+      bytes: [ 0x4d, 0xe2, 0x04, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btctr+ 2"
+  -
+    input:
+      bytes: [ 0x4d, 0xea, 0x00, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btlrl+ 10"
+  -
+    input:
+      bytes: [ 0x4d, 0xe2, 0x00, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btlrl+ 2"
+  -
+    input:
+      bytes: [ 0x4d, 0xea, 0x04, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btctrl+ 10"
+  -
+    input:
+      bytes: [ 0x4d, 0xe2, 0x04, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btctrl+ 2"
+  -
+    input:
+      bytes: [ 0x4d, 0xca, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btlr- 10"
+  -
+    input:
+      bytes: [ 0x4d, 0xc2, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btlr- 2"
+  -
+    input:
+      bytes: [ 0x4d, 0xca, 0x04, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btctr- 10"
+  -
+    input:
+      bytes: [ 0x4d, 0xc2, 0x04, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btctr- 2"
+  -
+    input:
+      bytes: [ 0x4d, 0xca, 0x00, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btlrl- 10"
+  -
+    input:
+      bytes: [ 0x4d, 0xc2, 0x00, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btlrl- 2"
+  -
+    input:
+      bytes: [ 0x4d, 0xca, 0x04, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btctrl- 10"
+  -
+    input:
+      bytes: [ 0x4d, 0xc2, 0x04, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btctrl- 2"
+  -
+    input:
+      bytes: [ 0x4c, 0x88, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bflr 8"
+  -
+    input:
+      bytes: [ 0x4c, 0x80, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bflr 0"
+  -
+    input:
+      bytes: [ 0x4c, 0x88, 0x04, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfctr 8"
+  -
+    input:
+      bytes: [ 0x4c, 0x80, 0x04, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfctr 0"
+  -
+    input:
+      bytes: [ 0x4c, 0x88, 0x00, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bflrl 8"
+  -
+    input:
+      bytes: [ 0x4c, 0x80, 0x00, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bflrl 0"
+  -
+    input:
+      bytes: [ 0x4c, 0x88, 0x04, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfctrl 8"
+  -
+    input:
+      bytes: [ 0x4c, 0x80, 0x04, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfctrl 0"
+  -
+    input:
+      bytes: [ 0x4c, 0xe8, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bflr+ 8"
+  -
+    input:
+      bytes: [ 0x4c, 0xe0, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bflr+ 0"
+  -
+    input:
+      bytes: [ 0x4c, 0xe8, 0x04, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfctr+ 8"
+  -
+    input:
+      bytes: [ 0x4c, 0xe0, 0x04, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfctr+ 0"
+  -
+    input:
+      bytes: [ 0x4c, 0xe8, 0x00, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bflrl+ 8"
+  -
+    input:
+      bytes: [ 0x4c, 0xe0, 0x00, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bflrl+ 0"
+  -
+    input:
+      bytes: [ 0x4c, 0xe8, 0x04, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfctrl+ 8"
+  -
+    input:
+      bytes: [ 0x4c, 0xe0, 0x04, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfctrl+ 0"
+  -
+    input:
+      bytes: [ 0x4c, 0xc8, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bflr- 8"
+  -
+    input:
+      bytes: [ 0x4c, 0xc0, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bflr- 0"
+  -
+    input:
+      bytes: [ 0x4c, 0xc8, 0x04, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfctr- 8"
+  -
+    input:
+      bytes: [ 0x4c, 0xc0, 0x04, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfctr- 0"
+  -
+    input:
+      bytes: [ 0x4c, 0xc8, 0x00, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bflrl- 8"
+  -
+    input:
+      bytes: [ 0x4c, 0xc0, 0x00, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bflrl- 0"
+  -
+    input:
+      bytes: [ 0x4c, 0xc8, 0x04, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfctrl- 8"
+  -
+    input:
+      bytes: [ 0x4c, 0xc0, 0x04, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfctrl- 0"
+  -
+    input:
+      bytes: [ 0x4d, 0x89, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btlr 9"
+  -
+    input:
+      bytes: [ 0x4d, 0x81, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btlr 1"
+  -
+    input:
+      bytes: [ 0x4d, 0x89, 0x04, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btctr 9"
+  -
+    input:
+      bytes: [ 0x4d, 0x81, 0x04, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btctr 1"
+  -
+    input:
+      bytes: [ 0x4d, 0x89, 0x00, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btlrl 9"
+  -
+    input:
+      bytes: [ 0x4d, 0x81, 0x00, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btlrl 1"
+  -
+    input:
+      bytes: [ 0x4d, 0x89, 0x04, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btctrl 9"
+  -
+    input:
+      bytes: [ 0x4d, 0x81, 0x04, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btctrl 1"
+  -
+    input:
+      bytes: [ 0x4d, 0xe9, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btlr+ 9"
+  -
+    input:
+      bytes: [ 0x4d, 0xe1, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btlr+ 1"
+  -
+    input:
+      bytes: [ 0x4d, 0xe9, 0x04, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btctr+ 9"
+  -
+    input:
+      bytes: [ 0x4d, 0xe1, 0x04, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btctr+ 1"
+  -
+    input:
+      bytes: [ 0x4d, 0xe9, 0x00, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btlrl+ 9"
+  -
+    input:
+      bytes: [ 0x4d, 0xe1, 0x00, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btlrl+ 1"
+  -
+    input:
+      bytes: [ 0x4d, 0xe9, 0x04, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btctrl+ 9"
+  -
+    input:
+      bytes: [ 0x4d, 0xe1, 0x04, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btctrl+ 1"
+  -
+    input:
+      bytes: [ 0x4d, 0xc9, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btlr- 9"
+  -
+    input:
+      bytes: [ 0x4d, 0xc1, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btlr- 1"
+  -
+    input:
+      bytes: [ 0x4d, 0xc9, 0x04, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btctr- 9"
+  -
+    input:
+      bytes: [ 0x4d, 0xc1, 0x04, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btctr- 1"
+  -
+    input:
+      bytes: [ 0x4d, 0xc9, 0x00, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btlrl- 9"
+  -
+    input:
+      bytes: [ 0x4d, 0xc1, 0x00, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btlrl- 1"
+  -
+    input:
+      bytes: [ 0x4d, 0xc9, 0x04, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btctrl- 9"
+  -
+    input:
+      bytes: [ 0x4d, 0xc1, 0x04, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btctrl- 1"
+  -
+    input:
+      bytes: [ 0x4c, 0x88, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bflr 8"
+  -
+    input:
+      bytes: [ 0x4c, 0x80, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bflr 0"
+  -
+    input:
+      bytes: [ 0x4c, 0x88, 0x04, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfctr 8"
+  -
+    input:
+      bytes: [ 0x4c, 0x80, 0x04, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfctr 0"
+  -
+    input:
+      bytes: [ 0x4c, 0x88, 0x00, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bflrl 8"
+  -
+    input:
+      bytes: [ 0x4c, 0x80, 0x00, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bflrl 0"
+  -
+    input:
+      bytes: [ 0x4c, 0x88, 0x04, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfctrl 8"
+  -
+    input:
+      bytes: [ 0x4c, 0x80, 0x04, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfctrl 0"
+  -
+    input:
+      bytes: [ 0x4c, 0xe8, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bflr+ 8"
+  -
+    input:
+      bytes: [ 0x4c, 0xe0, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bflr+ 0"
+  -
+    input:
+      bytes: [ 0x4c, 0xe8, 0x04, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfctr+ 8"
+  -
+    input:
+      bytes: [ 0x4c, 0xe0, 0x04, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfctr+ 0"
+  -
+    input:
+      bytes: [ 0x4c, 0xe8, 0x00, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bflrl+ 8"
+  -
+    input:
+      bytes: [ 0x4c, 0xe0, 0x00, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bflrl+ 0"
+  -
+    input:
+      bytes: [ 0x4c, 0xe8, 0x04, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfctrl+ 8"
+  -
+    input:
+      bytes: [ 0x4c, 0xe0, 0x04, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfctrl+ 0"
+  -
+    input:
+      bytes: [ 0x4c, 0xc8, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bflr- 8"
+  -
+    input:
+      bytes: [ 0x4c, 0xc0, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bflr- 0"
+  -
+    input:
+      bytes: [ 0x4c, 0xc8, 0x04, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfctr- 8"
+  -
+    input:
+      bytes: [ 0x4c, 0xc0, 0x04, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfctr- 0"
+  -
+    input:
+      bytes: [ 0x4c, 0xc8, 0x00, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bflrl- 8"
+  -
+    input:
+      bytes: [ 0x4c, 0xc0, 0x00, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bflrl- 0"
+  -
+    input:
+      bytes: [ 0x4c, 0xc8, 0x04, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfctrl- 8"
+  -
+    input:
+      bytes: [ 0x4c, 0xc0, 0x04, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfctrl- 0"
+  -
+    input:
+      bytes: [ 0x4c, 0x8a, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bflr 10"
+  -
+    input:
+      bytes: [ 0x4c, 0x82, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bflr 2"
+  -
+    input:
+      bytes: [ 0x4c, 0x8a, 0x04, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfctr 10"
+  -
+    input:
+      bytes: [ 0x4c, 0x82, 0x04, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfctr 2"
+  -
+    input:
+      bytes: [ 0x4c, 0x8a, 0x00, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bflrl 10"
+  -
+    input:
+      bytes: [ 0x4c, 0x82, 0x00, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bflrl 2"
+  -
+    input:
+      bytes: [ 0x4c, 0x8a, 0x04, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfctrl 10"
+  -
+    input:
+      bytes: [ 0x4c, 0x82, 0x04, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfctrl 2"
+  -
+    input:
+      bytes: [ 0x4c, 0xea, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bflr+ 10"
+  -
+    input:
+      bytes: [ 0x4c, 0xe2, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bflr+ 2"
+  -
+    input:
+      bytes: [ 0x4c, 0xea, 0x04, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfctr+ 10"
+  -
+    input:
+      bytes: [ 0x4c, 0xe2, 0x04, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfctr+ 2"
+  -
+    input:
+      bytes: [ 0x4c, 0xea, 0x00, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bflrl+ 10"
+  -
+    input:
+      bytes: [ 0x4c, 0xe2, 0x00, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bflrl+ 2"
+  -
+    input:
+      bytes: [ 0x4c, 0xea, 0x04, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfctrl+ 10"
+  -
+    input:
+      bytes: [ 0x4c, 0xe2, 0x04, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfctrl+ 2"
+  -
+    input:
+      bytes: [ 0x4c, 0xca, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bflr- 10"
+  -
+    input:
+      bytes: [ 0x4c, 0xc2, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bflr- 2"
+  -
+    input:
+      bytes: [ 0x4c, 0xca, 0x04, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfctr- 10"
+  -
+    input:
+      bytes: [ 0x4c, 0xc2, 0x04, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfctr- 2"
+  -
+    input:
+      bytes: [ 0x4c, 0xca, 0x00, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bflrl- 10"
+  -
+    input:
+      bytes: [ 0x4c, 0xc2, 0x00, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bflrl- 2"
+  -
+    input:
+      bytes: [ 0x4c, 0xca, 0x04, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfctrl- 10"
+  -
+    input:
+      bytes: [ 0x4c, 0xc2, 0x04, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfctrl- 2"
+  -
+    input:
+      bytes: [ 0x4c, 0x89, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bflr 9"
+  -
+    input:
+      bytes: [ 0x4c, 0x81, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bflr 1"
+  -
+    input:
+      bytes: [ 0x4c, 0x89, 0x04, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfctr 9"
+  -
+    input:
+      bytes: [ 0x4c, 0x81, 0x04, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfctr 1"
+  -
+    input:
+      bytes: [ 0x4c, 0x89, 0x00, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bflrl 9"
+  -
+    input:
+      bytes: [ 0x4c, 0x81, 0x00, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bflrl 1"
+  -
+    input:
+      bytes: [ 0x4c, 0x89, 0x04, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfctrl 9"
+  -
+    input:
+      bytes: [ 0x4c, 0x81, 0x04, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfctrl 1"
+  -
+    input:
+      bytes: [ 0x4c, 0xe9, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bflr+ 9"
+  -
+    input:
+      bytes: [ 0x4c, 0xe1, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bflr+ 1"
+  -
+    input:
+      bytes: [ 0x4c, 0xe9, 0x04, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfctr+ 9"
+  -
+    input:
+      bytes: [ 0x4c, 0xe1, 0x04, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfctr+ 1"
+  -
+    input:
+      bytes: [ 0x4c, 0xe9, 0x00, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bflrl+ 9"
+  -
+    input:
+      bytes: [ 0x4c, 0xe1, 0x00, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bflrl+ 1"
+  -
+    input:
+      bytes: [ 0x4c, 0xe9, 0x04, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfctrl+ 9"
+  -
+    input:
+      bytes: [ 0x4c, 0xe1, 0x04, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfctrl+ 1"
+  -
+    input:
+      bytes: [ 0x4c, 0xc9, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bflr- 9"
+  -
+    input:
+      bytes: [ 0x4c, 0xc1, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bflr- 1"
+  -
+    input:
+      bytes: [ 0x4c, 0xc9, 0x04, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfctr- 9"
+  -
+    input:
+      bytes: [ 0x4c, 0xc1, 0x04, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfctr- 1"
+  -
+    input:
+      bytes: [ 0x4c, 0xc9, 0x00, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bflrl- 9"
+  -
+    input:
+      bytes: [ 0x4c, 0xc1, 0x00, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bflrl- 1"
+  -
+    input:
+      bytes: [ 0x4c, 0xc9, 0x04, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfctrl- 9"
+  -
+    input:
+      bytes: [ 0x4c, 0xc1, 0x04, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfctrl- 1"
+  -
+    input:
+      bytes: [ 0x4d, 0x8b, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btlr 11"
+  -
+    input:
+      bytes: [ 0x4d, 0x83, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btlr 3"
+  -
+    input:
+      bytes: [ 0x4d, 0x8b, 0x04, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btctr 11"
+  -
+    input:
+      bytes: [ 0x4d, 0x83, 0x04, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btctr 3"
+  -
+    input:
+      bytes: [ 0x4d, 0x8b, 0x00, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btlrl 11"
+  -
+    input:
+      bytes: [ 0x4d, 0x83, 0x00, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btlrl 3"
+  -
+    input:
+      bytes: [ 0x4d, 0x8b, 0x04, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btctrl 11"
+  -
+    input:
+      bytes: [ 0x4d, 0x83, 0x04, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btctrl 3"
+  -
+    input:
+      bytes: [ 0x4d, 0xeb, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btlr+ 11"
+  -
+    input:
+      bytes: [ 0x4d, 0xe3, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btlr+ 3"
+  -
+    input:
+      bytes: [ 0x4d, 0xeb, 0x04, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btctr+ 11"
+  -
+    input:
+      bytes: [ 0x4d, 0xe3, 0x04, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btctr+ 3"
+  -
+    input:
+      bytes: [ 0x4d, 0xeb, 0x00, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btlrl+ 11"
+  -
+    input:
+      bytes: [ 0x4d, 0xe3, 0x00, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btlrl+ 3"
+  -
+    input:
+      bytes: [ 0x4d, 0xeb, 0x04, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btctrl+ 11"
+  -
+    input:
+      bytes: [ 0x4d, 0xe3, 0x04, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btctrl+ 3"
+  -
+    input:
+      bytes: [ 0x4d, 0xcb, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btlr- 11"
+  -
+    input:
+      bytes: [ 0x4d, 0xc3, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btlr- 3"
+  -
+    input:
+      bytes: [ 0x4d, 0xcb, 0x04, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btctr- 11"
+  -
+    input:
+      bytes: [ 0x4d, 0xc3, 0x04, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btctr- 3"
+  -
+    input:
+      bytes: [ 0x4d, 0xcb, 0x00, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btlrl- 11"
+  -
+    input:
+      bytes: [ 0x4d, 0xc3, 0x00, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btlrl- 3"
+  -
+    input:
+      bytes: [ 0x4d, 0xcb, 0x04, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btctrl- 11"
+  -
+    input:
+      bytes: [ 0x4d, 0xc3, 0x04, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btctrl- 3"
+  -
+    input:
+      bytes: [ 0x4c, 0x8b, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bflr 11"
+  -
+    input:
+      bytes: [ 0x4c, 0x83, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bflr 3"
+  -
+    input:
+      bytes: [ 0x4c, 0x8b, 0x04, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfctr 11"
+  -
+    input:
+      bytes: [ 0x4c, 0x83, 0x04, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfctr 3"
+  -
+    input:
+      bytes: [ 0x4c, 0x8b, 0x00, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bflrl 11"
+  -
+    input:
+      bytes: [ 0x4c, 0x83, 0x00, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bflrl 3"
+  -
+    input:
+      bytes: [ 0x4c, 0x8b, 0x04, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfctrl 11"
+  -
+    input:
+      bytes: [ 0x4c, 0x83, 0x04, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfctrl 3"
+  -
+    input:
+      bytes: [ 0x4c, 0xeb, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bflr+ 11"
+  -
+    input:
+      bytes: [ 0x4c, 0xe3, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bflr+ 3"
+  -
+    input:
+      bytes: [ 0x4c, 0xeb, 0x04, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfctr+ 11"
+  -
+    input:
+      bytes: [ 0x4c, 0xe3, 0x04, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfctr+ 3"
+  -
+    input:
+      bytes: [ 0x4c, 0xeb, 0x00, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bflrl+ 11"
+  -
+    input:
+      bytes: [ 0x4c, 0xe3, 0x00, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bflrl+ 3"
+  -
+    input:
+      bytes: [ 0x4c, 0xeb, 0x04, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfctrl+ 11"
+  -
+    input:
+      bytes: [ 0x4c, 0xe3, 0x04, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfctrl+ 3"
+  -
+    input:
+      bytes: [ 0x4c, 0xcb, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bflr- 11"
+  -
+    input:
+      bytes: [ 0x4c, 0xc3, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bflr- 3"
+  -
+    input:
+      bytes: [ 0x4c, 0xcb, 0x04, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfctr- 11"
+  -
+    input:
+      bytes: [ 0x4c, 0xc3, 0x04, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfctr- 3"
+  -
+    input:
+      bytes: [ 0x4c, 0xcb, 0x00, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bflrl- 11"
+  -
+    input:
+      bytes: [ 0x4c, 0xc3, 0x00, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bflrl- 3"
+  -
+    input:
+      bytes: [ 0x4c, 0xcb, 0x04, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfctrl- 11"
+  -
+    input:
+      bytes: [ 0x4c, 0xc3, 0x04, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfctrl- 3"
+  -
+    input:
+      bytes: [ 0x4d, 0x8b, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btlr 11"
+  -
+    input:
+      bytes: [ 0x4d, 0x83, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btlr 3"
+  -
+    input:
+      bytes: [ 0x4d, 0x8b, 0x04, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btctr 11"
+  -
+    input:
+      bytes: [ 0x4d, 0x83, 0x04, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btctr 3"
+  -
+    input:
+      bytes: [ 0x4d, 0x8b, 0x00, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btlrl 11"
+  -
+    input:
+      bytes: [ 0x4d, 0x83, 0x00, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btlrl 3"
+  -
+    input:
+      bytes: [ 0x4d, 0x8b, 0x04, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btctrl 11"
+  -
+    input:
+      bytes: [ 0x4d, 0x83, 0x04, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btctrl 3"
+  -
+    input:
+      bytes: [ 0x4d, 0xeb, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btlr+ 11"
+  -
+    input:
+      bytes: [ 0x4d, 0xe3, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btlr+ 3"
+  -
+    input:
+      bytes: [ 0x4d, 0xeb, 0x04, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btctr+ 11"
+  -
+    input:
+      bytes: [ 0x4d, 0xe3, 0x04, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btctr+ 3"
+  -
+    input:
+      bytes: [ 0x4d, 0xeb, 0x00, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btlrl+ 11"
+  -
+    input:
+      bytes: [ 0x4d, 0xe3, 0x00, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btlrl+ 3"
+  -
+    input:
+      bytes: [ 0x4d, 0xeb, 0x04, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btctrl+ 11"
+  -
+    input:
+      bytes: [ 0x4d, 0xe3, 0x04, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btctrl+ 3"
+  -
+    input:
+      bytes: [ 0x4d, 0xcb, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btlr- 11"
+  -
+    input:
+      bytes: [ 0x4d, 0xc3, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btlr- 3"
+  -
+    input:
+      bytes: [ 0x4d, 0xcb, 0x04, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btctr- 11"
+  -
+    input:
+      bytes: [ 0x4d, 0xc3, 0x04, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btctr- 3"
+  -
+    input:
+      bytes: [ 0x4d, 0xcb, 0x00, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btlrl- 11"
+  -
+    input:
+      bytes: [ 0x4d, 0xc3, 0x00, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btlrl- 3"
+  -
+    input:
+      bytes: [ 0x4d, 0xcb, 0x04, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btctrl- 11"
+  -
+    input:
+      bytes: [ 0x4d, 0xc3, 0x04, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "btctrl- 3"
+  -
+    input:
+      bytes: [ 0x4c, 0x8b, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bflr 11"
+  -
+    input:
+      bytes: [ 0x4c, 0x83, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bflr 3"
+  -
+    input:
+      bytes: [ 0x4c, 0x8b, 0x04, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfctr 11"
+  -
+    input:
+      bytes: [ 0x4c, 0x83, 0x04, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfctr 3"
+  -
+    input:
+      bytes: [ 0x4c, 0x8b, 0x00, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bflrl 11"
+  -
+    input:
+      bytes: [ 0x4c, 0x83, 0x00, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bflrl 3"
+  -
+    input:
+      bytes: [ 0x4c, 0x8b, 0x04, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfctrl 11"
+  -
+    input:
+      bytes: [ 0x4c, 0x83, 0x04, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfctrl 3"
+  -
+    input:
+      bytes: [ 0x4c, 0xeb, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bflr+ 11"
+  -
+    input:
+      bytes: [ 0x4c, 0xe3, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bflr+ 3"
+  -
+    input:
+      bytes: [ 0x4c, 0xeb, 0x04, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfctr+ 11"
+  -
+    input:
+      bytes: [ 0x4c, 0xe3, 0x04, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfctr+ 3"
+  -
+    input:
+      bytes: [ 0x4c, 0xeb, 0x00, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bflrl+ 11"
+  -
+    input:
+      bytes: [ 0x4c, 0xe3, 0x00, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bflrl+ 3"
+  -
+    input:
+      bytes: [ 0x4c, 0xeb, 0x04, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfctrl+ 11"
+  -
+    input:
+      bytes: [ 0x4c, 0xe3, 0x04, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfctrl+ 3"
+  -
+    input:
+      bytes: [ 0x4c, 0xcb, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bflr- 11"
+  -
+    input:
+      bytes: [ 0x4c, 0xc3, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bflr- 3"
+  -
+    input:
+      bytes: [ 0x4c, 0xcb, 0x04, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfctr- 11"
+  -
+    input:
+      bytes: [ 0x4c, 0xc3, 0x04, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfctr- 3"
+  -
+    input:
+      bytes: [ 0x4c, 0xcb, 0x00, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bflrl- 11"
+  -
+    input:
+      bytes: [ 0x4c, 0xc3, 0x00, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bflrl- 3"
+  -
+    input:
+      bytes: [ 0x4c, 0xcb, 0x04, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfctrl- 11"
+  -
+    input:
+      bytes: [ 0x4c, 0xc3, 0x04, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfctrl- 3"
+  -
+    input:
+      bytes: [ 0x4c, 0x42, 0x12, 0x42 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "crset 2"
+  -
+    input:
+      bytes: [ 0x4c, 0x42, 0x11, 0x82 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "crclr 2"
+  -
+    input:
+      bytes: [ 0x4c, 0x43, 0x1b, 0x82 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "crmove 2, 3"
+  -
+    input:
+      bytes: [ 0x4c, 0x43, 0x18, 0x42 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "crnot 2, 3"
+  -
+    input:
+      bytes: [ 0x38, 0x43, 0xff, 0x80 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "addi 2, 3, -128"
+  -
+    input:
+      bytes: [ 0x3c, 0x43, 0xff, 0x80 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "addis 2, 3, -128"
+  -
+    input:
+      bytes: [ 0x30, 0x43, 0xff, 0x80 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "addic 2, 3, -128"
+  -
+    input:
+      bytes: [ 0x34, 0x43, 0xff, 0x80 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "addic. 2, 3, -128"
+  -
+    input:
+      bytes: [ 0x7c, 0x44, 0x18, 0x50 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x44, 0x18, 0x51 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub. 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x44, 0x18, 0x10 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "subc 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x44, 0x18, 0x11 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "subc. 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x2d, 0x23, 0x00, 0x80 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpdi 2, 3, 128"
+  -
+    input:
+      bytes: [ 0x2c, 0x23, 0x00, 0x80 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpdi 3, 128"
+  -
+    input:
+      bytes: [ 0x7d, 0x23, 0x20, 0x00 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpd 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x23, 0x20, 0x00 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpd 3, 4"
+  -
+    input:
+      bytes: [ 0x29, 0x23, 0x00, 0x80 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpldi 2, 3, 128"
+  -
+    input:
+      bytes: [ 0x28, 0x23, 0x00, 0x80 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpldi 3, 128"
+  -
+    input:
+      bytes: [ 0x7d, 0x23, 0x20, 0x40 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpld 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x23, 0x20, 0x40 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpld 3, 4"
+  -
+    input:
+      bytes: [ 0x2d, 0x03, 0x00, 0x80 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpwi 2, 3, 128"
+  -
+    input:
+      bytes: [ 0x2c, 0x03, 0x00, 0x80 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpwi 3, 128"
+  -
+    input:
+      bytes: [ 0x7d, 0x03, 0x20, 0x00 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpw 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x03, 0x20, 0x00 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpw 3, 4"
+  -
+    input:
+      bytes: [ 0x29, 0x03, 0x00, 0x80 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmplwi 2, 3, 128"
+  -
+    input:
+      bytes: [ 0x28, 0x03, 0x00, 0x80 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmplwi 3, 128"
+  -
+    input:
+      bytes: [ 0x7d, 0x03, 0x20, 0x40 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmplw 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x03, 0x20, 0x40 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmplw 3, 4"
+  -
+    input:
+      bytes: [ 0x0e, 0x03, 0x00, 0x04 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "twlti 3, 4"
+  -
+    input:
+      bytes: [ 0x7e, 0x03, 0x20, 0x08 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "twlt 3, 4"
+  -
+    input:
+      bytes: [ 0x0a, 0x03, 0x00, 0x04 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "tdlti 3, 4"
+  -
+    input:
+      bytes: [ 0x7e, 0x03, 0x20, 0x88 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "tdlt 3, 4"
+  -
+    input:
+      bytes: [ 0x0e, 0x83, 0x00, 0x04 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "twi 20, 3, 4"
+  -
+    input:
+      bytes: [ 0x7e, 0x83, 0x20, 0x08 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "tw 20, 3, 4"
+  -
+    input:
+      bytes: [ 0x0a, 0x83, 0x00, 0x04 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "tdi 20, 3, 4"
+  -
+    input:
+      bytes: [ 0x7e, 0x83, 0x20, 0x88 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "td 20, 3, 4"
+  -
+    input:
+      bytes: [ 0x0c, 0x83, 0x00, 0x04 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "tweqi 3, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x83, 0x20, 0x08 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "tweq 3, 4"
+  -
+    input:
+      bytes: [ 0x08, 0x83, 0x00, 0x04 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "tdeqi 3, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x83, 0x20, 0x88 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "tdeq 3, 4"
+  -
+    input:
+      bytes: [ 0x0d, 0x83, 0x00, 0x04 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "twi 12, 3, 4"
+  -
+    input:
+      bytes: [ 0x7d, 0x83, 0x20, 0x08 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "tw 12, 3, 4"
+  -
+    input:
+      bytes: [ 0x09, 0x83, 0x00, 0x04 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "tdi 12, 3, 4"
+  -
+    input:
+      bytes: [ 0x7d, 0x83, 0x20, 0x88 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "td 12, 3, 4"
+  -
+    input:
+      bytes: [ 0x0d, 0x03, 0x00, 0x04 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "twgti 3, 4"
+  -
+    input:
+      bytes: [ 0x7d, 0x03, 0x20, 0x08 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "twgt 3, 4"
+  -
+    input:
+      bytes: [ 0x09, 0x03, 0x00, 0x04 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "tdgti 3, 4"
+  -
+    input:
+      bytes: [ 0x7d, 0x03, 0x20, 0x88 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "tdgt 3, 4"
+  -
+    input:
+      bytes: [ 0x0d, 0x83, 0x00, 0x04 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "twi 12, 3, 4"
+  -
+    input:
+      bytes: [ 0x7d, 0x83, 0x20, 0x08 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "tw 12, 3, 4"
+  -
+    input:
+      bytes: [ 0x09, 0x83, 0x00, 0x04 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "tdi 12, 3, 4"
+  -
+    input:
+      bytes: [ 0x7d, 0x83, 0x20, 0x88 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "td 12, 3, 4"
+  -
+    input:
+      bytes: [ 0x0f, 0x03, 0x00, 0x04 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "twnei 3, 4"
+  -
+    input:
+      bytes: [ 0x7f, 0x03, 0x20, 0x08 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "twne 3, 4"
+  -
+    input:
+      bytes: [ 0x0b, 0x03, 0x00, 0x04 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "tdnei 3, 4"
+  -
+    input:
+      bytes: [ 0x7f, 0x03, 0x20, 0x88 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "tdne 3, 4"
+  -
+    input:
+      bytes: [ 0x0e, 0x83, 0x00, 0x04 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "twi 20, 3, 4"
+  -
+    input:
+      bytes: [ 0x7e, 0x83, 0x20, 0x08 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "tw 20, 3, 4"
+  -
+    input:
+      bytes: [ 0x0a, 0x83, 0x00, 0x04 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "tdi 20, 3, 4"
+  -
+    input:
+      bytes: [ 0x7e, 0x83, 0x20, 0x88 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "td 20, 3, 4"
+  -
+    input:
+      bytes: [ 0x0c, 0x43, 0x00, 0x04 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "twllti 3, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x43, 0x20, 0x08 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "twllt 3, 4"
+  -
+    input:
+      bytes: [ 0x08, 0x43, 0x00, 0x04 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "tdllti 3, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x43, 0x20, 0x88 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "tdllt 3, 4"
+  -
+    input:
+      bytes: [ 0x0c, 0xc3, 0x00, 0x04 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "twi 6, 3, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0xc3, 0x20, 0x08 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "tw 6, 3, 4"
+  -
+    input:
+      bytes: [ 0x08, 0xc3, 0x00, 0x04 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "tdi 6, 3, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0xc3, 0x20, 0x88 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "td 6, 3, 4"
+  -
+    input:
+      bytes: [ 0x0c, 0xa3, 0x00, 0x04 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "twi 5, 3, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0xa3, 0x20, 0x08 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "tw 5, 3, 4"
+  -
+    input:
+      bytes: [ 0x08, 0xa3, 0x00, 0x04 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "tdi 5, 3, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0xa3, 0x20, 0x88 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "td 5, 3, 4"
+  -
+    input:
+      bytes: [ 0x0c, 0x23, 0x00, 0x04 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "twlgti 3, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x23, 0x20, 0x08 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "twlgt 3, 4"
+  -
+    input:
+      bytes: [ 0x08, 0x23, 0x00, 0x04 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "tdlgti 3, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x23, 0x20, 0x88 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "tdlgt 3, 4"
+  -
+    input:
+      bytes: [ 0x0c, 0xa3, 0x00, 0x04 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "twi 5, 3, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0xa3, 0x20, 0x08 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "tw 5, 3, 4"
+  -
+    input:
+      bytes: [ 0x08, 0xa3, 0x00, 0x04 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "tdi 5, 3, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0xa3, 0x20, 0x88 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "td 5, 3, 4"
+  -
+    input:
+      bytes: [ 0x0c, 0xc3, 0x00, 0x04 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "twi 6, 3, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0xc3, 0x20, 0x08 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "tw 6, 3, 4"
+  -
+    input:
+      bytes: [ 0x08, 0xc3, 0x00, 0x04 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "tdi 6, 3, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0xc3, 0x20, 0x88 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "td 6, 3, 4"
+  -
+    input:
+      bytes: [ 0x0f, 0xe3, 0x00, 0x04 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "twui 3, 4"
+  -
+    input:
+      bytes: [ 0x7f, 0xe3, 0x20, 0x08 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "twu 3, 4"
+  -
+    input:
+      bytes: [ 0x0b, 0xe3, 0x00, 0x04 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "tdui 3, 4"
+  -
+    input:
+      bytes: [ 0x7f, 0xe3, 0x20, 0x88 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "tdu 3, 4"
+  -
+    input:
+      bytes: [ 0x7f, 0xe0, 0x00, 0x08 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "trap"
+  -
+    input:
+      bytes: [ 0x78, 0x62, 0x28, 0xc4 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "rldicr 2, 3, 5, 3"
+  -
+    input:
+      bytes: [ 0x78, 0x62, 0x28, 0xc5 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "rldicr. 2, 3, 5, 3"
+  -
+    input:
+      bytes: [ 0x78, 0x62, 0x4f, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "rldicl 2, 3, 9, 60"
+  -
+    input:
+      bytes: [ 0x78, 0x62, 0x4f, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "rldicl. 2, 3, 9, 60"
+  -
+    input:
+      bytes: [ 0x78, 0x62, 0xb9, 0x4e ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "rldimi 2, 3, 55, 5"
+  -
+    input:
+      bytes: [ 0x78, 0x62, 0xb9, 0x4f ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "rldimi. 2, 3, 55, 5"
+  -
+    input:
+      bytes: [ 0x78, 0x62, 0x20, 0x00 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "rotldi 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x78, 0x62, 0x20, 0x01 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "rotldi. 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x78, 0x62, 0xe0, 0x02 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "rotldi 2, 3, 60"
+  -
+    input:
+      bytes: [ 0x78, 0x62, 0xe0, 0x03 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "rotldi. 2, 3, 60"
+  -
+    input:
+      bytes: [ 0x78, 0x62, 0x20, 0x10 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "rotld 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x78, 0x62, 0x20, 0x11 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "rotld. 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x78, 0x62, 0x26, 0xe4 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sldi 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x78, 0x62, 0x26, 0xe5 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "rldicr. 2, 3, 4, 59"
+  -
+    input:
+      bytes: [ 0x78, 0x62, 0xe1, 0x02 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "rldicl 2, 3, 60, 4"
+  -
+    input:
+      bytes: [ 0x78, 0x62, 0xe1, 0x03 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "rldicl. 2, 3, 60, 4"
+  -
+    input:
+      bytes: [ 0x78, 0x62, 0x01, 0x00 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "clrldi 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x78, 0x62, 0x01, 0x01 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "clrldi. 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x78, 0x62, 0x06, 0xe4 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "rldicr 2, 3, 0, 59"
+  -
+    input:
+      bytes: [ 0x78, 0x62, 0x06, 0xe5 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "rldicr. 2, 3, 0, 59"
+  -
+    input:
+      bytes: [ 0x78, 0x62, 0x20, 0x48 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "rldic 2, 3, 4, 1"
+  -
+    input:
+      bytes: [ 0x78, 0x62, 0x20, 0x49 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "rldic. 2, 3, 4, 1"
+  -
+    input:
+      bytes: [ 0x54, 0x62, 0x28, 0x06 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "rlwinm 2, 3, 5, 0, 3"
+  -
+    input:
+      bytes: [ 0x54, 0x62, 0x28, 0x07 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "rlwinm. 2, 3, 5, 0, 3"
+  -
+    input:
+      bytes: [ 0x54, 0x62, 0x4f, 0x3e ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "rlwinm 2, 3, 9, 28, 31"
+  -
+    input:
+      bytes: [ 0x54, 0x62, 0x4f, 0x3f ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "rlwinm. 2, 3, 9, 28, 31"
+  -
+    input:
+      bytes: [ 0x50, 0x62, 0xd9, 0x50 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "rlwimi 2, 3, 27, 5, 8"
+  -
+    input:
+      bytes: [ 0x50, 0x62, 0xd9, 0x51 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "rlwimi. 2, 3, 27, 5, 8"
+  -
+    input:
+      bytes: [ 0x50, 0x62, 0xb9, 0x50 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "rlwimi 2, 3, 23, 5, 8"
+  -
+    input:
+      bytes: [ 0x50, 0x62, 0xb9, 0x51 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "rlwimi. 2, 3, 23, 5, 8"
+  -
+    input:
+      bytes: [ 0x54, 0x62, 0x20, 0x3e ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "rotlwi 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x54, 0x62, 0x20, 0x3f ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "rotlwi. 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x54, 0x62, 0xe0, 0x3e ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "rotlwi 2, 3, 28"
+  -
+    input:
+      bytes: [ 0x54, 0x62, 0xe0, 0x3f ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "rotlwi. 2, 3, 28"
+  -
+    input:
+      bytes: [ 0x5c, 0x62, 0x20, 0x3e ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "rotlw 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x5c, 0x62, 0x20, 0x3f ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "rotlw. 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x54, 0x62, 0x20, 0x36 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "slwi 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x54, 0x62, 0x20, 0x37 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "rlwinm. 2, 3, 4, 0, 27"
+  -
+    input:
+      bytes: [ 0x54, 0x62, 0xe1, 0x3e ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "srwi 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x54, 0x62, 0xe1, 0x3f ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "rlwinm. 2, 3, 28, 4, 31"
+  -
+    input:
+      bytes: [ 0x54, 0x62, 0x01, 0x3e ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "clrlwi 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x54, 0x62, 0x01, 0x3f ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "clrlwi. 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x54, 0x62, 0x00, 0x36 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "rlwinm 2, 3, 0, 0, 27"
+  -
+    input:
+      bytes: [ 0x54, 0x62, 0x00, 0x37 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "rlwinm. 2, 3, 0, 0, 27"
+  -
+    input:
+      bytes: [ 0x54, 0x62, 0x20, 0x76 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "rlwinm 2, 3, 4, 1, 27"
+  -
+    input:
+      bytes: [ 0x54, 0x62, 0x20, 0x77 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "rlwinm. 2, 3, 4, 1, 27"
+  -
+    input:
+      bytes: [ 0x7c, 0x41, 0x03, 0xa6 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mtxer 2"
+  -
+    input:
+      bytes: [ 0x7c, 0x41, 0x02, 0xa6 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mfxer 2"
+  -
+    input:
+      bytes: [ 0x7c, 0x43, 0x03, 0xa6 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mtudscr 2"
+  -
+    input:
+      bytes: [ 0x7c, 0x43, 0x02, 0xa6 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mfudscr 2"
+  -
+    input:
+      bytes: [ 0x7c, 0x44, 0x02, 0xa6 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mfrtcu 2"
+  -
+    input:
+      bytes: [ 0x7c, 0x45, 0x02, 0xa6 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mfrtcl 2"
+  -
+    input:
+      bytes: [ 0x7c, 0x43, 0x03, 0xa6 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mtudscr 2"
+  -
+    input:
+      bytes: [ 0x7c, 0x43, 0x02, 0xa6 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mfudscr 2"
+  -
+    input:
+      bytes: [ 0x7c, 0x51, 0x03, 0xa6 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mtdscr 2"
+  -
+    input:
+      bytes: [ 0x7c, 0x51, 0x02, 0xa6 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mfdscr 2"
+  -
+    input:
+      bytes: [ 0x7c, 0x52, 0x03, 0xa6 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mtdsisr 2"
+  -
+    input:
+      bytes: [ 0x7c, 0x52, 0x02, 0xa6 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mfdsisr 2"
+  -
+    input:
+      bytes: [ 0x7c, 0x53, 0x03, 0xa6 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mtdar 2"
+  -
+    input:
+      bytes: [ 0x7c, 0x53, 0x02, 0xa6 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mfdar 2"
+  -
+    input:
+      bytes: [ 0x7c, 0x56, 0x03, 0xa6 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mtdec 2"
+  -
+    input:
+      bytes: [ 0x7c, 0x56, 0x02, 0xa6 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mfdec 2"
+  -
+    input:
+      bytes: [ 0x7c, 0x59, 0x03, 0xa6 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mtsdr1 2"
+  -
+    input:
+      bytes: [ 0x7c, 0x59, 0x02, 0xa6 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mfsdr1 2"
+  -
+    input:
+      bytes: [ 0x7c, 0x5a, 0x03, 0xa6 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mtsrr0 2"
+  -
+    input:
+      bytes: [ 0x7c, 0x5a, 0x02, 0xa6 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mfsrr0 2"
+  -
+    input:
+      bytes: [ 0x7c, 0x5b, 0x03, 0xa6 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mtsrr1 2"
+  -
+    input:
+      bytes: [ 0x7c, 0x5b, 0x02, 0xa6 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mfsrr1 2"
+  -
+    input:
+      bytes: [ 0x7c, 0x5c, 0x03, 0xa6 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mtcfar 2"
+  -
+    input:
+      bytes: [ 0x7c, 0x5c, 0x02, 0xa6 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mfcfar 2"
+  -
+    input:
+      bytes: [ 0x7c, 0x5d, 0x03, 0xa6 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mtamr 2"
+  -
+    input:
+      bytes: [ 0x7c, 0x5d, 0x02, 0xa6 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mfamr 2"
+  -
+    input:
+      bytes: [ 0x7c, 0x50, 0x0b, 0xa6 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mtpid 2"
+  -
+    input:
+      bytes: [ 0x7c, 0x50, 0x0a, 0xa6 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mfpid 2"
+  -
+    input:
+      bytes: [ 0x7c, 0x48, 0x03, 0xa6 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mtlr 2"
+  -
+    input:
+      bytes: [ 0x7c, 0x48, 0x02, 0xa6 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mflr 2"
+  -
+    input:
+      bytes: [ 0x7c, 0x49, 0x03, 0xa6 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mtctr 2"
+  -
+    input:
+      bytes: [ 0x7c, 0x49, 0x02, 0xa6 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mfctr 2"
+  -
+    input:
+      bytes: [ 0x7c, 0x4d, 0x03, 0xa6 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mtuamr 2"
+  -
+    input:
+      bytes: [ 0x7c, 0x4d, 0x02, 0xa6 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mfuamr 2"
+  -
+    input:
+      bytes: [ 0x7c, 0x40, 0xe3, 0xa6 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mtppr 2"
+  -
+    input:
+      bytes: [ 0x7c, 0x40, 0xe2, 0xa6 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mfppr 2"
+  -
+    input:
+      bytes: [ 0x7c, 0x40, 0x42, 0xa6 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mfspr 2, 256"
+  -
+    input:
+      bytes: [ 0x7c, 0x40, 0x43, 0xa6 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mtspr 256, 2"
+  -
+    input:
+      bytes: [ 0x60, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "nop"
+  -
+    input:
+      bytes: [ 0x68, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "xnop"
+  -
+    input:
+      bytes: [ 0x38, 0x40, 0x00, 0x80 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "li 2, 128"
+  -
+    input:
+      bytes: [ 0x3c, 0x40, 0x00, 0x80 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "lis 2, 128"
+  -
+    input:
+      bytes: [ 0x7c, 0x62, 0x1b, 0x78 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mr 2, 3"
+  -
+    input:
+      bytes: [ 0x7c, 0x62, 0x1b, 0x79 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mr. 2, 3"
+  -
+    input:
+      bytes: [ 0x7c, 0x62, 0x18, 0xf8 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "not 2, 3"
+  -
+    input:
+      bytes: [ 0x7c, 0x62, 0x18, 0xf9 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "not. 2, 3"
+  -
+    input:
+      bytes: [ 0x7c, 0x4f, 0xf1, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mtcr 2"
+  -
+    input:
+      bytes: [ 0x7c, 0x90, 0x42, 0xa6 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mfspr 4, 272"
+  -
+    input:
+      bytes: [ 0x7c, 0x91, 0x42, 0xa6 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mfspr 4, 273"
+  -
+    input:
+      bytes: [ 0x7c, 0x92, 0x42, 0xa6 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mfspr 4, 274"
+  -
+    input:
+      bytes: [ 0x7c, 0x93, 0x42, 0xa6 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mfspr 4, 275"
+  -
+    input:
+      bytes: [ 0x7c, 0x52, 0x42, 0xa6 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mfspr 2, 274"
+  -
+    input:
+      bytes: [ 0x7c, 0x50, 0x42, 0xa6 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mfspr 2, 272"
+  -
+    input:
+      bytes: [ 0x7c, 0x51, 0x42, 0xa6 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mfspr 2, 273"
+  -
+    input:
+      bytes: [ 0x7c, 0x52, 0x42, 0xa6 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mfspr 2, 274"
+  -
+    input:
+      bytes: [ 0x7c, 0x53, 0x42, 0xa6 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mfspr 2, 275"
+  -
+    input:
+      bytes: [ 0x7c, 0x90, 0x43, 0xa6 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mtspr 272, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x91, 0x43, 0xa6 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mtspr 273, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x92, 0x43, 0xa6 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mtspr 274, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x93, 0x43, 0xa6 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mtspr 275, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x52, 0x43, 0xa6 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mtspr 274, 2"
+  -
+    input:
+      bytes: [ 0x7c, 0x90, 0x43, 0xa6 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mtspr 272, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x91, 0x43, 0xa6 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mtspr 273, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x92, 0x43, 0xa6 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mtspr 274, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x93, 0x43, 0xa6 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mtspr 275, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x60, 0x06, 0x6c ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "dss 3"
+  -
+    input:
+      bytes: [ 0x7e, 0x00, 0x06, 0x6c ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "dssall"
+  -
+    input:
+      bytes: [ 0x7c, 0x6c, 0x5a, 0xac ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "dst 12, 11, 3"
+  -
+    input:
+      bytes: [ 0x7e, 0x6c, 0x5a, 0xac ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "dstt 12, 11, 3"
+  -
+    input:
+      bytes: [ 0x7c, 0x6c, 0x5a, 0xec ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "dstst 12, 11, 3"
+  -
+    input:
+      bytes: [ 0x7e, 0x6c, 0x5a, 0xec ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "dststt 12, 11, 3"
+  -
+    input:
+      bytes: [ 0x7c, 0x00, 0x02, 0xe4 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "tlbia"
+  -
+    input:
+      bytes: [ 0x7d, 0x06, 0x3c, 0xaa ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "lswi 8, 6, 7"
+  -
+    input:
+      bytes: [ 0x7d, 0x06, 0x3d, 0xaa ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "stswi 8, 6, 7"
+  -
+    input:
+      bytes: [ 0x4c, 0x00, 0x00, 0x24 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "rfid"
+  -
+    input:
+      bytes: [ 0x7c, 0x58, 0x42, 0xa6 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mfasr 2"
+  -
+    input:
+      bytes: [ 0x7c, 0x58, 0x43, 0xa6 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mtasr 2"
+  -
+    input:
+      bytes: [ 0x7e, 0xa5, 0x3e, 0xaa ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "lbzcix 21, 5, 7"
+  -
+    input:
+      bytes: [ 0x7e, 0xa5, 0x3e, 0x6a ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "lhzcix 21, 5, 7"
+  -
+    input:
+      bytes: [ 0x7e, 0xa5, 0x3e, 0x2a ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "lwzcix 21, 5, 7"
+  -
+    input:
+      bytes: [ 0x7e, 0xa5, 0x3e, 0xea ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldcix 21, 5, 7"
+  -
+    input:
+      bytes: [ 0x7e, 0xa5, 0x3f, 0xaa ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "stbcix 21, 5, 7"
+  -
+    input:
+      bytes: [ 0x7e, 0xa5, 0x3f, 0x6a ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sthcix 21, 5, 7"
+  -
+    input:
+      bytes: [ 0x7e, 0xa5, 0x3f, 0x2a ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "stwcix 21, 5, 7"
+  -
+    input:
+      bytes: [ 0x7e, 0xa5, 0x3f, 0xea ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "stdcix 21, 5, 7"
+  -
+    input:
+      bytes: [ 0x00, 0x00, 0x02, 0x00 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "attn"
+  -
+    input:
+      bytes: [ 0x7c, 0x22, 0x9e, 0x0c ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "copy 2, 19"
+  -
+    input:
+      bytes: [ 0x7c, 0x11, 0x0f, 0x0d ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "paste. 17, 1, 0"
+  -
+    input:
+      bytes: [ 0x7c, 0x31, 0x0f, 0x0d ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "paste. 17, 1"
+  -
+    input:
+      bytes: [ 0x7c, 0x31, 0x0f, 0x0d ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "paste. 17, 1"
diff --git a/tests/MC/PowerPC/ppc64-encoding-fp.s.yaml b/tests/MC/PowerPC/ppc64-encoding-fp.s.yaml
new file mode 100644
index 000000000..bb8a1184d
--- /dev/null
+++ b/tests/MC/PowerPC/ppc64-encoding-fp.s.yaml
@@ -0,0 +1,982 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xc0, 0x44, 0x00, 0x80 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "lfs 2, 128(4)"
+  -
+    input:
+      bytes: [ 0x7c, 0x43, 0x24, 0x2e ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "lfsx 2, 3, 4"
+  -
+    input:
+      bytes: [ 0xc4, 0x44, 0x00, 0x80 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "lfsu 2, 128(4)"
+  -
+    input:
+      bytes: [ 0x7c, 0x43, 0x24, 0x6e ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "lfsux 2, 3, 4"
+  -
+    input:
+      bytes: [ 0xc8, 0x44, 0x00, 0x80 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "lfd 2, 128(4)"
+  -
+    input:
+      bytes: [ 0x7c, 0x43, 0x24, 0xae ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "lfdx 2, 3, 4"
+  -
+    input:
+      bytes: [ 0xcc, 0x44, 0x00, 0x80 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "lfdu 2, 128(4)"
+  -
+    input:
+      bytes: [ 0x7c, 0x43, 0x24, 0xee ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "lfdux 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x43, 0x26, 0xae ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "lfiwax 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x43, 0x26, 0xee ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "lfiwzx 2, 3, 4"
+  -
+    input:
+      bytes: [ 0xd0, 0x44, 0x00, 0x80 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "stfs 2, 128(4)"
+  -
+    input:
+      bytes: [ 0x7c, 0x43, 0x25, 0x2e ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "stfsx 2, 3, 4"
+  -
+    input:
+      bytes: [ 0xd4, 0x44, 0x00, 0x80 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "stfsu 2, 128(4)"
+  -
+    input:
+      bytes: [ 0x7c, 0x43, 0x25, 0x6e ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "stfsux 2, 3, 4"
+  -
+    input:
+      bytes: [ 0xd8, 0x44, 0x00, 0x80 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "stfd 2, 128(4)"
+  -
+    input:
+      bytes: [ 0x7c, 0x43, 0x25, 0xae ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "stfdx 2, 3, 4"
+  -
+    input:
+      bytes: [ 0xdc, 0x44, 0x00, 0x80 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "stfdu 2, 128(4)"
+  -
+    input:
+      bytes: [ 0x7c, 0x43, 0x25, 0xee ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "stfdux 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x43, 0x27, 0xae ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "stfiwx 2, 3, 4"
+  -
+    input:
+      bytes: [ 0xfc, 0x40, 0x18, 0x90 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmr 2, 3"
+  -
+    input:
+      bytes: [ 0xfc, 0x40, 0x18, 0x91 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmr. 2, 3"
+  -
+    input:
+      bytes: [ 0xfc, 0x40, 0x18, 0x50 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fneg 2, 3"
+  -
+    input:
+      bytes: [ 0xfc, 0x40, 0x18, 0x51 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fneg. 2, 3"
+  -
+    input:
+      bytes: [ 0xfc, 0x40, 0x1a, 0x10 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fabs 2, 3"
+  -
+    input:
+      bytes: [ 0xfc, 0x40, 0x1a, 0x11 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fabs. 2, 3"
+  -
+    input:
+      bytes: [ 0xfc, 0x40, 0x19, 0x10 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fnabs 2, 3"
+  -
+    input:
+      bytes: [ 0xfc, 0x40, 0x19, 0x11 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fnabs. 2, 3"
+  -
+    input:
+      bytes: [ 0xfc, 0x43, 0x20, 0x10 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcpsgn 2, 3, 4"
+  -
+    input:
+      bytes: [ 0xfc, 0x43, 0x20, 0x11 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcpsgn. 2, 3, 4"
+  -
+    input:
+      bytes: [ 0xfc, 0x43, 0x20, 0x2a ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd 2, 3, 4"
+  -
+    input:
+      bytes: [ 0xfc, 0x43, 0x20, 0x2b ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadd. 2, 3, 4"
+  -
+    input:
+      bytes: [ 0xec, 0x43, 0x20, 0x2a ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadds 2, 3, 4"
+  -
+    input:
+      bytes: [ 0xec, 0x43, 0x20, 0x2b ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadds. 2, 3, 4"
+  -
+    input:
+      bytes: [ 0xfc, 0x43, 0x20, 0x28 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub 2, 3, 4"
+  -
+    input:
+      bytes: [ 0xfc, 0x43, 0x20, 0x29 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsub. 2, 3, 4"
+  -
+    input:
+      bytes: [ 0xec, 0x43, 0x20, 0x28 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsubs 2, 3, 4"
+  -
+    input:
+      bytes: [ 0xec, 0x43, 0x20, 0x29 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsubs. 2, 3, 4"
+  -
+    input:
+      bytes: [ 0xfc, 0x43, 0x01, 0x32 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmul 2, 3, 4"
+  -
+    input:
+      bytes: [ 0xfc, 0x43, 0x01, 0x33 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmul. 2, 3, 4"
+  -
+    input:
+      bytes: [ 0xec, 0x43, 0x01, 0x32 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmuls 2, 3, 4"
+  -
+    input:
+      bytes: [ 0xec, 0x43, 0x01, 0x33 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmuls. 2, 3, 4"
+  -
+    input:
+      bytes: [ 0xfc, 0x43, 0x20, 0x24 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdiv 2, 3, 4"
+  -
+    input:
+      bytes: [ 0xfc, 0x43, 0x20, 0x25 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdiv. 2, 3, 4"
+  -
+    input:
+      bytes: [ 0xec, 0x43, 0x20, 0x24 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdivs 2, 3, 4"
+  -
+    input:
+      bytes: [ 0xec, 0x43, 0x20, 0x25 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdivs. 2, 3, 4"
+  -
+    input:
+      bytes: [ 0xfc, 0x40, 0x18, 0x2c ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsqrt 2, 3"
+  -
+    input:
+      bytes: [ 0xfc, 0x40, 0x18, 0x2d ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsqrt. 2, 3"
+  -
+    input:
+      bytes: [ 0xec, 0x40, 0x18, 0x2c ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsqrts 2, 3"
+  -
+    input:
+      bytes: [ 0xec, 0x40, 0x18, 0x2d ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsqrts. 2, 3"
+  -
+    input:
+      bytes: [ 0xfc, 0x40, 0x18, 0x30 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fre 2, 3"
+  -
+    input:
+      bytes: [ 0xfc, 0x40, 0x18, 0x31 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fre. 2, 3"
+  -
+    input:
+      bytes: [ 0xec, 0x40, 0x18, 0x30 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fres 2, 3"
+  -
+    input:
+      bytes: [ 0xec, 0x40, 0x18, 0x31 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fres. 2, 3"
+  -
+    input:
+      bytes: [ 0xfc, 0x40, 0x18, 0x34 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "frsqrte 2, 3"
+  -
+    input:
+      bytes: [ 0xfc, 0x40, 0x18, 0x35 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "frsqrte. 2, 3"
+  -
+    input:
+      bytes: [ 0xec, 0x40, 0x18, 0x34 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "frsqrtes 2, 3"
+  -
+    input:
+      bytes: [ 0xec, 0x40, 0x18, 0x35 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "frsqrtes. 2, 3"
+  -
+    input:
+      bytes: [ 0xfc, 0x43, 0x29, 0x3a ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmadd 2, 3, 4, 5"
+  -
+    input:
+      bytes: [ 0xfc, 0x43, 0x29, 0x3b ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmadd. 2, 3, 4, 5"
+  -
+    input:
+      bytes: [ 0xec, 0x43, 0x29, 0x3a ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmadds 2, 3, 4, 5"
+  -
+    input:
+      bytes: [ 0xec, 0x43, 0x29, 0x3b ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmadds. 2, 3, 4, 5"
+  -
+    input:
+      bytes: [ 0xfc, 0x43, 0x29, 0x38 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmsub 2, 3, 4, 5"
+  -
+    input:
+      bytes: [ 0xfc, 0x43, 0x29, 0x39 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmsub. 2, 3, 4, 5"
+  -
+    input:
+      bytes: [ 0xec, 0x43, 0x29, 0x38 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmsubs 2, 3, 4, 5"
+  -
+    input:
+      bytes: [ 0xec, 0x43, 0x29, 0x39 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmsubs. 2, 3, 4, 5"
+  -
+    input:
+      bytes: [ 0xfc, 0x43, 0x29, 0x3e ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fnmadd 2, 3, 4, 5"
+  -
+    input:
+      bytes: [ 0xfc, 0x43, 0x29, 0x3f ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fnmadd. 2, 3, 4, 5"
+  -
+    input:
+      bytes: [ 0xec, 0x43, 0x29, 0x3e ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fnmadds 2, 3, 4, 5"
+  -
+    input:
+      bytes: [ 0xec, 0x43, 0x29, 0x3f ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fnmadds. 2, 3, 4, 5"
+  -
+    input:
+      bytes: [ 0xfc, 0x43, 0x29, 0x3c ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fnmsub 2, 3, 4, 5"
+  -
+    input:
+      bytes: [ 0xfc, 0x43, 0x29, 0x3d ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fnmsub. 2, 3, 4, 5"
+  -
+    input:
+      bytes: [ 0xec, 0x43, 0x29, 0x3c ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fnmsubs 2, 3, 4, 5"
+  -
+    input:
+      bytes: [ 0xec, 0x43, 0x29, 0x3d ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fnmsubs. 2, 3, 4, 5"
+  -
+    input:
+      bytes: [ 0xfc, 0x40, 0x18, 0x18 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "frsp 2, 3"
+  -
+    input:
+      bytes: [ 0xfc, 0x40, 0x18, 0x19 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "frsp. 2, 3"
+  -
+    input:
+      bytes: [ 0xfc, 0x40, 0x1e, 0x5c ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fctid 2, 3"
+  -
+    input:
+      bytes: [ 0xfc, 0x40, 0x1e, 0x5d ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fctid. 2, 3"
+  -
+    input:
+      bytes: [ 0xfc, 0x40, 0x1e, 0x5e ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fctidz 2, 3"
+  -
+    input:
+      bytes: [ 0xfc, 0x40, 0x1e, 0x5f ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fctidz. 2, 3"
+  -
+    input:
+      bytes: [ 0xfc, 0x40, 0x1f, 0x5e ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fctiduz 2, 3"
+  -
+    input:
+      bytes: [ 0xfc, 0x40, 0x1f, 0x5f ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fctiduz. 2, 3"
+  -
+    input:
+      bytes: [ 0xfc, 0x40, 0x18, 0x1c ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fctiw 2, 3"
+  -
+    input:
+      bytes: [ 0xfc, 0x40, 0x18, 0x1d ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fctiw. 2, 3"
+  -
+    input:
+      bytes: [ 0xfc, 0x40, 0x18, 0x1e ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fctiwz 2, 3"
+  -
+    input:
+      bytes: [ 0xfc, 0x40, 0x18, 0x1f ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fctiwz. 2, 3"
+  -
+    input:
+      bytes: [ 0xfc, 0x40, 0x19, 0x1e ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fctiwuz 2, 3"
+  -
+    input:
+      bytes: [ 0xfc, 0x40, 0x19, 0x1f ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fctiwuz. 2, 3"
+  -
+    input:
+      bytes: [ 0xfc, 0x40, 0x1e, 0x9c ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcfid 2, 3"
+  -
+    input:
+      bytes: [ 0xfc, 0x40, 0x1e, 0x9d ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcfid. 2, 3"
+  -
+    input:
+      bytes: [ 0xfc, 0x40, 0x1f, 0x9c ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcfidu 2, 3"
+  -
+    input:
+      bytes: [ 0xfc, 0x40, 0x1f, 0x9d ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcfidu. 2, 3"
+  -
+    input:
+      bytes: [ 0xec, 0x40, 0x1e, 0x9c ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcfids 2, 3"
+  -
+    input:
+      bytes: [ 0xec, 0x40, 0x1e, 0x9d ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcfids. 2, 3"
+  -
+    input:
+      bytes: [ 0xec, 0x40, 0x1f, 0x9c ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcfidus 2, 3"
+  -
+    input:
+      bytes: [ 0xec, 0x40, 0x1f, 0x9d ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcfidus. 2, 3"
+  -
+    input:
+      bytes: [ 0xfc, 0x40, 0x1b, 0x10 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "frin 2, 3"
+  -
+    input:
+      bytes: [ 0xfc, 0x40, 0x1b, 0x11 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "frin. 2, 3"
+  -
+    input:
+      bytes: [ 0xfc, 0x40, 0x1b, 0x90 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "frip 2, 3"
+  -
+    input:
+      bytes: [ 0xfc, 0x40, 0x1b, 0x91 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "frip. 2, 3"
+  -
+    input:
+      bytes: [ 0xfc, 0x40, 0x1b, 0x50 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "friz 2, 3"
+  -
+    input:
+      bytes: [ 0xfc, 0x40, 0x1b, 0x51 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "friz. 2, 3"
+  -
+    input:
+      bytes: [ 0xfc, 0x40, 0x1b, 0xd0 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "frim 2, 3"
+  -
+    input:
+      bytes: [ 0xfc, 0x40, 0x1b, 0xd1 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "frim. 2, 3"
+  -
+    input:
+      bytes: [ 0xfd, 0x03, 0x20, 0x00 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmpu 2, 3, 4"
+  -
+    input:
+      bytes: [ 0xfc, 0x43, 0x29, 0x2e ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsel 2, 3, 4, 5"
+  -
+    input:
+      bytes: [ 0xfc, 0x43, 0x29, 0x2f ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsel. 2, 3, 4, 5"
+  -
+    input:
+      bytes: [ 0xfc, 0x40, 0x04, 0x8e ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mffs 2"
+  -
+    input:
+      bytes: [ 0xff, 0xe0, 0x00, 0x8c ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mtfsb0 31"
+  -
+    input:
+      bytes: [ 0xff, 0xe0, 0x00, 0x4c ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mtfsb1 31"
diff --git a/tests/MC/PowerPC/ppc64-encoding-vmx.s.yaml b/tests/MC/PowerPC/ppc64-encoding-vmx.s.yaml
new file mode 100644
index 000000000..b3df32752
--- /dev/null
+++ b/tests/MC/PowerPC/ppc64-encoding-vmx.s.yaml
@@ -0,0 +1,1522 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x7c, 0x43, 0x20, 0x0e ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "lvebx 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x43, 0x20, 0x4e ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "lvehx 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x43, 0x20, 0x8e ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "lvewx 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x43, 0x20, 0xce ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "lvx 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x43, 0x22, 0xce ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "lvxl 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x43, 0x21, 0x0e ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "stvebx 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x43, 0x21, 0x4e ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "stvehx 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x43, 0x21, 0x8e ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "stvewx 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x43, 0x21, 0xce ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "stvx 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x43, 0x23, 0xce ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "stvxl 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x43, 0x20, 0x0c ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "lvsl 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x43, 0x20, 0x4c ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "lvsr 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x23, 0x0e ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpkpx 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x21, 0x8e ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpkshss 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x21, 0x0e ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpkshus 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x21, 0xce ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpkswss 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x21, 0x4e ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpkswus 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x20, 0x0e ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpkuhum 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x20, 0x8e ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpkuhus 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x20, 0x4e ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpkuwum 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x20, 0xce ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpkuwus 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x40, 0x1b, 0x4e ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vupkhpx 2, 3"
+  -
+    input:
+      bytes: [ 0x10, 0x40, 0x1a, 0x0e ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vupkhsb 2, 3"
+  -
+    input:
+      bytes: [ 0x10, 0x40, 0x1a, 0x4e ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vupkhsh 2, 3"
+  -
+    input:
+      bytes: [ 0x10, 0x40, 0x1b, 0xce ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vupklpx 2, 3"
+  -
+    input:
+      bytes: [ 0x10, 0x40, 0x1a, 0x8e ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vupklsb 2, 3"
+  -
+    input:
+      bytes: [ 0x10, 0x40, 0x1a, 0xce ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vupklsh 2, 3"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x20, 0x0c ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmrghb 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x20, 0x4c ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmrghh 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x20, 0x8c ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmrghw 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x21, 0x0c ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmrglb 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x21, 0x4c ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmrglh 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x21, 0x8c ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmrglw 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x41, 0x1a, 0x0c ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vspltb 2, 3, 1"
+  -
+    input:
+      bytes: [ 0x10, 0x41, 0x1a, 0x4c ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vsplth 2, 3, 1"
+  -
+    input:
+      bytes: [ 0x10, 0x41, 0x1a, 0x8c ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vspltw 2, 3, 1"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x03, 0x0c ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vspltisb 2, 3"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x03, 0x4c ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vspltish 2, 3"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x03, 0x8c ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vspltisw 2, 3"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x21, 0x6b ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vperm 2, 3, 4, 5"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x21, 0x6a ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vsel 2, 3, 4, 5"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x21, 0xc4 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vsl 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x21, 0x6c ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vsldoi 2, 3, 4, 5"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x24, 0x0c ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vslo 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x22, 0xc4 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vsr 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x24, 0x4c ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vsro 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x21, 0x80 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vaddcuw 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x23, 0x00 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vaddsbs 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x23, 0x40 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vaddshs 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x23, 0x80 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vaddsws 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x20, 0x00 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vaddubm 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x20, 0x40 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vadduhm 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x20, 0x80 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vadduwm 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x22, 0x00 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vaddubs 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x22, 0x40 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vadduhs 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x22, 0x80 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vadduws 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x25, 0x80 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vsubcuw 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x27, 0x00 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vsubsbs 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x27, 0x40 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vsubshs 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x27, 0x80 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vsubsws 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x24, 0x00 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vsububm 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x24, 0x40 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vsubuhm 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x24, 0x80 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vsubuwm 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x26, 0x00 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vsububs 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x26, 0x40 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vsubuhs 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x26, 0x80 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vsubuws 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x23, 0x08 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmulesb 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x23, 0x48 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmulesh 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x22, 0x08 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmuleub 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x22, 0x48 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmuleuh 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x21, 0x08 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmulosb 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x21, 0x48 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmulosh 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x20, 0x08 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmuloub 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x20, 0x48 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmulouh 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x21, 0x60 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmhaddshs 2, 3, 4, 5"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x21, 0x61 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmhraddshs 2, 3, 4, 5"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x21, 0x62 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmladduhm 2, 3, 4, 5"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x21, 0x64 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmsumubm 2, 3, 4, 5"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x21, 0x65 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmsummbm 2, 3, 4, 5"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x21, 0x68 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmsumshm 2, 3, 4, 5"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x21, 0x69 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmsumshs 2, 3, 4, 5"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x21, 0x66 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmsumuhm 2, 3, 4, 5"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x21, 0x67 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmsumuhs 2, 3, 4, 5"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x27, 0x88 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vsumsws 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x26, 0x88 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vsum2sws 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x27, 0x08 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vsum4sbs 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x26, 0x48 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vsum4shs 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x26, 0x08 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vsum4ubs 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x25, 0x02 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vavgsb 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x25, 0x42 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vavgsh 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x25, 0x82 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vavgsw 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x24, 0x02 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vavgub 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x24, 0x42 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vavguh 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x24, 0x82 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vavguw 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x21, 0x02 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmaxsb 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x21, 0x42 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmaxsh 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x21, 0x82 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmaxsw 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x20, 0x02 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmaxub 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x20, 0x42 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmaxuh 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x20, 0x82 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmaxuw 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x23, 0x02 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vminsb 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x23, 0x42 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vminsh 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x23, 0x82 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vminsw 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x22, 0x02 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vminub 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x22, 0x42 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vminuh 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x22, 0x82 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vminuw 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x20, 0x06 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpequb 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x24, 0x06 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpequb. 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x20, 0x46 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpequh 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x24, 0x46 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpequh. 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x20, 0x86 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpequw 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x24, 0x86 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpequw. 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x23, 0x06 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpgtsb 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x27, 0x06 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpgtsb. 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x23, 0x46 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpgtsh 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x27, 0x46 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpgtsh. 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x23, 0x86 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpgtsw 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x27, 0x86 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpgtsw. 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x22, 0x06 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpgtub 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x26, 0x06 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpgtub. 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x22, 0x46 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpgtuh 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x26, 0x46 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpgtuh. 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x22, 0x86 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpgtuw 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x26, 0x86 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpgtuw. 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x24, 0x04 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vand 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x24, 0x44 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vandc 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x25, 0x04 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vnor 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x24, 0x84 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vor 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x24, 0xc4 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vxor 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x20, 0x04 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vrlb 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x20, 0x44 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vrlh 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x20, 0x84 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vrlw 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x21, 0x04 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vslb 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x21, 0x44 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vslh 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x21, 0x84 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vslw 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x22, 0x04 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vsrb 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x22, 0x44 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vsrh 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x22, 0x84 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vsrw 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x23, 0x04 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vsrab 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x23, 0x44 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vsrah 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x23, 0x84 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vsraw 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x20, 0x0a ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vaddfp 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x20, 0x4a ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vsubfp 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x29, 0x2e ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmaddfp 2, 3, 4, 5"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x29, 0x2f ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vnmsubfp 2, 3, 4, 5"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x24, 0x0a ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmaxfp 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x24, 0x4a ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vminfp 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x44, 0x1b, 0xca ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vctsxs 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x44, 0x1b, 0x8a ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vctuxs 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x44, 0x1b, 0x4a ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcfsx 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x44, 0x1b, 0x0a ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcfux 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x40, 0x1a, 0xca ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vrfim 2, 3"
+  -
+    input:
+      bytes: [ 0x10, 0x40, 0x1a, 0x0a ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vrfin 2, 3"
+  -
+    input:
+      bytes: [ 0x10, 0x40, 0x1a, 0x8a ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vrfip 2, 3"
+  -
+    input:
+      bytes: [ 0x10, 0x40, 0x1a, 0x4a ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vrfiz 2, 3"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x23, 0xc6 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpbfp 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x27, 0xc6 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpbfp. 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x20, 0xc6 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpeqfp 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x24, 0xc6 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpeqfp. 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x21, 0xc6 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpgefp 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x25, 0xc6 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpgefp. 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x22, 0xc6 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpgtfp 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x43, 0x26, 0xc6 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpgtfp. 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x10, 0x40, 0x19, 0x8a ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vexptefp 2, 3"
+  -
+    input:
+      bytes: [ 0x10, 0x40, 0x19, 0xca ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vlogefp 2, 3"
+  -
+    input:
+      bytes: [ 0x10, 0x40, 0x19, 0x0a ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vrefp 2, 3"
+  -
+    input:
+      bytes: [ 0x10, 0x40, 0x19, 0x4a ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "vrsqrtefp 2, 3"
+  -
+    input:
+      bytes: [ 0x10, 0x00, 0x16, 0x44 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mtvscr 2"
+  -
+    input:
+      bytes: [ 0x10, 0x40, 0x06, 0x04 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mfvscr 2"
diff --git a/tests/MC/PowerPC/ppc64-encoding.s.yaml b/tests/MC/PowerPC/ppc64-encoding.s.yaml
new file mode 100644
index 000000000..803ae4836
--- /dev/null
+++ b/tests/MC/PowerPC/ppc64-encoding.s.yaml
@@ -0,0 +1,1801 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x4c, 0x8a, 0x18, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bclr 4, 10, 3"
+  -
+    input:
+      bytes: [ 0x4c, 0x8a, 0x00, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bflr 10"
+  -
+    input:
+      bytes: [ 0x4c, 0x8a, 0x18, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bclrl 4, 10, 3"
+  -
+    input:
+      bytes: [ 0x4c, 0x8a, 0x00, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bflrl 10"
+  -
+    input:
+      bytes: [ 0x4c, 0x8a, 0x1c, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bcctr 4, 10, 3"
+  -
+    input:
+      bytes: [ 0x4c, 0x8a, 0x04, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfctr 10"
+  -
+    input:
+      bytes: [ 0x4c, 0x8a, 0x1c, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bcctrl 4, 10, 3"
+  -
+    input:
+      bytes: [ 0x4c, 0x8a, 0x04, 0x21 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bfctrl 10"
+  -
+    input:
+      bytes: [ 0x4c, 0x43, 0x22, 0x02 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "crand 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x4c, 0x43, 0x21, 0xc2 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "crnand 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x4c, 0x43, 0x23, 0x82 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cror 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x4c, 0x43, 0x21, 0x82 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "crxor 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x4c, 0x43, 0x20, 0x42 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "crnor 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x4c, 0x43, 0x22, 0x42 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "creqv 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x4c, 0x43, 0x21, 0x02 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "crandc 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x4c, 0x43, 0x23, 0x42 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "crorc 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x4d, 0x0c, 0x00, 0x00 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mcrf 2, 3"
+  -
+    input:
+      bytes: [ 0x44, 0x00, 0x00, 0x22 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sc 1"
+  -
+    input:
+      bytes: [ 0x44, 0x00, 0x00, 0x02 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sc"
+  -
+    input:
+      bytes: [ 0x88, 0x44, 0x00, 0x80 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "lbz 2, 128(4)"
+  -
+    input:
+      bytes: [ 0x7c, 0x43, 0x20, 0xae ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "lbzx 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x8c, 0x44, 0x00, 0x80 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "lbzu 2, 128(4)"
+  -
+    input:
+      bytes: [ 0x7c, 0x43, 0x20, 0xee ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "lbzux 2, 3, 4"
+  -
+    input:
+      bytes: [ 0xa0, 0x44, 0x00, 0x80 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "lhz 2, 128(4)"
+  -
+    input:
+      bytes: [ 0x7c, 0x43, 0x22, 0x2e ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "lhzx 2, 3, 4"
+  -
+    input:
+      bytes: [ 0xa4, 0x44, 0x00, 0x80 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "lhzu 2, 128(4)"
+  -
+    input:
+      bytes: [ 0x7c, 0x43, 0x22, 0x6e ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "lhzux 2, 3, 4"
+  -
+    input:
+      bytes: [ 0xa8, 0x44, 0x00, 0x80 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "lha 2, 128(4)"
+  -
+    input:
+      bytes: [ 0x7c, 0x43, 0x22, 0xae ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "lhax 2, 3, 4"
+  -
+    input:
+      bytes: [ 0xac, 0x44, 0x00, 0x80 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "lhau 2, 128(4)"
+  -
+    input:
+      bytes: [ 0x7c, 0x43, 0x22, 0xee ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "lhaux 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x80, 0x44, 0x00, 0x80 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "lwz 2, 128(4)"
+  -
+    input:
+      bytes: [ 0x7c, 0x43, 0x20, 0x2e ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "lwzx 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x84, 0x44, 0x00, 0x80 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "lwzu 2, 128(4)"
+  -
+    input:
+      bytes: [ 0x7c, 0x43, 0x20, 0x6e ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "lwzux 2, 3, 4"
+  -
+    input:
+      bytes: [ 0xe8, 0x44, 0x00, 0x82 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "lwa 2, 128(4)"
+  -
+    input:
+      bytes: [ 0x7c, 0x43, 0x22, 0xaa ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "lwax 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x43, 0x22, 0xea ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "lwaux 2, 3, 4"
+  -
+    input:
+      bytes: [ 0xe8, 0x44, 0x00, 0x80 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld 2, 128(4)"
+  -
+    input:
+      bytes: [ 0x7c, 0x43, 0x20, 0x2a ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldx 2, 3, 4"
+  -
+    input:
+      bytes: [ 0xe8, 0x44, 0x00, 0x81 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldu 2, 128(4)"
+  -
+    input:
+      bytes: [ 0x7c, 0x43, 0x20, 0x6a ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldux 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x98, 0x44, 0x00, 0x80 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "stb 2, 128(4)"
+  -
+    input:
+      bytes: [ 0x7c, 0x43, 0x21, 0xae ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "stbx 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x9c, 0x44, 0x00, 0x80 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "stbu 2, 128(4)"
+  -
+    input:
+      bytes: [ 0x7c, 0x43, 0x21, 0xee ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "stbux 2, 3, 4"
+  -
+    input:
+      bytes: [ 0xb0, 0x44, 0x00, 0x80 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sth 2, 128(4)"
+  -
+    input:
+      bytes: [ 0x7c, 0x43, 0x23, 0x2e ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sthx 2, 3, 4"
+  -
+    input:
+      bytes: [ 0xb4, 0x44, 0x00, 0x80 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sthu 2, 128(4)"
+  -
+    input:
+      bytes: [ 0x7c, 0x43, 0x23, 0x6e ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sthux 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x90, 0x44, 0x00, 0x80 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "stw 2, 128(4)"
+  -
+    input:
+      bytes: [ 0x7c, 0x43, 0x21, 0x2e ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "stwx 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x94, 0x44, 0x00, 0x80 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "stwu 2, 128(4)"
+  -
+    input:
+      bytes: [ 0x7c, 0x43, 0x21, 0x6e ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "stwux 2, 3, 4"
+  -
+    input:
+      bytes: [ 0xf8, 0x44, 0x00, 0x80 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "std 2, 128(4)"
+  -
+    input:
+      bytes: [ 0x7c, 0x43, 0x21, 0x2a ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "stdx 2, 3, 4"
+  -
+    input:
+      bytes: [ 0xf8, 0x44, 0x00, 0x81 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "stdu 2, 128(4)"
+  -
+    input:
+      bytes: [ 0x7c, 0x43, 0x21, 0x6a ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "stdux 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x43, 0x26, 0x2c ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "lhbrx 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x43, 0x27, 0x2c ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sthbrx 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x43, 0x24, 0x2c ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "lwbrx 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x43, 0x25, 0x2c ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "stwbrx 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x43, 0x24, 0x28 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldbrx 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x43, 0x25, 0x28 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "stdbrx 2, 3, 4"
+  -
+    input:
+      bytes: [ 0xb8, 0x41, 0x00, 0x80 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "lmw 2, 128(1)"
+  -
+    input:
+      bytes: [ 0xbc, 0x41, 0x00, 0x80 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "stmw 2, 128(1)"
+  -
+    input:
+      bytes: [ 0x38, 0x43, 0x00, 0x80 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "addi 2, 3, 128"
+  -
+    input:
+      bytes: [ 0x3c, 0x43, 0x00, 0x80 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "addis 2, 3, 128"
+  -
+    input:
+      bytes: [ 0x7c, 0x43, 0x22, 0x14 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "add 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x43, 0x22, 0x15 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "add. 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x43, 0x20, 0x50 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub 2, 4, 3"
+  -
+    input:
+      bytes: [ 0x7c, 0x43, 0x20, 0x51 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub. 2, 4, 3"
+  -
+    input:
+      bytes: [ 0x30, 0x43, 0x00, 0x80 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "addic 2, 3, 128"
+  -
+    input:
+      bytes: [ 0x34, 0x43, 0x00, 0x80 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "addic. 2, 3, 128"
+  -
+    input:
+      bytes: [ 0x20, 0x43, 0x00, 0x04 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "subfic 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x43, 0x20, 0x14 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "addc 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x43, 0x20, 0x15 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "addc. 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x43, 0x20, 0x10 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "subc 2, 4, 3"
+  -
+    input:
+      bytes: [ 0x7c, 0x43, 0x21, 0x14 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "adde 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x43, 0x21, 0x15 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "adde. 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x43, 0x21, 0x10 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "subfe 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x43, 0x21, 0x11 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "subfe. 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x43, 0x01, 0xd4 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "addme 2, 3"
+  -
+    input:
+      bytes: [ 0x7c, 0x43, 0x01, 0xd5 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "addme. 2, 3"
+  -
+    input:
+      bytes: [ 0x7c, 0x43, 0x01, 0xd0 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "subfme 2, 3"
+  -
+    input:
+      bytes: [ 0x7c, 0x43, 0x01, 0xd1 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "subfme. 2, 3"
+  -
+    input:
+      bytes: [ 0x7c, 0x43, 0x01, 0x94 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "addze 2, 3"
+  -
+    input:
+      bytes: [ 0x7c, 0x43, 0x01, 0x95 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "addze. 2, 3"
+  -
+    input:
+      bytes: [ 0x7c, 0x43, 0x01, 0x90 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "subfze 2, 3"
+  -
+    input:
+      bytes: [ 0x7c, 0x43, 0x01, 0x91 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "subfze. 2, 3"
+  -
+    input:
+      bytes: [ 0x7c, 0x43, 0x00, 0xd0 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "neg 2, 3"
+  -
+    input:
+      bytes: [ 0x7c, 0x43, 0x00, 0xd1 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "neg. 2, 3"
+  -
+    input:
+      bytes: [ 0x1c, 0x43, 0x00, 0x80 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulli 2, 3, 128"
+  -
+    input:
+      bytes: [ 0x7c, 0x43, 0x20, 0x96 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulhw 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x43, 0x20, 0x97 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulhw. 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x43, 0x21, 0xd6 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mullw 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x43, 0x21, 0xd7 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mullw. 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x43, 0x20, 0x16 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulhwu 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x43, 0x20, 0x17 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulhwu. 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x43, 0x23, 0xd6 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "divw 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x43, 0x23, 0xd7 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "divw. 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x43, 0x23, 0x96 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "divwu 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x43, 0x23, 0x97 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "divwu. 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x43, 0x21, 0xd2 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulld 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x43, 0x21, 0xd3 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulld. 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x43, 0x20, 0x92 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulhd 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x43, 0x20, 0x93 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulhd. 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x43, 0x20, 0x12 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulhdu 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x43, 0x20, 0x13 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulhdu. 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x43, 0x23, 0xd2 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "divd 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x43, 0x23, 0xd3 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "divd. 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x43, 0x23, 0x92 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "divdu 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x43, 0x23, 0x93 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "divdu. 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x2d, 0x23, 0x00, 0x80 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpdi 2, 3, 128"
+  -
+    input:
+      bytes: [ 0x7d, 0x23, 0x20, 0x00 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpd 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x29, 0x23, 0x00, 0x80 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpldi 2, 3, 128"
+  -
+    input:
+      bytes: [ 0x7d, 0x23, 0x20, 0x40 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpld 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x2d, 0x03, 0x00, 0x80 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpwi 2, 3, 128"
+  -
+    input:
+      bytes: [ 0x7d, 0x03, 0x20, 0x00 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpw 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x29, 0x03, 0x00, 0x80 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmplwi 2, 3, 128"
+  -
+    input:
+      bytes: [ 0x7d, 0x03, 0x20, 0x40 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmplw 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x0c, 0x43, 0x00, 0x04 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "twllti 3, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x43, 0x20, 0x08 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "twllt 3, 4"
+  -
+    input:
+      bytes: [ 0x08, 0x43, 0x00, 0x04 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "tdllti 3, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x43, 0x20, 0x88 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "tdllt 3, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x43, 0x21, 0x5e ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "isel 2, 3, 4, 5"
+  -
+    input:
+      bytes: [ 0x70, 0x62, 0x00, 0x80 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "andi. 2, 3, 128"
+  -
+    input:
+      bytes: [ 0x74, 0x62, 0x00, 0x80 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "andis. 2, 3, 128"
+  -
+    input:
+      bytes: [ 0x60, 0x62, 0x00, 0x80 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ori 2, 3, 128"
+  -
+    input:
+      bytes: [ 0x64, 0x62, 0x00, 0x80 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "oris 2, 3, 128"
+  -
+    input:
+      bytes: [ 0x68, 0x62, 0x00, 0x80 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "xori 2, 3, 128"
+  -
+    input:
+      bytes: [ 0x6c, 0x62, 0x00, 0x80 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "xoris 2, 3, 128"
+  -
+    input:
+      bytes: [ 0x7c, 0x62, 0x20, 0x38 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "and 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x62, 0x20, 0x39 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "and. 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x62, 0x22, 0x78 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x62, 0x22, 0x79 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor. 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x62, 0x23, 0xb8 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "nand 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x62, 0x23, 0xb9 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "nand. 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x62, 0x23, 0x78 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "or 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x62, 0x23, 0x79 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "or. 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x62, 0x20, 0xf8 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "nor 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x62, 0x20, 0xf9 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "nor. 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x62, 0x22, 0x38 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "eqv 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x62, 0x22, 0x39 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "eqv. 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x62, 0x20, 0x78 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "andc 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x62, 0x20, 0x79 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "andc. 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x62, 0x23, 0x38 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "orc 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x62, 0x23, 0x39 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "orc. 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x62, 0x07, 0x74 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "extsb 2, 3"
+  -
+    input:
+      bytes: [ 0x7c, 0x62, 0x07, 0x75 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "extsb. 2, 3"
+  -
+    input:
+      bytes: [ 0x7c, 0x62, 0x07, 0x34 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "extsh 2, 3"
+  -
+    input:
+      bytes: [ 0x7c, 0x62, 0x07, 0x35 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "extsh. 2, 3"
+  -
+    input:
+      bytes: [ 0x7c, 0x62, 0x00, 0x34 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cntlzw 2, 3"
+  -
+    input:
+      bytes: [ 0x7c, 0x62, 0x00, 0x35 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cntlzw. 2, 3"
+  -
+    input:
+      bytes: [ 0x7c, 0x62, 0x02, 0xf4 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "popcntw 2, 3"
+  -
+    input:
+      bytes: [ 0x7c, 0x62, 0x07, 0xb4 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "extsw 2, 3"
+  -
+    input:
+      bytes: [ 0x7c, 0x62, 0x07, 0xb5 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "extsw. 2, 3"
+  -
+    input:
+      bytes: [ 0x7c, 0x62, 0x00, 0x74 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cntlzd 2, 3"
+  -
+    input:
+      bytes: [ 0x7c, 0x62, 0x00, 0x75 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cntlzd. 2, 3"
+  -
+    input:
+      bytes: [ 0x7c, 0x62, 0x03, 0xf4 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "popcntd 2, 3"
+  -
+    input:
+      bytes: [ 0x54, 0x62, 0x21, 0x4c ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "rlwinm 2, 3, 4, 5, 6"
+  -
+    input:
+      bytes: [ 0x54, 0x62, 0x21, 0x4d ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "rlwinm. 2, 3, 4, 5, 6"
+  -
+    input:
+      bytes: [ 0x5c, 0x62, 0x21, 0x4c ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "rlwnm 2, 3, 4, 5, 6"
+  -
+    input:
+      bytes: [ 0x5c, 0x62, 0x21, 0x4d ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "rlwnm. 2, 3, 4, 5, 6"
+  -
+    input:
+      bytes: [ 0x50, 0x62, 0x21, 0x4c ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "rlwimi 2, 3, 4, 5, 6"
+  -
+    input:
+      bytes: [ 0x50, 0x62, 0x21, 0x4d ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "rlwimi. 2, 3, 4, 5, 6"
+  -
+    input:
+      bytes: [ 0x78, 0x62, 0x21, 0x40 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "rldicl 2, 3, 4, 5"
+  -
+    input:
+      bytes: [ 0x78, 0x62, 0x21, 0x41 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "rldicl. 2, 3, 4, 5"
+  -
+    input:
+      bytes: [ 0x78, 0x62, 0x21, 0x44 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "rldicr 2, 3, 4, 5"
+  -
+    input:
+      bytes: [ 0x78, 0x62, 0x21, 0x45 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "rldicr. 2, 3, 4, 5"
+  -
+    input:
+      bytes: [ 0x78, 0x62, 0x21, 0x48 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "rldic 2, 3, 4, 5"
+  -
+    input:
+      bytes: [ 0x78, 0x62, 0x21, 0x49 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "rldic. 2, 3, 4, 5"
+  -
+    input:
+      bytes: [ 0x78, 0x62, 0x21, 0x50 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "rldcl 2, 3, 4, 5"
+  -
+    input:
+      bytes: [ 0x78, 0x62, 0x21, 0x51 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "rldcl. 2, 3, 4, 5"
+  -
+    input:
+      bytes: [ 0x78, 0x62, 0x21, 0x52 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "rldcr 2, 3, 4, 5"
+  -
+    input:
+      bytes: [ 0x78, 0x62, 0x21, 0x53 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "rldcr. 2, 3, 4, 5"
+  -
+    input:
+      bytes: [ 0x78, 0x62, 0x21, 0x4c ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "rldimi 2, 3, 4, 5"
+  -
+    input:
+      bytes: [ 0x78, 0x62, 0x21, 0x4d ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "rldimi. 2, 3, 4, 5"
+  -
+    input:
+      bytes: [ 0x7c, 0x62, 0x20, 0x30 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "slw 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x62, 0x20, 0x31 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "slw. 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x62, 0x24, 0x30 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "srw 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x62, 0x24, 0x31 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "srw. 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x62, 0x26, 0x70 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "srawi 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x62, 0x26, 0x71 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "srawi. 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x62, 0x26, 0x30 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sraw 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x62, 0x26, 0x31 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sraw. 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x62, 0x20, 0x36 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sld 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x62, 0x20, 0x37 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sld. 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x62, 0x24, 0x36 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "srd 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x62, 0x24, 0x37 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "srd. 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x62, 0x26, 0x74 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sradi 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x62, 0x26, 0x75 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sradi. 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x62, 0x26, 0x34 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "srad 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x62, 0x26, 0x35 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "srad. 2, 3, 4"
+  -
+    input:
+      bytes: [ 0x7c, 0x58, 0x93, 0xa6 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mtspr 600, 2"
+  -
+    input:
+      bytes: [ 0x7c, 0x58, 0x92, 0xa6 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mfspr 2, 600"
+  -
+    input:
+      bytes: [ 0x7c, 0x47, 0xb1, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mtcrf 123, 2"
+  -
+    input:
+      bytes: [ 0x7c, 0x40, 0x00, 0x26 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mfcr 2"
+  -
+    input:
+      bytes: [ 0x7c, 0x51, 0x01, 0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mtocrf 16, 2"
+  -
+    input:
+      bytes: [ 0x7e, 0x10, 0x80, 0x26 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mfocrf 16, 8"
diff --git a/tests/MC/PowerPC/ppc64-operands.s.yaml b/tests/MC/PowerPC/ppc64-operands.s.yaml
new file mode 100644
index 000000000..d85e7ba1a
--- /dev/null
+++ b/tests/MC/PowerPC/ppc64-operands.s.yaml
@@ -0,0 +1,275 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x7c, 0x22, 0x1a, 0x14 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "add 1, 2, 3"
+  -
+    input:
+      bytes: [ 0x7c, 0x22, 0x1a, 0x14 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "add 1, 2, 3"
+  -
+    input:
+      bytes: [ 0x7c, 0x00, 0x02, 0x14 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "add 0, 0, 0"
+  -
+    input:
+      bytes: [ 0x7f, 0xff, 0xfa, 0x14 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "add 31, 31, 31"
+  -
+    input:
+      bytes: [ 0x38, 0x20, 0x00, 0x00 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "li 1, 0"
+  -
+    input:
+      bytes: [ 0x38, 0x22, 0x00, 0x00 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "addi 1, 2, 0"
+  -
+    input:
+      bytes: [ 0x38, 0x20, 0x80, 0x00 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "li 1, -0x8000"
+  -
+    input:
+      bytes: [ 0x38, 0x20, 0x7f, 0xff ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "li 1, 0x7fff"
+  -
+    input:
+      bytes: [ 0x60, 0x41, 0x00, 0x00 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ori 1, 2, 0"
+  -
+    input:
+      bytes: [ 0x60, 0x41, 0xff, 0xff ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ori 1, 2, 65535"
+  -
+    input:
+      bytes: [ 0x3c, 0x20, 0x00, 0x00 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "lis 1, 0"
+  -
+    input:
+      bytes: [ 0x3c, 0x20, 0xff, 0xff ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "lis 1, -1"
+  -
+    input:
+      bytes: [ 0x80, 0x20, 0x00, 0x00 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "lwz 1, 0(0)"
+  -
+    input:
+      bytes: [ 0x80, 0x20, 0x00, 0x00 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "lwz 1, 0(0)"
+  -
+    input:
+      bytes: [ 0x80, 0x3f, 0x00, 0x00 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "lwz 1, 0(31)"
+  -
+    input:
+      bytes: [ 0x80, 0x3f, 0x00, 0x00 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "lwz 1, 0(31)"
+  -
+    input:
+      bytes: [ 0x80, 0x22, 0x80, 0x00 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "lwz 1, -32768(2)"
+  -
+    input:
+      bytes: [ 0x80, 0x22, 0x7f, 0xff ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "lwz 1, 32767(2)"
+  -
+    input:
+      bytes: [ 0xe8, 0x20, 0x00, 0x00 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld 1, 0(0)"
+  -
+    input:
+      bytes: [ 0xe8, 0x20, 0x00, 0x00 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld 1, 0(0)"
+  -
+    input:
+      bytes: [ 0xe8, 0x3f, 0x00, 0x00 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld 1, 0(31)"
+  -
+    input:
+      bytes: [ 0xe8, 0x3f, 0x00, 0x00 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld 1, 0(31)"
+  -
+    input:
+      bytes: [ 0xe8, 0x22, 0x80, 0x00 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld 1, -32768(2)"
+  -
+    input:
+      bytes: [ 0xe8, 0x22, 0x7f, 0xfc ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld 1, 32764(2)"
+  -
+    input:
+      bytes: [ 0xe8, 0x22, 0x00, 0x04 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld 1, 4(2)"
+  -
+    input:
+      bytes: [ 0xe8, 0x22, 0xff, 0xfc ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld 1, -4(2)"
+  -
+    input:
+      bytes: [ 0x48, 0x00, 0x04, 0x00 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "b 1024"
+    skip_reason: "Note: The assemble accepts it with .+. But the disassembler just returns the scalar."
+
+  -
+    input:
+      bytes: [ 0x48, 0x00, 0x04, 0x02 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ba 1024"
+  -
+    input:
+      bytes: [ 0x41, 0x82, 0x04, 0x00 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bt 2, 1024"
+    skip_reason: "Note: The assemble accepts it with .+. But the disassembler just returns the scalar."
+
+  -
+    input:
+      bytes: [ 0x41, 0x82, 0x04, 0x02 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_NOREGNAME", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "bta 2, 1024"
diff --git a/tests/MC/PowerPC/qpx.s.yaml b/tests/MC/PowerPC/qpx.s.yaml
new file mode 100644
index 000000000..a3d99f02b
--- /dev/null
+++ b/tests/MC/PowerPC/qpx.s.yaml
@@ -0,0 +1,1117 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x10, 0x60, 0x2a, 0x10 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvfabs q3, q5"
+  -
+    input:
+      bytes: [ 0x10, 0x60, 0x2a, 0x10 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvfabs q3, q5"
+  -
+    input:
+      bytes: [ 0x10, 0x64, 0x28, 0x2a ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvfadd q3, q4, q5"
+  -
+    input:
+      bytes: [ 0x00, 0x64, 0x28, 0x2a ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvfadds q3, q4, q5"
+  -
+    input:
+      bytes: [ 0x10, 0x64, 0x2a, 0x08 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvfandc q3, q4, q5"
+  -
+    input:
+      bytes: [ 0x10, 0x64, 0x28, 0x88 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvfand q3, q4, q5"
+  -
+    input:
+      bytes: [ 0x10, 0x60, 0x2e, 0x9c ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvfcfid q3, q5"
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0x2e, 0x9c ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvfcfids q3, q5"
+  -
+    input:
+      bytes: [ 0x10, 0x60, 0x2f, 0x9c ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvfcfidu q3, q5"
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0x2f, 0x9c ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvfcfidus q3, q5"
+  -
+    input:
+      bytes: [ 0x10, 0x63, 0x18, 0x08 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvfclr q3"
+  -
+    input:
+      bytes: [ 0x10, 0x64, 0x28, 0x10 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvfcpsgn q3, q4, q5"
+  -
+    input:
+      bytes: [ 0x10, 0x64, 0x22, 0x88 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvfctfb q3, q4"
+  -
+    input:
+      bytes: [ 0x10, 0x60, 0x2e, 0x5c ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvfctid q3, q5"
+  -
+    input:
+      bytes: [ 0x10, 0x60, 0x2f, 0x5c ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvfctidu q3, q5"
+  -
+    input:
+      bytes: [ 0x10, 0x60, 0x2f, 0x5e ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvfctiduz q3, q5"
+  -
+    input:
+      bytes: [ 0x10, 0x60, 0x2e, 0x5e ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvfctidz q3, q5"
+  -
+    input:
+      bytes: [ 0x10, 0x60, 0x28, 0x1c ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvfctiw q3, q5"
+  -
+    input:
+      bytes: [ 0x10, 0x60, 0x29, 0x1c ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvfctiwu q3, q5"
+  -
+    input:
+      bytes: [ 0x10, 0x60, 0x29, 0x1e ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvfctiwuz q3, q5"
+  -
+    input:
+      bytes: [ 0x10, 0x60, 0x28, 0x1e ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvfctiwz q3, q5"
+  -
+    input:
+      bytes: [ 0x10, 0x64, 0x2c, 0x88 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvfequ q3, q4, q5"
+  -
+    input:
+      bytes: [ 0x10, 0x64, 0x2e, 0x08 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvflogical q3, q4, q5, 12"
+  -
+    input:
+      bytes: [ 0x10, 0x64, 0x29, 0xba ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvfmadd q3, q4, q6, q5"
+  -
+    input:
+      bytes: [ 0x00, 0x64, 0x29, 0xba ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvfmadds q3, q4, q6, q5"
+  -
+    input:
+      bytes: [ 0x10, 0x60, 0x28, 0x90 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvfmr q3, q5"
+  -
+    input:
+      bytes: [ 0x10, 0x64, 0x29, 0xb8 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvfmsub q3, q4, q6, q5"
+  -
+    input:
+      bytes: [ 0x00, 0x64, 0x29, 0xb8 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvfmsubs q3, q4, q6, q5"
+  -
+    input:
+      bytes: [ 0x10, 0x64, 0x01, 0xb2 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvfmul q3, q4, q6"
+  -
+    input:
+      bytes: [ 0x00, 0x64, 0x01, 0xb2 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvfmuls q3, q4, q6"
+  -
+    input:
+      bytes: [ 0x10, 0x60, 0x29, 0x10 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvfnabs q3, q5"
+  -
+    input:
+      bytes: [ 0x10, 0x64, 0x2f, 0x08 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvfnand q3, q4, q5"
+  -
+    input:
+      bytes: [ 0x10, 0x60, 0x28, 0x50 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvfneg q3, q5"
+  -
+    input:
+      bytes: [ 0x10, 0x64, 0x29, 0xbe ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvfnmadd q3, q4, q6, q5"
+  -
+    input:
+      bytes: [ 0x00, 0x64, 0x29, 0xbe ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvfnmadds q3, q4, q6, q5"
+  -
+    input:
+      bytes: [ 0x10, 0x64, 0x29, 0xbc ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvfnmsub q3, q4, q6, q5"
+  -
+    input:
+      bytes: [ 0x00, 0x64, 0x29, 0xbc ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvfnmsubs q3, q4, q6, q5"
+  -
+    input:
+      bytes: [ 0x10, 0x64, 0x2c, 0x08 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvfnor q3, q4, q5"
+  -
+    input:
+      bytes: [ 0x10, 0x64, 0x25, 0x08 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvfnot q3, q4"
+  -
+    input:
+      bytes: [ 0x10, 0x64, 0x2e, 0x88 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvforc q3, q4, q5"
+  -
+    input:
+      bytes: [ 0x10, 0x64, 0x2b, 0x88 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvfor q3, q4, q5"
+  -
+    input:
+      bytes: [ 0x10, 0x64, 0x29, 0x8c ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvfperm q3, q4, q5, q6"
+  -
+    input:
+      bytes: [ 0x10, 0x60, 0x28, 0x30 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvfre q3, q5"
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0x28, 0x30 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvfres q3, q5"
+  -
+    input:
+      bytes: [ 0x10, 0x60, 0x2b, 0xd0 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvfrim q3, q5"
+  -
+    input:
+      bytes: [ 0x10, 0x60, 0x2b, 0x10 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvfrin q3, q5"
+  -
+    input:
+      bytes: [ 0x10, 0x60, 0x2b, 0x90 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvfrip q3, q5"
+  -
+    input:
+      bytes: [ 0x10, 0x60, 0x2b, 0x50 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvfriz q3, q5"
+  -
+    input:
+      bytes: [ 0x10, 0x60, 0x28, 0x18 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvfrsp q3, q5"
+  -
+    input:
+      bytes: [ 0x10, 0x60, 0x28, 0x34 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvfrsqrte q3, q5"
+  -
+    input:
+      bytes: [ 0x00, 0x60, 0x28, 0x34 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvfrsqrtes q3, q5"
+  -
+    input:
+      bytes: [ 0x10, 0x64, 0x29, 0xae ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvfsel q3, q4, q6, q5"
+  -
+    input:
+      bytes: [ 0x10, 0x63, 0x1f, 0x88 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvfset q3"
+  -
+    input:
+      bytes: [ 0x10, 0x64, 0x28, 0x28 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvfsub q3, q4, q5"
+  -
+    input:
+      bytes: [ 0x00, 0x64, 0x28, 0x28 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvfsubs q3, q4, q5"
+  -
+    input:
+      bytes: [ 0x10, 0x64, 0x29, 0x92 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvfxmadd q3, q4, q6, q5"
+  -
+    input:
+      bytes: [ 0x00, 0x64, 0x29, 0x92 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvfxmadds q3, q4, q6, q5"
+  -
+    input:
+      bytes: [ 0x10, 0x64, 0x01, 0xa2 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvfxmul q3, q4, q6"
+  -
+    input:
+      bytes: [ 0x00, 0x64, 0x01, 0xa2 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvfxmuls q3, q4, q6"
+  -
+    input:
+      bytes: [ 0x10, 0x64, 0x2b, 0x08 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvfxor q3, q4, q5"
+  -
+    input:
+      bytes: [ 0x10, 0x64, 0x29, 0x86 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvfxxcpnmadd q3, q4, q6, q5"
+  -
+    input:
+      bytes: [ 0x00, 0x64, 0x29, 0x86 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvfxxcpnmadds q3, q4, q6, q5"
+  -
+    input:
+      bytes: [ 0x10, 0x64, 0x29, 0x82 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvfxxmadd q3, q4, q6, q5"
+  -
+    input:
+      bytes: [ 0x00, 0x64, 0x29, 0x82 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvfxxmadds q3, q4, q6, q5"
+  -
+    input:
+      bytes: [ 0x10, 0x64, 0x29, 0x96 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvfxxnpmadd q3, q4, q6, q5"
+  -
+    input:
+      bytes: [ 0x00, 0x64, 0x29, 0x96 ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvfxxnpmadds q3, q4, q6, q5"
+  -
+    input:
+      bytes: [ 0x7c, 0x69, 0x58, 0xcf ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvlfcduxa q3, r9, r11"
+  -
+    input:
+      bytes: [ 0x7c, 0x69, 0x58, 0xce ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvlfcdux q3, r9, r11"
+  -
+    input:
+      bytes: [ 0x7c, 0x6a, 0x58, 0x8f ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvlfcdxa q3, r10, r11"
+  -
+    input:
+      bytes: [ 0x7c, 0x6a, 0x58, 0x8e ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvlfcdx q3, r10, r11"
+  -
+    input:
+      bytes: [ 0x7c, 0x69, 0x58, 0x4f ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvlfcsuxa q3, r9, r11"
+  -
+    input:
+      bytes: [ 0x7c, 0x69, 0x58, 0x4e ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvlfcsux q3, r9, r11"
+  -
+    input:
+      bytes: [ 0x7c, 0x6a, 0x58, 0x0f ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvlfcsxa q3, r10, r11"
+  -
+    input:
+      bytes: [ 0x7c, 0x6a, 0x58, 0x0e ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvlfcsx q3, r10, r11"
+  -
+    input:
+      bytes: [ 0x7c, 0x69, 0x5c, 0xcf ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvlfduxa q3, r9, r11"
+  -
+    input:
+      bytes: [ 0x7c, 0x69, 0x5c, 0xce ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvlfdux q3, r9, r11"
+  -
+    input:
+      bytes: [ 0x7c, 0x6a, 0x5c, 0x8f ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvlfdxa q3, r10, r11"
+  -
+    input:
+      bytes: [ 0x7c, 0x6a, 0x5c, 0x8e ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvlfdx q3, r10, r11"
+  -
+    input:
+      bytes: [ 0x7c, 0x6a, 0x5e, 0xcf ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvlfiwaxa q3, r10, r11"
+  -
+    input:
+      bytes: [ 0x7c, 0x6a, 0x5e, 0xce ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvlfiwax q3, r10, r11"
+  -
+    input:
+      bytes: [ 0x7c, 0x6a, 0x5e, 0x8f ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvlfiwzxa q3, r10, r11"
+  -
+    input:
+      bytes: [ 0x7c, 0x6a, 0x5e, 0x8e ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvlfiwzx q3, r10, r11"
+  -
+    input:
+      bytes: [ 0x7c, 0x69, 0x5c, 0x4f ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvlfsuxa q3, r9, r11"
+  -
+    input:
+      bytes: [ 0x7c, 0x69, 0x5c, 0x4e ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvlfsux q3, r9, r11"
+  -
+    input:
+      bytes: [ 0x7c, 0x6a, 0x5c, 0x0f ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvlfsxa q3, r10, r11"
+  -
+    input:
+      bytes: [ 0x7c, 0x6a, 0x5c, 0x0e ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvlfsx q3, r10, r11"
+  -
+    input:
+      bytes: [ 0x7c, 0x6a, 0x5c, 0x8c ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvlpcldx q3, r10, r11"
+  -
+    input:
+      bytes: [ 0x7c, 0x6a, 0x5c, 0x0c ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvlpclsx q3, r10, r11"
+  -
+    input:
+      bytes: [ 0x7c, 0x6a, 0x58, 0x8c ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvlpcrdx q3, r10, r11"
+  -
+    input:
+      bytes: [ 0x7c, 0x6a, 0x58, 0x0c ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvlpcrsx q3, r10, r11"
+  -
+    input:
+      bytes: [ 0x7c, 0x49, 0x59, 0xcf ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvstfcduxa q2, r9, r11"
+  -
+    input:
+      bytes: [ 0x7c, 0x49, 0x59, 0xcb ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvstfcduxia q2, r9, r11"
+  -
+    input:
+      bytes: [ 0x7c, 0x49, 0x59, 0xca ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvstfcduxi q2, r9, r11"
+  -
+    input:
+      bytes: [ 0x7c, 0x49, 0x59, 0xce ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvstfcdux q2, r9, r11"
+  -
+    input:
+      bytes: [ 0x7c, 0x4a, 0x59, 0x8f ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvstfcdxa q2, r10, r11"
+  -
+    input:
+      bytes: [ 0x7c, 0x4a, 0x59, 0x8b ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvstfcdxia q2, r10, r11"
+  -
+    input:
+      bytes: [ 0x7c, 0x4a, 0x59, 0x8a ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvstfcdxi q2, r10, r11"
+  -
+    input:
+      bytes: [ 0x7c, 0x4a, 0x59, 0x8e ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvstfcdx q2, r10, r11"
+  -
+    input:
+      bytes: [ 0x7c, 0x49, 0x59, 0x4f ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvstfcsuxa q2, r9, r11"
+  -
+    input:
+      bytes: [ 0x7c, 0x49, 0x59, 0x4b ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvstfcsuxia q2, r9, r11"
+  -
+    input:
+      bytes: [ 0x7c, 0x49, 0x59, 0x4a ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvstfcsuxi q2, r9, r11"
+  -
+    input:
+      bytes: [ 0x7c, 0x49, 0x59, 0x4e ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvstfcsux q2, r9, r11"
+  -
+    input:
+      bytes: [ 0x7c, 0x4a, 0x59, 0x0f ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvstfcsxa q2, r10, r11"
+  -
+    input:
+      bytes: [ 0x7c, 0x4a, 0x59, 0x0b ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvstfcsxia q2, r10, r11"
+  -
+    input:
+      bytes: [ 0x7c, 0x4a, 0x59, 0x0a ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvstfcsxi q2, r10, r11"
+  -
+    input:
+      bytes: [ 0x7c, 0x4a, 0x59, 0x0e ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvstfcsx q2, r10, r11"
+  -
+    input:
+      bytes: [ 0x7c, 0x49, 0x5d, 0xcf ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvstfduxa q2, r9, r11"
+  -
+    input:
+      bytes: [ 0x7c, 0x49, 0x5d, 0xcb ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvstfduxia q2, r9, r11"
+  -
+    input:
+      bytes: [ 0x7c, 0x49, 0x5d, 0xca ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvstfduxi q2, r9, r11"
+  -
+    input:
+      bytes: [ 0x7c, 0x49, 0x5d, 0xce ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvstfdux q2, r9, r11"
+  -
+    input:
+      bytes: [ 0x7c, 0x4a, 0x5d, 0x8f ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvstfdxa q2, r10, r11"
+  -
+    input:
+      bytes: [ 0x7c, 0x4a, 0x5d, 0x8b ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvstfdxia q2, r10, r11"
+  -
+    input:
+      bytes: [ 0x7c, 0x4a, 0x5d, 0x8a ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvstfdxi q2, r10, r11"
+  -
+    input:
+      bytes: [ 0x7c, 0x4a, 0x5d, 0x8e ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvstfdx q2, r10, r11"
+  -
+    input:
+      bytes: [ 0x7c, 0x4a, 0x5f, 0x8f ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvstfiwxa q2, r10, r11"
+  -
+    input:
+      bytes: [ 0x7c, 0x4a, 0x5f, 0x8e ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvstfiwx q2, r10, r11"
+  -
+    input:
+      bytes: [ 0x7c, 0x49, 0x5d, 0x4f ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvstfsuxa q2, r9, r11"
+  -
+    input:
+      bytes: [ 0x7c, 0x49, 0x5d, 0x4b ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvstfsuxia q2, r9, r11"
+  -
+    input:
+      bytes: [ 0x7c, 0x49, 0x5d, 0x4a ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvstfsuxi q2, r9, r11"
+  -
+    input:
+      bytes: [ 0x7c, 0x49, 0x5d, 0x4e ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvstfsux q2, r9, r11"
+  -
+    input:
+      bytes: [ 0x7c, 0x4a, 0x5d, 0x0f ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvstfsxa q2, r10, r11"
+  -
+    input:
+      bytes: [ 0x7c, 0x4a, 0x5d, 0x0b ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvstfsxia q2, r10, r11"
+  -
+    input:
+      bytes: [ 0x7c, 0x4a, 0x5d, 0x0a ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvstfsxi q2, r10, r11"
+  -
+    input:
+      bytes: [ 0x7c, 0x4a, 0x5d, 0x0e ]
+      arch: "CS_ARCH_PPC"
+      options: [ "CS_OPT_SYNTAX_DEFAULT", "CS_MODE_QPX", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "qvstfsx q2, r10, r11"
diff --git a/tests/MC/RISCV/insn-riscv32.s.yaml b/tests/MC/RISCV/insn-riscv32.s.yaml
new file mode 100644
index 000000000..b425cea48
--- /dev/null
+++ b/tests/MC/RISCV/insn-riscv32.s.yaml
@@ -0,0 +1,91 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x37, 0x34, 0x00, 0x00 ]
+      arch: "CS_ARCH_RISCV"
+      options: [ "CS_MODE_RISCV32" ]
+    expected:
+      insns:
+        -
+          asm_text: "lui s0, 3"
+  -
+    input:
+      bytes: [ 0x97, 0x82, 0x00, 0x00 ]
+      arch: "CS_ARCH_RISCV"
+      options: [ "CS_MODE_RISCV32" ]
+    expected:
+      insns:
+        -
+          asm_text: "auipc t0, 8"
+  -
+    input:
+      bytes: [ 0x2f, 0xae, 0xaa, 0x0a ]
+      arch: "CS_ARCH_RISCV"
+      options: [ "CS_MODE_RISCV32" ]
+    expected:
+      insns:
+        -
+          asm_text: "amoswap.w.rl t3, a0, (s5)"
+  -
+    input:
+      bytes: [ 0xe3, 0x1f, 0x31, 0x5e ]
+      arch: "CS_ARCH_RISCV"
+      options: [ "CS_MODE_RISCV32" ]
+    expected:
+      insns:
+        -
+          asm_text: "bne sp, gp, 0xdfe"
+  -
+    input:
+      bytes: [ 0x73, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_RISCV"
+      options: [ "CS_MODE_RISCV32" ]
+    expected:
+      insns:
+        -
+          asm_text: "ecall"
+  -
+    input:
+      bytes: [ 0x33, 0x00, 0x31, 0x02 ]
+      arch: "CS_ARCH_RISCV"
+      options: [ "CS_MODE_RISCV32" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul zero, sp, gp"
+  -
+    input:
+      bytes: [ 0x53, 0x00, 0x31, 0x28 ]
+      arch: "CS_ARCH_RISCV"
+      options: [ "CS_MODE_RISCV32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmin.s ft0, ft2, ft3"
+  -
+    input:
+      bytes: [ 0x53, 0x10, 0x31, 0x2a ]
+      arch: "CS_ARCH_RISCV"
+      options: [ "CS_MODE_RISCV32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmax.d ft0, ft2, ft3"
+  -
+    input:
+      bytes: [ 0x27, 0xaa, 0x6a, 0x00 ]
+      arch: "CS_ARCH_RISCV"
+      options: [ "CS_MODE_RISCV32" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsw ft6, 0x14(s5)"
+  -
+    input:
+      bytes: [ 0xef, 0xf0, 0x1f, 0xff ]
+      arch: "CS_ARCH_RISCV"
+      options: [ "CS_MODE_RISCV32" ]
+    expected:
+      insns:
+        -
+          asm_text: "jal -0x10"
diff --git a/tests/MC/RISCV/insn-riscv64.s.yaml b/tests/MC/RISCV/insn-riscv64.s.yaml
new file mode 100644
index 000000000..9fdbb1936
--- /dev/null
+++ b/tests/MC/RISCV/insn-riscv64.s.yaml
@@ -0,0 +1,55 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x13, 0x04, 0xa8, 0x7a ]
+      arch: "CS_ARCH_RISCV"
+      options: [ "CS_MODE_RISCV64" ]
+    expected:
+      insns:
+        -
+          asm_text: "addi s0, a6, 0x7aa"
+  -
+    input:
+      bytes: [ 0x1b, 0x8e, 0xaa, 0x2a ]
+      arch: "CS_ARCH_RISCV"
+      options: [ "CS_MODE_RISCV64" ]
+    expected:
+      insns:
+        -
+          asm_text: "addiw t3, s5, 0x2aa"
+  -
+    input:
+      bytes: [ 0x2f, 0xbe, 0xaa, 0x0a ]
+      arch: "CS_ARCH_RISCV"
+      options: [ "CS_MODE_RISCV64" ]
+    expected:
+      insns:
+        -
+          asm_text: "amoswap.d.rl t3, a0, (s5)"
+  -
+    input:
+      bytes: [ 0x3b, 0x00, 0x31, 0x02 ]
+      arch: "CS_ARCH_RISCV"
+      options: [ "CS_MODE_RISCV64" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulw zero, sp, gp"
+  -
+    input:
+      bytes: [ 0x53, 0xa0, 0x31, 0xd0 ]
+      arch: "CS_ARCH_RISCV"
+      options: [ "CS_MODE_RISCV64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcvt.s.lu ft0, gp, rdn"
+  -
+    input:
+      bytes: [ 0x53, 0x81, 0x01, 0xf2 ]
+      arch: "CS_ARCH_RISCV"
+      options: [ "CS_MODE_RISCV64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmv.d.x ft2, gp"
diff --git a/tests/MC/Sparc/sparc-alu-instructions.s.yaml b/tests/MC/Sparc/sparc-alu-instructions.s.yaml
new file mode 100644
index 000000000..7e777e3c2
--- /dev/null
+++ b/tests/MC/Sparc/sparc-alu-instructions.s.yaml
@@ -0,0 +1,415 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x80, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "add %g0, %g0, %g0"
+  -
+    input:
+      bytes: [ 0x86, 0x00, 0x40, 0x02 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "add %g1, %g2, %g3"
+  -
+    input:
+      bytes: [ 0xa0, 0x02, 0x00, 0x09 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "add %o0, %o1, %l0"
+  -
+    input:
+      bytes: [ 0xa0, 0x02, 0x20, 0x0a ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "add %o0, 10, %l0"
+  -
+    input:
+      bytes: [ 0x86, 0x80, 0x40, 0x02 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "addcc %g1, %g2, %g3"
+  -
+    input:
+      bytes: [ 0x86, 0xc0, 0x40, 0x02 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "addxcc %g1, %g2, %g3"
+  -
+    input:
+      bytes: [ 0x86, 0x70, 0x40, 0x02 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "udiv %g1, %g2, %g3"
+  -
+    input:
+      bytes: [ 0x86, 0x78, 0x40, 0x02 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdiv %g1, %g2, %g3"
+  -
+    input:
+      bytes: [ 0x86, 0x08, 0x40, 0x02 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "and %g1, %g2, %g3"
+  -
+    input:
+      bytes: [ 0x86, 0x28, 0x40, 0x02 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "andn %g1, %g2, %g3"
+  -
+    input:
+      bytes: [ 0x86, 0x10, 0x40, 0x02 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "or %g1, %g2, %g3"
+  -
+    input:
+      bytes: [ 0x86, 0x30, 0x40, 0x02 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "orn %g1, %g2, %g3"
+  -
+    input:
+      bytes: [ 0x86, 0x18, 0x40, 0x02 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor %g1, %g2, %g3"
+  -
+    input:
+      bytes: [ 0x86, 0x38, 0x40, 0x02 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "xnor %g1, %g2, %g3"
+  -
+    input:
+      bytes: [ 0x86, 0x50, 0x40, 0x02 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "umul %g1, %g2, %g3"
+  -
+    input:
+      bytes: [ 0x86, 0x58, 0x40, 0x02 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "smul %g1, %g2, %g3"
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "nop"
+  -
+    input:
+      bytes: [ 0x21, 0x00, 0x00, 0x0a ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sethi 10, %l0"
+  -
+    input:
+      bytes: [ 0x87, 0x28, 0x40, 0x02 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sll %g1, %g2, %g3"
+  -
+    input:
+      bytes: [ 0x87, 0x28, 0x60, 0x1f ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sll %g1, 31, %g3"
+  -
+    input:
+      bytes: [ 0x87, 0x30, 0x40, 0x02 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "srl %g1, %g2, %g3"
+  -
+    input:
+      bytes: [ 0x87, 0x30, 0x60, 0x1f ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "srl %g1, 31, %g3"
+  -
+    input:
+      bytes: [ 0x87, 0x38, 0x40, 0x02 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sra %g1, %g2, %g3"
+  -
+    input:
+      bytes: [ 0x87, 0x38, 0x60, 0x1f ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sra %g1, 31, %g3"
+  -
+    input:
+      bytes: [ 0x86, 0x20, 0x40, 0x02 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub %g1, %g2, %g3"
+  -
+    input:
+      bytes: [ 0x86, 0xa0, 0x40, 0x02 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "subcc %g1, %g2, %g3"
+  -
+    input:
+      bytes: [ 0x86, 0xe0, 0x40, 0x02 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "subxcc %g1, %g2, %g3"
+  -
+    input:
+      bytes: [ 0x86, 0x10, 0x00, 0x01 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov %g1, %g3"
+  -
+    input:
+      bytes: [ 0x86, 0x10, 0x20, 0xff ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov 0xff, %g3"
+  -
+    input:
+      bytes: [ 0x81, 0xe8, 0x00, 0x00 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "restore"
+  -
+    input:
+      bytes: [ 0x86, 0x40, 0x80, 0x01 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "addx %g2, %g1, %g3"
+  -
+    input:
+      bytes: [ 0x86, 0x60, 0x80, 0x01 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "subx %g2, %g1, %g3"
+  -
+    input:
+      bytes: [ 0x86, 0xd0, 0x80, 0x01 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "umulcc %g2, %g1, %g3"
+  -
+    input:
+      bytes: [ 0x86, 0xd8, 0x80, 0x01 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "smulcc %g2, %g1, %g3"
+  -
+    input:
+      bytes: [ 0x86, 0xf0, 0x80, 0x01 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "udivcc %g2, %g1, %g3"
+  -
+    input:
+      bytes: [ 0x86, 0xf8, 0x80, 0x01 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdivcc %g2, %g1, %g3"
+  -
+    input:
+      bytes: [ 0x86, 0x88, 0x80, 0x01 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "andcc %g2, %g1, %g3"
+  -
+    input:
+      bytes: [ 0x86, 0xa8, 0x80, 0x01 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "andncc %g2, %g1, %g3"
+  -
+    input:
+      bytes: [ 0x86, 0x90, 0x80, 0x01 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "orcc %g2, %g1, %g3"
+  -
+    input:
+      bytes: [ 0x86, 0xb0, 0x80, 0x01 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "orncc %g2, %g1, %g3"
+  -
+    input:
+      bytes: [ 0x86, 0x98, 0x80, 0x01 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "xorcc %g2, %g1, %g3"
+  -
+    input:
+      bytes: [ 0x86, 0xb8, 0x80, 0x01 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "xnorcc %g2, %g1, %g3"
+  -
+    input:
+      bytes: [ 0x87, 0x00, 0x80, 0x01 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "taddcc %g2, %g1, %g3"
+  -
+    input:
+      bytes: [ 0x87, 0x08, 0x80, 0x01 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "tsubcc %g2, %g1, %g3"
+  -
+    input:
+      bytes: [ 0x87, 0x10, 0x80, 0x01 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "taddcctv %g2, %g1, %g3"
+  -
+    input:
+      bytes: [ 0x87, 0x18, 0x80, 0x01 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "tsubcctv %g2, %g1, %g3"
diff --git a/tests/MC/Sparc/sparc-atomic-instructions.s.yaml b/tests/MC/Sparc/sparc-atomic-instructions.s.yaml
new file mode 100644
index 000000000..44a1c9721
--- /dev/null
+++ b/tests/MC/Sparc/sparc-atomic-instructions.s.yaml
@@ -0,0 +1,55 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x81, 0x43, 0xe0, 0x0f ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "membar 15"
+  -
+    input:
+      bytes: [ 0x81, 0x43, 0xc0, 0x00 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "stbar"
+  -
+    input:
+      bytes: [ 0xd4, 0x7e, 0x00, 0x16 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "swap [%i0+%l6], %o2"
+  -
+    input:
+      bytes: [ 0xd4, 0x7e, 0x20, 0x20 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "swap [%i0+32], %o2"
+  -
+    input:
+      bytes: [ 0xd5, 0xe6, 0x10, 0x16 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "cas [%i0], %l6, %o2"
+  -
+    input:
+      bytes: [ 0xd5, 0xf6, 0x10, 0x16 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "casx [%i0], %l6, %o2"
diff --git a/tests/MC/Sparc/sparc-ctrl-instructions.s.yaml b/tests/MC/Sparc/sparc-ctrl-instructions.s.yaml
new file mode 100644
index 000000000..f99104a8d
--- /dev/null
+++ b/tests/MC/Sparc/sparc-ctrl-instructions.s.yaml
@@ -0,0 +1,91 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x9f, 0xc0, 0x40, 0x1a ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "call %g1+%i2"
+  -
+    input:
+      bytes: [ 0x9f, 0xc2, 0x60, 0x08 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "call %o1+8"
+  -
+    input:
+      bytes: [ 0x9f, 0xc0, 0x60, 0x00 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "call %g1"
+  -
+    input:
+      bytes: [ 0x81, 0xc0, 0x40, 0x1a ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "jmp %g1+%i2"
+  -
+    input:
+      bytes: [ 0x81, 0xc2, 0x60, 0x08 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "jmp %o1+8"
+  -
+    input:
+      bytes: [ 0x81, 0xc0, 0x60, 0x00 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "jmp %g1"
+  -
+    input:
+      bytes: [ 0x85, 0xc0, 0x40, 0x1a ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "jmpl %g1+%i2, %g2"
+  -
+    input:
+      bytes: [ 0x85, 0xc2, 0x60, 0x08 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "jmpl %o1+8, %g2"
+  -
+    input:
+      bytes: [ 0x85, 0xc0, 0x60, 0x00 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "jmpl %g1, %g2"
+  -
+    input:
+      bytes: [ 0x81, 0xcf, 0xe0, 0x08 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "rett %i7+8"
diff --git a/tests/MC/Sparc/sparc-fp-instructions.s.yaml b/tests/MC/Sparc/sparc-fp-instructions.s.yaml
new file mode 100644
index 000000000..fbd0a2419
--- /dev/null
+++ b/tests/MC/Sparc/sparc-fp-instructions.s.yaml
@@ -0,0 +1,469 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x89, 0xa0, 0x18, 0x80 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_V9", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fitos %f0, %f4"
+  -
+    input:
+      bytes: [ 0x89, 0xa0, 0x19, 0x00 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_V9", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fitod %f0, %f4"
+  -
+    input:
+      bytes: [ 0x89, 0xa0, 0x19, 0x80 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_V9", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fitoq %f0, %f4"
+  -
+    input:
+      bytes: [ 0x89, 0xa0, 0x1a, 0x20 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_V9", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fstoi %f0, %f4"
+  -
+    input:
+      bytes: [ 0x89, 0xa0, 0x1a, 0x40 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_V9", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdtoi %f0, %f4"
+  -
+    input:
+      bytes: [ 0x89, 0xa0, 0x1a, 0x60 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_V9", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fqtoi %f0, %f4"
+  -
+    input:
+      bytes: [ 0x89, 0xa0, 0x19, 0x20 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_V9", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fstod %f0, %f4"
+  -
+    input:
+      bytes: [ 0x89, 0xa0, 0x19, 0xa0 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_V9", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fstoq %f0, %f4"
+  -
+    input:
+      bytes: [ 0x89, 0xa0, 0x18, 0xc0 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_V9", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdtos %f0, %f4"
+  -
+    input:
+      bytes: [ 0x89, 0xa0, 0x19, 0xc0 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_V9", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdtoq %f0, %f4"
+  -
+    input:
+      bytes: [ 0x89, 0xa0, 0x18, 0xe0 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_V9", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fqtos %f0, %f4"
+  -
+    input:
+      bytes: [ 0x89, 0xa0, 0x19, 0x60 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_V9", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fqtod %f0, %f4"
+  -
+    input:
+      bytes: [ 0x89, 0xa0, 0x00, 0x20 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_V9", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmovs %f0, %f4"
+  -
+    input:
+      bytes: [ 0x89, 0xa0, 0x00, 0x40 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_V9", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmovd %f0, %f4"
+  -
+    input:
+      bytes: [ 0x89, 0xa0, 0x00, 0x60 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_V9", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmovq %f0, %f4"
+  -
+    input:
+      bytes: [ 0x89, 0xa0, 0x00, 0xa0 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_V9", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fnegs %f0, %f4"
+  -
+    input:
+      bytes: [ 0x89, 0xa0, 0x00, 0xc0 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_V9", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fnegd %f0, %f4"
+  -
+    input:
+      bytes: [ 0x89, 0xa0, 0x00, 0xe0 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_V9", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fnegq %f0, %f4"
+  -
+    input:
+      bytes: [ 0x89, 0xa0, 0x01, 0x20 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_V9", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fabss %f0, %f4"
+  -
+    input:
+      bytes: [ 0x89, 0xa0, 0x01, 0x40 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_V9", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fabsd %f0, %f4"
+  -
+    input:
+      bytes: [ 0x89, 0xa0, 0x01, 0x60 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_V9", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fabsq %f0, %f4"
+  -
+    input:
+      bytes: [ 0x89, 0xa0, 0x05, 0x20 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_V9", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsqrts %f0, %f4"
+  -
+    input:
+      bytes: [ 0x89, 0xa0, 0x05, 0x40 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_V9", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsqrtd %f0, %f4"
+  -
+    input:
+      bytes: [ 0x89, 0xa0, 0x05, 0x60 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_V9", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsqrtq %f0, %f4"
+  -
+    input:
+      bytes: [ 0x91, 0xa0, 0x08, 0x24 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_V9", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fadds %f0, %f4, %f8"
+  -
+    input:
+      bytes: [ 0x91, 0xa0, 0x08, 0x44 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_V9", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "faddd %f0, %f4, %f8"
+  -
+    input:
+      bytes: [ 0x91, 0xa0, 0x08, 0x64 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_V9", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "faddq %f0, %f4, %f8"
+  -
+    input:
+      bytes: [ 0xbf, 0xa0, 0x48, 0x43 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_V9", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "faddd %f32, %f34, %f62"
+  -
+    input:
+      bytes: [ 0xbb, 0xa0, 0x48, 0x65 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_V9", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "faddq %f32, %f36, %f60"
+  -
+    input:
+      bytes: [ 0x91, 0xa0, 0x08, 0xa4 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_V9", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsubs %f0, %f4, %f8"
+  -
+    input:
+      bytes: [ 0x91, 0xa0, 0x08, 0xc4 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_V9", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsubd %f0, %f4, %f8"
+  -
+    input:
+      bytes: [ 0x91, 0xa0, 0x08, 0xe4 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_V9", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsubq %f0, %f4, %f8"
+  -
+    input:
+      bytes: [ 0x91, 0xa0, 0x09, 0x24 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_V9", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmuls %f0, %f4, %f8"
+  -
+    input:
+      bytes: [ 0x91, 0xa0, 0x09, 0x44 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_V9", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmuld %f0, %f4, %f8"
+  -
+    input:
+      bytes: [ 0x91, 0xa0, 0x09, 0x64 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_V9", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmulq %f0, %f4, %f8"
+  -
+    input:
+      bytes: [ 0x91, 0xa0, 0x0d, 0x24 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_V9", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fsmuld %f0, %f4, %f8"
+  -
+    input:
+      bytes: [ 0x91, 0xa0, 0x0d, 0xc4 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_V9", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdmulq %f0, %f4, %f8"
+  -
+    input:
+      bytes: [ 0x91, 0xa0, 0x09, 0xa4 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_V9", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdivs %f0, %f4, %f8"
+  -
+    input:
+      bytes: [ 0x91, 0xa0, 0x09, 0xc4 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_V9", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdivd %f0, %f4, %f8"
+  -
+    input:
+      bytes: [ 0x91, 0xa0, 0x09, 0xe4 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_V9", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdivq %f0, %f4, %f8"
+  -
+    input:
+      bytes: [ 0x85, 0xa8, 0x0a, 0x24 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_V9", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmps %fcc2, %f0, %f4"
+  -
+    input:
+      bytes: [ 0x85, 0xa8, 0x0a, 0x44 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_V9", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmpd %fcc2, %f0, %f4"
+  -
+    input:
+      bytes: [ 0x85, 0xa8, 0x0a, 0x64 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_V9", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmpq %fcc2, %f0, %f4"
+  -
+    input:
+      bytes: [ 0x85, 0xa8, 0x0a, 0xa4 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_V9", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmpes %fcc2, %f0, %f4"
+  -
+    input:
+      bytes: [ 0x85, 0xa8, 0x0a, 0xc4 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_V9", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmped %fcc2, %f0, %f4"
+  -
+    input:
+      bytes: [ 0x85, 0xa8, 0x0a, 0xe4 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_V9", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmpeq %fcc2, %f0, %f4"
+  -
+    input:
+      bytes: [ 0x89, 0xa0, 0x10, 0x80 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_V9", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fxtos %f0, %f4"
+  -
+    input:
+      bytes: [ 0x89, 0xa0, 0x11, 0x00 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_V9", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fxtod %f0, %f4"
+  -
+    input:
+      bytes: [ 0x89, 0xa0, 0x11, 0x80 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_V9", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fxtoq %f0, %f4"
+  -
+    input:
+      bytes: [ 0x89, 0xa0, 0x10, 0x20 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_V9", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fstox %f0, %f4"
+  -
+    input:
+      bytes: [ 0x89, 0xa0, 0x10, 0x40 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_V9", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fdtox %f0, %f4"
+  -
+    input:
+      bytes: [ 0x89, 0xa0, 0x10, 0x60 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_V9", "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fqtox %f0, %f4"
diff --git a/tests/MC/Sparc/sparc-mem-instructions.s.yaml b/tests/MC/Sparc/sparc-mem-instructions.s.yaml
new file mode 100644
index 000000000..e05445418
--- /dev/null
+++ b/tests/MC/Sparc/sparc-mem-instructions.s.yaml
@@ -0,0 +1,217 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xd4, 0x4e, 0x00, 0x16 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldsb [%i0+%l6], %o2"
+  -
+    input:
+      bytes: [ 0xd4, 0x4e, 0x20, 0x20 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldsb [%i0+32], %o2"
+  -
+    input:
+      bytes: [ 0xd8, 0x48, 0x60, 0x00 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldsb [%g1], %o4"
+  -
+    input:
+      bytes: [ 0xd4, 0x56, 0x00, 0x16 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldsh [%i0+%l6], %o2"
+  -
+    input:
+      bytes: [ 0xd4, 0x56, 0x20, 0x20 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldsh [%i0+32], %o2"
+  -
+    input:
+      bytes: [ 0xd8, 0x50, 0x60, 0x00 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldsh [%g1], %o4"
+  -
+    input:
+      bytes: [ 0xd4, 0x0e, 0x00, 0x16 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldub [%i0+%l6], %o2"
+  -
+    input:
+      bytes: [ 0xd4, 0x0e, 0x20, 0x20 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldub [%i0+32], %o2"
+  -
+    input:
+      bytes: [ 0xd4, 0x08, 0x60, 0x00 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldub [%g1], %o2"
+  -
+    input:
+      bytes: [ 0xd4, 0x16, 0x00, 0x16 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "lduh [%i0+%l6], %o2"
+  -
+    input:
+      bytes: [ 0xd4, 0x16, 0x20, 0x20 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "lduh [%i0+32], %o2"
+  -
+    input:
+      bytes: [ 0xd4, 0x10, 0x60, 0x00 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "lduh [%g1], %o2"
+  -
+    input:
+      bytes: [ 0xd4, 0x06, 0x00, 0x16 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld [%i0+%l6], %o2"
+  -
+    input:
+      bytes: [ 0xd4, 0x06, 0x20, 0x20 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld [%i0+32], %o2"
+  -
+    input:
+      bytes: [ 0xd4, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld [%g1], %o2"
+  -
+    input:
+      bytes: [ 0xd4, 0x2e, 0x00, 0x16 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "stb %o2, [%i0+%l6]"
+  -
+    input:
+      bytes: [ 0xd4, 0x2e, 0x20, 0x20 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "stb %o2, [%i0+32]"
+  -
+    input:
+      bytes: [ 0xd4, 0x28, 0x60, 0x00 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "stb %o2, [%g1]"
+  -
+    input:
+      bytes: [ 0xd4, 0x36, 0x00, 0x16 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sth %o2, [%i0+%l6]"
+  -
+    input:
+      bytes: [ 0xd4, 0x36, 0x20, 0x20 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sth %o2, [%i0+32]"
+  -
+    input:
+      bytes: [ 0xd4, 0x30, 0x60, 0x00 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sth %o2, [%g1]"
+  -
+    input:
+      bytes: [ 0xd4, 0x26, 0x00, 0x16 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "st %o2, [%i0+%l6]"
+  -
+    input:
+      bytes: [ 0xd4, 0x26, 0x20, 0x20 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "st %o2, [%i0+32]"
+  -
+    input:
+      bytes: [ 0xd4, 0x20, 0x60, 0x00 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "st %o2, [%g1]"
diff --git a/tests/MC/Sparc/sparc-vis.s.yaml b/tests/MC/Sparc/sparc-vis.s.yaml
new file mode 100644
index 000000000..617945899
--- /dev/null
+++ b/tests/MC/Sparc/sparc-vis.s.yaml
@@ -0,0 +1,10 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xbf, 0xb0, 0x0c, 0x20 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fzeros %f31"
diff --git a/tests/MC/Sparc/sparc64-alu-instructions.s.yaml b/tests/MC/Sparc/sparc64-alu-instructions.s.yaml
new file mode 100644
index 000000000..f0a107fcb
--- /dev/null
+++ b/tests/MC/Sparc/sparc64-alu-instructions.s.yaml
@@ -0,0 +1,109 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xb1, 0x28, 0x50, 0x1a ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sllx %g1, %i2, %i0"
+  -
+    input:
+      bytes: [ 0xb1, 0x28, 0x70, 0x3f ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sllx %g1, 63, %i0"
+  -
+    input:
+      bytes: [ 0xb1, 0x30, 0x50, 0x1a ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "srlx %g1, %i2, %i0"
+  -
+    input:
+      bytes: [ 0xb1, 0x30, 0x70, 0x3f ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "srlx %g1, 63, %i0"
+  -
+    input:
+      bytes: [ 0xb1, 0x38, 0x50, 0x1a ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "srax %g1, %i2, %i0"
+  -
+    input:
+      bytes: [ 0xb1, 0x38, 0x70, 0x3f ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "srax %g1, 63, %i0"
+  -
+    input:
+      bytes: [ 0xb0, 0x48, 0x40, 0x1a ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulx %g1, %i2, %i0"
+  -
+    input:
+      bytes: [ 0xb0, 0x48, 0x60, 0x3f ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulx %g1, 63, %i0"
+  -
+    input:
+      bytes: [ 0xb1, 0x68, 0x40, 0x1a ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdivx %g1, %i2, %i0"
+  -
+    input:
+      bytes: [ 0xb1, 0x68, 0x60, 0x3f ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "sdivx %g1, 63, %i0"
+  -
+    input:
+      bytes: [ 0xb0, 0x68, 0x40, 0x1a ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "udivx %g1, %i2, %i0"
+  -
+    input:
+      bytes: [ 0xb0, 0x68, 0x60, 0x3f ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "udivx %g1, 63, %i0"
diff --git a/tests/MC/Sparc/sparc64-ctrl-instructions.s.yaml b/tests/MC/Sparc/sparc64-ctrl-instructions.s.yaml
new file mode 100644
index 000000000..846de9602
--- /dev/null
+++ b/tests/MC/Sparc/sparc64-ctrl-instructions.s.yaml
@@ -0,0 +1,901 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x85, 0x66, 0x40, 0x01 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "movne %icc, %g1, %g2"
+  -
+    input:
+      bytes: [ 0x85, 0x64, 0x40, 0x01 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "move %icc, %g1, %g2"
+  -
+    input:
+      bytes: [ 0x85, 0x66, 0x80, 0x01 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "movg %icc, %g1, %g2"
+  -
+    input:
+      bytes: [ 0x85, 0x64, 0x80, 0x01 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "movle %icc, %g1, %g2"
+  -
+    input:
+      bytes: [ 0x85, 0x66, 0xc0, 0x01 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "movge %icc, %g1, %g2"
+  -
+    input:
+      bytes: [ 0x85, 0x64, 0xc0, 0x01 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "movl %icc, %g1, %g2"
+  -
+    input:
+      bytes: [ 0x85, 0x67, 0x00, 0x01 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "movgu %icc, %g1, %g2"
+  -
+    input:
+      bytes: [ 0x85, 0x65, 0x00, 0x01 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "movleu %icc, %g1, %g2"
+  -
+    input:
+      bytes: [ 0x85, 0x67, 0x40, 0x01 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "movcc %icc, %g1, %g2"
+  -
+    input:
+      bytes: [ 0x85, 0x65, 0x40, 0x01 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "movcs %icc, %g1, %g2"
+  -
+    input:
+      bytes: [ 0x85, 0x67, 0x80, 0x01 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "movpos %icc, %g1, %g2"
+  -
+    input:
+      bytes: [ 0x85, 0x65, 0x80, 0x01 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "movneg %icc, %g1, %g2"
+  -
+    input:
+      bytes: [ 0x85, 0x67, 0xc0, 0x01 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "movvc %icc, %g1, %g2"
+  -
+    input:
+      bytes: [ 0x85, 0x65, 0xc0, 0x01 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "movvs %icc, %g1, %g2"
+  -
+    input:
+      bytes: [ 0x85, 0x66, 0x50, 0x01 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "movne %xcc, %g1, %g2"
+  -
+    input:
+      bytes: [ 0x85, 0x64, 0x50, 0x01 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "move %xcc, %g1, %g2"
+  -
+    input:
+      bytes: [ 0x85, 0x66, 0x90, 0x01 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "movg %xcc, %g1, %g2"
+  -
+    input:
+      bytes: [ 0x85, 0x64, 0x90, 0x01 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "movle %xcc, %g1, %g2"
+  -
+    input:
+      bytes: [ 0x85, 0x66, 0xd0, 0x01 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "movge %xcc, %g1, %g2"
+  -
+    input:
+      bytes: [ 0x85, 0x64, 0xd0, 0x01 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "movl %xcc, %g1, %g2"
+  -
+    input:
+      bytes: [ 0x85, 0x67, 0x10, 0x01 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "movgu %xcc, %g1, %g2"
+  -
+    input:
+      bytes: [ 0x85, 0x65, 0x10, 0x01 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "movleu %xcc, %g1, %g2"
+  -
+    input:
+      bytes: [ 0x85, 0x67, 0x50, 0x01 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "movcc %xcc, %g1, %g2"
+  -
+    input:
+      bytes: [ 0x85, 0x65, 0x50, 0x01 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "movcs %xcc, %g1, %g2"
+  -
+    input:
+      bytes: [ 0x85, 0x67, 0x90, 0x01 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "movpos %xcc, %g1, %g2"
+  -
+    input:
+      bytes: [ 0x85, 0x65, 0x90, 0x01 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "movneg %xcc, %g1, %g2"
+  -
+    input:
+      bytes: [ 0x85, 0x67, 0xd0, 0x01 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "movvc %xcc, %g1, %g2"
+  -
+    input:
+      bytes: [ 0x85, 0x65, 0xd0, 0x01 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "movvs %xcc, %g1, %g2"
+  -
+    input:
+      bytes: [ 0x85, 0x61, 0xc0, 0x01 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "movu %fcc0, %g1, %g2"
+  -
+    input:
+      bytes: [ 0x85, 0x61, 0x80, 0x01 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "movg %fcc0, %g1, %g2"
+  -
+    input:
+      bytes: [ 0x85, 0x61, 0x40, 0x01 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "movug %fcc0, %g1, %g2"
+  -
+    input:
+      bytes: [ 0x85, 0x61, 0x00, 0x01 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "movl %fcc0, %g1, %g2"
+  -
+    input:
+      bytes: [ 0x85, 0x60, 0xc0, 0x01 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "movul %fcc0, %g1, %g2"
+  -
+    input:
+      bytes: [ 0x85, 0x60, 0x80, 0x01 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "movlg %fcc0, %g1, %g2"
+  -
+    input:
+      bytes: [ 0x85, 0x60, 0x40, 0x01 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "movne %fcc0, %g1, %g2"
+  -
+    input:
+      bytes: [ 0x85, 0x62, 0x40, 0x01 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "move %fcc0, %g1, %g2"
+  -
+    input:
+      bytes: [ 0x85, 0x62, 0x80, 0x01 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "movue %fcc0, %g1, %g2"
+  -
+    input:
+      bytes: [ 0x85, 0x62, 0xc0, 0x01 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "movge %fcc0, %g1, %g2"
+  -
+    input:
+      bytes: [ 0x85, 0x63, 0x00, 0x01 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "movuge %fcc0, %g1, %g2"
+  -
+    input:
+      bytes: [ 0x85, 0x63, 0x40, 0x01 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "movle %fcc0, %g1, %g2"
+  -
+    input:
+      bytes: [ 0x85, 0x63, 0x80, 0x01 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "movule %fcc0, %g1, %g2"
+  -
+    input:
+      bytes: [ 0x85, 0x63, 0xc0, 0x01 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "movo %fcc0, %g1, %g2"
+  -
+    input:
+      bytes: [ 0x85, 0xaa, 0x60, 0x21 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmovsne %icc, %f1, %f2"
+  -
+    input:
+      bytes: [ 0x85, 0xa8, 0x60, 0x21 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmovse %icc, %f1, %f2"
+  -
+    input:
+      bytes: [ 0x85, 0xaa, 0xa0, 0x21 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmovsg %icc, %f1, %f2"
+  -
+    input:
+      bytes: [ 0x85, 0xa8, 0xa0, 0x21 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmovsle %icc, %f1, %f2"
+  -
+    input:
+      bytes: [ 0x85, 0xaa, 0xe0, 0x21 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmovsge %icc, %f1, %f2"
+  -
+    input:
+      bytes: [ 0x85, 0xa8, 0xe0, 0x21 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmovsl %icc, %f1, %f2"
+  -
+    input:
+      bytes: [ 0x85, 0xab, 0x20, 0x21 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmovsgu %icc, %f1, %f2"
+  -
+    input:
+      bytes: [ 0x85, 0xa9, 0x20, 0x21 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmovsleu %icc, %f1, %f2"
+  -
+    input:
+      bytes: [ 0x85, 0xab, 0x60, 0x21 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmovscc %icc, %f1, %f2"
+  -
+    input:
+      bytes: [ 0x85, 0xa9, 0x60, 0x21 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmovscs %icc, %f1, %f2"
+  -
+    input:
+      bytes: [ 0x85, 0xab, 0xa0, 0x21 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmovspos %icc, %f1, %f2"
+  -
+    input:
+      bytes: [ 0x85, 0xa9, 0xa0, 0x21 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmovsneg %icc, %f1, %f2"
+  -
+    input:
+      bytes: [ 0x85, 0xab, 0xe0, 0x21 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmovsvc %icc, %f1, %f2"
+  -
+    input:
+      bytes: [ 0x85, 0xa9, 0xe0, 0x21 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmovsvs %icc, %f1, %f2"
+  -
+    input:
+      bytes: [ 0x85, 0xaa, 0x70, 0x21 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmovsne %xcc, %f1, %f2"
+  -
+    input:
+      bytes: [ 0x85, 0xa8, 0x70, 0x21 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmovse %xcc, %f1, %f2"
+  -
+    input:
+      bytes: [ 0x85, 0xaa, 0xb0, 0x21 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmovsg %xcc, %f1, %f2"
+  -
+    input:
+      bytes: [ 0x85, 0xa8, 0xb0, 0x21 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmovsle %xcc, %f1, %f2"
+  -
+    input:
+      bytes: [ 0x85, 0xaa, 0xf0, 0x21 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmovsge %xcc, %f1, %f2"
+  -
+    input:
+      bytes: [ 0x85, 0xa8, 0xf0, 0x21 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmovsl %xcc, %f1, %f2"
+  -
+    input:
+      bytes: [ 0x85, 0xab, 0x30, 0x21 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmovsgu %xcc, %f1, %f2"
+  -
+    input:
+      bytes: [ 0x85, 0xa9, 0x30, 0x21 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmovsleu %xcc, %f1, %f2"
+  -
+    input:
+      bytes: [ 0x85, 0xab, 0x70, 0x21 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmovscc %xcc, %f1, %f2"
+  -
+    input:
+      bytes: [ 0x85, 0xa9, 0x70, 0x21 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmovscs %xcc, %f1, %f2"
+  -
+    input:
+      bytes: [ 0x85, 0xab, 0xb0, 0x21 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmovspos %xcc, %f1, %f2"
+  -
+    input:
+      bytes: [ 0x85, 0xa9, 0xb0, 0x21 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmovsneg %xcc, %f1, %f2"
+  -
+    input:
+      bytes: [ 0x85, 0xab, 0xf0, 0x21 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmovsvc %xcc, %f1, %f2"
+  -
+    input:
+      bytes: [ 0x85, 0xa9, 0xf0, 0x21 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmovsvs %xcc, %f1, %f2"
+  -
+    input:
+      bytes: [ 0x85, 0xa9, 0xc0, 0x21 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmovsu %fcc0, %f1, %f2"
+  -
+    input:
+      bytes: [ 0x85, 0xa9, 0x80, 0x21 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmovsg %fcc0, %f1, %f2"
+  -
+    input:
+      bytes: [ 0x85, 0xa9, 0x40, 0x21 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmovsug %fcc0, %f1, %f2"
+  -
+    input:
+      bytes: [ 0x85, 0xa9, 0x00, 0x21 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmovsl %fcc0, %f1, %f2"
+  -
+    input:
+      bytes: [ 0x85, 0xa8, 0xc0, 0x21 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmovsul %fcc0, %f1, %f2"
+  -
+    input:
+      bytes: [ 0x85, 0xa8, 0x80, 0x21 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmovslg %fcc0, %f1, %f2"
+  -
+    input:
+      bytes: [ 0x85, 0xa8, 0x40, 0x21 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmovsne %fcc0, %f1, %f2"
+  -
+    input:
+      bytes: [ 0x85, 0xaa, 0x40, 0x21 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmovse %fcc0, %f1, %f2"
+  -
+    input:
+      bytes: [ 0x85, 0xaa, 0x80, 0x21 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmovsue %fcc0, %f1, %f2"
+  -
+    input:
+      bytes: [ 0x85, 0xaa, 0xc0, 0x21 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmovsge %fcc0, %f1, %f2"
+  -
+    input:
+      bytes: [ 0x85, 0xab, 0x00, 0x21 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmovsuge %fcc0, %f1, %f2"
+  -
+    input:
+      bytes: [ 0x85, 0xab, 0x40, 0x21 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmovsle %fcc0, %f1, %f2"
+  -
+    input:
+      bytes: [ 0x85, 0xab, 0x80, 0x21 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmovsule %fcc0, %f1, %f2"
+  -
+    input:
+      bytes: [ 0x85, 0xab, 0xc0, 0x21 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmovso %fcc0, %f1, %f2"
+  -
+    input:
+      bytes: [ 0x85, 0x61, 0xc8, 0x01 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "movu %fcc1, %g1, %g2"
+  -
+    input:
+      bytes: [ 0x85, 0xa9, 0x90, 0x21 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmovsg %fcc2, %f1, %f2"
+  -
+    input:
+      bytes: [ 0x87, 0x78, 0x44, 0x02 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "movrz %g1, %g2, %g3"
+  -
+    input:
+      bytes: [ 0x87, 0x78, 0x48, 0x02 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "movrlez %g1, %g2, %g3"
+  -
+    input:
+      bytes: [ 0x87, 0x78, 0x4c, 0x02 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "movrlz %g1, %g2, %g3"
+  -
+    input:
+      bytes: [ 0x87, 0x78, 0x54, 0x02 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "movrnz %g1, %g2, %g3"
+  -
+    input:
+      bytes: [ 0x87, 0x78, 0x58, 0x02 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "movrgz %g1, %g2, %g3"
+  -
+    input:
+      bytes: [ 0x87, 0x78, 0x5c, 0x02 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "movrgez %g1, %g2, %g3"
+  -
+    input:
+      bytes: [ 0x87, 0xa8, 0x44, 0xa2 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmovrsz %g1, %f2, %f3"
+  -
+    input:
+      bytes: [ 0x87, 0xa8, 0x48, 0xa2 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmovrslez %g1, %f2, %f3"
+  -
+    input:
+      bytes: [ 0x87, 0xa8, 0x4c, 0xa2 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmovrslz %g1, %f2, %f3"
+  -
+    input:
+      bytes: [ 0x87, 0xa8, 0x54, 0xa2 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmovrsnz %g1, %f2, %f3"
+  -
+    input:
+      bytes: [ 0x87, 0xa8, 0x58, 0xa2 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmovrsgz %g1, %f2, %f3"
+  -
+    input:
+      bytes: [ 0x87, 0xa8, 0x5c, 0xa2 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fmovrsgez %g1, %f2, %f3"
+  -
+    input:
+      bytes: [ 0x81, 0xcf, 0xe0, 0x08 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "rett %i7+8"
+  -
+    input:
+      bytes: [ 0x83, 0xd0, 0x30, 0x03 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "te %xcc, %g0 + 3"
diff --git a/tests/MC/Sparc/sparcv8-instructions.s.yaml b/tests/MC/Sparc/sparcv8-instructions.s.yaml
new file mode 100644
index 000000000..c233c9386
--- /dev/null
+++ b/tests/MC/Sparc/sparcv8-instructions.s.yaml
@@ -0,0 +1,55 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x81, 0xa8, 0x0a, 0x24 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmps %f0, %f4"
+  -
+    input:
+      bytes: [ 0x81, 0xa8, 0x0a, 0x44 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmpd %f0, %f4"
+  -
+    input:
+      bytes: [ 0x81, 0xa8, 0x0a, 0x64 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmpq %f0, %f4"
+  -
+    input:
+      bytes: [ 0x81, 0xa8, 0x0a, 0xa4 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmpes %f0, %f4"
+  -
+    input:
+      bytes: [ 0x81, 0xa8, 0x0a, 0xc4 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmped %f0, %f4"
+  -
+    input:
+      bytes: [ 0x81, 0xa8, 0x0a, 0xe4 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ "CS_MODE_BIG_ENDIAN" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcmpeq %f0, %f4"
diff --git a/tests/MC/SystemZ/insn-good-z196.s.yaml b/tests/MC/SystemZ/insn-good-z196.s.yaml
new file mode 100644
index 000000000..036a7344a
--- /dev/null
+++ b/tests/MC/SystemZ/insn-good-z196.s.yaml
@@ -0,0 +1,5149 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xec, 0x00, 0x80, 0x00, 0x00, 0xd9 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "aghik %r0, %r0, -32768"
+  -
+    input:
+      bytes: [ 0xec, 0x00, 0xff, 0xff, 0x00, 0xd9 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "aghik %r0, %r0, -1"
+  -
+    input:
+      bytes: [ 0xec, 0x00, 0x00, 0x00, 0x00, 0xd9 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "aghik %r0, %r0, 0"
+  -
+    input:
+      bytes: [ 0xec, 0x00, 0x00, 0x01, 0x00, 0xd9 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "aghik %r0, %r0, 1"
+  -
+    input:
+      bytes: [ 0xec, 0x00, 0x7f, 0xff, 0x00, 0xd9 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "aghik %r0, %r0, 32767"
+  -
+    input:
+      bytes: [ 0xec, 0x0f, 0x00, 0x00, 0x00, 0xd9 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "aghik %r0, %r15, 0"
+  -
+    input:
+      bytes: [ 0xec, 0xf0, 0x00, 0x00, 0x00, 0xd9 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "aghik %r15, %r0, 0"
+  -
+    input:
+      bytes: [ 0xec, 0x78, 0xff, 0xf0, 0x00, 0xd9 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "aghik %r7, %r8, -16"
+  -
+    input:
+      bytes: [ 0xb9, 0xe8, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "agrk %r0, %r0, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0xe8, 0xf0, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "agrk %r0, %r0, %r15"
+  -
+    input:
+      bytes: [ 0xb9, 0xe8, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "agrk %r0, %r15, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0xe8, 0x00, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "agrk %r15, %r0, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0xe8, 0x90, 0x78 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "agrk %r7, %r8, %r9"
+  -
+    input:
+      bytes: [ 0xec, 0x00, 0x80, 0x00, 0x00, 0xd8 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ahik %r0, %r0, -32768"
+  -
+    input:
+      bytes: [ 0xec, 0x00, 0xff, 0xff, 0x00, 0xd8 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ahik %r0, %r0, -1"
+  -
+    input:
+      bytes: [ 0xec, 0x00, 0x00, 0x00, 0x00, 0xd8 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ahik %r0, %r0, 0"
+  -
+    input:
+      bytes: [ 0xec, 0x00, 0x00, 0x01, 0x00, 0xd8 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ahik %r0, %r0, 1"
+  -
+    input:
+      bytes: [ 0xec, 0x00, 0x7f, 0xff, 0x00, 0xd8 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ahik %r0, %r0, 32767"
+  -
+    input:
+      bytes: [ 0xec, 0x0f, 0x00, 0x00, 0x00, 0xd8 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ahik %r0, %r15, 0"
+  -
+    input:
+      bytes: [ 0xec, 0xf0, 0x00, 0x00, 0x00, 0xd8 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ahik %r15, %r0, 0"
+  -
+    input:
+      bytes: [ 0xec, 0x78, 0xff, 0xf0, 0x00, 0xd8 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ahik %r7, %r8, -16"
+  -
+    input:
+      bytes: [ 0xcc, 0x08, 0x80, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "aih %r0, -2147483648"
+  -
+    input:
+      bytes: [ 0xcc, 0x08, 0xff, 0xff, 0xff, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "aih %r0, -1"
+  -
+    input:
+      bytes: [ 0xcc, 0x08, 0x00, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "aih %r0, 0"
+  -
+    input:
+      bytes: [ 0xcc, 0x08, 0x00, 0x00, 0x00, 0x01 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "aih %r0, 1"
+  -
+    input:
+      bytes: [ 0xcc, 0x08, 0x7f, 0xff, 0xff, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "aih %r0, 2147483647"
+  -
+    input:
+      bytes: [ 0xcc, 0xf8, 0x00, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "aih %r15, 0"
+  -
+    input:
+      bytes: [ 0xec, 0x00, 0x80, 0x00, 0x00, 0xdb ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "alghsik %r0, %r0, -32768"
+  -
+    input:
+      bytes: [ 0xec, 0x00, 0xff, 0xff, 0x00, 0xdb ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "alghsik %r0, %r0, -1"
+  -
+    input:
+      bytes: [ 0xec, 0x00, 0x00, 0x00, 0x00, 0xdb ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "alghsik %r0, %r0, 0"
+  -
+    input:
+      bytes: [ 0xec, 0x00, 0x00, 0x01, 0x00, 0xdb ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "alghsik %r0, %r0, 1"
+  -
+    input:
+      bytes: [ 0xec, 0x00, 0x7f, 0xff, 0x00, 0xdb ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "alghsik %r0, %r0, 32767"
+  -
+    input:
+      bytes: [ 0xec, 0x0f, 0x00, 0x00, 0x00, 0xdb ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "alghsik %r0, %r15, 0"
+  -
+    input:
+      bytes: [ 0xec, 0xf0, 0x00, 0x00, 0x00, 0xdb ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "alghsik %r15, %r0, 0"
+  -
+    input:
+      bytes: [ 0xec, 0x78, 0xff, 0xf0, 0x00, 0xdb ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "alghsik %r7, %r8, -16"
+  -
+    input:
+      bytes: [ 0xb9, 0xea, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "algrk %r0, %r0, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0xea, 0xf0, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "algrk %r0, %r0, %r15"
+  -
+    input:
+      bytes: [ 0xb9, 0xea, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "algrk %r0, %r15, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0xea, 0x00, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "algrk %r15, %r0, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0xea, 0x90, 0x78 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "algrk %r7, %r8, %r9"
+  -
+    input:
+      bytes: [ 0xec, 0x00, 0x80, 0x00, 0x00, 0xda ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "alhsik %r0, %r0, -32768"
+  -
+    input:
+      bytes: [ 0xec, 0x00, 0xff, 0xff, 0x00, 0xda ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "alhsik %r0, %r0, -1"
+  -
+    input:
+      bytes: [ 0xec, 0x00, 0x00, 0x00, 0x00, 0xda ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "alhsik %r0, %r0, 0"
+  -
+    input:
+      bytes: [ 0xec, 0x00, 0x00, 0x01, 0x00, 0xda ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "alhsik %r0, %r0, 1"
+  -
+    input:
+      bytes: [ 0xec, 0x00, 0x7f, 0xff, 0x00, 0xda ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "alhsik %r0, %r0, 32767"
+  -
+    input:
+      bytes: [ 0xec, 0x0f, 0x00, 0x00, 0x00, 0xda ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "alhsik %r0, %r15, 0"
+  -
+    input:
+      bytes: [ 0xec, 0xf0, 0x00, 0x00, 0x00, 0xda ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "alhsik %r15, %r0, 0"
+  -
+    input:
+      bytes: [ 0xec, 0x78, 0xff, 0xf0, 0x00, 0xda ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "alhsik %r7, %r8, -16"
+  -
+    input:
+      bytes: [ 0xb9, 0xfa, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "alrk %r0, %r0, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0xfa, 0xf0, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "alrk %r0, %r0, %r15"
+  -
+    input:
+      bytes: [ 0xb9, 0xfa, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "alrk %r0, %r15, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0xfa, 0x00, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "alrk %r15, %r0, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0xfa, 0x90, 0x78 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "alrk %r7, %r8, %r9"
+  -
+    input:
+      bytes: [ 0xb9, 0xf8, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ark %r0, %r0, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0xf8, 0xf0, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ark %r0, %r0, %r15"
+  -
+    input:
+      bytes: [ 0xb9, 0xf8, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ark %r0, %r15, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0xf8, 0x00, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ark %r15, %r0, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0xf8, 0x90, 0x78 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ark %r7, %r8, %r9"
+  -
+    input:
+      bytes: [ 0xb3, 0x91, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cdlfbr %f0, 0, %r0, 0"
+  -
+    input:
+      bytes: [ 0xb3, 0x91, 0x0f, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cdlfbr %f0, 0, %r0, 15"
+  -
+    input:
+      bytes: [ 0xb3, 0x91, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cdlfbr %f0, 0, %r15, 0"
+  -
+    input:
+      bytes: [ 0xb3, 0x91, 0xf0, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cdlfbr %f0, 15, %r0, 0"
+  -
+    input:
+      bytes: [ 0xb3, 0x91, 0x57, 0x46 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cdlfbr %f4, 5, %r6, 7"
+  -
+    input:
+      bytes: [ 0xb3, 0x91, 0x00, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cdlfbr %f15, 0, %r0, 0"
+  -
+    input:
+      bytes: [ 0xb3, 0xa1, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cdlgbr %f0, 0, %r0, 0"
+  -
+    input:
+      bytes: [ 0xb3, 0xa1, 0x0f, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cdlgbr %f0, 0, %r0, 15"
+  -
+    input:
+      bytes: [ 0xb3, 0xa1, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cdlgbr %f0, 0, %r15, 0"
+  -
+    input:
+      bytes: [ 0xb3, 0xa1, 0xf0, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cdlgbr %f0, 15, %r0, 0"
+  -
+    input:
+      bytes: [ 0xb3, 0xa1, 0x57, 0x46 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cdlgbr %f4, 5, %r6, 7"
+  -
+    input:
+      bytes: [ 0xb3, 0xa1, 0x00, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cdlgbr %f15, 0, %r0, 0"
+  -
+    input:
+      bytes: [ 0xb3, 0x90, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "celfbr %f0, 0, %r0, 0"
+  -
+    input:
+      bytes: [ 0xb3, 0x90, 0x0f, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "celfbr %f0, 0, %r0, 15"
+  -
+    input:
+      bytes: [ 0xb3, 0x90, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "celfbr %f0, 0, %r15, 0"
+  -
+    input:
+      bytes: [ 0xb3, 0x90, 0xf0, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "celfbr %f0, 15, %r0, 0"
+  -
+    input:
+      bytes: [ 0xb3, 0x90, 0x57, 0x46 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "celfbr %f4, 5, %r6, 7"
+  -
+    input:
+      bytes: [ 0xb3, 0x90, 0x00, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "celfbr %f15, 0, %r0, 0"
+  -
+    input:
+      bytes: [ 0xb3, 0xa0, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "celgbr %f0, 0, %r0, 0"
+  -
+    input:
+      bytes: [ 0xb3, 0xa0, 0x0f, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "celgbr %f0, 0, %r0, 15"
+  -
+    input:
+      bytes: [ 0xb3, 0xa0, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "celgbr %f0, 0, %r15, 0"
+  -
+    input:
+      bytes: [ 0xb3, 0xa0, 0xf0, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "celgbr %f0, 15, %r0, 0"
+  -
+    input:
+      bytes: [ 0xb3, 0xa0, 0x57, 0x46 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "celgbr %f4, 5, %r6, 7"
+  -
+    input:
+      bytes: [ 0xb3, 0xa0, 0x00, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "celgbr %f15, 0, %r0, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0xcd ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "chf %r0, -524288"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0xcd ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "chf %r0, -1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0xcd ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "chf %r0, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0xcd ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "chf %r0, 1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0xcd ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "chf %r0, 524287"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0xcd ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "chf %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0xcd ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "chf %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0xcd ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "chf %r0, 524287(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0xcd ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "chf %r0, 524287(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0xcd ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "chf %r15, 0"
+  -
+    input:
+      bytes: [ 0xcc, 0x0d, 0x80, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cih %r0, -2147483648"
+  -
+    input:
+      bytes: [ 0xcc, 0x0d, 0xff, 0xff, 0xff, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cih %r0, -1"
+  -
+    input:
+      bytes: [ 0xcc, 0x0d, 0x00, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cih %r0, 0"
+  -
+    input:
+      bytes: [ 0xcc, 0x0d, 0x00, 0x00, 0x00, 0x01 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cih %r0, 1"
+  -
+    input:
+      bytes: [ 0xcc, 0x0d, 0x7f, 0xff, 0xff, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cih %r0, 2147483647"
+  -
+    input:
+      bytes: [ 0xcc, 0xfd, 0x00, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cih %r15, 0"
+  -
+    input:
+      bytes: [ 0xb3, 0x9d, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clfdbr %r0, 0, %f0, 0"
+  -
+    input:
+      bytes: [ 0xb3, 0x9d, 0x0f, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clfdbr %r0, 0, %f0, 15"
+  -
+    input:
+      bytes: [ 0xb3, 0x9d, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clfdbr %r0, 0, %f15, 0"
+  -
+    input:
+      bytes: [ 0xb3, 0x9d, 0xf0, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clfdbr %r0, 15, %f0, 0"
+  -
+    input:
+      bytes: [ 0xb3, 0x9d, 0x57, 0x46 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clfdbr %r4, 5, %f6, 7"
+  -
+    input:
+      bytes: [ 0xb3, 0x9d, 0x00, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clfdbr %r15, 0, %f0, 0"
+  -
+    input:
+      bytes: [ 0xb3, 0x9c, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clfebr %r0, 0, %f0, 0"
+  -
+    input:
+      bytes: [ 0xb3, 0x9c, 0x0f, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clfebr %r0, 0, %f0, 15"
+  -
+    input:
+      bytes: [ 0xb3, 0x9c, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clfebr %r0, 0, %f15, 0"
+  -
+    input:
+      bytes: [ 0xb3, 0x9c, 0xf0, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clfebr %r0, 15, %f0, 0"
+  -
+    input:
+      bytes: [ 0xb3, 0x9c, 0x57, 0x46 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clfebr %r4, 5, %f6, 7"
+  -
+    input:
+      bytes: [ 0xb3, 0x9c, 0x00, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clfebr %r15, 0, %f0, 0"
+  -
+    input:
+      bytes: [ 0xb3, 0x9e, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clfxbr %r0, 0, %f0, 0"
+  -
+    input:
+      bytes: [ 0xb3, 0x9e, 0x0f, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clfxbr %r0, 0, %f0, 15"
+  -
+    input:
+      bytes: [ 0xb3, 0x9e, 0x00, 0x0d ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clfxbr %r0, 0, %f13, 0"
+  -
+    input:
+      bytes: [ 0xb3, 0x9e, 0xf0, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clfxbr %r0, 15, %f0, 0"
+  -
+    input:
+      bytes: [ 0xb3, 0x9e, 0x59, 0x78 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clfxbr %r7, 5, %f8, 9"
+  -
+    input:
+      bytes: [ 0xb3, 0x9e, 0x00, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clfxbr %r15, 0, %f0, 0"
+  -
+    input:
+      bytes: [ 0xb3, 0xad, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clgdbr %r0, 0, %f0, 0"
+  -
+    input:
+      bytes: [ 0xb3, 0xad, 0x0f, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clgdbr %r0, 0, %f0, 15"
+  -
+    input:
+      bytes: [ 0xb3, 0xad, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clgdbr %r0, 0, %f15, 0"
+  -
+    input:
+      bytes: [ 0xb3, 0xad, 0xf0, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clgdbr %r0, 15, %f0, 0"
+  -
+    input:
+      bytes: [ 0xb3, 0xad, 0x57, 0x46 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clgdbr %r4, 5, %f6, 7"
+  -
+    input:
+      bytes: [ 0xb3, 0xad, 0x00, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clgdbr %r15, 0, %f0, 0"
+  -
+    input:
+      bytes: [ 0xb3, 0xac, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clgebr %r0, 0, %f0, 0"
+  -
+    input:
+      bytes: [ 0xb3, 0xac, 0x0f, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clgebr %r0, 0, %f0, 15"
+  -
+    input:
+      bytes: [ 0xb3, 0xac, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clgebr %r0, 0, %f15, 0"
+  -
+    input:
+      bytes: [ 0xb3, 0xac, 0xf0, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clgebr %r0, 15, %f0, 0"
+  -
+    input:
+      bytes: [ 0xb3, 0xac, 0x57, 0x46 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clgebr %r4, 5, %f6, 7"
+  -
+    input:
+      bytes: [ 0xb3, 0xac, 0x00, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clgebr %r15, 0, %f0, 0"
+  -
+    input:
+      bytes: [ 0xb3, 0xae, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clgxbr %r0, 0, %f0, 0"
+  -
+    input:
+      bytes: [ 0xb3, 0xae, 0x0f, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clgxbr %r0, 0, %f0, 15"
+  -
+    input:
+      bytes: [ 0xb3, 0xae, 0x00, 0x0d ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clgxbr %r0, 0, %f13, 0"
+  -
+    input:
+      bytes: [ 0xb3, 0xae, 0xf0, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clgxbr %r0, 15, %f0, 0"
+  -
+    input:
+      bytes: [ 0xb3, 0xae, 0x59, 0x78 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clgxbr %r7, 5, %f8, 9"
+  -
+    input:
+      bytes: [ 0xb3, 0xae, 0x00, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clgxbr %r15, 0, %f0, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0xcf ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clhf %r0, -524288"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0xcf ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clhf %r0, -1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0xcf ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clhf %r0, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0xcf ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clhf %r0, 1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0xcf ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clhf %r0, 524287"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0xcf ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clhf %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0xcf ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clhf %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0xcf ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clhf %r0, 524287(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0xcf ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clhf %r0, 524287(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0xcf ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clhf %r15, 0"
+  -
+    input:
+      bytes: [ 0xcc, 0x0f, 0x00, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clih %r0, 0"
+  -
+    input:
+      bytes: [ 0xcc, 0x0f, 0x00, 0x00, 0x00, 0x01 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clih %r0, 1"
+  -
+    input:
+      bytes: [ 0xcc, 0x0f, 0xff, 0xff, 0xff, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clih %r0, 4294967295"
+  -
+    input:
+      bytes: [ 0xcc, 0xff, 0x00, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clih %r15, 0"
+  -
+    input:
+      bytes: [ 0xb3, 0x92, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cxlfbr %f0, 0, %r0, 0"
+  -
+    input:
+      bytes: [ 0xb3, 0x92, 0x0f, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cxlfbr %f0, 0, %r0, 15"
+  -
+    input:
+      bytes: [ 0xb3, 0x92, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cxlfbr %f0, 0, %r15, 0"
+  -
+    input:
+      bytes: [ 0xb3, 0x92, 0xf0, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cxlfbr %f0, 15, %r0, 0"
+  -
+    input:
+      bytes: [ 0xb3, 0x92, 0x5a, 0x49 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cxlfbr %f4, 5, %r9, 10"
+  -
+    input:
+      bytes: [ 0xb3, 0x92, 0x00, 0xd0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cxlfbr %f13, 0, %r0, 0"
+  -
+    input:
+      bytes: [ 0xb3, 0xa2, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cxlgbr %f0, 0, %r0, 0"
+  -
+    input:
+      bytes: [ 0xb3, 0xa2, 0x0f, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cxlgbr %f0, 0, %r0, 15"
+  -
+    input:
+      bytes: [ 0xb3, 0xa2, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cxlgbr %f0, 0, %r15, 0"
+  -
+    input:
+      bytes: [ 0xb3, 0xa2, 0xf0, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cxlgbr %f0, 15, %r0, 0"
+  -
+    input:
+      bytes: [ 0xb3, 0xa2, 0x5a, 0x49 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cxlgbr %f4, 5, %r9, 10"
+  -
+    input:
+      bytes: [ 0xb3, 0xa2, 0x00, 0xd0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cxlgbr %f13, 0, %r0, 0"
+  -
+    input:
+      bytes: [ 0xb3, 0x5f, 0x0f, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "fidbra %f0, 0, %f0, 15"
+  -
+    input:
+      bytes: [ 0xb3, 0x5f, 0x57, 0x46 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "fidbra %f4, 5, %f6, 7"
+  -
+    input:
+      bytes: [ 0xb3, 0x57, 0x0f, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "fiebra %f0, 0, %f0, 15"
+  -
+    input:
+      bytes: [ 0xb3, 0x57, 0x57, 0x46 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "fiebra %f4, 5, %f6, 7"
+  -
+    input:
+      bytes: [ 0xb3, 0x47, 0x0f, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "fixbra %f0, 0, %f0, 15"
+  -
+    input:
+      bytes: [ 0xb3, 0x47, 0x59, 0x48 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "fixbra %f4, 5, %f8, 9"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0xf8 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "laa %r0, %r0, -524288"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0xf8 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "laa %r0, %r0, -1"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0xf8 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "laa %r0, %r0, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0xf8 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "laa %r0, %r0, 1"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0xf8 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "laa %r0, %r0, 524287"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0xf8 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "laa %r0, %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0xf8 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "laa %r0, %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x1f, 0xff, 0x7f, 0xf8 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "laa %r0, %r0, 524287(%r1)"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0xff, 0xff, 0x7f, 0xf8 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "laa %r0, %r0, 524287(%r15)"
+  -
+    input:
+      bytes: [ 0xeb, 0x0f, 0x00, 0x00, 0x00, 0xf8 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "laa %r0, %r15, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0xf0, 0x00, 0x00, 0x00, 0xf8 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "laa %r15, %r0, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0xe8 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "laag %r0, %r0, -524288"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0xe8 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "laag %r0, %r0, -1"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0xe8 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "laag %r0, %r0, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0xe8 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "laag %r0, %r0, 1"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0xe8 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "laag %r0, %r0, 524287"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0xe8 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "laag %r0, %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0xe8 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "laag %r0, %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x1f, 0xff, 0x7f, 0xe8 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "laag %r0, %r0, 524287(%r1)"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0xff, 0xff, 0x7f, 0xe8 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "laag %r0, %r0, 524287(%r15)"
+  -
+    input:
+      bytes: [ 0xeb, 0x0f, 0x00, 0x00, 0x00, 0xe8 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "laag %r0, %r15, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0xf0, 0x00, 0x00, 0x00, 0xe8 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "laag %r15, %r0, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0xfa ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "laal %r0, %r0, -524288"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0xfa ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "laal %r0, %r0, -1"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0xfa ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "laal %r0, %r0, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0xfa ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "laal %r0, %r0, 1"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0xfa ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "laal %r0, %r0, 524287"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0xfa ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "laal %r0, %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0xfa ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "laal %r0, %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x1f, 0xff, 0x7f, 0xfa ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "laal %r0, %r0, 524287(%r1)"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0xff, 0xff, 0x7f, 0xfa ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "laal %r0, %r0, 524287(%r15)"
+  -
+    input:
+      bytes: [ 0xeb, 0x0f, 0x00, 0x00, 0x00, 0xfa ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "laal %r0, %r15, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0xf0, 0x00, 0x00, 0x00, 0xfa ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "laal %r15, %r0, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0xea ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "laalg %r0, %r0, -524288"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0xea ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "laalg %r0, %r0, -1"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0xea ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "laalg %r0, %r0, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0xea ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "laalg %r0, %r0, 1"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0xea ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "laalg %r0, %r0, 524287"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0xea ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "laalg %r0, %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0xea ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "laalg %r0, %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x1f, 0xff, 0x7f, 0xea ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "laalg %r0, %r0, 524287(%r1)"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0xff, 0xff, 0x7f, 0xea ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "laalg %r0, %r0, 524287(%r15)"
+  -
+    input:
+      bytes: [ 0xeb, 0x0f, 0x00, 0x00, 0x00, 0xea ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "laalg %r0, %r15, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0xf0, 0x00, 0x00, 0x00, 0xea ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "laalg %r15, %r0, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0xf4 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lan %r0, %r0, -524288"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0xf4 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lan %r0, %r0, -1"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0xf4 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lan %r0, %r0, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0xf4 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lan %r0, %r0, 1"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0xf4 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lan %r0, %r0, 524287"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0xf4 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lan %r0, %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0xf4 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lan %r0, %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x1f, 0xff, 0x7f, 0xf4 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lan %r0, %r0, 524287(%r1)"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0xff, 0xff, 0x7f, 0xf4 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lan %r0, %r0, 524287(%r15)"
+  -
+    input:
+      bytes: [ 0xeb, 0x0f, 0x00, 0x00, 0x00, 0xf4 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lan %r0, %r15, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0xf0, 0x00, 0x00, 0x00, 0xf4 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lan %r15, %r0, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0xe4 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lang %r0, %r0, -524288"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0xe4 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lang %r0, %r0, -1"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0xe4 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lang %r0, %r0, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0xe4 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lang %r0, %r0, 1"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0xe4 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lang %r0, %r0, 524287"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0xe4 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lang %r0, %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0xe4 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lang %r0, %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x1f, 0xff, 0x7f, 0xe4 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lang %r0, %r0, 524287(%r1)"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0xff, 0xff, 0x7f, 0xe4 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lang %r0, %r0, 524287(%r15)"
+  -
+    input:
+      bytes: [ 0xeb, 0x0f, 0x00, 0x00, 0x00, 0xe4 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lang %r0, %r15, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0xf0, 0x00, 0x00, 0x00, 0xe4 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lang %r15, %r0, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0xf6 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lao %r0, %r0, -524288"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0xf6 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lao %r0, %r0, -1"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0xf6 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lao %r0, %r0, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0xf6 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lao %r0, %r0, 1"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0xf6 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lao %r0, %r0, 524287"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0xf6 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lao %r0, %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0xf6 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lao %r0, %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x1f, 0xff, 0x7f, 0xf6 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lao %r0, %r0, 524287(%r1)"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0xff, 0xff, 0x7f, 0xf6 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lao %r0, %r0, 524287(%r15)"
+  -
+    input:
+      bytes: [ 0xeb, 0x0f, 0x00, 0x00, 0x00, 0xf6 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lao %r0, %r15, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0xf0, 0x00, 0x00, 0x00, 0xf6 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lao %r15, %r0, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0xe6 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "laog %r0, %r0, -524288"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0xe6 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "laog %r0, %r0, -1"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0xe6 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "laog %r0, %r0, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0xe6 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "laog %r0, %r0, 1"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0xe6 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "laog %r0, %r0, 524287"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0xe6 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "laog %r0, %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0xe6 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "laog %r0, %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x1f, 0xff, 0x7f, 0xe6 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "laog %r0, %r0, 524287(%r1)"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0xff, 0xff, 0x7f, 0xe6 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "laog %r0, %r0, 524287(%r15)"
+  -
+    input:
+      bytes: [ 0xeb, 0x0f, 0x00, 0x00, 0x00, 0xe6 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "laog %r0, %r15, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0xf0, 0x00, 0x00, 0x00, 0xe6 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "laog %r15, %r0, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0xf7 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lax %r0, %r0, -524288"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0xf7 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lax %r0, %r0, -1"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0xf7 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lax %r0, %r0, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0xf7 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lax %r0, %r0, 1"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0xf7 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lax %r0, %r0, 524287"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0xf7 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lax %r0, %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0xf7 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lax %r0, %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x1f, 0xff, 0x7f, 0xf7 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lax %r0, %r0, 524287(%r1)"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0xff, 0xff, 0x7f, 0xf7 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lax %r0, %r0, 524287(%r15)"
+  -
+    input:
+      bytes: [ 0xeb, 0x0f, 0x00, 0x00, 0x00, 0xf7 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lax %r0, %r15, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0xf0, 0x00, 0x00, 0x00, 0xf7 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lax %r15, %r0, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0xe7 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "laxg %r0, %r0, -524288"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0xe7 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "laxg %r0, %r0, -1"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0xe7 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "laxg %r0, %r0, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0xe7 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "laxg %r0, %r0, 1"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0xe7 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "laxg %r0, %r0, 524287"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0xe7 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "laxg %r0, %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0xe7 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "laxg %r0, %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x1f, 0xff, 0x7f, 0xe7 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "laxg %r0, %r0, 524287(%r1)"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0xff, 0xff, 0x7f, 0xe7 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "laxg %r0, %r0, 524287(%r15)"
+  -
+    input:
+      bytes: [ 0xeb, 0x0f, 0x00, 0x00, 0x00, 0xe7 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "laxg %r0, %r15, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0xf0, 0x00, 0x00, 0x00, 0xe7 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "laxg %r15, %r0, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0xc0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lbh %r0, -524288"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0xc0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lbh %r0, -1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0xc0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lbh %r0, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0xc0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lbh %r0, 1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0xc0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lbh %r0, 524287"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0xc0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lbh %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0xc0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lbh %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0xc0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lbh %r0, 524287(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0xc0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lbh %r0, 524287(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0xc0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lbh %r15, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0xca ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lfh %r0, -524288"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0xca ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lfh %r0, -1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0xca ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lfh %r0, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0xca ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lfh %r0, 1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0xca ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lfh %r0, 524287"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0xca ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lfh %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0xca ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lfh %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0xca ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lfh %r0, 524287(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0xca ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lfh %r0, 524287(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0xca ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lfh %r15, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0xc4 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lhh %r0, -524288"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0xc4 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lhh %r0, -1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0xc4 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lhh %r0, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0xc4 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lhh %r0, 1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0xc4 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lhh %r0, 524287"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0xc4 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lhh %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0xc4 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lhh %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0xc4 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lhh %r0, 524287(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0xc4 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lhh %r0, 524287(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0xc4 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lhh %r15, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0xc2 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "llch %r0, -524288"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0xc2 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "llch %r0, -1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0xc2 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "llch %r0, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0xc2 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "llch %r0, 1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0xc2 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "llch %r0, 524287"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0xc2 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "llch %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0xc2 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "llch %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0xc2 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "llch %r0, 524287(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0xc2 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "llch %r0, 524287(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0xc2 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "llch %r15, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0xc6 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "llhh %r0, -524288"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0xc6 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "llhh %r0, -1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0xc6 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "llhh %r0, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0xc6 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "llhh %r0, 1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0xc6 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "llhh %r0, 524287"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0xc6 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "llhh %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0xc6 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "llhh %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0xc6 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "llhh %r0, 524287(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0xc6 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "llhh %r0, 524287(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0xc6 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "llhh %r15, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0xf2 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "loc %r0, 0, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0x0f, 0x00, 0x00, 0x00, 0xf2 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "loc %r0, 0, 15"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0xf2 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "loc %r0, -524288, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0xf2 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "loc %r0, 524287, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0xf2 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "loc %r0, 0(%r1), 0"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0xf2 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "loc %r0, 0(%r15), 0"
+  -
+    input:
+      bytes: [ 0xeb, 0xf0, 0x00, 0x00, 0x00, 0xf2 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "loc %r15, 0, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0x11, 0x30, 0x02, 0x00, 0xf2 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "loco %r1, 2(%r3)"
+  -
+    input:
+      bytes: [ 0xeb, 0x12, 0x30, 0x02, 0x00, 0xf2 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "loch %r1, 2(%r3)"
+  -
+    input:
+      bytes: [ 0xeb, 0x13, 0x30, 0x02, 0x00, 0xf2 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "locnle %r1, 2(%r3)"
+  -
+    input:
+      bytes: [ 0xeb, 0x14, 0x30, 0x02, 0x00, 0xf2 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "locl %r1, 2(%r3)"
+  -
+    input:
+      bytes: [ 0xeb, 0x15, 0x30, 0x02, 0x00, 0xf2 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "locnhe %r1, 2(%r3)"
+  -
+    input:
+      bytes: [ 0xeb, 0x16, 0x30, 0x02, 0x00, 0xf2 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "loclh %r1, 2(%r3)"
+  -
+    input:
+      bytes: [ 0xeb, 0x17, 0x30, 0x02, 0x00, 0xf2 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "locne %r1, 2(%r3)"
+  -
+    input:
+      bytes: [ 0xeb, 0x18, 0x30, 0x02, 0x00, 0xf2 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "loce %r1, 2(%r3)"
+  -
+    input:
+      bytes: [ 0xeb, 0x19, 0x30, 0x02, 0x00, 0xf2 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "locnlh %r1, 2(%r3)"
+  -
+    input:
+      bytes: [ 0xeb, 0x1a, 0x30, 0x02, 0x00, 0xf2 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "loche %r1, 2(%r3)"
+  -
+    input:
+      bytes: [ 0xeb, 0x1b, 0x30, 0x02, 0x00, 0xf2 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "locnl %r1, 2(%r3)"
+  -
+    input:
+      bytes: [ 0xeb, 0x1c, 0x30, 0x02, 0x00, 0xf2 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "locle %r1, 2(%r3)"
+  -
+    input:
+      bytes: [ 0xeb, 0x1d, 0x30, 0x02, 0x00, 0xf2 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "locnh %r1, 2(%r3)"
+  -
+    input:
+      bytes: [ 0xeb, 0x1e, 0x30, 0x02, 0x00, 0xf2 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "locno %r1, 2(%r3)"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0xe2 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "locg %r0, 0, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0x0f, 0x00, 0x00, 0x00, 0xe2 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "locg %r0, 0, 15"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0xe2 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "locg %r0, -524288, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0xe2 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "locg %r0, 524287, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0xe2 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "locg %r0, 0(%r1), 0"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0xe2 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "locg %r0, 0(%r15), 0"
+  -
+    input:
+      bytes: [ 0xeb, 0xf0, 0x00, 0x00, 0x00, 0xe2 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "locg %r15, 0, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0x11, 0x30, 0x02, 0x00, 0xe2 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "locgo %r1, 2(%r3)"
+  -
+    input:
+      bytes: [ 0xeb, 0x12, 0x30, 0x02, 0x00, 0xe2 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "locgh %r1, 2(%r3)"
+  -
+    input:
+      bytes: [ 0xeb, 0x13, 0x30, 0x02, 0x00, 0xe2 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "locgnle %r1, 2(%r3)"
+  -
+    input:
+      bytes: [ 0xeb, 0x14, 0x30, 0x02, 0x00, 0xe2 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "locgl %r1, 2(%r3)"
+  -
+    input:
+      bytes: [ 0xeb, 0x15, 0x30, 0x02, 0x00, 0xe2 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "locgnhe %r1, 2(%r3)"
+  -
+    input:
+      bytes: [ 0xeb, 0x16, 0x30, 0x02, 0x00, 0xe2 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "locglh %r1, 2(%r3)"
+  -
+    input:
+      bytes: [ 0xeb, 0x17, 0x30, 0x02, 0x00, 0xe2 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "locgne %r1, 2(%r3)"
+  -
+    input:
+      bytes: [ 0xeb, 0x18, 0x30, 0x02, 0x00, 0xe2 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "locge %r1, 2(%r3)"
+  -
+    input:
+      bytes: [ 0xeb, 0x19, 0x30, 0x02, 0x00, 0xe2 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "locgnlh %r1, 2(%r3)"
+  -
+    input:
+      bytes: [ 0xeb, 0x1a, 0x30, 0x02, 0x00, 0xe2 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "locghe %r1, 2(%r3)"
+  -
+    input:
+      bytes: [ 0xeb, 0x1b, 0x30, 0x02, 0x00, 0xe2 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "locgnl %r1, 2(%r3)"
+  -
+    input:
+      bytes: [ 0xeb, 0x1c, 0x30, 0x02, 0x00, 0xe2 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "locgle %r1, 2(%r3)"
+  -
+    input:
+      bytes: [ 0xeb, 0x1d, 0x30, 0x02, 0x00, 0xe2 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "locgnh %r1, 2(%r3)"
+  -
+    input:
+      bytes: [ 0xeb, 0x1e, 0x30, 0x02, 0x00, 0xe2 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "locgno %r1, 2(%r3)"
+  -
+    input:
+      bytes: [ 0xb9, 0xe2, 0x00, 0x12 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "locgr %r1, %r2, 0"
+  -
+    input:
+      bytes: [ 0xb9, 0xe2, 0xf0, 0x12 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "locgr %r1, %r2, 15"
+  -
+    input:
+      bytes: [ 0xb9, 0xe2, 0x10, 0x13 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "locgro %r1, %r3"
+  -
+    input:
+      bytes: [ 0xb9, 0xe2, 0x20, 0x13 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "locgrh %r1, %r3"
+  -
+    input:
+      bytes: [ 0xb9, 0xe2, 0x30, 0x13 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "locgrnle %r1, %r3"
+  -
+    input:
+      bytes: [ 0xb9, 0xe2, 0x40, 0x13 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "locgrl %r1, %r3"
+  -
+    input:
+      bytes: [ 0xb9, 0xe2, 0x50, 0x13 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "locgrnhe %r1, %r3"
+  -
+    input:
+      bytes: [ 0xb9, 0xe2, 0x60, 0x13 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "locgrlh %r1, %r3"
+  -
+    input:
+      bytes: [ 0xb9, 0xe2, 0x70, 0x13 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "locgrne %r1, %r3"
+  -
+    input:
+      bytes: [ 0xb9, 0xe2, 0x80, 0x13 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "locgre %r1, %r3"
+  -
+    input:
+      bytes: [ 0xb9, 0xe2, 0x90, 0x13 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "locgrnlh %r1, %r3"
+  -
+    input:
+      bytes: [ 0xb9, 0xe2, 0xa0, 0x13 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "locgrhe %r1, %r3"
+  -
+    input:
+      bytes: [ 0xb9, 0xe2, 0xb0, 0x13 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "locgrnl %r1, %r3"
+  -
+    input:
+      bytes: [ 0xb9, 0xe2, 0xc0, 0x13 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "locgrle %r1, %r3"
+  -
+    input:
+      bytes: [ 0xb9, 0xe2, 0xd0, 0x13 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "locgrnh %r1, %r3"
+  -
+    input:
+      bytes: [ 0xb9, 0xe2, 0xe0, 0x13 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "locgrno %r1, %r3"
+  -
+    input:
+      bytes: [ 0xb9, 0xf2, 0x00, 0x12 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "locr %r1, %r2, 0"
+  -
+    input:
+      bytes: [ 0xb9, 0xf2, 0xf0, 0x12 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "locr %r1, %r2, 15"
+  -
+    input:
+      bytes: [ 0xb9, 0xf2, 0x10, 0x13 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "locro %r1, %r3"
+  -
+    input:
+      bytes: [ 0xb9, 0xf2, 0x20, 0x13 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "locrh %r1, %r3"
+  -
+    input:
+      bytes: [ 0xb9, 0xf2, 0x30, 0x13 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "locrnle %r1, %r3"
+  -
+    input:
+      bytes: [ 0xb9, 0xf2, 0x40, 0x13 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "locrl %r1, %r3"
+  -
+    input:
+      bytes: [ 0xb9, 0xf2, 0x50, 0x13 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "locrnhe %r1, %r3"
+  -
+    input:
+      bytes: [ 0xb9, 0xf2, 0x60, 0x13 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "locrlh %r1, %r3"
+  -
+    input:
+      bytes: [ 0xb9, 0xf2, 0x70, 0x13 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "locrne %r1, %r3"
+  -
+    input:
+      bytes: [ 0xb9, 0xf2, 0x80, 0x13 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "locre %r1, %r3"
+  -
+    input:
+      bytes: [ 0xb9, 0xf2, 0x90, 0x13 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "locrnlh %r1, %r3"
+  -
+    input:
+      bytes: [ 0xb9, 0xf2, 0xa0, 0x13 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "locrhe %r1, %r3"
+  -
+    input:
+      bytes: [ 0xb9, 0xf2, 0xb0, 0x13 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "locrnl %r1, %r3"
+  -
+    input:
+      bytes: [ 0xb9, 0xf2, 0xc0, 0x13 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "locrle %r1, %r3"
+  -
+    input:
+      bytes: [ 0xb9, 0xf2, 0xd0, 0x13 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "locrnh %r1, %r3"
+  -
+    input:
+      bytes: [ 0xb9, 0xf2, 0xe0, 0x13 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "locrno %r1, %r3"
+  -
+    input:
+      bytes: [ 0xb9, 0xe4, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ngrk %r0, %r0, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0xe4, 0xf0, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ngrk %r0, %r0, %r15"
+  -
+    input:
+      bytes: [ 0xb9, 0xe4, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ngrk %r0, %r15, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0xe4, 0x00, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ngrk %r15, %r0, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0xe4, 0x90, 0x78 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ngrk %r7, %r8, %r9"
+  -
+    input:
+      bytes: [ 0xb9, 0xf4, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "nrk %r0, %r0, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0xf4, 0xf0, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "nrk %r0, %r0, %r15"
+  -
+    input:
+      bytes: [ 0xb9, 0xf4, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "nrk %r0, %r15, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0xf4, 0x00, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "nrk %r15, %r0, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0xf4, 0x90, 0x78 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "nrk %r7, %r8, %r9"
+  -
+    input:
+      bytes: [ 0xb9, 0xe6, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ogrk %r0, %r0, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0xe6, 0xf0, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ogrk %r0, %r0, %r15"
+  -
+    input:
+      bytes: [ 0xb9, 0xe6, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ogrk %r0, %r15, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0xe6, 0x00, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ogrk %r15, %r0, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0xe6, 0x90, 0x78 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ogrk %r7, %r8, %r9"
+  -
+    input:
+      bytes: [ 0xb9, 0xf6, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ork %r0, %r0, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0xf6, 0xf0, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ork %r0, %r0, %r15"
+  -
+    input:
+      bytes: [ 0xb9, 0xf6, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ork %r0, %r15, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0xf6, 0x00, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ork %r15, %r0, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0xf6, 0x90, 0x78 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ork %r7, %r8, %r9"
+  -
+    input:
+      bytes: [ 0xec, 0x00, 0x00, 0x00, 0x00, 0x5d ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "risbhg %r0, %r0, 0, 0, 0"
+  -
+    input:
+      bytes: [ 0xec, 0x00, 0x00, 0x00, 0x3f, 0x5d ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "risbhg %r0, %r0, 0, 0, 63"
+  -
+    input:
+      bytes: [ 0xec, 0x00, 0x00, 0xff, 0x00, 0x5d ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "risbhg %r0, %r0, 0, 255, 0"
+  -
+    input:
+      bytes: [ 0xec, 0x00, 0xff, 0x00, 0x00, 0x5d ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "risbhg %r0, %r0, 255, 0, 0"
+  -
+    input:
+      bytes: [ 0xec, 0x0f, 0x00, 0x00, 0x00, 0x5d ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "risbhg %r0, %r15, 0, 0, 0"
+  -
+    input:
+      bytes: [ 0xec, 0xf0, 0x00, 0x00, 0x00, 0x5d ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "risbhg %r15, %r0, 0, 0, 0"
+  -
+    input:
+      bytes: [ 0xec, 0x45, 0x06, 0x07, 0x08, 0x5d ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "risbhg %r4, %r5, 6, 7, 8"
+  -
+    input:
+      bytes: [ 0xec, 0x00, 0x00, 0x00, 0x00, 0x51 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "risblg %r0, %r0, 0, 0, 0"
+  -
+    input:
+      bytes: [ 0xec, 0x00, 0x00, 0x00, 0x3f, 0x51 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "risblg %r0, %r0, 0, 0, 63"
+  -
+    input:
+      bytes: [ 0xec, 0x00, 0x00, 0xff, 0x00, 0x51 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "risblg %r0, %r0, 0, 255, 0"
+  -
+    input:
+      bytes: [ 0xec, 0x00, 0xff, 0x00, 0x00, 0x51 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "risblg %r0, %r0, 255, 0, 0"
+  -
+    input:
+      bytes: [ 0xec, 0x0f, 0x00, 0x00, 0x00, 0x51 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "risblg %r0, %r15, 0, 0, 0"
+  -
+    input:
+      bytes: [ 0xec, 0xf0, 0x00, 0x00, 0x00, 0x51 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "risblg %r15, %r0, 0, 0, 0"
+  -
+    input:
+      bytes: [ 0xec, 0x45, 0x06, 0x07, 0x08, 0x51 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "risblg %r4, %r5, 6, 7, 8"
+  -
+    input:
+      bytes: [ 0xb9, 0xe9, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sgrk %r0, %r0, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0xe9, 0xf0, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sgrk %r0, %r0, %r15"
+  -
+    input:
+      bytes: [ 0xb9, 0xe9, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sgrk %r0, %r15, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0xe9, 0x00, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sgrk %r15, %r0, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0xe9, 0x90, 0x78 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sgrk %r7, %r8, %r9"
+  -
+    input:
+      bytes: [ 0xb9, 0xeb, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "slgrk %r0, %r0, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0xeb, 0xf0, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "slgrk %r0, %r0, %r15"
+  -
+    input:
+      bytes: [ 0xb9, 0xeb, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "slgrk %r0, %r15, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0xeb, 0x00, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "slgrk %r15, %r0, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0xeb, 0x90, 0x78 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "slgrk %r7, %r8, %r9"
+  -
+    input:
+      bytes: [ 0xb9, 0xfb, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "slrk %r0, %r0, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0xfb, 0xf0, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "slrk %r0, %r0, %r15"
+  -
+    input:
+      bytes: [ 0xb9, 0xfb, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "slrk %r0, %r15, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0xfb, 0x00, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "slrk %r15, %r0, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0xfb, 0x90, 0x78 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "slrk %r7, %r8, %r9"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0xdf ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sllk %r0, %r0, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0xf1, 0x00, 0x00, 0x00, 0xdf ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sllk %r15, %r1, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0x1f, 0x00, 0x00, 0x00, 0xdf ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sllk %r1, %r15, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0xff, 0x00, 0x00, 0x00, 0xdf ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sllk %r15, %r15, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0xdf ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sllk %r0, %r0, -524288"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0xdf ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sllk %r0, %r0, -1"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0xdf ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sllk %r0, %r0, 1"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0xdf ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sllk %r0, %r0, 524287"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0xdf ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sllk %r0, %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0xdf ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sllk %r0, %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x1f, 0xff, 0x7f, 0xdf ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sllk %r0, %r0, 524287(%r1)"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0xff, 0xff, 0x7f, 0xdf ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sllk %r0, %r0, 524287(%r15)"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0xdc ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "srak %r0, %r0, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0xf1, 0x00, 0x00, 0x00, 0xdc ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "srak %r15, %r1, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0x1f, 0x00, 0x00, 0x00, 0xdc ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "srak %r1, %r15, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0xff, 0x00, 0x00, 0x00, 0xdc ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "srak %r15, %r15, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0xdc ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "srak %r0, %r0, -524288"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0xdc ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "srak %r0, %r0, -1"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0xdc ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "srak %r0, %r0, 1"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0xdc ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "srak %r0, %r0, 524287"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0xdc ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "srak %r0, %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0xdc ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "srak %r0, %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x1f, 0xff, 0x7f, 0xdc ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "srak %r0, %r0, 524287(%r1)"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0xff, 0xff, 0x7f, 0xdc ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "srak %r0, %r0, 524287(%r15)"
+  -
+    input:
+      bytes: [ 0xb9, 0xf9, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "srk %r0, %r0, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0xf9, 0xf0, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "srk %r0, %r0, %r15"
+  -
+    input:
+      bytes: [ 0xb9, 0xf9, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "srk %r0, %r15, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0xf9, 0x00, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "srk %r15, %r0, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0xf9, 0x90, 0x78 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "srk %r7, %r8, %r9"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0xde ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "srlk %r0, %r0, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0xf1, 0x00, 0x00, 0x00, 0xde ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "srlk %r15, %r1, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0x1f, 0x00, 0x00, 0x00, 0xde ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "srlk %r1, %r15, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0xff, 0x00, 0x00, 0x00, 0xde ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "srlk %r15, %r15, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0xde ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "srlk %r0, %r0, -524288"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0xde ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "srlk %r0, %r0, -1"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0xde ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "srlk %r0, %r0, 1"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0xde ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "srlk %r0, %r0, 524287"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0xde ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "srlk %r0, %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0xde ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "srlk %r0, %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x1f, 0xff, 0x7f, 0xde ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "srlk %r0, %r0, 524287(%r1)"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0xff, 0xff, 0x7f, 0xde ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "srlk %r0, %r0, 524287(%r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0xc3 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stch %r0, -524288"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0xc3 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stch %r0, -1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0xc3 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stch %r0, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0xc3 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stch %r0, 1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0xc3 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stch %r0, 524287"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0xc3 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stch %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0xc3 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stch %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0xc3 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stch %r0, 524287(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0xc3 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stch %r0, 524287(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0xc3 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stch %r15, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0xc7 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sthh %r0, -524288"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0xc7 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sthh %r0, -1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0xc7 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sthh %r0, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0xc7 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sthh %r0, 1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0xc7 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sthh %r0, 524287"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0xc7 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sthh %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0xc7 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sthh %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0xc7 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sthh %r0, 524287(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0xc7 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sthh %r0, 524287(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0xc7 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sthh %r15, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0xcb ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stfh %r0, -524288"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0xcb ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stfh %r0, -1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0xcb ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stfh %r0, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0xcb ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stfh %r0, 1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0xcb ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stfh %r0, 524287"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0xcb ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stfh %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0xcb ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stfh %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0xcb ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stfh %r0, 524287(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0xcb ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stfh %r0, 524287(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0xcb ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stfh %r15, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0xf3 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stoc %r0, 0, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0x0f, 0x00, 0x00, 0x00, 0xf3 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stoc %r0, 0, 15"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0xf3 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stoc %r0, -524288, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0xf3 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stoc %r0, 524287, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0xf3 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stoc %r0, 0(%r1), 0"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0xf3 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stoc %r0, 0(%r15), 0"
+  -
+    input:
+      bytes: [ 0xeb, 0xf0, 0x00, 0x00, 0x00, 0xf3 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stoc %r15, 0, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0x11, 0x30, 0x02, 0x00, 0xf3 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stoco %r1, 2(%r3)"
+  -
+    input:
+      bytes: [ 0xeb, 0x12, 0x30, 0x02, 0x00, 0xf3 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stoch %r1, 2(%r3)"
+  -
+    input:
+      bytes: [ 0xeb, 0x13, 0x30, 0x02, 0x00, 0xf3 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stocnle %r1, 2(%r3)"
+  -
+    input:
+      bytes: [ 0xeb, 0x14, 0x30, 0x02, 0x00, 0xf3 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stocl %r1, 2(%r3)"
+  -
+    input:
+      bytes: [ 0xeb, 0x15, 0x30, 0x02, 0x00, 0xf3 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stocnhe %r1, 2(%r3)"
+  -
+    input:
+      bytes: [ 0xeb, 0x16, 0x30, 0x02, 0x00, 0xf3 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stoclh %r1, 2(%r3)"
+  -
+    input:
+      bytes: [ 0xeb, 0x17, 0x30, 0x02, 0x00, 0xf3 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stocne %r1, 2(%r3)"
+  -
+    input:
+      bytes: [ 0xeb, 0x18, 0x30, 0x02, 0x00, 0xf3 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stoce %r1, 2(%r3)"
+  -
+    input:
+      bytes: [ 0xeb, 0x19, 0x30, 0x02, 0x00, 0xf3 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stocnlh %r1, 2(%r3)"
+  -
+    input:
+      bytes: [ 0xeb, 0x1a, 0x30, 0x02, 0x00, 0xf3 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stoche %r1, 2(%r3)"
+  -
+    input:
+      bytes: [ 0xeb, 0x1b, 0x30, 0x02, 0x00, 0xf3 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stocnl %r1, 2(%r3)"
+  -
+    input:
+      bytes: [ 0xeb, 0x1c, 0x30, 0x02, 0x00, 0xf3 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stocle %r1, 2(%r3)"
+  -
+    input:
+      bytes: [ 0xeb, 0x1d, 0x30, 0x02, 0x00, 0xf3 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stocnh %r1, 2(%r3)"
+  -
+    input:
+      bytes: [ 0xeb, 0x1e, 0x30, 0x02, 0x00, 0xf3 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stocno %r1, 2(%r3)"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0xe3 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stocg %r0, 0, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0x0f, 0x00, 0x00, 0x00, 0xe3 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stocg %r0, 0, 15"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0xe3 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stocg %r0, -524288, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0xe3 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stocg %r0, 524287, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0xe3 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stocg %r0, 0(%r1), 0"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0xe3 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stocg %r0, 0(%r15), 0"
+  -
+    input:
+      bytes: [ 0xeb, 0xf0, 0x00, 0x00, 0x00, 0xe3 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stocg %r15, 0, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0x11, 0x30, 0x02, 0x00, 0xe3 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stocgo %r1, 2(%r3)"
+  -
+    input:
+      bytes: [ 0xeb, 0x12, 0x30, 0x02, 0x00, 0xe3 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stocgh %r1, 2(%r3)"
+  -
+    input:
+      bytes: [ 0xeb, 0x13, 0x30, 0x02, 0x00, 0xe3 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stocgnle %r1, 2(%r3)"
+  -
+    input:
+      bytes: [ 0xeb, 0x14, 0x30, 0x02, 0x00, 0xe3 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stocgl %r1, 2(%r3)"
+  -
+    input:
+      bytes: [ 0xeb, 0x15, 0x30, 0x02, 0x00, 0xe3 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stocgnhe %r1, 2(%r3)"
+  -
+    input:
+      bytes: [ 0xeb, 0x16, 0x30, 0x02, 0x00, 0xe3 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stocglh %r1, 2(%r3)"
+  -
+    input:
+      bytes: [ 0xeb, 0x17, 0x30, 0x02, 0x00, 0xe3 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stocgne %r1, 2(%r3)"
+  -
+    input:
+      bytes: [ 0xeb, 0x18, 0x30, 0x02, 0x00, 0xe3 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stocge %r1, 2(%r3)"
+  -
+    input:
+      bytes: [ 0xeb, 0x19, 0x30, 0x02, 0x00, 0xe3 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stocgnlh %r1, 2(%r3)"
+  -
+    input:
+      bytes: [ 0xeb, 0x1a, 0x30, 0x02, 0x00, 0xe3 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stocghe %r1, 2(%r3)"
+  -
+    input:
+      bytes: [ 0xeb, 0x1b, 0x30, 0x02, 0x00, 0xe3 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stocgnl %r1, 2(%r3)"
+  -
+    input:
+      bytes: [ 0xeb, 0x1c, 0x30, 0x02, 0x00, 0xe3 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stocgle %r1, 2(%r3)"
+  -
+    input:
+      bytes: [ 0xeb, 0x1d, 0x30, 0x02, 0x00, 0xe3 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stocgnh %r1, 2(%r3)"
+  -
+    input:
+      bytes: [ 0xeb, 0x1e, 0x30, 0x02, 0x00, 0xe3 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stocgno %r1, 2(%r3)"
+  -
+    input:
+      bytes: [ 0xb9, 0xe7, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "xgrk %r0, %r0, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0xe7, 0xf0, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "xgrk %r0, %r0, %r15"
+  -
+    input:
+      bytes: [ 0xb9, 0xe7, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "xgrk %r0, %r15, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0xe7, 0x00, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "xgrk %r15, %r0, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0xe7, 0x90, 0x78 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "xgrk %r7, %r8, %r9"
+  -
+    input:
+      bytes: [ 0xb9, 0xf7, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "xrk %r0, %r0, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0xf7, 0xf0, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "xrk %r0, %r0, %r15"
+  -
+    input:
+      bytes: [ 0xb9, 0xf7, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "xrk %r0, %r15, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0xf7, 0x00, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "xrk %r15, %r0, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0xf7, 0x90, 0x78 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "xrk %r7, %r8, %r9"
diff --git a/tests/MC/SystemZ/insn-good.s.yaml b/tests/MC/SystemZ/insn-good.s.yaml
new file mode 100644
index 000000000..8afc270ac
--- /dev/null
+++ b/tests/MC/SystemZ/insn-good.s.yaml
@@ -0,0 +1,20242 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x5a, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "a %r0, 0"
+  -
+    input:
+      bytes: [ 0x5a, 0x00, 0x0f, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "a %r0, 4095"
+  -
+    input:
+      bytes: [ 0x5a, 0x00, 0x10, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "a %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0x5a, 0x00, 0xf0, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "a %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0x5a, 0x01, 0xff, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "a %r0, 4095(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0x5a, 0x0f, 0x1f, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "a %r0, 4095(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0x5a, 0xf0, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "a %r15, 0"
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x1a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "adb %f0, 0"
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x00, 0x1a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "adb %f0, 4095"
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x1a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "adb %f0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x1a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "adb %f0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xed, 0x01, 0xff, 0xff, 0x00, 0x1a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "adb %f0, 4095(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x00, 0x1a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "adb %f0, 4095(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0xed, 0xf0, 0x00, 0x00, 0x00, 0x1a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "adb %f15, 0"
+  -
+    input:
+      bytes: [ 0xb3, 0x1a, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "adbr %f0, %f0"
+  -
+    input:
+      bytes: [ 0xb3, 0x1a, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "adbr %f0, %f15"
+  -
+    input:
+      bytes: [ 0xb3, 0x1a, 0x00, 0x78 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "adbr %f7, %f8"
+  -
+    input:
+      bytes: [ 0xb3, 0x1a, 0x00, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "adbr %f15, %f0"
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x0a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "aeb %f0, 0"
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x00, 0x0a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "aeb %f0, 4095"
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x0a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "aeb %f0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x0a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "aeb %f0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xed, 0x01, 0xff, 0xff, 0x00, 0x0a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "aeb %f0, 4095(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x00, 0x0a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "aeb %f0, 4095(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0xed, 0xf0, 0x00, 0x00, 0x00, 0x0a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "aeb %f15, 0"
+  -
+    input:
+      bytes: [ 0xb3, 0x0a, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "aebr %f0, %f0"
+  -
+    input:
+      bytes: [ 0xb3, 0x0a, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "aebr %f0, %f15"
+  -
+    input:
+      bytes: [ 0xb3, 0x0a, 0x00, 0x78 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "aebr %f7, %f8"
+  -
+    input:
+      bytes: [ 0xb3, 0x0a, 0x00, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "aebr %f15, %f0"
+  -
+    input:
+      bytes: [ 0xc2, 0x09, 0x80, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "afi %r0, -2147483648"
+  -
+    input:
+      bytes: [ 0xc2, 0x09, 0xff, 0xff, 0xff, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "afi %r0, -1"
+  -
+    input:
+      bytes: [ 0xc2, 0x09, 0x00, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "afi %r0, 0"
+  -
+    input:
+      bytes: [ 0xc2, 0x09, 0x00, 0x00, 0x00, 0x01 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "afi %r0, 1"
+  -
+    input:
+      bytes: [ 0xc2, 0x09, 0x7f, 0xff, 0xff, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "afi %r0, 2147483647"
+  -
+    input:
+      bytes: [ 0xc2, 0xf9, 0x00, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "afi %r15, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x08 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ag %r0, -524288"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x08 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ag %r0, -1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x08 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ag %r0, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x08 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ag %r0, 1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x08 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ag %r0, 524287"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x08 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ag %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x08 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ag %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x08 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ag %r0, 524287(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x08 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ag %r0, 524287(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x08 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ag %r15, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x18 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "agf %r0, -524288"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x18 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "agf %r0, -1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x18 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "agf %r0, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x18 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "agf %r0, 1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x18 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "agf %r0, 524287"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x18 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "agf %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x18 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "agf %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x18 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "agf %r0, 524287(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x18 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "agf %r0, 524287(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x18 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "agf %r15, 0"
+  -
+    input:
+      bytes: [ 0xc2, 0x08, 0x80, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "agfi %r0, -2147483648"
+  -
+    input:
+      bytes: [ 0xc2, 0x08, 0xff, 0xff, 0xff, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "agfi %r0, -1"
+  -
+    input:
+      bytes: [ 0xc2, 0x08, 0x00, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "agfi %r0, 0"
+  -
+    input:
+      bytes: [ 0xc2, 0x08, 0x00, 0x00, 0x00, 0x01 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "agfi %r0, 1"
+  -
+    input:
+      bytes: [ 0xc2, 0x08, 0x7f, 0xff, 0xff, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "agfi %r0, 2147483647"
+  -
+    input:
+      bytes: [ 0xc2, 0xf8, 0x00, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "agfi %r15, 0"
+  -
+    input:
+      bytes: [ 0xb9, 0x18, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "agfr %r0, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0x18, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "agfr %r0, %r15"
+  -
+    input:
+      bytes: [ 0xb9, 0x18, 0x00, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "agfr %r15, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0x18, 0x00, 0x78 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "agfr %r7, %r8"
+  -
+    input:
+      bytes: [ 0xa7, 0x0b, 0x80, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "aghi %r0, -32768"
+  -
+    input:
+      bytes: [ 0xa7, 0x0b, 0xff, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "aghi %r0, -1"
+  -
+    input:
+      bytes: [ 0xa7, 0x0b, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "aghi %r0, 0"
+  -
+    input:
+      bytes: [ 0xa7, 0x0b, 0x00, 0x01 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "aghi %r0, 1"
+  -
+    input:
+      bytes: [ 0xa7, 0x0b, 0x7f, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "aghi %r0, 32767"
+  -
+    input:
+      bytes: [ 0xa7, 0xfb, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "aghi %r15, 0"
+  -
+    input:
+      bytes: [ 0xb9, 0x08, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "agr %r0, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0x08, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "agr %r0, %r15"
+  -
+    input:
+      bytes: [ 0xb9, 0x08, 0x00, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "agr %r15, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0x08, 0x00, 0x78 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "agr %r7, %r8"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0x7a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "agsi -524288, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0x7a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "agsi -1, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0x7a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "agsi 0, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0x7a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "agsi 1, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0x7a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "agsi 524287, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0x80, 0x00, 0x00, 0x00, 0x7a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "agsi 0, -128"
+  -
+    input:
+      bytes: [ 0xeb, 0xff, 0x00, 0x00, 0x00, 0x7a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "agsi 0, -1"
+  -
+    input:
+      bytes: [ 0xeb, 0x01, 0x00, 0x00, 0x00, 0x7a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "agsi 0, 1"
+  -
+    input:
+      bytes: [ 0xeb, 0x7f, 0x00, 0x00, 0x00, 0x7a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "agsi 0, 127"
+  -
+    input:
+      bytes: [ 0xeb, 0x2a, 0x10, 0x00, 0x00, 0x7a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "agsi 0(%r1), 42"
+  -
+    input:
+      bytes: [ 0xeb, 0x2a, 0xf0, 0x00, 0x00, 0x7a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "agsi 0(%r15), 42"
+  -
+    input:
+      bytes: [ 0xeb, 0x2a, 0x1f, 0xff, 0x7f, 0x7a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "agsi 524287(%r1), 42"
+  -
+    input:
+      bytes: [ 0xeb, 0x2a, 0xff, 0xff, 0x7f, 0x7a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "agsi 524287(%r15), 42"
+  -
+    input:
+      bytes: [ 0x4a, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ah %r0, 0"
+  -
+    input:
+      bytes: [ 0x4a, 0x00, 0x0f, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ah %r0, 4095"
+  -
+    input:
+      bytes: [ 0x4a, 0x00, 0x10, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ah %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0x4a, 0x00, 0xf0, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ah %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0x4a, 0x01, 0xff, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ah %r0, 4095(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0x4a, 0x0f, 0x1f, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ah %r0, 4095(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0x4a, 0xf0, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ah %r15, 0"
+  -
+    input:
+      bytes: [ 0xa7, 0x0a, 0x80, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ahi %r0, -32768"
+  -
+    input:
+      bytes: [ 0xa7, 0x0a, 0xff, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ahi %r0, -1"
+  -
+    input:
+      bytes: [ 0xa7, 0x0a, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ahi %r0, 0"
+  -
+    input:
+      bytes: [ 0xa7, 0x0a, 0x00, 0x01 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ahi %r0, 1"
+  -
+    input:
+      bytes: [ 0xa7, 0x0a, 0x7f, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ahi %r0, 32767"
+  -
+    input:
+      bytes: [ 0xa7, 0xfa, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ahi %r15, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x7a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ahy %r0, -524288"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x7a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ahy %r0, -1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x7a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ahy %r0, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x7a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ahy %r0, 1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x7a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ahy %r0, 524287"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x7a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ahy %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x7a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ahy %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x7a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ahy %r0, 524287(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x7a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ahy %r0, 524287(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x7a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ahy %r15, 0"
+  -
+    input:
+      bytes: [ 0x5e, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "al %r0, 0"
+  -
+    input:
+      bytes: [ 0x5e, 0x00, 0x0f, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "al %r0, 4095"
+  -
+    input:
+      bytes: [ 0x5e, 0x00, 0x10, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "al %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0x5e, 0x00, 0xf0, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "al %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0x5e, 0x01, 0xff, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "al %r0, 4095(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0x5e, 0x0f, 0x1f, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "al %r0, 4095(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0x5e, 0xf0, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "al %r15, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x98 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "alc %r0, -524288"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x98 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "alc %r0, -1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x98 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "alc %r0, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x98 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "alc %r0, 1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x98 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "alc %r0, 524287"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x98 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "alc %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x98 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "alc %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x98 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "alc %r0, 524287(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x98 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "alc %r0, 524287(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x98 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "alc %r15, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x88 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "alcg %r0, -524288"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x88 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "alcg %r0, -1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x88 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "alcg %r0, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x88 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "alcg %r0, 1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x88 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "alcg %r0, 524287"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x88 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "alcg %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x88 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "alcg %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x88 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "alcg %r0, 524287(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x88 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "alcg %r0, 524287(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x88 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "alcg %r15, 0"
+  -
+    input:
+      bytes: [ 0xb9, 0x88, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "alcgr %r0, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0x88, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "alcgr %r0, %r15"
+  -
+    input:
+      bytes: [ 0xb9, 0x88, 0x00, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "alcgr %r15, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0x88, 0x00, 0x78 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "alcgr %r7, %r8"
+  -
+    input:
+      bytes: [ 0xb9, 0x98, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "alcr %r0, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0x98, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "alcr %r0, %r15"
+  -
+    input:
+      bytes: [ 0xb9, 0x98, 0x00, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "alcr %r15, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0x98, 0x00, 0x78 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "alcr %r7, %r8"
+  -
+    input:
+      bytes: [ 0xc2, 0x0b, 0x00, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "alfi %r0, 0"
+  -
+    input:
+      bytes: [ 0xc2, 0x0b, 0xff, 0xff, 0xff, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "alfi %r0, 4294967295"
+  -
+    input:
+      bytes: [ 0xc2, 0xfb, 0x00, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "alfi %r15, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x0a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "alg %r0, -524288"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x0a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "alg %r0, -1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x0a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "alg %r0, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x0a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "alg %r0, 1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x0a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "alg %r0, 524287"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x0a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "alg %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x0a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "alg %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x0a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "alg %r0, 524287(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x0a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "alg %r0, 524287(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x0a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "alg %r15, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x1a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "algf %r0, -524288"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x1a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "algf %r0, -1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x1a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "algf %r0, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x1a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "algf %r0, 1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x1a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "algf %r0, 524287"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x1a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "algf %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x1a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "algf %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x1a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "algf %r0, 524287(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x1a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "algf %r0, 524287(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x1a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "algf %r15, 0"
+  -
+    input:
+      bytes: [ 0xc2, 0x0a, 0x00, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "algfi %r0, 0"
+  -
+    input:
+      bytes: [ 0xc2, 0x0a, 0xff, 0xff, 0xff, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "algfi %r0, 4294967295"
+  -
+    input:
+      bytes: [ 0xc2, 0xfa, 0x00, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "algfi %r15, 0"
+  -
+    input:
+      bytes: [ 0xb9, 0x1a, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "algfr %r0, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0x1a, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "algfr %r0, %r15"
+  -
+    input:
+      bytes: [ 0xb9, 0x1a, 0x00, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "algfr %r15, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0x1a, 0x00, 0x78 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "algfr %r7, %r8"
+  -
+    input:
+      bytes: [ 0xb9, 0x0a, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "algr %r0, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0x0a, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "algr %r0, %r15"
+  -
+    input:
+      bytes: [ 0xb9, 0x0a, 0x00, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "algr %r15, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0x0a, 0x00, 0x78 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "algr %r7, %r8"
+  -
+    input:
+      bytes: [ 0x1e, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "alr %r0, %r0"
+  -
+    input:
+      bytes: [ 0x1e, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "alr %r0, %r15"
+  -
+    input:
+      bytes: [ 0x1e, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "alr %r15, %r0"
+  -
+    input:
+      bytes: [ 0x1e, 0x78 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "alr %r7, %r8"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x5e ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "aly %r0, -524288"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x5e ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "aly %r0, -1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x5e ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "aly %r0, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x5e ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "aly %r0, 1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x5e ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "aly %r0, 524287"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x5e ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "aly %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x5e ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "aly %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x5e ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "aly %r0, 524287(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x5e ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "aly %r0, 524287(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x5e ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "aly %r15, 0"
+  -
+    input:
+      bytes: [ 0x1a, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ar %r0, %r0"
+  -
+    input:
+      bytes: [ 0x1a, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ar %r0, %r15"
+  -
+    input:
+      bytes: [ 0x1a, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ar %r15, %r0"
+  -
+    input:
+      bytes: [ 0x1a, 0x78 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ar %r7, %r8"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0x6a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "asi -524288, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0x6a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "asi -1, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0x6a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "asi 0, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0x6a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "asi 1, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0x6a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "asi 524287, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0x80, 0x00, 0x00, 0x00, 0x6a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "asi 0, -128"
+  -
+    input:
+      bytes: [ 0xeb, 0xff, 0x00, 0x00, 0x00, 0x6a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "asi 0, -1"
+  -
+    input:
+      bytes: [ 0xeb, 0x01, 0x00, 0x00, 0x00, 0x6a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "asi 0, 1"
+  -
+    input:
+      bytes: [ 0xeb, 0x7f, 0x00, 0x00, 0x00, 0x6a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "asi 0, 127"
+  -
+    input:
+      bytes: [ 0xeb, 0x2a, 0x10, 0x00, 0x00, 0x6a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "asi 0(%r1), 42"
+  -
+    input:
+      bytes: [ 0xeb, 0x2a, 0xf0, 0x00, 0x00, 0x6a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "asi 0(%r15), 42"
+  -
+    input:
+      bytes: [ 0xeb, 0x2a, 0x1f, 0xff, 0x7f, 0x6a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "asi 524287(%r1), 42"
+  -
+    input:
+      bytes: [ 0xeb, 0x2a, 0xff, 0xff, 0x7f, 0x6a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "asi 524287(%r15), 42"
+  -
+    input:
+      bytes: [ 0xb3, 0x4a, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "axbr %f0, %f0"
+  -
+    input:
+      bytes: [ 0xb3, 0x4a, 0x00, 0x0d ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "axbr %f0, %f13"
+  -
+    input:
+      bytes: [ 0xb3, 0x4a, 0x00, 0x88 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "axbr %f8, %f8"
+  -
+    input:
+      bytes: [ 0xb3, 0x4a, 0x00, 0xd0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "axbr %f13, %f0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x5a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ay %r0, -524288"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x5a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ay %r0, -1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x5a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ay %r0, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x5a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ay %r0, 1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x5a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ay %r0, 524287"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x5a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ay %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x5a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ay %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x5a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ay %r0, 524287(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x5a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ay %r0, 524287(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x5a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ay %r15, 0"
+  -
+    input:
+      bytes: [ 0x0d, 0x01 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "basr %r0, %r1"
+  -
+    input:
+      bytes: [ 0x0d, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "basr %r0, %r15"
+  -
+    input:
+      bytes: [ 0x0d, 0xe9 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "basr %r14, %r9"
+  -
+    input:
+      bytes: [ 0x0d, 0xf1 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "basr %r15, %r1"
+  -
+    input:
+      bytes: [ 0x07, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "bcr 0, %r0"
+  -
+    input:
+      bytes: [ 0x07, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "bcr 0, %r15"
+  -
+    input:
+      bytes: [ 0x07, 0x1f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "bor %r15"
+  -
+    input:
+      bytes: [ 0x07, 0x2f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "bhr %r15"
+  -
+    input:
+      bytes: [ 0x07, 0x3f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "bnler %r15"
+  -
+    input:
+      bytes: [ 0x07, 0x4f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "blr %r15"
+  -
+    input:
+      bytes: [ 0x07, 0x5f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "bnher %r15"
+  -
+    input:
+      bytes: [ 0x07, 0x6f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "blhr %r15"
+  -
+    input:
+      bytes: [ 0x07, 0x7f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "bner %r15"
+  -
+    input:
+      bytes: [ 0x07, 0x8f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ber %r15"
+  -
+    input:
+      bytes: [ 0x07, 0x9f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "bnlhr %r15"
+  -
+    input:
+      bytes: [ 0x07, 0xaf ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "bher %r15"
+  -
+    input:
+      bytes: [ 0x07, 0xbf ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "bnlr %r15"
+  -
+    input:
+      bytes: [ 0x07, 0xcf ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "bler %r15"
+  -
+    input:
+      bytes: [ 0x07, 0xdf ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "bnhr %r15"
+  -
+    input:
+      bytes: [ 0x07, 0xef ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "bnor %r15"
+  -
+    input:
+      bytes: [ 0x07, 0xf1 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "br %r1"
+  -
+    input:
+      bytes: [ 0x07, 0xfe ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "br %r14"
+  -
+    input:
+      bytes: [ 0x07, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "br %r15"
+  -
+    input:
+      bytes: [ 0x59, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "c %r0, 0"
+  -
+    input:
+      bytes: [ 0x59, 0x00, 0x0f, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "c %r0, 4095"
+  -
+    input:
+      bytes: [ 0x59, 0x00, 0x10, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "c %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0x59, 0x00, 0xf0, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "c %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0x59, 0x01, 0xff, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "c %r0, 4095(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0x59, 0x0f, 0x1f, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "c %r0, 4095(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0x59, 0xf0, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "c %r15, 0"
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x19 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cdb %f0, 0"
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x00, 0x19 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cdb %f0, 4095"
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x19 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cdb %f0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x19 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cdb %f0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xed, 0x01, 0xff, 0xff, 0x00, 0x19 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cdb %f0, 4095(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x00, 0x19 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cdb %f0, 4095(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0xed, 0xf0, 0x00, 0x00, 0x00, 0x19 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cdb %f15, 0"
+  -
+    input:
+      bytes: [ 0xb3, 0x19, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cdbr %f0, %f0"
+  -
+    input:
+      bytes: [ 0xb3, 0x19, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cdbr %f0, %f15"
+  -
+    input:
+      bytes: [ 0xb3, 0x19, 0x00, 0x78 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cdbr %f7, %f8"
+  -
+    input:
+      bytes: [ 0xb3, 0x19, 0x00, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cdbr %f15, %f0"
+  -
+    input:
+      bytes: [ 0xb3, 0x95, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cdfbr %f0, %r0"
+  -
+    input:
+      bytes: [ 0xb3, 0x95, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cdfbr %f0, %r15"
+  -
+    input:
+      bytes: [ 0xb3, 0x95, 0x00, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cdfbr %f15, %r0"
+  -
+    input:
+      bytes: [ 0xb3, 0x95, 0x00, 0x78 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cdfbr %f7, %r8"
+  -
+    input:
+      bytes: [ 0xb3, 0x95, 0x00, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cdfbr %f15, %r15"
+  -
+    input:
+      bytes: [ 0xb3, 0xa5, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cdgbr %f0, %r0"
+  -
+    input:
+      bytes: [ 0xb3, 0xa5, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cdgbr %f0, %r15"
+  -
+    input:
+      bytes: [ 0xb3, 0xa5, 0x00, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cdgbr %f15, %r0"
+  -
+    input:
+      bytes: [ 0xb3, 0xa5, 0x00, 0x78 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cdgbr %f7, %r8"
+  -
+    input:
+      bytes: [ 0xb3, 0xa5, 0x00, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cdgbr %f15, %r15"
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x09 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ceb %f0, 0"
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x00, 0x09 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ceb %f0, 4095"
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x09 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ceb %f0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x09 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ceb %f0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xed, 0x01, 0xff, 0xff, 0x00, 0x09 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ceb %f0, 4095(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x00, 0x09 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ceb %f0, 4095(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0xed, 0xf0, 0x00, 0x00, 0x00, 0x09 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ceb %f15, 0"
+  -
+    input:
+      bytes: [ 0xb3, 0x09, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cebr %f0, %f0"
+  -
+    input:
+      bytes: [ 0xb3, 0x09, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cebr %f0, %f15"
+  -
+    input:
+      bytes: [ 0xb3, 0x09, 0x00, 0x78 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cebr %f7, %f8"
+  -
+    input:
+      bytes: [ 0xb3, 0x09, 0x00, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cebr %f15, %f0"
+  -
+    input:
+      bytes: [ 0xb3, 0x94, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cefbr %f0, %r0"
+  -
+    input:
+      bytes: [ 0xb3, 0x94, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cefbr %f0, %r15"
+  -
+    input:
+      bytes: [ 0xb3, 0x94, 0x00, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cefbr %f15, %r0"
+  -
+    input:
+      bytes: [ 0xb3, 0x94, 0x00, 0x78 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cefbr %f7, %r8"
+  -
+    input:
+      bytes: [ 0xb3, 0x94, 0x00, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cefbr %f15, %r15"
+  -
+    input:
+      bytes: [ 0xb3, 0xa4, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cegbr %f0, %r0"
+  -
+    input:
+      bytes: [ 0xb3, 0xa4, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cegbr %f0, %r15"
+  -
+    input:
+      bytes: [ 0xb3, 0xa4, 0x00, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cegbr %f15, %r0"
+  -
+    input:
+      bytes: [ 0xb3, 0xa4, 0x00, 0x78 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cegbr %f7, %r8"
+  -
+    input:
+      bytes: [ 0xb3, 0xa4, 0x00, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cegbr %f15, %r15"
+  -
+    input:
+      bytes: [ 0xb3, 0x99, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cfdbr %r0, 0, %f0"
+  -
+    input:
+      bytes: [ 0xb3, 0x99, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cfdbr %r0, 0, %f15"
+  -
+    input:
+      bytes: [ 0xb3, 0x99, 0xf0, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cfdbr %r0, 15, %f0"
+  -
+    input:
+      bytes: [ 0xb3, 0x99, 0x50, 0x46 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cfdbr %r4, 5, %f6"
+  -
+    input:
+      bytes: [ 0xb3, 0x99, 0x00, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cfdbr %r15, 0, %f0"
+  -
+    input:
+      bytes: [ 0xb3, 0x98, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cfebr %r0, 0, %f0"
+  -
+    input:
+      bytes: [ 0xb3, 0x98, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cfebr %r0, 0, %f15"
+  -
+    input:
+      bytes: [ 0xb3, 0x98, 0xf0, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cfebr %r0, 15, %f0"
+  -
+    input:
+      bytes: [ 0xb3, 0x98, 0x50, 0x46 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cfebr %r4, 5, %f6"
+  -
+    input:
+      bytes: [ 0xb3, 0x98, 0x00, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cfebr %r15, 0, %f0"
+  -
+    input:
+      bytes: [ 0xc2, 0x0d, 0x80, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cfi %r0, -2147483648"
+  -
+    input:
+      bytes: [ 0xc2, 0x0d, 0xff, 0xff, 0xff, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cfi %r0, -1"
+  -
+    input:
+      bytes: [ 0xc2, 0x0d, 0x00, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cfi %r0, 0"
+  -
+    input:
+      bytes: [ 0xc2, 0x0d, 0x00, 0x00, 0x00, 0x01 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cfi %r0, 1"
+  -
+    input:
+      bytes: [ 0xc2, 0x0d, 0x7f, 0xff, 0xff, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cfi %r0, 2147483647"
+  -
+    input:
+      bytes: [ 0xc2, 0xfd, 0x00, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cfi %r15, 0"
+  -
+    input:
+      bytes: [ 0xb3, 0x9a, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cfxbr %r0, 0, %f0"
+  -
+    input:
+      bytes: [ 0xb3, 0x9a, 0x00, 0x0d ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cfxbr %r0, 0, %f13"
+  -
+    input:
+      bytes: [ 0xb3, 0x9a, 0xf0, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cfxbr %r0, 15, %f0"
+  -
+    input:
+      bytes: [ 0xb3, 0x9a, 0x50, 0x48 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cfxbr %r4, 5, %f8"
+  -
+    input:
+      bytes: [ 0xb3, 0x9a, 0x00, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cfxbr %r15, 0, %f0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x20 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cg %r0, -524288"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x20 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cg %r0, -1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x20 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cg %r0, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x20 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cg %r0, 1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x20 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cg %r0, 524287"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x20 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cg %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x20 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cg %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x20 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cg %r0, 524287(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x20 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cg %r0, 524287(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x20 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cg %r15, 0"
+  -
+    input:
+      bytes: [ 0xb3, 0xa9, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cgdbr %r0, 0, %f0"
+  -
+    input:
+      bytes: [ 0xb3, 0xa9, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cgdbr %r0, 0, %f15"
+  -
+    input:
+      bytes: [ 0xb3, 0xa9, 0xf0, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cgdbr %r0, 15, %f0"
+  -
+    input:
+      bytes: [ 0xb3, 0xa9, 0x50, 0x46 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cgdbr %r4, 5, %f6"
+  -
+    input:
+      bytes: [ 0xb3, 0xa9, 0x00, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cgdbr %r15, 0, %f0"
+  -
+    input:
+      bytes: [ 0xb3, 0xa8, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cgebr %r0, 0, %f0"
+  -
+    input:
+      bytes: [ 0xb3, 0xa8, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cgebr %r0, 0, %f15"
+  -
+    input:
+      bytes: [ 0xb3, 0xa8, 0xf0, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cgebr %r0, 15, %f0"
+  -
+    input:
+      bytes: [ 0xb3, 0xa8, 0x50, 0x46 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cgebr %r4, 5, %f6"
+  -
+    input:
+      bytes: [ 0xb3, 0xa8, 0x00, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cgebr %r15, 0, %f0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x30 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cgf %r0, -524288"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x30 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cgf %r0, -1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x30 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cgf %r0, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x30 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cgf %r0, 1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x30 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cgf %r0, 524287"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x30 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cgf %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x30 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cgf %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x30 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cgf %r0, 524287(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x30 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cgf %r0, 524287(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x30 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cgf %r15, 0"
+  -
+    input:
+      bytes: [ 0xc2, 0x0c, 0x80, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cgfi %r0, -2147483648"
+  -
+    input:
+      bytes: [ 0xc2, 0x0c, 0xff, 0xff, 0xff, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cgfi %r0, -1"
+  -
+    input:
+      bytes: [ 0xc2, 0x0c, 0x00, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cgfi %r0, 0"
+  -
+    input:
+      bytes: [ 0xc2, 0x0c, 0x00, 0x00, 0x00, 0x01 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cgfi %r0, 1"
+  -
+    input:
+      bytes: [ 0xc2, 0x0c, 0x7f, 0xff, 0xff, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cgfi %r0, 2147483647"
+  -
+    input:
+      bytes: [ 0xc2, 0xfc, 0x00, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cgfi %r15, 0"
+  -
+    input:
+      bytes: [ 0xb9, 0x30, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cgfr %r0, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0x30, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cgfr %r0, %r15"
+  -
+    input:
+      bytes: [ 0xb9, 0x30, 0x00, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cgfr %r15, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0x30, 0x00, 0x78 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cgfr %r7, %r8"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x34 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cgh %r0, -524288"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x34 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cgh %r0, -1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x34 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cgh %r0, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x34 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cgh %r0, 1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x34 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cgh %r0, 524287"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x34 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cgh %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x34 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cgh %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x34 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cgh %r0, 524287(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x34 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cgh %r0, 524287(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x34 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cgh %r15, 0"
+  -
+    input:
+      bytes: [ 0xa7, 0x0f, 0x80, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cghi %r0, -32768"
+  -
+    input:
+      bytes: [ 0xa7, 0x0f, 0xff, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cghi %r0, -1"
+  -
+    input:
+      bytes: [ 0xa7, 0x0f, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cghi %r0, 0"
+  -
+    input:
+      bytes: [ 0xa7, 0x0f, 0x00, 0x01 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cghi %r0, 1"
+  -
+    input:
+      bytes: [ 0xa7, 0x0f, 0x7f, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cghi %r0, 32767"
+  -
+    input:
+      bytes: [ 0xa7, 0xff, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cghi %r15, 0"
+  -
+    input:
+      bytes: [ 0xe5, 0x58, 0x00, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cghsi 0, 0"
+  -
+    input:
+      bytes: [ 0xe5, 0x58, 0x0f, 0xff, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cghsi 4095, 0"
+  -
+    input:
+      bytes: [ 0xe5, 0x58, 0x00, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cghsi 0, -32768"
+  -
+    input:
+      bytes: [ 0xe5, 0x58, 0x00, 0x00, 0xff, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cghsi 0, -1"
+  -
+    input:
+      bytes: [ 0xe5, 0x58, 0x00, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cghsi 0, 0"
+  -
+    input:
+      bytes: [ 0xe5, 0x58, 0x00, 0x00, 0x00, 0x01 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cghsi 0, 1"
+  -
+    input:
+      bytes: [ 0xe5, 0x58, 0x00, 0x00, 0x7f, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cghsi 0, 32767"
+  -
+    input:
+      bytes: [ 0xe5, 0x58, 0x10, 0x00, 0x00, 0x2a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cghsi 0(%r1), 42"
+  -
+    input:
+      bytes: [ 0xe5, 0x58, 0xf0, 0x00, 0x00, 0x2a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cghsi 0(%r15), 42"
+  -
+    input:
+      bytes: [ 0xe5, 0x58, 0x1f, 0xff, 0x00, 0x2a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cghsi 4095(%r1), 42"
+  -
+    input:
+      bytes: [ 0xe5, 0x58, 0xff, 0xff, 0x00, 0x2a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cghsi 4095(%r15), 42"
+  -
+    input:
+      bytes: [ 0xb9, 0x20, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cgr %r0, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0x20, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cgr %r0, %r15"
+  -
+    input:
+      bytes: [ 0xb9, 0x20, 0x00, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cgr %r15, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0x20, 0x00, 0x78 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cgr %r7, %r8"
+  -
+    input:
+      bytes: [ 0xb3, 0xaa, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cgxbr %r0, 0, %f0"
+  -
+    input:
+      bytes: [ 0xb3, 0xaa, 0x00, 0x0d ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cgxbr %r0, 0, %f13"
+  -
+    input:
+      bytes: [ 0xb3, 0xaa, 0xf0, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cgxbr %r0, 15, %f0"
+  -
+    input:
+      bytes: [ 0xb3, 0xaa, 0x50, 0x48 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cgxbr %r4, 5, %f8"
+  -
+    input:
+      bytes: [ 0xb3, 0xaa, 0x00, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cgxbr %r15, 0, %f0"
+  -
+    input:
+      bytes: [ 0x49, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ch %r0, 0"
+  -
+    input:
+      bytes: [ 0x49, 0x00, 0x0f, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ch %r0, 4095"
+  -
+    input:
+      bytes: [ 0x49, 0x00, 0x10, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ch %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0x49, 0x00, 0xf0, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ch %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0x49, 0x01, 0xff, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ch %r0, 4095(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0x49, 0x0f, 0x1f, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ch %r0, 4095(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0x49, 0xf0, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ch %r15, 0"
+  -
+    input:
+      bytes: [ 0xe5, 0x54, 0x00, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "chhsi 0, 0"
+  -
+    input:
+      bytes: [ 0xe5, 0x54, 0x0f, 0xff, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "chhsi 4095, 0"
+  -
+    input:
+      bytes: [ 0xe5, 0x54, 0x00, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "chhsi 0, -32768"
+  -
+    input:
+      bytes: [ 0xe5, 0x54, 0x00, 0x00, 0xff, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "chhsi 0, -1"
+  -
+    input:
+      bytes: [ 0xe5, 0x54, 0x00, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "chhsi 0, 0"
+  -
+    input:
+      bytes: [ 0xe5, 0x54, 0x00, 0x00, 0x00, 0x01 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "chhsi 0, 1"
+  -
+    input:
+      bytes: [ 0xe5, 0x54, 0x00, 0x00, 0x7f, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "chhsi 0, 32767"
+  -
+    input:
+      bytes: [ 0xe5, 0x54, 0x10, 0x00, 0x00, 0x2a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "chhsi 0(%r1), 42"
+  -
+    input:
+      bytes: [ 0xe5, 0x54, 0xf0, 0x00, 0x00, 0x2a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "chhsi 0(%r15), 42"
+  -
+    input:
+      bytes: [ 0xe5, 0x54, 0x1f, 0xff, 0x00, 0x2a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "chhsi 4095(%r1), 42"
+  -
+    input:
+      bytes: [ 0xe5, 0x54, 0xff, 0xff, 0x00, 0x2a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "chhsi 4095(%r15), 42"
+  -
+    input:
+      bytes: [ 0xa7, 0x0e, 0x80, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "chi %r0, -32768"
+  -
+    input:
+      bytes: [ 0xa7, 0x0e, 0xff, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "chi %r0, -1"
+  -
+    input:
+      bytes: [ 0xa7, 0x0e, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "chi %r0, 0"
+  -
+    input:
+      bytes: [ 0xa7, 0x0e, 0x00, 0x01 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "chi %r0, 1"
+  -
+    input:
+      bytes: [ 0xa7, 0x0e, 0x7f, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "chi %r0, 32767"
+  -
+    input:
+      bytes: [ 0xa7, 0xfe, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "chi %r15, 0"
+  -
+    input:
+      bytes: [ 0xe5, 0x5c, 0x00, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "chsi 0, 0"
+  -
+    input:
+      bytes: [ 0xe5, 0x5c, 0x0f, 0xff, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "chsi 4095, 0"
+  -
+    input:
+      bytes: [ 0xe5, 0x5c, 0x00, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "chsi 0, -32768"
+  -
+    input:
+      bytes: [ 0xe5, 0x5c, 0x00, 0x00, 0xff, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "chsi 0, -1"
+  -
+    input:
+      bytes: [ 0xe5, 0x5c, 0x00, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "chsi 0, 0"
+  -
+    input:
+      bytes: [ 0xe5, 0x5c, 0x00, 0x00, 0x00, 0x01 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "chsi 0, 1"
+  -
+    input:
+      bytes: [ 0xe5, 0x5c, 0x00, 0x00, 0x7f, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "chsi 0, 32767"
+  -
+    input:
+      bytes: [ 0xe5, 0x5c, 0x10, 0x00, 0x00, 0x2a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "chsi 0(%r1), 42"
+  -
+    input:
+      bytes: [ 0xe5, 0x5c, 0xf0, 0x00, 0x00, 0x2a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "chsi 0(%r15), 42"
+  -
+    input:
+      bytes: [ 0xe5, 0x5c, 0x1f, 0xff, 0x00, 0x2a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "chsi 4095(%r1), 42"
+  -
+    input:
+      bytes: [ 0xe5, 0x5c, 0xff, 0xff, 0x00, 0x2a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "chsi 4095(%r15), 42"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x79 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "chy %r0, -524288"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x79 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "chy %r0, -1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x79 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "chy %r0, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x79 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "chy %r0, 1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x79 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "chy %r0, 524287"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x79 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "chy %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x79 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "chy %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x79 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "chy %r0, 524287(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x79 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "chy %r0, 524287(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x79 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "chy %r15, 0"
+  -
+    input:
+      bytes: [ 0x55, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cl %r0, 0"
+  -
+    input:
+      bytes: [ 0x55, 0x00, 0x0f, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cl %r0, 4095"
+  -
+    input:
+      bytes: [ 0x55, 0x00, 0x10, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cl %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0x55, 0x00, 0xf0, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cl %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0x55, 0x01, 0xff, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cl %r0, 4095(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0x55, 0x0f, 0x1f, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cl %r0, 4095(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0x55, 0xf0, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cl %r15, 0"
+  -
+    input:
+      bytes: [ 0xd5, 0x00, 0x00, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clc 0(1), 0"
+  -
+    input:
+      bytes: [ 0xd5, 0x00, 0x00, 0x00, 0x10, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clc 0(1), 0(%r1)"
+  -
+    input:
+      bytes: [ 0xd5, 0x00, 0x00, 0x00, 0xf0, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clc 0(1), 0(%r15)"
+  -
+    input:
+      bytes: [ 0xd5, 0x00, 0x00, 0x00, 0x0f, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clc 0(1), 4095"
+  -
+    input:
+      bytes: [ 0xd5, 0x00, 0x00, 0x00, 0x1f, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clc 0(1), 4095(%r1)"
+  -
+    input:
+      bytes: [ 0xd5, 0x00, 0x00, 0x00, 0xff, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clc 0(1), 4095(%r15)"
+  -
+    input:
+      bytes: [ 0xd5, 0x00, 0x10, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clc 0(1, %r1), 0"
+  -
+    input:
+      bytes: [ 0xd5, 0x00, 0xf0, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clc 0(1, %r15), 0"
+  -
+    input:
+      bytes: [ 0xd5, 0x00, 0x1f, 0xff, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clc 4095(1, %r1), 0"
+  -
+    input:
+      bytes: [ 0xd5, 0x00, 0xff, 0xff, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clc 4095(1, %r15), 0"
+  -
+    input:
+      bytes: [ 0xd5, 0xff, 0x10, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clc 0(256, %r1), 0"
+  -
+    input:
+      bytes: [ 0xd5, 0xff, 0xf0, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clc 0(256, %r15), 0"
+  -
+    input:
+      bytes: [ 0xe5, 0x5d, 0x00, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clfhsi 0, 0"
+  -
+    input:
+      bytes: [ 0xe5, 0x5d, 0x0f, 0xff, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clfhsi 4095, 0"
+  -
+    input:
+      bytes: [ 0xe5, 0x5d, 0x00, 0x00, 0xff, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clfhsi 0, 65535"
+  -
+    input:
+      bytes: [ 0xe5, 0x5d, 0x10, 0x00, 0x00, 0x2a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clfhsi 0(%r1), 42"
+  -
+    input:
+      bytes: [ 0xe5, 0x5d, 0xf0, 0x00, 0x00, 0x2a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clfhsi 0(%r15), 42"
+  -
+    input:
+      bytes: [ 0xe5, 0x5d, 0x1f, 0xff, 0x00, 0x2a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clfhsi 4095(%r1), 42"
+  -
+    input:
+      bytes: [ 0xe5, 0x5d, 0xff, 0xff, 0x00, 0x2a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clfhsi 4095(%r15), 42"
+  -
+    input:
+      bytes: [ 0xc2, 0x0f, 0x00, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clfi %r0, 0"
+  -
+    input:
+      bytes: [ 0xc2, 0x0f, 0xff, 0xff, 0xff, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clfi %r0, 4294967295"
+  -
+    input:
+      bytes: [ 0xc2, 0xff, 0x00, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clfi %r15, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x21 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clg %r0, -524288"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x21 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clg %r0, -1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x21 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clg %r0, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x21 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clg %r0, 1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x21 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clg %r0, 524287"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x21 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clg %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x21 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clg %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x21 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clg %r0, 524287(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x21 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clg %r0, 524287(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x21 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clg %r15, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x31 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clgf %r0, -524288"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x31 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clgf %r0, -1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x31 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clgf %r0, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x31 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clgf %r0, 1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x31 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clgf %r0, 524287"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x31 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clgf %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x31 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clgf %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x31 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clgf %r0, 524287(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x31 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clgf %r0, 524287(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x31 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clgf %r15, 0"
+  -
+    input:
+      bytes: [ 0xc2, 0x0e, 0x00, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clgfi %r0, 0"
+  -
+    input:
+      bytes: [ 0xc2, 0x0e, 0xff, 0xff, 0xff, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clgfi %r0, 4294967295"
+  -
+    input:
+      bytes: [ 0xc2, 0xfe, 0x00, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clgfi %r15, 0"
+  -
+    input:
+      bytes: [ 0xb9, 0x31, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clgfr %r0, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0x31, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clgfr %r0, %r15"
+  -
+    input:
+      bytes: [ 0xb9, 0x31, 0x00, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clgfr %r15, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0x31, 0x00, 0x78 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clgfr %r7, %r8"
+  -
+    input:
+      bytes: [ 0xb9, 0x21, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clgr %r0, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0x21, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clgr %r0, %r15"
+  -
+    input:
+      bytes: [ 0xb9, 0x21, 0x00, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clgr %r15, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0x21, 0x00, 0x78 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clgr %r7, %r8"
+  -
+    input:
+      bytes: [ 0xe5, 0x55, 0x00, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clhhsi 0, 0"
+  -
+    input:
+      bytes: [ 0xe5, 0x55, 0x0f, 0xff, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clhhsi 4095, 0"
+  -
+    input:
+      bytes: [ 0xe5, 0x55, 0x00, 0x00, 0xff, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clhhsi 0, 65535"
+  -
+    input:
+      bytes: [ 0xe5, 0x55, 0x10, 0x00, 0x00, 0x2a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clhhsi 0(%r1), 42"
+  -
+    input:
+      bytes: [ 0xe5, 0x55, 0xf0, 0x00, 0x00, 0x2a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clhhsi 0(%r15), 42"
+  -
+    input:
+      bytes: [ 0xe5, 0x55, 0x1f, 0xff, 0x00, 0x2a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clhhsi 4095(%r1), 42"
+  -
+    input:
+      bytes: [ 0xe5, 0x55, 0xff, 0xff, 0x00, 0x2a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clhhsi 4095(%r15), 42"
+  -
+    input:
+      bytes: [ 0x95, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cli 0, 0"
+  -
+    input:
+      bytes: [ 0x95, 0x00, 0x0f, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cli 4095, 0"
+  -
+    input:
+      bytes: [ 0x95, 0xff, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cli 0, 255"
+  -
+    input:
+      bytes: [ 0x95, 0x2a, 0x10, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cli 0(%r1), 42"
+  -
+    input:
+      bytes: [ 0x95, 0x2a, 0xf0, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cli 0(%r15), 42"
+  -
+    input:
+      bytes: [ 0x95, 0x2a, 0x1f, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cli 4095(%r1), 42"
+  -
+    input:
+      bytes: [ 0x95, 0x2a, 0xff, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cli 4095(%r15), 42"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0x55 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cliy -524288, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0x55 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cliy -1, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0x55 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cliy 0, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0x55 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cliy 1, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0x55 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cliy 524287, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0xff, 0x00, 0x00, 0x00, 0x55 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cliy 0, 255"
+  -
+    input:
+      bytes: [ 0xeb, 0x2a, 0x10, 0x00, 0x00, 0x55 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cliy 0(%r1), 42"
+  -
+    input:
+      bytes: [ 0xeb, 0x2a, 0xf0, 0x00, 0x00, 0x55 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cliy 0(%r15), 42"
+  -
+    input:
+      bytes: [ 0xeb, 0x2a, 0x1f, 0xff, 0x7f, 0x55 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cliy 524287(%r1), 42"
+  -
+    input:
+      bytes: [ 0xeb, 0x2a, 0xff, 0xff, 0x7f, 0x55 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cliy 524287(%r15), 42"
+  -
+    input:
+      bytes: [ 0x15, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clr %r0, %r0"
+  -
+    input:
+      bytes: [ 0x15, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clr %r0, %r15"
+  -
+    input:
+      bytes: [ 0x15, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clr %r15, %r0"
+  -
+    input:
+      bytes: [ 0x15, 0x78 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clr %r7, %r8"
+  -
+    input:
+      bytes: [ 0xb2, 0x5d, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clst %r0, %r0"
+  -
+    input:
+      bytes: [ 0xb2, 0x5d, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clst %r0, %r15"
+  -
+    input:
+      bytes: [ 0xb2, 0x5d, 0x00, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clst %r15, %r0"
+  -
+    input:
+      bytes: [ 0xb2, 0x5d, 0x00, 0x78 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "clst %r7, %r8"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x55 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cly %r0, -524288"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x55 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cly %r0, -1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x55 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cly %r0, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x55 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cly %r0, 1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x55 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cly %r0, 524287"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x55 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cly %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x55 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cly %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x55 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cly %r0, 524287(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x55 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cly %r0, 524287(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x55 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cly %r15, 0"
+  -
+    input:
+      bytes: [ 0xb3, 0x72, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cpsdr %f0, %f0, %f0"
+  -
+    input:
+      bytes: [ 0xb3, 0x72, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cpsdr %f0, %f0, %f15"
+  -
+    input:
+      bytes: [ 0xb3, 0x72, 0xf0, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cpsdr %f0, %f15, %f0"
+  -
+    input:
+      bytes: [ 0xb3, 0x72, 0x00, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cpsdr %f15, %f0, %f0"
+  -
+    input:
+      bytes: [ 0xb3, 0x72, 0x20, 0x13 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cpsdr %f1, %f2, %f3"
+  -
+    input:
+      bytes: [ 0xb3, 0x72, 0xf0, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cpsdr %f15, %f15, %f15"
+  -
+    input:
+      bytes: [ 0x19, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cr %r0, %r0"
+  -
+    input:
+      bytes: [ 0x19, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cr %r0, %r15"
+  -
+    input:
+      bytes: [ 0x19, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cr %r15, %r0"
+  -
+    input:
+      bytes: [ 0x19, 0x78 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cr %r7, %r8"
+  -
+    input:
+      bytes: [ 0xba, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cs %r0, %r0, 0"
+  -
+    input:
+      bytes: [ 0xba, 0x00, 0x0f, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cs %r0, %r0, 4095"
+  -
+    input:
+      bytes: [ 0xba, 0x00, 0x10, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cs %r0, %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xba, 0x00, 0xf0, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cs %r0, %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xba, 0x00, 0x1f, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cs %r0, %r0, 4095(%r1)"
+  -
+    input:
+      bytes: [ 0xba, 0x00, 0xff, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cs %r0, %r0, 4095(%r15)"
+  -
+    input:
+      bytes: [ 0xba, 0x0f, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cs %r0, %r15, 0"
+  -
+    input:
+      bytes: [ 0xba, 0xf0, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cs %r15, %r0, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0x30 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "csg %r0, %r0, -524288"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0x30 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "csg %r0, %r0, -1"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0x30 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "csg %r0, %r0, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0x30 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "csg %r0, %r0, 1"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0x30 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "csg %r0, %r0, 524287"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0x30 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "csg %r0, %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0x30 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "csg %r0, %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x1f, 0xff, 0x7f, 0x30 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "csg %r0, %r0, 524287(%r1)"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0xff, 0xff, 0x7f, 0x30 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "csg %r0, %r0, 524287(%r15)"
+  -
+    input:
+      bytes: [ 0xeb, 0x0f, 0x00, 0x00, 0x00, 0x30 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "csg %r0, %r15, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0xf0, 0x00, 0x00, 0x00, 0x30 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "csg %r15, %r0, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0x14 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "csy %r0, %r0, -524288"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0x14 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "csy %r0, %r0, -1"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0x14 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "csy %r0, %r0, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0x14 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "csy %r0, %r0, 1"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0x14 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "csy %r0, %r0, 524287"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0x14 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "csy %r0, %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0x14 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "csy %r0, %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x1f, 0xff, 0x7f, 0x14 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "csy %r0, %r0, 524287(%r1)"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0xff, 0xff, 0x7f, 0x14 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "csy %r0, %r0, 524287(%r15)"
+  -
+    input:
+      bytes: [ 0xeb, 0x0f, 0x00, 0x00, 0x00, 0x14 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "csy %r0, %r15, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0xf0, 0x00, 0x00, 0x00, 0x14 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "csy %r15, %r0, 0"
+  -
+    input:
+      bytes: [ 0xb3, 0x49, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cxbr %f0, %f0"
+  -
+    input:
+      bytes: [ 0xb3, 0x49, 0x00, 0x0d ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cxbr %f0, %f13"
+  -
+    input:
+      bytes: [ 0xb3, 0x49, 0x00, 0x88 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cxbr %f8, %f8"
+  -
+    input:
+      bytes: [ 0xb3, 0x49, 0x00, 0xd0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cxbr %f13, %f0"
+  -
+    input:
+      bytes: [ 0xb3, 0x96, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cxfbr %f0, %r0"
+  -
+    input:
+      bytes: [ 0xb3, 0x96, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cxfbr %f0, %r15"
+  -
+    input:
+      bytes: [ 0xb3, 0x96, 0x00, 0xd0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cxfbr %f13, %r0"
+  -
+    input:
+      bytes: [ 0xb3, 0x96, 0x00, 0x87 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cxfbr %f8, %r7"
+  -
+    input:
+      bytes: [ 0xb3, 0x96, 0x00, 0xdf ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cxfbr %f13, %r15"
+  -
+    input:
+      bytes: [ 0xb3, 0xa6, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cxgbr %f0, %r0"
+  -
+    input:
+      bytes: [ 0xb3, 0xa6, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cxgbr %f0, %r15"
+  -
+    input:
+      bytes: [ 0xb3, 0xa6, 0x00, 0xd0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cxgbr %f13, %r0"
+  -
+    input:
+      bytes: [ 0xb3, 0xa6, 0x00, 0x87 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cxgbr %f8, %r7"
+  -
+    input:
+      bytes: [ 0xb3, 0xa6, 0x00, 0xdf ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cxgbr %f13, %r15"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x59 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cy %r0, -524288"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x59 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cy %r0, -1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x59 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cy %r0, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x59 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cy %r0, 1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x59 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cy %r0, 524287"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x59 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cy %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x59 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cy %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x59 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cy %r0, 524287(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x59 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cy %r0, 524287(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x59 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "cy %r15, 0"
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x1d ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ddb %f0, 0"
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x00, 0x1d ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ddb %f0, 4095"
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x1d ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ddb %f0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x1d ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ddb %f0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xed, 0x01, 0xff, 0xff, 0x00, 0x1d ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ddb %f0, 4095(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x00, 0x1d ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ddb %f0, 4095(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0xed, 0xf0, 0x00, 0x00, 0x00, 0x1d ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ddb %f15, 0"
+  -
+    input:
+      bytes: [ 0xb3, 0x1d, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ddbr %f0, %f0"
+  -
+    input:
+      bytes: [ 0xb3, 0x1d, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ddbr %f0, %f15"
+  -
+    input:
+      bytes: [ 0xb3, 0x1d, 0x00, 0x78 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ddbr %f7, %f8"
+  -
+    input:
+      bytes: [ 0xb3, 0x1d, 0x00, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ddbr %f15, %f0"
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x0d ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "deb %f0, 0"
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x00, 0x0d ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "deb %f0, 4095"
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x0d ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "deb %f0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x0d ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "deb %f0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xed, 0x01, 0xff, 0xff, 0x00, 0x0d ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "deb %f0, 4095(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x00, 0x0d ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "deb %f0, 4095(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0xed, 0xf0, 0x00, 0x00, 0x00, 0x0d ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "deb %f15, 0"
+  -
+    input:
+      bytes: [ 0xb3, 0x0d, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "debr %f0, %f0"
+  -
+    input:
+      bytes: [ 0xb3, 0x0d, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "debr %f0, %f15"
+  -
+    input:
+      bytes: [ 0xb3, 0x0d, 0x00, 0x78 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "debr %f7, %f8"
+  -
+    input:
+      bytes: [ 0xb3, 0x0d, 0x00, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "debr %f15, %f0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x97 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "dl %r0, -524288"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x97 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "dl %r0, -1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x97 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "dl %r0, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x97 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "dl %r0, 1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x97 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "dl %r0, 524287"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x97 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "dl %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x97 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "dl %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x97 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "dl %r0, 524287(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x97 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "dl %r0, 524287(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0xe0, 0x00, 0x00, 0x00, 0x97 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "dl %r14, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x87 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "dlg %r0, -524288"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x87 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "dlg %r0, -1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x87 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "dlg %r0, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x87 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "dlg %r0, 1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x87 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "dlg %r0, 524287"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x87 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "dlg %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x87 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "dlg %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x87 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "dlg %r0, 524287(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x87 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "dlg %r0, 524287(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0xe0, 0x00, 0x00, 0x00, 0x87 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "dlg %r14, 0"
+  -
+    input:
+      bytes: [ 0xb9, 0x87, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "dlgr %r0, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0x87, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "dlgr %r0, %r15"
+  -
+    input:
+      bytes: [ 0xb9, 0x87, 0x00, 0xe0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "dlgr %r14, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0x87, 0x00, 0x69 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "dlgr %r6, %r9"
+  -
+    input:
+      bytes: [ 0xb9, 0x97, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "dlr %r0, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0x97, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "dlr %r0, %r15"
+  -
+    input:
+      bytes: [ 0xb9, 0x97, 0x00, 0xe0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "dlr %r14, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0x97, 0x00, 0x69 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "dlr %r6, %r9"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x0d ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "dsg %r0, -524288"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x0d ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "dsg %r0, -1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x0d ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "dsg %r0, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x0d ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "dsg %r0, 1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x0d ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "dsg %r0, 524287"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x0d ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "dsg %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x0d ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "dsg %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x0d ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "dsg %r0, 524287(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x0d ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "dsg %r0, 524287(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0xe0, 0x00, 0x00, 0x00, 0x0d ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "dsg %r14, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x1d ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "dsgf %r0, -524288"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x1d ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "dsgf %r0, -1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x1d ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "dsgf %r0, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x1d ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "dsgf %r0, 1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x1d ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "dsgf %r0, 524287"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x1d ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "dsgf %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x1d ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "dsgf %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x1d ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "dsgf %r0, 524287(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x1d ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "dsgf %r0, 524287(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0xe0, 0x00, 0x00, 0x00, 0x1d ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "dsgf %r14, 0"
+  -
+    input:
+      bytes: [ 0xb9, 0x1d, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "dsgfr %r0, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0x1d, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "dsgfr %r0, %r15"
+  -
+    input:
+      bytes: [ 0xb9, 0x1d, 0x00, 0xe0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "dsgfr %r14, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0x1d, 0x00, 0x69 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "dsgfr %r6, %r9"
+  -
+    input:
+      bytes: [ 0xb9, 0x0d, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "dsgr %r0, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0x0d, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "dsgr %r0, %r15"
+  -
+    input:
+      bytes: [ 0xb9, 0x0d, 0x00, 0xe0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "dsgr %r14, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0x0d, 0x00, 0x69 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "dsgr %r6, %r9"
+  -
+    input:
+      bytes: [ 0xb3, 0x4d, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "dxbr %f0, %f0"
+  -
+    input:
+      bytes: [ 0xb3, 0x4d, 0x00, 0x0d ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "dxbr %f0, %f13"
+  -
+    input:
+      bytes: [ 0xb3, 0x4d, 0x00, 0x88 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "dxbr %f8, %f8"
+  -
+    input:
+      bytes: [ 0xb3, 0x4d, 0x00, 0xd0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "dxbr %f13, %f0"
+  -
+    input:
+      bytes: [ 0xb2, 0x4f, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ear %r0, %a0"
+  -
+    input:
+      bytes: [ 0xb2, 0x4f, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ear %r0, %a15"
+  -
+    input:
+      bytes: [ 0xb2, 0x4f, 0x00, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ear %r15, %a0"
+  -
+    input:
+      bytes: [ 0xb2, 0x4f, 0x00, 0x78 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ear %r7, %a8"
+  -
+    input:
+      bytes: [ 0xb2, 0x4f, 0x00, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ear %r15, %a15"
+  -
+    input:
+      bytes: [ 0xb3, 0x5f, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "fidbr %f0, 0, %f0"
+  -
+    input:
+      bytes: [ 0xb3, 0x5f, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "fidbr %f0, 0, %f15"
+  -
+    input:
+      bytes: [ 0xb3, 0x5f, 0xf0, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "fidbr %f0, 15, %f0"
+  -
+    input:
+      bytes: [ 0xb3, 0x5f, 0x50, 0x46 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "fidbr %f4, 5, %f6"
+  -
+    input:
+      bytes: [ 0xb3, 0x5f, 0x00, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "fidbr %f15, 0, %f0"
+  -
+    input:
+      bytes: [ 0xb3, 0x57, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "fiebr %f0, 0, %f0"
+  -
+    input:
+      bytes: [ 0xb3, 0x57, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "fiebr %f0, 0, %f15"
+  -
+    input:
+      bytes: [ 0xb3, 0x57, 0xf0, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "fiebr %f0, 15, %f0"
+  -
+    input:
+      bytes: [ 0xb3, 0x57, 0x50, 0x46 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "fiebr %f4, 5, %f6"
+  -
+    input:
+      bytes: [ 0xb3, 0x57, 0x00, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "fiebr %f15, 0, %f0"
+  -
+    input:
+      bytes: [ 0xb3, 0x47, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "fixbr %f0, 0, %f0"
+  -
+    input:
+      bytes: [ 0xb3, 0x47, 0x00, 0x0d ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "fixbr %f0, 0, %f13"
+  -
+    input:
+      bytes: [ 0xb3, 0x47, 0xf0, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "fixbr %f0, 15, %f0"
+  -
+    input:
+      bytes: [ 0xb3, 0x47, 0x50, 0x48 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "fixbr %f4, 5, %f8"
+  -
+    input:
+      bytes: [ 0xb3, 0x47, 0x00, 0xd0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "fixbr %f13, 0, %f0"
+  -
+    input:
+      bytes: [ 0xb9, 0x83, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "flogr %r0, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0x83, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "flogr %r0, %r15"
+  -
+    input:
+      bytes: [ 0xb9, 0x83, 0x00, 0xa9 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "flogr %r10, %r9"
+  -
+    input:
+      bytes: [ 0xb9, 0x83, 0x00, 0xe0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "flogr %r14, %r0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ic %r0, 0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x0f, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ic %r0, 4095"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x10, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ic %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0xf0, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ic %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0x43, 0x01, 0xff, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ic %r0, 4095(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0x43, 0x0f, 0x1f, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ic %r0, 4095(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0x43, 0xf0, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ic %r15, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x73 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "icy %r0, -524288"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x73 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "icy %r0, -1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x73 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "icy %r0, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x73 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "icy %r0, 1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x73 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "icy %r0, 524287"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x73 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "icy %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x73 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "icy %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x73 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "icy %r0, 524287(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x73 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "icy %r0, 524287(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x73 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "icy %r15, 0"
+  -
+    input:
+      bytes: [ 0xc0, 0x08, 0x00, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "iihf %r0, 0"
+  -
+    input:
+      bytes: [ 0xc0, 0x08, 0xff, 0xff, 0xff, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "iihf %r0, 4294967295"
+  -
+    input:
+      bytes: [ 0xc0, 0xf8, 0x00, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "iihf %r15, 0"
+  -
+    input:
+      bytes: [ 0xa5, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "iihh %r0, 0"
+  -
+    input:
+      bytes: [ 0xa5, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "iihh %r0, 32768"
+  -
+    input:
+      bytes: [ 0xa5, 0x00, 0xff, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "iihh %r0, 65535"
+  -
+    input:
+      bytes: [ 0xa5, 0xf0, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "iihh %r15, 0"
+  -
+    input:
+      bytes: [ 0xa5, 0x01, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "iihl %r0, 0"
+  -
+    input:
+      bytes: [ 0xa5, 0x01, 0x80, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "iihl %r0, 32768"
+  -
+    input:
+      bytes: [ 0xa5, 0x01, 0xff, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "iihl %r0, 65535"
+  -
+    input:
+      bytes: [ 0xa5, 0xf1, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "iihl %r15, 0"
+  -
+    input:
+      bytes: [ 0xc0, 0x09, 0x00, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "iilf %r0, 0"
+  -
+    input:
+      bytes: [ 0xc0, 0x09, 0xff, 0xff, 0xff, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "iilf %r0, 4294967295"
+  -
+    input:
+      bytes: [ 0xc0, 0xf9, 0x00, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "iilf %r15, 0"
+  -
+    input:
+      bytes: [ 0xa5, 0x02, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "iilh %r0, 0"
+  -
+    input:
+      bytes: [ 0xa5, 0x02, 0x80, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "iilh %r0, 32768"
+  -
+    input:
+      bytes: [ 0xa5, 0x02, 0xff, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "iilh %r0, 65535"
+  -
+    input:
+      bytes: [ 0xa5, 0xf2, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "iilh %r15, 0"
+  -
+    input:
+      bytes: [ 0xa5, 0x03, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "iill %r0, 0"
+  -
+    input:
+      bytes: [ 0xa5, 0x03, 0x80, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "iill %r0, 32768"
+  -
+    input:
+      bytes: [ 0xa5, 0x03, 0xff, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "iill %r0, 65535"
+  -
+    input:
+      bytes: [ 0xa5, 0xf3, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "iill %r15, 0"
+  -
+    input:
+      bytes: [ 0xb2, 0x22, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ipm %r0"
+  -
+    input:
+      bytes: [ 0xb2, 0x22, 0x00, 0x10 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ipm %r1"
+  -
+    input:
+      bytes: [ 0xb2, 0x22, 0x00, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ipm %r15"
+  -
+    input:
+      bytes: [ 0x58, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "l %r0, 0"
+  -
+    input:
+      bytes: [ 0x58, 0x00, 0x0f, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "l %r0, 4095"
+  -
+    input:
+      bytes: [ 0x58, 0x00, 0x10, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "l %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0x58, 0x00, 0xf0, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "l %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0x58, 0x01, 0xff, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "l %r0, 4095(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0x58, 0x0f, 0x1f, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "l %r0, 4095(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0x58, 0xf0, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "l %r15, 0"
+  -
+    input:
+      bytes: [ 0x41, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "la %r0, 0"
+  -
+    input:
+      bytes: [ 0x41, 0x00, 0x0f, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "la %r0, 4095"
+  -
+    input:
+      bytes: [ 0x41, 0x00, 0x10, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "la %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0x41, 0x00, 0xf0, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "la %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0x41, 0x01, 0xff, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "la %r0, 4095(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0x41, 0x0f, 0x1f, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "la %r0, 4095(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0x41, 0xf0, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "la %r15, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x71 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lay %r0, -524288"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x71 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lay %r0, -1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x71 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lay %r0, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x71 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lay %r0, 1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x71 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lay %r0, 524287"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x71 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lay %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x71 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lay %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x71 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lay %r0, 524287(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x71 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lay %r0, 524287(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x71 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lay %r15, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x76 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lb %r0, -524288"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x76 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lb %r0, -1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x76 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lb %r0, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x76 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lb %r0, 1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x76 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lb %r0, 524287"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x76 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lb %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x76 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lb %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x76 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lb %r0, 524287(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x76 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lb %r0, 524287(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x76 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lb %r15, 0"
+  -
+    input:
+      bytes: [ 0xb9, 0x26, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lbr %r0, %r15"
+  -
+    input:
+      bytes: [ 0xb9, 0x26, 0x00, 0x78 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lbr %r7, %r8"
+  -
+    input:
+      bytes: [ 0xb9, 0x26, 0x00, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lbr %r15, %r0"
+  -
+    input:
+      bytes: [ 0xb3, 0x13, 0x00, 0x09 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lcdbr %f0, %f9"
+  -
+    input:
+      bytes: [ 0xb3, 0x13, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lcdbr %f0, %f15"
+  -
+    input:
+      bytes: [ 0xb3, 0x13, 0x00, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lcdbr %f15, %f0"
+  -
+    input:
+      bytes: [ 0xb3, 0x13, 0x00, 0xf9 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lcdbr %f15, %f9"
+  -
+    input:
+      bytes: [ 0xb3, 0x03, 0x00, 0x09 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lcebr %f0, %f9"
+  -
+    input:
+      bytes: [ 0xb3, 0x03, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lcebr %f0, %f15"
+  -
+    input:
+      bytes: [ 0xb3, 0x03, 0x00, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lcebr %f15, %f0"
+  -
+    input:
+      bytes: [ 0xb3, 0x03, 0x00, 0xf9 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lcebr %f15, %f9"
+  -
+    input:
+      bytes: [ 0xb9, 0x13, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lcgfr %r0, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0x13, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lcgfr %r0, %r15"
+  -
+    input:
+      bytes: [ 0xb9, 0x13, 0x00, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lcgfr %r15, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0x13, 0x00, 0x78 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lcgfr %r7, %r8"
+  -
+    input:
+      bytes: [ 0xb9, 0x03, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lcgr %r0, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0x03, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lcgr %r0, %r15"
+  -
+    input:
+      bytes: [ 0xb9, 0x03, 0x00, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lcgr %r15, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0x03, 0x00, 0x78 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lcgr %r7, %r8"
+  -
+    input:
+      bytes: [ 0x13, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lcr %r0, %r0"
+  -
+    input:
+      bytes: [ 0x13, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lcr %r0, %r15"
+  -
+    input:
+      bytes: [ 0x13, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lcr %r15, %r0"
+  -
+    input:
+      bytes: [ 0x13, 0x78 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lcr %r7, %r8"
+  -
+    input:
+      bytes: [ 0xb3, 0x43, 0x00, 0x08 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lcxbr %f0, %f8"
+  -
+    input:
+      bytes: [ 0xb3, 0x43, 0x00, 0x0d ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lcxbr %f0, %f13"
+  -
+    input:
+      bytes: [ 0xb3, 0x43, 0x00, 0xd0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lcxbr %f13, %f0"
+  -
+    input:
+      bytes: [ 0xb3, 0x43, 0x00, 0xd9 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lcxbr %f13, %f9"
+  -
+    input:
+      bytes: [ 0x68, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ld %f0, 0"
+  -
+    input:
+      bytes: [ 0x68, 0x00, 0x0f, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ld %f0, 4095"
+  -
+    input:
+      bytes: [ 0x68, 0x00, 0x10, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ld %f0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0x68, 0x00, 0xf0, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ld %f0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0x68, 0x01, 0xff, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ld %f0, 4095(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0x68, 0x0f, 0x1f, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ld %f0, 4095(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0x68, 0xf0, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ld %f15, 0"
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ldeb %f0, 0"
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x00, 0x04 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ldeb %f0, 4095"
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ldeb %f0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ldeb %f0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xed, 0x01, 0xff, 0xff, 0x00, 0x04 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ldeb %f0, 4095(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x00, 0x04 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ldeb %f0, 4095(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0xed, 0xf0, 0x00, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ldeb %f15, 0"
+  -
+    input:
+      bytes: [ 0xb3, 0x04, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ldebr %f0, %f15"
+  -
+    input:
+      bytes: [ 0xb3, 0x04, 0x00, 0x78 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ldebr %f7, %f8"
+  -
+    input:
+      bytes: [ 0xb3, 0x04, 0x00, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ldebr %f15, %f0"
+  -
+    input:
+      bytes: [ 0xb3, 0xc1, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ldgr %f0, %r0"
+  -
+    input:
+      bytes: [ 0xb3, 0xc1, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ldgr %f0, %r15"
+  -
+    input:
+      bytes: [ 0xb3, 0xc1, 0x00, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ldgr %f15, %r0"
+  -
+    input:
+      bytes: [ 0xb3, 0xc1, 0x00, 0x79 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ldgr %f7, %r9"
+  -
+    input:
+      bytes: [ 0xb3, 0xc1, 0x00, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ldgr %f15, %r15"
+  -
+    input:
+      bytes: [ 0x28, 0x09 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr %f0, %f9"
+  -
+    input:
+      bytes: [ 0x28, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr %f0, %f15"
+  -
+    input:
+      bytes: [ 0x28, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr %f15, %f0"
+  -
+    input:
+      bytes: [ 0x28, 0xf9 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr %f15, %f9"
+  -
+    input:
+      bytes: [ 0xb3, 0x45, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ldxbr %f0, %f0"
+  -
+    input:
+      bytes: [ 0xb3, 0x45, 0x00, 0x0d ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ldxbr %f0, %f13"
+  -
+    input:
+      bytes: [ 0xb3, 0x45, 0x00, 0x8c ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ldxbr %f8, %f12"
+  -
+    input:
+      bytes: [ 0xb3, 0x45, 0x00, 0xd0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ldxbr %f13, %f0"
+  -
+    input:
+      bytes: [ 0xb3, 0x45, 0x00, 0xdd ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ldxbr %f13, %f13"
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0x00, 0x00, 0x80, 0x65 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ldy %f0, -524288"
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0x0f, 0xff, 0xff, 0x65 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ldy %f0, -1"
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x65 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ldy %f0, 0"
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0x00, 0x01, 0x00, 0x65 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ldy %f0, 1"
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x7f, 0x65 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ldy %f0, 524287"
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x65 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ldy %f0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x65 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ldy %f0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xed, 0x01, 0xff, 0xff, 0x7f, 0x65 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ldy %f0, 524287(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x7f, 0x65 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ldy %f0, 524287(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0xed, 0xf0, 0x00, 0x00, 0x00, 0x65 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ldy %f15, 0"
+  -
+    input:
+      bytes: [ 0x78, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "le %f0, 0"
+  -
+    input:
+      bytes: [ 0x78, 0x00, 0x0f, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "le %f0, 4095"
+  -
+    input:
+      bytes: [ 0x78, 0x00, 0x10, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "le %f0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0x78, 0x00, 0xf0, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "le %f0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0x78, 0x01, 0xff, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "le %f0, 4095(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0x78, 0x0f, 0x1f, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "le %f0, 4095(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0x78, 0xf0, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "le %f15, 0"
+  -
+    input:
+      bytes: [ 0xb3, 0x44, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ledbr %f0, %f0"
+  -
+    input:
+      bytes: [ 0xb3, 0x44, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ledbr %f0, %f15"
+  -
+    input:
+      bytes: [ 0xb3, 0x44, 0x00, 0x78 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ledbr %f7, %f8"
+  -
+    input:
+      bytes: [ 0xb3, 0x44, 0x00, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ledbr %f15, %f0"
+  -
+    input:
+      bytes: [ 0xb3, 0x44, 0x00, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ledbr %f15, %f15"
+  -
+    input:
+      bytes: [ 0x38, 0x09 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ler %f0, %f9"
+  -
+    input:
+      bytes: [ 0x38, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ler %f0, %f15"
+  -
+    input:
+      bytes: [ 0x38, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ler %f15, %f0"
+  -
+    input:
+      bytes: [ 0x38, 0xf9 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ler %f15, %f9"
+  -
+    input:
+      bytes: [ 0xb3, 0x46, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lexbr %f0, %f0"
+  -
+    input:
+      bytes: [ 0xb3, 0x46, 0x00, 0x0d ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lexbr %f0, %f13"
+  -
+    input:
+      bytes: [ 0xb3, 0x46, 0x00, 0x8c ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lexbr %f8, %f12"
+  -
+    input:
+      bytes: [ 0xb3, 0x46, 0x00, 0xd0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lexbr %f13, %f0"
+  -
+    input:
+      bytes: [ 0xb3, 0x46, 0x00, 0xdd ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lexbr %f13, %f13"
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0x00, 0x00, 0x80, 0x64 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ley %f0, -524288"
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0x0f, 0xff, 0xff, 0x64 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ley %f0, -1"
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x64 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ley %f0, 0"
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0x00, 0x01, 0x00, 0x64 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ley %f0, 1"
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x7f, 0x64 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ley %f0, 524287"
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x64 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ley %f0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x64 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ley %f0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xed, 0x01, 0xff, 0xff, 0x7f, 0x64 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ley %f0, 524287(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x7f, 0x64 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ley %f0, 524287(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0xed, 0xf0, 0x00, 0x00, 0x00, 0x64 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ley %f15, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x04 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lg %r0, -524288"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x04 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lg %r0, -1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lg %r0, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x04 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lg %r0, 1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x04 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lg %r0, 524287"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lg %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lg %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x04 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lg %r0, 524287(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x04 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lg %r0, 524287(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lg %r15, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x77 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lgb %r0, -524288"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x77 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lgb %r0, -1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x77 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lgb %r0, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x77 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lgb %r0, 1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x77 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lgb %r0, 524287"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x77 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lgb %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x77 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lgb %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x77 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lgb %r0, 524287(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x77 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lgb %r0, 524287(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x77 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lgb %r15, 0"
+  -
+    input:
+      bytes: [ 0xb9, 0x06, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lgbr %r0, %r15"
+  -
+    input:
+      bytes: [ 0xb9, 0x06, 0x00, 0x78 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lgbr %r7, %r8"
+  -
+    input:
+      bytes: [ 0xb9, 0x06, 0x00, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lgbr %r15, %r0"
+  -
+    input:
+      bytes: [ 0xb3, 0xcd, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lgdr %r0, %f0"
+  -
+    input:
+      bytes: [ 0xb3, 0xcd, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lgdr %r0, %f15"
+  -
+    input:
+      bytes: [ 0xb3, 0xcd, 0x00, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lgdr %r15, %f0"
+  -
+    input:
+      bytes: [ 0xb3, 0xcd, 0x00, 0x88 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lgdr %r8, %f8"
+  -
+    input:
+      bytes: [ 0xb3, 0xcd, 0x00, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lgdr %r15, %f15"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x14 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lgf %r0, -524288"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x14 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lgf %r0, -1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x14 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lgf %r0, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x14 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lgf %r0, 1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x14 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lgf %r0, 524287"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x14 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lgf %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x14 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lgf %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x14 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lgf %r0, 524287(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x14 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lgf %r0, 524287(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x14 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lgf %r15, 0"
+  -
+    input:
+      bytes: [ 0xc0, 0x01, 0x80, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lgfi %r0, -2147483648"
+  -
+    input:
+      bytes: [ 0xc0, 0x01, 0xff, 0xff, 0xff, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lgfi %r0, -1"
+  -
+    input:
+      bytes: [ 0xc0, 0x01, 0x00, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lgfi %r0, 0"
+  -
+    input:
+      bytes: [ 0xc0, 0x01, 0x00, 0x00, 0x00, 0x01 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lgfi %r0, 1"
+  -
+    input:
+      bytes: [ 0xc0, 0x01, 0x7f, 0xff, 0xff, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lgfi %r0, 2147483647"
+  -
+    input:
+      bytes: [ 0xc0, 0xf1, 0x00, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lgfi %r15, 0"
+  -
+    input:
+      bytes: [ 0xb9, 0x14, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lgfr %r0, %r15"
+  -
+    input:
+      bytes: [ 0xb9, 0x14, 0x00, 0x78 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lgfr %r7, %r8"
+  -
+    input:
+      bytes: [ 0xb9, 0x14, 0x00, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lgfr %r15, %r0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x15 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lgh %r0, -524288"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x15 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lgh %r0, -1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x15 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lgh %r0, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x15 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lgh %r0, 1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x15 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lgh %r0, 524287"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x15 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lgh %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x15 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lgh %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x15 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lgh %r0, 524287(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x15 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lgh %r0, 524287(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x15 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lgh %r15, 0"
+  -
+    input:
+      bytes: [ 0xa7, 0x09, 0x80, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lghi %r0, -32768"
+  -
+    input:
+      bytes: [ 0xa7, 0x09, 0xff, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lghi %r0, -1"
+  -
+    input:
+      bytes: [ 0xa7, 0x09, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lghi %r0, 0"
+  -
+    input:
+      bytes: [ 0xa7, 0x09, 0x00, 0x01 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lghi %r0, 1"
+  -
+    input:
+      bytes: [ 0xa7, 0x09, 0x7f, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lghi %r0, 32767"
+  -
+    input:
+      bytes: [ 0xa7, 0xf9, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lghi %r15, 0"
+  -
+    input:
+      bytes: [ 0xb9, 0x07, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lghr %r0, %r15"
+  -
+    input:
+      bytes: [ 0xb9, 0x07, 0x00, 0x78 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lghr %r7, %r8"
+  -
+    input:
+      bytes: [ 0xb9, 0x07, 0x00, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lghr %r15, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0x04, 0x00, 0x09 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lgr %r0, %r9"
+  -
+    input:
+      bytes: [ 0xb9, 0x04, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lgr %r0, %r15"
+  -
+    input:
+      bytes: [ 0xb9, 0x04, 0x00, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lgr %r15, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0x04, 0x00, 0xf9 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lgr %r15, %r9"
+  -
+    input:
+      bytes: [ 0x48, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lh %r0, 0"
+  -
+    input:
+      bytes: [ 0x48, 0x00, 0x0f, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lh %r0, 4095"
+  -
+    input:
+      bytes: [ 0x48, 0x00, 0x10, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lh %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0x48, 0x00, 0xf0, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lh %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0x48, 0x01, 0xff, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lh %r0, 4095(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0x48, 0x0f, 0x1f, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lh %r0, 4095(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0x48, 0xf0, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lh %r15, 0"
+  -
+    input:
+      bytes: [ 0xa7, 0x08, 0x80, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lhi %r0, -32768"
+  -
+    input:
+      bytes: [ 0xa7, 0x08, 0xff, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lhi %r0, -1"
+  -
+    input:
+      bytes: [ 0xa7, 0x08, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lhi %r0, 0"
+  -
+    input:
+      bytes: [ 0xa7, 0x08, 0x00, 0x01 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lhi %r0, 1"
+  -
+    input:
+      bytes: [ 0xa7, 0x08, 0x7f, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lhi %r0, 32767"
+  -
+    input:
+      bytes: [ 0xa7, 0xf8, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lhi %r15, 0"
+  -
+    input:
+      bytes: [ 0xb9, 0x27, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lhr %r0, %r15"
+  -
+    input:
+      bytes: [ 0xb9, 0x27, 0x00, 0x78 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lhr %r7, %r8"
+  -
+    input:
+      bytes: [ 0xb9, 0x27, 0x00, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lhr %r15, %r0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x78 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lhy %r0, -524288"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x78 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lhy %r0, -1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x78 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lhy %r0, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x78 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lhy %r0, 1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x78 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lhy %r0, 524287"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x78 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lhy %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x78 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lhy %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x78 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lhy %r0, 524287(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x78 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lhy %r0, 524287(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x78 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lhy %r15, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x94 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "llc %r0, -524288"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x94 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "llc %r0, -1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x94 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "llc %r0, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x94 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "llc %r0, 1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x94 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "llc %r0, 524287"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x94 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "llc %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x94 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "llc %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x94 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "llc %r0, 524287(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x94 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "llc %r0, 524287(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x94 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "llc %r15, 0"
+  -
+    input:
+      bytes: [ 0xb9, 0x94, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "llcr %r0, %r15"
+  -
+    input:
+      bytes: [ 0xb9, 0x94, 0x00, 0x78 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "llcr %r7, %r8"
+  -
+    input:
+      bytes: [ 0xb9, 0x94, 0x00, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "llcr %r15, %r0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x90 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "llgc %r0, -524288"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x90 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "llgc %r0, -1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x90 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "llgc %r0, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x90 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "llgc %r0, 1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x90 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "llgc %r0, 524287"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x90 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "llgc %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x90 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "llgc %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x90 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "llgc %r0, 524287(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x90 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "llgc %r0, 524287(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x90 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "llgc %r15, 0"
+  -
+    input:
+      bytes: [ 0xb9, 0x84, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "llgcr %r0, %r15"
+  -
+    input:
+      bytes: [ 0xb9, 0x84, 0x00, 0x78 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "llgcr %r7, %r8"
+  -
+    input:
+      bytes: [ 0xb9, 0x84, 0x00, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "llgcr %r15, %r0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x16 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "llgf %r0, -524288"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x16 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "llgf %r0, -1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x16 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "llgf %r0, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x16 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "llgf %r0, 1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x16 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "llgf %r0, 524287"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x16 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "llgf %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x16 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "llgf %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x16 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "llgf %r0, 524287(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x16 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "llgf %r0, 524287(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x16 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "llgf %r15, 0"
+  -
+    input:
+      bytes: [ 0xb9, 0x16, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "llgfr %r0, %r15"
+  -
+    input:
+      bytes: [ 0xb9, 0x16, 0x00, 0x78 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "llgfr %r7, %r8"
+  -
+    input:
+      bytes: [ 0xb9, 0x16, 0x00, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "llgfr %r15, %r0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x91 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "llgh %r0, -524288"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x91 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "llgh %r0, -1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x91 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "llgh %r0, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x91 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "llgh %r0, 1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x91 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "llgh %r0, 524287"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x91 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "llgh %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x91 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "llgh %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x91 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "llgh %r0, 524287(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x91 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "llgh %r0, 524287(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x91 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "llgh %r15, 0"
+  -
+    input:
+      bytes: [ 0xb9, 0x85, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "llghr %r0, %r15"
+  -
+    input:
+      bytes: [ 0xb9, 0x85, 0x00, 0x78 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "llghr %r7, %r8"
+  -
+    input:
+      bytes: [ 0xb9, 0x85, 0x00, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "llghr %r15, %r0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x95 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "llh %r0, -524288"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x95 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "llh %r0, -1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x95 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "llh %r0, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x95 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "llh %r0, 1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x95 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "llh %r0, 524287"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x95 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "llh %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x95 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "llh %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x95 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "llh %r0, 524287(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x95 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "llh %r0, 524287(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x95 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "llh %r15, 0"
+  -
+    input:
+      bytes: [ 0xb9, 0x95, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "llhr %r0, %r15"
+  -
+    input:
+      bytes: [ 0xb9, 0x95, 0x00, 0x78 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "llhr %r7, %r8"
+  -
+    input:
+      bytes: [ 0xb9, 0x95, 0x00, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "llhr %r15, %r0"
+  -
+    input:
+      bytes: [ 0xc0, 0x0e, 0x00, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "llihf %r0, 0"
+  -
+    input:
+      bytes: [ 0xc0, 0x0e, 0xff, 0xff, 0xff, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "llihf %r0, 4294967295"
+  -
+    input:
+      bytes: [ 0xc0, 0xfe, 0x00, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "llihf %r15, 0"
+  -
+    input:
+      bytes: [ 0xa5, 0x0c, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "llihh %r0, 0"
+  -
+    input:
+      bytes: [ 0xa5, 0x0c, 0x80, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "llihh %r0, 32768"
+  -
+    input:
+      bytes: [ 0xa5, 0x0c, 0xff, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "llihh %r0, 65535"
+  -
+    input:
+      bytes: [ 0xa5, 0xfc, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "llihh %r15, 0"
+  -
+    input:
+      bytes: [ 0xa5, 0x0d, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "llihl %r0, 0"
+  -
+    input:
+      bytes: [ 0xa5, 0x0d, 0x80, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "llihl %r0, 32768"
+  -
+    input:
+      bytes: [ 0xa5, 0x0d, 0xff, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "llihl %r0, 65535"
+  -
+    input:
+      bytes: [ 0xa5, 0xfd, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "llihl %r15, 0"
+  -
+    input:
+      bytes: [ 0xc0, 0x0f, 0x00, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "llilf %r0, 0"
+  -
+    input:
+      bytes: [ 0xc0, 0x0f, 0xff, 0xff, 0xff, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "llilf %r0, 4294967295"
+  -
+    input:
+      bytes: [ 0xc0, 0xff, 0x00, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "llilf %r15, 0"
+  -
+    input:
+      bytes: [ 0xa5, 0x0e, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "llilh %r0, 0"
+  -
+    input:
+      bytes: [ 0xa5, 0x0e, 0x80, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "llilh %r0, 32768"
+  -
+    input:
+      bytes: [ 0xa5, 0x0e, 0xff, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "llilh %r0, 65535"
+  -
+    input:
+      bytes: [ 0xa5, 0xfe, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "llilh %r15, 0"
+  -
+    input:
+      bytes: [ 0xa5, 0x0f, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "llill %r0, 0"
+  -
+    input:
+      bytes: [ 0xa5, 0x0f, 0x80, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "llill %r0, 32768"
+  -
+    input:
+      bytes: [ 0xa5, 0x0f, 0xff, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "llill %r0, 65535"
+  -
+    input:
+      bytes: [ 0xa5, 0xff, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "llill %r15, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lmg %r0, %r0, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0x0f, 0x00, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lmg %r0, %r15, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0xef, 0x00, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lmg %r14, %r15, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0xff, 0x00, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lmg %r15, %r15, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0x04 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lmg %r0, %r0, -524288"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0x04 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lmg %r0, %r0, -1"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lmg %r0, %r0, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0x04 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lmg %r0, %r0, 1"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0x04 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lmg %r0, %r0, 524287"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lmg %r0, %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lmg %r0, %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x1f, 0xff, 0x7f, 0x04 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lmg %r0, %r0, 524287(%r1)"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0xff, 0xff, 0x7f, 0x04 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lmg %r0, %r0, 524287(%r15)"
+  -
+    input:
+      bytes: [ 0xb3, 0x11, 0x00, 0x09 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lndbr %f0, %f9"
+  -
+    input:
+      bytes: [ 0xb3, 0x11, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lndbr %f0, %f15"
+  -
+    input:
+      bytes: [ 0xb3, 0x11, 0x00, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lndbr %f15, %f0"
+  -
+    input:
+      bytes: [ 0xb3, 0x11, 0x00, 0xf9 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lndbr %f15, %f9"
+  -
+    input:
+      bytes: [ 0xb3, 0x01, 0x00, 0x09 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lnebr %f0, %f9"
+  -
+    input:
+      bytes: [ 0xb3, 0x01, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lnebr %f0, %f15"
+  -
+    input:
+      bytes: [ 0xb3, 0x01, 0x00, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lnebr %f15, %f0"
+  -
+    input:
+      bytes: [ 0xb3, 0x01, 0x00, 0xf9 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lnebr %f15, %f9"
+  -
+    input:
+      bytes: [ 0xb9, 0x11, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lngfr %r0, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0x11, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lngfr %r0, %r15"
+  -
+    input:
+      bytes: [ 0xb9, 0x11, 0x00, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lngfr %r15, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0x11, 0x00, 0x78 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lngfr %r7, %r8"
+  -
+    input:
+      bytes: [ 0xb9, 0x01, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lngr %r0, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0x01, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lngr %r0, %r15"
+  -
+    input:
+      bytes: [ 0xb9, 0x01, 0x00, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lngr %r15, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0x01, 0x00, 0x78 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lngr %r7, %r8"
+  -
+    input:
+      bytes: [ 0x11, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lnr %r0, %r0"
+  -
+    input:
+      bytes: [ 0x11, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lnr %r0, %r15"
+  -
+    input:
+      bytes: [ 0x11, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lnr %r15, %r0"
+  -
+    input:
+      bytes: [ 0x11, 0x78 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lnr %r7, %r8"
+  -
+    input:
+      bytes: [ 0xb3, 0x41, 0x00, 0x08 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lnxbr %f0, %f8"
+  -
+    input:
+      bytes: [ 0xb3, 0x41, 0x00, 0x0d ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lnxbr %f0, %f13"
+  -
+    input:
+      bytes: [ 0xb3, 0x41, 0x00, 0xd0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lnxbr %f13, %f0"
+  -
+    input:
+      bytes: [ 0xb3, 0x41, 0x00, 0xd9 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lnxbr %f13, %f9"
+  -
+    input:
+      bytes: [ 0xb3, 0x10, 0x00, 0x09 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lpdbr %f0, %f9"
+  -
+    input:
+      bytes: [ 0xb3, 0x10, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lpdbr %f0, %f15"
+  -
+    input:
+      bytes: [ 0xb3, 0x10, 0x00, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lpdbr %f15, %f0"
+  -
+    input:
+      bytes: [ 0xb3, 0x10, 0x00, 0xf9 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lpdbr %f15, %f9"
+  -
+    input:
+      bytes: [ 0xb3, 0x00, 0x00, 0x09 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lpebr %f0, %f9"
+  -
+    input:
+      bytes: [ 0xb3, 0x00, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lpebr %f0, %f15"
+  -
+    input:
+      bytes: [ 0xb3, 0x00, 0x00, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lpebr %f15, %f0"
+  -
+    input:
+      bytes: [ 0xb3, 0x00, 0x00, 0xf9 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lpebr %f15, %f9"
+  -
+    input:
+      bytes: [ 0xb9, 0x10, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lpgfr %r0, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0x10, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lpgfr %r0, %r15"
+  -
+    input:
+      bytes: [ 0xb9, 0x10, 0x00, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lpgfr %r15, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0x10, 0x00, 0x78 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lpgfr %r7, %r8"
+  -
+    input:
+      bytes: [ 0xb9, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lpgr %r0, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0x00, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lpgr %r0, %r15"
+  -
+    input:
+      bytes: [ 0xb9, 0x00, 0x00, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lpgr %r15, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0x00, 0x00, 0x78 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lpgr %r7, %r8"
+  -
+    input:
+      bytes: [ 0x10, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lpr %r0, %r0"
+  -
+    input:
+      bytes: [ 0x10, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lpr %r0, %r15"
+  -
+    input:
+      bytes: [ 0x10, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lpr %r15, %r0"
+  -
+    input:
+      bytes: [ 0x10, 0x78 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lpr %r7, %r8"
+  -
+    input:
+      bytes: [ 0xb3, 0x40, 0x00, 0x08 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lpxbr %f0, %f8"
+  -
+    input:
+      bytes: [ 0xb3, 0x40, 0x00, 0x0d ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lpxbr %f0, %f13"
+  -
+    input:
+      bytes: [ 0xb3, 0x40, 0x00, 0xd0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lpxbr %f13, %f0"
+  -
+    input:
+      bytes: [ 0xb3, 0x40, 0x00, 0xd9 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lpxbr %f13, %f9"
+  -
+    input:
+      bytes: [ 0x18, 0x09 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lr %r0, %r9"
+  -
+    input:
+      bytes: [ 0x18, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lr %r0, %r15"
+  -
+    input:
+      bytes: [ 0x18, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lr %r15, %r0"
+  -
+    input:
+      bytes: [ 0x18, 0xf9 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lr %r15, %r9"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x1e ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lrv %r0, -524288"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x1e ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lrv %r0, -1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x1e ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lrv %r0, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x1e ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lrv %r0, 1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x1e ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lrv %r0, 524287"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x1e ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lrv %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x1e ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lrv %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x1e ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lrv %r0, 524287(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x1e ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lrv %r0, 524287(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x1e ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lrv %r15, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lrvg %r0, -524288"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lrvg %r0, -1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lrvg %r0, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lrvg %r0, 1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lrvg %r0, 524287"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lrvg %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lrvg %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lrvg %r0, 524287(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lrvg %r0, 524287(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lrvg %r15, 0"
+  -
+    input:
+      bytes: [ 0xb9, 0x0f, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lrvgr %r0, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0x0f, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lrvgr %r0, %r15"
+  -
+    input:
+      bytes: [ 0xb9, 0x0f, 0x00, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lrvgr %r15, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0x0f, 0x00, 0x78 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lrvgr %r7, %r8"
+  -
+    input:
+      bytes: [ 0xb9, 0x0f, 0x00, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lrvgr %r15, %r15"
+  -
+    input:
+      bytes: [ 0xb9, 0x1f, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lrvr %r0, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0x1f, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lrvr %r0, %r15"
+  -
+    input:
+      bytes: [ 0xb9, 0x1f, 0x00, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lrvr %r15, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0x1f, 0x00, 0x78 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lrvr %r7, %r8"
+  -
+    input:
+      bytes: [ 0xb9, 0x1f, 0x00, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lrvr %r15, %r15"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x12 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lt %r0, -524288"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x12 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lt %r0, -1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x12 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lt %r0, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x12 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lt %r0, 1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x12 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lt %r0, 524287"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x12 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lt %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x12 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lt %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x12 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lt %r0, 524287(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x12 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lt %r0, 524287(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x12 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lt %r15, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x02 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ltg %r0, -524288"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x02 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ltg %r0, -1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x02 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ltg %r0, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x02 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ltg %r0, 1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x02 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ltg %r0, 524287"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x02 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ltg %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x02 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ltg %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x02 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ltg %r0, 524287(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x02 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ltg %r0, 524287(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x02 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ltg %r15, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x32 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ltgf %r0, -524288"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x32 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ltgf %r0, -1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x32 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ltgf %r0, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x32 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ltgf %r0, 1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x32 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ltgf %r0, 524287"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x32 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ltgf %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x32 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ltgf %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x32 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ltgf %r0, 524287(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x32 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ltgf %r0, 524287(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x32 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ltgf %r15, 0"
+  -
+    input:
+      bytes: [ 0xb3, 0x12, 0x00, 0x09 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ltdbr %f0, %f9"
+  -
+    input:
+      bytes: [ 0xb3, 0x12, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ltdbr %f0, %f15"
+  -
+    input:
+      bytes: [ 0xb3, 0x12, 0x00, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ltdbr %f15, %f0"
+  -
+    input:
+      bytes: [ 0xb3, 0x12, 0x00, 0xf9 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ltdbr %f15, %f9"
+  -
+    input:
+      bytes: [ 0xb3, 0x02, 0x00, 0x09 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ltebr %f0, %f9"
+  -
+    input:
+      bytes: [ 0xb3, 0x02, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ltebr %f0, %f15"
+  -
+    input:
+      bytes: [ 0xb3, 0x02, 0x00, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ltebr %f15, %f0"
+  -
+    input:
+      bytes: [ 0xb3, 0x02, 0x00, 0xf9 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ltebr %f15, %f9"
+  -
+    input:
+      bytes: [ 0xb9, 0x12, 0x00, 0x09 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ltgfr %r0, %r9"
+  -
+    input:
+      bytes: [ 0xb9, 0x12, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ltgfr %r0, %r15"
+  -
+    input:
+      bytes: [ 0xb9, 0x12, 0x00, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ltgfr %r15, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0x12, 0x00, 0xf9 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ltgfr %r15, %r9"
+  -
+    input:
+      bytes: [ 0xb9, 0x02, 0x00, 0x09 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ltgr %r0, %r9"
+  -
+    input:
+      bytes: [ 0xb9, 0x02, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ltgr %r0, %r15"
+  -
+    input:
+      bytes: [ 0xb9, 0x02, 0x00, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ltgr %r15, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0x02, 0x00, 0xf9 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ltgr %r15, %r9"
+  -
+    input:
+      bytes: [ 0x12, 0x09 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ltr %r0, %r9"
+  -
+    input:
+      bytes: [ 0x12, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ltr %r0, %r15"
+  -
+    input:
+      bytes: [ 0x12, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ltr %r15, %r0"
+  -
+    input:
+      bytes: [ 0x12, 0xf9 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ltr %r15, %r9"
+  -
+    input:
+      bytes: [ 0xb3, 0x42, 0x00, 0x09 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ltxbr %f0, %f9"
+  -
+    input:
+      bytes: [ 0xb3, 0x42, 0x00, 0x0d ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ltxbr %f0, %f13"
+  -
+    input:
+      bytes: [ 0xb3, 0x42, 0x00, 0xd0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ltxbr %f13, %f0"
+  -
+    input:
+      bytes: [ 0xb3, 0x42, 0x00, 0xd9 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ltxbr %f13, %f9"
+  -
+    input:
+      bytes: [ 0xb3, 0x65, 0x00, 0x08 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lxr %f0, %f8"
+  -
+    input:
+      bytes: [ 0xb3, 0x65, 0x00, 0x0d ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lxr %f0, %f13"
+  -
+    input:
+      bytes: [ 0xb3, 0x65, 0x00, 0xd0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lxr %f13, %f0"
+  -
+    input:
+      bytes: [ 0xb3, 0x65, 0x00, 0xd9 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lxr %f13, %f9"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x58 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ly %r0, -524288"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x58 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ly %r0, -1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x58 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ly %r0, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x58 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ly %r0, 1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x58 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ly %r0, 524287"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x58 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ly %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x58 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ly %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x58 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ly %r0, 524287(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x58 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ly %r0, 524287(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x58 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ly %r15, 0"
+  -
+    input:
+      bytes: [ 0xb3, 0x75, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lzdr %f0"
+  -
+    input:
+      bytes: [ 0xb3, 0x75, 0x00, 0x70 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lzdr %f7"
+  -
+    input:
+      bytes: [ 0xb3, 0x75, 0x00, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lzdr %f15"
+  -
+    input:
+      bytes: [ 0xb3, 0x74, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lzer %f0"
+  -
+    input:
+      bytes: [ 0xb3, 0x74, 0x00, 0x70 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lzer %f7"
+  -
+    input:
+      bytes: [ 0xb3, 0x74, 0x00, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lzer %f15"
+  -
+    input:
+      bytes: [ 0xb3, 0x76, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lzxr %f0"
+  -
+    input:
+      bytes: [ 0xb3, 0x76, 0x00, 0x80 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lzxr %f8"
+  -
+    input:
+      bytes: [ 0xb3, 0x76, 0x00, 0xd0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lzxr %f13"
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x1e ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "madb %f0, %f0, 0"
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x00, 0x1e ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "madb %f0, %f0, 4095"
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x1e ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "madb %f0, %f0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x1e ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "madb %f0, %f0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xed, 0x01, 0xff, 0xff, 0x00, 0x1e ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "madb %f0, %f0, 4095(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x00, 0x1e ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "madb %f0, %f0, 4095(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0xed, 0xf0, 0x00, 0x00, 0x00, 0x1e ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "madb %f0, %f15, 0"
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0x00, 0x00, 0xf0, 0x1e ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "madb %f15, %f0, 0"
+  -
+    input:
+      bytes: [ 0xed, 0xf0, 0x00, 0x00, 0xf0, 0x1e ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "madb %f15, %f15, 0"
+  -
+    input:
+      bytes: [ 0xb3, 0x1e, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "madbr %f0, %f0, %f0"
+  -
+    input:
+      bytes: [ 0xb3, 0x1e, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "madbr %f0, %f0, %f15"
+  -
+    input:
+      bytes: [ 0xb3, 0x1e, 0x00, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "madbr %f0, %f15, %f0"
+  -
+    input:
+      bytes: [ 0xb3, 0x1e, 0xf0, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "madbr %f15, %f0, %f0"
+  -
+    input:
+      bytes: [ 0xb3, 0x1e, 0x70, 0x89 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "madbr %f7, %f8, %f9"
+  -
+    input:
+      bytes: [ 0xb3, 0x1e, 0xf0, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "madbr %f15, %f15, %f15"
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x0e ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "maeb %f0, %f0, 0"
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x00, 0x0e ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "maeb %f0, %f0, 4095"
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x0e ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "maeb %f0, %f0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x0e ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "maeb %f0, %f0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xed, 0x01, 0xff, 0xff, 0x00, 0x0e ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "maeb %f0, %f0, 4095(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x00, 0x0e ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "maeb %f0, %f0, 4095(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0xed, 0xf0, 0x00, 0x00, 0x00, 0x0e ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "maeb %f0, %f15, 0"
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0x00, 0x00, 0xf0, 0x0e ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "maeb %f15, %f0, 0"
+  -
+    input:
+      bytes: [ 0xed, 0xf0, 0x00, 0x00, 0xf0, 0x0e ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "maeb %f15, %f15, 0"
+  -
+    input:
+      bytes: [ 0xb3, 0x0e, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "maebr %f0, %f0, %f0"
+  -
+    input:
+      bytes: [ 0xb3, 0x0e, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "maebr %f0, %f0, %f15"
+  -
+    input:
+      bytes: [ 0xb3, 0x0e, 0x00, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "maebr %f0, %f15, %f0"
+  -
+    input:
+      bytes: [ 0xb3, 0x0e, 0xf0, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "maebr %f15, %f0, %f0"
+  -
+    input:
+      bytes: [ 0xb3, 0x0e, 0x70, 0x89 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "maebr %f7, %f8, %f9"
+  -
+    input:
+      bytes: [ 0xb3, 0x0e, 0xf0, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "maebr %f15, %f15, %f15"
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x1c ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mdb %f0, 0"
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x00, 0x1c ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mdb %f0, 4095"
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x1c ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mdb %f0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x1c ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mdb %f0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xed, 0x01, 0xff, 0xff, 0x00, 0x1c ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mdb %f0, 4095(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x00, 0x1c ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mdb %f0, 4095(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0xed, 0xf0, 0x00, 0x00, 0x00, 0x1c ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mdb %f15, 0"
+  -
+    input:
+      bytes: [ 0xb3, 0x1c, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mdbr %f0, %f0"
+  -
+    input:
+      bytes: [ 0xb3, 0x1c, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mdbr %f0, %f15"
+  -
+    input:
+      bytes: [ 0xb3, 0x1c, 0x00, 0x78 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mdbr %f7, %f8"
+  -
+    input:
+      bytes: [ 0xb3, 0x1c, 0x00, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mdbr %f15, %f0"
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x0c ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mdeb %f0, 0"
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x00, 0x0c ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mdeb %f0, 4095"
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x0c ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mdeb %f0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x0c ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mdeb %f0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xed, 0x01, 0xff, 0xff, 0x00, 0x0c ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mdeb %f0, 4095(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x00, 0x0c ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mdeb %f0, 4095(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0xed, 0xf0, 0x00, 0x00, 0x00, 0x0c ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mdeb %f15, 0"
+  -
+    input:
+      bytes: [ 0xb3, 0x0c, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mdebr %f0, %f0"
+  -
+    input:
+      bytes: [ 0xb3, 0x0c, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mdebr %f0, %f15"
+  -
+    input:
+      bytes: [ 0xb3, 0x0c, 0x00, 0x78 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mdebr %f7, %f8"
+  -
+    input:
+      bytes: [ 0xb3, 0x0c, 0x00, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mdebr %f15, %f0"
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x17 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "meeb %f0, 0"
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x00, 0x17 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "meeb %f0, 4095"
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x17 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "meeb %f0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x17 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "meeb %f0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xed, 0x01, 0xff, 0xff, 0x00, 0x17 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "meeb %f0, 4095(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x00, 0x17 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "meeb %f0, 4095(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0xed, 0xf0, 0x00, 0x00, 0x00, 0x17 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "meeb %f15, 0"
+  -
+    input:
+      bytes: [ 0xb3, 0x17, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "meebr %f0, %f0"
+  -
+    input:
+      bytes: [ 0xb3, 0x17, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "meebr %f0, %f15"
+  -
+    input:
+      bytes: [ 0xb3, 0x17, 0x00, 0x78 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "meebr %f7, %f8"
+  -
+    input:
+      bytes: [ 0xb3, 0x17, 0x00, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "meebr %f15, %f0"
+  -
+    input:
+      bytes: [ 0xa7, 0x0d, 0x80, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mghi %r0, -32768"
+  -
+    input:
+      bytes: [ 0xa7, 0x0d, 0xff, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mghi %r0, -1"
+  -
+    input:
+      bytes: [ 0xa7, 0x0d, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mghi %r0, 0"
+  -
+    input:
+      bytes: [ 0xa7, 0x0d, 0x00, 0x01 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mghi %r0, 1"
+  -
+    input:
+      bytes: [ 0xa7, 0x0d, 0x7f, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mghi %r0, 32767"
+  -
+    input:
+      bytes: [ 0xa7, 0xfd, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mghi %r15, 0"
+  -
+    input:
+      bytes: [ 0x4c, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mh %r0, 0"
+  -
+    input:
+      bytes: [ 0x4c, 0x00, 0x0f, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mh %r0, 4095"
+  -
+    input:
+      bytes: [ 0x4c, 0x00, 0x10, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mh %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0x4c, 0x00, 0xf0, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mh %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0x4c, 0x01, 0xff, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mh %r0, 4095(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0x4c, 0x0f, 0x1f, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mh %r0, 4095(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0x4c, 0xf0, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mh %r15, 0"
+  -
+    input:
+      bytes: [ 0xa7, 0x0c, 0x80, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mhi %r0, -32768"
+  -
+    input:
+      bytes: [ 0xa7, 0x0c, 0xff, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mhi %r0, -1"
+  -
+    input:
+      bytes: [ 0xa7, 0x0c, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mhi %r0, 0"
+  -
+    input:
+      bytes: [ 0xa7, 0x0c, 0x00, 0x01 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mhi %r0, 1"
+  -
+    input:
+      bytes: [ 0xa7, 0x0c, 0x7f, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mhi %r0, 32767"
+  -
+    input:
+      bytes: [ 0xa7, 0xfc, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mhi %r15, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x7c ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mhy %r0, -524288"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x7c ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mhy %r0, -1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x7c ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mhy %r0, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x7c ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mhy %r0, 1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x7c ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mhy %r0, 524287"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x7c ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mhy %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x7c ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mhy %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x7c ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mhy %r0, 524287(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x7c ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mhy %r0, 524287(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x7c ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mhy %r15, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x86 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mlg %r0, -524288"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x86 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mlg %r0, -1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x86 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mlg %r0, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x86 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mlg %r0, 1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x86 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mlg %r0, 524287"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x86 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mlg %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x86 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mlg %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x86 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mlg %r0, 524287(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x86 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mlg %r0, 524287(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0xe0, 0x00, 0x00, 0x00, 0x86 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mlg %r14, 0"
+  -
+    input:
+      bytes: [ 0xb9, 0x86, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mlgr %r0, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0x86, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mlgr %r0, %r15"
+  -
+    input:
+      bytes: [ 0xb9, 0x86, 0x00, 0xe0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mlgr %r14, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0x86, 0x00, 0x69 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mlgr %r6, %r9"
+  -
+    input:
+      bytes: [ 0x71, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ms %r0, 0"
+  -
+    input:
+      bytes: [ 0x71, 0x00, 0x0f, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ms %r0, 4095"
+  -
+    input:
+      bytes: [ 0x71, 0x00, 0x10, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ms %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0x71, 0x00, 0xf0, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ms %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0x71, 0x01, 0xff, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ms %r0, 4095(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0x71, 0x0f, 0x1f, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ms %r0, 4095(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0x71, 0xf0, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ms %r15, 0"
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x1f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "msdb %f0, %f0, 0"
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x00, 0x1f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "msdb %f0, %f0, 4095"
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x1f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "msdb %f0, %f0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x1f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "msdb %f0, %f0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xed, 0x01, 0xff, 0xff, 0x00, 0x1f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "msdb %f0, %f0, 4095(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x00, 0x1f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "msdb %f0, %f0, 4095(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0xed, 0xf0, 0x00, 0x00, 0x00, 0x1f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "msdb %f0, %f15, 0"
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0x00, 0x00, 0xf0, 0x1f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "msdb %f15, %f0, 0"
+  -
+    input:
+      bytes: [ 0xed, 0xf0, 0x00, 0x00, 0xf0, 0x1f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "msdb %f15, %f15, 0"
+  -
+    input:
+      bytes: [ 0xb3, 0x1f, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "msdbr %f0, %f0, %f0"
+  -
+    input:
+      bytes: [ 0xb3, 0x1f, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "msdbr %f0, %f0, %f15"
+  -
+    input:
+      bytes: [ 0xb3, 0x1f, 0x00, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "msdbr %f0, %f15, %f0"
+  -
+    input:
+      bytes: [ 0xb3, 0x1f, 0xf0, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "msdbr %f15, %f0, %f0"
+  -
+    input:
+      bytes: [ 0xb3, 0x1f, 0x70, 0x89 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "msdbr %f7, %f8, %f9"
+  -
+    input:
+      bytes: [ 0xb3, 0x1f, 0xf0, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "msdbr %f15, %f15, %f15"
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mseb %f0, %f0, 0"
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mseb %f0, %f0, 4095"
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mseb %f0, %f0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mseb %f0, %f0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xed, 0x01, 0xff, 0xff, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mseb %f0, %f0, 4095(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mseb %f0, %f0, 4095(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0xed, 0xf0, 0x00, 0x00, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mseb %f0, %f15, 0"
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0x00, 0x00, 0xf0, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mseb %f15, %f0, 0"
+  -
+    input:
+      bytes: [ 0xed, 0xf0, 0x00, 0x00, 0xf0, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mseb %f15, %f15, 0"
+  -
+    input:
+      bytes: [ 0xb3, 0x0f, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "msebr %f0, %f0, %f0"
+  -
+    input:
+      bytes: [ 0xb3, 0x0f, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "msebr %f0, %f0, %f15"
+  -
+    input:
+      bytes: [ 0xb3, 0x0f, 0x00, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "msebr %f0, %f15, %f0"
+  -
+    input:
+      bytes: [ 0xb3, 0x0f, 0xf0, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "msebr %f15, %f0, %f0"
+  -
+    input:
+      bytes: [ 0xb3, 0x0f, 0x70, 0x89 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "msebr %f7, %f8, %f9"
+  -
+    input:
+      bytes: [ 0xb3, 0x0f, 0xf0, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "msebr %f15, %f15, %f15"
+  -
+    input:
+      bytes: [ 0xc2, 0x01, 0x80, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "msfi %r0, -2147483648"
+  -
+    input:
+      bytes: [ 0xc2, 0x01, 0xff, 0xff, 0xff, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "msfi %r0, -1"
+  -
+    input:
+      bytes: [ 0xc2, 0x01, 0x00, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "msfi %r0, 0"
+  -
+    input:
+      bytes: [ 0xc2, 0x01, 0x00, 0x00, 0x00, 0x01 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "msfi %r0, 1"
+  -
+    input:
+      bytes: [ 0xc2, 0x01, 0x7f, 0xff, 0xff, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "msfi %r0, 2147483647"
+  -
+    input:
+      bytes: [ 0xc2, 0xf1, 0x00, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "msfi %r15, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x0c ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "msg %r0, -524288"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x0c ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "msg %r0, -1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x0c ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "msg %r0, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x0c ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "msg %r0, 1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x0c ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "msg %r0, 524287"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x0c ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "msg %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x0c ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "msg %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x0c ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "msg %r0, 524287(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x0c ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "msg %r0, 524287(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x0c ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "msg %r15, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x1c ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "msgf %r0, -524288"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x1c ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "msgf %r0, -1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x1c ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "msgf %r0, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x1c ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "msgf %r0, 1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x1c ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "msgf %r0, 524287"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x1c ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "msgf %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x1c ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "msgf %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x1c ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "msgf %r0, 524287(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x1c ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "msgf %r0, 524287(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x1c ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "msgf %r15, 0"
+  -
+    input:
+      bytes: [ 0xc2, 0x00, 0x80, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "msgfi %r0, -2147483648"
+  -
+    input:
+      bytes: [ 0xc2, 0x00, 0xff, 0xff, 0xff, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "msgfi %r0, -1"
+  -
+    input:
+      bytes: [ 0xc2, 0x00, 0x00, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "msgfi %r0, 0"
+  -
+    input:
+      bytes: [ 0xc2, 0x00, 0x00, 0x00, 0x00, 0x01 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "msgfi %r0, 1"
+  -
+    input:
+      bytes: [ 0xc2, 0x00, 0x7f, 0xff, 0xff, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "msgfi %r0, 2147483647"
+  -
+    input:
+      bytes: [ 0xc2, 0xf0, 0x00, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "msgfi %r15, 0"
+  -
+    input:
+      bytes: [ 0xb9, 0x1c, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "msgfr %r0, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0x1c, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "msgfr %r0, %r15"
+  -
+    input:
+      bytes: [ 0xb9, 0x1c, 0x00, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "msgfr %r15, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0x1c, 0x00, 0x78 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "msgfr %r7, %r8"
+  -
+    input:
+      bytes: [ 0xb9, 0x0c, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "msgr %r0, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0x0c, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "msgr %r0, %r15"
+  -
+    input:
+      bytes: [ 0xb9, 0x0c, 0x00, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "msgr %r15, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0x0c, 0x00, 0x78 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "msgr %r7, %r8"
+  -
+    input:
+      bytes: [ 0xb2, 0x52, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "msr %r0, %r0"
+  -
+    input:
+      bytes: [ 0xb2, 0x52, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "msr %r0, %r15"
+  -
+    input:
+      bytes: [ 0xb2, 0x52, 0x00, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "msr %r15, %r0"
+  -
+    input:
+      bytes: [ 0xb2, 0x52, 0x00, 0x78 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "msr %r7, %r8"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x51 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "msy %r0, -524288"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x51 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "msy %r0, -1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x51 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "msy %r0, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x51 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "msy %r0, 1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x51 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "msy %r0, 524287"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x51 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "msy %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x51 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "msy %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x51 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "msy %r0, 524287(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x51 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "msy %r0, 524287(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x51 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "msy %r15, 0"
+  -
+    input:
+      bytes: [ 0xd2, 0x00, 0x00, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mvc 0(1), 0"
+  -
+    input:
+      bytes: [ 0xd2, 0x00, 0x00, 0x00, 0x10, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mvc 0(1), 0(%r1)"
+  -
+    input:
+      bytes: [ 0xd2, 0x00, 0x00, 0x00, 0xf0, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mvc 0(1), 0(%r15)"
+  -
+    input:
+      bytes: [ 0xd2, 0x00, 0x00, 0x00, 0x0f, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mvc 0(1), 4095"
+  -
+    input:
+      bytes: [ 0xd2, 0x00, 0x00, 0x00, 0x1f, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mvc 0(1), 4095(%r1)"
+  -
+    input:
+      bytes: [ 0xd2, 0x00, 0x00, 0x00, 0xff, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mvc 0(1), 4095(%r15)"
+  -
+    input:
+      bytes: [ 0xd2, 0x00, 0x10, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mvc 0(1, %r1), 0"
+  -
+    input:
+      bytes: [ 0xd2, 0x00, 0xf0, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mvc 0(1, %r15), 0"
+  -
+    input:
+      bytes: [ 0xd2, 0x00, 0x1f, 0xff, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mvc 4095(1, %r1), 0"
+  -
+    input:
+      bytes: [ 0xd2, 0x00, 0xff, 0xff, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mvc 4095(1, %r15), 0"
+  -
+    input:
+      bytes: [ 0xd2, 0xff, 0x10, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mvc 0(256, %r1), 0"
+  -
+    input:
+      bytes: [ 0xd2, 0xff, 0xf0, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mvc 0(256, %r15), 0"
+  -
+    input:
+      bytes: [ 0xe5, 0x48, 0x00, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mvghi 0, 0"
+  -
+    input:
+      bytes: [ 0xe5, 0x48, 0x0f, 0xff, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mvghi 4095, 0"
+  -
+    input:
+      bytes: [ 0xe5, 0x48, 0x00, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mvghi 0, -32768"
+  -
+    input:
+      bytes: [ 0xe5, 0x48, 0x00, 0x00, 0xff, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mvghi 0, -1"
+  -
+    input:
+      bytes: [ 0xe5, 0x48, 0x00, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mvghi 0, 0"
+  -
+    input:
+      bytes: [ 0xe5, 0x48, 0x00, 0x00, 0x00, 0x01 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mvghi 0, 1"
+  -
+    input:
+      bytes: [ 0xe5, 0x48, 0x00, 0x00, 0x7f, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mvghi 0, 32767"
+  -
+    input:
+      bytes: [ 0xe5, 0x48, 0x10, 0x00, 0x00, 0x2a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mvghi 0(%r1), 42"
+  -
+    input:
+      bytes: [ 0xe5, 0x48, 0xf0, 0x00, 0x00, 0x2a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mvghi 0(%r15), 42"
+  -
+    input:
+      bytes: [ 0xe5, 0x48, 0x1f, 0xff, 0x00, 0x2a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mvghi 4095(%r1), 42"
+  -
+    input:
+      bytes: [ 0xe5, 0x48, 0xff, 0xff, 0x00, 0x2a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mvghi 4095(%r15), 42"
+  -
+    input:
+      bytes: [ 0xe5, 0x44, 0x00, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mvhhi 0, 0"
+  -
+    input:
+      bytes: [ 0xe5, 0x44, 0x0f, 0xff, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mvhhi 4095, 0"
+  -
+    input:
+      bytes: [ 0xe5, 0x44, 0x00, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mvhhi 0, -32768"
+  -
+    input:
+      bytes: [ 0xe5, 0x44, 0x00, 0x00, 0xff, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mvhhi 0, -1"
+  -
+    input:
+      bytes: [ 0xe5, 0x44, 0x00, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mvhhi 0, 0"
+  -
+    input:
+      bytes: [ 0xe5, 0x44, 0x00, 0x00, 0x00, 0x01 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mvhhi 0, 1"
+  -
+    input:
+      bytes: [ 0xe5, 0x44, 0x00, 0x00, 0x7f, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mvhhi 0, 32767"
+  -
+    input:
+      bytes: [ 0xe5, 0x44, 0x10, 0x00, 0x00, 0x2a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mvhhi 0(%r1), 42"
+  -
+    input:
+      bytes: [ 0xe5, 0x44, 0xf0, 0x00, 0x00, 0x2a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mvhhi 0(%r15), 42"
+  -
+    input:
+      bytes: [ 0xe5, 0x44, 0x1f, 0xff, 0x00, 0x2a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mvhhi 4095(%r1), 42"
+  -
+    input:
+      bytes: [ 0xe5, 0x44, 0xff, 0xff, 0x00, 0x2a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mvhhi 4095(%r15), 42"
+  -
+    input:
+      bytes: [ 0xe5, 0x4c, 0x00, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mvhi 0, 0"
+  -
+    input:
+      bytes: [ 0xe5, 0x4c, 0x0f, 0xff, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mvhi 4095, 0"
+  -
+    input:
+      bytes: [ 0xe5, 0x4c, 0x00, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mvhi 0, -32768"
+  -
+    input:
+      bytes: [ 0xe5, 0x4c, 0x00, 0x00, 0xff, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mvhi 0, -1"
+  -
+    input:
+      bytes: [ 0xe5, 0x4c, 0x00, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mvhi 0, 0"
+  -
+    input:
+      bytes: [ 0xe5, 0x4c, 0x00, 0x00, 0x00, 0x01 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mvhi 0, 1"
+  -
+    input:
+      bytes: [ 0xe5, 0x4c, 0x00, 0x00, 0x7f, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mvhi 0, 32767"
+  -
+    input:
+      bytes: [ 0xe5, 0x4c, 0x10, 0x00, 0x00, 0x2a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mvhi 0(%r1), 42"
+  -
+    input:
+      bytes: [ 0xe5, 0x4c, 0xf0, 0x00, 0x00, 0x2a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mvhi 0(%r15), 42"
+  -
+    input:
+      bytes: [ 0xe5, 0x4c, 0x1f, 0xff, 0x00, 0x2a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mvhi 4095(%r1), 42"
+  -
+    input:
+      bytes: [ 0xe5, 0x4c, 0xff, 0xff, 0x00, 0x2a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mvhi 4095(%r15), 42"
+  -
+    input:
+      bytes: [ 0x92, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mvi 0, 0"
+  -
+    input:
+      bytes: [ 0x92, 0x00, 0x0f, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mvi 4095, 0"
+  -
+    input:
+      bytes: [ 0x92, 0xff, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mvi 0, 255"
+  -
+    input:
+      bytes: [ 0x92, 0x2a, 0x10, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mvi 0(%r1), 42"
+  -
+    input:
+      bytes: [ 0x92, 0x2a, 0xf0, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mvi 0(%r15), 42"
+  -
+    input:
+      bytes: [ 0x92, 0x2a, 0x1f, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mvi 4095(%r1), 42"
+  -
+    input:
+      bytes: [ 0x92, 0x2a, 0xff, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mvi 4095(%r15), 42"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0x52 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mviy -524288, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0x52 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mviy -1, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0x52 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mviy 0, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0x52 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mviy 1, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0x52 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mviy 524287, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0xff, 0x00, 0x00, 0x00, 0x52 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mviy 0, 255"
+  -
+    input:
+      bytes: [ 0xeb, 0x2a, 0x10, 0x00, 0x00, 0x52 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mviy 0(%r1), 42"
+  -
+    input:
+      bytes: [ 0xeb, 0x2a, 0xf0, 0x00, 0x00, 0x52 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mviy 0(%r15), 42"
+  -
+    input:
+      bytes: [ 0xeb, 0x2a, 0x1f, 0xff, 0x7f, 0x52 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mviy 524287(%r1), 42"
+  -
+    input:
+      bytes: [ 0xeb, 0x2a, 0xff, 0xff, 0x7f, 0x52 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mviy 524287(%r15), 42"
+  -
+    input:
+      bytes: [ 0xb2, 0x55, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mvst %r0, %r0"
+  -
+    input:
+      bytes: [ 0xb2, 0x55, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mvst %r0, %r15"
+  -
+    input:
+      bytes: [ 0xb2, 0x55, 0x00, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mvst %r15, %r0"
+  -
+    input:
+      bytes: [ 0xb2, 0x55, 0x00, 0x78 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mvst %r7, %r8"
+  -
+    input:
+      bytes: [ 0xb3, 0x4c, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mxbr %f0, %f0"
+  -
+    input:
+      bytes: [ 0xb3, 0x4c, 0x00, 0x0d ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mxbr %f0, %f13"
+  -
+    input:
+      bytes: [ 0xb3, 0x4c, 0x00, 0x85 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mxbr %f8, %f5"
+  -
+    input:
+      bytes: [ 0xb3, 0x4c, 0x00, 0xdd ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mxbr %f13, %f13"
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x07 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mxdb %f0, 0"
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x00, 0x07 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mxdb %f0, 4095"
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x07 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mxdb %f0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x07 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mxdb %f0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xed, 0x01, 0xff, 0xff, 0x00, 0x07 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mxdb %f0, 4095(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x00, 0x07 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mxdb %f0, 4095(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0xed, 0xd0, 0x00, 0x00, 0x00, 0x07 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mxdb %f13, 0"
+  -
+    input:
+      bytes: [ 0xb3, 0x07, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mxdbr %f0, %f0"
+  -
+    input:
+      bytes: [ 0xb3, 0x07, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mxdbr %f0, %f15"
+  -
+    input:
+      bytes: [ 0xb3, 0x07, 0x00, 0x88 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mxdbr %f8, %f8"
+  -
+    input:
+      bytes: [ 0xb3, 0x07, 0x00, 0xd0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "mxdbr %f13, %f0"
+  -
+    input:
+      bytes: [ 0x54, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "n %r0, 0"
+  -
+    input:
+      bytes: [ 0x54, 0x00, 0x0f, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "n %r0, 4095"
+  -
+    input:
+      bytes: [ 0x54, 0x00, 0x10, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "n %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0x54, 0x00, 0xf0, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "n %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0x54, 0x01, 0xff, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "n %r0, 4095(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0x54, 0x0f, 0x1f, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "n %r0, 4095(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0x54, 0xf0, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "n %r15, 0"
+  -
+    input:
+      bytes: [ 0xd4, 0x00, 0x00, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "nc 0(1), 0"
+  -
+    input:
+      bytes: [ 0xd4, 0x00, 0x00, 0x00, 0x10, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "nc 0(1), 0(%r1)"
+  -
+    input:
+      bytes: [ 0xd4, 0x00, 0x00, 0x00, 0xf0, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "nc 0(1), 0(%r15)"
+  -
+    input:
+      bytes: [ 0xd4, 0x00, 0x00, 0x00, 0x0f, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "nc 0(1), 4095"
+  -
+    input:
+      bytes: [ 0xd4, 0x00, 0x00, 0x00, 0x1f, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "nc 0(1), 4095(%r1)"
+  -
+    input:
+      bytes: [ 0xd4, 0x00, 0x00, 0x00, 0xff, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "nc 0(1), 4095(%r15)"
+  -
+    input:
+      bytes: [ 0xd4, 0x00, 0x10, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "nc 0(1, %r1), 0"
+  -
+    input:
+      bytes: [ 0xd4, 0x00, 0xf0, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "nc 0(1, %r15), 0"
+  -
+    input:
+      bytes: [ 0xd4, 0x00, 0x1f, 0xff, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "nc 4095(1, %r1), 0"
+  -
+    input:
+      bytes: [ 0xd4, 0x00, 0xff, 0xff, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "nc 4095(1, %r15), 0"
+  -
+    input:
+      bytes: [ 0xd4, 0xff, 0x10, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "nc 0(256, %r1), 0"
+  -
+    input:
+      bytes: [ 0xd4, 0xff, 0xf0, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "nc 0(256, %r15), 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x80 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ng %r0, -524288"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x80 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ng %r0, -1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x80 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ng %r0, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x80 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ng %r0, 1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x80 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ng %r0, 524287"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x80 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ng %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x80 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ng %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x80 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ng %r0, 524287(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x80 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ng %r0, 524287(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x80 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ng %r15, 0"
+  -
+    input:
+      bytes: [ 0xb9, 0x80, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ngr %r0, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0x80, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ngr %r0, %r15"
+  -
+    input:
+      bytes: [ 0xb9, 0x80, 0x00, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ngr %r15, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0x80, 0x00, 0x78 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ngr %r7, %r8"
+  -
+    input:
+      bytes: [ 0x94, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ni 0, 0"
+  -
+    input:
+      bytes: [ 0x94, 0x00, 0x0f, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ni 4095, 0"
+  -
+    input:
+      bytes: [ 0x94, 0xff, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ni 0, 255"
+  -
+    input:
+      bytes: [ 0x94, 0x2a, 0x10, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ni 0(%r1), 42"
+  -
+    input:
+      bytes: [ 0x94, 0x2a, 0xf0, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ni 0(%r15), 42"
+  -
+    input:
+      bytes: [ 0x94, 0x2a, 0x1f, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ni 4095(%r1), 42"
+  -
+    input:
+      bytes: [ 0x94, 0x2a, 0xff, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ni 4095(%r15), 42"
+  -
+    input:
+      bytes: [ 0xc0, 0x0a, 0x00, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "nihf %r0, 0"
+  -
+    input:
+      bytes: [ 0xc0, 0x0a, 0xff, 0xff, 0xff, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "nihf %r0, 4294967295"
+  -
+    input:
+      bytes: [ 0xc0, 0xfa, 0x00, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "nihf %r15, 0"
+  -
+    input:
+      bytes: [ 0xa5, 0x04, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "nihh %r0, 0"
+  -
+    input:
+      bytes: [ 0xa5, 0x04, 0x80, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "nihh %r0, 32768"
+  -
+    input:
+      bytes: [ 0xa5, 0x04, 0xff, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "nihh %r0, 65535"
+  -
+    input:
+      bytes: [ 0xa5, 0xf4, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "nihh %r15, 0"
+  -
+    input:
+      bytes: [ 0xa5, 0x05, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "nihl %r0, 0"
+  -
+    input:
+      bytes: [ 0xa5, 0x05, 0x80, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "nihl %r0, 32768"
+  -
+    input:
+      bytes: [ 0xa5, 0x05, 0xff, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "nihl %r0, 65535"
+  -
+    input:
+      bytes: [ 0xa5, 0xf5, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "nihl %r15, 0"
+  -
+    input:
+      bytes: [ 0xc0, 0x0b, 0x00, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "nilf %r0, 0"
+  -
+    input:
+      bytes: [ 0xc0, 0x0b, 0xff, 0xff, 0xff, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "nilf %r0, 4294967295"
+  -
+    input:
+      bytes: [ 0xc0, 0xfb, 0x00, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "nilf %r15, 0"
+  -
+    input:
+      bytes: [ 0xa5, 0x06, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "nilh %r0, 0"
+  -
+    input:
+      bytes: [ 0xa5, 0x06, 0x80, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "nilh %r0, 32768"
+  -
+    input:
+      bytes: [ 0xa5, 0x06, 0xff, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "nilh %r0, 65535"
+  -
+    input:
+      bytes: [ 0xa5, 0xf6, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "nilh %r15, 0"
+  -
+    input:
+      bytes: [ 0xa5, 0x07, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "nill %r0, 0"
+  -
+    input:
+      bytes: [ 0xa5, 0x07, 0x80, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "nill %r0, 32768"
+  -
+    input:
+      bytes: [ 0xa5, 0x07, 0xff, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "nill %r0, 65535"
+  -
+    input:
+      bytes: [ 0xa5, 0xf7, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "nill %r15, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0x54 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "niy -524288, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0x54 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "niy -1, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0x54 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "niy 0, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0x54 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "niy 1, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0x54 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "niy 524287, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0xff, 0x00, 0x00, 0x00, 0x54 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "niy 0, 255"
+  -
+    input:
+      bytes: [ 0xeb, 0x2a, 0x10, 0x00, 0x00, 0x54 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "niy 0(%r1), 42"
+  -
+    input:
+      bytes: [ 0xeb, 0x2a, 0xf0, 0x00, 0x00, 0x54 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "niy 0(%r15), 42"
+  -
+    input:
+      bytes: [ 0xeb, 0x2a, 0x1f, 0xff, 0x7f, 0x54 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "niy 524287(%r1), 42"
+  -
+    input:
+      bytes: [ 0xeb, 0x2a, 0xff, 0xff, 0x7f, 0x54 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "niy 524287(%r15), 42"
+  -
+    input:
+      bytes: [ 0x14, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "nr %r0, %r0"
+  -
+    input:
+      bytes: [ 0x14, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "nr %r0, %r15"
+  -
+    input:
+      bytes: [ 0x14, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "nr %r15, %r0"
+  -
+    input:
+      bytes: [ 0x14, 0x78 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "nr %r7, %r8"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x54 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ny %r0, -524288"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x54 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ny %r0, -1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x54 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ny %r0, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x54 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ny %r0, 1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x54 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ny %r0, 524287"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x54 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ny %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x54 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ny %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x54 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ny %r0, 524287(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x54 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ny %r0, 524287(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x54 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ny %r15, 0"
+  -
+    input:
+      bytes: [ 0x56, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "o %r0, 0"
+  -
+    input:
+      bytes: [ 0x56, 0x00, 0x0f, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "o %r0, 4095"
+  -
+    input:
+      bytes: [ 0x56, 0x00, 0x10, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "o %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0x56, 0x00, 0xf0, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "o %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0x56, 0x01, 0xff, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "o %r0, 4095(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0x56, 0x0f, 0x1f, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "o %r0, 4095(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0x56, 0xf0, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "o %r15, 0"
+  -
+    input:
+      bytes: [ 0xd6, 0x00, 0x00, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "oc 0(1), 0"
+  -
+    input:
+      bytes: [ 0xd6, 0x00, 0x00, 0x00, 0x10, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "oc 0(1), 0(%r1)"
+  -
+    input:
+      bytes: [ 0xd6, 0x00, 0x00, 0x00, 0xf0, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "oc 0(1), 0(%r15)"
+  -
+    input:
+      bytes: [ 0xd6, 0x00, 0x00, 0x00, 0x0f, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "oc 0(1), 4095"
+  -
+    input:
+      bytes: [ 0xd6, 0x00, 0x00, 0x00, 0x1f, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "oc 0(1), 4095(%r1)"
+  -
+    input:
+      bytes: [ 0xd6, 0x00, 0x00, 0x00, 0xff, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "oc 0(1), 4095(%r15)"
+  -
+    input:
+      bytes: [ 0xd6, 0x00, 0x10, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "oc 0(1, %r1), 0"
+  -
+    input:
+      bytes: [ 0xd6, 0x00, 0xf0, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "oc 0(1, %r15), 0"
+  -
+    input:
+      bytes: [ 0xd6, 0x00, 0x1f, 0xff, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "oc 4095(1, %r1), 0"
+  -
+    input:
+      bytes: [ 0xd6, 0x00, 0xff, 0xff, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "oc 4095(1, %r15), 0"
+  -
+    input:
+      bytes: [ 0xd6, 0xff, 0x10, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "oc 0(256, %r1), 0"
+  -
+    input:
+      bytes: [ 0xd6, 0xff, 0xf0, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "oc 0(256, %r15), 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x81 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "og %r0, -524288"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x81 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "og %r0, -1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x81 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "og %r0, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x81 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "og %r0, 1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x81 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "og %r0, 524287"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x81 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "og %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x81 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "og %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x81 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "og %r0, 524287(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x81 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "og %r0, 524287(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x81 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "og %r15, 0"
+  -
+    input:
+      bytes: [ 0xb9, 0x81, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ogr %r0, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0x81, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ogr %r0, %r15"
+  -
+    input:
+      bytes: [ 0xb9, 0x81, 0x00, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ogr %r15, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0x81, 0x00, 0x78 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ogr %r7, %r8"
+  -
+    input:
+      bytes: [ 0x96, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "oi 0, 0"
+  -
+    input:
+      bytes: [ 0x96, 0x00, 0x0f, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "oi 4095, 0"
+  -
+    input:
+      bytes: [ 0x96, 0xff, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "oi 0, 255"
+  -
+    input:
+      bytes: [ 0x96, 0x2a, 0x10, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "oi 0(%r1), 42"
+  -
+    input:
+      bytes: [ 0x96, 0x2a, 0xf0, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "oi 0(%r15), 42"
+  -
+    input:
+      bytes: [ 0x96, 0x2a, 0x1f, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "oi 4095(%r1), 42"
+  -
+    input:
+      bytes: [ 0x96, 0x2a, 0xff, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "oi 4095(%r15), 42"
+  -
+    input:
+      bytes: [ 0xc0, 0x0c, 0x00, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "oihf %r0, 0"
+  -
+    input:
+      bytes: [ 0xc0, 0x0c, 0xff, 0xff, 0xff, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "oihf %r0, 4294967295"
+  -
+    input:
+      bytes: [ 0xc0, 0xfc, 0x00, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "oihf %r15, 0"
+  -
+    input:
+      bytes: [ 0xa5, 0x08, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "oihh %r0, 0"
+  -
+    input:
+      bytes: [ 0xa5, 0x08, 0x80, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "oihh %r0, 32768"
+  -
+    input:
+      bytes: [ 0xa5, 0x08, 0xff, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "oihh %r0, 65535"
+  -
+    input:
+      bytes: [ 0xa5, 0xf8, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "oihh %r15, 0"
+  -
+    input:
+      bytes: [ 0xa5, 0x09, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "oihl %r0, 0"
+  -
+    input:
+      bytes: [ 0xa5, 0x09, 0x80, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "oihl %r0, 32768"
+  -
+    input:
+      bytes: [ 0xa5, 0x09, 0xff, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "oihl %r0, 65535"
+  -
+    input:
+      bytes: [ 0xa5, 0xf9, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "oihl %r15, 0"
+  -
+    input:
+      bytes: [ 0xc0, 0x0d, 0x00, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "oilf %r0, 0"
+  -
+    input:
+      bytes: [ 0xc0, 0x0d, 0xff, 0xff, 0xff, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "oilf %r0, 4294967295"
+  -
+    input:
+      bytes: [ 0xc0, 0xfd, 0x00, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "oilf %r15, 0"
+  -
+    input:
+      bytes: [ 0xa5, 0x0a, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "oilh %r0, 0"
+  -
+    input:
+      bytes: [ 0xa5, 0x0a, 0x80, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "oilh %r0, 32768"
+  -
+    input:
+      bytes: [ 0xa5, 0x0a, 0xff, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "oilh %r0, 65535"
+  -
+    input:
+      bytes: [ 0xa5, 0xfa, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "oilh %r15, 0"
+  -
+    input:
+      bytes: [ 0xa5, 0x0b, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "oill %r0, 0"
+  -
+    input:
+      bytes: [ 0xa5, 0x0b, 0x80, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "oill %r0, 32768"
+  -
+    input:
+      bytes: [ 0xa5, 0x0b, 0xff, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "oill %r0, 65535"
+  -
+    input:
+      bytes: [ 0xa5, 0xfb, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "oill %r15, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0x56 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "oiy -524288, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0x56 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "oiy -1, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0x56 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "oiy 0, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0x56 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "oiy 1, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0x56 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "oiy 524287, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0xff, 0x00, 0x00, 0x00, 0x56 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "oiy 0, 255"
+  -
+    input:
+      bytes: [ 0xeb, 0x2a, 0x10, 0x00, 0x00, 0x56 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "oiy 0(%r1), 42"
+  -
+    input:
+      bytes: [ 0xeb, 0x2a, 0xf0, 0x00, 0x00, 0x56 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "oiy 0(%r15), 42"
+  -
+    input:
+      bytes: [ 0xeb, 0x2a, 0x1f, 0xff, 0x7f, 0x56 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "oiy 524287(%r1), 42"
+  -
+    input:
+      bytes: [ 0xeb, 0x2a, 0xff, 0xff, 0x7f, 0x56 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "oiy 524287(%r15), 42"
+  -
+    input:
+      bytes: [ 0x16, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "or %r0, %r0"
+  -
+    input:
+      bytes: [ 0x16, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "or %r0, %r15"
+  -
+    input:
+      bytes: [ 0x16, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "or %r15, %r0"
+  -
+    input:
+      bytes: [ 0x16, 0x78 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "or %r7, %r8"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x56 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "oy %r0, -524288"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x56 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "oy %r0, -1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x56 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "oy %r0, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x56 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "oy %r0, 1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x56 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "oy %r0, 524287"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x56 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "oy %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x56 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "oy %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x56 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "oy %r0, 524287(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x56 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "oy %r0, 524287(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x56 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "oy %r15, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x36 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "pfd 0, -524288"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x36 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "pfd 0, -1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x36 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "pfd 0, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x36 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "pfd 0, 1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x36 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "pfd 0, 524287"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x36 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "pfd 0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x36 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "pfd 0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x36 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "pfd 0, 524287(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x36 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "pfd 0, 524287(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x36 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "pfd 15, 0"
+  -
+    input:
+      bytes: [ 0xec, 0x00, 0x00, 0x00, 0x00, 0x55 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "risbg %r0, %r0, 0, 0, 0"
+  -
+    input:
+      bytes: [ 0xec, 0x00, 0x00, 0x00, 0x3f, 0x55 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "risbg %r0, %r0, 0, 0, 63"
+  -
+    input:
+      bytes: [ 0xec, 0x00, 0x00, 0xff, 0x00, 0x55 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "risbg %r0, %r0, 0, 255, 0"
+  -
+    input:
+      bytes: [ 0xec, 0x00, 0xff, 0x00, 0x00, 0x55 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "risbg %r0, %r0, 255, 0, 0"
+  -
+    input:
+      bytes: [ 0xec, 0x0f, 0x00, 0x00, 0x00, 0x55 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "risbg %r0, %r15, 0, 0, 0"
+  -
+    input:
+      bytes: [ 0xec, 0xf0, 0x00, 0x00, 0x00, 0x55 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "risbg %r15, %r0, 0, 0, 0"
+  -
+    input:
+      bytes: [ 0xec, 0x45, 0x06, 0x07, 0x08, 0x55 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "risbg %r4, %r5, 6, 7, 8"
+  -
+    input:
+      bytes: [ 0xec, 0x00, 0x00, 0x00, 0x00, 0x54 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "rnsbg %r0, %r0, 0, 0, 0"
+  -
+    input:
+      bytes: [ 0xec, 0x00, 0x00, 0x00, 0x3f, 0x54 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "rnsbg %r0, %r0, 0, 0, 63"
+  -
+    input:
+      bytes: [ 0xec, 0x00, 0x00, 0xff, 0x00, 0x54 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "rnsbg %r0, %r0, 0, 255, 0"
+  -
+    input:
+      bytes: [ 0xec, 0x00, 0xff, 0x00, 0x00, 0x54 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "rnsbg %r0, %r0, 255, 0, 0"
+  -
+    input:
+      bytes: [ 0xec, 0x0f, 0x00, 0x00, 0x00, 0x54 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "rnsbg %r0, %r15, 0, 0, 0"
+  -
+    input:
+      bytes: [ 0xec, 0xf0, 0x00, 0x00, 0x00, 0x54 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "rnsbg %r15, %r0, 0, 0, 0"
+  -
+    input:
+      bytes: [ 0xec, 0x45, 0x06, 0x07, 0x08, 0x54 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "rnsbg %r4, %r5, 6, 7, 8"
+  -
+    input:
+      bytes: [ 0xec, 0x00, 0x00, 0x00, 0x00, 0x56 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "rosbg %r0, %r0, 0, 0, 0"
+  -
+    input:
+      bytes: [ 0xec, 0x00, 0x00, 0x00, 0x3f, 0x56 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "rosbg %r0, %r0, 0, 0, 63"
+  -
+    input:
+      bytes: [ 0xec, 0x00, 0x00, 0xff, 0x00, 0x56 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "rosbg %r0, %r0, 0, 255, 0"
+  -
+    input:
+      bytes: [ 0xec, 0x00, 0xff, 0x00, 0x00, 0x56 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "rosbg %r0, %r0, 255, 0, 0"
+  -
+    input:
+      bytes: [ 0xec, 0x0f, 0x00, 0x00, 0x00, 0x56 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "rosbg %r0, %r15, 0, 0, 0"
+  -
+    input:
+      bytes: [ 0xec, 0xf0, 0x00, 0x00, 0x00, 0x56 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "rosbg %r15, %r0, 0, 0, 0"
+  -
+    input:
+      bytes: [ 0xec, 0x45, 0x06, 0x07, 0x08, 0x56 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "rosbg %r4, %r5, 6, 7, 8"
+  -
+    input:
+      bytes: [ 0xec, 0x00, 0x00, 0x00, 0x00, 0x57 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "rxsbg %r0, %r0, 0, 0, 0"
+  -
+    input:
+      bytes: [ 0xec, 0x00, 0x00, 0x00, 0x3f, 0x57 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "rxsbg %r0, %r0, 0, 0, 63"
+  -
+    input:
+      bytes: [ 0xec, 0x00, 0x00, 0xff, 0x00, 0x57 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "rxsbg %r0, %r0, 0, 255, 0"
+  -
+    input:
+      bytes: [ 0xec, 0x00, 0xff, 0x00, 0x00, 0x57 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "rxsbg %r0, %r0, 255, 0, 0"
+  -
+    input:
+      bytes: [ 0xec, 0x0f, 0x00, 0x00, 0x00, 0x57 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "rxsbg %r0, %r15, 0, 0, 0"
+  -
+    input:
+      bytes: [ 0xec, 0xf0, 0x00, 0x00, 0x00, 0x57 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "rxsbg %r15, %r0, 0, 0, 0"
+  -
+    input:
+      bytes: [ 0xec, 0x45, 0x06, 0x07, 0x08, 0x57 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "rxsbg %r4, %r5, 6, 7, 8"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0x1d ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "rll %r0, %r0, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0xf1, 0x00, 0x00, 0x00, 0x1d ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "rll %r15, %r1, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0x1f, 0x00, 0x00, 0x00, 0x1d ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "rll %r1, %r15, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0xff, 0x00, 0x00, 0x00, 0x1d ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "rll %r15, %r15, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0x1d ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "rll %r0, %r0, -524288"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0x1d ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "rll %r0, %r0, -1"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0x1d ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "rll %r0, %r0, 1"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0x1d ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "rll %r0, %r0, 524287"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0x1d ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "rll %r0, %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0x1d ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "rll %r0, %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x1f, 0xff, 0x7f, 0x1d ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "rll %r0, %r0, 524287(%r1)"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0xff, 0xff, 0x7f, 0x1d ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "rll %r0, %r0, 524287(%r15)"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0x1c ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "rllg %r0, %r0, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0xf1, 0x00, 0x00, 0x00, 0x1c ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "rllg %r15, %r1, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0x1f, 0x00, 0x00, 0x00, 0x1c ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "rllg %r1, %r15, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0xff, 0x00, 0x00, 0x00, 0x1c ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "rllg %r15, %r15, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0x1c ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "rllg %r0, %r0, -524288"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0x1c ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "rllg %r0, %r0, -1"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0x1c ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "rllg %r0, %r0, 1"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0x1c ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "rllg %r0, %r0, 524287"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0x1c ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "rllg %r0, %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0x1c ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "rllg %r0, %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x1f, 0xff, 0x7f, 0x1c ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "rllg %r0, %r0, 524287(%r1)"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0xff, 0xff, 0x7f, 0x1c ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "rllg %r0, %r0, 524287(%r15)"
+  -
+    input:
+      bytes: [ 0x5b, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "s %r0, 0"
+  -
+    input:
+      bytes: [ 0x5b, 0x00, 0x0f, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "s %r0, 4095"
+  -
+    input:
+      bytes: [ 0x5b, 0x00, 0x10, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "s %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0x5b, 0x00, 0xf0, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "s %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0x5b, 0x01, 0xff, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "s %r0, 4095(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0x5b, 0x0f, 0x1f, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "s %r0, 4095(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0x5b, 0xf0, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "s %r15, 0"
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x1b ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sdb %f0, 0"
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x00, 0x1b ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sdb %f0, 4095"
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x1b ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sdb %f0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x1b ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sdb %f0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xed, 0x01, 0xff, 0xff, 0x00, 0x1b ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sdb %f0, 4095(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x00, 0x1b ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sdb %f0, 4095(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0xed, 0xf0, 0x00, 0x00, 0x00, 0x1b ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sdb %f15, 0"
+  -
+    input:
+      bytes: [ 0xb3, 0x1b, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sdbr %f0, %f0"
+  -
+    input:
+      bytes: [ 0xb3, 0x1b, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sdbr %f0, %f15"
+  -
+    input:
+      bytes: [ 0xb3, 0x1b, 0x00, 0x78 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sdbr %f7, %f8"
+  -
+    input:
+      bytes: [ 0xb3, 0x1b, 0x00, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sdbr %f15, %f0"
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x0b ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "seb %f0, 0"
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x00, 0x0b ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "seb %f0, 4095"
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x0b ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "seb %f0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x0b ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "seb %f0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xed, 0x01, 0xff, 0xff, 0x00, 0x0b ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "seb %f0, 4095(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x00, 0x0b ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "seb %f0, 4095(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0xed, 0xf0, 0x00, 0x00, 0x00, 0x0b ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "seb %f15, 0"
+  -
+    input:
+      bytes: [ 0xb3, 0x0b, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sebr %f0, %f0"
+  -
+    input:
+      bytes: [ 0xb3, 0x0b, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sebr %f0, %f15"
+  -
+    input:
+      bytes: [ 0xb3, 0x0b, 0x00, 0x78 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sebr %f7, %f8"
+  -
+    input:
+      bytes: [ 0xb3, 0x0b, 0x00, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sebr %f15, %f0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x09 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sg %r0, -524288"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x09 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sg %r0, -1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x09 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sg %r0, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x09 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sg %r0, 1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x09 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sg %r0, 524287"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x09 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sg %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x09 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sg %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x09 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sg %r0, 524287(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x09 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sg %r0, 524287(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x09 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sg %r15, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x19 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sgf %r0, -524288"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x19 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sgf %r0, -1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x19 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sgf %r0, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x19 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sgf %r0, 1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x19 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sgf %r0, 524287"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x19 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sgf %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x19 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sgf %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x19 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sgf %r0, 524287(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x19 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sgf %r0, 524287(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x19 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sgf %r15, 0"
+  -
+    input:
+      bytes: [ 0xb9, 0x19, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sgfr %r0, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0x19, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sgfr %r0, %r15"
+  -
+    input:
+      bytes: [ 0xb9, 0x19, 0x00, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sgfr %r15, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0x19, 0x00, 0x78 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sgfr %r7, %r8"
+  -
+    input:
+      bytes: [ 0xb9, 0x09, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sgr %r0, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0x09, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sgr %r0, %r15"
+  -
+    input:
+      bytes: [ 0xb9, 0x09, 0x00, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sgr %r15, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0x09, 0x00, 0x78 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sgr %r7, %r8"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sh %r0, 0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0x0f, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sh %r0, 4095"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0x10, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sh %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0xf0, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sh %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0x4b, 0x01, 0xff, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sh %r0, 4095(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0x4b, 0x0f, 0x1f, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sh %r0, 4095(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0x4b, 0xf0, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sh %r15, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x7b ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "shy %r0, -524288"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x7b ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "shy %r0, -1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x7b ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "shy %r0, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x7b ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "shy %r0, 1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x7b ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "shy %r0, 524287"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x7b ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "shy %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x7b ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "shy %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x7b ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "shy %r0, 524287(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x7b ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "shy %r0, 524287(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x7b ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "shy %r15, 0"
+  -
+    input:
+      bytes: [ 0x5f, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sl %r0, 0"
+  -
+    input:
+      bytes: [ 0x5f, 0x00, 0x0f, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sl %r0, 4095"
+  -
+    input:
+      bytes: [ 0x5f, 0x00, 0x10, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sl %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0x5f, 0x00, 0xf0, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sl %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0x5f, 0x01, 0xff, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sl %r0, 4095(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0x5f, 0x0f, 0x1f, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sl %r0, 4095(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0x5f, 0xf0, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sl %r15, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x99 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "slb %r0, -524288"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x99 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "slb %r0, -1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x99 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "slb %r0, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x99 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "slb %r0, 1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x99 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "slb %r0, 524287"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x99 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "slb %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x99 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "slb %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x99 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "slb %r0, 524287(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x99 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "slb %r0, 524287(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x99 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "slb %r15, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x89 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "slbg %r0, -524288"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x89 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "slbg %r0, -1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x89 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "slbg %r0, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x89 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "slbg %r0, 1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x89 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "slbg %r0, 524287"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x89 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "slbg %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x89 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "slbg %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x89 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "slbg %r0, 524287(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x89 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "slbg %r0, 524287(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x89 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "slbg %r15, 0"
+  -
+    input:
+      bytes: [ 0xb9, 0x89, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "slbgr %r0, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0x89, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "slbgr %r0, %r15"
+  -
+    input:
+      bytes: [ 0xb9, 0x89, 0x00, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "slbgr %r15, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0x89, 0x00, 0x78 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "slbgr %r7, %r8"
+  -
+    input:
+      bytes: [ 0xb9, 0x99, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "slbr %r0, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0x99, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "slbr %r0, %r15"
+  -
+    input:
+      bytes: [ 0xb9, 0x99, 0x00, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "slbr %r15, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0x99, 0x00, 0x78 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "slbr %r7, %r8"
+  -
+    input:
+      bytes: [ 0xc2, 0x05, 0x00, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "slfi %r0, 0"
+  -
+    input:
+      bytes: [ 0xc2, 0x05, 0xff, 0xff, 0xff, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "slfi %r0, 4294967295"
+  -
+    input:
+      bytes: [ 0xc2, 0xf5, 0x00, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "slfi %r15, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x0b ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "slg %r0, -524288"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x0b ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "slg %r0, -1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x0b ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "slg %r0, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x0b ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "slg %r0, 1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x0b ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "slg %r0, 524287"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x0b ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "slg %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x0b ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "slg %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x0b ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "slg %r0, 524287(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x0b ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "slg %r0, 524287(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x0b ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "slg %r15, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x1b ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "slgf %r0, -524288"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x1b ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "slgf %r0, -1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x1b ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "slgf %r0, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x1b ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "slgf %r0, 1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x1b ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "slgf %r0, 524287"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x1b ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "slgf %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x1b ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "slgf %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x1b ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "slgf %r0, 524287(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x1b ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "slgf %r0, 524287(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x1b ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "slgf %r15, 0"
+  -
+    input:
+      bytes: [ 0xc2, 0x04, 0x00, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "slgfi %r0, 0"
+  -
+    input:
+      bytes: [ 0xc2, 0x04, 0xff, 0xff, 0xff, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "slgfi %r0, 4294967295"
+  -
+    input:
+      bytes: [ 0xc2, 0xf4, 0x00, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "slgfi %r15, 0"
+  -
+    input:
+      bytes: [ 0xb9, 0x1b, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "slgfr %r0, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0x1b, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "slgfr %r0, %r15"
+  -
+    input:
+      bytes: [ 0xb9, 0x1b, 0x00, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "slgfr %r15, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0x1b, 0x00, 0x78 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "slgfr %r7, %r8"
+  -
+    input:
+      bytes: [ 0xb9, 0x0b, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "slgr %r0, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0x0b, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "slgr %r0, %r15"
+  -
+    input:
+      bytes: [ 0xb9, 0x0b, 0x00, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "slgr %r15, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0x0b, 0x00, 0x78 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "slgr %r7, %r8"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sll %r0, 0"
+  -
+    input:
+      bytes: [ 0x89, 0x70, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sll %r7, 0"
+  -
+    input:
+      bytes: [ 0x89, 0xf0, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sll %r15, 0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x0f, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sll %r0, 4095"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x10, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sll %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0xf0, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sll %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x1f, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sll %r0, 4095(%r1)"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0xff, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sll %r0, 4095(%r15)"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0x0d ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sllg %r0, %r0, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0xf1, 0x00, 0x00, 0x00, 0x0d ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sllg %r15, %r1, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0x1f, 0x00, 0x00, 0x00, 0x0d ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sllg %r1, %r15, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0xff, 0x00, 0x00, 0x00, 0x0d ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sllg %r15, %r15, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0x0d ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sllg %r0, %r0, -524288"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0x0d ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sllg %r0, %r0, -1"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0x0d ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sllg %r0, %r0, 1"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0x0d ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sllg %r0, %r0, 524287"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0x0d ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sllg %r0, %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0x0d ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sllg %r0, %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x1f, 0xff, 0x7f, 0x0d ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sllg %r0, %r0, 524287(%r1)"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0xff, 0xff, 0x7f, 0x0d ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sllg %r0, %r0, 524287(%r15)"
+  -
+    input:
+      bytes: [ 0x1f, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "slr %r0, %r0"
+  -
+    input:
+      bytes: [ 0x1f, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "slr %r0, %r15"
+  -
+    input:
+      bytes: [ 0x1f, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "slr %r15, %r0"
+  -
+    input:
+      bytes: [ 0x1f, 0x78 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "slr %r7, %r8"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x5f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sly %r0, -524288"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x5f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sly %r0, -1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x5f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sly %r0, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x5f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sly %r0, 1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x5f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sly %r0, 524287"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x5f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sly %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x5f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sly %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x5f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sly %r0, 524287(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x5f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sly %r0, 524287(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x5f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sly %r15, 0"
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x15 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdb %f0, 0"
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x00, 0x15 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdb %f0, 4095"
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x15 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdb %f0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x15 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdb %f0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xed, 0x01, 0xff, 0xff, 0x00, 0x15 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdb %f0, 4095(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x00, 0x15 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdb %f0, 4095(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0xed, 0xf0, 0x00, 0x00, 0x00, 0x15 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdb %f15, 0"
+  -
+    input:
+      bytes: [ 0xb3, 0x15, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdbr %f0, %f0"
+  -
+    input:
+      bytes: [ 0xb3, 0x15, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdbr %f0, %f15"
+  -
+    input:
+      bytes: [ 0xb3, 0x15, 0x00, 0x78 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdbr %f7, %f8"
+  -
+    input:
+      bytes: [ 0xb3, 0x15, 0x00, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sqdbr %f15, %f0"
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x14 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sqeb %f0, 0"
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x00, 0x14 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sqeb %f0, 4095"
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x14 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sqeb %f0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x14 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sqeb %f0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xed, 0x01, 0xff, 0xff, 0x00, 0x14 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sqeb %f0, 4095(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x00, 0x14 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sqeb %f0, 4095(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0xed, 0xf0, 0x00, 0x00, 0x00, 0x14 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sqeb %f15, 0"
+  -
+    input:
+      bytes: [ 0xb3, 0x14, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sqebr %f0, %f0"
+  -
+    input:
+      bytes: [ 0xb3, 0x14, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sqebr %f0, %f15"
+  -
+    input:
+      bytes: [ 0xb3, 0x14, 0x00, 0x78 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sqebr %f7, %f8"
+  -
+    input:
+      bytes: [ 0xb3, 0x14, 0x00, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sqebr %f15, %f0"
+  -
+    input:
+      bytes: [ 0xb3, 0x16, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sqxbr %f0, %f0"
+  -
+    input:
+      bytes: [ 0xb3, 0x16, 0x00, 0x0d ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sqxbr %f0, %f13"
+  -
+    input:
+      bytes: [ 0xb3, 0x16, 0x00, 0x88 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sqxbr %f8, %f8"
+  -
+    input:
+      bytes: [ 0xb3, 0x16, 0x00, 0xd0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sqxbr %f13, %f0"
+  -
+    input:
+      bytes: [ 0x1b, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sr %r0, %r0"
+  -
+    input:
+      bytes: [ 0x1b, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sr %r0, %r15"
+  -
+    input:
+      bytes: [ 0x1b, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sr %r15, %r0"
+  -
+    input:
+      bytes: [ 0x1b, 0x78 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sr %r7, %r8"
+  -
+    input:
+      bytes: [ 0x8a, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sra %r0, 0"
+  -
+    input:
+      bytes: [ 0x8a, 0x70, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sra %r7, 0"
+  -
+    input:
+      bytes: [ 0x8a, 0xf0, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sra %r15, 0"
+  -
+    input:
+      bytes: [ 0x8a, 0x00, 0x0f, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sra %r0, 4095"
+  -
+    input:
+      bytes: [ 0x8a, 0x00, 0x10, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sra %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0x8a, 0x00, 0xf0, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sra %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0x8a, 0x00, 0x1f, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sra %r0, 4095(%r1)"
+  -
+    input:
+      bytes: [ 0x8a, 0x00, 0xff, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sra %r0, 4095(%r15)"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0x0a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "srag %r0, %r0, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0xf1, 0x00, 0x00, 0x00, 0x0a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "srag %r15, %r1, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0x1f, 0x00, 0x00, 0x00, 0x0a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "srag %r1, %r15, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0xff, 0x00, 0x00, 0x00, 0x0a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "srag %r15, %r15, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0x0a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "srag %r0, %r0, -524288"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0x0a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "srag %r0, %r0, -1"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0x0a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "srag %r0, %r0, 1"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0x0a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "srag %r0, %r0, 524287"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0x0a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "srag %r0, %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0x0a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "srag %r0, %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x1f, 0xff, 0x7f, 0x0a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "srag %r0, %r0, 524287(%r1)"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0xff, 0xff, 0x7f, 0x0a ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "srag %r0, %r0, 524287(%r15)"
+  -
+    input:
+      bytes: [ 0x88, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "srl %r0, 0"
+  -
+    input:
+      bytes: [ 0x88, 0x70, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "srl %r7, 0"
+  -
+    input:
+      bytes: [ 0x88, 0xf0, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "srl %r15, 0"
+  -
+    input:
+      bytes: [ 0x88, 0x00, 0x0f, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "srl %r0, 4095"
+  -
+    input:
+      bytes: [ 0x88, 0x00, 0x10, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "srl %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0x88, 0x00, 0xf0, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "srl %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0x88, 0x00, 0x1f, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "srl %r0, 4095(%r1)"
+  -
+    input:
+      bytes: [ 0x88, 0x00, 0xff, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "srl %r0, 4095(%r15)"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0x0c ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "srlg %r0, %r0, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0xf1, 0x00, 0x00, 0x00, 0x0c ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "srlg %r15, %r1, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0x1f, 0x00, 0x00, 0x00, 0x0c ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "srlg %r1, %r15, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0xff, 0x00, 0x00, 0x00, 0x0c ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "srlg %r15, %r15, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0x0c ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "srlg %r0, %r0, -524288"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0x0c ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "srlg %r0, %r0, -1"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0x0c ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "srlg %r0, %r0, 1"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0x0c ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "srlg %r0, %r0, 524287"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0x0c ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "srlg %r0, %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0x0c ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "srlg %r0, %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x1f, 0xff, 0x7f, 0x0c ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "srlg %r0, %r0, 524287(%r1)"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0xff, 0xff, 0x7f, 0x0c ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "srlg %r0, %r0, 524287(%r15)"
+  -
+    input:
+      bytes: [ 0xb2, 0x5e, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "srst %r0, %r0"
+  -
+    input:
+      bytes: [ 0xb2, 0x5e, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "srst %r0, %r15"
+  -
+    input:
+      bytes: [ 0xb2, 0x5e, 0x00, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "srst %r15, %r0"
+  -
+    input:
+      bytes: [ 0xb2, 0x5e, 0x00, 0x78 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "srst %r7, %r8"
+  -
+    input:
+      bytes: [ 0x50, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "st %r0, 0"
+  -
+    input:
+      bytes: [ 0x50, 0x00, 0x0f, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "st %r0, 4095"
+  -
+    input:
+      bytes: [ 0x50, 0x00, 0x10, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "st %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0x50, 0x00, 0xf0, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "st %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0x50, 0x01, 0xff, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "st %r0, 4095(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0x50, 0x0f, 0x1f, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "st %r0, 4095(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0x50, 0xf0, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "st %r15, 0"
+  -
+    input:
+      bytes: [ 0x42, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stc %r0, 0"
+  -
+    input:
+      bytes: [ 0x42, 0x00, 0x0f, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stc %r0, 4095"
+  -
+    input:
+      bytes: [ 0x42, 0x00, 0x10, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stc %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0x42, 0x00, 0xf0, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stc %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0x42, 0x01, 0xff, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stc %r0, 4095(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0x42, 0x0f, 0x1f, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stc %r0, 4095(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0x42, 0xf0, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stc %r15, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x72 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stcy %r0, -524288"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x72 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stcy %r0, -1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x72 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stcy %r0, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x72 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stcy %r0, 1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x72 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stcy %r0, 524287"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x72 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stcy %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x72 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stcy %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x72 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stcy %r0, 524287(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x72 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stcy %r0, 524287(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x72 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stcy %r15, 0"
+  -
+    input:
+      bytes: [ 0x60, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "std %f0, 0"
+  -
+    input:
+      bytes: [ 0x60, 0x00, 0x0f, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "std %f0, 4095"
+  -
+    input:
+      bytes: [ 0x60, 0x00, 0x10, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "std %f0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0x60, 0x00, 0xf0, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "std %f0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0x60, 0x01, 0xff, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "std %f0, 4095(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0x60, 0x0f, 0x1f, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "std %f0, 4095(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0x60, 0xf0, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "std %f15, 0"
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0x00, 0x00, 0x80, 0x67 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stdy %f0, -524288"
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0x0f, 0xff, 0xff, 0x67 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stdy %f0, -1"
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x67 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stdy %f0, 0"
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0x00, 0x01, 0x00, 0x67 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stdy %f0, 1"
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x7f, 0x67 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stdy %f0, 524287"
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x67 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stdy %f0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x67 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stdy %f0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xed, 0x01, 0xff, 0xff, 0x7f, 0x67 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stdy %f0, 524287(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x7f, 0x67 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stdy %f0, 524287(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0xed, 0xf0, 0x00, 0x00, 0x00, 0x67 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stdy %f15, 0"
+  -
+    input:
+      bytes: [ 0x70, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ste %f0, 0"
+  -
+    input:
+      bytes: [ 0x70, 0x00, 0x0f, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ste %f0, 4095"
+  -
+    input:
+      bytes: [ 0x70, 0x00, 0x10, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ste %f0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0x70, 0x00, 0xf0, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ste %f0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0x70, 0x01, 0xff, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ste %f0, 4095(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0x70, 0x0f, 0x1f, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ste %f0, 4095(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0x70, 0xf0, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ste %f15, 0"
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0x00, 0x00, 0x80, 0x66 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stey %f0, -524288"
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0x0f, 0xff, 0xff, 0x66 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stey %f0, -1"
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x66 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stey %f0, 0"
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0x00, 0x01, 0x00, 0x66 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stey %f0, 1"
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0x0f, 0xff, 0x7f, 0x66 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stey %f0, 524287"
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0x10, 0x00, 0x00, 0x66 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stey %f0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0xf0, 0x00, 0x00, 0x66 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stey %f0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xed, 0x01, 0xff, 0xff, 0x7f, 0x66 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stey %f0, 524287(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0xed, 0x0f, 0x1f, 0xff, 0x7f, 0x66 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stey %f0, 524287(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0xed, 0xf0, 0x00, 0x00, 0x00, 0x66 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stey %f15, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x24 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stg %r0, -524288"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x24 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stg %r0, -1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x24 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stg %r0, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x24 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stg %r0, 1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x24 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stg %r0, 524287"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x24 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stg %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x24 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stg %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x24 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stg %r0, 524287(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x24 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stg %r0, 524287(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x24 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stg %r15, 0"
+  -
+    input:
+      bytes: [ 0x40, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sth %r0, 0"
+  -
+    input:
+      bytes: [ 0x40, 0x00, 0x0f, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sth %r0, 4095"
+  -
+    input:
+      bytes: [ 0x40, 0x00, 0x10, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sth %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0x40, 0x00, 0xf0, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sth %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0x40, 0x01, 0xff, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sth %r0, 4095(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0x40, 0x0f, 0x1f, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sth %r0, 4095(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0x40, 0xf0, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sth %r15, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x70 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sthy %r0, -524288"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x70 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sthy %r0, -1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x70 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sthy %r0, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x70 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sthy %r0, 1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x70 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sthy %r0, 524287"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x70 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sthy %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x70 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sthy %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x70 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sthy %r0, 524287(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x70 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sthy %r0, 524287(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x70 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sthy %r15, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0x24 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stmg %r0, %r0, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0x0f, 0x00, 0x00, 0x00, 0x24 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stmg %r0, %r15, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0xef, 0x00, 0x00, 0x00, 0x24 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stmg %r14, %r15, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0xff, 0x00, 0x00, 0x00, 0x24 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stmg %r15, %r15, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0x24 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stmg %r0, %r0, -524288"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0x24 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stmg %r0, %r0, -1"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0x24 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stmg %r0, %r0, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0x24 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stmg %r0, %r0, 1"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0x24 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stmg %r0, %r0, 524287"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x10, 0x00, 0x00, 0x24 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stmg %r0, %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0xf0, 0x00, 0x00, 0x24 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stmg %r0, %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x1f, 0xff, 0x7f, 0x24 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stmg %r0, %r0, 524287(%r1)"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0xff, 0xff, 0x7f, 0x24 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "stmg %r0, %r0, 524287(%r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x3e ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "strv %r0, -524288"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x3e ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "strv %r0, -1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x3e ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "strv %r0, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x3e ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "strv %r0, 1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x3e ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "strv %r0, 524287"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x3e ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "strv %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x3e ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "strv %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x3e ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "strv %r0, 524287(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x3e ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "strv %r0, 524287(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x3e ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "strv %r15, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x2f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "strvg %r0, -524288"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x2f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "strvg %r0, -1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x2f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "strvg %r0, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x2f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "strvg %r0, 1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x2f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "strvg %r0, 524287"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x2f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "strvg %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x2f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "strvg %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x2f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "strvg %r0, 524287(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x2f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "strvg %r0, 524287(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x2f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "strvg %r15, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x50 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sty %r0, -524288"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x50 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sty %r0, -1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x50 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sty %r0, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x50 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sty %r0, 1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x50 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sty %r0, 524287"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x50 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sty %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x50 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sty %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x50 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sty %r0, 524287(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x50 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sty %r0, 524287(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x50 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sty %r15, 0"
+  -
+    input:
+      bytes: [ 0xb3, 0x4b, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sxbr %f0, %f0"
+  -
+    input:
+      bytes: [ 0xb3, 0x4b, 0x00, 0x0d ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sxbr %f0, %f13"
+  -
+    input:
+      bytes: [ 0xb3, 0x4b, 0x00, 0x88 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sxbr %f8, %f8"
+  -
+    input:
+      bytes: [ 0xb3, 0x4b, 0x00, 0xd0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sxbr %f13, %f0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x5b ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sy %r0, -524288"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x5b ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sy %r0, -1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x5b ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sy %r0, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x5b ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sy %r0, 1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x5b ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sy %r0, 524287"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x5b ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sy %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x5b ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sy %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x5b ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sy %r0, 524287(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x5b ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sy %r0, 524287(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x5b ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "sy %r15, 0"
+  -
+    input:
+      bytes: [ 0x91, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "tm 0, 0"
+  -
+    input:
+      bytes: [ 0x91, 0x00, 0x0f, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "tm 4095, 0"
+  -
+    input:
+      bytes: [ 0x91, 0xff, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "tm 0, 255"
+  -
+    input:
+      bytes: [ 0x91, 0x2a, 0x10, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "tm 0(%r1), 42"
+  -
+    input:
+      bytes: [ 0x91, 0x2a, 0xf0, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "tm 0(%r15), 42"
+  -
+    input:
+      bytes: [ 0x91, 0x2a, 0x1f, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "tm 4095(%r1), 42"
+  -
+    input:
+      bytes: [ 0x91, 0x2a, 0xff, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "tm 4095(%r15), 42"
+  -
+    input:
+      bytes: [ 0xa7, 0x02, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "tmhh %r0, 0"
+  -
+    input:
+      bytes: [ 0xa7, 0x02, 0x80, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "tmhh %r0, 32768"
+  -
+    input:
+      bytes: [ 0xa7, 0x02, 0xff, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "tmhh %r0, 65535"
+  -
+    input:
+      bytes: [ 0xa7, 0xf2, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "tmhh %r15, 0"
+  -
+    input:
+      bytes: [ 0xa7, 0x03, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "tmhl %r0, 0"
+  -
+    input:
+      bytes: [ 0xa7, 0x03, 0x80, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "tmhl %r0, 32768"
+  -
+    input:
+      bytes: [ 0xa7, 0x03, 0xff, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "tmhl %r0, 65535"
+  -
+    input:
+      bytes: [ 0xa7, 0xf3, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "tmhl %r15, 0"
+  -
+    input:
+      bytes: [ 0xa7, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "tmlh %r0, 0"
+  -
+    input:
+      bytes: [ 0xa7, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "tmlh %r0, 32768"
+  -
+    input:
+      bytes: [ 0xa7, 0x00, 0xff, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "tmlh %r0, 65535"
+  -
+    input:
+      bytes: [ 0xa7, 0xf0, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "tmlh %r15, 0"
+  -
+    input:
+      bytes: [ 0xa7, 0x01, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "tmll %r0, 0"
+  -
+    input:
+      bytes: [ 0xa7, 0x01, 0x80, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "tmll %r0, 32768"
+  -
+    input:
+      bytes: [ 0xa7, 0x01, 0xff, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "tmll %r0, 65535"
+  -
+    input:
+      bytes: [ 0xa7, 0xf1, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "tmll %r15, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0x51 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "tmy -524288, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0x51 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "tmy -1, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0x51 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "tmy 0, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0x51 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "tmy 1, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0x51 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "tmy 524287, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0xff, 0x00, 0x00, 0x00, 0x51 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "tmy 0, 255"
+  -
+    input:
+      bytes: [ 0xeb, 0x2a, 0x10, 0x00, 0x00, 0x51 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "tmy 0(%r1), 42"
+  -
+    input:
+      bytes: [ 0xeb, 0x2a, 0xf0, 0x00, 0x00, 0x51 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "tmy 0(%r15), 42"
+  -
+    input:
+      bytes: [ 0xeb, 0x2a, 0x1f, 0xff, 0x7f, 0x51 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "tmy 524287(%r1), 42"
+  -
+    input:
+      bytes: [ 0xeb, 0x2a, 0xff, 0xff, 0x7f, 0x51 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "tmy 524287(%r15), 42"
+  -
+    input:
+      bytes: [ 0x57, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "x %r0, 0"
+  -
+    input:
+      bytes: [ 0x57, 0x00, 0x0f, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "x %r0, 4095"
+  -
+    input:
+      bytes: [ 0x57, 0x00, 0x10, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "x %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0x57, 0x00, 0xf0, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "x %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0x57, 0x01, 0xff, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "x %r0, 4095(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0x57, 0x0f, 0x1f, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "x %r0, 4095(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0x57, 0xf0, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "x %r15, 0"
+  -
+    input:
+      bytes: [ 0xd7, 0x00, 0x00, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "xc 0(1), 0"
+  -
+    input:
+      bytes: [ 0xd7, 0x00, 0x00, 0x00, 0x10, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "xc 0(1), 0(%r1)"
+  -
+    input:
+      bytes: [ 0xd7, 0x00, 0x00, 0x00, 0xf0, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "xc 0(1), 0(%r15)"
+  -
+    input:
+      bytes: [ 0xd7, 0x00, 0x00, 0x00, 0x0f, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "xc 0(1), 4095"
+  -
+    input:
+      bytes: [ 0xd7, 0x00, 0x00, 0x00, 0x1f, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "xc 0(1), 4095(%r1)"
+  -
+    input:
+      bytes: [ 0xd7, 0x00, 0x00, 0x00, 0xff, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "xc 0(1), 4095(%r15)"
+  -
+    input:
+      bytes: [ 0xd7, 0x00, 0x10, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "xc 0(1, %r1), 0"
+  -
+    input:
+      bytes: [ 0xd7, 0x00, 0xf0, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "xc 0(1, %r15), 0"
+  -
+    input:
+      bytes: [ 0xd7, 0x00, 0x1f, 0xff, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "xc 4095(1, %r1), 0"
+  -
+    input:
+      bytes: [ 0xd7, 0x00, 0xff, 0xff, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "xc 4095(1, %r15), 0"
+  -
+    input:
+      bytes: [ 0xd7, 0xff, 0x10, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "xc 0(256, %r1), 0"
+  -
+    input:
+      bytes: [ 0xd7, 0xff, 0xf0, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "xc 0(256, %r15), 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x82 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "xg %r0, -524288"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x82 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "xg %r0, -1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x82 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "xg %r0, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x82 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "xg %r0, 1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x82 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "xg %r0, 524287"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x82 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "xg %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x82 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "xg %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x82 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "xg %r0, 524287(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x82 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "xg %r0, 524287(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x82 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "xg %r15, 0"
+  -
+    input:
+      bytes: [ 0xb9, 0x82, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "xgr %r0, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0x82, 0x00, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "xgr %r0, %r15"
+  -
+    input:
+      bytes: [ 0xb9, 0x82, 0x00, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "xgr %r15, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0x82, 0x00, 0x78 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "xgr %r7, %r8"
+  -
+    input:
+      bytes: [ 0x97, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "xi 0, 0"
+  -
+    input:
+      bytes: [ 0x97, 0x00, 0x0f, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "xi 4095, 0"
+  -
+    input:
+      bytes: [ 0x97, 0xff, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "xi 0, 255"
+  -
+    input:
+      bytes: [ 0x97, 0x2a, 0x10, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "xi 0(%r1), 42"
+  -
+    input:
+      bytes: [ 0x97, 0x2a, 0xf0, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "xi 0(%r15), 42"
+  -
+    input:
+      bytes: [ 0x97, 0x2a, 0x1f, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "xi 4095(%r1), 42"
+  -
+    input:
+      bytes: [ 0x97, 0x2a, 0xff, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "xi 4095(%r15), 42"
+  -
+    input:
+      bytes: [ 0xc0, 0x06, 0x00, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "xihf %r0, 0"
+  -
+    input:
+      bytes: [ 0xc0, 0x06, 0xff, 0xff, 0xff, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "xihf %r0, 4294967295"
+  -
+    input:
+      bytes: [ 0xc0, 0xf6, 0x00, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "xihf %r15, 0"
+  -
+    input:
+      bytes: [ 0xc0, 0x07, 0x00, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "xilf %r0, 0"
+  -
+    input:
+      bytes: [ 0xc0, 0x07, 0xff, 0xff, 0xff, 0xff ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "xilf %r0, 4294967295"
+  -
+    input:
+      bytes: [ 0xc0, 0xf7, 0x00, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "xilf %r15, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x80, 0x57 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "xiy -524288, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0xff, 0x57 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "xiy -1, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x00, 0x00, 0x00, 0x57 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "xiy 0, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x00, 0x01, 0x00, 0x57 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "xiy 1, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0x00, 0x0f, 0xff, 0x7f, 0x57 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "xiy 524287, 0"
+  -
+    input:
+      bytes: [ 0xeb, 0xff, 0x00, 0x00, 0x00, 0x57 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "xiy 0, 255"
+  -
+    input:
+      bytes: [ 0xeb, 0x2a, 0x10, 0x00, 0x00, 0x57 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "xiy 0(%r1), 42"
+  -
+    input:
+      bytes: [ 0xeb, 0x2a, 0xf0, 0x00, 0x00, 0x57 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "xiy 0(%r15), 42"
+  -
+    input:
+      bytes: [ 0xeb, 0x2a, 0x1f, 0xff, 0x7f, 0x57 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "xiy 524287(%r1), 42"
+  -
+    input:
+      bytes: [ 0xeb, 0x2a, 0xff, 0xff, 0x7f, 0x57 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "xiy 524287(%r15), 42"
+  -
+    input:
+      bytes: [ 0x17, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "xr %r0, %r0"
+  -
+    input:
+      bytes: [ 0x17, 0x0f ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "xr %r0, %r15"
+  -
+    input:
+      bytes: [ 0x17, 0xf0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "xr %r15, %r0"
+  -
+    input:
+      bytes: [ 0x17, 0x78 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "xr %r7, %r8"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x80, 0x57 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "xy %r0, -524288"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0xff, 0x57 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "xy %r0, -1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x00, 0x00, 0x57 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "xy %r0, 0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x00, 0x01, 0x00, 0x57 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "xy %r0, 1"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x0f, 0xff, 0x7f, 0x57 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "xy %r0, 524287"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x10, 0x00, 0x00, 0x57 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "xy %r0, 0(%r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xf0, 0x00, 0x00, 0x57 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "xy %r0, 0(%r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x57 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "xy %r0, 524287(%r1, %r15)"
+  -
+    input:
+      bytes: [ 0xe3, 0x0f, 0x1f, 0xff, 0x7f, 0x57 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "xy %r0, 524287(%r15, %r1)"
+  -
+    input:
+      bytes: [ 0xe3, 0xf0, 0x00, 0x00, 0x00, 0x57 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "xy %r15, 0"
diff --git a/tests/MC/SystemZ/regs-good.s.yaml b/tests/MC/SystemZ/regs-good.s.yaml
new file mode 100644
index 000000000..cec0be83f
--- /dev/null
+++ b/tests/MC/SystemZ/regs-good.s.yaml
@@ -0,0 +1,397 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x18, 0x01 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lr %r0, %r1"
+  -
+    input:
+      bytes: [ 0x18, 0x23 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lr %r2, %r3"
+  -
+    input:
+      bytes: [ 0x18, 0x45 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lr %r4, %r5"
+  -
+    input:
+      bytes: [ 0x18, 0x67 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lr %r6, %r7"
+  -
+    input:
+      bytes: [ 0x18, 0x89 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lr %r8, %r9"
+  -
+    input:
+      bytes: [ 0x18, 0xab ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lr %r10, %r11"
+  -
+    input:
+      bytes: [ 0x18, 0xcd ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lr %r12, %r13"
+  -
+    input:
+      bytes: [ 0x18, 0xef ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lr %r14, %r15"
+  -
+    input:
+      bytes: [ 0xb9, 0x04, 0x00, 0x01 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lgr %r0, %r1"
+  -
+    input:
+      bytes: [ 0xb9, 0x04, 0x00, 0x23 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lgr %r2, %r3"
+  -
+    input:
+      bytes: [ 0xb9, 0x04, 0x00, 0x45 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lgr %r4, %r5"
+  -
+    input:
+      bytes: [ 0xb9, 0x04, 0x00, 0x67 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lgr %r6, %r7"
+  -
+    input:
+      bytes: [ 0xb9, 0x04, 0x00, 0x89 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lgr %r8, %r9"
+  -
+    input:
+      bytes: [ 0xb9, 0x04, 0x00, 0xab ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lgr %r10, %r11"
+  -
+    input:
+      bytes: [ 0xb9, 0x04, 0x00, 0xcd ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lgr %r12, %r13"
+  -
+    input:
+      bytes: [ 0xb9, 0x04, 0x00, 0xef ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lgr %r14, %r15"
+  -
+    input:
+      bytes: [ 0xb9, 0x97, 0x00, 0x00 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "dlr %r0, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0x97, 0x00, 0x20 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "dlr %r2, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0x97, 0x00, 0x40 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "dlr %r4, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0x97, 0x00, 0x60 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "dlr %r6, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0x97, 0x00, 0x80 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "dlr %r8, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0x97, 0x00, 0xa0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "dlr %r10, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0x97, 0x00, 0xc0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "dlr %r12, %r0"
+  -
+    input:
+      bytes: [ 0xb9, 0x97, 0x00, 0xe0 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "dlr %r14, %r0"
+  -
+    input:
+      bytes: [ 0x38, 0x01 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ler %f0, %f1"
+  -
+    input:
+      bytes: [ 0x38, 0x23 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ler %f2, %f3"
+  -
+    input:
+      bytes: [ 0x38, 0x45 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ler %f4, %f5"
+  -
+    input:
+      bytes: [ 0x38, 0x67 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ler %f6, %f7"
+  -
+    input:
+      bytes: [ 0x38, 0x89 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ler %f8, %f9"
+  -
+    input:
+      bytes: [ 0x38, 0xab ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ler %f10, %f11"
+  -
+    input:
+      bytes: [ 0x38, 0xcd ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ler %f12, %f13"
+  -
+    input:
+      bytes: [ 0x38, 0xef ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ler %f14, %f15"
+  -
+    input:
+      bytes: [ 0x28, 0x01 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr %f0, %f1"
+  -
+    input:
+      bytes: [ 0x28, 0x23 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr %f2, %f3"
+  -
+    input:
+      bytes: [ 0x28, 0x45 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr %f4, %f5"
+  -
+    input:
+      bytes: [ 0x28, 0x67 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr %f6, %f7"
+  -
+    input:
+      bytes: [ 0x28, 0x89 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr %f8, %f9"
+  -
+    input:
+      bytes: [ 0x28, 0xab ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr %f10, %f11"
+  -
+    input:
+      bytes: [ 0x28, 0xcd ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr %f12, %f13"
+  -
+    input:
+      bytes: [ 0x28, 0xef ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "ldr %f14, %f15"
+  -
+    input:
+      bytes: [ 0xb3, 0x65, 0x00, 0x01 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lxr %f0, %f1"
+  -
+    input:
+      bytes: [ 0xb3, 0x65, 0x00, 0x45 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lxr %f4, %f5"
+  -
+    input:
+      bytes: [ 0xb3, 0x65, 0x00, 0x89 ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lxr %f8, %f9"
+  -
+    input:
+      bytes: [ 0xb3, 0x65, 0x00, 0xcd ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ ]
+    expected:
+      insns:
+        -
+          asm_text: "lxr %f12, %f13"
diff --git a/tests/MC/TriCore/ADC_Background_Scan_1_KIT_TC275_LK.s.yaml b/tests/MC/TriCore/ADC_Background_Scan_1_KIT_TC275_LK.s.yaml
new file mode 100644
index 000000000..fba549d2a
--- /dev/null
+++ b/tests/MC/TriCore/ADC_Background_Scan_1_KIT_TC275_LK.s.yaml
@@ -0,0 +1,7588 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x43, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x886"
+  -
+    input:
+      bytes: [ 0xc6, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor d0, d1"
+  -
+    input:
+      bytes: [ 0x0f, 0xf3, 0x00, 0x30 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh d3, d3, d15"
+  -
+    input:
+      bytes: [ 0x10, 0xaf ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addsc.a a15, sp, d15, #0"
+  -
+    input:
+      bytes: [ 0x8f, 0x33, 0x40, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or d15, d3, #0x3"
+  -
+    input:
+      bytes: [ 0xf6, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz d0, #0xc"
+  -
+    input:
+      bytes: [ 0x8f, 0xff, 0x83, 0x11 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor d1, d15, #0x3f"
+  -
+    input:
+      bytes: [ 0xfc, 0x2e ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "loop a2, #-0x4"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0x41, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "itof d15, d0"
+  -
+    input:
+      bytes: [ 0x10, 0xd4 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addsc.a a4, a13, d15, #0"
+  -
+    input:
+      bytes: [ 0x8b, 0x08, 0x01, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d1, d8, #0x10"
+  -
+    input:
+      bytes: [ 0x40, 0xf4 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.aa a4, a15"
+  -
+    input:
+      bytes: [ 0x82, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d1, #0"
+  -
+    input:
+      bytes: [ 0x3c, 0x11 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x22"
+  -
+    input:
+      bytes: [ 0x53, 0xc3, 0x20, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul d15, d3, #0xc"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x91, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x522"
+  -
+    input:
+      bytes: [ 0x7d, 0x4f, 0x0d, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne.a a15, a4, #0x1a"
+  -
+    input:
+      bytes: [ 0xee, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz d15, #0xc"
+  -
+    input:
+      bytes: [ 0xb7, 0x0f, 0x01, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, #0, #0x2, #0x1"
+  -
+    input:
+      bytes: [ 0x7f, 0x0f, 0x07, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jge.u d15, d0, #0xe"
+  -
+    input:
+      bytes: [ 0x3c, 0x1e ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x3c"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xf3, 0x0f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x1fe6"
+  -
+    input:
+      bytes: [ 0xa6, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or d0, d15"
+  -
+    input:
+      bytes: [ 0x82, 0x50 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d0, #0x5"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0x00, 0x86 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0x6200"
+  -
+    input:
+      bytes: [ 0x90, 0xdd ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addsc.a a13, a13, d15, #0x2"
+  -
+    input:
+      bytes: [ 0x10, 0xc2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addsc.a a2, a12, d15, #0"
+  -
+    input:
+      bytes: [ 0x5e, 0x13 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, #0x1, #0x6"
+  -
+    input:
+      bytes: [ 0x8f, 0x3c, 0x00, 0x41 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d4, d12, #0x3"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0x00, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0x3000"
+  -
+    input:
+      bytes: [ 0x53, 0x89, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul d0, d9, #0x8"
+  -
+    input:
+      bytes: [ 0x53, 0x84, 0x20, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul d15, d4, #0x8"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0x02, 0xc0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0x302"
+  -
+    input:
+      bytes: [ 0x7e, 0x93 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, d9, #0x6"
+  -
+    input:
+      bytes: [ 0x37, 0x0f, 0x81, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, d0, #0x1, #0x1"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xf1, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x1e2"
+  -
+    input:
+      bytes: [ 0xc2, 0xf8 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d8, #-0x1"
+  -
+    input:
+      bytes: [ 0x37, 0x0f, 0x81, 0xf7 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, d0, #0xf, #0x1"
+  -
+    input:
+      bytes: [ 0x37, 0x01, 0xe2, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d15, d1, #0x1, #0x2"
+  -
+    input:
+      bytes: [ 0x8f, 0x3f, 0x00, 0x30 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh d3, d15, #0x3"
+  -
+    input:
+      bytes: [ 0x37, 0xf3, 0x08, 0x30 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d3, d3, d15, #0, #0x8"
+  -
+    input:
+      bytes: [ 0x53, 0x88, 0x21, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul d15, d8, #0x18"
+  -
+    input:
+      bytes: [ 0xd9, 0x22, 0x0c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a2, [a2]#0xc"
+  -
+    input:
+      bytes: [ 0x5e, 0x1e ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, #0x1, #0x1c"
+  -
+    input:
+      bytes: [ 0x53, 0x88, 0x20, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul d15, d8, #0x8"
+  -
+    input:
+      bytes: [ 0x37, 0x0f, 0x68, 0x0c ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d0, d15, #0x18, #0x8"
+  -
+    input:
+      bytes: [ 0x60, 0xc2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.a a2, d12"
+  -
+    input:
+      bytes: [ 0xd9, 0x22, 0x08, 0x26 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a2, [a2]#0x6088"
+  -
+    input:
+      bytes: [ 0x76, 0xcf ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d12, #0x1e"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xdc, 0xfe ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x248"
+  -
+    input:
+      bytes: [ 0xc2, 0x31 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d1, #0x3"
+  -
+    input:
+      bytes: [ 0x8f, 0xff, 0x83, 0x21 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor d2, d15, #0x3f"
+  -
+    input:
+      bytes: [ 0x0f, 0x10, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh d0, d0, d1"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xee, 0xfa ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0xa24"
+  -
+    input:
+      bytes: [ 0x9b, 0x14, 0x85, 0x43 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addih d4, d4, #0x3851"
+  -
+    input:
+      bytes: [ 0x0f, 0x05, 0x10, 0x50 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha d5, d5, d0"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x06, 0xfe ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x3f4"
+  -
+    input:
+      bytes: [ 0x3b, 0x80, 0x00, 0x40 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d4, #0x8"
+  -
+    input:
+      bytes: [ 0x91, 0x30, 0x00, 0x3f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a3, #0xf003"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xb7, 0xfe ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x292"
+  -
+    input:
+      bytes: [ 0xc2, 0x18 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d8, #0x1"
+  -
+    input:
+      bytes: [ 0x82, 0x0b ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d11, #0"
+  -
+    input:
+      bytes: [ 0x6f, 0x1f, 0x12, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.t d15, #0x1, #0x24"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xa9, 0xfb ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x8ae"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x6b, 0x0b ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x16d6"
+  -
+    input:
+      bytes: [ 0xb7, 0x0f, 0x08, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, #0, #0, #0x8"
+  -
+    input:
+      bytes: [ 0xdf, 0x0c, 0x9b, 0x7f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d12, #0, #-0xca"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x83, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0xfa"
+  -
+    input:
+      bytes: [ 0x8f, 0x00, 0x21, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha d0, d0, #0x10"
+  -
+    input:
+      bytes: [ 0x3f, 0x0f, 0x04, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt.u d15, d0, #0x8"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x0d, 0xfe ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x3e6"
+  -
+    input:
+      bytes: [ 0xd9, 0x22, 0x14, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a2, [a2]#0x2014"
+  -
+    input:
+      bytes: [ 0x82, 0x0c ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d12, #0"
+  -
+    input:
+      bytes: [ 0x40, 0xc4 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.aa a4, a12"
+  -
+    input:
+      bytes: [ 0x37, 0x00, 0x70, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d0, d0, #0x10, #0x10"
+  -
+    input:
+      bytes: [ 0x4b, 0xf0, 0x11, 0x22 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "div.u e2, d0, d15"
+  -
+    input:
+      bytes: [ 0x9b, 0x10, 0x13, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addih d0, d0, #0x131"
+  -
+    input:
+      bytes: [ 0x3c, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0xe"
+  -
+    input:
+      bytes: [ 0xbe, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d0, #0x2a"
+  -
+    input:
+      bytes: [ 0x60, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.a a15, d15"
+  -
+    input:
+      bytes: [ 0x82, 0xf2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d2, #-0x1"
+  -
+    input:
+      bytes: [ 0x6e, 0xfa ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d15, #-0xc"
+  -
+    input:
+      bytes: [ 0x01, 0x20, 0x00, 0x26 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addsc.a a2, a2, d0, #0"
+  -
+    input:
+      bytes: [ 0x4b, 0xf1, 0x51, 0x20 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "div.f d2, d1, d15"
+  -
+    input:
+      bytes: [ 0x3b, 0x00, 0x40, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d15, #0x400"
+  -
+    input:
+      bytes: [ 0x06, 0xf4 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh d4, #-0x1"
+  -
+    input:
+      bytes: [ 0x37, 0x0f, 0xe1, 0xf3 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d15, d15, #0x7, #0x1"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xf2, 0xfc ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x61c"
+  -
+    input:
+      bytes: [ 0x3c, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0xa"
+  -
+    input:
+      bytes: [ 0x5e, 0x1a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, #0x1, #0x14"
+  -
+    input:
+      bytes: [ 0x82, 0x1a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d10, #0x1"
+  -
+    input:
+      bytes: [ 0x80, 0xf4 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.d d4, a15"
+  -
+    input:
+      bytes: [ 0x8f, 0xf8, 0x01, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d15, d8, #0x1f"
+  -
+    input:
+      bytes: [ 0x16, 0x1f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d15, #0x1f"
+  -
+    input:
+      bytes: [ 0x49, 0xf5, 0x00, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a5, [a15]#0"
+  -
+    input:
+      bytes: [ 0x37, 0x0f, 0x64, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d0, d15, #0x4, #0x4"
+  -
+    input:
+      bytes: [ 0x0f, 0x3f, 0x00, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh d15, d15, d3"
+  -
+    input:
+      bytes: [ 0xb4, 0xaf ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [sp], d15"
+  -
+    input:
+      bytes: [ 0x49, 0xff, 0x20, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0x20"
+  -
+    input:
+      bytes: [ 0x37, 0xf0, 0x02, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d0, d15, #0, #0x2"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x4e, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x164"
+  -
+    input:
+      bytes: [ 0x2e, 0x1b ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.t d15, #0x1, #0x16"
+  -
+    input:
+      bytes: [ 0x3c, 0x50 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0xa0"
+  -
+    input:
+      bytes: [ 0x4b, 0x2f, 0x41, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.f d15, d15, d2"
+  -
+    input:
+      bytes: [ 0x8b, 0xf4, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d0, d4, #0xf"
+  -
+    input:
+      bytes: [ 0xdf, 0x10, 0x2b, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d0, #0x1, #0x56"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0xc2, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0xc02"
+  -
+    input:
+      bytes: [ 0xdf, 0x19, 0x49, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d9, #0x1, #0x92"
+  -
+    input:
+      bytes: [ 0x4b, 0xf0, 0x11, 0x42 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "div.u e4, d0, d15"
+  -
+    input:
+      bytes: [ 0xbf, 0x45, 0x0b, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt.u d5, #0x4, #0x16"
+  -
+    input:
+      bytes: [ 0x3c, 0x94 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #-0xd8"
+  -
+    input:
+      bytes: [ 0x40, 0x4c ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.aa a12, a4"
+  -
+    input:
+      bytes: [ 0x92, 0x11 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d1, d15, #0x1"
+  -
+    input:
+      bytes: [ 0x9b, 0x11, 0x13, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addih d1, d1, #0x131"
+  -
+    input:
+      bytes: [ 0x6f, 0x1f, 0xfa, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz.t d15, #0x1, #-0xc"
+  -
+    input:
+      bytes: [ 0x26, 0x0f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d15, d0"
+  -
+    input:
+      bytes: [ 0x49, 0xff, 0x00, 0x1a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0x40"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xbe, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x84"
+  -
+    input:
+      bytes: [ 0xe2, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul d0, d1"
+  -
+    input:
+      bytes: [ 0x60, 0xf2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.a a2, d15"
+  -
+    input:
+      bytes: [ 0x96, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or d15, #0x2"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xe1, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x1c2"
+  -
+    input:
+      bytes: [ 0x3b, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d0, #0x400"
+  -
+    input:
+      bytes: [ 0x80, 0xf2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.d d2, a15"
+  -
+    input:
+      bytes: [ 0xda, 0x1f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d15, #0x1f"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0x0c, 0x46 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0x610c"
+  -
+    input:
+      bytes: [ 0x4b, 0x0f, 0x61, 0x21 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "utof d2, d15"
+  -
+    input:
+      bytes: [ 0xbb, 0x00, 0xc2, 0x2b ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.u d2, #0xbc20"
+  -
+    input:
+      bytes: [ 0x8b, 0xf0, 0x2f, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "min.u d0, d0, #0xff"
+  -
+    input:
+      bytes: [ 0x3c, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x20"
+  -
+    input:
+      bytes: [ 0x8f, 0x20, 0x00, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh d1, d0, #0x2"
+  -
+    input:
+      bytes: [ 0x3e, 0x0c ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d0, #0x18"
+  -
+    input:
+      bytes: [ 0x8f, 0x24, 0x40, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or d15, d4, #0x2"
+  -
+    input:
+      bytes: [ 0x8f, 0x24, 0x20, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha d15, d4, #0x2"
+  -
+    input:
+      bytes: [ 0x8b, 0x87, 0x01, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d0, d7, #0x18"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0x80, 0xcb ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#-0x4500"
+  -
+    input:
+      bytes: [ 0x49, 0xf4, 0x00, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a4, [a15]#0"
+  -
+    input:
+      bytes: [ 0x76, 0xdb ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d13, #0x16"
+  -
+    input:
+      bytes: [ 0x6e, 0x29 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d15, #0x52"
+  -
+    input:
+      bytes: [ 0xb7, 0x0f, 0x01, 0xf3 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, #0, #0x6, #0x1"
+  -
+    input:
+      bytes: [ 0xbe, 0x0c ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d0, #0x38"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x6a, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x12c"
+  -
+    input:
+      bytes: [ 0x20, 0x60 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub.a sp, #0x60"
+  -
+    input:
+      bytes: [ 0x91, 0x00, 0x00, 0x46 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a4, #0x6000"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0x2c, 0x11 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0x106c"
+  -
+    input:
+      bytes: [ 0x96, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or d15, #0x3"
+  -
+    input:
+      bytes: [ 0xc2, 0x19 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d9, #0x1"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xcb, 0xfd ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x46a"
+  -
+    input:
+      bytes: [ 0x9b, 0x6f, 0x58, 0xf3 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addih d15, d15, #0x3586"
+  -
+    input:
+      bytes: [ 0xd9, 0x33, 0xc0, 0x4f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a3, [a3]#-0x300"
+  -
+    input:
+      bytes: [ 0x3b, 0x90, 0x00, 0x40 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d4, #0x9"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x8d, 0xfe ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x2e6"
+  -
+    input:
+      bytes: [ 0x91, 0x30, 0x00, 0xcf ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a12, #0xf003"
+  -
+    input:
+      bytes: [ 0xd9, 0x22, 0x0c, 0x16 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a2, [a2]#0x604c"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xf0, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x9e0"
+  -
+    input:
+      bytes: [ 0xb7, 0x7f, 0x08, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, #0x7, #0, #0x8"
+  -
+    input:
+      bytes: [ 0x8f, 0x3f, 0x00, 0xd1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d13, d15, #0x3"
+  -
+    input:
+      bytes: [ 0x7b, 0x00, 0x27, 0xf4 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh d15, #0x4270"
+  -
+    input:
+      bytes: [ 0xfc, 0x29 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "loop a2, #-0xe"
+  -
+    input:
+      bytes: [ 0xb7, 0x2f, 0x82, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, #0x2, #0x1, #0x2"
+  -
+    input:
+      bytes: [ 0x0f, 0xa0, 0x10, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha d0, d0, d10"
+  -
+    input:
+      bytes: [ 0x53, 0x41, 0x20, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul d1, d1, #0x4"
+  -
+    input:
+      bytes: [ 0x5e, 0x32 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, #0x3, #0x4"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x32, 0xfa ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0xb9c"
+  -
+    input:
+      bytes: [ 0x3b, 0x00, 0x5a, 0xf2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d15, #0x25a0"
+  -
+    input:
+      bytes: [ 0x8f, 0xec, 0x1f, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh d15, d12, #-0x2"
+  -
+    input:
+      bytes: [ 0x37, 0xf0, 0x05, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d0, d15, #0, #0x5"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x0e, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x1c"
+  -
+    input:
+      bytes: [ 0xc6, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor d0, d15"
+  -
+    input:
+      bytes: [ 0x53, 0x48, 0x20, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul d15, d8, #0x4"
+  -
+    input:
+      bytes: [ 0x37, 0x0f, 0x68, 0x40 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d4, d15, #0, #0x8"
+  -
+    input:
+      bytes: [ 0xd9, 0x22, 0xc0, 0x0d ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a2, [a2]#-0x2400"
+  -
+    input:
+      bytes: [ 0x80, 0x41 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.d d1, a4"
+  -
+    input:
+      bytes: [ 0x82, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d0, #0x1"
+  -
+    input:
+      bytes: [ 0x20, 0x38 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub.a sp, #0x38"
+  -
+    input:
+      bytes: [ 0x91, 0x00, 0x80, 0x2f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a2, #0xf800"
+  -
+    input:
+      bytes: [ 0x7b, 0x00, 0x00, 0x11 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh d1, #0x1000"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x9a, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x1134"
+  -
+    input:
+      bytes: [ 0xd9, 0x3f, 0x00, 0x46 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a3]#0x6100"
+  -
+    input:
+      bytes: [ 0x37, 0x0f, 0x81, 0xf2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, d0, #0x5, #0x1"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x0a, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x1414"
+  -
+    input:
+      bytes: [ 0x4b, 0x0f, 0x71, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ftouz d0, d15"
+  -
+    input:
+      bytes: [ 0x5e, 0x23 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, #0x2, #0x6"
+  -
+    input:
+      bytes: [ 0x91, 0x20, 0x00, 0x27 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a2, #0x7002"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x1e, 0xfd ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x5c4"
+  -
+    input:
+      bytes: [ 0x4b, 0x0f, 0x41, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.f d15, d15, d0"
+  -
+    input:
+      bytes: [ 0x10, 0xdf ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addsc.a a15, a13, d15, #0"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x89, 0xfa ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0xaee"
+  -
+    input:
+      bytes: [ 0x82, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d2, #0"
+  -
+    input:
+      bytes: [ 0xa2, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub d0, d1"
+  -
+    input:
+      bytes: [ 0x37, 0x00, 0x68, 0x40 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d4, d0, #0, #0x8"
+  -
+    input:
+      bytes: [ 0x4b, 0xf2, 0x41, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.f d1, d2, d15"
+  -
+    input:
+      bytes: [ 0xd9, 0x22, 0x00, 0x26 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a2, [a2]#0x6080"
+  -
+    input:
+      bytes: [ 0x37, 0x03, 0x68, 0xf4 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d15, d3, #0x8, #0x8"
+  -
+    input:
+      bytes: [ 0xb7, 0x4f, 0x08, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, #0x4, #0, #0x8"
+  -
+    input:
+      bytes: [ 0xd9, 0x99, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a9, [a9]#0"
+  -
+    input:
+      bytes: [ 0xd9, 0x44, 0x0c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a4, [a4]#0xc"
+  -
+    input:
+      bytes: [ 0xee, 0x13 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz d15, #0x26"
+  -
+    input:
+      bytes: [ 0x9a, 0x14 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d15, d4, #0x1"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0xa8, 0x92 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0x2a68"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xa6, 0xfe ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x2b4"
+  -
+    input:
+      bytes: [ 0x89, 0x40, 0xc1, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachei.wi [a4+]#0x1"
+  -
+    input:
+      bytes: [ 0xbf, 0x48, 0xb1, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt.u d8, #0x4, #-0x9e"
+  -
+    input:
+      bytes: [ 0xac, 0xa1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [sp]#0x2, d15"
+  -
+    input:
+      bytes: [ 0xbb, 0x00, 0xc2, 0x0b ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.u d0, #0xbc20"
+  -
+    input:
+      bytes: [ 0x4b, 0x0f, 0x41, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "itof d15, d15"
+  -
+    input:
+      bytes: [ 0xdc, 0x0f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ji a15"
+  -
+    input:
+      bytes: [ 0x9b, 0x8f, 0xb9, 0xf4 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addih d15, d15, #0x4b98"
+  -
+    input:
+      bytes: [ 0xee, 0xfa ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz d15, #-0xc"
+  -
+    input:
+      bytes: [ 0x06, 0x50 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh d0, #0x5"
+  -
+    input:
+      bytes: [ 0x4b, 0x10, 0x01, 0x22 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "div e2, d0, d1"
+  -
+    input:
+      bytes: [ 0x37, 0x0f, 0x02, 0xf4 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, d0, #0x8, #0x2"
+  -
+    input:
+      bytes: [ 0xd9, 0x22, 0xc0, 0x0b ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a2, [a2]#-0x4400"
+  -
+    input:
+      bytes: [ 0x6f, 0x0f, 0xfe, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz.t d15, #0, #-0x4"
+  -
+    input:
+      bytes: [ 0x15, 0xd0, 0xc0, 0xeb ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldlcx #0xd0003f80"
+  -
+    input:
+      bytes: [ 0x3c, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x2"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xaf, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0xa2"
+  -
+    input:
+      bytes: [ 0x4b, 0x0f, 0x61, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "utof d15, d15"
+  -
+    input:
+      bytes: [ 0x91, 0x00, 0x00, 0x56 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a5, #0x6000"
+  -
+    input:
+      bytes: [ 0x53, 0xc2, 0x20, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul d15, d2, #0xc"
+  -
+    input:
+      bytes: [ 0x91, 0x20, 0x00, 0xa7 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a sp, #0x7002"
+  -
+    input:
+      bytes: [ 0x3c, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x14"
+  -
+    input:
+      bytes: [ 0xda, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d15, #0x10"
+  -
+    input:
+      bytes: [ 0xd9, 0xaa, 0x40, 0x89 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea sp, [sp]#-0x6a00"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x02, 0xfe ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x3fc"
+  -
+    input:
+      bytes: [ 0xb7, 0x0f, 0x02, 0xf2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, #0, #0x4, #0x2"
+  -
+    input:
+      bytes: [ 0x7b, 0x00, 0x1f, 0xf4 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh d15, #0x41f0"
+  -
+    input:
+      bytes: [ 0xc2, 0x11 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d1, #0x1"
+  -
+    input:
+      bytes: [ 0x3c, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x10"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xca, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x194"
+  -
+    input:
+      bytes: [ 0x76, 0xc5 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d12, #0xa"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x27, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x24e"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xab, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x556"
+  -
+    input:
+      bytes: [ 0x82, 0x14 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d4, #0x1"
+  -
+    input:
+      bytes: [ 0x91, 0x50, 0x88, 0x4f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a4, #0xf885"
+  -
+    input:
+      bytes: [ 0xbf, 0x30, 0xea, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt.u d0, #0x3, #-0x2c"
+  -
+    input:
+      bytes: [ 0x0f, 0x04, 0x10, 0x40 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha d4, d4, d0"
+  -
+    input:
+      bytes: [ 0x37, 0x0f, 0x6e, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d15, d15, #0x2, #0xe"
+  -
+    input:
+      bytes: [ 0xd9, 0xcc, 0x14, 0x36 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a12, [a12]#0x60d4"
+  -
+    input:
+      bytes: [ 0xb7, 0x0f, 0x0c, 0xfa ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, #0, #0x14, #0xc"
+  -
+    input:
+      bytes: [ 0x86, 0x24 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha d4, #0x2"
+  -
+    input:
+      bytes: [ 0x82, 0x12 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d2, #0x1"
+  -
+    input:
+      bytes: [ 0x4b, 0x20, 0x01, 0x22 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "div e2, d0, d2"
+  -
+    input:
+      bytes: [ 0x02, 0xf4 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d4, d15"
+  -
+    input:
+      bytes: [ 0x4b, 0x0f, 0x71, 0x41 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ftouz d4, d15"
+  -
+    input:
+      bytes: [ 0x26, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d0, d15"
+  -
+    input:
+      bytes: [ 0x37, 0x0f, 0x01, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, d0, #0x2, #0x1"
+  -
+    input:
+      bytes: [ 0x82, 0xf3 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d3, #-0x1"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x7a, 0xfb ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x90c"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x19, 0xfe ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x3ce"
+  -
+    input:
+      bytes: [ 0xa2, 0xdc ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub d12, d13"
+  -
+    input:
+      bytes: [ 0x82, 0x17 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d7, #0x1"
+  -
+    input:
+      bytes: [ 0x5e, 0x1b ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, #0x1, #0x16"
+  -
+    input:
+      bytes: [ 0x2d, 0x02, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "calli a2"
+  -
+    input:
+      bytes: [ 0x89, 0xa2, 0x86, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [sp]#0x6, d2"
+  -
+    input:
+      bytes: [ 0x49, 0xf2, 0x24, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a2, [a15]#0x24"
+  -
+    input:
+      bytes: [ 0xd9, 0xaa, 0x40, 0x8b ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea sp, [sp]#-0x4a00"
+  -
+    input:
+      bytes: [ 0x37, 0x0f, 0x61, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d15, d15, #0x2, #0x1"
+  -
+    input:
+      bytes: [ 0x8f, 0x0f, 0x1f, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh d0, d15, #-0x10"
+  -
+    input:
+      bytes: [ 0x6e, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d15, #0x6"
+  -
+    input:
+      bytes: [ 0x20, 0x20 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub.a sp, #0x20"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xda, 0xfe ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x24c"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x18, 0xfb ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x9d0"
+  -
+    input:
+      bytes: [ 0xda, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d15, #0x3"
+  -
+    input:
+      bytes: [ 0x02, 0x4f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d15, d4"
+  -
+    input:
+      bytes: [ 0x6e, 0x2d ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d15, #0x5a"
+  -
+    input:
+      bytes: [ 0x10, 0xd2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addsc.a a2, a13, d15, #0"
+  -
+    input:
+      bytes: [ 0xc2, 0xe0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d0, #-0x2"
+  -
+    input:
+      bytes: [ 0x3c, 0x34 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x68"
+  -
+    input:
+      bytes: [ 0x96, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or d15, #0x8"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xb3, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x9a"
+  -
+    input:
+      bytes: [ 0x3c, 0x37 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x6e"
+  -
+    input:
+      bytes: [ 0x91, 0x10, 0x00, 0x30 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a3, #0x1"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xe0, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x40"
+  -
+    input:
+      bytes: [ 0x76, 0x13 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d1, #0x6"
+  -
+    input:
+      bytes: [ 0x80, 0x20 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.d d0, a2"
+  -
+    input:
+      bytes: [ 0xfd, 0xf0, 0xed, 0x7f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "loop a15, #-0x26"
+  -
+    input:
+      bytes: [ 0x1d, 0xff, 0x77, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #-0x112"
+  -
+    input:
+      bytes: [ 0x91, 0x30, 0x00, 0x2f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a2, #0xf003"
+  -
+    input:
+      bytes: [ 0x7f, 0x81, 0x0a, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jge.u d1, d8, #0x14"
+  -
+    input:
+      bytes: [ 0xa2, 0x1f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub d15, d1"
+  -
+    input:
+      bytes: [ 0x10, 0x22 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addsc.a a2, a2, d15, #0"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x45, 0xfb ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x976"
+  -
+    input:
+      bytes: [ 0x82, 0x11 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d1, #0x1"
+  -
+    input:
+      bytes: [ 0x53, 0x4f, 0x20, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul d15, d15, #0x4"
+  -
+    input:
+      bytes: [ 0x9a, 0xf2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d15, d2, #-0x1"
+  -
+    input:
+      bytes: [ 0x40, 0x5c ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.aa a12, a5"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x72, 0x0b ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x16e4"
+  -
+    input:
+      bytes: [ 0x16, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d15, #0x3"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x47, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x48e"
+  -
+    input:
+      bytes: [ 0xd9, 0x22, 0x14, 0x36 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a2, [a2]#0x60d4"
+  -
+    input:
+      bytes: [ 0x91, 0x00, 0x00, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a8, #0"
+  -
+    input:
+      bytes: [ 0xb7, 0x6f, 0x08, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, #0x6, #0, #0x8"
+  -
+    input:
+      bytes: [ 0xd9, 0x22, 0x88, 0xc2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a2, [a2]#0x2b08"
+  -
+    input:
+      bytes: [ 0x91, 0x20, 0x00, 0x5f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a5, #0xf002"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xb3, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x566"
+  -
+    input:
+      bytes: [ 0x49, 0xf2, 0x1c, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a2, [a15]#0x1c"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0x9c, 0x82 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0x2a1c"
+  -
+    input:
+      bytes: [ 0x82, 0x19 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d9, #0x1"
+  -
+    input:
+      bytes: [ 0x30, 0xf3 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add.a a3, a15"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x15, 0x0c ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x182a"
+  -
+    input:
+      bytes: [ 0x37, 0xf0, 0x01, 0xf2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d0, d15, #0x4, #0x1"
+  -
+    input:
+      bytes: [ 0x3b, 0xf0, 0x0f, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d0, #0xff"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0xb4, 0x82 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0x2a34"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xc6, 0xfb ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x874"
+  -
+    input:
+      bytes: [ 0x8f, 0x3f, 0x00, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d0, d15, #0x3"
+  -
+    input:
+      bytes: [ 0x4b, 0xf0, 0x11, 0x82 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "div.u e8, d0, d15"
+  -
+    input:
+      bytes: [ 0x96, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or d15, #0x10"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x37, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x192"
+  -
+    input:
+      bytes: [ 0xc2, 0xfc ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d12, #-0x1"
+  -
+    input:
+      bytes: [ 0x37, 0x0f, 0x04, 0xf2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, d0, #0x4, #0x4"
+  -
+    input:
+      bytes: [ 0x91, 0x30, 0x00, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a15, #0xf003"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x50, 0x0c ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x18a0"
+  -
+    input:
+      bytes: [ 0x02, 0x92 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d2, d9"
+  -
+    input:
+      bytes: [ 0xda, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d15, #0"
+  -
+    input:
+      bytes: [ 0x4b, 0x10, 0x11, 0x82 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "div.u e8, d0, d1"
+  -
+    input:
+      bytes: [ 0x02, 0xf2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d2, d15"
+  -
+    input:
+      bytes: [ 0xa0, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.a a4, #0"
+  -
+    input:
+      bytes: [ 0x53, 0x42, 0x20, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul d15, d2, #0x4"
+  -
+    input:
+      bytes: [ 0x37, 0x0f, 0xe7, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d15, d15, #0x1, #0x7"
+  -
+    input:
+      bytes: [ 0xfc, 0x2f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "loop a2, #-0x2"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x5f, 0x0c ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x18be"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xde, 0xfa ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0xa44"
+  -
+    input:
+      bytes: [ 0x1d, 0x00, 0x02, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x4"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x5a, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x4b4"
+  -
+    input:
+      bytes: [ 0xb7, 0x0f, 0x01, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, #0, #0, #0x1"
+  -
+    input:
+      bytes: [ 0xb7, 0x0f, 0x14, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, #0, #0, #0x14"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xd6, 0xfd ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x454"
+  -
+    input:
+      bytes: [ 0x40, 0xd4 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.aa a4, a13"
+  -
+    input:
+      bytes: [ 0x49, 0x40, 0x40, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldmst [a4]#0, e0"
+  -
+    input:
+      bytes: [ 0x3c, 0x12 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x24"
+  -
+    input:
+      bytes: [ 0x91, 0x00, 0x00, 0x28 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a2, #0x8000"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xb4, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x98"
+  -
+    input:
+      bytes: [ 0xc5, 0x02, 0x3f, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a2, #0x3f"
+  -
+    input:
+      bytes: [ 0x8f, 0x34, 0x40, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or d15, d4, #0x3"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x65, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x12ca"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x41, 0x0f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x1e82"
+  -
+    input:
+      bytes: [ 0x3b, 0x00, 0x28, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d8, #0x280"
+  -
+    input:
+      bytes: [ 0x80, 0x4f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.d d15, a4"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0x8c, 0x62 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0x298c"
+  -
+    input:
+      bytes: [ 0xc6, 0xf3 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor d3, d15"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xd6, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x54"
+  -
+    input:
+      bytes: [ 0xb4, 0xa2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [sp], d2"
+  -
+    input:
+      bytes: [ 0x15, 0xd0, 0xc0, 0xe3 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "stlcx #0xd0003f80"
+  -
+    input:
+      bytes: [ 0xbb, 0xf0, 0xff, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.u d15, #0xffff"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x04, 0xfe ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x3f8"
+  -
+    input:
+      bytes: [ 0xda, 0x20 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d15, #0x20"
+  -
+    input:
+      bytes: [ 0x53, 0x40, 0x20, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul d15, d0, #0x4"
+  -
+    input:
+      bytes: [ 0xe2, 0x1f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul d15, d1"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0xe4, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0xfe4"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xf1, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x5e2"
+  -
+    input:
+      bytes: [ 0x37, 0xaf, 0x02, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, d10, #0, #0x2"
+  -
+    input:
+      bytes: [ 0x91, 0x20, 0x00, 0xf6 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a15, #0x6002"
+  -
+    input:
+      bytes: [ 0x06, 0x3f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh d15, #0x3"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0x10, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0x10"
+  -
+    input:
+      bytes: [ 0xde, 0x25 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, #0x2, #0x2a"
+  -
+    input:
+      bytes: [ 0x92, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d0, d15, #0x1"
+  -
+    input:
+      bytes: [ 0x7f, 0xf8, 0x0d, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jge.u d8, d15, #0x1a"
+  -
+    input:
+      bytes: [ 0x8f, 0x3c, 0x00, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d0, d12, #0x3"
+  -
+    input:
+      bytes: [ 0x3c, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x4"
+  -
+    input:
+      bytes: [ 0xdf, 0x1f, 0xfb, 0x7f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, #0x1, #-0xa"
+  -
+    input:
+      bytes: [ 0x8f, 0x4f, 0x1f, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh d1, d15, #-0xc"
+  -
+    input:
+      bytes: [ 0xd9, 0x44, 0x30, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a4, [a4]#0x30"
+  -
+    input:
+      bytes: [ 0x3c, 0x17 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x2e"
+  -
+    input:
+      bytes: [ 0x37, 0xf0, 0x01, 0x0f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d0, d0, d15, #0x1e, #0x1"
+  -
+    input:
+      bytes: [ 0x82, 0x30 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d0, #0x3"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xe8, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x30"
+  -
+    input:
+      bytes: [ 0x6e, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d15, #0x8"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0xe0, 0xe0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0xfa0"
+  -
+    input:
+      bytes: [ 0x3c, 0x1c ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x38"
+  -
+    input:
+      bytes: [ 0x4b, 0x10, 0x11, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "div.u e0, d0, d1"
+  -
+    input:
+      bytes: [ 0x3c, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0xc"
+  -
+    input:
+      bytes: [ 0xa6, 0x0f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or d15, d0"
+  -
+    input:
+      bytes: [ 0x3e, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d0, #0x8"
+  -
+    input:
+      bytes: [ 0xdf, 0x10, 0xee, 0x7f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d0, #0x1, #-0x24"
+  -
+    input:
+      bytes: [ 0x76, 0x17 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d1, #0xe"
+  -
+    input:
+      bytes: [ 0x40, 0xd5 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.aa a5, a13"
+  -
+    input:
+      bytes: [ 0xbf, 0x21, 0xcd, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt.u d1, #0x2, #-0x66"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0x30, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0x30"
+  -
+    input:
+      bytes: [ 0xa6, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or d1, d15"
+  -
+    input:
+      bytes: [ 0x7b, 0x00, 0x37, 0xf4 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh d15, #0x4370"
+  -
+    input:
+      bytes: [ 0xbb, 0xf0, 0xff, 0x2f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.u d2, #0xffff"
+  -
+    input:
+      bytes: [ 0x77, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "dextr d0, d0, d0, #0x8"
+  -
+    input:
+      bytes: [ 0x3c, 0xd9 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #-0x4e"
+  -
+    input:
+      bytes: [ 0xd9, 0x22, 0x30, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a2, [a2]#0x6030"
+  -
+    input:
+      bytes: [ 0x37, 0x0f, 0x02, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, d0, #0, #0x2"
+  -
+    input:
+      bytes: [ 0x01, 0x28, 0x00, 0x26 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addsc.a a2, a2, d8, #0"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x58, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x150"
+  -
+    input:
+      bytes: [ 0x53, 0x4a, 0x20, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul d15, d10, #0x4"
+  -
+    input:
+      bytes: [ 0xd9, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a0, [a0]#0"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0x40, 0x20 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0x480"
+  -
+    input:
+      bytes: [ 0x53, 0x41, 0x20, 0x30 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul d3, d1, #0x4"
+  -
+    input:
+      bytes: [ 0xac, 0xa3 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [sp]#0x6, d15"
+  -
+    input:
+      bytes: [ 0xee, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz d15, #0x10"
+  -
+    input:
+      bytes: [ 0x3c, 0x29 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x52"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0x0a, 0xa0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0x28a"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0xdc, 0xd0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0xf5c"
+  -
+    input:
+      bytes: [ 0x26, 0x32 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d2, d3"
+  -
+    input:
+      bytes: [ 0x40, 0x54 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.aa a4, a5"
+  -
+    input:
+      bytes: [ 0xee, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz d15, #0x6"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x15, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x2a"
+  -
+    input:
+      bytes: [ 0x76, 0x27 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d2, #0xe"
+  -
+    input:
+      bytes: [ 0x1e, 0x32 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, #0x3, #0x4"
+  -
+    input:
+      bytes: [ 0x37, 0xf1, 0x08, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d1, d15, #0, #0x8"
+  -
+    input:
+      bytes: [ 0x02, 0xa4 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d4, d10"
+  -
+    input:
+      bytes: [ 0x5f, 0x0f, 0x24, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d0, #0x48"
+  -
+    input:
+      bytes: [ 0x37, 0x3f, 0x02, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, d3, #0, #0x2"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x5b, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0xcb6"
+  -
+    input:
+      bytes: [ 0x8b, 0x87, 0x01, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d1, d7, #0x18"
+  -
+    input:
+      bytes: [ 0x82, 0x24 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d4, #0x2"
+  -
+    input:
+      bytes: [ 0x49, 0xf2, 0x14, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a2, [a15]#0x14"
+  -
+    input:
+      bytes: [ 0x37, 0x0f, 0x68, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d15, d15, #0, #0x8"
+  -
+    input:
+      bytes: [ 0xa6, 0x5f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or d15, d5"
+  -
+    input:
+      bytes: [ 0x91, 0x20, 0x00, 0x25 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a2, #0x5002"
+  -
+    input:
+      bytes: [ 0xde, 0x1e ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, #0x1, #0x3c"
+  -
+    input:
+      bytes: [ 0x96, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or d15, #0x1"
+  -
+    input:
+      bytes: [ 0xb7, 0x7f, 0x03, 0xfe ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, #0x7, #0x1c, #0x3"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x02, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x204"
+  -
+    input:
+      bytes: [ 0x37, 0x0f, 0x04, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, d0, #0, #0x4"
+  -
+    input:
+      bytes: [ 0x02, 0xd4 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d4, d13"
+  -
+    input:
+      bytes: [ 0x49, 0x42, 0x00, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a2, [a4]#0"
+  -
+    input:
+      bytes: [ 0xdf, 0x1f, 0x5d, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, #0x1, #0xba"
+  -
+    input:
+      bytes: [ 0x37, 0xf0, 0x03, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d0, d15, #0, #0x3"
+  -
+    input:
+      bytes: [ 0x8f, 0xff, 0x83, 0x81 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor d8, d15, #0x3f"
+  -
+    input:
+      bytes: [ 0x02, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d8, d0"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x1f, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x43e"
+  -
+    input:
+      bytes: [ 0x49, 0x33, 0x08, 0x8a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a3, [a3]#-0x1f8"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x72, 0x12 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x24e4"
+  -
+    input:
+      bytes: [ 0x37, 0x04, 0x68, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d0, d4, #0, #0x8"
+  -
+    input:
+      bytes: [ 0x3b, 0x00, 0xd0, 0x12 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d1, #0x2d00"
+  -
+    input:
+      bytes: [ 0xda, 0x0f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d15, #0xf"
+  -
+    input:
+      bytes: [ 0x8f, 0x28, 0x20, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha d15, d8, #0x2"
+  -
+    input:
+      bytes: [ 0x10, 0xe4 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addsc.a a4, a14, d15, #0"
+  -
+    input:
+      bytes: [ 0xa6, 0x28 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or d8, d2"
+  -
+    input:
+      bytes: [ 0xb7, 0x0f, 0x1c, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, #0, #0, #0x1c"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xea, 0x11 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x23d4"
+  -
+    input:
+      bytes: [ 0x7e, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, d0, #0xa"
+  -
+    input:
+      bytes: [ 0x4b, 0x02, 0x71, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ftouz d0, d2"
+  -
+    input:
+      bytes: [ 0x37, 0x01, 0x04, 0x14 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d1, d1, d0, #0x8, #0x4"
+  -
+    input:
+      bytes: [ 0x3c, 0x0e ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x1c"
+  -
+    input:
+      bytes: [ 0xd9, 0x22, 0x34, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a2, [a2]#0x6034"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xde, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x44"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0x00, 0x46 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0x6100"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x22, 0xfe ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x3bc"
+  -
+    input:
+      bytes: [ 0xd9, 0x22, 0x08, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a2, [a2]#0x8"
+  -
+    input:
+      bytes: [ 0x06, 0xec ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh d12, #-0x2"
+  -
+    input:
+      bytes: [ 0xc2, 0x81 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d1, #-0x8"
+  -
+    input:
+      bytes: [ 0x8f, 0x3f, 0x00, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh d1, d15, #0x3"
+  -
+    input:
+      bytes: [ 0x82, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d5, #0"
+  -
+    input:
+      bytes: [ 0x8b, 0xf2, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d0, d2, #0xf"
+  -
+    input:
+      bytes: [ 0xdf, 0x00, 0x2e, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d0, #0, #0x5c"
+  -
+    input:
+      bytes: [ 0xa0, 0x35 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.a a5, #0x3"
+  -
+    input:
+      bytes: [ 0xd9, 0x22, 0x04, 0x26 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a2, [a2]#0x6084"
+  -
+    input:
+      bytes: [ 0x4b, 0x08, 0x61, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "utof d0, d8"
+  -
+    input:
+      bytes: [ 0x06, 0xaf ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh d15, #-0x6"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x03, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x206"
+  -
+    input:
+      bytes: [ 0x37, 0x0f, 0xe1, 0xf2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d15, d15, #0x5, #0x1"
+  -
+    input:
+      bytes: [ 0x0f, 0xf1, 0x10, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha d1, d1, d15"
+  -
+    input:
+      bytes: [ 0xdf, 0x2f, 0x91, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, #0x2, #-0xde"
+  -
+    input:
+      bytes: [ 0x82, 0x20 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d0, #0x2"
+  -
+    input:
+      bytes: [ 0x8f, 0xf0, 0x83, 0x31 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor d3, d0, #0x3f"
+  -
+    input:
+      bytes: [ 0xd9, 0x55, 0x30, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a5, [a5]#0x30"
+  -
+    input:
+      bytes: [ 0xdf, 0x1f, 0xfe, 0x7f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, #0x1, #-0x4"
+  -
+    input:
+      bytes: [ 0x02, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d2, d0"
+  -
+    input:
+      bytes: [ 0xda, 0x40 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d15, #0x40"
+  -
+    input:
+      bytes: [ 0xc2, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d15, #-0x1"
+  -
+    input:
+      bytes: [ 0x16, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d15, #0x1"
+  -
+    input:
+      bytes: [ 0x80, 0xcf ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.d d15, a12"
+  -
+    input:
+      bytes: [ 0x82, 0x34 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d4, #0x3"
+  -
+    input:
+      bytes: [ 0x49, 0xff, 0x00, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x3a, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x1074"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x9c, 0xfa ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0xac8"
+  -
+    input:
+      bytes: [ 0x8f, 0x7f, 0x00, 0x21 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d2, d15, #0x7"
+  -
+    input:
+      bytes: [ 0x7f, 0x80, 0x04, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jge.u d0, d8, #0x8"
+  -
+    input:
+      bytes: [ 0x82, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d4, #0"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xbc, 0xfd ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x488"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xe8, 0xfb ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x830"
+  -
+    input:
+      bytes: [ 0x37, 0xf0, 0x07, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d0, d15, #0, #0x7"
+  -
+    input:
+      bytes: [ 0x3b, 0x00, 0x98, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d15, #0x980"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xbe, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x157c"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x00, 0xfc ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x800"
+  -
+    input:
+      bytes: [ 0x8b, 0x3f, 0x20, 0x43 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "min.u d4, d15, #0x3"
+  -
+    input:
+      bytes: [ 0xda, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d15, #0x2"
+  -
+    input:
+      bytes: [ 0x02, 0x24 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d4, d2"
+  -
+    input:
+      bytes: [ 0x3c, 0x1b ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x36"
+  -
+    input:
+      bytes: [ 0xa0, 0x56 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.a a6, #0x5"
+  -
+    input:
+      bytes: [ 0xfe, 0xdb ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, d13, #0x36"
+  -
+    input:
+      bytes: [ 0x26, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d1, d15"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xdc, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x11b8"
+  -
+    input:
+      bytes: [ 0x82, 0x27 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d7, #0x2"
+  -
+    input:
+      bytes: [ 0x4b, 0xf0, 0x51, 0x20 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "div.f d2, d0, d15"
+  -
+    input:
+      bytes: [ 0x3c, 0x27 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x4e"
+  -
+    input:
+      bytes: [ 0xc6, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor d1, d15"
+  -
+    input:
+      bytes: [ 0x15, 0xd0, 0xc0, 0xf7 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "stucx #0xd0003fc0"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xa4, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x548"
+  -
+    input:
+      bytes: [ 0x37, 0x00, 0x68, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d0, d0, #0, #0x8"
+  -
+    input:
+      bytes: [ 0x3c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x0"
+  -
+    input:
+      bytes: [ 0x53, 0x42, 0x20, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul d1, d2, #0x4"
+  -
+    input:
+      bytes: [ 0x26, 0x2f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d15, d2"
+  -
+    input:
+      bytes: [ 0x15, 0xd0, 0xc0, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lducx #0xd0003fc0"
+  -
+    input:
+      bytes: [ 0x4b, 0xf1, 0x11, 0x22 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "div.u e2, d1, d15"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x9d, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0xc6"
+  -
+    input:
+      bytes: [ 0x1d, 0x00, 0x03, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x6"
+  -
+    input:
+      bytes: [ 0xac, 0xa2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [sp]#0x4, d15"
+  -
+    input:
+      bytes: [ 0xc6, 0x1f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor d15, d1"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x53, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0xa6"
+  -
+    input:
+      bytes: [ 0xa0, 0x0f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.a a15, #0"
+  -
+    input:
+      bytes: [ 0x2e, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.t d15, #0, #0x6"
+  -
+    input:
+      bytes: [ 0x5f, 0x9f, 0x23, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d9, #0x46"
+  -
+    input:
+      bytes: [ 0x3f, 0xfc, 0xc9, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt.u d12, d15, #-0x6e"
+  -
+    input:
+      bytes: [ 0x02, 0x48 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d8, d4"
+  -
+    input:
+      bytes: [ 0x80, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.d d15, a15"
+  -
+    input:
+      bytes: [ 0x30, 0x43 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add.a a3, a4"
+  -
+    input:
+      bytes: [ 0xdf, 0x7f, 0xf6, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, #0x7, #-0x14"
+  -
+    input:
+      bytes: [ 0x4b, 0xf2, 0x51, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "div.f d15, d2, d15"
+  -
+    input:
+      bytes: [ 0x26, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d2, d0"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x4a, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x894"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x28, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x1b0"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xc6, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x218c"
+  -
+    input:
+      bytes: [ 0x06, 0x62 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh d2, #0x6"
+  -
+    input:
+      bytes: [ 0x37, 0x0f, 0xe1, 0xb1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d11, d15, #0x3, #0x1"
+  -
+    input:
+      bytes: [ 0x3c, 0x63 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0xc6"
+  -
+    input:
+      bytes: [ 0xa6, 0x4f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or d15, d4"
+  -
+    input:
+      bytes: [ 0xd7, 0x10, 0x21, 0x0f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "imask e0, #0x1, d15, #0x1"
+  -
+    input:
+      bytes: [ 0x3f, 0x40, 0xe3, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt.u d0, d4, #-0x3a"
+  -
+    input:
+      bytes: [ 0xa6, 0x12 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or d2, d1"
+  -
+    input:
+      bytes: [ 0x06, 0xef ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh d15, #-0x2"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xa5, 0x0b ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x174a"
+  -
+    input:
+      bytes: [ 0xbf, 0x81, 0xf3, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt.u d1, #0x8, #-0x1a"
+  -
+    input:
+      bytes: [ 0x3e, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d0, #0x10"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0x00, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0x5000"
+  -
+    input:
+      bytes: [ 0x37, 0x0f, 0x70, 0x20 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d2, d15, #0, #0x10"
+  -
+    input:
+      bytes: [ 0xd9, 0x44, 0x94, 0xd2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a4, [a4]#0x2b54"
+  -
+    input:
+      bytes: [ 0xb7, 0x0f, 0x02, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, #0, #0, #0x2"
+  -
+    input:
+      bytes: [ 0x53, 0x8f, 0x20, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul d15, d15, #0x8"
+  -
+    input:
+      bytes: [ 0x76, 0x23 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d2, #0x6"
+  -
+    input:
+      bytes: [ 0xc6, 0x3f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor d15, d3"
+  -
+    input:
+      bytes: [ 0x5f, 0x8f, 0x28, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d8, #0x50"
+  -
+    input:
+      bytes: [ 0x8f, 0x31, 0x40, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or d15, d1, #0x3"
+  -
+    input:
+      bytes: [ 0x37, 0xf1, 0x82, 0x16 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d1, d1, d15, #0xd, #0x2"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x1e, 0xfa ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0xbc4"
+  -
+    input:
+      bytes: [ 0x0f, 0x31, 0x10, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha d1, d1, d3"
+  -
+    input:
+      bytes: [ 0xf6, 0x26 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz d2, #0xc"
+  -
+    input:
+      bytes: [ 0x6f, 0x70, 0xec, 0x7f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.t d0, #0x7, #-0x28"
+  -
+    input:
+      bytes: [ 0x5e, 0x19 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, #0x1, #0x12"
+  -
+    input:
+      bytes: [ 0x91, 0x20, 0x00, 0xf5 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a15, #0x5002"
+  -
+    input:
+      bytes: [ 0x37, 0x0f, 0x61, 0xf2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d15, d15, #0x4, #0x1"
+  -
+    input:
+      bytes: [ 0x01, 0xdd, 0x00, 0xd6 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addsc.a a13, a13, d13, #0"
+  -
+    input:
+      bytes: [ 0x53, 0x42, 0x20, 0x30 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul d3, d2, #0x4"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0xd8, 0xc0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0xf18"
+  -
+    input:
+      bytes: [ 0xf6, 0x23 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz d2, #0x6"
+  -
+    input:
+      bytes: [ 0x53, 0x47, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul d0, d7, #0x4"
+  -
+    input:
+      bytes: [ 0x82, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d8, #0"
+  -
+    input:
+      bytes: [ 0x37, 0x0f, 0x01, 0xf2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, d0, #0x4, #0x1"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x87, 0xfa ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0xaf2"
+  -
+    input:
+      bytes: [ 0x8b, 0x09, 0x01, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d15, d9, #0x10"
+  -
+    input:
+      bytes: [ 0xbf, 0x89, 0xea, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt.u d9, #0x8, #-0x2c"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x87, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x50e"
+  -
+    input:
+      bytes: [ 0xb0, 0x14 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add.a a4, #0x1"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x91, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x122"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0x00, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0x4000"
+  -
+    input:
+      bytes: [ 0xdf, 0x0c, 0xd3, 0x7f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d12, #0, #-0x5a"
+  -
+    input:
+      bytes: [ 0x60, 0x4f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.a a15, d4"
+  -
+    input:
+      bytes: [ 0x82, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d0, #0"
+  -
+    input:
+      bytes: [ 0x37, 0x0f, 0x02, 0xf3 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, d0, #0x6, #0x2"
+  -
+    input:
+      bytes: [ 0x37, 0x4f, 0x9f, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, d4, #0x1, #0x1f"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xc3, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x7a"
+  -
+    input:
+      bytes: [ 0xbe, 0x0f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d0, #0x3e"
+  -
+    input:
+      bytes: [ 0x53, 0x41, 0x20, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul d15, d1, #0x4"
+  -
+    input:
+      bytes: [ 0xb7, 0x2f, 0x02, 0xf5 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, #0x2, #0xa, #0x2"
+  -
+    input:
+      bytes: [ 0xfc, 0x6e ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "loop a6, #-0x4"
+  -
+    input:
+      bytes: [ 0x37, 0x00, 0x6e, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d0, d0, #0x2, #0xe"
+  -
+    input:
+      bytes: [ 0x3c, 0x0c ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x18"
+  -
+    input:
+      bytes: [ 0x37, 0xf3, 0x08, 0x38 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d3, d3, d15, #0x10, #0x8"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xbc, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x1378"
+  -
+    input:
+      bytes: [ 0x8b, 0x09, 0x01, 0x40 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d4, d9, #0x10"
+  -
+    input:
+      bytes: [ 0x53, 0x47, 0x20, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul d1, d7, #0x4"
+  -
+    input:
+      bytes: [ 0x86, 0x23 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha d3, #0x2"
+  -
+    input:
+      bytes: [ 0x10, 0xe5 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addsc.a a5, a14, d15, #0"
+  -
+    input:
+      bytes: [ 0x02, 0x2f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d15, d2"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xb9, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x8e"
+  -
+    input:
+      bytes: [ 0x10, 0xcc ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addsc.a a12, a12, d15, #0"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0x14, 0x36 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0x60d4"
+  -
+    input:
+      bytes: [ 0xbf, 0x21, 0xcb, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt.u d1, #0x2, #-0x6a"
+  -
+    input:
+      bytes: [ 0x82, 0x32 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d2, #0x3"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x04, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x8"
+  -
+    input:
+      bytes: [ 0x6e, 0x20 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d15, #0x40"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x38, 0x0b ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x1670"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0x30, 0x21 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0x10b0"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x9a, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0xcc"
+  -
+    input:
+      bytes: [ 0x91, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a0, #0"
+  -
+    input:
+      bytes: [ 0xc6, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor d2, d0"
+  -
+    input:
+      bytes: [ 0x53, 0xcc, 0x20, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul d15, d12, #0xc"
+  -
+    input:
+      bytes: [ 0x02, 0xb4 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d4, d11"
+  -
+    input:
+      bytes: [ 0x3c, 0xed ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #-0x26"
+  -
+    input:
+      bytes: [ 0x02, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d1, d15"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xd6, 0xf8 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0xe54"
+  -
+    input:
+      bytes: [ 0x37, 0x0f, 0x82, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, d0, #0x3, #0x2"
+  -
+    input:
+      bytes: [ 0x6e, 0xc9 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d15, #-0x6e"
+  -
+    input:
+      bytes: [ 0x3b, 0x90, 0xd0, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d0, #0x3d09"
+  -
+    input:
+      bytes: [ 0x16, 0x0f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d15, #0xf"
+  -
+    input:
+      bytes: [ 0x02, 0x2a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d10, d2"
+  -
+    input:
+      bytes: [ 0xf6, 0x83 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz d8, #0x6"
+  -
+    input:
+      bytes: [ 0xc2, 0xf4 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d4, #-0x1"
+  -
+    input:
+      bytes: [ 0x37, 0x21, 0x81, 0x17 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d1, d1, d2, #0xf, #0x1"
+  -
+    input:
+      bytes: [ 0xa6, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or d0, d1"
+  -
+    input:
+      bytes: [ 0xfc, 0xf6 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "loop a15, #-0x14"
+  -
+    input:
+      bytes: [ 0xdf, 0x1f, 0x23, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, #0x1, #0x46"
+  -
+    input:
+      bytes: [ 0x82, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d1, #-0x1"
+  -
+    input:
+      bytes: [ 0x10, 0xe2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addsc.a a2, a14, d15, #0"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0x0c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0xc"
+  -
+    input:
+      bytes: [ 0x16, 0x7f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d15, #0x7f"
+  -
+    input:
+      bytes: [ 0xc2, 0xc5 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d5, #-0x4"
+  -
+    input:
+      bytes: [ 0x3c, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x6"
+  -
+    input:
+      bytes: [ 0x5e, 0x17 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, #0x1, #0xe"
+  -
+    input:
+      bytes: [ 0x0f, 0x10, 0x10, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha d0, d0, d1"
+  -
+    input:
+      bytes: [ 0x9b, 0xe2, 0xcb, 0x24 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addih d2, d2, #0x4cbe"
+  -
+    input:
+      bytes: [ 0xc2, 0x1c ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d12, #0x1"
+  -
+    input:
+      bytes: [ 0x80, 0xd0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.d d0, a13"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xe8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x1d0"
+  -
+    input:
+      bytes: [ 0xdf, 0x04, 0x31, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d4, #0, #0x62"
+  -
+    input:
+      bytes: [ 0x3c, 0xc4 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #-0x78"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0xc0, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#-0x6400"
+  -
+    input:
+      bytes: [ 0x16, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d15, #0x7"
+  -
+    input:
+      bytes: [ 0x89, 0xa2, 0x84, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [sp]#0x4, d2"
+  -
+    input:
+      bytes: [ 0x37, 0x0f, 0x62, 0xf2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d15, d15, #0x4, #0x2"
+  -
+    input:
+      bytes: [ 0xfc, 0x4e ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "loop a4, #-0x4"
+  -
+    input:
+      bytes: [ 0x86, 0x21 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha d1, #0x2"
+  -
+    input:
+      bytes: [ 0x7b, 0xa0, 0x47, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh d0, #0x447a"
+  -
+    input:
+      bytes: [ 0xd9, 0x44, 0x04, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a4, [a4]#0x4"
+  -
+    input:
+      bytes: [ 0x0f, 0xf0, 0x10, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha d0, d0, d15"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0x32, 0x31 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0x10f2"
+  -
+    input:
+      bytes: [ 0x82, 0x41 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d1, #0x4"
+  -
+    input:
+      bytes: [ 0xe2, 0x0f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul d15, d0"
+  -
+    input:
+      bytes: [ 0x01, 0xcd, 0x00, 0xc6 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addsc.a a12, a12, d13, #0"
+  -
+    input:
+      bytes: [ 0x37, 0x21, 0x81, 0x1b ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d1, d1, d2, #0x17, #0x1"
+  -
+    input:
+      bytes: [ 0x82, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d15, #-0x1"
+  -
+    input:
+      bytes: [ 0x10, 0x2f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addsc.a a15, a2, d15, #0"
+  -
+    input:
+      bytes: [ 0x3b, 0xd0, 0x7b, 0xf3 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d15, #0x37bd"
+  -
+    input:
+      bytes: [ 0xd9, 0x2d, 0x40, 0x20 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a13, [a2]#0x480"
+  -
+    input:
+      bytes: [ 0x3c, 0x14 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x28"
+  -
+    input:
+      bytes: [ 0x6f, 0x0f, 0xff, 0x7f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.t d15, #0, #-0x2"
+  -
+    input:
+      bytes: [ 0xd9, 0x11, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a1, [a1]#0"
+  -
+    input:
+      bytes: [ 0x3c, 0x0b ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x16"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0x00, 0x40 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0x100"
+  -
+    input:
+      bytes: [ 0x6f, 0x04, 0x05, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.t d4, #0, #0xa"
+  -
+    input:
+      bytes: [ 0x26, 0x1f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d15, d1"
+  -
+    input:
+      bytes: [ 0x10, 0xf4 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addsc.a a4, a15, d15, #0"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x1b, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x36"
+  -
+    input:
+      bytes: [ 0x82, 0x42 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d2, #0x4"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xc0, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x80"
+  -
+    input:
+      bytes: [ 0x8b, 0x09, 0x01, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d0, d9, #0x10"
+  -
+    input:
+      bytes: [ 0x3f, 0xf0, 0xfd, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt.u d0, d15, #-0x6"
+  -
+    input:
+      bytes: [ 0xb7, 0x2f, 0x08, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, #0x2, #0, #0x8"
+  -
+    input:
+      bytes: [ 0x3b, 0xf0, 0x01, 0x40 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d4, #0x1f"
+  -
+    input:
+      bytes: [ 0xe2, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul d0, d15"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x0d, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x1a"
+  -
+    input:
+      bytes: [ 0x09, 0xff, 0xc6, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.hu d15, [a15]#0x6"
+  -
+    input:
+      bytes: [ 0x40, 0xbf ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.aa a15, a11"
+  -
+    input:
+      bytes: [ 0x37, 0x03, 0x68, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d0, d3, #0x10, #0x8"
+  -
+    input:
+      bytes: [ 0x53, 0xcf, 0x20, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul d15, d15, #0xc"
+  -
+    input:
+      bytes: [ 0x7f, 0xf8, 0x0b, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jge.u d8, d15, #0x16"
+  -
+    input:
+      bytes: [ 0x60, 0x14 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.a a4, d1"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x2e, 0xfd ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x5a4"
+  -
+    input:
+      bytes: [ 0xa2, 0xfc ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub d12, d15"
+  -
+    input:
+      bytes: [ 0xb7, 0x00, 0x82, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d0, d0, #0, #0x5, #0x2"
+  -
+    input:
+      bytes: [ 0x3b, 0xf0, 0x00, 0x30 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d3, #0xf"
+  -
+    input:
+      bytes: [ 0x8f, 0x23, 0x20, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha d15, d3, #0x2"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x44, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x88"
+  -
+    input:
+      bytes: [ 0x82, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d6, #0"
+  -
+    input:
+      bytes: [ 0x60, 0x22 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.a a2, d2"
+  -
+    input:
+      bytes: [ 0x8f, 0x21, 0x20, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha d15, d1, #0x2"
+  -
+    input:
+      bytes: [ 0xd9, 0x22, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a2, [a2]#0"
+  -
+    input:
+      bytes: [ 0x20, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub.a sp, #0x8"
+  -
+    input:
+      bytes: [ 0x96, 0x20 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or d15, #0x20"
+  -
+    input:
+      bytes: [ 0x37, 0x0f, 0x03, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, d0, #0, #0x3"
+  -
+    input:
+      bytes: [ 0x91, 0x00, 0x00, 0xf6 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a15, #0x6000"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xc4, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x388"
+  -
+    input:
+      bytes: [ 0x6f, 0x0f, 0xfc, 0x7f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.t d15, #0, #-0x8"
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0x0b, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jge.u d15, #0x3, #0x16"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xfa, 0x11 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x23f4"
+  -
+    input:
+      bytes: [ 0x76, 0x6b ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d6, #0x16"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x34, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x68"
+  -
+    input:
+      bytes: [ 0x49, 0xa5, 0x00, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a5, [sp]#0"
+  -
+    input:
+      bytes: [ 0x91, 0x20, 0x00, 0x26 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a2, #0x6002"
+  -
+    input:
+      bytes: [ 0xff, 0x88, 0x1f, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jge.u d8, #0x8, #0x3e"
+  -
+    input:
+      bytes: [ 0x10, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addsc.a a15, a15, d15, #0"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xf2, 0xfd ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x41c"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0x30, 0x36 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0x60f0"
+  -
+    input:
+      bytes: [ 0x02, 0x29 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d9, d2"
+  -
+    input:
+      bytes: [ 0xdf, 0x08, 0x92, 0x81 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d8, #0, #0x324"
+  -
+    input:
+      bytes: [ 0xb7, 0x5f, 0x08, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, #0x5, #0, #0x8"
+  -
+    input:
+      bytes: [ 0x8f, 0x7f, 0x00, 0x31 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d3, d15, #0x7"
+  -
+    input:
+      bytes: [ 0x37, 0x0f, 0x02, 0xf2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, d0, #0x4, #0x2"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x8c, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x318"
+  -
+    input:
+      bytes: [ 0x9a, 0x81 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d15, d1, #-0x8"
+  -
+    input:
+      bytes: [ 0x7b, 0x00, 0x00, 0x0d ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh d0, #0xd000"
+  -
+    input:
+      bytes: [ 0x40, 0x4f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.aa a15, a4"
+  -
+    input:
+      bytes: [ 0xd9, 0x88, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a8, [a8]#0"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xf9, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0xff2"
+  -
+    input:
+      bytes: [ 0x91, 0x00, 0x00, 0x48 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a4, #0x8000"
+  -
+    input:
+      bytes: [ 0x89, 0xa2, 0x82, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [sp]#0x2, d2"
+  -
+    input:
+      bytes: [ 0x10, 0xcf ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addsc.a a15, a12, d15, #0"
+  -
+    input:
+      bytes: [ 0x82, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d7, #0"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xb2, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x9c"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x94, 0xfa ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0xad8"
+  -
+    input:
+      bytes: [ 0xb7, 0x0f, 0x81, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, #0, #0x3, #0x1"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x38, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x70"
+  -
+    input:
+      bytes: [ 0x02, 0x28 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d8, d2"
+  -
+    input:
+      bytes: [ 0xbb, 0x00, 0x68, 0xf9 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.u d15, #0x9680"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0x08, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0x8"
+  -
+    input:
+      bytes: [ 0x26, 0xf2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d2, d15"
+  -
+    input:
+      bytes: [ 0x09, 0xff, 0xc4, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.hu d15, [a15]#0x4"
+  -
+    input:
+      bytes: [ 0x91, 0x30, 0x88, 0x4f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a4, #0xf883"
+  -
+    input:
+      bytes: [ 0x37, 0xbf, 0x81, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, d11, #0x3, #0x1"
+  -
+    input:
+      bytes: [ 0x10, 0xf2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addsc.a a2, a15, d15, #0"
+  -
+    input:
+      bytes: [ 0xe2, 0x9f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul d15, d9"
+  -
+    input:
+      bytes: [ 0xa2, 0x0f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub d15, d0"
+  -
+    input:
+      bytes: [ 0xfc, 0x5e ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "loop a5, #-0x4"
+  -
+    input:
+      bytes: [ 0x3b, 0x00, 0xd0, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d0, #0x2d00"
+  -
+    input:
+      bytes: [ 0x02, 0x82 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d2, d8"
+  -
+    input:
+      bytes: [ 0x40, 0x5f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.aa a15, a5"
+  -
+    input:
+      bytes: [ 0x91, 0x00, 0x00, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a1, #0"
+  -
+    input:
+      bytes: [ 0x4b, 0xf2, 0x51, 0x20 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "div.f d2, d2, d15"
+  -
+    input:
+      bytes: [ 0x91, 0x00, 0x00, 0xf8 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a15, #0x8000"
+  -
+    input:
+      bytes: [ 0x37, 0xf0, 0x02, 0x0e ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d0, d0, d15, #0x1c, #0x2"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x85, 0xfa ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0xaf6"
+  -
+    input:
+      bytes: [ 0x02, 0x2b ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d11, d2"
+  -
+    input:
+      bytes: [ 0x0f, 0x0f, 0x10, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha d15, d15, d0"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x26, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x1b4"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0xac, 0x30 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0x8ec"
+  -
+    input:
+      bytes: [ 0x02, 0x5f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d15, d5"
+  -
+    input:
+      bytes: [ 0x6e, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d15, #0x12"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x21, 0xfd ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x5be"
+  -
+    input:
+      bytes: [ 0x91, 0x20, 0x00, 0xf7 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a15, #0x7002"
+  -
+    input:
+      bytes: [ 0x91, 0x20, 0x00, 0xa5 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a sp, #0x5002"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xa6, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0xb4"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0x00, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0x6000"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xbd, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x86"
+  -
+    input:
+      bytes: [ 0x82, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d10, #0"
+  -
+    input:
+      bytes: [ 0xa0, 0xc6 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.a a6, #0xc"
+  -
+    input:
+      bytes: [ 0xd9, 0x3f, 0x14, 0x36 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a3]#0x60d4"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xea, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x3d4"
+  -
+    input:
+      bytes: [ 0x9a, 0xd4 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d15, d4, #-0x3"
+  -
+    input:
+      bytes: [ 0x8f, 0xf0, 0x83, 0x41 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor d4, d0, #0x3f"
+  -
+    input:
+      bytes: [ 0xdf, 0x04, 0x7c, 0x7f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d4, #0, #-0x108"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x54, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x8a8"
+  -
+    input:
+      bytes: [ 0x02, 0x84 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d4, d8"
+  -
+    input:
+      bytes: [ 0xdf, 0x0c, 0xe0, 0x7f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d12, #0, #-0x40"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xc3, 0x0b ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x1786"
+  -
+    input:
+      bytes: [ 0x3c, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x8"
+  -
+    input:
+      bytes: [ 0x37, 0xf3, 0x08, 0x34 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d3, d3, d15, #0x8, #0x8"
+  -
+    input:
+      bytes: [ 0xda, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d15, #0x4"
+  -
+    input:
+      bytes: [ 0xbb, 0x70, 0x71, 0x4b ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.u d4, #0xb717"
+  -
+    input:
+      bytes: [ 0x96, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or d15, #0x80"
+  -
+    input:
+      bytes: [ 0x37, 0x0f, 0x68, 0x20 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d2, d15, #0, #0x8"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x73, 0xf5 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x151a"
+  -
+    input:
+      bytes: [ 0x96, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or d15, #0x4"
+  -
+    input:
+      bytes: [ 0x7e, 0x0d ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, d0, #0x1a"
+  -
+    input:
+      bytes: [ 0x7b, 0x00, 0x2f, 0xf4 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh d15, #0x42f0"
+  -
+    input:
+      bytes: [ 0x9b, 0x6f, 0x02, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addih d15, d15, #0x26"
+  -
+    input:
+      bytes: [ 0xda, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d15, #0x1"
+  -
+    input:
+      bytes: [ 0x9b, 0xe0, 0xcb, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addih d0, d0, #0x4cbe"
+  -
+    input:
+      bytes: [ 0x26, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d0, d1"
+  -
+    input:
+      bytes: [ 0x96, 0x40 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or d15, #0x40"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xbd, 0xfd ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x486"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x71, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x11e"
+  -
+    input:
+      bytes: [ 0x37, 0x0f, 0xe1, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d15, d15, #0x3, #0x1"
+  -
+    input:
+      bytes: [ 0x37, 0xf0, 0x04, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d0, d15, #0, #0x4"
+  -
+    input:
+      bytes: [ 0x6f, 0x1f, 0xf8, 0x7f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.t d15, #0x1, #-0x10"
+  -
+    input:
+      bytes: [ 0xb7, 0x1f, 0x08, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, #0x1, #0, #0x8"
+  -
+    input:
+      bytes: [ 0x37, 0xf0, 0x02, 0xf2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d0, d15, #0x4, #0x2"
+  -
+    input:
+      bytes: [ 0x91, 0x00, 0x00, 0x90 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a9, #0"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0x44, 0x60 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0x584"
+  -
+    input:
+      bytes: [ 0xb7, 0x1f, 0x02, 0xf2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, #0x1, #0x4, #0x2"
+  -
+    input:
+      bytes: [ 0x37, 0x0f, 0x05, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, d0, #0, #0x5"
+  -
+    input:
+      bytes: [ 0x37, 0x04, 0x68, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d15, d4, #0, #0x8"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xde, 0xfd ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x444"
+  -
+    input:
+      bytes: [ 0xdf, 0x1f, 0x57, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, #0x1, #0xae"
+  -
+    input:
+      bytes: [ 0xa2, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub d0, d15"
+  -
+    input:
+      bytes: [ 0x02, 0xc4 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d4, d12"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x2f, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x5e"
+  -
+    input:
+      bytes: [ 0xb7, 0x01, 0x02, 0x20 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d2, d1, #0, #0, #0x2"
+  -
+    input:
+      bytes: [ 0x4b, 0xaf, 0x41, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.f d15, d15, d10"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xfe, 0xfd ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x404"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xbb, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x376"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0x18, 0x46 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0x6118"
+  -
+    input:
+      bytes: [ 0x6e, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d15, #0xe"
+  -
+    input:
+      bytes: [ 0x53, 0x80, 0x20, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul d15, d0, #0x8"
+  -
+    input:
+      bytes: [ 0xd9, 0x44, 0x88, 0x72 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a4, [a4]#0x29c8"
+  -
+    input:
+      bytes: [ 0x3c, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x12"
+  -
+    input:
+      bytes: [ 0x37, 0x0c, 0x68, 0xc0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d12, d12, #0, #0x8"
+  -
+    input:
+      bytes: [ 0x37, 0xf0, 0x87, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d0, d15, #0x1, #0x7"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x71, 0x12 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x24e2"
+  -
+    input:
+      bytes: [ 0x37, 0x4f, 0x01, 0xf7 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, d4, #0xe, #0x1"
+  -
+    input:
+      bytes: [ 0x3c, 0x0d ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x1a"
+  -
+    input:
+      bytes: [ 0x37, 0x01, 0x81, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d0, d1, d0, #0x3, #0x1"
+  -
+    input:
+      bytes: [ 0xff, 0x8f, 0x1a, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jge.u d15, #0x8, #0x34"
+  -
+    input:
+      bytes: [ 0x80, 0xdf ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.d d15, a13"
+  -
+    input:
+      bytes: [ 0xc2, 0x1f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d15, #0x1"
+  -
+    input:
+      bytes: [ 0x4b, 0x8f, 0x41, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.f d15, d15, d8"
+  -
+    input:
+      bytes: [ 0xc2, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d1, #-0x1"
+  -
+    input:
+      bytes: [ 0x8b, 0xff, 0x21, 0xf3 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "min.u d15, d15, #0x1f"
+  -
+    input:
+      bytes: [ 0x40, 0xd2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.aa a2, a13"
+  -
+    input:
+      bytes: [ 0x9a, 0x22 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d15, d2, #0x2"
+  -
+    input:
+      bytes: [ 0x49, 0xa4, 0x00, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a4, [sp]#0"
+  -
+    input:
+      bytes: [ 0x3f, 0x08, 0x08, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt.u d8, d0, #0x10"
+  -
+    input:
+      bytes: [ 0x03, 0xf4, 0x0a, 0xf5 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd d15, d5, d4, d15"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0x80, 0xc9 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#-0x6500"
+  -
+    input:
+      bytes: [ 0x91, 0x00, 0x00, 0x26 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a2, #0x6000"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xf9, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x15f2"
+  -
+    input:
+      bytes: [ 0x0f, 0x80, 0x10, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha d0, d0, d8"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0x28, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0x1028"
+  -
+    input:
+      bytes: [ 0x91, 0x20, 0x00, 0xa6 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a sp, #0x6002"
+  -
+    input:
+      bytes: [ 0x02, 0x0c ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d12, d0"
+  -
+    input:
+      bytes: [ 0xd9, 0x55, 0x0c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a5, [a5]#0xc"
+  -
+    input:
+      bytes: [ 0xb7, 0x3f, 0x08, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, #0x3, #0, #0x8"
+  -
+    input:
+      bytes: [ 0x6f, 0x0f, 0xf2, 0x7f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.t d15, #0, #-0x1c"
+  -
+    input:
+      bytes: [ 0x4b, 0x0f, 0x71, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ftouz d15, d15"
+  -
+    input:
+      bytes: [ 0x53, 0x61, 0x20, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul d15, d1, #0x6"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x5c, 0xfd ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x548"
+  -
+    input:
+      bytes: [ 0x91, 0xf0, 0x01, 0xf8 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a15, #0x801f"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0xc0, 0x0b ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#-0x4400"
+  -
+    input:
+      bytes: [ 0xda, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d15, #0x8"
+  -
+    input:
+      bytes: [ 0x02, 0x94 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d4, d9"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x29, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x852"
+  -
+    input:
+      bytes: [ 0x37, 0xf1, 0x04, 0x18 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d1, d1, d15, #0x10, #0x4"
+  -
+    input:
+      bytes: [ 0x37, 0xf0, 0x01, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d0, d15, #0x2, #0x1"
+  -
+    input:
+      bytes: [ 0x7d, 0xf4, 0x04, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne.a a4, a15, #0x8"
+  -
+    input:
+      bytes: [ 0xd9, 0x22, 0x00, 0x16 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a2, [a2]#0x6040"
+  -
+    input:
+      bytes: [ 0x8f, 0x10, 0x00, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d0, d0, #0x1"
+  -
+    input:
+      bytes: [ 0x3e, 0x28 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d2, #0x10"
+  -
+    input:
+      bytes: [ 0xfe, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, d0, #0x28"
+  -
+    input:
+      bytes: [ 0x4b, 0x0f, 0x51, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "div.f d15, d15, d0"
+  -
+    input:
+      bytes: [ 0xdf, 0x0c, 0x86, 0x7f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d12, #0, #-0xf4"
+  -
+    input:
+      bytes: [ 0xc2, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d0, #0x1"
+  -
+    input:
+      bytes: [ 0x8f, 0x3c, 0x00, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d15, d12, #0x3"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x92, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x124"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xea, 0xfd ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x42c"
+  -
+    input:
+      bytes: [ 0x5f, 0x0f, 0x22, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d0, #0x44"
+  -
+    input:
+      bytes: [ 0x3c, 0x36 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x6c"
+  -
+    input:
+      bytes: [ 0x82, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d9, #0"
+  -
+    input:
+      bytes: [ 0x5e, 0x43 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, #0x4, #0x6"
diff --git a/tests/MC/TriCore/ADC_Queued_Scan_1_KIT_TC397_TFT.s.yaml b/tests/MC/TriCore/ADC_Queued_Scan_1_KIT_TC397_TFT.s.yaml
new file mode 100644
index 000000000..4c9319c6a
--- /dev/null
+++ b/tests/MC/TriCore/ADC_Queued_Scan_1_KIT_TC397_TFT.s.yaml
@@ -0,0 +1,8659 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xdf, 0x0f, 0x08, 0x82 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, #0, #0x410"
+  -
+    input:
+      bytes: [ 0x91, 0x10, 0x00, 0x25 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a2, #0x5001"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xef, 0xfb ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x822"
+  -
+    input:
+      bytes: [ 0x3f, 0xf1, 0xef, 0x7f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt d1, d15, #-0x22"
+  -
+    input:
+      bytes: [ 0x01, 0xd0, 0x00, 0x26 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addsc.a a2, a13, d0, #0"
+  -
+    input:
+      bytes: [ 0x8f, 0x24, 0x40, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or d15, d4, #0x2"
+  -
+    input:
+      bytes: [ 0xbe, 0x6a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d6, #0x34"
+  -
+    input:
+      bytes: [ 0x3c, 0x64 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0xc8"
+  -
+    input:
+      bytes: [ 0x4b, 0x0f, 0x41, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.f d15, d15, d0"
+  -
+    input:
+      bytes: [ 0x37, 0x0f, 0x04, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, d0, #0, #0x4"
+  -
+    input:
+      bytes: [ 0x10, 0xe5 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addsc.a a5, a14, d15, #0"
+  -
+    input:
+      bytes: [ 0x37, 0x00, 0x48, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr d15, d0, #0, #0x8"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0x28, 0xa6 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0x62a8"
+  -
+    input:
+      bytes: [ 0x3c, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x10"
+  -
+    input:
+      bytes: [ 0x37, 0x0f, 0x81, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, d0, #0x1f, #0x1"
+  -
+    input:
+      bytes: [ 0x37, 0x03, 0x68, 0xf4 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d15, d3, #0x8, #0x8"
+  -
+    input:
+      bytes: [ 0x37, 0xf3, 0x08, 0x34 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d3, d3, d15, #0x8, #0x8"
+  -
+    input:
+      bytes: [ 0x80, 0x4f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.d d15, a4"
+  -
+    input:
+      bytes: [ 0xd9, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a0, [a0]#0"
+  -
+    input:
+      bytes: [ 0x9a, 0xd4 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d15, d4, #-0x3"
+  -
+    input:
+      bytes: [ 0x9a, 0x20 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d15, d0, #0x2"
+  -
+    input:
+      bytes: [ 0xef, 0x8f, 0x0a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.t d15, #0x18, #0x14"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0xc0, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#-0x6400"
+  -
+    input:
+      bytes: [ 0xd9, 0x3f, 0x0c, 0x96 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a3]#0x624c"
+  -
+    input:
+      bytes: [ 0x37, 0xf0, 0x03, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d0, d0, d15, #0x8, #0x3"
+  -
+    input:
+      bytes: [ 0x3b, 0x00, 0x00, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d0, #0x1000"
+  -
+    input:
+      bytes: [ 0xee, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz d15, #0xa"
+  -
+    input:
+      bytes: [ 0x8f, 0xff, 0x83, 0x21 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor d2, d15, #0x3f"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x9c, 0xf8 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0xec8"
+  -
+    input:
+      bytes: [ 0x37, 0x0f, 0x01, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, d0, #0x2, #0x1"
+  -
+    input:
+      bytes: [ 0x3c, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x12"
+  -
+    input:
+      bytes: [ 0x4b, 0xf0, 0x11, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "div.u e0, d0, d15"
+  -
+    input:
+      bytes: [ 0x6f, 0x10, 0xf8, 0x7f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.t d0, #0x1, #-0x10"
+  -
+    input:
+      bytes: [ 0xdf, 0x1f, 0x23, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, #0x1, #0x46"
+  -
+    input:
+      bytes: [ 0x76, 0xc5 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d12, #0xa"
+  -
+    input:
+      bytes: [ 0x06, 0xef ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh d15, #-0x2"
+  -
+    input:
+      bytes: [ 0x8f, 0xff, 0x83, 0x81 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor d8, d15, #0x3f"
+  -
+    input:
+      bytes: [ 0x40, 0x4c ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.aa a12, a4"
+  -
+    input:
+      bytes: [ 0x80, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.d d15, a15"
+  -
+    input:
+      bytes: [ 0x6f, 0x0f, 0xff, 0x7f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.t d15, #0, #-0x2"
+  -
+    input:
+      bytes: [ 0x3c, 0x0b ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x16"
+  -
+    input:
+      bytes: [ 0x8f, 0xff, 0x83, 0x31 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor d3, d15, #0x3f"
+  -
+    input:
+      bytes: [ 0x09, 0xff, 0xc4, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.hu d15, [a15]#0x4"
+  -
+    input:
+      bytes: [ 0x9b, 0x10, 0x13, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addih d0, d0, #0x131"
+  -
+    input:
+      bytes: [ 0x49, 0x40, 0x40, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldmst [a4]#0, e0"
+  -
+    input:
+      bytes: [ 0x8f, 0xff, 0x83, 0x91 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor d9, d15, #0x3f"
+  -
+    input:
+      bytes: [ 0x02, 0x24 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d4, d2"
+  -
+    input:
+      bytes: [ 0x37, 0x0f, 0x02, 0xfe ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, d0, #0x1c, #0x2"
+  -
+    input:
+      bytes: [ 0x8b, 0x09, 0x01, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d15, d9, #0x10"
+  -
+    input:
+      bytes: [ 0x60, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.a a15, d15"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xab, 0xfb ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x8aa"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0x68, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0x428"
+  -
+    input:
+      bytes: [ 0xc2, 0x19 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d9, #0x1"
+  -
+    input:
+      bytes: [ 0xa2, 0x1f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub d15, d1"
+  -
+    input:
+      bytes: [ 0x80, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.d d0, a15"
+  -
+    input:
+      bytes: [ 0xbe, 0x41 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d4, #0x22"
+  -
+    input:
+      bytes: [ 0x10, 0xe2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addsc.a a2, a14, d15, #0"
+  -
+    input:
+      bytes: [ 0x10, 0x2f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addsc.a a15, a2, d15, #0"
+  -
+    input:
+      bytes: [ 0x49, 0x55, 0x0c, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a5, [a5]#0xc"
+  -
+    input:
+      bytes: [ 0x06, 0x50 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh d0, #0x5"
+  -
+    input:
+      bytes: [ 0xf6, 0x24 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz d2, #0x8"
+  -
+    input:
+      bytes: [ 0xfc, 0xf6 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "loop a15, #-0x14"
+  -
+    input:
+      bytes: [ 0x37, 0x00, 0x62, 0xfe ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d15, d0, #0x1c, #0x2"
+  -
+    input:
+      bytes: [ 0x6d, 0xb8, 0xf4, 0x11 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x7023e8"
+  -
+    input:
+      bytes: [ 0x91, 0x00, 0x03, 0xfa ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a15, #0xa030"
+  -
+    input:
+      bytes: [ 0x3b, 0x20, 0xfe, 0x0f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d0, #-0x1e"
+  -
+    input:
+      bytes: [ 0x37, 0x00, 0x61, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d0, d0, #0x6, #0x1"
+  -
+    input:
+      bytes: [ 0xda, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d15, #0x8"
+  -
+    input:
+      bytes: [ 0x60, 0xf2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.a a2, d15"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x15, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x2a"
+  -
+    input:
+      bytes: [ 0x80, 0xf2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.d d2, a15"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x91, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x122"
+  -
+    input:
+      bytes: [ 0x3e, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d0, #0xc"
+  -
+    input:
+      bytes: [ 0x8f, 0xff, 0x83, 0x11 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor d1, d15, #0x3f"
+  -
+    input:
+      bytes: [ 0x91, 0x40, 0x00, 0xf7 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a15, #0x7004"
+  -
+    input:
+      bytes: [ 0x53, 0x40, 0x20, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul d15, d0, #0x4"
+  -
+    input:
+      bytes: [ 0xc6, 0x1f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor d15, d1"
+  -
+    input:
+      bytes: [ 0x3b, 0x90, 0xd0, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d0, #0x3d09"
+  -
+    input:
+      bytes: [ 0x3b, 0xf0, 0x05, 0x20 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d2, #0x5f"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x57, 0xfc ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x752"
+  -
+    input:
+      bytes: [ 0xdf, 0x1f, 0x7f, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, #0x1, #0xfe"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0x88, 0x72 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0x29c8"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xb8, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x90"
+  -
+    input:
+      bytes: [ 0xd9, 0x44, 0x0c, 0x96 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a4, [a4]#0x624c"
+  -
+    input:
+      bytes: [ 0x1e, 0x12 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, #0x1, #0x4"
+  -
+    input:
+      bytes: [ 0x82, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d1, #-0x1"
+  -
+    input:
+      bytes: [ 0x7f, 0x0f, 0x04, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jge.u d15, d0, #0x8"
+  -
+    input:
+      bytes: [ 0x8b, 0xff, 0x21, 0xf3 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "min.u d15, d15, #0x1f"
+  -
+    input:
+      bytes: [ 0x37, 0x01, 0x68, 0xfc ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d15, d1, #0x18, #0x8"
+  -
+    input:
+      bytes: [ 0x7b, 0x00, 0x00, 0x0d ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh d0, #0xd000"
+  -
+    input:
+      bytes: [ 0x4b, 0x0f, 0x41, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.f d0, d15, d0"
+  -
+    input:
+      bytes: [ 0xb0, 0x4c ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add.a a12, #0x4"
+  -
+    input:
+      bytes: [ 0xda, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d15, #0x1"
+  -
+    input:
+      bytes: [ 0x96, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or d15, #0x1"
+  -
+    input:
+      bytes: [ 0xdf, 0x00, 0x2e, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d0, #0, #0x5c"
+  -
+    input:
+      bytes: [ 0xde, 0x1c ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, #0x1, #0x38"
+  -
+    input:
+      bytes: [ 0x10, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addsc.a a15, a15, d15, #0"
+  -
+    input:
+      bytes: [ 0x82, 0x21 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d1, #0x2"
+  -
+    input:
+      bytes: [ 0x96, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or d15, #0x4"
+  -
+    input:
+      bytes: [ 0x53, 0x41, 0x20, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul d15, d1, #0x4"
+  -
+    input:
+      bytes: [ 0x53, 0x88, 0x20, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul d15, d8, #0x8"
+  -
+    input:
+      bytes: [ 0x37, 0x4f, 0x82, 0xf6 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, d4, #0xd, #0x2"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0x00, 0x40 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0x100"
+  -
+    input:
+      bytes: [ 0x37, 0xf0, 0x02, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d0, d0, d15, #0x4, #0x2"
+  -
+    input:
+      bytes: [ 0x37, 0x01, 0x81, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d0, d1, d0, #0x1, #0x1"
+  -
+    input:
+      bytes: [ 0x80, 0xdf ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.d d15, a13"
+  -
+    input:
+      bytes: [ 0x82, 0x19 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d9, #0x1"
+  -
+    input:
+      bytes: [ 0x02, 0x4f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d15, d4"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0xf4, 0x42 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0x2d34"
+  -
+    input:
+      bytes: [ 0x89, 0x40, 0xc1, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachei.wi [a4+]#0x1"
+  -
+    input:
+      bytes: [ 0x91, 0x10, 0x00, 0x23 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a2, #0x3001"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x8b, 0xfe ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x2ea"
+  -
+    input:
+      bytes: [ 0x3c, 0x1f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x3e"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xce, 0x0d ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x1b9c"
+  -
+    input:
+      bytes: [ 0xda, 0x7f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d15, #0x7f"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0x24, 0x50 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0x164"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0x7a, 0x50 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0x57a"
+  -
+    input:
+      bytes: [ 0xbf, 0x38, 0xef, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt.u d8, #0x3, #-0x22"
+  -
+    input:
+      bytes: [ 0x8b, 0x87, 0x01, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d1, d7, #0x18"
+  -
+    input:
+      bytes: [ 0x3b, 0x00, 0x00, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d0, #0x6000"
+  -
+    input:
+      bytes: [ 0x91, 0x10, 0x00, 0xa4 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a sp, #0x4001"
+  -
+    input:
+      bytes: [ 0x37, 0xf0, 0x02, 0x0e ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d0, d0, d15, #0x1c, #0x2"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0xc8, 0x22 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0x2c88"
+  -
+    input:
+      bytes: [ 0x6d, 0xb8, 0x80, 0x11 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x702300"
+  -
+    input:
+      bytes: [ 0x15, 0xd0, 0xc0, 0xeb ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldlcx #0xd0003f80"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0x41, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "itof d0, d0"
+  -
+    input:
+      bytes: [ 0xb4, 0xc2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [a12], d2"
+  -
+    input:
+      bytes: [ 0x40, 0xd5 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.aa a5, a13"
+  -
+    input:
+      bytes: [ 0x80, 0x50 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.d d0, a5"
+  -
+    input:
+      bytes: [ 0x8f, 0x34, 0x40, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or d15, d4, #0x3"
+  -
+    input:
+      bytes: [ 0x26, 0xf3 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d3, d15"
+  -
+    input:
+      bytes: [ 0xc6, 0xf3 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor d3, d15"
+  -
+    input:
+      bytes: [ 0x37, 0x0f, 0x6e, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d15, d15, #0x2, #0xe"
+  -
+    input:
+      bytes: [ 0x02, 0x48 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d8, d4"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0x6c, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0x46c"
+  -
+    input:
+      bytes: [ 0xb0, 0x14 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add.a a4, #0x1"
+  -
+    input:
+      bytes: [ 0x6f, 0x00, 0x1f, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz.t d0, #0, #0x3e"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0x0c, 0x40 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0x10c"
+  -
+    input:
+      bytes: [ 0x7b, 0x00, 0x00, 0x11 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh d1, #0x1000"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xe6, 0xfc ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x634"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x6e, 0xfe ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x324"
+  -
+    input:
+      bytes: [ 0x3b, 0xf0, 0x0f, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d0, #0xff"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x0c, 0xfb ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x9e8"
+  -
+    input:
+      bytes: [ 0x40, 0x5c ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.aa a12, a5"
+  -
+    input:
+      bytes: [ 0x37, 0x0f, 0x62, 0xf3 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d15, d15, #0x6, #0x2"
+  -
+    input:
+      bytes: [ 0xd9, 0x22, 0x04, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a2, [a2]#0x4"
+  -
+    input:
+      bytes: [ 0x40, 0xc5 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.aa a5, a12"
+  -
+    input:
+      bytes: [ 0x53, 0x41, 0x20, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul d1, d1, #0x4"
+  -
+    input:
+      bytes: [ 0x91, 0x00, 0x00, 0x28 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a2, #0x8000"
+  -
+    input:
+      bytes: [ 0x82, 0x17 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d7, #0x1"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0x18, 0x96 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0x6258"
+  -
+    input:
+      bytes: [ 0x20, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub.a sp, #0x8"
+  -
+    input:
+      bytes: [ 0x8f, 0x29, 0x20, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha d15, d9, #0x2"
+  -
+    input:
+      bytes: [ 0x10, 0x22 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addsc.a a2, a2, d15, #0"
+  -
+    input:
+      bytes: [ 0x60, 0xc2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.a a2, d12"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0x30, 0x96 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0x6270"
+  -
+    input:
+      bytes: [ 0x37, 0xf0, 0x02, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d0, d15, #0, #0x2"
+  -
+    input:
+      bytes: [ 0x6d, 0xa0, 0x80, 0x11 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x402300"
+  -
+    input:
+      bytes: [ 0x3b, 0x00, 0x00, 0xf3 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d15, #0x3000"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x26, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0xa4c"
+  -
+    input:
+      bytes: [ 0xb7, 0x0f, 0x01, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, #0, #0x2, #0x1"
+  -
+    input:
+      bytes: [ 0x8f, 0x24, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh d0, d4, #0x2"
+  -
+    input:
+      bytes: [ 0x8b, 0xff, 0x01, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "rsub d15, d15, #0x1f"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0x3c, 0x96 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0x627c"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x0e, 0xfb ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x9e4"
+  -
+    input:
+      bytes: [ 0x6e, 0x36 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d15, #0x6c"
+  -
+    input:
+      bytes: [ 0x9b, 0xe1, 0xcb, 0x14 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addih d1, d1, #0x4cbe"
+  -
+    input:
+      bytes: [ 0xdc, 0x0f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ji a15"
+  -
+    input:
+      bytes: [ 0x53, 0x4f, 0x20, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul d15, d15, #0x4"
+  -
+    input:
+      bytes: [ 0xbf, 0x38, 0xce, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt.u d8, #0x3, #-0x64"
+  -
+    input:
+      bytes: [ 0x49, 0xf4, 0x00, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a4, [a15]#0"
+  -
+    input:
+      bytes: [ 0x37, 0xf0, 0x03, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d0, d0, d15, #0, #0x3"
+  -
+    input:
+      bytes: [ 0x37, 0x0f, 0xe1, 0xf2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d15, d15, #0x5, #0x1"
+  -
+    input:
+      bytes: [ 0x37, 0xf0, 0x02, 0x0f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d0, d0, d15, #0x1e, #0x2"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x1e, 0xe9 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x2dc4"
+  -
+    input:
+      bytes: [ 0x8f, 0x3f, 0x00, 0xd1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d13, d15, #0x3"
+  -
+    input:
+      bytes: [ 0x91, 0x10, 0x00, 0xf5 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a15, #0x5001"
+  -
+    input:
+      bytes: [ 0x0f, 0x91, 0x10, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha d1, d1, d9"
+  -
+    input:
+      bytes: [ 0x49, 0xfc, 0x14, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a12, [a15]#0x14"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xf4, 0xfa ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0xa18"
+  -
+    input:
+      bytes: [ 0xd9, 0xaa, 0x40, 0x89 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea sp, [sp]#-0x6a00"
+  -
+    input:
+      bytes: [ 0x1d, 0x00, 0x03, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x6"
+  -
+    input:
+      bytes: [ 0x91, 0x10, 0x00, 0xa5 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a sp, #0x5001"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xc3, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0xd86"
+  -
+    input:
+      bytes: [ 0x0f, 0x0f, 0x10, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha d15, d15, d0"
+  -
+    input:
+      bytes: [ 0xd9, 0x99, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a9, [a9]#0"
+  -
+    input:
+      bytes: [ 0x06, 0x21 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh d1, #0x2"
+  -
+    input:
+      bytes: [ 0x4b, 0x04, 0x11, 0x22 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "div.u e2, d4, d0"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xd2, 0xe7 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x305c"
+  -
+    input:
+      bytes: [ 0x20, 0x58 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub.a sp, #0x58"
+  -
+    input:
+      bytes: [ 0x7f, 0xf9, 0x04, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jge.u d9, d15, #0x8"
+  -
+    input:
+      bytes: [ 0xee, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz d15, #0xe"
+  -
+    input:
+      bytes: [ 0x49, 0xcf, 0x38, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a12]#0x38"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0x74, 0x30 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0x4f4"
+  -
+    input:
+      bytes: [ 0x4b, 0x10, 0x41, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.f d0, d0, d1"
+  -
+    input:
+      bytes: [ 0xbf, 0x81, 0x03, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt.u d1, #0x8, #0x6"
+  -
+    input:
+      bytes: [ 0x7f, 0xf9, 0x0b, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jge.u d9, d15, #0x16"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0x80, 0xc9 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#-0x6500"
+  -
+    input:
+      bytes: [ 0x6d, 0xd0, 0xf4, 0x11 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x5fdc18"
+  -
+    input:
+      bytes: [ 0xb7, 0x0f, 0x02, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, #0, #0, #0x2"
+  -
+    input:
+      bytes: [ 0xd9, 0x44, 0x08, 0x60 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a4, [a4]#0x188"
+  -
+    input:
+      bytes: [ 0x82, 0x26 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d6, #0x2"
+  -
+    input:
+      bytes: [ 0x37, 0x01, 0x70, 0x20 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d2, d1, #0, #0x10"
+  -
+    input:
+      bytes: [ 0xdc, 0x0b ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ji a11"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0xc0, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0x5c00"
+  -
+    input:
+      bytes: [ 0x8f, 0x00, 0x01, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh d0, d0, #0x10"
+  -
+    input:
+      bytes: [ 0x3c, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0xe"
+  -
+    input:
+      bytes: [ 0xc2, 0x18 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d8, #0x1"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xce, 0xfb ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x864"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x61, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x2c2"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xb7, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x16e"
+  -
+    input:
+      bytes: [ 0x8f, 0x3c, 0x00, 0x41 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d4, d12, #0x3"
+  -
+    input:
+      bytes: [ 0xc6, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor d0, d15"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x04, 0xfa ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0xbf8"
+  -
+    input:
+      bytes: [ 0xb7, 0x0f, 0x08, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, #0, #0, #0x8"
+  -
+    input:
+      bytes: [ 0x91, 0x40, 0x88, 0x4f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a4, #0xf884"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x1b, 0x0e ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x1c36"
+  -
+    input:
+      bytes: [ 0xb7, 0x0f, 0x01, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, #0, #0, #0x1"
+  -
+    input:
+      bytes: [ 0x7e, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, d0, #0x12"
+  -
+    input:
+      bytes: [ 0x8f, 0x24, 0x00, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh d15, d4, #0x2"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x8b, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0xea"
+  -
+    input:
+      bytes: [ 0x49, 0x33, 0x14, 0x8a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a3, [a3]#-0x1ec"
+  -
+    input:
+      bytes: [ 0xc6, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor d0, d1"
+  -
+    input:
+      bytes: [ 0x37, 0x10, 0x01, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d0, d0, d1, #0x2, #0x1"
+  -
+    input:
+      bytes: [ 0x4b, 0x0f, 0x51, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "div.f d15, d15, d0"
+  -
+    input:
+      bytes: [ 0x4b, 0x01, 0x51, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "div.f d0, d1, d0"
+  -
+    input:
+      bytes: [ 0x1e, 0x17 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, #0x1, #0xe"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x80, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x100"
+  -
+    input:
+      bytes: [ 0xbb, 0xf0, 0xff, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.u d15, #0xffff"
+  -
+    input:
+      bytes: [ 0x3e, 0x4a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d4, #0x14"
+  -
+    input:
+      bytes: [ 0x3b, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d0, #0x400"
+  -
+    input:
+      bytes: [ 0x37, 0xf0, 0x05, 0xf2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d0, d15, #0x4, #0x5"
+  -
+    input:
+      bytes: [ 0x91, 0x00, 0x03, 0xf8 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a15, #0x8030"
+  -
+    input:
+      bytes: [ 0x8f, 0x21, 0x20, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha d15, d1, #0x2"
+  -
+    input:
+      bytes: [ 0x7f, 0xf9, 0x0d, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jge.u d9, d15, #0x1a"
+  -
+    input:
+      bytes: [ 0x76, 0x91 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d9, #0x2"
+  -
+    input:
+      bytes: [ 0x02, 0x92 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d2, d9"
+  -
+    input:
+      bytes: [ 0x3f, 0x0f, 0xfd, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt.u d15, d0, #-0x6"
+  -
+    input:
+      bytes: [ 0x6d, 0xe8, 0x17, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x2fffd2"
+  -
+    input:
+      bytes: [ 0x82, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d8, #0"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x05, 0xfc ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x7f6"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0x08, 0x23 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0x3088"
+  -
+    input:
+      bytes: [ 0x37, 0x00, 0xe1, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d0, d0, #0x1, #0x1"
+  -
+    input:
+      bytes: [ 0x37, 0x0f, 0xe1, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d15, d15, #0x1, #0x1"
+  -
+    input:
+      bytes: [ 0x76, 0xcf ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d12, #0x1e"
+  -
+    input:
+      bytes: [ 0x82, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d1, #0"
+  -
+    input:
+      bytes: [ 0xa2, 0xdc ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub d12, d13"
+  -
+    input:
+      bytes: [ 0xd9, 0x44, 0x18, 0x60 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a4, [a4]#0x198"
+  -
+    input:
+      bytes: [ 0x9b, 0x81, 0xb9, 0x14 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addih d1, d1, #0x4b98"
+  -
+    input:
+      bytes: [ 0xb7, 0x0f, 0x01, 0xfc ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, #0, #0x18, #0x1"
+  -
+    input:
+      bytes: [ 0x37, 0x0f, 0x05, 0xf8 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, d0, #0x10, #0x5"
+  -
+    input:
+      bytes: [ 0x2d, 0x0f, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jli a15"
+  -
+    input:
+      bytes: [ 0x53, 0x44, 0x20, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul d15, d4, #0x4"
+  -
+    input:
+      bytes: [ 0x91, 0x40, 0x00, 0xa6 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a sp, #0x6004"
+  -
+    input:
+      bytes: [ 0x3e, 0x4e ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d4, #0x1c"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0x00, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0x6000"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x53, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0xa6"
+  -
+    input:
+      bytes: [ 0xb7, 0x0f, 0x0c, 0xfa ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, #0, #0x14, #0xc"
+  -
+    input:
+      bytes: [ 0xa0, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.a a4, #0"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xed, 0xf7 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x1026"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0x0c, 0x96 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0x624c"
+  -
+    input:
+      bytes: [ 0x3c, 0x21 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x42"
+  -
+    input:
+      bytes: [ 0x37, 0xf0, 0x02, 0xf2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d0, d15, #0x4, #0x2"
+  -
+    input:
+      bytes: [ 0xdf, 0x0c, 0xe0, 0x7f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d12, #0, #-0x40"
+  -
+    input:
+      bytes: [ 0xbb, 0xf0, 0xff, 0x2f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.u d2, #0xffff"
+  -
+    input:
+      bytes: [ 0x49, 0x42, 0x00, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a2, [a4]#0"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0x70, 0x20 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0x4b0"
+  -
+    input:
+      bytes: [ 0x8f, 0xec, 0x1f, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh d15, d12, #-0x2"
+  -
+    input:
+      bytes: [ 0xd9, 0x44, 0x28, 0xa6 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a4, [a4]#0x62a8"
+  -
+    input:
+      bytes: [ 0x7f, 0xf9, 0x03, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jge.u d9, d15, #0x6"
+  -
+    input:
+      bytes: [ 0x91, 0x20, 0x88, 0x4f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a4, #0xf882"
+  -
+    input:
+      bytes: [ 0xbb, 0x00, 0xc2, 0x2b ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.u d2, #0xbc20"
+  -
+    input:
+      bytes: [ 0xa0, 0x15 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.a a5, #0x1"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xfc, 0xfe ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x208"
+  -
+    input:
+      bytes: [ 0x6d, 0xe8, 0x90, 0x0f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x2fe0e0"
+  -
+    input:
+      bytes: [ 0x6f, 0x1f, 0xfa, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz.t d15, #0x1, #-0xc"
+  -
+    input:
+      bytes: [ 0x49, 0x33, 0x08, 0x8a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a3, [a3]#-0x1f8"
+  -
+    input:
+      bytes: [ 0xda, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d15, #0x10"
+  -
+    input:
+      bytes: [ 0x6f, 0x20, 0xf2, 0x7f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.t d0, #0x2, #-0x1c"
+  -
+    input:
+      bytes: [ 0xd9, 0x2e, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a14, [a2]#0x400"
+  -
+    input:
+      bytes: [ 0x26, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d0, d15"
+  -
+    input:
+      bytes: [ 0xb7, 0x01, 0x02, 0x20 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d2, d1, #0, #0, #0x2"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x99, 0xfb ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x8ce"
+  -
+    input:
+      bytes: [ 0x3e, 0x12 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d1, #0x4"
+  -
+    input:
+      bytes: [ 0x26, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d2, d0"
+  -
+    input:
+      bytes: [ 0xdf, 0x1f, 0x70, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, #0x1, #0xe0"
+  -
+    input:
+      bytes: [ 0x06, 0x1f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh d15, #0x1"
+  -
+    input:
+      bytes: [ 0x3e, 0x56 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d5, #0xc"
+  -
+    input:
+      bytes: [ 0xda, 0x1f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d15, #0x1f"
+  -
+    input:
+      bytes: [ 0xc2, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d1, #-0x1"
+  -
+    input:
+      bytes: [ 0x49, 0xff, 0x00, 0x1a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0x40"
+  -
+    input:
+      bytes: [ 0x4b, 0xf1, 0x41, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.f d1, d1, d15"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x67, 0xfc ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x732"
+  -
+    input:
+      bytes: [ 0x8f, 0x31, 0x40, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or d15, d1, #0x3"
+  -
+    input:
+      bytes: [ 0x96, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or d15, #0x3"
+  -
+    input:
+      bytes: [ 0x37, 0x0f, 0x04, 0xf2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, d0, #0x4, #0x4"
+  -
+    input:
+      bytes: [ 0x4b, 0x0f, 0x71, 0x41 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ftouz d4, d15"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x01, 0xfb ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x9fe"
+  -
+    input:
+      bytes: [ 0xc2, 0x12 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d2, #0x1"
+  -
+    input:
+      bytes: [ 0x37, 0x01, 0x10, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d1, d1, d0, #0, #0x10"
+  -
+    input:
+      bytes: [ 0x53, 0x4a, 0x20, 0x20 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul d2, d10, #0x4"
+  -
+    input:
+      bytes: [ 0xe2, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul d0, d1"
+  -
+    input:
+      bytes: [ 0x7f, 0x20, 0x04, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jge.u d0, d2, #0x8"
+  -
+    input:
+      bytes: [ 0x80, 0xd0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.d d0, a13"
+  -
+    input:
+      bytes: [ 0x37, 0x09, 0x68, 0x90 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d9, d9, #0, #0x8"
+  -
+    input:
+      bytes: [ 0x02, 0xf4 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d4, d15"
+  -
+    input:
+      bytes: [ 0x6f, 0x20, 0xf8, 0x7f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.t d0, #0x2, #-0x10"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x8a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x114"
+  -
+    input:
+      bytes: [ 0x3c, 0x17 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x2e"
+  -
+    input:
+      bytes: [ 0x3f, 0xf0, 0x05, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt.u d0, d15, #0xa"
+  -
+    input:
+      bytes: [ 0x3b, 0x00, 0x10, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d15, #0x100"
+  -
+    input:
+      bytes: [ 0xda, 0x0c ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d15, #0xc"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x4b, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x96"
+  -
+    input:
+      bytes: [ 0x8b, 0xf0, 0x2f, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "min.u d0, d0, #0xff"
+  -
+    input:
+      bytes: [ 0xbb, 0x00, 0x68, 0xf9 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.u d15, #0x9680"
+  -
+    input:
+      bytes: [ 0x3b, 0xb0, 0x7f, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d0, #0x7fb"
+  -
+    input:
+      bytes: [ 0xfe, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, d0, #0x28"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x45, 0xfc ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x776"
+  -
+    input:
+      bytes: [ 0xbb, 0xd0, 0xcc, 0x0c ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.u d0, #0xcccd"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x5d, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0xba"
+  -
+    input:
+      bytes: [ 0x82, 0x12 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d2, #0x1"
+  -
+    input:
+      bytes: [ 0x37, 0x0f, 0x01, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, d0, #0x1e, #0x1"
+  -
+    input:
+      bytes: [ 0xbf, 0x30, 0xe1, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt.u d0, #0x3, #-0x3e"
+  -
+    input:
+      bytes: [ 0x4b, 0xbf, 0x41, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.f d15, d15, d11"
+  -
+    input:
+      bytes: [ 0xbf, 0x20, 0xef, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt.u d0, #0x2, #-0x22"
+  -
+    input:
+      bytes: [ 0x3c, 0x1a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x34"
+  -
+    input:
+      bytes: [ 0x53, 0x69, 0x20, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul d15, d9, #0x6"
+  -
+    input:
+      bytes: [ 0x01, 0xcd, 0x00, 0xc6 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addsc.a a12, a12, d13, #0"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x1a, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x1234"
+  -
+    input:
+      bytes: [ 0x09, 0xc0, 0xca, 0x28 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.hu d0, [a12]#0x8a"
+  -
+    input:
+      bytes: [ 0x7f, 0xf9, 0x0f, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jge.u d9, d15, #0x1e"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x62, 0xfb ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x93c"
+  -
+    input:
+      bytes: [ 0xb7, 0x1f, 0x81, 0x1b ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d1, d15, #0x1, #0x17, #0x1"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0"
+  -
+    input:
+      bytes: [ 0xbf, 0xc9, 0x06, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt.u d9, #0xc, #0xc"
+  -
+    input:
+      bytes: [ 0xda, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d15, #0x2"
+  -
+    input:
+      bytes: [ 0x40, 0x5f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.aa a15, a5"
+  -
+    input:
+      bytes: [ 0x91, 0x20, 0x00, 0x5f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a5, #0xf002"
+  -
+    input:
+      bytes: [ 0x37, 0x0f, 0x61, 0xf2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d15, d15, #0x4, #0x1"
+  -
+    input:
+      bytes: [ 0x91, 0x00, 0x0c, 0xfa ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a15, #0xa0c0"
+  -
+    input:
+      bytes: [ 0x53, 0xc8, 0x21, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul d15, d8, #0x1c"
+  -
+    input:
+      bytes: [ 0x37, 0x0f, 0xe1, 0xf3 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d15, d15, #0x7, #0x1"
+  -
+    input:
+      bytes: [ 0xda, 0x0f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d15, #0xf"
+  -
+    input:
+      bytes: [ 0x6e, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d15, #0x8"
+  -
+    input:
+      bytes: [ 0x0f, 0xf1, 0x00, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh d1, d1, d15"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x7b, 0xfc ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x70a"
+  -
+    input:
+      bytes: [ 0x9b, 0xb0, 0xbf, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addih d0, d0, #0x4bfb"
+  -
+    input:
+      bytes: [ 0x09, 0xff, 0xca, 0x28 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.hu d15, [a15]#0x8a"
+  -
+    input:
+      bytes: [ 0xfc, 0x5e ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "loop a5, #-0x4"
+  -
+    input:
+      bytes: [ 0xda, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d15, #0x3"
+  -
+    input:
+      bytes: [ 0x20, 0x28 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub.a sp, #0x28"
+  -
+    input:
+      bytes: [ 0x82, 0x16 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d6, #0x1"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0x20, 0xe0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0x3a0"
+  -
+    input:
+      bytes: [ 0xee, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz d15, #0x8"
+  -
+    input:
+      bytes: [ 0x4b, 0xf0, 0x11, 0x22 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "div.u e2, d0, d15"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xf9, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0xff2"
+  -
+    input:
+      bytes: [ 0x16, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d15, #0x3"
+  -
+    input:
+      bytes: [ 0x4b, 0xf2, 0x51, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "div.f d15, d2, d15"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xca, 0xfc ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x66c"
+  -
+    input:
+      bytes: [ 0x82, 0x30 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d0, #0x3"
+  -
+    input:
+      bytes: [ 0x82, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d15, #-0x1"
+  -
+    input:
+      bytes: [ 0x8f, 0x3c, 0x00, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d0, d12, #0x3"
+  -
+    input:
+      bytes: [ 0x3e, 0x1b ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d1, #0x16"
+  -
+    input:
+      bytes: [ 0x32, 0x5f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "rsub d15"
+  -
+    input:
+      bytes: [ 0x82, 0xf2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d2, #-0x1"
+  -
+    input:
+      bytes: [ 0x40, 0xd2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.aa a2, a13"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0x80, 0xc5 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0x5b00"
+  -
+    input:
+      bytes: [ 0x91, 0x00, 0x00, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a1, #0"
+  -
+    input:
+      bytes: [ 0x3e, 0x47 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d4, #0xe"
+  -
+    input:
+      bytes: [ 0xdf, 0x10, 0x2b, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d0, #0x1, #0x56"
+  -
+    input:
+      bytes: [ 0xde, 0x28 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, #0x2, #0x30"
+  -
+    input:
+      bytes: [ 0x37, 0x0f, 0x68, 0x40 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d4, d15, #0, #0x8"
+  -
+    input:
+      bytes: [ 0x8f, 0xff, 0x83, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor d15, d15, #0x3f"
+  -
+    input:
+      bytes: [ 0x06, 0x3f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh d15, #0x3"
+  -
+    input:
+      bytes: [ 0x82, 0x14 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d4, #0x1"
+  -
+    input:
+      bytes: [ 0x3b, 0x90, 0xd0, 0x33 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d3, #0x3d09"
+  -
+    input:
+      bytes: [ 0x02, 0x94 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d4, d9"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x9b, 0xfc ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x6ca"
+  -
+    input:
+      bytes: [ 0x53, 0xc2, 0x20, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul d15, d2, #0xc"
+  -
+    input:
+      bytes: [ 0x7b, 0xc0, 0xff, 0x0f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh d0, #0xfffc"
+  -
+    input:
+      bytes: [ 0x6f, 0x1f, 0x12, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.t d15, #0x1, #0x24"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0x3c, 0x50 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0x17c"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0x78, 0x40 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0x538"
+  -
+    input:
+      bytes: [ 0x40, 0xf4 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.aa a4, a15"
+  -
+    input:
+      bytes: [ 0x4e, 0x33 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jgtz d3, #0x6"
+  -
+    input:
+      bytes: [ 0xdf, 0x1f, 0x29, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, #0x1, #0x52"
+  -
+    input:
+      bytes: [ 0xb7, 0x0f, 0x81, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, #0, #0x3, #0x1"
+  -
+    input:
+      bytes: [ 0x3e, 0x46 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d4, #0xc"
+  -
+    input:
+      bytes: [ 0x37, 0x01, 0x81, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d0, d1, d0, #0x3, #0x1"
+  -
+    input:
+      bytes: [ 0xc2, 0xf4 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d4, #-0x1"
+  -
+    input:
+      bytes: [ 0x91, 0x30, 0x00, 0x2f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a2, #0xf003"
+  -
+    input:
+      bytes: [ 0x3f, 0x02, 0x08, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt.u d2, d0, #0x10"
+  -
+    input:
+      bytes: [ 0x53, 0x80, 0x20, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul d15, d0, #0x8"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x53, 0xfc ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x75a"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0xc4, 0xc2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0x2f04"
+  -
+    input:
+      bytes: [ 0x96, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or d15, #0x8"
+  -
+    input:
+      bytes: [ 0x37, 0x0f, 0x62, 0xf2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d15, d15, #0x4, #0x2"
+  -
+    input:
+      bytes: [ 0x10, 0xf4 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addsc.a a4, a15, d15, #0"
+  -
+    input:
+      bytes: [ 0x4b, 0xf2, 0x51, 0x20 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "div.f d2, d2, d15"
+  -
+    input:
+      bytes: [ 0xda, 0x96 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d15, #0x96"
+  -
+    input:
+      bytes: [ 0x5e, 0x23 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, #0x2, #0x6"
+  -
+    input:
+      bytes: [ 0x82, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d4, #0"
+  -
+    input:
+      bytes: [ 0x16, 0x0f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d15, #0xf"
+  -
+    input:
+      bytes: [ 0xd9, 0x22, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a2, [a2]#0"
+  -
+    input:
+      bytes: [ 0x3e, 0x66 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d6, #0xc"
+  -
+    input:
+      bytes: [ 0x9b, 0xe2, 0xcb, 0x24 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addih d2, d2, #0x4cbe"
+  -
+    input:
+      bytes: [ 0x4e, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jgtz d0, #0x6"
+  -
+    input:
+      bytes: [ 0x1d, 0xff, 0x77, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #-0x112"
+  -
+    input:
+      bytes: [ 0xbf, 0x21, 0xcd, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt.u d1, #0x2, #-0x66"
+  -
+    input:
+      bytes: [ 0x3b, 0xf0, 0x00, 0x30 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d3, #0xf"
+  -
+    input:
+      bytes: [ 0x16, 0x5f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d15, #0x5f"
+  -
+    input:
+      bytes: [ 0x09, 0xff, 0xc6, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.hu d15, [a15]#0x6"
+  -
+    input:
+      bytes: [ 0x8b, 0xf2, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d0, d2, #0xf"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xdf, 0xfa ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0xa42"
+  -
+    input:
+      bytes: [ 0xf6, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz d0, #0xc"
+  -
+    input:
+      bytes: [ 0x02, 0x0c ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d12, d0"
+  -
+    input:
+      bytes: [ 0x91, 0x80, 0x88, 0x4f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a4, #0xf888"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0x24, 0x96 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0x6264"
+  -
+    input:
+      bytes: [ 0x37, 0x0f, 0x82, 0xf6 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, d0, #0xd, #0x2"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xae, 0xf8 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0xea4"
+  -
+    input:
+      bytes: [ 0x4b, 0xf0, 0x41, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.f d15, d0, d15"
+  -
+    input:
+      bytes: [ 0x82, 0x24 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d4, #0x2"
+  -
+    input:
+      bytes: [ 0x06, 0x24 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh d4, #0x2"
+  -
+    input:
+      bytes: [ 0xff, 0x8f, 0x1a, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jge.u d15, #0x8, #0x34"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x01, 0xfc ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x7fe"
+  -
+    input:
+      bytes: [ 0x8f, 0x3c, 0x00, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d15, d12, #0x3"
+  -
+    input:
+      bytes: [ 0x82, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d6, #0"
+  -
+    input:
+      bytes: [ 0x02, 0x90 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d0, d9"
+  -
+    input:
+      bytes: [ 0x4b, 0x0f, 0x71, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ftouz d0, d15"
+  -
+    input:
+      bytes: [ 0x37, 0x0f, 0x62, 0xf6 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d15, d15, #0xc, #0x2"
+  -
+    input:
+      bytes: [ 0x49, 0xcf, 0x28, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a12]#0x28"
+  -
+    input:
+      bytes: [ 0x01, 0x28, 0x00, 0x26 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addsc.a a2, a2, d8, #0"
+  -
+    input:
+      bytes: [ 0x06, 0xaf ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh d15, #-0x6"
+  -
+    input:
+      bytes: [ 0x86, 0x24 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha d4, #0x2"
+  -
+    input:
+      bytes: [ 0xb7, 0x3f, 0x08, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, #0x3, #0, #0x8"
+  -
+    input:
+      bytes: [ 0x9b, 0xb1, 0xa5, 0x14 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addih d1, d1, #0x4a5b"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x75, 0xfc ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x716"
+  -
+    input:
+      bytes: [ 0x3c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x0"
+  -
+    input:
+      bytes: [ 0x86, 0x21 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha d1, #0x2"
+  -
+    input:
+      bytes: [ 0xbe, 0x60 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d6, #0x20"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xc5, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x76"
+  -
+    input:
+      bytes: [ 0xdf, 0x10, 0xee, 0x7f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d0, #0x1, #-0x24"
+  -
+    input:
+      bytes: [ 0xfc, 0x29 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "loop a2, #-0xe"
+  -
+    input:
+      bytes: [ 0xa6, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or d0, d15"
+  -
+    input:
+      bytes: [ 0x8f, 0x2a, 0x20, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha d15, d10, #0x2"
+  -
+    input:
+      bytes: [ 0xda, 0x20 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d15, #0x20"
+  -
+    input:
+      bytes: [ 0x26, 0x30 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d0, d3"
+  -
+    input:
+      bytes: [ 0xc6, 0x3f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor d15, d3"
+  -
+    input:
+      bytes: [ 0x37, 0xf3, 0x08, 0x38 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d3, d3, d15, #0x10, #0x8"
+  -
+    input:
+      bytes: [ 0x4b, 0x08, 0x61, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "utof d0, d8"
+  -
+    input:
+      bytes: [ 0x37, 0x0f, 0xe2, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d15, d15, #0x1, #0x2"
+  -
+    input:
+      bytes: [ 0x0f, 0xf3, 0x00, 0x30 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh d3, d3, d15"
+  -
+    input:
+      bytes: [ 0x53, 0xcf, 0x20, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul d1, d15, #0xc"
+  -
+    input:
+      bytes: [ 0x7b, 0xa0, 0x47, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh d0, #0x447a"
+  -
+    input:
+      bytes: [ 0x5f, 0x2f, 0xf4, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, d2, #-0x18"
+  -
+    input:
+      bytes: [ 0x4b, 0xf0, 0x11, 0x42 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "div.u e4, d0, d15"
+  -
+    input:
+      bytes: [ 0xb7, 0x2f, 0x02, 0xf5 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, #0x2, #0xa, #0x2"
+  -
+    input:
+      bytes: [ 0x6e, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d15, #0x6"
+  -
+    input:
+      bytes: [ 0x5f, 0x6f, 0x23, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d6, #0x46"
+  -
+    input:
+      bytes: [ 0x3f, 0x10, 0x97, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt.u d0, d1, #-0xd2"
+  -
+    input:
+      bytes: [ 0x37, 0x0f, 0xe7, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d15, d15, #0x1, #0x7"
+  -
+    input:
+      bytes: [ 0x37, 0xf0, 0x03, 0x0c ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d0, d0, d15, #0x18, #0x3"
+  -
+    input:
+      bytes: [ 0xa6, 0x5f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or d15, d5"
+  -
+    input:
+      bytes: [ 0x91, 0x10, 0x88, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a15, #0xf881"
+  -
+    input:
+      bytes: [ 0xda, 0x15 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d15, #0x15"
+  -
+    input:
+      bytes: [ 0x53, 0x20, 0x20, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul d15, d0, #0x2"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x43, 0xfd ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x57a"
+  -
+    input:
+      bytes: [ 0x3c, 0xd9 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #-0x4e"
+  -
+    input:
+      bytes: [ 0xb7, 0x5f, 0x08, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, #0x5, #0, #0x8"
+  -
+    input:
+      bytes: [ 0x8f, 0x28, 0x00, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh d15, d8, #0x2"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x4b, 0xfb ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x96a"
+  -
+    input:
+      bytes: [ 0xbb, 0x00, 0x68, 0x19 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.u d1, #0x9680"
+  -
+    input:
+      bytes: [ 0x91, 0x10, 0x00, 0x24 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a2, #0x4001"
+  -
+    input:
+      bytes: [ 0xfc, 0x2e ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "loop a2, #-0x4"
+  -
+    input:
+      bytes: [ 0xfc, 0x2f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "loop a2, #-0x2"
+  -
+    input:
+      bytes: [ 0xd9, 0xaa, 0x40, 0x85 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea sp, [sp]#0x5600"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x32, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x19c"
+  -
+    input:
+      bytes: [ 0x91, 0x10, 0x00, 0xa1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a sp, #0x1001"
+  -
+    input:
+      bytes: [ 0x02, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d1, d15"
+  -
+    input:
+      bytes: [ 0xe2, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul d0, d15"
+  -
+    input:
+      bytes: [ 0x82, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d5, #0"
+  -
+    input:
+      bytes: [ 0x7e, 0x0d ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, d0, #0x1a"
+  -
+    input:
+      bytes: [ 0x37, 0xf0, 0x01, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d0, d15, #0, #0x1"
+  -
+    input:
+      bytes: [ 0x37, 0x0f, 0x81, 0xfb ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, d0, #0x17, #0x1"
+  -
+    input:
+      bytes: [ 0xdf, 0x1f, 0xfb, 0x7f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, #0x1, #-0xa"
+  -
+    input:
+      bytes: [ 0x15, 0xd0, 0xc0, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lducx #0xd0003fc0"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xb8, 0xf2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x1a90"
+  -
+    input:
+      bytes: [ 0xdf, 0x1f, 0x54, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, #0x1, #0xa8"
+  -
+    input:
+      bytes: [ 0x7e, 0x93 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, d9, #0x6"
+  -
+    input:
+      bytes: [ 0x37, 0x0f, 0x65, 0xf2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d15, d15, #0x4, #0x5"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x68, 0xfb ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x930"
+  -
+    input:
+      bytes: [ 0x91, 0x50, 0x02, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a15, #0xf025"
+  -
+    input:
+      bytes: [ 0x3c, 0x16 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x2c"
+  -
+    input:
+      bytes: [ 0x6f, 0x10, 0xf2, 0x7f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.t d0, #0x1, #-0x1c"
+  -
+    input:
+      bytes: [ 0xdf, 0x10, 0xea, 0x7f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d0, #0x1, #-0x2c"
+  -
+    input:
+      bytes: [ 0xdf, 0x10, 0xf6, 0x7f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d0, #0x1, #-0x14"
+  -
+    input:
+      bytes: [ 0x91, 0x00, 0x00, 0x47 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a4, #0x7000"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x83, 0xfc ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x6fa"
+  -
+    input:
+      bytes: [ 0xdf, 0x0c, 0x86, 0x7f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d12, #0, #-0xf4"
+  -
+    input:
+      bytes: [ 0x3c, 0xc4 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #-0x78"
+  -
+    input:
+      bytes: [ 0xa2, 0x8f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub d15, d8"
+  -
+    input:
+      bytes: [ 0x02, 0xf2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d2, d15"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0xa4, 0x72 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0x29e4"
+  -
+    input:
+      bytes: [ 0xd9, 0x22, 0xc0, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a2, [a2]#0x7c00"
+  -
+    input:
+      bytes: [ 0x82, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d0, #0"
+  -
+    input:
+      bytes: [ 0x37, 0x00, 0x68, 0x40 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d4, d0, #0, #0x8"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x5b, 0xfc ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x74a"
+  -
+    input:
+      bytes: [ 0x37, 0x00, 0xe7, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d0, d0, #0x1, #0x7"
+  -
+    input:
+      bytes: [ 0xdf, 0x12, 0x03, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d2, #0x1, #0x6"
+  -
+    input:
+      bytes: [ 0x91, 0x10, 0x00, 0xa3 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a sp, #0x3001"
+  -
+    input:
+      bytes: [ 0xc2, 0x31 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d1, #0x3"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x2f, 0xf8 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0xfa2"
+  -
+    input:
+      bytes: [ 0x37, 0xf1, 0x08, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d1, d15, #0, #0x8"
+  -
+    input:
+      bytes: [ 0x3b, 0x00, 0x98, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d15, #0x980"
+  -
+    input:
+      bytes: [ 0x82, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d9, #0"
+  -
+    input:
+      bytes: [ 0xbe, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d1, #0x20"
+  -
+    input:
+      bytes: [ 0xda, 0x1d ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d15, #0x1d"
+  -
+    input:
+      bytes: [ 0x3f, 0x10, 0xee, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt.u d0, d1, #-0x24"
+  -
+    input:
+      bytes: [ 0x82, 0x11 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d1, #0x1"
+  -
+    input:
+      bytes: [ 0x8f, 0x3f, 0x00, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d0, d15, #0x3"
+  -
+    input:
+      bytes: [ 0x40, 0xe4 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.aa a4, a14"
+  -
+    input:
+      bytes: [ 0xc5, 0x06, 0x14, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a6, #0x14"
+  -
+    input:
+      bytes: [ 0x96, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or d15, #0x80"
+  -
+    input:
+      bytes: [ 0x91, 0x10, 0x00, 0x21 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a2, #0x1001"
+  -
+    input:
+      bytes: [ 0x26, 0x0f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d15, d0"
+  -
+    input:
+      bytes: [ 0x0f, 0x31, 0x10, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha d1, d1, d3"
+  -
+    input:
+      bytes: [ 0x91, 0x30, 0x00, 0x3f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a3, #0xf003"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0x14, 0x23 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0x3094"
+  -
+    input:
+      bytes: [ 0x6d, 0xe8, 0x80, 0x11 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x2fdd00"
+  -
+    input:
+      bytes: [ 0x6e, 0x1d ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d15, #0x3a"
+  -
+    input:
+      bytes: [ 0x7f, 0xf9, 0x02, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jge.u d9, d15, #0x4"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0xe8, 0xc2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0x2f28"
+  -
+    input:
+      bytes: [ 0x37, 0x5f, 0x04, 0xf4 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, d5, #0x8, #0x4"
+  -
+    input:
+      bytes: [ 0x4b, 0xf2, 0x41, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.f d15, d2, d15"
+  -
+    input:
+      bytes: [ 0xd9, 0x22, 0x28, 0xa6 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a2, [a2]#0x62a8"
+  -
+    input:
+      bytes: [ 0xc2, 0x81 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d1, #-0x8"
+  -
+    input:
+      bytes: [ 0xbb, 0x00, 0xc2, 0xfb ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.u d15, #0xbc20"
+  -
+    input:
+      bytes: [ 0x37, 0x1f, 0x02, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, d1, #0, #0x2"
+  -
+    input:
+      bytes: [ 0x0f, 0xf1, 0x10, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha d1, d1, d15"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xf0, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x9e0"
+  -
+    input:
+      bytes: [ 0x0f, 0x3f, 0x00, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh d15, d15, d3"
+  -
+    input:
+      bytes: [ 0x02, 0xd4 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d4, d13"
+  -
+    input:
+      bytes: [ 0x40, 0x4f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.aa a15, a4"
+  -
+    input:
+      bytes: [ 0x9b, 0x1f, 0x8d, 0xf3 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addih d15, d15, #0x38d1"
+  -
+    input:
+      bytes: [ 0x7b, 0x00, 0xf0, 0x13 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh d1, #0x3f00"
+  -
+    input:
+      bytes: [ 0x7b, 0x00, 0x00, 0x14 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh d1, #0x4000"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xee, 0xe8 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x2e24"
+  -
+    input:
+      bytes: [ 0x06, 0x62 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh d2, #0x6"
+  -
+    input:
+      bytes: [ 0x4b, 0xf2, 0x51, 0xa0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "div.f d10, d2, d15"
+  -
+    input:
+      bytes: [ 0x49, 0xf2, 0x1c, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a2, [a15]#0x1c"
+  -
+    input:
+      bytes: [ 0x8f, 0x24, 0x20, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha d15, d4, #0x2"
+  -
+    input:
+      bytes: [ 0x40, 0xd4 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.aa a4, a13"
+  -
+    input:
+      bytes: [ 0x10, 0xd2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addsc.a a2, a13, d15, #0"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x6d, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x6da"
+  -
+    input:
+      bytes: [ 0xb7, 0x1f, 0x08, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, #0x1, #0, #0x8"
+  -
+    input:
+      bytes: [ 0xd9, 0x22, 0xc0, 0x0b ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a2, [a2]#-0x4400"
+  -
+    input:
+      bytes: [ 0x9a, 0x81 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d15, d1, #-0x8"
+  -
+    input:
+      bytes: [ 0x91, 0x00, 0x00, 0xf8 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a15, #0x8000"
+  -
+    input:
+      bytes: [ 0x37, 0x0f, 0x83, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, d0, #0x3, #0x3"
+  -
+    input:
+      bytes: [ 0x7e, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, d0, #0xa"
+  -
+    input:
+      bytes: [ 0x6d, 0xa0, 0xf4, 0x11 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x4023e8"
+  -
+    input:
+      bytes: [ 0x49, 0xff, 0x0c, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0xc"
+  -
+    input:
+      bytes: [ 0xb7, 0x6f, 0x08, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, #0x6, #0, #0x8"
+  -
+    input:
+      bytes: [ 0x10, 0xe4 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addsc.a a4, a14, d15, #0"
+  -
+    input:
+      bytes: [ 0x7f, 0xf0, 0x19, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jge d0, d15, #0x32"
+  -
+    input:
+      bytes: [ 0x7e, 0x91 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, d9, #0x2"
+  -
+    input:
+      bytes: [ 0x0f, 0x0f, 0x00, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh d15, d15, d0"
+  -
+    input:
+      bytes: [ 0x6e, 0xef ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d15, #-0x22"
+  -
+    input:
+      bytes: [ 0x3c, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0xa"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x25, 0x0d ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x1a4a"
+  -
+    input:
+      bytes: [ 0x42, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d1, d0"
+  -
+    input:
+      bytes: [ 0xae, 0x17 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz.t d15, #0x1, #0xe"
+  -
+    input:
+      bytes: [ 0x91, 0x40, 0x00, 0x27 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a2, #0x7004"
+  -
+    input:
+      bytes: [ 0x3b, 0x00, 0x40, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d15, #0x400"
+  -
+    input:
+      bytes: [ 0x09, 0xa0, 0xc4, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.hu d0, [sp]#0x4"
+  -
+    input:
+      bytes: [ 0x6f, 0x0f, 0xfc, 0x7f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.t d15, #0, #-0x8"
+  -
+    input:
+      bytes: [ 0x02, 0x82 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d2, d8"
+  -
+    input:
+      bytes: [ 0x37, 0x0f, 0x68, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d15, d15, #0, #0x8"
+  -
+    input:
+      bytes: [ 0x1d, 0x00, 0x02, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x4"
+  -
+    input:
+      bytes: [ 0xa2, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub d0, d1"
+  -
+    input:
+      bytes: [ 0x37, 0xf0, 0x01, 0xf3 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d0, d15, #0x6, #0x1"
+  -
+    input:
+      bytes: [ 0x91, 0x20, 0x00, 0x30 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a3, #0x2"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xd8, 0x0c ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x19b0"
+  -
+    input:
+      bytes: [ 0x6d, 0xd0, 0x80, 0x11 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x5fdd00"
+  -
+    input:
+      bytes: [ 0xae, 0x75 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz.t d15, #0x7, #0xa"
+  -
+    input:
+      bytes: [ 0x91, 0x50, 0x02, 0x2f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a2, #0xf025"
+  -
+    input:
+      bytes: [ 0x3c, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x4"
+  -
+    input:
+      bytes: [ 0xda, 0x14 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d15, #0x14"
+  -
+    input:
+      bytes: [ 0x82, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d2, #0"
+  -
+    input:
+      bytes: [ 0x82, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d7, #0"
+  -
+    input:
+      bytes: [ 0xbc, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.a a15, #0x2"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xe0, 0xfb ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x840"
+  -
+    input:
+      bytes: [ 0x37, 0x00, 0x70, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d0, d0, #0x10, #0x10"
+  -
+    input:
+      bytes: [ 0x82, 0x15 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d5, #0x1"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0xec, 0xe2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0x2fac"
+  -
+    input:
+      bytes: [ 0xbe, 0x40 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d4, #0x20"
+  -
+    input:
+      bytes: [ 0x3c, 0x1b ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x36"
+  -
+    input:
+      bytes: [ 0x37, 0xf0, 0x02, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d0, d0, d15, #0x14, #0x2"
+  -
+    input:
+      bytes: [ 0x8f, 0xff, 0x83, 0x41 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor d4, d15, #0x3f"
+  -
+    input:
+      bytes: [ 0x3e, 0x16 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d1, #0xc"
+  -
+    input:
+      bytes: [ 0x6e, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d15, #0x12"
+  -
+    input:
+      bytes: [ 0x3f, 0xf2, 0xf3, 0x7f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt d2, d15, #-0x1a"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x04, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x8"
+  -
+    input:
+      bytes: [ 0xa6, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or d0, d1"
+  -
+    input:
+      bytes: [ 0xda, 0x40 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d15, #0x40"
+  -
+    input:
+      bytes: [ 0x6e, 0x1a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d15, #0x34"
+  -
+    input:
+      bytes: [ 0x91, 0x00, 0x0f, 0xfa ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a15, #0xa0f0"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xc5, 0xfe ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x276"
+  -
+    input:
+      bytes: [ 0x9b, 0xc0, 0xfc, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addih d0, d0, #0x3fcc"
+  -
+    input:
+      bytes: [ 0x37, 0x0f, 0x02, 0xf3 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, d0, #0x6, #0x2"
+  -
+    input:
+      bytes: [ 0xdf, 0x10, 0x0a, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d0, #0x1, #0x14"
+  -
+    input:
+      bytes: [ 0x8f, 0x00, 0x21, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha d0, d0, #0x10"
+  -
+    input:
+      bytes: [ 0xfd, 0xf0, 0xed, 0x7f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "loop a15, #-0x26"
+  -
+    input:
+      bytes: [ 0x7b, 0x00, 0x00, 0xf4 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh d15, #0x4000"
+  -
+    input:
+      bytes: [ 0x37, 0x00, 0x62, 0xf2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d15, d0, #0x4, #0x2"
+  -
+    input:
+      bytes: [ 0x3f, 0x0f, 0x04, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt.u d15, d0, #0x8"
+  -
+    input:
+      bytes: [ 0x3c, 0x11 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x22"
+  -
+    input:
+      bytes: [ 0x01, 0xdd, 0x00, 0xd6 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addsc.a a13, a13, d13, #0"
+  -
+    input:
+      bytes: [ 0x82, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d0, #0x1"
+  -
+    input:
+      bytes: [ 0xee, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz d15, #0x4"
+  -
+    input:
+      bytes: [ 0x82, 0x27 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d7, #0x2"
+  -
+    input:
+      bytes: [ 0xfe, 0xdb ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, d13, #0x36"
+  -
+    input:
+      bytes: [ 0x37, 0x04, 0x68, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d15, d4, #0, #0x8"
+  -
+    input:
+      bytes: [ 0x3e, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d0, #0x8"
+  -
+    input:
+      bytes: [ 0x06, 0xf4 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh d4, #-0x1"
+  -
+    input:
+      bytes: [ 0x37, 0xf0, 0x01, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d0, d0, d15, #0, #0x1"
+  -
+    input:
+      bytes: [ 0xbf, 0xc9, 0x07, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt.u d9, #0xc, #0xe"
+  -
+    input:
+      bytes: [ 0x3c, 0x0e ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x1c"
+  -
+    input:
+      bytes: [ 0x7b, 0x00, 0x20, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh d0, #0x4200"
+  -
+    input:
+      bytes: [ 0x30, 0x43 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add.a a3, a4"
+  -
+    input:
+      bytes: [ 0x91, 0x00, 0x09, 0xfa ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a15, #0xa090"
+  -
+    input:
+      bytes: [ 0x91, 0x10, 0x00, 0xf3 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a15, #0x3001"
+  -
+    input:
+      bytes: [ 0x3c, 0x20 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x40"
+  -
+    input:
+      bytes: [ 0x6d, 0xe8, 0xe1, 0x0e ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x2fe23e"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xaa, 0xf9 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0xcac"
+  -
+    input:
+      bytes: [ 0xb7, 0x7f, 0x03, 0xfe ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, #0x7, #0x1c, #0x3"
+  -
+    input:
+      bytes: [ 0xb7, 0x00, 0x81, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d0, d0, #0, #0x3, #0x1"
+  -
+    input:
+      bytes: [ 0x0f, 0x10, 0x10, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha d0, d0, d1"
+  -
+    input:
+      bytes: [ 0xa2, 0x0f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub d15, d0"
+  -
+    input:
+      bytes: [ 0xc6, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor d1, d15"
+  -
+    input:
+      bytes: [ 0x8f, 0x3f, 0x00, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh d1, d15, #0x3"
+  -
+    input:
+      bytes: [ 0x49, 0xcf, 0x30, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a12]#0x30"
+  -
+    input:
+      bytes: [ 0x26, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d0, d1"
+  -
+    input:
+      bytes: [ 0x5e, 0x1b ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, #0x1, #0x16"
+  -
+    input:
+      bytes: [ 0xc6, 0x2f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor d15, d2"
+  -
+    input:
+      bytes: [ 0x53, 0x01, 0x21, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul d15, d1, #0x10"
+  -
+    input:
+      bytes: [ 0x91, 0x40, 0x00, 0xf6 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a15, #0x6004"
+  -
+    input:
+      bytes: [ 0xbf, 0xc9, 0x05, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt.u d9, #0xc, #0xa"
+  -
+    input:
+      bytes: [ 0x8f, 0xff, 0x83, 0xa1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor d10, d15, #0x3f"
+  -
+    input:
+      bytes: [ 0x91, 0x40, 0x00, 0x26 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a2, #0x6004"
+  -
+    input:
+      bytes: [ 0x37, 0xf3, 0x08, 0x30 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d3, d3, d15, #0, #0x8"
+  -
+    input:
+      bytes: [ 0x4b, 0xf0, 0x51, 0x20 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "div.f d2, d0, d15"
+  -
+    input:
+      bytes: [ 0x82, 0x0b ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d11, #0"
+  -
+    input:
+      bytes: [ 0x42, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d0, d15"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0x30, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0x3030"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xbe, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x57c"
+  -
+    input:
+      bytes: [ 0xb7, 0x0f, 0x1c, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, #0, #0, #0x1c"
+  -
+    input:
+      bytes: [ 0xa6, 0x64 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or d4, d6"
+  -
+    input:
+      bytes: [ 0x37, 0x4f, 0x9f, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, d4, #0x1, #0x1f"
+  -
+    input:
+      bytes: [ 0x6d, 0xe8, 0xf4, 0x11 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x2fdc18"
+  -
+    input:
+      bytes: [ 0x4b, 0x30, 0x11, 0x42 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "div.u e4, d0, d3"
+  -
+    input:
+      bytes: [ 0xd9, 0x44, 0x3c, 0x50 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a4, [a4]#0x17c"
+  -
+    input:
+      bytes: [ 0xc2, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d15, #-0x1"
+  -
+    input:
+      bytes: [ 0x26, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d1, d15"
+  -
+    input:
+      bytes: [ 0x91, 0x00, 0x0f, 0xf8 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a15, #0x80f0"
+  -
+    input:
+      bytes: [ 0x91, 0x30, 0x00, 0x4f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a4, #0xf003"
+  -
+    input:
+      bytes: [ 0x3b, 0x00, 0x02, 0x60 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d6, #0x20"
+  -
+    input:
+      bytes: [ 0x3f, 0xf9, 0x65, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt.u d9, d15, #-0x136"
+  -
+    input:
+      bytes: [ 0x3e, 0x58 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d5, #0x10"
+  -
+    input:
+      bytes: [ 0x10, 0xaf ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addsc.a a15, sp, d15, #0"
+  -
+    input:
+      bytes: [ 0xdf, 0x0c, 0xd3, 0x7f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d12, #0, #-0x5a"
+  -
+    input:
+      bytes: [ 0x53, 0x00, 0x21, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul d15, d0, #0x10"
+  -
+    input:
+      bytes: [ 0x3e, 0x4b ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d4, #0x16"
+  -
+    input:
+      bytes: [ 0x3f, 0xf0, 0xfd, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt.u d0, d15, #-0x6"
+  -
+    input:
+      bytes: [ 0xdf, 0x1f, 0xfe, 0x7f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, #0x1, #-0x4"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x6f, 0xfc ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x722"
+  -
+    input:
+      bytes: [ 0xfc, 0x4e ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "loop a4, #-0x4"
+  -
+    input:
+      bytes: [ 0x8b, 0x5f, 0x20, 0xf3 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "min.u d15, d15, #0x5"
+  -
+    input:
+      bytes: [ 0x01, 0xf0, 0x00, 0xf6 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addsc.a a15, a15, d0, #0"
+  -
+    input:
+      bytes: [ 0x8f, 0x3f, 0x00, 0x30 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh d3, d15, #0x3"
+  -
+    input:
+      bytes: [ 0x3c, 0x34 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x68"
+  -
+    input:
+      bytes: [ 0x90, 0xdd ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addsc.a a13, a13, d15, #0x2"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xa6, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0xb4"
+  -
+    input:
+      bytes: [ 0x37, 0x4f, 0x04, 0xf8 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, d4, #0x10, #0x4"
+  -
+    input:
+      bytes: [ 0x37, 0x00, 0x68, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d0, d0, #0, #0x8"
+  -
+    input:
+      bytes: [ 0x10, 0xcc ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addsc.a a12, a12, d15, #0"
+  -
+    input:
+      bytes: [ 0xee, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz d15, #0xc"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x00, 0xfb ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0xa00"
+  -
+    input:
+      bytes: [ 0x10, 0xcf ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addsc.a a15, a12, d15, #0"
+  -
+    input:
+      bytes: [ 0x7f, 0x0f, 0x07, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jge.u d15, d0, #0xe"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0x08, 0xa6 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0x6288"
+  -
+    input:
+      bytes: [ 0xbe, 0x65 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d6, #0x2a"
+  -
+    input:
+      bytes: [ 0x3e, 0x5a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d5, #0x14"
+  -
+    input:
+      bytes: [ 0x26, 0x2f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d15, d2"
+  -
+    input:
+      bytes: [ 0x92, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d0, d15, #0x1"
+  -
+    input:
+      bytes: [ 0x26, 0x3f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d15, d3"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x8b, 0xfb ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x8ea"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xf1, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x1e2"
+  -
+    input:
+      bytes: [ 0xdf, 0x04, 0x7c, 0x7f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d4, #0, #-0x108"
+  -
+    input:
+      bytes: [ 0x8f, 0x4f, 0x1f, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh d1, d15, #-0xc"
+  -
+    input:
+      bytes: [ 0xd9, 0x88, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a8, [a8]#0"
+  -
+    input:
+      bytes: [ 0xd7, 0x10, 0x21, 0x0f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "imask e0, #0x1, d15, #0x1"
+  -
+    input:
+      bytes: [ 0x8f, 0x23, 0x20, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha d15, d3, #0x2"
+  -
+    input:
+      bytes: [ 0x6b, 0x0f, 0x61, 0x41 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd.f d4, d1, d15, d0"
+  -
+    input:
+      bytes: [ 0xc2, 0x1f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d15, #0x1"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xb6, 0xfa ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0xa94"
+  -
+    input:
+      bytes: [ 0xc5, 0x02, 0x3f, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a2, #0x7f"
+  -
+    input:
+      bytes: [ 0x80, 0x20 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.d d0, a2"
+  -
+    input:
+      bytes: [ 0xbe, 0x9c ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d9, #0x38"
+  -
+    input:
+      bytes: [ 0x6e, 0xe8 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d15, #-0x30"
+  -
+    input:
+      bytes: [ 0x91, 0x10, 0x00, 0xf4 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a15, #0x4001"
+  -
+    input:
+      bytes: [ 0xe2, 0x9f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul d15, d9"
+  -
+    input:
+      bytes: [ 0x3c, 0x1e ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x3c"
+  -
+    input:
+      bytes: [ 0xb7, 0x04, 0x08, 0xfc ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d4, #0, #0x18, #0x8"
+  -
+    input:
+      bytes: [ 0x6e, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d15, #0xe"
+  -
+    input:
+      bytes: [ 0xbb, 0x00, 0x52, 0x0c ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.u d0, #0xc520"
+  -
+    input:
+      bytes: [ 0xa6, 0x20 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or d0, d2"
+  -
+    input:
+      bytes: [ 0x3c, 0x1d ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x3a"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x2d, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0xe5a"
+  -
+    input:
+      bytes: [ 0x8f, 0x0f, 0x1f, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh d0, d15, #-0x10"
+  -
+    input:
+      bytes: [ 0x8b, 0x09, 0x01, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d0, d9, #0x10"
+  -
+    input:
+      bytes: [ 0xc2, 0xfc ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d12, #-0x1"
+  -
+    input:
+      bytes: [ 0x3b, 0xf0, 0x49, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d0, #0x249f"
+  -
+    input:
+      bytes: [ 0x4b, 0x1f, 0x51, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "div.f d15, d15, d1"
+  -
+    input:
+      bytes: [ 0x60, 0x22 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.a a2, d2"
+  -
+    input:
+      bytes: [ 0xde, 0x25 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, #0x2, #0x2a"
+  -
+    input:
+      bytes: [ 0x5e, 0x26 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, #0x2, #0xc"
+  -
+    input:
+      bytes: [ 0x86, 0x20 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha d0, #0x2"
+  -
+    input:
+      bytes: [ 0x82, 0x18 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d8, #0x1"
+  -
+    input:
+      bytes: [ 0x37, 0x5f, 0x02, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, d5, #0, #0x2"
+  -
+    input:
+      bytes: [ 0xbf, 0x89, 0x05, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt.u d9, #0x8, #0xa"
+  -
+    input:
+      bytes: [ 0x5e, 0x16 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, #0x1, #0xc"
+  -
+    input:
+      bytes: [ 0x8f, 0xf9, 0x01, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d15, d9, #0x1f"
+  -
+    input:
+      bytes: [ 0xbb, 0x00, 0xc2, 0x1b ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.u d1, #0xbc20"
+  -
+    input:
+      bytes: [ 0x02, 0xc4 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d4, d12"
+  -
+    input:
+      bytes: [ 0x3c, 0x25 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x4a"
+  -
+    input:
+      bytes: [ 0xc2, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d0, #-0x1"
+  -
+    input:
+      bytes: [ 0x15, 0xd0, 0xc0, 0xe3 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "stlcx #0xd0003f80"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0x38, 0xf2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0x23f8"
+  -
+    input:
+      bytes: [ 0x2e, 0x1b ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.t d15, #0x1, #0x16"
+  -
+    input:
+      bytes: [ 0x3c, 0x19 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x32"
+  -
+    input:
+      bytes: [ 0xe2, 0x0f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul d15, d0"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x9e, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x73c"
+  -
+    input:
+      bytes: [ 0x37, 0xf0, 0x02, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d0, d0, d15, #0xc, #0x2"
+  -
+    input:
+      bytes: [ 0x1e, 0x13 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, #0x1, #0x6"
+  -
+    input:
+      bytes: [ 0x3c, 0x31 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x62"
+  -
+    input:
+      bytes: [ 0xff, 0xc9, 0x03, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jge.u d9, #0xc, #0x6"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0x34, 0x23 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0x30b4"
+  -
+    input:
+      bytes: [ 0x37, 0x0f, 0x05, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, d0, #0, #0x5"
+  -
+    input:
+      bytes: [ 0x91, 0x00, 0x0c, 0xf8 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a15, #0x80c0"
+  -
+    input:
+      bytes: [ 0x7b, 0x80, 0x2c, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh d0, #0x42c8"
+  -
+    input:
+      bytes: [ 0xbb, 0x00, 0x40, 0x2f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.u d2, #0xf400"
+  -
+    input:
+      bytes: [ 0xdf, 0x0f, 0xb1, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, #0, #0x162"
+  -
+    input:
+      bytes: [ 0xf6, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz d0, #0x4"
+  -
+    input:
+      bytes: [ 0x6f, 0x7f, 0xec, 0x7f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.t d15, #0x7, #-0x28"
+  -
+    input:
+      bytes: [ 0x3c, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0xc"
+  -
+    input:
+      bytes: [ 0x60, 0x14 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.a a4, d1"
+  -
+    input:
+      bytes: [ 0x49, 0xff, 0x00, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0"
+  -
+    input:
+      bytes: [ 0x3c, 0x12 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x24"
+  -
+    input:
+      bytes: [ 0xd9, 0x44, 0x20, 0x93 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a4, [a4]#0x3260"
+  -
+    input:
+      bytes: [ 0x91, 0x30, 0x00, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a15, #0xf003"
+  -
+    input:
+      bytes: [ 0x76, 0x6d ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d6, #0x1a"
+  -
+    input:
+      bytes: [ 0x6f, 0x0f, 0xf3, 0x7f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.t d15, #0, #-0x1a"
+  -
+    input:
+      bytes: [ 0xfc, 0x6e ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "loop a6, #-0x4"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xac, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0xa8"
+  -
+    input:
+      bytes: [ 0xef, 0x4f, 0x04, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.t d15, #0x14, #0x8"
+  -
+    input:
+      bytes: [ 0xbb, 0x70, 0x71, 0xfb ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.u d15, #0xb717"
+  -
+    input:
+      bytes: [ 0x0f, 0xf0, 0x10, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha d0, d0, d15"
+  -
+    input:
+      bytes: [ 0x0f, 0x04, 0x10, 0x40 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha d4, d4, d0"
+  -
+    input:
+      bytes: [ 0x5e, 0x14 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, #0x1, #0x8"
+  -
+    input:
+      bytes: [ 0x02, 0x28 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d8, d2"
+  -
+    input:
+      bytes: [ 0x37, 0x0f, 0x81, 0xf7 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, d0, #0xf, #0x1"
+  -
+    input:
+      bytes: [ 0x37, 0xf0, 0x87, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d0, d0, d15, #0x9, #0x7"
+  -
+    input:
+      bytes: [ 0xa0, 0x66 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.a a6, #0x6"
+  -
+    input:
+      bytes: [ 0x37, 0x0f, 0x02, 0xf2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, d0, #0x4, #0x2"
+  -
+    input:
+      bytes: [ 0x96, 0x40 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or d15, #0x40"
+  -
+    input:
+      bytes: [ 0xc2, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d0, #0x1"
+  -
+    input:
+      bytes: [ 0x8b, 0x87, 0x01, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d0, d7, #0x18"
+  -
+    input:
+      bytes: [ 0x91, 0x60, 0x88, 0x4f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a4, #0xf886"
+  -
+    input:
+      bytes: [ 0x49, 0xff, 0x20, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0x20"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x0f, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x21e"
+  -
+    input:
+      bytes: [ 0x3e, 0x0e ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d0, #0x1c"
+  -
+    input:
+      bytes: [ 0x3c, 0x23 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x46"
+  -
+    input:
+      bytes: [ 0xdf, 0x2f, 0x91, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, #0x2, #-0xde"
+  -
+    input:
+      bytes: [ 0x3c, 0x0c ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x18"
+  -
+    input:
+      bytes: [ 0x10, 0xf2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addsc.a a2, a15, d15, #0"
+  -
+    input:
+      bytes: [ 0x37, 0xf0, 0x01, 0x0f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d0, d0, d15, #0x1e, #0x1"
+  -
+    input:
+      bytes: [ 0xda, 0xbc ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d15, #0xbc"
+  -
+    input:
+      bytes: [ 0x0f, 0x05, 0x10, 0x50 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha d5, d5, d0"
+  -
+    input:
+      bytes: [ 0x91, 0x00, 0x06, 0xf8 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a15, #0x8060"
+  -
+    input:
+      bytes: [ 0x3c, 0x27 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x4e"
+  -
+    input:
+      bytes: [ 0xda, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d15, #0"
+  -
+    input:
+      bytes: [ 0x49, 0xa5, 0x00, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a5, [sp]#0"
+  -
+    input:
+      bytes: [ 0x96, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or d15, #0x2"
+  -
+    input:
+      bytes: [ 0x37, 0x0f, 0x81, 0xf2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, d0, #0x5, #0x1"
+  -
+    input:
+      bytes: [ 0x4b, 0x02, 0x71, 0x41 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ftouz d4, d2"
+  -
+    input:
+      bytes: [ 0x3e, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d0, #0x14"
+  -
+    input:
+      bytes: [ 0xa2, 0xfc ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub d12, d15"
+  -
+    input:
+      bytes: [ 0x53, 0xc9, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul d0, d9, #0xc"
+  -
+    input:
+      bytes: [ 0xd9, 0x44, 0xe0, 0x22 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a4, [a4]#0x2ca0"
+  -
+    input:
+      bytes: [ 0x60, 0x4f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.a a15, d4"
+  -
+    input:
+      bytes: [ 0x49, 0xa4, 0x00, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a4, [sp]#0"
+  -
+    input:
+      bytes: [ 0xb7, 0x0f, 0x81, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, #0, #0x1, #0x1"
+  -
+    input:
+      bytes: [ 0x4b, 0x0f, 0x41, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "itof d15, d15"
+  -
+    input:
+      bytes: [ 0x3e, 0x93 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d9, #0x6"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0x0c, 0xb0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0x2cc"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x38, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x70"
+  -
+    input:
+      bytes: [ 0xe2, 0x90 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul d0, d9"
+  -
+    input:
+      bytes: [ 0x4b, 0x0f, 0x41, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.f d1, d15, d0"
+  -
+    input:
+      bytes: [ 0xa6, 0x12 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or d2, d1"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0x41, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "itof d15, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x14, 0x1f, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d0, d4, #-0xf"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x9f, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x133e"
+  -
+    input:
+      bytes: [ 0x7e, 0x92 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, d9, #0x4"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x63, 0xfb ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x93a"
+  -
+    input:
+      bytes: [ 0x3c, 0x33 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x66"
+  -
+    input:
+      bytes: [ 0x6e, 0x0e ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d15, #0x1c"
+  -
+    input:
+      bytes: [ 0x1d, 0x00, 0xd4, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x3a8"
+  -
+    input:
+      bytes: [ 0xbb, 0x00, 0xa0, 0x1b ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.u d1, #0xba00"
+  -
+    input:
+      bytes: [ 0x6e, 0xf6 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d15, #-0x14"
+  -
+    input:
+      bytes: [ 0x77, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "dextr d0, d0, d0, #0x8"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xb4, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0xf68"
+  -
+    input:
+      bytes: [ 0x02, 0x8f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d15, d8"
+  -
+    input:
+      bytes: [ 0x26, 0xf2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d2, d15"
+  -
+    input:
+      bytes: [ 0x80, 0xf4 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.d d4, a15"
+  -
+    input:
+      bytes: [ 0x37, 0x04, 0xe8, 0x0b ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d0, d4, #0x17, #0x8"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x1f, 0xfb ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x9c2"
+  -
+    input:
+      bytes: [ 0x3b, 0x00, 0x00, 0x31 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d3, #0x1000"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x26, 0x0e ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x1c4c"
+  -
+    input:
+      bytes: [ 0x3e, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d0, #0x10"
+  -
+    input:
+      bytes: [ 0xd9, 0x22, 0xb8, 0xd2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a2, [a2]#0x2b78"
+  -
+    input:
+      bytes: [ 0x30, 0xf3 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add.a a3, a15"
+  -
+    input:
+      bytes: [ 0x91, 0x00, 0x00, 0x27 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a2, #0x7000"
+  -
+    input:
+      bytes: [ 0x37, 0x03, 0x68, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d0, d3, #0x10, #0x8"
+  -
+    input:
+      bytes: [ 0x91, 0x00, 0x09, 0xf8 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a15, #0x8090"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0x61, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "utof d15, d0"
+  -
+    input:
+      bytes: [ 0x6e, 0xc9 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d15, #-0x6e"
+  -
+    input:
+      bytes: [ 0x9b, 0xef, 0xcb, 0xf4 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addih d15, d15, #0x4cbe"
+  -
+    input:
+      bytes: [ 0x4b, 0x0f, 0x61, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "utof d15, d15"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0xb8, 0x42 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0x2938"
+  -
+    input:
+      bytes: [ 0xdf, 0x0c, 0x9b, 0x7f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d12, #0, #-0xca"
+  -
+    input:
+      bytes: [ 0x7b, 0xd0, 0x38, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh d0, #0x138d"
+  -
+    input:
+      bytes: [ 0x53, 0x47, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul d0, d7, #0x4"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xd3, 0x0d ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x1ba6"
+  -
+    input:
+      bytes: [ 0xbf, 0x10, 0x15, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt.u d0, #0x1, #0x2a"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x63, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0xc6"
+  -
+    input:
+      bytes: [ 0x82, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d10, #0"
+  -
+    input:
+      bytes: [ 0xa6, 0x4f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or d15, d4"
+  -
+    input:
+      bytes: [ 0x53, 0x4a, 0x20, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul d15, d10, #0x4"
+  -
+    input:
+      bytes: [ 0x37, 0xf0, 0x81, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d0, d15, #0x3, #0x1"
+  -
+    input:
+      bytes: [ 0x0f, 0x0f, 0xb0, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "clz d15, d15"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xcd, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0xf9a"
+  -
+    input:
+      bytes: [ 0x91, 0x00, 0x10, 0xf8 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a15, #0x8100"
+  -
+    input:
+      bytes: [ 0x26, 0x32 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d2, d3"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x22, 0xfb ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x9bc"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x56, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x2ac"
+  -
+    input:
+      bytes: [ 0x91, 0x00, 0x00, 0x48 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a4, #0x8000"
+  -
+    input:
+      bytes: [ 0xbb, 0x00, 0xc2, 0x0b ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.u d0, #0xbc20"
+  -
+    input:
+      bytes: [ 0x16, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d15, #0x7"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0x24, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0x3e4"
+  -
+    input:
+      bytes: [ 0x53, 0x41, 0x20, 0x30 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul d3, d1, #0x4"
+  -
+    input:
+      bytes: [ 0x0f, 0x2f, 0x00, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh d15, d15, d2"
+  -
+    input:
+      bytes: [ 0x3b, 0x00, 0x05, 0x40 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d4, #0x50"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0x00, 0x0e ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#-0x2000"
+  -
+    input:
+      bytes: [ 0x91, 0x00, 0x00, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a8, #0"
+  -
+    input:
+      bytes: [ 0x4e, 0xf3 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jgtz d15, #0x6"
+  -
+    input:
+      bytes: [ 0x06, 0xec ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh d12, #-0x2"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xc6, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0xf8c"
+  -
+    input:
+      bytes: [ 0x76, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d0, #0x6"
+  -
+    input:
+      bytes: [ 0x37, 0x00, 0x62, 0xfa ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d15, d0, #0x14, #0x2"
+  -
+    input:
+      bytes: [ 0x57, 0x00, 0x62, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d15, d0, d15, #0x2"
+  -
+    input:
+      bytes: [ 0xff, 0xc9, 0x04, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jge.u d9, #0xc, #0x8"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0x0c, 0x60 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0x18c"
+  -
+    input:
+      bytes: [ 0x6e, 0x30 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d15, #0x60"
+  -
+    input:
+      bytes: [ 0x80, 0xcf ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.d d15, a12"
+  -
+    input:
+      bytes: [ 0xc2, 0x11 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d1, #0x1"
+  -
+    input:
+      bytes: [ 0xdf, 0x04, 0x3b, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d4, #0, #0x76"
+  -
+    input:
+      bytes: [ 0xb7, 0x7f, 0x08, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, #0x7, #0, #0x8"
+  -
+    input:
+      bytes: [ 0x37, 0x0f, 0x01, 0xf6 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, d0, #0xc, #0x1"
+  -
+    input:
+      bytes: [ 0xd9, 0x55, 0x08, 0x60 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a5, [a5]#0x188"
+  -
+    input:
+      bytes: [ 0x42, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d1, d15"
+  -
+    input:
+      bytes: [ 0xa2, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub d0, d15"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x78, 0xfb ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x910"
+  -
+    input:
+      bytes: [ 0x3b, 0x00, 0xd0, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d0, #0x2d00"
+  -
+    input:
+      bytes: [ 0xd9, 0x11, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a1, [a1]#0"
+  -
+    input:
+      bytes: [ 0x6d, 0x88, 0x80, 0x11 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x102300"
+  -
+    input:
+      bytes: [ 0xda, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d15, #0x5"
+  -
+    input:
+      bytes: [ 0x3c, 0x0d ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x1a"
+  -
+    input:
+      bytes: [ 0xe2, 0x1f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul d15, d1"
+  -
+    input:
+      bytes: [ 0x8f, 0x10, 0x00, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d0, d0, #0x1"
+  -
+    input:
+      bytes: [ 0x15, 0xd0, 0xc0, 0xf7 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "stucx #0xd0003fc0"
+  -
+    input:
+      bytes: [ 0xbf, 0x89, 0x06, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt.u d9, #0x8, #0xc"
+  -
+    input:
+      bytes: [ 0x6f, 0x1f, 0xfc, 0x7f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.t d15, #0x1, #-0x8"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0x26, 0xb2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0x22e6"
+  -
+    input:
+      bytes: [ 0x91, 0x40, 0x00, 0xa7 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a sp, #0x7004"
+  -
+    input:
+      bytes: [ 0xd9, 0x22, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a2, [a2]#0x400"
+  -
+    input:
+      bytes: [ 0x91, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a0, #0"
+  -
+    input:
+      bytes: [ 0x80, 0x41 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.d d1, a4"
+  -
+    input:
+      bytes: [ 0x9b, 0xe0, 0xcb, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addih d0, d0, #0x4cbe"
+  -
+    input:
+      bytes: [ 0x10, 0xdf ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addsc.a a15, a13, d15, #0"
+  -
+    input:
+      bytes: [ 0x91, 0xc0, 0x88, 0x4f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a4, #0xf88c"
+  -
+    input:
+      bytes: [ 0x40, 0xbf ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.aa a15, a11"
+  -
+    input:
+      bytes: [ 0xc2, 0xf3 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d3, #-0x1"
+  -
+    input:
+      bytes: [ 0x02, 0x49 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d9, d4"
+  -
+    input:
+      bytes: [ 0x4b, 0xf0, 0x51, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "div.f d15, d0, d15"
+  -
+    input:
+      bytes: [ 0xb7, 0x2f, 0x08, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, #0x2, #0, #0x8"
+  -
+    input:
+      bytes: [ 0x37, 0x0f, 0x02, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, d0, #0, #0x2"
+  -
+    input:
+      bytes: [ 0xa6, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or d1, d15"
+  -
+    input:
+      bytes: [ 0x10, 0xef ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addsc.a a15, a14, d15, #0"
+  -
+    input:
+      bytes: [ 0x49, 0xf5, 0x00, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a5, [a15]#0"
+  -
+    input:
+      bytes: [ 0x76, 0xdb ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d13, #0x16"
+  -
+    input:
+      bytes: [ 0x9b, 0x8f, 0xb9, 0xf4 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addih d15, d15, #0x4b98"
+  -
+    input:
+      bytes: [ 0x02, 0x2f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d15, d2"
+  -
+    input:
+      bytes: [ 0x3c, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x6"
+  -
+    input:
+      bytes: [ 0xd9, 0x55, 0x3c, 0x50 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a5, [a5]#0x17c"
+  -
+    input:
+      bytes: [ 0xc6, 0x30 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor d0, d3"
+  -
+    input:
+      bytes: [ 0x2e, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.t d15, #0, #0x6"
+  -
+    input:
+      bytes: [ 0xb7, 0x4f, 0x08, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, #0x4, #0, #0x8"
+  -
+    input:
+      bytes: [ 0x91, 0x00, 0x06, 0xfa ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a15, #0xa060"
+  -
+    input:
+      bytes: [ 0x53, 0x4a, 0x20, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul d1, d10, #0x4"
+  -
+    input:
+      bytes: [ 0x3c, 0x0f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x1e"
+  -
+    input:
+      bytes: [ 0x8f, 0xf9, 0x03, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d15, d9, #0x3f"
+  -
+    input:
+      bytes: [ 0x4b, 0xaf, 0x41, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.f d15, d15, d10"
+  -
+    input:
+      bytes: [ 0x82, 0x20 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d0, #0x2"
+  -
+    input:
+      bytes: [ 0x0f, 0x10, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh d0, d0, d1"
+  -
+    input:
+      bytes: [ 0x37, 0x0f, 0x82, 0xf2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, d0, #0x5, #0x2"
+  -
+    input:
+      bytes: [ 0x3c, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x14"
+  -
+    input:
+      bytes: [ 0x3c, 0x13 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x26"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xe7, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0xfce"
+  -
+    input:
+      bytes: [ 0x3f, 0x40, 0xe3, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt.u d0, d4, #-0x3a"
+  -
+    input:
+      bytes: [ 0x8f, 0x21, 0x00, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh d15, d1, #0x2"
+  -
+    input:
+      bytes: [ 0x6f, 0x0f, 0xfe, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz.t d15, #0, #-0x4"
+  -
+    input:
+      bytes: [ 0x37, 0xf0, 0x03, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d0, d15, #0, #0x3"
+  -
+    input:
+      bytes: [ 0x4b, 0x0f, 0x71, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ftouz d15, d15"
+  -
+    input:
+      bytes: [ 0x91, 0x10, 0x00, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a15, #0x1001"
+  -
+    input:
+      bytes: [ 0x3c, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x2"
+  -
+    input:
+      bytes: [ 0x06, 0x63 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh d3, #0x6"
+  -
+    input:
+      bytes: [ 0xd9, 0x44, 0xb0, 0xd2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a4, [a4]#0x2b70"
+  -
+    input:
+      bytes: [ 0x1d, 0x00, 0x9c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x138"
+  -
+    input:
+      bytes: [ 0x02, 0x84 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d4, d8"
+  -
+    input:
+      bytes: [ 0x89, 0xcf, 0x8a, 0x28 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [a12]#0x8a, d15"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x41, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x282"
+  -
+    input:
+      bytes: [ 0xa6, 0x30 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or d0, d3"
+  -
+    input:
+      bytes: [ 0x3c, 0xfe ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #-0x4"
+  -
+    input:
+      bytes: [ 0x16, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d15, #0x1"
+  -
+    input:
+      bytes: [ 0x3e, 0x67 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d6, #0xe"
+  -
+    input:
+      bytes: [ 0x4b, 0xf1, 0x51, 0x20 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "div.f d2, d1, d15"
+  -
+    input:
+      bytes: [ 0xa6, 0x0f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or d15, d0"
+  -
+    input:
+      bytes: [ 0x7f, 0x20, 0x09, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jge.u d0, d2, #0x12"
+  -
+    input:
+      bytes: [ 0x53, 0x47, 0x20, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul d1, d7, #0x4"
+  -
+    input:
+      bytes: [ 0x4b, 0xf1, 0x51, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "div.f d0, d1, d15"
+  -
+    input:
+      bytes: [ 0x8b, 0x60, 0x09, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "rsub d15, d0, #0x96"
+  -
+    input:
+      bytes: [ 0xdf, 0x1f, 0xfa, 0x7f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, #0x1, #-0xc"
+  -
+    input:
+      bytes: [ 0xee, 0xf6 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz d15, #-0x14"
+  -
+    input:
+      bytes: [ 0x82, 0xf3 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d3, #-0x1"
+  -
+    input:
+      bytes: [ 0x53, 0xcf, 0x20, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul d15, d15, #0xc"
+  -
+    input:
+      bytes: [ 0x91, 0x00, 0x00, 0xf7 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a15, #0x7000"
+  -
+    input:
+      bytes: [ 0x3c, 0x94 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #-0xd8"
+  -
+    input:
+      bytes: [ 0x40, 0xc4 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.aa a4, a12"
+  -
+    input:
+      bytes: [ 0xc2, 0xe0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d0, #-0x2"
+  -
+    input:
+      bytes: [ 0x91, 0x00, 0x00, 0x90 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a9, #0"
+  -
+    input:
+      bytes: [ 0x91, 0x00, 0x00, 0x57 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a5, #0x7000"
diff --git a/tests/MC/TriCore/J_Call_Loop.s.yaml b/tests/MC/TriCore/J_Call_Loop.s.yaml
new file mode 100644
index 000000000..5f82468c8
--- /dev/null
+++ b/tests/MC/TriCore/J_Call_Loop.s.yaml
@@ -0,0 +1,2521 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x9d, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0xc6"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x02, 0xfe ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x3fc"
+  -
+    input:
+      bytes: [ 0x7f, 0xf8, 0x0b, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jge.u d8, d15, #0x16"
+  -
+    input:
+      bytes: [ 0x3c, 0x0b ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x16"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xb3, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x9a"
+  -
+    input:
+      bytes: [ 0xff, 0x88, 0x1f, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jge.u d8, #0x8, #0x3e"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x1b, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x36"
+  -
+    input:
+      bytes: [ 0x5e, 0x17 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, #0x1, #0xe"
+  -
+    input:
+      bytes: [ 0x3c, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x10"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xbe, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x84"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x58, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x150"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xbd, 0xfd ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x486"
+  -
+    input:
+      bytes: [ 0x7f, 0xf8, 0x0d, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jge.u d8, d15, #0x1a"
+  -
+    input:
+      bytes: [ 0x3c, 0x0d ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x1a"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x6a, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x12c"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x94, 0xfa ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0xad8"
+  -
+    input:
+      bytes: [ 0x3c, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x2"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x87, 0xfa ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0xaf2"
+  -
+    input:
+      bytes: [ 0xbf, 0x45, 0x0b, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt.u d5, #0x4, #0x16"
+  -
+    input:
+      bytes: [ 0x6f, 0x04, 0x05, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.t d4, #0, #0xa"
+  -
+    input:
+      bytes: [ 0x3c, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x6"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x9a, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0xcc"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x4e, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x164"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x83, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0xfa"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x37, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x192"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x32, 0xfa ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0xb9c"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xc3, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x7a"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x1e, 0xfa ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0xbc4"
+  -
+    input:
+      bytes: [ 0x7f, 0x81, 0x0a, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jge.u d1, d8, #0x14"
+  -
+    input:
+      bytes: [ 0x3f, 0x08, 0x08, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt.u d8, d0, #0x10"
+  -
+    input:
+      bytes: [ 0x7f, 0x80, 0x04, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jge.u d0, d8, #0x8"
+  -
+    input:
+      bytes: [ 0x3c, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0xa"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xa6, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0xb4"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x26, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x1b4"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xda, 0xfe ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x24c"
+  -
+    input:
+      bytes: [ 0xdf, 0x04, 0x31, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d4, #0, #0x62"
+  -
+    input:
+      bytes: [ 0x76, 0x6b ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d6, #0x16"
+  -
+    input:
+      bytes: [ 0x3c, 0x0c ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x18"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xdc, 0xfe ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x248"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x8d, 0xfe ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x2e6"
+  -
+    input:
+      bytes: [ 0x3c, 0x0e ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x1c"
+  -
+    input:
+      bytes: [ 0x6e, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d15, #0x6"
+  -
+    input:
+      bytes: [ 0xbf, 0x81, 0xf3, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt.u d1, #0x8, #-0x1a"
+  -
+    input:
+      bytes: [ 0xdf, 0x10, 0xee, 0x7f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d0, #0x1, #-0x24"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xa6, 0xfe ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x2b4"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x19, 0xfe ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x3ce"
+  -
+    input:
+      bytes: [ 0xee, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz d15, #0x10"
+  -
+    input:
+      bytes: [ 0x3c, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x12"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xbc, 0xfd ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x488"
+  -
+    input:
+      bytes: [ 0x6e, 0x20 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d15, #0x40"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x22, 0xfe ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x3bc"
+  -
+    input:
+      bytes: [ 0xff, 0x8f, 0x1a, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jge.u d15, #0x8, #0x34"
+  -
+    input:
+      bytes: [ 0x3c, 0x1b ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x36"
+  -
+    input:
+      bytes: [ 0x6e, 0x29 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d15, #0x52"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xcb, 0xfd ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x46a"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x1e, 0xfd ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x5c4"
+  -
+    input:
+      bytes: [ 0xfc, 0x6e ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "loop a6, #-0x4"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x5c, 0xfd ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x548"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x2e, 0xfd ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x5a4"
+  -
+    input:
+      bytes: [ 0x5e, 0x1b ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, #0x1, #0x16"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x06, 0xfe ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x3f4"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xfe, 0xfd ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x404"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xf2, 0xfd ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x41c"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xea, 0xfd ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x42c"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xde, 0xfd ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x444"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xd6, 0xfd ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x454"
+  -
+    input:
+      bytes: [ 0x5f, 0x9f, 0x23, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d9, #0x46"
+  -
+    input:
+      bytes: [ 0xdf, 0x1f, 0x5d, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, #0x1, #0xba"
+  -
+    input:
+      bytes: [ 0x6e, 0x2d ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d15, #0x5a"
+  -
+    input:
+      bytes: [ 0xfe, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, d0, #0x28"
+  -
+    input:
+      bytes: [ 0x3c, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0xe"
+  -
+    input:
+      bytes: [ 0xbe, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d0, #0x2a"
+  -
+    input:
+      bytes: [ 0x3c, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x4"
+  -
+    input:
+      bytes: [ 0xdf, 0x1f, 0x57, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, #0x1, #0xae"
+  -
+    input:
+      bytes: [ 0x7e, 0x93 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, d9, #0x6"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x7a, 0xfb ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x90c"
+  -
+    input:
+      bytes: [ 0x3c, 0x36 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x6c"
+  -
+    input:
+      bytes: [ 0x7f, 0x0f, 0x07, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jge.u d15, d0, #0xe"
+  -
+    input:
+      bytes: [ 0xbf, 0x21, 0xcb, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt.u d1, #0x2, #-0x6a"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x18, 0xfb ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x9d0"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x85, 0xfa ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0xaf6"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xd6, 0xf8 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0xe54"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x9c, 0xfa ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0xac8"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x00, 0xfc ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x800"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xc6, 0xfb ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x874"
+  -
+    input:
+      bytes: [ 0xf6, 0x23 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz d2, #0x6"
+  -
+    input:
+      bytes: [ 0x3c, 0x63 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0xc6"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xa9, 0xfb ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x8ae"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x45, 0xfb ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x976"
+  -
+    input:
+      bytes: [ 0x3c, 0x34 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x68"
+  -
+    input:
+      bytes: [ 0xbf, 0x21, 0xcd, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt.u d1, #0x2, #-0x66"
+  -
+    input:
+      bytes: [ 0xde, 0x1e ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, #0x1, #0x3c"
+  -
+    input:
+      bytes: [ 0x3c, 0x17 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x2e"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xde, 0xfa ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0xa44"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x89, 0xfa ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0xaee"
+  -
+    input:
+      bytes: [ 0xbf, 0x89, 0xea, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt.u d9, #0x8, #-0x2c"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xe8, 0xfb ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x830"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xee, 0xfa ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0xa24"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x73, 0xf5 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x151a"
+  -
+    input:
+      bytes: [ 0xee, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz d15, #0xc"
+  -
+    input:
+      bytes: [ 0x3c, 0x11 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x22"
+  -
+    input:
+      bytes: [ 0x5e, 0x19 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, #0x1, #0x12"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xde, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x44"
+  -
+    input:
+      bytes: [ 0x5e, 0x1a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, #0x1, #0x14"
+  -
+    input:
+      bytes: [ 0x3c, 0x29 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x52"
+  -
+    input:
+      bytes: [ 0x5e, 0x1e ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, #0x1, #0x1c"
+  -
+    input:
+      bytes: [ 0x3e, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d0, #0x8"
+  -
+    input:
+      bytes: [ 0x3e, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d0, #0x10"
+  -
+    input:
+      bytes: [ 0x3c, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x14"
+  -
+    input:
+      bytes: [ 0x3c, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0xc"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xb2, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x9c"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xe8, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x30"
+  -
+    input:
+      bytes: [ 0x3e, 0x0c ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d0, #0x18"
+  -
+    input:
+      bytes: [ 0xbe, 0x0c ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d0, #0x38"
+  -
+    input:
+      bytes: [ 0xbe, 0x0f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d0, #0x3e"
+  -
+    input:
+      bytes: [ 0x5f, 0x0f, 0x22, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d0, #0x44"
+  -
+    input:
+      bytes: [ 0x5f, 0x0f, 0x24, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d0, #0x48"
+  -
+    input:
+      bytes: [ 0x3c, 0x27 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x4e"
+  -
+    input:
+      bytes: [ 0xee, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz d15, #0x6"
+  -
+    input:
+      bytes: [ 0x3c, 0x12 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x24"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x43, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x886"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x54, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x8a8"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x91, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x522"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x4a, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x894"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xa4, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x548"
+  -
+    input:
+      bytes: [ 0xee, 0xfa ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz d15, #-0xc"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xc4, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x388"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x29, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x852"
+  -
+    input:
+      bytes: [ 0xdf, 0x08, 0x92, 0x81 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d8, #0, #0x324"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x5a, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x4b4"
+  -
+    input:
+      bytes: [ 0x6e, 0xfa ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d15, #-0xc"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xbb, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x376"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x8c, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x318"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xf1, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x5e2"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xe8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x1d0"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xab, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x556"
+  -
+    input:
+      bytes: [ 0x3c, 0x37 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x6e"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x03, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x206"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xb3, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x566"
+  -
+    input:
+      bytes: [ 0x6e, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d15, #0x12"
+  -
+    input:
+      bytes: [ 0x2d, 0x02, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "calli a2"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x91, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x122"
+  -
+    input:
+      bytes: [ 0x3f, 0xfc, 0xc9, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt.u d12, d15, #-0x6e"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xca, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x194"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x87, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x50e"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x92, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x124"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x47, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x48e"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x1f, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x43e"
+  -
+    input:
+      bytes: [ 0xf6, 0x83 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz d8, #0x6"
+  -
+    input:
+      bytes: [ 0x6f, 0x1f, 0xf8, 0x7f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.t d15, #0x1, #-0x10"
+  -
+    input:
+      bytes: [ 0x6f, 0x0f, 0xf2, 0x7f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.t d15, #0, #-0x1c"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x34, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x68"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xea, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x3d4"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x21, 0xfd ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x5be"
+  -
+    input:
+      bytes: [ 0x3f, 0xf0, 0xfd, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt.u d0, d15, #-0x6"
+  -
+    input:
+      bytes: [ 0x2e, 0x1b ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.t d15, #0x1, #0x16"
+  -
+    input:
+      bytes: [ 0xdf, 0x1f, 0xfe, 0x7f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, #0x1, #-0x4"
+  -
+    input:
+      bytes: [ 0x6f, 0x1f, 0x12, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.t d15, #0x1, #0x24"
+  -
+    input:
+      bytes: [ 0xdf, 0x1f, 0xfb, 0x7f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, #0x1, #-0xa"
+  -
+    input:
+      bytes: [ 0x6f, 0x0f, 0xff, 0x7f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.t d15, #0, #-0x2"
+  -
+    input:
+      bytes: [ 0x6f, 0x0f, 0xfc, 0x7f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.t d15, #0, #-0x8"
+  -
+    input:
+      bytes: [ 0xdc, 0x0f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ji a15"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x2f, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x5e"
+  -
+    input:
+      bytes: [ 0x3e, 0x28 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d2, #0x10"
+  -
+    input:
+      bytes: [ 0x5e, 0x13 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, #0x1, #0x6"
+  -
+    input:
+      bytes: [ 0xee, 0x13 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz d15, #0x26"
+  -
+    input:
+      bytes: [ 0x5e, 0x32 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, #0x3, #0x4"
+  -
+    input:
+      bytes: [ 0x7d, 0x4f, 0x0d, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne.a a15, a4, #0x1a"
+  -
+    input:
+      bytes: [ 0x3c, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x8"
+  -
+    input:
+      bytes: [ 0xbf, 0x30, 0xea, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt.u d0, #0x3, #-0x2c"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xe0, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x40"
+  -
+    input:
+      bytes: [ 0x1e, 0x32 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, #0x3, #0x4"
+  -
+    input:
+      bytes: [ 0x5e, 0x43 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, #0x4, #0x6"
+  -
+    input:
+      bytes: [ 0x5e, 0x23 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, #0x2, #0x6"
+  -
+    input:
+      bytes: [ 0xdf, 0x19, 0x49, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d9, #0x1, #0x92"
+  -
+    input:
+      bytes: [ 0x5f, 0x8f, 0x28, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d8, #0x50"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xa5, 0x0b ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x174a"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x0a, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x1414"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xc0, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x80"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xc3, 0x0b ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x1786"
+  -
+    input:
+      bytes: [ 0x3c, 0x1c ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x38"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x6b, 0x0b ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x16d6"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xbc, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x1378"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x72, 0x0b ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x16e4"
+  -
+    input:
+      bytes: [ 0xff, 0x3f, 0x0b, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jge.u d15, #0x3, #0x16"
+  -
+    input:
+      bytes: [ 0x7d, 0xf4, 0x04, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne.a a4, a15, #0x8"
+  -
+    input:
+      bytes: [ 0x3c, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x20"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xd6, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x54"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x28, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x1b0"
+  -
+    input:
+      bytes: [ 0xf6, 0x26 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz d2, #0xc"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x71, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x11e"
+  -
+    input:
+      bytes: [ 0x7e, 0x0d ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, d0, #0x1a"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x5b, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0xcb6"
+  -
+    input:
+      bytes: [ 0x3f, 0x0f, 0x04, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt.u d15, d0, #0x8"
+  -
+    input:
+      bytes: [ 0xdf, 0x7f, 0xf6, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, #0x7, #-0x14"
+  -
+    input:
+      bytes: [ 0x76, 0x17 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d1, #0xe"
+  -
+    input:
+      bytes: [ 0x76, 0x13 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d1, #0x6"
+  -
+    input:
+      bytes: [ 0x3c, 0x1e ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x3c"
+  -
+    input:
+      bytes: [ 0xf6, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz d0, #0xc"
+  -
+    input:
+      bytes: [ 0x7e, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, d0, #0xa"
+  -
+    input:
+      bytes: [ 0x3f, 0x40, 0xe3, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt.u d0, d4, #-0x3a"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x65, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x12ca"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xf9, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0xff2"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x3a, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x1074"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xf2, 0xfc ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x61c"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x9a, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x1134"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xdc, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x11b8"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xf0, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x9e0"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x0d, 0xfe ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x3e6"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x04, 0xfe ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x3f8"
+  -
+    input:
+      bytes: [ 0x76, 0x27 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d2, #0xe"
+  -
+    input:
+      bytes: [ 0x76, 0x23 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d2, #0x6"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x71, 0x12 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x24e2"
+  -
+    input:
+      bytes: [ 0xfc, 0x5e ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "loop a5, #-0x4"
+  -
+    input:
+      bytes: [ 0xfc, 0x29 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "loop a2, #-0xe"
+  -
+    input:
+      bytes: [ 0x6f, 0x0f, 0xfe, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz.t d15, #0, #-0x4"
+  -
+    input:
+      bytes: [ 0x6f, 0x1f, 0xfa, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz.t d15, #0x1, #-0xc"
+  -
+    input:
+      bytes: [ 0x1d, 0x00, 0x03, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x6"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x02, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x204"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xe1, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x1c2"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x0d, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x1a"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x72, 0x12 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x24e4"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xea, 0x11 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x23d4"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xfa, 0x11 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x23f4"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xf3, 0x0f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x1fe6"
+  -
+    input:
+      bytes: [ 0x3c, 0x50 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0xa0"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xc6, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x218c"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x41, 0x0f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x1e82"
+  -
+    input:
+      bytes: [ 0xbf, 0x48, 0xb1, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt.u d8, #0x4, #-0x9e"
+  -
+    input:
+      bytes: [ 0x6f, 0x70, 0xec, 0x7f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.t d0, #0x7, #-0x28"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x50, 0x0c ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x18a0"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xf9, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x15f2"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x5f, 0x0c ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x18be"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x38, 0x0b ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x1670"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x44, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x88"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x27, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x24e"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xb7, 0xfe ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x292"
+  -
+    input:
+      bytes: [ 0x3c, 0x14 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x28"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xbd, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x86"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xb9, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x8e"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xb4, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x98"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xaf, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0xa2"
+  -
+    input:
+      bytes: [ 0x3c, 0xed ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #-0x26"
+  -
+    input:
+      bytes: [ 0xfc, 0xf6 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "loop a15, #-0x14"
+  -
+    input:
+      bytes: [ 0xfd, 0xf0, 0xed, 0x7f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "loop a15, #-0x26"
+  -
+    input:
+      bytes: [ 0xdf, 0x1f, 0x23, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, #0x1, #0x46"
+  -
+    input:
+      bytes: [ 0x6e, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d15, #0x8"
+  -
+    input:
+      bytes: [ 0x76, 0xcf ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d12, #0x1e"
+  -
+    input:
+      bytes: [ 0xfc, 0x4e ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "loop a4, #-0x4"
+  -
+    input:
+      bytes: [ 0xdf, 0x0c, 0xe0, 0x7f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d12, #0, #-0x40"
+  -
+    input:
+      bytes: [ 0xfc, 0x2e ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "loop a2, #-0x4"
+  -
+    input:
+      bytes: [ 0x3c, 0xd9 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #-0x4e"
+  -
+    input:
+      bytes: [ 0xde, 0x25 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, #0x2, #0x2a"
+  -
+    input:
+      bytes: [ 0x2e, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.t d15, #0, #0x6"
+  -
+    input:
+      bytes: [ 0xdf, 0x0c, 0xd3, 0x7f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d12, #0, #-0x5a"
+  -
+    input:
+      bytes: [ 0x76, 0xc5 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d12, #0xa"
+  -
+    input:
+      bytes: [ 0xfc, 0x2f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "loop a2, #-0x2"
+  -
+    input:
+      bytes: [ 0x6e, 0xc9 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d15, #-0x6e"
+  -
+    input:
+      bytes: [ 0x3c, 0xc4 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #-0x78"
+  -
+    input:
+      bytes: [ 0xdf, 0x00, 0x2e, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d0, #0, #0x5c"
+  -
+    input:
+      bytes: [ 0xdf, 0x10, 0x2b, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d0, #0x1, #0x56"
+  -
+    input:
+      bytes: [ 0xfe, 0xdb ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, d13, #0x36"
+  -
+    input:
+      bytes: [ 0x76, 0xdb ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d13, #0x16"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x53, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0xa6"
+  -
+    input:
+      bytes: [ 0xdf, 0x0c, 0x9b, 0x7f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d12, #0, #-0xca"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x38, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x70"
+  -
+    input:
+      bytes: [ 0x3c, 0x94 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #-0xd8"
+  -
+    input:
+      bytes: [ 0xdf, 0x2f, 0x91, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, #0x2, #-0xde"
+  -
+    input:
+      bytes: [ 0x6e, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d15, #0xe"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x15, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x2a"
+  -
+    input:
+      bytes: [ 0xdf, 0x0c, 0x86, 0x7f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d12, #0, #-0xf4"
+  -
+    input:
+      bytes: [ 0xdf, 0x04, 0x7c, 0x7f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d4, #0, #-0x108"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x04, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x8"
+  -
+    input:
+      bytes: [ 0x1d, 0xff, 0x77, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #-0x112"
+  -
+    input:
+      bytes: [ 0x1d, 0x00, 0x02, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x4"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x15, 0x0c ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x182a"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xbe, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x157c"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x0e, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x1c"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xf1, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x1e2"
+  -
+    input:
+      bytes: [ 0x3c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x0"
diff --git a/tests/MC/TriCore/LoadStore.s.yaml b/tests/MC/TriCore/LoadStore.s.yaml
new file mode 100644
index 000000000..d3029e550
--- /dev/null
+++ b/tests/MC/TriCore/LoadStore.s.yaml
@@ -0,0 +1,2854 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x09, 0xff, 0x08, 0x29 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d15, [a15]#0x88"
+  -
+    input:
+      bytes: [ 0x89, 0xff, 0x08, 0x29 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w [a15]#0x88, d15"
+  -
+    input:
+      bytes: [ 0x09, 0xf0, 0x0c, 0x29 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d0, [a15]#0x8c"
+  -
+    input:
+      bytes: [ 0x89, 0xf0, 0x0c, 0x29 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w [a15]#0x8c, d0"
+  -
+    input:
+      bytes: [ 0x09, 0xff, 0x00, 0x29 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d15, [a15]#0x80"
+  -
+    input:
+      bytes: [ 0x89, 0xff, 0x00, 0x29 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w [a15]#0x80, d15"
+  -
+    input:
+      bytes: [ 0x09, 0xff, 0x40, 0x28 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d15, [a15]#0x80"
+  -
+    input:
+      bytes: [ 0x09, 0xff, 0x41, 0x28 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d15, [a15]#0x81"
+  -
+    input:
+      bytes: [ 0x54, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d15, [a15]"
+  -
+    input:
+      bytes: [ 0x4c, 0x41 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d15, [a4]#0x4"
+  -
+    input:
+      bytes: [ 0x6c, 0x41 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w [a4]#0x4, d15"
+  -
+    input:
+      bytes: [ 0x09, 0xff, 0x43, 0x28 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d15, [a15]#0x83"
+  -
+    input:
+      bytes: [ 0x89, 0xff, 0x03, 0x28 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [a15]#0x83, d15"
+  -
+    input:
+      bytes: [ 0x39, 0x2f, 0x43, 0x20 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d15, [a2]#0x483"
+  -
+    input:
+      bytes: [ 0xc8, 0x52 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.a a2, [a15]#0x14"
+  -
+    input:
+      bytes: [ 0xd4, 0x2d ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.a a13, [a2]"
+  -
+    input:
+      bytes: [ 0x09, 0x2e, 0x84, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.a a14, [a2]#0x4"
+  -
+    input:
+      bytes: [ 0x89, 0xc2, 0x84, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.a [a12]#0x4, a2"
+  -
+    input:
+      bytes: [ 0x09, 0xc2, 0x84, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.a a2, [a12]#0x4"
+  -
+    input:
+      bytes: [ 0x09, 0x29, 0x48, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d9, [a2]#0x8"
+  -
+    input:
+      bytes: [ 0x09, 0xfa, 0x0c, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.b d10, [a15]#0xc"
+  -
+    input:
+      bytes: [ 0x08, 0xe0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d0, [a15]#0xe"
+  -
+    input:
+      bytes: [ 0x09, 0x41, 0x41, 0x68 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d1, [a4]#0x181"
+  -
+    input:
+      bytes: [ 0x89, 0x20, 0x01, 0x68 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [a2]#0x181, d0"
+  -
+    input:
+      bytes: [ 0x08, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d0, [a15]#0xf"
+  -
+    input:
+      bytes: [ 0x09, 0x4f, 0x42, 0x68 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d15, [a4]#0x182"
+  -
+    input:
+      bytes: [ 0x89, 0x2f, 0x02, 0x68 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [a2]#0x182, d15"
+  -
+    input:
+      bytes: [ 0x09, 0xf0, 0x50, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d0, [a15]#0x10"
+  -
+    input:
+      bytes: [ 0x09, 0x4f, 0x40, 0x68 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d15, [a4]#0x180"
+  -
+    input:
+      bytes: [ 0x89, 0x2f, 0x00, 0x68 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [a2]#0x180, d15"
+  -
+    input:
+      bytes: [ 0x09, 0xf0, 0x51, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d0, [a15]#0x11"
+  -
+    input:
+      bytes: [ 0x08, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d0, [a15]#0x1"
+  -
+    input:
+      bytes: [ 0x09, 0x4f, 0x41, 0x68 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d15, [a4]#0x181"
+  -
+    input:
+      bytes: [ 0x89, 0x2f, 0x01, 0x68 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [a2]#0x181, d15"
+  -
+    input:
+      bytes: [ 0x08, 0xd0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d0, [a15]#0xd"
+  -
+    input:
+      bytes: [ 0x09, 0xf0, 0x53, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d0, [a15]#0x13"
+  -
+    input:
+      bytes: [ 0x08, 0x30 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d0, [a15]#0x3"
+  -
+    input:
+      bytes: [ 0x14, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d0, [a15]"
+  -
+    input:
+      bytes: [ 0x09, 0xf0, 0x52, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d0, [a15]#0x12"
+  -
+    input:
+      bytes: [ 0x08, 0x2f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d15, [a15]#0x2"
+  -
+    input:
+      bytes: [ 0x4c, 0xe2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d15, [a14]#0x8"
+  -
+    input:
+      bytes: [ 0x6c, 0xe2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w [a14]#0x8, d15"
+  -
+    input:
+      bytes: [ 0x08, 0xb0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d0, [a15]#0xb"
+  -
+    input:
+      bytes: [ 0x09, 0xc2, 0x00, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.b d2, [a12]#0"
+  -
+    input:
+      bytes: [ 0x09, 0xe1, 0x20, 0x49 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d1, [a14]#0x120"
+  -
+    input:
+      bytes: [ 0x89, 0xe1, 0x20, 0x49 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w [a14]#0x120, d1"
+  -
+    input:
+      bytes: [ 0x09, 0xef, 0x20, 0x49 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d15, [a14]#0x120"
+  -
+    input:
+      bytes: [ 0x89, 0xef, 0x20, 0x49 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w [a14]#0x120, d15"
+  -
+    input:
+      bytes: [ 0x09, 0xff, 0xc6, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.hu d15, [a15]#0x6"
+  -
+    input:
+      bytes: [ 0x08, 0xb5 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d5, [a15]#0xb"
+  -
+    input:
+      bytes: [ 0x09, 0xf0, 0x0c, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.b d0, [a15]#0xc"
+  -
+    input:
+      bytes: [ 0x89, 0xef, 0x10, 0x49 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w [a14]#0x110, d15"
+  -
+    input:
+      bytes: [ 0x08, 0x90 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d0, [a15]#0x9"
+  -
+    input:
+      bytes: [ 0x14, 0x21 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d1, [a2]"
+  -
+    input:
+      bytes: [ 0x34, 0x2f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [a2], d15"
+  -
+    input:
+      bytes: [ 0x0c, 0x21 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d15, [a2]#0x1"
+  -
+    input:
+      bytes: [ 0x2c, 0x21 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [a2]#0x1, d15"
+  -
+    input:
+      bytes: [ 0x0c, 0x23 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d15, [a2]#0x3"
+  -
+    input:
+      bytes: [ 0x2c, 0x23 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [a2]#0x3, d15"
+  -
+    input:
+      bytes: [ 0x08, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d15, [a15]#0xf"
+  -
+    input:
+      bytes: [ 0x08, 0xa0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d0, [a15]#0xa"
+  -
+    input:
+      bytes: [ 0x08, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d1, [a15]#0xf"
+  -
+    input:
+      bytes: [ 0x09, 0xe2, 0x30, 0x49 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d2, [a14]#0x130"
+  -
+    input:
+      bytes: [ 0x89, 0xe2, 0x30, 0x49 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w [a14]#0x130, d2"
+  -
+    input:
+      bytes: [ 0x09, 0xef, 0x30, 0x49 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d15, [a14]#0x130"
+  -
+    input:
+      bytes: [ 0x89, 0xef, 0x30, 0x49 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w [a14]#0x130, d15"
+  -
+    input:
+      bytes: [ 0x09, 0xe2, 0x34, 0x49 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d2, [a14]#0x134"
+  -
+    input:
+      bytes: [ 0x89, 0xe2, 0x34, 0x49 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w [a14]#0x134, d2"
+  -
+    input:
+      bytes: [ 0x09, 0xef, 0x34, 0x49 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d15, [a14]#0x134"
+  -
+    input:
+      bytes: [ 0x89, 0xef, 0x34, 0x49 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w [a14]#0x134, d15"
+  -
+    input:
+      bytes: [ 0x09, 0xff, 0xc4, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.hu d15, [a15]#0x4"
+  -
+    input:
+      bytes: [ 0x08, 0xa5 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d5, [a15]#0xa"
+  -
+    input:
+      bytes: [ 0x39, 0x5f, 0x03, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d15, [a5]#0x203"
+  -
+    input:
+      bytes: [ 0xe9, 0x4f, 0x03, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [a4]#0x203, d15"
+  -
+    input:
+      bytes: [ 0x89, 0xef, 0x14, 0x49 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w [a14]#0x114, d15"
+  -
+    input:
+      bytes: [ 0x08, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d0, [a15]#0x8"
+  -
+    input:
+      bytes: [ 0x2c, 0xc1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [a12]#0x1, d15"
+  -
+    input:
+      bytes: [ 0x09, 0xff, 0x0c, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.b d15, [a15]#0xc"
+  -
+    input:
+      bytes: [ 0x34, 0xcf ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [a12], d15"
+  -
+    input:
+      bytes: [ 0x44, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d15, [a15+]"
+  -
+    input:
+      bytes: [ 0x64, 0x2f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w [a2+], d15"
+  -
+    input:
+      bytes: [ 0x89, 0x45, 0x94, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.a [a4]#0x14, a5"
+  -
+    input:
+      bytes: [ 0xd4, 0xf2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.a a2, [a15]"
+  -
+    input:
+      bytes: [ 0xd4, 0x2c ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.a a12, [a2]"
+  -
+    input:
+      bytes: [ 0x08, 0x4f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d15, [a15]#0x4"
+  -
+    input:
+      bytes: [ 0x89, 0x4d, 0x84, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.a [a4]#0x4, a13"
+  -
+    input:
+      bytes: [ 0xd4, 0x22 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.a a2, [a2]"
+  -
+    input:
+      bytes: [ 0xf4, 0x42 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.a [a4], a2"
+  -
+    input:
+      bytes: [ 0x08, 0x49 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d9, [a15]#0x4"
+  -
+    input:
+      bytes: [ 0x89, 0x49, 0x08, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [a4]#0x8, d9"
+  -
+    input:
+      bytes: [ 0x09, 0xff, 0x6f, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d15, [a15]#0x2f"
+  -
+    input:
+      bytes: [ 0x09, 0xf5, 0x62, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d5, [a15]#0x22"
+  -
+    input:
+      bytes: [ 0x09, 0xf6, 0x63, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d6, [a15]#0x23"
+  -
+    input:
+      bytes: [ 0x09, 0xff, 0x70, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d15, [a15]#0x30"
+  -
+    input:
+      bytes: [ 0x09, 0xf5, 0x5a, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d5, [a15]#0x1a"
+  -
+    input:
+      bytes: [ 0x09, 0xf6, 0x5b, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d6, [a15]#0x1b"
+  -
+    input:
+      bytes: [ 0x09, 0xff, 0x71, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d15, [a15]#0x31"
+  -
+    input:
+      bytes: [ 0x09, 0xf5, 0x6a, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d5, [a15]#0x2a"
+  -
+    input:
+      bytes: [ 0x09, 0xf6, 0x6b, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d6, [a15]#0x2b"
+  -
+    input:
+      bytes: [ 0x08, 0x5f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d15, [a15]#0x5"
+  -
+    input:
+      bytes: [ 0x14, 0x20 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d0, [a2]"
+  -
+    input:
+      bytes: [ 0x09, 0xdf, 0x40, 0x18 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d15, [a13]#0x40"
+  -
+    input:
+      bytes: [ 0x89, 0xdf, 0x00, 0x18 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [a13]#0x40, d15"
+  -
+    input:
+      bytes: [ 0x09, 0xd1, 0x00, 0x19 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d1, [a13]#0x40"
+  -
+    input:
+      bytes: [ 0x89, 0xd1, 0x00, 0x19 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w [a13]#0x40, d1"
+  -
+    input:
+      bytes: [ 0x14, 0xd0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d0, [a13]"
+  -
+    input:
+      bytes: [ 0x34, 0xdf ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [a13], d15"
+  -
+    input:
+      bytes: [ 0x09, 0xff, 0x6e, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d15, [a15]#0x2e"
+  -
+    input:
+      bytes: [ 0x09, 0xff, 0x61, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d15, [a15]#0x21"
+  -
+    input:
+      bytes: [ 0x09, 0xdf, 0x44, 0x28 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d15, [a13]#0x84"
+  -
+    input:
+      bytes: [ 0x89, 0xdf, 0x04, 0x28 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [a13]#0x84, d15"
+  -
+    input:
+      bytes: [ 0x09, 0xf0, 0x5f, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d0, [a15]#0x1f"
+  -
+    input:
+      bytes: [ 0x09, 0xd1, 0x00, 0x29 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d1, [a13]#0x80"
+  -
+    input:
+      bytes: [ 0x89, 0xd1, 0x00, 0x29 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w [a13]#0x80, d1"
+  -
+    input:
+      bytes: [ 0x09, 0xff, 0x5e, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d15, [a15]#0x1e"
+  -
+    input:
+      bytes: [ 0x09, 0xf0, 0x60, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d0, [a15]#0x20"
+  -
+    input:
+      bytes: [ 0x14, 0x2f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d15, [a2]"
+  -
+    input:
+      bytes: [ 0x09, 0xd0, 0x45, 0x28 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d0, [a13]#0x85"
+  -
+    input:
+      bytes: [ 0x89, 0xdf, 0x05, 0x28 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [a13]#0x85, d15"
+  -
+    input:
+      bytes: [ 0x09, 0xff, 0x59, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d15, [a15]#0x19"
+  -
+    input:
+      bytes: [ 0x09, 0xdf, 0x64, 0x28 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d15, [a13]#0xa4"
+  -
+    input:
+      bytes: [ 0x89, 0xdf, 0x24, 0x28 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [a13]#0xa4, d15"
+  -
+    input:
+      bytes: [ 0x09, 0xf0, 0x57, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d0, [a15]#0x17"
+  -
+    input:
+      bytes: [ 0x09, 0xd1, 0x20, 0x29 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d1, [a13]#0xa0"
+  -
+    input:
+      bytes: [ 0x89, 0xd1, 0x20, 0x29 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w [a13]#0xa0, d1"
+  -
+    input:
+      bytes: [ 0x09, 0xff, 0x56, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d15, [a15]#0x16"
+  -
+    input:
+      bytes: [ 0x09, 0xf0, 0x58, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d0, [a15]#0x18"
+  -
+    input:
+      bytes: [ 0x09, 0xd0, 0x64, 0x28 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d0, [a13]#0xa4"
+  -
+    input:
+      bytes: [ 0x09, 0xff, 0x69, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d15, [a15]#0x29"
+  -
+    input:
+      bytes: [ 0x39, 0xcf, 0x04, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d15, [a12]#0x204"
+  -
+    input:
+      bytes: [ 0xe9, 0xcf, 0x04, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [a12]#0x204, d15"
+  -
+    input:
+      bytes: [ 0x09, 0xf0, 0x67, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d0, [a15]#0x27"
+  -
+    input:
+      bytes: [ 0x19, 0xc1, 0x00, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d1, [a12]#0x200"
+  -
+    input:
+      bytes: [ 0x59, 0xc1, 0x00, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w [a12]#0x200, d1"
+  -
+    input:
+      bytes: [ 0x09, 0xff, 0x66, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d15, [a15]#0x26"
+  -
+    input:
+      bytes: [ 0x09, 0xf0, 0x68, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d0, [a15]#0x28"
+  -
+    input:
+      bytes: [ 0x39, 0xc0, 0x04, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d0, [a12]#0x204"
+  -
+    input:
+      bytes: [ 0x09, 0xf5, 0x6c, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d5, [a15]#0x2c"
+  -
+    input:
+      bytes: [ 0x09, 0x20, 0x4a, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d0, [a2]#0xa"
+  -
+    input:
+      bytes: [ 0x09, 0x4f, 0x61, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d15, [a4]#0x21"
+  -
+    input:
+      bytes: [ 0x89, 0x2f, 0x21, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [a2]#0x21, d15"
+  -
+    input:
+      bytes: [ 0x09, 0x2f, 0x06, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d15, [a2]#0x6"
+  -
+    input:
+      bytes: [ 0x09, 0x4f, 0x60, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d15, [a4]#0x20"
+  -
+    input:
+      bytes: [ 0x89, 0x2f, 0x20, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [a2]#0x20, d15"
+  -
+    input:
+      bytes: [ 0x2c, 0x44 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [a4]#0x4, d15"
+  -
+    input:
+      bytes: [ 0xf4, 0x45 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.a [a4], a5"
+  -
+    input:
+      bytes: [ 0x0c, 0x44 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d15, [a4]#0x4"
+  -
+    input:
+      bytes: [ 0x2c, 0x45 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [a4]#0x5, d15"
+  -
+    input:
+      bytes: [ 0x89, 0x4f, 0x2c, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [a4]#0x2c, d15"
+  -
+    input:
+      bytes: [ 0xd4, 0xcd ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.a a13, [a12]"
+  -
+    input:
+      bytes: [ 0xf4, 0x4d ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.a [a4], a13"
+  -
+    input:
+      bytes: [ 0x74, 0xd0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w [a13], d0"
+  -
+    input:
+      bytes: [ 0x09, 0xc4, 0x5d, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d4, [a12]#0x1d"
+  -
+    input:
+      bytes: [ 0x4c, 0xc5 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d15, [a12]#0x14"
+  -
+    input:
+      bytes: [ 0x4c, 0xc4 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d15, [a12]#0x10"
+  -
+    input:
+      bytes: [ 0x09, 0xff, 0x61, 0x28 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d15, [a15]#0xa1"
+  -
+    input:
+      bytes: [ 0x89, 0x2f, 0x21, 0x28 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [a2]#0xa1, d15"
+  -
+    input:
+      bytes: [ 0x48, 0x1f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d15, [a15]#0x4"
+  -
+    input:
+      bytes: [ 0x09, 0x2f, 0x60, 0x28 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d15, [a2]#0xa0"
+  -
+    input:
+      bytes: [ 0x89, 0xff, 0x20, 0x28 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [a15]#0xa0, d15"
+  -
+    input:
+      bytes: [ 0x09, 0xcf, 0x5c, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d15, [a12]#0x1c"
+  -
+    input:
+      bytes: [ 0x34, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [a15], d15"
+  -
+    input:
+      bytes: [ 0xf4, 0xf5 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.a [a15], a5"
+  -
+    input:
+      bytes: [ 0x6c, 0xf5 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w [a15]#0x14, d15"
+  -
+    input:
+      bytes: [ 0x68, 0x42 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w [a15]#0x10, d2"
+  -
+    input:
+      bytes: [ 0x68, 0x62 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w [a15]#0x18, d2"
+  -
+    input:
+      bytes: [ 0x2c, 0xf8 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [a15]#0x8, d15"
+  -
+    input:
+      bytes: [ 0x6c, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w [a15]#0x4, d15"
+  -
+    input:
+      bytes: [ 0x2c, 0xfe ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [a15]#0xe, d15"
+  -
+    input:
+      bytes: [ 0x89, 0xff, 0x0a, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w [a15]#0xa, d15"
+  -
+    input:
+      bytes: [ 0x89, 0xff, 0x1c, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [a15]#0x1c, d15"
+  -
+    input:
+      bytes: [ 0x89, 0xff, 0x1d, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [a15]#0x1d, d15"
+  -
+    input:
+      bytes: [ 0x39, 0xff, 0x37, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d15, [a15]#0x6037"
+  -
+    input:
+      bytes: [ 0x09, 0xff, 0x54, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d15, [a15]#0x14"
+  -
+    input:
+      bytes: [ 0x09, 0xff, 0x5c, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d15, [a15]#0x1c"
+  -
+    input:
+      bytes: [ 0x09, 0xff, 0x5b, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d15, [a15]#0x1b"
+  -
+    input:
+      bytes: [ 0x39, 0xff, 0x33, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d15, [a15]#0x6033"
+  -
+    input:
+      bytes: [ 0x39, 0xff, 0x31, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d15, [a15]#0x6031"
+  -
+    input:
+      bytes: [ 0x39, 0xff, 0x32, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d15, [a15]#0x6032"
+  -
+    input:
+      bytes: [ 0x09, 0xff, 0x10, 0x19 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d15, [a15]#0x50"
+  -
+    input:
+      bytes: [ 0x74, 0x2f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w [a2], d15"
+  -
+    input:
+      bytes: [ 0x39, 0x2f, 0x30, 0x46 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d15, [a2]#0x6130"
+  -
+    input:
+      bytes: [ 0xe9, 0x2f, 0x30, 0x46 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [a2]#0x6130, d15"
+  -
+    input:
+      bytes: [ 0x39, 0x2f, 0x33, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d15, [a2]#0x6033"
+  -
+    input:
+      bytes: [ 0xe9, 0x2f, 0x33, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [a2]#0x6033, d15"
+  -
+    input:
+      bytes: [ 0x39, 0x2f, 0x18, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d15, [a2]#0x6018"
+  -
+    input:
+      bytes: [ 0xe9, 0x2f, 0x18, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [a2]#0x6018, d15"
+  -
+    input:
+      bytes: [ 0x39, 0x2f, 0x37, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d15, [a2]#0x6037"
+  -
+    input:
+      bytes: [ 0xe9, 0x2f, 0x37, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [a2]#0x6037, d15"
+  -
+    input:
+      bytes: [ 0x39, 0x2f, 0x14, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d15, [a2]#0x6014"
+  -
+    input:
+      bytes: [ 0x39, 0x20, 0x1c, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d0, [a2]#0x601c"
+  -
+    input:
+      bytes: [ 0x08, 0xaf ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d15, [a15]#0xa"
+  -
+    input:
+      bytes: [ 0xe9, 0x2f, 0x1c, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [a2]#0x601c, d15"
+  -
+    input:
+      bytes: [ 0x39, 0x20, 0x1b, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d0, [a2]#0x601b"
+  -
+    input:
+      bytes: [ 0x08, 0x8f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d15, [a15]#0x8"
+  -
+    input:
+      bytes: [ 0xe9, 0x2f, 0x1b, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [a2]#0x601b, d15"
+  -
+    input:
+      bytes: [ 0x39, 0x20, 0x19, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d0, [a2]#0x6019"
+  -
+    input:
+      bytes: [ 0x08, 0x9f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d15, [a15]#0x9"
+  -
+    input:
+      bytes: [ 0xe9, 0x2f, 0x19, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [a2]#0x6019, d15"
+  -
+    input:
+      bytes: [ 0x39, 0x2f, 0x1a, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d15, [a2]#0x601a"
+  -
+    input:
+      bytes: [ 0xe9, 0x2f, 0x1a, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [a2]#0x601a, d15"
+  -
+    input:
+      bytes: [ 0x48, 0x34 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d4, [a15]#0xc"
+  -
+    input:
+      bytes: [ 0x19, 0x20, 0x30, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d0, [a2]#0x6030"
+  -
+    input:
+      bytes: [ 0x48, 0x5f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d15, [a15]#0x14"
+  -
+    input:
+      bytes: [ 0x48, 0x41 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d1, [a15]#0x10"
+  -
+    input:
+      bytes: [ 0x74, 0x20 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w [a2], d0"
+  -
+    input:
+      bytes: [ 0x19, 0x20, 0x34, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d0, [a2]#0x6034"
+  -
+    input:
+      bytes: [ 0x48, 0x7f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d15, [a15]#0x1c"
+  -
+    input:
+      bytes: [ 0x48, 0x61 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d1, [a15]#0x18"
+  -
+    input:
+      bytes: [ 0x39, 0x2f, 0x03, 0x16 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d15, [a2]#0x6043"
+  -
+    input:
+      bytes: [ 0x19, 0x20, 0x00, 0x16 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d0, [a2]#0x6040"
+  -
+    input:
+      bytes: [ 0x48, 0x9f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d15, [a15]#0x24"
+  -
+    input:
+      bytes: [ 0x48, 0x81 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d1, [a15]#0x20"
+  -
+    input:
+      bytes: [ 0x39, 0x2f, 0x0f, 0x16 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d15, [a2]#0x604f"
+  -
+    input:
+      bytes: [ 0x19, 0x20, 0x0c, 0x16 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d0, [a2]#0x604c"
+  -
+    input:
+      bytes: [ 0x48, 0xbf ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d15, [a15]#0x2c"
+  -
+    input:
+      bytes: [ 0x48, 0xa1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d1, [a15]#0x28"
+  -
+    input:
+      bytes: [ 0x19, 0x20, 0x00, 0x26 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d0, [a2]#0x6080"
+  -
+    input:
+      bytes: [ 0x48, 0xdf ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d15, [a15]#0x34"
+  -
+    input:
+      bytes: [ 0x48, 0xc1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d1, [a15]#0x30"
+  -
+    input:
+      bytes: [ 0x19, 0x20, 0x04, 0x26 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d0, [a2]#0x6084"
+  -
+    input:
+      bytes: [ 0x48, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d15, [a15]#0x3c"
+  -
+    input:
+      bytes: [ 0x48, 0xe1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d1, [a15]#0x38"
+  -
+    input:
+      bytes: [ 0x19, 0x2f, 0x08, 0x26 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d15, [a2]#0x6088"
+  -
+    input:
+      bytes: [ 0x09, 0xf0, 0x04, 0x19 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d0, [a15]#0x44"
+  -
+    input:
+      bytes: [ 0x09, 0xf1, 0x00, 0x19 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d1, [a15]#0x40"
+  -
+    input:
+      bytes: [ 0x19, 0x2f, 0x14, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d15, [a2]#0x2014"
+  -
+    input:
+      bytes: [ 0x09, 0xf0, 0x0c, 0x19 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d0, [a15]#0x4c"
+  -
+    input:
+      bytes: [ 0x09, 0xf1, 0x08, 0x19 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d1, [a15]#0x48"
+  -
+    input:
+      bytes: [ 0xc8, 0x12 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.a a2, [a15]#0x4"
+  -
+    input:
+      bytes: [ 0x4c, 0x22 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d15, [a2]#0x8"
+  -
+    input:
+      bytes: [ 0x09, 0x22, 0x88, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.a a2, [a2]#0x8"
+  -
+    input:
+      bytes: [ 0x09, 0x24, 0x02, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d4, [a2]#0x2"
+  -
+    input:
+      bytes: [ 0x14, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d15, [a15]"
+  -
+    input:
+      bytes: [ 0x39, 0xff, 0x18, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d15, [a15]#0x6018"
+  -
+    input:
+      bytes: [ 0xe9, 0xff, 0x18, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [a15]#0x6018, d15"
+  -
+    input:
+      bytes: [ 0x39, 0xff, 0x2c, 0x46 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d15, [a15]#0x612c"
+  -
+    input:
+      bytes: [ 0xe9, 0xff, 0x2c, 0x46 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [a15]#0x612c, d15"
+  -
+    input:
+      bytes: [ 0x39, 0xff, 0x30, 0x46 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d15, [a15]#0x6130"
+  -
+    input:
+      bytes: [ 0xe9, 0xff, 0x30, 0x46 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [a15]#0x6130, d15"
+  -
+    input:
+      bytes: [ 0x39, 0xf0, 0x10, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d0, [a15]#0x6010"
+  -
+    input:
+      bytes: [ 0xe9, 0xf0, 0x10, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [a15]#0x6010, d0"
+  -
+    input:
+      bytes: [ 0x39, 0xf0, 0x12, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d0, [a15]#0x6012"
+  -
+    input:
+      bytes: [ 0x54, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d1, [a15]"
+  -
+    input:
+      bytes: [ 0xe9, 0xff, 0x12, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [a15]#0x6012, d15"
+  -
+    input:
+      bytes: [ 0x39, 0xff, 0x10, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d15, [a15]#0x6010"
+  -
+    input:
+      bytes: [ 0xe9, 0xff, 0x10, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [a15]#0x6010, d15"
+  -
+    input:
+      bytes: [ 0x39, 0xff, 0x11, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d15, [a15]#0x6011"
+  -
+    input:
+      bytes: [ 0x39, 0xff, 0x35, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d15, [a15]#0x6035"
+  -
+    input:
+      bytes: [ 0x85, 0xf1, 0x10, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d1, #0xf0000010"
+  -
+    input:
+      bytes: [ 0x85, 0xf0, 0x10, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d0, #0xf0000010"
+  -
+    input:
+      bytes: [ 0x54, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d0, [a15]"
+  -
+    input:
+      bytes: [ 0x74, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w [a15], d15"
+  -
+    input:
+      bytes: [ 0x19, 0xff, 0x30, 0x36 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d15, [a15]#0x60f0"
+  -
+    input:
+      bytes: [ 0x19, 0xf0, 0x30, 0x36 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d0, [a15]#0x60f0"
+  -
+    input:
+      bytes: [ 0x59, 0xff, 0x30, 0x36 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w [a15]#0x60f0, d15"
+  -
+    input:
+      bytes: [ 0x2c, 0xf4 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [a15]#0x4, d15"
+  -
+    input:
+      bytes: [ 0x39, 0xff, 0x34, 0x36 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d15, [a15]#0x60f4"
+  -
+    input:
+      bytes: [ 0xe9, 0xff, 0x34, 0x36 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [a15]#0x60f4, d15"
+  -
+    input:
+      bytes: [ 0x89, 0xa2, 0x40, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.d [sp]#0, e2"
+  -
+    input:
+      bytes: [ 0x09, 0xa0, 0x40, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.d e0, [sp]#0"
+  -
+    input:
+      bytes: [ 0x54, 0x31 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d1, [a3]"
+  -
+    input:
+      bytes: [ 0x08, 0x1f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d15, [a15]#0x1"
+  -
+    input:
+      bytes: [ 0xd4, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.a a15, [a15]"
+  -
+    input:
+      bytes: [ 0x54, 0x3f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d15, [a3]"
+  -
+    input:
+      bytes: [ 0x74, 0x3f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w [a3], d15"
+  -
+    input:
+      bytes: [ 0x39, 0x2f, 0x35, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d15, [a2]#0x6035"
+  -
+    input:
+      bytes: [ 0x85, 0xff, 0x10, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d15, #0xf0000010"
+  -
+    input:
+      bytes: [ 0x49, 0x40, 0x40, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldmst [a4]#0, e0"
+  -
+    input:
+      bytes: [ 0x74, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w [a15], d0"
+  -
+    input:
+      bytes: [ 0x74, 0x41 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w [a4], d1"
+  -
+    input:
+      bytes: [ 0x74, 0x4f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w [a4], d15"
+  -
+    input:
+      bytes: [ 0x15, 0xd0, 0xc0, 0xe3 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "stlcx #0xd0003f80"
+  -
+    input:
+      bytes: [ 0x15, 0xd0, 0xc0, 0xf7 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "stucx #0xd0003fc0"
+  -
+    input:
+      bytes: [ 0x85, 0xdf, 0xc4, 0xf3 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d15, #0xd0003fc4"
+  -
+    input:
+      bytes: [ 0x15, 0xd0, 0xc0, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lducx #0xd0003fc0"
+  -
+    input:
+      bytes: [ 0x15, 0xd0, 0xc0, 0xeb ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldlcx #0xd0003f80"
+  -
+    input:
+      bytes: [ 0x39, 0xff, 0x05, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d15, [a15]#0x205"
+  -
+    input:
+      bytes: [ 0xe9, 0xff, 0x05, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [a15]#0x205, d15"
+  -
+    input:
+      bytes: [ 0x2c, 0xa4 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [sp]#0x4, d15"
+  -
+    input:
+      bytes: [ 0x2c, 0xa5 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [sp]#0x5, d15"
+  -
+    input:
+      bytes: [ 0x89, 0xaf, 0x31, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [sp]#0x31, d15"
+  -
+    input:
+      bytes: [ 0x89, 0xaf, 0x24, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [sp]#0x24, d15"
+  -
+    input:
+      bytes: [ 0x89, 0xaf, 0x28, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [sp]#0x28, d15"
+  -
+    input:
+      bytes: [ 0x09, 0x2f, 0x00, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.b d15, [a2]#0"
+  -
+    input:
+      bytes: [ 0x2c, 0xfc ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [a15]#0xc, d15"
+  -
+    input:
+      bytes: [ 0x28, 0xf8 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [a15]#0xf, d8"
+  -
+    input:
+      bytes: [ 0x2c, 0xf2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [a15]#0x2, d15"
+  -
+    input:
+      bytes: [ 0x08, 0x81 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d1, [a15]#0x8"
+  -
+    input:
+      bytes: [ 0x09, 0xff, 0x00, 0x69 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d15, [a15]#0x180"
+  -
+    input:
+      bytes: [ 0x89, 0xf0, 0x00, 0x69 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w [a15]#0x180, d0"
+  -
+    input:
+      bytes: [ 0x09, 0x22, 0x84, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.a a2, [a2]#0x4"
+  -
+    input:
+      bytes: [ 0x19, 0xff, 0x00, 0xa0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d15, [a15]#0x280"
+  -
+    input:
+      bytes: [ 0xb4, 0xaf ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [sp], d15"
+  -
+    input:
+      bytes: [ 0xac, 0xa1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [sp]#0x2, d15"
+  -
+    input:
+      bytes: [ 0xac, 0xa2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [sp]#0x4, d15"
+  -
+    input:
+      bytes: [ 0xac, 0xa3 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [sp]#0x6, d15"
+  -
+    input:
+      bytes: [ 0xb4, 0xa2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [sp], d2"
+  -
+    input:
+      bytes: [ 0x89, 0xa2, 0x82, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [sp]#0x2, d2"
+  -
+    input:
+      bytes: [ 0x89, 0xa2, 0x84, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [sp]#0x4, d2"
+  -
+    input:
+      bytes: [ 0x89, 0xa2, 0x86, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [sp]#0x6, d2"
+  -
+    input:
+      bytes: [ 0x54, 0x2f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d15, [a2]"
+  -
+    input:
+      bytes: [ 0x09, 0x51, 0x01, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.b d1, [a5+]#0x1"
+  -
+    input:
+      bytes: [ 0x54, 0x22 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d2, [a2]"
+  -
+    input:
+      bytes: [ 0x74, 0x22 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w [a2], d2"
+  -
+    input:
+      bytes: [ 0xc8, 0x1c ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.a a12, [a15]#0x4"
+  -
+    input:
+      bytes: [ 0xc8, 0x2d ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.a a13, [a15]#0x8"
+  -
+    input:
+      bytes: [ 0x48, 0x3c ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d12, [a15]#0xc"
+  -
+    input:
+      bytes: [ 0x09, 0xff, 0x10, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d15, [a15+]#0x10"
+  -
+    input:
+      bytes: [ 0x04, 0xdf ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d15, [a13+]"
+  -
+    input:
+      bytes: [ 0x24, 0xcf ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [a12+], d15"
+  -
+    input:
+      bytes: [ 0x44, 0x21 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d1, [a2+]"
+  -
+    input:
+      bytes: [ 0x64, 0xc1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w [a12+], d1"
+  -
+    input:
+      bytes: [ 0x24, 0xc9 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [a12+], d9"
+  -
+    input:
+      bytes: [ 0x64, 0xca ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w [a12+], d10"
+  -
+    input:
+      bytes: [ 0x24, 0xcb ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [a12+], d11"
+  -
+    input:
+      bytes: [ 0x64, 0xc8 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w [a12+], d8"
diff --git a/tests/MC/TriCore/csfr.s.yaml b/tests/MC/TriCore/csfr.s.yaml
new file mode 100644
index 000000000..32536893f
--- /dev/null
+++ b/tests/MC/TriCore/csfr.s.yaml
@@ -0,0 +1,19 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xcd, 0x41, 0xe0, 0x0f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "mtcr #-0x1fc, d1"
+  -
+    input:
+      bytes: [ 0x4d, 0x40, 0xe0, 0x2f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "mfcr d2, #0xfe04"
diff --git a/tests/MC/TriCore/debug.s.yaml b/tests/MC/TriCore/debug.s.yaml
new file mode 100644
index 000000000..add2ee729
--- /dev/null
+++ b/tests/MC/TriCore/debug.s.yaml
@@ -0,0 +1,10 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmp.f d0, d0, d0"
diff --git a/tests/MC/TriCore/extr_u.s.yaml b/tests/MC/TriCore/extr_u.s.yaml
new file mode 100644
index 000000000..721c1728d
--- /dev/null
+++ b/tests/MC/TriCore/extr_u.s.yaml
@@ -0,0 +1,19 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x17, 0x01, 0x40, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr d0, d1, e2"
+  -
+    input:
+      bytes: [ 0x17, 0x01, 0x60, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d0, d1, e2"
diff --git a/tests/MC/TriCore/handwrite.s.yaml b/tests/MC/TriCore/handwrite.s.yaml
new file mode 100644
index 000000000..2faf1fc7f
--- /dev/null
+++ b/tests/MC/TriCore/handwrite.s.yaml
@@ -0,0 +1,10 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x8f, 0xff, 0x83, 0x81 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor d8, d15, #0x3f"
diff --git a/tests/MC/TriCore/iLLD_TC375_ADS_Bluetooth_RFCOMM.s.yaml b/tests/MC/TriCore/iLLD_TC375_ADS_Bluetooth_RFCOMM.s.yaml
new file mode 100644
index 000000000..0453ebb8a
--- /dev/null
+++ b/tests/MC/TriCore/iLLD_TC375_ADS_Bluetooth_RFCOMM.s.yaml
@@ -0,0 +1,23563 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x7e, 0xaa ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, d10, #0x14"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x75, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x116"
+  -
+    input:
+      bytes: [ 0xa2, 0x8f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub d15, d8"
+  -
+    input:
+      bytes: [ 0x1d, 0x00, 0x8c, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x318"
+  -
+    input:
+      bytes: [ 0xc2, 0x34 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d4, #0x3"
+  -
+    input:
+      bytes: [ 0x0b, 0x15, 0x90, 0xf2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.lt d15, d5, d1"
+  -
+    input:
+      bytes: [ 0x0b, 0xa8, 0x10, 0x48 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov e4, d8, d10"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x83, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0xfa"
+  -
+    input:
+      bytes: [ 0x6f, 0x9a, 0x0e, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.t d10, #0x9, #0x1c"
+  -
+    input:
+      bytes: [ 0xbb, 0xf0, 0xfe, 0x0f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.u d0, #0xffef"
+  -
+    input:
+      bytes: [ 0xd9, 0x44, 0xa8, 0x9a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a4, [a4]#-0x5598"
+  -
+    input:
+      bytes: [ 0x8c, 0xa6 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.h d15, [sp]#0xc"
+  -
+    input:
+      bytes: [ 0x6b, 0x0c, 0x31, 0xf5 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub.f d15, d5, d12"
+  -
+    input:
+      bytes: [ 0xce, 0x57 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jgez d5, #0xe"
+  -
+    input:
+      bytes: [ 0x91, 0x40, 0x00, 0x2f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a2, #0xf004"
+  -
+    input:
+      bytes: [ 0x61, 0xff, 0x3a, 0xda ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcall #-0x4b8c"
+  -
+    input:
+      bytes: [ 0x02, 0xa4 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d4, d10"
+  -
+    input:
+      bytes: [ 0x3f, 0xf0, 0xfd, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt.u d0, d15, #-0x6"
+  -
+    input:
+      bytes: [ 0x0b, 0x0f, 0x90, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "min.u d15, d15, d0"
+  -
+    input:
+      bytes: [ 0x6f, 0x0a, 0x0e, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz.t d10, #0, #0x1c"
+  -
+    input:
+      bytes: [ 0x89, 0x4f, 0xa4, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [a4]#0x24, d15"
+  -
+    input:
+      bytes: [ 0x37, 0x04, 0x50, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr d0, d4, #0, #0x10"
+  -
+    input:
+      bytes: [ 0x3c, 0x23 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x46"
+  -
+    input:
+      bytes: [ 0x40, 0xde ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.aa a14, a13"
+  -
+    input:
+      bytes: [ 0x9b, 0x14, 0x00, 0x40 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addih d4, d4, #0x1"
+  -
+    input:
+      bytes: [ 0x6f, 0x08, 0x18, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz.t d8, #0, #0x30"
+  -
+    input:
+      bytes: [ 0x37, 0x0f, 0x70, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d0, d15, #0, #0x10"
+  -
+    input:
+      bytes: [ 0xfe, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, d0, #0x26"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xe1, 0xfa ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0xa3e"
+  -
+    input:
+      bytes: [ 0x3b, 0x50, 0x04, 0x20 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d2, #0x45"
+  -
+    input:
+      bytes: [ 0x1a, 0x89 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d15, d9, d8"
+  -
+    input:
+      bytes: [ 0x8f, 0x24, 0x40, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or d15, d4, #0x2"
+  -
+    input:
+      bytes: [ 0xee, 0x0e ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz d15, #0x1c"
+  -
+    input:
+      bytes: [ 0x2e, 0x37 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.t d15, #0x3, #0xe"
+  -
+    input:
+      bytes: [ 0x6e, 0x1d ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d15, #0x3a"
+  -
+    input:
+      bytes: [ 0xae, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz.t d15, #0, #0x8"
+  -
+    input:
+      bytes: [ 0x2e, 0x1c ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.t d15, #0x1, #0x18"
+  -
+    input:
+      bytes: [ 0x40, 0xa4 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.aa a4, sp"
+  -
+    input:
+      bytes: [ 0x4b, 0xbf, 0x01, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmp.f d15, d15, d11"
+  -
+    input:
+      bytes: [ 0x02, 0x1f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d15, d1"
+  -
+    input:
+      bytes: [ 0x0b, 0x1b, 0x80, 0xf2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.ne d15, d11, d1"
+  -
+    input:
+      bytes: [ 0xd9, 0x99, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a9, [a9]#0"
+  -
+    input:
+      bytes: [ 0x3c, 0x94 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #-0xd8"
+  -
+    input:
+      bytes: [ 0x0b, 0xab, 0x10, 0x48 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov e4, d11, d10"
+  -
+    input:
+      bytes: [ 0xfe, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, d0, #0x2c"
+  -
+    input:
+      bytes: [ 0x3c, 0x18 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x30"
+  -
+    input:
+      bytes: [ 0x02, 0x94 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d4, d9"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x53, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x15a"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x09, 0x4c ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x167ee"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x5b, 0xfa ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0xb4a"
+  -
+    input:
+      bytes: [ 0xae, 0x17 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz.t d15, #0x1, #0xe"
+  -
+    input:
+      bytes: [ 0x3c, 0x19 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x32"
+  -
+    input:
+      bytes: [ 0x3c, 0x0c ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x18"
+  -
+    input:
+      bytes: [ 0x37, 0x00, 0x50, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr d8, d0, #0, #0x10"
+  -
+    input:
+      bytes: [ 0xac, 0x42 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [a4]#0x4, d15"
+  -
+    input:
+      bytes: [ 0xa2, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub d0, d15"
+  -
+    input:
+      bytes: [ 0xd9, 0x55, 0xa0, 0xca ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a5, [a5]#-0x54e0"
+  -
+    input:
+      bytes: [ 0xdf, 0x02, 0xee, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d2, #0, #-0x24"
+  -
+    input:
+      bytes: [ 0x49, 0xa2, 0x00, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a2, [sp]#0"
+  -
+    input:
+      bytes: [ 0x67, 0x23, 0x80, 0x3f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ins.t d3, d3, #0, d2, #0x1f"
+  -
+    input:
+      bytes: [ 0x82, 0x15 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d5, #0x1"
+  -
+    input:
+      bytes: [ 0x3b, 0x90, 0xd0, 0x33 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d3, #0x3d09"
+  -
+    input:
+      bytes: [ 0x8f, 0x00, 0x01, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh d0, d0, #0x10"
+  -
+    input:
+      bytes: [ 0x7d, 0xe2, 0x0a, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne.a a2, a14, #0x14"
+  -
+    input:
+      bytes: [ 0x3b, 0x00, 0x04, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d0, #0x1040"
+  -
+    input:
+      bytes: [ 0xee, 0x2b ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz d15, #0x56"
+  -
+    input:
+      bytes: [ 0x0b, 0x27, 0x00, 0xf2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.eq d15, d7, d2"
+  -
+    input:
+      bytes: [ 0x8c, 0x49 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.h d15, [a4]#0x12"
+  -
+    input:
+      bytes: [ 0xbb, 0x00, 0x68, 0x89 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.u d8, #0x9680"
+  -
+    input:
+      bytes: [ 0x5f, 0x0f, 0xad, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d0, #0x15a"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x2a, 0x3e ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x183ac"
+  -
+    input:
+      bytes: [ 0x49, 0xf4, 0x04, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a4, [a15]#0x4"
+  -
+    input:
+      bytes: [ 0x0e, 0xa4 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jltz d10, #0x8"
+  -
+    input:
+      bytes: [ 0x88, 0x20 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.h d0, [a15]#0x4"
+  -
+    input:
+      bytes: [ 0x1d, 0x00, 0xbc, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x178"
+  -
+    input:
+      bytes: [ 0x8f, 0x0a, 0x44, 0xa1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or d10, d10, #0x40"
+  -
+    input:
+      bytes: [ 0x7e, 0x0d ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, d0, #0x1a"
+  -
+    input:
+      bytes: [ 0xa0, 0xa4 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.a a4, #0xa"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x67, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x132"
+  -
+    input:
+      bytes: [ 0x9a, 0xfb ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d15, d11, #-0x1"
+  -
+    input:
+      bytes: [ 0x02, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d2, d0"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x06, 0xf6 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x13f4"
+  -
+    input:
+      bytes: [ 0x0b, 0xd1, 0xd0, 0xd0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "subc d13, d1, d13"
+  -
+    input:
+      bytes: [ 0x8b, 0x05, 0xa0, 0x50 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addc d5, d5, #0"
+  -
+    input:
+      bytes: [ 0x49, 0xff, 0x20, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0x20"
+  -
+    input:
+      bytes: [ 0x8f, 0xbf, 0x0f, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d0, d15, #0xfb"
+  -
+    input:
+      bytes: [ 0xae, 0x28 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz.t d15, #0x2, #0x10"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x1d, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0xa3a"
+  -
+    input:
+      bytes: [ 0x49, 0xa6, 0x04, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a6, [sp]#0x4"
+  -
+    input:
+      bytes: [ 0x8b, 0xf0, 0x20, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "min.u d0, d0, #0xf"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x85, 0xfd ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x4f6"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x55, 0xfe ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x356"
+  -
+    input:
+      bytes: [ 0x02, 0xab ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d11, d10"
+  -
+    input:
+      bytes: [ 0x8b, 0x0f, 0x01, 0xf2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "eq d15, d15, #0x10"
+  -
+    input:
+      bytes: [ 0x5e, 0x2b ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, #0x2, #0x16"
+  -
+    input:
+      bytes: [ 0x89, 0xff, 0xb6, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [a15]#0x36, d15"
+  -
+    input:
+      bytes: [ 0xb7, 0x1a, 0x81, 0xa5 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d10, d10, #0x1, #0xb, #0x1"
+  -
+    input:
+      bytes: [ 0x53, 0xcf, 0x20, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul d15, d15, #0xc"
+  -
+    input:
+      bytes: [ 0x6b, 0x0c, 0x31, 0xa5 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub.f d10, d5, d12"
+  -
+    input:
+      bytes: [ 0x8b, 0x01, 0x03, 0x40 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d4, d1, #0x30"
+  -
+    input:
+      bytes: [ 0x4b, 0xf1, 0x41, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.f d1, d1, d15"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x03, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x6"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x07, 0x14 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x280e"
+  -
+    input:
+      bytes: [ 0xab, 0x0f, 0x83, 0x41 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sel d4, d1, d15, #0x30"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x1a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x34"
+  -
+    input:
+      bytes: [ 0x3f, 0xf0, 0xf6, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt.u d0, d15, #-0x14"
+  -
+    input:
+      bytes: [ 0xde, 0x25 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, #0x2, #0x2a"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0x0c, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0x4c"
+  -
+    input:
+      bytes: [ 0xb0, 0xc4 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add.a a4, #-0x4"
+  -
+    input:
+      bytes: [ 0x82, 0x20 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d0, #0x2"
+  -
+    input:
+      bytes: [ 0xda, 0x39 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d15, #0x39"
+  -
+    input:
+      bytes: [ 0xab, 0x1f, 0x20, 0xa0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "caddn d10, d0, d15, #0x1"
+  -
+    input:
+      bytes: [ 0x10, 0x25 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addsc.a a5, a2, d15, #0"
+  -
+    input:
+      bytes: [ 0x89, 0x4f, 0xae, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [a4]#0x2e, d15"
+  -
+    input:
+      bytes: [ 0x09, 0xd4, 0xb4, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.h d4, [a13]#0x34"
+  -
+    input:
+      bytes: [ 0xd9, 0x55, 0x9c, 0xea ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a5, [a5]#-0x5464"
+  -
+    input:
+      bytes: [ 0x01, 0xf9, 0x00, 0x26 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addsc.a a2, a15, d9, #0"
+  -
+    input:
+      bytes: [ 0x82, 0x44 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d4, #0x4"
+  -
+    input:
+      bytes: [ 0xd9, 0xee, 0xaa, 0x60 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a14, [a14]#0x9aa"
+  -
+    input:
+      bytes: [ 0x5e, 0x17 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, #0x1, #0xe"
+  -
+    input:
+      bytes: [ 0x49, 0xcf, 0x04, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a12]#0x4"
+  -
+    input:
+      bytes: [ 0xdf, 0x0c, 0x1d, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d12, #0, #0x3a"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xbc, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x178"
+  -
+    input:
+      bytes: [ 0xdf, 0x04, 0x7c, 0x7f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d4, #0, #-0x108"
+  -
+    input:
+      bytes: [ 0x09, 0xf0, 0xd8, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.hu d0, [a15]#0x18"
+  -
+    input:
+      bytes: [ 0x87, 0x55, 0xbf, 0xdf ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.t d13, d5, #0x1f, d5, #0x1f"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x0f, 0xfb ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x9e2"
+  -
+    input:
+      bytes: [ 0x8f, 0x89, 0x01, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d15, d9, #0x18"
+  -
+    input:
+      bytes: [ 0x6f, 0x0f, 0xfc, 0x7f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.t d15, #0, #-0x8"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xd0, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x11a0"
+  -
+    input:
+      bytes: [ 0x49, 0xa6, 0x00, 0x4a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a6, [sp]#0x100"
+  -
+    input:
+      bytes: [ 0x4b, 0x0f, 0x41, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.f d15, d15, d0"
+  -
+    input:
+      bytes: [ 0x3c, 0x38 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x70"
+  -
+    input:
+      bytes: [ 0xd9, 0x55, 0x48, 0x4a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a5, [a5]#-0x5af8"
+  -
+    input:
+      bytes: [ 0xc5, 0xf5, 0x80, 0x40 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a5, #0xf0000900"
+  -
+    input:
+      bytes: [ 0xd9, 0x55, 0x64, 0x8a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a5, [a5]#-0x59dc"
+  -
+    input:
+      bytes: [ 0x82, 0x12 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d2, #0x1"
+  -
+    input:
+      bytes: [ 0xb7, 0x08, 0x01, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d8, #0, #0, #0x1"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0x80, 0xc5 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0x5b00"
+  -
+    input:
+      bytes: [ 0x3b, 0x20, 0xfe, 0x0f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d0, #-0x1e"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x9b, 0x11 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x2336"
+  -
+    input:
+      bytes: [ 0xb7, 0x04, 0x02, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d0, d4, #0, #0, #0x2"
+  -
+    input:
+      bytes: [ 0x0b, 0x60, 0x40, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addx d8, d0, d6"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x6c, 0xf5 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x1528"
+  -
+    input:
+      bytes: [ 0x40, 0xcd ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.aa a13, a12"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x4a, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x294"
+  -
+    input:
+      bytes: [ 0x89, 0xaf, 0xa0, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [sp]#0x20, d15"
+  -
+    input:
+      bytes: [ 0x49, 0x25, 0x01, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a5, [a2]#0x1"
+  -
+    input:
+      bytes: [ 0xbf, 0x10, 0x22, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt d0, #0x1, #0x44"
+  -
+    input:
+      bytes: [ 0x1e, 0xf8 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, #-0x1, #0x10"
+  -
+    input:
+      bytes: [ 0x89, 0x4f, 0xa2, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [a4]#0x22, d15"
+  -
+    input:
+      bytes: [ 0x96, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or d15, #0x2"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xf2, 0x38 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x18e1c"
+  -
+    input:
+      bytes: [ 0x5f, 0x0f, 0x23, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, d0, #0x46"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x01, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "eq d0, d0, #0x10"
+  -
+    input:
+      bytes: [ 0x6e, 0x36 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d15, #0x6c"
+  -
+    input:
+      bytes: [ 0x7b, 0x00, 0x00, 0x11 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh d1, #0x1000"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x9b, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x536"
+  -
+    input:
+      bytes: [ 0xdf, 0x10, 0x2b, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d0, #0x1, #0x56"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xfd, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x5fa"
+  -
+    input:
+      bytes: [ 0x8b, 0x16, 0x80, 0x60 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addx d6, d6, #0x1"
+  -
+    input:
+      bytes: [ 0x4b, 0xf1, 0x51, 0x20 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "div.f d2, d1, d15"
+  -
+    input:
+      bytes: [ 0x40, 0x42 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.aa a2, a4"
+  -
+    input:
+      bytes: [ 0x6e, 0xf3 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d15, #-0x1a"
+  -
+    input:
+      bytes: [ 0xda, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d15, #0xa"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x1a, 0xfe ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x3cc"
+  -
+    input:
+      bytes: [ 0x5e, 0x15 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, #0x1, #0xa"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x1f, 0x11 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x223e"
+  -
+    input:
+      bytes: [ 0xd9, 0x3f, 0x10, 0x18 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a3]#-0x7fb0"
+  -
+    input:
+      bytes: [ 0x49, 0xf2, 0x3f, 0x2a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a2, [a15]#0xbf"
+  -
+    input:
+      bytes: [ 0xbf, 0x1f, 0x13, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt d15, #0x1, #0x26"
+  -
+    input:
+      bytes: [ 0x82, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d5, #0"
+  -
+    input:
+      bytes: [ 0x89, 0xa2, 0x80, 0x48 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [sp]#0x100, d2"
+  -
+    input:
+      bytes: [ 0x9b, 0x88, 0xb9, 0x84 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addih d8, d8, #0x4b98"
+  -
+    input:
+      bytes: [ 0x09, 0x40, 0xc6, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.hu d0, [a4]#0x6"
+  -
+    input:
+      bytes: [ 0x82, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d4, #0"
+  -
+    input:
+      bytes: [ 0x20, 0x20 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub.a sp, #0x20"
+  -
+    input:
+      bytes: [ 0xc2, 0x1f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d15, #0x1"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x22, 0x0f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x1e44"
+  -
+    input:
+      bytes: [ 0xee, 0xc4 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz d15, #-0x78"
+  -
+    input:
+      bytes: [ 0x0b, 0x89, 0x10, 0x68 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov e6, d9, d8"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0x50, 0xca ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#-0x58f0"
+  -
+    input:
+      bytes: [ 0x5f, 0x5f, 0xfd, 0x7f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d5, #-0x6"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x1d, 0xf6 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x13c6"
+  -
+    input:
+      bytes: [ 0x49, 0xa6, 0x08, 0x4a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a6, [sp]#0x108"
+  -
+    input:
+      bytes: [ 0x92, 0x49 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d9, d15, #0x4"
+  -
+    input:
+      bytes: [ 0x94, 0xd4 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.h d4, [a13]"
+  -
+    input:
+      bytes: [ 0x8f, 0x89, 0x01, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d0, d9, #0x18"
+  -
+    input:
+      bytes: [ 0x0b, 0xf4, 0x80, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "min d15, d4, d15"
+  -
+    input:
+      bytes: [ 0xbf, 0x10, 0xfa, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt.u d0, #0x1, #-0xc"
+  -
+    input:
+      bytes: [ 0xfe, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, d0, #0x24"
+  -
+    input:
+      bytes: [ 0xa6, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or d1, d15"
+  -
+    input:
+      bytes: [ 0x49, 0xff, 0x10, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0x10"
+  -
+    input:
+      bytes: [ 0x91, 0x10, 0x00, 0xa5 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a sp, #0x5001"
+  -
+    input:
+      bytes: [ 0xd9, 0x55, 0x64, 0x5a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a5, [a5]#-0x5a9c"
+  -
+    input:
+      bytes: [ 0xbb, 0x00, 0xc2, 0x2b ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.u d2, #0xbc20"
+  -
+    input:
+      bytes: [ 0x6f, 0x3f, 0x30, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.t d15, #0x3, #0x60"
+  -
+    input:
+      bytes: [ 0x16, 0x1f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d15, #0x1f"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0xa4, 0xda ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#-0x549c"
+  -
+    input:
+      bytes: [ 0x8f, 0x3c, 0x00, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d0, d12, #0x3"
+  -
+    input:
+      bytes: [ 0x8b, 0x0f, 0x20, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ne d0, d15, #0"
+  -
+    input:
+      bytes: [ 0x1e, 0x17 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, #0x1, #0xe"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0x28, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0x28"
+  -
+    input:
+      bytes: [ 0x3f, 0x89, 0xd6, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt.u d9, d8, #-0x54"
+  -
+    input:
+      bytes: [ 0x76, 0x43 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d4, #0x6"
+  -
+    input:
+      bytes: [ 0x3f, 0xfa, 0xf9, 0x7f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt d10, d15, #-0xe"
+  -
+    input:
+      bytes: [ 0x82, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d15, #-0x1"
+  -
+    input:
+      bytes: [ 0x0b, 0x51, 0x50, 0x30 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addc d3, d1, d5"
+  -
+    input:
+      bytes: [ 0x94, 0xd0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.h d0, [a13]"
+  -
+    input:
+      bytes: [ 0x82, 0x18 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d8, #0x1"
+  -
+    input:
+      bytes: [ 0x8b, 0x6f, 0x1c, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d15, d15, #-0x3a"
+  -
+    input:
+      bytes: [ 0x12, 0x50 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d0, d15, d5"
+  -
+    input:
+      bytes: [ 0xb7, 0x0f, 0x81, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, #0, #0x3, #0x1"
+  -
+    input:
+      bytes: [ 0x67, 0xff, 0xbf, 0xaf ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insn.t d10, d15, #0x1f, d15, #0x1f"
+  -
+    input:
+      bytes: [ 0x53, 0x44, 0x20, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul d15, d4, #0x4"
+  -
+    input:
+      bytes: [ 0xd9, 0x22, 0x80, 0x0c ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a2, [a2]#-0x3800"
+  -
+    input:
+      bytes: [ 0x0b, 0xa0, 0x50, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ge.u d15, d0, d10"
+  -
+    input:
+      bytes: [ 0xc2, 0x2f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d15, #0x2"
+  -
+    input:
+      bytes: [ 0x7f, 0x1f, 0x04, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jge.u d15, d1, #0x8"
+  -
+    input:
+      bytes: [ 0x40, 0x4d ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.aa a13, a4"
+  -
+    input:
+      bytes: [ 0xce, 0x84 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jgez d8, #0x8"
+  -
+    input:
+      bytes: [ 0x3f, 0x89, 0xb8, 0x7e ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt d9, d8, #-0x290"
+  -
+    input:
+      bytes: [ 0x26, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d10, d0"
+  -
+    input:
+      bytes: [ 0xd9, 0x44, 0x24, 0xc0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a4, [a4]#0x324"
+  -
+    input:
+      bytes: [ 0x3f, 0x10, 0x97, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt.u d0, d1, #-0xd2"
+  -
+    input:
+      bytes: [ 0x5e, 0x1a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, #0x1, #0x14"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x22, 0xf5 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x15bc"
+  -
+    input:
+      bytes: [ 0xdf, 0x0f, 0xdf, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, #0, #0x1be"
+  -
+    input:
+      bytes: [ 0x1d, 0x00, 0x9e, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x13c"
+  -
+    input:
+      bytes: [ 0x02, 0xd8 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d8, d13"
+  -
+    input:
+      bytes: [ 0x0b, 0x23, 0x10, 0xa8 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov e10, d3, d2"
+  -
+    input:
+      bytes: [ 0xee, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz d15, #0x12"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x7a, 0xf7 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x110c"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0x00, 0x0e ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#-0x2000"
+  -
+    input:
+      bytes: [ 0xb7, 0x1a, 0x01, 0xa6 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d10, d10, #0x1, #0xc, #0x1"
+  -
+    input:
+      bytes: [ 0x1d, 0xff, 0xb5, 0xfd ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #-0x496"
+  -
+    input:
+      bytes: [ 0x49, 0xc2, 0x0c, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a2, [a12]#0xc"
+  -
+    input:
+      bytes: [ 0x49, 0xa2, 0x13, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a2, [sp]#0x13"
+  -
+    input:
+      bytes: [ 0x2e, 0x25 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.t d15, #0x2, #0xa"
+  -
+    input:
+      bytes: [ 0x61, 0xff, 0xe0, 0xd9 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcall #-0x4c40"
+  -
+    input:
+      bytes: [ 0x01, 0xc8, 0x00, 0xe6 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addsc.a a14, a12, d8, #0"
+  -
+    input:
+      bytes: [ 0x49, 0x40, 0x40, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldmst [a4]#0, e0"
+  -
+    input:
+      bytes: [ 0x0f, 0x0f, 0xb0, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "clz d15, d15"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x5f, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x14be"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0xc0, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#-0x6400"
+  -
+    input:
+      bytes: [ 0xf6, 0xa6 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz d10, #0xc"
+  -
+    input:
+      bytes: [ 0x40, 0x2e ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.aa a14, a2"
+  -
+    input:
+      bytes: [ 0xda, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d15, #0x80"
+  -
+    input:
+      bytes: [ 0x4b, 0x01, 0x71, 0x11 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ftouz d1, d1"
+  -
+    input:
+      bytes: [ 0xdf, 0x02, 0x12, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d2, #0, #0x24"
+  -
+    input:
+      bytes: [ 0x4b, 0x0a, 0x01, 0x82 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "div e8, d10, d0"
+  -
+    input:
+      bytes: [ 0x3b, 0xc0, 0x04, 0x50 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d5, #0x4c"
+  -
+    input:
+      bytes: [ 0x02, 0xf5 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d5, d15"
+  -
+    input:
+      bytes: [ 0x3c, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x6"
+  -
+    input:
+      bytes: [ 0xd9, 0x55, 0x74, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a5, [a5]#-0x5bcc"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xdd, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x5ba"
+  -
+    input:
+      bytes: [ 0x8b, 0xfe, 0x26, 0x82 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ne d8, d14, #0x6f"
+  -
+    input:
+      bytes: [ 0x8f, 0x3f, 0x00, 0xd1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d13, d15, #0x3"
+  -
+    input:
+      bytes: [ 0x10, 0xcc ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addsc.a a12, a12, d15, #0"
+  -
+    input:
+      bytes: [ 0x3b, 0x90, 0x06, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d0, #0x69"
+  -
+    input:
+      bytes: [ 0x3b, 0x60, 0x04, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d1, #0x46"
+  -
+    input:
+      bytes: [ 0x3c, 0x26 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x4c"
+  -
+    input:
+      bytes: [ 0x3b, 0xe0, 0x02, 0x40 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d4, #0x2e"
+  -
+    input:
+      bytes: [ 0x3e, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d0, #0x6"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x37, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x6e"
+  -
+    input:
+      bytes: [ 0x8b, 0x10, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addx d0, d0, #0x1"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x48, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x90"
+  -
+    input:
+      bytes: [ 0x40, 0x6c ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.aa a12, a6"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x36, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x6c"
+  -
+    input:
+      bytes: [ 0x49, 0x55, 0x00, 0x2a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a5, [a5]#0x80"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x6c, 0xf4 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x1728"
+  -
+    input:
+      bytes: [ 0x0b, 0x71, 0x00, 0xf2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.eq d15, d1, d7"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x16, 0xfe ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x3d4"
+  -
+    input:
+      bytes: [ 0x37, 0x0f, 0x04, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, d0, #0, #0x4"
+  -
+    input:
+      bytes: [ 0x01, 0xc0, 0x00, 0xf6 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addsc.a a15, a12, d0, #0"
+  -
+    input:
+      bytes: [ 0x49, 0xa2, 0x0a, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a2, [sp]#0xa"
+  -
+    input:
+      bytes: [ 0x0b, 0x54, 0x10, 0x88 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov e8, d4, d5"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x5e, 0x11 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x22bc"
+  -
+    input:
+      bytes: [ 0x4b, 0x0f, 0x51, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "div.f d15, d15, d0"
+  -
+    input:
+      bytes: [ 0x5f, 0x0f, 0xc4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d0, #0x188"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x34, 0x11 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x2268"
+  -
+    input:
+      bytes: [ 0x3b, 0xc0, 0x04, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d0, #0x4c"
+  -
+    input:
+      bytes: [ 0x6e, 0xef ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d15, #-0x22"
+  -
+    input:
+      bytes: [ 0x01, 0xf0, 0x00, 0x26 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addsc.a a2, a15, d0, #0"
+  -
+    input:
+      bytes: [ 0x49, 0xa5, 0x08, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a5, [sp]#0x8"
+  -
+    input:
+      bytes: [ 0x49, 0xaf, 0x12, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [sp]#0x12"
+  -
+    input:
+      bytes: [ 0x7f, 0xfa, 0x1d, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jge d10, d15, #0x3a"
+  -
+    input:
+      bytes: [ 0xbb, 0xf0, 0xfd, 0xaf ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.u d10, #0xffdf"
+  -
+    input:
+      bytes: [ 0x5f, 0x0f, 0x27, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, d0, #0x4e"
+  -
+    input:
+      bytes: [ 0x40, 0x5d ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.aa a13, a5"
+  -
+    input:
+      bytes: [ 0xdf, 0x12, 0x49, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d2, #0x1, #0x92"
+  -
+    input:
+      bytes: [ 0xbf, 0x10, 0x13, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt.u d0, #0x1, #0x26"
+  -
+    input:
+      bytes: [ 0x49, 0xff, 0x04, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0x4"
+  -
+    input:
+      bytes: [ 0x5f, 0x01, 0x04, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d1, d0, #0x8"
+  -
+    input:
+      bytes: [ 0x8b, 0x61, 0x09, 0x11 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "rsub d1, d1, #0x96"
+  -
+    input:
+      bytes: [ 0xdf, 0x04, 0x11, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d4, #0, #0x22"
+  -
+    input:
+      bytes: [ 0xb0, 0x15 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add.a a5, #0x1"
+  -
+    input:
+      bytes: [ 0xd9, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a0, [a0]#0"
+  -
+    input:
+      bytes: [ 0x01, 0xf2, 0x20, 0xf4 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lt.a d15, a2, a15"
+  -
+    input:
+      bytes: [ 0x6f, 0x08, 0xe2, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz.t d8, #0, #-0x3c"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0x04, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0x4"
+  -
+    input:
+      bytes: [ 0x37, 0x0f, 0x81, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, d0, #0x1, #0x1"
+  -
+    input:
+      bytes: [ 0x82, 0x40 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d0, #0x4"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x8f, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x11e"
+  -
+    input:
+      bytes: [ 0x3b, 0xa0, 0x00, 0x60 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d6, #0xa"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x3b, 0x18 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x3076"
+  -
+    input:
+      bytes: [ 0x3e, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d0, #0xc"
+  -
+    input:
+      bytes: [ 0x40, 0xf5 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.aa a5, a15"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x9e, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0xf3c"
+  -
+    input:
+      bytes: [ 0x3b, 0x90, 0x00, 0xb0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d11, #0x9"
+  -
+    input:
+      bytes: [ 0x91, 0x00, 0x00, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a15, #0"
+  -
+    input:
+      bytes: [ 0x6f, 0x29, 0x09, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.t d9, #0x2, #0x12"
+  -
+    input:
+      bytes: [ 0x16, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d15, #0x3"
+  -
+    input:
+      bytes: [ 0x8b, 0x01, 0x01, 0x11 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "rsub d1, d1, #0x10"
+  -
+    input:
+      bytes: [ 0x76, 0x33 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d3, #0x6"
+  -
+    input:
+      bytes: [ 0x3b, 0x50, 0x06, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d1, #0x65"
+  -
+    input:
+      bytes: [ 0xbe, 0xe4 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d14, #0x28"
+  -
+    input:
+      bytes: [ 0xff, 0x14, 0xea, 0x7f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jge d4, #0x1, #-0x2c"
+  -
+    input:
+      bytes: [ 0xf6, 0x82 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz d8, #0x4"
+  -
+    input:
+      bytes: [ 0x02, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d4, d0"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x8a, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x514"
+  -
+    input:
+      bytes: [ 0x3e, 0x0d ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d0, #0x1a"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x85, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x50a"
+  -
+    input:
+      bytes: [ 0xc2, 0xcb ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d11, #-0x4"
+  -
+    input:
+      bytes: [ 0x3f, 0xbc, 0xf9, 0x7f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt d12, d11, #-0xe"
+  -
+    input:
+      bytes: [ 0x1d, 0xff, 0x77, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #-0x112"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x7c, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x6f8"
+  -
+    input:
+      bytes: [ 0x23, 0x82, 0x0a, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub d0, d10, d2, d8"
+  -
+    input:
+      bytes: [ 0x8b, 0x02, 0x00, 0x22 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "eq d2, d2, #0"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x7a, 0x11 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x22f4"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xd4, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x58"
+  -
+    input:
+      bytes: [ 0x49, 0xf4, 0x08, 0x5a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a4, [a15]#0x148"
+  -
+    input:
+      bytes: [ 0xdf, 0x09, 0x14, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d9, #0, #0x28"
+  -
+    input:
+      bytes: [ 0x4b, 0x0d, 0x61, 0xa1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "utof d10, d13"
+  -
+    input:
+      bytes: [ 0xff, 0xdf, 0x6f, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jge d15, #-0x3, #0xde"
+  -
+    input:
+      bytes: [ 0x8b, 0x02, 0x03, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d15, d2, #0x30"
+  -
+    input:
+      bytes: [ 0x49, 0xff, 0x08, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0x8"
+  -
+    input:
+      bytes: [ 0x6f, 0x9a, 0x05, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.t d10, #0x9, #0xa"
+  -
+    input:
+      bytes: [ 0x3c, 0x0f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x1e"
+  -
+    input:
+      bytes: [ 0x37, 0xf0, 0x01, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d0, d15, #0x2, #0x1"
+  -
+    input:
+      bytes: [ 0x26, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d2, d0"
+  -
+    input:
+      bytes: [ 0x3f, 0xbf, 0x03, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt d15, d11, #0x6"
+  -
+    input:
+      bytes: [ 0x26, 0xa0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d0, d10"
+  -
+    input:
+      bytes: [ 0x9b, 0xc0, 0xfc, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addih d0, d0, #0x3fcc"
+  -
+    input:
+      bytes: [ 0x5f, 0x0f, 0x37, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, d0, #0x6e"
+  -
+    input:
+      bytes: [ 0xf6, 0x23 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz d2, #0x6"
+  -
+    input:
+      bytes: [ 0xdf, 0x05, 0x12, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d5, #0, #0x24"
+  -
+    input:
+      bytes: [ 0x8f, 0x29, 0x00, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d15, d9, #0x2"
+  -
+    input:
+      bytes: [ 0x8f, 0x24, 0x20, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha d15, d4, #0x2"
+  -
+    input:
+      bytes: [ 0xd2, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov e0, #0"
+  -
+    input:
+      bytes: [ 0x0f, 0x0a, 0x00, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh d15, d10, d0"
+  -
+    input:
+      bytes: [ 0x02, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d1, d15"
+  -
+    input:
+      bytes: [ 0x89, 0x45, 0x96, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [a4]#0x16, d5"
+  -
+    input:
+      bytes: [ 0xd9, 0x22, 0x28, 0xa6 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a2, [a2]#0x62a8"
+  -
+    input:
+      bytes: [ 0x61, 0xff, 0xcd, 0xd4 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcall #-0x5666"
+  -
+    input:
+      bytes: [ 0x02, 0x6a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d10, d6"
+  -
+    input:
+      bytes: [ 0x52, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub d0, d15, d0"
+  -
+    input:
+      bytes: [ 0x49, 0x4f, 0x08, 0x1a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a4]#0x48"
+  -
+    input:
+      bytes: [ 0xbf, 0x1f, 0x5c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt d15, #0x1, #0xb8"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xd0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "abss d0, d0"
+  -
+    input:
+      bytes: [ 0x3c, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x8"
+  -
+    input:
+      bytes: [ 0x7e, 0x12 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, d1, #0x4"
+  -
+    input:
+      bytes: [ 0xa6, 0x12 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or d2, d1"
+  -
+    input:
+      bytes: [ 0x49, 0xfd, 0x08, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a13, [a15]#0x8"
+  -
+    input:
+      bytes: [ 0x37, 0xf0, 0x01, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d0, d15, #0, #0x1"
+  -
+    input:
+      bytes: [ 0xee, 0x11 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz d15, #0x22"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x96, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x12c"
+  -
+    input:
+      bytes: [ 0x37, 0x0f, 0x62, 0xf6 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d15, d15, #0xc, #0x2"
+  -
+    input:
+      bytes: [ 0x7d, 0x24, 0x04, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq.a a4, a2, #0x8"
+  -
+    input:
+      bytes: [ 0x3b, 0x50, 0x07, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d0, #0x75"
+  -
+    input:
+      bytes: [ 0xda, 0x5b ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d15, #0x5b"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0xa0, 0xea ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#-0x5460"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x2a, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x1ac"
+  -
+    input:
+      bytes: [ 0x5f, 0x0f, 0x38, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d0, #0x70"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x05, 0xfa ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0xbf6"
+  -
+    input:
+      bytes: [ 0x80, 0xf2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.d d2, a15"
+  -
+    input:
+      bytes: [ 0x82, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d7, #0"
+  -
+    input:
+      bytes: [ 0x37, 0x00, 0x62, 0xfe ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d15, d0, #0x1c, #0x2"
+  -
+    input:
+      bytes: [ 0xee, 0x0c ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz d15, #0x18"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x71, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x14e2"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x02, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d15, d0, #0x20"
+  -
+    input:
+      bytes: [ 0x02, 0x40 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d0, d4"
+  -
+    input:
+      bytes: [ 0x8c, 0x4a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.h d15, [a4]#0x14"
+  -
+    input:
+      bytes: [ 0x0f, 0x49, 0x10, 0x90 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha d9, d9, d4"
+  -
+    input:
+      bytes: [ 0x37, 0x04, 0x48, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr d0, d4, #0, #0x8"
+  -
+    input:
+      bytes: [ 0x1d, 0x00, 0x17, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x22e"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x6f, 0xfe ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x322"
+  -
+    input:
+      bytes: [ 0x91, 0x40, 0x88, 0x4f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a4, #0xf884"
+  -
+    input:
+      bytes: [ 0x3b, 0x00, 0x10, 0x40 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d4, #0x100"
+  -
+    input:
+      bytes: [ 0xd9, 0x55, 0x5c, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a5, [a5]#-0x5be4"
+  -
+    input:
+      bytes: [ 0x60, 0x14 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.a a4, d1"
+  -
+    input:
+      bytes: [ 0x46, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "not d3"
+  -
+    input:
+      bytes: [ 0x8b, 0x0f, 0x20, 0xf2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ne d15, d15, #0"
+  -
+    input:
+      bytes: [ 0x37, 0xf0, 0x03, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d0, d15, #0, #0x3"
+  -
+    input:
+      bytes: [ 0x8b, 0x1a, 0x60, 0xf3 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "max.u d15, d10, #0x1"
+  -
+    input:
+      bytes: [ 0x8f, 0x0a, 0x02, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d15, d10, #0x20"
+  -
+    input:
+      bytes: [ 0x2e, 0x1b ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.t d15, #0x1, #0x16"
+  -
+    input:
+      bytes: [ 0x8f, 0x00, 0x21, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha d0, d0, #0x10"
+  -
+    input:
+      bytes: [ 0xbb, 0x00, 0x68, 0xf9 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.u d15, #0x9680"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0x00, 0x40 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0x100"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x11, 0x11 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x2222"
+  -
+    input:
+      bytes: [ 0xf6, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz d0, #0x4"
+  -
+    input:
+      bytes: [ 0x6f, 0x09, 0x15, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz.t d9, #0, #0x2a"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x06, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0xa0c"
+  -
+    input:
+      bytes: [ 0x82, 0x24 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d4, #0x2"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xda, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x7b4"
+  -
+    input:
+      bytes: [ 0x02, 0xf3 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d3, d15"
+  -
+    input:
+      bytes: [ 0x16, 0xfb ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d15, #0xfb"
+  -
+    input:
+      bytes: [ 0x1d, 0x00, 0x03, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x6"
+  -
+    input:
+      bytes: [ 0x91, 0x20, 0x00, 0xf8 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a15, #0x8002"
+  -
+    input:
+      bytes: [ 0xb7, 0x04, 0x08, 0xfc ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d4, #0, #0x18, #0x8"
+  -
+    input:
+      bytes: [ 0x7b, 0x80, 0x2c, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh d0, #0x42c8"
+  -
+    input:
+      bytes: [ 0x76, 0xf7 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d15, #0xe"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xa5, 0x21 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x434a"
+  -
+    input:
+      bytes: [ 0xd9, 0x44, 0x0c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a4, [a4]#0xc"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x5e, 0xfc ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x744"
+  -
+    input:
+      bytes: [ 0xd9, 0x22, 0xa4, 0xba ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a2, [a2]#-0x551c"
+  -
+    input:
+      bytes: [ 0xd9, 0x44, 0x08, 0xc0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a4, [a4]#0x308"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x0f, 0xf6 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x13e2"
+  -
+    input:
+      bytes: [ 0x3b, 0x80, 0x00, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d1, #0x8"
+  -
+    input:
+      bytes: [ 0x37, 0x04, 0xe8, 0x1b ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d1, d4, #0x17, #0x8"
+  -
+    input:
+      bytes: [ 0xfe, 0xe3 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, d14, #0x26"
+  -
+    input:
+      bytes: [ 0xd9, 0x55, 0xc0, 0x87 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a5, [a5]#0x7e00"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x75, 0x2a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x1ab16"
+  -
+    input:
+      bytes: [ 0xee, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz d15, #0x8"
+  -
+    input:
+      bytes: [ 0x8f, 0xff, 0x83, 0x21 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor d2, d15, #0x3f"
+  -
+    input:
+      bytes: [ 0x7b, 0x00, 0x12, 0xf4 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh d15, #0x4120"
+  -
+    input:
+      bytes: [ 0x2e, 0x4a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.t d15, #0x4, #0x14"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xf4, 0x4b ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x16818"
+  -
+    input:
+      bytes: [ 0x91, 0x40, 0x00, 0x27 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a2, #0x7004"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x07, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x20e"
+  -
+    input:
+      bytes: [ 0xb7, 0x00, 0x01, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d0, d0, #0, #0, #0x1"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x22, 0xfe ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x3bc"
+  -
+    input:
+      bytes: [ 0x0b, 0x08, 0x10, 0x21 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ne d2, d8, d0"
+  -
+    input:
+      bytes: [ 0x88, 0xaf ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.h d15, [a15]#0x14"
+  -
+    input:
+      bytes: [ 0x37, 0x0f, 0xe7, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d15, d15, #0x1, #0x7"
+  -
+    input:
+      bytes: [ 0xbb, 0xe0, 0x3c, 0x4b ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.u d4, #0xb3ce"
+  -
+    input:
+      bytes: [ 0xdf, 0x1f, 0x70, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, #0x1, #0xe0"
+  -
+    input:
+      bytes: [ 0x8c, 0x42 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.h d15, [a4]#0x4"
+  -
+    input:
+      bytes: [ 0x26, 0xfa ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d10, d15"
+  -
+    input:
+      bytes: [ 0xdf, 0x04, 0xfb, 0x7f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d4, #0, #-0xa"
+  -
+    input:
+      bytes: [ 0x6f, 0x1f, 0x12, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.t d15, #0x1, #0x24"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x2b, 0xf6 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x13aa"
+  -
+    input:
+      bytes: [ 0x3b, 0x80, 0x05, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d0, #0x58"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x26, 0x11 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x224c"
+  -
+    input:
+      bytes: [ 0x7b, 0x00, 0x00, 0xf4 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh d15, #0x4000"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x56, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x20ac"
+  -
+    input:
+      bytes: [ 0x01, 0x45, 0x30, 0xf4 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ge.a d15, a5, a4"
+  -
+    input:
+      bytes: [ 0x1d, 0xff, 0xd7, 0xfd ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #-0x452"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x84, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x308"
+  -
+    input:
+      bytes: [ 0x6e, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d15, #0x20"
+  -
+    input:
+      bytes: [ 0x0f, 0x0a, 0x80, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d15, d10, d0"
+  -
+    input:
+      bytes: [ 0x61, 0xff, 0x02, 0xd9 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcall #-0x4dfc"
+  -
+    input:
+      bytes: [ 0x3c, 0x30 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x60"
+  -
+    input:
+      bytes: [ 0xab, 0xf0, 0x1f, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "cadd d0, d0, d0, #-0x1"
+  -
+    input:
+      bytes: [ 0x6e, 0x3e ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d15, #0x7c"
+  -
+    input:
+      bytes: [ 0xba, 0x0f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "eq d15, d15, #0"
+  -
+    input:
+      bytes: [ 0xb7, 0x4f, 0x08, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, #0x4, #0, #0x8"
+  -
+    input:
+      bytes: [ 0x02, 0x5f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d15, d5"
+  -
+    input:
+      bytes: [ 0xee, 0x90 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz d15, #-0xe0"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x50, 0x11 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x22a0"
+  -
+    input:
+      bytes: [ 0x02, 0x9d ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d13, d9"
+  -
+    input:
+      bytes: [ 0x1d, 0x00, 0xa0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x140"
+  -
+    input:
+      bytes: [ 0x76, 0xdb ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d13, #0x16"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xb7, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x76e"
+  -
+    input:
+      bytes: [ 0x37, 0xf0, 0x03, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d0, d0, d15, #0, #0x3"
+  -
+    input:
+      bytes: [ 0x8b, 0x0d, 0x00, 0xf4 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.eq d15, d13, #0"
+  -
+    input:
+      bytes: [ 0x61, 0xff, 0x94, 0xd8 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcall #-0x4ed8"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xac, 0xfd ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x4a8"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x36, 0x0e ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x1c6c"
+  -
+    input:
+      bytes: [ 0x0b, 0x93, 0x00, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.eq d0, d3, d9"
+  -
+    input:
+      bytes: [ 0x09, 0xf0, 0x3c, 0xfa ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.q d0, [a15]#-0x4"
+  -
+    input:
+      bytes: [ 0x3c, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0xa"
+  -
+    input:
+      bytes: [ 0x0b, 0x04, 0x10, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ne d15, d4, d0"
+  -
+    input:
+      bytes: [ 0x02, 0xf2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d2, d15"
+  -
+    input:
+      bytes: [ 0xb7, 0x7f, 0x03, 0xfe ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, #0x7, #0x1c, #0x3"
+  -
+    input:
+      bytes: [ 0xdf, 0x1f, 0xfb, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, #0x1, #-0xa"
+  -
+    input:
+      bytes: [ 0x8b, 0x08, 0x00, 0x22 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "eq d2, d8, #0"
+  -
+    input:
+      bytes: [ 0x42, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d8, d0"
+  -
+    input:
+      bytes: [ 0x49, 0xa7, 0x00, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a7, [sp]#0"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xae, 0xfe ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x2a4"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x69, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x4d2"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xb8, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x90"
+  -
+    input:
+      bytes: [ 0x4b, 0xf0, 0x51, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "div.f d15, d0, d15"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xa1, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0xbe"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0xcc, 0xaa ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#-0x5174"
+  -
+    input:
+      bytes: [ 0x8b, 0x70, 0x00, 0xf3 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "min d15, d0, #0x7"
+  -
+    input:
+      bytes: [ 0xbf, 0xa0, 0xf6, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt.u d0, #0xa, #-0x14"
+  -
+    input:
+      bytes: [ 0x94, 0xf4 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.h d4, [a15]"
+  -
+    input:
+      bytes: [ 0x46, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "not d1"
+  -
+    input:
+      bytes: [ 0x0b, 0x02, 0x10, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ne d15, d2, d0"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0x10, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0x50"
+  -
+    input:
+      bytes: [ 0x4b, 0xbc, 0x51, 0x40 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "div.f d4, d12, d11"
+  -
+    input:
+      bytes: [ 0xda, 0x69 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d15, #0x69"
+  -
+    input:
+      bytes: [ 0xdf, 0x2d, 0x0b, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d13, #0x2, #0x16"
+  -
+    input:
+      bytes: [ 0x02, 0x0f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d15, d0"
+  -
+    input:
+      bytes: [ 0x3f, 0x0f, 0xf2, 0x7f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt d15, d0, #-0x1c"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xbf, 0xfd ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x482"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x77, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x4ee"
+  -
+    input:
+      bytes: [ 0x37, 0x0f, 0x02, 0xf2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, d0, #0x4, #0x2"
+  -
+    input:
+      bytes: [ 0x61, 0xff, 0x26, 0xd9 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcall #-0x4db4"
+  -
+    input:
+      bytes: [ 0x8f, 0xf4, 0x0f, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d15, d4, #0xff"
+  -
+    input:
+      bytes: [ 0x9b, 0x34, 0x42, 0x4a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addih d4, d4, #0xa423"
+  -
+    input:
+      bytes: [ 0x01, 0xf4, 0x20, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub.a a15, a4, a15"
+  -
+    input:
+      bytes: [ 0x01, 0xc0, 0x00, 0x26 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addsc.a a2, a12, d0, #0"
+  -
+    input:
+      bytes: [ 0x89, 0xff, 0xba, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [a15]#0x3a, d15"
+  -
+    input:
+      bytes: [ 0x8e, 0x87 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlez d8, #0xe"
+  -
+    input:
+      bytes: [ 0x3b, 0xc0, 0x06, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d0, #0x6c"
+  -
+    input:
+      bytes: [ 0x40, 0xd4 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.aa a4, a13"
+  -
+    input:
+      bytes: [ 0x7b, 0x60, 0x61, 0xf4 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh d15, #0x4616"
+  -
+    input:
+      bytes: [ 0xa0, 0xf4 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.a a4, #0xf"
+  -
+    input:
+      bytes: [ 0x37, 0xf0, 0x83, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d0, d15, #0x1, #0x3"
+  -
+    input:
+      bytes: [ 0xa6, 0x30 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or d0, d3"
+  -
+    input:
+      bytes: [ 0x09, 0xff, 0xe2, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.hu d15, [a15]#0x22"
+  -
+    input:
+      bytes: [ 0x37, 0x05, 0x68, 0xf4 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d15, d5, #0x8, #0x8"
+  -
+    input:
+      bytes: [ 0x8f, 0xf8, 0x00, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d0, d8, #0xf"
+  -
+    input:
+      bytes: [ 0x8b, 0x48, 0x60, 0xf3 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "max.u d15, d8, #0x4"
+  -
+    input:
+      bytes: [ 0x4b, 0xf0, 0x11, 0x42 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "div.u e4, d0, d15"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xd0, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x5a0"
+  -
+    input:
+      bytes: [ 0xbb, 0x00, 0xc2, 0x1b ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.u d1, #0xbc20"
+  -
+    input:
+      bytes: [ 0x49, 0x24, 0x3e, 0x2a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a4, [a2]#0xbe"
+  -
+    input:
+      bytes: [ 0x8f, 0x19, 0x40, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or d15, d9, #0x1"
+  -
+    input:
+      bytes: [ 0xae, 0x75 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz.t d15, #0x7, #0xa"
+  -
+    input:
+      bytes: [ 0x3f, 0xf8, 0x07, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt.u d8, d15, #0xe"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x16, 0x4c ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x167d4"
+  -
+    input:
+      bytes: [ 0xb7, 0x0f, 0x01, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d8, d15, #0, #0, #0x1"
+  -
+    input:
+      bytes: [ 0x49, 0xae, 0x13, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a14, [sp]#0x13"
+  -
+    input:
+      bytes: [ 0x0b, 0x23, 0x10, 0x48 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov e4, d3, d2"
+  -
+    input:
+      bytes: [ 0x8f, 0x10, 0x00, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d0, d0, #0x1"
+  -
+    input:
+      bytes: [ 0xa6, 0x20 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or d0, d2"
+  -
+    input:
+      bytes: [ 0x91, 0x10, 0x00, 0x25 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a2, #0x5001"
+  -
+    input:
+      bytes: [ 0x4b, 0x0f, 0x11, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "div.u e0, d15, d0"
+  -
+    input:
+      bytes: [ 0xe2, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul d0, d1"
+  -
+    input:
+      bytes: [ 0x0b, 0x60, 0xc0, 0xa0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "subx d10, d0, d6"
+  -
+    input:
+      bytes: [ 0x02, 0x0c ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d12, d0"
+  -
+    input:
+      bytes: [ 0x76, 0x12 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d1, #0x4"
+  -
+    input:
+      bytes: [ 0x91, 0x00, 0x00, 0xf8 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a15, #0x8000"
+  -
+    input:
+      bytes: [ 0x02, 0xf6 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d6, d15"
+  -
+    input:
+      bytes: [ 0xb7, 0x00, 0x81, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d0, d0, #0, #0x3, #0x1"
+  -
+    input:
+      bytes: [ 0x8f, 0x2a, 0x40, 0xa1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or d10, d10, #0x2"
+  -
+    input:
+      bytes: [ 0x3b, 0xe0, 0x02, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d0, #0x2e"
+  -
+    input:
+      bytes: [ 0xfc, 0x5e ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "loop a5, #-0x4"
+  -
+    input:
+      bytes: [ 0x26, 0x51 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d1, d5"
+  -
+    input:
+      bytes: [ 0x3b, 0xb0, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d0, #0xb"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x2c, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x1a8"
+  -
+    input:
+      bytes: [ 0x92, 0x30 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d0, d15, #0x3"
+  -
+    input:
+      bytes: [ 0xa2, 0x0f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub d15, d0"
+  -
+    input:
+      bytes: [ 0x3c, 0x11 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x22"
+  -
+    input:
+      bytes: [ 0x3e, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d0, #0x14"
+  -
+    input:
+      bytes: [ 0x3c, 0x1e ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x3c"
+  -
+    input:
+      bytes: [ 0xfe, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, d0, #0x22"
+  -
+    input:
+      bytes: [ 0x0b, 0x1d, 0x00, 0xf2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.eq d15, d13, d1"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x95, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x52a"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xf9, 0x2b ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x1a80e"
+  -
+    input:
+      bytes: [ 0xb7, 0x1a, 0x81, 0xa4 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d10, d10, #0x1, #0x9, #0x1"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x66, 0x35 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x19534"
+  -
+    input:
+      bytes: [ 0x4b, 0x12, 0x01, 0x22 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "div e2, d2, d1"
+  -
+    input:
+      bytes: [ 0x06, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh d0, #-0x1"
+  -
+    input:
+      bytes: [ 0x37, 0x0f, 0x68, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d15, d15, #0, #0x8"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x87, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x10e"
+  -
+    input:
+      bytes: [ 0x07, 0x57, 0xff, 0xcf ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor.t d12, d7, #0x1f, d5, #0x1f"
+  -
+    input:
+      bytes: [ 0xc2, 0xf4 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d4, #-0x1"
+  -
+    input:
+      bytes: [ 0xf6, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz d0, #0xc"
+  -
+    input:
+      bytes: [ 0x8f, 0xff, 0x83, 0x81 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor d8, d15, #0x3f"
+  -
+    input:
+      bytes: [ 0x3b, 0x50, 0xeb, 0x56 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d5, #0x6eb5"
+  -
+    input:
+      bytes: [ 0xd9, 0x22, 0x2c, 0x61 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a2, [a2]#0x11ac"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x0c, 0xfc ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x7e8"
+  -
+    input:
+      bytes: [ 0x37, 0x0f, 0xe1, 0xf2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d15, d15, #0x5, #0x1"
+  -
+    input:
+      bytes: [ 0x49, 0x2e, 0x0a, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a14, [a2]#0xa"
+  -
+    input:
+      bytes: [ 0x7e, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, d0, #0x4"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x23, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x1ba"
+  -
+    input:
+      bytes: [ 0xc6, 0x21 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor d1, d2"
+  -
+    input:
+      bytes: [ 0x5f, 0x0f, 0xd3, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d0, #0x1a6"
+  -
+    input:
+      bytes: [ 0x8c, 0xa2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.h d15, [sp]#0x4"
+  -
+    input:
+      bytes: [ 0x6e, 0xc8 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d15, #-0x70"
+  -
+    input:
+      bytes: [ 0xb7, 0x0f, 0x08, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, #0, #0, #0x8"
+  -
+    input:
+      bytes: [ 0x3b, 0x00, 0x03, 0x40 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d4, #0x30"
+  -
+    input:
+      bytes: [ 0x01, 0xef, 0x30, 0xf4 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ge.a d15, a15, a14"
+  -
+    input:
+      bytes: [ 0x09, 0xdf, 0xe4, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.hu d15, [a13]#0x24"
+  -
+    input:
+      bytes: [ 0x37, 0xf0, 0x02, 0xf2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d0, d15, #0x4, #0x2"
+  -
+    input:
+      bytes: [ 0x89, 0x4f, 0xa0, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [a4]#0x20, d15"
+  -
+    input:
+      bytes: [ 0x8f, 0x0a, 0x48, 0xa1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or d10, d10, #0x80"
+  -
+    input:
+      bytes: [ 0x37, 0xf0, 0x81, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d0, d15, #0x3, #0x1"
+  -
+    input:
+      bytes: [ 0x4b, 0xdf, 0x41, 0x40 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.f d4, d15, d13"
+  -
+    input:
+      bytes: [ 0x3c, 0xeb ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #-0x2a"
+  -
+    input:
+      bytes: [ 0x49, 0xa4, 0x14, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a4, [sp]#0x14"
+  -
+    input:
+      bytes: [ 0x89, 0x40, 0xc1, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachei.wi [a4+]#0x1"
+  -
+    input:
+      bytes: [ 0x49, 0xf2, 0x40, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldmst [a15]#0, e2"
+  -
+    input:
+      bytes: [ 0x9b, 0xf9, 0xff, 0x97 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addih d9, d9, #0x7fff"
+  -
+    input:
+      bytes: [ 0x5f, 0x0a, 0x0b, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d10, d0, #0x16"
+  -
+    input:
+      bytes: [ 0x9a, 0x18 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d15, d8, #0x1"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x81, 0x11 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x2302"
+  -
+    input:
+      bytes: [ 0xa2, 0xf2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub d2, d15"
+  -
+    input:
+      bytes: [ 0x5f, 0x0f, 0x9f, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, d0, #0x13e"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x96, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0xd2c"
+  -
+    input:
+      bytes: [ 0x6f, 0x04, 0x04, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.t d4, #0, #0x8"
+  -
+    input:
+      bytes: [ 0x96, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or d15, #0x8"
+  -
+    input:
+      bytes: [ 0x8f, 0x3a, 0x00, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d15, d10, #0x3"
+  -
+    input:
+      bytes: [ 0xab, 0xfa, 0x1f, 0xaa ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "cadd d10, d10, d10, #-0x1"
+  -
+    input:
+      bytes: [ 0x09, 0xf4, 0xb6, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.h d4, [a15]#0x36"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x29, 0x2c ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x1a7ae"
+  -
+    input:
+      bytes: [ 0x5f, 0x0f, 0xf9, 0x7f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d0, #-0xe"
+  -
+    input:
+      bytes: [ 0x02, 0x59 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d9, d5"
+  -
+    input:
+      bytes: [ 0x3b, 0x50, 0x06, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d0, #0x65"
+  -
+    input:
+      bytes: [ 0x6e, 0x75 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d15, #0xea"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xa0, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0xd40"
+  -
+    input:
+      bytes: [ 0x02, 0x42 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d2, d4"
+  -
+    input:
+      bytes: [ 0x6e, 0xca ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d15, #-0x6c"
+  -
+    input:
+      bytes: [ 0x8b, 0x03, 0x00, 0xf5 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.ne d15, d3, #0"
+  -
+    input:
+      bytes: [ 0x7e, 0x0f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, d0, #0x1e"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0"
+  -
+    input:
+      bytes: [ 0x37, 0xf0, 0x87, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d0, d0, d15, #0x9, #0x7"
+  -
+    input:
+      bytes: [ 0x3f, 0xf8, 0x04, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt d8, d15, #0x8"
+  -
+    input:
+      bytes: [ 0xda, 0x0c ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d15, #0xc"
+  -
+    input:
+      bytes: [ 0xa6, 0x51 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or d1, d5"
+  -
+    input:
+      bytes: [ 0x4b, 0x52, 0x51, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "div.f d0, d2, d5"
+  -
+    input:
+      bytes: [ 0x82, 0x1c ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d12, #0x1"
+  -
+    input:
+      bytes: [ 0xc5, 0x02, 0x3f, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a2, #0x7f"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x5d, 0xfb ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x946"
+  -
+    input:
+      bytes: [ 0xa0, 0x0f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.a a15, #0"
+  -
+    input:
+      bytes: [ 0xca, 0x70 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "caddn d0, d15, #0x7"
+  -
+    input:
+      bytes: [ 0x8f, 0xc3, 0x1f, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh d1, d3, #-0x4"
+  -
+    input:
+      bytes: [ 0x01, 0x2e, 0x20, 0xf4 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lt.a d15, a14, a2"
+  -
+    input:
+      bytes: [ 0x6e, 0xf6 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d15, #-0x14"
+  -
+    input:
+      bytes: [ 0x3c, 0x24 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x48"
+  -
+    input:
+      bytes: [ 0x09, 0xff, 0xe0, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.hu d15, [a15]#0x20"
+  -
+    input:
+      bytes: [ 0x37, 0x00, 0x62, 0xfa ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d15, d0, #0x14, #0x2"
+  -
+    input:
+      bytes: [ 0x3c, 0x4f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x9e"
+  -
+    input:
+      bytes: [ 0x3c, 0x56 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0xac"
+  -
+    input:
+      bytes: [ 0xf6, 0x14 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz d1, #0x8"
+  -
+    input:
+      bytes: [ 0x3f, 0xfb, 0xf2, 0x7f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt d11, d15, #-0x1c"
+  -
+    input:
+      bytes: [ 0x3b, 0xa0, 0x03, 0x40 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d4, #0x3a"
+  -
+    input:
+      bytes: [ 0x8f, 0x2a, 0x20, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha d15, d10, #0x2"
+  -
+    input:
+      bytes: [ 0x0b, 0x89, 0x80, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "min d15, d9, d8"
+  -
+    input:
+      bytes: [ 0xbc, 0xf4 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.a a15, #0x8"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xcc, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x598"
+  -
+    input:
+      bytes: [ 0xda, 0x44 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d15, #0x44"
+  -
+    input:
+      bytes: [ 0xa0, 0x0e ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.a a14, #0"
+  -
+    input:
+      bytes: [ 0x53, 0x4f, 0x20, 0x40 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul d4, d15, #0x4"
+  -
+    input:
+      bytes: [ 0xc2, 0x1d ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d13, #0x1"
+  -
+    input:
+      bytes: [ 0x37, 0x00, 0x68, 0x40 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d4, d0, #0, #0x8"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x96, 0xf9 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0xcd4"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xc4, 0x17 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x2f88"
+  -
+    input:
+      bytes: [ 0x77, 0x23, 0x00, 0x0e ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "dextr d0, d3, d2, #0x1c"
+  -
+    input:
+      bytes: [ 0x3c, 0x12 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x24"
+  -
+    input:
+      bytes: [ 0x82, 0x14 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d4, #0x1"
+  -
+    input:
+      bytes: [ 0x09, 0xa0, 0xc4, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.hu d0, [sp]#0x4"
+  -
+    input:
+      bytes: [ 0x4b, 0x0f, 0x71, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ftouz d0, d15"
+  -
+    input:
+      bytes: [ 0x80, 0x2f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.d d15, a2"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x00, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x200"
+  -
+    input:
+      bytes: [ 0xda, 0x41 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d15, #0x41"
+  -
+    input:
+      bytes: [ 0x8b, 0x61, 0x09, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "rsub d15, d1, #0x96"
+  -
+    input:
+      bytes: [ 0x0b, 0x37, 0x80, 0xf2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.ne d15, d7, d3"
+  -
+    input:
+      bytes: [ 0x91, 0x30, 0x00, 0x3f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a3, #0xf003"
+  -
+    input:
+      bytes: [ 0x4b, 0x1f, 0x01, 0x22 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "div e2, d15, d1"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xeb, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x1d6"
+  -
+    input:
+      bytes: [ 0x92, 0x1b ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d11, d15, #0x1"
+  -
+    input:
+      bytes: [ 0x42, 0xf9 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d9, d15"
+  -
+    input:
+      bytes: [ 0x1d, 0xff, 0xb3, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #-0x9a"
+  -
+    input:
+      bytes: [ 0x8f, 0xff, 0x83, 0x11 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor d1, d15, #0x3f"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x0c, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x618"
+  -
+    input:
+      bytes: [ 0x7b, 0x00, 0x18, 0x14 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh d1, #0x4180"
+  -
+    input:
+      bytes: [ 0x6f, 0x6a, 0x08, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.t d10, #0x6, #0x10"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x65, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0xaca"
+  -
+    input:
+      bytes: [ 0x4b, 0x12, 0x51, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "div.f d1, d2, d1"
+  -
+    input:
+      bytes: [ 0xda, 0x32 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d15, #0x32"
+  -
+    input:
+      bytes: [ 0xa6, 0x82 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or d2, d8"
+  -
+    input:
+      bytes: [ 0x06, 0x1f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh d15, #0x1"
+  -
+    input:
+      bytes: [ 0x37, 0x0f, 0x01, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, d0, #0x1e, #0x1"
+  -
+    input:
+      bytes: [ 0x4b, 0x01, 0x51, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "div.f d0, d1, d0"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xe2, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x7c4"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0x00, 0x0c ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#-0x4000"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x04, 0xf9 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0xdf8"
+  -
+    input:
+      bytes: [ 0x40, 0x2d ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.aa a13, a2"
+  -
+    input:
+      bytes: [ 0xb7, 0x3f, 0x08, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, #0x3, #0, #0x8"
+  -
+    input:
+      bytes: [ 0x4b, 0x08, 0x61, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "utof d0, d8"
+  -
+    input:
+      bytes: [ 0x8f, 0x0a, 0x42, 0xa1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or d10, d10, #0x20"
+  -
+    input:
+      bytes: [ 0x1d, 0xff, 0xee, 0xfd ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #-0x424"
+  -
+    input:
+      bytes: [ 0x60, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.a a15, d15"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x87, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x50e"
+  -
+    input:
+      bytes: [ 0x40, 0x4c ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.aa a12, a4"
+  -
+    input:
+      bytes: [ 0x37, 0x00, 0x48, 0x40 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr d4, d0, #0, #0x8"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x76, 0xfe ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x314"
+  -
+    input:
+      bytes: [ 0xd9, 0x44, 0x28, 0xa6 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a4, [a4]#0x62a8"
+  -
+    input:
+      bytes: [ 0x02, 0x96 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d6, d9"
+  -
+    input:
+      bytes: [ 0x8b, 0x0f, 0x20, 0x42 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ne d4, d15, #0"
+  -
+    input:
+      bytes: [ 0xc6, 0xf2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor d2, d15"
+  -
+    input:
+      bytes: [ 0x4e, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jgtz d0, #0x6"
+  -
+    input:
+      bytes: [ 0x49, 0xa7, 0x08, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a7, [sp]#0x8"
+  -
+    input:
+      bytes: [ 0x4e, 0xa8 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jgtz d10, #0x10"
+  -
+    input:
+      bytes: [ 0x3b, 0xf0, 0x26, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d15, #0x126f"
+  -
+    input:
+      bytes: [ 0xdf, 0x0d, 0x16, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d13, #0, #0x2c"
+  -
+    input:
+      bytes: [ 0x0f, 0xf0, 0xa0, 0x50 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or d5, d0, d15"
+  -
+    input:
+      bytes: [ 0x1d, 0xff, 0xc9, 0xfd ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #-0x46e"
+  -
+    input:
+      bytes: [ 0x9b, 0xe1, 0xcb, 0x14 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addih d1, d1, #0x4cbe"
+  -
+    input:
+      bytes: [ 0x1d, 0x00, 0x60, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x2c0"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x3a, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x18c"
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0xfc, 0x7f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jge d15, #0x1, #-0x8"
+  -
+    input:
+      bytes: [ 0xd9, 0x55, 0xb8, 0xba ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a5, [a5]#-0x5508"
+  -
+    input:
+      bytes: [ 0x80, 0x4f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.d d15, a4"
+  -
+    input:
+      bytes: [ 0x96, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or d15, #0x10"
+  -
+    input:
+      bytes: [ 0xf6, 0x49 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz d4, #0x12"
+  -
+    input:
+      bytes: [ 0xdf, 0x10, 0xf6, 0x7f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d0, #0x1, #-0x14"
+  -
+    input:
+      bytes: [ 0xf6, 0x2e ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz d2, #0x1c"
+  -
+    input:
+      bytes: [ 0x06, 0xaf ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh d15, #-0x6"
+  -
+    input:
+      bytes: [ 0x8b, 0x0f, 0x20, 0x12 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ne d1, d15, #0"
+  -
+    input:
+      bytes: [ 0x40, 0xcf ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.aa a15, a12"
+  -
+    input:
+      bytes: [ 0x3b, 0x60, 0x06, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d1, #0x66"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0xdc, 0xa2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0x2e9c"
+  -
+    input:
+      bytes: [ 0x3f, 0xe8, 0xe6, 0x7f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt d8, d14, #-0x34"
+  -
+    input:
+      bytes: [ 0xc2, 0xfc ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d12, #-0x1"
+  -
+    input:
+      bytes: [ 0x09, 0xff, 0xba, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.h d15, [a15]#0x3a"
+  -
+    input:
+      bytes: [ 0xbb, 0x00, 0x68, 0x19 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.u d1, #0x9680"
+  -
+    input:
+      bytes: [ 0xac, 0x48 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [a4]#0x10, d15"
+  -
+    input:
+      bytes: [ 0x02, 0xa0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d0, d10"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0xf4, 0xca ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#-0x50cc"
+  -
+    input:
+      bytes: [ 0x3c, 0x14 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x28"
+  -
+    input:
+      bytes: [ 0x2e, 0x4c ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.t d15, #0x4, #0x18"
+  -
+    input:
+      bytes: [ 0xd9, 0x55, 0x64, 0xba ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a5, [a5]#-0x591c"
+  -
+    input:
+      bytes: [ 0x5f, 0x0f, 0x74, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d0, #0xe8"
+  -
+    input:
+      bytes: [ 0xd9, 0x55, 0x88, 0xca ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a5, [a5]#-0x54f8"
+  -
+    input:
+      bytes: [ 0x0b, 0xb1, 0x00, 0xf2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.eq d15, d1, d11"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x14, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x1028"
+  -
+    input:
+      bytes: [ 0x01, 0xf9, 0x00, 0x46 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addsc.a a4, a15, d9, #0"
+  -
+    input:
+      bytes: [ 0x37, 0xf0, 0x02, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d0, d15, #0, #0x2"
+  -
+    input:
+      bytes: [ 0xda, 0x6f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d15, #0x6f"
+  -
+    input:
+      bytes: [ 0x5f, 0x0f, 0xbf, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d0, #0x17e"
+  -
+    input:
+      bytes: [ 0x8f, 0x1f, 0x00, 0xa0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh d10, d15, #0x1"
+  -
+    input:
+      bytes: [ 0x3c, 0xf9 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #-0xe"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xa9, 0x0f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x1f52"
+  -
+    input:
+      bytes: [ 0x0b, 0x45, 0x10, 0x88 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov e8, d5, d4"
+  -
+    input:
+      bytes: [ 0x0b, 0x01, 0x10, 0x48 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov e4, d1, d0"
+  -
+    input:
+      bytes: [ 0x9b, 0x81, 0xb9, 0x14 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addih d1, d1, #0x4b98"
+  -
+    input:
+      bytes: [ 0xc2, 0x20 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d0, #0x2"
+  -
+    input:
+      bytes: [ 0xdf, 0x7f, 0xf6, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, #0x7, #-0x14"
+  -
+    input:
+      bytes: [ 0x26, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d0, d15"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x04, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x1f8"
+  -
+    input:
+      bytes: [ 0x61, 0xff, 0x35, 0xd9 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcall #-0x4d96"
+  -
+    input:
+      bytes: [ 0xf6, 0x22 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz d2, #0x4"
+  -
+    input:
+      bytes: [ 0x09, 0xdf, 0xc8, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.hu d15, [a13]#0x8"
+  -
+    input:
+      bytes: [ 0x49, 0x4f, 0x04, 0x1a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a4]#0x44"
+  -
+    input:
+      bytes: [ 0x37, 0x0f, 0xe2, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d15, d15, #0x1, #0x2"
+  -
+    input:
+      bytes: [ 0xdf, 0x0f, 0x37, 0x7f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, #0, #-0x192"
+  -
+    input:
+      bytes: [ 0x37, 0x0f, 0x61, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d15, d15, #0x2, #0x1"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0x38, 0x30 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0xf8"
+  -
+    input:
+      bytes: [ 0x8f, 0xc8, 0x3f, 0x40 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha d4, d8, #-0x4"
+  -
+    input:
+      bytes: [ 0x61, 0x00, 0x0e, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcall #0x1c"
+  -
+    input:
+      bytes: [ 0x67, 0xff, 0xbf, 0xbf ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insn.t d11, d15, #0x1f, d15, #0x1f"
+  -
+    input:
+      bytes: [ 0xce, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jgez d0, #0x6"
+  -
+    input:
+      bytes: [ 0x91, 0x10, 0x00, 0x48 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a4, #0x8001"
+  -
+    input:
+      bytes: [ 0x2d, 0x0f, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jli a15"
+  -
+    input:
+      bytes: [ 0x96, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or d15, #0x1"
+  -
+    input:
+      bytes: [ 0x2d, 0x02, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "calli a2"
+  -
+    input:
+      bytes: [ 0x82, 0x50 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d0, #0x5"
+  -
+    input:
+      bytes: [ 0xb7, 0x7f, 0x08, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, #0x7, #0, #0x8"
+  -
+    input:
+      bytes: [ 0x2e, 0x3c ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.t d15, #0x3, #0x18"
+  -
+    input:
+      bytes: [ 0x76, 0x47 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d4, #0xe"
+  -
+    input:
+      bytes: [ 0x8f, 0x2a, 0x40, 0x71 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or d7, d10, #0x2"
+  -
+    input:
+      bytes: [ 0x6e, 0xfc ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d15, #-0x8"
+  -
+    input:
+      bytes: [ 0xd2, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov e6, #0"
+  -
+    input:
+      bytes: [ 0x12, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d9, d15, d0"
+  -
+    input:
+      bytes: [ 0x10, 0xc4 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addsc.a a4, a12, d15, #0"
+  -
+    input:
+      bytes: [ 0xc2, 0xf3 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d3, #-0x1"
+  -
+    input:
+      bytes: [ 0x6f, 0x0f, 0xff, 0x7f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.t d15, #0, #-0x2"
+  -
+    input:
+      bytes: [ 0x86, 0x4f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha d15, #0x4"
+  -
+    input:
+      bytes: [ 0xdf, 0x00, 0xc5, 0x7f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d0, #0, #-0x76"
+  -
+    input:
+      bytes: [ 0x02, 0x8f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d15, d8"
+  -
+    input:
+      bytes: [ 0xac, 0xa3 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [sp]#0x6, d15"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x6d, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0xcda"
+  -
+    input:
+      bytes: [ 0x91, 0x00, 0x00, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a1, #0"
+  -
+    input:
+      bytes: [ 0xd9, 0xee, 0x84, 0x70 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a14, [a14]#0x9c4"
+  -
+    input:
+      bytes: [ 0x8b, 0x60, 0x09, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "rsub d15, d0, #0x96"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x3c, 0x0c ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x1878"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xe8, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x30"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xc8, 0x0e ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x1d90"
+  -
+    input:
+      bytes: [ 0xb4, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [a15], d15"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x92, 0x2c ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x1a6dc"
+  -
+    input:
+      bytes: [ 0xee, 0xbf ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz d15, #-0x82"
+  -
+    input:
+      bytes: [ 0x53, 0x80, 0x20, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul d15, d0, #0x8"
+  -
+    input:
+      bytes: [ 0x86, 0x24 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha d4, #0x2"
+  -
+    input:
+      bytes: [ 0xa0, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.a a2, #0"
+  -
+    input:
+      bytes: [ 0xee, 0x40 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz d15, #0x80"
+  -
+    input:
+      bytes: [ 0xda, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d15, #0x4"
+  -
+    input:
+      bytes: [ 0x5e, 0x3c ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, #0x3, #0x18"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x02, 0x0e ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x1c04"
+  -
+    input:
+      bytes: [ 0xd9, 0x55, 0x2c, 0xda ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a5, [a5]#-0x5c94"
+  -
+    input:
+      bytes: [ 0x49, 0xf5, 0x3c, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a5, [a15]#0x3c"
+  -
+    input:
+      bytes: [ 0x02, 0x6e ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d14, d6"
+  -
+    input:
+      bytes: [ 0x49, 0xa6, 0x00, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a6, [sp]#0"
+  -
+    input:
+      bytes: [ 0x03, 0x6d, 0x0a, 0xc0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd d12, d0, d13, d6"
+  -
+    input:
+      bytes: [ 0x7f, 0xf0, 0xc3, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jge.u d0, d15, #-0x7a"
+  -
+    input:
+      bytes: [ 0x6e, 0x1a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d15, #0x34"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x49, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x16e"
+  -
+    input:
+      bytes: [ 0xee, 0xfb ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz d15, #-0xa"
+  -
+    input:
+      bytes: [ 0x61, 0xff, 0xda, 0xd9 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcall #-0x4c4c"
+  -
+    input:
+      bytes: [ 0xc2, 0xf2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d2, #-0x1"
+  -
+    input:
+      bytes: [ 0xa2, 0x98 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub d8, d9"
+  -
+    input:
+      bytes: [ 0x37, 0x0f, 0x62, 0xf3 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d15, d15, #0x6, #0x2"
+  -
+    input:
+      bytes: [ 0x3c, 0xc4 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #-0x78"
+  -
+    input:
+      bytes: [ 0x91, 0x40, 0x00, 0xf7 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a15, #0x7004"
+  -
+    input:
+      bytes: [ 0xdf, 0x0b, 0x11, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d11, #0, #0x22"
+  -
+    input:
+      bytes: [ 0x8f, 0xf0, 0x01, 0x50 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh d5, d0, #0x1f"
+  -
+    input:
+      bytes: [ 0x06, 0x24 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh d4, #0x2"
+  -
+    input:
+      bytes: [ 0x02, 0xa5 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d5, d10"
+  -
+    input:
+      bytes: [ 0xce, 0x96 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jgez d9, #0xc"
+  -
+    input:
+      bytes: [ 0x37, 0xf3, 0x08, 0x34 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d3, d3, d15, #0x8, #0x8"
+  -
+    input:
+      bytes: [ 0xda, 0x30 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d15, #0x30"
+  -
+    input:
+      bytes: [ 0x49, 0xa6, 0x08, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a6, [sp]#0x8"
+  -
+    input:
+      bytes: [ 0x6f, 0x0f, 0xf3, 0x7f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.t d15, #0, #-0x1a"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xb5, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x96"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xeb, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x2a"
+  -
+    input:
+      bytes: [ 0x15, 0xd0, 0xc0, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lducx #0xd0003fc0"
+  -
+    input:
+      bytes: [ 0x37, 0xf0, 0x03, 0xf3 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d0, d15, #0x6, #0x3"
+  -
+    input:
+      bytes: [ 0x4b, 0x0f, 0x61, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "utof d15, d15"
+  -
+    input:
+      bytes: [ 0x8f, 0x3c, 0x00, 0x41 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d4, d12, #0x3"
+  -
+    input:
+      bytes: [ 0x5f, 0x9f, 0xef, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, d9, #0x1de"
+  -
+    input:
+      bytes: [ 0x3e, 0xed ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d14, #0x1a"
+  -
+    input:
+      bytes: [ 0x3e, 0x0b ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d0, #0x16"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x88, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x710"
+  -
+    input:
+      bytes: [ 0x61, 0xff, 0x4d, 0xda ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcall #-0x4b66"
+  -
+    input:
+      bytes: [ 0x09, 0xd4, 0xae, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.h d4, [a13]#0x2e"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xbc, 0x11 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x2378"
+  -
+    input:
+      bytes: [ 0x42, 0x21 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d1, d2"
+  -
+    input:
+      bytes: [ 0x3b, 0x50, 0x06, 0x20 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d2, #0x65"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0x18, 0x96 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0x6258"
+  -
+    input:
+      bytes: [ 0x3a, 0x64 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "eq d15, d4, d6"
+  -
+    input:
+      bytes: [ 0xda, 0x25 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d15, #0x25"
+  -
+    input:
+      bytes: [ 0x8b, 0x01, 0x00, 0xf4 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.eq d15, d1, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x39, 0x90, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.lt d0, d9, d3"
+  -
+    input:
+      bytes: [ 0x8b, 0x0f, 0x02, 0x40 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d4, d15, #0x20"
+  -
+    input:
+      bytes: [ 0xab, 0x10, 0xa0, 0x9f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "seln d9, d15, d0, #0x1"
+  -
+    input:
+      bytes: [ 0xa6, 0x53 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or d3, d5"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xa8, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0xb0"
+  -
+    input:
+      bytes: [ 0x9b, 0xf6, 0xff, 0x67 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addih d6, d6, #0x7fff"
+  -
+    input:
+      bytes: [ 0x3f, 0xac, 0xf8, 0x7f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt d12, d10, #-0x10"
+  -
+    input:
+      bytes: [ 0xab, 0xf8, 0x1f, 0x88 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "cadd d8, d8, d8, #-0x1"
+  -
+    input:
+      bytes: [ 0x6f, 0x3a, 0xec, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz.t d10, #0x3, #-0x28"
+  -
+    input:
+      bytes: [ 0x3b, 0x80, 0x07, 0x60 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d6, #0x78"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x64, 0x2b ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x1a938"
+  -
+    input:
+      bytes: [ 0xda, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d15, #0"
+  -
+    input:
+      bytes: [ 0xab, 0x69, 0x80, 0x91 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sel d9, d1, d9, #0x6"
+  -
+    input:
+      bytes: [ 0x37, 0x0f, 0x50, 0x20 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr d2, d15, #0, #0x10"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x34, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x468"
+  -
+    input:
+      bytes: [ 0x10, 0xc5 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addsc.a a5, a12, d15, #0"
+  -
+    input:
+      bytes: [ 0x94, 0xdf ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.h d15, [a13]"
+  -
+    input:
+      bytes: [ 0x1d, 0x00, 0xe1, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x1c2"
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0xf1, 0x7f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jge d15, #0x1, #-0x1e"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0x28, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0x68"
+  -
+    input:
+      bytes: [ 0x0b, 0x19, 0x80, 0x22 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.ne d2, d9, d1"
+  -
+    input:
+      bytes: [ 0x3f, 0x0f, 0x04, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt.u d15, d0, #0x8"
+  -
+    input:
+      bytes: [ 0x40, 0xd2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.aa a2, a13"
+  -
+    input:
+      bytes: [ 0x37, 0x0f, 0xe8, 0xfb ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d15, d15, #0x17, #0x8"
+  -
+    input:
+      bytes: [ 0x53, 0xcf, 0x20, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul d1, d15, #0xc"
+  -
+    input:
+      bytes: [ 0x3f, 0xf0, 0xf3, 0x7f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt d0, d15, #-0x1a"
+  -
+    input:
+      bytes: [ 0xda, 0x19 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d15, #0x19"
+  -
+    input:
+      bytes: [ 0x67, 0x45, 0x80, 0x5f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ins.t d5, d5, #0, d4, #0x1f"
+  -
+    input:
+      bytes: [ 0x5f, 0x0f, 0x2f, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, d0, #0x5e"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0x80, 0xc9 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#-0x6500"
+  -
+    input:
+      bytes: [ 0x37, 0x04, 0x68, 0xf4 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d15, d4, #0x8, #0x8"
+  -
+    input:
+      bytes: [ 0x0b, 0x71, 0x50, 0x50 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addc d5, d1, d7"
+  -
+    input:
+      bytes: [ 0xda, 0x43 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d15, #0x43"
+  -
+    input:
+      bytes: [ 0x60, 0x52 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.a a2, d5"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0x61, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "utof d0, d0"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x67, 0x4c ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x16732"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x65, 0x11 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x22ca"
+  -
+    input:
+      bytes: [ 0x0b, 0x4f, 0x20, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lt d0, d15, d4"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x17, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x62e"
+  -
+    input:
+      bytes: [ 0x80, 0x55 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.d d5, a5"
+  -
+    input:
+      bytes: [ 0xef, 0x4f, 0x04, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.t d15, #0x14, #0x8"
+  -
+    input:
+      bytes: [ 0x9b, 0x34, 0x98, 0x4d ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addih d4, d4, #0xd983"
+  -
+    input:
+      bytes: [ 0x89, 0xf2, 0xb4, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [a15]#0x34, d2"
+  -
+    input:
+      bytes: [ 0xef, 0x8f, 0x0a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.t d15, #0x18, #0x14"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x97, 0x3e ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x182d2"
+  -
+    input:
+      bytes: [ 0x37, 0x0f, 0x48, 0x20 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr d2, d15, #0, #0x8"
+  -
+    input:
+      bytes: [ 0x10, 0xd2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addsc.a a2, a13, d15, #0"
+  -
+    input:
+      bytes: [ 0x9b, 0xef, 0xcb, 0xf4 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addih d15, d15, #0x4cbe"
+  -
+    input:
+      bytes: [ 0xee, 0x1d ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz d15, #0x3a"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x13, 0x0f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x1e26"
+  -
+    input:
+      bytes: [ 0x5f, 0x0f, 0x2c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d0, #0x58"
+  -
+    input:
+      bytes: [ 0x49, 0xa5, 0x14, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a5, [sp]#0x14"
+  -
+    input:
+      bytes: [ 0xb0, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add.a a5, #0"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0xc0, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0x5c00"
+  -
+    input:
+      bytes: [ 0x91, 0x00, 0x00, 0x47 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a4, #0x7000"
+  -
+    input:
+      bytes: [ 0x37, 0x0a, 0x68, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d0, d10, #0, #0x8"
+  -
+    input:
+      bytes: [ 0x2e, 0x3e ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.t d15, #0x3, #0x1c"
+  -
+    input:
+      bytes: [ 0xf6, 0x8a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz d8, #0x14"
+  -
+    input:
+      bytes: [ 0xd9, 0x55, 0x40, 0x9a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a5, [a5]#-0x59c0"
+  -
+    input:
+      bytes: [ 0x3b, 0x00, 0x10, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d15, #0x100"
+  -
+    input:
+      bytes: [ 0xd9, 0x55, 0x0c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a5, [a5]#0xc"
+  -
+    input:
+      bytes: [ 0x3c, 0x0b ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x16"
+  -
+    input:
+      bytes: [ 0x49, 0xa4, 0x00, 0x4a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a4, [sp]#0x100"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xab, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x156"
+  -
+    input:
+      bytes: [ 0x7e, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, d0, #0xc"
+  -
+    input:
+      bytes: [ 0x9d, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ja #0"
+  -
+    input:
+      bytes: [ 0x26, 0x31 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d1, d3"
+  -
+    input:
+      bytes: [ 0xa0, 0x74 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.a a4, #0x7"
+  -
+    input:
+      bytes: [ 0x01, 0xc9, 0x00, 0xf6 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addsc.a a15, a12, d9, #0"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0x34, 0x20 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0xb4"
+  -
+    input:
+      bytes: [ 0x91, 0x10, 0x88, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a15, #0xf881"
+  -
+    input:
+      bytes: [ 0xfe, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, d0, #0x30"
+  -
+    input:
+      bytes: [ 0x37, 0xf0, 0x02, 0xf3 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d0, d15, #0x6, #0x2"
+  -
+    input:
+      bytes: [ 0xd9, 0x55, 0x14, 0xea ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a5, [a5]#-0x5c6c"
+  -
+    input:
+      bytes: [ 0x3b, 0x60, 0x06, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d0, #0x66"
+  -
+    input:
+      bytes: [ 0x49, 0xa6, 0x0c, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a6, [sp]#0xc"
+  -
+    input:
+      bytes: [ 0x6b, 0x0f, 0x61, 0x41 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd.f d4, d1, d15, d0"
+  -
+    input:
+      bytes: [ 0xda, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d15, #0x3"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x81, 0xf7 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x10fe"
+  -
+    input:
+      bytes: [ 0xda, 0x42 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d15, #0x42"
+  -
+    input:
+      bytes: [ 0xda, 0x64 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d15, #0x64"
+  -
+    input:
+      bytes: [ 0x4e, 0x0d ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jgtz d0, #0x1a"
+  -
+    input:
+      bytes: [ 0x09, 0xaf, 0xc4, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.hu d15, [sp]#0x4"
+  -
+    input:
+      bytes: [ 0xd9, 0x22, 0xc0, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a2, [a2]#0x7c00"
+  -
+    input:
+      bytes: [ 0xa2, 0x54 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub d4, d5"
+  -
+    input:
+      bytes: [ 0x37, 0xf0, 0x0c, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d0, d15, #0, #0xc"
+  -
+    input:
+      bytes: [ 0x3c, 0x17 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x2e"
+  -
+    input:
+      bytes: [ 0x76, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d0, #0xe"
+  -
+    input:
+      bytes: [ 0x0b, 0x71, 0xa0, 0xf2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.lt.u d15, d1, d7"
+  -
+    input:
+      bytes: [ 0xae, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz.t d15, #0, #0x6"
+  -
+    input:
+      bytes: [ 0xb0, 0x4e ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add.a a14, #0x4"
+  -
+    input:
+      bytes: [ 0x8f, 0x0f, 0x1f, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh d0, d15, #-0x10"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x7b, 0x4c ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x1670a"
+  -
+    input:
+      bytes: [ 0x6f, 0x5f, 0x21, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz.t d15, #0x5, #0x42"
+  -
+    input:
+      bytes: [ 0x16, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d15, #0x1"
+  -
+    input:
+      bytes: [ 0x6e, 0x0b ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d15, #0x16"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x8b, 0xe1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x3cea"
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0xf5, 0x7f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jge d15, #0x1, #-0x16"
+  -
+    input:
+      bytes: [ 0xac, 0xf9 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [a15]#0x12, d15"
+  -
+    input:
+      bytes: [ 0x7e, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, d0, #0xa"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0x0c, 0x96 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0x624c"
+  -
+    input:
+      bytes: [ 0x10, 0xc2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addsc.a a2, a12, d15, #0"
+  -
+    input:
+      bytes: [ 0x4b, 0x0f, 0x41, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "itof d15, d15"
+  -
+    input:
+      bytes: [ 0x8a, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "cadd d15, d15, #-0x1"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x3f, 0xfa ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0xb82"
+  -
+    input:
+      bytes: [ 0x09, 0x40, 0x8e, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.h d0, [a4]#0xe"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x2f, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x85e"
+  -
+    input:
+      bytes: [ 0x3b, 0x50, 0x04, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d0, #0x45"
+  -
+    input:
+      bytes: [ 0x8b, 0x7f, 0x01, 0x40 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d4, d15, #0x17"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0xee, 0xe2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0x2fae"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0xa4, 0xba ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#-0x551c"
+  -
+    input:
+      bytes: [ 0x8b, 0x1f, 0x00, 0x22 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "eq d2, d15, #0x1"
+  -
+    input:
+      bytes: [ 0x46, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "not d4"
+  -
+    input:
+      bytes: [ 0xd9, 0xaa, 0x40, 0x85 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea sp, [sp]#0x5600"
+  -
+    input:
+      bytes: [ 0x76, 0x92 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d9, #0x4"
+  -
+    input:
+      bytes: [ 0xbd, 0x0e, 0x28, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.a a14, #0x50"
+  -
+    input:
+      bytes: [ 0x94, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.h d15, [a15]"
+  -
+    input:
+      bytes: [ 0x5f, 0x0f, 0xbc, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d0, #0x178"
+  -
+    input:
+      bytes: [ 0x49, 0xff, 0x00, 0x1a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0x40"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0x44, 0x20 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0x484"
+  -
+    input:
+      bytes: [ 0xda, 0x34 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d15, #0x34"
+  -
+    input:
+      bytes: [ 0x89, 0xff, 0xb4, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [a15]#0x34, d15"
+  -
+    input:
+      bytes: [ 0x7f, 0xf0, 0x03, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jge.u d0, d15, #0x6"
+  -
+    input:
+      bytes: [ 0x3f, 0xf9, 0xf7, 0x7f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt d9, d15, #-0x12"
+  -
+    input:
+      bytes: [ 0x7b, 0x00, 0xf0, 0x13 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh d1, #0x3f00"
+  -
+    input:
+      bytes: [ 0x61, 0xff, 0xbd, 0xd8 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcall #-0x4e86"
+  -
+    input:
+      bytes: [ 0xce, 0x77 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jgez d7, #0xe"
+  -
+    input:
+      bytes: [ 0xde, 0x28 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, #0x2, #0x30"
+  -
+    input:
+      bytes: [ 0xee, 0xfc ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz d15, #-0x8"
+  -
+    input:
+      bytes: [ 0xb7, 0x01, 0x02, 0x20 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d2, d1, #0, #0, #0x2"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0x41, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "itof d15, d0"
+  -
+    input:
+      bytes: [ 0x8f, 0x1a, 0x40, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or d15, d10, #0x1"
+  -
+    input:
+      bytes: [ 0x2e, 0x23 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.t d15, #0x2, #0x6"
+  -
+    input:
+      bytes: [ 0x3c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x0"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xab, 0xf9 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0xcaa"
+  -
+    input:
+      bytes: [ 0x80, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.d d0, a15"
+  -
+    input:
+      bytes: [ 0x7e, 0x17 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, d1, #0xe"
+  -
+    input:
+      bytes: [ 0x09, 0xf0, 0xb4, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.h d0, [a15]#0x34"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xe2, 0x19 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x33c4"
+  -
+    input:
+      bytes: [ 0xda, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d15, #0x1"
+  -
+    input:
+      bytes: [ 0x37, 0xf0, 0x81, 0xf3 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d0, d15, #0x7, #0x1"
+  -
+    input:
+      bytes: [ 0x4b, 0xf2, 0x51, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "div.f d15, d2, d15"
+  -
+    input:
+      bytes: [ 0xa0, 0x72 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.a a2, #0x7"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x48, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x490"
+  -
+    input:
+      bytes: [ 0xac, 0xa1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [sp]#0x2, d15"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0xfc, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0x1c3c"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0x30, 0x20 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0xb0"
+  -
+    input:
+      bytes: [ 0x3e, 0x0e ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d0, #0x1c"
+  -
+    input:
+      bytes: [ 0xd9, 0x22, 0xb8, 0x61 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a2, [a2]#0x19b8"
+  -
+    input:
+      bytes: [ 0x76, 0x15 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d1, #0xa"
+  -
+    input:
+      bytes: [ 0x2e, 0x27 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.t d15, #0x2, #0xe"
+  -
+    input:
+      bytes: [ 0xd9, 0xee, 0x9e, 0x70 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a14, [a14]#0x9de"
+  -
+    input:
+      bytes: [ 0x6b, 0x0e, 0x21, 0xf2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add.f d15, d2, d14"
+  -
+    input:
+      bytes: [ 0x82, 0x1e ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d14, #0x1"
+  -
+    input:
+      bytes: [ 0x86, 0x21 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha d1, #0x2"
+  -
+    input:
+      bytes: [ 0x4b, 0x0c, 0x61, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "utof d15, d12"
+  -
+    input:
+      bytes: [ 0x10, 0x4f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addsc.a a15, a4, d15, #0"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x27, 0x38 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x18fb2"
+  -
+    input:
+      bytes: [ 0x37, 0xf0, 0x01, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d0, d0, d15, #0, #0x1"
+  -
+    input:
+      bytes: [ 0x76, 0xb6 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d11, #0xc"
+  -
+    input:
+      bytes: [ 0x49, 0x55, 0x0c, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a5, [a5]#0xc"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x0a, 0xfe ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x3ec"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xdb, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x9b6"
+  -
+    input:
+      bytes: [ 0x5f, 0x8f, 0xc7, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d8, #0x18e"
+  -
+    input:
+      bytes: [ 0xda, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d15, #0x9"
+  -
+    input:
+      bytes: [ 0x37, 0x0f, 0x6c, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d15, d15, #0, #0xc"
+  -
+    input:
+      bytes: [ 0x37, 0x04, 0x68, 0xfc ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d15, d4, #0x18, #0x8"
+  -
+    input:
+      bytes: [ 0x6f, 0x2f, 0x12, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.t d15, #0x2, #0x24"
+  -
+    input:
+      bytes: [ 0x0f, 0x10, 0x10, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha d0, d0, d1"
+  -
+    input:
+      bytes: [ 0x6e, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d15, #0x4"
+  -
+    input:
+      bytes: [ 0x09, 0xf0, 0xb6, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.h d0, [a15]#0x36"
+  -
+    input:
+      bytes: [ 0x5f, 0x0f, 0xd6, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d0, #0x1ac"
+  -
+    input:
+      bytes: [ 0xc2, 0xfe ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d14, #-0x1"
+  -
+    input:
+      bytes: [ 0x6e, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d15, #0x10"
+  -
+    input:
+      bytes: [ 0x10, 0x2f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addsc.a a15, a2, d15, #0"
+  -
+    input:
+      bytes: [ 0x6e, 0x0e ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d15, #0x1c"
+  -
+    input:
+      bytes: [ 0xda, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d15, #0x8"
+  -
+    input:
+      bytes: [ 0xbd, 0x0f, 0x1a, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz.a a15, #0x34"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x01, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x1fe"
+  -
+    input:
+      bytes: [ 0x3c, 0x1f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x3e"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xab, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x556"
+  -
+    input:
+      bytes: [ 0x5f, 0x8f, 0x21, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d8, #0x42"
+  -
+    input:
+      bytes: [ 0x5f, 0x0f, 0xb9, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d0, #0x172"
+  -
+    input:
+      bytes: [ 0x73, 0xd7, 0x0a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul d0, d7, d13"
+  -
+    input:
+      bytes: [ 0x8b, 0x0f, 0x20, 0x32 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ne d3, d15, #0"
+  -
+    input:
+      bytes: [ 0x2e, 0x0c ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.t d15, #0, #0x18"
+  -
+    input:
+      bytes: [ 0xd9, 0x55, 0x98, 0xca ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a5, [a5]#-0x54e8"
+  -
+    input:
+      bytes: [ 0xd9, 0x44, 0x28, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a4, [a4]#0x28"
+  -
+    input:
+      bytes: [ 0x09, 0x40, 0x84, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.h d0, [a4]#0x4"
+  -
+    input:
+      bytes: [ 0xfc, 0x2e ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "loop a2, #-0x4"
+  -
+    input:
+      bytes: [ 0xea, 0x69 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmovn d9, d15, #0x6"
+  -
+    input:
+      bytes: [ 0x3c, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #-0x1e"
+  -
+    input:
+      bytes: [ 0x3c, 0x48 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x90"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0x00, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0x6000"
+  -
+    input:
+      bytes: [ 0x7a, 0xe8 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lt d15, d8, d14"
+  -
+    input:
+      bytes: [ 0x60, 0x4f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.a a15, d4"
+  -
+    input:
+      bytes: [ 0x82, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d9, #0"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x13, 0xf8 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0xfda"
+  -
+    input:
+      bytes: [ 0xdf, 0x0f, 0xcf, 0x81 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, #0, #0x39e"
+  -
+    input:
+      bytes: [ 0x7f, 0x0e, 0xde, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jge.u d14, d0, #-0x44"
+  -
+    input:
+      bytes: [ 0x3b, 0xa0, 0x07, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d0, #0x7a"
+  -
+    input:
+      bytes: [ 0xd9, 0x55, 0x70, 0x4a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a5, [a5]#-0x5ad0"
+  -
+    input:
+      bytes: [ 0xd9, 0x88, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a8, [a8]#0"
+  -
+    input:
+      bytes: [ 0xef, 0x7f, 0x06, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.t d15, #0x17, #0xc"
+  -
+    input:
+      bytes: [ 0xb0, 0x4f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add.a a15, #0x4"
+  -
+    input:
+      bytes: [ 0x92, 0x19 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d9, d15, #0x1"
+  -
+    input:
+      bytes: [ 0xd9, 0x55, 0xac, 0xca ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a5, [a5]#-0x54d4"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xb3, 0x2a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x1aa9a"
+  -
+    input:
+      bytes: [ 0x40, 0x45 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.aa a5, a4"
+  -
+    input:
+      bytes: [ 0x01, 0xdd, 0x00, 0xd6 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addsc.a a13, a13, d13, #0"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x2d, 0x11 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x225a"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x5a, 0xf9 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0xd4c"
+  -
+    input:
+      bytes: [ 0x1d, 0xff, 0x04, 0xfe ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #-0x3f8"
+  -
+    input:
+      bytes: [ 0x20, 0x60 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub.a sp, #0x60"
+  -
+    input:
+      bytes: [ 0x7f, 0x0f, 0x16, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jge d15, d0, #0x2c"
+  -
+    input:
+      bytes: [ 0xc5, 0xff, 0x00, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, #0xf0001000"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0xa8, 0xda ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#-0x5498"
+  -
+    input:
+      bytes: [ 0x37, 0x0f, 0x01, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, d0, #0x2, #0x1"
+  -
+    input:
+      bytes: [ 0x76, 0x4a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d4, #0x14"
+  -
+    input:
+      bytes: [ 0x3f, 0x0f, 0xe8, 0x7f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt d15, d0, #-0x30"
+  -
+    input:
+      bytes: [ 0xd9, 0x55, 0x8c, 0xda ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a5, [a5]#-0x54b4"
+  -
+    input:
+      bytes: [ 0x8b, 0x01, 0xa0, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addc d1, d1, #0"
+  -
+    input:
+      bytes: [ 0x09, 0xdf, 0xe2, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.hu d15, [a13]#0x22"
+  -
+    input:
+      bytes: [ 0xd9, 0xee, 0x2e, 0xe0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a14, [a14]#0x3ae"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x18, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x30"
+  -
+    input:
+      bytes: [ 0x3b, 0x80, 0x3e, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d0, #0x3e8"
+  -
+    input:
+      bytes: [ 0xbb, 0xd0, 0xcc, 0x0c ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.u d0, #0xcccd"
+  -
+    input:
+      bytes: [ 0x3e, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d0, #0xa"
+  -
+    input:
+      bytes: [ 0xee, 0xfd ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz d15, #-0x6"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x10, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x820"
+  -
+    input:
+      bytes: [ 0xc6, 0x1f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor d15, d1"
+  -
+    input:
+      bytes: [ 0x42, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d0, d8"
+  -
+    input:
+      bytes: [ 0xee, 0xfa ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz d15, #-0xc"
+  -
+    input:
+      bytes: [ 0xa6, 0x54 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or d4, d5"
+  -
+    input:
+      bytes: [ 0x91, 0x40, 0x00, 0xa7 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a sp, #0x7004"
+  -
+    input:
+      bytes: [ 0x6f, 0x5a, 0x06, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz.t d10, #0x5, #0xc"
+  -
+    input:
+      bytes: [ 0xd9, 0x22, 0xc0, 0x0b ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a2, [a2]#-0x4400"
+  -
+    input:
+      bytes: [ 0x3e, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d0, #0x10"
+  -
+    input:
+      bytes: [ 0x37, 0xf0, 0x02, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d0, d0, d15, #0x14, #0x2"
+  -
+    input:
+      bytes: [ 0x3c, 0x1a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x34"
+  -
+    input:
+      bytes: [ 0x02, 0xa7 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d7, d10"
+  -
+    input:
+      bytes: [ 0xda, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d15, #0x5"
+  -
+    input:
+      bytes: [ 0x3b, 0x60, 0xff, 0x1f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d1, #-0xa"
+  -
+    input:
+      bytes: [ 0x4e, 0xf7 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jgtz d15, #0xe"
+  -
+    input:
+      bytes: [ 0x3c, 0x3f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x7e"
+  -
+    input:
+      bytes: [ 0x37, 0x0f, 0x50, 0x40 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr d4, d15, #0, #0x10"
+  -
+    input:
+      bytes: [ 0x91, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a0, #0"
+  -
+    input:
+      bytes: [ 0x09, 0xf8, 0xb4, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.h d8, [a15]#0x34"
+  -
+    input:
+      bytes: [ 0x3b, 0x20, 0x05, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d0, #0x52"
+  -
+    input:
+      bytes: [ 0xdf, 0x02, 0x21, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d2, #0, #0x42"
+  -
+    input:
+      bytes: [ 0x6f, 0x20, 0xf8, 0x7f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.t d0, #0x2, #-0x10"
+  -
+    input:
+      bytes: [ 0x6e, 0x17 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d15, #0x2e"
+  -
+    input:
+      bytes: [ 0x3c, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0xc"
+  -
+    input:
+      bytes: [ 0x6f, 0x29, 0x1b, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.t d9, #0x2, #0x36"
+  -
+    input:
+      bytes: [ 0x3b, 0x00, 0x01, 0x50 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d5, #0x10"
+  -
+    input:
+      bytes: [ 0x82, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d3, #0"
+  -
+    input:
+      bytes: [ 0xc2, 0xf5 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d5, #-0x1"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0x420"
+  -
+    input:
+      bytes: [ 0x7f, 0xf0, 0x06, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jge.u d0, d15, #0xc"
+  -
+    input:
+      bytes: [ 0xee, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz d15, #0xc"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x94, 0x2a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x1aad8"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x08, 0xfc ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x7f0"
+  -
+    input:
+      bytes: [ 0x37, 0xf3, 0x08, 0x30 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d3, d3, d15, #0, #0x8"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xdf, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x1be"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0xc8, 0x41 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0x1d08"
+  -
+    input:
+      bytes: [ 0xd9, 0x22, 0x08, 0x21 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a2, [a2]#0x1088"
+  -
+    input:
+      bytes: [ 0x82, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d0, #0x1"
+  -
+    input:
+      bytes: [ 0xab, 0x0f, 0xa2, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "seln d15, d0, d15, #0x20"
+  -
+    input:
+      bytes: [ 0xfe, 0xdb ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, d13, #0x36"
+  -
+    input:
+      bytes: [ 0x37, 0xf0, 0x03, 0x0c ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d0, d0, d15, #0x18, #0x3"
+  -
+    input:
+      bytes: [ 0xd9, 0x22, 0x48, 0xe1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a2, [a2]#0x1788"
+  -
+    input:
+      bytes: [ 0x1d, 0x00, 0x6e, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x2dc"
+  -
+    input:
+      bytes: [ 0xdf, 0x1f, 0x29, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, #0x1, #0x52"
+  -
+    input:
+      bytes: [ 0x8f, 0x78, 0x00, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d15, d8, #0x7"
+  -
+    input:
+      bytes: [ 0x4b, 0xf2, 0x51, 0x20 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "div.f d2, d2, d15"
+  -
+    input:
+      bytes: [ 0x82, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d10, #0"
+  -
+    input:
+      bytes: [ 0x37, 0x4f, 0x9f, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, d4, #0x1, #0x1f"
+  -
+    input:
+      bytes: [ 0x3c, 0x28 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x50"
+  -
+    input:
+      bytes: [ 0x49, 0xfc, 0x10, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a12, [a15]#0x10"
+  -
+    input:
+      bytes: [ 0xfe, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, d0, #0x32"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x0d, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x1e6"
+  -
+    input:
+      bytes: [ 0x3b, 0xc0, 0x00, 0x90 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d9, #0xc"
+  -
+    input:
+      bytes: [ 0xda, 0x11 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d15, #0x11"
+  -
+    input:
+      bytes: [ 0x7b, 0xd0, 0x38, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh d0, #0x138d"
+  -
+    input:
+      bytes: [ 0xd9, 0x55, 0x48, 0x3a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a5, [a5]#-0x5b38"
+  -
+    input:
+      bytes: [ 0xbb, 0xf0, 0xff, 0x2f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.u d2, #0xffff"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x42, 0xfe ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x37c"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x62, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0xc4"
+  -
+    input:
+      bytes: [ 0x76, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d0, #0x12"
+  -
+    input:
+      bytes: [ 0xd9, 0x44, 0x3c, 0xa0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a4, [a4]#0x2bc"
+  -
+    input:
+      bytes: [ 0x3c, 0x43 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x86"
+  -
+    input:
+      bytes: [ 0x7f, 0xf0, 0x28, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jge d0, d15, #0x50"
+  -
+    input:
+      bytes: [ 0x37, 0x04, 0x68, 0xf8 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d15, d4, #0x10, #0x8"
+  -
+    input:
+      bytes: [ 0x0b, 0xc0, 0xc0, 0xc0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "subx d12, d0, d12"
+  -
+    input:
+      bytes: [ 0x0f, 0x05, 0xd0, 0x11 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "cls d1, d5"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0x14, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0x54"
+  -
+    input:
+      bytes: [ 0x0f, 0x31, 0x10, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha d1, d1, d3"
+  -
+    input:
+      bytes: [ 0xc6, 0x3f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor d15, d3"
+  -
+    input:
+      bytes: [ 0xa6, 0xf5 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or d5, d15"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xda, 0xfa ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0xa4c"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xcc, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0xf98"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x28, 0xfe ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x3b0"
+  -
+    input:
+      bytes: [ 0x15, 0xd0, 0xc0, 0xe3 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "stlcx #0xd0003f80"
+  -
+    input:
+      bytes: [ 0x61, 0xff, 0x4c, 0xda ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcall #-0x4b68"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x27, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x64e"
+  -
+    input:
+      bytes: [ 0x37, 0x09, 0x50, 0x90 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr d9, d9, #0, #0x10"
+  -
+    input:
+      bytes: [ 0x8c, 0x22 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.h d15, [a2]#0x4"
+  -
+    input:
+      bytes: [ 0x76, 0x2a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d2, #0x14"
+  -
+    input:
+      bytes: [ 0x3f, 0x98, 0xe0, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt.u d8, d9, #-0x40"
+  -
+    input:
+      bytes: [ 0x88, 0x22 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.h d2, [a15]#0x4"
+  -
+    input:
+      bytes: [ 0x76, 0x85 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d8, #0xa"
+  -
+    input:
+      bytes: [ 0xaa, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmov d0, d15, #0x1"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x91, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0xde"
+  -
+    input:
+      bytes: [ 0x2e, 0x22 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.t d15, #0x2, #0x4"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0x3c, 0x0b ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#-0x4fc4"
+  -
+    input:
+      bytes: [ 0x3c, 0x3c ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x78"
+  -
+    input:
+      bytes: [ 0x3b, 0x20, 0x03, 0xa0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d10, #0x32"
+  -
+    input:
+      bytes: [ 0x91, 0x20, 0x88, 0x4f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a4, #0xf882"
+  -
+    input:
+      bytes: [ 0x8f, 0xff, 0x83, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor d15, d15, #0x3f"
+  -
+    input:
+      bytes: [ 0x3b, 0x60, 0x09, 0x40 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d4, #0x96"
+  -
+    input:
+      bytes: [ 0x7f, 0x89, 0x04, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jge d9, d8, #0x8"
+  -
+    input:
+      bytes: [ 0x37, 0x0f, 0x70, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d15, d15, #0, #0x10"
+  -
+    input:
+      bytes: [ 0x3e, 0x46 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d4, #0xc"
+  -
+    input:
+      bytes: [ 0xd9, 0x22, 0xa8, 0xa1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a2, [a2]#0x1aa8"
+  -
+    input:
+      bytes: [ 0x37, 0x05, 0x68, 0xfc ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d15, d5, #0x18, #0x8"
+  -
+    input:
+      bytes: [ 0xd9, 0x11, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a1, [a1]#0"
+  -
+    input:
+      bytes: [ 0x0b, 0x45, 0x10, 0xa8 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov e10, d5, d4"
+  -
+    input:
+      bytes: [ 0x06, 0xf4 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh d4, #-0x1"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0x0c, 0x30 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0xcc"
+  -
+    input:
+      bytes: [ 0xfe, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, d0, #0x28"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x9a, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0xf34"
+  -
+    input:
+      bytes: [ 0x3b, 0xa0, 0x02, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d0, #0x2a"
+  -
+    input:
+      bytes: [ 0x6f, 0x2f, 0x34, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.t d15, #0x2, #0x68"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xbd, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x77a"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0x00, 0x20 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0x80"
+  -
+    input:
+      bytes: [ 0x53, 0x8f, 0x20, 0xc0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul d12, d15, #0x8"
+  -
+    input:
+      bytes: [ 0x17, 0x45, 0x80, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "dextr d0, d5, d4, d1"
+  -
+    input:
+      bytes: [ 0x02, 0x45 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d5, d4"
+  -
+    input:
+      bytes: [ 0x82, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d1, #0"
+  -
+    input:
+      bytes: [ 0xd9, 0x55, 0x60, 0xba ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a5, [a5]#-0x5920"
+  -
+    input:
+      bytes: [ 0xb7, 0x2f, 0x08, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, #0x2, #0, #0x8"
+  -
+    input:
+      bytes: [ 0x6e, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d15, #0x6"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x60, 0xfc ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x740"
+  -
+    input:
+      bytes: [ 0x37, 0x04, 0x70, 0x40 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d4, d4, #0, #0x10"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x93, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0xda"
+  -
+    input:
+      bytes: [ 0xb7, 0x1a, 0x01, 0xa5 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d10, d10, #0x1, #0xa, #0x1"
+  -
+    input:
+      bytes: [ 0x4b, 0x1f, 0x01, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmp.f d15, d15, d1"
+  -
+    input:
+      bytes: [ 0xdf, 0x1f, 0xfb, 0x7f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, #0x1, #-0xa"
+  -
+    input:
+      bytes: [ 0xc2, 0x12 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d2, #0x1"
+  -
+    input:
+      bytes: [ 0x37, 0x08, 0x70, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d0, d8, #0, #0x10"
+  -
+    input:
+      bytes: [ 0xda, 0x31 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d15, #0x31"
+  -
+    input:
+      bytes: [ 0x8b, 0x0f, 0x1d, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d8, d15, #-0x30"
+  -
+    input:
+      bytes: [ 0xd9, 0x55, 0xb4, 0xba ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a5, [a5]#-0x550c"
+  -
+    input:
+      bytes: [ 0x02, 0x82 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d2, d8"
+  -
+    input:
+      bytes: [ 0x76, 0xb2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d11, #0x4"
+  -
+    input:
+      bytes: [ 0x61, 0x00, 0x06, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcall #0xc"
+  -
+    input:
+      bytes: [ 0xbe, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d0, #0x2c"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xfa, 0xe1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x3c0c"
+  -
+    input:
+      bytes: [ 0x3f, 0x20, 0x0e, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt d0, d2, #0x1c"
+  -
+    input:
+      bytes: [ 0x8b, 0x1f, 0x03, 0xa1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "rsub d10, d15, #0x31"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xa7, 0xfc ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x6b2"
+  -
+    input:
+      bytes: [ 0x4b, 0xbf, 0x41, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.f d15, d15, d11"
+  -
+    input:
+      bytes: [ 0xfe, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, d0, #0x2a"
+  -
+    input:
+      bytes: [ 0x06, 0x14 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh d4, #0x1"
+  -
+    input:
+      bytes: [ 0x82, 0x78 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d8, #0x7"
+  -
+    input:
+      bytes: [ 0xf6, 0xb6 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz d11, #0xc"
+  -
+    input:
+      bytes: [ 0x02, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d0, d8"
+  -
+    input:
+      bytes: [ 0x3c, 0x39 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x72"
+  -
+    input:
+      bytes: [ 0x06, 0x63 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh d3, #0x6"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x91, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x722"
+  -
+    input:
+      bytes: [ 0x01, 0x42, 0x20, 0x20 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub.a a2, a2, a4"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xc9, 0xf4 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x166e"
+  -
+    input:
+      bytes: [ 0x37, 0x0f, 0x6e, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d15, d15, #0x2, #0xe"
+  -
+    input:
+      bytes: [ 0x89, 0xaf, 0xb4, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [sp]#0x34, d15"
+  -
+    input:
+      bytes: [ 0x6f, 0x04, 0x0d, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz.t d4, #0, #0x1a"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0x24, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0x24"
+  -
+    input:
+      bytes: [ 0x4b, 0xa2, 0x41, 0xa0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.f d10, d2, d10"
+  -
+    input:
+      bytes: [ 0x3e, 0x14 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d1, #0x8"
+  -
+    input:
+      bytes: [ 0x37, 0x0f, 0x0c, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, d0, #0, #0xc"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x0b, 0x2a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x1abea"
+  -
+    input:
+      bytes: [ 0x2b, 0x09, 0x00, 0x9f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "cadd d9, d15, d9, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x0f, 0x01, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "rsub d15, d15, #0x10"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0xb8, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0x1bf8"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x47, 0xfd ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x572"
+  -
+    input:
+      bytes: [ 0x6f, 0x1f, 0xfc, 0x7f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.t d15, #0x1, #-0x8"
+  -
+    input:
+      bytes: [ 0xda, 0x40 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d15, #0x40"
+  -
+    input:
+      bytes: [ 0xdf, 0xf0, 0x51, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d0, #-0x1, #0xa2"
+  -
+    input:
+      bytes: [ 0x5e, 0x23 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, #0x2, #0x6"
+  -
+    input:
+      bytes: [ 0x76, 0xcf ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d12, #0x1e"
+  -
+    input:
+      bytes: [ 0x9b, 0x8f, 0xb9, 0xf4 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addih d15, d15, #0x4b98"
+  -
+    input:
+      bytes: [ 0x8b, 0x8f, 0x00, 0x60 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d6, d15, #0x8"
+  -
+    input:
+      bytes: [ 0x7b, 0x00, 0x00, 0x14 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh d1, #0x4000"
+  -
+    input:
+      bytes: [ 0x3c, 0x2c ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x58"
+  -
+    input:
+      bytes: [ 0x92, 0x39 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d9, d15, #0x3"
+  -
+    input:
+      bytes: [ 0x5f, 0x8f, 0x07, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d8, #0x20e"
+  -
+    input:
+      bytes: [ 0x80, 0x41 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.d d1, a4"
+  -
+    input:
+      bytes: [ 0x92, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d0, d15, #0x1"
+  -
+    input:
+      bytes: [ 0x86, 0x6f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha d15, #0x6"
+  -
+    input:
+      bytes: [ 0xd9, 0x55, 0x4c, 0x2a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a5, [a5]#-0x5b74"
+  -
+    input:
+      bytes: [ 0xd9, 0x55, 0x50, 0x1a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a5, [a5]#-0x5bb0"
+  -
+    input:
+      bytes: [ 0xee, 0xf2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz d15, #-0x1c"
+  -
+    input:
+      bytes: [ 0xee, 0xeb ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz d15, #-0x2a"
+  -
+    input:
+      bytes: [ 0x49, 0xff, 0x0c, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0xc"
+  -
+    input:
+      bytes: [ 0x13, 0xa8, 0x20, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd d15, d15, d8, #0xa"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x18, 0x11 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x2230"
+  -
+    input:
+      bytes: [ 0x8b, 0x0f, 0x1d, 0x90 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d9, d15, #-0x30"
+  -
+    input:
+      bytes: [ 0xc2, 0x18 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d8, #0x1"
+  -
+    input:
+      bytes: [ 0x2e, 0x2b ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.t d15, #0x2, #0x16"
+  -
+    input:
+      bytes: [ 0x0f, 0xa1, 0x10, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha d1, d1, d10"
+  -
+    input:
+      bytes: [ 0x32, 0x58 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "rsub d8"
+  -
+    input:
+      bytes: [ 0xba, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "eq d15, d0, #0"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xc5, 0x29 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x1ac76"
+  -
+    input:
+      bytes: [ 0x5f, 0x0f, 0x59, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, d0, #0xb2"
+  -
+    input:
+      bytes: [ 0x5e, 0x16 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, #0x1, #0xc"
+  -
+    input:
+      bytes: [ 0x91, 0x40, 0x00, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a15, #0xf004"
+  -
+    input:
+      bytes: [ 0x0b, 0x17, 0x80, 0xf2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.ne d15, d7, d1"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xb9, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x2172"
+  -
+    input:
+      bytes: [ 0x37, 0x02, 0x68, 0xc0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d12, d2, #0, #0x8"
+  -
+    input:
+      bytes: [ 0x1d, 0x00, 0x8c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x118"
+  -
+    input:
+      bytes: [ 0x3b, 0x10, 0x04, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d0, #0x41"
+  -
+    input:
+      bytes: [ 0x49, 0xf5, 0x3e, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a5, [a15]#0x3e"
+  -
+    input:
+      bytes: [ 0x9b, 0x3f, 0xa8, 0xf3 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addih d15, d15, #0x3a83"
+  -
+    input:
+      bytes: [ 0x6e, 0x0d ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d15, #0x1a"
+  -
+    input:
+      bytes: [ 0x5e, 0xf3 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, #-0x1, #0x6"
+  -
+    input:
+      bytes: [ 0x3c, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x12"
+  -
+    input:
+      bytes: [ 0x0b, 0x71, 0xd0, 0xb0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "subc d11, d1, d7"
+  -
+    input:
+      bytes: [ 0x0f, 0x02, 0x10, 0x20 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha d2, d2, d0"
+  -
+    input:
+      bytes: [ 0xc2, 0xf9 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d9, #-0x1"
+  -
+    input:
+      bytes: [ 0x5f, 0x8f, 0x78, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d8, #0xf0"
+  -
+    input:
+      bytes: [ 0xbc, 0x2c ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.a a2, #0x18"
+  -
+    input:
+      bytes: [ 0x6b, 0x00, 0x31, 0xf5 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub.f d15, d5, d0"
+  -
+    input:
+      bytes: [ 0xd9, 0x44, 0xa0, 0xe5 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a4, [a4]#0x5ba0"
+  -
+    input:
+      bytes: [ 0x9a, 0xd4 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d15, d4, #-0x3"
+  -
+    input:
+      bytes: [ 0x26, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d0, d1"
+  -
+    input:
+      bytes: [ 0xee, 0x38 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz d15, #0x70"
+  -
+    input:
+      bytes: [ 0x91, 0x50, 0x02, 0x2f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a2, #0xf025"
+  -
+    input:
+      bytes: [ 0x4b, 0x19, 0x41, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.f d1, d9, d1"
+  -
+    input:
+      bytes: [ 0xd9, 0x22, 0x92, 0x31 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a2, [a2]#0x18d2"
+  -
+    input:
+      bytes: [ 0xa2, 0x24 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub d4, d2"
+  -
+    input:
+      bytes: [ 0x1d, 0x00, 0x9c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x138"
+  -
+    input:
+      bytes: [ 0xfc, 0x2c ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "loop a2, #-0x8"
+  -
+    input:
+      bytes: [ 0xee, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz d15, #-0x2"
+  -
+    input:
+      bytes: [ 0x3b, 0x60, 0x06, 0x60 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d6, #0x66"
+  -
+    input:
+      bytes: [ 0x01, 0xa0, 0x00, 0xf6 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addsc.a a15, sp, d0, #0"
+  -
+    input:
+      bytes: [ 0x9b, 0xb0, 0xbf, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addih d0, d0, #0x4bfb"
+  -
+    input:
+      bytes: [ 0x1d, 0x00, 0x18, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x430"
+  -
+    input:
+      bytes: [ 0x91, 0x30, 0x00, 0x2f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a2, #0xf003"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xa1, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x2142"
+  -
+    input:
+      bytes: [ 0x7f, 0xf0, 0x08, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jge d0, d15, #0x10"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xae, 0x0c ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x195c"
+  -
+    input:
+      bytes: [ 0xff, 0x14, 0xfc, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jge.u d4, #0x1, #-0x8"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x3a, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0xa74"
+  -
+    input:
+      bytes: [ 0xba, 0x0c ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "eq d15, d12, #0"
+  -
+    input:
+      bytes: [ 0x09, 0x4f, 0xc4, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.hu d15, [a4]#0x4"
+  -
+    input:
+      bytes: [ 0x7d, 0x2f, 0x15, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne.a a15, a2, #0x2a"
+  -
+    input:
+      bytes: [ 0x0b, 0x0f, 0xa0, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "max d15, d15, d0"
+  -
+    input:
+      bytes: [ 0x3b, 0x30, 0x06, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d0, #0x63"
+  -
+    input:
+      bytes: [ 0x91, 0x40, 0x00, 0xa6 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a sp, #0x6004"
+  -
+    input:
+      bytes: [ 0x9b, 0x1f, 0x8d, 0xf3 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addih d15, d15, #0x38d1"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x3b, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x2076"
+  -
+    input:
+      bytes: [ 0x61, 0xff, 0x0f, 0xd5 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcall #-0x55e2"
+  -
+    input:
+      bytes: [ 0xab, 0x0f, 0x83, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sel d15, d0, d15, #0x30"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xa0, 0x11 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x2340"
+  -
+    input:
+      bytes: [ 0xbe, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d0, #0x30"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x89, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0xee"
+  -
+    input:
+      bytes: [ 0x3f, 0xf0, 0x05, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt.u d0, d15, #0xa"
+  -
+    input:
+      bytes: [ 0x37, 0x02, 0x48, 0x20 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr d2, d2, #0, #0x8"
+  -
+    input:
+      bytes: [ 0x0b, 0x60, 0x40, 0xa0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addx d10, d0, d6"
+  -
+    input:
+      bytes: [ 0x49, 0xff, 0x00, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xe4, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x5c8"
+  -
+    input:
+      bytes: [ 0x6f, 0x3f, 0x2c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.t d15, #0x3, #0x58"
+  -
+    input:
+      bytes: [ 0xd9, 0x22, 0x8c, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a2, [a2]#0xbcc"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xc5, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x218a"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x7f, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x102"
+  -
+    input:
+      bytes: [ 0x7b, 0x00, 0x12, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh d0, #0x4120"
+  -
+    input:
+      bytes: [ 0x02, 0x84 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d4, d8"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x11, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x1de"
+  -
+    input:
+      bytes: [ 0x91, 0x20, 0x00, 0x30 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a3, #0x2"
+  -
+    input:
+      bytes: [ 0x9e, 0xf2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, #-0x1, #0x24"
+  -
+    input:
+      bytes: [ 0xf6, 0xa5 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz d10, #0xa"
+  -
+    input:
+      bytes: [ 0x5f, 0x0f, 0xf6, 0x7f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d0, #-0x14"
+  -
+    input:
+      bytes: [ 0x0f, 0x4f, 0x00, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh d15, d15, d4"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xd2, 0x14 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x29a4"
+  -
+    input:
+      bytes: [ 0xc2, 0x1a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d10, #0x1"
+  -
+    input:
+      bytes: [ 0xae, 0x29 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz.t d15, #0x2, #0x12"
+  -
+    input:
+      bytes: [ 0xb0, 0x22 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add.a a2, #0x2"
+  -
+    input:
+      bytes: [ 0x3b, 0x40, 0x06, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d1, #0x64"
+  -
+    input:
+      bytes: [ 0x10, 0xa2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addsc.a a2, sp, d15, #0"
+  -
+    input:
+      bytes: [ 0x7d, 0x4f, 0x0d, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne.a a15, a4, #0x1a"
+  -
+    input:
+      bytes: [ 0x8f, 0x0f, 0x01, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh d15, d15, #0x10"
+  -
+    input:
+      bytes: [ 0x32, 0x5f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "rsub d15"
+  -
+    input:
+      bytes: [ 0xbe, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d0, #0x26"
+  -
+    input:
+      bytes: [ 0xee, 0xf9 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz d15, #-0xe"
+  -
+    input:
+      bytes: [ 0x3b, 0x00, 0x03, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d0, #0x30"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x3b, 0x11 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x2276"
+  -
+    input:
+      bytes: [ 0x3b, 0x00, 0x04, 0xe0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d14, #0x40"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xb1, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x9e"
+  -
+    input:
+      bytes: [ 0x8b, 0x1f, 0xe0, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.eq d0, d15, #0x1"
+  -
+    input:
+      bytes: [ 0x32, 0x50 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "rsub d0"
+  -
+    input:
+      bytes: [ 0x92, 0xf4 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d4, d15, #-0x1"
+  -
+    input:
+      bytes: [ 0xb4, 0xc2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [a12], d2"
+  -
+    input:
+      bytes: [ 0x37, 0x01, 0x50, 0x20 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr d2, d1, #0, #0x10"
+  -
+    input:
+      bytes: [ 0xbb, 0xf0, 0x28, 0xec ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.u d14, #0xc28f"
+  -
+    input:
+      bytes: [ 0x3e, 0x8c ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d8, #0x18"
+  -
+    input:
+      bytes: [ 0x8f, 0x3c, 0x00, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d15, d12, #0x3"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x63, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0xc6"
+  -
+    input:
+      bytes: [ 0xdf, 0x08, 0x71, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d8, #0, #-0x11e"
+  -
+    input:
+      bytes: [ 0x02, 0x48 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d8, d4"
+  -
+    input:
+      bytes: [ 0x76, 0x23 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d2, #0x6"
+  -
+    input:
+      bytes: [ 0xee, 0xf7 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz d15, #-0x12"
+  -
+    input:
+      bytes: [ 0x96, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or d15, #0x4"
+  -
+    input:
+      bytes: [ 0xdf, 0x09, 0x63, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d9, #0, #0xc6"
+  -
+    input:
+      bytes: [ 0x6e, 0xe8 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d15, #-0x30"
+  -
+    input:
+      bytes: [ 0x10, 0x22 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addsc.a a2, a2, d15, #0"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xba, 0xfd ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x48c"
+  -
+    input:
+      bytes: [ 0x37, 0x00, 0x68, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d0, d0, #0, #0x8"
+  -
+    input:
+      bytes: [ 0x15, 0xd0, 0xc0, 0xeb ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldlcx #0xd0003f80"
+  -
+    input:
+      bytes: [ 0x1e, 0x12 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, #0x1, #0x4"
+  -
+    input:
+      bytes: [ 0xdf, 0x09, 0xf6, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d9, #0, #-0x14"
+  -
+    input:
+      bytes: [ 0x3b, 0x00, 0x98, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d15, #0x980"
+  -
+    input:
+      bytes: [ 0xb7, 0x0f, 0x03, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, #0, #0, #0x3"
+  -
+    input:
+      bytes: [ 0x76, 0x87 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d8, #0xe"
+  -
+    input:
+      bytes: [ 0xda, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d15, #0xff"
+  -
+    input:
+      bytes: [ 0x8f, 0x3f, 0x00, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d0, d15, #0x3"
+  -
+    input:
+      bytes: [ 0x7f, 0xf1, 0x06, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jge d1, d15, #0xc"
+  -
+    input:
+      bytes: [ 0xda, 0xbc ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d15, #0xbc"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xd4, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0xda8"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xb9, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0xd72"
+  -
+    input:
+      bytes: [ 0x91, 0x00, 0x00, 0xd7 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a13, #0x7000"
+  -
+    input:
+      bytes: [ 0x2e, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.t d15, #0, #0xa"
+  -
+    input:
+      bytes: [ 0x8f, 0x1f, 0x1e, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh d0, d15, #-0x1f"
+  -
+    input:
+      bytes: [ 0x26, 0x3f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d15, d3"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xee, 0xf9 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0xc24"
+  -
+    input:
+      bytes: [ 0x8f, 0x46, 0x1f, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh d15, d6, #-0xc"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0x61, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "utof d15, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0xcf, 0x01, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d15, d15, #0x1c"
+  -
+    input:
+      bytes: [ 0x4e, 0xf4 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jgtz d15, #0x8"
+  -
+    input:
+      bytes: [ 0xb7, 0x0f, 0x81, 0x2f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d2, d15, #0, #0x1f, #0x1"
+  -
+    input:
+      bytes: [ 0x26, 0x94 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d4, d9"
+  -
+    input:
+      bytes: [ 0x8f, 0x84, 0x1e, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh d15, d4, #-0x18"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x84, 0xfe ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x2f8"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x0e, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x1c"
+  -
+    input:
+      bytes: [ 0xbb, 0x70, 0x71, 0xfb ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.u d15, #0xb717"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x14, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x228"
+  -
+    input:
+      bytes: [ 0x3b, 0x80, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d0, #0x8"
+  -
+    input:
+      bytes: [ 0x3b, 0x00, 0x02, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d0, #0x20"
+  -
+    input:
+      bytes: [ 0x8f, 0x1a, 0x40, 0xa1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or d10, d10, #0x1"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xbd, 0xf9 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0xc86"
+  -
+    input:
+      bytes: [ 0x3f, 0x40, 0xe3, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt.u d0, d4, #-0x3a"
+  -
+    input:
+      bytes: [ 0x0b, 0x20, 0x50, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ge.u d15, d0, d2"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x6b, 0x4b ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x1692a"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xdc, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x13b8"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xaa, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0xac"
+  -
+    input:
+      bytes: [ 0x5f, 0x10, 0x09, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d0, d1, #0x12"
+  -
+    input:
+      bytes: [ 0xa2, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub d0, d1"
+  -
+    input:
+      bytes: [ 0x5f, 0xef, 0x67, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d14, #0xce"
+  -
+    input:
+      bytes: [ 0x49, 0xa5, 0x00, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a5, [sp]#0"
+  -
+    input:
+      bytes: [ 0xdf, 0x0c, 0x86, 0x7f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d12, #0, #-0xf4"
+  -
+    input:
+      bytes: [ 0x4e, 0x33 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jgtz d3, #0x6"
+  -
+    input:
+      bytes: [ 0x09, 0xff, 0xb6, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.h d15, [a15]#0x36"
+  -
+    input:
+      bytes: [ 0x3f, 0xf2, 0x05, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt d2, d15, #0xa"
+  -
+    input:
+      bytes: [ 0x3b, 0x80, 0x3e, 0x40 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d4, #0x3e8"
+  -
+    input:
+      bytes: [ 0x76, 0x8e ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d8, #0x1c"
+  -
+    input:
+      bytes: [ 0x3c, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x14"
+  -
+    input:
+      bytes: [ 0x6e, 0x21 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d15, #0x42"
+  -
+    input:
+      bytes: [ 0xdf, 0x1f, 0xf3, 0x7f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, #0x1, #-0x1a"
+  -
+    input:
+      bytes: [ 0x46, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "not d6"
+  -
+    input:
+      bytes: [ 0x61, 0xff, 0xfb, 0xd8 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcall #-0x4e0a"
+  -
+    input:
+      bytes: [ 0x82, 0x19 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d9, #0x1"
+  -
+    input:
+      bytes: [ 0xae, 0x13 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz.t d15, #0x1, #0x6"
+  -
+    input:
+      bytes: [ 0x4b, 0x0f, 0x41, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.f d1, d15, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x12, 0x80, 0x20 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addx d2, d2, #0x1"
+  -
+    input:
+      bytes: [ 0x49, 0xa4, 0x04, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a4, [sp]#0x4"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x84, 0xfa ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0xaf8"
+  -
+    input:
+      bytes: [ 0xa6, 0xf2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or d2, d15"
+  -
+    input:
+      bytes: [ 0x40, 0xc5 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.aa a5, a12"
+  -
+    input:
+      bytes: [ 0xda, 0x2b ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d15, #0x2b"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0x71, 0x61 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ftouz d6, d0"
+  -
+    input:
+      bytes: [ 0xd9, 0x55, 0x6c, 0x2a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a5, [a5]#-0x5b54"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0xc4, 0x31 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0x1cc4"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x32, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x64"
+  -
+    input:
+      bytes: [ 0x91, 0x20, 0x00, 0x28 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a2, #0x8002"
+  -
+    input:
+      bytes: [ 0x8f, 0x00, 0x21, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha d1, d0, #0x10"
+  -
+    input:
+      bytes: [ 0x40, 0x5c ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.aa a12, a5"
+  -
+    input:
+      bytes: [ 0x02, 0x79 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d9, d7"
+  -
+    input:
+      bytes: [ 0xac, 0xfc ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [a15]#0x18, d15"
+  -
+    input:
+      bytes: [ 0x6f, 0x3f, 0x37, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.t d15, #0x3, #0x6e"
+  -
+    input:
+      bytes: [ 0x6f, 0x29, 0x19, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.t d9, #0x2, #0x32"
+  -
+    input:
+      bytes: [ 0x40, 0xc4 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.aa a4, a12"
+  -
+    input:
+      bytes: [ 0x3f, 0x8b, 0xe7, 0x7f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt d11, d8, #-0x32"
+  -
+    input:
+      bytes: [ 0x26, 0x53 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d3, d5"
+  -
+    input:
+      bytes: [ 0xb7, 0x0f, 0x81, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, #0, #0x1, #0x1"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0xf0, 0xaa ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#-0x5150"
+  -
+    input:
+      bytes: [ 0xc2, 0xfa ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d10, #-0x1"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x69, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x2d2"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0x28, 0xa6 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0x62a8"
+  -
+    input:
+      bytes: [ 0x91, 0x30, 0x00, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a15, #0xf003"
+  -
+    input:
+      bytes: [ 0x6f, 0x3f, 0x2f, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.t d15, #0x3, #0x5e"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x44, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x888"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xd0, 0xf8 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0xe60"
+  -
+    input:
+      bytes: [ 0x37, 0x04, 0x50, 0x40 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr d4, d4, #0, #0x10"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x9d, 0x2d ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x1a4c6"
+  -
+    input:
+      bytes: [ 0x8b, 0xc8, 0x01, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d0, d8, #0x1c"
+  -
+    input:
+      bytes: [ 0xbb, 0x90, 0xff, 0x0f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.u d0, #0xfff9"
+  -
+    input:
+      bytes: [ 0x89, 0xff, 0xa2, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [a15]#0x22, d15"
+  -
+    input:
+      bytes: [ 0xff, 0x28, 0xf6, 0x7f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jge d8, #0x2, #-0x14"
+  -
+    input:
+      bytes: [ 0x01, 0xcf, 0x20, 0x20 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub.a a2, a15, a12"
+  -
+    input:
+      bytes: [ 0x3c, 0x16 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x2c"
+  -
+    input:
+      bytes: [ 0x0b, 0x8f, 0x10, 0x48 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov e4, d15, d8"
+  -
+    input:
+      bytes: [ 0xa6, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or d2, d0"
+  -
+    input:
+      bytes: [ 0x8f, 0xff, 0x83, 0x41 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor d4, d15, #0x3f"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0x8c, 0xea ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#-0x5474"
+  -
+    input:
+      bytes: [ 0x8b, 0x0d, 0x00, 0xf5 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.ne d15, d13, #0"
+  -
+    input:
+      bytes: [ 0x49, 0x33, 0x08, 0x8a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a3, [a3]#-0x1f8"
+  -
+    input:
+      bytes: [ 0x57, 0x0f, 0x61, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d15, d15, d0, #0x1"
+  -
+    input:
+      bytes: [ 0x4b, 0x0f, 0x51, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "div.f d0, d15, d0"
+  -
+    input:
+      bytes: [ 0x2e, 0x38 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.t d15, #0x3, #0x10"
+  -
+    input:
+      bytes: [ 0xde, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, #0x1, #0x20"
+  -
+    input:
+      bytes: [ 0x37, 0x0f, 0x68, 0x40 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d4, d15, #0, #0x8"
+  -
+    input:
+      bytes: [ 0x82, 0x1b ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d11, #0x1"
+  -
+    input:
+      bytes: [ 0x7d, 0xc2, 0x05, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne.a a2, a12, #0xa"
+  -
+    input:
+      bytes: [ 0x2e, 0x26 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.t d15, #0x2, #0xc"
+  -
+    input:
+      bytes: [ 0x0b, 0x75, 0xa0, 0xf2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.lt.u d15, d5, d7"
+  -
+    input:
+      bytes: [ 0x3f, 0xf1, 0x0a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt d1, d15, #0x14"
+  -
+    input:
+      bytes: [ 0x02, 0x95 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d5, d9"
+  -
+    input:
+      bytes: [ 0xda, 0x17 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d15, #0x17"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x46, 0xfc ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x774"
+  -
+    input:
+      bytes: [ 0x49, 0xdd, 0x10, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a13, [a13]#0x10"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0x38, 0x20 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0xb8"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x24, 0x1a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x3448"
+  -
+    input:
+      bytes: [ 0x3f, 0xbf, 0xf8, 0x7f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt d15, d11, #-0x10"
+  -
+    input:
+      bytes: [ 0xbd, 0x0c, 0x79, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.a a12, #0xf2"
+  -
+    input:
+      bytes: [ 0x0b, 0x2f, 0xa0, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "max d15, d15, d2"
+  -
+    input:
+      bytes: [ 0x1d, 0x00, 0x08, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x10"
+  -
+    input:
+      bytes: [ 0x4b, 0x10, 0x41, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.f d0, d0, d1"
+  -
+    input:
+      bytes: [ 0xd9, 0xee, 0x08, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a14, [a14]#0x3c8"
+  -
+    input:
+      bytes: [ 0xdf, 0x2d, 0x05, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d13, #0x2, #0xa"
+  -
+    input:
+      bytes: [ 0xa6, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or d0, d15"
+  -
+    input:
+      bytes: [ 0x6e, 0x2d ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d15, #0x5a"
+  -
+    input:
+      bytes: [ 0x4b, 0x0f, 0x71, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ftouz d15, d15"
+  -
+    input:
+      bytes: [ 0xbb, 0x00, 0xc2, 0xfb ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.u d15, #0xbc20"
+  -
+    input:
+      bytes: [ 0x8b, 0xff, 0x00, 0x40 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d4, d15, #0xf"
+  -
+    input:
+      bytes: [ 0x7f, 0x0f, 0x04, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jge.u d15, d0, #0x8"
+  -
+    input:
+      bytes: [ 0x4b, 0x0a, 0x41, 0xa0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.f d10, d10, d0"
+  -
+    input:
+      bytes: [ 0x61, 0xff, 0x77, 0xda ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcall #-0x4b12"
+  -
+    input:
+      bytes: [ 0x3c, 0xfe ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #-0x4"
+  -
+    input:
+      bytes: [ 0xee, 0x37 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz d15, #0x6e"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x33, 0xfe ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x39a"
+  -
+    input:
+      bytes: [ 0x8f, 0x21, 0x20, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha d15, d1, #0x2"
+  -
+    input:
+      bytes: [ 0xb0, 0xfc ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add.a a12, #-0x1"
+  -
+    input:
+      bytes: [ 0x61, 0xff, 0x41, 0xd9 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcall #-0x4d7e"
+  -
+    input:
+      bytes: [ 0x8b, 0x1f, 0xe0, 0x26 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.eq d2, d15, #0x1"
+  -
+    input:
+      bytes: [ 0xdf, 0x1f, 0xfe, 0x7f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, #0x1, #-0x4"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x15, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x82a"
+  -
+    input:
+      bytes: [ 0xdf, 0x02, 0xf9, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d2, #0, #-0xe"
+  -
+    input:
+      bytes: [ 0x82, 0x2d ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d13, #0x2"
+  -
+    input:
+      bytes: [ 0x91, 0x10, 0x00, 0xf5 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a15, #0x5001"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x1b, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x1ca"
+  -
+    input:
+      bytes: [ 0x49, 0xaf, 0x0b, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [sp]#0xb"
+  -
+    input:
+      bytes: [ 0x3e, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d0, #0xe"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xa7, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x114e"
+  -
+    input:
+      bytes: [ 0x8b, 0x14, 0x1f, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d0, d4, #-0xf"
+  -
+    input:
+      bytes: [ 0x2e, 0x0f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.t d15, #0, #0x1e"
+  -
+    input:
+      bytes: [ 0xda, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d15, #0x7"
+  -
+    input:
+      bytes: [ 0x40, 0xc6 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.aa a6, a12"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xa0, 0xfa ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0xac0"
+  -
+    input:
+      bytes: [ 0x15, 0xd0, 0xc0, 0xf7 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "stucx #0xd0003fc0"
+  -
+    input:
+      bytes: [ 0x4b, 0xf1, 0x01, 0x22 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "div e2, d1, d15"
+  -
+    input:
+      bytes: [ 0xa2, 0x5f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub d15, d5"
+  -
+    input:
+      bytes: [ 0x76, 0x29 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d2, #0x12"
+  -
+    input:
+      bytes: [ 0xfc, 0xf6 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "loop a15, #-0x14"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xe0, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0xbc0"
+  -
+    input:
+      bytes: [ 0x8f, 0x80, 0x20, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha d1, d0, #0x8"
+  -
+    input:
+      bytes: [ 0x3e, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d0, #0x8"
+  -
+    input:
+      bytes: [ 0x6d, 0xe8, 0x3d, 0x22 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x2fbb86"
+  -
+    input:
+      bytes: [ 0xc2, 0xfb ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d11, #-0x1"
+  -
+    input:
+      bytes: [ 0x0b, 0x15, 0x80, 0xf2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.ne d15, d5, d1"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x73, 0x0f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x1ee6"
+  -
+    input:
+      bytes: [ 0x3b, 0xc0, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d0, #0xc"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0x50, 0xea ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#-0x5870"
+  -
+    input:
+      bytes: [ 0xd9, 0x55, 0x7c, 0x4a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a5, [a5]#-0x5ac4"
+  -
+    input:
+      bytes: [ 0x6f, 0x10, 0xf8, 0x7f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.t d0, #0x1, #-0x10"
+  -
+    input:
+      bytes: [ 0x0f, 0xcb, 0x10, 0xb0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha d11, d11, d12"
+  -
+    input:
+      bytes: [ 0x32, 0x5a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "rsub d10"
+  -
+    input:
+      bytes: [ 0x8b, 0x01, 0x20, 0xf2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ne d15, d1, #0"
+  -
+    input:
+      bytes: [ 0x3f, 0x0f, 0xfd, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt.u d15, d0, #-0x6"
+  -
+    input:
+      bytes: [ 0x3f, 0xf9, 0x65, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt.u d9, d15, #-0x136"
+  -
+    input:
+      bytes: [ 0x20, 0x50 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub.a sp, #0x50"
+  -
+    input:
+      bytes: [ 0xe2, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul d0, d15"
+  -
+    input:
+      bytes: [ 0xff, 0x18, 0xe9, 0x7f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jge d8, #0x1, #-0x2e"
+  -
+    input:
+      bytes: [ 0xd9, 0x44, 0x14, 0x7d ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a4, [a4]#-0x2e2c"
+  -
+    input:
+      bytes: [ 0xd9, 0x44, 0xec, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a4, [a4]#0xc6c"
+  -
+    input:
+      bytes: [ 0x3b, 0x10, 0x06, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d0, #0x61"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xf2, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x5e4"
+  -
+    input:
+      bytes: [ 0xbc, 0x26 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.a a2, #0xc"
+  -
+    input:
+      bytes: [ 0x01, 0xca, 0x00, 0x56 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addsc.a a5, a12, d10, #0"
+  -
+    input:
+      bytes: [ 0x7f, 0x0f, 0x55, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jge d15, d0, #0xaa"
+  -
+    input:
+      bytes: [ 0x8f, 0x4f, 0x1f, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh d1, d15, #-0xc"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x9e, 0x4c ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x166c4"
+  -
+    input:
+      bytes: [ 0x6e, 0x55 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d15, #0xaa"
+  -
+    input:
+      bytes: [ 0x46, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "not d7"
+  -
+    input:
+      bytes: [ 0xa6, 0x2f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or d15, d2"
+  -
+    input:
+      bytes: [ 0x7f, 0x89, 0x08, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jge d9, d8, #0x10"
+  -
+    input:
+      bytes: [ 0x0f, 0x02, 0x00, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh d15, d2, d0"
+  -
+    input:
+      bytes: [ 0x6e, 0x12 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d15, #0x24"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x2d, 0x0e ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x1c5a"
+  -
+    input:
+      bytes: [ 0x10, 0xcf ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addsc.a a15, a12, d15, #0"
+  -
+    input:
+      bytes: [ 0x3f, 0x21, 0xf9, 0x7f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt d1, d2, #-0xe"
+  -
+    input:
+      bytes: [ 0x06, 0x50 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh d0, #0x5"
+  -
+    input:
+      bytes: [ 0xbf, 0xc0, 0xea, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt.u d0, #0xc, #-0x2c"
+  -
+    input:
+      bytes: [ 0x3e, 0x12 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d1, #0x4"
+  -
+    input:
+      bytes: [ 0x06, 0x15 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh d5, #0x1"
+  -
+    input:
+      bytes: [ 0x53, 0x48, 0x20, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul d15, d8, #0x4"
+  -
+    input:
+      bytes: [ 0x3e, 0xeb ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d14, #0x16"
+  -
+    input:
+      bytes: [ 0xbb, 0x00, 0x40, 0x2f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.u d2, #0xf400"
+  -
+    input:
+      bytes: [ 0x3f, 0xf2, 0xf3, 0x7f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt d2, d15, #-0x1a"
+  -
+    input:
+      bytes: [ 0x3b, 0xb0, 0x02, 0x40 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d4, #0x2b"
+  -
+    input:
+      bytes: [ 0x37, 0x01, 0x10, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d1, d1, d0, #0, #0x10"
+  -
+    input:
+      bytes: [ 0x49, 0xfc, 0x3f, 0x2a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a12, [a15]#0xbf"
+  -
+    input:
+      bytes: [ 0xac, 0x44 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [a4]#0x8, d15"
+  -
+    input:
+      bytes: [ 0xd9, 0x22, 0x1a, 0x21 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a2, [a2]#0x109a"
+  -
+    input:
+      bytes: [ 0x37, 0x0f, 0x81, 0xf2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, d0, #0x5, #0x1"
+  -
+    input:
+      bytes: [ 0x02, 0x2a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d10, d2"
+  -
+    input:
+      bytes: [ 0xa2, 0xaf ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub d15, d10"
+  -
+    input:
+      bytes: [ 0x6e, 0xc9 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d15, #-0x6e"
+  -
+    input:
+      bytes: [ 0x0b, 0x31, 0x00, 0xf2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.eq d15, d1, d3"
+  -
+    input:
+      bytes: [ 0x02, 0xb2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d2, d11"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0x30, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0x70"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0xb4, 0xe1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0x1bb4"
+  -
+    input:
+      bytes: [ 0x4b, 0x80, 0x11, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "div.u e0, d0, d8"
+  -
+    input:
+      bytes: [ 0x37, 0x0f, 0x01, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, d0, #0, #0x1"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0xf8, 0xea ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#-0x5048"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xf7, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x1ee"
+  -
+    input:
+      bytes: [ 0xb0, 0x1d ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add.a a13, #0x1"
+  -
+    input:
+      bytes: [ 0x16, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d15, #0x2"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xc6, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x74"
+  -
+    input:
+      bytes: [ 0x3c, 0x2f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x5e"
+  -
+    input:
+      bytes: [ 0xfc, 0x29 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "loop a2, #-0xe"
+  -
+    input:
+      bytes: [ 0xa0, 0x15 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.a a5, #0x1"
+  -
+    input:
+      bytes: [ 0x5f, 0x0f, 0x5d, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, d0, #0xba"
+  -
+    input:
+      bytes: [ 0x20, 0x18 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub.a sp, #0x18"
+  -
+    input:
+      bytes: [ 0x6b, 0x05, 0x00, 0x20 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "pack d2, e0, d5"
+  -
+    input:
+      bytes: [ 0x07, 0xbb, 0x9f, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "nand.t d15, d11, #0x1f, d11, #0x1f"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x93, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x1126"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xe8, 0x0d ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x1bd0"
+  -
+    input:
+      bytes: [ 0x82, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d2, #0"
+  -
+    input:
+      bytes: [ 0x7d, 0x42, 0x0f, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne.a a2, a4, #0x1e"
+  -
+    input:
+      bytes: [ 0xac, 0xfa ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [a15]#0x14, d15"
+  -
+    input:
+      bytes: [ 0x6e, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d15, #0x8"
+  -
+    input:
+      bytes: [ 0xdf, 0x08, 0xf9, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d8, #0, #-0xe"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xca, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x2194"
+  -
+    input:
+      bytes: [ 0x4b, 0xf8, 0x01, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "div e0, d8, d15"
+  -
+    input:
+      bytes: [ 0x02, 0x2f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d15, d2"
+  -
+    input:
+      bytes: [ 0xa0, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.a a4, #0"
+  -
+    input:
+      bytes: [ 0x0f, 0x0a, 0x80, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d1, d10, d0"
+  -
+    input:
+      bytes: [ 0x0f, 0xcf, 0x00, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh d15, d15, d12"
+  -
+    input:
+      bytes: [ 0x8b, 0x05, 0xc0, 0xfa ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "eqany.b d15, d5, #0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x20, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ne d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x7d, 0x2e, 0x0c, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne.a a14, a2, #0x18"
+  -
+    input:
+      bytes: [ 0x6f, 0x29, 0x68, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.t d9, #0x2, #0xd0"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x5f, 0xfc ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x742"
+  -
+    input:
+      bytes: [ 0x91, 0x00, 0x00, 0x57 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a5, #0x7000"
+  -
+    input:
+      bytes: [ 0x91, 0x00, 0x00, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a8, #0"
+  -
+    input:
+      bytes: [ 0xc2, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d15, #-0x1"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x3b, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0xa76"
+  -
+    input:
+      bytes: [ 0x3c, 0xd9 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #-0x4e"
+  -
+    input:
+      bytes: [ 0x7e, 0xe5 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, d14, #0xa"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x3f, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x182"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x5e, 0x0f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x1ebc"
+  -
+    input:
+      bytes: [ 0x96, 0x40 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or d15, #0x40"
+  -
+    input:
+      bytes: [ 0x37, 0x01, 0x70, 0x20 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d2, d1, #0, #0x10"
+  -
+    input:
+      bytes: [ 0x1e, 0xf4 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, #-0x1, #0x8"
+  -
+    input:
+      bytes: [ 0x76, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d0, #0x6"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x50, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x2a0"
+  -
+    input:
+      bytes: [ 0x0b, 0x1b, 0x90, 0xf2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.lt d15, d11, d1"
+  -
+    input:
+      bytes: [ 0x80, 0xdf ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.d d15, a13"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0x00, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#-0x6000"
+  -
+    input:
+      bytes: [ 0x37, 0x00, 0xe1, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d0, d0, #0x1, #0x1"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0x1c, 0x30 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0xdc"
+  -
+    input:
+      bytes: [ 0x02, 0x4f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d15, d4"
+  -
+    input:
+      bytes: [ 0x91, 0x20, 0x00, 0x58 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a5, #0x8002"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x4c, 0xfb ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x968"
+  -
+    input:
+      bytes: [ 0x3b, 0x00, 0x00, 0xf3 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d15, #0x3000"
+  -
+    input:
+      bytes: [ 0x37, 0xf0, 0x01, 0xf3 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d0, d15, #0x6, #0x1"
+  -
+    input:
+      bytes: [ 0x4b, 0x02, 0x41, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.f d15, d2, d0"
+  -
+    input:
+      bytes: [ 0xc6, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor d0, d15"
+  -
+    input:
+      bytes: [ 0x6e, 0x19 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d15, #0x32"
+  -
+    input:
+      bytes: [ 0x76, 0x55 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d5, #0xa"
+  -
+    input:
+      bytes: [ 0x42, 0xf4 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d4, d15"
+  -
+    input:
+      bytes: [ 0xee, 0xd2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz d15, #-0x5c"
+  -
+    input:
+      bytes: [ 0x5e, 0x26 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, #0x2, #0xc"
+  -
+    input:
+      bytes: [ 0x3c, 0x13 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x26"
+  -
+    input:
+      bytes: [ 0x10, 0xf2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addsc.a a2, a15, d15, #0"
+  -
+    input:
+      bytes: [ 0x2d, 0x07, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "calli a7"
+  -
+    input:
+      bytes: [ 0x6f, 0x2f, 0x17, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.t d15, #0x2, #0x2e"
+  -
+    input:
+      bytes: [ 0x4b, 0xf5, 0x41, 0x30 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.f d3, d5, d15"
+  -
+    input:
+      bytes: [ 0x3c, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0xe"
+  -
+    input:
+      bytes: [ 0x7f, 0x0f, 0x4d, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jge d15, d0, #0x9a"
+  -
+    input:
+      bytes: [ 0xa6, 0x0f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or d15, d0"
+  -
+    input:
+      bytes: [ 0x89, 0x4f, 0xb4, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [a4]#0x34, d15"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xbd, 0x0e ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x1d7a"
+  -
+    input:
+      bytes: [ 0x91, 0x00, 0x06, 0xf8 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a15, #0x8060"
+  -
+    input:
+      bytes: [ 0xdf, 0x12, 0x11, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d2, #0x1, #0x22"
+  -
+    input:
+      bytes: [ 0x0b, 0x0a, 0x10, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ne d15, d10, d0"
+  -
+    input:
+      bytes: [ 0x3c, 0x4c ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x98"
+  -
+    input:
+      bytes: [ 0xda, 0x1b ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d15, #0x1b"
+  -
+    input:
+      bytes: [ 0xbb, 0xf0, 0xf7, 0x4f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.u d4, #0xff7f"
+  -
+    input:
+      bytes: [ 0x26, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d1, d15"
+  -
+    input:
+      bytes: [ 0xbd, 0x04, 0x11, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.a a4, #0x22"
+  -
+    input:
+      bytes: [ 0x26, 0x82 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d2, d8"
+  -
+    input:
+      bytes: [ 0xc2, 0x11 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d1, #0x1"
+  -
+    input:
+      bytes: [ 0x4b, 0x06, 0x61, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "utof d0, d6"
+  -
+    input:
+      bytes: [ 0x3f, 0xf8, 0xf3, 0x7f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt d8, d15, #-0x1a"
+  -
+    input:
+      bytes: [ 0x37, 0xf0, 0x02, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d0, d0, d15, #0xc, #0x2"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xb0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x160"
+  -
+    input:
+      bytes: [ 0x3b, 0xf0, 0x06, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d0, #0x6f"
+  -
+    input:
+      bytes: [ 0x4b, 0xf2, 0x51, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "div.f d8, d2, d15"
+  -
+    input:
+      bytes: [ 0x37, 0x09, 0x68, 0x90 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d9, d9, #0, #0x8"
+  -
+    input:
+      bytes: [ 0xa2, 0x2f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub d15, d2"
+  -
+    input:
+      bytes: [ 0x3c, 0x45 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x8a"
+  -
+    input:
+      bytes: [ 0x5e, 0xf5 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, #-0x1, #0xa"
+  -
+    input:
+      bytes: [ 0x10, 0x24 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addsc.a a4, a2, d15, #0"
+  -
+    input:
+      bytes: [ 0x7e, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, d0, #0x8"
+  -
+    input:
+      bytes: [ 0xda, 0x2d ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d15, #0x2d"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x4d, 0xfa ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0xb66"
+  -
+    input:
+      bytes: [ 0xdf, 0x0c, 0x9b, 0x7f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d12, #0, #-0xca"
+  -
+    input:
+      bytes: [ 0x40, 0x54 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.aa a4, a5"
+  -
+    input:
+      bytes: [ 0x4b, 0xf9, 0x41, 0x50 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.f d5, d9, d15"
+  -
+    input:
+      bytes: [ 0xd9, 0xee, 0x14, 0xe0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a14, [a14]#0x394"
+  -
+    input:
+      bytes: [ 0x8b, 0x08, 0x08, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "rsub d15, d8, #0x80"
+  -
+    input:
+      bytes: [ 0x01, 0xcd, 0x00, 0xc6 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addsc.a a12, a12, d13, #0"
+  -
+    input:
+      bytes: [ 0xd9, 0x55, 0xa8, 0xca ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a5, [a5]#-0x54d8"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x16, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x2c"
+  -
+    input:
+      bytes: [ 0xb7, 0x6f, 0x08, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, #0x6, #0, #0x8"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x07, 0xd5 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x55f2"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x00, 0x48 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov e4, d0"
+  -
+    input:
+      bytes: [ 0x49, 0xa5, 0x04, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a5, [sp]#0x4"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0x00, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0x200"
+  -
+    input:
+      bytes: [ 0x40, 0xef ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.aa a15, a14"
+  -
+    input:
+      bytes: [ 0x6e, 0x65 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d15, #0xca"
+  -
+    input:
+      bytes: [ 0xfa, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lt d15, d0, #0x1"
+  -
+    input:
+      bytes: [ 0x26, 0x0f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d15, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x60, 0x30, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lt.u d15, d0, d6"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xf2, 0x11 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x23e4"
+  -
+    input:
+      bytes: [ 0x49, 0xaa, 0x38, 0xba ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea sp, [sp]#-0x108"
+  -
+    input:
+      bytes: [ 0x0b, 0x51, 0x00, 0xf2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.eq d15, d1, d5"
+  -
+    input:
+      bytes: [ 0x0f, 0x13, 0x00, 0x30 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh d3, d3, d1"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0x14, 0x30 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0xd4"
+  -
+    input:
+      bytes: [ 0x3f, 0x0f, 0xeb, 0x7f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt d15, d0, #-0x2a"
+  -
+    input:
+      bytes: [ 0xb7, 0x04, 0x89, 0x0b ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d0, d4, #0, #0x17, #0x9"
+  -
+    input:
+      bytes: [ 0xb7, 0x5f, 0x08, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, #0x5, #0, #0x8"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x09, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x12"
+  -
+    input:
+      bytes: [ 0x0b, 0x60, 0x40, 0x40 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addx d4, d0, d6"
+  -
+    input:
+      bytes: [ 0xbe, 0x0d ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d0, #0x3a"
+  -
+    input:
+      bytes: [ 0x8b, 0xf0, 0x1b, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d15, d0, #-0x41"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x8e, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x31c"
+  -
+    input:
+      bytes: [ 0x1d, 0xff, 0xbe, 0xfd ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #-0x484"
+  -
+    input:
+      bytes: [ 0xd9, 0x44, 0xe8, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a4, [a4]#0xc68"
+  -
+    input:
+      bytes: [ 0x8f, 0x8f, 0x01, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d0, d15, #0x18"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0x80, 0xea ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#-0x5480"
+  -
+    input:
+      bytes: [ 0x26, 0xf9 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d9, d15"
+  -
+    input:
+      bytes: [ 0x6f, 0x20, 0xf2, 0x7f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.t d0, #0x2, #-0x1c"
+  -
+    input:
+      bytes: [ 0x4b, 0xaf, 0x01, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmp.f d15, d15, d10"
+  -
+    input:
+      bytes: [ 0x8b, 0x07, 0xa0, 0x70 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addc d7, d7, #0"
+  -
+    input:
+      bytes: [ 0x49, 0xa5, 0x00, 0x4a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a5, [sp]#0x100"
+  -
+    input:
+      bytes: [ 0xdf, 0x10, 0x0a, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d0, #0x1, #0x14"
+  -
+    input:
+      bytes: [ 0x1d, 0x00, 0x98, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x130"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0x41, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "itof d0, d0"
+  -
+    input:
+      bytes: [ 0x3b, 0xd0, 0x02, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d8, #0x2d"
+  -
+    input:
+      bytes: [ 0x02, 0xb1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d1, d11"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x0a, 0x11 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x2214"
+  -
+    input:
+      bytes: [ 0x3b, 0xf0, 0x0f, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d0, #0xff"
+  -
+    input:
+      bytes: [ 0x40, 0xa2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.aa a2, sp"
+  -
+    input:
+      bytes: [ 0xc2, 0x1b ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d11, #0x1"
+  -
+    input:
+      bytes: [ 0xdf, 0x0f, 0xb1, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, #0, #0x162"
+  -
+    input:
+      bytes: [ 0xc2, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d1, #-0x1"
+  -
+    input:
+      bytes: [ 0x89, 0xaf, 0xa2, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [sp]#0x22, d15"
+  -
+    input:
+      bytes: [ 0x3b, 0x40, 0x07, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d0, #0x74"
+  -
+    input:
+      bytes: [ 0xdf, 0x12, 0x03, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d2, #0x1, #0x6"
+  -
+    input:
+      bytes: [ 0x3c, 0x6e ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0xdc"
+  -
+    input:
+      bytes: [ 0x82, 0x11 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d1, #0x1"
+  -
+    input:
+      bytes: [ 0x7c, 0x23 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz.a a2, #0x6"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x80, 0x4c ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x16700"
+  -
+    input:
+      bytes: [ 0x3b, 0x00, 0x00, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d0, #0x6000"
+  -
+    input:
+      bytes: [ 0x37, 0xf0, 0x01, 0x0f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d0, d0, d15, #0x1e, #0x1"
+  -
+    input:
+      bytes: [ 0x37, 0x00, 0x70, 0xa0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d10, d0, #0, #0x10"
+  -
+    input:
+      bytes: [ 0xac, 0xf8 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [a15]#0x10, d15"
+  -
+    input:
+      bytes: [ 0x16, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d15, #0x7"
+  -
+    input:
+      bytes: [ 0x7b, 0x00, 0x20, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh d0, #0x4200"
+  -
+    input:
+      bytes: [ 0x5f, 0x0f, 0xf4, 0x7f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d0, #-0x18"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xd6, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x5ac"
+  -
+    input:
+      bytes: [ 0xbb, 0x80, 0x02, 0x4a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.u d4, #0xa028"
+  -
+    input:
+      bytes: [ 0x02, 0x69 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d9, d6"
+  -
+    input:
+      bytes: [ 0x3e, 0x24 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d2, #0x8"
+  -
+    input:
+      bytes: [ 0x37, 0x00, 0xe7, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d0, d0, #0x1, #0x7"
+  -
+    input:
+      bytes: [ 0x8b, 0x0f, 0x1d, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d0, d15, #-0x30"
+  -
+    input:
+      bytes: [ 0x8f, 0x0a, 0x41, 0xa1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or d10, d10, #0x10"
+  -
+    input:
+      bytes: [ 0xdf, 0x02, 0xf8, 0x7f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d2, #0, #-0x10"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xf4, 0x0d ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x1be8"
+  -
+    input:
+      bytes: [ 0x37, 0x03, 0x68, 0xf4 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d15, d3, #0x8, #0x8"
+  -
+    input:
+      bytes: [ 0x37, 0x01, 0xe1, 0x17 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d1, d1, #0xf, #0x1"
+  -
+    input:
+      bytes: [ 0xbb, 0x00, 0x20, 0x4c ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.u d4, #0xc200"
+  -
+    input:
+      bytes: [ 0xac, 0x49 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [a4]#0x12, d15"
+  -
+    input:
+      bytes: [ 0x3c, 0x29 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x52"
+  -
+    input:
+      bytes: [ 0x49, 0xaf, 0x0a, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [sp]#0xa"
+  -
+    input:
+      bytes: [ 0x53, 0x20, 0x20, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul d15, d0, #0x2"
+  -
+    input:
+      bytes: [ 0x37, 0x00, 0xe1, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d0, d0, #0xf, #0x1"
+  -
+    input:
+      bytes: [ 0x09, 0x44, 0x94, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.h d4, [a4]#0x14"
+  -
+    input:
+      bytes: [ 0x01, 0x24, 0x00, 0x46 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addsc.a a4, a2, d4, #0"
+  -
+    input:
+      bytes: [ 0x8b, 0xff, 0x0f, 0xc2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "eq d12, d15, #0xff"
+  -
+    input:
+      bytes: [ 0x37, 0x09, 0x70, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d0, d9, #0, #0x10"
+  -
+    input:
+      bytes: [ 0xfd, 0xf0, 0xed, 0x7f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "loop a15, #-0x26"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xb0, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x760"
+  -
+    input:
+      bytes: [ 0xda, 0x75 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d15, #0x75"
+  -
+    input:
+      bytes: [ 0x9b, 0xe2, 0xcb, 0x24 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addih d2, d2, #0x4cbe"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x11, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x22"
+  -
+    input:
+      bytes: [ 0x37, 0xf0, 0x08, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d0, d15, #0, #0x8"
+  -
+    input:
+      bytes: [ 0x46, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "not d0"
+  -
+    input:
+      bytes: [ 0x26, 0x93 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d3, d9"
+  -
+    input:
+      bytes: [ 0x6e, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d15, #0xe"
+  -
+    input:
+      bytes: [ 0xdf, 0x0a, 0x33, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d10, #0, #0x66"
+  -
+    input:
+      bytes: [ 0xee, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz d15, #0xe"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xf3, 0xfe ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x21a"
+  -
+    input:
+      bytes: [ 0x09, 0xf0, 0xba, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.h d0, [a15]#0x3a"
+  -
+    input:
+      bytes: [ 0x8f, 0x14, 0x1e, 0x20 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh d2, d4, #-0x1f"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xb4, 0x0e ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x1d68"
+  -
+    input:
+      bytes: [ 0xee, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz d15, #0x14"
+  -
+    input:
+      bytes: [ 0x01, 0x54, 0x20, 0xf4 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lt.a d15, a4, a5"
+  -
+    input:
+      bytes: [ 0xdf, 0x08, 0x11, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d8, #0, #0x22"
+  -
+    input:
+      bytes: [ 0x8f, 0x23, 0x20, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha d15, d3, #0x2"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xdd, 0x2a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x1aa46"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xf8, 0x11 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x23f0"
+  -
+    input:
+      bytes: [ 0xee, 0x0b ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz d15, #0x16"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0x00, 0x30 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0xc0"
+  -
+    input:
+      bytes: [ 0xd9, 0x3f, 0x0c, 0x96 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a3]#0x624c"
+  -
+    input:
+      bytes: [ 0x26, 0x30 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d0, d3"
+  -
+    input:
+      bytes: [ 0x3c, 0x2b ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x56"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x25, 0xfe ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x3b6"
+  -
+    input:
+      bytes: [ 0x3f, 0x0f, 0xf6, 0x7f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt d15, d0, #-0x14"
+  -
+    input:
+      bytes: [ 0x3b, 0x00, 0x40, 0x41 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d4, #0x1400"
+  -
+    input:
+      bytes: [ 0x02, 0x51 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d1, d5"
+  -
+    input:
+      bytes: [ 0x46, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "not d2"
+  -
+    input:
+      bytes: [ 0xd9, 0x22, 0x32, 0x11 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a2, [a2]#0x1072"
+  -
+    input:
+      bytes: [ 0x06, 0xd5 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh d5, #-0x3"
+  -
+    input:
+      bytes: [ 0xdc, 0x0f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ji a15"
+  -
+    input:
+      bytes: [ 0x0b, 0x89, 0x10, 0x48 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov e4, d9, d8"
+  -
+    input:
+      bytes: [ 0x80, 0xcf ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.d d15, a12"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x28, 0x0f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x1e50"
+  -
+    input:
+      bytes: [ 0x76, 0x83 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d8, #0x6"
+  -
+    input:
+      bytes: [ 0x6d, 0xe8, 0xcf, 0x20 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x2fbe62"
+  -
+    input:
+      bytes: [ 0x76, 0xc5 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d12, #0xa"
+  -
+    input:
+      bytes: [ 0x3b, 0x10, 0x08, 0x40 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d4, #0x81"
+  -
+    input:
+      bytes: [ 0xda, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d15, #0x2"
+  -
+    input:
+      bytes: [ 0x13, 0xa9, 0x20, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd d15, d15, d9, #0xa"
+  -
+    input:
+      bytes: [ 0x49, 0xaa, 0x30, 0xba ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea sp, [sp]#-0x110"
+  -
+    input:
+      bytes: [ 0x40, 0xe2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.aa a2, a14"
+  -
+    input:
+      bytes: [ 0x9b, 0xc0, 0xdc, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addih d0, d0, #0x3dcc"
+  -
+    input:
+      bytes: [ 0x3e, 0x47 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d4, #0xe"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x76, 0xf9 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0xd14"
+  -
+    input:
+      bytes: [ 0xdf, 0x08, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d8, #0, #0x80"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x92, 0xfa ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0xadc"
+  -
+    input:
+      bytes: [ 0x09, 0xf0, 0xd4, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.hu d0, [a15]#0x14"
+  -
+    input:
+      bytes: [ 0x6e, 0x14 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d15, #0x28"
+  -
+    input:
+      bytes: [ 0xc2, 0x2b ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d11, #0x2"
+  -
+    input:
+      bytes: [ 0x6b, 0x0e, 0x21, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add.f d15, d15, d14"
+  -
+    input:
+      bytes: [ 0x3b, 0xf0, 0x0f, 0x40 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d4, #0xff"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0x08, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0x48"
+  -
+    input:
+      bytes: [ 0x6e, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d15, #0xa"
+  -
+    input:
+      bytes: [ 0x80, 0x20 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.d d0, a2"
+  -
+    input:
+      bytes: [ 0xd9, 0x44, 0xfc, 0xb5 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a4, [a4]#0x5efc"
+  -
+    input:
+      bytes: [ 0x61, 0xff, 0x86, 0xd4 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcall #-0x56f4"
+  -
+    input:
+      bytes: [ 0x89, 0x40, 0x94, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [a4]#0x14, d0"
+  -
+    input:
+      bytes: [ 0x6f, 0x8a, 0x45, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.t d10, #0x8, #0x8a"
+  -
+    input:
+      bytes: [ 0x5e, 0x2d ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, #0x2, #0x1a"
+  -
+    input:
+      bytes: [ 0x8b, 0xff, 0x01, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "rsub d15, d15, #0x1f"
+  -
+    input:
+      bytes: [ 0xdf, 0x00, 0x31, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d0, #0, #0x62"
+  -
+    input:
+      bytes: [ 0xbb, 0xb0, 0xff, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.u d15, #0xfffb"
+  -
+    input:
+      bytes: [ 0xd9, 0x55, 0x68, 0x1a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a5, [a5]#-0x5b98"
+  -
+    input:
+      bytes: [ 0x76, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d0, #0xa"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x7f, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0xfe"
+  -
+    input:
+      bytes: [ 0x40, 0x6f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.aa a15, a6"
+  -
+    input:
+      bytes: [ 0x61, 0xff, 0x95, 0xd4 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcall #-0x56d6"
+  -
+    input:
+      bytes: [ 0x3c, 0x0d ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x1a"
+  -
+    input:
+      bytes: [ 0xa2, 0xfc ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub d12, d15"
+  -
+    input:
+      bytes: [ 0x5f, 0x8f, 0xef, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d8, #0x1de"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x8a, 0x0d ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x1b14"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0x90, 0x9a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#-0x55b0"
+  -
+    input:
+      bytes: [ 0x82, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d8, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x64, 0x30, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lt.u d15, d4, d6"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x9f, 0x0d ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x1b3e"
+  -
+    input:
+      bytes: [ 0xa6, 0x93 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or d3, d9"
+  -
+    input:
+      bytes: [ 0x02, 0x28 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d8, d2"
+  -
+    input:
+      bytes: [ 0xda, 0x7e ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d15, #0x7e"
+  -
+    input:
+      bytes: [ 0x3c, 0x0e ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x1c"
+  -
+    input:
+      bytes: [ 0x3b, 0x30, 0x07, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d0, #0x73"
+  -
+    input:
+      bytes: [ 0xdf, 0x10, 0xee, 0x7f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d0, #0x1, #-0x24"
+  -
+    input:
+      bytes: [ 0x4b, 0xab, 0x01, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmp.f d15, d11, d10"
+  -
+    input:
+      bytes: [ 0x6f, 0x0f, 0xfc, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz.t d15, #0, #-0x8"
+  -
+    input:
+      bytes: [ 0x6f, 0x00, 0x1f, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz.t d0, #0, #0x3e"
+  -
+    input:
+      bytes: [ 0x6e, 0x0c ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d15, #0x18"
+  -
+    input:
+      bytes: [ 0x91, 0x00, 0x00, 0x90 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a9, #0"
+  -
+    input:
+      bytes: [ 0x10, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addsc.a a15, a15, d15, #0"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x98, 0xfd ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x4d0"
+  -
+    input:
+      bytes: [ 0x40, 0x7d ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.aa a13, a7"
+  -
+    input:
+      bytes: [ 0xd9, 0x55, 0x64, 0x3a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a5, [a5]#-0x5b1c"
+  -
+    input:
+      bytes: [ 0x91, 0x40, 0x00, 0x3f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a3, #0xf004"
+  -
+    input:
+      bytes: [ 0x37, 0x0f, 0xe1, 0xf3 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d15, d15, #0x7, #0x1"
+  -
+    input:
+      bytes: [ 0x8f, 0x28, 0x00, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh d15, d8, #0x2"
+  -
+    input:
+      bytes: [ 0x1d, 0x00, 0x5f, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x2be"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x32, 0xd5 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x559c"
+  -
+    input:
+      bytes: [ 0x37, 0x10, 0x01, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d0, d0, d1, #0x2, #0x1"
+  -
+    input:
+      bytes: [ 0x37, 0x02, 0x68, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d15, d2, #0, #0x8"
+  -
+    input:
+      bytes: [ 0x8b, 0x0c, 0x20, 0xf2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ne d15, d12, #0"
+  -
+    input:
+      bytes: [ 0x8b, 0x80, 0x00, 0x40 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d4, d0, #0x8"
+  -
+    input:
+      bytes: [ 0x46, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "not d5"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x9d, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0xc6"
+  -
+    input:
+      bytes: [ 0x26, 0x20 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d0, d2"
+  -
+    input:
+      bytes: [ 0x3a, 0x26 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "eq d15, d6, d2"
+  -
+    input:
+      bytes: [ 0x9b, 0xe0, 0xcb, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addih d0, d0, #0x4cbe"
+  -
+    input:
+      bytes: [ 0xfc, 0xe7 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "loop a14, #-0x12"
+  -
+    input:
+      bytes: [ 0x8f, 0x3f, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh d0, d15, #0x3"
+  -
+    input:
+      bytes: [ 0x37, 0x0f, 0x82, 0xf2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, d0, #0x5, #0x2"
+  -
+    input:
+      bytes: [ 0xc2, 0x1e ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d14, #0x1"
+  -
+    input:
+      bytes: [ 0x6e, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d15, #0x12"
+  -
+    input:
+      bytes: [ 0x3b, 0xe0, 0x06, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d0, #0x6e"
+  -
+    input:
+      bytes: [ 0x8c, 0x4b ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.h d15, [a4]#0x16"
+  -
+    input:
+      bytes: [ 0xb0, 0x42 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add.a a2, #0x4"
+  -
+    input:
+      bytes: [ 0x3b, 0x80, 0x06, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d0, #0x68"
+  -
+    input:
+      bytes: [ 0x0f, 0x0f, 0x10, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha d15, d15, d0"
+  -
+    input:
+      bytes: [ 0xbc, 0xfa ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.a a15, #0x14"
+  -
+    input:
+      bytes: [ 0x0b, 0x71, 0x50, 0xb0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addc d11, d1, d7"
+  -
+    input:
+      bytes: [ 0x42, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d4, d0"
+  -
+    input:
+      bytes: [ 0x7b, 0xa0, 0x47, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh d0, #0x447a"
+  -
+    input:
+      bytes: [ 0x0f, 0xf0, 0x10, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha d0, d0, d15"
+  -
+    input:
+      bytes: [ 0x8f, 0x3f, 0x00, 0x30 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh d3, d15, #0x3"
+  -
+    input:
+      bytes: [ 0x37, 0x00, 0x70, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d0, d0, #0x10, #0x10"
+  -
+    input:
+      bytes: [ 0x49, 0xa5, 0x10, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a5, [sp]#0x10"
+  -
+    input:
+      bytes: [ 0x37, 0x04, 0x68, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d0, d4, #0, #0x8"
+  -
+    input:
+      bytes: [ 0xda, 0x37 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d15, #0x37"
+  -
+    input:
+      bytes: [ 0xd9, 0x44, 0x4c, 0xb0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a4, [a4]#0x6cc"
+  -
+    input:
+      bytes: [ 0x20, 0x28 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub.a sp, #0x28"
+  -
+    input:
+      bytes: [ 0xb7, 0x0f, 0x01, 0xfc ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, #0, #0x18, #0x1"
+  -
+    input:
+      bytes: [ 0x49, 0x4f, 0x01, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a4]#0x1"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x91, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x122"
+  -
+    input:
+      bytes: [ 0xd9, 0x44, 0x34, 0x8b ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a4, [a4]#-0x4dcc"
+  -
+    input:
+      bytes: [ 0x4b, 0xfa, 0x51, 0xc0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "div.f d12, d10, d15"
+  -
+    input:
+      bytes: [ 0xee, 0x15 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz d15, #0x2a"
+  -
+    input:
+      bytes: [ 0x42, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d0, d15"
+  -
+    input:
+      bytes: [ 0x76, 0xc7 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d12, #0xe"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0x08, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0x8"
+  -
+    input:
+      bytes: [ 0x3f, 0x1f, 0x05, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt.u d15, d1, #0xa"
+  -
+    input:
+      bytes: [ 0xd9, 0x55, 0x34, 0xfa ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a5, [a5]#-0x5c0c"
+  -
+    input:
+      bytes: [ 0x76, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d0, #0x8"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xbd, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0xf7a"
+  -
+    input:
+      bytes: [ 0x6e, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d15, #0x14"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0x18, 0x60 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0x198"
+  -
+    input:
+      bytes: [ 0x40, 0x2c ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.aa a12, a2"
+  -
+    input:
+      bytes: [ 0x0b, 0x06, 0x10, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ne d15, d6, d0"
+  -
+    input:
+      bytes: [ 0x06, 0x13 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh d3, #0x1"
+  -
+    input:
+      bytes: [ 0xab, 0xf5, 0x3f, 0x55 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "caddn d5, d5, d5, #-0x1"
+  -
+    input:
+      bytes: [ 0x3b, 0xc0, 0x05, 0x50 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d5, #0x5c"
+  -
+    input:
+      bytes: [ 0x7e, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, d0, #0x10"
+  -
+    input:
+      bytes: [ 0x3f, 0x8f, 0xf8, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt.u d15, d8, #-0x10"
+  -
+    input:
+      bytes: [ 0x6d, 0xe8, 0xc9, 0x21 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x2fbc6e"
+  -
+    input:
+      bytes: [ 0x76, 0x8b ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d8, #0x16"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xb9, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x8e"
+  -
+    input:
+      bytes: [ 0x3b, 0xc0, 0xf9, 0x1f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d1, #-0x64"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0x08, 0x20 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0x88"
+  -
+    input:
+      bytes: [ 0xf6, 0x47 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz d4, #0xe"
+  -
+    input:
+      bytes: [ 0x0b, 0x45, 0x10, 0x68 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov e6, d5, d4"
+  -
+    input:
+      bytes: [ 0x40, 0x24 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.aa a4, a2"
+  -
+    input:
+      bytes: [ 0xa0, 0x64 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.a a4, #0x6"
+  -
+    input:
+      bytes: [ 0x94, 0xaf ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.h d15, [sp]"
+  -
+    input:
+      bytes: [ 0x53, 0x4f, 0x20, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul d15, d15, #0x4"
+  -
+    input:
+      bytes: [ 0x89, 0xaf, 0xae, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [sp]#0x2e, d15"
+  -
+    input:
+      bytes: [ 0x76, 0x25 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d2, #0xa"
+  -
+    input:
+      bytes: [ 0x3b, 0x00, 0x02, 0x40 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d4, #0x20"
+  -
+    input:
+      bytes: [ 0xb0, 0x14 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add.a a4, #0x1"
+  -
+    input:
+      bytes: [ 0x67, 0x10, 0x1f, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ins.t d0, d0, #0x1f, d1, #0"
+  -
+    input:
+      bytes: [ 0x76, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d0, #0xc"
+  -
+    input:
+      bytes: [ 0xb0, 0x12 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add.a a2, #0x1"
+  -
+    input:
+      bytes: [ 0xd9, 0x32, 0x10, 0x18 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a2, [a3]#-0x7fb0"
+  -
+    input:
+      bytes: [ 0x3b, 0xb0, 0x02, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d8, #0x2b"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0x64, 0x7a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#-0x5a1c"
+  -
+    input:
+      bytes: [ 0xab, 0x08, 0xa2, 0x8f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "seln d8, d15, d8, #0x20"
+  -
+    input:
+      bytes: [ 0xbf, 0x19, 0x18, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt d9, #0x1, #0x30"
+  -
+    input:
+      bytes: [ 0x8f, 0x0f, 0x08, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d0, d15, #0x80"
+  -
+    input:
+      bytes: [ 0x37, 0x03, 0x68, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d0, d3, #0x10, #0x8"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x45, 0x0c ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x188a"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xb8, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x370"
+  -
+    input:
+      bytes: [ 0xdf, 0x2f, 0x91, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, #0x2, #-0xde"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x23, 0x2c ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x1a7ba"
+  -
+    input:
+      bytes: [ 0x5f, 0x0f, 0xd9, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d0, #0x1b2"
+  -
+    input:
+      bytes: [ 0x80, 0x44 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.d d4, a4"
+  -
+    input:
+      bytes: [ 0x80, 0xd0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.d d0, a13"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x92, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x324"
+  -
+    input:
+      bytes: [ 0x53, 0x49, 0x20, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul d15, d9, #0x4"
+  -
+    input:
+      bytes: [ 0xda, 0x96 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d15, #0x96"
+  -
+    input:
+      bytes: [ 0x3c, 0x64 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0xc8"
+  -
+    input:
+      bytes: [ 0x4b, 0xf0, 0x11, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "div.u e0, d0, d15"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xef, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0xdde"
+  -
+    input:
+      bytes: [ 0x02, 0xb0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d0, d11"
+  -
+    input:
+      bytes: [ 0x02, 0xd4 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d4, d13"
+  -
+    input:
+      bytes: [ 0x91, 0x00, 0x03, 0xf8 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a15, #0x8030"
+  -
+    input:
+      bytes: [ 0x3c, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x4"
+  -
+    input:
+      bytes: [ 0x30, 0xf3 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add.a a3, a15"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x26, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x204c"
+  -
+    input:
+      bytes: [ 0x1e, 0x13 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, #0x1, #0x6"
+  -
+    input:
+      bytes: [ 0x0b, 0x73, 0x50, 0x30 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addc d3, d3, d7"
+  -
+    input:
+      bytes: [ 0x9b, 0x74, 0x02, 0x40 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addih d4, d4, #0x27"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x4c, 0x0f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x1e98"
+  -
+    input:
+      bytes: [ 0x06, 0x21 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh d1, #0x2"
+  -
+    input:
+      bytes: [ 0x37, 0x04, 0x50, 0x20 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr d2, d4, #0, #0x10"
+  -
+    input:
+      bytes: [ 0xbb, 0xd0, 0xff, 0x0f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.u d0, #0xfffd"
+  -
+    input:
+      bytes: [ 0x8b, 0xf8, 0x1f, 0x20 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d2, d8, #-0x1"
+  -
+    input:
+      bytes: [ 0x8b, 0x10, 0x00, 0xe0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d14, d0, #0x1"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xfc, 0xfe ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x208"
+  -
+    input:
+      bytes: [ 0x8f, 0x80, 0x40, 0xa1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or d10, d0, #0x8"
+  -
+    input:
+      bytes: [ 0xfb, 0xf0, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov e0, #0xf"
+  -
+    input:
+      bytes: [ 0x40, 0xfc ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.aa a12, a15"
+  -
+    input:
+      bytes: [ 0xa0, 0x3e ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.a a14, #0x3"
+  -
+    input:
+      bytes: [ 0x7f, 0xab, 0x05, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jge d11, d10, #0xa"
+  -
+    input:
+      bytes: [ 0x3b, 0xa0, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d0, #0xa"
+  -
+    input:
+      bytes: [ 0x8f, 0x1a, 0x00, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d15, d10, #0x1"
+  -
+    input:
+      bytes: [ 0x3f, 0xf8, 0xf2, 0x7f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt d8, d15, #-0x1c"
+  -
+    input:
+      bytes: [ 0x6b, 0x00, 0x31, 0xb5 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub.f d11, d5, d0"
+  -
+    input:
+      bytes: [ 0x76, 0x82 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d8, #0x4"
+  -
+    input:
+      bytes: [ 0x4b, 0x0f, 0x41, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.f d0, d15, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x14, 0x80, 0x40 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addx d4, d4, #0x1"
+  -
+    input:
+      bytes: [ 0x3c, 0xdc ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #-0x48"
+  -
+    input:
+      bytes: [ 0x7b, 0x10, 0x7e, 0xf4 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh d15, #0x47e1"
+  -
+    input:
+      bytes: [ 0xb0, 0xc5 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add.a a5, #-0x4"
+  -
+    input:
+      bytes: [ 0x7f, 0x4f, 0x06, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jge d15, d4, #0xc"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0x3c, 0xa0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0x2bc"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0x34, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0x74"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xf0, 0x2a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x1aa20"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x38, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x270"
+  -
+    input:
+      bytes: [ 0xa6, 0x31 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or d1, d3"
+  -
+    input:
+      bytes: [ 0xda, 0x33 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d15, #0x33"
+  -
+    input:
+      bytes: [ 0x37, 0x04, 0xe8, 0x0b ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d0, d4, #0x17, #0x8"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x10, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0xa20"
+  -
+    input:
+      bytes: [ 0xdf, 0x19, 0x22, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d9, #0x1, #0x44"
+  -
+    input:
+      bytes: [ 0x0b, 0x62, 0x40, 0x20 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addx d2, d2, d6"
+  -
+    input:
+      bytes: [ 0x5f, 0x0f, 0x25, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d0, #0x4a"
+  -
+    input:
+      bytes: [ 0x8b, 0x5f, 0x20, 0xf3 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "min.u d15, d15, #0x5"
+  -
+    input:
+      bytes: [ 0xd9, 0x55, 0x08, 0xc0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a5, [a5]#0x308"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0xc0, 0x21 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0x1c80"
+  -
+    input:
+      bytes: [ 0x1d, 0x00, 0xed, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x1da"
+  -
+    input:
+      bytes: [ 0x1d, 0xff, 0x68, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #-0x130"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xb1, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0xd62"
+  -
+    input:
+      bytes: [ 0x49, 0xfd, 0x16, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a13, [a15]#0x16"
+  -
+    input:
+      bytes: [ 0x6d, 0xe8, 0x11, 0x14 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x2fd7de"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x7f, 0x4c ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x16702"
+  -
+    input:
+      bytes: [ 0xb7, 0x1f, 0x81, 0x1b ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d1, d15, #0x1, #0x17, #0x1"
+  -
+    input:
+      bytes: [ 0x09, 0xff, 0xb4, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.h d15, [a15]#0x34"
+  -
+    input:
+      bytes: [ 0x3b, 0x80, 0x07, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d0, #0x78"
+  -
+    input:
+      bytes: [ 0xc6, 0x30 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor d0, d3"
+  -
+    input:
+      bytes: [ 0xb4, 0xdf ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [a13], d15"
+  -
+    input:
+      bytes: [ 0x4b, 0x0f, 0x31, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ftoiz d15, d15"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0x88, 0xda ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#-0x54b8"
+  -
+    input:
+      bytes: [ 0x37, 0xf0, 0x04, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d0, d15, #0, #0x4"
+  -
+    input:
+      bytes: [ 0x5f, 0x0f, 0x78, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d0, #0xf0"
+  -
+    input:
+      bytes: [ 0x82, 0x30 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d0, #0x3"
+  -
+    input:
+      bytes: [ 0x09, 0xff, 0xd4, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.hu d15, [a15]#0x14"
+  -
+    input:
+      bytes: [ 0x4b, 0x0a, 0x01, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmp.f d15, d10, d0"
+  -
+    input:
+      bytes: [ 0xf6, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz d0, #0x8"
+  -
+    input:
+      bytes: [ 0x67, 0x01, 0x80, 0x1f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ins.t d1, d1, #0, d0, #0x1f"
+  -
+    input:
+      bytes: [ 0x2e, 0x14 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.t d15, #0x1, #0x8"
+  -
+    input:
+      bytes: [ 0xee, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz d15, #0xa"
+  -
+    input:
+      bytes: [ 0x61, 0xff, 0xe9, 0xd9 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcall #-0x4c2e"
+  -
+    input:
+      bytes: [ 0xbe, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d0, #0x22"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x29, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x852"
+  -
+    input:
+      bytes: [ 0x5f, 0x0f, 0x2a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d0, #0x54"
+  -
+    input:
+      bytes: [ 0x42, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d1, d15"
+  -
+    input:
+      bytes: [ 0x3c, 0x20 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x40"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x68, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x6d0"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x49, 0x12 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x2492"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xf0, 0xfe ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x220"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x05, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0xa"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x42, 0x11 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x2284"
+  -
+    input:
+      bytes: [ 0xda, 0x1d ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d15, #0x1d"
+  -
+    input:
+      bytes: [ 0x91, 0x30, 0x00, 0x4f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a4, #0xf003"
+  -
+    input:
+      bytes: [ 0xb7, 0x00, 0x89, 0x0b ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d0, d0, #0, #0x17, #0x9"
+  -
+    input:
+      bytes: [ 0xbd, 0x02, 0x30, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.a a2, #0x60"
+  -
+    input:
+      bytes: [ 0x40, 0x52 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.aa a2, a5"
+  -
+    input:
+      bytes: [ 0x9b, 0xb1, 0xa5, 0x14 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addih d1, d1, #0x4a5b"
+  -
+    input:
+      bytes: [ 0x82, 0xf3 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d3, #-0x1"
+  -
+    input:
+      bytes: [ 0x5f, 0x01, 0x0b, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d1, d0, #0x16"
+  -
+    input:
+      bytes: [ 0x49, 0xa4, 0x00, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a4, [sp]#0"
+  -
+    input:
+      bytes: [ 0x76, 0xc6 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d12, #0xc"
+  -
+    input:
+      bytes: [ 0xbb, 0x00, 0x52, 0x0c ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.u d0, #0xc520"
+  -
+    input:
+      bytes: [ 0x3b, 0x40, 0x06, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d0, #0x64"
+  -
+    input:
+      bytes: [ 0x4b, 0x3b, 0x01, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmp.f d15, d11, d3"
+  -
+    input:
+      bytes: [ 0xac, 0xa6 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [sp]#0xc, d15"
+  -
+    input:
+      bytes: [ 0x7f, 0xf1, 0x04, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jge.u d1, d15, #0x8"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x94, 0x2b ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x1a8d8"
+  -
+    input:
+      bytes: [ 0xac, 0x47 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [a4]#0xe, d15"
+  -
+    input:
+      bytes: [ 0x82, 0x1a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d10, #0x1"
+  -
+    input:
+      bytes: [ 0x7f, 0xf0, 0x07, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jge d0, d15, #0xe"
+  -
+    input:
+      bytes: [ 0x73, 0x6d, 0x0a, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul d15, d13, d6"
+  -
+    input:
+      bytes: [ 0x26, 0x2f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d15, d2"
+  -
+    input:
+      bytes: [ 0xd9, 0x22, 0x96, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a2, [a2]#0x1816"
+  -
+    input:
+      bytes: [ 0x53, 0x69, 0x20, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul d15, d9, #0x6"
+  -
+    input:
+      bytes: [ 0x8b, 0x0f, 0x02, 0xc0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d12, d15, #0x20"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x03, 0xfe ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x3fa"
+  -
+    input:
+      bytes: [ 0x1d, 0x00, 0xe5, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x1ca"
+  -
+    input:
+      bytes: [ 0x77, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "dextr d0, d0, d0, #0x8"
+  -
+    input:
+      bytes: [ 0x7f, 0xf1, 0x09, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jge d1, d15, #0x12"
+  -
+    input:
+      bytes: [ 0x3c, 0xe8 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #-0x30"
+  -
+    input:
+      bytes: [ 0x0b, 0xcd, 0x10, 0x48 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov e4, d13, d12"
+  -
+    input:
+      bytes: [ 0x3f, 0x1f, 0x04, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt d15, d1, #0x8"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x2b, 0xfa ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0xbaa"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x03, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d15, d0, #0x30"
+  -
+    input:
+      bytes: [ 0x4b, 0x0a, 0x41, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.f d15, d10, d0"
+  -
+    input:
+      bytes: [ 0xb7, 0x0f, 0x89, 0xfb ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, #0, #0x17, #0x9"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xdc, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x48"
+  -
+    input:
+      bytes: [ 0x40, 0x4f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.aa a15, a4"
+  -
+    input:
+      bytes: [ 0x1d, 0x00, 0x8a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x114"
+  -
+    input:
+      bytes: [ 0x7b, 0x00, 0x05, 0x40 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh d4, #0x50"
+  -
+    input:
+      bytes: [ 0xd9, 0x22, 0x06, 0x71 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a2, [a2]#0x11c6"
+  -
+    input:
+      bytes: [ 0x1d, 0x00, 0x4a, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x294"
+  -
+    input:
+      bytes: [ 0x8b, 0xa0, 0x60, 0xf2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lt.u d15, d0, #0xa"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x68, 0xf9 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0xd30"
+  -
+    input:
+      bytes: [ 0xda, 0x78 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d15, #0x78"
+  -
+    input:
+      bytes: [ 0x26, 0x40 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d0, d4"
+  -
+    input:
+      bytes: [ 0x80, 0xf4 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.d d4, a15"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x5a, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x6b4"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x5f, 0x0f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x1ebe"
+  -
+    input:
+      bytes: [ 0x3b, 0x00, 0x08, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d0, #0x1080"
+  -
+    input:
+      bytes: [ 0x4b, 0xf0, 0x41, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.f d15, d0, d15"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xa3, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x2146"
+  -
+    input:
+      bytes: [ 0xee, 0x0d ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz d15, #0x1a"
+  -
+    input:
+      bytes: [ 0x37, 0x0c, 0xe8, 0xfb ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d15, d12, #0x17, #0x8"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0x10, 0x0b ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#-0x4ff0"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x1a, 0xf9 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0xdcc"
+  -
+    input:
+      bytes: [ 0x0b, 0xaa, 0x10, 0x88 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov e8, d10, d10"
+  -
+    input:
+      bytes: [ 0x3b, 0xa0, 0x00, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d1, #0xa"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x47, 0xf6 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x1372"
+  -
+    input:
+      bytes: [ 0x3b, 0x80, 0x07, 0x40 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d4, #0x78"
+  -
+    input:
+      bytes: [ 0x7e, 0x55 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, d5, #0xa"
+  -
+    input:
+      bytes: [ 0x0b, 0x01, 0x10, 0x28 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov e2, d1, d0"
+  -
+    input:
+      bytes: [ 0x07, 0x1d, 0xe0, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor.t d15, d13, #0, d1, #0x1f"
+  -
+    input:
+      bytes: [ 0x3b, 0xd0, 0x02, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d0, #0x2d"
+  -
+    input:
+      bytes: [ 0x3c, 0x70 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0xe0"
+  -
+    input:
+      bytes: [ 0x37, 0x0f, 0xe1, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d15, d15, #0x3, #0x1"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0x80, 0x9a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#-0x55c0"
+  -
+    input:
+      bytes: [ 0x53, 0x59, 0x2f, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul d15, d9, #0xf5"
+  -
+    input:
+      bytes: [ 0xb0, 0x54 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add.a a4, #0x5"
+  -
+    input:
+      bytes: [ 0x91, 0x40, 0x00, 0x57 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a5, #0x7004"
+  -
+    input:
+      bytes: [ 0x61, 0xff, 0xe9, 0xd8 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcall #-0x4e2e"
+  -
+    input:
+      bytes: [ 0xbc, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.a a15, #0x2"
+  -
+    input:
+      bytes: [ 0xdf, 0x1f, 0xfa, 0x7f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, #0x1, #-0xc"
+  -
+    input:
+      bytes: [ 0x0f, 0xf2, 0x00, 0x20 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh d2, d2, d15"
+  -
+    input:
+      bytes: [ 0x90, 0xdd ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addsc.a a13, a13, d15, #0x2"
+  -
+    input:
+      bytes: [ 0x8b, 0x40, 0x00, 0x90 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d9, d0, #0x4"
+  -
+    input:
+      bytes: [ 0x6d, 0xe8, 0xbd, 0x14 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x2fd686"
+  -
+    input:
+      bytes: [ 0xee, 0xf6 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz d15, #-0x14"
+  -
+    input:
+      bytes: [ 0x3b, 0x70, 0x06, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d0, #0x67"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x9d, 0x29 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x1acc6"
+  -
+    input:
+      bytes: [ 0xd9, 0x44, 0x40, 0x4b ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a4, [a4]#-0x4b00"
+  -
+    input:
+      bytes: [ 0x9b, 0x1f, 0x00, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addih d15, d15, #0x1"
+  -
+    input:
+      bytes: [ 0xb7, 0x1f, 0x08, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, #0x1, #0, #0x8"
+  -
+    input:
+      bytes: [ 0xb7, 0x0f, 0x01, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, #0, #0, #0x1"
+  -
+    input:
+      bytes: [ 0xff, 0x1f, 0xf7, 0x7f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jge d15, #0x1, #-0x12"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xbf, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x57e"
+  -
+    input:
+      bytes: [ 0xd9, 0x55, 0xa4, 0xca ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a5, [a5]#-0x54dc"
+  -
+    input:
+      bytes: [ 0x3c, 0x1b ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x36"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x7b, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x10a"
+  -
+    input:
+      bytes: [ 0xa0, 0x94 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.a a4, #0x9"
+  -
+    input:
+      bytes: [ 0x49, 0xa5, 0x02, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a5, [sp]#0x2"
+  -
+    input:
+      bytes: [ 0x3b, 0xe0, 0x07, 0x50 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d5, #0x7e"
+  -
+    input:
+      bytes: [ 0xb7, 0x0f, 0x81, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, #0, #0x1f, #0x1"
+  -
+    input:
+      bytes: [ 0xc2, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d0, #-0x1"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x04, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x8"
+  -
+    input:
+      bytes: [ 0x37, 0x04, 0x68, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d15, d4, #0, #0x8"
+  -
+    input:
+      bytes: [ 0x37, 0x4f, 0x05, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, d4, #0, #0x5"
+  -
+    input:
+      bytes: [ 0xdc, 0x0b ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ji a11"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xf3, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x11e6"
+  -
+    input:
+      bytes: [ 0x3b, 0x00, 0x40, 0x40 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d4, #0x400"
+  -
+    input:
+      bytes: [ 0xee, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz d15, #0x20"
+  -
+    input:
+      bytes: [ 0x3c, 0x2e ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x5c"
+  -
+    input:
+      bytes: [ 0xa0, 0x34 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.a a4, #0x3"
+  -
+    input:
+      bytes: [ 0x0b, 0x13, 0x80, 0xf2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.ne d15, d3, d1"
+  -
+    input:
+      bytes: [ 0xdf, 0x09, 0x38, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d9, #0, #0x70"
+  -
+    input:
+      bytes: [ 0xa6, 0x42 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or d2, d4"
+  -
+    input:
+      bytes: [ 0x8f, 0x39, 0x00, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d15, d9, #0x3"
+  -
+    input:
+      bytes: [ 0x37, 0xf0, 0x01, 0xf2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d0, d15, #0x4, #0x1"
+  -
+    input:
+      bytes: [ 0x06, 0x3f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh d15, #0x3"
+  -
+    input:
+      bytes: [ 0x3c, 0x40 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x80"
+  -
+    input:
+      bytes: [ 0xff, 0x1b, 0xf2, 0x7f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jge d11, #0x1, #-0x1c"
+  -
+    input:
+      bytes: [ 0xb7, 0x0f, 0x0c, 0xfa ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, #0, #0x14, #0xc"
+  -
+    input:
+      bytes: [ 0x3c, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #-0x20"
+  -
+    input:
+      bytes: [ 0x91, 0x00, 0x00, 0xf7 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a15, #0x7000"
+  -
+    input:
+      bytes: [ 0x7f, 0xf0, 0x27, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jge d0, d15, #0x4e"
+  -
+    input:
+      bytes: [ 0x4b, 0xf0, 0x51, 0x20 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "div.f d2, d0, d15"
+  -
+    input:
+      bytes: [ 0x52, 0x52 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub d2, d15, d5"
+  -
+    input:
+      bytes: [ 0x26, 0xf3 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d3, d15"
+  -
+    input:
+      bytes: [ 0x8f, 0xec, 0x1f, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh d15, d12, #-0x2"
+  -
+    input:
+      bytes: [ 0x87, 0x55, 0x9f, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.t d15, d5, #0x1f, d5, #0x1f"
+  -
+    input:
+      bytes: [ 0x37, 0x0f, 0x61, 0xf3 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d15, d15, #0x6, #0x1"
+  -
+    input:
+      bytes: [ 0xa6, 0x5f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or d15, d5"
+  -
+    input:
+      bytes: [ 0xce, 0xf6 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jgez d15, #0xc"
+  -
+    input:
+      bytes: [ 0xbd, 0x0e, 0x15, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.a a14, #0x2a"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x6c, 0x11 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x22d8"
+  -
+    input:
+      bytes: [ 0x4b, 0x0f, 0x41, 0x40 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.f d4, d15, d0"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x82, 0x2b ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x1a8fc"
+  -
+    input:
+      bytes: [ 0x37, 0x0f, 0xe1, 0xf7 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d15, d15, #0xf, #0x1"
+  -
+    input:
+      bytes: [ 0xbe, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d0, #0x20"
+  -
+    input:
+      bytes: [ 0x96, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or d15, #0x3"
+  -
+    input:
+      bytes: [ 0x8f, 0x8f, 0x01, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh d0, d15, #0x18"
+  -
+    input:
+      bytes: [ 0x3b, 0x00, 0x08, 0x40 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d4, #0x80"
+  -
+    input:
+      bytes: [ 0x7f, 0xab, 0x04, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jge d11, d10, #0x8"
+  -
+    input:
+      bytes: [ 0x02, 0x58 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d8, d5"
+  -
+    input:
+      bytes: [ 0xdf, 0x08, 0x17, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d8, #0, #0x2e"
+  -
+    input:
+      bytes: [ 0x60, 0xc2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.a a2, d12"
+  -
+    input:
+      bytes: [ 0x3c, 0xe2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #-0x3c"
+  -
+    input:
+      bytes: [ 0x49, 0xef, 0x01, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a14]#0x1"
+  -
+    input:
+      bytes: [ 0x37, 0x0f, 0x68, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d1, d15, #0, #0x8"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xdb, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x21b6"
+  -
+    input:
+      bytes: [ 0xca, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "caddn d15, d15, #-0x1"
+  -
+    input:
+      bytes: [ 0x0b, 0xf0, 0xa0, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "max d15, d0, d15"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x03, 0x40 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d4, d0, #0x30"
+  -
+    input:
+      bytes: [ 0x02, 0x86 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d6, d8"
+  -
+    input:
+      bytes: [ 0xa2, 0x9f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub d15, d9"
+  -
+    input:
+      bytes: [ 0x3b, 0xf0, 0xff, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d0, #0xfff"
+  -
+    input:
+      bytes: [ 0x49, 0xaf, 0x00, 0x1a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [sp]#0x40"
+  -
+    input:
+      bytes: [ 0x37, 0x0f, 0x62, 0xf2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d15, d15, #0x4, #0x2"
+  -
+    input:
+      bytes: [ 0xb4, 0xa4 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [sp], d4"
+  -
+    input:
+      bytes: [ 0x6f, 0x09, 0x14, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz.t d9, #0, #0x28"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xcc, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x1198"
+  -
+    input:
+      bytes: [ 0xc2, 0xe5 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d5, #-0x2"
+  -
+    input:
+      bytes: [ 0x09, 0xdf, 0xe0, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.hu d15, [a13]#0x20"
+  -
+    input:
+      bytes: [ 0xee, 0x12 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz d15, #0x24"
+  -
+    input:
+      bytes: [ 0x40, 0x7c ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.aa a12, a7"
+  -
+    input:
+      bytes: [ 0x0b, 0xd1, 0x90, 0xf2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.lt d15, d1, d13"
+  -
+    input:
+      bytes: [ 0xff, 0x1a, 0xea, 0x7f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jge d10, #0x1, #-0x2c"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x73, 0x11 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x22e6"
+  -
+    input:
+      bytes: [ 0x3b, 0xf0, 0x49, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d0, #0x249f"
+  -
+    input:
+      bytes: [ 0x37, 0x0f, 0x50, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr d1, d15, #0, #0x10"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xfc, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x13f8"
+  -
+    input:
+      bytes: [ 0xa0, 0xb4 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.a a4, #0xb"
+  -
+    input:
+      bytes: [ 0x3b, 0x00, 0x04, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d0, #0x40"
+  -
+    input:
+      bytes: [ 0x3c, 0x22 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x44"
+  -
+    input:
+      bytes: [ 0x6f, 0x10, 0xf2, 0x7f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.t d0, #0x1, #-0x1c"
+  -
+    input:
+      bytes: [ 0x4b, 0xf2, 0x41, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.f d15, d2, d15"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xc3, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x786"
+  -
+    input:
+      bytes: [ 0x7f, 0x0f, 0x05, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jge d15, d0, #0xa"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0x38, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0x78"
+  -
+    input:
+      bytes: [ 0x3b, 0xa0, 0x06, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d0, #0x6a"
+  -
+    input:
+      bytes: [ 0x91, 0x40, 0x00, 0x4f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a4, #0xf004"
+  -
+    input:
+      bytes: [ 0x8f, 0xf5, 0x0f, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d15, d5, #0xff"
+  -
+    input:
+      bytes: [ 0x7f, 0x2f, 0x05, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jge d15, d2, #0xa"
+  -
+    input:
+      bytes: [ 0x3b, 0xc0, 0x00, 0x40 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d4, #0xc"
+  -
+    input:
+      bytes: [ 0x37, 0x00, 0x62, 0xf2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d15, d0, #0x4, #0x2"
+  -
+    input:
+      bytes: [ 0x0b, 0xfa, 0x10, 0x68 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov e6, d10, d15"
+  -
+    input:
+      bytes: [ 0x3b, 0x70, 0x06, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d1, #0x67"
+  -
+    input:
+      bytes: [ 0x61, 0xff, 0xd2, 0xd8 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcall #-0x4e5c"
+  -
+    input:
+      bytes: [ 0x67, 0xaa, 0xbf, 0xaf ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insn.t d10, d10, #0x1f, d10, #0x1f"
+  -
+    input:
+      bytes: [ 0x8b, 0x0f, 0x03, 0x40 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d4, d15, #0x30"
+  -
+    input:
+      bytes: [ 0x01, 0xe2, 0x00, 0x26 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addsc.a a2, a14, d2, #0"
+  -
+    input:
+      bytes: [ 0x8f, 0x71, 0x01, 0x20 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh d2, d1, #0x17"
+  -
+    input:
+      bytes: [ 0x06, 0x62 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh d2, #0x6"
+  -
+    input:
+      bytes: [ 0xd9, 0xdd, 0xe4, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a13, [a13]#0xc64"
+  -
+    input:
+      bytes: [ 0x0b, 0x82, 0x50, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ge.u d0, d2, d8"
+  -
+    input:
+      bytes: [ 0x5f, 0xef, 0x6c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d14, #0xd8"
+  -
+    input:
+      bytes: [ 0x3c, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #-0x2"
+  -
+    input:
+      bytes: [ 0x6e, 0x0f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d15, #0x1e"
+  -
+    input:
+      bytes: [ 0x02, 0x12 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d2, d1"
+  -
+    input:
+      bytes: [ 0x5f, 0x0f, 0xf1, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, d0, #-0x1e"
+  -
+    input:
+      bytes: [ 0x37, 0x0f, 0x61, 0xf2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d15, d15, #0x4, #0x1"
+  -
+    input:
+      bytes: [ 0x7b, 0x00, 0xf8, 0xb3 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh d11, #0x3f80"
+  -
+    input:
+      bytes: [ 0x49, 0xa5, 0x0c, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a5, [sp]#0xc"
+  -
+    input:
+      bytes: [ 0x76, 0x8c ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d8, #0x18"
+  -
+    input:
+      bytes: [ 0x03, 0x6d, 0x0a, 0x90 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd d9, d0, d13, d6"
+  -
+    input:
+      bytes: [ 0xbe, 0x41 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d4, #0x22"
+  -
+    input:
+      bytes: [ 0x57, 0x00, 0x62, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d15, d0, d15, #0x2"
+  -
+    input:
+      bytes: [ 0xb7, 0x00, 0x89, 0xfb ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d0, #0, #0x17, #0x9"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x86, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0xf4"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xa9, 0xf4 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x16ae"
+  -
+    input:
+      bytes: [ 0x37, 0x04, 0x68, 0x40 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d4, d4, #0, #0x8"
+  -
+    input:
+      bytes: [ 0x3b, 0x00, 0x16, 0x50 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d5, #0x160"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x13, 0xfa ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0xbda"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0xb0, 0xda ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#-0x5490"
+  -
+    input:
+      bytes: [ 0x7d, 0xef, 0x03, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq.a a15, a14, #0x6"
+  -
+    input:
+      bytes: [ 0x9a, 0x49 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d15, d9, #0x4"
+  -
+    input:
+      bytes: [ 0xd9, 0x22, 0x36, 0x61 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a2, [a2]#0x11b6"
+  -
+    input:
+      bytes: [ 0x91, 0x40, 0x00, 0xf6 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a15, #0x6004"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0x30, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0x3f0"
+  -
+    input:
+      bytes: [ 0x8f, 0x3f, 0x00, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh d1, d15, #0x3"
+  -
+    input:
+      bytes: [ 0x6f, 0x5a, 0x06, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.t d10, #0x5, #0xc"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xd8, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x5b0"
+  -
+    input:
+      bytes: [ 0xa2, 0x1f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub d15, d1"
+  -
+    input:
+      bytes: [ 0xc2, 0xf8 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d8, #-0x1"
+  -
+    input:
+      bytes: [ 0x49, 0xfc, 0x14, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a12, [a15]#0x14"
+  -
+    input:
+      bytes: [ 0xc6, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor d0, d1"
+  -
+    input:
+      bytes: [ 0x6b, 0x02, 0x31, 0xf4 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub.f d15, d4, d2"
+  -
+    input:
+      bytes: [ 0x37, 0x0f, 0x50, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr d0, d15, #0, #0x10"
+  -
+    input:
+      bytes: [ 0xbb, 0x00, 0xa0, 0x1b ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.u d1, #0xba00"
+  -
+    input:
+      bytes: [ 0xa2, 0xdc ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub d12, d13"
+  -
+    input:
+      bytes: [ 0x8b, 0x0f, 0x00, 0x92 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "eq d9, d15, #0"
+  -
+    input:
+      bytes: [ 0x40, 0xf4 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.aa a4, a15"
+  -
+    input:
+      bytes: [ 0x3b, 0xd0, 0x02, 0x40 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d4, #0x2d"
+  -
+    input:
+      bytes: [ 0xee, 0xe9 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz d15, #-0x2e"
+  -
+    input:
+      bytes: [ 0xbe, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d0, #0x2e"
+  -
+    input:
+      bytes: [ 0xd9, 0x22, 0x96, 0x71 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a2, [a2]#0x19d6"
+  -
+    input:
+      bytes: [ 0x3b, 0x70, 0x04, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d0, #0x47"
+  -
+    input:
+      bytes: [ 0x37, 0x0f, 0x05, 0xf8 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, d0, #0x10, #0x5"
+  -
+    input:
+      bytes: [ 0x01, 0x2f, 0x10, 0xf4 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ne.a d15, a15, a2"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x79, 0x1a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x34f2"
+  -
+    input:
+      bytes: [ 0x3b, 0x60, 0x04, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d0, #0x46"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x20, 0xf2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ne d15, d0, #0"
+  -
+    input:
+      bytes: [ 0x42, 0xf8 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d8, d15"
+  -
+    input:
+      bytes: [ 0x37, 0x0f, 0x50, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr d15, d15, #0, #0x10"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0x10, 0x20 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0x90"
+  -
+    input:
+      bytes: [ 0x8f, 0x38, 0x20, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha d15, d8, #0x3"
+  -
+    input:
+      bytes: [ 0xa2, 0xf4 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub d4, d15"
+  -
+    input:
+      bytes: [ 0x3b, 0x50, 0x04, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d1, #0x45"
+  -
+    input:
+      bytes: [ 0x02, 0xe4 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d4, d14"
+  -
+    input:
+      bytes: [ 0x8f, 0x4a, 0x40, 0xa1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or d10, d10, #0x4"
+  -
+    input:
+      bytes: [ 0x4b, 0xfa, 0x41, 0x40 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.f d4, d10, d15"
+  -
+    input:
+      bytes: [ 0x49, 0xaa, 0x00, 0x8a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea sp, [sp]#-0x200"
+  -
+    input:
+      bytes: [ 0x61, 0xff, 0x60, 0xd9 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcall #-0x4d40"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xa6, 0x3e ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x182b4"
+  -
+    input:
+      bytes: [ 0xd9, 0x44, 0x00, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a4, [a4]#-0x6000"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xbc, 0xfd ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x488"
+  -
+    input:
+      bytes: [ 0x02, 0x89 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d9, d8"
+  -
+    input:
+      bytes: [ 0x37, 0x0f, 0x01, 0xf2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, d0, #0x4, #0x1"
+  -
+    input:
+      bytes: [ 0xf6, 0xa3 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz d10, #0x6"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x57, 0x11 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x22ae"
+  -
+    input:
+      bytes: [ 0xc2, 0x19 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d9, #0x1"
+  -
+    input:
+      bytes: [ 0x3c, 0x15 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x2a"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xf0, 0xfd ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x420"
+  -
+    input:
+      bytes: [ 0x3b, 0x20, 0x07, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d0, #0x72"
+  -
+    input:
+      bytes: [ 0x8f, 0x8f, 0x00, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh d15, d15, #0x8"
+  -
+    input:
+      bytes: [ 0xd9, 0x55, 0x20, 0xfa ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a5, [a5]#-0x5c20"
+  -
+    input:
+      bytes: [ 0x8f, 0x31, 0x40, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or d15, d1, #0x3"
+  -
+    input:
+      bytes: [ 0x80, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.d d15, a15"
+  -
+    input:
+      bytes: [ 0x0b, 0x40, 0x40, 0x20 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addx d2, d0, d4"
+  -
+    input:
+      bytes: [ 0xb7, 0x0f, 0x02, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, #0, #0, #0x2"
+  -
+    input:
+      bytes: [ 0x0b, 0x26, 0x10, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ne d15, d6, d2"
+  -
+    input:
+      bytes: [ 0x88, 0x8f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.h d15, [a15]#0x10"
+  -
+    input:
+      bytes: [ 0x91, 0x00, 0x00, 0x27 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a2, #0x7000"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xe7, 0xfe ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x232"
+  -
+    input:
+      bytes: [ 0x5f, 0x0f, 0xc2, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d0, #0x184"
+  -
+    input:
+      bytes: [ 0x09, 0x20, 0x94, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.h d0, [a2]#0x14"
+  -
+    input:
+      bytes: [ 0x91, 0x50, 0x02, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a15, #0xf025"
+  -
+    input:
+      bytes: [ 0x91, 0x40, 0x00, 0x26 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a2, #0x6004"
+  -
+    input:
+      bytes: [ 0xbd, 0x04, 0x31, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.a a4, #0x62"
+  -
+    input:
+      bytes: [ 0xd9, 0x22, 0x1a, 0x11 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a2, [a2]#0x105a"
+  -
+    input:
+      bytes: [ 0x53, 0xc2, 0x20, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul d15, d2, #0xc"
+  -
+    input:
+      bytes: [ 0xbd, 0x0d, 0x22, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.a a13, #0x44"
+  -
+    input:
+      bytes: [ 0x0b, 0x71, 0x50, 0x90 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addc d9, d1, d7"
+  -
+    input:
+      bytes: [ 0x30, 0x43 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add.a a3, a4"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x9f, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x33e"
+  -
+    input:
+      bytes: [ 0x02, 0x98 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d8, d9"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x85, 0x12 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x250a"
+  -
+    input:
+      bytes: [ 0x02, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d1, d0"
+  -
+    input:
+      bytes: [ 0x20, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub.a sp, #0x10"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x5d, 0xf4 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x1746"
+  -
+    input:
+      bytes: [ 0x91, 0x00, 0x00, 0xe8 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a14, #0x8000"
+  -
+    input:
+      bytes: [ 0x02, 0x9c ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d12, d9"
+  -
+    input:
+      bytes: [ 0x7e, 0x1d ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, d1, #0x1a"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x7b, 0xfa ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0xb0a"
+  -
+    input:
+      bytes: [ 0xb7, 0x0f, 0x1c, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, #0, #0, #0x1c"
+  -
+    input:
+      bytes: [ 0x5f, 0x0f, 0xdc, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d0, #0x1b8"
+  -
+    input:
+      bytes: [ 0x02, 0xc4 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d4, d12"
+  -
+    input:
+      bytes: [ 0xd9, 0x22, 0xb0, 0x4a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a2, [a2]#-0x56d0"
+  -
+    input:
+      bytes: [ 0x8f, 0xff, 0x83, 0x31 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor d3, d15, #0x3f"
+  -
+    input:
+      bytes: [ 0x37, 0x0f, 0x81, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, d0, #0x3, #0x1"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0x20, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0x220"
+  -
+    input:
+      bytes: [ 0x76, 0x13 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d1, #0x6"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xf8, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x21f0"
+  -
+    input:
+      bytes: [ 0x53, 0x40, 0x20, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul d15, d0, #0x4"
+  -
+    input:
+      bytes: [ 0xda, 0x0f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d15, #0xf"
+  -
+    input:
+      bytes: [ 0xbf, 0x10, 0xf5, 0x7f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt d0, #0x1, #-0x16"
+  -
+    input:
+      bytes: [ 0x8f, 0x41, 0x1f, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh d15, d1, #-0xc"
+  -
+    input:
+      bytes: [ 0x4b, 0xf0, 0x51, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "q31tof d15, d0, d15"
+  -
+    input:
+      bytes: [ 0x89, 0x40, 0x84, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [a4]#0x4, d0"
+  -
+    input:
+      bytes: [ 0x5f, 0x0f, 0x6e, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d0, #0xdc"
+  -
+    input:
+      bytes: [ 0x3b, 0x80, 0x01, 0xb0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d11, #0x18"
+  -
+    input:
+      bytes: [ 0x8f, 0xdf, 0x0f, 0x41 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d4, d15, #0xfd"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xc7, 0x0d ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x1b8e"
+  -
+    input:
+      bytes: [ 0xa2, 0x31 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub d1, d3"
+  -
+    input:
+      bytes: [ 0x0b, 0x13, 0x90, 0xf2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.lt d15, d3, d1"
+  -
+    input:
+      bytes: [ 0xdf, 0x04, 0x50, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d4, #0, #0x4a0"
+  -
+    input:
+      bytes: [ 0xd9, 0x44, 0xa8, 0x4a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a4, [a4]#-0x56d8"
+  -
+    input:
+      bytes: [ 0x3b, 0x30, 0x02, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d0, #0x23"
+  -
+    input:
+      bytes: [ 0xc2, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d0, #0x1"
+  -
+    input:
+      bytes: [ 0x5f, 0x0f, 0xed, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, d0, #-0x26"
+  -
+    input:
+      bytes: [ 0x91, 0x00, 0x03, 0xfa ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a15, #0xa030"
+  -
+    input:
+      bytes: [ 0xda, 0x0d ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d15, #0xd"
+  -
+    input:
+      bytes: [ 0x7e, 0x44 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, d4, #0x8"
+  -
+    input:
+      bytes: [ 0xf6, 0x84 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz d8, #0x8"
+  -
+    input:
+      bytes: [ 0xb7, 0x2f, 0x02, 0xf5 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, #0x2, #0xa, #0x2"
+  -
+    input:
+      bytes: [ 0x82, 0x74 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d4, #0x7"
+  -
+    input:
+      bytes: [ 0xfc, 0x2f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "loop a2, #-0x2"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0x2c, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0x22c"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x0d, 0xf9 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0xde6"
+  -
+    input:
+      bytes: [ 0xd9, 0x55, 0x54, 0x5a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a5, [a5]#-0x5aac"
+  -
+    input:
+      bytes: [ 0x4b, 0xdb, 0x41, 0xb0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.f d11, d11, d13"
+  -
+    input:
+      bytes: [ 0xc2, 0x3f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d15, #0x3"
+  -
+    input:
+      bytes: [ 0x7f, 0x89, 0x2c, 0x7f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jge d9, d8, #-0x1a8"
+  -
+    input:
+      bytes: [ 0x2e, 0x2c ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.t d15, #0x2, #0x18"
+  -
+    input:
+      bytes: [ 0x40, 0xbf ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.aa a15, a11"
+  -
+    input:
+      bytes: [ 0x6f, 0x1f, 0xfa, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz.t d15, #0x1, #-0xc"
+  -
+    input:
+      bytes: [ 0x40, 0xd5 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.aa a5, a13"
+  -
+    input:
+      bytes: [ 0xc2, 0x7f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d15, #0x7"
+  -
+    input:
+      bytes: [ 0xdf, 0x08, 0xd4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d8, #0, #0x1a8"
+  -
+    input:
+      bytes: [ 0x37, 0x05, 0x68, 0xf8 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d15, d5, #0x10, #0x8"
+  -
+    input:
+      bytes: [ 0x49, 0xa4, 0x06, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a4, [sp]#0x6"
+  -
+    input:
+      bytes: [ 0x7f, 0x80, 0x18, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jge.u d0, d8, #0x30"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xe5, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x13ca"
+  -
+    input:
+      bytes: [ 0x0b, 0x40, 0x50, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ge.u d15, d0, d4"
+  -
+    input:
+      bytes: [ 0x53, 0x4b, 0x20, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul d15, d11, #0x4"
+  -
+    input:
+      bytes: [ 0xbb, 0xf0, 0xff, 0x6f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.u d6, #0xffff"
+  -
+    input:
+      bytes: [ 0x49, 0xf2, 0x1c, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a2, [a15]#0x1c"
+  -
+    input:
+      bytes: [ 0x76, 0x28 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d2, #0x10"
+  -
+    input:
+      bytes: [ 0x7e, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, d0, #0xe"
+  -
+    input:
+      bytes: [ 0x6f, 0x08, 0x19, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz.t d8, #0, #0x32"
+  -
+    input:
+      bytes: [ 0x01, 0xfe, 0x20, 0xf4 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lt.a d15, a14, a15"
+  -
+    input:
+      bytes: [ 0x3f, 0xf0, 0x05, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt d0, d15, #0xa"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xf7, 0xfe ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x212"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0xac, 0xba ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#-0x5514"
+  -
+    input:
+      bytes: [ 0x02, 0xf4 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d4, d15"
+  -
+    input:
+      bytes: [ 0x8f, 0x24, 0x00, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh d15, d4, #0x2"
+  -
+    input:
+      bytes: [ 0xd9, 0x44, 0x0c, 0x96 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a4, [a4]#0x624c"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0x68, 0x60 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0x5a8"
+  -
+    input:
+      bytes: [ 0x3c, 0x3b ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x76"
+  -
+    input:
+      bytes: [ 0x86, 0x5f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha d15, #0x5"
+  -
+    input:
+      bytes: [ 0x6e, 0x30 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d15, #0x60"
+  -
+    input:
+      bytes: [ 0x3f, 0xaf, 0xf7, 0x7f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt d15, d10, #-0x12"
+  -
+    input:
+      bytes: [ 0x5f, 0x0f, 0x3c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d0, #0x78"
+  -
+    input:
+      bytes: [ 0x26, 0x42 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d2, d4"
+  -
+    input:
+      bytes: [ 0xfc, 0x4e ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "loop a4, #-0x4"
+  -
+    input:
+      bytes: [ 0x7b, 0x00, 0x00, 0x0d ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh d0, #0xd000"
+  -
+    input:
+      bytes: [ 0xd9, 0x55, 0x74, 0x5a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a5, [a5]#-0x5a8c"
+  -
+    input:
+      bytes: [ 0x49, 0xa2, 0x00, 0x1a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a2, [sp]#0x40"
+  -
+    input:
+      bytes: [ 0xdf, 0x08, 0x26, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d8, #0, #0x4c"
+  -
+    input:
+      bytes: [ 0xa6, 0x40 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or d0, d4"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xc2, 0xfa ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0xa7c"
+  -
+    input:
+      bytes: [ 0x1d, 0xff, 0x4d, 0xfe ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #-0x366"
+  -
+    input:
+      bytes: [ 0x82, 0xf2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d2, #-0x1"
+  -
+    input:
+      bytes: [ 0xc5, 0xf5, 0x80, 0xc0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a5, #0xf0000b00"
+  -
+    input:
+      bytes: [ 0x3c, 0x33 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x66"
+  -
+    input:
+      bytes: [ 0x8b, 0xff, 0x20, 0xf3 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "min.u d15, d15, #0xf"
+  -
+    input:
+      bytes: [ 0xdf, 0x04, 0xfd, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d4, #0, #-0x6"
+  -
+    input:
+      bytes: [ 0x8f, 0x34, 0x40, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or d15, d4, #0x3"
+  -
+    input:
+      bytes: [ 0x89, 0xff, 0xa0, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [a15]#0x20, d15"
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "calla #0"
+  -
+    input:
+      bytes: [ 0x1d, 0xff, 0xa6, 0xfe ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #-0x2b4"
+  -
+    input:
+      bytes: [ 0x80, 0x50 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.d d0, a5"
+  -
+    input:
+      bytes: [ 0x16, 0x0f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d15, #0xf"
+  -
+    input:
+      bytes: [ 0x3c, 0x1c ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x38"
+  -
+    input:
+      bytes: [ 0xee, 0x1f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz d15, #0x3e"
+  -
+    input:
+      bytes: [ 0x82, 0x0b ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d11, #0"
+  -
+    input:
+      bytes: [ 0x7f, 0xf8, 0x0a, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jge.u d8, d15, #0x14"
+  -
+    input:
+      bytes: [ 0x8f, 0x0a, 0x02, 0x11 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d1, d10, #0x20"
+  -
+    input:
+      bytes: [ 0x8b, 0x0f, 0xc0, 0x4a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "eqany.b d4, d15, #0"
+  -
+    input:
+      bytes: [ 0x49, 0xf2, 0x19, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a2, [a15]#0x19"
+  -
+    input:
+      bytes: [ 0xbf, 0x19, 0xe1, 0x7f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt d9, #0x1, #-0x3e"
+  -
+    input:
+      bytes: [ 0x3b, 0x00, 0x00, 0x31 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d3, #0x1000"
+  -
+    input:
+      bytes: [ 0x3c, 0x27 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x4e"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xf7, 0xf9 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0xc12"
+  -
+    input:
+      bytes: [ 0xbb, 0xf0, 0xff, 0x9f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.u d9, #0xffff"
+  -
+    input:
+      bytes: [ 0x60, 0x22 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.a a2, d2"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xac, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0xa8"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x3d, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x107a"
+  -
+    input:
+      bytes: [ 0xb7, 0x04, 0x02, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d4, #0, #0, #0x2"
+  -
+    input:
+      bytes: [ 0x2e, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.t d15, #0, #0x10"
+  -
+    input:
+      bytes: [ 0xd9, 0xaa, 0x40, 0x89 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea sp, [sp]#-0x6a00"
+  -
+    input:
+      bytes: [ 0x0b, 0x0c, 0x50, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ge.u d15, d12, d0"
+  -
+    input:
+      bytes: [ 0x49, 0xf2, 0x30, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a2, [a15]#0x30"
+  -
+    input:
+      bytes: [ 0x40, 0xfd ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.aa a13, a15"
+  -
+    input:
+      bytes: [ 0xf6, 0x83 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz d8, #0x6"
+  -
+    input:
+      bytes: [ 0x1d, 0x00, 0xcb, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x196"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x4c, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0xe98"
+  -
+    input:
+      bytes: [ 0x8f, 0xff, 0x83, 0x91 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor d9, d15, #0x3f"
+  -
+    input:
+      bytes: [ 0x3e, 0xe8 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d14, #0x10"
+  -
+    input:
+      bytes: [ 0x0b, 0x0f, 0x20, 0x11 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lt d1, d15, d0"
+  -
+    input:
+      bytes: [ 0x76, 0x26 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d2, #0xc"
+  -
+    input:
+      bytes: [ 0x02, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d7, d0"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xcc, 0xf9 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0xc68"
+  -
+    input:
+      bytes: [ 0xff, 0xdf, 0x33, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jge d15, #-0x3, #0x66"
+  -
+    input:
+      bytes: [ 0x12, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d0, d15, d8"
+  -
+    input:
+      bytes: [ 0xdf, 0x0c, 0xd3, 0x7f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d12, #0, #-0x5a"
+  -
+    input:
+      bytes: [ 0x3c, 0x62 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0xc4"
+  -
+    input:
+      bytes: [ 0xc2, 0x5f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d15, #0x5"
+  -
+    input:
+      bytes: [ 0xee, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz d15, #0x10"
+  -
+    input:
+      bytes: [ 0x37, 0xf0, 0x81, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d0, d15, #0x1, #0x1"
+  -
+    input:
+      bytes: [ 0x8b, 0x02, 0x20, 0xf2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ne d15, d2, #0"
+  -
+    input:
+      bytes: [ 0x1d, 0x00, 0x1b, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x36"
+  -
+    input:
+      bytes: [ 0x37, 0x0a, 0x50, 0x40 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr d4, d10, #0, #0x10"
+  -
+    input:
+      bytes: [ 0x7b, 0x10, 0x00, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh d15, #0x1"
+  -
+    input:
+      bytes: [ 0xd9, 0x22, 0x1a, 0x71 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a2, [a2]#0x11da"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x07, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x80e"
+  -
+    input:
+      bytes: [ 0x01, 0x2f, 0x20, 0xf4 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lt.a d15, a15, a2"
+  -
+    input:
+      bytes: [ 0x3b, 0x00, 0x07, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d0, #0x70"
+  -
+    input:
+      bytes: [ 0xbd, 0x0e, 0x1e, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.a a14, #0x3c"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0x40, 0x4b ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#-0x4b00"
+  -
+    input:
+      bytes: [ 0x40, 0x6d ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.aa a13, a6"
+  -
+    input:
+      bytes: [ 0x12, 0x19 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d9, d15, d1"
+  -
+    input:
+      bytes: [ 0x88, 0x9f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.h d15, [a15]#0x12"
+  -
+    input:
+      bytes: [ 0xdf, 0x00, 0x2e, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d0, #0, #0x5c"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xbe, 0x0f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x1f7c"
+  -
+    input:
+      bytes: [ 0x90, 0x22 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addsc.a a2, a2, d15, #0x2"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x79, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0xf2"
+  -
+    input:
+      bytes: [ 0xd9, 0x22, 0x3e, 0x61 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a2, [a2]#0x11be"
+  -
+    input:
+      bytes: [ 0x8b, 0x0f, 0x02, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d15, d15, #0x20"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xf2, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x9e4"
+  -
+    input:
+      bytes: [ 0x8f, 0x75, 0x00, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d15, d5, #0x7"
+  -
+    input:
+      bytes: [ 0xda, 0x20 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d15, #0x20"
+  -
+    input:
+      bytes: [ 0xab, 0x1f, 0x18, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "cadd d15, d15, d15, #-0x7f"
+  -
+    input:
+      bytes: [ 0x40, 0xc2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.aa a2, a12"
+  -
+    input:
+      bytes: [ 0x9b, 0x5e, 0xcf, 0xe3 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addih d14, d14, #0x3cf5"
+  -
+    input:
+      bytes: [ 0x0f, 0xf1, 0x00, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh d1, d1, d15"
+  -
+    input:
+      bytes: [ 0x3b, 0x00, 0x00, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d0, #0x1000"
+  -
+    input:
+      bytes: [ 0xd9, 0x55, 0x90, 0xca ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a5, [a5]#-0x54f0"
+  -
+    input:
+      bytes: [ 0x91, 0x20, 0x00, 0x48 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a4, #0x8002"
+  -
+    input:
+      bytes: [ 0x3f, 0xf8, 0xf0, 0x7f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt d8, d15, #-0x20"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xd0, 0x2b ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x1a860"
+  -
+    input:
+      bytes: [ 0xbf, 0x19, 0xef, 0x7f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt d9, #0x1, #-0x22"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xf6, 0xfe ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x214"
+  -
+    input:
+      bytes: [ 0x0f, 0x20, 0x10, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha d0, d0, d2"
+  -
+    input:
+      bytes: [ 0x7e, 0x2c ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, d2, #0x18"
+  -
+    input:
+      bytes: [ 0x02, 0x24 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d4, d2"
+  -
+    input:
+      bytes: [ 0x8b, 0x70, 0x01, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "rsub d0, d0, #0x17"
+  -
+    input:
+      bytes: [ 0xbb, 0x00, 0xc2, 0x0b ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.u d0, #0xbc20"
+  -
+    input:
+      bytes: [ 0x40, 0x64 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.aa a4, a6"
+  -
+    input:
+      bytes: [ 0xda, 0x58 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d15, #0x58"
+  -
+    input:
+      bytes: [ 0x49, 0xa6, 0x02, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a6, [sp]#0x2"
+  -
+    input:
+      bytes: [ 0x6f, 0x0f, 0x16, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz.t d15, #0, #0x2c"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0x1c, 0x0b ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#-0x4fe4"
+  -
+    input:
+      bytes: [ 0xbc, 0xf3 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.a a15, #0x6"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xa6, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0xb4"
+  -
+    input:
+      bytes: [ 0x8b, 0x03, 0xa0, 0x30 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addc d3, d3, #0"
+  -
+    input:
+      bytes: [ 0x5f, 0xef, 0x73, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d14, #0xe6"
+  -
+    input:
+      bytes: [ 0x1d, 0xff, 0x28, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #-0x1b0"
+  -
+    input:
+      bytes: [ 0x37, 0x0f, 0x02, 0xf3 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, d0, #0x6, #0x2"
+  -
+    input:
+      bytes: [ 0xd2, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov e4, #0"
+  -
+    input:
+      bytes: [ 0x82, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d0, #0"
+  -
+    input:
+      bytes: [ 0x4b, 0x30, 0x11, 0x42 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "div.u e4, d0, d3"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xcd, 0x0c ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x199a"
+  -
+    input:
+      bytes: [ 0x8f, 0xff, 0x83, 0xa1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor d10, d15, #0x3f"
+  -
+    input:
+      bytes: [ 0x3f, 0x10, 0xee, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt.u d0, d1, #-0x24"
+  -
+    input:
+      bytes: [ 0x16, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d15, #0x4"
+  -
+    input:
+      bytes: [ 0x3c, 0x1d ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x3a"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0xce, 0x61 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0x1d8e"
+  -
+    input:
+      bytes: [ 0x3b, 0xb0, 0x0d, 0x40 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d4, #0xdb"
+  -
+    input:
+      bytes: [ 0x49, 0xc2, 0x04, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a2, [a12]#0x4"
+  -
+    input:
+      bytes: [ 0x32, 0x52 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "rsub d2"
+  -
+    input:
+      bytes: [ 0xd9, 0xdd, 0xac, 0xba ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a13, [a13]#-0x5514"
+  -
+    input:
+      bytes: [ 0x7e, 0x13 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, d1, #0x6"
+  -
+    input:
+      bytes: [ 0xae, 0x22 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz.t d15, #0x2, #0x4"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0xcc, 0x51 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0x1d4c"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xfc, 0xf7 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x1008"
+  -
+    input:
+      bytes: [ 0x10, 0xaf ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addsc.a a15, sp, d15, #0"
+  -
+    input:
+      bytes: [ 0x7b, 0xc0, 0xff, 0x0f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh d0, #0xfffc"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x5d, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0xba"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0xe4, 0x2a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#-0x535c"
+  -
+    input:
+      bytes: [ 0x4b, 0x1f, 0x51, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "div.f d15, d15, d1"
+  -
+    input:
+      bytes: [ 0x9a, 0x48 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d15, d8, #0x4"
+  -
+    input:
+      bytes: [ 0x37, 0xf3, 0x08, 0x38 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d3, d3, d15, #0x10, #0x8"
+  -
+    input:
+      bytes: [ 0x82, 0x0c ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d12, #0"
+  -
+    input:
+      bytes: [ 0x6d, 0xe8, 0x91, 0x0b ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x2fe8de"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xae, 0x0d ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x1b5c"
+  -
+    input:
+      bytes: [ 0xb0, 0x4c ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add.a a12, #0x4"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x43, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x17a"
+  -
+    input:
+      bytes: [ 0xd9, 0xdd, 0xb0, 0xba ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a13, [a13]#-0x5510"
+  -
+    input:
+      bytes: [ 0x9b, 0x04, 0x05, 0x40 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addih d4, d4, #0x50"
+  -
+    input:
+      bytes: [ 0x1d, 0x00, 0x02, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x4"
+  -
+    input:
+      bytes: [ 0x37, 0x00, 0x61, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d0, d0, #0x6, #0x1"
+  -
+    input:
+      bytes: [ 0x6e, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d15, #0xc"
+  -
+    input:
+      bytes: [ 0xdf, 0x1f, 0x23, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, #0x1, #0x46"
+  -
+    input:
+      bytes: [ 0xb0, 0x1f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add.a a15, #0x1"
+  -
+    input:
+      bytes: [ 0xbf, 0x85, 0x23, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt.u d5, #0x8, #0x46"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x10, 0xfe ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x3e0"
+  -
+    input:
+      bytes: [ 0x40, 0x5f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.aa a15, a5"
+  -
+    input:
+      bytes: [ 0x3c, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x10"
+  -
+    input:
+      bytes: [ 0xdf, 0x0c, 0xe0, 0x7f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d12, #0, #-0x40"
+  -
+    input:
+      bytes: [ 0xd9, 0x22, 0x26, 0x11 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a2, [a2]#0x1066"
+  -
+    input:
+      bytes: [ 0xfe, 0x0c ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, d0, #0x38"
+  -
+    input:
+      bytes: [ 0x60, 0xf2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.a a2, d15"
+  -
+    input:
+      bytes: [ 0x2e, 0x36 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.t d15, #0x3, #0xc"
+  -
+    input:
+      bytes: [ 0x6f, 0x19, 0x13, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.t d9, #0x1, #0x26"
+  -
+    input:
+      bytes: [ 0x3f, 0x0f, 0xf0, 0x7f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt d15, d0, #-0x20"
+  -
+    input:
+      bytes: [ 0x4b, 0xf1, 0x51, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "div.f d0, d1, d15"
+  -
+    input:
+      bytes: [ 0xda, 0x7f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d15, #0x7f"
+  -
+    input:
+      bytes: [ 0xd9, 0x55, 0xc0, 0x88 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a5, [a5]#-0x7200"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0xb0, 0x21 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "clz d2, d0"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x67, 0xfe ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x332"
+  -
+    input:
+      bytes: [ 0x1d, 0x00, 0xaa, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x154"
+  -
+    input:
+      bytes: [ 0xf6, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz d0, #0x14"
+  -
+    input:
+      bytes: [ 0x2e, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.t d15, #0, #0x6"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xba, 0xf9 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0xc8c"
+  -
+    input:
+      bytes: [ 0x37, 0x0f, 0xe1, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d15, d15, #0x1, #0x1"
+  -
+    input:
+      bytes: [ 0x06, 0xec ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh d12, #-0x2"
+  -
+    input:
+      bytes: [ 0x37, 0xf0, 0x02, 0x0f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d0, d0, d15, #0x1e, #0x2"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0xfc, 0x11 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x23f8"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x32, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x19c"
+  -
+    input:
+      bytes: [ 0x37, 0x9f, 0x83, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, d9, #0x3, #0x3"
+  -
+    input:
+      bytes: [ 0x5f, 0x0f, 0x28, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d0, #0x50"
+  -
+    input:
+      bytes: [ 0xd9, 0x22, 0x22, 0x61 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a2, [a2]#0x11a2"
+  -
+    input:
+      bytes: [ 0x3b, 0x00, 0x50, 0x50 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d5, #0x500"
+  -
+    input:
+      bytes: [ 0x6f, 0x0f, 0xfe, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz.t d15, #0, #-0x4"
+  -
+    input:
+      bytes: [ 0xee, 0xfe ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz d15, #-0x4"
+  -
+    input:
+      bytes: [ 0xdf, 0x08, 0x6a, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d8, #0, #0xd4"
+  -
+    input:
+      bytes: [ 0x7f, 0xf0, 0x50, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jge d0, d15, #0xa0"
+  -
+    input:
+      bytes: [ 0xee, 0x22 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz d15, #0x44"
+  -
+    input:
+      bytes: [ 0x8f, 0xf0, 0x01, 0x20 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh d2, d0, #0x1f"
+  -
+    input:
+      bytes: [ 0x02, 0x92 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d2, d9"
+  -
+    input:
+      bytes: [ 0x8f, 0x21, 0x00, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh d15, d1, #0x2"
+  -
+    input:
+      bytes: [ 0x3b, 0x00, 0x08, 0x50 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d5, #0x80"
+  -
+    input:
+      bytes: [ 0x4e, 0xf3 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jgtz d15, #0x6"
+  -
+    input:
+      bytes: [ 0xee, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz d15, #0x6"
+  -
+    input:
+      bytes: [ 0xac, 0xa2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [sp]#0x4, d15"
+  -
+    input:
+      bytes: [ 0xb7, 0x1f, 0x81, 0x2b ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d2, d15, #0x1, #0x17, #0x1"
+  -
+    input:
+      bytes: [ 0x3b, 0x70, 0x04, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d1, #0x47"
+  -
+    input:
+      bytes: [ 0x20, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub.a sp, #0x8"
+  -
+    input:
+      bytes: [ 0x8b, 0x03, 0x03, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d15, d3, #0x30"
+  -
+    input:
+      bytes: [ 0x9a, 0xf0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d15, d0, #-0x1"
+  -
+    input:
+      bytes: [ 0xd9, 0x55, 0x3c, 0xea ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a5, [a5]#-0x5c44"
+  -
+    input:
+      bytes: [ 0x09, 0x41, 0x84, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.h d1, [a4]#0x4"
+  -
+    input:
+      bytes: [ 0x89, 0xaf, 0xa4, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [sp]#0x24, d15"
+  -
+    input:
+      bytes: [ 0xa0, 0x55 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.a a5, #0x5"
+  -
+    input:
+      bytes: [ 0x37, 0x0f, 0xe8, 0x1b ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d1, d15, #0x17, #0x8"
+  -
+    input:
+      bytes: [ 0x3c, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x2"
+  -
+    input:
+      bytes: [ 0x37, 0x00, 0x68, 0x50 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d5, d0, #0, #0x8"
+  -
+    input:
+      bytes: [ 0x5f, 0x8f, 0x66, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d8, #0xcc"
+  -
+    input:
+      bytes: [ 0xda, 0x22 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d15, #0x22"
+  -
+    input:
+      bytes: [ 0x49, 0x33, 0x14, 0x8a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a3, [a3]#-0x1ec"
+  -
+    input:
+      bytes: [ 0x8f, 0x0a, 0x50, 0xa1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or d10, d10, #0x100"
+  -
+    input:
+      bytes: [ 0x91, 0x00, 0x00, 0x28 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a2, #0x8000"
+  -
+    input:
+      bytes: [ 0x8f, 0x28, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha d0, d8, #0x2"
+  -
+    input:
+      bytes: [ 0x49, 0x44, 0x00, 0x1a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a4, [a4]#0x40"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x49, 0x11 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x2292"
+  -
+    input:
+      bytes: [ 0xee, 0x17 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz d15, #0x2e"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x8b, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0x516"
+  -
+    input:
+      bytes: [ 0x5f, 0x0f, 0xdf, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d0, #0x1be"
+  -
+    input:
+      bytes: [ 0xa6, 0x52 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or d2, d5"
+  -
+    input:
+      bytes: [ 0x1e, 0xf3 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, #-0x1, #0x6"
+  -
+    input:
+      bytes: [ 0x37, 0xf0, 0x02, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d0, d0, d15, #0x4, #0x2"
+  -
+    input:
+      bytes: [ 0xdf, 0x0f, 0x68, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, #0, #-0x130"
+  -
+    input:
+      bytes: [ 0x06, 0x11 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh d1, #0x1"
+  -
+    input:
+      bytes: [ 0x37, 0x0f, 0x02, 0xfe ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d15, d15, d0, #0x1c, #0x2"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x94, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0xd8"
+  -
+    input:
+      bytes: [ 0x2d, 0x0f, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "calli a15"
+  -
+    input:
+      bytes: [ 0x0b, 0x75, 0x00, 0xf2 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.eq d15, d5, d7"
+  -
+    input:
+      bytes: [ 0x82, 0x54 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d4, #0x5"
+  -
+    input:
+      bytes: [ 0x37, 0xf0, 0x02, 0x0e ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d0, d0, d15, #0x1c, #0x2"
+  -
+    input:
+      bytes: [ 0xee, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz d15, #-0x1e"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xeb, 0x3d ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x1842a"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0xe4, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0xc64"
+  -
+    input:
+      bytes: [ 0x5f, 0x01, 0x0d, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d1, d0, #0x1a"
+  -
+    input:
+      bytes: [ 0x91, 0x30, 0x00, 0x57 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a5, #0x7003"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x00, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov e0, d0"
+  -
+    input:
+      bytes: [ 0xde, 0x1c ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, #0x1, #0x38"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xb1, 0x2a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x1aa9e"
+  -
+    input:
+      bytes: [ 0x7b, 0x00, 0x12, 0xd4 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh d13, #0x4120"
+  -
+    input:
+      bytes: [ 0x49, 0xf2, 0x08, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a2, [a15]#0x8"
+  -
+    input:
+      bytes: [ 0x37, 0xf0, 0x03, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d0, d0, d15, #0x8, #0x3"
+  -
+    input:
+      bytes: [ 0xee, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz d15, #0x4"
+  -
+    input:
+      bytes: [ 0x06, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh d1, #-0x1"
+  -
+    input:
+      bytes: [ 0x7e, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, d0, #0x6"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0x58, 0xfb ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x950"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0x20, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0x60"
+  -
+    input:
+      bytes: [ 0x6d, 0xff, 0xa7, 0xfe ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #-0x2b2"
+  -
+    input:
+      bytes: [ 0x02, 0x68 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d8, d6"
+  -
+    input:
+      bytes: [ 0x1d, 0x00, 0x8a, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x314"
+  -
+    input:
+      bytes: [ 0xd7, 0x10, 0x21, 0x0f ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "imask e0, #0x1, d15, #0x1"
+  -
+    input:
+      bytes: [ 0x49, 0xa4, 0x08, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a4, [sp]#0x8"
+  -
+    input:
+      bytes: [ 0x82, 0x34 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d4, #0x3"
+  -
+    input:
+      bytes: [ 0x92, 0x44 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d4, d15, #0x4"
+  -
+    input:
+      bytes: [ 0x91, 0x20, 0x00, 0xd8 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a13, #0x8002"
+  -
+    input:
+      bytes: [ 0x82, 0xf1 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d1, #-0x1"
+  -
+    input:
+      bytes: [ 0x3b, 0x80, 0x00, 0x40 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d4, #0x8"
+  -
+    input:
+      bytes: [ 0x3c, 0x3a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x74"
+  -
+    input:
+      bytes: [ 0x82, 0x64 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d4, #0x6"
+  -
+    input:
+      bytes: [ 0x01, 0x2f, 0x30, 0xf4 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ge.a d15, a15, a2"
+  -
+    input:
+      bytes: [ 0xd9, 0xff, 0x24, 0x96 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a15, [a15]#0x6264"
+  -
+    input:
+      bytes: [ 0x8e, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlez d15, #0x1e"
+  -
+    input:
+      bytes: [ 0x91, 0x00, 0x00, 0x48 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a4, #0x8000"
+  -
+    input:
+      bytes: [ 0xa6, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or d0, d1"
+  -
+    input:
+      bytes: [ 0xdc, 0x0e ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ji a14"
+  -
+    input:
+      bytes: [ 0x1d, 0x00, 0x83, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0x106"
+  -
+    input:
+      bytes: [ 0xd9, 0x22, 0x4c, 0xb0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a2, [a2]#0x6cc"
+  -
+    input:
+      bytes: [ 0x5f, 0x0f, 0x29, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d0, #0x52"
+  -
+    input:
+      bytes: [ 0x37, 0x00, 0xe8, 0xfb ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d15, d0, #0x17, #0x8"
+  -
+    input:
+      bytes: [ 0x6f, 0x0f, 0xf5, 0xff ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz.t d15, #0, #-0x16"
+  -
+    input:
+      bytes: [ 0x3b, 0xb0, 0x02, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d0, #0x2b"
+  -
+    input:
+      bytes: [ 0x7c, 0x2a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz.a a2, #0x14"
diff --git a/tests/MC/TriCore/ldst_br_circ.s.yaml b/tests/MC/TriCore/ldst_br_circ.s.yaml
new file mode 100644
index 000000000..34fc412cc
--- /dev/null
+++ b/tests/MC/TriCore/ldst_br_circ.s.yaml
@@ -0,0 +1,415 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x80, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachea.i [p0+r]"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x8a, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachea.i [p0+c]#0xa"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x00, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachea.w [p0+r]"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x0a, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachea.w [p0+c]#0xa"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x40, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachea.wi [p0+r]"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x4a, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachea.wi [p0+c]#0xa"
+  -
+    input:
+      bytes: [ 0x69, 0x02, 0xc0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpswap.w [p0+r], e2"
+  -
+    input:
+      bytes: [ 0x69, 0x02, 0xca, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpswap.w [p0+c]#0xa, e2"
+  -
+    input:
+      bytes: [ 0x29, 0x02, 0x80, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.a a2, [p0+r]"
+  -
+    input:
+      bytes: [ 0x29, 0x02, 0x8a, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.a a2, [p0+c]#0xa"
+  -
+    input:
+      bytes: [ 0x29, 0x02, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.b d2, [p0+r]"
+  -
+    input:
+      bytes: [ 0x29, 0x02, 0x0a, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.b d2, [p0+c]#0xa"
+  -
+    input:
+      bytes: [ 0x29, 0x02, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d2, [p0+r]"
+  -
+    input:
+      bytes: [ 0x29, 0x02, 0x4a, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d2, [p0+c]#0xa"
+  -
+    input:
+      bytes: [ 0x29, 0x02, 0x40, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.d e2, [p0+r]"
+  -
+    input:
+      bytes: [ 0x29, 0x02, 0x4a, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.d e2, [p0+c]#0xa"
+  -
+    input:
+      bytes: [ 0x29, 0x02, 0xc0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.da p2, [p0+r]"
+  -
+    input:
+      bytes: [ 0x29, 0x02, 0xca, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.da p2, [p0+c]#0xa"
+  -
+    input:
+      bytes: [ 0x29, 0x02, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.h d2, [p0+r]"
+  -
+    input:
+      bytes: [ 0x29, 0x02, 0x8a, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.h d2, [p0+c]#0xa"
+  -
+    input:
+      bytes: [ 0x29, 0x02, 0xc0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.hu d2, [p0+r]"
+  -
+    input:
+      bytes: [ 0x29, 0x02, 0xca, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.hu d2, [p0+c]#0xa"
+  -
+    input:
+      bytes: [ 0x29, 0x02, 0x00, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.q d2, [p0+r]"
+  -
+    input:
+      bytes: [ 0x29, 0x02, 0x0a, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.q d2, [p0+c]#0xa"
+  -
+    input:
+      bytes: [ 0x29, 0x02, 0x00, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d2, [p0+r]"
+  -
+    input:
+      bytes: [ 0x29, 0x02, 0x0a, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d2, [p0+c]#0xa"
+  -
+    input:
+      bytes: [ 0x69, 0x02, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldmst [p0+r], e2"
+  -
+    input:
+      bytes: [ 0x69, 0x02, 0x4a, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldmst [p0+c]#0xa, e2"
+  -
+    input:
+      bytes: [ 0xa9, 0x02, 0x80, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.a [p0+r], a2"
+  -
+    input:
+      bytes: [ 0xa9, 0x02, 0x8a, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.a [p0+c]#0xa, a2"
+  -
+    input:
+      bytes: [ 0xa9, 0x02, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [p0+r], d2"
+  -
+    input:
+      bytes: [ 0xa9, 0x02, 0x0a, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [p0+c]#0xa, d2"
+  -
+    input:
+      bytes: [ 0xa9, 0x02, 0x40, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.d [p0+r], e2"
+  -
+    input:
+      bytes: [ 0xa9, 0x02, 0x4a, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.d [p0+c]#0xa, e2"
+  -
+    input:
+      bytes: [ 0xa9, 0x02, 0xc0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.da [p0+r], p2"
+  -
+    input:
+      bytes: [ 0xa9, 0x02, 0xca, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.da [p0+c]#0xa, p2"
+  -
+    input:
+      bytes: [ 0xa9, 0x02, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [p0+r], d2"
+  -
+    input:
+      bytes: [ 0xa9, 0x02, 0x8a, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [p0+c]#0xa, d2"
+  -
+    input:
+      bytes: [ 0xa9, 0x02, 0x00, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.q [p0+r], d2"
+  -
+    input:
+      bytes: [ 0xa9, 0x02, 0x0a, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.q [p0+c]#0xa, d2"
+  -
+    input:
+      bytes: [ 0xa9, 0x02, 0x00, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w [p0+r], d2"
+  -
+    input:
+      bytes: [ 0xa9, 0x02, 0x0a, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w [p0+c]#0xa, d2"
+  -
+    input:
+      bytes: [ 0x69, 0x02, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "swap.w [p0+r], d2"
+  -
+    input:
+      bytes: [ 0x69, 0x02, 0x0a, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "swap.w [p0+c]#0xa, d2"
+  -
+    input:
+      bytes: [ 0x69, 0x02, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "swapmsk.w [p0+r], e2"
+  -
+    input:
+      bytes: [ 0x69, 0x02, 0x8a, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "swapmsk.w [p0+c]#0xa, e2"
diff --git a/tests/MC/TriCore/rr_insn.s.yaml b/tests/MC/TriCore/rr_insn.s.yaml
new file mode 100644
index 000000000..5f75b11a7
--- /dev/null
+++ b/tests/MC/TriCore/rr_insn.s.yaml
@@ -0,0 +1,46 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x0b, 0x20, 0xc0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "abs d0, d2"
+  -
+    input:
+      bytes: [ 0x0b, 0x60, 0xc0, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "abs.b d0, d6"
+  -
+    input:
+      bytes: [ 0x0b, 0x40, 0xc0, 0x27 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "abs.h d2, d4"
+  -
+    input:
+      bytes: [ 0x0b, 0x10, 0xd0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "abss d0, d1"
+  -
+    input:
+      bytes: [ 0x0b, 0x10, 0xd0, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "abss.h d0, d1"
diff --git a/tests/MC/TriCore/tc110.s.yaml b/tests/MC/TriCore/tc110.s.yaml
new file mode 100644
index 000000000..f7af4985f
--- /dev/null
+++ b/tests/MC/TriCore/tc110.s.yaml
@@ -0,0 +1,5617 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xc0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "abs d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xc0, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "abs.b d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xc0, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "abs.h d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xe0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "absdif d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0xc0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "absdif d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xe0, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "absdif.b d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xe0, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "absdif.h d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xf0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "absdifs d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0xe0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "absdifs d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xf0, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "absdifs.b d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xf0, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "absdifs.h d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xd0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "abss d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xd0, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "abss.b d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xd0, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "abss.h d0, d0"
+  -
+    input:
+      bytes: [ 0x1a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d15, d0, d0"
+  -
+    input:
+      bytes: [ 0x42, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d0, d0"
+  -
+    input:
+      bytes: [ 0x9a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d15, d0, #0"
+  -
+    input:
+      bytes: [ 0xc2, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0x10, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "add.a a0, a0, a0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "add.b d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x00, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "add.h d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x50, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "addc d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0xa0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "addc d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x1b, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "addi d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x9b, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "addih d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x11, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "addih.a a0, a0, #0"
+  -
+    input:
+      bytes: [ 0x22, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "adds d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "adds d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "adds d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x20, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "adds.b d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x30, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "adds.bu d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x20, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "adds.h d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x30, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "adds.hu d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x30, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "adds.u d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "adds.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x10, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "addsc.a a0, d0, #0"
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0x00, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "addsc.a a0, a0, d0, #0"
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0x20, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "addsc.at a0, a0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "addx d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "addx d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x16, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d0, d0"
+  -
+    input:
+      bytes: [ 0x96, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d15, #0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8f, 0x00, 0x00, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x47, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.and.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x47, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.andn.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x00, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.eq d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.eq d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x40, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.ge d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x80, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.ge d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x50, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.ge.u d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0xa0, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.ge.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x20, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.lt d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x40, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.lt d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x30, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.lt.u d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x60, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.lt.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x10, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.ne d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x20, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.ne d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x47, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.nor.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x47, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.or.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x87, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0xe0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "andn d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8f, 0x00, 0xc0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "andn d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x87, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "andn.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0xc0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "bisr #0"
+  -
+    input:
+      bytes: [ 0xad, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "bisr #0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "bmerge d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0x00, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "bsplit e0, d0"
+  -
+    input:
+      bytes: [ 0x0a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "cadd d0, d15, d0"
+  -
+    input:
+      bytes: [ 0x8a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "cadd d0, d15, #0"
+  -
+    input:
+      bytes: [ 0x2b, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "cadd d0, d0, d0, d0"
+  -
+    input:
+      bytes: [ 0xab, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "cadd d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x21, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "cadd.a a0, d0, a0, a0"
+  -
+    input:
+      bytes: [ 0xa1, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "cadd.a a0, d0, a0, #0"
+  -
+    input:
+      bytes: [ 0x4a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "caddn d0, d15, d0"
+  -
+    input:
+      bytes: [ 0xca, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "caddn d0, d15, #0"
+  -
+    input:
+      bytes: [ 0x2b, 0x00, 0x10, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "caddn d0, d0, d0, d0"
+  -
+    input:
+      bytes: [ 0xab, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "caddn d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x21, 0x00, 0x10, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "caddn.a a0, d0, a0, a0"
+  -
+    input:
+      bytes: [ 0xa1, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "caddn.a a0, d0, a0, #0"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0"
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "calla #0"
+  -
+    input:
+      bytes: [ 0x2d, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "calli a0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0xc0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "clo d0, d0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0xd0, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "clo.b d0, d0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0xd0, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "clo.h d0, d0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0xd0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "cls d0, d0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0xe0, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "cls.b d0, d0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0xe0, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "cls.h d0, d0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0xb0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "clz d0, d0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0xc0, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "clz.b d0, d0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0xc0, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "clz.h d0, d0"
+  -
+    input:
+      bytes: [ 0x2a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmov d0, d15, d0"
+  -
+    input:
+      bytes: [ 0xaa, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmov d0, d15, #0"
+  -
+    input:
+      bytes: [ 0x6a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmovn d0, d15, d0"
+  -
+    input:
+      bytes: [ 0xea, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmovn d0, d15, #0"
+  -
+    input:
+      bytes: [ 0x2b, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "csub d0, d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x21, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "csub.a a0, d0, a0, a0"
+  -
+    input:
+      bytes: [ 0x2b, 0x00, 0x30, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "csubn d0, d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x21, 0x00, 0x30, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "csubn.a a0, d0, a0, a0"
+  -
+    input:
+      bytes: [ 0x00, 0xa0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "debug"
+  -
+    input:
+      bytes: [ 0x0d, 0x00, 0x00, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "debug"
+  -
+    input:
+      bytes: [ 0x77, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "dextr d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x17, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "dextr d0, d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0x00, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "difsc.a d0, a0, a0, #0"
+  -
+    input:
+      bytes: [ 0x0d, 0x00, 0x40, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "disable"
+  -
+    input:
+      bytes: [ 0x0d, 0x00, 0x80, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "dsync"
+  -
+    input:
+      bytes: [ 0x72, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "dvadj e0, d0"
+  -
+    input:
+      bytes: [ 0x2b, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "dvadj e0, e0, d0"
+  -
+    input:
+      bytes: [ 0x4f, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "dvinit e0, d0, d0"
+  -
+    input:
+      bytes: [ 0x4f, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "dvinit.b e0, d0, d0"
+  -
+    input:
+      bytes: [ 0x4f, 0x00, 0x50, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "dvinit.bu e0, d0, d0"
+  -
+    input:
+      bytes: [ 0x4f, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "dvinit.h e0, d0, d0"
+  -
+    input:
+      bytes: [ 0x4f, 0x00, 0x30, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "dvinit.hu e0, d0, d0"
+  -
+    input:
+      bytes: [ 0x4f, 0x00, 0x10, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "dvinit.u e0, d0, d0"
+  -
+    input:
+      bytes: [ 0x32, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "dvstep e0, d0"
+  -
+    input:
+      bytes: [ 0x2b, 0x00, 0x90, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "dvstep e0, e0, d0"
+  -
+    input:
+      bytes: [ 0xb2, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "dvstep.u e0, d0"
+  -
+    input:
+      bytes: [ 0x2b, 0x00, 0xa0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "dvstep.u e0, e0, d0"
+  -
+    input:
+      bytes: [ 0x0d, 0x00, 0x00, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "enable"
+  -
+    input:
+      bytes: [ 0x3a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "eq d15, d0, d0"
+  -
+    input:
+      bytes: [ 0xba, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "eq d15, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x00, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "eq d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x00, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "eq d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "eq.a d0, a0, a0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x00, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "eq.b d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x00, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "eq.h d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x00, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "eq.w d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x60, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "eqany.b d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0xc0, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "eqany.b d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x60, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "eqany.h d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0xc0, 0x0e ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "eqany.h d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0x80, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "eqz.a d0, a0"
+  -
+    input:
+      bytes: [ 0x17, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr d0, d0, e0"
+  -
+    input:
+      bytes: [ 0x37, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr d0, d0, #0, #0"
+  -
+    input:
+      bytes: [ 0x57, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x17, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d0, d0, e0"
+  -
+    input:
+      bytes: [ 0x37, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d0, d0, #0, #0"
+  -
+    input:
+      bytes: [ 0x57, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x40, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "ge d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x80, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "ge d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0x30, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "ge.a d0, a0, a0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x50, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "ge.u d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0xa0, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "ge.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x37, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "imask e0, d0, #0, #0"
+  -
+    input:
+      bytes: [ 0x57, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "imask e0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0xb7, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "imask e0, #0, #0, #0"
+  -
+    input:
+      bytes: [ 0xd7, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "imask e0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x67, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "ins.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x17, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d0, d0, d0, e0"
+  -
+    input:
+      bytes: [ 0x37, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d0, d0, d0, #0, #0"
+  -
+    input:
+      bytes: [ 0x57, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d0, d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x97, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d0, d0, #0, e0"
+  -
+    input:
+      bytes: [ 0xb7, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d0, d0, #0, #0, #0"
+  -
+    input:
+      bytes: [ 0xd7, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x67, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "insn.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0d, 0x00, 0xc0, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "isync"
+  -
+    input:
+      bytes: [ 0x5c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0"
+  -
+    input:
+      bytes: [ 0x1d, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0"
+  -
+    input:
+      bytes: [ 0x9d, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "ja #0"
+  -
+    input:
+      bytes: [ 0x1e, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d0, #0"
+  -
+    input:
+      bytes: [ 0x6e, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, #0, #0"
+  -
+    input:
+      bytes: [ 0x5f, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d0, d0, #0"
+  -
+    input:
+      bytes: [ 0xdf, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d0, #0, #0"
+  -
+    input:
+      bytes: [ 0x7d, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq.a a0, a0, #0"
+  -
+    input:
+      bytes: [ 0x7f, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "jge d0, d0, #0"
+  -
+    input:
+      bytes: [ 0xff, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "jge d0, #0, #0"
+  -
+    input:
+      bytes: [ 0x7f, 0x00, 0x00, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "jge.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0xff, 0x00, 0x00, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "jge.u d0, #0, #0"
+  -
+    input:
+      bytes: [ 0xfe, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "jgez d0, #0"
+  -
+    input:
+      bytes: [ 0x7e, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "jgtz d0, #0"
+  -
+    input:
+      bytes: [ 0x3c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "ji a0"
+  -
+    input:
+      bytes: [ 0x2d, 0x00, 0x30, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "ji a0"
+  -
+    input:
+      bytes: [ 0x5d, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "jl #0"
+  -
+    input:
+      bytes: [ 0xdd, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "jla #0"
+  -
+    input:
+      bytes: [ 0xbe, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlez d0, #0"
+  -
+    input:
+      bytes: [ 0x2d, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "jli a0"
+  -
+    input:
+      bytes: [ 0x3f, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt d0, d0, #0"
+  -
+    input:
+      bytes: [ 0xbf, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt d0, #0, #0"
+  -
+    input:
+      bytes: [ 0x3f, 0x00, 0x00, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0xbf, 0x00, 0x00, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt.u d0, #0, #0"
+  -
+    input:
+      bytes: [ 0x3e, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "jltz d0, #0"
+  -
+    input:
+      bytes: [ 0x9e, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, d0, #0"
+  -
+    input:
+      bytes: [ 0xee, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, #0, #0"
+  -
+    input:
+      bytes: [ 0x5f, 0x00, 0x00, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d0, d0, #0"
+  -
+    input:
+      bytes: [ 0xdf, 0x00, 0x00, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d0, #0, #0"
+  -
+    input:
+      bytes: [ 0x7d, 0x00, 0x00, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne.a a0, a0, #0"
+  -
+    input:
+      bytes: [ 0x1f, 0x00, 0x00, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "jned d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x9f, 0x00, 0x00, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "jned d0, #0, #0"
+  -
+    input:
+      bytes: [ 0x1f, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnei d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x9f, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnei d0, #0, #0"
+  -
+    input:
+      bytes: [ 0xae, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz d15, #0"
+  -
+    input:
+      bytes: [ 0xde, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz d0, #0"
+  -
+    input:
+      bytes: [ 0x7c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz.a a0, #0"
+  -
+    input:
+      bytes: [ 0xbd, 0x00, 0x00, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz.a a0, #0"
+  -
+    input:
+      bytes: [ 0x4e, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz.t d15, #0, #0"
+  -
+    input:
+      bytes: [ 0x6f, 0x00, 0x00, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz.t d0, #0, #0"
+  -
+    input:
+      bytes: [ 0x2e, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d15, #0"
+  -
+    input:
+      bytes: [ 0x5e, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d0, #0"
+  -
+    input:
+      bytes: [ 0xbc, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.a a0, #0"
+  -
+    input:
+      bytes: [ 0xbd, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.a a0, #0"
+  -
+    input:
+      bytes: [ 0x0e, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.t d15, #0, #0"
+  -
+    input:
+      bytes: [ 0x6f, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.t d0, #0, #0"
+  -
+    input:
+      bytes: [ 0x0c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.a a0, [a15]#0"
+  -
+    input:
+      bytes: [ 0x28, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.a a15, [a0]#0"
+  -
+    input:
+      bytes: [ 0x64, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.a a0, [a0+]"
+  -
+    input:
+      bytes: [ 0xb8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.a a0, [a0]"
+  -
+    input:
+      bytes: [ 0x99, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.a a0, [a0]#0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x80, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.a a0, [a0+]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0x80, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.a a0, [p0+r]"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x80, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.a a0, [+a0]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0x80, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.a a0, [p0+c]#0"
+  -
+    input:
+      bytes: [ 0x85, 0x00, 0x00, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.a a0, #0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x80, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.a a0, [a0]#0"
+  -
+    input:
+      bytes: [ 0x08, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.b d15, [a0]#0"
+  -
+    input:
+      bytes: [ 0x34, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.b d0, [a15]#0"
+  -
+    input:
+      bytes: [ 0x44, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.b d0, [a0+]"
+  -
+    input:
+      bytes: [ 0x98, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.b d0, [a0]"
+  -
+    input:
+      bytes: [ 0x05, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.b d0, #0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.b d0, [a0+]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.b d0, [p0+r]"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.b d0, [+a0]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.b d0, [p0+c]#0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x00, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.b d0, [a0]#0"
+  -
+    input:
+      bytes: [ 0x58, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d0, [a0]"
+  -
+    input:
+      bytes: [ 0x88, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d15, [a0]#0"
+  -
+    input:
+      bytes: [ 0xb4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d0, [a15]#0"
+  -
+    input:
+      bytes: [ 0xc4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d0, [a0+]"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d0, [a0+]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d0, [p0+r]"
+  -
+    input:
+      bytes: [ 0x05, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d0, #0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x40, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d0, [+a0]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0x40, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d0, [p0+c]#0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x40, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d0, [a0]#0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x40, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.d e0, [a0+]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0x40, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.d e0, [p0+r]"
+  -
+    input:
+      bytes: [ 0x85, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.d e0, #0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x40, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.d e0, [+a0]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0x40, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.d e0, [p0+c]#0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x40, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.d e0, [a0]#0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0xc0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.da p0, [a0+]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0xc0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.da p0, [p0+r]"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0xc0, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.da p0, [+a0]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0xc0, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.da p0, [p0+c]#0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0xc0, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.da p0, [a0]#0"
+  -
+    input:
+      bytes: [ 0x85, 0x00, 0x00, 0x0c ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.da p0, #0"
+  -
+    input:
+      bytes: [ 0x24, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.h d0, [a0+]"
+  -
+    input:
+      bytes: [ 0x48, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.h d15, [a0]#0"
+  -
+    input:
+      bytes: [ 0x74, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.h d0, [a15]#0"
+  -
+    input:
+      bytes: [ 0xd8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.h d0, [a0]"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.h d0, [a0+]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.h d0, [p0+r]"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x80, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.h d0, [+a0]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0x80, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.h d0, [p0+c]#0"
+  -
+    input:
+      bytes: [ 0x05, 0x00, 0x00, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.h d0, #0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x80, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.h d0, [a0]#0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0xc0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.hu d0, [a0+]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0xc0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.hu d0, [p0+r]"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0xc0, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.hu d0, [+a0]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0xc0, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.hu d0, [p0+c]#0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0xc0, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.hu d0, [a0]#0"
+  -
+    input:
+      bytes: [ 0x05, 0x00, 0x00, 0x0c ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.hu d0, #0"
+  -
+    input:
+      bytes: [ 0x45, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.q d0, #0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x00, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.q d0, [a0+]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0x00, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.q d0, [p0+r]"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x00, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.q d0, [+a0]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0x00, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.q d0, [p0+c]#0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x00, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.q d0, [a0]#0"
+  -
+    input:
+      bytes: [ 0x38, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d0, [a0]"
+  -
+    input:
+      bytes: [ 0xa4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d0, [a0+]"
+  -
+    input:
+      bytes: [ 0xc8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d15, [a0]#0"
+  -
+    input:
+      bytes: [ 0xf4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d0, [a15]#0"
+  -
+    input:
+      bytes: [ 0x19, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d0, [a0]#0"
+  -
+    input:
+      bytes: [ 0x85, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d0, #0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x00, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d0, [a0+]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0x00, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d0, [p0+r]"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x00, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d0, [+a0]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0x00, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d0, [p0+c]#0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x00, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d0, [a0]#0"
+  -
+    input:
+      bytes: [ 0x15, 0x00, 0x00, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldlcx #0"
+  -
+    input:
+      bytes: [ 0x49, 0x00, 0x00, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldlcx [a0]#0"
+  -
+    input:
+      bytes: [ 0x49, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldmst [a0+]#0, e0"
+  -
+    input:
+      bytes: [ 0x69, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldmst [p0+r], e0"
+  -
+    input:
+      bytes: [ 0xe5, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldmst #0, e0"
+  -
+    input:
+      bytes: [ 0x49, 0x00, 0x40, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldmst [+a0]#0, e0"
+  -
+    input:
+      bytes: [ 0x69, 0x00, 0x40, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldmst [p0+c]#0, e0"
+  -
+    input:
+      bytes: [ 0x49, 0x00, 0x40, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldmst [a0]#0, e0"
+  -
+    input:
+      bytes: [ 0x49, 0x00, 0x40, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "lducx [a0]#0"
+  -
+    input:
+      bytes: [ 0x15, 0x00, 0x00, 0x0c ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "lducx #0"
+  -
+    input:
+      bytes: [ 0xc5, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a0, #0"
+  -
+    input:
+      bytes: [ 0xd9, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a0, [a0]#0"
+  -
+    input:
+      bytes: [ 0x49, 0x00, 0x00, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a0, [a0]#0"
+  -
+    input:
+      bytes: [ 0xfc, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "loop a0, #0xffffffe0"
+  -
+    input:
+      bytes: [ 0xfd, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "loop a0, #0"
+  -
+    input:
+      bytes: [ 0x7a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "lt d15, d0, d0"
+  -
+    input:
+      bytes: [ 0xfa, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "lt d15, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x20, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "lt d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x40, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "lt d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0x20, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "lt.a d0, a0, a0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x20, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "lt.b d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x30, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "lt.bu d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x20, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "lt.h d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x30, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "lt.hu d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x06, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "lt.u d15, d0, d0"
+  -
+    input:
+      bytes: [ 0x86, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "lt.u d15, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x30, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "lt.u d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x60, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "lt.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x20, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "lt.w d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x30, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "lt.wu d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x03, 0x00, 0x0a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd d0, d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x13, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd.h e0, e0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x10, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd.q d0, d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x13, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddm e0, e0, d0, #0"
+  -
+    input:
+      bytes: [ 0x03, 0x00, 0x6a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddm e0, e0, d0, d0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0x70, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddm.h e0, e0, d0, d0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x70, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddm.q e0, e0, d0, d0"
+  -
+    input:
+      bytes: [ 0x13, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddm.u e0, e0, d0, #0"
+  -
+    input:
+      bytes: [ 0x03, 0x00, 0x68, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddm.u e0, e0, d0, d0"
+  -
+    input:
+      bytes: [ 0x13, 0x00, 0xe0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddms e0, e0, d0, #0"
+  -
+    input:
+      bytes: [ 0x03, 0x00, 0xea, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddms e0, e0, d0, d0"
+  -
+    input:
+      bytes: [ 0x13, 0x00, 0xc0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddms.u e0, e0, d0, #0"
+  -
+    input:
+      bytes: [ 0x03, 0x00, 0xe8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddms.u e0, e0, d0, d0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x78, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddr.h d0, e0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x18, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddr.q d0, d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0xf8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddrs.h d0, e0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x98, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddrs.q d0, d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x03, 0x00, 0x8a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds d0, d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x13, 0x00, 0xa0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0xe0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds.h e0, e0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x90, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds.q d0, d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x13, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds.u d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x03, 0x00, 0x88, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds.u d0, d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xa0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "max d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x40, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "max d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xa0, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "max.b d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xb0, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "max.bu d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xa0, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "max.h d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xb0, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "max.hu d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xb0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "max.u d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x60, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "max.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x4d, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "mfcr d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x80, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "min d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x00, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "min d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x80, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "min.b d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x90, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "min.bu d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x80, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "min.h d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x90, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "min.hu d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x90, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "min.u d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x20, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "min.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x02, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d0, d0"
+  -
+    input:
+      bytes: [ 0x82, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d0, #0"
+  -
+    input:
+      bytes: [ 0xc6, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d15, #0"
+  -
+    input:
+      bytes: [ 0x3b, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xf0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d0, d0"
+  -
+    input:
+      bytes: [ 0x30, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.a a0, d0"
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0x30, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.a a0, d0"
+  -
+    input:
+      bytes: [ 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.aa a0, a0"
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.aa a0, a0"
+  -
+    input:
+      bytes: [ 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.d d0, a0"
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0xc0, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.d d0, a0"
+  -
+    input:
+      bytes: [ 0xbb, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.u d0, #0"
+  -
+    input:
+      bytes: [ 0x7b, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh d0, #0"
+  -
+    input:
+      bytes: [ 0x91, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a0, #0"
+  -
+    input:
+      bytes: [ 0x00, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "movz.a a0"
+  -
+    input:
+      bytes: [ 0x23, 0x00, 0x0a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub d0, d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x33, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub.h e0, e0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x10, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub.q d0, d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x33, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubm e0, e0, d0, #0"
+  -
+    input:
+      bytes: [ 0x23, 0x00, 0x6a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubm e0, e0, d0, d0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0x70, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubm.h e0, e0, d0, d0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x70, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubm.q e0, e0, d0, d0"
+  -
+    input:
+      bytes: [ 0x33, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubm.u e0, e0, d0, #0"
+  -
+    input:
+      bytes: [ 0x23, 0x00, 0x68, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubm.u e0, e0, d0, d0"
+  -
+    input:
+      bytes: [ 0x33, 0x00, 0xe0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubms e0, e0, d0, #0"
+  -
+    input:
+      bytes: [ 0x23, 0x00, 0xea, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubms e0, e0, d0, d0"
+  -
+    input:
+      bytes: [ 0x33, 0x00, 0xc0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubms.u e0, e0, d0, #0"
+  -
+    input:
+      bytes: [ 0x23, 0x00, 0xe8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubms.u e0, e0, d0, d0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x78, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubr.h d0, e0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x18, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubr.q d0, d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0xf8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubrs.h d0, e0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x98, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubrs.q d0, d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x23, 0x00, 0x8a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs d0, d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x33, 0x00, 0xa0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0xe0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs.h e0, e0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x90, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs.q d0, d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x33, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs.u d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x23, 0x00, 0x88, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs.u d0, d0, d0, d0"
+  -
+    input:
+      bytes: [ 0xcd, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "mtcr #0, d0"
+  -
+    input:
+      bytes: [ 0xe2, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul d0, d0"
+  -
+    input:
+      bytes: [ 0x53, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x73, 0x00, 0xa0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul d0, d0, d0"
+  -
+    input:
+      bytes: [ 0xb3, 0x00, 0x80, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.h e0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x93, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.q d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x53, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulm e0, d0, #0"
+  -
+    input:
+      bytes: [ 0x73, 0x00, 0xa0, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulm e0, d0, d0"
+  -
+    input:
+      bytes: [ 0x53, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulm.u e0, d0, #0"
+  -
+    input:
+      bytes: [ 0x73, 0x00, 0x80, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulm.u e0, d0, d0"
+  -
+    input:
+      bytes: [ 0xb3, 0x00, 0xc0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulr.h d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x93, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulr.q d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x53, 0x00, 0xa0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "muls d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x73, 0x00, 0xa0, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "muls d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x53, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "muls.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x73, 0x00, 0x80, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "muls.u d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0x90, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "nand d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8f, 0x00, 0x20, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "nand d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x07, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "nand.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x10, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "ne d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x20, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "ne d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0x10, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "ne.a d0, a0, a0"
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0x90, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "nez.a d0, a0"
+  -
+    input:
+      bytes: [ 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "nop"
+  -
+    input:
+      bytes: [ 0x0d, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "nop"
+  -
+    input:
+      bytes: [ 0x36, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "nor d0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0xb0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "nor d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8f, 0x00, 0x60, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "nor d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x87, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "nor.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x56, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "or d0, d0"
+  -
+    input:
+      bytes: [ 0xd6, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "or d15, #0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0xa0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "or d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8f, 0x00, 0x40, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "or d0, d0, #0"
+  -
+    input:
+      bytes: [ 0xc7, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.and.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0xc7, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.andn.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x70, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.eq d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0xe0, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.eq d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xb0, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.ge d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x60, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.ge d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xc0, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.ge.u d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x80, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.ge.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x90, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.lt d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x20, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.lt d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xa0, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.lt.u d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x40, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.lt.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x80, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.ne d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x00, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.ne d0, d0, #0"
+  -
+    input:
+      bytes: [ 0xc7, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.nor.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0xc7, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.or.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x87, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0xf0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "orn d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8f, 0x00, 0xe0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "orn d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x07, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "orn.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x6b, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "pack d0, e0, d0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "parity d0, d0"
+  -
+    input:
+      bytes: [ 0x00, 0x90 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "ret"
+  -
+    input:
+      bytes: [ 0x0d, 0x00, 0x40, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "ret"
+  -
+    input:
+      bytes: [ 0x00, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "rfe"
+  -
+    input:
+      bytes: [ 0x0d, 0x00, 0x80, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "rfe"
+  -
+    input:
+      bytes: [ 0x0d, 0x00, 0x40, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "rslcx"
+  -
+    input:
+      bytes: [ 0x2f, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "rstv"
+  -
+    input:
+      bytes: [ 0xd2, 0x50 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "rsub d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x00, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "rsub d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x40, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "rsubs d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x60, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "rsubs.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0xd2, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "sat.b d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xe0, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "sat.b d0, d0"
+  -
+    input:
+      bytes: [ 0xd2, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "sat.bu d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xf0, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "sat.bu d0, d0"
+  -
+    input:
+      bytes: [ 0xd2, 0x20 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "sat.h d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xe0, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "sat.h d0, d0"
+  -
+    input:
+      bytes: [ 0xd2, 0x30 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "sat.hu d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xf0, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "sat.hu d0, d0"
+  -
+    input:
+      bytes: [ 0x2b, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "sel d0, d0, d0, d0"
+  -
+    input:
+      bytes: [ 0xab, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "sel d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x21, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "sel.a a0, d0, a0, a0"
+  -
+    input:
+      bytes: [ 0xa1, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "sel.a a0, d0, a0, #0"
+  -
+    input:
+      bytes: [ 0x2b, 0x00, 0x50, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "seln d0, d0, d0, d0"
+  -
+    input:
+      bytes: [ 0xab, 0x00, 0xa0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "seln d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x21, 0x00, 0x50, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "seln.a a0, d0, a0, a0"
+  -
+    input:
+      bytes: [ 0xa1, 0x00, 0xa0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "seln.a a0, d0, a0, #0"
+  -
+    input:
+      bytes: [ 0x26, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh d0, #0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8f, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x27, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.and.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x27, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.andn.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0x00, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.b d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8f, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.b d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x70, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.eq d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0xe0, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.eq d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xb0, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.ge d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x60, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.ge d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xc0, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.ge.u d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x80, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.ge.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.h d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8f, 0x00, 0x00, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.h d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x90, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.lt d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x20, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.lt d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xa0, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.lt.u d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x40, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.lt.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0xa7, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.nand.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x80, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.ne d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x00, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.ne d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x27, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.nor.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x27, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.or.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0xa7, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.orn.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0xa7, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.xnor.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0xa7, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.xor.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0xa6, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha d0, #0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0x10, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8f, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0x10, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha.b d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8f, 0x00, 0x20, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha.b d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0x10, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha.h d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8f, 0x00, 0x20, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha.h d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "shas d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8f, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "shas d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x18, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.a [a0]#0, a15"
+  -
+    input:
+      bytes: [ 0x2c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.a [a15]#0, a0"
+  -
+    input:
+      bytes: [ 0x54, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.a [a0+], a0"
+  -
+    input:
+      bytes: [ 0x84, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.a [a0], a0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x80, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.a [a0+]#0, a0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x80, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.a [p0+r], a0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x80, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.a [+a0]#0, a0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x80, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.a [p0+c]#0, a0"
+  -
+    input:
+      bytes: [ 0xa5, 0x00, 0x00, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.a #0, a0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x80, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.a [a0]#0, a0"
+  -
+    input:
+      bytes: [ 0x78, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [a0], d0"
+  -
+    input:
+      bytes: [ 0x8c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [a15]#0, d0"
+  -
+    input:
+      bytes: [ 0xa8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [a0]#0, d15"
+  -
+    input:
+      bytes: [ 0xe4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [a0+], d0"
+  -
+    input:
+      bytes: [ 0x25, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b #0, d0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [a0+]#0, d0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [p0+r], d0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [+a0]#0, d0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [p0+c]#0, d0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x00, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [a0]#0, d0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x40, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.d [a0+]#0, e0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x40, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.d [p0+r], e0"
+  -
+    input:
+      bytes: [ 0xa5, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.d #0, e0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x40, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.d [+a0]#0, e0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x40, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.d [p0+c]#0, e0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x40, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.d [a0]#0, e0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0xc0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.da [a0+]#0, p0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0xc0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.da [p0+r], p0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0xc0, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.da [+a0]#0, p0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0xc0, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.da [p0+c]#0, p0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0xc0, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.da [a0]#0, p0"
+  -
+    input:
+      bytes: [ 0xa5, 0x00, 0x00, 0x0c ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.da #0, p0"
+  -
+    input:
+      bytes: [ 0x14, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [a0+], d0"
+  -
+    input:
+      bytes: [ 0x4c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [a15]#0, d0"
+  -
+    input:
+      bytes: [ 0x68, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [a0]#0, d15"
+  -
+    input:
+      bytes: [ 0xf8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [a0], d0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [a0+]#0, d0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [p0+r], d0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x80, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [+a0]#0, d0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x80, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [p0+c]#0, d0"
+  -
+    input:
+      bytes: [ 0x25, 0x00, 0x00, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h #0, d0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x80, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [a0]#0, d0"
+  -
+    input:
+      bytes: [ 0x65, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.q #0, d0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x00, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.q [a0+]#0, d0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x00, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.q [p0+r], d0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x00, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.q [+a0]#0, d0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x00, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.q [p0+c]#0, d0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x00, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.q [a0]#0, d0"
+  -
+    input:
+      bytes: [ 0xd5, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.t #0, #0, #0"
+  -
+    input:
+      bytes: [ 0x04, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w [a0], d0"
+  -
+    input:
+      bytes: [ 0x94, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w [a0+], d0"
+  -
+    input:
+      bytes: [ 0xcc, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w [a15]#0, d0"
+  -
+    input:
+      bytes: [ 0xe8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w [a0]#0, d15"
+  -
+    input:
+      bytes: [ 0x59, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w [a0]#0, d0"
+  -
+    input:
+      bytes: [ 0xa5, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w #0, d0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x00, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w [a0+]#0, d0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x00, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w [p0+r], d0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x00, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w [+a0]#0, d0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x00, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w [p0+c]#0, d0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x00, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w [a0]#0, d0"
+  -
+    input:
+      bytes: [ 0x15, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "stlcx #0"
+  -
+    input:
+      bytes: [ 0x49, 0x00, 0x80, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "stlcx [a0]#0"
+  -
+    input:
+      bytes: [ 0x15, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "stucx #0"
+  -
+    input:
+      bytes: [ 0x49, 0x00, 0xc0, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "stucx [a0]#0"
+  -
+    input:
+      bytes: [ 0x5a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub d15, d0, d0"
+  -
+    input:
+      bytes: [ 0xa2, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub.a sp, #0"
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub.a a0, a0, a0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x80, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub.b d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x80, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub.h d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xd0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "subc d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x62, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "subs d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xa0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "subs d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xa0, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "subs.b d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xb0, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "subs.bu d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xa0, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "subs.h d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xb0, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "subs.hu d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xb0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "subs.u d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0x10, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "subsc.a a0, a0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xc0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "subx d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0d, 0x00, 0x00, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "svlcx"
+  -
+    input:
+      bytes: [ 0x49, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "swap.a [a0+]#0, a0"
+  -
+    input:
+      bytes: [ 0x69, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "swap.a [p0+r], a0"
+  -
+    input:
+      bytes: [ 0x49, 0x00, 0x80, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "swap.a [+a0]#0, a0"
+  -
+    input:
+      bytes: [ 0x69, 0x00, 0x80, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "swap.a [p0+c]#0, a0"
+  -
+    input:
+      bytes: [ 0xe5, 0x00, 0x00, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "swap.a #0, a0"
+  -
+    input:
+      bytes: [ 0x49, 0x00, 0x80, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "swap.a [a0]#0, a0"
+  -
+    input:
+      bytes: [ 0x49, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "swap.w [a0+]#0, d0"
+  -
+    input:
+      bytes: [ 0x69, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "swap.w [p0+r], d0"
+  -
+    input:
+      bytes: [ 0xe5, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "swap.w #0, d0"
+  -
+    input:
+      bytes: [ 0x49, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "swap.w [+a0]#0, d0"
+  -
+    input:
+      bytes: [ 0x69, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "swap.w [p0+c]#0, d0"
+  -
+    input:
+      bytes: [ 0x49, 0x00, 0x00, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "swap.w [a0]#0, d0"
+  -
+    input:
+      bytes: [ 0xad, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "syscall #0"
+  -
+    input:
+      bytes: [ 0x0d, 0x00, 0x40, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "trapsv"
+  -
+    input:
+      bytes: [ 0x0d, 0x00, 0x00, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "trapv"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0x00, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "unpack e0, d0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0xd0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "xnor d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8f, 0x00, 0xa0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "xnor d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x07, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "xnor.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0xc0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8f, 0x00, 0x80, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xf0, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor.eq d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0xe0, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor.eq d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x30, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor.ge d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x60, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor.ge d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x40, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor.ge.u d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x80, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor.ge.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x10, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor.lt d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x20, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor.lt d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x20, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor.lt.u d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x40, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor.lt.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x00, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor.ne d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x00, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor.ne d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x07, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_110" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor.t d0, d0, #0, d0, #0"
diff --git a/tests/MC/TriCore/tc120.s.yaml b/tests/MC/TriCore/tc120.s.yaml
new file mode 100644
index 000000000..ef4f2b79d
--- /dev/null
+++ b/tests/MC/TriCore/tc120.s.yaml
@@ -0,0 +1,6832 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xc0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "abs d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xc0, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "abs.b d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xc0, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "abs.h d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xe0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "absdif d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0xc0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "absdif d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xe0, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "absdif.b d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xe0, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "absdif.h d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xf0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "absdifs d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0xe0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "absdifs d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xf0, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "absdifs.h d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xd0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "abss d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xd0, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "abss.h d0, d0"
+  -
+    input:
+      bytes: [ 0x12, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d0, d15, d0"
+  -
+    input:
+      bytes: [ 0x92, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d0, d15, #0"
+  -
+    input:
+      bytes: [ 0x1a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d15, d0, d0"
+  -
+    input:
+      bytes: [ 0x42, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d0, d0"
+  -
+    input:
+      bytes: [ 0x9a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d15, d0, #0"
+  -
+    input:
+      bytes: [ 0xc2, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x30, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "add.a a0, a0"
+  -
+    input:
+      bytes: [ 0xb0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "add.a a0, #0"
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0x10, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "add.a a0, a0, a0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "add.b d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x00, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "add.h d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x50, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "addc d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0xa0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "addc d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x1b, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "addi d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x9b, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "addih d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x11, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "addih.a a0, a0, #0"
+  -
+    input:
+      bytes: [ 0x22, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "adds d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "adds d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "adds d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x20, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "adds.h d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x30, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "adds.hu d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x30, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "adds.u d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "adds.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x10, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "addsc.a a0, a0, d15, #0"
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0x00, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "addsc.a a0, a0, d0, #0"
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0x20, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "addsc.at a0, a0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "addx d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "addx d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x26, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d0, d0"
+  -
+    input:
+      bytes: [ 0x16, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d15, #0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8f, 0x00, 0x00, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x47, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.and.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x47, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.andn.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x00, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.eq d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.eq d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x40, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.ge d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x80, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.ge d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x50, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.ge.u d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0xa0, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.ge.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x20, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.lt d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x40, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.lt d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x30, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.lt.u d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x60, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.lt.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x10, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.ne d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x20, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.ne d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x47, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.nor.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x47, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.or.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x87, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0xe0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "andn d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8f, 0x00, 0xc0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "andn d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x87, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "andn.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0xe0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "bisr #0"
+  -
+    input:
+      bytes: [ 0xad, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "bisr #0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0x10, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "bmerge d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0x90, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "bsplit e0, d0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x80, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachea.i [a0+]#0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x80, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachea.i [p0+r]"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x80, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachea.i [+a0]#0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x80, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachea.i [p0+c]#0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x80, 0x0b ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachea.i [a0]#0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x00, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachea.w [a0+]#0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x00, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachea.w [p0+r]"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x00, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachea.w [+a0]#0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x00, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachea.w [p0+c]#0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x00, 0x0b ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachea.w [a0]#0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x40, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachea.wi [a0+]#0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x40, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachea.wi [p0+r]"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x40, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachea.wi [+a0]#0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x40, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachea.wi [p0+c]#0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x40, 0x0b ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachea.wi [a0]#0"
+  -
+    input:
+      bytes: [ 0x8a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "cadd d0, d15, #0"
+  -
+    input:
+      bytes: [ 0x2b, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "cadd d0, d0, d0, d0"
+  -
+    input:
+      bytes: [ 0xab, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "cadd d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0xca, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "caddn d0, d15, #0"
+  -
+    input:
+      bytes: [ 0x2b, 0x00, 0x10, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "caddn d0, d0, d0, d0"
+  -
+    input:
+      bytes: [ 0xab, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "caddn d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x5c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0"
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "calla #0"
+  -
+    input:
+      bytes: [ 0x2d, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "calli a0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0xc0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "clo d0, d0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0xd0, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "clo.h d0, d0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0xd0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "cls d0, d0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0xe0, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "cls.h d0, d0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0xb0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "clz d0, d0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0xc0, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "clz.h d0, d0"
+  -
+    input:
+      bytes: [ 0x2a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmov d0, d15, d0"
+  -
+    input:
+      bytes: [ 0xaa, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmov d0, d15, #0"
+  -
+    input:
+      bytes: [ 0x6a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmovn d0, d15, d0"
+  -
+    input:
+      bytes: [ 0xea, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmovn d0, d15, #0"
+  -
+    input:
+      bytes: [ 0x2b, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "csub d0, d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x2b, 0x00, 0x30, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "csubn d0, d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x00, 0xa0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "debug"
+  -
+    input:
+      bytes: [ 0x0d, 0x00, 0x00, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "debug"
+  -
+    input:
+      bytes: [ 0x77, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "dextr d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x17, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "dextr d0, d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0d, 0x00, 0x40, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "disable"
+  -
+    input:
+      bytes: [ 0x0d, 0x00, 0x80, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "dsync"
+  -
+    input:
+      bytes: [ 0x6b, 0x00, 0xd0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "dvadj e0, e0, d0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0xa0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "dvinit e0, d0, d0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0xa0, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "dvinit.b e0, d0, d0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0xa0, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "dvinit.bu e0, d0, d0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0xa0, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "dvinit.h e0, d0, d0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0xa0, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "dvinit.hu e0, d0, d0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0xa0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "dvinit.u e0, d0, d0"
+  -
+    input:
+      bytes: [ 0x6b, 0x00, 0xf0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "dvstep e0, e0, d0"
+  -
+    input:
+      bytes: [ 0x6b, 0x00, 0xe0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "dvstep.u e0, e0, d0"
+  -
+    input:
+      bytes: [ 0x0d, 0x00, 0x00, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "enable"
+  -
+    input:
+      bytes: [ 0x3a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "eq d15, d0, d0"
+  -
+    input:
+      bytes: [ 0xba, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "eq d15, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x00, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "eq d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x00, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "eq d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "eq.a d0, a0, a0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x00, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "eq.b d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x00, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "eq.h d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x00, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "eq.w d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x60, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "eqany.b d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0xc0, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "eqany.b d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x60, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "eqany.h d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0xc0, 0x0e ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "eqany.h d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0x80, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "eqz.a d0, a0"
+  -
+    input:
+      bytes: [ 0x17, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr d0, d0, e0"
+  -
+    input:
+      bytes: [ 0x37, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr d0, d0, #0, #0"
+  -
+    input:
+      bytes: [ 0x57, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x17, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d0, d0, e0"
+  -
+    input:
+      bytes: [ 0x37, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d0, d0, #0, #0"
+  -
+    input:
+      bytes: [ 0x57, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x40, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "ge d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x80, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "ge d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0x30, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "ge.a d0, a0, a0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x50, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "ge.u d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0xa0, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "ge.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x37, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "imask e0, d0, #0, #0"
+  -
+    input:
+      bytes: [ 0x57, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "imask e0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0xb7, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "imask e0, #0, #0, #0"
+  -
+    input:
+      bytes: [ 0xd7, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "imask e0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x67, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "ins.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x17, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d0, d0, d0, e0"
+  -
+    input:
+      bytes: [ 0x37, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d0, d0, d0, #0, #0"
+  -
+    input:
+      bytes: [ 0x57, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d0, d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x97, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d0, d0, #0, e0"
+  -
+    input:
+      bytes: [ 0xb7, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d0, d0, #0, #0, #0"
+  -
+    input:
+      bytes: [ 0xd7, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x67, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "insn.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0d, 0x00, 0xc0, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "isync"
+  -
+    input:
+      bytes: [ 0x3c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0"
+  -
+    input:
+      bytes: [ 0x1d, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0"
+  -
+    input:
+      bytes: [ 0x9d, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "ja #0"
+  -
+    input:
+      bytes: [ 0x1e, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, #0, #0"
+  -
+    input:
+      bytes: [ 0x5f, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d0, d0, #0"
+  -
+    input:
+      bytes: [ 0xdf, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d0, #0, #0"
+  -
+    input:
+      bytes: [ 0x7d, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq.a a0, a0, #0"
+  -
+    input:
+      bytes: [ 0x7f, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "jge d0, d0, #0"
+  -
+    input:
+      bytes: [ 0xff, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "jge d0, #0, #0"
+  -
+    input:
+      bytes: [ 0x7f, 0x00, 0x00, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "jge.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0xff, 0x00, 0x00, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "jge.u d0, #0, #0"
+  -
+    input:
+      bytes: [ 0xce, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "jgez d0, #0"
+  -
+    input:
+      bytes: [ 0x4e, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "jgtz d0, #0"
+  -
+    input:
+      bytes: [ 0xdc, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "ji a0"
+  -
+    input:
+      bytes: [ 0x2d, 0x00, 0x30, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "ji a0"
+  -
+    input:
+      bytes: [ 0x5d, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "jl #0"
+  -
+    input:
+      bytes: [ 0xdd, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "jla #0"
+  -
+    input:
+      bytes: [ 0x8e, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlez d0, #0"
+  -
+    input:
+      bytes: [ 0x2d, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "jli a0"
+  -
+    input:
+      bytes: [ 0x3f, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt d0, d0, #0"
+  -
+    input:
+      bytes: [ 0xbf, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt d0, #0, #0"
+  -
+    input:
+      bytes: [ 0x3f, 0x00, 0x00, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0xbf, 0x00, 0x00, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt.u d0, #0, #0"
+  -
+    input:
+      bytes: [ 0x0e, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "jltz d0, #0"
+  -
+    input:
+      bytes: [ 0x7e, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, d0, #0"
+  -
+    input:
+      bytes: [ 0x5e, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, #0, #0"
+  -
+    input:
+      bytes: [ 0x5f, 0x00, 0x00, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d0, d0, #0"
+  -
+    input:
+      bytes: [ 0xdf, 0x00, 0x00, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d0, #0, #0"
+  -
+    input:
+      bytes: [ 0x7d, 0x00, 0x00, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne.a a0, a0, #0"
+  -
+    input:
+      bytes: [ 0x1f, 0x00, 0x00, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "jned d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x9f, 0x00, 0x00, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "jned d0, #0, #0"
+  -
+    input:
+      bytes: [ 0x1f, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnei d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x9f, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnei d0, #0, #0"
+  -
+    input:
+      bytes: [ 0xee, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz d15, #0"
+  -
+    input:
+      bytes: [ 0xf6, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz d0, #0"
+  -
+    input:
+      bytes: [ 0x7c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz.a a0, #0"
+  -
+    input:
+      bytes: [ 0xbd, 0x00, 0x00, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz.a a0, #0"
+  -
+    input:
+      bytes: [ 0xae, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz.t d15, #0, #0"
+  -
+    input:
+      bytes: [ 0x6f, 0x00, 0x00, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz.t d0, #0, #0"
+  -
+    input:
+      bytes: [ 0x6e, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d15, #0"
+  -
+    input:
+      bytes: [ 0x76, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d0, #0"
+  -
+    input:
+      bytes: [ 0xbc, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.a a0, #0"
+  -
+    input:
+      bytes: [ 0xbd, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.a a0, #0"
+  -
+    input:
+      bytes: [ 0x2e, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.t d15, #0, #0"
+  -
+    input:
+      bytes: [ 0x6f, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.t d0, #0, #0"
+  -
+    input:
+      bytes: [ 0xd8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.a a15, [sp]#0"
+  -
+    input:
+      bytes: [ 0xc8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.a a0, [a15]#0"
+  -
+    input:
+      bytes: [ 0xcc, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.a a15, [a0]#0"
+  -
+    input:
+      bytes: [ 0xc4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.a a0, [a0+]"
+  -
+    input:
+      bytes: [ 0xd4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.a a0, [a0]"
+  -
+    input:
+      bytes: [ 0x99, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.a a0, [a0]#0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x80, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.a a0, [a0+]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0x80, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.a a0, [p0+r]"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x80, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.a a0, [+a0]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0x80, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.a a0, [p0+c]#0"
+  -
+    input:
+      bytes: [ 0x85, 0x00, 0x00, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.a a0, #0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x80, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.a a0, [a0]#0"
+  -
+    input:
+      bytes: [ 0x05, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.b d0, #0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.b d0, [a0+]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.b d0, [p0+r]"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.b d0, [+a0]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.b d0, [p0+c]#0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x00, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.b d0, [a0]#0"
+  -
+    input:
+      bytes: [ 0x14, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d0, [a0]"
+  -
+    input:
+      bytes: [ 0x0c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d15, [a0]#0"
+  -
+    input:
+      bytes: [ 0x08, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d0, [a15]#0"
+  -
+    input:
+      bytes: [ 0x04, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d0, [a0+]"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d0, [a0+]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d0, [p0+r]"
+  -
+    input:
+      bytes: [ 0x05, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d0, #0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x40, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d0, [+a0]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0x40, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d0, [p0+c]#0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x40, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d0, [a0]#0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x40, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.d e0, [a0+]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0x40, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.d e0, [p0+r]"
+  -
+    input:
+      bytes: [ 0x85, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.d e0, #0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x40, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.d e0, [+a0]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0x40, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.d e0, [p0+c]#0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x40, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.d e0, [a0]#0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0xc0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.da p0, [a0+]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0xc0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.da p0, [p0+r]"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0xc0, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.da p0, [+a0]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0xc0, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.da p0, [p0+c]#0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0xc0, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.da p0, [a0]#0"
+  -
+    input:
+      bytes: [ 0x85, 0x00, 0x00, 0x0c ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.da p0, #0"
+  -
+    input:
+      bytes: [ 0x84, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.h d0, [a0+]"
+  -
+    input:
+      bytes: [ 0x8c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.h d15, [a0]#0"
+  -
+    input:
+      bytes: [ 0x88, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.h d0, [a15]#0"
+  -
+    input:
+      bytes: [ 0x94, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.h d0, [a0]"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.h d0, [a0+]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.h d0, [p0+r]"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x80, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.h d0, [+a0]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0x80, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.h d0, [p0+c]#0"
+  -
+    input:
+      bytes: [ 0x05, 0x00, 0x00, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.h d0, #0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x80, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.h d0, [a0]#0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0xc0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.hu d0, [a0+]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0xc0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.hu d0, [p0+r]"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0xc0, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.hu d0, [+a0]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0xc0, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.hu d0, [p0+c]#0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0xc0, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.hu d0, [a0]#0"
+  -
+    input:
+      bytes: [ 0x05, 0x00, 0x00, 0x0c ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.hu d0, #0"
+  -
+    input:
+      bytes: [ 0x45, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.q d0, #0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x00, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.q d0, [a0+]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0x00, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.q d0, [p0+r]"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x00, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.q d0, [+a0]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0x00, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.q d0, [p0+c]#0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x00, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.q d0, [a0]#0"
+  -
+    input:
+      bytes: [ 0x58, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d15, [sp]#0"
+  -
+    input:
+      bytes: [ 0x54, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d0, [a0]"
+  -
+    input:
+      bytes: [ 0x44, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d0, [a0+]"
+  -
+    input:
+      bytes: [ 0x4c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d15, [a0]#0"
+  -
+    input:
+      bytes: [ 0x48, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d0, [a15]#0"
+  -
+    input:
+      bytes: [ 0x19, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d0, [a0]#0"
+  -
+    input:
+      bytes: [ 0x85, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d0, #0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x00, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d0, [a0+]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0x00, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d0, [p0+r]"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x00, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d0, [+a0]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0x00, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d0, [p0+c]#0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x00, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d0, [a0]#0"
+  -
+    input:
+      bytes: [ 0x15, 0x00, 0x00, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldlcx #0"
+  -
+    input:
+      bytes: [ 0x49, 0x00, 0x00, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldlcx [a0]#0"
+  -
+    input:
+      bytes: [ 0x49, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldmst [a0+]#0, e0"
+  -
+    input:
+      bytes: [ 0x69, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldmst [p0+r], e0"
+  -
+    input:
+      bytes: [ 0xe5, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldmst #0, e0"
+  -
+    input:
+      bytes: [ 0x49, 0x00, 0x40, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldmst [+a0]#0, e0"
+  -
+    input:
+      bytes: [ 0x69, 0x00, 0x40, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldmst [p0+c]#0, e0"
+  -
+    input:
+      bytes: [ 0x49, 0x00, 0x40, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldmst [a0]#0, e0"
+  -
+    input:
+      bytes: [ 0x49, 0x00, 0x40, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "lducx [a0]#0"
+  -
+    input:
+      bytes: [ 0x15, 0x00, 0x00, 0x0c ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "lducx #0"
+  -
+    input:
+      bytes: [ 0xc5, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a0, #0"
+  -
+    input:
+      bytes: [ 0xd9, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a0, [a0]#0"
+  -
+    input:
+      bytes: [ 0x49, 0x00, 0x00, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a0, [a0]#0"
+  -
+    input:
+      bytes: [ 0xfc, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "loop a0, #0xffffffe0"
+  -
+    input:
+      bytes: [ 0xfd, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "loop a0, #0"
+  -
+    input:
+      bytes: [ 0xfd, 0x00, 0x00, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "loopu #0"
+  -
+    input:
+      bytes: [ 0x7a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "lt d15, d0, d0"
+  -
+    input:
+      bytes: [ 0xfa, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "lt d15, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x20, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "lt d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x40, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "lt d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0x20, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "lt.a d0, a0, a0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x20, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "lt.b d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x30, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "lt.bu d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x20, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "lt.h d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x30, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "lt.hu d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x30, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "lt.u d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x60, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "lt.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x20, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "lt.w d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x30, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "lt.wu d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x03, 0x00, 0x0a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd d0, d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x13, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x13, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd e0, e0, d0, #0"
+  -
+    input:
+      bytes: [ 0x03, 0x00, 0x6a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd e0, e0, d0, d0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd.h e0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0x64, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd.h e0, e0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0x68, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd.h e0, e0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0x6c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd.h e0, e0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x10, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd.q d0, d0, d0u, d0u, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd.q d0, d0, d0, d0u, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x04, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd.q d0, d0, d0, d0l, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x08, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd.q d0, d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x14, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd.q d0, d0, d0l, d0l, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd.q e0, e0, d0, d0u, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x64, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd.q e0, e0, d0, d0l, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x6c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd.q e0, e0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x70, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd.q e0, e0, d0u, d0u, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x74, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd.q e0, e0, d0l, d0l, #0"
+  -
+    input:
+      bytes: [ 0x13, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd.u e0, e0, d0, #0"
+  -
+    input:
+      bytes: [ 0x03, 0x00, 0x68, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd.u e0, e0, d0, d0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0x70, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddm.h e0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0x74, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddm.h e0, e0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0x78, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddm.h e0, e0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0x7c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddm.h e0, e0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0xf0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddms.h e0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0xf4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddms.h e0, e0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0xf8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddms.h e0, e0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0xfc, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddms.h e0, e0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x78, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddr.h d0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0x30, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddr.h d0, d0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0x34, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddr.h d0, d0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0x38, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddr.h d0, d0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0x3c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddr.h d0, d0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x18, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddr.q d0, d0, d0u, d0u, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x1c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddr.q d0, d0, d0l, d0l, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0xf8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddrs.h d0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0xb0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddrs.h d0, d0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0xb4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddrs.h d0, d0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0xb8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddrs.h d0, d0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0xbc, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddrs.h d0, d0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x98, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddrs.q d0, d0, d0u, d0u, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x9c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddrs.q d0, d0, d0l, d0l, #0"
+  -
+    input:
+      bytes: [ 0x03, 0x00, 0x8a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds d0, d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x13, 0x00, 0xa0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x13, 0x00, 0xe0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds e0, e0, d0, #0"
+  -
+    input:
+      bytes: [ 0x03, 0x00, 0xea, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds e0, e0, d0, d0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0xe0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds.h e0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0xe4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds.h e0, e0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0xe8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds.h e0, e0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0xec, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds.h e0, e0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x90, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds.q d0, d0, d0u, d0u, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds.q d0, d0, d0, d0u, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x84, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds.q d0, d0, d0, d0l, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x88, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds.q d0, d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x94, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds.q d0, d0, d0l, d0l, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0xe0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds.q e0, e0, d0, d0u, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0xe4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds.q e0, e0, d0, d0l, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0xec, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds.q e0, e0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0xf0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds.q e0, e0, d0u, d0u, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0xf4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds.q e0, e0, d0l, d0l, #0"
+  -
+    input:
+      bytes: [ 0x13, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds.u d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x03, 0x00, 0x88, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds.u d0, d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x13, 0x00, 0xc0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds.u e0, e0, d0, #0"
+  -
+    input:
+      bytes: [ 0x03, 0x00, 0xe8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds.u e0, e0, d0, d0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsu.h e0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0x64, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsu.h e0, e0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0x68, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsu.h e0, e0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0x6c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsu.h e0, e0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0x70, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsum.h e0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0x74, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsum.h e0, e0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0x78, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsum.h e0, e0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0x7c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsum.h e0, e0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0xf0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsums.h e0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0xf4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsums.h e0, e0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0xf8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsums.h e0, e0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0xfc, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsums.h e0, e0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0x30, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsur.h d0, d0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0x34, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsur.h d0, d0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0x38, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsur.h d0, d0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0x3c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsur.h d0, d0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0xb0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsurs.h d0, d0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0xb4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsurs.h d0, d0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0xb8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsurs.h d0, d0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0xbc, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsurs.h d0, d0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0xe0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsus.h e0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0xe4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsus.h e0, e0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0xe8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsus.h e0, e0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0xec, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsus.h e0, e0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xa0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "max d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x40, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "max d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xa0, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "max.b d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xb0, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "max.bu d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xa0, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "max.h d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xb0, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "max.hu d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xb0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "max.u d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x60, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "max.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x4d, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "mfcr d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x80, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "min d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x00, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "min d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x80, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "min.b d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x90, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "min.bu d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x80, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "min.h d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x90, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "min.hu d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x90, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "min.u d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x20, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "min.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x02, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d0, d0"
+  -
+    input:
+      bytes: [ 0x82, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d0, #0"
+  -
+    input:
+      bytes: [ 0xda, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d15, #0"
+  -
+    input:
+      bytes: [ 0x3b, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xf0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d0, d0"
+  -
+    input:
+      bytes: [ 0xa0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.a a0, #0"
+  -
+    input:
+      bytes: [ 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.a a0, d0"
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0x30, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.a a0, d0"
+  -
+    input:
+      bytes: [ 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.aa a0, a0"
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.aa a0, a0"
+  -
+    input:
+      bytes: [ 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.d d0, a0"
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0xc0, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.d d0, a0"
+  -
+    input:
+      bytes: [ 0xbb, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.u d0, #0"
+  -
+    input:
+      bytes: [ 0x7b, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh d0, #0"
+  -
+    input:
+      bytes: [ 0x91, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a0, #0"
+  -
+    input:
+      bytes: [ 0x23, 0x00, 0x0a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub d0, d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x33, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x33, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub e0, e0, d0, #0"
+  -
+    input:
+      bytes: [ 0x23, 0x00, 0x6a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub e0, e0, d0, d0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub.h e0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0x64, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub.h e0, e0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0x68, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub.h e0, e0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0x6c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub.h e0, e0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x10, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub.q d0, d0, d0u, d0u, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub.q d0, d0, d0, d0u, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x04, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub.q d0, d0, d0, d0l, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x08, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub.q d0, d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x14, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub.q d0, d0, d0l, d0l, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub.q e0, e0, d0, d0u, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x64, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub.q e0, e0, d0, d0l, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x6c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub.q e0, e0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x70, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub.q e0, e0, d0u, d0u, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x74, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub.q e0, e0, d0l, d0l, #0"
+  -
+    input:
+      bytes: [ 0x33, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub.u e0, e0, d0, #0"
+  -
+    input:
+      bytes: [ 0x23, 0x00, 0x68, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub.u e0, e0, d0, d0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubad.h e0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x64, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubad.h e0, e0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x68, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubad.h e0, e0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x6c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubad.h e0, e0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x70, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubadm.h e0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x74, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubadm.h e0, e0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x78, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubadm.h e0, e0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x7c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubadm.h e0, e0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xf0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubadms.h e0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xf4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubadms.h e0, e0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xf8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubadms.h e0, e0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xfc, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubadms.h e0, e0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x30, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubadr.h d0, d0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x34, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubadr.h d0, d0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x38, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubadr.h d0, d0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x3c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubadr.h d0, d0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xb0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubadrs.h d0, d0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xb4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubadrs.h d0, d0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xb8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubadrs.h d0, d0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xbc, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubadrs.h d0, d0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xe0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubads.h e0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xe4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubads.h e0, e0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xe8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubads.h e0, e0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xec, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubads.h e0, e0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0x70, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubm.h e0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0x74, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubm.h e0, e0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0x78, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubm.h e0, e0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0x7c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubm.h e0, e0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0xf0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubms.h e0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0xf4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubms.h e0, e0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0xf8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubms.h e0, e0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0xfc, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubms.h e0, e0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x78, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubr.h d0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0x30, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubr.h d0, d0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0x34, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubr.h d0, d0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0x38, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubr.h d0, d0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0x3c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubr.h d0, d0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x18, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubr.q d0, d0, d0u, d0u, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x1c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubr.q d0, d0, d0l, d0l, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0xf8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubrs.h d0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0xb0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubrs.h d0, d0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0xb4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubrs.h d0, d0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0xb8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubrs.h d0, d0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0xbc, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubrs.h d0, d0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x98, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubrs.q d0, d0, d0u, d0u, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x9c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubrs.q d0, d0, d0l, d0l, #0"
+  -
+    input:
+      bytes: [ 0x23, 0x00, 0x8a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs d0, d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x33, 0x00, 0xa0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x33, 0x00, 0xe0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs e0, e0, d0, #0"
+  -
+    input:
+      bytes: [ 0x23, 0x00, 0xea, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs e0, e0, d0, d0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0xe0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs.h e0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0xe4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs.h e0, e0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0xe8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs.h e0, e0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0xec, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs.h e0, e0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x90, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs.q d0, d0, d0u, d0u, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs.q d0, d0, d0, d0u, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x84, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs.q d0, d0, d0, d0l, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x88, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs.q d0, d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x94, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs.q d0, d0, d0l, d0l, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0xe0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs.q e0, e0, d0, d0u, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0xe4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs.q e0, e0, d0, d0l, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0xec, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs.q e0, e0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0xf0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs.q e0, e0, d0u, d0u, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0xf4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs.q e0, e0, d0l, d0l, #0"
+  -
+    input:
+      bytes: [ 0x33, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs.u d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x23, 0x00, 0x88, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs.u d0, d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x33, 0x00, 0xc0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs.u e0, e0, d0, #0"
+  -
+    input:
+      bytes: [ 0x23, 0x00, 0xe8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs.u e0, e0, d0, d0"
+  -
+    input:
+      bytes: [ 0xcd, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "mtcr #0, d0"
+  -
+    input:
+      bytes: [ 0xe2, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul d0, d0"
+  -
+    input:
+      bytes: [ 0x53, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x73, 0x00, 0x0a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x53, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul e0, d0, #0"
+  -
+    input:
+      bytes: [ 0x73, 0x00, 0x6a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul e0, d0, d0"
+  -
+    input:
+      bytes: [ 0xb3, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.h e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xb3, 0x00, 0x64, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.h e0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xb3, 0x00, 0x68, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.h e0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xb3, 0x00, 0x6c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.h e0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0x93, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.q d0, d0, d0u, #0"
+  -
+    input:
+      bytes: [ 0x93, 0x00, 0x04, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.q d0, d0, d0l, #0"
+  -
+    input:
+      bytes: [ 0x93, 0x00, 0x08, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.q d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x93, 0x00, 0x10, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.q d0, d0u, d0u, #0"
+  -
+    input:
+      bytes: [ 0x93, 0x00, 0x14, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.q d0, d0l, d0l, #0"
+  -
+    input:
+      bytes: [ 0x93, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.q e0, d0, d0u, #0"
+  -
+    input:
+      bytes: [ 0x93, 0x00, 0x64, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.q e0, d0, d0l, #0"
+  -
+    input:
+      bytes: [ 0x93, 0x00, 0x6c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.q e0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x53, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.u e0, d0, #0"
+  -
+    input:
+      bytes: [ 0x73, 0x00, 0x68, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.u e0, d0, d0"
+  -
+    input:
+      bytes: [ 0xb3, 0x00, 0x70, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulm.h e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xb3, 0x00, 0x74, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulm.h e0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xb3, 0x00, 0x78, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulm.h e0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xb3, 0x00, 0x7c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulm.h e0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0xb3, 0x00, 0xf0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulms.h e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xb3, 0x00, 0xf4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulms.h e0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xb3, 0x00, 0xf8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulms.h e0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xb3, 0x00, 0xfc, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulms.h e0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0xb3, 0x00, 0x30, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulr.h d0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xb3, 0x00, 0x34, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulr.h d0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xb3, 0x00, 0x38, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulr.h d0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xb3, 0x00, 0x3c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulr.h d0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0x93, 0x00, 0x18, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulr.q d0, d0u, d0u, #0"
+  -
+    input:
+      bytes: [ 0x93, 0x00, 0x1c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulr.q d0, d0l, d0l, #0"
+  -
+    input:
+      bytes: [ 0x53, 0x00, 0xa0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "muls d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x73, 0x00, 0x8a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "muls d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x53, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "muls.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x73, 0x00, 0x88, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "muls.u d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0x90, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "nand d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8f, 0x00, 0x20, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "nand d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x07, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "nand.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x10, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "ne d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x20, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "ne d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0x10, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "ne.a d0, a0, a0"
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0x90, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "nez.a d0, a0"
+  -
+    input:
+      bytes: [ 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "nop"
+  -
+    input:
+      bytes: [ 0x0d, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "nop"
+  -
+    input:
+      bytes: [ 0x46, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "nor d0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0xb0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "nor d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8f, 0x00, 0x60, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "nor d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x87, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "nor.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0xa6, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "or d0, d0"
+  -
+    input:
+      bytes: [ 0x96, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "or d15, #0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0xa0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "or d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8f, 0x00, 0x40, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "or d0, d0, #0"
+  -
+    input:
+      bytes: [ 0xc7, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.and.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0xc7, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.andn.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x70, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.eq d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0xe0, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.eq d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xb0, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.ge d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x60, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.ge d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xc0, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.ge.u d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x80, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.ge.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x90, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.lt d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x20, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.lt d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xa0, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.lt.u d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x40, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.lt.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x80, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.ne d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x00, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.ne d0, d0, #0"
+  -
+    input:
+      bytes: [ 0xc7, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.nor.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0xc7, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.or.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x87, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0xf0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "orn d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8f, 0x00, 0xe0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "orn d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x07, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "orn.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x6b, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "pack d0, e0, d0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "parity d0, d0"
+  -
+    input:
+      bytes: [ 0x00, 0x90 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "ret"
+  -
+    input:
+      bytes: [ 0x0d, 0x00, 0x80, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "ret"
+  -
+    input:
+      bytes: [ 0x00, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "rfe"
+  -
+    input:
+      bytes: [ 0x0d, 0x00, 0xc0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "rfe"
+  -
+    input:
+      bytes: [ 0x0d, 0x00, 0x40, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "rfm"
+  -
+    input:
+      bytes: [ 0x0d, 0x00, 0x40, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "rslcx"
+  -
+    input:
+      bytes: [ 0x2f, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "rstv"
+  -
+    input:
+      bytes: [ 0x32, 0x50 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "rsub d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x00, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "rsub d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x40, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "rsubs d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x60, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "rsubs.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x32, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "sat.b d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xe0, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "sat.b d0, d0"
+  -
+    input:
+      bytes: [ 0x32, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "sat.bu d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xf0, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "sat.bu d0, d0"
+  -
+    input:
+      bytes: [ 0x32, 0x20 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "sat.h d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xe0, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "sat.h d0, d0"
+  -
+    input:
+      bytes: [ 0x32, 0x30 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "sat.hu d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xf0, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "sat.hu d0, d0"
+  -
+    input:
+      bytes: [ 0x2b, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "sel d0, d0, d0, d0"
+  -
+    input:
+      bytes: [ 0xab, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "sel d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x2b, 0x00, 0x50, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "seln d0, d0, d0, d0"
+  -
+    input:
+      bytes: [ 0xab, 0x00, 0xa0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "seln d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x06, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh d0, #0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8f, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x27, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.and.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x27, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.andn.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x70, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.eq d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0xe0, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.eq d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xb0, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.ge d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x60, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.ge d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xc0, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.ge.u d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x80, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.ge.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.h d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8f, 0x00, 0x00, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.h d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x90, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.lt d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x20, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.lt d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xa0, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.lt.u d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x40, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.lt.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0xa7, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.nand.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x80, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.ne d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x00, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.ne d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x27, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.nor.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x27, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.or.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0xa7, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.orn.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0xa7, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.xnor.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0xa7, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.xor.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x86, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha d0, #0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0x10, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8f, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0x10, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha.h d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8f, 0x00, 0x20, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha.h d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "shas d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8f, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "shas d0, d0, #0"
+  -
+    input:
+      bytes: [ 0xf8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.a [sp]#0, a15"
+  -
+    input:
+      bytes: [ 0xec, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.a [a0]#0, a15"
+  -
+    input:
+      bytes: [ 0xe8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.a [a15]#0, a0"
+  -
+    input:
+      bytes: [ 0xe4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.a [a0+], a0"
+  -
+    input:
+      bytes: [ 0xf4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.a [a0], a0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x80, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.a [a0+]#0, a0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x80, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.a [p0+r], a0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x80, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.a [+a0]#0, a0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x80, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.a [p0+c]#0, a0"
+  -
+    input:
+      bytes: [ 0xa5, 0x00, 0x00, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.a #0, a0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x80, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.a [a0]#0, a0"
+  -
+    input:
+      bytes: [ 0x34, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [a0], d0"
+  -
+    input:
+      bytes: [ 0x28, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [a15]#0, d0"
+  -
+    input:
+      bytes: [ 0x2c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [a0]#0, d15"
+  -
+    input:
+      bytes: [ 0x24, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [a0+], d0"
+  -
+    input:
+      bytes: [ 0x25, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b #0, d0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [a0+]#0, d0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [p0+r], d0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [+a0]#0, d0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [p0+c]#0, d0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x00, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [a0]#0, d0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x40, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.d [a0+]#0, e0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x40, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.d [p0+r], e0"
+  -
+    input:
+      bytes: [ 0xa5, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.d #0, e0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x40, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.d [+a0]#0, e0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x40, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.d [p0+c]#0, e0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x40, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.d [a0]#0, e0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0xc0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.da [a0+]#0, p0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0xc0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.da [p0+r], p0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0xc0, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.da [+a0]#0, p0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0xc0, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.da [p0+c]#0, p0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0xc0, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.da [a0]#0, p0"
+  -
+    input:
+      bytes: [ 0xa5, 0x00, 0x00, 0x0c ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.da #0, p0"
+  -
+    input:
+      bytes: [ 0xa4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [a0+], d0"
+  -
+    input:
+      bytes: [ 0xa8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [a15]#0, d0"
+  -
+    input:
+      bytes: [ 0xac, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [a0]#0, d15"
+  -
+    input:
+      bytes: [ 0xb4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [a0], d0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [a0+]#0, d0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [p0+r], d0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x80, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [+a0]#0, d0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x80, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [p0+c]#0, d0"
+  -
+    input:
+      bytes: [ 0x25, 0x00, 0x00, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h #0, d0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x80, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [a0]#0, d0"
+  -
+    input:
+      bytes: [ 0x65, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.q #0, d0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x00, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.q [a0+]#0, d0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x00, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.q [p0+r], d0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x00, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.q [+a0]#0, d0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x00, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.q [p0+c]#0, d0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x00, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.q [a0]#0, d0"
+  -
+    input:
+      bytes: [ 0xd5, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.t #0, #0, #0"
+  -
+    input:
+      bytes: [ 0x78, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w [sp]#0, d15"
+  -
+    input:
+      bytes: [ 0x74, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w [a0], d0"
+  -
+    input:
+      bytes: [ 0x64, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w [a0+], d0"
+  -
+    input:
+      bytes: [ 0x68, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w [a15]#0, d0"
+  -
+    input:
+      bytes: [ 0x6c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w [a0]#0, d15"
+  -
+    input:
+      bytes: [ 0x59, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w [a0]#0, d0"
+  -
+    input:
+      bytes: [ 0xa5, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w #0, d0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x00, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w [a0+]#0, d0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x00, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w [p0+r], d0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x00, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w [+a0]#0, d0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x00, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w [p0+c]#0, d0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x00, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w [a0]#0, d0"
+  -
+    input:
+      bytes: [ 0x15, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "stlcx #0"
+  -
+    input:
+      bytes: [ 0x49, 0x00, 0x80, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "stlcx [a0]#0"
+  -
+    input:
+      bytes: [ 0x15, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "stucx #0"
+  -
+    input:
+      bytes: [ 0x49, 0x00, 0xc0, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "stucx [a0]#0"
+  -
+    input:
+      bytes: [ 0x52, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub d0, d15, d0"
+  -
+    input:
+      bytes: [ 0x5a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub d15, d0, d0"
+  -
+    input:
+      bytes: [ 0xa2, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub.a sp, #0"
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub.a a0, a0, a0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x80, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub.b d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x80, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub.h d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xd0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "subc d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x62, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "subs d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xa0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "subs d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xa0, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "subs.h d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xb0, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "subs.hu d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xb0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "subs.u d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xc0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "subx d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0d, 0x00, 0x00, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "svlcx"
+  -
+    input:
+      bytes: [ 0x49, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "swap.w [a0+]#0, d0"
+  -
+    input:
+      bytes: [ 0x69, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "swap.w [p0+r], d0"
+  -
+    input:
+      bytes: [ 0xe5, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "swap.w #0, d0"
+  -
+    input:
+      bytes: [ 0x49, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "swap.w [+a0]#0, d0"
+  -
+    input:
+      bytes: [ 0x69, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "swap.w [p0+c]#0, d0"
+  -
+    input:
+      bytes: [ 0x49, 0x00, 0x00, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "swap.w [a0]#0, d0"
+  -
+    input:
+      bytes: [ 0xad, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "syscall #0"
+  -
+    input:
+      bytes: [ 0x0d, 0x00, 0x40, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "trapsv"
+  -
+    input:
+      bytes: [ 0x0d, 0x00, 0x00, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "trapv"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "unpack e0, d0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0xd0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "xnor d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8f, 0x00, 0xa0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "xnor d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x07, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "xnor.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0xc6, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor d0, d0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0xc0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8f, 0x00, 0x80, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xf0, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor.eq d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0xe0, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor.eq d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x30, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor.ge d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x60, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor.ge d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x40, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor.ge.u d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x80, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor.ge.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x10, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor.lt d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x20, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor.lt d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x20, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor.lt.u d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x40, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor.lt.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x00, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor.ne d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x00, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor.ne d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x07, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_120" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor.t d0, d0, #0, d0, #0"
diff --git a/tests/MC/TriCore/tc130.s.yaml b/tests/MC/TriCore/tc130.s.yaml
new file mode 100644
index 000000000..ba702ef1c
--- /dev/null
+++ b/tests/MC/TriCore/tc130.s.yaml
@@ -0,0 +1,7066 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xc0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "abs d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xc0, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "abs.b d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xc0, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "abs.h d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xe0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "absdif d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0xc0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "absdif d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xe0, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "absdif.b d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xe0, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "absdif.h d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xf0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "absdifs d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0xe0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "absdifs d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xf0, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "absdifs.h d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xd0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "abss d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xd0, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "abss.h d0, d0"
+  -
+    input:
+      bytes: [ 0x12, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d0, d15, d0"
+  -
+    input:
+      bytes: [ 0x92, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d0, d15, #0"
+  -
+    input:
+      bytes: [ 0x1a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d15, d0, d0"
+  -
+    input:
+      bytes: [ 0x42, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d0, d0"
+  -
+    input:
+      bytes: [ 0x9a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d15, d0, #0"
+  -
+    input:
+      bytes: [ 0xc2, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x30, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "add.a a0, a0"
+  -
+    input:
+      bytes: [ 0xb0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "add.a a0, #0"
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0x10, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "add.a a0, a0, a0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "add.b d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x6b, 0x00, 0x21, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "add.f d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x00, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "add.h d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x50, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "addc d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0xa0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "addc d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x1b, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "addi d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x9b, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "addih d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x11, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "addih.a a0, a0, #0"
+  -
+    input:
+      bytes: [ 0x22, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "adds d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "adds d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "adds d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x20, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "adds.h d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x30, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "adds.hu d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x30, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "adds.u d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "adds.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x10, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "addsc.a a0, a0, d15, #0"
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0x00, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "addsc.a a0, a0, d0, #0"
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0x20, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "addsc.at a0, a0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "addx d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "addx d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x26, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d0, d0"
+  -
+    input:
+      bytes: [ 0x16, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d15, #0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8f, 0x00, 0x00, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x47, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.and.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x47, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.andn.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x00, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.eq d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.eq d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x40, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.ge d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x80, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.ge d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x50, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.ge.u d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0xa0, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.ge.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x20, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.lt d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x40, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.lt d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x30, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.lt.u d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x60, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.lt.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x10, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.ne d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x20, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.ne d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x47, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.nor.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x47, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.or.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x87, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0xe0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "andn d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8f, 0x00, 0xc0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "andn d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x87, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "andn.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0xe0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "bisr #0"
+  -
+    input:
+      bytes: [ 0xad, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "bisr #0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0x10, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "bmerge d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0x90, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "bsplit e0, d0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x80, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachea.i [a0+]#0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x80, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachea.i [p0+r]"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x80, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachea.i [+a0]#0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x80, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachea.i [p0+c]#0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x80, 0x0b ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachea.i [a0]#0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x00, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachea.w [a0+]#0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x00, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachea.w [p0+r]"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x00, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachea.w [+a0]#0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x00, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachea.w [p0+c]#0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x00, 0x0b ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachea.w [a0]#0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x40, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachea.wi [a0+]#0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x40, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachea.wi [p0+r]"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x40, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachea.wi [+a0]#0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x40, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachea.wi [p0+c]#0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x40, 0x0b ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachea.wi [a0]#0"
+  -
+    input:
+      bytes: [ 0x8a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "cadd d0, d15, #0"
+  -
+    input:
+      bytes: [ 0x2b, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "cadd d0, d0, d0, d0"
+  -
+    input:
+      bytes: [ 0xab, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "cadd d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0xca, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "caddn d0, d15, #0"
+  -
+    input:
+      bytes: [ 0x2b, 0x00, 0x10, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "caddn d0, d0, d0, d0"
+  -
+    input:
+      bytes: [ 0xab, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "caddn d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x5c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0"
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "calla #0"
+  -
+    input:
+      bytes: [ 0x2d, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "calli a0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0xc0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "clo d0, d0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0xd0, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "clo.h d0, d0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0xd0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "cls d0, d0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0xe0, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "cls.h d0, d0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0xb0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "clz d0, d0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0xc0, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "clz.h d0, d0"
+  -
+    input:
+      bytes: [ 0x2a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmov d0, d15, d0"
+  -
+    input:
+      bytes: [ 0xaa, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmov d0, d15, #0"
+  -
+    input:
+      bytes: [ 0x6a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmovn d0, d15, d0"
+  -
+    input:
+      bytes: [ 0xea, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmovn d0, d15, #0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmp.f d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x2b, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "csub d0, d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x2b, 0x00, 0x30, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "csubn d0, d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x00, 0xa0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "debug"
+  -
+    input:
+      bytes: [ 0x0d, 0x00, 0x00, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "debug"
+  -
+    input:
+      bytes: [ 0x77, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "dextr d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x17, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "dextr d0, d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0d, 0x00, 0x40, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "disable"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0x51, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "div.f d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0d, 0x00, 0x80, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "dsync"
+  -
+    input:
+      bytes: [ 0x6b, 0x00, 0xd0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "dvadj e0, e0, d0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0xa0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "dvinit e0, d0, d0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0xa0, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "dvinit.b e0, d0, d0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0xa0, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "dvinit.bu e0, d0, d0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0xa0, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "dvinit.h e0, d0, d0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0xa0, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "dvinit.hu e0, d0, d0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0xa0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "dvinit.u e0, d0, d0"
+  -
+    input:
+      bytes: [ 0x6b, 0x00, 0xf0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "dvstep e0, e0, d0"
+  -
+    input:
+      bytes: [ 0x6b, 0x00, 0xe0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "dvstep.u e0, e0, d0"
+  -
+    input:
+      bytes: [ 0x0d, 0x00, 0x00, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "enable"
+  -
+    input:
+      bytes: [ 0x3a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "eq d15, d0, d0"
+  -
+    input:
+      bytes: [ 0xba, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "eq d15, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x00, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "eq d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x00, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "eq d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "eq.a d0, a0, a0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x00, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "eq.b d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x00, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "eq.h d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x00, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "eq.w d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x60, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "eqany.b d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0xc0, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "eqany.b d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x60, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "eqany.h d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0xc0, 0x0e ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "eqany.h d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0x80, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "eqz.a d0, a0"
+  -
+    input:
+      bytes: [ 0x17, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr d0, d0, e0"
+  -
+    input:
+      bytes: [ 0x37, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr d0, d0, #0, #0"
+  -
+    input:
+      bytes: [ 0x57, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x17, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d0, d0, e0"
+  -
+    input:
+      bytes: [ 0x37, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d0, d0, #0, #0"
+  -
+    input:
+      bytes: [ 0x57, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0x01, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "ftoi d0, d0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0x11, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "ftoq31 d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0x21, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "ftou d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x40, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "ge d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x80, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "ge d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0x30, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "ge.a d0, a0, a0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x50, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "ge.u d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0xa0, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "ge.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x37, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "imask e0, d0, #0, #0"
+  -
+    input:
+      bytes: [ 0x57, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "imask e0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0xb7, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "imask e0, #0, #0, #0"
+  -
+    input:
+      bytes: [ 0xd7, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "imask e0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x67, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "ins.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x17, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d0, d0, d0, e0"
+  -
+    input:
+      bytes: [ 0x37, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d0, d0, d0, #0, #0"
+  -
+    input:
+      bytes: [ 0x57, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d0, d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x97, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d0, d0, #0, e0"
+  -
+    input:
+      bytes: [ 0xb7, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d0, d0, #0, #0, #0"
+  -
+    input:
+      bytes: [ 0xd7, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x67, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "insn.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0d, 0x00, 0xc0, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "isync"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0x41, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "itof d0, d0"
+  -
+    input:
+      bytes: [ 0x6b, 0x00, 0xa0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "ixmax e0, e0, d0"
+  -
+    input:
+      bytes: [ 0x6b, 0x00, 0xb0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "ixmax.u e0, e0, d0"
+  -
+    input:
+      bytes: [ 0x6b, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "ixmin e0, e0, d0"
+  -
+    input:
+      bytes: [ 0x6b, 0x00, 0x90, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "ixmin.u e0, e0, d0"
+  -
+    input:
+      bytes: [ 0x3c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0"
+  -
+    input:
+      bytes: [ 0x1d, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0"
+  -
+    input:
+      bytes: [ 0x9d, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "ja #0"
+  -
+    input:
+      bytes: [ 0x3e, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d0, #0"
+  -
+    input:
+      bytes: [ 0x1e, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, #0, #0"
+  -
+    input:
+      bytes: [ 0x5f, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d0, d0, #0"
+  -
+    input:
+      bytes: [ 0xdf, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d0, #0, #0"
+  -
+    input:
+      bytes: [ 0x7d, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq.a a0, a0, #0"
+  -
+    input:
+      bytes: [ 0x7f, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "jge d0, d0, #0"
+  -
+    input:
+      bytes: [ 0xff, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "jge d0, #0, #0"
+  -
+    input:
+      bytes: [ 0x7f, 0x00, 0x00, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "jge.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0xff, 0x00, 0x00, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "jge.u d0, #0, #0"
+  -
+    input:
+      bytes: [ 0xce, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "jgez d0, #0"
+  -
+    input:
+      bytes: [ 0x4e, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "jgtz d0, #0"
+  -
+    input:
+      bytes: [ 0xdc, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "ji a0"
+  -
+    input:
+      bytes: [ 0x2d, 0x00, 0x30, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "ji a0"
+  -
+    input:
+      bytes: [ 0x5d, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "jl #0"
+  -
+    input:
+      bytes: [ 0xdd, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "jla #0"
+  -
+    input:
+      bytes: [ 0x8e, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlez d0, #0"
+  -
+    input:
+      bytes: [ 0x2d, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "jli a0"
+  -
+    input:
+      bytes: [ 0x3f, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt d0, d0, #0"
+  -
+    input:
+      bytes: [ 0xbf, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt d0, #0, #0"
+  -
+    input:
+      bytes: [ 0x3f, 0x00, 0x00, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0xbf, 0x00, 0x00, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt.u d0, #0, #0"
+  -
+    input:
+      bytes: [ 0x0e, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "jltz d0, #0"
+  -
+    input:
+      bytes: [ 0x7e, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, d0, #0"
+  -
+    input:
+      bytes: [ 0x5e, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, #0, #0"
+  -
+    input:
+      bytes: [ 0x5f, 0x00, 0x00, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d0, d0, #0"
+  -
+    input:
+      bytes: [ 0xdf, 0x00, 0x00, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d0, #0, #0"
+  -
+    input:
+      bytes: [ 0x7d, 0x00, 0x00, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne.a a0, a0, #0"
+  -
+    input:
+      bytes: [ 0x1f, 0x00, 0x00, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "jned d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x9f, 0x00, 0x00, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "jned d0, #0, #0"
+  -
+    input:
+      bytes: [ 0x1f, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnei d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x9f, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnei d0, #0, #0"
+  -
+    input:
+      bytes: [ 0xee, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz d15, #0"
+  -
+    input:
+      bytes: [ 0xf6, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz d0, #0"
+  -
+    input:
+      bytes: [ 0x7c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz.a a0, #0"
+  -
+    input:
+      bytes: [ 0xbd, 0x00, 0x00, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz.a a0, #0"
+  -
+    input:
+      bytes: [ 0xae, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz.t d15, #0, #0"
+  -
+    input:
+      bytes: [ 0x6f, 0x00, 0x00, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz.t d0, #0, #0"
+  -
+    input:
+      bytes: [ 0x6e, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d15, #0"
+  -
+    input:
+      bytes: [ 0x76, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d0, #0"
+  -
+    input:
+      bytes: [ 0xbc, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.a a0, #0"
+  -
+    input:
+      bytes: [ 0xbd, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.a a0, #0"
+  -
+    input:
+      bytes: [ 0x2e, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.t d15, #0, #0"
+  -
+    input:
+      bytes: [ 0x6f, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.t d0, #0, #0"
+  -
+    input:
+      bytes: [ 0xd8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.a a15, [sp]#0"
+  -
+    input:
+      bytes: [ 0xc8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.a a0, [a15]#0"
+  -
+    input:
+      bytes: [ 0xcc, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.a a15, [a0]#0"
+  -
+    input:
+      bytes: [ 0xc4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.a a0, [a0+]"
+  -
+    input:
+      bytes: [ 0xd4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.a a0, [a0]"
+  -
+    input:
+      bytes: [ 0x99, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.a a0, [a0]#0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x80, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.a a0, [a0+]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0x80, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.a a0, [p0+r]"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x80, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.a a0, [+a0]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0x80, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.a a0, [p0+c]#0"
+  -
+    input:
+      bytes: [ 0x85, 0x00, 0x00, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.a a0, #0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x80, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.a a0, [a0]#0"
+  -
+    input:
+      bytes: [ 0x05, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.b d0, #0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.b d0, [a0+]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.b d0, [p0+r]"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.b d0, [+a0]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.b d0, [p0+c]#0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x00, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.b d0, [a0]#0"
+  -
+    input:
+      bytes: [ 0x14, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d0, [a0]"
+  -
+    input:
+      bytes: [ 0x0c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d15, [a0]#0"
+  -
+    input:
+      bytes: [ 0x08, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d0, [a15]#0"
+  -
+    input:
+      bytes: [ 0x04, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d0, [a0+]"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d0, [a0+]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d0, [p0+r]"
+  -
+    input:
+      bytes: [ 0x05, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d0, #0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x40, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d0, [+a0]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0x40, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d0, [p0+c]#0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x40, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d0, [a0]#0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x40, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.d e0, [a0+]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0x40, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.d e0, [p0+r]"
+  -
+    input:
+      bytes: [ 0x85, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.d e0, #0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x40, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.d e0, [+a0]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0x40, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.d e0, [p0+c]#0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x40, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.d e0, [a0]#0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0xc0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.da p0, [a0+]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0xc0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.da p0, [p0+r]"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0xc0, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.da p0, [+a0]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0xc0, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.da p0, [p0+c]#0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0xc0, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.da p0, [a0]#0"
+  -
+    input:
+      bytes: [ 0x85, 0x00, 0x00, 0x0c ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.da p0, #0"
+  -
+    input:
+      bytes: [ 0x84, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.h d0, [a0+]"
+  -
+    input:
+      bytes: [ 0x8c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.h d15, [a0]#0"
+  -
+    input:
+      bytes: [ 0x88, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.h d0, [a15]#0"
+  -
+    input:
+      bytes: [ 0x94, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.h d0, [a0]"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.h d0, [a0+]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.h d0, [p0+r]"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x80, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.h d0, [+a0]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0x80, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.h d0, [p0+c]#0"
+  -
+    input:
+      bytes: [ 0x05, 0x00, 0x00, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.h d0, #0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x80, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.h d0, [a0]#0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0xc0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.hu d0, [a0+]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0xc0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.hu d0, [p0+r]"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0xc0, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.hu d0, [+a0]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0xc0, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.hu d0, [p0+c]#0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0xc0, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.hu d0, [a0]#0"
+  -
+    input:
+      bytes: [ 0x05, 0x00, 0x00, 0x0c ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.hu d0, #0"
+  -
+    input:
+      bytes: [ 0x45, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.q d0, #0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x00, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.q d0, [a0+]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0x00, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.q d0, [p0+r]"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x00, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.q d0, [+a0]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0x00, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.q d0, [p0+c]#0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x00, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.q d0, [a0]#0"
+  -
+    input:
+      bytes: [ 0x58, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d15, [sp]#0"
+  -
+    input:
+      bytes: [ 0x54, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d0, [a0]"
+  -
+    input:
+      bytes: [ 0x44, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d0, [a0+]"
+  -
+    input:
+      bytes: [ 0x4c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d15, [a0]#0"
+  -
+    input:
+      bytes: [ 0x48, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d0, [a15]#0"
+  -
+    input:
+      bytes: [ 0x19, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d0, [a0]#0"
+  -
+    input:
+      bytes: [ 0x85, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d0, #0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x00, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d0, [a0+]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0x00, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d0, [p0+r]"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x00, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d0, [+a0]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0x00, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d0, [p0+c]#0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x00, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d0, [a0]#0"
+  -
+    input:
+      bytes: [ 0x15, 0x00, 0x00, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldlcx #0"
+  -
+    input:
+      bytes: [ 0x49, 0x00, 0x00, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldlcx [a0]#0"
+  -
+    input:
+      bytes: [ 0x49, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldmst [a0+]#0, e0"
+  -
+    input:
+      bytes: [ 0x69, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldmst [p0+r], e0"
+  -
+    input:
+      bytes: [ 0xe5, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldmst #0, e0"
+  -
+    input:
+      bytes: [ 0x49, 0x00, 0x40, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldmst [+a0]#0, e0"
+  -
+    input:
+      bytes: [ 0x69, 0x00, 0x40, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldmst [p0+c]#0, e0"
+  -
+    input:
+      bytes: [ 0x49, 0x00, 0x40, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldmst [a0]#0, e0"
+  -
+    input:
+      bytes: [ 0x49, 0x00, 0x40, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "lducx [a0]#0"
+  -
+    input:
+      bytes: [ 0x15, 0x00, 0x00, 0x0c ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "lducx #0"
+  -
+    input:
+      bytes: [ 0xc5, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a0, #0"
+  -
+    input:
+      bytes: [ 0xd9, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a0, [a0]#0"
+  -
+    input:
+      bytes: [ 0x49, 0x00, 0x00, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a0, [a0]#0"
+  -
+    input:
+      bytes: [ 0xfc, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "loop a0, #0xffffffe0"
+  -
+    input:
+      bytes: [ 0xfd, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "loop a0, #0"
+  -
+    input:
+      bytes: [ 0xfd, 0x00, 0x00, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "loopu #0"
+  -
+    input:
+      bytes: [ 0x7a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "lt d15, d0, d0"
+  -
+    input:
+      bytes: [ 0xfa, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "lt d15, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x20, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "lt d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x40, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "lt d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0x20, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "lt.a d0, a0, a0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x20, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "lt.b d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x30, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "lt.bu d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x20, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "lt.h d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x30, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "lt.hu d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x30, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "lt.u d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x60, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "lt.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x20, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "lt.w d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x30, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "lt.wu d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x03, 0x00, 0x0a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd d0, d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x13, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x13, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd e0, e0, d0, #0"
+  -
+    input:
+      bytes: [ 0x03, 0x00, 0x6a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd e0, e0, d0, d0"
+  -
+    input:
+      bytes: [ 0x6b, 0x00, 0x61, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd.f d0, d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd.h e0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0x64, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd.h e0, e0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0x68, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd.h e0, e0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0x6c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd.h e0, e0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x10, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd.q d0, d0, d0u, d0u, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd.q d0, d0, d0, d0u, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x04, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd.q d0, d0, d0, d0l, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x08, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd.q d0, d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x14, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd.q d0, d0, d0l, d0l, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd.q e0, e0, d0, d0u, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x64, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd.q e0, e0, d0, d0l, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x6c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd.q e0, e0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x70, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd.q e0, e0, d0u, d0u, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x74, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd.q e0, e0, d0l, d0l, #0"
+  -
+    input:
+      bytes: [ 0x13, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd.u e0, e0, d0, #0"
+  -
+    input:
+      bytes: [ 0x03, 0x00, 0x68, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd.u e0, e0, d0, d0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0x70, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddm.h e0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0x74, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddm.h e0, e0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0x78, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddm.h e0, e0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0x7c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddm.h e0, e0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0xf0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddms.h e0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0xf4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddms.h e0, e0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0xf8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddms.h e0, e0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0xfc, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddms.h e0, e0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x78, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddr.h d0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0x30, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddr.h d0, d0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0x34, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddr.h d0, d0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0x38, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddr.h d0, d0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0x3c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddr.h d0, d0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x18, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddr.q d0, d0, d0u, d0u, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x1c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddr.q d0, d0, d0l, d0l, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0xf8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddrs.h d0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0xb0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddrs.h d0, d0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0xb4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddrs.h d0, d0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0xb8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddrs.h d0, d0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0xbc, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddrs.h d0, d0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x98, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddrs.q d0, d0, d0u, d0u, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x9c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddrs.q d0, d0, d0l, d0l, #0"
+  -
+    input:
+      bytes: [ 0x03, 0x00, 0x8a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds d0, d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x13, 0x00, 0xa0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x13, 0x00, 0xe0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds e0, e0, d0, #0"
+  -
+    input:
+      bytes: [ 0x03, 0x00, 0xea, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds e0, e0, d0, d0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0xe0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds.h e0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0xe4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds.h e0, e0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0xe8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds.h e0, e0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0xec, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds.h e0, e0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x90, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds.q d0, d0, d0u, d0u, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds.q d0, d0, d0, d0u, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x84, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds.q d0, d0, d0, d0l, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x88, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds.q d0, d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x94, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds.q d0, d0, d0l, d0l, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0xe0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds.q e0, e0, d0, d0u, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0xe4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds.q e0, e0, d0, d0l, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0xec, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds.q e0, e0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0xf0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds.q e0, e0, d0u, d0u, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0xf4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds.q e0, e0, d0l, d0l, #0"
+  -
+    input:
+      bytes: [ 0x13, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds.u d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x03, 0x00, 0x88, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds.u d0, d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x13, 0x00, 0xc0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds.u e0, e0, d0, #0"
+  -
+    input:
+      bytes: [ 0x03, 0x00, 0xe8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds.u e0, e0, d0, d0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsu.h e0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0x64, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsu.h e0, e0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0x68, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsu.h e0, e0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0x6c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsu.h e0, e0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0x70, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsum.h e0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0x74, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsum.h e0, e0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0x78, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsum.h e0, e0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0x7c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsum.h e0, e0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0xf0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsums.h e0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0xf4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsums.h e0, e0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0xf8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsums.h e0, e0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0xfc, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsums.h e0, e0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0x30, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsur.h d0, d0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0x34, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsur.h d0, d0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0x38, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsur.h d0, d0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0x3c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsur.h d0, d0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0xb0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsurs.h d0, d0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0xb4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsurs.h d0, d0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0xb8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsurs.h d0, d0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0xbc, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsurs.h d0, d0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0xe0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsus.h e0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0xe4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsus.h e0, e0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0xe8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsus.h e0, e0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0xec, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsus.h e0, e0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xa0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "max d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x40, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "max d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xa0, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "max.b d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xb0, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "max.bu d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xa0, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "max.h d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xb0, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "max.hu d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xb0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "max.u d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x60, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "max.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x4d, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "mfcr d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x80, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "min d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x00, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "min d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x80, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "min.b d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x90, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "min.bu d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x80, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "min.h d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x90, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "min.hu d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x90, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "min.u d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x20, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "min.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x02, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d0, d0"
+  -
+    input:
+      bytes: [ 0x82, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d0, #0"
+  -
+    input:
+      bytes: [ 0xda, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d15, #0"
+  -
+    input:
+      bytes: [ 0x3b, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xf0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d0, d0"
+  -
+    input:
+      bytes: [ 0xa0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.a a0, #0"
+  -
+    input:
+      bytes: [ 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.a a0, d0"
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0x30, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.a a0, d0"
+  -
+    input:
+      bytes: [ 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.aa a0, a0"
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.aa a0, a0"
+  -
+    input:
+      bytes: [ 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.d d0, a0"
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0xc0, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.d d0, a0"
+  -
+    input:
+      bytes: [ 0xbb, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.u d0, #0"
+  -
+    input:
+      bytes: [ 0x7b, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh d0, #0"
+  -
+    input:
+      bytes: [ 0x91, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a0, #0"
+  -
+    input:
+      bytes: [ 0x23, 0x00, 0x0a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub d0, d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x33, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x33, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub e0, e0, d0, #0"
+  -
+    input:
+      bytes: [ 0x23, 0x00, 0x6a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub e0, e0, d0, d0"
+  -
+    input:
+      bytes: [ 0x6b, 0x00, 0x71, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub.f d0, d0, d0, d0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub.h e0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0x64, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub.h e0, e0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0x68, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub.h e0, e0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0x6c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub.h e0, e0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x10, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub.q d0, d0, d0u, d0u, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub.q d0, d0, d0, d0u, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x04, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub.q d0, d0, d0, d0l, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x08, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub.q d0, d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x14, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub.q d0, d0, d0l, d0l, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub.q e0, e0, d0, d0u, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x64, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub.q e0, e0, d0, d0l, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x6c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub.q e0, e0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x70, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub.q e0, e0, d0u, d0u, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x74, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub.q e0, e0, d0l, d0l, #0"
+  -
+    input:
+      bytes: [ 0x33, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub.u e0, e0, d0, #0"
+  -
+    input:
+      bytes: [ 0x23, 0x00, 0x68, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub.u e0, e0, d0, d0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubad.h e0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x64, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubad.h e0, e0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x68, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubad.h e0, e0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x6c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubad.h e0, e0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x70, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubadm.h e0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x74, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubadm.h e0, e0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x78, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubadm.h e0, e0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x7c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubadm.h e0, e0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xf0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubadms.h e0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xf4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubadms.h e0, e0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xf8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubadms.h e0, e0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xfc, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubadms.h e0, e0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x30, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubadr.h d0, d0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x34, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubadr.h d0, d0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x38, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubadr.h d0, d0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x3c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubadr.h d0, d0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xb0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubadrs.h d0, d0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xb4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubadrs.h d0, d0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xb8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubadrs.h d0, d0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xbc, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubadrs.h d0, d0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xe0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubads.h e0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xe4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubads.h e0, e0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xe8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubads.h e0, e0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xec, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubads.h e0, e0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0x70, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubm.h e0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0x74, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubm.h e0, e0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0x78, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubm.h e0, e0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0x7c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubm.h e0, e0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0xf0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubms.h e0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0xf4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubms.h e0, e0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0xf8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubms.h e0, e0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0xfc, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubms.h e0, e0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x78, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubr.h d0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0x30, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubr.h d0, d0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0x34, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubr.h d0, d0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0x38, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubr.h d0, d0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0x3c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubr.h d0, d0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x18, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubr.q d0, d0, d0u, d0u, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x1c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubr.q d0, d0, d0l, d0l, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0xf8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubrs.h d0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0xb0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubrs.h d0, d0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0xb4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubrs.h d0, d0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0xb8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubrs.h d0, d0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0xbc, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubrs.h d0, d0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x98, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubrs.q d0, d0, d0u, d0u, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x9c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubrs.q d0, d0, d0l, d0l, #0"
+  -
+    input:
+      bytes: [ 0x23, 0x00, 0x8a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs d0, d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x33, 0x00, 0xa0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x33, 0x00, 0xe0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs e0, e0, d0, #0"
+  -
+    input:
+      bytes: [ 0x23, 0x00, 0xea, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs e0, e0, d0, d0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0xe0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs.h e0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0xe4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs.h e0, e0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0xe8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs.h e0, e0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0xec, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs.h e0, e0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x90, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs.q d0, d0, d0u, d0u, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs.q d0, d0, d0, d0u, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x84, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs.q d0, d0, d0, d0l, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x88, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs.q d0, d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x94, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs.q d0, d0, d0l, d0l, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0xe0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs.q e0, e0, d0, d0u, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0xe4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs.q e0, e0, d0, d0l, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0xec, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs.q e0, e0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0xf0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs.q e0, e0, d0u, d0u, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0xf4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs.q e0, e0, d0l, d0l, #0"
+  -
+    input:
+      bytes: [ 0x33, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs.u d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x23, 0x00, 0x88, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs.u d0, d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x33, 0x00, 0xc0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs.u e0, e0, d0, #0"
+  -
+    input:
+      bytes: [ 0x23, 0x00, 0xe8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs.u e0, e0, d0, d0"
+  -
+    input:
+      bytes: [ 0xcd, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "mtcr #0, d0"
+  -
+    input:
+      bytes: [ 0xe2, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul d0, d0"
+  -
+    input:
+      bytes: [ 0x53, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x73, 0x00, 0x0a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x53, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul e0, d0, #0"
+  -
+    input:
+      bytes: [ 0x73, 0x00, 0x6a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul e0, d0, d0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0x41, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.f d0, d0, d0"
+  -
+    input:
+      bytes: [ 0xb3, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.h e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xb3, 0x00, 0x64, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.h e0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xb3, 0x00, 0x68, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.h e0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xb3, 0x00, 0x6c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.h e0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0x93, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.q d0, d0, d0u, #0"
+  -
+    input:
+      bytes: [ 0x93, 0x00, 0x04, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.q d0, d0, d0l, #0"
+  -
+    input:
+      bytes: [ 0x93, 0x00, 0x08, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.q d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x93, 0x00, 0x10, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.q d0, d0u, d0u, #0"
+  -
+    input:
+      bytes: [ 0x93, 0x00, 0x14, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.q d0, d0l, d0l, #0"
+  -
+    input:
+      bytes: [ 0x93, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.q e0, d0, d0u, #0"
+  -
+    input:
+      bytes: [ 0x93, 0x00, 0x64, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.q e0, d0, d0l, #0"
+  -
+    input:
+      bytes: [ 0x93, 0x00, 0x6c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.q e0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x53, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.u e0, d0, #0"
+  -
+    input:
+      bytes: [ 0x73, 0x00, 0x68, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.u e0, d0, d0"
+  -
+    input:
+      bytes: [ 0xb3, 0x00, 0x70, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulm.h e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xb3, 0x00, 0x74, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulm.h e0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xb3, 0x00, 0x78, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulm.h e0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xb3, 0x00, 0x7c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulm.h e0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0xb3, 0x00, 0xf0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulms.h e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xb3, 0x00, 0xf4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulms.h e0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xb3, 0x00, 0xf8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulms.h e0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xb3, 0x00, 0xfc, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulms.h e0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0xb3, 0x00, 0x30, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulr.h d0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xb3, 0x00, 0x34, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulr.h d0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xb3, 0x00, 0x38, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulr.h d0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xb3, 0x00, 0x3c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulr.h d0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0x93, 0x00, 0x18, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulr.q d0, d0u, d0u, #0"
+  -
+    input:
+      bytes: [ 0x93, 0x00, 0x1c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulr.q d0, d0l, d0l, #0"
+  -
+    input:
+      bytes: [ 0x53, 0x00, 0xa0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "muls d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x73, 0x00, 0x8a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "muls d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x53, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "muls.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x73, 0x00, 0x88, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "muls.u d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0x90, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "nand d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8f, 0x00, 0x20, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "nand d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x07, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "nand.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x10, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "ne d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x20, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "ne d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0x10, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "ne.a d0, a0, a0"
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0x90, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "nez.a d0, a0"
+  -
+    input:
+      bytes: [ 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "nop"
+  -
+    input:
+      bytes: [ 0x0d, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "nop"
+  -
+    input:
+      bytes: [ 0x46, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "nor d0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0xb0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "nor d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8f, 0x00, 0x60, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "nor d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x87, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "nor.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0xa6, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "or d0, d0"
+  -
+    input:
+      bytes: [ 0x96, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "or d15, #0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0xa0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "or d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8f, 0x00, 0x40, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "or d0, d0, #0"
+  -
+    input:
+      bytes: [ 0xc7, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.and.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0xc7, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.andn.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x70, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.eq d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0xe0, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.eq d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xb0, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.ge d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x60, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.ge d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xc0, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.ge.u d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x80, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.ge.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x90, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.lt d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x20, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.lt d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xa0, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.lt.u d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x40, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.lt.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x80, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.ne d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x00, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.ne d0, d0, #0"
+  -
+    input:
+      bytes: [ 0xc7, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.nor.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0xc7, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.or.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x87, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0xf0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "orn d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8f, 0x00, 0xe0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "orn d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x07, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "orn.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x6b, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "pack d0, e0, d0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "parity d0, d0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0x51, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "q31tof d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0x91, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "qseed.f d0, d0"
+  -
+    input:
+      bytes: [ 0x00, 0x90 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "ret"
+  -
+    input:
+      bytes: [ 0x0d, 0x00, 0x80, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "ret"
+  -
+    input:
+      bytes: [ 0x00, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "rfe"
+  -
+    input:
+      bytes: [ 0x0d, 0x00, 0xc0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "rfe"
+  -
+    input:
+      bytes: [ 0x0d, 0x00, 0x40, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "rfm"
+  -
+    input:
+      bytes: [ 0x0d, 0x00, 0x40, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "rslcx"
+  -
+    input:
+      bytes: [ 0x2f, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "rstv"
+  -
+    input:
+      bytes: [ 0x32, 0x50 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "rsub d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x00, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "rsub d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x40, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "rsubs d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x60, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "rsubs.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x32, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "sat.b d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xe0, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "sat.b d0, d0"
+  -
+    input:
+      bytes: [ 0x32, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "sat.bu d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xf0, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "sat.bu d0, d0"
+  -
+    input:
+      bytes: [ 0x32, 0x20 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "sat.h d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xe0, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "sat.h d0, d0"
+  -
+    input:
+      bytes: [ 0x32, 0x30 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "sat.hu d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xf0, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "sat.hu d0, d0"
+  -
+    input:
+      bytes: [ 0x2b, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "sel d0, d0, d0, d0"
+  -
+    input:
+      bytes: [ 0xab, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "sel d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x2b, 0x00, 0x50, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "seln d0, d0, d0, d0"
+  -
+    input:
+      bytes: [ 0xab, 0x00, 0xa0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "seln d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x06, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh d0, #0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8f, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x27, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.and.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x27, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.andn.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x70, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.eq d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0xe0, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.eq d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xb0, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.ge d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x60, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.ge d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xc0, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.ge.u d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x80, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.ge.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.h d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8f, 0x00, 0x00, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.h d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x90, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.lt d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x20, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.lt d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xa0, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.lt.u d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x40, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.lt.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0xa7, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.nand.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x80, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.ne d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x00, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.ne d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x27, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.nor.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x27, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.or.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0xa7, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.orn.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0xa7, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.xnor.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0xa7, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.xor.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x86, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha d0, #0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0x10, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8f, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0x10, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha.h d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8f, 0x00, 0x20, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha.h d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "shas d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8f, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "shas d0, d0, #0"
+  -
+    input:
+      bytes: [ 0xf8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.a [sp]#0, a15"
+  -
+    input:
+      bytes: [ 0xec, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.a [a0]#0, a15"
+  -
+    input:
+      bytes: [ 0xe8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.a [a15]#0, a0"
+  -
+    input:
+      bytes: [ 0xe4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.a [a0+], a0"
+  -
+    input:
+      bytes: [ 0xf4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.a [a0], a0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x80, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.a [a0+]#0, a0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x80, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.a [p0+r], a0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x80, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.a [+a0]#0, a0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x80, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.a [p0+c]#0, a0"
+  -
+    input:
+      bytes: [ 0xa5, 0x00, 0x00, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.a #0, a0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x80, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.a [a0]#0, a0"
+  -
+    input:
+      bytes: [ 0x34, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [a0], d0"
+  -
+    input:
+      bytes: [ 0x28, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [a15]#0, d0"
+  -
+    input:
+      bytes: [ 0x2c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [a0]#0, d15"
+  -
+    input:
+      bytes: [ 0x24, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [a0+], d0"
+  -
+    input:
+      bytes: [ 0x25, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b #0, d0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [a0+]#0, d0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [p0+r], d0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [+a0]#0, d0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [p0+c]#0, d0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x00, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [a0]#0, d0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x40, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.d [a0+]#0, e0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x40, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.d [p0+r], e0"
+  -
+    input:
+      bytes: [ 0xa5, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.d #0, e0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x40, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.d [+a0]#0, e0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x40, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.d [p0+c]#0, e0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x40, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.d [a0]#0, e0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0xc0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.da [a0+]#0, p0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0xc0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.da [p0+r], p0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0xc0, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.da [+a0]#0, p0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0xc0, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.da [p0+c]#0, p0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0xc0, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.da [a0]#0, p0"
+  -
+    input:
+      bytes: [ 0xa5, 0x00, 0x00, 0x0c ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.da #0, p0"
+  -
+    input:
+      bytes: [ 0xa4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [a0+], d0"
+  -
+    input:
+      bytes: [ 0xa8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [a15]#0, d0"
+  -
+    input:
+      bytes: [ 0xac, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [a0]#0, d15"
+  -
+    input:
+      bytes: [ 0xb4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [a0], d0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [a0+]#0, d0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [p0+r], d0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x80, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [+a0]#0, d0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x80, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [p0+c]#0, d0"
+  -
+    input:
+      bytes: [ 0x25, 0x00, 0x00, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h #0, d0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x80, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [a0]#0, d0"
+  -
+    input:
+      bytes: [ 0x65, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.q #0, d0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x00, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.q [a0+]#0, d0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x00, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.q [p0+r], d0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x00, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.q [+a0]#0, d0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x00, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.q [p0+c]#0, d0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x00, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.q [a0]#0, d0"
+  -
+    input:
+      bytes: [ 0xd5, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.t #0, #0, #0"
+  -
+    input:
+      bytes: [ 0x78, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w [sp]#0, d15"
+  -
+    input:
+      bytes: [ 0x74, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w [a0], d0"
+  -
+    input:
+      bytes: [ 0x64, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w [a0+], d0"
+  -
+    input:
+      bytes: [ 0x68, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w [a15]#0, d0"
+  -
+    input:
+      bytes: [ 0x6c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w [a0]#0, d15"
+  -
+    input:
+      bytes: [ 0x59, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w [a0]#0, d0"
+  -
+    input:
+      bytes: [ 0xa5, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w #0, d0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x00, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w [a0+]#0, d0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x00, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w [p0+r], d0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x00, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w [+a0]#0, d0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x00, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w [p0+c]#0, d0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x00, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w [a0]#0, d0"
+  -
+    input:
+      bytes: [ 0x15, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "stlcx #0"
+  -
+    input:
+      bytes: [ 0x49, 0x00, 0x80, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "stlcx [a0]#0"
+  -
+    input:
+      bytes: [ 0x15, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "stucx #0"
+  -
+    input:
+      bytes: [ 0x49, 0x00, 0xc0, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "stucx [a0]#0"
+  -
+    input:
+      bytes: [ 0x52, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub d0, d15, d0"
+  -
+    input:
+      bytes: [ 0x5a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub d15, d0, d0"
+  -
+    input:
+      bytes: [ 0xa2, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub.a sp, #0"
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub.a a0, a0, a0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x80, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub.b d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x6b, 0x00, 0x31, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub.f d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x80, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub.h d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xd0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "subc d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x62, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "subs d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xa0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "subs d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xa0, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "subs.h d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xb0, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "subs.hu d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xb0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "subs.u d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xc0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "subx d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0d, 0x00, 0x00, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "svlcx"
+  -
+    input:
+      bytes: [ 0x49, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "swap.w [a0+]#0, d0"
+  -
+    input:
+      bytes: [ 0x69, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "swap.w [p0+r], d0"
+  -
+    input:
+      bytes: [ 0xe5, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "swap.w #0, d0"
+  -
+    input:
+      bytes: [ 0x49, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "swap.w [+a0]#0, d0"
+  -
+    input:
+      bytes: [ 0x69, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "swap.w [p0+c]#0, d0"
+  -
+    input:
+      bytes: [ 0x49, 0x00, 0x00, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "swap.w [a0]#0, d0"
+  -
+    input:
+      bytes: [ 0xad, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "syscall #0"
+  -
+    input:
+      bytes: [ 0x75, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "tlbdemap d0"
+  -
+    input:
+      bytes: [ 0x75, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "tlbflush.a"
+  -
+    input:
+      bytes: [ 0x75, 0x00, 0x50, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "tlbflush.b"
+  -
+    input:
+      bytes: [ 0x75, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "tlbmap e0"
+  -
+    input:
+      bytes: [ 0x75, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "tlbprobe.a d0"
+  -
+    input:
+      bytes: [ 0x75, 0x00, 0x90, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "tlbprobe.i d0"
+  -
+    input:
+      bytes: [ 0x0d, 0x00, 0x40, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "trapsv"
+  -
+    input:
+      bytes: [ 0x0d, 0x00, 0x00, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "trapv"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "unpack e0, d0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0xc1, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "updfl d0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0x61, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "utof d0, d0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0xd0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "xnor d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8f, 0x00, 0xa0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "xnor d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x07, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "xnor.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0xc6, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor d0, d0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0xc0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8f, 0x00, 0x80, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xf0, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor.eq d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0xe0, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor.eq d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x30, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor.ge d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x60, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor.ge d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x40, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor.ge.u d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x80, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor.ge.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x10, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor.lt d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x20, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor.lt d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x20, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor.lt.u d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x40, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor.lt.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x00, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor.ne d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x00, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor.ne d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x07, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_130" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor.t d0, d0, #0, d0, #0"
diff --git a/tests/MC/TriCore/tc131.s.yaml b/tests/MC/TriCore/tc131.s.yaml
new file mode 100644
index 000000000..72485a82d
--- /dev/null
+++ b/tests/MC/TriCore/tc131.s.yaml
@@ -0,0 +1,7147 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xc0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "abs d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xc0, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "abs.b d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xc0, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "abs.h d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xe0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "absdif d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0xc0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "absdif d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xe0, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "absdif.b d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xe0, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "absdif.h d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xf0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "absdifs d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0xe0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "absdifs d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xf0, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "absdifs.h d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xd0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "abss d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xd0, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "abss.h d0, d0"
+  -
+    input:
+      bytes: [ 0x12, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d0, d15, d0"
+  -
+    input:
+      bytes: [ 0x92, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d0, d15, #0"
+  -
+    input:
+      bytes: [ 0x1a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d15, d0, d0"
+  -
+    input:
+      bytes: [ 0x42, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d0, d0"
+  -
+    input:
+      bytes: [ 0x9a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d15, d0, #0"
+  -
+    input:
+      bytes: [ 0xc2, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x30, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "add.a a0, a0"
+  -
+    input:
+      bytes: [ 0xb0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "add.a a0, #0"
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0x10, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "add.a a0, a0, a0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "add.b d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x6b, 0x00, 0x21, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "add.f d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x00, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "add.h d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x50, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "addc d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0xa0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "addc d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x1b, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "addi d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x9b, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "addih d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x11, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "addih.a a0, a0, #0"
+  -
+    input:
+      bytes: [ 0x22, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "adds d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "adds d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "adds d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x20, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "adds.h d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x30, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "adds.hu d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x30, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "adds.u d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "adds.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x10, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "addsc.a a0, a0, d15, #0"
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0x00, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "addsc.a a0, a0, d0, #0"
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0x20, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "addsc.at a0, a0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "addx d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "addx d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x26, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d0, d0"
+  -
+    input:
+      bytes: [ 0x16, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d15, #0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8f, 0x00, 0x00, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x47, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.and.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x47, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.andn.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x00, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.eq d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.eq d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x40, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.ge d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x80, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.ge d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x50, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.ge.u d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0xa0, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.ge.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x20, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.lt d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x40, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.lt d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x30, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.lt.u d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x60, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.lt.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x10, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.ne d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x20, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.ne d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x47, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.nor.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x47, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.or.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x87, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0xe0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "andn d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8f, 0x00, 0xc0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "andn d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x87, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "andn.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0xe0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "bisr #0"
+  -
+    input:
+      bytes: [ 0xad, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "bisr #0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0x10, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "bmerge d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0x90, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "bsplit e0, d0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x80, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachea.i [a0+]#0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x80, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachea.i [p0+r]"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x80, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachea.i [+a0]#0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x80, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachea.i [p0+c]#0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x80, 0x0b ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachea.i [a0]#0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x00, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachea.w [a0+]#0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x00, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachea.w [p0+r]"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x00, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachea.w [+a0]#0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x00, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachea.w [p0+c]#0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x00, 0x0b ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachea.w [a0]#0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x40, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachea.wi [a0+]#0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x40, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachea.wi [p0+r]"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x40, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachea.wi [+a0]#0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x40, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachea.wi [p0+c]#0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x40, 0x0b ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachea.wi [a0]#0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0xc0, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachei.w [a0+]#0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0xc0, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachei.w [+a0]#0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0xc0, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachei.w [a0]#0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0xc0, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachei.wi [a0+]#0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0xc0, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachei.wi [+a0]#0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0xc0, 0x0b ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachei.wi [a0]#0"
+  -
+    input:
+      bytes: [ 0x8a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "cadd d0, d15, #0"
+  -
+    input:
+      bytes: [ 0x2b, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "cadd d0, d0, d0, d0"
+  -
+    input:
+      bytes: [ 0xab, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "cadd d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0xca, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "caddn d0, d15, #0"
+  -
+    input:
+      bytes: [ 0x2b, 0x00, 0x10, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "caddn d0, d0, d0, d0"
+  -
+    input:
+      bytes: [ 0xab, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "caddn d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x5c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0"
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "calla #0"
+  -
+    input:
+      bytes: [ 0x2d, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "calli a0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0xc0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "clo d0, d0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0xd0, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "clo.h d0, d0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0xd0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "cls d0, d0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0xe0, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "cls.h d0, d0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0xb0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "clz d0, d0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0xc0, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "clz.h d0, d0"
+  -
+    input:
+      bytes: [ 0x2a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmov d0, d15, d0"
+  -
+    input:
+      bytes: [ 0xaa, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmov d0, d15, #0"
+  -
+    input:
+      bytes: [ 0x6a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmovn d0, d15, d0"
+  -
+    input:
+      bytes: [ 0xea, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmovn d0, d15, #0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmp.f d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x2b, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "csub d0, d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x2b, 0x00, 0x30, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "csubn d0, d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x00, 0xa0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "debug"
+  -
+    input:
+      bytes: [ 0x0d, 0x00, 0x00, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "debug"
+  -
+    input:
+      bytes: [ 0x77, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "dextr d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x17, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "dextr d0, d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0d, 0x00, 0x40, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "disable"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0x51, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "div.f d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0d, 0x00, 0x80, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "dsync"
+  -
+    input:
+      bytes: [ 0x6b, 0x00, 0xd0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "dvadj e0, e0, d0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0xa0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "dvinit e0, d0, d0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0xa0, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "dvinit.b e0, d0, d0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0xa0, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "dvinit.bu e0, d0, d0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0xa0, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "dvinit.h e0, d0, d0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0xa0, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "dvinit.hu e0, d0, d0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0xa0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "dvinit.u e0, d0, d0"
+  -
+    input:
+      bytes: [ 0x6b, 0x00, 0xf0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "dvstep e0, e0, d0"
+  -
+    input:
+      bytes: [ 0x6b, 0x00, 0xe0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "dvstep.u e0, e0, d0"
+  -
+    input:
+      bytes: [ 0x0d, 0x00, 0x00, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "enable"
+  -
+    input:
+      bytes: [ 0x3a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "eq d15, d0, d0"
+  -
+    input:
+      bytes: [ 0xba, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "eq d15, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x00, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "eq d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x00, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "eq d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "eq.a d0, a0, a0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x00, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "eq.b d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x00, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "eq.h d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x00, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "eq.w d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x60, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "eqany.b d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0xc0, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "eqany.b d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x60, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "eqany.h d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0xc0, 0x0e ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "eqany.h d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0x80, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "eqz.a d0, a0"
+  -
+    input:
+      bytes: [ 0x17, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr d0, d0, e0"
+  -
+    input:
+      bytes: [ 0x37, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr d0, d0, #0, #0"
+  -
+    input:
+      bytes: [ 0x57, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x17, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d0, d0, e0"
+  -
+    input:
+      bytes: [ 0x37, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d0, d0, #0, #0"
+  -
+    input:
+      bytes: [ 0x57, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0x01, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "ftoi d0, d0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0x11, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "ftoq31 d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0x21, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "ftou d0, d0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0x31, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "ftoiz d0, d0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0x81, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "ftoq31z d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0x71, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "ftouz d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x40, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "ge d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x80, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "ge d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0x30, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "ge.a d0, a0, a0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x50, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "ge.u d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0xa0, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "ge.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x37, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "imask e0, d0, #0, #0"
+  -
+    input:
+      bytes: [ 0x57, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "imask e0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0xb7, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "imask e0, #0, #0, #0"
+  -
+    input:
+      bytes: [ 0xd7, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "imask e0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x67, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "ins.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x17, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d0, d0, d0, e0"
+  -
+    input:
+      bytes: [ 0x37, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d0, d0, d0, #0, #0"
+  -
+    input:
+      bytes: [ 0x57, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d0, d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x97, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d0, d0, #0, e0"
+  -
+    input:
+      bytes: [ 0xb7, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d0, d0, #0, #0, #0"
+  -
+    input:
+      bytes: [ 0xd7, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x67, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "insn.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0d, 0x00, 0xc0, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "isync"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0x41, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "itof d0, d0"
+  -
+    input:
+      bytes: [ 0x6b, 0x00, 0xa0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "ixmax e0, e0, d0"
+  -
+    input:
+      bytes: [ 0x6b, 0x00, 0xb0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "ixmax.u e0, e0, d0"
+  -
+    input:
+      bytes: [ 0x6b, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "ixmin e0, e0, d0"
+  -
+    input:
+      bytes: [ 0x6b, 0x00, 0x90, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "ixmin.u e0, e0, d0"
+  -
+    input:
+      bytes: [ 0x3c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0"
+  -
+    input:
+      bytes: [ 0x1d, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0"
+  -
+    input:
+      bytes: [ 0x9d, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "ja #0"
+  -
+    input:
+      bytes: [ 0x3e, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d0, #0"
+  -
+    input:
+      bytes: [ 0x1e, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, #0, #0"
+  -
+    input:
+      bytes: [ 0x5f, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d0, d0, #0"
+  -
+    input:
+      bytes: [ 0xdf, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d0, #0, #0"
+  -
+    input:
+      bytes: [ 0x7d, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq.a a0, a0, #0"
+  -
+    input:
+      bytes: [ 0x7f, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "jge d0, d0, #0"
+  -
+    input:
+      bytes: [ 0xff, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "jge d0, #0, #0"
+  -
+    input:
+      bytes: [ 0x7f, 0x00, 0x00, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "jge.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0xff, 0x00, 0x00, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "jge.u d0, #0, #0"
+  -
+    input:
+      bytes: [ 0xce, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "jgez d0, #0"
+  -
+    input:
+      bytes: [ 0x4e, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "jgtz d0, #0"
+  -
+    input:
+      bytes: [ 0xdc, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "ji a0"
+  -
+    input:
+      bytes: [ 0x2d, 0x00, 0x30, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "ji a0"
+  -
+    input:
+      bytes: [ 0x5d, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "jl #0"
+  -
+    input:
+      bytes: [ 0xdd, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "jla #0"
+  -
+    input:
+      bytes: [ 0x8e, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlez d0, #0"
+  -
+    input:
+      bytes: [ 0x2d, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "jli a0"
+  -
+    input:
+      bytes: [ 0x3f, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt d0, d0, #0"
+  -
+    input:
+      bytes: [ 0xbf, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt d0, #0, #0"
+  -
+    input:
+      bytes: [ 0x3f, 0x00, 0x00, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0xbf, 0x00, 0x00, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt.u d0, #0, #0"
+  -
+    input:
+      bytes: [ 0x0e, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "jltz d0, #0"
+  -
+    input:
+      bytes: [ 0x7e, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, d0, #0"
+  -
+    input:
+      bytes: [ 0x5e, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, #0, #0"
+  -
+    input:
+      bytes: [ 0x5f, 0x00, 0x00, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d0, d0, #0"
+  -
+    input:
+      bytes: [ 0xdf, 0x00, 0x00, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d0, #0, #0"
+  -
+    input:
+      bytes: [ 0x7d, 0x00, 0x00, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne.a a0, a0, #0"
+  -
+    input:
+      bytes: [ 0x1f, 0x00, 0x00, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "jned d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x9f, 0x00, 0x00, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "jned d0, #0, #0"
+  -
+    input:
+      bytes: [ 0x1f, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnei d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x9f, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnei d0, #0, #0"
+  -
+    input:
+      bytes: [ 0xee, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz d15, #0"
+  -
+    input:
+      bytes: [ 0xf6, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz d0, #0"
+  -
+    input:
+      bytes: [ 0x7c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz.a a0, #0"
+  -
+    input:
+      bytes: [ 0xbd, 0x00, 0x00, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz.a a0, #0"
+  -
+    input:
+      bytes: [ 0xae, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz.t d15, #0, #0"
+  -
+    input:
+      bytes: [ 0x6f, 0x00, 0x00, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz.t d0, #0, #0"
+  -
+    input:
+      bytes: [ 0x6e, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d15, #0"
+  -
+    input:
+      bytes: [ 0x76, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d0, #0"
+  -
+    input:
+      bytes: [ 0xbc, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.a a0, #0"
+  -
+    input:
+      bytes: [ 0xbd, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.a a0, #0"
+  -
+    input:
+      bytes: [ 0x2e, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.t d15, #0, #0"
+  -
+    input:
+      bytes: [ 0x6f, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.t d0, #0, #0"
+  -
+    input:
+      bytes: [ 0xd8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.a a15, [sp]#0"
+  -
+    input:
+      bytes: [ 0xc8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.a a0, [a15]#0"
+  -
+    input:
+      bytes: [ 0xcc, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.a a15, [a0]#0"
+  -
+    input:
+      bytes: [ 0xc4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.a a0, [a0+]"
+  -
+    input:
+      bytes: [ 0xd4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.a a0, [a0]"
+  -
+    input:
+      bytes: [ 0x99, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.a a0, [a0]#0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x80, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.a a0, [a0+]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0x80, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.a a0, [p0+r]"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x80, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.a a0, [+a0]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0x80, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.a a0, [p0+c]#0"
+  -
+    input:
+      bytes: [ 0x85, 0x00, 0x00, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.a a0, #0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x80, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.a a0, [a0]#0"
+  -
+    input:
+      bytes: [ 0x05, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.b d0, #0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.b d0, [a0+]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.b d0, [p0+r]"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.b d0, [+a0]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.b d0, [p0+c]#0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x00, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.b d0, [a0]#0"
+  -
+    input:
+      bytes: [ 0x14, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d0, [a0]"
+  -
+    input:
+      bytes: [ 0x0c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d15, [a0]#0"
+  -
+    input:
+      bytes: [ 0x08, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d0, [a15]#0"
+  -
+    input:
+      bytes: [ 0x04, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d0, [a0+]"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d0, [a0+]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d0, [p0+r]"
+  -
+    input:
+      bytes: [ 0x05, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d0, #0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x40, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d0, [+a0]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0x40, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d0, [p0+c]#0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x40, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d0, [a0]#0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x40, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.d e0, [a0+]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0x40, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.d e0, [p0+r]"
+  -
+    input:
+      bytes: [ 0x85, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.d e0, #0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x40, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.d e0, [+a0]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0x40, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.d e0, [p0+c]#0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x40, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.d e0, [a0]#0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0xc0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.da p0, [a0+]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0xc0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.da p0, [p0+r]"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0xc0, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.da p0, [+a0]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0xc0, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.da p0, [p0+c]#0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0xc0, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.da p0, [a0]#0"
+  -
+    input:
+      bytes: [ 0x85, 0x00, 0x00, 0x0c ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.da p0, #0"
+  -
+    input:
+      bytes: [ 0x84, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.h d0, [a0+]"
+  -
+    input:
+      bytes: [ 0x8c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.h d15, [a0]#0"
+  -
+    input:
+      bytes: [ 0x88, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.h d0, [a15]#0"
+  -
+    input:
+      bytes: [ 0x94, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.h d0, [a0]"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.h d0, [a0+]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.h d0, [p0+r]"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x80, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.h d0, [+a0]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0x80, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.h d0, [p0+c]#0"
+  -
+    input:
+      bytes: [ 0x05, 0x00, 0x00, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.h d0, #0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x80, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.h d0, [a0]#0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0xc0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.hu d0, [a0+]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0xc0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.hu d0, [p0+r]"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0xc0, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.hu d0, [+a0]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0xc0, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.hu d0, [p0+c]#0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0xc0, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.hu d0, [a0]#0"
+  -
+    input:
+      bytes: [ 0x05, 0x00, 0x00, 0x0c ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.hu d0, #0"
+  -
+    input:
+      bytes: [ 0x45, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.q d0, #0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x00, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.q d0, [a0+]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0x00, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.q d0, [p0+r]"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x00, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.q d0, [+a0]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0x00, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.q d0, [p0+c]#0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x00, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.q d0, [a0]#0"
+  -
+    input:
+      bytes: [ 0x58, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d15, [sp]#0"
+  -
+    input:
+      bytes: [ 0x54, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d0, [a0]"
+  -
+    input:
+      bytes: [ 0x44, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d0, [a0+]"
+  -
+    input:
+      bytes: [ 0x4c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d15, [a0]#0"
+  -
+    input:
+      bytes: [ 0x48, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d0, [a15]#0"
+  -
+    input:
+      bytes: [ 0x19, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d0, [a0]#0"
+  -
+    input:
+      bytes: [ 0x85, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d0, #0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x00, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d0, [a0+]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0x00, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d0, [p0+r]"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x00, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d0, [+a0]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0x00, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d0, [p0+c]#0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x00, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d0, [a0]#0"
+  -
+    input:
+      bytes: [ 0x15, 0x00, 0x00, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldlcx #0"
+  -
+    input:
+      bytes: [ 0x49, 0x00, 0x00, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldlcx [a0]#0"
+  -
+    input:
+      bytes: [ 0x49, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldmst [a0+]#0, e0"
+  -
+    input:
+      bytes: [ 0x69, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldmst [p0+r], e0"
+  -
+    input:
+      bytes: [ 0xe5, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldmst #0, e0"
+  -
+    input:
+      bytes: [ 0x49, 0x00, 0x40, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldmst [+a0]#0, e0"
+  -
+    input:
+      bytes: [ 0x69, 0x00, 0x40, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldmst [p0+c]#0, e0"
+  -
+    input:
+      bytes: [ 0x49, 0x00, 0x40, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldmst [a0]#0, e0"
+  -
+    input:
+      bytes: [ 0x49, 0x00, 0x40, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "lducx [a0]#0"
+  -
+    input:
+      bytes: [ 0x15, 0x00, 0x00, 0x0c ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "lducx #0"
+  -
+    input:
+      bytes: [ 0xc5, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a0, #0"
+  -
+    input:
+      bytes: [ 0xd9, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a0, [a0]#0"
+  -
+    input:
+      bytes: [ 0x49, 0x00, 0x00, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a0, [a0]#0"
+  -
+    input:
+      bytes: [ 0xfc, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "loop a0, #0xffffffe0"
+  -
+    input:
+      bytes: [ 0xfd, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "loop a0, #0"
+  -
+    input:
+      bytes: [ 0xfd, 0x00, 0x00, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "loopu #0"
+  -
+    input:
+      bytes: [ 0x7a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "lt d15, d0, d0"
+  -
+    input:
+      bytes: [ 0xfa, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "lt d15, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x20, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "lt d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x40, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "lt d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0x20, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "lt.a d0, a0, a0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x20, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "lt.b d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x30, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "lt.bu d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x20, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "lt.h d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x30, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "lt.hu d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x30, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "lt.u d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x60, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "lt.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x20, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "lt.w d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x30, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "lt.wu d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x03, 0x00, 0x0a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd d0, d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x13, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x13, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd e0, e0, d0, #0"
+  -
+    input:
+      bytes: [ 0x03, 0x00, 0x6a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd e0, e0, d0, d0"
+  -
+    input:
+      bytes: [ 0x6b, 0x00, 0x61, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd.f d0, d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd.h e0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0x64, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd.h e0, e0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0x68, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd.h e0, e0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0x6c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd.h e0, e0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x10, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd.q d0, d0, d0u, d0u, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd.q d0, d0, d0, d0u, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x04, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd.q d0, d0, d0, d0l, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x08, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd.q d0, d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x14, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd.q d0, d0, d0l, d0l, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd.q e0, e0, d0, d0u, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x64, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd.q e0, e0, d0, d0l, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x6c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd.q e0, e0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x70, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd.q e0, e0, d0u, d0u, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x74, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd.q e0, e0, d0l, d0l, #0"
+  -
+    input:
+      bytes: [ 0x13, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd.u e0, e0, d0, #0"
+  -
+    input:
+      bytes: [ 0x03, 0x00, 0x68, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd.u e0, e0, d0, d0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0x70, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddm.h e0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0x74, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddm.h e0, e0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0x78, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddm.h e0, e0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0x7c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddm.h e0, e0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0xf0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddms.h e0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0xf4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddms.h e0, e0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0xf8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddms.h e0, e0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0xfc, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddms.h e0, e0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x78, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddr.h d0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0x30, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddr.h d0, d0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0x34, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddr.h d0, d0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0x38, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddr.h d0, d0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0x3c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddr.h d0, d0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x18, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddr.q d0, d0, d0u, d0u, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x1c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddr.q d0, d0, d0l, d0l, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0xf8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddrs.h d0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0xb0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddrs.h d0, d0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0xb4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddrs.h d0, d0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0xb8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddrs.h d0, d0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0xbc, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddrs.h d0, d0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x98, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddrs.q d0, d0, d0u, d0u, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x9c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddrs.q d0, d0, d0l, d0l, #0"
+  -
+    input:
+      bytes: [ 0x03, 0x00, 0x8a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds d0, d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x13, 0x00, 0xa0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x13, 0x00, 0xe0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds e0, e0, d0, #0"
+  -
+    input:
+      bytes: [ 0x03, 0x00, 0xea, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds e0, e0, d0, d0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0xe0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds.h e0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0xe4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds.h e0, e0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0xe8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds.h e0, e0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0xec, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds.h e0, e0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x90, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds.q d0, d0, d0u, d0u, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds.q d0, d0, d0, d0u, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x84, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds.q d0, d0, d0, d0l, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x88, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds.q d0, d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x94, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds.q d0, d0, d0l, d0l, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0xe0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds.q e0, e0, d0, d0u, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0xe4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds.q e0, e0, d0, d0l, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0xec, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds.q e0, e0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0xf0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds.q e0, e0, d0u, d0u, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0xf4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds.q e0, e0, d0l, d0l, #0"
+  -
+    input:
+      bytes: [ 0x13, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds.u d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x03, 0x00, 0x88, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds.u d0, d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x13, 0x00, 0xc0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds.u e0, e0, d0, #0"
+  -
+    input:
+      bytes: [ 0x03, 0x00, 0xe8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds.u e0, e0, d0, d0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsu.h e0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0x64, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsu.h e0, e0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0x68, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsu.h e0, e0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0x6c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsu.h e0, e0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0x70, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsum.h e0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0x74, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsum.h e0, e0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0x78, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsum.h e0, e0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0x7c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsum.h e0, e0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0xf0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsums.h e0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0xf4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsums.h e0, e0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0xf8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsums.h e0, e0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0xfc, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsums.h e0, e0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0x30, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsur.h d0, d0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0x34, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsur.h d0, d0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0x38, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsur.h d0, d0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0x3c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsur.h d0, d0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0xb0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsurs.h d0, d0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0xb4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsurs.h d0, d0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0xb8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsurs.h d0, d0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0xbc, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsurs.h d0, d0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0xe0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsus.h e0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0xe4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsus.h e0, e0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0xe8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsus.h e0, e0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0xec, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsus.h e0, e0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xa0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "max d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x40, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "max d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xa0, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "max.b d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xb0, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "max.bu d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xa0, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "max.h d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xb0, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "max.hu d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xb0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "max.u d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x60, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "max.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x4d, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "mfcr d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x80, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "min d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x00, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "min d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x80, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "min.b d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x90, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "min.bu d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x80, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "min.h d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x90, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "min.hu d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x90, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "min.u d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x20, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "min.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x02, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d0, d0"
+  -
+    input:
+      bytes: [ 0x82, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d0, #0"
+  -
+    input:
+      bytes: [ 0xda, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d15, #0"
+  -
+    input:
+      bytes: [ 0x3b, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xf0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d0, d0"
+  -
+    input:
+      bytes: [ 0xa0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.a a0, #0"
+  -
+    input:
+      bytes: [ 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.a a0, d0"
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0x30, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.a a0, d0"
+  -
+    input:
+      bytes: [ 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.aa a0, a0"
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.aa a0, a0"
+  -
+    input:
+      bytes: [ 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.d d0, a0"
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0xc0, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.d d0, a0"
+  -
+    input:
+      bytes: [ 0xbb, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.u d0, #0"
+  -
+    input:
+      bytes: [ 0x7b, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh d0, #0"
+  -
+    input:
+      bytes: [ 0x91, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a0, #0"
+  -
+    input:
+      bytes: [ 0x23, 0x00, 0x0a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub d0, d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x33, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x33, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub e0, e0, d0, #0"
+  -
+    input:
+      bytes: [ 0x23, 0x00, 0x6a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub e0, e0, d0, d0"
+  -
+    input:
+      bytes: [ 0x6b, 0x00, 0x71, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub.f d0, d0, d0, d0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub.h e0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0x64, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub.h e0, e0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0x68, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub.h e0, e0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0x6c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub.h e0, e0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x10, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub.q d0, d0, d0u, d0u, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub.q d0, d0, d0, d0u, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x04, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub.q d0, d0, d0, d0l, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x08, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub.q d0, d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x14, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub.q d0, d0, d0l, d0l, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub.q e0, e0, d0, d0u, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x64, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub.q e0, e0, d0, d0l, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x6c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub.q e0, e0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x70, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub.q e0, e0, d0u, d0u, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x74, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub.q e0, e0, d0l, d0l, #0"
+  -
+    input:
+      bytes: [ 0x33, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub.u e0, e0, d0, #0"
+  -
+    input:
+      bytes: [ 0x23, 0x00, 0x68, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub.u e0, e0, d0, d0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubad.h e0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x64, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubad.h e0, e0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x68, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubad.h e0, e0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x6c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubad.h e0, e0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x70, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubadm.h e0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x74, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubadm.h e0, e0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x78, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubadm.h e0, e0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x7c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubadm.h e0, e0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xf0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubadms.h e0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xf4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubadms.h e0, e0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xf8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubadms.h e0, e0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xfc, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubadms.h e0, e0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x30, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubadr.h d0, d0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x34, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubadr.h d0, d0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x38, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubadr.h d0, d0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x3c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubadr.h d0, d0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xb0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubadrs.h d0, d0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xb4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubadrs.h d0, d0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xb8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubadrs.h d0, d0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xbc, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubadrs.h d0, d0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xe0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubads.h e0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xe4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubads.h e0, e0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xe8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubads.h e0, e0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xec, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubads.h e0, e0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0x70, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubm.h e0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0x74, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubm.h e0, e0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0x78, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubm.h e0, e0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0x7c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubm.h e0, e0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0xf0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubms.h e0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0xf4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubms.h e0, e0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0xf8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubms.h e0, e0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0xfc, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubms.h e0, e0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x78, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubr.h d0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0x30, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubr.h d0, d0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0x34, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubr.h d0, d0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0x38, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubr.h d0, d0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0x3c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubr.h d0, d0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x18, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubr.q d0, d0, d0u, d0u, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x1c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubr.q d0, d0, d0l, d0l, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0xf8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubrs.h d0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0xb0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubrs.h d0, d0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0xb4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubrs.h d0, d0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0xb8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubrs.h d0, d0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0xbc, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubrs.h d0, d0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x98, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubrs.q d0, d0, d0u, d0u, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x9c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubrs.q d0, d0, d0l, d0l, #0"
+  -
+    input:
+      bytes: [ 0x23, 0x00, 0x8a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs d0, d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x33, 0x00, 0xa0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x33, 0x00, 0xe0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs e0, e0, d0, #0"
+  -
+    input:
+      bytes: [ 0x23, 0x00, 0xea, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs e0, e0, d0, d0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0xe0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs.h e0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0xe4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs.h e0, e0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0xe8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs.h e0, e0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0xec, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs.h e0, e0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x90, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs.q d0, d0, d0u, d0u, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs.q d0, d0, d0, d0u, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x84, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs.q d0, d0, d0, d0l, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x88, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs.q d0, d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x94, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs.q d0, d0, d0l, d0l, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0xe0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs.q e0, e0, d0, d0u, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0xe4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs.q e0, e0, d0, d0l, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0xec, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs.q e0, e0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0xf0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs.q e0, e0, d0u, d0u, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0xf4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs.q e0, e0, d0l, d0l, #0"
+  -
+    input:
+      bytes: [ 0x33, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs.u d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x23, 0x00, 0x88, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs.u d0, d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x33, 0x00, 0xc0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs.u e0, e0, d0, #0"
+  -
+    input:
+      bytes: [ 0x23, 0x00, 0xe8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs.u e0, e0, d0, d0"
+  -
+    input:
+      bytes: [ 0xcd, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "mtcr #0, d0"
+  -
+    input:
+      bytes: [ 0xe2, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul d0, d0"
+  -
+    input:
+      bytes: [ 0x53, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x73, 0x00, 0x0a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x53, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul e0, d0, #0"
+  -
+    input:
+      bytes: [ 0x73, 0x00, 0x6a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul e0, d0, d0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0x41, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.f d0, d0, d0"
+  -
+    input:
+      bytes: [ 0xb3, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.h e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xb3, 0x00, 0x64, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.h e0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xb3, 0x00, 0x68, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.h e0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xb3, 0x00, 0x6c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.h e0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0x93, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.q d0, d0, d0u, #0"
+  -
+    input:
+      bytes: [ 0x93, 0x00, 0x04, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.q d0, d0, d0l, #0"
+  -
+    input:
+      bytes: [ 0x93, 0x00, 0x08, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.q d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x93, 0x00, 0x10, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.q d0, d0u, d0u, #0"
+  -
+    input:
+      bytes: [ 0x93, 0x00, 0x14, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.q d0, d0l, d0l, #0"
+  -
+    input:
+      bytes: [ 0x93, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.q e0, d0, d0u, #0"
+  -
+    input:
+      bytes: [ 0x93, 0x00, 0x64, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.q e0, d0, d0l, #0"
+  -
+    input:
+      bytes: [ 0x93, 0x00, 0x6c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.q e0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x53, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.u e0, d0, #0"
+  -
+    input:
+      bytes: [ 0x73, 0x00, 0x68, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.u e0, d0, d0"
+  -
+    input:
+      bytes: [ 0xb3, 0x00, 0x70, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulm.h e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xb3, 0x00, 0x74, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulm.h e0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xb3, 0x00, 0x78, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulm.h e0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xb3, 0x00, 0x7c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulm.h e0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0xb3, 0x00, 0xf0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulms.h e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xb3, 0x00, 0xf4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulms.h e0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xb3, 0x00, 0xf8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulms.h e0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xb3, 0x00, 0xfc, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulms.h e0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0xb3, 0x00, 0x30, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulr.h d0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xb3, 0x00, 0x34, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulr.h d0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xb3, 0x00, 0x38, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulr.h d0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xb3, 0x00, 0x3c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulr.h d0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0x93, 0x00, 0x18, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulr.q d0, d0u, d0u, #0"
+  -
+    input:
+      bytes: [ 0x93, 0x00, 0x1c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulr.q d0, d0l, d0l, #0"
+  -
+    input:
+      bytes: [ 0x53, 0x00, 0xa0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "muls d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x73, 0x00, 0x8a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "muls d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x53, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "muls.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x73, 0x00, 0x88, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "muls.u d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0x90, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "nand d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8f, 0x00, 0x20, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "nand d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x07, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "nand.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x10, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "ne d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x20, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "ne d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0x10, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "ne.a d0, a0, a0"
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0x90, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "nez.a d0, a0"
+  -
+    input:
+      bytes: [ 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "nop"
+  -
+    input:
+      bytes: [ 0x0d, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "nop"
+  -
+    input:
+      bytes: [ 0x46, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "nor d0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0xb0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "nor d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8f, 0x00, 0x60, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "nor d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x87, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "nor.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0xa6, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "or d0, d0"
+  -
+    input:
+      bytes: [ 0x96, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "or d15, #0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0xa0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "or d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8f, 0x00, 0x40, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "or d0, d0, #0"
+  -
+    input:
+      bytes: [ 0xc7, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.and.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0xc7, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.andn.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x70, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.eq d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0xe0, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.eq d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xb0, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.ge d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x60, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.ge d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xc0, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.ge.u d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x80, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.ge.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x90, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.lt d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x20, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.lt d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xa0, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.lt.u d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x40, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.lt.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x80, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.ne d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x00, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.ne d0, d0, #0"
+  -
+    input:
+      bytes: [ 0xc7, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.nor.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0xc7, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.or.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x87, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0xf0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "orn d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8f, 0x00, 0xe0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "orn d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x07, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "orn.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x6b, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "pack d0, e0, d0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "parity d0, d0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0x51, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "q31tof d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0x91, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "qseed.f d0, d0"
+  -
+    input:
+      bytes: [ 0x00, 0x90 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "ret"
+  -
+    input:
+      bytes: [ 0x0d, 0x00, 0x80, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "ret"
+  -
+    input:
+      bytes: [ 0x00, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "rfe"
+  -
+    input:
+      bytes: [ 0x0d, 0x00, 0xc0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "rfe"
+  -
+    input:
+      bytes: [ 0x0d, 0x00, 0x40, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "rfm"
+  -
+    input:
+      bytes: [ 0x0d, 0x00, 0x40, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "rslcx"
+  -
+    input:
+      bytes: [ 0x2f, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "rstv"
+  -
+    input:
+      bytes: [ 0x32, 0x50 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "rsub d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x00, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "rsub d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x40, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "rsubs d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x60, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "rsubs.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x32, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "sat.b d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xe0, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "sat.b d0, d0"
+  -
+    input:
+      bytes: [ 0x32, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "sat.bu d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xf0, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "sat.bu d0, d0"
+  -
+    input:
+      bytes: [ 0x32, 0x20 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "sat.h d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xe0, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "sat.h d0, d0"
+  -
+    input:
+      bytes: [ 0x32, 0x30 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "sat.hu d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xf0, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "sat.hu d0, d0"
+  -
+    input:
+      bytes: [ 0x2b, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "sel d0, d0, d0, d0"
+  -
+    input:
+      bytes: [ 0xab, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "sel d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x2b, 0x00, 0x50, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "seln d0, d0, d0, d0"
+  -
+    input:
+      bytes: [ 0xab, 0x00, 0xa0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "seln d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x06, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh d0, #0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8f, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x27, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.and.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x27, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.andn.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x70, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.eq d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0xe0, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.eq d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xb0, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.ge d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x60, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.ge d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xc0, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.ge.u d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x80, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.ge.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.h d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8f, 0x00, 0x00, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.h d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x90, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.lt d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x20, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.lt d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xa0, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.lt.u d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x40, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.lt.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0xa7, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.nand.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x80, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.ne d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x00, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.ne d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x27, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.nor.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x27, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.or.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0xa7, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.orn.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0xa7, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.xnor.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0xa7, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.xor.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x86, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha d0, #0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0x10, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8f, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0x10, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha.h d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8f, 0x00, 0x20, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha.h d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "shas d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8f, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "shas d0, d0, #0"
+  -
+    input:
+      bytes: [ 0xf8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.a [sp]#0, a15"
+  -
+    input:
+      bytes: [ 0xec, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.a [a0]#0, a15"
+  -
+    input:
+      bytes: [ 0xe8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.a [a15]#0, a0"
+  -
+    input:
+      bytes: [ 0xe4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.a [a0+], a0"
+  -
+    input:
+      bytes: [ 0xf4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.a [a0], a0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x80, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.a [a0+]#0, a0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x80, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.a [p0+r], a0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x80, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.a [+a0]#0, a0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x80, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.a [p0+c]#0, a0"
+  -
+    input:
+      bytes: [ 0xa5, 0x00, 0x00, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.a #0, a0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x80, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.a [a0]#0, a0"
+  -
+    input:
+      bytes: [ 0x34, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [a0], d0"
+  -
+    input:
+      bytes: [ 0x28, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [a15]#0, d0"
+  -
+    input:
+      bytes: [ 0x2c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [a0]#0, d15"
+  -
+    input:
+      bytes: [ 0x24, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [a0+], d0"
+  -
+    input:
+      bytes: [ 0x25, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b #0, d0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [a0+]#0, d0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [p0+r], d0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [+a0]#0, d0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [p0+c]#0, d0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x00, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [a0]#0, d0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x40, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.d [a0+]#0, e0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x40, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.d [p0+r], e0"
+  -
+    input:
+      bytes: [ 0xa5, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.d #0, e0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x40, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.d [+a0]#0, e0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x40, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.d [p0+c]#0, e0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x40, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.d [a0]#0, e0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0xc0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.da [a0+]#0, p0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0xc0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.da [p0+r], p0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0xc0, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.da [+a0]#0, p0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0xc0, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.da [p0+c]#0, p0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0xc0, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.da [a0]#0, p0"
+  -
+    input:
+      bytes: [ 0xa5, 0x00, 0x00, 0x0c ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.da #0, p0"
+  -
+    input:
+      bytes: [ 0xa4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [a0+], d0"
+  -
+    input:
+      bytes: [ 0xa8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [a15]#0, d0"
+  -
+    input:
+      bytes: [ 0xac, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [a0]#0, d15"
+  -
+    input:
+      bytes: [ 0xb4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [a0], d0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [a0+]#0, d0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [p0+r], d0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x80, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [+a0]#0, d0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x80, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [p0+c]#0, d0"
+  -
+    input:
+      bytes: [ 0x25, 0x00, 0x00, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h #0, d0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x80, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [a0]#0, d0"
+  -
+    input:
+      bytes: [ 0x65, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.q #0, d0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x00, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.q [a0+]#0, d0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x00, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.q [p0+r], d0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x00, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.q [+a0]#0, d0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x00, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.q [p0+c]#0, d0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x00, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.q [a0]#0, d0"
+  -
+    input:
+      bytes: [ 0xd5, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.t #0, #0, #0"
+  -
+    input:
+      bytes: [ 0x78, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w [sp]#0, d15"
+  -
+    input:
+      bytes: [ 0x74, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w [a0], d0"
+  -
+    input:
+      bytes: [ 0x64, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w [a0+], d0"
+  -
+    input:
+      bytes: [ 0x68, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w [a15]#0, d0"
+  -
+    input:
+      bytes: [ 0x6c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w [a0]#0, d15"
+  -
+    input:
+      bytes: [ 0x59, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w [a0]#0, d0"
+  -
+    input:
+      bytes: [ 0xa5, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w #0, d0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x00, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w [a0+]#0, d0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x00, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w [p0+r], d0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x00, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w [+a0]#0, d0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x00, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w [p0+c]#0, d0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x00, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w [a0]#0, d0"
+  -
+    input:
+      bytes: [ 0x15, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "stlcx #0"
+  -
+    input:
+      bytes: [ 0x49, 0x00, 0x80, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "stlcx [a0]#0"
+  -
+    input:
+      bytes: [ 0x15, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "stucx #0"
+  -
+    input:
+      bytes: [ 0x49, 0x00, 0xc0, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "stucx [a0]#0"
+  -
+    input:
+      bytes: [ 0x52, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub d0, d15, d0"
+  -
+    input:
+      bytes: [ 0x5a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub d15, d0, d0"
+  -
+    input:
+      bytes: [ 0xa2, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub.a sp, #0"
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub.a a0, a0, a0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x80, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub.b d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x6b, 0x00, 0x31, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub.f d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x80, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub.h d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xd0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "subc d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x62, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "subs d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xa0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "subs d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xa0, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "subs.h d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xb0, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "subs.hu d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xb0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "subs.u d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xc0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "subx d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0d, 0x00, 0x00, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "svlcx"
+  -
+    input:
+      bytes: [ 0x49, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "swap.w [a0+]#0, d0"
+  -
+    input:
+      bytes: [ 0x69, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "swap.w [p0+r], d0"
+  -
+    input:
+      bytes: [ 0xe5, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "swap.w #0, d0"
+  -
+    input:
+      bytes: [ 0x49, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "swap.w [+a0]#0, d0"
+  -
+    input:
+      bytes: [ 0x69, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "swap.w [p0+c]#0, d0"
+  -
+    input:
+      bytes: [ 0x49, 0x00, 0x00, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "swap.w [a0]#0, d0"
+  -
+    input:
+      bytes: [ 0xad, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "syscall #0"
+  -
+    input:
+      bytes: [ 0x75, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "tlbdemap d0"
+  -
+    input:
+      bytes: [ 0x75, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "tlbflush.a"
+  -
+    input:
+      bytes: [ 0x75, 0x00, 0x50, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "tlbflush.b"
+  -
+    input:
+      bytes: [ 0x75, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "tlbmap e0"
+  -
+    input:
+      bytes: [ 0x75, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "tlbprobe.a d0"
+  -
+    input:
+      bytes: [ 0x75, 0x00, 0x90, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "tlbprobe.i d0"
+  -
+    input:
+      bytes: [ 0x0d, 0x00, 0x40, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "trapsv"
+  -
+    input:
+      bytes: [ 0x0d, 0x00, 0x00, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "trapv"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "unpack e0, d0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0xc1, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "updfl d0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0x61, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "utof d0, d0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0xd0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "xnor d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8f, 0x00, 0xa0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "xnor d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x07, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "xnor.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0xc6, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor d0, d0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0xc0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8f, 0x00, 0x80, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xf0, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor.eq d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0xe0, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor.eq d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x30, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor.ge d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x60, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor.ge d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x40, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor.ge.u d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x80, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor.ge.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x10, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor.lt d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x20, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor.lt d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x20, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor.lt.u d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x40, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor.lt.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x00, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor.ne d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x00, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor.ne d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x07, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_131" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor.t d0, d0, #0, d0, #0"
diff --git a/tests/MC/TriCore/tc160.s.yaml b/tests/MC/TriCore/tc160.s.yaml
new file mode 100644
index 000000000..9f77d604a
--- /dev/null
+++ b/tests/MC/TriCore/tc160.s.yaml
@@ -0,0 +1,7399 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xc0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "abs d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xc0, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "abs.b d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xc0, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "abs.h d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xe0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "absdif d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0xc0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "absdif d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xe0, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "absdif.b d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xe0, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "absdif.h d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xf0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "absdifs d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0xe0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "absdifs d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xf0, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "absdifs.h d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xd0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "abss d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xd0, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "abss.h d0, d0"
+  -
+    input:
+      bytes: [ 0x12, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d0, d15, d0"
+  -
+    input:
+      bytes: [ 0x92, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d0, d15, #0"
+  -
+    input:
+      bytes: [ 0x1a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d15, d0, d0"
+  -
+    input:
+      bytes: [ 0x42, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d0, d0"
+  -
+    input:
+      bytes: [ 0x9a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d15, d0, #0"
+  -
+    input:
+      bytes: [ 0xc2, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x30, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "add.a a0, a0"
+  -
+    input:
+      bytes: [ 0xb0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "add.a a0, #0"
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0x10, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "add.a a0, a0, a0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "add.b d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x6b, 0x00, 0x21, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "add.f d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x00, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "add.h d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x50, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "addc d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0xa0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "addc d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x1b, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "addi d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x9b, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "addih d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x11, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "addih.a a0, a0, #0"
+  -
+    input:
+      bytes: [ 0x22, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "adds d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "adds d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "adds d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x20, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "adds.h d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x30, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "adds.hu d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x30, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "adds.u d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "adds.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x10, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "addsc.a a0, a0, d15, #0"
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0x00, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "addsc.a a0, a0, d0, #0"
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0x20, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "addsc.at a0, a0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "addx d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "addx d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x26, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d0, d0"
+  -
+    input:
+      bytes: [ 0x16, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d15, #0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8f, 0x00, 0x00, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x47, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.and.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x47, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.andn.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x00, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.eq d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.eq d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x40, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.ge d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x80, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.ge d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x50, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.ge.u d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0xa0, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.ge.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x20, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.lt d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x40, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.lt d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x30, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.lt.u d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x60, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.lt.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x10, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.ne d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x20, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.ne d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x47, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.nor.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x47, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.or.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x87, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0xe0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "andn d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8f, 0x00, 0xc0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "andn d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x87, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "andn.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0xe0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "bisr #0"
+  -
+    input:
+      bytes: [ 0xad, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "bisr #0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0x10, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "bmerge d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0x90, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "bsplit e0, d0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x80, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachea.i [a0+]#0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x80, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachea.i [p0+r]"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x80, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachea.i [+a0]#0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x80, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachea.i [p0+c]#0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x80, 0x0b ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachea.i [a0]#0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x00, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachea.w [a0+]#0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x00, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachea.w [p0+r]"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x00, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachea.w [+a0]#0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x00, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachea.w [p0+c]#0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x00, 0x0b ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachea.w [a0]#0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x40, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachea.wi [a0+]#0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x40, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachea.wi [p0+r]"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x40, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachea.wi [+a0]#0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x40, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachea.wi [p0+c]#0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x40, 0x0b ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachea.wi [a0]#0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x80, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachei.i [a0+]#0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x80, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachei.i [+a0]#0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x80, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachei.i [a0]#0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0xc0, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachei.w [a0+]#0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0xc0, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachei.w [+a0]#0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0xc0, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachei.w [a0]#0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0xc0, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachei.wi [a0+]#0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0xc0, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachei.wi [+a0]#0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0xc0, 0x0b ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachei.wi [a0]#0"
+  -
+    input:
+      bytes: [ 0x8a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "cadd d0, d15, #0"
+  -
+    input:
+      bytes: [ 0x2b, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "cadd d0, d0, d0, d0"
+  -
+    input:
+      bytes: [ 0xab, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "cadd d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0xca, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "caddn d0, d15, #0"
+  -
+    input:
+      bytes: [ 0x2b, 0x00, 0x10, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "caddn d0, d0, d0, d0"
+  -
+    input:
+      bytes: [ 0xab, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "caddn d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x5c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0"
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "calla #0"
+  -
+    input:
+      bytes: [ 0x2d, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "calli a0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0xc0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "clo d0, d0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0xd0, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "clo.h d0, d0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0xd0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "cls d0, d0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0xe0, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "cls.h d0, d0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0xb0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "clz d0, d0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0xc0, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "clz.h d0, d0"
+  -
+    input:
+      bytes: [ 0x2a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmov d0, d15, d0"
+  -
+    input:
+      bytes: [ 0xaa, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmov d0, d15, #0"
+  -
+    input:
+      bytes: [ 0x6a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmovn d0, d15, d0"
+  -
+    input:
+      bytes: [ 0xea, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmovn d0, d15, #0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmp.f d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x2b, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "csub d0, d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x2b, 0x00, 0x30, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "csubn d0, d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x00, 0xa0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "debug"
+  -
+    input:
+      bytes: [ 0x0d, 0x00, 0x00, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "debug"
+  -
+    input:
+      bytes: [ 0x77, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "dextr d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x17, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "dextr d0, d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0d, 0x00, 0x40, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "disable"
+  -
+    input:
+      bytes: [ 0x0d, 0x00, 0xc0, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "disable d0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0x01, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "div e0, d0, d0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0x11, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "div.u e0, d0, d0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0x51, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "div.f d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0d, 0x00, 0x80, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "dsync"
+  -
+    input:
+      bytes: [ 0x6b, 0x00, 0xd0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "dvadj e0, e0, d0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0xa0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "dvinit e0, d0, d0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0xa0, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "dvinit.b e0, d0, d0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0xa0, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "dvinit.bu e0, d0, d0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0xa0, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "dvinit.h e0, d0, d0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0xa0, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "dvinit.hu e0, d0, d0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0xa0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "dvinit.u e0, d0, d0"
+  -
+    input:
+      bytes: [ 0x6b, 0x00, 0xf0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "dvstep e0, e0, d0"
+  -
+    input:
+      bytes: [ 0x6b, 0x00, 0xe0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "dvstep.u e0, e0, d0"
+  -
+    input:
+      bytes: [ 0x0d, 0x00, 0x00, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "enable"
+  -
+    input:
+      bytes: [ 0x3a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "eq d15, d0, d0"
+  -
+    input:
+      bytes: [ 0xba, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "eq d15, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x00, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "eq d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x00, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "eq d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "eq.a d0, a0, a0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x00, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "eq.b d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x00, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "eq.h d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x00, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "eq.w d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x60, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "eqany.b d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0xc0, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "eqany.b d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x60, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "eqany.h d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0xc0, 0x0e ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "eqany.h d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0x80, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "eqz.a d0, a0"
+  -
+    input:
+      bytes: [ 0x17, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr d0, d0, e0"
+  -
+    input:
+      bytes: [ 0x37, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr d0, d0, #0, #0"
+  -
+    input:
+      bytes: [ 0x57, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x17, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d0, d0, e0"
+  -
+    input:
+      bytes: [ 0x37, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d0, d0, #0, #0"
+  -
+    input:
+      bytes: [ 0x57, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x61, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcall #0"
+  -
+    input:
+      bytes: [ 0xe1, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcalla #0"
+  -
+    input:
+      bytes: [ 0x2d, 0x00, 0x10, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcalli a0"
+  -
+    input:
+      bytes: [ 0x00, 0x70 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "fret"
+  -
+    input:
+      bytes: [ 0x0d, 0x00, 0xc0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "fret"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0x01, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "ftoi d0, d0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0x11, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "ftoq31 d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0x21, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "ftou d0, d0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0x31, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "ftoiz d0, d0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0x81, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "ftoq31z d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0x71, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "ftouz d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x40, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "ge d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x80, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "ge d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0x30, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "ge.a d0, a0, a0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x50, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "ge.u d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0xa0, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "ge.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x37, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "imask e0, d0, #0, #0"
+  -
+    input:
+      bytes: [ 0x57, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "imask e0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0xb7, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "imask e0, #0, #0, #0"
+  -
+    input:
+      bytes: [ 0xd7, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "imask e0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x67, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "ins.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x17, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d0, d0, d0, e0"
+  -
+    input:
+      bytes: [ 0x37, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d0, d0, d0, #0, #0"
+  -
+    input:
+      bytes: [ 0x57, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d0, d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x97, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d0, d0, #0, e0"
+  -
+    input:
+      bytes: [ 0xb7, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d0, d0, #0, #0, #0"
+  -
+    input:
+      bytes: [ 0xd7, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x67, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "insn.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0d, 0x00, 0xc0, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "isync"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0x41, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "itof d0, d0"
+  -
+    input:
+      bytes: [ 0x6b, 0x00, 0xa0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "ixmax e0, e0, d0"
+  -
+    input:
+      bytes: [ 0x6b, 0x00, 0xb0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "ixmax.u e0, e0, d0"
+  -
+    input:
+      bytes: [ 0x6b, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "ixmin e0, e0, d0"
+  -
+    input:
+      bytes: [ 0x6b, 0x00, 0x90, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "ixmin.u e0, e0, d0"
+  -
+    input:
+      bytes: [ 0x3c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0"
+  -
+    input:
+      bytes: [ 0x1d, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0"
+  -
+    input:
+      bytes: [ 0x9d, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "ja #0"
+  -
+    input:
+      bytes: [ 0xbe, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d0, #0x20"
+  -
+    input:
+      bytes: [ 0x9e, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, #0, #0x20"
+  -
+    input:
+      bytes: [ 0x3e, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d0, #0"
+  -
+    input:
+      bytes: [ 0x1e, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, #0, #0"
+  -
+    input:
+      bytes: [ 0x5f, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d0, d0, #0"
+  -
+    input:
+      bytes: [ 0xdf, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d0, #0, #0"
+  -
+    input:
+      bytes: [ 0x7d, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq.a a0, a0, #0"
+  -
+    input:
+      bytes: [ 0x7f, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "jge d0, d0, #0"
+  -
+    input:
+      bytes: [ 0xff, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "jge d0, #0, #0"
+  -
+    input:
+      bytes: [ 0x7f, 0x00, 0x00, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "jge.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0xff, 0x00, 0x00, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "jge.u d0, #0, #0"
+  -
+    input:
+      bytes: [ 0xce, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "jgez d0, #0"
+  -
+    input:
+      bytes: [ 0x4e, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "jgtz d0, #0"
+  -
+    input:
+      bytes: [ 0xdc, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "ji a0"
+  -
+    input:
+      bytes: [ 0x2d, 0x00, 0x30, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "ji a0"
+  -
+    input:
+      bytes: [ 0x5d, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "jl #0"
+  -
+    input:
+      bytes: [ 0xdd, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "jla #0"
+  -
+    input:
+      bytes: [ 0x8e, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlez d0, #0"
+  -
+    input:
+      bytes: [ 0x2d, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "jli a0"
+  -
+    input:
+      bytes: [ 0x3f, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt d0, d0, #0"
+  -
+    input:
+      bytes: [ 0xbf, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt d0, #0, #0"
+  -
+    input:
+      bytes: [ 0x3f, 0x00, 0x00, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0xbf, 0x00, 0x00, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt.u d0, #0, #0"
+  -
+    input:
+      bytes: [ 0x0e, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "jltz d0, #0"
+  -
+    input:
+      bytes: [ 0xfe, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, d0, #0x20"
+  -
+    input:
+      bytes: [ 0xde, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, #0, #0x20"
+  -
+    input:
+      bytes: [ 0x7e, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, d0, #0"
+  -
+    input:
+      bytes: [ 0x5e, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, #0, #0"
+  -
+    input:
+      bytes: [ 0x5f, 0x00, 0x00, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d0, d0, #0"
+  -
+    input:
+      bytes: [ 0xdf, 0x00, 0x00, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d0, #0, #0"
+  -
+    input:
+      bytes: [ 0x7d, 0x00, 0x00, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne.a a0, a0, #0"
+  -
+    input:
+      bytes: [ 0x1f, 0x00, 0x00, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "jned d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x9f, 0x00, 0x00, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "jned d0, #0, #0"
+  -
+    input:
+      bytes: [ 0x1f, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnei d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x9f, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnei d0, #0, #0"
+  -
+    input:
+      bytes: [ 0xee, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz d15, #0"
+  -
+    input:
+      bytes: [ 0xf6, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz d0, #0"
+  -
+    input:
+      bytes: [ 0x7c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz.a a0, #0"
+  -
+    input:
+      bytes: [ 0xbd, 0x00, 0x00, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz.a a0, #0"
+  -
+    input:
+      bytes: [ 0xae, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz.t d15, #0, #0"
+  -
+    input:
+      bytes: [ 0x6f, 0x00, 0x00, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz.t d0, #0, #0"
+  -
+    input:
+      bytes: [ 0x6e, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d15, #0"
+  -
+    input:
+      bytes: [ 0x76, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d0, #0"
+  -
+    input:
+      bytes: [ 0xbc, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.a a0, #0"
+  -
+    input:
+      bytes: [ 0xbd, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.a a0, #0"
+  -
+    input:
+      bytes: [ 0x2e, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.t d15, #0, #0"
+  -
+    input:
+      bytes: [ 0x6f, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.t d0, #0, #0"
+  -
+    input:
+      bytes: [ 0xd8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.a a15, [sp]#0"
+  -
+    input:
+      bytes: [ 0xc8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.a a0, [a15]#0"
+  -
+    input:
+      bytes: [ 0xcc, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.a a15, [a0]#0"
+  -
+    input:
+      bytes: [ 0xc4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.a a0, [a0+]"
+  -
+    input:
+      bytes: [ 0xd4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.a a0, [a0]"
+  -
+    input:
+      bytes: [ 0x99, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.a a0, [a0]#0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x80, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.a a0, [a0+]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0x80, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.a a0, [p0+r]"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x80, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.a a0, [+a0]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0x80, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.a a0, [p0+c]#0"
+  -
+    input:
+      bytes: [ 0x85, 0x00, 0x00, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.a a0, #0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x80, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.a a0, [a0]#0"
+  -
+    input:
+      bytes: [ 0x79, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.b d0, [a0]#0"
+  -
+    input:
+      bytes: [ 0x05, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.b d0, #0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.b d0, [a0+]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.b d0, [p0+r]"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.b d0, [+a0]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.b d0, [p0+c]#0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x00, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.b d0, [a0]#0"
+  -
+    input:
+      bytes: [ 0x14, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d0, [a0]"
+  -
+    input:
+      bytes: [ 0x0c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d15, [a0]#0"
+  -
+    input:
+      bytes: [ 0x08, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d0, [a15]#0"
+  -
+    input:
+      bytes: [ 0x04, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d0, [a0+]"
+  -
+    input:
+      bytes: [ 0x39, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d0, [a0]#0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d0, [a0+]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d0, [p0+r]"
+  -
+    input:
+      bytes: [ 0x05, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d0, #0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x40, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d0, [+a0]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0x40, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d0, [p0+c]#0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x40, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d0, [a0]#0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x40, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.d e0, [a0+]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0x40, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.d e0, [p0+r]"
+  -
+    input:
+      bytes: [ 0x85, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.d e0, #0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x40, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.d e0, [+a0]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0x40, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.d e0, [p0+c]#0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x40, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.d e0, [a0]#0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0xc0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.da p0, [a0+]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0xc0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.da p0, [p0+r]"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0xc0, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.da p0, [+a0]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0xc0, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.da p0, [p0+c]#0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0xc0, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.da p0, [a0]#0"
+  -
+    input:
+      bytes: [ 0x85, 0x00, 0x00, 0x0c ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.da p0, #0"
+  -
+    input:
+      bytes: [ 0x84, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.h d0, [a0+]"
+  -
+    input:
+      bytes: [ 0x8c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.h d15, [a0]#0"
+  -
+    input:
+      bytes: [ 0x88, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.h d0, [a15]#0"
+  -
+    input:
+      bytes: [ 0x94, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.h d0, [a0]"
+  -
+    input:
+      bytes: [ 0xc9, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.h d0, [a0]#0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.h d0, [a0+]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.h d0, [p0+r]"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x80, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.h d0, [+a0]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0x80, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.h d0, [p0+c]#0"
+  -
+    input:
+      bytes: [ 0x05, 0x00, 0x00, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.h d0, #0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x80, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.h d0, [a0]#0"
+  -
+    input:
+      bytes: [ 0xb9, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.hu d0, [a0]#0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0xc0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.hu d0, [a0+]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0xc0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.hu d0, [p0+r]"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0xc0, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.hu d0, [+a0]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0xc0, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.hu d0, [p0+c]#0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0xc0, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.hu d0, [a0]#0"
+  -
+    input:
+      bytes: [ 0x05, 0x00, 0x00, 0x0c ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.hu d0, #0"
+  -
+    input:
+      bytes: [ 0x45, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.q d0, #0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x00, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.q d0, [a0+]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0x00, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.q d0, [p0+r]"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x00, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.q d0, [+a0]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0x00, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.q d0, [p0+c]#0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x00, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.q d0, [a0]#0"
+  -
+    input:
+      bytes: [ 0x58, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d15, [sp]#0"
+  -
+    input:
+      bytes: [ 0x54, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d0, [a0]"
+  -
+    input:
+      bytes: [ 0x44, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d0, [a0+]"
+  -
+    input:
+      bytes: [ 0x4c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d15, [a0]#0"
+  -
+    input:
+      bytes: [ 0x48, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d0, [a15]#0"
+  -
+    input:
+      bytes: [ 0x19, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d0, [a0]#0"
+  -
+    input:
+      bytes: [ 0x85, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d0, #0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x00, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d0, [a0+]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0x00, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d0, [p0+r]"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x00, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d0, [+a0]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0x00, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d0, [p0+c]#0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x00, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d0, [a0]#0"
+  -
+    input:
+      bytes: [ 0x15, 0x00, 0x00, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldlcx #0"
+  -
+    input:
+      bytes: [ 0x49, 0x00, 0x00, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldlcx [a0]#0"
+  -
+    input:
+      bytes: [ 0x49, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldmst [a0+]#0, e0"
+  -
+    input:
+      bytes: [ 0x69, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldmst [p0+r], e0"
+  -
+    input:
+      bytes: [ 0xe5, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldmst #0, e0"
+  -
+    input:
+      bytes: [ 0x49, 0x00, 0x40, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldmst [+a0]#0, e0"
+  -
+    input:
+      bytes: [ 0x69, 0x00, 0x40, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldmst [p0+c]#0, e0"
+  -
+    input:
+      bytes: [ 0x49, 0x00, 0x40, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldmst [a0]#0, e0"
+  -
+    input:
+      bytes: [ 0x49, 0x00, 0x40, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "lducx [a0]#0"
+  -
+    input:
+      bytes: [ 0x15, 0x00, 0x00, 0x0c ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "lducx #0"
+  -
+    input:
+      bytes: [ 0xc5, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a0, #0"
+  -
+    input:
+      bytes: [ 0xd9, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a0, [a0]#0"
+  -
+    input:
+      bytes: [ 0x49, 0x00, 0x00, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a0, [a0]#0"
+  -
+    input:
+      bytes: [ 0xfc, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "loop a0, #0xffffffe0"
+  -
+    input:
+      bytes: [ 0xfd, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "loop a0, #0"
+  -
+    input:
+      bytes: [ 0xfd, 0x00, 0x00, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "loopu #0"
+  -
+    input:
+      bytes: [ 0x7a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "lt d15, d0, d0"
+  -
+    input:
+      bytes: [ 0xfa, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "lt d15, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x20, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "lt d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x40, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "lt d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0x20, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "lt.a d0, a0, a0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x20, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "lt.b d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x30, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "lt.bu d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x20, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "lt.h d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x30, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "lt.hu d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x30, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "lt.u d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x60, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "lt.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x20, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "lt.w d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x30, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "lt.wu d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x03, 0x00, 0x0a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd d0, d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x13, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x13, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd e0, e0, d0, #0"
+  -
+    input:
+      bytes: [ 0x03, 0x00, 0x6a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd e0, e0, d0, d0"
+  -
+    input:
+      bytes: [ 0x6b, 0x00, 0x61, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd.f d0, d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd.h e0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0x64, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd.h e0, e0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0x68, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd.h e0, e0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0x6c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd.h e0, e0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x10, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd.q d0, d0, d0u, d0u, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd.q d0, d0, d0, d0u, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x04, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd.q d0, d0, d0, d0l, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x08, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd.q d0, d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x14, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd.q d0, d0, d0l, d0l, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd.q e0, e0, d0, d0u, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x64, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd.q e0, e0, d0, d0l, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x6c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd.q e0, e0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x70, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd.q e0, e0, d0u, d0u, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x74, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd.q e0, e0, d0l, d0l, #0"
+  -
+    input:
+      bytes: [ 0x13, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd.u e0, e0, d0, #0"
+  -
+    input:
+      bytes: [ 0x03, 0x00, 0x68, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd.u e0, e0, d0, d0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0x70, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddm.h e0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0x74, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddm.h e0, e0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0x78, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddm.h e0, e0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0x7c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddm.h e0, e0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0xf0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddms.h e0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0xf4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddms.h e0, e0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0xf8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddms.h e0, e0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0xfc, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddms.h e0, e0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x78, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddr.h d0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0x30, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddr.h d0, d0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0x34, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddr.h d0, d0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0x38, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddr.h d0, d0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0x3c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddr.h d0, d0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x18, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddr.q d0, d0, d0u, d0u, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x1c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddr.q d0, d0, d0l, d0l, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0xf8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddrs.h d0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0xb0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddrs.h d0, d0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0xb4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddrs.h d0, d0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0xb8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddrs.h d0, d0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0xbc, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddrs.h d0, d0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x98, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddrs.q d0, d0, d0u, d0u, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x9c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddrs.q d0, d0, d0l, d0l, #0"
+  -
+    input:
+      bytes: [ 0x03, 0x00, 0x8a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds d0, d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x13, 0x00, 0xa0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x13, 0x00, 0xe0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds e0, e0, d0, #0"
+  -
+    input:
+      bytes: [ 0x03, 0x00, 0xea, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds e0, e0, d0, d0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0xe0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds.h e0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0xe4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds.h e0, e0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0xe8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds.h e0, e0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0xec, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds.h e0, e0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x90, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds.q d0, d0, d0u, d0u, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds.q d0, d0, d0, d0u, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x84, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds.q d0, d0, d0, d0l, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x88, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds.q d0, d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x94, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds.q d0, d0, d0l, d0l, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0xe0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds.q e0, e0, d0, d0u, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0xe4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds.q e0, e0, d0, d0l, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0xec, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds.q e0, e0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0xf0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds.q e0, e0, d0u, d0u, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0xf4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds.q e0, e0, d0l, d0l, #0"
+  -
+    input:
+      bytes: [ 0x13, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds.u d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x03, 0x00, 0x88, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds.u d0, d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x13, 0x00, 0xc0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds.u e0, e0, d0, #0"
+  -
+    input:
+      bytes: [ 0x03, 0x00, 0xe8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds.u e0, e0, d0, d0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsu.h e0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0x64, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsu.h e0, e0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0x68, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsu.h e0, e0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0x6c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsu.h e0, e0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0x70, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsum.h e0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0x74, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsum.h e0, e0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0x78, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsum.h e0, e0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0x7c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsum.h e0, e0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0xf0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsums.h e0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0xf4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsums.h e0, e0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0xf8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsums.h e0, e0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0xfc, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsums.h e0, e0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0x30, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsur.h d0, d0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0x34, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsur.h d0, d0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0x38, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsur.h d0, d0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0x3c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsur.h d0, d0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0xb0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsurs.h d0, d0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0xb4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsurs.h d0, d0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0xb8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsurs.h d0, d0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0xbc, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsurs.h d0, d0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0xe0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsus.h e0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0xe4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsus.h e0, e0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0xe8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsus.h e0, e0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0xec, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsus.h e0, e0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xa0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "max d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x40, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "max d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xa0, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "max.b d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xb0, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "max.bu d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xa0, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "max.h d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xb0, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "max.hu d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xb0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "max.u d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x60, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "max.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x4d, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "mfcr d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x80, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "min d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x00, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "min d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x80, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "min.b d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x90, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "min.bu d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x80, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "min.h d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x90, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "min.hu d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x90, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "min.u d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x20, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "min.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x02, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d0, d0"
+  -
+    input:
+      bytes: [ 0x82, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d0, #0"
+  -
+    input:
+      bytes: [ 0xd2, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov e0, #0"
+  -
+    input:
+      bytes: [ 0xda, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d15, #0"
+  -
+    input:
+      bytes: [ 0x3b, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xf0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d0, d0"
+  -
+    input:
+      bytes: [ 0xfb, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov e0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x00, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov e0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x10, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov e0, d0, d0"
+  -
+    input:
+      bytes: [ 0xa0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.a a0, #0"
+  -
+    input:
+      bytes: [ 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.a a0, d0"
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0x30, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.a a0, d0"
+  -
+    input:
+      bytes: [ 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.aa a0, a0"
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.aa a0, a0"
+  -
+    input:
+      bytes: [ 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.d d0, a0"
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0xc0, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.d d0, a0"
+  -
+    input:
+      bytes: [ 0xbb, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.u d0, #0"
+  -
+    input:
+      bytes: [ 0x7b, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh d0, #0"
+  -
+    input:
+      bytes: [ 0x91, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a0, #0"
+  -
+    input:
+      bytes: [ 0x23, 0x00, 0x0a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub d0, d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x33, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x33, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub e0, e0, d0, #0"
+  -
+    input:
+      bytes: [ 0x23, 0x00, 0x6a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub e0, e0, d0, d0"
+  -
+    input:
+      bytes: [ 0x6b, 0x00, 0x71, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub.f d0, d0, d0, d0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub.h e0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0x64, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub.h e0, e0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0x68, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub.h e0, e0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0x6c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub.h e0, e0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x10, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub.q d0, d0, d0u, d0u, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub.q d0, d0, d0, d0u, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x04, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub.q d0, d0, d0, d0l, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x08, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub.q d0, d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x14, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub.q d0, d0, d0l, d0l, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub.q e0, e0, d0, d0u, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x64, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub.q e0, e0, d0, d0l, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x6c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub.q e0, e0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x70, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub.q e0, e0, d0u, d0u, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x74, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub.q e0, e0, d0l, d0l, #0"
+  -
+    input:
+      bytes: [ 0x33, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub.u e0, e0, d0, #0"
+  -
+    input:
+      bytes: [ 0x23, 0x00, 0x68, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub.u e0, e0, d0, d0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubad.h e0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x64, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubad.h e0, e0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x68, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubad.h e0, e0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x6c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubad.h e0, e0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x70, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubadm.h e0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x74, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubadm.h e0, e0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x78, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubadm.h e0, e0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x7c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubadm.h e0, e0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xf0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubadms.h e0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xf4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubadms.h e0, e0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xf8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubadms.h e0, e0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xfc, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubadms.h e0, e0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x30, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubadr.h d0, d0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x34, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubadr.h d0, d0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x38, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubadr.h d0, d0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x3c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubadr.h d0, d0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xb0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubadrs.h d0, d0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xb4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubadrs.h d0, d0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xb8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubadrs.h d0, d0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xbc, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubadrs.h d0, d0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xe0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubads.h e0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xe4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubads.h e0, e0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xe8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubads.h e0, e0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xec, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubads.h e0, e0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0x70, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubm.h e0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0x74, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubm.h e0, e0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0x78, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubm.h e0, e0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0x7c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubm.h e0, e0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0xf0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubms.h e0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0xf4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubms.h e0, e0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0xf8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubms.h e0, e0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0xfc, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubms.h e0, e0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x78, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubr.h d0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0x30, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubr.h d0, d0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0x34, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubr.h d0, d0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0x38, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubr.h d0, d0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0x3c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubr.h d0, d0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x18, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubr.q d0, d0, d0u, d0u, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x1c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubr.q d0, d0, d0l, d0l, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0xf8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubrs.h d0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0xb0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubrs.h d0, d0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0xb4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubrs.h d0, d0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0xb8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubrs.h d0, d0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0xbc, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubrs.h d0, d0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x98, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubrs.q d0, d0, d0u, d0u, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x9c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubrs.q d0, d0, d0l, d0l, #0"
+  -
+    input:
+      bytes: [ 0x23, 0x00, 0x8a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs d0, d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x33, 0x00, 0xa0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x33, 0x00, 0xe0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs e0, e0, d0, #0"
+  -
+    input:
+      bytes: [ 0x23, 0x00, 0xea, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs e0, e0, d0, d0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0xe0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs.h e0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0xe4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs.h e0, e0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0xe8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs.h e0, e0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0xec, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs.h e0, e0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x90, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs.q d0, d0, d0u, d0u, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs.q d0, d0, d0, d0u, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x84, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs.q d0, d0, d0, d0l, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x88, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs.q d0, d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x94, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs.q d0, d0, d0l, d0l, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0xe0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs.q e0, e0, d0, d0u, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0xe4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs.q e0, e0, d0, d0l, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0xec, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs.q e0, e0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0xf0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs.q e0, e0, d0u, d0u, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0xf4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs.q e0, e0, d0l, d0l, #0"
+  -
+    input:
+      bytes: [ 0x33, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs.u d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x23, 0x00, 0x88, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs.u d0, d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x33, 0x00, 0xc0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs.u e0, e0, d0, #0"
+  -
+    input:
+      bytes: [ 0x23, 0x00, 0xe8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs.u e0, e0, d0, d0"
+  -
+    input:
+      bytes: [ 0xcd, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "mtcr #0, d0"
+  -
+    input:
+      bytes: [ 0xe2, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul d0, d0"
+  -
+    input:
+      bytes: [ 0x53, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x73, 0x00, 0x0a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x53, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul e0, d0, #0"
+  -
+    input:
+      bytes: [ 0x73, 0x00, 0x6a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul e0, d0, d0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0x41, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.f d0, d0, d0"
+  -
+    input:
+      bytes: [ 0xb3, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.h e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xb3, 0x00, 0x64, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.h e0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xb3, 0x00, 0x68, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.h e0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xb3, 0x00, 0x6c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.h e0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0x93, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.q d0, d0, d0u, #0"
+  -
+    input:
+      bytes: [ 0x93, 0x00, 0x04, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.q d0, d0, d0l, #0"
+  -
+    input:
+      bytes: [ 0x93, 0x00, 0x08, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.q d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x93, 0x00, 0x10, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.q d0, d0u, d0u, #0"
+  -
+    input:
+      bytes: [ 0x93, 0x00, 0x14, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.q d0, d0l, d0l, #0"
+  -
+    input:
+      bytes: [ 0x93, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.q e0, d0, d0u, #0"
+  -
+    input:
+      bytes: [ 0x93, 0x00, 0x64, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.q e0, d0, d0l, #0"
+  -
+    input:
+      bytes: [ 0x93, 0x00, 0x6c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.q e0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x53, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.u e0, d0, #0"
+  -
+    input:
+      bytes: [ 0x73, 0x00, 0x68, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.u e0, d0, d0"
+  -
+    input:
+      bytes: [ 0xb3, 0x00, 0x70, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulm.h e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xb3, 0x00, 0x74, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulm.h e0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xb3, 0x00, 0x78, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulm.h e0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xb3, 0x00, 0x7c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulm.h e0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0xb3, 0x00, 0xf0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulms.h e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xb3, 0x00, 0xf4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulms.h e0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xb3, 0x00, 0xf8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulms.h e0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xb3, 0x00, 0xfc, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulms.h e0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0xb3, 0x00, 0x30, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulr.h d0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xb3, 0x00, 0x34, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulr.h d0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xb3, 0x00, 0x38, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulr.h d0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xb3, 0x00, 0x3c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulr.h d0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0x93, 0x00, 0x18, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulr.q d0, d0u, d0u, #0"
+  -
+    input:
+      bytes: [ 0x93, 0x00, 0x1c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulr.q d0, d0l, d0l, #0"
+  -
+    input:
+      bytes: [ 0x53, 0x00, 0xa0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "muls d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x73, 0x00, 0x8a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "muls d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x53, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "muls.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x73, 0x00, 0x88, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "muls.u d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0x90, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "nand d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8f, 0x00, 0x20, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "nand d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x07, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "nand.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x10, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "ne d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x20, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "ne d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0x10, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "ne.a d0, a0, a0"
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0x90, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "nez.a d0, a0"
+  -
+    input:
+      bytes: [ 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "nop"
+  -
+    input:
+      bytes: [ 0x0d, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "nop"
+  -
+    input:
+      bytes: [ 0x46, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "nor d0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0xb0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "nor d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8f, 0x00, 0x60, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "nor d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x87, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "nor.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0xa6, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "or d0, d0"
+  -
+    input:
+      bytes: [ 0x96, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "or d15, #0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0xa0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "or d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8f, 0x00, 0x40, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "or d0, d0, #0"
+  -
+    input:
+      bytes: [ 0xc7, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.and.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0xc7, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.andn.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x70, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.eq d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0xe0, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.eq d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xb0, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.ge d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x60, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.ge d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xc0, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.ge.u d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x80, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.ge.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x90, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.lt d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x20, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.lt d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xa0, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.lt.u d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x40, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.lt.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x80, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.ne d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x00, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.ne d0, d0, #0"
+  -
+    input:
+      bytes: [ 0xc7, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.nor.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0xc7, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.or.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x87, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0xf0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "orn d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8f, 0x00, 0xe0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "orn d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x07, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "orn.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x6b, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "pack d0, e0, d0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "parity d0, d0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0x51, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "q31tof d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0x91, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "qseed.f d0, d0"
+  -
+    input:
+      bytes: [ 0x0d, 0x00, 0x80, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "restore d0"
+  -
+    input:
+      bytes: [ 0x00, 0x90 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "ret"
+  -
+    input:
+      bytes: [ 0x0d, 0x00, 0x80, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "ret"
+  -
+    input:
+      bytes: [ 0x00, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "rfe"
+  -
+    input:
+      bytes: [ 0x0d, 0x00, 0xc0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "rfe"
+  -
+    input:
+      bytes: [ 0x0d, 0x00, 0x40, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "rfm"
+  -
+    input:
+      bytes: [ 0x0d, 0x00, 0x40, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "rslcx"
+  -
+    input:
+      bytes: [ 0x2f, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "rstv"
+  -
+    input:
+      bytes: [ 0x32, 0x50 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "rsub d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x00, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "rsub d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x40, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "rsubs d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x60, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "rsubs.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x32, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "sat.b d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xe0, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "sat.b d0, d0"
+  -
+    input:
+      bytes: [ 0x32, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "sat.bu d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xf0, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "sat.bu d0, d0"
+  -
+    input:
+      bytes: [ 0x32, 0x20 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "sat.h d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xe0, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "sat.h d0, d0"
+  -
+    input:
+      bytes: [ 0x32, 0x30 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "sat.hu d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xf0, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "sat.hu d0, d0"
+  -
+    input:
+      bytes: [ 0x2b, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "sel d0, d0, d0, d0"
+  -
+    input:
+      bytes: [ 0xab, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "sel d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x2b, 0x00, 0x50, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "seln d0, d0, d0, d0"
+  -
+    input:
+      bytes: [ 0xab, 0x00, 0xa0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "seln d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x06, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh d0, #0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8f, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x27, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.and.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x27, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.andn.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x70, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.eq d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0xe0, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.eq d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xb0, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.ge d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x60, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.ge d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xc0, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.ge.u d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x80, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.ge.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.h d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8f, 0x00, 0x00, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.h d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x90, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.lt d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x20, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.lt d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xa0, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.lt.u d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x40, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.lt.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0xa7, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.nand.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x80, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.ne d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x00, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.ne d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x27, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.nor.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x27, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.or.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0xa7, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.orn.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0xa7, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.xnor.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0xa7, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.xor.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x86, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha d0, #0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0x10, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8f, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0x10, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha.h d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8f, 0x00, 0x20, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha.h d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "shas d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8f, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "shas d0, d0, #0"
+  -
+    input:
+      bytes: [ 0xf8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.a [sp]#0, a15"
+  -
+    input:
+      bytes: [ 0xec, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.a [a0]#0, a15"
+  -
+    input:
+      bytes: [ 0xe8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.a [a15]#0, a0"
+  -
+    input:
+      bytes: [ 0xe4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.a [a0+], a0"
+  -
+    input:
+      bytes: [ 0xf4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.a [a0], a0"
+  -
+    input:
+      bytes: [ 0xb5, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.a [a0]#0, a0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x80, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.a [a0+]#0, a0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x80, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.a [p0+r], a0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x80, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.a [+a0]#0, a0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x80, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.a [p0+c]#0, a0"
+  -
+    input:
+      bytes: [ 0xa5, 0x00, 0x00, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.a #0, a0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x80, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.a [a0]#0, a0"
+  -
+    input:
+      bytes: [ 0x34, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [a0], d0"
+  -
+    input:
+      bytes: [ 0x28, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [a15]#0, d0"
+  -
+    input:
+      bytes: [ 0x2c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [a0]#0, d15"
+  -
+    input:
+      bytes: [ 0x24, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [a0+], d0"
+  -
+    input:
+      bytes: [ 0xe9, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [a0]#0, d0"
+  -
+    input:
+      bytes: [ 0x25, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b #0, d0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [a0+]#0, d0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [p0+r], d0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [+a0]#0, d0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [p0+c]#0, d0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x00, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [a0]#0, d0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x40, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.d [a0+]#0, e0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x40, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.d [p0+r], e0"
+  -
+    input:
+      bytes: [ 0xa5, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.d #0, e0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x40, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.d [+a0]#0, e0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x40, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.d [p0+c]#0, e0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x40, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.d [a0]#0, e0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0xc0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.da [a0+]#0, p0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0xc0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.da [p0+r], p0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0xc0, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.da [+a0]#0, p0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0xc0, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.da [p0+c]#0, p0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0xc0, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.da [a0]#0, p0"
+  -
+    input:
+      bytes: [ 0xa5, 0x00, 0x00, 0x0c ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.da #0, p0"
+  -
+    input:
+      bytes: [ 0xa4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [a0+], d0"
+  -
+    input:
+      bytes: [ 0xa8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [a15]#0, d0"
+  -
+    input:
+      bytes: [ 0xac, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [a0]#0, d15"
+  -
+    input:
+      bytes: [ 0xb4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [a0], d0"
+  -
+    input:
+      bytes: [ 0xf9, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [a0]#0, d0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [a0+]#0, d0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [p0+r], d0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x80, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [+a0]#0, d0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x80, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [p0+c]#0, d0"
+  -
+    input:
+      bytes: [ 0x25, 0x00, 0x00, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h #0, d0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x80, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [a0]#0, d0"
+  -
+    input:
+      bytes: [ 0x65, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.q #0, d0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x00, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.q [a0+]#0, d0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x00, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.q [p0+r], d0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x00, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.q [+a0]#0, d0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x00, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.q [p0+c]#0, d0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x00, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.q [a0]#0, d0"
+  -
+    input:
+      bytes: [ 0xd5, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.t #0, #0, #0"
+  -
+    input:
+      bytes: [ 0x78, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w [sp]#0, d15"
+  -
+    input:
+      bytes: [ 0x74, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w [a0], d0"
+  -
+    input:
+      bytes: [ 0x64, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w [a0+], d0"
+  -
+    input:
+      bytes: [ 0x68, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w [a15]#0, d0"
+  -
+    input:
+      bytes: [ 0x6c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w [a0]#0, d15"
+  -
+    input:
+      bytes: [ 0x59, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w [a0]#0, d0"
+  -
+    input:
+      bytes: [ 0xa5, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w #0, d0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x00, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w [a0+]#0, d0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x00, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w [p0+r], d0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x00, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w [+a0]#0, d0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x00, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w [p0+c]#0, d0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x00, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w [a0]#0, d0"
+  -
+    input:
+      bytes: [ 0x15, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "stlcx #0"
+  -
+    input:
+      bytes: [ 0x49, 0x00, 0x80, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "stlcx [a0]#0"
+  -
+    input:
+      bytes: [ 0x15, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "stucx #0"
+  -
+    input:
+      bytes: [ 0x49, 0x00, 0xc0, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "stucx [a0]#0"
+  -
+    input:
+      bytes: [ 0x52, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub d0, d15, d0"
+  -
+    input:
+      bytes: [ 0x5a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub d15, d0, d0"
+  -
+    input:
+      bytes: [ 0xa2, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub.a sp, #0"
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub.a a0, a0, a0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x80, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub.b d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x6b, 0x00, 0x31, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub.f d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x80, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub.h d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xd0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "subc d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x62, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "subs d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xa0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "subs d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xa0, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "subs.h d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xb0, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "subs.hu d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xb0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "subs.u d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xc0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "subx d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0d, 0x00, 0x00, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "svlcx"
+  -
+    input:
+      bytes: [ 0x49, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "swap.w [a0+]#0, d0"
+  -
+    input:
+      bytes: [ 0x69, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "swap.w [p0+r], d0"
+  -
+    input:
+      bytes: [ 0xe5, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "swap.w #0, d0"
+  -
+    input:
+      bytes: [ 0x49, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "swap.w [+a0]#0, d0"
+  -
+    input:
+      bytes: [ 0x69, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "swap.w [p0+c]#0, d0"
+  -
+    input:
+      bytes: [ 0x49, 0x00, 0x00, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "swap.w [a0]#0, d0"
+  -
+    input:
+      bytes: [ 0x69, 0x00, 0x00, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "swap.w [p0+i], d0"
+  -
+    input:
+      bytes: [ 0xad, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "syscall #0"
+  -
+    input:
+      bytes: [ 0x75, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "tlbdemap d0"
+  -
+    input:
+      bytes: [ 0x75, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "tlbflush.a"
+  -
+    input:
+      bytes: [ 0x75, 0x00, 0x50, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "tlbflush.b"
+  -
+    input:
+      bytes: [ 0x75, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "tlbmap e0"
+  -
+    input:
+      bytes: [ 0x75, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "tlbprobe.a d0"
+  -
+    input:
+      bytes: [ 0x75, 0x00, 0x90, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "tlbprobe.i d0"
+  -
+    input:
+      bytes: [ 0x0d, 0x00, 0x40, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "trapsv"
+  -
+    input:
+      bytes: [ 0x0d, 0x00, 0x00, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "trapv"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "unpack e0, d0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0xc1, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "updfl d0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0x61, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "utof d0, d0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0xd0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "xnor d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8f, 0x00, 0xa0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "xnor d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x07, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "xnor.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0xc6, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor d0, d0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0xc0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8f, 0x00, 0x80, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xf0, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor.eq d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0xe0, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor.eq d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x30, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor.ge d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x60, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor.ge d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x40, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor.ge.u d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x80, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor.ge.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x10, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor.lt d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x20, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor.lt d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x20, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor.lt.u d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x40, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor.lt.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x00, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor.ne d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x00, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor.ne d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x07, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_160" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor.t d0, d0, #0, d0, #0"
diff --git a/tests/MC/TriCore/tc161.s.yaml b/tests/MC/TriCore/tc161.s.yaml
new file mode 100644
index 000000000..c380a16a0
--- /dev/null
+++ b/tests/MC/TriCore/tc161.s.yaml
@@ -0,0 +1,7516 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xc0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "abs d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xc0, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "abs.b d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xc0, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "abs.h d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xe0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "absdif d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0xc0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "absdif d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xe0, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "absdif.b d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xe0, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "absdif.h d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xf0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "absdifs d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0xe0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "absdifs d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xf0, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "absdifs.h d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xd0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "abss d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xd0, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "abss.h d0, d0"
+  -
+    input:
+      bytes: [ 0x12, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d0, d15, d0"
+  -
+    input:
+      bytes: [ 0x92, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d0, d15, #0"
+  -
+    input:
+      bytes: [ 0x1a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d15, d0, d0"
+  -
+    input:
+      bytes: [ 0x42, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d0, d0"
+  -
+    input:
+      bytes: [ 0x9a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d15, d0, #0"
+  -
+    input:
+      bytes: [ 0xc2, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x30, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "add.a a0, a0"
+  -
+    input:
+      bytes: [ 0xb0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "add.a a0, #0"
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0x10, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "add.a a0, a0, a0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "add.b d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x6b, 0x00, 0x21, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "add.f d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x00, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "add.h d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x50, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "addc d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0xa0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "addc d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x1b, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "addi d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x9b, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "addih d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x11, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "addih.a a0, a0, #0"
+  -
+    input:
+      bytes: [ 0x22, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "adds d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "adds d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "adds d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x20, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "adds.h d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x30, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "adds.hu d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x30, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "adds.u d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "adds.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x10, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "addsc.a a0, a0, d15, #0"
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0x00, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "addsc.a a0, a0, d0, #0"
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0x20, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "addsc.at a0, a0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "addx d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "addx d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x26, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d0, d0"
+  -
+    input:
+      bytes: [ 0x16, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d15, #0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8f, 0x00, 0x00, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x47, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.and.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x47, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.andn.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x00, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.eq d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.eq d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x40, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.ge d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x80, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.ge d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x50, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.ge.u d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0xa0, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.ge.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x20, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.lt d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x40, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.lt d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x30, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.lt.u d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x60, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.lt.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x10, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.ne d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x20, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.ne d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x47, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.nor.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x47, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.or.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x87, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0xe0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "andn d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8f, 0x00, 0xc0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "andn d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x87, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "andn.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0xe0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "bisr #0"
+  -
+    input:
+      bytes: [ 0xad, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "bisr #0"
+  -
+    input:
+      bytes: [ 0xad, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "bisr #0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0x10, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "bmerge d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0x90, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "bsplit e0, d0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x80, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachea.i [a0+]#0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x80, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachea.i [p0+r]"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x80, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachea.i [+a0]#0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x80, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachea.i [p0+c]#0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x80, 0x0b ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachea.i [a0]#0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x00, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachea.w [a0+]#0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x00, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachea.w [p0+r]"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x00, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachea.w [+a0]#0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x00, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachea.w [p0+c]#0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x00, 0x0b ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachea.w [a0]#0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x40, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachea.wi [a0+]#0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x40, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachea.wi [p0+r]"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x40, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachea.wi [+a0]#0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x40, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachea.wi [p0+c]#0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x40, 0x0b ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachea.wi [a0]#0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x80, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachei.i [a0+]#0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x80, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachei.i [+a0]#0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x80, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachei.i [a0]#0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0xc0, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachei.w [a0+]#0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0xc0, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachei.w [+a0]#0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0xc0, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachei.w [a0]#0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0xc0, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachei.wi [a0+]#0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0xc0, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachei.wi [+a0]#0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0xc0, 0x0b ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachei.wi [a0]#0"
+  -
+    input:
+      bytes: [ 0x8a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "cadd d0, d15, #0"
+  -
+    input:
+      bytes: [ 0x2b, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "cadd d0, d0, d0, d0"
+  -
+    input:
+      bytes: [ 0xab, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "cadd d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0xca, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "caddn d0, d15, #0"
+  -
+    input:
+      bytes: [ 0x2b, 0x00, 0x10, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "caddn d0, d0, d0, d0"
+  -
+    input:
+      bytes: [ 0xab, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "caddn d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x5c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0"
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "calla #0"
+  -
+    input:
+      bytes: [ 0x2d, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "calli a0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0xc0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "clo d0, d0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0xd0, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "clo.h d0, d0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0xd0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "cls d0, d0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0xe0, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "cls.h d0, d0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0xb0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "clz d0, d0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0xc0, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "clz.h d0, d0"
+  -
+    input:
+      bytes: [ 0x2a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmov d0, d15, d0"
+  -
+    input:
+      bytes: [ 0xaa, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmov d0, d15, #0"
+  -
+    input:
+      bytes: [ 0x6a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmovn d0, d15, d0"
+  -
+    input:
+      bytes: [ 0xea, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmovn d0, d15, #0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmp.f d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x49, 0x00, 0xc0, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpswap.w [a0]#0, e0"
+  -
+    input:
+      bytes: [ 0x69, 0x00, 0xc0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpswap.w [p0+r], e0"
+  -
+    input:
+      bytes: [ 0x69, 0x00, 0xc0, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpswap.w [p0+c]#0, e0"
+  -
+    input:
+      bytes: [ 0x49, 0x00, 0xc0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpswap.w [a0+]#0, e0"
+  -
+    input:
+      bytes: [ 0x49, 0x00, 0xc0, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpswap.w [+a0]#0, e0"
+  -
+    input:
+      bytes: [ 0x2b, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "csub d0, d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x2b, 0x00, 0x30, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "csubn d0, d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x00, 0xa0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "debug"
+  -
+    input:
+      bytes: [ 0x0d, 0x00, 0x00, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "debug"
+  -
+    input:
+      bytes: [ 0x77, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "dextr d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x17, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "dextr d0, d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0d, 0x00, 0x40, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "disable"
+  -
+    input:
+      bytes: [ 0x0d, 0x00, 0xc0, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "disable d0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0x01, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "div e0, d0, d0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0x11, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "div.u e0, d0, d0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0x51, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "div.f d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0d, 0x00, 0x80, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "dsync"
+  -
+    input:
+      bytes: [ 0x6b, 0x00, 0xd0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "dvadj e0, e0, d0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0xa0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "dvinit e0, d0, d0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0xa0, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "dvinit.b e0, d0, d0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0xa0, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "dvinit.bu e0, d0, d0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0xa0, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "dvinit.h e0, d0, d0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0xa0, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "dvinit.hu e0, d0, d0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0xa0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "dvinit.u e0, d0, d0"
+  -
+    input:
+      bytes: [ 0x6b, 0x00, 0xf0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "dvstep e0, e0, d0"
+  -
+    input:
+      bytes: [ 0x6b, 0x00, 0xe0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "dvstep.u e0, e0, d0"
+  -
+    input:
+      bytes: [ 0x0d, 0x00, 0x00, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "enable"
+  -
+    input:
+      bytes: [ 0x3a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "eq d15, d0, d0"
+  -
+    input:
+      bytes: [ 0xba, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "eq d15, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x00, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "eq d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x00, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "eq d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "eq.a d0, a0, a0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x00, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "eq.b d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x00, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "eq.h d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x00, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "eq.w d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x60, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "eqany.b d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0xc0, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "eqany.b d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x60, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "eqany.h d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0xc0, 0x0e ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "eqany.h d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0x80, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "eqz.a d0, a0"
+  -
+    input:
+      bytes: [ 0x17, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr d0, d0, e0"
+  -
+    input:
+      bytes: [ 0x37, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr d0, d0, #0, #0"
+  -
+    input:
+      bytes: [ 0x57, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x17, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d0, d0, e0"
+  -
+    input:
+      bytes: [ 0x37, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d0, d0, #0, #0"
+  -
+    input:
+      bytes: [ 0x57, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x61, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcall #0"
+  -
+    input:
+      bytes: [ 0xe1, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcalla #0"
+  -
+    input:
+      bytes: [ 0x2d, 0x00, 0x10, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcalli a0"
+  -
+    input:
+      bytes: [ 0x00, 0x70 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "fret"
+  -
+    input:
+      bytes: [ 0x0d, 0x00, 0xc0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "fret"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0x01, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "ftoi d0, d0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0x11, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "ftoq31 d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0x21, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "ftou d0, d0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0x31, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "ftoiz d0, d0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0x81, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "ftoq31z d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0x71, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "ftouz d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x40, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "ge d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x80, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "ge d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0x30, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "ge.a d0, a0, a0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x50, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "ge.u d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0xa0, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "ge.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x37, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "imask e0, d0, #0, #0"
+  -
+    input:
+      bytes: [ 0x57, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "imask e0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0xb7, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "imask e0, #0, #0, #0"
+  -
+    input:
+      bytes: [ 0xd7, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "imask e0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x67, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "ins.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x17, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d0, d0, d0, e0"
+  -
+    input:
+      bytes: [ 0x37, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d0, d0, d0, #0, #0"
+  -
+    input:
+      bytes: [ 0x57, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d0, d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x97, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d0, d0, #0, e0"
+  -
+    input:
+      bytes: [ 0xb7, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d0, d0, #0, #0, #0"
+  -
+    input:
+      bytes: [ 0xd7, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x67, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "insn.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0d, 0x00, 0xc0, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "isync"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0x41, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "itof d0, d0"
+  -
+    input:
+      bytes: [ 0x6b, 0x00, 0xa0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "ixmax e0, e0, d0"
+  -
+    input:
+      bytes: [ 0x6b, 0x00, 0xb0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "ixmax.u e0, e0, d0"
+  -
+    input:
+      bytes: [ 0x6b, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "ixmin e0, e0, d0"
+  -
+    input:
+      bytes: [ 0x6b, 0x00, 0x90, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "ixmin.u e0, e0, d0"
+  -
+    input:
+      bytes: [ 0x3c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0"
+  -
+    input:
+      bytes: [ 0x1d, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0"
+  -
+    input:
+      bytes: [ 0x9d, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "ja #0"
+  -
+    input:
+      bytes: [ 0xbe, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d0, #0x20"
+  -
+    input:
+      bytes: [ 0x9e, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, #0, #0x20"
+  -
+    input:
+      bytes: [ 0x3e, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d0, #0"
+  -
+    input:
+      bytes: [ 0x1e, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, #0, #0"
+  -
+    input:
+      bytes: [ 0x5f, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d0, d0, #0"
+  -
+    input:
+      bytes: [ 0xdf, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d0, #0, #0"
+  -
+    input:
+      bytes: [ 0x7d, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq.a a0, a0, #0"
+  -
+    input:
+      bytes: [ 0x7f, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "jge d0, d0, #0"
+  -
+    input:
+      bytes: [ 0xff, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "jge d0, #0, #0"
+  -
+    input:
+      bytes: [ 0x7f, 0x00, 0x00, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "jge.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0xff, 0x00, 0x00, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "jge.u d0, #0, #0"
+  -
+    input:
+      bytes: [ 0xce, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "jgez d0, #0"
+  -
+    input:
+      bytes: [ 0x4e, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "jgtz d0, #0"
+  -
+    input:
+      bytes: [ 0xdc, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "ji a0"
+  -
+    input:
+      bytes: [ 0x2d, 0x00, 0x30, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "ji a0"
+  -
+    input:
+      bytes: [ 0x5d, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "jl #0"
+  -
+    input:
+      bytes: [ 0xdd, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "jla #0"
+  -
+    input:
+      bytes: [ 0x8e, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlez d0, #0"
+  -
+    input:
+      bytes: [ 0x2d, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "jli a0"
+  -
+    input:
+      bytes: [ 0x3f, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt d0, d0, #0"
+  -
+    input:
+      bytes: [ 0xbf, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt d0, #0, #0"
+  -
+    input:
+      bytes: [ 0x3f, 0x00, 0x00, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0xbf, 0x00, 0x00, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt.u d0, #0, #0"
+  -
+    input:
+      bytes: [ 0x0e, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "jltz d0, #0"
+  -
+    input:
+      bytes: [ 0xfe, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, d0, #0x20"
+  -
+    input:
+      bytes: [ 0xde, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, #0, #0x20"
+  -
+    input:
+      bytes: [ 0x7e, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, d0, #0"
+  -
+    input:
+      bytes: [ 0x5e, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, #0, #0"
+  -
+    input:
+      bytes: [ 0x5f, 0x00, 0x00, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d0, d0, #0"
+  -
+    input:
+      bytes: [ 0xdf, 0x00, 0x00, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d0, #0, #0"
+  -
+    input:
+      bytes: [ 0x7d, 0x00, 0x00, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne.a a0, a0, #0"
+  -
+    input:
+      bytes: [ 0x1f, 0x00, 0x00, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "jned d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x9f, 0x00, 0x00, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "jned d0, #0, #0"
+  -
+    input:
+      bytes: [ 0x1f, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnei d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x9f, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnei d0, #0, #0"
+  -
+    input:
+      bytes: [ 0xee, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz d15, #0"
+  -
+    input:
+      bytes: [ 0xf6, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz d0, #0"
+  -
+    input:
+      bytes: [ 0x7c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz.a a0, #0"
+  -
+    input:
+      bytes: [ 0xbd, 0x00, 0x00, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz.a a0, #0"
+  -
+    input:
+      bytes: [ 0xae, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz.t d15, #0, #0"
+  -
+    input:
+      bytes: [ 0x6f, 0x00, 0x00, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz.t d0, #0, #0"
+  -
+    input:
+      bytes: [ 0x6e, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d15, #0"
+  -
+    input:
+      bytes: [ 0x76, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d0, #0"
+  -
+    input:
+      bytes: [ 0xbc, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.a a0, #0"
+  -
+    input:
+      bytes: [ 0xbd, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.a a0, #0"
+  -
+    input:
+      bytes: [ 0x2e, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.t d15, #0, #0"
+  -
+    input:
+      bytes: [ 0x6f, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.t d0, #0, #0"
+  -
+    input:
+      bytes: [ 0xd8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.a a15, [sp]#0"
+  -
+    input:
+      bytes: [ 0xc8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.a a0, [a15]#0"
+  -
+    input:
+      bytes: [ 0xcc, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.a a15, [a0]#0"
+  -
+    input:
+      bytes: [ 0xc4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.a a0, [a0+]"
+  -
+    input:
+      bytes: [ 0xd4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.a a0, [a0]"
+  -
+    input:
+      bytes: [ 0x99, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.a a0, [a0]#0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x80, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.a a0, [a0+]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0x80, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.a a0, [p0+r]"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x80, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.a a0, [+a0]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0x80, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.a a0, [p0+c]#0"
+  -
+    input:
+      bytes: [ 0x85, 0x00, 0x00, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.a a0, #0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x80, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.a a0, [a0]#0"
+  -
+    input:
+      bytes: [ 0x79, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.b d0, [a0]#0"
+  -
+    input:
+      bytes: [ 0x05, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.b d0, #0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.b d0, [a0+]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.b d0, [p0+r]"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.b d0, [+a0]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.b d0, [p0+c]#0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x00, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.b d0, [a0]#0"
+  -
+    input:
+      bytes: [ 0x14, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d0, [a0]"
+  -
+    input:
+      bytes: [ 0x0c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d15, [a0]#0"
+  -
+    input:
+      bytes: [ 0x08, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d0, [a15]#0"
+  -
+    input:
+      bytes: [ 0x04, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d0, [a0+]"
+  -
+    input:
+      bytes: [ 0x39, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d0, [a0]#0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d0, [a0+]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d0, [p0+r]"
+  -
+    input:
+      bytes: [ 0x05, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d0, #0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x40, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d0, [+a0]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0x40, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d0, [p0+c]#0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x40, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d0, [a0]#0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x40, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.d e0, [a0+]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0x40, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.d e0, [p0+r]"
+  -
+    input:
+      bytes: [ 0x85, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.d e0, #0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x40, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.d e0, [+a0]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0x40, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.d e0, [p0+c]#0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x40, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.d e0, [a0]#0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0xc0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.da p0, [a0+]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0xc0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.da p0, [p0+r]"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0xc0, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.da p0, [+a0]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0xc0, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.da p0, [p0+c]#0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0xc0, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.da p0, [a0]#0"
+  -
+    input:
+      bytes: [ 0x85, 0x00, 0x00, 0x0c ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.da p0, #0"
+  -
+    input:
+      bytes: [ 0x84, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.h d0, [a0+]"
+  -
+    input:
+      bytes: [ 0x8c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.h d15, [a0]#0"
+  -
+    input:
+      bytes: [ 0x88, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.h d0, [a15]#0"
+  -
+    input:
+      bytes: [ 0x94, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.h d0, [a0]"
+  -
+    input:
+      bytes: [ 0xc9, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.h d0, [a0]#0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.h d0, [a0+]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.h d0, [p0+r]"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x80, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.h d0, [+a0]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0x80, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.h d0, [p0+c]#0"
+  -
+    input:
+      bytes: [ 0x05, 0x00, 0x00, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.h d0, #0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x80, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.h d0, [a0]#0"
+  -
+    input:
+      bytes: [ 0xb9, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.hu d0, [a0]#0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0xc0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.hu d0, [a0+]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0xc0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.hu d0, [p0+r]"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0xc0, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.hu d0, [+a0]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0xc0, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.hu d0, [p0+c]#0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0xc0, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.hu d0, [a0]#0"
+  -
+    input:
+      bytes: [ 0x05, 0x00, 0x00, 0x0c ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.hu d0, #0"
+  -
+    input:
+      bytes: [ 0x45, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.q d0, #0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x00, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.q d0, [a0+]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0x00, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.q d0, [p0+r]"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x00, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.q d0, [+a0]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0x00, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.q d0, [p0+c]#0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x00, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.q d0, [a0]#0"
+  -
+    input:
+      bytes: [ 0x58, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d15, [sp]#0"
+  -
+    input:
+      bytes: [ 0x54, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d0, [a0]"
+  -
+    input:
+      bytes: [ 0x44, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d0, [a0+]"
+  -
+    input:
+      bytes: [ 0x4c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d15, [a0]#0"
+  -
+    input:
+      bytes: [ 0x48, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d0, [a15]#0"
+  -
+    input:
+      bytes: [ 0x19, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d0, [a0]#0"
+  -
+    input:
+      bytes: [ 0x85, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d0, #0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x00, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d0, [a0+]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0x00, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d0, [p0+r]"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x00, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d0, [+a0]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0x00, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d0, [p0+c]#0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x00, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d0, [a0]#0"
+  -
+    input:
+      bytes: [ 0x15, 0x00, 0x00, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldlcx #0"
+  -
+    input:
+      bytes: [ 0x49, 0x00, 0x00, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldlcx [a0]#0"
+  -
+    input:
+      bytes: [ 0x49, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldmst [a0+]#0, e0"
+  -
+    input:
+      bytes: [ 0x69, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldmst [p0+r], e0"
+  -
+    input:
+      bytes: [ 0xe5, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldmst #0, e0"
+  -
+    input:
+      bytes: [ 0x49, 0x00, 0x40, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldmst [+a0]#0, e0"
+  -
+    input:
+      bytes: [ 0x69, 0x00, 0x40, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldmst [p0+c]#0, e0"
+  -
+    input:
+      bytes: [ 0x49, 0x00, 0x40, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldmst [a0]#0, e0"
+  -
+    input:
+      bytes: [ 0x49, 0x00, 0x40, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "lducx [a0]#0"
+  -
+    input:
+      bytes: [ 0x15, 0x00, 0x00, 0x0c ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "lducx #0"
+  -
+    input:
+      bytes: [ 0xc5, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a0, #0"
+  -
+    input:
+      bytes: [ 0xd9, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a0, [a0]#0"
+  -
+    input:
+      bytes: [ 0x49, 0x00, 0x00, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a0, [a0]#0"
+  -
+    input:
+      bytes: [ 0xfc, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "loop a0, #0xffffffe0"
+  -
+    input:
+      bytes: [ 0xfd, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "loop a0, #0"
+  -
+    input:
+      bytes: [ 0xfd, 0x00, 0x00, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "loopu #0"
+  -
+    input:
+      bytes: [ 0x7a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "lt d15, d0, d0"
+  -
+    input:
+      bytes: [ 0xfa, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "lt d15, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x20, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "lt d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x40, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "lt d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0x20, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "lt.a d0, a0, a0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x20, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "lt.b d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x30, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "lt.bu d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x20, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "lt.h d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x30, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "lt.hu d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x30, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "lt.u d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x60, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "lt.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x20, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "lt.w d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x30, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "lt.wu d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x03, 0x00, 0x0a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd d0, d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x13, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x13, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd e0, e0, d0, #0"
+  -
+    input:
+      bytes: [ 0x03, 0x00, 0x6a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd e0, e0, d0, d0"
+  -
+    input:
+      bytes: [ 0x6b, 0x00, 0x61, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd.f d0, d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd.h e0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0x64, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd.h e0, e0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0x68, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd.h e0, e0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0x6c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd.h e0, e0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x10, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd.q d0, d0, d0u, d0u, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd.q d0, d0, d0, d0u, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x04, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd.q d0, d0, d0, d0l, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x08, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd.q d0, d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x14, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd.q d0, d0, d0l, d0l, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd.q e0, e0, d0, d0u, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x64, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd.q e0, e0, d0, d0l, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x6c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd.q e0, e0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x70, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd.q e0, e0, d0u, d0u, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x74, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd.q e0, e0, d0l, d0l, #0"
+  -
+    input:
+      bytes: [ 0x13, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd.u e0, e0, d0, #0"
+  -
+    input:
+      bytes: [ 0x03, 0x00, 0x68, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd.u e0, e0, d0, d0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0x70, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddm.h e0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0x74, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddm.h e0, e0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0x78, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddm.h e0, e0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0x7c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddm.h e0, e0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0xf0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddms.h e0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0xf4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddms.h e0, e0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0xf8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddms.h e0, e0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0xfc, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddms.h e0, e0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x78, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddr.h d0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0x30, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddr.h d0, d0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0x34, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddr.h d0, d0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0x38, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddr.h d0, d0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0x3c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddr.h d0, d0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x18, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddr.q d0, d0, d0u, d0u, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x1c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddr.q d0, d0, d0l, d0l, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0xf8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddrs.h d0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0xb0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddrs.h d0, d0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0xb4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddrs.h d0, d0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0xb8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddrs.h d0, d0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0xbc, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddrs.h d0, d0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x98, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddrs.q d0, d0, d0u, d0u, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x9c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddrs.q d0, d0, d0l, d0l, #0"
+  -
+    input:
+      bytes: [ 0x03, 0x00, 0x8a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds d0, d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x13, 0x00, 0xa0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x13, 0x00, 0xe0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds e0, e0, d0, #0"
+  -
+    input:
+      bytes: [ 0x03, 0x00, 0xea, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds e0, e0, d0, d0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0xe0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds.h e0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0xe4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds.h e0, e0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0xe8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds.h e0, e0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0xec, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds.h e0, e0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x90, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds.q d0, d0, d0u, d0u, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds.q d0, d0, d0, d0u, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x84, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds.q d0, d0, d0, d0l, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x88, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds.q d0, d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x94, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds.q d0, d0, d0l, d0l, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0xe0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds.q e0, e0, d0, d0u, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0xe4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds.q e0, e0, d0, d0l, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0xec, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds.q e0, e0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0xf0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds.q e0, e0, d0u, d0u, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0xf4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds.q e0, e0, d0l, d0l, #0"
+  -
+    input:
+      bytes: [ 0x13, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds.u d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x03, 0x00, 0x88, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds.u d0, d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x13, 0x00, 0xc0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds.u e0, e0, d0, #0"
+  -
+    input:
+      bytes: [ 0x03, 0x00, 0xe8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds.u e0, e0, d0, d0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsu.h e0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0x64, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsu.h e0, e0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0x68, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsu.h e0, e0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0x6c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsu.h e0, e0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0x70, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsum.h e0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0x74, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsum.h e0, e0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0x78, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsum.h e0, e0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0x7c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsum.h e0, e0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0xf0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsums.h e0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0xf4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsums.h e0, e0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0xf8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsums.h e0, e0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0xfc, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsums.h e0, e0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0x30, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsur.h d0, d0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0x34, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsur.h d0, d0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0x38, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsur.h d0, d0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0x3c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsur.h d0, d0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0xb0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsurs.h d0, d0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0xb4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsurs.h d0, d0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0xb8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsurs.h d0, d0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0xbc, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsurs.h d0, d0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0xe0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsus.h e0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0xe4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsus.h e0, e0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0xe8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsus.h e0, e0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0xec, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsus.h e0, e0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xa0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "max d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x40, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "max d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xa0, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "max.b d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xb0, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "max.bu d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xa0, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "max.h d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xb0, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "max.hu d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xb0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "max.u d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x60, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "max.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x4d, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "mfcr d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x80, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "min d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x00, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "min d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x80, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "min.b d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x90, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "min.bu d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x80, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "min.h d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x90, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "min.hu d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x90, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "min.u d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x20, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "min.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x02, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d0, d0"
+  -
+    input:
+      bytes: [ 0x82, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d0, #0"
+  -
+    input:
+      bytes: [ 0xd2, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov e0, #0"
+  -
+    input:
+      bytes: [ 0xda, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d15, #0"
+  -
+    input:
+      bytes: [ 0x3b, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xf0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d0, d0"
+  -
+    input:
+      bytes: [ 0xfb, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov e0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x00, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov e0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x10, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov e0, d0, d0"
+  -
+    input:
+      bytes: [ 0xa0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.a a0, #0"
+  -
+    input:
+      bytes: [ 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.a a0, d0"
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0x30, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.a a0, d0"
+  -
+    input:
+      bytes: [ 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.aa a0, a0"
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.aa a0, a0"
+  -
+    input:
+      bytes: [ 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.d d0, a0"
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0xc0, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.d d0, a0"
+  -
+    input:
+      bytes: [ 0xbb, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.u d0, #0"
+  -
+    input:
+      bytes: [ 0x7b, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh d0, #0"
+  -
+    input:
+      bytes: [ 0x91, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a0, #0"
+  -
+    input:
+      bytes: [ 0x23, 0x00, 0x0a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub d0, d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x33, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x33, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub e0, e0, d0, #0"
+  -
+    input:
+      bytes: [ 0x23, 0x00, 0x6a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub e0, e0, d0, d0"
+  -
+    input:
+      bytes: [ 0x6b, 0x00, 0x71, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub.f d0, d0, d0, d0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub.h e0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0x64, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub.h e0, e0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0x68, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub.h e0, e0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0x6c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub.h e0, e0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x10, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub.q d0, d0, d0u, d0u, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub.q d0, d0, d0, d0u, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x04, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub.q d0, d0, d0, d0l, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x08, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub.q d0, d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x14, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub.q d0, d0, d0l, d0l, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub.q e0, e0, d0, d0u, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x64, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub.q e0, e0, d0, d0l, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x6c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub.q e0, e0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x70, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub.q e0, e0, d0u, d0u, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x74, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub.q e0, e0, d0l, d0l, #0"
+  -
+    input:
+      bytes: [ 0x33, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub.u e0, e0, d0, #0"
+  -
+    input:
+      bytes: [ 0x23, 0x00, 0x68, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub.u e0, e0, d0, d0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubad.h e0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x64, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubad.h e0, e0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x68, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubad.h e0, e0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x6c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubad.h e0, e0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x70, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubadm.h e0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x74, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubadm.h e0, e0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x78, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubadm.h e0, e0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x7c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubadm.h e0, e0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xf0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubadms.h e0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xf4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubadms.h e0, e0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xf8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubadms.h e0, e0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xfc, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubadms.h e0, e0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x30, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubadr.h d0, d0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x34, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubadr.h d0, d0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x38, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubadr.h d0, d0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x3c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubadr.h d0, d0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xb0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubadrs.h d0, d0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xb4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubadrs.h d0, d0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xb8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubadrs.h d0, d0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xbc, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubadrs.h d0, d0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xe0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubads.h e0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xe4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubads.h e0, e0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xe8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubads.h e0, e0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xec, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubads.h e0, e0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0x70, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubm.h e0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0x74, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubm.h e0, e0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0x78, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubm.h e0, e0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0x7c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubm.h e0, e0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0xf0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubms.h e0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0xf4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubms.h e0, e0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0xf8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubms.h e0, e0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0xfc, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubms.h e0, e0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x78, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubr.h d0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0x30, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubr.h d0, d0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0x34, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubr.h d0, d0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0x38, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubr.h d0, d0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0x3c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubr.h d0, d0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x18, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubr.q d0, d0, d0u, d0u, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x1c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubr.q d0, d0, d0l, d0l, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0xf8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubrs.h d0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0xb0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubrs.h d0, d0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0xb4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubrs.h d0, d0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0xb8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubrs.h d0, d0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0xbc, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubrs.h d0, d0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x98, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubrs.q d0, d0, d0u, d0u, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x9c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubrs.q d0, d0, d0l, d0l, #0"
+  -
+    input:
+      bytes: [ 0x23, 0x00, 0x8a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs d0, d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x33, 0x00, 0xa0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x33, 0x00, 0xe0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs e0, e0, d0, #0"
+  -
+    input:
+      bytes: [ 0x23, 0x00, 0xea, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs e0, e0, d0, d0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0xe0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs.h e0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0xe4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs.h e0, e0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0xe8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs.h e0, e0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0xec, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs.h e0, e0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x90, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs.q d0, d0, d0u, d0u, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs.q d0, d0, d0, d0u, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x84, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs.q d0, d0, d0, d0l, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x88, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs.q d0, d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x94, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs.q d0, d0, d0l, d0l, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0xe0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs.q e0, e0, d0, d0u, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0xe4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs.q e0, e0, d0, d0l, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0xec, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs.q e0, e0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0xf0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs.q e0, e0, d0u, d0u, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0xf4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs.q e0, e0, d0l, d0l, #0"
+  -
+    input:
+      bytes: [ 0x33, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs.u d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x23, 0x00, 0x88, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs.u d0, d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x33, 0x00, 0xc0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs.u e0, e0, d0, #0"
+  -
+    input:
+      bytes: [ 0x23, 0x00, 0xe8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs.u e0, e0, d0, d0"
+  -
+    input:
+      bytes: [ 0xcd, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "mtcr #0, d0"
+  -
+    input:
+      bytes: [ 0xe2, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul d0, d0"
+  -
+    input:
+      bytes: [ 0x53, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x73, 0x00, 0x0a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x53, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul e0, d0, #0"
+  -
+    input:
+      bytes: [ 0x73, 0x00, 0x6a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul e0, d0, d0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0x41, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.f d0, d0, d0"
+  -
+    input:
+      bytes: [ 0xb3, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.h e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xb3, 0x00, 0x64, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.h e0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xb3, 0x00, 0x68, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.h e0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xb3, 0x00, 0x6c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.h e0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0x93, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.q d0, d0, d0u, #0"
+  -
+    input:
+      bytes: [ 0x93, 0x00, 0x04, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.q d0, d0, d0l, #0"
+  -
+    input:
+      bytes: [ 0x93, 0x00, 0x08, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.q d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x93, 0x00, 0x10, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.q d0, d0u, d0u, #0"
+  -
+    input:
+      bytes: [ 0x93, 0x00, 0x14, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.q d0, d0l, d0l, #0"
+  -
+    input:
+      bytes: [ 0x93, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.q e0, d0, d0u, #0"
+  -
+    input:
+      bytes: [ 0x93, 0x00, 0x64, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.q e0, d0, d0l, #0"
+  -
+    input:
+      bytes: [ 0x93, 0x00, 0x6c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.q e0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x53, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.u e0, d0, #0"
+  -
+    input:
+      bytes: [ 0x73, 0x00, 0x68, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.u e0, d0, d0"
+  -
+    input:
+      bytes: [ 0xb3, 0x00, 0x70, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulm.h e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xb3, 0x00, 0x74, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulm.h e0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xb3, 0x00, 0x78, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulm.h e0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xb3, 0x00, 0x7c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulm.h e0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0xb3, 0x00, 0xf0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulms.h e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xb3, 0x00, 0xf4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulms.h e0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xb3, 0x00, 0xf8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulms.h e0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xb3, 0x00, 0xfc, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulms.h e0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0xb3, 0x00, 0x30, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulr.h d0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xb3, 0x00, 0x34, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulr.h d0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xb3, 0x00, 0x38, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulr.h d0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xb3, 0x00, 0x3c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulr.h d0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0x93, 0x00, 0x18, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulr.q d0, d0u, d0u, #0"
+  -
+    input:
+      bytes: [ 0x93, 0x00, 0x1c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulr.q d0, d0l, d0l, #0"
+  -
+    input:
+      bytes: [ 0x53, 0x00, 0xa0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "muls d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x73, 0x00, 0x8a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "muls d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x53, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "muls.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x73, 0x00, 0x88, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "muls.u d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0x90, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "nand d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8f, 0x00, 0x20, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "nand d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x07, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "nand.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x10, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "ne d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x20, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "ne d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0x10, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "ne.a d0, a0, a0"
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0x90, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "nez.a d0, a0"
+  -
+    input:
+      bytes: [ 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "nop"
+  -
+    input:
+      bytes: [ 0x0d, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "nop"
+  -
+    input:
+      bytes: [ 0x46, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "nor d0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0xb0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "nor d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8f, 0x00, 0x60, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "nor d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x87, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "nor.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0xa6, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "or d0, d0"
+  -
+    input:
+      bytes: [ 0x96, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "or d15, #0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0xa0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "or d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8f, 0x00, 0x40, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "or d0, d0, #0"
+  -
+    input:
+      bytes: [ 0xc7, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.and.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0xc7, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.andn.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x70, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.eq d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0xe0, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.eq d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xb0, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.ge d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x60, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.ge d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xc0, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.ge.u d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x80, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.ge.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x90, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.lt d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x20, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.lt d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xa0, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.lt.u d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x40, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.lt.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x80, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.ne d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x00, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.ne d0, d0, #0"
+  -
+    input:
+      bytes: [ 0xc7, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.nor.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0xc7, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.or.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x87, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0xf0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "orn d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8f, 0x00, 0xe0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "orn d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x07, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "orn.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x6b, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "pack d0, e0, d0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "parity d0, d0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0x51, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "q31tof d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0x91, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "qseed.f d0, d0"
+  -
+    input:
+      bytes: [ 0x0d, 0x00, 0x80, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "restore d0"
+  -
+    input:
+      bytes: [ 0x00, 0x90 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "ret"
+  -
+    input:
+      bytes: [ 0x0d, 0x00, 0x80, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "ret"
+  -
+    input:
+      bytes: [ 0x00, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "rfe"
+  -
+    input:
+      bytes: [ 0x0d, 0x00, 0xc0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "rfe"
+  -
+    input:
+      bytes: [ 0x0d, 0x00, 0x40, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "rfm"
+  -
+    input:
+      bytes: [ 0x0d, 0x00, 0x40, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "rslcx"
+  -
+    input:
+      bytes: [ 0x2f, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "rstv"
+  -
+    input:
+      bytes: [ 0x32, 0x50 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "rsub d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x00, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "rsub d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x40, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "rsubs d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x60, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "rsubs.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x32, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "sat.b d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xe0, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "sat.b d0, d0"
+  -
+    input:
+      bytes: [ 0x32, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "sat.bu d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xf0, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "sat.bu d0, d0"
+  -
+    input:
+      bytes: [ 0x32, 0x20 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "sat.h d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xe0, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "sat.h d0, d0"
+  -
+    input:
+      bytes: [ 0x32, 0x30 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "sat.hu d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xf0, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "sat.hu d0, d0"
+  -
+    input:
+      bytes: [ 0x2b, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "sel d0, d0, d0, d0"
+  -
+    input:
+      bytes: [ 0xab, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "sel d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x2b, 0x00, 0x50, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "seln d0, d0, d0, d0"
+  -
+    input:
+      bytes: [ 0xab, 0x00, 0xa0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "seln d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x06, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh d0, #0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8f, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x27, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.and.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x27, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.andn.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x70, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.eq d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0xe0, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.eq d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xb0, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.ge d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x60, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.ge d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xc0, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.ge.u d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x80, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.ge.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.h d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8f, 0x00, 0x00, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.h d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x90, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.lt d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x20, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.lt d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xa0, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.lt.u d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x40, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.lt.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0xa7, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.nand.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x80, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.ne d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x00, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.ne d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x27, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.nor.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x27, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.or.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0xa7, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.orn.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0xa7, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.xnor.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0xa7, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.xor.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x86, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha d0, #0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0x10, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8f, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0x10, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha.h d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8f, 0x00, 0x20, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha.h d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "shas d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8f, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "shas d0, d0, #0"
+  -
+    input:
+      bytes: [ 0xf8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.a [sp]#0, a15"
+  -
+    input:
+      bytes: [ 0xec, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.a [a0]#0, a15"
+  -
+    input:
+      bytes: [ 0xe8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.a [a15]#0, a0"
+  -
+    input:
+      bytes: [ 0xe4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.a [a0+], a0"
+  -
+    input:
+      bytes: [ 0xf4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.a [a0], a0"
+  -
+    input:
+      bytes: [ 0xb5, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.a [a0]#0, a0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x80, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.a [a0+]#0, a0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x80, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.a [p0+r], a0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x80, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.a [+a0]#0, a0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x80, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.a [p0+c]#0, a0"
+  -
+    input:
+      bytes: [ 0xa5, 0x00, 0x00, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.a #0, a0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x80, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.a [a0]#0, a0"
+  -
+    input:
+      bytes: [ 0x34, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [a0], d0"
+  -
+    input:
+      bytes: [ 0x28, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [a15]#0, d0"
+  -
+    input:
+      bytes: [ 0x2c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [a0]#0, d15"
+  -
+    input:
+      bytes: [ 0x24, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [a0+], d0"
+  -
+    input:
+      bytes: [ 0xe9, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [a0]#0, d0"
+  -
+    input:
+      bytes: [ 0x25, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b #0, d0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [a0+]#0, d0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [p0+r], d0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [+a0]#0, d0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [p0+c]#0, d0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x00, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [a0]#0, d0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x40, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.d [a0+]#0, e0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x40, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.d [p0+r], e0"
+  -
+    input:
+      bytes: [ 0xa5, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.d #0, e0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x40, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.d [+a0]#0, e0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x40, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.d [p0+c]#0, e0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x40, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.d [a0]#0, e0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0xc0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.da [a0+]#0, p0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0xc0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.da [p0+r], p0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0xc0, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.da [+a0]#0, p0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0xc0, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.da [p0+c]#0, p0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0xc0, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.da [a0]#0, p0"
+  -
+    input:
+      bytes: [ 0xa5, 0x00, 0x00, 0x0c ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.da #0, p0"
+  -
+    input:
+      bytes: [ 0xa4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [a0+], d0"
+  -
+    input:
+      bytes: [ 0xa8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [a15]#0, d0"
+  -
+    input:
+      bytes: [ 0xac, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [a0]#0, d15"
+  -
+    input:
+      bytes: [ 0xb4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [a0], d0"
+  -
+    input:
+      bytes: [ 0xf9, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [a0]#0, d0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [a0+]#0, d0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [p0+r], d0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x80, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [+a0]#0, d0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x80, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [p0+c]#0, d0"
+  -
+    input:
+      bytes: [ 0x25, 0x00, 0x00, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h #0, d0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x80, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [a0]#0, d0"
+  -
+    input:
+      bytes: [ 0x65, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.q #0, d0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x00, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.q [a0+]#0, d0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x00, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.q [p0+r], d0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x00, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.q [+a0]#0, d0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x00, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.q [p0+c]#0, d0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x00, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.q [a0]#0, d0"
+  -
+    input:
+      bytes: [ 0xd5, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.t #0, #0, #0"
+  -
+    input:
+      bytes: [ 0x78, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w [sp]#0, d15"
+  -
+    input:
+      bytes: [ 0x74, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w [a0], d0"
+  -
+    input:
+      bytes: [ 0x64, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w [a0+], d0"
+  -
+    input:
+      bytes: [ 0x68, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w [a15]#0, d0"
+  -
+    input:
+      bytes: [ 0x6c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w [a0]#0, d15"
+  -
+    input:
+      bytes: [ 0x59, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w [a0]#0, d0"
+  -
+    input:
+      bytes: [ 0xa5, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w #0, d0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x00, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w [a0+]#0, d0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x00, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w [p0+r], d0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x00, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w [+a0]#0, d0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x00, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w [p0+c]#0, d0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x00, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w [a0]#0, d0"
+  -
+    input:
+      bytes: [ 0x15, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "stlcx #0"
+  -
+    input:
+      bytes: [ 0x49, 0x00, 0x80, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "stlcx [a0]#0"
+  -
+    input:
+      bytes: [ 0x15, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "stucx #0"
+  -
+    input:
+      bytes: [ 0x49, 0x00, 0xc0, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "stucx [a0]#0"
+  -
+    input:
+      bytes: [ 0x52, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub d0, d15, d0"
+  -
+    input:
+      bytes: [ 0x5a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub d15, d0, d0"
+  -
+    input:
+      bytes: [ 0xa2, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub.a sp, #0"
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub.a a0, a0, a0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x80, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub.b d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x6b, 0x00, 0x31, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub.f d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x80, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub.h d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xd0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "subc d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x62, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "subs d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xa0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "subs d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xa0, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "subs.h d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xb0, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "subs.hu d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xb0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "subs.u d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xc0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "subx d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0d, 0x00, 0x00, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "svlcx"
+  -
+    input:
+      bytes: [ 0x49, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "swap.w [a0+]#0, d0"
+  -
+    input:
+      bytes: [ 0x69, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "swap.w [p0+r], d0"
+  -
+    input:
+      bytes: [ 0xe5, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "swap.w #0, d0"
+  -
+    input:
+      bytes: [ 0x49, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "swap.w [+a0]#0, d0"
+  -
+    input:
+      bytes: [ 0x69, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "swap.w [p0+c]#0, d0"
+  -
+    input:
+      bytes: [ 0x49, 0x00, 0x00, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "swap.w [a0]#0, d0"
+  -
+    input:
+      bytes: [ 0x69, 0x00, 0x00, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "swap.w [p0+i], d0"
+  -
+    input:
+      bytes: [ 0x49, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "swapmsk.w [a0+]#0, e0"
+  -
+    input:
+      bytes: [ 0x69, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "swapmsk.w [p0+r], e0"
+  -
+    input:
+      bytes: [ 0x49, 0x00, 0x80, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "swapmsk.w [+a0]#0, e0"
+  -
+    input:
+      bytes: [ 0x69, 0x00, 0x80, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "swapmsk.w [p0+c]#0, e0"
+  -
+    input:
+      bytes: [ 0x49, 0x00, 0x80, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "swapmsk.w [a0]#0, e0"
+  -
+    input:
+      bytes: [ 0x69, 0x00, 0x80, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "swapmsk.w [p0+i], e0"
+  -
+    input:
+      bytes: [ 0xad, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "syscall #0"
+  -
+    input:
+      bytes: [ 0x75, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "tlbdemap d0"
+  -
+    input:
+      bytes: [ 0x75, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "tlbflush.a"
+  -
+    input:
+      bytes: [ 0x75, 0x00, 0x50, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "tlbflush.b"
+  -
+    input:
+      bytes: [ 0x75, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "tlbmap e0"
+  -
+    input:
+      bytes: [ 0x75, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "tlbprobe.a d0"
+  -
+    input:
+      bytes: [ 0x75, 0x00, 0x90, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "tlbprobe.i d0"
+  -
+    input:
+      bytes: [ 0x0d, 0x00, 0x40, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "trapsv"
+  -
+    input:
+      bytes: [ 0x0d, 0x00, 0x00, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "trapv"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "unpack e0, d0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0xc1, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "updfl d0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0x61, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "utof d0, d0"
+  -
+    input:
+      bytes: [ 0x0d, 0x00, 0x80, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "wait"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0xd0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "xnor d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8f, 0x00, 0xa0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "xnor d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x07, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "xnor.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0xc6, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor d0, d0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0xc0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8f, 0x00, 0x80, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xf0, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor.eq d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0xe0, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor.eq d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x30, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor.ge d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x60, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor.ge d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x40, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor.ge.u d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x80, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor.ge.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x10, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor.lt d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x20, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor.lt d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x20, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor.lt.u d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x40, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor.lt.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x00, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor.ne d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x00, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor.ne d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x07, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_161" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor.t d0, d0, #0, d0, #0"
diff --git a/tests/MC/TriCore/tc162.s.yaml b/tests/MC/TriCore/tc162.s.yaml
new file mode 100644
index 000000000..d15e727f2
--- /dev/null
+++ b/tests/MC/TriCore/tc162.s.yaml
@@ -0,0 +1,7579 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xc0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "abs d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xc0, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "abs.b d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xc0, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "abs.h d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xe0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "absdif d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0xc0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "absdif d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xe0, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "absdif.b d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xe0, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "absdif.h d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xf0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "absdifs d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0xe0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "absdifs d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xf0, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "absdifs.h d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xd0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "abss d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xd0, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "abss.h d0, d0"
+  -
+    input:
+      bytes: [ 0x12, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d0, d15, d0"
+  -
+    input:
+      bytes: [ 0x92, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d0, d15, #0"
+  -
+    input:
+      bytes: [ 0x1a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d15, d0, d0"
+  -
+    input:
+      bytes: [ 0x42, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d0, d0"
+  -
+    input:
+      bytes: [ 0x9a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d15, d0, #0"
+  -
+    input:
+      bytes: [ 0xc2, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x30, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add.a a0, a0"
+  -
+    input:
+      bytes: [ 0xb0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add.a a0, #0"
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0x10, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add.a a0, a0, a0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add.b d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x6b, 0x00, 0x21, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add.f d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x00, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "add.h d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x50, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addc d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0xa0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addc d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x1b, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addi d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x9b, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addih d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x11, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addih.a a0, a0, #0"
+  -
+    input:
+      bytes: [ 0x22, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "adds d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "adds d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "adds d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x20, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "adds.h d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x30, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "adds.hu d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x30, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "adds.u d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "adds.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x10, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addsc.a a0, a0, d15, #0"
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0x00, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addsc.a a0, a0, d0, #0"
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0x20, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addsc.at a0, a0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addx d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "addx d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x26, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d0, d0"
+  -
+    input:
+      bytes: [ 0x16, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d15, #0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8f, 0x00, 0x00, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x47, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.and.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x47, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.andn.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x00, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.eq d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.eq d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x40, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.ge d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x80, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.ge d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x50, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.ge.u d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0xa0, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.ge.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x20, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.lt d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x40, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.lt d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x30, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.lt.u d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x60, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.lt.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x10, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.ne d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x20, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.ne d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x47, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.nor.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x47, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.or.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x87, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "and.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0xe0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "andn d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8f, 0x00, 0xc0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "andn d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x87, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "andn.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0xe0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "bisr #0"
+  -
+    input:
+      bytes: [ 0xad, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "bisr #0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0x10, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "bmerge d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0x90, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "bsplit e0, d0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x80, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachea.i [a0+]#0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x80, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachea.i [p0+r]"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x80, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachea.i [+a0]#0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x80, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachea.i [p0+c]#0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x80, 0x0b ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachea.i [a0]#0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x00, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachea.w [a0+]#0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x00, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachea.w [p0+r]"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x00, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachea.w [+a0]#0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x00, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachea.w [p0+c]#0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x00, 0x0b ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachea.w [a0]#0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x40, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachea.wi [a0+]#0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x40, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachea.wi [p0+r]"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x40, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachea.wi [+a0]#0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x40, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachea.wi [p0+c]#0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x40, 0x0b ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachea.wi [a0]#0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x80, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachei.i [a0+]#0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x80, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachei.i [+a0]#0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x80, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachei.i [a0]#0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0xc0, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachei.w [a0+]#0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0xc0, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachei.w [+a0]#0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0xc0, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachei.w [a0]#0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0xc0, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachei.wi [a0+]#0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0xc0, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachei.wi [+a0]#0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0xc0, 0x0b ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "cachei.wi [a0]#0"
+  -
+    input:
+      bytes: [ 0x8a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "cadd d0, d15, #0"
+  -
+    input:
+      bytes: [ 0x2b, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "cadd d0, d0, d0, d0"
+  -
+    input:
+      bytes: [ 0xab, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "cadd d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0xca, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "caddn d0, d15, #0"
+  -
+    input:
+      bytes: [ 0x2b, 0x00, 0x10, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "caddn d0, d0, d0, d0"
+  -
+    input:
+      bytes: [ 0xab, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "caddn d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x5c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0"
+  -
+    input:
+      bytes: [ 0x6d, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "call #0"
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "calla #0"
+  -
+    input:
+      bytes: [ 0x2d, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "calli a0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0xc0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "clo d0, d0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0xd0, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "clo.h d0, d0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0xd0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "cls d0, d0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0xe0, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "cls.h d0, d0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0xb0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "clz d0, d0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0xc0, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "clz.h d0, d0"
+  -
+    input:
+      bytes: [ 0x2a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmov d0, d15, d0"
+  -
+    input:
+      bytes: [ 0xaa, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmov d0, d15, #0"
+  -
+    input:
+      bytes: [ 0x6a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmovn d0, d15, d0"
+  -
+    input:
+      bytes: [ 0xea, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmovn d0, d15, #0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmp.f d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x49, 0x00, 0xc0, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpswap.w [a0]#0, e0"
+  -
+    input:
+      bytes: [ 0x69, 0x00, 0xc0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpswap.w [p0+r], e0"
+  -
+    input:
+      bytes: [ 0x69, 0x00, 0xc0, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpswap.w [p0+c]#0, e0"
+  -
+    input:
+      bytes: [ 0x49, 0x00, 0xc0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpswap.w [a0+]#0, e0"
+  -
+    input:
+      bytes: [ 0x49, 0x00, 0xc0, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpswap.w [+a0]#0, e0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "crc32.b d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0x30, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "crc32b.w d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0x70, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "crc32l.w d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x6b, 0x00, 0x10, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "crcn d0, d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x2b, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "csub d0, d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x2b, 0x00, 0x30, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "csubn d0, d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x00, 0xa0 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "debug"
+  -
+    input:
+      bytes: [ 0x0d, 0x00, 0x00, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "debug"
+  -
+    input:
+      bytes: [ 0x77, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "dextr d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x17, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "dextr d0, d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0d, 0x00, 0x40, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "disable"
+  -
+    input:
+      bytes: [ 0x0d, 0x00, 0xc0, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "disable d0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0x01, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "div e0, d0, d0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0x11, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "div.u e0, d0, d0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0x51, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "div.f d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0d, 0x00, 0x80, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "dsync"
+  -
+    input:
+      bytes: [ 0x6b, 0x00, 0xd0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "dvadj e0, e0, d0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0xa0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "dvinit e0, d0, d0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0xa0, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "dvinit.b e0, d0, d0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0xa0, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "dvinit.bu e0, d0, d0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0xa0, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "dvinit.h e0, d0, d0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0xa0, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "dvinit.hu e0, d0, d0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0xa0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "dvinit.u e0, d0, d0"
+  -
+    input:
+      bytes: [ 0x6b, 0x00, 0xf0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "dvstep e0, e0, d0"
+  -
+    input:
+      bytes: [ 0x6b, 0x00, 0xe0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "dvstep.u e0, e0, d0"
+  -
+    input:
+      bytes: [ 0x0d, 0x00, 0x00, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "enable"
+  -
+    input:
+      bytes: [ 0x3a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "eq d15, d0, d0"
+  -
+    input:
+      bytes: [ 0xba, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "eq d15, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x00, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "eq d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x00, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "eq d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "eq.a d0, a0, a0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x00, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "eq.b d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x00, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "eq.h d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x00, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "eq.w d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x60, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "eqany.b d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0xc0, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "eqany.b d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x60, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "eqany.h d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0xc0, 0x0e ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "eqany.h d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0x80, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "eqz.a d0, a0"
+  -
+    input:
+      bytes: [ 0x17, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr d0, d0, e0"
+  -
+    input:
+      bytes: [ 0x37, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr d0, d0, #0, #0"
+  -
+    input:
+      bytes: [ 0x57, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x17, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d0, d0, e0"
+  -
+    input:
+      bytes: [ 0x37, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d0, d0, #0, #0"
+  -
+    input:
+      bytes: [ 0x57, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "extr.u d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x61, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcall #0"
+  -
+    input:
+      bytes: [ 0xe1, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcalla #0"
+  -
+    input:
+      bytes: [ 0x2d, 0x00, 0x10, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "fcalli a0"
+  -
+    input:
+      bytes: [ 0x00, 0x70 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "fret"
+  -
+    input:
+      bytes: [ 0x0d, 0x00, 0xc0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "fret"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0x01, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ftoi d0, d0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0x11, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ftoq31 d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0x21, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ftou d0, d0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0x31, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ftoiz d0, d0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0x81, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ftoq31z d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0x71, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ftouz d0, d0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0x51, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ftohp d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x40, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ge d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x80, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ge d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0x30, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ge.a d0, a0, a0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x50, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ge.u d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0xa0, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ge.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0x41, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "hptof d0, d0"
+  -
+    input:
+      bytes: [ 0x37, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "imask e0, d0, #0, #0"
+  -
+    input:
+      bytes: [ 0x57, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "imask e0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0xb7, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "imask e0, #0, #0, #0"
+  -
+    input:
+      bytes: [ 0xd7, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "imask e0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x67, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ins.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x17, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d0, d0, d0, e0"
+  -
+    input:
+      bytes: [ 0x37, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d0, d0, d0, #0, #0"
+  -
+    input:
+      bytes: [ 0x57, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d0, d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x97, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d0, d0, #0, e0"
+  -
+    input:
+      bytes: [ 0xb7, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d0, d0, #0, #0, #0"
+  -
+    input:
+      bytes: [ 0xd7, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insert d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x67, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "insn.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0d, 0x00, 0xc0, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "isync"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0x41, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "itof d0, d0"
+  -
+    input:
+      bytes: [ 0x6b, 0x00, 0xa0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ixmax e0, e0, d0"
+  -
+    input:
+      bytes: [ 0x6b, 0x00, 0xb0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ixmax.u e0, e0, d0"
+  -
+    input:
+      bytes: [ 0x6b, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ixmin e0, e0, d0"
+  -
+    input:
+      bytes: [ 0x6b, 0x00, 0x90, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ixmin.u e0, e0, d0"
+  -
+    input:
+      bytes: [ 0x3c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0"
+  -
+    input:
+      bytes: [ 0x1d, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "j #0"
+  -
+    input:
+      bytes: [ 0x9d, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ja #0"
+  -
+    input:
+      bytes: [ 0xbe, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d0, #0x20"
+  -
+    input:
+      bytes: [ 0x9e, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, #0, #0x20"
+  -
+    input:
+      bytes: [ 0x3e, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, d0, #0"
+  -
+    input:
+      bytes: [ 0x1e, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d15, #0, #0"
+  -
+    input:
+      bytes: [ 0x5f, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d0, d0, #0"
+  -
+    input:
+      bytes: [ 0xdf, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq d0, #0, #0"
+  -
+    input:
+      bytes: [ 0x7d, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jeq.a a0, a0, #0"
+  -
+    input:
+      bytes: [ 0x7f, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jge d0, d0, #0"
+  -
+    input:
+      bytes: [ 0xff, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jge d0, #0, #0"
+  -
+    input:
+      bytes: [ 0x7f, 0x00, 0x00, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jge.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0xff, 0x00, 0x00, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jge.u d0, #0, #0"
+  -
+    input:
+      bytes: [ 0xce, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jgez d0, #0"
+  -
+    input:
+      bytes: [ 0x4e, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jgtz d0, #0"
+  -
+    input:
+      bytes: [ 0xdc, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ji a0"
+  -
+    input:
+      bytes: [ 0x2d, 0x00, 0x30, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ji a0"
+  -
+    input:
+      bytes: [ 0x5d, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jl #0"
+  -
+    input:
+      bytes: [ 0xdd, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jla #0"
+  -
+    input:
+      bytes: [ 0x8e, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlez d0, #0"
+  -
+    input:
+      bytes: [ 0x2d, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jli a0"
+  -
+    input:
+      bytes: [ 0x3f, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt d0, d0, #0"
+  -
+    input:
+      bytes: [ 0xbf, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt d0, #0, #0"
+  -
+    input:
+      bytes: [ 0x3f, 0x00, 0x00, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0xbf, 0x00, 0x00, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jlt.u d0, #0, #0"
+  -
+    input:
+      bytes: [ 0x0e, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jltz d0, #0"
+  -
+    input:
+      bytes: [ 0xfe, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, d0, #0x20"
+  -
+    input:
+      bytes: [ 0xde, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, #0, #0x20"
+  -
+    input:
+      bytes: [ 0x7e, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, d0, #0"
+  -
+    input:
+      bytes: [ 0x5e, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d15, #0, #0"
+  -
+    input:
+      bytes: [ 0x5f, 0x00, 0x00, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d0, d0, #0"
+  -
+    input:
+      bytes: [ 0xdf, 0x00, 0x00, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne d0, #0, #0"
+  -
+    input:
+      bytes: [ 0x7d, 0x00, 0x00, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jne.a a0, a0, #0"
+  -
+    input:
+      bytes: [ 0x1f, 0x00, 0x00, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jned d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x9f, 0x00, 0x00, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jned d0, #0, #0"
+  -
+    input:
+      bytes: [ 0x1f, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnei d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x9f, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnei d0, #0, #0"
+  -
+    input:
+      bytes: [ 0xee, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz d15, #0"
+  -
+    input:
+      bytes: [ 0xf6, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz d0, #0"
+  -
+    input:
+      bytes: [ 0x7c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz.a a0, #0"
+  -
+    input:
+      bytes: [ 0xbd, 0x00, 0x00, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz.a a0, #0"
+  -
+    input:
+      bytes: [ 0xae, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz.t d15, #0, #0"
+  -
+    input:
+      bytes: [ 0x6f, 0x00, 0x00, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jnz.t d0, #0, #0"
+  -
+    input:
+      bytes: [ 0x6e, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d15, #0"
+  -
+    input:
+      bytes: [ 0x76, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz d0, #0"
+  -
+    input:
+      bytes: [ 0xbc, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.a a0, #0"
+  -
+    input:
+      bytes: [ 0xbd, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.a a0, #0"
+  -
+    input:
+      bytes: [ 0x2e, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.t d15, #0, #0"
+  -
+    input:
+      bytes: [ 0x6f, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "jz.t d0, #0, #0"
+  -
+    input:
+      bytes: [ 0xd8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.a a15, [sp]#0"
+  -
+    input:
+      bytes: [ 0xc8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.a a0, [a15]#0"
+  -
+    input:
+      bytes: [ 0xcc, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.a a15, [a0]#0"
+  -
+    input:
+      bytes: [ 0xc4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.a a0, [a0+]"
+  -
+    input:
+      bytes: [ 0xd4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.a a0, [a0]"
+  -
+    input:
+      bytes: [ 0x99, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.a a0, [a0]#0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x80, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.a a0, [a0+]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0x80, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.a a0, [p0+r]"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x80, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.a a0, [+a0]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0x80, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.a a0, [p0+c]#0"
+  -
+    input:
+      bytes: [ 0x85, 0x00, 0x00, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.a a0, #0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x80, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.a a0, [a0]#0"
+  -
+    input:
+      bytes: [ 0x79, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.b d0, [a0]#0"
+  -
+    input:
+      bytes: [ 0x05, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.b d0, #0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.b d0, [a0+]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.b d0, [p0+r]"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.b d0, [+a0]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.b d0, [p0+c]#0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x00, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.b d0, [a0]#0"
+  -
+    input:
+      bytes: [ 0x14, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d0, [a0]"
+  -
+    input:
+      bytes: [ 0x0c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d15, [a0]#0"
+  -
+    input:
+      bytes: [ 0x08, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d0, [a15]#0"
+  -
+    input:
+      bytes: [ 0x04, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d0, [a0+]"
+  -
+    input:
+      bytes: [ 0x39, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d0, [a0]#0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d0, [a0+]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d0, [p0+r]"
+  -
+    input:
+      bytes: [ 0x05, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d0, #0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x40, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d0, [+a0]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0x40, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d0, [p0+c]#0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x40, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.bu d0, [a0]#0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x40, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.d e0, [a0+]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0x40, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.d e0, [p0+r]"
+  -
+    input:
+      bytes: [ 0x85, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.d e0, #0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x40, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.d e0, [+a0]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0x40, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.d e0, [p0+c]#0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x40, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.d e0, [a0]#0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0xc0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.da p0, [a0+]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0xc0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.da p0, [p0+r]"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0xc0, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.da p0, [+a0]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0xc0, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.da p0, [p0+c]#0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0xc0, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.da p0, [a0]#0"
+  -
+    input:
+      bytes: [ 0x85, 0x00, 0x00, 0x0c ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.da p0, #0"
+  -
+    input:
+      bytes: [ 0x84, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.h d0, [a0+]"
+  -
+    input:
+      bytes: [ 0x8c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.h d15, [a0]#0"
+  -
+    input:
+      bytes: [ 0x88, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.h d0, [a15]#0"
+  -
+    input:
+      bytes: [ 0x94, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.h d0, [a0]"
+  -
+    input:
+      bytes: [ 0xc9, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.h d0, [a0]#0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.h d0, [a0+]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.h d0, [p0+r]"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x80, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.h d0, [+a0]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0x80, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.h d0, [p0+c]#0"
+  -
+    input:
+      bytes: [ 0x05, 0x00, 0x00, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.h d0, #0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x80, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.h d0, [a0]#0"
+  -
+    input:
+      bytes: [ 0xb9, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.hu d0, [a0]#0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0xc0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.hu d0, [a0+]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0xc0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.hu d0, [p0+r]"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0xc0, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.hu d0, [+a0]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0xc0, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.hu d0, [p0+c]#0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0xc0, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.hu d0, [a0]#0"
+  -
+    input:
+      bytes: [ 0x05, 0x00, 0x00, 0x0c ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.hu d0, #0"
+  -
+    input:
+      bytes: [ 0x45, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.q d0, #0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x00, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.q d0, [a0+]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0x00, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.q d0, [p0+r]"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x00, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.q d0, [+a0]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0x00, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.q d0, [p0+c]#0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x00, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.q d0, [a0]#0"
+  -
+    input:
+      bytes: [ 0x58, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d15, [sp]#0"
+  -
+    input:
+      bytes: [ 0x54, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d0, [a0]"
+  -
+    input:
+      bytes: [ 0x44, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d0, [a0+]"
+  -
+    input:
+      bytes: [ 0x4c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d15, [a0]#0"
+  -
+    input:
+      bytes: [ 0x48, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d0, [a15]#0"
+  -
+    input:
+      bytes: [ 0x19, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d0, [a0]#0"
+  -
+    input:
+      bytes: [ 0x85, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d0, #0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x00, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d0, [a0+]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0x00, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d0, [p0+r]"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x00, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d0, [+a0]#0"
+  -
+    input:
+      bytes: [ 0x29, 0x00, 0x00, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d0, [p0+c]#0"
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x00, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ld.w d0, [a0]#0"
+  -
+    input:
+      bytes: [ 0x15, 0x00, 0x00, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldlcx #0"
+  -
+    input:
+      bytes: [ 0x49, 0x00, 0x00, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldlcx [a0]#0"
+  -
+    input:
+      bytes: [ 0x49, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldmst [a0+]#0, e0"
+  -
+    input:
+      bytes: [ 0x69, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldmst [p0+r], e0"
+  -
+    input:
+      bytes: [ 0xe5, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldmst #0, e0"
+  -
+    input:
+      bytes: [ 0x49, 0x00, 0x40, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldmst [+a0]#0, e0"
+  -
+    input:
+      bytes: [ 0x69, 0x00, 0x40, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldmst [p0+c]#0, e0"
+  -
+    input:
+      bytes: [ 0x49, 0x00, 0x40, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ldmst [a0]#0, e0"
+  -
+    input:
+      bytes: [ 0x49, 0x00, 0x40, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lducx [a0]#0"
+  -
+    input:
+      bytes: [ 0x15, 0x00, 0x00, 0x0c ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lducx #0"
+  -
+    input:
+      bytes: [ 0xc5, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a0, #0"
+  -
+    input:
+      bytes: [ 0xd9, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a0, [a0]#0"
+  -
+    input:
+      bytes: [ 0x49, 0x00, 0x00, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lea a0, [a0]#0"
+  -
+    input:
+      bytes: [ 0xc5, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lha a0, #0"
+  -
+    input:
+      bytes: [ 0xfc, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "loop a0, #0xffffffe0"
+  -
+    input:
+      bytes: [ 0xfd, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "loop a0, #0"
+  -
+    input:
+      bytes: [ 0xfd, 0x00, 0x00, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "loopu #0"
+  -
+    input:
+      bytes: [ 0x7a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lt d15, d0, d0"
+  -
+    input:
+      bytes: [ 0xfa, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lt d15, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x20, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lt d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x40, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lt d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0x20, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lt.a d0, a0, a0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x20, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lt.b d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x30, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lt.bu d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x20, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lt.h d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x30, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lt.hu d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x30, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lt.u d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x60, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lt.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x20, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lt.w d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x30, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "lt.wu d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x03, 0x00, 0x0a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd d0, d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x13, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x13, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd e0, e0, d0, #0"
+  -
+    input:
+      bytes: [ 0x03, 0x00, 0x6a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd e0, e0, d0, d0"
+  -
+    input:
+      bytes: [ 0x6b, 0x00, 0x61, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd.f d0, d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd.h e0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0x64, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd.h e0, e0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0x68, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd.h e0, e0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0x6c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd.h e0, e0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x10, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd.q d0, d0, d0u, d0u, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd.q d0, d0, d0, d0u, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x04, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd.q d0, d0, d0, d0l, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x08, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd.q d0, d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x14, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd.q d0, d0, d0l, d0l, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd.q e0, e0, d0, d0u, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x64, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd.q e0, e0, d0, d0l, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x6c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd.q e0, e0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x70, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd.q e0, e0, d0u, d0u, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x74, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd.q e0, e0, d0l, d0l, #0"
+  -
+    input:
+      bytes: [ 0x13, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd.u e0, e0, d0, #0"
+  -
+    input:
+      bytes: [ 0x03, 0x00, 0x68, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "madd.u e0, e0, d0, d0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0x70, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddm.h e0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0x74, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddm.h e0, e0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0x78, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddm.h e0, e0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0x7c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddm.h e0, e0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0xf0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddms.h e0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0xf4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddms.h e0, e0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0xf8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddms.h e0, e0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0xfc, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddms.h e0, e0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x78, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddr.h d0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0x30, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddr.h d0, d0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0x34, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddr.h d0, d0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0x38, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddr.h d0, d0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0x3c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddr.h d0, d0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x18, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddr.q d0, d0, d0u, d0u, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x1c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddr.q d0, d0, d0l, d0l, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0xf8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddrs.h d0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0xb0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddrs.h d0, d0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0xb4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddrs.h d0, d0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0xb8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddrs.h d0, d0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0xbc, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddrs.h d0, d0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x98, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddrs.q d0, d0, d0u, d0u, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x9c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddrs.q d0, d0, d0l, d0l, #0"
+  -
+    input:
+      bytes: [ 0x03, 0x00, 0x8a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds d0, d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x13, 0x00, 0xa0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x13, 0x00, 0xe0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds e0, e0, d0, #0"
+  -
+    input:
+      bytes: [ 0x03, 0x00, 0xea, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds e0, e0, d0, d0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0xe0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds.h e0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0xe4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds.h e0, e0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0xe8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds.h e0, e0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0x83, 0x00, 0xec, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds.h e0, e0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x90, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds.q d0, d0, d0u, d0u, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds.q d0, d0, d0, d0u, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x84, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds.q d0, d0, d0, d0l, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x88, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds.q d0, d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0x94, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds.q d0, d0, d0l, d0l, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0xe0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds.q e0, e0, d0, d0u, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0xe4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds.q e0, e0, d0, d0l, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0xec, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds.q e0, e0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0xf0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds.q e0, e0, d0u, d0u, #0"
+  -
+    input:
+      bytes: [ 0x43, 0x00, 0xf4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds.q e0, e0, d0l, d0l, #0"
+  -
+    input:
+      bytes: [ 0x13, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds.u d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x03, 0x00, 0x88, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds.u d0, d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x13, 0x00, 0xc0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds.u e0, e0, d0, #0"
+  -
+    input:
+      bytes: [ 0x03, 0x00, 0xe8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "madds.u e0, e0, d0, d0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsu.h e0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0x64, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsu.h e0, e0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0x68, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsu.h e0, e0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0x6c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsu.h e0, e0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0x70, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsum.h e0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0x74, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsum.h e0, e0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0x78, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsum.h e0, e0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0x7c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsum.h e0, e0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0xf0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsums.h e0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0xf4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsums.h e0, e0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0xf8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsums.h e0, e0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0xfc, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsums.h e0, e0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0x30, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsur.h d0, d0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0x34, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsur.h d0, d0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0x38, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsur.h d0, d0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0x3c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsur.h d0, d0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0xb0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsurs.h d0, d0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0xb4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsurs.h d0, d0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0xb8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsurs.h d0, d0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0xbc, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsurs.h d0, d0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0xe0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsus.h e0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0xe4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsus.h e0, e0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0xe8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsus.h e0, e0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xc3, 0x00, 0xec, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "maddsus.h e0, e0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xa0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "max d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x40, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "max d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xa0, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "max.b d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xb0, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "max.bu d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xa0, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "max.h d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xb0, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "max.hu d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xb0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "max.u d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x60, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "max.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x4d, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mfcr d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x80, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "min d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x00, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "min d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x80, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "min.b d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x90, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "min.bu d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x80, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "min.h d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x90, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "min.hu d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x90, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "min.u d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x20, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "min.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x02, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d0, d0"
+  -
+    input:
+      bytes: [ 0x82, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d0, #0"
+  -
+    input:
+      bytes: [ 0xd2, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov e0, #0"
+  -
+    input:
+      bytes: [ 0xda, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d15, #0"
+  -
+    input:
+      bytes: [ 0x3b, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xf0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov d0, d0"
+  -
+    input:
+      bytes: [ 0xfb, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov e0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x00, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov e0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x10, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov e0, d0, d0"
+  -
+    input:
+      bytes: [ 0xa0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.a a0, #0"
+  -
+    input:
+      bytes: [ 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.a a0, d0"
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0x30, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.a a0, d0"
+  -
+    input:
+      bytes: [ 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.aa a0, a0"
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.aa a0, a0"
+  -
+    input:
+      bytes: [ 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.d d0, a0"
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0xc0, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.d d0, a0"
+  -
+    input:
+      bytes: [ 0xbb, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov.u d0, #0"
+  -
+    input:
+      bytes: [ 0x7b, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh d0, #0"
+  -
+    input:
+      bytes: [ 0x91, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "movh.a a0, #0"
+  -
+    input:
+      bytes: [ 0x23, 0x00, 0x0a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub d0, d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x33, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x33, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub e0, e0, d0, #0"
+  -
+    input:
+      bytes: [ 0x23, 0x00, 0x6a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub e0, e0, d0, d0"
+  -
+    input:
+      bytes: [ 0x6b, 0x00, 0x71, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub.f d0, d0, d0, d0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub.h e0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0x64, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub.h e0, e0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0x68, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub.h e0, e0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0x6c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub.h e0, e0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x10, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub.q d0, d0, d0u, d0u, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub.q d0, d0, d0, d0u, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x04, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub.q d0, d0, d0, d0l, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x08, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub.q d0, d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x14, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub.q d0, d0, d0l, d0l, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub.q e0, e0, d0, d0u, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x64, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub.q e0, e0, d0, d0l, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x6c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub.q e0, e0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x70, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub.q e0, e0, d0u, d0u, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x74, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub.q e0, e0, d0l, d0l, #0"
+  -
+    input:
+      bytes: [ 0x33, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub.u e0, e0, d0, #0"
+  -
+    input:
+      bytes: [ 0x23, 0x00, 0x68, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "msub.u e0, e0, d0, d0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubad.h e0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x64, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubad.h e0, e0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x68, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubad.h e0, e0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x6c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubad.h e0, e0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x70, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubadm.h e0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x74, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubadm.h e0, e0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x78, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubadm.h e0, e0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x7c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubadm.h e0, e0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xf0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubadms.h e0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xf4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubadms.h e0, e0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xf8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubadms.h e0, e0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xfc, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubadms.h e0, e0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x30, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubadr.h d0, d0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x34, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubadr.h d0, d0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x38, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubadr.h d0, d0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0x3c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubadr.h d0, d0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xb0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubadrs.h d0, d0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xb4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubadrs.h d0, d0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xb8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubadrs.h d0, d0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xbc, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubadrs.h d0, d0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xe0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubads.h e0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xe4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubads.h e0, e0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xe8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubads.h e0, e0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xe3, 0x00, 0xec, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubads.h e0, e0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0x70, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubm.h e0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0x74, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubm.h e0, e0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0x78, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubm.h e0, e0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0x7c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubm.h e0, e0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0xf0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubms.h e0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0xf4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubms.h e0, e0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0xf8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubms.h e0, e0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0xfc, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubms.h e0, e0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x78, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubr.h d0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0x30, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubr.h d0, d0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0x34, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubr.h d0, d0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0x38, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubr.h d0, d0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0x3c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubr.h d0, d0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x18, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubr.q d0, d0, d0u, d0u, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x1c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubr.q d0, d0, d0l, d0l, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0xf8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubrs.h d0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0xb0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubrs.h d0, d0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0xb4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubrs.h d0, d0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0xb8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubrs.h d0, d0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0xbc, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubrs.h d0, d0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x98, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubrs.q d0, d0, d0u, d0u, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x9c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubrs.q d0, d0, d0l, d0l, #0"
+  -
+    input:
+      bytes: [ 0x23, 0x00, 0x8a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs d0, d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x33, 0x00, 0xa0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x33, 0x00, 0xe0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs e0, e0, d0, #0"
+  -
+    input:
+      bytes: [ 0x23, 0x00, 0xea, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs e0, e0, d0, d0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0xe0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs.h e0, e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0xe4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs.h e0, e0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0xe8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs.h e0, e0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xa3, 0x00, 0xec, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs.h e0, e0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x90, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs.q d0, d0, d0u, d0u, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs.q d0, d0, d0, d0u, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x84, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs.q d0, d0, d0, d0l, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x88, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs.q d0, d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0x94, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs.q d0, d0, d0l, d0l, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0xe0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs.q e0, e0, d0, d0u, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0xe4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs.q e0, e0, d0, d0l, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0xec, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs.q e0, e0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0xf0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs.q e0, e0, d0u, d0u, #0"
+  -
+    input:
+      bytes: [ 0x63, 0x00, 0xf4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs.q e0, e0, d0l, d0l, #0"
+  -
+    input:
+      bytes: [ 0x33, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs.u d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x23, 0x00, 0x88, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs.u d0, d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x33, 0x00, 0xc0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs.u e0, e0, d0, #0"
+  -
+    input:
+      bytes: [ 0x23, 0x00, 0xe8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "msubs.u e0, e0, d0, d0"
+  -
+    input:
+      bytes: [ 0xcd, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mtcr #0, d0"
+  -
+    input:
+      bytes: [ 0xe2, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul d0, d0"
+  -
+    input:
+      bytes: [ 0x53, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x73, 0x00, 0x0a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x53, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul e0, d0, #0"
+  -
+    input:
+      bytes: [ 0x73, 0x00, 0x6a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul e0, d0, d0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0x41, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.f d0, d0, d0"
+  -
+    input:
+      bytes: [ 0xb3, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.h e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xb3, 0x00, 0x64, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.h e0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xb3, 0x00, 0x68, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.h e0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xb3, 0x00, 0x6c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.h e0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0x93, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.q d0, d0, d0u, #0"
+  -
+    input:
+      bytes: [ 0x93, 0x00, 0x04, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.q d0, d0, d0l, #0"
+  -
+    input:
+      bytes: [ 0x93, 0x00, 0x08, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.q d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x93, 0x00, 0x10, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.q d0, d0u, d0u, #0"
+  -
+    input:
+      bytes: [ 0x93, 0x00, 0x14, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.q d0, d0l, d0l, #0"
+  -
+    input:
+      bytes: [ 0x93, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.q e0, d0, d0u, #0"
+  -
+    input:
+      bytes: [ 0x93, 0x00, 0x64, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.q e0, d0, d0l, #0"
+  -
+    input:
+      bytes: [ 0x93, 0x00, 0x6c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.q e0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x53, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.u e0, d0, #0"
+  -
+    input:
+      bytes: [ 0x73, 0x00, 0x68, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mul.u e0, d0, d0"
+  -
+    input:
+      bytes: [ 0xb3, 0x00, 0x70, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulm.h e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xb3, 0x00, 0x74, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulm.h e0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xb3, 0x00, 0x78, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulm.h e0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xb3, 0x00, 0x7c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulm.h e0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0xb3, 0x00, 0xf0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulms.h e0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xb3, 0x00, 0xf4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulms.h e0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xb3, 0x00, 0xf8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulms.h e0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xb3, 0x00, 0xfc, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulms.h e0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0xb3, 0x00, 0x30, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulr.h d0, d0, d0ul, #0"
+  -
+    input:
+      bytes: [ 0xb3, 0x00, 0x34, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulr.h d0, d0, d0lu, #0"
+  -
+    input:
+      bytes: [ 0xb3, 0x00, 0x38, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulr.h d0, d0, d0ll, #0"
+  -
+    input:
+      bytes: [ 0xb3, 0x00, 0x3c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulr.h d0, d0, d0uu, #0"
+  -
+    input:
+      bytes: [ 0x93, 0x00, 0x18, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulr.q d0, d0u, d0u, #0"
+  -
+    input:
+      bytes: [ 0x93, 0x00, 0x1c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulr.q d0, d0l, d0l, #0"
+  -
+    input:
+      bytes: [ 0x53, 0x00, 0xa0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "muls d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x73, 0x00, 0x8a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "muls d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x53, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "muls.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x73, 0x00, 0x88, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "muls.u d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0x90, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "nand d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8f, 0x00, 0x20, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "nand d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x07, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "nand.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x10, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ne d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x20, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ne d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0x10, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ne.a d0, a0, a0"
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0x90, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "nez.a d0, a0"
+  -
+    input:
+      bytes: [ 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "nop"
+  -
+    input:
+      bytes: [ 0x0d, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "nop"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0xb0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "nor d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8f, 0x00, 0x60, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "nor d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x87, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "nor.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0xa6, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or d0, d0"
+  -
+    input:
+      bytes: [ 0x96, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or d15, #0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0xa0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8f, 0x00, 0x40, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or d0, d0, #0"
+  -
+    input:
+      bytes: [ 0xc7, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.and.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0xc7, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.andn.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x70, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.eq d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0xe0, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.eq d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xb0, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.ge d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x60, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.ge d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xc0, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.ge.u d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x80, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.ge.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x90, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.lt d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x20, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.lt d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xa0, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.lt.u d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x40, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.lt.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x80, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.ne d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x00, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.ne d0, d0, #0"
+  -
+    input:
+      bytes: [ 0xc7, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.nor.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0xc7, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.or.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x87, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "or.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0xf0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "orn d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8f, 0x00, 0xe0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "orn d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x07, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "orn.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x6b, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "pack d0, e0, d0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "parity d0, d0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0x20, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "popcnt.w d0, d0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0x51, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "q31tof d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0x91, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "qseed.f d0, d0"
+  -
+    input:
+      bytes: [ 0x0d, 0x00, 0x80, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "restore d0"
+  -
+    input:
+      bytes: [ 0x00, 0x90 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ret"
+  -
+    input:
+      bytes: [ 0x0d, 0x00, 0x80, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "ret"
+  -
+    input:
+      bytes: [ 0x00, 0x80 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "rfe"
+  -
+    input:
+      bytes: [ 0x0d, 0x00, 0xc0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "rfe"
+  -
+    input:
+      bytes: [ 0x0d, 0x00, 0x40, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "rfm"
+  -
+    input:
+      bytes: [ 0x0d, 0x00, 0x40, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "rslcx"
+  -
+    input:
+      bytes: [ 0x2f, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "rstv"
+  -
+    input:
+      bytes: [ 0x32, 0x50 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "rsub d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x00, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "rsub d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x40, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "rsubs d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x60, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "rsubs.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x32, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sat.b d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xe0, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sat.b d0, d0"
+  -
+    input:
+      bytes: [ 0x32, 0x10 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sat.bu d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xf0, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sat.bu d0, d0"
+  -
+    input:
+      bytes: [ 0x32, 0x20 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sat.h d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xe0, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sat.h d0, d0"
+  -
+    input:
+      bytes: [ 0x32, 0x30 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sat.hu d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xf0, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sat.hu d0, d0"
+  -
+    input:
+      bytes: [ 0x2b, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sel d0, d0, d0, d0"
+  -
+    input:
+      bytes: [ 0xab, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sel d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x2b, 0x00, 0x50, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "seln d0, d0, d0, d0"
+  -
+    input:
+      bytes: [ 0xab, 0x00, 0xa0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "seln d0, d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x06, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh d0, #0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8f, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x27, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.and.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x27, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.andn.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x70, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.eq d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0xe0, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.eq d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xb0, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.ge d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x60, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.ge d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xc0, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.ge.u d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x80, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.ge.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.h d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8f, 0x00, 0x00, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.h d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x90, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.lt d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x20, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.lt d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xa0, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.lt.u d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x40, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.lt.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0xa7, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.nand.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x80, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.ne d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x00, 0x07 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.ne d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x27, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.nor.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x27, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.or.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0xa7, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.orn.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0xa7, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.xnor.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0xa7, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sh.xor.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0x86, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha d0, #0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0x10, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8f, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0x10, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha.h d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8f, 0x00, 0x20, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha.h d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "shas d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8f, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "shas d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x8f, 0x00, 0xe0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "shuffle d0, d0, #0"
+  -
+    input:
+      bytes: [ 0xf8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.a [sp]#0, a15"
+  -
+    input:
+      bytes: [ 0xec, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.a [a0]#0, a15"
+  -
+    input:
+      bytes: [ 0xe8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.a [a15]#0, a0"
+  -
+    input:
+      bytes: [ 0xe4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.a [a0+], a0"
+  -
+    input:
+      bytes: [ 0xf4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.a [a0], a0"
+  -
+    input:
+      bytes: [ 0xb5, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.a [a0]#0, a0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x80, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.a [a0+]#0, a0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x80, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.a [p0+r], a0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x80, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.a [+a0]#0, a0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x80, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.a [p0+c]#0, a0"
+  -
+    input:
+      bytes: [ 0xa5, 0x00, 0x00, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.a #0, a0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x80, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.a [a0]#0, a0"
+  -
+    input:
+      bytes: [ 0x34, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [a0], d0"
+  -
+    input:
+      bytes: [ 0x28, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [a15]#0, d0"
+  -
+    input:
+      bytes: [ 0x2c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [a0]#0, d15"
+  -
+    input:
+      bytes: [ 0x24, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [a0+], d0"
+  -
+    input:
+      bytes: [ 0xe9, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [a0]#0, d0"
+  -
+    input:
+      bytes: [ 0x25, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b #0, d0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [a0+]#0, d0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [p0+r], d0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [+a0]#0, d0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [p0+c]#0, d0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x00, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.b [a0]#0, d0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x40, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.d [a0+]#0, e0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x40, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.d [p0+r], e0"
+  -
+    input:
+      bytes: [ 0xa5, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.d #0, e0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x40, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.d [+a0]#0, e0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x40, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.d [p0+c]#0, e0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x40, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.d [a0]#0, e0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0xc0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.da [a0+]#0, p0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0xc0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.da [p0+r], p0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0xc0, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.da [+a0]#0, p0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0xc0, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.da [p0+c]#0, p0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0xc0, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.da [a0]#0, p0"
+  -
+    input:
+      bytes: [ 0xa5, 0x00, 0x00, 0x0c ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.da #0, p0"
+  -
+    input:
+      bytes: [ 0xa4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [a0+], d0"
+  -
+    input:
+      bytes: [ 0xa8, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [a15]#0, d0"
+  -
+    input:
+      bytes: [ 0xac, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [a0]#0, d15"
+  -
+    input:
+      bytes: [ 0xb4, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [a0], d0"
+  -
+    input:
+      bytes: [ 0xf9, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [a0]#0, d0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [a0+]#0, d0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [p0+r], d0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x80, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [+a0]#0, d0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x80, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [p0+c]#0, d0"
+  -
+    input:
+      bytes: [ 0x25, 0x00, 0x00, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h #0, d0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x80, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.h [a0]#0, d0"
+  -
+    input:
+      bytes: [ 0x65, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.q #0, d0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x00, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.q [a0+]#0, d0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x00, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.q [p0+r], d0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x00, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.q [+a0]#0, d0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x00, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.q [p0+c]#0, d0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x00, 0x0a ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.q [a0]#0, d0"
+  -
+    input:
+      bytes: [ 0xd5, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.t #0, #0, #0"
+  -
+    input:
+      bytes: [ 0x78, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w [sp]#0, d15"
+  -
+    input:
+      bytes: [ 0x74, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w [a0], d0"
+  -
+    input:
+      bytes: [ 0x64, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w [a0+], d0"
+  -
+    input:
+      bytes: [ 0x68, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w [a15]#0, d0"
+  -
+    input:
+      bytes: [ 0x6c, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w [a0]#0, d15"
+  -
+    input:
+      bytes: [ 0x59, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w [a0]#0, d0"
+  -
+    input:
+      bytes: [ 0xa5, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w #0, d0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x00, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w [a0+]#0, d0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x00, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w [p0+r], d0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x00, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w [+a0]#0, d0"
+  -
+    input:
+      bytes: [ 0xa9, 0x00, 0x00, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w [p0+c]#0, d0"
+  -
+    input:
+      bytes: [ 0x89, 0x00, 0x00, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "st.w [a0]#0, d0"
+  -
+    input:
+      bytes: [ 0x15, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "stlcx #0"
+  -
+    input:
+      bytes: [ 0x49, 0x00, 0x80, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "stlcx [a0]#0"
+  -
+    input:
+      bytes: [ 0x15, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "stucx #0"
+  -
+    input:
+      bytes: [ 0x49, 0x00, 0xc0, 0x09 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "stucx [a0]#0"
+  -
+    input:
+      bytes: [ 0x52, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub d0, d15, d0"
+  -
+    input:
+      bytes: [ 0x5a, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub d15, d0, d0"
+  -
+    input:
+      bytes: [ 0xa2, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub.a sp, #0"
+  -
+    input:
+      bytes: [ 0x01, 0x00, 0x20, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub.a a0, a0, a0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x80, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub.b d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x6b, 0x00, 0x31, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub.f d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x80, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "sub.h d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xd0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "subc d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x62, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "subs d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xa0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "subs d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xa0, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "subs.h d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xb0, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "subs.hu d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xb0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "subs.u d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xc0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "subx d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x0d, 0x00, 0x00, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "svlcx"
+  -
+    input:
+      bytes: [ 0x49, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "swap.w [a0+]#0, d0"
+  -
+    input:
+      bytes: [ 0x69, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "swap.w [p0+r], d0"
+  -
+    input:
+      bytes: [ 0xe5, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "swap.w #0, d0"
+  -
+    input:
+      bytes: [ 0x49, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "swap.w [+a0]#0, d0"
+  -
+    input:
+      bytes: [ 0x69, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "swap.w [p0+c]#0, d0"
+  -
+    input:
+      bytes: [ 0x49, 0x00, 0x00, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "swap.w [a0]#0, d0"
+  -
+    input:
+      bytes: [ 0x69, 0x00, 0x00, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "swap.w [p0+i], d0"
+  -
+    input:
+      bytes: [ 0x49, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "swapmsk.w [a0+]#0, e0"
+  -
+    input:
+      bytes: [ 0x69, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "swapmsk.w [p0+r], e0"
+  -
+    input:
+      bytes: [ 0x49, 0x00, 0x80, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "swapmsk.w [+a0]#0, e0"
+  -
+    input:
+      bytes: [ 0x69, 0x00, 0x80, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "swapmsk.w [p0+c]#0, e0"
+  -
+    input:
+      bytes: [ 0x49, 0x00, 0x80, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "swapmsk.w [a0]#0, e0"
+  -
+    input:
+      bytes: [ 0x69, 0x00, 0x80, 0x08 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "swapmsk.w [p0+i], e0"
+  -
+    input:
+      bytes: [ 0xad, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "syscall #0"
+  -
+    input:
+      bytes: [ 0x75, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "tlbdemap d0"
+  -
+    input:
+      bytes: [ 0x75, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "tlbflush.a"
+  -
+    input:
+      bytes: [ 0x75, 0x00, 0x50, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "tlbflush.b"
+  -
+    input:
+      bytes: [ 0x75, 0x00, 0x00, 0x04 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "tlbmap e0"
+  -
+    input:
+      bytes: [ 0x75, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "tlbprobe.a d0"
+  -
+    input:
+      bytes: [ 0x75, 0x00, 0x90, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "tlbprobe.i d0"
+  -
+    input:
+      bytes: [ 0x0d, 0x00, 0x40, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "trapsv"
+  -
+    input:
+      bytes: [ 0x0d, 0x00, 0x00, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "trapv"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0x80, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "unpack e0, d0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0xc1, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "updfl d0"
+  -
+    input:
+      bytes: [ 0x4b, 0x00, 0x61, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "utof d0, d0"
+  -
+    input:
+      bytes: [ 0x0d, 0x00, 0x80, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "wait"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0xd0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "xnor d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8f, 0x00, 0xa0, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "xnor d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x07, 0x00, 0x40, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "xnor.t d0, d0, #0, d0, #0"
+  -
+    input:
+      bytes: [ 0xc6, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor d0, d0"
+  -
+    input:
+      bytes: [ 0x0f, 0x00, 0xc0, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8f, 0x00, 0x80, 0x01 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0xf0, 0x02 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor.eq d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0xe0, 0x05 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor.eq d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x30, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor.ge d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x60, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor.ge d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x40, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor.ge.u d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x80, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor.ge.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x10, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor.lt d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x20, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor.lt d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x20, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor.lt.u d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x40, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor.lt.u d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x0b, 0x00, 0x00, 0x03 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor.ne d0, d0, d0"
+  -
+    input:
+      bytes: [ 0x8b, 0x00, 0x00, 0x06 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor.ne d0, d0, #0"
+  -
+    input:
+      bytes: [ 0x07, 0x00, 0x60, 0x00 ]
+      arch: "CS_ARCH_TRICORE"
+      options: [ "CS_MODE_TRICORE_162" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor.t d0, d0, #0, d0, #0"
diff --git a/tests/MC/X86/3DNow.s.yaml b/tests/MC/X86/3DNow.s.yaml
new file mode 100644
index 000000000..1ca456338
--- /dev/null
+++ b/tests/MC/X86/3DNow.s.yaml
@@ -0,0 +1,253 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x0f, 0x0f, 0xca, 0xbf ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "pavgusb %mm2, %mm1"
+  -
+    input:
+      bytes: [ 0x0f, 0x0f, 0x5c, 0x16, 0x09, 0xbf ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "pavgusb 9(%esi, %edx), %mm3"
+  -
+    input:
+      bytes: [ 0x0f, 0x0f, 0xca, 0x1d ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "pf2id %mm2, %mm1"
+  -
+    input:
+      bytes: [ 0x0f, 0x0f, 0x5c, 0x16, 0x09, 0x1d ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "pf2id 9(%esi, %edx), %mm3"
+  -
+    input:
+      bytes: [ 0x0f, 0x0f, 0xca, 0xae ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "pfacc %mm2, %mm1"
+  -
+    input:
+      bytes: [ 0x0f, 0x0f, 0xca, 0x9e ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "pfadd %mm2, %mm1"
+  -
+    input:
+      bytes: [ 0x0f, 0x0f, 0xca, 0xb0 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "pfcmpeq %mm2, %mm1"
+  -
+    input:
+      bytes: [ 0x0f, 0x0f, 0xca, 0x90 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "pfcmpge %mm2, %mm1"
+  -
+    input:
+      bytes: [ 0x0f, 0x0f, 0xca, 0xa0 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "pfcmpgt %mm2, %mm1"
+  -
+    input:
+      bytes: [ 0x0f, 0x0f, 0xca, 0xa4 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "pfmax %mm2, %mm1"
+  -
+    input:
+      bytes: [ 0x0f, 0x0f, 0xca, 0x94 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "pfmin %mm2, %mm1"
+  -
+    input:
+      bytes: [ 0x0f, 0x0f, 0xca, 0xb4 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "pfmul %mm2, %mm1"
+  -
+    input:
+      bytes: [ 0x0f, 0x0f, 0xca, 0x96 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "pfrcp %mm2, %mm1"
+  -
+    input:
+      bytes: [ 0x0f, 0x0f, 0xca, 0xa6 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "pfrcpit1 %mm2, %mm1"
+  -
+    input:
+      bytes: [ 0x0f, 0x0f, 0xca, 0xb6 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "pfrcpit2 %mm2, %mm1"
+  -
+    input:
+      bytes: [ 0x0f, 0x0f, 0xca, 0xa7 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "pfrsqit1 %mm2, %mm1"
+  -
+    input:
+      bytes: [ 0x0f, 0x0f, 0xca, 0x97 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "pfrsqrt %mm2, %mm1"
+  -
+    input:
+      bytes: [ 0x0f, 0x0f, 0xca, 0x9a ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "pfsub %mm2, %mm1"
+  -
+    input:
+      bytes: [ 0x0f, 0x0f, 0xca, 0xaa ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "pfsubr %mm2, %mm1"
+  -
+    input:
+      bytes: [ 0x0f, 0x0f, 0xca, 0x0d ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "pi2fd %mm2, %mm1"
+  -
+    input:
+      bytes: [ 0x0f, 0x0f, 0xca, 0xb7 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "pmulhrw %mm2, %mm1"
+  -
+    input:
+      bytes: [ 0x0f, 0x0e ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "femms"
+  -
+    input:
+      bytes: [ 0x0f, 0x0d, 0x00 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "prefetch (%eax)"
+  -
+    input:
+      bytes: [ 0x0f, 0x0f, 0xca, 0x1c ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "pf2iw %mm2, %mm1"
+  -
+    input:
+      bytes: [ 0x0f, 0x0f, 0xca, 0x0c ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "pi2fw %mm2, %mm1"
+  -
+    input:
+      bytes: [ 0x0f, 0x0f, 0xca, 0x8a ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "pfnacc %mm2, %mm1"
+  -
+    input:
+      bytes: [ 0x0f, 0x0f, 0xca, 0x8e ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "pfpnacc %mm2, %mm1"
+  -
+    input:
+      bytes: [ 0x0f, 0x0f, 0xca, 0xbb ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "pswapd %mm2, %mm1"
diff --git a/tests/MC/X86/address-size.s.yaml b/tests/MC/X86/address-size.s.yaml
new file mode 100644
index 000000000..cae1ba1f4
--- /dev/null
+++ b/tests/MC/X86/address-size.s.yaml
@@ -0,0 +1,37 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x67, 0xc6, 0x06, 0x00 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "movb $0x0, (%esi)"
+  -
+    input:
+      bytes: [ 0xc6, 0x06, 0x00 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "movb $0x0, (%rsi)"
+  -
+    input:
+      bytes: [ 0x67, 0xc6, 0x06, 0x00 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "movb $0x0, (%esi)"
+  -
+    input:
+      bytes: [ 0xc6, 0x06, 0x00 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "movb $0x0, (%rsi)"
diff --git a/tests/MC/X86/avx512-encodings.s.yaml b/tests/MC/X86/avx512-encodings.s.yaml
new file mode 100644
index 000000000..e13d723ca
--- /dev/null
+++ b/tests/MC/X86/avx512-encodings.s.yaml
@@ -0,0 +1,100 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x62, 0xa3, 0x55, 0x48, 0x38, 0xcd, 0x01 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vinserti32x4 $1, %xmm21, %zmm5, %zmm17"
+  -
+    input:
+      bytes: [ 0x62, 0xe3, 0x1d, 0x40, 0x38, 0x4f, 0x10, 0x01 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vinserti32x4 $1, 256(%rdi), %zmm28, %zmm17"
+  -
+    input:
+      bytes: [ 0x62, 0x33, 0x7d, 0x48, 0x39, 0xc9, 0x01 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vextracti32x4 $1, %zmm9, %xmm17"
+  -
+    input:
+      bytes: [ 0x62, 0x33, 0xfd, 0x48, 0x3b, 0xc9, 0x01 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vextracti64x4 $1, %zmm9, %ymm17"
+  -
+    input:
+      bytes: [ 0x62, 0x73, 0xfd, 0x48, 0x3b, 0x4f, 0x10, 0x01 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vextracti64x4 $1, %zmm9, 512(%rdi)"
+  -
+    input:
+      bytes: [ 0x62, 0xb1, 0x35, 0x40, 0x72, 0xe1, 0x02 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpsrad $2, %zmm17, %zmm25"
+  -
+    input:
+      bytes: [ 0x62, 0xf1, 0x35, 0x40, 0x72, 0x64, 0xb7, 0x08, 0x02 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpsrad $2, 512(%rdi, %rsi, 4), %zmm25"
+  -
+    input:
+      bytes: [ 0x62, 0x21, 0x1d, 0x48, 0xe2, 0xc9 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpsrad %xmm17, %zmm12, %zmm25"
+  -
+    input:
+      bytes: [ 0x62, 0x61, 0x1d, 0x48, 0xe2, 0x4c, 0xb7, 0x20 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpsrad 512(%rdi, %rsi, 4), %zmm12, %zmm25"
+  -
+    input:
+      bytes: [ 0x62, 0xf2, 0x7d, 0xc9, 0x58, 0xc8 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpbroadcastd %xmm0, %zmm1 {%k1} {z}"
+  -
+    input:
+      bytes: [ 0x62, 0xf1, 0xfe, 0x4b, 0x6f, 0xc8 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovdqu64 %zmm0, %zmm1 {%k3}"
diff --git a/tests/MC/X86/intel-syntax-encoding.s.yaml b/tests/MC/X86/intel-syntax-encoding.s.yaml
new file mode 100644
index 000000000..cd827fbdb
--- /dev/null
+++ b/tests/MC/X86/intel-syntax-encoding.s.yaml
@@ -0,0 +1,262 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x66, 0x83, 0xf0, 0x0c ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor ax, 12"
+  -
+    input:
+      bytes: [ 0x83, 0xf0, 0x0c ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor eax, 12"
+  -
+    input:
+      bytes: [ 0x48, 0x83, 0xf0, 0x0c ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xor rax, 12"
+  -
+    input:
+      bytes: [ 0x66, 0x83, 0xc8, 0x0c ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "or ax, 12"
+  -
+    input:
+      bytes: [ 0x83, 0xc8, 0x0c ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "or eax, 12"
+  -
+    input:
+      bytes: [ 0x48, 0x83, 0xc8, 0x0c ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "or rax, 12"
+  -
+    input:
+      bytes: [ 0x66, 0x83, 0xf8, 0x0c ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmp ax, 12"
+  -
+    input:
+      bytes: [ 0x83, 0xf8, 0x0c ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmp eax, 12"
+  -
+    input:
+      bytes: [ 0x48, 0x83, 0xf8, 0x0c ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmp rax, 12"
+  -
+    input:
+      bytes: [ 0x48, 0x89, 0x44, 0x24, 0xf0 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "mov qword ptr [rsp - 16], rax"
+  -
+    input:
+      bytes: [ 0x66, 0x83, 0xc0, 0xf4 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add ax, -12"
+  -
+    input:
+      bytes: [ 0x83, 0xc0, 0xf4 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add eax, -12"
+  -
+    input:
+      bytes: [ 0x48, 0x83, 0xc0, 0xf4 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "add rax, -12"
+  -
+    input:
+      bytes: [ 0x66, 0x83, 0xd0, 0xf4 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "adc ax, -12"
+  -
+    input:
+      bytes: [ 0x83, 0xd0, 0xf4 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "adc eax, -12"
+  -
+    input:
+      bytes: [ 0x48, 0x83, 0xd0, 0xf4 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "adc rax, -12"
+  -
+    input:
+      bytes: [ 0x66, 0x83, 0xd8, 0xf4 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sbb ax, -12"
+  -
+    input:
+      bytes: [ 0x83, 0xd8, 0xf4 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sbb eax, -12"
+  -
+    input:
+      bytes: [ 0x48, 0x83, 0xd8, 0xf4 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sbb rax, -12"
+  -
+    input:
+      bytes: [ 0x66, 0x83, 0xf8, 0xf4 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmp ax, -12"
+  -
+    input:
+      bytes: [ 0x83, 0xf8, 0xf4 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmp eax, -12"
+  -
+    input:
+      bytes: [ 0x48, 0x83, 0xf8, 0xf4 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmp rax, -12"
+  -
+    input:
+      bytes: [ 0xf2, 0x0f, 0x10, 0x2c, 0x25, 0xf8, 0xff, 0xff, 0xff ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "movsd xmm5, qword ptr [0xfffffffffffffff8]"
+  -
+    input:
+      bytes: [ 0xd1, 0xe7 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "shl edi, 1"
+  -
+    input:
+      bytes: [ 0x0f, 0xc2, 0xd1, 0x01 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "cmpltps xmm2, xmm1"
+  -
+    input:
+      bytes: [ 0xc3 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "ret"
+  -
+    input:
+      bytes: [ 0xcb ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "retf"
+  -
+    input:
+      bytes: [ 0xc2, 0x08, 0x00 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "ret 8"
+  -
+    input:
+      bytes: [ 0xca, 0x08, 0x00 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "retf 8"
diff --git a/tests/MC/X86/x86-32-avx.s.yaml b/tests/MC/X86/x86-32-avx.s.yaml
new file mode 100644
index 000000000..bcf43a14b
--- /dev/null
+++ b/tests/MC/X86/x86-32-avx.s.yaml
@@ -0,0 +1,7354 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xc5, 0xca, 0x58, 0xd4 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vaddss %xmm4, %xmm6, %xmm2"
+  -
+    input:
+      bytes: [ 0xc5, 0xca, 0x59, 0xd4 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmulss %xmm4, %xmm6, %xmm2"
+  -
+    input:
+      bytes: [ 0xc5, 0xca, 0x5c, 0xd4 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vsubss %xmm4, %xmm6, %xmm2"
+  -
+    input:
+      bytes: [ 0xc5, 0xca, 0x5e, 0xd4 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vdivss %xmm4, %xmm6, %xmm2"
+  -
+    input:
+      bytes: [ 0xc5, 0xcb, 0x58, 0xd4 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vaddsd %xmm4, %xmm6, %xmm2"
+  -
+    input:
+      bytes: [ 0xc5, 0xcb, 0x59, 0xd4 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmulsd %xmm4, %xmm6, %xmm2"
+  -
+    input:
+      bytes: [ 0xc5, 0xcb, 0x5c, 0xd4 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vsubsd %xmm4, %xmm6, %xmm2"
+  -
+    input:
+      bytes: [ 0xc5, 0xcb, 0x5e, 0xd4 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vdivsd %xmm4, %xmm6, %xmm2"
+  -
+    input:
+      bytes: [ 0xc5, 0xea, 0x58, 0xac, 0xcb, 0xef, 0xbe, 0xad, 0xde ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vaddss 3735928559(%ebx, %ecx, 8), %xmm2, %xmm5"
+  -
+    input:
+      bytes: [ 0xc5, 0xea, 0x5c, 0xac, 0xcb, 0xef, 0xbe, 0xad, 0xde ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vsubss 3735928559(%ebx, %ecx, 8), %xmm2, %xmm5"
+  -
+    input:
+      bytes: [ 0xc5, 0xea, 0x59, 0xac, 0xcb, 0xef, 0xbe, 0xad, 0xde ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmulss 3735928559(%ebx, %ecx, 8), %xmm2, %xmm5"
+  -
+    input:
+      bytes: [ 0xc5, 0xea, 0x5e, 0xac, 0xcb, 0xef, 0xbe, 0xad, 0xde ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vdivss 3735928559(%ebx, %ecx, 8), %xmm2, %xmm5"
+  -
+    input:
+      bytes: [ 0xc5, 0xeb, 0x58, 0xac, 0xcb, 0xef, 0xbe, 0xad, 0xde ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vaddsd 3735928559(%ebx, %ecx, 8), %xmm2, %xmm5"
+  -
+    input:
+      bytes: [ 0xc5, 0xeb, 0x5c, 0xac, 0xcb, 0xef, 0xbe, 0xad, 0xde ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vsubsd 3735928559(%ebx, %ecx, 8), %xmm2, %xmm5"
+  -
+    input:
+      bytes: [ 0xc5, 0xeb, 0x59, 0xac, 0xcb, 0xef, 0xbe, 0xad, 0xde ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmulsd 3735928559(%ebx, %ecx, 8), %xmm2, %xmm5"
+  -
+    input:
+      bytes: [ 0xc5, 0xeb, 0x5e, 0xac, 0xcb, 0xef, 0xbe, 0xad, 0xde ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vdivsd 3735928559(%ebx, %ecx, 8), %xmm2, %xmm5"
+  -
+    input:
+      bytes: [ 0xc5, 0xc8, 0x58, 0xd4 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vaddps %xmm4, %xmm6, %xmm2"
+  -
+    input:
+      bytes: [ 0xc5, 0xc8, 0x5c, 0xd4 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vsubps %xmm4, %xmm6, %xmm2"
+  -
+    input:
+      bytes: [ 0xc5, 0xc8, 0x59, 0xd4 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmulps %xmm4, %xmm6, %xmm2"
+  -
+    input:
+      bytes: [ 0xc5, 0xc8, 0x5e, 0xd4 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vdivps %xmm4, %xmm6, %xmm2"
+  -
+    input:
+      bytes: [ 0xc5, 0xc9, 0x58, 0xd4 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vaddpd %xmm4, %xmm6, %xmm2"
+  -
+    input:
+      bytes: [ 0xc5, 0xc9, 0x5c, 0xd4 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vsubpd %xmm4, %xmm6, %xmm2"
+  -
+    input:
+      bytes: [ 0xc5, 0xc9, 0x59, 0xd4 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmulpd %xmm4, %xmm6, %xmm2"
+  -
+    input:
+      bytes: [ 0xc5, 0xc9, 0x5e, 0xd4 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vdivpd %xmm4, %xmm6, %xmm2"
+  -
+    input:
+      bytes: [ 0xc5, 0xe8, 0x58, 0xac, 0xcb, 0xef, 0xbe, 0xad, 0xde ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vaddps 3735928559(%ebx, %ecx, 8), %xmm2, %xmm5"
+  -
+    input:
+      bytes: [ 0xc5, 0xe8, 0x5c, 0xac, 0xcb, 0xef, 0xbe, 0xad, 0xde ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vsubps 3735928559(%ebx, %ecx, 8), %xmm2, %xmm5"
+  -
+    input:
+      bytes: [ 0xc5, 0xe8, 0x59, 0xac, 0xcb, 0xef, 0xbe, 0xad, 0xde ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmulps 3735928559(%ebx, %ecx, 8), %xmm2, %xmm5"
+  -
+    input:
+      bytes: [ 0xc5, 0xe8, 0x5e, 0xac, 0xcb, 0xef, 0xbe, 0xad, 0xde ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vdivps 3735928559(%ebx, %ecx, 8), %xmm2, %xmm5"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0x58, 0xac, 0xcb, 0xef, 0xbe, 0xad, 0xde ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vaddpd 3735928559(%ebx, %ecx, 8), %xmm2, %xmm5"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0x5c, 0xac, 0xcb, 0xef, 0xbe, 0xad, 0xde ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vsubpd 3735928559(%ebx, %ecx, 8), %xmm2, %xmm5"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0x59, 0xac, 0xcb, 0xef, 0xbe, 0xad, 0xde ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmulpd 3735928559(%ebx, %ecx, 8), %xmm2, %xmm5"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0x5e, 0xac, 0xcb, 0xef, 0xbe, 0xad, 0xde ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vdivpd 3735928559(%ebx, %ecx, 8), %xmm2, %xmm5"
+  -
+    input:
+      bytes: [ 0xc5, 0xda, 0x5f, 0xf2 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmaxss %xmm2, %xmm4, %xmm6"
+  -
+    input:
+      bytes: [ 0xc5, 0xdb, 0x5f, 0xf2 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmaxsd %xmm2, %xmm4, %xmm6"
+  -
+    input:
+      bytes: [ 0xc5, 0xda, 0x5d, 0xf2 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vminss %xmm2, %xmm4, %xmm6"
+  -
+    input:
+      bytes: [ 0xc5, 0xdb, 0x5d, 0xf2 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vminsd %xmm2, %xmm4, %xmm6"
+  -
+    input:
+      bytes: [ 0xc5, 0xea, 0x5f, 0x6c, 0xcb, 0xfc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmaxss -4(%ebx, %ecx, 8), %xmm2, %xmm5"
+  -
+    input:
+      bytes: [ 0xc5, 0xeb, 0x5f, 0x6c, 0xcb, 0xfc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmaxsd -4(%ebx, %ecx, 8), %xmm2, %xmm5"
+  -
+    input:
+      bytes: [ 0xc5, 0xea, 0x5d, 0x6c, 0xcb, 0xfc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vminss -4(%ebx, %ecx, 8), %xmm2, %xmm5"
+  -
+    input:
+      bytes: [ 0xc5, 0xeb, 0x5d, 0x6c, 0xcb, 0xfc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vminsd -4(%ebx, %ecx, 8), %xmm2, %xmm5"
+  -
+    input:
+      bytes: [ 0xc5, 0xd8, 0x5f, 0xf2 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmaxps %xmm2, %xmm4, %xmm6"
+  -
+    input:
+      bytes: [ 0xc5, 0xd9, 0x5f, 0xf2 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmaxpd %xmm2, %xmm4, %xmm6"
+  -
+    input:
+      bytes: [ 0xc5, 0xd8, 0x5d, 0xf2 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vminps %xmm2, %xmm4, %xmm6"
+  -
+    input:
+      bytes: [ 0xc5, 0xd9, 0x5d, 0xf2 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vminpd %xmm2, %xmm4, %xmm6"
+  -
+    input:
+      bytes: [ 0xc5, 0xe8, 0x5f, 0x6c, 0xcb, 0xfc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmaxps -4(%ebx, %ecx, 8), %xmm2, %xmm5"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0x5f, 0x6c, 0xcb, 0xfc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmaxpd -4(%ebx, %ecx, 8), %xmm2, %xmm5"
+  -
+    input:
+      bytes: [ 0xc5, 0xe8, 0x5d, 0x6c, 0xcb, 0xfc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vminps -4(%ebx, %ecx, 8), %xmm2, %xmm5"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0x5d, 0x6c, 0xcb, 0xfc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vminpd -4(%ebx, %ecx, 8), %xmm2, %xmm5"
+  -
+    input:
+      bytes: [ 0xc5, 0xd8, 0x54, 0xf2 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vandps %xmm2, %xmm4, %xmm6"
+  -
+    input:
+      bytes: [ 0xc5, 0xd9, 0x54, 0xf2 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vandpd %xmm2, %xmm4, %xmm6"
+  -
+    input:
+      bytes: [ 0xc5, 0xe8, 0x54, 0x6c, 0xcb, 0xfc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vandps -4(%ebx, %ecx, 8), %xmm2, %xmm5"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0x54, 0x6c, 0xcb, 0xfc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vandpd -4(%ebx, %ecx, 8), %xmm2, %xmm5"
+  -
+    input:
+      bytes: [ 0xc5, 0xd8, 0x56, 0xf2 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vorps %xmm2, %xmm4, %xmm6"
+  -
+    input:
+      bytes: [ 0xc5, 0xd9, 0x56, 0xf2 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vorpd %xmm2, %xmm4, %xmm6"
+  -
+    input:
+      bytes: [ 0xc5, 0xe8, 0x56, 0x6c, 0xcb, 0xfc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vorps -4(%ebx, %ecx, 8), %xmm2, %xmm5"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0x56, 0x6c, 0xcb, 0xfc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vorpd -4(%ebx, %ecx, 8), %xmm2, %xmm5"
+  -
+    input:
+      bytes: [ 0xc5, 0xd8, 0x57, 0xf2 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vxorps %xmm2, %xmm4, %xmm6"
+  -
+    input:
+      bytes: [ 0xc5, 0xd9, 0x57, 0xf2 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vxorpd %xmm2, %xmm4, %xmm6"
+  -
+    input:
+      bytes: [ 0xc5, 0xe8, 0x57, 0x6c, 0xcb, 0xfc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vxorps -4(%ebx, %ecx, 8), %xmm2, %xmm5"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0x57, 0x6c, 0xcb, 0xfc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vxorpd -4(%ebx, %ecx, 8), %xmm2, %xmm5"
+  -
+    input:
+      bytes: [ 0xc5, 0xd8, 0x55, 0xf2 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vandnps %xmm2, %xmm4, %xmm6"
+  -
+    input:
+      bytes: [ 0xc5, 0xd9, 0x55, 0xf2 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vandnpd %xmm2, %xmm4, %xmm6"
+  -
+    input:
+      bytes: [ 0xc5, 0xe8, 0x55, 0x6c, 0xcb, 0xfc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vandnps -4(%ebx, %ecx, 8), %xmm2, %xmm5"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0x55, 0x6c, 0xcb, 0xfc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vandnpd -4(%ebx, %ecx, 8), %xmm2, %xmm5"
+  -
+    input:
+      bytes: [ 0xc5, 0xfa, 0x10, 0x6c, 0xcb, 0xfc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovss -4(%ebx, %ecx, 8), %xmm5"
+  -
+    input:
+      bytes: [ 0xc5, 0xea, 0x10, 0xec ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovss %xmm4, %xmm2, %xmm5"
+  -
+    input:
+      bytes: [ 0xc5, 0xfb, 0x10, 0x6c, 0xcb, 0xfc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovsd -4(%ebx, %ecx, 8), %xmm5"
+  -
+    input:
+      bytes: [ 0xc5, 0xeb, 0x10, 0xec ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovsd %xmm4, %xmm2, %xmm5"
+  -
+    input:
+      bytes: [ 0xc5, 0xe8, 0x15, 0xe1 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vunpckhps %xmm1, %xmm2, %xmm4"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0x15, 0xe1 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vunpckhpd %xmm1, %xmm2, %xmm4"
+  -
+    input:
+      bytes: [ 0xc5, 0xe8, 0x14, 0xe1 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vunpcklps %xmm1, %xmm2, %xmm4"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0x14, 0xe1 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vunpcklpd %xmm1, %xmm2, %xmm4"
+  -
+    input:
+      bytes: [ 0xc5, 0xe8, 0x15, 0x6c, 0xcb, 0xfc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vunpckhps -4(%ebx, %ecx, 8), %xmm2, %xmm5"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0x15, 0x6c, 0xcb, 0xfc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vunpckhpd -4(%ebx, %ecx, 8), %xmm2, %xmm5"
+  -
+    input:
+      bytes: [ 0xc5, 0xe8, 0x14, 0x6c, 0xcb, 0xfc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vunpcklps -4(%ebx, %ecx, 8), %xmm2, %xmm5"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0x14, 0x6c, 0xcb, 0xfc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vunpcklpd -4(%ebx, %ecx, 8), %xmm2, %xmm5"
+  -
+    input:
+      bytes: [ 0xc5, 0xc8, 0xc2, 0xc8, 0x00 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpeqps %xmm0, %xmm6, %xmm1"
+  -
+    input:
+      bytes: [ 0xc5, 0xc8, 0xc2, 0x08, 0x00 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpeqps (%eax), %xmm6, %xmm1"
+  -
+    input:
+      bytes: [ 0xc5, 0xc8, 0xc2, 0xc8, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpordps %xmm0, %xmm6, %xmm1"
+  -
+    input:
+      bytes: [ 0xc5, 0xc9, 0xc2, 0xc8, 0x00 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpeqpd %xmm0, %xmm6, %xmm1"
+  -
+    input:
+      bytes: [ 0xc5, 0xc9, 0xc2, 0x08, 0x00 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpeqpd (%eax), %xmm6, %xmm1"
+  -
+    input:
+      bytes: [ 0xc5, 0xc9, 0xc2, 0xc8, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpordpd %xmm0, %xmm6, %xmm1"
+  -
+    input:
+      bytes: [ 0xc5, 0xe8, 0xc6, 0xd9, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vshufps $8, %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe8, 0xc6, 0x5c, 0xcb, 0xfc, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vshufps $8, -4(%ebx, %ecx, 8), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0xc6, 0xd9, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vshufpd $8, %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0xc6, 0x5c, 0xcb, 0xfc, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vshufpd $8, -4(%ebx, %ecx, 8), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe8, 0xc2, 0xd9, 0x00 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpeqps %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe8, 0xc2, 0xd9, 0x02 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpleps %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe8, 0xc2, 0xd9, 0x01 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpltps %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe8, 0xc2, 0xd9, 0x04 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpneqps %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe8, 0xc2, 0xd9, 0x06 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpnleps %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe8, 0xc2, 0xd9, 0x05 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpnltps %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe8, 0xc2, 0xd9, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpordps %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe8, 0xc2, 0xd9, 0x03 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpunordps %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe8, 0xc2, 0x5c, 0xcb, 0xfc, 0x00 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpeqps -4(%ebx, %ecx, 8), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe8, 0xc2, 0x5c, 0xcb, 0xfc, 0x02 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpleps -4(%ebx, %ecx, 8), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe8, 0xc2, 0x5c, 0xcb, 0xfc, 0x01 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpltps -4(%ebx, %ecx, 8), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe8, 0xc2, 0x5c, 0xcb, 0xfc, 0x04 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpneqps -4(%ebx, %ecx, 8), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe8, 0xc2, 0x5c, 0xcb, 0xfc, 0x06 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpnleps -4(%ebx, %ecx, 8), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe8, 0xc2, 0x5c, 0xcb, 0xfc, 0x05 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpnltps -4(%ebx, %ecx, 8), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xc8, 0xc2, 0x54, 0xcb, 0xfc, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpordps -4(%ebx, %ecx, 8), %xmm6, %xmm2"
+  -
+    input:
+      bytes: [ 0xc5, 0xe8, 0xc2, 0x5c, 0xcb, 0xfc, 0x03 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpunordps -4(%ebx, %ecx, 8), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0xc2, 0xd9, 0x00 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpeqpd %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0xc2, 0xd9, 0x02 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmplepd %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0xc2, 0xd9, 0x01 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpltpd %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0xc2, 0xd9, 0x04 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpneqpd %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0xc2, 0xd9, 0x06 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpnlepd %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0xc2, 0xd9, 0x05 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpnltpd %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0xc2, 0xd9, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpordpd %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0xc2, 0xd9, 0x03 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpunordpd %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0xc2, 0x5c, 0xcb, 0xfc, 0x00 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpeqpd -4(%ebx, %ecx, 8), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0xc2, 0x5c, 0xcb, 0xfc, 0x02 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmplepd -4(%ebx, %ecx, 8), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0xc2, 0x5c, 0xcb, 0xfc, 0x01 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpltpd -4(%ebx, %ecx, 8), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0xc2, 0x5c, 0xcb, 0xfc, 0x04 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpneqpd -4(%ebx, %ecx, 8), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0xc2, 0x5c, 0xcb, 0xfc, 0x06 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpnlepd -4(%ebx, %ecx, 8), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0xc2, 0x5c, 0xcb, 0xfc, 0x05 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpnltpd -4(%ebx, %ecx, 8), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xc9, 0xc2, 0x54, 0xcb, 0xfc, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpordpd -4(%ebx, %ecx, 8), %xmm6, %xmm2"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0xc2, 0x5c, 0xcb, 0xfc, 0x03 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpunordpd -4(%ebx, %ecx, 8), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xf8, 0x50, 0xc2 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovmskps %xmm2, %eax"
+  -
+    input:
+      bytes: [ 0xc5, 0xf9, 0x50, 0xc2 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovmskpd %xmm2, %eax"
+  -
+    input:
+      bytes: [ 0xc5, 0xfc, 0x50, 0xc2 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovmskps %ymm2, %eax"
+  -
+    input:
+      bytes: [ 0xc5, 0xfd, 0x50, 0xc2 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovmskpd %ymm2, %eax"
+  -
+    input:
+      bytes: [ 0xc5, 0xea, 0xc2, 0xd9, 0x00 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpeqss %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xea, 0xc2, 0xd9, 0x02 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpless %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xea, 0xc2, 0xd9, 0x01 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpltss %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xea, 0xc2, 0xd9, 0x04 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpneqss %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xea, 0xc2, 0xd9, 0x06 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpnless %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xea, 0xc2, 0xd9, 0x05 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpnltss %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xea, 0xc2, 0xd9, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpordss %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xea, 0xc2, 0xd9, 0x03 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpunordss %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xea, 0xc2, 0x5c, 0xcb, 0xfc, 0x00 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpeqss -4(%ebx, %ecx, 8), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xea, 0xc2, 0x5c, 0xcb, 0xfc, 0x02 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpless -4(%ebx, %ecx, 8), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xea, 0xc2, 0x5c, 0xcb, 0xfc, 0x01 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpltss -4(%ebx, %ecx, 8), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xea, 0xc2, 0x5c, 0xcb, 0xfc, 0x04 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpneqss -4(%ebx, %ecx, 8), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xea, 0xc2, 0x5c, 0xcb, 0xfc, 0x06 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpnless -4(%ebx, %ecx, 8), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xea, 0xc2, 0x5c, 0xcb, 0xfc, 0x05 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpnltss -4(%ebx, %ecx, 8), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xca, 0xc2, 0x54, 0xcb, 0xfc, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpordss -4(%ebx, %ecx, 8), %xmm6, %xmm2"
+  -
+    input:
+      bytes: [ 0xc5, 0xea, 0xc2, 0x5c, 0xcb, 0xfc, 0x03 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpunordss -4(%ebx, %ecx, 8), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xeb, 0xc2, 0xd9, 0x00 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpeqsd %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xeb, 0xc2, 0xd9, 0x02 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmplesd %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xeb, 0xc2, 0xd9, 0x01 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpltsd %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xeb, 0xc2, 0xd9, 0x04 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpneqsd %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xeb, 0xc2, 0xd9, 0x06 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpnlesd %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xeb, 0xc2, 0xd9, 0x05 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpnltsd %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xeb, 0xc2, 0xd9, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpordsd %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xeb, 0xc2, 0xd9, 0x03 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpunordsd %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xeb, 0xc2, 0x5c, 0xcb, 0xfc, 0x00 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpeqsd -4(%ebx, %ecx, 8), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xeb, 0xc2, 0x5c, 0xcb, 0xfc, 0x02 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmplesd -4(%ebx, %ecx, 8), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xeb, 0xc2, 0x5c, 0xcb, 0xfc, 0x01 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpltsd -4(%ebx, %ecx, 8), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xeb, 0xc2, 0x5c, 0xcb, 0xfc, 0x04 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpneqsd -4(%ebx, %ecx, 8), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xeb, 0xc2, 0x5c, 0xcb, 0xfc, 0x06 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpnlesd -4(%ebx, %ecx, 8), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xeb, 0xc2, 0x5c, 0xcb, 0xfc, 0x05 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpnltsd -4(%ebx, %ecx, 8), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xcb, 0xc2, 0x54, 0xcb, 0xfc, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpordsd -4(%ebx, %ecx, 8), %xmm6, %xmm2"
+  -
+    input:
+      bytes: [ 0xc5, 0xeb, 0xc2, 0x5c, 0xcb, 0xfc, 0x03 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpunordsd -4(%ebx, %ecx, 8), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xf8, 0x2e, 0xd1 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vucomiss %xmm1, %xmm2"
+  -
+    input:
+      bytes: [ 0xc5, 0xf8, 0x2e, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vucomiss (%eax), %xmm2"
+  -
+    input:
+      bytes: [ 0xc5, 0xf8, 0x2f, 0xd1 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcomiss %xmm1, %xmm2"
+  -
+    input:
+      bytes: [ 0xc5, 0xf8, 0x2f, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcomiss (%eax), %xmm2"
+  -
+    input:
+      bytes: [ 0xc5, 0xf9, 0x2e, 0xd1 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vucomisd %xmm1, %xmm2"
+  -
+    input:
+      bytes: [ 0xc5, 0xf9, 0x2e, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vucomisd (%eax), %xmm2"
+  -
+    input:
+      bytes: [ 0xc5, 0xf9, 0x2f, 0xd1 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcomisd %xmm1, %xmm2"
+  -
+    input:
+      bytes: [ 0xc5, 0xf9, 0x2f, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcomisd (%eax), %xmm2"
+  -
+    input:
+      bytes: [ 0xc5, 0xfa, 0x2c, 0xc1 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvttss2si %xmm1, %eax"
+  -
+    input:
+      bytes: [ 0xc5, 0xf2, 0x2a, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvtsi2ssl (%eax), %xmm1, %xmm2"
+  -
+    input:
+      bytes: [ 0xc5, 0xfb, 0x2c, 0xc1 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvttsd2si %xmm1, %eax"
+  -
+    input:
+      bytes: [ 0xc5, 0xfb, 0x2c, 0x01 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvttsd2si (%ecx), %eax"
+  -
+    input:
+      bytes: [ 0xc5, 0xf3, 0x2a, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvtsi2sdl (%eax), %xmm1, %xmm2"
+  -
+    input:
+      bytes: [ 0xc5, 0xf8, 0x28, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovaps (%eax), %xmm2"
+  -
+    input:
+      bytes: [ 0xc5, 0xf8, 0x28, 0xd1 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovaps %xmm1, %xmm2"
+  -
+    input:
+      bytes: [ 0xc5, 0xf8, 0x29, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovaps %xmm1, (%eax)"
+  -
+    input:
+      bytes: [ 0xc5, 0xf9, 0x28, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovapd (%eax), %xmm2"
+  -
+    input:
+      bytes: [ 0xc5, 0xf9, 0x28, 0xd1 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovapd %xmm1, %xmm2"
+  -
+    input:
+      bytes: [ 0xc5, 0xf9, 0x29, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovapd %xmm1, (%eax)"
+  -
+    input:
+      bytes: [ 0xc5, 0xf8, 0x10, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovups (%eax), %xmm2"
+  -
+    input:
+      bytes: [ 0xc5, 0xf8, 0x10, 0xd1 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovups %xmm1, %xmm2"
+  -
+    input:
+      bytes: [ 0xc5, 0xf8, 0x11, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovups %xmm1, (%eax)"
+  -
+    input:
+      bytes: [ 0xc5, 0xf9, 0x10, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovupd (%eax), %xmm2"
+  -
+    input:
+      bytes: [ 0xc5, 0xf9, 0x10, 0xd1 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovupd %xmm1, %xmm2"
+  -
+    input:
+      bytes: [ 0xc5, 0xf9, 0x11, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovupd %xmm1, (%eax)"
+  -
+    input:
+      bytes: [ 0xc5, 0xf8, 0x13, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovlps %xmm1, (%eax)"
+  -
+    input:
+      bytes: [ 0xc5, 0xe8, 0x12, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovlps (%eax), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xf9, 0x13, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovlpd %xmm1, (%eax)"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0x12, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovlpd (%eax), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xf8, 0x17, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovhps %xmm1, (%eax)"
+  -
+    input:
+      bytes: [ 0xc5, 0xe8, 0x16, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovhps (%eax), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xf9, 0x17, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovhpd %xmm1, (%eax)"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0x16, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovhpd (%eax), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe8, 0x16, 0xd9 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovlhps %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe8, 0x12, 0xd9 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovhlps %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xfa, 0x2d, 0xc1 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvtss2si %xmm1, %eax"
+  -
+    input:
+      bytes: [ 0xc5, 0xfa, 0x2d, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvtss2si (%eax), %ebx"
+  -
+    input:
+      bytes: [ 0xc5, 0xfa, 0x2d, 0xc1 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvtss2si %xmm1, %eax"
+  -
+    input:
+      bytes: [ 0xc5, 0xfa, 0x2d, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvtss2si (%eax), %ebx"
+  -
+    input:
+      bytes: [ 0xc5, 0xf8, 0x5b, 0xf5 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvtdq2ps %xmm5, %xmm6"
+  -
+    input:
+      bytes: [ 0xc5, 0xf8, 0x5b, 0x30 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvtdq2ps (%eax), %xmm6"
+  -
+    input:
+      bytes: [ 0xc5, 0xdb, 0x5a, 0xf2 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvtsd2ss %xmm2, %xmm4, %xmm6"
+  -
+    input:
+      bytes: [ 0xc5, 0xdb, 0x5a, 0x30 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvtsd2ss (%eax), %xmm4, %xmm6"
+  -
+    input:
+      bytes: [ 0xc5, 0xf9, 0x5b, 0xda ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvtps2dq %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xf9, 0x5b, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvtps2dq (%eax), %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xda, 0x5a, 0xf2 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvtss2sd %xmm2, %xmm4, %xmm6"
+  -
+    input:
+      bytes: [ 0xc5, 0xda, 0x5a, 0x30 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvtss2sd (%eax), %xmm4, %xmm6"
+  -
+    input:
+      bytes: [ 0xc5, 0xf8, 0x5b, 0xf4 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvtdq2ps %xmm4, %xmm6"
+  -
+    input:
+      bytes: [ 0xc5, 0xf8, 0x5b, 0x21 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvtdq2ps (%ecx), %xmm4"
+  -
+    input:
+      bytes: [ 0xc5, 0xfa, 0x5b, 0xda ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvttps2dq %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xfa, 0x5b, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvttps2dq (%eax), %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xf8, 0x5a, 0xda ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvtps2pd %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xf8, 0x5a, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvtps2pd (%eax), %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xf9, 0x5a, 0xda ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvtpd2ps %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xf9, 0x51, 0xd1 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vsqrtpd %xmm1, %xmm2"
+  -
+    input:
+      bytes: [ 0xc5, 0xf9, 0x51, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vsqrtpd (%eax), %xmm2"
+  -
+    input:
+      bytes: [ 0xc5, 0xf8, 0x51, 0xd1 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vsqrtps %xmm1, %xmm2"
+  -
+    input:
+      bytes: [ 0xc5, 0xf8, 0x51, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vsqrtps (%eax), %xmm2"
+  -
+    input:
+      bytes: [ 0xc5, 0xeb, 0x51, 0xd9 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vsqrtsd %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xeb, 0x51, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vsqrtsd (%eax), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xea, 0x51, 0xd9 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vsqrtss %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xea, 0x51, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vsqrtss (%eax), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xf8, 0x52, 0xd1 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vrsqrtps %xmm1, %xmm2"
+  -
+    input:
+      bytes: [ 0xc5, 0xf8, 0x52, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vrsqrtps (%eax), %xmm2"
+  -
+    input:
+      bytes: [ 0xc5, 0xea, 0x52, 0xd9 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vrsqrtss %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xea, 0x52, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vrsqrtss (%eax), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xf8, 0x53, 0xd1 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vrcpps %xmm1, %xmm2"
+  -
+    input:
+      bytes: [ 0xc5, 0xf8, 0x53, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vrcpps (%eax), %xmm2"
+  -
+    input:
+      bytes: [ 0xc5, 0xea, 0x53, 0xd9 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vrcpss %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xea, 0x53, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vrcpss (%eax), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xf9, 0xe7, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovntdq %xmm1, (%eax)"
+  -
+    input:
+      bytes: [ 0xc5, 0xf9, 0x2b, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovntpd %xmm1, (%eax)"
+  -
+    input:
+      bytes: [ 0xc5, 0xf8, 0x2b, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovntps %xmm1, (%eax)"
+  -
+    input:
+      bytes: [ 0xc5, 0xf8, 0xae, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vldmxcsr (%eax)"
+  -
+    input:
+      bytes: [ 0xc5, 0xf8, 0xae, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vstmxcsr (%eax)"
+  -
+    input:
+      bytes: [ 0xc5, 0xf8, 0xae, 0x15, 0xef, 0xbe, 0xad, 0xde ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vldmxcsr 0xdeadbeef"
+  -
+    input:
+      bytes: [ 0xc5, 0xf8, 0xae, 0x1d, 0xef, 0xbe, 0xad, 0xde ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vstmxcsr 0xdeadbeef"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0xf8, 0xd9 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpsubb %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0xf8, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpsubb (%eax), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0xf9, 0xd9 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpsubw %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0xf9, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpsubw (%eax), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0xfa, 0xd9 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpsubd %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0xfa, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpsubd (%eax), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0xfb, 0xd9 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpsubq %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0xfb, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpsubq (%eax), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0xe8, 0xd9 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpsubsb %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0xe8, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpsubsb (%eax), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0xe9, 0xd9 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpsubsw %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0xe9, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpsubsw (%eax), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0xd8, 0xd9 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpsubusb %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0xd8, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpsubusb (%eax), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0xd9, 0xd9 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpsubusw %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0xd9, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpsubusw (%eax), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0xfc, 0xd9 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpaddb %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0xfc, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpaddb (%eax), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0xfd, 0xd9 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpaddw %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0xfd, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpaddw (%eax), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0xfe, 0xd9 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpaddd %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0xfe, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpaddd (%eax), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0xd4, 0xd9 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpaddq %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0xd4, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpaddq (%eax), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0xec, 0xd9 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpaddsb %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0xec, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpaddsb (%eax), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0xed, 0xd9 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpaddsw %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0xed, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpaddsw (%eax), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0xdc, 0xd9 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpaddusb %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0xdc, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpaddusb (%eax), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0xdd, 0xd9 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpaddusw %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0xdd, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpaddusw (%eax), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0xe4, 0xd9 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmulhuw %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0xe4, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmulhuw (%eax), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0xe5, 0xd9 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmulhw %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0xe5, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmulhw (%eax), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0xd5, 0xd9 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmullw %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0xd5, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmullw (%eax), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0xf4, 0xd9 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmuludq %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0xf4, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmuludq (%eax), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0xe0, 0xd9 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpavgb %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0xe0, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpavgb (%eax), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0xe3, 0xd9 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpavgw %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0xe3, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpavgw (%eax), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0xea, 0xd9 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpminsw %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0xea, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpminsw (%eax), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0xda, 0xd9 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpminub %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0xda, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpminub (%eax), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0xee, 0xd9 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmaxsw %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0xee, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmaxsw (%eax), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0xde, 0xd9 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmaxub %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0xde, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmaxub (%eax), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0xf6, 0xd9 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpsadbw %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0xf6, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpsadbw (%eax), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0xf1, 0xd9 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpsllw %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0xf1, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpsllw (%eax), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0xf2, 0xd9 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpslld %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0xf2, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpslld (%eax), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0xf3, 0xd9 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpsllq %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0xf3, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpsllq (%eax), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0xe1, 0xd9 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpsraw %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0xe1, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpsraw (%eax), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0xe2, 0xd9 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpsrad %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0xe2, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpsrad (%eax), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0xd1, 0xd9 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpsrlw %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0xd1, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpsrlw (%eax), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0xd2, 0xd9 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpsrld %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0xd2, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpsrld (%eax), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0xd3, 0xd9 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpsrlq %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0xd3, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpsrlq (%eax), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe1, 0x72, 0xf2, 0x0a ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpslld $10, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe1, 0x73, 0xfa, 0x0a ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpslldq $10, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe1, 0x73, 0xf2, 0x0a ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpsllq $10, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe1, 0x71, 0xf2, 0x0a ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpsllw $10, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe1, 0x72, 0xe2, 0x0a ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpsrad $10, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe1, 0x71, 0xe2, 0x0a ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpsraw $10, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe1, 0x72, 0xd2, 0x0a ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpsrld $10, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe1, 0x73, 0xda, 0x0a ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpsrldq $10, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe1, 0x73, 0xd2, 0x0a ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpsrlq $10, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe1, 0x71, 0xd2, 0x0a ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpsrlw $10, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe1, 0x72, 0xf2, 0x0a ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpslld $10, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0xdb, 0xd9 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpand %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0xdb, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpand (%eax), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0xeb, 0xd9 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpor %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0xeb, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpor (%eax), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0xef, 0xd9 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpxor %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0xef, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpxor (%eax), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0xdf, 0xd9 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpandn %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0xdf, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpandn (%eax), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0x74, 0xd9 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpcmpeqb %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0x74, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpcmpeqb (%eax), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0x75, 0xd9 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpcmpeqw %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0x75, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpcmpeqw (%eax), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0x76, 0xd9 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpcmpeqd %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0x76, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpcmpeqd (%eax), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0x64, 0xd9 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpcmpgtb %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0x64, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpcmpgtb (%eax), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0x65, 0xd9 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpcmpgtw %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0x65, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpcmpgtw (%eax), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0x66, 0xd9 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpcmpgtd %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0x66, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpcmpgtd (%eax), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0x63, 0xd9 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpacksswb %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0x63, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpacksswb (%eax), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0x6b, 0xd9 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpackssdw %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0x6b, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpackssdw (%eax), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0x67, 0xd9 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpackuswb %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0x67, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpackuswb (%eax), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xf9, 0x70, 0xda, 0x04 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpshufd $4, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xf9, 0x70, 0x18, 0x04 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpshufd $4, (%eax), %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xfa, 0x70, 0xda, 0x04 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpshufhw $4, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xfa, 0x70, 0x18, 0x04 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpshufhw $4, (%eax), %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xfb, 0x70, 0xda, 0x04 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpshuflw $4, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xfb, 0x70, 0x18, 0x04 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpshuflw $4, (%eax), %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0x60, 0xd9 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpunpcklbw %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0x60, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpunpcklbw (%eax), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0x61, 0xd9 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpunpcklwd %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0x61, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpunpcklwd (%eax), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0x62, 0xd9 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpunpckldq %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0x62, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpunpckldq (%eax), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0x6c, 0xd9 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpunpcklqdq %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0x6c, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpunpcklqdq (%eax), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0x68, 0xd9 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpunpckhbw %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0x68, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpunpckhbw (%eax), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0x69, 0xd9 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpunpckhwd %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0x69, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpunpckhwd (%eax), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0x6a, 0xd9 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpunpckhdq %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0x6a, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpunpckhdq (%eax), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0x6d, 0xd9 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpunpckhqdq %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0x6d, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpunpckhqdq (%eax), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0xc4, 0xd8, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpinsrw $7, %eax, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0xc4, 0x18, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpinsrw $7, (%eax), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xf9, 0xc5, 0xc2, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpextrw $7, %xmm2, %eax"
+  -
+    input:
+      bytes: [ 0xc5, 0xf9, 0xd7, 0xc1 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmovmskb %xmm1, %eax"
+  -
+    input:
+      bytes: [ 0xc5, 0xf9, 0xf7, 0xd1 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmaskmovdqu %xmm1, %xmm2"
+  -
+    input:
+      bytes: [ 0xc5, 0xf9, 0x7e, 0xc8 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovd %xmm1, %eax"
+  -
+    input:
+      bytes: [ 0xc5, 0xf9, 0x7e, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovd %xmm1, (%eax)"
+  -
+    input:
+      bytes: [ 0xc5, 0xf9, 0x6e, 0xc8 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovd %eax, %xmm1"
+  -
+    input:
+      bytes: [ 0xc5, 0xf9, 0x6e, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovd (%eax), %xmm1"
+  -
+    input:
+      bytes: [ 0xc5, 0xf9, 0xd6, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovq %xmm1, (%eax)"
+  -
+    input:
+      bytes: [ 0xc5, 0xfa, 0x7e, 0xd1 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovq %xmm1, %xmm2"
+  -
+    input:
+      bytes: [ 0xc5, 0xfa, 0x7e, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovq (%eax), %xmm1"
+  -
+    input:
+      bytes: [ 0xc5, 0xfb, 0xe6, 0xd1 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvtpd2dq %xmm1, %xmm2"
+  -
+    input:
+      bytes: [ 0xc5, 0xfa, 0xe6, 0xd1 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvtdq2pd %xmm1, %xmm2"
+  -
+    input:
+      bytes: [ 0xc5, 0xfa, 0xe6, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvtdq2pd (%eax), %xmm2"
+  -
+    input:
+      bytes: [ 0xc5, 0xfa, 0x16, 0xd1 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovshdup %xmm1, %xmm2"
+  -
+    input:
+      bytes: [ 0xc5, 0xfa, 0x16, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovshdup (%eax), %xmm2"
+  -
+    input:
+      bytes: [ 0xc5, 0xfa, 0x12, 0xd1 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovsldup %xmm1, %xmm2"
+  -
+    input:
+      bytes: [ 0xc5, 0xfa, 0x12, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovsldup (%eax), %xmm2"
+  -
+    input:
+      bytes: [ 0xc5, 0xfb, 0x12, 0xd1 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovddup %xmm1, %xmm2"
+  -
+    input:
+      bytes: [ 0xc5, 0xfb, 0x12, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovddup (%eax), %xmm2"
+  -
+    input:
+      bytes: [ 0xc5, 0xeb, 0xd0, 0xd9 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vaddsubps %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xf3, 0xd0, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vaddsubps (%eax), %xmm1, %xmm2"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0xd0, 0xd9 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vaddsubpd %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xf1, 0xd0, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vaddsubpd (%eax), %xmm1, %xmm2"
+  -
+    input:
+      bytes: [ 0xc5, 0xeb, 0x7c, 0xd9 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vhaddps %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xeb, 0x7c, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vhaddps (%eax), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0x7c, 0xd9 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vhaddpd %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0x7c, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vhaddpd (%eax), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xeb, 0x7d, 0xd9 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vhsubps %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xeb, 0x7d, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vhsubps (%eax), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0x7d, 0xd9 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vhsubpd %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0x7d, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vhsubpd (%eax), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x79, 0x1c, 0xd1 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpabsb %xmm1, %xmm2"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x79, 0x1c, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpabsb (%eax), %xmm2"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x79, 0x1d, 0xd1 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpabsw %xmm1, %xmm2"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x79, 0x1d, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpabsw (%eax), %xmm2"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x79, 0x1e, 0xd1 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpabsd %xmm1, %xmm2"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x79, 0x1e, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpabsd (%eax), %xmm2"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x69, 0x01, 0xd9 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vphaddw %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x69, 0x01, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vphaddw (%eax), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x69, 0x02, 0xd9 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vphaddd %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x69, 0x02, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vphaddd (%eax), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x69, 0x03, 0xd9 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vphaddsw %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x69, 0x03, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vphaddsw (%eax), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x69, 0x05, 0xd9 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vphsubw %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x69, 0x05, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vphsubw (%eax), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x69, 0x06, 0xd9 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vphsubd %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x69, 0x06, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vphsubd (%eax), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x69, 0x07, 0xd9 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vphsubsw %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x69, 0x07, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vphsubsw (%eax), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x69, 0x04, 0xd9 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmaddubsw %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x69, 0x04, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmaddubsw (%eax), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x69, 0x00, 0xd9 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpshufb %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x69, 0x00, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpshufb (%eax), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x69, 0x08, 0xd9 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpsignb %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x69, 0x08, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpsignb (%eax), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x69, 0x09, 0xd9 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpsignw %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x69, 0x09, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpsignw (%eax), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x69, 0x0a, 0xd9 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpsignd %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x69, 0x0a, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpsignd (%eax), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x69, 0x0b, 0xd9 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmulhrsw %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x69, 0x0b, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmulhrsw (%eax), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x69, 0x0f, 0xd9, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpalignr $7, %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x69, 0x0f, 0x18, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpalignr $7, (%eax), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x69, 0x0b, 0xd9, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vroundsd $7, %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x69, 0x0b, 0x18, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vroundsd $7, (%eax), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x69, 0x0a, 0xd9, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vroundss $7, %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x69, 0x0a, 0x18, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vroundss $7, (%eax), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x79, 0x09, 0xda, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vroundpd $7, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x79, 0x09, 0x18, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vroundpd $7, (%eax), %xmm3"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x79, 0x08, 0xda, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vroundps $7, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x79, 0x08, 0x18, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vroundps $7, (%eax), %xmm3"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x79, 0x41, 0xda ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vphminposuw %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x79, 0x41, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vphminposuw (%eax), %xmm2"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x61, 0x2b, 0xca ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpackusdw %xmm2, %xmm3, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x69, 0x2b, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpackusdw (%eax), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x61, 0x29, 0xca ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpcmpeqq %xmm2, %xmm3, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x69, 0x29, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpcmpeqq (%eax), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x61, 0x38, 0xca ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpminsb %xmm2, %xmm3, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x69, 0x38, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpminsb (%eax), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x61, 0x39, 0xca ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpminsd %xmm2, %xmm3, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x69, 0x39, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpminsd (%eax), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x61, 0x3b, 0xca ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpminud %xmm2, %xmm3, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x69, 0x3b, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpminud (%eax), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x61, 0x3a, 0xca ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpminuw %xmm2, %xmm3, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x69, 0x3a, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpminuw (%eax), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x61, 0x3c, 0xca ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmaxsb %xmm2, %xmm3, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x69, 0x3c, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmaxsb (%eax), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x61, 0x3d, 0xca ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmaxsd %xmm2, %xmm3, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x69, 0x3d, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmaxsd (%eax), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x61, 0x3f, 0xca ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmaxud %xmm2, %xmm3, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x69, 0x3f, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmaxud (%eax), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x61, 0x3e, 0xca ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmaxuw %xmm2, %xmm3, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x69, 0x3e, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmaxuw (%eax), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x61, 0x28, 0xca ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmuldq %xmm2, %xmm3, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x69, 0x28, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmuldq (%eax), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x51, 0x40, 0xca ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmulld %xmm2, %xmm5, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x51, 0x40, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmulld (%eax), %xmm5, %xmm3"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x51, 0x0c, 0xca, 0x03 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vblendps $3, %xmm2, %xmm5, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x51, 0x0c, 0x08, 0x03 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vblendps $3, (%eax), %xmm5, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x51, 0x0d, 0xca, 0x03 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vblendpd $3, %xmm2, %xmm5, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x51, 0x0d, 0x08, 0x03 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vblendpd $3, (%eax), %xmm5, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x51, 0x0e, 0xca, 0x03 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpblendw $3, %xmm2, %xmm5, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x51, 0x0e, 0x08, 0x03 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpblendw $3, (%eax), %xmm5, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x51, 0x42, 0xca, 0x03 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmpsadbw $3, %xmm2, %xmm5, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x51, 0x42, 0x08, 0x03 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmpsadbw $3, (%eax), %xmm5, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x51, 0x40, 0xca, 0x03 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vdpps $3, %xmm2, %xmm5, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x51, 0x40, 0x08, 0x03 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vdpps $3, (%eax), %xmm5, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x51, 0x41, 0xca, 0x03 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vdppd $3, %xmm2, %xmm5, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x51, 0x41, 0x08, 0x03 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vdppd $3, (%eax), %xmm5, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x71, 0x4b, 0xdd, 0x20 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vblendvpd %xmm2, %xmm5, %xmm1, %xmm3"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x71, 0x4b, 0x18, 0x20 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vblendvpd %xmm2, (%eax), %xmm1, %xmm3"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x71, 0x4a, 0xdd, 0x20 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vblendvps %xmm2, %xmm5, %xmm1, %xmm3"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x71, 0x4a, 0x18, 0x20 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vblendvps %xmm2, (%eax), %xmm1, %xmm3"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x71, 0x4c, 0xdd, 0x20 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpblendvb %xmm2, %xmm5, %xmm1, %xmm3"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x71, 0x4c, 0x18, 0x20 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpblendvb %xmm2, (%eax), %xmm1, %xmm3"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x79, 0x20, 0xea ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmovsxbw %xmm2, %xmm5"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x79, 0x20, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmovsxbw (%eax), %xmm2"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x79, 0x23, 0xea ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmovsxwd %xmm2, %xmm5"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x79, 0x23, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmovsxwd (%eax), %xmm2"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x79, 0x25, 0xea ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmovsxdq %xmm2, %xmm5"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x79, 0x25, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmovsxdq (%eax), %xmm2"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x79, 0x30, 0xea ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmovzxbw %xmm2, %xmm5"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x79, 0x30, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmovzxbw (%eax), %xmm2"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x79, 0x33, 0xea ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmovzxwd %xmm2, %xmm5"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x79, 0x33, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmovzxwd (%eax), %xmm2"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x79, 0x35, 0xea ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmovzxdq %xmm2, %xmm5"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x79, 0x35, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmovzxdq (%eax), %xmm2"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x79, 0x22, 0xea ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmovsxbq %xmm2, %xmm5"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x79, 0x22, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmovsxbq (%eax), %xmm2"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x79, 0x32, 0xea ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmovzxbq %xmm2, %xmm5"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x79, 0x32, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmovzxbq (%eax), %xmm2"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x79, 0x21, 0xea ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmovsxbd %xmm2, %xmm5"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x79, 0x21, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmovsxbd (%eax), %xmm2"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x79, 0x24, 0xea ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmovsxwq %xmm2, %xmm5"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x79, 0x24, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmovsxwq (%eax), %xmm2"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x79, 0x31, 0xea ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmovzxbd %xmm2, %xmm5"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x79, 0x31, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmovzxbd (%eax), %xmm2"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x79, 0x34, 0xea ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmovzxwq %xmm2, %xmm5"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x79, 0x34, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmovzxwq (%eax), %xmm2"
+  -
+    input:
+      bytes: [ 0xc5, 0xf9, 0xc5, 0xc2, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpextrw $7, %xmm2, %eax"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x79, 0x15, 0x10, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpextrw $7, %xmm2, (%eax)"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x79, 0x16, 0xd0, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpextrd $7, %xmm2, %eax"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x79, 0x16, 0x10, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpextrd $7, %xmm2, (%eax)"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x79, 0x14, 0xd0, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpextrb $7, %xmm2, %eax"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x79, 0x14, 0x10, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpextrb $7, %xmm2, (%eax)"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x79, 0x17, 0x10, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vextractps $7, %xmm2, (%eax)"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x79, 0x17, 0xd0, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vextractps $7, %xmm2, %eax"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0xc4, 0xe8, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpinsrw $7, %eax, %xmm2, %xmm5"
+  -
+    input:
+      bytes: [ 0xc5, 0xe9, 0xc4, 0x28, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpinsrw $7, (%eax), %xmm2, %xmm5"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x69, 0x20, 0xe8, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpinsrb $7, %eax, %xmm2, %xmm5"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x69, 0x20, 0x28, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpinsrb $7, (%eax), %xmm2, %xmm5"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x69, 0x22, 0xe8, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpinsrd $7, %eax, %xmm2, %xmm5"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x69, 0x22, 0x28, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpinsrd $7, (%eax), %xmm2, %xmm5"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x51, 0x21, 0xca, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vinsertps $7, %xmm2, %xmm5, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x51, 0x21, 0x08, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vinsertps $7, (%eax), %xmm5, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x79, 0x17, 0xea ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vptest %xmm2, %xmm5"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x79, 0x17, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vptest (%eax), %xmm2"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x79, 0x2a, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovntdqa (%eax), %xmm2"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x51, 0x37, 0xca ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpcmpgtq %xmm2, %xmm5, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x51, 0x37, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpcmpgtq (%eax), %xmm5, %xmm3"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x79, 0x62, 0xea, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpcmpistrm $7, %xmm2, %xmm5"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x79, 0x62, 0x28, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpcmpistrm $7, (%eax), %xmm5"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x79, 0x60, 0xea, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpcmpestrm $7, %xmm2, %xmm5"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x79, 0x60, 0x28, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpcmpestrm $7, (%eax), %xmm5"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x79, 0x63, 0xea, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpcmpistri $7, %xmm2, %xmm5"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x79, 0x63, 0x28, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpcmpistri $7, (%eax), %xmm5"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x79, 0x61, 0xea, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpcmpestri $7, %xmm2, %xmm5"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x79, 0x61, 0x28, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpcmpestri $7, (%eax), %xmm5"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x79, 0xdb, 0xea ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vaesimc %xmm2, %xmm5"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x79, 0xdb, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vaesimc (%eax), %xmm2"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x51, 0xdc, 0xca ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vaesenc %xmm2, %xmm5, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x51, 0xdc, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vaesenc (%eax), %xmm5, %xmm3"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x51, 0xdd, 0xca ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vaesenclast %xmm2, %xmm5, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x51, 0xdd, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vaesenclast (%eax), %xmm5, %xmm3"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x51, 0xde, 0xca ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vaesdec %xmm2, %xmm5, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x51, 0xde, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vaesdec (%eax), %xmm5, %xmm3"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x51, 0xdf, 0xca ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vaesdeclast %xmm2, %xmm5, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x51, 0xdf, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vaesdeclast (%eax), %xmm5, %xmm3"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x79, 0xdf, 0xea, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vaeskeygenassist $7, %xmm2, %xmm5"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x79, 0xdf, 0x28, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vaeskeygenassist $7, (%eax), %xmm5"
+  -
+    input:
+      bytes: [ 0xc5, 0xe8, 0xc2, 0xd9, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpeq_uqps %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe8, 0xc2, 0xd9, 0x09 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpngeps %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe8, 0xc2, 0xd9, 0x0a ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpngtps %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe8, 0xc2, 0xd9, 0x0b ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpfalseps %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe8, 0xc2, 0xd9, 0x0c ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpneq_oqps %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe8, 0xc2, 0xd9, 0x0d ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpgeps %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe8, 0xc2, 0xd9, 0x0e ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpgtps %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe8, 0xc2, 0xd9, 0x0f ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmptrueps %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe8, 0xc2, 0xd9, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpeq_osps %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe8, 0xc2, 0xd9, 0x11 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmplt_oqps %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe8, 0xc2, 0xd9, 0x12 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmple_oqps %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe8, 0xc2, 0xd9, 0x13 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpunord_sps %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe8, 0xc2, 0xd9, 0x14 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpneq_usps %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe8, 0xc2, 0xd9, 0x15 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpnlt_uqps %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe8, 0xc2, 0xd9, 0x16 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpnle_uqps %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe8, 0xc2, 0xd9, 0x17 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpord_sps %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe8, 0xc2, 0xd9, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpeq_usps %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe8, 0xc2, 0xd9, 0x19 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpnge_uqps %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe8, 0xc2, 0xd9, 0x1a ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpngt_uqps %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe8, 0xc2, 0xd9, 0x1b ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpfalse_osps %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe8, 0xc2, 0xd9, 0x1c ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpneq_osps %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe8, 0xc2, 0xd9, 0x1d ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpge_oqps %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe8, 0xc2, 0xd9, 0x1e ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpgt_oqps %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xe8, 0xc2, 0xd9, 0x1f ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmptrue_usps %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xfc, 0x28, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovaps (%eax), %ymm2"
+  -
+    input:
+      bytes: [ 0xc5, 0xfc, 0x28, 0xd1 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovaps %ymm1, %ymm2"
+  -
+    input:
+      bytes: [ 0xc5, 0xfc, 0x29, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovaps %ymm1, (%eax)"
+  -
+    input:
+      bytes: [ 0xc5, 0xfd, 0x28, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovapd (%eax), %ymm2"
+  -
+    input:
+      bytes: [ 0xc5, 0xfd, 0x28, 0xd1 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovapd %ymm1, %ymm2"
+  -
+    input:
+      bytes: [ 0xc5, 0xfd, 0x29, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovapd %ymm1, (%eax)"
+  -
+    input:
+      bytes: [ 0xc5, 0xfc, 0x10, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovups (%eax), %ymm2"
+  -
+    input:
+      bytes: [ 0xc5, 0xfc, 0x10, 0xd1 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovups %ymm1, %ymm2"
+  -
+    input:
+      bytes: [ 0xc5, 0xfc, 0x11, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovups %ymm1, (%eax)"
+  -
+    input:
+      bytes: [ 0xc5, 0xfd, 0x10, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovupd (%eax), %ymm2"
+  -
+    input:
+      bytes: [ 0xc5, 0xfd, 0x10, 0xd1 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovupd %ymm1, %ymm2"
+  -
+    input:
+      bytes: [ 0xc5, 0xfd, 0x11, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovupd %ymm1, (%eax)"
+  -
+    input:
+      bytes: [ 0xc5, 0xec, 0x15, 0xe1 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vunpckhps %ymm1, %ymm2, %ymm4"
+  -
+    input:
+      bytes: [ 0xc5, 0xed, 0x15, 0xe1 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vunpckhpd %ymm1, %ymm2, %ymm4"
+  -
+    input:
+      bytes: [ 0xc5, 0xec, 0x14, 0xe1 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vunpcklps %ymm1, %ymm2, %ymm4"
+  -
+    input:
+      bytes: [ 0xc5, 0xed, 0x14, 0xe1 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vunpcklpd %ymm1, %ymm2, %ymm4"
+  -
+    input:
+      bytes: [ 0xc5, 0xec, 0x15, 0x6c, 0xcb, 0xfc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vunpckhps -4(%ebx, %ecx, 8), %ymm2, %ymm5"
+  -
+    input:
+      bytes: [ 0xc5, 0xed, 0x15, 0x6c, 0xcb, 0xfc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vunpckhpd -4(%ebx, %ecx, 8), %ymm2, %ymm5"
+  -
+    input:
+      bytes: [ 0xc5, 0xec, 0x14, 0x6c, 0xcb, 0xfc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vunpcklps -4(%ebx, %ecx, 8), %ymm2, %ymm5"
+  -
+    input:
+      bytes: [ 0xc5, 0xed, 0x14, 0x6c, 0xcb, 0xfc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vunpcklpd -4(%ebx, %ecx, 8), %ymm2, %ymm5"
+  -
+    input:
+      bytes: [ 0xc5, 0xfd, 0xe7, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovntdq %ymm1, (%eax)"
+  -
+    input:
+      bytes: [ 0xc5, 0xfd, 0x2b, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovntpd %ymm1, (%eax)"
+  -
+    input:
+      bytes: [ 0xc5, 0xfc, 0x2b, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovntps %ymm1, (%eax)"
+  -
+    input:
+      bytes: [ 0xc5, 0xf8, 0x50, 0xc2 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovmskps %xmm2, %eax"
+  -
+    input:
+      bytes: [ 0xc5, 0xf9, 0x50, 0xc2 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovmskpd %xmm2, %eax"
+  -
+    input:
+      bytes: [ 0xc5, 0xdc, 0x5f, 0xf2 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmaxps %ymm2, %ymm4, %ymm6"
+  -
+    input:
+      bytes: [ 0xc5, 0xdd, 0x5f, 0xf2 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmaxpd %ymm2, %ymm4, %ymm6"
+  -
+    input:
+      bytes: [ 0xc5, 0xdc, 0x5d, 0xf2 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vminps %ymm2, %ymm4, %ymm6"
+  -
+    input:
+      bytes: [ 0xc5, 0xdd, 0x5d, 0xf2 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vminpd %ymm2, %ymm4, %ymm6"
+  -
+    input:
+      bytes: [ 0xc5, 0xdc, 0x5c, 0xf2 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vsubps %ymm2, %ymm4, %ymm6"
+  -
+    input:
+      bytes: [ 0xc5, 0xdd, 0x5c, 0xf2 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vsubpd %ymm2, %ymm4, %ymm6"
+  -
+    input:
+      bytes: [ 0xc5, 0xdc, 0x5e, 0xf2 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vdivps %ymm2, %ymm4, %ymm6"
+  -
+    input:
+      bytes: [ 0xc5, 0xdd, 0x5e, 0xf2 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vdivpd %ymm2, %ymm4, %ymm6"
+  -
+    input:
+      bytes: [ 0xc5, 0xdc, 0x58, 0xf2 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vaddps %ymm2, %ymm4, %ymm6"
+  -
+    input:
+      bytes: [ 0xc5, 0xdd, 0x58, 0xf2 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vaddpd %ymm2, %ymm4, %ymm6"
+  -
+    input:
+      bytes: [ 0xc5, 0xdc, 0x59, 0xf2 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmulps %ymm2, %ymm4, %ymm6"
+  -
+    input:
+      bytes: [ 0xc5, 0xdd, 0x59, 0xf2 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmulpd %ymm2, %ymm4, %ymm6"
+  -
+    input:
+      bytes: [ 0xc5, 0xdc, 0x5f, 0x30 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmaxps (%eax), %ymm4, %ymm6"
+  -
+    input:
+      bytes: [ 0xc5, 0xdd, 0x5f, 0x30 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmaxpd (%eax), %ymm4, %ymm6"
+  -
+    input:
+      bytes: [ 0xc5, 0xdc, 0x5d, 0x30 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vminps (%eax), %ymm4, %ymm6"
+  -
+    input:
+      bytes: [ 0xc5, 0xdd, 0x5d, 0x30 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vminpd (%eax), %ymm4, %ymm6"
+  -
+    input:
+      bytes: [ 0xc5, 0xdc, 0x5c, 0x30 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vsubps (%eax), %ymm4, %ymm6"
+  -
+    input:
+      bytes: [ 0xc5, 0xdd, 0x5c, 0x30 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vsubpd (%eax), %ymm4, %ymm6"
+  -
+    input:
+      bytes: [ 0xc5, 0xdc, 0x5e, 0x30 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vdivps (%eax), %ymm4, %ymm6"
+  -
+    input:
+      bytes: [ 0xc5, 0xdd, 0x5e, 0x30 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vdivpd (%eax), %ymm4, %ymm6"
+  -
+    input:
+      bytes: [ 0xc5, 0xdc, 0x58, 0x30 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vaddps (%eax), %ymm4, %ymm6"
+  -
+    input:
+      bytes: [ 0xc5, 0xdd, 0x58, 0x30 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vaddpd (%eax), %ymm4, %ymm6"
+  -
+    input:
+      bytes: [ 0xc5, 0xdc, 0x59, 0x30 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmulps (%eax), %ymm4, %ymm6"
+  -
+    input:
+      bytes: [ 0xc5, 0xdd, 0x59, 0x30 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmulpd (%eax), %ymm4, %ymm6"
+  -
+    input:
+      bytes: [ 0xc5, 0xfd, 0x51, 0xd1 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vsqrtpd %ymm1, %ymm2"
+  -
+    input:
+      bytes: [ 0xc5, 0xfd, 0x51, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vsqrtpd (%eax), %ymm2"
+  -
+    input:
+      bytes: [ 0xc5, 0xfc, 0x51, 0xd1 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vsqrtps %ymm1, %ymm2"
+  -
+    input:
+      bytes: [ 0xc5, 0xfc, 0x51, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vsqrtps (%eax), %ymm2"
+  -
+    input:
+      bytes: [ 0xc5, 0xfc, 0x52, 0xd1 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vrsqrtps %ymm1, %ymm2"
+  -
+    input:
+      bytes: [ 0xc5, 0xfc, 0x52, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vrsqrtps (%eax), %ymm2"
+  -
+    input:
+      bytes: [ 0xc5, 0xfc, 0x53, 0xd1 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vrcpps %ymm1, %ymm2"
+  -
+    input:
+      bytes: [ 0xc5, 0xfc, 0x53, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vrcpps (%eax), %ymm2"
+  -
+    input:
+      bytes: [ 0xc5, 0xdc, 0x54, 0xf2 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vandps %ymm2, %ymm4, %ymm6"
+  -
+    input:
+      bytes: [ 0xc5, 0xdd, 0x54, 0xf2 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vandpd %ymm2, %ymm4, %ymm6"
+  -
+    input:
+      bytes: [ 0xc5, 0xec, 0x54, 0x6c, 0xcb, 0xfc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vandps -4(%ebx, %ecx, 8), %ymm2, %ymm5"
+  -
+    input:
+      bytes: [ 0xc5, 0xed, 0x54, 0x6c, 0xcb, 0xfc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vandpd -4(%ebx, %ecx, 8), %ymm2, %ymm5"
+  -
+    input:
+      bytes: [ 0xc5, 0xdc, 0x56, 0xf2 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vorps %ymm2, %ymm4, %ymm6"
+  -
+    input:
+      bytes: [ 0xc5, 0xdd, 0x56, 0xf2 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vorpd %ymm2, %ymm4, %ymm6"
+  -
+    input:
+      bytes: [ 0xc5, 0xec, 0x56, 0x6c, 0xcb, 0xfc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vorps -4(%ebx, %ecx, 8), %ymm2, %ymm5"
+  -
+    input:
+      bytes: [ 0xc5, 0xed, 0x56, 0x6c, 0xcb, 0xfc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vorpd -4(%ebx, %ecx, 8), %ymm2, %ymm5"
+  -
+    input:
+      bytes: [ 0xc5, 0xdc, 0x57, 0xf2 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vxorps %ymm2, %ymm4, %ymm6"
+  -
+    input:
+      bytes: [ 0xc5, 0xdd, 0x57, 0xf2 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vxorpd %ymm2, %ymm4, %ymm6"
+  -
+    input:
+      bytes: [ 0xc5, 0xec, 0x57, 0x6c, 0xcb, 0xfc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vxorps -4(%ebx, %ecx, 8), %ymm2, %ymm5"
+  -
+    input:
+      bytes: [ 0xc5, 0xed, 0x57, 0x6c, 0xcb, 0xfc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vxorpd -4(%ebx, %ecx, 8), %ymm2, %ymm5"
+  -
+    input:
+      bytes: [ 0xc5, 0xdc, 0x55, 0xf2 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vandnps %ymm2, %ymm4, %ymm6"
+  -
+    input:
+      bytes: [ 0xc5, 0xdd, 0x55, 0xf2 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vandnpd %ymm2, %ymm4, %ymm6"
+  -
+    input:
+      bytes: [ 0xc5, 0xec, 0x55, 0x6c, 0xcb, 0xfc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vandnps -4(%ebx, %ecx, 8), %ymm2, %ymm5"
+  -
+    input:
+      bytes: [ 0xc5, 0xed, 0x55, 0x6c, 0xcb, 0xfc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vandnpd -4(%ebx, %ecx, 8), %ymm2, %ymm5"
+  -
+    input:
+      bytes: [ 0xc5, 0xfc, 0x5a, 0xd3 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvtps2pd %xmm3, %ymm2"
+  -
+    input:
+      bytes: [ 0xc5, 0xfc, 0x5a, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvtps2pd (%eax), %ymm2"
+  -
+    input:
+      bytes: [ 0xc5, 0xfe, 0xe6, 0xd3 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvtdq2pd %xmm3, %ymm2"
+  -
+    input:
+      bytes: [ 0xc5, 0xfe, 0xe6, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvtdq2pd (%eax), %ymm2"
+  -
+    input:
+      bytes: [ 0xc5, 0xfc, 0x5b, 0xea ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvtdq2ps %ymm2, %ymm5"
+  -
+    input:
+      bytes: [ 0xc5, 0xfc, 0x5b, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvtdq2ps (%eax), %ymm2"
+  -
+    input:
+      bytes: [ 0xc5, 0xfd, 0x5b, 0xea ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvtps2dq %ymm2, %ymm5"
+  -
+    input:
+      bytes: [ 0xc5, 0xfd, 0x5b, 0x28 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvtps2dq (%eax), %ymm5"
+  -
+    input:
+      bytes: [ 0xc5, 0xfe, 0x5b, 0xea ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvttps2dq %ymm2, %ymm5"
+  -
+    input:
+      bytes: [ 0xc5, 0xfe, 0x5b, 0x28 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvttps2dq (%eax), %ymm5"
+  -
+    input:
+      bytes: [ 0xc5, 0xf9, 0xe6, 0xe9 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvttpd2dq %xmm1, %xmm5"
+  -
+    input:
+      bytes: [ 0xc5, 0xfd, 0xe6, 0xea ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvttpd2dq %ymm2, %xmm5"
+  -
+    input:
+      bytes: [ 0xc5, 0xf9, 0xe6, 0xe9 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvttpd2dq %xmm1, %xmm5"
+  -
+    input:
+      bytes: [ 0xc5, 0xf9, 0xe6, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvttpd2dqx (%eax), %xmm1"
+  -
+    input:
+      bytes: [ 0xc5, 0xfd, 0xe6, 0xca ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvttpd2dq %ymm2, %xmm1"
+  -
+    input:
+      bytes: [ 0xc5, 0xfd, 0xe6, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvttpd2dqy (%eax), %xmm1"
+  -
+    input:
+      bytes: [ 0xc5, 0xfd, 0x5a, 0xea ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvtpd2ps %ymm2, %xmm5"
+  -
+    input:
+      bytes: [ 0xc5, 0xf9, 0x5a, 0xe9 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvtpd2ps %xmm1, %xmm5"
+  -
+    input:
+      bytes: [ 0xc5, 0xf9, 0x5a, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvtpd2psx (%eax), %xmm1"
+  -
+    input:
+      bytes: [ 0xc5, 0xfd, 0x5a, 0xca ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvtpd2ps %ymm2, %xmm1"
+  -
+    input:
+      bytes: [ 0xc5, 0xfd, 0x5a, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvtpd2psy (%eax), %xmm1"
+  -
+    input:
+      bytes: [ 0xc5, 0xff, 0xe6, 0xea ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvtpd2dq %ymm2, %xmm5"
+  -
+    input:
+      bytes: [ 0xc5, 0xff, 0xe6, 0xca ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvtpd2dq %ymm2, %xmm1"
+  -
+    input:
+      bytes: [ 0xc5, 0xff, 0xe6, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvtpd2dqy (%eax), %xmm1"
+  -
+    input:
+      bytes: [ 0xc5, 0xfb, 0xe6, 0xe9 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvtpd2dq %xmm1, %xmm5"
+  -
+    input:
+      bytes: [ 0xc5, 0xfb, 0xe6, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvtpd2dqx (%eax), %xmm1"
+  -
+    input:
+      bytes: [ 0xc5, 0xec, 0xc2, 0xd9, 0x00 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpeqps %ymm1, %ymm2, %ymm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xec, 0xc2, 0xd9, 0x02 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpleps %ymm1, %ymm2, %ymm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xec, 0xc2, 0xd9, 0x01 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpltps %ymm1, %ymm2, %ymm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xec, 0xc2, 0xd9, 0x04 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpneqps %ymm1, %ymm2, %ymm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xec, 0xc2, 0xd9, 0x06 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpnleps %ymm1, %ymm2, %ymm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xec, 0xc2, 0xd9, 0x05 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpnltps %ymm1, %ymm2, %ymm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xec, 0xc2, 0xd9, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpordps %ymm1, %ymm2, %ymm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xec, 0xc2, 0xd9, 0x03 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpunordps %ymm1, %ymm2, %ymm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xec, 0xc2, 0x5c, 0xcb, 0xfc, 0x00 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpeqps -4(%ebx, %ecx, 8), %ymm2, %ymm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xec, 0xc2, 0x5c, 0xcb, 0xfc, 0x02 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpleps -4(%ebx, %ecx, 8), %ymm2, %ymm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xec, 0xc2, 0x5c, 0xcb, 0xfc, 0x01 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpltps -4(%ebx, %ecx, 8), %ymm2, %ymm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xec, 0xc2, 0x5c, 0xcb, 0xfc, 0x04 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpneqps -4(%ebx, %ecx, 8), %ymm2, %ymm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xec, 0xc2, 0x5c, 0xcb, 0xfc, 0x06 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpnleps -4(%ebx, %ecx, 8), %ymm2, %ymm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xec, 0xc2, 0x5c, 0xcb, 0xfc, 0x05 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpnltps -4(%ebx, %ecx, 8), %ymm2, %ymm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xcc, 0xc2, 0x54, 0xcb, 0xfc, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpordps -4(%ebx, %ecx, 8), %ymm6, %ymm2"
+  -
+    input:
+      bytes: [ 0xc5, 0xec, 0xc2, 0x5c, 0xcb, 0xfc, 0x03 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpunordps -4(%ebx, %ecx, 8), %ymm2, %ymm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xed, 0xc2, 0xd9, 0x00 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpeqpd %ymm1, %ymm2, %ymm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xed, 0xc2, 0xd9, 0x02 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmplepd %ymm1, %ymm2, %ymm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xed, 0xc2, 0xd9, 0x01 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpltpd %ymm1, %ymm2, %ymm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xed, 0xc2, 0xd9, 0x04 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpneqpd %ymm1, %ymm2, %ymm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xed, 0xc2, 0xd9, 0x06 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpnlepd %ymm1, %ymm2, %ymm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xed, 0xc2, 0xd9, 0x05 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpnltpd %ymm1, %ymm2, %ymm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xed, 0xc2, 0xd9, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpordpd %ymm1, %ymm2, %ymm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xed, 0xc2, 0xd9, 0x03 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpunordpd %ymm1, %ymm2, %ymm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xed, 0xc2, 0x5c, 0xcb, 0xfc, 0x00 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpeqpd -4(%ebx, %ecx, 8), %ymm2, %ymm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xed, 0xc2, 0x5c, 0xcb, 0xfc, 0x02 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmplepd -4(%ebx, %ecx, 8), %ymm2, %ymm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xed, 0xc2, 0x5c, 0xcb, 0xfc, 0x01 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpltpd -4(%ebx, %ecx, 8), %ymm2, %ymm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xed, 0xc2, 0x5c, 0xcb, 0xfc, 0x04 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpneqpd -4(%ebx, %ecx, 8), %ymm2, %ymm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xed, 0xc2, 0x5c, 0xcb, 0xfc, 0x06 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpnlepd -4(%ebx, %ecx, 8), %ymm2, %ymm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xed, 0xc2, 0x5c, 0xcb, 0xfc, 0x05 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpnltpd -4(%ebx, %ecx, 8), %ymm2, %ymm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xcd, 0xc2, 0x54, 0xcb, 0xfc, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpordpd -4(%ebx, %ecx, 8), %ymm6, %ymm2"
+  -
+    input:
+      bytes: [ 0xc5, 0xed, 0xc2, 0x5c, 0xcb, 0xfc, 0x03 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpunordpd -4(%ebx, %ecx, 8), %ymm2, %ymm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xec, 0xc2, 0xd9, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpeq_uqps %ymm1, %ymm2, %ymm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xec, 0xc2, 0xd9, 0x09 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpngeps %ymm1, %ymm2, %ymm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xec, 0xc2, 0xd9, 0x0a ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpngtps %ymm1, %ymm2, %ymm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xec, 0xc2, 0xd9, 0x0b ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpfalseps %ymm1, %ymm2, %ymm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xec, 0xc2, 0xd9, 0x0c ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpneq_oqps %ymm1, %ymm2, %ymm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xec, 0xc2, 0xd9, 0x0d ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpgeps %ymm1, %ymm2, %ymm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xec, 0xc2, 0xd9, 0x0e ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpgtps %ymm1, %ymm2, %ymm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xec, 0xc2, 0xd9, 0x0f ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmptrueps %ymm1, %ymm2, %ymm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xec, 0xc2, 0xd9, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpeq_osps %ymm1, %ymm2, %ymm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xec, 0xc2, 0xd9, 0x11 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmplt_oqps %ymm1, %ymm2, %ymm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xec, 0xc2, 0xd9, 0x12 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmple_oqps %ymm1, %ymm2, %ymm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xec, 0xc2, 0xd9, 0x13 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpunord_sps %ymm1, %ymm2, %ymm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xec, 0xc2, 0xd9, 0x14 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpneq_usps %ymm1, %ymm2, %ymm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xec, 0xc2, 0xd9, 0x15 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpnlt_uqps %ymm1, %ymm2, %ymm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xec, 0xc2, 0xd9, 0x16 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpnle_uqps %ymm1, %ymm2, %ymm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xec, 0xc2, 0xd9, 0x17 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpord_sps %ymm1, %ymm2, %ymm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xec, 0xc2, 0xd9, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpeq_usps %ymm1, %ymm2, %ymm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xec, 0xc2, 0xd9, 0x19 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpnge_uqps %ymm1, %ymm2, %ymm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xec, 0xc2, 0xd9, 0x1a ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpngt_uqps %ymm1, %ymm2, %ymm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xec, 0xc2, 0xd9, 0x1b ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpfalse_osps %ymm1, %ymm2, %ymm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xec, 0xc2, 0xd9, 0x1c ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpneq_osps %ymm1, %ymm2, %ymm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xec, 0xc2, 0xd9, 0x1d ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpge_oqps %ymm1, %ymm2, %ymm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xec, 0xc2, 0xd9, 0x1e ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpgt_oqps %ymm1, %ymm2, %ymm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xec, 0xc2, 0xd9, 0x1f ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmptrue_usps %ymm1, %ymm2, %ymm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xef, 0xd0, 0xd9 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vaddsubps %ymm1, %ymm2, %ymm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xf7, 0xd0, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vaddsubps (%eax), %ymm1, %ymm2"
+  -
+    input:
+      bytes: [ 0xc5, 0xed, 0xd0, 0xd9 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vaddsubpd %ymm1, %ymm2, %ymm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xf5, 0xd0, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vaddsubpd (%eax), %ymm1, %ymm2"
+  -
+    input:
+      bytes: [ 0xc5, 0xef, 0x7c, 0xd9 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vhaddps %ymm1, %ymm2, %ymm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xef, 0x7c, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vhaddps (%eax), %ymm2, %ymm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xed, 0x7c, 0xd9 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vhaddpd %ymm1, %ymm2, %ymm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xed, 0x7c, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vhaddpd (%eax), %ymm2, %ymm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xef, 0x7d, 0xd9 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vhsubps %ymm1, %ymm2, %ymm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xef, 0x7d, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vhsubps (%eax), %ymm2, %ymm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xed, 0x7d, 0xd9 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vhsubpd %ymm1, %ymm2, %ymm3"
+  -
+    input:
+      bytes: [ 0xc5, 0xed, 0x7d, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vhsubpd (%eax), %ymm2, %ymm3"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x55, 0x0c, 0xca, 0x03 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vblendps $3, %ymm2, %ymm5, %ymm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x55, 0x0c, 0x08, 0x03 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vblendps $3, (%eax), %ymm5, %ymm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x55, 0x0d, 0xca, 0x03 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vblendpd $3, %ymm2, %ymm5, %ymm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x55, 0x0d, 0x08, 0x03 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vblendpd $3, (%eax), %ymm5, %ymm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x55, 0x40, 0xca, 0x03 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vdpps $3, %ymm2, %ymm5, %ymm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x55, 0x40, 0x08, 0x03 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vdpps $3, (%eax), %ymm5, %ymm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x7d, 0x1a, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vbroadcastf128 (%eax), %ymm2"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x7d, 0x19, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vbroadcastsd (%eax), %ymm2"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x79, 0x18, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vbroadcastss (%eax), %xmm2"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x7d, 0x18, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vbroadcastss (%eax), %ymm2"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x6d, 0x18, 0xea, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vinsertf128 $7, %xmm2, %ymm2, %ymm5"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x6d, 0x18, 0x28, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vinsertf128 $7, (%eax), %ymm2, %ymm5"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x7d, 0x19, 0xd2, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vextractf128 $7, %ymm2, %xmm2"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x7d, 0x19, 0x10, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vextractf128 $7, %ymm2, (%eax)"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x51, 0x2f, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmaskmovpd %xmm2, %xmm5, (%eax)"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x55, 0x2f, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmaskmovpd %ymm2, %ymm5, (%eax)"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x69, 0x2d, 0x28 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmaskmovpd (%eax), %xmm2, %xmm5"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x6d, 0x2d, 0x28 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmaskmovpd (%eax), %ymm2, %ymm5"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x51, 0x2e, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmaskmovps %xmm2, %xmm5, (%eax)"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x55, 0x2e, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmaskmovps %ymm2, %ymm5, (%eax)"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x69, 0x2c, 0x28 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmaskmovps (%eax), %xmm2, %xmm5"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x6d, 0x2c, 0x28 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmaskmovps (%eax), %ymm2, %ymm5"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x79, 0x04, 0xe9, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpermilps $7, %xmm1, %xmm5"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x7d, 0x04, 0xcd, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpermilps $7, %ymm5, %ymm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x79, 0x04, 0x28, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpermilps $7, (%eax), %xmm5"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x7d, 0x04, 0x28, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpermilps $7, (%eax), %ymm5"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x51, 0x0c, 0xc9 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpermilps %xmm1, %xmm5, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x55, 0x0c, 0xc9 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpermilps %ymm1, %ymm5, %ymm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x51, 0x0c, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpermilps (%eax), %xmm5, %xmm3"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x55, 0x0c, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpermilps (%eax), %ymm5, %ymm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x79, 0x05, 0xe9, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpermilpd $7, %xmm1, %xmm5"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x7d, 0x05, 0xcd, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpermilpd $7, %ymm5, %ymm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x79, 0x05, 0x28, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpermilpd $7, (%eax), %xmm5"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x7d, 0x05, 0x28, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpermilpd $7, (%eax), %ymm5"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x51, 0x0d, 0xc9 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpermilpd %xmm1, %xmm5, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x55, 0x0d, 0xc9 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpermilpd %ymm1, %ymm5, %ymm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x51, 0x0d, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpermilpd (%eax), %xmm5, %xmm3"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x55, 0x0d, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpermilpd (%eax), %ymm5, %ymm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x55, 0x06, 0xca, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vperm2f128 $7, %ymm2, %ymm5, %ymm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x55, 0x06, 0x08, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vperm2f128 $7, (%eax), %ymm5, %ymm1"
+  -
+    input:
+      bytes: [ 0xc5, 0xfc, 0x77 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vzeroall"
+  -
+    input:
+      bytes: [ 0xc5, 0xf8, 0x77 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vzeroupper"
+  -
+    input:
+      bytes: [ 0xc5, 0xfb, 0x2d, 0xcc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvtsd2si %xmm4, %ecx"
+  -
+    input:
+      bytes: [ 0xc5, 0xfb, 0x2d, 0x09 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvtsd2si (%ecx), %ecx"
+  -
+    input:
+      bytes: [ 0xc5, 0xfb, 0x2d, 0xcc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvtsd2si %xmm4, %ecx"
+  -
+    input:
+      bytes: [ 0xc5, 0xfb, 0x2d, 0x09 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvtsd2si (%ecx), %ecx"
+  -
+    input:
+      bytes: [ 0xc5, 0xfb, 0x2a, 0x7d, 0x00 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvtsi2sdl (%ebp), %xmm0, %xmm7"
+  -
+    input:
+      bytes: [ 0xc5, 0xfb, 0x2a, 0x3c, 0x24 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvtsi2sdl (%esp), %xmm0, %xmm7"
+  -
+    input:
+      bytes: [ 0xc5, 0xfb, 0x2a, 0x7d, 0x00 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvtsi2sdl (%ebp), %xmm0, %xmm7"
+  -
+    input:
+      bytes: [ 0xc5, 0xfb, 0x2a, 0x3c, 0x24 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvtsi2sdl (%esp), %xmm0, %xmm7"
+  -
+    input:
+      bytes: [ 0xc5, 0xff, 0xf0, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vlddqu (%eax), %ymm2"
+  -
+    input:
+      bytes: [ 0xc5, 0xff, 0x12, 0xea ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovddup %ymm2, %ymm5"
+  -
+    input:
+      bytes: [ 0xc5, 0xff, 0x12, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovddup (%eax), %ymm2"
+  -
+    input:
+      bytes: [ 0xc5, 0xfd, 0x6f, 0xea ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovdqa %ymm2, %ymm5"
+  -
+    input:
+      bytes: [ 0xc5, 0xfd, 0x7f, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovdqa %ymm2, (%eax)"
+  -
+    input:
+      bytes: [ 0xc5, 0xfd, 0x6f, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovdqa (%eax), %ymm2"
+  -
+    input:
+      bytes: [ 0xc5, 0xfe, 0x6f, 0xea ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovdqu %ymm2, %ymm5"
+  -
+    input:
+      bytes: [ 0xc5, 0xfe, 0x7f, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovdqu %ymm2, (%eax)"
+  -
+    input:
+      bytes: [ 0xc5, 0xfe, 0x6f, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovdqu (%eax), %ymm2"
+  -
+    input:
+      bytes: [ 0xc5, 0xfe, 0x16, 0xea ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovshdup %ymm2, %ymm5"
+  -
+    input:
+      bytes: [ 0xc5, 0xfe, 0x16, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovshdup (%eax), %ymm2"
+  -
+    input:
+      bytes: [ 0xc5, 0xfe, 0x12, 0xea ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovsldup %ymm2, %ymm5"
+  -
+    input:
+      bytes: [ 0xc5, 0xfe, 0x12, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovsldup (%eax), %ymm2"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x7d, 0x17, 0xea ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vptest %ymm2, %ymm5"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x7d, 0x17, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vptest (%eax), %ymm2"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x7d, 0x09, 0xcd, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vroundpd $7, %ymm5, %ymm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x7d, 0x09, 0x28, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vroundpd $7, (%eax), %ymm5"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x7d, 0x08, 0xcd, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vroundps $7, %ymm5, %ymm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x7d, 0x08, 0x28, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vroundps $7, (%eax), %ymm5"
+  -
+    input:
+      bytes: [ 0xc5, 0xd5, 0xc6, 0xca, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vshufpd $7, %ymm2, %ymm5, %ymm1"
+  -
+    input:
+      bytes: [ 0xc5, 0xd5, 0xc6, 0x08, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vshufpd $7, (%eax), %ymm5, %ymm1"
+  -
+    input:
+      bytes: [ 0xc5, 0xd4, 0xc6, 0xca, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vshufps $7, %ymm2, %ymm5, %ymm1"
+  -
+    input:
+      bytes: [ 0xc5, 0xd4, 0xc6, 0x08, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vshufps $7, (%eax), %ymm5, %ymm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x79, 0x0f, 0xea ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vtestpd %xmm2, %xmm5"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x7d, 0x0f, 0xea ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vtestpd %ymm2, %ymm5"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x79, 0x0f, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vtestpd (%eax), %xmm2"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x7d, 0x0f, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vtestpd (%eax), %ymm2"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x79, 0x0e, 0xea ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vtestps %xmm2, %xmm5"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x7d, 0x0e, 0xea ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vtestps %ymm2, %ymm5"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x79, 0x0e, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vtestps (%eax), %xmm2"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x7d, 0x0e, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vtestps (%eax), %ymm2"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x75, 0x4b, 0x94, 0x20, 0xad, 0xde, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vblendvpd %ymm0, 0xdead(%eax), %ymm1, %ymm2"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x51, 0x44, 0xca, 0x11 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpclmulqdq $17, %xmm2, %xmm5, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x51, 0x44, 0x18, 0x11 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpclmulqdq $17, (%eax), %xmm5, %xmm3"
diff --git a/tests/MC/X86/x86-32-fma3.s.yaml b/tests/MC/X86/x86-32-fma3.s.yaml
new file mode 100644
index 000000000..52f78ef43
--- /dev/null
+++ b/tests/MC/X86/x86-32-fma3.s.yaml
@@ -0,0 +1,1504 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0xd1, 0x98, 0xca ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmadd132pd %xmm2, %xmm5, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0xd1, 0x98, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmadd132pd (%eax), %xmm5, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x51, 0x98, 0xca ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmadd132ps %xmm2, %xmm5, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x51, 0x98, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmadd132ps (%eax), %xmm5, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0xd1, 0xa8, 0xca ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmadd213pd %xmm2, %xmm5, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0xd1, 0xa8, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmadd213pd (%eax), %xmm5, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x51, 0xa8, 0xca ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmadd213ps %xmm2, %xmm5, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x51, 0xa8, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmadd213ps (%eax), %xmm5, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0xd1, 0xb8, 0xca ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmadd231pd %xmm2, %xmm5, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0xd1, 0xb8, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmadd231pd (%eax), %xmm5, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x51, 0xb8, 0xca ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmadd231ps %xmm2, %xmm5, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x51, 0xb8, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmadd231ps (%eax), %xmm5, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0xd5, 0x98, 0xca ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmadd132pd %ymm2, %ymm5, %ymm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0xd5, 0x98, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmadd132pd (%eax), %ymm5, %ymm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x55, 0x98, 0xca ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmadd132ps %ymm2, %ymm5, %ymm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x55, 0x98, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmadd132ps (%eax), %ymm5, %ymm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0xd5, 0xa8, 0xca ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmadd213pd %ymm2, %ymm5, %ymm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0xd5, 0xa8, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmadd213pd (%eax), %ymm5, %ymm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x55, 0xa8, 0xca ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmadd213ps %ymm2, %ymm5, %ymm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x55, 0xa8, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmadd213ps (%eax), %ymm5, %ymm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0xd5, 0xb8, 0xca ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmadd231pd %ymm2, %ymm5, %ymm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0xd5, 0xb8, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmadd231pd (%eax), %ymm5, %ymm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x55, 0xb8, 0xca ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmadd231ps %ymm2, %ymm5, %ymm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x55, 0xb8, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmadd231ps (%eax), %ymm5, %ymm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0xd1, 0x98, 0xca ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmadd132pd %xmm2, %xmm5, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0xd1, 0x98, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmadd132pd (%eax), %xmm5, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x51, 0x98, 0xca ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmadd132ps %xmm2, %xmm5, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x51, 0x98, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmadd132ps (%eax), %xmm5, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0xd1, 0xa8, 0xca ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmadd213pd %xmm2, %xmm5, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0xd1, 0xa8, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmadd213pd (%eax), %xmm5, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x51, 0xa8, 0xca ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmadd213ps %xmm2, %xmm5, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x51, 0xa8, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmadd213ps (%eax), %xmm5, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0xd1, 0xb8, 0xca ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmadd231pd %xmm2, %xmm5, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0xd1, 0xb8, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmadd231pd (%eax), %xmm5, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x51, 0xb8, 0xca ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmadd231ps %xmm2, %xmm5, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x51, 0xb8, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmadd231ps (%eax), %xmm5, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0xd1, 0x96, 0xca ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmaddsub132pd %xmm2, %xmm5, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0xd1, 0x96, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmaddsub132pd (%eax), %xmm5, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x51, 0x96, 0xca ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmaddsub132ps %xmm2, %xmm5, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x51, 0x96, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmaddsub132ps (%eax), %xmm5, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0xd1, 0xa6, 0xca ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmaddsub213pd %xmm2, %xmm5, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0xd1, 0xa6, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmaddsub213pd (%eax), %xmm5, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x51, 0xa6, 0xca ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmaddsub213ps %xmm2, %xmm5, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x51, 0xa6, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmaddsub213ps (%eax), %xmm5, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0xd1, 0xb6, 0xca ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmaddsub231pd %xmm2, %xmm5, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0xd1, 0xb6, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmaddsub231pd (%eax), %xmm5, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x51, 0xb6, 0xca ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmaddsub231ps %xmm2, %xmm5, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x51, 0xb6, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmaddsub231ps (%eax), %xmm5, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0xd1, 0x97, 0xca ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsubadd132pd %xmm2, %xmm5, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0xd1, 0x97, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsubadd132pd (%eax), %xmm5, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x51, 0x97, 0xca ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsubadd132ps %xmm2, %xmm5, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x51, 0x97, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsubadd132ps (%eax), %xmm5, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0xd1, 0xa7, 0xca ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsubadd213pd %xmm2, %xmm5, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0xd1, 0xa7, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsubadd213pd (%eax), %xmm5, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x51, 0xa7, 0xca ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsubadd213ps %xmm2, %xmm5, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x51, 0xa7, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsubadd213ps (%eax), %xmm5, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0xd1, 0xb7, 0xca ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsubadd231pd %xmm2, %xmm5, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0xd1, 0xb7, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsubadd231pd (%eax), %xmm5, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x51, 0xb7, 0xca ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsubadd231ps %xmm2, %xmm5, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x51, 0xb7, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsubadd231ps (%eax), %xmm5, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0xd1, 0x9a, 0xca ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsub132pd %xmm2, %xmm5, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0xd1, 0x9a, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsub132pd (%eax), %xmm5, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x51, 0x9a, 0xca ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsub132ps %xmm2, %xmm5, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x51, 0x9a, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsub132ps (%eax), %xmm5, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0xd1, 0xaa, 0xca ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsub213pd %xmm2, %xmm5, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0xd1, 0xaa, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsub213pd (%eax), %xmm5, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x51, 0xaa, 0xca ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsub213ps %xmm2, %xmm5, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x51, 0xaa, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsub213ps (%eax), %xmm5, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0xd1, 0xba, 0xca ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsub231pd %xmm2, %xmm5, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0xd1, 0xba, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsub231pd (%eax), %xmm5, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x51, 0xba, 0xca ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsub231ps %xmm2, %xmm5, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x51, 0xba, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsub231ps (%eax), %xmm5, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0xd1, 0x9c, 0xca ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmadd132pd %xmm2, %xmm5, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0xd1, 0x9c, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmadd132pd (%eax), %xmm5, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x51, 0x9c, 0xca ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmadd132ps %xmm2, %xmm5, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x51, 0x9c, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmadd132ps (%eax), %xmm5, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0xd1, 0xac, 0xca ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmadd213pd %xmm2, %xmm5, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0xd1, 0xac, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmadd213pd (%eax), %xmm5, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x51, 0xac, 0xca ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmadd213ps %xmm2, %xmm5, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x51, 0xac, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmadd213ps (%eax), %xmm5, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0xd1, 0xbc, 0xca ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmadd231pd %xmm2, %xmm5, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0xd1, 0xbc, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmadd231pd (%eax), %xmm5, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x51, 0xbc, 0xca ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmadd231ps %xmm2, %xmm5, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x51, 0xbc, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmadd231ps (%eax), %xmm5, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0xd1, 0x9e, 0xca ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmsub132pd %xmm2, %xmm5, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0xd1, 0x9e, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmsub132pd (%eax), %xmm5, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x51, 0x9e, 0xca ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmsub132ps %xmm2, %xmm5, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x51, 0x9e, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmsub132ps (%eax), %xmm5, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0xd1, 0xae, 0xca ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmsub213pd %xmm2, %xmm5, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0xd1, 0xae, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmsub213pd (%eax), %xmm5, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x51, 0xae, 0xca ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmsub213ps %xmm2, %xmm5, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x51, 0xae, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmsub213ps (%eax), %xmm5, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0xd1, 0xbe, 0xca ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmsub231pd %xmm2, %xmm5, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0xd1, 0xbe, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmsub231pd (%eax), %xmm5, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x51, 0xbe, 0xca ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmsub231ps %xmm2, %xmm5, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x51, 0xbe, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmsub231ps (%eax), %xmm5, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0xd5, 0x98, 0xca ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmadd132pd %ymm2, %ymm5, %ymm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0xd5, 0x98, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmadd132pd (%eax), %ymm5, %ymm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x55, 0x98, 0xca ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmadd132ps %ymm2, %ymm5, %ymm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x55, 0x98, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmadd132ps (%eax), %ymm5, %ymm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0xd5, 0xa8, 0xca ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmadd213pd %ymm2, %ymm5, %ymm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0xd5, 0xa8, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmadd213pd (%eax), %ymm5, %ymm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x55, 0xa8, 0xca ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmadd213ps %ymm2, %ymm5, %ymm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x55, 0xa8, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmadd213ps (%eax), %ymm5, %ymm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0xd5, 0xb8, 0xca ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmadd231pd %ymm2, %ymm5, %ymm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0xd5, 0xb8, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmadd231pd (%eax), %ymm5, %ymm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x55, 0xb8, 0xca ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmadd231ps %ymm2, %ymm5, %ymm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x55, 0xb8, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmadd231ps (%eax), %ymm5, %ymm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0xd5, 0x96, 0xca ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmaddsub132pd %ymm2, %ymm5, %ymm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0xd5, 0x96, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmaddsub132pd (%eax), %ymm5, %ymm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x55, 0x96, 0xca ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmaddsub132ps %ymm2, %ymm5, %ymm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x55, 0x96, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmaddsub132ps (%eax), %ymm5, %ymm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0xd5, 0xa6, 0xca ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmaddsub213pd %ymm2, %ymm5, %ymm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0xd5, 0xa6, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmaddsub213pd (%eax), %ymm5, %ymm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x55, 0xa6, 0xca ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmaddsub213ps %ymm2, %ymm5, %ymm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x55, 0xa6, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmaddsub213ps (%eax), %ymm5, %ymm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0xd5, 0xb6, 0xca ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmaddsub231pd %ymm2, %ymm5, %ymm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0xd5, 0xb6, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmaddsub231pd (%eax), %ymm5, %ymm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x55, 0xb6, 0xca ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmaddsub231ps %ymm2, %ymm5, %ymm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x55, 0xb6, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmaddsub231ps (%eax), %ymm5, %ymm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0xd5, 0x97, 0xca ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsubadd132pd %ymm2, %ymm5, %ymm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0xd5, 0x97, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsubadd132pd (%eax), %ymm5, %ymm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x55, 0x97, 0xca ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsubadd132ps %ymm2, %ymm5, %ymm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x55, 0x97, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsubadd132ps (%eax), %ymm5, %ymm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0xd5, 0xa7, 0xca ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsubadd213pd %ymm2, %ymm5, %ymm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0xd5, 0xa7, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsubadd213pd (%eax), %ymm5, %ymm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x55, 0xa7, 0xca ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsubadd213ps %ymm2, %ymm5, %ymm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x55, 0xa7, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsubadd213ps (%eax), %ymm5, %ymm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0xd5, 0xb7, 0xca ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsubadd231pd %ymm2, %ymm5, %ymm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0xd5, 0xb7, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsubadd231pd (%eax), %ymm5, %ymm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x55, 0xb7, 0xca ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsubadd231ps %ymm2, %ymm5, %ymm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x55, 0xb7, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsubadd231ps (%eax), %ymm5, %ymm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0xd5, 0x9a, 0xca ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsub132pd %ymm2, %ymm5, %ymm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0xd5, 0x9a, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsub132pd (%eax), %ymm5, %ymm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x55, 0x9a, 0xca ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsub132ps %ymm2, %ymm5, %ymm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x55, 0x9a, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsub132ps (%eax), %ymm5, %ymm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0xd5, 0xaa, 0xca ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsub213pd %ymm2, %ymm5, %ymm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0xd5, 0xaa, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsub213pd (%eax), %ymm5, %ymm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x55, 0xaa, 0xca ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsub213ps %ymm2, %ymm5, %ymm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x55, 0xaa, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsub213ps (%eax), %ymm5, %ymm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0xd5, 0xba, 0xca ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsub231pd %ymm2, %ymm5, %ymm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0xd5, 0xba, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsub231pd (%eax), %ymm5, %ymm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x55, 0xba, 0xca ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsub231ps %ymm2, %ymm5, %ymm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x55, 0xba, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsub231ps (%eax), %ymm5, %ymm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0xd5, 0x9c, 0xca ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmadd132pd %ymm2, %ymm5, %ymm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x55, 0x9c, 0xca ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmadd132ps %ymm2, %ymm5, %ymm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x55, 0x9c, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmadd132ps (%eax), %ymm5, %ymm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0xd5, 0xac, 0xca ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmadd213pd %ymm2, %ymm5, %ymm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0xd5, 0xac, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmadd213pd (%eax), %ymm5, %ymm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x55, 0xac, 0xca ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmadd213ps %ymm2, %ymm5, %ymm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x55, 0xac, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmadd213ps (%eax), %ymm5, %ymm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0xd5, 0xbc, 0xca ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmadd231pd %ymm2, %ymm5, %ymm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0xd5, 0xbc, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmadd231pd (%eax), %ymm5, %ymm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x55, 0xbc, 0xca ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmadd231ps %ymm2, %ymm5, %ymm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x55, 0xbc, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmadd231ps (%eax), %ymm5, %ymm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0xd5, 0x9e, 0xca ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmsub132pd %ymm2, %ymm5, %ymm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0xd5, 0x9e, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmsub132pd (%eax), %ymm5, %ymm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x55, 0x9e, 0xca ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmsub132ps %ymm2, %ymm5, %ymm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x55, 0x9e, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmsub132ps (%eax), %ymm5, %ymm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0xd5, 0xae, 0xca ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmsub213pd %ymm2, %ymm5, %ymm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0xd5, 0xae, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmsub213pd (%eax), %ymm5, %ymm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x55, 0xae, 0xca ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmsub213ps %ymm2, %ymm5, %ymm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x55, 0xae, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmsub213ps (%eax), %ymm5, %ymm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0xd5, 0xbe, 0xca ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmsub231pd %ymm2, %ymm5, %ymm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0xd5, 0xbe, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmsub231pd (%eax), %ymm5, %ymm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x55, 0xbe, 0xca ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmsub231ps %ymm2, %ymm5, %ymm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x55, 0xbe, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmsub231ps (%eax), %ymm5, %ymm1"
diff --git a/tests/MC/X86/x86-32-ms-inline-asm.s.yaml b/tests/MC/X86/x86-32-ms-inline-asm.s.yaml
new file mode 100644
index 000000000..c4a35a5cb
--- /dev/null
+++ b/tests/MC/X86/x86-32-ms-inline-asm.s.yaml
@@ -0,0 +1,235 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x8b, 0x03 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "movl (%ebx), %eax"
+  -
+    input:
+      bytes: [ 0x89, 0x4b, 0x04 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "movl %ecx, 4(%ebx)"
+  -
+    input:
+      bytes: [ 0x8b, 0x04, 0x85, 0x04, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "movl 4(, %eax, 4), %eax"
+  -
+    input:
+      bytes: [ 0x8b, 0x04, 0x85, 0x04, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "movl 4(, %eax, 4), %eax"
+  -
+    input:
+      bytes: [ 0x8b, 0x04, 0x06 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "movl (%esi, %eax), %eax"
+  -
+    input:
+      bytes: [ 0x8b, 0x04, 0x06 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "movl (%esi, %eax), %eax"
+  -
+    input:
+      bytes: [ 0x8b, 0x04, 0x86 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "movl (%esi, %eax, 4), %eax"
+  -
+    input:
+      bytes: [ 0x8b, 0x04, 0x86 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "movl (%esi, %eax, 4), %eax"
+  -
+    input:
+      bytes: [ 0x8b, 0x44, 0x06, 0x04 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "movl 4(%esi, %eax), %eax"
+  -
+    input:
+      bytes: [ 0x8b, 0x44, 0x06, 0x04 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "movl 4(%esi, %eax), %eax"
+  -
+    input:
+      bytes: [ 0x8b, 0x44, 0x06, 0x04 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "movl 4(%esi, %eax), %eax"
+  -
+    input:
+      bytes: [ 0x8b, 0x44, 0x06, 0x04 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "movl 4(%esi, %eax), %eax"
+  -
+    input:
+      bytes: [ 0x8b, 0x44, 0x46, 0x04 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "movl 4(%esi, %eax, 2), %eax"
+  -
+    input:
+      bytes: [ 0x8b, 0x44, 0x46, 0x04 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "movl 4(%esi, %eax, 2), %eax"
+  -
+    input:
+      bytes: [ 0x8b, 0x44, 0x46, 0x04 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "movl 4(%esi, %eax, 2), %eax"
+  -
+    input:
+      bytes: [ 0x8b, 0x44, 0x46, 0x04 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "movl 4(%esi, %eax, 2), %eax"
+  -
+    input:
+      bytes: [ 0x8b, 0x44, 0x46, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "movl 8(%esi, %eax, 2), %eax"
+  -
+    input:
+      bytes: [ 0x8b, 0x44, 0x46, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "movl 8(%esi, %eax, 2), %eax"
+  -
+    input:
+      bytes: [ 0x8b, 0x44, 0x46, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "movl 8(%esi, %eax, 2), %eax"
+  -
+    input:
+      bytes: [ 0x8b, 0x44, 0x46, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "movl 8(%esi, %eax, 2), %eax"
+  -
+    input:
+      bytes: [ 0x8b, 0x44, 0x46, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "movl 16(%esi, %eax, 2), %eax"
+  -
+    input:
+      bytes: [ 0x0f, 0x18, 0x40, 0x40 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "prefetchnta 64(%eax)"
+  -
+    input:
+      bytes: [ 0x60 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "pushal"
+  -
+    input:
+      bytes: [ 0x61 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "popal"
+  -
+    input:
+      bytes: [ 0x60 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "pushal"
+  -
+    input:
+      bytes: [ 0x61 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_MODE_32", "CS_OPT_SYNTAX_ATT" ]
+    expected:
+      insns:
+        -
+          asm_text: "popal"
diff --git a/tests/MC/X86/x86_64-avx-clmul-encoding.s.yaml b/tests/MC/X86/x86_64-avx-clmul-encoding.s.yaml
new file mode 100644
index 000000000..c8ca1c4e0
--- /dev/null
+++ b/tests/MC/X86/x86_64-avx-clmul-encoding.s.yaml
@@ -0,0 +1,19 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xc4, 0x43, 0x29, 0x44, 0xdc, 0x11 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpclmulqdq $17, %xmm12, %xmm10, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x63, 0x29, 0x44, 0x28, 0x11 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpclmulqdq $17, (%rax), %xmm10, %xmm13"
diff --git a/tests/MC/X86/x86_64-avx-encoding.s.yaml b/tests/MC/X86/x86_64-avx-encoding.s.yaml
new file mode 100644
index 000000000..50c2e4f06
--- /dev/null
+++ b/tests/MC/X86/x86_64-avx-encoding.s.yaml
@@ -0,0 +1,9514 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x32, 0x58, 0xd0 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vaddss %xmm8, %xmm9, %xmm10"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x32, 0x59, 0xd0 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmulss %xmm8, %xmm9, %xmm10"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x32, 0x5c, 0xd0 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vsubss %xmm8, %xmm9, %xmm10"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x32, 0x5e, 0xd0 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vdivss %xmm8, %xmm9, %xmm10"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x33, 0x58, 0xd0 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vaddsd %xmm8, %xmm9, %xmm10"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x33, 0x59, 0xd0 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmulsd %xmm8, %xmm9, %xmm10"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x33, 0x5c, 0xd0 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vsubsd %xmm8, %xmm9, %xmm10"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x33, 0x5e, 0xd0 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vdivsd %xmm8, %xmm9, %xmm10"
+  -
+    input:
+      bytes: [ 0xc5, 0x2a, 0x58, 0x5c, 0xd9, 0xfc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vaddss -4(%rcx, %rbx, 8), %xmm10, %xmm11"
+  -
+    input:
+      bytes: [ 0xc5, 0x2a, 0x5c, 0x5c, 0xd9, 0xfc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vsubss -4(%rcx, %rbx, 8), %xmm10, %xmm11"
+  -
+    input:
+      bytes: [ 0xc5, 0x2a, 0x59, 0x5c, 0xd9, 0xfc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmulss -4(%rcx, %rbx, 8), %xmm10, %xmm11"
+  -
+    input:
+      bytes: [ 0xc5, 0x2a, 0x5e, 0x5c, 0xd9, 0xfc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vdivss -4(%rcx, %rbx, 8), %xmm10, %xmm11"
+  -
+    input:
+      bytes: [ 0xc5, 0x2b, 0x58, 0x5c, 0xd9, 0xfc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vaddsd -4(%rcx, %rbx, 8), %xmm10, %xmm11"
+  -
+    input:
+      bytes: [ 0xc5, 0x2b, 0x5c, 0x5c, 0xd9, 0xfc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vsubsd -4(%rcx, %rbx, 8), %xmm10, %xmm11"
+  -
+    input:
+      bytes: [ 0xc5, 0x2b, 0x59, 0x5c, 0xd9, 0xfc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmulsd -4(%rcx, %rbx, 8), %xmm10, %xmm11"
+  -
+    input:
+      bytes: [ 0xc5, 0x2b, 0x5e, 0x5c, 0xd9, 0xfc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vdivsd -4(%rcx, %rbx, 8), %xmm10, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x20, 0x58, 0xfa ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vaddps %xmm10, %xmm11, %xmm15"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x20, 0x5c, 0xfa ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vsubps %xmm10, %xmm11, %xmm15"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x20, 0x59, 0xfa ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmulps %xmm10, %xmm11, %xmm15"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x20, 0x5e, 0xfa ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vdivps %xmm10, %xmm11, %xmm15"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x21, 0x58, 0xfa ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vaddpd %xmm10, %xmm11, %xmm15"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x21, 0x5c, 0xfa ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vsubpd %xmm10, %xmm11, %xmm15"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x21, 0x59, 0xfa ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmulpd %xmm10, %xmm11, %xmm15"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x21, 0x5e, 0xfa ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vdivpd %xmm10, %xmm11, %xmm15"
+  -
+    input:
+      bytes: [ 0xc5, 0x28, 0x58, 0x5c, 0xd9, 0xfc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vaddps -4(%rcx, %rbx, 8), %xmm10, %xmm11"
+  -
+    input:
+      bytes: [ 0xc5, 0x28, 0x5c, 0x5c, 0xd9, 0xfc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vsubps -4(%rcx, %rbx, 8), %xmm10, %xmm11"
+  -
+    input:
+      bytes: [ 0xc5, 0x28, 0x59, 0x5c, 0xd9, 0xfc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmulps -4(%rcx, %rbx, 8), %xmm10, %xmm11"
+  -
+    input:
+      bytes: [ 0xc5, 0x28, 0x5e, 0x5c, 0xd9, 0xfc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vdivps -4(%rcx, %rbx, 8), %xmm10, %xmm11"
+  -
+    input:
+      bytes: [ 0xc5, 0x29, 0x58, 0x5c, 0xd9, 0xfc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vaddpd -4(%rcx, %rbx, 8), %xmm10, %xmm11"
+  -
+    input:
+      bytes: [ 0xc5, 0x29, 0x5c, 0x5c, 0xd9, 0xfc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vsubpd -4(%rcx, %rbx, 8), %xmm10, %xmm11"
+  -
+    input:
+      bytes: [ 0xc5, 0x29, 0x59, 0x5c, 0xd9, 0xfc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmulpd -4(%rcx, %rbx, 8), %xmm10, %xmm11"
+  -
+    input:
+      bytes: [ 0xc5, 0x29, 0x5e, 0x5c, 0xd9, 0xfc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vdivpd -4(%rcx, %rbx, 8), %xmm10, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x0a, 0x5f, 0xe2 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmaxss %xmm10, %xmm14, %xmm12"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x0b, 0x5f, 0xe2 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmaxsd %xmm10, %xmm14, %xmm12"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x0a, 0x5d, 0xe2 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vminss %xmm10, %xmm14, %xmm12"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x0b, 0x5d, 0xe2 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vminsd %xmm10, %xmm14, %xmm12"
+  -
+    input:
+      bytes: [ 0xc5, 0x1a, 0x5f, 0x54, 0xcb, 0xfc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmaxss -4(%rbx, %rcx, 8), %xmm12, %xmm10"
+  -
+    input:
+      bytes: [ 0xc5, 0x1b, 0x5f, 0x54, 0xcb, 0xfc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmaxsd -4(%rbx, %rcx, 8), %xmm12, %xmm10"
+  -
+    input:
+      bytes: [ 0xc5, 0x1a, 0x5d, 0x54, 0xcb, 0xfc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vminss -4(%rbx, %rcx, 8), %xmm12, %xmm10"
+  -
+    input:
+      bytes: [ 0xc5, 0x1b, 0x5d, 0x54, 0xcb, 0xfc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vminsd -4(%rbx, %rcx, 8), %xmm12, %xmm10"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x08, 0x5f, 0xe2 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmaxps %xmm10, %xmm14, %xmm12"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x09, 0x5f, 0xe2 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmaxpd %xmm10, %xmm14, %xmm12"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x08, 0x5d, 0xe2 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vminps %xmm10, %xmm14, %xmm12"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x09, 0x5d, 0xe2 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vminpd %xmm10, %xmm14, %xmm12"
+  -
+    input:
+      bytes: [ 0xc5, 0x18, 0x5f, 0x54, 0xcb, 0xfc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmaxps -4(%rbx, %rcx, 8), %xmm12, %xmm10"
+  -
+    input:
+      bytes: [ 0xc5, 0x19, 0x5f, 0x54, 0xcb, 0xfc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmaxpd -4(%rbx, %rcx, 8), %xmm12, %xmm10"
+  -
+    input:
+      bytes: [ 0xc5, 0x18, 0x5d, 0x54, 0xcb, 0xfc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vminps -4(%rbx, %rcx, 8), %xmm12, %xmm10"
+  -
+    input:
+      bytes: [ 0xc5, 0x19, 0x5d, 0x54, 0xcb, 0xfc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vminpd -4(%rbx, %rcx, 8), %xmm12, %xmm10"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x08, 0x54, 0xe2 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vandps %xmm10, %xmm14, %xmm12"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x09, 0x54, 0xe2 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vandpd %xmm10, %xmm14, %xmm12"
+  -
+    input:
+      bytes: [ 0xc5, 0x18, 0x54, 0x54, 0xcb, 0xfc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vandps -4(%rbx, %rcx, 8), %xmm12, %xmm10"
+  -
+    input:
+      bytes: [ 0xc5, 0x19, 0x54, 0x54, 0xcb, 0xfc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vandpd -4(%rbx, %rcx, 8), %xmm12, %xmm10"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x08, 0x56, 0xe2 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vorps %xmm10, %xmm14, %xmm12"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x09, 0x56, 0xe2 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vorpd %xmm10, %xmm14, %xmm12"
+  -
+    input:
+      bytes: [ 0xc5, 0x18, 0x56, 0x54, 0xcb, 0xfc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vorps -4(%rbx, %rcx, 8), %xmm12, %xmm10"
+  -
+    input:
+      bytes: [ 0xc5, 0x19, 0x56, 0x54, 0xcb, 0xfc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vorpd -4(%rbx, %rcx, 8), %xmm12, %xmm10"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x08, 0x57, 0xe2 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vxorps %xmm10, %xmm14, %xmm12"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x09, 0x57, 0xe2 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vxorpd %xmm10, %xmm14, %xmm12"
+  -
+    input:
+      bytes: [ 0xc5, 0x18, 0x57, 0x54, 0xcb, 0xfc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vxorps -4(%rbx, %rcx, 8), %xmm12, %xmm10"
+  -
+    input:
+      bytes: [ 0xc5, 0x19, 0x57, 0x54, 0xcb, 0xfc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vxorpd -4(%rbx, %rcx, 8), %xmm12, %xmm10"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x08, 0x55, 0xe2 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vandnps %xmm10, %xmm14, %xmm12"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x09, 0x55, 0xe2 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vandnpd %xmm10, %xmm14, %xmm12"
+  -
+    input:
+      bytes: [ 0xc5, 0x18, 0x55, 0x54, 0xcb, 0xfc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vandnps -4(%rbx, %rcx, 8), %xmm12, %xmm10"
+  -
+    input:
+      bytes: [ 0xc5, 0x19, 0x55, 0x54, 0xcb, 0xfc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vandnpd -4(%rbx, %rcx, 8), %xmm12, %xmm10"
+  -
+    input:
+      bytes: [ 0xc5, 0x7a, 0x10, 0x54, 0xcb, 0xfc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovss -4(%rbx, %rcx, 8), %xmm10"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x2a, 0x10, 0xfe ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovss %xmm14, %xmm10, %xmm15"
+  -
+    input:
+      bytes: [ 0xc5, 0x7b, 0x10, 0x54, 0xcb, 0xfc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovsd -4(%rbx, %rcx, 8), %xmm10"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x2b, 0x10, 0xfe ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovsd %xmm14, %xmm10, %xmm15"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x18, 0x15, 0xef ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vunpckhps %xmm15, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x19, 0x15, 0xef ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vunpckhpd %xmm15, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x18, 0x14, 0xef ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vunpcklps %xmm15, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x19, 0x14, 0xef ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vunpcklpd %xmm15, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x18, 0x15, 0x7c, 0xcb, 0xfc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vunpckhps -4(%rbx, %rcx, 8), %xmm12, %xmm15"
+  -
+    input:
+      bytes: [ 0xc5, 0x19, 0x15, 0x7c, 0xcb, 0xfc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vunpckhpd -4(%rbx, %rcx, 8), %xmm12, %xmm15"
+  -
+    input:
+      bytes: [ 0xc5, 0x18, 0x14, 0x7c, 0xcb, 0xfc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vunpcklps -4(%rbx, %rcx, 8), %xmm12, %xmm15"
+  -
+    input:
+      bytes: [ 0xc5, 0x19, 0x14, 0x7c, 0xcb, 0xfc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vunpcklpd -4(%rbx, %rcx, 8), %xmm12, %xmm15"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xfa, 0x00 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpeqps %xmm10, %xmm12, %xmm15"
+  -
+    input:
+      bytes: [ 0xc5, 0x18, 0xc2, 0x38, 0x00 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpeqps (%rax), %xmm12, %xmm15"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xfa, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpordps %xmm10, %xmm12, %xmm15"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x19, 0xc2, 0xfa, 0x00 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpeqpd %xmm10, %xmm12, %xmm15"
+  -
+    input:
+      bytes: [ 0xc5, 0x19, 0xc2, 0x38, 0x00 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpeqpd (%rax), %xmm12, %xmm15"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x19, 0xc2, 0xfa, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpordpd %xmm10, %xmm12, %xmm15"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x18, 0xc6, 0xeb, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vshufps $8, %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x18, 0xc6, 0x6c, 0xcb, 0xfc, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vshufps $8, -4(%rbx, %rcx, 8), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x19, 0xc6, 0xeb, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vshufpd $8, %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x19, 0xc6, 0x6c, 0xcb, 0xfc, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vshufpd $8, -4(%rbx, %rcx, 8), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x00 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpeqps %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x02 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpleps %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x01 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpltps %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x04 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpneqps %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x06 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpnleps %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x05 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpnltps %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpordps %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x03 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpunordps %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x18, 0xc2, 0x6c, 0xcb, 0xfc, 0x00 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpeqps -4(%rbx, %rcx, 8), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x18, 0xc2, 0x6c, 0xcb, 0xfc, 0x02 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpleps -4(%rbx, %rcx, 8), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x18, 0xc2, 0x6c, 0xcb, 0xfc, 0x01 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpltps -4(%rbx, %rcx, 8), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x18, 0xc2, 0x6c, 0xcb, 0xfc, 0x04 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpneqps -4(%rbx, %rcx, 8), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x18, 0xc2, 0x6c, 0xcb, 0xfc, 0x06 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpnleps -4(%rbx, %rcx, 8), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x18, 0xc2, 0x6c, 0xcb, 0xfc, 0x05 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpnltps -4(%rbx, %rcx, 8), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0xc8, 0xc2, 0x54, 0xcb, 0xfc, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpordps -4(%rbx, %rcx, 8), %xmm6, %xmm2"
+  -
+    input:
+      bytes: [ 0xc5, 0x18, 0xc2, 0x6c, 0xcb, 0xfc, 0x03 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpunordps -4(%rbx, %rcx, 8), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x19, 0xc2, 0xeb, 0x00 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpeqpd %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x19, 0xc2, 0xeb, 0x02 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmplepd %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x19, 0xc2, 0xeb, 0x01 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpltpd %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x19, 0xc2, 0xeb, 0x04 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpneqpd %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x19, 0xc2, 0xeb, 0x06 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpnlepd %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x19, 0xc2, 0xeb, 0x05 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpnltpd %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x19, 0xc2, 0xeb, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpordpd %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x19, 0xc2, 0xeb, 0x03 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpunordpd %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x19, 0xc2, 0x6c, 0xcb, 0xfc, 0x00 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpeqpd -4(%rbx, %rcx, 8), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x19, 0xc2, 0x6c, 0xcb, 0xfc, 0x02 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmplepd -4(%rbx, %rcx, 8), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x19, 0xc2, 0x6c, 0xcb, 0xfc, 0x01 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpltpd -4(%rbx, %rcx, 8), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x19, 0xc2, 0x6c, 0xcb, 0xfc, 0x04 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpneqpd -4(%rbx, %rcx, 8), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x19, 0xc2, 0x6c, 0xcb, 0xfc, 0x06 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpnlepd -4(%rbx, %rcx, 8), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x19, 0xc2, 0x6c, 0xcb, 0xfc, 0x05 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpnltpd -4(%rbx, %rcx, 8), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0xc9, 0xc2, 0x54, 0xcb, 0xfc, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpordpd -4(%rbx, %rcx, 8), %xmm6, %xmm2"
+  -
+    input:
+      bytes: [ 0xc5, 0x19, 0xc2, 0x6c, 0xcb, 0xfc, 0x03 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpunordpd -4(%rbx, %rcx, 8), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x1a, 0xc2, 0xeb, 0x00 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpeqss %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x1a, 0xc2, 0xeb, 0x02 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpless %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x1a, 0xc2, 0xeb, 0x01 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpltss %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x1a, 0xc2, 0xeb, 0x04 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpneqss %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x1a, 0xc2, 0xeb, 0x06 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpnless %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x1a, 0xc2, 0xeb, 0x05 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpnltss %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x1a, 0xc2, 0xeb, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpordss %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x1a, 0xc2, 0xeb, 0x03 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpunordss %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x1a, 0xc2, 0x6c, 0xcb, 0xfc, 0x00 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpeqss -4(%rbx, %rcx, 8), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x1a, 0xc2, 0x6c, 0xcb, 0xfc, 0x02 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpless -4(%rbx, %rcx, 8), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x1a, 0xc2, 0x6c, 0xcb, 0xfc, 0x01 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpltss -4(%rbx, %rcx, 8), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x1a, 0xc2, 0x6c, 0xcb, 0xfc, 0x04 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpneqss -4(%rbx, %rcx, 8), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x1a, 0xc2, 0x6c, 0xcb, 0xfc, 0x06 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpnless -4(%rbx, %rcx, 8), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x1a, 0xc2, 0x6c, 0xcb, 0xfc, 0x05 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpnltss -4(%rbx, %rcx, 8), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0xca, 0xc2, 0x54, 0xcb, 0xfc, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpordss -4(%rbx, %rcx, 8), %xmm6, %xmm2"
+  -
+    input:
+      bytes: [ 0xc5, 0x1a, 0xc2, 0x6c, 0xcb, 0xfc, 0x03 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpunordss -4(%rbx, %rcx, 8), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x1b, 0xc2, 0xeb, 0x00 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpeqsd %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x1b, 0xc2, 0xeb, 0x02 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmplesd %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x1b, 0xc2, 0xeb, 0x01 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpltsd %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x1b, 0xc2, 0xeb, 0x04 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpneqsd %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x1b, 0xc2, 0xeb, 0x06 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpnlesd %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x1b, 0xc2, 0xeb, 0x05 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpnltsd %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x1b, 0xc2, 0xeb, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpordsd %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x1b, 0xc2, 0xeb, 0x03 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpunordsd %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x1b, 0xc2, 0x6c, 0xcb, 0xfc, 0x00 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpeqsd -4(%rbx, %rcx, 8), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x1b, 0xc2, 0x6c, 0xcb, 0xfc, 0x02 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmplesd -4(%rbx, %rcx, 8), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x1b, 0xc2, 0x6c, 0xcb, 0xfc, 0x01 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpltsd -4(%rbx, %rcx, 8), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x1b, 0xc2, 0x6c, 0xcb, 0xfc, 0x04 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpneqsd -4(%rbx, %rcx, 8), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x1b, 0xc2, 0x6c, 0xcb, 0xfc, 0x06 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpnlesd -4(%rbx, %rcx, 8), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x1b, 0xc2, 0x6c, 0xcb, 0xfc, 0x05 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpnltsd -4(%rbx, %rcx, 8), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0xcb, 0xc2, 0x54, 0xcb, 0xfc, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpordsd -4(%rbx, %rcx, 8), %xmm6, %xmm2"
+  -
+    input:
+      bytes: [ 0xc5, 0x1b, 0xc2, 0x6c, 0xcb, 0xfc, 0x03 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpunordsd -4(%rbx, %rcx, 8), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpeq_uqps %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x09 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpngeps %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x0a ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpngtps %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x0b ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpfalseps %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x0c ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpneq_oqps %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x0d ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpgeps %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x0e ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpgtps %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x0f ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmptrueps %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpeq_osps %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x11 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmplt_oqps %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x12 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmple_oqps %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x13 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpunord_sps %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x14 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpneq_usps %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x15 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpnlt_uqps %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x16 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpnle_uqps %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x17 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpord_sps %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpeq_usps %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x19 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpnge_uqps %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x1a ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpngt_uqps %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x1b ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpfalse_osps %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x1c ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpneq_osps %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x1d ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpge_oqps %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x1e ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpgt_oqps %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x1f ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmptrue_usps %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x18, 0xc2, 0x6c, 0xcb, 0xfc, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpeq_uqps -4(%rbx, %rcx, 8), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x18, 0xc2, 0x6c, 0xcb, 0xfc, 0x09 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpngeps -4(%rbx, %rcx, 8), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x18, 0xc2, 0x6c, 0xcb, 0xfc, 0x0a ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpngtps -4(%rbx, %rcx, 8), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x18, 0xc2, 0x6c, 0xcb, 0xfc, 0x0b ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpfalseps -4(%rbx, %rcx, 8), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x18, 0xc2, 0x6c, 0xcb, 0xfc, 0x0c ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpneq_oqps -4(%rbx, %rcx, 8), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x18, 0xc2, 0x6c, 0xcb, 0xfc, 0x0d ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpgeps -4(%rbx, %rcx, 8), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0xc8, 0xc2, 0x54, 0xcb, 0xfc, 0x0e ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpgtps -4(%rbx, %rcx, 8), %xmm6, %xmm2"
+  -
+    input:
+      bytes: [ 0xc5, 0x18, 0xc2, 0x6c, 0xcb, 0xfc, 0x0f ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmptrueps -4(%rbx, %rcx, 8), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x18, 0xc2, 0x6c, 0xcb, 0xfc, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpeq_osps -4(%rbx, %rcx, 8), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x18, 0xc2, 0x6c, 0xcb, 0xfc, 0x11 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmplt_oqps -4(%rbx, %rcx, 8), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x18, 0xc2, 0x6c, 0xcb, 0xfc, 0x12 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmple_oqps -4(%rbx, %rcx, 8), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x18, 0xc2, 0x6c, 0xcb, 0xfc, 0x13 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpunord_sps -4(%rbx, %rcx, 8), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x18, 0xc2, 0x6c, 0xcb, 0xfc, 0x14 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpneq_usps -4(%rbx, %rcx, 8), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x18, 0xc2, 0x6c, 0xcb, 0xfc, 0x15 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpnlt_uqps -4(%rbx, %rcx, 8), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0xc8, 0xc2, 0x54, 0xcb, 0xfc, 0x16 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpnle_uqps -4(%rbx, %rcx, 8), %xmm6, %xmm2"
+  -
+    input:
+      bytes: [ 0xc5, 0x18, 0xc2, 0x6c, 0xcb, 0xfc, 0x17 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpord_sps -4(%rbx, %rcx, 8), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x18, 0xc2, 0x6c, 0xcb, 0xfc, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpeq_usps -4(%rbx, %rcx, 8), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x18, 0xc2, 0x6c, 0xcb, 0xfc, 0x19 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpnge_uqps -4(%rbx, %rcx, 8), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x18, 0xc2, 0x6c, 0xcb, 0xfc, 0x1a ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpngt_uqps -4(%rbx, %rcx, 8), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x18, 0xc2, 0x6c, 0xcb, 0xfc, 0x1b ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpfalse_osps -4(%rbx, %rcx, 8), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x18, 0xc2, 0x6c, 0xcb, 0xfc, 0x1c ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpneq_osps -4(%rbx, %rcx, 8), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x18, 0xc2, 0x6c, 0xcb, 0xfc, 0x1d ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpge_oqps -4(%rbx, %rcx, 8), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0xc8, 0xc2, 0x54, 0xcb, 0xfc, 0x1e ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpgt_oqps -4(%rbx, %rcx, 8), %xmm6, %xmm2"
+  -
+    input:
+      bytes: [ 0xc5, 0x18, 0xc2, 0x6c, 0xcb, 0xfc, 0x1f ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmptrue_usps -4(%rbx, %rcx, 8), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x19, 0xc2, 0xeb, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpeq_uqpd %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x19, 0xc2, 0xeb, 0x09 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpngepd %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x19, 0xc2, 0xeb, 0x0a ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpngtpd %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x19, 0xc2, 0xeb, 0x0b ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpfalsepd %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x19, 0xc2, 0xeb, 0x0c ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpneq_oqpd %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x19, 0xc2, 0xeb, 0x0d ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpgepd %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x19, 0xc2, 0xeb, 0x0e ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpgtpd %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x19, 0xc2, 0xeb, 0x0f ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmptruepd %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x19, 0xc2, 0xeb, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpeq_ospd %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x19, 0xc2, 0xeb, 0x11 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmplt_oqpd %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x19, 0xc2, 0xeb, 0x12 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmple_oqpd %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x19, 0xc2, 0xeb, 0x13 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpunord_spd %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x19, 0xc2, 0xeb, 0x14 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpneq_uspd %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x19, 0xc2, 0xeb, 0x15 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpnlt_uqpd %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x19, 0xc2, 0xeb, 0x16 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpnle_uqpd %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x19, 0xc2, 0xeb, 0x17 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpord_spd %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x19, 0xc2, 0xeb, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpeq_uspd %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x19, 0xc2, 0xeb, 0x19 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpnge_uqpd %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x19, 0xc2, 0xeb, 0x1a ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpngt_uqpd %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x19, 0xc2, 0xeb, 0x1b ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpfalse_ospd %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x19, 0xc2, 0xeb, 0x1c ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpneq_ospd %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x19, 0xc2, 0xeb, 0x1d ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpge_oqpd %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x19, 0xc2, 0xeb, 0x1e ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpgt_oqpd %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x19, 0xc2, 0xeb, 0x1f ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmptrue_uspd %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x19, 0xc2, 0x6c, 0xcb, 0xfc, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpeq_uqpd -4(%rbx, %rcx, 8), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x19, 0xc2, 0x6c, 0xcb, 0xfc, 0x09 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpngepd -4(%rbx, %rcx, 8), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x19, 0xc2, 0x6c, 0xcb, 0xfc, 0x0a ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpngtpd -4(%rbx, %rcx, 8), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x19, 0xc2, 0x6c, 0xcb, 0xfc, 0x0b ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpfalsepd -4(%rbx, %rcx, 8), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x19, 0xc2, 0x6c, 0xcb, 0xfc, 0x0c ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpneq_oqpd -4(%rbx, %rcx, 8), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x19, 0xc2, 0x6c, 0xcb, 0xfc, 0x0d ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpgepd -4(%rbx, %rcx, 8), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0xc9, 0xc2, 0x54, 0xcb, 0xfc, 0x0e ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpgtpd -4(%rbx, %rcx, 8), %xmm6, %xmm2"
+  -
+    input:
+      bytes: [ 0xc5, 0x19, 0xc2, 0x6c, 0xcb, 0xfc, 0x0f ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmptruepd -4(%rbx, %rcx, 8), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x19, 0xc2, 0x6c, 0xcb, 0xfc, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpeq_ospd -4(%rbx, %rcx, 8), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x19, 0xc2, 0x6c, 0xcb, 0xfc, 0x11 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmplt_oqpd -4(%rbx, %rcx, 8), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x19, 0xc2, 0x6c, 0xcb, 0xfc, 0x12 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmple_oqpd -4(%rbx, %rcx, 8), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x19, 0xc2, 0x6c, 0xcb, 0xfc, 0x13 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpunord_spd -4(%rbx, %rcx, 8), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x19, 0xc2, 0x6c, 0xcb, 0xfc, 0x14 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpneq_uspd -4(%rbx, %rcx, 8), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x19, 0xc2, 0x6c, 0xcb, 0xfc, 0x15 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpnlt_uqpd -4(%rbx, %rcx, 8), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0xc9, 0xc2, 0x54, 0xcb, 0xfc, 0x16 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpnle_uqpd -4(%rbx, %rcx, 8), %xmm6, %xmm2"
+  -
+    input:
+      bytes: [ 0xc5, 0x19, 0xc2, 0x6c, 0xcb, 0xfc, 0x17 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpord_spd -4(%rbx, %rcx, 8), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x19, 0xc2, 0x6c, 0xcb, 0xfc, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpeq_uspd -4(%rbx, %rcx, 8), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x19, 0xc2, 0x6c, 0xcb, 0xfc, 0x19 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpnge_uqpd -4(%rbx, %rcx, 8), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x19, 0xc2, 0x6c, 0xcb, 0xfc, 0x1a ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpngt_uqpd -4(%rbx, %rcx, 8), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x19, 0xc2, 0x6c, 0xcb, 0xfc, 0x1b ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpfalse_ospd -4(%rbx, %rcx, 8), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x19, 0xc2, 0x6c, 0xcb, 0xfc, 0x1c ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpneq_ospd -4(%rbx, %rcx, 8), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x19, 0xc2, 0x6c, 0xcb, 0xfc, 0x1d ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpge_oqpd -4(%rbx, %rcx, 8), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0xc9, 0xc2, 0x54, 0xcb, 0xfc, 0x1e ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpgt_oqpd -4(%rbx, %rcx, 8), %xmm6, %xmm2"
+  -
+    input:
+      bytes: [ 0xc5, 0x19, 0xc2, 0x6c, 0xcb, 0xfc, 0x1f ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmptrue_uspd -4(%rbx, %rcx, 8), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x1a, 0xc2, 0xeb, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpeq_uqss %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x1a, 0xc2, 0xeb, 0x09 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpngess %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x1a, 0xc2, 0xeb, 0x0a ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpngtss %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x1a, 0xc2, 0xeb, 0x0b ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpfalsess %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x1a, 0xc2, 0xeb, 0x0c ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpneq_oqss %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x1a, 0xc2, 0xeb, 0x0d ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpgess %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x1a, 0xc2, 0xeb, 0x0e ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpgtss %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x1a, 0xc2, 0xeb, 0x0f ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmptruess %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x1a, 0xc2, 0xeb, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpeq_osss %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x1a, 0xc2, 0xeb, 0x11 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmplt_oqss %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x1a, 0xc2, 0xeb, 0x12 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmple_oqss %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x1a, 0xc2, 0xeb, 0x13 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpunord_sss %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x1a, 0xc2, 0xeb, 0x14 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpneq_usss %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x1a, 0xc2, 0xeb, 0x15 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpnlt_uqss %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x1a, 0xc2, 0xeb, 0x16 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpnle_uqss %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x1a, 0xc2, 0xeb, 0x17 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpord_sss %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x1a, 0xc2, 0xeb, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpeq_usss %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x1a, 0xc2, 0xeb, 0x19 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpnge_uqss %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x1a, 0xc2, 0xeb, 0x1a ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpngt_uqss %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x1a, 0xc2, 0xeb, 0x1b ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpfalse_osss %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x1a, 0xc2, 0xeb, 0x1c ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpneq_osss %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x1a, 0xc2, 0xeb, 0x1d ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpge_oqss %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x1a, 0xc2, 0xeb, 0x1e ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpgt_oqss %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x1a, 0xc2, 0xeb, 0x1f ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmptrue_usss %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x1a, 0xc2, 0x6c, 0xcb, 0xfc, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpeq_uqss -4(%rbx, %rcx, 8), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x1a, 0xc2, 0x6c, 0xcb, 0xfc, 0x09 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpngess -4(%rbx, %rcx, 8), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x1a, 0xc2, 0x6c, 0xcb, 0xfc, 0x0a ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpngtss -4(%rbx, %rcx, 8), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x1a, 0xc2, 0x6c, 0xcb, 0xfc, 0x0b ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpfalsess -4(%rbx, %rcx, 8), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x1a, 0xc2, 0x6c, 0xcb, 0xfc, 0x0c ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpneq_oqss -4(%rbx, %rcx, 8), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x1a, 0xc2, 0x6c, 0xcb, 0xfc, 0x0d ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpgess -4(%rbx, %rcx, 8), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0xca, 0xc2, 0x54, 0xcb, 0xfc, 0x0e ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpgtss -4(%rbx, %rcx, 8), %xmm6, %xmm2"
+  -
+    input:
+      bytes: [ 0xc5, 0x1a, 0xc2, 0x6c, 0xcb, 0xfc, 0x0f ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmptruess -4(%rbx, %rcx, 8), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x1a, 0xc2, 0x6c, 0xcb, 0xfc, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpeq_osss -4(%rbx, %rcx, 8), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x1a, 0xc2, 0x6c, 0xcb, 0xfc, 0x11 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmplt_oqss -4(%rbx, %rcx, 8), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x1a, 0xc2, 0x6c, 0xcb, 0xfc, 0x12 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmple_oqss -4(%rbx, %rcx, 8), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x1a, 0xc2, 0x6c, 0xcb, 0xfc, 0x13 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpunord_sss -4(%rbx, %rcx, 8), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x1a, 0xc2, 0x6c, 0xcb, 0xfc, 0x14 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpneq_usss -4(%rbx, %rcx, 8), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x1a, 0xc2, 0x6c, 0xcb, 0xfc, 0x15 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpnlt_uqss -4(%rbx, %rcx, 8), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0xca, 0xc2, 0x54, 0xcb, 0xfc, 0x16 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpnle_uqss -4(%rbx, %rcx, 8), %xmm6, %xmm2"
+  -
+    input:
+      bytes: [ 0xc5, 0x1a, 0xc2, 0x6c, 0xcb, 0xfc, 0x17 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpord_sss -4(%rbx, %rcx, 8), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x1a, 0xc2, 0x6c, 0xcb, 0xfc, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpeq_usss -4(%rbx, %rcx, 8), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x1a, 0xc2, 0x6c, 0xcb, 0xfc, 0x19 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpnge_uqss -4(%rbx, %rcx, 8), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x1a, 0xc2, 0x6c, 0xcb, 0xfc, 0x1a ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpngt_uqss -4(%rbx, %rcx, 8), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x1a, 0xc2, 0x6c, 0xcb, 0xfc, 0x1b ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpfalse_osss -4(%rbx, %rcx, 8), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x1a, 0xc2, 0x6c, 0xcb, 0xfc, 0x1c ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpneq_osss -4(%rbx, %rcx, 8), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x1a, 0xc2, 0x6c, 0xcb, 0xfc, 0x1d ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpge_oqss -4(%rbx, %rcx, 8), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0xca, 0xc2, 0x54, 0xcb, 0xfc, 0x1e ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpgt_oqss -4(%rbx, %rcx, 8), %xmm6, %xmm2"
+  -
+    input:
+      bytes: [ 0xc5, 0x1a, 0xc2, 0x6c, 0xcb, 0xfc, 0x1f ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmptrue_usss -4(%rbx, %rcx, 8), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x1b, 0xc2, 0xeb, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpeq_uqsd %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x1b, 0xc2, 0xeb, 0x09 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpngesd %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x1b, 0xc2, 0xeb, 0x0a ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpngtsd %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x1b, 0xc2, 0xeb, 0x0b ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpfalsesd %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x1b, 0xc2, 0xeb, 0x0c ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpneq_oqsd %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x1b, 0xc2, 0xeb, 0x0d ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpgesd %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x1b, 0xc2, 0xeb, 0x0e ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpgtsd %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x1b, 0xc2, 0xeb, 0x0f ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmptruesd %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x1b, 0xc2, 0xeb, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpeq_ossd %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x1b, 0xc2, 0xeb, 0x11 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmplt_oqsd %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x1b, 0xc2, 0xeb, 0x12 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmple_oqsd %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x1b, 0xc2, 0xeb, 0x13 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpunord_ssd %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x1b, 0xc2, 0xeb, 0x14 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpneq_ussd %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x1b, 0xc2, 0xeb, 0x15 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpnlt_uqsd %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x1b, 0xc2, 0xeb, 0x16 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpnle_uqsd %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x1b, 0xc2, 0xeb, 0x17 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpord_ssd %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x1b, 0xc2, 0xeb, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpeq_ussd %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x1b, 0xc2, 0xeb, 0x19 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpnge_uqsd %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x1b, 0xc2, 0xeb, 0x1a ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpngt_uqsd %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x1b, 0xc2, 0xeb, 0x1b ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpfalse_ossd %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x1b, 0xc2, 0xeb, 0x1c ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpneq_ossd %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x1b, 0xc2, 0xeb, 0x1d ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpge_oqsd %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x1b, 0xc2, 0xeb, 0x1e ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpgt_oqsd %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x1b, 0xc2, 0xeb, 0x1f ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmptrue_ussd %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x1b, 0xc2, 0x6c, 0xcb, 0xfc, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpeq_uqsd -4(%rbx, %rcx, 8), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x1b, 0xc2, 0x6c, 0xcb, 0xfc, 0x09 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpngesd -4(%rbx, %rcx, 8), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x1b, 0xc2, 0x6c, 0xcb, 0xfc, 0x0a ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpngtsd -4(%rbx, %rcx, 8), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x1b, 0xc2, 0x6c, 0xcb, 0xfc, 0x0b ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpfalsesd -4(%rbx, %rcx, 8), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x1b, 0xc2, 0x6c, 0xcb, 0xfc, 0x0c ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpneq_oqsd -4(%rbx, %rcx, 8), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x1b, 0xc2, 0x6c, 0xcb, 0xfc, 0x0d ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpgesd -4(%rbx, %rcx, 8), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0xcb, 0xc2, 0x54, 0xcb, 0xfc, 0x0e ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpgtsd -4(%rbx, %rcx, 8), %xmm6, %xmm2"
+  -
+    input:
+      bytes: [ 0xc5, 0x1b, 0xc2, 0x6c, 0xcb, 0xfc, 0x0f ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmptruesd -4(%rbx, %rcx, 8), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x1b, 0xc2, 0x6c, 0xcb, 0xfc, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpeq_ossd -4(%rbx, %rcx, 8), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x1b, 0xc2, 0x6c, 0xcb, 0xfc, 0x11 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmplt_oqsd -4(%rbx, %rcx, 8), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x1b, 0xc2, 0x6c, 0xcb, 0xfc, 0x12 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmple_oqsd -4(%rbx, %rcx, 8), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x1b, 0xc2, 0x6c, 0xcb, 0xfc, 0x13 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpunord_ssd -4(%rbx, %rcx, 8), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x1b, 0xc2, 0x6c, 0xcb, 0xfc, 0x14 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpneq_ussd -4(%rbx, %rcx, 8), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x1b, 0xc2, 0x6c, 0xcb, 0xfc, 0x15 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpnlt_uqsd -4(%rbx, %rcx, 8), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0xcb, 0xc2, 0x54, 0xcb, 0xfc, 0x16 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpnle_uqsd -4(%rbx, %rcx, 8), %xmm6, %xmm2"
+  -
+    input:
+      bytes: [ 0xc5, 0x1b, 0xc2, 0x6c, 0xcb, 0xfc, 0x17 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpord_ssd -4(%rbx, %rcx, 8), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x1b, 0xc2, 0x6c, 0xcb, 0xfc, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpeq_ussd -4(%rbx, %rcx, 8), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x1b, 0xc2, 0x6c, 0xcb, 0xfc, 0x19 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpnge_uqsd -4(%rbx, %rcx, 8), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x1b, 0xc2, 0x6c, 0xcb, 0xfc, 0x1a ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpngt_uqsd -4(%rbx, %rcx, 8), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x1b, 0xc2, 0x6c, 0xcb, 0xfc, 0x1b ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpfalse_ossd -4(%rbx, %rcx, 8), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x1b, 0xc2, 0x6c, 0xcb, 0xfc, 0x1c ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpneq_ossd -4(%rbx, %rcx, 8), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x1b, 0xc2, 0x6c, 0xcb, 0xfc, 0x1d ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpge_oqsd -4(%rbx, %rcx, 8), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0xcb, 0xc2, 0x54, 0xcb, 0xfc, 0x1e ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpgt_oqsd -4(%rbx, %rcx, 8), %xmm6, %xmm2"
+  -
+    input:
+      bytes: [ 0xc5, 0x1b, 0xc2, 0x6c, 0xcb, 0xfc, 0x1f ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmptrue_ussd -4(%rbx, %rcx, 8), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x78, 0x2e, 0xe3 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vucomiss %xmm11, %xmm12"
+  -
+    input:
+      bytes: [ 0xc5, 0x78, 0x2e, 0x20 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vucomiss (%rax), %xmm12"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x78, 0x2f, 0xe3 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcomiss %xmm11, %xmm12"
+  -
+    input:
+      bytes: [ 0xc5, 0x78, 0x2f, 0x20 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcomiss (%rax), %xmm12"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x79, 0x2e, 0xe3 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vucomisd %xmm11, %xmm12"
+  -
+    input:
+      bytes: [ 0xc5, 0x79, 0x2e, 0x20 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vucomisd (%rax), %xmm12"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x79, 0x2f, 0xe3 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcomisd %xmm11, %xmm12"
+  -
+    input:
+      bytes: [ 0xc5, 0x79, 0x2f, 0x20 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcomisd (%rax), %xmm12"
+  -
+    input:
+      bytes: [ 0xc5, 0xfa, 0x2c, 0x01 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvttss2si (%rcx), %eax"
+  -
+    input:
+      bytes: [ 0xc5, 0x22, 0x2a, 0x20 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvtsi2ssl (%rax), %xmm11, %xmm12"
+  -
+    input:
+      bytes: [ 0xc5, 0x22, 0x2a, 0x20 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvtsi2ssl (%rax), %xmm11, %xmm12"
+  -
+    input:
+      bytes: [ 0xc5, 0xfb, 0x2c, 0x01 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvttsd2si (%rcx), %eax"
+  -
+    input:
+      bytes: [ 0xc5, 0x23, 0x2a, 0x20 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvtsi2sdl (%rax), %xmm11, %xmm12"
+  -
+    input:
+      bytes: [ 0xc5, 0x23, 0x2a, 0x20 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvtsi2sdl (%rax), %xmm11, %xmm12"
+  -
+    input:
+      bytes: [ 0xc5, 0x78, 0x28, 0x20 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovaps (%rax), %xmm12"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x78, 0x28, 0xe3 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovaps %xmm11, %xmm12"
+  -
+    input:
+      bytes: [ 0xc5, 0x78, 0x29, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovaps %xmm11, (%rax)"
+  -
+    input:
+      bytes: [ 0xc5, 0x79, 0x28, 0x20 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovapd (%rax), %xmm12"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x79, 0x28, 0xe3 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovapd %xmm11, %xmm12"
+  -
+    input:
+      bytes: [ 0xc5, 0x79, 0x29, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovapd %xmm11, (%rax)"
+  -
+    input:
+      bytes: [ 0xc5, 0x78, 0x10, 0x20 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovups (%rax), %xmm12"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x78, 0x10, 0xe3 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovups %xmm11, %xmm12"
+  -
+    input:
+      bytes: [ 0xc5, 0x78, 0x11, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovups %xmm11, (%rax)"
+  -
+    input:
+      bytes: [ 0xc5, 0x79, 0x10, 0x20 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovupd (%rax), %xmm12"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x79, 0x10, 0xe3 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovupd %xmm11, %xmm12"
+  -
+    input:
+      bytes: [ 0xc5, 0x79, 0x11, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovupd %xmm11, (%rax)"
+  -
+    input:
+      bytes: [ 0xc5, 0x78, 0x13, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovlps %xmm11, (%rax)"
+  -
+    input:
+      bytes: [ 0xc5, 0x18, 0x12, 0x28 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovlps (%rax), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x79, 0x13, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovlpd %xmm11, (%rax)"
+  -
+    input:
+      bytes: [ 0xc5, 0x19, 0x12, 0x28 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovlpd (%rax), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x78, 0x17, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovhps %xmm11, (%rax)"
+  -
+    input:
+      bytes: [ 0xc5, 0x18, 0x16, 0x28 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovhps (%rax), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x79, 0x17, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovhpd %xmm11, (%rax)"
+  -
+    input:
+      bytes: [ 0xc5, 0x19, 0x16, 0x28 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovhpd (%rax), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x18, 0x16, 0xeb ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovlhps %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x18, 0x12, 0xeb ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovhlps %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0xc1, 0x7a, 0x2d, 0xc3 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvtss2si %xmm11, %eax"
+  -
+    input:
+      bytes: [ 0xc5, 0xfa, 0x2d, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvtss2si (%rax), %ebx"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x78, 0x5b, 0xe2 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvtdq2ps %xmm10, %xmm12"
+  -
+    input:
+      bytes: [ 0xc5, 0x78, 0x5b, 0x20 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvtdq2ps (%rax), %xmm12"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x13, 0x5a, 0xd4 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvtsd2ss %xmm12, %xmm13, %xmm10"
+  -
+    input:
+      bytes: [ 0xc5, 0x13, 0x5a, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvtsd2ss (%rax), %xmm13, %xmm10"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x79, 0x5b, 0xdc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvtps2dq %xmm12, %xmm11"
+  -
+    input:
+      bytes: [ 0xc5, 0x79, 0x5b, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvtps2dq (%rax), %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x12, 0x5a, 0xd4 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvtss2sd %xmm12, %xmm13, %xmm10"
+  -
+    input:
+      bytes: [ 0xc5, 0x12, 0x5a, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvtss2sd (%rax), %xmm13, %xmm10"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x78, 0x5b, 0xd5 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvtdq2ps %xmm13, %xmm10"
+  -
+    input:
+      bytes: [ 0xc5, 0x78, 0x5b, 0x29 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvtdq2ps (%rcx), %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x7a, 0x5b, 0xdc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvttps2dq %xmm12, %xmm11"
+  -
+    input:
+      bytes: [ 0xc5, 0x7a, 0x5b, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvttps2dq (%rax), %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x78, 0x5a, 0xdc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvtps2pd %xmm12, %xmm11"
+  -
+    input:
+      bytes: [ 0xc5, 0x78, 0x5a, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvtps2pd (%rax), %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x79, 0x5a, 0xdc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvtpd2ps %xmm12, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x79, 0x51, 0xe3 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vsqrtpd %xmm11, %xmm12"
+  -
+    input:
+      bytes: [ 0xc5, 0x79, 0x51, 0x20 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vsqrtpd (%rax), %xmm12"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x78, 0x51, 0xe3 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vsqrtps %xmm11, %xmm12"
+  -
+    input:
+      bytes: [ 0xc5, 0x78, 0x51, 0x20 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vsqrtps (%rax), %xmm12"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x1b, 0x51, 0xd3 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vsqrtsd %xmm11, %xmm12, %xmm10"
+  -
+    input:
+      bytes: [ 0xc5, 0x1b, 0x51, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vsqrtsd (%rax), %xmm12, %xmm10"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x1a, 0x51, 0xd3 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vsqrtss %xmm11, %xmm12, %xmm10"
+  -
+    input:
+      bytes: [ 0xc5, 0x1a, 0x51, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vsqrtss (%rax), %xmm12, %xmm10"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x78, 0x52, 0xe3 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vrsqrtps %xmm11, %xmm12"
+  -
+    input:
+      bytes: [ 0xc5, 0x78, 0x52, 0x20 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vrsqrtps (%rax), %xmm12"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x1a, 0x52, 0xd3 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vrsqrtss %xmm11, %xmm12, %xmm10"
+  -
+    input:
+      bytes: [ 0xc5, 0x1a, 0x52, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vrsqrtss (%rax), %xmm12, %xmm10"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x78, 0x53, 0xe3 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vrcpps %xmm11, %xmm12"
+  -
+    input:
+      bytes: [ 0xc5, 0x78, 0x53, 0x20 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vrcpps (%rax), %xmm12"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x1a, 0x53, 0xd3 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vrcpss %xmm11, %xmm12, %xmm10"
+  -
+    input:
+      bytes: [ 0xc5, 0x1a, 0x53, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vrcpss (%rax), %xmm12, %xmm10"
+  -
+    input:
+      bytes: [ 0xc5, 0x79, 0xe7, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovntdq %xmm11, (%rax)"
+  -
+    input:
+      bytes: [ 0xc5, 0x79, 0x2b, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovntpd %xmm11, (%rax)"
+  -
+    input:
+      bytes: [ 0xc5, 0x78, 0x2b, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovntps %xmm11, (%rax)"
+  -
+    input:
+      bytes: [ 0xc5, 0xf8, 0xae, 0x15, 0xfc, 0xff, 0xff, 0xff ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vldmxcsr -4(%rip)"
+  -
+    input:
+      bytes: [ 0xc5, 0xf8, 0xae, 0x5c, 0x24, 0xfc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vstmxcsr -4(%rsp)"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x19, 0xf8, 0xeb ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpsubb %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x19, 0xf8, 0x28 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpsubb (%rax), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x19, 0xf9, 0xeb ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpsubw %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x19, 0xf9, 0x28 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpsubw (%rax), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x19, 0xfa, 0xeb ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpsubd %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x19, 0xfa, 0x28 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpsubd (%rax), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x19, 0xfb, 0xeb ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpsubq %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x19, 0xfb, 0x28 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpsubq (%rax), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x19, 0xe8, 0xeb ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpsubsb %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x19, 0xe8, 0x28 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpsubsb (%rax), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x19, 0xe9, 0xeb ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpsubsw %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x19, 0xe9, 0x28 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpsubsw (%rax), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x19, 0xd8, 0xeb ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpsubusb %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x19, 0xd8, 0x28 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpsubusb (%rax), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x19, 0xd9, 0xeb ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpsubusw %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x19, 0xd9, 0x28 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpsubusw (%rax), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x19, 0xfc, 0xeb ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpaddb %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x19, 0xfc, 0x28 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpaddb (%rax), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x19, 0xfd, 0xeb ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpaddw %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x19, 0xfd, 0x28 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpaddw (%rax), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x19, 0xfe, 0xeb ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpaddd %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x19, 0xfe, 0x28 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpaddd (%rax), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x19, 0xd4, 0xeb ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpaddq %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x19, 0xd4, 0x28 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpaddq (%rax), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x19, 0xec, 0xeb ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpaddsb %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x19, 0xec, 0x28 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpaddsb (%rax), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x19, 0xed, 0xeb ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpaddsw %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x19, 0xed, 0x28 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpaddsw (%rax), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x19, 0xdc, 0xeb ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpaddusb %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x19, 0xdc, 0x28 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpaddusb (%rax), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x19, 0xdd, 0xeb ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpaddusw %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x19, 0xdd, 0x28 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpaddusw (%rax), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x19, 0xe4, 0xeb ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmulhuw %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x19, 0xe4, 0x28 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmulhuw (%rax), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x19, 0xe5, 0xeb ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmulhw %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x19, 0xe5, 0x28 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmulhw (%rax), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x19, 0xd5, 0xeb ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmullw %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x19, 0xd5, 0x28 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmullw (%rax), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x19, 0xf4, 0xeb ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmuludq %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x19, 0xf4, 0x28 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmuludq (%rax), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x19, 0xe0, 0xeb ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpavgb %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x19, 0xe0, 0x28 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpavgb (%rax), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x19, 0xe3, 0xeb ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpavgw %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x19, 0xe3, 0x28 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpavgw (%rax), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x19, 0xea, 0xeb ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpminsw %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x19, 0xea, 0x28 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpminsw (%rax), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x19, 0xda, 0xeb ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpminub %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x19, 0xda, 0x28 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpminub (%rax), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x19, 0xee, 0xeb ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmaxsw %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x19, 0xee, 0x28 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmaxsw (%rax), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x19, 0xde, 0xeb ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmaxub %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x19, 0xde, 0x28 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmaxub (%rax), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x19, 0xf6, 0xeb ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpsadbw %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x19, 0xf6, 0x28 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpsadbw (%rax), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x19, 0xf1, 0xeb ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpsllw %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x19, 0xf1, 0x28 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpsllw (%rax), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x19, 0xf2, 0xeb ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpslld %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x19, 0xf2, 0x28 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpslld (%rax), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x19, 0xf3, 0xeb ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpsllq %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x19, 0xf3, 0x28 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpsllq (%rax), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x19, 0xe1, 0xeb ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpsraw %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x19, 0xe1, 0x28 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpsraw (%rax), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x19, 0xe2, 0xeb ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpsrad %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x19, 0xe2, 0x28 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpsrad (%rax), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x19, 0xd1, 0xeb ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpsrlw %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x19, 0xd1, 0x28 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpsrlw (%rax), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x19, 0xd2, 0xeb ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpsrld %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x19, 0xd2, 0x28 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpsrld (%rax), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x19, 0xd3, 0xeb ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpsrlq %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x19, 0xd3, 0x28 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpsrlq (%rax), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0xc1, 0x11, 0x72, 0xf4, 0x0a ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpslld $10, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0xc1, 0x11, 0x73, 0xfc, 0x0a ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpslldq $10, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0xc1, 0x11, 0x73, 0xf4, 0x0a ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpsllq $10, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0xc1, 0x11, 0x71, 0xf4, 0x0a ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpsllw $10, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0xc1, 0x11, 0x72, 0xe4, 0x0a ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpsrad $10, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0xc1, 0x11, 0x71, 0xe4, 0x0a ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpsraw $10, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0xc1, 0x11, 0x72, 0xd4, 0x0a ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpsrld $10, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0xc1, 0x11, 0x73, 0xdc, 0x0a ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpsrldq $10, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0xc1, 0x11, 0x73, 0xd4, 0x0a ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpsrlq $10, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0xc1, 0x11, 0x71, 0xd4, 0x0a ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpsrlw $10, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0xc1, 0x11, 0x72, 0xf4, 0x0a ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpslld $10, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x19, 0xdb, 0xeb ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpand %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x19, 0xdb, 0x28 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpand (%rax), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x19, 0xeb, 0xeb ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpor %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x19, 0xeb, 0x28 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpor (%rax), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x19, 0xef, 0xeb ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpxor %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x19, 0xef, 0x28 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpxor (%rax), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x19, 0xdf, 0xeb ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpandn %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x19, 0xdf, 0x28 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpandn (%rax), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x19, 0x74, 0xeb ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpcmpeqb %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x19, 0x74, 0x28 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpcmpeqb (%rax), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x19, 0x75, 0xeb ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpcmpeqw %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x19, 0x75, 0x28 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpcmpeqw (%rax), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x19, 0x76, 0xeb ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpcmpeqd %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x19, 0x76, 0x28 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpcmpeqd (%rax), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x19, 0x64, 0xeb ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpcmpgtb %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x19, 0x64, 0x28 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpcmpgtb (%rax), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x19, 0x65, 0xeb ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpcmpgtw %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x19, 0x65, 0x28 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpcmpgtw (%rax), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x19, 0x66, 0xeb ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpcmpgtd %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x19, 0x66, 0x28 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpcmpgtd (%rax), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x19, 0x63, 0xeb ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpacksswb %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x19, 0x63, 0x28 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpacksswb (%rax), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x19, 0x6b, 0xeb ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpackssdw %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x19, 0x6b, 0x28 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpackssdw (%rax), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x19, 0x67, 0xeb ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpackuswb %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x19, 0x67, 0x28 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpackuswb (%rax), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x79, 0x70, 0xec, 0x04 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpshufd $4, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x79, 0x70, 0x28, 0x04 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpshufd $4, (%rax), %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x7a, 0x70, 0xec, 0x04 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpshufhw $4, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x7a, 0x70, 0x28, 0x04 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpshufhw $4, (%rax), %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x7b, 0x70, 0xec, 0x04 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpshuflw $4, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x7b, 0x70, 0x28, 0x04 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpshuflw $4, (%rax), %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x19, 0x60, 0xeb ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpunpcklbw %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x19, 0x60, 0x28 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpunpcklbw (%rax), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x19, 0x61, 0xeb ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpunpcklwd %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x19, 0x61, 0x28 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpunpcklwd (%rax), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x19, 0x62, 0xeb ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpunpckldq %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x19, 0x62, 0x28 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpunpckldq (%rax), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x19, 0x6c, 0xeb ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpunpcklqdq %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x19, 0x6c, 0x28 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpunpcklqdq (%rax), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x19, 0x68, 0xeb ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpunpckhbw %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x19, 0x68, 0x28 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpunpckhbw (%rax), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x19, 0x69, 0xeb ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpunpckhwd %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x19, 0x69, 0x28 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpunpckhwd (%rax), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x19, 0x6a, 0xeb ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpunpckhdq %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x19, 0x6a, 0x28 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpunpckhdq (%rax), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x19, 0x6d, 0xeb ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpunpckhqdq %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x19, 0x6d, 0x28 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpunpckhqdq (%rax), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x19, 0xc4, 0xe8, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpinsrw $7, %eax, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x19, 0xc4, 0x28, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpinsrw $7, (%rax), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0xc1, 0x79, 0xc5, 0xc4, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpextrw $7, %xmm12, %eax"
+  -
+    input:
+      bytes: [ 0xc4, 0xc1, 0x79, 0xd7, 0xc4 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmovmskb %xmm12, %eax"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x79, 0xf7, 0xfe ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmaskmovdqu %xmm14, %xmm15"
+  -
+    input:
+      bytes: [ 0xc5, 0x79, 0x6e, 0xf0 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovd %eax, %xmm14"
+  -
+    input:
+      bytes: [ 0xc5, 0x79, 0x6e, 0x30 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovd (%rax), %xmm14"
+  -
+    input:
+      bytes: [ 0xc5, 0x79, 0x7e, 0x30 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovd %xmm14, (%rax)"
+  -
+    input:
+      bytes: [ 0xc4, 0x61, 0xf9, 0x6e, 0xf0 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovq %rax, %xmm14"
+  -
+    input:
+      bytes: [ 0xc4, 0xe1, 0xf9, 0x7e, 0xc0 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovq %xmm0, %rax"
+  -
+    input:
+      bytes: [ 0xc5, 0x79, 0xd6, 0x30 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovq %xmm14, (%rax)"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x7a, 0x7e, 0xe6 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovq %xmm14, %xmm12"
+  -
+    input:
+      bytes: [ 0xc5, 0x7a, 0x7e, 0x30 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovq (%rax), %xmm14"
+  -
+    input:
+      bytes: [ 0xc4, 0x61, 0xf9, 0x6e, 0xf0 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovq %rax, %xmm14"
+  -
+    input:
+      bytes: [ 0xc4, 0x61, 0xf9, 0x7e, 0xf0 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovq %xmm14, %rax"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x7b, 0xe6, 0xe3 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvtpd2dq %xmm11, %xmm12"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x7a, 0xe6, 0xe3 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvtdq2pd %xmm11, %xmm12"
+  -
+    input:
+      bytes: [ 0xc5, 0x7a, 0xe6, 0x20 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvtdq2pd (%rax), %xmm12"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x7a, 0x16, 0xe3 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovshdup %xmm11, %xmm12"
+  -
+    input:
+      bytes: [ 0xc5, 0x7a, 0x16, 0x20 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovshdup (%rax), %xmm12"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x7a, 0x12, 0xe3 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovsldup %xmm11, %xmm12"
+  -
+    input:
+      bytes: [ 0xc5, 0x7a, 0x12, 0x20 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovsldup (%rax), %xmm12"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x7b, 0x12, 0xe3 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovddup %xmm11, %xmm12"
+  -
+    input:
+      bytes: [ 0xc5, 0x7b, 0x12, 0x20 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovddup (%rax), %xmm12"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x1b, 0xd0, 0xeb ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vaddsubps %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x23, 0xd0, 0x20 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vaddsubps (%rax), %xmm11, %xmm12"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x19, 0xd0, 0xeb ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vaddsubpd %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x21, 0xd0, 0x20 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vaddsubpd (%rax), %xmm11, %xmm12"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x1b, 0x7c, 0xeb ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vhaddps %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x1b, 0x7c, 0x28 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vhaddps (%rax), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x19, 0x7c, 0xeb ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vhaddpd %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x19, 0x7c, 0x28 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vhaddpd (%rax), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x1b, 0x7d, 0xeb ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vhsubps %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x1b, 0x7d, 0x28 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vhsubps (%rax), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x19, 0x7d, 0xeb ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vhsubpd %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x19, 0x7d, 0x28 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vhsubpd (%rax), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0x79, 0x1c, 0xe3 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpabsb %xmm11, %xmm12"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x79, 0x1c, 0x20 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpabsb (%rax), %xmm12"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0x79, 0x1d, 0xe3 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpabsw %xmm11, %xmm12"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x79, 0x1d, 0x20 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpabsw (%rax), %xmm12"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0x79, 0x1e, 0xe3 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpabsd %xmm11, %xmm12"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x79, 0x1e, 0x20 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpabsd (%rax), %xmm12"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0x19, 0x01, 0xeb ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vphaddw %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x19, 0x01, 0x28 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vphaddw (%rax), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0x19, 0x02, 0xeb ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vphaddd %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x19, 0x02, 0x28 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vphaddd (%rax), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0x19, 0x03, 0xeb ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vphaddsw %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x19, 0x03, 0x28 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vphaddsw (%rax), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0x19, 0x05, 0xeb ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vphsubw %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x19, 0x05, 0x28 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vphsubw (%rax), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0x19, 0x06, 0xeb ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vphsubd %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x19, 0x06, 0x28 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vphsubd (%rax), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0x19, 0x07, 0xeb ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vphsubsw %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x19, 0x07, 0x28 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vphsubsw (%rax), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0x19, 0x04, 0xeb ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmaddubsw %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x19, 0x04, 0x28 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmaddubsw (%rax), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0x19, 0x00, 0xeb ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpshufb %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x19, 0x00, 0x28 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpshufb (%rax), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0x19, 0x08, 0xeb ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpsignb %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x19, 0x08, 0x28 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpsignb (%rax), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0x19, 0x09, 0xeb ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpsignw %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x19, 0x09, 0x28 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpsignw (%rax), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0x19, 0x0a, 0xeb ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpsignd %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x19, 0x0a, 0x28 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpsignd (%rax), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0x19, 0x0b, 0xeb ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmulhrsw %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x19, 0x0b, 0x28 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmulhrsw (%rax), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x43, 0x19, 0x0f, 0xeb, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpalignr $7, %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x63, 0x19, 0x0f, 0x28, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpalignr $7, (%rax), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x43, 0x19, 0x0b, 0xeb, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vroundsd $7, %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x63, 0x19, 0x0b, 0x28, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vroundsd $7, (%rax), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x43, 0x19, 0x0a, 0xeb, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vroundss $7, %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x63, 0x19, 0x0a, 0x28, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vroundss $7, (%rax), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x43, 0x79, 0x09, 0xec, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vroundpd $7, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x63, 0x79, 0x09, 0x28, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vroundpd $7, (%rax), %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x43, 0x79, 0x08, 0xec, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vroundps $7, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x63, 0x79, 0x08, 0x28, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vroundps $7, (%rax), %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0x79, 0x41, 0xec ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vphminposuw %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x79, 0x41, 0x20 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vphminposuw (%rax), %xmm12"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0x11, 0x2b, 0xdc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpackusdw %xmm12, %xmm13, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x19, 0x2b, 0x28 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpackusdw (%rax), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0x11, 0x29, 0xdc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpcmpeqq %xmm12, %xmm13, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x19, 0x29, 0x28 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpcmpeqq (%rax), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0x11, 0x38, 0xdc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpminsb %xmm12, %xmm13, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x19, 0x38, 0x28 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpminsb (%rax), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0x11, 0x39, 0xdc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpminsd %xmm12, %xmm13, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x19, 0x39, 0x28 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpminsd (%rax), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0x11, 0x3b, 0xdc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpminud %xmm12, %xmm13, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x19, 0x3b, 0x28 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpminud (%rax), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0x11, 0x3a, 0xdc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpminuw %xmm12, %xmm13, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x19, 0x3a, 0x28 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpminuw (%rax), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0x11, 0x3c, 0xdc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmaxsb %xmm12, %xmm13, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x19, 0x3c, 0x28 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmaxsb (%rax), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0x11, 0x3d, 0xdc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmaxsd %xmm12, %xmm13, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x19, 0x3d, 0x28 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmaxsd (%rax), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0x11, 0x3f, 0xdc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmaxud %xmm12, %xmm13, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x19, 0x3f, 0x28 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmaxud (%rax), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0x11, 0x3e, 0xdc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmaxuw %xmm12, %xmm13, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x19, 0x3e, 0x28 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmaxuw (%rax), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0x11, 0x28, 0xdc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmuldq %xmm12, %xmm13, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x19, 0x28, 0x28 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmuldq (%rax), %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0x51, 0x40, 0xdc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmulld %xmm12, %xmm5, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x51, 0x40, 0x28 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmulld (%rax), %xmm5, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x43, 0x51, 0x0c, 0xdc, 0x03 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vblendps $3, %xmm12, %xmm5, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x63, 0x51, 0x0c, 0x18, 0x03 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vblendps $3, (%rax), %xmm5, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x43, 0x51, 0x0d, 0xdc, 0x03 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vblendpd $3, %xmm12, %xmm5, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x63, 0x51, 0x0d, 0x18, 0x03 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vblendpd $3, (%rax), %xmm5, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x43, 0x51, 0x0e, 0xdc, 0x03 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpblendw $3, %xmm12, %xmm5, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x63, 0x51, 0x0e, 0x18, 0x03 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpblendw $3, (%rax), %xmm5, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x43, 0x51, 0x42, 0xdc, 0x03 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmpsadbw $3, %xmm12, %xmm5, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x63, 0x51, 0x42, 0x18, 0x03 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmpsadbw $3, (%rax), %xmm5, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x43, 0x51, 0x40, 0xdc, 0x03 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vdpps $3, %xmm12, %xmm5, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x63, 0x51, 0x40, 0x18, 0x03 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vdpps $3, (%rax), %xmm5, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x43, 0x51, 0x41, 0xdc, 0x03 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vdppd $3, %xmm12, %xmm5, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x63, 0x51, 0x41, 0x18, 0x03 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vdppd $3, (%rax), %xmm5, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x63, 0x21, 0x4b, 0xed, 0xc0 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vblendvpd %xmm12, %xmm5, %xmm11, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x63, 0x21, 0x4b, 0x28, 0xc0 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vblendvpd %xmm12, (%rax), %xmm11, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x63, 0x21, 0x4a, 0xed, 0xc0 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vblendvps %xmm12, %xmm5, %xmm11, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x63, 0x21, 0x4a, 0x28, 0xc0 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vblendvps %xmm12, (%rax), %xmm11, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x63, 0x21, 0x4c, 0xed, 0xc0 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpblendvb %xmm12, %xmm5, %xmm11, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x63, 0x21, 0x4c, 0x28, 0xc0 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpblendvb %xmm12, (%rax), %xmm11, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0x79, 0x20, 0xd4 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmovsxbw %xmm12, %xmm10"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x79, 0x20, 0x20 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmovsxbw (%rax), %xmm12"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0x79, 0x23, 0xd4 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmovsxwd %xmm12, %xmm10"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x79, 0x23, 0x20 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmovsxwd (%rax), %xmm12"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0x79, 0x25, 0xd4 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmovsxdq %xmm12, %xmm10"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x79, 0x25, 0x20 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmovsxdq (%rax), %xmm12"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0x79, 0x30, 0xd4 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmovzxbw %xmm12, %xmm10"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x79, 0x30, 0x20 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmovzxbw (%rax), %xmm12"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0x79, 0x33, 0xd4 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmovzxwd %xmm12, %xmm10"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x79, 0x33, 0x20 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmovzxwd (%rax), %xmm12"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0x79, 0x35, 0xd4 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmovzxdq %xmm12, %xmm10"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x79, 0x35, 0x20 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmovzxdq (%rax), %xmm12"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0x79, 0x22, 0xd4 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmovsxbq %xmm12, %xmm10"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x79, 0x22, 0x20 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmovsxbq (%rax), %xmm12"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0x79, 0x32, 0xd4 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmovzxbq %xmm12, %xmm10"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x79, 0x32, 0x20 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmovzxbq (%rax), %xmm12"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0x79, 0x21, 0xd4 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmovsxbd %xmm12, %xmm10"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x79, 0x21, 0x20 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmovsxbd (%rax), %xmm12"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0x79, 0x24, 0xd4 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmovsxwq %xmm12, %xmm10"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x79, 0x24, 0x20 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmovsxwq (%rax), %xmm12"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0x79, 0x31, 0xd4 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmovzxbd %xmm12, %xmm10"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x79, 0x31, 0x20 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmovzxbd (%rax), %xmm12"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0x79, 0x34, 0xd4 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmovzxwq %xmm12, %xmm10"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x79, 0x34, 0x20 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmovzxwq (%rax), %xmm12"
+  -
+    input:
+      bytes: [ 0xc4, 0xc1, 0x79, 0xc5, 0xc4, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpextrw $7, %xmm12, %eax"
+  -
+    input:
+      bytes: [ 0xc4, 0x63, 0x79, 0x15, 0x20, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpextrw $7, %xmm12, (%rax)"
+  -
+    input:
+      bytes: [ 0xc4, 0x63, 0x79, 0x16, 0xe0, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpextrd $7, %xmm12, %eax"
+  -
+    input:
+      bytes: [ 0xc4, 0x63, 0x79, 0x16, 0x20, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpextrd $7, %xmm12, (%rax)"
+  -
+    input:
+      bytes: [ 0xc4, 0x63, 0x79, 0x14, 0xe0, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpextrb $7, %xmm12, %eax"
+  -
+    input:
+      bytes: [ 0xc4, 0x63, 0x79, 0x14, 0x20, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpextrb $7, %xmm12, (%rax)"
+  -
+    input:
+      bytes: [ 0xc4, 0x63, 0xf9, 0x16, 0xe1, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpextrq $7, %xmm12, %rcx"
+  -
+    input:
+      bytes: [ 0xc4, 0x63, 0xf9, 0x16, 0x21, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpextrq $7, %xmm12, (%rcx)"
+  -
+    input:
+      bytes: [ 0xc4, 0x63, 0x79, 0x17, 0x20, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vextractps $7, %xmm12, (%rax)"
+  -
+    input:
+      bytes: [ 0xc4, 0x63, 0x79, 0x17, 0xe0, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vextractps $7, %xmm12, %eax"
+  -
+    input:
+      bytes: [ 0xc5, 0x19, 0xc4, 0xd0, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpinsrw $7, %eax, %xmm12, %xmm10"
+  -
+    input:
+      bytes: [ 0xc5, 0x19, 0xc4, 0x10, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpinsrw $7, (%rax), %xmm12, %xmm10"
+  -
+    input:
+      bytes: [ 0xc4, 0x63, 0x19, 0x20, 0xd0, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpinsrb $7, %eax, %xmm12, %xmm10"
+  -
+    input:
+      bytes: [ 0xc4, 0x63, 0x19, 0x20, 0x10, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpinsrb $7, (%rax), %xmm12, %xmm10"
+  -
+    input:
+      bytes: [ 0xc4, 0x63, 0x19, 0x22, 0xd0, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpinsrd $7, %eax, %xmm12, %xmm10"
+  -
+    input:
+      bytes: [ 0xc4, 0x63, 0x19, 0x22, 0x10, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpinsrd $7, (%rax), %xmm12, %xmm10"
+  -
+    input:
+      bytes: [ 0xc4, 0x63, 0x99, 0x22, 0xd0, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpinsrq $7, %rax, %xmm12, %xmm10"
+  -
+    input:
+      bytes: [ 0xc4, 0x63, 0x99, 0x22, 0x10, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpinsrq $7, (%rax), %xmm12, %xmm10"
+  -
+    input:
+      bytes: [ 0xc4, 0x43, 0x29, 0x21, 0xdc, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vinsertps $7, %xmm12, %xmm10, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x63, 0x29, 0x21, 0x18, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vinsertps $7, (%rax), %xmm10, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0x79, 0x17, 0xd4 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vptest %xmm12, %xmm10"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x79, 0x17, 0x20 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vptest (%rax), %xmm12"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x79, 0x2a, 0x20 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovntdqa (%rax), %xmm12"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0x29, 0x37, 0xdc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpcmpgtq %xmm12, %xmm10, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x29, 0x37, 0x28 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpcmpgtq (%rax), %xmm10, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x43, 0x79, 0x62, 0xd4, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpcmpistrm $7, %xmm12, %xmm10"
+  -
+    input:
+      bytes: [ 0xc4, 0x63, 0x79, 0x62, 0x10, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpcmpistrm $7, (%rax), %xmm10"
+  -
+    input:
+      bytes: [ 0xc4, 0x43, 0x79, 0x60, 0xd4, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpcmpestrm $7, %xmm12, %xmm10"
+  -
+    input:
+      bytes: [ 0xc4, 0x63, 0x79, 0x60, 0x10, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpcmpestrm $7, (%rax), %xmm10"
+  -
+    input:
+      bytes: [ 0xc4, 0x43, 0x79, 0x63, 0xd4, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpcmpistri $7, %xmm12, %xmm10"
+  -
+    input:
+      bytes: [ 0xc4, 0x63, 0x79, 0x63, 0x10, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpcmpistri $7, (%rax), %xmm10"
+  -
+    input:
+      bytes: [ 0xc4, 0x43, 0x79, 0x61, 0xd4, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpcmpestri $7, %xmm12, %xmm10"
+  -
+    input:
+      bytes: [ 0xc4, 0x63, 0x79, 0x61, 0x10, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpcmpestri $7, (%rax), %xmm10"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0x79, 0xdb, 0xd4 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vaesimc %xmm12, %xmm10"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x79, 0xdb, 0x20 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vaesimc (%rax), %xmm12"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0x29, 0xdc, 0xdc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vaesenc %xmm12, %xmm10, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x29, 0xdc, 0x28 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vaesenc (%rax), %xmm10, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0x29, 0xdd, 0xdc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vaesenclast %xmm12, %xmm10, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x29, 0xdd, 0x28 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vaesenclast (%rax), %xmm10, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0x29, 0xde, 0xdc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vaesdec %xmm12, %xmm10, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x29, 0xde, 0x28 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vaesdec (%rax), %xmm10, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0x29, 0xdf, 0xdc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vaesdeclast %xmm12, %xmm10, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x29, 0xdf, 0x28 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vaesdeclast (%rax), %xmm10, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x43, 0x79, 0xdf, 0xd4, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vaeskeygenassist $7, %xmm12, %xmm10"
+  -
+    input:
+      bytes: [ 0xc4, 0x63, 0x79, 0xdf, 0x10, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vaeskeygenassist $7, (%rax), %xmm10"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpeq_uqps %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x09 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpngeps %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x0a ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpngtps %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x0b ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpfalseps %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x0c ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpneq_oqps %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x0d ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpgeps %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x0e ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpgtps %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x0f ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmptrueps %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpeq_osps %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x11 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmplt_oqps %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x12 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmple_oqps %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x13 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpunord_sps %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x14 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpneq_usps %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x15 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpnlt_uqps %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x16 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpnle_uqps %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x17 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpord_sps %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpeq_usps %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x19 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpnge_uqps %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x1a ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpngt_uqps %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x1b ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpfalse_osps %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x1c ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpneq_osps %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x1d ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpge_oqps %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x1e ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpgt_oqps %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x18, 0xc2, 0xeb, 0x1f ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmptrue_usps %xmm11, %xmm12, %xmm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x7c, 0x28, 0x20 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovaps (%rax), %ymm12"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x7c, 0x28, 0xe3 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovaps %ymm11, %ymm12"
+  -
+    input:
+      bytes: [ 0xc5, 0x7c, 0x29, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovaps %ymm11, (%rax)"
+  -
+    input:
+      bytes: [ 0xc5, 0x7d, 0x28, 0x20 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovapd (%rax), %ymm12"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x7d, 0x28, 0xe3 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovapd %ymm11, %ymm12"
+  -
+    input:
+      bytes: [ 0xc5, 0x7d, 0x29, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovapd %ymm11, (%rax)"
+  -
+    input:
+      bytes: [ 0xc5, 0x7c, 0x10, 0x20 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovups (%rax), %ymm12"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x7c, 0x10, 0xe3 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovups %ymm11, %ymm12"
+  -
+    input:
+      bytes: [ 0xc5, 0x7c, 0x11, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovups %ymm11, (%rax)"
+  -
+    input:
+      bytes: [ 0xc5, 0x7d, 0x10, 0x20 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovupd (%rax), %ymm12"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x7d, 0x10, 0xe3 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovupd %ymm11, %ymm12"
+  -
+    input:
+      bytes: [ 0xc5, 0x7d, 0x11, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovupd %ymm11, (%rax)"
+  -
+    input:
+      bytes: [ 0xc4, 0xc1, 0x1c, 0x15, 0xe3 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vunpckhps %ymm11, %ymm12, %ymm4"
+  -
+    input:
+      bytes: [ 0xc4, 0xc1, 0x1d, 0x15, 0xe3 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vunpckhpd %ymm11, %ymm12, %ymm4"
+  -
+    input:
+      bytes: [ 0xc4, 0xc1, 0x1c, 0x14, 0xe3 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vunpcklps %ymm11, %ymm12, %ymm4"
+  -
+    input:
+      bytes: [ 0xc4, 0xc1, 0x1d, 0x14, 0xe3 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vunpcklpd %ymm11, %ymm12, %ymm4"
+  -
+    input:
+      bytes: [ 0xc5, 0x1c, 0x15, 0x54, 0xcb, 0xfc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vunpckhps -4(%rbx, %rcx, 8), %ymm12, %ymm10"
+  -
+    input:
+      bytes: [ 0xc5, 0x1d, 0x15, 0x54, 0xcb, 0xfc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vunpckhpd -4(%rbx, %rcx, 8), %ymm12, %ymm10"
+  -
+    input:
+      bytes: [ 0xc5, 0x1c, 0x14, 0x54, 0xcb, 0xfc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vunpcklps -4(%rbx, %rcx, 8), %ymm12, %ymm10"
+  -
+    input:
+      bytes: [ 0xc5, 0x1d, 0x14, 0x54, 0xcb, 0xfc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vunpcklpd -4(%rbx, %rcx, 8), %ymm12, %ymm10"
+  -
+    input:
+      bytes: [ 0xc5, 0x7d, 0xe7, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovntdq %ymm11, (%rax)"
+  -
+    input:
+      bytes: [ 0xc5, 0x7d, 0x2b, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovntpd %ymm11, (%rax)"
+  -
+    input:
+      bytes: [ 0xc5, 0x7c, 0x2b, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovntps %ymm11, (%rax)"
+  -
+    input:
+      bytes: [ 0xc4, 0xc1, 0x78, 0x50, 0xc4 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovmskps %xmm12, %eax"
+  -
+    input:
+      bytes: [ 0xc4, 0xc1, 0x79, 0x50, 0xc4 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovmskpd %xmm12, %eax"
+  -
+    input:
+      bytes: [ 0xc4, 0xc1, 0x5c, 0x5f, 0xf4 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmaxps %ymm12, %ymm4, %ymm6"
+  -
+    input:
+      bytes: [ 0xc4, 0xc1, 0x5d, 0x5f, 0xf4 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmaxpd %ymm12, %ymm4, %ymm6"
+  -
+    input:
+      bytes: [ 0xc4, 0xc1, 0x5c, 0x5d, 0xf4 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vminps %ymm12, %ymm4, %ymm6"
+  -
+    input:
+      bytes: [ 0xc4, 0xc1, 0x5d, 0x5d, 0xf4 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vminpd %ymm12, %ymm4, %ymm6"
+  -
+    input:
+      bytes: [ 0xc4, 0xc1, 0x5c, 0x5c, 0xf4 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vsubps %ymm12, %ymm4, %ymm6"
+  -
+    input:
+      bytes: [ 0xc4, 0xc1, 0x5d, 0x5c, 0xf4 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vsubpd %ymm12, %ymm4, %ymm6"
+  -
+    input:
+      bytes: [ 0xc4, 0xc1, 0x5c, 0x5e, 0xf4 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vdivps %ymm12, %ymm4, %ymm6"
+  -
+    input:
+      bytes: [ 0xc4, 0xc1, 0x5d, 0x5e, 0xf4 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vdivpd %ymm12, %ymm4, %ymm6"
+  -
+    input:
+      bytes: [ 0xc4, 0xc1, 0x5c, 0x58, 0xf4 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vaddps %ymm12, %ymm4, %ymm6"
+  -
+    input:
+      bytes: [ 0xc4, 0xc1, 0x5d, 0x58, 0xf4 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vaddpd %ymm12, %ymm4, %ymm6"
+  -
+    input:
+      bytes: [ 0xc4, 0xc1, 0x5c, 0x59, 0xf4 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmulps %ymm12, %ymm4, %ymm6"
+  -
+    input:
+      bytes: [ 0xc4, 0xc1, 0x5d, 0x59, 0xf4 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmulpd %ymm12, %ymm4, %ymm6"
+  -
+    input:
+      bytes: [ 0xc5, 0xdc, 0x5f, 0x30 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmaxps (%rax), %ymm4, %ymm6"
+  -
+    input:
+      bytes: [ 0xc5, 0xdd, 0x5f, 0x30 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmaxpd (%rax), %ymm4, %ymm6"
+  -
+    input:
+      bytes: [ 0xc5, 0xdc, 0x5d, 0x30 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vminps (%rax), %ymm4, %ymm6"
+  -
+    input:
+      bytes: [ 0xc5, 0xdd, 0x5d, 0x30 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vminpd (%rax), %ymm4, %ymm6"
+  -
+    input:
+      bytes: [ 0xc5, 0xdc, 0x5c, 0x30 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vsubps (%rax), %ymm4, %ymm6"
+  -
+    input:
+      bytes: [ 0xc5, 0xdd, 0x5c, 0x30 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vsubpd (%rax), %ymm4, %ymm6"
+  -
+    input:
+      bytes: [ 0xc5, 0xdc, 0x5e, 0x30 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vdivps (%rax), %ymm4, %ymm6"
+  -
+    input:
+      bytes: [ 0xc5, 0xdd, 0x5e, 0x30 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vdivpd (%rax), %ymm4, %ymm6"
+  -
+    input:
+      bytes: [ 0xc5, 0xdc, 0x58, 0x30 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vaddps (%rax), %ymm4, %ymm6"
+  -
+    input:
+      bytes: [ 0xc5, 0xdd, 0x58, 0x30 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vaddpd (%rax), %ymm4, %ymm6"
+  -
+    input:
+      bytes: [ 0xc5, 0xdc, 0x59, 0x30 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmulps (%rax), %ymm4, %ymm6"
+  -
+    input:
+      bytes: [ 0xc5, 0xdd, 0x59, 0x30 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmulpd (%rax), %ymm4, %ymm6"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x7d, 0x51, 0xe3 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vsqrtpd %ymm11, %ymm12"
+  -
+    input:
+      bytes: [ 0xc5, 0x7d, 0x51, 0x20 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vsqrtpd (%rax), %ymm12"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x7c, 0x51, 0xe3 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vsqrtps %ymm11, %ymm12"
+  -
+    input:
+      bytes: [ 0xc5, 0x7c, 0x51, 0x20 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vsqrtps (%rax), %ymm12"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x7c, 0x52, 0xe3 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vrsqrtps %ymm11, %ymm12"
+  -
+    input:
+      bytes: [ 0xc5, 0x7c, 0x52, 0x20 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vrsqrtps (%rax), %ymm12"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x7c, 0x53, 0xe3 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vrcpps %ymm11, %ymm12"
+  -
+    input:
+      bytes: [ 0xc5, 0x7c, 0x53, 0x20 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vrcpps (%rax), %ymm12"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x0c, 0x54, 0xdc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vandps %ymm12, %ymm14, %ymm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x0d, 0x54, 0xdc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vandpd %ymm12, %ymm14, %ymm11"
+  -
+    input:
+      bytes: [ 0xc5, 0x1c, 0x54, 0x54, 0xcb, 0xfc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vandps -4(%rbx, %rcx, 8), %ymm12, %ymm10"
+  -
+    input:
+      bytes: [ 0xc5, 0x1d, 0x54, 0x54, 0xcb, 0xfc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vandpd -4(%rbx, %rcx, 8), %ymm12, %ymm10"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x0c, 0x56, 0xdc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vorps %ymm12, %ymm14, %ymm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x0d, 0x56, 0xdc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vorpd %ymm12, %ymm14, %ymm11"
+  -
+    input:
+      bytes: [ 0xc5, 0x1c, 0x56, 0x54, 0xcb, 0xfc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vorps -4(%rbx, %rcx, 8), %ymm12, %ymm10"
+  -
+    input:
+      bytes: [ 0xc5, 0x1d, 0x56, 0x54, 0xcb, 0xfc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vorpd -4(%rbx, %rcx, 8), %ymm12, %ymm10"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x0c, 0x57, 0xdc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vxorps %ymm12, %ymm14, %ymm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x0d, 0x57, 0xdc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vxorpd %ymm12, %ymm14, %ymm11"
+  -
+    input:
+      bytes: [ 0xc5, 0x1c, 0x57, 0x54, 0xcb, 0xfc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vxorps -4(%rbx, %rcx, 8), %ymm12, %ymm10"
+  -
+    input:
+      bytes: [ 0xc5, 0x1d, 0x57, 0x54, 0xcb, 0xfc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vxorpd -4(%rbx, %rcx, 8), %ymm12, %ymm10"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x0c, 0x55, 0xdc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vandnps %ymm12, %ymm14, %ymm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x0d, 0x55, 0xdc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vandnpd %ymm12, %ymm14, %ymm11"
+  -
+    input:
+      bytes: [ 0xc5, 0x1c, 0x55, 0x54, 0xcb, 0xfc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vandnps -4(%rbx, %rcx, 8), %ymm12, %ymm10"
+  -
+    input:
+      bytes: [ 0xc5, 0x1d, 0x55, 0x54, 0xcb, 0xfc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vandnpd -4(%rbx, %rcx, 8), %ymm12, %ymm10"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x7c, 0x5a, 0xe5 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvtps2pd %xmm13, %ymm12"
+  -
+    input:
+      bytes: [ 0xc5, 0x7c, 0x5a, 0x20 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvtps2pd (%rax), %ymm12"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x7e, 0xe6, 0xe5 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvtdq2pd %xmm13, %ymm12"
+  -
+    input:
+      bytes: [ 0xc5, 0x7e, 0xe6, 0x20 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvtdq2pd (%rax), %ymm12"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x7c, 0x5b, 0xd4 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvtdq2ps %ymm12, %ymm10"
+  -
+    input:
+      bytes: [ 0xc5, 0x7c, 0x5b, 0x20 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvtdq2ps (%rax), %ymm12"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x7d, 0x5b, 0xd4 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvtps2dq %ymm12, %ymm10"
+  -
+    input:
+      bytes: [ 0xc5, 0x7d, 0x5b, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvtps2dq (%rax), %ymm10"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x7e, 0x5b, 0xd4 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvttps2dq %ymm12, %ymm10"
+  -
+    input:
+      bytes: [ 0xc5, 0x7e, 0x5b, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvttps2dq (%rax), %ymm10"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x79, 0xe6, 0xd3 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvttpd2dq %xmm11, %xmm10"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x7d, 0xe6, 0xd4 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvttpd2dq %ymm12, %xmm10"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x79, 0xe6, 0xd3 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvttpd2dq %xmm11, %xmm10"
+  -
+    input:
+      bytes: [ 0xc5, 0x79, 0xe6, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvttpd2dqx (%rax), %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x7d, 0xe6, 0xdc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvttpd2dq %ymm12, %xmm11"
+  -
+    input:
+      bytes: [ 0xc5, 0x7d, 0xe6, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvttpd2dqy (%rax), %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x7d, 0x5a, 0xd4 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvtpd2ps %ymm12, %xmm10"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x79, 0x5a, 0xd3 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvtpd2ps %xmm11, %xmm10"
+  -
+    input:
+      bytes: [ 0xc5, 0x79, 0x5a, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvtpd2psx (%rax), %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x7d, 0x5a, 0xdc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvtpd2ps %ymm12, %xmm11"
+  -
+    input:
+      bytes: [ 0xc5, 0x7d, 0x5a, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvtpd2psy (%rax), %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x7f, 0xe6, 0xd4 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvtpd2dq %ymm12, %xmm10"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x7f, 0xe6, 0xdc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvtpd2dq %ymm12, %xmm11"
+  -
+    input:
+      bytes: [ 0xc5, 0x7f, 0xe6, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvtpd2dqy (%rax), %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x7b, 0xe6, 0xd3 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvtpd2dq %xmm11, %xmm10"
+  -
+    input:
+      bytes: [ 0xc5, 0x7b, 0xe6, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvtpd2dqx (%rax), %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x1c, 0xc2, 0xeb, 0x00 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpeqps %ymm11, %ymm12, %ymm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x1c, 0xc2, 0xeb, 0x02 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpleps %ymm11, %ymm12, %ymm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x1c, 0xc2, 0xeb, 0x01 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpltps %ymm11, %ymm12, %ymm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x1c, 0xc2, 0xeb, 0x04 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpneqps %ymm11, %ymm12, %ymm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x1c, 0xc2, 0xeb, 0x06 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpnleps %ymm11, %ymm12, %ymm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x1c, 0xc2, 0xeb, 0x05 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpnltps %ymm11, %ymm12, %ymm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x1c, 0xc2, 0xeb, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpordps %ymm11, %ymm12, %ymm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x1c, 0xc2, 0xeb, 0x03 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpunordps %ymm11, %ymm12, %ymm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x1c, 0xc2, 0x6c, 0xcb, 0xfc, 0x00 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpeqps -4(%rbx, %rcx, 8), %ymm12, %ymm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x1c, 0xc2, 0x6c, 0xcb, 0xfc, 0x02 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpleps -4(%rbx, %rcx, 8), %ymm12, %ymm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x1c, 0xc2, 0x6c, 0xcb, 0xfc, 0x01 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpltps -4(%rbx, %rcx, 8), %ymm12, %ymm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x1c, 0xc2, 0x6c, 0xcb, 0xfc, 0x04 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpneqps -4(%rbx, %rcx, 8), %ymm12, %ymm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x1c, 0xc2, 0x6c, 0xcb, 0xfc, 0x06 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpnleps -4(%rbx, %rcx, 8), %ymm12, %ymm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x1c, 0xc2, 0x6c, 0xcb, 0xfc, 0x05 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpnltps -4(%rbx, %rcx, 8), %ymm12, %ymm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x4c, 0xc2, 0x64, 0xcb, 0xfc, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpordps -4(%rbx, %rcx, 8), %ymm6, %ymm12"
+  -
+    input:
+      bytes: [ 0xc5, 0x1c, 0xc2, 0x6c, 0xcb, 0xfc, 0x03 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpunordps -4(%rbx, %rcx, 8), %ymm12, %ymm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x1d, 0xc2, 0xeb, 0x00 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpeqpd %ymm11, %ymm12, %ymm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x1d, 0xc2, 0xeb, 0x02 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmplepd %ymm11, %ymm12, %ymm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x1d, 0xc2, 0xeb, 0x01 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpltpd %ymm11, %ymm12, %ymm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x1d, 0xc2, 0xeb, 0x04 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpneqpd %ymm11, %ymm12, %ymm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x1d, 0xc2, 0xeb, 0x06 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpnlepd %ymm11, %ymm12, %ymm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x1d, 0xc2, 0xeb, 0x05 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpnltpd %ymm11, %ymm12, %ymm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x1d, 0xc2, 0xeb, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpordpd %ymm11, %ymm12, %ymm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x1d, 0xc2, 0xeb, 0x03 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpunordpd %ymm11, %ymm12, %ymm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x1d, 0xc2, 0x6c, 0xcb, 0xfc, 0x00 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpeqpd -4(%rbx, %rcx, 8), %ymm12, %ymm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x1d, 0xc2, 0x6c, 0xcb, 0xfc, 0x02 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmplepd -4(%rbx, %rcx, 8), %ymm12, %ymm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x1d, 0xc2, 0x6c, 0xcb, 0xfc, 0x01 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpltpd -4(%rbx, %rcx, 8), %ymm12, %ymm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x1d, 0xc2, 0x6c, 0xcb, 0xfc, 0x04 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpneqpd -4(%rbx, %rcx, 8), %ymm12, %ymm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x1d, 0xc2, 0x6c, 0xcb, 0xfc, 0x06 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpnlepd -4(%rbx, %rcx, 8), %ymm12, %ymm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x1d, 0xc2, 0x6c, 0xcb, 0xfc, 0x05 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpnltpd -4(%rbx, %rcx, 8), %ymm12, %ymm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x4d, 0xc2, 0x64, 0xcb, 0xfc, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpordpd -4(%rbx, %rcx, 8), %ymm6, %ymm12"
+  -
+    input:
+      bytes: [ 0xc5, 0x1d, 0xc2, 0x6c, 0xcb, 0xfc, 0x03 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpunordpd -4(%rbx, %rcx, 8), %ymm12, %ymm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x1c, 0xc2, 0xeb, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpeq_uqps %ymm11, %ymm12, %ymm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x1c, 0xc2, 0xeb, 0x09 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpngeps %ymm11, %ymm12, %ymm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x1c, 0xc2, 0xeb, 0x0a ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpngtps %ymm11, %ymm12, %ymm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x1c, 0xc2, 0xeb, 0x0b ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpfalseps %ymm11, %ymm12, %ymm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x1c, 0xc2, 0xeb, 0x0c ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpneq_oqps %ymm11, %ymm12, %ymm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x1c, 0xc2, 0xeb, 0x0d ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpgeps %ymm11, %ymm12, %ymm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x1c, 0xc2, 0xeb, 0x0e ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpgtps %ymm11, %ymm12, %ymm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x1c, 0xc2, 0xeb, 0x0f ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmptrueps %ymm11, %ymm12, %ymm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x1c, 0xc2, 0xeb, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpeq_osps %ymm11, %ymm12, %ymm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x1c, 0xc2, 0xeb, 0x11 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmplt_oqps %ymm11, %ymm12, %ymm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x1c, 0xc2, 0xeb, 0x12 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmple_oqps %ymm11, %ymm12, %ymm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x1c, 0xc2, 0xeb, 0x13 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpunord_sps %ymm11, %ymm12, %ymm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x1c, 0xc2, 0xeb, 0x14 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpneq_usps %ymm11, %ymm12, %ymm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x1c, 0xc2, 0xeb, 0x15 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpnlt_uqps %ymm11, %ymm12, %ymm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x1c, 0xc2, 0xeb, 0x16 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpnle_uqps %ymm11, %ymm12, %ymm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x1c, 0xc2, 0xeb, 0x17 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpord_sps %ymm11, %ymm12, %ymm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x1c, 0xc2, 0xeb, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpeq_usps %ymm11, %ymm12, %ymm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x1c, 0xc2, 0xeb, 0x19 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpnge_uqps %ymm11, %ymm12, %ymm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x1c, 0xc2, 0xeb, 0x1a ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpngt_uqps %ymm11, %ymm12, %ymm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x1c, 0xc2, 0xeb, 0x1b ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpfalse_osps %ymm11, %ymm12, %ymm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x1c, 0xc2, 0xeb, 0x1c ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpneq_osps %ymm11, %ymm12, %ymm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x1c, 0xc2, 0xeb, 0x1d ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpge_oqps %ymm11, %ymm12, %ymm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x1c, 0xc2, 0xeb, 0x1e ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmpgt_oqps %ymm11, %ymm12, %ymm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x1c, 0xc2, 0xeb, 0x1f ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcmptrue_usps %ymm11, %ymm12, %ymm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x1f, 0xd0, 0xeb ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vaddsubps %ymm11, %ymm12, %ymm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x27, 0xd0, 0x20 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vaddsubps (%rax), %ymm11, %ymm12"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x1d, 0xd0, 0xeb ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vaddsubpd %ymm11, %ymm12, %ymm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x25, 0xd0, 0x20 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vaddsubpd (%rax), %ymm11, %ymm12"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x1f, 0x7c, 0xeb ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vhaddps %ymm11, %ymm12, %ymm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x1f, 0x7c, 0x28 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vhaddps (%rax), %ymm12, %ymm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x1d, 0x7c, 0xeb ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vhaddpd %ymm11, %ymm12, %ymm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x1d, 0x7c, 0x28 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vhaddpd (%rax), %ymm12, %ymm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x1f, 0x7d, 0xeb ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vhsubps %ymm11, %ymm12, %ymm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x1f, 0x7d, 0x28 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vhsubps (%rax), %ymm12, %ymm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x1d, 0x7d, 0xeb ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vhsubpd %ymm11, %ymm12, %ymm13"
+  -
+    input:
+      bytes: [ 0xc5, 0x1d, 0x7d, 0x28 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vhsubpd (%rax), %ymm12, %ymm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x43, 0x2d, 0x0c, 0xdc, 0x03 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vblendps $3, %ymm12, %ymm10, %ymm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x63, 0x2d, 0x0c, 0x18, 0x03 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vblendps $3, (%rax), %ymm10, %ymm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x43, 0x2d, 0x0d, 0xdc, 0x03 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vblendpd $3, %ymm12, %ymm10, %ymm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x63, 0x2d, 0x0d, 0x18, 0x03 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vblendpd $3, (%rax), %ymm10, %ymm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x43, 0x2d, 0x40, 0xdc, 0x03 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vdpps $3, %ymm12, %ymm10, %ymm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x63, 0x2d, 0x40, 0x18, 0x03 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vdpps $3, (%rax), %ymm10, %ymm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x7d, 0x1a, 0x20 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vbroadcastf128 (%rax), %ymm12"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x7d, 0x19, 0x20 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vbroadcastsd (%rax), %ymm12"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x79, 0x18, 0x20 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vbroadcastss (%rax), %xmm12"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x7d, 0x18, 0x20 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vbroadcastss (%rax), %ymm12"
+  -
+    input:
+      bytes: [ 0xc4, 0x43, 0x1d, 0x18, 0xd4, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vinsertf128 $7, %xmm12, %ymm12, %ymm10"
+  -
+    input:
+      bytes: [ 0xc4, 0x63, 0x1d, 0x18, 0x10, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vinsertf128 $7, (%rax), %ymm12, %ymm10"
+  -
+    input:
+      bytes: [ 0xc4, 0x43, 0x7d, 0x19, 0xe4, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vextractf128 $7, %ymm12, %xmm12"
+  -
+    input:
+      bytes: [ 0xc4, 0x63, 0x7d, 0x19, 0x20, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vextractf128 $7, %ymm12, (%rax)"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x29, 0x2f, 0x20 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmaskmovpd %xmm12, %xmm10, (%rax)"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x2d, 0x2f, 0x20 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmaskmovpd %ymm12, %ymm10, (%rax)"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x19, 0x2d, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmaskmovpd (%rax), %xmm12, %xmm10"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x1d, 0x2d, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmaskmovpd (%rax), %ymm12, %ymm10"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x29, 0x2e, 0x20 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmaskmovps %xmm12, %xmm10, (%rax)"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x2d, 0x2e, 0x20 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmaskmovps %ymm12, %ymm10, (%rax)"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x19, 0x2c, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmaskmovps (%rax), %xmm12, %xmm10"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x1d, 0x2c, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmaskmovps (%rax), %ymm12, %ymm10"
+  -
+    input:
+      bytes: [ 0xc4, 0x43, 0x79, 0x04, 0xd3, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpermilps $7, %xmm11, %xmm10"
+  -
+    input:
+      bytes: [ 0xc4, 0x43, 0x7d, 0x04, 0xda, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpermilps $7, %ymm10, %ymm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x63, 0x79, 0x04, 0x10, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpermilps $7, (%rax), %xmm10"
+  -
+    input:
+      bytes: [ 0xc4, 0x63, 0x7d, 0x04, 0x10, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpermilps $7, (%rax), %ymm10"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0x29, 0x0c, 0xdb ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpermilps %xmm11, %xmm10, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0x2d, 0x0c, 0xdb ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpermilps %ymm11, %ymm10, %ymm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x29, 0x0c, 0x28 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpermilps (%rax), %xmm10, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x2d, 0x0c, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpermilps (%rax), %ymm10, %ymm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x43, 0x79, 0x05, 0xd3, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpermilpd $7, %xmm11, %xmm10"
+  -
+    input:
+      bytes: [ 0xc4, 0x43, 0x7d, 0x05, 0xda, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpermilpd $7, %ymm10, %ymm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x63, 0x79, 0x05, 0x10, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpermilpd $7, (%rax), %xmm10"
+  -
+    input:
+      bytes: [ 0xc4, 0x63, 0x7d, 0x05, 0x10, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpermilpd $7, (%rax), %ymm10"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0x29, 0x0d, 0xdb ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpermilpd %xmm11, %xmm10, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0x2d, 0x0d, 0xdb ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpermilpd %ymm11, %ymm10, %ymm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x29, 0x0d, 0x28 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpermilpd (%rax), %xmm10, %xmm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x2d, 0x0d, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpermilpd (%rax), %ymm10, %ymm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x43, 0x2d, 0x06, 0xdc, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vperm2f128 $7, %ymm12, %ymm10, %ymm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x63, 0x2d, 0x06, 0x18, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vperm2f128 $7, (%rax), %ymm10, %ymm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x7b, 0x2d, 0xc0 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvtsd2si %xmm8, %r8d"
+  -
+    input:
+      bytes: [ 0xc5, 0xfb, 0x2d, 0x09 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvtsd2si (%rcx), %ecx"
+  -
+    input:
+      bytes: [ 0xc4, 0xe1, 0xfa, 0x2d, 0xcc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvtss2si %xmm4, %rcx"
+  -
+    input:
+      bytes: [ 0xc4, 0x61, 0xfa, 0x2d, 0x01 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvtss2si (%rcx), %r8"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x3b, 0x2a, 0xf8 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvtsi2sdl %r8d, %xmm8, %xmm15"
+  -
+    input:
+      bytes: [ 0xc5, 0x3b, 0x2a, 0x7d, 0x00 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvtsi2sdl (%rbp), %xmm8, %xmm15"
+  -
+    input:
+      bytes: [ 0xc4, 0xe1, 0xdb, 0x2a, 0xf1 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvtsi2sdq %rcx, %xmm4, %xmm6"
+  -
+    input:
+      bytes: [ 0xc4, 0xe1, 0xdb, 0x2a, 0x31 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvtsi2sdq (%rcx), %xmm4, %xmm6"
+  -
+    input:
+      bytes: [ 0xc4, 0xe1, 0xda, 0x2a, 0xf1 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvtsi2ssq %rcx, %xmm4, %xmm6"
+  -
+    input:
+      bytes: [ 0xc4, 0xe1, 0xda, 0x2a, 0x31 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvtsi2ssq (%rcx), %xmm4, %xmm6"
+  -
+    input:
+      bytes: [ 0xc4, 0xe1, 0xfb, 0x2c, 0xcc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvttsd2si %xmm4, %rcx"
+  -
+    input:
+      bytes: [ 0xc4, 0xe1, 0xfb, 0x2c, 0x09 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvttsd2si (%rcx), %rcx"
+  -
+    input:
+      bytes: [ 0xc4, 0xe1, 0xfa, 0x2c, 0xcc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvttss2si %xmm4, %rcx"
+  -
+    input:
+      bytes: [ 0xc4, 0xe1, 0xfa, 0x2c, 0x09 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vcvttss2si (%rcx), %rcx"
+  -
+    input:
+      bytes: [ 0xc5, 0x7f, 0xf0, 0x20 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vlddqu (%rax), %ymm12"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x7f, 0x12, 0xd4 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovddup %ymm12, %ymm10"
+  -
+    input:
+      bytes: [ 0xc5, 0x7f, 0x12, 0x20 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovddup (%rax), %ymm12"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x7d, 0x6f, 0xd4 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovdqa %ymm12, %ymm10"
+  -
+    input:
+      bytes: [ 0xc5, 0x7d, 0x7f, 0x20 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovdqa %ymm12, (%rax)"
+  -
+    input:
+      bytes: [ 0xc5, 0x7d, 0x6f, 0x20 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovdqa (%rax), %ymm12"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x7e, 0x6f, 0xd4 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovdqu %ymm12, %ymm10"
+  -
+    input:
+      bytes: [ 0xc5, 0x7e, 0x7f, 0x20 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovdqu %ymm12, (%rax)"
+  -
+    input:
+      bytes: [ 0xc5, 0x7e, 0x6f, 0x20 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovdqu (%rax), %ymm12"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x7e, 0x16, 0xd4 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovshdup %ymm12, %ymm10"
+  -
+    input:
+      bytes: [ 0xc5, 0x7e, 0x16, 0x20 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovshdup (%rax), %ymm12"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x7e, 0x12, 0xd4 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovsldup %ymm12, %ymm10"
+  -
+    input:
+      bytes: [ 0xc5, 0x7e, 0x12, 0x20 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovsldup (%rax), %ymm12"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0x7d, 0x17, 0xd4 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vptest %ymm12, %ymm10"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x7d, 0x17, 0x20 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vptest (%rax), %ymm12"
+  -
+    input:
+      bytes: [ 0xc4, 0x43, 0x7d, 0x09, 0xda, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vroundpd $7, %ymm10, %ymm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x63, 0x7d, 0x09, 0x10, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vroundpd $7, (%rax), %ymm10"
+  -
+    input:
+      bytes: [ 0xc4, 0x43, 0x7d, 0x08, 0xda, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vroundps $7, %ymm10, %ymm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x63, 0x7d, 0x08, 0x10, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vroundps $7, (%rax), %ymm10"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x2d, 0xc6, 0xdc, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vshufpd $7, %ymm12, %ymm10, %ymm11"
+  -
+    input:
+      bytes: [ 0xc5, 0x2d, 0xc6, 0x18, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vshufpd $7, (%rax), %ymm10, %ymm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x2c, 0xc6, 0xdc, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vshufps $7, %ymm12, %ymm10, %ymm11"
+  -
+    input:
+      bytes: [ 0xc5, 0x2c, 0xc6, 0x18, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vshufps $7, (%rax), %ymm10, %ymm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0x79, 0x0f, 0xd4 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vtestpd %xmm12, %xmm10"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0x7d, 0x0f, 0xd4 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vtestpd %ymm12, %ymm10"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x79, 0x0f, 0x20 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vtestpd (%rax), %xmm12"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x7d, 0x0f, 0x20 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vtestpd (%rax), %ymm12"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0x79, 0x0e, 0xd4 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vtestps %xmm12, %xmm10"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0x7d, 0x0e, 0xd4 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vtestps %ymm12, %ymm10"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x79, 0x0e, 0x20 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vtestps (%rax), %xmm12"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x7d, 0x0e, 0x20 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vtestps (%rax), %ymm12"
+  -
+    input:
+      bytes: [ 0xc4, 0x43, 0x79, 0x17, 0xc0, 0x0a ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vextractps $10, %xmm8, %r8d"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x79, 0x17, 0xe1, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vextractps $7, %xmm4, %ecx"
+  -
+    input:
+      bytes: [ 0xc4, 0xe1, 0xf9, 0x7e, 0xe1 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovq %xmm4, %rcx"
+  -
+    input:
+      bytes: [ 0xc5, 0xf9, 0x50, 0xcc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovmskpd %xmm4, %ecx"
+  -
+    input:
+      bytes: [ 0xc5, 0xfd, 0x50, 0xcc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovmskpd %ymm4, %ecx"
+  -
+    input:
+      bytes: [ 0xc5, 0xf8, 0x50, 0xcc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovmskps %xmm4, %ecx"
+  -
+    input:
+      bytes: [ 0xc5, 0xfc, 0x50, 0xcc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovmskps %ymm4, %ecx"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x79, 0x14, 0xe1, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpextrb $7, %xmm4, %ecx"
+  -
+    input:
+      bytes: [ 0xc4, 0x41, 0x01, 0xc4, 0xc0, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpinsrw $7, %r8d, %xmm15, %xmm8"
+  -
+    input:
+      bytes: [ 0xc5, 0xd9, 0xc4, 0xf1, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpinsrw $7, %ecx, %xmm4, %xmm6"
+  -
+    input:
+      bytes: [ 0xc5, 0xf9, 0xd7, 0xcc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmovmskb %xmm4, %ecx"
+  -
+    input:
+      bytes: [ 0xc4, 0x63, 0x1d, 0x4b, 0xac, 0x20, 0xad, 0xde, 0x00, 0x00, 0xb0 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vblendvpd %ymm11, 0xdead(%rax, %riz), %ymm12, %ymm13"
+  -
+    input:
+      bytes: [ 0xc4, 0x81, 0x78, 0x29, 0x1c, 0x1e ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovaps %xmm3, (%r14, %r11)"
+  -
+    input:
+      bytes: [ 0xc4, 0x81, 0x78, 0x28, 0x1c, 0x1e ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovaps (%r14, %r11), %xmm3"
+  -
+    input:
+      bytes: [ 0xc4, 0xc1, 0x78, 0x29, 0x1c, 0x1e ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovaps %xmm3, (%r14, %rbx)"
+  -
+    input:
+      bytes: [ 0xc4, 0xc1, 0x78, 0x28, 0x1c, 0x1e ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovaps (%r14, %rbx), %xmm3"
+  -
+    input:
+      bytes: [ 0xc4, 0xa1, 0x78, 0x29, 0x1c, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovaps %xmm3, (%rax, %r11)"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0xf9, 0x92, 0x14, 0x4f ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vgatherdpd %xmm0, (%rdi, %xmm1, 2), %xmm2"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0xf9, 0x93, 0x14, 0x4f ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vgatherqpd %xmm0, (%rdi, %xmm1, 2), %xmm2"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0xfd, 0x92, 0x14, 0x4f ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vgatherdpd %ymm0, (%rdi, %xmm1, 2), %ymm2"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0xfd, 0x93, 0x14, 0x4f ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vgatherqpd %ymm0, (%rdi, %ymm1, 2), %ymm2"
+  -
+    input:
+      bytes: [ 0xc4, 0x02, 0x39, 0x92, 0x14, 0x4f ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vgatherdps %xmm8, (%r15, %xmm9, 2), %xmm10"
+  -
+    input:
+      bytes: [ 0xc4, 0x02, 0x39, 0x93, 0x14, 0x4f ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vgatherqps %xmm8, (%r15, %xmm9, 2), %xmm10"
+  -
+    input:
+      bytes: [ 0xc4, 0x02, 0x3d, 0x92, 0x14, 0x4f ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vgatherdps %ymm8, (%r15, %ymm9, 2), %ymm10"
+  -
+    input:
+      bytes: [ 0xc4, 0x02, 0x3d, 0x93, 0x14, 0x4f ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vgatherqps %xmm8, (%r15, %ymm9, 2), %xmm10"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0xf9, 0x90, 0x14, 0x4f ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpgatherdq %xmm0, (%rdi, %xmm1, 2), %xmm2"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0xf9, 0x91, 0x14, 0x4f ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpgatherqq %xmm0, (%rdi, %xmm1, 2), %xmm2"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0xfd, 0x90, 0x14, 0x4f ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpgatherdq %ymm0, (%rdi, %xmm1, 2), %ymm2"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0xfd, 0x91, 0x14, 0x4f ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpgatherqq %ymm0, (%rdi, %ymm1, 2), %ymm2"
+  -
+    input:
+      bytes: [ 0xc4, 0x02, 0x39, 0x90, 0x14, 0x4f ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpgatherdd %xmm8, (%r15, %xmm9, 2), %xmm10"
+  -
+    input:
+      bytes: [ 0xc4, 0x02, 0x39, 0x91, 0x14, 0x4f ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpgatherqd %xmm8, (%r15, %xmm9, 2), %xmm10"
+  -
+    input:
+      bytes: [ 0xc4, 0x02, 0x3d, 0x90, 0x14, 0x4f ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpgatherdd %ymm8, (%r15, %ymm9, 2), %ymm10"
+  -
+    input:
+      bytes: [ 0xc4, 0x02, 0x3d, 0x91, 0x14, 0x4f ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpgatherqd %xmm8, (%r15, %ymm9, 2), %xmm10"
+  -
+    input:
+      bytes: [ 0xc5, 0x78, 0x28, 0xc0 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovaps %xmm0, %xmm8"
+  -
+    input:
+      bytes: [ 0xc5, 0x78, 0x29, 0xc0 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovaps %xmm8, %xmm0"
+  -
+    input:
+      bytes: [ 0xc5, 0x7c, 0x28, 0xc0 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovaps %ymm0, %ymm8"
+  -
+    input:
+      bytes: [ 0xc5, 0x7c, 0x29, 0xc0 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovaps %ymm8, %ymm0"
+  -
+    input:
+      bytes: [ 0xc5, 0x78, 0x10, 0xc0 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovups %xmm0, %xmm8"
+  -
+    input:
+      bytes: [ 0xc5, 0x78, 0x11, 0xc0 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovups %xmm8, %xmm0"
+  -
+    input:
+      bytes: [ 0xc5, 0x7c, 0x10, 0xc0 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovups %ymm0, %ymm8"
+  -
+    input:
+      bytes: [ 0xc5, 0x7c, 0x11, 0xc0 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovups %ymm8, %ymm0"
+  -
+    input:
+      bytes: [ 0xc5, 0x7a, 0x10, 0xc0 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovss %xmm0, %xmm0, %xmm8"
+  -
+    input:
+      bytes: [ 0xc5, 0xba, 0x10, 0xc0 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovss %xmm0, %xmm8, %xmm0"
+  -
+    input:
+      bytes: [ 0xc5, 0x7a, 0x11, 0xc0 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovss %xmm8, %xmm0, %xmm0"
+  -
+    input:
+      bytes: [ 0xc5, 0x7b, 0x10, 0xc0 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovsd %xmm0, %xmm0, %xmm8"
+  -
+    input:
+      bytes: [ 0xc5, 0xbb, 0x10, 0xc0 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovsd %xmm0, %xmm8, %xmm0"
+  -
+    input:
+      bytes: [ 0xc5, 0x7b, 0x11, 0xc0 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vmovsd %xmm8, %xmm0, %xmm0"
diff --git a/tests/MC/X86/x86_64-bmi-encoding.s.yaml b/tests/MC/X86/x86_64-bmi-encoding.s.yaml
new file mode 100644
index 000000000..af5be80f7
--- /dev/null
+++ b/tests/MC/X86/x86_64-bmi-encoding.s.yaml
@@ -0,0 +1,451 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xc4, 0xc2, 0x28, 0xf3, 0xd3 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "blsmskl %r11d, %r10d"
+  -
+    input:
+      bytes: [ 0xc4, 0xc2, 0xa8, 0xf3, 0xd3 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "blsmskq %r11, %r10"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x28, 0xf3, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "blsmskl (%rax), %r10d"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0xa8, 0xf3, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "blsmskq (%rax), %r10"
+  -
+    input:
+      bytes: [ 0xc4, 0xc2, 0x28, 0xf3, 0xdb ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "blsil %r11d, %r10d"
+  -
+    input:
+      bytes: [ 0xc4, 0xc2, 0xa8, 0xf3, 0xdb ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "blsiq %r11, %r10"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x28, 0xf3, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "blsil (%rax), %r10d"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0xa8, 0xf3, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "blsiq (%rax), %r10"
+  -
+    input:
+      bytes: [ 0xc4, 0xc2, 0x28, 0xf3, 0xcb ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "blsrl %r11d, %r10d"
+  -
+    input:
+      bytes: [ 0xc4, 0xc2, 0xa8, 0xf3, 0xcb ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "blsrq %r11, %r10"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0x28, 0xf3, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "blsrl (%rax), %r10d"
+  -
+    input:
+      bytes: [ 0xc4, 0xe2, 0xa8, 0xf3, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "blsrq (%rax), %r10"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x20, 0xf2, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "andnl (%rax), %r11d, %r10d"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0xa0, 0xf2, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "andnq (%rax), %r11, %r10"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x18, 0xf7, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "bextrl %r12d, (%rax), %r10d"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0x18, 0xf7, 0xd3 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "bextrl %r12d, %r11d, %r10d"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x98, 0xf7, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "bextrq %r12, (%rax), %r10"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0x98, 0xf7, 0xd3 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "bextrq %r12, %r11, %r10"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x18, 0xf5, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "bzhil %r12d, (%rax), %r10d"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0x18, 0xf5, 0xd3 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "bzhil %r12d, %r11d, %r10d"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x98, 0xf5, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "bzhiq %r12, (%rax), %r10"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0x98, 0xf5, 0xd3 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "bzhiq %r12, %r11, %r10"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0x22, 0xf5, 0xd4 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "pextl %r12d, %r11d, %r10d"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x22, 0xf5, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "pextl (%rax), %r11d, %r10d"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0xa2, 0xf5, 0xd4 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "pextq %r12, %r11, %r10"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0xa2, 0xf5, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "pextq (%rax), %r11, %r10"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0x23, 0xf5, 0xd4 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "pdepl %r12d, %r11d, %r10d"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x23, 0xf5, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "pdepl (%rax), %r11d, %r10d"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0xa3, 0xf5, 0xd4 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "pdepq %r12, %r11, %r10"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0xa3, 0xf5, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "pdepq (%rax), %r11, %r10"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0x23, 0xf6, 0xd4 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulxl %r12d, %r11d, %r10d"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x23, 0xf6, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulxl (%rax), %r11d, %r10d"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0xa3, 0xf6, 0xd4 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulxq %r12, %r11, %r10"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0xa3, 0xf6, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "mulxq (%rax), %r11, %r10"
+  -
+    input:
+      bytes: [ 0xc4, 0x43, 0x7b, 0xf0, 0xd4, 0x0a ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rorxl $10, %r12d, %r10d"
+  -
+    input:
+      bytes: [ 0xc4, 0x63, 0x7b, 0xf0, 0x10, 0x1f ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rorxl $31, (%rax), %r10d"
+  -
+    input:
+      bytes: [ 0xc4, 0x43, 0xfb, 0xf0, 0xd4, 0x01 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rorxq $1, %r12, %r10"
+  -
+    input:
+      bytes: [ 0xc4, 0x63, 0xfb, 0xf0, 0x10, 0x3f ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rorxq $63, (%rax), %r10"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x19, 0xf7, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "shlxl %r12d, (%rax), %r10d"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0x19, 0xf7, 0xd3 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "shlxl %r12d, %r11d, %r10d"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x99, 0xf7, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "shlxq %r12, (%rax), %r10"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0x99, 0xf7, 0xd3 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "shlxq %r12, %r11, %r10"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x1a, 0xf7, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sarxl %r12d, (%rax), %r10d"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0x1a, 0xf7, 0xd3 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sarxl %r12d, %r11d, %r10d"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x9a, 0xf7, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sarxq %r12, (%rax), %r10"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0x9a, 0xf7, 0xd3 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sarxq %r12, %r11, %r10"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x1b, 0xf7, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "shrxl %r12d, (%rax), %r10d"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0x1b, 0xf7, 0xd3 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "shrxl %r12d, %r11d, %r10d"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x9b, 0xf7, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "shrxq %r12, (%rax), %r10"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0x9b, 0xf7, 0xd3 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "shrxq %r12, %r11, %r10"
diff --git a/tests/MC/X86/x86_64-encoding.s.yaml b/tests/MC/X86/x86_64-encoding.s.yaml
new file mode 100644
index 000000000..9c83b28e6
--- /dev/null
+++ b/tests/MC/X86/x86_64-encoding.s.yaml
@@ -0,0 +1,523 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x65, 0x48, 0x8b, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "movq %gs:(%rdi), %rax"
+  -
+    input:
+      bytes: [ 0xf2, 0x0f, 0x38, 0xf0, 0xc3 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "crc32b %bl, %eax"
+  -
+    input:
+      bytes: [ 0xf2, 0x0f, 0x38, 0xf0, 0x43, 0x04 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "crc32b 4(%rbx), %eax"
+  -
+    input:
+      bytes: [ 0x66, 0xf2, 0x0f, 0x38, 0xf1, 0xc3 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "crc32w %bx, %eax"
+  -
+    input:
+      bytes: [ 0x66, 0xf2, 0x0f, 0x38, 0xf1, 0x43, 0x04 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "crc32w 4(%rbx), %eax"
+  -
+    input:
+      bytes: [ 0xf2, 0x0f, 0x38, 0xf1, 0xc3 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "crc32l %ebx, %eax"
+  -
+    input:
+      bytes: [ 0xf2, 0x0f, 0x38, 0xf1, 0x43, 0x04 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "crc32l 4(%rbx), %eax"
+  -
+    input:
+      bytes: [ 0xf2, 0x0f, 0x38, 0xf1, 0x8c, 0xcb, 0xef, 0xbe, 0xad, 0xde ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "crc32l -0x21524111(%rbx, %rcx, 8), %ecx"
+  -
+    input:
+      bytes: [ 0xf2, 0x0f, 0x38, 0xf1, 0x0c, 0x25, 0x45, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "crc32l 0x45, %ecx"
+  -
+    input:
+      bytes: [ 0xf2, 0x0f, 0x38, 0xf1, 0x0c, 0x25, 0xed, 0x7e, 0x00, 0x00 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "crc32l 0x7eed, %ecx"
+  -
+    input:
+      bytes: [ 0xf2, 0x0f, 0x38, 0xf1, 0x0c, 0x25, 0xfe, 0xca, 0xbe, 0xba ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "crc32l 0xffffffffbabecafe, %ecx"
+  -
+    input:
+      bytes: [ 0xf2, 0x0f, 0x38, 0xf1, 0xc9 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "crc32l %ecx, %ecx"
+  -
+    input:
+      bytes: [ 0xf2, 0x41, 0x0f, 0x38, 0xf0, 0xc3 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "crc32b %r11b, %eax"
+  -
+    input:
+      bytes: [ 0xf2, 0x0f, 0x38, 0xf0, 0x43, 0x04 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "crc32b 4(%rbx), %eax"
+  -
+    input:
+      bytes: [ 0xf2, 0x48, 0x0f, 0x38, 0xf0, 0xc7 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "crc32b %dil, %rax"
+  -
+    input:
+      bytes: [ 0xf2, 0x49, 0x0f, 0x38, 0xf0, 0xc3 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "crc32b %r11b, %rax"
+  -
+    input:
+      bytes: [ 0xf2, 0x48, 0x0f, 0x38, 0xf0, 0x43, 0x04 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "crc32b 4(%rbx), %rax"
+  -
+    input:
+      bytes: [ 0xf2, 0x48, 0x0f, 0x38, 0xf1, 0xc3 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "crc32q %rbx, %rax"
+  -
+    input:
+      bytes: [ 0xf2, 0x48, 0x0f, 0x38, 0xf1, 0x43, 0x04 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "crc32q 4(%rbx), %rax"
+  -
+    input:
+      bytes: [ 0x49, 0x0f, 0x6e, 0xc8 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "movq %r8, %mm1"
+  -
+    input:
+      bytes: [ 0x41, 0x0f, 0x6e, 0xc8 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "movd %r8d, %mm1"
+  -
+    input:
+      bytes: [ 0x48, 0x0f, 0x6e, 0xca ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "movq %rdx, %mm1"
+  -
+    input:
+      bytes: [ 0x0f, 0x6e, 0xca ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "movd %edx, %mm1"
+  -
+    input:
+      bytes: [ 0x49, 0x0f, 0x7e, 0xc8 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "movq %mm1, %r8"
+  -
+    input:
+      bytes: [ 0x41, 0x0f, 0x7e, 0xc8 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "movd %mm1, %r8d"
+  -
+    input:
+      bytes: [ 0x48, 0x0f, 0x7e, 0xca ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "movq %mm1, %rdx"
+  -
+    input:
+      bytes: [ 0x0f, 0x7e, 0xca ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "movd %mm1, %edx"
+  -
+    input:
+      bytes: [ 0x0f, 0x3a, 0xcc, 0xd1, 0x01 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha1rnds4 $1, %xmm1, %xmm2"
+  -
+    input:
+      bytes: [ 0x0f, 0x3a, 0xcc, 0x10, 0x01 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha1rnds4 $1, (%rax), %xmm2"
+  -
+    input:
+      bytes: [ 0x0f, 0x38, 0xc8, 0xd1 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha1nexte %xmm1, %xmm2"
+  -
+    input:
+      bytes: [ 0x0f, 0x38, 0xc9, 0xd1 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha1msg1 %xmm1, %xmm2"
+  -
+    input:
+      bytes: [ 0x0f, 0x38, 0xc9, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha1msg1 (%rax), %xmm2"
+  -
+    input:
+      bytes: [ 0x0f, 0x38, 0xca, 0xd1 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha1msg2 %xmm1, %xmm2"
+  -
+    input:
+      bytes: [ 0x0f, 0x38, 0xca, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha1msg2 (%rax), %xmm2"
+  -
+    input:
+      bytes: [ 0x0f, 0x38, 0xcb, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha256rnds2 %xmm0, (%rax), %xmm2"
+  -
+    input:
+      bytes: [ 0x0f, 0x38, 0xcb, 0xd1 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha256rnds2 %xmm0, %xmm1, %xmm2"
+  -
+    input:
+      bytes: [ 0x0f, 0x38, 0xcb, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha256rnds2 %xmm0, (%rax), %xmm2"
+  -
+    input:
+      bytes: [ 0x0f, 0x38, 0xcb, 0xd1 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha256rnds2 %xmm0, %xmm1, %xmm2"
+  -
+    input:
+      bytes: [ 0x0f, 0x38, 0xcc, 0xd1 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha256msg1 %xmm1, %xmm2"
+  -
+    input:
+      bytes: [ 0x0f, 0x38, 0xcc, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha256msg1 (%rax), %xmm2"
+  -
+    input:
+      bytes: [ 0x0f, 0x38, 0xcd, 0xd1 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha256msg2 %xmm1, %xmm2"
+  -
+    input:
+      bytes: [ 0x0f, 0x38, 0xcd, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "sha256msg2 (%rax), %xmm2"
+  -
+    input:
+      bytes: [ 0x48, 0x8b, 0x1c, 0x25, 0xad, 0xde, 0x00, 0x00 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "movq 0xdead, %rbx"
+  -
+    input:
+      bytes: [ 0x48, 0x8b, 0x04, 0x25, 0xef, 0xbe, 0x00, 0x00 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "movq 0xbeef, %rax"
+  -
+    input:
+      bytes: [ 0x48, 0x8b, 0x04, 0xe5, 0xfc, 0xff, 0xff, 0xff ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "movq -4(, %riz, 8), %rax"
+  -
+    input:
+      bytes: [ 0x48, 0x8b, 0x04, 0x21 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "movq (%rcx, %riz), %rax"
+  -
+    input:
+      bytes: [ 0x48, 0x8b, 0x04, 0xe1 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "movq (%rcx, %riz, 8), %rax"
+  -
+    input:
+      bytes: [ 0x48, 0x0f, 0xae, 0x00 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fxsave64 (%rax)"
+  -
+    input:
+      bytes: [ 0x48, 0x0f, 0xae, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "fxrstor64 (%rax)"
+  -
+    input:
+      bytes: [ 0xc9 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "leave"
+  -
+    input:
+      bytes: [ 0xc9 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "leave"
+  -
+    input:
+      bytes: [ 0x67, 0xd9, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "flds (%edi)"
+  -
+    input:
+      bytes: [ 0x67, 0xdf, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "filds (%edi)"
+  -
+    input:
+      bytes: [ 0xd9, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "flds (%rdi)"
+  -
+    input:
+      bytes: [ 0xdf, 0x07 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "filds (%rdi)"
+  -
+    input:
+      bytes: [ 0x66, 0x0f, 0xd7, 0xcd ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "pmovmskb %xmm5, %ecx"
+  -
+    input:
+      bytes: [ 0x66, 0x0f, 0xc4, 0xe9, 0x03 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "pinsrw $3, %ecx, %xmm5"
+  -
+    input:
+      bytes: [ 0x66, 0x0f, 0xc4, 0xe9, 0x03 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "pinsrw $3, %ecx, %xmm5"
diff --git a/tests/MC/X86/x86_64-fma3-encoding.s.yaml b/tests/MC/X86/x86_64-fma3-encoding.s.yaml
new file mode 100644
index 000000000..472444201
--- /dev/null
+++ b/tests/MC/X86/x86_64-fma3-encoding.s.yaml
@@ -0,0 +1,1513 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0xa9, 0x98, 0xdc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmadd132pd %xmm12, %xmm10, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0xa9, 0x98, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmadd132pd (%rax), %xmm10, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0x29, 0x98, 0xdc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmadd132ps %xmm12, %xmm10, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x29, 0x98, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmadd132ps (%rax), %xmm10, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0xa9, 0xa8, 0xdc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmadd213pd %xmm12, %xmm10, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0xa9, 0xa8, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmadd213pd (%rax), %xmm10, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0x29, 0xa8, 0xdc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmadd213ps %xmm12, %xmm10, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x29, 0xa8, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmadd213ps (%rax), %xmm10, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0xa9, 0xb8, 0xdc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmadd231pd %xmm12, %xmm10, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0xa9, 0xb8, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmadd231pd (%rax), %xmm10, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0x29, 0xb8, 0xdc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmadd231ps %xmm12, %xmm10, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x29, 0xb8, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmadd231ps (%rax), %xmm10, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0xad, 0x98, 0xdc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmadd132pd %ymm12, %ymm10, %ymm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0xad, 0x98, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmadd132pd (%rax), %ymm10, %ymm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0x2d, 0x98, 0xdc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmadd132ps %ymm12, %ymm10, %ymm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x2d, 0x98, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmadd132ps (%rax), %ymm10, %ymm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0xad, 0xa8, 0xdc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmadd213pd %ymm12, %ymm10, %ymm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0xad, 0xa8, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmadd213pd (%rax), %ymm10, %ymm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0x2d, 0xa8, 0xdc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmadd213ps %ymm12, %ymm10, %ymm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x2d, 0xa8, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmadd213ps (%rax), %ymm10, %ymm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0xad, 0xb8, 0xdc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmadd231pd %ymm12, %ymm10, %ymm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0xad, 0xb8, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmadd231pd (%rax), %ymm10, %ymm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0x2d, 0xb8, 0xdc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmadd231ps %ymm12, %ymm10, %ymm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x2d, 0xb8, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmadd231ps (%rax), %ymm10, %ymm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0xa9, 0x98, 0xdc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmadd132pd %xmm12, %xmm10, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0xa9, 0x98, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmadd132pd (%rax), %xmm10, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0x29, 0x98, 0xdc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmadd132ps %xmm12, %xmm10, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x29, 0x98, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmadd132ps (%rax), %xmm10, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0xa9, 0xa8, 0xdc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmadd213pd %xmm12, %xmm10, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0xa9, 0xa8, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmadd213pd (%rax), %xmm10, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0x29, 0xa8, 0xdc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmadd213ps %xmm12, %xmm10, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x29, 0xa8, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmadd213ps (%rax), %xmm10, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0xa9, 0xb8, 0xdc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmadd231pd %xmm12, %xmm10, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0xa9, 0xb8, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmadd231pd (%rax), %xmm10, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0x29, 0xb8, 0xdc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmadd231ps %xmm12, %xmm10, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x29, 0xb8, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmadd231ps (%rax), %xmm10, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0xa9, 0x96, 0xdc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmaddsub132pd %xmm12, %xmm10, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0xa9, 0x96, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmaddsub132pd (%rax), %xmm10, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0x29, 0x96, 0xdc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmaddsub132ps %xmm12, %xmm10, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x29, 0x96, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmaddsub132ps (%rax), %xmm10, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0xa9, 0xa6, 0xdc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmaddsub213pd %xmm12, %xmm10, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0xa9, 0xa6, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmaddsub213pd (%rax), %xmm10, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0x29, 0xa6, 0xdc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmaddsub213ps %xmm12, %xmm10, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x29, 0xa6, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmaddsub213ps (%rax), %xmm10, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0xa9, 0xb6, 0xdc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmaddsub231pd %xmm12, %xmm10, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0xa9, 0xb6, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmaddsub231pd (%rax), %xmm10, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0x29, 0xb6, 0xdc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmaddsub231ps %xmm12, %xmm10, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x29, 0xb6, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmaddsub231ps (%rax), %xmm10, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0xa9, 0x97, 0xdc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsubadd132pd %xmm12, %xmm10, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0xa9, 0x97, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsubadd132pd (%rax), %xmm10, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0x29, 0x97, 0xdc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsubadd132ps %xmm12, %xmm10, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x29, 0x97, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsubadd132ps (%rax), %xmm10, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0xa9, 0xa7, 0xdc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsubadd213pd %xmm12, %xmm10, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0xa9, 0xa7, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsubadd213pd (%rax), %xmm10, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0x29, 0xa7, 0xdc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsubadd213ps %xmm12, %xmm10, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x29, 0xa7, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsubadd213ps (%rax), %xmm10, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0xa9, 0xb7, 0xdc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsubadd231pd %xmm12, %xmm10, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0xa9, 0xb7, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsubadd231pd (%rax), %xmm10, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0x29, 0xb7, 0xdc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsubadd231ps %xmm12, %xmm10, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x29, 0xb7, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsubadd231ps (%rax), %xmm10, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0xa9, 0x9a, 0xdc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsub132pd %xmm12, %xmm10, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0xa9, 0x9a, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsub132pd (%rax), %xmm10, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0x29, 0x9a, 0xdc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsub132ps %xmm12, %xmm10, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x29, 0x9a, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsub132ps (%rax), %xmm10, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0xa9, 0xaa, 0xdc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsub213pd %xmm12, %xmm10, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0xa9, 0xaa, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsub213pd (%rax), %xmm10, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0x29, 0xaa, 0xdc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsub213ps %xmm12, %xmm10, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x29, 0xaa, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsub213ps (%rax), %xmm10, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0xa9, 0xba, 0xdc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsub231pd %xmm12, %xmm10, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0xa9, 0xba, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsub231pd (%rax), %xmm10, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0x29, 0xba, 0xdc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsub231ps %xmm12, %xmm10, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x29, 0xba, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsub231ps (%rax), %xmm10, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0xa9, 0x9c, 0xdc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmadd132pd %xmm12, %xmm10, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0xa9, 0x9c, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmadd132pd (%rax), %xmm10, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0x29, 0x9c, 0xdc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmadd132ps %xmm12, %xmm10, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x29, 0x9c, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmadd132ps (%rax), %xmm10, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0xa9, 0xac, 0xdc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmadd213pd %xmm12, %xmm10, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0xa9, 0xac, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmadd213pd (%rax), %xmm10, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0x29, 0xac, 0xdc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmadd213ps %xmm12, %xmm10, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x29, 0xac, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmadd213ps (%rax), %xmm10, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0xa9, 0xbc, 0xdc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmadd231pd %xmm12, %xmm10, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0xa9, 0xbc, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmadd231pd (%rax), %xmm10, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0x29, 0xbc, 0xdc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmadd231ps %xmm12, %xmm10, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x29, 0xbc, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmadd231ps (%rax), %xmm10, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0xa9, 0x9e, 0xdc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmsub132pd %xmm12, %xmm10, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0xa9, 0x9e, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmsub132pd (%rax), %xmm10, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0x29, 0x9e, 0xdc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmsub132ps %xmm12, %xmm10, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x29, 0x9e, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmsub132ps (%rax), %xmm10, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0xa9, 0xae, 0xdc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmsub213pd %xmm12, %xmm10, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0xa9, 0xae, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmsub213pd (%rax), %xmm10, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0x29, 0xae, 0xdc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmsub213ps %xmm12, %xmm10, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x29, 0xae, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmsub213ps (%rax), %xmm10, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0xa9, 0xbe, 0xdc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmsub231pd %xmm12, %xmm10, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0xa9, 0xbe, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmsub231pd (%rax), %xmm10, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0x29, 0xbe, 0xdc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmsub231ps %xmm12, %xmm10, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x29, 0xbe, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmsub231ps (%rax), %xmm10, %xmm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0xad, 0x98, 0xdc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmadd132pd %ymm12, %ymm10, %ymm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0xad, 0x98, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmadd132pd (%rax), %ymm10, %ymm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0x2d, 0x98, 0xdc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmadd132ps %ymm12, %ymm10, %ymm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x2d, 0x98, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmadd132ps (%rax), %ymm10, %ymm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0xad, 0xa8, 0xdc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmadd213pd %ymm12, %ymm10, %ymm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0xad, 0xa8, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmadd213pd (%rax), %ymm10, %ymm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0x2d, 0xa8, 0xdc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmadd213ps %ymm12, %ymm10, %ymm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x2d, 0xa8, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmadd213ps (%rax), %ymm10, %ymm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0xad, 0xb8, 0xdc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmadd231pd %ymm12, %ymm10, %ymm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0xad, 0xb8, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmadd231pd (%rax), %ymm10, %ymm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0x2d, 0xb8, 0xdc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmadd231ps %ymm12, %ymm10, %ymm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x2d, 0xb8, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmadd231ps (%rax), %ymm10, %ymm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0xad, 0x96, 0xdc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmaddsub132pd %ymm12, %ymm10, %ymm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0xad, 0x96, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmaddsub132pd (%rax), %ymm10, %ymm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0x2d, 0x96, 0xdc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmaddsub132ps %ymm12, %ymm10, %ymm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x2d, 0x96, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmaddsub132ps (%rax), %ymm10, %ymm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0xad, 0xa6, 0xdc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmaddsub213pd %ymm12, %ymm10, %ymm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0xad, 0xa6, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmaddsub213pd (%rax), %ymm10, %ymm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0x2d, 0xa6, 0xdc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmaddsub213ps %ymm12, %ymm10, %ymm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x2d, 0xa6, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmaddsub213ps (%rax), %ymm10, %ymm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0xad, 0xb6, 0xdc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmaddsub231pd %ymm12, %ymm10, %ymm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0xad, 0xb6, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmaddsub231pd (%rax), %ymm10, %ymm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0x2d, 0xb6, 0xdc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmaddsub231ps %ymm12, %ymm10, %ymm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x2d, 0xb6, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmaddsub231ps (%rax), %ymm10, %ymm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0xad, 0x97, 0xdc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsubadd132pd %ymm12, %ymm10, %ymm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0xad, 0x97, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsubadd132pd (%rax), %ymm10, %ymm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0x2d, 0x97, 0xdc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsubadd132ps %ymm12, %ymm10, %ymm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x2d, 0x97, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsubadd132ps (%rax), %ymm10, %ymm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0xad, 0xa7, 0xdc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsubadd213pd %ymm12, %ymm10, %ymm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0xad, 0xa7, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsubadd213pd (%rax), %ymm10, %ymm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0x2d, 0xa7, 0xdc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsubadd213ps %ymm12, %ymm10, %ymm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x2d, 0xa7, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsubadd213ps (%rax), %ymm10, %ymm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0xad, 0xb7, 0xdc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsubadd231pd %ymm12, %ymm10, %ymm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0xad, 0xb7, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsubadd231pd (%rax), %ymm10, %ymm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0x2d, 0xb7, 0xdc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsubadd231ps %ymm12, %ymm10, %ymm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x2d, 0xb7, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsubadd231ps (%rax), %ymm10, %ymm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0xad, 0x9a, 0xdc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsub132pd %ymm12, %ymm10, %ymm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0xad, 0x9a, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsub132pd (%rax), %ymm10, %ymm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0x2d, 0x9a, 0xdc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsub132ps %ymm12, %ymm10, %ymm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x2d, 0x9a, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsub132ps (%rax), %ymm10, %ymm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0xad, 0xaa, 0xdc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsub213pd %ymm12, %ymm10, %ymm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0xad, 0xaa, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsub213pd (%rax), %ymm10, %ymm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0x2d, 0xaa, 0xdc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsub213ps %ymm12, %ymm10, %ymm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x2d, 0xaa, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsub213ps (%rax), %ymm10, %ymm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0xad, 0xba, 0xdc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsub231pd %ymm12, %ymm10, %ymm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0xad, 0xba, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsub231pd (%rax), %ymm10, %ymm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0x2d, 0xba, 0xdc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsub231ps %ymm12, %ymm10, %ymm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x2d, 0xba, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsub231ps (%rax), %ymm10, %ymm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0xad, 0x9c, 0xdc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmadd132pd %ymm12, %ymm10, %ymm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0xad, 0x9c, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmadd132pd (%rax), %ymm10, %ymm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0x2d, 0x9c, 0xdc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmadd132ps %ymm12, %ymm10, %ymm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x2d, 0x9c, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmadd132ps (%rax), %ymm10, %ymm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0xad, 0xac, 0xdc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmadd213pd %ymm12, %ymm10, %ymm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0xad, 0xac, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmadd213pd (%rax), %ymm10, %ymm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0x2d, 0xac, 0xdc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmadd213ps %ymm12, %ymm10, %ymm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x2d, 0xac, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmadd213ps (%rax), %ymm10, %ymm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0xad, 0xbc, 0xdc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmadd231pd %ymm12, %ymm10, %ymm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0xad, 0xbc, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmadd231pd (%rax), %ymm10, %ymm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0x2d, 0xbc, 0xdc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmadd231ps %ymm12, %ymm10, %ymm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x2d, 0xbc, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmadd231ps (%rax), %ymm10, %ymm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0xad, 0x9e, 0xdc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmsub132pd %ymm12, %ymm10, %ymm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0xad, 0x9e, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmsub132pd (%rax), %ymm10, %ymm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0x2d, 0x9e, 0xdc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmsub132ps %ymm12, %ymm10, %ymm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x2d, 0x9e, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmsub132ps (%rax), %ymm10, %ymm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0xad, 0xae, 0xdc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmsub213pd %ymm12, %ymm10, %ymm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0xad, 0xae, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmsub213pd (%rax), %ymm10, %ymm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0x2d, 0xae, 0xdc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmsub213ps %ymm12, %ymm10, %ymm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x2d, 0xae, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmsub213ps (%rax), %ymm10, %ymm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0xad, 0xbe, 0xdc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmsub231pd %ymm12, %ymm10, %ymm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0xad, 0xbe, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmsub231pd (%rax), %ymm10, %ymm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x42, 0x2d, 0xbe, 0xdc ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmsub231ps %ymm12, %ymm10, %ymm11"
+  -
+    input:
+      bytes: [ 0xc4, 0x62, 0x2d, 0xbe, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmsub231ps (%rax), %ymm10, %ymm11"
diff --git a/tests/MC/X86/x86_64-fma4-encoding.s.yaml b/tests/MC/X86/x86_64-fma4-encoding.s.yaml
new file mode 100644
index 000000000..84384b122
--- /dev/null
+++ b/tests/MC/X86/x86_64-fma4-encoding.s.yaml
@@ -0,0 +1,874 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0xf9, 0x6a, 0x01, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmaddss (%rcx), %xmm1, %xmm0, %xmm0"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x79, 0x6a, 0x01, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmaddss %xmm1, (%rcx), %xmm0, %xmm0"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0xf9, 0x6a, 0xc2, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmaddss %xmm2, %xmm1, %xmm0, %xmm0"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0xf9, 0x6b, 0x01, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmaddsd (%rcx), %xmm1, %xmm0, %xmm0"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x79, 0x6b, 0x01, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmaddsd %xmm1, (%rcx), %xmm0, %xmm0"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0xf9, 0x6b, 0xc2, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmaddsd %xmm2, %xmm1, %xmm0, %xmm0"
+  -
+    input:
+      bytes: [ 0xc4, 0xc3, 0xf9, 0x6b, 0xc2, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmaddsd %xmm10, %xmm1, %xmm0, %xmm0"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0xf9, 0x68, 0x01, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmaddps (%rcx), %xmm1, %xmm0, %xmm0"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x79, 0x68, 0x01, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmaddps %xmm1, (%rcx), %xmm0, %xmm0"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0xf9, 0x68, 0xc2, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmaddps %xmm2, %xmm1, %xmm0, %xmm0"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0xf9, 0x69, 0x01, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmaddpd (%rcx), %xmm1, %xmm0, %xmm0"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x79, 0x69, 0x01, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmaddpd %xmm1, (%rcx), %xmm0, %xmm0"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0xf9, 0x69, 0xc2, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmaddpd %xmm2, %xmm1, %xmm0, %xmm0"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0xfd, 0x68, 0x01, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmaddps (%rcx), %ymm1, %ymm0, %ymm0"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x7d, 0x68, 0x01, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmaddps %ymm1, (%rcx), %ymm0, %ymm0"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0xfd, 0x68, 0xc2, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmaddps %ymm2, %ymm1, %ymm0, %ymm0"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0xfd, 0x69, 0x01, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmaddpd (%rcx), %ymm1, %ymm0, %ymm0"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x7d, 0x69, 0x01, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmaddpd %ymm1, (%rcx), %ymm0, %ymm0"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0xfd, 0x69, 0xc2, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmaddpd %ymm2, %ymm1, %ymm0, %ymm0"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0xf9, 0x6e, 0x01, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsubss (%rcx), %xmm1, %xmm0, %xmm0"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x79, 0x6e, 0x01, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsubss %xmm1, (%rcx), %xmm0, %xmm0"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0xf9, 0x6e, 0xc2, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsubss %xmm2, %xmm1, %xmm0, %xmm0"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0xf9, 0x6f, 0x01, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsubsd (%rcx), %xmm1, %xmm0, %xmm0"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x79, 0x6f, 0x01, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsubsd %xmm1, (%rcx), %xmm0, %xmm0"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0xf9, 0x6f, 0xc2, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsubsd %xmm2, %xmm1, %xmm0, %xmm0"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0xf9, 0x6c, 0x01, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsubps (%rcx), %xmm1, %xmm0, %xmm0"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x79, 0x6c, 0x01, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsubps %xmm1, (%rcx), %xmm0, %xmm0"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0xf9, 0x6c, 0xc2, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsubps %xmm2, %xmm1, %xmm0, %xmm0"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0xf9, 0x6d, 0x01, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsubpd (%rcx), %xmm1, %xmm0, %xmm0"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x79, 0x6d, 0x01, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsubpd %xmm1, (%rcx), %xmm0, %xmm0"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0xf9, 0x6d, 0xc2, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsubpd %xmm2, %xmm1, %xmm0, %xmm0"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0xfd, 0x6c, 0x01, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsubps (%rcx), %ymm1, %ymm0, %ymm0"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x7d, 0x6c, 0x01, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsubps %ymm1, (%rcx), %ymm0, %ymm0"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0xfd, 0x6c, 0xc2, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsubps %ymm2, %ymm1, %ymm0, %ymm0"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0xfd, 0x6d, 0x01, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsubpd (%rcx), %ymm1, %ymm0, %ymm0"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x7d, 0x6d, 0x01, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsubpd %ymm1, (%rcx), %ymm0, %ymm0"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0xfd, 0x6d, 0xc2, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsubpd %ymm2, %ymm1, %ymm0, %ymm0"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0xf9, 0x7a, 0x01, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmaddss (%rcx), %xmm1, %xmm0, %xmm0"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x79, 0x7a, 0x01, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmaddss %xmm1, (%rcx), %xmm0, %xmm0"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0xf9, 0x7a, 0xc2, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmaddss %xmm2, %xmm1, %xmm0, %xmm0"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0xf9, 0x7b, 0x01, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmaddsd (%rcx), %xmm1, %xmm0, %xmm0"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x79, 0x7b, 0x01, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmaddsd %xmm1, (%rcx), %xmm0, %xmm0"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0xf9, 0x7b, 0xc2, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmaddsd %xmm2, %xmm1, %xmm0, %xmm0"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0xf9, 0x78, 0x01, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmaddps (%rcx), %xmm1, %xmm0, %xmm0"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x79, 0x78, 0x01, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmaddps %xmm1, (%rcx), %xmm0, %xmm0"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0xf9, 0x78, 0xc2, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmaddps %xmm2, %xmm1, %xmm0, %xmm0"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0xf9, 0x79, 0x01, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmaddpd (%rcx), %xmm1, %xmm0, %xmm0"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x79, 0x79, 0x01, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmaddpd %xmm1, (%rcx), %xmm0, %xmm0"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0xf9, 0x79, 0xc2, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmaddpd %xmm2, %xmm1, %xmm0, %xmm0"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0xfd, 0x78, 0x01, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmaddps (%rcx), %ymm1, %ymm0, %ymm0"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x7d, 0x78, 0x01, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmaddps %ymm1, (%rcx), %ymm0, %ymm0"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0xfd, 0x78, 0xc2, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmaddps %ymm2, %ymm1, %ymm0, %ymm0"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0xfd, 0x79, 0x01, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmaddpd (%rcx), %ymm1, %ymm0, %ymm0"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x7d, 0x79, 0x01, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmaddpd %ymm1, (%rcx), %ymm0, %ymm0"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0xfd, 0x79, 0xc2, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmaddpd %ymm2, %ymm1, %ymm0, %ymm0"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0xf9, 0x7e, 0x01, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmsubss (%rcx), %xmm1, %xmm0, %xmm0"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x79, 0x7e, 0x01, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmsubss %xmm1, (%rcx), %xmm0, %xmm0"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0xf9, 0x7e, 0xc2, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmsubss %xmm2, %xmm1, %xmm0, %xmm0"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0xf9, 0x7f, 0x01, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmsubsd (%rcx), %xmm1, %xmm0, %xmm0"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x79, 0x7f, 0x01, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmsubsd %xmm1, (%rcx), %xmm0, %xmm0"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0xf9, 0x7f, 0xc2, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmsubsd %xmm2, %xmm1, %xmm0, %xmm0"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0xf9, 0x7c, 0x01, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmsubps (%rcx), %xmm1, %xmm0, %xmm0"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x79, 0x7c, 0x01, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmsubps %xmm1, (%rcx), %xmm0, %xmm0"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0xf9, 0x7c, 0xc2, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmsubps %xmm2, %xmm1, %xmm0, %xmm0"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0xf9, 0x7d, 0x01, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmsubpd (%rcx), %xmm1, %xmm0, %xmm0"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x79, 0x7d, 0x01, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmsubpd %xmm1, (%rcx), %xmm0, %xmm0"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0xf9, 0x7d, 0xc2, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmsubpd %xmm2, %xmm1, %xmm0, %xmm0"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0xfd, 0x7c, 0x01, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmsubps (%rcx), %ymm1, %ymm0, %ymm0"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x7d, 0x7c, 0x01, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmsubps %ymm1, (%rcx), %ymm0, %ymm0"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0xfd, 0x7c, 0xc2, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmsubps %ymm2, %ymm1, %ymm0, %ymm0"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0xfd, 0x7d, 0x01, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmsubpd (%rcx), %ymm1, %ymm0, %ymm0"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x7d, 0x7d, 0x01, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmsubpd %ymm1, (%rcx), %ymm0, %ymm0"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0xfd, 0x7d, 0xc2, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfnmsubpd %ymm2, %ymm1, %ymm0, %ymm0"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0xf9, 0x5c, 0x01, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmaddsubps (%rcx), %xmm1, %xmm0, %xmm0"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x79, 0x5c, 0x01, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmaddsubps %xmm1, (%rcx), %xmm0, %xmm0"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0xf9, 0x5c, 0xc2, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmaddsubps %xmm2, %xmm1, %xmm0, %xmm0"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0xf9, 0x5d, 0x01, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmaddsubpd (%rcx), %xmm1, %xmm0, %xmm0"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x79, 0x5d, 0x01, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmaddsubpd %xmm1, (%rcx), %xmm0, %xmm0"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0xf9, 0x5d, 0xc2, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmaddsubpd %xmm2, %xmm1, %xmm0, %xmm0"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0xfd, 0x5c, 0x01, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmaddsubps (%rcx), %ymm1, %ymm0, %ymm0"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x7d, 0x5c, 0x01, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmaddsubps %ymm1, (%rcx), %ymm0, %ymm0"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0xfd, 0x5c, 0xc2, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmaddsubps %ymm2, %ymm1, %ymm0, %ymm0"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0xfd, 0x5d, 0x01, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmaddsubpd (%rcx), %ymm1, %ymm0, %ymm0"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x7d, 0x5d, 0x01, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmaddsubpd %ymm1, (%rcx), %ymm0, %ymm0"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0xfd, 0x5d, 0xc2, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmaddsubpd %ymm2, %ymm1, %ymm0, %ymm0"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0xf9, 0x5e, 0x01, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsubaddps (%rcx), %xmm1, %xmm0, %xmm0"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x79, 0x5e, 0x01, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsubaddps %xmm1, (%rcx), %xmm0, %xmm0"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0xf9, 0x5e, 0xc2, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsubaddps %xmm2, %xmm1, %xmm0, %xmm0"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0xf9, 0x5f, 0x01, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsubaddpd (%rcx), %xmm1, %xmm0, %xmm0"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x79, 0x5f, 0x01, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsubaddpd %xmm1, (%rcx), %xmm0, %xmm0"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0xf9, 0x5f, 0xc2, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsubaddpd %xmm2, %xmm1, %xmm0, %xmm0"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0xfd, 0x5e, 0x01, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsubaddps (%rcx), %ymm1, %ymm0, %ymm0"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x7d, 0x5e, 0x01, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsubaddps %ymm1, (%rcx), %ymm0, %ymm0"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0xfd, 0x5e, 0xc2, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsubaddps %ymm2, %ymm1, %ymm0, %ymm0"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0xfd, 0x5f, 0x01, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsubaddpd (%rcx), %ymm1, %ymm0, %ymm0"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x7d, 0x5f, 0x01, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsubaddpd %ymm1, (%rcx), %ymm0, %ymm0"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0xfd, 0x5f, 0xc2, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfmsubaddpd %ymm2, %ymm1, %ymm0, %ymm0"
diff --git a/tests/MC/X86/x86_64-imm-widths.s.yaml b/tests/MC/X86/x86_64-imm-widths.s.yaml
new file mode 100644
index 000000000..d88cee52c
--- /dev/null
+++ b/tests/MC/X86/x86_64-imm-widths.s.yaml
@@ -0,0 +1,235 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x04, 0x00 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "addb $0x00, %al"
+  -
+    input:
+      bytes: [ 0x04, 0x7f ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "addb $0x7F, %al"
+  -
+    input:
+      bytes: [ 0x04, 0x80 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "addb $0x80, %al"
+  -
+    input:
+      bytes: [ 0x04, 0xff ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "addb $0xFF, %al"
+  -
+    input:
+      bytes: [ 0x66, 0x83, 0xc0, 0x00 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "addw $0x0000, %ax"
+  -
+    input:
+      bytes: [ 0x66, 0x83, 0xc0, 0x7f ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "addw $0x007F, %ax"
+  -
+    input:
+      bytes: [ 0x66, 0x83, 0xc0, 0x80 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "addw $-0x80, %ax"
+  -
+    input:
+      bytes: [ 0x66, 0x83, 0xc0, 0xff ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "addw $-1, %ax"
+  -
+    input:
+      bytes: [ 0x83, 0xc0, 0x00 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "addl $0x00000000, %eax"
+  -
+    input:
+      bytes: [ 0x83, 0xc0, 0x7f ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "addl $0x0000007F, %eax"
+  -
+    input:
+      bytes: [ 0x05, 0x80, 0xff, 0x00, 0x00 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "addl $0xFF80, %eax"
+  -
+    input:
+      bytes: [ 0x05, 0xff, 0xff, 0x00, 0x00 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "addl $0xFFFF, %eax"
+  -
+    input:
+      bytes: [ 0x83, 0xc0, 0x80 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "addl $-0x80, %eax"
+  -
+    input:
+      bytes: [ 0x83, 0xc0, 0xff ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "addl $-1, %eax"
+  -
+    input:
+      bytes: [ 0x48, 0x83, 0xc0, 0x00 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "addq $0x0000000000000000, %rax"
+  -
+    input:
+      bytes: [ 0x48, 0x83, 0xc0, 0x7f ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "addq $0x000000000000007F, %rax"
+  -
+    input:
+      bytes: [ 0x48, 0x83, 0xc0, 0x80 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "addq $0xFFFFFFFFFFFFFF80, %rax"
+  -
+    input:
+      bytes: [ 0x48, 0x83, 0xc0, 0xff ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "addq $0xFFFFFFFFFFFFFFFF, %rax"
+  -
+    input:
+      bytes: [ 0x48, 0x83, 0xc0, 0x00 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "addq $0x0000000000000000, %rax"
+  -
+    input:
+      bytes: [ 0x48, 0x05, 0x80, 0xff, 0x00, 0x00 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "addq $0xFF80, %rax"
+  -
+    input:
+      bytes: [ 0x48, 0x05, 0xff, 0xff, 0x00, 0x00 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "addq $0xFFFF, %rax"
+  -
+    input:
+      bytes: [ 0x48, 0xb8, 0x80, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "movabsq $0xFFFFFF80, %rax"
+  -
+    input:
+      bytes: [ 0x48, 0xb8, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "movabsq $0xFFFFFFFF, %rax"
+  -
+    input:
+      bytes: [ 0x48, 0x05, 0xff, 0xff, 0xff, 0x7f ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "addq $0x000000007FFFFFFF, %rax"
+  -
+    input:
+      bytes: [ 0x48, 0x05, 0x00, 0x00, 0x00, 0x80 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "addq $0xFFFFFFFF80000000, %rax"
+  -
+    input:
+      bytes: [ 0x48, 0x05, 0x00, 0xff, 0xff, 0xff ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "addq $0xFFFFFFFFFFFFFF00, %rax"
diff --git a/tests/MC/X86/x86_64-rand-encoding.s.yaml b/tests/MC/X86/x86_64-rand-encoding.s.yaml
new file mode 100644
index 000000000..30339e469
--- /dev/null
+++ b/tests/MC/X86/x86_64-rand-encoding.s.yaml
@@ -0,0 +1,109 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x66, 0x0f, 0xc7, 0xf0 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rdrandw %ax"
+  -
+    input:
+      bytes: [ 0x0f, 0xc7, 0xf0 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rdrandl %eax"
+  -
+    input:
+      bytes: [ 0x48, 0x0f, 0xc7, 0xf0 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rdrandq %rax"
+  -
+    input:
+      bytes: [ 0x66, 0x41, 0x0f, 0xc7, 0xf3 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rdrandw %r11w"
+  -
+    input:
+      bytes: [ 0x41, 0x0f, 0xc7, 0xf3 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rdrandl %r11d"
+  -
+    input:
+      bytes: [ 0x49, 0x0f, 0xc7, 0xf3 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rdrandq %r11"
+  -
+    input:
+      bytes: [ 0x66, 0x0f, 0xc7, 0xf8 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rdseedw %ax"
+  -
+    input:
+      bytes: [ 0x0f, 0xc7, 0xf8 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rdseedl %eax"
+  -
+    input:
+      bytes: [ 0x48, 0x0f, 0xc7, 0xf8 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rdseedq %rax"
+  -
+    input:
+      bytes: [ 0x66, 0x41, 0x0f, 0xc7, 0xfb ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rdseedw %r11w"
+  -
+    input:
+      bytes: [ 0x41, 0x0f, 0xc7, 0xfb ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rdseedl %r11d"
+  -
+    input:
+      bytes: [ 0x49, 0x0f, 0xc7, 0xfb ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "rdseedq %r11"
diff --git a/tests/MC/X86/x86_64-rtm-encoding.s.yaml b/tests/MC/X86/x86_64-rtm-encoding.s.yaml
new file mode 100644
index 000000000..0efe2adbe
--- /dev/null
+++ b/tests/MC/X86/x86_64-rtm-encoding.s.yaml
@@ -0,0 +1,28 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x0f, 0x01, 0xd5 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xend"
+  -
+    input:
+      bytes: [ 0x0f, 0x01, 0xd6 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xtest"
+  -
+    input:
+      bytes: [ 0xc6, 0xf8, 0x0d ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "xabort $13"
diff --git a/tests/MC/X86/x86_64-tbm-encoding.s.yaml b/tests/MC/X86/x86_64-tbm-encoding.s.yaml
new file mode 100644
index 000000000..6110a9a5d
--- /dev/null
+++ b/tests/MC/X86/x86_64-tbm-encoding.s.yaml
@@ -0,0 +1,352 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x8f, 0xea, 0x78, 0x10, 0xc7, 0xfe, 0x0a, 0x00, 0x00 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "bextrl $2814, %edi, %eax"
+  -
+    input:
+      bytes: [ 0x8f, 0xea, 0x78, 0x10, 0x07, 0xfe, 0x0a, 0x00, 0x00 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "bextrl $2814, (%rdi), %eax"
+  -
+    input:
+      bytes: [ 0x8f, 0xea, 0xf8, 0x10, 0xc7, 0xfe, 0x0a, 0x00, 0x00 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "bextrq $2814, %rdi, %rax"
+  -
+    input:
+      bytes: [ 0x8f, 0xea, 0xf8, 0x10, 0x07, 0xfe, 0x0a, 0x00, 0x00 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "bextrq $2814, (%rdi), %rax"
+  -
+    input:
+      bytes: [ 0x8f, 0xe9, 0x78, 0x01, 0xcf ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "blcfilll %edi, %eax"
+  -
+    input:
+      bytes: [ 0x8f, 0xe9, 0x78, 0x01, 0x0f ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "blcfilll (%rdi), %eax"
+  -
+    input:
+      bytes: [ 0x8f, 0xe9, 0xf8, 0x01, 0xcf ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "blcfillq %rdi, %rax"
+  -
+    input:
+      bytes: [ 0x8f, 0xe9, 0xf8, 0x01, 0x0f ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "blcfillq (%rdi), %rax"
+  -
+    input:
+      bytes: [ 0x8f, 0xe9, 0x78, 0x02, 0xf7 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "blcil %edi, %eax"
+  -
+    input:
+      bytes: [ 0x8f, 0xe9, 0x78, 0x02, 0x37 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "blcil (%rdi), %eax"
+  -
+    input:
+      bytes: [ 0x8f, 0xe9, 0xf8, 0x02, 0xf7 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "blciq %rdi, %rax"
+  -
+    input:
+      bytes: [ 0x8f, 0xe9, 0xf8, 0x02, 0x37 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "blciq (%rdi), %rax"
+  -
+    input:
+      bytes: [ 0x8f, 0xe9, 0x78, 0x01, 0xef ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "blcicl %edi, %eax"
+  -
+    input:
+      bytes: [ 0x8f, 0xe9, 0x78, 0x01, 0x2f ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "blcicl (%rdi), %eax"
+  -
+    input:
+      bytes: [ 0x8f, 0xe9, 0xf8, 0x01, 0xef ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "blcicq %rdi, %rax"
+  -
+    input:
+      bytes: [ 0x8f, 0xe9, 0xf8, 0x01, 0x2f ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "blcicq (%rdi), %rax"
+  -
+    input:
+      bytes: [ 0x8f, 0xe9, 0x78, 0x02, 0xcf ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "blcmskl %edi, %eax"
+  -
+    input:
+      bytes: [ 0x8f, 0xe9, 0x78, 0x02, 0x0f ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "blcmskl (%rdi), %eax"
+  -
+    input:
+      bytes: [ 0x8f, 0xe9, 0xf8, 0x02, 0xcf ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "blcmskq %rdi, %rax"
+  -
+    input:
+      bytes: [ 0x8f, 0xe9, 0xf8, 0x02, 0x0f ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "blcmskq (%rdi), %rax"
+  -
+    input:
+      bytes: [ 0x8f, 0xe9, 0x78, 0x01, 0xdf ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "blcsl %edi, %eax"
+  -
+    input:
+      bytes: [ 0x8f, 0xe9, 0x78, 0x01, 0x1f ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "blcsl (%rdi), %eax"
+  -
+    input:
+      bytes: [ 0x8f, 0xe9, 0xf8, 0x01, 0xdf ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "blcsq %rdi, %rax"
+  -
+    input:
+      bytes: [ 0x8f, 0xe9, 0xf8, 0x01, 0x1f ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "blcsq (%rdi), %rax"
+  -
+    input:
+      bytes: [ 0x8f, 0xe9, 0x78, 0x01, 0xd7 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "blsfilll %edi, %eax"
+  -
+    input:
+      bytes: [ 0x8f, 0xe9, 0x78, 0x01, 0x17 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "blsfilll (%rdi), %eax"
+  -
+    input:
+      bytes: [ 0x8f, 0xe9, 0xf8, 0x01, 0xd7 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "blsfillq %rdi, %rax"
+  -
+    input:
+      bytes: [ 0x8f, 0xe9, 0xf8, 0x01, 0x17 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "blsfillq (%rdi), %rax"
+  -
+    input:
+      bytes: [ 0x8f, 0xe9, 0x78, 0x01, 0xf7 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "blsicl %edi, %eax"
+  -
+    input:
+      bytes: [ 0x8f, 0xe9, 0x78, 0x01, 0x37 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "blsicl (%rdi), %eax"
+  -
+    input:
+      bytes: [ 0x8f, 0xe9, 0xf8, 0x01, 0xf7 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "blsicq %rdi, %rax"
+  -
+    input:
+      bytes: [ 0x8f, 0xe9, 0x78, 0x01, 0xff ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "t1mskcl %edi, %eax"
+  -
+    input:
+      bytes: [ 0x8f, 0xe9, 0x78, 0x01, 0x3f ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "t1mskcl (%rdi), %eax"
+  -
+    input:
+      bytes: [ 0x8f, 0xe9, 0xf8, 0x01, 0xff ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "t1mskcq %rdi, %rax"
+  -
+    input:
+      bytes: [ 0x8f, 0xe9, 0xf8, 0x01, 0x3f ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "t1mskcq (%rdi), %rax"
+  -
+    input:
+      bytes: [ 0x8f, 0xe9, 0x78, 0x01, 0xe7 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "tzmskl %edi, %eax"
+  -
+    input:
+      bytes: [ 0x8f, 0xe9, 0x78, 0x01, 0x27 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "tzmskl (%rdi), %eax"
+  -
+    input:
+      bytes: [ 0x8f, 0xe9, 0xf8, 0x01, 0xe7 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "tzmskq %rdi, %rax"
+  -
+    input:
+      bytes: [ 0x8f, 0xe9, 0xf8, 0x01, 0x27 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "tzmskq (%rdi), %rax"
diff --git a/tests/MC/X86/x86_64-xop-encoding.s.yaml b/tests/MC/X86/x86_64-xop-encoding.s.yaml
new file mode 100644
index 000000000..d1400f937
--- /dev/null
+++ b/tests/MC/X86/x86_64-xop-encoding.s.yaml
@@ -0,0 +1,1360 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x8f, 0xe9, 0x78, 0xe2, 0x0c, 0x01 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vphsubwd (%rcx, %rax), %xmm1"
+  -
+    input:
+      bytes: [ 0x8f, 0xe9, 0x78, 0xe2, 0xc8 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vphsubwd %xmm0, %xmm1"
+  -
+    input:
+      bytes: [ 0x8f, 0xe9, 0x78, 0xe3, 0x0c, 0x01 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vphsubdq (%rcx, %rax), %xmm1"
+  -
+    input:
+      bytes: [ 0x8f, 0xe9, 0x78, 0xe3, 0xc8 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vphsubdq %xmm0, %xmm1"
+  -
+    input:
+      bytes: [ 0x8f, 0xe9, 0x78, 0xe1, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vphsubbw (%rax), %xmm1"
+  -
+    input:
+      bytes: [ 0x8f, 0xe9, 0x78, 0xe1, 0xca ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vphsubbw %xmm2, %xmm1"
+  -
+    input:
+      bytes: [ 0x8f, 0xe9, 0x78, 0xc7, 0x21 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vphaddwq (%rcx), %xmm4"
+  -
+    input:
+      bytes: [ 0x8f, 0xe9, 0x78, 0xc7, 0xd6 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vphaddwq %xmm6, %xmm2"
+  -
+    input:
+      bytes: [ 0x8f, 0xe9, 0x78, 0xc6, 0x3c, 0x02 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vphaddwd (%rdx, %rax), %xmm7"
+  -
+    input:
+      bytes: [ 0x8f, 0xe9, 0x78, 0xc6, 0xe3 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vphaddwd %xmm3, %xmm4"
+  -
+    input:
+      bytes: [ 0x8f, 0xe9, 0x78, 0xd7, 0x34, 0x01 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vphadduwq (%rcx, %rax), %xmm6"
+  -
+    input:
+      bytes: [ 0x8f, 0xe9, 0x78, 0xd7, 0xc7 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vphadduwq %xmm7, %xmm0"
+  -
+    input:
+      bytes: [ 0x8f, 0xe9, 0x78, 0xd6, 0x28 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vphadduwd (%rax), %xmm5"
+  -
+    input:
+      bytes: [ 0x8f, 0xe9, 0x78, 0xd6, 0xca ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vphadduwd %xmm2, %xmm1"
+  -
+    input:
+      bytes: [ 0x8f, 0xe9, 0x78, 0xdb, 0x64, 0x01, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vphaddudq 8(%rcx, %rax), %xmm4"
+  -
+    input:
+      bytes: [ 0x8f, 0xe9, 0x78, 0xdb, 0xd6 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vphaddudq %xmm6, %xmm2"
+  -
+    input:
+      bytes: [ 0x8f, 0xe9, 0x78, 0xd1, 0x19 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vphaddubw (%rcx), %xmm3"
+  -
+    input:
+      bytes: [ 0x8f, 0xe9, 0x78, 0xd1, 0xc5 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vphaddubw %xmm5, %xmm0"
+  -
+    input:
+      bytes: [ 0x8f, 0xe9, 0x78, 0xd3, 0x21 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vphaddubq (%rcx), %xmm4"
+  -
+    input:
+      bytes: [ 0x8f, 0xe9, 0x78, 0xd3, 0xd2 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vphaddubq %xmm2, %xmm2"
+  -
+    input:
+      bytes: [ 0x8f, 0xe9, 0x78, 0xd2, 0x28 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vphaddubd (%rax), %xmm5"
+  -
+    input:
+      bytes: [ 0x8f, 0xe9, 0x78, 0xd2, 0xfd ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vphaddubd %xmm5, %xmm7"
+  -
+    input:
+      bytes: [ 0x8f, 0xe9, 0x78, 0xcb, 0x22 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vphadddq (%rdx), %xmm4"
+  -
+    input:
+      bytes: [ 0x8f, 0xe9, 0x78, 0xcb, 0xec ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vphadddq %xmm4, %xmm5"
+  -
+    input:
+      bytes: [ 0x8f, 0xe9, 0x78, 0xc1, 0x0c, 0x01 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vphaddbw (%rcx, %rax), %xmm1"
+  -
+    input:
+      bytes: [ 0x8f, 0xe9, 0x78, 0xc1, 0xf5 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vphaddbw %xmm5, %xmm6"
+  -
+    input:
+      bytes: [ 0x8f, 0xe9, 0x78, 0xc3, 0x0c, 0x01 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vphaddbq (%rcx, %rax), %xmm1"
+  -
+    input:
+      bytes: [ 0x8f, 0xe9, 0x78, 0xc3, 0xc2 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vphaddbq %xmm2, %xmm0"
+  -
+    input:
+      bytes: [ 0x8f, 0xe9, 0x78, 0xc2, 0x0c, 0x01 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vphaddbd (%rcx, %rax), %xmm1"
+  -
+    input:
+      bytes: [ 0x8f, 0xe9, 0x78, 0xc2, 0xd9 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vphaddbd %xmm1, %xmm3"
+  -
+    input:
+      bytes: [ 0x8f, 0xe9, 0x78, 0x82, 0x0c, 0x01 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfrczss (%rcx, %rax), %xmm1"
+  -
+    input:
+      bytes: [ 0x8f, 0xe9, 0x78, 0x82, 0xfd ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfrczss %xmm5, %xmm7"
+  -
+    input:
+      bytes: [ 0x8f, 0xe9, 0x78, 0x83, 0x0c, 0x01 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfrczsd (%rcx, %rax), %xmm1"
+  -
+    input:
+      bytes: [ 0x8f, 0xe9, 0x78, 0x83, 0xc7 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfrczsd %xmm7, %xmm0"
+  -
+    input:
+      bytes: [ 0x8f, 0xe9, 0x78, 0x80, 0x58, 0x04 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfrczps 4(%rax), %xmm3"
+  -
+    input:
+      bytes: [ 0x8f, 0xe9, 0x78, 0x80, 0xee ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfrczps %xmm6, %xmm5"
+  -
+    input:
+      bytes: [ 0x8f, 0xe9, 0x78, 0x80, 0x09 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfrczps (%rcx), %xmm1"
+  -
+    input:
+      bytes: [ 0x8f, 0xe9, 0x7c, 0x80, 0xe2 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfrczps %ymm2, %ymm4"
+  -
+    input:
+      bytes: [ 0x8f, 0xe9, 0x78, 0x81, 0x0c, 0x01 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfrczpd (%rcx, %rax), %xmm1"
+  -
+    input:
+      bytes: [ 0x8f, 0xe9, 0x78, 0x81, 0xc7 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfrczpd %xmm7, %xmm0"
+  -
+    input:
+      bytes: [ 0x8f, 0xe9, 0x7c, 0x81, 0x14, 0x01 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfrczpd (%rcx, %rax), %ymm2"
+  -
+    input:
+      bytes: [ 0x8f, 0xe9, 0x7c, 0x81, 0xdd ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vfrczpd %ymm5, %ymm3"
+  -
+    input:
+      bytes: [ 0x8f, 0xe9, 0x78, 0x95, 0xd1 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpshlw %xmm0, %xmm1, %xmm2"
+  -
+    input:
+      bytes: [ 0x8f, 0xe9, 0xf0, 0x95, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpshlw (%rax), %xmm1, %xmm2"
+  -
+    input:
+      bytes: [ 0x8f, 0xe9, 0x78, 0x95, 0x14, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpshlw %xmm0, (%rax, %rcx), %xmm2"
+  -
+    input:
+      bytes: [ 0x8f, 0xe9, 0x68, 0x97, 0xf4 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpshlq %xmm2, %xmm4, %xmm6"
+  -
+    input:
+      bytes: [ 0x8f, 0xe9, 0xe8, 0x97, 0x09 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpshlq (%rcx), %xmm2, %xmm1"
+  -
+    input:
+      bytes: [ 0x8f, 0xe9, 0x50, 0x97, 0x34, 0x0a ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpshlq %xmm5, (%rdx, %rcx), %xmm6"
+  -
+    input:
+      bytes: [ 0x8f, 0xe9, 0x40, 0x96, 0xdd ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpshld %xmm7, %xmm5, %xmm3"
+  -
+    input:
+      bytes: [ 0x8f, 0xe9, 0xe0, 0x96, 0x58, 0x04 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpshld 4(%rax), %xmm3, %xmm3"
+  -
+    input:
+      bytes: [ 0x8f, 0xe9, 0x70, 0x96, 0x2c, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpshld %xmm1, (%rax, %rcx), %xmm5"
+  -
+    input:
+      bytes: [ 0x8f, 0xe9, 0x70, 0x94, 0xda ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpshlb %xmm1, %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0x8f, 0xe9, 0xf8, 0x94, 0x39 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpshlb (%rcx), %xmm0, %xmm7"
+  -
+    input:
+      bytes: [ 0x8f, 0xe9, 0x68, 0x94, 0x1c, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpshlb %xmm2, (%rax, %rdx), %xmm3"
+  -
+    input:
+      bytes: [ 0x8f, 0xe9, 0x40, 0x99, 0xdd ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpshaw %xmm7, %xmm5, %xmm3"
+  -
+    input:
+      bytes: [ 0x8f, 0xe9, 0xe8, 0x99, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpshaw (%rax), %xmm2, %xmm1"
+  -
+    input:
+      bytes: [ 0x8f, 0xe9, 0x78, 0x99, 0x5c, 0x08, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpshaw %xmm0, 8(%rax, %rcx), %xmm3"
+  -
+    input:
+      bytes: [ 0x8f, 0xe9, 0x58, 0x9b, 0xe4 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpshaq %xmm4, %xmm4, %xmm4"
+  -
+    input:
+      bytes: [ 0x8f, 0xe9, 0xe8, 0x9b, 0x01 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpshaq (%rcx), %xmm2, %xmm0"
+  -
+    input:
+      bytes: [ 0x8f, 0xe9, 0x48, 0x9b, 0x2c, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpshaq %xmm6, (%rax, %rcx), %xmm5"
+  -
+    input:
+      bytes: [ 0x8f, 0xe9, 0x50, 0x9a, 0xc4 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpshad %xmm5, %xmm4, %xmm0"
+  -
+    input:
+      bytes: [ 0x8f, 0xe9, 0xe8, 0x9a, 0x28 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpshad (%rax), %xmm2, %xmm5"
+  -
+    input:
+      bytes: [ 0x8f, 0xe9, 0x68, 0x9a, 0x28 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpshad %xmm2, (%rax), %xmm5"
+  -
+    input:
+      bytes: [ 0x8f, 0xe9, 0x70, 0x98, 0xc1 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpshab %xmm1, %xmm1, %xmm0"
+  -
+    input:
+      bytes: [ 0x8f, 0xe9, 0xd8, 0x98, 0x01 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpshab (%rcx), %xmm4, %xmm0"
+  -
+    input:
+      bytes: [ 0x8f, 0xe9, 0x50, 0x98, 0x19 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpshab %xmm5, (%rcx), %xmm3"
+  -
+    input:
+      bytes: [ 0x8f, 0xe9, 0xe0, 0x91, 0x30 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vprotw (%rax), %xmm3, %xmm6"
+  -
+    input:
+      bytes: [ 0x8f, 0xe9, 0x50, 0x91, 0x0c, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vprotw %xmm5, (%rax, %rcx), %xmm1"
+  -
+    input:
+      bytes: [ 0x8f, 0xe9, 0x78, 0x91, 0xd1 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vprotw %xmm0, %xmm1, %xmm2"
+  -
+    input:
+      bytes: [ 0x8f, 0xe8, 0x78, 0xc1, 0x09, 0x2a ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vprotw $42, (%rcx), %xmm1"
+  -
+    input:
+      bytes: [ 0x8f, 0xe8, 0x78, 0xc1, 0x20, 0x29 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vprotw $41, (%rax), %xmm4"
+  -
+    input:
+      bytes: [ 0x8f, 0xe8, 0x78, 0xc1, 0xd9, 0x28 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vprotw $40, %xmm1, %xmm3"
+  -
+    input:
+      bytes: [ 0x8f, 0xe9, 0xf0, 0x93, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vprotq (%rax), %xmm1, %xmm2"
+  -
+    input:
+      bytes: [ 0x8f, 0xe9, 0xf0, 0x93, 0x14, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vprotq (%rax, %rcx), %xmm1, %xmm2"
+  -
+    input:
+      bytes: [ 0x8f, 0xe9, 0x78, 0x93, 0xd1 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vprotq %xmm0, %xmm1, %xmm2"
+  -
+    input:
+      bytes: [ 0x8f, 0xe8, 0x78, 0xc3, 0x10, 0x2a ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vprotq $42, (%rax), %xmm2"
+  -
+    input:
+      bytes: [ 0x8f, 0xe8, 0x78, 0xc3, 0x14, 0x08, 0x2a ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vprotq $42, (%rax, %rcx), %xmm2"
+  -
+    input:
+      bytes: [ 0x8f, 0xe8, 0x78, 0xc3, 0xd1, 0x2a ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vprotq $42, %xmm1, %xmm2"
+  -
+    input:
+      bytes: [ 0x8f, 0xe9, 0xf8, 0x92, 0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vprotd (%rax), %xmm0, %xmm3"
+  -
+    input:
+      bytes: [ 0x8f, 0xe9, 0x68, 0x92, 0x24, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vprotd %xmm2, (%rax, %rcx), %xmm4"
+  -
+    input:
+      bytes: [ 0x8f, 0xe9, 0x50, 0x92, 0xd3 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vprotd %xmm5, %xmm3, %xmm2"
+  -
+    input:
+      bytes: [ 0x8f, 0xe8, 0x78, 0xc2, 0x31, 0x2b ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vprotd $43, (%rcx), %xmm6"
+  -
+    input:
+      bytes: [ 0x8f, 0xe8, 0x78, 0xc2, 0x3c, 0x08, 0x2c ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vprotd $44, (%rax, %rcx), %xmm7"
+  -
+    input:
+      bytes: [ 0x8f, 0xe8, 0x78, 0xc2, 0xe4, 0x2d ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vprotd $45, %xmm4, %xmm4"
+  -
+    input:
+      bytes: [ 0x8f, 0xe9, 0xe8, 0x90, 0x29 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vprotb (%rcx), %xmm2, %xmm5"
+  -
+    input:
+      bytes: [ 0x8f, 0xe9, 0x50, 0x90, 0x24, 0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vprotb %xmm5, (%rax, %rcx), %xmm4"
+  -
+    input:
+      bytes: [ 0x8f, 0xe9, 0x58, 0x90, 0xd3 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vprotb %xmm4, %xmm3, %xmm2"
+  -
+    input:
+      bytes: [ 0x8f, 0xe8, 0x78, 0xc0, 0x18, 0x2e ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vprotb $46, (%rax), %xmm3"
+  -
+    input:
+      bytes: [ 0x8f, 0xe8, 0x78, 0xc0, 0x3c, 0x08, 0x2f ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vprotb $47, (%rax, %rcx), %xmm7"
+  -
+    input:
+      bytes: [ 0x8f, 0xe8, 0x78, 0xc0, 0xed, 0x30 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vprotb $48, %xmm5, %xmm5"
+  -
+    input:
+      bytes: [ 0x8f, 0xe8, 0x60, 0xb6, 0xe2, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmadcswd %xmm1, %xmm2, %xmm3, %xmm4"
+  -
+    input:
+      bytes: [ 0x8f, 0xe8, 0x60, 0xb6, 0x20, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmadcswd %xmm1, (%rax), %xmm3, %xmm4"
+  -
+    input:
+      bytes: [ 0x8f, 0xe8, 0x48, 0xa6, 0xe4, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmadcsswd %xmm1, %xmm4, %xmm6, %xmm4"
+  -
+    input:
+      bytes: [ 0x8f, 0xe8, 0x60, 0xa6, 0x24, 0x08, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmadcsswd %xmm1, (%rax, %rcx), %xmm3, %xmm4"
+  -
+    input:
+      bytes: [ 0x8f, 0xe8, 0x50, 0x95, 0xe2, 0x00 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmacsww %xmm0, %xmm2, %xmm5, %xmm4"
+  -
+    input:
+      bytes: [ 0x8f, 0xe8, 0x48, 0x95, 0x20, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmacsww %xmm1, (%rax), %xmm6, %xmm4"
+  -
+    input:
+      bytes: [ 0x8f, 0xe8, 0x48, 0x96, 0xfd, 0x40 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmacswd %xmm4, %xmm5, %xmm6, %xmm7"
+  -
+    input:
+      bytes: [ 0x8f, 0xe8, 0x70, 0x96, 0x10, 0x00 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmacswd %xmm0, (%rax), %xmm1, %xmm2"
+  -
+    input:
+      bytes: [ 0x8f, 0xe8, 0x68, 0x85, 0xcb, 0x40 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmacssww %xmm4, %xmm3, %xmm2, %xmm1"
+  -
+    input:
+      bytes: [ 0x8f, 0xe8, 0x40, 0x85, 0x39, 0x60 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmacssww %xmm6, (%rcx), %xmm7, %xmm7"
+  -
+    input:
+      bytes: [ 0x8f, 0xe8, 0x58, 0x86, 0xd2, 0x40 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmacsswd %xmm4, %xmm2, %xmm4, %xmm2"
+  -
+    input:
+      bytes: [ 0x8f, 0xe8, 0x70, 0x86, 0x44, 0x08, 0x08, 0x00 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmacsswd %xmm0, 8(%rax, %rcx), %xmm1, %xmm0"
+  -
+    input:
+      bytes: [ 0x8f, 0xe8, 0x68, 0x87, 0xe1, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmacssdql %xmm1, %xmm1, %xmm2, %xmm4"
+  -
+    input:
+      bytes: [ 0x8f, 0xe8, 0x48, 0x87, 0x29, 0x70 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmacssdql %xmm7, (%rcx), %xmm6, %xmm5"
+  -
+    input:
+      bytes: [ 0x8f, 0xe8, 0x78, 0x8f, 0xca, 0x30 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmacssdqh %xmm3, %xmm2, %xmm0, %xmm1"
+  -
+    input:
+      bytes: [ 0x8f, 0xe8, 0x68, 0x8f, 0x1c, 0x08, 0x70 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmacssdqh %xmm7, (%rax, %rcx), %xmm2, %xmm3"
+  -
+    input:
+      bytes: [ 0x8f, 0xe8, 0x60, 0x8e, 0xea, 0x20 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmacssdd %xmm2, %xmm2, %xmm3, %xmm5"
+  -
+    input:
+      bytes: [ 0x8f, 0xe8, 0x70, 0x8e, 0x10, 0x40 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmacssdd %xmm4, (%rax), %xmm1, %xmm2"
+  -
+    input:
+      bytes: [ 0x8f, 0xe8, 0x48, 0x97, 0xf8, 0x30 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmacsdql %xmm3, %xmm0, %xmm6, %xmm7"
+  -
+    input:
+      bytes: [ 0x8f, 0xe8, 0x60, 0x97, 0x69, 0x08, 0x50 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmacsdql %xmm5, 8(%rcx), %xmm3, %xmm5"
+  -
+    input:
+      bytes: [ 0x8f, 0xe8, 0x60, 0x9f, 0xd5, 0x70 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmacsdqh %xmm7, %xmm5, %xmm3, %xmm2"
+  -
+    input:
+      bytes: [ 0x8f, 0xe8, 0x68, 0x9f, 0x40, 0x04, 0x50 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmacsdqh %xmm5, 4(%rax), %xmm2, %xmm0"
+  -
+    input:
+      bytes: [ 0x8f, 0xe8, 0x58, 0x9e, 0xd6, 0x40 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmacsdd %xmm4, %xmm6, %xmm4, %xmm2"
+  -
+    input:
+      bytes: [ 0x8f, 0xe8, 0x58, 0x9e, 0x1c, 0x08, 0x40 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpmacsdd %xmm4, (%rax, %rcx), %xmm4, %xmm3"
+  -
+    input:
+      bytes: [ 0x8f, 0xe8, 0x60, 0xcd, 0xe2, 0x2a ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpcomw $42, %xmm2, %xmm3, %xmm4"
+  -
+    input:
+      bytes: [ 0x8f, 0xe8, 0x60, 0xcd, 0x20, 0x2a ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpcomw $42, (%rax), %xmm3, %xmm4"
+  -
+    input:
+      bytes: [ 0x8f, 0xe8, 0x60, 0xed, 0xe9, 0x2b ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpcomuw $43, %xmm1, %xmm3, %xmm5"
+  -
+    input:
+      bytes: [ 0x8f, 0xe8, 0x78, 0xed, 0x34, 0x08, 0x2c ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpcomuw $44, (%rax, %rcx), %xmm0, %xmm6"
+  -
+    input:
+      bytes: [ 0x8f, 0xe8, 0x60, 0xef, 0xfb, 0x2d ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpcomuq $45, %xmm3, %xmm3, %xmm7"
+  -
+    input:
+      bytes: [ 0x8f, 0xe8, 0x60, 0xef, 0x08, 0x2e ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpcomuq $46, (%rax), %xmm3, %xmm1"
+  -
+    input:
+      bytes: [ 0x8f, 0xe8, 0x70, 0xee, 0xd0, 0x2f ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpcomud $47, %xmm0, %xmm1, %xmm2"
+  -
+    input:
+      bytes: [ 0x8f, 0xe8, 0x48, 0xee, 0x58, 0x04, 0x30 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpcomud $48, 4(%rax), %xmm6, %xmm3"
+  -
+    input:
+      bytes: [ 0x8f, 0xe8, 0x58, 0xec, 0xeb, 0x31 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpcomub $49, %xmm3, %xmm4, %xmm5"
+  -
+    input:
+      bytes: [ 0x8f, 0xe8, 0x48, 0xec, 0x11, 0x32 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpcomub $50, (%rcx), %xmm6, %xmm2"
+  -
+    input:
+      bytes: [ 0x8f, 0xe8, 0x78, 0xcf, 0xeb, 0x33 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpcomq $51, %xmm3, %xmm0, %xmm5"
+  -
+    input:
+      bytes: [ 0x8f, 0xe8, 0x70, 0xcf, 0x38, 0x34 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpcomq $52, (%rax), %xmm1, %xmm7"
+  -
+    input:
+      bytes: [ 0x8f, 0xe8, 0x60, 0xce, 0xc3, 0x35 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpcomd $53, %xmm3, %xmm3, %xmm0"
+  -
+    input:
+      bytes: [ 0x8f, 0xe8, 0x68, 0xce, 0x11, 0x36 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpcomd $54, (%rcx), %xmm2, %xmm2"
+  -
+    input:
+      bytes: [ 0x8f, 0xe8, 0x58, 0xcc, 0xd6, 0x37 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpcomb $55, %xmm6, %xmm4, %xmm2"
+  -
+    input:
+      bytes: [ 0x8f, 0xe8, 0x60, 0xcc, 0x50, 0x08, 0x38 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpcomb $56, 8(%rax), %xmm3, %xmm2"
+  -
+    input:
+      bytes: [ 0x8f, 0xe8, 0x60, 0xa3, 0xe2, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpperm %xmm1, %xmm2, %xmm3, %xmm4"
+  -
+    input:
+      bytes: [ 0x8f, 0xe8, 0xe0, 0xa3, 0x20, 0x20 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpperm (%rax), %xmm2, %xmm3, %xmm4"
+  -
+    input:
+      bytes: [ 0x8f, 0xe8, 0x60, 0xa3, 0x20, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpperm %xmm1, (%rax), %xmm3, %xmm4"
+  -
+    input:
+      bytes: [ 0x8f, 0xe8, 0x60, 0xa2, 0xe2, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpcmov %xmm1, %xmm2, %xmm3, %xmm4"
+  -
+    input:
+      bytes: [ 0x8f, 0xe8, 0xe0, 0xa2, 0x20, 0x20 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpcmov (%rax), %xmm2, %xmm3, %xmm4"
+  -
+    input:
+      bytes: [ 0x8f, 0xe8, 0x60, 0xa2, 0x20, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpcmov %xmm1, (%rax), %xmm3, %xmm4"
+  -
+    input:
+      bytes: [ 0x8f, 0xe8, 0x64, 0xa2, 0xe2, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpcmov %ymm1, %ymm2, %ymm3, %ymm4"
+  -
+    input:
+      bytes: [ 0x8f, 0xe8, 0xe4, 0xa2, 0x20, 0x20 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpcmov (%rax), %ymm2, %ymm3, %ymm4"
+  -
+    input:
+      bytes: [ 0x8f, 0xe8, 0x64, 0xa2, 0x20, 0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpcmov %ymm1, (%rax), %ymm3, %ymm4"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x71, 0x49, 0xfa, 0x51 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpermil2pd $1, %xmm5, %xmm2, %xmm1, %xmm7"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0xe1, 0x49, 0x20, 0x32 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpermil2pd $2, (%rax), %xmm3, %xmm3, %xmm4"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0xdd, 0x49, 0x70, 0x08, 0x03 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpermil2pd $3, 8(%rax), %ymm0, %ymm4, %ymm6"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x71, 0x49, 0x04, 0x08, 0x30 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpermil2pd $0, %xmm3, (%rax, %rcx), %xmm1, %xmm0"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x65, 0x49, 0xe2, 0x11 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpermil2pd $1, %ymm1, %ymm2, %ymm3, %ymm4"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x65, 0x49, 0x20, 0x12 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpermil2pd $2, %ymm1, (%rax), %ymm3, %ymm4"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x69, 0x48, 0xcb, 0x40 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpermil2ps $0, %xmm4, %xmm3, %xmm2, %xmm1"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0xe1, 0x48, 0x40, 0x04, 0x21 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpermil2ps $1, 4(%rax), %xmm2, %xmm3, %xmm0"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0xd5, 0x48, 0x30, 0x12 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpermil2ps $2, (%rax), %ymm1, %ymm5, %ymm6"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x61, 0x48, 0x20, 0x13 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpermil2ps $3, %xmm1, (%rax), %xmm3, %xmm4"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x6d, 0x48, 0xd4, 0x40 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpermil2ps $0, %ymm4, %ymm4, %ymm2, %ymm2"
+  -
+    input:
+      bytes: [ 0xc4, 0xe3, 0x75, 0x49, 0x40, 0x04, 0x11 ]
+      arch: "CS_ARCH_X86"
+      options: [ "CS_OPT_SYNTAX_ATT", "CS_MODE_64" ]
+    expected:
+      insns:
+        -
+          asm_text: "vpermil2pd $1, %ymm1, 4(%rax), %ymm1, %ymm0"
diff --git a/tests/Makefile b/tests/Makefile
deleted file mode 100644
index 9d44f09cb..000000000
--- a/tests/Makefile
+++ /dev/null
@@ -1,203 +0,0 @@
-# Capstone Disassembler Engine
-# By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014
-
-include ../config.mk
-include ../functions.mk
-
-# Verbose output?
-V ?= 0
-
-INCDIR = ../include
-ifndef BUILDDIR
-TESTDIR = .
-OBJDIR = .
-LIBDIR = ..
-else
-TESTDIR = $(BUILDDIR)/tests
-OBJDIR = $(BUILDDIR)/obj/tests
-LIBDIR = $(BUILDDIR)
-endif
-
-ifeq ($(CROSS),)
-CC ?= cc
-else
-CC = $(CROSS)gcc
-endif
-
-
-CFLAGS += -Wall -I$(INCDIR)
-LDFLAGS += -L$(LIBDIR)
-
-CFLAGS += $(foreach arch,$(LIBARCHS),-arch $(arch))
-LDFLAGS += $(foreach arch,$(LIBARCHS),-arch $(arch))
-
-LIBNAME = capstone
-
-BIN_EXT =
-AR_EXT = a
-
-# Cygwin?
-IS_CYGWIN := $(shell $(CC) -dumpmachine | grep -i cygwin | wc -l)
-ifeq ($(IS_CYGWIN),1)
-CFLAGS := $(CFLAGS:-fPIC=)
-BIN_EXT = .exe
-AR_EXT = lib
-else
-# mingw?
-IS_MINGW := $(shell $(CC) --version 2>/dev/null | grep -i "\(mingw\|MSYS\)" | wc -l)
-ifeq ($(IS_MINGW),1)
-CFLAGS := $(CFLAGS:-fPIC=)
-BIN_EXT = .exe
-AR_EXT = lib
-endif
-endif
-
-ifeq ($(CAPSTONE_STATIC),yes)
-ifeq ($(IS_MINGW),1)
-ARCHIVE = $(LIBDIR)/$(LIBNAME).$(AR_EXT)
-else ifeq ($(IS_CYGWIN),1)
-ARCHIVE = $(LIBDIR)/$(LIBNAME).$(AR_EXT)
-else
-ARCHIVE = $(LIBDIR)/lib$(LIBNAME).$(AR_EXT)
-endif
-endif
-
-.PHONY: all clean
-
-SOURCES = test_basic.c test_detail.c test_skipdata.c test_iter.c test_customized_mnem.c
-ifneq (,$(findstring arm,$(CAPSTONE_ARCHS)))
-CFLAGS += -DCAPSTONE_HAS_ARM
-SOURCES += test_arm.c
-endif
-ifneq (,$(findstring aarch64,$(CAPSTONE_ARCHS)))
-CFLAGS += -DCAPSTONE_HAS_AARCH64
-SOURCES += test_aarch64.c
-endif
-ifneq (,$(findstring m68k,$(CAPSTONE_ARCHS)))
-CFLAGS += -DCAPSTONE_HAS_M68K
-SOURCES += test_m68k.c
-endif
-ifneq (,$(findstring mips,$(CAPSTONE_ARCHS)))
-CFLAGS += -DCAPSTONE_HAS_MIPS
-SOURCES += test_mips.c
-endif
-ifneq (,$(findstring powerpc,$(CAPSTONE_ARCHS)))
-CFLAGS += -DCAPSTONE_HAS_POWERPC
-SOURCES += test_ppc.c
-endif
-ifneq (,$(findstring sparc,$(CAPSTONE_ARCHS)))
-CFLAGS += -DCAPSTONE_HAS_SPARC
-SOURCES += test_sparc.c
-endif
-ifneq (,$(findstring systemz,$(CAPSTONE_ARCHS)))
-CFLAGS += -DCAPSTONE_HAS_SYSZ
-SOURCES += test_systemz.c
-endif
-ifneq (,$(findstring x86,$(CAPSTONE_ARCHS)))
-CFLAGS += -DCAPSTONE_HAS_X86
-SOURCES += test_x86.c
-endif
-ifneq (,$(findstring xcore,$(CAPSTONE_ARCHS)))
-CFLAGS += -DCAPSTONE_HAS_XCORE
-SOURCES += test_xcore.c
-endif
-ifneq (,$(findstring tms320c64x,$(CAPSTONE_ARCHS)))
-CFLAGS += -DCAPSTONE_HAS_TMS320C64X
-SOURCES += test_tms320c64x.c
-endif
-ifneq (,$(findstring m680x,$(CAPSTONE_ARCHS)))
-CFLAGS += -DCAPSTONE_HAS_M680X
-SOURCES += test_m680x.c
-endif
-ifneq (,$(findstring evm,$(CAPSTONE_ARCHS)))
-CFLAGS += -DCAPSTONE_HAS_EVM
-SOURCES += test_evm.c
-endif
-ifneq (,$(findstring riscv,$(CAPSTONE_ARCHS)))
-CFLAGS += -DCAPSTONE_HAS_RISCV
-SOURCES += test_riscv.c
-endif
-ifneq (,$(findstring wasm,$(CAPSTONE_ARCHS)))
-CFLAGS += -DCAPSTONE_HAS_WASM
-SOURCES += test_wasm.c
-endif
-ifneq (,$(findstring evm,$(CAPSTONE_ARCHS)))
-CFLAGS += -DCAPSTONE_HAS_MOS65XX
-SOURCES += test_mos65xx.c
-endif
-ifneq (,$(findstring bpf,$(CAPSTONE_ARCHS)))
-CFLAGS += -DCAPSTONE_HAS_BPF
-SOURCES += test_bpf.c
-endif
-ifneq (,$(findstring tricore,$(CAPSTONE_ARCHS)))
-CFLAGS += -DCAPSTONE_HAS_TRICORE
-SOURCES += test_tricore.c
-endif
-ifneq (,$(findstring sh,$(CAPSTONE_ARCHS)))
-CFLAGS += -DCAPSTONE_HAS_SH
-SOURCES += test_sh.c
-endif
-ifneq (,$(findstring alpha,$(CAPSTONE_ARCHS)))
-CFLAGS += -DCAPSTONE_HAS_ALPHA
-SOURCES += test_alpha.c
-endif
-ifneq (,$(findstring hppa,$(CAPSTONE_ARCHS)))
-CFLAGS += -DCAPSTONE_HAS_HPPA
-SOURCES += test_hppa.c
-endif
-
-
-OBJS = $(addprefix $(OBJDIR)/,$(SOURCES:.c=.o))
-BINARY = $(addprefix $(TESTDIR)/,$(SOURCES:.c=$(BIN_EXT)))
-
-all: $(BINARY)
-
-clean:
-	rm -rf $(OBJS) $(BINARY) $(TESTDIR)/*.exe $(TESTDIR)/*.static $(OBJDIR)/lib$(LIBNAME).* $(OBJDIR)/$(LIBNAME).*
-	rm -f *.d $(TESTDIR)/*.d $(OBJDIR)/*.d
-	# remove orphan files due to renaming from test.c to test_basic.c
-	rm -rf $(TESTDIR)/test.o $(TESTDIR)/test.exe $(TESTDIR)/test.static $(TESTDIR)/test
-
-$(BINARY): $(OBJS)
-
-$(TESTDIR)/%$(BIN_EXT): $(OBJDIR)/%.o
-	@mkdir -p $(@D)
-ifeq ($(V),0)
-ifeq ($(CAPSTONE_SHARED),yes)
-	$(call log,LINK,$(notdir $@))
-	@$(link-dynamic)
-endif
-ifeq ($(CAPSTONE_STATIC),yes)
-	$(call log,LINK,$(notdir $(call staticname,$@)))
-	@$(link-static)
-endif
-else
-ifeq ($(CAPSTONE_SHARED),yes)
-	$(link-dynamic)
-endif
-ifeq ($(CAPSTONE_STATIC),yes)
-	$(link-static)
-endif
-endif
-
-$(OBJDIR)/%.o: %.c
-	@mkdir -p $(@D)
-ifeq ($(V),0)
-	$(call log,CC,$(@:$(OBJDIR)/%=%))
-	@$(compile)
-else
-	$(compile)
-endif
-
-
-define link-dynamic
-	$(CC) $(LDFLAGS) $< -l$(LIBNAME) -o $@
-endef
-
-
-define link-static
-	$(CC) $(LDFLAGS) $< $(ARCHIVE) -o $(call staticname,$@)
-endef
-
-
-staticname = $(subst $(BIN_EXT),,$(1)).static$(BIN_EXT)
diff --git a/tests/README b/tests/README
deleted file mode 100644
index e5d3efb48..000000000
--- a/tests/README
+++ /dev/null
@@ -1,31 +0,0 @@
-This directory contains some test code to show how to use Capstone API.
-
-- test_basic.c
-  This code shows the most simple form of API where we only want to get basic
-  information out of disassembled instruction, such as address, mnemonic and
-  operand string.
-
-- test_detail.c:
-  This code shows how to access to architecture-neutral information in disassembled
-  instructions, such as implicit registers read/written, or groups of instructions
-  that this instruction belong to.
-
-- test_skipdata.c:
-  This code shows how to use SKIPDATA option to skip broken instructions (most likely
-  some data mixed with instructions) and continue to decode at the next legitimate
-  instructions.
-
-- test_iter.c:
-  This code shows how to use the API cs_disasm_iter() to decode one instruction at
-  a time inside a loop.
-
-- test_customized_mnem.c:
-  This code shows how to use MNEMONIC option to customize instruction mnemonic
-  at run-time, and then how to reset the engine to use the default mnemonic.
-
-- test_<arch>.c
-  These code show how to access architecture-specific information for each
-  architecture.
-
-- test_winkernel.cpp
-  This code shows how to use Capstone from a Windows driver.
diff --git a/tests/README.md b/tests/README.md
new file mode 100644
index 000000000..94484d744
--- /dev/null
+++ b/tests/README.md
@@ -0,0 +1,159 @@
+# Testing in Capstone
+
+## Running tests
+
+### Types of test and their location
+
+_YAML test files_
+
+These test files are consumed by the various `cstest` tools.
+They contain all detail tests. As well as the LLVM regression tests (`MC` tests).
+
+Directories group tests by the category they intent to test.
+
+_Legacy (integration)_
+
+Legacy tests which only printed to `stdout`. In practice they only test if the code segfaults.
+Checking the produced output was not implemented.
+
+### Testing tools and usage
+
+#### `cstest`
+
+`cstest` is the testing tool written in C. It is implemented in `suite/cstest/`
+It consumes the `yaml` files and reports errors or mismatches for disassembled instructions and their details.
+
+**Building**
+
+> _Dependencies:_ `cstest` requires the `libyaml` library.
+
+You build `cstest` by adding the `-DCAPSTONE_BUILD_CSTEST=1` option during configuration of the Capstone build.
+
+If you build and install Capstone `cstest` gets installed as well.
+Otherwise you find it in the build directory.
+
+```bash
+# Install libyaml
+# sudo apt install libyaml-dev
+# or
+# sudo dnf install libyaml-devel
+cd "<capstone-repo-root>"
+# Optionally add the `-DENABLE_ASAN=1` flag.
+cmake -B build -DCMAKE_BUILD_TYPE=Debug -DCAPSTONE_BUILD_CSTEST=ON
+cmake --build build --config Debug
+cmake --install build --prefix "<install-prefix>"
+```
+
+Run the integration tests for `cstest` itself
+
+```bash
+./suite/cstest/test/integration_tests.py cstest
+```
+
+**Run the tests**
+
+```bash
+# Check supported options
+cstest -h
+# Run all
+cstest tests/
+```
+
+Alternatively, you can use the `CMake` test manager.
+
+```bash
+# List available tests
+ctest --test-dir build -N
+# Run a specific test
+ctest --test-dir build -R "<name>"
+```
+
+#### `cstest_py`
+
+`cstest_py` is the testing tool written in Python. It is implemented in `bindings/python/cstest_py`
+It consumes the `yaml` files and reports errors or mismatches for disassembled instructions and their details.
+
+**Installing**
+
+You need to install the Capstone Python bindings first and afterwards the `cstest_py`.
+
+```bash
+# Optionally, create a new virtual environment
+python3 -m venv .venv
+source .venv/bin/activate
+
+cd bindings/python
+pip install -e .
+pip install -e cstest_py
+cd ../..
+```
+
+Run the integration tests for `cstest_py` itself
+
+```bash
+./suite/cstest/test/integration_tests.py cstest_py
+```
+
+And run the tests
+
+```bash
+# Check supported options
+cstest_py -h
+# Run all
+cstest_py tests/
+```
+
+## Add new tests
+
+### Unit and integration tests
+
+Add the source into `test/integration` or `test/unit` respectively and update the `CMakeLists.txt` file.
+
+### YAML
+
+There are very few fields which are mandatory to fill.
+Check `suite/cstest/test/min_valid_test_file.yaml` to see which one.
+
+- In general it is useful to just copy a previous test file and rewrite it accordingly.
+- If you assign C enumeration identifiers to some fields (to check enumeration values),
+ensure they are added on the `suite/cstest/include/test_mapping.h`. Otherwise, `cstest` cannot map the strings
+to the values for comparison.
+- Rarely used, but useful fields are: `name`, `skip`, `skip_reason`.
+
+#### MC regression tests
+
+The `MCUpdater` translates most test files of the LLVM MC regression tests into our YAML files.
+
+The LLVM regression tests, check the bytes and assembly for all instructions of an architecture.
+They do it by passing bytes or assembly to the `llvm-mc` and `FileCheck` tool and compare the output.
+We capture this output and process it into YAML.
+So you need to install `llvm-mc` and `FileCheck` for our updater to work.
+
+To update the YAML MC regression tests, you need to install `Auto-Sync` and run the `MCUpdater`.
+
+```bash
+cd suite/auto-sync/
+# Follow install instructions of Auto-Sync described in the README
+# And run the updater:
+./src/autosync/MCUpdater.py -a ARCH
+ls build/mc_out/
+# The produce yaml files. Copy them manually to tests/MC/ARCH
+```
+
+**Please note:**
+
+Each of the LLVM test files can contain several `llvm-mc` commands to run on the same file.
+This is done to test the same file with different CPU features enabled.
+So it can test different assembly flavors etc.
+
+In Capstone all modules enable always all CPU features (even if this is not
+possible in reality).
+Due to this, we always parse all `llvm-mc` commands but only write the last version of them to disk.
+So if the same test file is tested with three different features enables, once with `FeatureA`, `FeatureB` and `FeatureC`
+we only save the output with `FeatureC` enabled.
+
+This might give you MC test files which fail due to valid but mismatching disassembly.
+You can set the `skip` field for those tests and add a `skip_reason`.
+
+Once https://github.com/capstone-engine/capstone/issues/1992 is resolved, we can
+test all variants.
diff --git a/tests/cs_details/issue.cs b/tests/cs_details/issue.cs
deleted file mode 100644
index fc99d5e23..000000000
--- a/tests/cs_details/issue.cs
+++ /dev/null
@@ -1,670 +0,0 @@
-!# issue 0 ARM operand groups 0x90,0xe8,0x0e,0x00 == ldm.w r0, {r1, r2, r3} ;
-!# CS_ARCH_ARM, CS_MODE_THUMB, CS_OPT_DETAIL
-0x90,0xe8,0x0e,0x00 == ldm.w r0, {r1, r2, r3} ; op_count: 4 ; operands[0].type: REG = r0 ; operands[0].access: READ ; operands[1].type: REG = r1 ; operands[1].access: WRITE ; operands[2].type: REG = r2 ; operands[2].access: WRITE ; operands[3].type: REG = r3 ; operands[3].access: WRITE ; Registers read: r0 ; Registers modified: r1 r2 r3 ; Groups: IsThumb2
-
-!# issue 0 ARM operand groups 0x0e,0xc8 == ldm r0!, {r1, r2, r3} ;
-!# CS_ARCH_ARM, CS_MODE_THUMB, CS_OPT_DETAIL
-0x0e,0xc8 == ldm r0!, {r1, r2, r3}  ; op_count: 4 ; operands[0].type: REG = r0 ; operands[0].access: READ | WRITE ; operands[1].type: REG = r1 ; operands[1].access: WRITE ; operands[2].type: REG = r2 ; operands[2].access: WRITE ; operands[3].type: REG = r3 ; operands[3].access: WRITE ; Write-back: True ; Registers read: r0 ; Registers modified: r0 r1 r2 r3 ; Groups: IsThumb
-
-!# issue 0 ARM operand groups 0x00,0x2a,0xf7,0xee == vmov.f32 s5, #1.000000e+00 ;
-!# CS_ARCH_ARM, CS_MODE_ARM, CS_OPT_DETAIL
-0x00,0x2a,0xf7,0xee == vmov.f32 s5, #1.000000e+00 ; op_count: 2 ; operands[0].type: REG = s5 ; operands[0].access: WRITE ; operands[1].type: FP = 1.000000 ; Registers modified: s5 ; Groups: HasVFP3
-
-!# issue 0 ARM operand groups 0x0f,0x00,0x71,0xe3 == cmn r1, #15 ;
-!# CS_ARCH_ARM, CS_MODE_ARM, CS_OPT_DETAIL
-0x0f,0x00,0x71,0xe3 == cmn r1, #0xf ; op_count: 2 ; operands[0].type: REG = r1 ; operands[0].access: READ ; operands[1].type: IMM = 0xf ; operands[1].access: READ ; Update-flags: True ; Registers read: r1 ; Registers modified: cpsr ; Groups: IsARM
-
-!# issue 0 ARM operand groups 0x03,0x20,0xb0,0xe1 == movs r2, r3 ;
-!# CS_ARCH_ARM, CS_MODE_ARM, CS_OPT_DETAIL
-0x03,0x20,0xb0,0xe1 == movs r2, r3 ;  op_count: 2 ; operands[0].type: REG = r2 ; operands[0].access: WRITE ; operands[1].type: REG = r3 ; operands[1].access: READ ; Update-flags: True ; Registers read: r3 ; Registers modified: cpsr r2 ; Groups: IsARM
-
-!# issue 0 ARM operand groups 0xfd,0x8f == ldrh r5, [r7, #62] ;
-!# CS_ARCH_ARM, CS_MODE_THUMB, CS_OPT_DETAIL
-0xfd,0x8f == ldrh r5, [r7, #0x3e] ; op_count: 2 ; operands[0].type: REG = r5 ; operands[0].access: WRITE ; operands[1].type: MEM ; operands[1].mem.base: REG = r7 ; operands[1].mem.disp: 0x3e ; operands[1].access: READ ; Registers read: r7 ; Registers modified: r5 ; Groups: IsThumb
-
-!# issue 0 ARM operand groups 0x61,0xb6 == cpsie f ;
-!# CS_ARCH_ARM, CS_MODE_THUMB, CS_OPT_DETAIL
-0x61,0xb6 == cpsie f ; CPSI-mode: 2 ; CPSI-flag: 1 ; Groups: IsThumb
-
-!# issue 0 ARM operand groups 0x18,0xf8,0x03,0x1e == ldrbt r1, [r8, #3] ;
-!# CS_ARCH_ARM, CS_MODE_THUMB, CS_OPT_DETAIL
-0x18,0xf8,0x03,0x1e == ldrbt r1, [r8, #3] ; op_count: 2 ; operands[0].type: REG = r1 ; operands[0].access: WRITE ; operands[1].type: MEM ; operands[1].mem.base: REG = r8 ; operands[1].mem.disp: 0x3 ; operands[1].access: READ ; Registers read: r8 ; Registers modified: r1 ; Groups: IsThumb2
-
-!# issue 0 ARM operand groups 0xb0,0xf8,0x01,0xf1 == pldw [r0, #257] ;
-!# CS_ARCH_ARM, CS_MODE_THUMB, CS_OPT_DETAIL
-0xb0,0xf8,0x01,0xf1 == pldw [r0, #0x101] ; op_count: 1 ; operands[0].type: MEM ; operands[0].mem.base: REG = r0 ; operands[0].mem.disp: 0x101 ; operands[0].access: READ ; Registers read: r0 ; Groups: IsThumb2 HasV7 HasMP
-
-!# issue 0 ARM operand groups 0xd3,0xe8,0x08,0xf0 == tbb [r3, r8] ;
-!# CS_ARCH_ARM, CS_MODE_THUMB, CS_OPT_DETAIL
-0xd3,0xe8,0x08,0xf0 == tbb [r3, r8] ; op_count: 1 ; operands[0].type: MEM ; operands[0].mem.base: REG = r3 ; operands[0].mem.index: REG = r8 ; operands[0].access: READ ; Registers read: r3 r8 ; Groups: jump IsThumb2
-
-!# issue 0 ARM operand groups 0xd3,0xe8,0x18,0xf0 == tbh [r3, r8, lsl #1] ;
-!# CS_ARCH_ARM, CS_MODE_THUMB, CS_OPT_DETAIL
-0xd3,0xe8,0x18,0xf0 == tbh [r3, r8, lsl #1] ;  op_count: 1 ; operands[0].type: MEM ; operands[0].mem.base: REG = r3 ; operands[0].mem.index: REG = r8 ; operands[0].mem.lshift: 0x1 ; operands[0].access: READ ; Shift: 2 = 1 ; Registers read: r3 r8 ; Groups: jump IsThumb2
-
-!# issue 0 ARM operand groups 0xaf,0xf3,0x43,0x85 == cpsie i, #3 ;
-!# CS_ARCH_ARM, CS_MODE_THUMB, CS_OPT_DETAIL
-0xaf,0xf3,0x43,0x85 == cpsie i, #3 ; cpsie i, #3 ; op_count: 1 ; operands[0].type: IMM = 0x3 ; operands[0].access: READ ; CPSI-mode: 2 ; CPSI-flag: 2 ; Groups: IsThumb2 IsNotMClass
-
-!# issue 0 ARM operand groups 0xbf,0xf3,0x6f,0x8f == isb sy ;
-!# CS_ARCH_ARM, CS_MODE_THUMB, CS_OPT_DETAIL
-0xbf,0xf3,0x6f,0x8f == isb sy ; isb sy ; Memory-barrier: 15 ; Groups: IsThumb HasDB
-
-!# issue 0 ARM operand groups 0x59,0xea,0x7b,0x89 == csel r9, r9, r11, vc ;
-!# CS_ARCH_ARM, CS_MODE_THUMB | CS_MODE_V8, CS_OPT_DETAIL
-0x59,0xea,0x7b,0x89 == csel r9, r9, r11, vc ; op_count: 3 ; operands[0].type: REG = r9 ; operands[0].access: WRITE ; operands[1].type: REG = r9 ; operands[1].access: READ ; operands[2].type: REG = r11 ; operands[2].access: READ ; Code condition: 7 ; Registers read: cpsr r9 r11 ; Registers modified: r9 ; Groups: HasV8_1MMainline
-
-!# issue 0 ARM operand groups 0xbf,0xf3,0x56,0x8f == dmb nshst ;
-!# CS_ARCH_ARM, CS_MODE_THUMB, CS_OPT_DETAIL
-0xbf,0xf3,0x56,0x8f == dmb nshst ; dmb nshst ; Memory-barrier: 6 ; Groups: IsThumb HasDB
-
-!# issue 0 ARM operand groups 0x31,0xfa,0x02,0xf2 == lsrs.w r2, r1, r2 ;
-!# CS_ARCH_ARM, CS_MODE_THUMB, CS_OPT_DETAIL
-0x31,0xfa,0x02,0xf2 == lsrs.w r2, r1, r2 ;  op_count: 3 ; operands[0].type: REG = r2 ; operands[0].access: WRITE ; operands[1].type: REG = r1 ; operands[1].access: READ ; operands[2].type: REG = r2 ; operands[2].access: READ ; Update-flags: True ; Registers read: r1 r2 ; Registers modified: cpsr r2 ; Groups: IsThumb2
-
-!# issue 0 ARM operand groups 0x5f,0xf0,0x0c,0x01 == movseq.w r1, #12 ;
-!# CS_ARCH_ARM, CS_MODE_THUMB, CS_OPT_DETAIL
-0x08,0xbf == it eq ; Code condition: 0 ; Predicate Mask: 0x1 ; Registers modified: itstate ; Groups: IsThumb2
-0x5f,0xf0,0x0c,0x01 == movseq.w r1, #0xc ; op_count: 2 ; operands[0].type: REG = r1 ; operands[0].access: WRITE ; operands[1].type: IMM = 0xc ; operands[1].access: READ ; Code condition: 0 ; Update-flags: True ; Registers modified: cpsr r1 ; Groups: IsThumb2
-
-!# issue 0 ARM operand groups 0x52,0xe8,0x01,0x1f == ldrex r1, [r2, #4] ;
-!# CS_ARCH_ARM, CS_MODE_THUMB, CS_OPT_DETAIL
-0x52,0xe8,0x01,0x1f == ldrex r1, [r2, #4] ; op_count: 2 ; operands[0].type: REG = r1 ; operands[0].access: WRITE ; operands[1].type: MEM ; operands[1].mem.base: REG = r2 ; operands[1].mem.disp: 0x4 ; operands[1].access: READ ; Registers read: r2 ; Registers modified: r1 ; Groups: IsThumb HasV8MBaseline
-
-!# issue 0 ARM operand groups 0xdf,0xec,0x1d,0x1a == vscclrmhi {s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31, vpr} ;
-!# CS_ARCH_ARM, CS_MODE_THUMB | CS_MODE_V8, CS_OPT_DETAIL
-0x88,0xbf == it hi ; Code condition: 8 ; Predicate Mask: 0x1 ; Groups: IsThumb2
-0xdf,0xec,0x1d,0x1a == vscclrmhi {s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31, vpr} ; op_count: 30 ; operands[0].type: REG = s3 ; operands[0].access: WRITE ; operands[1].type: REG = s4 ; operands[1].access: WRITE ; operands[2].type: REG = s5 ; operands[2].access: WRITE ; operands[3].type: REG = s6 ; operands[3].access: WRITE ; operands[4].type: REG = s7 ; operands[4].access: WRITE ; operands[5].type: REG = s8 ; operands[5].access: WRITE ; operands[6].type: REG = s9 ; operands[6].access: WRITE ; operands[7].type: REG = s10 ; operands[7].access: WRITE ; operands[8].type: REG = s11 ; operands[8].access: WRITE ; operands[9].type: REG = s12 ; operands[9].access: WRITE ; operands[10].type: REG = s13 ; operands[10].access: WRITE ; operands[11].type: REG = s14 ; operands[11].access: WRITE ; operands[12].type: REG = s15 ; operands[12].access: WRITE ; operands[13].type: REG = s16 ; operands[13].access: WRITE ; operands[14].type: REG = s17 ; operands[14].access: WRITE ; operands[15].type: REG = s18 ; operands[15].access: WRITE ; operands[16].type: REG = s19 ; operands[16].access: WRITE ; operands[17].type: REG = s20 ; operands[17].access: WRITE ; operands[18].type: REG = s21 ; operands[18].access: WRITE ; operands[19].type: REG = s22 ; operands[19].access: WRITE ; operands[20].type: REG = s23 ; operands[20].access: WRITE ; operands[21].type: REG = s24 ; operands[21].access: WRITE ; operands[22].type: REG = s25 ; operands[22].access: WRITE ; operands[23].type: REG = s26 ; operands[23].access: WRITE ; operands[24].type: REG = s27 ; operands[24].access: WRITE ; operands[25].type: REG = s28 ; operands[25].access: WRITE ; operands[26].type: REG = s29 ; operands[26].access: WRITE ; operands[27].type: REG = s30 ; operands[27].access: WRITE ; operands[28].type: REG = s31 ; operands[28].access: WRITE ; operands[29].type: REG = vpr ; operands[29].access: WRITE ; Code condition: 8 ; Registers modified: s3 s4 s5 s6 s7 s8 s9 s10 s11 s12 s13 s14 s15 s16 s17 s18 s19 s20 s21 s22 s23 s24 s25 s26 s27 s28 s29 s30 s31 vpr ; Groups: HasV8_1MMainline Has8MSecExt
-
-!# issue 0 ARM operand groups 0x9f,0xec,0x06,0x5b == vscclrm {d5, d6, d7, vpr} ;
-!# CS_ARCH_ARM, CS_MODE_THUMB | CS_MODE_V8, CS_OPT_DETAIL
-0x9f,0xec,0x06,0x5b == vscclrm {d5, d6, d7, vpr} ; op_count: 4 ; operands[0].type: REG = d5 ; operands[0].access: WRITE ; operands[1].type: REG = d6 ; operands[1].access: WRITE ; operands[2].type: REG = d7 ; operands[2].access: WRITE ; operands[3].type: REG = vpr ; operands[3].access: WRITE ; Registers modified: d5 d6 d7 vpr ; Groups: HasV8_1MMainline Has8MSecExt
-
-!# issue 0 ARM operand groups 0xbc,0xfd,0x7f,0xaf == vldrh.u32 q5, [r4, #254]! ;
-!# CS_ARCH_ARM, CS_MODE_THUMB | CS_MODE_V8 | CS_MODE_MCLASS, CS_OPT_DETAIL
-0xbc,0xfd,0x7f,0xaf == vldrh.u32 q5, [r4, #0xfe]! ; op_count: 2 ; operands[0].type: REG = q5 ; operands[0].access: WRITE ; operands[1].type: MEM ; operands[1].mem.base: REG = r4 ; operands[1].mem.disp: 0xfe ; operands[1].access: READ ; Write-back: True ; Registers read: r4 ; Registers modified: r4 q5 ; Groups: HasMVEInt
-
-!# issue 0 ARM operand groups 0x80,0xfc,0x80,0x1e == vst20.16 {q0, q1}, [r0] ;
-!# CS_ARCH_ARM, CS_MODE_THUMB | CS_MODE_MCLASS, CS_OPT_DETAIL
-0x80,0xfc,0x80,0x1e == vst20.16 {q0, q1}, [r0] ; op_count: 3 ; operands[0].type: REG = q0 ; operands[0].access: READ ; operands[1].type: REG = q1 ; operands[1].access: READ ; operands[2].type: MEM ; operands[2].mem.base: REG = r0 ; operands[2].access: WRITE ; Registers read: q0 q1 r0 ; Groups: HasMVEInt
-
-!# issue 0 ARM operand groups 0x98,0xfc,0x4e,0x08 == vcadd.f32 q0, q4, q7, #90 ;
-!# CS_ARCH_ARM, CS_MODE_THUMB | CS_MODE_MCLASS, CS_OPT_DETAIL
-0x98,0xfc,0x4e,0x08 == vcadd.f32 q0, q4, q7, #90 ; op_count: 4 ; operands[0].type: REG = q0 ; operands[0].access: READ | WRITE ; operands[1].type: REG = q4 ; operands[1].access: READ ; operands[2].type: REG = q7 ; operands[2].access: READ ; operands[3].type: IMM = 0x5a ; operands[3].access: READ ; Registers read: q0 q4 q7 ; Registers modified: q0 ; Groups: HasMVEFloat
-
-!# issue 0 ARM operand groups 0x94,0xfd,0x46,0x48 == vcadd.f32 q2, q2, q3, #270 ;
-!# CS_ARCH_ARM, CS_MODE_THUMB | CS_MODE_V8, CS_OPT_DETAIL
-0x94,0xfd,0x46,0x48 == vcadd.f32 q2, q2, q3, #270 ; op_count: 4 ; operands[0].type: REG = q2 ; operands[0].access: WRITE ; operands[1].type: REG = q2 ; operands[1].access: READ ; operands[2].type: REG = q3 ; operands[2].access: READ ; operands[3].type: IMM = 0x10e ; operands[3].access: READ ; Registers read: q2 q3 ; Registers modified: q2 ; Groups: HasNEON HasV8_3a
-
-!# issue 0 ARM operand groups 0x9d,0xec,0x82,0x6e == vldrb.s16 q3, [sp, q1] ;
-!# CS_ARCH_ARM, CS_MODE_THUMB | CS_MODE_MCLASS, CS_OPT_DETAIL
-0x9d,0xec,0x82,0x6e == vldrb.s16 q3, [sp, q1] ; op_count: 2 ; operands[0].type: REG = q3 ; operands[0].access: WRITE ; operands[1].type: MEM ; operands[1].mem.base: REG = r13 ; operands[1].mem.index: REG = q1 ; operands[1].access: READ ; Registers read: r13 q1 ; Registers modified: q3 ; Groups: HasMVEInt
-
-!# issue 0 ARM operand groups 0x90,0xec,0x12,0x6f == vldrh.s32 q3, [r0, q1] ;
-!# CS_ARCH_ARM, CS_MODE_THUMB | CS_MODE_MCLASS, CS_OPT_DETAIL
-0x90,0xec,0x12,0x6f == vldrh.s32 q3, [r0, q1] ; op_count: 2 ; operands[0].type: REG = q3 ; operands[0].access: WRITE ; operands[1].type: MEM ; operands[1].mem.base: REG = r0 ; operands[1].mem.index: REG = q1 ; operands[1].access: READ ; Registers read: r0 q1 ; Registers modified: q3 ; Groups: HasMVEInt
-
-!# issue 0 ARM operand groups 0x5f,0xea,0x2d,0x83 == sqrshrl lr, r3, #64, r8 ;
-!# CS_ARCH_ARM, CS_MODE_THUMB | CS_MODE_V8 | CS_MODE_MCLASS, CS_OPT_DETAIL
-0x5f,0xea,0x2d,0x83 == sqrshrl lr, r3, #0x40, r8 ; op_count: 4 ; operands[0].type: REG = r14 ; operands[0].access: READ | WRITE ; operands[1].type: REG = r3 ; operands[1].access: READ | WRITE ; operands[2].type: IMM = 0x40 ; operands[2].access: READ ; operands[3].type: REG = r8 ; operands[3].access: READ ; Write-back: True ; Registers read: r14 r3 r8 ; Registers modified: r14 r3 ; Groups: HasV8_1MMainline HasMVEInt
-
-!# issue 0 ARM operand groups 0x82,0xfd,0x21,0xff == vstrd.64 q7, [q1, #264] ;
-!# CS_ARCH_ARM, CS_MODE_THUMB | CS_MODE_MCLASS, CS_OPT_DETAIL
-0x82,0xfd,0x21,0xff == vstrd.64 q7, [q1, #0x108] ; op_count: 2 ; operands[0].type: REG = q7 ; operands[0].access: READ ; operands[1].type: MEM ; operands[1].mem.base: REG = q1 ; operands[1].mem.disp: 0x108 ; operands[1].access: WRITE ; Registers read: q7 q1 ; Groups: HasMVEInt
-
-!# issue 0 ARM operand groups 0x06,0x16,0x72,0xe6 == ldrbt r1, [r2], -r6, lsl #12 ;
-!# CS_ARCH_ARM, CS_MODE_ARM, CS_OPT_DETAIL
-0x06,0x16,0x72,0xe6 == ldrbt r1, [r2], -r6, lsl #12 ; op_count: 2 ; operands[0].type: REG = r1 ; operands[0].access: WRITE ; operands[1].type: MEM ; operands[1].mem.base: REG = r2 ; operands[1].mem.index: REG = r6 ; operands[1].access: READ ; Shift: 2 = 12 ; Subtracted: True ; Write-back: True ; Registers read: r2 r6 ; Registers modified: r2 r1 ; Groups: IsARM
-
-!# issue 0 ARM operand groups 0xf6,0x50,0x33,0xe1 == ldrsh r5, [r3, -r6]! ;
-!# CS_ARCH_ARM, CS_MODE_ARM, CS_OPT_DETAIL
-0xf6,0x50,0x33,0xe1 == ldrsh r5, [r3, -r6]! ; op_count: 2 ; operands[0].type: REG = r5 ; operands[0].access: WRITE ; operands[1].type: MEM ; operands[1].mem.base: REG = r3 ; operands[1].mem.index: REG = r6 ; operands[1].access: READ ; Subtracted: True ; Write-back: True ; Registers read: r3 r6 ; Registers modified: r3 r5 ; Groups: IsARM
-
-!# issue 0 ARM operand groups 0x1e,0x19,0x7a,0xfd == ldc2l p9, c1, [r10, #-120]! ;
-!# CS_ARCH_ARM, CS_MODE_ARM, CS_OPT_DETAIL
-0x1e,0x19,0x7a,0xfd == ldc2l p9, c1, [r10, #-0x78]! ; op_count: 3 ; operands[0].type: P-IMM = 9 ; operands[0].access: READ ; operands[1].type: C-IMM = 1 ; operands[1].access: READ ; operands[2].type: MEM ; operands[2].mem.base: REG = r10 ; operands[2].mem.disp: 0x78 ; operands[2].access: READ ; Registers read: r10 ; Registers modified: r10 ; Groups: IsARM PreV8
-
-!# issue 0 ARM operand groups 0x12,0x31,0x7c,0xfc == ldc2l p1, c3, [r12], #-72 ;
-!# CS_ARCH_ARM, CS_MODE_ARM, CS_OPT_DETAIL
-0x12,0x31,0x7c,0xfc == ldc2l p1, c3, [r12], #-0x48 ; op_count: 3 ; operands[0].type: P-IMM = 1 ; operands[0].access: READ ; operands[1].type: C-IMM = 3 ; operands[1].access: READ ; operands[2].type: MEM ; operands[2].mem.base: REG = r12 ; operands[2].access: READ ; operands[2].mem.disp: 0x48 ; Subtracted: True ; Registers read: r12 ; Groups: IsARM PreV8
-
-!# issue 0 ARM operand groups 0xa4,0xf9,0x6d,0x0e == vld3.16 {d0[], d2[], d4[]}, [r4]! ;
-!# CS_ARCH_ARM, CS_MODE_THUMB, CS_OPT_DETAIL
-0xa4,0xf9,0x6d,0x0e == vld3.16 {d0[], d2[], d4[]}, [r4]! ; op_count: 4 ; operands[0].type: REG = d0 ; operands[0].access: WRITE ; operands[1].type: REG = d2 ; operands[1].access: WRITE ; operands[2].type: REG = d4 ; operands[2].access: WRITE ; operands[3].type: MEM ; operands[3].mem.base: REG = r4 ; operands[3].access: READ | WRITE ; Write-back: True ; Registers read: r4 ; Registers modified: r4 d0 d2 d4
-
-!# issue 0 ARM operand groups 0x0d,0x50,0x66,0xe4 == strbt r5, [r6], #-13 ;
-!# CS_ARCH_ARM, CS_MODE_ARM, CS_OPT_DETAIL
-0x0d,0x50,0x66,0xe4 == strbt r5, [r6], #-0xd ; op_count: 2 ; operands[0].type: REG = r5 ; operands[0].access: READ ; operands[1].type: MEM ; operands[1].mem.base: REG = r6 ; operands[1].access: WRITE ; operands[1].mem.disp: 0xd ; Subtracted: True ; Write-back: True ; Registers read: r5 r6 ; Registers modified: r6 ; Groups: IsARM
-
-!# issue 0 ARM operand groups 0x00,0x10,0x4f,0xe2 == sub r1, pc, #0 ;
-!# CS_ARCH_ARM, CS_MODE_ARM, CS_OPT_DETAIL
-0x00,0x10,0x4f,0xe2 == sub r1, pc, #0 ; op_count: 3 ; operands[0].type: REG = r1 ; operands[0].access: WRITE ; operands[1].type: REG = r15 ; operands[1].access: READ ; operands[2].type: IMM = 0x0 ; operands[2].access: READ ; Registers read: r15 ; Registers modified: r1 ; Groups: IsARM
-
-!# issue 0 ARM operand groups 0x9f,0x51,0xd3,0xe7 == bfc r5, #3, #17 ;
-!# CS_ARCH_ARM, CS_MODE_ARM, CS_OPT_DETAIL
-0x9f,0x51,0xd3,0xe7 == bfc r5, #3, #0x11 ; op_count: 3 ; operands[0].type: REG = r5 ; operands[0].access: READ | WRITE ; operands[1].type: IMM = 0x3 ; operands[1].access: READ ; operands[2].type: IMM = 0x11 ; operands[2].access: READ ; Write-back: True ; Registers read: r5 ; Registers modified: r5 ; Groups: IsARM HasV6T2
-
-!# issue 0 ARM operand groups 0xd8,0xe8,0xff,0x67 == ldaexd r6, r7, [r8] ;
-!# CS_ARCH_ARM, CS_MODE_THUMB, CS_OPT_DETAIL
-0xd8,0xe8,0xff,0x67 == ldaexd r6, r7, [r8] ; op_count: 3 ; operands[0].type: REG = r6 ; operands[0].access: WRITE ; operands[1].type: REG = r7 ; operands[1].access: WRITE ; operands[2].type: MEM ; operands[2].mem.base: REG = r8 ; operands[2].access: READ ; Registers read: r8 ; Registers modified: r6 r7 ; Groups: IsThumb HasAcquireRelease HasV7Clrex IsNotMClass
-
-!# issue 0 ARM operand groups 0x30,0x0f,0xa6,0xe6 == ssat16 r0, #7, r0 ;
-!# CS_ARCH_ARM, CS_MODE_ARM, CS_OPT_DETAIL
-0x30,0x0f,0xa6,0xe6 == ssat16 r0, #7, r0 ; op_count: 3 ; operands[0].type: REG = r0 ; operands[0].access: WRITE ; operands[1].type: IMM = 0x7 ; operands[1].access: READ ; operands[2].type: REG = r0 ; operands[2].access: READ ; Registers read: r0 ; Registers modified: r0 ; Groups: IsARM HasV6
-
-!# issue 0 ARM operand groups 0x9a,0x8f,0xa0,0xe6 == ssat r8, #1, r10, lsl #31 ;
-!# CS_ARCH_ARM, CS_MODE_ARM, CS_OPT_DETAIL
-0x9a,0x8f,0xa0,0xe6 == ssat r8, #1, r10, lsl #0x1f ; op_count: 3 ; operands[0].type: REG = r8 ; operands[0].access: WRITE ; operands[1].type: IMM = 0x1 ; operands[1].access: READ ; operands[2].type: REG = r10 ; operands[2].access: READ ; Shift: 2 = 31 ; Registers read: r10 ; Registers modified: r8 ; Groups: IsARM HasV6
-
-!# issue 0 ARM operand groups 0x40,0x1b,0xf5,0xee == vcmp.f64 d17, #0 ;
-!# CS_ARCH_ARM, CS_MODE_ARM, CS_OPT_DETAIL
-0x40,0x1b,0xf5,0xee == vcmp.f64 d17, #0 ; op_count: 2 ; operands[0].type: REG = d17 ; operands[0].access: READ ; operands[1].type: IMM = 0x0 ; operands[1].access: READ ; Update-flags: True ; Registers read: d17 ; Registers modified: fpscr_nzcv ; Groups: HasVFP2 HasDPVFP
-
-!# issue 0 ARM operand groups 0x05,0xf0,0x2f,0xe3 == msr CPSR_fsxc, #5 ;
-!# CS_ARCH_ARM, CS_MODE_ARM, CS_OPT_DETAIL
-0x05,0xf0,0x2f,0xe3 == msr cpsr_fsxc, #5 ; op_count: 2 ; operands[0].type: CPSR = fsxc ; operands[0].type: MASK = 15 ; operands[0].access: WRITE ; operands[1].type: IMM = 0x5 ; operands[1].access: READ ; Update-flags: True ; Registers modified: cpsr ; Groups: IsARM
-
-!# issue 0 ARM operand groups 0xa4,0xf9,0xed,0x0b == vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:128]! ;
-!# CS_ARCH_ARM, CS_MODE_THUMB, CS_OPT_DETAIL
-0xa4,0xf9,0xed,0x0b == vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:0x80]! ; op_count: 5 ; operands[0].type: REG = d0 ; operands[0].neon_lane = 1 ; operands[0].access: READ | WRITE ; operands[1].type: REG = d2 ; operands[1].neon_lane = 1 ; operands[1].access: READ | WRITE ; operands[2].type: REG = d4 ; operands[2].neon_lane = 1 ; operands[2].access: READ | WRITE ; operands[3].type: REG = d6 ; operands[3].neon_lane = 1 ; operands[3].access: READ | WRITE ; operands[4].type: MEM ; operands[4].mem.base: REG = r4 ; operands[4].mem.align: 0x80 ; operands[4].access: READ | WRITE ; Write-back: True ; Registers read: d0 d2 d4 d6 r4 ; Registers modified: r4 d0 d2 d4 d6
-
-!# issue 0 ARM operand groups 0x42,0x03,0xb0,0xf3 == aesd.8 q0, q1 ;
-!# CS_ARCH_ARM, CS_MODE_ARM | CS_MODE_V8, CS_OPT_DETAIL
-0x42,0x03,0xb0,0xf3 == aesd.8 q0, q1 ; op_count: 2 ; operands[0].type: REG = q0 ; operands[0].access: READ | WRITE ; operands[1].type: REG = q1 ; operands[1].access: READ ; Write-back: True ; Registers read: q0 q1 ; Registers modified: q0 ; Groups: HasV8 HasAES
-
-!# issue 0 ARM operand groups 0x11,0x57,0x54,0xfc == mrrc2 p7, #1, r5, r4, c1 ;
-!# CS_ARCH_ARM, CS_MODE_ARM, CS_OPT_DETAIL
-0x11,0x57,0x54,0xfc == mrrc2 p7, #1, r5, r4, c1 ; op_count: 5 ; operands[0].type: P-IMM = 7 ; operands[0].access: READ ; operands[1].type: IMM = 0x1 ; operands[1].access: READ ; operands[2].type: REG = r5 ; operands[2].access: WRITE ; operands[3].type: REG = r4 ; operands[3].access: WRITE ; operands[4].type: C-IMM = 1 ; operands[4].access: READ ; Registers modified: r5 r4 ; Groups: IsARM PreV8
-
-!# issue 0 ARM operand groups 0xd3,0x2f,0x82,0xe6 == pkhtb r2, r2, r3, asr #31 ;
-!# CS_ARCH_ARM, CS_MODE_ARM, CS_OPT_DETAIL
-0xd3,0x2f,0x82,0xe6 == pkhtb r2, r2, r3, asr #0x1f ; op_count: 3 ; operands[0].type: REG = r2 ; operands[0].access: WRITE ; operands[1].type: REG = r2 ; operands[1].access: READ ; operands[2].type: REG = r3 ; operands[2].access: READ ; Shift: 1 = 31 ; Registers read: r2 r3 ; Registers modified: r2 ; Groups: IsARM HasV6
-
-!# issue 0 ARM operand groups 0x93,0x27,0x82,0xe6 == pkhbt r2, r2, r3, lsl #15 ;
-!# CS_ARCH_ARM, CS_MODE_ARM, CS_OPT_DETAIL
-0x93,0x27,0x82,0xe6 == pkhbt r2, r2, r3, lsl #0xf ; op_count: 3 ; operands[0].type: REG = r2 ; operands[0].access: WRITE ; operands[1].type: REG = r2 ; operands[1].access: READ ; operands[2].type: REG = r3 ; operands[2].access: READ ; Shift: 2 = 15 ; Registers read: r2 r3 ; Registers modified: r2 ; Groups: IsARM HasV6
-
-!# issue 0 ARM operand groups 0xb4,0x10,0xf0,0xe0 == ldrht r1, [r0], #4 ;
-!# CS_ARCH_ARM, CS_MODE_ARM, CS_OPT_DETAIL
-0xb4,0x10,0xf0,0xe0 == ldrht r1, [r0], #4 ; op_count: 2 ; operands[0].type: REG = r1 ; operands[0].access: WRITE ; operands[1].type: MEM ; operands[1].mem.base: REG = r0 ; operands[1].access: READ ; operands[1].mem.disp: 0x4 ; Write-back: True ; Registers read: r0 ; Registers modified: r0 r1 ; Groups: IsARM
-
-!# issue 0 ARM operand groups 0x2f,0xfa,0xa1,0xf3 == sxtb16 r3, r1, ror #16 ;
-!# CS_ARCH_ARM, CS_MODE_THUMB, CS_OPT_DETAIL
-0x2f,0xfa,0xa1,0xf3 == sxtb16 r3, r1, ror #16 ; op_count: 2 ; operands[0].type: REG = r3 ; operands[0].access: WRITE ; operands[1].type: REG = r1 ; operands[1].access: READ ; Shift: 4 = 16 ; Registers read: r1 ; Registers modified: r3 ; Groups: HasDSP IsThumb2
-
-!# issue 0 ARM operand groups 0x00,0x02,0x01,0xf1 == setend be ;
-!# CS_ARCH_ARM, CS_MODE_ARM, CS_OPT_DETAIL
-0x00,0x02,0x01,0xf1 == setend be ; op_count: 1 ; operands[0].type: SETEND = be ; Groups: IsARM
-
-!# issue 0 ARM operand groups 0xd0,0xe8,0xaf,0x0f == lda r0, [r0]
-!# CS_ARCH_ARM, CS_MODE_THUMB, CS_OPT_DETAIL
-0xd0,0xe8,0xaf,0x0f == lda r0, [r0] ; op_count: 2 ; operands[0].type: REG = r0 ; operands[0].access: WRITE ; operands[1].type: MEM ; operands[1].mem.base: REG = r0 ; operands[1].access: READ ; Registers read: r0 ; Registers modified: r0 ; Groups: IsThumb HasAcquireRelease
-
-!# issue 0 ARM operand groups 0xef,0xf3,0x11,0x85 == ldrhi pc, [r1, #-0x3ef]
-!# CS_ARCH_ARM, CS_MODE_ARM, CS_OPT_DETAIL
-0xef,0xf3,0x11,0x85 == ldrhi pc, [r1, #-0x3ef] ; op_count: 2 ; operands[0].type: REG = r15 ; operands[0].access: WRITE ; operands[1].type: MEM ; operands[1].mem.base: REG = r1 ; operands[1].mem.disp: 0x3ef ; operands[1].access: READ ; Code condition: 8 ; Registers read: cpsr r1 ; Registers modified: r15 ; Groups: IsARM jump
-
-!# issue 0 PPC operand groups 0x54,0x22,0xe0,0x06 == slwi r2, r1, 0x1c
-!# CS_ARCH_PPC, CS_MODE_32 | CS_MODE_BIG_ENDIAN, CS_OPT_DETAIL
-0x54,0x22,0xe0,0x06 == slwi r2, r1, 0x1c ; op_count: 3 ; operands[0].type: REG = r2 ; operands[1].type: REG = r1 ; operands[2].type: IMM = 0x1c
-
-!# issue 0 PPC operand groups 0x54,0x66,0xf0,0xbe == srwi r6, r3, 2
-!# CS_ARCH_PPC, CS_MODE_32 | CS_MODE_BIG_ENDIAN, CS_OPT_DETAIL
-0x54,0x66,0xf0,0xbe == srwi r6, r3, 2 ; op_count: 3 ; operands[0].type: REG = r6 ; operands[1].type: REG = r3 ; operands[2].type: IMM = 0x2
-
-!# issue 0 PPC operand groups 0x78,0x62,0x26,0xe4 == sldi r2, r3, 4
-!# CS_ARCH_PPC, CS_MODE_32 | CS_MODE_BIG_ENDIAN, CS_OPT_DETAIL
-0x78,0x62,0x26,0xe4 == sldi r2, r3, 4 ; op_count: 3 ; operands[0].type: REG = r2 ; operands[1].type: REG = r3 ; operands[2].type: IMM = 0x4
-
-!# issue 0 RISCV operand groups 0x37,0x34,0x00,0x00 == lui s0, 3
-!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL
-0x37,0x34,0x00,0x00 == lui s0, 3 ; op_count: 2 ; operands[0].type: REG = s0 ; operands[0].access: WRITE ; operands[1].type: IMM = 0x3 ; operands[1].access: READ
-
-!# issue 0 RISCV operand groups 0x97,0x82,0x00,0x00 == auipc t0, 8
-!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL
-0x97,0x82,0x00,0x00 == auipc t0, 8 ; op_count: 2 ; operands[0].type: REG = t0 ; operands[0].access: WRITE ; operands[1].type: IMM = 0x8 ; operands[1].access: READ
-
-!# issue 0 RISCV operand groups 0xef,0x00,0x80,0x00 == jal 8
-!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL
-0xef,0x00,0x80,0x00 == jal 8 ; op_count: 1 ; operands[0].type: IMM = 0x8 ; operands[0].access: READ ; Groups: call
-
-!# issue 0 RISCV operand groups 0xef,0xf0,0x1f,0xff == jal -0x10
-!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL
-0xef,0xf0,0x1f,0xff == jal -0x10 ; op_count: 1 ; operands[0].type: IMM = 0xfffffff0 ; operands[0].access: READ ; Groups: call
-
-!# issue 0 RISCV operand groups 0xe7,0x00,0x45,0x00 == jalr ra, a0, 4
-!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL
-0xe7,0x00,0x45,0x00 == jalr ra, a0, 4 ; op_count: 3 ; operands[0].type: REG = ra ; operands[0].access: WRITE ; operands[1].type: REG = a0 ; operands[1].access: READ ; operands[2].type: IMM = 0x4 ; operands[2].access: READ ; Groups: call
-
-!# issue 0 RISCV operand groups 0xe7,0x00,0xc0,0xff == jalr ra, zero, -4
-!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL
-0xe7,0x00,0xc0,0xff == jalr ra, zero, -4 ; op_count: 3 ; operands[0].type: REG = ra ; operands[0].access: WRITE ; operands[1].type: REG = zero ; operands[1].access: READ ; operands[2].type: IMM = 0xfffffffc ; operands[2].access: READ ; Groups: call
-
-!# issue 0 RISCV operand groups 0x63,0x05,0x41,0x00 == beq sp, tp, 0xa
-!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL
-0x63,0x05,0x41,0x00 == beq sp, tp, 0xa ; op_count: 3 ; operands[0].type: REG = sp ; operands[0].access: READ ; operands[1].type: REG = tp ; operands[1].access: READ ; operands[2].type: IMM = 0xa ; operands[2].access: READ ; Groups: branch_relative jump
-
-!# issue 0 RISCV operand groups 0xe3,0x9d,0x61,0xfe == bne gp, t1, -6
-!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL
-0xe3,0x9d,0x61,0xfe == bne gp, t1, -6 ; op_count: 3 ; operands[0].type: REG = gp ; operands[0].access: READ ; operands[1].type: REG = t1 ; operands[1].access: READ ; operands[2].type: IMM = 0xfffffffa ; operands[2].access: READ ; Groups: branch_relative jump
-
-!# issue 0 RISCV operand groups 0x63,0xca,0x93,0x00 == blt t2, s1, 0x14
-!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL
-0x63,0xca,0x93,0x00 == blt t2, s1, 0x14 ; op_count: 3 ; operands[0].type: REG = t2 ; operands[0].access: READ ; operands[1].type: REG = s1 ; operands[1].access: READ ; operands[2].type: IMM = 0x14 ; operands[2].access: READ ; Groups: branch_relative jump
-
-!# issue 0 RISCV operand groups 0x63,0x53,0xb5,0x00 == bge a0, a1, 6
-!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL
-0x63,0x53,0xb5,0x00 == bge a0, a1, 6 ; op_count: 3 ; operands[0].type: REG = a0 ; operands[0].access: READ ; operands[1].type: REG = a1 ; operands[1].access: READ ; operands[2].type: IMM = 0x6 ; operands[2].access: READ ; Groups: branch_relative jump
-
-!# issue 0 RISCV operand groups 0x63,0x65,0xd6,0x00 == bltu a2, a3, 0xa
-!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL
-0x63,0x65,0xd6,0x00 == bltu a2, a3, 0xa ; op_count: 3 ; operands[0].type: REG = a2 ; operands[0].access: READ ; operands[1].type: REG = a3 ; operands[1].access: READ ; operands[2].type: IMM = 0xa ; operands[2].access: READ ; Groups: branch_relative jump
-
-!# issue 0 RISCV operand groups 0x63,0x76,0xf7,0x00 == bgeu a4, a5, 0xc
-!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL
-0x63,0x76,0xf7,0x00 == bgeu a4, a5, 0xc ; op_count: 3 ; operands[0].type: REG = a4 ; operands[0].access: READ ; operands[1].type: REG = a5 ; operands[1].access: READ ; operands[2].type: IMM = 0xc ; operands[2].access: READ ; Groups: branch_relative jump
-
-!# issue 0 RISCV operand groups 0x03,0x88,0x18,0x00 == lb a6, 1(a7)
-!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL
-0x03,0x88,0x18,0x00 == lb a6, 1(a7) ; op_count: 2 ; operands[0].type: REG = a6 ; operands[0].access: WRITE ; operands[1].type: MEM ; operands[1].mem.base: REG = a7 ; operands[1].mem.disp: 0x1 ; operands[1].access: READ
-
-!# issue 0 RISCV operand groups 0x03,0x99,0x49,0x00 == lh s2, 4(s3)
-!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL
-0x03,0x99,0x49,0x00 == lh s2, 4(s3) ; op_count: 2 ; operands[0].type: REG = s2 ; operands[0].access: WRITE ; operands[1].type: MEM ; operands[1].mem.base: REG = s3 ; operands[1].mem.disp: 0x4 ; operands[1].access: READ
-
-!# issue 0 RISCV operand groups 0x03,0xaa,0x6a,0x00 == lw s4, 6(s5)
-!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL
-0x03,0xaa,0x6a,0x00 == lw s4, 6(s5) ; op_count: 2 ; operands[0].type: REG = s4 ; operands[0].access: WRITE ; operands[1].type: MEM ; operands[1].mem.base: REG = s5 ; operands[1].mem.disp: 0x6 ; operands[1].access: READ
-
-!# issue 0 RISCV operand groups 0x03,0xcb,0x2b,0x01 == lbu s6, 0x12(s7)
-!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL
-0x03,0xcb,0x2b,0x01 == lbu s6, 0x12(s7) ; op_count: 2 ; operands[0].type: REG = s6 ; operands[0].access: WRITE ; operands[1].type: MEM ; operands[1].mem.base: REG = s7 ; operands[1].mem.disp: 0x12 ; operands[1].access: READ
-
-!# issue 0 RISCV operand groups 0x03,0xdc,0x8c,0x01 == lhu s8, 0x18(s9)
-!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL
-0x03,0xdc,0x8c,0x01 == lhu s8, 0x18(s9) ; op_count: 2 ; operands[0].type: REG = s8 ; operands[0].access: WRITE ; operands[1].type: MEM ; operands[1].mem.base: REG = s9 ; operands[1].mem.disp: 0x18 ; operands[1].access: READ
-
-!# issue 0 RISCV operand groups 0x23,0x86,0xad,0x03 == sb s10, 0x2c(s11)
-!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL
-0x23,0x86,0xad,0x03 == sb s10, 0x2c(s11) ; op_count: 2 ; operands[0].type: REG = s10 ; operands[0].access: READ ; operands[1].type: MEM ; operands[1].mem.base: REG = s11 ; operands[1].mem.disp: 0x2c ; operands[1].access: WRITE
-
-!# issue 0 RISCV operand groups 0x23,0x9a,0xce,0x03 == sh t3, 0x34(t4)
-!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL
-0x23,0x9a,0xce,0x03 == sh t3, 0x34(t4) ; op_count: 2 ; operands[0].type: REG = t3 ; operands[0].access: READ ; operands[1].type: MEM ; operands[1].mem.base: REG = t4 ; operands[1].mem.disp: 0x34 ; operands[1].access: WRITE
-
-!# issue 0 RISCV operand groups 0x23,0x8f,0xef,0x01 == sb t5, 0x1e(t6)
-!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL
-0x23,0x8f,0xef,0x01 == sb t5, 0x1e(t6) ; op_count: 2 ; operands[0].type: REG = t5 ; operands[0].access: READ ; operands[1].type: MEM ; operands[1].mem.base: REG = t6 ; operands[1].mem.disp: 0x1e ; operands[1].access: WRITE
-
-!# issue 0 RISCV operand groups 0x93,0x00,0xe0,0x00 == addi ra, zero, 0xe
-!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL
-0x93,0x00,0xe0,0x00 == addi ra, zero, 0xe ; op_count: 3 ; operands[0].type: REG = ra ; operands[0].access: WRITE ; operands[1].type: REG = zero ; operands[1].access: READ ; operands[2].type: IMM = 0xe ; operands[2].access: READ
-
-!# issue 0 RISCV operand groups 0x13,0xa1,0x01,0x01 == slti sp, gp, 0x10
-!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL
-0x13,0xa1,0x01,0x01 == slti sp, gp, 0x10 ; op_count: 3 ; operands[0].type: REG = sp ; operands[0].access: WRITE ; operands[1].type: REG = gp ; operands[1].access: READ ; operands[2].type: IMM = 0x10 ; operands[2].access: READ
-
-!# issue 0 RISCV operand groups 0x13,0xb2,0x02,0x7d == sltiu tp, t0, 0x7d0
-!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL
-0x13,0xb2,0x02,0x7d == sltiu tp, t0, 0x7d0 ; op_count: 3 ; operands[0].type: REG = tp ; operands[0].access: WRITE ; operands[1].type: REG = t0 ; operands[1].access: READ ; operands[2].type: IMM = 0x7d0 ; operands[2].access: READ
-
-!# issue 0 RISCV operand groups 0x13,0xc3,0x03,0xdd == xori t1, t2, -0x230
-!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL
-0x13,0xc3,0x03,0xdd == xori t1, t2, -0x230 ; op_count: 3 ; operands[0].type: REG = t1 ; operands[0].access: WRITE ; operands[1].type: REG = t2 ; operands[1].access: READ ; operands[2].type: IMM = 0xfffffdd0 ; operands[2].access: READ
-
-!# issue 0 RISCV operand groups 0x13,0xe4,0xc4,0x12 == ori s0, s1, 0x12c
-!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL
-0x13,0xe4,0xc4,0x12 == ori s0, s1, 0x12c ; op_count: 3 ; operands[0].type: REG = s0 ; operands[0].access: WRITE ; operands[1].type: REG = s1 ; operands[1].access: READ ; operands[2].type: IMM = 0x12c ; operands[2].access: READ
-
-!# issue 0 RISCV operand groups 0x13,0xf5,0x85,0x0c == andi a0, a1, 0xc8
-!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL
-0x13,0xf5,0x85,0x0c == andi a0, a1, 0xc8 ; op_count: 3 ; operands[0].type: REG = a0 ; operands[0].access: WRITE ; operands[1].type: REG = a1 ; operands[1].access: READ ; operands[2].type: IMM = 0xc8 ; operands[2].access: READ
-
-!# issue 0 RISCV operand groups 0x13,0x96,0xe6,0x01 == slli a2, a3, 0x1e
-!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL
-0x13,0x96,0xe6,0x01 == slli a2, a3, 0x1e ; op_count: 3 ; operands[0].type: REG = a2 ; operands[0].access: WRITE ; operands[1].type: REG = a3 ; operands[1].access: READ ; operands[2].type: IMM = 0x1e ; operands[2].access: READ
-
-!# issue 0 RISCV operand groups 0x13,0xd7,0x97,0x01 == srli a4, a5, 0x19
-!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL
-0x13,0xd7,0x97,0x01 == srli a4, a5, 0x19 ; op_count: 3 ; operands[0].type: REG = a4 ; operands[0].access: WRITE ; operands[1].type: REG = a5 ; operands[1].access: READ ; operands[2].type: IMM = 0x19 ; operands[2].access: READ
-
-!# issue 0 RISCV operand groups 0x13,0xd8,0xf8,0x40 == srai a6, a7, 0xf
-!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL
-0x13,0xd8,0xf8,0x40 == srai a6, a7, 0xf ; op_count: 3 ; operands[0].type: REG = a6 ; operands[0].access: WRITE ; operands[1].type: REG = a7 ; operands[1].access: READ ; operands[2].type: IMM = 0xf ; operands[2].access: READ
-
-!# issue 0 RISCV operand groups 0x33,0x89,0x49,0x01 == add s2, s3, s4
-!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL
-0x33,0x89,0x49,0x01 == add s2, s3, s4 ; op_count: 3 ; operands[0].type: REG = s2 ; operands[0].access: WRITE ; operands[1].type: REG = s3 ; operands[1].access: READ ; operands[2].type: REG = s4 ; operands[2].access: READ
-
-!# issue 0 RISCV operand groups 0xb3,0x0a,0x7b,0x41 == sub s5, s6, s7
-!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL
-0xb3,0x0a,0x7b,0x41 == sub s5, s6, s7 ; op_count: 3 ; operands[0].type: REG = s5 ; operands[0].access: WRITE ; operands[1].type: REG = s6 ; operands[1].access: READ ; operands[2].type: REG = s7 ; operands[2].access: READ
-
-!# issue 0 RISCV operand groups 0x33,0xac,0xac,0x01 == slt s8, s9, s10
-!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL
-0x33,0xac,0xac,0x01 == slt s8, s9, s10 ; op_count: 3 ; operands[0].type: REG = s8 ; operands[0].access: WRITE ; operands[1].type: REG = s9 ; operands[1].access: READ ; operands[2].type: REG = s10 ; operands[2].access: READ
-
-!# issue 0 RISCV operand groups 0xb3,0x3d,0xde,0x01 == sltu s11, t3, t4
-!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL
-0xb3,0x3d,0xde,0x01 == sltu s11, t3, t4 ; op_count: 3 ; operands[0].type: REG = s11 ; operands[0].access: WRITE ; operands[1].type: REG = t3 ; operands[1].access: READ ; operands[2].type: REG = t4 ; operands[2].access: READ
-
-!# issue 0 RISCV operand groups 0x33,0xd2,0x62,0x40 == sra tp, t0, t1
-!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL
-0x33,0xd2,0x62,0x40 == sra tp, t0, t1 ; op_count: 3 ; operands[0].type: REG = tp ; operands[0].access: WRITE ; operands[1].type: REG = t0 ; operands[1].access: READ ; operands[2].type: REG = t1 ; operands[2].access: READ
-
-!# issue 0 RISCV operand groups 0xb3,0x43,0x94,0x00 == xor t2, s0, s1
-!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL
-0xb3,0x43,0x94,0x00 == xor t2, s0, s1 ; op_count: 3 ; operands[0].type: REG = t2 ; operands[0].access: WRITE ; operands[1].type: REG = s0 ; operands[1].access: READ ; operands[2].type: REG = s1 ; operands[2].access: READ
-
-!# issue 0 RISCV operand groups 0x33,0xe5,0xc5,0x00 == or a0, a1, a2
-!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL
-0x33,0xe5,0xc5,0x00 == or a0, a1, a2 ; op_count: 3 ; operands[0].type: REG = a0 ; operands[0].access: WRITE ; operands[1].type: REG = a1 ; operands[1].access: READ ; operands[2].type: REG = a2 ; operands[2].access: READ
-
-!# issue 0 RISCV operand groups 0xb3,0x76,0xf7,0x00 == and a3, a4, a5
-!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL
-0xb3,0x76,0xf7,0x00 == and a3, a4, a5 ; op_count: 3 ; operands[0].type: REG = a3 ; operands[0].access: WRITE ; operands[1].type: REG = a4 ; operands[1].access: READ ; operands[2].type: REG = a5 ; operands[2].access: READ
-
-!# issue 0 RISCV operand groups 0xb3,0x54,0x39,0x01 == srl s1, s2, s3
-!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL
-0xb3,0x54,0x39,0x01 == srl s1, s2, s3 ; op_count: 3 ; operands[0].type: REG = s1 ; operands[0].access: WRITE ; operands[1].type: REG = s2 ; operands[1].access: READ ; operands[2].type: REG = s3 ; operands[2].access: READ
-
-!# issue 0 RISCV operand groups 0xb3,0x50,0x31,0x00 == srl ra, sp, gp
-!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL
-0xb3,0x50,0x31,0x00 == srl ra, sp, gp ; op_count: 3 ; operands[0].type: REG = ra ; operands[0].access: WRITE ; operands[1].type: REG = sp ; operands[1].access: READ ; operands[2].type: REG = gp ; operands[2].access: READ
-
-!# issue 0 RISCV operand groups 0x33,0x9f,0x0f,0x00 == sll t5, t6, zero
-!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL
-0x33,0x9f,0x0f,0x00 == sll t5, t6, zero ; op_count: 3 ; operands[0].type: REG = t5 ; operands[0].access: WRITE ; operands[1].type: REG = t6 ; operands[1].access: READ ; operands[2].type: REG = zero ; operands[2].access: READ
-
-!# issue 0 RISCV operand groups 0x73,0x15,0x04,0xb0 == csrrw a0, mcycle, s0
-!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL
-0x73,0x15,0x04,0xb0 == csrrw a0, mcycle, s0 ; op_count: 2 ; operands[0].type: REG = a0 ; operands[0].access: WRITE ; operands[1].type: REG = s0 ; operands[1].access: READ
-
-!# issue 0 RISCV operand groups 0xf3,0x56,0x00,0x10 == csrrwi a3, sstatus, 0
-!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL
-0xf3,0x56,0x00,0x10 == csrrwi a3, sstatus, 0 ; op_count: 2 ; operands[0].type: REG = a3 ; operands[0].access: WRITE ; operands[1].type: IMM = 0x0 ; operands[1].access: READ
-
-!# issue 0 RISCV operand groups 0x33,0x05,0x7b,0x03 == mul a0, s6, s7
-!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL
-0x33,0x05,0x7b,0x03 == mul a0, s6, s7 ; op_count: 3 ; operands[0].type: REG = a0 ; operands[0].access: WRITE ; operands[1].type: REG = s6 ; operands[1].access: READ ; operands[2].type: REG = s7 ; operands[2].access: READ ; Groups: hasStdExtM
-
-!# issue 0 RISCV operand groups 0xb3,0x45,0x9c,0x03 == div a1, s8, s9
-!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL
-0xb3,0x45,0x9c,0x03 == div a1, s8, s9 ; op_count: 3 ; operands[0].type: REG = a1 ; operands[0].access: WRITE ; operands[1].type: REG = s8 ; operands[1].access: READ ; operands[2].type: REG = s9 ; operands[2].access: READ ; Groups: hasStdExtM
-
-!# issue 0 RISCV operand groups 0x33,0x66,0xbd,0x03 == rem a2, s10, s11
-!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL
-0x33,0x66,0xbd,0x03 == rem a2, s10, s11 ; op_count: 3 ; operands[0].type: REG = a2 ; operands[0].access: WRITE ; operands[1].type: REG = s10 ; operands[1].access: READ ; operands[2].type: REG = s11 ; operands[2].access: READ ; Groups: hasStdExtM
-
-!# issue 0 RISCV operand groups 0x2f,0xa4,0x02,0x10 == lr.w s0, (t0)
-!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL
-0x2f,0xa4,0x02,0x10 == lr.w s0, (t0) ; op_count: 2 ; operands[0].type: REG = s0 ; operands[0].access: WRITE ; operands[1].type: MEM ; operands[1].mem.base: REG = t0 ; operands[1].access: READ ; Groups: hasStdExtA
-
-!# issue 0 RISCV operand groups 0xaf,0x23,0x65,0x18 == sc.w t2, t1, (a0)
-!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL
-0xaf,0x23,0x65,0x18 == sc.w t2, t1, (a0) ; op_count: 3 ; operands[0].type: REG = t2 ; operands[0].access: WRITE ; operands[1].type: REG = t1 ; operands[1].access: READ ; operands[2].type: MEM ; operands[2].mem.base: REG = a0 ; operands[2].access: WRITE ; Groups: hasStdExtA
-
-!# issue 0 RISCV operand groups 0x2f,0x27,0x2f,0x01 == amoadd.w a4, s2, (t5)
-!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL
-0x2f,0x27,0x2f,0x01 == amoadd.w a4, s2, (t5) ; op_count: 3 ; operands[0].type: REG = a4 ; operands[0].access: WRITE ; operands[1].type: REG = s2 ; operands[1].access: READ ; operands[2].type: MEM ; operands[2].mem.base: REG = t5 ; operands[2].access: READ | WRITE ; Groups: hasStdExtA
-
-!# issue 0 RISCV operand groups 0x43,0xf0,0x20,0x18 == fmadd.s ft0, ft1, ft2, ft3
-!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL
-0x43,0xf0,0x20,0x18 == fmadd.s ft0, ft1, ft2, ft3 ; op_count: 4 ; operands[0].type: REG = ft0 ; operands[0].access: WRITE ; operands[1].type: REG = ft1 ; operands[1].access: READ ; operands[2].type: REG = ft2 ; operands[2].access: READ ; operands[3].type: REG = ft3 ; operands[3].access: READ ; Groups: hasStdExtF
-
-!# issue 0 RISCV operand groups 0xd3,0x72,0x73,0x00 == fadd.s ft5, ft6, ft7
-!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL
-0xd3,0x72,0x73,0x00 == fadd.s ft5, ft6, ft7 ; op_count: 3 ; operands[0].type: REG = ft5 ; operands[0].access: WRITE ; operands[1].type: REG = ft6 ; operands[1].access: READ ; operands[2].type: REG = ft7 ; operands[2].access: READ ; Groups: hasStdExtF
-
-!# issue 0 RISCV operand groups 0x53,0xf4,0x04,0x58 == fsqrt.s fs0, fs1
-!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL
-0x53,0xf4,0x04,0x58 == fsqrt.s fs0, fs1 ; op_count: 2 ; operands[0].type: REG = fs0 ; operands[0].access: WRITE ; operands[1].type: REG = fs1 ; operands[1].access: READ ; Groups: hasStdExtF
-
-!# issue 0 RISCV operand groups 0x53,0x85,0xc5,0x28 == fmin.s fa0, fa1, fa2
-!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL
-0x53,0x85,0xc5,0x28 == fmin.s fa0, fa1, fa2 ; op_count: 3 ; operands[0].type: REG = fa0 ; operands[0].access: WRITE ; operands[1].type: REG = fa1 ; operands[1].access: READ ; operands[2].type: REG = fa2 ; operands[2].access: READ ; Groups: hasStdExtF
-
-!# issue 0 RISCV operand groups 0x53,0x2e,0xde,0xa1 == feq.s t3, ft8, ft9
-!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL
-0x53,0x2e,0xde,0xa1 == feq.s t3, ft8, ft9 ; op_count: 3 ; operands[0].type: REG = t3 ; operands[0].access: WRITE ; operands[1].type: REG = ft8 ; operands[1].access: READ ; operands[2].type: REG = ft9 ; operands[2].access: READ ; Groups: hasStdExtF
-
-!# issue 0 RISCV operand groups 0xd3,0x84,0x05,0xf0 == fmv.w.x fs1, a1
-!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL
-0xd3,0x84,0x05,0xf0 == fmv.w.x fs1, a1 ; op_count: 2 ; operands[0].type: REG = fs1 ; operands[0].access: WRITE ; operands[1].type: REG = a1 ; operands[1].access: READ ; Groups: hasStdExtF
-
-!# issue 0 RISCV operand groups 0x53,0x06,0x05,0xe0 == fmv.x.w a2, fa0
-!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL
-0x53,0x06,0x05,0xe0 == fmv.x.w a2, fa0 ; op_count: 2 ; operands[0].type: REG = a2 ; operands[0].access: WRITE ; operands[1].type: REG = fa0 ; operands[1].access: READ ; Groups: hasStdExtF
-
-!# issue 0 RISCV operand groups 0x53,0x75,0x00,0xc0 == fcvt.w.s a0, ft0
-!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL
-0x53,0x75,0x00,0xc0 == fcvt.w.s a0, ft0 ; op_count: 2 ; operands[0].type: REG = a0 ; operands[0].access: WRITE ; operands[1].type: REG = ft0 ; operands[1].access: READ ; Groups: hasStdExtF
-
-!# issue 0 RISCV operand groups 0xd3,0xf0,0x05,0xd0 == fcvt.s.w ft1, a1
-!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL
-0xd3,0xf0,0x05,0xd0 == fcvt.s.w ft1, a1 ; op_count: 2 ; operands[0].type: REG = ft1 ; operands[0].access: WRITE ; operands[1].type: REG = a1 ; operands[1].access: READ ; Groups: hasStdExtF
-
-!# issue 0 RISCV operand groups 0xd3,0x15,0x08,0xe0 == fclass.s a1, fa6
-!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL
-0xd3,0x15,0x08,0xe0 == fclass.s a1, fa6 ; op_count: 2 ; operands[0].type: REG = a1 ; operands[0].access: WRITE ; operands[1].type: REG = fa6 ; operands[1].access: READ ; Groups: hasStdExtF
-
-!# issue 0 RISCV operand groups 0x87,0xaa,0x75,0x00 == flw fs5, 7(a1)
-!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL
-0x87,0xaa,0x75,0x00 == flw fs5, 7(a1) ; op_count: 2 ; operands[0].type: REG = fs5 ; operands[0].access: WRITE ; operands[1].type: MEM ; operands[1].mem.base: REG = a1 ; operands[1].mem.disp: 0x7 ; operands[1].access: READ ; Groups: hasStdExtF
-
-!# issue 0 RISCV operand groups 0x27,0x27,0x66,0x01 == fsw fs6, 0xe(a2)
-!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL
-0x27,0x27,0x66,0x01 == fsw fs6, 0xe(a2) ; op_count: 2 ; operands[0].type: REG = fs6 ; operands[0].access: READ ; operands[1].type: MEM ; operands[1].mem.base: REG = a2 ; operands[1].mem.disp: 0xe ; operands[1].access: WRITE ; Groups: hasStdExtF
-
-!# issue 0 RISCV operand groups 0x43,0xf0,0x20,0x1a == fmadd.d ft0, ft1, ft2, ft3
-!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL
-0x43,0xf0,0x20,0x1a == fmadd.d ft0, ft1, ft2, ft3 ; op_count: 4 ; operands[0].type: REG = ft0 ; operands[0].access: WRITE ; operands[1].type: REG = ft1 ; operands[1].access: READ ; operands[2].type: REG = ft2 ; operands[2].access: READ ; operands[3].type: REG = ft3 ; operands[3].access: READ ; Groups: hasStdExtD
-
-!# issue 0 RISCV operand groups 0xd3,0x72,0x73,0x02 == fadd.d ft5, ft6, ft7
-!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL
-0xd3,0x72,0x73,0x02 == fadd.d ft5, ft6, ft7 ; op_count: 3 ; operands[0].type: REG = ft5 ; operands[0].access: WRITE ; operands[1].type: REG = ft6 ; operands[1].access: READ ; operands[2].type: REG = ft7 ; operands[2].access: READ ; Groups: hasStdExtD
-
-!# issue 0 RISCV operand groups 0x53,0xf4,0x04,0x5a == fsqrt.d fs0, fs1
-!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL
-0x53,0xf4,0x04,0x5a == fsqrt.d fs0, fs1 ; op_count: 2 ; operands[0].type: REG = fs0 ; operands[0].access: WRITE ; operands[1].type: REG = fs1 ; operands[1].access: READ ; Groups: hasStdExtD
-
-!# issue 0 RISCV operand groups 0x53,0x85,0xc5,0x2a == fmin.d fa0, fa1, fa2
-!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL
-0x53,0x85,0xc5,0x2a == fmin.d fa0, fa1, fa2 ; op_count: 3 ; operands[0].type: REG = fa0 ; operands[0].access: WRITE ; operands[1].type: REG = fa1 ; operands[1].access: READ ; operands[2].type: REG = fa2 ; operands[2].access: READ ; Groups: hasStdExtD
-
-!# issue 0 RISCV operand groups 0x53,0x2e,0xde,0xa3 == feq.d t3, ft8, ft9
-!# CS_ARCH_RISCV, CS_MODE_RISCV32, CS_OPT_DETAIL
-0x53,0x2e,0xde,0xa3 == feq.d t3, ft8, ft9 ; op_count: 3 ; operands[0].type: REG = t3 ; operands[0].access: WRITE ; operands[1].type: REG = ft8 ; operands[1].access: READ ; operands[2].type: REG = ft9 ; operands[2].access: READ ; Groups: hasStdExtD
-
-!# issue 0 RISCV operand groups 0x13,0x04,0xa8,0x7a == addi s0, a6, 0x7aa
-!# CS_ARCH_RISCV, CS_MODE_RISCV64, CS_OPT_DETAIL
-0x13,0x04,0xa8,0x7a == addi s0, a6, 0x7aa ; op_count: 3 ; operands[0].type: REG = s0 ; operands[0].access: WRITE ; operands[1].type: REG = a6 ; operands[1].access: READ ; operands[2].type: IMM = 0x7aa ; operands[2].access: READ
-
-!# issue 0 RISCV operand groups 0xbb,0x07,0x9c,0x02 == mulw a5, s8, s1
-!# CS_ARCH_RISCV, CS_MODE_RISCV64, CS_OPT_DETAIL
-0xbb,0x07,0x9c,0x02 == mulw a5, s8, s1 ; op_count: 3 ; operands[0].type: REG = a5 ; operands[0].access: WRITE ; operands[1].type: REG = s8 ; operands[1].access: READ ; operands[2].type: REG = s1 ; operands[2].access: READ ; Groups: hasStdExtM isrv64
-
-!# issue 0 RISCV operand groups 0xbb,0x40,0x5d,0x02 == divw ra, s10, t0
-!# CS_ARCH_RISCV, CS_MODE_RISCV64, CS_OPT_DETAIL
-0xbb,0x40,0x5d,0x02 == divw ra, s10, t0 ; op_count: 3 ; operands[0].type: REG = ra ; operands[0].access: WRITE ; operands[1].type: REG = s10 ; operands[1].access: READ ; operands[2].type: REG = t0 ; operands[2].access: READ ; Groups: hasStdExtM isrv64
-
-!# issue 0 RISCV operand groups 0x3b,0x63,0xb7,0x03 == remw t1, a4, s11
-!# CS_ARCH_RISCV, CS_MODE_RISCV64, CS_OPT_DETAIL
-0x3b,0x63,0xb7,0x03 == remw t1, a4, s11 ; op_count: 3 ; operands[0].type: REG = t1 ; operands[0].access: WRITE ; operands[1].type: REG = a4 ; operands[1].access: READ ; operands[2].type: REG = s11 ; operands[2].access: READ ; Groups: hasStdExtM isrv64
-
-!# issue 0 RISCV operand groups 0x2f,0xb4,0x02,0x10 == lr.d s0, (t0)
-!# CS_ARCH_RISCV, CS_MODE_RISCV64, CS_OPT_DETAIL
-0x2f,0xb4,0x02,0x10 == lr.d s0, (t0) ; op_count: 2 ; operands[0].type: REG = s0 ; operands[0].access: WRITE ; operands[1].type: MEM ; operands[1].mem.base: REG = t0 ; operands[1].access: READ ; Groups: hasStdExtA isrv64
-
-!# issue 0 RISCV operand groups 0xaf,0x33,0x65,0x18 == sc.d t2, t1, (a0)
-!# CS_ARCH_RISCV, CS_MODE_RISCV64, CS_OPT_DETAIL
-0xaf,0x33,0x65,0x18 == sc.d t2, t1, (a0) ; op_count: 3 ; operands[0].type: REG = t2 ; operands[0].access: WRITE ; operands[1].type: REG = t1 ; operands[1].access: READ ; operands[2].type: MEM ; operands[2].mem.base: REG = a0 ; operands[2].access: WRITE ; Groups: hasStdExtA isrv64
-
-!# issue 0 RISCV operand groups 0x2f,0x37,0x2f,0x01 == amoadd.d a4, s2, (t5)
-!# CS_ARCH_RISCV, CS_MODE_RISCV64, CS_OPT_DETAIL
-0x2f,0x37,0x2f,0x01 == amoadd.d a4, s2, (t5) ; op_count: 3 ; operands[0].type: REG = a4 ; operands[0].access: WRITE ; operands[1].type: REG = s2 ; operands[1].access: READ ; operands[2].type: MEM ; operands[2].mem.base: REG = t5 ; operands[2].access: READ | WRITE ; Groups: hasStdExtA isrv64
-
-!# issue 0 RISCV operand groups 0x53,0x75,0x20,0xc0 == fcvt.l.s a0, ft0
-!# CS_ARCH_RISCV, CS_MODE_RISCV64, CS_OPT_DETAIL
-0x53,0x75,0x20,0xc0 == fcvt.l.s a0, ft0 ; op_count: 2 ; operands[0].type: REG = a0 ; operands[0].access: WRITE ; operands[1].type: REG = ft0 ; operands[1].access: READ ; Groups: hasStdExtF isrv64
-
-!# issue 0 RISCV operand groups 0xd3,0xf0,0x25,0xd0 == fcvt.s.l ft1, a1
-!# CS_ARCH_RISCV, CS_MODE_RISCV64, CS_OPT_DETAIL
-0xd3,0xf0,0x25,0xd0 == fcvt.s.l ft1, a1 ; op_count: 2 ; operands[0].type: REG = ft1 ; operands[0].access: WRITE ; operands[1].type: REG = a1 ; operands[1].access: READ ; Groups: hasStdExtF isrv64
-
-!# issue 0 RISCV operand groups 0xd3,0x84,0x05,0xf2 == fmv.d.x fs1, a1
-!# CS_ARCH_RISCV, CS_MODE_RISCV64, CS_OPT_DETAIL
-0xd3,0x84,0x05,0xf2 == fmv.d.x fs1, a1 ; op_count: 2 ; operands[0].type: REG = fs1 ; operands[0].access: WRITE ; operands[1].type: REG = a1 ; operands[1].access: READ ; Groups: hasStdExtD isrv64
-
-!# issue 0 RISCV operand groups 0x53,0x06,0x05,0xe2 == fmv.x.d a2, fa0
-!# CS_ARCH_RISCV, CS_MODE_RISCV64, CS_OPT_DETAIL
-0x53,0x06,0x05,0xe2 == fmv.x.d a2, fa0 ; op_count: 2 ; operands[0].type: REG = a2 ; operands[0].access: WRITE ; operands[1].type: REG = fa0 ; operands[1].access: READ ; Groups: hasStdExtD isrv64
-
-!# issue 0 RISCV operand groups 0x53,0x75,0x00,0xc2 == fcvt.w.d a0, ft0
-!# CS_ARCH_RISCV, CS_MODE_RISCV64, CS_OPT_DETAIL
-0x53,0x75,0x00,0xc2 == fcvt.w.d a0, ft0 ; op_count: 2 ; operands[0].type: REG = a0 ; operands[0].access: WRITE ; operands[1].type: REG = ft0 ; operands[1].access: READ ; Groups: hasStdExtD
-
-!# issue 0 RISCV operand groups 0xd3,0x80,0x05,0xd2 == fcvt.d.w ft1, a1
-!# CS_ARCH_RISCV, CS_MODE_RISCV64, CS_OPT_DETAIL
-0xd3,0x80,0x05,0xd2 == fcvt.d.w ft1, a1 ; op_count: 2 ; operands[0].type: REG = ft1 ; operands[0].access: WRITE ; operands[1].type: REG = a1 ; operands[1].access: READ ; Groups: hasStdExtD
-
-!# issue 0 RISCV operand groups 0xd3,0x15,0x08,0xe2 == fclass.d a1, fa6
-!# CS_ARCH_RISCV, CS_MODE_RISCV64, CS_OPT_DETAIL
-0xd3,0x15,0x08,0xe2 == fclass.d a1, fa6 ; op_count: 2 ; operands[0].type: REG = a1 ; operands[0].access: WRITE ; operands[1].type: REG = fa6 ; operands[1].access: READ ; Groups: hasStdExtD
-
-!# issue 0 RISCV operand groups 0x87,0xba,0x75,0x00 == fld fs5, 7(a1)
-!# CS_ARCH_RISCV, CS_MODE_RISCV64, CS_OPT_DETAIL
-0x87,0xba,0x75,0x00 == fld fs5, 7(a1) ; op_count: 2 ; operands[0].type: REG = fs5 ; operands[0].access: WRITE ; operands[1].type: MEM ; operands[1].mem.base: REG = a1 ; operands[1].mem.disp: 0x7 ; operands[1].access: READ ; Groups: hasStdExtD
-
-!# issue 0 RISCV operand groups 0x27,0x37,0x66,0x01 == fsd fs6, 0xe(a2)
-!# CS_ARCH_RISCV, CS_MODE_RISCV64, CS_OPT_DETAIL
-0x27,0x37,0x66,0x01 == fsd fs6, 0xe(a2) ; op_count: 2 ; operands[0].type: REG = fs6 ; operands[0].access: READ ; operands[1].type: MEM ; operands[1].mem.base: REG = a2 ; operands[1].mem.disp: 0xe ; operands[1].access: WRITE ; Groups: hasStdExtD
-
-!# issue 0 RISCV operand groups 0xe8,0x1f == c.addi4spn a0, sp, 0x3fc
-!# CS_ARCH_RISCV, CS_MODE_RISCVC, CS_OPT_DETAIL
-0xe8,0x1f == c.addi4spn a0, sp, 0x3fc ; op_count: 3 ; operands[0].type: REG = a0 ; operands[0].access: WRITE ; operands[1].type: REG = sp ; operands[1].access: READ ; operands[2].type: IMM = 0x3fc ; operands[2].access: READ ; Groups: hasStdExtC
-
-!# issue 0 RISCV operand groups 0x7d,0x61 == c.addi16sp sp, 0x1f0
-!# CS_ARCH_RISCV, CS_MODE_RISCVC, CS_OPT_DETAIL
-0x7d,0x61 == c.addi16sp sp, 0x1f0 ; op_count: 2 ; operands[0].type: REG = sp ; operands[0].access: READ | WRITE ; operands[1].type: IMM = 0x1f0 ; operands[1].access: READ ; Groups: hasStdExtC
-
-!# issue 0 RISCV operand groups 0x80,0x25 == c.fld fs0, 8(a1)
-!# CS_ARCH_RISCV, CS_MODE_RISCVC, CS_OPT_DETAIL
-0x80,0x25 == c.fld fs0, 8(a1) ; op_count: 2 ; operands[0].type: REG = fs0 ; operands[0].access: WRITE ; operands[1].type: MEM ; operands[1].mem.base: REG = a1 ; operands[1].mem.disp: 0x8 ; operands[1].access: READ ; Groups: hasStdExtC hasStdExtD
-
-!# issue 0 RISCV operand groups 0x00,0x46 == c.lw s0, 8(a2)
-!# CS_ARCH_RISCV, CS_MODE_RISCVC, CS_OPT_DETAIL
-0x00,0x46 == c.lw s0, 8(a2) ; op_count: 2 ; operands[0].type: REG = s0 ; operands[0].access: WRITE ; operands[1].type: MEM ; operands[1].mem.base: REG = a2 ; operands[1].mem.disp: 0x8 ; operands[1].access: READ ; Groups: hasStdExtC
-
-!# issue 0 RISCV operand groups 0x88,0xa2 == c.fsd fa0, 0(a3)
-!# CS_ARCH_RISCV, CS_MODE_RISCVC, CS_OPT_DETAIL
-0x88,0xa2 == c.fsd fa0, 0(a3) ; op_count: 2 ; operands[0].type: REG = fa0 ; operands[0].access: READ ; operands[1].type: MEM ; operands[1].mem.base: REG = a3 ; operands[1].access: WRITE ; Groups: hasStdExtC hasStdExtD
-
-!# issue 0 RISCV operand groups 0x04,0xcb == c.sw s1, 0x10(a4)
-!# CS_ARCH_RISCV, CS_MODE_RISCVC, CS_OPT_DETAIL
-0x04,0xcb == c.sw s1, 0x10(a4) ; op_count: 2 ; operands[0].type: REG = s1 ; operands[0].access: READ ; operands[1].type: MEM ; operands[1].mem.base: REG = a4 ; operands[1].mem.disp: 0x10 ; operands[1].access: WRITE ; Groups: hasStdExtC
-
-!# issue 0 RISCV operand groups 0x55,0x13 == c.addi t1, -0xb
-!# CS_ARCH_RISCV, CS_MODE_RISCVC, CS_OPT_DETAIL
-0x55,0x13 == c.addi t1, -0xb ; op_count: 2 ; operands[0].type: REG = t1 ; operands[0].access: READ | WRITE ; operands[1].type: IMM = 0xfffffff5 ; operands[1].access: READ ; Groups: hasStdExtC
-
-!# issue 0 RISCV operand groups 0xf2,0x93 == c.add t2, t3
-!# CS_ARCH_RISCV, CS_MODE_RISCVC, CS_OPT_DETAIL
-0xf2,0x93 == c.add t2, t3 ; op_count: 2 ; operands[0].type: REG = t2 ; operands[0].access: READ | WRITE ; operands[1].type: REG = t3 ; operands[1].access: READ ; Groups: hasStdExtC
-
-!# issue 0 RISCV operand groups 0x5d,0x45 == c.li a0, 0x17
-!# CS_ARCH_RISCV, CS_MODE_RISCVC, CS_OPT_DETAIL
-0x5d,0x45 == c.li a0, 0x17 ; op_count: 2 ; operands[0].type: REG = a0 ; operands[0].access: WRITE ; operands[1].type: IMM = 0x17 ; operands[1].access: READ ; Groups: hasStdExtC
-
-!# issue 0 RISCV operand groups 0x19,0x80 == c.srli s0, 6
-!# CS_ARCH_RISCV, CS_MODE_RISCVC, CS_OPT_DETAIL
-0x19,0x80 == c.srli s0, 6 ; op_count: 2 ; operands[0].type: REG = s0 ; operands[0].access: READ | WRITE ; operands[1].type: IMM = 0x6 ; operands[1].access: READ ; Groups: hasStdExtC
-
-!# issue 0 RISCV operand groups 0x15,0x68 == c.lui a6, 5
-!# CS_ARCH_RISCV, CS_MODE_RISCVC, CS_OPT_DETAIL
-0x15,0x68 == c.lui a6, 5 ; op_count: 2 ; operands[0].type: REG = a6 ; operands[0].access: WRITE ; operands[1].type: IMM = 0x5 ; operands[1].access: READ ; Groups: hasStdExtC
-
-!# issue 0 RISCV operand groups 0x2a,0xa4 == c.fsdsp fa0, 8(sp)
-!# CS_ARCH_RISCV, CS_MODE_RISCVC, CS_OPT_DETAIL
-0x2a,0xa4 == c.fsdsp fa0, 8(sp) ; op_count: 2 ; operands[0].type: REG = fa0 ; operands[0].access: READ ; operands[1].type: MEM ; operands[1].mem.base: REG = sp ; operands[1].mem.disp: 0x8 ; operands[1].access: WRITE ; Groups: hasStdExtC hasStdExtD
-
-!# issue 0 RISCV operand groups 0x62,0x24 == c.fldsp fs0, 0x18(sp)
-!# CS_ARCH_RISCV, CS_MODE_RISCVC, CS_OPT_DETAIL
-0x62,0x24 == c.fldsp fs0, 0x18(sp) ; op_count: 2 ; operands[0].type: REG = fs0 ; operands[0].access: WRITE ; operands[1].type: MEM ; operands[1].mem.base: REG = sp ; operands[1].mem.disp: 0x18 ; operands[1].access: READ ; Groups: hasStdExtC hasStdExtD
-
-!# issue 0 RISCV operand groups 0xa6,0xff == c.fswsp fs1, 0xfc(sp)
-!# CS_ARCH_RISCV, CS_MODE_RISCVC, CS_OPT_DETAIL
-0xa6,0xff == c.fswsp fs1, 0xfc(sp) ; op_count: 3 ; operands[0].type: REG = fs1 ; operands[0].access: READ ; operands[1].type: IMM = 0xfc ; operands[1].access: READ ; operands[2].type: REG = sp ; operands[2].access: WRITE ; Groups: hasStdExtC hasStdExtF isrv32
-
-!# issue 0 RISCV operand groups 0x2a,0x65 == c.flwsp fa0, 0x88(sp)
-!# CS_ARCH_RISCV, CS_MODE_RISCVC, CS_OPT_DETAIL
-0x2a,0x65 == c.flwsp fa0, 0x88(sp) ; op_count: 3 ; operands[0].type: REG = fa0 ; operands[0].access: WRITE ; operands[1].type: IMM = 0x88 ; operands[1].access: READ ; operands[2].type: REG = sp ; operands[2].access: READ ; Groups: hasStdExtC hasStdExtF isrv32
-
-!# issue 0 RISCV operand groups 0x76,0x86 == c.mv a2, t4
-!# CS_ARCH_RISCV, CS_MODE_RISCVC, CS_OPT_DETAIL
-0x76,0x86 == c.mv a2, t4 ; op_count: 2 ; operands[0].type: REG = a2 ; operands[0].access: WRITE ; operands[1].type: REG = t4 ; operands[1].access: READ ; Groups: hasStdExtC
-
-!# issue 0 RISCV operand groups 0x65,0xdd == c.beqz a0, -8
-!# CS_ARCH_RISCV, CS_MODE_RISCVC, CS_OPT_DETAIL
-0x65,0xdd == c.beqz a0, -8 ; op_count: 2 ; operands[0].type: REG = a0 ; operands[0].access: READ ; operands[1].type: IMM = 0xfffffff8 ; operands[1].access: READ ; Groups: hasStdExtC branch_relative jump
-
-!# issue 0 RISCV operand groups 0x01,0x00 == c.nop
-!# CS_ARCH_RISCV, CS_MODE_RISCVC, CS_OPT_DETAIL
-0x01,0x00 == c.nop ; Groups: hasStdExtC
-
-!# issue 0 RISCV operand groups 0xfd,0xaf == c.j 0x7fe
-!# CS_ARCH_RISCV, CS_MODE_RISCVC, CS_OPT_DETAIL
-0xfd,0xaf == c.j 0x7fe ; op_count: 1 ; operands[0].type: IMM = 0x7fe ; operands[0].access: READ ; Groups: hasStdExtC jump
-
-!# issue 0 RISCV operand groups 0x82,0x82 == c.jr t0
-!# CS_ARCH_RISCV, CS_MODE_RISCVC, CS_OPT_DETAIL
-0x82,0x82 == c.jr t0 ; op_count: 1 ; operands[0].type: REG = t0 ; operands[0].access: READ ; Groups: hasStdExtC jump
-
-!# issue 0 RISCV operand groups 0x11,0x20 == c.jal 4
-!# CS_ARCH_RISCV, CS_MODE_RISCVC, CS_OPT_DETAIL
-0x11,0x20 == c.jal 4 ; op_count: 1 ; operands[0].type: IMM = 0x4 ; operands[0].access: READ ; Groups: hasStdExtC isrv32 call
-
-!# issue 0 RISCV operand groups 0x82,0x94 == c.jalr s1
-!# CS_ARCH_RISCV, CS_MODE_RISCVC, CS_OPT_DETAIL
-0x82,0x94 == c.jalr s1 ; op_count: 1 ; operands[0].type: REG = s1 ; operands[0].access: READ ; Groups: hasStdExtC call
-
-!# issue 2285 AArch64 operands
-!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL
-0xc0,0x08,0x9f,0xe0 == ld1w {za0h.s[w12, 0]}, p2/z, [x6] ; op_count: 3 ; operands[0].type: SME_MATRIX ; operands[0].sme.type: 2 ; operands[0].sme.tile: za0.s ; operands[0].sme.slice_reg: w12 ; operands[0].sme.slice_offset: 0 ; operands[0].sme.is_vertical: false ; operands[0].access: WRITE ; operands[0].vas: 0x20 ; operands[1].type: PREDICATE ; operands[1].pred.reg: p2 ; operands[1].access: READ ; operands[2].type: MEM ; operands[2].mem.base: REG = x6 ; operands[2].access: READ ; Registers read: w12 p2 x6 ; Registers modified: za0.s ; Groups: HasSME
-
-!# issue 2285 AArch64 operands
-!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL
-0x41,0x31,0xa2,0xe0 == st1w {za0h.s[w13, 1]}, p4, [x10, x2, lsl #2] ; op_count: 3 ; operands[0].type: SME_MATRIX ; operands[0].sme.type: 2 ; operands[0].sme.tile: za0.s ; operands[0].sme.slice_reg: w13 ; operands[0].sme.slice_offset: 1 ; operands[0].sme.is_vertical: false ; operands[0].access: READ ; operands[0].vas: 0x20 ; operands[1].type: PREDICATE ; operands[1].pred.reg: p4 ; operands[1].access: READ ; operands[2].type: MEM ; operands[2].mem.base: REG = x10 ; operands[2].mem.index: REG = x2 ; operands[2].access: WRITE ; Shift: type = 1, value = 2 ; Registers read: za0.s w13 p4 x10 x2 ; Groups: HasSME
-
-!# issue 2285 AArch64 operands
-!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL
-0x67,0x44,0x71,0x25 == psel p7, p1, p3.s[w13, 1] ; op_count: 3 ; operands[0].type: PREDICATE ; operands[0].pred.reg: p7 ; operands[0].access: WRITE ; operands[1].type: PREDICATE ; operands[1].pred.reg: p1 ; operands[1].access: READ ; operands[2].type: PREDICATE ; operands[2].pred.reg: p3 ; operands[2].pred.vec_select: w13 ; operands[2].pred.imm_index: 1 ; operands[2].access: READ ; operands[2].vas: 0x20 ; Registers read: p1 p3 w13 ; Registers modified: p7 ; Groups: HasSVE2p1_or_HasSME
-
-!# issue 2285 AArch64 operands
-!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL
-0x7f,0x47,0x03,0xd5 == smstart ; Code-condition: 16 ; Groups: privilege
-
-!# issue 2285 AArch64 operands
-!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL
-0x55,0x00,0x08,0xc0 == zero {za0.h} ; op_count: 1 ; operands[0].type: SME_MATRIX ; operands[0].sme.type: 1 ; operands[0].sme.tile: za0.h ; operands[0].access: WRITE ; operands[0].vas: 0x10 ; Code-condition: 16 ; Registers modified: za0.h ; Groups: HasSME
-
-!# issue 2285 AArch64 operands
-!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL
-0x02,0xf8,0x55,0xc1 == sdot za.s[w11, 2, vgx4], { z0.h - z3.h }, z5.h[2] ; op_count: 6 ; operands[0].type: SME_MATRIX ; operands[0].sme.type: 2 ; operands[0].sme.tile: za ; operands[0].sme.slice_reg: w11 ; operands[0].sme.slice_offset: 2 ; operands[0].sme.is_vertical: false ; operands[0].access: READ | WRITE ; operands[0].vas: 0x20 ; operands[1].type: REG = z0 ; operands[1].is_list_member: true ; operands[1].access: READ ; operands[1].vas: 0x10 ; operands[2].type: REG = z1 ; operands[2].is_list_member: true ; operands[2].access: READ ; operands[2].vas: 0x10 ; operands[3].type: REG = z2 ; operands[3].is_list_member: true ; operands[3].access: READ ; operands[3].vas: 0x10 ; operands[4].type: REG = z3 ; operands[4].is_list_member: true ; operands[4].access: READ ; operands[4].vas: 0x10 ; operands[5].type: REG = z5 ; operands[5].access: READ ; operands[5].vas: 0x10 ; operands[5].vector_index: 2 ; Write-back: True ; Code-condition: 16 ; Registers read: za w11 z0 z1 z2 z3 z5 ; Registers modified: za ; Groups: HasSME2
-
-!# issue 2285 AArch64 operands
-!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL
-0xa4,0x0e,0x06,0xc0 == movaz { z4.d - z7.d }, za.d[w8, 5, vgx4] ; op_count: 5 ; operands[0].type: REG = z4 ; operands[0].is_list_member: true ; operands[0].access: WRITE ; operands[0].vas: 0x40 ; operands[1].type: REG = z5 ; operands[1].is_list_member: true ; operands[1].access: WRITE ; operands[1].vas: 0x40 ; operands[2].type: REG = z6 ; operands[2].is_list_member: true ; operands[2].access: WRITE ; operands[2].vas: 0x40 ; operands[3].type: REG = z7 ; operands[3].is_list_member: true ; operands[3].access: WRITE ; operands[3].vas: 0x40 ; operands[4].type: SME_MATRIX ; operands[4].sme.type: 2 ; operands[4].sme.tile: za ; operands[4].sme.slice_reg: w8 ; operands[4].sme.slice_offset: 5 ; operands[4].sme.is_vertical: false ; operands[4].access: READ | WRITE ; operands[4].vas: 0x40 ; Write-back: True ; Code-condition: 16 ; Registers read: za w8 ; Registers modified: z4 z5 z6 z7 za ; Groups: HasSME2p1
-
-!# issue 2285 AArch64 operands
-!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL
-0x80,0xa0,0x8d,0xc0 == luti2 { z0.s - z3.s }, zt0, z4[1] ; op_count: 6 ; operands[0].type: REG = z0 ; operands[0].is_list_member: true ; operands[0].access: WRITE ; operands[0].vas: 0x20 ; operands[1].type: REG = z1 ; operands[1].is_list_member: true ; operands[1].access: WRITE ; operands[1].vas: 0x20 ; operands[2].type: REG = z2 ; operands[2].is_list_member: true ; operands[2].access: WRITE ; operands[2].vas: 0x20 ; operands[3].type: REG = z3 ; operands[3].is_list_member: true ; operands[3].access: WRITE ; operands[3].vas: 0x20 ; operands[4].type: REG = zt0 ; operands[4].access: READ ; operands[5].type: REG = z4 ; operands[5].access: READ ; operands[5].vector_index: 1 ; Code-condition: 16 ; Registers read: zt0 z4 ; Registers modified: z0 z1 z2 z3 ; Groups: HasSME2
-
-!# issue 2285 AArch64 operands
-!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL
-0x00,0xb1,0x10,0xc1 == fmla za.h[w9, 0, vgx4], { z8.h - z11.h }, z0.h[0] ; op_count: 6 ; operands[0].type: SME_MATRIX ; operands[0].sme.type: 2 ; operands[0].sme.tile: za ; operands[0].sme.slice_reg: w9 ; operands[0].sme.slice_offset: 0 ; operands[0].sme.is_vertical: false ; operands[0].access: READ | WRITE ; operands[0].vas: 0x10 ; operands[1].type: REG = z8 ; operands[1].is_list_member: true ; operands[1].access: READ ; operands[1].vas: 0x10 ; operands[2].type: REG = z9 ; operands[2].is_list_member: true ; operands[2].access: READ ; operands[2].vas: 0x10 ; operands[3].type: REG = z10 ; operands[3].is_list_member: true ; operands[3].access: READ ; operands[3].vas: 0x10 ; operands[4].type: REG = z11 ; operands[4].is_list_member: true ; operands[4].access: READ ; operands[4].vas: 0x10 ; operands[5].type: REG = z0 ; operands[5].access: READ ; operands[5].vas: 0x10 ; operands[5].vector_index: 0 ; Write-back: True ; Code-condition: 16 ; Registers read: za w9 z8 z9 z10 z11 z0 ; Registers modified: za ; Groups: HasSME2p1 HasSMEF16F16
-
-!# issue 2285 AArch64 operands
-!# CS_ARCH_AARCH64, CS_MODE_ARM, CS_OPT_DETAIL
-0x05,0xd0,0x9b,0xc1 == fmlal za.s[w10, 2:3, vgx4], { z0.h - z3.h }, z11.h[1] ; op_count: 6 ; operands[0].type: SME_MATRIX ; operands[0].sme.type: 2 ; operands[0].sme.tile: za ; operands[0].sme.slice_reg: w10 ; operands[0].sme.slice_offset: 2:3 ; operands[0].sme.is_vertical: false ; operands[0].access: READ | WRITE ; operands[0].vas: 0x20 ; operands[1].type: REG = z0 ; operands[1].is_list_member: true ; operands[1].access: READ ; operands[1].vas: 0x10 ; operands[2].type: REG = z1 ; operands[2].is_list_member: true ; operands[2].access: READ ; operands[2].vas: 0x10 ; operands[3].type: REG = z2 ; operands[3].is_list_member: true ; operands[3].access: READ ; operands[3].vas: 0x10 ; operands[4].type: REG = z3 ; operands[4].is_list_member: true ; operands[4].access: READ ; operands[4].vas: 0x10 ; operands[5].type: REG = z11 ; operands[5].access: READ ; operands[5].vas: 0x10 ; operands[5].vector_index: 1 ; Write-back: True ; Code-condition: 16 ; Registers read: za w10 z0 z1 z2 z3 z11 ; Registers modified: za ; Groups: HasSME2
-
diff --git a/tests/cs_details/README.md b/tests/details/README.md
similarity index 100%
rename from tests/cs_details/README.md
rename to tests/details/README.md
diff --git a/tests/details/aarch64.yaml b/tests/details/aarch64.yaml
new file mode 100644
index 000000000..b452333f5
--- /dev/null
+++ b/tests/details/aarch64.yaml
@@ -0,0 +1,875 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x38, 0xd5, 0xbf, 0x40, 0x00, 0xd5, 0x0c, 0x05, 0x13, 0xd5, 0x20, 0x50, 0x02, 0x0e, 0x20, 0xe4, 0x3d, 0x0f, 0x00, 0x18, 0xa0, 0x5f, 0xa2, 0x00, 0xae, 0x9e, 0x9f, 0x37, 0x03, 0xd5, 0xbf, 0x33, 0x03, 0xd5, 0xdf, 0x3f, 0x03, 0xd5, 0x21, 0x7c, 0x02, 0x9b, 0x21, 0x7c, 0x00, 0x53, 0x00, 0x40, 0x21, 0x4b, 0xe1, 0x0b, 0x40, 0xb9, 0x20, 0x04, 0x81, 0xda, 0x20, 0x08, 0x02, 0x8b, 0x10, 0x5b, 0xe8, 0x3c, 0xfd, 0x7b, 0xba, 0xa9, 0xfd, 0xc7, 0x43, 0xf8 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ "CS_OPT_DETAIL" ]
+      address: 0x2c
+    expected:
+      insns:
+      -
+        asm_text: "mrs x9, MIDR_EL1"
+        details:
+          aarch64:
+            operands:
+              -
+                type: AARCH64_OP_REG
+                reg: x9
+                access: CS_AC_WRITE
+              -
+                type: AARCH64_OP_SYSREG
+                sub_type: AARCH64_OP_REG_MRS
+                sys_raw_val: 0xc000
+            cc: AArch64CC_Invalid
+            update_flags: 1
+          regs_write: [ nzcv, x9 ]
+
+      -
+        asm_text: "msr SPSel, #0"
+        details:
+          aarch64:
+            operands:
+            -
+              type: AARCH64_OP_SYSALIAS
+              sub_type: AARCH64_OP_PSTATEIMM0_15
+              sys_raw_val: 0x5
+            -
+              type: AARCH64_OP_IMM
+              imm: 0x0
+              access: CS_AC_READ
+            cc: AArch64CC_Invalid
+
+      -
+        asm_text: "msr DBGDTRTX_EL0, x12"
+        details:
+          aarch64:
+            operands:
+            -
+              type: AARCH64_OP_SYSREG
+              sub_type: AARCH64_OP_REG_MSR
+              sys_raw_val: 0x9828
+            -
+              type: AARCH64_OP_REG
+              reg: x12
+              access: CS_AC_READ
+            cc: AArch64CC_Invalid
+          regs_read: [ x12 ]
+
+      -
+        asm_text: "tbx v0.8b, { v1.16b, v2.16b, v3.16b }, v2.8b"
+        details:
+          aarch64:
+            operands:
+            -
+              type: AARCH64_OP_REG
+              reg: d0
+              access: CS_AC_READ_WRITE
+              vas: AARCH64LAYOUT_VL_8B
+              is_vreg: 1
+            -
+              type: AARCH64_OP_REG
+              reg: q1
+              access: CS_AC_READ
+              vas: AARCH64LAYOUT_VL_16B
+              is_vreg: 1
+            -
+              type: AARCH64_OP_REG
+              reg: q2
+              access: CS_AC_READ
+              vas: AARCH64LAYOUT_VL_16B
+              is_vreg: 1
+            -
+              type: AARCH64_OP_REG
+              reg: q3
+              access: CS_AC_READ
+              vas: AARCH64LAYOUT_VL_16B
+              is_vreg: 1
+            -
+              type: AARCH64_OP_REG
+              reg: d2
+              access: CS_AC_READ
+              vas: AARCH64LAYOUT_VL_8B
+              is_vreg: 1
+            cc: AArch64CC_Invalid
+          writeback: 1
+          regs_read: [ d0, q1, q2, q3, d2 ]
+          regs_write: [ d0 ]
+
+      -
+        asm_text: "scvtf v0.2s, v1.2s, #3"
+        details:
+          aarch64:
+            operands:
+            -
+              type: AARCH64_OP_REG
+              reg: d0
+              access: CS_AC_WRITE
+              vas: AARCH64LAYOUT_VL_2S
+            -
+              type: AARCH64_OP_REG
+              reg: d1
+              access: CS_AC_READ
+              vas: AARCH64LAYOUT_VL_2S
+            -
+              type: AARCH64_OP_IMM
+              imm: 0x3
+              access: CS_AC_READ
+            cc: AArch64CC_Invalid
+          regs_read: [ d1 ]
+          regs_write: [ d0 ]
+
+      -
+        asm_text: "fmla s0, s0, v0.s[3]"
+        details:
+          aarch64:
+            operands:
+            -
+              type: AARCH64_OP_REG
+              reg: s0
+              access: CS_AC_READ_WRITE
+            -
+              type: AARCH64_OP_REG
+              reg: s0
+              access: CS_AC_READ
+            -
+              type: AARCH64_OP_REG
+              reg: q0
+              access: CS_AC_READ
+              vas: AARCH64LAYOUT_VL_S
+              vector_index: 3
+              vector_index_is_set: true
+            cc: AArch64CC_Invalid
+          writeback: 1
+          regs_read: [ fpcr, s0, q0 ]
+          regs_write: [ s0 ]
+
+      -
+        asm_text: "fmov x2, v5.d[1]"
+        details:
+          aarch64:
+            operands:
+            -
+              type: AARCH64_OP_REG
+              reg: x2
+              access: CS_AC_WRITE
+            -
+              type: AARCH64_OP_REG
+              reg: q5
+              access: CS_AC_READ
+              vas: AARCH64LAYOUT_VL_D
+              vector_index: 1
+              vector_index_is_set: true
+            cc: AArch64CC_Invalid
+          regs_read: [ q5 ]
+          regs_write: [ x2 ]
+
+      -
+        asm_text: "dsb nsh"
+        details:
+          aarch64:
+            operands:
+            -
+              type: AARCH64_OP_SYSALIAS
+              sub_type: AARCH64_OP_DB
+              sys_raw_val: 0x7
+            cc: AArch64CC_Invalid
+
+      -
+        asm_text: "dmb osh"
+        details:
+          aarch64:
+            operands:
+            -
+              type: AARCH64_OP_SYSALIAS
+              sub_type: AARCH64_OP_DB
+              sys_raw_val: 0x3
+            cc: AArch64CC_Invalid
+
+      -
+        asm_text: "isb"
+
+      -
+        asm_text: "mul x1, x1, x2"
+        details:
+          aarch64:
+            operands:
+            -
+              type: AARCH64_OP_REG
+              reg: x1
+              access: CS_AC_WRITE
+            -
+              type: AARCH64_OP_REG
+              reg: x1
+              access: CS_AC_READ
+            -
+              type: AARCH64_OP_REG
+              reg: x2
+              access: CS_AC_READ
+            cc: AArch64CC_Invalid
+          regs_read: [ x1, x2 ]
+          regs_write: [ x1 ]
+
+      -
+        asm_text: "lsr w1, w1, #0"
+        details:
+          aarch64:
+            operands:
+            -
+              type: AARCH64_OP_REG
+              reg: w1
+              access: CS_AC_WRITE
+            -
+              type: AARCH64_OP_REG
+              reg: w1
+              access: CS_AC_READ
+            cc: AArch64CC_Invalid
+          regs_read: [ w1 ]
+          regs_write: [ w1 ]
+
+      -
+        asm_text: "sub w0, w0, w1, uxtw"
+        details:
+          aarch64:
+            operands:
+            -
+              type: AARCH64_OP_REG
+              reg: w0
+              access: CS_AC_WRITE
+            -
+              type: AARCH64_OP_REG
+              reg: w0
+              access: CS_AC_READ
+            -
+              type: AARCH64_OP_REG
+              reg: w1
+              access: CS_AC_READ
+              ext: AARCH64_EXT_UXTW
+            cc: AArch64CC_Invalid
+          regs_read: [ w0, w1 ]
+          regs_write: [ w0 ]
+
+      -
+        asm_text: "ldr w1, [sp, #8]"
+        details:
+          aarch64:
+            operands:
+            -
+              type: AARCH64_OP_REG
+              reg: w1
+              access: CS_AC_WRITE
+            -
+              type: AARCH64_OP_MEM
+              mem_base: sp
+              mem_disp: 0x8
+              access: CS_AC_READ
+            cc: AArch64CC_Invalid
+          regs_read: [ sp ]
+          regs_write: [ w1 ]
+
+      -
+        asm_text: "cneg x0, x1, ne"
+        details:
+          aarch64:
+            operands:
+            -
+              type: AARCH64_OP_REG
+              reg: x0
+              access: CS_AC_WRITE
+            -
+              type: AARCH64_OP_REG
+              reg: x1
+              access: CS_AC_READ
+            cc: AArch64CC_NE
+          regs_read: [ nzcv, x1 ]
+          regs_write: [ x0 ]
+
+      -
+        asm_text: "add x0, x1, x2, lsl #2"
+        details:
+          aarch64:
+            operands:
+            -
+              type: AARCH64_OP_REG
+              reg: x0
+              access: CS_AC_WRITE
+            -
+              type: AARCH64_OP_REG
+              reg: x1
+              access: CS_AC_READ
+            -
+              type: AARCH64_OP_REG
+              reg: x2
+              access: CS_AC_READ
+              shift_type: AARCH64_SFT_LSL
+              shift_value: 2
+            cc: AArch64CC_Invalid
+          regs_read: [ x1, x2 ]
+          regs_write: [ x0 ]
+
+      -
+        asm_text: "ldr q16, [x24, w8, uxtw #4]"
+        details:
+          aarch64:
+            operands:
+            -
+              type: AARCH64_OP_REG
+              reg: q16
+              access: CS_AC_WRITE
+            -
+              type: AARCH64_OP_MEM
+              mem_base: x24
+              mem_index: w8
+              access: CS_AC_READ
+              shift_type: AARCH64_SFT_LSL
+              shift_value: 4
+              ext: AARCH64_EXT_UXTW
+            cc: AArch64CC_Invalid
+          regs_read: [ x24, w8 ]
+          regs_write: [ q16 ]
+
+      -
+        asm_text: "stp x29, x30, [sp, #-0x60]!"
+        details:
+          aarch64:
+            operands:
+            -
+              type: AARCH64_OP_REG
+              reg: x29
+              access: CS_AC_READ
+            -
+              type: AARCH64_OP_REG
+              reg: x30
+              access: CS_AC_READ
+            -
+              type: AARCH64_OP_MEM
+              mem_base: sp
+              mem_disp: -0x60
+              access: CS_AC_WRITE
+            cc: AArch64CC_Invalid
+          writeback: 1
+          regs_read: [ x29, x30, sp ]
+          regs_write: [ sp ]
+
+      -
+        asm_text: "ldr x29, [sp], #0x3c"
+        details:
+          aarch64:
+            operands:
+            -
+              type: AARCH64_OP_REG
+              reg: x29
+              access: CS_AC_WRITE
+            -
+              type: AARCH64_OP_MEM
+              mem_base: sp
+              access: CS_AC_READ
+            -
+              type: AARCH64_OP_IMM
+              imm: 0x3c
+              access: CS_AC_READ
+            post_indexed: 1
+            cc: AArch64CC_Invalid
+          writeback: 1
+          regs_read: [ sp ]
+          regs_write: [ sp, x29 ]
+  -
+    input:
+      bytes: [ 0xc0,0x08,0x9f,0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "ld1w {za0h.s[w12, 0]}, p2/z, [x6]"
+        details:
+          aarch64:
+            operands:
+              -
+                type: AARCH64_OP_SME
+                sme:
+                  type: AARCH64_SME_OP_TILE_VEC
+                  tile: za0.s
+                  slice_reg: w12
+                  slice_offset_imm: 0
+                  is_vertical: -1
+                access: CS_AC_WRITE
+                vas: AARCH64LAYOUT_VL_S
+              -
+                type: AARCH64_OP_PRED
+                pred_reg: p2
+                access: CS_AC_READ
+              -
+                type: AARCH64_OP_MEM
+                mem_base: x6
+                access: CS_AC_READ
+          regs_read: [ w12, p2, x6 ]
+          regs_write: [ za0.s ]
+          groups: [ HasSME ]
+  -
+    input:
+      bytes: [ 0x41,0x31,0xa2,0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "st1w {za0h.s[w13, 1]}, p4, [x10, x2, lsl #2]"
+        details:
+          aarch64:
+            operands:
+              -
+                type: AARCH64_OP_SME
+                sme:
+                  type: AARCH64_SME_OP_TILE_VEC
+                  tile: za0.s
+                  slice_reg: w13
+                  slice_offset_imm: 1
+                  is_vertical: -1
+                access: CS_AC_READ
+                vas: AARCH64LAYOUT_VL_S
+              -
+                type: AARCH64_OP_PRED
+                pred_reg: p4
+                access: CS_AC_READ
+              -
+                type: AARCH64_OP_MEM
+                mem_base: x10
+                mem_index: x2
+                access: CS_AC_WRITE
+                shift_type: ARM_SFT_ASR
+                shift_value: 2
+          regs_read: [ za0.s, w13, p4, x10, x2 ]
+          groups: [ HasSME ]
+  -
+    input:
+      bytes: [ 0x67,0x44,0x71,0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "psel p7, p1, p3.s[w13, 1]"
+        details:
+          aarch64:
+            operands:
+              -
+                type: AARCH64_OP_PRED
+                pred_reg: p7
+                access: CS_AC_WRITE
+              -
+                type: AARCH64_OP_PRED
+                pred_reg: p1
+                access: CS_AC_READ
+              -
+                type: AARCH64_OP_PRED
+                pred_reg: p3
+                pred_vec_select: w13
+                pred_imm_index: 1
+                pred_imm_index_set: true
+                access: CS_AC_READ
+                vas: AARCH64LAYOUT_VL_S
+          regs_read: [ p1, p3, w13 ]
+          regs_write: [ p7 ]
+          groups: [ HasSVE2p1_or_HasSME ]
+  -
+    input:
+      bytes: [ 0x7f,0x47,0x03,0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "smstart"
+        details:
+          aarch64:
+            cc: AArch64CC_Invalid
+          groups: [ privilege ]
+  -
+    input:
+      bytes: [ 0x55,0x00,0x08,0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "zero {za0.h}"
+        details:
+          aarch64:
+            operands:
+              -
+                type: AARCH64_OP_SME
+                sme:
+                  type: AARCH64_SME_OP_TILE
+                  tile: za0.h
+                access: CS_AC_WRITE
+                vas: AARCH64LAYOUT_VL_H
+            cc: AArch64CC_Invalid
+          regs_write: [ za0.h ]
+          groups: [ HasSME ]
+  -
+    input:
+      bytes: [ 0x02,0xf8,0x55,0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "sdot za.s[w11, 2, vgx4], { z0.h - z3.h }, z5.h[2]"
+        details:
+          aarch64:
+            operands:
+              -
+                type: AARCH64_OP_SME
+                sme:
+                  type: AARCH64_SME_OP_TILE_VEC
+                  tile: za
+                  slice_reg: w11
+                  slice_offset_imm: 2
+                  is_vertical: -1
+                access: CS_AC_READ_WRITE
+                vas: AARCH64LAYOUT_VL_S
+              -
+                type: AARCH64_OP_REG
+                reg: z0
+                is_list_member: 1
+                access: CS_AC_READ
+                vas: AARCH64LAYOUT_VL_H
+              -
+                type: AARCH64_OP_REG
+                reg: z1
+                is_list_member: 1
+                access: CS_AC_READ
+                vas: AARCH64LAYOUT_VL_H
+              -
+                type: AARCH64_OP_REG
+                reg: z2
+                is_list_member: 1
+                access: CS_AC_READ
+                vas: AARCH64LAYOUT_VL_H
+              -
+                type: AARCH64_OP_REG
+                reg: z3
+                is_list_member: 1
+                access: CS_AC_READ
+                vas: AARCH64LAYOUT_VL_H
+              -
+                type: AARCH64_OP_REG
+                reg: z5
+                access: CS_AC_READ
+                vas: AARCH64LAYOUT_VL_H
+                vector_index: 2
+                vector_index_is_set: true
+            cc: AArch64CC_Invalid
+          writeback: 1
+          regs_read: [ za, w11, z0, z1, z2, z3, z5 ]
+          regs_write: [ za ]
+          groups: [ HasSME2 ]
+  -
+    input:
+      bytes: [ 0xa4,0x0e,0x06,0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "movaz { z4.d - z7.d }, za.d[w8, 5, vgx4]"
+        details:
+          aarch64:
+            operands:
+              -
+                type: AARCH64_OP_REG
+                reg: z4
+                is_list_member: 1
+                access: CS_AC_WRITE
+                vas: AARCH64LAYOUT_VL_D
+              -
+                type: AARCH64_OP_REG
+                reg: z5
+                is_list_member: 1
+                access: CS_AC_WRITE
+                vas: AARCH64LAYOUT_VL_D
+              -
+                type: AARCH64_OP_REG
+                reg: z6
+                is_list_member: 1
+                access: CS_AC_WRITE
+                vas: AARCH64LAYOUT_VL_D
+              -
+                type: AARCH64_OP_REG
+                reg: z7
+                is_list_member: 1
+                access: CS_AC_WRITE
+                vas: AARCH64LAYOUT_VL_D
+              -
+                type: AARCH64_OP_SME
+                sme:
+                  type: AARCH64_SME_OP_TILE_VEC
+                  tile: za
+                  slice_reg: w8
+                  slice_offset_imm: 5
+                  is_vertical: -1
+                access: CS_AC_READ_WRITE
+                vas: AARCH64LAYOUT_VL_D
+            cc: AArch64CC_Invalid
+          writeback: 1
+          regs_read: [ za, w8 ]
+          regs_write: [ z4, z5, z6, z7, za ]
+          groups: [ HasSME2p1 ]
+  -
+    input:
+      bytes: [ 0x80,0xa0,0x8d,0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "luti2 { z0.s - z3.s }, zt0, z4[1]"
+        details:
+          aarch64:
+            operands:
+              -
+                type: AARCH64_OP_REG
+                reg: z0
+                is_list_member: 1
+                access: CS_AC_WRITE
+                vas: AARCH64LAYOUT_VL_S
+              -
+                type: AARCH64_OP_REG
+                reg: z1
+                is_list_member: 1
+                access: CS_AC_WRITE
+                vas: AARCH64LAYOUT_VL_S
+              -
+                type: AARCH64_OP_REG
+                reg: z2
+                is_list_member: 1
+                access: CS_AC_WRITE
+                vas: AARCH64LAYOUT_VL_S
+              -
+                type: AARCH64_OP_REG
+                reg: z3
+                is_list_member: 1
+                access: CS_AC_WRITE
+                vas: AARCH64LAYOUT_VL_S
+              -
+                type: AARCH64_OP_REG
+                reg: zt0
+                access: CS_AC_READ
+              -
+                type: AARCH64_OP_REG
+                reg: z4
+                access: CS_AC_READ
+                vector_index: 1
+                vector_index_is_set: true
+            cc: AArch64CC_Invalid
+          regs_read: [ zt0, z4 ]
+          regs_write: [ z0, z1, z2, z3 ]
+          groups: [ HasSME2 ]
+  -
+    input:
+      bytes: [ 0x00,0xb1,0x10,0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "fmla za.h[w9, 0, vgx4], { z8.h - z11.h }, z0.h[0]"
+        details:
+          aarch64:
+            operands:
+              -
+                type: AARCH64_OP_SME
+                sme:
+                  type: AARCH64_SME_OP_TILE_VEC
+                  tile: za
+                  slice_reg: w9
+                  slice_offset_imm: 0
+                  is_vertical: -1
+                access: CS_AC_READ_WRITE
+                vas: AARCH64LAYOUT_VL_H
+              -
+                type: AARCH64_OP_REG
+                reg: z8
+                is_list_member: 1
+                access: CS_AC_READ
+                vas: AARCH64LAYOUT_VL_H
+              -
+                type: AARCH64_OP_REG
+                reg: z9
+                is_list_member: 1
+                access: CS_AC_READ
+                vas: AARCH64LAYOUT_VL_H
+              -
+                type: AARCH64_OP_REG
+                reg: z10
+                is_list_member: 1
+                access: CS_AC_READ
+                vas: AARCH64LAYOUT_VL_H
+              -
+                type: AARCH64_OP_REG
+                reg: z11
+                is_list_member: 1
+                access: CS_AC_READ
+                vas: AARCH64LAYOUT_VL_H
+              -
+                type: AARCH64_OP_REG
+                reg: z0
+                access: CS_AC_READ
+                vas: AARCH64LAYOUT_VL_H
+                vector_index: 0
+                vector_index_is_set: true
+            cc: AArch64CC_Invalid
+          writeback: 1
+          regs_read: [ za, w9, z8, z9, z10, z11, z0 ]
+          regs_write: [ za ]
+          groups: [ HasSME2p1, HasSMEF16F16 ]
+  -
+    input:
+      bytes: [ 0x05,0xd0,0x9b,0xc1 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "fmlal za.s[w10, 2:3, vgx4], { z0.h - z3.h }, z11.h[1]"
+        details:
+          aarch64:
+            operands:
+              -
+                type: AARCH64_OP_SME
+                sme:
+                  type: AARCH64_SME_OP_TILE_VEC
+                  tile: za
+                  slice_reg: w10
+                  slice_offset_ir_first: 2
+                  slice_offset_ir_offset: 3
+                  slice_offset_ir_set: true
+                  is_vertical: -1
+                access: CS_AC_READ_WRITE
+                vas: AARCH64LAYOUT_VL_S
+              -
+                type: AARCH64_OP_REG
+                reg: z0
+                is_list_member: 1
+                access: CS_AC_READ
+                vas: AARCH64LAYOUT_VL_H
+              -
+                type: AARCH64_OP_REG
+                reg: z1
+                is_list_member: 1
+                access: CS_AC_READ
+                vas: AARCH64LAYOUT_VL_H
+              -
+                type: AARCH64_OP_REG
+                reg: z2
+                is_list_member: 1
+                access: CS_AC_READ
+                vas: AARCH64LAYOUT_VL_H
+              -
+                type: AARCH64_OP_REG
+                reg: z3
+                is_list_member: 1
+                access: CS_AC_READ
+                vas: AARCH64LAYOUT_VL_H
+              -
+                type: AARCH64_OP_REG
+                reg: z11
+                access: CS_AC_READ
+                vas: AARCH64LAYOUT_VL_H
+                vector_index: 1
+                vector_index_is_set: true
+            cc: AArch64CC_Invalid
+          writeback: 1
+          regs_read: [ za, w10, z0, z1, z2, z3, z11 ]
+          regs_write: [ za ]
+          groups: [ HasSME2 ]
+  -
+    input:
+      bytes: [ 0x15,0x50,0xdf,0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "mov	z21.d, p15/m, #-0x80"
+        details:
+          aarch64:
+            operands:
+              -
+                type: AARCH64_OP_REG
+                reg: z21
+                access: CS_AC_READ_WRITE
+                vas: AARCH64LAYOUT_VL_D
+              -
+                type: AARCH64_OP_PRED
+                pred_reg: p15
+                access: CS_AC_READ
+              -
+                type: AARCH64_OP_IMM
+                imm: -0x80
+                access: CS_AC_READ
+  -
+    input:
+      bytes: [ 0xd3,0x03,0x9b,0xc0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "luti4	{ z19.b, z23.b, z27.b, z31.b }, zt0, { z30, z31 }"
+        details:
+          aarch64:
+            operands:
+              -
+                type: AARCH64_OP_REG
+                reg: z19
+                is_list_member: 1
+                access: CS_AC_WRITE
+                vas: AARCH64LAYOUT_VL_B
+              -
+                type: AARCH64_OP_REG
+                reg: z23
+                is_list_member: 1
+                access: CS_AC_WRITE
+                vas: AARCH64LAYOUT_VL_B
+              -
+                type: AARCH64_OP_REG
+                reg: z27
+                is_list_member: 1
+                access: CS_AC_WRITE
+                vas: AARCH64LAYOUT_VL_B
+              -
+                type: AARCH64_OP_REG
+                reg: z31
+                is_list_member: 1
+                access: CS_AC_WRITE
+                vas: AARCH64LAYOUT_VL_B
+              -
+                type: AARCH64_OP_REG
+                reg: zt0
+                access: CS_AC_READ
+              -
+                type: AARCH64_OP_REG
+                reg: z30
+                is_list_member: 1
+                access: CS_AC_READ
+              -
+                type: AARCH64_OP_REG
+                reg: z31
+                is_list_member: 1
+                access: CS_AC_READ
+          regs_read: [ zt0, z30, z31 ]
+          regs_write: [ z19, z23, z27, z31 ]
+          groups: [ HasSME2p1, HasSME_LUTv2 ]
diff --git a/tests/details/alpha.yaml b/tests/details/alpha.yaml
new file mode 100644
index 000000000..3d6886043
--- /dev/null
+++ b/tests/details/alpha.yaml
@@ -0,0 +1,130 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x02, 0x00, 0xbb, 0x27, 0x50, 0x7a, 0xbd, 0x23, 0xd0, 0xff, 0xde, 0x23, 0x00, 0x00, 0x5e, 0xb7  ]
+      arch: "alpha"
+      options: [ CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "ldah $15,2($13)"
+        details:
+          alpha:
+            operands:
+              -
+                type: ALPHA_OP_REG
+                reg: $15
+              -
+                type: ALPHA_OP_IMM
+                imm: 0x2
+              -
+                type: ALPHA_OP_REG
+                reg: $13
+      -
+        asm_text: "lda $15,0x7a50($15)"
+        details:
+          alpha:
+            operands:
+              -
+                type: ALPHA_OP_REG
+                reg: $15
+              -
+                type: ALPHA_OP_IMM
+                imm: 0x7a50
+              -
+                type: ALPHA_OP_REG
+                reg: $15
+      -
+        asm_text: "lda $30,0xffd0($30)"
+        details:
+          alpha:
+            operands:
+              -
+                type: ALPHA_OP_REG
+                reg: $30
+              -
+                type: ALPHA_OP_IMM
+                imm: 0xffd0
+              -
+                type: ALPHA_OP_REG
+                reg: $30
+      -
+        asm_text: "stq $12,0($30)"
+        details:
+          alpha:
+            operands:
+              -
+                type: ALPHA_OP_REG
+                reg: $12
+              -
+                type: ALPHA_OP_IMM
+                imm: 0x0
+              -
+                type: ALPHA_OP_REG
+                reg: $30
+  -
+    input:
+      bytes: [ 0x27, 0xbb, 0x00, 0x02, 0x23, 0xbd, 0x7a, 0x50, 0x23, 0xde, 0xff, 0xd0, 0xb7, 0x5e, 0x00, 0x00  ]
+      arch: "alpha"
+      options: [ CS_MODE_BIG_ENDIAN, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "ldah $15,2($13)"
+        details:
+          alpha:
+            operands:
+              -
+                type: ALPHA_OP_REG
+                reg: $15
+              -
+                type: ALPHA_OP_IMM
+                imm: 0x2
+              -
+                type: ALPHA_OP_REG
+                reg: $13
+      -
+        asm_text: "lda $15,0x7a50($15)"
+        details:
+          alpha:
+            operands:
+              -
+                type: ALPHA_OP_REG
+                reg: $15
+              -
+                type: ALPHA_OP_IMM
+                imm: 0x7a50
+              -
+                type: ALPHA_OP_REG
+                reg: $15
+      -
+        asm_text: "lda $30,0xffd0($30)"
+        details:
+          alpha:
+            operands:
+              -
+                type: ALPHA_OP_REG
+                reg: $30
+              -
+                type: ALPHA_OP_IMM
+                imm: 0xffd0
+              -
+                type: ALPHA_OP_REG
+                reg: $30
+      -
+        asm_text: "stq $12,0($30)"
+        details:
+          alpha:
+            operands:
+              -
+                type: ALPHA_OP_REG
+                reg: $12
+              -
+                type: ALPHA_OP_IMM
+                imm: 0x0
+              -
+                type: ALPHA_OP_REG
+                reg: $30
+
diff --git a/tests/details/arm.yaml b/tests/details/arm.yaml
new file mode 100644
index 000000000..fe862b533
--- /dev/null
+++ b/tests/details/arm.yaml
@@ -0,0 +1,2291 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x86, 0x48, 0x60, 0xf4, 0x4d, 0x0f, 0xe2, 0xf4, 0xed, 0xff, 0xff, 0xeb, 0x04, 0xe0, 0x2d, 0xe5, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x83, 0x22, 0xe5, 0xf1, 0x02, 0x03, 0x0e, 0x00, 0x00, 0xa0, 0xe3, 0x02, 0x30, 0xc1, 0xe7, 0x00, 0x00, 0x53, 0xe3, 0x00, 0x02, 0x01, 0xf1, 0x05, 0x40, 0xd0, 0xe8, 0xf4, 0x80, 0x00, 0x00 ]
+      arch: "arm"
+      options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
+      address: 0x80001000
+    expected:
+      insns:
+      -
+        asm_text: "vld2.32 {d20, d21}, [r0], r6"
+        details:
+          arm:
+            operands:
+              -
+                type: ARM_OP_REG
+                reg: d20
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_REG
+                reg: d21
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_MEM
+                mem_base: r0
+                mem_index: r6
+                access: CS_AC_READ_WRITE
+            post_indexed: 1
+            vector_size: 32
+          writeback: 1
+          regs_read: [ r0, r6 ]
+          regs_write: [ r0, d20, d21 ]
+      -
+        asm_text: "vld4.16 {d16[], d17[], d18[], d19[]}, [r2]!"
+        details:
+          arm:
+            operands:
+              -
+                type: ARM_OP_REG
+                reg: d16
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_REG
+                reg: d17
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_REG
+                reg: d18
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_REG
+                reg: d19
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_MEM
+                mem_base: r2
+                access: CS_AC_READ_WRITE
+            post_indexed: -1
+            vector_size: 16
+          writeback: 1
+          regs_read: [ r2 ]
+          regs_write: [ r2, d16, d17, d18, d19 ]
+      -
+        asm_text: "bl 0x80000fc4"
+        details:
+          arm:
+            operands:
+              -
+                type: ARM_OP_IMM
+                imm: 0x80000fc4
+                access: CS_AC_READ
+          regs_read: [ r13 ]
+          regs_write: [ r14 ]
+      -
+        asm_text: "str lr, [sp, #-4]!"
+        details:
+          arm:
+            operands:
+              -
+                type: ARM_OP_REG
+                reg: r14
+                access: CS_AC_READ
+              -
+                type: ARM_OP_MEM
+                mem_base: r13
+                mem_disp: 0x4
+                access: CS_AC_WRITE
+                subtracted: 1
+            post_indexed: -1
+          writeback: 1
+          regs_read: [ r14, r13 ]
+          regs_write: [ r13 ]
+      -
+        asm_text: "andeq r0, r0, r0"
+        details:
+          arm:
+            operands:
+              -
+                type: ARM_OP_REG
+                reg: r0
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_REG
+                reg: r0
+                access: CS_AC_READ
+              -
+                type: ARM_OP_REG
+                reg: r0
+                access: CS_AC_READ
+            cc: ARMCC_EQ
+          regs_read: [ cpsr, r0 ]
+          regs_write: [ r0 ]
+      -
+        asm_text: "str r8, [r2, #-0x3e0]!"
+        details:
+          arm:
+            operands:
+              -
+                type: ARM_OP_REG
+                reg: r8
+                access: CS_AC_READ
+              -
+                type: ARM_OP_MEM
+                mem_base: r2
+                mem_disp: 0x3e0
+                access: CS_AC_WRITE
+                subtracted: 1
+            post_indexed: -1
+          writeback: 1
+          regs_read: [ r8, r2 ]
+          regs_write: [ r2 ]
+      -
+        asm_text: "mcreq p2, #0, r0, c3, c1, #7"
+        details:
+          arm:
+            operands:
+              -
+                type: ARM_OP_PIMM
+                imm: 2
+                access: CS_AC_READ
+              -
+                type: ARM_OP_IMM
+                imm: 0x0
+                access: CS_AC_READ
+              -
+                type: ARM_OP_REG
+                reg: r0
+                access: CS_AC_READ
+              -
+                type: ARM_OP_CIMM
+                imm: 3
+                access: CS_AC_READ
+              -
+                type: ARM_OP_CIMM
+                imm: 1
+                access: CS_AC_READ
+              -
+                type: ARM_OP_IMM
+                imm: 0x7
+                access: CS_AC_READ
+            cc: ARMCC_EQ
+          regs_read: [ cpsr, r0 ]
+      -
+        asm_text: "mov r0, #0"
+        details:
+          arm:
+            operands:
+              -
+                type: ARM_OP_REG
+                reg: r0
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_IMM
+                imm: 0x0
+                access: CS_AC_READ
+          regs_write: [ r0 ]
+      -
+        asm_text: "strb r3, [r1, r2]"
+        details:
+          arm:
+            operands:
+              -
+                type: ARM_OP_REG
+                reg: r3
+                access: CS_AC_READ
+              -
+                type: ARM_OP_MEM
+                mem_base: r1
+                mem_index: r2
+                access: CS_AC_WRITE
+          regs_read: [ r3, r1, r2 ]
+      -
+        asm_text: "cmp r3, #0"
+        details:
+          arm:
+            operands:
+              -
+                type: ARM_OP_REG
+                reg: r3
+                access: CS_AC_READ
+              -
+                type: ARM_OP_IMM
+                imm: 0x0
+                access: CS_AC_READ
+            update_flags: 1
+          regs_read: [ r3 ]
+          regs_write: [ cpsr ]
+      -
+        asm_text: "setend be"
+        details:
+          arm:
+            operands:
+              -
+                type: ARM_OP_SETEND
+                setend: ARM_SETEND_BE
+      -
+        asm_text: "ldm r0, {r0, r2, lr} ^"
+        details:
+          arm:
+            operands:
+              -
+                type: ARM_OP_REG
+                reg: r0
+                access: CS_AC_READ
+              -
+                type: ARM_OP_REG
+                reg: r0
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_REG
+                reg: r2
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_REG
+                reg: r14
+                access: CS_AC_WRITE
+          regs_read: [ r0 ]
+          regs_write: [ r0, r2, r14 ]
+      -
+        asm_text: "strdeq r8, r9, [r0], -r4"
+        details:
+          arm:
+            operands:
+              -
+                type: ARM_OP_REG
+                reg: r8
+                access: CS_AC_READ
+              -
+                type: ARM_OP_REG
+                reg: r9
+                access: CS_AC_READ
+              -
+                type: ARM_OP_MEM
+                mem_base: r0
+                mem_index: r4
+                access: CS_AC_WRITE
+                subtracted: 1
+            cc: ARMCC_EQ
+            post_indexed: 1
+          writeback: 1
+          regs_read: [ cpsr, r8, r9, r0, r4 ]
+          regs_write: [ r0 ]
+
+  -
+    input:
+      bytes: [ 0x60, 0xf9, 0x1f, 0x04, 0xe0, 0xf9, 0x4f, 0x07, 0x70, 0x47, 0x00, 0xf0, 0x10, 0xe8, 0xeb, 0x46, 0x83, 0xb0, 0xc9, 0x68, 0x1f, 0xb1, 0x30, 0xbf, 0xaf, 0xf3, 0x20, 0x84, 0x52, 0xf8, 0x23, 0xf0 ]
+      arch: "arm"
+      options: [ CS_MODE_THUMB, CS_OPT_DETAIL ]
+      address: 0x80001000
+    expected:
+      insns:
+      -
+        asm_text: "vld3.8 {d16, d17, d18}, [r0:0x40]"
+        details:
+          arm:
+            operands:
+              -
+                type: ARM_OP_REG
+                reg: d16
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_REG
+                reg: d17
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_REG
+                reg: d18
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_MEM
+                mem_base: r0
+                mem_align: 0x40
+                access: CS_AC_READ
+            vector_size: 8
+          regs_read: [ r0 ]
+          regs_write: [ d16, d17, d18 ]
+      -
+        asm_text: "vld4.16 {d16[1], d17[1], d18[1], d19[1]}, [r0]"
+        details:
+          arm:
+            operands:
+              -
+                type: ARM_OP_REG
+                reg: d16
+                neon_lane: 1
+                access: CS_AC_READ_WRITE
+              -
+                type: ARM_OP_REG
+                reg: d17
+                neon_lane: 1
+                access: CS_AC_READ_WRITE
+              -
+                type: ARM_OP_REG
+                reg: d18
+                neon_lane: 1
+                access: CS_AC_READ_WRITE
+              -
+                type: ARM_OP_REG
+                reg: d19
+                neon_lane: 1
+                access: CS_AC_READ_WRITE
+              -
+                type: ARM_OP_MEM
+                mem_base: r0
+                access: CS_AC_READ
+            vector_size: 16
+          regs_read: [ d16, d17, d18, d19, r0 ]
+          regs_write: [ d16, d17, d18, d19 ]
+      -
+        asm_text: "bx lr"
+        details:
+          arm:
+            operands:
+              -
+                type: ARM_OP_REG
+                reg: r14
+                access: CS_AC_READ
+          regs_read: [ r14 ]
+      -
+        asm_text: "blx 0x8000102c"
+        details:
+          arm:
+            operands:
+              -
+                type: ARM_OP_IMM
+                imm: 0x8000102c
+                access: CS_AC_READ
+          regs_read: [ r13 ]
+          regs_write: [ r14 ]
+      -
+        asm_text: "mov r11, sp"
+        details:
+          arm:
+            operands:
+              -
+                type: ARM_OP_REG
+                reg: r11
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_REG
+                reg: r13
+                access: CS_AC_READ
+          regs_read: [ r13 ]
+          regs_write: [ r11 ]
+      -
+        asm_text: "sub sp, #0xc"
+        details:
+          arm:
+            operands:
+              -
+                type: ARM_OP_REG
+                reg: r13
+                access: CS_AC_READ_WRITE
+              -
+                type: ARM_OP_IMM
+                imm: 0xc
+                access: CS_AC_READ
+            post_indexed: -1
+          writeback: 1
+          regs_read: [ r13 ]
+          regs_write: [ r13 ]
+      -
+        asm_text: "ldr r1, [r1, #0xc]"
+        details:
+          arm:
+            operands:
+              -
+                type: ARM_OP_REG
+                reg: r1
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_MEM
+                mem_base: r1
+                mem_disp: 0xc
+                access: CS_AC_READ
+          regs_read: [ r1 ]
+          regs_write: [ r1 ]
+      -
+        asm_text: "cbz r7, 0x8000101e"
+        details:
+          arm:
+            operands:
+              -
+                type: ARM_OP_REG
+                reg: r7
+                access: CS_AC_READ
+              -
+                type: ARM_OP_IMM
+                imm: 0x8000101e
+                access: CS_AC_READ
+          regs_read: [ r7 ]
+      -
+        asm_text: "wfi"
+      -
+        asm_text: "cpsie.w f"
+        details:
+          arm:
+            cps_mode: ARM_CPSMODE_IE
+            cps_flag: ARM_CPSFLAG_F
+      -
+        asm_text: "ldr.w pc, [r2, r3, lsl #2]"
+        details:
+          arm:
+            operands:
+              -
+                type: ARM_OP_REG
+                reg: r15
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_MEM
+                mem_base: r2
+                mem_index: r3
+                shift_type: ARM_SFT_LSL
+                shift_value: 2
+          regs_read: [ r2, r3 ]
+          regs_write: [ r15 ]
+
+  -
+    input:
+      bytes: [ 0xd1, 0xe8, 0x00, 0xf0, 0xf0, 0x24, 0x04, 0x07, 0x1f, 0x3c, 0xf2, 0xc0, 0x00, 0x00, 0x4f, 0xf0, 0x00, 0x01, 0x46, 0x6c ]
+      arch: "arm"
+      options: [ CS_MODE_THUMB, CS_OPT_DETAIL ]
+      address: 0x80001000
+    expected:
+      insns:
+      -
+        asm_text: "tbb [r1, r0]"
+        details:
+          arm:
+            operands:
+              -
+                type: ARM_OP_MEM
+                mem_base: r1
+                mem_index: r0
+                access: CS_AC_READ
+          regs_read: [ r1, r0 ]
+      -
+        asm_text: "movs r4, #0xf0"
+        details:
+          arm:
+            operands:
+              -
+                type: ARM_OP_REG
+                reg: r4
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_IMM
+                imm: 0xf0
+                access: CS_AC_READ
+            update_flags: 1
+          regs_write: [ cpsr, r4 ]
+      -
+        asm_text: "lsls r4, r0, #0x1c"
+        details:
+          arm:
+            operands:
+              -
+                type: ARM_OP_REG
+                reg: r4
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_REG
+                reg: r0
+                access: CS_AC_READ
+              -
+                type: ARM_OP_IMM
+                imm: 0x1c
+                access: CS_AC_READ
+            update_flags: 1
+          regs_read: [ r0 ]
+          regs_write: [ cpsr, r4 ]
+      -
+        asm_text: "subs r4, #0x1f"
+        details:
+          arm:
+            operands:
+              -
+                type: ARM_OP_REG
+                reg: r4
+                access: CS_AC_READ_WRITE
+              -
+                type: ARM_OP_IMM
+                imm: 0x1f
+                access: CS_AC_READ
+            update_flags: 1
+            post_indexed: -1
+          writeback: 1
+          regs_read: [ r4 ]
+          regs_write: [ cpsr, r4 ]
+      -
+        asm_text: "stm r0!, {r1, r4, r5, r6, r7}"
+        details:
+          arm:
+            operands:
+              -
+                type: ARM_OP_REG
+                reg: r0
+                access: CS_AC_READ_WRITE
+              -
+                type: ARM_OP_REG
+                reg: r1
+                access: CS_AC_READ
+              -
+                type: ARM_OP_REG
+                reg: r4
+                access: CS_AC_READ
+              -
+                type: ARM_OP_REG
+                reg: r5
+                access: CS_AC_READ
+              -
+                type: ARM_OP_REG
+                reg: r6
+                access: CS_AC_READ
+              -
+                type: ARM_OP_REG
+                reg: r7
+                access: CS_AC_READ
+            post_indexed: -1
+          writeback: 1
+          regs_read: [ r0, r1, r4, r5, r6, r7 ]
+          regs_write: [ r0 ]
+      -
+        asm_text: "movs r0, r0"
+        details:
+          arm:
+            operands:
+              -
+                type: ARM_OP_REG
+                reg: r0
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_REG
+                reg: r0
+                access: CS_AC_READ
+            update_flags: 1
+          regs_read: [ r0 ]
+          regs_write: [ cpsr, r0 ]
+      -
+        asm_text: "mov.w r1, #0"
+        details:
+          arm:
+            operands:
+              -
+                type: ARM_OP_REG
+                reg: r1
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_IMM
+                imm: 0x0
+                access: CS_AC_READ
+          regs_write: [ r1 ]
+      -
+        asm_text: "ldr r6, [r0, #0x44]"
+        details:
+          arm:
+            operands:
+              -
+                type: ARM_OP_REG
+                reg: r6
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_MEM
+                mem_base: r0
+                mem_disp: 0x44
+                access: CS_AC_READ
+          regs_read: [ r0 ]
+          regs_write: [ r6 ]
+
+  -
+    input:
+      bytes: [ 0x4f, 0xf0, 0x00, 0x01, 0xbd, 0xe8, 0x00, 0x88, 0xd1, 0xe8, 0x00, 0xf0, 0x18, 0xbf, 0xad, 0xbf, 0xf3, 0xff, 0x0b, 0x0c, 0x86, 0xf3, 0x00, 0x89, 0x80, 0xf3, 0x00, 0x8c, 0x4f, 0xfa, 0x99, 0xf6, 0xd0, 0xff, 0xa2, 0x01 ]
+      arch: "arm"
+      options: [ CS_MODE_THUMB, CS_OPT_DETAIL ]
+      address: 0x80001000
+    expected:
+      insns:
+      -
+        asm_text: "mov.w r1, #0"
+        details:
+          arm:
+            operands:
+              -
+                type: ARM_OP_REG
+                reg: r1
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_IMM
+                imm: 0x0
+                access: CS_AC_READ
+          regs_write: [ r1 ]
+      -
+        asm_text: "pop.w {r11, pc}"
+        details:
+          arm:
+            operands:
+              -
+                type: ARM_OP_REG
+                reg: r11
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_REG
+                reg: r15
+                access: CS_AC_WRITE
+            post_indexed: -1
+          writeback: 1
+          regs_write: [ r11, r15 ]
+      -
+        asm_text: "tbb [r1, r0]"
+        details:
+          arm:
+            operands:
+              -
+                type: ARM_OP_MEM
+                mem_base: r1
+                mem_index: r0
+                access: CS_AC_READ
+          regs_read: [ r1, r0 ]
+      -
+        asm_text: "it ne"
+        details:
+          arm:
+            cc: ARMCC_NE
+            pred_mask: 0x1
+          regs_read: [ cpsr ]
+          regs_write: [ itstate ]
+      -
+        asm_text: "iteet ge"
+        details:
+          arm:
+            cc: ARMCC_GE
+            pred_mask: 0xd
+          regs_read: [ cpsr ]
+          regs_write: [ itstate ]
+      -
+        asm_text: "vdupge.8 d16, d11[1]"
+        details:
+          arm:
+            operands:
+              -
+                type: ARM_OP_REG
+                reg: d16
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_REG
+                reg: d11
+                access: CS_AC_READ
+                vector_index: 1
+                vector_index_is_set: true
+            cc: ARMCC_GE
+            vector_size: 8
+          regs_read: [ cpsr, d11 ]
+          regs_write: [ d16 ]
+      -
+        asm_text: "msrlt cpsr_fc, r6"
+        details:
+          arm:
+            operands:
+              -
+                type: ARM_OP_CPSR
+                sys_psr_bits: [ ARM_FIELD_CPSR_C, ARM_FIELD_CPSR_C ]
+                sys_msr_mask: 9
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_REG
+                reg: r6
+                access: CS_AC_READ
+            cc: ARMCC_LT
+            update_flags: 1
+          regs_read: [ cpsr, r6 ]
+          regs_write: [ cpsr ]
+      -
+        asm_text: "msrlt apsr_nzcvqg, r0"
+        details:
+          arm:
+            operands:
+              -
+                type: ARM_OP_SYSREG
+                reg: apsr_nzcvqg
+                sys_msr_mask: 12
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_REG
+                reg: r0
+                access: CS_AC_READ
+            cc: ARMCC_LT
+            update_flags: 1
+          regs_read: [ cpsr, r0 ]
+          regs_write: [ cpsr ]
+      -
+        asm_text: "sxtbge.w r6, r9, ror #8"
+        details:
+          arm:
+            operands:
+              -
+                type: ARM_OP_REG
+                reg: r6
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_REG
+                reg: r9
+                access: CS_AC_READ
+                shift_type: ARM_SFT_ROR
+                shift_value: 8
+            cc: ARMCC_GE
+          regs_read: [ cpsr, r9 ]
+          regs_write: [ r6 ]
+      -
+        asm_text: "vaddw.u16 q8, q8, d18"
+        details:
+          arm:
+            operands:
+              -
+                type: ARM_OP_REG
+                reg: q8
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_REG
+                reg: q8
+                access: CS_AC_READ
+              -
+                type: ARM_OP_REG
+                reg: d18
+                access: CS_AC_READ
+            vector_data: ARM_VECTORDATA_U16
+          regs_read: [ q8, d18 ]
+          regs_write: [ q8 ]
+
+  -
+    input:
+      bytes: [ 0xef, 0xf3, 0x02, 0x80 ]
+      arch: "arm"
+      options: [ CS_MODE_THUMB, CS_MODE_MCLASS, CS_OPT_DETAIL ]
+      address: 0x80001000
+    expected:
+      insns:
+      -
+        asm_text: "mrs r0, eapsr"
+        details:
+          arm:
+            operands:
+              -
+                type: ARM_OP_REG
+                reg: r0
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_SYSREG
+                reg: eapsr
+                sys_msr_mask: 2
+                access: CS_AC_READ
+          regs_write: [ r0 ]
+
+  -
+    input:
+      bytes: [ 0xe0, 0x3b, 0xb2, 0xee, 0x42, 0x00, 0x01, 0xe1, 0x51, 0xf0, 0x7f, 0xf5 ]
+      arch: "arm"
+      options: [ CS_MODE_ARM, CS_MODE_V8, CS_OPT_DETAIL ]
+      address: 0x80001000
+    expected:
+      insns:
+      -
+        asm_text: "vcvtt.f64.f16 d3, s1"
+        details:
+          arm:
+            operands:
+              -
+                type: ARM_OP_REG
+                reg: d3
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_REG
+                reg: s1
+                access: CS_AC_READ
+            vector_data: ARM_VECTORDATA_F64F16
+          regs_read: [ s1 ]
+          regs_write: [ d3 ]
+      -
+        asm_text: "crc32b r0, r1, r2"
+        details:
+          arm:
+            operands:
+              -
+                type: ARM_OP_REG
+                reg: r0
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_REG
+                reg: r1
+                access: CS_AC_READ
+              -
+                type: ARM_OP_REG
+                reg: r2
+                access: CS_AC_READ
+          regs_read: [ r1, r2 ]
+          regs_write: [ r0 ]
+      -
+        asm_text: "dmb oshld"
+        details:
+          arm:
+            mem_barrier: ARM_MB_OSHLD
+  -
+    input:
+      bytes: [ 0x90,0xe8,0x0e,0x00 ]
+      arch: "CS_ARCH_ARM"
+      options: [ CS_MODE_THUMB, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "ldm.w r0, {r1, r2, r3}"
+        details:
+          arm:
+            operands:
+              -
+                type: ARM_OP_REG
+                reg: r0
+                access: CS_AC_READ
+              -
+                type: ARM_OP_REG
+                reg: r1
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_REG
+                reg: r2
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_REG
+                reg: r3
+                access: CS_AC_WRITE
+          regs_read: [ r0 ]
+          regs_write: [ r1, r2, r3 ]
+          groups: [ IsThumb2 ]
+  -
+    input:
+      bytes: [ 0x0e,0xc8 ]
+      arch: "CS_ARCH_ARM"
+      options: [ CS_MODE_THUMB, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "ldm r0!, {r1, r2, r3}"
+        details:
+          arm:
+            operands:
+              -
+                type: ARM_OP_REG
+                reg: r0
+                access: CS_AC_READ_WRITE
+              -
+                type: ARM_OP_REG
+                reg: r1
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_REG
+                reg: r2
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_REG
+                reg: r3
+                access: CS_AC_WRITE
+          writeback: 1
+          regs_read: [ r0 ]
+          regs_write: [ r0, r1, r2, r3 ]
+          groups: [ IsThumb ]
+  -
+    input:
+      bytes: [ 0x00,0x2a,0xf7,0xee ]
+      arch: "CS_ARCH_ARM"
+      options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "vmov.f32 s5, #1.000000e+00"
+        details:
+          arm:
+            operands:
+              -
+                type: ARM_OP_REG
+                reg: s5
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_FP
+                fp: 1.0
+          regs_write: [ s5 ]
+          groups: [ HasVFP3 ]
+  -
+    input:
+      bytes: [ 0x0f,0x00,0x71,0xe3 ]
+      arch: "CS_ARCH_ARM"
+      options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "cmn r1, #0xf"
+        details:
+          arm:
+            operands:
+              -
+                type: ARM_OP_REG
+                reg: r1
+                access: CS_AC_READ
+              -
+                type: ARM_OP_IMM
+                imm: 0xf
+                access: CS_AC_READ
+            update_flags: 1
+          regs_read: [ r1 ]
+          regs_write: [ cpsr ]
+          groups: [ IsARM ]
+  -
+    input:
+      bytes: [ 0x03,0x20,0xb0,0xe1 ]
+      arch: "CS_ARCH_ARM"
+      options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "movs r2, r3"
+        details:
+          arm:
+            operands:
+              -
+                type: ARM_OP_REG
+                reg: r2
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_REG
+                reg: r3
+                access: CS_AC_READ
+            update_flags: 1
+          regs_read: [ r3 ]
+          regs_write: [ cpsr, r2 ]
+          groups: [ IsARM ]
+  -
+    input:
+      bytes: [ 0xfd,0x8f ]
+      arch: "CS_ARCH_ARM"
+      options: [ CS_MODE_THUMB, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "ldrh r5, [r7, #0x3e]"
+        details:
+          arm:
+            operands:
+              -
+                type: ARM_OP_REG
+                reg: r5
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_MEM
+                mem_base: r7
+                mem_disp: 0x3e
+                access: CS_AC_READ
+          regs_read: [ r7 ]
+          regs_write: [ r5 ]
+          groups: [ IsThumb ]
+  -
+    input:
+      bytes: [ 0x61,0xb6 ]
+      arch: "CS_ARCH_ARM"
+      options: [ CS_MODE_THUMB, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "cpsie f"
+        details:
+          arm:
+            cps_mode: ARM_CPSMODE_IE
+            cps_flag: ARM_CPSFLAG_F
+          groups: [ IsThumb ]
+  -
+    input:
+      bytes: [ 0x18,0xf8,0x03,0x1e ]
+      arch: "CS_ARCH_ARM"
+      options: [ CS_MODE_THUMB, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "ldrbt r1, [r8, #3]"
+        details:
+          arm:
+            operands:
+              -
+                type: ARM_OP_REG
+                reg: r1
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_MEM
+                mem_base: r8
+                mem_disp: 0x3
+                access: CS_AC_READ
+          regs_read: [ r8 ]
+          regs_write: [ r1 ]
+          groups: [ IsThumb2 ]
+  -
+    input:
+      bytes: [ 0xb0,0xf8,0x01,0xf1 ]
+      arch: "CS_ARCH_ARM"
+      options: [ CS_MODE_THUMB, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "pldw [r0, #0x101]"
+        details:
+          arm:
+            operands:
+              -
+                type: ARM_OP_MEM
+                mem_base: r0
+                mem_disp: 0x101
+                access: CS_AC_READ
+          regs_read: [ r0 ]
+          groups: [ IsThumb2, HasV7, HasMP ]
+  -
+    input:
+      bytes: [ 0xd3,0xe8,0x08,0xf0 ]
+      arch: "CS_ARCH_ARM"
+      options: [ CS_MODE_THUMB, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "tbb [r3, r8]"
+        details:
+          arm:
+            operands:
+              -
+                type: ARM_OP_MEM
+                mem_base: r3
+                mem_index: r8
+                access: CS_AC_READ
+          regs_read: [ r3, r8 ]
+          groups: [ jump, IsThumb2 ]
+  -
+    input:
+      bytes: [ 0xd3,0xe8,0x18,0xf0 ]
+      arch: "CS_ARCH_ARM"
+      options: [ CS_MODE_THUMB, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "tbh [r3, r8, lsl #1]"
+        details:
+          arm:
+            operands:
+              -
+                type: ARM_OP_MEM
+                mem_base: r3
+                mem_index: r8
+                access: CS_AC_READ
+                shift_type: ARM_SFT_LSL
+                shift_value: 1
+          regs_read: [ r3, r8 ]
+          groups: [ jump, IsThumb2 ]
+  -
+    input:
+      bytes: [ 0xaf,0xf3,0x43,0x85 ]
+      arch: "CS_ARCH_ARM"
+      options: [ CS_MODE_THUMB, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "cpsie i, #3"
+        details:
+          arm:
+            operands:
+              -
+                type: ARM_OP_IMM
+                imm: 0x3
+                access: CS_AC_READ
+            cps_mode: ARM_CPSMODE_IE
+            cps_flag: ARM_CPSFLAG_I
+          groups: [ IsThumb2, IsNotMClass ]
+  -
+    input:
+      bytes: [ 0xbf,0xf3,0x6f,0x8f ]
+      arch: "CS_ARCH_ARM"
+      options: [ CS_MODE_THUMB, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "isb sy"
+        details:
+          arm:
+            mem_barrier: ARM_MB_SY
+          groups: [ IsThumb, HasDB ]
+  -
+    input:
+      bytes: [ 0x59,0xea,0x7b,0x89 ]
+      arch: "CS_ARCH_ARM"
+      options: [ CS_MODE_THUMB, CS_MODE_V8, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "csel r9, r9, r11, vc"
+        details:
+          arm:
+            operands:
+              -
+                type: ARM_OP_REG
+                reg: r9
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_REG
+                reg: r9
+                access: CS_AC_READ
+              -
+                type: ARM_OP_REG
+                reg: r11
+                access: CS_AC_READ
+            cc: ARMCC_VC
+          regs_read: [ cpsr, r9, r11 ]
+          regs_write: [ r9 ]
+          groups: [ HasV8_1MMainline ]
+  -
+    input:
+      bytes: [ 0xbf,0xf3,0x56,0x8f ]
+      arch: "CS_ARCH_ARM"
+      options: [ CS_MODE_THUMB, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "dmb nshst"
+        details:
+          arm:
+            mem_barrier: ARM_MB_NSHST
+          groups: [ IsThumb, HasDB ]
+  -
+    input:
+      bytes: [ 0x31,0xfa,0x02,0xf2 ]
+      arch: "CS_ARCH_ARM"
+      options: [ CS_MODE_THUMB, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "lsrs.w r2, r1, r2"
+        details:
+          arm:
+            operands:
+              -
+                type: ARM_OP_REG
+                reg: r2
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_REG
+                reg: r1
+                access: CS_AC_READ
+              -
+                type: ARM_OP_REG
+                reg: r2
+                access: CS_AC_READ
+            update_flags: 1
+          regs_read: [ r1, r2 ]
+          regs_write: [ cpsr, r2 ]
+          groups: [ IsThumb2 ]
+  -
+    input:
+      bytes: [ 0x08,0xbf,0x5f,0xf0,0x0c,0x01 ]
+      arch: "CS_ARCH_ARM"
+      options: [ CS_MODE_THUMB, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "it eq"
+        details:
+          arm:
+            cc: ARMCC_EQ
+            pred_mask: 0x1
+          regs_write: [ itstate ]
+          groups: [ IsThumb2 ]
+      -
+        asm_text: "movseq.w r1, #0xc"
+        details:
+          arm:
+            operands:
+              -
+                type: ARM_OP_REG
+                reg: r1
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_IMM
+                imm: 0xc
+                access: CS_AC_READ
+            cc: ARMCC_EQ
+            update_flags: 1
+          regs_write: [ cpsr, r1 ]
+          groups: [ IsThumb2 ]
+  -
+    input:
+      bytes: [ 0x52,0xe8,0x01,0x1f ]
+      arch: "CS_ARCH_ARM"
+      options: [ CS_MODE_THUMB, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "ldrex r1, [r2, #4]"
+        details:
+          arm:
+            operands:
+              -
+                type: ARM_OP_REG
+                reg: r1
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_MEM
+                mem_base: r2
+                mem_disp: 0x4
+                access: CS_AC_READ
+          regs_read: [ r2 ]
+          regs_write: [ r1 ]
+          groups: [ IsThumb, HasV8MBaseline ]
+  -
+    input:
+      bytes: [ 0x88,0xbf,0xdf,0xec,0x1d,0x1a ]
+      arch: "CS_ARCH_ARM"
+      options: [ CS_MODE_THUMB, CS_MODE_V8, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "it hi"
+        details:
+          arm:
+            cc: ARMCC_HI
+            pred_mask: 0x1
+          groups: [ IsThumb2 ]
+      -
+        asm_text: "vscclrmhi {s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31, vpr}"
+        details:
+          arm:
+            operands:
+              -
+                type: ARM_OP_REG
+                reg: s3
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_REG
+                reg: s4
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_REG
+                reg: s5
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_REG
+                reg: s6
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_REG
+                reg: s7
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_REG
+                reg: s8
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_REG
+                reg: s9
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_REG
+                reg: s10
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_REG
+                reg: s11
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_REG
+                reg: s12
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_REG
+                reg: s13
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_REG
+                reg: s14
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_REG
+                reg: s15
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_REG
+                reg: s16
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_REG
+                reg: s17
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_REG
+                reg: s18
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_REG
+                reg: s19
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_REG
+                reg: s20
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_REG
+                reg: s21
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_REG
+                reg: s22
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_REG
+                reg: s23
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_REG
+                reg: s24
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_REG
+                reg: s25
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_REG
+                reg: s26
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_REG
+                reg: s27
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_REG
+                reg: s28
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_REG
+                reg: s29
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_REG
+                reg: s30
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_REG
+                reg: s31
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_REG
+                reg: vpr
+                access: CS_AC_WRITE
+            cc: ARMCC_HI
+          regs_write: [ s3, s4, s5, s6, s7, s8, s9, s10, s11, s12, s13, s14, s15, s16, s17, s18, s19, s20, s21, s22, s23, s24, s25, s26, s27, s28, s29, s30, s31, vpr ]
+          groups: [ HasV8_1MMainline, Has8MSecExt ]
+  -
+    input:
+      bytes: [ 0x9f,0xec,0x06,0x5b ]
+      arch: "CS_ARCH_ARM"
+      options: [ CS_MODE_THUMB, CS_MODE_V8, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "vscclrm {d5, d6, d7, vpr}"
+        details:
+          arm:
+            operands:
+              -
+                type: ARM_OP_REG
+                reg: d5
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_REG
+                reg: d6
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_REG
+                reg: d7
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_REG
+                reg: vpr
+                access: CS_AC_WRITE
+          regs_write: [ d5, d6, d7, vpr ]
+          groups: [ HasV8_1MMainline, Has8MSecExt ]
+  -
+    input:
+      bytes: [ 0xbc,0xfd,0x7f,0xaf ]
+      arch: "CS_ARCH_ARM"
+      options: [ CS_MODE_THUMB, CS_MODE_V8, CS_MODE_MCLASS, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "vldrh.u32 q5, [r4, #0xfe]!"
+        details:
+          arm:
+            operands:
+              -
+                type: ARM_OP_REG
+                reg: q5
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_MEM
+                mem_base: r4
+                mem_disp: 0xfe
+                access: CS_AC_READ
+          writeback: 1
+          regs_read: [ r4 ]
+          regs_write: [ r4, q5 ]
+          groups: [ HasMVEInt ]
+  -
+    input:
+      bytes: [ 0x80,0xfc,0x80,0x1e ]
+      arch: "CS_ARCH_ARM"
+      options: [ CS_MODE_THUMB, CS_MODE_MCLASS, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "vst20.16 {q0, q1}, [r0]"
+        details:
+          arm:
+            operands:
+              -
+                type: ARM_OP_REG
+                reg: q0
+                access: CS_AC_READ
+              -
+                type: ARM_OP_REG
+                reg: q1
+                access: CS_AC_READ
+              -
+                type: ARM_OP_MEM
+                mem_base: r0
+                access: CS_AC_WRITE
+          regs_read: [ q0, q1, r0 ]
+          groups: [ HasMVEInt ]
+  -
+    input:
+      bytes: [ 0x98,0xfc,0x4e,0x08 ]
+      arch: "CS_ARCH_ARM"
+      options: [ CS_MODE_THUMB, CS_MODE_MCLASS, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "vcadd.f32 q0, q4, q7, #90"
+        details:
+          arm:
+            operands:
+              -
+                type: ARM_OP_REG
+                reg: q0
+                access: CS_AC_READ_WRITE
+              -
+                type: ARM_OP_REG
+                reg: q4
+                access: CS_AC_READ
+              -
+                type: ARM_OP_REG
+                reg: q7
+                access: CS_AC_READ
+              -
+                type: ARM_OP_IMM
+                imm: 0x5a
+                access: CS_AC_READ
+          regs_read: [ q0, q4, q7 ]
+          regs_write: [ q0 ]
+          groups: [ HasMVEFloat ]
+  -
+    input:
+      bytes: [ 0x94,0xfd,0x46,0x48 ]
+      arch: "CS_ARCH_ARM"
+      options: [ CS_MODE_THUMB, CS_MODE_V8, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "vcadd.f32 q2, q2, q3, #270"
+        details:
+          arm:
+            operands:
+              -
+                type: ARM_OP_REG
+                reg: q2
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_REG
+                reg: q2
+                access: CS_AC_READ
+              -
+                type: ARM_OP_REG
+                reg: q3
+                access: CS_AC_READ
+              -
+                type: ARM_OP_IMM
+                imm: 0x10e
+                access: CS_AC_READ
+          regs_read: [ q2, q3 ]
+          regs_write: [ q2 ]
+          groups: [ HasNEON, HasV8_3a ]
+  -
+    input:
+      bytes: [ 0x9d,0xec,0x82,0x6e ]
+      arch: "CS_ARCH_ARM"
+      options: [ CS_MODE_THUMB, CS_MODE_MCLASS, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "vldrb.s16 q3, [sp, q1]"
+        details:
+          arm:
+            operands:
+              -
+                type: ARM_OP_REG
+                reg: q3
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_MEM
+                mem_base: r13
+                mem_index: q1
+                access: CS_AC_READ
+          regs_read: [ r13, q1 ]
+          regs_write: [ q3 ]
+          groups: [ HasMVEInt ]
+  -
+    input:
+      bytes: [ 0x90,0xec,0x12,0x6f ]
+      arch: "CS_ARCH_ARM"
+      options: [ CS_MODE_THUMB, CS_MODE_MCLASS, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "vldrh.s32 q3, [r0, q1]"
+        details:
+          arm:
+            operands:
+              -
+                type: ARM_OP_REG
+                reg: q3
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_MEM
+                mem_base: r0
+                mem_index: q1
+                access: CS_AC_READ
+          regs_read: [ r0, q1 ]
+          regs_write: [ q3 ]
+          groups: [ HasMVEInt ]
+  -
+    input:
+      bytes: [ 0x5f,0xea,0x2d,0x83 ]
+      arch: "CS_ARCH_ARM"
+      options: [ CS_MODE_THUMB, CS_MODE_V8, CS_MODE_MCLASS, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "sqrshrl lr, r3, #0x40, r8"
+        details:
+          arm:
+            operands:
+              -
+                type: ARM_OP_REG
+                reg: r14
+                access: CS_AC_READ_WRITE
+              -
+                type: ARM_OP_REG
+                reg: r3
+                access: CS_AC_READ_WRITE
+              -
+                type: ARM_OP_IMM
+                imm: 0x40
+                access: CS_AC_READ
+              -
+                type: ARM_OP_REG
+                reg: r8
+                access: CS_AC_READ
+          writeback: 1
+          regs_read: [ r14, r3, r8 ]
+          regs_write: [ r14, r3 ]
+          groups: [ HasV8_1MMainline, HasMVEInt ]
+  -
+    input:
+      bytes: [ 0x82,0xfd,0x21,0xff ]
+      arch: "CS_ARCH_ARM"
+      options: [ CS_MODE_THUMB, CS_MODE_MCLASS, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "vstrd.64 q7, [q1, #0x108]"
+        details:
+          arm:
+            operands:
+              -
+                type: ARM_OP_REG
+                reg: q7
+                access: CS_AC_READ
+              -
+                type: ARM_OP_MEM
+                mem_base: q1
+                mem_disp: 0x108
+                access: CS_AC_WRITE
+          regs_read: [ q7, q1 ]
+          groups: [ HasMVEInt ]
+  -
+    input:
+      bytes: [ 0x06,0x16,0x72,0xe6 ]
+      arch: "CS_ARCH_ARM"
+      options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "ldrbt r1, [r2], -r6, lsl #12"
+        details:
+          arm:
+            operands:
+              -
+                type: ARM_OP_REG
+                reg: r1
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_MEM
+                mem_base: r2
+                mem_index: r6
+                access: CS_AC_READ
+                shift_type: ARM_SFT_LSL
+                shift_value: 12
+                subtracted: 1
+          writeback: 1
+          regs_read: [ r2, r6 ]
+          regs_write: [ r2, r1 ]
+          groups: [ IsARM ]
+  -
+    input:
+      bytes: [ 0xf6,0x50,0x33,0xe1 ]
+      arch: "CS_ARCH_ARM"
+      options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "ldrsh r5, [r3, -r6]!"
+        details:
+          arm:
+            operands:
+              -
+                type: ARM_OP_REG
+                reg: r5
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_MEM
+                mem_base: r3
+                mem_index: r6
+                access: CS_AC_READ
+                subtracted: 1
+          writeback: 1
+          regs_read: [ r3, r6 ]
+          regs_write: [ r3, r5 ]
+          groups: [ IsARM ]
+  -
+    input:
+      bytes: [ 0x1e,0x19,0x7a,0xfd ]
+      arch: "CS_ARCH_ARM"
+      options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "ldc2l p9, c1, [r10, #-0x78]!"
+        details:
+          arm:
+            operands:
+              -
+                type: ARM_OP_PIMM
+                imm: 9
+                access: CS_AC_READ
+              -
+                type: ARM_OP_CIMM
+                imm: 1
+                access: CS_AC_READ
+              -
+                type: ARM_OP_MEM
+                mem_base: r10
+                mem_disp: 0x78
+                access: CS_AC_READ
+          regs_read: [ r10 ]
+          regs_write: [ r10 ]
+          groups: [ IsARM, PreV8 ]
+  -
+    input:
+      bytes: [ 0x12,0x31,0x7c,0xfc ]
+      arch: "CS_ARCH_ARM"
+      options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "ldc2l p1, c3, [r12], #-0x48"
+        details:
+          arm:
+            operands:
+              -
+                type: ARM_OP_PIMM
+                imm: 1
+                access: CS_AC_READ
+              -
+                type: ARM_OP_CIMM
+                imm: 3
+                access: CS_AC_READ
+              -
+                type: ARM_OP_MEM
+                mem_base: r12
+                access: CS_AC_READ
+                mem_disp: 0x48
+                subtracted: 1
+          regs_read: [ r12 ]
+          groups: [ IsARM, PreV8 ]
+  -
+    input:
+      bytes: [ 0xa4,0xf9,0x6d,0x0e ]
+      arch: "CS_ARCH_ARM"
+      options: [ CS_MODE_THUMB, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "vld3.16 {d0[], d2[], d4[]}, [r4]!"
+        details:
+          arm:
+            operands:
+              -
+                type: ARM_OP_REG
+                reg: d0
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_REG
+                reg: d2
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_REG
+                reg: d4
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_MEM
+                mem_base: r4
+                access: CS_AC_READ_WRITE
+          writeback: 1
+          regs_read: [ r4 ]
+          regs_write: [ r4, d0, d2, d4 ]
+  -
+    input:
+      bytes: [ 0x0d,0x50,0x66,0xe4 ]
+      arch: "CS_ARCH_ARM"
+      options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "strbt r5, [r6], #-0xd"
+        details:
+          arm:
+            operands:
+              -
+                type: ARM_OP_REG
+                reg: r5
+                access: CS_AC_READ
+              -
+                type: ARM_OP_MEM
+                mem_base: r6
+                access: CS_AC_WRITE
+                mem_disp: 0xd
+                subtracted: 1
+          writeback: 1
+          regs_read: [ r5, r6 ]
+          regs_write: [ r6 ]
+          groups: [ IsARM ]
+  -
+    input:
+      bytes: [ 0x00,0x10,0x4f,0xe2 ]
+      arch: "CS_ARCH_ARM"
+      options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "sub r1, pc, #0"
+        details:
+          arm:
+            operands:
+              -
+                type: ARM_OP_REG
+                reg: r1
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_REG
+                reg: r15
+                access: CS_AC_READ
+              -
+                type: ARM_OP_IMM
+                imm: 0x0
+                access: CS_AC_READ
+          regs_read: [ r15 ]
+          regs_write: [ r1 ]
+          groups: [ IsARM ]
+  -
+    input:
+      bytes: [ 0x9f,0x51,0xd3,0xe7 ]
+      arch: "CS_ARCH_ARM"
+      options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "bfc r5, #3, #0x11"
+        details:
+          arm:
+            operands:
+              -
+                type: ARM_OP_REG
+                reg: r5
+                access: CS_AC_READ_WRITE
+              -
+                type: ARM_OP_IMM
+                imm: 0x3
+                access: CS_AC_READ
+              -
+                type: ARM_OP_IMM
+                imm: 0x11
+                access: CS_AC_READ
+          writeback: 1
+          regs_read: [ r5 ]
+          regs_write: [ r5 ]
+          groups: [ IsARM, HasV6T2 ]
+  -
+    input:
+      bytes: [ 0xd8,0xe8,0xff,0x67 ]
+      arch: "CS_ARCH_ARM"
+      options: [ CS_MODE_THUMB, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "ldaexd r6, r7, [r8]"
+        details:
+          arm:
+            operands:
+              -
+                type: ARM_OP_REG
+                reg: r6
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_REG
+                reg: r7
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_MEM
+                mem_base: r8
+                access: CS_AC_READ
+          regs_read: [ r8 ]
+          regs_write: [ r6, r7 ]
+          groups: [ IsThumb, HasAcquireRelease, HasV7Clrex, IsNotMClass ]
+  -
+    input:
+      bytes: [ 0x30,0x0f,0xa6,0xe6 ]
+      arch: "CS_ARCH_ARM"
+      options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "ssat16 r0, #7, r0"
+        details:
+          arm:
+            operands:
+              -
+                type: ARM_OP_REG
+                reg: r0
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_IMM
+                imm: 0x7
+                access: CS_AC_READ
+              -
+                type: ARM_OP_REG
+                reg: r0
+                access: CS_AC_READ
+          regs_read: [ r0 ]
+          regs_write: [ r0 ]
+          groups: [ IsARM, HasV6 ]
+  -
+    input:
+      bytes: [ 0x9a,0x8f,0xa0,0xe6 ]
+      arch: "CS_ARCH_ARM"
+      options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "ssat r8, #1, r10, lsl #0x1f"
+        details:
+          arm:
+            operands:
+              -
+                type: ARM_OP_REG
+                reg: r8
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_IMM
+                imm: 0x1
+                access: CS_AC_READ
+              -
+                type: ARM_OP_REG
+                reg: r10
+                access: CS_AC_READ
+                shift_type: ARM_SFT_LSL
+                shift_value: 31
+          regs_read: [ r10 ]
+          regs_write: [ r8 ]
+          groups: [ IsARM, HasV6 ]
+  -
+    input:
+      bytes: [ 0x40,0x1b,0xf5,0xee ]
+      arch: "CS_ARCH_ARM"
+      options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "vcmp.f64 d17, #0"
+        details:
+          arm:
+            operands:
+              -
+                type: ARM_OP_REG
+                reg: d17
+                access: CS_AC_READ
+              -
+                type: ARM_OP_IMM
+                imm: 0x0
+                access: CS_AC_READ
+            update_flags: 1
+          regs_read: [ d17 ]
+          regs_write: [ fpscr_nzcv ]
+          groups: [ HasVFP2, HasDPVFP ]
+  -
+    input:
+      bytes: [ 0x05,0xf0,0x2f,0xe3 ]
+      arch: "CS_ARCH_ARM"
+      options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "msr cpsr_fsxc, #5"
+        details:
+          arm:
+            operands:
+              -
+                type: ARM_OP_CPSR
+                sys_psr_bits: [ ARM_FIELD_CPSR_F, ARM_FIELD_CPSR_S, ARM_FIELD_CPSR_X, ARM_FIELD_CPSR_C ]
+                sys_msr_mask: 0xf
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_IMM
+                imm: 0x5
+                access: CS_AC_READ
+            update_flags: 1
+          regs_write: [ cpsr ]
+          groups: [ IsARM ]
+  -
+    input:
+      bytes: [ 0xa4,0xf9,0xed,0x0b ]
+      arch: "CS_ARCH_ARM"
+      options: [ CS_MODE_THUMB, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "vld4.32 {d0[1], d2[1], d4[1], d6[1]}, [r4:0x80]!"
+        details:
+          arm:
+            operands:
+              -
+                type: ARM_OP_REG
+                reg: d0
+                neon_lane: 1
+                access: CS_AC_READ_WRITE
+              -
+                type: ARM_OP_REG
+                reg: d2
+                neon_lane: 1
+                access: CS_AC_READ_WRITE
+              -
+                type: ARM_OP_REG
+                reg: d4
+                neon_lane: 1
+                access: CS_AC_READ_WRITE
+              -
+                type: ARM_OP_REG
+                reg: d6
+                neon_lane: 1
+                access: CS_AC_READ_WRITE
+              -
+                type: ARM_OP_MEM
+                mem_base: r4
+                mem_align: 0x80
+                access: CS_AC_READ_WRITE
+          writeback: 1
+          regs_read: [ d0, d2, d4, d6, r4 ]
+          regs_write: [ r4, d0, d2, d4, d6 ]
+  -
+    input:
+      bytes: [ 0x42,0x03,0xb0,0xf3 ]
+      arch: "CS_ARCH_ARM"
+      options: [ CS_MODE_ARM, CS_MODE_V8, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "aesd.8 q0, q1"
+        details:
+          arm:
+            operands:
+              -
+                type: ARM_OP_REG
+                reg: q0
+                access: CS_AC_READ_WRITE
+              -
+                type: ARM_OP_REG
+                reg: q1
+                access: CS_AC_READ
+          writeback: 1
+          regs_read: [ q0, q1 ]
+          regs_write: [ q0 ]
+          groups: [ HasV8, HasAES ]
+  -
+    input:
+      bytes: [ 0x11,0x57,0x54,0xfc ]
+      arch: "CS_ARCH_ARM"
+      options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "mrrc2 p7, #1, r5, r4, c1"
+        details:
+          arm:
+            operands:
+              -
+                type: ARM_OP_PIMM
+                imm: 7
+                access: CS_AC_READ
+              -
+                type: ARM_OP_IMM
+                imm: 0x1
+                access: CS_AC_READ
+              -
+                type: ARM_OP_REG
+                reg: r5
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_REG
+                reg: r4
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_CIMM
+                imm: 1
+                access: CS_AC_READ
+          regs_write: [ r5, r4 ]
+          groups: [ IsARM, PreV8 ]
+  -
+    input:
+      bytes: [ 0xd3,0x2f,0x82,0xe6 ]
+      arch: "CS_ARCH_ARM"
+      options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "pkhtb r2, r2, r3, asr #0x1f"
+        details:
+          arm:
+            operands:
+              -
+                type: ARM_OP_REG
+                reg: r2
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_REG
+                reg: r2
+                access: CS_AC_READ
+              -
+                type: ARM_OP_REG
+                reg: r3
+                access: CS_AC_READ
+                shift_type: ARM_SFT_ASR
+                shift_value: 31
+          regs_read: [ r2, r3 ]
+          regs_write: [ r2 ]
+          groups: [ IsARM, HasV6 ]
+  -
+    input:
+      bytes: [ 0x93,0x27,0x82,0xe6 ]
+      arch: "CS_ARCH_ARM"
+      options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "pkhbt r2, r2, r3, lsl #0xf"
+        details:
+          arm:
+            operands:
+              -
+                type: ARM_OP_REG
+                reg: r2
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_REG
+                reg: r2
+                access: CS_AC_READ
+              -
+                type: ARM_OP_REG
+                reg: r3
+                access: CS_AC_READ
+                shift_type: ARM_SFT_LSL
+                shift_value: 15
+          regs_read: [ r2, r3 ]
+          regs_write: [ r2 ]
+          groups: [ IsARM, HasV6 ]
+  -
+    input:
+      bytes: [ 0xb4,0x10,0xf0,0xe0 ]
+      arch: "CS_ARCH_ARM"
+      options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "ldrht r1, [r0], #4"
+        details:
+          arm:
+            operands:
+              -
+                type: ARM_OP_REG
+                reg: r1
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_MEM
+                mem_base: r0
+                access: CS_AC_READ
+                mem_disp: 0x4
+          writeback: 1
+          regs_read: [ r0 ]
+          regs_write: [ r0, r1 ]
+          groups: [ IsARM ]
+  -
+    input:
+      bytes: [ 0x2f,0xfa,0xa1,0xf3 ]
+      arch: "CS_ARCH_ARM"
+      options: [ CS_MODE_THUMB, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "sxtb16 r3, r1, ror #16"
+        details:
+          arm:
+            operands:
+              -
+                type: ARM_OP_REG
+                reg: r3
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_REG
+                reg: r1
+                access: CS_AC_READ
+                shift_type: ARM_SFT_ROR
+                shift_value: 16
+          regs_read: [ r1 ]
+          regs_write: [ r3 ]
+          groups: [ HasDSP, IsThumb2 ]
+  -
+    input:
+      bytes: [ 0x00,0x02,0x01,0xf1 ]
+      arch: "CS_ARCH_ARM"
+      options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "setend be"
+        details:
+          arm:
+            operands:
+              -
+                type: ARM_OP_SETEND
+          groups: [ IsARM ]
+  -
+    input:
+      bytes: [ 0xd0,0xe8,0xaf,0x0f ]
+      arch: "CS_ARCH_ARM"
+      options: [ CS_MODE_THUMB, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "lda r0, [r0]"
+        details:
+          arm:
+            operands:
+              -
+                type: ARM_OP_REG
+                reg: r0
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_MEM
+                mem_base: r0
+                access: CS_AC_READ
+          regs_read: [ r0 ]
+          regs_write: [ r0 ]
+          groups: [ IsThumb, HasAcquireRelease ]
+  -
+    input:
+      bytes: [ 0xef,0xf3,0x11,0x85 ]
+      arch: "CS_ARCH_ARM"
+      options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "ldrhi pc, [r1, #-0x3ef]"
+        details:
+          arm:
+            operands:
+              -
+                type: ARM_OP_REG
+                reg: r15
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_MEM
+                mem_base: r1
+                mem_disp: 0x3ef
+                access: CS_AC_READ
+            cc: ARMCC_HI
+          regs_read: [ cpsr, r1 ]
+          regs_write: [ r15 ]
+          groups: [ IsARM, jump ]
diff --git a/tests/details/bpf.yaml b/tests/details/bpf.yaml
new file mode 100644
index 000000000..8988b6ff4
--- /dev/null
+++ b/tests/details/bpf.yaml
@@ -0,0 +1,137 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x94, 0x09, 0x00, 0x00, 0x37, 0x13, 0x03, 0x00, 0x87, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x16, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 ]
+      arch: "bpf"
+      options: [ CS_OPT_DETAIL, CS_MODE_BPF_CLASSIC ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "mod 0x31337"
+        details:
+          groups: [ BPF_GRP_ALU ]
+          bpf:
+            operands:
+              -
+                type: BPF_OP_IMM
+                imm: 0x31337
+          regs_read: [ a ]
+          regs_write: [ a ]
+      -
+        asm_text: "txa"
+        details:
+          regs_read: [ x ]
+          groups: [ BPF_GRP_MISC ]
+          regs_write: [ a ]
+      -
+        asm_text: "tax"
+        details:
+          regs_read: [ a ]
+          groups: [ BPF_GRP_MISC ]
+          regs_write: [ x ]
+      -
+        asm_text: "ret a"
+        details:
+          groups: [ BPF_GRP_RETURN ]
+          bpf:
+            operands:
+              -
+                type: BPF_OP_REG
+                reg: a
+          regs_read: [ a ]
+      -
+        asm_text: "ld #len"
+        details:
+          groups: [ BPF_GRP_LOAD ]
+          bpf:
+            operands:
+              -
+                type: BPF_OP_EXT
+                ext: BPF_EXT_LEN
+          regs_write: [ a ]
+  -
+    input:
+      bytes: [ 0x97, 0x09, 0x00, 0x00, 0x37, 0x13, 0x03, 0x00, 0xdc, 0x02, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xdb, 0x3a, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x84, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x6d, 0x33, 0x17, 0x02, 0x00, 0x00, 0x00, 0x00 ]
+      arch: "bpf"
+      options: [ CS_OPT_DETAIL, CS_MODE_BPF_EXTENDED ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "mod64 r9, 0x31337"
+        details:
+          groups: [ BPF_GRP_ALU ]
+          bpf:
+            operands:
+              -
+                type: BPF_OP_REG
+                reg: r9
+              -
+                type: BPF_OP_IMM
+                imm: 0x31337
+          regs_read: [ r9 ]
+          regs_write: [ r9 ]
+      -
+        asm_text: "be32 r2"
+        details:
+          groups: [ BPF_GRP_ALU ]
+          bpf:
+            operands:
+              -
+                type: BPF_OP_REG
+                reg: r2
+          regs_read: [ r2 ]
+          regs_write: [ r2 ]
+      -
+        asm_text: "ldb [0x0]"
+        details:
+          groups: [ BPF_GRP_LOAD ]
+          bpf:
+            operands:
+              -
+                type: BPF_OP_MEM
+                mem_disp: 0x0
+          regs_write: [ r0 ]
+      -
+        asm_text: "xadddw [r10+0x100], r3"
+        details:
+          groups: [ BPF_GRP_STORE ]
+          bpf:
+            operands:
+              -
+                type: BPF_OP_MEM
+                mem_base: r10
+                mem_disp: 0x100
+              -
+                type: BPF_OP_REG
+                reg: r3
+          regs_read: [ r3, r10 ]
+      -
+        asm_text: "neg r2"
+        details:
+          groups: [ BPF_GRP_ALU ]
+          bpf:
+            operands:
+              -
+                type: BPF_OP_REG
+                reg: r2
+          regs_read: [ r2 ]
+          regs_write: [ r2 ]
+      -
+        asm_text: "jsgt r3, r3, +0x217"
+        details:
+          groups: [ BPF_GRP_JUMP ]
+          bpf:
+            operands:
+              -
+                type: BPF_OP_REG
+                reg: r3
+              -
+                type: BPF_OP_REG
+                reg: r3
+              -
+                type: BPF_OP_OFF
+                off: 0x217
+          regs_read: [ r3 ]
+
diff --git a/tests/details/cs_common_details.yaml b/tests/details/cs_common_details.yaml
new file mode 100644
index 000000000..4dd602077
--- /dev/null
+++ b/tests/details/cs_common_details.yaml
@@ -0,0 +1,2213 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x8d, 0x4c, 0x32, 0x08, 0x01, 0xd8, 0x81, 0xc6, 0x34, 0x12, 0x00, 0x00  ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_OPT_DETAIL, CS_MODE_16 ]
+      address: 0x1000
+    expected:
+      insns:
+        -
+          asm_text: "lea cx, [si + 0x32]"
+          mnemonic: "lea"
+          op_str: "cx, [si + 0x32]"
+        -
+          asm_text: "or byte ptr [bx + di], al"
+          mnemonic: "or"
+          op_str: "byte ptr [bx + di], al"
+          details:
+            regs_impl_write: [ flags ]
+        -
+          asm_text: "fadd dword ptr [bx + di + 0x34c6]"
+          mnemonic: "fadd"
+          op_str: "dword ptr [bx + di + 0x34c6]"
+          details:
+            regs_impl_write: [ fpsw ]
+            groups: [ fpu ]
+        -
+          asm_text: "adc al, byte ptr [bx + si]"
+          mnemonic: "adc"
+          op_str: "al, byte ptr [bx + si]"
+          details:
+            regs_impl_read: [ flags ]
+            regs_impl_write: [ flags ]
+  -
+    input:
+      bytes: [ 0x8d, 0x4c, 0x32, 0x08, 0x01, 0xd8, 0x81, 0xc6, 0x34, 0x12, 0x00, 0x00  ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_OPT_DETAIL, CS_MODE_32, CS_OPT_SYNTAX_ATT]
+      address: 0x1000
+    expected:
+      insns:
+        -
+          asm_text: "leal 8(%edx, %esi), %ecx"
+          mnemonic: "leal"
+          op_str: "8(%edx, %esi), %ecx"
+          details:
+            groups: [ not64bitmode ]
+        -
+          asm_text: "addl %ebx, %eax"
+          mnemonic: "addl"
+          op_str: "%ebx, %eax"
+          details:
+            regs_impl_write: [ eflags ]
+        -
+          asm_text: "addl $0x1234, %esi"
+          mnemonic: "addl"
+          op_str: "$0x1234, %esi"
+          details:
+            regs_impl_write: [ eflags ]
+  -
+    input:
+      bytes: [ 0x8d, 0x4c, 0x32, 0x08, 0x01, 0xd8, 0x81, 0xc6, 0x34, 0x12, 0x00, 0x00  ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_OPT_DETAIL, CS_MODE_32 ]
+      address: 0x1000
+    expected:
+      insns:
+        -
+          asm_text: "lea ecx, [edx + esi + 8]"
+          mnemonic: "lea"
+          op_str: "ecx, [edx + esi + 8]"
+          details:
+            groups: [ not64bitmode ]
+        -
+          asm_text: "add eax, ebx"
+          mnemonic: "add"
+          op_str: "eax, ebx"
+          details:
+            regs_impl_write: [ eflags ]
+        -
+          asm_text: "add esi, 0x1234"
+          mnemonic: "add"
+          op_str: "esi, 0x1234"
+          details:
+            regs_impl_write: [ eflags ]
+  -
+    input:
+      bytes: [ 0x55, 0x48, 0x8b, 0x05, 0xb8, 0x13, 0x00, 0x00  ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_OPT_DETAIL, CS_MODE_64 ]
+      address: 0x1000
+    expected:
+      insns:
+        -
+          asm_text: "push rbp"
+          mnemonic: "push"
+          op_str: "rbp"
+          details:
+            regs_impl_read: [ rsp ]
+            regs_impl_write: [ rsp ]
+            groups: [ mode64 ]
+        -
+          asm_text: "mov rax, qword ptr [rip + 0x13b8]"
+          mnemonic: "mov"
+          op_str: "rax, qword ptr [rip + 0x13b8]"
+  -
+    input:
+      bytes: [ 0xed, 0xff, 0xff, 0xeb, 0x04, 0xe0, 0x2d, 0xe5, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x83, 0x22, 0xe5, 0xf1, 0x02, 0x03, 0x0e, 0x00, 0x00, 0xa0, 0xe3, 0x02, 0x30, 0xc1, 0xe7, 0x00, 0x00, 0x53, 0xe3  ]
+      arch: "CS_ARCH_ARM"
+      options: [ CS_OPT_DETAIL, CS_MODE_ARM ]
+      address: 0x1000
+    expected:
+      insns:
+        -
+          asm_text: "bl 0xfbc"
+          mnemonic: "bl"
+          op_str: "0xfbc"
+          details:
+            regs_impl_read: [ r13 ]
+            regs_impl_write: [ r14 ]
+            groups: [ call, branch_relative, IsARM ]
+        -
+          asm_text: "str lr, [sp, #-4]!"
+          mnemonic: "str"
+          op_str: "lr, [sp, #-4]!"
+          details:
+            regs_impl_write: [ r13 ]
+            groups: [ IsARM ]
+        -
+          asm_text: "andeq r0, r0, r0"
+          mnemonic: "andeq"
+          op_str: "r0, r0, r0"
+          details:
+            regs_impl_read: [ cpsr ]
+            groups: [ IsARM ]
+        -
+          asm_text: "str r8, [r2, #-0x3e0]!"
+          mnemonic: "str"
+          op_str: "r8, [r2, #-0x3e0]!"
+          details:
+            regs_impl_write: [ r2 ]
+            groups: [ IsARM ]
+        -
+          asm_text: "mcreq p2, #0, r0, c3, c1, #7"
+          mnemonic: "mcreq"
+          op_str: "p2, #0, r0, c3, c1, #7"
+          details:
+            regs_impl_read: [ cpsr ]
+            groups: [ IsARM, privilege ]
+        -
+          asm_text: "mov r0, #0"
+          mnemonic: "mov"
+          op_str: "r0, #0"
+          details:
+            groups: [ IsARM ]
+        -
+          asm_text: "strb r3, [r1, r2]"
+          mnemonic: "strb"
+          op_str: "r3, [r1, r2]"
+          details:
+            groups: [ IsARM ]
+        -
+          asm_text: "cmp r3, #0"
+          mnemonic: "cmp"
+          op_str: "r3, #0"
+          details:
+            regs_impl_write: [ cpsr ]
+            groups: [ IsARM ]
+  -
+    input:
+      bytes: [ 0x10, 0xf1, 0x10, 0xe7, 0x11, 0xf2, 0x31, 0xe7, 0xdc, 0xa1, 0x2e, 0xf3, 0xe8, 0x4e, 0x62, 0xf3  ]
+      arch: "CS_ARCH_ARM"
+      options: [ CS_OPT_DETAIL, CS_MODE_ARM ]
+      address: 0x1000
+    expected:
+      insns:
+        -
+          asm_text: "sdiv r0, r0, r1"
+          mnemonic: "sdiv"
+          op_str: "r0, r0, r1"
+          details:
+            groups: [ IsARM, HasDivideInARM ]
+        -
+          asm_text: "udiv r1, r1, r2"
+          mnemonic: "udiv"
+          op_str: "r1, r1, r2"
+          details:
+            groups: [ IsARM, HasDivideInARM ]
+        -
+          asm_text: "vbit q5, q15, q6"
+          mnemonic: "vbit"
+          op_str: "q5, q15, q6"
+          details:
+            groups: [ HasNEON ]
+        -
+          asm_text: "vcgt.f32 q10, q9, q12"
+          mnemonic: "vcgt.f32"
+          op_str: "q10, q9, q12"
+          details:
+            groups: [ HasNEON ]
+  -
+    input:
+      bytes: [ 0x70, 0x47, 0xeb, 0x46, 0x83, 0xb0, 0xc9, 0x68  ]
+      arch: "CS_ARCH_ARM"
+      options: [ CS_OPT_DETAIL, CS_MODE_THUMB ]
+      address: 0x1000
+    expected:
+      insns:
+        -
+          asm_text: "bx lr"
+          mnemonic: "bx"
+          op_str: "lr"
+          details:
+            groups: [ jump, IsThumb ]
+        -
+          asm_text: "mov r11, sp"
+          mnemonic: "mov"
+          op_str: "r11, sp"
+          details:
+            groups: [ IsThumb ]
+        -
+          asm_text: "sub sp, #0xc"
+          mnemonic: "sub"
+          op_str: "sp, #0xc"
+          details:
+            groups: [ IsThumb ]
+        -
+          asm_text: "ldr r1, [r1, #0xc]"
+          mnemonic: "ldr"
+          op_str: "r1, [r1, #0xc]"
+          details:
+            groups: [ IsThumb ]
+  -
+    input:
+      bytes: [ 0x4f, 0xf0, 0x00, 0x01, 0xbd, 0xe8, 0x00, 0x88, 0xd1, 0xe8, 0x00, 0xf0  ]
+      arch: "CS_ARCH_ARM"
+      options: [ CS_OPT_DETAIL, CS_MODE_THUMB ]
+      address: 0x1000
+    expected:
+      insns:
+        -
+          asm_text: "mov.w r1, #0"
+          mnemonic: "mov.w"
+          op_str: "r1, #0"
+          details:
+            groups: [ IsThumb2 ]
+        -
+          asm_text: "pop.w {r11, pc}"
+          mnemonic: "pop.w"
+          op_str: "{r11, pc}"
+          details:
+            groups: [ IsThumb2, jump ]
+        -
+          asm_text: "tbb [r1, r0]"
+          mnemonic: "tbb"
+          op_str: "[r1, r0]"
+          details:
+            groups: [ jump, IsThumb2 ]
+  -
+    input:
+      bytes: [ 0xef, 0xf3, 0x02, 0x80  ]
+      arch: "CS_ARCH_ARM"
+      options: [ CS_OPT_DETAIL, CS_MODE_THUMB, CS_MODE_MCLASS ]
+      address: 0x1000
+    expected:
+      insns:
+        -
+          asm_text: "mrs r0, eapsr"
+          mnemonic: "mrs"
+          op_str: "r0, eapsr"
+          details:
+            groups: [ IsThumb, IsMClass ]
+  -
+    input:
+      bytes: [ 0xe0, 0x3b, 0xb2, 0xee, 0x42, 0x00, 0x01, 0xe1, 0x51, 0xf0, 0x7f, 0xf5  ]
+      arch: "CS_ARCH_ARM"
+      options: [ CS_OPT_DETAIL, CS_MODE_ARM, CS_MODE_V8 ]
+      address: 0x1000
+    expected:
+      insns:
+        -
+          asm_text: "vcvtt.f64.f16 d3, s1"
+          mnemonic: "vcvtt.f64.f16"
+          op_str: "d3, s1"
+          details:
+            groups: [ HasFPARMv8, HasDPVFP ]
+        -
+          asm_text: "crc32b r0, r1, r2"
+          mnemonic: "crc32b"
+          op_str: "r0, r1, r2"
+          details:
+            groups: [ IsARM, HasV8, HasCRC ]
+        -
+          asm_text: "dmb oshld"
+          mnemonic: "dmb"
+          op_str: "oshld"
+          details:
+            groups: [ IsARM, HasDB ]
+  -
+    input:
+      bytes: [ 0x09, 0x00, 0x38, 0xd5, 0xbf, 0x40, 0x00, 0xd5, 0x0c, 0x05, 0x13, 0xd5, 0x20, 0x50, 0x02, 0x0e, 0x20, 0xe4, 0x3d, 0x0f, 0x00, 0x18, 0xa0, 0x5f, 0xa2, 0x00, 0xae, 0x9e, 0x9f, 0x37, 0x03, 0xd5, 0xbf, 0x33, 0x03, 0xd5, 0xdf, 0x3f, 0x03, 0xd5, 0x21, 0x7c, 0x02, 0x9b, 0x21, 0x7c, 0x00, 0x53, 0x00, 0x40, 0x21, 0x4b, 0xe1, 0x0b, 0x40, 0xb9, 0x20, 0x04, 0x81, 0xda, 0x20, 0x08, 0x02, 0x8b, 0x10, 0x5b, 0xe8, 0x3c  ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ CS_OPT_DETAIL, CS_MODE_ARM ]
+      address: 0x1000
+    expected:
+      insns:
+        -
+          asm_text: "mrs x9, MIDR_EL1"
+          mnemonic: "mrs"
+          op_str: "x9, MIDR_EL1"
+          details:
+            regs_impl_write: [ nzcv ]
+            groups: [ privilege ]
+        -
+          asm_text: "msr SPSel, #0"
+          mnemonic: "msr"
+          op_str: "SPSel, #0"
+          details:
+            groups: [ privilege ]
+        -
+          asm_text: "msr DBGDTRTX_EL0, x12"
+          mnemonic: "msr"
+          op_str: "DBGDTRTX_EL0, x12"
+          details:
+            groups: [ privilege ]
+        -
+          asm_text: "tbx v0.8b, { v1.16b, v2.16b, v3.16b }, v2.8b"
+          mnemonic: "tbx"
+          op_str: "v0.8b, { v1.16b, v2.16b, v3.16b }, v2.8b"
+          details:
+            groups: [ HasNEON ]
+        -
+          asm_text: "scvtf v0.2s, v1.2s, #3"
+          mnemonic: "scvtf"
+          op_str: "v0.2s, v1.2s, #3"
+          details:
+            groups: [ HasNEON ]
+        -
+          asm_text: "fmla s0, s0, v0.s[3]"
+          mnemonic: "fmla"
+          op_str: "s0, s0, v0.s[3]"
+          details:
+            regs_impl_read: [ fpcr ]
+            groups: [ HasNEON ]
+        -
+          asm_text: "fmov x2, v5.d[1]"
+          mnemonic: "fmov"
+          op_str: "x2, v5.d[1]"
+          details:
+            groups: [ HasFPARMv8 ]
+        -
+          asm_text: "dsb nsh"
+          mnemonic: "dsb"
+          op_str: "nsh"
+        -
+          asm_text: "dmb osh"
+          mnemonic: "dmb"
+          op_str: "osh"
+        -
+          asm_text: "isb"
+          mnemonic: "isb"
+        -
+          asm_text: "mul x1, x1, x2"
+          mnemonic: "mul"
+          op_str: "x1, x1, x2"
+        -
+          asm_text: "lsr w1, w1, #0"
+          mnemonic: "lsr"
+          op_str: "w1, w1, #0"
+        -
+          asm_text: "sub w0, w0, w1, uxtw"
+          mnemonic: "sub"
+          op_str: "w0, w0, w1, uxtw"
+        -
+          asm_text: "ldr w1, [sp, #8]"
+          mnemonic: "ldr"
+          op_str: "w1, [sp, #8]"
+        -
+          asm_text: "cneg x0, x1, ne"
+          mnemonic: "cneg"
+          op_str: "x0, x1, ne"
+          details:
+            regs_impl_read: [ nzcv ]
+        -
+          asm_text: "add x0, x1, x2, lsl #2"
+          mnemonic: "add"
+          op_str: "x0, x1, x2, lsl #2"
+        -
+          asm_text: "ldr q16, [x24, w8, uxtw #4]"
+          mnemonic: "ldr"
+          op_str: "q16, [x24, w8, uxtw #4]"
+          details:
+            groups: [ HasFPARMv8 ]
+  -
+    input:
+      bytes: [ 0x0c, 0x10, 0x00, 0x97, 0x00, 0x00, 0x00, 0x00, 0x24, 0x02, 0x00, 0x0c, 0x8f, 0xa2, 0x00, 0x00, 0x34, 0x21, 0x34, 0x56, 0x00, 0x80, 0x04, 0x08  ]
+      arch: "CS_ARCH_MIPS"
+      options: [ CS_OPT_DETAIL, CS_MODE_MIPS32, CS_MODE_BIG_ENDIAN ]
+      address: 0x1000
+    expected:
+      insns:
+        -
+          asm_text: "jal 0x40025c"
+          mnemonic: "jal"
+          op_str: "0x40025c"
+          details:
+            regs_impl_write: [ ra ]
+            groups: [ stdenc ]
+        -
+          asm_text: "nop"
+          mnemonic: "nop"
+          details:
+            groups: [ stdenc, notinmicromips ]
+        -
+          asm_text: "addiu $v0, $zero, 0xc"
+          mnemonic: "addiu"
+          op_str: "$v0, $zero, 0xc"
+          details:
+            groups: [ stdenc, notinmicromips ]
+        -
+          asm_text: "lw $v0, ($sp)"
+          mnemonic: "lw"
+          op_str: "$v0, ($sp)"
+          details:
+            groups: [ stdenc, notinmicromips ]
+        -
+          asm_text: "ori $at, $at, 0x3456"
+          mnemonic: "ori"
+          op_str: "$at, $at, 0x3456"
+          details:
+            groups: [ stdenc ]
+        -
+          asm_text: "jr.hb $a0"
+          mnemonic: "jr.hb"
+          op_str: "$a0"
+          details:
+            groups: [ stdenc, mips32, notmips32r6, notmips64r6, jump ]
+  -
+    input:
+      bytes: [ 0x56, 0x34, 0x21, 0x34, 0xc2, 0x17, 0x01, 0x00  ]
+      arch: "CS_ARCH_MIPS"
+      options: [ CS_OPT_DETAIL, CS_MODE_MIPS64, CS_MODE_LITTLE_ENDIAN ]
+      address: 0x1000
+    expected:
+      insns:
+        -
+          asm_text: "ori $at, $at, 0x3456"
+          mnemonic: "ori"
+          op_str: "$at, $at, 0x3456"
+          details:
+            groups: [ stdenc ]
+        -
+          asm_text: "srl $v0, $at, 0x1f"
+          mnemonic: "srl"
+          op_str: "$v0, $at, 0x1f"
+          details:
+            groups: [ stdenc, notinmicromips ]
+  -
+    input:
+      bytes: [ 0x00, 0x07, 0x00, 0x07, 0x00, 0x11, 0x93, 0x7c, 0x01, 0x8c, 0x8b, 0x7c, 0x00, 0xc7, 0x48, 0xd0  ]
+      arch: "CS_ARCH_MIPS"
+      options: [ CS_OPT_DETAIL, CS_MODE_MIPS32R6, CS_MODE_MICRO, CS_MODE_BIG_ENDIAN ]
+      address: 0x1000
+    expected:
+      insns:
+        -
+          asm_text: "break 7, 0"
+          mnemonic: "break"
+          op_str: "7, 0"
+          details:
+            groups: [ micromips ]
+        -
+          asm_text: "wait 0x11"
+          mnemonic: "wait"
+          op_str: "0x11"
+          details:
+            groups: [ micromips ]
+        -
+          asm_text: "syscall 0x18c"
+          mnemonic: "syscall"
+          op_str: "0x18c"
+          details:
+            groups: [ micromips, int ]
+        -
+          asm_text: "rotrv $t1, $a2, $a3"
+          mnemonic: "rotrv"
+          op_str: "$t1, $a2, $a3"
+          details:
+            groups: [ micromips ]
+  -
+    input:
+      bytes: [ 0xec, 0x80, 0x00, 0x19, 0x7c, 0x43, 0x22, 0xa0  ]
+      arch: "CS_ARCH_MIPS"
+      options: [ CS_OPT_DETAIL, CS_MODE_MIPS32R6, CS_MODE_BIG_ENDIAN ]
+      address: 0x1000
+    expected:
+      insns:
+        -
+          asm_text: "addiupc $a0, 0x64"
+          mnemonic: "addiupc"
+          op_str: "$a0, 0x64"
+          details:
+            groups: [ stdenc, mips32r6 ]
+        -
+          asm_text: "align $a0, $v0, $v1, 2"
+          mnemonic: "align"
+          op_str: "$a0, $v0, $v1, 2"
+          details:
+            groups: [ stdenc, mips32r6 ]
+  -
+    input:
+      bytes: [ 0x80, 0x20, 0x00, 0x00, 0x80, 0x3f, 0x00, 0x00, 0x10, 0x43, 0x23, 0x0e, 0xd0, 0x44, 0x00, 0x80, 0x4c, 0x43, 0x22, 0x02, 0x2d, 0x03, 0x00, 0x80, 0x7c, 0x43, 0x20, 0x14, 0x7c, 0x43, 0x20, 0x93, 0x4f, 0x20, 0x00, 0x21, 0x4c, 0xc8, 0x00, 0x21, 0x40, 0x82, 0x00, 0x14  ]
+      arch: "CS_ARCH_PPC"
+      options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN ]
+      address: 0x1000
+    expected:
+      insns:
+        -
+          asm_text: "lwz r1, 0(0)"
+          mnemonic: "lwz"
+          op_str: "r1, 0(0)"
+        -
+          asm_text: "lwz r1, 0(r31)"
+          mnemonic: "lwz"
+          op_str: "r1, 0(r31)"
+        -
+          asm_text: "vpkpx v2, v3, v4"
+          mnemonic: "vpkpx"
+          op_str: "v2, v3, v4"
+        -
+          asm_text: "stfs f2, 0x80(r4)"
+          mnemonic: "stfs"
+          op_str: "f2, 0x80(r4)"
+          details:
+            groups: [ HasFPU ]
+        -
+          asm_text: "crand eq, un, 4*cr1+lt"
+          mnemonic: "crand"
+          op_str: "eq, un, 4*cr1+lt"
+        -
+          asm_text: "cmpwi cr2, r3, 0x80"
+          mnemonic: "cmpwi"
+          op_str: "cr2, r3, 0x80"
+        -
+          asm_text: "addc r2, r3, r4"
+          mnemonic: "addc"
+          op_str: "r2, r3, r4"
+          details:
+            regs_impl_write: [ xer ]
+        -
+          asm_text: "mulhd. r2, r3, r4"
+          mnemonic: "mulhd."
+          op_str: "r2, r3, r4"
+          details:
+            regs_impl_write: [ cr0 ]
+        -
+          asm_text: "bdnzlrl+"
+          mnemonic: "bdnzlrl+"
+          details:
+            regs_impl_read: [ "ctr", "lr", "**ROUNDING MODE**" ]
+            regs_impl_write: [ lr, ctr ]
+            groups: [ jump ]
+        -
+          asm_text: "bflrl- 4*cr2+lt"
+          mnemonic: "bflrl-"
+          op_str: "4*cr2+lt"
+          details:
+            regs_impl_read: [ "ctr", "lr", "**ROUNDING MODE**" ]
+            regs_impl_write: [ lr, ctr ]
+            groups: [ jump ]
+        -
+          asm_text: "bf eq, 0x103c"
+          mnemonic: "bf"
+          op_str: "eq, 0x103c"
+          details:
+            regs_impl_read: [ "ctr", "**ROUNDING MODE**" ]
+            regs_impl_write: [ ctr ]
+            groups: [ jump, branch_relative ]
+  -
+    input:
+      bytes: [ 0x10, 0x60, 0x2a, 0x10, 0x10, 0x64, 0x28, 0x88, 0x7c, 0x4a, 0x5d, 0x0f  ]
+      arch: "CS_ARCH_PPC"
+      options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_QPX ]
+      address: 0x1000
+    expected:
+      insns:
+        -
+          asm_text: "qvfabs q3, q5"
+          mnemonic: "qvfabs"
+          op_str: "q3, q5"
+          details:
+            regs_impl_read: [ "**ROUNDING MODE**" ]
+            groups: [ HasQPX ]
+        -
+          asm_text: "qvfand q3, q4, q5"
+          mnemonic: "qvfand"
+          op_str: "q3, q4, q5"
+          details:
+            regs_impl_read: [ "**ROUNDING MODE**" ]
+            groups: [ HasQPX ]
+        -
+          asm_text: "qvstfsxa q2, r10, r11"
+          mnemonic: "qvstfsxa"
+          op_str: "q2, r10, r11"
+          details:
+            regs_impl_read: [ "**ROUNDING MODE**" ]
+            groups: [ HasQPX ]
+  -
+    input:
+      bytes: [ 0x80, 0xa0, 0x40, 0x02, 0x85, 0xc2, 0x60, 0x08, 0x85, 0xe8, 0x20, 0x01, 0x81, 0xe8, 0x00, 0x00, 0x90, 0x10, 0x20, 0x01, 0xd5, 0xf6, 0x10, 0x16, 0x21, 0x00, 0x00, 0x0a, 0x86, 0x00, 0x40, 0x02, 0x01, 0x00, 0x00, 0x00, 0x12, 0xbf, 0xff, 0xff, 0x10, 0xbf, 0xff, 0xff, 0xa0, 0x02, 0x00, 0x09, 0x0d, 0xbf, 0xff, 0xff, 0xd4, 0x20, 0x60, 0x00, 0xd4, 0x4e, 0x00, 0x16, 0x2a, 0xc2, 0x80, 0x03  ]
+      arch: "CS_ARCH_SPARC"
+      options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN ]
+      address: 0x1000
+    expected:
+      insns:
+        -
+          asm_text: "cmp %g1, %g2"
+          mnemonic: "cmp"
+          op_str: "%g1, %g2"
+          details:
+            regs_impl_write: [ icc ]
+        -
+          asm_text: "jmpl %o1+8, %g2"
+          mnemonic: "jmpl"
+          op_str: "%o1+8, %g2"
+        -
+          asm_text: "restore %g0, 1, %g2"
+          mnemonic: "restore"
+          op_str: "%g0, 1, %g2"
+        -
+          asm_text: "restore"
+          mnemonic: "restore"
+        -
+          asm_text: "mov 1, %o0"
+          mnemonic: "mov"
+          op_str: "1, %o0"
+        -
+          asm_text: "casx [%i0], %l6, %o2"
+          mnemonic: "casx"
+          op_str: "[%i0], %l6, %o2"
+          details:
+            groups: [ 64bit ]
+        -
+          asm_text: "sethi 0xa, %l0"
+          mnemonic: "sethi"
+          op_str: "0xa, %l0"
+        -
+          asm_text: "add %g1, %g2, %g3"
+          mnemonic: "add"
+          op_str: "%g1, %g2, %g3"
+        -
+          asm_text: "nop"
+          mnemonic: "nop"
+        -
+          asm_text: "bne 0x1020"
+          mnemonic: "bne"
+          op_str: "0x1020"
+          details:
+            regs_impl_read: [ icc ]
+            groups: [ jump ]
+        -
+          asm_text: "ba 0x1024"
+          mnemonic: "ba"
+          op_str: "0x1024"
+          details:
+            groups: [ jump ]
+        -
+          asm_text: "add %o0, %o1, %l0"
+          mnemonic: "add"
+          op_str: "%o0, %o1, %l0"
+        -
+          asm_text: "fbg 0x102c"
+          mnemonic: "fbg"
+          op_str: "0x102c"
+          details:
+            regs_impl_read: [ fcc0 ]
+            groups: [ jump ]
+        -
+          asm_text: "st %o2, [%g1]"
+          mnemonic: "st"
+          op_str: "%o2, [%g1]"
+        -
+          asm_text: "ldsb [%i0+%l6], %o2"
+          mnemonic: "ldsb"
+          op_str: "[%i0+%l6], %o2"
+        -
+          asm_text: "brnz,a,pn %o2, 0x1048"
+          mnemonic: "brnz,a,pn"
+          op_str: "%o2, 0x1048"
+          details:
+            groups: [ 64bit, jump ]
+  -
+    input:
+      bytes: [ 0x81, 0xa8, 0x0a, 0x24, 0x89, 0xa0, 0x10, 0x20, 0x89, 0xa0, 0x1a, 0x60, 0x89, 0xa0, 0x00, 0xe0  ]
+      arch: "CS_ARCH_SPARC"
+      options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_V9 ]
+      address: 0x1000
+    expected:
+      insns:
+        -
+          asm_text: "fcmps %f0, %f4"
+          mnemonic: "fcmps"
+          op_str: "%f0, %f4"
+        -
+          asm_text: "fstox %f0, %f4"
+          mnemonic: "fstox"
+          op_str: "%f0, %f4"
+          details:
+            groups: [ 64bit ]
+        -
+          asm_text: "fqtoi %f0, %f4"
+          mnemonic: "fqtoi"
+          op_str: "%f0, %f4"
+          details:
+            groups: [ hardquad ]
+        -
+          asm_text: "fnegq %f0, %f4"
+          mnemonic: "fnegq"
+          op_str: "%f0, %f4"
+          details:
+            groups: [ v9 ]
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x1a, 0x5a, 0x0f, 0x1f, 0xff, 0xc2, 0x09, 0x80, 0x00, 0x00, 0x00, 0x07, 0xf7, 0xeb, 0x2a, 0xff, 0xff, 0x7f, 0x57, 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x57, 0xeb, 0x00, 0xf0, 0x00, 0x00, 0x24, 0xb2, 0x4f, 0x00, 0x78  ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ CS_OPT_DETAIL ]
+      address: 0x1000
+    expected:
+      insns:
+        -
+          asm_text: "adb %f0, 0"
+          mnemonic: "adb"
+          op_str: "%f0, 0"
+          details:
+            regs_impl_write: [ cc ]
+        -
+          asm_text: "a %r0, 0xfff(%r15, %r1)"
+          mnemonic: "a"
+          op_str: "%r0, 0xfff(%r15, %r1)"
+          details:
+            regs_impl_write: [ cc ]
+        -
+          asm_text: "afi %r0, -0x80000000"
+          mnemonic: "afi"
+          op_str: "%r0, -0x80000000"
+          details:
+            regs_impl_write: [ cc ]
+        -
+          asm_text: "br %r7"
+          mnemonic: "br"
+          op_str: "%r7"
+          details:
+            groups: [ jump ]
+        -
+          asm_text: "xiy 0x7ffff(%r15), 0x2a"
+          mnemonic: "xiy"
+          op_str: "0x7ffff(%r15), 0x2a"
+          details:
+            regs_impl_write: [ cc ]
+        -
+          asm_text: "xy %r0, 0x7ffff(%r1, %r15)"
+          mnemonic: "xy"
+          op_str: "%r0, 0x7ffff(%r1, %r15)"
+          details:
+            regs_impl_write: [ cc ]
+        -
+          asm_text: "stmg %r0, %r0, 0(%r15)"
+          mnemonic: "stmg"
+          op_str: "%r0, %r0, 0(%r15)"
+        -
+          asm_text: "ear %r7, %a8"
+          mnemonic: "ear"
+          op_str: "%r7, %a8"
+  -
+    input:
+      bytes: [ 0xfe, 0x0f, 0xfe, 0x17, 0x13, 0x17, 0xc6, 0xfe, 0xec, 0x17, 0x97, 0xf8, 0xec, 0x4f, 0x1f, 0xfd, 0xec, 0x37, 0x07, 0xf2, 0x45, 0x5b, 0xf9, 0xfa, 0x02, 0x06, 0x1b, 0x10  ]
+      arch: "CS_ARCH_XCORE"
+      options: [ CS_OPT_DETAIL]
+      address: 0x1000
+    expected:
+      insns:
+        -
+          asm_text: "get r11, ed"
+          mnemonic: "get"
+          op_str: "r11, ed"
+          details:
+            regs_impl_write: [ r11 ]
+        -
+          asm_text: "ldw et, sp[4]"
+          mnemonic: "ldw"
+          op_str: "et, sp[4]"
+          details:
+            regs_impl_read: [ sp ]
+        -
+          asm_text: "setd res[r3], r4"
+          mnemonic: "setd"
+          op_str: "res[r3], r4"
+        -
+          asm_text: "init t[r2]:lr, r1"
+          mnemonic: "init"
+          op_str: "t[r2]:lr, r1"
+        -
+          asm_text: "divu r9, r1, r3"
+          mnemonic: "divu"
+          op_str: "r9, r1, r3"
+        -
+          asm_text: "lda16 r9, r3[-r11]"
+          mnemonic: "lda16"
+          op_str: "r9, r3[-r11]"
+        -
+          asm_text: "ldw dp, dp[0x81c5]"
+          mnemonic: "ldw"
+          op_str: "dp, dp[0x81c5]"
+        -
+          asm_text: "lmul r11, r0, r2, r5, r8, r10"
+          mnemonic: "lmul"
+          op_str: "r11, r0, r2, r5, r8, r10"
+        -
+          asm_text: "add r1, r2, r3"
+          mnemonic: "add"
+          op_str: "r1, r2, r3"
+  -
+    input:
+      bytes: [ 0xd4, 0x40, 0x87, 0x5a, 0x4e, 0x71, 0x02, 0xb4, 0xc0, 0xde, 0xc0, 0xde, 0x5c, 0x00, 0x1d, 0x80, 0x71, 0x12, 0x01, 0x23, 0xf2, 0x3c, 0x44, 0x22, 0x40, 0x49, 0x0e, 0x56, 0x54, 0xc5, 0xf2, 0x3c, 0x44, 0x00, 0x44, 0x7a, 0x00, 0x00, 0xf2, 0x00, 0x0a, 0x28, 0x4e, 0xb9, 0x00, 0x00, 0x00, 0x12, 0x4e, 0x75  ]
+      arch: "CS_ARCH_M68K"
+      options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040 ]
+      address: 0x1000
+    expected:
+      insns:
+        -
+          asm_text: "add.w d0, d2"
+          mnemonic: "add.w"
+          op_str: "d0, d2"
+          details:
+            regs_impl_read: [ d0 ]
+            regs_impl_write: [ d2 ]
+        -
+          asm_text: "or.w d3, (a2)+"
+          mnemonic: "or.w"
+          op_str: "d3, (a2)+"
+          details:
+            regs_impl_read: [ d3 ]
+            regs_impl_write: [ a2 ]
+        -
+          asm_text: "nop"
+          mnemonic: "nop"
+        -
+          asm_text: "andi.l #$c0dec0de, (a4, d5.l * 4)"
+          mnemonic: "andi.l"
+          op_str: "#$c0dec0de, (a4, d5.l * 4)"
+          details:
+            regs_impl_read: [ d5, a4 ]
+        -
+          asm_text: "move.b d0, ([a6, d7.w], $123)"
+          mnemonic: "move.b"
+          op_str: "d0, ([a6, d7.w], $123)"
+          details:
+            regs_impl_read: [ d0, d7, a6 ]
+        -
+          asm_text: "fadd.s #3.141500, fp0"
+          mnemonic: "fadd.s"
+          op_str: "#3.141500, fp0"
+          details:
+            regs_impl_write: [ fp0 ]
+        -
+          asm_text: "scc.b d5"
+          mnemonic: "scc.b"
+          op_str: "d5"
+          details:
+            regs_impl_write: [ d5 ]
+        -
+          asm_text: "fmove.s #1000.000000, fp0"
+          mnemonic: "fmove.s"
+          op_str: "#1000.000000, fp0"
+          details:
+            regs_impl_write: [ fp0 ]
+        -
+          asm_text: "fsub fp2, fp4"
+          mnemonic: "fsub"
+          op_str: "fp2, fp4"
+          details:
+            regs_impl_read: [ fp2 ]
+            regs_impl_write: [ fp4 ]
+        -
+          asm_text: "jsr $12.l"
+          mnemonic: "jsr"
+          op_str: "$12.l"
+          details:
+            groups: [ jump ]
+        -
+          asm_text: "rts"
+          mnemonic: "rts"
+          details:
+            groups: [ ret ]
+  -
+    input:
+      bytes: [ 0x06, 0x10, 0x19, 0x1a, 0x55, 0x1e, 0x01, 0x23, 0xe9, 0x31, 0x06, 0x34, 0x55, 0xa6, 0x81, 0xa7, 0x89, 0x7f, 0xff, 0xa6, 0x9d, 0x10, 0x00, 0xa7, 0x91, 0xa6, 0x9f, 0x10, 0x00, 0x11, 0xac, 0x99, 0x10, 0x00, 0x39  ]
+      arch: "CS_ARCH_M680X"
+      options: [ CS_OPT_DETAIL, CS_MODE_M680X_6809 ]
+      address: 0x1000
+    expected:
+      insns:
+        -
+          asm_text: "ror $10"
+          mnemonic: "ror"
+          op_str: "$10"
+          details:
+            regs_impl_read: [ cc ]
+            regs_impl_write: [ cc ]
+        -
+          asm_text: "daa"
+          mnemonic: "daa"
+          details:
+            regs_impl_read: [ cc, a ]
+            regs_impl_write: [ cc, a ]
+        -
+          asm_text: "orcc #85"
+          mnemonic: "orcc"
+          op_str: "#85"
+          details:
+            regs_impl_read: [ cc ]
+            regs_impl_write: [ cc ]
+        -
+          asm_text: "exg d, x"
+          mnemonic: "exg"
+          op_str: "d, x"
+          details:
+            regs_impl_read: [ d, x ]
+            regs_impl_write: [ d, x ]
+        -
+          asm_text: "bls $0ff2"
+          mnemonic: "bls"
+          op_str: "$0ff2"
+          details:
+            regs_impl_read: [ cc ]
+            groups: [ branch_relative, jump ]
+        -
+          asm_text: "leay 6, x"
+          mnemonic: "leay"
+          op_str: "6, x"
+          details:
+            regs_impl_read: [ cc, x ]
+            regs_impl_write: [ cc, y ]
+        -
+          asm_text: "pshs cc, b, x, u"
+          mnemonic: "pshs"
+          op_str: "cc, b, x, u"
+          details:
+            regs_impl_read: [ s, cc, b, x, u ]
+            regs_impl_write: [ s ]
+        -
+          asm_text: "lda , x++"
+          mnemonic: "lda"
+          op_str: ", x++"
+          details:
+            regs_impl_read: [ cc, x ]
+            regs_impl_write: [ cc, a, x ]
+        -
+          asm_text: "sta 32767, x"
+          mnemonic: "sta"
+          op_str: "32767, x"
+          details:
+            regs_impl_read: [ cc, a, x ]
+            regs_impl_write: [ cc ]
+        -
+          asm_text: "lda [$2017, pcr]"
+          mnemonic: "lda"
+          op_str: "[$2017, pcr]"
+          details:
+            regs_impl_read: [ cc, pc ]
+            regs_impl_write: [ cc, a ]
+        -
+          asm_text: "sta [, x++]"
+          mnemonic: "sta"
+          op_str: "[, x++]"
+          details:
+            regs_impl_read: [ cc, a, x ]
+            regs_impl_write: [ cc, x ]
+        -
+          asm_text: "lda [$1000]"
+          mnemonic: "lda"
+          op_str: "[$1000]"
+          details:
+            regs_impl_read: [ cc ]
+            regs_impl_write: [ cc, a ]
+        -
+          asm_text: "cmps [4096, x]"
+          mnemonic: "cmps"
+          op_str: "[4096, x]"
+          details:
+            regs_impl_read: [ cc, s, x ]
+            regs_impl_write: [ cc ]
+        -
+          asm_text: "rts"
+          mnemonic: "rts"
+          details:
+            regs_impl_read: [ s ]
+            regs_impl_write: [ s, pc ]
+            groups: [ return ]
+  -
+    input:
+      bytes: [ 0x0a, 0x00, 0xfe, 0x34, 0x12, 0xd0, 0xff, 0xea, 0x19, 0x56, 0x34, 0x46, 0x80 ]
+      arch: "CS_ARCH_MOS65XX"
+      options: [ CS_OPT_DETAIL]
+      address: 0x1000
+    expected:
+      insns:
+        -
+          asm_text: asl a
+          mnemonic: asl
+          op_str: a
+          details:
+            regs_impl_read: [ A ]
+            regs_impl_write: [ A, P ]
+        -
+          asm_text: brk 0xfe
+          mnemonic: brk
+          op_str: "0xfe"
+          details:
+            groups: [ int ]
+  -
+    input:
+      bytes: [ 0x97, 0x09, 0x00, 0x00, 0x37, 0x13, 0x03, 0x00, 0xdc, 0x02, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xdb, 0x3a, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x84, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x6d, 0x33, 0x17, 0x02, 0x00, 0x00, 0x00, 0x00 ]
+      arch: "CS_ARCH_BPF"
+      options: [ CS_OPT_DETAIL, CS_MODE_LITTLE_ENDIAN, CS_MODE_BPF_EXTENDED ]
+      address: 0x1000
+    expected:
+      insns:
+        -
+          asm_text: "mod64 r9, 0x31337"
+          mnemonic: mod64
+          op_str: "r9, 0x31337"
+          details:
+            groups: [ alu ]
+        -
+          asm_text: "be32 r2"
+          mnemonic: be32
+          op_str: "r2"
+          details:
+              groups: [ alu ]
+        -
+          asm_text: "ldb [0x0]"
+          mnemonic: ldb
+          op_str: "[0x0]"
+          details:
+            regs_write: [ r0 ]
+            groups: [ load ]
+        -
+          asm_text: "xadddw [r10+0x100], r3"
+          mnemonic: xadddw
+          op_str: "[r10+0x100], r3"
+          details:
+            groups: [ store ]
+        -
+          asm_text: "neg r2"
+          mnemonic: neg
+          op_str: "r2"
+          details:
+            groups: [ alu ]
+        -
+          asm_text: "jsgt r3, r3, +0x217"
+          mnemonic: jsgt
+          op_str: "r3, r3, +0x217"
+          details:
+            groups: [ jump ]
+  -
+    input:
+      bytes: [ 0x02, 0x00, 0xbb, 0x27, 0x50, 0x7a, 0xbd, 0x23, 0xd0, 0xff, 0xde, 0x23, 0x00, 0x00, 0x5e, 0xb7 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ CS_OPT_DETAIL, CS_MODE_LITTLE_ENDIAN ]
+      address: 0x1000
+    expected:
+      insns:
+        -
+          asm_text: "ldah $15,2($13)"
+          mnemonic: "ldah"
+          op_str: "$15,2($13)"
+          details:
+            regs_impl_write: [ $28 ]
+        -
+          asm_text: "lda $15,0x7a50($15)"
+          mnemonic: "lda"
+          op_str: "$15,0x7a50($15)"
+          details:
+            regs_impl_write: [ $28 ]
+        -
+          asm_text: "lda $30,0xffd0($30)"
+          mnemonic: "lda"
+          op_str: "$30,0xffd0($30)"
+          details:
+            regs_impl_write: [ $28 ]
+        -
+          asm_text: "stq $12,0($30)"
+          mnemonic: "stq"
+          op_str: "$12,0($30)"
+          details:
+            regs_impl_write: [ $28 ]
+
+  -
+    input:
+      bytes: [ 0x27, 0xbb, 0x00, 0x02, 0x23, 0xbd, 0x7a, 0x50, 0x23, 0xde, 0xff, 0xd0, 0xb7, 0x5e, 0x00, 0x00 ]
+      arch: "CS_ARCH_ALPHA"
+      options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN ]
+      address: 0x1000
+    expected:
+      insns:
+        -
+          asm_text: "ldah $15,2($13)"
+          mnemonic: "ldah"
+          op_str: "$15,2($13)"
+          details:
+            regs_impl_write: [ $28 ]
+        -
+          asm_text: "lda $15,0x7a50($15)"
+          mnemonic: "lda"
+          op_str: "$15,0x7a50($15)"
+          details:
+            regs_impl_write: [ $28 ]
+        -
+          asm_text: "lda $30,0xffd0($30)"
+          mnemonic: "lda"
+          op_str: "$30,0xffd0($30)"
+          details:
+            regs_impl_write: [ $28 ]
+        -
+          asm_text: "stq $12,0($30)"
+          mnemonic: "stq"
+          op_str: "$12,0($30)"
+          details:
+            regs_impl_write: [ $28 ]
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x50, 0xa2, 0x00, 0x01, 0x58, 0x20, 0x00, 0x00, 0x44, 0xa1, 0x00, 0x41, 0x18, 0x40, 0x00, 0x20, 0x08, 0xa2, 0x01, 0x60, 0x48, 0xa1, 0x01, 0x61, 0x18, 0xc0, 0x00, 0x00, 0x14, 0xa1, 0x00, 0x0f, 0x0d, 0x61, 0x00, 0x0f, 0x0e, 0x61, 0x00, 0x01, 0x18, 0x60, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x0c, 0xa0, 0x03, 0xff, 0xc0, 0x1f, 0x00, 0x00, 0x04, 0x00, 0x00, 0x10, 0x04, 0x00, 0x04, 0x22, 0x51, 0x83, 0x04, 0x22, 0x51, 0xc3, 0x04, 0x22, 0x51, 0x83, 0x04, 0x2f, 0x71, 0x83, 0x04, 0x2f, 0x71, 0xc3, 0x04, 0x2f, 0x71, 0x83, 0x04, 0x41, 0x53, 0x43, 0x04, 0x41, 0x53, 0x63, 0x04, 0x41, 0x53, 0x03, 0x04, 0x41, 0x12, 0x00, 0x04, 0x41, 0x16, 0x00, 0x04, 0x41, 0x16, 0x20, 0x04, 0x41, 0x42, 0x00, 0x04, 0x41, 0x46, 0x00, 0x04, 0x41, 0x46, 0x20, 0x04, 0x41, 0x12, 0x40, 0x04, 0x41, 0x12, 0x60, 0x04, 0x41, 0x42, 0x40, 0x04, 0x41, 0x42, 0x60, 0x04, 0x41, 0x18, 0x00, 0x04, 0x41, 0x08, 0x00, 0x04, 0x41, 0x13, 0x80, 0x04, 0x41, 0x13, 0xa0, 0x04, 0x41, 0x52, 0x80, 0x04, 0x41, 0x52, 0xa0, 0x04, 0x5e, 0x72, 0x80, 0x04, 0x41, 0x42, 0x80, 0x04, 0x41, 0x52, 0xc0, 0x04, 0x41, 0x52, 0xe0, 0x04, 0x41, 0x42, 0xc0, 0x04, 0x41, 0x42, 0xe0, 0x14, 0x00, 0xde, 0xad  ]
+      arch: "CS_ARCH_HPPA"
+      options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_HPPA_20 ]
+      address: 0x1000
+    expected:
+      insns:
+        -
+          asm_text: "ldsid (sr1,r1),rp"
+          mnemonic: "ldsid"
+          op_str: "(sr1,r1),rp"
+          details:
+            groups: [ system_control ]
+        -
+          asm_text: "mtsp r1,sr1"
+          mnemonic: "mtsp"
+          op_str: "r1,sr1"
+          details:
+            groups: [ system_control ]
+        -
+          asm_text: "mfsp sr1,r1"
+          mnemonic: "mfsp"
+          op_str: "sr1,r1"
+          details:
+            groups: [ system_control ]
+        -
+          asm_text: "mtctl r1,cr2"
+          mnemonic: "mtctl"
+          op_str: "r1,cr2"
+          details:
+            groups: [ system_control ]
+        -
+          asm_text: "mfctl cr1,rp"
+          mnemonic: "mfctl"
+          op_str: "cr1,rp"
+          details:
+            groups: [ system_control ]
+        -
+          asm_text: "mfctl,w sar,r1"
+          mnemonic: "mfctl,w"
+          op_str: "sar,r1"
+          details:
+            groups: [ system_control ]
+        -
+          asm_text: "mtsarcm r1"
+          mnemonic: "mtsarcm"
+          op_str: "r1"
+          details:
+            groups: [ system_control ]
+        -
+          asm_text: "mfia r1"
+          mnemonic: "mfia"
+          op_str: "r1"
+          details:
+            groups: [ system_control ]
+        -
+          asm_text: "ssm 0xf,r1"
+          mnemonic: "ssm"
+          op_str: "0xf,r1"
+          details:
+            groups: [ system_control ]
+        -
+          asm_text: "rsm 0xf,r1"
+          mnemonic: "rsm"
+          op_str: "0xf,r1"
+          details:
+            groups: [ system_control ]
+        -
+          asm_text: "mtsm r1"
+          mnemonic: "mtsm"
+          op_str: "r1"
+          details:
+            groups: [ system_control ]
+        -
+          asm_text: "rfi"
+          mnemonic: "rfi"
+          details:
+            groups: [ system_control ]
+        -
+          asm_text: "rfi,r"
+          mnemonic: "rfi,r"
+          details:
+            regs_impl_write: [ r1, r8, r9, r16, r17, r24, r25 ]
+            groups: [ system_control ]
+        -
+          asm_text: "break 0x1f,0x1ffe"
+          mnemonic: "break"
+          op_str: "0x1f,0x1ffe"
+          details:
+            groups: [ system_control ]
+        -
+          asm_text: "sync"
+          mnemonic: "sync"
+          details:
+            groups: [ system_control ]
+        -
+          asm_text: "syncdma"
+          mnemonic: "syncdma"
+          details:
+            groups: [ system_control ]
+        -
+          asm_text: "probe,r (sr1,r1),rp,r3"
+          mnemonic: "probe,r"
+          op_str: "(sr1,r1),rp,r3"
+          details:
+            groups: [ system_control ]
+        -
+          asm_text: "probe,w (sr1,r1),rp,r3"
+          mnemonic: "probe,w"
+          op_str: "(sr1,r1),rp,r3"
+          details:
+            groups: [ system_control ]
+        -
+          asm_text: "probe,r (sr1,r1),rp,r3"
+          mnemonic: "probe,r"
+          op_str: "(sr1,r1),rp,r3"
+          details:
+            groups: [ system_control ]
+        -
+          asm_text: "probei,r (sr1,r1),0xf,r3"
+          mnemonic: "probei,r"
+          op_str: "(sr1,r1),0xf,r3"
+          details:
+            groups: [ system_control ]
+        -
+          asm_text: "probei,w (sr1,r1),0xf,r3"
+          mnemonic: "probei,w"
+          op_str: "(sr1,r1),0xf,r3"
+          details:
+            groups: [ system_control ]
+        -
+          asm_text: "probei,r (sr1,r1),0xf,r3"
+          mnemonic: "probei,r"
+          op_str: "(sr1,r1),0xf,r3"
+          details:
+            groups: [ system_control ]
+        -
+          asm_text: "lpa r1(sr1,rp),r3"
+          mnemonic: "lpa"
+          op_str: "r1(sr1,rp),r3"
+          details:
+            groups: [ system_control ]
+        -
+          asm_text: "lpa,m r1(sr1,rp),r3"
+          mnemonic: "lpa,m"
+          op_str: "r1(sr1,rp),r3"
+          details:
+            groups: [ system_control ]
+        -
+          asm_text: "lci r1(sr1,rp),r3"
+          mnemonic: "lci"
+          op_str: "r1(sr1,rp),r3"
+          details:
+            groups: [ system_control ]
+        -
+          asm_text: "pdtlb r1(rp)"
+          mnemonic: "pdtlb"
+          op_str: "r1(rp)"
+          details:
+            groups: [ system_control ]
+        -
+          asm_text: "pdtlb,l r1(rp)"
+          mnemonic: "pdtlb,l"
+          op_str: "r1(rp)"
+          details:
+            groups: [ system_control ]
+        -
+          asm_text: "pdtlb,l,m r1(rp)"
+          mnemonic: "pdtlb,l,m"
+          op_str: "r1(rp)"
+          details:
+            groups: [ system_control ]
+        -
+          asm_text: "pitlb r1(sr1,rp)"
+          mnemonic: "pitlb"
+          op_str: "r1(sr1,rp)"
+          details:
+            groups: [ system_control ]
+        -
+          asm_text: "pitlb,l r1(sr1,rp)"
+          mnemonic: "pitlb,l"
+          op_str: "r1(sr1,rp)"
+          details:
+            groups: [ system_control ]
+        -
+          asm_text: "pitlb,l,m r1(sr1,rp)"
+          mnemonic: "pitlb,l,m"
+          op_str: "r1(sr1,rp)"
+          details:
+            groups: [ system_control ]
+        -
+          asm_text: "pdtlbe r1(rp)"
+          mnemonic: "pdtlbe"
+          op_str: "r1(rp)"
+          details:
+            groups: [ system_control ]
+        -
+          asm_text: "pdtlbe,m r1(rp)"
+          mnemonic: "pdtlbe,m"
+          op_str: "r1(rp)"
+          details:
+            groups: [ system_control ]
+        -
+          asm_text: "pitlbe r1(sr1,rp)"
+          mnemonic: "pitlbe"
+          op_str: "r1(sr1,rp)"
+          details:
+            groups: [ system_control ]
+        -
+          asm_text: "pitlbe,m r1(sr1,rp)"
+          mnemonic: "pitlbe,m"
+          op_str: "r1(sr1,rp)"
+          details:
+            groups: [ system_control ]
+        -
+          asm_text: "idtlbt r1,rp"
+          mnemonic: "idtlbt"
+          op_str: "r1,rp"
+          details:
+            groups: [ system_control ]
+        -
+          asm_text: "iitlbt r1,rp"
+          mnemonic: "iitlbt"
+          op_str: "r1,rp"
+          details:
+            groups: [ system_control ]
+        -
+          asm_text: "pdc r1(rp)"
+          mnemonic: "pdc"
+          op_str: "r1(rp)"
+          details:
+            groups: [ system_control ]
+        -
+          asm_text: "pdc,m r1(rp)"
+          mnemonic: "pdc,m"
+          op_str: "r1(rp)"
+          details:
+            groups: [ system_control ]
+        -
+          asm_text: "fdc r1(sr1,rp)"
+          mnemonic: "fdc"
+          op_str: "r1(sr1,rp)"
+          details:
+            groups: [ system_control ]
+        -
+          asm_text: "fdc,m r1(sr1,rp)"
+          mnemonic: "fdc,m"
+          op_str: "r1(sr1,rp)"
+          details:
+            groups: [ system_control ]
+        -
+          asm_text: "fdc 0xf(sr1,rp)"
+          mnemonic: "fdc"
+          op_str: "0xf(sr1,rp)"
+          details:
+            groups: [ system_control ]
+        -
+          asm_text: "fic r1(sr1,rp)"
+          mnemonic: "fic"
+          op_str: "r1(sr1,rp)"
+          details:
+            groups: [ system_control ]
+        -
+          asm_text: "fdce r1(sr1,rp)"
+          mnemonic: "fdce"
+          op_str: "r1(sr1,rp)"
+          details:
+            groups: [ system_control ]
+        -
+          asm_text: "fdce,m r1(sr1,rp)"
+          mnemonic: "fdce,m"
+          op_str: "r1(sr1,rp)"
+          details:
+            groups: [ system_control ]
+        -
+          asm_text: "fice r1(sr1,rp)"
+          mnemonic: "fice"
+          op_str: "r1(sr1,rp)"
+          details:
+            groups: [ system_control ]
+        -
+          asm_text: "fice,m r1(sr1,rp)"
+          mnemonic: "fice,m"
+          op_str: "r1(sr1,rp)"
+          details:
+            groups: [ system_control ]
+        -
+          asm_text: "diag 0xdead"
+          mnemonic: "diag"
+          op_str: "0xdead"
+          details:
+            groups: [ system_control ]
+  -
+    input:
+      bytes: [ 0xa2, 0x50, 0x20, 0x00, 0x20, 0x58, 0x01, 0x00, 0xa1, 0x44, 0x00, 0x00, 0x40, 0x18, 0x41, 0x00, 0xa2, 0x08, 0x20, 0x00, 0xa1, 0x48, 0x60, 0x01, 0xc0, 0x18, 0x61, 0x01, 0xa1, 0x14, 0x00, 0x00, 0x61, 0x0d, 0x0f, 0x00, 0x61, 0x0e, 0x0f, 0x00, 0x60, 0x18, 0x01, 0x00, 0x00, 0x0c, 0x00, 0x00, 0xa0, 0x0c, 0x00, 0x00, 0x1f, 0xc0, 0xff, 0x03, 0x00, 0x04, 0x00, 0x00, 0x00, 0x04, 0x10, 0x00, 0x83, 0x51, 0x22, 0x04, 0xc3, 0x51, 0x22, 0x04, 0x83, 0x51, 0x22, 0x04, 0x83, 0x71, 0x2f, 0x04, 0xc3, 0x71, 0x2f, 0x04, 0x83, 0x71, 0x2f, 0x04, 0x43, 0x53, 0x41, 0x04, 0x63, 0x53, 0x41, 0x04, 0x03, 0x53, 0x41, 0x04, 0x00, 0x12, 0x41, 0x04, 0x00, 0x16, 0x41, 0x04, 0x20, 0x16, 0x41, 0x04, 0x00, 0x42, 0x41, 0x04, 0x00, 0x46, 0x41, 0x04, 0x20, 0x46, 0x41, 0x04, 0x40, 0x12, 0x41, 0x04, 0x60, 0x12, 0x41, 0x04, 0x40, 0x42, 0x41, 0x04, 0x60, 0x42, 0x41, 0x04, 0x00, 0x18, 0x41, 0x04, 0x00, 0x08, 0x41, 0x04, 0x80, 0x13, 0x41, 0x04, 0xa0, 0x13, 0x41, 0x04, 0x80, 0x52, 0x41, 0x04, 0xa0, 0x52, 0x41, 0x04, 0x80, 0x72, 0x5e, 0x04, 0x80, 0x42, 0x41, 0x04, 0xc0, 0x52, 0x41, 0x04, 0xe0, 0x52, 0x41, 0x04, 0xc0, 0x42, 0x41, 0x04, 0xe0, 0x42, 0x41, 0x04, 0xad, 0xde, 0x00, 0x14  ]
+      arch: "CS_ARCH_HPPA"
+      options: [ CS_OPT_DETAIL, CS_MODE_LITTLE_ENDIAN, CS_MODE_HPPA_20 ]
+      address: 0x1000
+    expected:
+      insns:
+        -
+          asm_text: "ldsid (sr1,r1),rp"
+          mnemonic: "ldsid"
+          op_str: "(sr1,r1),rp"
+          details:
+            groups: [ system_control ]
+        -
+          asm_text: "mtsp r1,sr1"
+          mnemonic: "mtsp"
+          op_str: "r1,sr1"
+          details:
+            groups: [ system_control ]
+        -
+          asm_text: "mfsp sr1,r1"
+          mnemonic: "mfsp"
+          op_str: "sr1,r1"
+          details:
+            groups: [ system_control ]
+        -
+          asm_text: "mtctl r1,cr2"
+          mnemonic: "mtctl"
+          op_str: "r1,cr2"
+          details:
+            groups: [ system_control ]
+        -
+          asm_text: "mfctl cr1,rp"
+          mnemonic: "mfctl"
+          op_str: "cr1,rp"
+          details:
+            groups: [ system_control ]
+        -
+          asm_text: "mfctl,w sar,r1"
+          mnemonic: "mfctl,w"
+          op_str: "sar,r1"
+          details:
+            groups: [ system_control ]
+        -
+          asm_text: "mtsarcm r1"
+          mnemonic: "mtsarcm"
+          op_str: "r1"
+          details:
+            groups: [ system_control ]
+        -
+          asm_text: "mfia r1"
+          mnemonic: "mfia"
+          op_str: "r1"
+          details:
+            groups: [ system_control ]
+        -
+          asm_text: "ssm 0xf,r1"
+          mnemonic: "ssm"
+          op_str: "0xf,r1"
+          details:
+            groups: [ system_control ]
+        -
+          asm_text: "rsm 0xf,r1"
+          mnemonic: "rsm"
+          op_str: "0xf,r1"
+          details:
+            groups: [ system_control ]
+        -
+          asm_text: "mtsm r1"
+          mnemonic: "mtsm"
+          op_str: "r1"
+          details:
+            groups: [ system_control ]
+        -
+          asm_text: "rfi"
+          mnemonic: "rfi"
+          details:
+            groups: [ system_control ]
+        -
+          asm_text: "rfi,r"
+          mnemonic: "rfi,r"
+          details:
+            regs_impl_write: [ r1, r8, r9, r16, r17, r24, r25 ]
+            groups: [ system_control ]
+        -
+          asm_text: "break 0x1f,0x1ffe"
+          mnemonic: "break"
+          op_str: "0x1f,0x1ffe"
+          details:
+            groups: [ system_control ]
+        -
+          asm_text: "sync"
+          mnemonic: "sync"
+          details:
+            groups: [ system_control ]
+        -
+          asm_text: "syncdma"
+          mnemonic: "syncdma"
+          details:
+            groups: [ system_control ]
+        -
+          asm_text: "probe,r (sr1,r1),rp,r3"
+          mnemonic: "probe,r"
+          op_str: "(sr1,r1),rp,r3"
+          details:
+            groups: [ system_control ]
+        -
+          asm_text: "probe,w (sr1,r1),rp,r3"
+          mnemonic: "probe,w"
+          op_str: "(sr1,r1),rp,r3"
+          details:
+            groups: [ system_control ]
+        -
+          asm_text: "probe,r (sr1,r1),rp,r3"
+          mnemonic: "probe,r"
+          op_str: "(sr1,r1),rp,r3"
+          details:
+            groups: [ system_control ]
+        -
+          asm_text: "probei,r (sr1,r1),0xf,r3"
+          mnemonic: "probei,r"
+          op_str: "(sr1,r1),0xf,r3"
+          details:
+            groups: [ system_control ]
+        -
+          asm_text: "probei,w (sr1,r1),0xf,r3"
+          mnemonic: "probei,w"
+          op_str: "(sr1,r1),0xf,r3"
+          details:
+            groups: [ system_control ]
+        -
+          asm_text: "probei,r (sr1,r1),0xf,r3"
+          mnemonic: "probei,r"
+          op_str: "(sr1,r1),0xf,r3"
+          details:
+            groups: [ system_control ]
+        -
+          asm_text: "lpa r1(sr1,rp),r3"
+          mnemonic: "lpa"
+          op_str: "r1(sr1,rp),r3"
+          details:
+            groups: [ system_control ]
+        -
+          asm_text: "lpa,m r1(sr1,rp),r3"
+          mnemonic: "lpa,m"
+          op_str: "r1(sr1,rp),r3"
+          details:
+            groups: [ system_control ]
+        -
+          asm_text: "lci r1(sr1,rp),r3"
+          mnemonic: "lci"
+          op_str: "r1(sr1,rp),r3"
+          details:
+            groups: [ system_control ]
+        -
+          asm_text: "pdtlb r1(rp)"
+          mnemonic: "pdtlb"
+          op_str: "r1(rp)"
+          details:
+            groups: [ system_control ]
+        -
+          asm_text: "pdtlb,l r1(rp)"
+          mnemonic: "pdtlb,l"
+          op_str: "r1(rp)"
+          details:
+            groups: [ system_control ]
+        -
+          asm_text: "pdtlb,l,m r1(rp)"
+          mnemonic: "pdtlb,l,m"
+          op_str: "r1(rp)"
+          details:
+            groups: [ system_control ]
+        -
+          asm_text: "pitlb r1(sr1,rp)"
+          mnemonic: "pitlb"
+          op_str: "r1(sr1,rp)"
+          details:
+            groups: [ system_control ]
+        -
+          asm_text: "pitlb,l r1(sr1,rp)"
+          mnemonic: "pitlb,l"
+          op_str: "r1(sr1,rp)"
+          details:
+            groups: [ system_control ]
+        -
+          asm_text: "pitlb,l,m r1(sr1,rp)"
+          mnemonic: "pitlb,l,m"
+          op_str: "r1(sr1,rp)"
+          details:
+            groups: [ system_control ]
+        -
+          asm_text: "pdtlbe r1(rp)"
+          mnemonic: "pdtlbe"
+          op_str: "r1(rp)"
+          details:
+            groups: [ system_control ]
+        -
+          asm_text: "pdtlbe,m r1(rp)"
+          mnemonic: "pdtlbe,m"
+          op_str: "r1(rp)"
+          details:
+            groups: [ system_control ]
+        -
+          asm_text: "pitlbe r1(sr1,rp)"
+          mnemonic: "pitlbe"
+          op_str: "r1(sr1,rp)"
+          details:
+            groups: [ system_control ]
+        -
+          asm_text: "pitlbe,m r1(sr1,rp)"
+          mnemonic: "pitlbe,m"
+          op_str: "r1(sr1,rp)"
+          details:
+            groups: [ system_control ]
+        -
+          asm_text: "idtlbt r1,rp"
+          mnemonic: "idtlbt"
+          op_str: "r1,rp"
+          details:
+            groups: [ system_control ]
+        -
+          asm_text: "iitlbt r1,rp"
+          mnemonic: "iitlbt"
+          op_str: "r1,rp"
+          details:
+            groups: [ system_control ]
+        -
+          asm_text: "pdc r1(rp)"
+          mnemonic: "pdc"
+          op_str: "r1(rp)"
+          details:
+            groups: [ system_control ]
+        -
+          asm_text: "pdc,m r1(rp)"
+          mnemonic: "pdc,m"
+          op_str: "r1(rp)"
+          details:
+            groups: [ system_control ]
+        -
+          asm_text: "fdc r1(sr1,rp)"
+          mnemonic: "fdc"
+          op_str: "r1(sr1,rp)"
+          details:
+            groups: [ system_control ]
+        -
+          asm_text: "fdc,m r1(sr1,rp)"
+          mnemonic: "fdc,m"
+          op_str: "r1(sr1,rp)"
+          details:
+            groups: [ system_control ]
+        -
+          asm_text: "fdc 0xf(sr1,rp)"
+          mnemonic: "fdc"
+          op_str: "0xf(sr1,rp)"
+          details:
+            groups: [ system_control ]
+        -
+          asm_text: "fic r1(sr1,rp)"
+          mnemonic: "fic"
+          op_str: "r1(sr1,rp)"
+          details:
+            groups: [ system_control ]
+        -
+          asm_text: "fdce r1(sr1,rp)"
+          mnemonic: "fdce"
+          op_str: "r1(sr1,rp)"
+          details:
+            groups: [ system_control ]
+        -
+          asm_text: "fdce,m r1(sr1,rp)"
+          mnemonic: "fdce,m"
+          op_str: "r1(sr1,rp)"
+          details:
+            groups: [ system_control ]
+        -
+          asm_text: "fice r1(sr1,rp)"
+          mnemonic: "fice"
+          op_str: "r1(sr1,rp)"
+          details:
+            groups: [ system_control ]
+        -
+          asm_text: "fice,m r1(sr1,rp)"
+          mnemonic: "fice,m"
+          op_str: "r1(sr1,rp)"
+          details:
+            groups: [ system_control ]
+        -
+          asm_text: "diag 0xdead"
+          mnemonic: "diag"
+          op_str: "0xdead"
+          details:
+            groups: [ system_control ]
+  -
+    input:
+      bytes: [ 0x24, 0x41, 0x40, 0xc3, 0x24, 0x41, 0x60, 0xc3, 0x24, 0x41, 0x40, 0xe3, 0x24, 0x41, 0x60, 0xe3, 0x24, 0x41, 0x68, 0xe3, 0x2c, 0x41, 0x40, 0xc3, 0x2c, 0x41, 0x60, 0xc3, 0x2c, 0x41, 0x40, 0xe3, 0x2c, 0x41, 0x60, 0xe3, 0x2c, 0x41, 0x68, 0xe3, 0x24, 0x62, 0x42, 0xc1, 0x24, 0x62, 0x62, 0xc1, 0x24, 0x62, 0x42, 0xe1, 0x24, 0x62, 0x46, 0xe1, 0x24, 0x62, 0x62, 0xe1, 0x24, 0x62, 0x6a, 0xe1, 0x2c, 0x62, 0x42, 0xc1, 0x2c, 0x62, 0x62, 0xc1, 0x2c, 0x62, 0x42, 0xe1, 0x2c, 0x62, 0x46, 0xe1, 0x2c, 0x62, 0x62, 0xe1, 0x2c, 0x62, 0x6a, 0xe1, 0x24, 0x3e, 0x50, 0xc2, 0x24, 0x3e, 0x50, 0xe2, 0x24, 0x3e, 0x70, 0xe2, 0x24, 0x3e, 0x78, 0xe2, 0x2c, 0x3e, 0x50, 0xc2, 0x2c, 0x3e, 0x50, 0xe2, 0x2c, 0x3e, 0x70, 0xe2, 0x2c, 0x3e, 0x78, 0xe2, 0x24, 0x5e, 0x52, 0xc1, 0x24, 0x5e, 0x52, 0xe1, 0x24, 0x5e, 0x56, 0xe1, 0x24, 0x5e, 0x72, 0xe1, 0x24, 0x5e, 0x7a, 0xe1, 0x2c, 0x5e, 0x52, 0xc1, 0x2c, 0x5e, 0x52, 0xe1, 0x2c, 0x5e, 0x56, 0xe1, 0x2c, 0x5e, 0x72, 0xe1, 0x2c, 0x5e, 0x7a, 0xe1  ]
+      arch: "CS_ARCH_HPPA"
+      options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_HPPA_11 ]
+      address: 0x1000
+    expected:
+      insns:
+        -
+          asm_text: "cldwx,3 r1(sr1,rp),r3"
+          mnemonic: "cldwx,3"
+          op_str: "r1(sr1,rp),r3"
+          details:
+            groups: [ assist ]
+        -
+          asm_text: "cldwx,3,s r1(sr1,rp),r3"
+          mnemonic: "cldwx,3,s"
+          op_str: "r1(sr1,rp),r3"
+          details:
+            groups: [ assist ]
+        -
+          asm_text: "cldwx,3,m r1(sr1,rp),r3"
+          mnemonic: "cldwx,3,m"
+          op_str: "r1(sr1,rp),r3"
+          details:
+            groups: [ assist ]
+        -
+          asm_text: "cldwx,3,sm r1(sr1,rp),r3"
+          mnemonic: "cldwx,3,sm"
+          op_str: "r1(sr1,rp),r3"
+          details:
+            groups: [ assist ]
+        -
+          asm_text: "cldwx,3,sm,sl r1(sr1,rp),r3"
+          mnemonic: "cldwx,3,sm,sl"
+          op_str: "r1(sr1,rp),r3"
+          details:
+            groups: [ assist ]
+        -
+          asm_text: "clddx,3 r1(sr1,rp),r3"
+          mnemonic: "clddx,3"
+          op_str: "r1(sr1,rp),r3"
+          details:
+            groups: [ assist ]
+        -
+          asm_text: "clddx,3,s r1(sr1,rp),r3"
+          mnemonic: "clddx,3,s"
+          op_str: "r1(sr1,rp),r3"
+          details:
+            groups: [ assist ]
+        -
+          asm_text: "clddx,3,m r1(sr1,rp),r3"
+          mnemonic: "clddx,3,m"
+          op_str: "r1(sr1,rp),r3"
+          details:
+            groups: [ assist ]
+        -
+          asm_text: "clddx,3,sm r1(sr1,rp),r3"
+          mnemonic: "clddx,3,sm"
+          op_str: "r1(sr1,rp),r3"
+          details:
+            groups: [ assist ]
+        -
+          asm_text: "clddx,3,sm,sl r1(sr1,rp),r3"
+          mnemonic: "clddx,3,sm,sl"
+          op_str: "r1(sr1,rp),r3"
+          details:
+            groups: [ assist ]
+        -
+          asm_text: "cstwx,3 r1,rp(sr1,r3)"
+          mnemonic: "cstwx,3"
+          op_str: "r1,rp(sr1,r3)"
+          details:
+            groups: [ assist ]
+        -
+          asm_text: "cstwx,3,s r1,rp(sr1,r3)"
+          mnemonic: "cstwx,3,s"
+          op_str: "r1,rp(sr1,r3)"
+          details:
+            groups: [ assist ]
+        -
+          asm_text: "cstwx,3,m r1,rp(sr1,r3)"
+          mnemonic: "cstwx,3,m"
+          op_str: "r1,rp(sr1,r3)"
+          details:
+            groups: [ assist ]
+        -
+          asm_text: "cstwx,3,m,bc r1,rp(sr1,r3)"
+          mnemonic: "cstwx,3,m,bc"
+          op_str: "r1,rp(sr1,r3)"
+          details:
+            groups: [ assist ]
+        -
+          asm_text: "cstwx,3,sm r1,rp(sr1,r3)"
+          mnemonic: "cstwx,3,sm"
+          op_str: "r1,rp(sr1,r3)"
+          details:
+            groups: [ assist ]
+        -
+          asm_text: "cstwx,3,sm,sl r1,rp(sr1,r3)"
+          mnemonic: "cstwx,3,sm,sl"
+          op_str: "r1,rp(sr1,r3)"
+          details:
+            groups: [ assist ]
+        -
+          asm_text: "cstdx,3 r1,rp(sr1,r3)"
+          mnemonic: "cstdx,3"
+          op_str: "r1,rp(sr1,r3)"
+          details:
+            groups: [ assist ]
+        -
+          asm_text: "cstdx,3,s r1,rp(sr1,r3)"
+          mnemonic: "cstdx,3,s"
+          op_str: "r1,rp(sr1,r3)"
+          details:
+            groups: [ assist ]
+        -
+          asm_text: "cstdx,3,m r1,rp(sr1,r3)"
+          mnemonic: "cstdx,3,m"
+          op_str: "r1,rp(sr1,r3)"
+          details:
+            groups: [ assist ]
+        -
+          asm_text: "cstdx,3,m,bc r1,rp(sr1,r3)"
+          mnemonic: "cstdx,3,m,bc"
+          op_str: "r1,rp(sr1,r3)"
+          details:
+            groups: [ assist ]
+        -
+          asm_text: "cstdx,3,sm r1,rp(sr1,r3)"
+          mnemonic: "cstdx,3,sm"
+          op_str: "r1,rp(sr1,r3)"
+          details:
+            groups: [ assist ]
+        -
+          asm_text: "cstdx,3,sm,sl r1,rp(sr1,r3)"
+          mnemonic: "cstdx,3,sm,sl"
+          op_str: "r1,rp(sr1,r3)"
+          details:
+            groups: [ assist ]
+        -
+          asm_text: "cldws,3 0xf(sr1,r1),rp"
+          mnemonic: "cldws,3"
+          op_str: "0xf(sr1,r1),rp"
+          details:
+            groups: [ assist ]
+        -
+          asm_text: "cldws,3,ma 0xf(sr1,r1),rp"
+          mnemonic: "cldws,3,ma"
+          op_str: "0xf(sr1,r1),rp"
+          details:
+            groups: [ assist ]
+        -
+          asm_text: "cldws,3,mb 0xf(sr1,r1),rp"
+          mnemonic: "cldws,3,mb"
+          op_str: "0xf(sr1,r1),rp"
+          details:
+            groups: [ assist ]
+        -
+          asm_text: "cldws,3,mb,sl 0xf(sr1,r1),rp"
+          mnemonic: "cldws,3,mb,sl"
+          op_str: "0xf(sr1,r1),rp"
+          details:
+            groups: [ assist ]
+        -
+          asm_text: "cldds,3 0xf(sr1,r1),rp"
+          mnemonic: "cldds,3"
+          op_str: "0xf(sr1,r1),rp"
+          details:
+            groups: [ assist ]
+        -
+          asm_text: "cldds,3,ma 0xf(sr1,r1),rp"
+          mnemonic: "cldds,3,ma"
+          op_str: "0xf(sr1,r1),rp"
+          details:
+            groups: [ assist ]
+        -
+          asm_text: "cldds,3,mb 0xf(sr1,r1),rp"
+          mnemonic: "cldds,3,mb"
+          op_str: "0xf(sr1,r1),rp"
+          details:
+            groups: [ assist ]
+        -
+          asm_text: "cldds,3,mb,sl 0xf(sr1,r1),rp"
+          mnemonic: "cldds,3,mb,sl"
+          op_str: "0xf(sr1,r1),rp"
+          details:
+            groups: [ assist ]
+        -
+          asm_text: "cstws,3 r1,0xf(sr1,rp)"
+          mnemonic: "cstws,3"
+          op_str: "r1,0xf(sr1,rp)"
+          details:
+            groups: [ assist ]
+        -
+          asm_text: "cstws,3,ma r1,0xf(sr1,rp)"
+          mnemonic: "cstws,3,ma"
+          op_str: "r1,0xf(sr1,rp)"
+          details:
+            groups: [ assist ]
+        -
+          asm_text: "cstws,3,ma,bc r1,0xf(sr1,rp)"
+          mnemonic: "cstws,3,ma,bc"
+          op_str: "r1,0xf(sr1,rp)"
+          details:
+            groups: [ assist ]
+        -
+          asm_text: "cstws,3,mb r1,0xf(sr1,rp)"
+          mnemonic: "cstws,3,mb"
+          op_str: "r1,0xf(sr1,rp)"
+          details:
+            groups: [ assist ]
+        -
+          asm_text: "cstws,3,mb,sl r1,0xf(sr1,rp)"
+          mnemonic: "cstws,3,mb,sl"
+          op_str: "r1,0xf(sr1,rp)"
+          details:
+            groups: [ assist ]
+        -
+          asm_text: "cstds,3 r1,0xf(sr1,rp)"
+          mnemonic: "cstds,3"
+          op_str: "r1,0xf(sr1,rp)"
+          details:
+            groups: [ assist ]
+        -
+          asm_text: "cstds,3,ma r1,0xf(sr1,rp)"
+          mnemonic: "cstds,3,ma"
+          op_str: "r1,0xf(sr1,rp)"
+          details:
+            groups: [ assist ]
+        -
+          asm_text: "cstds,3,ma,bc r1,0xf(sr1,rp)"
+          mnemonic: "cstds,3,ma,bc"
+          op_str: "r1,0xf(sr1,rp)"
+          details:
+            groups: [ assist ]
+        -
+          asm_text: "cstds,3,mb r1,0xf(sr1,rp)"
+          mnemonic: "cstds,3,mb"
+          op_str: "r1,0xf(sr1,rp)"
+          details:
+            groups: [ assist ]
+        -
+          asm_text: "cstds,3,mb,sl r1,0xf(sr1,rp)"
+          mnemonic: "cstds,3,mb,sl"
+          op_str: "r1,0xf(sr1,rp)"
+          details:
+            groups: [ assist ]
+  -
+    input:
+      bytes: [ 0xc3, 0x40, 0x41, 0x24, 0xc3, 0x60, 0x41, 0x24, 0xe3, 0x40, 0x41, 0x24, 0xe3, 0x60, 0x41, 0x24, 0xe3, 0x68, 0x41, 0x24, 0xc3, 0x40, 0x41, 0x2c, 0xc3, 0x60, 0x41, 0x2c, 0xe3, 0x40, 0x41, 0x2c, 0xe3, 0x60, 0x41, 0x2c, 0xe3, 0x68, 0x41, 0x2c, 0xc1, 0x42, 0x62, 0x24, 0xc1, 0x62, 0x62, 0x24, 0xe1, 0x42, 0x62, 0x24, 0xe1, 0x46, 0x62, 0x24, 0xe1, 0x62, 0x62, 0x24, 0xe1, 0x6a, 0x62, 0x24, 0xc1, 0x42, 0x62, 0x2c, 0xc1, 0x62, 0x62, 0x2c, 0xe1, 0x42, 0x62, 0x2c, 0xe1, 0x46, 0x62, 0x2c, 0xe1, 0x62, 0x62, 0x2c, 0xe1, 0x6a, 0x62, 0x2c, 0xc2, 0x50, 0x3e, 0x24, 0xe2, 0x50, 0x3e, 0x24, 0xe2, 0x70, 0x3e, 0x24, 0xe2, 0x78, 0x3e, 0x24, 0xc2, 0x50, 0x3e, 0x2c, 0xe2, 0x50, 0x3e, 0x2c, 0xe2, 0x70, 0x3e, 0x2c, 0xe2, 0x78, 0x3e, 0x2c, 0xc1, 0x52, 0x5e, 0x24, 0xe1, 0x52, 0x5e, 0x24, 0xe1, 0x56, 0x5e, 0x24, 0xe1, 0x72, 0x5e, 0x24, 0xe1, 0x7a, 0x5e, 0x24, 0xc1, 0x52, 0x5e, 0x2c, 0xe1, 0x52, 0x5e, 0x2c, 0xe1, 0x56, 0x5e, 0x2c, 0xe1, 0x72, 0x5e, 0x2c, 0xe1, 0x7a, 0x5e, 0x2c  ]
+      arch: "CS_ARCH_HPPA"
+      options: [ CS_OPT_DETAIL, CS_MODE_LITTLE_ENDIAN, CS_MODE_HPPA_11 ]
+      address: 0x1000
+    expected:
+      insns:
+        -
+          asm_text: "cldwx,3 r1(sr1,rp),r3"
+          mnemonic: "cldwx,3"
+          op_str: "r1(sr1,rp),r3"
+          details:
+            groups: [ assist ]
+        -
+          asm_text: "cldwx,3,s r1(sr1,rp),r3"
+          mnemonic: "cldwx,3,s"
+          op_str: "r1(sr1,rp),r3"
+          details:
+            groups: [ assist ]
+        -
+          asm_text: "cldwx,3,m r1(sr1,rp),r3"
+          mnemonic: "cldwx,3,m"
+          op_str: "r1(sr1,rp),r3"
+          details:
+            groups: [ assist ]
+        -
+          asm_text: "cldwx,3,sm r1(sr1,rp),r3"
+          mnemonic: "cldwx,3,sm"
+          op_str: "r1(sr1,rp),r3"
+          details:
+            groups: [ assist ]
+        -
+          asm_text: "cldwx,3,sm,sl r1(sr1,rp),r3"
+          mnemonic: "cldwx,3,sm,sl"
+          op_str: "r1(sr1,rp),r3"
+          details:
+            groups: [ assist ]
+        -
+          asm_text: "clddx,3 r1(sr1,rp),r3"
+          mnemonic: "clddx,3"
+          op_str: "r1(sr1,rp),r3"
+          details:
+            groups: [ assist ]
+        -
+          asm_text: "clddx,3,s r1(sr1,rp),r3"
+          mnemonic: "clddx,3,s"
+          op_str: "r1(sr1,rp),r3"
+          details:
+            groups: [ assist ]
+        -
+          asm_text: "clddx,3,m r1(sr1,rp),r3"
+          mnemonic: "clddx,3,m"
+          op_str: "r1(sr1,rp),r3"
+          details:
+            groups: [ assist ]
+        -
+          asm_text: "clddx,3,sm r1(sr1,rp),r3"
+          mnemonic: "clddx,3,sm"
+          op_str: "r1(sr1,rp),r3"
+          details:
+            groups: [ assist ]
+        -
+          asm_text: "clddx,3,sm,sl r1(sr1,rp),r3"
+          mnemonic: "clddx,3,sm,sl"
+          op_str: "r1(sr1,rp),r3"
+          details:
+            groups: [ assist ]
+        -
+          asm_text: "cstwx,3 r1,rp(sr1,r3)"
+          mnemonic: "cstwx,3"
+          op_str: "r1,rp(sr1,r3)"
+          details:
+            groups: [ assist ]
+        -
+          asm_text: "cstwx,3,s r1,rp(sr1,r3)"
+          mnemonic: "cstwx,3,s"
+          op_str: "r1,rp(sr1,r3)"
+          details:
+            groups: [ assist ]
+        -
+          asm_text: "cstwx,3,m r1,rp(sr1,r3)"
+          mnemonic: "cstwx,3,m"
+          op_str: "r1,rp(sr1,r3)"
+          details:
+            groups: [ assist ]
+        -
+          asm_text: "cstwx,3,m,bc r1,rp(sr1,r3)"
+          mnemonic: "cstwx,3,m,bc"
+          op_str: "r1,rp(sr1,r3)"
+          details:
+            groups: [ assist ]
+        -
+          asm_text: "cstwx,3,sm r1,rp(sr1,r3)"
+          mnemonic: "cstwx,3,sm"
+          op_str: "r1,rp(sr1,r3)"
+          details:
+            groups: [ assist ]
+        -
+          asm_text: "cstwx,3,sm,sl r1,rp(sr1,r3)"
+          mnemonic: "cstwx,3,sm,sl"
+          op_str: "r1,rp(sr1,r3)"
+          details:
+            groups: [ assist ]
+        -
+          asm_text: "cstdx,3 r1,rp(sr1,r3)"
+          mnemonic: "cstdx,3"
+          op_str: "r1,rp(sr1,r3)"
+          details:
+            groups: [ assist ]
+        -
+          asm_text: "cstdx,3,s r1,rp(sr1,r3)"
+          mnemonic: "cstdx,3,s"
+          op_str: "r1,rp(sr1,r3)"
+          details:
+            groups: [ assist ]
+        -
+          asm_text: "cstdx,3,m r1,rp(sr1,r3)"
+          mnemonic: "cstdx,3,m"
+          op_str: "r1,rp(sr1,r3)"
+          details:
+            groups: [ assist ]
+        -
+          asm_text: "cstdx,3,m,bc r1,rp(sr1,r3)"
+          mnemonic: "cstdx,3,m,bc"
+          op_str: "r1,rp(sr1,r3)"
+          details:
+            groups: [ assist ]
+        -
+          asm_text: "cstdx,3,sm r1,rp(sr1,r3)"
+          mnemonic: "cstdx,3,sm"
+          op_str: "r1,rp(sr1,r3)"
+          details:
+            groups: [ assist ]
+        -
+          asm_text: "cstdx,3,sm,sl r1,rp(sr1,r3)"
+          mnemonic: "cstdx,3,sm,sl"
+          op_str: "r1,rp(sr1,r3)"
+          details:
+            groups: [ assist ]
+        -
+          asm_text: "cldws,3 0xf(sr1,r1),rp"
+          mnemonic: "cldws,3"
+          op_str: "0xf(sr1,r1),rp"
+          details:
+            groups: [ assist ]
+        -
+          asm_text: "cldws,3,ma 0xf(sr1,r1),rp"
+          mnemonic: "cldws,3,ma"
+          op_str: "0xf(sr1,r1),rp"
+          details:
+            groups: [ assist ]
+        -
+          asm_text: "cldws,3,mb 0xf(sr1,r1),rp"
+          mnemonic: "cldws,3,mb"
+          op_str: "0xf(sr1,r1),rp"
+          details:
+            groups: [ assist ]
+        -
+          asm_text: "cldws,3,mb,sl 0xf(sr1,r1),rp"
+          mnemonic: "cldws,3,mb,sl"
+          op_str: "0xf(sr1,r1),rp"
+          details:
+            groups: [ assist ]
+        -
+          asm_text: "cldds,3 0xf(sr1,r1),rp"
+          mnemonic: "cldds,3"
+          op_str: "0xf(sr1,r1),rp"
+          details:
+            groups: [ assist ]
+        -
+          asm_text: "cldds,3,ma 0xf(sr1,r1),rp"
+          mnemonic: "cldds,3,ma"
+          op_str: "0xf(sr1,r1),rp"
+          details:
+            groups: [ assist ]
+        -
+          asm_text: "cldds,3,mb 0xf(sr1,r1),rp"
+          mnemonic: "cldds,3,mb"
+          op_str: "0xf(sr1,r1),rp"
+          details:
+            groups: [ assist ]
+        -
+          asm_text: "cldds,3,mb,sl 0xf(sr1,r1),rp"
+          mnemonic: "cldds,3,mb,sl"
+          op_str: "0xf(sr1,r1),rp"
+          details:
+            groups: [ assist ]
+        -
+          asm_text: "cstws,3 r1,0xf(sr1,rp)"
+          mnemonic: "cstws,3"
+          op_str: "r1,0xf(sr1,rp)"
+          details:
+            groups: [ assist ]
+        -
+          asm_text: "cstws,3,ma r1,0xf(sr1,rp)"
+          mnemonic: "cstws,3,ma"
+          op_str: "r1,0xf(sr1,rp)"
+          details:
+            groups: [ assist ]
+        -
+          asm_text: "cstws,3,ma,bc r1,0xf(sr1,rp)"
+          mnemonic: "cstws,3,ma,bc"
+          op_str: "r1,0xf(sr1,rp)"
+          details:
+            groups: [ assist ]
+        -
+          asm_text: "cstws,3,mb r1,0xf(sr1,rp)"
+          mnemonic: "cstws,3,mb"
+          op_str: "r1,0xf(sr1,rp)"
+          details:
+            groups: [ assist ]
+        -
+          asm_text: "cstws,3,mb,sl r1,0xf(sr1,rp)"
+          mnemonic: "cstws,3,mb,sl"
+          op_str: "r1,0xf(sr1,rp)"
+          details:
+            groups: [ assist ]
+        -
+          asm_text: "cstds,3 r1,0xf(sr1,rp)"
+          mnemonic: "cstds,3"
+          op_str: "r1,0xf(sr1,rp)"
+          details:
+            groups: [ assist ]
+        -
+          asm_text: "cstds,3,ma r1,0xf(sr1,rp)"
+          mnemonic: "cstds,3,ma"
+          op_str: "r1,0xf(sr1,rp)"
+          details:
+            groups: [ assist ]
+        -
+          asm_text: "cstds,3,ma,bc r1,0xf(sr1,rp)"
+          mnemonic: "cstds,3,ma,bc"
+          op_str: "r1,0xf(sr1,rp)"
+          details:
+            groups: [ assist ]
+        -
+          asm_text: "cstds,3,mb r1,0xf(sr1,rp)"
+          mnemonic: "cstds,3,mb"
+          op_str: "r1,0xf(sr1,rp)"
+          details:
+            groups: [ assist ]
+        -
+          asm_text: "cstds,3,mb,sl r1,0xf(sr1,rp)"
+          mnemonic: "cstds,3,mb,sl"
+          op_str: "r1,0xf(sr1,rp)"
+          details:
+            groups: [ assist ]
+
diff --git a/tests/details/evm.yaml b/tests/details/evm.yaml
new file mode 100644
index 000000000..6858de6d5
--- /dev/null
+++ b/tests/details/evm.yaml
@@ -0,0 +1,24 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x60, 0x61, 0x50 ]
+      arch: "evm"
+      options: [ CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "push1 61"
+        details:
+          evm:
+            push: 1
+            fee: 3
+          groups: [ EVM_GRP_STACK_WRITE ]
+      -
+        asm_text: "pop"
+        details:
+          evm:
+            pop: 1
+            fee: 2
+          groups: [ EVM_GRP_STACK_READ ]
+
diff --git a/tests/details/hppa.yaml b/tests/details/hppa.yaml
new file mode 100644
index 000000000..ecc7d8ad3
--- /dev/null
+++ b/tests/details/hppa.yaml
@@ -0,0 +1,2308 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x00, 0x20, 0x50, 0xa2, 0x00, 0x01, 0x58, 0x20, 0x00, 0x00, 0x44, 0xa1, 0x00, 0x41, 0x18, 0x40, 0x00, 0x20, 0x08, 0xa2, 0x01, 0x60, 0x48, 0xa1, 0x01, 0x61, 0x18, 0xc0, 0x00, 0x00, 0x14, 0xa1, 0x00, 0x0f, 0x0d, 0x61, 0x00, 0x0f, 0x0e, 0x61, 0x00, 0x01, 0x18, 0x60, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x0c, 0xa0, 0x03, 0xff, 0xc0, 0x1f, 0x00, 0x00, 0x04, 0x00, 0x00, 0x10, 0x04, 0x00, 0x04, 0x22, 0x51, 0x83, 0x04, 0x22, 0x51, 0xc3, 0x04, 0x22, 0x51, 0x83, 0x04, 0x2f, 0x71, 0x83, 0x04, 0x2f, 0x71, 0xc3, 0x04, 0x2f, 0x71, 0x83, 0x04, 0x41, 0x53, 0x43, 0x04, 0x41, 0x53, 0x63, 0x04, 0x41, 0x53, 0x03, 0x04, 0x41, 0x12, 0x00, 0x04, 0x41, 0x16, 0x00, 0x04, 0x41, 0x16, 0x20, 0x04, 0x41, 0x42, 0x00, 0x04, 0x41, 0x46, 0x00, 0x04, 0x41, 0x46, 0x20, 0x04, 0x41, 0x12, 0x40, 0x04, 0x41, 0x12, 0x60, 0x04, 0x41, 0x42, 0x40, 0x04, 0x41, 0x42, 0x60, 0x04, 0x41, 0x18, 0x00, 0x04, 0x41, 0x08, 0x00, 0x04, 0x41, 0x13, 0x80, 0x04, 0x41, 0x13, 0xa0, 0x04, 0x41, 0x52, 0x80, 0x04, 0x41, 0x52, 0xa0, 0x04, 0x5e, 0x72, 0x80, 0x04, 0x41, 0x42, 0x80, 0x04, 0x41, 0x52, 0xc0, 0x04, 0x41, 0x52, 0xe0, 0x04, 0x41, 0x42, 0xc0, 0x04, 0x41, 0x42, 0xe0, 0x14, 0x00, 0xde, 0xad  ]
+      arch: "hppa"
+      options: [ CS_MODE_BIG_ENDIAN, CS_MODE_HPPA_20, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "ldsid (sr1,r1),rp"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: r1
+              -
+                type: HPPA_OP_REG
+                reg: rp
+      -
+        asm_text: "mtsp r1,sr1"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_REG
+                reg: r1
+              -
+                type: HPPA_OP_REG
+                reg: sr1
+      -
+        asm_text: "mfsp sr1,r1"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_REG
+                reg: sr1
+              -
+                type: HPPA_OP_REG
+                reg: r1
+      -
+        asm_text: "mtctl r1,cr2"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_REG
+                reg: r1
+              -
+                type: HPPA_OP_REG
+                reg: cr2
+      -
+        asm_text: "mfctl cr1,rp"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_REG
+                reg: cr1
+              -
+                type: HPPA_OP_REG
+                reg: rp
+      -
+        asm_text: "mfctl,w sar,r1"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_REG
+                reg: sar
+              -
+                type: HPPA_OP_REG
+                reg: r1
+      -
+        asm_text: "mtsarcm r1"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_REG
+                reg: r1
+      -
+        asm_text: "mfia r1"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_REG
+                reg: r1
+      -
+        asm_text: "ssm 0xf,r1"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_IMM
+                imm: 0xf
+              -
+                type: HPPA_OP_REG
+                reg: r1
+      -
+        asm_text: "rsm 0xf,r1"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_IMM
+                imm: 0xf
+              -
+                type: HPPA_OP_REG
+                reg: r1
+      -
+        asm_text: "mtsm r1"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_REG
+                reg: r1
+      -
+        asm_text: "rfi"
+      -
+        asm_text: "rfi,r"
+      -
+        asm_text: "break 0x1f,0x1ffe"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_IMM
+                imm: 0x1f
+              -
+                type: HPPA_OP_IMM
+                imm: 0x1ffe
+      -
+        asm_text: "sync"
+      -
+        asm_text: "syncdma"
+      -
+        asm_text: "probe,r (sr1,r1),rp,r3"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: r1
+              -
+                type: HPPA_OP_REG
+                reg: rp
+              -
+                type: HPPA_OP_REG
+                reg: r3
+      -
+        asm_text: "probe,w (sr1,r1),rp,r3"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: r1
+              -
+                type: HPPA_OP_REG
+                reg: rp
+              -
+                type: HPPA_OP_REG
+                reg: r3
+      -
+        asm_text: "probe,r (sr1,r1),rp,r3"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: r1
+              -
+                type: HPPA_OP_REG
+                reg: rp
+              -
+                type: HPPA_OP_REG
+                reg: r3
+      -
+        asm_text: "probei,r (sr1,r1),0xf,r3"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: r1
+              -
+                type: HPPA_OP_IMM
+                imm: 0xf
+              -
+                type: HPPA_OP_REG
+                reg: r3
+      -
+        asm_text: "probei,w (sr1,r1),0xf,r3"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: r1
+              -
+                type: HPPA_OP_IMM
+                imm: 0xf
+              -
+                type: HPPA_OP_REG
+                reg: r3
+      -
+        asm_text: "probei,r (sr1,r1),0xf,r3"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: r1
+              -
+                type: HPPA_OP_IMM
+                imm: 0xf
+              -
+                type: HPPA_OP_REG
+                reg: r3
+      -
+        asm_text: "lpa r1(sr1,rp),r3"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_IDX_REG
+                reg: r1
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: rp
+              -
+                type: HPPA_OP_REG
+                reg: r3
+      -
+        asm_text: "lpa,m r1(sr1,rp),r3"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_IDX_REG
+                reg: r1
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: rp
+              -
+                type: HPPA_OP_REG
+                reg: r3
+      -
+        asm_text: "lci r1(sr1,rp),r3"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_IDX_REG
+                reg: r1
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: rp
+              -
+                type: HPPA_OP_REG
+                reg: r3
+      -
+        asm_text: "pdtlb r1(rp)"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_IDX_REG
+                reg: r1
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr0
+                mem_base: rp
+      -
+        asm_text: "pdtlb,l r1(rp)"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_IDX_REG
+                reg: r1
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr0
+                mem_base: rp
+      -
+        asm_text: "pdtlb,l,m r1(rp)"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_IDX_REG
+                reg: r1
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr0
+                mem_base: rp
+      -
+        asm_text: "pitlb r1(sr1,rp)"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_IDX_REG
+                reg: r1
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: rp
+      -
+        asm_text: "pitlb,l r1(sr1,rp)"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_IDX_REG
+                reg: r1
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: rp
+      -
+        asm_text: "pitlb,l,m r1(sr1,rp)"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_IDX_REG
+                reg: r1
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: rp
+      -
+        asm_text: "pdtlbe r1(rp)"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_IDX_REG
+                reg: r1
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr0
+                mem_base: rp
+      -
+        asm_text: "pdtlbe,m r1(rp)"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_IDX_REG
+                reg: r1
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr0
+                mem_base: rp
+      -
+        asm_text: "pitlbe r1(sr1,rp)"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_IDX_REG
+                reg: r1
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: rp
+      -
+        asm_text: "pitlbe,m r1(sr1,rp)"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_IDX_REG
+                reg: r1
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: rp
+      -
+        asm_text: "idtlbt r1,rp"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_REG
+                reg: r1
+              -
+                type: HPPA_OP_REG
+                reg: rp
+      -
+        asm_text: "iitlbt r1,rp"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_REG
+                reg: r1
+              -
+                type: HPPA_OP_REG
+                reg: rp
+      -
+        asm_text: "pdc r1(rp)"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_IDX_REG
+                reg: r1
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr0
+                mem_base: rp
+      -
+        asm_text: "pdc,m r1(rp)"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_IDX_REG
+                reg: r1
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr0
+                mem_base: rp
+      -
+        asm_text: "fdc r1(sr1,rp)"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_IDX_REG
+                reg: r1
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: rp
+      -
+        asm_text: "fdc,m r1(sr1,rp)"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_IDX_REG
+                reg: r1
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: rp
+      -
+        asm_text: "fdc 0xf(sr1,rp)"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_DISP
+                imm: 0xf
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: rp
+      -
+        asm_text: "fic r1(sr1,rp)"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_IDX_REG
+                reg: r1
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: rp
+      -
+        asm_text: "fdce r1(sr1,rp)"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_IDX_REG
+                reg: r1
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: rp
+      -
+        asm_text: "fdce,m r1(sr1,rp)"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_IDX_REG
+                reg: r1
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: rp
+      -
+        asm_text: "fice r1(sr1,rp)"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_IDX_REG
+                reg: r1
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: rp
+      -
+        asm_text: "fice,m r1(sr1,rp)"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_IDX_REG
+                reg: r1
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: rp
+      -
+        asm_text: "diag 0xdead"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_IMM
+                imm: 0xdead
+  -
+    input:
+      bytes: [ 0xa2, 0x50, 0x20, 0x00, 0x20, 0x58, 0x01, 0x00, 0xa1, 0x44, 0x00, 0x00, 0x40, 0x18, 0x41, 0x00, 0xa2, 0x08, 0x20, 0x00, 0xa1, 0x48, 0x60, 0x01, 0xc0, 0x18, 0x61, 0x01, 0xa1, 0x14, 0x00, 0x00, 0x61, 0x0d, 0x0f, 0x00, 0x61, 0x0e, 0x0f, 0x00, 0x60, 0x18, 0x01, 0x00, 0x00, 0x0c, 0x00, 0x00, 0xa0, 0x0c, 0x00, 0x00, 0x1f, 0xc0, 0xff, 0x03, 0x00, 0x04, 0x00, 0x00, 0x00, 0x04, 0x10, 0x00, 0x83, 0x51, 0x22, 0x04, 0xc3, 0x51, 0x22, 0x04, 0x83, 0x51, 0x22, 0x04, 0x83, 0x71, 0x2f, 0x04, 0xc3, 0x71, 0x2f, 0x04, 0x83, 0x71, 0x2f, 0x04, 0x43, 0x53, 0x41, 0x04, 0x63, 0x53, 0x41, 0x04, 0x03, 0x53, 0x41, 0x04, 0x00, 0x12, 0x41, 0x04, 0x00, 0x16, 0x41, 0x04, 0x20, 0x16, 0x41, 0x04, 0x00, 0x42, 0x41, 0x04, 0x00, 0x46, 0x41, 0x04, 0x20, 0x46, 0x41, 0x04, 0x40, 0x12, 0x41, 0x04, 0x60, 0x12, 0x41, 0x04, 0x40, 0x42, 0x41, 0x04, 0x60, 0x42, 0x41, 0x04, 0x00, 0x18, 0x41, 0x04, 0x00, 0x08, 0x41, 0x04, 0x80, 0x13, 0x41, 0x04, 0xa0, 0x13, 0x41, 0x04, 0x80, 0x52, 0x41, 0x04, 0xa0, 0x52, 0x41, 0x04, 0x80, 0x72, 0x5e, 0x04, 0x80, 0x42, 0x41, 0x04, 0xc0, 0x52, 0x41, 0x04, 0xe0, 0x52, 0x41, 0x04, 0xc0, 0x42, 0x41, 0x04, 0xe0, 0x42, 0x41, 0x04, 0xad, 0xde, 0x00, 0x14  ]
+      arch: "hppa"
+      options: [ CS_OPT_DETAIL, CS_MODE_HPPA_20 ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "ldsid (sr1,r1),rp"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: r1
+              -
+                type: HPPA_OP_REG
+                reg: rp
+      -
+        asm_text: "mtsp r1,sr1"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_REG
+                reg: r1
+              -
+                type: HPPA_OP_REG
+                reg: sr1
+      -
+        asm_text: "mfsp sr1,r1"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_REG
+                reg: sr1
+              -
+                type: HPPA_OP_REG
+                reg: r1
+      -
+        asm_text: "mtctl r1,cr2"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_REG
+                reg: r1
+              -
+                type: HPPA_OP_REG
+                reg: cr2
+      -
+        asm_text: "mfctl cr1,rp"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_REG
+                reg: cr1
+              -
+                type: HPPA_OP_REG
+                reg: rp
+      -
+        asm_text: "mfctl,w sar,r1"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_REG
+                reg: sar
+              -
+                type: HPPA_OP_REG
+                reg: r1
+      -
+        asm_text: "mtsarcm r1"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_REG
+                reg: r1
+      -
+        asm_text: "mfia r1"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_REG
+                reg: r1
+      -
+        asm_text: "ssm 0xf,r1"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_IMM
+                imm: 0xf
+              -
+                type: HPPA_OP_REG
+                reg: r1
+      -
+        asm_text: "rsm 0xf,r1"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_IMM
+                imm: 0xf
+              -
+                type: HPPA_OP_REG
+                reg: r1
+      -
+        asm_text: "mtsm r1"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_REG
+                reg: r1
+      -
+        asm_text: "rfi"
+      -
+        asm_text: "rfi,r"
+      -
+        asm_text: "break 0x1f,0x1ffe"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_IMM
+                imm: 0x1f
+              -
+                type: HPPA_OP_IMM
+                imm: 0x1ffe
+      -
+        asm_text: "sync"
+      -
+        asm_text: "syncdma"
+      -
+        asm_text: "probe,r (sr1,r1),rp,r3"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: r1
+              -
+                type: HPPA_OP_REG
+                reg: rp
+              -
+                type: HPPA_OP_REG
+                reg: r3
+      -
+        asm_text: "probe,w (sr1,r1),rp,r3"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: r1
+              -
+                type: HPPA_OP_REG
+                reg: rp
+              -
+                type: HPPA_OP_REG
+                reg: r3
+      -
+        asm_text: "probe,r (sr1,r1),rp,r3"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: r1
+              -
+                type: HPPA_OP_REG
+                reg: rp
+              -
+                type: HPPA_OP_REG
+                reg: r3
+      -
+        asm_text: "probei,r (sr1,r1),0xf,r3"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: r1
+              -
+                type: HPPA_OP_IMM
+                imm: 0xf
+              -
+                type: HPPA_OP_REG
+                reg: r3
+      -
+        asm_text: "probei,w (sr1,r1),0xf,r3"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: r1
+              -
+                type: HPPA_OP_IMM
+                imm: 0xf
+              -
+                type: HPPA_OP_REG
+                reg: r3
+      -
+        asm_text: "probei,r (sr1,r1),0xf,r3"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: r1
+              -
+                type: HPPA_OP_IMM
+                imm: 0xf
+              -
+                type: HPPA_OP_REG
+                reg: r3
+      -
+        asm_text: "lpa r1(sr1,rp),r3"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_IDX_REG
+                reg: r1
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: rp
+              -
+                type: HPPA_OP_REG
+                reg: r3
+      -
+        asm_text: "lpa,m r1(sr1,rp),r3"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_IDX_REG
+                reg: r1
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: rp
+              -
+                type: HPPA_OP_REG
+                reg: r3
+      -
+        asm_text: "lci r1(sr1,rp),r3"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_IDX_REG
+                reg: r1
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: rp
+              -
+                type: HPPA_OP_REG
+                reg: r3
+      -
+        asm_text: "pdtlb r1(rp)"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_IDX_REG
+                reg: r1
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr0
+                mem_base: rp
+      -
+        asm_text: "pdtlb,l r1(rp)"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_IDX_REG
+                reg: r1
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr0
+                mem_base: rp
+      -
+        asm_text: "pdtlb,l,m r1(rp)"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_IDX_REG
+                reg: r1
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr0
+                mem_base: rp
+      -
+        asm_text: "pitlb r1(sr1,rp)"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_IDX_REG
+                reg: r1
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: rp
+      -
+        asm_text: "pitlb,l r1(sr1,rp)"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_IDX_REG
+                reg: r1
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: rp
+      -
+        asm_text: "pitlb,l,m r1(sr1,rp)"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_IDX_REG
+                reg: r1
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: rp
+      -
+        asm_text: "pdtlbe r1(rp)"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_IDX_REG
+                reg: r1
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr0
+                mem_base: rp
+      -
+        asm_text: "pdtlbe,m r1(rp)"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_IDX_REG
+                reg: r1
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr0
+                mem_base: rp
+      -
+        asm_text: "pitlbe r1(sr1,rp)"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_IDX_REG
+                reg: r1
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: rp
+      -
+        asm_text: "pitlbe,m r1(sr1,rp)"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_IDX_REG
+                reg: r1
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: rp
+      -
+        asm_text: "idtlbt r1,rp"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_REG
+                reg: r1
+              -
+                type: HPPA_OP_REG
+                reg: rp
+      -
+        asm_text: "iitlbt r1,rp"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_REG
+                reg: r1
+              -
+                type: HPPA_OP_REG
+                reg: rp
+      -
+        asm_text: "pdc r1(rp)"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_IDX_REG
+                reg: r1
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr0
+                mem_base: rp
+      -
+        asm_text: "pdc,m r1(rp)"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_IDX_REG
+                reg: r1
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr0
+                mem_base: rp
+      -
+        asm_text: "fdc r1(sr1,rp)"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_IDX_REG
+                reg: r1
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: rp
+      -
+        asm_text: "fdc,m r1(sr1,rp)"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_IDX_REG
+                reg: r1
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: rp
+      -
+        asm_text: "fdc 0xf(sr1,rp)"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_DISP
+                imm: 0xf
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: rp
+      -
+        asm_text: "fic r1(sr1,rp)"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_IDX_REG
+                reg: r1
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: rp
+      -
+        asm_text: "fdce r1(sr1,rp)"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_IDX_REG
+                reg: r1
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: rp
+      -
+        asm_text: "fdce,m r1(sr1,rp)"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_IDX_REG
+                reg: r1
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: rp
+      -
+        asm_text: "fice r1(sr1,rp)"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_IDX_REG
+                reg: r1
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: rp
+      -
+        asm_text: "fice,m r1(sr1,rp)"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_IDX_REG
+                reg: r1
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: rp
+      -
+        asm_text: "diag 0xdead"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_IMM
+                imm: 0xdead
+  -
+    input:
+      bytes: [ 0x24, 0x41, 0x40, 0xc3, 0x24, 0x41, 0x60, 0xc3, 0x24, 0x41, 0x40, 0xe3, 0x24, 0x41, 0x60, 0xe3, 0x24, 0x41, 0x68, 0xe3, 0x2c, 0x41, 0x40, 0xc3, 0x2c, 0x41, 0x60, 0xc3, 0x2c, 0x41, 0x40, 0xe3, 0x2c, 0x41, 0x60, 0xe3, 0x2c, 0x41, 0x68, 0xe3, 0x24, 0x62, 0x42, 0xc1, 0x24, 0x62, 0x62, 0xc1, 0x24, 0x62, 0x42, 0xe1, 0x24, 0x62, 0x46, 0xe1, 0x24, 0x62, 0x62, 0xe1, 0x24, 0x62, 0x6a, 0xe1, 0x2c, 0x62, 0x42, 0xc1, 0x2c, 0x62, 0x62, 0xc1, 0x2c, 0x62, 0x42, 0xe1, 0x2c, 0x62, 0x46, 0xe1, 0x2c, 0x62, 0x62, 0xe1, 0x2c, 0x62, 0x6a, 0xe1, 0x24, 0x3e, 0x50, 0xc2, 0x24, 0x3e, 0x50, 0xe2, 0x24, 0x3e, 0x70, 0xe2, 0x24, 0x3e, 0x78, 0xe2, 0x2c, 0x3e, 0x50, 0xc2, 0x2c, 0x3e, 0x50, 0xe2, 0x2c, 0x3e, 0x70, 0xe2, 0x2c, 0x3e, 0x78, 0xe2, 0x24, 0x5e, 0x52, 0xc1, 0x24, 0x5e, 0x52, 0xe1, 0x24, 0x5e, 0x56, 0xe1, 0x24, 0x5e, 0x72, 0xe1, 0x24, 0x5e, 0x7a, 0xe1, 0x2c, 0x5e, 0x52, 0xc1, 0x2c, 0x5e, 0x52, 0xe1, 0x2c, 0x5e, 0x56, 0xe1, 0x2c, 0x5e, 0x72, 0xe1, 0x2c, 0x5e, 0x7a, 0xe1  ]
+      arch: "hppa"
+      options: [ CS_OPT_DETAIL, CS_MODE_HPPA_11, CS_MODE_BIG_ENDIAN ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "cldwx,3 r1(sr1,rp),r3"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_IDX_REG
+                reg: r1
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: rp
+              -
+                type: HPPA_OP_REG
+                reg: r3
+      -
+        asm_text: "cldwx,3,s r1(sr1,rp),r3"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_IDX_REG
+                reg: r1
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: rp
+              -
+                type: HPPA_OP_REG
+                reg: r3
+      -
+        asm_text: "cldwx,3,m r1(sr1,rp),r3"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_IDX_REG
+                reg: r1
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: rp
+              -
+                type: HPPA_OP_REG
+                reg: r3
+      -
+        asm_text: "cldwx,3,sm r1(sr1,rp),r3"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_IDX_REG
+                reg: r1
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: rp
+              -
+                type: HPPA_OP_REG
+                reg: r3
+      -
+        asm_text: "cldwx,3,sm,sl r1(sr1,rp),r3"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_IDX_REG
+                reg: r1
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: rp
+              -
+                type: HPPA_OP_REG
+                reg: r3
+      -
+        asm_text: "clddx,3 r1(sr1,rp),r3"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_IDX_REG
+                reg: r1
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: rp
+              -
+                type: HPPA_OP_REG
+                reg: r3
+      -
+        asm_text: "clddx,3,s r1(sr1,rp),r3"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_IDX_REG
+                reg: r1
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: rp
+              -
+                type: HPPA_OP_REG
+                reg: r3
+      -
+        asm_text: "clddx,3,m r1(sr1,rp),r3"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_IDX_REG
+                reg: r1
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: rp
+              -
+                type: HPPA_OP_REG
+                reg: r3
+      -
+        asm_text: "clddx,3,sm r1(sr1,rp),r3"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_IDX_REG
+                reg: r1
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: rp
+              -
+                type: HPPA_OP_REG
+                reg: r3
+      -
+        asm_text: "clddx,3,sm,sl r1(sr1,rp),r3"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_IDX_REG
+                reg: r1
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: rp
+              -
+                type: HPPA_OP_REG
+                reg: r3
+      -
+        asm_text: "cstwx,3 r1,rp(sr1,r3)"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_REG
+                reg: r1
+              -
+                type: HPPA_OP_IDX_REG
+                reg: rp
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: r3
+      -
+        asm_text: "cstwx,3,s r1,rp(sr1,r3)"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_REG
+                reg: r1
+              -
+                type: HPPA_OP_IDX_REG
+                reg: rp
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: r3
+      -
+        asm_text: "cstwx,3,m r1,rp(sr1,r3)"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_REG
+                reg: r1
+              -
+                type: HPPA_OP_IDX_REG
+                reg: rp
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: r3
+      -
+        asm_text: "cstwx,3,m,bc r1,rp(sr1,r3)"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_REG
+                reg: r1
+              -
+                type: HPPA_OP_IDX_REG
+                reg: rp
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: r3
+      -
+        asm_text: "cstwx,3,sm r1,rp(sr1,r3)"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_REG
+                reg: r1
+              -
+                type: HPPA_OP_IDX_REG
+                reg: rp
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: r3
+      -
+        asm_text: "cstwx,3,sm,sl r1,rp(sr1,r3)"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_REG
+                reg: r1
+              -
+                type: HPPA_OP_IDX_REG
+                reg: rp
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: r3
+      -
+        asm_text: "cstdx,3 r1,rp(sr1,r3)"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_REG
+                reg: r1
+              -
+                type: HPPA_OP_IDX_REG
+                reg: rp
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: r3
+      -
+        asm_text: "cstdx,3,s r1,rp(sr1,r3)"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_REG
+                reg: r1
+              -
+                type: HPPA_OP_IDX_REG
+                reg: rp
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: r3
+      -
+        asm_text: "cstdx,3,m r1,rp(sr1,r3)"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_REG
+                reg: r1
+              -
+                type: HPPA_OP_IDX_REG
+                reg: rp
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: r3
+      -
+        asm_text: "cstdx,3,m,bc r1,rp(sr1,r3)"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_REG
+                reg: r1
+              -
+                type: HPPA_OP_IDX_REG
+                reg: rp
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: r3
+      -
+        asm_text: "cstdx,3,sm r1,rp(sr1,r3)"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_REG
+                reg: r1
+              -
+                type: HPPA_OP_IDX_REG
+                reg: rp
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: r3
+      -
+        asm_text: "cstdx,3,sm,sl r1,rp(sr1,r3)"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_REG
+                reg: r1
+              -
+                type: HPPA_OP_IDX_REG
+                reg: rp
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: r3
+      -
+        asm_text: "cldws,3 0xf(sr1,r1),rp"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_DISP
+                imm: 0xf
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: r1
+              -
+                type: HPPA_OP_REG
+                reg: rp
+      -
+        asm_text: "cldws,3,ma 0xf(sr1,r1),rp"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_DISP
+                imm: 0xf
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: r1
+              -
+                type: HPPA_OP_REG
+                reg: rp
+      -
+        asm_text: "cldws,3,mb 0xf(sr1,r1),rp"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_DISP
+                imm: 0xf
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: r1
+              -
+                type: HPPA_OP_REG
+                reg: rp
+      -
+        asm_text: "cldws,3,mb,sl 0xf(sr1,r1),rp"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_DISP
+                imm: 0xf
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: r1
+              -
+                type: HPPA_OP_REG
+                reg: rp
+      -
+        asm_text: "cldds,3 0xf(sr1,r1),rp"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_DISP
+                imm: 0xf
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: r1
+              -
+                type: HPPA_OP_REG
+                reg: rp
+      -
+        asm_text: "cldds,3,ma 0xf(sr1,r1),rp"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_DISP
+                imm: 0xf
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: r1
+              -
+                type: HPPA_OP_REG
+                reg: rp
+      -
+        asm_text: "cldds,3,mb 0xf(sr1,r1),rp"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_DISP
+                imm: 0xf
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: r1
+              -
+                type: HPPA_OP_REG
+                reg: rp
+      -
+        asm_text: "cldds,3,mb,sl 0xf(sr1,r1),rp"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_DISP
+                imm: 0xf
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: r1
+              -
+                type: HPPA_OP_REG
+                reg: rp
+      -
+        asm_text: "cstws,3 r1,0xf(sr1,rp)"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_REG
+                reg: r1
+              -
+                type: HPPA_OP_DISP
+                imm: 0xf
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: rp
+      -
+        asm_text: "cstws,3,ma r1,0xf(sr1,rp)"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_REG
+                reg: r1
+              -
+                type: HPPA_OP_DISP
+                imm: 0xf
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: rp
+      -
+        asm_text: "cstws,3,ma,bc r1,0xf(sr1,rp)"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_REG
+                reg: r1
+              -
+                type: HPPA_OP_DISP
+                imm: 0xf
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: rp
+      -
+        asm_text: "cstws,3,mb r1,0xf(sr1,rp)"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_REG
+                reg: r1
+              -
+                type: HPPA_OP_DISP
+                imm: 0xf
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: rp
+      -
+        asm_text: "cstws,3,mb,sl r1,0xf(sr1,rp)"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_REG
+                reg: r1
+              -
+                type: HPPA_OP_DISP
+                imm: 0xf
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: rp
+      -
+        asm_text: "cstds,3 r1,0xf(sr1,rp)"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_REG
+                reg: r1
+              -
+                type: HPPA_OP_DISP
+                imm: 0xf
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: rp
+      -
+        asm_text: "cstds,3,ma r1,0xf(sr1,rp)"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_REG
+                reg: r1
+              -
+                type: HPPA_OP_DISP
+                imm: 0xf
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: rp
+      -
+        asm_text: "cstds,3,ma,bc r1,0xf(sr1,rp)"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_REG
+                reg: r1
+              -
+                type: HPPA_OP_DISP
+                imm: 0xf
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: rp
+      -
+        asm_text: "cstds,3,mb r1,0xf(sr1,rp)"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_REG
+                reg: r1
+              -
+                type: HPPA_OP_DISP
+                imm: 0xf
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: rp
+      -
+        asm_text: "cstds,3,mb,sl r1,0xf(sr1,rp)"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_REG
+                reg: r1
+              -
+                type: HPPA_OP_DISP
+                imm: 0xf
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: rp
+  -
+    input:
+      bytes: [ 0xc3, 0x40, 0x41, 0x24, 0xc3, 0x60, 0x41, 0x24, 0xe3, 0x40, 0x41, 0x24, 0xe3, 0x60, 0x41, 0x24, 0xe3, 0x68, 0x41, 0x24, 0xc3, 0x40, 0x41, 0x2c, 0xc3, 0x60, 0x41, 0x2c, 0xe3, 0x40, 0x41, 0x2c, 0xe3, 0x60, 0x41, 0x2c, 0xe3, 0x68, 0x41, 0x2c, 0xc1, 0x42, 0x62, 0x24, 0xc1, 0x62, 0x62, 0x24, 0xe1, 0x42, 0x62, 0x24, 0xe1, 0x46, 0x62, 0x24, 0xe1, 0x62, 0x62, 0x24, 0xe1, 0x6a, 0x62, 0x24, 0xc1, 0x42, 0x62, 0x2c, 0xc1, 0x62, 0x62, 0x2c, 0xe1, 0x42, 0x62, 0x2c, 0xe1, 0x46, 0x62, 0x2c, 0xe1, 0x62, 0x62, 0x2c, 0xe1, 0x6a, 0x62, 0x2c, 0xc2, 0x50, 0x3e, 0x24, 0xe2, 0x50, 0x3e, 0x24, 0xe2, 0x70, 0x3e, 0x24, 0xe2, 0x78, 0x3e, 0x24, 0xc2, 0x50, 0x3e, 0x2c, 0xe2, 0x50, 0x3e, 0x2c, 0xe2, 0x70, 0x3e, 0x2c, 0xe2, 0x78, 0x3e, 0x2c, 0xc1, 0x52, 0x5e, 0x24, 0xe1, 0x52, 0x5e, 0x24, 0xe1, 0x56, 0x5e, 0x24, 0xe1, 0x72, 0x5e, 0x24, 0xe1, 0x7a, 0x5e, 0x24, 0xc1, 0x52, 0x5e, 0x2c, 0xe1, 0x52, 0x5e, 0x2c, 0xe1, 0x56, 0x5e, 0x2c, 0xe1, 0x72, 0x5e, 0x2c, 0xe1, 0x7a, 0x5e, 0x2c  ]
+      arch: "hppa"
+      options: [ CS_OPT_DETAIL, CS_MODE_HPPA_11 ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "cldwx,3 r1(sr1,rp),r3"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_IDX_REG
+                reg: r1
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: rp
+              -
+                type: HPPA_OP_REG
+                reg: r3
+      -
+        asm_text: "cldwx,3,s r1(sr1,rp),r3"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_IDX_REG
+                reg: r1
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: rp
+              -
+                type: HPPA_OP_REG
+                reg: r3
+      -
+        asm_text: "cldwx,3,m r1(sr1,rp),r3"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_IDX_REG
+                reg: r1
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: rp
+              -
+                type: HPPA_OP_REG
+                reg: r3
+      -
+        asm_text: "cldwx,3,sm r1(sr1,rp),r3"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_IDX_REG
+                reg: r1
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: rp
+              -
+                type: HPPA_OP_REG
+                reg: r3
+      -
+        asm_text: "cldwx,3,sm,sl r1(sr1,rp),r3"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_IDX_REG
+                reg: r1
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: rp
+              -
+                type: HPPA_OP_REG
+                reg: r3
+      -
+        asm_text: "clddx,3 r1(sr1,rp),r3"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_IDX_REG
+                reg: r1
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: rp
+              -
+                type: HPPA_OP_REG
+                reg: r3
+      -
+        asm_text: "clddx,3,s r1(sr1,rp),r3"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_IDX_REG
+                reg: r1
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: rp
+              -
+                type: HPPA_OP_REG
+                reg: r3
+      -
+        asm_text: "clddx,3,m r1(sr1,rp),r3"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_IDX_REG
+                reg: r1
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: rp
+              -
+                type: HPPA_OP_REG
+                reg: r3
+      -
+        asm_text: "clddx,3,sm r1(sr1,rp),r3"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_IDX_REG
+                reg: r1
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: rp
+              -
+                type: HPPA_OP_REG
+                reg: r3
+      -
+        asm_text: "clddx,3,sm,sl r1(sr1,rp),r3"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_IDX_REG
+                reg: r1
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: rp
+              -
+                type: HPPA_OP_REG
+                reg: r3
+      -
+        asm_text: "cstwx,3 r1,rp(sr1,r3)"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_REG
+                reg: r1
+              -
+                type: HPPA_OP_IDX_REG
+                reg: rp
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: r3
+      -
+        asm_text: "cstwx,3,s r1,rp(sr1,r3)"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_REG
+                reg: r1
+              -
+                type: HPPA_OP_IDX_REG
+                reg: rp
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: r3
+      -
+        asm_text: "cstwx,3,m r1,rp(sr1,r3)"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_REG
+                reg: r1
+              -
+                type: HPPA_OP_IDX_REG
+                reg: rp
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: r3
+      -
+        asm_text: "cstwx,3,m,bc r1,rp(sr1,r3)"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_REG
+                reg: r1
+              -
+                type: HPPA_OP_IDX_REG
+                reg: rp
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: r3
+      -
+        asm_text: "cstwx,3,sm r1,rp(sr1,r3)"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_REG
+                reg: r1
+              -
+                type: HPPA_OP_IDX_REG
+                reg: rp
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: r3
+      -
+        asm_text: "cstwx,3,sm,sl r1,rp(sr1,r3)"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_REG
+                reg: r1
+              -
+                type: HPPA_OP_IDX_REG
+                reg: rp
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: r3
+      -
+        asm_text: "cstdx,3 r1,rp(sr1,r3)"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_REG
+                reg: r1
+              -
+                type: HPPA_OP_IDX_REG
+                reg: rp
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: r3
+      -
+        asm_text: "cstdx,3,s r1,rp(sr1,r3)"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_REG
+                reg: r1
+              -
+                type: HPPA_OP_IDX_REG
+                reg: rp
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: r3
+      -
+        asm_text: "cstdx,3,m r1,rp(sr1,r3)"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_REG
+                reg: r1
+              -
+                type: HPPA_OP_IDX_REG
+                reg: rp
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: r3
+      -
+        asm_text: "cstdx,3,m,bc r1,rp(sr1,r3)"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_REG
+                reg: r1
+              -
+                type: HPPA_OP_IDX_REG
+                reg: rp
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: r3
+      -
+        asm_text: "cstdx,3,sm r1,rp(sr1,r3)"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_REG
+                reg: r1
+              -
+                type: HPPA_OP_IDX_REG
+                reg: rp
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: r3
+      -
+        asm_text: "cstdx,3,sm,sl r1,rp(sr1,r3)"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_REG
+                reg: r1
+              -
+                type: HPPA_OP_IDX_REG
+                reg: rp
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: r3
+      -
+        asm_text: "cldws,3 0xf(sr1,r1),rp"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_DISP
+                imm: 0xf
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: r1
+              -
+                type: HPPA_OP_REG
+                reg: rp
+      -
+        asm_text: "cldws,3,ma 0xf(sr1,r1),rp"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_DISP
+                imm: 0xf
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: r1
+              -
+                type: HPPA_OP_REG
+                reg: rp
+      -
+        asm_text: "cldws,3,mb 0xf(sr1,r1),rp"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_DISP
+                imm: 0xf
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: r1
+              -
+                type: HPPA_OP_REG
+                reg: rp
+      -
+        asm_text: "cldws,3,mb,sl 0xf(sr1,r1),rp"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_DISP
+                imm: 0xf
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: r1
+              -
+                type: HPPA_OP_REG
+                reg: rp
+      -
+        asm_text: "cldds,3 0xf(sr1,r1),rp"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_DISP
+                imm: 0xf
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: r1
+              -
+                type: HPPA_OP_REG
+                reg: rp
+      -
+        asm_text: "cldds,3,ma 0xf(sr1,r1),rp"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_DISP
+                imm: 0xf
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: r1
+              -
+                type: HPPA_OP_REG
+                reg: rp
+      -
+        asm_text: "cldds,3,mb 0xf(sr1,r1),rp"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_DISP
+                imm: 0xf
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: r1
+              -
+                type: HPPA_OP_REG
+                reg: rp
+      -
+        asm_text: "cldds,3,mb,sl 0xf(sr1,r1),rp"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_DISP
+                imm: 0xf
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: r1
+              -
+                type: HPPA_OP_REG
+                reg: rp
+      -
+        asm_text: "cstws,3 r1,0xf(sr1,rp)"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_REG
+                reg: r1
+              -
+                type: HPPA_OP_DISP
+                imm: 0xf
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: rp
+      -
+        asm_text: "cstws,3,ma r1,0xf(sr1,rp)"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_REG
+                reg: r1
+              -
+                type: HPPA_OP_DISP
+                imm: 0xf
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: rp
+      -
+        asm_text: "cstws,3,ma,bc r1,0xf(sr1,rp)"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_REG
+                reg: r1
+              -
+                type: HPPA_OP_DISP
+                imm: 0xf
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: rp
+      -
+        asm_text: "cstws,3,mb r1,0xf(sr1,rp)"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_REG
+                reg: r1
+              -
+                type: HPPA_OP_DISP
+                imm: 0xf
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: rp
+      -
+        asm_text: "cstws,3,mb,sl r1,0xf(sr1,rp)"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_REG
+                reg: r1
+              -
+                type: HPPA_OP_DISP
+                imm: 0xf
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: rp
+      -
+        asm_text: "cstds,3 r1,0xf(sr1,rp)"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_REG
+                reg: r1
+              -
+                type: HPPA_OP_DISP
+                imm: 0xf
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: rp
+      -
+        asm_text: "cstds,3,ma r1,0xf(sr1,rp)"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_REG
+                reg: r1
+              -
+                type: HPPA_OP_DISP
+                imm: 0xf
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: rp
+      -
+        asm_text: "cstds,3,ma,bc r1,0xf(sr1,rp)"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_REG
+                reg: r1
+              -
+                type: HPPA_OP_DISP
+                imm: 0xf
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: rp
+      -
+        asm_text: "cstds,3,mb r1,0xf(sr1,rp)"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_REG
+                reg: r1
+              -
+                type: HPPA_OP_DISP
+                imm: 0xf
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: rp
+      -
+        asm_text: "cstds,3,mb,sl r1,0xf(sr1,rp)"
+        details:
+          hppa:
+            operands:
+              -
+                type: HPPA_OP_REG
+                reg: r1
+              -
+                type: HPPA_OP_DISP
+                imm: 0xf
+              -
+                type: HPPA_OP_MEM
+                mem_space: sr1
+                mem_base: rp
+
diff --git a/tests/details/loongarch.yaml b/tests/details/loongarch.yaml
new file mode 100644
index 000000000..0fd5a79e2
--- /dev/null
+++ b/tests/details/loongarch.yaml
@@ -0,0 +1,107 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x0c, 0x00, 0x08, 0x14, 0x8c, 0xfd, 0xbf, 0x02  ]
+      arch: "loongarch"
+      options: [ CS_OPT_DETAIL, CS_MODE_LOONGARCH32 ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "lu12i.w $t0, 0x4000"
+        details:
+          loongarch:
+            operands:
+              -
+                type: LOONGARCH_OP_REG
+                reg: t0
+              -
+                type: LOONGARCH_OP_IMM
+                imm: 0x4000
+      -
+        asm_text: "addi.w $t0, $t0, -1"
+        details:
+          loongarch:
+            operands:
+              -
+                type: LOONGARCH_OP_REG
+                reg: t0
+              -
+                type: LOONGARCH_OP_REG
+                reg: t0
+              -
+                type: LOONGARCH_OP_IMM
+                imm: -1
+  -
+    input:
+      bytes: [ 0x80, 0x80, 0x00, 0x40, 0x63, 0x80, 0xff, 0x02, 0x78, 0x20, 0xc0, 0x29, 0x00, 0x84, 0x00, 0x01, 0x00, 0xa4, 0x14, 0x01  ]
+      arch: "loongarch"
+      options: [ CS_OPT_DETAIL, CS_MODE_LOONGARCH64]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "beqz $a0, 0x80"
+        details:
+          loongarch:
+            operands:
+              -
+                type: LOONGARCH_OP_REG
+                reg: a0
+              -
+                type: LOONGARCH_OP_IMM
+                imm: 0x80
+          groups: [ LOONGARCH_GRP_JUMP, LOONGARCH_GRP_BRANCH_RELATIVE ]
+      -
+        asm_text: "addi.d $sp, $sp, -0x20"
+        details:
+          loongarch:
+            operands:
+              -
+                type: LOONGARCH_OP_REG
+                reg: sp
+              -
+                type: LOONGARCH_OP_REG
+                reg: sp
+              -
+                type: LOONGARCH_OP_IMM
+                imm: -0x20
+          groups: [ LOONGARCH_FEATURE_ISLA64 ]
+      -
+        asm_text: "st.d $s1, $sp, 8"
+        details:
+          loongarch:
+            operands:
+              -
+                type: LOONGARCH_OP_REG
+                reg: s1
+              -
+                type: LOONGARCH_OP_MEM
+                mem_base: sp
+                mem_disp: 0x8
+          groups: [ LOONGARCH_FEATURE_ISLA64 ]
+      -
+        asm_text: "fadd.s $fa0, $fa0, $fa1"
+        details:
+          loongarch:
+            operands:
+              -
+                type: LOONGARCH_OP_REG
+                reg: fa0
+              -
+                type: LOONGARCH_OP_REG
+                reg: fa0
+              -
+                type: LOONGARCH_OP_REG
+                reg: fa1
+      -
+        asm_text: "movgr2fr.w $fa0, $zero"
+        details:
+          loongarch:
+            operands:
+              -
+                type: LOONGARCH_OP_REG
+                reg: fa0
+              -
+                type: LOONGARCH_OP_REG
+                reg: zero
diff --git a/tests/details/m680x.yaml b/tests/details/m680x.yaml
new file mode 100644
index 000000000..162231c4f
--- /dev/null
+++ b/tests/details/m680x.yaml
@@ -0,0 +1,3271 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x6b, 0x10, 0x00, 0x71, 0x10, 0x00, 0x72, 0x10, 0x10, 0x39  ]
+      arch: "m680x"
+      options: [ CS_OPT_DETAIL, CS_MODE_M680X_6301 ]
+      address: 0x1000
+    expected:
+      insns:
+      -
+        asm_text: "tim #16; 0, x"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_IMMEDIATE
+                imm: 16
+                size: 1
+                access: CS_AC_READ
+              -
+                type: M680X_OP_INDEXED
+                idx:
+                  base_reg: x
+                  offset: 0
+                  offset_bits: 8
+                size: 1
+                access: CS_AC_READ
+          regs_read: [ cc, x ]
+          regs_write: [ cc ]
+      -
+        asm_text: "aim #16, $00"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_IMMEDIATE
+                imm: 16
+                size: 1
+                access: CS_AC_READ
+              -
+                type: M680X_OP_DIRECT
+                direct_addr: 0x0000
+                direct_addr_set: true
+                size: 1
+                access: CS_AC_READ_WRITE
+          regs_read: [ cc ]
+          regs_write: [ cc ]
+      -
+        asm_text: "oim #16, $10"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_IMMEDIATE
+                imm: 16
+                size: 1
+                access: CS_AC_READ
+              -
+                type: M680X_OP_DIRECT
+                direct_addr: 0x0010
+                direct_addr_set: true
+                size: 1
+                access: CS_AC_READ_WRITE
+          regs_read: [ cc ]
+          regs_write: [ cc ]
+      -
+        asm_text: "rts"
+        details:
+          regs_read: [ s ]
+          regs_write: [ s, pc ]
+          groups: [ M680X_GRP_RET ]
+  -
+    input:
+      bytes: [ 0x01, 0x10, 0x10, 0x62, 0x10, 0x10, 0x7b, 0x10, 0x10, 0x00, 0xcd, 0x49, 0x96, 0x02, 0xd2, 0x10, 0x30, 0x23, 0x10, 0x38, 0x10, 0x3b, 0x10, 0x53, 0x10, 0x5d, 0x11, 0x30, 0x43, 0x10, 0x11, 0x37, 0x25, 0x10, 0x11, 0x38, 0x12, 0x11, 0x39, 0x23, 0x11, 0x3b, 0x34, 0x11, 0x8e, 0x10, 0x00, 0x11, 0xaf, 0x10, 0x11, 0xab, 0x10, 0x11, 0xf6, 0x80, 0x00  ]
+      arch: "m680x"
+      options: [ CS_OPT_DETAIL, CS_MODE_M680X_6309 ]
+      address: 0x1000
+    expected:
+      insns:
+      -
+        asm_text: "oim #16, $10"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_IMMEDIATE
+                imm: 16
+                size: 1
+                access: CS_AC_READ
+              -
+                type: M680X_OP_DIRECT
+                direct_addr: 0x0010
+                direct_addr_set: true
+                size: 1
+                access: CS_AC_READ_WRITE
+          regs_read: [ cc ]
+          regs_write: [ cc ]
+      -
+        asm_text: "aim #16; -16, x"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_IMMEDIATE
+                imm: 16
+                size: 1
+                access: CS_AC_READ
+              -
+                type: M680X_OP_INDEXED
+                idx:
+                  base_reg: x
+                  offset: -16
+                  offset_bits: 5
+                size: 1
+                access: CS_AC_READ_WRITE
+          regs_read: [ cc, x ]
+          regs_write: [ cc ]
+      -
+        asm_text: "tim #16, $1000"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_IMMEDIATE
+                imm: 16
+                size: 1
+                access: CS_AC_READ
+              -
+                type: M680X_OP_EXTENDED
+                ext_address: 0x1000
+                ext_indirect: -1
+                size: 1
+                access: CS_AC_READ
+          regs_read: [ cc ]
+          regs_write: [ cc ]
+      -
+        asm_text: "ldq #1234567890"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: q
+                size: 4
+                access: CS_AC_WRITE
+              -
+                type: M680X_OP_IMMEDIATE
+                imm: 1234567890
+                size: 4
+                access: CS_AC_READ
+            flags: [M680X_FIRST_OP_IN_MNEM ]
+          regs_read: [ cc ]
+          regs_write: [ cc, q ]
+      -
+        asm_text: "addr y, u"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: y
+                size: 2
+                access: CS_AC_READ
+              -
+                type: M680X_OP_REGISTER
+                reg: u
+                size: 2
+                access: CS_AC_READ_WRITE
+          regs_read: [ cc, y, u ]
+          regs_write: [ cc, u ]
+      -
+        asm_text: "pshsw"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: s
+                size: 2
+                access: CS_AC_READ_WRITE
+              -
+                type: M680X_OP_REGISTER
+                reg: w
+                size: 2
+                access: CS_AC_READ
+            flags: [M680X_FIRST_OP_IN_MNEM, M680X_SECOND_OP_IN_MNEM ]
+          regs_read: [ s, w ]
+          regs_write: [ s ]
+      -
+        asm_text: "puluw"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: u
+                size: 2
+                access: CS_AC_READ_WRITE
+              -
+                type: M680X_OP_REGISTER
+                reg: w
+                size: 2
+                access: CS_AC_WRITE
+            flags: [M680X_FIRST_OP_IN_MNEM, M680X_SECOND_OP_IN_MNEM ]
+          regs_read: [ u ]
+          regs_write: [ u, w ]
+      -
+        asm_text: "comw"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: w
+                size: 2
+                access: CS_AC_READ_WRITE
+            flags: [M680X_FIRST_OP_IN_MNEM ]
+          regs_read: [ cc, w ]
+          regs_write: [ cc, w ]
+      -
+        asm_text: "tstw"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: w
+                size: 2
+                access: CS_AC_READ
+            flags: [M680X_FIRST_OP_IN_MNEM ]
+          regs_read: [ cc, w ]
+          regs_write: [ cc ]
+      -
+        asm_text: "band a, 0, 3, $10"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: a
+                size: 1
+                access: CS_AC_READ_WRITE
+              -
+                type: M680X_OP_CONSTANT
+                const_val: 0
+                access: CS_AC_READ
+              -
+                type: M680X_OP_CONSTANT
+                const_val: 3
+                access: CS_AC_READ
+              -
+                type: M680X_OP_DIRECT
+                direct_addr: 0x0010
+                direct_addr_set: true
+                size: 1
+                access: CS_AC_READ
+          regs_read: [ a ]
+          regs_write: [ a ]
+      -
+        asm_text: "stbt cc, 4, 5, $10"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: cc
+                size: 1
+                access: CS_AC_READ
+              -
+                type: M680X_OP_CONSTANT
+                const_val: 4
+                access: CS_AC_READ
+              -
+                type: M680X_OP_CONSTANT
+                const_val: 5
+                access: CS_AC_READ
+              -
+                type: M680X_OP_DIRECT
+                direct_addr: 0x0010
+                direct_addr_set: true
+                size: 1
+                access: CS_AC_READ_WRITE
+          regs_read: [ cc ]
+      -
+        asm_text: "tfm x+, y+"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_INDEXED
+                idx:
+                  base_reg: x
+                  inc_dec: 1
+                  flags: [ M680X_IDX_NO_COMMA, M680X_IDX_POST_INC_DEC ]
+                size: 1
+                access: CS_AC_READ
+              -
+                type: M680X_OP_INDEXED
+                idx:
+                  base_reg: y
+                  inc_dec: 1
+                  flags: [ M680X_IDX_NO_COMMA, M680X_IDX_POST_INC_DEC ]
+                size: 1
+                access: CS_AC_WRITE
+          regs_read: [ w, x, y ]
+          regs_write: [ w, x, y ]
+      -
+        asm_text: "tfm y-, u-"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_INDEXED
+                idx:
+                  base_reg: y
+                  inc_dec: -1
+                  flags: [ M680X_IDX_NO_COMMA, M680X_IDX_POST_INC_DEC ]
+                size: 1
+                access: CS_AC_READ
+              -
+                type: M680X_OP_INDEXED
+                idx:
+                  base_reg: u
+                  inc_dec: -1
+                  flags: [ M680X_IDX_NO_COMMA, M680X_IDX_POST_INC_DEC ]
+                size: 1
+                access: CS_AC_WRITE
+          regs_read: [ w, y, u ]
+          regs_write: [ w, y, u ]
+      -
+        asm_text: "tfm u, s+"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_INDEXED
+                idx:
+                  base_reg: u
+                  flags: [ M680X_IDX_NO_COMMA ]
+                size: 1
+                access: CS_AC_READ
+              -
+                type: M680X_OP_INDEXED
+                idx:
+                  base_reg: s
+                  inc_dec: 1
+                  flags: [ M680X_IDX_NO_COMMA, M680X_IDX_POST_INC_DEC ]
+                size: 1
+                access: CS_AC_WRITE
+          regs_read: [ w, u, s ]
+          regs_write: [ w, s ]
+      -
+        asm_text: "divq #4096"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: q
+                size: 4
+                access: CS_AC_READ_WRITE
+              -
+                type: M680X_OP_IMMEDIATE
+                imm: 4096
+                size: 2
+                access: CS_AC_READ
+            flags: [M680X_FIRST_OP_IN_MNEM ]
+          regs_read: [ cc, q ]
+          regs_write: [ cc, q ]
+      -
+        asm_text: "muld -16, x"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: d
+                size: 2
+                access: CS_AC_READ_WRITE
+              -
+                type: M680X_OP_INDEXED
+                idx:
+                  base_reg: x
+                  offset: -16
+                  offset_bits: 5
+                size: 2
+                access: CS_AC_READ
+            flags: [M680X_FIRST_OP_IN_MNEM ]
+          regs_read: [ cc, d, x ]
+          regs_write: [ cc, d, w ]
+      -
+        asm_text: "adde -16, x"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: e
+                size: 1
+                access: CS_AC_READ_WRITE
+              -
+                type: M680X_OP_INDEXED
+                idx:
+                  base_reg: x
+                  offset: -16
+                  offset_bits: 5
+                size: 1
+                access: CS_AC_READ
+            flags: [M680X_FIRST_OP_IN_MNEM ]
+          regs_read: [ cc, e, x ]
+          regs_write: [ cc, e ]
+      -
+        asm_text: "ldf $8000"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: f
+                size: 1
+                access: CS_AC_WRITE
+              -
+                type: M680X_OP_EXTENDED
+                ext_address: 0x8000
+                ext_indirect: -1
+                size: 1
+                access: CS_AC_READ
+            flags: [M680X_FIRST_OP_IN_MNEM ]
+          regs_read: [ cc ]
+          regs_write: [ cc, f ]
+  -
+    input:
+      bytes: [ 0x01, 0x09, 0x36, 0x64, 0x7f, 0x74, 0x10, 0x00, 0x90, 0x10, 0xa4, 0x10, 0xb6, 0x10, 0x00, 0x39  ]
+      arch: "m680x"
+      options: [ CS_OPT_DETAIL, CS_MODE_M680X_6800 ]
+      address: 0x1000
+    expected:
+      insns:
+      -
+        asm_text: "nop"
+      -
+        asm_text: "dex"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: x
+                size: 2
+                access: CS_AC_READ_WRITE
+            flags: [M680X_FIRST_OP_IN_MNEM ]
+          regs_read: [ cc, x ]
+          regs_write: [ cc, x ]
+      -
+        asm_text: "psha"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: a
+                size: 1
+                access: CS_AC_READ
+            flags: [M680X_FIRST_OP_IN_MNEM ]
+          regs_read: [ a, s ]
+          regs_write: [ s ]
+      -
+        asm_text: "lsr 127, x"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_INDEXED
+                idx:
+                  base_reg: x
+                  offset: 127
+                  offset_bits: 8
+                size: 1
+                access: CS_AC_READ_WRITE
+          regs_read: [ cc, x ]
+          regs_write: [ cc ]
+      -
+        asm_text: "lsr $1000"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_EXTENDED
+                ext_address: 0x1000
+                ext_indirect: -1
+                size: 1
+                access: CS_AC_READ_WRITE
+          regs_read: [ cc ]
+          regs_write: [ cc ]
+      -
+        asm_text: "suba $10"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: a
+                size: 1
+                access: CS_AC_READ_WRITE
+              -
+                type: M680X_OP_DIRECT
+                direct_addr: 0x0010
+                direct_addr_set: true
+                size: 1
+                access: CS_AC_READ
+            flags: [M680X_FIRST_OP_IN_MNEM ]
+          regs_read: [ cc, a ]
+          regs_write: [ cc, a ]
+      -
+        asm_text: "anda 16, x"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: a
+                size: 1
+                access: CS_AC_READ_WRITE
+              -
+                type: M680X_OP_INDEXED
+                idx:
+                  base_reg: x
+                  offset: 16
+                  offset_bits: 8
+                size: 1
+                access: CS_AC_READ
+            flags: [M680X_FIRST_OP_IN_MNEM ]
+          regs_read: [ cc, a, x ]
+          regs_write: [ cc, a ]
+      -
+        asm_text: "ldaa $1000"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: a
+                size: 1
+                access: CS_AC_WRITE
+              -
+                type: M680X_OP_EXTENDED
+                ext_address: 0x1000
+                ext_indirect: -1
+                size: 1
+                access: CS_AC_READ
+            flags: [M680X_FIRST_OP_IN_MNEM ]
+          regs_read: [ cc ]
+          regs_write: [ cc, a ]
+      -
+        asm_text: "rts"
+        details:
+          regs_read: [ s ]
+          regs_write: [ s, pc ]
+          groups: [ M680X_GRP_RET ]
+  -
+    input:
+      bytes: [ 0x04, 0x05, 0x3c, 0x3d, 0x38, 0x93, 0x10, 0xec, 0x10, 0xed, 0x10, 0x39  ]
+      arch: "m680x"
+      options: [ CS_OPT_DETAIL, CS_MODE_M680X_6801 ]
+      address: 0x1000
+    expected:
+      insns:
+      -
+        asm_text: "lsrd"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: d
+                size: 2
+                access: CS_AC_READ_WRITE
+            flags: [M680X_FIRST_OP_IN_MNEM ]
+          regs_read: [ cc, d ]
+          regs_write: [ cc, d ]
+      -
+        asm_text: "asld"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: d
+                size: 2
+                access: CS_AC_READ_WRITE
+            flags: [M680X_FIRST_OP_IN_MNEM ]
+          regs_read: [ cc, d ]
+          regs_write: [ cc, d ]
+      -
+        asm_text: "pshx"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: x
+                size: 2
+                access: CS_AC_READ
+            flags: [M680X_FIRST_OP_IN_MNEM ]
+          regs_read: [ x, s ]
+          regs_write: [ s ]
+      -
+        asm_text: "mul"
+        details:
+          regs_read: [ cc, a, b ]
+          regs_write: [ cc, a, b ]
+      -
+        asm_text: "pulx"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: x
+                size: 2
+                access: CS_AC_WRITE
+            flags: [M680X_FIRST_OP_IN_MNEM ]
+          regs_read: [ s ]
+          regs_write: [ x, s ]
+      -
+        asm_text: "subd $10"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: d
+                size: 2
+                access: CS_AC_READ_WRITE
+              -
+                type: M680X_OP_DIRECT
+                direct_addr: 0x0010
+                direct_addr_set: true
+                size: 2
+                access: CS_AC_READ
+            flags: [M680X_FIRST_OP_IN_MNEM ]
+          regs_read: [ cc, d ]
+          regs_write: [ cc, d ]
+      -
+        asm_text: "ldd 16, x"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: d
+                size: 2
+                access: CS_AC_WRITE
+              -
+                type: M680X_OP_INDEXED
+                idx:
+                  base_reg: x
+                  offset: 16
+                  offset_bits: 8
+                size: 2
+                access: CS_AC_READ
+            flags: [M680X_FIRST_OP_IN_MNEM ]
+          regs_read: [ cc, x ]
+          regs_write: [ cc, d ]
+      -
+        asm_text: "std 16, x"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: d
+                size: 2
+                access: CS_AC_READ
+              -
+                type: M680X_OP_INDEXED
+                idx:
+                  base_reg: x
+                  offset: 16
+                  offset_bits: 8
+                size: 2
+                access: CS_AC_WRITE
+            flags: [M680X_FIRST_OP_IN_MNEM ]
+          regs_read: [ cc, d, x ]
+          regs_write: [ cc ]
+      -
+        asm_text: "rts"
+        details:
+          regs_read: [ s ]
+          regs_write: [ s, pc ]
+          groups: [ M680X_GRP_RET ]
+  -
+    input:
+      bytes: [ 0x04, 0x7f, 0x00, 0x17, 0x22, 0x28, 0x00, 0x2e, 0x00, 0x40, 0x42, 0x5a, 0x70, 0x8e, 0x97, 0x9c, 0xa0, 0x15, 0xad, 0x00, 0xc3, 0x10, 0x00, 0xda, 0x12, 0x34, 0xe5, 0x7f, 0xfe  ]
+      arch: "m680x"
+      options: [ CS_OPT_DETAIL, CS_MODE_M680X_6805 ]
+      address: 0x1000
+    expected:
+      insns:
+      -
+        asm_text: "brset 2, $7f, $1003"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_CONSTANT
+                const_val: 2
+                access: CS_AC_READ
+              -
+                type: M680X_OP_DIRECT
+                direct_addr: 0x007f
+                direct_addr_set: true
+                size: 1
+                access: CS_AC_READ
+              -
+                type: M680X_OP_RELATIVE
+                rel_address: 0x1003
+                rel_offset: 0
+          regs_read: [ cc ]
+          regs_write: [ cc ]
+          groups: [  M680X_GRP_BRAREL, M680X_GRP_JUMP ]
+      -
+        asm_text: "bset 3, $22"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_CONSTANT
+                const_val: 3
+                access: CS_AC_READ
+              -
+                type: M680X_OP_DIRECT
+                direct_addr: 0x0022
+                direct_addr_set: true
+                size: 1
+                access: CS_AC_READ_WRITE
+      -
+        asm_text: "bhcc $1007"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_RELATIVE
+                rel_address: 0x1007
+                rel_offset: 0
+          regs_read: [ cc ]
+          groups: [  M680X_GRP_BRAREL, M680X_GRP_JUMP ]
+      -
+        asm_text: "bil $1009"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_RELATIVE
+                rel_address: 0x1009
+                rel_offset: 0
+          regs_read: [ cc ]
+          groups: [  M680X_GRP_BRAREL, M680X_GRP_JUMP ]
+      -
+        asm_text: "nega"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: a
+                size: 1
+                access: CS_AC_READ_WRITE
+            flags: [M680X_FIRST_OP_IN_MNEM ]
+          regs_read: [ cc, a ]
+          regs_write: [ cc, a ]
+      -
+        asm_text: "mul"
+        details:
+          regs_read: [ cc, a, x ]
+          regs_write: [ cc, a, x ]
+      -
+        asm_text: "decx"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: x
+                size: 1
+                access: CS_AC_READ_WRITE
+            flags: [M680X_FIRST_OP_IN_MNEM ]
+          regs_read: [ cc, x ]
+          regs_write: [ cc, x ]
+      -
+        asm_text: "neg , x"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_INDEXED
+                idx:
+                  base_reg: x
+                size: 1
+                access: CS_AC_READ_WRITE
+          regs_read: [ cc, x ]
+          regs_write: [ cc ]
+      -
+        asm_text: "stop"
+      -
+        asm_text: "tax"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: a
+                size: 1
+                access: CS_AC_READ
+              -
+                type: M680X_OP_REGISTER
+                reg: x
+                size: 1
+                access: CS_AC_WRITE
+            flags: [M680X_FIRST_OP_IN_MNEM, M680X_SECOND_OP_IN_MNEM ]
+          regs_read: [ a ]
+          regs_write: [ x ]
+      -
+        asm_text: "rsp"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: s
+                size: 2
+                access: CS_AC_WRITE
+            flags: [M680X_FIRST_OP_IN_MNEM ]
+          regs_write: [ s ]
+      -
+        asm_text: "sub #21"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: a
+                size: 1
+                access: CS_AC_READ_WRITE
+              -
+                type: M680X_OP_IMMEDIATE
+                imm: 21
+                size: 1
+                access: CS_AC_READ
+            flags: [M680X_FIRST_OP_IN_MNEM ]
+          regs_read: [ cc, a ]
+          regs_write: [ cc, a ]
+      -
+        asm_text: "bsr $1014"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_RELATIVE
+                rel_address: 0x1014
+                rel_offset: 0
+          regs_read: [ s ]
+          regs_write: [ s ]
+          groups: [  M680X_GRP_BRAREL, M680X_GRP_CALL ]
+      -
+        asm_text: "cpx $1000"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: x
+                size: 1
+                access: CS_AC_READ
+              -
+                type: M680X_OP_EXTENDED
+                ext_address: 0x1000
+                ext_indirect: -1
+                size: 1
+                access: CS_AC_READ
+            flags: [M680X_FIRST_OP_IN_MNEM ]
+          regs_read: [ cc, x ]
+          regs_write: [ cc ]
+      -
+        asm_text: "ora 4660, x"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: a
+                size: 1
+                access: CS_AC_READ_WRITE
+              -
+                type: M680X_OP_INDEXED
+                idx:
+                  base_reg: x
+                  offset: 4660
+                  offset_bits: 16
+                size: 1
+                access: CS_AC_READ
+            flags: [M680X_FIRST_OP_IN_MNEM ]
+          regs_read: [ cc, a, x ]
+          regs_write: [ cc, a ]
+      -
+        asm_text: "bit 127, x"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: a
+                size: 1
+                access: CS_AC_READ
+              -
+                type: M680X_OP_INDEXED
+                idx:
+                  base_reg: x
+                  offset: 127
+                  offset_bits: 8
+                size: 1
+                access: CS_AC_READ
+            flags: [M680X_FIRST_OP_IN_MNEM ]
+          regs_read: [ cc, a, x ]
+          regs_write: [ cc ]
+      -
+        asm_text: "ldx , x"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: x
+                size: 1
+                access: CS_AC_WRITE
+              -
+                type: M680X_OP_INDEXED
+                idx:
+                  base_reg: x
+                size: 1
+                access: CS_AC_READ
+            flags: [M680X_FIRST_OP_IN_MNEM ]
+          regs_read: [ cc, x ]
+          regs_write: [ cc, x ]
+  -
+    input:
+      bytes: [ 0x31, 0x22, 0x00, 0x35, 0x22, 0x45, 0x10, 0x00, 0x4b, 0x00, 0x51, 0x10, 0x52, 0x5e, 0x22, 0x62, 0x65, 0x12, 0x34, 0x72, 0x84, 0x85, 0x86, 0x87, 0x8a, 0x8b, 0x8c, 0x94, 0x95, 0xa7, 0x10, 0xaf, 0x10, 0x9e, 0x60, 0x7f, 0x9e, 0x6b, 0x7f, 0x00, 0x9e, 0xd6, 0x10, 0x00, 0x9e, 0xe6, 0x7f  ]
+      arch: "m680x"
+      options: [ CS_OPT_DETAIL, CS_MODE_M680X_6808 ]
+      address: 0x1000
+    expected:
+      insns:
+      -
+        asm_text: "cbeq $22, $1003"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: a
+                size: 1
+                access: CS_AC_READ
+              -
+                type: M680X_OP_DIRECT
+                direct_addr: 0x0022
+                direct_addr_set: true
+                size: 1
+                access: CS_AC_READ
+              -
+                type: M680X_OP_RELATIVE
+                rel_address: 0x1003
+                rel_offset: 0
+            flags: [M680X_FIRST_OP_IN_MNEM ]
+          regs_read: [ cc, a ]
+          groups: [  M680X_GRP_BRAREL, M680X_GRP_JUMP ]
+      -
+        asm_text: "sthx $22"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: hx
+                size: 2
+                access: CS_AC_READ
+              -
+                type: M680X_OP_DIRECT
+                direct_addr: 0x0022
+                direct_addr_set: true
+                size: 2
+                access: CS_AC_WRITE
+            flags: [M680X_FIRST_OP_IN_MNEM ]
+          regs_read: [ cc, hx ]
+          regs_write: [ cc ]
+      -
+        asm_text: "ldhx #4096"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: hx
+                size: 2
+                access: CS_AC_WRITE
+              -
+                type: M680X_OP_IMMEDIATE
+                imm: 4096
+                size: 2
+                access: CS_AC_READ
+            flags: [M680X_FIRST_OP_IN_MNEM ]
+          regs_read: [ cc ]
+          regs_write: [ cc, hx ]
+      -
+        asm_text: "dbnza $100a"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: a
+                size: 1
+                access: CS_AC_READ_WRITE
+              -
+                type: M680X_OP_RELATIVE
+                rel_address: 0x100a
+                rel_offset: 0
+            flags: [M680X_FIRST_OP_IN_MNEM ]
+          regs_read: [ cc, a ]
+          regs_write: [ a ]
+          groups: [  M680X_GRP_BRAREL, M680X_GRP_JUMP ]
+      -
+        asm_text: "cbeqx #16, $105f"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: x
+                size: 1
+                access: CS_AC_READ
+              -
+                type: M680X_OP_IMMEDIATE
+                imm: 16
+                size: 1
+                access: CS_AC_READ
+              -
+                type: M680X_OP_RELATIVE
+                rel_address: 0x105f
+                rel_offset: 82
+            flags: [M680X_FIRST_OP_IN_MNEM ]
+          regs_read: [ cc, x ]
+          groups: [  M680X_GRP_BRAREL, M680X_GRP_JUMP ]
+      -
+        asm_text: "mov $22; x+"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_DIRECT
+                direct_addr: 0x0022
+                direct_addr_set: true
+                size: 1
+                access: CS_AC_READ
+              -
+                type: M680X_OP_INDEXED
+                idx:
+                  base_reg: x
+                  inc_dec: 1
+                  flags: [ M680X_IDX_NO_COMMA, M680X_IDX_POST_INC_DEC ]
+                size: 1
+                access: CS_AC_WRITE
+          regs_read: [ cc, x, h ]
+          regs_write: [ cc, x, h ]
+      -
+        asm_text: "nsa"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: a
+                size: 1
+                access: CS_AC_READ_WRITE
+            flags: [M680X_FIRST_OP_IN_MNEM ]
+          regs_read: [ cc, a ]
+          regs_write: [ cc, a ]
+      -
+        asm_text: "cphx #4660"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: hx
+                size: 2
+                access: CS_AC_READ
+              -
+                type: M680X_OP_IMMEDIATE
+                imm: 4660
+                size: 2
+                access: CS_AC_READ
+            flags: [M680X_FIRST_OP_IN_MNEM ]
+          regs_read: [ cc, hx ]
+          regs_write: [ cc ]
+      -
+        asm_text: "daa"
+        details:
+          regs_read: [ cc, a ]
+          regs_write: [ cc, a ]
+      -
+        asm_text: "tap"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: a
+                size: 1
+                access: CS_AC_READ
+              -
+                type: M680X_OP_REGISTER
+                reg: cc
+                size: 1
+                access: CS_AC_WRITE
+            flags: [M680X_FIRST_OP_IN_MNEM, M680X_SECOND_OP_IN_MNEM ]
+          regs_read: [ a ]
+          regs_write: [ cc ]
+      -
+        asm_text: "tpa"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: cc
+                size: 1
+                access: CS_AC_READ
+              -
+                type: M680X_OP_REGISTER
+                reg: a
+                size: 1
+                access: CS_AC_WRITE
+            flags: [M680X_FIRST_OP_IN_MNEM, M680X_SECOND_OP_IN_MNEM ]
+          regs_read: [ cc ]
+          regs_write: [ a ]
+      -
+        asm_text: "pula"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: a
+                size: 1
+                access: CS_AC_WRITE
+            flags: [M680X_FIRST_OP_IN_MNEM ]
+          regs_read: [ s ]
+          regs_write: [ a, s ]
+      -
+        asm_text: "psha"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: a
+                size: 1
+                access: CS_AC_READ
+            flags: [M680X_FIRST_OP_IN_MNEM ]
+          regs_read: [ a, s ]
+          regs_write: [ s ]
+      -
+        asm_text: "pulh"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: h
+                size: 1
+                access: CS_AC_WRITE
+            flags: [M680X_FIRST_OP_IN_MNEM ]
+          regs_read: [ s ]
+          regs_write: [ h, s ]
+      -
+        asm_text: "pshh"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: h
+                size: 1
+                access: CS_AC_READ
+            flags: [M680X_FIRST_OP_IN_MNEM ]
+          regs_read: [ h, s ]
+          regs_write: [ s ]
+      -
+        asm_text: "clrh"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: h
+                size: 1
+                access: CS_AC_WRITE
+            flags: [M680X_FIRST_OP_IN_MNEM ]
+          regs_read: [ cc ]
+          regs_write: [ cc, h ]
+      -
+        asm_text: "txs"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: hx
+                size: 2
+                access: CS_AC_READ
+              -
+                type: M680X_OP_REGISTER
+                reg: s
+                size: 2
+                access: CS_AC_WRITE
+            flags: [M680X_FIRST_OP_IN_MNEM, M680X_SECOND_OP_IN_MNEM ]
+          regs_read: [ hx ]
+          regs_write: [ s ]
+      -
+        asm_text: "tsx"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: s
+                size: 2
+                access: CS_AC_READ
+              -
+                type: M680X_OP_REGISTER
+                reg: hx
+                size: 2
+                access: CS_AC_WRITE
+            flags: [M680X_FIRST_OP_IN_MNEM, M680X_SECOND_OP_IN_MNEM ]
+          regs_read: [ s ]
+          regs_write: [ hx ]
+      -
+        asm_text: "ais #16"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: s
+                size: 2
+                access: CS_AC_READ_WRITE
+              -
+                type: M680X_OP_IMMEDIATE
+                imm: 16
+                size: 1
+                access: CS_AC_READ
+            flags: [M680X_FIRST_OP_IN_MNEM ]
+          regs_read: [ s ]
+          regs_write: [ s ]
+      -
+        asm_text: "aix #16"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: hx
+                size: 2
+                access: CS_AC_READ_WRITE
+              -
+                type: M680X_OP_IMMEDIATE
+                imm: 16
+                size: 1
+                access: CS_AC_READ
+            flags: [M680X_FIRST_OP_IN_MNEM ]
+          regs_read: [ hx ]
+          regs_write: [ hx ]
+      -
+        asm_text: "neg 127, s"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_INDEXED
+                idx:
+                  base_reg: s
+                  offset: 127
+                  offset_bits: 8
+                size: 1
+                access: CS_AC_READ_WRITE
+          regs_read: [ cc, s ]
+          regs_write: [ cc ]
+      -
+        asm_text: "dbnz 127, s; $1028"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_INDEXED
+                idx:
+                  base_reg: s
+                  offset: 127
+                  offset_bits: 8
+                size: 1
+                access: CS_AC_READ_WRITE
+              -
+                type: M680X_OP_RELATIVE
+                rel_address: 0x1028
+                rel_offset: 0
+          regs_read: [ cc, s ]
+          groups: [  M680X_GRP_BRAREL, M680X_GRP_JUMP ]
+      -
+        asm_text: "lda 4096, s"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: a
+                size: 1
+                access: CS_AC_WRITE
+              -
+                type: M680X_OP_INDEXED
+                idx:
+                  base_reg: s
+                  offset: 4096
+                  offset_bits: 16
+                size: 1
+                access: CS_AC_READ
+            flags: [M680X_FIRST_OP_IN_MNEM ]
+          regs_read: [ cc, s ]
+          regs_write: [ cc, a ]
+      -
+        asm_text: "lda 127, s"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: a
+                size: 1
+                access: CS_AC_WRITE
+              -
+                type: M680X_OP_INDEXED
+                idx:
+                  base_reg: s
+                  offset: 127
+                  offset_bits: 8
+                size: 1
+                access: CS_AC_READ
+            flags: [M680X_FIRST_OP_IN_MNEM ]
+          regs_read: [ cc, s ]
+          regs_write: [ cc, a ]
+  -
+    input:
+      bytes: [ 0x06, 0x10, 0x19, 0x1a, 0x55, 0x1e, 0x01, 0x23, 0xe9, 0x31, 0x06, 0x34, 0x55, 0xa6, 0x81, 0xa7, 0x89, 0x7f, 0xff, 0xa6, 0x9d, 0x10, 0x00, 0xa7, 0x91, 0xa6, 0x9f, 0x10, 0x00, 0x11, 0xac, 0x99, 0x10, 0x00, 0x39, 0xa6, 0x07, 0xa6, 0x27, 0xa6, 0x47, 0xa6, 0x67, 0xa6, 0x0f, 0xa6, 0x10, 0xa6, 0x80, 0xa6, 0x81, 0xa6, 0x82, 0xa6, 0x83, 0xa6, 0x84, 0xa6, 0x85, 0xa6, 0x86, 0xa6, 0x88, 0x7f, 0xa6, 0x88, 0x80, 0xa6, 0x89, 0x7f, 0xff, 0xa6, 0x89, 0x80, 0x00, 0xa6, 0x8b, 0xa6, 0x8c, 0x10, 0xa6, 0x8d, 0x10, 0x00, 0xa6, 0x91, 0xa6, 0x93, 0xa6, 0x94, 0xa6, 0x95, 0xa6, 0x96, 0xa6, 0x98, 0x7f, 0xa6, 0x98, 0x80, 0xa6, 0x99, 0x7f, 0xff, 0xa6, 0x99, 0x80, 0x00, 0xa6, 0x9b, 0xa6, 0x9c, 0x10, 0xa6, 0x9d, 0x10, 0x00, 0xa6, 0x9f, 0x10, 0x00  ]
+      arch: "m680x"
+      options: [ CS_OPT_DETAIL, CS_MODE_M680X_6809 ]
+      address: 0x1000
+    expected:
+      insns:
+      -
+        asm_text: "ror $10"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_DIRECT
+                direct_addr: 0x0010
+                direct_addr_set: true
+                size: 1
+                access: CS_AC_READ_WRITE
+          regs_read: [ cc ]
+          regs_write: [ cc ]
+      -
+        asm_text: "daa"
+        details:
+          regs_read: [ cc, a ]
+          regs_write: [ cc, a ]
+      -
+        asm_text: "orcc #85"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: cc
+                size: 1
+                access: CS_AC_READ_WRITE
+              -
+                type: M680X_OP_IMMEDIATE
+                imm: 85
+                size: 1
+                access: CS_AC_READ
+            flags: [M680X_FIRST_OP_IN_MNEM ]
+          regs_read: [ cc ]
+          regs_write: [ cc ]
+      -
+        asm_text: "exg d, x"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: d
+                size: 2
+                access: CS_AC_READ_WRITE
+              -
+                type: M680X_OP_REGISTER
+                reg: x
+                size: 2
+                access: CS_AC_READ_WRITE
+          regs_read: [ d, x ]
+          regs_write: [ d, x ]
+      -
+        asm_text: "bls $0ff2"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_RELATIVE
+                rel_address: 0x0ff2
+                rel_offset: -23
+          regs_read: [ cc ]
+          groups: [  M680X_GRP_BRAREL, M680X_GRP_JUMP ]
+      -
+        asm_text: "leay 6, x"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: y
+                size: 2
+                access: CS_AC_WRITE
+              -
+                type: M680X_OP_INDEXED
+                idx:
+                  base_reg: x
+                  offset: 6
+                  offset_bits: 5
+                size: 2
+                access: CS_AC_READ
+            flags: [M680X_FIRST_OP_IN_MNEM ]
+          regs_read: [ cc, x ]
+          regs_write: [ cc, y ]
+      -
+        asm_text: "pshs cc, b, x, u"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: s
+                size: 2
+                access: CS_AC_READ_WRITE
+              -
+                type: M680X_OP_REGISTER
+                reg: cc
+                size: 1
+                access: CS_AC_READ
+              -
+                type: M680X_OP_REGISTER
+                reg: b
+                size: 1
+                access: CS_AC_READ
+              -
+                type: M680X_OP_REGISTER
+                reg: x
+                size: 2
+                access: CS_AC_READ
+              -
+                type: M680X_OP_REGISTER
+                reg: u
+                size: 2
+                access: CS_AC_READ
+            flags: [M680X_FIRST_OP_IN_MNEM ]
+          regs_read: [ s, cc, b, x, u ]
+          regs_write: [ s ]
+      -
+        asm_text: "lda , x++"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: a
+                size: 1
+                access: CS_AC_WRITE
+              -
+                type: M680X_OP_INDEXED
+                idx:
+                  base_reg: x
+                  inc_dec: 2
+                  flags: [ M680X_IDX_POST_INC_DEC ]
+                size: 1
+                access: CS_AC_READ
+            flags: [M680X_FIRST_OP_IN_MNEM ]
+          regs_read: [ cc, x ]
+          regs_write: [ cc, a, x ]
+      -
+        asm_text: "sta 32767, x"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: a
+                size: 1
+                access: CS_AC_READ
+              -
+                type: M680X_OP_INDEXED
+                idx:
+                  base_reg: x
+                  offset: 32767
+                  offset_bits: 16
+                size: 1
+                access: CS_AC_WRITE
+            flags: [M680X_FIRST_OP_IN_MNEM ]
+          regs_read: [ cc, a, x ]
+          regs_write: [ cc ]
+      -
+        asm_text: "lda [$2017, pcr]"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: a
+                size: 1
+                access: CS_AC_WRITE
+              -
+                type: M680X_OP_INDEXED
+                idx:
+                  base_reg: pc
+                  offset: 4096
+                  offset_addr: 0x2017
+                  offset_bits: 16
+                  flags: [ M680X_IDX_INDIRECT ]
+                size: 1
+                access: CS_AC_READ
+            flags: [M680X_FIRST_OP_IN_MNEM ]
+          regs_read: [ cc, pc ]
+          regs_write: [ cc, a ]
+      -
+        asm_text: "sta [, x++]"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: a
+                size: 1
+                access: CS_AC_READ
+              -
+                type: M680X_OP_INDEXED
+                idx:
+                  base_reg: x
+                  inc_dec: 2
+                  flags: [ M680X_IDX_INDIRECT, M680X_IDX_POST_INC_DEC ]
+                size: 1
+                access: CS_AC_WRITE
+            flags: [M680X_FIRST_OP_IN_MNEM ]
+          regs_read: [ cc, a, x ]
+          regs_write: [ cc, x ]
+      -
+        asm_text: "lda [$1000]"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: a
+                size: 1
+                access: CS_AC_WRITE
+              -
+                type: M680X_OP_EXTENDED
+                ext_address: 0x1000
+                ext_indirect: 1
+                size: 1
+                access: CS_AC_READ
+            flags: [M680X_FIRST_OP_IN_MNEM ]
+          regs_read: [ cc ]
+          regs_write: [ cc, a ]
+      -
+        asm_text: "cmps [4096, x]"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: s
+                size: 2
+                access: CS_AC_READ
+              -
+                type: M680X_OP_INDEXED
+                idx:
+                  base_reg: x
+                  offset: 4096
+                  offset_bits: 16
+                  flags: [ M680X_IDX_INDIRECT ]
+                size: 2
+                access: CS_AC_READ
+            flags: [M680X_FIRST_OP_IN_MNEM ]
+          regs_read: [ cc, s, x ]
+          regs_write: [ cc ]
+      -
+        asm_text: "rts"
+        details:
+          regs_read: [ s ]
+          regs_write: [ s, pc ]
+          groups: [ M680X_GRP_RET ]
+      -
+        asm_text: "lda 7, x"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: a
+                size: 1
+                access: CS_AC_WRITE
+              -
+                type: M680X_OP_INDEXED
+                idx:
+                  base_reg: x
+                  offset: 7
+                  offset_bits: 5
+                size: 1
+                access: CS_AC_READ
+            flags: [M680X_FIRST_OP_IN_MNEM ]
+          regs_read: [ cc, x ]
+          regs_write: [ cc, a ]
+      -
+        asm_text: "lda 7, y"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: a
+                size: 1
+                access: CS_AC_WRITE
+              -
+                type: M680X_OP_INDEXED
+                idx:
+                  base_reg: y
+                  offset: 7
+                  offset_bits: 5
+                size: 1
+                access: CS_AC_READ
+            flags: [M680X_FIRST_OP_IN_MNEM ]
+          regs_read: [ cc, y ]
+          regs_write: [ cc, a ]
+      -
+        asm_text: "lda 7, u"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: a
+                size: 1
+                access: CS_AC_WRITE
+              -
+                type: M680X_OP_INDEXED
+                idx:
+                  base_reg: u
+                  offset: 7
+                  offset_bits: 5
+                size: 1
+                access: CS_AC_READ
+            flags: [M680X_FIRST_OP_IN_MNEM ]
+          regs_read: [ cc, u ]
+          regs_write: [ cc, a ]
+      -
+        asm_text: "lda 7, s"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: a
+                size: 1
+                access: CS_AC_WRITE
+              -
+                type: M680X_OP_INDEXED
+                idx:
+                  base_reg: s
+                  offset: 7
+                  offset_bits: 5
+                size: 1
+                access: CS_AC_READ
+            flags: [M680X_FIRST_OP_IN_MNEM ]
+          regs_read: [ cc, s ]
+          regs_write: [ cc, a ]
+      -
+        asm_text: "lda 15, x"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: a
+                size: 1
+                access: CS_AC_WRITE
+              -
+                type: M680X_OP_INDEXED
+                idx:
+                  base_reg: x
+                  offset: 15
+                  offset_bits: 5
+                size: 1
+                access: CS_AC_READ
+            flags: [M680X_FIRST_OP_IN_MNEM ]
+          regs_read: [ cc, x ]
+          regs_write: [ cc, a ]
+      -
+        asm_text: "lda -16, x"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: a
+                size: 1
+                access: CS_AC_WRITE
+              -
+                type: M680X_OP_INDEXED
+                idx:
+                  base_reg: x
+                  offset: -16
+                  offset_bits: 5
+                size: 1
+                access: CS_AC_READ
+            flags: [M680X_FIRST_OP_IN_MNEM ]
+          regs_read: [ cc, x ]
+          regs_write: [ cc, a ]
+      -
+        asm_text: "lda , x+"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: a
+                size: 1
+                access: CS_AC_WRITE
+              -
+                type: M680X_OP_INDEXED
+                idx:
+                  base_reg: x
+                  inc_dec: 1
+                  flags: [ M680X_IDX_POST_INC_DEC ]
+                size: 1
+                access: CS_AC_READ
+            flags: [M680X_FIRST_OP_IN_MNEM ]
+          regs_read: [ cc, x ]
+          regs_write: [ cc, a, x ]
+      -
+        asm_text: "lda , x++"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: a
+                size: 1
+                access: CS_AC_WRITE
+              -
+                type: M680X_OP_INDEXED
+                idx:
+                  base_reg: x
+                  inc_dec: 2
+                  flags: [ M680X_IDX_POST_INC_DEC ]
+                size: 1
+                access: CS_AC_READ
+            flags: [M680X_FIRST_OP_IN_MNEM ]
+          regs_read: [ cc, x ]
+          regs_write: [ cc, a, x ]
+      -
+        asm_text: "lda , -x"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: a
+                size: 1
+                access: CS_AC_WRITE
+              -
+                type: M680X_OP_INDEXED
+                idx:
+                  base_reg: x
+                  inc_dec: -1
+                size: 1
+                access: CS_AC_READ
+            flags: [M680X_FIRST_OP_IN_MNEM ]
+          regs_read: [ cc, x ]
+          regs_write: [ cc, a, x ]
+      -
+        asm_text: "lda , --x"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: a
+                size: 1
+                access: CS_AC_WRITE
+              -
+                type: M680X_OP_INDEXED
+                idx:
+                  base_reg: x
+                  inc_dec: -2
+                size: 1
+                access: CS_AC_READ
+            flags: [M680X_FIRST_OP_IN_MNEM ]
+          regs_read: [ cc, x ]
+          regs_write: [ cc, a, x ]
+      -
+        asm_text: "lda , x"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: a
+                size: 1
+                access: CS_AC_WRITE
+              -
+                type: M680X_OP_INDEXED
+                idx:
+                  base_reg: x
+                size: 1
+                access: CS_AC_READ
+            flags: [M680X_FIRST_OP_IN_MNEM ]
+          regs_read: [ cc, x ]
+          regs_write: [ cc, a ]
+      -
+        asm_text: "lda b, x"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: a
+                size: 1
+                access: CS_AC_WRITE
+              -
+                type: M680X_OP_INDEXED
+                idx:
+                  base_reg: x
+                  offset_reg: b
+                size: 1
+                access: CS_AC_READ
+            flags: [M680X_FIRST_OP_IN_MNEM ]
+          regs_read: [ cc, x, b ]
+          regs_write: [ cc, a ]
+      -
+        asm_text: "lda a, x"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: a
+                size: 1
+                access: CS_AC_WRITE
+              -
+                type: M680X_OP_INDEXED
+                idx:
+                  base_reg: x
+                  offset_reg: a
+                size: 1
+                access: CS_AC_READ
+            flags: [M680X_FIRST_OP_IN_MNEM ]
+          regs_read: [ cc, x, a ]
+          regs_write: [ cc, a ]
+      -
+        asm_text: "lda 127, x"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: a
+                size: 1
+                access: CS_AC_WRITE
+              -
+                type: M680X_OP_INDEXED
+                idx:
+                  base_reg: x
+                  offset: 127
+                  offset_bits: 8
+                size: 1
+                access: CS_AC_READ
+            flags: [M680X_FIRST_OP_IN_MNEM ]
+          regs_read: [ cc, x ]
+          regs_write: [ cc, a ]
+      -
+        asm_text: "lda -128, x"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: a
+                size: 1
+                access: CS_AC_WRITE
+              -
+                type: M680X_OP_INDEXED
+                idx:
+                  base_reg: x
+                  offset: -128
+                  offset_bits: 8
+                size: 1
+                access: CS_AC_READ
+            flags: [M680X_FIRST_OP_IN_MNEM ]
+          regs_read: [ cc, x ]
+          regs_write: [ cc, a ]
+      -
+        asm_text: "lda 32767, x"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: a
+                size: 1
+                access: CS_AC_WRITE
+              -
+                type: M680X_OP_INDEXED
+                idx:
+                  base_reg: x
+                  offset: 32767
+                  offset_bits: 16
+                size: 1
+                access: CS_AC_READ
+            flags: [M680X_FIRST_OP_IN_MNEM ]
+          regs_read: [ cc, x ]
+          regs_write: [ cc, a ]
+      -
+        asm_text: "lda -32768, x"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: a
+                size: 1
+                access: CS_AC_WRITE
+              -
+                type: M680X_OP_INDEXED
+                idx:
+                  base_reg: x
+                  offset: -32768
+                  offset_bits: 16
+                size: 1
+                access: CS_AC_READ
+            flags: [M680X_FIRST_OP_IN_MNEM ]
+          regs_read: [ cc, x ]
+          regs_write: [ cc, a ]
+      -
+        asm_text: "lda d, x"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: a
+                size: 1
+                access: CS_AC_WRITE
+              -
+                type: M680X_OP_INDEXED
+                idx:
+                  base_reg: x
+                  offset_reg: d
+                size: 1
+                access: CS_AC_READ
+            flags: [M680X_FIRST_OP_IN_MNEM ]
+          regs_read: [ cc, x, d ]
+          regs_write: [ cc, a ]
+      -
+        asm_text: "lda $1050, pcr"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: a
+                size: 1
+                access: CS_AC_WRITE
+              -
+                type: M680X_OP_INDEXED
+                idx:
+                  base_reg: pc
+                  offset: 16
+                  offset_addr: 0x1050
+                  offset_bits: 8
+                size: 1
+                access: CS_AC_READ
+            flags: [M680X_FIRST_OP_IN_MNEM ]
+          regs_read: [ cc, pc ]
+          regs_write: [ cc, a ]
+      -
+        asm_text: "lda $2054, pcr"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: a
+                size: 1
+                access: CS_AC_WRITE
+              -
+                type: M680X_OP_INDEXED
+                idx:
+                  base_reg: pc
+                  offset: 4096
+                  offset_addr: 0x2054
+                  offset_bits: 16
+                size: 1
+                access: CS_AC_READ
+            flags: [M680X_FIRST_OP_IN_MNEM ]
+          regs_read: [ cc, pc ]
+          regs_write: [ cc, a ]
+      -
+        asm_text: "lda [, x++]"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: a
+                size: 1
+                access: CS_AC_WRITE
+              -
+                type: M680X_OP_INDEXED
+                idx:
+                  base_reg: x
+                  inc_dec: 2
+                  flags: [ M680X_IDX_INDIRECT, M680X_IDX_POST_INC_DEC ]
+                size: 1
+                access: CS_AC_READ
+            flags: [M680X_FIRST_OP_IN_MNEM ]
+          regs_read: [ cc, x ]
+          regs_write: [ cc, a, x ]
+      -
+        asm_text: "lda [, --x]"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: a
+                size: 1
+                access: CS_AC_WRITE
+              -
+                type: M680X_OP_INDEXED
+                idx:
+                  base_reg: x
+                  inc_dec: -2
+                  flags: [ M680X_IDX_INDIRECT ]
+                size: 1
+                access: CS_AC_READ
+            flags: [M680X_FIRST_OP_IN_MNEM ]
+          regs_read: [ cc, x ]
+          regs_write: [ cc, a, x ]
+      -
+        asm_text: "lda [, x]"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: a
+                size: 1
+                access: CS_AC_WRITE
+              -
+                type: M680X_OP_INDEXED
+                idx:
+                  base_reg: x
+                  flags: [ M680X_IDX_INDIRECT ]
+                size: 1
+                access: CS_AC_READ
+            flags: [M680X_FIRST_OP_IN_MNEM ]
+          regs_read: [ cc, x ]
+          regs_write: [ cc, a ]
+      -
+        asm_text: "lda [b, x]"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: a
+                size: 1
+                access: CS_AC_WRITE
+              -
+                type: M680X_OP_INDEXED
+                idx:
+                  base_reg: x
+                  offset_reg: b
+                  flags: [ M680X_IDX_INDIRECT ]
+                size: 1
+                access: CS_AC_READ
+            flags: [M680X_FIRST_OP_IN_MNEM ]
+          regs_read: [ cc, x, b ]
+          regs_write: [ cc, a ]
+      -
+        asm_text: "lda [a, x]"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: a
+                size: 1
+                access: CS_AC_WRITE
+              -
+                type: M680X_OP_INDEXED
+                idx:
+                  base_reg: x
+                  offset_reg: a
+                  flags: [ M680X_IDX_INDIRECT ]
+                size: 1
+                access: CS_AC_READ
+            flags: [M680X_FIRST_OP_IN_MNEM ]
+          regs_read: [ cc, x, a ]
+          regs_write: [ cc, a ]
+      -
+        asm_text: "lda [127, x]"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: a
+                size: 1
+                access: CS_AC_WRITE
+              -
+                type: M680X_OP_INDEXED
+                idx:
+                  base_reg: x
+                  offset: 127
+                  offset_bits: 8
+                  flags: [ M680X_IDX_INDIRECT ]
+                size: 1
+                access: CS_AC_READ
+            flags: [M680X_FIRST_OP_IN_MNEM ]
+          regs_read: [ cc, x ]
+          regs_write: [ cc, a ]
+      -
+        asm_text: "lda [-128, x]"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: a
+                size: 1
+                access: CS_AC_WRITE
+              -
+                type: M680X_OP_INDEXED
+                idx:
+                  base_reg: x
+                  offset: -128
+                  offset_bits: 8
+                  flags: [ M680X_IDX_INDIRECT ]
+                size: 1
+                access: CS_AC_READ
+            flags: [M680X_FIRST_OP_IN_MNEM ]
+          regs_read: [ cc, x ]
+          regs_write: [ cc, a ]
+      -
+        asm_text: "lda [32767, x]"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: a
+                size: 1
+                access: CS_AC_WRITE
+              -
+                type: M680X_OP_INDEXED
+                idx:
+                  base_reg: x
+                  offset: 32767
+                  offset_bits: 16
+                  flags: [ M680X_IDX_INDIRECT ]
+                size: 1
+                access: CS_AC_READ
+            flags: [M680X_FIRST_OP_IN_MNEM ]
+          regs_read: [ cc, x ]
+          regs_write: [ cc, a ]
+      -
+        asm_text: "lda [-32768, x]"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: a
+                size: 1
+                access: CS_AC_WRITE
+              -
+                type: M680X_OP_INDEXED
+                idx:
+                  base_reg: x
+                  offset: -32768
+                  offset_bits: 16
+                  flags: [ M680X_IDX_INDIRECT ]
+                size: 1
+                access: CS_AC_READ
+            flags: [M680X_FIRST_OP_IN_MNEM ]
+          regs_read: [ cc, x ]
+          regs_write: [ cc, a ]
+      -
+        asm_text: "lda [d, x]"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: a
+                size: 1
+                access: CS_AC_WRITE
+              -
+                type: M680X_OP_INDEXED
+                idx:
+                  base_reg: x
+                  offset_reg: d
+                  flags: [ M680X_IDX_INDIRECT ]
+                size: 1
+                access: CS_AC_READ
+            flags: [M680X_FIRST_OP_IN_MNEM ]
+          regs_read: [ cc, x, d ]
+          regs_write: [ cc, a ]
+      -
+        asm_text: "lda [$1071, pcr]"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: a
+                size: 1
+                access: CS_AC_WRITE
+              -
+                type: M680X_OP_INDEXED
+                idx:
+                  base_reg: pc
+                  offset: 16
+                  offset_addr: 0x1071
+                  offset_bits: 8
+                  flags: [ M680X_IDX_INDIRECT ]
+                size: 1
+                access: CS_AC_READ
+            flags: [M680X_FIRST_OP_IN_MNEM ]
+          regs_read: [ cc, pc ]
+          regs_write: [ cc, a ]
+      -
+        asm_text: "lda [$2075, pcr]"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: a
+                size: 1
+                access: CS_AC_WRITE
+              -
+                type: M680X_OP_INDEXED
+                idx:
+                  base_reg: pc
+                  offset: 4096
+                  offset_addr: 0x2075
+                  offset_bits: 16
+                  flags: [ M680X_IDX_INDIRECT ]
+                size: 1
+                access: CS_AC_READ
+            flags: [M680X_FIRST_OP_IN_MNEM ]
+          regs_read: [ cc, pc ]
+          regs_write: [ cc, a ]
+      -
+        asm_text: "lda [$1000]"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: a
+                size: 1
+                access: CS_AC_WRITE
+              -
+                type: M680X_OP_EXTENDED
+                ext_address: 0x1000
+                ext_indirect: 1
+                size: 1
+                access: CS_AC_READ
+            flags: [M680X_FIRST_OP_IN_MNEM ]
+          regs_read: [ cc ]
+          regs_write: [ cc, a ]
+  -
+    input:
+      bytes: [ 0x02, 0x03, 0x12, 0x7f, 0x10, 0x00, 0x13, 0x99, 0x08, 0x00, 0x14, 0x7f, 0x02, 0x15, 0x7f, 0x01, 0x1e, 0x7f, 0x20, 0x00, 0x8f, 0xcf, 0x18, 0x08, 0x18, 0x30, 0x18, 0x3c, 0x18, 0x67, 0x18, 0x8c, 0x10, 0x00, 0x18, 0x8f, 0x18, 0xce, 0x10, 0x00, 0x18, 0xff, 0x10, 0x00, 0x1a, 0xa3, 0x7f, 0x1a, 0xac, 0x1a, 0xee, 0x7f, 0x1a, 0xef, 0x7f, 0xcd, 0xac, 0x7f  ]
+      arch: "m680x"
+      options: [ CS_OPT_DETAIL, CS_MODE_M680X_6811 ]
+      address: 0x1000
+    expected:
+      insns:
+      -
+        asm_text: "idiv"
+        details:
+          regs_read: [ cc, d, x ]
+          regs_write: [ cc, d, x ]
+      -
+        asm_text: "fdiv"
+        details:
+          regs_read: [ cc, d, x ]
+          regs_write: [ cc, d, x ]
+      -
+        asm_text: "brset $7f, #16, $1006"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_DIRECT
+                direct_addr: 0x007f
+                direct_addr_set: true
+                size: 1
+                access: CS_AC_READ
+              -
+                type: M680X_OP_IMMEDIATE
+                imm: 16
+                size: 1
+                access: CS_AC_READ
+              -
+                type: M680X_OP_RELATIVE
+                rel_address: 0x1006
+                rel_offset: 0
+          regs_read: [ cc ]
+          groups: [  M680X_GRP_BRAREL, M680X_GRP_JUMP ]
+      -
+        asm_text: "brclr $99, #8, $100a"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_DIRECT
+                direct_addr: 0x0099
+                direct_addr_set: true
+                size: 1
+                access: CS_AC_READ
+              -
+                type: M680X_OP_IMMEDIATE
+                imm: 8
+                size: 1
+                access: CS_AC_READ
+              -
+                type: M680X_OP_RELATIVE
+                rel_address: 0x100a
+                rel_offset: 0
+          regs_read: [ cc ]
+          groups: [  M680X_GRP_BRAREL, M680X_GRP_JUMP ]
+      -
+        asm_text: "bset $7f, #2"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_DIRECT
+                direct_addr: 0x007f
+                direct_addr_set: true
+                size: 1
+                access: CS_AC_READ_WRITE
+              -
+                type: M680X_OP_IMMEDIATE
+                imm: 2
+                size: 1
+                access: CS_AC_READ
+          regs_read: [ cc ]
+          regs_write: [ cc ]
+      -
+        asm_text: "bclr $7f, #1"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_DIRECT
+                direct_addr: 0x007f
+                direct_addr_set: true
+                size: 1
+                access: CS_AC_READ_WRITE
+              -
+                type: M680X_OP_IMMEDIATE
+                imm: 1
+                size: 1
+                access: CS_AC_READ
+          regs_read: [ cc ]
+          regs_write: [ cc ]
+      -
+        asm_text: "brset 127, x; #32; $1014"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_INDEXED
+                idx:
+                  base_reg: x
+                  offset: 127
+                  offset_bits: 8
+                size: 1
+                access: CS_AC_READ
+              -
+                type: M680X_OP_IMMEDIATE
+                imm: 32
+                size: 1
+                access: CS_AC_READ
+              -
+                type: M680X_OP_RELATIVE
+                rel_address: 0x1014
+                rel_offset: 0
+          regs_read: [ cc, x ]
+          groups: [  M680X_GRP_BRAREL, M680X_GRP_JUMP ]
+      -
+        asm_text: "xgdx"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: d
+                size: 2
+                access: CS_AC_READ_WRITE
+              -
+                type: M680X_OP_REGISTER
+                reg: x
+                size: 2
+                access: CS_AC_READ_WRITE
+            flags: [M680X_FIRST_OP_IN_MNEM, M680X_SECOND_OP_IN_MNEM ]
+          regs_read: [ d, x ]
+          regs_write: [ d, x ]
+      -
+        asm_text: "stop"
+      -
+        asm_text: "iny"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: y
+                size: 2
+                access: CS_AC_READ_WRITE
+            flags: [M680X_FIRST_OP_IN_MNEM ]
+          regs_read: [ cc, y ]
+          regs_write: [ cc, y ]
+      -
+        asm_text: "tsy"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: s
+                size: 2
+                access: CS_AC_READ
+              -
+                type: M680X_OP_REGISTER
+                reg: y
+                size: 2
+                access: CS_AC_WRITE
+            flags: [M680X_FIRST_OP_IN_MNEM, M680X_SECOND_OP_IN_MNEM ]
+          regs_read: [ s ]
+          regs_write: [ y ]
+      -
+        asm_text: "pshy"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: y
+                size: 2
+                access: CS_AC_READ
+            flags: [M680X_FIRST_OP_IN_MNEM ]
+          regs_read: [ y, s ]
+          regs_write: [ s ]
+      -
+        asm_text: "asr 24, y"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_INDEXED
+                idx:
+                  base_reg: y
+                  offset: 24
+                  offset_bits: 8
+                size: 1
+                access: CS_AC_READ_WRITE
+          regs_read: [ cc, y ]
+          regs_write: [ cc ]
+      -
+        asm_text: "cpx #4096"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: x
+                size: 2
+                access: CS_AC_READ
+              -
+                type: M680X_OP_IMMEDIATE
+                imm: 4096
+                size: 2
+                access: CS_AC_READ
+            flags: [M680X_FIRST_OP_IN_MNEM ]
+          regs_read: [ cc, x ]
+          regs_write: [ cc ]
+      -
+        asm_text: "xgdy"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: d
+                size: 2
+                access: CS_AC_READ_WRITE
+              -
+                type: M680X_OP_REGISTER
+                reg: y
+                size: 2
+                access: CS_AC_READ_WRITE
+            flags: [M680X_FIRST_OP_IN_MNEM, M680X_SECOND_OP_IN_MNEM ]
+          regs_read: [ d, y ]
+          regs_write: [ d, y ]
+      -
+        asm_text: "ldy #4096"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: y
+                size: 2
+                access: CS_AC_WRITE
+              -
+                type: M680X_OP_IMMEDIATE
+                imm: 4096
+                size: 2
+                access: CS_AC_READ
+            flags: [M680X_FIRST_OP_IN_MNEM ]
+          regs_read: [ cc ]
+          regs_write: [ cc, y ]
+      -
+        asm_text: "sty $1000"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: y
+                size: 2
+                access: CS_AC_READ
+              -
+                type: M680X_OP_EXTENDED
+                ext_address: 0x1000
+                ext_indirect: -1
+                size: 2
+                access: CS_AC_WRITE
+            flags: [M680X_FIRST_OP_IN_MNEM ]
+          regs_read: [ cc, y ]
+          regs_write: [ cc ]
+      -
+        asm_text: "cpd 127, x"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: d
+                size: 2
+                access: CS_AC_READ
+              -
+                type: M680X_OP_INDEXED
+                idx:
+                  base_reg: x
+                  offset: 127
+                  offset_bits: 8
+                size: 2
+                access: CS_AC_READ
+            flags: [M680X_FIRST_OP_IN_MNEM ]
+          regs_read: [ cc, d, x ]
+          regs_write: [ cc ]
+      -
+        asm_text: "cpy 26, x"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: y
+                size: 2
+                access: CS_AC_READ
+              -
+                type: M680X_OP_INDEXED
+                idx:
+                  base_reg: x
+                  offset: 26
+                  offset_bits: 8
+                size: 2
+                access: CS_AC_READ
+            flags: [M680X_FIRST_OP_IN_MNEM ]
+          regs_read: [ cc, y, x ]
+          regs_write: [ cc ]
+      -
+        asm_text: "ldx 127, x"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: x
+                size: 2
+                access: CS_AC_WRITE
+              -
+                type: M680X_OP_INDEXED
+                idx:
+                  base_reg: x
+                  offset: 127
+                  offset_bits: 8
+                size: 2
+                access: CS_AC_READ
+            flags: [M680X_FIRST_OP_IN_MNEM ]
+          regs_read: [ cc, x ]
+          regs_write: [ cc, x ]
+      -
+        asm_text: "sty 127, x"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: y
+                size: 2
+                access: CS_AC_READ
+              -
+                type: M680X_OP_INDEXED
+                idx:
+                  base_reg: x
+                  offset: 127
+                  offset_bits: 8
+                size: 2
+                access: CS_AC_WRITE
+            flags: [M680X_FIRST_OP_IN_MNEM ]
+          regs_read: [ cc, y, x ]
+          regs_write: [ cc ]
+      -
+        asm_text: "cpx 127, y"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: x
+                size: 2
+                access: CS_AC_READ
+              -
+                type: M680X_OP_INDEXED
+                idx:
+                  base_reg: y
+                  offset: 127
+                  offset_bits: 8
+                size: 2
+                access: CS_AC_READ
+            flags: [M680X_FIRST_OP_IN_MNEM ]
+          regs_read: [ cc, x, y ]
+          regs_write: [ cc ]
+  -
+    input:
+      bytes: [ 0x00, 0x04, 0x01, 0x00, 0x0c, 0x00, 0x80, 0x0e, 0x00, 0x80, 0x00, 0x11, 0x1e, 0x10, 0x00, 0x80, 0x00, 0x3b, 0x4a, 0x10, 0x00, 0x04, 0x4b, 0x01, 0x04, 0x4f, 0x7f, 0x80, 0x00, 0x8f, 0x10, 0x00, 0xb7, 0x52, 0xb7, 0xb1, 0xa6, 0x67, 0xa6, 0xfe, 0xa6, 0xf7, 0x18, 0x02, 0xe2, 0x30, 0x39, 0xe2, 0x10, 0x00, 0x18, 0x0c, 0x30, 0x39, 0x10, 0x00, 0x18, 0x11, 0x18, 0x12, 0x10, 0x00, 0x18, 0x19, 0x00, 0x18, 0x1e, 0x00, 0x18, 0x3e, 0x18, 0x3f, 0x00  ]
+      arch: "m680x"
+      options: [ CS_OPT_DETAIL, CS_MODE_M680X_CPU12 ]
+      address: 0x1000
+    expected:
+      insns:
+      -
+        asm_text: "bgnd"
+      -
+        asm_text: "dbeq b, $1004"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: b
+                size: 1
+                access: CS_AC_READ_WRITE
+              -
+                type: M680X_OP_RELATIVE
+                rel_address: 0x1004
+                rel_offset: 0
+          regs_read: [ b ]
+          regs_write: [ b ]
+          groups: [  M680X_GRP_BRAREL, M680X_GRP_JUMP ]
+      -
+        asm_text: "bset 0, x; #-128"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_INDEXED
+                idx:
+                  base_reg: x
+                  offset: 0
+                  offset_bits: 5
+                size: 1
+                access: CS_AC_READ_WRITE
+              -
+                type: M680X_OP_IMMEDIATE
+                imm: -128
+                size: 1
+                access: CS_AC_READ
+          regs_read: [ cc, x ]
+          regs_write: [ cc ]
+      -
+        asm_text: "brset 0, x; #-128; $100b"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_INDEXED
+                idx:
+                  base_reg: x
+                  offset: 0
+                  offset_bits: 5
+                size: 1
+                access: CS_AC_READ
+              -
+                type: M680X_OP_IMMEDIATE
+                imm: -128
+                size: 1
+                access: CS_AC_READ
+              -
+                type: M680X_OP_RELATIVE
+                rel_address: 0x100b
+                rel_offset: 0
+          regs_read: [ cc, x ]
+          groups: [  M680X_GRP_BRAREL, M680X_GRP_JUMP ]
+      -
+        asm_text: "ediv"
+        details:
+          regs_read: [ cc, d, y, x ]
+          regs_write: [ cc, d, y ]
+      -
+        asm_text: "brset $1000, #-128, $1011"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_EXTENDED
+                ext_address: 0x1000
+                ext_indirect: -1
+                size: 1
+                access: CS_AC_READ
+              -
+                type: M680X_OP_IMMEDIATE
+                imm: -128
+                size: 1
+                access: CS_AC_READ
+              -
+                type: M680X_OP_RELATIVE
+                rel_address: 0x1011
+                rel_offset: 0
+          regs_read: [ cc ]
+          groups: [  M680X_GRP_BRAREL, M680X_GRP_JUMP ]
+      -
+        asm_text: "pshd"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: d
+                size: 2
+                access: CS_AC_READ
+            flags: [M680X_FIRST_OP_IN_MNEM ]
+          regs_read: [ d, s ]
+          regs_write: [ s ]
+      -
+        asm_text: "call $1000, 4"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_EXTENDED
+                ext_address: 0x1000
+                ext_indirect: -1
+                size: 1
+              -
+                type: M680X_OP_CONSTANT
+                const_val: 4
+          regs_read: [ s ]
+          regs_write: [ s ]
+          groups: [  M680X_GRP_CALL ]
+      -
+        asm_text: "call 1, x; 4"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_INDEXED
+                idx:
+                  base_reg: x
+                  offset: 1
+                  offset_bits: 5
+                size: 1
+              -
+                type: M680X_OP_CONSTANT
+                const_val: 4
+          regs_read: [ x, s ]
+          regs_write: [ s ]
+          groups: [  M680X_GRP_CALL ]
+      -
+        asm_text: "brclr $7f, #-128, $101d"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_DIRECT
+                direct_addr: 0x007f
+                direct_addr_set: true
+                size: 1
+                access: CS_AC_READ
+              -
+                type: M680X_OP_IMMEDIATE
+                imm: -128
+                size: 1
+                access: CS_AC_READ
+              -
+                type: M680X_OP_RELATIVE
+                rel_address: 0x101d
+                rel_offset: 0
+          regs_read: [ cc ]
+          groups: [  M680X_GRP_BRAREL, M680X_GRP_JUMP ]
+      -
+        asm_text: "cps #4096"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: s
+                size: 2
+                access: CS_AC_READ
+              -
+                type: M680X_OP_IMMEDIATE
+                imm: 4096
+                size: 2
+                access: CS_AC_READ
+            flags: [M680X_FIRST_OP_IN_MNEM ]
+          regs_read: [ cc, s ]
+          regs_write: [ cc ]
+      -
+        asm_text: "tfr x, cc"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: x
+                size: 2
+                access: CS_AC_READ
+              -
+                type: M680X_OP_REGISTER
+                reg: cc
+                size: 1
+                access: CS_AC_WRITE
+          regs_read: [ x ]
+          regs_write: [ cc ]
+      -
+        asm_text: "exg tmp3, b"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: tmp3
+                size: 2
+                access: CS_AC_READ_WRITE
+              -
+                type: M680X_OP_REGISTER
+                reg: b
+                size: 1
+                access: CS_AC_READ_WRITE
+          regs_read: [ tmp3, b ]
+          regs_write: [ tmp3, b ]
+      -
+        asm_text: "ldaa 8, +y"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: a
+                size: 1
+                access: CS_AC_WRITE
+              -
+                type: M680X_OP_INDEXED
+                idx:
+                  base_reg: y
+                  inc_dec: 8
+                size: 1
+                access: CS_AC_READ
+            flags: [M680X_FIRST_OP_IN_MNEM ]
+          regs_read: [ cc, y ]
+          regs_write: [ cc, a, y ]
+      -
+        asm_text: "ldaa d, pc"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: a
+                size: 1
+                access: CS_AC_WRITE
+              -
+                type: M680X_OP_INDEXED
+                idx:
+                  base_reg: pc
+                  offset_reg: d
+                size: 1
+                access: CS_AC_READ
+            flags: [M680X_FIRST_OP_IN_MNEM ]
+          regs_read: [ cc, pc, d ]
+          regs_write: [ cc, a ]
+      -
+        asm_text: "ldaa [d, s]"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: a
+                size: 1
+                access: CS_AC_WRITE
+              -
+                type: M680X_OP_INDEXED
+                idx:
+                  base_reg: s
+                  offset_reg: d
+                  flags: [ M680X_IDX_INDIRECT ]
+                size: 1
+                access: CS_AC_READ
+            flags: [M680X_FIRST_OP_IN_MNEM ]
+          regs_read: [ cc, s, d ]
+          regs_write: [ cc, a ]
+      -
+        asm_text: "movw 12345, x; 4096, x"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_INDEXED
+                idx:
+                  base_reg: x
+                  offset: 12345
+                  offset_bits: 16
+                size: 2
+                access: CS_AC_READ
+              -
+                type: M680X_OP_INDEXED
+                idx:
+                  base_reg: x
+                  offset: 4096
+                  offset_bits: 16
+                size: 2
+                access: CS_AC_WRITE
+          regs_read: [ x ]
+      -
+        asm_text: "movb $3039, $1000"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_EXTENDED
+                ext_address: 0x3039
+                ext_indirect: -1
+                size: 1
+                access: CS_AC_READ
+              -
+                type: M680X_OP_EXTENDED
+                ext_address: 0x1000
+                ext_indirect: -1
+                size: 1
+                access: CS_AC_WRITE
+      -
+        asm_text: "fdiv"
+        details:
+          regs_read: [ cc, d, x ]
+          regs_write: [ cc, d, x ]
+      -
+        asm_text: "emacs $1000"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_EXTENDED
+                ext_address: 0x1000
+                ext_indirect: -1
+                size: 4
+                access: CS_AC_READ_WRITE
+          regs_read: [ cc, x, y ]
+          regs_write: [ cc, x ]
+      -
+        asm_text: "mina 0, x"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: a
+                size: 1
+                access: CS_AC_READ_WRITE
+              -
+                type: M680X_OP_INDEXED
+                idx:
+                  base_reg: x
+                  offset: 0
+                  offset_bits: 5
+                size: 1
+                access: CS_AC_READ
+            flags: [M680X_FIRST_OP_IN_MNEM ]
+          regs_read: [ cc, a, x ]
+          regs_write: [ cc, a ]
+      -
+        asm_text: "emaxm 0, x"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_INDEXED
+                idx:
+                  base_reg: x
+                  offset: 0
+                  offset_bits: 5
+                size: 1
+                access: CS_AC_READ_WRITE
+          regs_read: [ cc, x, d ]
+          regs_write: [ cc ]
+      -
+        asm_text: "stop"
+      -
+        asm_text: "etbl 0, x"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_INDEXED
+                idx:
+                  base_reg: x
+                  offset: 0
+                  offset_bits: 5
+                size: 1
+                access: CS_AC_READ
+          regs_read: [ cc, x, b ]
+          regs_write: [ cc, a, b ]
+  -
+    input:
+      bytes: [ 0x32, 0x10, 0x00, 0x9e, 0xae, 0x9e, 0xce, 0x7f, 0x9e, 0xbe, 0x10, 0x00, 0x9e, 0xfe, 0x7f, 0x3e, 0x10, 0x00, 0x9e, 0xf3, 0x7f, 0x96, 0x10, 0x00, 0x9e, 0xff, 0x7f, 0x82  ]
+      arch: "m680x"
+      options: [ CS_OPT_DETAIL, CS_MODE_M680X_HCS08 ]
+      address: 0x1000
+    expected:
+      insns:
+      -
+        asm_text: "ldhx $1000"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: hx
+                size: 2
+                access: CS_AC_WRITE
+              -
+                type: M680X_OP_EXTENDED
+                ext_address: 0x1000
+                ext_indirect: -1
+                size: 2
+                access: CS_AC_READ
+            flags: [M680X_FIRST_OP_IN_MNEM ]
+          regs_read: [ cc ]
+          regs_write: [ cc, hx ]
+      -
+        asm_text: "ldhx , x"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: hx
+                size: 2
+                access: CS_AC_WRITE
+              -
+                type: M680X_OP_INDEXED
+                idx:
+                  base_reg: x
+                size: 2
+                access: CS_AC_READ
+            flags: [M680X_FIRST_OP_IN_MNEM ]
+          regs_read: [ cc, x, h ]
+          regs_write: [ cc, hx ]
+      -
+        asm_text: "ldhx 127, x"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: hx
+                size: 2
+                access: CS_AC_WRITE
+              -
+                type: M680X_OP_INDEXED
+                idx:
+                  base_reg: x
+                  offset: 127
+                  offset_bits: 8
+                size: 2
+                access: CS_AC_READ
+            flags: [M680X_FIRST_OP_IN_MNEM ]
+          regs_read: [ cc, x, h ]
+          regs_write: [ cc, hx ]
+      -
+        asm_text: "ldhx 4096, x"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: hx
+                size: 2
+                access: CS_AC_WRITE
+              -
+                type: M680X_OP_INDEXED
+                idx:
+                  base_reg: x
+                  offset: 4096
+                  offset_bits: 16
+                size: 2
+                access: CS_AC_READ
+            flags: [M680X_FIRST_OP_IN_MNEM ]
+          regs_read: [ cc, x, h ]
+          regs_write: [ cc, hx ]
+      -
+        asm_text: "ldhx 127, s"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: hx
+                size: 2
+                access: CS_AC_WRITE
+              -
+                type: M680X_OP_INDEXED
+                idx:
+                  base_reg: s
+                  offset: 127
+                  offset_bits: 8
+                size: 2
+                access: CS_AC_READ
+            flags: [M680X_FIRST_OP_IN_MNEM ]
+          regs_read: [ cc, s ]
+          regs_write: [ cc, hx ]
+      -
+        asm_text: "cphx $1000"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: hx
+                size: 2
+                access: CS_AC_READ
+              -
+                type: M680X_OP_EXTENDED
+                ext_address: 0x1000
+                ext_indirect: -1
+                size: 2
+                access: CS_AC_READ
+            flags: [M680X_FIRST_OP_IN_MNEM ]
+          regs_read: [ cc, hx ]
+          regs_write: [ cc ]
+      -
+        asm_text: "cphx 127, s"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: hx
+                size: 2
+                access: CS_AC_READ
+              -
+                type: M680X_OP_INDEXED
+                idx:
+                  base_reg: s
+                  offset: 127
+                  offset_bits: 8
+                size: 2
+                access: CS_AC_READ
+            flags: [M680X_FIRST_OP_IN_MNEM ]
+          regs_read: [ cc, hx, s ]
+          regs_write: [ cc ]
+      -
+        asm_text: "sthx $1000"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: hx
+                size: 2
+                access: CS_AC_READ
+              -
+                type: M680X_OP_EXTENDED
+                ext_address: 0x1000
+                ext_indirect: -1
+                size: 2
+                access: CS_AC_WRITE
+            flags: [M680X_FIRST_OP_IN_MNEM ]
+          regs_read: [ cc, hx ]
+          regs_write: [ cc ]
+      -
+        asm_text: "sthx 127, s"
+        details:
+          m680x:
+            operands:
+              -
+                type: M680X_OP_REGISTER
+                reg: hx
+                size: 2
+                access: CS_AC_READ
+              -
+                type: M680X_OP_INDEXED
+                idx:
+                  base_reg: s
+                  offset: 127
+                  offset_bits: 8
+                size: 2
+                access: CS_AC_WRITE
+            flags: [M680X_FIRST_OP_IN_MNEM ]
+          regs_read: [ cc, hx, s ]
+          regs_write: [ cc ]
+      -
+        asm_text: "bgnd"
+
diff --git a/tests/details/m68k.yaml b/tests/details/m68k.yaml
new file mode 100644
index 000000000..cd9a78656
--- /dev/null
+++ b/tests/details/m68k.yaml
@@ -0,0 +1,212 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xf0, 0x10, 0xf0, 0x00, 0x48, 0xaf, 0xff, 0xff, 0x7f, 0xff, 0x11, 0xb0, 0x01, 0x37, 0x7f, 0xff, 0xff, 0xff, 0x12, 0x34, 0x56, 0x78, 0x01, 0x33, 0x10, 0x10, 0x10, 0x10, 0x32, 0x32, 0x32, 0x32, 0x4c, 0x00, 0x54, 0x04, 0x48, 0xe7, 0xe0, 0x30, 0x4c, 0xdf, 0x0c, 0x07, 0xd4, 0x40, 0x87, 0x5a, 0x4e, 0x71, 0x02, 0xb4, 0xc0, 0xde, 0xc0, 0xde, 0x5c, 0x00, 0x1d, 0x80, 0x71, 0x12, 0x01, 0x23, 0xf2, 0x3c, 0x44, 0x22, 0x40, 0x49, 0x0e, 0x56, 0x54, 0xc5, 0xf2, 0x3c, 0x44, 0x00, 0x44, 0x7a, 0x00, 0x00, 0xf2, 0x00, 0x0a, 0x28, 0x4e, 0xb9, 0x00, 0x00, 0x00, 0x12, 0x4e, 0x75  ]
+      arch: "m68k"
+      options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040 ]
+      address: 0x1000
+    expected:
+      insns:
+      -
+        asm_text: "fmovem #$0, (a0)"
+        details:
+          regs_read: [ a0 ]
+          m68k:
+            operands:
+              -
+                type: M68K_OP_REG_BITS
+                register_bits: 0x0
+              -
+                type: M68K_OP_MEM
+                address_mode: M68K_AM_REGI_ADDR
+      -
+        asm_text: "movem.w d0-d7/a0-a7, $7fff(a7)"
+        details:
+          regs_read: [ d0, d1, d2, d3, d4, d5, d6, d7, a0, a1, a2, a3, a4, a5, a6, a7 ]
+          m68k:
+            operands:
+              -
+                type: M68K_OP_REG_BITS
+                register_bits: 0xffff
+              -
+                type: M68K_OP_MEM
+                mem:
+                  base_reg: a7
+                  disp: 0x7fff
+                address_mode: M68K_AM_REGI_ADDR_DISP
+      -
+        asm_text: "move.b ([$7fffffff, a0], d0.w, $12345678), ([$10101010, a0, d0.w], $32323232)"
+        details:
+          regs_read: [ d0, a0 ]
+          m68k:
+            operands:
+              -
+                type: M68K_OP_MEM
+                mem:
+                  base_reg: a0
+                  index_reg: d0
+                  index_size: -1
+                address_mode: M68K_AM_MEMI_POST_INDEX
+              -
+                type: M68K_OP_MEM
+                mem:
+                  base_reg: a0
+                  index_reg: d0
+                  index_size: -1
+                address_mode: M68K_AM_MEMI_PRE_INDEX
+      -
+        asm_text: "mulu.l d0, d4:d5"
+        details:
+          regs_read: [ d0 ]
+          regs_write: [ d4, d5 ]
+          m68k:
+            operands:
+              -
+                type: M68K_OP_REG
+                reg: d0
+              -
+                type: M68K_OP_REG_PAIR
+                reg_pair_0: d4
+                reg_pair_1: d5
+      -
+        asm_text: "movem.l d0-d2/a2-a3, -(a7)"
+        details:
+          regs_read: [ d0, d1, d2, a2, a3 ]
+          regs_write: [ a7 ]
+          m68k:
+            operands:
+              -
+                type: M68K_OP_REG_BITS
+                register_bits: 0xc07
+              -
+                type: M68K_OP_MEM
+                address_mode: M68K_AM_REGI_ADDR_PRE_DEC
+      -
+        asm_text: "movem.l (a7)+, d0-d2/a2-a3"
+        details:
+          regs_write: [ a7, d0, d1, d2, a2, a3 ]
+          m68k:
+            operands:
+              -
+                type: M68K_OP_MEM
+                address_mode: M68K_AM_REGI_ADDR_POST_INC
+              -
+                type: M68K_OP_REG_BITS
+                register_bits: 0xc07
+      -
+        asm_text: "add.w d0, d2"
+        details:
+          regs_read: [ d0 ]
+          regs_write: [ d2 ]
+          m68k:
+            operands:
+              -
+                type: M68K_OP_REG
+                reg: d0
+              -
+                type: M68K_OP_REG
+                reg: d2
+      -
+        asm_text: "or.w d3, (a2)+"
+        details:
+          regs_read: [ d3 ]
+          regs_write: [ a2 ]
+          m68k:
+            operands:
+              -
+                type: M68K_OP_REG
+                reg: d3
+              -
+                type: M68K_OP_MEM
+                address_mode: M68K_AM_REGI_ADDR_POST_INC
+      -
+        asm_text: "nop"
+      -
+        asm_text: "andi.l #$c0dec0de, (a4, d5.l * 4)"
+        details:
+          regs_read: [ d5, a4 ]
+          m68k:
+            operands:
+              -
+                type: M68K_OP_IMM
+                imm: 0xc0dec0de
+              -
+                type: M68K_OP_MEM
+                mem:
+                  base_reg: a4
+                  index_reg: d5
+                  index_size: 1
+                  scale: 4
+                address_mode: M68K_AM_AREGI_INDEX_BASE_DISP
+      -
+        asm_text: "move.b d0, ([a6, d7.w], $123)"
+        details:
+          regs_read: [ d0, d7, a6 ]
+          m68k:
+            operands:
+              -
+                type: M68K_OP_REG
+                reg: d0
+              -
+                type: M68K_OP_MEM
+                mem:
+                  base_reg: a6
+                  index_reg: d7
+                  index_size: -1
+                address_mode: M68K_AM_MEMI_PRE_INDEX
+      -
+        asm_text: "fadd.s #3.141500, fp0"
+        details:
+          regs_write: [ fp0 ]
+          m68k:
+            operands:
+              -
+                type: M68K_OP_FP_SINGLE
+                simm: 3.141500
+              -
+                type: M68K_OP_REG
+                reg: fp0
+      -
+        asm_text: "scc.b d5"
+        details:
+          regs_write: [ d5 ]
+          m68k:
+            operands:
+              -
+                type: M68K_OP_REG
+                reg: d5
+      -
+        asm_text: "fmove.s #1000.000000, fp0"
+        details:
+          regs_write: [ fp0 ]
+          m68k:
+            operands:
+              -
+                type: M68K_OP_FP_SINGLE
+                simm: 1000.000000
+              -
+                type: M68K_OP_REG
+                reg: fp0
+      -
+        asm_text: "fsub fp2, fp4"
+        details:
+          regs_read: [ fp2 ]
+          regs_write: [ fp4 ]
+          m68k:
+            operands:
+              -
+                type: M68K_OP_REG
+                reg: fp2
+              -
+                type: M68K_OP_REG
+                reg: fp4
+      -
+        asm_text: "jsr $12.l"
+        details:
+          m68k:
+            operands:
+              -
+                type: M68K_OP_MEM
+                address_mode: M68K_AM_ABSOLUTE_DATA_LONG
+      -
+        asm_text: "rts"
diff --git a/tests/details/mips.yaml b/tests/details/mips.yaml
new file mode 100644
index 000000000..1695728f8
--- /dev/null
+++ b/tests/details/mips.yaml
@@ -0,0 +1,220 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x0c, 0x10, 0x00, 0x97, 0x00, 0x00, 0x00, 0x00, 0x24, 0x02, 0x00, 0x0c, 0x8f, 0xa2, 0x00, 0x00, 0x34, 0x21, 0x34, 0x56  ]
+      arch: "mips"
+      options: [ CS_OPT_DETAIL, CS_MODE_MIPS32, CS_MODE_BIG_ENDIAN ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "jal 0x40025c"
+        details:
+          mips:
+            operands:
+              -
+                type: MIPS_OP_IMM
+                imm: 0x40025c
+      -
+        asm_text: "nop"
+      -
+        asm_text: "addiu $v0, $zero, 0xc"
+        details:
+          mips:
+            operands:
+              -
+                type: MIPS_OP_REG
+                reg: v0
+              -
+                type: MIPS_OP_REG
+                reg: zero
+              -
+                type: MIPS_OP_IMM
+                imm: 0xc
+      -
+        asm_text: "lw $v0, ($sp)"
+        details:
+          mips:
+            operands:
+              -
+                type: MIPS_OP_REG
+                reg: v0
+              -
+                type: MIPS_OP_MEM
+                mem_base: sp
+      -
+        asm_text: "ori $at, $at, 0x3456"
+        details:
+          mips:
+            operands:
+              -
+                type: MIPS_OP_REG
+                reg: at
+              -
+                type: MIPS_OP_REG
+                reg: at
+              -
+                type: MIPS_OP_IMM
+                imm: 0x3456
+  -
+    input:
+      bytes: [ 0x56, 0x34, 0x21, 0x34, 0xc2, 0x17, 0x01, 0x00  ]
+      arch: "mips"
+      options: [ CS_OPT_DETAIL, CS_MODE_MIPS64, CS_MODE_LITTLE_ENDIAN ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "ori $at, $at, 0x3456"
+        details:
+          mips:
+            operands:
+              -
+                type: MIPS_OP_REG
+                reg: at
+              -
+                type: MIPS_OP_REG
+                reg: at
+              -
+                type: MIPS_OP_IMM
+                imm: 0x3456
+      -
+        asm_text: "srl $v0, $at, 0x1f"
+        details:
+          mips:
+            operands:
+              -
+                type: MIPS_OP_REG
+                reg: v0
+              -
+                type: MIPS_OP_REG
+                reg: at
+              -
+                type: MIPS_OP_IMM
+                imm: 0x1f
+  -
+    input:
+      bytes: [ 0x00, 0x07, 0x00, 0x07, 0x00, 0x11, 0x93, 0x7c, 0x01, 0x8c, 0x8b, 0x7c, 0x00, 0xc7, 0x48, 0xd0  ]
+      arch: "mips"
+      options: [ CS_OPT_DETAIL, CS_MODE_MIPS32R6, CS_MODE_MICRO, CS_MODE_BIG_ENDIAN ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "break 7, 0"
+        details:
+          mips:
+            operands:
+              -
+                type: MIPS_OP_IMM
+                imm: 0x7
+              -
+                type: MIPS_OP_IMM
+                imm: 0x0
+      -
+        asm_text: "wait 0x11"
+        details:
+          mips:
+            operands:
+              -
+                type: MIPS_OP_IMM
+                imm: 0x11
+      -
+        asm_text: "syscall 0x18c"
+        details:
+          mips:
+            operands:
+              -
+                type: MIPS_OP_IMM
+                imm: 0x18c
+      -
+        asm_text: "rotrv $t1, $a2, $a3"
+        details:
+          mips:
+            operands:
+              -
+                type: MIPS_OP_REG
+                reg: t1
+              -
+                type: MIPS_OP_REG
+                reg: a2
+              -
+                type: MIPS_OP_REG
+                reg: a3
+  -
+    input:
+      bytes: [ 0xec, 0x80, 0x00, 0x19, 0x7c, 0x43, 0x22, 0xa0  ]
+      arch: "mips"
+      options: [ CS_OPT_DETAIL, CS_MODE_MIPS32R6, CS_MODE_BIG_ENDIAN ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "addiupc $a0, 0x64"
+        details:
+          mips:
+            operands:
+              -
+                type: MIPS_OP_REG
+                reg: a0
+              -
+                type: MIPS_OP_IMM
+                imm: 0x64
+      -
+        asm_text: "align $a0, $v0, $v1, 2"
+        details:
+          mips:
+            operands:
+              -
+                type: MIPS_OP_REG
+                reg: a0
+              -
+                type: MIPS_OP_REG
+                reg: v0
+              -
+                type: MIPS_OP_REG
+                reg: v1
+              -
+                type: MIPS_OP_IMM
+                imm: 0x2
+  -
+    input:
+      bytes: [ 0x70, 0x00, 0xb2, 0xff  ]
+      arch: "mips"
+      options: [ CS_MODE_MIPS64, CS_MODE_MIPS2, CS_MODE_LITTLE_ENDIAN, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "sdc3 $18, 0x70($sp)"
+        details:
+          mips:
+            operands:
+              -
+                type: MIPS_OP_REG
+                reg: s2
+              -
+                type: MIPS_OP_MEM
+                mem_base: sp
+                mem_disp: 0x70
+  -
+    input:
+      bytes: [ 0x70, 0x00, 0xb2, 0xff  ]
+      arch: "mips"
+      options: [ CS_OPT_DETAIL, CS_MODE_MIPS64, CS_MODE_LITTLE_ENDIAN]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "sd $s2, 0x70($sp)"
+        details:
+          mips:
+            operands:
+              -
+                type: MIPS_OP_REG
+                reg: s2
+              -
+                type: MIPS_OP_MEM
+                mem_base: sp
+                mem_disp: 0x70
+
diff --git a/tests/details/mos65xx.yaml b/tests/details/mos65xx.yaml
new file mode 100644
index 000000000..7b79af589
--- /dev/null
+++ b/tests/details/mos65xx.yaml
@@ -0,0 +1,520 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xa1, 0x12, 0xa5, 0x12, 0xa9, 0x12, 0xad, 0x34, 0x12, 0xb1, 0x12, 0xb5, 0x12, 0xb9, 0x34, 0x12, 0xbd, 0x34, 0x12, 0x0d, 0x34, 0x12, 0x00, 0x81, 0x87, 0x6c, 0x01, 0x00, 0x85, 0xff, 0x10, 0x00, 0x19, 0x42, 0x42, 0x00, 0x49, 0x42  ]
+      arch: "mos65xx"
+      options: [ CS_OPT_DETAIL, CS_MODE_MOS65XX_6502, CS_OPT_SYNTAX_MOTOROLA ]
+      address: 0x1000
+    expected:
+      insns:
+      -
+        asm_text: "lda ($12, x)"
+        details:
+          mos65xx:
+            am: MOS65XX_AM_ZP_X_IND
+            modifies_flags: 1
+            operands:
+              -
+                type: MOS65XX_OP_MEM
+                mem: 0x12
+      -
+        asm_text: "lda $12"
+        details:
+          mos65xx:
+            am: MOS65XX_AM_ZP
+            modifies_flags: 1
+            operands:
+              -
+                type: MOS65XX_OP_MEM
+                mem: 0x12
+      -
+        asm_text: "lda #$12"
+        details:
+          mos65xx:
+            am: MOS65XX_AM_IMM
+            modifies_flags: 1
+            operands:
+              -
+                type: MOS65XX_OP_IMM
+                imm: 0x12
+      -
+        asm_text: "lda $1234"
+        details:
+          mos65xx:
+            am: MOS65XX_AM_ABS
+            modifies_flags: 1
+            operands:
+              -
+                type: MOS65XX_OP_MEM
+                mem: 0x1234
+      -
+        asm_text: "lda ($12), y"
+        details:
+          mos65xx:
+            am: MOS65XX_AM_ZP_IND_Y
+            modifies_flags: 1
+            operands:
+              -
+                type: MOS65XX_OP_MEM
+                mem: 0x12
+      -
+        asm_text: "lda $12, x"
+        details:
+          mos65xx:
+            am: MOS65XX_AM_ZP_X
+            modifies_flags: 1
+            operands:
+              -
+                type: MOS65XX_OP_MEM
+                mem: 0x12
+      -
+        asm_text: "lda $1234, y"
+        details:
+          mos65xx:
+            am: MOS65XX_AM_ABS_Y
+            modifies_flags: 1
+            operands:
+              -
+                type: MOS65XX_OP_MEM
+                mem: 0x1234
+      -
+        asm_text: "lda $1234, x"
+        details:
+          mos65xx:
+            am: MOS65XX_AM_ABS_X
+            modifies_flags: 1
+            operands:
+              -
+                type: MOS65XX_OP_MEM
+                mem: 0x1234
+      -
+        asm_text: "ora $1234"
+        details:
+          mos65xx:
+            am: MOS65XX_AM_ABS
+            modifies_flags: 1
+            operands:
+              -
+                type: MOS65XX_OP_MEM
+                mem: 0x1234
+      -
+        asm_text: "brk $81"
+        details:
+          mos65xx:
+            am: MOS65XX_AM_INT
+            modifies_flags: -1
+            operands:
+              -
+                type: MOS65XX_OP_MEM
+                mem: 0x81
+  -
+    input:
+      bytes: [ 0x1a, 0x3a, 0x02, 0x12, 0x03, 0x5c, 0x34, 0x12  ]
+      arch: "mos65xx"
+      options: [ CS_OPT_DETAIL, CS_MODE_MOS65XX_65C02, CS_OPT_SYNTAX_MOTOROLA ]
+      address: 0x1000
+    expected:
+      insns:
+      -
+        asm_text: "inc a"
+        details:
+          mos65xx:
+            am: MOS65XX_AM_ACC
+            modifies_flags: 1
+            operands:
+              -
+                type: MOS65XX_OP_REG
+                reg: A
+      -
+        asm_text: "dec a"
+        details:
+          mos65xx:
+            am: MOS65XX_AM_ACC
+            modifies_flags: 1
+            operands:
+              -
+                type: MOS65XX_OP_REG
+                reg: A
+      -
+        asm_text: "nop"
+        details:
+          mos65xx:
+            am: MOS65XX_AM_IMP
+            modifies_flags: -1
+      -
+        asm_text: "nop"
+        details:
+          mos65xx:
+            am: MOS65XX_AM_IMP
+            modifies_flags: -1
+      -
+        asm_text: "nop"
+        details:
+          mos65xx:
+            am: MOS65XX_AM_IMP
+            modifies_flags: -1
+  -
+    input:
+      bytes: [ 0x07, 0x12, 0x27, 0x12, 0x47, 0x12, 0x67, 0x12, 0x87, 0x12, 0xa7, 0x12, 0xc7, 0x12, 0xe7, 0x12, 0x10, 0xfe, 0x0f, 0x12, 0xfd, 0x4f, 0x12, 0xfd, 0x8f, 0x12, 0xfd, 0xcf, 0x12, 0xfd  ]
+      arch: "mos65xx"
+      options: [ CS_OPT_DETAIL, CS_MODE_MOS65XX_W65C02, CS_OPT_SYNTAX_MOTOROLA ]
+      address: 0x1000
+    expected:
+      insns:
+      -
+        asm_text: "rmb0 $12"
+        details:
+          mos65xx:
+            am: MOS65XX_AM_ZP
+            modifies_flags: -1
+            operands:
+              -
+                type: MOS65XX_OP_MEM
+                mem: 0x12
+      -
+        asm_text: "rmb2 $12"
+        details:
+          mos65xx:
+            am: MOS65XX_AM_ZP
+            modifies_flags: -1
+            operands:
+              -
+                type: MOS65XX_OP_MEM
+                mem: 0x12
+      -
+        asm_text: "rmb4 $12"
+        details:
+          mos65xx:
+            am: MOS65XX_AM_ZP
+            modifies_flags: -1
+            operands:
+              -
+                type: MOS65XX_OP_MEM
+                mem: 0x12
+      -
+        asm_text: "rmb6 $12"
+        details:
+          mos65xx:
+            am: MOS65XX_AM_ZP
+            modifies_flags: -1
+            operands:
+              -
+                type: MOS65XX_OP_MEM
+                mem: 0x12
+      -
+        asm_text: "smb0 $12"
+        details:
+          mos65xx:
+            am: MOS65XX_AM_ZP
+            modifies_flags: -1
+            operands:
+              -
+                type: MOS65XX_OP_MEM
+                mem: 0x12
+      -
+        asm_text: "smb2 $12"
+        details:
+          mos65xx:
+            am: MOS65XX_AM_ZP
+            modifies_flags: -1
+            operands:
+              -
+                type: MOS65XX_OP_MEM
+                mem: 0x12
+      -
+        asm_text: "smb4 $12"
+        details:
+          mos65xx:
+            am: MOS65XX_AM_ZP
+            modifies_flags: -1
+            operands:
+              -
+                type: MOS65XX_OP_MEM
+                mem: 0x12
+      -
+        asm_text: "smb6 $12"
+        details:
+          mos65xx:
+            am: MOS65XX_AM_ZP
+            modifies_flags: -1
+            operands:
+              -
+                type: MOS65XX_OP_MEM
+                mem: 0x12
+      -
+        asm_text: "bpl $1010"
+        details:
+          mos65xx:
+            am: MOS65XX_AM_REL
+            modifies_flags: -1
+            operands:
+              -
+                type: MOS65XX_OP_MEM
+                mem: 0x1010
+      -
+        asm_text: "bbr0 $12, $1012"
+        details:
+          mos65xx:
+            am: MOS65XX_AM_ZP_REL
+            modifies_flags: -1
+            operands:
+              -
+                type: MOS65XX_OP_MEM
+                mem: 0x12
+              -
+                type: MOS65XX_OP_MEM
+                mem: 0x1012
+      -
+        asm_text: "bbr4 $12, $1015"
+        details:
+          mos65xx:
+            am: MOS65XX_AM_ZP_REL
+            modifies_flags: -1
+            operands:
+              -
+                type: MOS65XX_OP_MEM
+                mem: 0x12
+              -
+                type: MOS65XX_OP_MEM
+                mem: 0x1015
+      -
+        asm_text: "bbs0 $12, $1018"
+        details:
+          mos65xx:
+            am: MOS65XX_AM_ZP_REL
+            modifies_flags: -1
+            operands:
+              -
+                type: MOS65XX_OP_MEM
+                mem: 0x12
+              -
+                type: MOS65XX_OP_MEM
+                mem: 0x1018
+      -
+        asm_text: "bbs4 $12, $101b"
+        details:
+          mos65xx:
+            am: MOS65XX_AM_ZP_REL
+            modifies_flags: -1
+            operands:
+              -
+                type: MOS65XX_OP_MEM
+                mem: 0x12
+              -
+                type: MOS65XX_OP_MEM
+                mem: 0x101b
+  -
+    input:
+      bytes: [ 0xa9, 0x34, 0x12, 0xad, 0x34, 0x12, 0xbd, 0x34, 0x12, 0xb9, 0x34, 0x12, 0xaf, 0x56, 0x34, 0x12, 0xbf, 0x56, 0x34, 0x12, 0xa5, 0x12, 0xb5, 0x12, 0xb2, 0x12, 0xa1, 0x12, 0xb1, 0x12, 0xa7, 0x12, 0xb7, 0x12, 0xa3, 0x12, 0xb3, 0x12, 0xc2, 0x00, 0xe2, 0x00, 0x54, 0x34, 0x12, 0x44, 0x34, 0x12, 0x02, 0x12  ]
+      arch: "mos65xx"
+      options: [ CS_OPT_DETAIL, CS_MODE_MOS65XX_65816_LONG_MX, CS_OPT_SYNTAX_MOTOROLA ]
+      address: 0x1000
+    expected:
+      insns:
+      -
+        asm_text: "lda #$1234"
+        details:
+          mos65xx:
+            am: MOS65XX_AM_IMM
+            modifies_flags: 1
+            operands:
+              -
+                type: MOS65XX_OP_IMM
+                imm: 0x1234
+      -
+        asm_text: "lda $1234"
+        details:
+          mos65xx:
+            am: MOS65XX_AM_ABS
+            modifies_flags: 1
+            operands:
+              -
+                type: MOS65XX_OP_MEM
+                mem: 0x1234
+      -
+        asm_text: "lda $1234, x"
+        details:
+          mos65xx:
+            am: MOS65XX_AM_ABS_X
+            modifies_flags: 1
+            operands:
+              -
+                type: MOS65XX_OP_MEM
+                mem: 0x1234
+      -
+        asm_text: "lda $1234, y"
+        details:
+          mos65xx:
+            am: MOS65XX_AM_ABS_Y
+            modifies_flags: 1
+            operands:
+              -
+                type: MOS65XX_OP_MEM
+                mem: 0x1234
+      -
+        asm_text: "lda $123456"
+        details:
+          mos65xx:
+            am: MOS65XX_AM_ABS_LONG
+            modifies_flags: 1
+            operands:
+              -
+                type: MOS65XX_OP_MEM
+                mem: 0x123456
+      -
+        asm_text: "lda $123456, x"
+        details:
+          mos65xx:
+            am: MOS65XX_AM_ABS_LONG_X
+            modifies_flags: 1
+            operands:
+              -
+                type: MOS65XX_OP_MEM
+                mem: 0x123456
+      -
+        asm_text: "lda $12"
+        details:
+          mos65xx:
+            am: MOS65XX_AM_ZP
+            modifies_flags: 1
+            operands:
+              -
+                type: MOS65XX_OP_MEM
+                mem: 0x12
+      -
+        asm_text: "lda $12, x"
+        details:
+          mos65xx:
+            am: MOS65XX_AM_ZP_X
+            modifies_flags: 1
+            operands:
+              -
+                type: MOS65XX_OP_MEM
+                mem: 0x12
+      -
+        asm_text: "lda ($12)"
+        details:
+          mos65xx:
+            am: MOS65XX_AM_ZP_IND
+            modifies_flags: 1
+            operands:
+              -
+                type: MOS65XX_OP_MEM
+                mem: 0x12
+      -
+        asm_text: "lda ($12, x)"
+        details:
+          mos65xx:
+            am: MOS65XX_AM_ZP_X_IND
+            modifies_flags: 1
+            operands:
+              -
+                type: MOS65XX_OP_MEM
+                mem: 0x12
+      -
+        asm_text: "lda ($12), y"
+        details:
+          mos65xx:
+            am: MOS65XX_AM_ZP_IND_Y
+            modifies_flags: 1
+            operands:
+              -
+                type: MOS65XX_OP_MEM
+                mem: 0x12
+      -
+        asm_text: "lda [$12]"
+        details:
+          mos65xx:
+            am: MOS65XX_AM_ZP_IND_LONG
+            modifies_flags: 1
+            operands:
+              -
+                type: MOS65XX_OP_MEM
+                mem: 0x12
+      -
+        asm_text: "lda [$12], y"
+        details:
+          mos65xx:
+            am: MOS65XX_AM_ZP_IND_LONG_Y
+            modifies_flags: 1
+            operands:
+              -
+                type: MOS65XX_OP_MEM
+                mem: 0x12
+      -
+        asm_text: "lda $12, s"
+        details:
+          mos65xx:
+            am: MOS65XX_AM_SR
+            modifies_flags: 1
+            operands:
+              -
+                type: MOS65XX_OP_MEM
+                mem: 0x12
+      -
+        asm_text: "lda ($12, s), y"
+        details:
+          mos65xx:
+            am: MOS65XX_AM_SR_IND_Y
+            modifies_flags: 1
+            operands:
+              -
+                type: MOS65XX_OP_MEM
+                mem: 0x12
+      -
+        asm_text: "rep #$00"
+        details:
+          mos65xx:
+            am: MOS65XX_AM_IMM
+            modifies_flags: 1
+            operands:
+              -
+                type: MOS65XX_OP_IMM
+                imm: 0x0
+      -
+        asm_text: "sep #$00"
+        details:
+          mos65xx:
+            am: MOS65XX_AM_IMM
+            modifies_flags: 1
+            operands:
+              -
+                type: MOS65XX_OP_IMM
+                imm: 0x0
+      -
+        asm_text: "mvn $12, $34"
+        details:
+          mos65xx:
+            am: MOS65XX_AM_BLOCK
+            modifies_flags: -1
+            operands:
+              -
+                type: MOS65XX_OP_MEM
+                mem: 0x12
+              -
+                type: MOS65XX_OP_MEM
+                mem: 0x34
+      -
+        asm_text: "mvp $12, $34"
+        details:
+          mos65xx:
+            am: MOS65XX_AM_BLOCK
+            modifies_flags: -1
+            operands:
+              -
+                type: MOS65XX_OP_MEM
+                mem: 0x12
+              -
+                type: MOS65XX_OP_MEM
+                mem: 0x34
+      -
+        asm_text: "cop $12"
+        details:
+          mos65xx:
+            am: MOS65XX_AM_INT
+            modifies_flags: -1
+            operands:
+              -
+                type: MOS65XX_OP_MEM
+                mem: 0x12
+
diff --git a/tests/details/ppc.yaml b/tests/details/ppc.yaml
new file mode 100644
index 000000000..079f06ef6
--- /dev/null
+++ b/tests/details/ppc.yaml
@@ -0,0 +1,1498 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x43, 0x20, 0x0c, 0x07, 0x41, 0x56, 0xff, 0x17, 0x80, 0x20, 0x00, 0x00, 0x80, 0x3f, 0x00, 0x00, 0x10, 0x43, 0x23, 0x0e, 0xd0, 0x44, 0x00, 0x80, 0x4c, 0x43, 0x22, 0x02, 0x2d, 0x03, 0x00, 0x80, 0x7c, 0x43, 0x20, 0x14, 0x7c, 0x43, 0x20, 0x93, 0x4f, 0x20, 0x00, 0x21, 0x4c, 0xc8, 0x00, 0x21, 0x40, 0x82, 0x00, 0x14 ]
+      arch: "ppc"
+      options: [ CS_MODE_BIG_ENDIAN, CS_OPT_DETAIL ]
+      address: 0x1000
+    expected:
+      insns:
+      -
+        asm_text: "bcla 0x19, lt, 0xc04"
+        details:
+         ppc:
+            operands:
+              -
+                type: PPC_OP_IMM
+                imm: 0x19
+                access: CS_AC_READ
+              -
+                type: PPC_OP_REG
+                reg: "0"
+                access: CS_AC_READ
+              -
+                type: PPC_OP_IMM
+                imm: 0xc04
+                access: CS_AC_READ
+            bc:
+              bi: 0
+              bi_set: true
+              bo: 25
+              bo_set: true
+              pred_ctr: PPC_PRED_NZ
+      -
+        asm_text: "bdztla 4*cr5+eq, 0xff14"
+        details:
+         ppc:
+            operands:
+              -
+                type: PPC_OP_REG
+                reg: "22"
+                access: CS_AC_READ
+              -
+                type: PPC_OP_IMM
+                imm: 0xff14
+                access: CS_AC_READ
+            bc:
+              bi: 22
+              bi_set: true
+              bo: 10
+              bo_set: true
+              crX: cr5
+              crX_bit: PPC_BI_Z
+              pred_ctr: PPC_PRED_Z
+      -
+        asm_text: "lwz r1, 0(0)"
+        details:
+         ppc:
+            operands:
+              -
+                type: PPC_OP_REG
+                reg: r1
+                access: CS_AC_WRITE
+              -
+                type: PPC_OP_MEM
+                mem_base: "0"
+                access: CS_AC_READ
+      -
+        asm_text: "lwz r1, 0(r31)"
+        details:
+         ppc:
+            operands:
+              -
+                type: PPC_OP_REG
+                reg: r1
+                access: CS_AC_WRITE
+              -
+                type: PPC_OP_MEM
+                mem_base: r31
+                access: CS_AC_READ
+      -
+        asm_text: "vpkpx v2, v3, v4"
+        details:
+         ppc:
+            operands:
+              -
+                type: PPC_OP_REG
+                reg: v2
+                access: CS_AC_WRITE
+              -
+                type: PPC_OP_REG
+                reg: v3
+                access: CS_AC_READ
+              -
+                type: PPC_OP_REG
+                reg: v4
+                access: CS_AC_READ
+      -
+        asm_text: "stfs f2, 0x80(r4)"
+        details:
+         ppc:
+            operands:
+              -
+                type: PPC_OP_REG
+                reg: f2
+                access: CS_AC_READ
+              -
+                type: PPC_OP_MEM
+                mem_base: r4
+                mem_disp: 0x80
+                access: CS_AC_WRITE
+      -
+        asm_text: "crand eq, un, 4*cr1+lt"
+        details:
+         ppc:
+            operands:
+              -
+                type: PPC_OP_REG
+                reg: "2"
+                access: CS_AC_WRITE
+              -
+                type: PPC_OP_REG
+                reg: "3"
+                access: CS_AC_READ
+              -
+                type: PPC_OP_REG
+                reg: "4"
+                access: CS_AC_READ
+      -
+        asm_text: "cmpwi cr2, r3, 0x80"
+        details:
+         ppc:
+            operands:
+              -
+                type: PPC_OP_REG
+                reg: cr2
+                access: CS_AC_WRITE
+              -
+                type: PPC_OP_REG
+                reg: r3
+                access: CS_AC_READ
+              -
+                type: PPC_OP_IMM
+                imm: 0x80
+                access: CS_AC_READ
+      -
+        asm_text: "addc r2, r3, r4"
+        details:
+         ppc:
+            operands:
+              -
+                type: PPC_OP_REG
+                reg: r2
+                access: CS_AC_WRITE
+              -
+                type: PPC_OP_REG
+                reg: r3
+                access: CS_AC_READ
+              -
+                type: PPC_OP_REG
+                reg: r4
+                access: CS_AC_READ
+      -
+        asm_text: "mulhd. r2, r3, r4"
+        details:
+         ppc:
+            operands:
+              -
+                type: PPC_OP_REG
+                reg: r2
+                access: CS_AC_WRITE
+              -
+                type: PPC_OP_REG
+                reg: r3
+                access: CS_AC_READ
+              -
+                type: PPC_OP_REG
+                reg: r4
+                access: CS_AC_READ
+            update_cr0: 1
+      -
+        asm_text: "bdnzlrl+"
+        details:
+         ppc:
+           bc:
+             bi: 0
+             bi_set: true
+             bo: 25
+             bo_set: true
+             bh: PPC_BH_SUBROUTINE_RET
+             pred_ctr: PPC_PRED_NZ
+             hint: PPC_BR_TAKEN
+      -
+        asm_text: "bflrl- 4*cr2+lt"
+        details:
+          ppc:
+            operands:
+              -
+                type: PPC_OP_REG
+                reg: "8"
+                access: CS_AC_READ
+            bc:
+               bi: 8
+               bi_set: true
+               bo: 6
+               bo_set: true
+               bh: PPC_BH_SUBROUTINE_RET
+               crX: cr2
+               crX_bit: PPC_BI_LT
+               hint: PPC_BR_NOT_TAKEN
+      -
+        asm_text: "bf eq, 0x1044"
+        details:
+          ppc:
+             operands:
+               -
+                 type: PPC_OP_REG
+                 reg: "2"
+                 access: CS_AC_READ
+               -
+                 type: PPC_OP_IMM
+                 imm: 0x1044
+                 access: CS_AC_READ
+             bc:
+               bi: 2
+               bi_set: true
+               bo: 4
+               bo_set: true
+               crX: cr0
+               crX_bit: PPC_BI_Z
+  -
+    input:
+      bytes: [ 0x10, 0x60, 0x2a, 0x10, 0x10, 0x64, 0x28, 0x88, 0x7c, 0x4a, 0x5d, 0x0f  ]
+      arch: "ppc"
+      options: [ CS_MODE_64, CS_MODE_BIG_ENDIAN, CS_MODE_QPX, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "qvfabs q3, q5"
+        details:
+         ppc:
+            operands:
+              -
+                type: PPC_OP_REG
+                reg: q3
+                access: CS_AC_WRITE
+              -
+                type: PPC_OP_REG
+                reg: q5
+                access: CS_AC_READ
+      -
+        asm_text: "qvfand q3, q4, q5"
+        details:
+         ppc:
+            operands:
+              -
+                type: PPC_OP_REG
+                reg: q3
+                access: CS_AC_WRITE
+              -
+                type: PPC_OP_REG
+                reg: q4
+                access: CS_AC_READ
+              -
+                type: PPC_OP_REG
+                reg: q5
+                access: CS_AC_READ
+      -
+        asm_text: "qvstfsxa q2, r10, r11"
+        details:
+         ppc:
+            operands:
+              -
+                type: PPC_OP_REG
+                reg: q2
+                access: CS_AC_READ
+              -
+                type: PPC_OP_MEM
+                mem_base: r10
+                mem_offset: r11
+                access: CS_AC_WRITE
+  -
+    input:
+      bytes: [ 0x10, 0x00, 0x1f, 0xec, 0xe0, 0x6d, 0x80, 0x04, 0xe4, 0x6d, 0x80, 0x04, 0x10, 0x60, 0x1c, 0x4c, 0x10, 0x60, 0x1c, 0x0c, 0xf0, 0x6d, 0x80, 0x04, 0xf4, 0x6d, 0x80, 0x04, 0x10, 0x60, 0x1c, 0x4e, 0x10, 0x60, 0x1c, 0x0e, 0x10, 0x60, 0x1a, 0x10, 0x10, 0x60, 0x1a, 0x11, 0x10, 0x63, 0x20, 0x2a, 0x10, 0x63, 0x20, 0x2b, 0x10, 0x83, 0x20, 0x40, 0x10, 0x83, 0x20, 0xc0, 0x10, 0x83, 0x20, 0x00, 0x10, 0x83, 0x20, 0x80, 0x10, 0x63, 0x20, 0x24, 0x10, 0x63, 0x20, 0x25, 0x10, 0x63, 0x29, 0x3a, 0x10, 0x63, 0x29, 0x3b, 0x10, 0x63, 0x29, 0x1c, 0x10, 0x63, 0x29, 0x1d, 0x10, 0x63, 0x29, 0x1e, 0x10, 0x63, 0x29, 0x1f, 0x10, 0x63, 0x24, 0x20, 0x10, 0x63, 0x24, 0x21, 0x10, 0x63, 0x24, 0x60, 0x10, 0x63, 0x24, 0x61, 0x10, 0x63, 0x24, 0xa0, 0x10, 0x63, 0x24, 0xa1, 0x10, 0x63, 0x24, 0xe0, 0x10, 0x63, 0x24, 0xe1, 0x10, 0x60, 0x20, 0x90, 0x10, 0x60, 0x20, 0x91, 0x10, 0x63, 0x29, 0x38, 0x10, 0x63, 0x29, 0x39, 0x10, 0x63, 0x01, 0x32, 0x10, 0x63, 0x01, 0x33, 0x10, 0x63, 0x01, 0x18, 0x10, 0x63, 0x01, 0x19, 0x10, 0x63, 0x01, 0x1a, 0x10, 0x63, 0x01, 0x1b, 0x10, 0x60, 0x19, 0x10, 0x10, 0x60, 0x19, 0x11, 0x10, 0x60, 0x18, 0x50, 0x10, 0x60, 0x18, 0x51, 0x10, 0x63, 0x29, 0x3e, 0x10, 0x63, 0x29, 0x3f, 0x10, 0x63, 0x29, 0x3c, 0x10, 0x63, 0x29, 0x3d, 0x10, 0x60, 0x18, 0x30, 0x10, 0x60, 0x18, 0x31, 0x10, 0x60, 0x18, 0x34, 0x10, 0x60, 0x18, 0x35, 0x10, 0x63, 0x29, 0x2e, 0x10, 0x63, 0x29, 0x2f, 0x10, 0x63, 0x20, 0x28, 0x10, 0x63, 0x20, 0x29, 0x10, 0x63, 0x29, 0x14, 0x10, 0x63, 0x29, 0x15, 0x10, 0x63, 0x29, 0x16, 0x10, 0x63, 0x29, 0x17  ]
+      arch: "ppc"
+      options: [ CS_MODE_BIG_ENDIAN, CS_MODE_PS, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "dcbz_l r0, r3"
+        details:
+         ppc:
+            operands:
+              -
+                type: PPC_OP_REG
+                reg: r0
+                access: CS_AC_READ
+              -
+                type: PPC_OP_REG
+                reg: r3
+                access: CS_AC_READ
+      -
+        asm_text: "psq_l f3, 4(r13), 1, 0"
+        details:
+         ppc:
+            operands:
+              -
+                type: PPC_OP_REG
+                reg: f3
+                access: CS_AC_WRITE
+              -
+                type: PPC_OP_MEM
+                mem_base: r13
+                mem_disp: 0x4
+                access: CS_AC_READ
+              -
+                type: PPC_OP_IMM
+                imm: 0x1
+                access: CS_AC_READ
+              -
+                type: PPC_OP_IMM
+                imm: 0x0
+                access: CS_AC_READ
+      -
+        asm_text: "psq_lu f3, 4(r13), 1, 0"
+        details:
+         ppc:
+            operands:
+              -
+                type: PPC_OP_REG
+                reg: f3
+                access: CS_AC_WRITE
+              -
+                type: PPC_OP_MEM
+                mem_base: r13
+                mem_disp: 0x4
+                access: CS_AC_READ
+              -
+                type: PPC_OP_IMM
+                imm: 0x1
+                access: CS_AC_READ
+              -
+                type: PPC_OP_IMM
+                imm: 0x0
+                access: CS_AC_READ
+      -
+        asm_text: "psq_lux f3, r0, r3, 1, 0"
+        details:
+         ppc:
+            operands:
+              -
+                type: PPC_OP_REG
+                reg: f3
+                access: CS_AC_WRITE
+              -
+                type: PPC_OP_REG
+                reg: r0
+                access: CS_AC_READ
+              -
+                type: PPC_OP_REG
+                reg: r3
+                access: CS_AC_READ
+              -
+                type: PPC_OP_IMM
+                imm: 0x1
+                access: CS_AC_READ
+              -
+                type: PPC_OP_IMM
+                imm: 0x0
+                access: CS_AC_READ
+      -
+        asm_text: "psq_lx f3, r0, r3, 1, 0"
+        details:
+         ppc:
+            operands:
+              -
+                type: PPC_OP_REG
+                reg: f3
+                access: CS_AC_WRITE
+              -
+                type: PPC_OP_REG
+                reg: r0
+                access: CS_AC_READ
+              -
+                type: PPC_OP_REG
+                reg: r3
+                access: CS_AC_READ
+              -
+                type: PPC_OP_IMM
+                imm: 0x1
+                access: CS_AC_READ
+              -
+                type: PPC_OP_IMM
+                imm: 0x0
+                access: CS_AC_READ
+      -
+        asm_text: "psq_st f3, 4(r13), 1, 0"
+        details:
+         ppc:
+            operands:
+              -
+                type: PPC_OP_REG
+                reg: f3
+                access: CS_AC_READ
+              -
+                type: PPC_OP_MEM
+                mem_base: r13
+                mem_disp: 0x4
+                access: CS_AC_WRITE
+              -
+                type: PPC_OP_IMM
+                imm: 0x1
+                access: CS_AC_READ
+              -
+                type: PPC_OP_IMM
+                imm: 0x0
+                access: CS_AC_READ
+      -
+        asm_text: "psq_stu f3, 4(r13), 1, 0"
+        details:
+         ppc:
+            operands:
+              -
+                type: PPC_OP_REG
+                reg: f3
+                access: CS_AC_READ
+              -
+                type: PPC_OP_MEM
+                mem_base: r13
+                mem_disp: 0x4
+                access: CS_AC_WRITE
+              -
+                type: PPC_OP_IMM
+                imm: 0x1
+                access: CS_AC_READ
+              -
+                type: PPC_OP_IMM
+                imm: 0x0
+                access: CS_AC_READ
+      -
+        asm_text: "psq_stux f3, r0, r3, 1, 0"
+        details:
+         ppc:
+            operands:
+              -
+                type: PPC_OP_REG
+                reg: f3
+                access: CS_AC_READ
+              -
+                type: PPC_OP_REG
+                reg: r0
+                access: CS_AC_READ
+              -
+                type: PPC_OP_REG
+                reg: r3
+                access: CS_AC_READ
+              -
+                type: PPC_OP_IMM
+                imm: 0x1
+                access: CS_AC_READ
+              -
+                type: PPC_OP_IMM
+                imm: 0x0
+                access: CS_AC_READ
+      -
+        asm_text: "psq_stx f3, r0, r3, 1, 0"
+        details:
+         ppc:
+            operands:
+              -
+                type: PPC_OP_REG
+                reg: f3
+                access: CS_AC_READ
+              -
+                type: PPC_OP_REG
+                reg: r0
+                access: CS_AC_READ
+              -
+                type: PPC_OP_REG
+                reg: r3
+                access: CS_AC_READ
+              -
+                type: PPC_OP_IMM
+                imm: 0x1
+                access: CS_AC_READ
+              -
+                type: PPC_OP_IMM
+                imm: 0x0
+                access: CS_AC_READ
+      -
+        asm_text: "ps_abs f3, f3"
+        details:
+         ppc:
+            operands:
+              -
+                type: PPC_OP_REG
+                reg: f3
+                access: CS_AC_WRITE
+              -
+                type: PPC_OP_REG
+                reg: f3
+                access: CS_AC_READ
+      -
+        asm_text: "ps_abs. f3, f3"
+        details:
+         ppc:
+            operands:
+              -
+                type: PPC_OP_REG
+                reg: f3
+                access: CS_AC_WRITE
+              -
+                type: PPC_OP_REG
+                reg: f3
+                access: CS_AC_READ
+      -
+        asm_text: "ps_add f3, f3, f4"
+        details:
+         ppc:
+            operands:
+              -
+                type: PPC_OP_REG
+                reg: f3
+                access: CS_AC_WRITE
+              -
+                type: PPC_OP_REG
+                reg: f3
+                access: CS_AC_READ
+              -
+                type: PPC_OP_REG
+                reg: f4
+                access: CS_AC_READ
+      -
+        asm_text: "ps_add. f3, f3, f4"
+        details:
+         ppc:
+            operands:
+              -
+                type: PPC_OP_REG
+                reg: f3
+                access: CS_AC_WRITE
+              -
+                type: PPC_OP_REG
+                reg: f3
+                access: CS_AC_READ
+              -
+                type: PPC_OP_REG
+                reg: f4
+                access: CS_AC_READ
+      -
+        asm_text: "ps_cmpo0 cr1, f3, f4"
+        details:
+         ppc:
+            operands:
+              -
+                type: PPC_OP_REG
+                reg: cr1
+                access: CS_AC_WRITE
+              -
+                type: PPC_OP_REG
+                reg: f3
+                access: CS_AC_READ
+              -
+                type: PPC_OP_REG
+                reg: f4
+                access: CS_AC_READ
+      -
+        asm_text: "ps_cmpo1 cr1, f3, f4"
+        details:
+         ppc:
+            operands:
+              -
+                type: PPC_OP_REG
+                reg: cr1
+                access: CS_AC_WRITE
+              -
+                type: PPC_OP_REG
+                reg: f3
+                access: CS_AC_READ
+              -
+                type: PPC_OP_REG
+                reg: f4
+                access: CS_AC_READ
+      -
+        asm_text: "ps_cmpu0 cr1, f3, f4"
+        details:
+         ppc:
+            operands:
+              -
+                type: PPC_OP_REG
+                reg: cr1
+                access: CS_AC_WRITE
+              -
+                type: PPC_OP_REG
+                reg: f3
+                access: CS_AC_READ
+              -
+                type: PPC_OP_REG
+                reg: f4
+                access: CS_AC_READ
+      -
+        asm_text: "ps_cmpu1 cr1, f3, f4"
+        details:
+         ppc:
+            operands:
+              -
+                type: PPC_OP_REG
+                reg: cr1
+                access: CS_AC_WRITE
+              -
+                type: PPC_OP_REG
+                reg: f3
+                access: CS_AC_READ
+              -
+                type: PPC_OP_REG
+                reg: f4
+                access: CS_AC_READ
+      -
+        asm_text: "ps_div f3, f3, f4"
+        details:
+         ppc:
+            operands:
+              -
+                type: PPC_OP_REG
+                reg: f3
+                access: CS_AC_WRITE
+              -
+                type: PPC_OP_REG
+                reg: f3
+                access: CS_AC_READ
+              -
+                type: PPC_OP_REG
+                reg: f4
+                access: CS_AC_READ
+      -
+        asm_text: "ps_div. f3, f3, f4"
+        details:
+         ppc:
+            operands:
+              -
+                type: PPC_OP_REG
+                reg: f3
+                access: CS_AC_WRITE
+              -
+                type: PPC_OP_REG
+                reg: f3
+                access: CS_AC_READ
+              -
+                type: PPC_OP_REG
+                reg: f4
+                access: CS_AC_READ
+      -
+        asm_text: "ps_madd f3, f3, f4, f5"
+        details:
+         ppc:
+            operands:
+              -
+                type: PPC_OP_REG
+                reg: f3
+                access: CS_AC_WRITE
+              -
+                type: PPC_OP_REG
+                reg: f3
+                access: CS_AC_READ
+              -
+                type: PPC_OP_REG
+                reg: f4
+                access: CS_AC_READ
+              -
+                type: PPC_OP_REG
+                reg: f5
+                access: CS_AC_READ
+      -
+        asm_text: "ps_madd. f3, f3, f4, f5"
+        details:
+         ppc:
+            operands:
+              -
+                type: PPC_OP_REG
+                reg: f3
+                access: CS_AC_WRITE
+              -
+                type: PPC_OP_REG
+                reg: f3
+                access: CS_AC_READ
+              -
+                type: PPC_OP_REG
+                reg: f4
+                access: CS_AC_READ
+              -
+                type: PPC_OP_REG
+                reg: f5
+                access: CS_AC_READ
+      -
+        asm_text: "ps_madds0 f3, f3, f4, f5"
+        details:
+         ppc:
+            operands:
+              -
+                type: PPC_OP_REG
+                reg: f3
+                access: CS_AC_WRITE
+              -
+                type: PPC_OP_REG
+                reg: f3
+                access: CS_AC_READ
+              -
+                type: PPC_OP_REG
+                reg: f4
+                access: CS_AC_READ
+              -
+                type: PPC_OP_REG
+                reg: f5
+                access: CS_AC_READ
+      -
+        asm_text: "ps_madds0. f3, f3, f4, f5"
+        details:
+         ppc:
+            operands:
+              -
+                type: PPC_OP_REG
+                reg: f3
+                access: CS_AC_WRITE
+              -
+                type: PPC_OP_REG
+                reg: f3
+                access: CS_AC_READ
+              -
+                type: PPC_OP_REG
+                reg: f4
+                access: CS_AC_READ
+              -
+                type: PPC_OP_REG
+                reg: f5
+                access: CS_AC_READ
+      -
+        asm_text: "ps_madds1 f3, f3, f4, f5"
+        details:
+         ppc:
+            operands:
+              -
+                type: PPC_OP_REG
+                reg: f3
+                access: CS_AC_WRITE
+              -
+                type: PPC_OP_REG
+                reg: f3
+                access: CS_AC_READ
+              -
+                type: PPC_OP_REG
+                reg: f4
+                access: CS_AC_READ
+              -
+                type: PPC_OP_REG
+                reg: f5
+                access: CS_AC_READ
+      -
+        asm_text: "ps_madds1. f3, f3, f4, f5"
+        details:
+         ppc:
+            operands:
+              -
+                type: PPC_OP_REG
+                reg: f3
+                access: CS_AC_WRITE
+              -
+                type: PPC_OP_REG
+                reg: f3
+                access: CS_AC_READ
+              -
+                type: PPC_OP_REG
+                reg: f4
+                access: CS_AC_READ
+              -
+                type: PPC_OP_REG
+                reg: f5
+                access: CS_AC_READ
+      -
+        asm_text: "ps_merge00 f3, f3, f4"
+        details:
+         ppc:
+            operands:
+              -
+                type: PPC_OP_REG
+                reg: f3
+                access: CS_AC_WRITE
+              -
+                type: PPC_OP_REG
+                reg: f3
+                access: CS_AC_READ
+              -
+                type: PPC_OP_REG
+                reg: f4
+                access: CS_AC_READ
+      -
+        asm_text: "ps_merge00. f3, f3, f4"
+        details:
+         ppc:
+            operands:
+              -
+                type: PPC_OP_REG
+                reg: f3
+                access: CS_AC_WRITE
+              -
+                type: PPC_OP_REG
+                reg: f3
+                access: CS_AC_READ
+              -
+                type: PPC_OP_REG
+                reg: f4
+                access: CS_AC_READ
+      -
+        asm_text: "ps_merge01 f3, f3, f4"
+        details:
+         ppc:
+            operands:
+              -
+                type: PPC_OP_REG
+                reg: f3
+                access: CS_AC_WRITE
+              -
+                type: PPC_OP_REG
+                reg: f3
+                access: CS_AC_READ
+              -
+                type: PPC_OP_REG
+                reg: f4
+                access: CS_AC_READ
+      -
+        asm_text: "ps_merge01. f3, f3, f4"
+        details:
+         ppc:
+            operands:
+              -
+                type: PPC_OP_REG
+                reg: f3
+                access: CS_AC_WRITE
+              -
+                type: PPC_OP_REG
+                reg: f3
+                access: CS_AC_READ
+              -
+                type: PPC_OP_REG
+                reg: f4
+                access: CS_AC_READ
+      -
+        asm_text: "ps_merge10 f3, f3, f4"
+        details:
+         ppc:
+            operands:
+              -
+                type: PPC_OP_REG
+                reg: f3
+                access: CS_AC_WRITE
+              -
+                type: PPC_OP_REG
+                reg: f3
+                access: CS_AC_READ
+              -
+                type: PPC_OP_REG
+                reg: f4
+                access: CS_AC_READ
+      -
+        asm_text: "ps_merge10. f3, f3, f4"
+        details:
+         ppc:
+            operands:
+              -
+                type: PPC_OP_REG
+                reg: f3
+                access: CS_AC_WRITE
+              -
+                type: PPC_OP_REG
+                reg: f3
+                access: CS_AC_READ
+              -
+                type: PPC_OP_REG
+                reg: f4
+                access: CS_AC_READ
+      -
+        asm_text: "ps_merge11 f3, f3, f4"
+        details:
+         ppc:
+            operands:
+              -
+                type: PPC_OP_REG
+                reg: f3
+                access: CS_AC_WRITE
+              -
+                type: PPC_OP_REG
+                reg: f3
+                access: CS_AC_READ
+              -
+                type: PPC_OP_REG
+                reg: f4
+                access: CS_AC_READ
+      -
+        asm_text: "ps_merge11. f3, f3, f4"
+        details:
+         ppc:
+            operands:
+              -
+                type: PPC_OP_REG
+                reg: f3
+                access: CS_AC_WRITE
+              -
+                type: PPC_OP_REG
+                reg: f3
+                access: CS_AC_READ
+              -
+                type: PPC_OP_REG
+                reg: f4
+                access: CS_AC_READ
+      -
+        asm_text: "ps_mr f3, f4"
+        details:
+         ppc:
+            operands:
+              -
+                type: PPC_OP_REG
+                reg: f3
+                access: CS_AC_WRITE
+              -
+                type: PPC_OP_REG
+                reg: f4
+                access: CS_AC_READ
+      -
+        asm_text: "ps_mr. f3, f4"
+        details:
+         ppc:
+            operands:
+              -
+                type: PPC_OP_REG
+                reg: f3
+                access: CS_AC_WRITE
+              -
+                type: PPC_OP_REG
+                reg: f4
+                access: CS_AC_READ
+      -
+        asm_text: "ps_msub f3, f3, f4, f5"
+        details:
+         ppc:
+            operands:
+              -
+                type: PPC_OP_REG
+                reg: f3
+                access: CS_AC_WRITE
+              -
+                type: PPC_OP_REG
+                reg: f3
+                access: CS_AC_READ
+              -
+                type: PPC_OP_REG
+                reg: f4
+                access: CS_AC_READ
+              -
+                type: PPC_OP_REG
+                reg: f5
+                access: CS_AC_READ
+      -
+        asm_text: "ps_msub. f3, f3, f4, f5"
+        details:
+         ppc:
+            operands:
+              -
+                type: PPC_OP_REG
+                reg: f3
+                access: CS_AC_WRITE
+              -
+                type: PPC_OP_REG
+                reg: f3
+                access: CS_AC_READ
+              -
+                type: PPC_OP_REG
+                reg: f4
+                access: CS_AC_READ
+              -
+                type: PPC_OP_REG
+                reg: f5
+                access: CS_AC_READ
+      -
+        asm_text: "ps_mul f3, f3, f4"
+        details:
+         ppc:
+            operands:
+              -
+                type: PPC_OP_REG
+                reg: f3
+                access: CS_AC_WRITE
+              -
+                type: PPC_OP_REG
+                reg: f3
+                access: CS_AC_READ
+              -
+                type: PPC_OP_REG
+                reg: f4
+                access: CS_AC_READ
+      -
+        asm_text: "ps_mul. f3, f3, f4"
+        details:
+         ppc:
+            operands:
+              -
+                type: PPC_OP_REG
+                reg: f3
+                access: CS_AC_WRITE
+              -
+                type: PPC_OP_REG
+                reg: f3
+                access: CS_AC_READ
+              -
+                type: PPC_OP_REG
+                reg: f4
+                access: CS_AC_READ
+      -
+        asm_text: "ps_muls0 f3, f3, f4"
+        details:
+         ppc:
+            operands:
+              -
+                type: PPC_OP_REG
+                reg: f3
+                access: CS_AC_WRITE
+              -
+                type: PPC_OP_REG
+                reg: f3
+                access: CS_AC_READ
+              -
+                type: PPC_OP_REG
+                reg: f4
+                access: CS_AC_READ
+      -
+        asm_text: "ps_muls0. f3, f3, f4"
+        details:
+         ppc:
+            operands:
+              -
+                type: PPC_OP_REG
+                reg: f3
+                access: CS_AC_WRITE
+              -
+                type: PPC_OP_REG
+                reg: f3
+                access: CS_AC_READ
+              -
+                type: PPC_OP_REG
+                reg: f4
+                access: CS_AC_READ
+      -
+        asm_text: "ps_muls1 f3, f3, f4"
+        details:
+         ppc:
+            operands:
+              -
+                type: PPC_OP_REG
+                reg: f3
+                access: CS_AC_WRITE
+              -
+                type: PPC_OP_REG
+                reg: f3
+                access: CS_AC_READ
+              -
+                type: PPC_OP_REG
+                reg: f4
+                access: CS_AC_READ
+      -
+        asm_text: "ps_muls1. f3, f3, f4"
+        details:
+         ppc:
+            operands:
+              -
+                type: PPC_OP_REG
+                reg: f3
+                access: CS_AC_WRITE
+              -
+                type: PPC_OP_REG
+                reg: f3
+                access: CS_AC_READ
+              -
+                type: PPC_OP_REG
+                reg: f4
+                access: CS_AC_READ
+      -
+        asm_text: "ps_nabs f3, f3"
+        details:
+         ppc:
+            operands:
+              -
+                type: PPC_OP_REG
+                reg: f3
+                access: CS_AC_WRITE
+              -
+                type: PPC_OP_REG
+                reg: f3
+                access: CS_AC_READ
+      -
+        asm_text: "ps_nabs. f3, f3"
+        details:
+         ppc:
+            operands:
+              -
+                type: PPC_OP_REG
+                reg: f3
+                access: CS_AC_WRITE
+              -
+                type: PPC_OP_REG
+                reg: f3
+                access: CS_AC_READ
+      -
+        asm_text: "ps_neg f3, f3"
+        details:
+         ppc:
+            operands:
+              -
+                type: PPC_OP_REG
+                reg: f3
+                access: CS_AC_WRITE
+              -
+                type: PPC_OP_REG
+                reg: f3
+                access: CS_AC_READ
+      -
+        asm_text: "ps_neg. f3, f3"
+        details:
+         ppc:
+            operands:
+              -
+                type: PPC_OP_REG
+                reg: f3
+                access: CS_AC_WRITE
+              -
+                type: PPC_OP_REG
+                reg: f3
+                access: CS_AC_READ
+      -
+        asm_text: "ps_nmadd f3, f3, f4, f5"
+        details:
+         ppc:
+            operands:
+              -
+                type: PPC_OP_REG
+                reg: f3
+                access: CS_AC_WRITE
+              -
+                type: PPC_OP_REG
+                reg: f3
+                access: CS_AC_READ
+              -
+                type: PPC_OP_REG
+                reg: f4
+                access: CS_AC_READ
+              -
+                type: PPC_OP_REG
+                reg: f5
+                access: CS_AC_READ
+      -
+        asm_text: "ps_nmadd. f3, f3, f4, f5"
+        details:
+         ppc:
+            operands:
+              -
+                type: PPC_OP_REG
+                reg: f3
+                access: CS_AC_WRITE
+              -
+                type: PPC_OP_REG
+                reg: f3
+                access: CS_AC_READ
+              -
+                type: PPC_OP_REG
+                reg: f4
+                access: CS_AC_READ
+              -
+                type: PPC_OP_REG
+                reg: f5
+                access: CS_AC_READ
+      -
+        asm_text: "ps_nmsub f3, f3, f4, f5"
+        details:
+         ppc:
+            operands:
+              -
+                type: PPC_OP_REG
+                reg: f3
+                access: CS_AC_WRITE
+              -
+                type: PPC_OP_REG
+                reg: f3
+                access: CS_AC_READ
+              -
+                type: PPC_OP_REG
+                reg: f4
+                access: CS_AC_READ
+              -
+                type: PPC_OP_REG
+                reg: f5
+                access: CS_AC_READ
+      -
+        asm_text: "ps_nmsub. f3, f3, f4, f5"
+        details:
+         ppc:
+            operands:
+              -
+                type: PPC_OP_REG
+                reg: f3
+                access: CS_AC_WRITE
+              -
+                type: PPC_OP_REG
+                reg: f3
+                access: CS_AC_READ
+              -
+                type: PPC_OP_REG
+                reg: f4
+                access: CS_AC_READ
+              -
+                type: PPC_OP_REG
+                reg: f5
+                access: CS_AC_READ
+      -
+        asm_text: "ps_res f3, f3"
+        details:
+         ppc:
+            operands:
+              -
+                type: PPC_OP_REG
+                reg: f3
+                access: CS_AC_WRITE
+              -
+                type: PPC_OP_REG
+                reg: f3
+                access: CS_AC_READ
+      -
+        asm_text: "ps_res. f3, f3"
+        details:
+         ppc:
+            operands:
+              -
+                type: PPC_OP_REG
+                reg: f3
+                access: CS_AC_WRITE
+              -
+                type: PPC_OP_REG
+                reg: f3
+                access: CS_AC_READ
+      -
+        asm_text: "ps_rsqrte f3, f3"
+        details:
+         ppc:
+            operands:
+              -
+                type: PPC_OP_REG
+                reg: f3
+                access: CS_AC_WRITE
+              -
+                type: PPC_OP_REG
+                reg: f3
+                access: CS_AC_READ
+      -
+        asm_text: "ps_rsqrte. f3, f3"
+        details:
+         ppc:
+            operands:
+              -
+                type: PPC_OP_REG
+                reg: f3
+                access: CS_AC_WRITE
+              -
+                type: PPC_OP_REG
+                reg: f3
+                access: CS_AC_READ
+      -
+        asm_text: "ps_sel f3, f3, f4, f5"
+        details:
+         ppc:
+            operands:
+              -
+                type: PPC_OP_REG
+                reg: f3
+                access: CS_AC_WRITE
+              -
+                type: PPC_OP_REG
+                reg: f3
+                access: CS_AC_READ
+              -
+                type: PPC_OP_REG
+                reg: f4
+                access: CS_AC_READ
+              -
+                type: PPC_OP_REG
+                reg: f5
+                access: CS_AC_READ
+      -
+        asm_text: "ps_sel. f3, f3, f4, f5"
+        details:
+         ppc:
+            operands:
+              -
+                type: PPC_OP_REG
+                reg: f3
+                access: CS_AC_WRITE
+              -
+                type: PPC_OP_REG
+                reg: f3
+                access: CS_AC_READ
+              -
+                type: PPC_OP_REG
+                reg: f4
+                access: CS_AC_READ
+              -
+                type: PPC_OP_REG
+                reg: f5
+                access: CS_AC_READ
+      -
+        asm_text: "ps_sub f3, f3, f4"
+        details:
+         ppc:
+            operands:
+              -
+                type: PPC_OP_REG
+                reg: f3
+                access: CS_AC_WRITE
+              -
+                type: PPC_OP_REG
+                reg: f3
+                access: CS_AC_READ
+              -
+                type: PPC_OP_REG
+                reg: f4
+                access: CS_AC_READ
+      -
+        asm_text: "ps_sub. f3, f3, f4"
+        details:
+         ppc:
+            operands:
+              -
+                type: PPC_OP_REG
+                reg: f3
+                access: CS_AC_WRITE
+              -
+                type: PPC_OP_REG
+                reg: f3
+                access: CS_AC_READ
+              -
+                type: PPC_OP_REG
+                reg: f4
+                access: CS_AC_READ
+      -
+        asm_text: "ps_sum0 f3, f3, f4, f5"
+        details:
+         ppc:
+            operands:
+              -
+                type: PPC_OP_REG
+                reg: f3
+                access: CS_AC_WRITE
+              -
+                type: PPC_OP_REG
+                reg: f3
+                access: CS_AC_READ
+              -
+                type: PPC_OP_REG
+                reg: f4
+                access: CS_AC_READ
+              -
+                type: PPC_OP_REG
+                reg: f5
+                access: CS_AC_READ
+      -
+        asm_text: "ps_sum0. f3, f3, f4, f5"
+        details:
+         ppc:
+            operands:
+              -
+                type: PPC_OP_REG
+                reg: f3
+                access: CS_AC_WRITE
+              -
+                type: PPC_OP_REG
+                reg: f3
+                access: CS_AC_READ
+              -
+                type: PPC_OP_REG
+                reg: f4
+                access: CS_AC_READ
+              -
+                type: PPC_OP_REG
+                reg: f5
+                access: CS_AC_READ
+      -
+        asm_text: "ps_sum1 f3, f3, f4, f5"
+        details:
+         ppc:
+            operands:
+              -
+                type: PPC_OP_REG
+                reg: f3
+                access: CS_AC_WRITE
+              -
+                type: PPC_OP_REG
+                reg: f3
+                access: CS_AC_READ
+              -
+                type: PPC_OP_REG
+                reg: f4
+                access: CS_AC_READ
+              -
+                type: PPC_OP_REG
+                reg: f5
+                access: CS_AC_READ
+      -
+        asm_text: "ps_sum1. f3, f3, f4, f5"
+        details:
+         ppc:
+            operands:
+              -
+                type: PPC_OP_REG
+                reg: f3
+                access: CS_AC_WRITE
+              -
+                type: PPC_OP_REG
+                reg: f3
+                access: CS_AC_READ
+              -
+                type: PPC_OP_REG
+                reg: f4
+                access: CS_AC_READ
+              -
+                type: PPC_OP_REG
+                reg: f5
+                access: CS_AC_READ
+  -
+    input:
+      bytes: [ 0x54,0x22,0xe0,0x06 ]
+      arch: "CS_ARCH_PPC"
+      options: [ CS_MODE_32, CS_MODE_BIG_ENDIAN, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "slwi r2, r1, 0x1c"
+        details:
+          ppc:
+            operands:
+              -
+                type: PPC_OP_REG
+                reg: r2
+              -
+                type: PPC_OP_REG
+                reg: r1
+              -
+                type: PPC_OP_IMM
+                imm: 0x1c
+  -
+    input:
+      bytes: [ 0x54,0x66,0xf0,0xbe ]
+      arch: "CS_ARCH_PPC"
+      options: [ CS_MODE_32, CS_MODE_BIG_ENDIAN, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "srwi r6, r3, 2"
+        details:
+          ppc:
+            operands:
+              -
+                type: PPC_OP_REG
+                reg: r6
+              -
+                type: PPC_OP_REG
+                reg: r3
+              -
+                type: PPC_OP_IMM
+                imm: 0x2
+  -
+    input:
+      bytes: [ 0x78,0x62,0x26,0xe4 ]
+      arch: "CS_ARCH_PPC"
+      options: [ CS_MODE_32, CS_MODE_BIG_ENDIAN, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "sldi r2, r3, 4"
+        details:
+          ppc:
+            operands:
+              -
+                type: PPC_OP_REG
+                reg: r2
+              -
+                type: PPC_OP_REG
+                reg: r3
+              -
+                type: PPC_OP_IMM
+                imm: 0x4
diff --git a/tests/details/riscv.yaml b/tests/details/riscv.yaml
new file mode 100644
index 000000000..9bd6be20f
--- /dev/null
+++ b/tests/details/riscv.yaml
@@ -0,0 +1,4049 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x37, 0x34, 0x00, 0x00, 0x97, 0x82, 0x00, 0x00, 0xef, 0x00, 0x80, 0x00, 0xef, 0xf0, 0x1f, 0xff, 0xe7, 0x00, 0x45, 0x00, 0xe7, 0x00, 0xc0, 0xff, 0x63, 0x05, 0x41, 0x00, 0xe3, 0x9d, 0x61, 0xfe, 0x63, 0xca, 0x93, 0x00, 0x63, 0x53, 0xb5, 0x00, 0x63, 0x65, 0xd6, 0x00, 0x63, 0x76, 0xf7, 0x00, 0x03, 0x88, 0x18, 0x00, 0x03, 0x99, 0x49, 0x00, 0x03, 0xaa, 0x6a, 0x00, 0x03, 0xcb, 0x2b, 0x01, 0x03, 0xdc, 0x8c, 0x01, 0x23, 0x86, 0xad, 0x03, 0x23, 0x9a, 0xce, 0x03, 0x23, 0x8f, 0xef, 0x01, 0x93, 0x00, 0xe0, 0x00, 0x13, 0xa1, 0x01, 0x01, 0x13, 0xb2, 0x02, 0x7d, 0x13, 0xc3, 0x03, 0xdd, 0x13, 0xe4, 0xc4, 0x12, 0x13, 0xf5, 0x85, 0x0c, 0x13, 0x96, 0xe6, 0x01, 0x13, 0xd7, 0x97, 0x01, 0x13, 0xd8, 0xf8, 0x40, 0x33, 0x89, 0x49, 0x01, 0xb3, 0x0a, 0x7b, 0x41, 0x33, 0xac, 0xac, 0x01, 0xb3, 0x3d, 0xde, 0x01, 0x33, 0xd2, 0x62, 0x40, 0xb3, 0x43, 0x94, 0x00, 0x33, 0xe5, 0xc5, 0x00, 0xb3, 0x76, 0xf7, 0x00, 0xb3, 0x54, 0x39, 0x01, 0xb3, 0x50, 0x31, 0x00, 0x33, 0x9f, 0x0f, 0x00, 0x73, 0x15, 0x04, 0xb0, 0xf3, 0x56, 0x00, 0x10, 0x33, 0x05, 0x7b, 0x03, 0xb3, 0x45, 0x9c, 0x03, 0x33, 0x66, 0xbd, 0x03, 0x2f, 0xa4, 0x02, 0x10, 0xaf, 0x23, 0x65, 0x18, 0x2f, 0x27, 0x2f, 0x01, 0x43, 0xf0, 0x20, 0x18, 0xd3, 0x72, 0x73, 0x00, 0x53, 0xf4, 0x04, 0x58, 0x53, 0x85, 0xc5, 0x28, 0x53, 0x2e, 0xde, 0xa1, 0xd3, 0x84, 0x05, 0xf0, 0x53, 0x06, 0x05, 0xe0, 0x53, 0x75, 0x00, 0xc0, 0xd3, 0xf0, 0x05, 0xd0, 0xd3, 0x15, 0x08, 0xe0, 0x87, 0xaa, 0x75, 0x00, 0x27, 0x27, 0x66, 0x01, 0x43, 0xf0, 0x20, 0x1a, 0xd3, 0x72, 0x73, 0x02, 0x53, 0xf4, 0x04, 0x5a, 0x53, 0x85, 0xc5, 0x2a, 0x53, 0x2e, 0xde, 0xa3  ]
+      arch: "riscv"
+      options: [ CS_OPT_DETAIL, CS_MODE_RISCV32 ]
+      address: 0x1000
+    expected:
+      insns:
+      -
+        asm_text: "lui s0, 3"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: s0
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_IMM
+                imm: 0x3
+                access: CS_AC_READ
+      -
+        asm_text: "auipc t0, 8"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: t0
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_IMM
+                imm: 0x8
+                access: CS_AC_READ
+      -
+        asm_text: "jal 8"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_IMM
+                imm: 0x8
+                access: CS_AC_READ
+          groups: [ RISCV_GRP_CALL ]
+      -
+        asm_text: "jal -0x10"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_IMM
+                imm: -0x10
+                access: CS_AC_READ
+          groups: [ RISCV_GRP_CALL ]
+      -
+        asm_text: "jalr ra, a0, 4"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: ra
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: a0
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_IMM
+                imm: 0x4
+                access: CS_AC_READ
+          groups: [ RISCV_GRP_CALL ]
+      -
+        asm_text: "jalr ra, zero, -4"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: ra
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: zero
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_IMM
+                imm: -4
+                access: CS_AC_READ
+          groups: [ RISCV_GRP_CALL ]
+      -
+        asm_text: "beq sp, tp, 0xa"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: sp
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_REG
+                reg: tp
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_IMM
+                imm: 0xa
+                access: CS_AC_READ
+          groups: [ RISCV_GRP_BRANCH_RELATIVE, RISCV_GRP_JUMP ]
+      -
+        asm_text: "bne gp, t1, -6"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: gp
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_REG
+                reg: t1
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_IMM
+                imm: -6
+                access: CS_AC_READ
+          groups: [ RISCV_GRP_BRANCH_RELATIVE, RISCV_GRP_JUMP ]
+      -
+        asm_text: "blt t2, s1, 0x14"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: t2
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_REG
+                reg: s1
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_IMM
+                imm: 0x14
+                access: CS_AC_READ
+          groups: [ RISCV_GRP_BRANCH_RELATIVE, RISCV_GRP_JUMP ]
+      -
+        asm_text: "bge a0, a1, 6"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: a0
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_REG
+                reg: a1
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_IMM
+                imm: 0x6
+                access: CS_AC_READ
+          groups: [ RISCV_GRP_BRANCH_RELATIVE, RISCV_GRP_JUMP ]
+      -
+        asm_text: "bltu a2, a3, 0xa"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: a2
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_REG
+                reg: a3
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_IMM
+                imm: 0xa
+                access: CS_AC_READ
+          groups: [ RISCV_GRP_BRANCH_RELATIVE, RISCV_GRP_JUMP ]
+      -
+        asm_text: "bgeu a4, a5, 0xc"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: a4
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_REG
+                reg: a5
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_IMM
+                imm: 0xc
+                access: CS_AC_READ
+          groups: [ RISCV_GRP_BRANCH_RELATIVE, RISCV_GRP_JUMP ]
+      -
+        asm_text: "lb a6, 1(a7)"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: a6
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_MEM
+                mem_base: a7
+                mem_disp: 0x1
+                access: CS_AC_READ
+      -
+        asm_text: "lh s2, 4(s3)"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: s2
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_MEM
+                mem_base: s3
+                mem_disp: 0x4
+                access: CS_AC_READ
+      -
+        asm_text: "lw s4, 6(s5)"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: s4
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_MEM
+                mem_base: s5
+                mem_disp: 0x6
+                access: CS_AC_READ
+      -
+        asm_text: "lbu s6, 0x12(s7)"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: s6
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_MEM
+                mem_base: s7
+                mem_disp: 0x12
+                access: CS_AC_READ
+      -
+        asm_text: "lhu s8, 0x18(s9)"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: s8
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_MEM
+                mem_base: s9
+                mem_disp: 0x18
+                access: CS_AC_READ
+      -
+        asm_text: "sb s10, 0x2c(s11)"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: s10
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_MEM
+                mem_base: s11
+                mem_disp: 0x2c
+                access: CS_AC_WRITE
+      -
+        asm_text: "sh t3, 0x34(t4)"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: t3
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_MEM
+                mem_base: t4
+                mem_disp: 0x34
+                access: CS_AC_WRITE
+      -
+        asm_text: "sb t5, 0x1e(t6)"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: t5
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_MEM
+                mem_base: t6
+                mem_disp: 0x1e
+                access: CS_AC_WRITE
+      -
+        asm_text: "addi ra, zero, 0xe"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: ra
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: zero
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_IMM
+                imm: 0xe
+                access: CS_AC_READ
+      -
+        asm_text: "slti sp, gp, 0x10"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: sp
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: gp
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_IMM
+                imm: 0x10
+                access: CS_AC_READ
+      -
+        asm_text: "sltiu tp, t0, 0x7d0"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: tp
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: t0
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_IMM
+                imm: 0x7d0
+                access: CS_AC_READ
+      -
+        asm_text: "xori t1, t2, -0x230"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: t1
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: t2
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_IMM
+                imm: -0x230
+                access: CS_AC_READ
+      -
+        asm_text: "ori s0, s1, 0x12c"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: s0
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: s1
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_IMM
+                imm: 0x12c
+                access: CS_AC_READ
+      -
+        asm_text: "andi a0, a1, 0xc8"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: a0
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: a1
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_IMM
+                imm: 0xc8
+                access: CS_AC_READ
+      -
+        asm_text: "slli a2, a3, 0x1e"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: a2
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: a3
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_IMM
+                imm: 0x1e
+                access: CS_AC_READ
+      -
+        asm_text: "srli a4, a5, 0x19"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: a4
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: a5
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_IMM
+                imm: 0x19
+                access: CS_AC_READ
+      -
+        asm_text: "srai a6, a7, 0xf"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: a6
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: a7
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_IMM
+                imm: 0xf
+                access: CS_AC_READ
+      -
+        asm_text: "add s2, s3, s4"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: s2
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: s3
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_REG
+                reg: s4
+                access: CS_AC_READ
+      -
+        asm_text: "sub s5, s6, s7"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: s5
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: s6
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_REG
+                reg: s7
+                access: CS_AC_READ
+      -
+        asm_text: "slt s8, s9, s10"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: s8
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: s9
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_REG
+                reg: s10
+                access: CS_AC_READ
+      -
+        asm_text: "sltu s11, t3, t4"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: s11
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: t3
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_REG
+                reg: t4
+                access: CS_AC_READ
+      -
+        asm_text: "sra tp, t0, t1"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: tp
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: t0
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_REG
+                reg: t1
+                access: CS_AC_READ
+      -
+        asm_text: "xor t2, s0, s1"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: t2
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: s0
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_REG
+                reg: s1
+                access: CS_AC_READ
+      -
+        asm_text: "or a0, a1, a2"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: a0
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: a1
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_REG
+                reg: a2
+                access: CS_AC_READ
+      -
+        asm_text: "and a3, a4, a5"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: a3
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: a4
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_REG
+                reg: a5
+                access: CS_AC_READ
+      -
+        asm_text: "srl s1, s2, s3"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: s1
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: s2
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_REG
+                reg: s3
+                access: CS_AC_READ
+      -
+        asm_text: "srl ra, sp, gp"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: ra
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: sp
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_REG
+                reg: gp
+                access: CS_AC_READ
+      -
+        asm_text: "sll t5, t6, zero"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: t5
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: t6
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_REG
+                reg: zero
+                access: CS_AC_READ
+      -
+        asm_text: "csrrw a0, mcycle, s0"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: a0
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: s0
+                access: CS_AC_READ
+      -
+        asm_text: "csrrwi a3, sstatus, 0"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: a3
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_IMM
+                imm: 0x0
+                access: CS_AC_READ
+      -
+        asm_text: "mul a0, s6, s7"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: a0
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: s6
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_REG
+                reg: s7
+                access: CS_AC_READ
+          groups: [ RISCV_GRP_HASSTDEXTM ]
+      -
+        asm_text: "div a1, s8, s9"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: a1
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: s8
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_REG
+                reg: s9
+                access: CS_AC_READ
+          groups: [ RISCV_GRP_HASSTDEXTM ]
+      -
+        asm_text: "rem a2, s10, s11"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: a2
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: s10
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_REG
+                reg: s11
+                access: CS_AC_READ
+          groups: [ RISCV_GRP_HASSTDEXTM ]
+      -
+        asm_text: "lr.w s0, (t0)"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: s0
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_MEM
+                mem_base: t0
+                access: CS_AC_READ
+          groups: [ RISCV_GRP_HASSTDEXTA ]
+      -
+        asm_text: "sc.w t2, t1, (a0)"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: t2
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: t1
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_MEM
+                mem_base: a0
+                access: CS_AC_WRITE
+          groups: [ RISCV_GRP_HASSTDEXTA ]
+      -
+        asm_text: "amoadd.w a4, s2, (t5)"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: a4
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: s2
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_MEM
+                mem_base: t5
+                access: CS_AC_READ_WRITE
+          groups: [ RISCV_GRP_HASSTDEXTA ]
+      -
+        asm_text: "fmadd.s ft0, ft1, ft2, ft3"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: ft0
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: ft1
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_REG
+                reg: ft2
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_REG
+                reg: ft3
+                access: CS_AC_READ
+          groups: [ RISCV_GRP_HASSTDEXTF ]
+      -
+        asm_text: "fadd.s ft5, ft6, ft7"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: ft5
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: ft6
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_REG
+                reg: ft7
+                access: CS_AC_READ
+          groups: [ RISCV_GRP_HASSTDEXTF ]
+      -
+        asm_text: "fsqrt.s fs0, fs1"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: fs0
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: fs1
+                access: CS_AC_READ
+          groups: [ RISCV_GRP_HASSTDEXTF ]
+      -
+        asm_text: "fmin.s fa0, fa1, fa2"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: fa0
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: fa1
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_REG
+                reg: fa2
+                access: CS_AC_READ
+          groups: [ RISCV_GRP_HASSTDEXTF ]
+      -
+        asm_text: "feq.s t3, ft8, ft9"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: t3
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: ft8
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_REG
+                reg: ft9
+                access: CS_AC_READ
+          groups: [ RISCV_GRP_HASSTDEXTF ]
+      -
+        asm_text: "fmv.w.x fs1, a1"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: fs1
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: a1
+                access: CS_AC_READ
+          groups: [ RISCV_GRP_HASSTDEXTF ]
+      -
+        asm_text: "fmv.x.w a2, fa0"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: a2
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: fa0
+                access: CS_AC_READ
+          groups: [ RISCV_GRP_HASSTDEXTF ]
+      -
+        asm_text: "fcvt.w.s a0, ft0"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: a0
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: ft0
+                access: CS_AC_READ
+          groups: [ RISCV_GRP_HASSTDEXTF ]
+      -
+        asm_text: "fcvt.s.w ft1, a1"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: ft1
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: a1
+                access: CS_AC_READ
+          groups: [ RISCV_GRP_HASSTDEXTF ]
+      -
+        asm_text: "fclass.s a1, fa6"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: a1
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: fa6
+                access: CS_AC_READ
+          groups: [ RISCV_GRP_HASSTDEXTF ]
+      -
+        asm_text: "flw fs5, 7(a1)"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: fs5
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_MEM
+                mem_base: a1
+                mem_disp: 0x7
+                access: CS_AC_READ
+          groups: [ RISCV_GRP_HASSTDEXTF ]
+      -
+        asm_text: "fsw fs6, 0xe(a2)"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: fs6
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_MEM
+                mem_base: a2
+                mem_disp: 0xe
+                access: CS_AC_WRITE
+          groups: [ RISCV_GRP_HASSTDEXTF ]
+      -
+        asm_text: "fmadd.d ft0, ft1, ft2, ft3"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: ft0
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: ft1
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_REG
+                reg: ft2
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_REG
+                reg: ft3
+                access: CS_AC_READ
+          groups: [ RISCV_GRP_HASSTDEXTD ]
+      -
+        asm_text: "fadd.d ft5, ft6, ft7"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: ft5
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: ft6
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_REG
+                reg: ft7
+                access: CS_AC_READ
+          groups: [ RISCV_GRP_HASSTDEXTD ]
+      -
+        asm_text: "fsqrt.d fs0, fs1"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: fs0
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: fs1
+                access: CS_AC_READ
+          groups: [ RISCV_GRP_HASSTDEXTD ]
+      -
+        asm_text: "fmin.d fa0, fa1, fa2"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: fa0
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: fa1
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_REG
+                reg: fa2
+                access: CS_AC_READ
+          groups: [ RISCV_GRP_HASSTDEXTD ]
+      -
+        asm_text: "feq.d t3, ft8, ft9"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: t3
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: ft8
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_REG
+                reg: ft9
+                access: CS_AC_READ
+          groups: [ RISCV_GRP_HASSTDEXTD ]
+  -
+    input:
+      bytes: [ 0x13, 0x04, 0xa8, 0x7a, 0xbb, 0x07, 0x9c, 0x02, 0xbb, 0x40, 0x5d, 0x02, 0x3b, 0x63, 0xb7, 0x03, 0x2f, 0xb4, 0x02, 0x10, 0xaf, 0x33, 0x65, 0x18, 0x2f, 0x37, 0x2f, 0x01, 0x53, 0x75, 0x20, 0xc0, 0xd3, 0xf0, 0x25, 0xd0, 0xd3, 0x84, 0x05, 0xf2, 0x53, 0x06, 0x05, 0xe2, 0x53, 0x75, 0x00, 0xc2, 0xd3, 0x80, 0x05, 0xd2, 0xd3, 0x15, 0x08, 0xe2, 0x87, 0xba, 0x75, 0x00, 0x27, 0x37, 0x66, 0x01  ]
+      arch: "riscv"
+      options: [ CS_OPT_DETAIL, CS_MODE_RISCV64 ]
+      address: 0x1000
+    expected:
+      insns:
+      -
+        asm_text: "addi s0, a6, 0x7aa"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: s0
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: a6
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_IMM
+                imm: 0x7aa
+                access: CS_AC_READ
+      -
+        asm_text: "mulw a5, s8, s1"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: a5
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: s8
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_REG
+                reg: s1
+                access: CS_AC_READ
+          groups: [ RISCV_GRP_HASSTDEXTM, RISCV_GRP_ISRV64 ]
+      -
+        asm_text: "divw ra, s10, t0"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: ra
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: s10
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_REG
+                reg: t0
+                access: CS_AC_READ
+          groups: [ RISCV_GRP_HASSTDEXTM, RISCV_GRP_ISRV64 ]
+      -
+        asm_text: "remw t1, a4, s11"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: t1
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: a4
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_REG
+                reg: s11
+                access: CS_AC_READ
+          groups: [ RISCV_GRP_HASSTDEXTM, RISCV_GRP_ISRV64 ]
+      -
+        asm_text: "lr.d s0, (t0)"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: s0
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_MEM
+                mem_base: t0
+                access: CS_AC_READ
+          groups: [ RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64 ]
+      -
+        asm_text: "sc.d t2, t1, (a0)"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: t2
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: t1
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_MEM
+                mem_base: a0
+                access: CS_AC_WRITE
+          groups: [ RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64 ]
+      -
+        asm_text: "amoadd.d a4, s2, (t5)"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: a4
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: s2
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_MEM
+                mem_base: t5
+                access: CS_AC_READ_WRITE
+          groups: [ RISCV_GRP_HASSTDEXTA, RISCV_GRP_ISRV64 ]
+      -
+        asm_text: "fcvt.l.s a0, ft0"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: a0
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: ft0
+                access: CS_AC_READ
+          groups: [ RISCV_GRP_HASSTDEXTF, RISCV_GRP_ISRV64 ]
+      -
+        asm_text: "fcvt.s.l ft1, a1"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: ft1
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: a1
+                access: CS_AC_READ
+          groups: [ RISCV_GRP_HASSTDEXTF, RISCV_GRP_ISRV64 ]
+      -
+        asm_text: "fmv.d.x fs1, a1"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: fs1
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: a1
+                access: CS_AC_READ
+          groups: [ RISCV_GRP_HASSTDEXTD, RISCV_GRP_ISRV64 ]
+      -
+        asm_text: "fmv.x.d a2, fa0"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: a2
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: fa0
+                access: CS_AC_READ
+          groups: [ RISCV_GRP_HASSTDEXTD, RISCV_GRP_ISRV64 ]
+      -
+        asm_text: "fcvt.w.d a0, ft0"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: a0
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: ft0
+                access: CS_AC_READ
+          groups: [ RISCV_GRP_HASSTDEXTD ]
+      -
+        asm_text: "fcvt.d.w ft1, a1"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: ft1
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: a1
+                access: CS_AC_READ
+          groups: [ RISCV_GRP_HASSTDEXTD ]
+      -
+        asm_text: "fclass.d a1, fa6"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: a1
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: fa6
+                access: CS_AC_READ
+          groups: [ RISCV_GRP_HASSTDEXTD ]
+      -
+        asm_text: "fld fs5, 7(a1)"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: fs5
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_MEM
+                mem_base: a1
+                mem_disp: 0x7
+                access: CS_AC_READ
+          groups: [ RISCV_GRP_HASSTDEXTD ]
+      -
+        asm_text: "fsd fs6, 0xe(a2)"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: fs6
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_MEM
+                mem_base: a2
+                mem_disp: 0xe
+                access: CS_AC_WRITE
+          groups: [ RISCV_GRP_HASSTDEXTD ]
+  -
+    input:
+      bytes: [ 0xe8, 0x1f, 0x7d, 0x61, 0x80, 0x25, 0x00, 0x46, 0x88, 0xa2, 0x04, 0xcb, 0x55, 0x13, 0xf2, 0x93, 0x5d, 0x45, 0x19, 0x80, 0x15, 0x68, 0x2a, 0xa4, 0x62, 0x24, 0xa6, 0xff, 0x2a, 0x65, 0x76, 0x86, 0x65, 0xdd, 0x01, 0x00, 0xfd, 0xaf, 0x82, 0x82, 0x11, 0x20, 0x82, 0x94  ]
+      arch: "riscv"
+      options: [ CS_OPT_DETAIL, CS_MODE_RISCVC ]
+      address: 0x1000
+    expected:
+      insns:
+      -
+        asm_text: "c.addi4spn a0, sp, 0x3fc"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: a0
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: sp
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_IMM
+                imm: 0x3fc
+                access: CS_AC_READ
+          groups: [ RISCV_GRP_HASSTDEXTC ]
+      -
+        asm_text: "c.addi16sp sp, 0x1f0"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: sp
+                access: CS_AC_READ_WRITE
+              -
+                type: RISCV_OP_IMM
+                imm: 0x1f0
+                access: CS_AC_READ
+          groups: [ RISCV_GRP_HASSTDEXTC ]
+      -
+        asm_text: "c.fld fs0, 8(a1)"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: fs0
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_MEM
+                mem_base: a1
+                mem_disp: 0x8
+                access: CS_AC_READ
+          groups: [ RISCV_GRP_HASSTDEXTC, RISCV_GRP_HASSTDEXTD ]
+      -
+        asm_text: "c.lw s0, 8(a2)"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: s0
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_MEM
+                mem_base: a2
+                mem_disp: 0x8
+                access: CS_AC_READ
+          groups: [ RISCV_GRP_HASSTDEXTC ]
+      -
+        asm_text: "c.fsd fa0, 0(a3)"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: fa0
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_MEM
+                mem_base: a3
+                access: CS_AC_WRITE
+          groups: [ RISCV_GRP_HASSTDEXTC, RISCV_GRP_HASSTDEXTD ]
+      -
+        asm_text: "c.sw s1, 0x10(a4)"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: s1
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_MEM
+                mem_base: a4
+                mem_disp: 0x10
+                access: CS_AC_WRITE
+          groups: [ RISCV_GRP_HASSTDEXTC ]
+      -
+        asm_text: "c.addi t1, -0xb"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: t1
+                access: CS_AC_READ_WRITE
+              -
+                type: RISCV_OP_IMM
+                imm: -0xb
+                access: CS_AC_READ
+          groups: [ RISCV_GRP_HASSTDEXTC ]
+      -
+        asm_text: "c.add t2, t3"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: t2
+                access: CS_AC_READ_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: t3
+                access: CS_AC_READ
+          groups: [ RISCV_GRP_HASSTDEXTC ]
+      -
+        asm_text: "c.li a0, 0x17"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: a0
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_IMM
+                imm: 0x17
+                access: CS_AC_READ
+          groups: [ RISCV_GRP_HASSTDEXTC ]
+      -
+        asm_text: "c.srli s0, 6"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: s0
+                access: CS_AC_READ_WRITE
+              -
+                type: RISCV_OP_IMM
+                imm: 0x6
+                access: CS_AC_READ
+          groups: [ RISCV_GRP_HASSTDEXTC ]
+      -
+        asm_text: "c.lui a6, 5"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: a6
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_IMM
+                imm: 0x5
+                access: CS_AC_READ
+          groups: [ RISCV_GRP_HASSTDEXTC ]
+      -
+        asm_text: "c.fsdsp fa0, 8(sp)"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: fa0
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_MEM
+                mem_base: sp
+                mem_disp: 0x8
+                access: CS_AC_WRITE
+          groups: [ RISCV_GRP_HASSTDEXTC, RISCV_GRP_HASSTDEXTD ]
+      -
+        asm_text: "c.fldsp fs0, 0x18(sp)"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: fs0
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_MEM
+                mem_base: sp
+                mem_disp: 0x18
+                access: CS_AC_READ
+          groups: [ RISCV_GRP_HASSTDEXTC, RISCV_GRP_HASSTDEXTD ]
+      -
+        asm_text: "c.fswsp fs1, 0xfc(sp)"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: fs1
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_IMM
+                imm: 0xfc
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_REG
+                reg: sp
+                access: CS_AC_WRITE
+          groups: [ RISCV_GRP_HASSTDEXTC, RISCV_GRP_HASSTDEXTF, RISCV_GRP_ISRV32 ]
+      -
+        asm_text: "c.flwsp fa0, 0x88(sp)"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: fa0
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_IMM
+                imm: 0x88
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_REG
+                reg: sp
+                access: CS_AC_READ
+          groups: [ RISCV_GRP_HASSTDEXTC, RISCV_GRP_HASSTDEXTF, RISCV_GRP_ISRV32 ]
+      -
+        asm_text: "c.mv a2, t4"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: a2
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: t4
+                access: CS_AC_READ
+          groups: [ RISCV_GRP_HASSTDEXTC ]
+      -
+        asm_text: "c.beqz a0, -8"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: a0
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_IMM
+                imm: -8
+                access: CS_AC_READ
+          groups: [ RISCV_GRP_HASSTDEXTC, RISCV_GRP_BRANCH_RELATIVE, RISCV_GRP_JUMP ]
+      -
+        asm_text: "c.nop"
+        details:
+          groups: [ RISCV_GRP_HASSTDEXTC ]
+      -
+        asm_text: "c.j 0x7fe"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_IMM
+                imm: 0x7fe
+                access: CS_AC_READ
+          groups: [ RISCV_GRP_HASSTDEXTC, RISCV_GRP_JUMP ]
+      -
+        asm_text: "c.jr t0"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: t0
+                access: CS_AC_READ
+          groups: [ RISCV_GRP_HASSTDEXTC, RISCV_GRP_JUMP ]
+      -
+        asm_text: "c.jal 4"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_IMM
+                imm: 0x4
+                access: CS_AC_READ
+          groups: [ RISCV_GRP_HASSTDEXTC, RISCV_GRP_ISRV32, RISCV_GRP_CALL ]
+      -
+        asm_text: "c.jalr s1"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: s1
+                access: CS_AC_READ
+          groups: [ RISCV_GRP_HASSTDEXTC, RISCV_GRP_CALL ]
+  -
+    input:
+      bytes: [ 0x37,0x34,0x00,0x00 ]
+      arch: "CS_ARCH_RISCV"
+      options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "lui s0, 3"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: s0
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_IMM
+                imm: 0x3
+                access: CS_AC_READ
+  -
+    input:
+      bytes: [ 0x97,0x82,0x00,0x00 ]
+      arch: "CS_ARCH_RISCV"
+      options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "auipc t0, 8"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: t0
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_IMM
+                imm: 0x8
+                access: CS_AC_READ
+  -
+    input:
+      bytes: [ 0xef,0x00,0x80,0x00 ]
+      arch: "CS_ARCH_RISCV"
+      options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "jal 8"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_IMM
+                imm: 0x8
+                access: CS_AC_READ
+          groups: [ call ]
+  -
+    input:
+      bytes: [ 0xef,0xf0,0x1f,0xff ]
+      arch: "CS_ARCH_RISCV"
+      options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "jal -0x10"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_IMM
+                imm: -0x10
+                access: CS_AC_READ
+          groups: [ call ]
+  -
+    input:
+      bytes: [ 0xe7,0x00,0x45,0x00 ]
+      arch: "CS_ARCH_RISCV"
+      options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "jalr ra, a0, 4"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: ra
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: a0
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_IMM
+                imm: 0x4
+                access: CS_AC_READ
+          groups: [ call ]
+  -
+    input:
+      bytes: [ 0xe7,0x00,0xc0,0xff ]
+      arch: "CS_ARCH_RISCV"
+      options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "jalr ra, zero, -4"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: ra
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: zero
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_IMM
+                imm: -4
+                access: CS_AC_READ
+          groups: [ call ]
+  -
+    input:
+      bytes: [ 0x63,0x05,0x41,0x00 ]
+      arch: "CS_ARCH_RISCV"
+      options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "beq sp, tp, 0xa"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: sp
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_REG
+                reg: tp
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_IMM
+                imm: 0xa
+                access: CS_AC_READ
+          groups: [ branch_relative, jump ]
+  -
+    input:
+      bytes: [ 0xe3,0x9d,0x61,0xfe ]
+      arch: "CS_ARCH_RISCV"
+      options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "bne gp, t1, -6"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: gp
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_REG
+                reg: t1
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_IMM
+                imm: -6
+                access: CS_AC_READ
+          groups: [ branch_relative, jump ]
+  -
+    input:
+      bytes: [ 0x63,0xca,0x93,0x00 ]
+      arch: "CS_ARCH_RISCV"
+      options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "blt t2, s1, 0x14"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: t2
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_REG
+                reg: s1
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_IMM
+                imm: 0x14
+                access: CS_AC_READ
+          groups: [ branch_relative, jump ]
+  -
+    input:
+      bytes: [ 0x63,0x53,0xb5,0x00 ]
+      arch: "CS_ARCH_RISCV"
+      options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "bge a0, a1, 6"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: a0
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_REG
+                reg: a1
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_IMM
+                imm: 0x6
+                access: CS_AC_READ
+          groups: [ branch_relative, jump ]
+  -
+    input:
+      bytes: [ 0x63,0x65,0xd6,0x00 ]
+      arch: "CS_ARCH_RISCV"
+      options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "bltu a2, a3, 0xa"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: a2
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_REG
+                reg: a3
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_IMM
+                imm: 0xa
+                access: CS_AC_READ
+          groups: [ branch_relative, jump ]
+  -
+    input:
+      bytes: [ 0x63,0x76,0xf7,0x00 ]
+      arch: "CS_ARCH_RISCV"
+      options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "bgeu a4, a5, 0xc"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: a4
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_REG
+                reg: a5
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_IMM
+                imm: 0xc
+                access: CS_AC_READ
+          groups: [ branch_relative, jump ]
+  -
+    input:
+      bytes: [ 0x03,0x88,0x18,0x00 ]
+      arch: "CS_ARCH_RISCV"
+      options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "lb a6, 1(a7)"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: a6
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_MEM
+                mem_base: a7
+                mem_disp: 0x1
+                access: CS_AC_READ
+  -
+    input:
+      bytes: [ 0x03,0x99,0x49,0x00 ]
+      arch: "CS_ARCH_RISCV"
+      options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "lh s2, 4(s3)"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: s2
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_MEM
+                mem_base: s3
+                mem_disp: 0x4
+                access: CS_AC_READ
+  -
+    input:
+      bytes: [ 0x03,0xaa,0x6a,0x00 ]
+      arch: "CS_ARCH_RISCV"
+      options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "lw s4, 6(s5)"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: s4
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_MEM
+                mem_base: s5
+                mem_disp: 0x6
+                access: CS_AC_READ
+  -
+    input:
+      bytes: [ 0x03,0xcb,0x2b,0x01 ]
+      arch: "CS_ARCH_RISCV"
+      options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "lbu s6, 0x12(s7)"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: s6
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_MEM
+                mem_base: s7
+                mem_disp: 0x12
+                access: CS_AC_READ
+  -
+    input:
+      bytes: [ 0x03,0xdc,0x8c,0x01 ]
+      arch: "CS_ARCH_RISCV"
+      options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "lhu s8, 0x18(s9)"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: s8
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_MEM
+                mem_base: s9
+                mem_disp: 0x18
+                access: CS_AC_READ
+  -
+    input:
+      bytes: [ 0x23,0x86,0xad,0x03 ]
+      arch: "CS_ARCH_RISCV"
+      options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "sb s10, 0x2c(s11)"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: s10
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_MEM
+                mem_base: s11
+                mem_disp: 0x2c
+                access: CS_AC_WRITE
+  -
+    input:
+      bytes: [ 0x23,0x9a,0xce,0x03 ]
+      arch: "CS_ARCH_RISCV"
+      options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "sh t3, 0x34(t4)"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: t3
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_MEM
+                mem_base: t4
+                mem_disp: 0x34
+                access: CS_AC_WRITE
+  -
+    input:
+      bytes: [ 0x23,0x8f,0xef,0x01 ]
+      arch: "CS_ARCH_RISCV"
+      options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "sb t5, 0x1e(t6)"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: t5
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_MEM
+                mem_base: t6
+                mem_disp: 0x1e
+                access: CS_AC_WRITE
+  -
+    input:
+      bytes: [ 0x93,0x00,0xe0,0x00 ]
+      arch: "CS_ARCH_RISCV"
+      options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "addi ra, zero, 0xe"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: ra
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: zero
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_IMM
+                imm: 0xe
+                access: CS_AC_READ
+  -
+    input:
+      bytes: [ 0x13,0xa1,0x01,0x01 ]
+      arch: "CS_ARCH_RISCV"
+      options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "slti sp, gp, 0x10"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: sp
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: gp
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_IMM
+                imm: 0x10
+                access: CS_AC_READ
+  -
+    input:
+      bytes: [ 0x13,0xb2,0x02,0x7d ]
+      arch: "CS_ARCH_RISCV"
+      options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "sltiu tp, t0, 0x7d0"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: tp
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: t0
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_IMM
+                imm: 0x7d0
+                access: CS_AC_READ
+  -
+    input:
+      bytes: [ 0x13,0xc3,0x03,0xdd ]
+      arch: "CS_ARCH_RISCV"
+      options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "xori t1, t2, -0x230"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: t1
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: t2
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_IMM
+                imm: -0x230
+                access: CS_AC_READ
+  -
+    input:
+      bytes: [ 0x13,0xe4,0xc4,0x12 ]
+      arch: "CS_ARCH_RISCV"
+      options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "ori s0, s1, 0x12c"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: s0
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: s1
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_IMM
+                imm: 0x12c
+                access: CS_AC_READ
+  -
+    input:
+      bytes: [ 0x13,0xf5,0x85,0x0c ]
+      arch: "CS_ARCH_RISCV"
+      options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "andi a0, a1, 0xc8"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: a0
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: a1
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_IMM
+                imm: 0xc8
+                access: CS_AC_READ
+  -
+    input:
+      bytes: [ 0x13,0x96,0xe6,0x01 ]
+      arch: "CS_ARCH_RISCV"
+      options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "slli a2, a3, 0x1e"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: a2
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: a3
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_IMM
+                imm: 0x1e
+                access: CS_AC_READ
+  -
+    input:
+      bytes: [ 0x13,0xd7,0x97,0x01 ]
+      arch: "CS_ARCH_RISCV"
+      options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "srli a4, a5, 0x19"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: a4
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: a5
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_IMM
+                imm: 0x19
+                access: CS_AC_READ
+  -
+    input:
+      bytes: [ 0x13,0xd8,0xf8,0x40 ]
+      arch: "CS_ARCH_RISCV"
+      options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "srai a6, a7, 0xf"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: a6
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: a7
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_IMM
+                imm: 0xf
+                access: CS_AC_READ
+  -
+    input:
+      bytes: [ 0x33,0x89,0x49,0x01 ]
+      arch: "CS_ARCH_RISCV"
+      options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "add s2, s3, s4"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: s2
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: s3
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_REG
+                reg: s4
+                access: CS_AC_READ
+  -
+    input:
+      bytes: [ 0xb3,0x0a,0x7b,0x41 ]
+      arch: "CS_ARCH_RISCV"
+      options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "sub s5, s6, s7"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: s5
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: s6
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_REG
+                reg: s7
+                access: CS_AC_READ
+  -
+    input:
+      bytes: [ 0x33,0xac,0xac,0x01 ]
+      arch: "CS_ARCH_RISCV"
+      options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "slt s8, s9, s10"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: s8
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: s9
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_REG
+                reg: s10
+                access: CS_AC_READ
+  -
+    input:
+      bytes: [ 0xb3,0x3d,0xde,0x01 ]
+      arch: "CS_ARCH_RISCV"
+      options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "sltu s11, t3, t4"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: s11
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: t3
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_REG
+                reg: t4
+                access: CS_AC_READ
+  -
+    input:
+      bytes: [ 0x33,0xd2,0x62,0x40 ]
+      arch: "CS_ARCH_RISCV"
+      options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "sra tp, t0, t1"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: tp
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: t0
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_REG
+                reg: t1
+                access: CS_AC_READ
+  -
+    input:
+      bytes: [ 0xb3,0x43,0x94,0x00 ]
+      arch: "CS_ARCH_RISCV"
+      options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "xor t2, s0, s1"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: t2
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: s0
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_REG
+                reg: s1
+                access: CS_AC_READ
+  -
+    input:
+      bytes: [ 0x33,0xe5,0xc5,0x00 ]
+      arch: "CS_ARCH_RISCV"
+      options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "or a0, a1, a2"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: a0
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: a1
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_REG
+                reg: a2
+                access: CS_AC_READ
+  -
+    input:
+      bytes: [ 0xb3,0x76,0xf7,0x00 ]
+      arch: "CS_ARCH_RISCV"
+      options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "and a3, a4, a5"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: a3
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: a4
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_REG
+                reg: a5
+                access: CS_AC_READ
+  -
+    input:
+      bytes: [ 0xb3,0x54,0x39,0x01 ]
+      arch: "CS_ARCH_RISCV"
+      options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "srl s1, s2, s3"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: s1
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: s2
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_REG
+                reg: s3
+                access: CS_AC_READ
+  -
+    input:
+      bytes: [ 0xb3,0x50,0x31,0x00 ]
+      arch: "CS_ARCH_RISCV"
+      options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "srl ra, sp, gp"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: ra
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: sp
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_REG
+                reg: gp
+                access: CS_AC_READ
+  -
+    input:
+      bytes: [ 0x33,0x9f,0x0f,0x00 ]
+      arch: "CS_ARCH_RISCV"
+      options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "sll t5, t6, zero"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: t5
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: t6
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_REG
+                reg: zero
+                access: CS_AC_READ
+  -
+    input:
+      bytes: [ 0x73,0x15,0x04,0xb0 ]
+      arch: "CS_ARCH_RISCV"
+      options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "csrrw a0, mcycle, s0"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: a0
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: s0
+                access: CS_AC_READ
+  -
+    input:
+      bytes: [ 0xf3,0x56,0x00,0x10 ]
+      arch: "CS_ARCH_RISCV"
+      options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "csrrwi a3, sstatus, 0"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: a3
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_IMM
+                imm: 0x0
+                access: CS_AC_READ
+  -
+    input:
+      bytes: [ 0x33,0x05,0x7b,0x03 ]
+      arch: "CS_ARCH_RISCV"
+      options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "mul a0, s6, s7"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: a0
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: s6
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_REG
+                reg: s7
+                access: CS_AC_READ
+          groups: [ hasStdExtM ]
+  -
+    input:
+      bytes: [ 0xb3,0x45,0x9c,0x03 ]
+      arch: "CS_ARCH_RISCV"
+      options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "div a1, s8, s9"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: a1
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: s8
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_REG
+                reg: s9
+                access: CS_AC_READ
+          groups: [ hasStdExtM ]
+  -
+    input:
+      bytes: [ 0x33,0x66,0xbd,0x03 ]
+      arch: "CS_ARCH_RISCV"
+      options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "rem a2, s10, s11"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: a2
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: s10
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_REG
+                reg: s11
+                access: CS_AC_READ
+          groups: [ hasStdExtM ]
+  -
+    input:
+      bytes: [ 0x2f,0xa4,0x02,0x10 ]
+      arch: "CS_ARCH_RISCV"
+      options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "lr.w s0, (t0)"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: s0
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_MEM
+                mem_base: t0
+                access: CS_AC_READ
+          groups: [ hasStdExtA ]
+  -
+    input:
+      bytes: [ 0xaf,0x23,0x65,0x18 ]
+      arch: "CS_ARCH_RISCV"
+      options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "sc.w t2, t1, (a0)"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: t2
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: t1
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_MEM
+                mem_base: a0
+                access: CS_AC_WRITE
+          groups: [ hasStdExtA ]
+  -
+    input:
+      bytes: [ 0x2f,0x27,0x2f,0x01 ]
+      arch: "CS_ARCH_RISCV"
+      options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "amoadd.w a4, s2, (t5)"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: a4
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: s2
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_MEM
+                mem_base: t5
+                access: CS_AC_READ_WRITE
+          groups: [ hasStdExtA ]
+  -
+    input:
+      bytes: [ 0x43,0xf0,0x20,0x18 ]
+      arch: "CS_ARCH_RISCV"
+      options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "fmadd.s ft0, ft1, ft2, ft3"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: ft0
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: ft1
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_REG
+                reg: ft2
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_REG
+                reg: ft3
+                access: CS_AC_READ
+          groups: [ hasStdExtF ]
+  -
+    input:
+      bytes: [ 0xd3,0x72,0x73,0x00 ]
+      arch: "CS_ARCH_RISCV"
+      options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "fadd.s ft5, ft6, ft7"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: ft5
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: ft6
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_REG
+                reg: ft7
+                access: CS_AC_READ
+          groups: [ hasStdExtF ]
+  -
+    input:
+      bytes: [ 0x53,0xf4,0x04,0x58 ]
+      arch: "CS_ARCH_RISCV"
+      options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "fsqrt.s fs0, fs1"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: fs0
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: fs1
+                access: CS_AC_READ
+          groups: [ hasStdExtF ]
+  -
+    input:
+      bytes: [ 0x53,0x85,0xc5,0x28 ]
+      arch: "CS_ARCH_RISCV"
+      options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "fmin.s fa0, fa1, fa2"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: fa0
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: fa1
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_REG
+                reg: fa2
+                access: CS_AC_READ
+          groups: [ hasStdExtF ]
+  -
+    input:
+      bytes: [ 0x53,0x2e,0xde,0xa1 ]
+      arch: "CS_ARCH_RISCV"
+      options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "feq.s t3, ft8, ft9"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: t3
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: ft8
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_REG
+                reg: ft9
+                access: CS_AC_READ
+          groups: [ hasStdExtF ]
+  -
+    input:
+      bytes: [ 0xd3,0x84,0x05,0xf0 ]
+      arch: "CS_ARCH_RISCV"
+      options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "fmv.w.x fs1, a1"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: fs1
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: a1
+                access: CS_AC_READ
+          groups: [ hasStdExtF ]
+  -
+    input:
+      bytes: [ 0x53,0x06,0x05,0xe0 ]
+      arch: "CS_ARCH_RISCV"
+      options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "fmv.x.w a2, fa0"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: a2
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: fa0
+                access: CS_AC_READ
+          groups: [ hasStdExtF ]
+  -
+    input:
+      bytes: [ 0x53,0x75,0x00,0xc0 ]
+      arch: "CS_ARCH_RISCV"
+      options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "fcvt.w.s a0, ft0"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: a0
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: ft0
+                access: CS_AC_READ
+          groups: [ hasStdExtF ]
+  -
+    input:
+      bytes: [ 0xd3,0xf0,0x05,0xd0 ]
+      arch: "CS_ARCH_RISCV"
+      options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "fcvt.s.w ft1, a1"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: ft1
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: a1
+                access: CS_AC_READ
+          groups: [ hasStdExtF ]
+  -
+    input:
+      bytes: [ 0xd3,0x15,0x08,0xe0 ]
+      arch: "CS_ARCH_RISCV"
+      options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "fclass.s a1, fa6"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: a1
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: fa6
+                access: CS_AC_READ
+          groups: [ hasStdExtF ]
+  -
+    input:
+      bytes: [ 0x87,0xaa,0x75,0x00 ]
+      arch: "CS_ARCH_RISCV"
+      options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "flw fs5, 7(a1)"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: fs5
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_MEM
+                mem_base: a1
+                mem_disp: 0x7
+                access: CS_AC_READ
+          groups: [ hasStdExtF ]
+  -
+    input:
+      bytes: [ 0x27,0x27,0x66,0x01 ]
+      arch: "CS_ARCH_RISCV"
+      options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "fsw fs6, 0xe(a2)"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: fs6
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_MEM
+                mem_base: a2
+                mem_disp: 0xe
+                access: CS_AC_WRITE
+          groups: [ hasStdExtF ]
+  -
+    input:
+      bytes: [ 0x43,0xf0,0x20,0x1a ]
+      arch: "CS_ARCH_RISCV"
+      options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "fmadd.d ft0, ft1, ft2, ft3"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: ft0
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: ft1
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_REG
+                reg: ft2
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_REG
+                reg: ft3
+                access: CS_AC_READ
+          groups: [ hasStdExtD ]
+  -
+    input:
+      bytes: [ 0xd3,0x72,0x73,0x02 ]
+      arch: "CS_ARCH_RISCV"
+      options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "fadd.d ft5, ft6, ft7"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: ft5
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: ft6
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_REG
+                reg: ft7
+                access: CS_AC_READ
+          groups: [ hasStdExtD ]
+  -
+    input:
+      bytes: [ 0x53,0xf4,0x04,0x5a ]
+      arch: "CS_ARCH_RISCV"
+      options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "fsqrt.d fs0, fs1"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: fs0
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: fs1
+                access: CS_AC_READ
+          groups: [ hasStdExtD ]
+  -
+    input:
+      bytes: [ 0x53,0x85,0xc5,0x2a ]
+      arch: "CS_ARCH_RISCV"
+      options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "fmin.d fa0, fa1, fa2"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: fa0
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: fa1
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_REG
+                reg: fa2
+                access: CS_AC_READ
+          groups: [ hasStdExtD ]
+  -
+    input:
+      bytes: [ 0x53,0x2e,0xde,0xa3 ]
+      arch: "CS_ARCH_RISCV"
+      options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "feq.d t3, ft8, ft9"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: t3
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: ft8
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_REG
+                reg: ft9
+                access: CS_AC_READ
+          groups: [ hasStdExtD ]
+  -
+    input:
+      bytes: [ 0x13,0x04,0xa8,0x7a ]
+      arch: "CS_ARCH_RISCV"
+      options: [ CS_MODE_RISCV64, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "addi s0, a6, 0x7aa"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: s0
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: a6
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_IMM
+                imm: 0x7aa
+                access: CS_AC_READ
+  -
+    input:
+      bytes: [ 0xbb,0x07,0x9c,0x02 ]
+      arch: "CS_ARCH_RISCV"
+      options: [ CS_MODE_RISCV64, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "mulw a5, s8, s1"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: a5
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: s8
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_REG
+                reg: s1
+                access: CS_AC_READ
+          groups: [ hasStdExtM, isrv64 ]
+  -
+    input:
+      bytes: [ 0xbb,0x40,0x5d,0x02 ]
+      arch: "CS_ARCH_RISCV"
+      options: [ CS_MODE_RISCV64, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "divw ra, s10, t0"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: ra
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: s10
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_REG
+                reg: t0
+                access: CS_AC_READ
+          groups: [ hasStdExtM, isrv64 ]
+  -
+    input:
+      bytes: [ 0x3b,0x63,0xb7,0x03 ]
+      arch: "CS_ARCH_RISCV"
+      options: [ CS_MODE_RISCV64, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "remw t1, a4, s11"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: t1
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: a4
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_REG
+                reg: s11
+                access: CS_AC_READ
+          groups: [ hasStdExtM, isrv64 ]
+  -
+    input:
+      bytes: [ 0x2f,0xb4,0x02,0x10 ]
+      arch: "CS_ARCH_RISCV"
+      options: [ CS_MODE_RISCV64, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "lr.d s0, (t0)"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: s0
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_MEM
+                mem_base: t0
+                access: CS_AC_READ
+          groups: [ hasStdExtA, isrv64 ]
+  -
+    input:
+      bytes: [ 0xaf,0x33,0x65,0x18 ]
+      arch: "CS_ARCH_RISCV"
+      options: [ CS_MODE_RISCV64, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "sc.d t2, t1, (a0)"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: t2
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: t1
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_MEM
+                mem_base: a0
+                access: CS_AC_WRITE
+          groups: [ hasStdExtA, isrv64 ]
+  -
+    input:
+      bytes: [ 0x2f,0x37,0x2f,0x01 ]
+      arch: "CS_ARCH_RISCV"
+      options: [ CS_MODE_RISCV64, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "amoadd.d a4, s2, (t5)"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: a4
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: s2
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_MEM
+                mem_base: t5
+                access: CS_AC_READ_WRITE
+          groups: [ hasStdExtA, isrv64 ]
+  -
+    input:
+      bytes: [ 0x53,0x75,0x20,0xc0 ]
+      arch: "CS_ARCH_RISCV"
+      options: [ CS_MODE_RISCV64, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "fcvt.l.s a0, ft0"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: a0
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: ft0
+                access: CS_AC_READ
+          groups: [ hasStdExtF, isrv64 ]
+  -
+    input:
+      bytes: [ 0xd3,0xf0,0x25,0xd0 ]
+      arch: "CS_ARCH_RISCV"
+      options: [ CS_MODE_RISCV64, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "fcvt.s.l ft1, a1"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: ft1
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: a1
+                access: CS_AC_READ
+          groups: [ hasStdExtF, isrv64 ]
+  -
+    input:
+      bytes: [ 0xd3,0x84,0x05,0xf2 ]
+      arch: "CS_ARCH_RISCV"
+      options: [ CS_MODE_RISCV64, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "fmv.d.x fs1, a1"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: fs1
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: a1
+                access: CS_AC_READ
+          groups: [ hasStdExtD, isrv64 ]
+  -
+    input:
+      bytes: [ 0x53,0x06,0x05,0xe2 ]
+      arch: "CS_ARCH_RISCV"
+      options: [ CS_MODE_RISCV64, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "fmv.x.d a2, fa0"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: a2
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: fa0
+                access: CS_AC_READ
+          groups: [ hasStdExtD, isrv64 ]
+  -
+    input:
+      bytes: [ 0x53,0x75,0x00,0xc2 ]
+      arch: "CS_ARCH_RISCV"
+      options: [ CS_MODE_RISCV64, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "fcvt.w.d a0, ft0"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: a0
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: ft0
+                access: CS_AC_READ
+          groups: [ hasStdExtD ]
+  -
+    input:
+      bytes: [ 0xd3,0x80,0x05,0xd2 ]
+      arch: "CS_ARCH_RISCV"
+      options: [ CS_MODE_RISCV64, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "fcvt.d.w ft1, a1"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: ft1
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: a1
+                access: CS_AC_READ
+          groups: [ hasStdExtD ]
+  -
+    input:
+      bytes: [ 0xd3,0x15,0x08,0xe2 ]
+      arch: "CS_ARCH_RISCV"
+      options: [ CS_MODE_RISCV64, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "fclass.d a1, fa6"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: a1
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: fa6
+                access: CS_AC_READ
+          groups: [ hasStdExtD ]
+  -
+    input:
+      bytes: [ 0x87,0xba,0x75,0x00 ]
+      arch: "CS_ARCH_RISCV"
+      options: [ CS_MODE_RISCV64, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "fld fs5, 7(a1)"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: fs5
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_MEM
+                mem_base: a1
+                mem_disp: 0x7
+                access: CS_AC_READ
+          groups: [ hasStdExtD ]
+  -
+    input:
+      bytes: [ 0x27,0x37,0x66,0x01 ]
+      arch: "CS_ARCH_RISCV"
+      options: [ CS_MODE_RISCV64, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "fsd fs6, 0xe(a2)"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: fs6
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_MEM
+                mem_base: a2
+                mem_disp: 0xe
+                access: CS_AC_WRITE
+          groups: [ hasStdExtD ]
+  -
+    input:
+      bytes: [ 0xe8,0x1f ]
+      arch: "CS_ARCH_RISCV"
+      options: [ CS_MODE_RISCVC, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "c.addi4spn a0, sp, 0x3fc"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: a0
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: sp
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_IMM
+                imm: 0x3fc
+                access: CS_AC_READ
+          groups: [ hasStdExtC ]
+  -
+    input:
+      bytes: [ 0x7d,0x61 ]
+      arch: "CS_ARCH_RISCV"
+      options: [ CS_MODE_RISCVC, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "c.addi16sp sp, 0x1f0"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: sp
+                access: CS_AC_READ_WRITE
+              -
+                type: RISCV_OP_IMM
+                imm: 0x1f0
+                access: CS_AC_READ
+          groups: [ hasStdExtC ]
+  -
+    input:
+      bytes: [ 0x80,0x25 ]
+      arch: "CS_ARCH_RISCV"
+      options: [ CS_MODE_RISCVC, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "c.fld fs0, 8(a1)"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: fs0
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_MEM
+                mem_base: a1
+                mem_disp: 0x8
+                access: CS_AC_READ
+          groups: [ hasStdExtC, hasStdExtD ]
+  -
+    input:
+      bytes: [ 0x00,0x46 ]
+      arch: "CS_ARCH_RISCV"
+      options: [ CS_MODE_RISCVC, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "c.lw s0, 8(a2)"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: s0
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_MEM
+                mem_base: a2
+                mem_disp: 0x8
+                access: CS_AC_READ
+          groups: [ hasStdExtC ]
+  -
+    input:
+      bytes: [ 0x88,0xa2 ]
+      arch: "CS_ARCH_RISCV"
+      options: [ CS_MODE_RISCVC, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "c.fsd fa0, 0(a3)"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: fa0
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_MEM
+                mem_base: a3
+                access: CS_AC_WRITE
+          groups: [ hasStdExtC, hasStdExtD ]
+  -
+    input:
+      bytes: [ 0x04,0xcb ]
+      arch: "CS_ARCH_RISCV"
+      options: [ CS_MODE_RISCVC, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "c.sw s1, 0x10(a4)"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: s1
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_MEM
+                mem_base: a4
+                mem_disp: 0x10
+                access: CS_AC_WRITE
+          groups: [ hasStdExtC ]
+  -
+    input:
+      bytes: [ 0x55,0x13 ]
+      arch: "CS_ARCH_RISCV"
+      options: [ CS_MODE_RISCVC, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "c.addi t1, -0xb"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: t1
+                access: CS_AC_READ_WRITE
+              -
+                type: RISCV_OP_IMM
+                imm: -0xb
+                access: CS_AC_READ
+          groups: [ hasStdExtC ]
+  -
+    input:
+      bytes: [ 0xf2,0x93 ]
+      arch: "CS_ARCH_RISCV"
+      options: [ CS_MODE_RISCVC, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "c.add t2, t3"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: t2
+                access: CS_AC_READ_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: t3
+                access: CS_AC_READ
+          groups: [ hasStdExtC ]
+  -
+    input:
+      bytes: [ 0x5d,0x45 ]
+      arch: "CS_ARCH_RISCV"
+      options: [ CS_MODE_RISCVC, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "c.li a0, 0x17"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: a0
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_IMM
+                imm: 0x17
+                access: CS_AC_READ
+          groups: [ hasStdExtC ]
+  -
+    input:
+      bytes: [ 0x19,0x80 ]
+      arch: "CS_ARCH_RISCV"
+      options: [ CS_MODE_RISCVC, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "c.srli s0, 6"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: s0
+                access: CS_AC_READ_WRITE
+              -
+                type: RISCV_OP_IMM
+                imm: 0x6
+                access: CS_AC_READ
+          groups: [ hasStdExtC ]
+  -
+    input:
+      bytes: [ 0x15,0x68 ]
+      arch: "CS_ARCH_RISCV"
+      options: [ CS_MODE_RISCVC, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "c.lui a6, 5"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: a6
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_IMM
+                imm: 0x5
+                access: CS_AC_READ
+          groups: [ hasStdExtC ]
+  -
+    input:
+      bytes: [ 0x2a,0xa4 ]
+      arch: "CS_ARCH_RISCV"
+      options: [ CS_MODE_RISCVC, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "c.fsdsp fa0, 8(sp)"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: fa0
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_MEM
+                mem_base: sp
+                mem_disp: 0x8
+                access: CS_AC_WRITE
+          groups: [ hasStdExtC, hasStdExtD ]
+  -
+    input:
+      bytes: [ 0x62,0x24 ]
+      arch: "CS_ARCH_RISCV"
+      options: [ CS_MODE_RISCVC, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "c.fldsp fs0, 0x18(sp)"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: fs0
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_MEM
+                mem_base: sp
+                mem_disp: 0x18
+                access: CS_AC_READ
+          groups: [ hasStdExtC, hasStdExtD ]
+  -
+    input:
+      bytes: [ 0xa6,0xff ]
+      arch: "CS_ARCH_RISCV"
+      options: [ CS_MODE_RISCVC, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "c.fswsp fs1, 0xfc(sp)"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: fs1
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_IMM
+                imm: 0xfc
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_REG
+                reg: sp
+                access: CS_AC_WRITE
+          groups: [ hasStdExtC, hasStdExtF, isrv32 ]
+  -
+    input:
+      bytes: [ 0x2a,0x65 ]
+      arch: "CS_ARCH_RISCV"
+      options: [ CS_MODE_RISCVC, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "c.flwsp fa0, 0x88(sp)"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: fa0
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_IMM
+                imm: 0x88
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_REG
+                reg: sp
+                access: CS_AC_READ
+          groups: [ hasStdExtC, hasStdExtF, isrv32 ]
+  -
+    input:
+      bytes: [ 0x76,0x86 ]
+      arch: "CS_ARCH_RISCV"
+      options: [ CS_MODE_RISCVC, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "c.mv a2, t4"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: a2
+                access: CS_AC_WRITE
+              -
+                type: RISCV_OP_REG
+                reg: t4
+                access: CS_AC_READ
+          groups: [ hasStdExtC ]
+  -
+    input:
+      bytes: [ 0x65,0xdd ]
+      arch: "CS_ARCH_RISCV"
+      options: [ CS_MODE_RISCVC, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "c.beqz a0, -8"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: a0
+                access: CS_AC_READ
+              -
+                type: RISCV_OP_IMM
+                imm: -0x8
+                access: CS_AC_READ
+          groups: [ hasStdExtC, branch_relative, jump ]
+  -
+    input:
+      bytes: [ 0x01,0x00 ]
+      arch: "CS_ARCH_RISCV"
+      options: [ CS_MODE_RISCVC, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "c.nop"
+        details:
+          groups: [ hasStdExtC ]
+  -
+    input:
+      bytes: [ 0xfd,0xaf ]
+      arch: "CS_ARCH_RISCV"
+      options: [ CS_MODE_RISCVC, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "c.j 0x7fe"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_IMM
+                imm: 0x7fe
+                access: CS_AC_READ
+          groups: [ hasStdExtC, jump ]
+  -
+    input:
+      bytes: [ 0x82,0x82 ]
+      arch: "CS_ARCH_RISCV"
+      options: [ CS_MODE_RISCVC, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "c.jr t0"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: t0
+                access: CS_AC_READ
+          groups: [ hasStdExtC, jump ]
+  -
+    input:
+      bytes: [ 0x11,0x20 ]
+      arch: "CS_ARCH_RISCV"
+      options: [ CS_MODE_RISCVC, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "c.jal 4"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_IMM
+                imm: 0x4
+                access: CS_AC_READ
+          groups: [ hasStdExtC, isrv32, call ]
+  -
+    input:
+      bytes: [ 0x82,0x94 ]
+      arch: "CS_ARCH_RISCV"
+      options: [ CS_MODE_RISCVC, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "c.jalr s1"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: s1
+                access: CS_AC_READ
+          groups: [ hasStdExtC, call ]
diff --git a/tests/details/sh.yaml b/tests/details/sh.yaml
new file mode 100644
index 000000000..2118f3c47
--- /dev/null
+++ b/tests/details/sh.yaml
@@ -0,0 +1,111 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x0c, 0x31, 0x10, 0x20, 0x22, 0x21, 0x36, 0x64, 0x46, 0x25, 0x12, 0x12, 0x1c, 0x02, 0x08, 0xc1, 0x05, 0xc7, 0x0c, 0x71, 0x1f, 0x02, 0x22, 0xcf, 0x06, 0x89, 0x23, 0x00, 0x2b, 0x41, 0x0b, 0x00, 0x0e, 0x40, 0x32, 0x00, 0x0a, 0xf1, 0x09, 0x00  ]
+      arch: "sh"
+      options: [ CS_OPT_DETAIL, CS_MODE_SH4A, CS_MODE_SHFPU ]
+      address: 0x80000000
+    expected:
+      insns:
+      -
+        asm_text: "add r0,r1"
+        details:
+          regs_read: [ r0 ]
+          regs_write: [ r1 ]
+      -
+        asm_text: "mov.b r1,@r0"
+        details:
+          regs_read: [ r0, r1 ]
+      -
+        asm_text: "mov.l r2,@r1"
+        details:
+          regs_read: [ r1, r2 ]
+      -
+        asm_text: "mov.l @r3+,r4"
+        details:
+          regs_write: [ r3, r4 ]
+      -
+        asm_text: "mov.l r4,@-r5"
+        details:
+          regs_read: [ r4 ]
+          regs_write: [ r5 ]
+      -
+        asm_text: "mov.l r1,@(8,r2)"
+        details:
+          regs_read: [ r2, r1 ]
+      -
+        asm_text: "mov.b @(r0,r1),r2"
+        details:
+          regs_read: [ r0, r1 ]
+          regs_write: [ r2 ]
+      -
+        asm_text: "mov.w r0,@(16,gbr)"
+        details:
+          regs_read: [ gbr, r0 ]
+      -
+        asm_text: "mova 0x80000028,r0"
+        details:
+          regs_write: [ r0 ]
+      -
+        asm_text: "add #12,r1"
+        details:
+          regs_write: [ r1 ]
+      -
+        asm_text: "mac.l @r1+,@r2+"
+        details:
+          regs_write: [ r1, r2 ]
+      -
+        asm_text: "or.b #34,@(r0,gbr)"
+        details:
+          regs_read: [ gbr, r0 ]
+      -
+        asm_text: "bt 0x80000028"
+        details:
+          groups: [ SH_GRP_JUMP, SH_GRP_BRANCH_RELATIVE ]
+      -
+        asm_text: "braf r0"
+        details:
+          regs_read: [ r0 ]
+          groups: [ SH_GRP_JUMP, SH_GRP_BRANCH_RELATIVE ]
+      -
+        asm_text: "jmp @r1"
+        details:
+          regs_read: [ r1 ]
+          groups: [ SH_GRP_JUMP ]
+      -
+        asm_text: "rts"
+
+      -
+        asm_text: "ldc r0,sr"
+        details:
+          regs_read: [ r0 ]
+          regs_write: [ sr ]
+      -
+        asm_text: "stc ssr,r0"
+        details:
+          regs_read: [ ssr ]
+          regs_write: [ r0 ]
+      -
+        asm_text: "fmov fr0,@r1"
+        details:
+          regs_read: [ r1, fr0 ]
+      -
+        asm_text: "nop"
+  -
+    input:
+      bytes: [ 0x32, 0x11, 0x92, 0x00, 0x32, 0x49, 0x31, 0x00  ]
+      arch: "sh"
+      options: [ CS_OPT_DETAIL, CS_MODE_SH2A, CS_MODE_SHFPU, CS_MODE_BIG_ENDIAN ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "movu.w @(1024,r1),r2"
+        details:
+          regs_read: [ r1 ]
+          regs_write: [ r2 ]
+      -
+        asm_text: "bld.b #4,@(256,r2)"
+        details:
+          regs_read: [ r2 ]
+
diff --git a/tests/details/sparc.yaml b/tests/details/sparc.yaml
new file mode 100644
index 000000000..23eac965a
--- /dev/null
+++ b/tests/details/sparc.yaml
@@ -0,0 +1,228 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x80, 0xa0, 0x40, 0x02, 0x85, 0xc2, 0x60, 0x08, 0x85, 0xe8, 0x20, 0x01, 0x81, 0xe8, 0x00, 0x00, 0x90, 0x10, 0x20, 0x01, 0xd5, 0xf6, 0x10, 0x16, 0x21, 0x00, 0x00, 0x0a, 0x86, 0x00, 0x40, 0x02, 0x01, 0x00, 0x00, 0x00, 0x12, 0xbf, 0xff, 0xff, 0x10, 0xbf, 0xff, 0xff, 0xa0, 0x02, 0x00, 0x09, 0x0d, 0xbf, 0xff, 0xff, 0xd4, 0x20, 0x60, 0x00, 0xd4, 0x4e, 0x00, 0x16, 0x2a, 0xc2, 0x80, 0x03  ]
+      arch: "sparc"
+      options: [ CS_OPT_DETAIL ]
+      address: 0x1000
+    expected:
+      insns:
+      -
+        asm_text: "cmp %g1, %g2"
+        details:
+          sparc:
+            operands:
+              -
+                type: SPARC_OP_REG
+                reg: g1
+              -
+                type: SPARC_OP_REG
+                reg: g2
+      -
+        asm_text: "jmpl %o1+8, %g2"
+        details:
+          sparc:
+            operands:
+              -
+                type: SPARC_OP_MEM
+                mem_base: o1
+                mem_disp: 0x8
+              -
+                type: SPARC_OP_REG
+                reg: g2
+      -
+        asm_text: "restore %g0, 1, %g2"
+        details:
+          sparc:
+            operands:
+              -
+                type: SPARC_OP_REG
+                reg: g0
+              -
+                type: SPARC_OP_IMM
+                imm: 0x1
+              -
+                type: SPARC_OP_REG
+                reg: g2
+      -
+        asm_text: "restore"
+      -
+        asm_text: "mov 1, %o0"
+        details:
+          sparc:
+            operands:
+              -
+                type: SPARC_OP_IMM
+                imm: 0x1
+              -
+                type: SPARC_OP_REG
+                reg: o0
+      -
+        asm_text: "casx [%i0], %l6, %o2"
+        details:
+          sparc:
+            operands:
+              -
+                type: SPARC_OP_MEM
+                mem_base: i0
+              -
+                type: SPARC_OP_REG
+                reg: l6
+              -
+                type: SPARC_OP_REG
+                reg: o2
+      -
+        asm_text: "sethi 0xa, %l0"
+        details:
+          sparc:
+            operands:
+              -
+                type: SPARC_OP_IMM
+                imm: 0xa
+              -
+                type: SPARC_OP_REG
+                reg: l0
+      -
+        asm_text: "add %g1, %g2, %g3"
+        details:
+          sparc:
+            operands:
+              -
+                type: SPARC_OP_REG
+                reg: g1
+              -
+                type: SPARC_OP_REG
+                reg: g2
+              -
+                type: SPARC_OP_REG
+                reg: g3
+      -
+        asm_text: "nop"
+      -
+        asm_text: "bne 0x1020"
+        details:
+          sparc:
+            operands:
+              -
+                type: SPARC_OP_IMM
+                imm: 0x1020
+            cc: SPARC_CC_ICC_NE
+      -
+        asm_text: "ba 0x1024"
+        details:
+          sparc:
+            operands:
+              -
+                type: SPARC_OP_IMM
+                imm: 0x1024
+      -
+        asm_text: "add %o0, %o1, %l0"
+        details:
+          sparc:
+            operands:
+              -
+                type: SPARC_OP_REG
+                reg: o0
+              -
+                type: SPARC_OP_REG
+                reg: o1
+              -
+                type: SPARC_OP_REG
+                reg: l0
+      -
+        asm_text: "fbg 0x102c"
+        details:
+          sparc:
+            operands:
+              -
+                type: SPARC_OP_IMM
+                imm: 0x102c
+            cc: SPARC_CC_FCC_G
+      -
+        asm_text: "st %o2, [%g1]"
+        details:
+          sparc:
+            operands:
+              -
+                type: SPARC_OP_REG
+                reg: o2
+              -
+                type: SPARC_OP_MEM
+                mem_base: g1
+      -
+        asm_text: "ldsb [%i0+%l6], %o2"
+        details:
+          sparc:
+            operands:
+              -
+                type: SPARC_OP_MEM
+                mem_base: i0
+                mem_index: l6
+              -
+                type: SPARC_OP_REG
+                reg: o2
+      -
+        asm_text: "brnz,a,pn %o2, 0x1048"
+        details:
+          sparc:
+            operands:
+              -
+                type: SPARC_OP_REG
+                reg: o2
+              -
+                type: SPARC_OP_IMM
+                imm: 0x1048
+            hint: SPARC_HINT_A_PN
+  -
+    input:
+      bytes: [ 0x81, 0xa8, 0x0a, 0x24, 0x89, 0xa0, 0x10, 0x20, 0x89, 0xa0, 0x1a, 0x60, 0x89, 0xa0, 0x00, 0xe0  ]
+      arch: "sparc"
+      options: [ CS_OPT_DETAIL ]
+      address: 0x1000
+    expected:
+      insns:
+      -
+        asm_text: "fcmps %f0, %f4"
+        details:
+          sparc:
+            operands:
+              -
+                type: SPARC_OP_REG
+                reg: f0
+              -
+                type: SPARC_OP_REG
+                reg: f4
+      -
+        asm_text: "fstox %f0, %f4"
+        details:
+          sparc:
+            operands:
+              -
+                type: SPARC_OP_REG
+                reg: f0
+              -
+                type: SPARC_OP_REG
+                reg: f4
+      -
+        asm_text: "fqtoi %f0, %f4"
+        details:
+          sparc:
+            operands:
+              -
+                type: SPARC_OP_REG
+                reg: f0
+              -
+                type: SPARC_OP_REG
+                reg: f4
+      -
+        asm_text: "fnegq %f0, %f4"
+        details:
+          sparc:
+            operands:
+              -
+                type: SPARC_OP_REG
+                reg: f0
+              -
+                type: SPARC_OP_REG
+                reg: f4
+
diff --git a/tests/details/systemz.yaml b/tests/details/systemz.yaml
new file mode 100644
index 000000000..da96cbe65
--- /dev/null
+++ b/tests/details/systemz.yaml
@@ -0,0 +1,117 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x1a, 0x5a, 0x0f, 0x1f, 0xff, 0xc2, 0x09, 0x80, 0x00, 0x00, 0x00, 0x07, 0xf7, 0xeb, 0x2a, 0xff, 0xff, 0x7f, 0x57, 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x57, 0xeb, 0x00, 0xf0, 0x00, 0x00, 0x24, 0xb2, 0x4f, 0x00, 0x78, 0xec, 0x18, 0x00, 0x00, 0xc1, 0x7f  ]
+      arch: "CS_ARCH_SYSZ"
+      options: [ CS_OPT_DETAIL ]
+      address: 0x1000
+    expected:
+      insns:
+      -
+        asm_text: "adb %f0, 0"
+        details:
+          systemz:
+            operands:
+              -
+                type: SYSZ_OP_REG
+                reg: f0
+              -
+                type: SYSZ_OP_IMM
+                imm: 0x0
+      -
+        asm_text: "a %r0, 0xfff(%r15, %r1)"
+        details:
+          systemz:
+            operands:
+              -
+                type: SYSZ_OP_REG
+                reg: "0"
+              -
+                type: SYSZ_OP_MEM
+                mem_base: "1"
+                mem_index: "15"
+                mem_disp: 0xfff
+      -
+        asm_text: "afi %r0, -0x80000000"
+        details:
+          systemz:
+            operands:
+              -
+                type: SYSZ_OP_REG
+                reg: "0"
+              -
+                type: SYSZ_OP_IMM
+                imm: -0x80000000
+      -
+        asm_text: "br %r7"
+        details:
+          systemz:
+            operands:
+              -
+                type: SYSZ_OP_REG
+                reg: "7"
+      -
+        asm_text: "xiy 0x7ffff(%r15), 0x2a"
+        details:
+          systemz:
+            operands:
+              -
+                type: SYSZ_OP_MEM
+                mem_base: "15"
+                mem_disp: 0x7ffff
+              -
+                type: SYSZ_OP_IMM
+                imm: 0x2a
+      -
+        asm_text: "xy %r0, 0x7ffff(%r1, %r15)"
+        details:
+          systemz:
+            operands:
+              -
+                type: SYSZ_OP_REG
+                reg: "0"
+              -
+                type: SYSZ_OP_MEM
+                mem_base: "15"
+                mem_index: "1"
+                mem_disp: 0x7ffff
+      -
+        asm_text: "stmg %r0, %r0, 0(%r15)"
+        details:
+          systemz:
+            operands:
+              -
+                type: SYSZ_OP_REG
+                reg: "0"
+              -
+                type: SYSZ_OP_REG
+                reg: "0"
+              -
+                type: SYSZ_OP_MEM
+                mem_base: "15"
+      -
+        asm_text: "ear %r7, %a8"
+        details:
+          systemz:
+            operands:
+              -
+                type: SYSZ_OP_REG
+                reg: "7"
+              -
+                type: SYSZ_OP_REG
+                reg: a8
+      -
+        asm_text: "clije %r1, 0xc1, 0x1028"
+        details:
+          systemz:
+            operands:
+              -
+                type: SYSZ_OP_REG
+                reg: "1"
+              -
+                type: SYSZ_OP_IMM
+                imm: 0xc1
+              -
+                type: SYSZ_OP_IMM
+                imm: 0x1028
+
diff --git a/tests/details/tms320c64x.yaml b/tests/details/tms320c64x.yaml
new file mode 100644
index 000000000..93610edc7
--- /dev/null
+++ b/tests/details/tms320c64x.yaml
@@ -0,0 +1,147 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x01, 0xac, 0x88, 0x40, 0x81, 0xac, 0x88, 0x43, 0x00, 0x00, 0x00, 0x00, 0x02, 0x90, 0x32, 0x96, 0x02, 0x80, 0x46, 0x9e, 0x05, 0x3c, 0x83, 0xe6, 0x0b, 0x0c, 0x8b, 0x24  ]
+      arch: "tms320c64x"
+      options: [ CS_OPT_DETAIL ]
+      address: 0x1000
+    expected:
+      insns:
+      -
+        asm_text: "add.D1 a11, a4, a3"
+        details:
+          tms320c64x:
+            operands:
+              -
+                type: TMS320C64X_OP_REG
+                reg: a11
+              -
+                type: TMS320C64X_OP_REG
+                reg: a4
+              -
+                type: TMS320C64X_OP_REG
+                reg: a3
+            funit_unit: TMS320C64X_FUNIT_D
+            funit_side: 1
+            funit_side_set: true
+            parallel: 0
+            parallel_set: true
+      -
+        asm_text: "[ a1] add.D2 b11, b4, b3 ||"
+        details:
+          tms320c64x:
+            operands:
+              -
+                type: TMS320C64X_OP_REG
+                reg: b11
+              -
+                type: TMS320C64X_OP_REG
+                reg: b4
+              -
+                type: TMS320C64X_OP_REG
+                reg: b3
+            funit_unit: TMS320C64X_FUNIT_D
+            funit_side: 2
+            funit_side_set: true
+            cond_reg: a1
+            cond_zero: -1
+            parallel: 1
+            parallel_set: true
+      -
+        asm_text: "NOP"
+        details:
+          tms320c64x:
+            funit_unit: TMS320C64X_FUNIT_NO
+            parallel: 0
+            parallel_set: true
+      -
+        asm_text: "ldbu.D1T2 *++a4[1], b5"
+        details:
+          tms320c64x:
+            operands:
+              -
+                type: TMS320C64X_OP_MEM
+                mem_base: a4
+                mem_disptype: TMS320C64X_MEM_DISP_CONSTANT
+                mem_disp_const: 0x1
+                mem_unit: 2
+                mem_direction: TMS320C64X_MEM_DIR_FW
+                mem_modify: TMS320C64X_MEM_MOD_PRE
+                mem_scaled: 1
+              -
+                type: TMS320C64X_OP_REG
+                reg: b5
+            funit_unit: TMS320C64X_FUNIT_D
+            funit_side: 2
+            funit_side_set: true
+            parallel: 0
+            parallel_set: true
+      -
+        asm_text: "ldbu.D2T2 *+b15[0x46], b5"
+        details:
+          tms320c64x:
+            operands:
+              -
+                type: TMS320C64X_OP_MEM
+                mem_base: b15
+                mem_disptype: TMS320C64X_MEM_DISP_CONSTANT
+                mem_disp_const: 0x46
+                mem_unit: 2
+                mem_direction: TMS320C64X_MEM_DIR_FW
+                mem_modify: TMS320C64X_MEM_MOD_NO
+                mem_scaled: -1
+              -
+                type: TMS320C64X_OP_REG
+                reg: b5
+            funit_unit: TMS320C64X_FUNIT_D
+            funit_side: 2
+            funit_side_set: true
+            parallel: 0
+            parallel_set: true
+      -
+        asm_text: "lddw.D1T2 *+a15[4], b11:b10"
+        details:
+          tms320c64x:
+            operands:
+              -
+                type: TMS320C64X_OP_MEM
+                mem_base: a15
+                mem_disptype: TMS320C64X_MEM_DISP_CONSTANT
+                mem_disp_const: 0x4
+                mem_unit: 2
+                mem_direction: TMS320C64X_MEM_DIR_FW
+                mem_modify: TMS320C64X_MEM_MOD_NO
+                mem_scaled: 1
+              -
+                type: TMS320C64X_OP_REGPAIR
+                reg_pair_0: b11
+                reg_pair_1: b10
+            funit_unit: TMS320C64X_FUNIT_D
+            funit_side: 2
+            funit_side_set: true
+            parallel: 0
+            parallel_set: true
+      -
+        asm_text: "ldndw.D1T1 *+a3(a4), a23:a22"
+        details:
+          tms320c64x:
+            operands:
+              -
+                type: TMS320C64X_OP_MEM
+                mem_base: a3
+                mem_disptype: TMS320C64X_MEM_DISP_REGISTER
+                mem_disp_reg: a4
+                mem_unit: 1
+                mem_direction: TMS320C64X_MEM_DIR_FW
+                mem_modify: TMS320C64X_MEM_MOD_NO
+                mem_scaled: -1
+              -
+                type: TMS320C64X_OP_REGPAIR
+                reg_pair_0: a23
+                reg_pair_1: a22
+            funit_unit: TMS320C64X_FUNIT_D
+            funit_side: 1
+            funit_side_set: true
+            parallel: 0
+            parallel_set: true
+
diff --git a/tests/details/tricore.yaml b/tests/details/tricore.yaml
new file mode 100644
index 000000000..1ded01616
--- /dev/null
+++ b/tests/details/tricore.yaml
@@ -0,0 +1,101 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x09, 0xcf, 0xbc, 0xf5, 0x09, 0xf4, 0x01, 0x00, 0x89, 0xfb, 0x8f, 0x74, 0x89, 0xfe, 0x48, 0x01, 0x29, 0x00, 0x19, 0x25, 0x29, 0x03, 0x09, 0xf4, 0x85, 0xf9, 0x68, 0x0f, 0x16, 0x01  ]
+      arch: "tricore"
+      options: [ CS_MODE_TRICORE_162, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "ld.a a15, [+a12]#-4"
+        details:
+          tricore:
+            operands:
+              -
+                type: TRICORE_OP_REG
+                reg: a15
+              -
+                type: TRICORE_OP_MEM
+                mem_base: a12
+                mem_disp: -4
+      -
+        asm_text: "ld.b d4, [a15+]#1"
+        details:
+          tricore:
+            operands:
+              -
+                type: TRICORE_OP_REG
+                reg: d4
+              -
+                type: TRICORE_OP_MEM
+                mem_base: a15
+                mem_disp: 0x1
+      -
+        asm_text: "st.h [+a15]#0x1cf, d11"
+        details:
+          tricore:
+            operands:
+              -
+                type: TRICORE_OP_MEM
+                mem_base: a15
+                mem_disp: 0x1cf
+              -
+                type: TRICORE_OP_REG
+                reg: d11
+      -
+        asm_text: "st.d [a15+]#8, e14"
+        details:
+          tricore:
+            operands:
+              -
+                type: TRICORE_OP_MEM
+                mem_base: a15
+                mem_disp: 0x8
+              -
+                type: TRICORE_OP_REG
+                reg: e14
+      -
+        asm_text: "ld.w d0, [p0+c]#0x99"
+        details:
+          tricore:
+            operands:
+              -
+                type: TRICORE_OP_REG
+                reg: d0
+              -
+                type: TRICORE_OP_MEM
+                mem_base: p0
+                mem_disp: 0x99
+      -
+        asm_text: "ld.b d3, [p0+c]#-0x37"
+        details:
+          tricore:
+            operands:
+              -
+                type: TRICORE_OP_REG
+                reg: d3
+              -
+                type: TRICORE_OP_MEM
+                mem_base: p0
+                mem_disp: -0x37
+      -
+        asm_text: "ld.da p8, #0xf0003428"
+        details:
+          tricore:
+            operands:
+              -
+                type: TRICORE_OP_REG
+                reg: p8
+              -
+                type: TRICORE_OP_IMM
+                imm: 0xf0003428
+      -
+        asm_text: "and d15, #1"
+        details:
+          tricore:
+            operands:
+              -
+                type: TRICORE_OP_IMM
+                imm: 0x1
+
diff --git a/tests/details/wasm.yaml b/tests/details/wasm.yaml
new file mode 100644
index 000000000..1a3a49297
--- /dev/null
+++ b/tests/details/wasm.yaml
@@ -0,0 +1,58 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x20, 0x00, 0x20, 0x01, 0x41, 0x20, 0x10, 0xc9, 0x01, 0x45, 0x0b  ]
+      arch: "wasm"
+      options: [ CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "get_local 0x0"
+        details:
+          groups: [ WASM_GRP_VARIABLE ]
+          wasm:
+            operands:
+              -
+                type: WASM_OP_VARUINT32
+                varuint32: 0x0
+                size: 1
+      -
+        asm_text: "get_local 0x1"
+        details:
+          groups: [ WASM_GRP_VARIABLE ]
+          wasm:
+            operands:
+              -
+                type: WASM_OP_VARUINT32
+                varuint32: 0x1
+                size: 1
+      -
+        asm_text: "i32.const 0x20"
+        details:
+          groups: [ WASM_GRP_NUMBERIC ]
+          wasm:
+            operands:
+              -
+                type: WASM_OP_VARUINT32
+                varuint32: 0x20
+                size: 1
+      -
+        asm_text: "call 0xc9"
+        details:
+          groups: [ WASM_GRP_CONTROL ]
+          wasm:
+            operands:
+              -
+                type: WASM_OP_VARUINT32
+                varuint32: 0xc9
+                size: 2
+      -
+        asm_text: "i32.eqz"
+        details:
+          groups: [ WASM_GRP_NUMBERIC ]
+      -
+        asm_text: "end"
+        details:
+          groups: [ WASM_GRP_CONTROL ]
+
diff --git a/tests/details/x86.yaml b/tests/details/x86.yaml
new file mode 100644
index 000000000..4f453121d
--- /dev/null
+++ b/tests/details/x86.yaml
@@ -0,0 +1,1242 @@
+test_cases:
+  -
+    input:
+      bytes: [0x8d, 0x4c, 0x32, 0x08, 0x01, 0xd8, 0x81, 0xc6, 0x34, 0x12, 0x00, 0x00, 0x05, 0x23, 0x01, 0x00, 0x00, 0x36, 0x8b, 0x84, 0x91, 0x23, 0x01, 0x00, 0x00, 0x41, 0x8d, 0x84, 0x39, 0x89, 0x67, 0x00, 0x00, 0x8d, 0x87, 0x89, 0x67, 0x00, 0x00, 0xb4, 0xc6, 0x66, 0xe9, 0xb8, 0x00, 0x00, 0x00, 0x67, 0xff, 0xa0, 0x23, 0x01, 0x00, 0x00, 0x66, 0xe8, 0xcb, 0x00, 0x00, 0x00, 0x74, 0xfc, ]
+      arch: "x86"
+      options: [ CS_OPT_DETAIL, CS_MODE_16 ]
+      address: 0x1000
+    expected:
+      insns:
+      -
+        asm_text: "lea cx, [si + 0x32]"
+        details:
+          x86:
+            prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ]
+            opcode: [ 0x8d, 0x00, 0x00, 0x00 ]
+            rex: 0x0
+            addr_size: 2
+            modrm: 0x4c
+            enc_modrm_offset: 0x1
+            disp: 0x32
+            enc_disp_offset: 0x2
+            enc_disp_size: 0x1
+            operands:
+              -
+                type: X86_OP_REG
+                reg: cx
+                size: 2
+                access: CS_AC_WRITE
+              -
+                type: X86_OP_MEM
+                mem_base: si
+                mem_disp: 0x32
+                size: 2
+                access: CS_AC_READ
+          regs_read: [ si ]
+          regs_write: [ cx ]
+      -
+        asm_text: "or byte ptr [bx + di], al"
+        details:
+          x86:
+            prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ]
+            opcode: [ 0x08, 0x00, 0x00, 0x00 ]
+            rex: 0x0
+            addr_size: 2
+            modrm: 0x1
+            enc_modrm_offset: 0x1
+            disp: 0x0
+            operands:
+              -
+                type: X86_OP_MEM
+                mem_base: bx
+                mem_index: di
+                size: 1
+                access: CS_AC_READ_WRITE
+              -
+                type: X86_OP_REG
+                reg: al
+                size: 1
+                access: CS_AC_READ
+            eflags: [ X86_EFLAGS_MODIFY_SF, X86_EFLAGS_MODIFY_ZF, X86_EFLAGS_MODIFY_PF, X86_EFLAGS_RESET_OF, X86_EFLAGS_RESET_CF, X86_EFLAGS_UNDEFINED_AF ]
+          regs_read: [ bx, di, al ]
+          regs_write: [ flags ]
+      -
+        asm_text: "fadd dword ptr [bx + di + 0x34c6]"
+        details:
+          x86:
+            prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ]
+            opcode: [ 0xd8, 0x00, 0x00, 0x00 ]
+            rex: 0x0
+            addr_size: 2
+            modrm: 0x81
+            enc_modrm_offset: 0x1
+            disp: 0x34c6
+            enc_disp_offset: 0x2
+            enc_disp_size: 0x2
+            operands:
+              -
+                type: X86_OP_MEM
+                mem_base: bx
+                mem_index: di
+                mem_disp: 0x34c6
+                size: 4
+                access: CS_AC_READ
+            fpu_flags: [ X86_FPU_FLAGS_MODIFY_C1, X86_FPU_FLAGS_UNDEFINED_C0, X86_FPU_FLAGS_UNDEFINED_C2, X86_FPU_FLAGS_UNDEFINED_C3]
+          regs_read: [ bx, di ]
+          regs_write: [ fpsw ]
+      -
+        asm_text: "adc al, byte ptr [bx + si]"
+        details:
+          x86:
+            prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ]
+            opcode: [ 0x12, 0x00, 0x00, 0x00 ]
+            rex: 0x0
+            addr_size: 2
+            modrm: 0x0
+            enc_modrm_offset: 0x1
+            disp: 0x0
+            operands:
+              -
+                type: X86_OP_REG
+                reg: al
+                size: 1
+                access: CS_AC_READ_WRITE
+              -
+                type: X86_OP_MEM
+                mem_base: bx
+                mem_index: si
+                size: 1
+                access: CS_AC_READ
+            eflags: [  X86_EFLAGS_MODIFY_AF, X86_EFLAGS_MODIFY_CF, X86_EFLAGS_MODIFY_SF, X86_EFLAGS_MODIFY_ZF, X86_EFLAGS_MODIFY_PF, X86_EFLAGS_MODIFY_OF, X86_EFLAGS_TEST_CF ]
+          regs_read: [ flags, al, bx, si ]
+          regs_write: [ flags, al ]
+      -
+        asm_text: "add byte ptr [di], al"
+        details:
+          x86:
+            prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ]
+            opcode: [ 0x00, 0x00, 0x00, 0x00 ]
+            rex: 0x0
+            addr_size: 2
+            modrm: 0x5
+            enc_modrm_offset: 0x1
+            disp: 0x0
+            operands:
+              -
+                type: X86_OP_MEM
+                mem_base: di
+                size: 1
+                access: CS_AC_READ_WRITE
+              -
+                type: X86_OP_REG
+                reg: al
+                size: 1
+                access: CS_AC_READ
+            eflags: [  X86_EFLAGS_MODIFY_AF, X86_EFLAGS_MODIFY_CF, X86_EFLAGS_MODIFY_SF, X86_EFLAGS_MODIFY_ZF, X86_EFLAGS_MODIFY_PF, X86_EFLAGS_MODIFY_OF ]
+          regs_read: [ di, al ]
+          regs_write: [ flags ]
+      -
+        asm_text: "and ax, word ptr [bx + di]"
+        details:
+          x86:
+            prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ]
+            opcode: [ 0x23, 0x00, 0x00, 0x00 ]
+            rex: 0x0
+            addr_size: 2
+            modrm: 0x1
+            enc_modrm_offset: 0x1
+            disp: 0x0
+            operands:
+              -
+                type: X86_OP_REG
+                reg: ax
+                size: 2
+                access: CS_AC_READ_WRITE
+              -
+                type: X86_OP_MEM
+                mem_base: bx
+                mem_index: di
+                size: 2
+                access: CS_AC_READ
+            eflags: [  X86_EFLAGS_MODIFY_SF, X86_EFLAGS_MODIFY_ZF, X86_EFLAGS_MODIFY_PF, X86_EFLAGS_RESET_OF, X86_EFLAGS_RESET_CF, X86_EFLAGS_UNDEFINED_AF ]
+          regs_read: [ ax, bx, di ]
+          regs_write: [ flags, ax ]
+      -
+        asm_text: "add byte ptr [bx + si], al"
+        details:
+          x86:
+            prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ]
+            opcode: [ 0x00, 0x00, 0x00, 0x00 ]
+            rex: 0x0
+            addr_size: 2
+            modrm: 0x0
+            enc_modrm_offset: 0x1
+            disp: 0x0
+            operands:
+              -
+                type: X86_OP_MEM
+                mem_base: bx
+                mem_index: si
+                size: 1
+                access: CS_AC_READ_WRITE
+              -
+                type: X86_OP_REG
+                reg: al
+                size: 1
+                access: CS_AC_READ
+            eflags: [  X86_EFLAGS_MODIFY_AF, X86_EFLAGS_MODIFY_CF, X86_EFLAGS_MODIFY_SF, X86_EFLAGS_MODIFY_ZF, X86_EFLAGS_MODIFY_PF, X86_EFLAGS_MODIFY_OF ]
+          regs_read: [ bx, si, al ]
+          regs_write: [ flags ]
+      -
+        asm_text: "mov ax, word ptr ss:[si + 0x2391]"
+        details:
+          x86:
+            prefix: [ X86_PREFIX_0, X86_PREFIX_SS, X86_PREFIX_0, X86_PREFIX_0 ]
+            opcode: [ 0x8b, 0x00, 0x00, 0x00 ]
+            rex: 0x0
+            addr_size: 2
+            modrm: 0x84
+            enc_modrm_offset: 0x2
+            disp: 0x2391
+            enc_disp_offset: 0x3
+            enc_disp_size: 0x2
+            operands:
+              -
+                type: X86_OP_REG
+                reg: ax
+                size: 2
+                access: CS_AC_WRITE
+              -
+                type: X86_OP_MEM
+                mem_segment: ss
+                mem_base: si
+                mem_disp: 0x2391
+                size: 2
+                access: CS_AC_READ
+          regs_read: [ ss, si ]
+          regs_write: [ ax ]
+      -
+        asm_text: "add word ptr [bx + si], ax"
+        details:
+          x86:
+            prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ]
+            opcode: [ 0x01, 0x00, 0x00, 0x00 ]
+            rex: 0x0
+            addr_size: 2
+            modrm: 0x0
+            enc_modrm_offset: 0x1
+            disp: 0x0
+            operands:
+              -
+                type: X86_OP_MEM
+                mem_base: bx
+                mem_index: si
+                size: 2
+                access: CS_AC_READ_WRITE
+              -
+                type: X86_OP_REG
+                reg: ax
+                size: 2
+                access: CS_AC_READ
+            eflags: [  X86_EFLAGS_MODIFY_AF, X86_EFLAGS_MODIFY_CF, X86_EFLAGS_MODIFY_SF, X86_EFLAGS_MODIFY_ZF, X86_EFLAGS_MODIFY_PF, X86_EFLAGS_MODIFY_OF ]
+          regs_read: [ bx, si, ax ]
+          regs_write: [ flags ]
+      -
+        asm_text: "add byte ptr [bx + di - 0x73], al"
+        details:
+          x86:
+            prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ]
+            opcode: [ 0x00, 0x00, 0x00, 0x00 ]
+            rex: 0x0
+            addr_size: 2
+            modrm: 0x41
+            enc_modrm_offset: 0x1
+            disp: -0x73
+            enc_disp_offset: 0x2
+            enc_disp_size: 0x1
+            operands:
+              -
+                type: X86_OP_MEM
+                mem_base: bx
+                mem_index: di
+                mem_disp: -0x73
+                size: 1
+                access: CS_AC_READ_WRITE
+              -
+                type: X86_OP_REG
+                reg: al
+                size: 1
+                access: CS_AC_READ
+            eflags: [  X86_EFLAGS_MODIFY_AF, X86_EFLAGS_MODIFY_CF, X86_EFLAGS_MODIFY_SF, X86_EFLAGS_MODIFY_ZF, X86_EFLAGS_MODIFY_PF, X86_EFLAGS_MODIFY_OF ]
+          regs_read: [ bx, di, al ]
+          regs_write: [ flags ]
+      -
+        asm_text: "test byte ptr [bx + di], bh"
+        details:
+          x86:
+            prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ]
+            opcode: [ 0x84, 0x00, 0x00, 0x00 ]
+            rex: 0x0
+            addr_size: 2
+            modrm: 0x39
+            enc_modrm_offset: 0x1
+            disp: 0x0
+            operands:
+              -
+                type: X86_OP_MEM
+                mem_base: bx
+                mem_index: di
+                size: 1
+              -
+                type: X86_OP_REG
+                reg: bh
+                size: 1
+          regs_read: [ bx, di ]
+      -
+        asm_text: "mov word ptr [bx], sp"
+        details:
+          x86:
+            prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ]
+            opcode: [ 0x89, 0x00, 0x00, 0x00 ]
+            rex: 0x0
+            addr_size: 2
+            modrm: 0x67
+            enc_modrm_offset: 0x1
+            disp: 0x0
+            enc_disp_offset: 0x2
+            enc_disp_size: 0x1
+            operands:
+              -
+                type: X86_OP_MEM
+                mem_base: bx
+                size: 2
+                access: CS_AC_WRITE
+              -
+                type: X86_OP_REG
+                reg: sp
+                size: 2
+                access: CS_AC_READ
+          regs_read: [ bx, sp ]
+      -
+        asm_text: "add byte ptr [di - 0x7679], cl"
+        details:
+          x86:
+            prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ]
+            opcode: [ 0x00, 0x00, 0x00, 0x00 ]
+            rex: 0x0
+            addr_size: 2
+            modrm: 0x8d
+            enc_modrm_offset: 0x1
+            disp: -0x7679
+            enc_disp_offset: 0x2
+            enc_disp_size: 0x2
+            operands:
+              -
+                type: X86_OP_MEM
+                mem_base: di
+                mem_disp: -0x7679
+                size: 1
+                access: CS_AC_READ_WRITE
+              -
+                type: X86_OP_REG
+                reg: cl
+                size: 1
+                access: CS_AC_READ
+            eflags: [  X86_EFLAGS_MODIFY_AF, X86_EFLAGS_MODIFY_CF, X86_EFLAGS_MODIFY_SF, X86_EFLAGS_MODIFY_ZF, X86_EFLAGS_MODIFY_PF, X86_EFLAGS_MODIFY_OF ]
+          regs_read: [ di, cl ]
+          regs_write: [ flags ]
+      -
+        asm_text: "add byte ptr [eax], al"
+        details:
+          x86:
+            prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_ADDRSIZE ]
+            opcode: [ 0x00, 0x00, 0x00, 0x00 ]
+            rex: 0x0
+            addr_size: 4
+            modrm: 0x0
+            enc_modrm_offset: 0x2
+            disp: 0x0
+            operands:
+              -
+                type: X86_OP_MEM
+                mem_base: eax
+                size: 1
+                access: CS_AC_READ_WRITE
+              -
+                type: X86_OP_REG
+                reg: al
+                size: 1
+                access: CS_AC_READ
+            eflags: [  X86_EFLAGS_MODIFY_AF, X86_EFLAGS_MODIFY_CF, X86_EFLAGS_MODIFY_SF, X86_EFLAGS_MODIFY_ZF, X86_EFLAGS_MODIFY_PF, X86_EFLAGS_MODIFY_OF ]
+          regs_read: [ eax, al ]
+          regs_write: [ flags ]
+      -
+        asm_text: "mov ah, 0xc6"
+        details:
+          x86:
+            prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ]
+            opcode: [ 0xb4, 0x00, 0x00, 0x00 ]
+            rex: 0x0
+            addr_size: 2
+            modrm: 0x0
+            disp: 0x0
+            operands:
+              -
+                type: X86_OP_REG
+                reg: ah
+                size: 1
+                access: CS_AC_WRITE
+              -
+                type: X86_OP_IMM
+                imm: 0xc6
+                size: 1
+          regs_write: [ ah ]
+      -
+        asm_text: "jmp 0x10e7"
+        details:
+          x86:
+            prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_OPSIZE, X86_PREFIX_0 ]
+            opcode: [ 0xe9, 0x00, 0x00, 0x00 ]
+            rex: 0x0
+            addr_size: 2
+            modrm: 0x0
+            disp: 0x0
+            operands:
+              -
+                type: X86_OP_IMM
+                imm: 0x10e7
+                size: 4
+      -
+        asm_text: "jmp word ptr [eax + 0x123]"
+        details:
+          x86:
+            prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_ADDRSIZE ]
+            opcode: [ 0xff, 0x00, 0x00, 0x00 ]
+            rex: 0x0
+            addr_size: 4
+            modrm: 0xa0
+            enc_modrm_offset: 0x2
+            disp: 0x123
+            enc_disp_offset: 0x3
+            enc_disp_size: 0x4
+            operands:
+              -
+                type: X86_OP_MEM
+                mem_base: eax
+                mem_disp: 0x123
+                size: 2
+                access: CS_AC_READ
+          regs_read: [ eax ]
+      -
+        asm_text: "call 0x1107"
+        details:
+          x86:
+            prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_OPSIZE, X86_PREFIX_0 ]
+            opcode: [ 0xe8, 0x00, 0x00, 0x00 ]
+            rex: 0x0
+            addr_size: 2
+            modrm: 0x0
+            disp: 0x0
+            operands:
+              -
+                type: X86_OP_IMM
+                imm: 0x1107
+                size: 4
+          regs_read: [ esp, eip ]
+          regs_write: [ esp ]
+      -
+        asm_text: "je 0x103a"
+        details:
+          x86:
+            prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ]
+            opcode: [ 0x74, 0x00, 0x00, 0x00 ]
+            rex: 0x0
+            addr_size: 2
+            modrm: 0x0
+            disp: 0x0
+            operands:
+              -
+                type: X86_OP_IMM
+                imm: 0x103a
+                size: 2
+            eflags: [  X86_EFLAGS_TEST_ZF ]
+          regs_read: [ flags ]
+  -
+    input:
+      bytes: [0x8d, 0x4c, 0x32, 0x08, 0x01, 0xd8, 0x81, 0xc6, 0x34, 0x12, 0x00, 0x00, 0x05, 0x23, 0x01, 0x00, 0x00, 0x36, 0x8b, 0x84, 0x91, 0x23, 0x01, 0x00, 0x00, 0x41, 0x8d, 0x84, 0x39, 0x89, 0x67, 0x00, 0x00, 0x8d, 0x87, 0x89, 0x67, 0x00, 0x00, 0xb4, 0xc6, 0xe9, 0xea, 0xbe, 0xad, 0xde, 0xff, 0xa0, 0x23, 0x01, 0x00, 0x00, 0xe8, 0xdf, 0xbe, 0xad, 0xde, 0x74, 0xff, ]
+      arch: "x86"
+      options: [ CS_OPT_DETAIL, CS_MODE_32, CS_OPT_SYNTAX_ATT ]
+      address: 0x1000
+    expected:
+      insns:
+      -
+        asm_text: "leal 8(%edx, %esi), %ecx"
+        details:
+          x86:
+            prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ]
+            opcode: [ 0x8d, 0x00, 0x00, 0x00 ]
+            rex: 0x0
+            addr_size: 4
+            modrm: 0x4c
+            enc_modrm_offset: 0x1
+            disp: 0x8
+            enc_disp_offset: 0x3
+            enc_disp_size: 0x1
+            sib: 0x32
+            sib_base: edx
+            sib_index: esi
+            sib_scale: 1
+            operands:
+              -
+                type: X86_OP_MEM
+                mem_base: edx
+                mem_index: esi
+                mem_disp: 0x8
+                size: 4
+                access: CS_AC_READ
+              -
+                type: X86_OP_REG
+                reg: ecx
+                size: 4
+                access: CS_AC_WRITE
+          regs_read: [ edx, esi ]
+          regs_write: [ ecx ]
+      -
+        asm_text: "addl %ebx, %eax"
+        details:
+          x86:
+            prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ]
+            opcode: [ 0x01, 0x00, 0x00, 0x00 ]
+            rex: 0x0
+            addr_size: 4
+            modrm: 0xd8
+            enc_modrm_offset: 0x1
+            disp: 0x0
+            sib: 0x0
+            operands:
+              -
+                type: X86_OP_REG
+                reg: ebx
+                size: 4
+                access: CS_AC_READ
+              -
+                type: X86_OP_REG
+                reg: eax
+                size: 4
+                access: CS_AC_READ_WRITE
+            eflags: [  X86_EFLAGS_MODIFY_AF, X86_EFLAGS_MODIFY_CF, X86_EFLAGS_MODIFY_SF, X86_EFLAGS_MODIFY_ZF, X86_EFLAGS_MODIFY_PF, X86_EFLAGS_MODIFY_OF ]
+          regs_read: [ ebx, eax ]
+          regs_write: [ eflags, eax ]
+      -
+        asm_text: "addl $0x1234, %esi"
+        details:
+          x86:
+            prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ]
+            opcode: [ 0x81, 0x00, 0x00, 0x00 ]
+            rex: 0x0
+            addr_size: 4
+            modrm: 0xc6
+            enc_modrm_offset: 0x1
+            disp: 0x0
+            sib: 0x0
+            operands:
+              -
+                type: X86_OP_IMM
+                imm: 0x1234
+                size: 4
+              -
+                type: X86_OP_REG
+                reg: esi
+                size: 4
+                access: CS_AC_READ_WRITE
+            eflags: [  X86_EFLAGS_MODIFY_AF, X86_EFLAGS_MODIFY_CF, X86_EFLAGS_MODIFY_SF, X86_EFLAGS_MODIFY_ZF, X86_EFLAGS_MODIFY_PF, X86_EFLAGS_MODIFY_OF ]
+          regs_read: [ esi ]
+          regs_write: [ eflags, esi ]
+      -
+        asm_text: "addl $0x123, %eax"
+        details:
+          x86:
+            prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ]
+            opcode: [ 0x05, 0x00, 0x00, 0x00 ]
+            rex: 0x0
+            addr_size: 4
+            modrm: 0x0
+            disp: 0x0
+            sib: 0x0
+            operands:
+              -
+                type: X86_OP_IMM
+                imm: 0x123
+                size: 4
+              -
+                type: X86_OP_REG
+                reg: eax
+                size: 4
+                access: CS_AC_READ_WRITE
+            eflags: [  X86_EFLAGS_MODIFY_AF, X86_EFLAGS_MODIFY_CF, X86_EFLAGS_MODIFY_SF, X86_EFLAGS_MODIFY_ZF, X86_EFLAGS_MODIFY_PF, X86_EFLAGS_MODIFY_OF ]
+          regs_read: [ eax ]
+          regs_write: [ eflags, eax ]
+      -
+        asm_text: "movl %ss:0x123(%ecx, %edx, 4), %eax"
+        details:
+          x86:
+            prefix: [ X86_PREFIX_0, X86_PREFIX_SS, X86_PREFIX_0, X86_PREFIX_0 ]
+            opcode: [ 0x8b, 0x00, 0x00, 0x00 ]
+            rex: 0x0
+            addr_size: 4
+            modrm: 0x84
+            enc_modrm_offset: 0x2
+            disp: 0x123
+            enc_disp_offset: 0x4
+            enc_disp_size: 0x4
+            sib: 0x91
+            sib_base: ecx
+            sib_index: edx
+            sib_scale: 4
+            operands:
+              -
+                type: X86_OP_MEM
+                mem_segment: ss
+                mem_base: ecx
+                mem_index: edx
+                mem_scale: 4
+                mem_disp: 0x123
+                size: 4
+                access: CS_AC_READ
+              -
+                type: X86_OP_REG
+                reg: eax
+                size: 4
+                access: CS_AC_WRITE
+          regs_read: [ ss, ecx, edx ]
+          regs_write: [ eax ]
+      -
+        asm_text: "incl %ecx"
+        details:
+          x86:
+            prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ]
+            opcode: [ 0x41, 0x00, 0x00, 0x00 ]
+            rex: 0x0
+            addr_size: 4
+            modrm: 0x0
+            disp: 0x0
+            sib: 0x0
+            operands:
+              -
+                type: X86_OP_REG
+                reg: ecx
+                size: 4
+                access: CS_AC_READ_WRITE
+            eflags: [  X86_EFLAGS_MODIFY_AF, X86_EFLAGS_MODIFY_SF, X86_EFLAGS_MODIFY_ZF, X86_EFLAGS_MODIFY_PF, X86_EFLAGS_MODIFY_OF ]
+          regs_read: [ ecx ]
+          regs_write: [ eflags, ecx ]
+      -
+        asm_text: "leal 0x6789(%ecx, %edi), %eax"
+        details:
+          x86:
+            prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ]
+            opcode: [ 0x8d, 0x00, 0x00, 0x00 ]
+            rex: 0x0
+            addr_size: 4
+            modrm: 0x84
+            enc_modrm_offset: 0x1
+            disp: 0x6789
+            enc_disp_offset: 0x3
+            enc_disp_size: 0x4
+            sib: 0x39
+            sib_base: ecx
+            sib_index: edi
+            sib_scale: 1
+            operands:
+              -
+                type: X86_OP_MEM
+                mem_base: ecx
+                mem_index: edi
+                mem_disp: 0x6789
+                size: 4
+                access: CS_AC_READ
+              -
+                type: X86_OP_REG
+                reg: eax
+                size: 4
+                access: CS_AC_WRITE
+          regs_read: [ ecx, edi ]
+          regs_write: [ eax ]
+      -
+        asm_text: "leal 0x6789(%edi), %eax"
+        details:
+          x86:
+            prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ]
+            opcode: [ 0x8d, 0x00, 0x00, 0x00 ]
+            rex: 0x0
+            addr_size: 4
+            modrm: 0x87
+            enc_modrm_offset: 0x1
+            disp: 0x6789
+            enc_disp_offset: 0x2
+            enc_disp_size: 0x4
+            sib: 0x0
+            operands:
+              -
+                type: X86_OP_MEM
+                mem_base: edi
+                mem_disp: 0x6789
+                size: 4
+                access: CS_AC_READ
+              -
+                type: X86_OP_REG
+                reg: eax
+                size: 4
+                access: CS_AC_WRITE
+          regs_read: [ edi ]
+          regs_write: [ eax ]
+      -
+        asm_text: "movb $0xc6, %ah"
+        details:
+          x86:
+            prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ]
+            opcode: [ 0xb4, 0x00, 0x00, 0x00 ]
+            rex: 0x0
+            addr_size: 4
+            modrm: 0x0
+            disp: 0x0
+            sib: 0x0
+            operands:
+              -
+                type: X86_OP_IMM
+                imm: 0xc6
+                size: 1
+              -
+                type: X86_OP_REG
+                reg: ah
+                size: 1
+                access: CS_AC_WRITE
+          regs_write: [ ah ]
+      -
+        asm_text: "jmp 0xdeadcf18"
+        details:
+          x86:
+            prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ]
+            opcode: [ 0xe9, 0x00, 0x00, 0x00 ]
+            rex: 0x0
+            addr_size: 4
+            modrm: 0x0
+            disp: 0x0
+            sib: 0x0
+            operands:
+              -
+                type: X86_OP_IMM
+                imm: 0xdeadcf18
+                size: 4
+      -
+        asm_text: "jmpl *0x123(%eax)"
+        details:
+          x86:
+            prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ]
+            opcode: [ 0xff, 0x00, 0x00, 0x00 ]
+            rex: 0x0
+            addr_size: 4
+            modrm: 0xa0
+            enc_modrm_offset: 0x1
+            disp: 0x123
+            enc_disp_offset: 0x2
+            enc_disp_size: 0x4
+            sib: 0x0
+            operands:
+              -
+                type: X86_OP_MEM
+                mem_base: eax
+                mem_disp: 0x123
+                size: 4
+                access: CS_AC_READ
+          regs_read: [ eax ]
+      -
+        asm_text: "calll 0xdeadcf18"
+        details:
+          x86:
+            prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ]
+            opcode: [ 0xe8, 0x00, 0x00, 0x00 ]
+            rex: 0x0
+            addr_size: 4
+            modrm: 0x0
+            disp: 0x0
+            sib: 0x0
+            operands:
+              -
+                type: X86_OP_IMM
+                imm: 0xdeadcf18
+                size: 4
+          regs_read: [ esp, eip ]
+          regs_write: [ esp ]
+      -
+        asm_text: "je 0x103a"
+        details:
+          x86:
+            prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ]
+            opcode: [ 0x74, 0x00, 0x00, 0x00 ]
+            rex: 0x0
+            addr_size: 4
+            modrm: 0x0
+            disp: 0x0
+            sib: 0x0
+            operands:
+              -
+                type: X86_OP_IMM
+                imm: 0x103a
+                size: 4
+            eflags: [  X86_EFLAGS_TEST_ZF ]
+          regs_read: [ eflags ]
+  -
+    input:
+      bytes: [0x8d, 0x4c, 0x32, 0x08, 0x01, 0xd8, 0x81, 0xc6, 0x34, 0x12, 0x00, 0x00, 0x05, 0x23, 0x01, 0x00, 0x00, 0x36, 0x8b, 0x84, 0x91, 0x23, 0x01, 0x00, 0x00, 0x41, 0x8d, 0x84, 0x39, 0x89, 0x67, 0x00, 0x00, 0x8d, 0x87, 0x89, 0x67, 0x00, 0x00, 0xb4, 0xc6, 0xe9, 0xea, 0xbe, 0xad, 0xde, 0xff, 0xa0, 0x23, 0x01, 0x00, 0x00, 0xe8, 0xdf, 0xbe, 0xad, 0xde, 0x74, 0xff, ]
+      arch: "x86"
+      options: [ CS_OPT_DETAIL, CS_MODE_32 ]
+      address: 0x1000
+    expected:
+      insns:
+      -
+        asm_text: "lea ecx, [edx + esi + 8]"
+        details:
+          x86:
+            prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ]
+            opcode: [ 0x8d, 0x00, 0x00, 0x00 ]
+            rex: 0x0
+            addr_size: 4
+            modrm: 0x4c
+            enc_modrm_offset: 0x1
+            disp: 0x8
+            enc_disp_offset: 0x3
+            enc_disp_size: 0x1
+            sib: 0x32
+            sib_base: edx
+            sib_index: esi
+            sib_scale: 1
+            operands:
+              -
+                type: X86_OP_REG
+                reg: ecx
+                size: 4
+                access: CS_AC_WRITE
+              -
+                type: X86_OP_MEM
+                mem_base: edx
+                mem_index: esi
+                mem_disp: 0x8
+                size: 4
+                access: CS_AC_READ
+          regs_read: [ edx, esi ]
+          regs_write: [ ecx ]
+      -
+        asm_text: "add eax, ebx"
+        details:
+          x86:
+            prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ]
+            opcode: [ 0x01, 0x00, 0x00, 0x00 ]
+            rex: 0x0
+            addr_size: 4
+            modrm: 0xd8
+            enc_modrm_offset: 0x1
+            disp: 0x0
+            sib: 0x0
+            operands:
+              -
+                type: X86_OP_REG
+                reg: eax
+                size: 4
+                access: CS_AC_READ_WRITE
+              -
+                type: X86_OP_REG
+                reg: ebx
+                size: 4
+                access: CS_AC_READ
+            eflags: [  X86_EFLAGS_MODIFY_AF, X86_EFLAGS_MODIFY_CF, X86_EFLAGS_MODIFY_SF, X86_EFLAGS_MODIFY_ZF, X86_EFLAGS_MODIFY_PF, X86_EFLAGS_MODIFY_OF ]
+          regs_read: [ eax, ebx ]
+          regs_write: [ eflags, eax ]
+      -
+        asm_text: "add esi, 0x1234"
+        details:
+          x86:
+            prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ]
+            opcode: [ 0x81, 0x00, 0x00, 0x00 ]
+            rex: 0x0
+            addr_size: 4
+            modrm: 0xc6
+            enc_modrm_offset: 0x1
+            disp: 0x0
+            sib: 0x0
+            operands:
+              -
+                type: X86_OP_REG
+                reg: esi
+                size: 4
+                access: CS_AC_READ_WRITE
+              -
+                type: X86_OP_IMM
+                imm: 0x1234
+                size: 4
+            eflags: [  X86_EFLAGS_MODIFY_AF, X86_EFLAGS_MODIFY_CF, X86_EFLAGS_MODIFY_SF, X86_EFLAGS_MODIFY_ZF, X86_EFLAGS_MODIFY_PF, X86_EFLAGS_MODIFY_OF ]
+          regs_read: [ esi ]
+          regs_write: [ eflags, esi ]
+      -
+        asm_text: "add eax, 0x123"
+        details:
+          x86:
+            prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ]
+            opcode: [ 0x05, 0x00, 0x00, 0x00 ]
+            rex: 0x0
+            addr_size: 4
+            modrm: 0x0
+            disp: 0x0
+            sib: 0x0
+            operands:
+              -
+                type: X86_OP_REG
+                reg: eax
+                size: 4
+                access: CS_AC_READ_WRITE
+              -
+                type: X86_OP_IMM
+                imm: 0x123
+                size: 4
+            eflags: [  X86_EFLAGS_MODIFY_AF, X86_EFLAGS_MODIFY_CF, X86_EFLAGS_MODIFY_SF, X86_EFLAGS_MODIFY_ZF, X86_EFLAGS_MODIFY_PF, X86_EFLAGS_MODIFY_OF ]
+          regs_read: [ eax ]
+          regs_write: [ eflags, eax ]
+      -
+        asm_text: "mov eax, dword ptr ss:[ecx + edx*4 + 0x123]"
+        details:
+          x86:
+            prefix: [ X86_PREFIX_0, X86_PREFIX_SS, X86_PREFIX_0, X86_PREFIX_0 ]
+            opcode: [ 0x8b, 0x00, 0x00, 0x00 ]
+            rex: 0x0
+            addr_size: 4
+            modrm: 0x84
+            enc_modrm_offset: 0x2
+            disp: 0x123
+            enc_disp_offset: 0x4
+            enc_disp_size: 0x4
+            sib: 0x91
+            sib_base: ecx
+            sib_index: edx
+            sib_scale: 4
+            operands:
+              -
+                type: X86_OP_REG
+                reg: eax
+                size: 4
+                access: CS_AC_WRITE
+              -
+                type: X86_OP_MEM
+                mem_segment: ss
+                mem_base: ecx
+                mem_index: edx
+                mem_scale: 4
+                mem_disp: 0x123
+                size: 4
+                access: CS_AC_READ
+          regs_read: [ ss, ecx, edx ]
+          regs_write: [ eax ]
+      -
+        asm_text: "inc ecx"
+        details:
+          x86:
+            prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ]
+            opcode: [ 0x41, 0x00, 0x00, 0x00 ]
+            rex: 0x0
+            addr_size: 4
+            modrm: 0x0
+            disp: 0x0
+            sib: 0x0
+            operands:
+              -
+                type: X86_OP_REG
+                reg: ecx
+                size: 4
+                access: CS_AC_READ_WRITE
+            eflags: [  X86_EFLAGS_MODIFY_AF, X86_EFLAGS_MODIFY_SF, X86_EFLAGS_MODIFY_ZF, X86_EFLAGS_MODIFY_PF, X86_EFLAGS_MODIFY_OF ]
+          regs_read: [ ecx ]
+          regs_write: [ eflags, ecx ]
+      -
+        asm_text: "lea eax, [ecx + edi + 0x6789]"
+        details:
+          x86:
+            prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ]
+            opcode: [ 0x8d, 0x00, 0x00, 0x00 ]
+            rex: 0x0
+            addr_size: 4
+            modrm: 0x84
+            enc_modrm_offset: 0x1
+            disp: 0x6789
+            enc_disp_offset: 0x3
+            enc_disp_size: 0x4
+            sib: 0x39
+            sib_base: ecx
+            sib_index: edi
+            sib_scale: 1
+            operands:
+              -
+                type: X86_OP_REG
+                reg: eax
+                size: 4
+                access: CS_AC_WRITE
+              -
+                type: X86_OP_MEM
+                mem_base: ecx
+                mem_index: edi
+                mem_disp: 0x6789
+                size: 4
+                access: CS_AC_READ
+          regs_read: [ ecx, edi ]
+          regs_write: [ eax ]
+      -
+        asm_text: "lea eax, [edi + 0x6789]"
+        details:
+          x86:
+            prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ]
+            opcode: [ 0x8d, 0x00, 0x00, 0x00 ]
+            rex: 0x0
+            addr_size: 4
+            modrm: 0x87
+            enc_modrm_offset: 0x1
+            disp: 0x6789
+            enc_disp_offset: 0x2
+            enc_disp_size: 0x4
+            sib: 0x0
+            operands:
+              -
+                type: X86_OP_REG
+                reg: eax
+                size: 4
+                access: CS_AC_WRITE
+              -
+                type: X86_OP_MEM
+                mem_base: edi
+                mem_disp: 0x6789
+                size: 4
+                access: CS_AC_READ
+          regs_read: [ edi ]
+          regs_write: [ eax ]
+      -
+        asm_text: "mov ah, 0xc6"
+        details:
+          x86:
+            prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ]
+            opcode: [ 0xb4, 0x00, 0x00, 0x00 ]
+            rex: 0x0
+            addr_size: 4
+            modrm: 0x0
+            disp: 0x0
+            sib: 0x0
+            operands:
+              -
+                type: X86_OP_REG
+                reg: ah
+                size: 1
+                access: CS_AC_WRITE
+              -
+                type: X86_OP_IMM
+                imm: 0xc6
+                size: 1
+          regs_write: [ ah ]
+      -
+        asm_text: "jmp 0xdeadcf18"
+        details:
+          x86:
+            prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ]
+            opcode: [ 0xe9, 0x00, 0x00, 0x00 ]
+            rex: 0x0
+            addr_size: 4
+            modrm: 0x0
+            disp: 0x0
+            sib: 0x0
+            operands:
+              -
+                type: X86_OP_IMM
+                imm: 0xdeadcf18
+                size: 4
+      -
+        asm_text: "jmp dword ptr [eax + 0x123]"
+        details:
+          x86:
+            prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ]
+            opcode: [ 0xff, 0x00, 0x00, 0x00 ]
+            rex: 0x0
+            addr_size: 4
+            modrm: 0xa0
+            enc_modrm_offset: 0x1
+            disp: 0x123
+            enc_disp_offset: 0x2
+            enc_disp_size: 0x4
+            sib: 0x0
+            operands:
+              -
+                type: X86_OP_MEM
+                mem_base: eax
+                mem_disp: 0x123
+                size: 4
+                access: CS_AC_READ
+          regs_read: [ eax ]
+      -
+        asm_text: "call 0xdeadcf18"
+        details:
+          x86:
+            prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ]
+            opcode: [ 0xe8, 0x00, 0x00, 0x00 ]
+            rex: 0x0
+            addr_size: 4
+            modrm: 0x0
+            disp: 0x0
+            sib: 0x0
+            operands:
+              -
+                type: X86_OP_IMM
+                imm: 0xdeadcf18
+                size: 4
+          regs_read: [ esp, eip ]
+          regs_write: [ esp ]
+      -
+        asm_text: "je 0x103a"
+        details:
+          x86:
+            prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ]
+            opcode: [ 0x74, 0x00, 0x00, 0x00 ]
+            rex: 0x0
+            addr_size: 4
+            modrm: 0x0
+            disp: 0x0
+            sib: 0x0
+            operands:
+              -
+                type: X86_OP_IMM
+                imm: 0x103a
+                size: 4
+            eflags: [  X86_EFLAGS_TEST_ZF ]
+          regs_read: [ eflags ]
+  -
+    input:
+      bytes: [0x55, 0x48, 0x8b, 0x05, 0xb8, 0x13, 0x00, 0x00, 0xe9, 0xea, 0xbe, 0xad, 0xde, 0xff, 0x25, 0x23, 0x01, 0x00, 0x00, 0xe8, 0xdf, 0xbe, 0xad, 0xde, 0x74, 0xff, ]
+      arch: "x86"
+      options: [ CS_OPT_DETAIL, CS_MODE_64 ]
+      address: 0x1000
+    expected:
+      insns:
+      -
+        asm_text: "push rbp"
+        details:
+          x86:
+            prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ]
+            opcode: [ 0x55, 0x00, 0x00, 0x00 ]
+            rex: 0x0
+            addr_size: 8
+            modrm: 0x0
+            disp: 0x0
+            sib: 0x0
+            operands:
+              -
+                type: X86_OP_REG
+                reg: rbp
+                size: 8
+                access: CS_AC_READ
+          regs_read: [ rsp, rbp ]
+          regs_write: [ rsp ]
+      -
+        asm_text: "mov rax, qword ptr [rip + 0x13b8]"
+        details:
+          x86:
+            prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ]
+            opcode: [ 0x8b, 0x00, 0x00, 0x00 ]
+            rex: 0x48
+            addr_size: 8
+            modrm: 0x5
+            enc_modrm_offset: 0x2
+            disp: 0x13b8
+            enc_disp_offset: 0x3
+            enc_disp_size: 0x4
+            sib: 0x0
+            operands:
+              -
+                type: X86_OP_REG
+                reg: rax
+                size: 8
+                access: CS_AC_WRITE
+              -
+                type: X86_OP_MEM
+                mem_base: rip
+                mem_disp: 0x13b8
+                size: 8
+                access: CS_AC_READ
+          regs_read: [ rip ]
+          regs_write: [ rax ]
+      -
+        asm_text: "jmp 0xffffffffdeadcef7"
+        details:
+          x86:
+            prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ]
+            opcode: [ 0xe9, 0x00, 0x00, 0x00 ]
+            rex: 0x0
+            addr_size: 8
+            modrm: 0x0
+            disp: 0x0
+            sib: 0x0
+            operands:
+              -
+                type: X86_OP_IMM
+                imm: -0x21523109
+                size: 8
+      -
+        asm_text: "jmp qword ptr [rip + 0x123]"
+        details:
+          x86:
+            prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ]
+            opcode: [ 0xff, 0x00, 0x00, 0x00 ]
+            rex: 0x0
+            addr_size: 8
+            modrm: 0x25
+            enc_modrm_offset: 0x1
+            disp: 0x123
+            enc_disp_offset: 0x2
+            enc_disp_size: 0x4
+            sib: 0x0
+            operands:
+              -
+                type: X86_OP_MEM
+                mem_base: rip
+                mem_disp: 0x123
+                size: 8
+                access: CS_AC_READ
+          regs_read: [ rip ]
+      -
+        asm_text: "call 0xffffffffdeadcef7"
+        details:
+          x86:
+            prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ]
+            opcode: [ 0xe8, 0x00, 0x00, 0x00 ]
+            rex: 0x0
+            addr_size: 8
+            modrm: 0x0
+            disp: 0x0
+            sib: 0x0
+            operands:
+              -
+                type: X86_OP_IMM
+                imm: -0x21523109
+                size: 8
+          regs_read: [ rsp, rip ]
+          regs_write: [ rsp ]
+      -
+        asm_text: "je 0x1019"
+        details:
+          x86:
+            prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ]
+            opcode: [ 0x74, 0x00, 0x00, 0x00 ]
+            rex: 0x0
+            addr_size: 8
+            modrm: 0x0
+            disp: 0x0
+            sib: 0x0
+            operands:
+              -
+                type: X86_OP_IMM
+                imm: 0x1019
+                size: 8
+            eflags: [  X86_EFLAGS_TEST_ZF ]
+          regs_read: [ rflags ]
diff --git a/tests/details/xcore.yaml b/tests/details/xcore.yaml
new file mode 100644
index 000000000..bf5a348fb
--- /dev/null
+++ b/tests/details/xcore.yaml
@@ -0,0 +1,128 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0xfe, 0x0f, 0xfe, 0x17, 0x13, 0x17, 0xc6, 0xfe, 0xec, 0x17, 0x97, 0xf8, 0xec, 0x4f, 0x1f, 0xfd, 0xec, 0x37, 0x07, 0xf2, 0x45, 0x5b, 0xf9, 0xfa, 0x02, 0x06, 0x1b, 0x10, 0x09, 0xfd, 0xec, 0xa7  ]
+      arch: "xcore"
+      options: [ CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "get r11, ed"
+        details:
+          xcore:
+            operands:
+              -
+                type: XCORE_OP_REG
+                reg: r11
+              -
+                type: XCORE_OP_REG
+                reg: ed
+      -
+        asm_text: "ldw et, sp[4]"
+        details:
+          xcore:
+            operands:
+              -
+                type: XCORE_OP_REG
+                reg: et
+              -
+                type: XCORE_OP_MEM
+                mem_base: sp
+                mem_disp: 0x4
+      -
+        asm_text: "setd res[r3], r4"
+        details:
+          xcore:
+            operands:
+              -
+                type: XCORE_OP_REG
+                reg: r4
+      -
+        asm_text: "init t[r2]:lr, r1"
+        details:
+          xcore:
+            operands:
+              -
+                type: XCORE_OP_MEM
+                mem_base: r2
+                mem_index: lr
+              -
+                type: XCORE_OP_REG
+                reg: r1
+      -
+        asm_text: "divu r9, r1, r3"
+        details:
+          xcore:
+            operands:
+              -
+                type: XCORE_OP_REG
+                reg: r9
+              -
+                type: XCORE_OP_REG
+                reg: r1
+              -
+                type: XCORE_OP_REG
+                reg: r3
+      -
+        asm_text: "lda16 r9, r3[-r11]"
+        details:
+          xcore:
+            operands:
+              -
+                type: XCORE_OP_REG
+                reg: r9
+      -
+        asm_text: "ldw dp, dp[0x81c5]"
+        details:
+          xcore:
+            operands:
+              -
+                type: XCORE_OP_REG
+                reg: dp
+      -
+        asm_text: "lmul r11, r0, r2, r5, r8, r10"
+        details:
+          xcore:
+            operands:
+              -
+                type: XCORE_OP_REG
+                reg: r11
+              -
+                type: XCORE_OP_REG
+                reg: r0
+              -
+                type: XCORE_OP_REG
+                reg: r2
+              -
+                type: XCORE_OP_REG
+                reg: r5
+              -
+                type: XCORE_OP_REG
+                reg: r8
+              -
+                type: XCORE_OP_REG
+                reg: r10
+      -
+        asm_text: "add r1, r2, r3"
+        details:
+          xcore:
+            operands:
+              -
+                type: XCORE_OP_REG
+                reg: r1
+              -
+                type: XCORE_OP_REG
+                reg: r2
+              -
+                type: XCORE_OP_REG
+                reg: r3
+      -
+        asm_text: "ldaw r8, r2[-9]"
+        details:
+          xcore:
+            operands:
+              -
+                type: XCORE_OP_REG
+                reg: r8
+
diff --git a/tests/features/skipdata.yaml b/tests/features/skipdata.yaml
new file mode 100644
index 000000000..133803d94
--- /dev/null
+++ b/tests/features/skipdata.yaml
@@ -0,0 +1,49 @@
+test_cases:
+  -
+    input:
+      bytes: [ 0x8d, 0x4c, 0x32, 0x08, 0x01, 0xd8, 0x81, 0xc6, 0x34, 0x12, 0x00, 0x00, 0x00, 0x91, 0x92  ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_32, CS_OPT_SKIPDATA ]
+      address: 0x1000
+    expected:
+      insns:
+      -
+        asm_text: "lea ecx, [edx + esi + 8]"
+      -
+        asm_text: "add eax, ebx"
+      -
+        asm_text: "add esi, 0x1234"
+      -
+        asm_text: ".byte 0x00"
+      -
+        asm_text: "xchg ecx, eax"
+      -
+        asm_text: "xchg edx, eax"
+  -
+    input:
+      bytes: [ 0xed, 0x00, 0x00, 0x00, 0x00, 0x1a, 0x5a, 0x0f, 0x1f, 0xff, 0xc2, 0x09, 0x80, 0x00, 0x00, 0x00, 0x07, 0xf7, 0xeb, 0x2a, 0xff, 0xff, 0x7f, 0x57, 0xe3, 0x01, 0xff, 0xff, 0x7f, 0x57, 0xeb, 0x00, 0xf0, 0x00, 0x00, 0x24, 0xb2, 0x4f, 0x00, 0x78  ]
+      arch: "CS_ARCH_ARM"
+      options: [ CS_MODE_ARM, CS_OPT_SKIPDATA ]
+      address: 0x1000
+    expected:
+      insns:
+      -
+        asm_text: "andeq r0, r0, sp, ror #1"
+      -
+        asm_text: "svceq #0x5a1a00"
+      -
+        asm_text: "stmibeq r2, {r0, r1, r2, r3, r4, r8, r9, r10, r11, r12, sp, lr, pc} ^"
+      -
+        asm_text: "andeq r0, r0, r0, lsl #1"
+      -
+        asm_text: "bhs 0xffafec34"
+      -
+        asm_text: ".byte 0xff, 0xff, 0x7f, 0x57"
+      -
+        asm_text: ".byte 0xe3, 0x01, 0xff, 0xff"
+      -
+        asm_text: "rsceq r5, r11, pc, ror r7"
+      -
+        asm_text: "strhs r0, [r0], #-0xf0"
+      -
+        asm_text: "stmdavc r0, {r1, r4, r5, r7, r8, r9, r10, r11, lr}"
diff --git a/tests/integration/CMakeLists.txt b/tests/integration/CMakeLists.txt
new file mode 100644
index 000000000..4aee94820
--- /dev/null
+++ b/tests/integration/CMakeLists.txt
@@ -0,0 +1,17 @@
+cmake_minimum_required(VERSION 3.15)
+
+# Old integration tests.
+if (CAPSTONE_BUILD_LEGACY_TESTS)
+  enable_testing()
+  set(TEST_SOURCES test_skipdata.c test_iter.c)
+  if(CAPSTONE_X86_SUPPORT)
+    set(TEST_SOURCES ${TEST_SOURCES} test_customized_mnem.c)
+  endif()
+
+  foreach(TSRC ${TEST_SOURCES})
+      string(REGEX REPLACE ".c$" "" TBIN ${TSRC})
+      add_executable(${TBIN} "${TESTS_INTEGRATION_DIR}/${TSRC}")
+      target_link_libraries(${TBIN} PRIVATE capstone)
+      add_test(NAME "legacy_${TBIN}" COMMAND ${TBIN})
+  endforeach()
+endif()
diff --git a/tests/integration/README.md b/tests/integration/README.md
new file mode 100644
index 000000000..bac4202d1
--- /dev/null
+++ b/tests/integration/README.md
@@ -0,0 +1,12 @@
+This directory contains some test code to show how to use Capstone API.
+
+- test_iter.c:
+  This code shows how to use the API cs_disasm_iter() to decode one instruction at
+  a time inside a loop.
+
+- test_customized_mnem.c:
+  This code shows how to use MNEMONIC option to customize instruction mnemonic
+  at run-time, and then how to reset the engine to use the default mnemonic.
+
+- test_winkernel.cpp
+  This code shows how to use Capstone from a Windows driver.
diff --git a/tests/test_customized_mnem.c b/tests/integration/test_customized_mnem.c
similarity index 100%
rename from tests/test_customized_mnem.c
rename to tests/integration/test_customized_mnem.c
diff --git a/tests/test_iter.c b/tests/integration/test_iter.c
similarity index 100%
rename from tests/test_iter.c
rename to tests/integration/test_iter.c
diff --git a/tests/test_skipdata.c b/tests/integration/test_skipdata.c
similarity index 100%
rename from tests/test_skipdata.c
rename to tests/integration/test_skipdata.c
diff --git a/tests/test_winkernel.cpp b/tests/integration/test_winkernel.cpp
similarity index 100%
rename from tests/test_winkernel.cpp
rename to tests/integration/test_winkernel.cpp
diff --git a/tests/issues/issues.yaml b/tests/issues/issues.yaml
new file mode 100644
index 000000000..fe7a8c5b1
--- /dev/null
+++ b/tests/issues/issues.yaml
@@ -0,0 +1,4817 @@
+test_cases:
+  -
+    input:
+      name: "issue 2323 eBPF bswap16 instruction"
+      bytes: [ 0xd7,0x53,0x3f,0x0c,0x10,0x00,0x00,0x00 ]
+      arch: "CS_ARCH_BPF"
+      options: [ CS_MODE_LITTLE_ENDIAN, CS_MODE_BPF_EXTENDED, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "bswap16 r3"
+  -
+    input:
+      name: "issue 2323 eBPF bswap32 instruction"
+      bytes: [ 0xd7,0x53,0x3f,0x0c,0x20,0x00,0x00,0x00 ]
+      arch: "CS_ARCH_BPF"
+      options: [ CS_MODE_LITTLE_ENDIAN, CS_MODE_BPF_EXTENDED, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "bswap32 r3"
+  -
+    input:
+      name: "issue 2323 eBPF bswap64 instruction"
+      bytes: [ 0xd7,0x53,0x3f,0x0c,0x40,0x00,0x00,0x00 ]
+      arch: "CS_ARCH_BPF"
+      options: [ CS_MODE_LITTLE_ENDIAN, CS_MODE_BPF_EXTENDED, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "bswap64 r3"
+  -
+    input:
+      name: "issue 2258 vcmpunordss incorrect read/modified register"
+      bytes: [ 0x62,0xd1,0x56,0x08,0xc2,0xca,0x03 ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_64, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "vcmpunordss k1, xmm5, xmm10"
+        details:
+          x86:
+            operands:
+              -
+                type: X86_OP_REG
+                access: CS_AC_WRITE
+              -
+                type: X86_OP_REG
+                access: CS_AC_READ
+              -
+                type: X86_OP_REG
+                access: CS_AC_READ
+  -
+    input:
+      name: "issue 2062 repz Prefix"
+      bytes: [ 0xf3,0xc3 ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_64, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "repz ret"
+        details:
+          x86:
+            prefix: [ X86_PREFIX_REP, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ]
+  -
+    input:
+      name: "issue 2007 RISCV64 instruction groups"
+      bytes: [ 0x63,0x04,0x03,0x00 ]
+      arch: "CS_ARCH_RISCV"
+      options: [ CS_MODE_RISCV64, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "beqz t1, 8"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: t1
+              -
+                type: RISCV_OP_IMM
+                imm: 0x8
+          groups: [ branch_relative, jump ]
+  -
+    input:
+      name: "issue 2007 RISCV64 instruction groups"
+      bytes: [ 0x73,0x00,0x00,0x00 ]
+      arch: "CS_ARCH_RISCV"
+      options: [ CS_MODE_RISCV64, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "ecall"
+        details:
+          groups: [ int ]
+  -
+    input:
+      name: "issue 2007 RISCV64 instruction groups"
+      bytes: [ 0xef,0x00,0x40,0x00 ]
+      arch: "CS_ARCH_RISCV"
+      options: [ CS_MODE_RISCV64, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "jal 4"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_IMM
+                imm: 0x4
+          groups: [ call ]
+  -
+    input:
+      name: "issue 2007 RISCV32 instruction groups"
+      bytes: [ 0x63,0x04,0x03,0x00 ]
+      arch: "CS_ARCH_RISCV"
+      options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "beqz t1, 8"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: t1
+              -
+                type: RISCV_OP_IMM
+                imm: 0x8
+          groups: [ branch_relative, jump ]
+  -
+    input:
+      name: "issue 2007 RISCV32 instruction groups"
+      bytes: [ 0x73,0x00,0x00,0x00 ]
+      arch: "CS_ARCH_RISCV"
+      options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "ecall"
+        details:
+          groups: [ int ]
+  -
+    input:
+      name: "issue 2007 RISCV32 instruction groups"
+      bytes: [ 0xef,0x00,0x40,0x00 ]
+      arch: "CS_ARCH_RISCV"
+      options: [ CS_MODE_RISCV32, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "jal 4"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_IMM
+                imm: 0x4
+          groups: [ call ]
+  -
+    input:
+      name: "issue 2007 RISCV32 instruction groups"
+      bytes: [ 0x11,0x20 ]
+      arch: "CS_ARCH_RISCV"
+      options: [ CS_MODE_RISCV32, CS_MODE_RISCVC, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "c.jal 4"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_IMM
+                imm: 0x4
+          groups: [ hasStdExtC, isrv32, call ]
+  -
+    input:
+      name: "issue 2007 RISCV32 instruction groups"
+      bytes: [ 0x91,0xc1 ]
+      arch: "CS_ARCH_RISCV"
+      options: [ CS_MODE_RISCV32, CS_MODE_RISCVC, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "c.beqz a1, 4"
+        details:
+          riscv:
+            operands:
+              -
+                type: RISCV_OP_REG
+                reg: a1
+              -
+                type: RISCV_OP_IMM
+                imm: 0x4
+          groups: [ hasStdExtC, branch_relative, jump ]
+  -
+    input:
+      name: "issue 1997 notrack jmp"
+      bytes: [ 0x3e,0xff,0xe0 ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_64 ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "notrack jmp rax"
+  -
+    input:
+      name: "issue 1997 notrack call"
+      bytes: [ 0x3e,0xff,0xd0 ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_64 ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "notrack call rax"
+  -
+    input:
+      name: "issue 1924 SME Index instruction alias printing is not always valid"
+      bytes: [ 0x02,0x00,0x9f,0xe0 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "ld1w {za0h.s[w12, 2]}, p0/z, [x0]"
+        details:
+          aarch64:
+            operands:
+              -
+                type: AARCH64_OP_SME
+                sme:
+                  type: AARCH64_SME_MATRIX_SLICE_REG
+                  tile: za0.s
+                  slice_reg: w12
+                  slice_offset_imm: 2
+                  is_vertical: -1
+                access: CS_AC_WRITE
+                vas: AARCH64LAYOUT_VL_S
+              -
+                type: AARCH64_OP_PRED
+                pred_reg: p0
+                access: CS_AC_READ
+              -
+                type: AARCH64_OP_MEM
+                mem_base: x0
+                access: CS_AC_READ
+          regs_read: [ w12, p0, x0 ]
+          regs_write: [ za0.s ]
+          groups: [ HasSME ]
+  -
+    input:
+      name: "issue 1912 PPC register name"
+      bytes: [ 0x2d,0x03,0x00,0x80 ]
+      arch: "CS_ARCH_PPC"
+      options: [ CS_MODE_BIG_ENDIAN ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "cmpwi cr2, r3, 0x80"
+  -
+    input:
+      name: "issue 1912 PPC no register name"
+      bytes: [ 0x2d,0x03,0x00,0x80 ]
+      arch: "CS_ARCH_PPC"
+      options: [ CS_MODE_BIG_ENDIAN, CS_OPT_SYNTAX_NOREGNAME ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "cmpwi 2, 3, 0x80"
+  -
+    input:
+      name: "issue 1902 PPC psq_st negative displacement"
+      bytes: [ 0xf3,0xec,0x0f,0xf8 ]
+      arch: "CS_ARCH_PPC"
+      options: [ CS_MODE_32, CS_MODE_BIG_ENDIAN, CS_MODE_PS, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "psq_st f31, -8(r12), 0, 0"
+        details:
+          ppc:
+            operands:
+              -
+                type: PPC_OP_REG
+                reg: f31
+              -
+                type: PPC_OP_MEM
+                mem_base: r12
+                mem_disp: -8
+              -
+                type: PPC_OP_IMM
+                imm: 0x0
+              -
+                type: PPC_OP_IMM
+                imm: 0x0
+  -
+    input:
+      name: "issue 1873 AArch64 missing VAS specifiers in aliased instructions"
+      bytes: [ 0x21,0x04,0x03,0x5e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "mov b1, v1.b[1]"
+        details:
+          aarch64:
+            operands:
+              -
+                type: AARCH64_OP_REG
+              -
+                type: AARCH64_OP_REG
+                vas: AARCH64LAYOUT_VL_B
+                vector_index: 1
+                vector_index_is_set: true
+  -
+    input:
+      name: "issue 1873 AArch64 missing VAS specifiers in aliased instructions"
+      bytes: [ 0xc0,0x1e,0x03,0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "mov v0.b[1], w22"
+        details:
+          aarch64:
+            operands:
+              -
+                type: AARCH64_OP_REG
+                vas: AARCH64LAYOUT_VL_B
+                vector_index: 1
+                vector_index_is_set: true
+              -
+                type: AARCH64_OP_REG
+  -
+    input:
+      name: "issue 1873 AArch64 missing VAS specifiers in aliased instructions"
+      bytes: [ 0xc0,0x1e,0x06,0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "mov v0.h[1], w22"
+        details:
+          aarch64:
+            operands:
+              -
+                type: AARCH64_OP_REG
+                vas: AARCH64LAYOUT_VL_H
+                vector_index: 1
+                vector_index_is_set: true
+              -
+                type: AARCH64_OP_REG
+  -
+    input:
+      name: "issue 1873 AArch64 missing VAS specifiers in aliased instructions"
+      bytes: [ 0xc0,0x1e,0x0c,0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "mov v0.s[1], w22"
+        details:
+          aarch64:
+            operands:
+              -
+                type: AARCH64_OP_REG
+                vas: AARCH64LAYOUT_VL_S
+                vector_index: 1
+                vector_index_is_set: true
+              -
+                type: AARCH64_OP_REG
+  -
+    input:
+      name: "issue 1873 AArch64 missing VAS specifiers in aliased instructions"
+      bytes: [ 0xc0,0x1e,0x18,0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "mov v0.d[1], x22"
+        details:
+          aarch64:
+            operands:
+              -
+                type: AARCH64_OP_REG
+                vas: AARCH64LAYOUT_VL_D
+                vector_index: 1
+                vector_index_is_set: true
+              -
+                type: AARCH64_OP_REG
+  -
+    input:
+      name: "issue 1873 AArch64 missing VAS specifiers in aliased instructions"
+      bytes: [ 0x20,0x0c,0x03,0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "mov v0.b[1], v1.b[1]"
+        details:
+          aarch64:
+            operands:
+              -
+                type: AARCH64_OP_REG
+                vas: AARCH64LAYOUT_VL_B
+                vector_index: 1
+                vector_index_is_set: true
+              -
+                type: AARCH64_OP_REG
+                vas: AARCH64LAYOUT_VL_B
+                vector_index: 1
+                vector_index_is_set: true
+  -
+    input:
+      name: "issue 1873 AArch64 missing VAS specifiers in aliased instructions"
+      bytes: [ 0x20,0x14,0x06,0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "mov v0.h[1], v1.h[1]"
+        details:
+          aarch64:
+            operands:
+              -
+                type: AARCH64_OP_REG
+                vas: AARCH64LAYOUT_VL_H
+                vector_index: 1
+                vector_index_is_set: true
+              -
+                type: AARCH64_OP_REG
+                vas: AARCH64LAYOUT_VL_H
+                vector_index: 1
+                vector_index_is_set: true
+  -
+    input:
+      name: "issue 1873 AArch64 missing VAS specifiers in aliased instructions"
+      bytes: [ 0x20,0x24,0x0c,0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "mov v0.s[1], v1.s[1]"
+        details:
+          aarch64:
+            operands:
+              -
+                type: AARCH64_OP_REG
+                vas: AARCH64LAYOUT_VL_S
+                vector_index: 1
+                vector_index_is_set: true
+              -
+                type: AARCH64_OP_REG
+                vas: AARCH64LAYOUT_VL_S
+                vector_index: 1
+                vector_index_is_set: true
+  -
+    input:
+      name: "issue 1873 AArch64 missing VAS specifiers in aliased instructions"
+      bytes: [ 0x20,0x44,0x18,0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "mov v0.d[1], v1.d[1]"
+        details:
+          aarch64:
+            operands:
+              -
+                type: AARCH64_OP_REG
+                vas: AARCH64LAYOUT_VL_D
+                vector_index: 1
+                vector_index_is_set: true
+              -
+                type: AARCH64_OP_REG
+                vas: AARCH64LAYOUT_VL_D
+                vector_index: 1
+                vector_index_is_set: true
+  -
+    input:
+      name: "issue 1873 AArch64 missing VAS specifiers in aliased instructions"
+      bytes: [ 0x20,0x3c,0x0c,0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "mov w0, v1.s[1]"
+        details:
+          aarch64:
+            operands:
+              -
+                type: AARCH64_OP_REG
+              -
+                type: AARCH64_OP_REG
+                vas: AARCH64LAYOUT_VL_S
+                vector_index: 1
+                vector_index_is_set: true
+  -
+    input:
+      name: "issue 1873 AArch64 missing VAS specifiers in aliased instructions"
+      bytes: [ 0x20,0x3c,0x0c,0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "mov w0, v1.s[1]"
+        details:
+          aarch64:
+            operands:
+              -
+                type: AARCH64_OP_REG
+              -
+                type: AARCH64_OP_REG
+                vas: AARCH64LAYOUT_VL_S
+                vector_index: 1
+                vector_index_is_set: true
+  -
+    input:
+      name: "issue 1873 AArch64 missing VAS specifiers in aliased instructions"
+      bytes: [ 0x20,0x3c,0x18,0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "mov x0, v1.d[1]"
+        details:
+          aarch64:
+            operands:
+              -
+                type: AARCH64_OP_REG
+              -
+                type: AARCH64_OP_REG
+                vas: AARCH64LAYOUT_VL_D
+                vector_index: 1
+                vector_index_is_set: true
+  -
+    input:
+      name: "issue 1873 AArch64 missing VAS specifiers in aliased instructions"
+      bytes: [ 0x20,0x3c,0x18,0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "mov x0, v1.d[1]"
+        details:
+          aarch64:
+            operands:
+              -
+                type: AARCH64_OP_REG
+              -
+                type: AARCH64_OP_REG
+                vas: AARCH64LAYOUT_VL_D
+                vector_index: 1
+                vector_index_is_set: true
+  -
+    input:
+      name: "issue 1873 AArch64 missing VAS specifiers in aliased instructions"
+      bytes: [ 0x00,0xc0,0x50,0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "fmov z0.h, p0/m, #2.00000000"
+        details:
+          aarch64:
+            operands:
+              -
+                type: AARCH64_OP_REG
+                vas: AARCH64LAYOUT_VL_H
+              -
+                type: AARCH64_OP_PRED
+              -
+                type: AARCH64_OP_FP
+                fp: 2.0
+  -
+    input:
+      name: "issue 1873 AArch64 missing VAS specifiers in aliased instructions"
+      bytes: [ 0x00,0xc0,0x79,0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "fmov z0.h, #2.00000000"
+        details:
+          aarch64:
+            operands:
+              -
+                type: AARCH64_OP_REG
+                vas: AARCH64LAYOUT_VL_H
+              -
+                type: AARCH64_OP_FP
+                fp: 2.0
+  -
+    input:
+      name: "issue 1873 AArch64 missing VAS specifiers in aliased instructions"
+      bytes: [ 0xa1,0xca,0xf8,0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "mov z1.d, #0x55"
+        details:
+          aarch64:
+            operands:
+              -
+                type: AARCH64_OP_REG
+                vas: AARCH64LAYOUT_VL_D
+              -
+                type: AARCH64_OP_IMM
+                imm: 0x55
+  -
+    input:
+      name: "issue 1873 AArch64 missing VAS specifiers in aliased instructions"
+      bytes: [ 0x21,0x44,0x81,0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "mov p1.b, p1.b"
+        details:
+          aarch64:
+            operands:
+              -
+                type: AARCH64_OP_PRED
+                vas: AARCH64LAYOUT_VL_B
+              -
+                type: AARCH64_OP_PRED
+                vas: AARCH64LAYOUT_VL_B
+  -
+    input:
+      name: "issue 1873 AArch64 missing VAS specifiers in aliased instructions"
+      bytes: [ 0x21,0x40,0x51,0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "mov z1.h, p1/m, #1"
+        details:
+          aarch64:
+            operands:
+              -
+                type: AARCH64_OP_REG
+                vas: AARCH64LAYOUT_VL_H
+              -
+                type: AARCH64_OP_PRED
+              -
+                type: AARCH64_OP_IMM
+                imm: 0x1
+  -
+    input:
+      name: "issue 1873 AArch64 missing VAS specifiers in aliased instructions"
+      bytes: [ 0x21,0x00,0x51,0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "mov z1.h, p1/z, #1"
+        details:
+          aarch64:
+            operands:
+              -
+                type: AARCH64_OP_REG
+                vas: AARCH64LAYOUT_VL_H
+              -
+                type: AARCH64_OP_PRED
+              -
+                type: AARCH64_OP_IMM
+                imm: 0x1
+  -
+    input:
+      name: "issue 1873 AArch64 missing VAS specifiers in aliased instructions"
+      bytes: [ 0x20,0xc0,0x38,0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "mov z0.b, #1"
+        details:
+          aarch64:
+            operands:
+              -
+                type: AARCH64_OP_REG
+                vas: AARCH64LAYOUT_VL_B
+              -
+                type: AARCH64_OP_IMM
+                imm: 0x1
+  -
+    input:
+      name: "issue 1873 AArch64 missing VAS specifiers in aliased instructions"
+      bytes: [ 0x71,0x4a,0x01,0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "mov p1.b, p2/m, p3.b"
+        details:
+          aarch64:
+            operands:
+              -
+                type: AARCH64_OP_PRED
+                vas: AARCH64LAYOUT_VL_B
+              -
+                type: AARCH64_OP_PRED
+              -
+                type: AARCH64_OP_PRED
+                vas: AARCH64LAYOUT_VL_B
+  -
+    input:
+      name: "issue 1873 AArch64 missing VAS specifiers in aliased instructions"
+      bytes: [ 0x61,0x48,0x03,0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "mov p1.b, p2/z, p3.b"
+        details:
+          aarch64:
+            operands:
+              -
+                type: AARCH64_OP_PRED
+                vas: AARCH64LAYOUT_VL_B
+              -
+                type: AARCH64_OP_PRED
+              -
+                type: AARCH64_OP_PRED
+                vas: AARCH64LAYOUT_VL_B
+  -
+    input:
+      name: "issue 1873 AArch64 missing VAS specifiers in aliased instructions"
+      bytes: [ 0x21,0xa8,0x28,0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "mov z1.b, p2/m, w1"
+        details:
+          aarch64:
+            operands:
+              -
+                type: AARCH64_OP_REG
+                vas: AARCH64LAYOUT_VL_B
+              -
+                type: AARCH64_OP_PRED
+              -
+                type: AARCH64_OP_REG
+  -
+    input:
+      name: "issue 1873 AArch64 missing VAS specifiers in aliased instructions"
+      bytes: [ 0x21,0x38,0x20,0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "mov z1.b, w1"
+        details:
+          aarch64:
+            operands:
+              -
+                type: AARCH64_OP_REG
+                vas: AARCH64LAYOUT_VL_B
+              -
+                type: AARCH64_OP_REG
+  -
+    input:
+      name: "issue 1873 AArch64 missing VAS specifiers in aliased instructions"
+      bytes: [ 0x01,0x88,0x20,0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "mov z1.b, p2/m, b0"
+        details:
+          aarch64:
+            operands:
+              -
+                type: AARCH64_OP_REG
+                vas: AARCH64LAYOUT_VL_B
+              -
+                type: AARCH64_OP_PRED
+              -
+                type: AARCH64_OP_REG
+  -
+    input:
+      name: "issue 1873 AArch64 missing VAS specifiers in aliased instructions"
+      bytes: [ 0x00,0x20,0x21,0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "mov z0.b, b0"
+        details:
+          aarch64:
+            operands:
+              -
+                type: AARCH64_OP_REG
+                vas: AARCH64LAYOUT_VL_B
+              -
+                type: AARCH64_OP_REG
+  -
+    input:
+      name: "issue 1873 AArch64 missing VAS specifiers in aliased instructions"
+      bytes: [ 0x00,0x20,0x23,0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "mov z0.b, z0.b[1]"
+        details:
+          aarch64:
+            operands:
+              -
+                type: AARCH64_OP_REG
+                vas: AARCH64LAYOUT_VL_B
+              -
+                type: AARCH64_OP_REG
+                vas: AARCH64LAYOUT_VL_B
+                vector_index: 1
+                vector_index_is_set: true
+  -
+    input:
+      name: "issue 1873 AArch64 missing VAS specifiers in aliased instructions"
+      bytes: [ 0x20,0xc4,0x20,0x05 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "mov z0.b, p1/m, z1.b"
+        details:
+          aarch64:
+            operands:
+              -
+                type: AARCH64_OP_REG
+                vas: AARCH64LAYOUT_VL_B
+              -
+                type: AARCH64_OP_PRED
+              -
+                type: AARCH64_OP_REG
+                vas: AARCH64LAYOUT_VL_B
+  -
+    input:
+      name: "issue 1873 AArch64 missing VAS specifiers in aliased instructions"
+      bytes: [ 0x20,0x30,0x61,0x04 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "mov z0.d, z1.d"
+        details:
+          aarch64:
+            operands:
+              -
+                type: AARCH64_OP_REG
+                vas: AARCH64LAYOUT_VL_D
+              -
+                type: AARCH64_OP_REG
+                vas: AARCH64LAYOUT_VL_D
+  -
+    input:
+      name: "issue 1873 AArch64 missing VAS specifiers in aliased instructions"
+      bytes: [ 0x40,0x44,0x42,0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "movs p0.b, p1/z, p2.b"
+        details:
+          aarch64:
+            operands:
+              -
+                type: AARCH64_OP_PRED
+                vas: AARCH64LAYOUT_VL_B
+              -
+                type: AARCH64_OP_PRED
+              -
+                type: AARCH64_OP_PRED
+                vas: AARCH64LAYOUT_VL_B
+  -
+    input:
+      name: "issue 1873 AArch64 missing VAS specifiers in aliased instructions"
+      bytes: [ 0x20,0x44,0xc1,0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "movs p0.b, p1.b"
+        details:
+          aarch64:
+            operands:
+              -
+                type: AARCH64_OP_PRED
+                vas: AARCH64LAYOUT_VL_B
+              -
+                type: AARCH64_OP_PRED
+                vas: AARCH64LAYOUT_VL_B
+  -
+    input:
+      name: "issue 1873 AArch64 missing VAS specifiers in aliased instructions"
+      bytes: [ 0x40,0x46,0x01,0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "not p0.b, p1/z, p2.b"
+        details:
+          aarch64:
+            operands:
+              -
+                type: AARCH64_OP_PRED
+                vas: AARCH64LAYOUT_VL_B
+              -
+                type: AARCH64_OP_PRED
+              -
+                type: AARCH64_OP_PRED
+                vas: AARCH64LAYOUT_VL_B
+  -
+    input:
+      name: "issue 1873 AArch64 missing VAS specifiers in aliased instructions"
+      bytes: [ 0x40,0x46,0x41,0x25 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "nots p0.b, p1/z, p2.b"
+        details:
+          aarch64:
+            operands:
+              -
+                type: AARCH64_OP_PRED
+                vas: AARCH64LAYOUT_VL_B
+              -
+                type: AARCH64_OP_PRED
+              -
+                type: AARCH64_OP_PRED
+                vas: AARCH64LAYOUT_VL_B
+  -
+    input:
+      name: "issue 1856 AArch64 SYS instruction operands: tlbi 1 op"
+      bytes: [ 0x1f,0x83,0x08,0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "tlbi vmalle1is"
+        details:
+          aarch64:
+            operands:
+              -
+                type: AARCH64_OP_SYSREG
+                sub_type: AARCH64_OP_TLBI
+                sys_raw_val: 0x418
+  -
+    input:
+      name: "issue 1856 AArch64 SYS instruction operands: tlbi 2 op"
+      bytes: [ 0x22,0x87,0x08,0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "tlbi vae1, x2"
+        details:
+          aarch64:
+            operands:
+              -
+                type: AARCH64_OP_SYSREG
+                sub_type: AARCH64_OP_TLBI
+                sys_raw_val: 0x439
+              -
+                type: AARCH64_OP_REG
+  -
+    input:
+      name: "issue 1856 AArch64 SYS instruction operands: at"
+      bytes: [ 0xc0,0x78,0x0c,0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "at s12e0r, x0"
+        details:
+          aarch64:
+            operands:
+              -
+                type: AARCH64_OP_SYSALIAS
+                sub_type: AARCH64_OP_AT
+                sys_raw_val: 0x23c6
+              -
+                type: AARCH64_OP_REG
+  -
+    input:
+      name: "issue 1856 AArch64 SYS instruction operands: dc"
+      bytes: [ 0x22,0x7b,0x0b,0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "dc cvau, x2"
+        details:
+          aarch64:
+            operands:
+              -
+                type: AARCH64_OP_SYSALIAS
+                sub_type: AARCH64_OP_DC
+                sys_raw_val: 0x1bd9
+              -
+                type: AARCH64_OP_REG
+  -
+    input:
+      name: "issue 1856 AArch64 SYS instruction operands: ic"
+      bytes: [ 0x20,0x75,0x0b,0xd5 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "ic ivau, x0"
+        details:
+          aarch64:
+            operands:
+              -
+                type: AARCH64_OP_SYSREG
+                sub_type: AARCH64_OP_IC
+                sys_raw_val: 0x1ba9
+              -
+                type: AARCH64_OP_REG
+  -
+    input:
+      name: "issue 1843 AArch64 missing VAS specifiers in aliased instructions: mov 16b"
+      bytes: [ 0x40,0x1e,0xb2,0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "mov v0.16b, v18.16b"
+        details:
+          aarch64:
+            operands:
+              -
+                type: AARCH64_OP_REG
+                reg: q0
+                is_vreg: 1
+                vas: AARCH64LAYOUT_VL_16B
+              -
+                type: AARCH64_OP_REG
+                reg: q18
+                is_vreg: 1
+                vas: AARCH64LAYOUT_VL_16B
+  -
+    input:
+      name: "issue 1843 AArch64 missing VAS specifiers in aliased instructions: mov 8b"
+      bytes: [ 0x40,0x1e,0xb2,0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "mov v0.8b, v18.8b"
+        details:
+          aarch64:
+            operands:
+              -
+                type: AARCH64_OP_REG
+                reg: d0
+                is_vreg: 1
+                vas: AARCH64LAYOUT_VL_8B
+              -
+                type: AARCH64_OP_REG
+                reg: d18
+                is_vreg: 1
+                vas: AARCH64LAYOUT_VL_8B
+  -
+    input:
+      name: "issue 1843 AArch64 missing VAS specifiers in aliased instructions: mvn 16b"
+      bytes: [ 0x40,0x5a,0x20,0x6e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "mvn v0.16b, v18.16b"
+        details:
+          aarch64:
+            operands:
+              -
+                type: AARCH64_OP_REG
+                reg: q0
+                is_vreg: 1
+                vas: AARCH64LAYOUT_VL_16B
+              -
+                type: AARCH64_OP_REG
+                reg: q18
+                is_vreg: 1
+                vas: AARCH64LAYOUT_VL_16B
+  -
+    input:
+      name: "issue 1843 AArch64 missing VAS specifiers in aliased instructions: mvn 8b"
+      bytes: [ 0x40,0x5a,0x20,0x2e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "mvn v0.8b, v18.8b"
+        details:
+          aarch64:
+            operands:
+              -
+                type: AARCH64_OP_REG
+                reg: d0
+                is_vreg: 1
+                vas: AARCH64LAYOUT_VL_8B
+              -
+                type: AARCH64_OP_REG
+                reg: d18
+                is_vreg: 1
+                vas: AARCH64LAYOUT_VL_8B
+  -
+    input:
+      name: "issue 1839 AArch64 Incorrect detailed disassembly of ldr"
+      bytes: [ 0x41,0x00,0x40,0xf9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "ldr x1, [x2]"
+        details:
+          aarch64:
+            operands:
+              -
+                type: AARCH64_OP_REG
+                access: CS_AC_WRITE
+              -
+                type: AARCH64_OP_MEM
+                access: CS_AC_READ
+  -
+    input:
+      name: "issue 1827 x16 lcall seg:off format"
+      bytes: [ 0xb8,0x01,0x00,0x00,0x00 ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_32, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "mov eax, 1"
+  -
+    input:
+      name: "issue 1827 x16 lcall seg:off format"
+      bytes: [ 0xb9,0x00,0x00,0x00,0x00 ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_32, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "mov ecx, 0"
+  -
+    input:
+      name: "issue 1827 x16 lcall seg:off format"
+      bytes: [ 0x80,0xb8,0x01,0x00,0x00,0x00,0xb9 ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_32, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "cmp byte ptr [eax + 1], 0xb9"
+  -
+    input:
+      name: "issue 1827 x16 lcall seg:off format"
+      bytes: [ 0x00,0x00 ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_32, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "add byte ptr [eax], al"
+  -
+    input:
+      name: "issue 1827 x16 lcall seg:off format"
+      bytes: [ 0x01,0x00 ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_32, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "add dword ptr [eax], eax"
+  -
+    input:
+      name: "issue 1827 x16 lcall seg:off format"
+      bytes: [ 0x33,0xc0 ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_16, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "xor ax, ax"
+  -
+    input:
+      name: "issue 1827 x16 lcall seg:off format"
+      bytes: [ 0xba,0x5a,0xff ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_16, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "mov dx, 0xff5a"
+  -
+    input:
+      name: "issue 1710 M68K floating point immediates broken on big endian hosts"
+      bytes: [ 0xf2,0x3c,0x44,0x22,0x40,0x49,0x0e,0x56 ]
+      arch: "CS_ARCH_M68K"
+      options: [ CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040 ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "fadd.s #3.141500, fp0"
+  -
+    input:
+      name: "issue 1708 M68K floating point loads and stores generate the same op_str"
+      bytes: [ 0xf2,0x27,0x74,0x00 ]
+      arch: "CS_ARCH_M68K"
+      options: [ CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040 ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "fmove.d fp0, -(a7)"
+  -
+    input:
+      name: "issue 1708 M68K floating point loads and stores generate the same op_str"
+      bytes: [ 0xf2,0x1f,0x54,0x80 ]
+      arch: "CS_ARCH_M68K"
+      options: [ CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040 ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "fmove.d (a7)+, fp1"
+  -
+    input:
+      name: "issue 1708 M68K floating point loads and stores generate the same op_str"
+      bytes: [ 0x4e,0x75 ]
+      arch: "CS_ARCH_M68K"
+      options: [ CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040 ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "rts"
+  -
+    input:
+      name: "issue 1661 M68K invalid transfer direction in MOVEC instruction"
+      bytes: [ 0x4E,0x7A,0x00,0x02 ]
+      arch: "CS_ARCH_M68K"
+      options: [ CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040 ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "movec cacr, d0"
+  -
+    input:
+      name: "issue 1643 M68K incorrect read of 32-bit imm for bsr"
+      bytes: [ 0x61,0xff,0x00,0x00,0x0b,0xea ]
+      arch: "CS_ARCH_M68K"
+      options: [ CS_MODE_BIG_ENDIAN, CS_MODE_M68K_040 ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "bsr.l $bec"
+  -
+    input:
+      name: "issue 1627 Arm64 LD1 missing immediate operand"
+      bytes: [ 0xe0,0x73,0xdf,0x0c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "ld1 { v0.8b }, [sp], #8"
+        details:
+          aarch64:
+            operands:
+              -
+                type: AARCH64_OP_REG
+                vas: AARCH64LAYOUT_VL_8B
+              -
+                type: AARCH64_OP_MEM
+                mem_base: sp
+                mem_disp: 0x8
+                access: CS_AC_READ
+  -
+    input:
+      name: "issue 1587 ARM thumb pushed registers write"
+      bytes: [ 0x2d,0xe9,0xf0,0x47 ]
+      arch: "CS_ARCH_ARM"
+      options: [ CS_MODE_THUMB, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "push.w {r4, r5, r6, r7, r8, r9, r10, lr}"
+        details:
+          arm:
+            operands:
+              -
+                type: ARM_OP_REG
+                access: CS_AC_READ
+              -
+                type: ARM_OP_REG
+                access: CS_AC_READ
+              -
+                type: ARM_OP_REG
+                access: CS_AC_READ
+              -
+                type: ARM_OP_REG
+                access: CS_AC_READ
+              -
+                type: ARM_OP_REG
+                access: CS_AC_READ
+              -
+                type: ARM_OP_REG
+                access: CS_AC_READ
+              -
+                type: ARM_OP_REG
+                access: CS_AC_READ
+              -
+                type: ARM_OP_REG
+                access: CS_AC_READ
+  -
+    input:
+      name: "issue 1504 movhps qword ptr"
+      bytes: [ 0x0f,0x16,0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_64, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "movhps xmm1, qword ptr [rax]"
+        details:
+          x86:
+            opcode: [ 0x0f, 0x16, 0x00, 0x00 ]
+  -
+    input:
+      name: "issue 1505 opcode 0f"
+      bytes: [ 0x0f,0xa5,0xc2 ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_64, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "shld edx, eax, cl"
+        details:
+          x86:
+            opcode: [ 0x0f, 0xa5, 0x00, 0x00 ]
+  -
+    input:
+      name: "issue 1478 tbegin."
+      bytes: [ 0x7c,0x20,0x05,0x1d ]
+      arch: "CS_ARCH_PPC"
+      options: [ CS_MODE_64, CS_MODE_BIG_ENDIAN, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "tbegin. 1"
+        details:
+          ppc:
+            update_cr0: 1
+  -
+    input:
+      name: "issue 970 PPC bdnzt lt"
+      bytes: [ 0x41,0x00,0xff,0xac ]
+      arch: "CS_ARCH_PPC"
+      options: [ CS_MODE_64, CS_MODE_BIG_ENDIAN, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "bdnzt lt, 0xffffffffffffffac"
+        details:
+          ppc:
+            operands:
+              -
+                type: PPC_OP_REG
+                reg: "0"
+              -
+                type: PPC_OP_IMM
+                imm: -0x54
+  -
+    input:
+      name: "issue 970 PPC bdnzt eq"
+      bytes: [ 0x41,0x02,0xff,0xac ]
+      arch: "CS_ARCH_PPC"
+      options: [ CS_MODE_64, CS_MODE_BIG_ENDIAN, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "bdnzt eq, 0xffffffffffffffac"
+        details:
+          ppc:
+            operands:
+              -
+                type: PPC_OP_REG
+                reg: "2"
+              -
+                type: PPC_OP_IMM
+                imm: -0x54
+  -
+    input:
+      name: "issue 969 PPC bdnzflr operand 2"
+      bytes: [ 0x4c,0x10,0x00,0x20 ]
+      arch: "CS_ARCH_PPC"
+      options: [ CS_MODE_64, CS_MODE_BIG_ENDIAN, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "bdnzflr 4*cr4+lt"
+        details:
+          ppc:
+            operands:
+              -
+                type: PPC_OP_REG
+                reg: "16"
+  -
+    input:
+      name: "issue 1481 AARCH64 LDR operand2"
+      bytes: [ 0xe9,0x03,0x40,0xf9 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ CS_MODE_LITTLE_ENDIAN, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "ldr x9, [sp]"
+        details:
+          aarch64:
+            operands:
+              -
+                type: AARCH64_OP_REG
+              -
+                type: AARCH64_OP_MEM
+                mem_base: sp
+  -
+    input:
+      name: "issue 968 PPC absolute branch: bdnzla"
+      bytes: [ 0x42,0x00,0x12,0x37 ]
+      arch: "CS_ARCH_PPC"
+      options: [ CS_MODE_64, CS_MODE_BIG_ENDIAN ]
+      address: 0x1000
+    expected:
+      insns:
+      -
+        asm_text: "bcla 0x10, lt, 0x1234"
+  -
+    input:
+      name: "issue 968 PPC absolute branch: bdzla"
+      bytes: [ 0x42,0x40,0x12,0x37 ]
+      arch: "CS_ARCH_PPC"
+      options: [ CS_MODE_64, CS_MODE_BIG_ENDIAN ]
+      address: 0x1000
+    expected:
+      insns:
+      -
+        asm_text: "bcla	0x12, lt, 0x1234"
+  -
+    input:
+      name: "issue X86 xrelease xchg"
+      bytes: [ 0xf3,0x87,0x03 ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_32 ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "xrelease xchg dword ptr [ebx], eax"
+  -
+    input:
+      name: "issue X86 xacquire xchg"
+      bytes: [ 0xf2,0x87,0x03 ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_32 ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "xacquire xchg dword ptr [ebx], eax"
+  -
+    input:
+      name: "issue X86 xrelease"
+      bytes: [ 0xf3,0xf0,0x31,0x1f ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_64 ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "xrelease lock xor dword ptr [rdi], ebx"
+  -
+    input:
+      name: "issue 1477 X86 xacquire"
+      bytes: [ 0xf2,0xf0,0x31,0x1f ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_64 ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "xacquire lock xor dword ptr [rdi], ebx"
+  -
+    input:
+      name: "issue PPC JUMP group"
+      bytes: [ 0x41,0x82,0x00,0x10 ]
+      arch: "CS_ARCH_PPC"
+      options: [ CS_MODE_64, CS_MODE_BIG_ENDIAN, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "bt eq, 0x10"
+        details:
+          groups: [ jump, branch_relative ]
+  -
+    input:
+      name: "issue 1468 PPC bdnz"
+      bytes: [ 0x42,0x00,0xff,0xf8 ]
+      arch: "CS_ARCH_PPC"
+      options: [ CS_MODE_64, CS_MODE_BIG_ENDIAN ]
+      address: 0x101086c
+    expected:
+      insns:
+      -
+        asm_text: "bc 0x10, lt, 0x1010864"
+  -
+    input:
+      name: "issue PPC bdnzt"
+      bytes: [ 0x41,0x00,0xff,0xac ]
+      arch: "CS_ARCH_PPC"
+      options: [ CS_MODE_64, CS_MODE_BIG_ENDIAN ]
+      address: 0x1000
+    expected:
+      insns:
+      -
+        asm_text: "bdnzt lt, 0xfac"
+  -
+    input:
+      name: "issue 1469 PPC CRx"
+      bytes: [ 0x4c,0x02,0x39,0x82 ]
+      arch: "CS_ARCH_PPC"
+      options: [ CS_MODE_64, CS_MODE_BIG_ENDIAN, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "crxor lt, eq, 4*cr1+un"
+        details:
+          ppc:
+            operands:
+              -
+                type: PPC_OP_REG
+                reg: "0"
+              -
+                type: PPC_OP_REG
+                reg: "2"
+              -
+                type: PPC_OP_REG
+                reg: "7"
+  -
+    input:
+      name: "issue 1468 B target"
+      bytes: [ 0x4b,0xff,0xf8,0x00 ]
+      arch: "CS_ARCH_PPC"
+      options: [ CS_MODE_64, CS_MODE_BIG_ENDIAN ]
+      address: 0x1000
+    expected:
+      insns:
+      -
+        asm_text: "b 0x800"
+  -
+    input:
+      name: "issue 1456 test alt 1"
+      bytes: [ 0xf6,0x08,0x00 ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_32 ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "test byte ptr [eax], 0"
+  -
+    input:
+      name: "issue 1456 test alt 2"
+      bytes: [ 0xf7,0x08,0x00,0x00,0x00,0x00 ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_32 ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "test dword ptr [eax], 0"
+  -
+    input:
+      name: "issue 1472 lock sub"
+      bytes: [ 0xF0,0x2B,0x45,0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_32 ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "lock sub eax, dword ptr [ebp + 8]"
+  -
+    input:
+      name: "issue 1472 lock or"
+      bytes: [ 0xF0,0x0B,0x45,0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_32 ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "lock or eax, dword ptr [ebp + 8]"
+  -
+    input:
+      name: "issue 1472 lock and"
+      bytes: [ 0xF0,0x23,0x45,0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_32 ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "lock and eax, dword ptr [ebp + 8]"
+  -
+    input:
+      name: "issue 1472 lock add"
+      bytes: [ 0xF0,0x03,0x45,0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_32 ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "lock add eax, dword ptr [ebp + 8]"
+  -
+    input:
+      name: "issue 1456 MOV dr"
+      bytes: [ 0x0f,0x23,0x00 ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_32 ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "mov dr0, eax"
+  -
+    input:
+      name: "issue 1456 MOV dr"
+      bytes: [ 0x0f,0x21,0x00 ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_32 ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "mov eax, dr0"
+  -
+    input:
+      name: "issue 1456 MOV cr"
+      bytes: [ 0x0f,0x22,0x00 ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_32 ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "mov cr0, eax"
+  -
+    input:
+      name: "issue 1472 lock adc"
+      bytes: [ 0xf0,0x12,0x45,0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_32 ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "lock adc al, byte ptr [ebp + 8]"
+  -
+    input:
+      name: "issue 1456 xmmword"
+      bytes: [ 0x66,0x0f,0x2f,0x00 ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_32 ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "comisd xmm0, xmmword ptr [eax]"
+  -
+    input:
+      name: "issue 1456 ARM printPKHASRShiftImm"
+      bytes: [ 0xca,0xea,0x21,0x06 ]
+      arch: "CS_ARCH_ARM"
+      options: [ CS_MODE_THUMB ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "pkhtb r6, r10, r1, asr #0x20"
+  -
+    input:
+      name: "issue 1456 EIZ"
+      bytes: [ 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00 ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_32 ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "lea esi, [esi]"
+  -
+    input:
+      name: "issue 1456 ARM POP"
+      bytes: [ 0x04,0x10,0x9d,0xe4 ]
+      arch: "CS_ARCH_ARM"
+      options: [ CS_MODE_LITTLE_ENDIAN ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "pop {r1}"
+  -
+    input:
+      name: "issue 1456"
+      bytes: [ 0x31,0x02,0xa0,0xe1 ]
+      arch: "CS_ARCH_ARM"
+      options: [ CS_MODE_LITTLE_ENDIAN, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "lsr r0, r1, r2"
+        details:
+          arm:
+            operands:
+              -
+                type: ARM_OP_REG
+                reg: r0
+              -
+                type: ARM_OP_REG
+                reg: r1
+              -
+                type: ARM_OP_REG
+                reg: r2
+  -
+    input:
+      name: "issue 1456"
+      bytes: [ 0x0c,0x00,0x80,0x12 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ CS_MODE_LITTLE_ENDIAN, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "mov w12, #-1"
+        details:
+          aarch64:
+            operands:
+              -
+                type: AARCH64_OP_REG
+                reg: w12
+              -
+                type: AARCH64_OP_IMM
+                imm: -1
+  -
+    input:
+      name: "issue 1456"
+      bytes: [ 0xb8,0x00,0x00,0x00,0x00 ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_32, CS_OPT_SYNTAX_ATT ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "movl $0, %eax"
+  -
+    input:
+      name: "issue 1456"
+      bytes: [ 0xd1,0x5e,0x48 ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_32, CS_OPT_SYNTAX_ATT ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "rcrl $1, 0x48(%esi)"
+  -
+    input:
+      name: "issue 1456"
+      bytes: [ 0xd1,0x5e,0x48 ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_32 ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "rcr dword ptr [esi + 0x48], 1"
+  -
+    input:
+      name: "issue 1456"
+      bytes: [ 0xd1,0x5e,0x48 ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_32, CS_OPT_SYNTAX_ATT ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "rcrl $1, 0x48(%esi)"
+  -
+    input:
+      name: "issue 1456"
+      bytes: [ 0x62,0x00 ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_32 ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "bound eax, qword ptr [eax]"
+  -
+    input:
+      name: "issue 1454"
+      bytes: [ 0xf0,0x0f,0xb1,0x1e ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_32, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "lock cmpxchg dword ptr [esi], ebx"
+        details:
+          regs_read: [ eax, esi, ebx ]
+  -
+    input:
+      name: "issue 1452"
+      bytes: [ 0x20,0x3c,0x0c,0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ CS_MODE_LITTLE_ENDIAN, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "mov w0, v1.s[1]"
+        details:
+          aarch64:
+            operands:
+              -
+                type: AARCH64_OP_REG
+              -
+                type: AARCH64_OP_REG
+                vas: AARCH64LAYOUT_VL_S
+  -
+    input:
+      name: "issue 1452"
+      bytes: [ 0x20,0x3c,0x18,0x4e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ CS_MODE_LITTLE_ENDIAN, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "mov x0, v1.d[1]"
+        details:
+          aarch64:
+            operands:
+              -
+                type: AARCH64_OP_REG
+              -
+                type: AARCH64_OP_REG
+                vas: AARCH64LAYOUT_VL_D
+  -
+    input:
+      name: "issue 1452"
+      bytes: [ 0x20,0x3c,0x03,0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ CS_MODE_LITTLE_ENDIAN, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "umov w0, v1.b[1]"
+        details:
+          aarch64:
+            operands:
+              -
+                type: AARCH64_OP_REG
+              -
+                type: AARCH64_OP_REG
+                vas: AARCH64LAYOUT_VL_B
+  -
+    input:
+      name: "issue 1452"
+      bytes: [ 0x20,0x3c,0x06,0x0e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ CS_MODE_LITTLE_ENDIAN, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "umov w0, v1.h[1]"
+        details:
+          aarch64:
+            operands:
+              -
+                type: AARCH64_OP_REG
+              -
+                type: AARCH64_OP_REG
+                vas: AARCH64LAYOUT_VL_H
+  -
+    input:
+      name: "issue 1211"
+      bytes: [ 0xc4,0xe1,0xf8,0x90,0xc0 ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_64 ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "kmovq k0, k0"
+  -
+    input:
+      name: "issue 1211"
+      bytes: [ 0xc4,0xe1,0xfb,0x92,0xc3 ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_64 ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "kmovq k0, rbx"
+  -
+    input:
+      name: "issue 1211"
+      bytes: [ 0x62,0xf1,0x7d,0x48,0x74,0x83,0x12,0x00,0x00,0x00 ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_64 ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "vpcmpeqb k0, zmm0, zmmword ptr [rbx + 0x12]"
+  -
+    input:
+      name: "issue 1211"
+      bytes: [ 0x62,0xf2,0x7d,0x48,0x30,0x43,0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_64 ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "vpmovzxbw zmm0, ymmword ptr [rbx + 0x100]"
+  -
+    input:
+      name: "issue x86 BND register (OSS-fuzz #13467)"
+      bytes: [ 0x0f,0x1a,0x1a ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_32, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "bndldx bnd3, [edx]"
+        details:
+          x86:
+            operands:
+              -
+                type: X86_OP_REG
+                reg: bnd3
+              -
+                type: X86_OP_MEM
+  -
+    input:
+      name: "issue 1335"
+      bytes: [ 0x0f,0x1f,0xc0 ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_32 ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "nop eax"
+  -
+    input:
+      name: "issue 1335"
+      bytes: [ 0x48,0x0f,0x1f,0x00 ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_64 ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "nop qword ptr [rax]"
+  -
+    input:
+      name: "issue 1259"
+      bytes: [ 0x0f,0x0d,0x44,0x11,0x40 ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_64 ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "prefetch byte ptr [rcx + rdx + 0x40]"
+  -
+    input:
+      name: "issue 1259"
+      bytes: [ 0x41,0x0f,0x0d,0x44,0x12,0x40 ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_64 ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "prefetch byte ptr [r10 + rdx + 0x40]"
+  -
+    input:
+      name: "issue 1304"
+      bytes: [ 0x66,0x0f,0x7f,0x4c,0x24,0x40 ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_64, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "movdqa xmmword ptr [rsp + 0x40], xmm1"
+        details:
+          x86:
+            operands:
+              -
+                type: X86_OP_MEM
+                access: CS_AC_WRITE
+              -
+                type: X86_OP_REG
+                access: CS_AC_READ
+  -
+    input:
+      name: "issue 1304"
+      bytes: [ 0x66,0x0f,0x7e,0x04,0x24 ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_64, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "movd dword ptr [rsp], xmm0"
+        details:
+          x86:
+            operands:
+              -
+                type: X86_OP_MEM
+                access: CS_AC_WRITE
+              -
+                type: X86_OP_REG
+                access: CS_AC_READ
+  -
+    input:
+      name: "issue 1304"
+      bytes: [ 0xf3,0x41,0x0f,0x7f,0x4d,0x00 ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_64, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "movdqu xmmword ptr [r13], xmm1"
+        details:
+          x86:
+            operands:
+              -
+                type: X86_OP_MEM
+                access: CS_AC_WRITE
+              -
+                type: X86_OP_REG
+                access: CS_AC_READ
+  -
+    input:
+      name: "issue 1346"
+      bytes: [ 0xf3,0x48,0x0f,0x1e,0xc8 ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_64 ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "rdsspq rax"
+  -
+    input:
+      name: "issue 1346"
+      bytes: [ 0xf3,0x0f,0x1e,0xc8 ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_64 ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "rdsspd eax"
+  -
+    input:
+      name: "issue 1346"
+      bytes: [ 0xf3,0x48,0x0f,0xae,0xe8 ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_64 ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "incsspq rax"
+  -
+    input:
+      name: "issue 1346"
+      bytes: [ 0xf3,0x0f,0xae,0xe8 ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_64 ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "incsspd eax"
+  -
+    input:
+      name: "issue 1346"
+      bytes: [ 0xf3,0x0f,0x01,0xea ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_64 ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "saveprevssp"
+  -
+    input:
+      name: "issue 1346"
+      bytes: [ 0xf3,0x0f,0x01,0x28 ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_64 ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "rstorssp dword ptr [rax]"
+  -
+    input:
+      name: "issue 1346"
+      bytes: [ 0x67,0xf3,0x0f,0x01,0x28 ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_64 ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "rstorssp dword ptr [eax]"
+  -
+    input:
+      name: "issue 1346"
+      bytes: [ 0x48,0x0f,0x38,0xf6,0x00 ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_64 ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "wrssq qword ptr [rax], rax"
+  -
+    input:
+      name: "issue 1346"
+      bytes: [ 0x67,0x0f,0x38,0xf6,0x00 ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_64 ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "wrssd dword ptr [eax], eax"
+  -
+    input:
+      name: "issue 1346"
+      bytes: [ 0xf3,0x0f,0x01,0xe8 ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_64 ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "setssbsy"
+  -
+    input:
+      name: "issue 1346"
+      bytes: [ 0xf3,0x0f,0xae,0x30 ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_64 ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "clrssbsy dword ptr [rax]"
+  -
+    input:
+      name: "issue 1346"
+      bytes: [ 0x67,0xf3,0x0f,0xae,0x30 ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_64 ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "clrssbsy dword ptr [eax]"
+  -
+    input:
+      name: "issue 1206"
+      bytes: [ 0xc4,0xe2,0x7d,0x5a,0x0c,0x0e ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_64 ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "vbroadcasti128 ymm1, xmmword ptr [rsi + rcx]"
+  -
+    input:
+      name: "issue xchg 16bit"
+      bytes: [ 0x91 ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_16 ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "xchg cx, ax"
+  -
+    input:
+      name: "issue ROL 1, ATT syntax"
+      bytes: [ 0x66,0x48,0xf3,0xd1,0xc0 ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_64, CS_OPT_SYNTAX_ATT ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "rolw $1, %ax"
+  -
+    input:
+      name: "issue 1129"
+      bytes: [ 0xf3,0x0f,0x1e,0xfa ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_64 ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "endbr64"
+  -
+    input:
+      name: "issue 1129"
+      bytes: [ 0xf3,0x0f,0x1e,0xfa ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_32 ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "endbr64"
+  -
+    input:
+      name: "issue 1129"
+      bytes: [ 0xf3,0x0f,0x1e,0xfb ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_64 ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "endbr32"
+  -
+    input:
+      name: "issue 1129"
+      bytes: [ 0xf3,0x0f,0x1e,0xfb ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_32 ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "endbr32"
+  -
+    input:
+      name: "issue x64 jmp"
+      bytes: [ 0xeb,0xfe ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_64 ]
+      address: 0x1000
+    expected:
+      insns:
+      -
+        asm_text: "jmp 0x1000"
+  -
+    input:
+      name: "issue x64att jmp"
+      bytes: [ 0xeb,0xfe ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_64, CS_OPT_SYNTAX_ATT ]
+      address: 0x1000
+    expected:
+      insns:
+      -
+        asm_text: "jmp 0x1000"
+  -
+    input:
+      name: "issue x32 jmp"
+      bytes: [ 0xeb,0xfe ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_32 ]
+      address: 0x1000
+    expected:
+      insns:
+      -
+        asm_text: "jmp 0x1000"
+  -
+    input:
+      name: "issue x32att jmp"
+      bytes: [ 0xeb,0xfe ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_32, CS_OPT_SYNTAX_ATT ]
+      address: 0x1000
+    expected:
+      insns:
+      -
+        asm_text: "jmp 0x1000"
+  -
+    input:
+      name: "issue 1389"
+      bytes: [ 0x66,0x0f,0x73,0xf9,0x01 ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_64, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "pslldq xmm1, 1"
+        details:
+          x86:
+            operands:
+              -
+                type: X86_OP_REG
+                access: CS_AC_READ_WRITE
+                reg: xmm1
+              -
+                type: X86_OP_IMM
+                size: 1
+                imm: 1
+  -
+    input:
+      name: "issue x64 unsigned"
+      bytes: [ 0x66,0x83,0xc0,0x80 ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_64, CS_OPT_UNSIGNED ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "add ax, 0xff80"
+  -
+    input:
+      name: "issue x64att unsigned"
+      bytes: [ 0x66,0x83,0xc0,0x80 ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_64, CS_OPT_SYNTAX_ATT, CS_OPT_UNSIGNED ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "addw $0xff80, %ax"
+  -
+    input:
+      name: "issue 1323"
+      bytes: [ 0x70,0x47,0x00 ]
+      arch: "CS_ARCH_ARM"
+      options: [ CS_MODE_THUMB, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "bx lr"
+        details:
+          arm:
+            operands:
+              -
+                type: ARM_OP_REG
+                reg: r14
+                access: CS_AC_READ
+          regs_read: [ r14 ]
+          groups: [ jump, IsThumb ]
+  -
+    input:
+      name: "issue 1317"
+      bytes: [ 0xd0,0xe8,0x11,0xf0 ]
+      arch: "CS_ARCH_ARM"
+      options: [ CS_MODE_THUMB, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "tbh [r0, r1, lsl #1]"
+        details:
+          arm:
+            operands:
+              -
+                type: ARM_OP_MEM
+                mem_base: r0
+                mem_index: r1
+                access: CS_AC_READ
+                shift_type: ARM_SFT_LSL
+                shift_value: 1
+          regs_read: [ r0, r1 ]
+          groups: [ jump, IsThumb2 ]
+  -
+    input:
+      name: "issue 1308"
+      bytes: [ 0x83,0x3d,0xa1,0x75,0x21,0x00,0x04 ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_64, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "cmp dword ptr [rip + 0x2175a1], 4"
+        details:
+          x86:
+            prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ]
+            opcode: [ 0x83, 0x00, 0x00, 0x00 ]
+            rex: 0x0
+            addr_size: 8
+            modrm: 0x3d
+            disp: 0x2175a1
+            sib: 0x0
+            operands:
+              -
+                type: X86_OP_MEM
+                mem_base: rip
+                mem_disp: 0x2175a1
+                size: 4
+                access: CS_AC_READ
+              -
+                type: X86_OP_IMM
+                imm: 0x4
+                size: 4
+            eflags: [ X86_EFLAGS_MODIFY_AF, X86_EFLAGS_MODIFY_CF, X86_EFLAGS_MODIFY_SF, X86_EFLAGS_MODIFY_ZF, X86_EFLAGS_MODIFY_PF, X86_EFLAGS_MODIFY_OF ]
+          regs_read: [ rip ]
+          regs_write: [ rflags ]
+  -
+    input:
+      name: "issue 1262"
+      bytes: [ 0x0f,0x95,0x44,0x24,0x5e ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_64, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "setne byte ptr [rsp + 0x5e]"
+        details:
+          x86:
+            prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ]
+            opcode: [ 0x0f, 0x95, 0x00, 0x00 ]
+            rex: 0x0
+            addr_size: 8
+            modrm: 0x44
+            disp: 0x5e
+            sib: 0x24
+            sib_base: rsp
+            sib_scale: 1
+            operands:
+              -
+                type: X86_OP_MEM
+                mem_base: rsp
+                mem_disp: 0x5e
+                size: 1
+                access: CS_AC_WRITE
+            eflags: [ X86_EFLAGS_TEST_ZF ]
+          regs_read: [ rflags, rsp ]
+  -
+    input:
+      name: "issue 1262"
+      bytes: [ 0x0f,0x94,0x44,0x24,0x1f ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_64, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "sete byte ptr [rsp + 0x1f]"
+        details:
+          x86:
+            prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ]
+            opcode: [ 0x0f, 0x94, 0x00, 0x00 ]
+            rex: 0x0
+            addr_size: 8
+            modrm: 0x44
+            disp: 0x1f
+            sib: 0x24
+            sib_base: rsp
+            sib_scale: 1
+            operands:
+              -
+                type: X86_OP_MEM
+                mem_base: rsp
+                mem_disp: 0x1f
+                size: 1
+                access: CS_AC_WRITE
+            eflags: [ X86_EFLAGS_TEST_ZF ]
+          regs_read: [ rflags, rsp ]
+  -
+    input:
+      name: "issue 1263"
+      bytes: [ 0x67,0x48,0x89,0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_64 ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "mov qword ptr [eax], rbx"
+  -
+    input:
+      name: "issue 1263"
+      bytes: [ 0x67,0x48,0x8b,0x03 ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_64 ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "mov rax, qword ptr [ebx]"
+  -
+    input:
+      name: "issue 1255"
+      bytes: [ 0xdb,0x7c,0x24,0x40 ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_64, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "fstp xword ptr [rsp + 0x40]"
+        details:
+          x86:
+            prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ]
+            opcode: [ 0xdb, 0x00, 0x00, 0x00 ]
+            rex: 0x0
+            addr_size: 8
+            modrm: 0x7c
+            disp: 0x40
+            sib: 0x24
+            sib_base: rsp
+            sib_scale: 1
+            operands:
+              -
+                type: X86_OP_MEM
+                mem_base: rsp
+                mem_disp: 0x40
+                size: 10
+                access: CS_AC_WRITE
+            fpu_flags: [ X86_FPU_FLAGS_MODIFY_C1, X86_FPU_FLAGS_UNDEFINED_C0, X86_FPU_FLAGS_UNDEFINED_C2, X86_FPU_FLAGS_UNDEFINED_C3 ]
+          regs_read: [ rsp ]
+          regs_write: [ fpsw ]
+          groups: [ fpu ]
+  -
+    input:
+      name: "issue 1255"
+      bytes: [ 0xdd,0xd9 ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_64, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "fstp st(1)"
+        details:
+          x86:
+            prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ]
+            opcode: [ 0xdd, 0x00, 0x00, 0x00 ]
+            rex: 0x0
+            addr_size: 8
+            modrm: 0xd9
+            disp: 0x0
+            sib: 0x0
+            operands:
+              -
+                type: X86_OP_REG
+                reg: st(1)
+                size: 10
+                access: CS_AC_WRITE
+            eflags: [ X86_EFLAGS_MODIFY_CF, X86_EFLAGS_PRIOR_SF, X86_EFLAGS_PRIOR_AF, X86_EFLAGS_PRIOR_PF ]
+          regs_write: [ fpsw, st(1) ]
+  -
+    input:
+      name: "issue 1255"
+      bytes: [ 0xdf,0x7c,0x24,0x68 ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_64, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "fistp qword ptr [rsp + 0x68]"
+        details:
+          x86:
+            prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ]
+            opcode: [ 0xdf, 0x00, 0x00, 0x00 ]
+            rex: 0x0
+            addr_size: 8
+            modrm: 0x7c
+            disp: 0x68
+            sib: 0x24
+            sib_base: rsp
+            sib_scale: 1
+            operands:
+              -
+                type: X86_OP_MEM
+                mem_base: rsp
+                mem_disp: 0x68
+                size: 8
+                access: CS_AC_WRITE
+            fpu_flags: [ X86_FPU_FLAGS_RESET_C1, X86_FPU_FLAGS_UNDEFINED_C0, X86_FPU_FLAGS_UNDEFINED_C2, X86_FPU_FLAGS_UNDEFINED_C3 ]
+          regs_read: [ rsp ]
+          regs_write: [ fpsw ]
+          groups: [ fpu ]
+  -
+    input:
+      name: "issue 1221"
+      bytes: [ 0x55,0x48,0x89,0xe5 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ CS_MODE_BIG_ENDIAN ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "call 0x55222794"
+  -
+    input:
+      name: "issue 1144"
+      bytes: [ 0x00,0x00,0x02,0xb6 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ CS_MODE_LITTLE_ENDIAN ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "tbz x0, #0x20, 0x4000"
+  -
+    input:
+      name: "issue 1144"
+      bytes: [ 0x00,0x00,0x04,0xb6 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ CS_MODE_LITTLE_ENDIAN ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "tbz x0, #0x20, 0xffffffffffff8000"
+  -
+    input:
+      name: "issue 1144"
+      bytes: [ 0x00,0x00,0x02,0xb7 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ CS_MODE_LITTLE_ENDIAN ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "tbnz x0, #0x20, 0x4000"
+  -
+    input:
+      name: "issue 1144"
+      bytes: [ 0x00,0x00,0x04,0xb7 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ CS_MODE_LITTLE_ENDIAN ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "tbnz x0, #0x20, 0xffffffffffff8000"
+  -
+    input:
+      name: "issue 826"
+      bytes: [ 0x0b,0x00,0x00,0x0a ]
+      arch: "CS_ARCH_ARM"
+      options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "beq 0x34"
+        details:
+          arm:
+            operands:
+              -
+                type: ARM_OP_IMM
+                imm: 0x34
+            cc: ARMCC_EQ
+          regs_read: [ cpsr ]
+          groups: [ jump, branch_relative, IsARM ]
+  -
+    input:
+      name: "issue 1047"
+      bytes: [ 0x48,0x83,0xe4,0xf0 ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_64, CS_OPT_SYNTAX_ATT ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "andq $0xfffffffffffffff0, %rsp"
+  -
+    input:
+      name: "issue 959"
+      bytes: [ 0xa0,0x28,0x57,0x88,0x7c ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_32 ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "mov al, byte ptr [0x7c885728]"
+  -
+    input:
+      name: "issue 950"
+      bytes: [ 0x66,0xa3,0x94,0x90,0x04,0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_32, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "mov word ptr [0x8049094], ax"
+        details:
+          x86:
+            prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_OPSIZE, X86_PREFIX_0 ]
+            opcode: [ 0xa3, 0x00, 0x00, 0x00 ]
+            rex: 0x0
+            addr_size: 4
+            modrm: 0x0
+            disp: 0x8049094
+            sib: 0x0
+            operands:
+              -
+                type: X86_OP_MEM
+                mem_disp: 0x8049094
+                size: 2
+                access: CS_AC_WRITE
+              -
+                type: X86_OP_REG
+                reg: ax
+                size: 2
+                access: CS_AC_READ
+          regs_read: [ ax ]
+  -
+    input:
+      name: "issue 938"
+      bytes: [ 0x70,0x00,0xb2,0xff ]
+      arch: "CS_ARCH_MIPS"
+      options: [ CS_MODE_MIPS64, CS_MODE_LITTLE_ENDIAN ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "sd $s2, 0x70($sp)"
+  -
+    input:
+      name: "issue 915"
+      bytes: [ 0xf0,0x0f,0x1f,0x00 ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_64 ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "lock nop dword ptr [rax]"
+  -
+    input:
+      name: "!# issue 913"
+      bytes: [ 0x04,0x10,0x9d,0xe4 ]
+      arch: "CS_ARCH_ARM"
+      options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "pop {r1}"
+        details:
+          arm:
+            operands:
+              -
+                type: ARM_OP_REG
+                reg: r1
+                access: CS_AC_WRITE
+          writeback: 1
+          regs_read: [ r13 ]
+          regs_write: [ r13, r1 ]
+          groups: [ IsARM ]
+  -
+    input:
+      name: "issue 884"
+      bytes: [ 0x64,0x48,0x03,0x04,0x25,0x00,0x00,0x00,0x00 ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_64, CS_OPT_SYNTAX_ATT ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "addq %fs:0, %rax"
+  -
+    input:
+      name: "issue 872"
+      bytes: [ 0xf2,0xeb,0x3e ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_32 ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "bnd jmp 0x41"
+  -
+    input:
+      name: "issue 861"
+      bytes: [ 0x01,0x81,0xa0,0xfc ]
+      arch: "CS_ARCH_ARM"
+      options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "stc2 p1, c8, [r0], #4"
+        details:
+          arm:
+            operands:
+              -
+                type: ARM_OP_PIMM
+                imm: 1
+                access: CS_AC_READ
+              -
+                type: ARM_OP_CIMM
+                imm: 8
+                access: CS_AC_READ
+              -
+                type: ARM_OP_MEM
+                mem_base: r0
+                mem_disp: 0x4
+                access: CS_AC_WRITE
+          regs_read: [ r0 ]
+          groups: [ IsARM, PreV8 ]
+  -
+    input:
+      name: "issue 852"
+      bytes: [ 0x64,0xa3,0x00,0x00,0x00,0x00 ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_32, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "mov dword ptr fs:[0], eax"
+        details:
+          x86:
+            prefix: [ X86_PREFIX_0, X86_PREFIX_FS, X86_PREFIX_0, X86_PREFIX_0 ]
+            opcode: [ 0xa3, 0x00, 0x00, 0x00 ]
+            rex: 0x0
+            addr_size: 4
+            modrm: 0x0
+            disp: 0x0
+            sib: 0x0
+            operands:
+              -
+                type: X86_OP_MEM
+                mem_segment: fs
+                size: 4
+                access: CS_AC_WRITE
+              -
+                type: X86_OP_REG
+                reg: eax
+                size: 4
+                access: CS_AC_READ
+          regs_read: [ fs, eax ]
+  -
+    input:
+      name: "issue 825"
+      bytes: [ 0x0e,0xf0,0xa0,0xe1 ]
+      arch: "CS_ARCH_ARM"
+      options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "mov pc, lr"
+        details:
+          arm:
+            operands:
+              -
+                type: ARM_OP_REG
+                reg: r15
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_REG
+                reg: r14
+                access: CS_AC_READ
+          regs_read: [ r14 ]
+          regs_write: [ r15 ]
+          groups: [ jump, return, IsARM ]
+  -
+    input:
+      name: "issue 813"
+      bytes: [ 0xF6,0xC0,0x04,0x01 ]
+      arch: "CS_ARCH_ARM"
+      options: [ CS_MODE_THUMB, CS_MODE_BIG_ENDIAN ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "movt r4, #0x801"
+  -
+    input:
+      name: "issue 809"
+      bytes: [ 0x0f,0x29,0x8d,0xf0,0xfd,0xff,0xff ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_64, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "movaps xmmword ptr [rbp - 0x210], xmm1"
+        details:
+          x86:
+            prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ]
+            opcode: [ 0x0f, 0x29, 0x00, 0x00 ]
+            rex: 0x0
+            addr_size: 8
+            modrm: 0x8d
+            disp: -0x210
+            sib: 0x0
+            operands:
+              -
+                type: X86_OP_MEM
+                mem_base: rbp
+                mem_disp: -0x210
+                size: 16
+                access: CS_AC_WRITE
+              -
+                type: X86_OP_REG
+                reg: xmm1
+                size: 16
+                access: CS_AC_READ
+          regs_read: [ rbp, xmm1 ]
+          groups: [ sse1 ]
+  -
+    input:
+      name: "issue 807"
+      bytes: [ 0x4c,0x0f,0x00,0x80,0x16,0x76,0x8a,0xfe ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_64 ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "sldt word ptr [rax - 0x17589ea]"
+  -
+    input:
+      name: "issue 806"
+      bytes: [ 0x0f,0x35 ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_64 ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "sysexit"
+  -
+    input:
+      name: "issue 805"
+      bytes: [ 0x48,0x4c,0x0f,0xb5,0x80,0x16,0x76,0x8a,0xfe ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_64, CS_OPT_SYNTAX_ATT ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "lgs -0x17589ea(%rax), %r8"
+  -
+    input:
+      name: "issue 804"
+      bytes: [ 0x66,0x48,0xf3,0xd1,0xc0 ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_64, CS_OPT_SYNTAX_ATT ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "rolw $1, %ax"
+  -
+    input:
+      name: "issue 789"
+      bytes: [ 0x8e,0x1e ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_64, CS_OPT_SYNTAX_ATT ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "movw (%rsi), %ds"
+  -
+    input:
+      name: "issue 767"
+      bytes: [ 0xb1,0xe8,0xfc,0x07 ]
+      arch: "CS_ARCH_ARM"
+      options: [ CS_MODE_THUMB, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "ldm.w r1!, {r2, r3, r4, r5, r6, r7, r8, r9, r10}"
+        details:
+          arm:
+            operands:
+              -
+                type: ARM_OP_REG
+                reg: r1
+                access: CS_AC_READ_WRITE
+              -
+                type: ARM_OP_REG
+                reg: r2
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_REG
+                reg: r3
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_REG
+                reg: r4
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_REG
+                reg: r5
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_REG
+                reg: r6
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_REG
+                reg: r7
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_REG
+                reg: r8
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_REG
+                reg: r9
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_REG
+                reg: r10
+                access: CS_AC_WRITE
+          writeback: 1
+          regs_read: [ r1 ]
+          regs_write: [ r1, r2, r3, r4, r5, r6, r7, r8, r9, r10 ]
+          groups: [ IsThumb2 ]
+  -
+    input:
+      name: "issue 760"
+      bytes: [ 0x02,0x80,0xbd,0xe8 ]
+      arch: "CS_ARCH_ARM"
+      options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "pop {r1, pc}"
+        details:
+          arm:
+            operands:
+              -
+                type: ARM_OP_REG
+                reg: r1
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_REG
+                reg: r15
+                access: CS_AC_WRITE
+          writeback: 1
+          regs_read: [ r13 ]
+          regs_write: [ r13, r1, r15 ]
+          groups: [ IsARM, return, jump ]
+  -
+    input:
+      name: "issue 750"
+      bytes: [ 0x0e,0x00,0x20,0xe9 ]
+      arch: "CS_ARCH_ARM"
+      options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "stmdb r0!, {r1, r2, r3}"
+        details:
+          arm:
+            operands:
+              -
+                type: ARM_OP_REG
+                reg: r0
+                access: CS_AC_READ_WRITE
+              -
+                type: ARM_OP_REG
+                reg: r1
+                access: CS_AC_READ
+              -
+                type: ARM_OP_REG
+                reg: r2
+                access: CS_AC_READ
+              -
+                type: ARM_OP_REG
+                reg: r3
+                access: CS_AC_READ
+          writeback: 1
+          regs_read: [ r0, r1, r2, r3 ]
+          regs_write: [ r0 ]
+          groups: [ IsARM ]
+  -
+    input:
+      name: "issue 747"
+      bytes: [ 0x0e,0x00,0xb0,0xe8 ]
+      arch: "CS_ARCH_ARM"
+      options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "ldm r0!, {r1, r2, r3}"
+        details:
+          arm:
+            operands:
+              -
+                type: ARM_OP_REG
+                reg: r0
+                access: CS_AC_READ_WRITE
+              -
+                type: ARM_OP_REG
+                reg: r1
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_REG
+                reg: r2
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_REG
+                reg: r3
+                access: CS_AC_WRITE
+          writeback: 1
+          regs_read: [ r0 ]
+          regs_write: [ r0, r1, r2, r3 ]
+          groups: [ IsARM ]
+  -
+    input:
+      name: "issue 747"
+      bytes: [ 0x0e,0xc8 ]
+      arch: "CS_ARCH_ARM"
+      options: [ CS_MODE_THUMB, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "ldm r0!, {r1, r2, r3}"
+        details:
+          arm:
+            operands:
+              -
+                type: ARM_OP_REG
+                reg: r0
+                access: CS_AC_READ_WRITE
+              -
+                type: ARM_OP_REG
+                reg: r1
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_REG
+                reg: r2
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_REG
+                reg: r3
+                access: CS_AC_WRITE
+          writeback: 1
+          regs_read: [ r0 ]
+          regs_write: [ r0, r1, r2, r3 ]
+          groups: [ IsThumb ]
+  -
+    input:
+      name: "issue 746"
+      bytes: [ 0x89,0x00,0x2d,0xe9 ]
+      arch: "CS_ARCH_ARM"
+      options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "push {r0, r3, r7}"
+        details:
+          arm:
+            operands:
+              -
+                type: ARM_OP_REG
+                reg: r0
+                access: CS_AC_READ
+              -
+                type: ARM_OP_REG
+                reg: r3
+                access: CS_AC_READ
+              -
+                type: ARM_OP_REG
+                reg: r7
+                access: CS_AC_READ
+          writeback: 1
+          regs_read: [ r13, r0, r3, r7 ]
+          regs_write: [ r13 ]
+          groups: [ IsARM ]
+  -
+    input:
+      name: "issue 744"
+      bytes: [ 0x02,0x80,0xbd,0xe8 ]
+      arch: "CS_ARCH_ARM"
+      options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "pop {r1, pc}"
+        details:
+          arm:
+            operands:
+              -
+                type: ARM_OP_REG
+                reg: r1
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_REG
+                reg: r15
+                access: CS_AC_WRITE
+          writeback: 1
+          regs_read: [ r13 ]
+          regs_write: [ r13, r1, r15 ]
+          groups: [ IsARM, return, jump ]
+  -
+    input:
+      name: "issue 741"
+      bytes: [ 0x83,0xff,0xf7 ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_32 ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "cmp edi, -9"
+  -
+    input:
+      name: "issue 717"
+      bytes: [ 0x48,0x8b,0x04,0x25,0x00,0x00,0x00,0x00 ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_64, CS_OPT_SYNTAX_ATT ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "movq 0, %rax"
+  -
+    input:
+      name: "issue 711"
+      bytes: [ 0xa3,0x44,0xb0,0x00,0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_32, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "mov dword ptr [0x1000b044], eax"
+        details:
+          x86:
+            prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ]
+            opcode: [ 0xa3, 0x00, 0x00, 0x00 ]
+            rex: 0x0
+            addr_size: 4
+            modrm: 0x0
+            disp: 0x1000b044
+            sib: 0x0
+            operands:
+              -
+                type: X86_OP_MEM
+                mem_disp: 0x1000b044
+                size: 4
+                access: CS_AC_WRITE
+              -
+                type: X86_OP_REG
+                reg: eax
+                size: 4
+                access: CS_AC_READ
+          regs_read: [ eax ]
+  -
+    input:
+      name: "issue 613"
+      bytes: [ 0xd9,0x74,0x24,0xd8 ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_64 ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "fnstenv [rsp - 0x28]"
+  -
+    input:
+      name: "issue 554"
+      bytes: [ 0xe7,0x84 ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_32 ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "out 0x84, eax"
+  -
+    input:
+      name: "issue 554"
+      bytes: [ 0xe5,0x8c ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_32 ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "in eax, 0x8c"
+  -
+    input:
+      name: "issue 545"
+      bytes: [ 0x95 ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_32, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "xchg ebp, eax"
+        details:
+          x86:
+            prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ]
+            opcode: [ 0x95, 0x00, 0x00, 0x00 ]
+            rex: 0x0
+            addr_size: 4
+            modrm: 0x0
+            disp: 0x0
+            sib: 0x0
+            operands:
+              -
+                type: X86_OP_REG
+                reg: ebp
+                size: 4
+                access: CS_AC_READ_WRITE
+              -
+                type: X86_OP_REG
+                reg: eax
+                size: 4
+                access: CS_AC_READ_WRITE
+          regs_read: [ ebp, eax ]
+          regs_write: [ ebp, eax ]
+          groups: [ not64bitmode ]
+  -
+    input:
+      name: "issue 544"
+      bytes: [ 0xdf,0x30 ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_32 ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "fbstp tbyte ptr [eax]"
+  -
+    input:
+      name: "issue 544"
+      bytes: [ 0xdf,0x20 ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_32 ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "fbld tbyte ptr [eax]"
+  -
+    input:
+      name: "issue 541"
+      bytes: [ 0x48,0xb8,0x00,0x00,0x00,0x00,0x80,0xf8,0xff,0xff ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_64 ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "movabs rax, 0xfffff88000000000"
+  -
+    input:
+      name: "issue 499"
+      bytes: [ 0x48,0xb8,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x80 ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_64 ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "movabs rax, 0x8000000000000000"
+  -
+    input:
+      name: "issue 492"
+      bytes: [ 0xff,0x18 ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_32 ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "call ptr [eax]"
+  -
+    input:
+      name: "issue 492"
+      bytes: [ 0xff,0x28 ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_32 ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "jmp ptr [eax]"
+  -
+    input:
+      name: "issue 492"
+      bytes: [ 0x0f,0xae,0x04,0x24 ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_32 ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "fxsave [esp]"
+  -
+    input:
+      name: "issue 492"
+      bytes: [ 0x0f,0xae,0x0c,0x24 ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_32 ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "fxrstor [esp]"
+  -
+    input:
+      name: "issue 470"
+      bytes: [ 0x0f,0x01,0x05,0xa0,0x90,0x04,0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_32 ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "sgdt [0x80490a0]"
+  -
+    input:
+      name: "issue 470"
+      bytes: [ 0x0f,0x01,0x0d,0xa7,0x90,0x04,0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_32 ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "sidt [0x80490a7]"
+  -
+    input:
+      name: "issue 470"
+      bytes: [ 0x0f,0x01,0x15,0xa0,0x90,0x04,0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_32 ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "lgdt [0x80490a0]"
+  -
+    input:
+      name: "issue 470"
+      bytes: [ 0x0f,0x01,0x1d,0xa7,0x90,0x04,0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_32 ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "lidt [0x80490a7]"
+  -
+    input:
+      name: "issue 459"
+      bytes: [ 0xd3,0x20,0x11,0xe1 ]
+      arch: "CS_ARCH_ARM"
+      options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "ldrsb r2, [r1, -r3]"
+        details:
+          arm:
+            operands:
+              -
+                type: ARM_OP_REG
+                reg: r2
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_MEM
+                mem_base: r1
+                mem_index: r3
+                mem_scale: 0
+                access: CS_AC_READ
+                subtracted: 1
+          regs_read: [ r1, r3 ]
+          regs_write: [ r2 ]
+          groups: [ IsARM ]
+  -
+    input:
+      name: "issue 456"
+      bytes: [ 0xe8,0x35,0x64 ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_16 ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "call 0x6438"
+  -
+    input:
+      name: "issue 456"
+      bytes: [ 0xe9,0x35,0x64 ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_16 ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "jmp 0x6438"
+  -
+    input:
+      name: "issue 456"
+      bytes: [ 0x66,0xe9,0x35,0x64,0x93,0x53 ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_16 ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "jmp 0x5393643b"
+  -
+    input:
+      name: "issue 456"
+      bytes: [ 0x66,0xe8,0x35,0x64,0x93,0x53 ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_16 ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "call 0x5393643b"
+  -
+    input:
+      name: "issue 456"
+      bytes: [ 0x66,0xe9,0x35,0x64,0x93,0x53 ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_16 ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "jmp 0x5393643b"
+  -
+    input:
+      name: "issue 456"
+      bytes: [ 0x66,0xe8,0x35,0x64 ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_32 ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "call 0x6439"
+  -
+    input:
+      name: "issue 456"
+      bytes: [ 0xe9,0x35,0x64,0x93,0x53 ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_32 ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "jmp 0x5393643a"
+  -
+    input:
+      name: "issue 456"
+      bytes: [ 0x66,0xe9,0x35,0x64 ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_32 ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "jmp 0x6439"
+  -
+    input:
+      name: "issue 458"
+      bytes: [ 0xA1,0x12,0x34,0x90,0x90 ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_32, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "mov eax, dword ptr [0x90903412]"
+        details:
+          x86:
+            prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ]
+            opcode: [ 0xa1, 0x00, 0x00, 0x00 ]
+            rex: 0x0
+            addr_size: 4
+            modrm: 0x0
+            disp: 0x90903412
+            sib: 0x0
+            operands:
+              -
+                type: X86_OP_REG
+                reg: eax
+                size: 4
+                access: CS_AC_WRITE
+              -
+                type: X86_OP_MEM
+                mem_disp: 0x90903412
+                size: 4
+                access: CS_AC_READ
+          regs_write: [ eax ]
+  -
+    input:
+      name: "issue 454"
+      bytes: [ 0xf2,0x6c ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_32 ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "repne insb byte ptr es:[edi], dx"
+  -
+    input:
+      name: "issue 454"
+      bytes: [ 0xf2,0x6d ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_32 ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "repne insd dword ptr es:[edi], dx"
+  -
+    input:
+      name: "issue 454"
+      bytes: [ 0xf2,0x6e ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_32 ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "repne outsb dx, byte ptr [esi]"
+  -
+    input:
+      name: "issue 454"
+      bytes: [ 0xf2,0x6f ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_32 ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "repne outsd dx, dword ptr [esi]"
+  -
+    input:
+      name: "issue 454"
+      bytes: [ 0xf2,0xac ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_32 ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "repne lodsb al, byte ptr [esi]"
+  -
+    input:
+      name: "issue 454"
+      bytes: [ 0xf2,0xad ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_32 ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "repne lodsd eax, dword ptr [esi]"
+  -
+    input:
+      name: "issue 450"
+      bytes: [ 0xff,0x2d,0x34,0x35,0x23,0x01 ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_32, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "jmp ptr [0x1233534]"
+        details:
+          x86:
+            prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ]
+            opcode: [ 0xff, 0x00, 0x00, 0x00 ]
+            rex: 0x0
+            addr_size: 4
+            modrm: 0x2d
+            disp: 0x1233534
+            sib: 0x0
+            operands:
+              -
+                type: X86_OP_MEM
+                mem_disp: 0x1233534
+                size: 6
+          groups: [ jump ]
+  -
+    input:
+      name: "issue 448"
+      bytes: [ 0xea,0x12,0x34,0x56,0x78,0x9a,0xbc ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_32, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "ljmp 0xbc9a:0x78563412"
+        details:
+          x86:
+            prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ]
+            opcode: [ 0xea, 0x00, 0x00, 0x00 ]
+            rex: 0x0
+            addr_size: 4
+            modrm: 0x0
+            disp: 0x0
+            sib: 0x0
+            operands:
+              -
+                type: X86_OP_IMM
+                imm: 0xbc9a
+                size: 2
+              -
+                type: X86_OP_IMM
+                imm: 0x78563412
+                size: 4
+          groups: [ not64bitmode, jump ]
+  -
+    input:
+      name: "issue 426"
+      bytes: [ 0xbb,0x70,0x00,0x00 ]
+      arch: "CS_ARCH_SPARC"
+      options: [ CS_MODE_BIG_ENDIAN ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "popc %g0, %i5"
+  -
+    input:
+      name: "issue 358"
+      bytes: [ 0xe8,0xe3,0xf6,0xff,0xff ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_32, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "call 0xfffff6e8"
+        details:
+          x86:
+            prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ]
+            opcode: [ 0xe8, 0x00, 0x00, 0x00 ]
+            rex: 0x0
+            addr_size: 4
+            modrm: 0x0
+            disp: 0x0
+            sib: 0x0
+            operands:
+              -
+                type: X86_OP_IMM
+                imm: 0xfffff6e8
+                size: 4
+          regs_read: [ esp, eip ]
+          regs_write: [ esp ]
+          groups: [ call, branch_relative, not64bitmode ]
+  -
+    input:
+      name: "issue 353"
+      bytes: [ 0xe6,0xa2 ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_32, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "out 0xa2, al"
+        details:
+          x86:
+            prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ]
+            opcode: [ 0xe6, 0x00, 0x00, 0x00 ]
+            rex: 0x0
+            addr_size: 4
+            modrm: 0x0
+            disp: 0x0
+            sib: 0x0
+            operands:
+              -
+                type: X86_OP_IMM
+                imm: 0xa2
+                size: 1
+              -
+                type: X86_OP_REG
+                reg: al
+                size: 1
+                access: CS_AC_READ
+          regs_read: [ al ]
+  -
+    input:
+      name: "issue 305"
+      bytes: [ 0x34,0x8b ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_32 ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "xor al, 0x8b"
+  -
+    input:
+      name: "issue 298"
+      bytes: [ 0xf3,0x90 ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_32 ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "pause"
+  -
+    input:
+      name: "issue 298"
+      bytes: [ 0x66,0xf3,0xf2,0x0f,0x59,0xff ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_32 ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "mulsd xmm7, xmm7"
+  -
+    input:
+      name: "issue 294"
+      bytes: [ 0xc1,0xe6,0x08 ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_32, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "shl esi, 8"
+        details:
+          x86:
+            prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ]
+            opcode: [ 0xc1, 0x00, 0x00, 0x00 ]
+            rex: 0x0
+            addr_size: 4
+            modrm: 0xe6
+            disp: 0x0
+            sib: 0x0
+            operands:
+              -
+                type: X86_OP_REG
+                reg: esi
+                size: 4
+                access: CS_AC_READ_WRITE
+              -
+                type: X86_OP_IMM
+                imm: 0x8
+                size: 1
+            eflags: [ X86_EFLAGS_MODIFY_CF, X86_EFLAGS_MODIFY_SF, X86_EFLAGS_MODIFY_ZF, X86_EFLAGS_MODIFY_PF, X86_EFLAGS_MODIFY_OF, X86_EFLAGS_UNDEFINED_AF ]
+          regs_read: [ esi ]
+          regs_write: [ eflags, esi ]
+  -
+    input:
+      name: "issue 285"
+      bytes: [ 0x3c,0x12,0x80 ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_32, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "cmp al, 0x12"
+        details:
+          x86:
+            prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ]
+            opcode: [ 0x3c, 0x00, 0x00, 0x00 ]
+            rex: 0x0
+            addr_size: 4
+            modrm: 0x0
+            disp: 0x0
+            sib: 0x0
+            operands:
+              -
+                type: X86_OP_REG
+                reg: al
+                size: 1
+                access: CS_AC_READ
+              -
+                type: X86_OP_IMM
+                imm: 0x12
+                size: 1
+            eflags: [ X86_EFLAGS_MODIFY_AF, X86_EFLAGS_MODIFY_CF, X86_EFLAGS_MODIFY_SF, X86_EFLAGS_MODIFY_ZF, X86_EFLAGS_MODIFY_PF, X86_EFLAGS_MODIFY_OF ]
+          regs_read: [ al ]
+          regs_write: [ eflags ]
+  -
+    input:
+      name: "issue 265"
+      bytes: [ 0x52,0xf8,0x23,0x30 ]
+      arch: "CS_ARCH_ARM"
+      options: [ CS_MODE_THUMB, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "ldr.w r3, [r2, r3, lsl #2]"
+        details:
+          arm:
+            operands:
+              -
+                type: ARM_OP_REG
+                reg: r3
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_MEM
+                mem_base: r2
+                mem_index: r3
+                mem_scale: 0
+                shift_type: ARM_SFT_LSL
+                shift_value: 2
+          regs_read: [ r2, r3 ]
+          regs_write: [ r3 ]
+          groups: [ IsThumb2 ]
+  -
+    input:
+      name: "issue 264"
+      bytes: [ 0x0c,0xbf ]
+      arch: "CS_ARCH_ARM"
+      options: [ CS_MODE_THUMB ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "ite eq"
+  -
+    input:
+      name: "issue 264"
+      bytes: [ 0x17,0x20 ]
+      arch: "CS_ARCH_ARM"
+      options: [ CS_MODE_THUMB ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "movs r0, #0x17"
+  -
+    input:
+      name: "issue 264"
+      bytes: [ 0x4f,0xf0,0xff,0x30 ]
+      arch: "CS_ARCH_ARM"
+      options: [ CS_MODE_THUMB ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "mov.w r0, #0xffffffff"
+  -
+    input:
+      name: "issue 246"
+      bytes: [ 0x52,0xf8,0x23,0xf0 ]
+      arch: "CS_ARCH_ARM"
+      options: [ CS_MODE_THUMB ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "ldr.w pc, [r2, r3, lsl #2]"
+  -
+    input:
+      name: "issue 232"
+      bytes: [ 0x8e,0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_32, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "mov ss, word ptr [eax]"
+        details:
+          x86:
+            prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ]
+            opcode: [ 0x8e, 0x00, 0x00, 0x00 ]
+            rex: 0x0
+            addr_size: 4
+            modrm: 0x10
+            disp: 0x0
+            sib: 0x0
+            operands:
+              -
+                type: X86_OP_REG
+                reg: ss
+                size: 2
+                access: CS_AC_WRITE
+              -
+                type: X86_OP_MEM
+                mem_base: eax
+                size: 2
+                access: CS_AC_READ
+          regs_read: [ eax ]
+          regs_write: [ ss ]
+          groups: [ privilege ]
+  -
+    input:
+      name: "issue 231"
+      bytes: [ 0x66,0x6b,0xc0,0x02 ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_32, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "imul ax, ax, 2"
+        details:
+          x86:
+            prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_OPSIZE, X86_PREFIX_0 ]
+            opcode: [ 0x6b, 0x00, 0x00, 0x00 ]
+            rex: 0x0
+            addr_size: 4
+            modrm: 0xc0
+            disp: 0x0
+            sib: 0x0
+            operands:
+              -
+                type: X86_OP_REG
+                reg: ax
+                size: 2
+                access: CS_AC_WRITE
+              -
+                type: X86_OP_REG
+                reg: ax
+                size: 2
+                access: CS_AC_READ
+              -
+                type: X86_OP_IMM
+                imm: 0x2
+                size: 2
+            eflags: [ X86_EFLAGS_MODIFY_CF, X86_EFLAGS_MODIFY_SF, X86_EFLAGS_MODIFY_OF, X86_EFLAGS_UNDEFINED_ZF, X86_EFLAGS_UNDEFINED_PF, X86_EFLAGS_UNDEFINED_AF ]
+          regs_read: [ ax ]
+          regs_write: [ eflags, ax ]
+  -
+    input:
+      name: "issue 230"
+      bytes: [ 0xec ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_32, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "in al, dx"
+        details:
+          x86:
+            prefix: [ X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0, X86_PREFIX_0 ]
+            opcode: [ 0xec, 0x00, 0x00, 0x00 ]
+            rex: 0x0
+            addr_size: 4
+            modrm: 0x0
+            disp: 0x0
+            sib: 0x0
+            operands:
+              -
+                type: X86_OP_REG
+                reg: al
+                size: 1
+                access: CS_AC_WRITE
+              -
+                type: X86_OP_REG
+                reg: dx
+                size: 2
+                access: CS_AC_READ
+          regs_read: [ dx ]
+          regs_write: [ al ]
+  -
+    input:
+      name: "issue 213"
+      bytes: [ 0xea,0xaa,0xff,0x00,0xf0 ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_16 ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "ljmp 0xf000:0xffaa"
+  -
+    input:
+      name: "issue 191"
+      bytes: [ 0xc5,0xe8,0xc2,0x33,0x9b ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_64 ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "vcmpps xmm6, xmm2, xmmword ptr [rbx], 0x9b"
+  -
+    input:
+      name: "issue 176"
+      bytes: [ 0xfd,0xff,0xff,0x1a ]
+      arch: "CS_ARCH_ARM"
+      options: [ CS_MODE_ARM ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "bne 0xfffffffc"
+  -
+    input:
+      name: "issue 151"
+      bytes: [ 0x4d,0x8d,0x3d,0x02,0x00,0x00,0x00 ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_64 ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "lea r15, [rip + 2]"
+  -
+    input:
+      name: "issue 151"
+      bytes: [ 0xeb,0xb0 ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_64 ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "jmp 0xffffffffffffffb2"
+  -
+    input:
+      name: "issue 134"
+      bytes: [ 0xe7,0x92,0x11,0x80 ]
+      arch: "CS_ARCH_ARM"
+      options: [ CS_MODE_BIG_ENDIAN, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "ldr r1, [r2, r0, lsl #3]"
+        details:
+          arm:
+            operands:
+              -
+                type: ARM_OP_REG
+                reg: r1
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_MEM
+                mem_base: r2
+                mem_index: r0
+                access: CS_AC_READ
+                shift_type: ARM_SFT_LSL
+                shift_value: 3
+          regs_read: [ r2, r0 ]
+          regs_write: [ r1 ]
+          groups: [ IsARM ]
+  -
+    input:
+      name: "issue 133"
+      bytes: [ 0xed,0xdf,0x2b,0x1b ]
+      arch: "CS_ARCH_ARM"
+      options: [ CS_MODE_BIG_ENDIAN, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "vldr d18, [pc, #0x6c]"
+        details:
+          arm:
+            operands:
+              -
+                type: ARM_OP_REG
+                reg: d18
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_MEM
+                mem_base: r15
+                mem_disp: 0x6c
+                access: CS_AC_READ
+          regs_read: [ r15 ]
+          regs_write: [ d18 ]
+          groups: [ HasFPRegs ]
+  -
+    input:
+      name: "issue 132"
+      bytes: [ 0x49,0x19 ]
+      arch: "CS_ARCH_ARM"
+      options: [ CS_MODE_THUMB, CS_MODE_BIG_ENDIAN, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "ldr r1, [pc, #0x64]"
+        details:
+          arm:
+            operands:
+              -
+                type: ARM_OP_REG
+                reg: r1
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_MEM
+                mem_base: r15
+                mem_disp: 0x64
+                access: CS_AC_READ
+          regs_read: [ r15 ]
+          regs_write: [ r1 ]
+          groups: [ IsThumb ]
+  -
+    input:
+      name: "issue 130"
+      bytes: [ 0xe1,0xa0,0xf0,0x0e ]
+      arch: "CS_ARCH_ARM"
+      options: [ CS_MODE_BIG_ENDIAN, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "mov pc, lr"
+        details:
+          arm:
+            operands:
+              -
+                type: ARM_OP_REG
+                reg: r15
+                access: CS_AC_WRITE
+              -
+                type: ARM_OP_REG
+                reg: r14
+                access: CS_AC_READ
+          regs_read: [ r14 ]
+          regs_write: [ r15 ]
+          groups: [ jump, return, IsARM ]
+  -
+    input:
+      name: "issue 85"
+      bytes: [ 0xee,0x3f,0xbf,0x29 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ CS_MODE_LITTLE_ENDIAN ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "stp w14, w15, [sp, #-8]!"
+  -
+    input:
+      name: "issue 82"
+      bytes: [ 0xf2,0x66,0xaf ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_64 ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "repne scasw ax, word ptr [rdi]"
+  -
+    input:
+      name: "issue 35"
+      bytes: [ 0xe8,0xc6,0x02,0x00,0x00 ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_32 ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "call 0x2cb"
+  -
+    input:
+      name: "issue 8"
+      bytes: [ 0xff,0x8c,0xf9,0xff,0xff,0x9b,0xf9 ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_32 ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "dec dword ptr [ecx + edi*8 - 0x6640001]"
+  -
+    input:
+      name: "issue 29"
+      bytes: [ 0x00,0x00,0x00,0x4c ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ CS_MODE_ARM ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "st4 { v0.16b, v1.16b, v2.16b, v3.16b }, [x0]"
+  -
+    input:
+      name: "issue 2233 ARM write to PC is branch"
+      bytes: [ 0x87,0x46 ]
+      arch: "CS_ARCH_ARM"
+      options: [ CS_MODE_THUMB, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "mov pc, r0"
+        details:
+          groups: [ IsThumb, jump ]
+  -
+    input:
+      name: "issue 2128"
+      bytes: [ 0x4c,0x85,0x7d,0x30 ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_64, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "test	qword ptr [rbp + 0x30], r15"
+        details:
+          x86:
+            operands:
+              -
+                type: X86_OP_MEM
+              -
+                type: X86_OP_REG
+                reg: r15
+                access: CS_AC_READ
+          regs_read: [ rbp, r15 ]
+          regs_write: [ rflags ]
+  -
+    input:
+      name: "issue 2079"
+      bytes: [ 0xd1,0x10 ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_32, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "rcl	dword ptr [eax]"
+        details:
+          x86:
+            operands:
+              -
+                type: X86_OP_MEM
+                mem_base: eax
+              -
+                type: X86_OP_IMM
+                imm: 0x1
+  -
+    input:
+      name: "issue 2244"
+      bytes: [ 0xc5,0xfb,0xc2,0xda,0x06 ]
+      arch: "CS_ARCH_X86"
+      options: [ CS_MODE_64, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "vcmpnlesd	xmm3, xmm0, xmm2"
+        id: 797
+  -
+    input:
+      name: "issue 2349"
+      bytes: [ 0xcf, 0x41, 0xd0, 0x28 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ CS_MODE_LOONGARCH64, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "ld.d $t3, $t2, 0x410"
+        details:
+          loongarch:
+            operands:
+              -
+                type: LOONGARCH_OP_REG
+              -
+                type: LOONGARCH_OP_MEM
+                mem_base: t2
+                mem_disp: 0x410
+  -
+    input:
+      name: "issue 2349"
+      bytes: [ 0x8d, 0x59, 0x10, 0x27 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ CS_MODE_LOONGARCH64, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "stptr.d $t1, $t0, 0x1058"
+        details:
+          loongarch:
+            operands:
+              -
+                type: LOONGARCH_OP_REG
+              -
+                type: LOONGARCH_OP_MEM
+                mem_base: t0
+                mem_disp: 0x1058
+  -
+    input:
+      name: "issue 2349"
+      bytes: [ 0xa4, 0x15, 0x20, 0x30 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ CS_MODE_LOONGARCH64, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "vldrepl.w $vr4, $t1, 0x14"
+        details:
+          loongarch:
+            operands:
+              -
+                type: LOONGARCH_OP_REG
+              -
+                type: LOONGARCH_OP_MEM
+                mem_base: t1
+                mem_disp: 0x14
+  -
+    input:
+      name: "issue 2349"
+      bytes: [ 0x68, 0x22, 0xc2, 0x2a ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ CS_MODE_LOONGARCH64, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "preld 8, $t7, 0x88"
+        details:
+          loongarch:
+            operands:
+              -
+                type: LOONGARCH_OP_IMM
+                imm: 0x8
+              -
+                type: LOONGARCH_OP_MEM
+                mem_base: t7
+                mem_disp: 0x88
+  -
+    input:
+      name: "issue 2349"
+      bytes: [ 0xe1, 0x2c, 0x30, 0x38 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ CS_MODE_LOONGARCH64, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "fldx.s $fa1, $a3, $a7"
+        details:
+          loongarch:
+            operands:
+              -
+                type: LOONGARCH_OP_REG
+              -
+                type: LOONGARCH_OP_MEM
+                mem_base: a3
+                mem_index: a7
+  -
+    input:
+      name: "issue 2349"
+      bytes: [ 0xc4, 0x14, 0x57, 0x38 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ CS_MODE_LOONGARCH64, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "sc.q $a0, $a1, $a2"
+        details:
+          loongarch:
+            operands:
+              -
+                type: LOONGARCH_OP_REG
+                reg: a0
+              -
+                type: LOONGARCH_OP_REG
+                reg: a1
+              -
+                type: LOONGARCH_OP_MEM
+                mem_base: a2
+  -
+    input:
+      name: "issue 2349"
+      bytes: [ 0xc4, 0x14, 0x61, 0x38 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ CS_MODE_LOONGARCH64, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "amadd.w $a0, $a1, $a2"
+        details:
+          loongarch:
+            operands:
+              -
+                type: LOONGARCH_OP_REG
+                reg: a0
+              -
+                type: LOONGARCH_OP_REG
+                reg: a1
+              -
+                type: LOONGARCH_OP_MEM
+                mem_base: a2
+  -
+    input:
+      name: "issue 2349"
+      bytes: [ 0xa4, 0x18, 0x78, 0x38 ]
+      arch: "CS_ARCH_LOONGARCH"
+      options: [ CS_MODE_LOONGARCH64, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "ldgt.b $a0, $a1, $a2"
+        details:
+          loongarch:
+            operands:
+              -
+                type: LOONGARCH_OP_REG
+              -
+                type: LOONGARCH_OP_MEM
+                mem_base: a1
+              -
+                type: LOONGARCH_OP_REG
+                reg: a2
+  -
+    input:
+      name: "issue 2268"
+      bytes: [ 0x00,0x80,0x58,0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "fadd z0.h, p0/m, z0.h, #0.5"
+        details:
+          aarch64:
+            operands:
+              -
+                type: AARCH64_OP_REG
+                access: CS_AC_READ_WRITE
+              -
+                type: AARCH64_OP_PRED
+                access: CS_AC_READ
+              -
+                type: AARCH64_OP_REG
+                access: CS_AC_READ_WRITE
+              -
+                type: AARCH64_OP_SYSIMM
+                sub_type: AARCH64_OP_EXACTFPIMM
+                sys_raw_val: 1
+  -
+    input:
+      name: "issue 2268"
+      bytes: [ 0x20,0x80,0x58,0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "fadd z0.h, p0/m, z0.h, #1.0"
+        details:
+          aarch64:
+            operands:
+              -
+                type: AARCH64_OP_REG
+                access: CS_AC_READ_WRITE
+              -
+                type: AARCH64_OP_PRED
+                access: CS_AC_READ
+              -
+                type: AARCH64_OP_REG
+                access: CS_AC_READ_WRITE
+              -
+                type: AARCH64_OP_SYSIMM
+                sub_type: AARCH64_OP_EXACTFPIMM
+                sys_raw_val: 2
+  -
+    input:
+      name: "issue 2268"
+      bytes: [ 0x3f,0x9c,0xda,0x65 ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "fmul z31.d, p7/m, z31.d, #2.0"
+        details:
+          aarch64:
+            operands:
+              -
+                type: AARCH64_OP_REG
+                access: CS_AC_READ_WRITE
+              -
+                type: AARCH64_OP_PRED
+                access: CS_AC_READ
+              -
+                type: AARCH64_OP_REG
+                access: CS_AC_READ_WRITE
+              -
+                type: AARCH64_OP_SYSIMM
+                sub_type: AARCH64_OP_EXACTFPIMM
+                sys_raw_val: 3
+  -
+    input:
+      name: "issue 2268"
+      bytes: [ 0x6a,0xd9,0xf8,0x7e ]
+      arch: "CS_ARCH_AARCH64"
+      options: [ CS_MODE_ARM, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "fcmle h10, h11, #0.0"
+        details:
+          aarch64:
+            operands:
+              -
+                type: AARCH64_OP_REG
+                access: CS_AC_WRITE
+              -
+                type: AARCH64_OP_REG
+                access: CS_AC_READ
+              -
+                type: AARCH64_OP_SYSIMM
+                sub_type: AARCH64_OP_EXACTFPIMM
+                sys_raw_val: 0
+  -
+    input:
+      name: "issue 2419"
+      bytes: [ 0x12,0xbf,0xff,0xff ]
+      arch: "CS_ARCH_SPARC"
+      options: [ CS_MODE_BIG_ENDIAN, CS_OPT_DETAIL ]
+      address: 0x0
+    expected:
+      insns:
+      -
+        asm_text: "bne -4"
+        details:
+          sparc:
+            cc: SPARC_CC_ICC_NE
diff --git a/tests/test_aarch64.c b/tests/test_aarch64.c
deleted file mode 100644
index 3c0aa7afb..000000000
--- a/tests/test_aarch64.c
+++ /dev/null
@@ -1,370 +0,0 @@
-/* Capstone Disassembler Engine */
-/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
-
-#include "capstone/aarch64.h"
-#include <stdio.h>
-#include <stdlib.h>
-
-#include <capstone/platform.h>
-#include <capstone/capstone.h>
-
-static csh handle;
-
-struct platform {
-	cs_arch arch;
-	cs_mode mode;
-	unsigned char *code;
-	size_t size;
-	const char *comment;
-};
-
-static void print_string_hex(const char *comment, unsigned char *str, size_t len)
-{
-	unsigned char *c;
-
-	printf("%s", comment);
-	for (c = str; c < str + len; c++) {
-		printf("0x%02x ", *c & 0xff);
-	}
-
-	printf("\n");
-}
-
-static void print_insn_detail(cs_insn *ins)
-{
-	cs_aarch64 *aarch64;
-	int i;
-	cs_regs regs_read, regs_write;
-	unsigned char regs_read_count, regs_write_count;
-	unsigned char access;
-
-	// detail can be NULL if SKIPDATA option is turned ON
-	if (ins->detail == NULL)
-		return;
-
-	aarch64 = &(ins->detail->aarch64);
-	if (aarch64->op_count)
-		printf("\top_count: %u\n", aarch64->op_count);
-
-	for (i = 0; i < aarch64->op_count; i++) {
-		cs_aarch64_op *op = &(aarch64->operands[i]);
-		switch(op->type) {
-		default:
-			break;
-		case AARCH64_OP_REG:
-			printf("\t\toperands[%u].type: REG = %s\n", i, cs_reg_name(handle, op->reg));
-			break;
-		case AARCH64_OP_IMM:
-			printf("\t\toperands[%u].type: IMM = 0x%" PRIx64 "\n", i, op->imm);
-			break;
-		case AARCH64_OP_FP:
-#if defined(_KERNEL_MODE)
-			// Issue #681: Windows kernel does not support formatting float point
-			printf("\t\toperands[%u].type: FP = <float_point_unsupported>\n", i);
-#else
-			printf("\t\toperands[%u].type: FP = %f\n", i, op->fp);
-#endif
-			break;
-		case AARCH64_OP_MEM:
-			printf("\t\toperands[%u].type: MEM\n", i);
-			if (op->mem.base != AARCH64_REG_INVALID)
-				printf("\t\t\toperands[%u].mem.base: REG = %s\n", i, cs_reg_name(handle, op->mem.base));
-			if (op->mem.index != AARCH64_REG_INVALID)
-				printf("\t\t\toperands[%u].mem.index: REG = %s\n", i, cs_reg_name(handle, op->mem.index));
-			if (op->mem.disp != 0)
-				printf("\t\t\toperands[%u].mem.disp: 0x%x\n", i, op->mem.disp);
-			if (ins->detail->aarch64.post_index)
-				printf("\t\t\tpost-indexed: true\n");
-
-			break;
-		case AARCH64_OP_SME:
-			printf("\t\toperands[%u].type: SME_MATRIX\n", i);
-			printf("\t\toperands[%u].sme.type: %d\n", i, op->sme.type);
-
-			if (op->sme.tile != AARCH64_REG_INVALID)
-				printf("\t\toperands[%u].sme.tile: %s\n", i, cs_reg_name(handle, op->sme.tile));
-			if (op->sme.slice_reg != AARCH64_REG_INVALID)
-				printf("\t\toperands[%u].sme.slice_reg: %s\n", i, cs_reg_name(handle, op->sme.slice_reg));
-			if (op->sme.slice_offset.imm != -1 || op->sme.slice_offset.imm_range.first != -1) {
-				printf("\t\toperands[%u].sme.slice_offset: ", i);
-				if (op->sme.has_range_offset)
-					printf("%hhd:%hhd\n", op->sme.slice_offset.imm_range.first, op->sme.slice_offset.imm_range.offset);
-				else
-					printf("%d\n", op->sme.slice_offset.imm);
-			}
-			if (op->sme.slice_reg != AARCH64_REG_INVALID || op->sme.slice_offset.imm != -1)
-				printf("\t\toperands[%u].sme.is_vertical: %s\n", i, (op->sme.is_vertical ? "true" : "false"));
-			break;
-		case AARCH64_OP_PRED:
-			printf("\t\toperands[%u].type: PREDICATE\n", i);
-			if (op->pred.reg != AARCH64_REG_INVALID)
-				printf("\t\toperands[%u].pred.reg: %s\n", i, cs_reg_name(handle, op->pred.reg));
-			if (op->pred.vec_select != AARCH64_REG_INVALID)
-				printf("\t\toperands[%u].pred.vec_select: %s\n", i, cs_reg_name(handle, op->pred.vec_select));
-			if (op->pred.imm_index != -1)
-				printf("\t\toperands[%u].pred.imm_index: %d\n", i, op->pred.imm_index);
-			break;
-		case AARCH64_OP_CIMM:
-			printf("\t\toperands[%u].type: C-IMM = %u\n", i, (int)op->imm);
-			break;
-		case AARCH64_OP_SYSREG:
-			printf("\t\toperands[%u].type: SYS REG:\n", i);
-			switch (op->sysop.sub_type) {
-			default:
-				printf("Sub type %d not handled.\n", op->sysop.sub_type);
-				break;
-			case AARCH64_OP_REG_MRS:
-				printf("\t\toperands[%u].subtype: REG_MRS = 0x%x\n", i, op->sysop.reg.sysreg);
-				break;
-			case AARCH64_OP_REG_MSR:
-				printf("\t\toperands[%u].subtype: REG_MSR = 0x%x\n", i, op->sysop.reg.sysreg);
-				break;
-			case AARCH64_OP_TLBI:
-				printf("\t\toperands[%u].subtype TLBI = 0x%x\n", i, op->sysop.reg.tlbi);
-				break;
-			case AARCH64_OP_IC:
-				printf("\t\toperands[%u].subtype IC = 0x%x\n", i, op->sysop.reg.ic);
-				break;
-			}
-			break;
-		case AARCH64_OP_SYSALIAS:
-			printf("\t\toperands[%u].type: SYS ALIAS:\n", i);
-			switch (op->sysop.sub_type) {
-			default:
-				printf("Sub type %d not handled.\n", op->sysop.sub_type);
-				break;
-			case AARCH64_OP_SVCR:
-				if(op->sysop.alias.svcr == AARCH64_SVCR_SVCRSM)
-					printf("\t\t\toperands[%u].svcr: BIT = SM\n", i);
-				else if(op->sysop.alias.svcr == AARCH64_SVCR_SVCRZA)
-					printf("\t\t\toperands[%u].svcr: BIT = ZA\n", i);
-				else if(op->sysop.alias.svcr == AARCH64_SVCR_SVCRSMZA)
-					printf("\t\t\toperands[%u].svcr: BIT = SM & ZA\n", i);
-				break;
-			case AARCH64_OP_AT:
-				printf("\t\toperands[%u].subtype AT = 0x%x\n", i, op->sysop.alias.at);
-				break;
-			case AARCH64_OP_DB:
-				printf("\t\toperands[%u].subtype DB = 0x%x\n", i, op->sysop.alias.db);
-				break;
-			case AARCH64_OP_DC:
-				printf("\t\toperands[%u].subtype DC = 0x%x\n", i, op->sysop.alias.dc);
-				break;
-			case AARCH64_OP_ISB:
-				printf("\t\toperands[%u].subtype ISB = 0x%x\n", i, op->sysop.alias.isb);
-				break;
-			case AARCH64_OP_TSB:
-				printf("\t\toperands[%u].subtype TSB = 0x%x\n", i, op->sysop.alias.tsb);
-				break;
-			case AARCH64_OP_PRFM:
-				printf("\t\toperands[%u].subtype PRFM = 0x%x\n", i, op->sysop.alias.prfm);
-				break;
-			case AARCH64_OP_SVEPRFM:
-				printf("\t\toperands[%u].subtype SVEPRFM = 0x%x\n", i, op->sysop.alias.sveprfm);
-				break;
-			case AARCH64_OP_RPRFM:
-				printf("\t\toperands[%u].subtype RPRFM = 0x%x\n", i, op->sysop.alias.rprfm);
-				break;
-			case AARCH64_OP_PSTATEIMM0_15:
-				printf("\t\toperands[%u].subtype PSTATEIMM0_15 = 0x%x\n", i, op->sysop.alias.pstateimm0_15);
-				break;
-			case AARCH64_OP_PSTATEIMM0_1:
-				printf("\t\toperands[%u].subtype PSTATEIMM0_1 = 0x%x\n", i, op->sysop.alias.pstateimm0_1);
-				break;
-			case AARCH64_OP_PSB:
-				printf("\t\toperands[%u].subtype PSB = 0x%x\n", i, op->sysop.alias.psb);
-				break;
-			case AARCH64_OP_BTI:
-				printf("\t\toperands[%u].subtype BTI = 0x%x\n", i, op->sysop.alias.bti);
-				break;
-			case AARCH64_OP_SVEPREDPAT:
-				printf("\t\toperands[%u].subtype SVEPREDPAT = 0x%x\n", i, op->sysop.alias.svepredpat);
-				break;
-			case AARCH64_OP_SVEVECLENSPECIFIER:
-				printf("\t\toperands[%u].subtype SVEVECLENSPECIFIER = 0x%x\n", i, op->sysop.alias.sveveclenspecifier);
-				break;
-			}
-			break;
-		case AARCH64_OP_SYSIMM:
-			printf("\t\toperands[%u].type: SYS IMM:\n", i);
-			switch(op->sysop.sub_type) {
-			default:
-				printf("Sub type %d not handled.\n", op->sysop.sub_type);
-				break;
-			case AARCH64_OP_EXACTFPIMM:
-				printf("\t\toperands[%u].subtype EXACTFPIMM = %d\n", i, op->sysop.imm.exactfpimm);
-				break;
-			case AARCH64_OP_DBNXS:
-				printf("\t\toperands[%u].subtype DBNXS = %d\n", i, op->sysop.imm.dbnxs);
-				break;
-			}
-			break;
-		}
-		
-		access = op->access;
-		switch(access) {
-			default:
-				break;
-			case CS_AC_READ:
-				printf("\t\toperands[%u].access: READ\n", i);
-				break;
-			case CS_AC_WRITE:
-				printf("\t\toperands[%u].access: WRITE\n", i);
-				break;
-			case CS_AC_READ | CS_AC_WRITE:
-				printf("\t\toperands[%u].access: READ | WRITE\n", i);
-				break;
-		}
-		
-		if (op->shift.type != AARCH64_SFT_INVALID &&
-			op->shift.value)
-			printf("\t\t\tShift: type = %u, value = %u\n",
-				   op->shift.type, op->shift.value);
-
-		if (op->ext != AARCH64_EXT_INVALID)
-			printf("\t\t\tExt: %u\n", op->ext);
-
-		if (op->vas != AARCH64LAYOUT_INVALID)
-			printf("\t\t\tVector Arrangement Specifier: 0x%x\n", op->vas);
-
-		if (op->vector_index != -1)
-			printf("\t\t\tVector Index: %u\n", op->vector_index);
-	}
-
-	if (aarch64->update_flags)
-		printf("\tUpdate-flags: True\n");
-
-	if (ins->detail->writeback)
-		printf("\tWrite-back: True\n");
-
-	if (aarch64->cc != AArch64CC_Invalid)
-		printf("\tCode-condition: %u\n", aarch64->cc);
-
-	// Print out all registers accessed by this instruction (either implicit or explicit)
-	if (!cs_regs_access(handle, ins,
-				regs_read, &regs_read_count,
-				regs_write, &regs_write_count)) {
-		if (regs_read_count) {
-			printf("\tRegisters read:");
-			for(i = 0; i < regs_read_count; i++) {
-				printf(" %s", cs_reg_name(handle, regs_read[i]));
-			}
-			printf("\n");
-		}
-
-		if (regs_write_count) {
-			printf("\tRegisters modified:");
-			for(i = 0; i < regs_write_count; i++) {
-				printf(" %s", cs_reg_name(handle, regs_write[i]));
-			}
-			printf("\n");
-		}
-	}
-
-	printf("\n");
-}
-
-static void test()
-{
-#define AArch64_CODE "\x09\x00\x38\xd5" \
-    "\xbf\x40\x00\xd5" \
-    "\x0c\x05\x13\xd5" \
-    "\x20\x50\x02\x0e" \
-    "\x20\xe4\x3d\x0f" \
-	"\x00\x18\xa0\x5f" \
-	"\xa2\x00\xae\x9e" \
-    "\x9f\x37\x03\xd5" \
-	"\xbf\x33\x03\xd5" \
-	"\xdf\x3f\x03\xd5" \
-	"\x21\x7c\x02\x9b" \
-	"\x21\x7c\x00\x53" \
-	"\x00\x40\x21\x4b" \
-	"\xe1\x0b\x40\xb9" \
-	"\x20\x04\x81\xda" \
-	"\x20\x08\x02\x8b" \
-	"\x10\x5b\xe8\x3c" \
-	"\xfd\x7b\xba\xa9" \
-	"\xfd\xc7\x43\xf8"
-
-	struct platform platforms[] = {
-		{
-			CS_ARCH_AARCH64,
-			CS_MODE_ARM,
-			(unsigned char *)AArch64_CODE,
-			sizeof(AArch64_CODE) - 1,
-			"AARCH64"
-		},
-	};
-
-	uint64_t address = 0x2c;
-	cs_insn *insn;
-	int i;
-	size_t count;
-
-	for (i = 0; i < sizeof(platforms)/sizeof(platforms[0]); i++) {
-		cs_err err = cs_open(platforms[i].arch, platforms[i].mode, &handle);
-		if (err) {
-			printf("Failed on cs_open() with error returned: %u\n", err);
-			abort();
-		}
-
-		cs_option(handle, CS_OPT_DETAIL, CS_OPT_ON);
-
-		count = cs_disasm(handle, platforms[i].code, platforms[i].size, address, 0, &insn);
-		if (count) {
-			size_t j;
-
-			printf("****************\n");
-			printf("Platform: %s\n", platforms[i].comment);
-			print_string_hex("Code: ", platforms[i].code, platforms[i].size);
-			printf("Disasm:\n");
-
-			for (j = 0; j < count; j++) {
-				printf("0x%" PRIx64 ":\t%s\t%s\n", insn[j].address, insn[j].mnemonic, insn[j].op_str);
-				print_insn_detail(&insn[j]);
-			}
-			printf("0x%" PRIx64 ":\n", insn[j-1].address + insn[j-1].size);
-
-			// free memory allocated by cs_disasm()
-			cs_free(insn, count);
-		} else {
-			printf("****************\n");
-			printf("Platform: %s\n", platforms[i].comment);
-			print_string_hex("Code: ", platforms[i].code, platforms[i].size);
-			printf("ERROR: Failed to disasm given code!\n");
-			abort();
-		}
-
-		printf("\n");
-
-		cs_close(&handle);
-	}
-}
-
-int test_macros() {
-	assert(CS_AARCH64(_INS_BL) == AARCH64_INS_BL);
-	assert(CS_AARCH64pre(CS_ARCH_) == CS_ARCH_AARCH64);
-	assert(CS_AARCH64CC(_AL) == AArch64CC_AL);
-	assert(CS_AARCH64_VL_(16B) == AARCH64LAYOUT_VL_16B);
-	cs_detail detail = { 0 };
-	CS_cs_aarch64() aarch64_detail = { 0 };
-	detail.aarch64 = aarch64_detail;
-	CS_aarch64_op() op = { 0 };
-	detail.CS_aarch64_.operands[0] = op;
-	CS_aarch64_reg() reg = 1;
-	CS_aarch64_cc() cc = AArch64CC_AL;
-	CS_aarch64_extender() aarch64_extender = AARCH64_EXT_SXTB;
-	CS_aarch64_shifter() aarch64_shifter = AARCH64_SFT_LSL;
-	CS_aarch64_vas() aarch64_vas = AARCH64LAYOUT_VL_16B;
-	// Do something with them to prevent compiler warnings.
-	return reg + cc + aarch64_extender + aarch64_shifter + aarch64_vas + detail.aarch64.cc;
-
-}
-
-int main()
-{
-	test();
-	test_macros();
-
-	return 0;
-}
diff --git a/tests/test_all.sh b/tests/test_all.sh
deleted file mode 100644
index 1ff49959b..000000000
--- a/tests/test_all.sh
+++ /dev/null
@@ -1,23 +0,0 @@
-./test_arm
-./test_aarch64
-./test_basic
-./test_bpf
-./test_customized_mnem
-./test_detail
-./test_evm
-./test_iter
-./test_m680x
-./test_m68k
-./test_mips
-./test_mos65xx
-./test_ppc
-./test_skipdata
-./test_sparc
-./test_systemz
-./test_tms320c64x
-./test_wasm
-./test_winkernel
-./test_x86
-./test_xcore
-./test_alpha
-./test_hppa
\ No newline at end of file
diff --git a/tests/test_alpha.c b/tests/test_alpha.c
deleted file mode 100644
index 0206f25f6..000000000
--- a/tests/test_alpha.c
+++ /dev/null
@@ -1,144 +0,0 @@
-/* Capstone Disassembler Engine */
-/* By Dmitry Sibirtsev <sibirtsevdl@gmail.com>, 2023 */
-
-#include <stdio.h>
-
-#include <capstone/platform.h>
-#include <capstone/capstone.h>
-
-struct platform {
-	cs_arch arch;
-	cs_mode mode;
-	unsigned char *code;
-	size_t size;
-	char *comment;
-};
-
-static csh handle;
-
-static void print_string_hex(char *comment, unsigned char *str, size_t len)
-{
-	unsigned char *c;
-
-	printf("%s", comment);
-	for (c = str; c < str + len; c++) {
-		printf("0x%02x ", *c & 0xff);
-	}
-
-	printf("\n");
-}
-
-static void print_insn_detail(cs_insn *ins)
-{
-	cs_alpha *alpha;
-	int i;
-
-	// detail can be NULL on "data" instruction if SKIPDATA option is turned ON
-	if (ins->detail == NULL)
-		return;
-
-	alpha = &(ins->detail->alpha);
-	if (alpha->op_count)
-		printf("\top_count: %u\n", alpha->op_count);
-
-	for (i = 0; i < alpha->op_count; i++) {
-		cs_alpha_op *op = &(alpha->operands[i]);
-		switch ((int)op->type) {
-		default:
-			break;
-		case ALPHA_OP_REG:
-			printf("\t\toperands[%u].type: REG = %s\n", i,
-			       cs_reg_name(handle, op->reg));
-			break;
-		case ALPHA_OP_IMM:
-			printf("\t\toperands[%u].type: IMM = 0x%x\n", i,
-			       op->imm);
-			break;
-		}
-	}
-
-	printf("\n");
-}
-
-static void test()
-{
-#define ALPHA_CODE \
-	"\x02\x00\xbb\x27\x50\x7a\xbd\x23\xd0\xff\xde\x23\x00\x00\x5e\xb7"
-#define ALPHA_CODE_BE \
-	"\x27\xbb\x00\x02\x23\xbd\x7a\x50\x23\xde\xff\xd0\xb7\x5e\x00\x00"
-
-	struct platform platforms[] = {
-		{
-			CS_ARCH_ALPHA,
-			CS_MODE_LITTLE_ENDIAN,
-			(unsigned char *)ALPHA_CODE,
-			sizeof(ALPHA_CODE) - 1,
-			"Alpha (Little-endian)",
-		},
-		{
-			CS_ARCH_ALPHA,
-			CS_MODE_BIG_ENDIAN,
-			(unsigned char *)ALPHA_CODE_BE,
-			sizeof(ALPHA_CODE) - 1,
-			"Alpha (Big-endian)",
-		},
-	};
-
-	uint64_t address = 0x1000;
-	cs_insn *insn;
-	int i;
-	size_t count;
-
-	for (i = 0; i < sizeof(platforms) / sizeof(platforms[0]); i++) {
-		cs_err err =
-			cs_open(platforms[i].arch, platforms[i].mode, &handle);
-		if (err) {
-			printf("Failed on cs_open() with error returned: %u\n",
-			       err);
-			continue;
-		}
-
-		cs_option(handle, CS_OPT_DETAIL, CS_OPT_ON);
-
-		count = cs_disasm(handle, platforms[i].code, platforms[i].size,
-				  address, 0, &insn);
-		if (count) {
-			size_t j;
-
-			printf("****************\n");
-			printf("Platform: %s\n", platforms[i].comment);
-			print_string_hex("Code: ", platforms[i].code,
-					 platforms[i].size);
-			printf("Disasm:\n");
-
-			for (j = 0; j < count; j++) {
-				printf("0x%" PRIx64 ":\t%s\t%s\n",
-				       insn[j].address, insn[j].mnemonic,
-				       insn[j].op_str);
-				print_insn_detail(&insn[j]);
-			}
-			printf("0x%" PRIx64 ":\n",
-			       insn[j - 1].address + insn[j - 1].size);
-
-			// free memory allocated by cs_disasm()
-			cs_free(insn, count);
-		} else {
-			printf("****************\n");
-			printf("Platform: %s\n", platforms[i].comment);
-			print_string_hex("Code:", platforms[i].code,
-					 platforms[i].size);
-			printf("ERROR: Failed to disasm given code!\n");
-		}
-
-		printf("\n");
-
-		cs_close(&handle);
-	}
-}
-
-int main()
-{
-	test();
-
-	return 0;
-}
diff --git a/tests/test_arm.c b/tests/test_arm.c
deleted file mode 100644
index 0696de572..000000000
--- a/tests/test_arm.c
+++ /dev/null
@@ -1,334 +0,0 @@
-/* Capstone Disassembler Engine */
-/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
-
-#include <stdio.h>
-#include <stdlib.h>
-
-#include <capstone/platform.h>
-#include <capstone/capstone.h>
-
-static csh handle;
-
-struct platform {
-	cs_arch arch;
-	cs_mode mode;
-	unsigned char *code;
-	size_t size;
-	const char *comment;
-	int syntax;
-};
-
-static void print_string_hex(const char *comment, unsigned char *str, size_t len)
-{
-	unsigned char *c;
-
-	printf("%s", comment);
-	for (c = str; c < str + len; c++) {
-		printf("0x%02x ", *c & 0xff);
-	}
-
-	printf("\n");
-}
-
-static void print_insn_detail(csh cs_handle, cs_insn *ins)
-{
-	cs_arm *arm;
-	int i;
-	cs_regs regs_read, regs_write;
-	uint8_t regs_read_count, regs_write_count;
-
-	// detail can be NULL on "data" instruction if SKIPDATA option is turned ON
-	if (ins->detail == NULL)
-		return;
-
-	arm = &(ins->detail->arm);
-
-	if (arm->op_count)
-		printf("\top_count: %u\n", arm->op_count);
-
-	for (i = 0; i < arm->op_count; i++) {
-		cs_arm_op *op = &(arm->operands[i]);
-		switch((int)op->type) {
-			default:
-				break;
-			case ARM_OP_REG:
-				printf("\t\toperands[%u].type: REG = %s\n", i, cs_reg_name(cs_handle, op->reg));
-				break;
-			case ARM_OP_IMM:
-				if (op->imm < 0)
-					printf("\t\toperands[%u].type: IMM = -0x%" PRIx64 "\n", i, -(op->imm));
-				else
-					printf("\t\toperands[%u].type: IMM = 0x%" PRIx64 "\n", i, op->imm);
-				break;
-			case ARM_OP_FP:
-#if defined(_KERNEL_MODE)
-				// Issue #681: Windows kernel does not support formatting float point
-				printf("\t\toperands[%u].type: FP = <float_point_unsupported>\n", i);
-#else
-				printf("\t\toperands[%u].type: FP = %f\n", i, op->fp);
-#endif
-				break;
-			case ARM_OP_MEM:
-				printf("\t\toperands[%u].type: MEM\n", i);
-				if (op->mem.base != ARM_REG_INVALID)
-					printf("\t\t\toperands[%u].mem.base: REG = %s\n",
-							i, cs_reg_name(cs_handle, op->mem.base));
-				if (op->mem.index != ARM_REG_INVALID)
-					printf("\t\t\toperands[%u].mem.index: REG = %s\n",
-							i, cs_reg_name(cs_handle, op->mem.index));
-				if (op->mem.scale != 1)
-					printf("\t\t\toperands[%u].mem.scale: %u\n", i, op->mem.scale);
-				if (op->mem.disp != 0)
-					printf("\t\t\toperands[%u].mem.disp: 0x%x\n", i, op->mem.disp);
-				if (op->mem.lshift != 0)
-					printf("\t\t\toperands[%u].mem.lshift: 0x%x\n", i, op->mem.lshift);
-
-				break;
-			case ARM_OP_PIMM:
-				printf("\t\toperands[%u].type: P-IMM = %" PRIu64 "\n", i, op->imm);
-				break;
-			case ARM_OP_CIMM:
-				printf("\t\toperands[%u].type: C-IMM = %" PRIu64 "\n", i, op->imm);
-				break;
-			case ARM_OP_SETEND:
-				printf("\t\toperands[%u].type: SETEND = %s\n", i, op->setend == ARM_SETEND_BE? "be" : "le");
-				break;
-			case ARM_OP_SYSM:
-				printf("\t\toperands[%u].type: SYSM = 0x%" PRIx16 "\n", i, op->sysop.sysm);
-				printf("\t\toperands[%u].type: MASK = %" PRIu8 "\n", i, op->sysop.msr_mask);
-				break;
-			case ARM_OP_SYSREG:
-				printf("\t\toperands[%u].type: SYSREG = %s\n", i, cs_reg_name(handle, (uint32_t) op->sysop.reg.mclasssysreg));
-				printf("\t\toperands[%u].type: MASK = %" PRIu8 "\n", i, op->sysop.msr_mask);
-				break;
-			case ARM_OP_BANKEDREG:
-				// FIXME: Printing the name is currenliy not supported if the encodings overlap
-				// with system registers.
-				printf("\t\toperands[%u].type: BANKEDREG = %" PRIu32 "\n", i, (uint32_t) op->sysop.reg.bankedreg);
-				if (op->sysop.msr_mask != UINT8_MAX)
-					printf("\t\toperands[%u].type: MASK = %" PRIu8 "\n", i, op->sysop.msr_mask);
-			case ARM_OP_SPSR:
-			case ARM_OP_CPSR: {
-				const char type = op->type == ARM_OP_SPSR ? 'S' : 'C';
-				printf("\t\toperands[%u].type: %cPSR = ", i, type);
-				uint16_t field = op->sysop.psr_bits;
-				if ((field & ARM_FIELD_SPSR_F) || (field & ARM_FIELD_CPSR_F))
-					printf("f");
-				if ((field & ARM_FIELD_SPSR_S) || (field & ARM_FIELD_CPSR_S))
-					printf("s");
-				if ((field & ARM_FIELD_SPSR_X) || (field & ARM_FIELD_CPSR_X))
-					printf("x");
-				if ((field & ARM_FIELD_SPSR_C) || (field & ARM_FIELD_CPSR_C))
-					printf("c");
-				printf("\n");
-				printf("\t\toperands[%u].type: MASK = %" PRIu8 "\n", i, op->sysop.msr_mask);
-				break;
-			}
-		}
-
-		if (op->neon_lane != -1) {
-			printf("\t\toperands[%u].neon_lane = %u\n", i, op->neon_lane);
-		}
-
-		switch(op->access) {
-			default:
-				break;
-			case CS_AC_READ:
-				printf("\t\toperands[%u].access: READ\n", i);
-				break;
-			case CS_AC_WRITE:
-				printf("\t\toperands[%u].access: WRITE\n", i);
-				break;
-			case CS_AC_READ | CS_AC_WRITE:
-				printf("\t\toperands[%u].access: READ | WRITE\n", i);
-				break;
-		}
-
-		if (op->shift.type != ARM_SFT_INVALID && op->shift.value) {
-			if (op->shift.type < ARM_SFT_ASR_REG)
-				// shift with constant value
-				printf("\t\t\tShift: %u = %u\n", op->shift.type, op->shift.value);
-			else
-				// shift with register
-				printf("\t\t\tShift: %u = %s\n", op->shift.type,
-						cs_reg_name(cs_handle, op->shift.value));
-		}
-
-		if (op->vector_index != -1) {
-			printf("\t\toperands[%u].vector_index = %u\n", i, op->vector_index);
-		}
-
-		if (op->subtracted)
-			printf("\t\toperands[%u].subtracted = True\n", i);
-	}
-
-	if (arm->cc != ARMCC_AL && arm->cc != ARMCC_UNDEF)
-		printf("\tCode condition: %u\n", arm->cc);
-
-	if (arm->vcc != ARMVCC_None)
-		printf("\tVector code condition: %u\n", arm->vcc);
-
-	if (arm->update_flags)
-		printf("\tUpdate-flags: True\n");
-
-	if (ins->detail->writeback) {
-		if (arm->post_index)
-			printf("\tWrite-back: Post\n");
-		else
-			printf("\tWrite-back: Pre\n");
-	}
-
-	if (arm->cps_mode)
-		printf("\tCPSI-mode: %u\n", arm->cps_mode);
-
-	if (arm->cps_flag)
-		printf("\tCPSI-flag: %u\n", arm->cps_flag);
-
-	if (arm->vector_data)
-		printf("\tVector-data: %u\n", arm->vector_data);
-
-	if (arm->vector_size)
-		printf("\tVector-size: %u\n", arm->vector_size);
-
-	if (arm->usermode)
-		printf("\tUser-mode: True\n");
-
-	if (arm->mem_barrier)
-		printf("\tMemory-barrier: %u\n", arm->mem_barrier);
-	
-	if (arm->pred_mask)
-		printf("\tPredicate Mask: 0x%x\n", arm->pred_mask);
-
-	// Print out all registers accessed by this instruction (either implicit or explicit)
-	if (!cs_regs_access(cs_handle, ins,
-				regs_read, &regs_read_count,
-				regs_write, &regs_write_count)) {
-		if (regs_read_count) {
-			printf("\tRegisters read:");
-			for(i = 0; i < regs_read_count; i++) {
-				printf(" %s", cs_reg_name(cs_handle, regs_read[i]));
-			}
-			printf("\n");
-		}
-
-		if (regs_write_count) {
-			printf("\tRegisters modified:");
-			for(i = 0; i < regs_write_count; i++) {
-				printf(" %s", cs_reg_name(cs_handle, regs_write[i]));
-			}
-			printf("\n");
-		}
-	}
-
-	printf("\n");
-}
-
-static void test()
-{
-#define ARM_CODE "\x86\x48\x60\xf4\x4d\x0f\xe2\xf4\xED\xFF\xFF\xEB\x04\xe0\x2d\xe5\x00\x00\x00\x00\xe0\x83\x22\xe5\xf1\x02\x03\x0e\x00\x00\xa0\xe3\x02\x30\xc1\xe7\x00\x00\x53\xe3\x00\x02\x01\xf1\x05\x40\xd0\xe8\xf4\x80\x00\x00"
-#define ARM_CODE2 "\xd1\xe8\x00\xf0\xf0\x24\x04\x07\x1f\x3c\xf2\xc0\x00\x00\x4f\xf0\x00\x01\x46\x6c"
-#define THUMB_CODE "\x60\xf9\x1f\x04\xe0\xf9\x4f\x07\x70\x47\x00\xf0\x10\xe8\xeb\x46\x83\xb0\xc9\x68\x1f\xb1\x30\xbf\xaf\xf3\x20\x84\x52\xf8\x23\xf0"
-#define THUMB_CODE2 "\x4f\xf0\x00\x01\xbd\xe8\x00\x88\xd1\xe8\x00\xf0\x18\xbf\xad\xbf\xf3\xff\x0b\x0c\x86\xf3\x00\x89\x80\xf3\x00\x8c\x4f\xfa\x99\xf6\xd0\xff\xa2\x01"
-#define THUMB_MCLASS "\xef\xf3\x02\x80"
-#define ARMV8 "\xe0\x3b\xb2\xee\x42\x00\x01\xe1\x51\xf0\x7f\xf5"
-
-	struct platform platforms[] = {
-		{
-			CS_ARCH_ARM,
-			CS_MODE_ARM,
-			(unsigned char *)ARM_CODE,
-			sizeof(ARM_CODE) - 1,
-			"ARM"
-		},
-		{
-			CS_ARCH_ARM,
-			CS_MODE_THUMB,
-			(unsigned char *)THUMB_CODE,
-			sizeof(THUMB_CODE) - 1,
-			"Thumb"
-		},
-		{
-			CS_ARCH_ARM,
-			CS_MODE_THUMB,
-			(unsigned char *)ARM_CODE2,
-			sizeof(ARM_CODE2) - 1,
-			"Thumb-mixed"
-		},
-		{
-			CS_ARCH_ARM,
-			CS_MODE_THUMB,
-			(unsigned char *)THUMB_CODE2,
-			sizeof(THUMB_CODE2) - 1,
-			"Thumb-2 & register named with numbers",
-			CS_OPT_SYNTAX_NOREGNAME
-		},
-		{
-			CS_ARCH_ARM,
-			(cs_mode)(CS_MODE_THUMB + CS_MODE_MCLASS),
-			(unsigned char*)THUMB_MCLASS,
-			sizeof(THUMB_MCLASS) - 1,
-			"Thumb-MClass"
-		},
-		{
-			CS_ARCH_ARM,
-			(cs_mode)(CS_MODE_ARM + CS_MODE_V8),
-			(unsigned char*)ARMV8,
-			sizeof(ARMV8) - 1,
-			"Arm-V8"
-		},
-	};
-
-	uint64_t address = 0x80001000;
-	cs_insn *insn;
-	int i;
-	size_t count;
-
-	for (i = 0; i < sizeof(platforms)/sizeof(platforms[0]); i++) {
-		cs_err err = cs_open(platforms[i].arch, platforms[i].mode, &handle);
-		if (err) {
-			printf("Failed on cs_open() with error returned: %u\n", err);
-			abort();
-		}
-
-		cs_option(handle, CS_OPT_DETAIL, CS_OPT_ON);
-
-		if (platforms[i].syntax)
-			cs_option(handle, CS_OPT_SYNTAX, platforms[i].syntax);
-
-		count = cs_disasm(handle, platforms[i].code, platforms[i].size, address, 0, &insn);
-		if (count) {
-			size_t j;
-			printf("****************\n");
-			printf("Platform: %s\n", platforms[i].comment);
-			print_string_hex("Code:", platforms[i].code, platforms[i].size);
-			printf("Disasm:\n");
-
-			for (j = 0; j < count; j++) {
-				printf("0x%" PRIx64 ":\t%s\t%s\n", insn[j].address, insn[j].mnemonic, insn[j].op_str);
-				print_insn_detail(handle, &insn[j]);
-			}
-			printf("0x%" PRIx64 ":\n", insn[j-1].address + insn[j-1].size);
-
-			// free memory allocated by cs_disasm()
-			cs_free(insn, count);
-		} else {
-			printf("****************\n");
-			printf("Platform: %s\n", platforms[i].comment);
-			print_string_hex("Code:", platforms[i].code, platforms[i].size);
-			printf("ERROR: Failed to disasm given code!\n");
-			abort();
-		}
-
-		printf("\n");
-
-		cs_close(&handle);
-	}
-}
-
-int main()
-{
-	test();
-
-	return 0;
-}
-
diff --git a/tests/test_basic.c b/tests/test_basic.c
deleted file mode 100644
index dbd37a9ff..000000000
--- a/tests/test_basic.c
+++ /dev/null
@@ -1,480 +0,0 @@
-/* Capstone Disassembler Engine */
-/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
-
-#include <stdio.h>
-#include <stdlib.h>
-
-#include <capstone/platform.h>
-#include <capstone/capstone.h>
-
-struct platform {
-	cs_arch arch;
-	cs_mode mode;
-	unsigned char *code;
-	size_t size;
-	const char *comment;
-	cs_opt_type opt_type;
-	cs_opt_value opt_value;
-};
-
-static void print_string_hex(unsigned char *str, size_t len)
-{
-	unsigned char *c;
-
-	printf("Code: ");
-	for (c = str; c < str + len; c++) {
-		printf("0x%02x ", *c & 0xff);
-	}
-	printf("\n");
-}
-
-static void test()
-{
-#ifdef CAPSTONE_HAS_X86
-#define X86_CODE16 "\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00"
-#define X86_CODE32 "\xba\xcd\xab\x00\x00\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00"
-#define X86_CODE64 "\x55\x48\x8b\x05\xb8\x13\x00\x00"
-#endif
-#ifdef CAPSTONE_HAS_ARM
-#define ARM_CODE "\xED\xFF\xFF\xEB\x04\xe0\x2d\xe5\x00\x00\x00\x00\xe0\x83\x22\xe5\xf1\x02\x03\x0e\x00\x00\xa0\xe3\x02\x30\xc1\xe7\x00\x00\x53\xe3"
-#define ARM_CODE2 "\x10\xf1\x10\xe7\x11\xf2\x31\xe7\xdc\xa1\x2e\xf3\xe8\x4e\x62\xf3"
-#define ARMV8 "\xe0\x3b\xb2\xee\x42\x00\x01\xe1\x51\xf0\x7f\xf5"
-#define THUMB_MCLASS "\xef\xf3\x02\x80"
-#define THUMB_CODE "\x70\x47\xeb\x46\x83\xb0\xc9\x68"
-#define THUMB_CODE2 "\x4f\xf0\x00\x01\xbd\xe8\x00\x88\xd1\xe8\x00\xf0"
-#endif
-#ifdef CAPSTONE_HAS_MIPS
-#define MIPS_CODE "\x0C\x10\x00\x97\x00\x00\x00\x00\x24\x02\x00\x0c\x8f\xa2\x00\x00\x34\x21\x34\x56"
-#define MIPS_CODE2 "\x56\x34\x21\x34\xc2\x17\x01\x00"
-#define MIPS_32R6M "\x00\x07\x00\x07\x00\x11\x93\x7c\x01\x8c\x8b\x7c\x00\xc7\x48\xd0"
-#define MIPS_32R6 "\xec\x80\x00\x19\x7c\x43\x22\xa0"
-#endif
-#ifdef CAPSTONE_HAS_AARCH64
-#define AARCH64_CODE "\x21\x7c\x02\x9b\x21\x7c\x00\x53\x00\x40\x21\x4b\xe1\x0b\x40\xb9"
-#endif
-#ifdef CAPSTONE_HAS_POWERPC
-#define PPC_CODE "\x80\x20\x00\x00\x80\x3f\x00\x00\x10\x43\x23\x0e\xd0\x44\x00\x80\x4c\x43\x22\x02\x2d\x03\x00\x80\x7c\x43\x20\x14\x7c\x43\x20\x93\x4f\x20\x00\x21\x4c\xc8\x00\x21"
-#define PPC_CODE2 "\x10\x60\x2a\x10\x10\x64\x28\x88\x7c\x4a\x5d\x0f"
-#endif
-#ifdef CAPSTONE_HAS_SPARC
-#define SPARC_CODE "\x80\xa0\x40\x02\x85\xc2\x60\x08\x85\xe8\x20\x01\x81\xe8\x00\x00\x90\x10\x20\x01\xd5\xf6\x10\x16\x21\x00\x00\x0a\x86\x00\x40\x02\x01\x00\x00\x00\x12\xbf\xff\xff\x10\xbf\xff\xff\xa0\x02\x00\x09\x0d\xbf\xff\xff\xd4\x20\x60\x00\xd4\x4e\x00\x16\x2a\xc2\x80\x03"
-#define SPARCV9_CODE "\x81\xa8\x0a\x24\x89\xa0\x10\x20\x89\xa0\x1a\x60\x89\xa0\x00\xe0"
-#endif
-#ifdef CAPSTONE_HAS_SYSZ
-#define SYSZ_CODE "\xed\x00\x00\x00\x00\x1a\x5a\x0f\x1f\xff\xc2\x09\x80\x00\x00\x00\x07\xf7\xeb\x2a\xff\xff\x7f\x57\xe3\x01\xff\xff\x7f\x57\xeb\x00\xf0\x00\x00\x24\xb2\x4f\x00\x78"
-#endif
-#ifdef CAPSTONE_HAS_XCORE
-#define XCORE_CODE "\xfe\x0f\xfe\x17\x13\x17\xc6\xfe\xec\x17\x97\xf8\xec\x4f\x1f\xfd\xec\x37\x07\xf2\x45\x5b\xf9\xfa\x02\x06\x1b\x10"
-#endif
-#ifdef CAPSTONE_HAS_M68K
-#define M68K_CODE "\xd4\x40\x87\x5a\x4e\x71\x02\xb4\xc0\xde\xc0\xde\x5c\x00\x1d\x80\x71\x12\x01\x23\xf2\x3c\x44\x22\x40\x49\x0e\x56\x54\xc5\xf2\x3c\x44\x00\x44\x7a\x00\x00\xf2\x00\x0a\x28\x4E\xB9\x00\x00\x00\x12\x4E\x75"
-#endif
-#ifdef CAPSTONE_HAS_TMS320C64X
-#define TMS320C64X_CODE "\x01\xac\x88\x40\x81\xac\x88\x43\x00\x00\x00\x00\x02\x90\x32\x96\x02\x80\x46\x9e\x05\x3c\x83\xe6\x0b\x0c\x8b\x24"
-#endif
-#ifdef CAPSTONE_HAS_M680X
-#define M680X_CODE "\x06\x10\x19\x1a\x55\x1e\x01\x23\xe9\x31\x06\x34\x55\xa6\x81\xa7\x89\x7f\xff\xa6\x9d\x10\x00\xa7\x91\xa6\x9f\x10\x00\x11\xac\x99\x10\x00\x39"
-#endif
-#ifdef CAPSTONE_HAS_EVM
-#define EVM_CODE "\x60\x61"
-#endif
-#ifdef CAPSTONE_HAS_WASM
-#define WASM_CODE "\x20\x00\x20\x01\x41\x20\x10\xc9\x01\x45\x0b"
-#endif
-#ifdef CAPSTONE_HAS_MOS65XX
-#define MOS65XX_CODE "\x0d\x34\x12\x00\x81\x65\x6c\x01\x00\x85\xFF\x10\x00\x19\x42\x42\x00\x49\x42"
-#endif
-#ifdef CAPSTONE_HAS_BPF
-#define EBPF_CODE "\x97\x09\x00\x00\x37\x13\x03\x00\xdc\x02\x00\x00\x20\x00\x00\x00\x30\x00\x00\x00\x00\x00\x00\x00\xdb\x3a\x00\x01\x00\x00\x00\x00\x84\x02\x00\x00\x00\x00\x00\x00\x6d\x33\x17\x02\x00\x00\x00\x00"
-#endif
-#ifdef CAPSTONE_HAS_RISCV
-#define RISCV_CODE32 "\x37\x34\x00\x00\x97\x82\x00\x00\xef\x00\x80\x00\xef\xf0\x1f\xff\xe7\x00\x45\x00\xe7\x00\xc0\xff\x63\x05\x41\x00\xe3\x9d\x61\xfe\x63\xca\x93\x00\x63\x53\xb5\x00\x63\x65\xd6\x00\x63\x76\xf7\x00\x03\x88\x18\x00\x03\x99\x49\x00\x03\xaa\x6a\x00\x03\xcb\x2b\x01\x03\xdc\x8c\x01\x23\x86\xad\x03\x23\x9a\xce\x03\x23\x8f\xef\x01\x93\x00\xe0\x00\x13\xa1\x01\x01\x13\xb2\x02\x7d\x13\xc3\x03\xdd\x13\xe4\xc4\x12\x13\xf5\x85\x0c\x13\x96\xe6\x01\x13\xd7\x97\x01\x13\xd8\xf8\x40\x33\x89\x49\x01\xb3\x0a\x7b\x41\x33\xac\xac\x01\xb3\x3d\xde\x01\x33\xd2\x62\x40\xb3\x43\x94\x00\x33\xe5\xc5\x00\xb3\x76\xf7\x00\xb3\x54\x39\x01\xb3\x50\x31\x00\x33\x9f\x0f\x00"
-#define RISCV_CODE64 "\x13\x04\xa8\x7a"  // aaa80413
-#endif
-#ifdef CAPSTONE_HAS_ALPHA
-#define ALPHA_CODE "\x02\x00\xbb\x27\x50\x7a\xbd\x23\xd0\xff\xde\x23\x00\x00\x5e\xb7"
-#define ALPHA_CODE_BE "\x27\xbb\x00\x02\x23\xbd\x7a\x50\x23\xde\xff\xd0\xb7\x5e\x00\x00"
-#endif
-#ifdef CAPSTONE_HAS_HPPA
-#define HPPA_20_CODE_BE  "\x00\x20\x50\xa2\x00\x01\x58\x20\x00\x00\x44\xa1\x00\x41\x18\x40\x00\x20\x08\xa2\x01\x60\x48\xa1\x01\x61\x18\xc0\x00\x00\x14\xa1\x00\x0f\x0d\x61\x00\x0f\x0e\x61\x00\x01\x18\x60\x00\x00\x0c\x00\x00\x00\x0c\xa0\x03\xff\xc0\x1f\x00\x00\x04\x00\x00\x10\x04\x00\x04\x22\x51\x83\x04\x22\x51\xc3\x04\x22\x51\x83\x04\x2f\x71\x83\x04\x2f\x71\xc3\x04\x2f\x71\x83\x04\x41\x53\x43\x04\x41\x53\x63\x04\x41\x53\x03\x04\x41\x12\x00\x04\x41\x16\x00\x04\x41\x16\x20\x04\x41\x42\x00\x04\x41\x46\x00\x04\x41\x46\x20\x04\x41\x12\x40\x04\x41\x12\x60\x04\x41\x42\x40\x04\x41\x42\x60\x04\x41\x18\x00\x04\x41\x08\x00\x04\x41\x13\x80\x04\x41\x13\xa0\x04\x41\x52\x80\x04\x41\x52\xa0\x04\x5e\x72\x80\x04\x41\x42\x80\x04\x41\x52\xc0\x04\x41\x52\xe0\x04\x41\x42\xc0\x04\x41\x42\xe0\x14\x00\xde\xad"
-#define HPPA_20_CODE     "\xa2\x50\x20\x00\x20\x58\x01\x00\xa1\x44\x00\x00\x40\x18\x41\x00\xa2\x08\x20\x00\xa1\x48\x60\x01\xc0\x18\x61\x01\xa1\x14\x00\x00\x61\x0d\x0f\x00\x61\x0e\x0f\x00\x60\x18\x01\x00\x00\x0c\x00\x00\xa0\x0c\x00\x00\x1f\xc0\xff\x03\x00\x04\x00\x00\x00\x04\x10\x00\x83\x51\x22\x04\xc3\x51\x22\x04\x83\x51\x22\x04\x83\x71\x2f\x04\xc3\x71\x2f\x04\x83\x71\x2f\x04\x43\x53\x41\x04\x63\x53\x41\x04\x03\x53\x41\x04\x00\x12\x41\x04\x00\x16\x41\x04\x20\x16\x41\x04\x00\x42\x41\x04\x00\x46\x41\x04\x20\x46\x41\x04\x40\x12\x41\x04\x60\x12\x41\x04\x40\x42\x41\x04\x60\x42\x41\x04\x00\x18\x41\x04\x00\x08\x41\x04\x80\x13\x41\x04\xa0\x13\x41\x04\x80\x52\x41\x04\xa0\x52\x41\x04\x80\x72\x5e\x04\x80\x42\x41\x04\xc0\x52\x41\x04\xe0\x52\x41\x04\xc0\x42\x41\x04\xe0\x42\x41\x04\xad\xde\x00\x14"
-#define HPPA_11_CODE_BE  "\x24\x41\x40\xc3\x24\x41\x60\xc3\x24\x41\x40\xe3\x24\x41\x60\xe3\x24\x41\x68\xe3\x2c\x41\x40\xc3\x2c\x41\x60\xc3\x2c\x41\x40\xe3\x2c\x41\x60\xe3\x2c\x41\x68\xe3\x24\x62\x42\xc1\x24\x62\x62\xc1\x24\x62\x42\xe1\x24\x62\x46\xe1\x24\x62\x62\xe1\x24\x62\x6a\xe1\x2c\x62\x42\xc1\x2c\x62\x62\xc1\x2c\x62\x42\xe1\x2c\x62\x46\xe1\x2c\x62\x62\xe1\x2c\x62\x6a\xe1\x24\x3e\x50\xc2\x24\x3e\x50\xe2\x24\x3e\x70\xe2\x24\x3e\x78\xe2\x2c\x3e\x50\xc2\x2c\x3e\x50\xe2\x2c\x3e\x70\xe2\x2c\x3e\x78\xe2\x24\x5e\x52\xc1\x24\x5e\x52\xe1\x24\x5e\x56\xe1\x24\x5e\x72\xe1\x24\x5e\x7a\xe1\x2c\x5e\x52\xc1\x2c\x5e\x52\xe1\x2c\x5e\x56\xe1\x2c\x5e\x72\xe1\x2c\x5e\x7a\xe1"
-#define HPPA_11_CODE     "\xc3\x40\x41\x24\xc3\x60\x41\x24\xe3\x40\x41\x24\xe3\x60\x41\x24\xe3\x68\x41\x24\xc3\x40\x41\x2c\xc3\x60\x41\x2c\xe3\x40\x41\x2c\xe3\x60\x41\x2c\xe3\x68\x41\x2c\xc1\x42\x62\x24\xc1\x62\x62\x24\xe1\x42\x62\x24\xe1\x46\x62\x24\xe1\x62\x62\x24\xe1\x6a\x62\x24\xc1\x42\x62\x2c\xc1\x62\x62\x2c\xe1\x42\x62\x2c\xe1\x46\x62\x2c\xe1\x62\x62\x2c\xe1\x6a\x62\x2c\xc2\x50\x3e\x24\xe2\x50\x3e\x24\xe2\x70\x3e\x24\xe2\x78\x3e\x24\xc2\x50\x3e\x2c\xe2\x50\x3e\x2c\xe2\x70\x3e\x2c\xe2\x78\x3e\x2c\xc1\x52\x5e\x24\xe1\x52\x5e\x24\xe1\x56\x5e\x24\xe1\x72\x5e\x24\xe1\x7a\x5e\x24\xc1\x52\x5e\x2c\xe1\x52\x5e\x2c\xe1\x56\x5e\x2c\xe1\x72\x5e\x2c\xe1\x7a\x5e\x2c"
-#endif
-
-	struct platform {
-		cs_arch arch;
-		cs_mode mode;
-		unsigned char *code;
-		size_t size;
-		const char *comment;
-		cs_opt_type opt_type;
-		cs_opt_value opt_value;
-	};
-	struct platform platforms[] = {
-#ifdef CAPSTONE_HAS_X86
-		{
-			CS_ARCH_X86,
-			CS_MODE_16,
-			(unsigned char*)X86_CODE16,
-			sizeof(X86_CODE16) - 1,
-			"X86 16bit (Intel syntax)"
-		},
-		{
-			CS_ARCH_X86,
-			CS_MODE_32,
-			(unsigned char*)X86_CODE32,
-			sizeof(X86_CODE32) - 1,
-			"X86 32bit (ATT syntax)",
-			CS_OPT_SYNTAX,
-			CS_OPT_SYNTAX_ATT,
-		},
-		{
-			CS_ARCH_X86,
-			CS_MODE_32,
-			(unsigned char*)X86_CODE32,
-			sizeof(X86_CODE32) - 1,
-			"X86 32 (Intel syntax)"
-		},
-		{
-			CS_ARCH_X86,
-			CS_MODE_32,
-			(unsigned char*)X86_CODE32,
-			sizeof(X86_CODE32) - 1,
-			"X86 32 (MASM syntax)",
-			CS_OPT_SYNTAX,
-			CS_OPT_SYNTAX_MASM,
-		},
-		{
-			CS_ARCH_X86,
-			CS_MODE_64,
-			(unsigned char*)X86_CODE64,
-			sizeof(X86_CODE64) - 1,
-			"X86 64 (Intel syntax)"
-		},
-#endif
-#ifdef CAPSTONE_HAS_ARM
-		{
-			CS_ARCH_ARM,
-			CS_MODE_ARM,
-			(unsigned char*)ARM_CODE,
-			sizeof(ARM_CODE) - 1,
-			"ARM"
-		},
-		{
-			CS_ARCH_ARM,
-			CS_MODE_THUMB,
-			(unsigned char*)THUMB_CODE2,
-			sizeof(THUMB_CODE2) - 1,
-			"THUMB-2"
-		},
-		{
-			CS_ARCH_ARM,
-			CS_MODE_ARM,
-			(unsigned char*)ARM_CODE2,
-			sizeof(ARM_CODE2) - 1,
-			"ARM: Cortex-A15 + NEON"
-		},
-		{
-			CS_ARCH_ARM,
-			CS_MODE_THUMB,
-			(unsigned char*)THUMB_CODE,
-			sizeof(THUMB_CODE) - 1,
-			"THUMB"
-		},
-		{
-			CS_ARCH_ARM,
-			(cs_mode)(CS_MODE_THUMB + CS_MODE_MCLASS),
-			(unsigned char*)THUMB_MCLASS,
-			sizeof(THUMB_MCLASS) - 1,
-			"Thumb-MClass"
-		},
-		{
-			CS_ARCH_ARM,
-			(cs_mode)(CS_MODE_ARM + CS_MODE_V8),
-			(unsigned char*)ARMV8,
-			sizeof(ARMV8) - 1,
-			"Arm-V8"
-		},
-#endif
-#ifdef CAPSTONE_HAS_MIPS
-		{
-			CS_ARCH_MIPS,
-			(cs_mode)(CS_MODE_MIPS32 + CS_MODE_BIG_ENDIAN),
-			(unsigned char*)MIPS_CODE,
-			sizeof(MIPS_CODE) - 1,
-			"MIPS-32 (Big-endian)"
-		},
-		{
-			CS_ARCH_MIPS,
-			(cs_mode)(CS_MODE_MIPS64 + CS_MODE_LITTLE_ENDIAN),
-			(unsigned char*)MIPS_CODE2,
-			sizeof(MIPS_CODE2) - 1,
-			"MIPS-64-EL (Little-endian)"
-		},
-		{
-			CS_ARCH_MIPS,
-			(cs_mode)(CS_MODE_MIPS32R6 + CS_MODE_MICRO + CS_MODE_BIG_ENDIAN),
-			(unsigned char*)MIPS_32R6M,
-			sizeof(MIPS_32R6M) - 1,
-			"MIPS-32R6 | Micro (Big-endian)"
-		},
-		{
-			CS_ARCH_MIPS,
-			(cs_mode)(CS_MODE_MIPS32R6 + CS_MODE_BIG_ENDIAN),
-			(unsigned char*)MIPS_32R6,
-			sizeof(MIPS_32R6) - 1,
-			"MIPS-32R6 (Big-endian)"
-		},
-#endif
-#ifdef CAPSTONE_HAS_AARCH64
-		{
-			CS_ARCH_AARCH64,
-			CS_MODE_ARM,
-			(unsigned char*)AARCH64_CODE,
-			sizeof(AARCH64_CODE) - 1,
-			"AARCH64"
-		},
-#endif
-#ifdef CAPSTONE_HAS_POWERPC
-		{
-			CS_ARCH_PPC,
-			CS_MODE_BIG_ENDIAN,
-			(unsigned char*)PPC_CODE,
-			sizeof(PPC_CODE) - 1,
-			"PPC-64"
-		},
-		{
-			CS_ARCH_PPC,
-			CS_MODE_BIG_ENDIAN,
-			(unsigned char*)PPC_CODE,
-			sizeof(PPC_CODE) - 1,
-			"PPC-64, print register with number only",
-			CS_OPT_SYNTAX,
-			CS_OPT_SYNTAX_NOREGNAME
-		},
-		{
-			CS_ARCH_PPC,
-			CS_MODE_BIG_ENDIAN + CS_MODE_QPX,
-			(unsigned char*)PPC_CODE2,
-			sizeof(PPC_CODE2) - 1,
-			"PPC-64 + QPX",
-		},
-#endif
-#ifdef CAPSTONE_HAS_SPARC
-		{
-			CS_ARCH_SPARC,
-			CS_MODE_BIG_ENDIAN,
-			(unsigned char*)SPARC_CODE,
-			sizeof(SPARC_CODE) - 1,
-			"Sparc"
-		},
-		{
-			CS_ARCH_SPARC,
-			(cs_mode)(CS_MODE_BIG_ENDIAN + CS_MODE_V9),
-			(unsigned char*)SPARCV9_CODE,
-			sizeof(SPARCV9_CODE) - 1,
-			"SparcV9"
-		},
-#endif
-#ifdef CAPSTONE_HAS_SYSZ
-		{
-			CS_ARCH_SYSZ,
-			(cs_mode)0,
-			(unsigned char*)SYSZ_CODE,
-			sizeof(SYSZ_CODE) - 1,
-			"SystemZ"
-		},
-#endif
-#ifdef CAPSTONE_HAS_XCORE
-		{
-			CS_ARCH_XCORE,
-			(cs_mode)0,
-			(unsigned char*)XCORE_CODE,
-			sizeof(XCORE_CODE) - 1,
-			"XCore"
-		},
-#endif
-#ifdef CAPSTONE_HAS_M68K
-		{
-			CS_ARCH_M68K,
-			(cs_mode)(CS_MODE_BIG_ENDIAN | CS_MODE_M68K_040),
-			(unsigned char*)M68K_CODE,
-			sizeof(M68K_CODE) - 1,
-			"M68K",
-		},
-#endif
-#ifdef CAPSTONE_HAS_TMS320C64X
-		{
-			CS_ARCH_TMS320C64X,
-			0,
-			(unsigned char*)TMS320C64X_CODE,
-			sizeof(TMS320C64X_CODE) - 1,
-			"TMS320C64x",
-		},
-#endif
-#ifdef CAPSTONE_HAS_M680X
-		{
-			CS_ARCH_M680X,
-			(cs_mode)(CS_MODE_M680X_6809),
-			(unsigned char*)M680X_CODE,
-			sizeof(M680X_CODE) - 1,
-			"M680X_M6809",
-		},
-#endif
-#ifdef CAPSTONE_HAS_EVM
-		{
-			CS_ARCH_EVM,
-			0,
-			(unsigned char*)EVM_CODE,
-			sizeof(EVM_CODE) - 1,
-			"EVM",
-		},
-#endif
-#ifdef CAPSTONE_HAS_WASM
-		{
-			CS_ARCH_WASM,
-			0,
-			(unsigned char*)WASM_CODE,
-			sizeof(WASM_CODE) - 1,
-			"WASM",
-		},
-#endif
-#ifdef CAPSTONE_HAS_MOS65XX
-		{
-			CS_ARCH_MOS65XX,
-			0,
-			(unsigned char *)MOS65XX_CODE,
-			sizeof(MOS65XX_CODE) - 1,
-			"MOS65XX"
-		},
-#endif
-#ifdef CAPSTONE_HAS_BPF
-		{
-			CS_ARCH_BPF,
-			CS_MODE_LITTLE_ENDIAN | CS_MODE_BPF_EXTENDED,
-			(unsigned char*) EBPF_CODE,
-			sizeof(EBPF_CODE) - 1,
-			"eBPF"
-		},
-#endif
-#ifdef CAPSTONE_HAS_RISCV
-		{
-			CS_ARCH_RISCV,
-			CS_MODE_RISCV32,
-			(unsigned char *)RISCV_CODE32,
-			sizeof(RISCV_CODE32) - 1,
-			"RISCV32"
-		},
-		{
-			CS_ARCH_RISCV,
-			CS_MODE_RISCV64,
-			(unsigned char *)RISCV_CODE64,
-			sizeof(RISCV_CODE64) - 1,
-			"RISCV64"
-		},
-#endif
-#ifdef CAPSTONE_HAS_ALPHA
-		{
-			CS_ARCH_ALPHA,
-			CS_MODE_LITTLE_ENDIAN,
-			(unsigned char*)ALPHA_CODE,
-			sizeof(ALPHA_CODE) - 1,
-			"Alpha (Little-endian)"
-		},
-		{
-			CS_ARCH_ALPHA,
-			CS_MODE_BIG_ENDIAN,
-			(unsigned char*)ALPHA_CODE_BE,
-			sizeof(ALPHA_CODE) - 1,
-			"Alpha (Big-endian)"
-		},
-#endif
-#ifdef CAPSTONE_HAS_HPPA
-	    {
-		CS_ARCH_HPPA,
-		CS_MODE_BIG_ENDIAN | CS_MODE_HPPA_20,
-		(unsigned char*)HPPA_20_CODE_BE,
-		sizeof(HPPA_20_CODE_BE) - 1,
-		"HPPA 2.0 (Big-endian)"
-	    },
-	    {
-		CS_ARCH_HPPA,
-		CS_MODE_LITTLE_ENDIAN | CS_MODE_HPPA_20,
-		(unsigned char*)HPPA_20_CODE,
-		sizeof(HPPA_20_CODE) - 1,
-		"HPPA 2.0 (Little-endian)"
-	    },
-	    {
-		CS_ARCH_HPPA,
-		CS_MODE_BIG_ENDIAN | CS_MODE_HPPA_11,
-		(unsigned char*)HPPA_11_CODE_BE,
-		sizeof(HPPA_11_CODE_BE) - 1,
-		"HPPA 1.1 (Big-endian)"
-	    },
-	    {
-		CS_ARCH_HPPA,
-		CS_MODE_LITTLE_ENDIAN | CS_MODE_HPPA_11,
-		(unsigned char*)HPPA_11_CODE,
-		sizeof(HPPA_11_CODE) - 1,
-		"HPPA 1.1 (Little-endian)"
-	    },
-#endif
-	};
-
-	csh handle;
-	uint64_t address = 0x1000;
-	cs_insn *insn;
-	int i;
-	size_t count;
-	cs_err err;
-
-	for (i = 0; i < sizeof(platforms)/sizeof(platforms[0]); i++) {
-		printf("****************\n");
-		printf("Platform: %s\n", platforms[i].comment);
-		err = cs_open(platforms[i].arch, platforms[i].mode, &handle);
-		if (err) {
-			printf("Failed on cs_open() with error returned: %u\n", err);
-			abort();
-		}
-
-		if (platforms[i].opt_type)
-			cs_option(handle, platforms[i].opt_type, platforms[i].opt_value);
-
-		count = cs_disasm(handle, platforms[i].code, platforms[i].size, address, 0, &insn);
-		if (count) {
-			size_t j;
-
-			print_string_hex(platforms[i].code, platforms[i].size);
-			printf("Disasm:\n");
-
-			for (j = 0; j < count; j++) {
-				printf("0x%" PRIx64 ":\t%s\t\t%s\n",
-						insn[j].address, insn[j].mnemonic, insn[j].op_str);
-			}
-
-			// print out the next offset, after the last insn
-			printf("0x%" PRIx64 ":\n", insn[j-1].address + insn[j-1].size);
-
-			// free memory allocated by cs_disasm()
-			cs_free(insn, count);
-		} else {
-			printf("****************\n");
-			printf("Platform: %s\n", platforms[i].comment);
-			print_string_hex(platforms[i].code, platforms[i].size);
-			printf("ERROR: Failed to disasm given code!\n");
-			abort();
-		}
-
-		printf("\n");
-
-		cs_close(&handle);
-	}
-}
-
-int main()
-{
-	test();
-
-	return 0;
-}
diff --git a/tests/test_bpf.c b/tests/test_bpf.c
deleted file mode 100644
index b97e330cb..000000000
--- a/tests/test_bpf.c
+++ /dev/null
@@ -1,187 +0,0 @@
-/* Capstone Disassembly Engine */
-/* By david942j <david942j@gmail.com>, 2019 */
-
-#include <capstone/capstone.h>
-#include <capstone/platform.h>
-
-static csh handle;
-
-struct platform {
-	cs_arch arch;
-	cs_mode mode;
-	const unsigned char *code;
-	size_t size;
-	const char *comment;
-};
-
-static void print_string_hex(const char *comment, const unsigned char *str, size_t len)
-{
-	const unsigned char *c;
-
-	printf("%s", comment);
-	for (c = str; c < str + len; c++) {
-		printf(" 0x%02x", *c & 0xff);
-	}
-
-	printf("\n");
-}
-
-static const char * ext_name[] = {
-	[BPF_EXT_LEN] = "#len",
-};
-
-static void print_insn_detail(csh cs_handle, cs_insn *ins)
-{
-	cs_bpf *bpf;
-	cs_regs regs_read, regs_write;
-	uint8_t regs_read_count, regs_write_count;
-	unsigned i;
-
-	// detail can be NULL on "data" instruction if SKIPDATA option is turned ON
-	if (ins->detail == NULL)
-		return;
-
-	if (ins->detail->groups_count) {
-		int j;
-
-		printf("\tGroups:");
-		for(j = 0; j < ins->detail->groups_count; j++)
-			printf(" %s", cs_group_name(handle, ins->detail->groups[j]));
-		printf("\n");
-	}
-
-	bpf = &(ins->detail->bpf);
-
-	printf("\tOperand count: %u\n", bpf->op_count);
-	for (i = 0; i < bpf->op_count; i++) {
-		cs_bpf_op *op = &(bpf->operands[i]);
-		printf("\t\toperands[%u].type: ", i);
-		switch (op->type) {
-		case BPF_OP_INVALID:
-			printf("INVALID\n");
-			break;
-		case BPF_OP_REG:
-			printf("REG = %s\n", cs_reg_name(handle, op->reg));
-			break;
-		case BPF_OP_IMM:
-			printf("IMM = 0x%" PRIx64 "\n", op->imm);
-			break;
-		case BPF_OP_OFF:
-			printf("OFF = +0x%x\n", op->off);
-			break;
-		case BPF_OP_MEM:
-			printf("MEM\n");
-			if (op->mem.base != BPF_REG_INVALID)
-				printf("\t\t\toperands[%u].mem.base: REG = %s\n",
-						i, cs_reg_name(handle, op->mem.base));
-			printf("\t\t\toperands[%u].mem.disp: 0x%x\n", i, op->mem.disp);
-			break;
-		case BPF_OP_MMEM:
-			printf("MMEM = M[0x%x]\n", op->mmem);
-			break;
-		case BPF_OP_MSH:
-			printf("MSH = 4*([0x%x]&0xf)\n", op->msh);
-			break;
-		case BPF_OP_EXT:
-			printf("EXT = %s\n", ext_name[op->ext]);
-			break;
-		}
-	}
-
-	/* print all registers that are involved in this instruction */
-	if (!cs_regs_access(cs_handle, ins,
-			regs_read, &regs_read_count,
-			regs_write, &regs_write_count)) {
-		if (regs_read_count) {
-			printf("\tRegisters read:");
-			for(i = 0; i < regs_read_count; i++)
-				printf(" %s", cs_reg_name(cs_handle, regs_read[i]));
-			printf("\n");
-		}
-
-		if (regs_write_count) {
-			printf("\tRegisters modified:");
-			for(i = 0; i < regs_write_count; i++)
-				printf(" %s", cs_reg_name(cs_handle, regs_write[i]));
-			printf("\n");
-		}
-	}
-	puts("");
-}
-
-static void test()
-{
-#define CBPF_CODE	"\x94\x09\x00\x00\x37\x13\x03\x00" \
-			"\x87\x00\x00\x00\x00\x00\x00\x00" \
-			"\x07\x00\x00\x00\x00\x00\x00\x00" \
-			"\x16\x00\x00\x00\x00\x00\x00\x00" \
-			"\x80\x00\x00\x00\x00\x00\x00\x00"
-
-#define EBPF_CODE	"\x97\x09\x00\x00\x37\x13\x03\x00" \
-			"\xdc\x02\x00\x00\x20\x00\x00\x00" \
-			"\x30\x00\x00\x00\x00\x00\x00\x00" \
-			"\xdb\x3a\x00\x01\x00\x00\x00\x00" \
-			"\x84\x02\x00\x00\x00\x00\x00\x00" \
-			"\x6d\x33\x17\x02\x00\x00\x00\x00"
-	struct platform platforms[] = {
-		{
-			CS_ARCH_BPF,
-			CS_MODE_LITTLE_ENDIAN | CS_MODE_BPF_CLASSIC,
-			(unsigned char *)CBPF_CODE,
-			sizeof(CBPF_CODE) - 1,
-			"cBPF Le"
-		},
-		{
-			CS_ARCH_BPF,
-			CS_MODE_LITTLE_ENDIAN | CS_MODE_BPF_EXTENDED,
-			(unsigned char *)EBPF_CODE,
-			sizeof(EBPF_CODE) - 1,
-			"eBPF Le"
-		},
-	};
-	uint64_t address = 0x0;
-	cs_insn *insn;
-	int i;
-	size_t count;
-
-	for (i = 0; i < sizeof(platforms)/sizeof(platforms[0]); i++) {
-		cs_err err = cs_open(platforms[i].arch, platforms[i].mode, &handle);
-		if (err) {
-			printf("Failed on cs_open() with error returned: %u\n", err);
-			abort();
-		}
-
-		cs_option(handle, CS_OPT_DETAIL, CS_OPT_ON);
-
-		count = cs_disasm(handle, platforms[i].code, platforms[i].size, address, 0, &insn);
-		if (count) {
-			size_t j;
-			printf("****************\n");
-			printf("Platform: %s\n", platforms[i].comment);
-			print_string_hex("Code:", platforms[i].code, platforms[i].size);
-			printf("Disasm:\n");
-
-			for (j = 0; j < count; j++) {
-				printf("0x%" PRIx64 ":\t%s\t%s\n", insn[j].address, insn[j].mnemonic, insn[j].op_str);
-				print_insn_detail(handle, &insn[j]);
-			}
-
-			// free memory allocated by cs_disasm()
-			cs_free(insn, count);
-		} else {
-			printf("****************\n");
-			printf("Platform: %s\n", platforms[i].comment);
-			print_string_hex("Code:", platforms[i].code, platforms[i].size);
-			printf("ERROR: Failed to disasm given code!\n");
-			abort();
-		}
-
-		cs_close(&handle);
-	}
-}
-
-int main()
-{
-	test();
-	return 0;
-}
diff --git a/tests/test_detail.c b/tests/test_detail.c
deleted file mode 100644
index ab8de7e1f..000000000
--- a/tests/test_detail.c
+++ /dev/null
@@ -1,432 +0,0 @@
-/* Capstone Disassembler Engine */
-/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
-
-#include <stdio.h>
-#include <stdlib.h>
-
-#include <capstone/platform.h>
-#include <capstone/capstone.h>
-
-struct platform {
-	cs_arch arch;
-	cs_mode mode;
-	unsigned char *code;
-	size_t size;
-	const char *comment;
-	cs_opt_type opt_type;
-	cs_opt_value opt_value;
-};
-
-static void print_string_hex(unsigned char *str, size_t len)
-{
-	unsigned char *c;
-
-	printf("Code: ");
-	for (c = str; c < str + len; c++) {
-		printf("0x%02x ", *c & 0xff);
-	}
-	printf("\n");
-}
-
-static void test()
-{
-#ifdef CAPSTONE_HAS_X86
-#define X86_CODE16 "\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00"
-#define X86_CODE32 "\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00"
-#define X86_CODE64 "\x55\x48\x8b\x05\xb8\x13\x00\x00"
-#endif
-#ifdef CAPSTONE_HAS_ARM
-#define ARM_CODE "\xED\xFF\xFF\xEB\x04\xe0\x2d\xe5\x00\x00\x00\x00\xe0\x83\x22\xe5\xf1\x02\x03\x0e\x00\x00\xa0\xe3\x02\x30\xc1\xe7\x00\x00\x53\xe3"
-#define ARM_CODE2 "\x10\xf1\x10\xe7\x11\xf2\x31\xe7\xdc\xa1\x2e\xf3\xe8\x4e\x62\xf3"
-#define THUMB_CODE "\x70\x47\xeb\x46\x83\xb0\xc9\x68"
-#define THUMB_CODE2 "\x4f\xf0\x00\x01\xbd\xe8\x00\x88\xd1\xe8\x00\xf0"
-#define THUMB_MCLASS "\xef\xf3\x02\x80"
-#define ARMV8 "\xe0\x3b\xb2\xee\x42\x00\x01\xe1\x51\xf0\x7f\xf5"
-#endif
-#ifdef CAPSTONE_HAS_MIPS
-#define MIPS_CODE "\x0C\x10\x00\x97\x00\x00\x00\x00\x24\x02\x00\x0c\x8f\xa2\x00\x00\x34\x21\x34\x56\x00\x80\x04\x08"
-#define MIPS_CODE2 "\x56\x34\x21\x34\xc2\x17\x01\x00"
-#define MIPS_32R6M "\x00\x07\x00\x07\x00\x11\x93\x7c\x01\x8c\x8b\x7c\x00\xc7\x48\xd0"
-#define MIPS_32R6 "\xec\x80\x00\x19\x7c\x43\x22\xa0"
-#endif
-#ifdef CAPSTONE_HAS_AARCH64
-#define AARCH64_CODE "\x09\x00\x38\xd5\xbf\x40\x00\xd5\x0c\x05\x13\xd5\x20\x50\x02\x0e\x20\xe4\x3d\x0f\x00\x18\xa0\x5f\xa2\x00\xae\x9e\x9f\x37\x03\xd5\xbf\x33\x03\xd5\xdf\x3f\x03\xd5\x21\x7c\x02\x9b\x21\x7c\x00\x53\x00\x40\x21\x4b\xe1\x0b\x40\xb9\x20\x04\x81\xda\x20\x08\x02\x8b\x10\x5b\xe8\x3c"
-#endif
-#ifdef CAPSTONE_HAS_POWERPC
-#define PPC_CODE "\x80\x20\x00\x00\x80\x3f\x00\x00\x10\x43\x23\x0e\xd0\x44\x00\x80\x4c\x43\x22\x02\x2d\x03\x00\x80\x7c\x43\x20\x14\x7c\x43\x20\x93\x4f\x20\x00\x21\x4c\xc8\x00\x21\x40\x82\x00\x14"
-#define PPC_CODE2 "\x10\x60\x2a\x10\x10\x64\x28\x88\x7c\x4a\x5d\x0f"
-#endif
-#ifdef CAPSTONE_HAS_SPARC
-#define SPARC_CODE "\x80\xa0\x40\x02\x85\xc2\x60\x08\x85\xe8\x20\x01\x81\xe8\x00\x00\x90\x10\x20\x01\xd5\xf6\x10\x16\x21\x00\x00\x0a\x86\x00\x40\x02\x01\x00\x00\x00\x12\xbf\xff\xff\x10\xbf\xff\xff\xa0\x02\x00\x09\x0d\xbf\xff\xff\xd4\x20\x60\x00\xd4\x4e\x00\x16\x2a\xc2\x80\x03"
-#define SPARCV9_CODE "\x81\xa8\x0a\x24\x89\xa0\x10\x20\x89\xa0\x1a\x60\x89\xa0\x00\xe0"
-#endif
-#ifdef CAPSTONE_HAS_SYSZ
-#define SYSZ_CODE "\xed\x00\x00\x00\x00\x1a\x5a\x0f\x1f\xff\xc2\x09\x80\x00\x00\x00\x07\xf7\xeb\x2a\xff\xff\x7f\x57\xe3\x01\xff\xff\x7f\x57\xeb\x00\xf0\x00\x00\x24\xb2\x4f\x00\x78"
-#endif
-#ifdef CAPSTONE_HAS_XCORE
-#define XCORE_CODE "\xfe\x0f\xfe\x17\x13\x17\xc6\xfe\xec\x17\x97\xf8\xec\x4f\x1f\xfd\xec\x37\x07\xf2\x45\x5b\xf9\xfa\x02\x06\x1b\x10"
-#endif
-#ifdef CAPSTONE_HAS_M68K
-#define M68K_CODE "\xd4\x40\x87\x5a\x4e\x71\x02\xb4\xc0\xde\xc0\xde\x5c\x00\x1d\x80\x71\x12\x01\x23\xf2\x3c\x44\x22\x40\x49\x0e\x56\x54\xc5\xf2\x3c\x44\x00\x44\x7a\x00\x00\xf2\x00\x0a\x28\x4E\xB9\x00\x00\x00\x12\x4E\x75"
-#endif
-#ifdef CAPSTONE_HAS_M680X
-#define M680X_CODE "\x06\x10\x19\x1a\x55\x1e\x01\x23\xe9\x31\x06\x34\x55\xa6\x81\xa7\x89\x7f\xff\xa6\x9d\x10\x00\xa7\x91\xa6\x9f\x10\x00\x11\xac\x99\x10\x00\x39"
-#endif
-#ifdef CAPSTONE_HAS_MOS65XX
-#define MOS65XX_CODE "\x0A\x00\xFE\x34\x12\xD0\xFF\xEA\x19\x56\x34\x46\x80"
-#endif
-#ifdef CAPSTONE_HAS_BPF
-#define EBPF_CODE "\x97\x09\x00\x00\x37\x13\x03\x00\xdc\x02\x00\x00\x20\x00\x00\x00\x30\x00\x00\x00\x00\x00\x00\x00\xdb\x3a\x00\x01\x00\x00\x00\x00\x84\x02\x00\x00\x00\x00\x00\x00\x6d\x33\x17\x02\x00\x00\x00\x00"
-#endif
-#ifdef CAPSTONE_HAS_ALPHA
-#define ALPHA_CODE "\x02\x00\xbb\x27\x50\x7a\xbd\x23\xd0\xff\xde\x23\x00\x00\x5e\xb7"
-#define ALPHA_CODE_BE "\x27\xbb\x00\x02\x23\xbd\x7a\x50\x23\xde\xff\xd0\xb7\x5e\x00\x00"
-#endif
-#ifdef CAPSTONE_HAS_HPPA
-#define HPPA_20_CODE_BE  "\x00\x20\x50\xa2\x00\x01\x58\x20\x00\x00\x44\xa1\x00\x41\x18\x40\x00\x20\x08\xa2\x01\x60\x48\xa1\x01\x61\x18\xc0\x00\x00\x14\xa1\x00\x0f\x0d\x61\x00\x0f\x0e\x61\x00\x01\x18\x60\x00\x00\x0c\x00\x00\x00\x0c\xa0\x03\xff\xc0\x1f\x00\x00\x04\x00\x00\x10\x04\x00\x04\x22\x51\x83\x04\x22\x51\xc3\x04\x22\x51\x83\x04\x2f\x71\x83\x04\x2f\x71\xc3\x04\x2f\x71\x83\x04\x41\x53\x43\x04\x41\x53\x63\x04\x41\x53\x03\x04\x41\x12\x00\x04\x41\x16\x00\x04\x41\x16\x20\x04\x41\x42\x00\x04\x41\x46\x00\x04\x41\x46\x20\x04\x41\x12\x40\x04\x41\x12\x60\x04\x41\x42\x40\x04\x41\x42\x60\x04\x41\x18\x00\x04\x41\x08\x00\x04\x41\x13\x80\x04\x41\x13\xa0\x04\x41\x52\x80\x04\x41\x52\xa0\x04\x5e\x72\x80\x04\x41\x42\x80\x04\x41\x52\xc0\x04\x41\x52\xe0\x04\x41\x42\xc0\x04\x41\x42\xe0\x14\x00\xde\xad"
-#define HPPA_20_CODE     "\xa2\x50\x20\x00\x20\x58\x01\x00\xa1\x44\x00\x00\x40\x18\x41\x00\xa2\x08\x20\x00\xa1\x48\x60\x01\xc0\x18\x61\x01\xa1\x14\x00\x00\x61\x0d\x0f\x00\x61\x0e\x0f\x00\x60\x18\x01\x00\x00\x0c\x00\x00\xa0\x0c\x00\x00\x1f\xc0\xff\x03\x00\x04\x00\x00\x00\x04\x10\x00\x83\x51\x22\x04\xc3\x51\x22\x04\x83\x51\x22\x04\x83\x71\x2f\x04\xc3\x71\x2f\x04\x83\x71\x2f\x04\x43\x53\x41\x04\x63\x53\x41\x04\x03\x53\x41\x04\x00\x12\x41\x04\x00\x16\x41\x04\x20\x16\x41\x04\x00\x42\x41\x04\x00\x46\x41\x04\x20\x46\x41\x04\x40\x12\x41\x04\x60\x12\x41\x04\x40\x42\x41\x04\x60\x42\x41\x04\x00\x18\x41\x04\x00\x08\x41\x04\x80\x13\x41\x04\xa0\x13\x41\x04\x80\x52\x41\x04\xa0\x52\x41\x04\x80\x72\x5e\x04\x80\x42\x41\x04\xc0\x52\x41\x04\xe0\x52\x41\x04\xc0\x42\x41\x04\xe0\x42\x41\x04\xad\xde\x00\x14"
-#define HPPA_11_CODE_BE  "\x24\x41\x40\xc3\x24\x41\x60\xc3\x24\x41\x40\xe3\x24\x41\x60\xe3\x24\x41\x68\xe3\x2c\x41\x40\xc3\x2c\x41\x60\xc3\x2c\x41\x40\xe3\x2c\x41\x60\xe3\x2c\x41\x68\xe3\x24\x62\x42\xc1\x24\x62\x62\xc1\x24\x62\x42\xe1\x24\x62\x46\xe1\x24\x62\x62\xe1\x24\x62\x6a\xe1\x2c\x62\x42\xc1\x2c\x62\x62\xc1\x2c\x62\x42\xe1\x2c\x62\x46\xe1\x2c\x62\x62\xe1\x2c\x62\x6a\xe1\x24\x3e\x50\xc2\x24\x3e\x50\xe2\x24\x3e\x70\xe2\x24\x3e\x78\xe2\x2c\x3e\x50\xc2\x2c\x3e\x50\xe2\x2c\x3e\x70\xe2\x2c\x3e\x78\xe2\x24\x5e\x52\xc1\x24\x5e\x52\xe1\x24\x5e\x56\xe1\x24\x5e\x72\xe1\x24\x5e\x7a\xe1\x2c\x5e\x52\xc1\x2c\x5e\x52\xe1\x2c\x5e\x56\xe1\x2c\x5e\x72\xe1\x2c\x5e\x7a\xe1"
-#define HPPA_11_CODE     "\xc3\x40\x41\x24\xc3\x60\x41\x24\xe3\x40\x41\x24\xe3\x60\x41\x24\xe3\x68\x41\x24\xc3\x40\x41\x2c\xc3\x60\x41\x2c\xe3\x40\x41\x2c\xe3\x60\x41\x2c\xe3\x68\x41\x2c\xc1\x42\x62\x24\xc1\x62\x62\x24\xe1\x42\x62\x24\xe1\x46\x62\x24\xe1\x62\x62\x24\xe1\x6a\x62\x24\xc1\x42\x62\x2c\xc1\x62\x62\x2c\xe1\x42\x62\x2c\xe1\x46\x62\x2c\xe1\x62\x62\x2c\xe1\x6a\x62\x2c\xc2\x50\x3e\x24\xe2\x50\x3e\x24\xe2\x70\x3e\x24\xe2\x78\x3e\x24\xc2\x50\x3e\x2c\xe2\x50\x3e\x2c\xe2\x70\x3e\x2c\xe2\x78\x3e\x2c\xc1\x52\x5e\x24\xe1\x52\x5e\x24\xe1\x56\x5e\x24\xe1\x72\x5e\x24\xe1\x7a\x5e\x24\xc1\x52\x5e\x2c\xe1\x52\x5e\x2c\xe1\x56\x5e\x2c\xe1\x72\x5e\x2c\xe1\x7a\x5e\x2c"
-#endif
-
-	struct platform platforms[] = {
-#ifdef CAPSTONE_HAS_X86
-		{
-			CS_ARCH_X86,
-			CS_MODE_16,
-			(unsigned char *)X86_CODE16,
-			sizeof(X86_CODE16) - 1,
-			"X86 16bit (Intel syntax)"
-		},
-		{
-			CS_ARCH_X86,
-			CS_MODE_32,
-			(unsigned char *)X86_CODE32,
-			sizeof(X86_CODE32) - 1,
-			"X86 32bit (ATT syntax)",
-			CS_OPT_SYNTAX,
-			CS_OPT_SYNTAX_ATT,
-		},
-		{
-			CS_ARCH_X86,
-			CS_MODE_32,
-			(unsigned char *)X86_CODE32,
-			sizeof(X86_CODE32) - 1,
-			"X86 32 (Intel syntax)"
-		},
-		{
-			CS_ARCH_X86,
-			CS_MODE_64,
-			(unsigned char *)X86_CODE64,
-			sizeof(X86_CODE64) - 1,
-			"X86 64 (Intel syntax)"
-		},
-#endif
-#ifdef CAPSTONE_HAS_ARM
-		{
-			CS_ARCH_ARM,
-			CS_MODE_ARM,
-			(unsigned char *)ARM_CODE,
-			sizeof(ARM_CODE) - 1,
-			"ARM"
-		},
-		{
-			CS_ARCH_ARM,
-			CS_MODE_ARM,
-			(unsigned char *)ARM_CODE2,
-			sizeof(ARM_CODE2) - 1,
-			"ARM: Cortex-A15 + NEON"
-		},
-		{
-			CS_ARCH_ARM,
-			CS_MODE_THUMB,
-			(unsigned char *)THUMB_CODE,
-			sizeof(THUMB_CODE) - 1,
-			"THUMB"
-		},
-		{
-			CS_ARCH_ARM,
-			CS_MODE_THUMB,
-			(unsigned char *)THUMB_CODE2,
-			sizeof(THUMB_CODE2) - 1,
-			"THUMB-2"
-		},
-		{
-			CS_ARCH_ARM,
-			(cs_mode)(CS_MODE_THUMB + CS_MODE_MCLASS),
-			(unsigned char*)THUMB_MCLASS,
-			sizeof(THUMB_MCLASS) - 1,
-			"Thumb-MClass"
-		},
-		{
-			CS_ARCH_ARM,
-			(cs_mode)(CS_MODE_ARM + CS_MODE_V8),
-			(unsigned char*)ARMV8,
-			sizeof(ARMV8) - 1,
-			"Arm-V8"
-		},
-#endif
-#ifdef CAPSTONE_HAS_AARCH64
-		{
-			CS_ARCH_AARCH64,
-			CS_MODE_ARM,
-			(unsigned char *)AARCH64_CODE,
-			sizeof(AARCH64_CODE) - 1,
-			"AARCH64"
-		},
-#endif
-#ifdef CAPSTONE_HAS_MIPS
-		{
-			CS_ARCH_MIPS,
-			(cs_mode)(CS_MODE_MIPS32 + CS_MODE_BIG_ENDIAN),
-			(unsigned char *)MIPS_CODE,
-			sizeof(MIPS_CODE) - 1,
-			"MIPS-32 (Big-endian)"
-		},
-		{
-			CS_ARCH_MIPS,
-			(cs_mode)(CS_MODE_MIPS64 + CS_MODE_LITTLE_ENDIAN),
-			(unsigned char *)MIPS_CODE2,
-			sizeof(MIPS_CODE2) - 1,
-			"MIPS-64-EL (Little-endian)"
-		},
-		{
-			CS_ARCH_MIPS,
-			(cs_mode)(CS_MODE_MIPS32R6 + CS_MODE_MICRO + CS_MODE_BIG_ENDIAN),
-			(unsigned char*)MIPS_32R6M,
-			sizeof(MIPS_32R6M) - 1,
-			"MIPS-32R6 | Micro (Big-endian)"
-		},
-		{
-			CS_ARCH_MIPS,
-			(cs_mode)(CS_MODE_MIPS32R6 + CS_MODE_BIG_ENDIAN),
-			(unsigned char*)MIPS_32R6,
-			sizeof(MIPS_32R6) - 1,
-			"MIPS-32R6 (Big-endian)"
-		},
-#endif
-#ifdef CAPSTONE_HAS_POWERPC
-		{
-			CS_ARCH_PPC,
-			CS_MODE_BIG_ENDIAN,
-			(unsigned char*)PPC_CODE,
-			sizeof(PPC_CODE) - 1,
-			"PPC-64"
-		},
-		{
-			CS_ARCH_PPC,
-			CS_MODE_BIG_ENDIAN + CS_MODE_QPX,
-			(unsigned char*)PPC_CODE2,
-			sizeof(PPC_CODE2) - 1,
-			"PPC-64 + QPX",
-		},
-#endif
-#ifdef CAPSTONE_HAS_SPARC
-		{
-			CS_ARCH_SPARC,
-			CS_MODE_BIG_ENDIAN,
-			(unsigned char*)SPARC_CODE,
-			sizeof(SPARC_CODE) - 1,
-			"Sparc"
-		},
-		{
-			CS_ARCH_SPARC,
-			(cs_mode)(CS_MODE_BIG_ENDIAN + CS_MODE_V9),
-			(unsigned char*)SPARCV9_CODE,
-			sizeof(SPARCV9_CODE) - 1,
-			"SparcV9"
-		},
-#endif
-#ifdef CAPSTONE_HAS_SYSZ
-		{
-			CS_ARCH_SYSZ,
-			(cs_mode)0,
-			(unsigned char*)SYSZ_CODE,
-			sizeof(SYSZ_CODE) - 1,
-			"SystemZ"
-		},
-#endif
-#ifdef CAPSTONE_HAS_XCORE
-		{
-			CS_ARCH_XCORE,
-			(cs_mode)0,
-			(unsigned char*)XCORE_CODE,
-			sizeof(XCORE_CODE) - 1,
-			"XCore"
-		},
-#endif
-#ifdef CAPSTONE_HAS_M68K
-		{
-			CS_ARCH_M68K,
-			(cs_mode)(CS_MODE_BIG_ENDIAN | CS_MODE_M68K_040),
-			(unsigned char*)M68K_CODE,
-			sizeof(M68K_CODE) - 1,
-			"M68K",
-		},
-#endif
-#ifdef CAPSTONE_HAS_M680X
-		{
-			CS_ARCH_M680X,
-			(cs_mode)(CS_MODE_M680X_6809),
-			(unsigned char*)M680X_CODE,
-			sizeof(M680X_CODE) - 1,
-			"M680X_M6809",
-		},
-#endif
-#ifdef CAPSTONE_HAS_MOS65XX
-		{
-				CS_ARCH_MOS65XX,
-				(cs_mode)0,
-				(unsigned char*)MOS65XX_CODE,
-				sizeof(MOS65XX_CODE) - 1,
-				"MOS65XX",
-		},
-#endif
-#ifdef CAPSTONE_HAS_BPF
-		{
-			CS_ARCH_BPF,
-			CS_MODE_LITTLE_ENDIAN | CS_MODE_BPF_EXTENDED,
-			(unsigned char*) EBPF_CODE,
-			sizeof(EBPF_CODE) - 1,
-			"eBPF"
-		},
-#endif
-#ifdef CAPSTONE_HAS_ALPHA
-		{
-			CS_ARCH_ALPHA,
-			CS_MODE_LITTLE_ENDIAN,
-			(unsigned char*)ALPHA_CODE,
-			sizeof(ALPHA_CODE) - 1,
-			"Alpha (Little-endian)"
-		},
-		{
-			CS_ARCH_ALPHA,
-			CS_MODE_BIG_ENDIAN,
-			(unsigned char*)ALPHA_CODE_BE,
-			sizeof(ALPHA_CODE) - 1,
-			"Alpha (Big-endian)"
-		},
-#endif
-#ifdef CAPSTONE_HAS_HPPA
-	    {
-		CS_ARCH_HPPA,
-		CS_MODE_BIG_ENDIAN | CS_MODE_HPPA_20,
-		(unsigned char*)HPPA_20_CODE_BE,
-		sizeof(HPPA_20_CODE_BE) - 1,
-		"HPPA 2.0 (Big-endian)"
-	    },
-	    {
-		CS_ARCH_HPPA,
-		CS_MODE_LITTLE_ENDIAN | CS_MODE_HPPA_20,
-		(unsigned char*)HPPA_20_CODE,
-		sizeof(HPPA_20_CODE) - 1,
-		"HPPA 2.0 (Little-endian)"
-	    },
-	    {
-		CS_ARCH_HPPA,
-		CS_MODE_BIG_ENDIAN | CS_MODE_HPPA_11,
-		(unsigned char*)HPPA_11_CODE_BE,
-		sizeof(HPPA_11_CODE_BE) - 1,
-		"HPPA 1.1 (Big-endian)"
-	    },
-	    {
-		CS_ARCH_HPPA,
-		CS_MODE_LITTLE_ENDIAN | CS_MODE_HPPA_11,
-		(unsigned char*)HPPA_11_CODE,
-		sizeof(HPPA_11_CODE) - 1,
-		"HPPA 1.1 (Little-endian)"
-	    },
-#endif
-	};
-
-	csh handle;
-	uint64_t address = 0x1000;
-	cs_insn *all_insn;
-	cs_detail *detail;
-	int i;
-	size_t count;
-	cs_err err;
-
-	for (i = 0; i < sizeof(platforms)/sizeof(platforms[0]); i++) {
-		printf("****************\n");
-		printf("Platform: %s\n", platforms[i].comment);
-		err = cs_open(platforms[i].arch, platforms[i].mode, &handle);
-		if (err) {
-			printf("Failed on cs_open() with error returned: %u\n", err);
-			abort();
-		}
-
-		if (platforms[i].opt_type)
-			cs_option(handle, platforms[i].opt_type, platforms[i].opt_value);
-
-		cs_option(handle, CS_OPT_DETAIL, CS_OPT_ON);
-
-		count = cs_disasm(handle, platforms[i].code, platforms[i].size, address, 0, &all_insn);
-		if (count) {
-			size_t j;
-			int n;
-
-			print_string_hex(platforms[i].code, platforms[i].size);
-			printf("Disasm:\n");
-
-			for (j = 0; j < count; j++) {
-				cs_insn *in = &(all_insn[j]);
-				printf("0x%" PRIx64 ":\t%s\t\t%s // insn-ID: %u, insn-mnem: %s\n",
-						in->address, in->mnemonic, in->op_str,
-						in->id, cs_insn_name(handle, in->id));
-
-				// print implicit registers used by this instruction
-				detail = in->detail;
-
-				if (detail->regs_read_count > 0) {
-					printf("\tImplicit registers read: ");
-					for (n = 0; n < detail->regs_read_count; n++) {
-						printf("%s ", cs_reg_name(handle, detail->regs_read[n]));
-					}
-					printf("\n");
-				}
-
-				// print implicit registers modified by this instruction
-				if (detail->regs_write_count > 0) {
-					printf("\tImplicit registers modified: ");
-					for (n = 0; n < detail->regs_write_count; n++) {
-						printf("%s ", cs_reg_name(handle, detail->regs_write[n]));
-					}
-					printf("\n");
-				}
-
-				// print the groups this instruction belong to
-				if (detail->groups_count > 0) {
-					printf("\tThis instruction belongs to groups: ");
-					for (n = 0; n < detail->groups_count; n++) {
-						printf("%s ", cs_group_name(handle, detail->groups[n]));
-					}
-					printf("\n");
-				}
-			}
-
-			// print out the next offset, after the last insn
-			printf("0x%" PRIx64 ":\n", all_insn[j-1].address + all_insn[j-1].size);
-
-			// free memory allocated by cs_disasm()
-			cs_free(all_insn, count);
-		} else {
-			printf("****************\n");
-			printf("Platform: %s\n", platforms[i].comment);
-			print_string_hex(platforms[i].code, platforms[i].size);
-			printf("ERROR: Failed to disasm given code!\n");
-			abort();
-		}
-
-		printf("\n");
-
-		cs_close(&handle);
-	}
-}
-
-int main()
-{
-	test();
-
-	return 0;
-}
diff --git a/tests/test_evm.c b/tests/test_evm.c
deleted file mode 100644
index 7fd0aa30f..000000000
--- a/tests/test_evm.c
+++ /dev/null
@@ -1,126 +0,0 @@
-/* Capstone Disassembler Engine */
-/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2018-2019 */
-
-#include <stdio.h>
-#include <stdlib.h>
-
-#include <capstone/platform.h>
-#include <capstone/capstone.h>
-
-static csh handle;
-
-struct platform {
-	cs_arch arch;
-	cs_mode mode;
-	unsigned char *code;
-	size_t size;
-	const char *comment;
-};
-
-static void print_string_hex(const char *comment, unsigned char *str, size_t len)
-{
-	unsigned char *c;
-
-	printf("%s", comment);
-	for (c = str; c < str + len; c++) {
-		printf("0x%02x ", *c & 0xff);
-	}
-
-	printf("\n");
-}
-
-static void print_insn_detail(csh cs_handle, cs_insn *ins)
-{
-	cs_evm *evm;
-
-	// detail can be NULL on "data" instruction if SKIPDATA option is turned ON
-	if (ins->detail == NULL)
-		return;
-
-	evm = &(ins->detail->evm);
-
-	if (evm->pop)
-		printf("\tPop:     %u\n", evm->pop);
-
-	if (evm->push)
-		printf("\tPush:    %u\n", evm->push);
-
-	if (evm->fee)
-		printf("\tGas fee: %u\n", evm->fee);
-
-	if (ins->detail->groups_count) {
-		int j;
-
-		printf("\tGroups: ");
-		for(j = 0; j < ins->detail->groups_count; j++) {
-			printf("%s ", cs_group_name(handle, ins->detail->groups[j]));
-		}
-		printf("\n");
-	}
-}
-
-static void test()
-{
-#define EVM_CODE "\x60\x61\x50"
-
-	struct platform platforms[] = {
-		{
-			CS_ARCH_EVM,
-			0,
-			(unsigned char *)EVM_CODE,
-			sizeof(EVM_CODE) - 1,
-			"EVM"
-		},
-	};
-
-	uint64_t address = 0x80001000;
-	cs_insn *insn;
-	int i;
-	size_t count;
-
-	for (i = 0; i < sizeof(platforms)/sizeof(platforms[0]); i++) {
-		cs_err err = cs_open(platforms[i].arch, platforms[i].mode, &handle);
-		if (err) {
-			printf("Failed on cs_open() with error returned: %u\n", err);
-			abort();
-		}
-
-		cs_option(handle, CS_OPT_DETAIL, CS_OPT_ON);
-
-		count = cs_disasm(handle, platforms[i].code, platforms[i].size, address, 0, &insn);
-		if (count) {
-			size_t j;
-			printf("****************\n");
-			printf("Platform: %s\n", platforms[i].comment);
-			print_string_hex("Code:", platforms[i].code, platforms[i].size);
-			printf("Disasm:\n");
-
-			for (j = 0; j < count; j++) {
-				printf("0x%" PRIx64 ":\t%s\t%s\n", insn[j].address, insn[j].mnemonic, insn[j].op_str);
-				print_insn_detail(handle, &insn[j]);
-			}
-			printf("0x%" PRIx64 ":\n", insn[j-1].address + insn[j-1].size);
-
-			// free memory allocated by cs_disasm()
-			cs_free(insn, count);
-		} else {
-			printf("****************\n");
-			printf("Platform: %s\n", platforms[i].comment);
-			print_string_hex("Code:", platforms[i].code, platforms[i].size);
-			printf("ERROR: Failed to disasm given code!\n");
-			abort();
-		}
-
-		printf("\n");
-
-		cs_close(&handle);
-	}
-}
-
-int main()
-{
-	test();
-
-	return 0;
-}
-
diff --git a/tests/test_hppa.c b/tests/test_hppa.c
deleted file mode 100644
index d96693cc7..000000000
--- a/tests/test_hppa.c
+++ /dev/null
@@ -1,186 +0,0 @@
-/* Capstone Disassembler Engine */
-/* By Dmitry Sibirtsev <sibirtsevdl@gmail.com>, 2023 */
-
-#include <stdio.h>
-
-#include <capstone/platform.h>
-#include <capstone/capstone.h>
-
-struct platform {
-	cs_arch arch;
-	cs_mode mode;
-	unsigned char *code;
-	size_t size;
-	char *comment;
-};
-
-static csh handle;
-
-static void print_string_hex(char *comment, unsigned char *str, size_t len)
-{
-	unsigned char *c;
-
-	printf("%s", comment);
-	for (c = str; c < str + len; c++) {
-		printf("0x%02x ", *c & 0xff);
-	}
-
-	printf("\n");
-}
-
-static void print_insn_detail(cs_insn *ins)
-{
-	cs_hppa *hppa;
-	int i;
-
-	// detail can be NULL on "data" instruction if SKIPDATA option is turned ON
-	if (ins->detail == NULL)
-		return;
-
-	hppa = &(ins->detail->hppa);
-	if (hppa->op_count)
-		printf("\top_count: %u\n", hppa->op_count);
-
-	for (i = 0; i < hppa->op_count; i++) {
-		cs_hppa_op *op = &(hppa->operands[i]);
-		switch ((int)op->type) {
-		default:
-			break;
-		case HPPA_OP_REG:
-			printf("\t\toperands[%u].type: REG = %s\n", i,
-			       cs_reg_name(handle, op->reg));
-			break;
-		case HPPA_OP_IMM:
-			printf("\t\toperands[%u].type: IMM = 0x%" PRIx64 "\n",
-			       i, op->imm);
-			break;
-		case HPPA_OP_IDX_REG:
-			printf("\t\toperands[%u].type: IDX_REG = %s\n", i,
-			       cs_reg_name(handle, op->reg));
-			break;
-		case HPPA_OP_DISP:
-			printf("\t\toperands[%u].type: DISP = 0x%" PRIx64 "\n",
-			       i, op->imm);
-			break;
-		case HPPA_OP_MEM:
-			printf("\t\toperands[%u].type: MEM\n", i);
-			if (op->mem.space != HPPA_REG_INVALID) {
-				printf("\t\t\toperands[%u].mem.space: REG = %s\n",
-				       i, cs_reg_name(handle, op->mem.space));
-			}
-			printf("\t\t\toperands[%u].mem.base: REG = %s\n", i,
-			       cs_reg_name(handle, op->mem.base));
-			break;
-		case HPPA_OP_TARGET:
-			printf("\t\toperands[%u].type: ", i);
-			if (op->imm >= 0x8000000000000000)
-				printf("TARGET = -0x%" PRIx64 "\n", -op->imm);
-			else
-				printf("TARGET = 0x%" PRIx64 "\n", op->imm);
-			break;
-		}
-	}
-
-	printf("\n");
-}
-
-static void test()
-{
-#define HPPA_20_CODE_BE \
-	"\x00\x20\x50\xa2\x00\x01\x58\x20\x00\x00\x44\xa1\x00\x41\x18\x40\x00\x20\x08\xa2\x01\x60\x48\xa1\x01\x61\x18\xc0\x00\x00\x14\xa1\x00\x0f\x0d\x61\x00\x0f\x0e\x61\x00\x01\x18\x60\x00\x00\x0c\x00\x00\x00\x0c\xa0\x03\xff\xc0\x1f\x00\x00\x04\x00\x00\x10\x04\x00\x04\x22\x51\x83\x04\x22\x51\xc3\x04\x22\x51\x83\x04\x2f\x71\x83\x04\x2f\x71\xc3\x04\x2f\x71\x83\x04\x41\x53\x43\x04\x41\x53\x63\x04\x41\x53\x03\x04\x41\x12\x00\x04\x41\x16\x00\x04\x41\x16\x20\x04\x41\x42\x00\x04\x41\x46\x00\x04\x41\x46\x20\x04\x41\x12\x40\x04\x41\x12\x60\x04\x41\x42\x40\x04\x41\x42\x60\x04\x41\x18\x00\x04\x41\x08\x00\x04\x41\x13\x80\x04\x41\x13\xa0\x04\x41\x52\x80\x04\x41\x52\xa0\x04\x5e\x72\x80\x04\x41\x42\x80\x04\x41\x52\xc0\x04\x41\x52\xe0\x04\x41\x42\xc0\x04\x41\x42\xe0\x14\x00\xde\xad"
-#define HPPA_20_CODE \
-	"\xa2\x50\x20\x00\x20\x58\x01\x00\xa1\x44\x00\x00\x40\x18\x41\x00\xa2\x08\x20\x00\xa1\x48\x60\x01\xc0\x18\x61\x01\xa1\x14\x00\x00\x61\x0d\x0f\x00\x61\x0e\x0f\x00\x60\x18\x01\x00\x00\x0c\x00\x00\xa0\x0c\x00\x00\x1f\xc0\xff\x03\x00\x04\x00\x00\x00\x04\x10\x00\x83\x51\x22\x04\xc3\x51\x22\x04\x83\x51\x22\x04\x83\x71\x2f\x04\xc3\x71\x2f\x04\x83\x71\x2f\x04\x43\x53\x41\x04\x63\x53\x41\x04\x03\x53\x41\x04\x00\x12\x41\x04\x00\x16\x41\x04\x20\x16\x41\x04\x00\x42\x41\x04\x00\x46\x41\x04\x20\x46\x41\x04\x40\x12\x41\x04\x60\x12\x41\x04\x40\x42\x41\x04\x60\x42\x41\x04\x00\x18\x41\x04\x00\x08\x41\x04\x80\x13\x41\x04\xa0\x13\x41\x04\x80\x52\x41\x04\xa0\x52\x41\x04\x80\x72\x5e\x04\x80\x42\x41\x04\xc0\x52\x41\x04\xe0\x52\x41\x04\xc0\x42\x41\x04\xe0\x42\x41\x04\xad\xde\x00\x14"
-#define HPPA_11_CODE_BE \
-	"\x24\x41\x40\xc3\x24\x41\x60\xc3\x24\x41\x40\xe3\x24\x41\x60\xe3\x24\x41\x68\xe3\x2c\x41\x40\xc3\x2c\x41\x60\xc3\x2c\x41\x40\xe3\x2c\x41\x60\xe3\x2c\x41\x68\xe3\x24\x62\x42\xc1\x24\x62\x62\xc1\x24\x62\x42\xe1\x24\x62\x46\xe1\x24\x62\x62\xe1\x24\x62\x6a\xe1\x2c\x62\x42\xc1\x2c\x62\x62\xc1\x2c\x62\x42\xe1\x2c\x62\x46\xe1\x2c\x62\x62\xe1\x2c\x62\x6a\xe1\x24\x3e\x50\xc2\x24\x3e\x50\xe2\x24\x3e\x70\xe2\x24\x3e\x78\xe2\x2c\x3e\x50\xc2\x2c\x3e\x50\xe2\x2c\x3e\x70\xe2\x2c\x3e\x78\xe2\x24\x5e\x52\xc1\x24\x5e\x52\xe1\x24\x5e\x56\xe1\x24\x5e\x72\xe1\x24\x5e\x7a\xe1\x2c\x5e\x52\xc1\x2c\x5e\x52\xe1\x2c\x5e\x56\xe1\x2c\x5e\x72\xe1\x2c\x5e\x7a\xe1"
-#define HPPA_11_CODE \
-	"\xc3\x40\x41\x24\xc3\x60\x41\x24\xe3\x40\x41\x24\xe3\x60\x41\x24\xe3\x68\x41\x24\xc3\x40\x41\x2c\xc3\x60\x41\x2c\xe3\x40\x41\x2c\xe3\x60\x41\x2c\xe3\x68\x41\x2c\xc1\x42\x62\x24\xc1\x62\x62\x24\xe1\x42\x62\x24\xe1\x46\x62\x24\xe1\x62\x62\x24\xe1\x6a\x62\x24\xc1\x42\x62\x2c\xc1\x62\x62\x2c\xe1\x42\x62\x2c\xe1\x46\x62\x2c\xe1\x62\x62\x2c\xe1\x6a\x62\x2c\xc2\x50\x3e\x24\xe2\x50\x3e\x24\xe2\x70\x3e\x24\xe2\x78\x3e\x24\xc2\x50\x3e\x2c\xe2\x50\x3e\x2c\xe2\x70\x3e\x2c\xe2\x78\x3e\x2c\xc1\x52\x5e\x24\xe1\x52\x5e\x24\xe1\x56\x5e\x24\xe1\x72\x5e\x24\xe1\x7a\x5e\x24\xc1\x52\x5e\x2c\xe1\x52\x5e\x2c\xe1\x56\x5e\x2c\xe1\x72\x5e\x2c\xe1\x7a\x5e\x2c"
-
-	struct platform platforms[] = {
-		{
-			CS_ARCH_HPPA,
-			CS_MODE_BIG_ENDIAN | CS_MODE_HPPA_20,
-			(unsigned char *)HPPA_20_CODE_BE,
-			sizeof(HPPA_20_CODE_BE) - 1,
-			"HPPA 2.0 (Big-endian)",
-		},
-		{
-			CS_ARCH_HPPA,
-			CS_MODE_LITTLE_ENDIAN | CS_MODE_HPPA_20,
-			(unsigned char *)HPPA_20_CODE,
-			sizeof(HPPA_20_CODE) - 1,
-			"HPPA 2.0 (Little-endian)",
-		},
-		{
-			CS_ARCH_HPPA,
-			CS_MODE_BIG_ENDIAN | CS_MODE_HPPA_11,
-			(unsigned char *)HPPA_11_CODE_BE,
-			sizeof(HPPA_11_CODE_BE) - 1,
-			"HPPA 1.1 (Big-endian)",
-		},
-		{
-			CS_ARCH_HPPA,
-			CS_MODE_LITTLE_ENDIAN | CS_MODE_HPPA_11,
-			(unsigned char *)HPPA_11_CODE,
-			sizeof(HPPA_11_CODE) - 1,
-			"HPPA 1.1 (Little-endian)",
-		},
-	};
-
-	uint64_t address = 0x1000;
-	cs_insn *insn;
-	int i;
-	size_t count;
-
-	for (i = 0; i < sizeof(platforms) / sizeof(platforms[0]); i++) {
-		cs_err err =
-			cs_open(platforms[i].arch, platforms[i].mode, &handle);
-		if (err) {
-			printf("Failed on cs_open() with error returned: %u\n",
-			       err);
-			continue;
-		}
-
-		cs_option(handle, CS_OPT_DETAIL, CS_OPT_ON);
-
-		count = cs_disasm(handle, platforms[i].code, platforms[i].size,
-				  address, 0, &insn);
-		if (count) {
-			size_t j;
-
-			printf("****************\n");
-			printf("Platform: %s\n", platforms[i].comment);
-			print_string_hex("Code: ", platforms[i].code,
-					 platforms[i].size);
-			printf("Disasm:\n");
-
-			for (j = 0; j < count; j++) {
-				printf("0x%" PRIx64 ":\t%s\t%s\n",
-				       insn[j].address, insn[j].mnemonic,
-				       insn[j].op_str);
-				print_insn_detail(&insn[j]);
-			}
-			printf("0x%" PRIx64 ":\n",
-			       insn[j - 1].address + insn[j - 1].size);
-
-			// free memory allocated by cs_disasm()
-			cs_free(insn, count);
-		} else {
-			printf("****************\n");
-			printf("Platform: %s\n", platforms[i].comment);
-			print_string_hex("Code:", platforms[i].code,
-					 platforms[i].size);
-			printf("ERROR: Failed to disasm given code!\n");
-		}
-
-		printf("\n");
-
-		cs_close(&handle);
-	}
-}
-
-int main()
-{
-	test();
-
-	return 0;
-}
diff --git a/tests/test_loongarch.c b/tests/test_loongarch.c
deleted file mode 100644
index 9f67e9c9f..000000000
--- a/tests/test_loongarch.c
+++ /dev/null
@@ -1,160 +0,0 @@
-#include <stdio.h>
-#include <stdlib.h>
-
-#include <capstone/capstone.h>
-#include <capstone/platform.h>
-
-struct platform {
-	cs_arch arch;
-	cs_mode mode;
-	unsigned char *code;
-	size_t size;
-	const char *comment;
-};
-
-static csh handle;
-
-static void print_string_hex(const char *comment, unsigned char *str,
-			     size_t len)
-{
-	unsigned char *c;
-
-	printf("%s", comment);
-	for (c = str; c < str + len; c++) {
-		printf("0x%02x ", *c & 0xff);
-	}
-
-	printf("\n");
-}
-
-static void print_insn_detail(cs_insn *ins)
-{
-	int i;
-	int n;
-	cs_loongarch *loongarch;
-	cs_detail *detail;
-
-	// detail can be NULL on "data" instruction if SKIPDATA option is turned ON
-	if (ins->detail == NULL)
-		return;
-
-	loongarch = &(ins->detail->loongarch);
-	detail = ins->detail;
-	if (loongarch->op_count)
-		printf("\top_count: %u\n", loongarch->op_count);
-
-	for (i = 0; i < loongarch->op_count; i++) {
-		cs_loongarch_op *op = &(loongarch->operands[i]);
-		switch ((int)op->type) {
-		default:
-			printf("\terror in opt_type: %u\n", (int)op->type);
-			break;
-		case LOONGARCH_OP_REG:
-			printf("\t\toperands[%u].type: REG = %s\n", i,
-			       cs_reg_name(handle, op->reg));
-			break;
-		case LOONGARCH_OP_IMM:
-			printf("\t\toperands[%u].type: IMM = 0x%" PRIx64 "\n",
-			       i, op->imm);
-			break;
-		case LOONGARCH_OP_MEM:
-			printf("\t\toperands[%u].type: MEM\n", i);
-			if (op->mem.base != LOONGARCH_REG_INVALID)
-				printf("\t\t\toperands[%u].mem.base: REG = %s\n",
-				       i, cs_reg_name(handle, op->mem.base));
-			if (op->mem.disp != 0)
-				printf("\t\t\toperands[%u].mem.disp: 0x%" PRIx64
-				       "\n",
-				       i, op->mem.disp);
-
-			break;
-		}
-	}
-
-	// print the groups this instruction belongs to
-	if (detail->groups_count > 0) {
-		printf("\tgroups: ");
-		for (n = 0; n < detail->groups_count; n++) {
-			printf("%s ", cs_group_name(handle, detail->groups[n]));
-		}
-		printf("\n");
-	}
-
-	printf("\n");
-}
-
-static void test()
-{
-#define LOONGARCH_CODE32 "\x0c\x00\x08\x14\x8c\xfd\xbf\x02"
-#define LOONGARCH_CODE64 \
-	"\x80\x80\x00\x40\x63\x80\xff\x02\x78\x20\xc0\x29\x00\x84\x00\x01\x00\xa4" \
-	"\x14\x01"
-	struct platform platforms[] = {
-		{ CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH32,
-		  (unsigned char *)LOONGARCH_CODE32,
-		  sizeof(LOONGARCH_CODE32) - 1, "loongarch32" },
-		{ CS_ARCH_LOONGARCH, CS_MODE_LOONGARCH64,
-		  (unsigned char *)LOONGARCH_CODE64,
-		  sizeof(LOONGARCH_CODE64) - 1, "loongarch64" }
-	};
-
-	uint64_t address = 0x1000;
-	cs_insn *insn;
-	int i;
-	size_t count;
-
-	for (i = 0; i < sizeof(platforms) / sizeof(platforms[0]); i++) {
-		cs_err err =
-			cs_open(platforms[i].arch, platforms[i].mode, &handle);
-		if (err) {
-			printf("Failed on cs_open() with error returned: %u\n",
-			       err);
-			continue;
-		}
-
-		// To turn on or off the Print Details option
-		// cs_option(handle, CS_OPT_DETAIL, CS_OPT_OFF);
-		cs_option(handle, CS_OPT_DETAIL, CS_OPT_ON);
-
-		count = cs_disasm(handle, platforms[i].code, platforms[i].size,
-				  address, 0, &insn);
-		if (count) {
-			size_t j;
-
-			printf("****************\n");
-			printf("Platform: %s\n", platforms[i].comment);
-			print_string_hex("Code:", platforms[i].code,
-					 platforms[i].size);
-			printf("Disasm:\n");
-
-			for (j = 0; j < count; j++) {
-				printf("0x%" PRIx64 ":\t%s\t%s\n",
-				       insn[j].address, insn[j].mnemonic,
-				       insn[j].op_str);
-				print_insn_detail(&insn[j]);
-			}
-			printf("0x%" PRIx64 ":\n",
-			       insn[j - 1].address + insn[j - 1].size);
-
-			// free memory allocated by cs_disasm()
-			cs_free(insn, count);
-		} else {
-			printf("****************\n");
-			printf("Platform: %s\n", platforms[i].comment);
-			print_string_hex("Code:", platforms[i].code,
-					 platforms[i].size);
-			printf("ERROR: Failed to disasm given code!\n");
-		}
-
-		printf("\n");
-
-		cs_close(&handle);
-	}
-}
-
-int main()
-{
-	test();
-
-	return 0;
-}
diff --git a/tests/test_m680x.c b/tests/test_m680x.c
deleted file mode 100644
index aa1f57272..000000000
--- a/tests/test_m680x.c
+++ /dev/null
@@ -1,396 +0,0 @@
-/* Capstone Disassembler Engine */
-/* M680X Backend by Wolfgang Schwotzer <wolfgang.schwotzer@gmx.net> 2017 */
-
-#include <stdio.h>
-#include <string.h>
-
-#include <capstone/platform.h>
-#include <capstone/capstone.h>
-
-#define WITH_DETAILS
-
-struct platform {
-	cs_arch arch;
-	cs_mode mode;
-	unsigned char *code;
-	size_t size;
-	const char *comment;
-};
-
-static void print_string_hex(const char *comment, unsigned char *str, size_t len)
-{
-	unsigned char *c;
-
-	printf("%s", comment);
-
-	for (c = str; c < str + len; c++)
-		printf("0x%02x ", *c & 0xff);
-
-	printf("\n");
-}
-
-static void print_string_hex_short(unsigned char *str, size_t len)
-{
-	unsigned char *c;
-
-	for (c = str; c < str + len; c++)
-		printf("%02x", *c & 0xff);
-}
-
-static const char *s_access[] = {
-	"UNCHANGED", "READ", "WRITE", "READ | WRITE",
-};
-
-static void print_read_write_regs(csh handle, cs_detail *detail)
-{
-	int i;
-
-	if (detail->regs_read_count > 0) {
-		printf("\tRegisters read:");
-
-		for (i = 0; i < detail->regs_read_count; ++i)
-			printf(" %s",
-				cs_reg_name(handle, detail->regs_read[i]));
-
-		printf("\n");
-	}
-
-	if (detail->regs_write_count > 0) {
-		printf("\tRegisters modified:");
-
-		for (i = 0; i < detail->regs_write_count; ++i)
-			printf(" %s",
-				cs_reg_name(handle, detail->regs_write[i]));
-
-		printf("\n");
-	}
-}
-
-static void print_insn_detail(csh handle, cs_insn *insn)
-{
-	cs_detail *detail = insn->detail;
-	cs_m680x *m680x = NULL;
-	int i;
-
-	// detail can be NULL on "data" instruction if SKIPDATA option is turned ON
-	if (detail == NULL)
-		return;
-
-	m680x = &detail->m680x;
-
-	if (m680x->op_count)
-		printf("\top_count: %u\n", m680x->op_count);
-
-	for (i = 0; i < m680x->op_count; i++) {
-		cs_m680x_op *op = &(m680x->operands[i]);
-		const char *comment;
-
-		switch ((int)op->type) {
-		default:
-			break;
-
-		case M680X_OP_REGISTER:
-			comment = "";
-
-			if ((i == 0 && (m680x->flags &
-						M680X_FIRST_OP_IN_MNEM)) ||
-				((i == 1 && (m680x->flags &
-							M680X_SECOND_OP_IN_MNEM))))
-				comment = " (in mnemonic)";
-
-			printf("\t\toperands[%u].type: REGISTER = %s%s\n", i,
-				cs_reg_name(handle, op->reg), comment);
-			break;
-
-		case M680X_OP_CONSTANT:
-			printf("\t\toperands[%u].type: CONSTANT = %u\n", i,
-				op->const_val);
-			break;
-
-		case M680X_OP_IMMEDIATE:
-			printf("\t\toperands[%u].type: IMMEDIATE = #%d\n", i,
-				op->imm);
-			break;
-
-		case M680X_OP_DIRECT:
-			printf("\t\toperands[%u].type: DIRECT = 0x%02x\n", i,
-				op->direct_addr);
-			break;
-
-		case M680X_OP_EXTENDED:
-			printf("\t\toperands[%u].type: EXTENDED %s = 0x%04x\n",
-				i, op->ext.indirect ? "INDIRECT" : "",
-				op->ext.address);
-			break;
-
-		case M680X_OP_RELATIVE:
-			printf("\t\toperands[%u].type: RELATIVE = 0x%04x\n", i,
-				op->rel.address);
-			break;
-
-		case M680X_OP_INDEXED:
-			printf("\t\toperands[%u].type: INDEXED%s\n", i,
-				(op->idx.flags & M680X_IDX_INDIRECT) ?
-				" INDIRECT" : "");
-
-			if (op->idx.base_reg != M680X_REG_INVALID)
-				printf("\t\t\tbase register: %s\n",
-					cs_reg_name(handle, op->idx.base_reg));
-
-			if (op->idx.offset_reg != M680X_REG_INVALID)
-				printf("\t\t\toffset register: %s\n",
-					cs_reg_name(handle, op->idx.offset_reg));
-
-			if ((op->idx.offset_bits != 0) &&
-				(op->idx.offset_reg == M680X_REG_INVALID) &&
-				!op->idx.inc_dec) {
-				printf("\t\t\toffset: %d\n", op->idx.offset);
-
-				if (op->idx.base_reg == M680X_REG_PC)
-					printf("\t\t\toffset address: 0x%x\n",
-						op->idx.offset_addr);
-
-				printf("\t\t\toffset bits: %u\n",
-					op->idx.offset_bits);
-			}
-
-			if (op->idx.inc_dec) {
-				const char *post_pre = op->idx.flags &
-					M680X_IDX_POST_INC_DEC ? "post" : "pre";
-				const char *inc_dec = (op->idx.inc_dec > 0) ?
-					"increment" : "decrement";
-
-				printf("\t\t\t%s %s: %d\n", post_pre, inc_dec,
-					abs(op->idx.inc_dec));
-			}
-
-			break;
-		}
-
-		if (op->size != 0)
-			printf("\t\t\tsize: %u\n", op->size);
-
-		if (op->access != CS_AC_INVALID)
-			printf("\t\t\taccess: %s\n", s_access[op->access]);
-
-	}
-
-	print_read_write_regs(handle, detail);
-
-	if (detail->groups_count) {
-		printf("\tgroups_count: %u\n", detail->groups_count);
-	}
-
-	printf("\n");
-}
-
-static bool consistency_checks()
-{
-	return true;
-}
-
-static void test()
-{
-#define M6800_CODE \
-  "\x01\x09\x36\x64\x7f\x74\x10\x00\x90\x10\xA4\x10\xb6\x10\x00\x39"
-
-#define M6801_CODE \
-  "\x04\x05\x3c\x3d\x38\x93\x10\xec\x10\xed\x10\x39"
-
-#define M6805_CODE \
-  "\x04\x7f\x00\x17\x22\x28\x00\x2e\x00\x40\x42\x5a\x70\x8e\x97\x9c" \
-  "\xa0\x15\xad\x00\xc3\x10\x00\xda\x12\x34\xe5\x7f\xfe"
-
-#define M6808_CODE \
-  "\x31\x22\x00\x35\x22\x45\x10\x00\x4b\x00\x51\x10\x52\x5e\x22\x62" \
-  "\x65\x12\x34\x72\x84\x85\x86\x87\x8a\x8b\x8c\x94\x95\xa7\x10\xaf\x10" \
-  "\x9e\x60\x7f\x9e\x6b\x7f\x00\x9e\xd6\x10\x00\x9e\xe6\x7f"
-
-#define HCS08_CODE \
-  "\x32\x10\x00\x9e\xae\x9e\xce\x7f\x9e\xbe\x10\x00\x9e\xfe\x7f" \
-  "\x3e\x10\x00\x9e\xf3\x7f\x96\x10\x00\x9e\xff\x7f\x82"
-
-#define M6811_CODE \
-  "\x02\x03\x12\x7f\x10\x00\x13\x99\x08\x00\x14\x7f\x02\x15\x7f\x01" \
-  "\x1e\x7f\x20\x00\x8f\xcf" \
-  "\x18\x08\x18\x30\x18\x3c\x18\x67\x18\x8c\x10\x00\x18\x8f" \
-  "\x18\xce\x10\x00\x18\xff\x10\x00" \
-  "\x1a\xa3\x7f\x1a\xac\x1a\xee\x7f\x1a\xef\x7f\xcd\xac\x7f"
-
-#define CPU12_CODE \
-  "\x00\x04\x01\x00\x0c\x00\x80\x0e\x00\x80\x00\x11\x1e\x10\x00\x80\x00" \
-  "\x3b\x4a\x10\x00\x04\x4b\x01\x04\x4f\x7f\x80\x00\x8f\x10\x00\xb7\x52" \
-  "\xb7\xb1\xa6\x67\xa6\xfe\xa6\xf7\x18\x02\xe2\x30\x39\xe2\x10\x00" \
-  "\x18\x0c\x30\x39\x10\x00\x18\x11\x18\x12\x10\x00\x18\x19\x00\x18\x1e\x00" \
-  "\x18\x3e\x18\x3f\x00"
-
-#define HD6301_CODE \
-  "\x6b\x10\x00\x71\x10\x00\x72\x10\x10\x39"
-
-#define M6809_CODE \
-  "\x06\x10\x19\x1a\x55\x1e\x01\x23\xe9\x31\x06\x34\x55\xa6\x81" \
-  "\xa7\x89\x7f\xff\xa6\x9d\x10\x00\xa7\x91\xa6\x9f\x10\x00" \
-  "\x11\xac\x99\x10\x00\x39" \
-  \
-  "\xA6\x07\xA6\x27\xA6\x47\xA6\x67\xA6\x0F\xA6\x10" \
-  "\xA6\x80\xA6\x81\xA6\x82\xA6\x83\xA6\x84\xA6\x85\xA6\x86" \
-  "\xA6\x88\x7F\xA6\x88\x80\xA6\x89\x7F\xFF\xA6\x89\x80\x00" \
-  "\xA6\x8B\xA6\x8C\x10\xA6\x8D\x10\x00" \
-  \
-  "\xA6\x91\xA6\x93\xA6\x94\xA6\x95\xA6\x96" \
-  "\xA6\x98\x7F\xA6\x98\x80\xA6\x99\x7F\xFF\xA6\x99\x80\x00" \
-  "\xA6\x9B\xA6\x9C\x10\xA6\x9D\x10\x00\xA6\x9F\x10\x00"
-
-#define HD6309_CODE \
-  "\x01\x10\x10\x62\x10\x10\x7b\x10\x10\x00\xcd\x49\x96\x02\xd2" \
-  "\x10\x30\x23\x10\x38\x10\x3b\x10\x53\x10\x5d" \
-  "\x11\x30\x43\x10\x11\x37\x25\x10\x11\x38\x12\x11\x39\x23\x11\x3b\x34" \
-  "\x11\x8e\x10\x00\x11\xaf\x10\x11\xab\x10\x11\xf6\x80\x00"
-
-	struct platform platforms[] = {
-		{
-			CS_ARCH_M680X,
-			(cs_mode)(CS_MODE_M680X_6301),
-			(unsigned char *)HD6301_CODE,
-			sizeof(HD6301_CODE) - 1,
-			"M680X_HD6301",
-		},
-		{
-			CS_ARCH_M680X,
-			(cs_mode)(CS_MODE_M680X_6309),
-			(unsigned char *)HD6309_CODE,
-			sizeof(HD6309_CODE) - 1,
-			"M680X_HD6309",
-		},
-		{
-			CS_ARCH_M680X,
-			(cs_mode)(CS_MODE_M680X_6800),
-			(unsigned char *)M6800_CODE,
-			sizeof(M6800_CODE) - 1,
-			"M680X_M6800",
-		},
-		{
-			CS_ARCH_M680X,
-			(cs_mode)(CS_MODE_M680X_6801),
-			(unsigned char *)M6801_CODE,
-			sizeof(M6801_CODE) - 1,
-			"M680X_M6801",
-		},
-		{
-			CS_ARCH_M680X,
-			(cs_mode)(CS_MODE_M680X_6805),
-			(unsigned char *)M6805_CODE,
-			sizeof(M6805_CODE) - 1,
-			"M680X_M68HC05",
-		},
-		{
-			CS_ARCH_M680X,
-			(cs_mode)(CS_MODE_M680X_6808),
-			(unsigned char *)M6808_CODE,
-			sizeof(M6808_CODE) - 1,
-			"M680X_M68HC08",
-		},
-		{
-			CS_ARCH_M680X,
-			(cs_mode)(CS_MODE_M680X_6809),
-			(unsigned char *)M6809_CODE,
-			sizeof(M6809_CODE) - 1,
-			"M680X_M6809",
-		},
-		{
-			CS_ARCH_M680X,
-			(cs_mode)(CS_MODE_M680X_6811),
-			(unsigned char *)M6811_CODE,
-			sizeof(M6811_CODE) - 1,
-			"M680X_M68HC11",
-		},
-		{
-			CS_ARCH_M680X,
-			(cs_mode)(CS_MODE_M680X_CPU12),
-			(unsigned char *)CPU12_CODE,
-			sizeof(CPU12_CODE) - 1,
-			"M680X_CPU12",
-		},
-		{
-			CS_ARCH_M680X,
-			(cs_mode)(CS_MODE_M680X_HCS08),
-			(unsigned char *)HCS08_CODE,
-			sizeof(HCS08_CODE) - 1,
-			"M680X_HCS08",
-		},
-	};
-
-	uint64_t address = 0x1000;
-	csh handle;
-	cs_insn *insn;
-	int i;
-	size_t count;
-	const char *nine_spaces = "         ";
-
-	if (!consistency_checks())
-		abort();
-
-	for (i = 0; i < sizeof(platforms) / sizeof(platforms[0]); i++) {
-		cs_err err = cs_open(platforms[i].arch, platforms[i].mode,
-				&handle);
-
-		if (err) {
-			printf("Failed on cs_open() with error returned: %u\n",
-				err);
-			abort();
-		}
-
-#ifdef WITH_DETAILS
-		cs_option(handle, CS_OPT_DETAIL, CS_OPT_ON);
-#endif
-
-		count = cs_disasm(handle, platforms[i].code, platforms[i].size,
-				address, 0, &insn);
-
-		if (count) {
-			size_t j;
-
-			printf("********************\n");
-			printf("Platform: %s\n", platforms[i].comment);
-			print_string_hex("Code: ", platforms[i].code,
-				platforms[i].size);
-			printf("Disasm:\n");
-
-			for (j = 0; j < count; j++) {
-				int slen;
-				printf("0x%04x: ", (uint16_t)insn[j].address);
-				print_string_hex_short(insn[j].bytes,
-					insn[j].size);
-				printf("%.*s", 1 + ((5 - insn[j].size) * 2),
-					nine_spaces);
-				printf("%s", insn[j].mnemonic);
-				slen = (int)strlen(insn[j].mnemonic);
-				printf("%.*s", 1 + (5 - slen), nine_spaces);
-				printf("%s\n", insn[j].op_str);
-#ifdef WITH_DETAILS
-				print_insn_detail(handle, &insn[j]);
-#endif
-			}
-
-			// free memory allocated by cs_disasm()
-			cs_free(insn, count);
-		}
-		else {
-			printf("********************\n");
-			printf("Platform: %s\n", platforms[i].comment);
-			print_string_hex("Code:", platforms[i].code,
-				platforms[i].size);
-			printf("ERROR: Failed to disasm given code!\n");
-			abort();
-		}
-
-		cs_close(&handle);
-	}
-}
-
-int main()
-{
-	test();
-
-	return 0;
-}
diff --git a/tests/test_m68k.c b/tests/test_m68k.c
deleted file mode 100644
index e003f486b..000000000
--- a/tests/test_m68k.c
+++ /dev/null
@@ -1,222 +0,0 @@
-/* Capstone Disassembler Engine */
-/* By Daniel Collin, 2013-2019 */
-
-#include <stdio.h>
-#include <assert.h>
-
-#include <capstone/platform.h>
-#include <capstone/capstone.h>
-
-struct platform {
-	cs_arch arch;
-	cs_mode mode;
-	unsigned char* code;
-	size_t size;
-	const char* comment;
-};
-
-static csh handle;
-
-static void print_string_hex(const char* comment, unsigned char* str, size_t len)
-{
-	unsigned char *c;
-
-	printf("%s", comment);
-	for (c = str; c < str + len; c++) {
-		printf("0x%02x ", *c & 0xff);
-	}
-
-	printf("\n");
-}
-
-const char* s_addressing_modes[] = {
-	"<invalid mode>",
-
-	"Register Direct - Data",
-	"Register Direct - Address",
-
-	"Register Indirect - Address",
-	"Register Indirect - Address with Postincrement",
-	"Register Indirect - Address with Predecrement",
-	"Register Indirect - Address with Displacement",
-
-	"Address Register Indirect With Index - 8-bit displacement",
-	"Address Register Indirect With Index - Base displacement",
-
-	"Memory indirect - Postindex",
-	"Memory indirect - Preindex",
-
-	"Program Counter Indirect - with Displacement",
-
-	"Program Counter Indirect with Index - with 8-Bit Displacement",
-	"Program Counter Indirect with Index - with Base Displacement",
-
-	"Program Counter Memory Indirect - Postindexed",
-	"Program Counter Memory Indirect - Preindexed",
-
-	"Absolute Data Addressing  - Short",
-	"Absolute Data Addressing  - Long",
-	"Immediate value",
-	"Branch Displacement",
-};
-
-static void print_read_write_regs(cs_detail* detail)
-{
-	int i;
-
-	for (i = 0; i < detail->regs_read_count; ++i)
-	{
-		uint16_t reg_id = detail->regs_read[i];
-		const char* reg_name = cs_reg_name(handle, reg_id);
-		printf("\treading from reg: %s\n", reg_name);
-	}
-
-	for (i = 0; i < detail->regs_write_count; ++i)
-	{
-		uint16_t reg_id = detail->regs_write[i];
-		const char* reg_name = cs_reg_name(handle, reg_id);
-		printf("\twriting to reg:   %s\n", reg_name);
-	}
-}
-
-static void print_insn_detail(cs_insn *ins)
-{
-	cs_m68k* m68k;
-	cs_detail* detail;
-	int i;
-
-	// detail can be NULL on "data" instruction if SKIPDATA option is turned ON
-	if (ins->detail == NULL)
-		return;
-
-	detail = ins->detail;
-	m68k = &detail->m68k;
-	if (m68k->op_count)
-		printf("\top_count: %u\n", m68k->op_count);
-
-	print_read_write_regs(detail);
-
-	printf("\tgroups_count: %u\n", detail->groups_count);
-
-	for (i = 0; i < m68k->op_count; i++) {
-		cs_m68k_op* op = &(m68k->operands[i]);
-
-		switch((int)op->type) {
-			default:
-				break;
-			case M68K_OP_REG:
-				printf("\t\toperands[%u].type: REG = %s\n", i, cs_reg_name(handle, op->reg));
-				break;
-			case M68K_OP_IMM:
-				printf("\t\toperands[%u].type: IMM = 0x%x\n", i, (int)op->imm);
-				break;
-			case M68K_OP_MEM:
-				printf("\t\toperands[%u].type: MEM\n", i);
-				if (op->mem.base_reg != M68K_REG_INVALID)
-					printf("\t\t\toperands[%u].mem.base: REG = %s\n",
-							i, cs_reg_name(handle, op->mem.base_reg));
-				if (op->mem.index_reg != M68K_REG_INVALID) {
-					printf("\t\t\toperands[%u].mem.index: REG = %s\n",
-							i, cs_reg_name(handle, op->mem.index_reg));
-					printf("\t\t\toperands[%u].mem.index: size = %c\n",
-							i, op->mem.index_size ? 'l' : 'w');
-				}
-				if (op->mem.disp != 0)
-					printf("\t\t\toperands[%u].mem.disp: 0x%x\n", i, op->mem.disp);
-				if (op->mem.scale != 0)
-					printf("\t\t\toperands[%u].mem.scale: %d\n", i, op->mem.scale);
-
-				printf("\t\taddress mode: %s\n", s_addressing_modes[op->address_mode]);
-				break;
-			case M68K_OP_FP_SINGLE:
-				printf("\t\toperands[%u].type: FP_SINGLE\n", i);
-				printf("\t\t\toperands[%u].simm: %f\n", i, op->simm);
-				break;
-			case M68K_OP_FP_DOUBLE:
-				printf("\t\toperands[%u].type: FP_DOUBLE\n", i);
-				printf("\t\t\toperands[%u].dimm: %lf\n", i, op->dimm);
-				break;
-			case M68K_OP_REG_BITS:
-				printf("\t\toperands[%u].type: REG_BITS = $%x\n", i, op->register_bits);
-				break;
-			case M68K_OP_REG_PAIR:
-				printf("\t\toperands[%u].type: REG_PAIR = (%s, %s)\n", i,
-					cs_reg_name(handle, op->reg_pair.reg_0),
-					cs_reg_name(handle, op->reg_pair.reg_1));
-				break;
-			case M68K_OP_BR_DISP:
-				printf("\t\toperands[%u].br_disp.disp: 0x%x", i, op->br_disp.disp);
-				printf("\t\toperands[%u].br_disp.disp_size: %d", i, op->br_disp.disp_size);
-				break;
-		}
-	}
-
-	printf("\n");
-}
-
-static void test()
-{
-#define M68K_CODE "\xf0\x10\xf0\x00\x48\xaf\xff\xff\x7f\xff\x11\xb0\x01\x37\x7f\xff\xff\xff\x12\x34\x56\x78\x01\x33\x10\x10\x10\x10\x32\x32\x32\x32\x4C\x00\x54\x04\x48\xe7\xe0\x30\x4C\xDF\x0C\x07\xd4\x40\x87\x5a\x4e\x71\x02\xb4\xc0\xde\xc0\xde\x5c\x00\x1d\x80\x71\x12\x01\x23\xf2\x3c\x44\x22\x40\x49\x0e\x56\x54\xc5\xf2\x3c\x44\x00\x44\x7a\x00\x00\xf2\x00\x0a\x28\x4E\xB9\x00\x00\x00\x12\x4E\x75"
-	struct platform platforms[] = {
-		{
-			CS_ARCH_M68K,
-			(cs_mode)(CS_MODE_BIG_ENDIAN | CS_MODE_M68K_040),
-			(unsigned char*)M68K_CODE,
-			sizeof(M68K_CODE) - 1,
-			"M68K",
-		},
-	};
-
-	uint64_t address = 0x01000;
-	cs_insn *insn;
-	int i;
-	size_t count;
-
-	for (i = 0; i < sizeof(platforms)/sizeof(platforms[0]); i++) {
-		cs_err err = cs_open(platforms[i].arch, platforms[i].mode, &handle);
-		if (err) {
-			printf("Failed on cs_open() with error returned: %u\n", err);
-			abort();
-		}
-
-		cs_option(handle, CS_OPT_DETAIL, CS_OPT_ON);
-
-		count = cs_disasm(handle, platforms[i].code, platforms[i].size, address, 0, &insn);
-		if (count) {
-			size_t j;
-
-			printf("****************\n");
-			printf("Platform: %s\n", platforms[i].comment);
-			print_string_hex("Code: ", platforms[i].code, platforms[i].size);
-			printf("Disasm:\n");
-
-			for (j = 0; j < count; j++) {
-				assert(address == insn[j].address && "this means the size of the previous instruction was incorrect");
-				address += insn[j].size;
-				printf("0x%" PRIx64 ":\t%s\t%s\n", insn[j].address, insn[j].mnemonic, insn[j].op_str);
-				print_insn_detail(&insn[j]);
-			}
-			printf("0x%" PRIx64 ":\n", insn[j-1].address + insn[j-1].size);
-
-			// free memory allocated by cs_disasm()
-			cs_free(insn, count);
-		} else {
-			printf("****************\n");
-			printf("Platform: %s\n", platforms[i].comment);
-			print_string_hex("Code:", platforms[i].code, platforms[i].size);
-			printf("ERROR: Failed to disasm given code!\n");
-			abort();
-		}
-
-		printf("\n");
-
-		cs_close(&handle);
-	}
-}
-
-int main()
-{
-	test();
-
-	return 0;
-}
diff --git a/tests/test_mips.c b/tests/test_mips.c
deleted file mode 100644
index e5c5a400c..000000000
--- a/tests/test_mips.c
+++ /dev/null
@@ -1,175 +0,0 @@
-/* Capstone Disassembler Engine */
-/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
-
-#include <stdio.h>
-#include <stdlib.h>
-
-#include <capstone/platform.h>
-#include <capstone/capstone.h>
-
-struct platform {
-	cs_arch arch;
-	cs_mode mode;
-	unsigned char *code;
-	size_t size;
-	const char *comment;
-};
-
-static csh handle;
-
-static void print_string_hex(const char *comment, unsigned char *str, size_t len)
-{
-	unsigned char *c;
-
-	printf("%s", comment);
-	for (c = str; c < str + len; c++) {
-		printf("0x%02x ", *c & 0xff);
-	}
-
-	printf("\n");
-}
-
-static void print_insn_detail(cs_insn *ins)
-{
-	int i;
-	cs_mips *mips;
-
-	// detail can be NULL on "data" instruction if SKIPDATA option is turned ON
-	if (ins->detail == NULL)
-		return;
-
-	mips = &(ins->detail->mips);
-	if (mips->op_count)
-		printf("\top_count: %u\n", mips->op_count);
-
-	for (i = 0; i < mips->op_count; i++) {
-		cs_mips_op *op = &(mips->operands[i]);
-		switch((int)op->type) {
-			default:
-				break;
-			case MIPS_OP_REG:
-				printf("\t\toperands[%u].type: REG = %s\n", i, cs_reg_name(handle, op->reg));
-				break;
-			case MIPS_OP_IMM:
-				printf("\t\toperands[%u].type: IMM = 0x%" PRIx64 "\n", i, op->imm);
-				break;
-			case MIPS_OP_MEM:
-				printf("\t\toperands[%u].type: MEM\n", i);
-				if (op->mem.base != MIPS_REG_INVALID)
-					printf("\t\t\toperands[%u].mem.base: REG = %s\n",
-							i, cs_reg_name(handle, op->mem.base));
-				if (op->mem.disp != 0)
-					printf("\t\t\toperands[%u].mem.disp: 0x%" PRIx64 "\n", i, op->mem.disp);
-
-				break;
-		}
-
-	}
-
-	printf("\n");
-}
-
-static void test()
-{
-#define MIPS_CODE "\x0C\x10\x00\x97\x00\x00\x00\x00\x24\x02\x00\x0c\x8f\xa2\x00\x00\x34\x21\x34\x56"
-#define MIPS_CODE2 "\x56\x34\x21\x34\xc2\x17\x01\x00"
-#define MIPS_32R6M "\x00\x07\x00\x07\x00\x11\x93\x7c\x01\x8c\x8b\x7c\x00\xc7\x48\xd0"
-#define MIPS_32R6 "\xec\x80\x00\x19\x7c\x43\x22\xa0"
-#define MIPS_64SD "\x70\x00\xb2\xff"
-
-	struct platform platforms[] = {
-		{
-			CS_ARCH_MIPS,
-			(cs_mode)(CS_MODE_MIPS32 | CS_MODE_BIG_ENDIAN),
-			(unsigned char *)MIPS_CODE,
-			sizeof(MIPS_CODE) - 1,
-			"MIPS-32 (Big-endian)"
-		},
-		{
-			CS_ARCH_MIPS,
-			(cs_mode)(CS_MODE_MIPS64 | CS_MODE_LITTLE_ENDIAN),
-			(unsigned char *)MIPS_CODE2,
-			sizeof(MIPS_CODE2) - 1,
-			"MIPS-64-EL (Little-endian)"
-		},
-		{
-			CS_ARCH_MIPS,
-			(cs_mode)(CS_MODE_MIPS32R6 | CS_MODE_MICRO | CS_MODE_BIG_ENDIAN),
-			(unsigned char*)MIPS_32R6M,
-			sizeof(MIPS_32R6M) - 1,
-			"MIPS-32R6 | Micro (Big-endian)"
-		},
-		{
-			CS_ARCH_MIPS,
-			(cs_mode)(CS_MODE_MIPS32R6 | CS_MODE_BIG_ENDIAN),
-			(unsigned char*)MIPS_32R6,
-			sizeof(MIPS_32R6) - 1,
-			"MIPS-32R6 (Big-endian)"
-		},
-		{
-			CS_ARCH_MIPS,
-			(cs_mode)(CS_MODE_MIPS64 | CS_MODE_MIPS2 | CS_MODE_LITTLE_ENDIAN),
-			(unsigned char *)MIPS_64SD,
-			sizeof(MIPS_64SD) - 1,
-			"MIPS-64-EL + Mips II (Little-endian)"
-		},
-		{
-			CS_ARCH_MIPS,
-			(cs_mode)(CS_MODE_MIPS64 | CS_MODE_LITTLE_ENDIAN),
-			(unsigned char *)MIPS_64SD,
-			sizeof(MIPS_64SD) - 1,
-			"MIPS-64-EL (Little-endian)"
-		},
-	};
-
-	uint64_t address = 0x1000;
-	cs_insn *insn;
-	int i;
-	size_t count;
-
-	for (i = 0; i < sizeof(platforms)/sizeof(platforms[0]); i++) {
-		cs_err err = cs_open(platforms[i].arch, platforms[i].mode, &handle);
-		if (err) {
-			printf("Failed on cs_open() with error returned: %u\n", err);
-			abort();
-		}
-
-		cs_option(handle, CS_OPT_DETAIL, CS_OPT_ON);
-
-		count = cs_disasm(handle, platforms[i].code, platforms[i].size, address, 0, &insn);
-		if (count) {
-			size_t j;
-
-			printf("****************\n");
-			printf("Platform: %s\n", platforms[i].comment);
-			print_string_hex("Code:", platforms[i].code, platforms[i].size);
-			printf("Disasm:\n");
-
-			for (j = 0; j < count; j++) {
-				printf("0x%" PRIx64 ":\t%s\t%s\n", insn[j].address, insn[j].mnemonic, insn[j].op_str);
-				print_insn_detail(&insn[j]);
-			}
-			printf("0x%" PRIx64 ":\n", insn[j-1].address + insn[j-1].size);
-
-			// free memory allocated by cs_disasm()
-			cs_free(insn, count);
-		} else {
-			printf("****************\n");
-			printf("Platform: %s\n", platforms[i].comment);
-			print_string_hex("Code:", platforms[i].code, platforms[i].size);
-			printf("ERROR: Failed to disasm given code!\n");
-			abort();
-		}
-
-		printf("\n");
-
-		cs_close(&handle);
-	}
-}
-
-int main()
-{
-	test();
-
-	return 0;
-}
diff --git a/tests/test_mos65xx.c b/tests/test_mos65xx.c
deleted file mode 100644
index bb53bea2e..000000000
--- a/tests/test_mos65xx.c
+++ /dev/null
@@ -1,230 +0,0 @@
-/* Capstone Disassembler Engine */
-/* By Sebastian Macke <sebastian@macke.de>, 2018 */
-
-#include <stdio.h>
-#include <stdlib.h>
-
-#include <capstone/platform.h>
-#include <capstone/capstone.h>
-
-struct platform {
-	cs_arch arch;
-	cs_mode mode;
-	unsigned char *code;
-	size_t size;
-	const char *comment;
-};
-
-static csh handle;
-
-static void print_string_hex(const char *comment, unsigned char *str, size_t len)
-{
-	unsigned char *c;
-
-	printf("%s", comment);
-	for (c = str; c < str + len; c++) {
-		printf("0x%02x ", *c & 0xff);
-	}
-
-	printf("\n");
-}
-
-static const char *get_am_name(mos65xx_address_mode mode)
-{
-	switch(mode) {
-		default:
-		case MOS65XX_AM_NONE:
-			return "No address mode";
-		case MOS65XX_AM_IMP:
-			return "implied";
-		case MOS65XX_AM_ACC:
-			return "accumulator";
-		case MOS65XX_AM_IMM:
-			return "immediate value";
-		case MOS65XX_AM_REL:
-			return "relative";
-		case MOS65XX_AM_INT:
-			return "interrupt signature";
-		case MOS65XX_AM_BLOCK:
-			return "block move";
-		case MOS65XX_AM_ZP:
-			return "zero page";
-		case MOS65XX_AM_ZP_X:
-			return "zero page indexed with x";
-		case MOS65XX_AM_ZP_Y:
-			return "zero page indexed with y";
-		case MOS65XX_AM_ZP_REL:
-			return "relative bit branch";
-		case MOS65XX_AM_ZP_IND:
-			return "zero page indirect";
-		case MOS65XX_AM_ZP_X_IND:
-			return "zero page indexed with x indirect";
-		case MOS65XX_AM_ZP_IND_Y:
-			return "zero page indirect indexed with y";
-		case MOS65XX_AM_ZP_IND_LONG:
-			return "zero page indirect long";
-		case MOS65XX_AM_ZP_IND_LONG_Y:
-			return "zero page indirect long indexed with y";
-		case MOS65XX_AM_ABS:
-			return "absolute";
-		case MOS65XX_AM_ABS_X:
-			return "absolute indexed with x";
-		case MOS65XX_AM_ABS_Y:
-			return "absolute indexed with y";
-		case MOS65XX_AM_ABS_IND:
-			return "absolute indirect";
-		case MOS65XX_AM_ABS_X_IND:
-			return "absolute indexed with x indirect";
-		case MOS65XX_AM_ABS_IND_LONG:
-			return "absolute indirect long";
-		case MOS65XX_AM_ABS_LONG:
-			return "absolute long";
-		case MOS65XX_AM_ABS_LONG_X:
-			return "absolute long indexed with x";
-		case MOS65XX_AM_SR:
-			return "stack relative";
-		case MOS65XX_AM_SR_IND_Y:
-			return "stack relative indirect indexed with y";
-	}
-}
-
-
-static void print_insn_detail(cs_insn *ins)
-{
-	cs_mos65xx *mos65xx;
-	int i;
-
-	// detail can be NULL on "data" instruction if SKIPDATA option is turned ON
-	if (ins->detail == NULL)
-		return;
-
-	mos65xx = &(ins->detail->mos65xx);
-
-	// printf("insn_detail\n");
-	printf("\taddress mode: %s\n", get_am_name(mos65xx->am));
-	printf("\tmodifies flags: %s\n", mos65xx->modifies_flags ? "true": "false");
-
-	if (mos65xx->op_count)
-		printf("\top_count: %u\n", mos65xx->op_count);
-
-	for (i = 0; i < mos65xx->op_count; i++) {
-		cs_mos65xx_op *op = &(mos65xx->operands[i]);
-		switch((int)op->type) {
-			default:
-				break;
-			case MOS65XX_OP_REG:
-				printf("\t\toperands[%u].type: REG = %s\n", i, cs_reg_name(handle, op->reg));
-				break;
-			case MOS65XX_OP_IMM:
-				printf("\t\toperands[%u].type: IMM = 0x%x\n", i, op->imm);
-				break;
-			case MOS65XX_OP_MEM:
-				printf("\t\toperands[%u].type: MEM = 0x%x\n", i, op->mem);
-				break;
-		}
-	}
-}
-
-static void test()
-{
-#define M6502_CODE "\xa1\x12\xa5\x12\xa9\x12\xad\x34\x12\xb1\x12\xb5\x12\xb9\x34\x12\xbd\x34\x12" \
-	"\x0d\x34\x12\x00\x81\x87\x6c\x01\x00\x85\xFF\x10\x00\x19\x42\x42\x00\x49\x42"
-
-#define M65C02_CODE "\x1a\x3a" \
-	"\x02\x12\x03\x5c\x34\x12"
-
-#define MW65C02_CODE \
-	"\x07\x12\x27\x12\x47\x12\x67\x12\x87\x12\xa7\x12\xc7\x12\xe7\x12" \
-	"\x10\xfe\x0f\x12\xfd\x4f\x12\xfd\x8f\x12\xfd\xcf\x12\xfd"
-
-#define M65816_CODE \
-	"\xa9\x34\x12" "\xad\x34\x12" "\xbd\x34\x12" "\xb9\x34\x12" \
-	"\xaf\x56\x34\x12" "\xbf\x56\x34\x12" \
-	"\xa5\x12" "\xb5\x12" "\xb2\x12" "\xa1\x12" "\xb1\x12" "\xa7\x12" "\xb7\x12" \
-	"\xa3\x12" "\xb3\x12" \
-	"\xc2\x00" "\xe2\x00" "\x54\x34\x12" "\x44\x34\x12" "\x02\x12"
-
-	struct platform platforms[] = {
-		{
-			CS_ARCH_MOS65XX,
-			(cs_mode)(CS_MODE_MOS65XX_6502),
-			(unsigned char *)M6502_CODE,
-			sizeof(M6502_CODE) - 1,
-			"MOS65XX_6502"
-		},
-		{
-			CS_ARCH_MOS65XX,
-			(cs_mode)(CS_MODE_MOS65XX_65C02),
-			(unsigned char *)M65C02_CODE,
-			sizeof(M65C02_CODE) - 1,
-			"MOS65XX_65C02"
-		},
-		{
-			CS_ARCH_MOS65XX,
-			(cs_mode)(CS_MODE_MOS65XX_W65C02),
-			(unsigned char *)MW65C02_CODE,
-			sizeof(MW65C02_CODE) - 1,
-			"MOS65XX_W65C02"
-		},
-		{
-			CS_ARCH_MOS65XX,
-			(cs_mode)(CS_MODE_MOS65XX_65816_LONG_MX),
-			(unsigned char *)M65816_CODE,
-			sizeof(M65816_CODE) - 1,
-			"MOS65XX_65816 (long m/x)"
-		},
-	};
-
-	uint64_t address = 0x1000;
-	cs_insn *insn;
-	int i;
-	size_t count;
-
-	for (i = 0; i < sizeof(platforms)/sizeof(platforms[0]); i++) {
-		cs_err err = cs_open(platforms[i].arch, platforms[i].mode, &handle);
-		if (err) {
-			printf("Failed on cs_open() with error returned: %u (%s)\n", err, cs_strerror(err));
-			abort();
-		}
-
-		cs_option(handle, CS_OPT_DETAIL, CS_OPT_ON);
-		cs_option(handle, CS_OPT_SYNTAX, CS_OPT_SYNTAX_MOTOROLA);
-
-		count = cs_disasm(handle, platforms[i].code, platforms[i].size, address, 0, &insn);
-
-		if (count) {
-			size_t j;
-
-			printf("****************\n");
-			printf("Platform: %s\n", platforms[i].comment);
-			print_string_hex("Code: ", platforms[i].code, platforms[i].size);
-			printf("Disasm:\n");
-
-			for (j = 0; j < count; j++) {
-				printf("0x%" PRIx64 ":\t%s\t%s\n", insn[j].address, insn[j].mnemonic, insn[j].op_str);
-				print_insn_detail(&insn[j]);
-				puts("");
-			}
-			printf("0x%" PRIx64 ":\n", insn[j-1].address + insn[j-1].size);
-
-			// free memory allocated by cs_disasm()
-			cs_free(insn, count);
-		} else {
-			printf("****************\n");
-			printf("Platform: %s\n", platforms[i].comment);
-			print_string_hex("Code:", platforms[i].code, platforms[i].size);
-			printf("ERROR: Failed to disasm given code!\n");
-			abort();
-		}
-
-		printf("\n");
-
-		cs_close(&handle);
-	}
-}
-
-int main()
-{
-	test();
-	return 0;
-}
diff --git a/tests/test_ppc.c b/tests/test_ppc.c
deleted file mode 100644
index 2a21cbe7c..000000000
--- a/tests/test_ppc.c
+++ /dev/null
@@ -1,178 +0,0 @@
-/* Capstone Disassembler Engine */
-/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
-
-#include <stdio.h>
-
-#include <capstone/platform.h>
-#include <capstone/capstone.h>
-
-struct platform {
-	cs_arch arch;
-	cs_mode mode;
-	unsigned char *code;
-	size_t size;
-	const char *comment;
-};
-
-static csh handle;
-
-static void print_string_hex(const char *comment, unsigned char *str, size_t len)
-{
-	unsigned char *c;
-
-	printf("%s", comment);
-	for (c = str; c < str + len; c++) {
-		printf("0x%02x ", *c & 0xff);
-	}
-
-	printf("\n");
-}
-
-static void print_insn_detail(cs_insn *ins)
-{
-	cs_ppc *ppc;
-	int i;
-
-	// detail can be NULL on "data" instruction if SKIPDATA option is turned ON
-	if (ins->detail == NULL)
-		return;
-
-	ppc = &(ins->detail->ppc);
-	if (ppc->op_count)
-		printf("\top_count: %u\n", ppc->op_count);
-
-	for (i = 0; i < ppc->op_count; i++) {
-		cs_ppc_op *op = &(ppc->operands[i]);
-		switch((int)op->type) {
-			default:
-				break;
-			case PPC_OP_REG:
-				printf("\t\toperands[%u].type: REG = %s\n", i, cs_reg_name(handle, op->reg));
-				break;
-			case PPC_OP_IMM:
-				printf("\t\toperands[%u].type: IMM = 0x%" PRIx64 "\n", i, op->imm);
-				break;
-			case PPC_OP_MEM:
-				printf("\t\toperands[%u].type: MEM\n", i);
-				if (op->mem.base != PPC_REG_INVALID)
-					printf("\t\t\toperands[%u].mem.base: REG = %s\n",
-							i, cs_reg_name(handle, op->mem.base));
-				if (op->mem.offset != 0)
-					printf("\t\t\toperands[%u].mem.offset: REG = %s\n",
-							i, cs_reg_name(handle, op->mem.offset));
-				if (op->mem.disp != 0)
-					printf("\t\t\toperands[%u].mem.disp: 0x%x\n", i, op->mem.disp);
-
-				break;
-		}
-		if (op->access == CS_AC_READ)
-			printf("\t\t\toperands[%u].access: READ\n", i);
-		else if (op->access == CS_AC_WRITE)
-			printf("\t\t\toperands[%u].access: WRITE\n", i);
-		else if (op->access == (CS_AC_READ | CS_AC_WRITE))
-			printf("\t\t\toperands[%u].access: READ | WRITE\n", i);
-	}
-
-	if (ppc->bc.pred_cr != PPC_PRED_INVALID || ppc->bc.pred_ctr != PPC_PRED_INVALID) {
-		printf("\tBranch:\n");
-		printf("\t\tbi: %u\n", ppc->bc.bi);
-		printf("\t\tbo: %u\n", ppc->bc.bo);
-		if (ppc->bc.bh != PPC_BH_INVALID)
-			printf("\t\tbh: %u\n", ppc->bc.bh);
-		if (ppc->bc.pred_cr != PPC_PRED_INVALID) {
-			printf("\t\tcrX: %s\n", cs_reg_name(handle, ppc->bc.crX));
-			printf("\t\tpred CR-bit: %u\n", ppc->bc.pred_cr);
-		}
-		if (ppc->bc.pred_ctr != PPC_PRED_INVALID)
-			printf("\t\tpred CTR: %u\n", ppc->bc.pred_ctr);
-		if (ppc->bc.hint != PPC_BR_NOT_GIVEN)
-			printf("\t\thint: %u\n", ppc->bc.hint);
-	}
-
-	if (ppc->update_cr0)
-		printf("\tUpdate-CR0: True\n");
-
-	printf("\n");
-}
-
-static void test()
-{
-#define PPC_CODE "\x43\x20\x0c\x07\x41\x56\xff\x17\x80\x20\x00\x00\x80\x3f\x00\x00\x10\x43\x23\x0e\xd0\x44\x00\x80\x4c\x43\x22\x02\x2d\x03\x00\x80\x7c\x43\x20\x14\x7c\x43\x20\x93\x4f\x20\x00\x21\x4c\xc8\x00\x21\x40\x82\x00\x14"
-#define PPC_CODE2 "\x10\x60\x2a\x10\x10\x64\x28\x88\x7c\x4a\x5d\x0f"
-#define PPC_CODE3 "\x10\x00\x1f\xec\xe0\x6d\x80\x04\xe4\x6d\x80\x04\x10\x60\x1c\x4c\x10\x60\x1c\x0c\xf0\x6d\x80\x04\xf4\x6d\x80\x04\x10\x60\x1c\x4e\x10\x60\x1c\x0e\x10\x60\x1a\x10\x10\x60\x1a\x11\x10\x63\x20\x2a\x10\x63\x20\x2b\x10\x83\x20\x40\x10\x83\x20\xC0\x10\x83\x20\x00\x10\x83\x20\x80\x10\x63\x20\x24\x10\x63\x20\x25\x10\x63\x29\x3a\x10\x63\x29\x3b\x10\x63\x29\x1c\x10\x63\x29\x1d\x10\x63\x29\x1e\x10\x63\x29\x1f\x10\x63\x24\x20\x10\x63\x24\x21\x10\x63\x24\x60\x10\x63\x24\x61\x10\x63\x24\xA0\x10\x63\x24\xA1\x10\x63\x24\xE0\x10\x63\x24\xE1\x10\x60\x20\x90\x10\x60\x20\x91\x10\x63\x29\x38\x10\x63\x29\x39\x10\x63\x01\x32\x10\x63\x01\x33\x10\x63\x01\x18\x10\x63\x01\x19\x10\x63\x01\x1A\x10\x63\x01\x1B\x10\x60\x19\x10\x10\x60\x19\x11\x10\x60\x18\x50\x10\x60\x18\x51\x10\x63\x29\x3e\x10\x63\x29\x3f\x10\x63\x29\x3c\x10\x63\x29\x3d\x10\x60\x18\x30\x10\x60\x18\x31\x10\x60\x18\x34\x10\x60\x18\x35\x10\x63\x29\x2e\x10\x63\x29\x2f\x10\x63\x20\x28\x10\x63\x20\x29\x10\x63\x29\x14\x10\x63\x29\x15\x10\x63\x29\x16\x10\x63\x29\x17"
-
-	struct platform platforms[] = {
-		{
-			CS_ARCH_PPC,
-			CS_MODE_BIG_ENDIAN,
-			(unsigned char*)PPC_CODE,
-			sizeof(PPC_CODE) - 1,
-			"PPC-64",
-		},
-		{
-			CS_ARCH_PPC,
-			(cs_mode)(CS_MODE_BIG_ENDIAN + CS_MODE_QPX),
-			(unsigned char*)PPC_CODE2,
-			sizeof(PPC_CODE2) - 1,
-			"PPC-64 + QPX",
-		},
-		{
-			CS_ARCH_PPC,
-			(cs_mode)(CS_MODE_BIG_ENDIAN + CS_MODE_PS),
-			(unsigned char*)PPC_CODE3,
-			sizeof(PPC_CODE3) - 1,
-			"PPC + PS",
-		},
-	};
-
-	uint64_t address = 0x1000;
-	cs_insn *insn;
-	int i;
-	size_t count;
-
-	for (i = 0; i < sizeof(platforms)/sizeof(platforms[0]); i++) {
-		cs_err err = cs_open(platforms[i].arch, platforms[i].mode, &handle);
-		if (err) {
-			printf("Failed on cs_open() with error returned: %u\n", err);
-			abort();
-		}
-
-		cs_option(handle, CS_OPT_DETAIL, CS_OPT_ON);
-
-		count = cs_disasm(handle, platforms[i].code, platforms[i].size, address, 0, &insn);
-		if (count) {
-			size_t j;
-
-			printf("****************\n");
-			printf("Platform: %s\n", platforms[i].comment);
-			print_string_hex("Code:", platforms[i].code, platforms[i].size);
-			printf("Disasm:\n");
-
-			for (j = 0; j < count; j++) {
-				printf("0x%" PRIx64 ":\t%s\t%s\n", insn[j].address, insn[j].mnemonic, insn[j].op_str);
-				print_insn_detail(&insn[j]);
-			}
-			printf("0x%" PRIx64 ":\n", insn[j-1].address + insn[j-1].size);
-
-			// free memory allocated by cs_disasm()
-			cs_free(insn, count);
-		} else {
-			printf("****************\n");
-			printf("Platform: %s\n", platforms[i].comment);
-			print_string_hex("Code:", platforms[i].code, platforms[i].size);
-			printf("ERROR: Failed to disasm given code!\n");
-			abort();
-		}
-
-		printf("\n");
-
-		cs_close(&handle);
-	}
-}
-
-int main()
-{
-	test();
-
-	return 0;
-}
diff --git a/tests/test_riscv.c b/tests/test_riscv.c
deleted file mode 100644
index 7da86e36f..000000000
--- a/tests/test_riscv.c
+++ /dev/null
@@ -1,176 +0,0 @@
-#include <stdio.h>
-#include <stdlib.h>
-
-#include <capstone/platform.h>
-#include <capstone/capstone.h>
-
-struct platform {
-	cs_arch arch;
-	cs_mode mode;
-	unsigned char *code;
-	size_t size;
-	const char *comment;
-};
-
-static csh handle;
-
-static void print_string_hex(const char *comment, unsigned char *str, size_t len)
-{
-	unsigned char *c;
-
-	printf("%s", comment);
-	for (c = str; c < str + len; c++) {
-		printf("0x%02x ", *c & 0xff);
-	}
-
-	printf("\n");
-}
-
-static void print_insn_detail(cs_insn *ins)
-{
-	int i;
-	int n;
-	cs_riscv *riscv;
-	cs_detail *detail;
-
-	// detail can be NULL on "data" instruction if SKIPDATA option is turned ON
-	if (ins->detail == NULL)
-		return;
-
-	riscv = &(ins->detail->riscv);
-	detail = ins->detail;
-	if (riscv->op_count)
-		printf("\top_count: %u\n", riscv->op_count);
-
-	for (i = 0; i < riscv->op_count; i++) {
-		cs_riscv_op *op = &(riscv->operands[i]);
-		switch((int)op->type) {
-			default:
-				printf("\terror in opt_type: %u\n", (int)op->type);
-				break;
-			case RISCV_OP_REG:
-				printf("\t\toperands[%u].type: REG = %s\n", i, cs_reg_name(handle, op->reg));
-				break;
-			case RISCV_OP_IMM:
-				printf("\t\toperands[%u].type: IMM = 0x%" PRIx64 "\n", i, op->imm);
-				break;
-			case RISCV_OP_MEM:
-				printf("\t\toperands[%u].type: MEM\n", i);
-				if (op->mem.base != RISCV_REG_INVALID)
-					printf("\t\t\toperands[%u].mem.base: REG = %s\n",
-							i, cs_reg_name(handle, op->mem.base));
-				if (op->mem.disp != 0)
-					printf("\t\t\toperands[%u].mem.disp: 0x%" PRIx64 "\n", i, op->mem.disp);
-
-				break;
-		}
-
-		switch(op->access) {
-			default:
-				break;
-			case CS_AC_READ:
-				printf("\t\toperands[%u].access: READ\n", i);
-				break;
-			case CS_AC_WRITE:
-				printf("\t\toperands[%u].access: WRITE\n", i);
-				break;
-			case CS_AC_READ | CS_AC_WRITE:
-				printf("\t\toperands[%u].access: READ | WRITE\n", i);
-				break;
-		}
-
-	}
-	
-	//print the groups this instruction belongs to
-	if (detail->groups_count > 0) {
-		printf("\tgroups: ");
-		for (n = 0; n < detail->groups_count; n++) {
-			printf("%s ", cs_group_name(handle, detail->groups[n]));
-		}
-		printf("\n");
-	}
-
-	printf("\n");
-}
-
-static void test()
-{
-#define RISCV_CODE32 "\x37\x34\x00\x00\x97\x82\x00\x00\xef\x00\x80\x00\xef\xf0\x1f\xff\xe7\x00\x45\x00\xe7\x00\xc0\xff\x63\x05\x41\x00\xe3\x9d\x61\xfe\x63\xca\x93\x00\x63\x53\xb5\x00\x63\x65\xd6\x00\x63\x76\xf7\x00\x03\x88\x18\x00\x03\x99\x49\x00\x03\xaa\x6a\x00\x03\xcb\x2b\x01\x03\xdc\x8c\x01\x23\x86\xad\x03\x23\x9a\xce\x03\x23\x8f\xef\x01\x93\x00\xe0\x00\x13\xa1\x01\x01\x13\xb2\x02\x7d\x13\xc3\x03\xdd\x13\xe4\xc4\x12\x13\xf5\x85\x0c\x13\x96\xe6\x01\x13\xd7\x97\x01\x13\xd8\xf8\x40\x33\x89\x49\x01\xb3\x0a\x7b\x41\x33\xac\xac\x01\xb3\x3d\xde\x01\x33\xd2\x62\x40\xb3\x43\x94\x00\x33\xe5\xc5\x00\xb3\x76\xf7\x00\xb3\x54\x39\x01\xb3\x50\x31\x00\x33\x9f\x0f\x00\x73\x15\x04\xb0\xf3\x56\x00\x10\x33\x05\x7b\x03\xb3\x45\x9c\x03\x33\x66\xbd\x03\x2f\xa4\x02\x10\xaf\x23\x65\x18\x2f\x27\x2f\x01\x43\xf0\x20\x18\xd3\x72\x73\x00\x53\xf4\x04\x58\x53\x85\xc5\x28\x53\x2e\xde\xa1\xd3\x84\x05\xf0\x53\x06\x05\xe0\x53\x75\x00\xc0\xd3\xf0\x05\xd0\xd3\x15\x08\xe0\x87\xaa\x75\x00\x27\x27\x66\x01\x43\xf0\x20\x1a\xd3\x72\x73\x02\x53\xf4\x04\x5a\x53\x85\xc5\x2a\x53\x2e\xde\xa3"
-#define RISCV_CODE64 "\x13\x04\xa8\x7a\xbb\x07\x9c\x02\xbb\x40\x5d\x02\x3b\x63\xb7\x03\x2f\xb4\x02\x10\xaf\x33\x65\x18\x2f\x37\x2f\x01\x53\x75\x20\xc0\xd3\xf0\x25\xd0\xd3\x84\x05\xf2\x53\x06\x05\xe2\x53\x75\x00\xc2\xd3\x80\x05\xd2\xd3\x15\x08\xe2\x87\xba\x75\x00\x27\x37\x66\x01"
-#define RISCV_CODEC "\xe8\x1f\x7d\x61\x80\x25\x00\x46\x88\xa2\x04\xcb\x55\x13\xf2\x93\x5d\x45\x19\x80\x15\x68\x2a\xa4\x62\x24\xa6\xff\x2a\x65\x76\x86\x65\xdd\x01\x00\xfd\xaf\x82\x82\x11\x20\x82\x94"
-	struct platform platforms[] = {
-		{
-			CS_ARCH_RISCV,
-			CS_MODE_RISCV32,
-			(unsigned char *)RISCV_CODE32,
-			sizeof(RISCV_CODE32) - 1,
-			"riscv32"
-		},
-		{
-			CS_ARCH_RISCV,
-			CS_MODE_RISCV64,
-			(unsigned char *)RISCV_CODE64,
-			sizeof(RISCV_CODE64) - 1,
-			"riscv64"
-		},
-		{
-			CS_ARCH_RISCV,
-			CS_MODE_RISCVC,
-			(unsigned char *)RISCV_CODEC,
-			sizeof(RISCV_CODEC) - 1,
-			"riscvc"
-		}
-	};
-	
-	uint64_t address = 0x1000;
-	cs_insn *insn;
-	int i;
-	size_t count;
-
-	for (i = 0; i < sizeof(platforms)/sizeof(platforms[0]); i++) {
-		cs_err err = cs_open(platforms[i].arch, platforms[i].mode, &handle);
-		if (err) {
-			printf("Failed on cs_open() with error returned: %u\n", err);
-			continue;
-		}
-		
-		//To turn on or off the Print Details option
-		//cs_option(handle, CS_OPT_DETAIL, CS_OPT_OFF); 
-		cs_option(handle, CS_OPT_DETAIL, CS_OPT_ON);
-
-		count = cs_disasm(handle, platforms[i].code, platforms[i].size, address, 0, &insn);
-		if (count) {
-			size_t j;
-
-			printf("****************\n");
-			printf("Platform: %s\n", platforms[i].comment);
-			print_string_hex("Code:", platforms[i].code, platforms[i].size);
-			printf("Disasm:\n");
-
-			for (j = 0; j < count; j++) {
-				printf("0x%" PRIx64 ":\t%s\t%s\n", insn[j].address, insn[j].mnemonic, insn[j].op_str);
-				print_insn_detail(&insn[j]);
-			}
-			printf("0x%" PRIx64 ":\n", insn[j-1].address + insn[j-1].size);
-
-			// free memory allocated by cs_disasm()
-			cs_free(insn, count);
-		} else {
-			printf("****************\n");
-			printf("Platform: %s\n", platforms[i].comment);
-			print_string_hex("Code:", platforms[i].code, platforms[i].size);
-			printf("ERROR: Failed to disasm given code!\n");
-		}
-
-		printf("\n");
-
-		cs_close(&handle);
-	}
-}
-
-int main()
-{
-	test();
-
-	return 0;
-}
diff --git a/tests/test_sh.c b/tests/test_sh.c
deleted file mode 100644
index de49fa016..000000000
--- a/tests/test_sh.c
+++ /dev/null
@@ -1,253 +0,0 @@
-/* Capstone Disassembler Engine */
-/* SuperH Backend by Yoshinori Sato <ysato@users.sourceforge.jp> */
-
-#include <stdio.h>
-#include <string.h>
-
-#include <capstone/platform.h>
-#include <capstone/capstone.h>
-
-#define WITH_DETAILS
-
-struct platform {
-	cs_arch arch;
-	cs_mode mode;
-	unsigned char *code;
-	size_t size;
-	const char *comment;
-};
-
-static void print_string_hex(const char *comment, unsigned char *str, size_t len)
-{
-	unsigned char *c;
-
-	printf("%s", comment);
-
-	for (c = str; c < str + len; c++)
-		printf("0x%02x ", *c & 0xff);
-
-	printf("\n");
-}
-
-static void print_read_write_regs(csh handle, cs_detail *detail)
-{
-	int i;
-
-	if (detail->regs_read_count > 0) {
-		printf("\tRegisters read:");
-
-		for (i = 0; i < detail->regs_read_count; ++i)
-			printf(" %s",
-				cs_reg_name(handle, detail->regs_read[i]));
-
-		printf("\n");
-	}
-
-	if (detail->regs_write_count > 0) {
-		printf("\tRegisters modified:");
-
-		for (i = 0; i < detail->regs_write_count; ++i)
-			printf(" %s",
-				cs_reg_name(handle, detail->regs_write[i]));
-
-		printf("\n");
-	}
-}
-
-static char *reg_address_msg[] = {
-	"Register indirect",
-	"Register indirect with predecrement",
-	"Register indirect with postincrement",
-};
-
-static void print_insn_detail(csh handle, cs_insn *insn)
-{
-	cs_detail *detail = insn->detail;
-	cs_sh *sh = NULL;
-	int i;
-	int n;
-
-	// detail can be NULL on "data" instruction if SKIPDATA option is turned ON
-	if (detail == NULL)
-		return;
-
-	sh = &detail->sh;
-
-	if (sh->op_count)
-		printf("\top_count: %u\n", sh->op_count);
-
-	for (i = 0; i < sh->op_count; i++) {
-		cs_sh_op *op = &(sh->operands[i]);
-
-		switch ((int)op->type) {
-		default:
-			break;
-
-		case SH_OP_REG:
-			printf("\t\toperands[%u].type: REGISTER = %s\n", i,
-				cs_reg_name(handle, op->reg));
-			break;
-
-		case SH_OP_IMM:
-			printf("\t\toperands[%u].type: IMMEDIATE = #%" PRIu64 "\n", i,
-			       op->imm);
-			break;
-
-		case SH_OP_MEM:
-			printf("\t\toperands[%u].type: MEM ", i);
-			switch(op->mem.address) {
-			case SH_OP_MEM_REG_IND:
-			case SH_OP_MEM_REG_POST:
-			case SH_OP_MEM_REG_PRE:
-				printf("%s REG %s\n",
-				       reg_address_msg[op->mem.address - SH_OP_MEM_REG_IND],
-				       cs_reg_name(handle, op->mem.reg));
-				break;
-			case SH_OP_MEM_REG_DISP:
-				printf("Register indirect with displacement REG %s, DISP %d\n",
-				       cs_reg_name(handle, op->mem.reg),
-				       op->mem.disp);
-				break;
-				
-			case SH_OP_MEM_REG_R0:
-				printf("R0 indexed\n");
-				break;
-				
-			case SH_OP_MEM_GBR_DISP:
-				printf("GBR base with displacement DISP %d\n",
-				       op->mem.disp);
-				break;
-				
-			case SH_OP_MEM_GBR_R0:
-				printf("GBR base with R0 indexed\n");
-				break;
-
-			case SH_OP_MEM_PCR:
-				printf("PC relative Address=0x%08x\n",
-				       op->mem.disp);
-				break;
-
-			case SH_OP_MEM_TBR_DISP:
-				printf("TBR base with displacement DISP %d\n",
-				       op->mem.disp);
-				break;
-			case SH_OP_MEM_INVALID:
-				break;
-			}
-			break;
-		}
-
-		if (sh->size != 0)
-			printf("\t\t\tsize: %u\n", sh->size);
-
-	}
-
-	print_read_write_regs(handle, detail);
-
-	if (detail->groups_count > 0) {
-		printf("\tgroups: ");
-		for (n = 0; n < detail->groups_count; n++) {
-			printf("%s ", cs_group_name(handle, detail->groups[n]));
-		}
-		printf("\n");
-	}
-
-	printf("\n");
-}
-
-static bool consistency_checks()
-{
-	return true;
-}
-
-static void test()
-{
-#define SH4A_CODE \
-  "\x0c\x31\x10\x20\x22\x21\x36\x64\x46\x25\x12\x12\x1c\x02\x08\xc1\x05\xc7\x0c" \
-  "\x71\x1f\x02\x22\xcf\x06\x89\x23\x00\x2b\x41\x0b\x00\x0e\x40\x32\x00\x0a\xf1\x09\x00"
-
-#define SH2A_CODE \
-  "\x32\x11\x92\x00\x32\x49\x31\x00"
-
-	struct platform platforms[] = {
-		{
-			CS_ARCH_SH,
-			(cs_mode)(CS_MODE_SH4A | CS_MODE_SHFPU),
-			(unsigned char *)SH4A_CODE,
-			sizeof(SH4A_CODE) - 1,
-			"SH_SH4A",
-		},
-		{
-			CS_ARCH_SH,
-			(cs_mode)(CS_MODE_SH2A | CS_MODE_SHFPU | CS_MODE_BIG_ENDIAN),
-			(unsigned char *)SH2A_CODE,
-			sizeof(SH2A_CODE) - 1,
-			"SH_SH2A",
-		},
-	};
-
-	uint64_t address = 0x80000000;
-	csh handle;
-	cs_insn *insn;
-	int i;
-	size_t count;
-
-	if (!consistency_checks())
-		abort();
-
-	for (i = 0; i < sizeof(platforms) / sizeof(platforms[0]); i++) {
-		cs_err err = cs_open(platforms[i].arch, platforms[i].mode,
-				&handle);
-
-		if (err) {
-			printf("Failed on cs_open() with error returned: %u\n",
-				err);
-			abort();
-		}
-
-#ifdef WITH_DETAILS
-		cs_option(handle, CS_OPT_DETAIL, CS_OPT_ON);
-#endif
-
-		count = cs_disasm(handle, platforms[i].code, platforms[i].size,
-				address, 0, &insn);
-
-		if (count) {
-			size_t j;
-
-			printf("****************\n");
-			printf("Platform: %s\n", platforms[i].comment);
-			print_string_hex("Code: ", platforms[i].code,
-				platforms[i].size);
-			printf("Disasm:\n");
-
-			for (j = 0; j < count; j++) {
-				printf("0x%"PRIx64":\t%s\t%s\n", insn[j].address, insn[j].mnemonic, insn[j].op_str);
-#ifdef WITH_DETAILS
-				print_insn_detail(handle, &insn[j]);
-#endif
-			}
-			printf("0x%" PRIx64 ":\n", insn[j-1].address + insn[j-1].size);
-
-			// free memory allocated by cs_disasm()
-			cs_free(insn, count);
-		}
-		else {
-			printf("****************\n");
-			printf("Platform: %s\n", platforms[i].comment);
-			print_string_hex("Code:", platforms[i].code,
-				platforms[i].size);
-			printf("ERROR: Failed to disasm given code!\n");
-			abort();
-		}
-
-		cs_close(&handle);
-	}
-}
-
-int main()
-{
-	test();
-
-	return 0;
-}
diff --git a/tests/test_sparc.c b/tests/test_sparc.c
deleted file mode 100644
index 98c39494e..000000000
--- a/tests/test_sparc.c
+++ /dev/null
@@ -1,152 +0,0 @@
-/* Capstone Disassembler Engine */
-/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
-
-#include <stdio.h>
-
-#include <capstone/platform.h>
-#include <capstone/capstone.h>
-
-struct platform {
-	cs_arch arch;
-	cs_mode mode;
-	unsigned char *code;
-	size_t size;
-	const char *comment;
-};
-
-static csh handle;
-
-static void print_string_hex(const char *comment, unsigned char *str, size_t len)
-{
-	unsigned char *c;
-
-	printf("%s", comment);
-	for (c = str; c < str + len; c++) {
-		printf("0x%02x ", *c & 0xff);
-	}
-
-	printf("\n");
-}
-
-static void print_insn_detail(cs_insn *ins)
-{
-	cs_sparc *sparc;
-	int i;
-
-	// detail can be NULL on "data" instruction if SKIPDATA option is turned ON
-	if (ins->detail == NULL)
-		return;
-
-	sparc = &(ins->detail->sparc);
-	if (sparc->op_count)
-		printf("\top_count: %u\n", sparc->op_count);
-
-	for (i = 0; i < sparc->op_count; i++) {
-		cs_sparc_op *op = &(sparc->operands[i]);
-		switch((int)op->type) {
-			default:
-				break;
-			case SPARC_OP_REG:
-				printf("\t\toperands[%u].type: REG = %s\n", i, cs_reg_name(handle, op->reg));
-				break;
-			case SPARC_OP_IMM:
-				printf("\t\toperands[%u].type: IMM = 0x%" PRIx64 "\n", i, op->imm);
-				break;
-			case SPARC_OP_MEM:
-				printf("\t\toperands[%u].type: MEM\n", i);
-				if (op->mem.base != X86_REG_INVALID)
-					printf("\t\t\toperands[%u].mem.base: REG = %s\n",
-							i, cs_reg_name(handle, op->mem.base));
-				if (op->mem.index != X86_REG_INVALID)
-					printf("\t\t\toperands[%u].mem.index: REG = %s\n",
-							i, cs_reg_name(handle, op->mem.index));
-				if (op->mem.disp != 0)
-					printf("\t\t\toperands[%u].mem.disp: 0x%x\n", i, op->mem.disp);
-
-				break;
-		}
-	}
-
-	if (sparc->cc != 0)
-		printf("\tCode condition: %u\n", sparc->cc);
-
-	if (sparc->hint != 0)
-		printf("\tHint code: %u\n", sparc->hint);
-
-	printf("\n");
-}
-
-static void test()
-{
-#define SPARC_CODE "\x80\xa0\x40\x02\x85\xc2\x60\x08\x85\xe8\x20\x01\x81\xe8\x00\x00\x90\x10\x20\x01\xd5\xf6\x10\x16\x21\x00\x00\x0a\x86\x00\x40\x02\x01\x00\x00\x00\x12\xbf\xff\xff\x10\xbf\xff\xff\xa0\x02\x00\x09\x0d\xbf\xff\xff\xd4\x20\x60\x00\xd4\x4e\x00\x16\x2a\xc2\x80\x03"
-
-#define SPARCV9_CODE "\x81\xa8\x0a\x24\x89\xa0\x10\x20\x89\xa0\x1a\x60\x89\xa0\x00\xe0"
-
-	struct platform platforms[] = {
-		{
-			CS_ARCH_SPARC,
-			CS_MODE_BIG_ENDIAN,
-			(unsigned char*)SPARC_CODE,
-			sizeof(SPARC_CODE) - 1,
-			"Sparc",
-		},
-		{
-			CS_ARCH_SPARC,
-			(cs_mode)(CS_MODE_BIG_ENDIAN + CS_MODE_V9),
-			(unsigned char*)SPARCV9_CODE,
-			sizeof(SPARCV9_CODE) - 1,
-			"SparcV9"
-		},
-	};
-
-	uint64_t address = 0x1000;
-	cs_insn *insn;
-	int i;
-	size_t count;
-
-	for (i = 0; i < sizeof(platforms)/sizeof(platforms[0]); i++) {
-		cs_err err = cs_open(platforms[i].arch, platforms[i].mode, &handle);
-		if (err) {
-			printf("Failed on cs_open() with error returned: %u\n", err);
-			abort();
-		}
-
-		cs_option(handle, CS_OPT_DETAIL, CS_OPT_ON);
-
-		count = cs_disasm(handle, platforms[i].code, platforms[i].size, address, 0, &insn);
-		if (count) {
-			size_t j;
-
-			printf("****************\n");
-			printf("Platform: %s\n", platforms[i].comment);
-			print_string_hex("Code:", platforms[i].code, platforms[i].size);
-			printf("Disasm:\n");
-
-			for (j = 0; j < count; j++) {
-				printf("0x%" PRIx64 ":\t%s\t%s\n", insn[j].address, insn[j].mnemonic, insn[j].op_str);
-				print_insn_detail(&insn[j]);
-			}
-			printf("0x%" PRIx64 ":\n", insn[j-1].address + insn[j-1].size);
-
-			// free memory allocated by cs_disasm()
-			cs_free(insn, count);
-		} else {
-			printf("****************\n");
-			printf("Platform: %s\n", platforms[i].comment);
-			print_string_hex("Code:", platforms[i].code, platforms[i].size);
-			printf("ERROR: Failed to disasm given code!\n");
-			abort();
-		}
-
-		printf("\n");
-
-		cs_close(&handle);
-	}
-}
-
-int main()
-{
-	test();
-
-	return 0;
-}
diff --git a/tests/test_systemz.c b/tests/test_systemz.c
deleted file mode 100644
index f662247b8..000000000
--- a/tests/test_systemz.c
+++ /dev/null
@@ -1,145 +0,0 @@
-/* Capstone Disassembler Engine */
-/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
-
-#include <stdio.h>
-
-#include <capstone/platform.h>
-#include <capstone/capstone.h>
-
-struct platform {
-	cs_arch arch;
-	cs_mode mode;
-	unsigned char *code;
-	size_t size;
-	const char *comment;
-};
-
-static csh handle;
-
-static void print_string_hex(const char *comment, unsigned char *str, size_t len)
-{
-	unsigned char *c;
-
-	printf("%s", comment);
-	for (c = str; c < str + len; c++) {
-		printf("0x%02x ", *c & 0xff);
-	}
-
-	printf("\n");
-}
-
-static void print_insn_detail(cs_insn *ins)
-{
-	cs_sysz *sysz;
-	int i;
-
-	// detail can be NULL on "data" instruction if SKIPDATA option is turned ON
-	if (ins->detail == NULL)
-		return;
-
-	sysz = &(ins->detail->sysz);
-	if (sysz->op_count)
-		printf("\top_count: %u\n", sysz->op_count);
-
-	for (i = 0; i < sysz->op_count; i++) {
-		cs_sysz_op *op = &(sysz->operands[i]);
-		switch((int)op->type) {
-			default:
-				break;
-			case SYSZ_OP_REG:
-				printf("\t\toperands[%u].type: REG = %s\n", i, cs_reg_name(handle, op->reg));
-				break;
-			case SYSZ_OP_ACREG:
-				printf("\t\toperands[%u].type: ACREG = %u\n", i, op->reg);
-				break;
-			case SYSZ_OP_IMM:
-				printf("\t\toperands[%u].type: IMM = 0x%" PRIx64 "\n", i, op->imm);
-				break;
-			case SYSZ_OP_MEM:
-				printf("\t\toperands[%u].type: MEM\n", i);
-				if (op->mem.base != SYSZ_REG_INVALID)
-					printf("\t\t\toperands[%u].mem.base: REG = %s\n",
-							i, cs_reg_name(handle, op->mem.base));
-				if (op->mem.index != SYSZ_REG_INVALID)
-					printf("\t\t\toperands[%u].mem.index: REG = %s\n",
-							i, cs_reg_name(handle, op->mem.index));
-				if (op->mem.length != 0)
-					printf("\t\t\toperands[%u].mem.length: 0x%" PRIx64 "\n", i, op->mem.length);
-				if (op->mem.disp != 0)
-					printf("\t\t\toperands[%u].mem.disp: 0x%" PRIx64 "\n", i, op->mem.disp);
-
-				break;
-		}
-	}
-
-	if (sysz->cc != 0)
-		printf("\tCode condition: %u\n", sysz->cc);
-
-	printf("\n");
-}
-
-static void test()
-{
-#define SYSZ_CODE "\xed\x00\x00\x00\x00\x1a\x5a\x0f\x1f\xff\xc2\x09\x80\x00\x00\x00\x07\xf7\xeb\x2a\xff\xff\x7f\x57\xe3\x01\xff\xff\x7f\x57\xeb\x00\xf0\x00\x00\x24\xb2\x4f\x00\x78\xec\x18\x00\x00\xc1\x7f"
-
-	struct platform platforms[] = {
-		{
-			CS_ARCH_SYSZ,
-			CS_MODE_BIG_ENDIAN,
-			(unsigned char*)SYSZ_CODE,
-			sizeof(SYSZ_CODE) - 1,
-			"SystemZ",
-		},
-	};
-
-	uint64_t address = 0x1000;
-	cs_insn *insn;
-	int i;
-	size_t count;
-
-	for (i = 0; i < sizeof(platforms)/sizeof(platforms[0]); i++) {
-		cs_err err = cs_open(platforms[i].arch, platforms[i].mode, &handle);
-		if (err) {
-			printf("Failed on cs_open() with error returned: %u\n", err);
-			abort();
-		}
-
-		cs_option(handle, CS_OPT_DETAIL, CS_OPT_ON);
-
-		count = cs_disasm(handle, platforms[i].code, platforms[i].size, address, 0, &insn);
-		if (count) {
-			size_t j;
-
-			printf("****************\n");
-			printf("Platform: %s\n", platforms[i].comment);
-			print_string_hex("Code:", platforms[i].code, platforms[i].size);
-			printf("Disasm:\n");
-
-			for (j = 0; j < count; j++) {
-				printf("0x%" PRIx64 ":\t%s\t%s\n", insn[j].address, insn[j].mnemonic, insn[j].op_str);
-				print_insn_detail(&insn[j]);
-			}
-			printf("0x%" PRIx64 ":\n", insn[j-1].address + insn[j-1].size);
-
-			// free memory allocated by cs_disasm()
-			cs_free(insn, count);
-		} else {
-			printf("****************\n");
-			printf("Platform: %s\n", platforms[i].comment);
-			print_string_hex("Code:", platforms[i].code, platforms[i].size);
-			printf("ERROR: Failed to disasm given code!\n");
-			abort();
-		}
-
-		printf("\n");
-
-		cs_close(&handle);
-	}
-}
-
-int main()
-{
-	test();
-
-	return 0;
-}
diff --git a/tests/test_tms320c64x.c b/tests/test_tms320c64x.c
deleted file mode 100644
index 28bc05e28..000000000
--- a/tests/test_tms320c64x.c
+++ /dev/null
@@ -1,193 +0,0 @@
-/* Capstone Disassembly Engine */
-/* TMS320C64x Backend by Fotis Loukos <me@fotisl.com> 2016 */
-
-#include <stdio.h>
-
-#include <capstone/capstone.h>
-
-struct platform {
-	cs_arch arch;
-	cs_mode mode;
-	unsigned char *code;
-	size_t size;
-	const char *comment;
-};
-
-static csh handle;
-
-static void print_string_hex(const char *comment, unsigned char *str, size_t len)
-{
-	unsigned char *c;
-
-	printf("%s", comment);
-	for (c = str; c < str + len; c++) {
-		printf("0x%02x ", *c & 0xff);
-	}
-
-	printf("\n");
-}
-
-static void print_insn_detail(cs_insn *ins)
-{
-	cs_tms320c64x *tms320c64x;
-	int i;
-
-	// detail can be NULL on "data" instruction if SKIPDATA option is turned ON
-	if (ins->detail == NULL)
-		return;
-
-	tms320c64x = &(ins->detail->tms320c64x);
-	if (tms320c64x->op_count)
-		printf("\top_count: %u\n", tms320c64x->op_count);
-
-	for (i = 0; i < tms320c64x->op_count; i++) {
-		cs_tms320c64x_op *op = &(tms320c64x->operands[i]);
-		switch((int)op->type) {
-			default:
-				break;
-			case TMS320C64X_OP_REG:
-				printf("\t\toperands[%u].type: REG = %s\n", i, cs_reg_name(handle, op->reg));
-				break;
-			case TMS320C64X_OP_IMM:
-				printf("\t\toperands[%u].type: IMM = 0x%x\n", i, op->imm);
-				break;
-			case TMS320C64X_OP_MEM:
-				printf("\t\toperands[%u].type: MEM\n", i);
-				if (op->mem.base != TMS320C64X_REG_INVALID)
-					printf("\t\t\toperands[%u].mem.base: REG = %s\n",
-							i, cs_reg_name(handle, op->mem.base));
-				printf("\t\t\toperands[%u].mem.disptype: ", i);
-				if(op->mem.disptype == TMS320C64X_MEM_DISP_INVALID) {
-					printf("Invalid\n");
-					printf("\t\t\toperands[%u].mem.disp: 0x%x\n", i, op->mem.disp);
-				}
-				if(op->mem.disptype == TMS320C64X_MEM_DISP_CONSTANT) {
-					printf("Constant\n");
-					printf("\t\t\toperands[%u].mem.disp: 0x%x\n", i, op->mem.disp);
-				}
-				if(op->mem.disptype == TMS320C64X_MEM_DISP_REGISTER) {
-					printf("Register\n");
-					printf("\t\t\toperands[%u].mem.disp: %s\n", i, cs_reg_name(handle, op->mem.disp));
-				}
-				printf("\t\t\toperands[%u].mem.unit: %u\n", i, op->mem.unit);
-				printf("\t\t\toperands[%u].mem.direction: ", i);
-				if(op->mem.direction == TMS320C64X_MEM_DIR_INVALID)
-					printf("Invalid\n");
-				if(op->mem.direction == TMS320C64X_MEM_DIR_FW)
-					printf("Forward\n");
-				if(op->mem.direction == TMS320C64X_MEM_DIR_BW)
-					printf("Backward\n");
-				printf("\t\t\toperands[%u].mem.modify: ", i);
-				if(op->mem.modify == TMS320C64X_MEM_MOD_INVALID)
-					printf("Invalid\n");
-				if(op->mem.modify == TMS320C64X_MEM_MOD_NO)
-					printf("No\n");
-				if(op->mem.modify == TMS320C64X_MEM_MOD_PRE)
-					printf("Pre\n");
-				if(op->mem.modify == TMS320C64X_MEM_MOD_POST)
-					printf("Post\n");
-				printf("\t\t\toperands[%u].mem.scaled: %u\n", i, op->mem.scaled);
-
-
-				break;
-			case TMS320C64X_OP_REGPAIR:
-				printf("\t\toperands[%u].type: REGPAIR = %s:%s\n", i, cs_reg_name(handle, op->reg + 1), cs_reg_name(handle, op->reg));
-				break;
-		}
-	}
-
-	printf("\tFunctional unit: ");
-	switch(tms320c64x->funit.unit) {
-		case TMS320C64X_FUNIT_D:
-			printf("D%u\n", tms320c64x->funit.side);
-			break;
-		case TMS320C64X_FUNIT_L:
-			printf("L%u\n", tms320c64x->funit.side);
-			break;
-		case TMS320C64X_FUNIT_M:
-			printf("M%u\n", tms320c64x->funit.side);
-			break;
-		case TMS320C64X_FUNIT_S:
-			printf("S%u\n", tms320c64x->funit.side);
-			break;
-		case TMS320C64X_FUNIT_NO:
-			printf("No Functional Unit\n");
-			break;
-		default:
-			printf("Unknown (Unit %u, Side %u)\n", tms320c64x->funit.unit, tms320c64x->funit.side);
-			break;
-	}
-	if(tms320c64x->funit.crosspath == 1)
-		printf("\tCrosspath: 1\n");
-
-	if(tms320c64x->condition.reg != TMS320C64X_REG_INVALID)
-		printf("\tCondition: [%c%s]\n", (tms320c64x->condition.zero == 1) ? '!' : ' ', cs_reg_name(handle, tms320c64x->condition.reg));
-	printf("\tParallel: %s\n", (tms320c64x->parallel == 1) ? "true" : "false");
-
-	printf("\n");
-}
-
-static void test()
-{
-#define TMS320C64X_CODE "\x01\xac\x88\x40\x81\xac\x88\x43\x00\x00\x00\x00\x02\x90\x32\x96\x02\x80\x46\x9e\x05\x3c\x83\xe6\x0b\x0c\x8b\x24"
-
-	struct platform platforms[] = {
-		{
-			CS_ARCH_TMS320C64X,
-			CS_MODE_BIG_ENDIAN,
-			(unsigned char*)TMS320C64X_CODE,
-			sizeof(TMS320C64X_CODE) - 1,
-			"TMS320C64x",
-		},
-	};
-
-	uint64_t address = 0x1000;
-	cs_insn *insn;
-	int i;
-	size_t count;
-
-	for (i = 0; i < sizeof(platforms)/sizeof(platforms[0]); i++) {
-		cs_err err = cs_open(platforms[i].arch, platforms[i].mode, &handle);
-		if (err) {
-			printf("Failed on cs_open() with error returned: %u\n", err);
-			continue;
-		}
-
-		cs_option(handle, CS_OPT_DETAIL, CS_OPT_ON);
-
-		count = cs_disasm(handle, platforms[i].code, platforms[i].size, address, 0, &insn);
-		if (count) {
-			size_t j;
-
-			printf("****************\n");
-			printf("Platform: %s\n", platforms[i].comment);
-			print_string_hex("Code:", platforms[i].code, platforms[i].size);
-			printf("Disasm:\n");
-
-			for (j = 0; j < count; j++) {
-				printf("0x%"PRIx64":\t%s\t%s\n", insn[j].address, insn[j].mnemonic, insn[j].op_str);
-				print_insn_detail(&insn[j]);
-			}
-			printf("0x%"PRIx64":\n", insn[j-1].address + insn[j-1].size);
-
-			// free memory allocated by cs_disasm()
-			cs_free(insn, count);
-		} else {
-			printf("****************\n");
-			printf("Platform: %s\n", platforms[i].comment);
-			print_string_hex("Code:", platforms[i].code, platforms[i].size);
-			printf("ERROR: Failed to disasm given code!\n");
-		}
-
-		printf("\n");
-
-		cs_close(&handle);
-	}
-}
-
-int main()
-{
-	test();
-
-	return 0;
-}
diff --git a/tests/test_tricore.c b/tests/test_tricore.c
deleted file mode 100644
index 38e71ba6e..000000000
--- a/tests/test_tricore.c
+++ /dev/null
@@ -1,145 +0,0 @@
-/* Capstone Disassembler Engine */
-/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
-
-#include <stdio.h>
-
-#include <capstone/platform.h>
-#include <capstone/capstone.h>
-
-struct platform {
-	cs_arch arch;
-	cs_mode mode;
-	unsigned char *code;
-	size_t size;
-	char *comment;
-};
-
-static csh handle;
-
-static void print_string_hex(char *comment, unsigned char *str, size_t len)
-{
-	unsigned char *c;
-
-	printf("%s", comment);
-	for (c = str; c < str + len; c++) {
-		printf("0x%02x ", *c & 0xff);
-	}
-
-	printf("\n");
-}
-
-static void print_insn_detail(cs_insn *ins)
-{
-	cs_tricore *tricore;
-	int i;
-
-	// detail can be NULL on "data" instruction if SKIPDATA option is turned ON
-	if (ins->detail == NULL)
-		return;
-
-	tricore = &(ins->detail->tricore);
-	if (tricore->op_count)
-		printf("\top_count: %u\n", tricore->op_count);
-
-	for (i = 0; i < tricore->op_count; i++) {
-		cs_tricore_op *op = &(tricore->operands[i]);
-		switch ((int)op->type) {
-		default:
-			break;
-		case TRICORE_OP_REG:
-			printf("\t\toperands[%u].type: REG = %s\n", i,
-			       cs_reg_name(handle, op->reg));
-			break;
-		case TRICORE_OP_IMM:
-			printf("\t\toperands[%u].type: IMM = 0x%" PRIx64 "\n",
-			       i, op->imm);
-			break;
-		case TRICORE_OP_MEM:
-			printf("\t\toperands[%u].type: MEM\n", i);
-			if (op->mem.base != TRICORE_REG_INVALID)
-				printf("\t\t\toperands[%u].mem.base: REG = %s\n",
-				       i, cs_reg_name(handle, op->mem.base));
-			if (op->mem.disp != 0)
-				printf("\t\t\toperands[%u].mem.disp: 0x%" PRIx64
-				       "\n",
-				       i, op->mem.disp);
-
-			break;
-		}
-	}
-
-	printf("\n");
-}
-
-static void test()
-{
-//#define TRICORE_CODE "\x16\x01\x20\x01\x1d\x00\x02\x00\x8f\x70\x00\x11\x40\xae\x89\xee\x04\x09\x42\xf2\xe2\xf2\xc2\x11\x19\xff\xc0\x70\x19\xff\x20\x10"
-#define TRICORE_CODE \
-	"\x09\xcf\xbc\xf5\x09\xf4\x01\x00\x89\xfb\x8f\x74\x89\xfe\x48\x01\x29\x00\x19\x25\x29\x03\x09\xf4\x85\xf9\x68\x0f\x16\x01"
-
-	struct platform platforms[] = {
-		{
-			CS_ARCH_TRICORE,
-			CS_MODE_TRICORE_162,
-			(unsigned char *)TRICORE_CODE,
-			sizeof(TRICORE_CODE) - 1,
-			"TriCore",
-		},
-	};
-
-	uint64_t address = 0x1000;
-	cs_insn *insn;
-	int i;
-	size_t count;
-
-	for (i = 0; i < sizeof(platforms) / sizeof(platforms[0]); i++) {
-		cs_err err =
-			cs_open(platforms[i].arch, platforms[i].mode, &handle);
-		if (err) {
-			printf("Failed on cs_open() with error returned: %u\n",
-			       err);
-			continue;
-		}
-
-		cs_option(handle, CS_OPT_DETAIL, CS_OPT_ON);
-
-		count = cs_disasm(handle, platforms[i].code, platforms[i].size,
-				  address, 0, &insn);
-		if (count) {
-			size_t j;
-
-			printf("****************\n");
-			printf("Platform: %s\n", platforms[i].comment);
-			print_string_hex("Code:", platforms[i].code,
-					 platforms[i].size);
-			printf("Disasm:\n");
-
-			for (j = 0; j < count; j++) {
-				printf("0x%" PRIx64 ":\t%s\t%s\n",
-				       insn[j].address, insn[j].mnemonic,
-				       insn[j].op_str);
-				print_insn_detail(&insn[j]);
-			}
-			printf("0x%" PRIx64 ":\n",
-			       insn[j - 1].address + insn[j - 1].size);
-
-			// free memory allocated by cs_disasm()
-			cs_free(insn, count);
-		} else {
-			printf("****************\n");
-			printf("Platform: %s\n", platforms[i].comment);
-			print_string_hex("Code:", platforms[i].code,
-					 platforms[i].size);
-			printf("ERROR: Failed to disasm given code!\n");
-		}
-
-		cs_close(&handle);
-	}
-}
-
-int main()
-{
-	test();
-
-	return 0;
-}
diff --git a/tests/test_wasm.c b/tests/test_wasm.c
deleted file mode 100644
index 95e387d19..000000000
--- a/tests/test_wasm.c
+++ /dev/null
@@ -1,159 +0,0 @@
-/* Capstone Disassembler Engine */
-/* By Spike <spikeinhouse@gmail.com>, 2018 */
-
-#include <stdio.h>
-#include <stdlib.h>
-
-#include <capstone/platform.h>
-#include <capstone/capstone.h>
-
-static csh handle;
-
-struct platform {
-	cs_arch arch;
-	cs_mode mode;
-	unsigned char *code;
-	size_t size;
-	const char *comment;
-};
-
-static void print_string_hex(const char *comment, unsigned char *str, size_t len)
-{
-	unsigned char *c;
-
-	printf("%s", comment);
-	for (c = str; c < str + len; c++) {
-		printf("0x%02x ", *c & 0xff);
-	}
-
-	printf("\n");
-}
-
-static void print_insn_detail(csh cs_handle, cs_insn *ins)
-{
-	cs_wasm *wasm;
-
-	// detail can be NULL on "data" instruction if SKIPDATA option is turned ON
-	if (ins->detail == NULL)
-		return;
-
-	if (ins->detail->groups_count) {
-		int j;
-
-		printf("\tGroups: ");
-		for(j = 0; j < ins->detail->groups_count; j++) {
-			printf("%s ", cs_group_name(handle, ins->detail->groups[j]));
-		}
-		printf("\n");
-	}
-
-	wasm = &(ins->detail->wasm);
-
-	if (wasm->op_count > 0) {
-		unsigned int i;
-
-		printf("\tOperand count: %u\n", wasm->op_count);
-
-		for (i = 0; i < wasm->op_count; i++) {
-			switch (wasm->operands[i].type) {
-				default:
-					break;
-				case WASM_OP_INT7:
-					printf("\t\tOperand[%u] type: int7\n", i);
-					printf("\t\tOperand[%u] value: %d\n", i, wasm->operands[i].int7);
-					break;
-				case WASM_OP_UINT32:
-					printf("\t\tOperand[%u] type: uint32\n", i);
-					printf("\t\tOperand[%u] value: 0x%x\n", i, wasm->operands[i].uint32);
-					break;
-				case WASM_OP_UINT64:
-					printf("\t\tOperand[%u] type: uint64\n", i);
-					printf("\t\tOperand[%u] value: 0x%" PRIx64 "\n", i, wasm->operands[i].uint64);
-					break;
-				case WASM_OP_VARUINT32:
-					printf("\t\tOperand[%u] type: varuint32\n", i);
-					printf("\t\tOperand[%u] value: 0x%x\n", i, wasm->operands[i].varuint32);
-					break;
-				case WASM_OP_VARUINT64:
-					printf("\t\tOperand[%u] type: varuint64\n", i);
-					printf("\t\tOperand[%u] value: 0x%" PRIx64 "\n", i, wasm->operands[i].varuint64);
-					break;
-				case WASM_OP_IMM:
-					printf("\t\tOperand[%u] type: imm\n", i);
-					printf("\t\tOperand[%u] value: 0x%x 0x%x\n", i, wasm->operands[i].immediate[0], wasm->operands[i].immediate[1]);
-					break;
-				case WASM_OP_BRTABLE:
-					printf("\t\tOperand[%u] type: brtable\n", i);
-					printf("\t\tOperand[%u] value: length=0x%x, address=0x%" PRIx64 ", default_target=%x\n", i, wasm->operands[i].brtable.length, wasm->operands[i].brtable.address, wasm->operands[i].brtable.default_target);
-					break;
-			}
-			printf("\t\tOperand[%u] size: %u\n", i, wasm->operands[i].size);
-		}
-	}
-
-	printf("\n");
-}
-
-static void test()
-{
-#define WASM_CODE "\x20\x00\x20\x01\x41\x20\x10\xc9\x01\x45\x0b"
-	struct platform platforms[] = {
-		{
-			CS_ARCH_WASM,
-			0,
-			(unsigned char *)WASM_CODE,
-			sizeof(WASM_CODE) - 1,
-			"WASM"
-		},
-	};
-
-	uint64_t address = 0xffff;
-	cs_insn *insn;
-	size_t count;
-	int i;
-
-	for (i = 0; i < sizeof(platforms)/sizeof(platforms[0]); i++) {
-		cs_err err = cs_open(platforms[i].arch, platforms[i].mode, &handle);
-		if (err) {
-			printf("Failed on cs_open() with error returned: %u\n", err);
-			abort();
-		}
-
-		cs_option(handle, CS_OPT_DETAIL, CS_OPT_ON);
-
-		count = cs_disasm(handle, platforms[i].code, platforms[i].size, address, 0, &insn);
-		if (count) {
-			size_t j;
-			printf("****************\n");
-			printf("Platform: %s\n", platforms[i].comment);
-			print_string_hex("Code: ", platforms[i].code, platforms[i].size);
-			printf("Disasm:\n");
-
-			for (j = 0; j < count; j++) {
-				printf("0x%" PRIx64 ":\t%s\t%s\n", insn[j].address, insn[j].mnemonic, insn[j].op_str);
-				print_insn_detail(handle, &insn[j]);
-			}
-			printf("0x%" PRIx64 ":\n", insn[j-1].address + insn[j-1].size);
-
-			// free memory allocated by cs_disasm()
-			cs_free(insn, count);
-		} else {
-			printf("****************\n");
-			printf("Platform: %s\n", platforms[i].comment);
-			print_string_hex("Code: ", platforms[i].code, platforms[i].size);
-			printf("ERROR: Failed to disasm given code!\n");
-			abort();
-		}
-
-		printf("\n");
-
-		cs_close(&handle);
-	}
-}
-
-int main()
-{
-	test();
-	return 0;
-}
-
diff --git a/tests/test_x86.c b/tests/test_x86.c
deleted file mode 100644
index 775c096d3..000000000
--- a/tests/test_x86.c
+++ /dev/null
@@ -1,464 +0,0 @@
-/* Capstone Disassembler Engine */
-/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013 */
-
-#include <stdio.h>
-#include <stdlib.h>
-
-#include <capstone/platform.h>
-#include <capstone/capstone.h>
-
-static csh handle;
-
-struct platform {
-	cs_arch arch;
-	cs_mode mode;
-	unsigned char *code;
-	size_t size;
-	const char *comment;
-	cs_opt_type opt_type;
-	cs_opt_value opt_value;
-};
-
-static void print_string_hex(const char *comment, unsigned char *str, size_t len)
-{
-	unsigned char *c;
-
-	printf("%s", comment);
-	for (c = str; c < str + len; c++) {
-		printf("0x%02x ", *c & 0xff);
-	}
-
-	printf("\n");
-}
-
-static const char *get_eflag_name(uint64_t flag)
-{
-	switch(flag) {
-		default:
-			return NULL;
-		case X86_EFLAGS_UNDEFINED_OF:
-			return "UNDEF_OF";
-		case X86_EFLAGS_UNDEFINED_SF:
-			return "UNDEF_SF";
-		case X86_EFLAGS_UNDEFINED_ZF:
-			return "UNDEF_ZF";
-		case X86_EFLAGS_MODIFY_AF:
-			return "MOD_AF";
-		case X86_EFLAGS_UNDEFINED_PF:
-			return "UNDEF_PF";
-		case X86_EFLAGS_MODIFY_CF:
-			return "MOD_CF";
-		case X86_EFLAGS_MODIFY_SF:
-			return "MOD_SF";
-		case X86_EFLAGS_MODIFY_ZF:
-			return "MOD_ZF";
-		case X86_EFLAGS_UNDEFINED_AF:
-			return "UNDEF_AF";
-		case X86_EFLAGS_MODIFY_PF:
-			return "MOD_PF";
-		case X86_EFLAGS_UNDEFINED_CF:
-			return "UNDEF_CF";
-		case X86_EFLAGS_MODIFY_OF:
-			return "MOD_OF";
-		case X86_EFLAGS_RESET_OF:
-			return "RESET_OF";
-		case X86_EFLAGS_RESET_CF:
-			return "RESET_CF";
-		case X86_EFLAGS_RESET_DF:
-			return "RESET_DF";
-		case X86_EFLAGS_RESET_IF:
-			return "RESET_IF";
-		case X86_EFLAGS_TEST_OF:
-			return "TEST_OF";
-		case X86_EFLAGS_TEST_SF:
-			return "TEST_SF";
-		case X86_EFLAGS_TEST_ZF:
-			return "TEST_ZF";
-		case X86_EFLAGS_TEST_PF:
-			return "TEST_PF";
-		case X86_EFLAGS_TEST_CF:
-			return "TEST_CF";
-		case X86_EFLAGS_RESET_SF:
-			return "RESET_SF";
-		case X86_EFLAGS_RESET_AF:
-			return "RESET_AF";
-		case X86_EFLAGS_RESET_TF:
-			return "RESET_TF";
-		case X86_EFLAGS_RESET_NT:
-			return "RESET_NT";
-		case X86_EFLAGS_PRIOR_OF:
-			return "PRIOR_OF";
-		case X86_EFLAGS_PRIOR_SF:
-			return "PRIOR_SF";
-		case X86_EFLAGS_PRIOR_ZF:
-			return "PRIOR_ZF";
-		case X86_EFLAGS_PRIOR_AF:
-			return "PRIOR_AF";
-		case X86_EFLAGS_PRIOR_PF:
-			return "PRIOR_PF";
-		case X86_EFLAGS_PRIOR_CF:
-			return "PRIOR_CF";
-		case X86_EFLAGS_PRIOR_TF:
-			return "PRIOR_TF";
-		case X86_EFLAGS_PRIOR_IF:
-			return "PRIOR_IF";
-		case X86_EFLAGS_PRIOR_DF:
-			return "PRIOR_DF";
-		case X86_EFLAGS_TEST_NT:
-			return "TEST_NT";
-		case X86_EFLAGS_TEST_DF:
-			return "TEST_DF";
-		case X86_EFLAGS_RESET_PF:
-			return "RESET_PF";
-		case X86_EFLAGS_PRIOR_NT:
-			return "PRIOR_NT";
-		case X86_EFLAGS_MODIFY_TF:
-			return "MOD_TF";
-		case X86_EFLAGS_MODIFY_IF:
-			return "MOD_IF";
-		case X86_EFLAGS_MODIFY_DF:
-			return "MOD_DF";
-		case X86_EFLAGS_MODIFY_NT:
-			return "MOD_NT";
-		case X86_EFLAGS_MODIFY_RF:
-			return "MOD_RF";
-		case X86_EFLAGS_SET_CF:
-			return "SET_CF";
-		case X86_EFLAGS_SET_DF:
-			return "SET_DF";
-		case X86_EFLAGS_SET_IF:
-			return "SET_IF";
-	}
-}
-
-static const char *get_fpu_flag_name(uint64_t flag)
-{
-	switch (flag) {
-		default:
-			return NULL;
-		case X86_FPU_FLAGS_MODIFY_C0:
-			return "MOD_C0";
-		case X86_FPU_FLAGS_MODIFY_C1:
-			return "MOD_C1";
-		case X86_FPU_FLAGS_MODIFY_C2:
-			return "MOD_C2";
-		case X86_FPU_FLAGS_MODIFY_C3:
-			return "MOD_C3";
-		case X86_FPU_FLAGS_RESET_C0:
-			return "RESET_C0";
-		case X86_FPU_FLAGS_RESET_C1:
-			return "RESET_C1";
-		case X86_FPU_FLAGS_RESET_C2:
-			return "RESET_C2";
-		case X86_FPU_FLAGS_RESET_C3:
-			return "RESET_C3";
-		case X86_FPU_FLAGS_SET_C0:
-			return "SET_C0";
-		case X86_FPU_FLAGS_SET_C1:
-			return "SET_C1";
-		case X86_FPU_FLAGS_SET_C2:
-			return "SET_C2";
-		case X86_FPU_FLAGS_SET_C3:
-			return "SET_C3";
-		case X86_FPU_FLAGS_UNDEFINED_C0:
-			return "UNDEF_C0";
-		case X86_FPU_FLAGS_UNDEFINED_C1:
-			return "UNDEF_C1";
-		case X86_FPU_FLAGS_UNDEFINED_C2:
-			return "UNDEF_C2";
-		case X86_FPU_FLAGS_UNDEFINED_C3:
-			return "UNDEF_C3";
-		case X86_FPU_FLAGS_TEST_C0:
-			return "TEST_C0";
-		case X86_FPU_FLAGS_TEST_C1:
-			return "TEST_C1";
-		case X86_FPU_FLAGS_TEST_C2:
-			return "TEST_C2";
-		case X86_FPU_FLAGS_TEST_C3:
-			return "TEST_C3";
-	}
-}
-
-static void print_insn_detail(csh ud, cs_mode mode, cs_insn *ins)
-{
-	int count, i;
-	cs_x86 *x86;
-	cs_regs regs_read, regs_write;
-	uint8_t regs_read_count, regs_write_count;
-
-	// detail can be NULL on "data" instruction if SKIPDATA option is turned ON
-	if (ins->detail == NULL)
-		return;
-
-	x86 = &(ins->detail->x86);
-
-	print_string_hex("\tPrefix:", x86->prefix, 4);
-
-	print_string_hex("\tOpcode:", x86->opcode, 4);
-
-	printf("\trex: 0x%x\n", x86->rex);
-
-	printf("\taddr_size: %u\n", x86->addr_size);
-	printf("\tmodrm: 0x%x\n", x86->modrm);
-	if (x86->encoding.modrm_offset != 0) {
-		printf("\tmodrm_offset: 0x%x\n", x86->encoding.modrm_offset);
-	}
-	
-	printf("\tdisp: 0x%" PRIx64 "\n", x86->disp);
-	if (x86->encoding.disp_offset != 0) {
-		printf("\tdisp_offset: 0x%x\n", x86->encoding.disp_offset);
-	}
-	
-	if (x86->encoding.disp_size != 0) {
-		printf("\tdisp_size: 0x%x\n", x86->encoding.disp_size);
-	}
-	
-	// SIB is not available in 16-bit mode
-	if ((mode & CS_MODE_16) == 0) {
-		printf("\tsib: 0x%x\n", x86->sib);
-		if (x86->sib_base != X86_REG_INVALID)
-			printf("\t\tsib_base: %s\n", cs_reg_name(handle, x86->sib_base));
-		if (x86->sib_index != X86_REG_INVALID)
-			printf("\t\tsib_index: %s\n", cs_reg_name(handle, x86->sib_index));
-		if (x86->sib_scale != 0)
-			printf("\t\tsib_scale: %d\n", x86->sib_scale);
-	}
-
-	// XOP code condition
-	if (x86->xop_cc != X86_XOP_CC_INVALID) {
-		printf("\txop_cc: %u\n", x86->xop_cc);
-	}
-
-	// SSE code condition
-	if (x86->sse_cc != X86_SSE_CC_INVALID) {
-		printf("\tsse_cc: %u\n", x86->sse_cc);
-	}
-
-	// AVX code condition
-	if (x86->avx_cc != X86_AVX_CC_INVALID) {
-		printf("\tavx_cc: %u\n", x86->avx_cc);
-	}
-
-	// AVX Suppress All Exception
-	if (x86->avx_sae) {
-		printf("\tavx_sae: %u\n", x86->avx_sae);
-	}
-
-	// AVX Rounding Mode
-	if (x86->avx_rm != X86_AVX_RM_INVALID) {
-		printf("\tavx_rm: %u\n", x86->avx_rm);
-	}
-
-	// Print out all immediate operands
-	count = cs_op_count(ud, ins, X86_OP_IMM);
-	if (count) {
-		printf("\timm_count: %u\n", count);
-		for (i = 1; i < count + 1; i++) {
-			int index = cs_op_index(ud, ins, X86_OP_IMM, i);
-			printf("\t\timms[%u]: 0x%" PRIx64 "\n", i, x86->operands[index].imm);
-			if (x86->encoding.imm_offset != 0) {
-				printf("\timm_offset: 0x%x\n", x86->encoding.imm_offset);
-			}
-			
-			if (x86->encoding.imm_size != 0) {
-				printf("\timm_size: 0x%x\n", x86->encoding.imm_size);
-			}
-		}
-	}
-
-	if (x86->op_count)
-		printf("\top_count: %u\n", x86->op_count);
-
-	// Print out all operands
-	for (i = 0; i < x86->op_count; i++) {
-		cs_x86_op *op = &(x86->operands[i]);
-
-		switch((int)op->type) {
-			case X86_OP_REG:
-				printf("\t\toperands[%u].type: REG = %s\n", i, cs_reg_name(handle, op->reg));
-				break;
-			case X86_OP_IMM:
-				printf("\t\toperands[%u].type: IMM = 0x%" PRIx64 "\n", i, op->imm);
-				break;
-			case X86_OP_MEM:
-				printf("\t\toperands[%u].type: MEM\n", i);
-				if (op->mem.segment != X86_REG_INVALID)
-					printf("\t\t\toperands[%u].mem.segment: REG = %s\n", i, cs_reg_name(handle, op->mem.segment));
-				if (op->mem.base != X86_REG_INVALID)
-					printf("\t\t\toperands[%u].mem.base: REG = %s\n", i, cs_reg_name(handle, op->mem.base));
-				if (op->mem.index != X86_REG_INVALID)
-					printf("\t\t\toperands[%u].mem.index: REG = %s\n", i, cs_reg_name(handle, op->mem.index));
-				if (op->mem.scale != 1)
-					printf("\t\t\toperands[%u].mem.scale: %u\n", i, op->mem.scale);
-				if (op->mem.disp != 0)
-					printf("\t\t\toperands[%u].mem.disp: 0x%" PRIx64 "\n", i, op->mem.disp);
-				break;
-			default:
-				break;
-		}
-
-		// AVX broadcast type
-		if (op->avx_bcast != X86_AVX_BCAST_INVALID)
-			printf("\t\toperands[%u].avx_bcast: %u\n", i, op->avx_bcast);
-
-		// AVX zero opmask {z}
-		if (op->avx_zero_opmask != false)
-			printf("\t\toperands[%u].avx_zero_opmask: TRUE\n", i);
-
-		printf("\t\toperands[%u].size: %u\n", i, op->size);
-
-		switch(op->access) {
-			default:
-				break;
-			case CS_AC_READ:
-				printf("\t\toperands[%u].access: READ\n", i);
-				break;
-			case CS_AC_WRITE:
-				printf("\t\toperands[%u].access: WRITE\n", i);
-				break;
-			case CS_AC_READ | CS_AC_WRITE:
-				printf("\t\toperands[%u].access: READ | WRITE\n", i);
-				break;
-		}
-	}
-
-	// Print out all registers accessed by this instruction (either implicit or explicit)
-	if (!cs_regs_access(ud, ins,
-				regs_read, &regs_read_count,
-				regs_write, &regs_write_count)) {
-		if (regs_read_count) {
-			printf("\tRegisters read:");
-			for(i = 0; i < regs_read_count; i++) {
-				printf(" %s", cs_reg_name(handle, regs_read[i]));
-			}
-			printf("\n");
-		}
-
-		if (regs_write_count) {
-			printf("\tRegisters modified:");
-			for(i = 0; i < regs_write_count; i++) {
-				printf(" %s", cs_reg_name(handle, regs_write[i]));
-			}
-			printf("\n");
-		}
-	}
-
-	if (x86->eflags || x86->fpu_flags) {
-		for(i = 0; i < ins->detail->groups_count; i++) {
-			if (ins->detail->groups[i] == X86_GRP_FPU) {
-				printf("\tFPU_FLAGS:");
-				for(i = 0; i <= 63; i++)
-					if (x86->fpu_flags & ((uint64_t)1 << i)) {
-						printf(" %s", get_fpu_flag_name((uint64_t)1 << i));
-					}
-				printf("\n");
-				break;
-			}
-		}
-
-		if (i == ins->detail->groups_count) {
-			printf("\tEFLAGS:");
-			for(i = 0; i <= 63; i++)
-				if (x86->eflags & ((uint64_t)1 << i)) {
-					printf(" %s", get_eflag_name((uint64_t)1 << i));
-				}
-			printf("\n");
-		}
-	}
-
-	printf("\n");
-}
-
-static void test()
-{
-#define X86_CODE64 "\x55\x48\x8b\x05\xb8\x13\x00\x00\xe9\xea\xbe\xad\xde\xff\x25\x23\x01\x00\x00\xe8\xdf\xbe\xad\xde\x74\xff"
-#define X86_CODE16 "\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00\x05\x23\x01\x00\x00\x36\x8b\x84\x91\x23\x01\x00\x00\x41\x8d\x84\x39\x89\x67\x00\x00\x8d\x87\x89\x67\x00\x00\xb4\xc6\x66\xe9\xb8\x00\x00\x00\x67\xff\xa0\x23\x01\x00\x00\x66\xe8\xcb\x00\x00\x00\x74\xfc"
-#define X86_CODE32 "\x8d\x4c\x32\x08\x01\xd8\x81\xc6\x34\x12\x00\x00\x05\x23\x01\x00\x00\x36\x8b\x84\x91\x23\x01\x00\x00\x41\x8d\x84\x39\x89\x67\x00\x00\x8d\x87\x89\x67\x00\x00\xb4\xc6\xe9\xea\xbe\xad\xde\xff\xa0\x23\x01\x00\x00\xe8\xdf\xbe\xad\xde\x74\xff"
-
-	struct platform platforms[] = {
-		{
-			CS_ARCH_X86,
-			CS_MODE_16,
-			(unsigned char *)X86_CODE16,
-			sizeof(X86_CODE16) - 1,
-			"X86 16bit (Intel syntax)"
-		},
-		{
-			CS_ARCH_X86,
-			CS_MODE_32,
-			(unsigned char *)X86_CODE32,
-			sizeof(X86_CODE32) - 1,
-			"X86 32 (AT&T syntax)",
-			CS_OPT_SYNTAX,
-			CS_OPT_SYNTAX_ATT,
-		},
-		{
-			CS_ARCH_X86,
-			CS_MODE_32,
-			(unsigned char *)X86_CODE32,
-			sizeof(X86_CODE32) - 1,
-			"X86 32 (Intel syntax)"
-		},
-		{
-			CS_ARCH_X86,
-			CS_MODE_64,
-			(unsigned char *)X86_CODE64,
-			sizeof(X86_CODE64) - 1,
-			"X86 64 (Intel syntax)"
-		},
-	};
-
-	uint64_t address = 0x1000;
-	cs_insn *insn;
-	int i;
-	size_t count;
-
-	for (i = 0; i < sizeof(platforms)/sizeof(platforms[0]); i++) {
-		cs_err err = cs_open(platforms[i].arch, platforms[i].mode, &handle);
-		if (err) {
-			printf("Failed on cs_open() with error returned: %u\n", err);
-			abort();
-		}
-
-		if (platforms[i].opt_type)
-			cs_option(handle, platforms[i].opt_type, platforms[i].opt_value);
-
-		cs_option(handle, CS_OPT_DETAIL, CS_OPT_ON);
-
-		count = cs_disasm(handle, platforms[i].code, platforms[i].size, address, 0, &insn);
-		if (count) {
-			size_t j;
-
-			printf("****************\n");
-			printf("Platform: %s\n", platforms[i].comment);
-			print_string_hex("Code:", platforms[i].code, platforms[i].size);
-			printf("Disasm:\n");
-
-			for (j = 0; j < count; j++) {
-				printf("0x%" PRIx64 ":\t%s\t%s\n", insn[j].address, insn[j].mnemonic, insn[j].op_str);
-				print_insn_detail(handle, platforms[i].mode, &insn[j]);
-			}
-			printf("0x%" PRIx64 ":\n", insn[j-1].address + insn[j-1].size);
-
-			// free memory allocated by cs_disasm()
-			cs_free(insn, count);
-		} else {
-			printf("****************\n");
-			printf("Platform: %s\n", platforms[i].comment);
-			print_string_hex("Code:", platforms[i].code, platforms[i].size);
-			printf("ERROR: Failed to disasm given code!\n");
-			abort();
-		}
-
-		printf("\n");
-
-		cs_close(&handle);
-	}
-}
-
-int main()
-{
-	test();
-
-	return 0;
-}
diff --git a/tests/test_xcore.c b/tests/test_xcore.c
deleted file mode 100644
index 12cc1f1bb..000000000
--- a/tests/test_xcore.c
+++ /dev/null
@@ -1,140 +0,0 @@
-/* Capstone Disassembler Engine */
-/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
-
-#include <stdio.h>
-
-#include <capstone/platform.h>
-#include <capstone/capstone.h>
-
-struct platform {
-	cs_arch arch;
-	cs_mode mode;
-	unsigned char *code;
-	size_t size;
-	const char *comment;
-};
-
-static csh handle;
-
-static void print_string_hex(const char *comment, unsigned char *str, size_t len)
-{
-	unsigned char *c;
-
-	printf("%s", comment);
-	for (c = str; c < str + len; c++) {
-		printf("0x%02x ", *c & 0xff);
-	}
-
-	printf("\n");
-}
-
-static void print_insn_detail(cs_insn *ins)
-{
-	cs_xcore *xcore;
-	int i;
-
-	// detail can be NULL on "data" instruction if SKIPDATA option is turned ON
-	if (ins->detail == NULL)
-		return;
-
-	xcore = &(ins->detail->xcore);
-	if (xcore->op_count)
-		printf("\top_count: %u\n", xcore->op_count);
-
-	for (i = 0; i < xcore->op_count; i++) {
-		cs_xcore_op *op = &(xcore->operands[i]);
-		switch((int)op->type) {
-			default:
-				break;
-			case XCORE_OP_REG:
-				printf("\t\toperands[%u].type: REG = %s\n", i, cs_reg_name(handle, op->reg));
-				break;
-			case XCORE_OP_IMM:
-				printf("\t\toperands[%u].type: IMM = 0x%x\n", i, op->imm);
-				break;
-			case XCORE_OP_MEM:
-				printf("\t\toperands[%u].type: MEM\n", i);
-				if (op->mem.base != XCORE_REG_INVALID)
-					printf("\t\t\toperands[%u].mem.base: REG = %s\n",
-							i, cs_reg_name(handle, op->mem.base));
-				if (op->mem.index != XCORE_REG_INVALID)
-					printf("\t\t\toperands[%u].mem.index: REG = %s\n",
-							i, cs_reg_name(handle, op->mem.index));
-				if (op->mem.disp != 0)
-					printf("\t\t\toperands[%u].mem.disp: 0x%x\n", i, op->mem.disp);
-				if (op->mem.direct != 1)
-					printf("\t\t\toperands[%u].mem.direct: -1\n", i);
-
-
-				break;
-		}
-	}
-
-	printf("\n");
-}
-
-static void test()
-{
-#define XCORE_CODE "\xfe\x0f\xfe\x17\x13\x17\xc6\xfe\xec\x17\x97\xf8\xec\x4f\x1f\xfd\xec\x37\x07\xf2\x45\x5b\xf9\xfa\x02\x06\x1b\x10\x09\xfd\xec\xa7"
-
-	struct platform platforms[] = {
-		{
-			CS_ARCH_XCORE,
-			CS_MODE_BIG_ENDIAN,
-			(unsigned char*)XCORE_CODE,
-			sizeof(XCORE_CODE) - 1,
-			"XCore",
-		},
-	};
-
-	uint64_t address = 0x1000;
-	cs_insn *insn;
-	int i;
-	size_t count;
-
-	for (i = 0; i < sizeof(platforms)/sizeof(platforms[0]); i++) {
-		cs_err err = cs_open(platforms[i].arch, platforms[i].mode, &handle);
-		if (err) {
-			printf("Failed on cs_open() with error returned: %u\n", err);
-			abort();
-		}
-
-		cs_option(handle, CS_OPT_DETAIL, CS_OPT_ON);
-
-		count = cs_disasm(handle, platforms[i].code, platforms[i].size, address, 0, &insn);
-		if (count) {
-			size_t j;
-
-			printf("****************\n");
-			printf("Platform: %s\n", platforms[i].comment);
-			print_string_hex("Code:", platforms[i].code, platforms[i].size);
-			printf("Disasm:\n");
-
-			for (j = 0; j < count; j++) {
-				printf("0x%" PRIx64 ":\t%s\t%s\n", insn[j].address, insn[j].mnemonic, insn[j].op_str);
-				print_insn_detail(&insn[j]);
-			}
-			printf("0x%" PRIx64 ":\n", insn[j-1].address + insn[j-1].size);
-
-			// free memory allocated by cs_disasm()
-			cs_free(insn, count);
-		} else {
-			printf("****************\n");
-			printf("Platform: %s\n", platforms[i].comment);
-			print_string_hex("Code:", platforms[i].code, platforms[i].size);
-			printf("ERROR: Failed to disasm given code!\n");
-			abort();
-		}
-
-		printf("\n");
-
-		cs_close(&handle);
-	}
-}
-
-int main()
-{
-	test();
-
-	return 0;
-}
diff --git a/tests/unit/CMakeLists.txt b/tests/unit/CMakeLists.txt
new file mode 100644
index 000000000..e69de29bb
diff --git a/tests/unit/README.md b/tests/unit/README.md
new file mode 100644
index 000000000..cf9e0e650
--- /dev/null
+++ b/tests/unit/README.md
@@ -0,0 +1,2 @@
+Nothing in here yet :(
+
diff --git a/utils.c b/utils.c
index bd5fcf561..3edf519c5 100644
--- a/utils.c
+++ b/utils.c
@@ -113,7 +113,11 @@ uint16_t readBytes16(MCInst *MI, const uint8_t *Bytes)
 /// @param str The string to append to.
 /// @param str_size The length of @p str
 /// @param src The string to append.
+/// Does nothing if any of the given strings is NULL.
 void append_to_str_lower(char *str, size_t str_size, const char *src) {
+	if (!str || !src) {
+		return;
+	}
 	char *dest = strchr(str, '\0');
 	if (dest - str >= str_size) {
 		assert("str_size does not match actual string length." && 0);
@@ -125,4 +129,61 @@ void append_to_str_lower(char *str, size_t str_size, const char *src) {
 		str[i] = tolower(src[j]);
 	}
 	str[i] = '\0';
-}
\ No newline at end of file
+}
+
+/// @brief Appends the string @p src to the string @p str. @p src is put to lower case.
+/// @param str The string to append to.
+/// @param str_buf_size Size of buffer @p str.
+/// @param src The string to append.
+/// Does nothing if any of the given strings is NULL.
+void append_to_str(char *str, size_t str_buf_size, const char *src) {
+	if (!str || !src) {
+		return;
+	}
+	if (strlen(str) + strlen(src) + 1 > str_buf_size) {
+		assert("str_size does not match actual string length." && 0);
+		return;
+	}
+	strncat(str, src, str_buf_size);
+}
+
+
+/// Allocates memory of strlen(str_a) + strlen(str_b) + 1 chars
+/// and copies all strings into it as str_a + str_b
+/// str_a is passed to realloc and should not be used afterwards.
+/// Returns the result.
+/// Returns NULL in case of failure.
+char *str_append(char *str_a, const char *str_b) {
+	if (!str_a || !str_b) {
+		return NULL;
+	}
+	assert(str_a && str_b);
+	size_t asize = strlen(str_a) + strlen(str_b) + 1;
+	str_a = realloc(str_a, asize);
+	strncat(str_a, str_b, asize);
+	return str_a;
+}
+
+/// Returns the given byte sequence @bytes as a string of the
+/// form: 0xXX,0xXX...
+/// Returns NULL in case of failure.
+char *byte_seq_to_str(uint8_t *bytes, size_t len)
+{
+	if (!bytes) {
+		return NULL;
+	}
+	if (len == 0) {
+		return NULL;
+	}
+	char single_byte[8] = { 0 };
+	char *s = calloc(sizeof(char), 32);
+	for (size_t i = 0; i < len; ++i) {
+		cs_snprintf(single_byte, sizeof(single_byte), "0x%02" PRIx8 "%s",
+			    bytes[i], i == len - 1 ? "" : ",");
+		s = str_append(s, single_byte);
+		if (!s) {
+			return NULL;
+		}
+	}
+	return s;
+}
diff --git a/utils.h b/utils.h
index 55b2ca255..3cca580c8 100644
--- a/utils.h
+++ b/utils.h
@@ -4,6 +4,7 @@
 #ifndef CS_UTILS_H
 #define CS_UTILS_H
 
+#include <stdint.h>
 #if defined(CAPSTONE_HAS_OSXKERNEL)
 #include <libkern/libkern.h>
 #else
@@ -41,9 +42,13 @@ uint16_t readBytes16(MCInst *MI, const uint8_t *Bytes);
 uint32_t readBytes32(MCInst *MI, const uint8_t *Bytes);
 
 void append_to_str_lower(char *str, size_t str_size, const char *src);
+void append_to_str(char *str, size_t str_buf_size, const char *src);
+char *str_append(char *str_a, const char *str_b);
 static inline bool strings_match(const char *str0, const char *str1) { return strcmp(str0, str1) == 0; }
 
 static inline bool is_blank_char(const char c) {
 	return c == ' ' || c == '\t';
 }
+
+char *byte_seq_to_str(uint8_t *bytes, size_t len);
 #endif
diff --git a/windowsce/COMPILE.md b/windowsce/COMPILE.md
index 6ed5abc4c..2aaceb8c2 100644
--- a/windowsce/COMPILE.md
+++ b/windowsce/COMPILE.md
@@ -2,7 +2,7 @@ This documentation explains how to compile Capstone for:
 - Windows CE 7, a.k.a, [Windows Embedded Compact 7](https://www.microsoft.com/windowsembedded/en-us/windows-embedded-compact-7.aspx), on [ARMv7](http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0406c/index.html).
 - Windows CE 8, a.k.a, [Windows Embedded Compact 2013](https://www.microsoft.com/windowsembedded/en-us/windows-embedded-compact-2013.aspx), on [ARMv7](http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0406c/index.html).
 
-To build Capstone for a different platform, please refer to `COMPILE.TXT`.
+To build Capstone for a different platform, please refer to `COMPILE_CMAKE.TXT`.
 
 # Prerequisites